--- /home/fdroid/fdroiddata/tmp/space.celestia.mobilecelestia_570.apk +++ /home/fdroid/fdroiddata/tmp/sigcp_space.celestia.mobilecelestia_570.apk ├── /usr/lib/android-sdk/build-tools/debian/apksigner verify --verbose --print-certs {} │┄ error from `/usr/lib/android-sdk/build-tools/debian/apksigner verify --verbose --print-certs {}` (b): │┄ DOES NOT VERIFY │┄ ERROR: APK Signature Scheme v3 signer #1: APK integrity check failed. CHUNKED_SHA256 digest mismatch. Expected: <46c74e5f7b6a4ee9d250d61d0532a6451d142aacd0d53eb68c4efdfed30a8a8e>, actual: <0692d206756fa8daad9e76fd67bd163144f4b2286d891bad5814e2fb146743c2> │┄ ERROR: APK Signature Scheme v3 signer #1: APK integrity check failed. VERITY_CHUNKED_SHA256 digest mismatch. Expected: <88e0320cf99bc473081cff8894abea7440a479426e9b0838217649b157aba127a8345b1700000000>, actual: <77e43f245b1c953350624d7fb9d177a11563f487bb7df307af5a3342e904e1c1a8345b1700000000> │ @@ -1,103 +0,0 @@ │ -Verifies │ -Verified using v1 scheme (JAR signing): true │ -Verified using v2 scheme (APK Signature Scheme v2): true │ -Verified using v3 scheme (APK Signature Scheme v3): true │ -Verified using v4 scheme (APK Signature Scheme v4): false │ -Verified for SourceStamp: false │ -Number of signers: 1 │ -Signer #1 certificate DN: CN=FDroid, OU=FDroid, O=fdroid.org, L=ORG, ST=ORG, C=UK │ -Signer #1 certificate SHA-256 digest: 77dd218436a66b04b3cf3f80a0618ca1b851b78bd37e585b73be3e302aedae8b │ -Signer #1 certificate SHA-1 digest: e37cefc65f285384d89ab05f4e640418b5457675 │ -Signer #1 certificate MD5 digest: fc6b677bba104240a6bfba6e16e1b820 │ -Signer #1 key algorithm: RSA │ -Signer #1 key size (bits): 2048 │ -Signer #1 public key SHA-256 digest: 56420afe78230195507481831ffc3b769f99a228ad832fa54e522bfe090628c6 │ -Signer #1 public key SHA-1 digest: 5e4f7a235e4f9a11153e59856929bd2ed568bd45 │ -Signer #1 public key MD5 digest: f783bfcb493593341ba2a8576a00b4ee │ -WARNING: META-INF/com/android/build/gradle/app-metadata.properties not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/version-control-info.textproto not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/NOTICE.md not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/README.md not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.activity_activity-compose.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.activity_activity-ktx.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.activity_activity.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.annotation_annotation-experimental.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.appcompat_appcompat-resources.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.appcompat_appcompat.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.arch.core_core-runtime.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.autofill_autofill.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.cardview_cardview.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.compose.animation_animation-core.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.compose.animation_animation.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.compose.foundation_foundation-layout.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.compose.foundation_foundation.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.compose.material3_material3.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.compose.material_material-icons-core.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.compose.material_material-ripple.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.compose.runtime_runtime-saveable.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.compose.runtime_runtime.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.compose.ui_ui-geometry.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.compose.ui_ui-graphics.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.compose.ui_ui-text.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.compose.ui_ui-unit.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.compose.ui_ui-util.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.compose.ui_ui.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.coordinatorlayout_coordinatorlayout.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.core_core-ktx.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.core_core.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.cursoradapter_cursoradapter.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.customview_customview-poolingcontainer.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.customview_customview.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.documentfile_documentfile.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.drawerlayout_drawerlayout.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.dynamicanimation_dynamicanimation.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.emoji2_emoji2-views-helper.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.emoji2_emoji2.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.fragment_fragment-ktx.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.fragment_fragment.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.graphics_graphics-path.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.hilt_hilt-navigation-compose.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.hilt_hilt-navigation.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.interpolator_interpolator.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.legacy_legacy-support-core-utils.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.lifecycle_lifecycle-livedata-core-ktx.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.lifecycle_lifecycle-livedata-core.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.lifecycle_lifecycle-livedata.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.lifecycle_lifecycle-process.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.lifecycle_lifecycle-runtime-compose.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.lifecycle_lifecycle-runtime-ktx.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.lifecycle_lifecycle-runtime.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.lifecycle_lifecycle-viewmodel-compose.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.lifecycle_lifecycle-viewmodel-ktx.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.lifecycle_lifecycle-viewmodel-savedstate.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.lifecycle_lifecycle-viewmodel.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.loader_loader.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.localbroadcastmanager_localbroadcastmanager.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.navigation_navigation-common-ktx.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.navigation_navigation-common.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.navigation_navigation-compose.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.navigation_navigation-runtime-ktx.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.navigation_navigation-runtime.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.print_print.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.profileinstaller_profileinstaller.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.recyclerview_recyclerview.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.savedstate_savedstate-ktx.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.savedstate_savedstate.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.startup_startup-runtime.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.tracing_tracing.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.transition_transition.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.vectordrawable_vectordrawable-animated.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.vectordrawable_vectordrawable.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.versionedparcelable_versionedparcelable.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.viewpager2_viewpager2.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.viewpager_viewpager.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/androidx.webkit_webkit.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/com.google.android.material_material.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/com.google.dagger_dagger-lint-aar.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/com.google.dagger_dagger.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/com.google.dagger_hilt-android.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/com.google.dagger_hilt-core.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/kotlinx_coroutines_android.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/kotlinx_coroutines_core.version not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/services/kotlinx.coroutines.u not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. │ -WARNING: META-INF/services/s2.a not protected by signature. Unauthorized modifications to this JAR entry will not be detected. Delete or move the entry outside of META-INF/. ├── zipinfo {} │ @@ -1878,8 +1878,8 @@ │ -rw---- 0.0 fat 464 b- defN 81-Jan-01 01:01 res/zq.xml │ -rw---- 0.0 fat 10500 b- stor 81-Jan-01 01:01 res/zr.png │ -rw---- 0.0 fat 884 b- stor 81-Jan-01 01:01 res/zz.png │ -rw---- 0.0 fat 1392552 b- stor 81-Jan-01 01:01 resources.arsc │ -rw---- 2.0 fat 201864 b- defN 81-Jan-01 01:01 META-INF/F7DB8DC7.SF │ -rw---- 2.0 fat 1336 b- defN 81-Jan-01 01:01 META-INF/F7DB8DC7.RSA │ -rw---- 2.0 fat 201737 b- defN 81-Jan-01 01:01 META-INF/MANIFEST.MF │ -1883 files, 558093442 bytes uncompressed, 391576491 bytes compressed: 29.8% │ +1883 files, 558093442 bytes uncompressed, 391576597 bytes compressed: 29.8% ├── lib/armeabi-v7a/libcelestia.so │┄ File has been modified after NT_GNU_BUILD_ID has been applied. │ ├── readelf --wide --notes {} │ │ @@ -1,8 +1,8 @@ │ │ │ │ Displaying notes found in: .note.android.ident │ │ Owner Data size Description │ │ Android 0x00000084 NT_VERSION (version) description data: 17 00 00 00 72 32 37 62 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 31 32 32 39 37 30 30 36 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 │ │ │ │ Displaying notes found in: .note.gnu.build-id │ │ Owner Data size Description │ │ - GNU 0x00000014 NT_GNU_BUILD_ID (unique build ID bitstring) Build ID: f71b40160405f8f8b914930e805312e1b867f3cd │ │ + GNU 0x00000014 NT_GNU_BUILD_ID (unique build ID bitstring) Build ID: 606cec9d5f66bc8663aa325f3db8ea82665fbec8 │ ├── strings --all --bytes=8 {} │ │ @@ -21840,14 +21840,15 @@ │ │ Barycenter │ │ DDS file {} has bad surface desc. │ │ Unsupported format for DDS texture file {}. │ │ Error skipping {} trailing bytes │ │ Processing MaterialAmbient chunk │ │ eglCreateWindowSurface() returned error %d │ │ msgctxt │ │ +libjpeg-turbo version 3.0.4 (build 20241209) │ │ Suspension not allowed here │ │ Bogus DHT index %d │ │ Invalid JPEG file structure: two SOI markers │ │ with %d x %d thumbnail image │ │ Inconsistent progression sequence for component %d coefficient %d │ │ BlueScale │ │ FontName │ │ @@ -25081,15 +25082,14 @@ │ │ h = max(0.0, length(atmSamplePoint) - atmosphereRadius.z); │ │ Sorting stars into octree . . . │ │ Loading cross index failed - unexpected EOF │ │ Error parsing virtual texture │ │ Content size {} too small to include point array with {} entries │ │ cannot use operator[] with a numeric argument with │ │ libGLESv2.so │ │ -libjpeg-turbo version 3.0.4 (build 20241006) │ │ Invalid memory pool code %d │ │ Write to XMS failed │ │ Adobe APP14 marker: version %d, flags 0x%04x 0x%04x, transform %d │ │ Opened temporary file %s │ │ FREETYPE_PROPERTIES │ │ UnderlinePosition │ │ ExpansionFactor │ ├── readelf --wide --decompress --string-dump=.rodata {} │ │ @@ -1707,3874 +1707,3875 @@ │ │ [ 8f78] Unsupported format for DDS texture file {}.\n │ │ [ 8fa5] Error skipping {} trailing bytes\n │ │ [ 8fc7] Processing MaterialAmbient chunk\n │ │ [ 8fe9] ()V │ │ [ 8fed] \ufffd │ │ [ 8ff4] eglCreateWindowSurface() returned error %d │ │ [ 9020] msgctxt │ │ - [ 9029] Suspension not allowed here │ │ - [ 9045] Bogus DHT index %d │ │ - [ 9058] Invalid JPEG file structure: two SOI markers │ │ - [ 9085] with %d x %d thumbnail image │ │ - [ 90a6] Inconsistent progression sequence for component %d coefficient %d │ │ - [ 90e8] BlueScale │ │ - [ 90f2] FontName │ │ - [ 90fb] lenBuildCharArray │ │ - [ 910d] 8859 │ │ - [ 9112] FOUNDRY │ │ - [ 911a] RAW_POINT_SIZE │ │ - [ 9129] RAW_SUBSCRIPT_Y │ │ - [ 9139] STRIKEOUT_ASCENT │ │ - [ 914a] STRIKEOUT_DESCENT │ │ - [ 915c] _MULE_BASELINE_OFFSET │ │ - [ 9172] W1X │ │ - [ 9176] metamethod │ │ - [ 9181] Snlf │ │ - [ 9186] bytecode instructions │ │ - [ 919c] _G │ │ - [ 919f] too many captures │ │ - [ 91b1] too many arguments │ │ - [ 91c4] yday │ │ - [ 91c9] open │ │ - [ 91ce] 'package.loaders' must be a table │ │ - [ 91f0] Linux │ │ - [ 91f6] Invalid image height in IHDR │ │ - [ 9213] rgb+alpha color-map: too few entries │ │ - [ 9238] bad width format │ │ - [ 9249] no space in chunk cache │ │ - [ 9261] Invalid interlace type specified │ │ - [ 9282] SPICE(EMPTYSTRING) │ │ - [ 9295] op │ │ - [ 9298] EXPLAIN │ │ - [ 92a0] Version Identification of GEF File is Invalid │ │ - [ 92ce] SPICE(INCOMPATIBLEUNITS) │ │ - [ 92e7] SPICE(WINDOWTOOSMALL) │ │ - [ 92fd] iswhsp_c │ │ - [ 9306] There is no room left in KEEPER to load another SPICE kernel. The current limit on the number of files that can be loaded is #. If you really need more than this many files, you should increase the parameter MAXFIL in the subroutine KEEPER. │ │ - [ 93fa] SPICE(RECURSIVELOADING) │ │ - [ 9412] CK │ │ - [ 9415] CKUPF │ │ - [ 941b] RESUME │ │ - [ 9422] The file, '#', connected to unit # is not a DAF. │ │ - [ 9453] ZERO │ │ - [ 9458] truncation failed in endfile │ │ - [ 9475] No address for record #, word #. │ │ - [ 9496] cdue │ │ - [ 949b] DAFBBS │ │ - [ 94a2] SPICE(EKSEGTABLEFULL) │ │ - [ 94b8] The EK file # could not be loaded; the segment # contains duplicate column names in table #. │ │ - [ 9515] EKUEF │ │ - [ 951b] fort.%ld │ │ - [ 9524] CARDC │ │ - [ 952a] SPICE(INSUFFLEN) │ │ - [ 953b] hnbufd │ │ - [ 9542] SPICE(INVALIDSUBLIST) │ │ - [ 9558] PCKBSR │ │ - [ 955f] chvals │ │ - [ 9566] GCPOOL │ │ - [ 956d] SPICE(BADVARNAME) │ │ - [ 957f] INSLAI │ │ - [ 9586] rot2 │ │ - [ 958b] REMLAI │ │ - [ 9592] cnvrtn │ │ - [ 9599] Segment does not contain angular velocity data. │ │ - [ 95c9] Beginning address (#) greater than ending address (#). │ │ - [ 9600] vbuff │ │ - [ 9606] CKE02 │ │ - [ 960c] CKR06 │ │ - [ 9612] Input file # has architecture #. The file must be a binary SPK file to be readable by this routine. If the input file is an SPK file in transfer format, run TOBIN on the file to convert it to binary format. │ │ - [ 96e2] The file name is blank. │ │ - [ 96fa] IOSTAT error in INQUIRE statement. IOSTAT = #. │ │ - [ 9729] SPKPVN │ │ - [ 9730] sbound │ │ - [ 9737] SPKE17 │ │ - [ 973e] SPICE(BADSEMIAXIS) │ │ - [ 9751] SPKE21 │ │ - [ 9758] SPKR18 │ │ - [ 975f] Unexpected SPK type 18 subtype # found in type 18 segment. │ │ - [ 979a] SPICE(DEGREEOUTOFRANGE) │ │ - [ 97b2] NUT_PREC_PM │ │ - [ 97be] LOCATI │ │ - [ 97c5] SPICE(BADVARIABLESIZE) │ │ - [ 97dc] SPICE(NAMESDONOTMATCH) │ │ - [ 97f3] lio │ │ - [ 97f7] no imaginary part │ │ - [ 9809] SPICE(BADCOLUMNCOUNT) │ │ - [ 981f] bmat │ │ - [ 9824] Could not read non-native DAS integer record into character array. File = # Record number = #. IOSTAT = #. │ │ - [ 988f] DLABBS │ │ - [ 9896] ZZDYNBID │ │ - [ 989f] Variable # not found after DTPOOL indicated it was present in pool. │ │ - [ 98e3] ZZDYNFRM │ │ - [ 98ec] AXIS │ │ - [ 98f1] EULER │ │ - [ 98f7] rrows │ │ - [ 98fd] Column # should be CHR but has type #. │ │ - [ 9924] namidx │ │ - [ 992b] IAU_MERCURY_BARYCENTER │ │ - [ 9942] IAU_JUPITER │ │ - [ 994e] IAU_CALLISTO │ │ - [ 995b] IAU_TITANIA │ │ - [ 9967] IAU_THALASSA │ │ - [ 9974] IAU_CHALDENE │ │ - [ 9981] IAU_NIX │ │ - [ 9989] The reference frame # is a dynamic frame. Dynamic frames may not be used at recursion level 1. │ │ - [ 99e8] USED ITEM COUNT │ │ - [ 99f8] CALLISTO │ │ - [ 9a01] ALBIORIX │ │ - [ 9a0a] TARQEQ │ │ - [ 9a11] MOM │ │ - [ 9a15] WIND │ │ - [ 9a1a] LP │ │ - [ 9a1d] VIKING 1 ORBITER │ │ - [ 9a2e] GRAIL-B │ │ - [ 9a36] CLUSTER 1 │ │ - [ 9a40] NSYT │ │ - [ 9a45] SHOEMAKER-LEVY 9-V │ │ - [ 9a58] SHOEMAKER-LEVY 9-R │ │ - [ 9a6b] AREND │ │ - [ 9a71] BRADFIELD │ │ - [ 9a7b] DANIEL │ │ - [ 9a82] DENNING-FUJIKAWA │ │ - [ 9a93] MAURY │ │ - [ 9a99] SHOEMAKER-LEVY 1 │ │ - [ 9aaa] NOTO │ │ - [ 9aaf] DSS-43 │ │ - [ 9ab6] COMPILER │ │ - [ 9abf] zzdynrt0_ │ │ - [ 9ac9] A kernel variable was not properly formed on line # of the file #. Such an assignment should have the form: ' [+]= '. This line was '#'. │ │ - [ 9b6a] n │ │ - [ 9b6c] Mmi │ │ - [ 9b70] MmD │ │ - [ 9b74] The month specified, #, was not an integer. The month must be an integer in the range from 1 to 12. │ │ - [ 9bd9] TTRANS │ │ - [ 9be0] TAI │ │ - [ 9be5] YMWDF │ │ - [ 9bec] The seconds component of '#' is out of range. In the specified time zone (#) leapseconds can occur during the year # only in the second that immediately follows the time #:#:59 on # # and # #. │ │ - [ 9caf] AM │ │ - [ 9cb2] DD │ │ - [ 9cb5] Two substrings representing minutes of the hour were identified in the input time string <#> and <#>: " │ │ - [ 9d1d] Y-i/i:i:n │ │ - [ 9d27] Yimi:n │ │ - [ 9d2e] Ymii:i:n │ │ - [ 9d37] i-idi:n │ │ - [ 9d3f] i-iti:n │ │ - [ 9d47] i:i:iimY │ │ - [ 9d50] i-i-itn │ │ - [ 9d58] i:i:ii-i-Y │ │ - [ 9d63] ZZTWOVXF │ │ - [ 9d6c] und_ │ │ - [ 9d71] ab │ │ - [ 9d74] brx │ │ - [ 9d78] dua │ │ - [ 9d7c] es │ │ - [ 9d7f] fj │ │ - [ 9d82] kam │ │ - [ 9d86] khw │ │ - [ 9d8a] kk │ │ - [ 9d8d] oc │ │ - [ 9d90] sat │ │ - [ 9d94] sbp │ │ - [ 9d98] sdh │ │ - [ 9d9c] sm │ │ - [ 9d9f] bre │ │ - [ 9da3] iii │ │ - [ 9da7] mri │ │ - [ 9dab] mkd │ │ - [ 9daf] rus │ │ - [ 9db3] ven │ │ - [ 9db7] CQ │ │ - [ 9dba] ES │ │ - [ 9dbd] JO │ │ - [ 9dc0] KN │ │ - [ 9dc3] MG │ │ - [ 9dc6] NA │ │ - [ 9dc9] PK │ │ - [ 9dcc] BRB │ │ - [ 9dd0] CHE │ │ - [ 9dd4] CHN │ │ - [ 9dd8] FIN │ │ - [ 9ddc] FJI │ │ - [ 9de0] UGA │ │ - [ 9de4] my_MM │ │ - [ 9dea] heploc │ │ - [ 9df1] hepburn │ │ - [ 9df9] __system_property_read_callback │ │ - [ 9e19] KRAT │ │ - [ 9e1e] PMDT │ │ - [ 9e23] FKST │ │ - [ 9e28] ar_IQ │ │ - [ 9e2e] dz_BT │ │ - [ 9e34] es_BO │ │ - [ 9e3a] es_PY │ │ - [ 9e40] fa_AF │ │ - [ 9e46] fo_FO │ │ - [ 9e4c] fr_015 │ │ - [ 9e53] fr_029 │ │ - [ 9e5a] no_NO_NY │ │ - [ 9e63] sah_RU │ │ - [ 9e6a] xh_ZA │ │ - [ 9e70] en-gb-oed │ │ - [ 9e7a] i-tao │ │ - [ 9e80] vgt │ │ - [ 9e84] res_index │ │ - [ 9e8e] Regions │ │ - [ 9e96] currency │ │ - [ 9e9f] space separator │ │ - [ 9eaf] U_INPUT_TOO_LONG_ERROR │ │ - [ 9ec6] U_DIFFERENT_UCA_VERSION │ │ - [ 9ede] U_MALFORMED_UNICODE_ESCAPE │ │ - [ 9ef9] U_MULTIPLE_DECIMAL_SEPARATORS │ │ - [ 9f17] U_MF_OPERAND_MISMATCH_ERROR │ │ - [ 9f33] U_REGEX_NUMBER_TOO_BIG │ │ - [ 9f4a] U_REGEX_TIME_OUT │ │ - [ 9f5b] U_REGEX_INVALID_CAPTURE_GROUP_NAME │ │ - [ 9f7e] AOR │ │ - [ 9f82] BRL │ │ - [ 9f86] BYN │ │ - [ 9f8a] CHW │ │ - [ 9f8e] ERN │ │ - [ 9f92] GHC │ │ - [ 9f96] MKN │ │ - [ 9f9a] MNT │ │ - [ 9f9e] MZE │ │ - [ 9fa2] SBD │ │ - [ 9fa6] VUV │ │ - [ 9faa] frequency │ │ - [ 9fb4] BGJ │ │ - [ 9fb8] ohm │ │ - [ 9fbc] centimeter │ │ - [ 9fc7] ounce │ │ - [ 9fcd] fluid-ounce │ │ - [ 9fd9] accusative │ │ - [ 9fe4] plusSign │ │ - [ 9fed] ero │ │ - [ 9ff1] cubic- │ │ - [ 9ff8] /patternsLong │ │ - [ a006] tailoring primary after ignorables not supported │ │ - [ a037] factor │ │ - [ a03e] processor │ │ - [ a048] void swappy::SwappyCommon::startFrame() │ │ - [ a070] Swappy: CPU frame time │ │ - [ a087] charentered │ │ - [ a093] Error opening constellation boundaries file {}.\n │ │ - [ a0c4] Found non-string value in {} array.\n │ │ - [ a0e9] local │ │ - [ a0ef] phaselock │ │ - [ a0f9] Failed to get default measurement system {}, fallback to Metric system │ │ - [ a140] Earth │ │ - [ a146] invalid format │ │ - [ a155] {:.2f}" │ │ - [ a15d] Mpc │ │ - [ a161] ft │ │ - [ a164] Error opening {}\n │ │ - [ a176] Failed to load symbol: %s\n │ │ - [ a191] Channels: %d -> %d\n │ │ - [ a1ac] CHANNEL_BACK_LEFT │ │ - [ a1be] CHANNEL_AUX_0 │ │ - [ a1cc] CHANNEL_AUX_5 │ │ - [ a1da] CHANNEL_AUX_8 │ │ - [ a1e8] Unknown error │ │ - [ a1f6] flac │ │ - [ a1fb] Failed to start playing sound file {} │ │ - [ a221] AAudioStream_getFormat │ │ - [ a238] SL_IID_PLAY │ │ - [ a244] WAVE │ │ - [ a249] track │ │ - [ a24f] August │ │ - [ a256] Could not open font {}\n │ │ - [ a26e] brown │ │ - [ a274] mediumorchid │ │ - [ a281] oldlace │ │ - [ a289] .dds │ │ - [ a28e] .celx │ │ - [ a294] ~/.local/share │ │ - [ a2a3] TET │ │ - [ a2a7] Beta │ │ - [ a2ac] Iota │ │ - [ a2b1] Nu │ │ - [ a2b7] markers │ │ - [ a2bf] oceanus │ │ - [ a2c7] other │ │ - [ a2cd] planetorbits │ │ - [ a2da] setactiveview │ │ - [ a2e8] lookback │ │ - [ a2f1] fuzzypoints │ │ - [ a2fd] duration │ │ - [ a306] jd │ │ - [ a309] settimescale │ │ - [ a316] getdsocount │ │ - [ a322] takescreenshot │ │ - [ a331] createcelscript │ │ - [ a341] setaudiopan │ │ - [ a34d] One to four arguments expected to function celestia:printatpixel │ │ - [ a38e] Arguments to celestia:showlabel() must be strings │ │ - [ a3c0] Arguments to celestia:hidelabel() must be strings │ │ - [ a3f2] Argument to celestia:hideconstellations() must be a table │ │ - [ a42c] First argument to celestia:setconstellationcolor() must be a number │ │ - [ a470] No or one argument expected to function celestia:paused │ │ - [ a4a8] point │ │ - [ a4ae] Fourth arg to celestia:tojulianday must be a number │ │ - [ a4e2] One or two arguments expected for celestia:seturl │ │ - [ a514] WARNING:\n │ │ + [ 9029] libjpeg-turbo version 3.0.4 (build 20241209) │ │ + [ 9056] Suspension not allowed here │ │ + [ 9072] Bogus DHT index %d │ │ + [ 9085] Invalid JPEG file structure: two SOI markers │ │ + [ 90b2] with %d x %d thumbnail image │ │ + [ 90d3] Inconsistent progression sequence for component %d coefficient %d │ │ + [ 9115] BlueScale │ │ + [ 911f] FontName │ │ + [ 9128] lenBuildCharArray │ │ + [ 913a] 8859 │ │ + [ 913f] FOUNDRY │ │ + [ 9147] RAW_POINT_SIZE │ │ + [ 9156] RAW_SUBSCRIPT_Y │ │ + [ 9166] STRIKEOUT_ASCENT │ │ + [ 9177] STRIKEOUT_DESCENT │ │ + [ 9189] _MULE_BASELINE_OFFSET │ │ + [ 919f] W1X │ │ + [ 91a3] metamethod │ │ + [ 91ae] Snlf │ │ + [ 91b3] bytecode instructions │ │ + [ 91c9] _G │ │ + [ 91cc] too many captures │ │ + [ 91de] too many arguments │ │ + [ 91f1] yday │ │ + [ 91f6] open │ │ + [ 91fb] 'package.loaders' must be a table │ │ + [ 921d] Linux │ │ + [ 9223] Invalid image height in IHDR │ │ + [ 9240] rgb+alpha color-map: too few entries │ │ + [ 9265] bad width format │ │ + [ 9276] no space in chunk cache │ │ + [ 928e] Invalid interlace type specified │ │ + [ 92af] SPICE(EMPTYSTRING) │ │ + [ 92c2] op │ │ + [ 92c5] EXPLAIN │ │ + [ 92cd] Version Identification of GEF File is Invalid │ │ + [ 92fb] SPICE(INCOMPATIBLEUNITS) │ │ + [ 9314] SPICE(WINDOWTOOSMALL) │ │ + [ 932a] iswhsp_c │ │ + [ 9333] There is no room left in KEEPER to load another SPICE kernel. The current limit on the number of files that can be loaded is #. If you really need more than this many files, you should increase the parameter MAXFIL in the subroutine KEEPER. │ │ + [ 9427] SPICE(RECURSIVELOADING) │ │ + [ 943f] CK │ │ + [ 9442] CKUPF │ │ + [ 9448] RESUME │ │ + [ 944f] The file, '#', connected to unit # is not a DAF. │ │ + [ 9480] ZERO │ │ + [ 9485] truncation failed in endfile │ │ + [ 94a2] No address for record #, word #. │ │ + [ 94c3] cdue │ │ + [ 94c8] DAFBBS │ │ + [ 94cf] SPICE(EKSEGTABLEFULL) │ │ + [ 94e5] The EK file # could not be loaded; the segment # contains duplicate column names in table #. │ │ + [ 9542] EKUEF │ │ + [ 9548] fort.%ld │ │ + [ 9551] CARDC │ │ + [ 9557] SPICE(INSUFFLEN) │ │ + [ 9568] hnbufd │ │ + [ 956f] SPICE(INVALIDSUBLIST) │ │ + [ 9585] PCKBSR │ │ + [ 958c] chvals │ │ + [ 9593] GCPOOL │ │ + [ 959a] SPICE(BADVARNAME) │ │ + [ 95ac] INSLAI │ │ + [ 95b3] rot2 │ │ + [ 95b8] REMLAI │ │ + [ 95bf] cnvrtn │ │ + [ 95c6] Segment does not contain angular velocity data. │ │ + [ 95f6] Beginning address (#) greater than ending address (#). │ │ + [ 962d] vbuff │ │ + [ 9633] CKE02 │ │ + [ 9639] CKR06 │ │ + [ 963f] Input file # has architecture #. The file must be a binary SPK file to be readable by this routine. If the input file is an SPK file in transfer format, run TOBIN on the file to convert it to binary format. │ │ + [ 970f] The file name is blank. │ │ + [ 9727] IOSTAT error in INQUIRE statement. IOSTAT = #. │ │ + [ 9756] SPKPVN │ │ + [ 975d] sbound │ │ + [ 9764] SPKE17 │ │ + [ 976b] SPICE(BADSEMIAXIS) │ │ + [ 977e] SPKE21 │ │ + [ 9785] SPKR18 │ │ + [ 978c] Unexpected SPK type 18 subtype # found in type 18 segment. │ │ + [ 97c7] SPICE(DEGREEOUTOFRANGE) │ │ + [ 97df] NUT_PREC_PM │ │ + [ 97eb] LOCATI │ │ + [ 97f2] SPICE(BADVARIABLESIZE) │ │ + [ 9809] SPICE(NAMESDONOTMATCH) │ │ + [ 9820] lio │ │ + [ 9824] no imaginary part │ │ + [ 9836] SPICE(BADCOLUMNCOUNT) │ │ + [ 984c] bmat │ │ + [ 9851] Could not read non-native DAS integer record into character array. File = # Record number = #. IOSTAT = #. │ │ + [ 98bc] DLABBS │ │ + [ 98c3] ZZDYNBID │ │ + [ 98cc] Variable # not found after DTPOOL indicated it was present in pool. │ │ + [ 9910] ZZDYNFRM │ │ + [ 9919] AXIS │ │ + [ 991e] EULER │ │ + [ 9924] rrows │ │ + [ 992a] Column # should be CHR but has type #. │ │ + [ 9951] namidx │ │ + [ 9958] IAU_MERCURY_BARYCENTER │ │ + [ 996f] IAU_JUPITER │ │ + [ 997b] IAU_CALLISTO │ │ + [ 9988] IAU_TITANIA │ │ + [ 9994] IAU_THALASSA │ │ + [ 99a1] IAU_CHALDENE │ │ + [ 99ae] IAU_NIX │ │ + [ 99b6] The reference frame # is a dynamic frame. Dynamic frames may not be used at recursion level 1. │ │ + [ 9a15] USED ITEM COUNT │ │ + [ 9a25] CALLISTO │ │ + [ 9a2e] ALBIORIX │ │ + [ 9a37] TARQEQ │ │ + [ 9a3e] MOM │ │ + [ 9a42] WIND │ │ + [ 9a47] LP │ │ + [ 9a4a] VIKING 1 ORBITER │ │ + [ 9a5b] GRAIL-B │ │ + [ 9a63] CLUSTER 1 │ │ + [ 9a6d] NSYT │ │ + [ 9a72] SHOEMAKER-LEVY 9-V │ │ + [ 9a85] SHOEMAKER-LEVY 9-R │ │ + [ 9a98] AREND │ │ + [ 9a9e] BRADFIELD │ │ + [ 9aa8] DANIEL │ │ + [ 9aaf] DENNING-FUJIKAWA │ │ + [ 9ac0] MAURY │ │ + [ 9ac6] SHOEMAKER-LEVY 1 │ │ + [ 9ad7] NOTO │ │ + [ 9adc] DSS-43 │ │ + [ 9ae3] COMPILER │ │ + [ 9aec] zzdynrt0_ │ │ + [ 9af6] A kernel variable was not properly formed on line # of the file #. Such an assignment should have the form: ' [+]= '. This line was '#'. │ │ + [ 9b97] n │ │ + [ 9b99] Mmi │ │ + [ 9b9d] MmD │ │ + [ 9ba1] The month specified, #, was not an integer. The month must be an integer in the range from 1 to 12. │ │ + [ 9c06] TTRANS │ │ + [ 9c0d] TAI │ │ + [ 9c12] YMWDF │ │ + [ 9c19] The seconds component of '#' is out of range. In the specified time zone (#) leapseconds can occur during the year # only in the second that immediately follows the time #:#:59 on # # and # #. │ │ + [ 9cdc] AM │ │ + [ 9cdf] DD │ │ + [ 9ce2] Two substrings representing minutes of the hour were identified in the input time string <#> and <#>: " │ │ + [ 9d4a] Y-i/i:i:n │ │ + [ 9d54] Yimi:n │ │ + [ 9d5b] Ymii:i:n │ │ + [ 9d64] i-idi:n │ │ + [ 9d6c] i-iti:n │ │ + [ 9d74] i:i:iimY │ │ + [ 9d7d] i-i-itn │ │ + [ 9d85] i:i:ii-i-Y │ │ + [ 9d90] ZZTWOVXF │ │ + [ 9d99] und_ │ │ + [ 9d9e] ab │ │ + [ 9da1] brx │ │ + [ 9da5] dua │ │ + [ 9da9] es │ │ + [ 9dac] fj │ │ + [ 9daf] kam │ │ + [ 9db3] khw │ │ + [ 9db7] kk │ │ + [ 9dba] oc │ │ + [ 9dbd] sat │ │ + [ 9dc1] sbp │ │ + [ 9dc5] sdh │ │ + [ 9dc9] sm │ │ + [ 9dcc] bre │ │ + [ 9dd0] iii │ │ + [ 9dd4] mri │ │ + [ 9dd8] mkd │ │ + [ 9ddc] rus │ │ + [ 9de0] ven │ │ + [ 9de4] CQ │ │ + [ 9de7] ES │ │ + [ 9dea] JO │ │ + [ 9ded] KN │ │ + [ 9df0] MG │ │ + [ 9df3] NA │ │ + [ 9df6] PK │ │ + [ 9df9] BRB │ │ + [ 9dfd] CHE │ │ + [ 9e01] CHN │ │ + [ 9e05] FIN │ │ + [ 9e09] FJI │ │ + [ 9e0d] UGA │ │ + [ 9e11] my_MM │ │ + [ 9e17] heploc │ │ + [ 9e1e] hepburn │ │ + [ 9e26] __system_property_read_callback │ │ + [ 9e46] KRAT │ │ + [ 9e4b] PMDT │ │ + [ 9e50] FKST │ │ + [ 9e55] ar_IQ │ │ + [ 9e5b] dz_BT │ │ + [ 9e61] es_BO │ │ + [ 9e67] es_PY │ │ + [ 9e6d] fa_AF │ │ + [ 9e73] fo_FO │ │ + [ 9e79] fr_015 │ │ + [ 9e80] fr_029 │ │ + [ 9e87] no_NO_NY │ │ + [ 9e90] sah_RU │ │ + [ 9e97] xh_ZA │ │ + [ 9e9d] en-gb-oed │ │ + [ 9ea7] i-tao │ │ + [ 9ead] vgt │ │ + [ 9eb1] res_index │ │ + [ 9ebb] Regions │ │ + [ 9ec3] currency │ │ + [ 9ecc] space separator │ │ + [ 9edc] U_INPUT_TOO_LONG_ERROR │ │ + [ 9ef3] U_DIFFERENT_UCA_VERSION │ │ + [ 9f0b] U_MALFORMED_UNICODE_ESCAPE │ │ + [ 9f26] U_MULTIPLE_DECIMAL_SEPARATORS │ │ + [ 9f44] U_MF_OPERAND_MISMATCH_ERROR │ │ + [ 9f60] U_REGEX_NUMBER_TOO_BIG │ │ + [ 9f77] U_REGEX_TIME_OUT │ │ + [ 9f88] U_REGEX_INVALID_CAPTURE_GROUP_NAME │ │ + [ 9fab] AOR │ │ + [ 9faf] BRL │ │ + [ 9fb3] BYN │ │ + [ 9fb7] CHW │ │ + [ 9fbb] ERN │ │ + [ 9fbf] GHC │ │ + [ 9fc3] MKN │ │ + [ 9fc7] MNT │ │ + [ 9fcb] MZE │ │ + [ 9fcf] SBD │ │ + [ 9fd3] VUV │ │ + [ 9fd7] frequency │ │ + [ 9fe1] BGJ │ │ + [ 9fe5] ohm │ │ + [ 9fe9] centimeter │ │ + [ 9ff4] ounce │ │ + [ 9ffa] fluid-ounce │ │ + [ a006] accusative │ │ + [ a011] plusSign │ │ + [ a01a] ero │ │ + [ a01e] cubic- │ │ + [ a025] /patternsLong │ │ + [ a033] tailoring primary after ignorables not supported │ │ + [ a064] factor │ │ + [ a06b] processor │ │ + [ a075] void swappy::SwappyCommon::startFrame() │ │ + [ a09d] Swappy: CPU frame time │ │ + [ a0b4] charentered │ │ + [ a0c0] Error opening constellation boundaries file {}.\n │ │ + [ a0f1] Found non-string value in {} array.\n │ │ + [ a116] local │ │ + [ a11c] phaselock │ │ + [ a126] Failed to get default measurement system {}, fallback to Metric system │ │ + [ a16d] Earth │ │ + [ a173] invalid format │ │ + [ a182] {:.2f}" │ │ + [ a18a] Mpc │ │ + [ a18e] ft │ │ + [ a191] Error opening {}\n │ │ + [ a1a3] Failed to load symbol: %s\n │ │ + [ a1be] Channels: %d -> %d\n │ │ + [ a1d9] CHANNEL_BACK_LEFT │ │ + [ a1eb] CHANNEL_AUX_0 │ │ + [ a1f9] CHANNEL_AUX_5 │ │ + [ a207] CHANNEL_AUX_8 │ │ + [ a215] Unknown error │ │ + [ a223] flac │ │ + [ a228] Failed to start playing sound file {} │ │ + [ a24e] AAudioStream_getFormat │ │ + [ a265] SL_IID_PLAY │ │ + [ a271] WAVE │ │ + [ a276] track │ │ + [ a27c] August │ │ + [ a283] Could not open font {}\n │ │ + [ a29b] brown │ │ + [ a2a1] mediumorchid │ │ + [ a2ae] oldlace │ │ + [ a2b6] .dds │ │ + [ a2bb] .celx │ │ + [ a2c1] ~/.local/share │ │ + [ a2d0] TET │ │ + [ a2d4] Beta │ │ + [ a2d9] Iota │ │ + [ a2de] Nu │ │ + [ a2e4] markers │ │ + [ a2ec] oceanus │ │ + [ a2f4] other │ │ + [ a2fa] planetorbits │ │ + [ a307] setactiveview │ │ + [ a315] lookback │ │ + [ a31e] fuzzypoints │ │ + [ a32a] duration │ │ + [ a333] jd │ │ + [ a336] settimescale │ │ + [ a343] getdsocount │ │ + [ a34f] takescreenshot │ │ + [ a35e] createcelscript │ │ + [ a36e] setaudiopan │ │ + [ a37a] One to four arguments expected to function celestia:printatpixel │ │ + [ a3bb] Arguments to celestia:showlabel() must be strings │ │ + [ a3ed] Arguments to celestia:hidelabel() must be strings │ │ + [ a41f] Argument to celestia:hideconstellations() must be a table │ │ + [ a459] First argument to celestia:setconstellationcolor() must be a number │ │ + [ a49d] No or one argument expected to function celestia:paused │ │ + [ a4d5] point │ │ + [ a4db] Fourth arg to celestia:tojulianday must be a number │ │ + [ a50f] One or two arguments expected for celestia:seturl │ │ + [ a541] WARNING:\n │ │ This script requests permission to read/write files\n │ │ and execute external programs. Allowing this can be\n │ │ dangerous.\n │ │ Do you trust the script and want to allow this?\n │ │ y = yes, ESC = cancel script, any other key = no │ │ - [ a5f3] Error: LuaState invalid in Celx_SafeGetBoolean\n │ │ - [ a623] PushMatrix │ │ - [ a62e] QUADS │ │ - [ a634] Two arguments expected for gl.TexCoord() │ │ - [ a65d] One argument expected to function font:gettextwidth │ │ - [ a691] Argument 3 to object:setorbitcolor() must be a number │ │ - [ a6c7] body to body direction │ │ - [ a6de] Empty texture name passed to object:setringstexture() │ │ - [ a714] Selection object is empty! │ │ - [ a72f] One to two arguments expected to observer:gotosurface │ │ - [ a765] One argument required for setorientation │ │ - [ a78e] Bad position subtraction! │ │ - [ a7a8] [Vector] │ │ - [ a7b1] Bad vector multiplication! │ │ - [ a7cc] Optimized mesh groups: had {} groups, now: {} of them.\n │ │ - [ a804] saturn-sun │ │ - [ a80f] triton │ │ - [ a816] Loaded DE{} ephemeris. Valid from JD {:.8f} to JD {:.8f}\n │ │ - [ a850] Error opening ASCII sample file {}.\n │ │ - [ a875] Specified time interval for target {} not available.\n │ │ - [ a8ab] in_Brightness │ │ - [ a8b9] Crv │ │ - [ a8bd] Hyi │ │ - [ a8c1] Ori │ │ - [ a8c5] Pic │ │ - [ a8c9] Scl │ │ - [ a8cd] Radius │ │ - [ a8d4] Globular (core radius: %4.2f', King concentration: %4.2f) │ │ - [ a90e] PU │ │ - [ a911] LU │ │ - [ a914] Read a mesh of {} x {}\n │ │ - [ a92c] Object has incorrect spice orbit syntax.\n │ │ - [ a956] Object has incorrect UniformRotation syntax.\n │ │ - [ a984] Origin name missing from SPICE orbit\n │ │ - [ a9aa] Module │ │ - [ a9b1] Period cannot be zero.\n │ │ - [ a9c9] Frame name missing from SPICE rotation\n │ │ - [ a9f1] Ending specified for SPICE rotation, but beginning is missing.\n │ │ - [ aa31] Object has incorrect body-fixed frame syntax.\n │ │ - [ aa60] No center specified for reference frame.\n │ │ - [ aa8a] cloudShadowTexOffset │ │ - [ aa9f] normTexCoord = │ │ - [ aaaf] float shadowR;\n │ │ - [ aabf] * pow(NH, shininess) * │ │ - [ aad8] if (ringShadowTexCoordX >= 0.0 && ringShadowTexCoordX <= 1.0)\n │ │ + [ a620] Error: LuaState invalid in Celx_SafeGetBoolean\n │ │ + [ a650] PushMatrix │ │ + [ a65b] QUADS │ │ + [ a661] Two arguments expected for gl.TexCoord() │ │ + [ a68a] One argument expected to function font:gettextwidth │ │ + [ a6be] Argument 3 to object:setorbitcolor() must be a number │ │ + [ a6f4] body to body direction │ │ + [ a70b] Empty texture name passed to object:setringstexture() │ │ + [ a741] Selection object is empty! │ │ + [ a75c] One to two arguments expected to observer:gotosurface │ │ + [ a792] One argument required for setorientation │ │ + [ a7bb] Bad position subtraction! │ │ + [ a7d5] [Vector] │ │ + [ a7de] Bad vector multiplication! │ │ + [ a7f9] Optimized mesh groups: had {} groups, now: {} of them.\n │ │ + [ a831] saturn-sun │ │ + [ a83c] triton │ │ + [ a843] Loaded DE{} ephemeris. Valid from JD {:.8f} to JD {:.8f}\n │ │ + [ a87d] Error opening ASCII sample file {}.\n │ │ + [ a8a2] Specified time interval for target {} not available.\n │ │ + [ a8d8] in_Brightness │ │ + [ a8e6] Crv │ │ + [ a8ea] Hyi │ │ + [ a8ee] Ori │ │ + [ a8f2] Pic │ │ + [ a8f6] Scl │ │ + [ a8fa] Radius │ │ + [ a901] Globular (core radius: %4.2f', King concentration: %4.2f) │ │ + [ a93b] PU │ │ + [ a93e] LU │ │ + [ a941] Read a mesh of {} x {}\n │ │ + [ a959] Object has incorrect spice orbit syntax.\n │ │ + [ a983] Object has incorrect UniformRotation syntax.\n │ │ + [ a9b1] Origin name missing from SPICE orbit\n │ │ + [ a9d7] Module │ │ + [ a9de] Period cannot be zero.\n │ │ + [ a9f6] Frame name missing from SPICE rotation\n │ │ + [ aa1e] Ending specified for SPICE rotation, but beginning is missing.\n │ │ + [ aa5e] Object has incorrect body-fixed frame syntax.\n │ │ + [ aa8d] No center specified for reference frame.\n │ │ + [ aab7] cloudShadowTexOffset │ │ + [ aacc] normTexCoord = │ │ + [ aadc] float shadowR;\n │ │ + [ aaec] * pow(NH, shininess) * │ │ + [ ab05] if (ringShadowTexCoordX >= 0.0 && ringShadowTexCoordX <= 1.0)\n │ │ {\n │ │ - [ ab19] shadow *= 1.0 - texture2D(ringTex, vec2(ringShadowTexCoordX, 0.0), │ │ - [ ab5d] float cosTheta = dot(eyeDir, │ │ - [ ab7f] triangle_strip │ │ - [ ab8e] MeshScale │ │ - [ ab98] 2 │ │ - [ ab9a] Ia-0 │ │ - [ ab9f] StarDatabase::read: nStars = {}, time = {} ms\n │ │ - [ abce] Bad star definition at line {}.\n │ │ - [ abef] AppMag │ │ - [ abf6] AppMag cannot be used close to the origin │ │ - [ ac20] Failed to read entry {} of point array\n │ │ - [ ac48] Processing MaterialShininess chunk\n │ │ - [ ac6c] getY │ │ - [ ac71] , │ │ - [ ac74] engineStarted │ │ - [ ac82] cannot write to file │ │ - [ ac97] lli │ │ - [ ac9b] %s\n │ │ - [ ac9f] Insufficient memory (case %d) │ │ - [ acbd] Premature end of JPEG file │ │ - [ acd8] type1 │ │ - [ acde] FullName │ │ - [ ace7] UnderlineThickness │ │ - [ acfa] SubrMapOffset │ │ - [ ad08] winfonts │ │ - [ ad11] AVERAGE_WIDTH │ │ - [ ad1f] SPACING │ │ - [ ad27] RAW_AVERAGE_WIDTH │ │ - [ ad39] RAW_FIGURE_WIDTH │ │ - [ ad4a] RAW_PIXEL_SIZE │ │ - [ ad59] RAW_SUBSCRIPT_SIZE │ │ - [ ad6c] default-script │ │ - [ ad7b] smooth │ │ - [ ad82] PCC │ │ - [ ad86] StartDirection │ │ - [ ad95] dead │ │ - [ ad9a] 'package.preload' must be a table │ │ - [ adbc] unexpected zlib return code │ │ - [ add8] RGB color space not permitted on grayscale PNG │ │ - [ ae07] Invalid image width in IHDR │ │ - [ ae23] Invalid color type in IHDR │ │ - [ ae3e] fixed point overflow ignored │ │ - [ ae5b] internal sequential row size calculation error │ │ - [ ae8a] bad data option (internal error) │ │ - [ aeab] bad compression info │ │ - [ aec0] Only compression windows >= 256 supported by PNG │ │ - [ aef1] Ignoring attempt to write bKGD chunk out-of-range for bit_depth │ │ - [ af31] iTXt: uncompressed text too long │ │ - [ af52] String "#" has length #; must be >= 2. │ │ - [ af79] SPICE(TRACEBACKOVERFLOW) │ │ - [ af92] SPICE(WINDOWEXCESS) │ │ - [ afa6] KERNELS_TO_LOAD │ │ - [ afb6] There is no room left in KEEPER to load another SPICE kernel. The current limit on the number of files that can be loaded is #. │ │ - [ b036] itruex │ │ - [ b03d] ADD TO FRONT │ │ - [ b04a] READ │ │ - [ b04f] FILE_FORMAT │ │ - [ b05b] An element could not be inserted into the set due to lack of space; set size is #. │ │ - [ b0ae] Attempt was made to write to a read-only file. │ │ - [ b0dd] The EK file # could not be loaded; the maximum number of distinct tables has already been reached. │ │ - [ b140] SPICE(EKTABLELISTFULL) │ │ - [ b157] SPICE(EKCOLATTRTABLEFULL) │ │ - [ b171] ops │ │ - [ b175] cends │ │ - [ b17b] chtype │ │ - [ b182] DAS SCRATCH FILE │ │ - [ b193] lastwd │ │ - [ b19a] Attempt to read file record failed. File was '#'. Value of IOSTAT was '#'. │ │ - [ b1e6] DASHLU │ │ - [ b1ed] DASHOF │ │ - [ b1f4] APPNDI │ │ - [ b1fb] Directory record # in DAS file with handle # is probably corrupted. No high cluster address at or above the input address # was found, though it should have been. High address was #. Data type was #. │ │ - [ b2c3] Could not write DAS double precision record. File = # Record number = #. IOSTAT = #. │ │ - [ b318] dassdr_ │ │ - [ b320] RDKER: You have called an entry which performs no run-time function. This may indicate a bug. Please check the documentation for the subroutine RDKER. │ │ - [ b3b7] RDKNEW │ │ - [ b3be] RDTEXT │ │ - [ b3c5] fndlun_ │ │ - [ b3cd] FRMNAM │ │ - [ b3d4] kcent │ │ - [ b3da] An unexpected character was found while attempting to parse the input string. │ │ - [ b429] CONVRT │ │ - [ b430] SPICE(DIVIDEBYZERO) │ │ - [ b444] SPICE(SCLKTRUNCATED) │ │ - [ b459] TDB │ │ - [ b45d] integer │ │ - [ b465] KPL │ │ - [ b469] CKFXFM │ │ - [ b470] SPK type # is not supported in your version of the SPICE library. You will need to upgrade your version of the library to make use of ephemerides that contain this SPK data type. │ │ - [ b525] spke19_ │ │ - [ b52d] The trajectory pole vector supplied to SPKE15 had length zero. The most likely cause of this problem is a corrupted SPK (ephemeris) file. │ │ - [ b5b8] KPSOLV │ │ - [ b5bf] CHBIGR │ │ - [ b5c6] SPICE(WRONGSPKTYPE) │ │ - [ b5da] SPKR13 │ │ - [ b5e1] bpcref │ │ - [ b5e8] BODY#_CONSTANTS_JED_EPOCH │ │ - [ b602] BODY#_CONSTS_JED_EPOCH │ │ - [ b619] sinth │ │ - [ b61f] EUL2M │ │ - [ b625] BODFND │ │ - [ b62c] alt │ │ - [ b630] begindata │ │ - [ b63b] WNFETD: No such interval. │ │ - [ b655] ZZCLN │ │ - [ b65b] The attempt to load file, '#', with architecture, '#', failed because this file architecture is unsupported. │ │ - [ b6c8] SPICE(FTFULL) │ │ - [ b6d6] Attempt to open file, '#', for read access has failed. This file utilizes an unknown binary file format. This error may result from attempting to open a corrupt file or one of an unknown type. │ │ - [ b799] Invalid access method. This error should never be signaled. │ │ - [ b7d5] TWO-VECTOR │ │ - [ b7e0] OBSERVER_TARGET_POSITION │ │ - [ b7f9] The kernel variable # has used to define frame # was not found after DTPOOL indicated it was present in pool. │ │ - [ b867] spoint │ │ - [ b86e] lrows │ │ - [ b874] SPICE(UNNATURALRELATION) │ │ - [ b88d] The segment type # is not supported. │ │ - [ b8b2] CHR page = #; valid range is [1:#] │ │ - [ b8d5] ZZEKPGRI │ │ - [ b8de] ZZEKPGPG │ │ - [ b8e7] String end index must be in the range #:# but was #. │ │ - [ b91c] Column type is #; value type is #. │ │ - [ b93f] Runaway node pointer chain. Key = #; valid range = 1:#. Tree = #, file = # │ │ - [ b98b] An attempt to copy a C string to a temporary string of length # failed. This may be due to an unterminated input string. │ │ - [ ba05] IAU_PASIPHAE │ │ - [ ba12] IAU_TRITON │ │ - [ ba1d] VENUS_BARYCENTER │ │ - [ ba2e] ENCELADUS │ │ - [ ba38] TELESTO │ │ - [ ba40] YMIR │ │ - [ ba45] MUNDILFARI │ │ - [ ba50] NARVI │ │ - [ ba56] POLYDEUCES │ │ - [ ba61] BESTLA │ │ - [ ba68] CHARON │ │ - [ ba6f] VCO │ │ - [ ba73] STARDUST │ │ - [ ba7c] HST │ │ - [ ba80] OSIRIS-REX │ │ - [ ba8b] EPOXI │ │ - [ ba91] SOLAR ORBITER │ │ - [ ba9f] EXM ROVER │ │ - [ baa9] VSAT │ │ - [ baae] SELENE Vstar │ │ - [ babb] JACKSON-NEUJMIN │ │ - [ bacb] SCHWASSMANN-WACHMANN 2 │ │ - [ bae2] SHOEMAKER 2 │ │ - [ baee] STEPHAN-OTERMA │ │ - [ bafd] LOVAS 2 │ │ - [ bb05] PALLAS │ │ - [ bb0c] QUETA │ │ - [ bb12] DSS-28 │ │ - [ bb19] DSS-45 │ │ - [ bb20] LTL-IEEE │ │ - [ bb29] ZZDYNRT0 │ │ - [ bb32] *j* │ │ - [ bb36] *N* │ │ - [ bb3a] SCLK_DATA_TYPE_ │ │ - [ bb4a] kvmaxn │ │ - [ bb51] SPICE(BADFRAME) │ │ - [ bb61] Aberration correction flag # calls for stellar aberration but not light time corrections. This combination is not expected. │ │ - [ bbdd] ZZSPKPA0 │ │ - [ bbe6] bascnt │ │ - [ bbed] SPICE(NOPICTURE) │ │ - [ bbfe] Hour │ │ - [ bc03] Second │ │ - [ bc0a] Julian Date indicator │ │ - [ bc20] JUNE │ │ - [ bc25] Y-i/i:i │ │ - [ bc2d] i-Ydi:n │ │ - [ bc35] i-iti:i │ │ - [ bc3d] iid │ │ - [ bc41] YDmHM │ │ - [ bc47] imii:i:n │ │ - [ bc50] inY │ │ - [ bc54] i/i/ii:i:i │ │ - [ bc5f] Y-i-itn │ │ - [ bc67] i-itx │ │ - [ bc6d] i-i-itnx │ │ - [ bc76] The caller specified that # double precision numbers are to be translated from binary format # to #. However there is only room to hold # integers in the output array. This error should never occur. │ │ - [ bd3f] RH │ │ - [ bd42] GB │ │ - [ bd45] gan │ │ - [ bd49] ang │ │ - [ bd4d] arc │ │ - [ bd51] bg │ │ - [ bd54] bjn │ │ - [ bd58] bm │ │ - [ bd5b] byn │ │ - [ bd5f] cad │ │ - [ bd63] csb │ │ - [ bd67] fan │ │ - [ bd6b] frm │ │ - [ bd6f] is │ │ - [ bd72] it │ │ - [ bd75] koi │ │ - [ bd79] krl │ │ - [ bd7d] lad │ │ - [ bd81] li │ │ - [ bd84] sam │ │ - [ bd88] tsi │ │ - [ bd8c] swc │ │ - [ bd90] afr │ │ - [ bd94] cha │ │ - [ bd98] chu │ │ - [ bd9c] kor │ │ - [ bda0] mlg │ │ - [ bda4] roh │ │ - [ bda8] wln │ │ - [ bdac] yor │ │ - [ bdb0] BI │ │ - [ bdb3] DG │ │ - [ bdb6] NC │ │ - [ bdb9] NF │ │ - [ bdbc] WS │ │ - [ bdbf] ALB │ │ - [ bdc3] CYP │ │ - [ bdc7] MHL │ │ - [ bdcb] NCL │ │ - [ bdcf] SLE │ │ - [ bdd3] SSD │ │ - [ bdd7] VNM │ │ - [ bddb] XKK │ │ - [ bddf] ZWE │ │ - [ bde3] TMP │ │ - [ bde7] et_EE │ │ - [ bded] is_IS │ │ - [ bdf3] mn_MN │ │ - [ bdf9] NY │ │ - [ bdfc] Asia/Choibalsan │ │ - [ be0c] OMST │ │ - [ be11] YEKT │ │ - [ be16] VOLST │ │ - [ be1c] EEST │ │ - [ be21] Africa/Windhoek │ │ - [ be31] America/Miquelon │ │ - [ be42] America/Godthab │ │ - [ be52] ICU_TIMEZONE_FILES_DIR │ │ - [ be69] trie │ │ - [ be6e] ar_BH │ │ - [ be74] ar_MA │ │ - [ be7a] en_AU │ │ - [ be80] en_ZW │ │ - [ be86] es_MX │ │ - [ be8c] fr_RE │ │ - [ be92] bs_Latn_BA │ │ - [ be9d] pa_Arab_PK │ │ - [ bea8] ts_ZA │ │ - [ beae] sgn-be-nl │ │ - [ beb8] ucnv_openAlgorithmic │ │ - [ becd] resc │ │ - [ bed2] hebrew │ │ - [ bed9] ethiopic │ │ - [ bee2] M03 │ │ - [ bee6] contextTransforms │ │ - [ bef8] Countries%short │ │ - [ bf08] unassigned │ │ - [ bf13] enclosing mark │ │ - [ bf22] decimal digit number │ │ - [ bf37] initial punctuation │ │ - [ bf4b] U_INVALID_TABLE_FORMAT │ │ - [ bf62] U_MISPLACED_QUANTIFIER │ │ - [ bf79] U_ILLEGAL_CHAR_IN_SEGMENT │ │ - [ bf93] U_INTERNAL_TRANSLITERATOR_ERROR │ │ - [ bfb3] U_BRK_ASSIGN_ERROR │ │ - [ bfc6] U_BRK_NEW_LINE_IN_QUOTED_STRING │ │ - [ bfe6] U_PLUGIN_DIDNT_SET_LEVEL │ │ - [ bfff] BYR │ │ - [ c003] EEK │ │ - [ c007] FJD │ │ - [ c00b] GHS │ │ - [ c00f] LKR │ │ - [ c013] TOP │ │ - [ c017] transPre32 │ │ - [ c022] M04L │ │ - [ c027] M07L │ │ - [ c02c] terabit │ │ - [ c034] dot │ │ - [ c038] pixel-per-inch │ │ - [ c047] watt │ │ - [ c04c] cup │ │ - [ c050] hectoliter │ │ - [ c05b] dative │ │ - [ c062] minusSign │ │ - [ c06c] deka │ │ - [ c071] case │ │ - [ c076] dn │ │ - [ c079] account │ │ - [ c081] tertiary tailoring gap too small │ │ - [ c0a2] starred-relation string range is not all NFD-inert │ │ - [ c0d5] last variable │ │ - [ c0e3] in3_to_m3 │ │ - [ c0ed] glucose_molar_mass │ │ - [ c100] AChoreographerFrameCallbackData_getFrameTimelineDeadlineNanos │ │ - [ c13e] /proc/cpuinfo │ │ - [ c14c] thread constructor failed │ │ - [ c166] android/app/NativeActivity │ │ - [ c181] android/view/WindowManager │ │ - [ c19c] mousebuttonup │ │ - [ c1aa] Anti-aliasing enabled │ │ - [ c1c0] cel: │ │ - [ c1c5] argument not found │ │ - [ c1d8] StarNameDatabase │ │ - [ c1e9] LinearFadeFraction │ │ - [ c1fc] OrbitPathSamplePoints │ │ - [ c212] Renderer: %s\n │ │ - [ c220] minutes │ │ - [ c228] Rotation period: {} {}\n │ │ - [ c240] solar system │ │ - [ c24d] NEON: %s\n │ │ - [ c25b] Conversion:\n │ │ - [ c26c] CHANNEL_MONO │ │ - [ c279] 0.12.42 │ │ - [ c281] libaaudio.so │ │ - [ c28e] AAudioStreamBuilder_delete │ │ - [ c2a9] AAudioStreamBuilder_setInputPreset │ │ - [ c2cc] ox │ │ - [ c2cf] February │ │ - [ c2d8] lightgoldenrodyellow │ │ - [ c2ed] palegreen │ │ - [ c2f7] pink │ │ - [ c2fc] salmon │ │ - [ c303] .jpeg │ │ - [ c309] .clx │ │ - [ c30e] .cmod │ │ - [ c318] COM │ │ - [ c31c] Celestia │ │ - [ c325] planitia │ │ - [ c32e] planetographicgrid │ │ - [ c341] Unknown command name '{}' │ │ - [ c35b] cls │ │ - [ c35f] splitview │ │ - [ c369] up │ │ - [ c36c] radius │ │ - [ c373] Second argument to celestia:setsafeareainsets() must be a number │ │ - [ c3b4] getscreendpi │ │ - [ c3c1] getlabelflags │ │ - [ c3cf] getorbitflags │ │ - [ c3dd] gettextcolor │ │ - [ c3ea] geteventhandler │ │ - [ c3fa] windowbordersvisible │ │ - [ c40f] setaudioloop │ │ - [ c41c] getcategories │ │ - [ c42a] Second argument to celestia:flash must be a number │ │ - [ c45d] One argument expected to function celestia:setaltazimuthmode │ │ - [ c49a] Values in table-argument to celestia:setrenderflags() must be boolean │ │ - [ c4e0] Unknown key: {}\n │ │ - [ c4f1] setlabelcolor: color values must be numbers │ │ - [ c51d] One argument expected for function celestia:find() │ │ - [ c550] Internal Error: renderer is nullptr! │ │ - [ c575] disc │ │ - [ c57a] First arg to celestia:utctotdb must be a number │ │ - [ c5aa] Second arg to celestia:newvector must be a number │ │ - [ c5dc] Argument to celestia:runscript must be a string │ │ - [ c60c] Third argument to celestia:overlay must be a number (yoffset) │ │ - [ c64a] Function celestia:setaudioloop requires two arguments │ │ - [ c680] Third argument to celestia:loadtexture must be a string │ │ - [ c6b8] WARNING:\n │ │ + [ ab46] shadow *= 1.0 - texture2D(ringTex, vec2(ringShadowTexCoordX, 0.0), │ │ + [ ab8a] float cosTheta = dot(eyeDir, │ │ + [ abac] triangle_strip │ │ + [ abbb] MeshScale │ │ + [ abc5] 2 │ │ + [ abc7] Ia-0 │ │ + [ abcc] StarDatabase::read: nStars = {}, time = {} ms\n │ │ + [ abfb] Bad star definition at line {}.\n │ │ + [ ac1c] AppMag │ │ + [ ac23] AppMag cannot be used close to the origin │ │ + [ ac4d] Failed to read entry {} of point array\n │ │ + [ ac75] Processing MaterialShininess chunk\n │ │ + [ ac99] getY │ │ + [ ac9e] , │ │ + [ aca1] engineStarted │ │ + [ acaf] cannot write to file │ │ + [ acc4] lli │ │ + [ acc8] %s\n │ │ + [ accc] Insufficient memory (case %d) │ │ + [ acea] Premature end of JPEG file │ │ + [ ad05] type1 │ │ + [ ad0b] FullName │ │ + [ ad14] UnderlineThickness │ │ + [ ad27] SubrMapOffset │ │ + [ ad35] winfonts │ │ + [ ad3e] AVERAGE_WIDTH │ │ + [ ad4c] SPACING │ │ + [ ad54] RAW_AVERAGE_WIDTH │ │ + [ ad66] RAW_FIGURE_WIDTH │ │ + [ ad77] RAW_PIXEL_SIZE │ │ + [ ad86] RAW_SUBSCRIPT_SIZE │ │ + [ ad99] default-script │ │ + [ ada8] smooth │ │ + [ adaf] PCC │ │ + [ adb3] StartDirection │ │ + [ adc2] dead │ │ + [ adc7] 'package.preload' must be a table │ │ + [ ade9] unexpected zlib return code │ │ + [ ae05] RGB color space not permitted on grayscale PNG │ │ + [ ae34] Invalid image width in IHDR │ │ + [ ae50] Invalid color type in IHDR │ │ + [ ae6b] fixed point overflow ignored │ │ + [ ae88] internal sequential row size calculation error │ │ + [ aeb7] bad data option (internal error) │ │ + [ aed8] bad compression info │ │ + [ aeed] Only compression windows >= 256 supported by PNG │ │ + [ af1e] Ignoring attempt to write bKGD chunk out-of-range for bit_depth │ │ + [ af5e] iTXt: uncompressed text too long │ │ + [ af7f] String "#" has length #; must be >= 2. │ │ + [ afa6] SPICE(TRACEBACKOVERFLOW) │ │ + [ afbf] SPICE(WINDOWEXCESS) │ │ + [ afd3] KERNELS_TO_LOAD │ │ + [ afe3] There is no room left in KEEPER to load another SPICE kernel. The current limit on the number of files that can be loaded is #. │ │ + [ b063] itruex │ │ + [ b06a] ADD TO FRONT │ │ + [ b077] READ │ │ + [ b07c] FILE_FORMAT │ │ + [ b088] An element could not be inserted into the set due to lack of space; set size is #. │ │ + [ b0db] Attempt was made to write to a read-only file. │ │ + [ b10a] The EK file # could not be loaded; the maximum number of distinct tables has already been reached. │ │ + [ b16d] SPICE(EKTABLELISTFULL) │ │ + [ b184] SPICE(EKCOLATTRTABLEFULL) │ │ + [ b19e] ops │ │ + [ b1a2] cends │ │ + [ b1a8] chtype │ │ + [ b1af] DAS SCRATCH FILE │ │ + [ b1c0] lastwd │ │ + [ b1c7] Attempt to read file record failed. File was '#'. Value of IOSTAT was '#'. │ │ + [ b213] DASHLU │ │ + [ b21a] DASHOF │ │ + [ b221] APPNDI │ │ + [ b228] Directory record # in DAS file with handle # is probably corrupted. No high cluster address at or above the input address # was found, though it should have been. High address was #. Data type was #. │ │ + [ b2f0] Could not write DAS double precision record. File = # Record number = #. IOSTAT = #. │ │ + [ b345] dassdr_ │ │ + [ b34d] RDKER: You have called an entry which performs no run-time function. This may indicate a bug. Please check the documentation for the subroutine RDKER. │ │ + [ b3e4] RDKNEW │ │ + [ b3eb] RDTEXT │ │ + [ b3f2] fndlun_ │ │ + [ b3fa] FRMNAM │ │ + [ b401] kcent │ │ + [ b407] An unexpected character was found while attempting to parse the input string. │ │ + [ b456] CONVRT │ │ + [ b45d] SPICE(DIVIDEBYZERO) │ │ + [ b471] SPICE(SCLKTRUNCATED) │ │ + [ b486] TDB │ │ + [ b48a] integer │ │ + [ b492] KPL │ │ + [ b496] CKFXFM │ │ + [ b49d] SPK type # is not supported in your version of the SPICE library. You will need to upgrade your version of the library to make use of ephemerides that contain this SPK data type. │ │ + [ b552] spke19_ │ │ + [ b55a] The trajectory pole vector supplied to SPKE15 had length zero. The most likely cause of this problem is a corrupted SPK (ephemeris) file. │ │ + [ b5e5] KPSOLV │ │ + [ b5ec] CHBIGR │ │ + [ b5f3] SPICE(WRONGSPKTYPE) │ │ + [ b607] SPKR13 │ │ + [ b60e] bpcref │ │ + [ b615] BODY#_CONSTANTS_JED_EPOCH │ │ + [ b62f] BODY#_CONSTS_JED_EPOCH │ │ + [ b646] sinth │ │ + [ b64c] EUL2M │ │ + [ b652] BODFND │ │ + [ b659] alt │ │ + [ b65d] begindata │ │ + [ b668] WNFETD: No such interval. │ │ + [ b682] ZZCLN │ │ + [ b688] The attempt to load file, '#', with architecture, '#', failed because this file architecture is unsupported. │ │ + [ b6f5] SPICE(FTFULL) │ │ + [ b703] Attempt to open file, '#', for read access has failed. This file utilizes an unknown binary file format. This error may result from attempting to open a corrupt file or one of an unknown type. │ │ + [ b7c6] Invalid access method. This error should never be signaled. │ │ + [ b802] TWO-VECTOR │ │ + [ b80d] OBSERVER_TARGET_POSITION │ │ + [ b826] The kernel variable # has used to define frame # was not found after DTPOOL indicated it was present in pool. │ │ + [ b894] spoint │ │ + [ b89b] lrows │ │ + [ b8a1] SPICE(UNNATURALRELATION) │ │ + [ b8ba] The segment type # is not supported. │ │ + [ b8df] CHR page = #; valid range is [1:#] │ │ + [ b902] ZZEKPGRI │ │ + [ b90b] ZZEKPGPG │ │ + [ b914] String end index must be in the range #:# but was #. │ │ + [ b949] Column type is #; value type is #. │ │ + [ b96c] Runaway node pointer chain. Key = #; valid range = 1:#. Tree = #, file = # │ │ + [ b9b8] An attempt to copy a C string to a temporary string of length # failed. This may be due to an unterminated input string. │ │ + [ ba32] IAU_PASIPHAE │ │ + [ ba3f] IAU_TRITON │ │ + [ ba4a] VENUS_BARYCENTER │ │ + [ ba5b] ENCELADUS │ │ + [ ba65] TELESTO │ │ + [ ba6d] YMIR │ │ + [ ba72] MUNDILFARI │ │ + [ ba7d] NARVI │ │ + [ ba83] POLYDEUCES │ │ + [ ba8e] BESTLA │ │ + [ ba95] CHARON │ │ + [ ba9c] VCO │ │ + [ baa0] STARDUST │ │ + [ baa9] HST │ │ + [ baad] OSIRIS-REX │ │ + [ bab8] EPOXI │ │ + [ babe] SOLAR ORBITER │ │ + [ bacc] EXM ROVER │ │ + [ bad6] VSAT │ │ + [ badb] SELENE Vstar │ │ + [ bae8] JACKSON-NEUJMIN │ │ + [ baf8] SCHWASSMANN-WACHMANN 2 │ │ + [ bb0f] SHOEMAKER 2 │ │ + [ bb1b] STEPHAN-OTERMA │ │ + [ bb2a] LOVAS 2 │ │ + [ bb32] PALLAS │ │ + [ bb39] QUETA │ │ + [ bb3f] DSS-28 │ │ + [ bb46] DSS-45 │ │ + [ bb4d] LTL-IEEE │ │ + [ bb56] ZZDYNRT0 │ │ + [ bb5f] *j* │ │ + [ bb63] *N* │ │ + [ bb67] SCLK_DATA_TYPE_ │ │ + [ bb77] kvmaxn │ │ + [ bb7e] SPICE(BADFRAME) │ │ + [ bb8e] Aberration correction flag # calls for stellar aberration but not light time corrections. This combination is not expected. │ │ + [ bc0a] ZZSPKPA0 │ │ + [ bc13] bascnt │ │ + [ bc1a] SPICE(NOPICTURE) │ │ + [ bc2b] Hour │ │ + [ bc30] Second │ │ + [ bc37] Julian Date indicator │ │ + [ bc4d] JUNE │ │ + [ bc52] Y-i/i:i │ │ + [ bc5a] i-Ydi:n │ │ + [ bc62] i-iti:i │ │ + [ bc6a] iid │ │ + [ bc6e] YDmHM │ │ + [ bc74] imii:i:n │ │ + [ bc7d] inY │ │ + [ bc81] i/i/ii:i:i │ │ + [ bc8c] Y-i-itn │ │ + [ bc94] i-itx │ │ + [ bc9a] i-i-itnx │ │ + [ bca3] The caller specified that # double precision numbers are to be translated from binary format # to #. However there is only room to hold # integers in the output array. This error should never occur. │ │ + [ bd6c] RH │ │ + [ bd6f] GB │ │ + [ bd72] gan │ │ + [ bd76] ang │ │ + [ bd7a] arc │ │ + [ bd7e] bg │ │ + [ bd81] bjn │ │ + [ bd85] bm │ │ + [ bd88] byn │ │ + [ bd8c] cad │ │ + [ bd90] csb │ │ + [ bd94] fan │ │ + [ bd98] frm │ │ + [ bd9c] is │ │ + [ bd9f] it │ │ + [ bda2] koi │ │ + [ bda6] krl │ │ + [ bdaa] lad │ │ + [ bdae] li │ │ + [ bdb1] sam │ │ + [ bdb5] tsi │ │ + [ bdb9] swc │ │ + [ bdbd] afr │ │ + [ bdc1] cha │ │ + [ bdc5] chu │ │ + [ bdc9] kor │ │ + [ bdcd] mlg │ │ + [ bdd1] roh │ │ + [ bdd5] wln │ │ + [ bdd9] yor │ │ + [ bddd] BI │ │ + [ bde0] DG │ │ + [ bde3] NC │ │ + [ bde6] NF │ │ + [ bde9] WS │ │ + [ bdec] ALB │ │ + [ bdf0] CYP │ │ + [ bdf4] MHL │ │ + [ bdf8] NCL │ │ + [ bdfc] SLE │ │ + [ be00] SSD │ │ + [ be04] VNM │ │ + [ be08] XKK │ │ + [ be0c] ZWE │ │ + [ be10] TMP │ │ + [ be14] et_EE │ │ + [ be1a] is_IS │ │ + [ be20] mn_MN │ │ + [ be26] NY │ │ + [ be29] Asia/Choibalsan │ │ + [ be39] OMST │ │ + [ be3e] YEKT │ │ + [ be43] VOLST │ │ + [ be49] EEST │ │ + [ be4e] Africa/Windhoek │ │ + [ be5e] America/Miquelon │ │ + [ be6f] America/Godthab │ │ + [ be7f] ICU_TIMEZONE_FILES_DIR │ │ + [ be96] trie │ │ + [ be9b] ar_BH │ │ + [ bea1] ar_MA │ │ + [ bea7] en_AU │ │ + [ bead] en_ZW │ │ + [ beb3] es_MX │ │ + [ beb9] fr_RE │ │ + [ bebf] bs_Latn_BA │ │ + [ beca] pa_Arab_PK │ │ + [ bed5] ts_ZA │ │ + [ bedb] sgn-be-nl │ │ + [ bee5] ucnv_openAlgorithmic │ │ + [ befa] resc │ │ + [ beff] hebrew │ │ + [ bf06] ethiopic │ │ + [ bf0f] M03 │ │ + [ bf13] contextTransforms │ │ + [ bf25] Countries%short │ │ + [ bf35] unassigned │ │ + [ bf40] enclosing mark │ │ + [ bf4f] decimal digit number │ │ + [ bf64] initial punctuation │ │ + [ bf78] U_INVALID_TABLE_FORMAT │ │ + [ bf8f] U_MISPLACED_QUANTIFIER │ │ + [ bfa6] U_ILLEGAL_CHAR_IN_SEGMENT │ │ + [ bfc0] U_INTERNAL_TRANSLITERATOR_ERROR │ │ + [ bfe0] U_BRK_ASSIGN_ERROR │ │ + [ bff3] U_BRK_NEW_LINE_IN_QUOTED_STRING │ │ + [ c013] U_PLUGIN_DIDNT_SET_LEVEL │ │ + [ c02c] BYR │ │ + [ c030] EEK │ │ + [ c034] FJD │ │ + [ c038] GHS │ │ + [ c03c] LKR │ │ + [ c040] TOP │ │ + [ c044] transPre32 │ │ + [ c04f] M04L │ │ + [ c054] M07L │ │ + [ c059] terabit │ │ + [ c061] dot │ │ + [ c065] pixel-per-inch │ │ + [ c074] watt │ │ + [ c079] cup │ │ + [ c07d] hectoliter │ │ + [ c088] dative │ │ + [ c08f] minusSign │ │ + [ c099] deka │ │ + [ c09e] case │ │ + [ c0a3] dn │ │ + [ c0a6] account │ │ + [ c0ae] tertiary tailoring gap too small │ │ + [ c0cf] starred-relation string range is not all NFD-inert │ │ + [ c102] last variable │ │ + [ c110] in3_to_m3 │ │ + [ c11a] glucose_molar_mass │ │ + [ c12d] AChoreographerFrameCallbackData_getFrameTimelineDeadlineNanos │ │ + [ c16b] /proc/cpuinfo │ │ + [ c179] thread constructor failed │ │ + [ c193] android/app/NativeActivity │ │ + [ c1ae] android/view/WindowManager │ │ + [ c1c9] mousebuttonup │ │ + [ c1d7] Anti-aliasing enabled │ │ + [ c1ed] cel: │ │ + [ c1f2] argument not found │ │ + [ c205] StarNameDatabase │ │ + [ c216] LinearFadeFraction │ │ + [ c229] OrbitPathSamplePoints │ │ + [ c23f] Renderer: %s\n │ │ + [ c24d] minutes │ │ + [ c255] Rotation period: {} {}\n │ │ + [ c26d] solar system │ │ + [ c27a] NEON: %s\n │ │ + [ c288] Conversion:\n │ │ + [ c299] CHANNEL_MONO │ │ + [ c2a6] 0.12.42 │ │ + [ c2ae] libaaudio.so │ │ + [ c2bb] AAudioStreamBuilder_delete │ │ + [ c2d6] AAudioStreamBuilder_setInputPreset │ │ + [ c2f9] ox │ │ + [ c2fc] February │ │ + [ c305] lightgoldenrodyellow │ │ + [ c31a] palegreen │ │ + [ c324] pink │ │ + [ c329] salmon │ │ + [ c330] .jpeg │ │ + [ c336] .clx │ │ + [ c33b] .cmod │ │ + [ c345] COM │ │ + [ c349] Celestia │ │ + [ c352] planitia │ │ + [ c35b] planetographicgrid │ │ + [ c36e] Unknown command name '{}' │ │ + [ c388] cls │ │ + [ c38c] splitview │ │ + [ c396] up │ │ + [ c399] radius │ │ + [ c3a0] Second argument to celestia:setsafeareainsets() must be a number │ │ + [ c3e1] getscreendpi │ │ + [ c3ee] getlabelflags │ │ + [ c3fc] getorbitflags │ │ + [ c40a] gettextcolor │ │ + [ c417] geteventhandler │ │ + [ c427] windowbordersvisible │ │ + [ c43c] setaudioloop │ │ + [ c449] getcategories │ │ + [ c457] Second argument to celestia:flash must be a number │ │ + [ c48a] One argument expected to function celestia:setaltazimuthmode │ │ + [ c4c7] Values in table-argument to celestia:setrenderflags() must be boolean │ │ + [ c50d] Unknown key: {}\n │ │ + [ c51e] setlabelcolor: color values must be numbers │ │ + [ c54a] One argument expected for function celestia:find() │ │ + [ c57d] Internal Error: renderer is nullptr! │ │ + [ c5a2] disc │ │ + [ c5a7] First arg to celestia:utctotdb must be a number │ │ + [ c5d7] Second arg to celestia:newvector must be a number │ │ + [ c609] Argument to celestia:runscript must be a string │ │ + [ c639] Third argument to celestia:overlay must be a number (yoffset) │ │ + [ c677] Function celestia:setaudioloop requires two arguments │ │ + [ c6ad] Third argument to celestia:loadtexture must be a string │ │ + [ c6e5] WARNING:\n │ │ This script requests permission to read/write files\n │ │ and execute external programs. Allowing this can be\n │ │ dangerous.\n │ │ Do you trust the script and want to allow this? │ │ - [ c765] BLEND │ │ - [ c76b] NEAREST │ │ - [ c773] argument 5 to gl.Frustum must be a number │ │ - [ c79d] argument 1 to gl.TexCoord must be a number │ │ - [ c7c8] No arguments expected for image:getheight() │ │ - [ c7f4] setorbitcolor │ │ - [ c802] spectraltype │ │ - [ c80f] No arguments allowed for object:bodyfixedframe │ │ - [ c83e] One or no arguments allowed for to object:orbitframe │ │ - [ c873] gettrackedobject │ │ - [ c884] Argument to observer:setorientation must be a rotation │ │ - [ c8bb] No arguments expected to observer:gettime │ │ - [ c8e5] __sub │ │ - [ c8eb] second argument to rotation:slerp must be a number │ │ - [ c91e] Error opening LuaHook {} │ │ - [ c937] .lua │ │ - [ c93c] color0 │ │ - [ c943] texcoord3 │ │ - [ c94d] specular {} {} {}\n │ │ - [ c960] {} │ │ - [ c964] neptune-sun │ │ - [ c970] enceladus │ │ - [ c97a] jpl-saturn-sun │ │ - [ c989] pluto │ │ - [ c98f] jpl-mercury-sun │ │ - [ c99f] Error reading sample file {}.\n │ │ - [ c9be] Cannot load ScriptedOrbit package: 'require' function is unavailable\n │ │ - [ ca04] Error calling ScriptedRotation generator function: {}\n │ │ - [ ca3b] in_Size │ │ - [ ca43] Empty or single-element chain found in asterism "{}"\n │ │ - [ ca79] XXX │ │ - [ ca7d] Col │ │ - [ ca81] Visible │ │ - [ ca89] GL_EXT_texture_border_clamp │ │ - [ caa5] Error compiling fragment shader:\n │ │ - [ cac7] CH │ │ - [ caca] AS │ │ - [ cacd] Landing Site │ │ - [ cada] OC │ │ - [ cadd] Invalid filename in SampledOrientation\n │ │ - [ cb05] Beginning │ │ - [ cb0f] ArgOfPericenter │ │ - [ cb1f] MeanAnomaly │ │ - [ cb2b] Planetographic │ │ - [ cb3a] Kernel list for SPICE rotation is neither a string nor array of strings\n │ │ - [ cb83] Tilt │ │ - [ cb88] mE │ │ - [ cb8b] ringPlane │ │ - [ cb95] ringShadowTexCoord │ │ - [ cba8] vec2 shadowCenter;\n │ │ - [ cbbc] NL = dot( │ │ - [ cbc6] gl_FragColor = color * diff + texture2D(specTex, │ │ - [ cbf8] float cosTheta = dot(V, │ │ - [ cc15] gl_FragColor = vec4(color, dot(scatterEx, vec3(0.333)));\n │ │ - [ cc53] mieH │ │ - [ cc58] in_PositionNext │ │ - [ cc68] {}{}_{} │ │ - [ cc71] float calculateShadow()\n │ │ + [ c792] BLEND │ │ + [ c798] NEAREST │ │ + [ c7a0] argument 5 to gl.Frustum must be a number │ │ + [ c7ca] argument 1 to gl.TexCoord must be a number │ │ + [ c7f5] No arguments expected for image:getheight() │ │ + [ c821] setorbitcolor │ │ + [ c82f] spectraltype │ │ + [ c83c] No arguments allowed for object:bodyfixedframe │ │ + [ c86b] One or no arguments allowed for to object:orbitframe │ │ + [ c8a0] gettrackedobject │ │ + [ c8b1] Argument to observer:setorientation must be a rotation │ │ + [ c8e8] No arguments expected to observer:gettime │ │ + [ c912] __sub │ │ + [ c918] second argument to rotation:slerp must be a number │ │ + [ c94b] Error opening LuaHook {} │ │ + [ c964] .lua │ │ + [ c969] color0 │ │ + [ c970] texcoord3 │ │ + [ c97a] specular {} {} {}\n │ │ + [ c98d] {} │ │ + [ c991] neptune-sun │ │ + [ c99d] enceladus │ │ + [ c9a7] jpl-saturn-sun │ │ + [ c9b6] pluto │ │ + [ c9bc] jpl-mercury-sun │ │ + [ c9cc] Error reading sample file {}.\n │ │ + [ c9eb] Cannot load ScriptedOrbit package: 'require' function is unavailable\n │ │ + [ ca31] Error calling ScriptedRotation generator function: {}\n │ │ + [ ca68] in_Size │ │ + [ ca70] Empty or single-element chain found in asterism "{}"\n │ │ + [ caa6] XXX │ │ + [ caaa] Col │ │ + [ caae] Visible │ │ + [ cab6] GL_EXT_texture_border_clamp │ │ + [ cad2] Error compiling fragment shader:\n │ │ + [ caf4] CH │ │ + [ caf7] AS │ │ + [ cafa] Landing Site │ │ + [ cb07] OC │ │ + [ cb0a] Invalid filename in SampledOrientation\n │ │ + [ cb32] Beginning │ │ + [ cb3c] ArgOfPericenter │ │ + [ cb4c] MeanAnomaly │ │ + [ cb58] Planetographic │ │ + [ cb67] Kernel list for SPICE rotation is neither a string nor array of strings\n │ │ + [ cbb0] Tilt │ │ + [ cbb5] mE │ │ + [ cbb8] ringPlane │ │ + [ cbc2] ringShadowTexCoord │ │ + [ cbd5] vec2 shadowCenter;\n │ │ + [ cbe9] NL = dot( │ │ + [ cbf3] gl_FragColor = color * diff + texture2D(specTex, │ │ + [ cc25] float cosTheta = dot(V, │ │ + [ cc42] gl_FragColor = vec4(color, dot(scatterEx, vec3(0.333)));\n │ │ + [ cc80] mieH │ │ + [ cc85] in_PositionNext │ │ + [ cc95] {}{}_{} │ │ + [ cc9e] float calculateShadow()\n │ │ {\n │ │ float texelSize = 1.0 / shadowMapSize;\n │ │ float s = 0.0;\n │ │ float bias = max(0.005 * (1.0 - cosNormalLightDir), 0.0005);\n │ │ for(float x = -1.0; x <= 1.0; x += 1.0)\n │ │ {\n │ │ for(float y = -1.0; y <= 1.0; y += 1.0)\n │ │ {\n │ │ float pcfDepth = texture2D(shadowMapTex0, shadowTexCoord0.xy + vec2(x * texelSize, y * texelSize)).r;\n │ │ s += shadowTexCoord0.z - bias > pcfDepth ? 1.0 : 0.0;\n │ │ }\n │ │ }\n │ │ return 1.0 - s / 9.0;\n │ │ }\n │ │ - [ ce57] totalLight = 1.0 - totalLight;\n │ │ + [ ce84] totalLight = 1.0 - totalLight;\n │ │ totalLight = totalLight * totalLight * totalLight * totalLight;\n │ │ - [ ceb7] Error in timeline of '{}': phase {} is not a property group.\n │ │ - [ cef5] Loading image from file {}\n │ │ - [ cf11] Read3DSFile: Error reading 3DS file top level chunk size\n │ │ - [ cf4b] Failed to read entry {} of smoothing group array\n │ │ - [ cf7d] Processing MaterialTexmap chunk\n │ │ - [ cf9e] {"bytes":[ │ │ - [ cfa9] : 0x │ │ - [ cfae] libGLESv1_CM.so │ │ - [ cfbe] Requested feature was omitted at compile time │ │ - [ cfec] Seek failed on temporary file │ │ - [ d00a] Start of Image │ │ - [ d019] OpticalSize │ │ - [ d025] CDV │ │ - [ d029] BlendDesignPositions │ │ - [ d03e] BlendDesignMap │ │ - [ d051] KP │ │ - [ d054] W0Y │ │ - [ d058] constants │ │ - [ d062] seeall │ │ - [ d069] / │ │ - [ d06b] Unknown compression method in IHDR │ │ - [ d08e] h: │ │ - [ d092] sCAL width │ │ - [ d09d] png_read_update_info/png_start_read_image: duplicate call │ │ - [ d0d7] png_image_begin_read_from_stdio: incorrect PNG_IMAGE_VERSION │ │ - [ d114] png_image_finish_read: row_stride too large │ │ - [ d140] rgb[ga] color-map: too few entries │ │ - [ d163] Invalid pCAL parameter count │ │ - [ d180] tRNS chunk has out-of-range samples for bit_depth │ │ - [ d1b2] unknown chunk: out of memory │ │ - [ d1cf] Compression buffer size cannot be changed because it is in use │ │ - [ d20e] Call to NULL write function │ │ - [ d22a] Wrote palette index exceeding num_palette │ │ - [ d254] Invalid image color type specified │ │ - [ d277] Invalid number of transparent colors specified │ │ - [ d2a6] zTXt: invalid keyword │ │ - [ d2bc] iTXt: invalid keyword │ │ - [ d2d2] SPICE(INVALIDOPERATION) │ │ - [ d2ea] ERRACT │ │ - [ d2f1] Window Does Not Have an Even Number of Endpoints │ │ - [ d322] Number of path symbols is #; number of path values is #; counts must match. │ │ - [ d36e] UNLOAD │ │ - [ d375] The file type contains nonprinting characters. │ │ - [ d3a4] formatted io not allowed │ │ - [ d3bd] An excess of │ │ - [ d3ca] daffa_ │ │ - [ d3d1] stthis │ │ - [ d3d8] No array is current; the `next' array is the first array of DAF # │ │ - [ d41a] ekqmgr_ │ │ - [ d422] tbstpt │ │ - [ d429] stnrow │ │ - [ d430] rsize │ │ - [ d436] DAS │ │ - [ d43a] dirrec │ │ - [ d441] There is no DAS file open with handle = # │ │ - [ d46b] DASWRC │ │ - [ d472] ktotal_c │ │ - [ d47b] Node # cannot be found by forward traversal, starting at node #. │ │ - [ d4bc] PREV was #. LIST was #. Valid range is 1 to #. │ │ - [ d4ec] LNKINI │ │ - [ d4f3] The internal file table is already full, with # entries. │ │ - [ d52c] PCKSFS │ │ - [ d533] The value associated with index # of the kernel variable # is outside the range of integers. The value stored was: # . │ │ - [ d5aa] resnum │ │ - [ d5b1] FRINFO │ │ - [ d5b8] _CLASS │ │ - [ d5bf] MILLION │ │ - [ d5c7] sclks │ │ - [ d5cd] CK_ │ │ - [ d5d1] Window size in type 05 segment was #; max allowed value is # for subtypes 1 and 3 (Lagrange, 4 or 7-element packets). │ │ - [ d647] SEPOOL │ │ - [ d64e] SPICE(INDEXTOOLARGE) │ │ - [ d663] meta │ │ - [ d668] ASC │ │ - [ d66c] Insufficient ephemeris data has been loaded to compute the state of TARG relative to OBS at the ephemeris epoch #. │ │ - [ d6e0] v2 │ │ - [ d6e3] SPKE19 │ │ - [ d6ea] prop2b_ │ │ - [ d6f2] SPKE03 │ │ - [ d6f9] SPKR21 │ │ - [ d700] PCKE20 │ │ - [ d707] The data array associated with variable # has dimension #, which is larger than the available space # in the output array. │ │ - [ d782] TKFRAM │ │ - [ d789] SPICE(INCOMPLETEFRAME) │ │ - [ d7a0] Frame name-based and frame ID-based text kernel (fixed-offset) frame definition keywords '#' and '#' are both present in the POOL. Most likely this is because loaded text kernels contain competing definitions of the '#' frame using different keyword styles, which is not allowed. │ │ - [ d8b9] MATRIX │ │ - [ d8c0] TRCPKG: You have called an entry that performs no run-time function. │ │ - [ d906] trcpkg_ │ │ - [ d90e] left off │ │ - [ d917] ZZBODGET │ │ - [ d920] SPICE(UNSUPPORTEDMETHOD) │ │ - [ d939] INQUIRE failed. │ │ - [ d949] SPICE(RWCONFLICT) │ │ - [ d95b] HANDLE # was not found in the file table but was located in the unit table. This error should never occur. │ │ - [ d9c7] orderv │ │ - [ d9ce] Attempt to remove row # from the unit table failed because valid row indices range from 1 to NUT. │ │ - [ da30] Size of d.p. component of segment is #; cannot extract descriptor. This is a file format error which may be indicative of a corrupted file. │ │ - [ dabd] OBSERVER │ │ - [ dac6] UNITS │ │ - [ dacc] RECTANGULAR │ │ - [ dad8] copy │ │ - [ dadd] ZZEKJSRT │ │ - [ dae6] rhans │ │ - [ daec] ZZEKILLE │ │ - [ daf5] ZZEKLLEI │ │ - [ dafe] SPICE(UNPARSEDQUERY) │ │ - [ db13] DASADD │ │ - [ db1a] ZZEKRD08 │ │ - [ db23] ZZEKRD04 │ │ - [ db2c] ZZEKMLOC │ │ - [ db35] Key #; valid range = 1:#. Tree = #, file = #. Key was not found. This probably indicates a corrupted file or a bug in the EK code. │ │ - [ dbba] An attempt to create a temporary string failed. │ │ - [ dbea] Attempt to allocate string of length # failed. │ │ - [ dc19] IAU_EUROPA │ │ - [ dc24] IAU_CALYPSO │ │ - [ dc30] IAU_KALYKE │ │ - [ dc3b] ZZGFTREB │ │ - [ dc44] HASH SIZE │ │ - [ dc4e] NEPTUNE BARYCENTER │ │ - [ dc61] EURYDOME │ │ - [ dc6a] PROMETHEUS │ │ - [ dc75] BERGELMIR │ │ - [ dc7f] PERDITA │ │ - [ dc87] IMAP │ │ - [ dc8c] VSOP │ │ - [ dc91] MCOB │ │ - [ dc96] MGS SIMULATION │ │ - [ dca5] PERSEVERANCE │ │ - [ dcb2] SOIL MOISTURE ACTIVE AND PASSIVE │ │ - [ dcd3] MER-2 │ │ - [ dcd9] ASHBROOK-JACKSON │ │ - [ dcea] DE VICO-SWIFT │ │ - [ dcf8] KOWAL 2 │ │ - [ dd00] TEMPEL-TUTTLE │ │ - [ dd0e] PARKER-HARTLEY │ │ - [ dd1d] 1992KD │ │ - [ dd24] GOLDSTONE │ │ - [ dd2e] DSS-42 │ │ - [ dd35] The ZZHASH function calculated a negative value for string $1. Contact NAIF. │ │ - [ dd82] SYSTEM │ │ - [ dd89] O/S │ │ - [ dd8d] zzrvar_ │ │ - [ dd95] A kernel pool variable name read from a kernel file exceeds the maximum allowed length #1. The actual length of the variable name is #2, the offending variable name to #3 characters: '#4'. │ │ - [ de52] SPICE(BADTIMESPEC) │ │ - [ de65] [e] │ │ - [ de69] H*M*S │ │ - [ de6f] DAYSEC │ │ - [ de77] JDTDT │ │ - [ de7e] The FROM time representation '#' is not recognized. │ │ - [ deb3] Cosine of the aberration angle is 0; this cannot occur for realistic observer velocities. This case can arise due to uninitialized inputs. This cosine value is used as a divisor in a later computation, so it must not be equal to zero. │ │ - [ df9e] stops │ │ - [ dfa4] ZZSWFFET │ │ - [ dfad] SPICE(MISSINGFRAMEVAR) │ │ - [ dfc4] The requested frame # has # associated base frames. The maximum number that can be supported is #. │ │ - [ e027] SPICE(UNPARSEDTIME) │ │ - [ e03b] comma │ │ - [ e041] DOY │ │ - [ e045] lx4uns_ │ │ - [ e04d] Y*m*D* │ │ - [ e054] YDmH │ │ - [ e059] Ynm │ │ - [ e05d] iYdi:i:i │ │ - [ e066] iiYi:i │ │ - [ e06d] imii │ │ - [ e072] miY │ │ - [ e076] mDYHM │ │ - [ e07c] Y*y** │ │ - [ e082] DE │ │ - [ e085] jw │ │ - [ e088] aeb │ │ - [ e08c] ase │ │ - [ e090] bqi │ │ - [ e094] ca │ │ - [ e097] ff │ │ - [ e09a] fi │ │ - [ e09d] ia │ │ - [ e0a0] jmc │ │ - [ e0a4] kiu │ │ - [ e0a8] lui │ │ - [ e0ac] naq │ │ - [ e0b0] nso │ │ - [ e0b4] pcd │ │ - [ e0b8] sad │ │ - [ e0bc] saz │ │ - [ e0c0] mlt │ │ - [ e0c4] LY │ │ - [ e0c7] MS │ │ - [ e0ca] NP │ │ - [ e0cd] CPV │ │ - [ e0d1] JPN │ │ - [ e0d5] KEN │ │ - [ e0d9] MAR │ │ - [ e0dd] uprv_ebcdicFromAscii() string[%d] contains a variant character in position %d\n │ │ - [ e12c] si_LK │ │ - [ e132] subdivision │ │ - [ e13e] Asia/Hovd │ │ - [ e148] Brazil/East │ │ - [ e154] AKDT │ │ - [ e159] ar_AE │ │ - [ e15f] en_ZA │ │ - [ e165] bs_Cyrl │ │ - [ e16d] sr_Latn_BA │ │ - [ e178] dsb_DE │ │ - [ e17f] quz_EC │ │ - [ e186] i-tsu │ │ - [ e18c] en-x-i-default │ │ - [ e19b] sfs │ │ - [ e19f] LOCALE │ │ - [ e1a6] Latn │ │ - [ e1ab] ucnv_openPackage │ │ - [ e1bc] chinese │ │ - [ e1c4] dangi │ │ - [ e1ca] day-standalone-except-narrow │ │ - [ e1e7] month-narrow │ │ - [ e1f4] coptic │ │ - [ e1fb] M11 │ │ - [ e1ff] nfkc │ │ - [ e204] udict_swap(): too few bytes (%d after header) for dictionary data\n │ │ - [ e247] U_MALFORMED_VARIABLE_REFERENCE │ │ - [ e266] U_UNDEFINED_SEGMENT_REFERENCE │ │ - [ e284] U_REGEX_RULE_SYNTAX │ │ - [ e298] AZN │ │ - [ e29c] GBP │ │ - [ e2a0] GQE │ │ - [ e2a4] MDL │ │ - [ e2a8] MRU │ │ - [ e2ac] MVP │ │ - [ e2b0] MZN │ │ - [ e2b4] SDD │ │ - [ e2b8] ZWL │ │ - [ e2bc] currencyFormat │ │ - [ e2cb] Conversion syntax │ │ - [ e2dd] Clamped │ │ - [ e2e5] No status │ │ - [ e2ef] force │ │ - [ e2f5] graphics │ │ - [ e2fe] arc-second │ │ - [ e309] square-kilometer │ │ - [ e31a] pixel-per-centimeter │ │ - [ e32f] astronomical-unit │ │ - [ e341] ounce-troy │ │ - [ e34c] dessert-spoon │ │ - [ e35a] instrumental │ │ - [ e367] one │ │ - [ e36b] pluralRanges │ │ - [ e378] pow2- │ │ - [ e37e] convertUnits │ │ - [ e38b] femto │ │ - [ e391] yocto │ │ - [ e397] per │ │ - [ e39b] Sequence │ │ - [ e3a4] CollationBuilder initialization failed │ │ - [ e3cb] reset primary-before [first trailing] not supported │ │ - [ e3ff] range without start in starred-relation string │ │ - [ e42e] string contains an unpaired surrogate │ │ - [ e454] not a valid UnicodeSet pattern │ │ - [ e473] unitPreferenceData │ │ - [ e486] sho_to_m3 │ │ - [ e490] Unable to write to %s file. │ │ - [ e4ac] Using internal %s class from dex bytes. │ │ - [ e4d4] static void swappy::SwappyGL::resetFramePacing() │ │ - [ e505] void swappy::SwappyCommon::onChoreographer(int64_t) │ │ - [ e539] android/os/Build$VERSION │ │ - [ e552] SDK_INT │ │ - [ e55a] eglCreateSyncKHR │ │ - [ e56b] eglDestroySyncKHR │ │ - [ e57e] Unable to render viewport effect.\n │ │ - [ e5a1] kelvin │ │ - [ e5a8] number is too big │ │ - [ e5ba] ProjectionMode │ │ - [ e5c9] SAOCrossIndex │ │ - [ e5d7] ReverseMouseWheel │ │ - [ e5e9] AntialiasingSamples │ │ - [ e5fd] IgnoreGLExtensions │ │ - [ e610] WO │ │ - [ e614] angle │ │ - [ e61c] Edit Mode │ │ - [ e626] LockTo │ │ - [ e62d] Star system barycenter\n │ │ - [ e645] days │ │ - [ e64a] Playback Device │ │ - [ e65a] Invalid argument │ │ - [ e66b] Connection reset │ │ - [ e67c] AAudioStreamBuilder_setContentType │ │ - [ e69f] LIST │ │ - [ e6a4] &tsrc= │ │ - [ e6ab] May │ │ - [ e6af] June │ │ - [ e6b4] lightgrey │ │ - [ e6be] olivedrab │ │ - [ e6c8] skyblue │ │ - [ e6d3] globulars │ │ - [ e6dd] grid │ │ - [ e6e2] mare │ │ - [ e6e7] loop │ │ - [ e6ec] haschild │ │ - [ e6f5] Argument of category:createchild must be a string! │ │ - [ e728] flash │ │ - [ e72e] getscreendimension │ │ - [ e741] tdbtoutc │ │ - [ e74a] One argument expected for celestia:getlinecolor() │ │ - [ e77c] One argument expected for celestia:setminfeaturesize() │ │ - [ e7b3] Argument to celestia:setminorbitsize() must be a number │ │ - [ e7eb] enhanced │ │ - [ e7f4] newrotation: first argument must be a vector │ │ - [ e821] Need 0 to 2 arguments for celestia:takescreenshot │ │ - [ e853] Two arguments required for celestia:registereventhandler │ │ - [ e88c] Second argument to celestia:playaudio must be a string │ │ - [ e8c3] One argument required for celestia:settimeslice() │ │ - [ e8f5] In line {}: {} │ │ - [ e904] Internal Error: Invalid table entry for LuaState-pointer │ │ - [ e93d] class_frame │ │ - [ e949] class_font │ │ - [ e954] class_category │ │ - [ e963] Internal Error: Invalid value in checkTimeslice │ │ - [ e993] from │ │ - [ e998] getrefobject │ │ - [ e9a5] Enable │ │ - [ e9ac] argument 1 to gl.Color must be a number │ │ - [ e9d4] getwidth │ │ - [ e9dd] getheight │ │ - [ e9e7] [Celscript] │ │ - [ e9f3] No arguments expected for font:getmaxdescent() │ │ - [ ea22] No arguments expected to function object:radius │ │ - [ ea52] unknown │ │ - [ ea5a] rotationPeriod │ │ - [ ea69] geomAlbedo │ │ - [ ea74] oblateness │ │ - [ ea7f] Second argument to object:mark must be a string │ │ - [ eaaf] lowercolor │ │ - [ eaba] [Observer] │ │ - [ eac5] One to five arguments expected to observer:gotolonglat │ │ - [ eafc] First argument to observer:synchronous must be an object │ │ - [ eb35] slerp │ │ - [ eb3b] add │ │ - [ eb3f] jpl-pluto-sun │ │ - [ eb4d] oberon │ │ - [ eb54] jpl-saturn-ssb │ │ - [ eb63] Ephemeris record size: {} doubles, with {} endianess.\n │ │ - [ eb9a] Error finding data in ASCII sample file {}.\n │ │ - [ ebc7] Error parsing asterism file: expected string\n │ │ - [ ebf5] Cir │ │ - [ ebf9] CrB │ │ - [ ebfd] Tri │ │ - [ ec01] Vol │ │ - [ ec05] Sb │ │ - [ ec08] v │ │ - [ ec0a] Unknown object passed to GetInfoLog()!\n │ │ - [ ec32] AR │ │ - [ ec35] Period │ │ - [ ec3c] RGBA{}{}{}{} │ │ - [ ec49] ringRadius │ │ - [ ec54] overlayTexCoord = │ │ - [ ec67] eyePosition │ │ - [ ec73] vec3 N = normalize(normal);\n │ │ - [ ec90] vec3 eyeDir = normalize(eyePosition - nposition);\n │ │ - [ ecc3] intensity │ │ - [ eccd] shadow = 1.0;\n │ │ - [ ecdc] ;\n │ │ - [ ece0] scatterCoeffSum │ │ - [ ecf1] attribute vec4 in_Position;\n\n │ │ + [ cee4] Error in timeline of '{}': phase {} is not a property group.\n │ │ + [ cf22] Loading image from file {}\n │ │ + [ cf3e] Read3DSFile: Error reading 3DS file top level chunk size\n │ │ + [ cf78] Failed to read entry {} of smoothing group array\n │ │ + [ cfaa] Processing MaterialTexmap chunk\n │ │ + [ cfcb] {"bytes":[ │ │ + [ cfd6] : 0x │ │ + [ cfdb] libGLESv1_CM.so │ │ + [ cfeb] Requested feature was omitted at compile time │ │ + [ d019] Seek failed on temporary file │ │ + [ d037] Start of Image │ │ + [ d046] OpticalSize │ │ + [ d052] CDV │ │ + [ d056] BlendDesignPositions │ │ + [ d06b] BlendDesignMap │ │ + [ d07e] KP │ │ + [ d081] W0Y │ │ + [ d085] constants │ │ + [ d08f] seeall │ │ + [ d096] / │ │ + [ d098] Unknown compression method in IHDR │ │ + [ d0bb] h: │ │ + [ d0bf] sCAL width │ │ + [ d0ca] png_read_update_info/png_start_read_image: duplicate call │ │ + [ d104] png_image_begin_read_from_stdio: incorrect PNG_IMAGE_VERSION │ │ + [ d141] png_image_finish_read: row_stride too large │ │ + [ d16d] rgb[ga] color-map: too few entries │ │ + [ d190] Invalid pCAL parameter count │ │ + [ d1ad] tRNS chunk has out-of-range samples for bit_depth │ │ + [ d1df] unknown chunk: out of memory │ │ + [ d1fc] Compression buffer size cannot be changed because it is in use │ │ + [ d23b] Call to NULL write function │ │ + [ d257] Wrote palette index exceeding num_palette │ │ + [ d281] Invalid image color type specified │ │ + [ d2a4] Invalid number of transparent colors specified │ │ + [ d2d3] zTXt: invalid keyword │ │ + [ d2e9] iTXt: invalid keyword │ │ + [ d2ff] SPICE(INVALIDOPERATION) │ │ + [ d317] ERRACT │ │ + [ d31e] Window Does Not Have an Even Number of Endpoints │ │ + [ d34f] Number of path symbols is #; number of path values is #; counts must match. │ │ + [ d39b] UNLOAD │ │ + [ d3a2] The file type contains nonprinting characters. │ │ + [ d3d1] formatted io not allowed │ │ + [ d3ea] An excess of │ │ + [ d3f7] daffa_ │ │ + [ d3fe] stthis │ │ + [ d405] No array is current; the `next' array is the first array of DAF # │ │ + [ d447] ekqmgr_ │ │ + [ d44f] tbstpt │ │ + [ d456] stnrow │ │ + [ d45d] rsize │ │ + [ d463] DAS │ │ + [ d467] dirrec │ │ + [ d46e] There is no DAS file open with handle = # │ │ + [ d498] DASWRC │ │ + [ d49f] ktotal_c │ │ + [ d4a8] Node # cannot be found by forward traversal, starting at node #. │ │ + [ d4e9] PREV was #. LIST was #. Valid range is 1 to #. │ │ + [ d519] LNKINI │ │ + [ d520] The internal file table is already full, with # entries. │ │ + [ d559] PCKSFS │ │ + [ d560] The value associated with index # of the kernel variable # is outside the range of integers. The value stored was: # . │ │ + [ d5d7] resnum │ │ + [ d5de] FRINFO │ │ + [ d5e5] _CLASS │ │ + [ d5ec] MILLION │ │ + [ d5f4] sclks │ │ + [ d5fa] CK_ │ │ + [ d5fe] Window size in type 05 segment was #; max allowed value is # for subtypes 1 and 3 (Lagrange, 4 or 7-element packets). │ │ + [ d674] SEPOOL │ │ + [ d67b] SPICE(INDEXTOOLARGE) │ │ + [ d690] meta │ │ + [ d695] ASC │ │ + [ d699] Insufficient ephemeris data has been loaded to compute the state of TARG relative to OBS at the ephemeris epoch #. │ │ + [ d70d] v2 │ │ + [ d710] SPKE19 │ │ + [ d717] prop2b_ │ │ + [ d71f] SPKE03 │ │ + [ d726] SPKR21 │ │ + [ d72d] PCKE20 │ │ + [ d734] The data array associated with variable # has dimension #, which is larger than the available space # in the output array. │ │ + [ d7af] TKFRAM │ │ + [ d7b6] SPICE(INCOMPLETEFRAME) │ │ + [ d7cd] Frame name-based and frame ID-based text kernel (fixed-offset) frame definition keywords '#' and '#' are both present in the POOL. Most likely this is because loaded text kernels contain competing definitions of the '#' frame using different keyword styles, which is not allowed. │ │ + [ d8e6] MATRIX │ │ + [ d8ed] TRCPKG: You have called an entry that performs no run-time function. │ │ + [ d933] trcpkg_ │ │ + [ d93b] left off │ │ + [ d944] ZZBODGET │ │ + [ d94d] SPICE(UNSUPPORTEDMETHOD) │ │ + [ d966] INQUIRE failed. │ │ + [ d976] SPICE(RWCONFLICT) │ │ + [ d988] HANDLE # was not found in the file table but was located in the unit table. This error should never occur. │ │ + [ d9f4] orderv │ │ + [ d9fb] Attempt to remove row # from the unit table failed because valid row indices range from 1 to NUT. │ │ + [ da5d] Size of d.p. component of segment is #; cannot extract descriptor. This is a file format error which may be indicative of a corrupted file. │ │ + [ daea] OBSERVER │ │ + [ daf3] UNITS │ │ + [ daf9] RECTANGULAR │ │ + [ db05] copy │ │ + [ db0a] ZZEKJSRT │ │ + [ db13] rhans │ │ + [ db19] ZZEKILLE │ │ + [ db22] ZZEKLLEI │ │ + [ db2b] SPICE(UNPARSEDQUERY) │ │ + [ db40] DASADD │ │ + [ db47] ZZEKRD08 │ │ + [ db50] ZZEKRD04 │ │ + [ db59] ZZEKMLOC │ │ + [ db62] Key #; valid range = 1:#. Tree = #, file = #. Key was not found. This probably indicates a corrupted file or a bug in the EK code. │ │ + [ dbe7] An attempt to create a temporary string failed. │ │ + [ dc17] Attempt to allocate string of length # failed. │ │ + [ dc46] IAU_EUROPA │ │ + [ dc51] IAU_CALYPSO │ │ + [ dc5d] IAU_KALYKE │ │ + [ dc68] ZZGFTREB │ │ + [ dc71] HASH SIZE │ │ + [ dc7b] NEPTUNE BARYCENTER │ │ + [ dc8e] EURYDOME │ │ + [ dc97] PROMETHEUS │ │ + [ dca2] BERGELMIR │ │ + [ dcac] PERDITA │ │ + [ dcb4] IMAP │ │ + [ dcb9] VSOP │ │ + [ dcbe] MCOB │ │ + [ dcc3] MGS SIMULATION │ │ + [ dcd2] PERSEVERANCE │ │ + [ dcdf] SOIL MOISTURE ACTIVE AND PASSIVE │ │ + [ dd00] MER-2 │ │ + [ dd06] ASHBROOK-JACKSON │ │ + [ dd17] DE VICO-SWIFT │ │ + [ dd25] KOWAL 2 │ │ + [ dd2d] TEMPEL-TUTTLE │ │ + [ dd3b] PARKER-HARTLEY │ │ + [ dd4a] 1992KD │ │ + [ dd51] GOLDSTONE │ │ + [ dd5b] DSS-42 │ │ + [ dd62] The ZZHASH function calculated a negative value for string $1. Contact NAIF. │ │ + [ ddaf] SYSTEM │ │ + [ ddb6] O/S │ │ + [ ddba] zzrvar_ │ │ + [ ddc2] A kernel pool variable name read from a kernel file exceeds the maximum allowed length #1. The actual length of the variable name is #2, the offending variable name to #3 characters: '#4'. │ │ + [ de7f] SPICE(BADTIMESPEC) │ │ + [ de92] [e] │ │ + [ de96] H*M*S │ │ + [ de9c] DAYSEC │ │ + [ dea4] JDTDT │ │ + [ deab] The FROM time representation '#' is not recognized. │ │ + [ dee0] Cosine of the aberration angle is 0; this cannot occur for realistic observer velocities. This case can arise due to uninitialized inputs. This cosine value is used as a divisor in a later computation, so it must not be equal to zero. │ │ + [ dfcb] stops │ │ + [ dfd1] ZZSWFFET │ │ + [ dfda] SPICE(MISSINGFRAMEVAR) │ │ + [ dff1] The requested frame # has # associated base frames. The maximum number that can be supported is #. │ │ + [ e054] SPICE(UNPARSEDTIME) │ │ + [ e068] comma │ │ + [ e06e] DOY │ │ + [ e072] lx4uns_ │ │ + [ e07a] Y*m*D* │ │ + [ e081] YDmH │ │ + [ e086] Ynm │ │ + [ e08a] iYdi:i:i │ │ + [ e093] iiYi:i │ │ + [ e09a] imii │ │ + [ e09f] miY │ │ + [ e0a3] mDYHM │ │ + [ e0a9] Y*y** │ │ + [ e0af] DE │ │ + [ e0b2] jw │ │ + [ e0b5] aeb │ │ + [ e0b9] ase │ │ + [ e0bd] bqi │ │ + [ e0c1] ca │ │ + [ e0c4] ff │ │ + [ e0c7] fi │ │ + [ e0ca] ia │ │ + [ e0cd] jmc │ │ + [ e0d1] kiu │ │ + [ e0d5] lui │ │ + [ e0d9] naq │ │ + [ e0dd] nso │ │ + [ e0e1] pcd │ │ + [ e0e5] sad │ │ + [ e0e9] saz │ │ + [ e0ed] mlt │ │ + [ e0f1] LY │ │ + [ e0f4] MS │ │ + [ e0f7] NP │ │ + [ e0fa] CPV │ │ + [ e0fe] JPN │ │ + [ e102] KEN │ │ + [ e106] MAR │ │ + [ e10a] uprv_ebcdicFromAscii() string[%d] contains a variant character in position %d\n │ │ + [ e159] si_LK │ │ + [ e15f] subdivision │ │ + [ e16b] Asia/Hovd │ │ + [ e175] Brazil/East │ │ + [ e181] AKDT │ │ + [ e186] ar_AE │ │ + [ e18c] en_ZA │ │ + [ e192] bs_Cyrl │ │ + [ e19a] sr_Latn_BA │ │ + [ e1a5] dsb_DE │ │ + [ e1ac] quz_EC │ │ + [ e1b3] i-tsu │ │ + [ e1b9] en-x-i-default │ │ + [ e1c8] sfs │ │ + [ e1cc] LOCALE │ │ + [ e1d3] Latn │ │ + [ e1d8] ucnv_openPackage │ │ + [ e1e9] chinese │ │ + [ e1f1] dangi │ │ + [ e1f7] day-standalone-except-narrow │ │ + [ e214] month-narrow │ │ + [ e221] coptic │ │ + [ e228] M11 │ │ + [ e22c] nfkc │ │ + [ e231] udict_swap(): too few bytes (%d after header) for dictionary data\n │ │ + [ e274] U_MALFORMED_VARIABLE_REFERENCE │ │ + [ e293] U_UNDEFINED_SEGMENT_REFERENCE │ │ + [ e2b1] U_REGEX_RULE_SYNTAX │ │ + [ e2c5] AZN │ │ + [ e2c9] GBP │ │ + [ e2cd] GQE │ │ + [ e2d1] MDL │ │ + [ e2d5] MRU │ │ + [ e2d9] MVP │ │ + [ e2dd] MZN │ │ + [ e2e1] SDD │ │ + [ e2e5] ZWL │ │ + [ e2e9] currencyFormat │ │ + [ e2f8] Conversion syntax │ │ + [ e30a] Clamped │ │ + [ e312] No status │ │ + [ e31c] force │ │ + [ e322] graphics │ │ + [ e32b] arc-second │ │ + [ e336] square-kilometer │ │ + [ e347] pixel-per-centimeter │ │ + [ e35c] astronomical-unit │ │ + [ e36e] ounce-troy │ │ + [ e379] dessert-spoon │ │ + [ e387] instrumental │ │ + [ e394] one │ │ + [ e398] pluralRanges │ │ + [ e3a5] pow2- │ │ + [ e3ab] convertUnits │ │ + [ e3b8] femto │ │ + [ e3be] yocto │ │ + [ e3c4] per │ │ + [ e3c8] Sequence │ │ + [ e3d1] CollationBuilder initialization failed │ │ + [ e3f8] reset primary-before [first trailing] not supported │ │ + [ e42c] range without start in starred-relation string │ │ + [ e45b] string contains an unpaired surrogate │ │ + [ e481] not a valid UnicodeSet pattern │ │ + [ e4a0] unitPreferenceData │ │ + [ e4b3] sho_to_m3 │ │ + [ e4bd] Unable to write to %s file. │ │ + [ e4d9] Using internal %s class from dex bytes. │ │ + [ e501] static void swappy::SwappyGL::resetFramePacing() │ │ + [ e532] void swappy::SwappyCommon::onChoreographer(int64_t) │ │ + [ e566] android/os/Build$VERSION │ │ + [ e57f] SDK_INT │ │ + [ e587] eglCreateSyncKHR │ │ + [ e598] eglDestroySyncKHR │ │ + [ e5ab] Unable to render viewport effect.\n │ │ + [ e5ce] kelvin │ │ + [ e5d5] number is too big │ │ + [ e5e7] ProjectionMode │ │ + [ e5f6] SAOCrossIndex │ │ + [ e604] ReverseMouseWheel │ │ + [ e616] AntialiasingSamples │ │ + [ e62a] IgnoreGLExtensions │ │ + [ e63d] WO │ │ + [ e641] angle │ │ + [ e649] Edit Mode │ │ + [ e653] LockTo │ │ + [ e65a] Star system barycenter\n │ │ + [ e672] days │ │ + [ e677] Playback Device │ │ + [ e687] Invalid argument │ │ + [ e698] Connection reset │ │ + [ e6a9] AAudioStreamBuilder_setContentType │ │ + [ e6cc] LIST │ │ + [ e6d1] &tsrc= │ │ + [ e6d8] May │ │ + [ e6dc] June │ │ + [ e6e1] lightgrey │ │ + [ e6eb] olivedrab │ │ + [ e6f5] skyblue │ │ + [ e700] globulars │ │ + [ e70a] grid │ │ + [ e70f] mare │ │ + [ e714] loop │ │ + [ e719] haschild │ │ + [ e722] Argument of category:createchild must be a string! │ │ + [ e755] flash │ │ + [ e75b] getscreendimension │ │ + [ e76e] tdbtoutc │ │ + [ e777] One argument expected for celestia:getlinecolor() │ │ + [ e7a9] One argument expected for celestia:setminfeaturesize() │ │ + [ e7e0] Argument to celestia:setminorbitsize() must be a number │ │ + [ e818] enhanced │ │ + [ e821] newrotation: first argument must be a vector │ │ + [ e84e] Need 0 to 2 arguments for celestia:takescreenshot │ │ + [ e880] Two arguments required for celestia:registereventhandler │ │ + [ e8b9] Second argument to celestia:playaudio must be a string │ │ + [ e8f0] One argument required for celestia:settimeslice() │ │ + [ e922] In line {}: {} │ │ + [ e931] Internal Error: Invalid table entry for LuaState-pointer │ │ + [ e96a] class_frame │ │ + [ e976] class_font │ │ + [ e981] class_category │ │ + [ e990] Internal Error: Invalid value in checkTimeslice │ │ + [ e9c0] from │ │ + [ e9c5] getrefobject │ │ + [ e9d2] Enable │ │ + [ e9d9] argument 1 to gl.Color must be a number │ │ + [ ea01] getwidth │ │ + [ ea0a] getheight │ │ + [ ea14] [Celscript] │ │ + [ ea20] No arguments expected for font:getmaxdescent() │ │ + [ ea4f] No arguments expected to function object:radius │ │ + [ ea7f] unknown │ │ + [ ea87] rotationPeriod │ │ + [ ea96] geomAlbedo │ │ + [ eaa1] oblateness │ │ + [ eaac] Second argument to object:mark must be a string │ │ + [ eadc] lowercolor │ │ + [ eae7] [Observer] │ │ + [ eaf2] One to five arguments expected to observer:gotolonglat │ │ + [ eb29] First argument to observer:synchronous must be an object │ │ + [ eb62] slerp │ │ + [ eb68] add │ │ + [ eb6c] jpl-pluto-sun │ │ + [ eb7a] oberon │ │ + [ eb81] jpl-saturn-ssb │ │ + [ eb90] Ephemeris record size: {} doubles, with {} endianess.\n │ │ + [ ebc7] Error finding data in ASCII sample file {}.\n │ │ + [ ebf4] Error parsing asterism file: expected string\n │ │ + [ ec22] Cir │ │ + [ ec26] CrB │ │ + [ ec2a] Tri │ │ + [ ec2e] Vol │ │ + [ ec32] Sb │ │ + [ ec35] v │ │ + [ ec37] Unknown object passed to GetInfoLog()!\n │ │ + [ ec5f] AR │ │ + [ ec62] Period │ │ + [ ec69] RGBA{}{}{}{} │ │ + [ ec76] ringRadius │ │ + [ ec81] overlayTexCoord = │ │ + [ ec94] eyePosition │ │ + [ eca0] vec3 N = normalize(normal);\n │ │ + [ ecbd] vec3 eyeDir = normalize(eyePosition - nposition);\n │ │ + [ ecf0] intensity │ │ + [ ecfa] shadow = 1.0;\n │ │ + [ ed09] ;\n │ │ + [ ed0d] scatterCoeffSum │ │ + [ ed1e] attribute vec4 in_Position;\n\n │ │ void main(void)\n │ │ {\n │ │ gl_Position = MVPMatrix * in_Position;\n │ │ }\n │ │ - [ ed4f] uniform {} {};\n │ │ - [ ed5f] xyzw │ │ - [ ed64] pointFade = min(1.0, ptSize * ptSize);\n │ │ - [ ed8c] shadow *= 1.0 - texture2DLod(ringTex, vec2(ringShadowTexCoordX, 0.0), │ │ - [ edd3] OrbitColor │ │ - [ edde] CloudMap │ │ - [ ede7] Modify requested for nonexistent star.\n │ │ - [ ee0f] ignoring orbit for object without OrbitBarycenter │ │ - [ ee41] Warning in .stc file ({}): {}\n │ │ - [ ee60] screenRatio │ │ - [ ee6c] DDS texture file {} has bad header.\n │ │ - [ ee91] {}: unrecognized or unsupported image file type.\n │ │ - [ eec3] java/util/ArrayList │ │ - [ eed7] java/util/HashMap │ │ - [ eee9] %i.%i │ │ - [ eeef] llu │ │ - [ eef3] llX │ │ - [ eef7] LC_NUMERIC │ │ - [ ef02] plural= │ │ - [ ef0b] msgstr ""\n │ │ - [ ef16] Unsupported JPEG data precision %d │ │ - [ ef39] Invalid restart interval %d; must be an integer multiple of the number of MCUs in an MCU row (%d) │ │ - [ ef9b] JSIMD_NOHUFFENC │ │ - [ efab] StdVW │ │ - [ efb1] dup │ │ - [ efb5] UIDBase │ │ - [ efbd] DESTINATION │ │ - [ efc9] RAW_POINTSIZE │ │ - [ efd7] SUBSCRIPT_Y │ │ - [ efe3] UNDERLINE_THICKNESS │ │ - [ effb] � � │ │ - [ f009] � │ │ - [ f00e] Ascender │ │ - [ f017] StartComposites │ │ - [ f027] W0X │ │ - [ f02b] "] │ │ - [ f02e] [string] │ │ - [ f037] table.new │ │ - [ f041] cannot close standard file │ │ - [ f05c] . │ │ - [ f05e] =(debug command) │ │ - [ f070] libpng version 1.6.44\n │ │ + [ ed7c] uniform {} {};\n │ │ + [ ed8c] xyzw │ │ + [ ed91] pointFade = min(1.0, ptSize * ptSize);\n │ │ + [ edb9] shadow *= 1.0 - texture2DLod(ringTex, vec2(ringShadowTexCoordX, 0.0), │ │ + [ ee00] OrbitColor │ │ + [ ee0b] CloudMap │ │ + [ ee14] Modify requested for nonexistent star.\n │ │ + [ ee3c] ignoring orbit for object without OrbitBarycenter │ │ + [ ee6e] Warning in .stc file ({}): {}\n │ │ + [ ee8d] screenRatio │ │ + [ ee99] DDS texture file {} has bad header.\n │ │ + [ eebe] {}: unrecognized or unsupported image file type.\n │ │ + [ eef0] java/util/ArrayList │ │ + [ ef04] java/util/HashMap │ │ + [ ef16] %i.%i │ │ + [ ef1c] llu │ │ + [ ef20] llX │ │ + [ ef24] LC_NUMERIC │ │ + [ ef2f] plural= │ │ + [ ef38] msgstr ""\n │ │ + [ ef43] Unsupported JPEG data precision %d │ │ + [ ef66] Invalid restart interval %d; must be an integer multiple of the number of MCUs in an MCU row (%d) │ │ + [ efc8] JSIMD_NOHUFFENC │ │ + [ efd8] StdVW │ │ + [ efde] dup │ │ + [ efe2] UIDBase │ │ + [ efea] DESTINATION │ │ + [ eff6] RAW_POINTSIZE │ │ + [ f004] SUBSCRIPT_Y │ │ + [ f010] UNDERLINE_THICKNESS │ │ + [ f028] � � │ │ + [ f036] � │ │ + [ f03b] Ascender │ │ + [ f044] StartComposites │ │ + [ f054] W0X │ │ + [ f058] "] │ │ + [ f05b] [string] │ │ + [ f064] table.new │ │ + [ f06e] cannot close standard file │ │ + [ f089] . │ │ + [ f08b] =(debug command) │ │ + [ f09d] libpng version 1.6.44\n │ │ Copyright (c) 2018-2024 Cosmin Truta\n │ │ Copyright (c) 1998-2002,2004,2006-2018 Glenn Randers-Pehrson\n │ │ Copyright (c) 1996-1997 Andreas Dilger\n │ │ Copyright (c) 1995-1996 Guy Eric Schalnat, Group 42, Inc.\n │ │ - [ f14a] gamma value out of range │ │ - [ f163] invalid chromaticities │ │ - [ f17a] background color must be supplied to remove alpha/transparency │ │ - [ f1b9] Saving unknown chunk: │ │ - [ f1cf] cHRM Blue Y │ │ - [ f1db] png_set_gAMA │ │ - [ f1e8] Invalid palette size, hIST allocation skipped │ │ - [ f216] Insufficient memory for pCAL parameter │ │ - [ f23d] keyword "@1": bad character '0x@2' │ │ - [ f260] Only compression method 8 is supported by PNG │ │ - [ f28e] Ignoring attempt to write 16-bit tRNS chunk when bit_depth is 8 │ │ - [ f2ce] chkout_c │ │ - [ f2d7] errint_c │ │ - [ f2e0] SPICE(FILEALREADYOPEN) │ │ - [ f2f7] SPICE(FILEREADFAILED) │ │ - [ f30d] An Invalid Option Value Was Supplied │ │ - [ f332] kind │ │ - [ f337] itprvh │ │ - [ f33e] SPICE(DAFINVALIDPARAMS) │ │ - [ f356] sequential io not allowed │ │ - [ f370] external │ │ - [ f379] #1 │ │ - [ f37c] > │ │ - [ f37e] SPICE(EKNOSEGMENTS) │ │ - [ f392] DONE │ │ - [ f397] EKGI │ │ - [ f39c] The file table is full, with # entries. Could not open a scratch file. If a call to DASOPS was not made and this error occurred, it is likely that the DAS file table was full and an attempt to close a file opened with write access was made. See the DAS required reading and DASFM for details. │ │ - [ f4c1] lastla │ │ - [ f4c8] endfile │ │ - [ f4d0] The cell cannot accommodate the addition of the item *. │ │ - [ f508] DASA2L │ │ - [ f50f] rnbufi │ │ - [ f516] ' │ │ - [ f518] pxform_c │ │ - [ f521] CLASS_ID │ │ - [ f52a] The reference frame # has class #. This form of reference frame is not supported in version # of ROTGET. You need to update your version of SPICELIB to the latest version in order to support this frame. │ │ - [ f5f6] SPICE(WRONGDATATYPE) │ │ - [ f60b] pbuffr │ │ - [ f612] rotmat_ │ │ - [ f61a] SCFM01 │ │ - [ f621] SCTE01 │ │ - [ f628] FAILURE │ │ - [ f630] outmsg_ │ │ - [ f638] TOOLKIT │ │ - [ f640] Unexpected SPK type 19 subtype found in type 19 record. │ │ - [ f678] SPICE(BADLATUSRECTUM) │ │ - [ f68e] savegm │ │ - [ f695] SPICE(ECCOUTOFBOUNDS) │ │ - [ f6ab] spke08_ │ │ - [ f6b3] Request time # is outside of descriptor bounds # : #. │ │ - [ f6e9] SPICE(TIMEOUTOFBOUNDS) │ │ - [ f700] SPKR09 │ │ - [ f707] Packet count # is less than the minimum valid value, which is 2. │ │ - [ f748] Window size in type 18 segment was #; max allowed value is # for subtype 0 (Hermite, 12-element packets). │ │ - [ f7b2] Window size in type 18 segment was #; max allowed value is # for subtype 1 (Lagrange, 6-element packets). │ │ - [ f81c] BODY#_PM │ │ - [ f825] bnphco │ │ - [ f82c] The data associated with variable # are not of numeric type. │ │ - [ f869] #: The kernel pool variable '#' must be of type "NUMERIC". However, the current type is character. │ │ - [ f8ce] %+.2d │ │ - [ f8d4] dididx │ │ - [ f8db] Logical unit associated with # file $, is trying to be unlocked by routines in in the % system. │ │ - [ f93b] At least one of the kernel variables FRAME_#_# or FRAME_#_# was expected to be present in the kernel pool but neither was found. One of these variables is needed to define the reference frame #. Usually this type of problem is due to a missing keyword assignment in a frame kernel. Another, less likely, possibility is that other errors in a frame kernel have confused the frame subsystem into wrongly deciding these variables are needed. │ │ - [ faf4] In definition of frame #, the frame associated with a constant vector has frame ID code #, but no frame center, frame class, or frame class ID was found by FRINFO. This situation MAY be caused by an error in a frame kernel in which the frame is defined. The problem also could be indicative of a SPICELIB bug. │ │ - [ fc2b] QDERIV │ │ - [ fc32] SPICE(UNDEFINEDFRAME) │ │ - [ fc48] seqnce │ │ - [ fc4f] ZZDYNVAD │ │ - [ fc58] Column # should be DP or TIME but has type #. │ │ - [ fc86] ZZEKRSC │ │ - [ fc8e] PRTDEC │ │ - [ fc95] ZZEKRD02 │ │ - [ fc9e] Attempted to read uninitialized column entry. SEGNO = #; COLIDX = #; RECNO = #; EK = # │ │ - [ fcf6] ZZEKTRLK │ │ - [ fcff] Table count for first join row set was #; valid range is 1:# │ │ - [ fd3c] IAU_SINOPE │ │ - [ fd47] IAU_RHEA │ │ - [ fd50] ITRF93 │ │ - [ fd57] IAU_PATROCLUS_BARYCENTER │ │ - [ fd70] MERCURY │ │ - [ fd78] JUPITER │ │ - [ fd80] IO │ │ - [ fd83] ISONOE │ │ - [ fd8a] PRAXIDIKE │ │ - [ fd94] KALE │ │ - [ fd99] KALLICHORE │ │ - [ fda4] SATURN │ │ - [ fdab] RHEA │ │ - [ fdb0] ARIEL │ │ - [ fdb6] SETEBOS │ │ - [ fdbe] KERBEROS │ │ - [ fdc7] VENUS ORBITER │ │ - [ fdd5] JNSB │ │ - [ fdda] MSL │ │ - [ fdde] CASSINI ITL │ │ - [ fdea] DFLY │ │ - [ fdef] KOREAN PATHFINDER LUNAR ORBITER │ │ - [ fe0f] SMART1 │ │ - [ fe16] VEX │ │ - [ fe1a] BEPICOLOMBO MTM │ │ - [ fe2a] JOHNSON │ │ - [ fe32] RUSSELL 1 │ │ - [ fe3c] RUSSELL 4 │ │ - [ fe46] VESTA │ │ - [ fe4c] EURYBATES_BARYCENTER │ │ - [ fe61] ZZNAMFRM │ │ - [ fe6a] attcpy │ │ - [ fe71] YD │ │ - [ fe74] e │ │ - [ fe76] P.M. │ │ - [ fe7b] i:i:i:i │ │ - [ fe83] The day of the month specified for the month of # was #. For # the day must be at least 1.0D0 and less than #. │ │ - [ fef4] ZZRVBF │ │ - [ fefb] SCLU01 │ │ - [ ff02] Mean eccentricity value, #, beyond allowed bounds [-0.001,1.0). This error may indicate a bad TLE set. │ │ - [ ff69] SPICE(BADMSEMIMAJOR) │ │ - [ ff7e] ttrans_ │ │ - [ ff86] RMAIND │ │ - [ ff8d] GREGORIAN │ │ - [ ff97] Day of Year │ │ - [ ffa3] APRIL │ │ - [ ffa9] PST │ │ - [ ffad] mnmrk │ │ - [ ffb3] Y-i-iti:i:n │ │ - [ ffbf] Y-i-iti:n │ │ - [ ffc9] Ymn │ │ - [ ffcd] i/i/Y │ │ - [ ffd3] Y-iti │ │ - [ ffd9] Y-i-iti:nx │ │ - [ ffe4] i-i-iti:nx │ │ - [ ffef] bem │ │ - [ fff3] din │ │ - [ fff7] dum │ │ - [ fffb] ksb │ │ - [ ffff] lmo │ │ - [ 10003] lo │ │ - [ 10006] mad │ │ - [ 1000a] nd │ │ - [ 1000d] so │ │ - [ 10010] twq │ │ - [ 10014] wa │ │ - [ 10017] wo │ │ - [ 1001a] arg │ │ - [ 1001e] div │ │ - [ 10022] ewe │ │ - [ 10026] glv │ │ - [ 1002a] srd │ │ - [ 1002e] smo │ │ - [ 10032] swa │ │ - [ 10036] AZ │ │ - [ 10039] BD │ │ - [ 1003c] BV │ │ - [ 1003f] FJ │ │ - [ 10042] PH │ │ - [ 10045] AND │ │ - [ 10049] GEO │ │ - [ 1004d] NZL │ │ - [ 10051] REU │ │ - [ 10055] bg_BG │ │ - [ 1005b] ms_MY │ │ - [ 10061] sk_SK │ │ - [ 10067] sw_TZ │ │ - [ 1006d] ta_IN │ │ - [ 10073] territory │ │ - [ 1007d] replacement │ │ - [ 10089] EST5EDT │ │ - [ 10091] VLAST │ │ - [ 10097] America/St_Johns │ │ - [ 100a8] und-u- │ │ - [ 100af] langInfo │ │ - [ 100b8] ar_LY │ │ - [ 100be] bin_NG │ │ - [ 100c5] sr_Cyrl │ │ - [ 100cd] kr_NG │ │ - [ 100d3] REORDER_CODE │ │ - [ 100e0] RG_KEY_VALUE │ │ - [ 100ed] ami │ │ - [ 100f1] tay │ │ - [ 100f5] tsu │ │ - [ 100f9] bfi │ │ - [ 100fd] sgn-nl │ │ - [ 10104] cmn-hant │ │ - [ 1010d] ucnv_flushCache │ │ - [ 1011d] buddhist │ │ - [ 10126] unorm2_swap(): data format %02x.%02x.%02x.%02x (format version %02x) is not recognized as Normalizer2 data\n │ │ - [ 10192] lowercase letter │ │ - [ 101a3] math symbol │ │ - [ 101af] U_INVALID_CHAR_FOUND │ │ - [ 101c4] U_UNDEFINED_VARIABLE │ │ - [ 101d9] U_INVALID_FUNCTION │ │ - [ 101ec] ARP │ │ - [ 101f0] BRE │ │ - [ 101f4] COP │ │ - [ 101f8] CZK │ │ - [ 101fc] GIP │ │ - [ 10200] GNF │ │ - [ 10204] ILP │ │ - [ 10208] LTL │ │ - [ 1020c] MAD │ │ - [ 10210] MCF │ │ - [ 10214] MUR │ │ - [ 10218] 9.223372036854775808E+18 │ │ - [ 10231] Subnormal │ │ - [ 1023b] permillion │ │ - [ 10246] byte │ │ - [ 1024b] newton │ │ - [ 10252] cubic-meter │ │ - [ 1025e] common │ │ - [ 10265] /replacement │ │ - [ 10272] secondary │ │ - [ 1027c] starred-relation string range contains U+FFFD, U+FFFE or U+FFFF │ │ - [ 102bc] [import langTag] is not supported │ │ - [ 102de] last primary ignorable │ │ - [ 102f5] first variable │ │ - [ 10304] mu │ │ - [ 10307] ft2_to_m2 │ │ - [ 10311] AChoreographer_registerRefreshRateCallback │ │ - [ 1033c] dalvik/system/PathClassLoader │ │ - [ 1035a] getCacheDir │ │ - [ 10366] bool swappy::SwappyGL::setPresentationTime(swappy::EGLDisplay, swappy::EGLSurface) │ │ - [ 103b9] getRefreshRate │ │ - [ 103c8] mPipelineMode │ │ - [ 103d6] MANUFACTURER │ │ - [ 103e3] Invalid filetype │ │ - [ 103f4] Light gain: {:3.0f} % │ │ - [ 1040a] planetographic grid │ │ - [ 1041e] Error opening asterisms file {}.\n │ │ - [ 10440] SolarSystemCatalogs │ │ - [ 10454] M │ │ - [ 10456] S │ │ - [ 10458] Number of interpolators: %s\n │ │ - [ 10475] c │ │ - [ 10477] Black hole │ │ - [ 10482] m │ │ - [ 10484] {} {} │ │ - [ 1048a] Capture │ │ - [ 10492] CHANNEL_FRONT_LEFT │ │ - [ 104a5] Resource already exists │ │ - [ 104bd] Too many open files │ │ - [ 104d1] AAudioStream_close │ │ - [ 104e4] AAudioStream_requestStart │ │ - [ 104fe] [OpenSL] Failed to start internal capture device. │ │ - [ 10530] cue │ │ - [ 10535] Unsupported URL version: {}\n │ │ - [ 10552] Mar │ │ - [ 10556] darkmagenta │ │ - [ 10562] darkviolet │ │ - [ 1056d] fuchsia │ │ - [ 10575] greenyellow │ │ - [ 10581] ZET │ │ - [ 10589] automag │ │ - [ 10591] tessera │ │ - [ 10599] volcano │ │ - [ 105a1] fluctus │ │ - [ 105a9] albedo │ │ - [ 105b0] saxum │ │ - [ 105b6] overlay │ │ - [ 105be] setambientlight │ │ - [ 105ce] jpg │ │ - [ 105d2] find │ │ - [ 105d7] gettitlefont │ │ - [ 105e4] One argument expected to function celestia:gettextwidth │ │ - [ 1061c] No arguments expected for celestia:getlabelflags() │ │ - [ 1064f] One argument expected to function celestia:settime │ │ - [ 10682] No argument expected in celestia:getstardistancelimit │ │ - [ 106b8] Second argument for celestia:setaudionopause must be a boolean │ │ - [ 106f7] argument 2 to gl.TexCoord must be a number │ │ - [ 10722] One argument expected for gl.MatrixMode() │ │ - [ 1074c] One argument required for font:render │ │ - [ 10772] No arguments expected for image:getwidth() │ │ - [ 1079d] orbitvisibility │ │ - [ 107ad] null │ │ - [ 107b2] No arguments are expected for object:getdensity() │ │ - [ 107e4] rayleigh │ │ - [ 107ed] sunsetcolor │ │ - [ 107f9] travelling │ │ - [ 10804] __eq │ │ - [ 10809] No arguments expected for observer:isvalid() │ │ - [ 10836] Argument 1 and 2 (of 3) to observer:lookat must be of type position │ │ - [ 1087a] One argument expected to observer:setsurface() │ │ - [ 108a9] One argument expected for observer:setlocationflags() │ │ - [ 108df] getx │ │ - [ 108e4] No arguments expected for position:getz() │ │ - [ 1090e] real │ │ - [ 10913] pointsize │ │ - [ 1091d] has tangents: {}\n │ │ - [ 1092f] normalmap "{}"\n │ │ - [ 1093f] color0 │ │ - [ 10947] f1\n │ │ - [ 1094b] end_vertexdesc\n │ │ - [ 1095b] jpl-neptune-ssb │ │ - [ 1096b] jpl-venus-ssb │ │ - [ 10979] saturn │ │ - [ 10980] pluto-sun │ │ - [ 1098a] dione │ │ - [ 10990] ariel │ │ - [ 10996] iau-mercury │ │ - [ 109a2] eclipj2000 │ │ - [ 109ad] Men │ │ - [ 109b1] Mus │ │ - [ 109b5] Exceeded maximum DSO count.\n │ │ - [ 109d2] LO │ │ - [ 109d5] CM │ │ - [ 109d8] Historical │ │ - [ 109e3] CustomRotation │ │ - [ 109f2] EquatorJ2000 │ │ - [ 109ff] +x │ │ - [ 10a02] + vec2(textureOffset, 0.0);\n │ │ - [ 10a20] , n);\n │ │ - [ 10a27] , n)) * clamp( │ │ - [ 10a36] vec4 color = v_Color;\n │ │ - [ 10a51] overlayTex │ │ - [ 10a5c] in_TexCoord2 │ │ - [ 10a69] Deprecated parameter Albedo used in {} definition.\n │ │ + [ f177] gamma value out of range │ │ + [ f190] invalid chromaticities │ │ + [ f1a7] background color must be supplied to remove alpha/transparency │ │ + [ f1e6] Saving unknown chunk: │ │ + [ f1fc] cHRM Blue Y │ │ + [ f208] png_set_gAMA │ │ + [ f215] Invalid palette size, hIST allocation skipped │ │ + [ f243] Insufficient memory for pCAL parameter │ │ + [ f26a] keyword "@1": bad character '0x@2' │ │ + [ f28d] Only compression method 8 is supported by PNG │ │ + [ f2bb] Ignoring attempt to write 16-bit tRNS chunk when bit_depth is 8 │ │ + [ f2fb] chkout_c │ │ + [ f304] errint_c │ │ + [ f30d] SPICE(FILEALREADYOPEN) │ │ + [ f324] SPICE(FILEREADFAILED) │ │ + [ f33a] An Invalid Option Value Was Supplied │ │ + [ f35f] kind │ │ + [ f364] itprvh │ │ + [ f36b] SPICE(DAFINVALIDPARAMS) │ │ + [ f383] sequential io not allowed │ │ + [ f39d] external │ │ + [ f3a6] #1 │ │ + [ f3a9] > │ │ + [ f3ab] SPICE(EKNOSEGMENTS) │ │ + [ f3bf] DONE │ │ + [ f3c4] EKGI │ │ + [ f3c9] The file table is full, with # entries. Could not open a scratch file. If a call to DASOPS was not made and this error occurred, it is likely that the DAS file table was full and an attempt to close a file opened with write access was made. See the DAS required reading and DASFM for details. │ │ + [ f4ee] lastla │ │ + [ f4f5] endfile │ │ + [ f4fd] The cell cannot accommodate the addition of the item *. │ │ + [ f535] DASA2L │ │ + [ f53c] rnbufi │ │ + [ f543] ' │ │ + [ f545] pxform_c │ │ + [ f54e] CLASS_ID │ │ + [ f557] The reference frame # has class #. This form of reference frame is not supported in version # of ROTGET. You need to update your version of SPICELIB to the latest version in order to support this frame. │ │ + [ f623] SPICE(WRONGDATATYPE) │ │ + [ f638] pbuffr │ │ + [ f63f] rotmat_ │ │ + [ f647] SCFM01 │ │ + [ f64e] SCTE01 │ │ + [ f655] FAILURE │ │ + [ f65d] outmsg_ │ │ + [ f665] TOOLKIT │ │ + [ f66d] Unexpected SPK type 19 subtype found in type 19 record. │ │ + [ f6a5] SPICE(BADLATUSRECTUM) │ │ + [ f6bb] savegm │ │ + [ f6c2] SPICE(ECCOUTOFBOUNDS) │ │ + [ f6d8] spke08_ │ │ + [ f6e0] Request time # is outside of descriptor bounds # : #. │ │ + [ f716] SPICE(TIMEOUTOFBOUNDS) │ │ + [ f72d] SPKR09 │ │ + [ f734] Packet count # is less than the minimum valid value, which is 2. │ │ + [ f775] Window size in type 18 segment was #; max allowed value is # for subtype 0 (Hermite, 12-element packets). │ │ + [ f7df] Window size in type 18 segment was #; max allowed value is # for subtype 1 (Lagrange, 6-element packets). │ │ + [ f849] BODY#_PM │ │ + [ f852] bnphco │ │ + [ f859] The data associated with variable # are not of numeric type. │ │ + [ f896] #: The kernel pool variable '#' must be of type "NUMERIC". However, the current type is character. │ │ + [ f8fb] %+.2d │ │ + [ f901] dididx │ │ + [ f908] Logical unit associated with # file $, is trying to be unlocked by routines in in the % system. │ │ + [ f968] At least one of the kernel variables FRAME_#_# or FRAME_#_# was expected to be present in the kernel pool but neither was found. One of these variables is needed to define the reference frame #. Usually this type of problem is due to a missing keyword assignment in a frame kernel. Another, less likely, possibility is that other errors in a frame kernel have confused the frame subsystem into wrongly deciding these variables are needed. │ │ + [ fb21] In definition of frame #, the frame associated with a constant vector has frame ID code #, but no frame center, frame class, or frame class ID was found by FRINFO. This situation MAY be caused by an error in a frame kernel in which the frame is defined. The problem also could be indicative of a SPICELIB bug. │ │ + [ fc58] QDERIV │ │ + [ fc5f] SPICE(UNDEFINEDFRAME) │ │ + [ fc75] seqnce │ │ + [ fc7c] ZZDYNVAD │ │ + [ fc85] Column # should be DP or TIME but has type #. │ │ + [ fcb3] ZZEKRSC │ │ + [ fcbb] PRTDEC │ │ + [ fcc2] ZZEKRD02 │ │ + [ fccb] Attempted to read uninitialized column entry. SEGNO = #; COLIDX = #; RECNO = #; EK = # │ │ + [ fd23] ZZEKTRLK │ │ + [ fd2c] Table count for first join row set was #; valid range is 1:# │ │ + [ fd69] IAU_SINOPE │ │ + [ fd74] IAU_RHEA │ │ + [ fd7d] ITRF93 │ │ + [ fd84] IAU_PATROCLUS_BARYCENTER │ │ + [ fd9d] MERCURY │ │ + [ fda5] JUPITER │ │ + [ fdad] IO │ │ + [ fdb0] ISONOE │ │ + [ fdb7] PRAXIDIKE │ │ + [ fdc1] KALE │ │ + [ fdc6] KALLICHORE │ │ + [ fdd1] SATURN │ │ + [ fdd8] RHEA │ │ + [ fddd] ARIEL │ │ + [ fde3] SETEBOS │ │ + [ fdeb] KERBEROS │ │ + [ fdf4] VENUS ORBITER │ │ + [ fe02] JNSB │ │ + [ fe07] MSL │ │ + [ fe0b] CASSINI ITL │ │ + [ fe17] DFLY │ │ + [ fe1c] KOREAN PATHFINDER LUNAR ORBITER │ │ + [ fe3c] SMART1 │ │ + [ fe43] VEX │ │ + [ fe47] BEPICOLOMBO MTM │ │ + [ fe57] JOHNSON │ │ + [ fe5f] RUSSELL 1 │ │ + [ fe69] RUSSELL 4 │ │ + [ fe73] VESTA │ │ + [ fe79] EURYBATES_BARYCENTER │ │ + [ fe8e] ZZNAMFRM │ │ + [ fe97] attcpy │ │ + [ fe9e] YD │ │ + [ fea1] e │ │ + [ fea3] P.M. │ │ + [ fea8] i:i:i:i │ │ + [ feb0] The day of the month specified for the month of # was #. For # the day must be at least 1.0D0 and less than #. │ │ + [ ff21] ZZRVBF │ │ + [ ff28] SCLU01 │ │ + [ ff2f] Mean eccentricity value, #, beyond allowed bounds [-0.001,1.0). This error may indicate a bad TLE set. │ │ + [ ff96] SPICE(BADMSEMIMAJOR) │ │ + [ ffab] ttrans_ │ │ + [ ffb3] RMAIND │ │ + [ ffba] GREGORIAN │ │ + [ ffc4] Day of Year │ │ + [ ffd0] APRIL │ │ + [ ffd6] PST │ │ + [ ffda] mnmrk │ │ + [ ffe0] Y-i-iti:i:n │ │ + [ ffec] Y-i-iti:n │ │ + [ fff6] Ymn │ │ + [ fffa] i/i/Y │ │ + [ 10000] Y-iti │ │ + [ 10006] Y-i-iti:nx │ │ + [ 10011] i-i-iti:nx │ │ + [ 1001c] bem │ │ + [ 10020] din │ │ + [ 10024] dum │ │ + [ 10028] ksb │ │ + [ 1002c] lmo │ │ + [ 10030] lo │ │ + [ 10033] mad │ │ + [ 10037] nd │ │ + [ 1003a] so │ │ + [ 1003d] twq │ │ + [ 10041] wa │ │ + [ 10044] wo │ │ + [ 10047] arg │ │ + [ 1004b] div │ │ + [ 1004f] ewe │ │ + [ 10053] glv │ │ + [ 10057] srd │ │ + [ 1005b] smo │ │ + [ 1005f] swa │ │ + [ 10063] AZ │ │ + [ 10066] BD │ │ + [ 10069] BV │ │ + [ 1006c] FJ │ │ + [ 1006f] PH │ │ + [ 10072] AND │ │ + [ 10076] GEO │ │ + [ 1007a] NZL │ │ + [ 1007e] REU │ │ + [ 10082] bg_BG │ │ + [ 10088] ms_MY │ │ + [ 1008e] sk_SK │ │ + [ 10094] sw_TZ │ │ + [ 1009a] ta_IN │ │ + [ 100a0] territory │ │ + [ 100aa] replacement │ │ + [ 100b6] EST5EDT │ │ + [ 100be] VLAST │ │ + [ 100c4] America/St_Johns │ │ + [ 100d5] und-u- │ │ + [ 100dc] langInfo │ │ + [ 100e5] ar_LY │ │ + [ 100eb] bin_NG │ │ + [ 100f2] sr_Cyrl │ │ + [ 100fa] kr_NG │ │ + [ 10100] REORDER_CODE │ │ + [ 1010d] RG_KEY_VALUE │ │ + [ 1011a] ami │ │ + [ 1011e] tay │ │ + [ 10122] tsu │ │ + [ 10126] bfi │ │ + [ 1012a] sgn-nl │ │ + [ 10131] cmn-hant │ │ + [ 1013a] ucnv_flushCache │ │ + [ 1014a] buddhist │ │ + [ 10153] unorm2_swap(): data format %02x.%02x.%02x.%02x (format version %02x) is not recognized as Normalizer2 data\n │ │ + [ 101bf] lowercase letter │ │ + [ 101d0] math symbol │ │ + [ 101dc] U_INVALID_CHAR_FOUND │ │ + [ 101f1] U_UNDEFINED_VARIABLE │ │ + [ 10206] U_INVALID_FUNCTION │ │ + [ 10219] ARP │ │ + [ 1021d] BRE │ │ + [ 10221] COP │ │ + [ 10225] CZK │ │ + [ 10229] GIP │ │ + [ 1022d] GNF │ │ + [ 10231] ILP │ │ + [ 10235] LTL │ │ + [ 10239] MAD │ │ + [ 1023d] MCF │ │ + [ 10241] MUR │ │ + [ 10245] 9.223372036854775808E+18 │ │ + [ 1025e] Subnormal │ │ + [ 10268] permillion │ │ + [ 10273] byte │ │ + [ 10278] newton │ │ + [ 1027f] cubic-meter │ │ + [ 1028b] common │ │ + [ 10292] /replacement │ │ + [ 1029f] secondary │ │ + [ 102a9] starred-relation string range contains U+FFFD, U+FFFE or U+FFFF │ │ + [ 102e9] [import langTag] is not supported │ │ + [ 1030b] last primary ignorable │ │ + [ 10322] first variable │ │ + [ 10331] mu │ │ + [ 10334] ft2_to_m2 │ │ + [ 1033e] AChoreographer_registerRefreshRateCallback │ │ + [ 10369] dalvik/system/PathClassLoader │ │ + [ 10387] getCacheDir │ │ + [ 10393] bool swappy::SwappyGL::setPresentationTime(swappy::EGLDisplay, swappy::EGLSurface) │ │ + [ 103e6] getRefreshRate │ │ + [ 103f5] mPipelineMode │ │ + [ 10403] MANUFACTURER │ │ + [ 10410] Invalid filetype │ │ + [ 10421] Light gain: {:3.0f} % │ │ + [ 10437] planetographic grid │ │ + [ 1044b] Error opening asterisms file {}.\n │ │ + [ 1046d] SolarSystemCatalogs │ │ + [ 10481] M │ │ + [ 10483] S │ │ + [ 10485] Number of interpolators: %s\n │ │ + [ 104a2] c │ │ + [ 104a4] Black hole │ │ + [ 104af] m │ │ + [ 104b1] {} {} │ │ + [ 104b7] Capture │ │ + [ 104bf] CHANNEL_FRONT_LEFT │ │ + [ 104d2] Resource already exists │ │ + [ 104ea] Too many open files │ │ + [ 104fe] AAudioStream_close │ │ + [ 10511] AAudioStream_requestStart │ │ + [ 1052b] [OpenSL] Failed to start internal capture device. │ │ + [ 1055d] cue │ │ + [ 10562] Unsupported URL version: {}\n │ │ + [ 1057f] Mar │ │ + [ 10583] darkmagenta │ │ + [ 1058f] darkviolet │ │ + [ 1059a] fuchsia │ │ + [ 105a2] greenyellow │ │ + [ 105ae] ZET │ │ + [ 105b6] automag │ │ + [ 105be] tessera │ │ + [ 105c6] volcano │ │ + [ 105ce] fluctus │ │ + [ 105d6] albedo │ │ + [ 105dd] saxum │ │ + [ 105e3] overlay │ │ + [ 105eb] setambientlight │ │ + [ 105fb] jpg │ │ + [ 105ff] find │ │ + [ 10604] gettitlefont │ │ + [ 10611] One argument expected to function celestia:gettextwidth │ │ + [ 10649] No arguments expected for celestia:getlabelflags() │ │ + [ 1067c] One argument expected to function celestia:settime │ │ + [ 106af] No argument expected in celestia:getstardistancelimit │ │ + [ 106e5] Second argument for celestia:setaudionopause must be a boolean │ │ + [ 10724] argument 2 to gl.TexCoord must be a number │ │ + [ 1074f] One argument expected for gl.MatrixMode() │ │ + [ 10779] One argument required for font:render │ │ + [ 1079f] No arguments expected for image:getwidth() │ │ + [ 107ca] orbitvisibility │ │ + [ 107da] null │ │ + [ 107df] No arguments are expected for object:getdensity() │ │ + [ 10811] rayleigh │ │ + [ 1081a] sunsetcolor │ │ + [ 10826] travelling │ │ + [ 10831] __eq │ │ + [ 10836] No arguments expected for observer:isvalid() │ │ + [ 10863] Argument 1 and 2 (of 3) to observer:lookat must be of type position │ │ + [ 108a7] One argument expected to observer:setsurface() │ │ + [ 108d6] One argument expected for observer:setlocationflags() │ │ + [ 1090c] getx │ │ + [ 10911] No arguments expected for position:getz() │ │ + [ 1093b] real │ │ + [ 10940] pointsize │ │ + [ 1094a] has tangents: {}\n │ │ + [ 1095c] normalmap "{}"\n │ │ + [ 1096c] color0 │ │ + [ 10974] f1\n │ │ + [ 10978] end_vertexdesc\n │ │ + [ 10988] jpl-neptune-ssb │ │ + [ 10998] jpl-venus-ssb │ │ + [ 109a6] saturn │ │ + [ 109ad] pluto-sun │ │ + [ 109b7] dione │ │ + [ 109bd] ariel │ │ + [ 109c3] iau-mercury │ │ + [ 109cf] eclipj2000 │ │ + [ 109da] Men │ │ + [ 109de] Mus │ │ + [ 109e2] Exceeded maximum DSO count.\n │ │ + [ 109ff] LO │ │ + [ 10a02] CM │ │ + [ 10a05] Historical │ │ + [ 10a10] CustomRotation │ │ + [ 10a1f] EquatorJ2000 │ │ + [ 10a2c] +x │ │ + [ 10a2f] + vec2(textureOffset, 0.0);\n │ │ + [ 10a4d] , n);\n │ │ + [ 10a54] , n)) * clamp( │ │ + [ 10a63] vec4 color = v_Color;\n │ │ + [ 10a7e] overlayTex │ │ + [ 10a89] in_TexCoord2 │ │ + [ 10a96] Deprecated parameter Albedo used in {} definition.\n │ │ Use GeomAlbedo & BondAlbedo instead.\n │ │ - [ 10ac2] Mass │ │ - [ 10ac7] Invalid filename in CloudNormalMap\n │ │ - [ 10aeb] Invalid filename in SpecularTexture\n │ │ - [ 10b10] DQ │ │ - [ 10b13] SAO {} │ │ - [ 10b1a] Creating ordinary texture: {}x{}\n │ │ - [ 10b3c] Error opening virtual texture file: {}\n │ │ - [ 10b64] Failed to read face array count\n │ │ - [ 10b85] ": │ │ - [ 10b88] Destroying context │ │ - [ 10b9b] eglDestroySurface() returned error %d │ │ - [ 10bc1] ju │ │ - [ 10bc4] Unsupported color conversion request │ │ - [ 10be9] Output file write error --- out of disk space? │ │ - [ 10c18] Freed EMS handle %u │ │ - [ 10c2c] t1cid │ │ - [ 10c32] tt-glyf │ │ - [ 10c3a] interpreter-version │ │ - [ 10c4e] PaintType │ │ - [ 10c58] known │ │ - [ 10c5e] MAX_SPACE │ │ - [ 10c68] RAW_X_HEIGHT │ │ - [ 10c75] RELATIVE_SETWIDTH │ │ - [ 10c87] SWIDTH │ │ - [ 10c8e] EndFontMetrics │ │ - [ 10c9d] IsCIDFont │ │ - [ 10ca7] trace │ │ - [ 10cad] (*temporary) │ │ - [ 10cba] closed file │ │ - [ 10cc6] lastlinedefined │ │ - [ 10cd6] Invalid attempt to read row data │ │ - [ 10cf7] Can't set both read_data_fn and write_data_fn in the same structure │ │ - [ 10d3b] invalid alpha mode │ │ - [ 10d4e] Not a PNG file │ │ - [ 10d5d] No space in chunk cache for sPLT │ │ - [ 10d7e] using zstream │ │ - [ 10d8d] too many sPLT chunks │ │ - [ 10da2] No IDATs written into file │ │ - [ 10dbd] Unrecognized unit type for pHYs chunk │ │ - [ 10de3] Invalid time specified for tIME chunk │ │ - [ 10e09] # │ │ - [ 10e0b] chkin_c │ │ - [ 10e13] b │ │ - [ 10e15] The Input and Output Units are Incompatible │ │ - [ 10e41] An Invalid Operation Value Was Supplied │ │ - [ 10e69] keeper_ │ │ - [ 10e71] SEARCH W/O BUFF │ │ - [ 10e81] reading │ │ - [ 10e89] DAFRS │ │ - [ 10e8f] SUMMARIZE_SEGMENT │ │ - [ 10ea1] ctindx │ │ - [ 10ea8] Column indices for table # range from # to #; requested index was #. │ │ - [ 10eed] rtbidx │ │ - [ 10ef4] Array indices FIRST and LAST were #, #; allowed range for both is [#, #]. File was #, record number was #. │ │ - [ 10f60] dasrwr_ │ │ - [ 10f68] rnbufc │ │ - [ 10f6f] LNKAN │ │ - [ 10f75] Node HEAD: node number = #; backward pointer = #; forward pointer = #. Node TAIL: node number = #; backward pointer = #; forward pointer = #. ("FREE" is #) │ │ - [ 11013] LNKILB │ │ - [ 1101a] PCPOOL │ │ - [ 11021] SZPOOL │ │ - [ 11028] kclass │ │ - [ 1102f] Invalid frame specification found in kernel pool: frame class keyword is # but integer class was not associated with this keyword. │ │ - [ 110b2] SPICE(INVALIDFRAMEDEF) │ │ - [ 110c9] _ID │ │ - [ 110cd] The input string could not be recognized as a number. │ │ - [ 11104] usrctr │ │ - [ 1110b] Unexpected CK type 5 subtype # found in type 5 segment. │ │ - [ 11143] Quaternion sign error: quaternion at index # in the input record is farther than its negative from the preceding quaternion in the record. Quaternion is (#, #, #, #); predecessor is (#, #, #, #). This makes the quaternion sequence unsuitable for Hermite interpolation. The quaternions, and if applicable, their derivatives, must be adjusted before they are passed to this routine. │ │ - [ 112c0] state │ │ - [ 112c6] Window size in type 06 segment was #; must be even for subtype #. Mini-segment index is #. │ │ - [ 11321] SPICE(BUG): The trcdep_ routine returned a depth, %i, larger than the maximum allowed depth, %i. This error should never signal. Please contact NAIF.\n │ │ + [ 10aef] Mass │ │ + [ 10af4] Invalid filename in CloudNormalMap\n │ │ + [ 10b18] Invalid filename in SpecularTexture\n │ │ + [ 10b3d] DQ │ │ + [ 10b40] SAO {} │ │ + [ 10b47] Creating ordinary texture: {}x{}\n │ │ + [ 10b69] Error opening virtual texture file: {}\n │ │ + [ 10b91] Failed to read face array count\n │ │ + [ 10bb2] ": │ │ + [ 10bb5] Destroying context │ │ + [ 10bc8] eglDestroySurface() returned error %d │ │ + [ 10bee] ju │ │ + [ 10bf1] Unsupported color conversion request │ │ + [ 10c16] Output file write error --- out of disk space? │ │ + [ 10c45] Freed EMS handle %u │ │ + [ 10c59] t1cid │ │ + [ 10c5f] tt-glyf │ │ + [ 10c67] interpreter-version │ │ + [ 10c7b] PaintType │ │ + [ 10c85] known │ │ + [ 10c8b] MAX_SPACE │ │ + [ 10c95] RAW_X_HEIGHT │ │ + [ 10ca2] RELATIVE_SETWIDTH │ │ + [ 10cb4] SWIDTH │ │ + [ 10cbb] EndFontMetrics │ │ + [ 10cca] IsCIDFont │ │ + [ 10cd4] trace │ │ + [ 10cda] (*temporary) │ │ + [ 10ce7] closed file │ │ + [ 10cf3] lastlinedefined │ │ + [ 10d03] Invalid attempt to read row data │ │ + [ 10d24] Can't set both read_data_fn and write_data_fn in the same structure │ │ + [ 10d68] invalid alpha mode │ │ + [ 10d7b] Not a PNG file │ │ + [ 10d8a] No space in chunk cache for sPLT │ │ + [ 10dab] using zstream │ │ + [ 10dba] too many sPLT chunks │ │ + [ 10dcf] No IDATs written into file │ │ + [ 10dea] Unrecognized unit type for pHYs chunk │ │ + [ 10e10] Invalid time specified for tIME chunk │ │ + [ 10e36] # │ │ + [ 10e38] chkin_c │ │ + [ 10e40] b │ │ + [ 10e42] The Input and Output Units are Incompatible │ │ + [ 10e6e] An Invalid Operation Value Was Supplied │ │ + [ 10e96] keeper_ │ │ + [ 10e9e] SEARCH W/O BUFF │ │ + [ 10eae] reading │ │ + [ 10eb6] DAFRS │ │ + [ 10ebc] SUMMARIZE_SEGMENT │ │ + [ 10ece] ctindx │ │ + [ 10ed5] Column indices for table # range from # to #; requested index was #. │ │ + [ 10f1a] rtbidx │ │ + [ 10f21] Array indices FIRST and LAST were #, #; allowed range for both is [#, #]. File was #, record number was #. │ │ + [ 10f8d] dasrwr_ │ │ + [ 10f95] rnbufc │ │ + [ 10f9c] LNKAN │ │ + [ 10fa2] Node HEAD: node number = #; backward pointer = #; forward pointer = #. Node TAIL: node number = #; backward pointer = #; forward pointer = #. ("FREE" is #) │ │ + [ 11040] LNKILB │ │ + [ 11047] PCPOOL │ │ + [ 1104e] SZPOOL │ │ + [ 11055] kclass │ │ + [ 1105c] Invalid frame specification found in kernel pool: frame class keyword is # but integer class was not associated with this keyword. │ │ + [ 110df] SPICE(INVALIDFRAMEDEF) │ │ + [ 110f6] _ID │ │ + [ 110fa] The input string could not be recognized as a number. │ │ + [ 11131] usrctr │ │ + [ 11138] Unexpected CK type 5 subtype # found in type 5 segment. │ │ + [ 11170] Quaternion sign error: quaternion at index # in the input record is farther than its negative from the preceding quaternion in the record. Quaternion is (#, #, #, #); predecessor is (#, #, #, #). This makes the quaternion sequence unsuitable for Hermite interpolation. The quaternions, and if applicable, their derivatives, must be adjusted before they are passed to this routine. │ │ + [ 112ed] state │ │ + [ 112f3] Window size in type 06 segment was #; must be even for subtype #. Mini-segment index is #. │ │ + [ 1134e] SPICE(BUG): The trcdep_ routine returned a depth, %i, larger than the maximum allowed depth, %i. This error should never signal. Please contact NAIF.\n │ │ sc01_ │ │ - [ 113bf] SCPR01 │ │ - [ 113c6] words │ │ - [ 113cc] MSGSEL: An invalid error message type was supplied as input; the type specifiedwas: │ │ - [ 11423] Input file # has architecture #. The file must be a binary SPK file to be readable by this routine. Binary SPK files have DAF architecture. If you expected the file to be a binary SPK file, the problem may be due to the file being an old non-native file lacking binary file format information. It's also possible the file has been corrupted. │ │ - [ 1157b] GETFAT │ │ - [ 11582] The mass supplied for the central body of a type 15 segment was non-positive. Masses must be positive. The value supplied was #. │ │ - [ 11605] The eccentricity supplied for a type 17 segment is greater than 0.9. It must be less than 0.9.The value supplied to the type 17 evaluator was #. │ │ - [ 11698] The semi-major axis supplied to EQNCPV was non-positive. The value is required to be positive by this routine. The value supplied was #. │ │ - [ 11722] PCK data required to compute the orientation of the # # for epoch # TDB were not found. If these data were to be provided by a binary PCK file, then it is possible that the PCK file does not have coverage for the specified body-fixed frame at the time of interest. If the data were to be provided by a text PCK file, then possibly the file does not contain data for the specified body-fixed frame. In either case it is possible that a required PCK file was not loaded at all. │ │ - [ 118fe] MAX_PHASE_DEGREE │ │ - [ 1190f] dtipm │ │ - [ 11915] N0067 │ │ - [ 1191b] marker or final newline character, or is │ │ - [ 11945] Left endpoint was *. Right endpoint was *. │ │ - [ 11970] IOSTAT = │ │ - [ 1197a] CLLINE: File = │ │ - [ 1198b] w_ed, unexpected code: %d\n │ │ - [ 119a6] defnam │ │ - [ 119ad] An attempt to assign the code, #, to a blank string was made. Check loaded text kernels for a blank string in the NAIF_BODY_NAME array. │ │ - [ 11a36] ZZDAFGSR │ │ - [ 11a3f] The attempt to load file, '#', with access method, '#', failed because this access method is unsupported. │ │ - [ 11aa9] strarc │ │ - [ 11ab0] Definition of frame # contains # specification #. The only valid rotation states are # or #. This situation is usually caused by an error in a frame kernel in which the frame is defined. │ │ - [ 11b6b] NONE │ │ - [ 11b70] ddat │ │ - [ 11b75] N_D_ALLOC │ │ - [ 11b7f] ZZEKSZ05 │ │ - [ 11b88] IAU_DEIMOS │ │ - [ 11b93] IAU_OPHELIA │ │ - [ 11b9f] LONGEST LIST SIZE │ │ - [ 11bb1] MAB │ │ - [ 11bb5] MEX │ │ - [ 11bb9] JUNO │ │ - [ 11bbe] NEAR EARTH ASTEROID RENDEZVOUS │ │ - [ 11bdd] DIXI │ │ - [ 11be2] CH2L │ │ - [ 11be7] MAP │ │ - [ 11beb] DAWN │ │ - [ 11bf0] RBSP_A │ │ - [ 11bf7] MARS-96 │ │ - [ 11bff] SHOEMAKER-LEVY 9-N │ │ - [ 11c12] SHOEMAKER-LEVY 9-B │ │ - [ 11c25] FAYE │ │ - [ 11c2a] GICLAS │ │ - [ 11c31] SCHUSTER │ │ - [ 11c3a] TRITTON │ │ - [ 11c42] HELIN-ROMAN-ALU 1 │ │ - [ 11c54] MATHILDE │ │ - [ 11c5d] MADRID │ │ - [ 11c64] DSS-17 │ │ - [ 11c6b] # is a CK frame; a CK file containing data for instrument or structure # at the epoch shown above, as well as a corresponding SCLK kernel, must be loaded in order to use this frame. │ │ - [ 11d21] │ │ - [ 11d42] zzplatfm_ │ │ - [ 11d4c] ZZPLTCHK │ │ - [ 11d55] zzrefch0_ │ │ - [ 11d5f] [w] │ │ - [ 11d63] Dm │ │ - [ 11d66] The type of the time vector specified was #, only 'YD' and 'YMD' are recognized. │ │ - [ 11db8] SPICE(BADKERNELVARTYPE) │ │ - [ 11dd0] Offset count # does not match field count # for SCLK #. │ │ - [ 11e08] SPICE(BADPECCENTRICITY) │ │ - [ 11e20] Semi-latus rectum less-than zero. │ │ - [ 11e42] zzspkgp0_ │ │ - [ 11e4c] Interval time bounds are not strictly increasing at interval index # for switch frame #. Time bounds are #:# TDB (# TDB : # TDB) │ │ - [ 11ecd] White Space │ │ - [ 11ed9] Month │ │ - [ 11edf] recog │ │ - [ 11ee5] UTC- │ │ - [ 11eea] Two substrings indicating a calendar year were identified in the input time string <#> and <#>: " │ │ - [ 11f4c] Both a day of year and month were identified in the input string. " │ │ - [ 11f90] ############## │ │ - [ 11f9f] Y*m*D*H*M │ │ - [ 11fa9] Y-idi:i │ │ - [ 11fb1] Y-idi:n │ │ - [ 11fb9] i-Y/i:i:n │ │ - [ 11fc3] i-i/i:i │ │ - [ 11fcb] miii:n │ │ - [ 11fd2] i-i-Yi:i:i │ │ - [ 11fdd] Y-itx │ │ - [ 11fe3] The direction vectors associated with states AXDEF and PLNDEF are linearly dependent. │ │ - [ 12039] hy__AREVMDA │ │ - [ 12045] aa │ │ - [ 12048] blo │ │ - [ 1204c] dsb │ │ - [ 12050] gn │ │ - [ 12053] grb │ │ - [ 12057] hai │ │ - [ 1205b] ho │ │ - [ 1205e] ksf │ │ - [ 12062] ku │ │ - [ 12065] lam │ │ - [ 12069] ml │ │ - [ 1206c] pap │ │ - [ 12070] tli │ │ - [ 12074] zbl │ │ - [ 12078] cos │ │ - [ 1207c] fra │ │ - [ 12080] jpn │ │ - [ 12084] nau │ │ - [ 12088] oci │ │ - [ 1208c] oji │ │ - [ 12090] sna │ │ - [ 12094] sun │ │ - [ 12098] DM │ │ - [ 1209b] GF │ │ - [ 1209e] GU │ │ - [ 120a1] LV │ │ - [ 120a4] PT │ │ - [ 120a7] SB │ │ - [ 120aa] TM │ │ - [ 120ad] ZM │ │ - [ 120b0] ATG │ │ - [ 120b4] CAN │ │ - [ 120b8] FRA │ │ - [ 120bc] GRC │ │ - [ 120c0] MKD │ │ - [ 120c4] MYS │ │ - [ 120c8] PCN │ │ - [ 120cc] SVN │ │ - [ 120d0] cs_CZ │ │ - [ 120d6] pl_PL │ │ - [ 120dc] ur_PK │ │ - [ 120e2] MST7MDT │ │ - [ 120ea] AST │ │ - [ 120ee] Chile/EasterIsland │ │ - [ 12101] America/Guatemala │ │ - [ 12113] ar_KW │ │ - [ 12119] en_MP │ │ - [ 1211f] fr_CI │ │ - [ 12125] haw_US │ │ - [ 1212c] om_ET │ │ - [ 12132] sd_Arab │ │ - [ 1213a] ti_ER │ │ - [ 12140] sgn-mx │ │ - [ 12147] ures_swap(): too few bytes (%d after header) for a resource bundle\n │ │ - [ 1218b] ures_swap().swapArray16(16-bit units[%d]) failed\n │ │ - [ 121bd] windowsZones │ │ - [ 121ca] weekData │ │ - [ 121d3] calendarPreferenceData │ │ - [ 121ea] M02 │ │ - [ 121ee] mapTimezones │ │ - [ 121fb] icudt75l-zone │ │ - [ 12209] pattern │ │ - [ 12211] line separator │ │ - [ 12220] U_UNSUPPORTED_ERROR │ │ - [ 12234] U_NO_SPACE_AVAILABLE │ │ - [ 12249] U_UNTERMINATED_QUOTE │ │ - [ 1225e] U_ILLEGAL_PAD_POSITION │ │ - [ 12275] U_ARGUMENT_TYPE_MISMATCH │ │ - [ 1228e] U_BRK_VARIABLE_REDFINITION │ │ - [ 122a9] U_BRK_MISMATCHED_PAREN │ │ - [ 122c0] U_BRK_UNDEFINED_VARIABLE │ │ - [ 122d9] U_REGEX_LOOK_BEHIND_LIMIT │ │ - [ 122f3] U_IDNA_LABEL_TOO_LONG_ERROR │ │ - [ 1230f] exceptions │ │ - [ 1231a] BOV │ │ - [ 1231e] BWP │ │ - [ 12322] CSK │ │ - [ 12326] ECV │ │ - [ 1232a] ESB │ │ - [ 1232e] LBP │ │ - [ 12332] LUL │ │ - [ 12336] SIT │ │ - [ 1233a] XBB │ │ - [ 1233e] XEU │ │ - [ 12342] XSU │ │ - [ 12346] Division by zero │ │ - [ 12357] Insufficient storage │ │ - [ 1236c] calendarData │ │ - [ 12379] @calendar=coptic │ │ - [ 1238a] concentr │ │ - [ 12393] consumption │ │ - [ 1239f] revolution │ │ - [ 123aa] square-mile │ │ - [ 123b6] liter-per-kilometer │ │ - [ 123ca] kilobit │ │ - [ 123d2] kilojoule │ │ - [ 123dc] milligram │ │ - [ 123e6] beaufort │ │ - [ 123ef] micro │ │ - [ 123f5] nano │ │ - [ 123fa] or-short │ │ - [ 12403] cldrVersion │ │ - [ 1240f] tsubo_to_m2 │ │ - [ 1241b] dalvik/system/InMemoryDexClassLoader │ │ - [ 12440] android/view/Display │ │ - [ 12455] MODEL │ │ - [ 1245b] unique_lock::lock: references null mutex │ │ - [ 12484] Comet tails disabled │ │ - [ 12499] Time: Backward │ │ - [ 124a8] ltr │ │ - [ 124ac] inverting crosshair │ │ - [ 124c0] MeasurementSystem │ │ - [ 124d2] RayBasedDragging │ │ - [ 124e3] OrbitPeriodsShown │ │ - [ 124f5] false\n │ │ - [ 124fd] selection " │ │ - [ 12509] LT │ │ - [ 1250e] Chase %s\n │ │ - [ 12518] Density: {} lb/ft�\n │ │ - [ 1252d] Loading symbol: %s\n │ │ - [ 12541] Capture Device │ │ - [ 12550] Attempting to initialize %s backend...\n │ │ - [ 12578] Failed to initialize %s backend.\n │ │ - [ 1259a] Channel Routing: %s\n │ │ - [ 125bc] CHANNEL_AUX_4 │ │ - [ 125ca] Out of memory │ │ - [ 125d8] Failed to initialize backend │ │ - [ 125f5] [AAudio] Device Disconnected. Failed to post job for rerouting.\n │ │ - [ 12636] AAudioStreamBuilder_setFormat │ │ - [ 12654] AAudioStream_getState │ │ - [ 1266a] [OpenSL] Failed to stop internal playback device. │ │ - [ 1269c] labl │ │ - [ 126a1] note │ │ - [ 126a6] darksalmon │ │ - [ 126b1] darkturquoise │ │ - [ 126bf] mediumaquamarine │ │ - [ 126d6] cloudmaps │ │ - [ 126e0] facula │ │ - [ 126e7] gotoloc │ │ - [ 126ef] setwindowbordersvisible │ │ - [ 12707] unmark │ │ - [ 1270e] unmarkall │ │ - [ 12718] view │ │ - [ 1271d] User data expected │ │ - [ 12730] showconstellations │ │ - [ 12743] hideconstellations │ │ - [ 12756] setoverlayelements │ │ - [ 12769] getstarstyle │ │ - [ 12776] tojulianday │ │ - [ 12782] getstar │ │ - [ 1278a] newcategory │ │ - [ 12796] Third argument to celestia:print must be a number │ │ - [ 127c8] Argument to celestia:getlabelcolor() must be a string │ │ - [ 127fe] setlinecolor: color values must be numbers │ │ - [ 12829] Values in table-argument to celestia:setoverlayelements() must be boolean │ │ - [ 12873] One argument expected for celestia:setgalaxylightgain() │ │ - [ 128ab] One argument expected for celestia:select() │ │ - [ 128d7] No argument expected to function celestia:ispaused │ │ - [ 1290a] No argument expected to function celestia:istimesynchronized │ │ - [ 12947] No argument expected to function celestia:gettimescale │ │ - [ 1297e] Second arg to celestia:settimescale must be a number │ │ - [ 129b3] No argument expected in celestia:getstarstyle │ │ - [ 129e1] Argument to celestia:setstarcolor must be a string │ │ - [ 12a14] Fourth argument to celestia:overlay must be a number (alpha) │ │ - [ 12a51] Second argument to celestia:play must be a number (volume) │ │ - [ 12a8c] edgeclamp │ │ - [ 12a96] string │ │ - [ 12a9d] Error: LuaState invalid in Celx_SafeGetNumber\n │ │ - [ 12acc] class_matrix │ │ - [ 12ad9] class_rotation │ │ - [ 12ae8] Color │ │ - [ 12aee] Translate │ │ - [ 12af8] One argument expected for gl.LineWidth() │ │ - [ 12b21] No arguments expected for font:unbind() │ │ - [ 12b49] Error while parsing CEL-script. │ │ - [ 12b69] First argument to object:setorbitvisibility() must be a string │ │ - [ 12ba8] Unknown visibility policy: {}\n │ │ - [ 12bc7] invisible │ │ - [ 12bd1] stellarClass │ │ - [ 12bde] absoluteMagnitude │ │ - [ 12bf0] hasRings │ │ - [ 12bf9] Time expected as argument to object:getphase │ │ - [ 12c26] setfov │ │ - [ 12c2d] accelTime │ │ - [ 12c37] Bad observer object (maybe tried to access a deleted view?)! │ │ - [ 12c74] Argument for observer:orbit must be a rotation │ │ - [ 12ca3] Bad phase object during garbage collection! │ │ - [ 12ccf] Bad phase object! │ │ - [ 12ce1] second argument to rotation:setaxisangle must be a number │ │ - [ 12d1b] normalize │ │ - [ 12d25] emissive │ │ - [ 12d2e] trilist │ │ - [ 12d36] texcoord1 │ │ - [ 12d41] jpl-sun-ssb │ │ - [ 12d4d] miranda │ │ - [ 12d55] iau-titan │ │ - [ 12d5f] Failed to load module for ScriptedOrbit: {}\n │ │ - [ 12d8c] ScriptedRotation generator function returned bad value.\n │ │ - [ 12dc5] %ld │ │ - [ 12dca] Loaded SPK file {}\n │ │ - [ 12dde] spk │ │ - [ 12de2] pixelWeight │ │ - [ 12dee] Error parsing asterism {} chain: expected array\n │ │ - [ 12e1f] Aur │ │ - [ 12e23] Cyg │ │ - [ 12e27] Sco │ │ - [ 12e2b] Error parsing deep sky catalog entry {}\n │ │ - [ 12e54] Galaxy (Hubble type: %s) │ │ - [ 12e6d] models/SBa.png │ │ - [ 12e7c] s │ │ - [ 12e7e] NoiseOffset │ │ - [ 12e8a] Could not find custom rotation model named '{}'\n │ │ - [ 12ebb] FixedAttitude │ │ - [ 12ec9] FixedPosition planetographic coordinates are not valid for stars.\n │ │ - [ 12f0c] MeridianAngle │ │ - [ 12f1a] Object has incorrect topocentric frame syntax.\n │ │ - [ 12f4a] Bad two-vector frame: vector has invalid axis label.\n │ │ - [ 12f80] rE │ │ - [ 12f83] tangent = in_Tangent;\n │ │ - [ 12f9a] );\n │ │ - [ 12f9e] shadowMaxDepth │ │ - [ 12fad] l = mix(NL, (NL / (max(NV, 0.001) + NL)), lunarLambert) * clamp( │ │ - [ 12fee] color.rgb = mix(color.rgb, overlayColor.rgb, overlayColor.a);\n │ │ - [ 1302d] gl_FragColor = color * diff + spec;\n │ │ - [ 13052] .st) * totalLight;\n │ │ - [ 13066] opticalDepth │ │ - [ 13073] ringShadowTexCoordX = │ │ - [ 1308a] triangles │ │ - [ 13094] Invalid SemiAxes value for object {}: [{}, {}, {}]\n │ │ - [ 130c8] Mie │ │ - [ 130cc] CloudNormalMap │ │ - [ 130db] OverlayTexture │ │ - [ 130ea] LabelColor │ │ - [ 130f5] Ia │ │ - [ 130f8] unrecognized object type │ │ - [ 13111] Content size {} too small to include face array count\n │ │ - [ 13148] (DDD)V │ │ - [ 1314f] (Ljava/lang/Object;)Z │ │ - [ 13165] Locations │ │ - [ 1316f] ],\n │ │ - [ 13173] occulter │ │ - [ 1317c] receiver │ │ - [ 13185] (I)Z │ │ - [ 1318a] LC_COLLATE │ │ - [ 13195] Bogus virtual array access │ │ - [ 131b0] Memory limit exceeded │ │ - [ 131c6] Not a JPEG file: starts with 0x%02x 0x%02x │ │ - [ 131f1] ._ │ │ - [ 131f4] .AppleDouble/ │ │ - [ 13202] multi-masters │ │ - [ 13210] BlueFuzz │ │ - [ 13219] MinFeature │ │ - [ 13224] StrokeWidth │ │ - [ 13230] BlendAxisTypes │ │ - [ 1323f] XUID │ │ - [ 13244] Bold Italic │ │ - [ 13250] ADD_STYLE_NAME │ │ - [ 1325f] AVG_CAPITAL_WIDTH │ │ - [ 13271] DEFAULT_CHAR │ │ - [ 1327e] RAW_CAP_HEIGHT │ │ - [ 13290] � │ │ - [ 13295] StartKernPairs │ │ - [ 132a4] upval │ │ - [ 132aa] k │ │ - [ 132ac] && │ │ - [ 132af] luaopen_%s │ │ - [ 132ba] external hook │ │ - [ 132c9] 32bit^Cfpu^Fsoftfp^Deabi^Ble │ │ - [ 132e2] png_image_begin_read_from_file: invalid argument │ │ - [ 13313] missing IHDR │ │ - [ 13320] hIST must be after │ │ - [ 13333] too many profiles │ │ - [ 13345] iCCP: invalid keyword │ │ - [ 1335b] SPICE(INVALIDSIZE) │ │ - [ 1336e] SPICE(INVALIDCLUSTERNUM) │ │ - [ 13387] SPICE(INVALIDOPTION) │ │ - [ 1339c] SPICE(PATHTOOLONG) │ │ - [ 133af] itbeg │ │ - [ 133b5] ithfs │ │ - [ 133bb] Number of files loaded is at a maximum, as specified by the parameter FTSIZE, the value of which is #. You will need to either load fewer files, or change the parameter FTSIZE. │ │ - [ 1346c] SPICE(NOLOADEDFILES) │ │ - [ 13481] NI was #, should be in range [2,#]. │ │ - [ 134a5] internal │ │ - [ 134ae] No record, word for address #. │ │ - [ 134cd] DAFBFS │ │ - [ 134d4] DAFFNA │ │ - [ 134db] Character record write failed. Value of IOSTAT was # │ │ - [ 13510] stncol │ │ - [ 13517] EKCCNT │ │ - [ 1351e] sizes │ │ - [ 13524] The number of comment records allocated must be non-negative but was #. │ │ - [ 1356c] lastrc │ │ - [ 13573] SPICE(DASNOSUCHHANDLE) │ │ - [ 1358a] rcbufd │ │ - [ 13591] SPICE(INVALIDNODE) │ │ - [ 135a4] r+b │ │ - [ 135a8] malloc failure │ │ - [ 135b7] btchkp │ │ - [ 135be] pckbsr_ │ │ - [ 135c6] btruex │ │ - [ 135cd] pool_ │ │ - [ 135d3] The watched kernel variable name list WTVARS has room for # more elements, so the # new names (in a list of # names) associated with agent # cannot be inserted. │ │ - [ 13674] J2000 │ │ - [ 1367a] FRAME_ │ │ - [ 13681] SPICE(NONEXISTELEMENTS) │ │ - [ 13699] SPICE(PASTENDSTR) │ │ - [ 136ab] SPICE(BADSUBSTR) │ │ - [ 136bc] CONVRT: Input units │ │ - [ 136d1] type: │ │ - [ 136d8] agent │ │ - [ 136de] cks │ │ - [ 136e2] CKR01 │ │ - [ 136e8] DAFGDA │ │ - [ 136ef] SPICE(BADQUATSIGN) │ │ - [ 13702] SPICE(NOTAROTATION) │ │ - [ 13716] rd_ed, unexpected code: %d\n │ │ - [ 13732] OUTMSG: An invalid message type was specified in the type list. │ │ - [ 13774] SPICE(INVALIDFORMAT) │ │ - [ 13789] DAFETF │ │ - [ 13790] 'NAIF/DAF' │ │ - [ 1379b] The input record has a maximum table dimension of #, while the maximum supported by this routine is #. It is possible that this problem is due to your SPICE Toolkit being out of date. │ │ - [ 13853] LGRESP │ │ - [ 1385a] SPKR14 │ │ - [ 13861] Both kernel variables # and # are present in the kernel pool. At most one form of the kernel variable name may be present. │ │ - [ 138dc] PCKE02 │ │ - [ 138e3] SCREEN │ │ - [ 138ea] frozen │ │ - [ 138f1] & │ │ - [ 138f3] WRLINE: File = │ │ - [ 13903] list in │ │ - [ 1390b] bltnam │ │ - [ 13912] SPICE(HANDLENOTFOUND) │ │ - [ 13928] ZZDASNFR │ │ - [ 13931] ZZDDHHLU │ │ - [ 1393a] The binary file format, '#', is not supported by this version of the toolkit. This is a serious problem, contact NAIF. │ │ - [ 139bd] Attempt to open file '#' failed. Value of IOSTAT was #. │ │ - [ 139f5] SPICE(UNKNOWNFILARC) │ │ - [ 13a0a] itmaxe │ │ - [ 13a11] itmunt │ │ - [ 13a18] VECTOR │ │ - [ 13a1f] NUT_MODEL │ │ - [ 13a29] OBLIQ_MODEL │ │ - [ 13a35] nearpt_ │ │ - [ 13a3d] axisqr │ │ - [ 13a44] Norm of scaled point is 0. POSITN = ( #, #, # ) │ │ - [ 13a74] zzekjtst_ │ │ - [ 13a7e] idxset │ │ - [ 13a85] ZZEKLLED │ │ - [ 13a8e] SPICE(DASNOTEMPTY) │ │ - [ 13aa1] ZZEKRSD │ │ - [ 13aa9] ZZEKRD01 │ │ - [ 13ab2] Key = #; valid range = 1:#. Tree = #, file = # │ │ - [ 13ae1] An attempt to create a temporary string array failed. Attempted to allocate # bytes. │ │ - [ 13b37] An attempt to copy a string using C2F_StrCpy failed. │ │ - [ 13b6c] There is an inconsistency between the version of the routine calling ZZFDAT and the current version of ZZFDAT. Check to make sure that you have the most current versions of ZZFDAT and the routines that make use of it. │ │ - [ 13c46] IAU_UMBRIEL │ │ - [ 13c52] IAU_GALATEA │ │ - [ 13c5e] IAU_EURYBATES │ │ - [ 13c6c] zzdynfr0_ │ │ - [ 13c76] SPICE(INVALIDDIVISOR) │ │ - [ 13c8c] EARTH_BARYCENTER │ │ - [ 13c9d] LEDA │ │ - [ 13ca2] THYONE │ │ - [ 13ca9] HEGEMONE │ │ - [ 13cb2] HERSE │ │ - [ 13cb8] CALYPSO │ │ - [ 13cc0] HATI │ │ - [ 13cc5] LOGE │ │ - [ 13cca] DESPINA │ │ - [ 13cd2] LADEE │ │ - [ 13cd8] P10 │ │ - [ 13cdc] PIONEER-11 │ │ - [ 13ce7] JANUS_B │ │ - [ 13cef] TROPICAL RAINFALL MEASURING MISSION │ │ - [ 13d13] ICE │ │ - [ 13d17] CASP │ │ - [ 13d1c] MARTIAN MOONS EXPLORATION │ │ - [ 13d36] SELENE VLBI Radio Satellite │ │ - [ 13d52] SHOEMAKER-LEVY 9-E │ │ - [ 13d65] RUSSELL 3 │ │ - [ 13d6f] SCHAUMASSE │ │ - [ 13d7a] SINGER-BREWSTER │ │ - [ 13d8a] HOLT-OLMSTEAD │ │ - [ 13d98] DSS-27 │ │ - [ 13d9f] xmit │ │ - [ 13da4] TPARSE does not support the specification of a time system in a string. The time system # was specified. │ │ - [ 13e0f] *w* │ │ - [ 13e13] The year value was #. This must be an integral value. │ │ - [ 13e4b] YMD │ │ - [ 13e50] SPICE(BADTIMEBOUNDS) │ │ - [ 13e65] YDF │ │ - [ 13e69] YMDF │ │ - [ 13e6e] SPICE(BADPICTURE) │ │ - [ 13e80] UTC-Offset indicator │ │ - [ 13e95] JANUARY │ │ - [ 13e9d] The input time string is blank. │ │ - [ 13ebd] │ │ - [ 13ec3] Y-it │ │ - [ 13ec8] YmDH*M*S │ │ - [ 13ed1] Yiiiii │ │ - [ 13ed8] i:i:nimY │ │ - [ 13ee1] mDYH*M │ │ - [ 13ee8] imYi:i │ │ - [ 13eef] i/i/Yi:i:n │ │ - [ 13efa] mo │ │ - [ 13efd] zh_GAN │ │ - [ 13f04] be │ │ - [ 13f07] bgn │ │ - [ 13f0b] fil │ │ - [ 13f0f] goh │ │ - [ 13f13] hil │ │ - [ 13f17] kaw │ │ - [ 13f1b] ky │ │ - [ 13f1e] lzh │ │ - [ 13f22] mai │ │ - [ 13f26] mde │ │ - [ 13f2a] mh │ │ - [ 13f2d] mn │ │ - [ 13f30] srr │ │ - [ 13f34] su │ │ - [ 13f37] ve │ │ - [ 13f3a] xnr │ │ - [ 13f3e] zun │ │ - [ 13f42] fao │ │ - [ 13f46] hun │ │ - [ 13f4a] ndo │ │ - [ 13f4e] slk │ │ - [ 13f52] tgk │ │ - [ 13f56] tso │ │ - [ 13f5a] tah │ │ - [ 13f5e] BH │ │ - [ 13f61] IC │ │ - [ 13f64] KY │ │ - [ 13f67] SJ │ │ - [ 13f6a] SX │ │ - [ 13f6d] TN │ │ - [ 13f70] AUS │ │ - [ 13f74] AZE │ │ - [ 13f78] BDI │ │ - [ 13f7c] COK │ │ - [ 13f80] CMR │ │ - [ 13f84] CYM │ │ - [ 13f88] LBY │ │ - [ 13f8c] STP │ │ - [ 13f90] UZB │ │ - [ 13f94] ZAF │ │ - [ 13f98] uprv_copyEbcdic() string[%] contains a variant character in position %d\n │ │ - [ 13fe1] es_ES │ │ - [ 13fe7] km_KH │ │ - [ 13fed] lo_LA │ │ - [ 13ff3] yue_Hant_HK │ │ - [ 13fff] metadata │ │ - [ 14008] Asia/Anadyr │ │ - [ 14014] Asia/Yakutsk │ │ - [ 14021] Asia/Ulaanbaatar │ │ - [ 14032] AZT │ │ - [ 14036] WET │ │ - [ 1403a] BRST │ │ - [ 1403f] America/Cuiaba │ │ - [ 1404e] US/Central │ │ - [ 14059] PSACCENT │ │ - [ 14062] PSCRACK │ │ - [ 1406a] partitions │ │ - [ 14075] en_PH │ │ - [ 1407b] gd_GB │ │ - [ 14081] it_CH │ │ - [ 14087] ms_BN │ │ - [ 1408d] qu_PE │ │ - [ 14093] ur_IN │ │ - [ 14099] i-ami │ │ - [ 1409f] sgn-br │ │ - [ 140a6] ncs │ │ - [ 140aa] dse │ │ - [ 140ae] zh-cmn-hans │ │ - [ 140ba] zh-wuu │ │ - [ 140c1] ucnv_unload │ │ - [ 140cd] ucol_openFromShortString │ │ - [ 140e6] layout │ │ - [ 140ed] TZVersion │ │ - [ 140f7] uchar_swapNames(): too few bytes (%d after header) for unames.icu\n │ │ - [ 1413a] udict_swap(): too few bytes (%d after header) for all of dictionary data\n │ │ - [ 14184] U_ZERO_ERROR │ │ - [ 14191] U_INTERNAL_PROGRAM_ERROR │ │ - [ 141aa] U_BUFFER_OVERFLOW_ERROR │ │ - [ 141c2] U_ILLEGAL_ESCAPE_SEQUENCE │ │ - [ 141dc] U_MISMATCHED_SEGMENT_DELIMITERS │ │ - [ 141fc] U_UNSUPPORTED_ATTRIBUTE │ │ - [ 14214] U_MF_SELECTOR_ERROR │ │ - [ 14228] U_BRK_RULE_SYNTAX │ │ - [ 1423a] U_REGEX_PROPERTY_SYNTAX │ │ - [ 14252] U_REGEX_UNIMPLEMENTED │ │ - [ 14268] currencyNumericCodes │ │ - [ 1427d] CNY │ │ - [ 14281] ETB │ │ - [ 14285] KMF │ │ - [ 14289] KRO │ │ - [ 1428d] KYD │ │ - [ 14291] THB │ │ - [ 14295] TMT │ │ - [ 14299] XCG │ │ - [ 1429d] typeOffsets │ │ - [ 142a9] M10L │ │ - [ 142ae] @calendar=ethiopic │ │ - [ 142c1] digital │ │ - [ 142c9] speed │ │ - [ 142cf] millimole-per-liter │ │ - [ 142e3] ZWN │ │ - [ 142e7] millimeter │ │ - [ 142f2] yard │ │ - [ 142f7] kilogram │ │ - [ 14300] centiliter │ │ - [ 1430b] cubic-centimeter │ │ - [ 1431c] personal │ │ - [ 14325] any │ │ - [ 14329] zepto │ │ - [ 1432f] grammaticalFeatures │ │ - [ 14343] UCARules │ │ - [ 1434c] AMU │ │ - [ 14350] ATrace_setCounter │ │ - [ 14362] preferredRefreshPeriod │ │ - [ 14379] Alt-azimuth mode disabled │ │ - [ 14393] Time and script are paused │ │ - [ 143ae] High res textures │ │ - [ 143c0] Unknown script system access policy {}\n │ │ - [ 143e8] invalid precision │ │ - [ 143fa] negative precision │ │ - [ 1440d] AsterismsFile │ │ - [ 1441b] HDCrossIndex │ │ - [ 14428] WarpMeshFile │ │ - [ 14435] FocusZooming │ │ - [ 14442] R │ │ - [ 14444] angle │ │ - [ 1444a] true\n │ │ - [ 14450] "\n │ │ - [ 14453] Travelling ({})\n │ │ - [ 14464] seconds │ │ - [ 1446c] Mass: {} lb\n │ │ - [ 14479] Error reading {} catalog file: {}\n │ │ - [ 1449c] Failed to load library: %s\n │ │ - [ 144b8] Failed to initialize mutex for device info retrieval. ma_context_get_device_info() is not thread safe.\n │ │ - [ 14520] Passthrough: %s\n │ │ - [ 14542] CHANNEL_AUX_3 │ │ - [ 14550] CHANNEL_AUX_14 │ │ - [ 1455f] Format not supported │ │ - [ 14574] WASAPI │ │ - [ 1457b] SL_IID_AUDIOIODEVICECAPABILITIES │ │ - [ 1459c] {:%c} │ │ - [ 145a2] {:%Y %b %d %H:%M:%S %Z} │ │ - [ 145ba] darkolivegreen │ │ - [ 145c9] lightgreen │ │ - [ 145d4] lightseagreen │ │ - [ 145e2] mediumvioletred │ │ - [ 145f2] purple │ │ - [ 145f9] yellowgreen │ │ - [ 14605] .tga │ │ - [ 14610] labes │ │ - [ 14616] ring │ │ - [ 1461b] Time │ │ - [ 14620] magnitude │ │ - [ 1462a] getaltazimuthmode │ │ - [ 1463c] hidelabel │ │ - [ 14646] fromjulianday │ │ - [ 14654] runscript │ │ - [ 1465e] settimeslice │ │ - [ 1466b] Argument to celestia:setlabelflags() must be a table │ │ - [ 146a0] Keys in table-argument to celestia:setlabelflags() must be strings │ │ - [ 146e3] Wrong number of arguments to function celestia:tojulianday │ │ - [ 1471e] Third arg to celestia:utctotdb must be a number │ │ - [ 1474e] newframe: one object argument required for frame │ │ - [ 1477f] First arg to celestia:newvector must be a number │ │ - [ 147b0] Argument to celestia:setwindowbordersvisible must be a boolean │ │ - [ 147ef] One argument expected to function celestia:verbosity │ │ - [ 14824] First argument for celestia:isplayingaudio must be a number │ │ - [ 14860] First argument for celestia:stopaudio must be a number │ │ - [ 14897] First argument for celestia:setaudioloop must be a number │ │ - [ 148d1] Second argument for celestia:setaudioloop must be a boolean │ │ - [ 1490d] One argument expected to function celestia:log │ │ - [ 1493c] Error while executing tick callback: {}\n │ │ - [ 14965] celestia │ │ - [ 1496e] PROJECTION │ │ - [ 14979] No arguments expected for font:bind() │ │ - [ 1499f] No arguments expected for font:getmaxascent() │ │ - [ 149cd] setorbitvisibility │ │ - [ 149e0] No arguments expected to object:orbitvisibility │ │ - [ 14a10] atmosphereCloudHeight │ │ - [ 14a26] Sixth argument to object:mark must be a boolean │ │ - [ 14a56] skycolor │ │ - [ 14a5f] Value of {} must be number │ │ - [ 14a7a] isvalid │ │ - [ 14a82] Last argument to observer:lookat must be of type vector │ │ - [ 14aba] No arguments expected to observer:getposition │ │ - [ 14ae8] Vector components must be numbers │ │ - [ 14b0a] Merged similar meshes: {} -> {}.\n │ │ - [ 14b2c] end_material │ │ - [ 14b39] jpl-earth-sun │ │ - [ 14b47] mars-sun │ │ - [ 14b50] jpl-mercury-ssb │ │ - [ 14b60] vsop87-mercury │ │ - [ 14b6f] mercury-jpl │ │ - [ 14b7b] iau-prometheus │ │ - [ 14b8a] iau-ganymede │ │ - [ 14b97] earth-p03lp │ │ - [ 14ba3] ScriptedOrbit generator function returned bad value.\n │ │ - [ 14bd9] viewMat │ │ - [ 14be1] Crt │ │ - [ 14be5] Cru │ │ - [ 14be9] AbsMag │ │ - [ 14bf0] SC │ │ - [ 14bf3] SampledTrajectory │ │ - [ 14c05] EllipticalOrbit │ │ - [ 14c15] RotationOffset │ │ - [ 14c24] {}_vert.glsl │ │ - [ 14c31] /***************************************************\n │ │ - [ 14c67] diff │ │ - [ 14c6c] ringWidth │ │ - [ 14c76] #extension GL_ARB_shader_texture_lod : enable\n │ │ - [ 14ca5] shininess │ │ - [ 14caf] vec4 diff = vec4(ambientColor, opacity);\n │ │ - [ 14cd9] * │ │ - [ 14cdd] set_vp(vec4(position.xyz, 1.0));\n │ │ - [ 14cff] position = in_Position.xyz;\n │ │ - [ 14d20] v_TexCoord0.st = │ │ - [ 14d36] rayleighH │ │ - [ 14d40] sampler2D │ │ - [ 14d4a] Fragment shader source:\n │ │ - [ 14d63] shadow *= 1.0 - shadowR;\n │ │ - [ 14d7d] Oblateness │ │ - [ 14d88] Sunset │ │ - [ 14d8f] LunarLambert │ │ - [ 14d9c] OrbitBarycenter cycle detected │ │ - [ 14dbb] AbsMag ignored on Barycenter │ │ - [ 14dd8] Extinction │ │ - [ 14de3] Extinction ignored for stars close to the origin │ │ - [ 14e14] tex │ │ - [ 14e18] Error reading PNG image file {}\n │ │ - [ 14e39] Failed to read chunk type\n │ │ - [ 14e54] Chunk size {} too small to include header\n │ │ - [ 14e7f] Failed to read element {} of mesh matrix\n │ │ - [ 14ea9] Content size {} too small to include float color\n │ │ - [ 14edb] Processing IntPercentage chunk\n │ │ - [ 14efb] ()J │ │ - [ 14eff] zh_CN │ │ - [ 14f05] boolean │ │ - [ 14f0d] startTime │ │ - [ 14f17] flushTasks │ │ - [ 14f22] GL_ARB_shading_language_100 │ │ - [ 14f3e] Missing Huffman code table entry │ │ - [ 14f5f] Empty input file │ │ - [ 14f70] Scan script does not transmit all data │ │ - [ 14f97] End Of Image │ │ - [ 14fa4] RST%d │ │ - [ 14faa] Component %d: dc=%d ac=%d │ │ - [ 14fc8] Corrupt JPEG data: %u extraneous bytes before marker 0x%02x │ │ - [ 15004] adobe │ │ - [ 1500a] ItalicAngle │ │ - [ 15016] isFixedPitch │ │ - [ 15023] lenIV │ │ - [ 15029] %!PS-Adobe-3.0 Resource-CIDFont │ │ - [ 15049] FACE_NAME │ │ - [ 15053] QUAD_WIDTH │ │ - [ 1505e] SUPERSCRIPT_X │ │ - [ 1506f] � � │ │ - [ 15084] � │ │ - [ 15089] StartAxis │ │ - [ 15093] 0123456789abcdefpx │ │ - [ 150a6] if │ │ - [ 150a9] in │ │ - [ 150ac] ... │ │ - [ 150b0] union │ │ - [ 150b6] %s at line %d │ │ - [ 150c4] inconsistent rendering intents │ │ - [ 150e3] internal error handling cHRM->XYZ │ │ - [ 15105] inconsistent chromaticities │ │ - [ 15121] Missing PLTE before IDAT │ │ - [ 1513a] png_start_read_image/png_read_update_info: duplicate call │ │ - [ 15174] gray+alpha color-map: too few entries │ │ - [ 1519a] non-positive width │ │ - [ 151ad] bad height format │ │ - [ 151bf] Invalid sCAL width ignored │ │ - [ 151da] png_image_write_to_file: incorrect PNG_IMAGE_VERSION │ │ - [ 1520f] Writing zero-length unknown chunk │ │ - [ 15231] memory image too large │ │ - [ 15248] ICC profile too short │ │ - [ 1525e] tEXt: invalid keyword │ │ - [ 15274] deflateEnd failed (ignored) │ │ - [ 15290] erract_c │ │ - [ 15299] furnsh_c │ │ - [ 152a2] Invalid Endpoints--Left Endpoint Exceeds Right Endpoint │ │ - [ 152da] SPICE(DATATYPENOTRECOG) │ │ - [ 152f2] Invalid embedded blank was found in character string │ │ - [ 15327] SPICE(INVALIDCHECKOUT) │ │ - [ 1533e] Specification of Time String Format Was Not Recognized │ │ - [ 15375] Window Does Not Contain Interval Corresponding to the Supplied Index │ │ - [ 153ba] SPICE(UNITSNOTREC) │ │ - [ 153cd] Cardinality of Output Window is Too Small │ │ - [ 153f7] Input Vector is the Zero Vector │ │ - [ 15417] kdata_c │ │ - [ 1541f] PATH_SYMBOLS │ │ - [ 1542c] In meta-kernel <#>, the file name at index # in the KERNELS_TO_LOAD list has length # characters; the limit is # characters. │ │ - [ 154a9] DSK │ │ - [ 154ad] SPICE(CKBOGUSENTRY) │ │ - [ 154c1] invalid array section │ │ - [ 154d7] %s: %s\n │ │ - [ 154df] COPYI │ │ - [ 154e5] TABLE_LIST_FULL │ │ - [ 154f5] cnams │ │ - [ 154fb] The EK file # could not be loaded; the maximum number of columns havingdistinct attributes has already been reached. │ │ - [ 15570] ldrec │ │ - [ 15576] Attempt to update file record failed. File was '#'. Value of IOSTAT was '#'. │ │ - [ 155c4] SPICE(INVALIDHANDLE) │ │ - [ 155d9] dasa2l_ │ │ - [ 155e1] SPICE(DASNOSUCHADDRESS) │ │ - [ 155f9] DASWBR │ │ - [ 15600] EXPOOL │ │ - [ 15607] uvalue │ │ - [ 1560e] eqchr_ │ │ - [ 15615] typeid │ │ - [ 1561c] REPMOT │ │ - [ 15623] ONE │ │ - [ 15627] TWELFTH │ │ - [ 1562f] REPSUB error: LEFT (#) must not be less than 1. │ │ - [ 1565f] [ │ │ - [ 15661] SCLK │ │ - [ 15666] CKE05 │ │ - [ 1566c] yvals │ │ - [ 15672] , │ │ - [ 15674] frmchg_ │ │ - [ 1567c] dpjan0 │ │ - [ 15683] Epoch before │ │ - [ 15691] wc │ │ - [ 15694] The eccentricity supplied for a type 15 segment is negative. It must be non-negative. The value supplied to the type 15 evaluator was #. │ │ - [ 1571f] body-fixed frame │ │ - [ 15730] ; popped name is │ │ - [ 15742] JDTDT │ │ - [ 15748] Relational operator, *, is not recognized. │ │ - [ 15773] vhatg_ │ │ - [ 1577a] WRLINE: Maximum number of logical units that can be allocated by SPICELIB has already been reached │ │ - [ 157dd] no comma │ │ - [ 157e6] drdtrt │ │ - [ 157ed] The block size is not positive. The block size is #. │ │ - [ 15822] defcod │ │ - [ 15829] There is no room available for adding '#' to the list of name/code pairs. The number of names that can be supported is #. This number has been reached. │ │ - [ 158c4] zzdafgfr_ │ │ - [ 158ce] ZZDASGRD │ │ - [ 158d7] Attempt to open file, '$' for % access failed. IOSTAT was #. │ │ - [ 15914] Attempt to open file, '#', for write access has failed. This file utilizes an unknown binary file format. This error may result from attempting to open a corrupt file or one of an unknown type. │ │ - [ 159d8] ZZDDHRMU │ │ - [ 159e1] itmvec │ │ - [ 159e8] Definition of frame # specifies frame center # and obliquity model #. This obliquity model is not applicable to body #. This situation is usually caused by an error in a frame kernel in which the frame is defined. │ │ - [ 15abf] coeffs │ │ - [ 15ac6] ZZDYNFID │ │ - [ 15acf] ? │ │ - [ 15ad3] SPICE(NOCLASS) │ │ - [ 15ae2] ZZEKIXLK │ │ - [ 15aeb] Number tables in first join row set was #; valid range is 1:# │ │ - [ 15b29] zzekjsqz_ │ │ - [ 15b33] Constraint index # is out of valid range 1:#. │ │ - [ 15b61] The relational operator # was not recognized or was not applicable for data type #. │ │ - [ 15bb5] IAU_TAYGETE │ │ - [ 15bc1] IAU_STEINS │ │ - [ 15bcc] MOON │ │ - [ 15bd1] ANANKE │ │ - [ 15bd8] METIS │ │ - [ 15bde] AUTONOE │ │ - [ 15be6] NEPTUNE │ │ - [ 15bee] P6 │ │ - [ 15bf1] MAGELLAN │ │ - [ 15bfa] LCROSS │ │ - [ 15c01] LUCY │ │ - [ 15c06] CHANDRAYAAN-1 │ │ - [ 15c14] TRMM │ │ - [ 15c19] EXM RSP SP │ │ - [ 15c24] GLL PROBE │ │ - [ 15c2e] CROMMELIN │ │ - [ 15c38] PONS-WINNECKE │ │ - [ 15c46] WIRTANEN │ │ - [ 15c4f] MUELLER 2 │ │ - [ 15c59] DAVIDA │ │ - [ 15c60] PARKES │ │ - [ 15c67] SPICE(NOSUCHFILE) │ │ - [ 15c79] ZZPRSCOR │ │ - [ 15c82] ZZREFCH1 │ │ - [ 15c8b] There is a quoted string with no characters on line # of the text kernel file '#'. │ │ - [ 15cdf] Encountered '#' while attempting to parse a time on line # of the text kernel file '#'. Error message: '#' │ │ - [ 15d4b] miY> │ │ - [ 15d50] imY │ │ - [ 15d54] Field count was not found for SCLK #. │ │ - [ 15d7a] The routine ZZSGP4 is an umbrella for the SGP4 initializer and propagator entry points. Do not call ZZSGP4. It is likely that a programming error has been made. │ │ - [ 15e1b] daytab │ │ - [ 15e22] The string supplied to specify the reference frame, ('#') contains non-printing characters. The two most common causes for this kind of error are: 1. an error in the call to ZZSPKGO0; 2. an uninitialized variable. │ │ - [ 15efa] ZZSWFINI │ │ - [ 15f03] FRAME_#_START │ │ - [ 15f11] SPICE(TOOMANYBASEFRAMES) │ │ - [ 15f2a] Start time kernel variable # exists but DTPOOL returned data type # rather than one of the expected values: 'C' or 'N'. │ │ - [ 15fa2] The Year may be abbreviated only if the year belongs to the Christian Era (A.D.) │ │ - [ 15ff4] The default value assigned to the time system must be one of 'UTC', 'TDT', 'TT', or 'TDB'. The value supplied was '#'. │ │ - [ 1606c] SPICE(OUTPUTTOOSHORT) │ │ - [ 16082] Day of Month │ │ - [ 1608f] An unexpected # ("#") was encountered in the time string: │ │ - [ 160ca] Two substrings indicating a day of year were identified in the input time string <#> and <#>: " │ │ - [ 1612a] A month was identified in the time string "#", but a day of month could not be identified. │ │ - [ 16186] Yiii:n │ │ - [ 1618d] YDm │ │ - [ 16191] i-Ydi:i │ │ - [ 16199] i:iimY │ │ - [ 161a0] iiYi:n │ │ - [ 161a7] i/i/Y/i:n │ │ - [ 161b1] Y*m*D*H*M* │ │ - [ 161bc] Y*y*H* │ │ - [ 161c3] angrt │ │ - [ 161c9] collation │ │ - [ 161d3] NH │ │ - [ 161d6] hsn │ │ - [ 161da] ar │ │ - [ 161dd] ary │ │ - [ 161e1] bas │ │ - [ 161e5] bo │ │ - [ 161e8] br │ │ - [ 161eb] ckb │ │ - [ 161ef] fo │ │ - [ 161f2] frr │ │ - [ 161f6] jrb │ │ - [ 161fa] kab │ │ - [ 161fe] kfo │ │ - [ 16202] kho │ │ - [ 16206] khq │ │ - [ 1620a] kmb │ │ - [ 1620e] lag │ │ - [ 16212] lfn │ │ - [ 16216] lij │ │ - [ 1621a] mdr │ │ - [ 1621e] nwc │ │ - [ 16222] pau │ │ - [ 16226] pfl │ │ - [ 1622a] sli │ │ - [ 1622e] tly │ │ - [ 16232] zap │ │ - [ 16236] zgh │ │ - [ 1623a] ces │ │ - [ 1623e] hin │ │ - [ 16242] nbl │ │ - [ 16246] BM │ │ - [ 16249] BW │ │ - [ 1624c] GA │ │ - [ 1624f] KE │ │ - [ 16252] MW │ │ - [ 16255] MX │ │ - [ 16258] PS │ │ - [ 1625b] RW │ │ - [ 1625e] SL │ │ - [ 16261] AGO │ │ - [ 16265] CAF │ │ - [ 16269] CRQ │ │ - [ 1626d] CRI │ │ - [ 16271] SGS │ │ - [ 16275] HND │ │ - [ 16279] IDN │ │ - [ 1627d] IRL │ │ - [ 16281] ISL │ │ - [ 16285] JEY │ │ - [ 16289] MLI │ │ - [ 1628d] QAT │ │ - [ 16291] SAU │ │ - [ 16295] SYR │ │ - [ 16299] fil_PH │ │ - [ 162a0] variant │ │ - [ 162a8] __system_property_get │ │ - [ 162be] YAKST │ │ - [ 162c4] Asia/Baku │ │ - [ 162ce] BST │ │ - [ 162d2] America/Scoresbysund │ │ - [ 162e7] Canada/Atlantic │ │ - [ 162f7] en_MH │ │ - [ 162fd] es_CO │ │ - [ 16303] mn_Cyrl │ │ - [ 1630b] qu_BO │ │ - [ 16311] tt_RU │ │ - [ 16317] yi_001 │ │ - [ 1631e] i-enochian │ │ - [ 16329] csn │ │ - [ 1632d] sgn-dk │ │ - [ 16334] sgn-ie │ │ - [ 1633b] psr │ │ - [ 1633f] ures_swap().udata_swapInvStringBlock(keys[%d]) failed\n │ │ - [ 16376] ures_swapResource(array res=%08x)[%d].recurse(%08x) failed\n │ │ - [ 163b2] ucol_swap(formatVersion=4): unknown data at IX_RESERVED10_OFFSET\n │ │ - [ 163f4] supplementalData │ │ - [ 16405] icudt75l-curr │ │ - [ 16413] U_MESSAGE_PARSE_ERROR │ │ - [ 16429] U_MF_UNSUPPORTED_EXPRESSION_ERROR │ │ - [ 1644b] AOK │ │ - [ 1644f] ARA │ │ - [ 16453] BGL │ │ - [ 16457] CNX │ │ - [ 1645b] IRR │ │ - [ 1645f] LUC │ │ - [ 16463] LYD │ │ - [ 16467] MVR │ │ - [ 1646b] OMR │ │ - [ 1646f] RSD │ │ - [ 16473] RUR │ │ - [ 16477] SKK │ │ - [ 1647b] SLL │ │ - [ 1647f] XFU │ │ - [ 16483] date │ │ - [ 16488] INFINITY │ │ - [ 16491] dunam │ │ - [ 16497] AYM │ │ - [ 1649b] CSJ │ │ - [ 1649f] ZWC │ │ - [ 164a3] dot-per-inch │ │ - [ 164b0] atmosphere │ │ - [ 164bb] acre-foot │ │ - [ 164c5] cubic-inch │ │ - [ 164d0] gallon-imperial │ │ - [ 164e0] tablespoon │ │ - [ 164eb] genitive │ │ - [ 164f4] few │ │ - [ 164f8] ronto │ │ - [ 164fe] Week │ │ - [ 16503] -short │ │ - [ 1650a] -narrow │ │ - [ 16512] grouping │ │ - [ 1651b] reset secondary-before secondary ignorable not possible │ │ - [ 16553] secondary tailoring gap too small │ │ - [ 16575] alternateQuotationStart │ │ - [ 1658d] ()F │ │ - [ 16591] Anti-aliasing disabled │ │ - [ 165a8] Auto-magnitude disabled │ │ - [ 165c0] Could not find locale, falling back to classic.\n │ │ - [ 165f1] format specifier requires numeric argument │ │ - [ 1661c] cannot switch from manual to automatic argument indexing │ │ - [ 16655] StarTextures │ │ - [ 16662] A │ │ - [ 16664] Distance │ │ - [ 1666d] km │ │ - [ 16670] base │ │ - [ 16675] Depth component: %s\n │ │ - [ 1668a] Max anisotropy filtering: %s\n │ │ - [ 166a8] F11 Start/Pause F12 Stop │ │ - [ 166c4] catalog^Ddeep sky │ │ - [ 166d5] star │ │ - [ 166da] 0.11.21 │ │ - [ 166e2] Buffer Size: %d*%d (%d)\n │ │ - [ 166ff] CHANNEL_SIDE_LEFT │ │ - [ 16711] Invalid file │ │ - [ 1671e] Memory already mapped │ │ - [ 16734] SL_IID_ANDROIDCONFIGURATION │ │ - [ 16750] [OpenSL] Cannot find symbol slCreateEngine. │ │ - [ 1677c] &ver= │ │ - [ 16782] oy │ │ - [ 16785] crimson │ │ - [ 1678d] cyan │ │ - [ 16792] darkslategray │ │ - [ 167a0] lime │ │ - [ 167a5] midnightblue │ │ - [ 167b2] orangered │ │ - [ 167bc] {}{} │ │ - [ 167c1] "/:<>?\| │ │ - [ 167ca] ecliptic │ │ - [ 167d3] insula │ │ - [ 167da] sulcus │ │ - [ 167e1] selectioncursor │ │ - [ 167f1] capture │ │ - [ 167f9] timerate │ │ - [ 16802] orbit │ │ - [ 16808] xrot │ │ - [ 1680d] render │ │ - [ 16814] requestkeyboard │ │ - [ 16824] findcategory │ │ - [ 16831] Bad method call! │ │ - [ 16842] fuzzy │ │ - [ 16848] screenshot-{}{:06i} │ │ - [ 1685c] mousedown │ │ - [ 16866] l │ │ - [ 16868] Internal Error: Invalid table entry in checkTimeslice │ │ - [ 1689e] Timeout: script hasn't returned control to celestia (forgot to call wait()?) │ │ - [ 168eb] to │ │ - [ 168ee] Position or rotation expected as second argument to frame:from() │ │ - [ 1692f] Frustum │ │ - [ 16937] argument 1 to gl.TexParameter must be a number │ │ - [ 16966] argument 2 to gl.TexParameter must be a number │ │ - [ 16995] argument 1 to gl.BlendFunc must be a number │ │ - [ 169c1] removereferencemark │ │ - [ 169d5] bodyframe │ │ - [ 169df] setatmosphere │ │ - [ 169ed] location │ │ - [ 169f6] dwarfplanet │ │ - [ 16a02] parent │ │ - [ 16a09] Argument to object:catalognumber must be a string │ │ - [ 16a3b] getframe │ │ - [ 16a44] makeactiveview │ │ - [ 16a53] timespan │ │ - [ 16a5c] Internal error: couldn't get metatable │ │ - [ 16a83] setaxisangle │ │ - [ 16a90] No arguments expected for vector:gety │ │ - [ 16ab6] Unknown error loading hook script │ │ - [ 16ad8] texcoord2 │ │ - [ 16ae2] linestrip │ │ - [ 16aec] diffuse {} {} {}\n │ │ - [ 16afe] normal\n │ │ - [ 16b06] mimas │ │ - [ 16b0c] jpl-earth-emb │ │ - [ 16b1a] jpl-pluto-ssb │ │ - [ 16b28] iau-phobos │ │ - [ 16b33] Unsupported byte order {}, expected {} in {}.\n │ │ - [ 16b62] tidalSize │ │ - [ 16b6c] scale │ │ - [ 16b72] largestar │ │ - [ 16b7c] Cnc │ │ - [ 16b80] PsA │ │ - [ 16b84] Sge │ │ - [ 16b88] .* │ │ - [ 16b8b] Open cluster │ │ - [ 16b98] Bad spice orbit\n │ │ - [ 16ba9] Missing coordinates for FixedPosition\n │ │ - [ 16bd0] RelativeVelocity │ │ - [ 16be1] vec3 ringShadowProj;\n │ │ - [ 16bf7] float NV = dot(N, eyeDir);\n │ │ - [ 16c13] vec3 H;\n │ │ - [ 16c1c] totalLight += l * │ │ - [ 16c2f] vec4 overlayColor = texture2D(overlayTex, overlayTexCoord.st);\n │ │ - [ 16c6f] scatterEx │ │ - [ 16c79] gl_FragColor.rgb = gl_FragColor.rgb * scatterEx + scatterColor;\n │ │ - [ 16cba] shadowCenter │ │ - [ 16cc7] mieK │ │ - [ 16ccc] pointFade = 1.0;\n │ │ - [ 16cde] line_strip │ │ - [ 16ce9] ReferencePoint │ │ - [ 16cf8] No valid orbit specified for object '{}'. Skipping.\n │ │ - [ 16d2d] Error: Beginning can only be specified for initial phase of timeline.\n │ │ - [ 16d74] Lower │ │ - [ 16d7a] Inner │ │ - [ 16d80] BumpHeight │ │ - [ 16d8b] III │ │ - [ 16d8f] Texture is ignored on Barycenters │ │ - [ 16db1] {}1 {} A │ │ - [ 16dba] ()D │ │ - [ 16dbe] (JI)V │ │ - [ 16dc4] ,\n │ │ - [ 16dc7] [\n │ │ - [ 16dca] No known providers. This is likely a bug in libepoxy code generation\n │ │ - [ 16e15] %s() not found: %s\n │ │ - [ 16e29] int epoxy_egl_version(EGLDisplay) │ │ - [ 16e4b] Too many color components: %d, max %d │ │ - [ 16e71] Bogus DAC index %d │ │ - [ 16e84] %3d %3d %3d %3d %3d %3d %3d %3d │ │ - [ 16eac] JFIF extension marker: type 0x%02x, length %u │ │ - [ 16eda] Corrupt JPEG data: premature end of data segment │ │ - [ 16f0b] Component index %d: mismatching sampling ratio %d:%d, %d:%d, %c │ │ - [ 16f4b] resource.frk/ │ │ - [ 16f59] /sfnts │ │ - [ 16f60] FDBytes │ │ - [ 16f68] pcf │ │ - [ 16f6c] IRV │ │ - [ 16f74] � │ │ - [ 16f7d] � │ │ - [ 16f85] � │ │ - [ 16f8a] raster1 │ │ - [ 16f92] svg-hooks │ │ - [ 16f9c] Version │ │ - [ 16fa4] WX │ │ - [ 16fa7] function │ │ - [ 16fb0] ^$*+?.([%- │ │ - [ 16fbb] global │ │ - [ 16fc2] stack traceback: │ │ - [ 16fd7] $^P^H^T^X^\^F^P^F^X^X^\ $(,^F^H^H^H^L │ │ - [ 16fed] -> │ │ - [ 16ff0] LUA_CPATH │ │ - [ 16ffa] short_src │ │ - [ 17004] isvararg │ │ - [ 1700d] activelines │ │ - [ 17019] exceeds application limits │ │ - [ 17034] MNG features are not allowed in a PNG datastream │ │ - [ 17065] Not recognizing known sRGB profile that has been edited │ │ - [ 1709d] bad encoding (internal error) │ │ - [ 170bb] unknown compression type │ │ - [ 170d4] insufficient memory to read chunk │ │ - [ 170f6] cHRM Blue X │ │ - [ 17102] image row stride too large │ │ - [ 1711d] Invalid sBIT depth specified │ │ - [ 1713a] card_c │ │ - [ 17141] SPICE(INVALIDACTION) │ │ - [ 17156] The Value in the Kernel File was Expected to be a date. │ │ - [ 1718e] An Invalid Function Argument was Supplied │ │ - [ 171b8] An Invalid Epoch Type Specification Was Supplied │ │ - [ 171e9] SPICE(NUMBEREXPECTED) │ │ - [ 171ff] SPICE(WRITEERROR) │ │ - [ 17211] files │ │ - [ 17217] DAFHOF │ │ - [ 1721e] SEQUENTIAL │ │ - [ 17229] variable count incorrect │ │ - [ 17242] can't read file │ │ - [ 17252] lately %s %s %s %s │ │ - [ 17265] IO │ │ - [ 17269] DAFRCR │ │ - [ 17270] ivals │ │ - [ 17276] SPICE(DASFTFULL) │ │ - [ 17287] nw │ │ - [ 1728a] The file type contains nonprinting characters. │ │ - [ 172ba] DASUFS │ │ - [ 172c1] SPICE(DASNOSUCHFILE) │ │ - [ 172d6] SPICE(DASINVALIDTYPE) │ │ - [ 172ec] poold │ │ - [ 172f2] Could not read DAS double precision record. File = # Record number = #. IOSTAT = #. │ │ - [ 17346] Could not write DAS character record. File = # Record number = #. IOSTAT = #. │ │ - [ 17397] NEW BODY │ │ - [ 173a0] writing a variable to the output kernel file │ │ - [ 173ce] This is never supposed to happen. The requested name, '#', was found in the name list, but the pointer to the head of the data for this variable is zero. Please note your activities and report this error to NAIF. │ │ - [ 174a5] LMPOOL │ │ - [ 174ac] ELEMC │ │ - [ 174b2] \begindata │ │ - [ 174bd] Invalid frame specification found in kernel pool: frame class keyword is # but associated frame name assignment was not found. │ │ - [ 1753c] BODC2N │ │ - [ 17543] BILLION │ │ - [ 1754b] del │ │ - [ 1754f] This segment reports that it has # meta data items. Every generic segment must have at least #. │ │ - [ 175af] xmeta │ │ - [ 175b5] XFR │ │ - [ 175b9] NIP │ │ - [ 175bd] ) │ │ - [ 175bf] SPICE(SPKINSUFFDATA) │ │ - [ 175d4] SPICE(NONPOSITIVEMASS) │ │ - [ 175eb] The periapsis and trajectory pole vectors are not orthogonal. The anglebetween them is # degrees. │ │ - [ 1764e] sb2rv │ │ - [ 17654] SPKE02 │ │ - [ 1765b] SPKE12 │ │ - [ 17662] SPKR02 │ │ - [ 17669] tsipm │ │ - [ 1766f] The variable # could not be found in the kernel pool. │ │ - [ 176a5] idents │ │ - [ 176ac] => │ │ - [ 176af] otherwise corrupted---or deleting previous │ │ - [ 176da] invalid integer │ │ - [ 176ea] no real part │ │ - [ 176f7] A subsystem state counter overflowed. For this to happen there must be a SPICE bug or you must have been running your SPICE-based application for a very long time. Please contact NAIF.and report the circumstances under which this happened. │ │ - [ 177e7] File '#' already loaded. │ │ - [ 17800] ftmnm │ │ - [ 17806] Attempt to reconnect logical unit to file '#' failed. IOSTAT was #. │ │ - [ 1784a] ZZDDHINI │ │ - [ 17853] ZZDDHGTU │ │ - [ 1785c] zzddhnfc_ │ │ - [ 17866] Unable to determine the binary file format of DAF '#'. │ │ - [ 1789d] ZZDSKSNS ran out of segment table room while trying to append to the tail of the segment list for body #. Current state is ADD TO END. │ │ - [ 17924] ZZDSKCHK │ │ - [ 1792d] itmfrm │ │ - [ 17934] TARGET │ │ - [ 1793b] LATITUDE │ │ - [ 17944] Definition of frame # specifies frame center # and nutation model #. This nutation model is not applicable to body #. This situation is usually caused by an error in a frame kernel in which the frame is defined. │ │ - [ 17a19] FROM_FRAMES │ │ - [ 17a25] The kernel variable # used to define frame # is assigned the character value #. This value was expected to be a reference frame name, but NAMFRM cannot translate this name to a frame ID code. │ │ - [ 17ae6] SPICE(BADAXISLENGTH) │ │ - [ 17afb] zzdynrot_ │ │ - [ 17b05] SPICE(BADSUBSTRINGBOUNDS) │ │ - [ 17b1f] ZZEKJOIN │ │ - [ 17b28] rsdsc │ │ - [ 17b2e] ZZEKQSEL │ │ - [ 17b37] ZZEKPGAL │ │ - [ 17b40] Attempt to free non-existent CHR page. Page number = #; valid range is 1:# │ │ - [ 17b8b] Statistic # is not supported. │ │ - [ 17ba9] ZZEKVCAL │ │ - [ 17bb2] ZZEKVMCH │ │ - [ 17bbb] EK = #; COLIDX = #; ROW = #; ELTIDX = #. Column entry element was not found. │ │ - [ 17c0b] IAU_JUPITER_BARYCENTER │ │ - [ 17c22] IAU_BORRELLY │ │ - [ 17c2f] MARS_BARYCENTER │ │ - [ 17c3f] SINOPE │ │ - [ 17c46] CARPO │ │ - [ 17c4c] DAPHNIS │ │ - [ 17c54] ANTHE │ │ - [ 17c5a] CORDELIA │ │ - [ 17c63] CALIBAN │ │ - [ 17c6b] FERDINAND │ │ - [ 17c75] BEPICOLOMBO MMO │ │ - [ 17c85] SIRTF │ │ - [ 17c8b] MPL │ │ - [ 17c8f] EXM SPACECRAFT COMPOSITE │ │ - [ 17ca8] EXOMARS SP │ │ - [ 17cb3] CLUSTER 3 │ │ - [ 17cbd] SHOEMAKER-LEVY 9-W │ │ - [ 17cd0] CLARK │ │ - [ 17cd6] GEHRELS 3 │ │ - [ 17ce0] KOPFF │ │ - [ 17ce6] TUTTLE │ │ - [ 17ced] WILSON-HARRINGTON │ │ - [ 17cff] POLYMELE │ │ - [ 17d08] zzmsxf_ │ │ - [ 17d10] ZZSHSH │ │ - [ 17d17] SPICE(BADVARASSIGN) │ │ - [ 17d2b] Oi │ │ - [ 17d2e] yY* │ │ - [ 17d32] Ydi │ │ - [ 17d36] zzrvbf_ │ │ - [ 17d3e] There is a non-printing character embedded in line # of the text buffer. Non-printing characters are not allowed in kernel variable assignments. The non-printing character has ASCII code #. │ │ - [ 17dff] The kernel variable # has been set up as a numeric or time variable. However, the value that you are attempting to assign to this variable on line # of the kernel buffer is not a numeric or time value. │ │ - [ 17ecb] SPICE(TOOMANYCOEFFS) │ │ - [ 17ee0] SPICE(KERNELVARTOOLARGE) │ │ - [ 17ef9] SCLI01 │ │ - [ 17f00] JDUTC │ │ - [ 17f06] ZZSPKGO1 │ │ - [ 17f0f] Target range rate magnitude is approximately the speed of light. The light time derivative cannot be computed. │ │ - [ 17f7e] tvec │ │ - [ 17f83] The input time string '#' cannot be processed because it contains more than @ recognizable tokens. The token that could not be processed was '#'. │ │ - [ 18015] CDT │ │ - [ 18019] Yidi:i:n │ │ - [ 18022] Yimi │ │ - [ 18027] i-i-iti:i:n │ │ - [ 18033] i-idi:i:i │ │ - [ 1803d] H*M*SmDY │ │ - [ 18046] iiY │ │ - [ 1804a] iiYn │ │ - [ 1804f] iimi │ │ - [ 18054] DmH*M*SY │ │ - [ 1805d] imiiin │ │ - [ 18064] miYi:i:n │ │ - [ 1806d] mii:i:nY │ │ - [ 18076] Y-i-iti │ │ - [ 1807e] i:i:ni/i/i │ │ - [ 18089] i:ii/i/Y │ │ - [ 18092] ZZXLATED │ │ - [ 1809b] FX │ │ - [ 1809e] art__LOJBAN │ │ - [ 180aa] ach │ │ - [ 180ae] dar │ │ - [ 180b2] de │ │ - [ 180b5] krj │ │ - [ 180b9] ltg │ │ - [ 180bd] lua │ │ - [ 180c1] luo │ │ - [ 180c5] mfe │ │ - [ 180c9] nyo │ │ - [ 180cd] rn │ │ - [ 180d0] sd │ │ - [ 180d3] cre │ │ - [ 180d7] eng │ │ - [ 180db] gla │ │ - [ 180df] ibo │ │ - [ 180e3] cor │ │ - [ 180e7] ori │ │ - [ 180eb] tel │ │ - [ 180ef] twi │ │ - [ 180f3] AW │ │ - [ 180f6] JE │ │ - [ 180f9] KI │ │ - [ 180fc] TW │ │ - [ 180ff] UG │ │ - [ 18102] AFG │ │ - [ 18106] ASM │ │ - [ 1810a] ERI │ │ - [ 1810e] GHA │ │ - [ 18112] GNQ │ │ - [ 18116] ISR │ │ - [ 1811a] da_DK │ │ - [ 18120] kk_KZ │ │ - [ 18126] ro_RO │ │ - [ 1812c] tk_TM │ │ - [ 18132] PETST │ │ - [ 18138] ULAT │ │ - [ 1813d] languageAliases │ │ - [ 1814d] en_ID │ │ - [ 18153] en_IN │ │ - [ 18159] es_CU │ │ - [ 1815f] es_EC │ │ - [ 18165] fr_MA │ │ - [ 1816b] la_001 │ │ - [ 18172] mn_Mong │ │ - [ 1817a] ures_swap(): resource top %d exceeds bundle length %d\n │ │ - [ 181b1] ures_swap(): unable to allocate memory for tracking resources\n │ │ - [ 181f0] ucol_strcollIter │ │ - [ 18201] night2 │ │ - [ 18208] indian │ │ - [ 1820f] Countries │ │ - [ 18219] parseRegions │ │ - [ 18226] {0}, {1} │ │ - [ 1822f] other number │ │ - [ 1823c] U_STRING_NOT_TERMINATED_WARNING │ │ - [ 1825c] U_TRAILING_BACKSLASH │ │ - [ 18271] U_INVALID_RBT_SYNTAX │ │ - [ 18286] AUD │ │ - [ 1828a] BAM │ │ - [ 1828e] CLE │ │ - [ 18292] KHR │ │ - [ 18296] MGA │ │ - [ 1829a] MTL │ │ - [ 1829e] RHD │ │ - [ 182a2] SOS │ │ - [ 182a6] SYP │ │ - [ 182aa] scientificFormat │ │ - [ 182bb] M02L │ │ - [ 182c0] milligram-ofglucose-per-deciliter │ │ - [ 182e2] liter-per-100-kilometer │ │ - [ 182fa] GNE │ │ - [ 182fe] petabyte │ │ - [ 18307] day-person │ │ - [ 18312] kilowatt-hour │ │ - [ 18320] earth-mass │ │ - [ 1832b] pinch │ │ - [ 18331] pow10- │ │ - [ 18338] compound │ │ - [ 18341] unit-narrow │ │ - [ 1834d] /decimalFormat │ │ - [ 1835c] yes │ │ - [ 18360] ucadata │ │ - [ 18368] reset position maps to too many collation elements (more than 31) │ │ - [ 183aa] LDML forbids tailoring to U+FFFF │ │ - [ 183cb] lb_to_kg │ │ - [ 183d4] speed_of_light_meters_per_second │ │ - [ 183f5] AChoreographerFrameCallbackData_getPreferredFrameTimelineIndex │ │ - [ 18434] mPipelineModeAutoMode │ │ - [ 1844a] Swappy: GPU frame time │ │ - [ 18461] View too small to be split │ │ - [ 1847c] cannot switch from automatic to manual argument indexing │ │ - [ 184b5] {} must be an array of strings.\n │ │ - [ 184d6] Target │ │ - [ 184dd] Error parsing favorites file.\n │ │ - [ 184fc] Point size granularity: %s\n │ │ - [ 18518] {}\n │ │ - [ 18520] inf │ │ - [ 18524] Time stopped │ │ - [ 18534] CHANNEL_TOP_BACK_LEFT │ │ - [ 1854a] Too large │ │ - [ 18554] NULL Playback Device │ │ - [ 18569] Failed to retrieve data buffer connector. Unknown data supply type.\n │ │ - [ 185ae] ICMT │ │ - [ 185b3] ^I │ │ - [ 185b6] URL must have at least mode and time!\n │ │ - [ 185dd] tsrc │ │ - [ 185e2] failed to format time │ │ - [ 185f8] Jul │ │ - [ 185fc] text │ │ - [ 18601] azure │ │ - [ 18607] cadetblue │ │ - [ 18611] cornsilk │ │ - [ 1861a] gray │ │ - [ 1861f] maroon │ │ - [ 18626] .png │ │ - [ 1862b] .ctx │ │ - [ 18630] XI │ │ - [ 18633] TAU │ │ - [ 18641] Comet │ │ - [ 18647] regio │ │ - [ 1864d] synchronous │ │ - [ 18659] filename │ │ - [ 18662] longitude │ │ - [ 1866c] downarrow │ │ - [ 18676] row │ │ - [ 1867a] xoffset │ │ - [ 18682] colorbottom │ │ - [ 1868e] createchild │ │ - [ 1869a] getlinecolor │ │ - [ 186a7] getfaintestvisible │ │ - [ 186ba] getsystemtime │ │ - [ 186c8] No arguments expected for celestia:getrenderflags() │ │ - [ 186fc] One argument expected for celestia:setfaintestvisible() │ │ - [ 18734] Argument to celestia:setstarstyle must be a string │ │ - [ 18767] First argument to celestia:seturl must be a string │ │ - [ 1879a] Function celestia:seekaudio requires two arguments │ │ - [ 187cd] mouseup │ │ - [ 187d5] Oops, expected savedrenderflags to be userdata\n │ │ - [ 18805] class_phase │ │ - [ 18811] No arguments expected for frame:getcoordinatesystem() │ │ - [ 18847] Begin │ │ - [ 1884d] TEXTURE_MIN_FILTER │ │ - [ 18860] argument 4 to gl.Frustum must be a number │ │ - [ 1888a] argument 1 to gl.Vertex must be a number │ │ - [ 188b3] catalognumber │ │ - [ 188c1] globular │ │ - [ 188ca] First arg to observer:gotoobject must be object or position │ │ - [ 18906] Second arg to observer:gotodistance must be a number │ │ - [ 1893b] Argument to observer:setpos must be a rotation │ │ - [ 1896a] One argument expected to observer:getsurface() │ │ - [ 18999] Bad vector addition! │ │ - [ 189ae] Need two operands for sub │ │ - [ 189c8] hook thread failed\n │ │ - [ 189dc] emissivemap │ │ - [ 189e8] texcoord2 │ │ - [ 189f3] ganymede │ │ - [ 189fc] iapetus │ │ - [ 18a04] iau-mars │ │ - [ 18a0d] iau-jupiter │ │ - [ 18a19] colorTex │ │ - [ 18a22] Error parsing asterism {} chain: expected string\n │ │ - [ 18a54] Aql │ │ - [ 18a58] Cae │ │ - [ 18a5c] RA │ │ - [ 18a5f] GL_OES_vertex_array_object │ │ - [ 18a7a] AMD │ │ - [ 18a7e] SU │ │ - [ 18a81] RotationPeriod │ │ - [ 18a90] PrecessionPeriod │ │ - [ 18aa1] AU │ │ - [ 18aa4] GLSL │ │ - [ 18aaa] usesShadows = {}\n │ │ + [ 113ec] SCPR01 │ │ + [ 113f3] words │ │ + [ 113f9] MSGSEL: An invalid error message type was supplied as input; the type specifiedwas: │ │ + [ 11450] Input file # has architecture #. The file must be a binary SPK file to be readable by this routine. Binary SPK files have DAF architecture. If you expected the file to be a binary SPK file, the problem may be due to the file being an old non-native file lacking binary file format information. It's also possible the file has been corrupted. │ │ + [ 115a8] GETFAT │ │ + [ 115af] The mass supplied for the central body of a type 15 segment was non-positive. Masses must be positive. The value supplied was #. │ │ + [ 11632] The eccentricity supplied for a type 17 segment is greater than 0.9. It must be less than 0.9.The value supplied to the type 17 evaluator was #. │ │ + [ 116c5] The semi-major axis supplied to EQNCPV was non-positive. The value is required to be positive by this routine. The value supplied was #. │ │ + [ 1174f] PCK data required to compute the orientation of the # # for epoch # TDB were not found. If these data were to be provided by a binary PCK file, then it is possible that the PCK file does not have coverage for the specified body-fixed frame at the time of interest. If the data were to be provided by a text PCK file, then possibly the file does not contain data for the specified body-fixed frame. In either case it is possible that a required PCK file was not loaded at all. │ │ + [ 1192b] MAX_PHASE_DEGREE │ │ + [ 1193c] dtipm │ │ + [ 11942] N0067 │ │ + [ 11948] marker or final newline character, or is │ │ + [ 11972] Left endpoint was *. Right endpoint was *. │ │ + [ 1199d] IOSTAT = │ │ + [ 119a7] CLLINE: File = │ │ + [ 119b8] w_ed, unexpected code: %d\n │ │ + [ 119d3] defnam │ │ + [ 119da] An attempt to assign the code, #, to a blank string was made. Check loaded text kernels for a blank string in the NAIF_BODY_NAME array. │ │ + [ 11a63] ZZDAFGSR │ │ + [ 11a6c] The attempt to load file, '#', with access method, '#', failed because this access method is unsupported. │ │ + [ 11ad6] strarc │ │ + [ 11add] Definition of frame # contains # specification #. The only valid rotation states are # or #. This situation is usually caused by an error in a frame kernel in which the frame is defined. │ │ + [ 11b98] NONE │ │ + [ 11b9d] ddat │ │ + [ 11ba2] N_D_ALLOC │ │ + [ 11bac] ZZEKSZ05 │ │ + [ 11bb5] IAU_DEIMOS │ │ + [ 11bc0] IAU_OPHELIA │ │ + [ 11bcc] LONGEST LIST SIZE │ │ + [ 11bde] MAB │ │ + [ 11be2] MEX │ │ + [ 11be6] JUNO │ │ + [ 11beb] NEAR EARTH ASTEROID RENDEZVOUS │ │ + [ 11c0a] DIXI │ │ + [ 11c0f] CH2L │ │ + [ 11c14] MAP │ │ + [ 11c18] DAWN │ │ + [ 11c1d] RBSP_A │ │ + [ 11c24] MARS-96 │ │ + [ 11c2c] SHOEMAKER-LEVY 9-N │ │ + [ 11c3f] SHOEMAKER-LEVY 9-B │ │ + [ 11c52] FAYE │ │ + [ 11c57] GICLAS │ │ + [ 11c5e] SCHUSTER │ │ + [ 11c67] TRITTON │ │ + [ 11c6f] HELIN-ROMAN-ALU 1 │ │ + [ 11c81] MATHILDE │ │ + [ 11c8a] MADRID │ │ + [ 11c91] DSS-17 │ │ + [ 11c98] # is a CK frame; a CK file containing data for instrument or structure # at the epoch shown above, as well as a corresponding SCLK kernel, must be loaded in order to use this frame. │ │ + [ 11d4e] │ │ + [ 11d6f] zzplatfm_ │ │ + [ 11d79] ZZPLTCHK │ │ + [ 11d82] zzrefch0_ │ │ + [ 11d8c] [w] │ │ + [ 11d90] Dm │ │ + [ 11d93] The type of the time vector specified was #, only 'YD' and 'YMD' are recognized. │ │ + [ 11de5] SPICE(BADKERNELVARTYPE) │ │ + [ 11dfd] Offset count # does not match field count # for SCLK #. │ │ + [ 11e35] SPICE(BADPECCENTRICITY) │ │ + [ 11e4d] Semi-latus rectum less-than zero. │ │ + [ 11e6f] zzspkgp0_ │ │ + [ 11e79] Interval time bounds are not strictly increasing at interval index # for switch frame #. Time bounds are #:# TDB (# TDB : # TDB) │ │ + [ 11efa] White Space │ │ + [ 11f06] Month │ │ + [ 11f0c] recog │ │ + [ 11f12] UTC- │ │ + [ 11f17] Two substrings indicating a calendar year were identified in the input time string <#> and <#>: " │ │ + [ 11f79] Both a day of year and month were identified in the input string. " │ │ + [ 11fbd] ############## │ │ + [ 11fcc] Y*m*D*H*M │ │ + [ 11fd6] Y-idi:i │ │ + [ 11fde] Y-idi:n │ │ + [ 11fe6] i-Y/i:i:n │ │ + [ 11ff0] i-i/i:i │ │ + [ 11ff8] miii:n │ │ + [ 11fff] i-i-Yi:i:i │ │ + [ 1200a] Y-itx │ │ + [ 12010] The direction vectors associated with states AXDEF and PLNDEF are linearly dependent. │ │ + [ 12066] hy__AREVMDA │ │ + [ 12072] aa │ │ + [ 12075] blo │ │ + [ 12079] dsb │ │ + [ 1207d] gn │ │ + [ 12080] grb │ │ + [ 12084] hai │ │ + [ 12088] ho │ │ + [ 1208b] ksf │ │ + [ 1208f] ku │ │ + [ 12092] lam │ │ + [ 12096] ml │ │ + [ 12099] pap │ │ + [ 1209d] tli │ │ + [ 120a1] zbl │ │ + [ 120a5] cos │ │ + [ 120a9] fra │ │ + [ 120ad] jpn │ │ + [ 120b1] nau │ │ + [ 120b5] oci │ │ + [ 120b9] oji │ │ + [ 120bd] sna │ │ + [ 120c1] sun │ │ + [ 120c5] DM │ │ + [ 120c8] GF │ │ + [ 120cb] GU │ │ + [ 120ce] LV │ │ + [ 120d1] PT │ │ + [ 120d4] SB │ │ + [ 120d7] TM │ │ + [ 120da] ZM │ │ + [ 120dd] ATG │ │ + [ 120e1] CAN │ │ + [ 120e5] FRA │ │ + [ 120e9] GRC │ │ + [ 120ed] MKD │ │ + [ 120f1] MYS │ │ + [ 120f5] PCN │ │ + [ 120f9] SVN │ │ + [ 120fd] cs_CZ │ │ + [ 12103] pl_PL │ │ + [ 12109] ur_PK │ │ + [ 1210f] MST7MDT │ │ + [ 12117] AST │ │ + [ 1211b] Chile/EasterIsland │ │ + [ 1212e] America/Guatemala │ │ + [ 12140] ar_KW │ │ + [ 12146] en_MP │ │ + [ 1214c] fr_CI │ │ + [ 12152] haw_US │ │ + [ 12159] om_ET │ │ + [ 1215f] sd_Arab │ │ + [ 12167] ti_ER │ │ + [ 1216d] sgn-mx │ │ + [ 12174] ures_swap(): too few bytes (%d after header) for a resource bundle\n │ │ + [ 121b8] ures_swap().swapArray16(16-bit units[%d]) failed\n │ │ + [ 121ea] windowsZones │ │ + [ 121f7] weekData │ │ + [ 12200] calendarPreferenceData │ │ + [ 12217] M02 │ │ + [ 1221b] mapTimezones │ │ + [ 12228] icudt75l-zone │ │ + [ 12236] pattern │ │ + [ 1223e] line separator │ │ + [ 1224d] U_UNSUPPORTED_ERROR │ │ + [ 12261] U_NO_SPACE_AVAILABLE │ │ + [ 12276] U_UNTERMINATED_QUOTE │ │ + [ 1228b] U_ILLEGAL_PAD_POSITION │ │ + [ 122a2] U_ARGUMENT_TYPE_MISMATCH │ │ + [ 122bb] U_BRK_VARIABLE_REDFINITION │ │ + [ 122d6] U_BRK_MISMATCHED_PAREN │ │ + [ 122ed] U_BRK_UNDEFINED_VARIABLE │ │ + [ 12306] U_REGEX_LOOK_BEHIND_LIMIT │ │ + [ 12320] U_IDNA_LABEL_TOO_LONG_ERROR │ │ + [ 1233c] exceptions │ │ + [ 12347] BOV │ │ + [ 1234b] BWP │ │ + [ 1234f] CSK │ │ + [ 12353] ECV │ │ + [ 12357] ESB │ │ + [ 1235b] LBP │ │ + [ 1235f] LUL │ │ + [ 12363] SIT │ │ + [ 12367] XBB │ │ + [ 1236b] XEU │ │ + [ 1236f] XSU │ │ + [ 12373] Division by zero │ │ + [ 12384] Insufficient storage │ │ + [ 12399] calendarData │ │ + [ 123a6] @calendar=coptic │ │ + [ 123b7] concentr │ │ + [ 123c0] consumption │ │ + [ 123cc] revolution │ │ + [ 123d7] square-mile │ │ + [ 123e3] liter-per-kilometer │ │ + [ 123f7] kilobit │ │ + [ 123ff] kilojoule │ │ + [ 12409] milligram │ │ + [ 12413] beaufort │ │ + [ 1241c] micro │ │ + [ 12422] nano │ │ + [ 12427] or-short │ │ + [ 12430] cldrVersion │ │ + [ 1243c] tsubo_to_m2 │ │ + [ 12448] dalvik/system/InMemoryDexClassLoader │ │ + [ 1246d] android/view/Display │ │ + [ 12482] MODEL │ │ + [ 12488] unique_lock::lock: references null mutex │ │ + [ 124b1] Comet tails disabled │ │ + [ 124c6] Time: Backward │ │ + [ 124d5] ltr │ │ + [ 124d9] inverting crosshair │ │ + [ 124ed] MeasurementSystem │ │ + [ 124ff] RayBasedDragging │ │ + [ 12510] OrbitPeriodsShown │ │ + [ 12522] false\n │ │ + [ 1252a] selection " │ │ + [ 12536] LT │ │ + [ 1253b] Chase %s\n │ │ + [ 12545] Density: {} lb/ft�\n │ │ + [ 1255a] Loading symbol: %s\n │ │ + [ 1256e] Capture Device │ │ + [ 1257d] Attempting to initialize %s backend...\n │ │ + [ 125a5] Failed to initialize %s backend.\n │ │ + [ 125c7] Channel Routing: %s\n │ │ + [ 125e9] CHANNEL_AUX_4 │ │ + [ 125f7] Out of memory │ │ + [ 12605] Failed to initialize backend │ │ + [ 12622] [AAudio] Device Disconnected. Failed to post job for rerouting.\n │ │ + [ 12663] AAudioStreamBuilder_setFormat │ │ + [ 12681] AAudioStream_getState │ │ + [ 12697] [OpenSL] Failed to stop internal playback device. │ │ + [ 126c9] labl │ │ + [ 126ce] note │ │ + [ 126d3] darksalmon │ │ + [ 126de] darkturquoise │ │ + [ 126ec] mediumaquamarine │ │ + [ 12703] cloudmaps │ │ + [ 1270d] facula │ │ + [ 12714] gotoloc │ │ + [ 1271c] setwindowbordersvisible │ │ + [ 12734] unmark │ │ + [ 1273b] unmarkall │ │ + [ 12745] view │ │ + [ 1274a] User data expected │ │ + [ 1275d] showconstellations │ │ + [ 12770] hideconstellations │ │ + [ 12783] setoverlayelements │ │ + [ 12796] getstarstyle │ │ + [ 127a3] tojulianday │ │ + [ 127af] getstar │ │ + [ 127b7] newcategory │ │ + [ 127c3] Third argument to celestia:print must be a number │ │ + [ 127f5] Argument to celestia:getlabelcolor() must be a string │ │ + [ 1282b] setlinecolor: color values must be numbers │ │ + [ 12856] Values in table-argument to celestia:setoverlayelements() must be boolean │ │ + [ 128a0] One argument expected for celestia:setgalaxylightgain() │ │ + [ 128d8] One argument expected for celestia:select() │ │ + [ 12904] No argument expected to function celestia:ispaused │ │ + [ 12937] No argument expected to function celestia:istimesynchronized │ │ + [ 12974] No argument expected to function celestia:gettimescale │ │ + [ 129ab] Second arg to celestia:settimescale must be a number │ │ + [ 129e0] No argument expected in celestia:getstarstyle │ │ + [ 12a0e] Argument to celestia:setstarcolor must be a string │ │ + [ 12a41] Fourth argument to celestia:overlay must be a number (alpha) │ │ + [ 12a7e] Second argument to celestia:play must be a number (volume) │ │ + [ 12ab9] edgeclamp │ │ + [ 12ac3] string │ │ + [ 12aca] Error: LuaState invalid in Celx_SafeGetNumber\n │ │ + [ 12af9] class_matrix │ │ + [ 12b06] class_rotation │ │ + [ 12b15] Color │ │ + [ 12b1b] Translate │ │ + [ 12b25] One argument expected for gl.LineWidth() │ │ + [ 12b4e] No arguments expected for font:unbind() │ │ + [ 12b76] Error while parsing CEL-script. │ │ + [ 12b96] First argument to object:setorbitvisibility() must be a string │ │ + [ 12bd5] Unknown visibility policy: {}\n │ │ + [ 12bf4] invisible │ │ + [ 12bfe] stellarClass │ │ + [ 12c0b] absoluteMagnitude │ │ + [ 12c1d] hasRings │ │ + [ 12c26] Time expected as argument to object:getphase │ │ + [ 12c53] setfov │ │ + [ 12c5a] accelTime │ │ + [ 12c64] Bad observer object (maybe tried to access a deleted view?)! │ │ + [ 12ca1] Argument for observer:orbit must be a rotation │ │ + [ 12cd0] Bad phase object during garbage collection! │ │ + [ 12cfc] Bad phase object! │ │ + [ 12d0e] second argument to rotation:setaxisangle must be a number │ │ + [ 12d48] normalize │ │ + [ 12d52] emissive │ │ + [ 12d5b] trilist │ │ + [ 12d63] texcoord1 │ │ + [ 12d6e] jpl-sun-ssb │ │ + [ 12d7a] miranda │ │ + [ 12d82] iau-titan │ │ + [ 12d8c] Failed to load module for ScriptedOrbit: {}\n │ │ + [ 12db9] ScriptedRotation generator function returned bad value.\n │ │ + [ 12df2] %ld │ │ + [ 12df7] Loaded SPK file {}\n │ │ + [ 12e0b] spk │ │ + [ 12e0f] pixelWeight │ │ + [ 12e1b] Error parsing asterism {} chain: expected array\n │ │ + [ 12e4c] Aur │ │ + [ 12e50] Cyg │ │ + [ 12e54] Sco │ │ + [ 12e58] Error parsing deep sky catalog entry {}\n │ │ + [ 12e81] Galaxy (Hubble type: %s) │ │ + [ 12e9a] models/SBa.png │ │ + [ 12ea9] s │ │ + [ 12eab] NoiseOffset │ │ + [ 12eb7] Could not find custom rotation model named '{}'\n │ │ + [ 12ee8] FixedAttitude │ │ + [ 12ef6] FixedPosition planetographic coordinates are not valid for stars.\n │ │ + [ 12f39] MeridianAngle │ │ + [ 12f47] Object has incorrect topocentric frame syntax.\n │ │ + [ 12f77] Bad two-vector frame: vector has invalid axis label.\n │ │ + [ 12fad] rE │ │ + [ 12fb0] tangent = in_Tangent;\n │ │ + [ 12fc7] );\n │ │ + [ 12fcb] shadowMaxDepth │ │ + [ 12fda] l = mix(NL, (NL / (max(NV, 0.001) + NL)), lunarLambert) * clamp( │ │ + [ 1301b] color.rgb = mix(color.rgb, overlayColor.rgb, overlayColor.a);\n │ │ + [ 1305a] gl_FragColor = color * diff + spec;\n │ │ + [ 1307f] .st) * totalLight;\n │ │ + [ 13093] opticalDepth │ │ + [ 130a0] ringShadowTexCoordX = │ │ + [ 130b7] triangles │ │ + [ 130c1] Invalid SemiAxes value for object {}: [{}, {}, {}]\n │ │ + [ 130f5] Mie │ │ + [ 130f9] CloudNormalMap │ │ + [ 13108] OverlayTexture │ │ + [ 13117] LabelColor │ │ + [ 13122] Ia │ │ + [ 13125] unrecognized object type │ │ + [ 1313e] Content size {} too small to include face array count\n │ │ + [ 13175] (DDD)V │ │ + [ 1317c] (Ljava/lang/Object;)Z │ │ + [ 13192] Locations │ │ + [ 1319c] ],\n │ │ + [ 131a0] occulter │ │ + [ 131a9] receiver │ │ + [ 131b2] (I)Z │ │ + [ 131b7] LC_COLLATE │ │ + [ 131c2] Bogus virtual array access │ │ + [ 131dd] Memory limit exceeded │ │ + [ 131f3] Not a JPEG file: starts with 0x%02x 0x%02x │ │ + [ 1321e] ._ │ │ + [ 13221] .AppleDouble/ │ │ + [ 1322f] multi-masters │ │ + [ 1323d] BlueFuzz │ │ + [ 13246] MinFeature │ │ + [ 13251] StrokeWidth │ │ + [ 1325d] BlendAxisTypes │ │ + [ 1326c] XUID │ │ + [ 13271] Bold Italic │ │ + [ 1327d] ADD_STYLE_NAME │ │ + [ 1328c] AVG_CAPITAL_WIDTH │ │ + [ 1329e] DEFAULT_CHAR │ │ + [ 132ab] RAW_CAP_HEIGHT │ │ + [ 132bd] � │ │ + [ 132c2] StartKernPairs │ │ + [ 132d1] upval │ │ + [ 132d7] k │ │ + [ 132d9] && │ │ + [ 132dc] luaopen_%s │ │ + [ 132e7] external hook │ │ + [ 132f6] 32bit^Cfpu^Fsoftfp^Deabi^Ble │ │ + [ 1330f] png_image_begin_read_from_file: invalid argument │ │ + [ 13340] missing IHDR │ │ + [ 1334d] hIST must be after │ │ + [ 13360] too many profiles │ │ + [ 13372] iCCP: invalid keyword │ │ + [ 13388] SPICE(INVALIDSIZE) │ │ + [ 1339b] SPICE(INVALIDCLUSTERNUM) │ │ + [ 133b4] SPICE(INVALIDOPTION) │ │ + [ 133c9] SPICE(PATHTOOLONG) │ │ + [ 133dc] itbeg │ │ + [ 133e2] ithfs │ │ + [ 133e8] Number of files loaded is at a maximum, as specified by the parameter FTSIZE, the value of which is #. You will need to either load fewer files, or change the parameter FTSIZE. │ │ + [ 13499] SPICE(NOLOADEDFILES) │ │ + [ 134ae] NI was #, should be in range [2,#]. │ │ + [ 134d2] internal │ │ + [ 134db] No record, word for address #. │ │ + [ 134fa] DAFBFS │ │ + [ 13501] DAFFNA │ │ + [ 13508] Character record write failed. Value of IOSTAT was # │ │ + [ 1353d] stncol │ │ + [ 13544] EKCCNT │ │ + [ 1354b] sizes │ │ + [ 13551] The number of comment records allocated must be non-negative but was #. │ │ + [ 13599] lastrc │ │ + [ 135a0] SPICE(DASNOSUCHHANDLE) │ │ + [ 135b7] rcbufd │ │ + [ 135be] SPICE(INVALIDNODE) │ │ + [ 135d1] r+b │ │ + [ 135d5] malloc failure │ │ + [ 135e4] btchkp │ │ + [ 135eb] pckbsr_ │ │ + [ 135f3] btruex │ │ + [ 135fa] pool_ │ │ + [ 13600] The watched kernel variable name list WTVARS has room for # more elements, so the # new names (in a list of # names) associated with agent # cannot be inserted. │ │ + [ 136a1] J2000 │ │ + [ 136a7] FRAME_ │ │ + [ 136ae] SPICE(NONEXISTELEMENTS) │ │ + [ 136c6] SPICE(PASTENDSTR) │ │ + [ 136d8] SPICE(BADSUBSTR) │ │ + [ 136e9] CONVRT: Input units │ │ + [ 136fe] type: │ │ + [ 13705] agent │ │ + [ 1370b] cks │ │ + [ 1370f] CKR01 │ │ + [ 13715] DAFGDA │ │ + [ 1371c] SPICE(BADQUATSIGN) │ │ + [ 1372f] SPICE(NOTAROTATION) │ │ + [ 13743] rd_ed, unexpected code: %d\n │ │ + [ 1375f] OUTMSG: An invalid message type was specified in the type list. │ │ + [ 137a1] SPICE(INVALIDFORMAT) │ │ + [ 137b6] DAFETF │ │ + [ 137bd] 'NAIF/DAF' │ │ + [ 137c8] The input record has a maximum table dimension of #, while the maximum supported by this routine is #. It is possible that this problem is due to your SPICE Toolkit being out of date. │ │ + [ 13880] LGRESP │ │ + [ 13887] SPKR14 │ │ + [ 1388e] Both kernel variables # and # are present in the kernel pool. At most one form of the kernel variable name may be present. │ │ + [ 13909] PCKE02 │ │ + [ 13910] SCREEN │ │ + [ 13917] frozen │ │ + [ 1391e] & │ │ + [ 13920] WRLINE: File = │ │ + [ 13930] list in │ │ + [ 13938] bltnam │ │ + [ 1393f] SPICE(HANDLENOTFOUND) │ │ + [ 13955] ZZDASNFR │ │ + [ 1395e] ZZDDHHLU │ │ + [ 13967] The binary file format, '#', is not supported by this version of the toolkit. This is a serious problem, contact NAIF. │ │ + [ 139ea] Attempt to open file '#' failed. Value of IOSTAT was #. │ │ + [ 13a22] SPICE(UNKNOWNFILARC) │ │ + [ 13a37] itmaxe │ │ + [ 13a3e] itmunt │ │ + [ 13a45] VECTOR │ │ + [ 13a4c] NUT_MODEL │ │ + [ 13a56] OBLIQ_MODEL │ │ + [ 13a62] nearpt_ │ │ + [ 13a6a] axisqr │ │ + [ 13a71] Norm of scaled point is 0. POSITN = ( #, #, # ) │ │ + [ 13aa1] zzekjtst_ │ │ + [ 13aab] idxset │ │ + [ 13ab2] ZZEKLLED │ │ + [ 13abb] SPICE(DASNOTEMPTY) │ │ + [ 13ace] ZZEKRSD │ │ + [ 13ad6] ZZEKRD01 │ │ + [ 13adf] Key = #; valid range = 1:#. Tree = #, file = # │ │ + [ 13b0e] An attempt to create a temporary string array failed. Attempted to allocate # bytes. │ │ + [ 13b64] An attempt to copy a string using C2F_StrCpy failed. │ │ + [ 13b99] There is an inconsistency between the version of the routine calling ZZFDAT and the current version of ZZFDAT. Check to make sure that you have the most current versions of ZZFDAT and the routines that make use of it. │ │ + [ 13c73] IAU_UMBRIEL │ │ + [ 13c7f] IAU_GALATEA │ │ + [ 13c8b] IAU_EURYBATES │ │ + [ 13c99] zzdynfr0_ │ │ + [ 13ca3] SPICE(INVALIDDIVISOR) │ │ + [ 13cb9] EARTH_BARYCENTER │ │ + [ 13cca] LEDA │ │ + [ 13ccf] THYONE │ │ + [ 13cd6] HEGEMONE │ │ + [ 13cdf] HERSE │ │ + [ 13ce5] CALYPSO │ │ + [ 13ced] HATI │ │ + [ 13cf2] LOGE │ │ + [ 13cf7] DESPINA │ │ + [ 13cff] LADEE │ │ + [ 13d05] P10 │ │ + [ 13d09] PIONEER-11 │ │ + [ 13d14] JANUS_B │ │ + [ 13d1c] TROPICAL RAINFALL MEASURING MISSION │ │ + [ 13d40] ICE │ │ + [ 13d44] CASP │ │ + [ 13d49] MARTIAN MOONS EXPLORATION │ │ + [ 13d63] SELENE VLBI Radio Satellite │ │ + [ 13d7f] SHOEMAKER-LEVY 9-E │ │ + [ 13d92] RUSSELL 3 │ │ + [ 13d9c] SCHAUMASSE │ │ + [ 13da7] SINGER-BREWSTER │ │ + [ 13db7] HOLT-OLMSTEAD │ │ + [ 13dc5] DSS-27 │ │ + [ 13dcc] xmit │ │ + [ 13dd1] TPARSE does not support the specification of a time system in a string. The time system # was specified. │ │ + [ 13e3c] *w* │ │ + [ 13e40] The year value was #. This must be an integral value. │ │ + [ 13e78] YMD │ │ + [ 13e7d] SPICE(BADTIMEBOUNDS) │ │ + [ 13e92] YDF │ │ + [ 13e96] YMDF │ │ + [ 13e9b] SPICE(BADPICTURE) │ │ + [ 13ead] UTC-Offset indicator │ │ + [ 13ec2] JANUARY │ │ + [ 13eca] The input time string is blank. │ │ + [ 13eea] │ │ + [ 13ef0] Y-it │ │ + [ 13ef5] YmDH*M*S │ │ + [ 13efe] Yiiiii │ │ + [ 13f05] i:i:nimY │ │ + [ 13f0e] mDYH*M │ │ + [ 13f15] imYi:i │ │ + [ 13f1c] i/i/Yi:i:n │ │ + [ 13f27] mo │ │ + [ 13f2a] zh_GAN │ │ + [ 13f31] be │ │ + [ 13f34] bgn │ │ + [ 13f38] fil │ │ + [ 13f3c] goh │ │ + [ 13f40] hil │ │ + [ 13f44] kaw │ │ + [ 13f48] ky │ │ + [ 13f4b] lzh │ │ + [ 13f4f] mai │ │ + [ 13f53] mde │ │ + [ 13f57] mh │ │ + [ 13f5a] mn │ │ + [ 13f5d] srr │ │ + [ 13f61] su │ │ + [ 13f64] ve │ │ + [ 13f67] xnr │ │ + [ 13f6b] zun │ │ + [ 13f6f] fao │ │ + [ 13f73] hun │ │ + [ 13f77] ndo │ │ + [ 13f7b] slk │ │ + [ 13f7f] tgk │ │ + [ 13f83] tso │ │ + [ 13f87] tah │ │ + [ 13f8b] BH │ │ + [ 13f8e] IC │ │ + [ 13f91] KY │ │ + [ 13f94] SJ │ │ + [ 13f97] SX │ │ + [ 13f9a] TN │ │ + [ 13f9d] AUS │ │ + [ 13fa1] AZE │ │ + [ 13fa5] BDI │ │ + [ 13fa9] COK │ │ + [ 13fad] CMR │ │ + [ 13fb1] CYM │ │ + [ 13fb5] LBY │ │ + [ 13fb9] STP │ │ + [ 13fbd] UZB │ │ + [ 13fc1] ZAF │ │ + [ 13fc5] uprv_copyEbcdic() string[%] contains a variant character in position %d\n │ │ + [ 1400e] es_ES │ │ + [ 14014] km_KH │ │ + [ 1401a] lo_LA │ │ + [ 14020] yue_Hant_HK │ │ + [ 1402c] metadata │ │ + [ 14035] Asia/Anadyr │ │ + [ 14041] Asia/Yakutsk │ │ + [ 1404e] Asia/Ulaanbaatar │ │ + [ 1405f] AZT │ │ + [ 14063] WET │ │ + [ 14067] BRST │ │ + [ 1406c] America/Cuiaba │ │ + [ 1407b] US/Central │ │ + [ 14086] PSACCENT │ │ + [ 1408f] PSCRACK │ │ + [ 14097] partitions │ │ + [ 140a2] en_PH │ │ + [ 140a8] gd_GB │ │ + [ 140ae] it_CH │ │ + [ 140b4] ms_BN │ │ + [ 140ba] qu_PE │ │ + [ 140c0] ur_IN │ │ + [ 140c6] i-ami │ │ + [ 140cc] sgn-br │ │ + [ 140d3] ncs │ │ + [ 140d7] dse │ │ + [ 140db] zh-cmn-hans │ │ + [ 140e7] zh-wuu │ │ + [ 140ee] ucnv_unload │ │ + [ 140fa] ucol_openFromShortString │ │ + [ 14113] layout │ │ + [ 1411a] TZVersion │ │ + [ 14124] uchar_swapNames(): too few bytes (%d after header) for unames.icu\n │ │ + [ 14167] udict_swap(): too few bytes (%d after header) for all of dictionary data\n │ │ + [ 141b1] U_ZERO_ERROR │ │ + [ 141be] U_INTERNAL_PROGRAM_ERROR │ │ + [ 141d7] U_BUFFER_OVERFLOW_ERROR │ │ + [ 141ef] U_ILLEGAL_ESCAPE_SEQUENCE │ │ + [ 14209] U_MISMATCHED_SEGMENT_DELIMITERS │ │ + [ 14229] U_UNSUPPORTED_ATTRIBUTE │ │ + [ 14241] U_MF_SELECTOR_ERROR │ │ + [ 14255] U_BRK_RULE_SYNTAX │ │ + [ 14267] U_REGEX_PROPERTY_SYNTAX │ │ + [ 1427f] U_REGEX_UNIMPLEMENTED │ │ + [ 14295] currencyNumericCodes │ │ + [ 142aa] CNY │ │ + [ 142ae] ETB │ │ + [ 142b2] KMF │ │ + [ 142b6] KRO │ │ + [ 142ba] KYD │ │ + [ 142be] THB │ │ + [ 142c2] TMT │ │ + [ 142c6] XCG │ │ + [ 142ca] typeOffsets │ │ + [ 142d6] M10L │ │ + [ 142db] @calendar=ethiopic │ │ + [ 142ee] digital │ │ + [ 142f6] speed │ │ + [ 142fc] millimole-per-liter │ │ + [ 14310] ZWN │ │ + [ 14314] millimeter │ │ + [ 1431f] yard │ │ + [ 14324] kilogram │ │ + [ 1432d] centiliter │ │ + [ 14338] cubic-centimeter │ │ + [ 14349] personal │ │ + [ 14352] any │ │ + [ 14356] zepto │ │ + [ 1435c] grammaticalFeatures │ │ + [ 14370] UCARules │ │ + [ 14379] AMU │ │ + [ 1437d] ATrace_setCounter │ │ + [ 1438f] preferredRefreshPeriod │ │ + [ 143a6] Alt-azimuth mode disabled │ │ + [ 143c0] Time and script are paused │ │ + [ 143db] High res textures │ │ + [ 143ed] Unknown script system access policy {}\n │ │ + [ 14415] invalid precision │ │ + [ 14427] negative precision │ │ + [ 1443a] AsterismsFile │ │ + [ 14448] HDCrossIndex │ │ + [ 14455] WarpMeshFile │ │ + [ 14462] FocusZooming │ │ + [ 1446f] R │ │ + [ 14471] angle │ │ + [ 14477] true\n │ │ + [ 1447d] "\n │ │ + [ 14480] Travelling ({})\n │ │ + [ 14491] seconds │ │ + [ 14499] Mass: {} lb\n │ │ + [ 144a6] Error reading {} catalog file: {}\n │ │ + [ 144c9] Failed to load library: %s\n │ │ + [ 144e5] Failed to initialize mutex for device info retrieval. ma_context_get_device_info() is not thread safe.\n │ │ + [ 1454d] Passthrough: %s\n │ │ + [ 1456f] CHANNEL_AUX_3 │ │ + [ 1457d] CHANNEL_AUX_14 │ │ + [ 1458c] Format not supported │ │ + [ 145a1] WASAPI │ │ + [ 145a8] SL_IID_AUDIOIODEVICECAPABILITIES │ │ + [ 145c9] {:%c} │ │ + [ 145cf] {:%Y %b %d %H:%M:%S %Z} │ │ + [ 145e7] darkolivegreen │ │ + [ 145f6] lightgreen │ │ + [ 14601] lightseagreen │ │ + [ 1460f] mediumvioletred │ │ + [ 1461f] purple │ │ + [ 14626] yellowgreen │ │ + [ 14632] .tga │ │ + [ 1463d] labes │ │ + [ 14643] ring │ │ + [ 14648] Time │ │ + [ 1464d] magnitude │ │ + [ 14657] getaltazimuthmode │ │ + [ 14669] hidelabel │ │ + [ 14673] fromjulianday │ │ + [ 14681] runscript │ │ + [ 1468b] settimeslice │ │ + [ 14698] Argument to celestia:setlabelflags() must be a table │ │ + [ 146cd] Keys in table-argument to celestia:setlabelflags() must be strings │ │ + [ 14710] Wrong number of arguments to function celestia:tojulianday │ │ + [ 1474b] Third arg to celestia:utctotdb must be a number │ │ + [ 1477b] newframe: one object argument required for frame │ │ + [ 147ac] First arg to celestia:newvector must be a number │ │ + [ 147dd] Argument to celestia:setwindowbordersvisible must be a boolean │ │ + [ 1481c] One argument expected to function celestia:verbosity │ │ + [ 14851] First argument for celestia:isplayingaudio must be a number │ │ + [ 1488d] First argument for celestia:stopaudio must be a number │ │ + [ 148c4] First argument for celestia:setaudioloop must be a number │ │ + [ 148fe] Second argument for celestia:setaudioloop must be a boolean │ │ + [ 1493a] One argument expected to function celestia:log │ │ + [ 14969] Error while executing tick callback: {}\n │ │ + [ 14992] celestia │ │ + [ 1499b] PROJECTION │ │ + [ 149a6] No arguments expected for font:bind() │ │ + [ 149cc] No arguments expected for font:getmaxascent() │ │ + [ 149fa] setorbitvisibility │ │ + [ 14a0d] No arguments expected to object:orbitvisibility │ │ + [ 14a3d] atmosphereCloudHeight │ │ + [ 14a53] Sixth argument to object:mark must be a boolean │ │ + [ 14a83] skycolor │ │ + [ 14a8c] Value of {} must be number │ │ + [ 14aa7] isvalid │ │ + [ 14aaf] Last argument to observer:lookat must be of type vector │ │ + [ 14ae7] No arguments expected to observer:getposition │ │ + [ 14b15] Vector components must be numbers │ │ + [ 14b37] Merged similar meshes: {} -> {}.\n │ │ + [ 14b59] end_material │ │ + [ 14b66] jpl-earth-sun │ │ + [ 14b74] mars-sun │ │ + [ 14b7d] jpl-mercury-ssb │ │ + [ 14b8d] vsop87-mercury │ │ + [ 14b9c] mercury-jpl │ │ + [ 14ba8] iau-prometheus │ │ + [ 14bb7] iau-ganymede │ │ + [ 14bc4] earth-p03lp │ │ + [ 14bd0] ScriptedOrbit generator function returned bad value.\n │ │ + [ 14c06] viewMat │ │ + [ 14c0e] Crt │ │ + [ 14c12] Cru │ │ + [ 14c16] AbsMag │ │ + [ 14c1d] SC │ │ + [ 14c20] SampledTrajectory │ │ + [ 14c32] EllipticalOrbit │ │ + [ 14c42] RotationOffset │ │ + [ 14c51] {}_vert.glsl │ │ + [ 14c5e] /***************************************************\n │ │ + [ 14c94] diff │ │ + [ 14c99] ringWidth │ │ + [ 14ca3] #extension GL_ARB_shader_texture_lod : enable\n │ │ + [ 14cd2] shininess │ │ + [ 14cdc] vec4 diff = vec4(ambientColor, opacity);\n │ │ + [ 14d06] * │ │ + [ 14d0a] set_vp(vec4(position.xyz, 1.0));\n │ │ + [ 14d2c] position = in_Position.xyz;\n │ │ + [ 14d4d] v_TexCoord0.st = │ │ + [ 14d63] rayleighH │ │ + [ 14d6d] sampler2D │ │ + [ 14d77] Fragment shader source:\n │ │ + [ 14d90] shadow *= 1.0 - shadowR;\n │ │ + [ 14daa] Oblateness │ │ + [ 14db5] Sunset │ │ + [ 14dbc] LunarLambert │ │ + [ 14dc9] OrbitBarycenter cycle detected │ │ + [ 14de8] AbsMag ignored on Barycenter │ │ + [ 14e05] Extinction │ │ + [ 14e10] Extinction ignored for stars close to the origin │ │ + [ 14e41] tex │ │ + [ 14e45] Error reading PNG image file {}\n │ │ + [ 14e66] Failed to read chunk type\n │ │ + [ 14e81] Chunk size {} too small to include header\n │ │ + [ 14eac] Failed to read element {} of mesh matrix\n │ │ + [ 14ed6] Content size {} too small to include float color\n │ │ + [ 14f08] Processing IntPercentage chunk\n │ │ + [ 14f28] ()J │ │ + [ 14f2c] zh_CN │ │ + [ 14f32] boolean │ │ + [ 14f3a] startTime │ │ + [ 14f44] flushTasks │ │ + [ 14f4f] GL_ARB_shading_language_100 │ │ + [ 14f6b] Missing Huffman code table entry │ │ + [ 14f8c] Empty input file │ │ + [ 14f9d] Scan script does not transmit all data │ │ + [ 14fc4] End Of Image │ │ + [ 14fd1] RST%d │ │ + [ 14fd7] Component %d: dc=%d ac=%d │ │ + [ 14ff5] Corrupt JPEG data: %u extraneous bytes before marker 0x%02x │ │ + [ 15031] adobe │ │ + [ 15037] ItalicAngle │ │ + [ 15043] isFixedPitch │ │ + [ 15050] lenIV │ │ + [ 15056] %!PS-Adobe-3.0 Resource-CIDFont │ │ + [ 15076] FACE_NAME │ │ + [ 15080] QUAD_WIDTH │ │ + [ 1508b] SUPERSCRIPT_X │ │ + [ 1509c] � � │ │ + [ 150b1] � │ │ + [ 150b6] StartAxis │ │ + [ 150c0] 0123456789abcdefpx │ │ + [ 150d3] if │ │ + [ 150d6] in │ │ + [ 150d9] ... │ │ + [ 150dd] union │ │ + [ 150e3] %s at line %d │ │ + [ 150f1] inconsistent rendering intents │ │ + [ 15110] internal error handling cHRM->XYZ │ │ + [ 15132] inconsistent chromaticities │ │ + [ 1514e] Missing PLTE before IDAT │ │ + [ 15167] png_start_read_image/png_read_update_info: duplicate call │ │ + [ 151a1] gray+alpha color-map: too few entries │ │ + [ 151c7] non-positive width │ │ + [ 151da] bad height format │ │ + [ 151ec] Invalid sCAL width ignored │ │ + [ 15207] png_image_write_to_file: incorrect PNG_IMAGE_VERSION │ │ + [ 1523c] Writing zero-length unknown chunk │ │ + [ 1525e] memory image too large │ │ + [ 15275] ICC profile too short │ │ + [ 1528b] tEXt: invalid keyword │ │ + [ 152a1] deflateEnd failed (ignored) │ │ + [ 152bd] erract_c │ │ + [ 152c6] furnsh_c │ │ + [ 152cf] Invalid Endpoints--Left Endpoint Exceeds Right Endpoint │ │ + [ 15307] SPICE(DATATYPENOTRECOG) │ │ + [ 1531f] Invalid embedded blank was found in character string │ │ + [ 15354] SPICE(INVALIDCHECKOUT) │ │ + [ 1536b] Specification of Time String Format Was Not Recognized │ │ + [ 153a2] Window Does Not Contain Interval Corresponding to the Supplied Index │ │ + [ 153e7] SPICE(UNITSNOTREC) │ │ + [ 153fa] Cardinality of Output Window is Too Small │ │ + [ 15424] Input Vector is the Zero Vector │ │ + [ 15444] kdata_c │ │ + [ 1544c] PATH_SYMBOLS │ │ + [ 15459] In meta-kernel <#>, the file name at index # in the KERNELS_TO_LOAD list has length # characters; the limit is # characters. │ │ + [ 154d6] DSK │ │ + [ 154da] SPICE(CKBOGUSENTRY) │ │ + [ 154ee] invalid array section │ │ + [ 15504] %s: %s\n │ │ + [ 1550c] COPYI │ │ + [ 15512] TABLE_LIST_FULL │ │ + [ 15522] cnams │ │ + [ 15528] The EK file # could not be loaded; the maximum number of columns havingdistinct attributes has already been reached. │ │ + [ 1559d] ldrec │ │ + [ 155a3] Attempt to update file record failed. File was '#'. Value of IOSTAT was '#'. │ │ + [ 155f1] SPICE(INVALIDHANDLE) │ │ + [ 15606] dasa2l_ │ │ + [ 1560e] SPICE(DASNOSUCHADDRESS) │ │ + [ 15626] DASWBR │ │ + [ 1562d] EXPOOL │ │ + [ 15634] uvalue │ │ + [ 1563b] eqchr_ │ │ + [ 15642] typeid │ │ + [ 15649] REPMOT │ │ + [ 15650] ONE │ │ + [ 15654] TWELFTH │ │ + [ 1565c] REPSUB error: LEFT (#) must not be less than 1. │ │ + [ 1568c] [ │ │ + [ 1568e] SCLK │ │ + [ 15693] CKE05 │ │ + [ 15699] yvals │ │ + [ 1569f] , │ │ + [ 156a1] frmchg_ │ │ + [ 156a9] dpjan0 │ │ + [ 156b0] Epoch before │ │ + [ 156be] wc │ │ + [ 156c1] The eccentricity supplied for a type 15 segment is negative. It must be non-negative. The value supplied to the type 15 evaluator was #. │ │ + [ 1574c] body-fixed frame │ │ + [ 1575d] ; popped name is │ │ + [ 1576f] JDTDT │ │ + [ 15775] Relational operator, *, is not recognized. │ │ + [ 157a0] vhatg_ │ │ + [ 157a7] WRLINE: Maximum number of logical units that can be allocated by SPICELIB has already been reached │ │ + [ 1580a] no comma │ │ + [ 15813] drdtrt │ │ + [ 1581a] The block size is not positive. The block size is #. │ │ + [ 1584f] defcod │ │ + [ 15856] There is no room available for adding '#' to the list of name/code pairs. The number of names that can be supported is #. This number has been reached. │ │ + [ 158f1] zzdafgfr_ │ │ + [ 158fb] ZZDASGRD │ │ + [ 15904] Attempt to open file, '$' for % access failed. IOSTAT was #. │ │ + [ 15941] Attempt to open file, '#', for write access has failed. This file utilizes an unknown binary file format. This error may result from attempting to open a corrupt file or one of an unknown type. │ │ + [ 15a05] ZZDDHRMU │ │ + [ 15a0e] itmvec │ │ + [ 15a15] Definition of frame # specifies frame center # and obliquity model #. This obliquity model is not applicable to body #. This situation is usually caused by an error in a frame kernel in which the frame is defined. │ │ + [ 15aec] coeffs │ │ + [ 15af3] ZZDYNFID │ │ + [ 15afc] ? │ │ + [ 15b00] SPICE(NOCLASS) │ │ + [ 15b0f] ZZEKIXLK │ │ + [ 15b18] Number tables in first join row set was #; valid range is 1:# │ │ + [ 15b56] zzekjsqz_ │ │ + [ 15b60] Constraint index # is out of valid range 1:#. │ │ + [ 15b8e] The relational operator # was not recognized or was not applicable for data type #. │ │ + [ 15be2] IAU_TAYGETE │ │ + [ 15bee] IAU_STEINS │ │ + [ 15bf9] MOON │ │ + [ 15bfe] ANANKE │ │ + [ 15c05] METIS │ │ + [ 15c0b] AUTONOE │ │ + [ 15c13] NEPTUNE │ │ + [ 15c1b] P6 │ │ + [ 15c1e] MAGELLAN │ │ + [ 15c27] LCROSS │ │ + [ 15c2e] LUCY │ │ + [ 15c33] CHANDRAYAAN-1 │ │ + [ 15c41] TRMM │ │ + [ 15c46] EXM RSP SP │ │ + [ 15c51] GLL PROBE │ │ + [ 15c5b] CROMMELIN │ │ + [ 15c65] PONS-WINNECKE │ │ + [ 15c73] WIRTANEN │ │ + [ 15c7c] MUELLER 2 │ │ + [ 15c86] DAVIDA │ │ + [ 15c8d] PARKES │ │ + [ 15c94] SPICE(NOSUCHFILE) │ │ + [ 15ca6] ZZPRSCOR │ │ + [ 15caf] ZZREFCH1 │ │ + [ 15cb8] There is a quoted string with no characters on line # of the text kernel file '#'. │ │ + [ 15d0c] Encountered '#' while attempting to parse a time on line # of the text kernel file '#'. Error message: '#' │ │ + [ 15d78] miY> │ │ + [ 15d7d] imY │ │ + [ 15d81] Field count was not found for SCLK #. │ │ + [ 15da7] The routine ZZSGP4 is an umbrella for the SGP4 initializer and propagator entry points. Do not call ZZSGP4. It is likely that a programming error has been made. │ │ + [ 15e48] daytab │ │ + [ 15e4f] The string supplied to specify the reference frame, ('#') contains non-printing characters. The two most common causes for this kind of error are: 1. an error in the call to ZZSPKGO0; 2. an uninitialized variable. │ │ + [ 15f27] ZZSWFINI │ │ + [ 15f30] FRAME_#_START │ │ + [ 15f3e] SPICE(TOOMANYBASEFRAMES) │ │ + [ 15f57] Start time kernel variable # exists but DTPOOL returned data type # rather than one of the expected values: 'C' or 'N'. │ │ + [ 15fcf] The Year may be abbreviated only if the year belongs to the Christian Era (A.D.) │ │ + [ 16021] The default value assigned to the time system must be one of 'UTC', 'TDT', 'TT', or 'TDB'. The value supplied was '#'. │ │ + [ 16099] SPICE(OUTPUTTOOSHORT) │ │ + [ 160af] Day of Month │ │ + [ 160bc] An unexpected # ("#") was encountered in the time string: │ │ + [ 160f7] Two substrings indicating a day of year were identified in the input time string <#> and <#>: " │ │ + [ 16157] A month was identified in the time string "#", but a day of month could not be identified. │ │ + [ 161b3] Yiii:n │ │ + [ 161ba] YDm │ │ + [ 161be] i-Ydi:i │ │ + [ 161c6] i:iimY │ │ + [ 161cd] iiYi:n │ │ + [ 161d4] i/i/Y/i:n │ │ + [ 161de] Y*m*D*H*M* │ │ + [ 161e9] Y*y*H* │ │ + [ 161f0] angrt │ │ + [ 161f6] collation │ │ + [ 16200] NH │ │ + [ 16203] hsn │ │ + [ 16207] ar │ │ + [ 1620a] ary │ │ + [ 1620e] bas │ │ + [ 16212] bo │ │ + [ 16215] br │ │ + [ 16218] ckb │ │ + [ 1621c] fo │ │ + [ 1621f] frr │ │ + [ 16223] jrb │ │ + [ 16227] kab │ │ + [ 1622b] kfo │ │ + [ 1622f] kho │ │ + [ 16233] khq │ │ + [ 16237] kmb │ │ + [ 1623b] lag │ │ + [ 1623f] lfn │ │ + [ 16243] lij │ │ + [ 16247] mdr │ │ + [ 1624b] nwc │ │ + [ 1624f] pau │ │ + [ 16253] pfl │ │ + [ 16257] sli │ │ + [ 1625b] tly │ │ + [ 1625f] zap │ │ + [ 16263] zgh │ │ + [ 16267] ces │ │ + [ 1626b] hin │ │ + [ 1626f] nbl │ │ + [ 16273] BM │ │ + [ 16276] BW │ │ + [ 16279] GA │ │ + [ 1627c] KE │ │ + [ 1627f] MW │ │ + [ 16282] MX │ │ + [ 16285] PS │ │ + [ 16288] RW │ │ + [ 1628b] SL │ │ + [ 1628e] AGO │ │ + [ 16292] CAF │ │ + [ 16296] CRQ │ │ + [ 1629a] CRI │ │ + [ 1629e] SGS │ │ + [ 162a2] HND │ │ + [ 162a6] IDN │ │ + [ 162aa] IRL │ │ + [ 162ae] ISL │ │ + [ 162b2] JEY │ │ + [ 162b6] MLI │ │ + [ 162ba] QAT │ │ + [ 162be] SAU │ │ + [ 162c2] SYR │ │ + [ 162c6] fil_PH │ │ + [ 162cd] variant │ │ + [ 162d5] __system_property_get │ │ + [ 162eb] YAKST │ │ + [ 162f1] Asia/Baku │ │ + [ 162fb] BST │ │ + [ 162ff] America/Scoresbysund │ │ + [ 16314] Canada/Atlantic │ │ + [ 16324] en_MH │ │ + [ 1632a] es_CO │ │ + [ 16330] mn_Cyrl │ │ + [ 16338] qu_BO │ │ + [ 1633e] tt_RU │ │ + [ 16344] yi_001 │ │ + [ 1634b] i-enochian │ │ + [ 16356] csn │ │ + [ 1635a] sgn-dk │ │ + [ 16361] sgn-ie │ │ + [ 16368] psr │ │ + [ 1636c] ures_swap().udata_swapInvStringBlock(keys[%d]) failed\n │ │ + [ 163a3] ures_swapResource(array res=%08x)[%d].recurse(%08x) failed\n │ │ + [ 163df] ucol_swap(formatVersion=4): unknown data at IX_RESERVED10_OFFSET\n │ │ + [ 16421] supplementalData │ │ + [ 16432] icudt75l-curr │ │ + [ 16440] U_MESSAGE_PARSE_ERROR │ │ + [ 16456] U_MF_UNSUPPORTED_EXPRESSION_ERROR │ │ + [ 16478] AOK │ │ + [ 1647c] ARA │ │ + [ 16480] BGL │ │ + [ 16484] CNX │ │ + [ 16488] IRR │ │ + [ 1648c] LUC │ │ + [ 16490] LYD │ │ + [ 16494] MVR │ │ + [ 16498] OMR │ │ + [ 1649c] RSD │ │ + [ 164a0] RUR │ │ + [ 164a4] SKK │ │ + [ 164a8] SLL │ │ + [ 164ac] XFU │ │ + [ 164b0] date │ │ + [ 164b5] INFINITY │ │ + [ 164be] dunam │ │ + [ 164c4] AYM │ │ + [ 164c8] CSJ │ │ + [ 164cc] ZWC │ │ + [ 164d0] dot-per-inch │ │ + [ 164dd] atmosphere │ │ + [ 164e8] acre-foot │ │ + [ 164f2] cubic-inch │ │ + [ 164fd] gallon-imperial │ │ + [ 1650d] tablespoon │ │ + [ 16518] genitive │ │ + [ 16521] few │ │ + [ 16525] ronto │ │ + [ 1652b] Week │ │ + [ 16530] -short │ │ + [ 16537] -narrow │ │ + [ 1653f] grouping │ │ + [ 16548] reset secondary-before secondary ignorable not possible │ │ + [ 16580] secondary tailoring gap too small │ │ + [ 165a2] alternateQuotationStart │ │ + [ 165ba] ()F │ │ + [ 165be] Anti-aliasing disabled │ │ + [ 165d5] Auto-magnitude disabled │ │ + [ 165ed] Could not find locale, falling back to classic.\n │ │ + [ 1661e] format specifier requires numeric argument │ │ + [ 16649] cannot switch from manual to automatic argument indexing │ │ + [ 16682] StarTextures │ │ + [ 1668f] A │ │ + [ 16691] Distance │ │ + [ 1669a] km │ │ + [ 1669d] base │ │ + [ 166a2] Depth component: %s\n │ │ + [ 166b7] Max anisotropy filtering: %s\n │ │ + [ 166d5] F11 Start/Pause F12 Stop │ │ + [ 166f1] catalog^Ddeep sky │ │ + [ 16702] star │ │ + [ 16707] 0.11.21 │ │ + [ 1670f] Buffer Size: %d*%d (%d)\n │ │ + [ 1672c] CHANNEL_SIDE_LEFT │ │ + [ 1673e] Invalid file │ │ + [ 1674b] Memory already mapped │ │ + [ 16761] SL_IID_ANDROIDCONFIGURATION │ │ + [ 1677d] [OpenSL] Cannot find symbol slCreateEngine. │ │ + [ 167a9] &ver= │ │ + [ 167af] oy │ │ + [ 167b2] crimson │ │ + [ 167ba] cyan │ │ + [ 167bf] darkslategray │ │ + [ 167cd] lime │ │ + [ 167d2] midnightblue │ │ + [ 167df] orangered │ │ + [ 167e9] {}{} │ │ + [ 167ee] "/:<>?\| │ │ + [ 167f7] ecliptic │ │ + [ 16800] insula │ │ + [ 16807] sulcus │ │ + [ 1680e] selectioncursor │ │ + [ 1681e] capture │ │ + [ 16826] timerate │ │ + [ 1682f] orbit │ │ + [ 16835] xrot │ │ + [ 1683a] render │ │ + [ 16841] requestkeyboard │ │ + [ 16851] findcategory │ │ + [ 1685e] Bad method call! │ │ + [ 1686f] fuzzy │ │ + [ 16875] screenshot-{}{:06i} │ │ + [ 16889] mousedown │ │ + [ 16893] l │ │ + [ 16895] Internal Error: Invalid table entry in checkTimeslice │ │ + [ 168cb] Timeout: script hasn't returned control to celestia (forgot to call wait()?) │ │ + [ 16918] to │ │ + [ 1691b] Position or rotation expected as second argument to frame:from() │ │ + [ 1695c] Frustum │ │ + [ 16964] argument 1 to gl.TexParameter must be a number │ │ + [ 16993] argument 2 to gl.TexParameter must be a number │ │ + [ 169c2] argument 1 to gl.BlendFunc must be a number │ │ + [ 169ee] removereferencemark │ │ + [ 16a02] bodyframe │ │ + [ 16a0c] setatmosphere │ │ + [ 16a1a] location │ │ + [ 16a23] dwarfplanet │ │ + [ 16a2f] parent │ │ + [ 16a36] Argument to object:catalognumber must be a string │ │ + [ 16a68] getframe │ │ + [ 16a71] makeactiveview │ │ + [ 16a80] timespan │ │ + [ 16a89] Internal error: couldn't get metatable │ │ + [ 16ab0] setaxisangle │ │ + [ 16abd] No arguments expected for vector:gety │ │ + [ 16ae3] Unknown error loading hook script │ │ + [ 16b05] texcoord2 │ │ + [ 16b0f] linestrip │ │ + [ 16b19] diffuse {} {} {}\n │ │ + [ 16b2b] normal\n │ │ + [ 16b33] mimas │ │ + [ 16b39] jpl-earth-emb │ │ + [ 16b47] jpl-pluto-ssb │ │ + [ 16b55] iau-phobos │ │ + [ 16b60] Unsupported byte order {}, expected {} in {}.\n │ │ + [ 16b8f] tidalSize │ │ + [ 16b99] scale │ │ + [ 16b9f] largestar │ │ + [ 16ba9] Cnc │ │ + [ 16bad] PsA │ │ + [ 16bb1] Sge │ │ + [ 16bb5] .* │ │ + [ 16bb8] Open cluster │ │ + [ 16bc5] Bad spice orbit\n │ │ + [ 16bd6] Missing coordinates for FixedPosition\n │ │ + [ 16bfd] RelativeVelocity │ │ + [ 16c0e] vec3 ringShadowProj;\n │ │ + [ 16c24] float NV = dot(N, eyeDir);\n │ │ + [ 16c40] vec3 H;\n │ │ + [ 16c49] totalLight += l * │ │ + [ 16c5c] vec4 overlayColor = texture2D(overlayTex, overlayTexCoord.st);\n │ │ + [ 16c9c] scatterEx │ │ + [ 16ca6] gl_FragColor.rgb = gl_FragColor.rgb * scatterEx + scatterColor;\n │ │ + [ 16ce7] shadowCenter │ │ + [ 16cf4] mieK │ │ + [ 16cf9] pointFade = 1.0;\n │ │ + [ 16d0b] line_strip │ │ + [ 16d16] ReferencePoint │ │ + [ 16d25] No valid orbit specified for object '{}'. Skipping.\n │ │ + [ 16d5a] Error: Beginning can only be specified for initial phase of timeline.\n │ │ + [ 16da1] Lower │ │ + [ 16da7] Inner │ │ + [ 16dad] BumpHeight │ │ + [ 16db8] III │ │ + [ 16dbc] Texture is ignored on Barycenters │ │ + [ 16dde] {}1 {} A │ │ + [ 16de7] ()D │ │ + [ 16deb] (JI)V │ │ + [ 16df1] ,\n │ │ + [ 16df4] [\n │ │ + [ 16df7] No known providers. This is likely a bug in libepoxy code generation\n │ │ + [ 16e42] %s() not found: %s\n │ │ + [ 16e56] int epoxy_egl_version(EGLDisplay) │ │ + [ 16e78] Too many color components: %d, max %d │ │ + [ 16e9e] Bogus DAC index %d │ │ + [ 16eb1] %3d %3d %3d %3d %3d %3d %3d %3d │ │ + [ 16ed9] JFIF extension marker: type 0x%02x, length %u │ │ + [ 16f07] Corrupt JPEG data: premature end of data segment │ │ + [ 16f38] Component index %d: mismatching sampling ratio %d:%d, %d:%d, %c │ │ + [ 16f78] resource.frk/ │ │ + [ 16f86] /sfnts │ │ + [ 16f8d] FDBytes │ │ + [ 16f95] pcf │ │ + [ 16f99] IRV │ │ + [ 16fa1] � │ │ + [ 16faa] � │ │ + [ 16fb2] � │ │ + [ 16fb7] raster1 │ │ + [ 16fbf] svg-hooks │ │ + [ 16fc9] Version │ │ + [ 16fd1] WX │ │ + [ 16fd4] function │ │ + [ 16fdd] ^$*+?.([%- │ │ + [ 16fe8] global │ │ + [ 16fef] stack traceback: │ │ + [ 17004] $^P^H^T^X^\^F^P^F^X^X^\ $(,^F^H^H^H^L │ │ + [ 1701a] -> │ │ + [ 1701d] LUA_CPATH │ │ + [ 17027] short_src │ │ + [ 17031] isvararg │ │ + [ 1703a] activelines │ │ + [ 17046] exceeds application limits │ │ + [ 17061] MNG features are not allowed in a PNG datastream │ │ + [ 17092] Not recognizing known sRGB profile that has been edited │ │ + [ 170ca] bad encoding (internal error) │ │ + [ 170e8] unknown compression type │ │ + [ 17101] insufficient memory to read chunk │ │ + [ 17123] cHRM Blue X │ │ + [ 1712f] image row stride too large │ │ + [ 1714a] Invalid sBIT depth specified │ │ + [ 17167] card_c │ │ + [ 1716e] SPICE(INVALIDACTION) │ │ + [ 17183] The Value in the Kernel File was Expected to be a date. │ │ + [ 171bb] An Invalid Function Argument was Supplied │ │ + [ 171e5] An Invalid Epoch Type Specification Was Supplied │ │ + [ 17216] SPICE(NUMBEREXPECTED) │ │ + [ 1722c] SPICE(WRITEERROR) │ │ + [ 1723e] files │ │ + [ 17244] DAFHOF │ │ + [ 1724b] SEQUENTIAL │ │ + [ 17256] variable count incorrect │ │ + [ 1726f] can't read file │ │ + [ 1727f] lately %s %s %s %s │ │ + [ 17292] IO │ │ + [ 17296] DAFRCR │ │ + [ 1729d] ivals │ │ + [ 172a3] SPICE(DASFTFULL) │ │ + [ 172b4] nw │ │ + [ 172b7] The file type contains nonprinting characters. │ │ + [ 172e7] DASUFS │ │ + [ 172ee] SPICE(DASNOSUCHFILE) │ │ + [ 17303] SPICE(DASINVALIDTYPE) │ │ + [ 17319] poold │ │ + [ 1731f] Could not read DAS double precision record. File = # Record number = #. IOSTAT = #. │ │ + [ 17373] Could not write DAS character record. File = # Record number = #. IOSTAT = #. │ │ + [ 173c4] NEW BODY │ │ + [ 173cd] writing a variable to the output kernel file │ │ + [ 173fb] This is never supposed to happen. The requested name, '#', was found in the name list, but the pointer to the head of the data for this variable is zero. Please note your activities and report this error to NAIF. │ │ + [ 174d2] LMPOOL │ │ + [ 174d9] ELEMC │ │ + [ 174df] \begindata │ │ + [ 174ea] Invalid frame specification found in kernel pool: frame class keyword is # but associated frame name assignment was not found. │ │ + [ 17569] BODC2N │ │ + [ 17570] BILLION │ │ + [ 17578] del │ │ + [ 1757c] This segment reports that it has # meta data items. Every generic segment must have at least #. │ │ + [ 175dc] xmeta │ │ + [ 175e2] XFR │ │ + [ 175e6] NIP │ │ + [ 175ea] ) │ │ + [ 175ec] SPICE(SPKINSUFFDATA) │ │ + [ 17601] SPICE(NONPOSITIVEMASS) │ │ + [ 17618] The periapsis and trajectory pole vectors are not orthogonal. The anglebetween them is # degrees. │ │ + [ 1767b] sb2rv │ │ + [ 17681] SPKE02 │ │ + [ 17688] SPKE12 │ │ + [ 1768f] SPKR02 │ │ + [ 17696] tsipm │ │ + [ 1769c] The variable # could not be found in the kernel pool. │ │ + [ 176d2] idents │ │ + [ 176d9] => │ │ + [ 176dc] otherwise corrupted---or deleting previous │ │ + [ 17707] invalid integer │ │ + [ 17717] no real part │ │ + [ 17724] A subsystem state counter overflowed. For this to happen there must be a SPICE bug or you must have been running your SPICE-based application for a very long time. Please contact NAIF.and report the circumstances under which this happened. │ │ + [ 17814] File '#' already loaded. │ │ + [ 1782d] ftmnm │ │ + [ 17833] Attempt to reconnect logical unit to file '#' failed. IOSTAT was #. │ │ + [ 17877] ZZDDHINI │ │ + [ 17880] ZZDDHGTU │ │ + [ 17889] zzddhnfc_ │ │ + [ 17893] Unable to determine the binary file format of DAF '#'. │ │ + [ 178ca] ZZDSKSNS ran out of segment table room while trying to append to the tail of the segment list for body #. Current state is ADD TO END. │ │ + [ 17951] ZZDSKCHK │ │ + [ 1795a] itmfrm │ │ + [ 17961] TARGET │ │ + [ 17968] LATITUDE │ │ + [ 17971] Definition of frame # specifies frame center # and nutation model #. This nutation model is not applicable to body #. This situation is usually caused by an error in a frame kernel in which the frame is defined. │ │ + [ 17a46] FROM_FRAMES │ │ + [ 17a52] The kernel variable # used to define frame # is assigned the character value #. This value was expected to be a reference frame name, but NAMFRM cannot translate this name to a frame ID code. │ │ + [ 17b13] SPICE(BADAXISLENGTH) │ │ + [ 17b28] zzdynrot_ │ │ + [ 17b32] SPICE(BADSUBSTRINGBOUNDS) │ │ + [ 17b4c] ZZEKJOIN │ │ + [ 17b55] rsdsc │ │ + [ 17b5b] ZZEKQSEL │ │ + [ 17b64] ZZEKPGAL │ │ + [ 17b6d] Attempt to free non-existent CHR page. Page number = #; valid range is 1:# │ │ + [ 17bb8] Statistic # is not supported. │ │ + [ 17bd6] ZZEKVCAL │ │ + [ 17bdf] ZZEKVMCH │ │ + [ 17be8] EK = #; COLIDX = #; ROW = #; ELTIDX = #. Column entry element was not found. │ │ + [ 17c38] IAU_JUPITER_BARYCENTER │ │ + [ 17c4f] IAU_BORRELLY │ │ + [ 17c5c] MARS_BARYCENTER │ │ + [ 17c6c] SINOPE │ │ + [ 17c73] CARPO │ │ + [ 17c79] DAPHNIS │ │ + [ 17c81] ANTHE │ │ + [ 17c87] CORDELIA │ │ + [ 17c90] CALIBAN │ │ + [ 17c98] FERDINAND │ │ + [ 17ca2] BEPICOLOMBO MMO │ │ + [ 17cb2] SIRTF │ │ + [ 17cb8] MPL │ │ + [ 17cbc] EXM SPACECRAFT COMPOSITE │ │ + [ 17cd5] EXOMARS SP │ │ + [ 17ce0] CLUSTER 3 │ │ + [ 17cea] SHOEMAKER-LEVY 9-W │ │ + [ 17cfd] CLARK │ │ + [ 17d03] GEHRELS 3 │ │ + [ 17d0d] KOPFF │ │ + [ 17d13] TUTTLE │ │ + [ 17d1a] WILSON-HARRINGTON │ │ + [ 17d2c] POLYMELE │ │ + [ 17d35] zzmsxf_ │ │ + [ 17d3d] ZZSHSH │ │ + [ 17d44] SPICE(BADVARASSIGN) │ │ + [ 17d58] Oi │ │ + [ 17d5b] yY* │ │ + [ 17d5f] Ydi │ │ + [ 17d63] zzrvbf_ │ │ + [ 17d6b] There is a non-printing character embedded in line # of the text buffer. Non-printing characters are not allowed in kernel variable assignments. The non-printing character has ASCII code #. │ │ + [ 17e2c] The kernel variable # has been set up as a numeric or time variable. However, the value that you are attempting to assign to this variable on line # of the kernel buffer is not a numeric or time value. │ │ + [ 17ef8] SPICE(TOOMANYCOEFFS) │ │ + [ 17f0d] SPICE(KERNELVARTOOLARGE) │ │ + [ 17f26] SCLI01 │ │ + [ 17f2d] JDUTC │ │ + [ 17f33] ZZSPKGO1 │ │ + [ 17f3c] Target range rate magnitude is approximately the speed of light. The light time derivative cannot be computed. │ │ + [ 17fab] tvec │ │ + [ 17fb0] The input time string '#' cannot be processed because it contains more than @ recognizable tokens. The token that could not be processed was '#'. │ │ + [ 18042] CDT │ │ + [ 18046] Yidi:i:n │ │ + [ 1804f] Yimi │ │ + [ 18054] i-i-iti:i:n │ │ + [ 18060] i-idi:i:i │ │ + [ 1806a] H*M*SmDY │ │ + [ 18073] iiY │ │ + [ 18077] iiYn │ │ + [ 1807c] iimi │ │ + [ 18081] DmH*M*SY │ │ + [ 1808a] imiiin │ │ + [ 18091] miYi:i:n │ │ + [ 1809a] mii:i:nY │ │ + [ 180a3] Y-i-iti │ │ + [ 180ab] i:i:ni/i/i │ │ + [ 180b6] i:ii/i/Y │ │ + [ 180bf] ZZXLATED │ │ + [ 180c8] FX │ │ + [ 180cb] art__LOJBAN │ │ + [ 180d7] ach │ │ + [ 180db] dar │ │ + [ 180df] de │ │ + [ 180e2] krj │ │ + [ 180e6] ltg │ │ + [ 180ea] lua │ │ + [ 180ee] luo │ │ + [ 180f2] mfe │ │ + [ 180f6] nyo │ │ + [ 180fa] rn │ │ + [ 180fd] sd │ │ + [ 18100] cre │ │ + [ 18104] eng │ │ + [ 18108] gla │ │ + [ 1810c] ibo │ │ + [ 18110] cor │ │ + [ 18114] ori │ │ + [ 18118] tel │ │ + [ 1811c] twi │ │ + [ 18120] AW │ │ + [ 18123] JE │ │ + [ 18126] KI │ │ + [ 18129] TW │ │ + [ 1812c] UG │ │ + [ 1812f] AFG │ │ + [ 18133] ASM │ │ + [ 18137] ERI │ │ + [ 1813b] GHA │ │ + [ 1813f] GNQ │ │ + [ 18143] ISR │ │ + [ 18147] da_DK │ │ + [ 1814d] kk_KZ │ │ + [ 18153] ro_RO │ │ + [ 18159] tk_TM │ │ + [ 1815f] PETST │ │ + [ 18165] ULAT │ │ + [ 1816a] languageAliases │ │ + [ 1817a] en_ID │ │ + [ 18180] en_IN │ │ + [ 18186] es_CU │ │ + [ 1818c] es_EC │ │ + [ 18192] fr_MA │ │ + [ 18198] la_001 │ │ + [ 1819f] mn_Mong │ │ + [ 181a7] ures_swap(): resource top %d exceeds bundle length %d\n │ │ + [ 181de] ures_swap(): unable to allocate memory for tracking resources\n │ │ + [ 1821d] ucol_strcollIter │ │ + [ 1822e] night2 │ │ + [ 18235] indian │ │ + [ 1823c] Countries │ │ + [ 18246] parseRegions │ │ + [ 18253] {0}, {1} │ │ + [ 1825c] other number │ │ + [ 18269] U_STRING_NOT_TERMINATED_WARNING │ │ + [ 18289] U_TRAILING_BACKSLASH │ │ + [ 1829e] U_INVALID_RBT_SYNTAX │ │ + [ 182b3] AUD │ │ + [ 182b7] BAM │ │ + [ 182bb] CLE │ │ + [ 182bf] KHR │ │ + [ 182c3] MGA │ │ + [ 182c7] MTL │ │ + [ 182cb] RHD │ │ + [ 182cf] SOS │ │ + [ 182d3] SYP │ │ + [ 182d7] scientificFormat │ │ + [ 182e8] M02L │ │ + [ 182ed] milligram-ofglucose-per-deciliter │ │ + [ 1830f] liter-per-100-kilometer │ │ + [ 18327] GNE │ │ + [ 1832b] petabyte │ │ + [ 18334] day-person │ │ + [ 1833f] kilowatt-hour │ │ + [ 1834d] earth-mass │ │ + [ 18358] pinch │ │ + [ 1835e] pow10- │ │ + [ 18365] compound │ │ + [ 1836e] unit-narrow │ │ + [ 1837a] /decimalFormat │ │ + [ 18389] yes │ │ + [ 1838d] ucadata │ │ + [ 18395] reset position maps to too many collation elements (more than 31) │ │ + [ 183d7] LDML forbids tailoring to U+FFFF │ │ + [ 183f8] lb_to_kg │ │ + [ 18401] speed_of_light_meters_per_second │ │ + [ 18422] AChoreographerFrameCallbackData_getPreferredFrameTimelineIndex │ │ + [ 18461] mPipelineModeAutoMode │ │ + [ 18477] Swappy: GPU frame time │ │ + [ 1848e] View too small to be split │ │ + [ 184a9] cannot switch from automatic to manual argument indexing │ │ + [ 184e2] {} must be an array of strings.\n │ │ + [ 18503] Target │ │ + [ 1850a] Error parsing favorites file.\n │ │ + [ 18529] Point size granularity: %s\n │ │ + [ 18545] {}\n │ │ + [ 1854d] inf │ │ + [ 18551] Time stopped │ │ + [ 18561] CHANNEL_TOP_BACK_LEFT │ │ + [ 18577] Too large │ │ + [ 18581] NULL Playback Device │ │ + [ 18596] Failed to retrieve data buffer connector. Unknown data supply type.\n │ │ + [ 185db] ICMT │ │ + [ 185e0] ^I │ │ + [ 185e3] URL must have at least mode and time!\n │ │ + [ 1860a] tsrc │ │ + [ 1860f] failed to format time │ │ + [ 18625] Jul │ │ + [ 18629] text │ │ + [ 1862e] azure │ │ + [ 18634] cadetblue │ │ + [ 1863e] cornsilk │ │ + [ 18647] gray │ │ + [ 1864c] maroon │ │ + [ 18653] .png │ │ + [ 18658] .ctx │ │ + [ 1865d] XI │ │ + [ 18660] TAU │ │ + [ 1866e] Comet │ │ + [ 18674] regio │ │ + [ 1867a] synchronous │ │ + [ 18686] filename │ │ + [ 1868f] longitude │ │ + [ 18699] downarrow │ │ + [ 186a3] row │ │ + [ 186a7] xoffset │ │ + [ 186af] colorbottom │ │ + [ 186bb] createchild │ │ + [ 186c7] getlinecolor │ │ + [ 186d4] getfaintestvisible │ │ + [ 186e7] getsystemtime │ │ + [ 186f5] No arguments expected for celestia:getrenderflags() │ │ + [ 18729] One argument expected for celestia:setfaintestvisible() │ │ + [ 18761] Argument to celestia:setstarstyle must be a string │ │ + [ 18794] First argument to celestia:seturl must be a string │ │ + [ 187c7] Function celestia:seekaudio requires two arguments │ │ + [ 187fa] mouseup │ │ + [ 18802] Oops, expected savedrenderflags to be userdata\n │ │ + [ 18832] class_phase │ │ + [ 1883e] No arguments expected for frame:getcoordinatesystem() │ │ + [ 18874] Begin │ │ + [ 1887a] TEXTURE_MIN_FILTER │ │ + [ 1888d] argument 4 to gl.Frustum must be a number │ │ + [ 188b7] argument 1 to gl.Vertex must be a number │ │ + [ 188e0] catalognumber │ │ + [ 188ee] globular │ │ + [ 188f7] First arg to observer:gotoobject must be object or position │ │ + [ 18933] Second arg to observer:gotodistance must be a number │ │ + [ 18968] Argument to observer:setpos must be a rotation │ │ + [ 18997] One argument expected to observer:getsurface() │ │ + [ 189c6] Bad vector addition! │ │ + [ 189db] Need two operands for sub │ │ + [ 189f5] hook thread failed\n │ │ + [ 18a09] emissivemap │ │ + [ 18a15] texcoord2 │ │ + [ 18a20] ganymede │ │ + [ 18a29] iapetus │ │ + [ 18a31] iau-mars │ │ + [ 18a3a] iau-jupiter │ │ + [ 18a46] colorTex │ │ + [ 18a4f] Error parsing asterism {} chain: expected string\n │ │ + [ 18a81] Aql │ │ + [ 18a85] Cae │ │ + [ 18a89] RA │ │ + [ 18a8c] GL_OES_vertex_array_object │ │ + [ 18aa7] AMD │ │ + [ 18aab] SU │ │ + [ 18aae] RotationPeriod │ │ + [ 18abd] PrecessionPeriod │ │ + [ 18ace] AU │ │ + [ 18ad1] GLSL │ │ + [ 18ad7] usesShadows = {}\n │ │ usesTangentSpaceLighting = {}\n │ │ hasEclipseShadows = {}\n │ │ hasRingShadows = {}\n │ │ hasSelfShadows = {}\n │ │ hasCloudShadows = {}\n │ │ hasSpecular = {}\n │ │ hasScattering = {}\n │ │ isViewDependent = {}\n │ │ lightModel = {:x}\n │ │ - [ 18ba1] diffTexCoord.x += textureOffset;\n │ │ - [ 18bc3] ringShadowLOD │ │ - [ 18bd1] float shadow;\n │ │ - [ 18be0] gl_FragColor += texture2D(nightTex, │ │ - [ 18c05] litSide │ │ - [ 18c0d] intensity = mix(intensity, intensity * (1.0 - opticalDepth), litSide);\n │ │ - [ 18c55] gl_FragColor = v_Color * texture2D(diffTex, gl_PointCoord);\n │ │ - [ 18c96] gl_FragColor = v_Color;\n │ │ - [ 18cb3] lineWidthY │ │ - [ 18cbe] specTex │ │ - [ 18cc6] light{}_halfVector │ │ - [ 18cd9] shadowTexCoord0 │ │ - [ 18ce9] in_ScaleFactor │ │ - [ 18cf9] if (cosNormalLightDir > 0.0)\n │ │ + [ 18bce] diffTexCoord.x += textureOffset;\n │ │ + [ 18bf0] ringShadowLOD │ │ + [ 18bfe] float shadow;\n │ │ + [ 18c0d] gl_FragColor += texture2D(nightTex, │ │ + [ 18c32] litSide │ │ + [ 18c3a] intensity = mix(intensity, intensity * (1.0 - opticalDepth), litSide);\n │ │ + [ 18c82] gl_FragColor = v_Color * texture2D(diffTex, gl_PointCoord);\n │ │ + [ 18cc3] gl_FragColor = v_Color;\n │ │ + [ 18ce0] lineWidthY │ │ + [ 18ceb] specTex │ │ + [ 18cf3] light{}_halfVector │ │ + [ 18d06] shadowTexCoord0 │ │ + [ 18d16] in_ScaleFactor │ │ + [ 18d26] if (cosNormalLightDir > 0.0)\n │ │ {{\n │ │ shadowMapCoeff = calculateShadow();\n │ │ diff.rgb *= shadowMapCoeff;\n │ │ {}\n │ │ }}\n │ │ - [ 18d6c] float distSun = -rq + d;\n │ │ - [ 18d8a] AltSurface │ │ - [ 18d95] Atmosphere must be an associative array.\n │ │ - [ 18dbf] CloudSpeed │ │ - [ 18dca] 6 │ │ - [ 18dcc] missing SpectralType on Star │ │ - [ 18de9] invalid filename in Texture │ │ - [ 18e05] Bad header for cross index\n │ │ - [ 18e21] Processing PointArray chunk\n │ │ - [ 18e3e] Processing MaterialMapname chunk\n │ │ - [ 18e60] Asteroids │ │ - [ 18e6a] Stopping renderer thread │ │ - [ 18e83] unmatched '}' in format string │ │ - [ 18ea2] Unknown Adobe color transform code %d │ │ - [ 18ec8] postscript-font-name │ │ - [ 18edd] random-seed │ │ - [ 18ee9] CharStrings │ │ - [ 18ef5] CIDFontType │ │ - [ 18f03] � │ │ - [ 18f0a] � │ │ - [ 18f13] � � │ │ - [ 18f1e] glyph-to-script-map │ │ - [ 18f32] StartKernData │ │ - [ 18f40] StartKernPairs1 │ │ - [ 18f50] VM handler failed: │ │ - [ 18f64] do │ │ - [ 18f67] │ │ - [ 18f6d] ;; │ │ - [ 18f70] %s.so │ │ - [ 18f76] invalid end points │ │ - [ 18f89] invalid length │ │ - [ 18f98] unexpected DeviceLink ICC profile class │ │ - [ 18fc0] gamma table being rebuilt │ │ - [ 18fda] 123456789 │ │ - [ 18fe4] ..Too many IDATs found │ │ - [ 18ffb] Read Error │ │ - [ 19006] gamma value │ │ - [ 19012] bad compression method │ │ - [ 19029] Insufficient memory for pCAL params │ │ - [ 1904d] Invalid iCCP compression method │ │ - [ 1906d] text chunk: out of memory │ │ - [ 19087] png_set_filler: inappropriate color type │ │ - [ 190b0] png_write_info was never called before png_write_row │ │ - [ 190e5] internal write transform logic error │ │ - [ 1910a] String "#" has length zero. │ │ - [ 19126] marker │ │ - [ 1912d] This Entry Point Contains No Executable Code │ │ - [ 1915a] Error Writing to Ephemeris File │ │ - [ 1917a] Name of Device Exceeds 128-Character Limit │ │ - [ 191a5] SPICE(KERNELVARNOTFOUND) │ │ - [ 191be] SPICE(NOSEGMENT) │ │ - [ 191cf] digits │ │ - [ 191d6] SPICE(NOMOREROOM) │ │ - [ 191e8] SPK │ │ - [ 191ec] DAF │ │ - [ 191f0] DAFOPN │ │ - [ 191f7] There is no file open with unit = # │ │ - [ 1921b] The file, '#', is not a DAF. │ │ - [ 19238] %s: end of file\n │ │ - [ 19249] cell │ │ - [ 1924e] DAFFA │ │ - [ 19254] #2 │ │ - [ 19257] │ │ + [ 18f9a] ;; │ │ + [ 18f9d] %s.so │ │ + [ 18fa3] invalid end points │ │ + [ 18fb6] invalid length │ │ + [ 18fc5] unexpected DeviceLink ICC profile class │ │ + [ 18fed] gamma table being rebuilt │ │ + [ 19007] 123456789 │ │ + [ 19011] ..Too many IDATs found │ │ + [ 19028] Read Error │ │ + [ 19033] gamma value │ │ + [ 1903f] bad compression method │ │ + [ 19056] Insufficient memory for pCAL params │ │ + [ 1907a] Invalid iCCP compression method │ │ + [ 1909a] text chunk: out of memory │ │ + [ 190b4] png_set_filler: inappropriate color type │ │ + [ 190dd] png_write_info was never called before png_write_row │ │ + [ 19112] internal write transform logic error │ │ + [ 19137] String "#" has length zero. │ │ + [ 19153] marker │ │ + [ 1915a] This Entry Point Contains No Executable Code │ │ + [ 19187] Error Writing to Ephemeris File │ │ + [ 191a7] Name of Device Exceeds 128-Character Limit │ │ + [ 191d2] SPICE(KERNELVARNOTFOUND) │ │ + [ 191eb] SPICE(NOSEGMENT) │ │ + [ 191fc] digits │ │ + [ 19203] SPICE(NOMOREROOM) │ │ + [ 19215] SPK │ │ + [ 19219] DAF │ │ + [ 1921d] DAFOPN │ │ + [ 19224] There is no file open with unit = # │ │ + [ 19248] The file, '#', is not a DAF. │ │ + [ 19265] %s: end of file\n │ │ + [ 19276] cell │ │ + [ 1927b] DAFFA │ │ + [ 19281] #2 │ │ + [ 19284] │ │ - [ 195a1] SPKUEF │ │ - [ 195a8] SPICE(EVECOUTOFRANGE) │ │ - [ 195be] The range of constants requested extends beyond the available constant data. Constants are available for indices 1 to #. You have requested data from # to #. │ │ - [ 1965f] SPKR05 │ │ - [ 19666] BODY │ │ - [ 1966b] TKFRAME_# │ │ - [ 19675] _MATRIX │ │ - [ 1967d] angles │ │ - [ 19684] SPICE(VARIABLENOTFOUND) │ │ - [ 1969c] < │ │ - [ 1969e] DELTET/M │ │ - [ 196a7] v1 │ │ - [ 196aa] zzbodtrn_ │ │ - [ 196b4] The kernel pool vector, #, used in mapping between names and ID-codes is absent, while # is not. This is often due to an improperly constructed text kernel. Check loaded kernels for these keywords. │ │ - [ 1977c] The kernel pool vectors used for mapping between names and ID-codes are not the same size. The size of the name vector, NAIF_BODY_NAME is #. The size of the ID-code vector, NAIF_BODY_CODE is #. You need to examine the ID-code kernel you loaded and correct the mismatch. │ │ - [ 1988b] ID to name mappings. │ │ - [ 198a0] ZZCTR: You have called an entry which performs performs no run-time function. This may indicate a bug. Please check the documentation for the subroutine ZZCTR. │ │ - [ 19940] SPICE(SPICEISTIRED) │ │ - [ 19954] Attempt to open file, '#', for read access has failed. The non-native binary file format '#' is not currently supported on this platform. Obtain a transfer format version, and convert it to the native format. See the Convert User's Guide for details. │ │ - [ 19a51] Error reading the file record from the binary DAF file '#'. IOSTAT = #. │ │ - [ 19a9a] FTP transfer error detected. This binary $, '#', has most likely been corrupted by an ASCII mode FTP transfer. Obtain the file using IMAGE or BINARY transfer mode from the source. │ │ - [ 19b4f] zzdskbsr_ │ │ - [ 19b59] itmra │ │ - [ 19b5f] itmdec │ │ - [ 19b66] Definition of frame # specifies nutation model #, which is not recognized. This situation is usually caused by an error in a frame kernel in which the frame is defined. │ │ - [ 19c0f] ZZDYNROT │ │ - [ 19c18] DASRDC │ │ - [ 19c1f] File # has last d.p. address #; `top' = #. │ │ - [ 19c4a] Attempt to free non-existent DP page. Page number = #; valid range is 1:# │ │ - [ 19c94] ZZEKRD09 │ │ - [ 19c9d] Data pointer is corrupted. SEGNO = #; COLIDX = #; RECNO = #; EK = # │ │ - [ 19ce2] ZZEKSDEC │ │ - [ 19ceb] ZZEKSZ06 │ │ - [ 19cf4] page │ │ - [ 19cf9] Row vector index was #; valid range is 0:# │ │ - [ 19d24] C2F_CreateStr_Sig │ │ - [ 19d36] IAU_MOON │ │ - [ 19d3f] IAU_MIMAS │ │ - [ 19d49] IAU_OBERON │ │ - [ 19d54] IAU_CRESSIDA │ │ - [ 19d61] IAU_PORTIA │ │ - [ 19d6c] IAU_NAIAD │ │ - [ 19d76] IAU_VESTA │ │ - [ 19d80] IAU_HYDRA │ │ - [ 19d8a] Degenerate case. The # axis of body # is negative or zero. Please check the text PCK file. You should fix the # component of the kernel pool variable BODY#_RADII. │ │ - [ 19e30] ZZHSICHK │ │ - [ 19e39] ZZHASHI │ │ - [ 19e41] MERCURY BARYCENTER │ │ - [ 19e54] CHALDENE │ │ - [ 19e5d] IOCASTE │ │ - [ 19e65] IAPETUS │ │ - [ 19e6d] ATLAS │ │ - [ 19e73] IJIRAQ │ │ - [ 19e7a] NEREID │ │ - [ 19e81] BEAGLE 2 │ │ - [ 19e8a] MMO │ │ - [ 19e8e] CASSINI SIMULATION │ │ - [ 19ea1] SPP │ │ - [ 19ea5] TRACE GAS ORBITER │ │ - [ 19eb7] CHANDRAYAAN-2 ORBITER │ │ - [ 19ecd] CLUSTER 2 │ │ - [ 19ed7] HANEDA-CAMPOS │ │ - [ 19ee5] HERSCHEL-RIGOLLET │ │ - [ 19ef7] WOLF │ │ - [ 19efc] DSS-16 │ │ - [ 19f03] DSS-53 │ │ - [ 19f0a] ZZLDKER │ │ - [ 19f12] ::RND │ │ - [ 19f18] There are two successive delimiters <#> in the input string. This is an ambiguous input. ' │ │ - [ 19f75] ,/-:. │ │ - [ 19f7b] SPICE(TOOMANYPARTITIONS) │ │ - [ 19f94] The variable that points to the leapseconds (DELTET/DELTA_AT) could not be located in the kernel pool. It is likely that the leapseconds kernel has not been loaded. │ │ - [ 1a03a] ZZDSPR │ │ - [ 1a041] Stop time kernel variable # exists but DTPOOL returned data type # rather than one of the expected values: 'C' or 'N'. │ │ - [ 1a0b8] FORMAL │ │ - [ 1a0bf] Format pictures must have at least one significant character. The picture provided '#' does not. │ │ - [ 1a121] Year │ │ - [ 1a126] Time-Zone indicator │ │ - [ 1a13a] MONTH │ │ - [ 1a140] wkd │ │ - [ 1a144] WKD │ │ - [ 1a148] DECEMBER │ │ - [ 1a151] JULY │ │ - [ 1a156] UTC+ │ │ - [ 1a15b] JULIAND │ │ - [ 1a163] The meaning of the decimal number <#> could not be determined: │ │ - [ 1a1a3] Two substrings representing an hour of the day were identified in the input time string <#> and <#>: " │ │ - [ 1a20a] Y-i-iti:i:i │ │ - [ 1a216] Y*y*H*M*S │ │ - [ 1a220] YmDHMS │ │ - [ 1a227] i-Yd │ │ - [ 1a22c] i-i-iti:i:i │ │ - [ 1a238] i:i:imiY │ │ - [ 1a241] iimi:i:i │ │ - [ 1a24a] DmYH*M │ │ - [ 1a251] mnY │ │ - [ 1a255] nmY │ │ - [ 1a259] Y-i-iti:i:nx │ │ - [ 1a266] Y-iti:i:ix │ │ - [ 1a271] ; │ │ - [ 1a273] hyw │ │ - [ 1a277] zh__GUOYU │ │ - [ 1a281] av │ │ - [ 1a284] bkm │ │ - [ 1a288] cay │ │ - [ 1a28c] dyu │ │ - [ 1a290] ik │ │ - [ 1a293] kaa │ │ - [ 1a297] la │ │ - [ 1a29a] men │ │ - [ 1a29e] mic │ │ - [ 1a2a2] mnc │ │ - [ 1a2a6] na │ │ - [ 1a2a9] njo │ │ - [ 1a2ad] sly │ │ - [ 1a2b1] suk │ │ - [ 1a2b5] tok │ │ - [ 1a2b9] yao │ │ - [ 1a2bd] zza │ │ - [ 1a2c1] amh │ │ - [ 1a2c5] aze │ │ - [ 1a2c9] bak │ │ - [ 1a2cd] che │ │ - [ 1a2d1] eus │ │ - [ 1a2d5] gle │ │ - [ 1a2d9] sin │ │ - [ 1a2dd] AE │ │ - [ 1a2e0] BS │ │ - [ 1a2e3] CL │ │ - [ 1a2e6] CN │ │ - [ 1a2e9] EE │ │ - [ 1a2ec] KW │ │ - [ 1a2ef] PN │ │ - [ 1a2f2] SO │ │ - [ 1a2f5] UM │ │ - [ 1a2f8] BMU │ │ - [ 1a2fc] BLR │ │ - [ 1a300] DOM │ │ - [ 1a304] GUY │ │ - [ 1a308] MAC │ │ - [ 1a30c] NAM │ │ - [ 1a310] UKR │ │ - [ 1a314] ka_GE │ │ - [ 1a31a] lt_LT │ │ - [ 1a320] sl_SI │ │ - [ 1a326] yue_Hant │ │ - [ 1a32f] zh_Hant_TW │ │ - [ 1a33a] language │ │ - [ 1a343] VLAT │ │ - [ 1a348] bo_BT │ │ - [ 1a34e] es_PE │ │ - [ 1a354] es@collation=traditional │ │ - [ 1a36d] fr_ML │ │ - [ 1a373] iu_Latn_CA │ │ - [ 1a37e] ti_ET │ │ - [ 1a384] uz_Cyrl_UZ │ │ - [ 1a38f] CODEPOINTS │ │ - [ 1a39a] see-x-i-mingo │ │ - [ 1a3a8] sgn-fr │ │ - [ 1a3af] ures_swapResource(root res=%08x) failed\n │ │ - [ 1a3d8] ucol_swapInverseUCA(): data format %02x.%02x.%02x.%02x (format version %02x.%02x) is not an inverse UCA collation file\n │ │ - [ 1a450] @calendar=gregory │ │ - [ 1a462] tzdbNames │ │ - [ 1a46c] Scripts │ │ - [ 1a474] U_MULTIPLE_POST_CONTEXTS │ │ - [ 1a48d] U_PATTERN_SYNTAX_ERROR │ │ - [ 1a4a4] U_IDNA_DOMAIN_NAME_TOO_LONG_ERROR │ │ - [ 1a4c6] BAD │ │ - [ 1a4ca] BAN │ │ - [ 1a4ce] BRR │ │ - [ 1a4d2] KRH │ │ - [ 1a4d6] MYR │ │ - [ 1a4da] NAD │ │ - [ 1a4de] PYG │ │ - [ 1a4e2] QAR │ │ - [ 1a4e6] XAG │ │ - [ 1a4ea] ZRN │ │ - [ 1a4ee] M12L │ │ - [ 1a4f3] arc-minute │ │ - [ 1a4fe] CHC │ │ - [ 1a502] pound-force │ │ - [ 1a50e] fathom │ │ - [ 1a515] bushel │ │ - [ 1a51c] quart-imperial │ │ - [ 1a52b] approximatelySign │ │ - [ 1a53d] ew │ │ - [ 1a540] pow9- │ │ - [ 1a546] pow11- │ │ - [ 1a54d] giga │ │ - [ 1a552] hecto │ │ - [ 1a558] plural │ │ - [ 1a55f] er │ │ - [ 1a562] in 'prefix|str', prefix and str must each start with an NFC boundary │ │ - [ 1a5a7] [hiraganaQ on] is not supported │ │ - [ 1a5c7] first regular │ │ - [ 1a5d5] last regular │ │ - [ 1a5e2] ATrace_endSection │ │ - [ 1a5f4] ()Landroid/view/WindowManager; │ │ - [ 1a613] android/os/Build │ │ - [ 1a624] sounds │ │ - [ 1a62b] celsius │ │ - [ 1a633] StarDatabase │ │ - [ 1a640] LuaHook │ │ - [ 1a648] RotateAcceleration │ │ - [ 1a65b] L │ │ - [ 1a65d] Error parsing destinations file.\n │ │ - [ 1a67f] Name │ │ - [ 1a685] isFolder │ │ - [ 1a68f] Sync │ │ - [ 1a694] {:3d}:{:05.2f} │ │ - [ 1a6a3] {} �F │ │ - [ 1a6aa] %s backend is disabled.\n │ │ - [ 1a6c3] CHANNEL_AUX_1 │ │ - [ 1a6d1] Input/output error │ │ - [ 1a6e4] Resource already in use │ │ - [ 1a6fc] Invalid data │ │ - [ 1a709] Address family not supported │ │ - [ 1a726] Operation in progress │ │ - [ 1a73c] Failed to stop backend device │ │ - [ 1a75a] AAudioStream_waitForStateChange │ │ - [ 1a77a] slCreateEngine │ │ - [ 1a789] androidRecordingPreset │ │ - [ 1a7a0] [OpenSL] Failed to create audio player. │ │ - [ 1a7c8] RIFF │ │ - [ 1a7cd] bext │ │ - [ 1a7d2] ICOP │ │ - [ 1a7d7] %{:02x} │ │ - [ 1a7df] lm │ │ - [ 1a7e2] no format │ │ - [ 1a7ec] Sat │ │ - [ 1a7f0] Sunday │ │ - [ 1a7f7] darkgoldenrod │ │ - [ 1a805] indigo │ │ - [ 1a80c] lemonchiffon │ │ - [ 1a819] lightslategray │ │ - [ 1a828] peachpuff │ │ - [ 1a832] Alpha │ │ - [ 1a840] observatory │ │ - [ 1a84c] tholus │ │ - [ 1a853] scopulus │ │ - [ 1a85c] wait │ │ - [ 1a861] renderflags │ │ - [ 1a86d] scaleddiscs │ │ - [ 1a879] zrot │ │ - [ 1a87e] leftarrow │ │ - [ 1a888] show │ │ - [ 1a88d] setsafeareainsets │ │ - [ 1a89f] isplayingaudio │ │ - [ 1a8ae] Wrong number of arguments to celestia:hide │ │ - [ 1a8d9] No argument expected in celestia:getlayoutdirection │ │ - [ 1a90d] Invalid layoutDirection │ │ - [ 1a925] Fourth argument to celestia:setconstellationcolor() must be a table │ │ - [ 1a969] No argument expected to function celestia:getsystemtime │ │ - [ 1a9a1] arguments to celestia:newrotation must either be (vec, number) or four numbers │ │ - [ 1a9f0] Sixth argument to celestia:play must be a number (nopause) │ │ - [ 1aa2b] First argument for celestia:seekaudio must be a number │ │ - [ 1aa62] Celx_istype failed! Unregistered class.\n │ │ - [ 1aa8c] Error while executing cleanup-callback: {}\n │ │ - [ 1aab8] io │ │ - [ 1aabb] Bad frame object! │ │ - [ 1aacd] argument 2 to gl.BlendFunc must be a number │ │ - [ 1aaf9] Argument to object:addreferencemark() must be a table │ │ - [ 1ab2f] luminosity │ │ - [ 1ab3a] orbitPeriod │ │ - [ 1ab46] No arguments allowed for to object:equatorialframe │ │ - [ 1ab79] gotosurface │ │ - [ 1ab85] cancelgoto │ │ - [ 1ab90] getorientation │ │ - [ 1ab9f] getfov │ │ - [ 1aba6] finalOrientation │ │ - [ 1abb7] Second arg to observer:gotosurface must be a number │ │ - [ 1abeb] First argument to observer:centerorbit must be an object │ │ - [ 1ac24] setaxisangle: first argument must be a vector │ │ - [ 1ac52] Invalid access of rotation-component │ │ - [ 1ac77] #celmodel__ascii │ │ - [ 1ac88] pointsize │ │ - [ 1ac93] Texture coordinate must be a float2\n │ │ - [ 1acb8] native │ │ - [ 1acbf] iau-enceladus │ │ - [ 1accd] iau-io │ │ - [ 1acd4] Bad binary xyzv file {}.\n │ │ - [ 1acee] Cas │ │ - [ 1acf2] Ind │ │ - [ 1acf6] Sct │ │ - [ 1acfa] Angle │ │ - [ 1ad00] E7 │ │ - [ 1ad03] SF │ │ - [ 1ad06] Could not load SPICE orbit\n │ │ - [ 1ad22] EquatorAscendingNode │ │ - [ 1ad37] Ending specified for SPICE orbit, but beginning is missing.\n │ │ - [ 1ad74] AscendingNode │ │ - [ 1ad82] Roll │ │ - [ 1ad87] Object has incorrect J2000 equator frame syntax.\n │ │ - [ 1adb9] n.z = sqrt(1.0 - n.x * n.x - n.y * n.y);\n │ │ - [ 1ade3] shadow │ │ - [ 1adea] v_Color = vec4({}, opacity);\n │ │ - [ 1ae0c] mieCoeff │ │ - [ 1ae15] light{}_diffuse │ │ - [ 1ae25] vec4 │ │ - [ 1ae2a] samplerCube │ │ - [ 1ae36] ) - 0.5;\n │ │ - [ 1ae40] shadowR = clamp((2.0 * sqrt(dot(shadowCenter, shadowCenter)) - 1.0) * │ │ - [ 1ae87] Sky │ │ - [ 1ae8b] SpecularColor │ │ - [ 1ae99] NormalMap │ │ - [ 1aea3] 8 │ │ - [ 1aea5] 9 │ │ - [ 1aea7] {} {} A │ │ - [ 1aeaf] Loading bump map: {}\n │ │ - [ 1aec5] dds │ │ - [ 1aec9] level{:d} │ │ - [ 1aed3] ImageDirectory │ │ - [ 1aee2] TileSize is missing from virtual texture\n │ │ - [ 1af0c] Error skipping {} bytes of unknown/unexpected chunk type {}\n │ │ - [ 1af49] Processing MaterialSpecular chunk\n │ │ - [ 1af6c] Content size {} too small to include integer perecentage\n │ │ - [ 1afa6] (DDDD)V │ │ - [ 1afae] space/celestia/celestia/Selection │ │ - [ 1afd0] cannot use push_back() with │ │ - [ 1afee] msgid │ │ - [ 1aff5] C.UTF-8 │ │ - [ 1affd] Type 1 │ │ - [ 1b004] .resource/ │ │ - [ 1b00f] pshinter │ │ - [ 1b018] Black │ │ - [ 1b01e] def │ │ - [ 1b022] SDBytes │ │ - [ 1b02d] � � │ │ - [ 1b03a] StartTrackKern │ │ - [ 1b049] %s │ │ - [ 1b04c] │ │ - [ 1b053] != │ │ - [ 1b057] set^Ccur^Cend │ │ - [ 1b063] file (closed) │ │ - [ 1b071] loaded │ │ - [ 1b078] >%s │ │ - [ 1b07c] Gray color space not permitted on RGB PNG │ │ - [ 1b0a6] Missing IHDR before IDAT │ │ - [ 1b0bf] png_do_quantize returned rowbytes=0 │ │ - [ 1b0e3] invalid before the PNG header has been read │ │ - [ 1b10f] unrecognized equation type │ │ - [ 1b12a] chunk data is too large │ │ - [ 1b142] cHRM White X │ │ - [ 1b14f] cHRM Red Y │ │ - [ 1b15a] Insufficient memory for hIST chunk data │ │ - [ 1b182] too many unknown chunks │ │ - [ 1b19a] keyword truncated │ │ - [ 1b1ac] png_image_write_to_file: invalid argument │ │ - [ 1b1d6] tEXt: text too long │ │ - [ 1b1ea] in use by IDAT │ │ - [ 1b1f9] BODN2C │ │ - [ 1b200] ERRACT: An invalid value of OP was supplied. The value was: │ │ - [ 1b23f] An Attempt to Open a File Failed │ │ - [ 1b260] SPICE(TOOMANYFILESOPEN) │ │ - [ 1b278] $ │ │ - [ 1b27a] CKBSR │ │ - [ 1b280] At least one CK file must be loaded by CKLPF before beginning a search. │ │ - [ 1b2c8] ftnd │ │ - [ 1b2cd] unformatted io not allowed │ │ - [ 1b2e8] %s: illegal error number %d\n │ │ - [ 1b305] DAFRN │ │ - [ 1b30b] rbdat │ │ - [ 1b311] DAFWCR │ │ - [ 1b318] tbfils │ │ - [ 1b31f] MISSING_COLUMN │ │ - [ 1b32e] segvec │ │ - [ 1b335] SCRATCH │ │ - [ 1b33d] DASHFN │ │ - [ 1b344] DASURC │ │ - [ 1b34b] Invalid data type: #. │ │ - [ 1b362] NODE was #; backward pointer = #; forward pointer = #. "FREE" is #) │ │ - [ 1b3a6] btprvi │ │ - [ 1b3ad] CLPOOL │ │ - [ 1b3b4] datlst │ │ - [ 1b3bb] SPICE(INTOUTOFRANGE) │ │ - [ 1b3d0] DTPOOL │ │ - [ 1b3d7] Trying to remove non-existent elements. │ │ - [ 1b3ff] IRFROT │ │ - [ 1b406] The reference frame with id-code # is not a recognized inertial reference frame. │ │ - [ 1b458] The segment is not a type 1 segment. Type is # │ │ - [ 1b488] SPICE(INVALIDVALUE) │ │ - [ 1b49c] DTOL should be non-negative; it is #. │ │ - [ 1b4c2] prodm │ │ - [ 1b4c8] SGFRVI │ │ - [ 1b4cf] SPKGEO │ │ - [ 1b4d6] OBS │ │ - [ 1b4da] FRMCHG │ │ - [ 1b4e1] B.C. │ │ - [ 1b4e8] kq │ │ - [ 1b4eb] SPICE(ZEROVELOCITY) │ │ - [ 1b4ff] NUT_PREC_RA │ │ - [ 1b50b] Insufficient number of nutation/precession angles for body * at time #. Number of angles is #; number required is #. │ │ - [ 1b580] bna │ │ - [ 1b584] bnw │ │ - [ 1b588] _Q │ │ - [ 1b58b] SPICE(UNKNOWNCOMPARE) │ │ - [ 1b5a1] SETC │ │ - [ 1b5a6] WNINSD │ │ - [ 1b5ad] complex format │ │ - [ 1b5bc] kernam │ │ - [ 1b5c3] ID │ │ - [ 1b5c6] ZZDDHMAN │ │ - [ 1b5cf] utlck │ │ - [ 1b5d5] ftabs │ │ - [ 1b5db] zzddhppf_ │ │ - [ 1b5e5] stdlad │ │ - [ 1b5ec] DEF_STYLE │ │ - [ 1b5f6] PARAMETERIZED │ │ - [ 1b604] SPICE(NOTANINTEGER) │ │ - [ 1b618] The A,B, and C axes were #, #, and # respectively. │ │ - [ 1b64b] The input vectors AXDEF and PLNDEF are linearly dependent. │ │ - [ 1b686] Cross product table index for right hand side of constraint # was #; valid range is 1:# │ │ - [ 1b6de] ZZEKRP2N │ │ - [ 1b6e7] ZZEKSZ04 │ │ - [ 1b6f0] SPICE(VERSIONMISMATCH1) │ │ - [ 1b708] SPICE(VERSIONMISMATCH2) │ │ - [ 1b720] IAU_TETHYS │ │ - [ 1b72b] IAU_IAPETUS │ │ - [ 1b737] IAU_ATLAS │ │ - [ 1b741] IAU_CERES │ │ - [ 1b74b] IAU_LEUCUS │ │ - [ 1b756] SATURN BARYCENTER │ │ - [ 1b768] HIMALIA │ │ - [ 1b770] TAYGETE │ │ - [ 1b778] THELXINOE │ │ - [ 1b782] SIARNAQ │ │ - [ 1b78a] SYCORAX │ │ - [ 1b792] MARS ORBITER MISSION │ │ - [ 1b7a7] PIONEER 12 │ │ - [ 1b7b2] DS-1 │ │ - [ 1b7b7] VOYAGER 1 │ │ - [ 1b7c1] ORX │ │ - [ 1b7c5] MARS OBSERVER │ │ - [ 1b7d3] BEPICOLOMBO MPO │ │ - [ 1b7e3] CHANDRAYAAN-2 LANDER │ │ - [ 1b7f8] IMAGE │ │ - [ 1b7fe] VIPER │ │ - [ 1b804] SHOEMAKER-LEVY 9-Q │ │ - [ 1b817] SHOEMAKER-LEVY 9-P │ │ - [ 1b82a] SHOEMAKER-LEVY 9-H │ │ - [ 1b83d] HOWELL │ │ - [ 1b844] LONGMORE │ │ - [ 1b84d] PATROCLUS BARYCENTER │ │ - [ 1b862] DIDYMOS_BARYCENTER │ │ - [ 1b875] PATROCLUS │ │ - [ 1b87f] DSS-05 │ │ - [ 1b886] DSS-23 │ │ - [ 1b88d] The latter is a CK frame; a CK file containing data for instrument or structure # at the epoch shown above, as well as a corresponding SCLK kernel, must be loaded in order to use this frame. │ │ - [ 1b94c] SPICE(NEGATIVEHASHVALUE2) │ │ - [ 1b966] i.i │ │ - [ 1b96a] Ye │ │ - [ 1b96d] A.M. │ │ - [ 1b972] i:i:i │ │ - [ 1b978] Smi │ │ - [ 1b97c] The numbers of partition start times # and stop times # are unequal for spacecraft clock #. │ │ - [ 1b9d8] Kernel variable # for spacecraft clock # does not have numeric type. │ │ - [ 1ba1d] sclu01_ │ │ - [ 1ba25] XXSGP4I │ │ - [ 1ba2d] ZZSPKLT1 │ │ - [ 1ba36] FRAME_#_CLASS_ID │ │ - [ 1ba47] FRAME_# │ │ - [ 1ba4f] The specified item '#' is not a recognized time default item. The items that you may "SET" via the routine TIMDEF are 'CALENDAR', 'SYSTEM', or 'ZONE' │ │ - [ 1bae7] zztime_ │ │ - [ 1baef] The input time string '#' cannot be processed because the internal picture describing it requires more than @ characters. The token that could not be processed was '#'. │ │ - [ 1bb98] weekday │ │ - [ 1bba0] SUNDAY │ │ - [ 1bba7] MM │ │ - [ 1bbaa] No numeric components were supplied in the time string. │ │ - [ 1bbe3] There is more than one Julian Date specified in the epoch string. │ │ - [ 1bc26] H*MDmY │ │ - [ 1bc2d] imiin │ │ - [ 1bc33] miYi:i:i │ │ - [ 1bc3c] i/i/ii:n │ │ - [ 1bc45] zzwahr_ │ │ - [ 1bc4d] VN │ │ - [ 1bc50] cop │ │ - [ 1bc54] csw │ │ - [ 1bc58] eo │ │ - [ 1bc5b] frp │ │ - [ 1bc5f] kri │ │ - [ 1bc63] liv │ │ - [ 1bc67] loz │ │ - [ 1bc6b] moh │ │ - [ 1bc6f] nn │ │ - [ 1bc72] pms │ │ - [ 1bc76] sc │ │ - [ 1bc79] was │ │ - [ 1bc7d] yav │ │ - [ 1bc81] ara │ │ - [ 1bc85] epo │ │ - [ 1bc89] ido │ │ - [ 1bc8d] por │ │ - [ 1bc91] mol │ │ - [ 1bc95] BQ │ │ - [ 1bc98] BT │ │ - [ 1bc9b] EH │ │ - [ 1bc9e] IM │ │ - [ 1bca1] PF │ │ - [ 1bca4] SD │ │ - [ 1bca7] ARG │ │ - [ 1bcab] BOL │ │ - [ 1bcaf] XIC │ │ - [ 1bcb3] KWT │ │ - [ 1bcb7] MNP │ │ - [ 1bcbb] RWA │ │ - [ 1bcbf] TUN │ │ - [ 1bcc3] TTO │ │ - [ 1bcc7] uprv_asciiFromEbcdic() string[%d] contains a variant character in position %d\n │ │ - [ 1bd16] as_IN │ │ - [ 1bd1c] eu_ES │ │ - [ 1bd22] fr_FR │ │ - [ 1bd28] ga_IE │ │ - [ 1bd2e] pa_IN │ │ - [ 1bd34] WST │ │ - [ 1bd38] EASST │ │ - [ 1bd3e] az_Cyrl_AZ │ │ - [ 1bd49] ba_RU │ │ - [ 1bd4f] en_SG │ │ - [ 1bd55] es_GT │ │ - [ 1bd5b] fr_LU │ │ - [ 1bd61] hr_BA │ │ - [ 1bd67] kl_GL │ │ - [ 1bd6d] ko_KP │ │ - [ 1bd73] pa_PK │ │ - [ 1bd79] en-gb-oxendict │ │ - [ 1bd88] ssp │ │ - [ 1bd8c] gss │ │ - [ 1bd90] zh-gan │ │ - [ 1bd97] calendar/gregorian/DateTimePatterns%atTime │ │ - [ 1bdc2] afternoon2 │ │ - [ 1bdcd] islamic │ │ - [ 1bdd5] Zones │ │ - [ 1bddb] Keys │ │ - [ 1bde0] icu │ │ - [ 1bde4] unorm2_swap(): too few bytes (%d after header) for Normalizer2 data\n │ │ - [ 1be29] U_TOO_MANY_ALIASES_ERROR │ │ - [ 1be42] U_BRK_SEMICOLON_EXPECTED │ │ - [ 1be5b] AON │ │ - [ 1be5f] ATS │ │ - [ 1be63] DDM │ │ - [ 1be67] LSL │ │ - [ 1be6b] USN │ │ - [ 1be6f] sNaN │ │ - [ 1be74] @calendar=chinese │ │ - [ 1be86] degree │ │ - [ 1be8d] UGW │ │ - [ 1be91] VNC │ │ - [ 1be95] microsecond │ │ - [ 1bea1] quarter │ │ - [ 1bea9] dot-per-centimeter │ │ - [ 1bebc] picometer │ │ - [ 1bec6] tonne │ │ - [ 1becc] millimeter-ofhg │ │ - [ 1bedc] milliliter │ │ - [ 1bee7] quart │ │ - [ 1beed] oblique │ │ - [ 1bef5] %%.%dfe%%d │ │ - [ 1bf00] milli │ │ - [ 1bf06] cf │ │ - [ 1bf09] colNumeric │ │ - [ 1bf14] upper │ │ - [ 1bf1a] expected a reset or setting or comment │ │ - [ 1bf41] starred-relation string is not all NFD-inert │ │ - [ 1bf6e] unknown script or reorder code │ │ - [ 1bf8d] last trailing │ │ - [ 1bf9b] ExemplarCharactersIndex │ │ - [ 1bfb3] PaperSize │ │ - [ 1bfbd] nSetSupportedRefreshPeriods │ │ - [ 1bfd9] static void swappy::SwappyGL::setBufferStuffingFixWait(int32_t) │ │ - [ 1c019] eglGetError │ │ - [ 1c025] frame latency: │ │ - [ 1c042] Initialization of SPICE library failed. │ │ - [ 1c06a] frame center direction │ │ - [ 1c081] Unable to open log file {}\n │ │ - [ 1c09d] C-{:c} │ │ - [ 1c0a4] invalid format string │ │ - [ 1c0ba] Cursor │ │ - [ 1c0c2] coordsys " │ │ - [ 1c0cd] Max simultaneous textures: %s\n │ │ - [ 1c0ec] true │ │ - [ 1c0f1] {}x{} at {:.2f} fps {} │ │ - [ 1c109] Radius: {} ({} � {} � {})\n │ │ - [ 1c126] ERROR │ │ - [ 1c12c] Loading library: %s\n │ │ - [ 1c141] Failed to start backend device │ │ - [ 1c160] mp3 │ │ - [ 1c164] Failed to load file "%s". %s.\n │ │ - [ 1c183] AAudioStreamBuilder_setPerformanceMode │ │ - [ 1c1aa] AAudioStreamBuilder_setAllowedCapturePolicy │ │ - [ 1c1d6] IGNR │ │ - [ 1c1db] string_view::substr │ │ - [ 1c1ef] Freeflight │ │ - [ 1c1fa] January │ │ - [ 1c202] November │ │ - [ 1c20b] forestgreen │ │ - [ 1c217] mistyrose │ │ - [ 1c221] sienna │ │ - [ 1c228] wheat │ │ - [ 1c22e] .dxt5nm │ │ - [ 1c236] XDG_DATA_HOME │ │ - [ 1c244] cloudshadows │ │ - [ 1c251] mons │ │ - [ 1c256] mensa │ │ - [ 1c25c] linea │ │ - [ 1c262] farrum │ │ - [ 1c269] follow │ │ - [ 1c270] settextcolor │ │ - [ 1c27d] setlinecolor │ │ - [ 1c28a] lock │ │ - [ 1c28f] colorbottomright │ │ - [ 1c2a0] FOV │ │ - [ 1c2a4] Argument of category:createchild must be a string or userdata! │ │ - [ 1c2e3] getwindowdimension │ │ - [ 1c2f6] setambient │ │ - [ 1c301] setstarstyle │ │ - [ 1c30e] One argument expected for celestia:setscreendpi() │ │ - [ 1c340] No arguments expected for celestia:getorbitflags() │ │ - [ 1c373] Argument to celestia:showconstellations() must be a table │ │ - [ 1c3ad] No arguments expected for celestia:getminfeaturesize() │ │ - [ 1c3e4] First argument to celestia:takescreenshot must be a string │ │ - [ 1c41f] No argument expected for celestia:getscriptpath() │ │ - [ 1c451] First argument to celestia:verbosity must be a number (level) │ │ - [ 1c48f] Sixth argument to celestia:playaudio must be a boolean │ │ - [ 1c4c6] Function celestia:setaudiovolume requires two arguments │ │ - [ 1c4fe] One argument required for celestia:setluahook() │ │ - [ 1c52e] Internal Error: Invalid LuaState-pointer │ │ - [ 1c557] math │ │ - [ 1c55c] TexCoord │ │ - [ 1c565] [Texture:{}x{}] │ │ - [ 1c575] No arguments expected for texture:getwidth() │ │ - [ 1c5a2] component │ │ - [ 1c5ac] featureType │ │ - [ 1c5b8] No arguments expected to function object:localname │ │ - [ 1c5eb] Time expected as argument to object:getposition │ │ - [ 1c61b] centerorbit │ │ - [ 1c627] Second arg to observer:gotoobject must be a number │ │ - [ 1c65a] Third arg to observer:gotoobject must be a number │ │ - [ 1c68c] Sixth argument to observer:gotolonglat must be a vector │ │ - [ 1c6c4] First arg to observer:gotodistance must be object │ │ - [ 1c6f6] No argument expected to observer:getfov() │ │ - [ 1c720] First argument to observer:follow must be an object │ │ - [ 1c754] Argument to observer:setframe must be a frame │ │ - [ 1c782] specularmap │ │ - [ 1c78e] # {}\n │ │ - [ 1c794] f3\n │ │ - [ 1c798] uranus │ │ - [ 1c79f] vsop87-venus │ │ - [ 1c7ac] iau-mimas │ │ - [ 1c7b6] iau-rhea │ │ - [ 1c7bf] {:02}{} │ │ - [ 1c7c8] Aps │ │ - [ 1c7cc] Phe │ │ - [ 1c7d0] Detail │ │ - [ 1c7d7] models/SBb.png │ │ - [ 1c7e6] GL_EXT_texture_compression_s3tc │ │ - [ 1c806] KingConcentration │ │ - [ 1c818] City │ │ - [ 1c81d] RU │ │ - [ 1c820] LF │ │ - [ 1c823] MN │ │ - [ 1c826] XX │ │ - [ 1c829] UN │ │ - [ 1c82c] VS │ │ - [ 1c82f] Unknown model format '{}'\n │ │ - [ 1c84a] SpiceRotation │ │ - [ 1c858] Function name missing from script orbit definition.\n │ │ - [ 1c88d] MeanLongitude │ │ - [ 1c89b] Freeze │ │ - [ 1c8a3] void main(void)\n │ │ + [ 1956b] Attempt to set cardinality of cell to invalid value. The value was #. │ │ + [ 195b2] cmptks │ │ + [ 195b9] SGMETA │ │ + [ 195c0] TRACEBACK │ │ + [ 195ca] --> │ │ + [ 195ce] SPKUEF │ │ + [ 195d5] SPICE(EVECOUTOFRANGE) │ │ + [ 195eb] The range of constants requested extends beyond the available constant data. Constants are available for indices 1 to #. You have requested data from # to #. │ │ + [ 1968c] SPKR05 │ │ + [ 19693] BODY │ │ + [ 19698] TKFRAME_# │ │ + [ 196a2] _MATRIX │ │ + [ 196aa] angles │ │ + [ 196b1] SPICE(VARIABLENOTFOUND) │ │ + [ 196c9] < │ │ + [ 196cb] DELTET/M │ │ + [ 196d4] v1 │ │ + [ 196d7] zzbodtrn_ │ │ + [ 196e1] The kernel pool vector, #, used in mapping between names and ID-codes is absent, while # is not. This is often due to an improperly constructed text kernel. Check loaded kernels for these keywords. │ │ + [ 197a9] The kernel pool vectors used for mapping between names and ID-codes are not the same size. The size of the name vector, NAIF_BODY_NAME is #. The size of the ID-code vector, NAIF_BODY_CODE is #. You need to examine the ID-code kernel you loaded and correct the mismatch. │ │ + [ 198b8] ID to name mappings. │ │ + [ 198cd] ZZCTR: You have called an entry which performs performs no run-time function. This may indicate a bug. Please check the documentation for the subroutine ZZCTR. │ │ + [ 1996d] SPICE(SPICEISTIRED) │ │ + [ 19981] Attempt to open file, '#', for read access has failed. The non-native binary file format '#' is not currently supported on this platform. Obtain a transfer format version, and convert it to the native format. See the Convert User's Guide for details. │ │ + [ 19a7e] Error reading the file record from the binary DAF file '#'. IOSTAT = #. │ │ + [ 19ac7] FTP transfer error detected. This binary $, '#', has most likely been corrupted by an ASCII mode FTP transfer. Obtain the file using IMAGE or BINARY transfer mode from the source. │ │ + [ 19b7c] zzdskbsr_ │ │ + [ 19b86] itmra │ │ + [ 19b8c] itmdec │ │ + [ 19b93] Definition of frame # specifies nutation model #, which is not recognized. This situation is usually caused by an error in a frame kernel in which the frame is defined. │ │ + [ 19c3c] ZZDYNROT │ │ + [ 19c45] DASRDC │ │ + [ 19c4c] File # has last d.p. address #; `top' = #. │ │ + [ 19c77] Attempt to free non-existent DP page. Page number = #; valid range is 1:# │ │ + [ 19cc1] ZZEKRD09 │ │ + [ 19cca] Data pointer is corrupted. SEGNO = #; COLIDX = #; RECNO = #; EK = # │ │ + [ 19d0f] ZZEKSDEC │ │ + [ 19d18] ZZEKSZ06 │ │ + [ 19d21] page │ │ + [ 19d26] Row vector index was #; valid range is 0:# │ │ + [ 19d51] C2F_CreateStr_Sig │ │ + [ 19d63] IAU_MOON │ │ + [ 19d6c] IAU_MIMAS │ │ + [ 19d76] IAU_OBERON │ │ + [ 19d81] IAU_CRESSIDA │ │ + [ 19d8e] IAU_PORTIA │ │ + [ 19d99] IAU_NAIAD │ │ + [ 19da3] IAU_VESTA │ │ + [ 19dad] IAU_HYDRA │ │ + [ 19db7] Degenerate case. The # axis of body # is negative or zero. Please check the text PCK file. You should fix the # component of the kernel pool variable BODY#_RADII. │ │ + [ 19e5d] ZZHSICHK │ │ + [ 19e66] ZZHASHI │ │ + [ 19e6e] MERCURY BARYCENTER │ │ + [ 19e81] CHALDENE │ │ + [ 19e8a] IOCASTE │ │ + [ 19e92] IAPETUS │ │ + [ 19e9a] ATLAS │ │ + [ 19ea0] IJIRAQ │ │ + [ 19ea7] NEREID │ │ + [ 19eae] BEAGLE 2 │ │ + [ 19eb7] MMO │ │ + [ 19ebb] CASSINI SIMULATION │ │ + [ 19ece] SPP │ │ + [ 19ed2] TRACE GAS ORBITER │ │ + [ 19ee4] CHANDRAYAAN-2 ORBITER │ │ + [ 19efa] CLUSTER 2 │ │ + [ 19f04] HANEDA-CAMPOS │ │ + [ 19f12] HERSCHEL-RIGOLLET │ │ + [ 19f24] WOLF │ │ + [ 19f29] DSS-16 │ │ + [ 19f30] DSS-53 │ │ + [ 19f37] ZZLDKER │ │ + [ 19f3f] ::RND │ │ + [ 19f45] There are two successive delimiters <#> in the input string. This is an ambiguous input. ' │ │ + [ 19fa2] ,/-:. │ │ + [ 19fa8] SPICE(TOOMANYPARTITIONS) │ │ + [ 19fc1] The variable that points to the leapseconds (DELTET/DELTA_AT) could not be located in the kernel pool. It is likely that the leapseconds kernel has not been loaded. │ │ + [ 1a067] ZZDSPR │ │ + [ 1a06e] Stop time kernel variable # exists but DTPOOL returned data type # rather than one of the expected values: 'C' or 'N'. │ │ + [ 1a0e5] FORMAL │ │ + [ 1a0ec] Format pictures must have at least one significant character. The picture provided '#' does not. │ │ + [ 1a14e] Year │ │ + [ 1a153] Time-Zone indicator │ │ + [ 1a167] MONTH │ │ + [ 1a16d] wkd │ │ + [ 1a171] WKD │ │ + [ 1a175] DECEMBER │ │ + [ 1a17e] JULY │ │ + [ 1a183] UTC+ │ │ + [ 1a188] JULIAND │ │ + [ 1a190] The meaning of the decimal number <#> could not be determined: │ │ + [ 1a1d0] Two substrings representing an hour of the day were identified in the input time string <#> and <#>: " │ │ + [ 1a237] Y-i-iti:i:i │ │ + [ 1a243] Y*y*H*M*S │ │ + [ 1a24d] YmDHMS │ │ + [ 1a254] i-Yd │ │ + [ 1a259] i-i-iti:i:i │ │ + [ 1a265] i:i:imiY │ │ + [ 1a26e] iimi:i:i │ │ + [ 1a277] DmYH*M │ │ + [ 1a27e] mnY │ │ + [ 1a282] nmY │ │ + [ 1a286] Y-i-iti:i:nx │ │ + [ 1a293] Y-iti:i:ix │ │ + [ 1a29e] ; │ │ + [ 1a2a0] hyw │ │ + [ 1a2a4] zh__GUOYU │ │ + [ 1a2ae] av │ │ + [ 1a2b1] bkm │ │ + [ 1a2b5] cay │ │ + [ 1a2b9] dyu │ │ + [ 1a2bd] ik │ │ + [ 1a2c0] kaa │ │ + [ 1a2c4] la │ │ + [ 1a2c7] men │ │ + [ 1a2cb] mic │ │ + [ 1a2cf] mnc │ │ + [ 1a2d3] na │ │ + [ 1a2d6] njo │ │ + [ 1a2da] sly │ │ + [ 1a2de] suk │ │ + [ 1a2e2] tok │ │ + [ 1a2e6] yao │ │ + [ 1a2ea] zza │ │ + [ 1a2ee] amh │ │ + [ 1a2f2] aze │ │ + [ 1a2f6] bak │ │ + [ 1a2fa] che │ │ + [ 1a2fe] eus │ │ + [ 1a302] gle │ │ + [ 1a306] sin │ │ + [ 1a30a] AE │ │ + [ 1a30d] BS │ │ + [ 1a310] CL │ │ + [ 1a313] CN │ │ + [ 1a316] EE │ │ + [ 1a319] KW │ │ + [ 1a31c] PN │ │ + [ 1a31f] SO │ │ + [ 1a322] UM │ │ + [ 1a325] BMU │ │ + [ 1a329] BLR │ │ + [ 1a32d] DOM │ │ + [ 1a331] GUY │ │ + [ 1a335] MAC │ │ + [ 1a339] NAM │ │ + [ 1a33d] UKR │ │ + [ 1a341] ka_GE │ │ + [ 1a347] lt_LT │ │ + [ 1a34d] sl_SI │ │ + [ 1a353] yue_Hant │ │ + [ 1a35c] zh_Hant_TW │ │ + [ 1a367] language │ │ + [ 1a370] VLAT │ │ + [ 1a375] bo_BT │ │ + [ 1a37b] es_PE │ │ + [ 1a381] es@collation=traditional │ │ + [ 1a39a] fr_ML │ │ + [ 1a3a0] iu_Latn_CA │ │ + [ 1a3ab] ti_ET │ │ + [ 1a3b1] uz_Cyrl_UZ │ │ + [ 1a3bc] CODEPOINTS │ │ + [ 1a3c7] see-x-i-mingo │ │ + [ 1a3d5] sgn-fr │ │ + [ 1a3dc] ures_swapResource(root res=%08x) failed\n │ │ + [ 1a405] ucol_swapInverseUCA(): data format %02x.%02x.%02x.%02x (format version %02x.%02x) is not an inverse UCA collation file\n │ │ + [ 1a47d] @calendar=gregory │ │ + [ 1a48f] tzdbNames │ │ + [ 1a499] Scripts │ │ + [ 1a4a1] U_MULTIPLE_POST_CONTEXTS │ │ + [ 1a4ba] U_PATTERN_SYNTAX_ERROR │ │ + [ 1a4d1] U_IDNA_DOMAIN_NAME_TOO_LONG_ERROR │ │ + [ 1a4f3] BAD │ │ + [ 1a4f7] BAN │ │ + [ 1a4fb] BRR │ │ + [ 1a4ff] KRH │ │ + [ 1a503] MYR │ │ + [ 1a507] NAD │ │ + [ 1a50b] PYG │ │ + [ 1a50f] QAR │ │ + [ 1a513] XAG │ │ + [ 1a517] ZRN │ │ + [ 1a51b] M12L │ │ + [ 1a520] arc-minute │ │ + [ 1a52b] CHC │ │ + [ 1a52f] pound-force │ │ + [ 1a53b] fathom │ │ + [ 1a542] bushel │ │ + [ 1a549] quart-imperial │ │ + [ 1a558] approximatelySign │ │ + [ 1a56a] ew │ │ + [ 1a56d] pow9- │ │ + [ 1a573] pow11- │ │ + [ 1a57a] giga │ │ + [ 1a57f] hecto │ │ + [ 1a585] plural │ │ + [ 1a58c] er │ │ + [ 1a58f] in 'prefix|str', prefix and str must each start with an NFC boundary │ │ + [ 1a5d4] [hiraganaQ on] is not supported │ │ + [ 1a5f4] first regular │ │ + [ 1a602] last regular │ │ + [ 1a60f] ATrace_endSection │ │ + [ 1a621] ()Landroid/view/WindowManager; │ │ + [ 1a640] android/os/Build │ │ + [ 1a651] sounds │ │ + [ 1a658] celsius │ │ + [ 1a660] StarDatabase │ │ + [ 1a66d] LuaHook │ │ + [ 1a675] RotateAcceleration │ │ + [ 1a688] L │ │ + [ 1a68a] Error parsing destinations file.\n │ │ + [ 1a6ac] Name │ │ + [ 1a6b2] isFolder │ │ + [ 1a6bc] Sync │ │ + [ 1a6c1] {:3d}:{:05.2f} │ │ + [ 1a6d0] {} �F │ │ + [ 1a6d7] %s backend is disabled.\n │ │ + [ 1a6f0] CHANNEL_AUX_1 │ │ + [ 1a6fe] Input/output error │ │ + [ 1a711] Resource already in use │ │ + [ 1a729] Invalid data │ │ + [ 1a736] Address family not supported │ │ + [ 1a753] Operation in progress │ │ + [ 1a769] Failed to stop backend device │ │ + [ 1a787] AAudioStream_waitForStateChange │ │ + [ 1a7a7] slCreateEngine │ │ + [ 1a7b6] androidRecordingPreset │ │ + [ 1a7cd] [OpenSL] Failed to create audio player. │ │ + [ 1a7f5] RIFF │ │ + [ 1a7fa] bext │ │ + [ 1a7ff] ICOP │ │ + [ 1a804] %{:02x} │ │ + [ 1a80c] lm │ │ + [ 1a80f] no format │ │ + [ 1a819] Sat │ │ + [ 1a81d] Sunday │ │ + [ 1a824] darkgoldenrod │ │ + [ 1a832] indigo │ │ + [ 1a839] lemonchiffon │ │ + [ 1a846] lightslategray │ │ + [ 1a855] peachpuff │ │ + [ 1a85f] Alpha │ │ + [ 1a86d] observatory │ │ + [ 1a879] tholus │ │ + [ 1a880] scopulus │ │ + [ 1a889] wait │ │ + [ 1a88e] renderflags │ │ + [ 1a89a] scaleddiscs │ │ + [ 1a8a6] zrot │ │ + [ 1a8ab] leftarrow │ │ + [ 1a8b5] show │ │ + [ 1a8ba] setsafeareainsets │ │ + [ 1a8cc] isplayingaudio │ │ + [ 1a8db] Wrong number of arguments to celestia:hide │ │ + [ 1a906] No argument expected in celestia:getlayoutdirection │ │ + [ 1a93a] Invalid layoutDirection │ │ + [ 1a952] Fourth argument to celestia:setconstellationcolor() must be a table │ │ + [ 1a996] No argument expected to function celestia:getsystemtime │ │ + [ 1a9ce] arguments to celestia:newrotation must either be (vec, number) or four numbers │ │ + [ 1aa1d] Sixth argument to celestia:play must be a number (nopause) │ │ + [ 1aa58] First argument for celestia:seekaudio must be a number │ │ + [ 1aa8f] Celx_istype failed! Unregistered class.\n │ │ + [ 1aab9] Error while executing cleanup-callback: {}\n │ │ + [ 1aae5] io │ │ + [ 1aae8] Bad frame object! │ │ + [ 1aafa] argument 2 to gl.BlendFunc must be a number │ │ + [ 1ab26] Argument to object:addreferencemark() must be a table │ │ + [ 1ab5c] luminosity │ │ + [ 1ab67] orbitPeriod │ │ + [ 1ab73] No arguments allowed for to object:equatorialframe │ │ + [ 1aba6] gotosurface │ │ + [ 1abb2] cancelgoto │ │ + [ 1abbd] getorientation │ │ + [ 1abcc] getfov │ │ + [ 1abd3] finalOrientation │ │ + [ 1abe4] Second arg to observer:gotosurface must be a number │ │ + [ 1ac18] First argument to observer:centerorbit must be an object │ │ + [ 1ac51] setaxisangle: first argument must be a vector │ │ + [ 1ac7f] Invalid access of rotation-component │ │ + [ 1aca4] #celmodel__ascii │ │ + [ 1acb5] pointsize │ │ + [ 1acc0] Texture coordinate must be a float2\n │ │ + [ 1ace5] native │ │ + [ 1acec] iau-enceladus │ │ + [ 1acfa] iau-io │ │ + [ 1ad01] Bad binary xyzv file {}.\n │ │ + [ 1ad1b] Cas │ │ + [ 1ad1f] Ind │ │ + [ 1ad23] Sct │ │ + [ 1ad27] Angle │ │ + [ 1ad2d] E7 │ │ + [ 1ad30] SF │ │ + [ 1ad33] Could not load SPICE orbit\n │ │ + [ 1ad4f] EquatorAscendingNode │ │ + [ 1ad64] Ending specified for SPICE orbit, but beginning is missing.\n │ │ + [ 1ada1] AscendingNode │ │ + [ 1adaf] Roll │ │ + [ 1adb4] Object has incorrect J2000 equator frame syntax.\n │ │ + [ 1ade6] n.z = sqrt(1.0 - n.x * n.x - n.y * n.y);\n │ │ + [ 1ae10] shadow │ │ + [ 1ae17] v_Color = vec4({}, opacity);\n │ │ + [ 1ae39] mieCoeff │ │ + [ 1ae42] light{}_diffuse │ │ + [ 1ae52] vec4 │ │ + [ 1ae57] samplerCube │ │ + [ 1ae63] ) - 0.5;\n │ │ + [ 1ae6d] shadowR = clamp((2.0 * sqrt(dot(shadowCenter, shadowCenter)) - 1.0) * │ │ + [ 1aeb4] Sky │ │ + [ 1aeb8] SpecularColor │ │ + [ 1aec6] NormalMap │ │ + [ 1aed0] 8 │ │ + [ 1aed2] 9 │ │ + [ 1aed4] {} {} A │ │ + [ 1aedc] Loading bump map: {}\n │ │ + [ 1aef2] dds │ │ + [ 1aef6] level{:d} │ │ + [ 1af00] ImageDirectory │ │ + [ 1af0f] TileSize is missing from virtual texture\n │ │ + [ 1af39] Error skipping {} bytes of unknown/unexpected chunk type {}\n │ │ + [ 1af76] Processing MaterialSpecular chunk\n │ │ + [ 1af99] Content size {} too small to include integer perecentage\n │ │ + [ 1afd3] (DDDD)V │ │ + [ 1afdb] space/celestia/celestia/Selection │ │ + [ 1affd] cannot use push_back() with │ │ + [ 1b01b] msgid │ │ + [ 1b022] C.UTF-8 │ │ + [ 1b02a] Type 1 │ │ + [ 1b031] .resource/ │ │ + [ 1b03c] pshinter │ │ + [ 1b045] Black │ │ + [ 1b04b] def │ │ + [ 1b04f] SDBytes │ │ + [ 1b05a] � � │ │ + [ 1b067] StartTrackKern │ │ + [ 1b076] %s │ │ + [ 1b079] │ │ + [ 1b080] != │ │ + [ 1b084] set^Ccur^Cend │ │ + [ 1b090] file (closed) │ │ + [ 1b09e] loaded │ │ + [ 1b0a5] >%s │ │ + [ 1b0a9] Gray color space not permitted on RGB PNG │ │ + [ 1b0d3] Missing IHDR before IDAT │ │ + [ 1b0ec] png_do_quantize returned rowbytes=0 │ │ + [ 1b110] invalid before the PNG header has been read │ │ + [ 1b13c] unrecognized equation type │ │ + [ 1b157] chunk data is too large │ │ + [ 1b16f] cHRM White X │ │ + [ 1b17c] cHRM Red Y │ │ + [ 1b187] Insufficient memory for hIST chunk data │ │ + [ 1b1af] too many unknown chunks │ │ + [ 1b1c7] keyword truncated │ │ + [ 1b1d9] png_image_write_to_file: invalid argument │ │ + [ 1b203] tEXt: text too long │ │ + [ 1b217] in use by IDAT │ │ + [ 1b226] BODN2C │ │ + [ 1b22d] ERRACT: An invalid value of OP was supplied. The value was: │ │ + [ 1b26c] An Attempt to Open a File Failed │ │ + [ 1b28d] SPICE(TOOMANYFILESOPEN) │ │ + [ 1b2a5] $ │ │ + [ 1b2a7] CKBSR │ │ + [ 1b2ad] At least one CK file must be loaded by CKLPF before beginning a search. │ │ + [ 1b2f5] ftnd │ │ + [ 1b2fa] unformatted io not allowed │ │ + [ 1b315] %s: illegal error number %d\n │ │ + [ 1b332] DAFRN │ │ + [ 1b338] rbdat │ │ + [ 1b33e] DAFWCR │ │ + [ 1b345] tbfils │ │ + [ 1b34c] MISSING_COLUMN │ │ + [ 1b35b] segvec │ │ + [ 1b362] SCRATCH │ │ + [ 1b36a] DASHFN │ │ + [ 1b371] DASURC │ │ + [ 1b378] Invalid data type: #. │ │ + [ 1b38f] NODE was #; backward pointer = #; forward pointer = #. "FREE" is #) │ │ + [ 1b3d3] btprvi │ │ + [ 1b3da] CLPOOL │ │ + [ 1b3e1] datlst │ │ + [ 1b3e8] SPICE(INTOUTOFRANGE) │ │ + [ 1b3fd] DTPOOL │ │ + [ 1b404] Trying to remove non-existent elements. │ │ + [ 1b42c] IRFROT │ │ + [ 1b433] The reference frame with id-code # is not a recognized inertial reference frame. │ │ + [ 1b485] The segment is not a type 1 segment. Type is # │ │ + [ 1b4b5] SPICE(INVALIDVALUE) │ │ + [ 1b4c9] DTOL should be non-negative; it is #. │ │ + [ 1b4ef] prodm │ │ + [ 1b4f5] SGFRVI │ │ + [ 1b4fc] SPKGEO │ │ + [ 1b503] OBS │ │ + [ 1b507] FRMCHG │ │ + [ 1b50e] B.C. │ │ + [ 1b515] kq │ │ + [ 1b518] SPICE(ZEROVELOCITY) │ │ + [ 1b52c] NUT_PREC_RA │ │ + [ 1b538] Insufficient number of nutation/precession angles for body * at time #. Number of angles is #; number required is #. │ │ + [ 1b5ad] bna │ │ + [ 1b5b1] bnw │ │ + [ 1b5b5] _Q │ │ + [ 1b5b8] SPICE(UNKNOWNCOMPARE) │ │ + [ 1b5ce] SETC │ │ + [ 1b5d3] WNINSD │ │ + [ 1b5da] complex format │ │ + [ 1b5e9] kernam │ │ + [ 1b5f0] ID │ │ + [ 1b5f3] ZZDDHMAN │ │ + [ 1b5fc] utlck │ │ + [ 1b602] ftabs │ │ + [ 1b608] zzddhppf_ │ │ + [ 1b612] stdlad │ │ + [ 1b619] DEF_STYLE │ │ + [ 1b623] PARAMETERIZED │ │ + [ 1b631] SPICE(NOTANINTEGER) │ │ + [ 1b645] The A,B, and C axes were #, #, and # respectively. │ │ + [ 1b678] The input vectors AXDEF and PLNDEF are linearly dependent. │ │ + [ 1b6b3] Cross product table index for right hand side of constraint # was #; valid range is 1:# │ │ + [ 1b70b] ZZEKRP2N │ │ + [ 1b714] ZZEKSZ04 │ │ + [ 1b71d] SPICE(VERSIONMISMATCH1) │ │ + [ 1b735] SPICE(VERSIONMISMATCH2) │ │ + [ 1b74d] IAU_TETHYS │ │ + [ 1b758] IAU_IAPETUS │ │ + [ 1b764] IAU_ATLAS │ │ + [ 1b76e] IAU_CERES │ │ + [ 1b778] IAU_LEUCUS │ │ + [ 1b783] SATURN BARYCENTER │ │ + [ 1b795] HIMALIA │ │ + [ 1b79d] TAYGETE │ │ + [ 1b7a5] THELXINOE │ │ + [ 1b7af] SIARNAQ │ │ + [ 1b7b7] SYCORAX │ │ + [ 1b7bf] MARS ORBITER MISSION │ │ + [ 1b7d4] PIONEER 12 │ │ + [ 1b7df] DS-1 │ │ + [ 1b7e4] VOYAGER 1 │ │ + [ 1b7ee] ORX │ │ + [ 1b7f2] MARS OBSERVER │ │ + [ 1b800] BEPICOLOMBO MPO │ │ + [ 1b810] CHANDRAYAAN-2 LANDER │ │ + [ 1b825] IMAGE │ │ + [ 1b82b] VIPER │ │ + [ 1b831] SHOEMAKER-LEVY 9-Q │ │ + [ 1b844] SHOEMAKER-LEVY 9-P │ │ + [ 1b857] SHOEMAKER-LEVY 9-H │ │ + [ 1b86a] HOWELL │ │ + [ 1b871] LONGMORE │ │ + [ 1b87a] PATROCLUS BARYCENTER │ │ + [ 1b88f] DIDYMOS_BARYCENTER │ │ + [ 1b8a2] PATROCLUS │ │ + [ 1b8ac] DSS-05 │ │ + [ 1b8b3] DSS-23 │ │ + [ 1b8ba] The latter is a CK frame; a CK file containing data for instrument or structure # at the epoch shown above, as well as a corresponding SCLK kernel, must be loaded in order to use this frame. │ │ + [ 1b979] SPICE(NEGATIVEHASHVALUE2) │ │ + [ 1b993] i.i │ │ + [ 1b997] Ye │ │ + [ 1b99a] A.M. │ │ + [ 1b99f] i:i:i │ │ + [ 1b9a5] Smi │ │ + [ 1b9a9] The numbers of partition start times # and stop times # are unequal for spacecraft clock #. │ │ + [ 1ba05] Kernel variable # for spacecraft clock # does not have numeric type. │ │ + [ 1ba4a] sclu01_ │ │ + [ 1ba52] XXSGP4I │ │ + [ 1ba5a] ZZSPKLT1 │ │ + [ 1ba63] FRAME_#_CLASS_ID │ │ + [ 1ba74] FRAME_# │ │ + [ 1ba7c] The specified item '#' is not a recognized time default item. The items that you may "SET" via the routine TIMDEF are 'CALENDAR', 'SYSTEM', or 'ZONE' │ │ + [ 1bb14] zztime_ │ │ + [ 1bb1c] The input time string '#' cannot be processed because the internal picture describing it requires more than @ characters. The token that could not be processed was '#'. │ │ + [ 1bbc5] weekday │ │ + [ 1bbcd] SUNDAY │ │ + [ 1bbd4] MM │ │ + [ 1bbd7] No numeric components were supplied in the time string. │ │ + [ 1bc10] There is more than one Julian Date specified in the epoch string. │ │ + [ 1bc53] H*MDmY │ │ + [ 1bc5a] imiin │ │ + [ 1bc60] miYi:i:i │ │ + [ 1bc69] i/i/ii:n │ │ + [ 1bc72] zzwahr_ │ │ + [ 1bc7a] VN │ │ + [ 1bc7d] cop │ │ + [ 1bc81] csw │ │ + [ 1bc85] eo │ │ + [ 1bc88] frp │ │ + [ 1bc8c] kri │ │ + [ 1bc90] liv │ │ + [ 1bc94] loz │ │ + [ 1bc98] moh │ │ + [ 1bc9c] nn │ │ + [ 1bc9f] pms │ │ + [ 1bca3] sc │ │ + [ 1bca6] was │ │ + [ 1bcaa] yav │ │ + [ 1bcae] ara │ │ + [ 1bcb2] epo │ │ + [ 1bcb6] ido │ │ + [ 1bcba] por │ │ + [ 1bcbe] mol │ │ + [ 1bcc2] BQ │ │ + [ 1bcc5] BT │ │ + [ 1bcc8] EH │ │ + [ 1bccb] IM │ │ + [ 1bcce] PF │ │ + [ 1bcd1] SD │ │ + [ 1bcd4] ARG │ │ + [ 1bcd8] BOL │ │ + [ 1bcdc] XIC │ │ + [ 1bce0] KWT │ │ + [ 1bce4] MNP │ │ + [ 1bce8] RWA │ │ + [ 1bcec] TUN │ │ + [ 1bcf0] TTO │ │ + [ 1bcf4] uprv_asciiFromEbcdic() string[%d] contains a variant character in position %d\n │ │ + [ 1bd43] as_IN │ │ + [ 1bd49] eu_ES │ │ + [ 1bd4f] fr_FR │ │ + [ 1bd55] ga_IE │ │ + [ 1bd5b] pa_IN │ │ + [ 1bd61] WST │ │ + [ 1bd65] EASST │ │ + [ 1bd6b] az_Cyrl_AZ │ │ + [ 1bd76] ba_RU │ │ + [ 1bd7c] en_SG │ │ + [ 1bd82] es_GT │ │ + [ 1bd88] fr_LU │ │ + [ 1bd8e] hr_BA │ │ + [ 1bd94] kl_GL │ │ + [ 1bd9a] ko_KP │ │ + [ 1bda0] pa_PK │ │ + [ 1bda6] en-gb-oxendict │ │ + [ 1bdb5] ssp │ │ + [ 1bdb9] gss │ │ + [ 1bdbd] zh-gan │ │ + [ 1bdc4] calendar/gregorian/DateTimePatterns%atTime │ │ + [ 1bdef] afternoon2 │ │ + [ 1bdfa] islamic │ │ + [ 1be02] Zones │ │ + [ 1be08] Keys │ │ + [ 1be0d] icu │ │ + [ 1be11] unorm2_swap(): too few bytes (%d after header) for Normalizer2 data\n │ │ + [ 1be56] U_TOO_MANY_ALIASES_ERROR │ │ + [ 1be6f] U_BRK_SEMICOLON_EXPECTED │ │ + [ 1be88] AON │ │ + [ 1be8c] ATS │ │ + [ 1be90] DDM │ │ + [ 1be94] LSL │ │ + [ 1be98] USN │ │ + [ 1be9c] sNaN │ │ + [ 1bea1] @calendar=chinese │ │ + [ 1beb3] degree │ │ + [ 1beba] UGW │ │ + [ 1bebe] VNC │ │ + [ 1bec2] microsecond │ │ + [ 1bece] quarter │ │ + [ 1bed6] dot-per-centimeter │ │ + [ 1bee9] picometer │ │ + [ 1bef3] tonne │ │ + [ 1bef9] millimeter-ofhg │ │ + [ 1bf09] milliliter │ │ + [ 1bf14] quart │ │ + [ 1bf1a] oblique │ │ + [ 1bf22] %%.%dfe%%d │ │ + [ 1bf2d] milli │ │ + [ 1bf33] cf │ │ + [ 1bf36] colNumeric │ │ + [ 1bf41] upper │ │ + [ 1bf47] expected a reset or setting or comment │ │ + [ 1bf6e] starred-relation string is not all NFD-inert │ │ + [ 1bf9b] unknown script or reorder code │ │ + [ 1bfba] last trailing │ │ + [ 1bfc8] ExemplarCharactersIndex │ │ + [ 1bfe0] PaperSize │ │ + [ 1bfea] nSetSupportedRefreshPeriods │ │ + [ 1c006] static void swappy::SwappyGL::setBufferStuffingFixWait(int32_t) │ │ + [ 1c046] eglGetError │ │ + [ 1c052] frame latency: │ │ + [ 1c06f] Initialization of SPICE library failed. │ │ + [ 1c097] frame center direction │ │ + [ 1c0ae] Unable to open log file {}\n │ │ + [ 1c0ca] C-{:c} │ │ + [ 1c0d1] invalid format string │ │ + [ 1c0e7] Cursor │ │ + [ 1c0ef] coordsys " │ │ + [ 1c0fa] Max simultaneous textures: %s\n │ │ + [ 1c119] true │ │ + [ 1c11e] {}x{} at {:.2f} fps {} │ │ + [ 1c136] Radius: {} ({} � {} � {})\n │ │ + [ 1c153] ERROR │ │ + [ 1c159] Loading library: %s\n │ │ + [ 1c16e] Failed to start backend device │ │ + [ 1c18d] mp3 │ │ + [ 1c191] Failed to load file "%s". %s.\n │ │ + [ 1c1b0] AAudioStreamBuilder_setPerformanceMode │ │ + [ 1c1d7] AAudioStreamBuilder_setAllowedCapturePolicy │ │ + [ 1c203] IGNR │ │ + [ 1c208] string_view::substr │ │ + [ 1c21c] Freeflight │ │ + [ 1c227] January │ │ + [ 1c22f] November │ │ + [ 1c238] forestgreen │ │ + [ 1c244] mistyrose │ │ + [ 1c24e] sienna │ │ + [ 1c255] wheat │ │ + [ 1c25b] .dxt5nm │ │ + [ 1c263] XDG_DATA_HOME │ │ + [ 1c271] cloudshadows │ │ + [ 1c27e] mons │ │ + [ 1c283] mensa │ │ + [ 1c289] linea │ │ + [ 1c28f] farrum │ │ + [ 1c296] follow │ │ + [ 1c29d] settextcolor │ │ + [ 1c2aa] setlinecolor │ │ + [ 1c2b7] lock │ │ + [ 1c2bc] colorbottomright │ │ + [ 1c2cd] FOV │ │ + [ 1c2d1] Argument of category:createchild must be a string or userdata! │ │ + [ 1c310] getwindowdimension │ │ + [ 1c323] setambient │ │ + [ 1c32e] setstarstyle │ │ + [ 1c33b] One argument expected for celestia:setscreendpi() │ │ + [ 1c36d] No arguments expected for celestia:getorbitflags() │ │ + [ 1c3a0] Argument to celestia:showconstellations() must be a table │ │ + [ 1c3da] No arguments expected for celestia:getminfeaturesize() │ │ + [ 1c411] First argument to celestia:takescreenshot must be a string │ │ + [ 1c44c] No argument expected for celestia:getscriptpath() │ │ + [ 1c47e] First argument to celestia:verbosity must be a number (level) │ │ + [ 1c4bc] Sixth argument to celestia:playaudio must be a boolean │ │ + [ 1c4f3] Function celestia:setaudiovolume requires two arguments │ │ + [ 1c52b] One argument required for celestia:setluahook() │ │ + [ 1c55b] Internal Error: Invalid LuaState-pointer │ │ + [ 1c584] math │ │ + [ 1c589] TexCoord │ │ + [ 1c592] [Texture:{}x{}] │ │ + [ 1c5a2] No arguments expected for texture:getwidth() │ │ + [ 1c5cf] component │ │ + [ 1c5d9] featureType │ │ + [ 1c5e5] No arguments expected to function object:localname │ │ + [ 1c618] Time expected as argument to object:getposition │ │ + [ 1c648] centerorbit │ │ + [ 1c654] Second arg to observer:gotoobject must be a number │ │ + [ 1c687] Third arg to observer:gotoobject must be a number │ │ + [ 1c6b9] Sixth argument to observer:gotolonglat must be a vector │ │ + [ 1c6f1] First arg to observer:gotodistance must be object │ │ + [ 1c723] No argument expected to observer:getfov() │ │ + [ 1c74d] First argument to observer:follow must be an object │ │ + [ 1c781] Argument to observer:setframe must be a frame │ │ + [ 1c7af] specularmap │ │ + [ 1c7bb] # {}\n │ │ + [ 1c7c1] f3\n │ │ + [ 1c7c5] uranus │ │ + [ 1c7cc] vsop87-venus │ │ + [ 1c7d9] iau-mimas │ │ + [ 1c7e3] iau-rhea │ │ + [ 1c7ec] {:02}{} │ │ + [ 1c7f5] Aps │ │ + [ 1c7f9] Phe │ │ + [ 1c7fd] Detail │ │ + [ 1c804] models/SBb.png │ │ + [ 1c813] GL_EXT_texture_compression_s3tc │ │ + [ 1c833] KingConcentration │ │ + [ 1c845] City │ │ + [ 1c84a] RU │ │ + [ 1c84d] LF │ │ + [ 1c850] MN │ │ + [ 1c853] XX │ │ + [ 1c856] UN │ │ + [ 1c859] VS │ │ + [ 1c85c] Unknown model format '{}'\n │ │ + [ 1c877] SpiceRotation │ │ + [ 1c885] Function name missing from script orbit definition.\n │ │ + [ 1c8ba] MeanLongitude │ │ + [ 1c8c8] Freeze │ │ + [ 1c8d0] void main(void)\n │ │ {\n │ │ - [ 1c8b6] emissiveTexCoord = │ │ - [ 1c8ca] = (length(ringShadowProj - ringCenter) - ringRadius) * ringWidth;\n │ │ - [ 1c90e] lunarLambert │ │ - [ 1c91b] pointFade │ │ - [ 1c925] .st).ag * 2.0 - vec2(1.0);\n │ │ - [ 1c941] )));\n │ │ - [ 1c947] color = texture2D(diffTex, gl_PointCoord);\n │ │ - [ 1c973] // buildAtmosphereVertexShader\n │ │ - [ 1c993] * texture2D(diffTex, v_TexCoord0.st);\n │ │ - [ 1c9bb] texCoordDelta{} │ │ - [ 1c9cc] vec4 calc_vp(vec4 in_Position)\n │ │ + [ 1c8e3] emissiveTexCoord = │ │ + [ 1c8f7] = (length(ringShadowProj - ringCenter) - ringRadius) * ringWidth;\n │ │ + [ 1c93b] lunarLambert │ │ + [ 1c948] pointFade │ │ + [ 1c952] .st).ag * 2.0 - vec2(1.0);\n │ │ + [ 1c96e] )));\n │ │ + [ 1c974] color = texture2D(diffTex, gl_PointCoord);\n │ │ + [ 1c9a0] // buildAtmosphereVertexShader\n │ │ + [ 1c9c0] * texture2D(diffTex, v_TexCoord0.st);\n │ │ + [ 1c9e8] texCoordDelta{} │ │ + [ 1c9f9] vec4 calc_vp(vec4 in_Position)\n │ │ {\n │ │ float PID2 = 1.570796326794896619231322;\n │ │ vec4 inPos = ModelViewMatrix * in_Position;\n │ │ float l = length(inPos.xy);\n │ │ if (l != 0.0)\n │ │ {\n │ │ float phi = atan(l, -inPos.z);\n │ │ @@ -5583,2028 +5584,2027 @@ │ │ }\n │ │ return ProjectionMatrix * inPos;\n │ │ }\n │ │ void set_vp(vec4 in_Position)\n │ │ {\n │ │ gl_Position = calc_vp(in_Position);\n │ │ }\n │ │ - [ 1cb65] set_vp(in_Position);\n │ │ - [ 1cb7f] NL = max(0.0, dot(N, │ │ - [ 1cb95] triangles_adjacency │ │ - [ 1cba9] bad alternate surface │ │ - [ 1cbbf] Error: Ending is required for all timeline phases other than the final one.\n │ │ - [ 1cc0c] MeshCenter │ │ - [ 1cc17] Invalid filename in OverlayTexture\n │ │ - [ 1cc3b] TYC {}-{}-{} │ │ - [ 1cc48] ignoring RA/Dec/Distance in favor of Position │ │ - [ 1cc76] - {} │ │ - [ 1cc7c] {}{} {}{} │ │ - [ 1cc86] Loading texture: {}\n │ │ - [ 1cc9b] dxt5nm │ │ - [ 1cca2] TileType │ │ - [ 1ccab] Failed to read chunk size\n │ │ - [ 1ccc6] Failed to read point array count\n │ │ - [ 1cce8] java/lang/String │ │ - [ 1ccf9] getObjectType │ │ - [ 1cd07] LANG │ │ - [ 1cd0c] zh_Hans │ │ - [ 1cd14] o │ │ - [ 1cd16] LC_MONETARY │ │ - [ 1cd22] LC_MESSAGES │ │ - [ 1cd2e] Invalid component ID %d in SOS │ │ - [ 1cd4d] Write to EMS failed │ │ - [ 1cd61] Huffman table 0x%02x was not defined │ │ - [ 1cd86] Invalid JPEG file structure: two SOF markers │ │ - [ 1cdb3] Define Arithmetic Table 0x%02x: 0x%02x │ │ - [ 1cdda] sfnt-table │ │ - [ 1cde5] ISOLatin1Encoding │ │ - [ 1cdf7] StartData │ │ - [ 1ce01] (Hex) │ │ - [ 1ce07] %!PS-TrueTypeFont │ │ - [ 1ce19] Windows FNT │ │ - [ 1ce25] RAW_SUBSCRIPT_X │ │ - [ 1ce35] RESOLUTION │ │ - [ 1ce40] flip_y │ │ - [ 1ce47] EndCharMetrics │ │ - [ 1ce56] EndKernData │ │ - [ 1ce62] __index__newindex__gc__mode__eq__len__lt__le__concat__call__add__sub__mul__div__mod__pow__unm__metatable__tostring__new__pairs__ipairs │ │ - [ 1ceeb] ... │ │ - [ 1ceef] .. │ │ - [ 1cef2] │ │ - [ 1ceff] kv │ │ - [ 1cf03] full^Dline^Bno │ │ - [ 1cf10] cpath │ │ - [ 1cf16] path too long │ │ - [ 1cf24] nups │ │ - [ 1cf29] unexpected end of LZ stream │ │ - [ 1cf45] invalid ICC profile color space │ │ - [ 1cf65] Image height exceeds user limit in IHDR │ │ - [ 1cf8d] libpng error: %s │ │ - [ 1cf9e] png_image_begin_read_from_memory: incorrect PNG_IMAGE_VERSION │ │ - [ 1cfdc] rgb-alpha color-map: too few entries │ │ - [ 1d001] color-map index out of range │ │ - [ 1d01e] png_set_background │ │ - [ 1d031] ignoring out of range rgb_to_gray coefficients │ │ - [ 1d060] libpng does not support gamma+background+rgb_to_gray │ │ - [ 1d095] invalid background gamma type │ │ - [ 1d0b3] bKGD must be after │ │ - [ 1d0c6] forcing save of an unhandled chunk; please call png_set_keep_unknown_chunks │ │ - [ 1d112] cHRM Red Z │ │ - [ 1d11d] Insufficient memory for pCAL purpose │ │ - [ 1d142] Invalid sCAL height ignored │ │ - [ 1d15e] Insufficient memory to process iCCP profile │ │ - [ 1d18a] zTXt: invalid compression type │ │ - [ 1d1a9] SPICE(CELLTOOSMALL) │ │ - [ 1d1bd] SPICE(INVALIDLISTITEM) │ │ - [ 1d1d4] SPICE(NAMETABLEFULL) │ │ - [ 1d1e9] The SPICELIB Limit for Number of Open Files Has Already Been Reached │ │ - [ 1d22e] Cardinality of Window Is Too Small to Contain Result of the Requested Operation │ │ - [ 1d27e] @ │ │ - [ 1d280] itprvd │ │ - [ 1d287] OLD SEGMENTS │ │ - [ 1d294] last format: %s\n │ │ - [ 1d2a5] SPICE(DAFNOSUCHADDR) │ │ - [ 1d2ba] syserr │ │ - [ 1d2c1] DAFRDR │ │ - [ 1d2c8] SPICE(DAFDPWRITEFAIL) │ │ - [ 1d2de] tbctpt │ │ - [ 1d2e5] The index # does not correspond to a loaded table. │ │ - [ 1d318] DASHFS │ │ - [ 1d31f] SPICE(PCKFILETABLEFULL) │ │ - [ 1d337] There is no room available for adding another character value to the kernel pool. │ │ - [ 1d389] SPICE(KERNELPOOLFULL) │ │ - [ 1d39f] ZZVUPOOL │ │ - [ 1d3a8] \begintext │ │ - [ 1d3b3] bnmidx │ │ - [ 1d3ba] IETH │ │ - [ 1d3bf] The input string is blank. Blank strings are not considered to be numbers. │ │ - [ 1d40b] SPICE(UNKNOWNCKMETA) │ │ - [ 1d420] ARCH │ │ - [ 1d425] TXT │ │ - [ 1d429] tframe │ │ - [ 1d430] spke21_ │ │ - [ 1d438] REMLAD │ │ - [ 1d43f] STPOOL │ │ - [ 1d446] BODY#_CONSTANTS_REF_FRAME │ │ - [ 1d460] Maximum phase angle degree for body # must be in the range 1:# but was #. │ │ - [ 1d4aa] The Text Kernel (TK) frame with ID code # does not have a recognized name. │ │ - [ 1d4f6] Names Overflowed> │ │ - [ 1d508] UNITIM │ │ - [ 1d50f] window │ │ - [ 1d516] exponent field │ │ - [ 1d525] Total number of name/ID mappings: │ │ - [ 1d548] The binary file format, '#', is not supported by this version of the toolkit. This is a serious problem, contact NAIF. │ │ - [ 1d5bf] The attempt to load file '#' as a # has failed because it is already loaded as a #. │ │ - [ 1d613] There are less files in the file table than units in the unit table, and no row with a zero-valued handle can be found. This should never occur. │ │ - [ 1d6a5] The integer code, '#' indicating the file architecture to examine is out of range. │ │ - [ 1d6f8] A request to load the # file, $, has been made by the % system. This operation is not permitted. │ │ - [ 1d75a] ZZCOREPC │ │ - [ 1d763] conmap │ │ - [ 1d76a] zzekreqi_ │ │ - [ 1d774] ZZEKPGIN │ │ - [ 1d77d] End address END was #; valid range is 1:# │ │ - [ 1d7a7] IAU_PLUTO │ │ - [ 1d7b1] IAU_LYSITHEA │ │ - [ 1d7be] IAU_MENOETIUS │ │ - [ 1d7cc] The reference frame # has class #. This form of reference frame is not supported in version # of ZZFRMGT0. You need to update your version of SPICELIB to the latest version in order to support this frame. │ │ - [ 1d89a] SOLAR SYSTEM BARYCENTER │ │ - [ 1d8b2] EARTH-MOON BARYCENTER │ │ - [ 1d8c8] SATURN_BARYCENTER │ │ - [ 1d8da] NEPTUNE_BARYCENTER │ │ - [ 1d8ed] PAN │ │ - [ 1d8f1] THRYMR │ │ - [ 1d8f8] CUPID │ │ - [ 1d8fe] JUICE │ │ - [ 1d904] CLEMENTINE │ │ - [ 1d90f] LUNAR ICECUBE │ │ - [ 1d91d] GIOTTO │ │ - [ 1d924] EXOMARS 2016 TGO │ │ - [ 1d935] INSIGHT │ │ - [ 1d93d] RSAT │ │ - [ 1d942] SHOEMAKER-LEVY 9-G │ │ - [ 1d955] SMIRNOVA-CHERNYKH │ │ - [ 1d967] IDA │ │ - [ 1d96b] DSS-12 │ │ - [ 1d972] zzphsh_ │ │ - [ 1d97a] Aberration correction specification # is not recognized. │ │ - [ 1d9b3] ZZREFCH0 │ │ - [ 1d9bc] A kernel variable was not properly formed on line # of the file #. Such an assignment should have the form: ' [+]= '. More specifically, the assignment operator did not have one of the expected forms: '=' or '+='. The line was '#'. │ │ - [ 1dabd] -n │ │ - [ 1dac0] The substring "#" is a duplicate modifier of the input string: ' │ │ - [ 1db02] │ │ + [ 1cf2c] kv │ │ + [ 1cf30] full^Dline^Bno │ │ + [ 1cf3d] cpath │ │ + [ 1cf43] path too long │ │ + [ 1cf51] nups │ │ + [ 1cf56] unexpected end of LZ stream │ │ + [ 1cf72] invalid ICC profile color space │ │ + [ 1cf92] Image height exceeds user limit in IHDR │ │ + [ 1cfba] libpng error: %s │ │ + [ 1cfcb] png_image_begin_read_from_memory: incorrect PNG_IMAGE_VERSION │ │ + [ 1d009] rgb-alpha color-map: too few entries │ │ + [ 1d02e] color-map index out of range │ │ + [ 1d04b] png_set_background │ │ + [ 1d05e] ignoring out of range rgb_to_gray coefficients │ │ + [ 1d08d] libpng does not support gamma+background+rgb_to_gray │ │ + [ 1d0c2] invalid background gamma type │ │ + [ 1d0e0] bKGD must be after │ │ + [ 1d0f3] forcing save of an unhandled chunk; please call png_set_keep_unknown_chunks │ │ + [ 1d13f] cHRM Red Z │ │ + [ 1d14a] Insufficient memory for pCAL purpose │ │ + [ 1d16f] Invalid sCAL height ignored │ │ + [ 1d18b] Insufficient memory to process iCCP profile │ │ + [ 1d1b7] zTXt: invalid compression type │ │ + [ 1d1d6] SPICE(CELLTOOSMALL) │ │ + [ 1d1ea] SPICE(INVALIDLISTITEM) │ │ + [ 1d201] SPICE(NAMETABLEFULL) │ │ + [ 1d216] The SPICELIB Limit for Number of Open Files Has Already Been Reached │ │ + [ 1d25b] Cardinality of Window Is Too Small to Contain Result of the Requested Operation │ │ + [ 1d2ab] @ │ │ + [ 1d2ad] itprvd │ │ + [ 1d2b4] OLD SEGMENTS │ │ + [ 1d2c1] last format: %s\n │ │ + [ 1d2d2] SPICE(DAFNOSUCHADDR) │ │ + [ 1d2e7] syserr │ │ + [ 1d2ee] DAFRDR │ │ + [ 1d2f5] SPICE(DAFDPWRITEFAIL) │ │ + [ 1d30b] tbctpt │ │ + [ 1d312] The index # does not correspond to a loaded table. │ │ + [ 1d345] DASHFS │ │ + [ 1d34c] SPICE(PCKFILETABLEFULL) │ │ + [ 1d364] There is no room available for adding another character value to the kernel pool. │ │ + [ 1d3b6] SPICE(KERNELPOOLFULL) │ │ + [ 1d3cc] ZZVUPOOL │ │ + [ 1d3d5] \begintext │ │ + [ 1d3e0] bnmidx │ │ + [ 1d3e7] IETH │ │ + [ 1d3ec] The input string is blank. Blank strings are not considered to be numbers. │ │ + [ 1d438] SPICE(UNKNOWNCKMETA) │ │ + [ 1d44d] ARCH │ │ + [ 1d452] TXT │ │ + [ 1d456] tframe │ │ + [ 1d45d] spke21_ │ │ + [ 1d465] REMLAD │ │ + [ 1d46c] STPOOL │ │ + [ 1d473] BODY#_CONSTANTS_REF_FRAME │ │ + [ 1d48d] Maximum phase angle degree for body # must be in the range 1:# but was #. │ │ + [ 1d4d7] The Text Kernel (TK) frame with ID code # does not have a recognized name. │ │ + [ 1d523] Names Overflowed> │ │ + [ 1d535] UNITIM │ │ + [ 1d53c] window │ │ + [ 1d543] exponent field │ │ + [ 1d552] Total number of name/ID mappings: │ │ + [ 1d575] The binary file format, '#', is not supported by this version of the toolkit. This is a serious problem, contact NAIF. │ │ + [ 1d5ec] The attempt to load file '#' as a # has failed because it is already loaded as a #. │ │ + [ 1d640] There are less files in the file table than units in the unit table, and no row with a zero-valued handle can be found. This should never occur. │ │ + [ 1d6d2] The integer code, '#' indicating the file architecture to examine is out of range. │ │ + [ 1d725] A request to load the # file, $, has been made by the % system. This operation is not permitted. │ │ + [ 1d787] ZZCOREPC │ │ + [ 1d790] conmap │ │ + [ 1d797] zzekreqi_ │ │ + [ 1d7a1] ZZEKPGIN │ │ + [ 1d7aa] End address END was #; valid range is 1:# │ │ + [ 1d7d4] IAU_PLUTO │ │ + [ 1d7de] IAU_LYSITHEA │ │ + [ 1d7eb] IAU_MENOETIUS │ │ + [ 1d7f9] The reference frame # has class #. This form of reference frame is not supported in version # of ZZFRMGT0. You need to update your version of SPICELIB to the latest version in order to support this frame. │ │ + [ 1d8c7] SOLAR SYSTEM BARYCENTER │ │ + [ 1d8df] EARTH-MOON BARYCENTER │ │ + [ 1d8f5] SATURN_BARYCENTER │ │ + [ 1d907] NEPTUNE_BARYCENTER │ │ + [ 1d91a] PAN │ │ + [ 1d91e] THRYMR │ │ + [ 1d925] CUPID │ │ + [ 1d92b] JUICE │ │ + [ 1d931] CLEMENTINE │ │ + [ 1d93c] LUNAR ICECUBE │ │ + [ 1d94a] GIOTTO │ │ + [ 1d951] EXOMARS 2016 TGO │ │ + [ 1d962] INSIGHT │ │ + [ 1d96a] RSAT │ │ + [ 1d96f] SHOEMAKER-LEVY 9-G │ │ + [ 1d982] SMIRNOVA-CHERNYKH │ │ + [ 1d994] IDA │ │ + [ 1d998] DSS-12 │ │ + [ 1d99f] zzphsh_ │ │ + [ 1d9a7] Aberration correction specification # is not recognized. │ │ + [ 1d9e0] ZZREFCH0 │ │ + [ 1d9e9] A kernel variable was not properly formed on line # of the file #. Such an assignment should have the form: ' [+]= '. More specifically, the assignment operator did not have one of the expected forms: '=' or '+='. The line was '#'. │ │ + [ 1daea] -n │ │ + [ 1daed] The substring "#" is a duplicate modifier of the input string: ' │ │ + [ 1db2f] │ │ - [ 1ee19] >> │ │ - [ 1ee1c] Lua 5.1 │ │ - [ 1ee24] sec │ │ - [ 1ee28] wday │ │ - [ 1ee2d] _LOADLIB │ │ - [ 1ee36] searchpath │ │ - [ 1ee41] 'package.%s' must be a string │ │ - [ 1ee5f] unsupported zlib version │ │ - [ 1ee78] invalid embedded Abstract ICC profile │ │ - [ 1ee9e] read beyond end of data │ │ - [ 1eeb6] invalid PNG color type │ │ - [ 1eecd] png_do_encode_alpha: unexpected call │ │ - [ 1eef2] PNG unsigned integer out of range │ │ - [ 1ef14] incorrect byte-order specifier │ │ - [ 1ef33] Not enough image data │ │ - [ 1ef49] cHRM Blue Z │ │ - [ 1ef55] sPLT out of memory │ │ - [ 1ef68] png_image_write_to_stdio: incorrect PNG_IMAGE_VERSION │ │ - [ 1ef9e] Invalid bit depth for grayscale+alpha image │ │ - [ 1efca] GETMSG: An invalid value of OPTION was input. Valid choices are 'SHORT', 'EXPLAIN', or 'LONG'. The value that was input was: │ │ - [ 1f051] SPICE(ZEROVECTOR) │ │ - [ 1f063] FURNSH │ │ - [ 1f06a] CHECK PARTIAL LIST │ │ - [ 1f07d] DAFHSF │ │ - [ 1f084] DAFGS │ │ - [ 1f08a] The EK file # contains no segments. │ │ - [ 1f0ae] SPICE(INVALIDTABLENAME) │ │ - [ 1f0c6] activv │ │ - [ 1f0cd] # is not name of a column in FROM table #. │ │ - [ 1f0f8] ocols │ │ - [ 1f0fe] The cell cannot accommodate the addition of the element *. │ │ - [ 1f13a] There are no free nodes left for allocating in the supplied linked list pool. │ │ - [ 1f189] SPICE(NOFREENODES) │ │ - [ 1f19c] LNKFSL │ │ - [ 1f1a3] Node NEXT: node number = #; backward pointer = #; forward pointer = #. Node LIST: node number = #; backward pointer = #; forward pointer = #. ("FREE" is #) │ │ - [ 1f241] wtagnt │ │ - [ 1f248] #3 │ │ - [ 1f24b] SPICE(UPDATEPENDING) │ │ - [ 1f260] were not recognized │ │ - [ 1f275] CKR05 │ │ - [ 1f27b] SPICE(NOTSUPPORTED) │ │ - [ 1f28f] NTOL should be non-negative; it is #. │ │ - [ 1f2b5] The segment is not a type 2 segment. Type is # │ │ - [ 1f2e5] SPICE(INVALIDMETADATA) │ │ - [ 1f2fc] SUCCESS │ │ - [ 1f304] double precision │ │ - [ 1f315] cover │ │ - [ 1f31b] SPKCOV │ │ - [ 1f322] 00 │ │ - [ 1f325] The periapse vector supplied to SPKE15 had length zero. The most likely cause of this problem is a corrupted SPK (ephemeris) file. │ │ - [ 1f3a9] SPICE(INVALIDSTEPSIZE) │ │ - [ 1f3c0] spkr09_ │ │ - [ 1f3c8] SPKR12 │ │ - [ 1f3cf] SPICE(MALFORMEDSEGMENT) │ │ - [ 1f3e7] bpckep │ │ - [ 1f3ee] bdcoef │ │ - [ 1f3f5] PCKE03 │ │ - [ 1f3fc] do_ud │ │ - [ 1f402] wnincd_c │ │ - [ 1f40b] SCARDD │ │ - [ 1f412] lread │ │ - [ 1f418] XF2EUL │ │ - [ 1f41f] xf2eul_ │ │ - [ 1f427] nornam │ │ - [ 1f42e] zzddhgtu_ │ │ - [ 1f438] SPICE(FILARCHMISMATCH) │ │ - [ 1f44f] The file '#' utilizes the binary file format '#'. This format is currently unknown to this toolkit. A toolkit update may be in order. │ │ - [ 1f4d7] The native architecture for this platform is unknown to this version of the toolkit. This is a severe problem that should never occur, please contact NAIF. │ │ - [ 1f573] EARTH_IAU_1980 │ │ - [ 1f582] AXIS(#) + LAMBDA/AXIS(#) is zero. │ │ - [ 1f5a4] ZZDYNOAC │ │ - [ 1f5ad] twovec_ │ │ - [ 1f5b5] EK = #; SEG = #; ROW = #; COLIDX = #; ELT = #; column entry elt was not found. │ │ - [ 1f604] SPICE(UNINITIALIZED) │ │ - [ 1f619] ZZEKPGWD │ │ - [ 1f622] SPICE(STRINGCOPYFAIL) │ │ - [ 1f638] F_Alloc │ │ - [ 1f640] F2C_CreateStrArr_Sig │ │ - [ 1f655] IAU_THEBE │ │ - [ 1f65f] ZZHSCADD │ │ - [ 1f668] The hash has no room for any more items. │ │ - [ 1f691] ADRASTEA │ │ - [ 1f69a] SKATHI │ │ - [ 1f6a1] JARNSAXA │ │ - [ 1f6aa] GEOTAIL │ │ - [ 1f6b2] NEXT │ │ - [ 1f6b7] RADIOASTRON │ │ - [ 1f6c3] LRO │ │ - [ 1f6c7] LUNAR RECONNAISSANCE ORBITER │ │ - [ 1f6e4] MGS │ │ - [ 1f6e8] INTEGRAL │ │ - [ 1f6f1] SMART LANDER FOR INVESTIGATING MOON │ │ - [ 1f715] RADIATION BELT STORM PROBE B │ │ - [ 1f732] SHOEMAKER-LEVY 9-C │ │ - [ 1f745] KOWAL 1 │ │ - [ 1f74d] VAISALA 1 │ │ - [ 1f757] WOLF-HARRINGTON │ │ - [ 1f767] WISEMAN-SKIFF │ │ - [ 1f775] C/2013 A1 │ │ - [ 1f77f] STEINS │ │ - [ 1f786] BRAILLE │ │ - [ 1f78e] SPICE(TRANSFERFILE) │ │ - [ 1f7a2] temp │ │ - [ 1f7a7] E │ │ - [ 1f7a9] BIG-IEEE LTL-IEEE │ │ - [ 1f7bb] ZZROTGT1 │ │ - [ 1f7c4] SPICE(NONPRINTINGCHAR) │ │ - [ 1f7db] oi │ │ - [ 1f7de] m* │ │ - [ 1f7e1] mD │ │ - [ 1f7e4] SCLK01_N_FIELDS_ │ │ - [ 1f7f5] The number of values associated with the kernel variable # for clock # is #, which exceeds the limit #. │ │ - [ 1f85d] SPICE(NUMPARTSUNEQUAL) │ │ - [ 1f874] SPICE(ORBITDECAY) │ │ - [ 1f886] JDTDB │ │ - [ 1f88d] ZZSPKEZ1 │ │ - [ 1f896] ZZSPKGP1 │ │ - [ 1f89f] Base frame kernel variable # exists but DTPOOL returned data type # rather than one of the expected values: 'C' or 'N'. │ │ - [ 1f917] The seconds component of '#' is out of range. On the Julian Calendar in the specified time zone (#) leapseconds can occur during the year # only in the second that immediately follows the time #:#:59 on # # and # #. │ │ - [ 1f9f2] mon │ │ - [ 1f9f6] DPFMT │ │ - [ 1f9fc] ( │ │ - [ 1f9fe] EDT │ │ - [ 1fa02] OCTOBER │ │ - [ 1fa0a] Two substrings indicating a calendar month were identified in the input time string <#> and <#>: " │ │ - [ 1fa6d] Y-iti:i:i │ │ - [ 1fa77] Yidi:n │ │ - [ 1fa7e] Yiii │ │ - [ 1fa83] YDmH*M │ │ - [ 1fa8a] Yimi:i:n │ │ - [ 1fa93] mDYH*M*S │ │ - [ 1fa9c] inm │ │ - [ 1faa0] miiiii │ │ - [ 1faa7] i/i/Yi:i │ │ - [ 1fab0] Y-i-iti:ix │ │ - [ 1fabb] ZZVALCOR │ │ - [ 1fac4] matrix │ │ - [ 1facb] AN │ │ - [ 1face] YU │ │ - [ 1fad1] CD │ │ - [ 1fad4] wuu │ │ - [ 1fad8] ak │ │ - [ 1fadb] akk │ │ - [ 1fadf] ale │ │ - [ 1fae3] bss │ │ - [ 1fae7] chy │ │ - [ 1faeb] cr │ │ - [ 1faee] dje │ │ - [ 1faf2] egy │ │ - [ 1faf6] ewo │ │ - [ 1fafa] fro │ │ - [ 1fafe] gur │ │ - [ 1fb02] ig │ │ - [ 1fb05] ilo │ │ - [ 1fb09] kaj │ │ - [ 1fb0d] kde │ │ - [ 1fb11] kru │ │ - [ 1fb15] lah │ │ - [ 1fb19] mwr │ │ - [ 1fb1d] nds │ │ - [ 1fb21] niu │ │ - [ 1fb25] nog │ │ - [ 1fb29] ny │ │ - [ 1fb2c] pdt │ │ - [ 1fb30] pon │ │ - [ 1fb34] tsd │ │ - [ 1fb38] uk │ │ - [ 1fb3b] vep │ │ - [ 1fb3f] vun │ │ - [ 1fb43] ave │ │ - [ 1fb47] dzo │ │ - [ 1fb4b] kas │ │ - [ 1fb4f] mah │ │ - [ 1fb53] mya │ │ - [ 1fb57] nob │ │ - [ 1fb5b] que │ │ - [ 1fb5f] run │ │ - [ 1fb63] xho │ │ - [ 1fb67] CG │ │ - [ 1fb6a] GL │ │ - [ 1fb6d] GW │ │ - [ 1fb70] SK │ │ - [ 1fb73] SY │ │ - [ 1fb76] TO │ │ - [ 1fb79] AUT │ │ - [ 1fb7d] CXR │ │ - [ 1fb81] GUF │ │ - [ 1fb85] GRL │ │ - [ 1fb89] IRQ │ │ - [ 1fb8d] KAZ │ │ - [ 1fb91] TZA │ │ - [ 1fb95] ne_NP │ │ - [ 1fb9b] sq_AL │ │ - [ 1fba1] sr_Latn │ │ - [ 1fba9] persist.sys.timezone │ │ - [ 1fbbe] NZST │ │ - [ 1fbc3] ANAST │ │ - [ 1fbc9] Europe/Athens │ │ - [ 1fbd7] Asia/Jerusalem │ │ - [ 1fbe6] AZOST │ │ - [ 1fbec] PYT │ │ - [ 1fbf0] match │ │ - [ 1fbf6] chr_Cher_US │ │ - [ 1fc02] ckb_Arab_IQ │ │ - [ 1fc0e] en_VI │ │ - [ 1fc14] es_VE │ │ - [ 1fc1a] fuv_NG │ │ - [ 1fc21] ibb_NG │ │ - [ 1fc28] no_NO │ │ - [ 1fc2e] quc_Latn_GT │ │ - [ 1fc3a] rm_CH │ │ - [ 1fc40] sd_Arab_PK │ │ - [ 1fc4b] wo_SN │ │ - [ 1fc51] -u │ │ - [ 1fc54] i-navajo │ │ - [ 1fc5d] nan-x-zh-min │ │ - [ 1fc6a] ja-latn-alalc97 │ │ - [ 1fc7a] afternoon1 │ │ - [ 1fc85] localeDisplayPattern │ │ - [ 1fc9a] {0}={1} │ │ - [ 1fca2] noncharacter │ │ - [ 1fcaf] U_INDEX_OUTOFBOUNDS_ERROR │ │ - [ 1fcc9] U_MALFORMED_VARIABLE_DEFINITION │ │ - [ 1fce9] U_MISPLACED_ANCHOR_START │ │ - [ 1fd02] U_MULTIPLE_COMPOUND_FILTERS │ │ - [ 1fd1e] U_UNSUPPORTED_PROPERTY │ │ - [ 1fd35] U_BRK_INIT_ERROR │ │ - [ 1fd46] U_REGEX_SET_CONTAINS_STRING │ │ - [ 1fd62] ADP │ │ - [ 1fd66] AWG │ │ - [ 1fd6a] CSD │ │ - [ 1fd6e] NGN │ │ - [ 1fd72] NPR │ │ - [ 1fd76] SDP │ │ - [ 1fd7a] SGD │ │ - [ 1fd7e] VND │ │ - [ 1fd82] YER │ │ - [ 1fd86] YUD │ │ - [ 1fd8a] ZWR │ │ - [ 1fd8e] lenient │ │ - [ 1fd96] -Subnormal │ │ - [ 1fda1] ICU_ENABLE_TENTATIVE_ERA │ │ - [ 1fdba] mole │ │ - [ 1fdbf] mile-per-gallon │ │ - [ 1fdcf] gigabyte │ │ - [ 1fdd8] solar-radius │ │ - [ 1fde5] hectopascal │ │ - [ 1fdf1] inch-ofhg │ │ - [ 1fdfb] megapascal │ │ - [ 1fe06] locative_copulative │ │ - [ 1fe1a] locales_ordinals │ │ - [ 1fe2b] locales/ │ │ - [ 1fe34] -and- │ │ - [ 1fe3a] pow4- │ │ - [ 1fe40] pow6- │ │ - [ 1fe46] pow14- │ │ - [ 1fe4d] kilo │ │ - [ 1fe52] or-narrow │ │ - [ 1fe5c] icudt75l-coll │ │ - [ 1fe6a] last implicit │ │ - [ 1fe78] at │ │ - [ 1fe7b] %.*g │ │ - [ 1fe80] setPreferredDisplayModeId │ │ - [ 1fe9a] unique_lock::lock: already locked │ │ - [ 1febc] Comet tails enabled │ │ - [ 1fed0] INF │ │ - [ 1fed4] {:02d}' {:.1f}" │ │ - [ 1fee4] kpc │ │ - [ 1fee8] Distance from center: %s\n │ │ - [ 1ff02] Temperature: %s\n │ │ - [ 1ff13] CHANNEL_AUX_27 │ │ - [ 1ff22] Already connected │ │ - [ 1ff34] Core Audio │ │ - [ 1ff3f] [OpenSL] Failed to register buffer queue callback. │ │ - [ 1ff72] [OpenSL] Failed to enqueue buffer for playback device. │ │ - [ 1ffa9] Failed to post MA_JOB_TYPE_RESOURCE_MANAGER_LOAD_DATA_BUFFER_NODE job. %s.\n │ │ - [ 1fff5] adtl │ │ - [ 1fffa] Path {} doesn't exist or isn't a directory\n │ │ - [ 20026] x │ │ - [ 20028] SyncOrbit │ │ - [ 20032] aliceblue │ │ - [ 2003c] mediumseagreen │ │ - [ 2004b] OMI │ │ - [ 2004f] CHI │ │ - [ 20053] Kappa │ │ - [ 20059] comettails │ │ - [ 20064] boundaries │ │ - [ 2006f] center │ │ - [ 20076] settextureresolution │ │ - [ 2008b] upframe │ │ - [ 20093] object │ │ - [ 2009a] square │ │ - [ 200a1] filledsquare │ │ - [ 200ae] circle │ │ - [ 200b5] Argument of category:haschild must be string or userdata! │ │ - [ 200ef] getobservers │ │ - [ 200fc] Expected three or four arguments to celestia:setconstellationcolor() │ │ - [ 20141] One argument expected for celestia:setoverlayelements() │ │ - [ 20179] No argument expected for celestia:windowbordersvisible │ │ - [ 201b0] Function celestia:pauseaudio requires one argument │ │ - [ 201e3] No arguments expected to function celestia:gettitlefont │ │ - [ 2021b] Need one argument for celestia:loadfont() │ │ - [ 20245] char │ │ - [ 2024a] class_celestia │ │ - [ 20259] LoadIdentity │ │ - [ 20266] No arguments expected for texture:getheight() │ │ - [ 20294] getmass │ │ - [ 2029c] mass │ │ - [ 202a1] getspeed │ │ - [ 202aa] Third arg to observer:gotodistance must be a number │ │ - [ 202de] Expected no arguments to observer:cancelgoto │ │ - [ 2030b] No arguments expected for observer:getlocationflags() │ │ - [ 20341] Argument to observer:setlocationflags() must be a table │ │ - [ 20379] Need two operands for addition │ │ - [ 20398] Bad {} value in material │ │ - [ 203b1] color1 │ │ - [ 203b8] linelist │ │ - [ 203c1] material\n │ │ - [ 203cb] mesh\n │ │ - [ 203d1] {}\n │ │ - [ 203d6] Texture coordinates must be present in mesh to generate tangents\n │ │ - [ 20418] jpl-emb-ssb │ │ - [ 20424] phobos │ │ - [ 2042b] iau-oberon │ │ - [ 20436] cel_script_object_ │ │ - [ 20449] galaxy150 │ │ - [ 20453] Ari │ │ - [ 20457] Psc │ │ - [ 2045b] OpenCluster │ │ - [ 20467] Spatially sorting DSOs for improved locality of reference . . .\n │ │ - [ 204a8] E4 │ │ - [ 204ab] models/E0.png │ │ - [ 204b9] FA │ │ - [ 204bc] ScriptedOrbit │ │ - [ 204ca] Could not load sampled orbit file '{}'\n │ │ - [ 204f2] FixedPosition │ │ - [ 20500] Invalid beginning date specified for SPICE orbit.\n │ │ - [ 20533] MeanEquator │ │ - [ 2053f] Primary axis missing from two-vector frame.\n │ │ - [ 2056c] diffTexCoord = │ │ - [ 2057c] vec4 color;\n │ │ - [ 20589] eyeDir_tan │ │ - [ 20594] gl_FragColor = │ │ - [ 205a8] vec2 │ │ - [ 205ad] vec3 │ │ - [ 205b2] cloudShadowTexCoord{} │ │ - [ 205c8] specFactors.{} │ │ - [ 205d7] float distAtm = length(atmEnter - atmLeave);\n │ │ - [ 20609] * exp(-extinctionCoeff * density * distSun);\n │ │ - [ 20638] vec3 ex = exp(-extinctionCoeff * density * distAtm);\n │ │ - [ 20672] scatterEx = ex;\n │ │ - [ 20687] scatterColor = (phRayleigh * rayleighCoeff + phMie * mieCoeff) * invScatterCoeffSum * sunColor * │ │ - [ 206ed] float phMie = (1.0 - mieK * mieK) / ((1.0 - mieK * cosTheta) * (1.0 - mieK * cosTheta));\n │ │ - [ 2074b] Class │ │ - [ 20751] Density │ │ - [ 20759] Height │ │ - [ 20760] V │ │ - [ 20762] Bad spectral type in star database, star #{}\n │ │ - [ 20790] {}1 {}{} │ │ - [ 20799] Processing Meshdata chunk\n │ │ - [ 207b4] Content size {} too small to include texture coord array with {} entries\n │ │ - [ 207fe] onCelestiaProgress │ │ - [ 20811] Comets │ │ - [ 20818] binary │ │ - [ 2081f] number │ │ - [ 20826] Creating renderer thread │ │ - [ 2083f] Bogus marker length │ │ - [ 20853] Empty JPEG image (DNL not supported) │ │ - [ 20878] Read from XMS failed │ │ - [ 2088d] TrueType │ │ - [ 20896] Notice │ │ - [ 2089d] Subrs │ │ - [ 208a3] CFF │ │ - [ 208a7] /FSType │ │ - [ 208af] %ADOBeginFontDict │ │ - [ 208c1] CIDFontVersion │ │ - [ 208d0] GDBytes │ │ - [ 208d8] ForceBoldThreshold │ │ - [ 208eb] ITALIC_ANGLE │ │ - [ 208f8] NOTICE │ │ - [ 208ff] SUBSCRIPT_SIZE │ │ - [ 2090e] WEIGHT │ │ - [ 20915] BBX │ │ - [ 2091c] � │ │ - [ 20921] KPX │ │ - [ 20925] XHeight │ │ - [ 2092d] variable names │ │ - [ 2093c] cannot open %s: %s │ │ - [ 2094f] __mode │ │ - [ 20956] << │ │ - [ 20959] ./?.lua;/home/vagrant/build/apple-android/LuaJIT-87ae18af97fd4de790bb6c476b212e047689cc93/output/share/luajit-2.1/?.lua;/usr/local/share/lua/5.1/?.lua;/usr/local/share/lua/5.1/?/init.lua;/home/vagrant/build/apple-android/LuaJIT-87ae18af97fd4de790bb6c476b212e047689cc93/output/share/lua/5.1/?.lua;/home/vagrant/build/apple-android/LuaJIT-87ae18af97fd4de790bb6c476b212e047689cc93/output/share/lua/5.1/?/init.lua │ │ - [ 20af3] linedefined │ │ - [ 20aff] INPUT │ │ - [ 20b05] tostring │ │ - [ 20b0e] damaged LZ stream │ │ - [ 20b20] internal error checking chromaticities │ │ - [ 20b47] length does not match profile │ │ - [ 20b65] Invalid color type/bit depth combination in IHDR │ │ - [ 20b96] Unknown interlace method in IHDR │ │ - [ 20bb7] Invalid IHDR data │ │ - [ 20bc9] internal error: array alloc │ │ - [ 20be5] png_image_begin_read_from_memory: invalid argument │ │ - [ 20c18] gray[16] color-map: too few entries │ │ - [ 20c3c] gray-alpha color-map: too few entries │ │ - [ 20c62] unknown interlace type │ │ - [ 20c79] Too much image data │ │ - [ 20c8d] zstream unclaimed │ │ - [ 20c9f] png_set_keep_unknown_chunks: no chunk list │ │ - [ 20cca] png_set_filter: UP/AVG/PAETH cannot be added after start │ │ - [ 20d03] Invalid number of colors in palette │ │ - [ 20d27] Can't write tRNS with an alpha channel │ │ - [ 20d4e] action │ │ - [ 20d55] SPICE(INVALIDEPOCH) │ │ - [ 20d69] SPICE(INVALIDINDEX) │ │ - [ 20d7d] There Is No Element Corresponding to the Supplied Index │ │ - [ 20db5] Summary size was #, should not exceed #. │ │ - [ 20dde] An attempt was made to reserve a negative number (#) of records. │ │ - [ 20e1f] Attempt to write file '#' failed. Value of IOSTAT was #. │ │ - [ 20e58] writing │ │ - [ 20e60] No array is current; the `previous' array is the last array of DAF # │ │ - [ 20ea5] EKQMGR │ │ - [ 20eac] ABORT │ │ - [ 20eb2] SPICE(BLANKFILENAME) │ │ - [ 20ec7] Action was #; should be READ or WRITE │ │ - [ 20eed] DECHAR │ │ - [ 20ef4] SPICE(BADDASDIRECTORY) │ │ - [ 20f0b] DASRRD │ │ - [ 20f12] SPICE(INDEXOUTOFRANGE) │ │ - [ 20f29] String indices FIRST and LAST were #, #; allowed range for both is [#, #]. File was #, record number was #. │ │ - [ 20f96] WRITE │ │ - [ 20f9d] NEXT was #. LIST was #. Valid range is 1 to #. │ │ - [ 20fcd] dppool │ │ - [ 20fd4] WRPOOL │ │ - [ 20fdb] chpool │ │ - [ 20fe2] CVPOOL │ │ - [ 20fe9] SPICE(BADARRAYSIZE) │ │ - [ 20ffd] GNPOOL │ │ - [ 21004] power │ │ - [ 2100a] INQUIRE error. File = #, IOSTAT = #. │ │ - [ 21030] (A) │ │ - [ 21034] EIGHT │ │ - [ 2103a] SPICE(UNKNOWNFRAMETYPE) │ │ - [ 21052] SPICE(IRFNOTREC) │ │ - [ 21063] ckmeta_ │ │ - [ 2106b] M2Q │ │ - [ 2106f] ISROT │ │ - [ 21075] scard_c │ │ - [ 2107d] SCLKDP │ │ - [ 21084] Invalid time system code # was found for SCLK #. │ │ - [ 210b5] SCEC01 │ │ - [ 210bc] SGFPKT │ │ - [ 210c3] Attempt to read from file '#' failed. IOSTAT = #. │ │ - [ 210f5] IDW2AT │ │ - [ 210fc] : │ │ - [ 210fe] SPKR08 │ │ - [ 21105] A type 15 segment should contain exactly 16 double precision values. The segment supplied had #. The segment is badly formed. │ │ - [ 21186] The input value of X must be greater than #. The input value was # │ │ - [ 211ca] bnd │ │ - [ 211ce] Bad fixed offset frame specification: the frame '#' (frame ID #) is defined relative to itself. SPICE cannot work with such frames. │ │ - [ 21253] SPICE(TRACESTACKEMPTY) │ │ - [ 2126a] bltcod │ │ - [ 21271] The file table is full, with # entries. As a result, the file '#' could not be loaded. │ │ - [ 212c8] ftrtm │ │ - [ 212ce] vname │ │ - [ 212d4] xform │ │ - [ 212da] mxmg_ │ │ - [ 212e0] zzekjoin_ │ │ - [ 212ea] ZZEKQTAB │ │ - [ 212f3] N_C_ALLOC │ │ - [ 212fd] EK stack pointer = #; call requests popping # items. │ │ - [ 21332] ZZEKWEED │ │ - [ 2133b] IAU_EARTH_BARYCENTER │ │ - [ 21350] IAU_SUN │ │ - [ 21358] IAU_MARS │ │ - [ 21361] IAU_DIONE │ │ - [ 2136b] IAU_HYPERION │ │ - [ 21378] IAU_DESPINA │ │ - [ 21384] zzfrmch0_ │ │ - [ 2138e] ZZDYNFR0 │ │ - [ 21397] ZZHSCINI │ │ - [ 213a0] DIONE │ │ - [ 213a6] STEPHANO │ │ - [ 213af] FRANCISCO │ │ - [ 213b9] P7 │ │ - [ 213bc] P8 │ │ - [ 213bf] SDU │ │ - [ 213c3] VOYAGER 2 │ │ - [ 213cd] HAYABUSA2 │ │ - [ 213d7] SUISEI │ │ - [ 213de] MARS PATHFINDER │ │ - [ 213ee] MARS SURVEYOR 01 ORBITER │ │ - [ 21407] LUNAR RECON ORBITER │ │ - [ 2141b] EOS-AM1 │ │ - [ 21423] EUROPA CLIPPER │ │ - [ 21432] LARA │ │ - [ 21437] SLIM │ │ - [ 2143c] RBSP_B │ │ - [ 21443] MTM │ │ - [ 21447] BORRELLY │ │ - [ 21450] HARRINGTON-ABELL │ │ - [ 21461] SANGUIN │ │ - [ 21469] CERES │ │ - [ 2146f] KLEOPATRA │ │ - [ 21479] DSS-65 │ │ - [ 21480] DSS-66 │ │ - [ 21487] Name not available │ │ - [ 2149a] JULIAND. │ │ - [ 214a3] .# │ │ - [ 214a6] [Z] │ │ - [ 214aa] Day # has been specified for the year #. The correct range for the day of year for this year is from 1 to #. │ │ - [ 21518] A kernel pool variable name in the input buffer exceeds the maximum allowed length #1. The actual length of the variable name is #2, the offending variable name to #3 characters: '#4'. │ │ - [ 215d1] Mean semi-major axis value, #, below allowed minimum of 0.95. This error may indicate a bad TLE set or a decayed orbit. │ │ - [ 21649] YD │ │ - [ 2164d] forml │ │ - [ 21653] ZZSPKAC1 │ │ - [ 2165c] Base frame name # of switch frame # could not be translated to a frame ID code │ │ - [ 216ac] mname │ │ - [ 216b2] The format picture must begin with a non-blank character. The picture supplied was begun with a blank. │ │ - [ 21719] MDT │ │ - [ 2171d] i-i/i:i:n │ │ - [ 21727] i-i/i:n │ │ - [ 2172f] imiii │ │ - [ 21735] m*D*Y │ │ - [ 2173b] i:ni/i/Y │ │ - [ 21744] Y-i-itix │ │ - [ 2174d] id │ │ - [ 21750] hy │ │ - [ 21753] zh__HAKKA │ │ - [ 2175d] ace │ │ - [ 21761] arp │ │ - [ 21765] chg │ │ - [ 21769] chp │ │ - [ 2176d] cy │ │ - [ 21770] dv │ │ - [ 21773] esu │ │ - [ 21777] gag │ │ - [ 2177b] gom │ │ - [ 2177f] lg │ │ - [ 21782] luy │ │ - [ 21786] mg │ │ - [ 21789] mt │ │ - [ 2178c] nap │ │ - [ 21790] nyn │ │ - [ 21794] pi │ │ - [ 21797] rif │ │ - [ 2179b] rue │ │ - [ 2179f] sco │ │ - [ 217a3] teo │ │ - [ 217a7] tkr │ │ - [ 217ab] tzm │ │ - [ 217af] vi │ │ - [ 217b2] wal │ │ - [ 217b6] est │ │ - [ 217ba] kik │ │ - [ 217be] lug │ │ - [ 217c2] ton │ │ - [ 217c6] AF │ │ - [ 217c9] CZ │ │ - [ 217cc] EA │ │ - [ 217cf] HM │ │ - [ 217d2] HT │ │ - [ 217d5] SR │ │ - [ 217d8] TC │ │ - [ 217db] VG │ │ - [ 217de] BEN │ │ - [ 217e2] BES │ │ - [ 217e6] COG │ │ - [ 217ea] DZA │ │ - [ 217ee] FRO │ │ - [ 217f2] GRD │ │ - [ 217f6] HMD │ │ - [ 217fa] KIR │ │ - [ 217fe] LIE │ │ - [ 21802] MSR │ │ - [ 21806] MUS │ │ - [ 2180a] NIU │ │ - [ 2180e] ROU │ │ - [ 21812] TCD │ │ - [ 21816] URY │ │ - [ 2181a] ROM │ │ - [ 2181e] /zoneinfo/ │ │ - [ 21829] 75.1 │ │ - [ 2182e] WAT │ │ - [ 21832] GMT │ │ - [ 21836] Chile/Continental │ │ - [ 21848] EAST │ │ - [ 2184d] de_AT │ │ - [ 21853] de_LI │ │ - [ 21859] de_LU │ │ - [ 2185f] en_HK │ │ - [ 21865] ff_Latn_SN │ │ - [ 21870] fr_CM │ │ - [ 21876] sr_Cyrl_CS │ │ - [ 21881] iw_IL │ │ - [ 21887] sa_IN │ │ - [ 2188d] sms_FI │ │ - [ 21894] bnn │ │ - [ 21898] i-pwn │ │ - [ 2189e] jsl │ │ - [ 218a2] collations │ │ - [ 218ad] %%Parent │ │ - [ 218b6] *NULL* │ │ - [ 218be] ucol_close │ │ - [ 218c9] metazone-short │ │ - [ 218d8] M05 │ │ - [ 218dc] Languages │ │ - [ 218e6] Rules │ │ - [ 218ec] languages │ │ - [ 218f6] paragraph separator │ │ - [ 2190a] other punctuation │ │ - [ 2191c] 0123456789ABCDEF<>- │ │ - [ 21930] U_NO_WRITE_PERMISSION │ │ - [ 21946] U_AMBIGUOUS_ALIAS_WARNING │ │ - [ 21960] U_INVALID_PROPERTY_PATTERN │ │ - [ 2197b] U_REGEX_MISSING_CLOSE_BRACKET │ │ - [ 21999] U_STRINGPREP_PROHIBITED_ERROR │ │ - [ 219b7] SentenceBreak │ │ - [ 219c5] ANG │ │ - [ 219c9] BRZ │ │ - [ 219cd] EUR │ │ - [ 219d1] IDR │ │ - [ 219d5] PGK │ │ - [ 219d9] VED │ │ - [ 219dd] YUN │ │ - [ 219e1] percentFormat │ │ - [ 219ef] Division impossible │ │ - [ 21a03] Division undefined │ │ - [ 21a16] -Normal │ │ - [ 21a1e] british-thermal-unit │ │ - [ 21a33] liter │ │ - [ 21a39] decimal │ │ - [ 21a41] [:digit:] │ │ - [ 21a4b] zetta │ │ - [ 21a51] tera │ │ - [ 21a56] kibi │ │ - [ 21a5b] gender │ │ - [ 21a62] missing root elements data, tailoring not supported │ │ - [ 21a96] reset primary-before ignorable not possible │ │ - [ 21ac2] modifying collation elements │ │ - [ 21adf] starred-relation string range contains a surrogate │ │ - [ 21b12] backslash escape at the end of the rule string │ │ - [ 21b41] not a valid setting/option │ │ - [ 21b5c] last tertiary ignorable │ │ - [ 21b74] ussystem │ │ - [ 21b7d] special │ │ - [ 21b85] ft_to_m │ │ - [ 21b8d] ATrace_endAsyncSection │ │ - [ 21ba4] ()Landroid/view/Display; │ │ - [ 21bbd] mAutoSwapInterval │ │ - [ 21bd0] │ │ - [ 21bd2] Chase │ │ - [ 21bd8] renderoverlay │ │ - [ 21be6] Failed to initialize renderer │ │ - [ 21c04] velocity vector │ │ - [ 21c14] C-{} │ │ - [ 21c19] width is not integer │ │ - [ 21c2e] FFVHEncoderOptions │ │ - [ 21c41] TitleFont │ │ - [ 21c4b] O │ │ - [ 21c4d] G │ │ - [ 21c4f] Y │ │ - [ 21c51] " {\n │ │ - [ 21c57] time │ │ - [ 21c5f] Track %s\n │ │ - [ 21c69] ft/s │ │ - [ 21c6e] Abs (app) mag: {:.2f} ({:.2f})\n │ │ - [ 21c8e] WARNING │ │ - [ 21c96] SSE2: %s\n │ │ - [ 21ca4] [%s]\n │ │ - [ 21caa] Format: %s -> %s\n │ │ - [ 21cc5] CHANNEL_LFE │ │ - [ 21cd1] CHANNEL_AUX_25 │ │ - [ 21ce0] Timeout │ │ - [ 21ce8] Socket operation on non-socket │ │ - [ 21d07] 8-bit Unsigned Integer │ │ - [ 21d1e] 32-bit Signed Integer │ │ - [ 21d34] Failed to post MA_JOB_TYPE_RESOURCE_MANAGER_FREE_DATA_BUFFER_NODE job. %s.\n │ │ - [ 21d80] fmt │ │ - [ 21d85] July │ │ - [ 21d8a] limegreen │ │ - [ 21d94] _ │ │ - [ 21d96] locale │ │ - [ 21d9d] EPS │ │ - [ 21da4] horizontalgrid │ │ - [ 21db3] rupes │ │ - [ 21db9] setsurface │ │ - [ 21dc4] clear │ │ - [ 21dca] visible │ │ - [ 21dd2] Celx class expected │ │ - [ 21de6] setlayoutdirection │ │ - [ 21df9] getminfeaturesize │ │ - [ 21e0b] ispaused │ │ - [ 21e14] dsos │ │ - [ 21e19] Values in table-argument to celestia:setlabelflags() must be boolean │ │ - [ 21e5e] Third argument to celestia:setconstellationcolor() must be a number │ │ - [ 21ea2] Argument to celestia:setminfeaturesize() must be a number │ │ - [ 21edc] Wrong number of arguments to function celestia:utctotdb │ │ - [ 21f14] Arguments to celestia:newposition must be either numbers or strings │ │ - [ 21f58] Two to six arguments expected to function celestia:play │ │ - [ 21f90] First argument for celestia:play must be a number │ │ - [ 21fc2] Function celestia:stopaudio requires one argument │ │ - [ 21ff4] First argument for celestia:setaudiopan must be a number │ │ - [ 2202d] Argument to celestia:getparamstring must be a string │ │ - [ 22062] Invalid mipMapMode │ │ - [ 22075] package │ │ - [ 2207d] button │ │ - [ 22084] class_celscript │ │ - [ 22094] POINTS │ │ - [ 2209b] POLYGON │ │ - [ 220a3] MODELVIEW │ │ - [ 220ad] argument 3 to gl.Color must be a number │ │ - [ 220d5] Two arguments expected for gl.BlendFunc() │ │ - [ 220ff] comet │ │ - [ 22105] gotoobject │ │ - [ 22110] One argument required for setpos │ │ - [ 22131] One argument expected for observer:synchronous │ │ - [ 22160] One argument expected for observer:lock │ │ - [ 22188] One argument expected for observer:track │ │ - [ 221b1] One argument required for observer:setframe() │ │ - [ 221df] No arguments expected for vector:normalize │ │ - [ 2220a] ?.lua; │ │ - [ 22211] Error: Unknown block type {} │ │ - [ 2222e] texcoord1 │ │ - [ 22238] callisto │ │ - [ 22241] iau-neptune │ │ - [ 2224d] Could not read XYZV binary file {}.\n │ │ - [ 22272] boundingRadius │ │ - [ 22281] Failed to load module for ScriptedRotation: {}\n │ │ - [ 222b1] galaxyTex │ │ - [ 222bb] tidalTex │ │ - [ 222c4] celestia-data │ │ - [ 222d2] Error parsing asterism "{}": expected array\n │ │ - [ 222ff] Dor │ │ - [ 22303] Lyn │ │ - [ 22307] Per │ │ - [ 2230b] Tel │ │ - [ 2230f] qupeculavnctis minoris austrinise maeleonagittanajorisiopeiasoeniboologirsacadrpiucharicornoceromedangule berenicescopisum venaticorumba australes venaticis australisyxpenforoscopiculptoretertaurodisphindhemigaygborealiscinaelopardalisilalia │ │ - [ 22401] RT │ │ - [ 22404] MO │ │ - [ 22407] FeatureHeight │ │ - [ 22415] Failed to read mesh header\n │ │ - [ 22431] Bad syntax for primary axis of two-vector frame.\n │ │ - [ 22463] -x │ │ - [ 22466] Bad two-vector frame: no target specified for vector.\n │ │ - [ 2249d] textureOffset │ │ - [ 224ab] ringCenter │ │ - [ 224b6] diff.rgb += │ │ - [ 224c3] {0}.x = dot(T, {1});\n │ │ + [ 1e9d3] FixedRotation │ │ + [ 1e9e1] DoublePrecision │ │ + [ 1e9f1] Epoch │ │ + [ 1e9f7] Rectangular │ │ + [ 1ea03] ConstantVector │ │ + [ 1ea12] Bad two-vector frame: observer object '{}' of vector not found.\n │ │ + [ 1ea53] arcmin │ │ + [ 1ea5a] Error creating shadow FBO.\n │ │ + [ 1ea76] cloudHeight │ │ + [ 1ea82] vec3 T = normalize(tangent);\n │ │ + [ 1eaa0] diffFactors │ │ + [ 1eaac] vec3 V = normalize(eyeDir_tan);\n │ │ + [ 1eacd] NH = max(0.0, dot(n, H));\n │ │ + [ 1eae8] color.a │ │ + [ 1eaf0] {}{}{}{}{}{}\n │ │ + [ 1eafe] lineWidthX │ │ + [ 1eb09] in_TexCoord3 │ │ + [ 1eb16] BodyFrame │ │ + [ 1eb20] Importance │ │ + [ 1eb2b] 3 │ │ + [ 1eb2d] 4 │ │ + [ 1eb2f] OrbitBarycenter should be either a string or an integer │ │ + [ 1eb67] invalid SpectralType │ │ + [ 1eb7c] no magnitude defined for star │ │ + [ 1eb9a] %d_%d. │ │ + [ 1eba1] 1.6.44 │ │ + [ 1eba8] Content size {} too small to include texture coord array count\n │ │ + [ 1ebe8] Content size {} too small to include smoothing group array with {} entries\n │ │ + [ 1ec34] Unknown color chunk type {}\n │ │ + [ 1ec51] Content size {} too small to include 24-bit color\n │ │ + [ 1ec84] (FFLspace/celestia/celestia/Selection;)V │ │ + [ 1ecad] jo │ │ + [ 1ecb0] DCT coefficient (lossy) or spatial difference (lossless) out of range │ │ + [ 1ecf6] Bogus input colorspace │ │ + [ 1ed0d] CCIR601 sampling not implemented yet │ │ + [ 1ed32] Unexpected marker 0x%02x │ │ + [ 1ed4b] Selected %d colors for quantization │ │ + [ 1ed6f] Closed temporary file %s │ │ + [ 1ed88] Arithmetic table 0x%02x was not defined │ │ + [ 1edb0] Registry │ │ + [ 1edb9] pfr-metrics │ │ + [ 1edc5] WEIGHT_NAME │ │ + [ 1edd1] + │ │ + [ 1edd4] RELATIVE_WEIGHT │ │ + [ 1ede6] � � │ │ + [ 1edf0] � � � │ │ + [ 1edfd] Descender │ │ + [ 1ee07] W0 │ │ + [ 1ee0a] W1 │ │ + [ 1ee0d] no value │ │ + [ 1ee16] field │ │ + [ 1ee1c] main │ │ + [ 1ee21] in function '%s' │ │ + [ 1ee33] or │ │ + [ 1ee36] return │ │ + [ 1ee3d] │ │ + [ 1ee46] >> │ │ + [ 1ee49] Lua 5.1 │ │ + [ 1ee51] sec │ │ + [ 1ee55] wday │ │ + [ 1ee5a] _LOADLIB │ │ + [ 1ee63] searchpath │ │ + [ 1ee6e] 'package.%s' must be a string │ │ + [ 1ee8c] unsupported zlib version │ │ + [ 1eea5] invalid embedded Abstract ICC profile │ │ + [ 1eecb] read beyond end of data │ │ + [ 1eee3] invalid PNG color type │ │ + [ 1eefa] png_do_encode_alpha: unexpected call │ │ + [ 1ef1f] PNG unsigned integer out of range │ │ + [ 1ef41] incorrect byte-order specifier │ │ + [ 1ef60] Not enough image data │ │ + [ 1ef76] cHRM Blue Z │ │ + [ 1ef82] sPLT out of memory │ │ + [ 1ef95] png_image_write_to_stdio: incorrect PNG_IMAGE_VERSION │ │ + [ 1efcb] Invalid bit depth for grayscale+alpha image │ │ + [ 1eff7] GETMSG: An invalid value of OPTION was input. Valid choices are 'SHORT', 'EXPLAIN', or 'LONG'. The value that was input was: │ │ + [ 1f07e] SPICE(ZEROVECTOR) │ │ + [ 1f090] FURNSH │ │ + [ 1f097] CHECK PARTIAL LIST │ │ + [ 1f0aa] DAFHSF │ │ + [ 1f0b1] DAFGS │ │ + [ 1f0b7] The EK file # contains no segments. │ │ + [ 1f0db] SPICE(INVALIDTABLENAME) │ │ + [ 1f0f3] activv │ │ + [ 1f0fa] # is not name of a column in FROM table #. │ │ + [ 1f125] ocols │ │ + [ 1f12b] The cell cannot accommodate the addition of the element *. │ │ + [ 1f167] There are no free nodes left for allocating in the supplied linked list pool. │ │ + [ 1f1b6] SPICE(NOFREENODES) │ │ + [ 1f1c9] LNKFSL │ │ + [ 1f1d0] Node NEXT: node number = #; backward pointer = #; forward pointer = #. Node LIST: node number = #; backward pointer = #; forward pointer = #. ("FREE" is #) │ │ + [ 1f26e] wtagnt │ │ + [ 1f275] #3 │ │ + [ 1f278] SPICE(UPDATEPENDING) │ │ + [ 1f28d] were not recognized │ │ + [ 1f2a2] CKR05 │ │ + [ 1f2a8] SPICE(NOTSUPPORTED) │ │ + [ 1f2bc] NTOL should be non-negative; it is #. │ │ + [ 1f2e2] The segment is not a type 2 segment. Type is # │ │ + [ 1f312] SPICE(INVALIDMETADATA) │ │ + [ 1f329] SUCCESS │ │ + [ 1f331] double precision │ │ + [ 1f342] cover │ │ + [ 1f348] SPKCOV │ │ + [ 1f34f] 00 │ │ + [ 1f352] The periapse vector supplied to SPKE15 had length zero. The most likely cause of this problem is a corrupted SPK (ephemeris) file. │ │ + [ 1f3d6] SPICE(INVALIDSTEPSIZE) │ │ + [ 1f3ed] spkr09_ │ │ + [ 1f3f5] SPKR12 │ │ + [ 1f3fc] SPICE(MALFORMEDSEGMENT) │ │ + [ 1f414] bpckep │ │ + [ 1f41b] bdcoef │ │ + [ 1f422] PCKE03 │ │ + [ 1f429] do_ud │ │ + [ 1f42f] wnincd_c │ │ + [ 1f438] SCARDD │ │ + [ 1f43f] lread │ │ + [ 1f445] XF2EUL │ │ + [ 1f44c] xf2eul_ │ │ + [ 1f454] nornam │ │ + [ 1f45b] zzddhgtu_ │ │ + [ 1f465] SPICE(FILARCHMISMATCH) │ │ + [ 1f47c] The file '#' utilizes the binary file format '#'. This format is currently unknown to this toolkit. A toolkit update may be in order. │ │ + [ 1f504] The native architecture for this platform is unknown to this version of the toolkit. This is a severe problem that should never occur, please contact NAIF. │ │ + [ 1f5a0] EARTH_IAU_1980 │ │ + [ 1f5af] AXIS(#) + LAMBDA/AXIS(#) is zero. │ │ + [ 1f5d1] ZZDYNOAC │ │ + [ 1f5da] twovec_ │ │ + [ 1f5e2] EK = #; SEG = #; ROW = #; COLIDX = #; ELT = #; column entry elt was not found. │ │ + [ 1f631] SPICE(UNINITIALIZED) │ │ + [ 1f646] ZZEKPGWD │ │ + [ 1f64f] SPICE(STRINGCOPYFAIL) │ │ + [ 1f665] F_Alloc │ │ + [ 1f66d] F2C_CreateStrArr_Sig │ │ + [ 1f682] IAU_THEBE │ │ + [ 1f68c] ZZHSCADD │ │ + [ 1f695] The hash has no room for any more items. │ │ + [ 1f6be] ADRASTEA │ │ + [ 1f6c7] SKATHI │ │ + [ 1f6ce] JARNSAXA │ │ + [ 1f6d7] GEOTAIL │ │ + [ 1f6df] NEXT │ │ + [ 1f6e4] RADIOASTRON │ │ + [ 1f6f0] LRO │ │ + [ 1f6f4] LUNAR RECONNAISSANCE ORBITER │ │ + [ 1f711] MGS │ │ + [ 1f715] INTEGRAL │ │ + [ 1f71e] SMART LANDER FOR INVESTIGATING MOON │ │ + [ 1f742] RADIATION BELT STORM PROBE B │ │ + [ 1f75f] SHOEMAKER-LEVY 9-C │ │ + [ 1f772] KOWAL 1 │ │ + [ 1f77a] VAISALA 1 │ │ + [ 1f784] WOLF-HARRINGTON │ │ + [ 1f794] WISEMAN-SKIFF │ │ + [ 1f7a2] C/2013 A1 │ │ + [ 1f7ac] STEINS │ │ + [ 1f7b3] BRAILLE │ │ + [ 1f7bb] SPICE(TRANSFERFILE) │ │ + [ 1f7cf] temp │ │ + [ 1f7d4] E │ │ + [ 1f7d6] BIG-IEEE LTL-IEEE │ │ + [ 1f7e8] ZZROTGT1 │ │ + [ 1f7f1] SPICE(NONPRINTINGCHAR) │ │ + [ 1f808] oi │ │ + [ 1f80b] m* │ │ + [ 1f80e] mD │ │ + [ 1f811] SCLK01_N_FIELDS_ │ │ + [ 1f822] The number of values associated with the kernel variable # for clock # is #, which exceeds the limit #. │ │ + [ 1f88a] SPICE(NUMPARTSUNEQUAL) │ │ + [ 1f8a1] SPICE(ORBITDECAY) │ │ + [ 1f8b3] JDTDB │ │ + [ 1f8ba] ZZSPKEZ1 │ │ + [ 1f8c3] ZZSPKGP1 │ │ + [ 1f8cc] Base frame kernel variable # exists but DTPOOL returned data type # rather than one of the expected values: 'C' or 'N'. │ │ + [ 1f944] The seconds component of '#' is out of range. On the Julian Calendar in the specified time zone (#) leapseconds can occur during the year # only in the second that immediately follows the time #:#:59 on # # and # #. │ │ + [ 1fa1f] mon │ │ + [ 1fa23] DPFMT │ │ + [ 1fa29] ( │ │ + [ 1fa2b] EDT │ │ + [ 1fa2f] OCTOBER │ │ + [ 1fa37] Two substrings indicating a calendar month were identified in the input time string <#> and <#>: " │ │ + [ 1fa9a] Y-iti:i:i │ │ + [ 1faa4] Yidi:n │ │ + [ 1faab] Yiii │ │ + [ 1fab0] YDmH*M │ │ + [ 1fab7] Yimi:i:n │ │ + [ 1fac0] mDYH*M*S │ │ + [ 1fac9] inm │ │ + [ 1facd] miiiii │ │ + [ 1fad4] i/i/Yi:i │ │ + [ 1fadd] Y-i-iti:ix │ │ + [ 1fae8] ZZVALCOR │ │ + [ 1faf1] matrix │ │ + [ 1faf8] AN │ │ + [ 1fafb] YU │ │ + [ 1fafe] CD │ │ + [ 1fb01] wuu │ │ + [ 1fb05] ak │ │ + [ 1fb08] akk │ │ + [ 1fb0c] ale │ │ + [ 1fb10] bss │ │ + [ 1fb14] chy │ │ + [ 1fb18] cr │ │ + [ 1fb1b] dje │ │ + [ 1fb1f] egy │ │ + [ 1fb23] ewo │ │ + [ 1fb27] fro │ │ + [ 1fb2b] gur │ │ + [ 1fb2f] ig │ │ + [ 1fb32] ilo │ │ + [ 1fb36] kaj │ │ + [ 1fb3a] kde │ │ + [ 1fb3e] kru │ │ + [ 1fb42] lah │ │ + [ 1fb46] mwr │ │ + [ 1fb4a] nds │ │ + [ 1fb4e] niu │ │ + [ 1fb52] nog │ │ + [ 1fb56] ny │ │ + [ 1fb59] pdt │ │ + [ 1fb5d] pon │ │ + [ 1fb61] tsd │ │ + [ 1fb65] uk │ │ + [ 1fb68] vep │ │ + [ 1fb6c] vun │ │ + [ 1fb70] ave │ │ + [ 1fb74] dzo │ │ + [ 1fb78] kas │ │ + [ 1fb7c] mah │ │ + [ 1fb80] mya │ │ + [ 1fb84] nob │ │ + [ 1fb88] que │ │ + [ 1fb8c] run │ │ + [ 1fb90] xho │ │ + [ 1fb94] CG │ │ + [ 1fb97] GL │ │ + [ 1fb9a] GW │ │ + [ 1fb9d] SK │ │ + [ 1fba0] SY │ │ + [ 1fba3] TO │ │ + [ 1fba6] AUT │ │ + [ 1fbaa] CXR │ │ + [ 1fbae] GUF │ │ + [ 1fbb2] GRL │ │ + [ 1fbb6] IRQ │ │ + [ 1fbba] KAZ │ │ + [ 1fbbe] TZA │ │ + [ 1fbc2] ne_NP │ │ + [ 1fbc8] sq_AL │ │ + [ 1fbce] sr_Latn │ │ + [ 1fbd6] persist.sys.timezone │ │ + [ 1fbeb] NZST │ │ + [ 1fbf0] ANAST │ │ + [ 1fbf6] Europe/Athens │ │ + [ 1fc04] Asia/Jerusalem │ │ + [ 1fc13] AZOST │ │ + [ 1fc19] PYT │ │ + [ 1fc1d] match │ │ + [ 1fc23] chr_Cher_US │ │ + [ 1fc2f] ckb_Arab_IQ │ │ + [ 1fc3b] en_VI │ │ + [ 1fc41] es_VE │ │ + [ 1fc47] fuv_NG │ │ + [ 1fc4e] ibb_NG │ │ + [ 1fc55] no_NO │ │ + [ 1fc5b] quc_Latn_GT │ │ + [ 1fc67] rm_CH │ │ + [ 1fc6d] sd_Arab_PK │ │ + [ 1fc78] wo_SN │ │ + [ 1fc7e] -u │ │ + [ 1fc81] i-navajo │ │ + [ 1fc8a] nan-x-zh-min │ │ + [ 1fc97] ja-latn-alalc97 │ │ + [ 1fca7] afternoon1 │ │ + [ 1fcb2] localeDisplayPattern │ │ + [ 1fcc7] {0}={1} │ │ + [ 1fccf] noncharacter │ │ + [ 1fcdc] U_INDEX_OUTOFBOUNDS_ERROR │ │ + [ 1fcf6] U_MALFORMED_VARIABLE_DEFINITION │ │ + [ 1fd16] U_MISPLACED_ANCHOR_START │ │ + [ 1fd2f] U_MULTIPLE_COMPOUND_FILTERS │ │ + [ 1fd4b] U_UNSUPPORTED_PROPERTY │ │ + [ 1fd62] U_BRK_INIT_ERROR │ │ + [ 1fd73] U_REGEX_SET_CONTAINS_STRING │ │ + [ 1fd8f] ADP │ │ + [ 1fd93] AWG │ │ + [ 1fd97] CSD │ │ + [ 1fd9b] NGN │ │ + [ 1fd9f] NPR │ │ + [ 1fda3] SDP │ │ + [ 1fda7] SGD │ │ + [ 1fdab] VND │ │ + [ 1fdaf] YER │ │ + [ 1fdb3] YUD │ │ + [ 1fdb7] ZWR │ │ + [ 1fdbb] lenient │ │ + [ 1fdc3] -Subnormal │ │ + [ 1fdce] ICU_ENABLE_TENTATIVE_ERA │ │ + [ 1fde7] mole │ │ + [ 1fdec] mile-per-gallon │ │ + [ 1fdfc] gigabyte │ │ + [ 1fe05] solar-radius │ │ + [ 1fe12] hectopascal │ │ + [ 1fe1e] inch-ofhg │ │ + [ 1fe28] megapascal │ │ + [ 1fe33] locative_copulative │ │ + [ 1fe47] locales_ordinals │ │ + [ 1fe58] locales/ │ │ + [ 1fe61] -and- │ │ + [ 1fe67] pow4- │ │ + [ 1fe6d] pow6- │ │ + [ 1fe73] pow14- │ │ + [ 1fe7a] kilo │ │ + [ 1fe7f] or-narrow │ │ + [ 1fe89] icudt75l-coll │ │ + [ 1fe97] last implicit │ │ + [ 1fea5] at │ │ + [ 1fea8] %.*g │ │ + [ 1fead] setPreferredDisplayModeId │ │ + [ 1fec7] unique_lock::lock: already locked │ │ + [ 1fee9] Comet tails enabled │ │ + [ 1fefd] INF │ │ + [ 1ff01] {:02d}' {:.1f}" │ │ + [ 1ff11] kpc │ │ + [ 1ff15] Distance from center: %s\n │ │ + [ 1ff2f] Temperature: %s\n │ │ + [ 1ff40] CHANNEL_AUX_27 │ │ + [ 1ff4f] Already connected │ │ + [ 1ff61] Core Audio │ │ + [ 1ff6c] [OpenSL] Failed to register buffer queue callback. │ │ + [ 1ff9f] [OpenSL] Failed to enqueue buffer for playback device. │ │ + [ 1ffd6] Failed to post MA_JOB_TYPE_RESOURCE_MANAGER_LOAD_DATA_BUFFER_NODE job. %s.\n │ │ + [ 20022] adtl │ │ + [ 20027] Path {} doesn't exist or isn't a directory\n │ │ + [ 20053] x │ │ + [ 20055] SyncOrbit │ │ + [ 2005f] aliceblue │ │ + [ 20069] mediumseagreen │ │ + [ 20078] OMI │ │ + [ 2007c] CHI │ │ + [ 20080] Kappa │ │ + [ 20086] comettails │ │ + [ 20091] boundaries │ │ + [ 2009c] center │ │ + [ 200a3] settextureresolution │ │ + [ 200b8] upframe │ │ + [ 200c0] object │ │ + [ 200c7] square │ │ + [ 200ce] filledsquare │ │ + [ 200db] circle │ │ + [ 200e2] Argument of category:haschild must be string or userdata! │ │ + [ 2011c] getobservers │ │ + [ 20129] Expected three or four arguments to celestia:setconstellationcolor() │ │ + [ 2016e] One argument expected for celestia:setoverlayelements() │ │ + [ 201a6] No argument expected for celestia:windowbordersvisible │ │ + [ 201dd] Function celestia:pauseaudio requires one argument │ │ + [ 20210] No arguments expected to function celestia:gettitlefont │ │ + [ 20248] Need one argument for celestia:loadfont() │ │ + [ 20272] char │ │ + [ 20277] class_celestia │ │ + [ 20286] LoadIdentity │ │ + [ 20293] No arguments expected for texture:getheight() │ │ + [ 202c1] getmass │ │ + [ 202c9] mass │ │ + [ 202ce] getspeed │ │ + [ 202d7] Third arg to observer:gotodistance must be a number │ │ + [ 2030b] Expected no arguments to observer:cancelgoto │ │ + [ 20338] No arguments expected for observer:getlocationflags() │ │ + [ 2036e] Argument to observer:setlocationflags() must be a table │ │ + [ 203a6] Need two operands for addition │ │ + [ 203c5] Bad {} value in material │ │ + [ 203de] color1 │ │ + [ 203e5] linelist │ │ + [ 203ee] material\n │ │ + [ 203f8] mesh\n │ │ + [ 203fe] {}\n │ │ + [ 20403] Texture coordinates must be present in mesh to generate tangents\n │ │ + [ 20445] jpl-emb-ssb │ │ + [ 20451] phobos │ │ + [ 20458] iau-oberon │ │ + [ 20463] cel_script_object_ │ │ + [ 20476] galaxy150 │ │ + [ 20480] Ari │ │ + [ 20484] Psc │ │ + [ 20488] OpenCluster │ │ + [ 20494] Spatially sorting DSOs for improved locality of reference . . .\n │ │ + [ 204d5] E4 │ │ + [ 204d8] models/E0.png │ │ + [ 204e6] FA │ │ + [ 204e9] ScriptedOrbit │ │ + [ 204f7] Could not load sampled orbit file '{}'\n │ │ + [ 2051f] FixedPosition │ │ + [ 2052d] Invalid beginning date specified for SPICE orbit.\n │ │ + [ 20560] MeanEquator │ │ + [ 2056c] Primary axis missing from two-vector frame.\n │ │ + [ 20599] diffTexCoord = │ │ + [ 205a9] vec4 color;\n │ │ + [ 205b6] eyeDir_tan │ │ + [ 205c1] gl_FragColor = │ │ + [ 205d5] vec2 │ │ + [ 205da] vec3 │ │ + [ 205df] cloudShadowTexCoord{} │ │ + [ 205f5] specFactors.{} │ │ + [ 20604] float distAtm = length(atmEnter - atmLeave);\n │ │ + [ 20636] * exp(-extinctionCoeff * density * distSun);\n │ │ + [ 20665] vec3 ex = exp(-extinctionCoeff * density * distAtm);\n │ │ + [ 2069f] scatterEx = ex;\n │ │ + [ 206b4] scatterColor = (phRayleigh * rayleighCoeff + phMie * mieCoeff) * invScatterCoeffSum * sunColor * │ │ + [ 2071a] float phMie = (1.0 - mieK * mieK) / ((1.0 - mieK * cosTheta) * (1.0 - mieK * cosTheta));\n │ │ + [ 20778] Class │ │ + [ 2077e] Density │ │ + [ 20786] Height │ │ + [ 2078d] V │ │ + [ 2078f] Bad spectral type in star database, star #{}\n │ │ + [ 207bd] {}1 {}{} │ │ + [ 207c6] Processing Meshdata chunk\n │ │ + [ 207e1] Content size {} too small to include texture coord array with {} entries\n │ │ + [ 2082b] onCelestiaProgress │ │ + [ 2083e] Comets │ │ + [ 20845] binary │ │ + [ 2084c] number │ │ + [ 20853] Creating renderer thread │ │ + [ 2086c] Bogus marker length │ │ + [ 20880] Empty JPEG image (DNL not supported) │ │ + [ 208a5] Read from XMS failed │ │ + [ 208ba] TrueType │ │ + [ 208c3] Notice │ │ + [ 208ca] Subrs │ │ + [ 208d0] CFF │ │ + [ 208d4] /FSType │ │ + [ 208dc] %ADOBeginFontDict │ │ + [ 208ee] CIDFontVersion │ │ + [ 208fd] GDBytes │ │ + [ 20905] ForceBoldThreshold │ │ + [ 20918] ITALIC_ANGLE │ │ + [ 20925] NOTICE │ │ + [ 2092c] SUBSCRIPT_SIZE │ │ + [ 2093b] WEIGHT │ │ + [ 20942] BBX │ │ + [ 20949] � │ │ + [ 2094e] KPX │ │ + [ 20952] XHeight │ │ + [ 2095a] variable names │ │ + [ 20969] cannot open %s: %s │ │ + [ 2097c] __mode │ │ + [ 20983] << │ │ + [ 20986] ./?.lua;/home/vagrant/build/apple-android/LuaJIT-87ae18af97fd4de790bb6c476b212e047689cc93/output/share/luajit-2.1/?.lua;/usr/local/share/lua/5.1/?.lua;/usr/local/share/lua/5.1/?/init.lua;/home/vagrant/build/apple-android/LuaJIT-87ae18af97fd4de790bb6c476b212e047689cc93/output/share/lua/5.1/?.lua;/home/vagrant/build/apple-android/LuaJIT-87ae18af97fd4de790bb6c476b212e047689cc93/output/share/lua/5.1/?/init.lua │ │ + [ 20b20] linedefined │ │ + [ 20b2c] INPUT │ │ + [ 20b32] tostring │ │ + [ 20b3b] damaged LZ stream │ │ + [ 20b4d] internal error checking chromaticities │ │ + [ 20b74] length does not match profile │ │ + [ 20b92] Invalid color type/bit depth combination in IHDR │ │ + [ 20bc3] Unknown interlace method in IHDR │ │ + [ 20be4] Invalid IHDR data │ │ + [ 20bf6] internal error: array alloc │ │ + [ 20c12] png_image_begin_read_from_memory: invalid argument │ │ + [ 20c45] gray[16] color-map: too few entries │ │ + [ 20c69] gray-alpha color-map: too few entries │ │ + [ 20c8f] unknown interlace type │ │ + [ 20ca6] Too much image data │ │ + [ 20cba] zstream unclaimed │ │ + [ 20ccc] png_set_keep_unknown_chunks: no chunk list │ │ + [ 20cf7] png_set_filter: UP/AVG/PAETH cannot be added after start │ │ + [ 20d30] Invalid number of colors in palette │ │ + [ 20d54] Can't write tRNS with an alpha channel │ │ + [ 20d7b] action │ │ + [ 20d82] SPICE(INVALIDEPOCH) │ │ + [ 20d96] SPICE(INVALIDINDEX) │ │ + [ 20daa] There Is No Element Corresponding to the Supplied Index │ │ + [ 20de2] Summary size was #, should not exceed #. │ │ + [ 20e0b] An attempt was made to reserve a negative number (#) of records. │ │ + [ 20e4c] Attempt to write file '#' failed. Value of IOSTAT was #. │ │ + [ 20e85] writing │ │ + [ 20e8d] No array is current; the `previous' array is the last array of DAF # │ │ + [ 20ed2] EKQMGR │ │ + [ 20ed9] ABORT │ │ + [ 20edf] SPICE(BLANKFILENAME) │ │ + [ 20ef4] Action was #; should be READ or WRITE │ │ + [ 20f1a] DECHAR │ │ + [ 20f21] SPICE(BADDASDIRECTORY) │ │ + [ 20f38] DASRRD │ │ + [ 20f3f] SPICE(INDEXOUTOFRANGE) │ │ + [ 20f56] String indices FIRST and LAST were #, #; allowed range for both is [#, #]. File was #, record number was #. │ │ + [ 20fc3] WRITE │ │ + [ 20fca] NEXT was #. LIST was #. Valid range is 1 to #. │ │ + [ 20ffa] dppool │ │ + [ 21001] WRPOOL │ │ + [ 21008] chpool │ │ + [ 2100f] CVPOOL │ │ + [ 21016] SPICE(BADARRAYSIZE) │ │ + [ 2102a] GNPOOL │ │ + [ 21031] power │ │ + [ 21037] INQUIRE error. File = #, IOSTAT = #. │ │ + [ 2105d] (A) │ │ + [ 21061] EIGHT │ │ + [ 21067] SPICE(UNKNOWNFRAMETYPE) │ │ + [ 2107f] SPICE(IRFNOTREC) │ │ + [ 21090] ckmeta_ │ │ + [ 21098] M2Q │ │ + [ 2109c] ISROT │ │ + [ 210a2] scard_c │ │ + [ 210aa] SCLKDP │ │ + [ 210b1] Invalid time system code # was found for SCLK #. │ │ + [ 210e2] SCEC01 │ │ + [ 210e9] SGFPKT │ │ + [ 210f0] Attempt to read from file '#' failed. IOSTAT = #. │ │ + [ 21122] IDW2AT │ │ + [ 21129] : │ │ + [ 2112b] SPKR08 │ │ + [ 21132] A type 15 segment should contain exactly 16 double precision values. The segment supplied had #. The segment is badly formed. │ │ + [ 211b3] The input value of X must be greater than #. The input value was # │ │ + [ 211f7] bnd │ │ + [ 211fb] Bad fixed offset frame specification: the frame '#' (frame ID #) is defined relative to itself. SPICE cannot work with such frames. │ │ + [ 21280] SPICE(TRACESTACKEMPTY) │ │ + [ 21297] bltcod │ │ + [ 2129e] The file table is full, with # entries. As a result, the file '#' could not be loaded. │ │ + [ 212f5] ftrtm │ │ + [ 212fb] vname │ │ + [ 21301] xform │ │ + [ 21307] mxmg_ │ │ + [ 2130d] zzekjoin_ │ │ + [ 21317] ZZEKQTAB │ │ + [ 21320] N_C_ALLOC │ │ + [ 2132a] EK stack pointer = #; call requests popping # items. │ │ + [ 2135f] ZZEKWEED │ │ + [ 21368] IAU_EARTH_BARYCENTER │ │ + [ 2137d] IAU_SUN │ │ + [ 21385] IAU_MARS │ │ + [ 2138e] IAU_DIONE │ │ + [ 21398] IAU_HYPERION │ │ + [ 213a5] IAU_DESPINA │ │ + [ 213b1] zzfrmch0_ │ │ + [ 213bb] ZZDYNFR0 │ │ + [ 213c4] ZZHSCINI │ │ + [ 213cd] DIONE │ │ + [ 213d3] STEPHANO │ │ + [ 213dc] FRANCISCO │ │ + [ 213e6] P7 │ │ + [ 213e9] P8 │ │ + [ 213ec] SDU │ │ + [ 213f0] VOYAGER 2 │ │ + [ 213fa] HAYABUSA2 │ │ + [ 21404] SUISEI │ │ + [ 2140b] MARS PATHFINDER │ │ + [ 2141b] MARS SURVEYOR 01 ORBITER │ │ + [ 21434] LUNAR RECON ORBITER │ │ + [ 21448] EOS-AM1 │ │ + [ 21450] EUROPA CLIPPER │ │ + [ 2145f] LARA │ │ + [ 21464] SLIM │ │ + [ 21469] RBSP_B │ │ + [ 21470] MTM │ │ + [ 21474] BORRELLY │ │ + [ 2147d] HARRINGTON-ABELL │ │ + [ 2148e] SANGUIN │ │ + [ 21496] CERES │ │ + [ 2149c] KLEOPATRA │ │ + [ 214a6] DSS-65 │ │ + [ 214ad] DSS-66 │ │ + [ 214b4] Name not available │ │ + [ 214c7] JULIAND. │ │ + [ 214d0] .# │ │ + [ 214d3] [Z] │ │ + [ 214d7] Day # has been specified for the year #. The correct range for the day of year for this year is from 1 to #. │ │ + [ 21545] A kernel pool variable name in the input buffer exceeds the maximum allowed length #1. The actual length of the variable name is #2, the offending variable name to #3 characters: '#4'. │ │ + [ 215fe] Mean semi-major axis value, #, below allowed minimum of 0.95. This error may indicate a bad TLE set or a decayed orbit. │ │ + [ 21676] YD │ │ + [ 2167a] forml │ │ + [ 21680] ZZSPKAC1 │ │ + [ 21689] Base frame name # of switch frame # could not be translated to a frame ID code │ │ + [ 216d9] mname │ │ + [ 216df] The format picture must begin with a non-blank character. The picture supplied was begun with a blank. │ │ + [ 21746] MDT │ │ + [ 2174a] i-i/i:i:n │ │ + [ 21754] i-i/i:n │ │ + [ 2175c] imiii │ │ + [ 21762] m*D*Y │ │ + [ 21768] i:ni/i/Y │ │ + [ 21771] Y-i-itix │ │ + [ 2177a] id │ │ + [ 2177d] hy │ │ + [ 21780] zh__HAKKA │ │ + [ 2178a] ace │ │ + [ 2178e] arp │ │ + [ 21792] chg │ │ + [ 21796] chp │ │ + [ 2179a] cy │ │ + [ 2179d] dv │ │ + [ 217a0] esu │ │ + [ 217a4] gag │ │ + [ 217a8] gom │ │ + [ 217ac] lg │ │ + [ 217af] luy │ │ + [ 217b3] mg │ │ + [ 217b6] mt │ │ + [ 217b9] nap │ │ + [ 217bd] nyn │ │ + [ 217c1] pi │ │ + [ 217c4] rif │ │ + [ 217c8] rue │ │ + [ 217cc] sco │ │ + [ 217d0] teo │ │ + [ 217d4] tkr │ │ + [ 217d8] tzm │ │ + [ 217dc] vi │ │ + [ 217df] wal │ │ + [ 217e3] est │ │ + [ 217e7] kik │ │ + [ 217eb] lug │ │ + [ 217ef] ton │ │ + [ 217f3] AF │ │ + [ 217f6] CZ │ │ + [ 217f9] EA │ │ + [ 217fc] HM │ │ + [ 217ff] HT │ │ + [ 21802] SR │ │ + [ 21805] TC │ │ + [ 21808] VG │ │ + [ 2180b] BEN │ │ + [ 2180f] BES │ │ + [ 21813] COG │ │ + [ 21817] DZA │ │ + [ 2181b] FRO │ │ + [ 2181f] GRD │ │ + [ 21823] HMD │ │ + [ 21827] KIR │ │ + [ 2182b] LIE │ │ + [ 2182f] MSR │ │ + [ 21833] MUS │ │ + [ 21837] NIU │ │ + [ 2183b] ROU │ │ + [ 2183f] TCD │ │ + [ 21843] URY │ │ + [ 21847] ROM │ │ + [ 2184b] /zoneinfo/ │ │ + [ 21856] 75.1 │ │ + [ 2185b] WAT │ │ + [ 2185f] GMT │ │ + [ 21863] Chile/Continental │ │ + [ 21875] EAST │ │ + [ 2187a] de_AT │ │ + [ 21880] de_LI │ │ + [ 21886] de_LU │ │ + [ 2188c] en_HK │ │ + [ 21892] ff_Latn_SN │ │ + [ 2189d] fr_CM │ │ + [ 218a3] sr_Cyrl_CS │ │ + [ 218ae] iw_IL │ │ + [ 218b4] sa_IN │ │ + [ 218ba] sms_FI │ │ + [ 218c1] bnn │ │ + [ 218c5] i-pwn │ │ + [ 218cb] jsl │ │ + [ 218cf] collations │ │ + [ 218da] %%Parent │ │ + [ 218e3] *NULL* │ │ + [ 218eb] ucol_close │ │ + [ 218f6] metazone-short │ │ + [ 21905] M05 │ │ + [ 21909] Languages │ │ + [ 21913] Rules │ │ + [ 21919] languages │ │ + [ 21923] paragraph separator │ │ + [ 21937] other punctuation │ │ + [ 21949] 0123456789ABCDEF<>- │ │ + [ 2195d] U_NO_WRITE_PERMISSION │ │ + [ 21973] U_AMBIGUOUS_ALIAS_WARNING │ │ + [ 2198d] U_INVALID_PROPERTY_PATTERN │ │ + [ 219a8] U_REGEX_MISSING_CLOSE_BRACKET │ │ + [ 219c6] U_STRINGPREP_PROHIBITED_ERROR │ │ + [ 219e4] SentenceBreak │ │ + [ 219f2] ANG │ │ + [ 219f6] BRZ │ │ + [ 219fa] EUR │ │ + [ 219fe] IDR │ │ + [ 21a02] PGK │ │ + [ 21a06] VED │ │ + [ 21a0a] YUN │ │ + [ 21a0e] percentFormat │ │ + [ 21a1c] Division impossible │ │ + [ 21a30] Division undefined │ │ + [ 21a43] -Normal │ │ + [ 21a4b] british-thermal-unit │ │ + [ 21a60] liter │ │ + [ 21a66] decimal │ │ + [ 21a6e] [:digit:] │ │ + [ 21a78] zetta │ │ + [ 21a7e] tera │ │ + [ 21a83] kibi │ │ + [ 21a88] gender │ │ + [ 21a8f] missing root elements data, tailoring not supported │ │ + [ 21ac3] reset primary-before ignorable not possible │ │ + [ 21aef] modifying collation elements │ │ + [ 21b0c] starred-relation string range contains a surrogate │ │ + [ 21b3f] backslash escape at the end of the rule string │ │ + [ 21b6e] not a valid setting/option │ │ + [ 21b89] last tertiary ignorable │ │ + [ 21ba1] ussystem │ │ + [ 21baa] special │ │ + [ 21bb2] ft_to_m │ │ + [ 21bba] ATrace_endAsyncSection │ │ + [ 21bd1] ()Landroid/view/Display; │ │ + [ 21bea] mAutoSwapInterval │ │ + [ 21bfd] │ │ + [ 21bff] Chase │ │ + [ 21c05] renderoverlay │ │ + [ 21c13] Failed to initialize renderer │ │ + [ 21c31] velocity vector │ │ + [ 21c41] C-{} │ │ + [ 21c46] width is not integer │ │ + [ 21c5b] FFVHEncoderOptions │ │ + [ 21c6e] TitleFont │ │ + [ 21c78] O │ │ + [ 21c7a] G │ │ + [ 21c7c] Y │ │ + [ 21c7e] " {\n │ │ + [ 21c84] time │ │ + [ 21c8c] Track %s\n │ │ + [ 21c96] ft/s │ │ + [ 21c9b] Abs (app) mag: {:.2f} ({:.2f})\n │ │ + [ 21cbb] WARNING │ │ + [ 21cc3] SSE2: %s\n │ │ + [ 21cd1] [%s]\n │ │ + [ 21cd7] Format: %s -> %s\n │ │ + [ 21cf2] CHANNEL_LFE │ │ + [ 21cfe] CHANNEL_AUX_25 │ │ + [ 21d0d] Timeout │ │ + [ 21d15] Socket operation on non-socket │ │ + [ 21d34] 8-bit Unsigned Integer │ │ + [ 21d4b] 32-bit Signed Integer │ │ + [ 21d61] Failed to post MA_JOB_TYPE_RESOURCE_MANAGER_FREE_DATA_BUFFER_NODE job. %s.\n │ │ + [ 21dad] fmt │ │ + [ 21db2] July │ │ + [ 21db7] limegreen │ │ + [ 21dc1] _ │ │ + [ 21dc3] locale │ │ + [ 21dca] EPS │ │ + [ 21dd1] horizontalgrid │ │ + [ 21de0] rupes │ │ + [ 21de6] setsurface │ │ + [ 21df1] clear │ │ + [ 21df7] visible │ │ + [ 21dff] Celx class expected │ │ + [ 21e13] setlayoutdirection │ │ + [ 21e26] getminfeaturesize │ │ + [ 21e38] ispaused │ │ + [ 21e41] dsos │ │ + [ 21e46] Values in table-argument to celestia:setlabelflags() must be boolean │ │ + [ 21e8b] Third argument to celestia:setconstellationcolor() must be a number │ │ + [ 21ecf] Argument to celestia:setminfeaturesize() must be a number │ │ + [ 21f09] Wrong number of arguments to function celestia:utctotdb │ │ + [ 21f41] Arguments to celestia:newposition must be either numbers or strings │ │ + [ 21f85] Two to six arguments expected to function celestia:play │ │ + [ 21fbd] First argument for celestia:play must be a number │ │ + [ 21fef] Function celestia:stopaudio requires one argument │ │ + [ 22021] First argument for celestia:setaudiopan must be a number │ │ + [ 2205a] Argument to celestia:getparamstring must be a string │ │ + [ 2208f] Invalid mipMapMode │ │ + [ 220a2] package │ │ + [ 220aa] button │ │ + [ 220b1] class_celscript │ │ + [ 220c1] POINTS │ │ + [ 220c8] POLYGON │ │ + [ 220d0] MODELVIEW │ │ + [ 220da] argument 3 to gl.Color must be a number │ │ + [ 22102] Two arguments expected for gl.BlendFunc() │ │ + [ 2212c] comet │ │ + [ 22132] gotoobject │ │ + [ 2213d] One argument required for setpos │ │ + [ 2215e] One argument expected for observer:synchronous │ │ + [ 2218d] One argument expected for observer:lock │ │ + [ 221b5] One argument expected for observer:track │ │ + [ 221de] One argument required for observer:setframe() │ │ + [ 2220c] No arguments expected for vector:normalize │ │ + [ 22237] ?.lua; │ │ + [ 2223e] Error: Unknown block type {} │ │ + [ 2225b] texcoord1 │ │ + [ 22265] callisto │ │ + [ 2226e] iau-neptune │ │ + [ 2227a] Could not read XYZV binary file {}.\n │ │ + [ 2229f] boundingRadius │ │ + [ 222ae] Failed to load module for ScriptedRotation: {}\n │ │ + [ 222de] galaxyTex │ │ + [ 222e8] tidalTex │ │ + [ 222f1] celestia-data │ │ + [ 222ff] Error parsing asterism "{}": expected array\n │ │ + [ 2232c] Dor │ │ + [ 22330] Lyn │ │ + [ 22334] Per │ │ + [ 22338] Tel │ │ + [ 2233c] qupeculavnctis minoris austrinise maeleonagittanajorisiopeiasoeniboologirsacadrpiucharicornoceromedangule berenicescopisum venaticorumba australes venaticis australisyxpenforoscopiculptoretertaurodisphindhemigaygborealiscinaelopardalisilalia │ │ + [ 2242e] RT │ │ + [ 22431] MO │ │ + [ 22434] FeatureHeight │ │ + [ 22442] Failed to read mesh header\n │ │ + [ 2245e] Bad syntax for primary axis of two-vector frame.\n │ │ + [ 22490] -x │ │ + [ 22493] Bad two-vector frame: no target specified for vector.\n │ │ + [ 224ca] textureOffset │ │ + [ 224d8] ringCenter │ │ + [ 224e3] diff.rgb += │ │ + [ 224f0] {0}.x = dot(T, {1});\n │ │ {0}.y = dot(-bitangent, {1});\n │ │ {0}.z = dot(N, {1});\n │ │ - [ 2250c] ).a * 0.75;\n │ │ - [ 22519] NormalizeMesh │ │ - [ 22527] Invalid filename in rings Texture\n │ │ - [ 2254a] Invalid filename in BumpMap\n │ │ - [ 22567] {}{}{} │ │ - [ 2256e] 1 │ │ - [ 22570] D │ │ - [ 22572] SpectralType │ │ - [ 2257f] Loading cross index failed\n │ │ - [ 2259b] Error writing PNG file '{}'\n │ │ - [ 225b8] Processing NamedObject chunk\n │ │ - [ 225d6] Processing BackgroundColor chunk\n │ │ - [ 225f8] Error occurred reading string\n │ │ - [ 22617] Content size {} too small to include point array count\n │ │ - [ 2264f] Processing MaterialDiffuse chunk\n │ │ - [ 22671] space/celestia/celestia/Star │ │ - [ 2268e] put │ │ - [ 22692] Planets │ │ - [ 2269a] discarded │ │ - [ 226a4] invalid UTF-8 byte at index │ │ - [ 226c1] incomplete UTF-8 string; last byte: 0x │ │ - [ 226e8] {} ({}) │ │ - [ 226f0] %s\n │ │ - [ 226f8] llx │ │ - [ 226fc] LC_ALL │ │ - [ 22703] nplurals= │ │ - [ 2270d] Improper call to JPEG library in state %d │ │ - [ 22737] Requested features are incompatible │ │ - [ 2275b] Unsupported JPEG process: SOF type 0x%02x │ │ - [ 22785] Invalid JPEG file structure: SOS before SOF │ │ - [ 227b1] JFIF extension marker: JPEG-compressed thumbnail image, length %u │ │ - [ 227f3] Corrupt JPEG data: bad arithmetic code │ │ - [ 2281a] %ld%c │ │ - [ 22820] FamilyName │ │ - [ 2282b] sfnts │ │ - [ 22831] 10646 │ │ - [ 22837] STARTPROPERTIES │ │ - [ 22847] RAW_ASCENT │ │ - [ 22852] _XFREE86_GLYPH_RANGES │ │ - [ 22868] ENDCHAR │ │ - [ 22870] 1.2.8 │ │ - [ 22876] IsBaseFont │ │ - [ 22881] MappingScheme │ │ - [ 2288f] [string " │ │ - [ 22899] abort │ │ - [ 2289f] _LOADED │ │ - [ 228a7] init │ │ - [ 228ac] flnSu │ │ - [ 228b2] ctype<%s> │ │ - [ 228bc] /* GNU ld script │ │ - [ 228cd] gamma value does not match libpng estimate │ │ - [ 228f8] profile ' │ │ - [ 22902] gray[8] color-map: too few entries │ │ - [ 22925] Call to NULL read function │ │ - [ 22940] output gamma out of expected range │ │ - [ 22963] conflicting calls to set alpha mode and background │ │ - [ 22996] extra compressed data │ │ - [ 229ac] sPLT chunk has bad length │ │ - [ 229c6] too many text chunks │ │ - [ 229db] png_set_keep_unknown_chunks: invalid keep │ │ - [ 22a05] ERRACT: An invalid value of ACTION was supplied. The value was: │ │ - [ 22a48] errch_c │ │ - [ 22a50] SPICE(EMBEDDEDBLANK) │ │ - [ 22a65] An Invalid Action Value Was Supplied │ │ - [ 22a8a] No Further Symbols Can be Inserted; the Name Table is Full │ │ - [ 22ac5] intstr_ │ │ - [ 22acd] Input file name <#> has length @ characters. The limit on the length of file names stored by FURNSH is @ characters. │ │ - [ 22b42] srces │ │ - [ 22b48] KCLEAR │ │ - [ 22b4f] sthan │ │ - [ 22b55] SPICE(CKTOOMANYFILES) │ │ - [ 22b6b] NEW INSTRUMENT │ │ - [ 22b7a] MAKE ROOM │ │ - [ 22b84] SPICE(DAFFTFULL) │ │ - [ 22b95] off end of record │ │ - [ 22ba7] INSRTI │ │ - [ 22bae] write start │ │ - [ 22bba] sthvnr │ │ - [ 22bc1] rbreq │ │ - [ 22bc7] DUPLICATE_COLUMN_NAMES │ │ - [ 22bde] stsidx │ │ - [ 22be5] ATTRIBUTE_TABLE_FULL │ │ - [ 22bfa] NUM_TABLES │ │ - [ 22c05] Row indices for query result range from 1 to #; requested row index was #. │ │ - [ 22c50] Column # has data type #. │ │ - [ 22c6a] SPICE(DASNOSUCHUNIT) │ │ - [ 22c7f] upbufd │ │ - [ 22c86] DASRRC │ │ - [ 22c8d] upbufc │ │ - [ 22c94] DASSDR │ │ - [ 22c9b] NWORDS was #; should be non-negative. │ │ - [ 22cc1] NODE was #; valid range is 1 to #. │ │ - [ 22ce4] (1X,A,D25.17,A) │ │ - [ 22cf4] An error occurred while │ │ - [ 22d0c] 0.0000000000000000000000000 │ │ - [ 22d29] ipower │ │ - [ 22d30] j2000 │ │ - [ 22d36] REMOVC │ │ - [ 22d3d] THREE │ │ - [ 22d43] Window size in type 05 segment was #; must be even for subtypes 1 and 3 (Lagrange, 4 or 7-element packets). │ │ - [ 22daf] LGRINT │ │ - [ 22db6] Input matrix was not a rotation. │ │ - [ 22dd7] SPICE(BADSUBSCRIPT): Subscript out of range on file line %ld, procedure "%s". Attempt to access element %ld of variable "%s".\n │ │ + [ 22539] ).a * 0.75;\n │ │ + [ 22546] NormalizeMesh │ │ + [ 22554] Invalid filename in rings Texture\n │ │ + [ 22577] Invalid filename in BumpMap\n │ │ + [ 22594] {}{}{} │ │ + [ 2259b] 1 │ │ + [ 2259d] D │ │ + [ 2259f] SpectralType │ │ + [ 225ac] Loading cross index failed\n │ │ + [ 225c8] Error writing PNG file '{}'\n │ │ + [ 225e5] Processing NamedObject chunk\n │ │ + [ 22603] Processing BackgroundColor chunk\n │ │ + [ 22625] Error occurred reading string\n │ │ + [ 22644] Content size {} too small to include point array count\n │ │ + [ 2267c] Processing MaterialDiffuse chunk\n │ │ + [ 2269e] space/celestia/celestia/Star │ │ + [ 226bb] put │ │ + [ 226bf] Planets │ │ + [ 226c7] discarded │ │ + [ 226d1] invalid UTF-8 byte at index │ │ + [ 226ee] incomplete UTF-8 string; last byte: 0x │ │ + [ 22715] {} ({}) │ │ + [ 2271d] %s\n │ │ + [ 22725] llx │ │ + [ 22729] LC_ALL │ │ + [ 22730] nplurals= │ │ + [ 2273a] Improper call to JPEG library in state %d │ │ + [ 22764] Requested features are incompatible │ │ + [ 22788] Unsupported JPEG process: SOF type 0x%02x │ │ + [ 227b2] Invalid JPEG file structure: SOS before SOF │ │ + [ 227de] JFIF extension marker: JPEG-compressed thumbnail image, length %u │ │ + [ 22820] Corrupt JPEG data: bad arithmetic code │ │ + [ 22847] %ld%c │ │ + [ 2284d] FamilyName │ │ + [ 22858] sfnts │ │ + [ 2285e] 10646 │ │ + [ 22864] STARTPROPERTIES │ │ + [ 22874] RAW_ASCENT │ │ + [ 2287f] _XFREE86_GLYPH_RANGES │ │ + [ 22895] ENDCHAR │ │ + [ 2289d] 1.2.8 │ │ + [ 228a3] IsBaseFont │ │ + [ 228ae] MappingScheme │ │ + [ 228bc] [string " │ │ + [ 228c6] abort │ │ + [ 228cc] _LOADED │ │ + [ 228d4] init │ │ + [ 228d9] flnSu │ │ + [ 228df] ctype<%s> │ │ + [ 228e9] /* GNU ld script │ │ + [ 228fa] gamma value does not match libpng estimate │ │ + [ 22925] profile ' │ │ + [ 2292f] gray[8] color-map: too few entries │ │ + [ 22952] Call to NULL read function │ │ + [ 2296d] output gamma out of expected range │ │ + [ 22990] conflicting calls to set alpha mode and background │ │ + [ 229c3] extra compressed data │ │ + [ 229d9] sPLT chunk has bad length │ │ + [ 229f3] too many text chunks │ │ + [ 22a08] png_set_keep_unknown_chunks: invalid keep │ │ + [ 22a32] ERRACT: An invalid value of ACTION was supplied. The value was: │ │ + [ 22a75] errch_c │ │ + [ 22a7d] SPICE(EMBEDDEDBLANK) │ │ + [ 22a92] An Invalid Action Value Was Supplied │ │ + [ 22ab7] No Further Symbols Can be Inserted; the Name Table is Full │ │ + [ 22af2] intstr_ │ │ + [ 22afa] Input file name <#> has length @ characters. The limit on the length of file names stored by FURNSH is @ characters. │ │ + [ 22b6f] srces │ │ + [ 22b75] KCLEAR │ │ + [ 22b7c] sthan │ │ + [ 22b82] SPICE(CKTOOMANYFILES) │ │ + [ 22b98] NEW INSTRUMENT │ │ + [ 22ba7] MAKE ROOM │ │ + [ 22bb1] SPICE(DAFFTFULL) │ │ + [ 22bc2] off end of record │ │ + [ 22bd4] INSRTI │ │ + [ 22bdb] write start │ │ + [ 22be7] sthvnr │ │ + [ 22bee] rbreq │ │ + [ 22bf4] DUPLICATE_COLUMN_NAMES │ │ + [ 22c0b] stsidx │ │ + [ 22c12] ATTRIBUTE_TABLE_FULL │ │ + [ 22c27] NUM_TABLES │ │ + [ 22c32] Row indices for query result range from 1 to #; requested row index was #. │ │ + [ 22c7d] Column # has data type #. │ │ + [ 22c97] SPICE(DASNOSUCHUNIT) │ │ + [ 22cac] upbufd │ │ + [ 22cb3] DASRRC │ │ + [ 22cba] upbufc │ │ + [ 22cc1] DASSDR │ │ + [ 22cc8] NWORDS was #; should be non-negative. │ │ + [ 22cee] NODE was #; valid range is 1 to #. │ │ + [ 22d11] (1X,A,D25.17,A) │ │ + [ 22d21] An error occurred while │ │ + [ 22d39] 0.0000000000000000000000000 │ │ + [ 22d56] ipower │ │ + [ 22d5d] j2000 │ │ + [ 22d63] REMOVC │ │ + [ 22d6a] THREE │ │ + [ 22d70] Window size in type 05 segment was #; must be even for subtypes 1 and 3 (Lagrange, 4 or 7-element packets). │ │ + [ 22ddc] LGRINT │ │ + [ 22de3] Input matrix was not a rotation. │ │ + [ 22e04] SPICE(BADSUBSCRIPT): Subscript out of range on file line %ld, procedure "%s". Attempt to access element %ld of variable "%s".\n │ │ SCARDI │ │ - [ 22e5e] SPKSFS │ │ - [ 22e65] spkgeo_c │ │ - [ 22e6e] extra │ │ - [ 22e74] SPKE15 │ │ - [ 22e7b] SPKE18 │ │ - [ 22e82] KEPLEQ │ │ - [ 22e89] SPICE(INSUFFICIENTANGLES) │ │ - [ 22ea3] bwcoef │ │ - [ 22eaa] PCKR03 │ │ - [ 22eb1] TRCNAM: An invalid index was input. The value was: │ │ - [ 22ee6] GPS │ │ - [ 22eea] <> │ │ - [ 22eed] vout │ │ - [ 22ef2] invalid number │ │ - [ 22f01] ZZBODINI │ │ - [ 22f0a] Insufficient room to copy the stored body name-code mappings to the output arguments. Space required is #, but the caller supplied #. │ │ - [ 22f91] ZZBODLST │ │ - [ 22f9a] Name to ID mappings. │ │ - [ 22faf] zzdafgdr_ │ │ - [ 22fb9] Attempt to write file '#' failed. Value of IOSTAT was #. The file has been deleted. │ │ - [ 2300d] The maximum number of units are locked to handles. As such, there is no room to open the requested scratch file. │ │ - [ 2307f] ftbff │ │ - [ 23085] # file $ is open for READ access. Attempt to close and delete file has failed. │ │ - [ 230d6] SPICE(FILENOTCONNECTED) │ │ - [ 230ee] ZZDSKBSR │ │ - [ 230f7] CONSTANT │ │ - [ 23100] Kernel variable # was expected to be present in the kernel pool but was not found. The alternative form of kernel variable name FRAME_#_# was not searched for because this name has excessive length (# characters vs allowed maximum of #). One of these variables is needed to define the parameterized dynamic frame #. Usually this type of problem is due to a missing keyword assignment in a frame kernel. Another, less likely, possibility is that other errors in a frame kernel have confused the frame subsystem into wrongly deciding these variables are needed. │ │ - [ 23334] Delta abscissa value is zero; a non-zero value is required. │ │ - [ 23370] orignl │ │ - [ 23377] Cross product table index for left hand side of constraint # was #; valid range is 1:# │ │ - [ 233ce] ZZEKQORD │ │ - [ 233d7] NAMES_RESOLVED │ │ - [ 233e6] ZZEKRCMP │ │ - [ 233ef] The data type code # was not recognized. │ │ - [ 23418] Item # not found. │ │ - [ 2342a] SPICE(INVALIDNAME) │ │ - [ 2343d] Segment number = #; valid range is 1:#. │ │ - [ 23465] ZZEKVADR │ │ - [ 2346e] SPICE(BADADDRESS) │ │ - [ 23480] Data type mismatch for order-by column having index #; type for segment # = #; type for segment # is # │ │ - [ 234e7] C2F_CreateStrArr_Sig │ │ - [ 234fc] IAU_VENUS │ │ - [ 23506] IAU_URANUS │ │ - [ 23511] IAU_NEPTUNE │ │ - [ 2351d] IAU_TITAN │ │ - [ 23527] IAU_BIANCA │ │ - [ 23532] IAU_QUETA │ │ - [ 2353c] MARS BARYCENTER │ │ - [ 2354c] MIMAS │ │ - [ 23552] HYPERION │ │ - [ 2355b] PANDORA │ │ - [ 23563] FENRIR │ │ - [ 2356a] SURTUR │ │ - [ 23571] PLC │ │ - [ 23575] PLANET-C │ │ - [ 2357e] BEAGLE2 │ │ - [ 23586] GENESIS │ │ - [ 2358e] TGO │ │ - [ 23592] MUSES-B │ │ - [ 2359a] NISAR │ │ - [ 235a0] LICIACUBE │ │ - [ 235aa] SELENE VRAD Satellite │ │ - [ 235c0] SHOEMAKER-LEVY 9-Q1 │ │ - [ 235d4] BUS │ │ - [ 235d8] 67P/CHURYUMOV-GERASIMENKO (1969 R1) │ │ - [ 235fc] COMAS SOLA │ │ - [ 23607] TSUCHINSHAN 1 │ │ - [ 23615] VAN BIESBROECK │ │ - [ 23624] ORUS │ │ - [ 23629] Failure to find required CK data could be due to one or more CK files not having been loaded, or to the epoch shown above lying within a coverage gap or beyond the coverage bounds of the loaded CK files. It is also possible that no loaded CK file has required angular velocity data for the input epoch, even if a loaded CK does have attitude data for that epoch. You can use CKBRIEF with the -dump option to display coverage intervals of a CK file. │ │ - [ 237ea] SPICE(CALLEDOUTOFORDER) │ │ - [ 23802] lt │ │ - [ 23805] Z │ │ - [ 23807] _# │ │ - [ 2380a] Item # has size # but output array has size #. │ │ - [ 23839] TDB │ │ - [ 2383e] TDT │ │ - [ 23843] YWD │ │ - [ 23848] ZZSPKLT0 │ │ - [ 23851] basbeg │ │ - [ 23858] SPICE(BADDEFAULTVALUE) │ │ - [ 2386f] substring │ │ - [ 23879] MONDAY │ │ - [ 23880] The year associated with the calendar string "#" could not be identified. │ │ - [ 238cb] Yy*H*M │ │ - [ 238d2] Ymii:i │ │ - [ 238d9] y*Y*H*M │ │ - [ 238e1] iidi:i:n │ │ - [ 238ea] iimiin │ │ - [ 238f1] i-itn │ │ - [ 238f7] i:ni/i/i │ │ - [ 23900] i:ni-i-Y │ │ - [ 23909] Y-itnx │ │ - [ 23910] Aberration correction specification # calls for relativistic corrections, which are not supported. │ │ - [ 23973] RS │ │ - [ 23976] YE │ │ - [ 23979] as │ │ - [ 2397c] asa │ │ - [ 23980] awa │ │ - [ 23984] bal │ │ - [ 23988] bi │ │ - [ 2398b] den │ │ - [ 2398f] eu │ │ - [ 23992] gez │ │ - [ 23996] kxv │ │ - [ 2399a] mua │ │ - [ 2399e] om │ │ - [ 239a1] osa │ │ - [ 239a5] sa │ │ - [ 239a8] shi │ │ - [ 239ac] tk │ │ - [ 239af] tlh │ │ - [ 239b3] uz │ │ - [ 239b6] wae │ │ - [ 239ba] aar │ │ - [ 239be] bos │ │ - [ 239c2] fij │ │ - [ 239c6] jav │ │ - [ 239ca] ltz │ │ - [ 239ce] nya │ │ - [ 239d2] oss │ │ - [ 239d6] tir │ │ - [ 239da] tsn │ │ - [ 239de] FI │ │ - [ 239e1] GT │ │ - [ 239e4] KR │ │ - [ 239e7] BHR │ │ - [ 239eb] BLM │ │ - [ 239ef] BHS │ │ - [ 239f3] DMA │ │ - [ 239f7] LAO │ │ - [ 239fb] LUX │ │ - [ 239ff] MDA │ │ - [ 23a03] MTQ │ │ - [ 23a07] SRB │ │ - [ 23a0b] SYC │ │ - [ 23a0f] TUR │ │ - [ 23a13] VAT │ │ - [ 23a17] am_ET │ │ - [ 23a1d] Asia/Sakhalin │ │ - [ 23a2b] Asia/Vladivostok │ │ - [ 23a3c] Asia/Yerevan │ │ - [ 23a49] MSD │ │ - [ 23a4d] Africa/Algiers │ │ - [ 23a5c] Europe/London │ │ - [ 23a6a] ar_DZ │ │ - [ 23a70] es_AR │ │ - [ 23a76] fr_CD │ │ - [ 23a7c] mn_Mong_CN │ │ - [ 23a87] sgn-ch-de │ │ - [ 23a91] zh-hakka │ │ - [ 23a9a] sgn-de │ │ - [ 23aa1] nb nn │ │ - [ 23aa7] zoneinfo64 │ │ - [ 23ab2] hebr │ │ - [ 23ab7] month-format-except-narrow │ │ - [ 23ad2] zone-long │ │ - [ 23adc] ethiopic-amete-alem │ │ - [ 23af0] M01 │ │ - [ 23af4] characters │ │ - [ 23aff] Names │ │ - [ 23b05] standard │ │ - [ 23b0e] ubrk_swap(): RBBI Data header is invalid.\n │ │ - [ 23b39] out of memory swapping %u unames.icu tokens\n │ │ - [ 23b66] U_BAD_VARIABLE_DEFINITION │ │ - [ 23b80] U_DECIMAL_NUMBER_SYNTAX_ERROR │ │ - [ 23b9e] U_BRK_HEX_DIGITS_EXPECTED │ │ - [ 23bb8] U_STRINGPREP_UNASSIGNED_ERROR │ │ - [ 23bd6] U_IDNA_ZERO_LENGTH_LABEL_ERROR │ │ - [ 23bf5] BYB │ │ - [ 23bf9] CHF │ │ - [ 23bfd] CUC │ │ - [ 23c01] HKD │ │ - [ 23c05] MXV │ │ - [ 23c09] XAF │ │ - [ 23c0d] XPT │ │ - [ 23c11] NaN │ │ - [ 23c15] light │ │ - [ 23c1b] megabyte │ │ - [ 23c24] kilocalorie │ │ - [ 23c30] parsec │ │ - [ 23c37] solar-mass │ │ - [ 23c42] millibar │ │ - [ 23c4b] pow15- │ │ - [ 23c52] deci │ │ - [ 23c57] weekOfMonth │ │ - [ 23c63] colReorder │ │ - [ 23c6e] normalizing the reset position │ │ - [ 23c8d] item_per_mole │ │ - [ 23c9b] virtual void swappy::ChoreographerThread::postFrameCallbacks() │ │ - [ 23cda] (Ljava/lang/String;Ljava/lang/ClassLoader;)V │ │ - [ 23d07] SwappyDisplayManager │ │ - [ 23d1c] getPresentationDeadlineNanos │ │ - [ 23d39] keydown │ │ - [ 23d41] Star style: fuzzy points │ │ - [ 23d5a] ~/.celestia/celestia.cfg │ │ - [ 23d73] Invalid URL │ │ - [ 23d7f] spin vector │ │ - [ 23d8b] terminator │ │ - [ 23d96] LayoutDirection │ │ - [ 23da6] parentFolder │ │ - [ 23db4] offset [ │ │ - [ 23dbe] Real time │ │ - [ 23dc8] {} �C │ │ - [ 23dcf] Default Capture Device │ │ - [ 23de6] LE │ │ - [ 23de9] Interrupted │ │ - [ 23df5] Bad address │ │ - [ 23e01] Invalid message │ │ - [ 23e11] Not connected │ │ - [ 23e1f] Invalid device config │ │ - [ 23e35] 0.6.38 │ │ - [ 23e3c] OpenSL|ES │ │ - [ 23e46] AAudioStreamBuilder_setDirection │ │ - [ 23e67] ??? │ │ - [ 23e6b] Loading character {:x} failed!\n │ │ - [ 23e8b] antiquewhite │ │ - [ 23e98] linen │ │ - [ 23e9e] mediumspringgreen │ │ - [ 23eb0] tomato │ │ - [ 23eb7] .xyz │ │ - [ 23ebf] ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/ │ │ - [ 23f00] arcus │ │ - [ 23f06] Selection │ │ - [ 23f10] spacecraftorbits │ │ - [ 23f21] texture │ │ - [ 23f29] color │ │ - [ 23f2f] Unknown {} flag: {}\n │ │ - [ 23f44] bottom │ │ - [ 23f4b] left │ │ - [ 23f50] fitscreen │ │ - [ 23f5a] setminorbitsize │ │ - [ 23f6a] geturl │ │ - [ 23f71] Keys in table-argument to celestia:setoverlayelements() must be strings │ │ - [ 23fb9] One argument expected to function celestia:mark │ │ - [ 23fe9] First arg to celestia:getdso must be a number │ │ - [ 24017] newframe: two objects required for lock frame │ │ - [ 24045] First argument for celestia:registereventhandler must be a string │ │ - [ 24087] Third argument to celestia:play must be a number (pan) │ │ - [ 240be] default │ │ - [ 240c6] celestia_keyboard_callback │ │ - [ 240e1] dt │ │ - [ 240e4] argument 6 to gl.Frustum must be a number │ │ - [ 2410e] argument 5 to gl.Ortho must be a number │ │ - [ 24136] phases │ │ - [ 2413d] Expected no or one argument to object:getposition │ │ - [ 2416f] No argument expected for observer:makeactiveview() │ │ - [ 241a2] addvector │ │ - [ 241ac] [Rotation] │ │ - [ 241b7] Script coroutine initialization failed │ │ - [ 241de] sprites │ │ - [ 241e6] Vertex position must be a float3\n │ │ - [ 24208] venus-jpl │ │ - [ 24212] rhea │ │ - [ 24217] iau-pan │ │ - [ 2421f] Couldn't find SPICE ID for {}\n │ │ - [ 2423e] Cen │ │ - [ 24242] Eri │ │ - [ 24246] Hor │ │ - [ 2424a] Mic │ │ - [ 2424e] Globular │ │ - [ 24257] models/Sb.png │ │ - [ 24265] GL_OES_texture_border_clamp │ │ - [ 24281] Mesa │ │ - [ 24286] Error compiling geometry shader:\n │ │ - [ 242a8] MA │ │ - [ 242ab] VA │ │ - [ 242ae] LC │ │ - [ 242b1] Skipping mesh with 0 primitive groups!\n │ │ - [ 242d9] Mesh index {} is higher than VBO count {}! │ │ - [ 24304] Object has incorrect FixedPosition syntax.\n │ │ - [ 24330] BoundingRadius │ │ - [ 2433f] SemiMajorAxis │ │ - [ 2434d] LongOfPericenter │ │ - [ 2435e] BaseFrame │ │ - [ 24368] {:.2f} │ │ - [ 2436f] Loading rotation model: {}\n │ │ - [ 2438b] shaders │ │ - [ 24393] {}_frag.glsl │ │ - [ 243a0] ***************************************************/\n │ │ - [ 243d6] cosNormalLightDir = dot(in_Normal, │ │ - [ 243fa] * max(0.0, t / dot( │ │ - [ 2440f] shadowTexGenT │ │ - [ 2441d] cloudShadowTex │ │ - [ 2442c] NL = max(0.0, NL);\n │ │ - [ 24440] .z * 8.0, 0.0, 1.0);\n │ │ - [ 24456] l = max(0.0, dot( │ │ - [ 24468] halfVector │ │ - [ 24473] = dot(position, │ │ - [ 24485] atmosphereRadius │ │ - [ 24496] attribute {} {};\n │ │ - [ 244a9] vec4 calc_vp(vec4 in_Position)\n │ │ + [ 22e8b] SPKSFS │ │ + [ 22e92] spkgeo_c │ │ + [ 22e9b] extra │ │ + [ 22ea1] SPKE15 │ │ + [ 22ea8] SPKE18 │ │ + [ 22eaf] KEPLEQ │ │ + [ 22eb6] SPICE(INSUFFICIENTANGLES) │ │ + [ 22ed0] bwcoef │ │ + [ 22ed7] PCKR03 │ │ + [ 22ede] TRCNAM: An invalid index was input. The value was: │ │ + [ 22f13] GPS │ │ + [ 22f17] <> │ │ + [ 22f1a] vout │ │ + [ 22f1f] invalid number │ │ + [ 22f2e] ZZBODINI │ │ + [ 22f37] Insufficient room to copy the stored body name-code mappings to the output arguments. Space required is #, but the caller supplied #. │ │ + [ 22fbe] ZZBODLST │ │ + [ 22fc7] Name to ID mappings. │ │ + [ 22fdc] zzdafgdr_ │ │ + [ 22fe6] Attempt to write file '#' failed. Value of IOSTAT was #. The file has been deleted. │ │ + [ 2303a] The maximum number of units are locked to handles. As such, there is no room to open the requested scratch file. │ │ + [ 230ac] ftbff │ │ + [ 230b2] # file $ is open for READ access. Attempt to close and delete file has failed. │ │ + [ 23103] SPICE(FILENOTCONNECTED) │ │ + [ 2311b] ZZDSKBSR │ │ + [ 23124] CONSTANT │ │ + [ 2312d] Kernel variable # was expected to be present in the kernel pool but was not found. The alternative form of kernel variable name FRAME_#_# was not searched for because this name has excessive length (# characters vs allowed maximum of #). One of these variables is needed to define the parameterized dynamic frame #. Usually this type of problem is due to a missing keyword assignment in a frame kernel. Another, less likely, possibility is that other errors in a frame kernel have confused the frame subsystem into wrongly deciding these variables are needed. │ │ + [ 23361] Delta abscissa value is zero; a non-zero value is required. │ │ + [ 2339d] orignl │ │ + [ 233a4] Cross product table index for left hand side of constraint # was #; valid range is 1:# │ │ + [ 233fb] ZZEKQORD │ │ + [ 23404] NAMES_RESOLVED │ │ + [ 23413] ZZEKRCMP │ │ + [ 2341c] The data type code # was not recognized. │ │ + [ 23445] Item # not found. │ │ + [ 23457] SPICE(INVALIDNAME) │ │ + [ 2346a] Segment number = #; valid range is 1:#. │ │ + [ 23492] ZZEKVADR │ │ + [ 2349b] SPICE(BADADDRESS) │ │ + [ 234ad] Data type mismatch for order-by column having index #; type for segment # = #; type for segment # is # │ │ + [ 23514] C2F_CreateStrArr_Sig │ │ + [ 23529] IAU_VENUS │ │ + [ 23533] IAU_URANUS │ │ + [ 2353e] IAU_NEPTUNE │ │ + [ 2354a] IAU_TITAN │ │ + [ 23554] IAU_BIANCA │ │ + [ 2355f] IAU_QUETA │ │ + [ 23569] MARS BARYCENTER │ │ + [ 23579] MIMAS │ │ + [ 2357f] HYPERION │ │ + [ 23588] PANDORA │ │ + [ 23590] FENRIR │ │ + [ 23597] SURTUR │ │ + [ 2359e] PLC │ │ + [ 235a2] PLANET-C │ │ + [ 235ab] BEAGLE2 │ │ + [ 235b3] GENESIS │ │ + [ 235bb] TGO │ │ + [ 235bf] MUSES-B │ │ + [ 235c7] NISAR │ │ + [ 235cd] LICIACUBE │ │ + [ 235d7] SELENE VRAD Satellite │ │ + [ 235ed] SHOEMAKER-LEVY 9-Q1 │ │ + [ 23601] BUS │ │ + [ 23605] 67P/CHURYUMOV-GERASIMENKO (1969 R1) │ │ + [ 23629] COMAS SOLA │ │ + [ 23634] TSUCHINSHAN 1 │ │ + [ 23642] VAN BIESBROECK │ │ + [ 23651] ORUS │ │ + [ 23656] Failure to find required CK data could be due to one or more CK files not having been loaded, or to the epoch shown above lying within a coverage gap or beyond the coverage bounds of the loaded CK files. It is also possible that no loaded CK file has required angular velocity data for the input epoch, even if a loaded CK does have attitude data for that epoch. You can use CKBRIEF with the -dump option to display coverage intervals of a CK file. │ │ + [ 23817] SPICE(CALLEDOUTOFORDER) │ │ + [ 2382f] lt │ │ + [ 23832] Z │ │ + [ 23834] _# │ │ + [ 23837] Item # has size # but output array has size #. │ │ + [ 23866] TDB │ │ + [ 2386b] TDT │ │ + [ 23870] YWD │ │ + [ 23875] ZZSPKLT0 │ │ + [ 2387e] basbeg │ │ + [ 23885] SPICE(BADDEFAULTVALUE) │ │ + [ 2389c] substring │ │ + [ 238a6] MONDAY │ │ + [ 238ad] The year associated with the calendar string "#" could not be identified. │ │ + [ 238f8] Yy*H*M │ │ + [ 238ff] Ymii:i │ │ + [ 23906] y*Y*H*M │ │ + [ 2390e] iidi:i:n │ │ + [ 23917] iimiin │ │ + [ 2391e] i-itn │ │ + [ 23924] i:ni/i/i │ │ + [ 2392d] i:ni-i-Y │ │ + [ 23936] Y-itnx │ │ + [ 2393d] Aberration correction specification # calls for relativistic corrections, which are not supported. │ │ + [ 239a0] RS │ │ + [ 239a3] YE │ │ + [ 239a6] as │ │ + [ 239a9] asa │ │ + [ 239ad] awa │ │ + [ 239b1] bal │ │ + [ 239b5] bi │ │ + [ 239b8] den │ │ + [ 239bc] eu │ │ + [ 239bf] gez │ │ + [ 239c3] kxv │ │ + [ 239c7] mua │ │ + [ 239cb] om │ │ + [ 239ce] osa │ │ + [ 239d2] sa │ │ + [ 239d5] shi │ │ + [ 239d9] tk │ │ + [ 239dc] tlh │ │ + [ 239e0] uz │ │ + [ 239e3] wae │ │ + [ 239e7] aar │ │ + [ 239eb] bos │ │ + [ 239ef] fij │ │ + [ 239f3] jav │ │ + [ 239f7] ltz │ │ + [ 239fb] nya │ │ + [ 239ff] oss │ │ + [ 23a03] tir │ │ + [ 23a07] tsn │ │ + [ 23a0b] FI │ │ + [ 23a0e] GT │ │ + [ 23a11] KR │ │ + [ 23a14] BHR │ │ + [ 23a18] BLM │ │ + [ 23a1c] BHS │ │ + [ 23a20] DMA │ │ + [ 23a24] LAO │ │ + [ 23a28] LUX │ │ + [ 23a2c] MDA │ │ + [ 23a30] MTQ │ │ + [ 23a34] SRB │ │ + [ 23a38] SYC │ │ + [ 23a3c] TUR │ │ + [ 23a40] VAT │ │ + [ 23a44] am_ET │ │ + [ 23a4a] Asia/Sakhalin │ │ + [ 23a58] Asia/Vladivostok │ │ + [ 23a69] Asia/Yerevan │ │ + [ 23a76] MSD │ │ + [ 23a7a] Africa/Algiers │ │ + [ 23a89] Europe/London │ │ + [ 23a97] ar_DZ │ │ + [ 23a9d] es_AR │ │ + [ 23aa3] fr_CD │ │ + [ 23aa9] mn_Mong_CN │ │ + [ 23ab4] sgn-ch-de │ │ + [ 23abe] zh-hakka │ │ + [ 23ac7] sgn-de │ │ + [ 23ace] nb nn │ │ + [ 23ad4] zoneinfo64 │ │ + [ 23adf] hebr │ │ + [ 23ae4] month-format-except-narrow │ │ + [ 23aff] zone-long │ │ + [ 23b09] ethiopic-amete-alem │ │ + [ 23b1d] M01 │ │ + [ 23b21] characters │ │ + [ 23b2c] Names │ │ + [ 23b32] standard │ │ + [ 23b3b] ubrk_swap(): RBBI Data header is invalid.\n │ │ + [ 23b66] out of memory swapping %u unames.icu tokens\n │ │ + [ 23b93] U_BAD_VARIABLE_DEFINITION │ │ + [ 23bad] U_DECIMAL_NUMBER_SYNTAX_ERROR │ │ + [ 23bcb] U_BRK_HEX_DIGITS_EXPECTED │ │ + [ 23be5] U_STRINGPREP_UNASSIGNED_ERROR │ │ + [ 23c03] U_IDNA_ZERO_LENGTH_LABEL_ERROR │ │ + [ 23c22] BYB │ │ + [ 23c26] CHF │ │ + [ 23c2a] CUC │ │ + [ 23c2e] HKD │ │ + [ 23c32] MXV │ │ + [ 23c36] XAF │ │ + [ 23c3a] XPT │ │ + [ 23c3e] NaN │ │ + [ 23c42] light │ │ + [ 23c48] megabyte │ │ + [ 23c51] kilocalorie │ │ + [ 23c5d] parsec │ │ + [ 23c64] solar-mass │ │ + [ 23c6f] millibar │ │ + [ 23c78] pow15- │ │ + [ 23c7f] deci │ │ + [ 23c84] weekOfMonth │ │ + [ 23c90] colReorder │ │ + [ 23c9b] normalizing the reset position │ │ + [ 23cba] item_per_mole │ │ + [ 23cc8] virtual void swappy::ChoreographerThread::postFrameCallbacks() │ │ + [ 23d07] (Ljava/lang/String;Ljava/lang/ClassLoader;)V │ │ + [ 23d34] SwappyDisplayManager │ │ + [ 23d49] getPresentationDeadlineNanos │ │ + [ 23d66] keydown │ │ + [ 23d6e] Star style: fuzzy points │ │ + [ 23d87] ~/.celestia/celestia.cfg │ │ + [ 23da0] Invalid URL │ │ + [ 23dac] spin vector │ │ + [ 23db8] terminator │ │ + [ 23dc3] LayoutDirection │ │ + [ 23dd3] parentFolder │ │ + [ 23de1] offset [ │ │ + [ 23deb] Real time │ │ + [ 23df5] {} �C │ │ + [ 23dfc] Default Capture Device │ │ + [ 23e13] LE │ │ + [ 23e16] Interrupted │ │ + [ 23e22] Bad address │ │ + [ 23e2e] Invalid message │ │ + [ 23e3e] Not connected │ │ + [ 23e4c] Invalid device config │ │ + [ 23e62] 0.6.38 │ │ + [ 23e69] OpenSL|ES │ │ + [ 23e73] AAudioStreamBuilder_setDirection │ │ + [ 23e94] ??? │ │ + [ 23e98] Loading character {:x} failed!\n │ │ + [ 23eb8] antiquewhite │ │ + [ 23ec5] linen │ │ + [ 23ecb] mediumspringgreen │ │ + [ 23edd] tomato │ │ + [ 23ee4] .xyz │ │ + [ 23eec] ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/ │ │ + [ 23f2d] arcus │ │ + [ 23f33] Selection │ │ + [ 23f3d] spacecraftorbits │ │ + [ 23f4e] texture │ │ + [ 23f56] color │ │ + [ 23f5c] Unknown {} flag: {}\n │ │ + [ 23f71] bottom │ │ + [ 23f78] left │ │ + [ 23f7d] fitscreen │ │ + [ 23f87] setminorbitsize │ │ + [ 23f97] geturl │ │ + [ 23f9e] Keys in table-argument to celestia:setoverlayelements() must be strings │ │ + [ 23fe6] One argument expected to function celestia:mark │ │ + [ 24016] First arg to celestia:getdso must be a number │ │ + [ 24044] newframe: two objects required for lock frame │ │ + [ 24072] First argument for celestia:registereventhandler must be a string │ │ + [ 240b4] Third argument to celestia:play must be a number (pan) │ │ + [ 240eb] default │ │ + [ 240f3] celestia_keyboard_callback │ │ + [ 2410e] dt │ │ + [ 24111] argument 6 to gl.Frustum must be a number │ │ + [ 2413b] argument 5 to gl.Ortho must be a number │ │ + [ 24163] phases │ │ + [ 2416a] Expected no or one argument to object:getposition │ │ + [ 2419c] No argument expected for observer:makeactiveview() │ │ + [ 241cf] addvector │ │ + [ 241d9] [Rotation] │ │ + [ 241e4] Script coroutine initialization failed │ │ + [ 2420b] sprites │ │ + [ 24213] Vertex position must be a float3\n │ │ + [ 24235] venus-jpl │ │ + [ 2423f] rhea │ │ + [ 24244] iau-pan │ │ + [ 2424c] Couldn't find SPICE ID for {}\n │ │ + [ 2426b] Cen │ │ + [ 2426f] Eri │ │ + [ 24273] Hor │ │ + [ 24277] Mic │ │ + [ 2427b] Globular │ │ + [ 24284] models/Sb.png │ │ + [ 24292] GL_OES_texture_border_clamp │ │ + [ 242ae] Mesa │ │ + [ 242b3] Error compiling geometry shader:\n │ │ + [ 242d5] MA │ │ + [ 242d8] VA │ │ + [ 242db] LC │ │ + [ 242de] Skipping mesh with 0 primitive groups!\n │ │ + [ 24306] Mesh index {} is higher than VBO count {}! │ │ + [ 24331] Object has incorrect FixedPosition syntax.\n │ │ + [ 2435d] BoundingRadius │ │ + [ 2436c] SemiMajorAxis │ │ + [ 2437a] LongOfPericenter │ │ + [ 2438b] BaseFrame │ │ + [ 24395] {:.2f} │ │ + [ 2439c] Loading rotation model: {}\n │ │ + [ 243b8] shaders │ │ + [ 243c0] {}_frag.glsl │ │ + [ 243cd] ***************************************************/\n │ │ + [ 24403] cosNormalLightDir = dot(in_Normal, │ │ + [ 24427] * max(0.0, t / dot( │ │ + [ 2443c] shadowTexGenT │ │ + [ 2444a] cloudShadowTex │ │ + [ 24459] NL = max(0.0, NL);\n │ │ + [ 2446d] .z * 8.0, 0.0, 1.0);\n │ │ + [ 24483] l = max(0.0, dot( │ │ + [ 24495] halfVector │ │ + [ 244a0] = dot(position, │ │ + [ 244b2] atmosphereRadius │ │ + [ 244c3] attribute {} {};\n │ │ + [ 244d6] vec4 calc_vp(vec4 in_Position)\n │ │ {\n │ │ return MVPMatrix * in_Position;\n │ │ }\n │ │ void set_vp(vec4 in_Position)\n │ │ {\n │ │ gl_Position = calc_vp(in_Position);\n │ │ }\n │ │ - [ 2453b] vec3 atmSamplePointSun = mix(atmEnter, atmLeave, 0.5);\n │ │ - [ 24577] Modify │ │ - [ 2457e] Error in .ssc file (line {}): {}\n │ │ - [ 245a0] Incorrect BondAlbedo value: {}\n │ │ - [ 245c0] OrbitBarycenter │ │ - [ 245d0] ignoring stellar coordinates in favor of OrbitBarycenter │ │ - [ 24609] Error in .stc file ({}): {}\n │ │ - [ 24626] DDS Format: {}\n │ │ - [ 24636] Read3DSFile: Wrong magic number in header\n │ │ - [ 24661] Processing MaterialName chunk\n │ │ - [ 24680] Unknown percentage {}\n │ │ - [ 24697] en │ │ - [ 2469a] null} │ │ - [ 246a0] Renderer │ │ - [ 246a9] No provider of %s found. Requires one of:\n │ │ - [ 246d5] jx │ │ - [ 246d8] Huffman code size table overflow │ │ - [ 246f9] Failed to create temporary file %s │ │ - [ 2471c] Unknown APP0 marker (not JFIF), length %u │ │ - [ 24746] Obtained EMS handle %u │ │ - [ 2475d] Corrupt JPEG data: found marker 0x%02x instead of RST%d │ │ - [ 24795] Invalid SOS parameters for sequential JPEG │ │ - [ 247c0] Application transferred too many scanlines │ │ - [ 247eb] font-format │ │ - [ 247f7] truetype │ │ - [ 24800] no-stem-darkening │ │ - [ 24812] FontType │ │ - [ 2481b] CIDFontName │ │ - [ 24827] Type 42 │ │ - [ 2482f] SUBSCRIPT_X │ │ - [ 2483b] _MULE_RELATIVE_COMPOSE │ │ - [ 24855] � � │ │ - [ 24861] � � │ │ - [ 2486a] EncodingScheme │ │ - [ 24879] EndKernPairs │ │ - [ 24886] cdata │ │ - [ 2488c] break │ │ - [ 24892] enum │ │ - [ 24897] too many upvalues │ │ - [ 248a9] LUA_PATH │ │ - [ 248b2] error loading module '%s' from file '%s':\n │ │ + [ 24568] vec3 atmSamplePointSun = mix(atmEnter, atmLeave, 0.5);\n │ │ + [ 245a4] Modify │ │ + [ 245ab] Error in .ssc file (line {}): {}\n │ │ + [ 245cd] Incorrect BondAlbedo value: {}\n │ │ + [ 245ed] OrbitBarycenter │ │ + [ 245fd] ignoring stellar coordinates in favor of OrbitBarycenter │ │ + [ 24636] Error in .stc file ({}): {}\n │ │ + [ 24653] DDS Format: {}\n │ │ + [ 24663] Read3DSFile: Wrong magic number in header\n │ │ + [ 2468e] Processing MaterialName chunk\n │ │ + [ 246ad] Unknown percentage {}\n │ │ + [ 246c4] en │ │ + [ 246c7] null} │ │ + [ 246cd] Renderer │ │ + [ 246d6] No provider of %s found. Requires one of:\n │ │ + [ 24702] jx │ │ + [ 24705] Huffman code size table overflow │ │ + [ 24726] Failed to create temporary file %s │ │ + [ 24749] Unknown APP0 marker (not JFIF), length %u │ │ + [ 24773] Obtained EMS handle %u │ │ + [ 2478a] Corrupt JPEG data: found marker 0x%02x instead of RST%d │ │ + [ 247c2] Invalid SOS parameters for sequential JPEG │ │ + [ 247ed] Application transferred too many scanlines │ │ + [ 24818] font-format │ │ + [ 24824] truetype │ │ + [ 2482d] no-stem-darkening │ │ + [ 2483f] FontType │ │ + [ 24848] CIDFontName │ │ + [ 24854] Type 42 │ │ + [ 2485c] SUBSCRIPT_X │ │ + [ 24868] _MULE_RELATIVE_COMPOSE │ │ + [ 24882] � � │ │ + [ 2488e] � � │ │ + [ 24897] EncodingScheme │ │ + [ 248a6] EndKernPairs │ │ + [ 248b3] cdata │ │ + [ 248b9] break │ │ + [ 248bf] enum │ │ + [ 248c4] too many upvalues │ │ + [ 248d6] LUA_PATH │ │ + [ 248df] error loading module '%s' from file '%s':\n │ │ %s │ │ - [ 248e0] C type │ │ - [ 248e7] string/number/__tostring │ │ - [ 24900] but running with │ │ - [ 24913] truncated │ │ - [ 2491d] unexpected 8-bit transformation │ │ - [ 2493d] CRC error │ │ - [ 24947] cHRM Red X │ │ - [ 24952] Memory allocation failed while processing sCAL │ │ - [ 24981] Z_OK on Z_FINISH with output space │ │ - [ 249a4] Can't write sCAL (buffer too small) │ │ - [ 249c8] option │ │ - [ 249cf] PATH_VALUES │ │ - [ 249db] ftnum │ │ - [ 249e1] itexp │ │ - [ 249e7] SPICE(BLANKFILETYPE) │ │ - [ 249fc] UNFORMATTED │ │ - [ 24a08] can't backspace file │ │ - [ 24a1d] bad namelist name │ │ - [ 24a2f] substring out of bounds │ │ - [ 24a47] unformatted │ │ - [ 24a53] FIND_TABLE │ │ - [ 24a5e] SPICE(COLDESCTABLEFULL) │ │ - [ 24a76] The EK file # could not be loaded; the column # in already loaded table # is not present in segment # in the EK file. │ │ - [ 24aec] SPICE(TABLENOTLOADED) │ │ - [ 24b02] seltab │ │ - [ 24b09] EKNELT │ │ - [ 24b10] rowvec │ │ - [ 24b17] prev │ │ - [ 24b1c] SPICE(UNRECOGNIZEDACTION) │ │ - [ 24b36] rngloc │ │ - [ 24b3d] DASCLS │ │ - [ 24b44] DASLLA │ │ - [ 24b4b] There is no room available for adding another numeric value to the kernel pool. │ │ - [ 24b9b] do_fio │ │ - [ 24ba2] E- │ │ - [ 24ba5] Could not read from #. │ │ - [ 24bbc] resvd │ │ - [ 24bc2] FIVE │ │ - [ 24bc7] IRFNAM │ │ - [ 24bce] CONVRT: Incompatible units. You are attempting to convert │ │ - [ 24c09] CKFROT │ │ - [ 24c10] SPICE(WRONGCKTYPE) │ │ - [ 24c23] CKR03 │ │ - [ 24c29] SCTYPE │ │ - [ 24c30] A traceback follows. The name of the highest level module is first. │ │ - [ 24c75] SIZEI │ │ - [ 24c7b] character │ │ - [ 24c85] The reference frame # has class #. This form of reference frame is not supported in version # of FRMGET. You need to update your version of SPICELIB to the latest version in order to support this frame. │ │ - [ 24d51] mxvg_ │ │ - [ 24d57] Storage for # double precision numbers is needed for an SPK data record and only # locations were available. Update the parameter MAXREC in the subroutine SPKPVN and notify the NAIF group of this problem. │ │ - [ 24e24] The semi-latus rectum supplied to the SPK type 15 evaluator was non-positive. This value must be positive. The value supplied was #. │ │ - [ 24eaa] SPICE(BADVECTOR) │ │ - [ 24ebb] SPICE(ECCOUTOFRANGE) │ │ - [ 24ed0] Attempt to set size of cell to invalid value. The value was #. │ │ - [ 24f10] TIPBOD │ │ - [ 24f17] tisbod_ │ │ - [ 24f1f] BODY#_CONSTS_REF_FRAME │ │ - [ 24f36] SPICE(COMPETINGFRAMESPEC) │ │ - [ 24f50] PCKR02 │ │ - [ 24f57] Axis numbers are #, #, #. │ │ - [ 24f74] The frame to which frame # is relatively defined is not recognized. The kernel pool specification of the relative frame is '#'. This is not a recognized frame. │ │ - [ 25016] #: The number of components of the kernel pool variable '#' is required to be divisible by #. However, the actual number of components is # which is not evenly divisible by #. │ │ - [ 250c8] CHKOUT: Caller is │ │ - [ 250dc] VALIDC │ │ - [ 250e3] Input matrix is not a rotation. │ │ - [ 25103] The number of rows in the matrix is not positive. The number of rows is #. │ │ - [ 2514e] kercod │ │ - [ 25155] ZZCKSPK │ │ - [ 2515d] ZZCVPOOL │ │ - [ 25166] The file, #, has a unidentified file architecture. Check that this file is a properly created binary SPICE kernel. │ │ - [ 251da] SPICE(DSKBOGUSENTRY) │ │ - [ 251ef] SPICE(BUFFEROVERFLOW) │ │ - [ 25205] SPICE(VARNAMETOOLONG) │ │ - [ 2521b] Definition of frame # specifies obliquity model #, which is not recognized. This situation is usually caused by an error in a frame kernel in which the frame is defined. │ │ - [ 252c5] Dynamic frame family # (in definition of frame #) is not supported. This situation is usually caused by an error in a frame kernel in which the frame is defined. │ │ - [ 25367] Ratio of length of axis #* to length of axis #* is *; this value may cause numeric overflow. │ │ - [ 253c4] ZZDYNVAC │ │ - [ 253cd] Kernel variable # was expected to be present in the kernel pool but was not found. The alternative form of kernel variable name FRAME_#_# was not searched for because this name has excessive length (# characters vs allowed maximum of #). One of these variables is needed to define the parameterized dynamic frame #. Usually this type of problem is due to an error in a frame definition provided in a frame kernel. │ │ - [ 2556e] The index type # is not supported. │ │ - [ 25591] ZZEKILLT │ │ - [ 2559a] ZZEKLLTD │ │ - [ 255a3] SEM_CHECKED │ │ - [ 255af] Record having pointer # not found in segment # of file # │ │ - [ 255e8] File # contains data; LASTC = #; LASTD = #; LASTI = #. │ │ - [ 2561f] Attempt to free non-existent INT page. Page number = #; valid range is 1:# │ │ - [ 2566a] DASUDD │ │ - [ 25671] IAU_PLUTO_BARYCENTER │ │ - [ 25686] IAU_BENNU │ │ - [ 25690] IAU_DIDYMOS │ │ - [ 2569c] EARTH BARYCENTER │ │ - [ 256ad] PLUTO BARYCENTER │ │ - [ 256be] MNEME │ │ - [ 256c4] MARGARET │ │ - [ 256cd] LARISSA │ │ - [ 256d5] VIKING 2 ORBITER │ │ - [ 256e6] MPF │ │ - [ 256ea] EDL DEMONSTRATOR MODULE │ │ - [ 25702] LUNAR TRAILBLAZER │ │ - [ 25714] MERCURY TRANSFER MODULE │ │ - [ 2572c] FINLAY │ │ - [ 25733] GEHRELS 1 │ │ - [ 2573d] GRIGG-SKJELLERUP │ │ - [ 2574e] KOHOUTEK │ │ - [ 25757] PSYCHE │ │ - [ 2575e] LUTETIA │ │ - [ 25766] GASPRA │ │ - [ 2576d] DONALDJOHANSON │ │ - [ 2577c] DSS-14 │ │ - [ 25783] There is a non-printing character embedded in line # of the text kernel file #. Non-printing characters are not allowed in kernel variable assignments. The non-printing character has ASCII code #. │ │ - [ 2584b] The kernel variable # has been set up as a string variable. However, the value that you are attempting to assign to this variable on line # of the kernel file '#' is not a string value. │ │ - [ 25907] The only type of time strings that are handled by TPARSE are 'JD', 'YMD' and 'YD' (year day-of-year). You've entered a string of the type #. │ │ - [ 25996] w. │ │ - [ 25999] tpartv_ │ │ - [ 259a1] meanng │ │ - [ 259a8] The input string uses the ISO "T" date/time delimiter but does not match any of the accepted ISO formats. │ │ - [ 25a14] *Y │ │ - [ 25a17] The substring "#" could not be resolved in the input string: ' │ │ - [ 25a57] DmH │ │ - [ 25a5b] kvtype │ │ - [ 25a62] lb │ │ - [ 25a65] Modulus count # does not match field count # for SCLK #. │ │ - [ 25a9e] YWDF │ │ - [ 25aa4] ZZSPKPA1 │ │ - [ 25aad] clsses │ │ - [ 25ab4] SPICE(FRAMENAMENOTFOUND) │ │ - [ 25acd] TIMDEF │ │ - [ 25ad4] Invalid data type code # seen │ │ - [ 25af2] SEPTEMBER │ │ - [ 25afc] A character at location #1 does not have ASCII value [32,126] for REP string. │ │ - [ 25b4a] AP │ │ - [ 25b4d] A minutes components of the time was identified in the time string "#", but the hours component could not be identified. │ │ - [ 25bc8] Yidi:i │ │ - [ 25bcf] Yiii:i:i │ │ - [ 25bd8] Yimn │ │ - [ 25bdd] iYdi:i:n │ │ - [ 25be6] iYdi:n │ │ - [ 25bed] i-iti │ │ - [ 25bf3] i-i-Yi:i:n │ │ - [ 25bfe] Y*m*D*H* │ │ - [ 25c07] CS │ │ - [ 25c0a] CW │ │ - [ 25c0d] iw │ │ - [ 25c10] ada │ │ - [ 25c14] af │ │ - [ 25c17] chm │ │ - [ 25c1b] cps │ │ - [ 25c1f] egl │ │ - [ 25c23] el │ │ - [ 25c26] enm │ │ - [ 25c2a] et │ │ - [ 25c2d] ext │ │ - [ 25c31] kcg │ │ - [ 25c35] krc │ │ - [ 25c39] ks │ │ - [ 25c3c] lv │ │ - [ 25c3f] mk │ │ - [ 25c42] ms │ │ - [ 25c45] mwv │ │ - [ 25c49] non │ │ - [ 25c4d] nus │ │ - [ 25c51] sei │ │ - [ 25c55] ty │ │ - [ 25c58] xmf │ │ - [ 25c5c] fin │ │ - [ 25c60] lat │ │ - [ 25c64] nep │ │ - [ 25c68] san │ │ - [ 25c6c] slv │ │ - [ 25c70] zho │ │ - [ 25c74] AO │ │ - [ 25c77] CU │ │ - [ 25c7a] GN │ │ - [ 25c7d] LS │ │ - [ 25c80] MP │ │ - [ 25c83] MT │ │ - [ 25c86] TF │ │ - [ 25c89] US │ │ - [ 25c8c] WF │ │ - [ 25c8f] DGA │ │ - [ 25c93] GBR │ │ - [ 25c97] GMB │ │ - [ 25c9b] MAF │ │ - [ 25c9f] SPM │ │ - [ 25ca3] SWE │ │ - [ 25ca7] SOM │ │ - [ 25cab] TON │ │ - [ 25caf] YEM │ │ - [ 25cb3] YUG │ │ - [ 25cb7] gl_ES │ │ - [ 25cbd] it_IT │ │ - [ 25cc3] posix/ │ │ - [ 25cca] CLT │ │ - [ 25cce] ar_YE │ │ - [ 25cd4] ckb_Arab │ │ - [ 25cdd] de_CH │ │ - [ 25ce3] en_CA │ │ - [ 25ce9] se_NO │ │ - [ 25cef] sma_NO │ │ - [ 25cf6] tn_BW │ │ - [ 25cfc] sgn-gr │ │ - [ 25d03] isg │ │ - [ 25d07] sgn-it │ │ - [ 25d0e] sgn-us │ │ - [ 25d15] zh-cmn-hant │ │ - [ 25d21] M09 │ │ - [ 25d25] Scripts%short │ │ - [ 25d33] Types │ │ - [ 25d39] lw │ │ - [ 25d3c] nfc │ │ - [ 25d40] AliasLocales │ │ - [ 25d4d] [BOGUS UErrorCode] │ │ - [ 25d60] U_INVALID_STATE_ERROR │ │ - [ 25d76] U_MULTIPLE_CURSORS │ │ - [ 25d89] U_UNEXPECTED_TOKEN │ │ - [ 25d9c] U_MF_VARIANT_KEY_MISMATCH_ERROR │ │ - [ 25dbc] U_BRK_RULE_EMPTY_SET │ │ - [ 25dd1] U_REGEX_OCTAL_TOO_BIG │ │ - [ 25de7] BDT │ │ - [ 25deb] BGN │ │ - [ 25def] BND │ │ - [ 25df3] ISJ │ │ - [ 25df7] KZT │ │ - [ 25dfb] MMK │ │ - [ 25dff] PAB │ │ - [ 25e03] -Infinity │ │ - [ 25e0d] M11L │ │ - [ 25e12] square-foot │ │ - [ 25e1e] square-yard │ │ - [ 25e2a] milligram-per-deciliter │ │ - [ 25e42] GHP │ │ - [ 25e46] kilobyte │ │ - [ 25e4f] megabit │ │ - [ 25e57] century │ │ - [ 25e5f] milliampere │ │ - [ 25e6b] earth-radius │ │ - [ 25e78] stone │ │ - [ 25e7e] newton-meter │ │ - [ 25e8b] pound-force-foot │ │ - [ 25e9c] dessert-spoon-imperial │ │ - [ 25eb3] pint-metric │ │ - [ 25ebf] nominative │ │ - [ 25eca] masculine │ │ - [ 25ed4] ther │ │ - [ 25ed9] per- │ │ - [ 25ede] -per- │ │ - [ 25ee4] NumberElements/minimumGroupingDigits │ │ - [ 25f09] dayOfYear │ │ - [ 25f13] idValidity │ │ - [ 25f1e] OrdinalRules │ │ - [ 25f2b] primary │ │ - [ 25f33] lower │ │ - [ 25f39] primary tailoring gap too small │ │ - [ 25f59] string contains U+FFFD, U+FFFE or U+FFFF │ │ - [ 25f82] first tertiary ignorable │ │ - [ 25f9b] first trailing │ │ - [ 25faa] metric_adjacent │ │ - [ 25fba] com/google/androidgamesdk/SwappyDisplayManager │ │ - [ 25fe9] static int swappy::SwappyGL::getSupportedRefreshPeriodsNS(uint64_t *, int) │ │ - [ 26034] eglGetFrameTimestampsANDROID │ │ - [ 26051] mousemove │ │ - [ 2605b] Markers enabled │ │ - [ 2606b] Time is paused │ │ - [ 2607a] Auto magnitude limit at 45 degrees: {:.2f} │ │ - [ 260a6] passthrough │ │ - [ 260b2] WN │ │ - [ 260b5] ly/s │ │ - [ 260ba] mi/s │ │ - [ 260bf] Luminosity: {}x Sun\n │ │ - [ 260d4] Pre Format Conversion: %s\n │ │ - [ 260f6] CHANNEL_AUX_6 │ │ - [ 26104] CHANNEL_AUX_11 │ │ - [ 26113] CHANNEL_AUX_16 │ │ - [ 26122] CHANNEL_AUX_26 │ │ - [ 26131] Socket type not supported │ │ - [ 2614b] Device not initialized │ │ - [ 26162] WinMM │ │ - [ 26168] AAudioStream_getFramesPerBurst │ │ - [ 26187] Target name: {} │ │ - [ 26197] UTC │ │ - [ 2619b] Mon │ │ - [ 2619f] Thu │ │ - [ 261a3] Font is not scalable: {}\n │ │ - [ 261bd] gainsboro │ │ - [ 261c7] green │ │ - [ 261cd] springgreen │ │ - [ 261d9] teal │ │ - [ 261de] yellow │ │ - [ 261e5] .mkv │ │ - [ 261ea] MU │ │ - [ 261ed] Delta │ │ - [ 261f3] Spacecraft │ │ - [ 261fe] Star │ │ - [ 26203] landingsite │ │ - [ 2620f] reticulum │ │ - [ 26219] macula │ │ - [ 26220] setframe │ │ - [ 26229] print │ │ - [ 2622f] value │ │ - [ 26235] observer │ │ - [ 2623e] nopause │ │ - [ 26246] yrot │ │ - [ 2624b] utc │ │ - [ 2624f] medium │ │ - [ 26256] symbol │ │ - [ 2625d] Unknown error loading script │ │ - [ 2627a] getobserver │ │ - [ 26286] getminorbitsize │ │ - [ 26296] getscripttime │ │ - [ 262a4] First argument to celestia:setlabelstyle() must be a string │ │ - [ 262e0] No arguments expected for celestia:getgalaxylightgain() │ │ - [ 26318] No arguments expected for celestia:getobserver() │ │ - [ 26349] No argument expected to function celestia:gettime │ │ - [ 2637b] No argument expected in celestia:setambient │ │ - [ 263a7] No argument expected in celestia:getstarcolor │ │ - [ 263d5] Second arg to celestia:utctotdb must be a number │ │ - [ 26406] Fifth argument to celestia:playaudio must be a number │ │ - [ 2643c] Seventh argument to celestia:playaudio must be a number(nopause) │ │ - [ 2647d] loadlib │ │ - [ 26485] __gc │ │ - [ 2648a] [Frame] │ │ - [ 26492] LineWidth │ │ - [ 2649c] Vertex │ │ - [ 264a3] argument 2 to gl.Color must be a number │ │ - [ 264cb] removefromcategory │ │ - [ 264de] lifespanEnd │ │ - [ 264ea] atmosphereHeight │ │ - [ 264fb] Third arg to object:mark must be a number │ │ - [ 26525] No arguments are expected for object:getmass() │ │ - [ 26554] One parameter expected to function object:setatmosphere │ │ - [ 2658c] Value of {} must be array of 3 numbers │ │ - [ 265b3] initialOrientation │ │ - [ 265c6] Fifth arg to observer:gotolonglat must be a number │ │ - [ 265f9] One argument expected to position:addvector() │ │ - [ 26627] Two arguments expected for rotation:setaxisangle() │ │ - [ 2665a] Need two operands for add │ │ - [ 26674] {} (line {}) │ │ - [ 26681] {} {} {} │ │ - [ 2668a] Mesh should contain just triangle lists\n │ │ - [ 266b3] jpl-venus-sun │ │ - [ 266c1] jpl-moon-emb │ │ - [ 266ce] europa │ │ - [ 266d5] Bad script orbit: valid range end < begin\n │ │ - [ 26700] starTex │ │ - [ 26708] CrA │ │ - [ 2670c] Gru │ │ - [ 26710] TrA │ │ - [ 26714] InfoURL │ │ - [ 2671c] file:///{}/{} │ │ - [ 2672a] GL_EXT_texture_filter_anisotropic │ │ - [ 2674c] RE │ │ - [ 2674f] FM │ │ - [ 26752] Failed to read mesh data\n │ │ - [ 2676c] ScriptedRotation │ │ - [ 2677d] PrecessingRotation │ │ - [ 26790] Invalid Source filename for SampledTrajectory\n │ │ - [ 267bf] Could not load sampled trajectory from '{}'\n │ │ - [ 267ec] Secondary │ │ - [ 267f6] Observer │ │ - [ 267ff] Observer object '{}' for topocentric frame not found.\n │ │ - [ 26836] rJ │ │ - [ 26839] float NV = dot(n, V);\n │ │ - [ 26850] position = in_Position.xyz * (ringRadius + ringWidth * in_TexCoord0.s);\n │ │ - [ 26899] Vertex shader source:\n │ │ - [ 268b0] h = max(0.0, length(atmSamplePoint) - atmosphereRadius.z);\n │ │ - [ 268f0] BumpMap │ │ - [ 268f8] Sorting stars into octree . . .\n │ │ - [ 26919] Loading cross index failed - unexpected EOF\n │ │ - [ 26946] hires │ │ - [ 2694c] .{:s} │ │ - [ 26952] Error parsing virtual texture\n │ │ - [ 26971] {:04x} │ │ - [ 26978] Content size {} too small to include point array with {} entries │ │ - [ 269b9] (J)V │ │ - [ 269be] {}_{} │ │ - [ 269c4] ] │ │ - [ 269c7] cannot use operator[] with a numeric argument with │ │ - [ 269fb] libGLESv2.so │ │ - [ 26a08] llo │ │ - [ 26a0c] LC_TIME │ │ - [ 26a14] libjpeg-turbo version 3.0.4 (build 20241006) │ │ + [ 2490d] C type │ │ + [ 24914] string/number/__tostring │ │ + [ 2492d] but running with │ │ + [ 24940] truncated │ │ + [ 2494a] unexpected 8-bit transformation │ │ + [ 2496a] CRC error │ │ + [ 24974] cHRM Red X │ │ + [ 2497f] Memory allocation failed while processing sCAL │ │ + [ 249ae] Z_OK on Z_FINISH with output space │ │ + [ 249d1] Can't write sCAL (buffer too small) │ │ + [ 249f5] option │ │ + [ 249fc] PATH_VALUES │ │ + [ 24a08] ftnum │ │ + [ 24a0e] itexp │ │ + [ 24a14] SPICE(BLANKFILETYPE) │ │ + [ 24a29] UNFORMATTED │ │ + [ 24a35] can't backspace file │ │ + [ 24a4a] bad namelist name │ │ + [ 24a5c] substring out of bounds │ │ + [ 24a74] unformatted │ │ + [ 24a80] FIND_TABLE │ │ + [ 24a8b] SPICE(COLDESCTABLEFULL) │ │ + [ 24aa3] The EK file # could not be loaded; the column # in already loaded table # is not present in segment # in the EK file. │ │ + [ 24b19] SPICE(TABLENOTLOADED) │ │ + [ 24b2f] seltab │ │ + [ 24b36] EKNELT │ │ + [ 24b3d] rowvec │ │ + [ 24b44] prev │ │ + [ 24b49] SPICE(UNRECOGNIZEDACTION) │ │ + [ 24b63] rngloc │ │ + [ 24b6a] DASCLS │ │ + [ 24b71] DASLLA │ │ + [ 24b78] There is no room available for adding another numeric value to the kernel pool. │ │ + [ 24bc8] do_fio │ │ + [ 24bcf] E- │ │ + [ 24bd2] Could not read from #. │ │ + [ 24be9] resvd │ │ + [ 24bef] FIVE │ │ + [ 24bf4] IRFNAM │ │ + [ 24bfb] CONVRT: Incompatible units. You are attempting to convert │ │ + [ 24c36] CKFROT │ │ + [ 24c3d] SPICE(WRONGCKTYPE) │ │ + [ 24c50] CKR03 │ │ + [ 24c56] SCTYPE │ │ + [ 24c5d] A traceback follows. The name of the highest level module is first. │ │ + [ 24ca2] SIZEI │ │ + [ 24ca8] character │ │ + [ 24cb2] The reference frame # has class #. This form of reference frame is not supported in version # of FRMGET. You need to update your version of SPICELIB to the latest version in order to support this frame. │ │ + [ 24d7e] mxvg_ │ │ + [ 24d84] Storage for # double precision numbers is needed for an SPK data record and only # locations were available. Update the parameter MAXREC in the subroutine SPKPVN and notify the NAIF group of this problem. │ │ + [ 24e51] The semi-latus rectum supplied to the SPK type 15 evaluator was non-positive. This value must be positive. The value supplied was #. │ │ + [ 24ed7] SPICE(BADVECTOR) │ │ + [ 24ee8] SPICE(ECCOUTOFRANGE) │ │ + [ 24efd] Attempt to set size of cell to invalid value. The value was #. │ │ + [ 24f3d] TIPBOD │ │ + [ 24f44] tisbod_ │ │ + [ 24f4c] BODY#_CONSTS_REF_FRAME │ │ + [ 24f63] SPICE(COMPETINGFRAMESPEC) │ │ + [ 24f7d] PCKR02 │ │ + [ 24f84] Axis numbers are #, #, #. │ │ + [ 24fa1] The frame to which frame # is relatively defined is not recognized. The kernel pool specification of the relative frame is '#'. This is not a recognized frame. │ │ + [ 25043] #: The number of components of the kernel pool variable '#' is required to be divisible by #. However, the actual number of components is # which is not evenly divisible by #. │ │ + [ 250f5] CHKOUT: Caller is │ │ + [ 25109] VALIDC │ │ + [ 25110] Input matrix is not a rotation. │ │ + [ 25130] The number of rows in the matrix is not positive. The number of rows is #. │ │ + [ 2517b] kercod │ │ + [ 25182] ZZCKSPK │ │ + [ 2518a] ZZCVPOOL │ │ + [ 25193] The file, #, has a unidentified file architecture. Check that this file is a properly created binary SPICE kernel. │ │ + [ 25207] SPICE(DSKBOGUSENTRY) │ │ + [ 2521c] SPICE(BUFFEROVERFLOW) │ │ + [ 25232] SPICE(VARNAMETOOLONG) │ │ + [ 25248] Definition of frame # specifies obliquity model #, which is not recognized. This situation is usually caused by an error in a frame kernel in which the frame is defined. │ │ + [ 252f2] Dynamic frame family # (in definition of frame #) is not supported. This situation is usually caused by an error in a frame kernel in which the frame is defined. │ │ + [ 25394] Ratio of length of axis #* to length of axis #* is *; this value may cause numeric overflow. │ │ + [ 253f1] ZZDYNVAC │ │ + [ 253fa] Kernel variable # was expected to be present in the kernel pool but was not found. The alternative form of kernel variable name FRAME_#_# was not searched for because this name has excessive length (# characters vs allowed maximum of #). One of these variables is needed to define the parameterized dynamic frame #. Usually this type of problem is due to an error in a frame definition provided in a frame kernel. │ │ + [ 2559b] The index type # is not supported. │ │ + [ 255be] ZZEKILLT │ │ + [ 255c7] ZZEKLLTD │ │ + [ 255d0] SEM_CHECKED │ │ + [ 255dc] Record having pointer # not found in segment # of file # │ │ + [ 25615] File # contains data; LASTC = #; LASTD = #; LASTI = #. │ │ + [ 2564c] Attempt to free non-existent INT page. Page number = #; valid range is 1:# │ │ + [ 25697] DASUDD │ │ + [ 2569e] IAU_PLUTO_BARYCENTER │ │ + [ 256b3] IAU_BENNU │ │ + [ 256bd] IAU_DIDYMOS │ │ + [ 256c9] EARTH BARYCENTER │ │ + [ 256da] PLUTO BARYCENTER │ │ + [ 256eb] MNEME │ │ + [ 256f1] MARGARET │ │ + [ 256fa] LARISSA │ │ + [ 25702] VIKING 2 ORBITER │ │ + [ 25713] MPF │ │ + [ 25717] EDL DEMONSTRATOR MODULE │ │ + [ 2572f] LUNAR TRAILBLAZER │ │ + [ 25741] MERCURY TRANSFER MODULE │ │ + [ 25759] FINLAY │ │ + [ 25760] GEHRELS 1 │ │ + [ 2576a] GRIGG-SKJELLERUP │ │ + [ 2577b] KOHOUTEK │ │ + [ 25784] PSYCHE │ │ + [ 2578b] LUTETIA │ │ + [ 25793] GASPRA │ │ + [ 2579a] DONALDJOHANSON │ │ + [ 257a9] DSS-14 │ │ + [ 257b0] There is a non-printing character embedded in line # of the text kernel file #. Non-printing characters are not allowed in kernel variable assignments. The non-printing character has ASCII code #. │ │ + [ 25878] The kernel variable # has been set up as a string variable. However, the value that you are attempting to assign to this variable on line # of the kernel file '#' is not a string value. │ │ + [ 25934] The only type of time strings that are handled by TPARSE are 'JD', 'YMD' and 'YD' (year day-of-year). You've entered a string of the type #. │ │ + [ 259c3] w. │ │ + [ 259c6] tpartv_ │ │ + [ 259ce] meanng │ │ + [ 259d5] The input string uses the ISO "T" date/time delimiter but does not match any of the accepted ISO formats. │ │ + [ 25a41] *Y │ │ + [ 25a44] The substring "#" could not be resolved in the input string: ' │ │ + [ 25a84] DmH │ │ + [ 25a88] kvtype │ │ + [ 25a8f] lb │ │ + [ 25a92] Modulus count # does not match field count # for SCLK #. │ │ + [ 25acb] YWDF │ │ + [ 25ad1] ZZSPKPA1 │ │ + [ 25ada] clsses │ │ + [ 25ae1] SPICE(FRAMENAMENOTFOUND) │ │ + [ 25afa] TIMDEF │ │ + [ 25b01] Invalid data type code # seen │ │ + [ 25b1f] SEPTEMBER │ │ + [ 25b29] A character at location #1 does not have ASCII value [32,126] for REP string. │ │ + [ 25b77] AP │ │ + [ 25b7a] A minutes components of the time was identified in the time string "#", but the hours component could not be identified. │ │ + [ 25bf5] Yidi:i │ │ + [ 25bfc] Yiii:i:i │ │ + [ 25c05] Yimn │ │ + [ 25c0a] iYdi:i:n │ │ + [ 25c13] iYdi:n │ │ + [ 25c1a] i-iti │ │ + [ 25c20] i-i-Yi:i:n │ │ + [ 25c2b] Y*m*D*H* │ │ + [ 25c34] CS │ │ + [ 25c37] CW │ │ + [ 25c3a] iw │ │ + [ 25c3d] ada │ │ + [ 25c41] af │ │ + [ 25c44] chm │ │ + [ 25c48] cps │ │ + [ 25c4c] egl │ │ + [ 25c50] el │ │ + [ 25c53] enm │ │ + [ 25c57] et │ │ + [ 25c5a] ext │ │ + [ 25c5e] kcg │ │ + [ 25c62] krc │ │ + [ 25c66] ks │ │ + [ 25c69] lv │ │ + [ 25c6c] mk │ │ + [ 25c6f] ms │ │ + [ 25c72] mwv │ │ + [ 25c76] non │ │ + [ 25c7a] nus │ │ + [ 25c7e] sei │ │ + [ 25c82] ty │ │ + [ 25c85] xmf │ │ + [ 25c89] fin │ │ + [ 25c8d] lat │ │ + [ 25c91] nep │ │ + [ 25c95] san │ │ + [ 25c99] slv │ │ + [ 25c9d] zho │ │ + [ 25ca1] AO │ │ + [ 25ca4] CU │ │ + [ 25ca7] GN │ │ + [ 25caa] LS │ │ + [ 25cad] MP │ │ + [ 25cb0] MT │ │ + [ 25cb3] TF │ │ + [ 25cb6] US │ │ + [ 25cb9] WF │ │ + [ 25cbc] DGA │ │ + [ 25cc0] GBR │ │ + [ 25cc4] GMB │ │ + [ 25cc8] MAF │ │ + [ 25ccc] SPM │ │ + [ 25cd0] SWE │ │ + [ 25cd4] SOM │ │ + [ 25cd8] TON │ │ + [ 25cdc] YEM │ │ + [ 25ce0] YUG │ │ + [ 25ce4] gl_ES │ │ + [ 25cea] it_IT │ │ + [ 25cf0] posix/ │ │ + [ 25cf7] CLT │ │ + [ 25cfb] ar_YE │ │ + [ 25d01] ckb_Arab │ │ + [ 25d0a] de_CH │ │ + [ 25d10] en_CA │ │ + [ 25d16] se_NO │ │ + [ 25d1c] sma_NO │ │ + [ 25d23] tn_BW │ │ + [ 25d29] sgn-gr │ │ + [ 25d30] isg │ │ + [ 25d34] sgn-it │ │ + [ 25d3b] sgn-us │ │ + [ 25d42] zh-cmn-hant │ │ + [ 25d4e] M09 │ │ + [ 25d52] Scripts%short │ │ + [ 25d60] Types │ │ + [ 25d66] lw │ │ + [ 25d69] nfc │ │ + [ 25d6d] AliasLocales │ │ + [ 25d7a] [BOGUS UErrorCode] │ │ + [ 25d8d] U_INVALID_STATE_ERROR │ │ + [ 25da3] U_MULTIPLE_CURSORS │ │ + [ 25db6] U_UNEXPECTED_TOKEN │ │ + [ 25dc9] U_MF_VARIANT_KEY_MISMATCH_ERROR │ │ + [ 25de9] U_BRK_RULE_EMPTY_SET │ │ + [ 25dfe] U_REGEX_OCTAL_TOO_BIG │ │ + [ 25e14] BDT │ │ + [ 25e18] BGN │ │ + [ 25e1c] BND │ │ + [ 25e20] ISJ │ │ + [ 25e24] KZT │ │ + [ 25e28] MMK │ │ + [ 25e2c] PAB │ │ + [ 25e30] -Infinity │ │ + [ 25e3a] M11L │ │ + [ 25e3f] square-foot │ │ + [ 25e4b] square-yard │ │ + [ 25e57] milligram-per-deciliter │ │ + [ 25e6f] GHP │ │ + [ 25e73] kilobyte │ │ + [ 25e7c] megabit │ │ + [ 25e84] century │ │ + [ 25e8c] milliampere │ │ + [ 25e98] earth-radius │ │ + [ 25ea5] stone │ │ + [ 25eab] newton-meter │ │ + [ 25eb8] pound-force-foot │ │ + [ 25ec9] dessert-spoon-imperial │ │ + [ 25ee0] pint-metric │ │ + [ 25eec] nominative │ │ + [ 25ef7] masculine │ │ + [ 25f01] ther │ │ + [ 25f06] per- │ │ + [ 25f0b] -per- │ │ + [ 25f11] NumberElements/minimumGroupingDigits │ │ + [ 25f36] dayOfYear │ │ + [ 25f40] idValidity │ │ + [ 25f4b] OrdinalRules │ │ + [ 25f58] primary │ │ + [ 25f60] lower │ │ + [ 25f66] primary tailoring gap too small │ │ + [ 25f86] string contains U+FFFD, U+FFFE or U+FFFF │ │ + [ 25faf] first tertiary ignorable │ │ + [ 25fc8] first trailing │ │ + [ 25fd7] metric_adjacent │ │ + [ 25fe7] com/google/androidgamesdk/SwappyDisplayManager │ │ + [ 26016] static int swappy::SwappyGL::getSupportedRefreshPeriodsNS(uint64_t *, int) │ │ + [ 26061] eglGetFrameTimestampsANDROID │ │ + [ 2607e] mousemove │ │ + [ 26088] Markers enabled │ │ + [ 26098] Time is paused │ │ + [ 260a7] Auto magnitude limit at 45 degrees: {:.2f} │ │ + [ 260d3] passthrough │ │ + [ 260df] WN │ │ + [ 260e2] ly/s │ │ + [ 260e7] mi/s │ │ + [ 260ec] Luminosity: {}x Sun\n │ │ + [ 26101] Pre Format Conversion: %s\n │ │ + [ 26123] CHANNEL_AUX_6 │ │ + [ 26131] CHANNEL_AUX_11 │ │ + [ 26140] CHANNEL_AUX_16 │ │ + [ 2614f] CHANNEL_AUX_26 │ │ + [ 2615e] Socket type not supported │ │ + [ 26178] Device not initialized │ │ + [ 2618f] WinMM │ │ + [ 26195] AAudioStream_getFramesPerBurst │ │ + [ 261b4] Target name: {} │ │ + [ 261c4] UTC │ │ + [ 261c8] Mon │ │ + [ 261cc] Thu │ │ + [ 261d0] Font is not scalable: {}\n │ │ + [ 261ea] gainsboro │ │ + [ 261f4] green │ │ + [ 261fa] springgreen │ │ + [ 26206] teal │ │ + [ 2620b] yellow │ │ + [ 26212] .mkv │ │ + [ 26217] MU │ │ + [ 2621a] Delta │ │ + [ 26220] Spacecraft │ │ + [ 2622b] Star │ │ + [ 26230] landingsite │ │ + [ 2623c] reticulum │ │ + [ 26246] macula │ │ + [ 2624d] setframe │ │ + [ 26256] print │ │ + [ 2625c] value │ │ + [ 26262] observer │ │ + [ 2626b] nopause │ │ + [ 26273] yrot │ │ + [ 26278] utc │ │ + [ 2627c] medium │ │ + [ 26283] symbol │ │ + [ 2628a] Unknown error loading script │ │ + [ 262a7] getobserver │ │ + [ 262b3] getminorbitsize │ │ + [ 262c3] getscripttime │ │ + [ 262d1] First argument to celestia:setlabelstyle() must be a string │ │ + [ 2630d] No arguments expected for celestia:getgalaxylightgain() │ │ + [ 26345] No arguments expected for celestia:getobserver() │ │ + [ 26376] No argument expected to function celestia:gettime │ │ + [ 263a8] No argument expected in celestia:setambient │ │ + [ 263d4] No argument expected in celestia:getstarcolor │ │ + [ 26402] Second arg to celestia:utctotdb must be a number │ │ + [ 26433] Fifth argument to celestia:playaudio must be a number │ │ + [ 26469] Seventh argument to celestia:playaudio must be a number(nopause) │ │ + [ 264aa] loadlib │ │ + [ 264b2] __gc │ │ + [ 264b7] [Frame] │ │ + [ 264bf] LineWidth │ │ + [ 264c9] Vertex │ │ + [ 264d0] argument 2 to gl.Color must be a number │ │ + [ 264f8] removefromcategory │ │ + [ 2650b] lifespanEnd │ │ + [ 26517] atmosphereHeight │ │ + [ 26528] Third arg to object:mark must be a number │ │ + [ 26552] No arguments are expected for object:getmass() │ │ + [ 26581] One parameter expected to function object:setatmosphere │ │ + [ 265b9] Value of {} must be array of 3 numbers │ │ + [ 265e0] initialOrientation │ │ + [ 265f3] Fifth arg to observer:gotolonglat must be a number │ │ + [ 26626] One argument expected to position:addvector() │ │ + [ 26654] Two arguments expected for rotation:setaxisangle() │ │ + [ 26687] Need two operands for add │ │ + [ 266a1] {} (line {}) │ │ + [ 266ae] {} {} {} │ │ + [ 266b7] Mesh should contain just triangle lists\n │ │ + [ 266e0] jpl-venus-sun │ │ + [ 266ee] jpl-moon-emb │ │ + [ 266fb] europa │ │ + [ 26702] Bad script orbit: valid range end < begin\n │ │ + [ 2672d] starTex │ │ + [ 26735] CrA │ │ + [ 26739] Gru │ │ + [ 2673d] TrA │ │ + [ 26741] InfoURL │ │ + [ 26749] file:///{}/{} │ │ + [ 26757] GL_EXT_texture_filter_anisotropic │ │ + [ 26779] RE │ │ + [ 2677c] FM │ │ + [ 2677f] Failed to read mesh data\n │ │ + [ 26799] ScriptedRotation │ │ + [ 267aa] PrecessingRotation │ │ + [ 267bd] Invalid Source filename for SampledTrajectory\n │ │ + [ 267ec] Could not load sampled trajectory from '{}'\n │ │ + [ 26819] Secondary │ │ + [ 26823] Observer │ │ + [ 2682c] Observer object '{}' for topocentric frame not found.\n │ │ + [ 26863] rJ │ │ + [ 26866] float NV = dot(n, V);\n │ │ + [ 2687d] position = in_Position.xyz * (ringRadius + ringWidth * in_TexCoord0.s);\n │ │ + [ 268c6] Vertex shader source:\n │ │ + [ 268dd] h = max(0.0, length(atmSamplePoint) - atmosphereRadius.z);\n │ │ + [ 2691d] BumpMap │ │ + [ 26925] Sorting stars into octree . . .\n │ │ + [ 26946] Loading cross index failed - unexpected EOF\n │ │ + [ 26973] hires │ │ + [ 26979] .{:s} │ │ + [ 2697f] Error parsing virtual texture\n │ │ + [ 2699e] {:04x} │ │ + [ 269a5] Content size {} too small to include point array with {} entries │ │ + [ 269e6] (J)V │ │ + [ 269eb] {}_{} │ │ + [ 269f1] ] │ │ + [ 269f4] cannot use operator[] with a numeric argument with │ │ + [ 26a28] libGLESv2.so │ │ + [ 26a35] llo │ │ + [ 26a39] LC_TIME │ │ [ 26a41] Invalid memory pool code %d │ │ [ 26a5d] Write to XMS failed │ │ [ 26a71] Adobe APP14 marker: version %d, flags 0x%04x 0x%04x, transform %d │ │ [ 26ab3] Opened temporary file %s │ │ [ 26acc] FREETYPE_PROPERTIES │ │ [ 26ae0] kerning │ │ [ 26ae8] cff │ │ @@ -4194297,8 +4194297,8 @@ │ │ [19665c6] } │ │ [19665c8] │ │ [19665dc] │ │ [19665ea] { │ │ [19665ec] 0 │ │ [19665ee] } │ │ [19665f0] │ │ -[ Too much input for diff (SHA256: bab3594e584d66bf6a8f6a2ba8196c2f73cd982d0c1af33ea1f9bb161089b71b) ] │ │ +[ Too much input for diff (SHA256: a147b0ffd784aaf9eb4640a9fec81280d3829ecbb8f7b0e6bc62230d86b58379) ] │ ├── objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {} │ │ @@ -130,15 +130,15 @@ │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ add r4, pc, #584 @ (adr r4, 207d4d8 <_ZNSt6__ndk112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6appendB8ne180000IPKcTnNS_9enable_ifIXsr31__has_forward_iterator_categoryIT_EE5valueEiE4typeELi0EEERS5_SA_SA_@@Base+0xa0>) │ │ lsls r3, r5, #1 │ │ add r4, pc, #584 @ (adr r4, 207d4dc <_ZNSt6__ndk112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6appendB8ne180000IPKcTnNS_9enable_ifIXsr31__has_forward_iterator_categoryIT_EE5valueEiE4typeELi0EEERS5_SA_SA_@@Base+0xa4>) │ │ lsls r3, r5, #1 │ │ - bl 1dc1ecc │ │ + bl 1deeecc │ │ add r3, pc, #944 @ (adr r3, 207d64c ) │ │ lsls r3, r5, #1 │ │ │ │ 0207d29c : │ │ vmov s0, r1 │ │ vldr s2, [r0, #16] │ │ vcmp.f32 s2, s0 │ │ @@ -2924,15 +2924,15 @@ │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ ldrh r2, [r6, #6] │ │ lsls r3, r5, #1 │ │ strh r2, [r2, #60] @ 0x3c │ │ lsls r3, r5, #1 │ │ - adds r6, #211 @ 0xd3 │ │ + adds r7, #0 │ │ Address 0x207eeea is out of bounds. │ │ │ │ │ │ 0207eeec , std::__ndk1::allocator > const&, bool)@@Base>: │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #32 │ │ @@ -3351,15 +3351,15 @@ │ │ addeq sp, #48 @ 0x30 │ │ vpopeq {d8-d10} │ │ ldmiaeq.w sp!, {r8, r9, sl} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ strh r6, [r4, #40] @ 0x28 │ │ lsls r3, r5, #1 │ │ - bl 218df76 > >, std::__ndk1::__unordered_map_hasher > >, std::__ndk1::hash, std::__ndk1::equal_to, true>, std::__ndk1::__unordered_map_equal > >, std::__ndk1::equal_to, std::__ndk1::hash, true>, std::__ndk1::allocator > > > >::__erase_unique(Selection const&)@@Base+0xf6> │ │ + bl 21baf76 │ │ strh r2, [r1, #24] │ │ lsls r3, r5, #1 │ │ │ │ 0207f348 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -3750,15 +3750,15 @@ │ │ movs r1, #8 │ │ ldr r2, [r0, #0] │ │ ldr r2, [r2, #8] │ │ ldr.w r8, [sp], #4 │ │ ldmia.w sp!, {r4, r5, r6, r7, lr} │ │ bx r2 │ │ nop │ │ - ldrh r3, [r1, #18] │ │ + ldrh r0, [r7, #18] │ │ Address 0x207f75e is out of bounds. │ │ │ │ │ │ 0207f760 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -4035,15 +4035,15 @@ │ │ b.n 2080074 │ │ nop │ │ nop │ │ lsls r0, r0, #4 │ │ lsls r2, r0, #12 │ │ lsrs r4, r1, #20 │ │ lsrs r6, r1, #28 │ │ - lsrs r1, r5, #14 │ │ + lsrs r6, r2, #15 │ │ cdp2 15, 1, cr11, cr11, cr0, {0} │ │ nop │ │ str r5, [r0, #28] │ │ ldr r7, [pc, #124] @ (207fb60 ) │ │ lsrs r7, r7, #13 │ │ adcs r2, r4 │ │ movs r0, r0 │ │ @@ -5496,15 +5496,15 @@ │ │ blx r2 │ │ b.n 2080aea │ │ nop │ │ ldr r1, [sp, #616] @ 0x268 │ │ ldr r1, [sp, #612] @ 0x264 │ │ ldr r1, [sp, #612] @ 0x264 │ │ subs r7, #241 @ 0xf1 │ │ - strh r5, [r2, r6] │ │ + strh r2, [r0, r7] │ │ Address 0x2080c6a is out of bounds. │ │ │ │ │ │ 02080c6c : │ │ ldrb.w r0, [r0, #580] @ 0x244 │ │ bx lr │ │ │ │ @@ -5971,15 +5971,15 @@ │ │ ldr.w r0, [r5], #4 │ │ movs r2, #1 │ │ ldr r1, [r0, #0] │ │ ldr r3, [r1, #8] │ │ mov r1, r8 │ │ blx r3 │ │ b.n 20810d4 │ │ - cbz r7, 208112e │ │ + cbz r4, 208113a │ │ cdp2 12, 1, cr12, cr9, cr13, {6} │ │ subs r5, #76 @ 0x4c │ │ ldmia r4!, {r0, r2, r3, r6, r7} │ │ pop {r2, r3, r6, pc} │ │ nop │ │ nop │ │ ldmia r4!, {r2, r3, r6, r7} │ │ @@ -6380,21 +6380,21 @@ │ │ ldmia r4!, {r0, r2, r3, r6, r7} │ │ bkpt 0x004c │ │ strh r6, [r2, r4] │ │ cdp2 3, 1, cr6, cr9, cr0, {4} │ │ lsls r3, r5, #1 │ │ str r6, [r4, #100] @ 0x64 │ │ subs r7, #134 @ 0x86 │ │ - asrs r6, r5, #4 │ │ + asrs r3, r3, #5 │ │ cdp2 0, 1, cr0, cr10, cr0, {0} │ │ cmn r0, r1 │ │ str r2, [r1, #40] @ 0x28 │ │ lsls r3, r5, #1 │ │ - adds r1, #41 @ 0x29 │ │ - mrc2 0, 0, r1, cr10, cr4, {0} │ │ + adds r1, #86 @ 0x56 │ │ + cdp2 0, 1, cr1, cr10, cr1, {2} │ │ mrc2 1, 0, r6, cr10, cr0, {3} │ │ lsls r3, r5, #1 │ │ mov r0, r8 │ │ blx 27000b0 │ │ mov r0, r8 │ │ blx 2700210 │ │ ldr.w r0, [r8, #56] @ 0x38 │ │ @@ -6715,21 +6715,21 @@ │ │ vmov.f64 d16, #112 @ 0x3f800000 1.0 │ │ vmov r2, r3, d16 │ │ mov r0, r8 │ │ mov r1, r4 │ │ blx 2700120 │ │ b.w 2082b9e │ │ nop │ │ - cmp r7, #112 @ 0x70 │ │ - mrc2 7, 0, r4, cr10, cr15, {5} │ │ - cdp2 15, 1, cr6, cr11, cr13, {2} │ │ + cmp r7, #157 @ 0x9d │ │ + cdp2 7, 1, cr4, cr10, cr12, {7} │ │ + mrc2 15, 0, r6, cr11, cr10, {3} │ │ cdp2 4, 1, cr2, cr10, cr3, {2} │ │ cdp2 15, 1, cr9, cr12, cr12, {2} │ │ mrc2 14, 0, r9, cr12, cr7, {4} │ │ - mrc2 3, 0, r2, cr12, cr12, {7} │ │ + cdp2 4, 1, cr2, cr12, cr9, {1} │ │ vfmsl.f16 d6, s22, s5[0] │ │ lsls r3, r5, #1 │ │ mov r0, r8 │ │ blx 2700210 │ │ mov r0, r9 │ │ blx 27007d0 │ │ ldr r1, [pc, #792] @ (2081cf4 ) │ │ @@ -6999,24 +6999,24 @@ │ │ lsls r3, r5, #1 │ │ str r2, [r7, #92] @ 0x5c │ │ lsls r3, r5, #1 │ │ adds r3, #51 @ 0x33 │ │ subs r7, #115 @ 0x73 │ │ ldmia r4!, {r0, r2, r3, r6, r7} │ │ subs r5, #76 @ 0x4c │ │ - ldr r2, [pc, #956] @ (20820b0 ) │ │ - mrc2 12, 0, lr, cr10, cr15, {4} │ │ - cdp2 12, 1, cr14, cr9, cr15, {4} │ │ + ldr r3, [pc, #112] @ (2081d64 ) │ │ + cdp2 12, 1, cr14, cr10, cr12, {6} │ │ + mrc2 12, 0, lr, cr9, cr12, {5} │ │ mrc2 15, 0, r6, cr9, cr6, {1} │ │ mrc2 10, 0, sp, cr9, cr12, {1} @ │ │ movs r2, #56 @ 0x38 │ │ adds r2, r5, #5 │ │ asrs r2, r2 │ │ b.n 20824ca │ │ - mrc2 10, 0, r6, cr11, cr12, {4} @ │ │ + @ instruction: 0xfe1b6ac9 │ │ @ instruction: 0xfe1a3a65 │ │ cdp2 6, 1, cr6, cr12, cr6, {3} │ │ subs r7, #134 @ 0x86 │ │ mov r0, r8 │ │ blx 2700210 │ │ mov r0, r9 │ │ blx 27001b0 │ │ @@ -7793,35 +7793,35 @@ │ │ ldr r3, [r1, #8] │ │ mov r1, r8 │ │ blx r3 │ │ cmp r5, r4 │ │ bne.n 20825fc │ │ b.w 208102c │ │ nop │ │ - b.n 20828ec │ │ + b.n 2082946 │ │ cdp2 0, 1, cr0, cr10, cr0, {0} │ │ movs r0, r0 │ │ blt.n 20825d6 │ │ cdp2 3, 1, cr5, cr11, cr14, {3} │ │ lsls r3, r5, #1 │ │ ldmia r4!, {r0, r2, r3, r6, r7} │ │ pop {r2, r3, r6, r7, pc} │ │ - ldrsh r2, [r0, r0] │ │ + ldrsh r7, [r5, r0] │ │ mrc2 2, 0, r5, cr11, cr14, {6} │ │ lsls r3, r5, #1 │ │ qadd16 lr, r6, fp │ │ - @ instruction: 0xfbccfe1a │ │ - bkpt 0x006a │ │ + @ instruction: 0xfbf9fe1a │ │ + bkpt 0x0097 │ │ @ instruction: 0xfe19d9e3 │ │ mrc2 1, 0, r5, cr11, cr6, {3} │ │ lsls r3, r5, #1 │ │ strh r3, [r5, #12] │ │ cdp2 13, 1, cr7, cr9, cr8, {1} │ │ mrc2 1, 0, r9, cr11, cr6, {5} │ │ - mrc2 11, 0, r5, cr12, cr3, {4} @ │ │ + @ instruction: 0xfe1c5bc0 │ │ cdp2 12, 1, cr12, cr11, cr13, {6} │ │ subs r5, #204 @ 0xcc │ │ ldr.w r0, [r8, #20] │ │ blx 2700890 │ │ vmov.f32 s0, #40 @ 0x41400000 12.0 │ │ vmov s2, r0 │ │ vcmp.f32 s2, s0 │ │ @@ -8161,30 +8161,30 @@ │ │ ldr r3, [r1, #8] │ │ mov r1, r8 │ │ blx r3 │ │ cmp r5, r4 │ │ bne.n 2082a1c │ │ b.w 208102c │ │ nop │ │ - ldrh r2, [r3, r3] │ │ + ldrh r7, [r0, r4] │ │ mrc2 15, 0, r4, cr11, cr6, {5} │ │ lsls r3, r5, #1 │ │ ldrb r1, [r7, #29] │ │ cdp2 15, 1, cr2, cr9, cr3, {5} │ │ cdp2 14, 1, cr4, cr12, cr4, {7} │ │ lsls r3, r5, #1 │ │ lsrs r2, r3, #6 │ │ adcs.w r5, r1, #260096 @ 0x3f800 │ │ cmp r1, r4 │ │ ldr r6, [pc, #664] @ (2082cec ) │ │ lsls r3, r5, #1 │ │ ldr r3, [r7, #76] @ 0x4c │ │ cdp2 6, 1, cr13, cr12, cr0, {0} │ │ vfmsl.f16 , d11, d0[1] │ │ - mrc2 11, 0, r3, cr9, cr12, {6} @ │ │ + cdp2 12, 1, cr3, cr9, cr9, {0} │ │ mrc2 9, 0, ip, cr10, cr15, {7} @ │ │ cdp2 13, 1, cr4, cr12, cr2, {1} │ │ lsls r3, r5, #1 │ │ asrs r0, r2, #29 │ │ vfmsl.f16 , d25, d0[1] │ │ movs r4, r2 │ │ movs r1, #2 │ │ @@ -8441,17 +8441,17 @@ │ │ ldrb.w r0, [sp, #112] @ 0x70 │ │ lsls r0, r0, #31 │ │ bne.n 2082d2e │ │ blx 26ffb60 │ │ ldr r0, [sp, #120] @ 0x78 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ - bls.n 2082d42 │ │ - mrc2 9, 0, r3, cr10, cr9, {2} @ │ │ - cdp2 5, 1, cr5, cr10, cr9, {7} │ │ + bls.n 2082d9c │ │ + vselvs.f16 s6, s21, s12 │ │ + mrc2 6, 0, r5, cr10, cr6, {0} │ │ mrc2 3, 0, sp, cr11, cr9, {0} │ │ mrc2 12, 0, r7, cr11, cr0, {1} │ │ vfmsl.f16 , d9, d2[3] │ │ cdp2 2, 1, cr13, cr11, cr6, {6} │ │ vselvs.f32 s8, s23, s9 │ │ lsls r3, r5, #1 │ │ stmia r6!, {r0, r1, r3, r4, r5, r6, r7} │ │ @@ -8597,16 +8597,16 @@ │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ mov r0, r4 │ │ bl 207d3d8 │ │ ldr r0, [pc, #200] @ (2082f88 , std::__ndk1::allocator > const&, double)@@Base+0x90>) │ │ lsls r3, r5, #1 │ │ - cbz r5, 2082f20 , std::__ndk1::allocator > const&, double)@@Base+0x28> │ │ - mrc2 14, 0, r0, cr10, cr0, {5} │ │ + cbz r2, 2082f2c , std::__ndk1::allocator > const&, double)@@Base+0x34> │ │ + mrc2 14, 0, r0, cr10, cr13, {6} │ │ cdp2 7, 1, cr4, cr11, cr12, {4} │ │ lsls r3, r5, #1 │ │ │ │ 02082ecc : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -8892,15 +8892,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ cmp r2, sp │ │ lsls r3, r5, #1 │ │ - strb r3, [r7, #17] │ │ + strb r0, [r5, #18] │ │ mrc2 4, 0, r4, cr10, cr4, {3} │ │ lsls r3, r5, #1 │ │ strh r5, [r4, #50] @ 0x32 │ │ Address 0x20831f6 is out of bounds. │ │ │ │ │ │ 020831f8 : │ │ @@ -9478,15 +9478,15 @@ │ │ b.n 208377c >)@@Base+0x118> │ │ add r0, sp, #16 │ │ blx 26ffd80 │ │ blx 26ffb60 │ │ nop │ │ subs r7, #174 @ 0xae │ │ lsls r3, r5, #1 │ │ - movs r7, #177 @ 0xb1 │ │ + movs r7, #222 @ 0xde │ │ cdp2 14, 1, cr3, cr11, cr8, {7} │ │ lsls r3, r5, #1 │ │ │ │ 02083794 , std::__ndk1::allocator > const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -9576,15 +9576,15 @@ │ │ ittt eq │ │ addeq sp, #16 │ │ ldmiaeq.w sp!, {r8, r9, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ subs r6, #132 @ 0x84 │ │ lsls r3, r5, #1 │ │ - add r2, sp, #856 @ 0x358 │ │ + add r3, sp, #12 │ │ cdp2 13, 1, cr3, cr9, cr10, {6} │ │ lsls r3, r5, #1 │ │ │ │ 02083884 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ @@ -10646,15 +10646,15 @@ │ │ ldr.w r8, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ adds r3, #51 @ 0x33 │ │ rors r3, r1 │ │ movs r0, r0 │ │ negs r4, r2 │ │ - bl 1ffb2b4 │ │ + bl 20282b4 │ │ │ │ 02084680 : │ │ movs r0, #1 │ │ bx lr │ │ │ │ 02084684 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -10800,15 +10800,15 @@ │ │ movs r3, #34 @ 0x22 │ │ strd r5, r5, [sp] │ │ blx 26ffe60 │ │ b.n 20847c8 │ │ nop │ │ cmp r7, #148 @ 0x94 │ │ lsls r3, r5, #1 │ │ - bkpt 0x0076 │ │ + bkpt 0x00a3 │ │ mrc2 14, 0, r2, cr9, cr12, {2} │ │ lsls r3, r5, #1 │ │ │ │ 02084820 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ @@ -10833,15 +10833,15 @@ │ │ strd r1, lr, [sp, #8] │ │ add.w r1, r4, #24 │ │ strd ip, r5, [sp] │ │ blx 2700bd0 │ │ add sp, #16 │ │ pop {r4, r5, r7, pc} │ │ nop │ │ - bl 1d274a0 │ │ + bl 1d544a0 │ │ │ │ 0208486c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #8 │ │ mov r6, r0 │ │ @@ -11205,21 +11205,21 @@ │ │ ldr r1, [r1, #0] │ │ cmp r1, r0 │ │ itt eq │ │ addeq sp, #24 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ - cbnz r7, 2084c14 > const&, ProgressNotifier*)@@Base+0x2c> │ │ + cbnz r4, 2084c20 > const&, ProgressNotifier*)@@Base+0x38> │ │ @ instruction: 0xfe192ac8 │ │ lsls r3, r5, #1 │ │ - cbnz r1, 2084c18 > const&, ProgressNotifier*)@@Base+0x30> │ │ + cbnz r6, 2084c22 > const&, ProgressNotifier*)@@Base+0x3a> │ │ @ instruction: 0xfe192aec │ │ lsls r3, r5, #1 │ │ - subs r3, #30 │ │ + subs r3, #75 @ 0x4b │ │ mrc2 4, 0, r7, cr10, cr10, {4} │ │ mrc2 10, 0, r2, cr11, cr4, {3} @ │ │ lsls r3, r5, #1 │ │ │ │ 02084be8 > const&, ProgressNotifier*)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -11646,15 +11646,15 @@ │ │ b.n 208509e > const&, ProgressNotifier*)@@Base+0x4b6> │ │ bl 1d47c9c │ │ cmp r1, #160 @ 0xa0 │ │ lsls r3, r5, #1 │ │ str r5, [sp, #660] @ 0x294 │ │ mrc2 3, 0, pc, cr11, cr11, {7} │ │ mrc2 7, 0, r4, cr8, cr12, {6} │ │ - cdp2 0, 1, cr1, cr12, cr8, {4} │ │ + mrc2 0, 0, r1, cr12, cr5, {5} │ │ mrc2 9, 0, r6, cr11, cr10, {1} @ │ │ cdp2 7, 1, cr2, cr12, cr14, {3} │ │ lsls r3, r5, #1 │ │ movs r0, r0 │ │ movs r0, r0 │ │ adds r0, r0, r0 │ │ lsrs r5, r6 │ │ @@ -12029,24 +12029,24 @@ │ │ ldr r2, [r1, #8] │ │ add r1, sp, #80 @ 0x50 │ │ blx r2 │ │ b.n 20854fc > const&, ProgressNotifier*)@@Base+0x914> │ │ nop │ │ movs r5, #110 @ 0x6e │ │ lsls r3, r5, #1 │ │ - ldrh r0, [r7, #58] @ 0x3a │ │ + ldrh r5, [r4, #60] @ 0x3c │ │ mrc2 4, 0, r2, cr10, cr0, {3} │ │ lsls r3, r5, #1 │ │ movs r0, r0 │ │ orrs r4, r6 │ │ adc.w r0, sl, #15400960 @ 0xeb0000 │ │ adc.w r0, r4, #15400960 @ 0xeb0000 │ │ lsrs r3, r3, #31 │ │ eors r1, r1 │ │ - ldr r1, [r1, #100] @ 0x64 │ │ + ldr r6, [r6, #100] @ 0x64 │ │ mrc2 15, 0, r9, cr9, cr9, {1} │ │ cdp2 1, 1, cr1, cr12, cr12, {6} │ │ mrc2 2, 0, pc, cr9, cr10, {3} │ │ b.n 2084e32 > const&, ProgressNotifier*)@@Base+0x24a> │ │ mov r4, r0 │ │ ldr r0, [r0, #8] │ │ cmp r0, #0 │ │ @@ -12442,15 +12442,15 @@ │ │ subs r7, #52 @ 0x34 │ │ vfmsl.f16 q5, d12, d6[3] │ │ cdp2 12, 1, cr4, cr11, cr11, {1} │ │ cdp2 15, 1, cr1, cr11, cr6, {7} │ │ lsls r3, r5, #1 │ │ subs r2, r4, #6 │ │ lsls r3, r5, #1 │ │ - cmp r2, #18 │ │ + cmp r2, #63 @ 0x3f │ │ vselvs.f32 s4, s22, s17 │ │ lsls r3, r5, #1 │ │ ldrd r2, r1, [r0, #184] @ 0xb8 │ │ add r0, sp, #80 @ 0x50 │ │ bl 207d390 │ │ add r1, sp, #80 @ 0x50 │ │ mov r0, r4 │ │ @@ -12642,26 +12642,26 @@ │ │ lsrs r2, r0, #25 │ │ vselvs.f16 s28, s18, s5 │ │ cdp2 13, 1, cr1, cr8, cr10, {6} │ │ lsls r3, r5, #1 │ │ ldrb r2, [r3, #29] │ │ mrc2 0, 0, r3, cr12, cr1, {3} │ │ mrc2 14, 0, r7, cr9, cr6, {5} │ │ - mrc2 10, 0, sl, cr12, cr1, {4} @ │ │ - mrc2 10, 0, sl, cr10, cr6, {3} @ │ │ + mrc2 10, 0, sl, cr12, cr14, {5} @ │ │ + vselvs.f32 s20, s21, s7 │ │ mrc2 3, 0, r2, cr10, cr3, {0} │ │ mrc2 11, 0, r3, cr12, cr10, {3} @ │ │ - mrc2 12, 0, sl, cr12, cr7, {3} │ │ - mrc2 12, 0, r6, cr9, cr13, {6} │ │ + cdp2 12, 1, cr10, cr12, cr4, {5} │ │ + cdp2 13, 1, cr6, cr9, cr10, {0} │ │ vcmla.f16 q2, q5, d11[0], #90 │ │ cdp2 12, 1, cr4, cr11, cr6, {3} │ │ cdp2 12, 1, cr4, cr9, cr4, {2} │ │ cdp2 5, 1, cr6, cr9, cr4, {3} │ │ cdp2 5, 1, cr6, cr11, cr6, {2} │ │ - mrc2 9, 0, r0, cr11, cr14, {4} @ │ │ + @ instruction: 0xfe1b09cb │ │ cdp2 0, 1, cr2, cr10, cr2, {0} │ │ str.w r0, [sl, #704] @ 0x2c0 │ │ ldr.w r3, [sl] │ │ ldrb.w r0, [r3, #776] @ 0x308 │ │ ldr.w r1, [r3, #780] @ 0x30c │ │ lsls r6, r0, #31 │ │ it eq │ │ @@ -12966,18 +12966,18 @@ │ │ add r0, sp, #80 @ 0x50 │ │ blx 26ffe80 │ │ blx 26ffb60 │ │ bl 207deaa │ │ nop │ │ movs r2, #70 @ 0x46 │ │ lsls r3, r5, #1 │ │ - @ instruction: 0xea00fe19 │ │ + @ instruction: 0xea2dfe19 │ │ cmp r5, #196 @ 0xc4 │ │ vselvs.f16 s6, s19, s7 │ │ - vfmsl.f16 q7, d28, d0[0] │ │ + vfmsl.f16 q7, d28, d5[3] │ │ cdp2 4, 1, cr14, cr9, cr9, {1} │ │ Address 0x2085ee6 is out of bounds. │ │ │ │ │ │ 02085ee8 : │ │ mov r2, r1 │ │ ldr r1, [r0, #0] │ │ @@ -13096,15 +13096,15 @@ │ │ b.n 2086006 │ │ b.n 2086006 │ │ add r0, sp, #20 │ │ blx 26ffe80 │ │ blx 26ffb60 │ │ asrs r0, r5, #28 │ │ lsls r3, r5, #1 │ │ - stmia r5!, {r3, r5, r6, r7} │ │ + stmia r6!, {r0, r2, r4} │ │ mrc2 7, 0, r1, cr9, cr10, {0} │ │ lsls r3, r5, #1 │ │ asrs r4, r6, #26 │ │ lsls r3, r5, #1 │ │ asrs r6, r0, #25 │ │ lsls r3, r5, #1 │ │ push {r4, r5, r6, r7, lr} │ │ @@ -13777,15 +13777,15 @@ │ │ bl 208686a │ │ b.n 20866ce │ │ add r0, sp, #72 @ 0x48 │ │ bl 2086830 │ │ blx 26ffb60 │ │ asrs r2, r6, #11 │ │ lsls r3, r5, #1 │ │ - bls.n 20866e0 │ │ + bls.n 208673a │ │ mrc2 15, 0, r0, cr10, cr8, {5} │ │ lsls r3, r5, #1 │ │ ldr r2, [sp, #648] @ 0x288 │ │ cdp2 12, 1, cr13, cr11, cr5, {3} │ │ mrc2 1, 0, r1, cr8, cr2, {3} │ │ lsls r3, r5, #1 │ │ push {r4, r5, r6, r7, lr} │ │ @@ -13909,15 +13909,15 @@ │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ lsrs r2, r5, #28 │ │ lsls r3, r5, #1 │ │ lsrs r2, r4, #25 │ │ lsls r3, r5, #1 │ │ - ldr r5, [sp, #80] @ 0x50 │ │ + ldr r5, [sp, #260] @ 0x104 │ │ mrc2 5, 0, fp, cr10, cr0, {5} │ │ add r7, sp, #8 │ │ ldr r4, [r0, #4] │ │ cbz r4, 2086868 │ │ adds r1, r4, #4 │ │ dmb ish │ │ ldrex r2, [r1] │ │ @@ -14898,20 +14898,20 @@ │ │ lsrs r2, r4, #32 │ │ lsls r3, r5, #1 │ │ bcs.n 20870bc , std::__ndk1::allocator > const&, Selection)@@Base+0x2c4> │ │ cdp2 5, 1, cr0, cr8, cr2, {4} │ │ lsls r3, r5, #1 │ │ subs r0, #18 │ │ mrc2 3, 0, r3, cr9, cr14, {7} │ │ - mrc2 13, 0, ip, cr11, cr0, {6} │ │ - mrc2 15, 0, lr, cr10, cr11, {1} │ │ - mrc2 1, 0, r7, cr10, cr14, {7} │ │ - mrc2 5, 0, fp, cr10, cr0, {2} │ │ - cdp2 14, 1, cr14, cr9, cr9, {5} │ │ - cdp2 14, 1, cr14, cr10, cr11, {2} │ │ + mrc2 13, 0, ip, cr11, cr13, {7} │ │ + cdp2 15, 1, cr14, cr10, cr8, {3} │ │ + cdp2 2, 1, cr7, cr10, cr11, {1} │ │ + mrc2 5, 0, fp, cr10, cr13, {3} │ │ + mrc2 14, 0, lr, cr9, cr6, {6} │ │ + mrc2 14, 0, lr, cr10, cr8, {3} │ │ mrc2 5, 0, fp, cr10, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ mov r4, r0 │ │ movs r0, #52 @ 0x34 │ │ mov r6, r1 │ │ blx 26ffbf0 │ │ @@ -16763,15 +16763,15 @@ │ │ orn r0, r0, #15335424 @ 0xea0000 │ │ bic.w r0, r8, #15335424 @ 0xea0000 │ │ @ instruction: 0xf3d6006a │ │ @ instruction: 0xf3ba006a │ │ @ instruction: 0xf38c006a │ │ @ instruction: 0xf35a006a │ │ @ instruction: 0xf4b6006a │ │ - ldrsh r1, [r1, r7] │ │ + ldrsh r6, [r6, r7] │ │ cdp2 3, 1, cr15, cr10, cr4, {2} │ │ lsls r2, r5, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ ldr r4, [r0, #0] │ │ movs r1, #0 │ │ @@ -17587,17 +17587,17 @@ │ │ beq.n 2088b6e ::format_custom_arg >(void*, fmt::v11::basic_format_parse_context&, fmt::v11::context&)@@Base+0x4e6> │ │ ldr r0, [pc, #12] @ (2088b94 ::format_custom_arg >(void*, fmt::v11::basic_format_parse_context&, fmt::v11::context&)@@Base+0x50c>) │ │ add r0, pc │ │ bl 221a388 │ │ ldr r0, [pc, #16] @ (2088ba0 ::format_custom_arg >(void*, fmt::v11::basic_format_parse_context&, fmt::v11::context&)@@Base+0x518>) │ │ add r0, pc │ │ bl 221a388 │ │ - smmlsr lr, r7, r9, pc @ │ │ + @ instruction: 0xfb94fe19 │ │ str r5, [sp, #548] @ 0x224 │ │ - mrc2 10, 0, sp, cr8, cr10, {2} @ │ │ + vselvs.f32 s26, s17, s14 │ │ mrc2 10, 0, sp, cr9, cr5, {4} @ │ │ mrc2 5, 0, fp, cr8, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #16 │ │ ldr r5, [pc, #236] @ (2088c9c ::format_custom_arg >(void*, fmt::v11::basic_format_parse_context&, fmt::v11::context&)@@Base+0x614>) │ │ add r5, pc │ │ @@ -17692,19 +17692,19 @@ │ │ add r0, pc │ │ bl 221a388 │ │ ldr r0, [pc, #20] @ (2088ca8 ::format_custom_arg >(void*, fmt::v11::basic_format_parse_context&, fmt::v11::context&)@@Base+0x620>) │ │ add r0, pc │ │ bl 221a388 │ │ nop │ │ orns r0, ip, sl, asr #1 │ │ - ldrb r4, [r2, #10] │ │ + ldrb r1, [r0, #11] │ │ mrc2 9, 0, lr, cr9, cr10, {5} @ │ │ lsls r2, r5, #1 │ │ - qadd8 lr, r4, r9 │ │ - strb r4, [r2, r4] │ │ + @ instruction: 0xfab1fe19 │ │ + strb r1, [r0, r5] │ │ mrc2 5, 0, fp, cr10, cr0, {7} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ ldrb r3, [r0, #0] │ │ sub.w r6, r3, #48 @ 0x30 │ │ cmp r6, #9 │ │ bhi.n 2088cd0 ::format_custom_arg >(void*, fmt::v11::basic_format_parse_context&, fmt::v11::context&)@@Base+0x648> │ │ @@ -17797,16 +17797,16 @@ │ │ ldr r0, [pc, #20] @ (2088dc0 ::format_custom_arg >(void*, fmt::v11::basic_format_parse_context&, fmt::v11::context&)@@Base+0x738>) │ │ add r0, pc │ │ bl 221a388 │ │ ldr r0, [pc, #8] @ (2088dbc ::format_custom_arg >(void*, fmt::v11::basic_format_parse_context&, fmt::v11::context&)@@Base+0x734>) │ │ add r0, pc │ │ bl 221a388 │ │ nop │ │ - asrs r4, r0, #31 │ │ - mrc2 3, 0, r5, cr10, cr4, {7} │ │ + asrs r1, r6, #31 │ │ + cdp2 4, 1, cr5, cr10, cr1, {1} │ │ Address 0x2088dc2 is out of bounds. │ │ │ │ │ │ 02088dc4 >, char, void>::format(std::__ndk1::basic_string_view >, fmt::v11::context&) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ @@ -17952,15 +17952,15 @@ │ │ ldr r0, [pc, #12] @ (2088f3c >, char, void>::format(std::__ndk1::basic_string_view >, fmt::v11::context&) const@@Base+0x178>) │ │ add r0, pc │ │ bl 221a388 │ │ b.n 2088e68 >, char, void>::format(std::__ndk1::basic_string_view >, fmt::v11::context&) const@@Base+0xa4> │ │ lsls r2, r5, #1 │ │ b.n 2088d68 ::format_custom_arg >(void*, fmt::v11::basic_format_parse_context&, fmt::v11::context&)@@Base+0x6e0> │ │ lsls r2, r5, #1 │ │ - strh r3, [r2, r6] │ │ + strh r0, [r0, r7] │ │ mrc2 5, 0, fp, cr9, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #24 │ │ mov r6, r0 │ │ ldr r0, [pc, #160] @ (2088ff0 >, char, void>::format(std::__ndk1::basic_string_view >, fmt::v11::context&) const@@Base+0x22c>) │ │ cmp r1, #2 │ │ @@ -18026,15 +18026,15 @@ │ │ ldr r0, [pc, #12] @ (2088ff8 >, char, void>::format(std::__ndk1::basic_string_view >, fmt::v11::context&) const@@Base+0x234>) │ │ add r0, pc │ │ bl 221a388 │ │ b.n 2088dac ::format_custom_arg >(void*, fmt::v11::basic_format_parse_context&, fmt::v11::context&)@@Base+0x724> │ │ lsls r2, r5, #1 │ │ b.n 2088cac ::format_custom_arg >(void*, fmt::v11::basic_format_parse_context&, fmt::v11::context&)@@Base+0x624> │ │ lsls r2, r5, #1 │ │ - strh r7, [r2, r3] │ │ + strh r4, [r0, r4] │ │ mrc2 5, 0, fp, cr9, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #52 @ 0x34 │ │ mov r8, r0 │ │ ldr r0, [pc, #340] @ (2089160 >, char, void>::format(std::__ndk1::basic_string_view >, fmt::v11::context&) const@@Base+0x39c>) │ │ mov r4, r3 │ │ @@ -19784,16 +19784,16 @@ │ │ ldr r0, [pc, #16] @ (208a170 )#1}>(fmt::v11::basic_string_view, fmt::v11::detail::find_escape(char const*, char const*)::{lambda(unsigned int, fmt::v11::basic_string_view)#1})::{lambda(char const*, char const*)#1}::operator()(char const*, char const*) const@@Base+0xa00>) │ │ add r0, pc │ │ bl 221a388 │ │ ldr r0, [pc, #12] @ (208a174 )#1}>(fmt::v11::basic_string_view, fmt::v11::detail::find_escape(char const*, char const*)::{lambda(unsigned int, fmt::v11::basic_string_view)#1})::{lambda(char const*, char const*)#1}::operator()(char const*, char const*) const@@Base+0xa04>) │ │ add r0, pc │ │ bl 221a388 │ │ adcs r4, r4 │ │ - mrc2 11, 0, r9, cr11, cr7, {5} @ │ │ - mrc2 5, 0, r6, cr10, cr14, {1} │ │ + @ instruction: 0xfe1b9be4 │ │ + cdp2 5, 1, cr6, cr10, cr11, {3} │ │ mrc2 5, 0, fp, cr9, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #20 │ │ strd r1, r0, [sp, #12] │ │ ldr r0, [r1, #4] │ │ lsls r1, r0, #1 │ │ @@ -19920,17 +19920,17 @@ │ │ pop {r7, pc} │ │ ldr r0, [pc, #16] @ (208a2d8 )#1}>(fmt::v11::basic_string_view, fmt::v11::detail::find_escape(char const*, char const*)::{lambda(unsigned int, fmt::v11::basic_string_view)#1})::{lambda(char const*, char const*)#1}::operator()(char const*, char const*) const@@Base+0xb68>) │ │ add r0, pc │ │ bl 221a388 │ │ ldr r0, [pc, #12] @ (208a2dc )#1}>(fmt::v11::basic_string_view, fmt::v11::detail::find_escape(char const*, char const*)::{lambda(unsigned int, fmt::v11::basic_string_view)#1})::{lambda(char const*, char const*)#1}::operator()(char const*, char const*) const@@Base+0xb6c>) │ │ add r0, pc │ │ bl 221a388 │ │ - stmia r2!, {r1, r2, r3, r6} │ │ - cdp2 1, 1, cr6, cr9, cr5, {3} │ │ - mrc2 3, 0, r6, cr10, cr6, {6} │ │ + stmia r2!, {r0, r1, r3, r4, r5, r6} │ │ + mrc2 1, 0, r6, cr9, cr2, {4} │ │ + cdp2 4, 1, cr6, cr10, cr3, {0} │ │ cdp2 5, 1, cr11, cr9, cr0, {4} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (208a2ec )#1}>(fmt::v11::basic_string_view, fmt::v11::detail::find_escape(char const*, char const*)::{lambda(unsigned int, fmt::v11::basic_string_view)#1})::{lambda(char const*, char const*)#1}::operator()(char const*, char const*) const@@Base+0xb7c>) │ │ add r0, pc │ │ bl 207d3e8 │ │ ldrb r4, [r2, r0] │ │ mrc2 5, 0, fp, cr11, cr0, {7} │ │ @@ -36225,15 +36225,15 @@ │ │ ldr r2, [pc, #12] @ (2095ac8 ) │ │ add r2, pc │ │ add r0, sp, #240 @ 0xf0 │ │ mov r1, fp │ │ movs r3, #12 │ │ blx 2701cc0 │ │ b.n 2095acc │ │ - ldr r5, [r6, #68] @ 0x44 │ │ + ldr r2, [r4, #72] @ 0x48 │ │ vfmsl.f16 d15, s19, s10[1] │ │ lsls r4, r7, #3 │ │ cbz r0, 2095af0 │ │ add r1, sp, #240 @ 0xf0 │ │ mov r0, r6 │ │ blx 26ffb20 │ │ ldrb.w r0, [sp, #252] @ 0xfc │ │ @@ -36246,15 +36246,15 @@ │ │ ldr r2, [pc, #12] @ (2095b00 ) │ │ add r2, pc │ │ add r0, sp, #240 @ 0xf0 │ │ mov r1, fp │ │ movs r3, #16 │ │ blx 2701cc0 │ │ b.n 2095b04 │ │ - strh r2, [r4, #62] @ 0x3e │ │ + ldrh r7, [r1, #0] │ │ vfmsl.f16 d15, s17, s10[1] │ │ lsls r4, r7, #3 │ │ cbz r0, 2095b2a │ │ add.w r0, r6, #12 │ │ add r1, sp, #240 @ 0xf0 │ │ blx 26ffb20 │ │ ldrb.w r0, [sp, #252] @ 0xfc │ │ @@ -36267,15 +36267,15 @@ │ │ ldr r2, [pc, #16] @ (2095b3c ) │ │ add r2, pc │ │ add.w r0, r6, #24 │ │ mov r1, fp │ │ movs r3, #19 │ │ bl 20965f4 │ │ b.n 2095b40 │ │ - ldmia r2!, {r4} │ │ + ldmia r2, {r0, r2, r3, r4, r5} │ │ vselvs.f32 s8, s16, s8 │ │ add r2, pc │ │ add.w r0, r6, #36 @ 0x24 │ │ mov r1, fp │ │ movs r3, #12 │ │ bl 20965f4 │ │ b.n 2095b58 │ │ @@ -36311,15 +36311,15 @@ │ │ vselvs.f32 s8, s20, s6 │ │ add r2, pc │ │ add r0, sp, #240 @ 0xf0 │ │ mov r1, fp │ │ movs r3, #13 │ │ blx 2701cc0 │ │ b.n 2095bb4 │ │ - lsrs r7, r4, #5 │ │ + lsrs r4, r2, #6 │ │ vfmsl.f16 d15, s19, s10[1] │ │ lsls r4, r7, #3 │ │ cbz r0, 2095bda │ │ add.w r0, r6, #84 @ 0x54 │ │ add r1, sp, #240 @ 0xf0 │ │ blx 26ffb20 │ │ ldrb.w r0, [sp, #252] @ 0xfc │ │ @@ -36333,15 +36333,15 @@ │ │ add r2, pc │ │ add r0, sp, #240 @ 0xf0 │ │ mov r1, fp │ │ movs r3, #14 │ │ blx 2701cc0 │ │ b.n 2095bf0 │ │ nop │ │ - add r0, sp, #440 @ 0x1b8 │ │ + add r0, sp, #620 @ 0x26c │ │ vfmsl.f16 d15, s19, s10[1] │ │ lsls r4, r7, #3 │ │ cbz r0, 2095c16 │ │ add.w r0, r6, #96 @ 0x60 │ │ add r1, sp, #240 @ 0xf0 │ │ blx 26ffb20 │ │ ldrb.w r0, [sp, #252] @ 0xfc │ │ @@ -36756,38 +36756,38 @@ │ │ ldrb.w r0, [sp, #248] @ 0xf8 │ │ cmp r0, #0 │ │ beq.n 2096138 │ │ vldr d16, [sp, #240] @ 0xf0 │ │ vcvt.f32.f64 s0, d16 │ │ vstr s0, [r6, #332] @ 0x14c │ │ b.n 209613c │ │ - lsrs r7, r1, #32 │ │ - vselvs.f16 s20, s19, s18 │ │ - mrc2 7, 0, r0, cr8, cr4, {5} │ │ + lsrs r4, r7, #32 │ │ + mrc2 9, 0, sl, cr9, cr6, {5} @ │ │ + cdp2 7, 1, cr0, cr8, cr1, {7} │ │ cdp2 0, 1, cr12, cr9, cr8, {6} │ │ mrc2 5, 0, r4, cr10, cr5, {0} │ │ - mrc2 9, 0, r6, cr10, cr0, {1} @ │ │ + mrc2 9, 0, r6, cr10, cr13, {2} @ │ │ mrc2 7, 0, r0, cr9, cr14, {7} │ │ vfmsl.f16 , d24, d7[1] │ │ - mrc2 14, 0, sp, cr10, cr5, {4} │ │ - mrc2 2, 0, r8, cr9, cr10, {6} │ │ - vfmsl.f16 q3, d9, d0[0] │ │ + cdp2 14, 1, cr13, cr10, cr2, {6} │ │ + cdp2 3, 1, cr8, cr9, cr7, {0} │ │ + vfmsl.f16 q3, d9, d5[3] │ │ @ instruction: 0xfe19796b │ │ - mrc2 7, 0, sl, cr11, cr15, {4} │ │ - cdp2 6, 1, cr14, cr8, cr2, {4} │ │ - cdp2 5, 1, cr0, cr8, cr13, {6} │ │ + cdp2 7, 1, cr10, cr11, cr12, {6} │ │ + cdp2 6, 1, cr14, cr8, cr15, {5} │ │ + mrc2 5, 0, r0, cr8, cr10, {7} │ │ cdp2 3, 1, cr4, cr9, cr11, {4} │ │ - cdp2 6, 1, cr14, cr10, cr5, {2} │ │ - cdp2 3, 1, cr8, cr8, cr13, {1} │ │ + mrc2 6, 0, lr, cr10, cr2, {3} │ │ + mrc2 3, 0, r8, cr8, cr10, {2} │ │ mrc2 7, 0, r5, cr8, cr14, {6} │ │ - cdp2 4, 1, cr10, cr11, cr3, {3} │ │ + mrc2 4, 0, sl, cr11, cr0, {4} │ │ cdp2 14, 1, cr11, cr9, cr6, {3} │ │ - cdp2 2, 1, cr8, cr10, cr2, {6} │ │ - cdp2 6, 1, cr10, cr8, cr15, {4} │ │ - mrc2 3, 0, sl, cr8, cr5, {7} │ │ + cdp2 2, 1, cr8, cr10, cr15, {7} │ │ + mrc2 6, 0, sl, cr8, cr12, {5} │ │ + cdp2 4, 1, cr10, cr8, cr2, {1} │ │ cdp2 2, 1, cr15, cr9, cr9, {3} │ │ b.n 2095e32 │ │ mov r6, r0 │ │ ldr r0, [r0, #8] │ │ cmp r0, #0 │ │ bmi.w 20964f6 │ │ ldr r0, [pc, #712] @ (20963d0 ) │ │ @@ -37057,15 +37057,15 @@ │ │ bl 2096a9c , std::__ndk1::allocator >* std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > >::__emplace_back_slow_path, std::__ndk1::allocator > const&>(std::__ndk1::basic_string, std::__ndk1::allocator > const&)@@Base+0x1b0> │ │ b.n 209640c │ │ adds r4, #148 @ 0x94 │ │ mrc2 5, 0, r1, cr11, cr2, {2} │ │ lsls r2, r5, #1 │ │ adds r4, #132 @ 0x84 │ │ mrc2 10, 0, sp, cr11, cr8, {4} @ │ │ - mrc2 5, 0, sl, cr10, cr3, {3} │ │ + cdp2 5, 1, cr10, cr10, cr0, {5} │ │ cdp2 2, 1, cr15, cr8, cr9, {3} │ │ b.n 2095e32 │ │ ldr r1, [r0, #8] │ │ cmp r1, #0 │ │ bmi.n 209640c │ │ ldr r2, [pc, #392] @ (2096578 ) │ │ movs r1, #12 │ │ @@ -37208,46 +37208,46 @@ │ │ add r0, sp, #60 @ 0x3c │ │ blx 26ffe80 │ │ blx 26ffb60 │ │ adds r6, r7, #3 │ │ lsls r2, r5, #1 │ │ subs r6, r2, r7 │ │ lsls r2, r5, #1 │ │ - ldrsh r2, [r0, r6] │ │ - mrc2 3, 0, r4, cr8, cr15, {4} │ │ - mrc2 4, 0, r2, cr9, cr9, {7} │ │ + ldrsh r7, [r5, r6] │ │ + cdp2 3, 1, cr4, cr8, cr12, {6} │ │ + cdp2 5, 1, cr2, cr9, cr6, {1} │ │ cdp2 12, 1, cr5, cr9, cr14, {4} │ │ - @ instruction: 0xfe1adac7 │ │ + mrc2 10, 0, sp, cr10, cr4, {7} @ │ │ cdp2 0, 1, cr4, cr9, cr6, {4} │ │ - mrc2 4, 0, r2, cr10, cr14, {5} │ │ + cdp2 4, 1, cr2, cr10, cr11, {7} │ │ mrc2 13, 0, r5, cr9, cr1, {7} │ │ - vselvs.f32 s26, s21, s18 │ │ + mrc2 10, 0, sp, cr10, cr6, {5} @ │ │ mrc2 3, 0, r0, cr9, cr3, {3} │ │ - mrc2 2, 0, ip, cr8, cr0, {3} │ │ - cdp2 2, 1, cr0, cr8, cr14, {2} │ │ - mrc2 2, 0, ip, cr9, cr2, {2} │ │ + mrc2 2, 0, ip, cr8, cr13, {4} │ │ + mrc2 2, 0, r0, cr8, cr11, {3} │ │ + mrc2 2, 0, ip, cr9, cr15, {3} │ │ @ instruction: 0xfe1819ed │ │ mrc2 6, 0, r2, cr11, cr10, {4} │ │ - mrc2 14, 0, r1, cr8, cr14, {3} │ │ - cdp2 3, 1, cr10, cr10, cr12, {6} │ │ + cdp2 14, 1, cr1, cr8, cr11, {5} │ │ + mrc2 3, 0, sl, cr10, cr9, {7} │ │ cdp2 5, 1, cr7, cr8, cr8, {2} │ │ - mrc2 3, 0, r6, cr11, cr7, {7} │ │ + cdp2 4, 1, cr6, cr11, cr4, {1} │ │ mrc2 14, 0, sp, cr9, cr3, {4} │ │ - @ instruction: 0xfe17d9cb │ │ + mrc2 9, 0, sp, cr7, cr8, {7} @ │ │ mrc2 12, 0, r5, cr9, cr8, {5} │ │ vcmla.f16 , q5, d12[1], #90 │ │ cdp2 2, 1, cr3, cr10, cr9, {0} │ │ mrc2 4, 0, r7, cr11, cr12, {6} │ │ - cdp2 2, 1, cr10, cr11, cr8, {5} │ │ + mrc2 2, 0, sl, cr11, cr5, {6} │ │ mrc2 10, 0, r9, cr8, cr11, {6} @ │ │ mrc2 15, 0, r8, cr10, cr14, {0} │ │ - vfmsl.f16 , d27, d4[0] │ │ - cdp2 1, 1, cr14, cr9, cr14, {2} │ │ + vselvs.f16 s26, s22, s2 │ │ + mrc2 1, 0, lr, cr9, cr11, {3} │ │ cdp2 14, 1, cr8, cr8, cr9, {7} │ │ - mrc2 9, 0, pc, cr11, cr4, {7} @ │ │ + vselvs.f32 s30, s22, s3 │ │ mrc2 13, 0, sp, cr9, cr4, {1} │ │ mrc2 2, 0, pc, cr7, cr13, {3} │ │ mrc2 5, 0, fp, cr10, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #60 @ 0x3c │ │ mov r4, r0 │ │ @@ -37433,15 +37433,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #32] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ asrs r2, r5, #32 │ │ lsls r2, r5, #1 │ │ - ldrh r0, [r6, r1] │ │ + ldrh r5, [r3, r2] │ │ cdp2 1, 1, cr7, cr8, cr8, {1} │ │ mrc2 14, 0, r0, cr11, cr10, {4} │ │ lsls r2, r5, #1 │ │ │ │ 020967e4 >::__emplace_back_slow_path(std::__ndk1::__fs::filesystem::path&&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -38216,30 +38216,30 @@ │ │ blx 27017a0 │ │ b.n 2097006 >&)@@Base+0x4b6> │ │ add r0, sp, #44 @ 0x2c │ │ blx 2701ca0 │ │ blx 26ffb60 │ │ lsrs r0, r0, #11 │ │ lsls r2, r5, #1 │ │ - ldr r3, [r4, r0] │ │ - vfmsl.f16 d5, s18, s14[0] │ │ + ldr r0, [r2, r1] │ │ + vcmla.f16 , , d4[0], #90 │ │ cdp2 6, 1, cr0, cr9, cr10, {3} │ │ lsls r2, r5, #1 │ │ - ldrh r7, [r4, r3] │ │ + ldrh r4, [r2, r4] │ │ mrc2 5, 0, r3, cr9, cr4, {3} │ │ cdp2 5, 1, cr3, cr10, cr8, {3} │ │ - mrc2 9, 0, r3, cr10, cr14, {0} @ │ │ + @ instruction: 0xfe1a394b │ │ mrc2 10, 0, r6, cr9, cr2, {6} @ │ │ @ instruction: 0xfe1b6ac6 │ │ mrc2 5, 0, r7, cr11, cr12, {7} │ │ - mrc2 10, 0, r1, cr10, cr8, {3} @ │ │ + vselvs.f32 s2, s21, s11 │ │ mrc2 4, 0, fp, cr9, cr4, {0} │ │ mrc2 4, 0, sp, cr7, cr7, {6} │ │ @ instruction: 0xfe1739cd │ │ - mrc2 9, 0, r1, cr8, cr11, {7} @ │ │ + vselvs.f32 s2, s16, s17 │ │ cdp2 5, 1, cr11, cr9, cr0, {4} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (209705c >&)@@Base+0x50c>) │ │ add r0, pc │ │ bl 207d3e8 │ │ ldrh r4, [r4, #52] @ 0x34 │ │ Address 0x209705e is out of bounds. │ │ @@ -39326,16 +39326,16 @@ │ │ ldr r1, [sp, #148] @ 0x94 │ │ str.w sl, [sp, #148] @ 0x94 │ │ str.w r1, [r0], #4 │ │ b.n 2097cc0 >&)@@Base+0x4e0> │ │ lsls r1, r0, #16 │ │ mrc2 10, 0, r7, cr11, cr12, {0} @ │ │ mrc2 9, 0, r7, cr11, cr8, {7} @ │ │ - mrc2 4, 0, lr, cr11, cr6, {7} │ │ - cdp2 13, 1, cr0, cr9, cr8, {5} │ │ + cdp2 5, 1, cr14, cr11, cr3, {1} │ │ + mrc2 13, 0, r0, cr9, cr5, {6} │ │ cdp2 3, 1, cr0, cr9, cr6, {0} │ │ vselvs.f16 s20, s22, s11 │ │ mov r0, r8 │ │ blx 2701e30 │ │ movs r6, #0 │ │ str.w r0, [r8, #4] │ │ mov r0, fp │ │ @@ -39471,18 +39471,18 @@ │ │ asrs r6, r5 │ │ stc 0, cr10, [sp, #724] @ 0x2d4 │ │ stmia r6!, {r0, r1, r2, r4, r5, r6, r7} │ │ subs r6, #176 @ 0xb0 │ │ movs r0, r0 │ │ movs r0, r0 │ │ cdp2 0, 2, cr0, cr12, cr9, {3} │ │ - cmp r0, #183 @ 0xb7 │ │ - vcmla.f16 d2, d25, d11[1], #90 │ │ + cmp r0, #228 @ 0xe4 │ │ + vfmsl.f16 q1, d25, d0[1] │ │ mrc2 5, 0, sl, cr9, cr14, {7} │ │ - @ instruction: 0xfe17e9c2 │ │ + @ instruction: 0xfe17e9ef │ │ cdp2 13, 1, cr0, cr8, cr1, {7} │ │ mrc2 11, 0, r3, cr8, cr13, {5} @ │ │ cdp2 4, 1, cr4, cr11, cr0, {4} │ │ cdp2 2, 1, cr8, cr10, cr5, {6} │ │ cdp2 2, 1, cr10, cr10, cr11, {1} │ │ cdp2 6, 1, cr6, cr10, cr6, {3} │ │ vcmla.f16 , q13, d0[0], #90 │ │ @@ -39842,16 +39842,16 @@ │ │ add r1, pc │ │ b.n 2097eaa >, std::__ndk1::allocator > > >&, std::__ndk1::basic_ostream >&)@@Base+0x52> │ │ nop │ │ nop │ │ stc 0, cr10, [sp, #724] @ 0x2d4 │ │ stmia r6!, {r0, r1, r2, r4, r5, r6, r7} │ │ subs r6, #176 @ 0xb0 │ │ - bkpt 0x00bb │ │ - vcmla.f16 q2, , d2[1], #90 │ │ + bkpt 0x00e8 │ │ + vselvs.f16 s8, s18, s30 │ │ vfmsl.f16 d9, s18, s3[0] │ │ ldr r1, [pc, #44] @ (2098278 >, std::__ndk1::allocator > > >&, std::__ndk1::basic_ostream >&)@@Base+0x420>) │ │ add r1, pc │ │ ldr r1, [r1, #0] │ │ ldr r1, [r1, #0] │ │ cmp r1, r0 │ │ itttt eq │ │ @@ -39859,39 +39859,39 @@ │ │ vpopeq {d8-d15} │ │ addeq sp, #4 │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ it eq │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ - b.n 2097fac >, std::__ndk1::allocator > > >&, std::__ndk1::basic_ostream >&)@@Base+0x154> │ │ + b.n 2098006 >, std::__ndk1::allocator > > >&, std::__ndk1::basic_ostream >&)@@Base+0x1ae> │ │ mrc2 3, 0, ip, cr8, cr4, {2} │ │ mrc2 7, 0, pc, cr7, cr14, {5} │ │ lsls r1, r5, #1 │ │ @ instruction: 0xf3e00069 │ │ - bx lr │ │ - mrc2 5, 0, ip, cr9, cr11, {6} │ │ + @ instruction: 0x47a3 │ │ + cdp2 6, 1, cr12, cr9, cr8, {0} │ │ mrc2 3, 0, r2, cr8, cr4, {0} │ │ - cdp2 5, 1, cr14, cr10, cr6, {0} │ │ + mrc2 5, 0, lr, cr10, cr3, {1} │ │ cdp2 0, 1, cr10, cr8, cr15, {6} │ │ mrc2 5, 0, r1, cr7, cr7, {0} │ │ - mrc2 13, 0, sp, cr11, cr3, {7} │ │ + cdp2 14, 1, cr13, cr11, cr0, {1} │ │ mrc2 12, 0, pc, cr9, cr13, {0} │ │ - mrc2 5, 0, r8, cr10, cr13, {5} │ │ - mrc2 11, 0, fp, cr8, cr8, {6} @ │ │ - mrc2 4, 0, ip, cr9, cr0, {2} │ │ - cdp2 15, 1, cr5, cr8, cr9, {7} │ │ - cdp2 15, 1, cr3, cr9, cr11, {7} │ │ + cdp2 5, 1, cr8, cr10, cr10, {7} │ │ + cdp2 12, 1, cr11, cr8, cr5, {0} │ │ + mrc2 4, 0, ip, cr9, cr13, {3} │ │ + mrc2 0, 0, r6, cr8, cr6, {0} │ │ + mrc2 0, 0, r4, cr9, cr8, {0} │ │ cdp2 13, 1, cr7, cr8, cr11, {1} │ │ cdp2 12, 1, cr9, cr10, cr9, {4} │ │ cdp2 0, 1, cr6, cr10, cr2, {6} │ │ - cdp2 15, 1, cr3, cr10, cr11, {6} │ │ + mrc2 15, 0, r3, cr10, cr8, {7} │ │ mrc2 0, 0, r6, cr8, cr7, {6} │ │ mrc2 15, 0, r9, cr10, cr8, {1} │ │ - mrc2 3, 0, lr, cr7, cr12, {0} │ │ + cdp2 3, 1, cr14, cr7, cr9, {2} │ │ Address 0x20982ca is out of bounds. │ │ │ │ │ │ 020982cc >* std::__ndk1::vector >, std::__ndk1::allocator > > >::__push_back_slow_path > >(std::__ndk1::unique_ptr >&&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -40649,15 +40649,15 @@ │ │ str.w fp, [sp, #73] @ 0x49 │ │ strb.w r0, [sp, #72] @ 0x48 │ │ beq.w 2098be2 │ │ mov r6, r8 │ │ b.n 2098ab0 │ │ nop │ │ str r4, [sp, #656] @ 0x290 │ │ - mrc2 12, 0, r7, cr11, cr10, {5} │ │ + cdp2 12, 1, cr7, cr11, cr7, {7} │ │ cdp2 3, 1, cr15, cr9, cr8, {4} │ │ vfmsl.f16 d6, s20, s13[0] │ │ cmp r6, #0 │ │ beq.w 2098be2 │ │ ldrb r0, [r6, #16] │ │ ldrd r5, r4, [r6, #20] │ │ ands.w r1, r0, #1 │ │ @@ -41035,16 +41035,16 @@ │ │ vld1.16 {d8}, [r1] │ │ movs r1, #0 │ │ vst1.8 {d9}, [r8] │ │ strb.w r1, [r8, #14] │ │ vst1.8 {d8}, [r0] │ │ b.n 2098ec0 │ │ nop │ │ - ldrsb r4, [r5, r7] │ │ - mrc2 7, 0, r7, cr8, cr10, {7} │ │ + ldr r1, [r3, r0] │ │ + vcmla.f16 d7, d8, d7[1], #90 │ │ cdp2 13, 1, cr8, cr9, cr0, {6} │ │ @ instruction: 0xfe1b8b64 │ │ cdp2 0, 1, cr9, cr11, cr14, {7} │ │ cdp2 4, 1, cr3, cr11, cr4, {0} │ │ ldr r4, [r4, #0] │ │ cmp r4, #0 │ │ beq.w 2098ff4 │ │ @@ -41463,17 +41463,17 @@ │ │ mov.w r0, #0 │ │ strb.w r0, [fp, #12] │ │ vst1.8 {d8}, [fp] │ │ beq.w 209966e │ │ mov r6, sl │ │ b.n 209931c │ │ nop │ │ - pldw [r9, #24] │ │ + str??t pc, [r6, #24] │ │ str r1, [sp, #536] @ 0x218 │ │ - cdp2 1, 1, cr5, cr11, cr7, {1} │ │ + mrc2 1, 0, r5, cr11, cr4, {2} │ │ vfmsl.f16 d6, s18, s13[0] │ │ cmp r6, #0 │ │ beq.w 209966e │ │ ldrb r0, [r6, #16] │ │ ldrd r5, r8, [r6, #20] │ │ ands.w r1, r0, #1 │ │ itt eq │ │ @@ -42691,20 +42691,20 @@ │ │ blxne 26ffb40 │ │ ldrb.w r0, [sp, #56] @ 0x38 │ │ lsls r0, r0, #31 │ │ beq.w 2099d60 │ │ ldr r0, [sp, #64] @ 0x40 │ │ b.n 2099d5c │ │ nop │ │ - ldrh r0, [r3, #10] │ │ + ldrh r5, [r0, #12] │ │ vcmla.f16 d7, d24, d6[1], #90 │ │ cdp2 5, 1, cr0, cr11, cr4, {7} │ │ cdp2 0, 1, cr8, cr10, cr4, {2} │ │ - mrc2 7, 0, r0, cr11, cr10, {6} │ │ - vcmla.f16 d14, d25, d2[1], #90 │ │ + vcmla.f16 d0, d11, d7[0], #90 │ │ + vcmla.f16 q7, , d15[0], #90 │ │ @ instruction: 0xfe1849e0 │ │ add r1, pc │ │ ldr r0, [sp, #36] @ 0x24 │ │ blx 2701ed0 │ │ add r2, sp, #56 @ 0x38 │ │ adds r0, r2, #1 │ │ str r0, [sp, #24] │ │ @@ -43042,15 +43042,15 @@ │ │ blxne 26ffb40 │ │ b.n 209a372 │ │ b.n 209a3dc │ │ b.n 209a3dc │ │ b.n 209a3dc │ │ b.n 209a34c │ │ ldr r4, [sp, #324] @ 0x144 │ │ - cdp2 5, 1, cr0, cr10, cr6, {4} │ │ + mrc2 5, 0, r0, cr10, cr3, {5} │ │ cdp2 0, 1, cr14, cr9, cr8, {2} │ │ b.n 209a384 │ │ ldrb.w r0, [sp, #72] @ 0x48 │ │ lsls r0, r0, #31 │ │ beq.n 209a384 │ │ ldr r0, [sp, #80] @ 0x50 │ │ b.n 209a37c │ │ @@ -43118,17 +43118,17 @@ │ │ ldr r0, [sp, #36] @ 0x24 │ │ ldr r0, [r0, #8] │ │ blx 26ffb40 │ │ ldr r1, [sp, #88] @ 0x58 │ │ add r0, sp, #84 @ 0x54 │ │ bl 209a5f4 , std::__ndk1::allocator > fmt::v11::sprintf, std::__ndk1::allocator >, char>(char* const&, std::__ndk1::basic_string, std::__ndk1::allocator > const&)@@Base+0xe4> │ │ blx 26ffb60 │ │ - lsls r2, r5, #19 │ │ - mrc2 4, 0, r0, cr9, cr10, {3} │ │ - cdp2 3, 1, cr0, cr9, cr10, {7} │ │ + lsls r7, r2, #20 │ │ + cdp2 4, 1, cr0, cr9, cr7, {5} │ │ + mrc2 4, 0, r0, cr9, cr7, {0} │ │ cdp2 3, 1, cr13, cr9, cr14, {4} │ │ lsls r1, r5, #1 │ │ │ │ 0209a408 , std::__ndk1::allocator > fmt::v11::sprintf, std::__ndk1::allocator >, std::__ndk1::basic_string, std::__ndk1::allocator >, char>(char* const&, std::__ndk1::basic_string, std::__ndk1::allocator > const&, std::__ndk1::basic_string, std::__ndk1::allocator > const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ @@ -44426,26 +44426,26 @@ │ │ add r0, pc │ │ bl 221a388 │ │ ldr r0, [pc, #12] @ (209b11c >(fmt::v11::detail::buffer&, fmt::v11::basic_string_view, fmt::v11::basic_format_args >)@@Base+0xa30>) │ │ add r0, pc │ │ bl 221a388 │ │ ldmia r7!, {r5} │ │ lsls r1, r5, #1 │ │ - adds r1, #227 @ 0xe3 │ │ - mrc2 5, 0, r5, cr8, cr6, {4} │ │ - cdp2 3, 1, cr5, cr8, cr5, {1} │ │ + adds r2, #16 │ │ + cdp2 5, 1, cr5, cr8, cr3, {6} │ │ + mrc2 3, 0, r5, cr8, cr2, {2} │ │ mrc2 7, 0, r7, cr9, cr8, {7} │ │ cdp2 6, 1, cr7, cr11, cr2, {6} │ │ cdp2 7, 1, cr7, cr11, cr0, {0} │ │ mrc2 7, 0, r7, cr11, cr2, {2} │ │ cdp2 5, 1, cr12, cr11, cr14, {3} │ │ lsls r1, r5, #1 │ │ - bvs.n 209b170 >(fmt::v11::detail::buffer&, fmt::v11::basic_string_view, fmt::v11::basic_format_args >)::{lambda(int)#1}>(char const*&, char const*, fmt::v11::format_specs&, fmt::v11::detail::vprintf >(fmt::v11::detail::buffer&, fmt::v11::basic_string_view, fmt::v11::basic_format_args >)::{lambda(int)#1})@@Base+0x28> │ │ - cdp2 4, 1, cr15, cr8, cr2, {4} │ │ - mrc2 0, 0, r3, cr8, cr2, {5} │ │ + bvs.n 209b1ca >(fmt::v11::detail::buffer&, fmt::v11::basic_string_view, fmt::v11::basic_format_args >)::{lambda(int)#1}>(char const*&, char const*, fmt::v11::format_specs&, fmt::v11::detail::vprintf >(fmt::v11::detail::buffer&, fmt::v11::basic_string_view, fmt::v11::basic_format_args >)::{lambda(int)#1})@@Base+0x82> │ │ + cdp2 4, 1, cr15, cr8, cr15, {5} │ │ + mrc2 0, 0, r3, cr8, cr15, {6} │ │ mrc2 0, 0, r7, cr9, cr11, {0} │ │ Address 0x209b146 is out of bounds. │ │ │ │ │ │ 0209b148 >(fmt::v11::detail::buffer&, fmt::v11::basic_string_view, fmt::v11::basic_format_args >)::{lambda(int)#1}>(char const*&, char const*, fmt::v11::format_specs&, fmt::v11::detail::vprintf >(fmt::v11::detail::buffer&, fmt::v11::basic_string_view, fmt::v11::basic_format_args >)::{lambda(int)#1})@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -44698,19 +44698,19 @@ │ │ bl 221a388 │ │ ldr r0, [pc, #24] @ (209b440 >(fmt::v11::detail::buffer&, fmt::v11::basic_string_view, fmt::v11::basic_format_args >)::{lambda(int)#1}>(char const*&, char const*, fmt::v11::format_specs&, fmt::v11::detail::vprintf >(fmt::v11::detail::buffer&, fmt::v11::basic_string_view, fmt::v11::basic_format_args >)::{lambda(int)#1})@@Base+0x2f8>) │ │ add r0, pc │ │ bl 221a388 │ │ ldr r0, [pc, #20] @ (209b444 >(fmt::v11::detail::buffer&, fmt::v11::basic_string_view, fmt::v11::basic_format_args >)::{lambda(int)#1}>(char const*&, char const*, fmt::v11::format_specs&, fmt::v11::detail::vprintf >(fmt::v11::detail::buffer&, fmt::v11::basic_string_view, fmt::v11::basic_format_args >)::{lambda(int)#1})@@Base+0x2fc>) │ │ add r0, pc │ │ bl 221a388 │ │ - strh r6, [r1, r2] │ │ - cdp2 14, 1, cr2, cr8, cr3, {5} │ │ - cdp2 3, 1, cr5, cr8, cr8, {4} │ │ - vcmla.f16 q4, q12, d15[1], #90 │ │ - cdp2 2, 1, cr13, cr9, cr10, {7} │ │ + strh r3, [r7, r2] │ │ + mrc2 14, 0, r2, cr8, cr0, {6} │ │ + mrc2 3, 0, r5, cr8, cr5, {5} │ │ + mrc2 9, 0, r8, cr8, cr12, {0} @ │ │ + mrc2 3, 0, sp, cr9, cr7, {0} │ │ Address 0x209b446 is out of bounds. │ │ │ │ │ │ 0209b448 , char>(fmt::v11::basic_format_arg >&, char)@@Base>: │ │ ldr r2, [r0, #8] │ │ subs r2, #1 │ │ cmp r2, #7 │ │ @@ -47713,15 +47713,15 @@ │ │ blx 26ffb50 │ │ add r4, pc, #232 @ (adr r4, 209d37c ::operator()(char const*)@@Base+0x1bdc>) │ │ lsls r1, r5, #1 │ │ strh r2, [r0, r6] │ │ mrc2 3, 0, sl, cr11, cr2, {5} │ │ lsls r1, r5, #1 │ │ ldr r7, [pc, #216] @ (209d378 ::operator()(char const*)@@Base+0x1bd8>) │ │ - mrc2 15, 0, r0, cr7, cr6, {6} │ │ + cdp2 0, 1, cr1, cr7, cr3, {0} │ │ mrc2 5, 0, fp, cr9, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r4, r0 │ │ ldr r0, [pc, #248] @ (209d3ac ::operator()(char const*)@@Base+0x1c0c>) │ │ mov r5, r1 │ │ @@ -48153,22 +48153,22 @@ │ │ blx 26ffb60 │ │ nop │ │ movs r0, r0 │ │ ldrb r0, [r0, #30] │ │ add r1, pc, #552 @ (adr r1, 209d950 ::operator()(char const*)@@Base+0x21b0>) │ │ lsls r1, r5, #1 │ │ strh r2, [r2, #12] │ │ - @ instruction: 0xfe1a49e2 │ │ + vselvs.f32 s8, s20, s30 │ │ mrc2 7, 0, sl, cr9, cr6, {2} │ │ - cdp2 0, 1, cr13, cr10, cr10, {1} │ │ + mrc2 0, 0, sp, cr10, cr7, {2} │ │ cdp2 15, 1, cr9, cr8, cr12, {2} │ │ lsls r1, r5, #1 │ │ add r1, pc, #392 @ (adr r1, 209d8c8 ::operator()(char const*)@@Base+0x2128>) │ │ lsls r1, r5, #1 │ │ - cmp r7, #162 @ 0xa2 │ │ + cmp r7, #207 @ 0xcf │ │ mrc2 5, 0, fp, cr8, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #52 @ 0x34 │ │ ldr r2, [pc, #880] @ (209dac0 ::operator()(char const*)@@Base+0x2320>) │ │ ldrh.w r9, [r7, #9] │ │ add r2, pc │ │ @@ -49167,15 +49167,15 @@ │ │ blx 26ffc10 │ │ mov r0, r4 │ │ blx 26ffc20 │ │ blx 26ffb60 │ │ nop │ │ ldr r3, [sp, #208] @ 0xd0 │ │ lsls r1, r5, #1 │ │ - movs r4, #164 @ 0xa4 │ │ + movs r4, #209 @ 0xd1 │ │ mrc2 4, 0, r9, cr8, cr2, {6} │ │ lsls r1, r5, #1 │ │ str r4, [sp, #848] @ 0x350 │ │ lsls r1, r5, #1 │ │ mov ip, r2 │ │ cdp2 6, 1, cr4, cr11, cr2, {1} │ │ cdp2 4, 1, cr9, cr11, cr12, {3} │ │ @@ -51186,15 +51186,15 @@ │ │ cmp r0, r1 │ │ it ne │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ ldrh r6, [r0, #48] @ 0x30 │ │ lsls r1, r5, #1 │ │ - asrs r0, r3, #3 │ │ + asrs r5, r0, #4 │ │ mrc2 1, 0, r8, cr8, cr2, {0} │ │ lsls r1, r5, #1 │ │ strh r2, [r0, #8] │ │ lsls r1, r5, #1 │ │ strh r2, [r0, #8] │ │ lsls r1, r5, #1 │ │ strh r4, [r0, #12] │ │ @@ -53922,22 +53922,22 @@ │ │ movs r0, r0 │ │ movs r0, r0 │ │ movs r0, r0 │ │ ldrb r0, [r6, #31] │ │ str r0, [r6, #104] @ 0x68 │ │ lsls r1, r5, #1 │ │ mov lr, r5 │ │ - mrc2 14, 0, r0, cr10, cr14, {7} │ │ + cdp2 15, 1, cr0, cr10, cr11, {1} │ │ mrc2 12, 0, r6, cr9, cr2, {3} │ │ - cdp2 5, 1, cr9, cr10, cr6, {2} │ │ + mrc2 5, 0, r9, cr10, cr3, {3} │ │ cdp2 4, 1, cr6, cr8, cr10, {3} │ │ lsls r1, r5, #1 │ │ str r0, [r0, #104] @ 0x68 │ │ lsls r1, r5, #1 │ │ - bl 1d61e56 │ │ + bl 1d8ee56 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8} │ │ sub.w sp, sp, #576 @ 0x240 │ │ mov ip, r0 │ │ @@ -54181,22 +54181,22 @@ │ │ movs r0, r0 │ │ movs r0, r0 │ │ movs r0, r0 │ │ ldrb r0, [r6, #31] │ │ str r0, [r5, #60] @ 0x3c │ │ lsls r1, r5, #1 │ │ mvns r6, r4 │ │ - mrc2 12, 0, r0, cr10, cr6, {1} │ │ + cdp2 12, 1, cr0, cr10, cr3, {3} │ │ vselvs.f16 s12, s19, s21 │ │ - mrc2 2, 0, r9, cr10, cr14, {3} │ │ + cdp2 2, 1, cr9, cr10, cr11, {5} │ │ cdp2 1, 1, cr6, cr8, cr2, {5} │ │ lsls r1, r5, #1 │ │ str r0, [r7, #56] @ 0x38 │ │ lsls r1, r5, #1 │ │ - bl 229a11e │ │ + bl 22c711e │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #20 │ │ mov r5, r1 │ │ mov r4, r0 │ │ ldr r0, [pc, #304] @ (20a1630 ::operator()(char const*)@@Base+0x5e90>) │ │ @@ -54372,15 +54372,15 @@ │ │ str r0, [r4, #16] │ │ mov r0, r1 │ │ movs r1, #1 │ │ blx 2701fc0 │ │ str r0, [r4, #24] │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ - lsrs r0, r6, #26 │ │ + lsrs r5, r3, #27 │ │ Address 0x20a16b6 is out of bounds. │ │ │ │ │ │ 020a16b8 const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -54421,15 +54421,15 @@ │ │ str r0, [r4, #20] │ │ mov r0, r1 │ │ movs r1, #1 │ │ blx 2701fc0 │ │ str r0, [r4, #28] │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ - lsrs r4, r7, #24 │ │ + lsrs r1, r5, #25 │ │ mrc2 4, 0, sp, cr8, cr4, {6} │ │ bmi.n 20a16da const&)@@Base+0x22> │ │ │ │ 020a1730 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -54847,15 +54847,15 @@ │ │ movs r1, #1 │ │ blx 2701fc0 │ │ movs r1, #0 │ │ str r0, [r4, #44] @ 0x2c │ │ str r1, [r4, #76] @ 0x4c │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ - lsrs r4, r4, #8 │ │ + lsrs r1, r2, #9 │ │ Address 0x20a1b46 is out of bounds. │ │ │ │ │ │ 020a1b48 : │ │ adds r0, #28 │ │ bx lr │ │ │ │ @@ -54900,15 +54900,15 @@ │ │ str r0, [r4, #40] @ 0x28 │ │ mov r0, r1 │ │ movs r1, #1 │ │ blx 2701fc0 │ │ str r0, [r4, #48] @ 0x30 │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ - lsrs r0, r5, #6 │ │ + lsrs r5, r2, #7 │ │ Address 0x20a1bbe is out of bounds. │ │ │ │ │ │ 020a1bc0 : │ │ ldr r2, [r1, #40] @ 0x28 │ │ ldr r1, [r1, #48] @ 0x30 │ │ strd r1, r2, [r0] │ │ @@ -54983,15 +54983,15 @@ │ │ addeq sp, #40 @ 0x28 │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ ldrh r4, [r2, r1] │ │ lsls r1, r5, #1 │ │ subs r3, #84 @ 0x54 │ │ - mrc2 5, 0, sl, cr10, cr9, {7} │ │ + cdp2 6, 1, cr10, cr10, cr6, {1} │ │ cdp2 12, 1, cr0, cr7, cr10, {3} │ │ mrc2 9, 0, r5, cr11, cr0, {6} @ │ │ lsls r1, r5, #1 │ │ │ │ 020a1c88 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -55428,23 +55428,23 @@ │ │ add r2, pc │ │ cdp2 15, 15, cr3, cr12, cr13, {6} │ │ ldr r2, [r1, r6] │ │ lsls r1, r5, #1 │ │ strh r0, [r5, #44] @ 0x2c │ │ vselvs.f32 s6, s18, s18 │ │ mrc2 5, 0, r8, cr10, cr2, {3} │ │ - cdp2 3, 1, cr6, cr9, cr9, {2} │ │ + mrc2 3, 0, r6, cr9, cr6, {3} │ │ vcmla.f16 d8, d25, d12[1], #90 │ │ - mrc2 4, 0, r0, cr7, cr7, {5} │ │ - cdp2 0, 1, cr6, cr8, cr6, {6} │ │ - cdp2 15, 1, cr1, cr9, cr11, {0} │ │ + cdp2 4, 1, cr0, cr7, cr4, {7} │ │ + mrc2 0, 0, r6, cr8, cr3, {7} │ │ + mrc2 15, 0, r1, cr9, cr8, {1} │ │ cdp2 14, 1, cr13, cr9, cr14, {2} │ │ @ instruction: 0xfe191b4a │ │ @ instruction: 0xfe1a3961 │ │ - mrc2 6, 0, lr, cr10, cr14, {7} │ │ + cdp2 7, 1, cr14, cr10, cr11, {1} │ │ mrc2 5, 0, r5, cr7, cr6, {4} │ │ lsls r1, r5, #1 │ │ bmi.n 20a2128 │ │ bmi.n 20a212a │ │ │ │ 020a2180 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -55766,15 +55766,15 @@ │ │ ldr r7, [pc, #124] @ (20a25c0 ) │ │ lsrs r7, r7, #13 │ │ adcs r2, r4 │ │ ldmia r4!, {r2, r3, r6, r7} │ │ ldmia r2, {r2, r3, r6} │ │ subs r0, r1, #6 │ │ tst r0, r3 │ │ - movs r3, #25 │ │ + movs r3, #70 @ 0x46 │ │ mrc2 6, 0, r4, cr8, cr0, {2} │ │ blx 27006a0 │ │ vmov d16, r0, r1 │ │ vldr d17, [pc, #368] @ 20a26d0 │ │ vabs.f64 d16, d16 │ │ vcmp.f64 d16, d17 │ │ vmrs APSR_nzcv, fpscr │ │ @@ -55906,20 +55906,20 @@ │ │ subs r6, #176 @ 0xb0 │ │ ldrsb r6, [r2, r0] │ │ ldr r6, [sp, #924] @ 0x39c │ │ lsls r7, r5, #14 │ │ subs r4, #210 @ 0xd2 │ │ strb r6, [r1, r2] │ │ lsls r1, r5, #1 │ │ - movs r1, #129 @ 0x81 │ │ + movs r1, #174 @ 0xae │ │ cdp2 14, 1, cr7, cr8, cr10, {4} │ │ mrc2 14, 0, ip, cr9, cr5, {4} │ │ - vselvs.f16 s6, s21, s1 │ │ - cdp2 0, 1, cr8, cr9, cr10, {5} │ │ - mrc2 14, 0, sp, cr8, cr12, {2} │ │ + @ instruction: 0xfe1a39cd │ │ + mrc2 0, 0, r8, cr9, cr7, {6} │ │ + cdp2 14, 1, cr13, cr8, cr9, {4} │ │ mrc2 1, 0, r3, cr8, cr12, {2} │ │ mrc2 11, 0, pc, cr10, cr12, {4} @ │ │ mrc2 0, 0, r5, cr6, cr10, {1} │ │ lsls r1, r5, #1 │ │ │ │ 020a2700 (std::__ndk1::locale const&, std::__ndk1::basic_string_view >, float const&)@@Base>: │ │ push {r4, r5, r7, lr} │ │ @@ -56354,16 +56354,16 @@ │ │ nop │ │ adds r3, #51 @ 0x33 │ │ rors r3, r1 │ │ str r6, [r4, #100] @ 0x64 │ │ subs r7, #166 @ 0xa6 │ │ ldr??.w pc, [r8, #3606] @ 0xe16 │ │ ldrb r0, [r2, #11] │ │ - cdp2 12, 1, cr3, cr9, cr15, {6} │ │ - cdp2 4, 1, cr1, cr8, cr11, {4} │ │ + mrc2 12, 0, r3, cr9, cr12, {7} │ │ + mrc2 4, 0, r1, cr8, cr8, {5} │ │ vselvs.f16 s2, s18, s4 │ │ vselvs.f32 s24, s15, s17 │ │ @ instruction: 0xfe1a79c4 │ │ mrc2 0, 0, r6, cr9, cr3, {0} │ │ cdp2 4, 1, cr15, cr7, cr13, {3} │ │ @ instruction: 0xfe19c9c8 │ │ vfmsl.f16 d4, s21, s0[1] │ │ @@ -56593,23 +56593,23 @@ │ │ blx 26ffb60 │ │ movs r0, r0 │ │ orrs r4, r6 │ │ vst3. {d3[0],d5[0],d7[0]}, [r3], r2 │ │ ldr r6, [pc, #552] @ (20a302c const&)@@Base+0x1ec>) │ │ lsls r1, r5, #1 │ │ @ instruction: 0xb75d │ │ - mrc2 11, 0, r9, cr9, cr15, {5} @ │ │ + @ instruction: 0xfe199bec │ │ cdp2 7, 1, cr12, cr8, cr6, {7} │ │ mrc2 13, 0, r2, cr10, cr14, {3} │ │ cdp2 1, 1, cr1, cr10, cr9, {3} │ │ mrc2 9, 0, ip, cr10, cr4, {1} @ │ │ vcmla.f16 q6, q13, d8[0], #90 │ │ - cdp2 12, 1, cr13, cr10, cr14, {1} │ │ - mrc2 9, 0, r1, cr7, cr4, {6} @ │ │ - cdp2 0, 1, cr1, cr8, cr14, {3} │ │ + mrc2 12, 0, sp, cr10, cr11, {2} │ │ + vselvs.f32 s2, s14, s2 │ │ + mrc2 0, 0, r1, cr8, cr11, {4} │ │ mrc2 7, 0, ip, cr9, cr2, {2} │ │ mrc2 6, 0, r7, cr10, cr8, {3} │ │ cdp2 6, 1, cr11, cr9, cr0, {0} │ │ vfmsl.f16 d4, s19, s5[0] │ │ lsls r1, r5, #1 │ │ bmi.n 20a2de8 │ │ bmi.n 20a2dea │ │ @@ -57046,21 +57046,21 @@ │ │ b.n 20a3742 const&)@@Base+0x902> │ │ movs r0, #4 │ │ ldr.w r8, [sp, #60] @ 0x3c │ │ str r0, [sp, #36] @ 0x24 │ │ b.w 20a41e6 const&)@@Base+0x13a6> │ │ nop │ │ strb r4, [r3, #13] │ │ - mrc2 4, 0, sp, cr9, cr4, {5} │ │ + cdp2 4, 1, cr13, cr9, cr1, {7} │ │ cdp2 15, 1, cr11, cr8, cr0, {0} │ │ nop │ │ lsrs r2, r3, #6 │ │ adcs.w r5, r1, #260096 @ 0x3f800 │ │ cmp r1, r4 │ │ - str r1, [sp, #424] @ 0x1a8 │ │ + str r1, [sp, #604] @ 0x25c │ │ cdp2 15, 1, cr8, cr7, cr9, {2} │ │ cdp2 6, 1, cr4, cr9, cr11, {6} │ │ ldr r5, [sp, #112] @ 0x70 │ │ ldr.w r0, [r8, #52] @ 0x34 │ │ add.w r1, r8, #28 │ │ blx 2702050 │ │ ldr.w r0, [r8, #52] @ 0x34 │ │ @@ -57384,34 +57384,34 @@ │ │ mov r0, fp │ │ mov r1, r4 │ │ blx 2702100 │ │ ldr.w r8, [sp, #48] @ 0x30 │ │ b.n 20a3c64 const&)@@Base+0xe24> │ │ ldr r0, [r6, #124] @ 0x7c │ │ cdp2 15, 1, cr6, cr9, cr4, {3} │ │ - @ instruction: 0xfe19ebec │ │ - mrc2 0, 0, sp, cr8, cr10, {3} │ │ + mrc2 12, 0, lr, cr9, cr9, {0} │ │ + cdp2 0, 1, cr13, cr8, cr7, {5} │ │ @ instruction: 0xfe18cacf │ │ cdp2 0, 1, cr0, cr9, cr0, {0} │ │ stmia r4!, {r1, r3, r4, r5, r6} │ │ @ instruction: 0xb8bb │ │ lsls r5, r1, #26 │ │ ldr r6, [pc, #960] @ (20a3ad8 const&)@@Base+0xc98>) │ │ eors r0, r0 │ │ pop {r1, r2, r4, r5, r6, pc} │ │ eors r0, r2 │ │ str r0, [r3, #8] │ │ cdp2 13, 1, cr6, cr10, cr14, {5} │ │ - mrc2 14, 0, ip, cr9, cr4, {7} │ │ - mrc2 7, 0, r0, cr8, cr2, {1} │ │ + cdp2 15, 1, cr12, cr9, cr1, {1} │ │ + mrc2 7, 0, r0, cr8, cr15, {2} │ │ mrc2 6, 0, lr, cr9, cr15, {7} │ │ cmp r6, #219 @ 0xdb │ │ - ldr r3, [pc, #196] @ (20a37f8 const&)@@Base+0x9b8>) │ │ + ldr r3, [pc, #376] @ (20a38ac const&)@@Base+0xa6c>) │ │ cdp2 12, 1, cr10, cr9, cr11, {2} │ │ - cdp2 0, 1, cr13, cr9, cr13, {2} │ │ + mrc2 0, 0, sp, cr9, cr10, {3} │ │ cdp2 0, 1, cr15, cr7, cr15, {2} │ │ lsrs r2, r0, #12 │ │ mov r4, sl │ │ ldr.w r0, [r8, #52] @ 0x34 │ │ add.w r1, r8, #28 │ │ blx 2702050 │ │ ldr.w r0, [r8, #52] @ 0x34 │ │ @@ -57729,15 +57729,15 @@ │ │ it mi │ │ movmi r0, #69 @ 0x45 │ │ strb.w r0, [sp, #128] @ 0x80 │ │ vstr d17, [sp, #144] @ 0x90 │ │ vstr d18, [sp, #160] @ 0xa0 │ │ b.n 20a3b90 const&)@@Base+0xd50> │ │ ldr r2, [r1, #60] @ 0x3c │ │ - mrc2 12, 0, ip, cr9, cr0, {7} │ │ + mrc2 13, 0, ip, cr9, cr13, {0} │ │ mrc2 9, 0, r0, cr8, cr10, {4} @ │ │ adcs.w r5, r1, #260096 @ 0x3f800 │ │ cmp r1, r4 │ │ lsrs r2, r2, #7 │ │ cdp2 15, 1, cr11, cr7, cr0, {0} │ │ nop │ │ movs r0, r0 │ │ @@ -57745,15 +57745,15 @@ │ │ push {r2, r3, r5} │ │ adcs r2, r0 │ │ movs r0, r0 │ │ movs r0, r0 │ │ movs r0, r0 │ │ strh r0, [r0, #0] │ │ lsls r4, r1, #11 │ │ - @ instruction: 0xfe1aebed │ │ + mrc2 12, 0, lr, cr10, cr10, {0} │ │ mrc2 9, 0, r6, cr7, cr8, {5} @ │ │ cdp2 14, 1, cr7, cr9, cr2, {1} │ │ mrc2 14, 0, lr, cr10, cr5, {5} │ │ add r3, sp, #256 @ 0x100 │ │ vmrs APSR_nzcv, fpscr │ │ ble.n 20a3b58 const&)@@Base+0xd18> │ │ movs r0, #69 @ 0x45 │ │ @@ -57988,15 +57988,15 @@ │ │ movs r0, r0 │ │ movs r0, r0 │ │ strh r0, [r0, #0] │ │ eors r6, r6 │ │ @ instruction: 0xb853 │ │ cdp2 6, 1, cr0, cr10, cr6, {1} │ │ mrc2 10, 0, r6, cr7, cr7, {4} @ │ │ - mrc2 5, 0, sl, cr7, cr1, {1} │ │ + mrc2 5, 0, sl, cr7, cr14, {2} │ │ cdp2 1, 1, cr6, cr8, cr5, {6} │ │ ldr r7, [pc, #124] @ (20a3e80 const&)@@Base+0x1040>) │ │ lsrs r7, r7, #13 │ │ adcs r2, r4 │ │ cmp r7, #182 @ 0xb6 │ │ asrs r7, r4, #12 │ │ stmia r2!, {r0, r1, r3, r4, r5, r6} │ │ @@ -58263,24 +58263,24 @@ │ │ movs r0, #3 │ │ strd r0, r0, [sp, #232] @ 0xe8 │ │ str r6, [sp, #224] @ 0xe0 │ │ vstr s16, [sp, #228] @ 0xe4 │ │ b.n 20a4180 const&)@@Base+0x1340> │ │ nop │ │ push {r1, r2, r6} │ │ - cdp2 6, 1, cr6, cr10, cr9, {4} │ │ + mrc2 6, 0, r6, cr10, cr6, {5} │ │ cdp2 2, 1, cr1, cr8, cr15, {3} │ │ subs r2, #131 @ 0x83 │ │ - movs r5, #44 @ 0x2c │ │ + movs r5, #89 @ 0x59 │ │ cdp2 0, 1, cr0, cr8, cr0, {0} │ │ negs r0, r1 │ │ strb r0, [r2, r6] │ │ vcmla.f16 , q5, d4[0], #90 │ │ mrc2 6, 0, r6, cr10, cr5, {3} │ │ - cdp2 5, 1, cr0, cr7, cr2, {0} │ │ + cdp2 5, 1, cr0, cr7, cr15, {1} │ │ mrc2 5, 0, r2, cr8, cr0, {6} │ │ sbcs r0, r0 │ │ ldr r0, [pc, #28] @ (20a417c const&)@@Base+0x133c>) │ │ add r0, pc │ │ blx 26ffe40 │ │ mov r4, r0 │ │ blx 26ffea0 │ │ @@ -58319,15 +58319,15 @@ │ │ mov r0, r9 │ │ mov r1, r4 │ │ mov r2, r5 │ │ mov r3, r6 │ │ blx 27022b0 │ │ b.n 20a41d8 const&)@@Base+0x1398> │ │ nop │ │ - udf #90 @ 0x5a │ │ + udf #135 @ 0x87 │ │ vfmsl.f16 d15, s17, s10[1] │ │ lsls r0, r4, #3 │ │ lsls r0, r0, #31 │ │ beq.n 20a41e6 const&)@@Base+0x13a6> │ │ ldr r0, [sp, #232] @ 0xe8 │ │ blx 26ffb40 │ │ ldr r0, [sp, #56] @ 0x38 │ │ @@ -58680,15 +58680,15 @@ │ │ lsls r0, r0, #31 │ │ beq.n 20a4614 const&)@@Base+0x17d4> │ │ ldr r0, [sp, #72] @ 0x48 │ │ blx 26ffb40 │ │ b.n 20a4614 const&)@@Base+0x17d4> │ │ b.n 20a4614 const&)@@Base+0x17d4> │ │ b.n 20a4636 const&)@@Base+0x17f6> │ │ - strh r2, [r1, #0] │ │ + strh r7, [r6, #0] │ │ vfmsl.f16 d15, s15, s10[1] │ │ lsls r0, r6, #2 │ │ lsls r0, r0, #31 │ │ beq.n 20a4684 const&)@@Base+0x1844> │ │ ldr r0, [sp, #184] @ 0xb8 │ │ b.n 20a4680 const&)@@Base+0x1840> │ │ b.n 20a4636 const&)@@Base+0x17f6> │ │ @@ -58771,15 +58771,15 @@ │ │ ittee │ │ cmp r5, #24 │ │ strb r4, [r0, r1] │ │ moval r1, #251 @ 0xfb │ │ subal r7, #249 @ 0xf9 │ │ ldr r6, [sp, #384] @ 0x180 │ │ cdp2 2, 1, cr7, cr9, cr8, {5} │ │ - cdp2 0, 1, cr6, cr10, cr11, {5} │ │ + mrc2 0, 0, r6, cr10, cr8, {6} │ │ mrc2 0, 0, r3, cr8, cr4, {3} │ │ lsls r1, r5, #1 │ │ │ │ 020a46e8 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ vpush {d8} │ │ @@ -59104,19 +59104,19 @@ │ │ movs r0, r0 │ │ movs r1, r0 │ │ movs r0, r0 │ │ movs r0, r0 │ │ negs r0, r6 │ │ cmp r6, #52 @ 0x34 │ │ lsls r1, r5, #1 │ │ - ldr r1, [sp, #116] @ 0x74 │ │ + ldr r1, [sp, #296] @ 0x128 │ │ mrc2 14, 0, r1, cr8, cr11, {1} │ │ cdp2 0, 1, cr4, cr7, cr10, {7} │ │ - cdp2 13, 1, cr7, cr7, cr6, {6} │ │ - mrc2 13, 0, r3, cr8, cr10, {3} │ │ + mrc2 13, 0, r7, cr7, cr3, {7} │ │ + cdp2 13, 1, cr3, cr8, cr7, {5} │ │ mrc2 11, 0, r2, cr8, cr6, {6} @ │ │ lsls r1, r5, #1 │ │ │ │ 020a4ab0 (std::__ndk1::locale const&, std::__ndk1::basic_string_view >, double const&)@@Base>: │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #48 @ 0x30 │ │ @@ -59631,16 +59631,16 @@ │ │ itt eq │ │ addeq sp, #64 @ 0x40 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ movs r7, #2 │ │ lsls r1, r5, #1 │ │ add r4, pc, #312 @ (adr r4, 20a5110 (std::__ndk1::locale const&, std::__ndk1::basic_string_view >, int const&, float const&)@@Base+0x88>) │ │ - cdp2 0, 1, cr13, cr10, cr4, {2} │ │ - cdp2 2, 1, cr7, cr8, cr15, {5} │ │ + mrc2 0, 0, sp, cr10, cr1, {3} │ │ + mrc2 2, 0, r7, cr8, cr12, {6} │ │ cdp2 6, 1, cr2, cr7, cr14, {3} │ │ lsls r1, r5, #1 │ │ │ │ 020a4fe4 (std::__ndk1::locale const&, std::__ndk1::basic_string_view >, int const&, int const&, float const&, char* const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -59905,15 +59905,15 @@ │ │ mov r1, r2 │ │ b.w 26fe9cc │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (20a5284 ::format_custom_arg, fmt::v11::formatter, char, void> >(void*, fmt::v11::basic_format_parse_context&, fmt::v11::context&)@@Base+0x20>) │ │ add r0, pc │ │ blx 27025b0 │ │ - ldr r4, [r0, #124] @ 0x7c │ │ + ldr r1, [r6, #124] @ 0x7c │ │ Address 0x20a5286 is out of bounds. │ │ │ │ │ │ 020a5288 : │ │ push {r7, lr} │ │ mov r7, sp │ │ bl 221a388 │ │ @@ -60018,18 +60018,18 @@ │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ movs r4, #20 │ │ lsls r1, r5, #1 │ │ movs r3, #134 @ 0x86 │ │ lsls r1, r5, #1 │ │ - cbz r4, 20a53b8 , std::__ndk1::allocator > >(std::__ndk1::basic_string_view >, std::__ndk1::basic_string, std::__ndk1::allocator > const&)@@Base+0x14> │ │ - cdp2 1, 1, cr11, cr8, cr2, {4} │ │ - mrc2 1, 0, fp, cr8, cr14, {6} │ │ - cdp2 1, 1, cr11, cr8, cr12, {6} │ │ + cbz r1, 20a53c4 , std::__ndk1::allocator > >(std::__ndk1::basic_string_view >, std::__ndk1::basic_string, std::__ndk1::allocator > const&)@@Base+0x20> │ │ + cdp2 1, 1, cr11, cr8, cr15, {5} │ │ + cdp2 2, 1, cr11, cr8, cr11, {0} │ │ + mrc2 1, 0, fp, cr8, cr9, {7} │ │ mrc2 2, 0, r2, cr8, cr0, {6} │ │ lsls r1, r5, #1 │ │ │ │ 020a53a4 , std::__ndk1::allocator > >(std::__ndk1::basic_string_view >, std::__ndk1::basic_string, std::__ndk1::allocator > const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -60302,23 +60302,23 @@ │ │ ldrsh.w r3, [r2, #3891] @ 0xf33 │ │ subs r0, #160 @ 0xa0 │ │ ldrb r0, [r0, #26] │ │ itttt le │ │ suble r7, #249 @ 0xf9 │ │ movle r1, #84 @ 0x54 │ │ lslle r1, r5, #1 │ │ - ldrle r1, [r1, #80] @ 0x50 │ │ - mrc2 10, 0, ip, cr7, cr10, {3} @ │ │ + ldrle r6, [r6, #80] @ 0x50 │ │ + vselvs.f32 s24, s15, s15 │ │ mrc2 12, 0, lr, cr8, cr1, {4} │ │ mrc2 1, 0, r5, cr6, cr13, {4} │ │ cdp2 0, 1, cr4, cr7, cr11, {4} │ │ - cdp2 12, 1, cr6, cr10, cr3, {3} │ │ - mrc2 1, 0, r3, cr7, cr9, {3} │ │ - mrc2 15, 0, ip, cr8, cr2, {3} │ │ - cdp2 15, 1, cr12, cr7, cr14, {7} │ │ + mrc2 12, 0, r6, cr10, cr0, {4} │ │ + cdp2 1, 1, cr3, cr7, cr6, {5} │ │ + mrc2 15, 0, ip, cr8, cr15, {4} │ │ + mrc2 0, 0, sp, cr7, cr11, {0} │ │ mrc2 1, 0, r2, cr7, cr12, {2} │ │ lsls r1, r5, #1 │ │ movs r0, #102 @ 0x66 │ │ lsls r1, r5, #1 │ │ │ │ 020a56a8 (std::__ndk1::locale const&, std::__ndk1::basic_string_view >, float const&, float const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -60636,18 +60636,18 @@ │ │ stmia r3!, {r0, r2, r5, r6, r7} │ │ str r3, [sp, #204] @ 0xcc │ │ stmia r3!, {r3, r7} │ │ adds r6, r1, #5 │ │ lsls r1, r5, #1 │ │ adds r2, r7, #7 │ │ lsls r1, r5, #1 │ │ - lsls r4, r7, #22 │ │ + lsls r1, r5, #23 │ │ mrc2 13, 0, r1, cr9, cr12, {5} │ │ lsls r1, r5, #1 │ │ - ldr r5, [r3, #100] @ 0x64 │ │ + ldr r2, [r1, #104] @ 0x68 │ │ cdp2 13, 1, cr1, cr8, cr10, {4} │ │ lsls r1, r5, #1 │ │ lsrs r7, r7, #22 │ │ mrc2 12, 0, r1, cr7, cr0, {4} │ │ lsls r1, r5, #1 │ │ │ │ 020a59dc , std::__ndk1::basic_string, std::__ndk1::allocator > >(std::__ndk1::basic_string_view >, celestia::util::FormattedFloat const&, std::__ndk1::basic_string, std::__ndk1::allocator > const&)@@Base>: │ │ @@ -60876,19 +60876,19 @@ │ │ eors r6, r1 │ │ ldr r7, [r2, #64] @ 0x40 │ │ asrs r1, r0, #27 │ │ stmia r1!, {r2, r3, r5, r6} │ │ subs r7, #70 @ 0x46 │ │ subs r4, r4, r3 │ │ lsls r1, r5, #1 │ │ - add r3, sp, #900 @ 0x384 │ │ + add r4, sp, #56 @ 0x38 │ │ cdp2 13, 1, cr7, cr7, cr6, {3} │ │ - cdp2 7, 1, cr8, cr10, cr0, {4} │ │ - mrc2 9, 0, r0, cr7, cr0, {5} @ │ │ - cdp2 7, 1, cr8, cr8, cr10, {3} │ │ + cdp2 7, 1, cr8, cr10, cr13, {5} │ │ + mrc2 9, 0, r0, cr7, cr13, {6} @ │ │ + mrc2 7, 0, r8, cr8, cr7, {4} │ │ @ instruction: 0xfe171a44 │ │ lsls r1, r5, #1 │ │ │ │ 020a5c3c ::format_custom_arg, fmt::v11::formatter, char, void> >(void*, fmt::v11::basic_format_parse_context&, fmt::v11::context&)@@Base>: │ │ ldr r3, [r1, #4] │ │ cmp r3, #0 │ │ ittt ne │ │ @@ -60899,15 +60899,15 @@ │ │ mov r1, r2 │ │ b.w 26fe9d8 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (20a5c5c ::format_custom_arg, fmt::v11::formatter, char, void> >(void*, fmt::v11::basic_format_parse_context&, fmt::v11::context&)@@Base+0x20>) │ │ add r0, pc │ │ blx 27025b0 │ │ - str r4, [r5, #92] @ 0x5c │ │ + str r1, [r3, #96] @ 0x60 │ │ Address 0x20a5c5e is out of bounds. │ │ │ │ │ │ 020a5c60 ::format(fmt::v11::context&) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -61009,18 +61009,18 @@ │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ subs r4, r0, r1 │ │ lsls r1, r5, #1 │ │ adds r6, r6, r6 │ │ lsls r1, r5, #1 │ │ - add r7, pc, #768 @ (adr r7, 20a606c , std::__ndk1::allocator > >(std::__ndk1::locale const&, std::__ndk1::basic_string_view >, double const&, char const&, double const&, char const&, std::__ndk1::basic_string, std::__ndk1::allocator > const&)@@Base+0x30>) │ │ - cdp2 7, 1, cr10, cr8, cr12, {5} │ │ - vcmla.f16 d10, d8, d14[0], #90 │ │ - mrc2 7, 0, sl, cr8, cr10, {7} │ │ + add r7, pc, #948 @ (adr r7, 20a6120 (std::__ndk1::locale const&, std::__ndk1::basic_string_view >, int const&, int const&, double const&)@@Base+0x10>) │ │ + mrc2 7, 0, sl, cr8, cr9, {6} │ │ + vfmsl.f16 d10, s16, s7[1] │ │ + vcmla.f16 d10, d8, d7[1], #90 │ │ vfmsl.f16 , d24, d0[3] │ │ lsls r1, r5, #1 │ │ │ │ 020a5d7c , char const*>(std::__ndk1::basic_string_view >, celestia::util::FormattedFloat const&, char const* const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -61720,15 +61720,15 @@ │ │ blx 26ffb40 │ │ add r0, sp, #56 @ 0x38 │ │ bl 20a6a80 ::loadExtras(celestia::util::array_view)@@Base+0x2bc> │ │ blx 26ffb60 │ │ nop │ │ asrs r0, r3, #13 │ │ lsls r1, r5, #1 │ │ - movs r4, #192 @ 0xc0 │ │ + movs r4, #237 @ 0xed │ │ cdp2 0, 1, cr4, cr8, cr4, {2} │ │ cdp2 1, 1, cr1, cr9, cr12, {7} │ │ lsls r1, r5, #1 │ │ │ │ 020a64b4 ::process(std::__ndk1::__fs::filesystem::path const&, std::__ndk1::__fs::filesystem::path const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -62011,15 +62011,15 @@ │ │ mrc2 1, 0, r1, cr9, cr10, {0} │ │ lsls r1, r5, #1 │ │ lsrs r4, r2, #27 │ │ lsls r1, r5, #1 │ │ cbnz r6, 20a6828 ::loadExtras(celestia::util::array_view)@@Base+0x64> │ │ cdp2 0, 1, cr1, cr6, cr6, {6} │ │ lsls r1, r5, #1 │ │ - mcr2 14, 5, pc, cr3, cr7, {0} @ │ │ + mrc2 14, 6, pc, cr0, cr7, {0} │ │ lsrs r6, r6, #29 │ │ lsls r1, r5, #1 │ │ lsrs r2, r0, #29 │ │ lsls r1, r5, #1 │ │ │ │ 020a67c4 ::loadExtras(celestia::util::array_view)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -64159,15 +64159,15 @@ │ │ blx 26ffb40 │ │ add r0, sp, #44 @ 0x2c │ │ bl 20a849c ::loadExtras(celestia::util::array_view)@@Base+0x2bc> │ │ blx 26ffb60 │ │ nop │ │ vst4.16 {d0-d3}, [r6 :128], r8 │ │ stmia r4!, {r1, r4, r6, r7} │ │ - cdp2 5, 1, cr6, cr6, cr4, {7} │ │ + mrc2 6, 0, r6, cr6, cr1, {0} │ │ mrc2 7, 0, pc, cr7, cr12, {5} │ │ lsls r0, r5, #1 │ │ │ │ 020a7ed0 ::process(std::__ndk1::__fs::filesystem::path const&, std::__ndk1::__fs::filesystem::path const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -64447,15 +64447,15 @@ │ │ movs r4, #37 @ 0x25 │ │ mrc2 6, 0, pc, cr9, cr14, {7} │ │ lsls r0, r5, #1 │ │ @ instruction: 0xf4b80068 │ │ add r1, pc, #744 @ (adr r1, 20a84b8 ::loadExtras(celestia::util::array_view)@@Base+0x2d8>) │ │ cdp2 6, 1, cr15, cr6, cr10, {5} │ │ lsls r0, r5, #1 │ │ - b.n 20a7ae6 &, std::__ndk1::__fs::filesystem::path*, false>(std::__ndk1::__fs::filesystem::path*, std::__ndk1::__fs::filesystem::path*, std::__ndk1::__less&, std::__ndk1::iterator_traits::difference_type, bool)@@Base+0xf8a> │ │ + b.n 20a7b40 &, std::__ndk1::__fs::filesystem::path*, false>(std::__ndk1::__fs::filesystem::path*, std::__ndk1::__fs::filesystem::path*, std::__ndk1::__less&, std::__ndk1::iterator_traits::difference_type, bool)@@Base+0xfe4> │ │ mrc2 5, 0, pc, cr7, cr10, {2} │ │ lsls r0, r5, #1 │ │ @ instruction: 0xf5260068 │ │ │ │ 020a81e0 ::loadExtras(celestia::util::array_view)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -65228,15 +65228,15 @@ │ │ lsls r0, r0, #31 │ │ beq.n 20a8a42 │ │ ldr r0, [sp, #120] @ 0x78 │ │ blx 26ffb40 │ │ b.n 20a8a42 │ │ b.n 20a8a34 │ │ b.n 20a8a34 │ │ - subs r4, #34 @ 0x22 │ │ + subs r4, #79 @ 0x4f │ │ cdp2 0, 1, cr15, cr7, cr12, {0} │ │ lsls r0, r5, #1 │ │ vmla.i16 d16, d12, d0[3] │ │ b.n 20a8a42 │ │ b.n 20a8a34 │ │ b.n 20a8a18 │ │ add r0, sp, #112 @ 0x70 │ │ @@ -65269,20 +65269,20 @@ │ │ str r5, [sp, #304] @ 0x130 │ │ cdp2 12, 1, cr14, cr9, cr12, {7} │ │ lsls r0, r5, #1 │ │ ldcl 0, cr0, [r2], #-416 @ 0xfffffe60 │ │ lsls r1, r1, #10 │ │ mrc2 14, 0, lr, cr7, cr0, {7} │ │ lsls r0, r5, #1 │ │ - subs r3, #124 @ 0x7c │ │ + subs r3, #169 @ 0xa9 │ │ cdp2 15, 1, cr14, cr7, cr8, {3} │ │ lsls r0, r5, #1 │ │ cdp 0, 13, cr0, cr2, cr8, {3} │ │ ldr r4, [r3, #60] @ 0x3c │ │ - cdp2 15, 1, cr15, cr10, cr7, {5} │ │ + mrc2 15, 0, pc, cr10, cr4, {6} │ │ mrc2 5, 0, fp, cr7, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ sub sp, #216 @ 0xd8 │ │ mov r5, r2 │ │ ldr r2, [pc, #288] @ (20a8ba8 ) │ │ add r2, pc │ │ @@ -65689,15 +65689,15 @@ │ │ vselvs.f32 s28, s18, s20 │ │ lsls r0, r5, #1 │ │ b.n 20a8e48 ::process(std::__ndk1::__fs::filesystem::path const&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x284> │ │ lsls r0, r5, #1 │ │ str r4, [sp, #792] @ 0x318 │ │ mrc2 9, 0, lr, cr6, cr6, {5} @ │ │ lsls r0, r5, #1 │ │ - bvc.n 20a8df2 ::process(std::__ndk1::__fs::filesystem::path const&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x22e> │ │ + bvc.n 20a8e4c ::process(std::__ndk1::__fs::filesystem::path const&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x288> │ │ vcmla.f16 q7, , d6[1], #90 │ │ lsls r0, r5, #1 │ │ @ instruction: 0xe8320068 │ │ │ │ 020a8ed4 ::loadExtras(celestia::util::array_view)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -66094,15 +66094,15 @@ │ │ bmi.n 20a926e │ │ │ │ 020a92c4 : │ │ ldr r0, [pc, #4] @ (20a92cc ) │ │ add r0, pc │ │ bx lr │ │ nop │ │ - bl 1db9efe │ │ + bl 1de6efe │ │ │ │ 020a92d0 : │ │ cmp r0, #0 │ │ itt eq │ │ moveq r0, #22 │ │ bxeq lr │ │ cmp r1, #0 │ │ @@ -66673,15 +66673,15 @@ │ │ add r1, pc │ │ ldr.w r0, [r1, r0, lsl #2] │ │ bx lr │ │ ldr r0, [pc, #4] @ (20a97f4 ) │ │ add r0, pc │ │ bx lr │ │ nop │ │ - ldr r2, [pc, #208] @ (20a98c8 ) │ │ + ldr r2, [pc, #388] @ (20a997c ) │ │ mrc2 3, 0, r6, cr8, cr8, {1} │ │ lsls r7, r4, #1 │ │ │ │ 020a97fc : │ │ strd r1, r2, [r0] │ │ bx lr │ │ bmi.n 20a97ae │ │ @@ -68920,16 +68920,16 @@ │ │ movs r1, #3 │ │ add r2, pc │ │ mov r3, r4 │ │ blx 2702930 │ │ mov r0, r6 │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ - adds r4, #28 │ │ - cdp2 7, 1, cr11, cr8, cr12, {3} │ │ + adds r4, #73 @ 0x49 │ │ + mrc2 7, 0, fp, cr8, cr9, {4} │ │ Address 0x20aae42 is out of bounds. │ │ │ │ │ │ 020aae44 : │ │ mov r0, r1 │ │ b.w 26fea44 │ │ bmi.n 20aadf6 │ │ @@ -68959,16 +68959,16 @@ │ │ add r2, pc │ │ mov r3, r4 │ │ blx 2702930 │ │ mov r0, r6 │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ - str r7, [sp, #820] @ 0x334 │ │ - mrc2 3, 0, r1, cr7, cr4, {7} │ │ + str r7, [sp, #1000] @ 0x3e8 │ │ + cdp2 4, 1, cr1, cr7, cr1, {1} │ │ Address 0x20aae96 is out of bounds. │ │ │ │ │ │ 020aae98 : │ │ cbz r0, 20aaec6 │ │ ldr.w ip, [r0, #516] @ 0x204 │ │ cmp.w ip, #63 @ 0x3f │ │ @@ -69126,28 +69126,28 @@ │ │ cbz r4, 20ab008 │ │ ldr r1, [pc, #16] @ (20ab010 ) │ │ add r1, pc │ │ ldr.w r0, [r1, r0, lsl #3] │ │ str r0, [r4, #0] │ │ movs r0, #0 │ │ pop {r4, r5, r7, pc} │ │ - @ instruction: 0xb774 │ │ + @ instruction: 0xb7a1 │ │ @ instruction: 0xfe174a6c │ │ lsls r7, r4, #1 │ │ str r2, [r1, r4] │ │ - cdp2 3, 1, cr13, cr9, cr6, {2} │ │ - cdp2 1, 1, cr7, cr8, cr10, {0} │ │ + mrc2 3, 0, sp, cr9, cr3, {3} │ │ + mrc2 1, 0, r7, cr8, cr7, {1} │ │ vcmla.f16 , q12, d14[0], #90 │ │ mrc2 5, 0, r4, cr6, cr15, {1} │ │ cdp2 15, 1, cr6, cr10, cr13, {7} │ │ cdp2 15, 1, cr6, cr9, cr3, {7} │ │ mrc2 9, 0, r2, cr9, cr9, {4} @ │ │ mrc2 11, 0, sp, cr10, cr10, {3} @ │ │ vselvs.f16 s4, s13, s12 │ │ - cdp2 15, 1, cr10, cr10, cr10, {5} │ │ + mrc2 15, 0, sl, cr10, cr7, {6} │ │ mrc2 4, 0, pc, cr8, cr11, {3} │ │ cdp2 12, 1, cr8, cr8, cr3, {7} │ │ mrc2 2, 0, r9, cr9, cr1, {5} │ │ Address 0x20ab04a is out of bounds. │ │ │ │ │ │ 020ab04c : │ │ @@ -69793,17 +69793,17 @@ │ │ cmp r5, #0 │ │ beq.w 20ab4f2 │ │ mov r0, r8 │ │ mov r1, r5 │ │ blx 26fe3b4 │ │ b.n 20ab4f2 │ │ nop │ │ - str r2, [sp, #532] @ 0x214 │ │ - vselvs.f32 s20, s15, s10 │ │ - cdp2 2, 1, cr5, cr8, cr14, {6} │ │ + str r2, [sp, #712] @ 0x2c8 │ │ + mrc2 10, 0, sl, cr7, cr2, {5} @ │ │ + mrc2 2, 0, r5, cr8, cr11, {7} │ │ cdp2 15, 1, cr3, cr7, cr3, {4} │ │ cdp2 5, 1, cr15, cr10, cr13, {0} │ │ str r2, [r0, #12] │ │ movs r1, #0 │ │ mov r2, r5 │ │ blx 2702a80 │ │ cmp r0, #0 │ │ @@ -70974,36 +70974,36 @@ │ │ cdp2 2, 1, cr0, cr9, cr15, {3} │ │ movs r0, r0 │ │ str r6, [sp, #684] @ 0x2ac │ │ mrc2 12, 0, r0, cr9, cr3, {1} │ │ movs r0, r0 │ │ subs r0, #174 @ 0xae │ │ lsls r7, r4, #1 │ │ - strh r2, [r0, #36] @ 0x24 │ │ + strh r7, [r5, #36] @ 0x24 │ │ mrc2 7, 0, ip, cr7, cr11, {4} │ │ - cdp2 3, 1, cr10, cr6, cr6, {1} │ │ + mrc2 3, 0, sl, cr6, cr3, {2} │ │ cdp2 5, 1, cr9, cr7, cr10, {3} │ │ cdp2 7, 1, cr12, cr9, cr0, {6} │ │ - mrc2 12, 0, r9, cr6, cr8, {1} │ │ - mrc2 10, 0, r7, cr8, cr10, {6} @ │ │ + cdp2 12, 1, cr9, cr6, cr5, {3} │ │ + vselvs.f64 d7, d8, d7 │ │ mrc2 0, 0, lr, cr8, cr7, {6} │ │ cdp2 6, 1, cr1, cr8, cr11, {1} │ │ - mrc2 0, 0, r2, cr10, cr1, {3} │ │ + mrc2 0, 0, r2, cr10, cr14, {4} │ │ mrc2 14, 0, r5, cr7, cr12, {4} │ │ mrc2 3, 0, fp, cr6, cr12, {7} │ │ lsls r0, r5, #1 │ │ asrs r0, r5, #27 │ │ vfmsl.f16 , d10, d0[2] │ │ lsls r7, r4, #1 │ │ - lsls r0, r4, #22 │ │ + lsls r5, r1, #23 │ │ cdp2 6, 1, cr1, cr8, cr10, {5} │ │ - cdp2 4, 1, cr8, cr10, cr4, {4} │ │ + mrc2 4, 0, r8, cr10, cr1, {5} │ │ vselvs.f16 s6, s15, s25 │ │ lsls r7, r4, #1 │ │ - strh r2, [r5, #44] @ 0x2c │ │ + strh r7, [r2, #46] @ 0x2e │ │ mrc2 5, 0, fp, cr7, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ sub sp, #24 │ │ mov r4, r0 │ │ ldr.w r0, [pc, #2372] @ 20accfc │ │ mov r8, r2 │ │ @@ -71027,16 +71027,16 @@ │ │ movs r1, #0 │ │ mov.w r9, #0 │ │ blx 2702a10 │ │ cmp r0, #0 │ │ beq.w 20accbc │ │ b.n 20ac3fc │ │ nop │ │ - subs r4, r2, #1 │ │ - cdp2 15, 1, cr1, cr8, cr7, {5} │ │ + subs r1, r0, #2 │ │ + mrc2 15, 0, r1, cr8, cr4, {6} │ │ vselvs.f32 s8, s14, s20 │ │ mov r6, r0 │ │ ldr r5, [pc, #40] @ (20ac42c ) │ │ movs r1, #4 │ │ ldr.w r9, [r4, #56] @ 0x38 │ │ add r2, pc │ │ add r5, pc │ │ @@ -71047,26 +71047,26 @@ │ │ mov r0, r6 │ │ mov r1, r5 │ │ blx 2702a40 │ │ mov r5, r0 │ │ cbnz r0, 20ac44c │ │ b.n 20ac430 │ │ nop │ │ - strh r1, [r4, #16] │ │ + strh r6, [r1, #18] │ │ cdp2 6, 1, cr12, cr7, cr11, {7} │ │ vselvs.f32 s8, s12, s8 │ │ mov r0, r9 │ │ ldr r3, [pc, #16] @ (20ac448 ) │ │ movs r1, #2 │ │ add r2, pc │ │ add r3, pc │ │ blx 2702930 │ │ b.n 20ac44c │ │ nop │ │ - mrc2 14, 1, pc, cr10, cr6, {0} │ │ + mcr2 14, 3, pc, cr7, cr6, {0} @ │ │ stmia r6!, {r0, r1, r3, r4, r5, r7} │ │ vselvs.f32 s8, s12, s20 │ │ movs r1, #4 │ │ ldr r6, [pc, #40] @ (20ac47c ) │ │ ldr.w r9, [r4, #56] @ 0x38 │ │ add r2, pc │ │ add r6, pc │ │ @@ -71077,27 +71077,27 @@ │ │ blx 2702930 │ │ mov r0, sl │ │ mov r1, r6 │ │ blx 2702a40 │ │ mov r5, r0 │ │ cbnz r0, 20ac49c │ │ b.n 20ac480 │ │ - strh r3, [r2, #14] │ │ - mrc2 15, 0, r1, cr7, cr2, {1} │ │ + strh r0, [r0, #16] │ │ + mrc2 15, 0, r1, cr7, cr15, {2} │ │ vselvs.f32 s8, s14, s8 │ │ mov r0, r9 │ │ ldr r3, [pc, #16] @ (20ac498 ) │ │ movs r1, #2 │ │ add r2, pc │ │ add r3, pc │ │ blx 2702930 │ │ b.n 20ac49c │ │ nop │ │ - stc2l 14, cr15, [sl, #88]! @ 0x58 │ │ - subs r0, r0, #4 │ │ + mrc2 14, 0, pc, cr7, cr6, {0} │ │ + subs r5, r5, #4 │ │ vselvs.f32 s8, s14, s20 │ │ movs r1, #4 │ │ ldr r6, [pc, #40] @ (20ac4cc ) │ │ ldr.w r9, [r4, #56] @ 0x38 │ │ add r2, pc │ │ add r6, pc │ │ ldr.w sl, [r4, #168] @ 0xa8 │ │ @@ -71107,26 +71107,26 @@ │ │ blx 2702930 │ │ mov r0, sl │ │ mov r1, r6 │ │ blx 2702a40 │ │ mov r5, r0 │ │ cbnz r0, 20ac4ec │ │ b.n 20ac4d0 │ │ - strh r3, [r0, #12] │ │ + strh r0, [r6, #12] │ │ cdp2 4, 1, cr1, cr7, cr7, {3} │ │ vselvs.f32 s8, s20, s8 │ │ mov r0, r9 │ │ ldr r3, [pc, #16] @ (20ac4e8 ) │ │ movs r1, #2 │ │ add r2, pc │ │ add r3, pc │ │ blx 2702930 │ │ b.n 20ac4ec │ │ nop │ │ - ldc2 14, cr15, [sl, #88] @ 0x58 │ │ + stc2l 14, cr15, [r7, #88] @ 0x58 │ │ asrs r5, r6, #16 │ │ vselvs.f32 s8, s20, s20 │ │ movs r1, #4 │ │ ldr r6, [pc, #40] @ (20ac51c ) │ │ ldr.w r9, [r4, #56] @ 0x38 │ │ add r2, pc │ │ add r6, pc │ │ @@ -71137,27 +71137,27 @@ │ │ blx 2702930 │ │ mov r0, sl │ │ mov r1, r6 │ │ blx 2702a40 │ │ mov r5, r0 │ │ cbnz r0, 20ac53c │ │ b.n 20ac520 │ │ - strh r3, [r6, #8] │ │ - @ instruction: 0xfe179a4a │ │ + strh r0, [r4, #10] │ │ + mrc2 10, 0, r9, cr7, cr7, {3} @ │ │ vselvs.f32 s8, s16, s8 │ │ mov r0, r9 │ │ ldr r3, [pc, #16] @ (20ac538 ) │ │ movs r1, #2 │ │ add r2, pc │ │ add r3, pc │ │ blx 2702930 │ │ b.n 20ac53c │ │ nop │ │ - stc2l 14, cr15, [sl, #-88] @ 0xffffffa8 │ │ - ldr r2, [sp, #96] @ 0x60 │ │ + ldc2l 14, cr15, [r7, #-88]! @ 0xffffffa8 │ │ + ldr r2, [sp, #276] @ 0x114 │ │ vselvs.f32 s8, s16, s20 │ │ movs r1, #4 │ │ ldr r6, [pc, #40] @ (20ac56c ) │ │ ldr.w r9, [r4, #56] @ 0x38 │ │ add r2, pc │ │ add r6, pc │ │ ldr.w sl, [r4, #168] @ 0xa8 │ │ @@ -71167,26 +71167,26 @@ │ │ blx 2702930 │ │ mov r0, sl │ │ mov r1, r6 │ │ blx 2702a40 │ │ mov r5, r0 │ │ cbnz r0, 20ac58c │ │ b.n 20ac570 │ │ - strh r3, [r4, #6] │ │ + strh r0, [r2, #8] │ │ cdp2 7, 1, cr7, cr7, cr8, {2} │ │ vselvs.f32 s8, s18, s8 │ │ mov r0, r9 │ │ ldr r3, [pc, #16] @ (20ac588 ) │ │ movs r1, #2 │ │ add r2, pc │ │ add r3, pc │ │ blx 2702930 │ │ b.n 20ac58c │ │ nop │ │ - ldc2l 14, cr15, [sl], #88 @ 0x58 │ │ + stc2 14, cr15, [r7, #-88]! @ 0xffffffa8 │ │ strb r6, [r2, #28] │ │ vselvs.f32 s8, s18, s20 │ │ movs r1, #4 │ │ ldr r6, [pc, #40] @ (20ac5bc ) │ │ ldr.w r9, [r4, #56] @ 0x38 │ │ add r2, pc │ │ add r6, pc │ │ @@ -71197,27 +71197,27 @@ │ │ blx 2702930 │ │ mov r0, sl │ │ mov r1, r6 │ │ blx 2702a40 │ │ mov r5, r0 │ │ cbnz r0, 20ac5dc │ │ b.n 20ac5c0 │ │ - strh r3, [r2, #4] │ │ - mrc2 1, 0, r8, cr7, cr10, {4} │ │ + strh r0, [r0, #6] │ │ + cdp2 1, 1, cr8, cr7, cr7, {6} │ │ vselvs.f32 s8, s14, s8 │ │ mov r0, r9 │ │ ldr r3, [pc, #16] @ (20ac5d8 ) │ │ movs r1, #2 │ │ add r2, pc │ │ add r3, pc │ │ blx 2702930 │ │ b.n 20ac5dc │ │ nop │ │ - stc2 14, cr15, [sl], #88 @ 0x58 │ │ - strh r0, [r5, #10] │ │ + ldc2l 14, cr15, [r7], {22} │ │ + strh r5, [r2, #12] │ │ vselvs.f32 s8, s14, s20 │ │ movs r1, #4 │ │ ldr r6, [pc, #40] @ (20ac60c ) │ │ ldr.w r9, [r4, #56] @ 0x38 │ │ add r2, pc │ │ add r6, pc │ │ ldr.w sl, [r4, #168] @ 0xa8 │ │ @@ -71227,26 +71227,26 @@ │ │ blx 2702930 │ │ mov r0, sl │ │ mov r1, r6 │ │ blx 2702a40 │ │ mov r5, r0 │ │ cbnz r0, 20ac62c │ │ b.n 20ac610 │ │ - strh r3, [r0, #2] │ │ + strh r0, [r6, #2] │ │ mrc2 0, 0, sp, cr7, cr0, {3} │ │ vselvs.f32 s8, s18, s8 │ │ mov r0, r9 │ │ ldr r3, [pc, #16] @ (20ac628 ) │ │ movs r1, #2 │ │ add r2, pc │ │ add r3, pc │ │ blx 2702930 │ │ b.n 20ac62c │ │ nop │ │ - mrrc2 14, 1, pc, sl, cr6 @ │ │ + stc2 14, cr15, [r7], {22} │ │ beq.n 20ac6a8 │ │ vselvs.f32 s8, s18, s20 │ │ movs r1, #4 │ │ ldr r6, [pc, #40] @ (20ac65c ) │ │ ldr.w r9, [r4, #56] @ 0x38 │ │ add r2, pc │ │ add r6, pc │ │ @@ -71257,26 +71257,26 @@ │ │ blx 2702930 │ │ mov r0, sl │ │ mov r1, r6 │ │ blx 2702a40 │ │ mov r5, r0 │ │ cbnz r0, 20ac67c │ │ b.n 20ac660 │ │ - ldrb r3, [r6, #31] │ │ + strh r0, [r4, #0] │ │ mrc2 1, 0, sl, cr7, cr2, {4} │ │ vselvs.f32 s8, s12, s8 │ │ mov r0, r9 │ │ ldr r3, [pc, #16] @ (20ac678 ) │ │ movs r1, #2 │ │ add r2, pc │ │ add r3, pc │ │ blx 2702930 │ │ b.n 20ac67c │ │ nop │ │ - stc2 14, cr15, [sl], {22} │ │ + ldc2 14, cr15, [r7], #-88 @ 0xffffffa8 │ │ add r1, pc, #384 @ (adr r1, 20ac7fc ) │ │ vselvs.f32 s8, s12, s20 │ │ movs r1, #4 │ │ ldr r6, [pc, #40] @ (20ac6ac ) │ │ ldr.w r9, [r4, #56] @ 0x38 │ │ add r2, pc │ │ add r6, pc │ │ @@ -71287,26 +71287,26 @@ │ │ blx 2702930 │ │ mov r0, sl │ │ mov r1, r6 │ │ blx 2702a40 │ │ mov r5, r0 │ │ cbnz r0, 20ac6cc │ │ b.n 20ac6b0 │ │ - ldrb r3, [r4, #30] │ │ + ldrb r0, [r2, #31] │ │ mrc2 10, 0, pc, cr7, cr10, {5} @ │ │ vselvs.f32 s8, s16, s8 │ │ mov r0, r9 │ │ ldr r3, [pc, #16] @ (20ac6c8 ) │ │ movs r1, #2 │ │ add r2, pc │ │ add r3, pc │ │ blx 2702930 │ │ b.n 20ac6cc │ │ nop │ │ - @ instruction: 0xfbbafe16 │ │ + @ instruction: 0xfbe7fe16 │ │ qadd8 lr, r8, r8 │ │ ldr r2, [pc, #40] @ (20ac6f8 ) │ │ movs r1, #4 │ │ ldr r6, [pc, #40] @ (20ac6fc ) │ │ ldr.w r9, [r4, #56] @ 0x38 │ │ add r2, pc │ │ add r6, pc │ │ @@ -71317,26 +71317,26 @@ │ │ blx 2702930 │ │ mov r0, sl │ │ mov r1, r6 │ │ blx 2702a40 │ │ mov r5, r0 │ │ cbnz r0, 20ac71c │ │ b.n 20ac700 │ │ - ldrb r3, [r2, #29] │ │ + ldrb r0, [r0, #30] │ │ mrc2 4, 0, ip, cr7, cr8, {1} │ │ vselvs.f32 s8, s12, s8 │ │ mov r0, r9 │ │ ldr r3, [pc, #16] @ (20ac718 ) │ │ movs r1, #2 │ │ add r2, pc │ │ add r3, pc │ │ blx 2702930 │ │ b.n 20ac71c │ │ nop │ │ - smmlsr lr, sl, r6, pc @ │ │ + @ instruction: 0xfb97fe16 │ │ stmia r4!, {r1, r2} │ │ vselvs.f32 s8, s12, s20 │ │ movs r1, #4 │ │ ldr r6, [pc, #40] @ (20ac74c ) │ │ ldr.w r9, [r4, #56] @ 0x38 │ │ add r2, pc │ │ add r6, pc │ │ @@ -71347,26 +71347,26 @@ │ │ blx 2702930 │ │ mov r0, sl │ │ mov r1, r6 │ │ blx 2702a40 │ │ mov r5, r0 │ │ cbnz r0, 20ac76c │ │ b.n 20ac750 │ │ - ldrb r3, [r0, #28] │ │ + ldrb r0, [r6, #28] │ │ cdp2 12, 1, cr1, cr7, cr5, {5} │ │ vselvs.f32 s8, s18, s8 │ │ mov r0, r9 │ │ ldr r3, [pc, #16] @ (20ac768 ) │ │ movs r1, #2 │ │ add r2, pc │ │ add r3, pc │ │ blx 2702930 │ │ b.n 20ac76c │ │ nop │ │ - smulbt lr, sl, r6 │ │ + smusdx lr, r7, r6 │ │ adds r3, r6, #1 │ │ vselvs.f32 s8, s18, s20 │ │ movs r1, #4 │ │ ldr r6, [pc, #40] @ (20ac79c ) │ │ ldr.w r9, [r4, #56] @ 0x38 │ │ add r2, pc │ │ add r6, pc │ │ @@ -71377,26 +71377,26 @@ │ │ blx 2702930 │ │ mov r0, sl │ │ mov r1, r6 │ │ blx 2702a40 │ │ mov r5, r0 │ │ cbnz r0, 20ac7bc │ │ b.n 20ac7a0 │ │ - ldrb r3, [r6, #26] │ │ + ldrb r0, [r4, #27] │ │ mrc2 0, 0, lr, cr7, cr0, {4} │ │ vselvs.f32 s8, s12, s8 │ │ mov r0, r9 │ │ ldr r3, [pc, #16] @ (20ac7b8 ) │ │ movs r1, #2 │ │ add r2, pc │ │ add r3, pc │ │ blx 2702930 │ │ b.n 20ac7bc │ │ nop │ │ - qsub8 lr, sl, r6 │ │ + @ instruction: 0xfaf7fe16 │ │ b.n 20ac878 │ │ vselvs.f32 s8, s12, s20 │ │ movs r1, #4 │ │ ldr r6, [pc, #40] @ (20ac7ec ) │ │ ldr.w r9, [r4, #56] @ 0x38 │ │ add r2, pc │ │ add r6, pc │ │ @@ -71407,27 +71407,27 @@ │ │ blx 2702930 │ │ mov r0, sl │ │ mov r1, r6 │ │ blx 2702a40 │ │ mov r5, r0 │ │ cbnz r0, 20ac80c │ │ b.n 20ac7f0 │ │ - ldrb r3, [r4, #25] │ │ - mrc2 10, 0, r1, cr7, cr7, {5} @ │ │ + ldrb r0, [r2, #26] │ │ + @ instruction: 0xfe171ae4 │ │ vselvs.f32 s8, s16, s8 │ │ mov r0, r9 │ │ ldr r3, [pc, #16] @ (20ac808 ) │ │ movs r1, #2 │ │ add r2, pc │ │ add r3, pc │ │ blx 2702930 │ │ b.n 20ac80c │ │ nop │ │ - @ instruction: 0xfa7afe16 │ │ - subs r5, r0, r2 │ │ + qasx lr, r7, r6 │ │ + subs r2, r6, r2 │ │ vselvs.f32 s8, s16, s20 │ │ movs r1, #4 │ │ ldr r6, [pc, #40] @ (20ac83c ) │ │ ldr.w r9, [r4, #56] @ 0x38 │ │ add r2, pc │ │ add r6, pc │ │ ldr.w sl, [r4, #168] @ 0xa8 │ │ @@ -71437,26 +71437,26 @@ │ │ blx 2702930 │ │ mov r0, sl │ │ mov r1, r6 │ │ blx 2702a40 │ │ mov r5, r0 │ │ cbnz r0, 20ac85c │ │ b.n 20ac840 │ │ - ldrb r3, [r2, #24] │ │ + ldrb r0, [r0, #25] │ │ mrc2 0, 0, lr, cr7, cr5, {0} │ │ vselvs.f32 s8, s12, s8 │ │ mov r0, r9 │ │ ldr r3, [pc, #16] @ (20ac858 ) │ │ movs r1, #2 │ │ add r2, pc │ │ add r3, pc │ │ blx 2702930 │ │ b.n 20ac85c │ │ nop │ │ - @ instruction: 0xfa2afe16 │ │ + @ instruction: 0xfa57fe16 │ │ svc 227 @ 0xe3 │ │ vselvs.f32 s8, s12, s20 │ │ movs r1, #4 │ │ ldr r6, [pc, #40] @ (20ac88c ) │ │ ldr.w r9, [r4, #56] @ 0x38 │ │ add r2, pc │ │ add r6, pc │ │ @@ -71467,27 +71467,27 @@ │ │ blx 2702930 │ │ mov r0, sl │ │ mov r1, r6 │ │ blx 2702a40 │ │ mov r5, r0 │ │ cbnz r0, 20ac8ac │ │ b.n 20ac890 │ │ - ldrb r3, [r0, #23] │ │ - mrc2 15, 0, r3, cr7, cr0, {0} │ │ + ldrb r0, [r6, #23] │ │ + mrc2 15, 0, r3, cr7, cr13, {1} │ │ vselvs.f32 s8, s14, s8 │ │ mov r0, r9 │ │ ldr r3, [pc, #16] @ (20ac8a8 ) │ │ movs r1, #2 │ │ add r2, pc │ │ add r3, pc │ │ blx 2702930 │ │ b.n 20ac8ac │ │ nop │ │ - ldr??.w pc, [sl, #3606] @ 0xe16 │ │ - subs r6, #222 @ 0xde │ │ + @ instruction: 0xfa07fe16 │ │ + subs r7, #11 │ │ vselvs.f32 s8, s14, s20 │ │ movs r1, #4 │ │ ldr r6, [pc, #40] @ (20ac8dc ) │ │ ldr.w r9, [r4, #56] @ 0x38 │ │ add r2, pc │ │ add r6, pc │ │ ldr.w sl, [r4, #168] @ 0xa8 │ │ @@ -71497,16 +71497,16 @@ │ │ blx 2702930 │ │ mov r0, sl │ │ mov r1, r6 │ │ blx 2702a40 │ │ mov r5, r0 │ │ cbnz r0, 20ac8f0 │ │ b.n 20ac8e0 │ │ - ldrb r3, [r6, #21] │ │ - @ instruction: 0xfe171aed │ │ + ldrb r0, [r4, #22] │ │ + mrc2 11, 0, r1, cr7, cr10, {0} @ │ │ @ instruction: 0xfe174aee │ │ mov r0, r9 │ │ ldr r3, [pc, #952] @ (20acca0 ) │ │ movs r1, #2 │ │ add r2, pc │ │ add r3, pc │ │ blx 2702930 │ │ @@ -71870,21 +71870,21 @@ │ │ mov r1, sl │ │ blx 27029e0 │ │ ldr.w r0, [r4, #168] @ 0xa8 │ │ blx 2702a20 │ │ mov r0, r6 │ │ str.w r9, [r4, #168] @ 0xa8 │ │ b.n 20accd8 │ │ - vst3. @ instruction: 0xf98afe16 │ │ - subs r3, r7, r2 │ │ - cdp2 13, 1, cr7, cr7, cr15, {1} │ │ - vselvs.f16 s2, s15, s21 │ │ - mrc2 9, 0, pc, cr8, cr0, {2} @ │ │ - vselvs.f16 s2, s13, s4 │ │ - mrc2 12, 0, r7, cr8, cr5, {7} │ │ + ldrsh.w pc, [r7, #3606] @ 0xe16 │ │ + subs r0, r5, r3 │ │ + mrc2 13, 0, r7, cr7, cr12, {2} │ │ + mrc2 9, 0, r1, cr7, cr7, {6} @ │ │ + mrc2 9, 0, pc, cr8, cr13, {3} @ │ │ + vselvs.f16 s2, s13, s31 │ │ + cdp2 13, 1, cr7, cr8, cr2, {1} │ │ mrc2 14, 0, r9, cr7, cr6, {5} │ │ mrc2 10, 0, r4, cr6, cr0, {0} @ │ │ mov r0, r6 │ │ ldr r3, [pc, #64] @ (20acd04 ) │ │ movs r1, #3 │ │ add r2, pc │ │ add r3, pc │ │ @@ -71905,61 +71905,61 @@ │ │ blx 26ffb50 │ │ movs r0, #1 │ │ str.w r0, [r4, #376] @ 0x178 │ │ movs r0, #0 │ │ b.n 20accd8 │ │ sxtb r0, r6 │ │ lsls r0, r5, #1 │ │ - ldr r0, [sp, #848] @ 0x350 │ │ - mrc2 6, 0, r1, cr7, cr7, {5} │ │ - mrc2 9, 0, pc, cr7, cr6, {0} @ │ │ + ldr r1, [sp, #4] │ │ + cdp2 6, 1, cr1, cr7, cr4, {7} │ │ + @ instruction: 0xfe17f943 │ │ cdp2 14, 1, cr9, cr6, cr14, {4} │ │ - mrc2 12, 0, r7, cr6, cr11, {5} │ │ - mrc2 12, 0, r5, cr7, cr13, {2} │ │ - vfmsl.f16 , d23, d4[1] │ │ - mrc2 12, 0, r5, cr6, cr5, {1} │ │ - cdp2 12, 1, cr7, cr7, cr1, {4} │ │ - cdp2 13, 1, cr7, cr7, cr6, {5} │ │ - vcmla.f16 d15, d23, d2[1], #90 │ │ - mrc2 13, 0, r7, cr6, cr14, {3} │ │ - cdp2 12, 1, cr7, cr7, cr7, {2} │ │ - mrc2 14, 0, pc, cr7, cr2, {3} │ │ - vcmla.f16 , , d8[1], #90 │ │ - cdp2 14, 1, cr15, cr6, cr10, {2} │ │ - cdp2 12, 1, cr7, cr7, cr13, {0} │ │ - vfmsl.f16 , d23, d7[3] │ │ - vcmla.f16 d15, d6, d14[1], #90 │ │ - vfmsl.f16 , d22, d7[0] │ │ - mrc2 11, 0, r7, cr6, cr3, {6} @ │ │ + cdp2 12, 1, cr7, cr6, cr8, {7} │ │ + cdp2 12, 1, cr5, cr7, cr10, {4} │ │ + vselvs.f16 s30, s14, s18 │ │ + cdp2 12, 1, cr5, cr6, cr2, {3} │ │ + cdp2 12, 1, cr7, cr7, cr14, {5} │ │ + mrc2 13, 0, r7, cr7, cr3, {6} │ │ + vcmla.f16 , , d15[0], #90 │ │ + cdp2 13, 1, cr7, cr6, cr11, {5} │ │ + mrc2 12, 0, r7, cr7, cr4, {3} │ │ + mrc2 14, 0, pc, cr7, cr15, {4} │ │ + vfmsl.f16 d15, s15, s10[0] │ │ + mrc2 14, 0, pc, cr6, cr7, {3} │ │ + mrc2 12, 0, r7, cr7, cr10, {1} │ │ + vselvs.f16 s30, s14, s25 │ │ + vfmsl.f16 , d6, d3[1] │ │ + vselvs.f16 s30, s12, s8 │ │ + cdp2 12, 1, cr7, cr6, cr0, {0} │ │ mrc2 4, 0, r5, cr7, cr4, {7} │ │ - mrc2 7, 0, pc, cr9, cr4, {7} │ │ + vcmla.f16 d15, d9, d1[1], #90 │ │ cdp2 4, 1, cr5, cr6, cr12, {6} │ │ - mrc2 11, 0, r7, cr9, cr9, {4} @ │ │ + @ instruction: 0xfe197bc6 │ │ cdp2 7, 1, cr5, cr7, cr12, {2} │ │ - mrc2 7, 0, pc, cr6, cr10, {5} │ │ + cdp2 7, 1, cr15, cr6, cr7, {7} │ │ cdp2 7, 1, cr5, cr6, cr4, {1} │ │ - mrc2 11, 0, r7, cr6, cr15, {2} @ │ │ + vselvs.f64 d7, d22, d12 │ │ mrc2 11, 0, ip, cr7, cr0, {5} @ │ │ - cdp2 7, 1, cr15, cr9, cr0, {4} │ │ + cdp2 7, 1, cr15, cr9, cr13, {5} │ │ vselvs.f64 d12, d22, d8 │ │ - vselvs.f64 d7, d9, d21 │ │ + mrc2 11, 0, r7, cr9, cr2, {2} @ │ │ mrc2 6, 0, r5, cr7, cr3, {7} │ │ - cdp2 7, 1, cr15, cr6, cr6, {2} │ │ + mrc2 7, 0, pc, cr6, cr3, {3} │ │ cdp2 6, 1, cr5, cr6, cr11, {6} │ │ - @ instruction: 0xfe167aeb │ │ - cdp2 7, 1, cr11, cr7, cr4, {1} │ │ - cdp2 7, 1, cr15, cr8, cr12, {0} │ │ - mrc2 6, 0, fp, cr6, cr12, {7} │ │ - mrc2 10, 0, r7, cr8, cr1, {5} @ │ │ - @ instruction: 0xfe175a66 │ │ - mrc2 6, 0, pc, cr7, cr2, {6} │ │ - mrc2 10, 0, r5, cr6, cr14, {1} @ │ │ - mrc2 10, 0, r7, cr7, cr7, {3} @ │ │ + mrc2 11, 0, r7, cr6, cr8, {0} @ │ │ + mrc2 7, 0, fp, cr7, cr1, {2} │ │ + mrc2 7, 0, pc, cr8, cr9, {1} │ │ + cdp2 7, 1, cr11, cr6, cr9, {1} │ │ + mrc2 10, 0, r7, cr8, cr14, {6} @ │ │ + mrc2 10, 0, r5, cr7, cr3, {4} @ │ │ + mrc2 6, 0, pc, cr7, cr15, {7} │ │ + @ instruction: 0xfe165a6b │ │ + vselvs.f32 s14, s15, s9 │ │ mrc2 12, 0, r9, cr7, cr7, {2} │ │ - mrc2 6, 0, pc, cr6, cr8, {4} │ │ + cdp2 6, 1, cr15, cr6, cr5, {6} │ │ cdp2 12, 1, cr9, cr6, cr15, {1} │ │ cdp2 1, 1, cr0, cr6, cr13, {5} │ │ movs r4, r0 │ │ ldr.w r0, [r5, #3] │ │ strb.w r0, [fp, #3] │ │ @ instruction: 0xf7e70003 │ │ lsls r1, r2, #1 │ │ @@ -72216,33 +72216,33 @@ │ │ str.w r1, [r8, #40] @ 0x28 │ │ strd r5, r4, [r8, #8] │ │ strd r3, lr, [r8, #16] │ │ strd r2, ip, [r8, #24] │ │ ldmia.w sp!, {r8, r9, fp} │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ - asrs r6, r3, #16 │ │ + asrs r3, r1, #17 │ │ @ instruction: 0xfe188ac6 │ │ - mrc2 6, 0, r9, cr9, cr0, {2} │ │ + mrc2 6, 0, r9, cr9, cr13, {3} │ │ vselvs.f16 s16, s15, s16 │ │ cdp2 14, 1, cr10, cr9, cr14, {4} │ │ - mrc2 7, 0, r7, cr9, cr9, {7} │ │ + vcmla.f16 d7, d9, d6[1], #90 │ │ vselvs.f32 s16, s15, s31 │ │ - mrc2 3, 0, pc, cr9, cr2, {2} │ │ + mrc2 3, 0, pc, cr9, cr15, {3} │ │ mrc2 9, 0, sp, cr6, cr10, {1} @ │ │ - cdp2 7, 1, cr7, cr6, cr13, {6} │ │ - vfmsl.f16 d9, s14, s10[0] │ │ - cdp2 7, 1, cr7, cr7, cr1, {5} │ │ + mrc2 7, 0, r7, cr6, cr10, {7} │ │ + vcmla.f16 , , d2[0], #90 │ │ + cdp2 7, 1, cr7, cr7, cr14, {6} │ │ mrc2 9, 0, sp, cr7, cr12, {5} @ │ │ - mrc2 7, 0, r7, cr6, cr7, {3} │ │ + cdp2 7, 1, cr7, cr6, cr4, {5} │ │ cdp2 1, 1, cr3, cr7, cr8, {3} │ │ - cdp2 4, 1, cr15, cr9, cr0, {3} │ │ + cdp2 4, 1, cr15, cr9, cr13, {4} │ │ @ instruction: 0xfe160a45 │ │ - mrc2 9, 0, fp, cr10, cr6, {1} @ │ │ - vfmsl.f16 , d23, d0[0] │ │ + @ instruction: 0xfe1ab963 │ │ + vfmsl.f16 , d23, d5[3] │ │ mrc2 11, 0, r0, cr7, cr14, {0} @ │ │ lsls r3, r5, #1 │ │ ldr r7, [pc, #364] @ (20ad234 ) │ │ mrc2 13, 0, r0, cr9, cr1, {6} │ │ movs r4, r0 │ │ lsrs r1, r1, #10 │ │ movs r4, r0 │ │ @@ -72253,15 +72253,15 @@ │ │ lsls r1, r4, #3 │ │ movs r4, r0 │ │ lsls r7, r6, #1 │ │ movs r4, r0 │ │ lsrs r7, r7, #11 │ │ movs r4, r0 │ │ ldc2 15, cr15, [r9, #1020] @ 0x3fc │ │ - @ instruction: 0xb826 │ │ + @ instruction: 0xb853 │ │ mrc2 5, 0, fp, cr7, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ ldr r5, [pc, #72] @ (20ad140 ) │ │ mov.w ip, #0 │ │ ldr r0, [pc, #72] @ (20ad144 ) │ │ add r5, pc │ │ @@ -73325,33 +73325,33 @@ │ │ b.n 20adc8c │ │ nop │ │ lsrs r7, r1, #12 │ │ movs r0, r0 │ │ vacgt.f32 d31, d4, d9 │ │ movs r1, #46 @ 0x2e │ │ lsls r7, r4, #1 │ │ - str r6, [r2, #68] @ 0x44 │ │ + str r3, [r0, #72] @ 0x48 │ │ vfmsl.f16 d4, s16, s4[1] │ │ mrc2 10, 0, ip, cr6, cr3, {1} @ │ │ cdp2 14, 1, cr13, cr8, cr8, {4} │ │ - @ instruction: 0xfe194bee │ │ + mrc2 12, 0, r4, cr9, cr11, {0} │ │ mrc2 1, 0, r2, cr7, cr4, {3} │ │ lsls r7, r4, #1 │ │ ldr r1, [r1, #4] │ │ cdp2 1, 1, cr2, cr6, cr14, {0} │ │ lsls r7, r4, #1 │ │ ldr r3, [r6, #0] │ │ - mrc2 3, 0, r6, cr6, cr6, {3} │ │ - vfmsl.f16 d14, s16, s11[1] │ │ + cdp2 3, 1, cr6, cr6, cr3, {5} │ │ + vcmla.f16 q7, q4, d10[1], #90 │ │ cdp2 4, 1, cr4, cr6, cr4, {2} │ │ - cdp2 13, 1, cr10, cr9, cr14, {2} │ │ - vcmla.f16 d0, d23, d11[1], #90 │ │ - cdp2 7, 1, cr10, cr7, cr4, {0} │ │ + mrc2 13, 0, sl, cr9, cr11, {3} │ │ + vfmsl.f16 q0, d23, d0[1] │ │ + mrc2 7, 0, sl, cr7, cr1, {1} │ │ cdp2 13, 1, cr7, cr8, cr10, {1} │ │ - vselvs.f64 d6, d25, d2 │ │ + vselvs.f64 d6, d25, d31 │ │ cdp2 13, 1, cr7, cr7, cr4, {0} │ │ vselvs.f16 s8, s19, s25 │ │ add r1, pc │ │ ldr r2, [pc, #692] @ (20adf44 ) │ │ str r1, [sp, #0] │ │ movs r1, #3 │ │ add r2, pc │ │ @@ -73586,36 +73586,36 @@ │ │ b.w 20ad558 │ │ add r1, pc, #336 @ (adr r1, 20ae064 ) │ │ lsls r0, r5, #1 │ │ add r0, pc, #816 @ (adr r0, 20ae248 ) │ │ lsls r0, r5, #1 │ │ ldr r2, [pc, #256] @ (20ae01c ) │ │ @ instruction: 0xfe1a49ca │ │ - @ instruction: 0xfe1a8ac0 │ │ - mrc2 9, 0, r2, cr7, cr4, {1} @ │ │ + @ instruction: 0xfe1a8aed │ │ + @ instruction: 0xfe172961 │ │ mrc2 11, 0, ip, cr8, cr10, {4} @ │ │ cdp2 12, 1, cr13, cr6, cr12, {1} │ │ cdp2 12, 1, cr7, cr9, cr10, {3} │ │ mrc2 6, 0, r6, cr9, cr13, {1} │ │ mrc2 15, 0, r1, cr6, cr8, {0} │ │ lsls r7, r4, #1 │ │ str r1, [r2, #92] @ 0x5c │ │ cdp2 15, 1, cr1, cr6, cr2, {0} │ │ lsls r7, r4, #1 │ │ - str r4, [r2, #16] │ │ - mrc2 5, 0, lr, cr8, cr11, {6} │ │ + str r1, [r0, #20] │ │ + cdp2 6, 1, cr14, cr8, cr8, {0} │ │ cdp2 1, 1, cr4, cr6, cr2, {7} │ │ - @ instruction: 0xfe19aaec │ │ - cdp2 6, 1, cr0, cr7, cr9, {2} │ │ - cdp2 4, 1, cr10, cr7, cr2, {5} │ │ + mrc2 11, 0, sl, cr9, cr9, {0} @ │ │ + mrc2 6, 0, r0, cr7, cr6, {3} │ │ + cdp2 4, 1, cr10, cr7, cr15, {6} │ │ @ instruction: 0xfe187ac8 │ │ - vselvs.f16 s12, s18, s1 │ │ + @ instruction: 0xfe19694d │ │ vselvs.f32 s14, s15, s5 │ │ - vfmsl.f16 q4, d9, d6[1] │ │ - mrc2 6, 0, r2, cr7, cr4, {6} │ │ + vcmla.f16 d8, d25, d11[0], #90 │ │ + cdp2 7, 1, cr2, cr7, cr1, {0} │ │ mrc2 9, 0, ip, cr8, cr8, {1} @ │ │ mrc2 4, 0, sp, cr6, cr4, {6} │ │ bmi.n 20adf22 │ │ bmi.n 20adf24 │ │ bmi.n 20adf26 │ │ bmi.n 20adf28 │ │ bmi.n 20adf2a │ │ @@ -102854,79 +102854,79 @@ │ │ ldr r0, [pc, #28] @ (20c1c44 ) │ │ add r0, pc │ │ bx lr │ │ ldr r0, [pc, #28] @ (20c1c4c ) │ │ add r0, pc │ │ bx lr │ │ nop │ │ - @ instruction: 0xeb58fe15 │ │ + @ instruction: 0xeb85fe15 │ │ lsls r4, r6, #26 │ │ - mrc2 10, 0, r2, cr5, cr10, {6} @ │ │ - mrc2 9, 0, lr, cr6, cr12, {0} @ │ │ + vselvs.f64 d2, d5, d7 │ │ + @ instruction: 0xfe16e949 │ │ cdp2 14, 1, cr6, cr6, cr11, {3} │ │ vselvs.f64 d8, d21, d0 │ │ - mrc2 9, 0, r0, cr5, cr3, {3} @ │ │ - mrc2 9, 0, r0, cr6, cr9, {6} @ │ │ - mrc2 12, 0, r6, cr6, cr5, {0} │ │ - vselvs.f64 d8, d22, d6 │ │ + vselvs.f16 s0, s11, s1 │ │ + vselvs.f32 s0, s12, s12 │ │ + cdp2 12, 1, cr6, cr6, cr2, {2} │ │ + mrc2 11, 0, r8, cr6, cr3, {5} @ │ │ @ instruction: 0xfe168be6 │ │ mrc2 0, 0, r2, cr5, cr1, {6} │ │ vcmla.f16 q4, q12, d5[1], #90 │ │ mrc2 5, 0, r0, cr7, cr8, {5} │ │ vcmla.f16 d13, d5, d6[0], #90 │ │ cdp2 13, 1, cr3, cr8, cr9, {7} │ │ mrc2 6, 0, sl, cr8, cr1, {1} │ │ cdp2 3, 1, cr0, cr7, cr7, {4} │ │ - mrc2 11, 0, sl, cr8, cr7, {5} @ │ │ - mrc2 3, 0, r4, cr6, cr9, {2} │ │ + @ instruction: 0xfe18abe4 │ │ + cdp2 3, 1, cr4, cr6, cr6, {4} │ │ cdp2 6, 1, cr2, cr7, cr12, {6} │ │ - mrc2 12, 0, sl, cr5, cr0, {7} │ │ - mrc2 4, 0, r4, cr6, cr13, {1} │ │ + mrc2 13, 0, sl, cr5, cr13, {0} │ │ + cdp2 4, 1, cr4, cr6, cr10, {3} │ │ mrc2 5, 0, r0, cr7, cr7, {7} │ │ cdp2 1, 1, cr2, cr5, cr15, {0} │ │ vcmla.f16 d8, d24, d15[0], #90 │ │ mrc2 13, 0, r3, cr7, cr2, {6} │ │ - mrc2 10, 0, lr, cr8, cr1, {1} @ │ │ + mrc2 10, 0, lr, cr8, cr14, {2} @ │ │ vcmla.f16 d13, d22, d4[1], #90 │ │ - mrc2 4, 0, r4, cr8, cr9, {0} │ │ + cdp2 4, 1, cr4, cr8, cr6, {2} │ │ mrc2 3, 0, lr, cr7, cr3, {4} │ │ - mrc2 12, 0, sl, cr7, cr6, {1} │ │ - mrc2 2, 0, r2, cr6, cr10, {6} │ │ + cdp2 12, 1, cr10, cr7, cr3, {3} │ │ + cdp2 3, 1, cr2, cr6, cr7, {0} │ │ vfmsl.f16 q4, d23, d2[2] │ │ vselvs.f16 s26, s14, s26 │ │ - cdp2 2, 1, cr2, cr8, cr0, {2} │ │ + cdp2 2, 1, cr2, cr8, cr13, {3} │ │ mrc2 12, 0, r4, cr7, cr12, {1} │ │ vselvs.f16 s26, s10, s21 │ │ cdp2 5, 1, cr10, cr8, cr12, {0} │ │ cdp2 4, 1, cr14, cr7, cr11, {6} │ │ cdp2 12, 1, cr8, cr7, cr8, {5} │ │ - mrc2 12, 0, sl, cr5, cr15, {3} │ │ - cdp2 7, 1, cr6, cr6, cr7, {0} │ │ - mrc2 12, 0, lr, cr7, cr7, {0} │ │ - mrc2 5, 0, r0, cr5, cr6, {0} │ │ - mrc2 3, 0, r4, cr7, cr11, {0} │ │ + cdp2 12, 1, cr10, cr5, cr12, {5} │ │ + mrc2 7, 0, r6, cr6, cr4, {1} │ │ + cdp2 12, 1, cr14, cr7, cr4, {2} │ │ + cdp2 5, 1, cr0, cr5, cr3, {2} │ │ + cdp2 3, 1, cr4, cr7, cr8, {2} │ │ vfmsl.f16 d12, s14, s10[0] │ │ cdp2 12, 1, cr4, cr7, cr7, {5} │ │ - mrc2 12, 0, sl, cr5, cr10, {2} │ │ + cdp2 12, 1, cr10, cr5, cr7, {4} │ │ cdp2 12, 1, cr8, cr6, cr12, {0} │ │ - cdp2 12, 1, cr6, cr5, cr4, {3} │ │ - vselvs.f32 s8, s13, s23 │ │ + mrc2 12, 0, r6, cr5, cr1, {4} │ │ + mrc2 10, 0, r4, cr6, cr8, {6} @ │ │ vcmla.f16 q4, q11, d10[0], #90 │ │ cdp2 13, 1, cr3, cr7, cr3, {3} │ │ - mrc2 9, 0, lr, cr8, cr7, {5} @ │ │ + @ instruction: 0xfe18e9e4 │ │ cdp2 12, 1, cr8, cr6, cr2, {6} │ │ cdp2 12, 1, cr9, cr5, cr13, {3} │ │ - mrc2 3, 0, r4, cr8, cr11, {7} │ │ - mrc2 7, 0, r6, cr7, cr3, {1} │ │ + cdp2 4, 1, cr4, cr8, cr8, {1} │ │ + cdp2 7, 1, cr6, cr7, cr0, {3} │ │ vcmla.f16 q6, , d12[0], #90 │ │ - vselvs.f64 d2, d7, d26 │ │ + mrc2 11, 0, r2, cr7, cr7, {2} @ │ │ cdp2 3, 1, cr0, cr6, cr13, {4} │ │ - cdp2 6, 1, cr12, cr8, cr1, {7} │ │ - cdp2 12, 1, cr10, cr6, cr4, {6} │ │ - vfmsl.f16 d10, s12, s13[0] │ │ + cdp2 7, 1, cr12, cr8, cr14, {0} │ │ + mrc2 12, 0, sl, cr6, cr1, {7} │ │ + vcmla.f16 q5, q3, d3[1], #90 │ │ mrc2 2, 0, pc, cr5, cr12, {1} │ │ cpsie ai │ │ │ │ 020c1d3c : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ @@ -105966,15 +105966,15 @@ │ │ bl 20a9690 │ │ cmp r0, #0 │ │ it eq │ │ moveq.w r0, #4294967295 @ 0xffffffff │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ b.n 20c39f4 │ │ - @ instruction: 0xfe14ca4c │ │ + mrc2 10, 0, ip, cr4, cr9, {3} @ │ │ cdp2 14, 1, cr6, cr6, cr7, {0} │ │ mrc2 5, 0, fp, cr5, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #8 │ │ mov ip, r0 │ │ ldr r0, [pc, #112] @ (20c3ba4 ) │ │ @@ -106271,15 +106271,15 @@ │ │ cmp r0, #0 │ │ it eq │ │ moveq.w r0, #4294967295 @ 0xffffffff │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ b.n 20c3760 │ │ - cdp2 7, 1, cr12, cr4, cr12, {4} │ │ + mrc2 7, 0, ip, cr4, cr9, {5} │ │ @ instruction: 0xfe166b47 │ │ Address 0x20c3e0e is out of bounds. │ │ │ │ │ │ 020c3e10 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -106909,15 +106909,15 @@ │ │ mov r0, r8 │ │ blx 2701950 │ │ mov r0, r4 │ │ b.n 20c42ac │ │ nop │ │ adds r4, #46 @ 0x2e │ │ lsls r7, r4, #1 │ │ - stmia r2!, {r2, r3, r4, r6, r7} │ │ + stmia r3!, {r0, r3} │ │ mrc2 4, 0, lr, cr6, cr0, {1} │ │ mrc2 3, 0, r3, cr8, cr12, {3} │ │ lsls r7, r4, #1 │ │ │ │ 020c43c8 : │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -110919,15 +110919,15 @@ │ │ nop │ │ nop │ │ ... │ │ @ instruction: 0xffffffff │ │ @ instruction: 0xffffffff │ │ blt.n 20c6f48 │ │ lsls r7, r4, #1 │ │ - str r7, [sp, #88] @ 0x58 │ │ + str r7, [sp, #268] @ 0x10c │ │ vfmsl.f16 , d22, d1[1] │ │ movs r1, r0 │ │ @ instruction: 0xb8df │ │ movs r1, r0 │ │ │ │ 020c6e80 : │ │ cmp r0, #0 │ │ @@ -110958,15 +110958,15 @@ │ │ pop {r4, r5, r7, pc} │ │ mov r0, r5 │ │ blx 27030a0 │ │ movs r0, #0 │ │ add sp, #16 │ │ pop {r4, r5, r7, pc} │ │ nop │ │ - str r6, [sp, #608] @ 0x260 │ │ + str r6, [sp, #788] @ 0x314 │ │ vfmsl.f16 , d6, d3[1] │ │ movs r1, r0 │ │ @ instruction: 0xb861 │ │ movs r1, r0 │ │ bmi.n 20c6e80 │ │ bmi.n 20c6e82 │ │ bmi.n 20c6e84 │ │ @@ -119085,15 +119085,15 @@ │ │ nop │ │ nop │ │ ... │ │ @ instruction: 0xffffffff │ │ @ instruction: 0xffffffff │ │ ldrb r4, [r5, #11] │ │ lsls r7, r4, #1 │ │ - adds r6, #132 @ 0x84 │ │ + adds r6, #177 @ 0xb1 │ │ mrc2 13, 0, fp, cr6, cr11, {0} │ │ movs r1, r0 │ │ pop {r0, r5, pc} │ │ movs r1, r0 │ │ │ │ 020ccf10 : │ │ cmp r1, #0 │ │ @@ -119127,15 +119127,15 @@ │ │ mov r0, r4 │ │ blx 27030a0 │ │ movs r0, #0 │ │ add sp, #8 │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ - adds r6, #0 │ │ + adds r6, #45 @ 0x2d │ │ mrc2 12, 0, fp, cr6, cr7, {4} │ │ movs r1, r0 │ │ pop {r0, r2, r3, r4, r7} │ │ movs r1, r0 │ │ bmi.n 20ccf18 │ │ bmi.n 20ccf1a │ │ │ │ @@ -121903,15 +121903,15 @@ │ │ lsls r1, r0, #22 │ │ movs r0, r0 │ │ str r6, [r0, #24] │ │ lsls r7, r4, #1 │ │ adds r4, #217 @ 0xd9 │ │ vraddhn.i d19, , │ │ vsri.64 , , #1 │ │ - vdup.8 , d12[7] │ │ + vcvt.f16.u16 , , #1 │ │ cdp2 0, 1, cr6, cr6, cr8, {5} │ │ lsls r7, r4, #1 │ │ str r4, [r3, #8] │ │ lsls r7, r4, #1 │ │ str r2, [r5, #8] │ │ lsls r7, r4, #1 │ │ subs r1, r2, #6 │ │ @@ -122085,24 +122085,24 @@ │ │ lsls r7, r4, #1 │ │ subs r1, r1, #2 │ │ movs r2, r0 │ │ subs r1, r0, #2 │ │ movs r2, r0 │ │ subs r1, r1, #2 │ │ movs r2, r0 │ │ - bvc.n 20cedb0 │ │ + bvc.n 20cec0a │ │ mrc2 14, 0, r5, cr4, cr4, {0} │ │ lsls r7, r4, #1 │ │ adds r1, r2, #4 │ │ movs r2, r0 │ │ adds r1, r1, #4 │ │ movs r2, r0 │ │ adds r1, r2, #4 │ │ movs r2, r0 │ │ - bl 1eff946 │ │ + bl 1f2c946 │ │ ldrb r2, [r3, r6] │ │ lsls r7, r4, #1 │ │ adds r3, r0, #2 │ │ movs r2, r0 │ │ adds r3, r7, #1 │ │ movs r2, r0 │ │ adds r3, r0, #2 │ │ @@ -123212,18 +123212,18 @@ │ │ strb r2, [r5, r3] │ │ lsls r7, r4, #1 │ │ strb r0, [r7, r3] │ │ lsls r7, r4, #1 │ │ sxtb r4, r6 │ │ cdp2 4, 1, cr5, cr4, cr14, {0} │ │ lsls r7, r4, #1 │ │ - ldmia r4, {r2, r4, r5, r6, r7} │ │ + ldmia r5, {r0, r5} │ │ cdp2 3, 1, cr5, cr4, cr14, {5} │ │ lsls r7, r4, #1 │ │ - @ instruction: 0xebeafe15 │ │ + ldc 14, cr15, [r7], {21} │ │ strh r6, [r2, r2] │ │ lsls r7, r4, #1 │ │ strh r2, [r5, r4] │ │ lsls r7, r4, #1 │ │ strh r4, [r3, r4] │ │ lsls r7, r4, #1 │ │ strh r2, [r6, #10] │ │ @@ -129675,15 +129675,15 @@ │ │ subs r5, #138 @ 0x8a │ │ lsls r6, r4, #1 │ │ lsrs r0, r6, #31 │ │ lsls r7, r4, #1 │ │ bkpt 0x0082 │ │ lsls r4, r4, #1 │ │ ldrb r0, [r3, #20] │ │ - vselvs.f32 s12, s14, s11 │ │ + mrc2 10, 0, r6, cr7, cr2, {2} @ │ │ @ instruction: 0xfe1539cc │ │ lsls r6, r4, #1 │ │ bmi.n 20d3c84 │ │ bmi.n 20d3c86 │ │ bmi.n 20d3c88 │ │ bmi.n 20d3c8a │ │ │ │ @@ -130356,16 +130356,16 @@ │ │ mov r1, fp │ │ b.n 20d428c │ │ mvn.w r0, #24 │ │ b.n 20d4342 │ │ nop │ │ adds r4, #230 @ 0xe6 │ │ lsls r6, r4, #1 │ │ - str r3, [r2, #72] @ 0x48 │ │ - mrc2 3, 0, r6, cr5, cr9, {3} │ │ + str r0, [r0, #76] @ 0x4c │ │ + cdp2 3, 1, cr6, cr5, cr6, {5} │ │ cdp2 2, 1, cr3, cr5, cr6, {7} │ │ lsls r6, r4, #1 │ │ │ │ 020d43ec : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -130532,15 +130532,15 @@ │ │ bne.n 20d4568 │ │ movs r4, #0 │ │ mov.w r3, #4294967295 @ 0xffffffff │ │ movs r1, #0 │ │ mov r0, r8 │ │ b.n 20d4562 │ │ nop │ │ - str r3, [r2, #16] │ │ + str r0, [r0, #20] │ │ Address 0x20d459a is out of bounds. │ │ │ │ │ │ 020d459c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -130796,15 +130796,15 @@ │ │ cbz r2, 20d480a │ │ ldmia.w sp!, {r4, r6, r7, lr} │ │ bx r2 │ │ mvn.w r2, #28 │ │ mov r0, r2 │ │ pop {r4, r6, r7, pc} │ │ nop │ │ - ldrsh r5, [r7, r1] │ │ + ldrsh r2, [r5, r2] │ │ Address 0x20d4816 is out of bounds. │ │ │ │ │ │ 020d4818 : │ │ cmp r0, #0 │ │ itt eq │ │ mvneq.w r0, #1 │ │ @@ -131502,15 +131502,15 @@ │ │ bne.w 20d4e22 │ │ b.n 20d4ea6 │ │ nop │ │ cmp r5, #164 @ 0xa4 │ │ lsls r6, r4, #1 │ │ add r5, sp, #832 @ 0x340 │ │ lsls r4, r4, #1 │ │ - bmi.n 20d4fb6 │ │ + bmi.n 20d5010 │ │ mrc2 6, 0, r5, cr5, cr2, {1} │ │ cdp2 7, 1, cr2, cr6, cr6, {7} │ │ lsls r6, r4, #1 │ │ │ │ 020d4f88 : │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -131918,15 +131918,15 @@ │ │ beq.w 20d5280 │ │ adds.w r2, r1, #51 @ 0x33 │ │ bne.n 20d534c │ │ b.n 20d5280 │ │ nop │ │ movs r4, #236 @ 0xec │ │ lsls r6, r4, #1 │ │ - @ instruction: 0xebfcfe15 │ │ + stc 14, cr15, [r9], #-84 @ 0xffffffac │ │ add r7, pc, #464 @ (adr r7, 20d5568 ) │ │ lsls r4, r4, #1 │ │ movs r3, #168 @ 0xa8 │ │ lsls r6, r4, #1 │ │ bmi.n 20d5348 │ │ bmi.n 20d534a │ │ │ │ @@ -133890,15 +133890,15 @@ │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ mvn.w r0, #28 │ │ b.n 20d6858 │ │ lsrs r2, r5, #31 │ │ lsls r6, r4, #1 │ │ - subs r6, #37 @ 0x25 │ │ + subs r6, #82 @ 0x52 │ │ mrc2 13, 0, r0, cr5, cr0, {6} │ │ lsls r6, r4, #1 │ │ │ │ 020d6884 : │ │ cbz r0, 20d68c8 │ │ ldrb.w r3, [r0, #560] @ 0x230 │ │ lsls r3, r3, #31 │ │ @@ -134264,15 +134264,15 @@ │ │ cbz r2, 20d6c8a │ │ ldmia.w sp!, {r4, r6, r7, lr} │ │ bx r2 │ │ mvn.w r2, #28 │ │ mov r0, r2 │ │ pop {r4, r6, r7, pc} │ │ nop │ │ - subs r1, #253 @ 0xfd │ │ + subs r2, #42 @ 0x2a │ │ Address 0x20d6c96 is out of bounds. │ │ │ │ │ │ 020d6c98 : │ │ cmp r0, #0 │ │ itt eq │ │ mvneq.w r0, #1 │ │ @@ -147692,21 +147692,21 @@ │ │ bne.n 20df76c │ │ mov r0, r4 │ │ bl 20f3564 │ │ add r5, r0 │ │ b.n 20df768 │ │ strh r6, [r1, #8] │ │ lsls r5, r4, #1 │ │ - bcc.n 20df8bc │ │ + bcc.n 20df916 │ │ mrc2 10, 0, r3, cr4, cr0, {5} @ │ │ mrc2 10, 0, r3, cr7, cr14, {4} @ │ │ mrc2 12, 0, r4, cr7, cr6, {4} │ │ - mrc2 13, 0, ip, cr3, cr0, {2} │ │ + mrc2 13, 0, ip, cr3, cr13, {3} │ │ vselvs.f32 s0, s6, s1 │ │ - cdp2 7, 1, cr4, cr6, cr8, {7} │ │ + vfmsl.f16 d4, s12, s10[0] │ │ mrc2 9, 0, r3, cr5, cr10, {5} @ │ │ mrc2 1, 0, r6, cr7, cr12, {4} │ │ vcmla.f16 , q11, d4[1], #90 │ │ cdp2 1, 1, cr6, cr7, cr2, {3} │ │ mrc2 14, 0, r7, cr6, cr0, {1} │ │ lsls r5, r4, #1 │ │ │ │ @@ -147925,15 +147925,15 @@ │ │ ldmia.w sp!, {r8, r9, fp} │ │ pop {r4, r5, r6, r7, pc} │ │ mov r0, r6 │ │ blx 27030a0 │ │ movs r0, #0 │ │ ldmia.w sp!, {r8, r9, fp} │ │ pop {r4, r5, r6, r7, pc} │ │ - lsrs r2, r4, #12 │ │ + lsrs r7, r1, #13 │ │ @ instruction: 0xfe150947 │ │ movs r0, r0 │ │ ldr r3, [pc, #300] @ (20dfbc8 ) │ │ movs r1, r0 │ │ cmp r1, #175 @ 0xaf │ │ movs r1, r0 │ │ cmp r1, #169 @ 0xa9 │ │ @@ -148087,15 +148087,15 @@ │ │ pop {r4, r5, r6, r7, pc} │ │ mov r0, r4 │ │ blx 27030a0 │ │ movs r0, #0 │ │ ldr.w r8, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ - lsrs r2, r3, #6 │ │ + lsrs r7, r0, #7 │ │ cdp2 7, 1, cr0, cr5, cr7, {6} │ │ movs r0, r0 │ │ ldr r1, [pc, #812] @ (20dff4c ) │ │ movs r1, r0 │ │ cmp r0, #47 @ 0x2f │ │ movs r1, r0 │ │ cmp r0, #41 @ 0x29 │ │ @@ -152391,15 +152391,15 @@ │ │ bx lr │ │ │ │ 020e26f4 : │ │ ldr r0, [pc, #4] @ (20e26fc ) │ │ add r0, pc │ │ bx lr │ │ nop │ │ - pop {r0, r1, r2, r3, r4, r5, r6} │ │ + pop {r2, r3, r5, r7} │ │ cdp2 6, 1, cr4, cr3, cr3, {0} │ │ mov r0, r1 │ │ movs r1, #1 │ │ b.w 26febb8 │ │ push {r7, lr} │ │ mov r7, sp │ │ subs r2, #1 │ │ @@ -152442,15 +152442,15 @@ │ │ mov r0, r8 │ │ blx 27030a0 │ │ movs r0, #0 │ │ add sp, #16 │ │ ldr.w r8, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ - ble.n 20e2750 │ │ + udf #25 │ │ cdp2 15, 1, cr15, cr4, cr15, {5} │ │ @ instruction: 0xffffffb3 │ │ vsli.64 , q8, #63 @ 0x3f │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub.w sp, sp, #4800 @ 0x12c0 │ │ sub sp, #4 │ │ @@ -155465,15 +155465,15 @@ │ │ mov r0, r8 │ │ blx 27030a0 │ │ movs r0, #0 │ │ add sp, #16 │ │ ldmia.w sp!, {r8, r9, fp} │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ - pop {r2, r3, r5, r6, r7, pc} │ │ + bkpt 0x0019 │ │ cdp2 15, 1, cr13, cr4, cr15, {5} │ │ @ instruction: 0xffffdfb5 │ │ Address 0x20e4792 is out of bounds. │ │ │ │ │ │ 020e4794 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -155523,15 +155523,15 @@ │ │ mov r0, r8 │ │ blx 27030a0 │ │ movs r0, #0 │ │ add sp, #16 │ │ ldmia.w sp!, {r8, r9, fp} │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ - pop {r2, r5, r6, pc} │ │ + pop {r0, r4, r7, pc} │ │ cdp2 15, 1, cr13, cr4, cr7, {1} │ │ @ instruction: 0xffffdf2d │ │ Address 0x20e481a is out of bounds. │ │ │ │ │ │ 020e481c : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -155581,15 +155581,15 @@ │ │ mov r0, r8 │ │ blx 27030a0 │ │ movs r0, #0 │ │ add sp, #16 │ │ ldmia.w sp!, {r8, r9, fp} │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ - pop {r2, r3, r4, r6, r7} │ │ + pop {r0, r3, pc} │ │ mrc2 14, 0, sp, cr4, cr15, {4} │ │ @ instruction: 0xffffdea5 │ │ Address 0x20e48a2 is out of bounds. │ │ │ │ │ │ 020e48a4 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -155961,15 +155961,15 @@ │ │ bmi.n 20e4bd2 │ │ │ │ 020e4c28 : │ │ ldr r0, [pc, #4] @ (20e4c30 ) │ │ add r0, pc │ │ bx lr │ │ nop │ │ - asrs r7, r0, #12 │ │ + asrs r4, r6, #12 │ │ Address 0x20e4c32 is out of bounds. │ │ │ │ │ │ 020e4c34 : │ │ movw r1, #6152 @ 0x1808 │ │ movs r2, #0 │ │ strb r2, [r0, r1] │ │ @@ -162667,15 +162667,15 @@ │ │ cmpne r2, #0 │ │ ldrne r1, [r5, #0] │ │ blxne r2 │ │ b.n 20e9996 │ │ nop │ │ ble.n 20e9a08 │ │ lsls r4, r4, #1 │ │ - ldr r2, [r6, #60] @ 0x3c │ │ + ldr r7, [r3, #64] @ 0x40 │ │ cdp2 2, 1, cr15, cr4, cr15, {3} │ │ vrshr.u32 , , #1 │ │ vsra.u64 d16, d29, #1 │ │ movs r0, r0 │ │ str r5, [r2, r7] │ │ movs r1, r0 │ │ lsls r5, r2, #7 │ │ @@ -162770,15 +162770,15 @@ │ │ cmpne r2, #0 │ │ ldrne r1, [r5, #0] │ │ blxne r2 │ │ b.n 20e9a9a │ │ nop │ │ bgt.n 20e9b04 │ │ lsls r4, r4, #1 │ │ - ldr r6, [r5, #44] @ 0x2c │ │ + ldr r3, [r3, #48] @ 0x30 │ │ cdp2 1, 1, cr15, cr4, cr11, {3} │ │ vsra.u32 , , #1 │ │ vshr.u64 d16, d25, #1 │ │ movs r0, r0 │ │ str r1, [r2, r3] │ │ movs r1, r0 │ │ lsls r1, r2, #3 │ │ @@ -163566,22 +163566,22 @@ │ │ blx 26ffb60 │ │ nop │ │ @ instruction: 0xffffffff │ │ @ instruction: 0xffffffff │ │ ... │ │ bhi.n 20ea370 │ │ lsls r4, r4, #1 │ │ - subs r3, r6, #7 │ │ + movs r0, #32 │ │ mrc2 3, 0, sp, cr3, cr4, {2} │ │ lsls r4, r4, #1 │ │ - subs r1, r4, #7 │ │ - cdp2 15, 1, cr1, cr3, cr13, {5} │ │ + movs r0, #14 │ │ + mrc2 15, 0, r1, cr3, cr10, {6} │ │ cdp2 3, 1, cr13, cr3, cr14, {0} │ │ lsls r4, r4, #1 │ │ - subs r3, r3, #6 │ │ + subs r0, r1, #7 │ │ cdp2 4, 1, cr13, cr3, cr2, {1} │ │ lsls r4, r4, #1 │ │ │ │ 020ea3e0 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -164256,15 +164256,15 @@ │ │ b.n 20ea8b4 │ │ ldmia r6, {r1, r2, r5, r6} │ │ lsls r4, r4, #1 │ │ ldmia r5, {r3, r4, r5, r6, r7} │ │ lsls r4, r4, #1 │ │ subs r2, #247 @ 0xf7 │ │ cdp2 2, 1, cr13, cr5, cr9, {6} │ │ - mrc2 10, 0, r3, cr5, cr10, {1} @ │ │ + @ instruction: 0xfe153a67 │ │ cdp2 12, 1, cr12, cr4, cr14, {0} │ │ lsls r4, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ mov r4, r0 │ │ ldr r1, [r0, #16] │ │ @@ -165691,15 +165691,15 @@ │ │ ldr.w r0, [r9, #104] @ 0x68 │ │ str r0, [r6, #64] @ 0x40 │ │ movs r0, #2 │ │ b.n 20eb9ca │ │ nop │ │ pop {r1, r6, r7, pc} │ │ lsls r4, r4, #1 │ │ - cmp r1, #76 @ 0x4c │ │ + cmp r1, #121 @ 0x79 │ │ cdp2 15, 1, cr6, cr4, cr8, {1} │ │ @ instruction: 0xfe16bbee │ │ lsls r4, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #24 │ │ @@ -165753,15 +165753,15 @@ │ │ addeq sp, #24 │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ cbnz r2, 20ebbb2 │ │ lsls r4, r4, #1 │ │ - movs r7, #78 @ 0x4e │ │ + movs r7, #123 @ 0x7b │ │ @ instruction: 0xfe14bae8 │ │ lsls r4, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ mov r5, r0 │ │ ldr r0, [r1, #20] │ │ @@ -167183,15 +167183,15 @@ │ │ ldmiaeq.w sp!, {r8, r9, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ add r4, sp, #472 @ 0x1d8 │ │ lsls r4, r4, #1 │ │ ldmia r4, {r0, r2, r3, r4, r5} │ │ - cdp2 12, 1, cr7, cr5, cr15, {5} │ │ + mrc2 12, 0, r7, cr5, cr12, {6} │ │ @ instruction: 0xfe13abe0 │ │ lsls r4, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ ldr r2, [r0, #20] │ │ ldrd r1, r4, [r0] │ │ cbz r2, 20eca88 │ │ @@ -167368,15 +167368,15 @@ │ │ addweq sp, sp, #1556 @ 0x614 │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ add r2, sp, #920 @ 0x398 │ │ lsls r4, r4, #1 │ │ cmp r0, #157 @ 0x9d │ │ - mrc2 2, 0, r9, cr6, cr1, {7} │ │ + mrc2 3, 0, r9, cr6, cr14, {0} │ │ mrc2 9, 0, sl, cr4, cr10, {7} @ │ │ lsls r4, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ sub sp, #16 │ │ mov r8, r0 │ │ @@ -167489,15 +167489,15 @@ │ │ mov r0, r1 │ │ ldr.w r2, [r8, #244] @ 0xf4 │ │ blx r2 │ │ movs r0, #0 │ │ b.n 20eccf6 │ │ add r1, sp, #760 @ 0x2f8 │ │ lsls r4, r4, #1 │ │ - str r2, [sp, #236] @ 0xec │ │ + str r2, [sp, #416] @ 0x1a0 │ │ mrc2 7, 0, r2, cr4, cr5, {3} │ │ mrc2 9, 0, sl, cr6, cr2, {1} @ │ │ lsls r4, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #24 │ │ mov r4, r0 │ │ @@ -167692,15 +167692,15 @@ │ │ add.w r2, r6, r2, lsl #4 │ │ strd r1, r0, [r2, #8] │ │ ldmia.w sp!, {r8, r9, fp} │ │ pop {r4, r5, r6, r7, pc} │ │ mvn.w r0, #2 │ │ ldmia.w sp!, {r8, r9, fp} │ │ pop {r4, r5, r6, r7, pc} │ │ - ldrh r1, [r3, #62] @ 0x3e │ │ + str r0, [sp, #24] │ │ cdp2 5, 1, cr2, cr4, cr7, {0} │ │ mrc2 5, 0, fp, cr6, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ mov r8, r2 │ │ mov r5, r0 │ │ cmp r0, #0 │ │ @@ -167736,16 +167736,16 @@ │ │ mov r3, r4 │ │ add r2, pc │ │ blx 2702930 │ │ mvn.w r0, #202 @ 0xca │ │ ldmia.w sp!, {r8, r9, fp} │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ - strb r5, [r3, #25] │ │ - mrc2 2, 0, pc, cr3, cr10, {3} │ │ + strb r2, [r1, #26] │ │ + cdp2 2, 1, cr15, cr3, cr7, {5} │ │ vcmla.f16 , q1, d4[1], #90 │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #8 │ │ ldr r6, [pc, #132] @ (20ed0b4 ) │ │ mov r1, r0 │ │ @@ -167929,15 +167929,15 @@ │ │ blx 26ffb50 │ │ nop │ │ lsrs r4, r2, #6 │ │ lsls r7, r4, #1 │ │ add r4, pc, #920 @ (adr r4, 20ed584 ) │ │ lsls r4, r4, #1 │ │ movs r2, #147 @ 0x93 │ │ - cdp2 13, 1, cr8, cr6, cr3, {1} │ │ + mrc2 13, 0, r8, cr6, cr0, {2} │ │ cdp2 4, 1, cr10, cr4, cr2, {3} │ │ lsls r4, r4, #1 │ │ ldr r0, [pc, #308] @ (20ed330 ) │ │ add r0, pc │ │ ldr r0, [r0, #0] │ │ cmp r0, #0 │ │ itt eq │ │ @@ -168046,15 +168046,15 @@ │ │ b.n 20ed2fc │ │ movs r0, #0 │ │ ldmia.w sp!, {r8, r9, fp} │ │ pop {r4, r5, r6, r7, pc} │ │ lsrs r6, r3, #3 │ │ lsls r7, r4, #1 │ │ movs r1, #217 @ 0xd9 │ │ - cdp2 12, 1, cr8, cr6, cr3, {4} │ │ + mrc2 12, 0, r8, cr6, cr0, {5} │ │ cdp2 6, 1, cr5, cr4, cr14, {2} │ │ mrc2 5, 0, fp, cr6, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #148 @ 0x94 │ │ ldr r4, [pc, #708] @ (20ed610 ) │ │ ldr.w r6, [pc, #1824] @ 20eda70 │ │ @@ -168338,24 +168338,24 @@ │ │ add r2, pc │ │ b.n 20ed51c │ │ nop │ │ lsls r0, r1, #30 │ │ lsls r7, r4, #1 │ │ lsls r2, r1, #27 │ │ lsls r7, r4, #1 │ │ - bl 2489242 │ │ + bl 24b6242 │ │ ldmia r7!, {r0, r2} │ │ cdp2 15, 1, cr1, cr4, cr14, {2} │ │ vselvs.f32 s16, s12, s28 │ │ mrc2 15, 0, r1, cr6, cr4, {0} │ │ mrc2 2, 0, lr, cr6, cr14, {4} │ │ mrc2 14, 0, r1, cr5, cr14, {6} │ │ vselvs.f64 d0, d22, d19 │ │ movs r0, r0 │ │ - ldr r2, [pc, #228] @ (20ed720 ) │ │ + ldr r2, [pc, #408] @ (20ed7d4 ) │ │ cdp2 2, 1, cr14, cr4, cr2, {3} │ │ vcmla.f16 d9, d5, d4[0], #90 │ │ mov r1, sl │ │ ldrd r2, r3, [sp, #20] │ │ str r0, [sp, #0] │ │ add r0, sp, #88 @ 0x58 │ │ bl 20ee214 │ │ @@ -168801,33 +168801,33 @@ │ │ movs r0, r0 │ │ movs r4, #0 │ │ lsls r4, r6, #3 │ │ movs r0, r2 │ │ movs r0, r0 │ │ add r2, pc, #872 @ (adr r2, 20edddc ) │ │ lsls r4, r4, #1 │ │ - mov pc, pc │ │ + bxns r5 │ │ cdp2 3, 1, cr6, cr4, cr1, {1} │ │ cdp2 1, 1, cr14, cr5, cr3, {2} │ │ mrc2 1, 0, sp, cr5, cr11, {1} │ │ - mrc2 12, 0, r2, cr2, cr5, {4} │ │ - cdp2 13, 1, cr2, cr4, cr3, {2} │ │ - mrc2 15, 0, lr, cr4, cr6, {4} │ │ - cdp2 0, 1, cr15, cr3, cr12, {0} │ │ - cdp2 12, 1, cr2, cr3, cr15, {4} │ │ + cdp2 12, 1, cr2, cr2, cr2, {6} │ │ + mrc2 13, 0, r2, cr4, cr0, {3} │ │ + cdp2 15, 1, cr14, cr4, cr3, {6} │ │ + mrc2 0, 0, pc, cr3, cr9, {1} │ │ + mrc2 12, 0, r2, cr3, cr12, {5} │ │ vfmsl.f16 q2, d20, d3[1] │ │ vselvs.f16 s8, s4, s3 │ │ mrc2 15, 0, sp, cr2, cr1, {2} │ │ cdp2 15, 1, cr13, cr5, cr5, {5} │ │ cdp2 14, 1, cr13, cr5, cr2, {5} │ │ cdp2 14, 1, cr13, cr5, cr12, {7} │ │ mrc2 9, 0, r0, cr5, cr15, {7} @ │ │ movs r0, r0 │ │ - cmp sp, pc │ │ - mrc2 6, 0, r4, cr4, cr9, {3} │ │ + mov r2, r5 │ │ + cdp2 6, 1, cr4, cr4, cr6, {5} │ │ mrc2 14, 0, r4, cr4, cr14, {3} │ │ cdp2 14, 1, cr9, cr6, cr6, {4} │ │ lsls r4, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #128] @ (20edb4c ) │ │ @@ -169144,20 +169144,20 @@ │ │ mov r0, r8 │ │ blx 27028f0 │ │ mov r0, r9 │ │ cmp.w r9, #16 │ │ bls.w 20edc3c │ │ b.n 20edd1a │ │ vhadd.u q8, q6, q11 │ │ - ldr r2, [pc, #368] @ (20edf5c ) │ │ + ldr r2, [pc, #548] @ (20ee010 ) │ │ cdp2 12, 1, cr4, cr3, cr6, {5} │ │ @ instruction: 0xfe16cb67 │ │ mrc2 7, 0, r1, cr2, cr15, {7} │ │ mrc2 12, 0, r4, cr6, cr12, {1} │ │ - mrc2 2, 0, r4, cr6, cr0, {6} │ │ + mrc2 2, 0, r4, cr6, cr13, {7} │ │ mrc2 3, 0, r8, cr4, cr14, {1} │ │ mrc2 5, 0, fp, cr6, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ sub sp, #32 │ │ mov r8, r0 │ │ ldr r0, [pc, #536] @ (20ee02c ) │ │ @@ -169377,15 +169377,15 @@ │ │ ldmiaeq.w sp!, {r8, r9, sl} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ stc2l 0, cr0, [r4], {102} @ 0x66 │ │ ldr r0, [sp, #88] @ 0x58 │ │ lsls r4, r4, #1 │ │ ldrb r5, [r3, #8] │ │ - cdp2 7, 1, cr6, cr5, cr6, {4} │ │ + mrc2 7, 0, r6, cr5, cr3, {5} │ │ mrc2 15, 0, r7, cr3, cr4, {7} │ │ mrc2 6, 0, r9, cr6, cr6, {0} │ │ lsls r4, r4, #1 │ │ cmp r0, #16 │ │ itt hi │ │ movhi.w r0, #4294967295 @ 0xffffffff │ │ bxhi lr │ │ @@ -169829,15 +169829,15 @@ │ │ addeq.w sp, sp, #1552 @ 0x610 │ │ ldmiaeq.w sp!, {r8, r9, sl} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ str r1, [sp, #912] @ 0x390 │ │ lsls r4, r4, #1 │ │ - stmia r1!, {r2, r5, r6, r7} │ │ + stmia r2!, {r0, r4} │ │ cdp2 3, 1, cr8, cr3, cr6, {4} │ │ mrc2 1, 0, r9, cr2, cr4, {3} │ │ lsls r4, r4, #1 │ │ cmp r2, #0 │ │ itt ne │ │ ldrne r0, [r2, #0] │ │ cmpne r0, #0 │ │ @@ -169863,15 +169863,15 @@ │ │ strd r0, r0, [r4, #512] @ 0x200 │ │ movs r0, #0 │ │ pop {r4, r6, r7, pc} │ │ mvn.w r0, #203 @ 0xcb │ │ bx lr │ │ nop │ │ strh r0, [r5, #24] │ │ - mrc2 1, 0, ip, cr2, cr0, {2} │ │ + mrc2 1, 0, ip, cr2, cr13, {3} │ │ mrc2 5, 0, fp, cr3, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #20 │ │ vmov.i32 q8, #0 @ 0x00000000 │ │ addw sl, r0, #2904 @ 0xb58 │ │ mov r9, r0 │ │ @@ -173667,15 +173667,15 @@ │ │ bne.n 20f0c90 │ │ movs r4, #0 │ │ mov.w r3, #4294967295 @ 0xffffffff │ │ movs r1, #0 │ │ mov r0, r8 │ │ b.n 20f0c8a │ │ nop │ │ - ldr r1, [sp, #940] @ 0x3ac │ │ + ldr r2, [sp, #96] @ 0x60 │ │ cdp2 5, 1, cr11, cr3, cr0, {4} │ │ mov r7, sp │ │ ldrd ip, lr, [r7, #8] │ │ strd ip, lr, [r7, #8] │ │ ldmia.w sp!, {r7, lr} │ │ b.w 26feb1c │ │ mov ip, r0 │ │ @@ -173772,15 +173772,15 @@ │ │ cbz r2, 20f0dc6 │ │ ldmia.w sp!, {r4, r6, r7, lr} │ │ bx r2 │ │ mvn.w r2, #28 │ │ mov r0, r2 │ │ pop {r4, r6, r7, pc} │ │ nop │ │ - ldr r0, [sp, #772] @ 0x304 │ │ + ldr r0, [sp, #952] @ 0x3b8 │ │ cdp2 5, 1, cr11, cr3, cr0, {4} │ │ mov r7, sp │ │ add.w r2, r0, #96 @ 0x60 │ │ dmb ish │ │ ldrex r3, [r2] │ │ strex r3, r1, [r2] │ │ cmp r3, #0 │ │ @@ -173817,15 +173817,15 @@ │ │ moveq r0, #0 │ │ ldr r2, [pc, #12] @ (20f0e44 ) │ │ add r2, pc │ │ blx 2702930 │ │ movs r0, #0 │ │ pop {r7, pc} │ │ nop │ │ - ldr r0, [sp, #180] @ 0xb4 │ │ + ldr r0, [sp, #360] @ 0x168 │ │ mrc2 5, 0, fp, cr3, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ mov r4, r0 │ │ blx 26ffea0 │ │ asrs r1, r0, #31 │ │ movw r8, #32768 @ 0x8000 │ │ @@ -178030,18 +178030,18 @@ │ │ b.n 20f3f5a │ │ addw r6, r6, #610 @ 0x262 │ │ cmp r0, #0 │ │ mov r1, r4 │ │ it ne │ │ addne r6, r0 │ │ b.n 20f3f52 │ │ - ldmia r6, {r0, r1, r4, r5, r6} │ │ - mrc2 0, 0, r9, cr3, cr7, {7} │ │ + ldmia r6!, {r5, r7} │ │ + cdp2 1, 1, cr9, cr3, cr4, {1} │ │ cdp2 0, 1, cr2, cr3, cr7, {7} │ │ - mrc2 12, 0, lr, cr5, cr6, {5} │ │ + cdp2 12, 1, cr14, cr5, cr3, {7} │ │ cdp2 3, 1, cr0, cr2, cr5, {1} │ │ cdp2 1, 1, cr15, cr5, cr6, {0} │ │ lsls r0, r5, #8 │ │ movs r0, #4 │ │ adds r6, r0, r2 │ │ cmp r1, #0 │ │ beq.n 20f3bf2 │ │ @@ -178796,15 +178796,15 @@ │ │ bgt.n 20f42a0 │ │ cmp r2, #1 │ │ beq.n 20f4348 │ │ cmp r2, #64 @ 0x40 │ │ beq.n 20f42ac │ │ b.n 20f427a │ │ nop │ │ - stmia r7!, {r0, r1, r2, r4, r6, r7} │ │ + ldmia r0!, {r2} │ │ cdp2 3, 1, cr6, cr2, cr4, {5} │ │ mrc2 5, 0, pc, cr4, cr2, {5} │ │ ldrb r0, [r0, #30] │ │ beq.w 20f43c8 │ │ cmp r2, #128 @ 0x80 │ │ bne.n 20f427a │ │ ldr.w r0, [sl, #12] │ │ @@ -178899,22 +178899,22 @@ │ │ blx r6 │ │ b.n 20f4534 │ │ lsls r4, r6 │ │ lsls r4, r4, #1 │ │ lsls r6, r3 │ │ lsls r4, r4, #1 │ │ svc 80 @ 0x50 │ │ - vfmsl.f16 q4, d4, d0[2] │ │ + vfmsl.f16 d8, s9, s10[1] │ │ vfmsl.f16 d1, s7, s13[1] │ │ mrc2 10, 0, r4, cr5, cr15, {5} @ │ │ mrc2 12, 0, pc, cr2, cr4, {0} │ │ cdp2 1, 1, cr0, cr4, cr15, {4} │ │ - cdp2 1, 1, cr10, cr2, cr14, {7} │ │ - cdp2 5, 1, cr6, cr3, cr0, {6} │ │ - mrc2 4, 0, ip, cr3, cr4, {4} │ │ + mrc2 2, 0, sl, cr2, cr11, {0} │ │ + cdp2 5, 1, cr6, cr3, cr13, {7} │ │ + cdp2 4, 1, cr12, cr3, cr1, {6} │ │ vfmsl.f16 d9, s6, s4[0] │ │ cmp r0, #0 │ │ beq.w 20f4504 │ │ strd r9, r4, [sp, #44] @ 0x2c │ │ movs r2, #4 │ │ ldr.w r0, [r8] │ │ ldr.w r3, [fp] │ │ @@ -179061,18 +179061,18 @@ │ │ blx r3 │ │ b.n 20f4566 │ │ movs r0, #1 │ │ ldr r4, [sp, #48] @ 0x30 │ │ add r6, r0 │ │ b.n 20f427a │ │ nop │ │ - stmia r5!, {r0, r3, r5, r6} │ │ - mrc2 14, 0, sp, cr2, cr9, {4} │ │ - cdp2 4, 1, cr0, cr3, cr12, {6} │ │ - cdp2 4, 1, cr0, cr3, cr11, {6} │ │ + stmia r5!, {r1, r2, r4, r7} │ │ + cdp2 14, 1, cr13, cr2, cr6, {6} │ │ + mrc2 4, 0, r0, cr3, cr9, {7} │ │ + mrc2 4, 0, r0, cr3, cr8, {7} │ │ cdp2 14, 1, cr13, cr3, cr11, {3} │ │ cdp2 5, 1, cr11, cr1, cr0, {4} │ │ mov r7, sp │ │ subs r2, #1 │ │ clz r2, r2 │ │ lsrs r2, r2, #5 │ │ blx 27030f0 │ │ @@ -193458,15 +193458,15 @@ │ │ bl 20a6ae4 ::loadExtras(celestia::util::array_view)@@Base+0x320> │ │ mov r0, sl │ │ bl 20ff116 │ │ blx 26ffb60 │ │ nop │ │ ldrh r6, [r7, #20] │ │ lsls r3, r4, #1 │ │ - adds r4, #196 @ 0xc4 │ │ + adds r4, #241 @ 0xf1 │ │ mrc2 10, 0, r8, cr3, cr8, {0} @ │ │ lsls r3, r4, #1 │ │ ldrh r4, [r7, #2] │ │ lsls r3, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -193726,19 +193726,19 @@ │ │ add r0, sp, #540 @ 0x21c │ │ blx 26ffe80 │ │ blx 26ffb60 │ │ ldrh r0, [r2, #0] │ │ lsls r3, r4, #1 │ │ strh r2, [r3, #54] @ 0x36 │ │ lsls r3, r4, #1 │ │ - bl 2350ce8 │ │ + bl 237dce8 │ │ ldrb r4, [r3, #0] │ │ - mrc2 6, 0, fp, cr1, cr13, {3} │ │ - cdp2 2, 1, cr15, cr2, cr9, {2} │ │ - mrc2 6, 0, fp, cr2, cr13, {2} │ │ + cdp2 6, 1, cr11, cr1, cr10, {5} │ │ + mrc2 2, 0, pc, cr2, cr6, {3} │ │ + cdp2 6, 1, cr11, cr2, cr10, {4} │ │ vfmsl.f16 d8, s4, s12[0] │ │ lsls r3, r4, #1 │ │ strh r0, [r5, #60] @ 0x3c │ │ lsls r3, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ ldr r4, [r0, #4] │ │ @@ -194468,15 +194468,15 @@ │ │ adds r3, #255 @ 0xff │ │ adds r3, #51 @ 0x33 │ │ rors r3, r1 │ │ ldmia r4!, {r0, r2, r3, r6, r7} │ │ asrs r4, r2 │ │ ldrb r0, [r1, #29] │ │ lsls r3, r4, #1 │ │ - ldrh r5, [r7, #20] │ │ + ldrh r2, [r5, #22] │ │ mrc2 14, 0, r7, cr3, cr8, {0} │ │ lsls r3, r4, #1 │ │ │ │ 020ff854 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -195041,19 +195041,19 @@ │ │ ldrb r4, [r4, #6] │ │ lsls r3, r4, #1 │ │ ldrb r2, [r4, #6] │ │ lsls r3, r4, #1 │ │ ldrb r6, [r6, #4] │ │ lsls r3, r4, #1 │ │ ldr r0, [sp, #772] @ 0x304 │ │ - cdp2 4, 1, cr14, cr4, cr9, {6} │ │ + mrc2 4, 0, lr, cr4, cr6, {7} │ │ cdp2 0, 1, cr2, cr2, cr3, {1} │ │ mrc2 10, 0, sp, cr4, cr10, {2} @ │ │ - cdp2 14, 1, cr3, cr4, cr8, {4} │ │ - mrc2 2, 0, r2, cr3, cr8, {6} │ │ + mrc2 14, 0, r3, cr4, cr5, {5} │ │ + cdp2 3, 1, cr2, cr3, cr5, {0} │ │ @ instruction: 0xfe1349eb │ │ add r1, pc │ │ movs r2, #9 │ │ bl 2094bc4 ::InfoType* std::__ndk1::vector::InfoType, std::__ndk1::allocator::InfoType> >::__emplace_back_slow_path(WarpMeshInfo const&)@@Base+0x24c> │ │ ldr r0, [r5, #0] │ │ cbz r0, 20ffed8 │ │ movs r0, #47 @ 0x2f │ │ @@ -195393,18 +195393,18 @@ │ │ mrc2 1, 0, ip, cr3, cr10, {6} │ │ mrc2 9, 0, sl, cr3, cr10, {0} @ │ │ vselvs.f16 s20, s2, s28 │ │ mrc2 9, 0, r5, cr1, cr13, {0} @ │ │ mrc2 13, 0, r7, cr4, cr9, {6} │ │ mrc2 10, 0, r8, cr4, cr8, {6} @ │ │ @ instruction: 0xfe118ac0 │ │ - cdp2 4, 1, cr0, cr1, cr1, {7} │ │ - mrc2 4, 0, r0, cr3, cr1, {5} │ │ - mrc2 6, 0, r0, cr3, cr4, {5} │ │ - mrc2 7, 0, r8, cr2, cr8, {3} │ │ + cdp2 5, 1, cr0, cr1, cr14, {0} │ │ + mrc2 4, 0, r0, cr3, cr14, {6} │ │ + cdp2 6, 1, cr0, cr3, cr1, {7} │ │ + cdp2 7, 1, cr8, cr2, cr5, {5} │ │ mrc2 4, 0, r7, cr2, cr6, {5} │ │ lsls r3, r4, #1 │ │ │ │ 0210025c , std::__ndk1::allocator >, std::__ndk1::basic_string, std::__ndk1::allocator >, std::__ndk1::basic_string, std::__ndk1::allocator > >(std::__ndk1::basic_ostream >&, fmt::v11::basic_format_string, std::__ndk1::allocator > >::type, fmt::v11::type_identity, std::__ndk1::allocator > >::type, fmt::v11::type_identity, std::__ndk1::allocator > >::type>, std::__ndk1::basic_string, std::__ndk1::allocator >&&, std::__ndk1::basic_string, std::__ndk1::allocator >&&, std::__ndk1::basic_string, std::__ndk1::allocator >&&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -196585,15 +196585,15 @@ │ │ lsls r3, r4, #1 │ │ ldr r0, [r2, #36] @ 0x24 │ │ lsls r3, r4, #1 │ │ ldr r4, [r4, #20] │ │ lsls r3, r4, #1 │ │ ldr r2, [r6, #28] │ │ lsls r3, r4, #1 │ │ - cbnz r5, 2100ec6 >)@@Base+0x5e> │ │ + cbnz r2, 2100ed2 >)@@Base+0x6a> │ │ vfmsl.f16 d6, s4, s12[0] │ │ lsls r3, r4, #1 │ │ │ │ 02100e68 >)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -196815,15 +196815,15 @@ │ │ beq.n 21010a0 >)@@Base+0x238> │ │ ldr r0, [sp, #20] │ │ ldr r0, [r0, #8] │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ str r2, [r6, #120] @ 0x78 │ │ lsls r3, r4, #1 │ │ - bcs.n 2101152 (std::__ndk1::basic_ostream >&, fmt::v11::basic_format_string::type>, unsigned char&)@@Base+0x9e> │ │ + bcs.n 2100fac >)@@Base+0x144> │ │ cdp2 2, 1, cr3, cr2, cr2, {6} │ │ cdp2 5, 1, cr6, cr1, cr0, {6} │ │ lsls r3, r4, #1 │ │ │ │ 021010b4 (std::__ndk1::basic_ostream >&, fmt::v11::basic_format_string::type>, unsigned char&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -197243,21 +197243,21 @@ │ │ mov r2, r5 │ │ blx 26ffe60 │ │ mov.w r8, #0 │ │ b.n 2101cf8 >)@@Base+0xb88> │ │ nop │ │ strh r3, [r3, #40] @ 0x28 │ │ mrc2 14, 0, lr, cr4, cr3, {1} │ │ - mrc2 4, 0, r9, cr3, cr8, {2} │ │ - mrc2 15, 0, ip, cr2, cr13, {6} │ │ + cdp2 4, 1, cr9, cr3, cr5, {4} │ │ + cdp2 0, 1, cr13, cr2, cr10, {0} │ │ vfmsl.f16 d14, s5, s5[1] │ │ lsls r1, r4, #1 │ │ lsrs r7, r6, #11 │ │ - mrc2 13, 0, r0, cr4, cr4, {5} │ │ - @ instruction: 0xfe13294e │ │ + cdp2 13, 1, cr0, cr4, cr1, {7} │ │ + mrc2 9, 0, r2, cr3, cr11, {3} @ │ │ cdp2 5, 1, cr4, cr3, cr4, {6} │ │ cdp2 5, 1, cr10, cr4, cr13, {5} │ │ mrc2 12, 0, sl, cr4, cr10, {6} │ │ cdp2 4, 1, cr10, cr3, cr3, {5} │ │ vselvs.f64 d14, d4, d4 │ │ lsrs r0, r0, #4 │ │ sub.w r6, fp, r0 │ │ @@ -198191,23 +198191,23 @@ │ │ ... │ │ movs r0, r0 │ │ subs r7, #128 @ 0x80 │ │ str r4, [r3, #72] @ 0x48 │ │ lsls r3, r4, #1 │ │ str r0, [r4, #56] @ 0x38 │ │ lsls r3, r4, #1 │ │ - stmia r4!, {r0, r5, r7} │ │ - mrc2 4, 0, ip, cr2, cr9, {4} │ │ - mrc2 4, 0, ip, cr2, cr1, {4} │ │ + stmia r4!, {r1, r2, r3, r6, r7} │ │ + cdp2 4, 1, cr12, cr2, cr6, {6} │ │ + mrc2 4, 0, ip, cr2, cr14, {5} │ │ vselvs.f64 d7, d2, d23 │ │ - mrc2 4, 0, ip, cr4, cr7, {5} │ │ + cdp2 4, 1, cr12, cr4, cr4, {7} │ │ @ instruction: 0xfe127ac3 │ │ mrc2 12, 0, r3, cr4, cr15, {5} │ │ - mrc2 9, 0, r0, cr4, cr9, {7} @ │ │ - cdp2 4, 1, cr12, cr2, cr15, {5} │ │ + vselvs.f32 s0, s8, s13 │ │ + mrc2 4, 0, ip, cr2, cr12, {6} │ │ Address 0x2101efa is out of bounds. │ │ │ │ │ │ 02101efc (char const*) const@@Base>: │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #32 │ │ @@ -199029,26 +199029,26 @@ │ │ cmp r4, #2 │ │ it hi │ │ movhi r9, r6 │ │ ldr r0, [pc, #52] @ (2102710 >, std::__ndk1::basic_string, std::__ndk1::allocator >, std::__ndk1::less > >, std::__ndk1::allocator > const, std::__ndk1::basic_string, std::__ndk1::allocator > > > > const&, std::__ndk1::basic_string_view >)@@Base+0x440>) │ │ add r0, pc │ │ str r0, [sp, #24] │ │ b.n 2102734 >, std::__ndk1::basic_string, std::__ndk1::allocator >, std::__ndk1::less > >, std::__ndk1::allocator > const, std::__ndk1::basic_string, std::__ndk1::allocator > > > > const&, std::__ndk1::basic_string_view >)@@Base+0x464> │ │ - stc2 14, cr15, [r0, #72]! @ 0x48 │ │ - stc2l 14, cr15, [r2, #-72] @ 0xffffffb8 │ │ + stc2l 14, cr15, [sp, #72] @ 0x48 │ │ + stc2l 14, cr15, [pc, #-72]! @ 21026a0 >, std::__ndk1::basic_string, std::__ndk1::allocator >, std::__ndk1::less > >, std::__ndk1::allocator > const, std::__ndk1::basic_string, std::__ndk1::allocator > > > > const&, std::__ndk1::basic_string_view >)@@Base+0x3d0> │ │ adds r5, #78 @ 0x4e │ │ mrc2 4, 0, r3, cr4, cr6, {7} │ │ cdp2 5, 1, cr9, cr4, cr10, {0} │ │ mrc2 4, 0, r9, cr4, cr8, {5} │ │ mrc2 12, 0, r9, cr4, cr12, {0} │ │ @ instruction: 0xfe139bc8 │ │ - mrc2 13, 0, fp, cr3, cr2, {6} │ │ - mrc2 13, 0, fp, cr1, cr12, {3} │ │ - mrc2 2, 0, r6, cr1, cr2, {0} │ │ - cdp2 1, 1, cr6, cr2, cr0, {6} │ │ + mrc2 13, 0, fp, cr3, cr15, {7} │ │ + cdp2 13, 1, cr11, cr1, cr9, {5} │ │ + mrc2 2, 0, r6, cr1, cr15, {1} │ │ + cdp2 1, 1, cr6, cr2, cr13, {7} │ │ cdp2 14, 1, cr12, cr2, cr2, {2} │ │ cdp2 0, 1, cr15, cr4, cr15, {2} │ │ adds r0, #255 @ 0xff │ │ cmp r4, #1 │ │ it hi │ │ movhi r0, #1 │ │ cmp r0, #0 │ │ @@ -199451,23 +199451,23 @@ │ │ ldrne r0, [sp, #108] @ 0x6c │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ strh r0, [r1, r5] │ │ lsls r3, r4, #1 │ │ ldrb r4, [r7, #17] │ │ - mrc2 10, 0, r9, cr3, cr11, {5} @ │ │ + @ instruction: 0xfe139ae8 │ │ cdp2 12, 1, cr12, cr1, cr13, {3} │ │ @ instruction: 0xfe14f960 │ │ mrc2 15, 0, r7, cr0, cr9, {6} │ │ cdp2 1, 1, cr6, cr1, cr10, {7} │ │ cdp2 5, 1, cr15, cr1, cr9, {7} │ │ cdp2 15, 1, cr7, cr3, cr8, {0} │ │ - mrc2 14, 0, r9, cr1, cr11, {2} │ │ - mrc2 12, 0, r7, cr2, cr15, {0} │ │ + cdp2 14, 1, cr9, cr1, cr8, {4} │ │ + cdp2 12, 1, cr7, cr2, cr12, {2} │ │ mrc2 13, 0, r4, cr2, cr6, {7} │ │ lsls r3, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ mov r8, r0 │ │ ldr.w r0, [r8, #4]! │ │ @@ -202744,15 +202744,15 @@ │ │ movs r7, #82 @ 0x52 │ │ ldr r1, [sp, #640] @ 0x280 │ │ ands r6, r7 │ │ movs r0, r0 │ │ movs r0, r0 │ │ movs r0, r0 │ │ eors r6, r1 │ │ - adds r3, #17 │ │ + adds r3, #62 @ 0x3e │ │ Address 0x210503a is out of bounds. │ │ │ │ │ │ 0210503c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ @@ -202863,16 +202863,16 @@ │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ movs r5, #224 @ 0xe0 │ │ lsls r3, r4, #1 │ │ add r7, sp, #888 @ 0x378 │ │ mrc2 6, 0, r2, cr3, cr4, {1} │ │ lsls r3, r4, #1 │ │ - asrs r2, r4, #22 │ │ - cdp2 5, 1, cr1, cr2, cr0, {4} │ │ + asrs r7, r1, #23 │ │ + cdp2 5, 1, cr1, cr2, cr13, {5} │ │ cdp2 7, 1, cr5, cr2, cr0, {7} │ │ mrc2 4, 0, r2, cr1, cr10, {6} │ │ lsls r3, r4, #1 │ │ bmi.n 2105130 │ │ bmi.n 2105132 │ │ │ │ 02105188 : │ │ @@ -204613,26 +204613,26 @@ │ │ b.n 21063f2 (char const*, char const*, fmt::v11::detail::tm_format_checker&&)@@Base+0x29a> │ │ b.n 21063f2 (char const*, char const*, fmt::v11::detail::tm_format_checker&&)@@Base+0x29a> │ │ b.n 21063f2 (char const*, char const*, fmt::v11::detail::tm_format_checker&&)@@Base+0x29a> │ │ b.n 21063f2 (char const*, char const*, fmt::v11::detail::tm_format_checker&&)@@Base+0x29a> │ │ mov r0, r4 │ │ blx 26ffc20 │ │ blx 26ffb60 │ │ - ldrsh r4, [r6, r2] │ │ + ldrsh r1, [r4, r3] │ │ cdp2 3, 1, cr1, cr1, cr6, {3} │ │ lsls r3, r4, #1 │ │ asrs r0, r5, #13 │ │ lsls r3, r4, #1 │ │ - ldrsh r0, [r5, r3] │ │ - mrc2 14, 0, r5, cr1, cr6, {6} │ │ - mrc2 14, 0, r5, cr1, cr8, {3} │ │ - mrc2 14, 0, r5, cr1, cr14, {7} │ │ - cdp2 14, 1, cr5, cr1, cr10, {4} │ │ - cdp2 14, 1, cr5, cr1, cr6, {3} │ │ - mrc2 14, 0, r5, cr1, cr12, {4} │ │ + ldrsh r5, [r2, r4] │ │ + cdp2 15, 1, cr5, cr1, cr3, {0} │ │ + cdp2 14, 1, cr5, cr1, cr5, {5} │ │ + cdp2 15, 1, cr5, cr1, cr11, {1} │ │ + mrc2 14, 0, r5, cr1, cr7, {5} │ │ + mrc2 14, 0, r5, cr1, cr3, {4} │ │ + cdp2 14, 1, cr5, cr1, cr9, {6} │ │ Address 0x2106422 is out of bounds. │ │ │ │ │ │ 02106424 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ movs r0, #8 │ │ @@ -204648,15 +204648,15 @@ │ │ ldr r1, [r0, #0] │ │ mov r0, r4 │ │ ldr r2, [r2, #0] │ │ blx 26ffc10 │ │ mov r0, r4 │ │ blx 26ffc20 │ │ blx 26ffb60 │ │ - str r4, [r5, #72] @ 0x48 │ │ + str r1, [r3, #76] @ 0x4c │ │ cdp2 2, 1, cr1, cr2, cr0, {5} │ │ lsls r3, r4, #1 │ │ asrs r2, r4, #10 │ │ lsls r3, r4, #1 │ │ │ │ 02106460 ::do_format > >(tm const&, fmt::v11::context&, std::__ndk1::chrono::duration > const*) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -205650,15 +205650,15 @@ │ │ b.n 2106ef6 > >, char, std::__ndk1::chrono::duration > >&>(char const*, char const*, fmt::v11::detail::tm_writer > >, char, std::__ndk1::chrono::duration > >&)@@Base+0x8fe> │ │ ldr r4, [pc, #12] @ (2106db4 > >, char, std::__ndk1::chrono::duration > >&>(char const*, char const*, fmt::v11::detail::tm_writer > >, char, std::__ndk1::chrono::duration > >&)@@Base+0x7bc>) │ │ add r4, pc │ │ b.n 2106f0e > >, char, std::__ndk1::chrono::duration > >&>(char const*, char const*, fmt::v11::detail::tm_writer > >, char, std::__ndk1::chrono::duration > >&)@@Base+0x916> │ │ mls lr, r2, r0, pc │ │ lsrs r0, r3, #9 │ │ lsls r3, r4, #1 │ │ - bl 22c29dc │ │ + bl 22ef9dc │ │ mov.w r1, r9, asr #31 │ │ strd r0, r1, [sp, #16] │ │ movw r0, #1900 @ 0x76c │ │ adds.w r5, r9, r0 │ │ str r5, [sp, #12] │ │ adc.w r4, r1, #0 │ │ str r4, [sp, #8] │ │ @@ -205994,29 +205994,29 @@ │ │ b.n 2107122 > >, char, std::__ndk1::chrono::duration > >&>(char const*, char const*, fmt::v11::detail::tm_writer > >, char, std::__ndk1::chrono::duration > >&)@@Base+0xb2a> │ │ b.n 2107122 > >, char, std::__ndk1::chrono::duration > >&>(char const*, char const*, fmt::v11::detail::tm_writer > >, char, std::__ndk1::chrono::duration > >&)@@Base+0xb2a> │ │ mov r0, r4 │ │ blx 26ffc20 │ │ blx 26ffb60 │ │ asrs r2, r4, #32 │ │ lsls r3, r4, #1 │ │ - str r0, [r2, r6] │ │ + str r5, [r7, r6] │ │ cdp2 6, 1, cr0, cr1, cr2, {2} │ │ lsls r3, r4, #1 │ │ lsls r4, r0, #25 │ │ lsls r3, r4, #1 │ │ - str r4, [r0, r7] │ │ - mrc2 1, 0, r5, cr1, cr2, {5} │ │ - cdp2 0, 1, cr15, cr1, cr3, {3} │ │ + str r1, [r6, r7] │ │ + mrc2 1, 0, r5, cr1, cr15, {6} │ │ + mrc2 0, 0, pc, cr1, cr0, {4} │ │ mrc2 12, 0, r1, cr2, cr2, {2} │ │ mrc2 12, 0, r1, cr1, cr8, {2} │ │ - cdp2 1, 1, cr5, cr1, cr12, {3} │ │ - cdp2 1, 1, cr5, cr1, cr8, {2} │ │ - mrc2 1, 0, r5, cr1, cr14, {3} │ │ - mrc2 1, 0, r5, cr1, cr6, {1} │ │ - mrc2 1, 0, r5, cr1, cr10, {2} │ │ + mrc2 1, 0, r5, cr1, cr9, {4} │ │ + mrc2 1, 0, r5, cr1, cr5, {3} │ │ + cdp2 1, 1, cr5, cr1, cr11, {5} │ │ + cdp2 1, 1, cr5, cr1, cr3, {3} │ │ + cdp2 1, 1, cr5, cr1, cr7, {4} │ │ cdp2 0, 1, cr1, cr1, cr10, {0} │ │ lsls r3, r4, #1 │ │ │ │ 02107168 > >, char, std::__ndk1::chrono::duration > >::on_year(fmt::v11::detail::numeric_system)@@Base>: │ │ cbz r1, 2107178 > >, char, std::__ndk1::chrono::duration > >::on_year(fmt::v11::detail::numeric_system)@@Base+0x10> │ │ ldrb r1, [r0, #4] │ │ cmp r1, #0 │ │ @@ -206852,18 +206852,18 @@ │ │ mov.w r1, r0, asr #31 │ │ adc.w r3, r1, #0 │ │ mov r0, r4 │ │ ldr.w fp, [sp], #4 │ │ ldmia.w sp!, {r4, r5, r6, r7, lr} │ │ b.w 26fec90 │ │ nop │ │ - b.n 2107796 > >, char, std::__ndk1::chrono::duration > >::on_day_of_month(fmt::v11::detail::numeric_system, fmt::v11::detail::pad_type)@@Base+0x2> │ │ + b.n 21077f0 > >, char, std::__ndk1::chrono::duration > >::on_minute(fmt::v11::detail::numeric_system, fmt::v11::detail::pad_type)@@Base+0x6> │ │ mrc2 14, 0, pc, cr2, cr6, {7} │ │ lsls r2, r4, #1 │ │ - b.n 21076e6 > >, char, std::__ndk1::chrono::duration > >::on_day_of_year()@@Base+0x12> │ │ + b.n 2107740 > >, char, std::__ndk1::chrono::duration > >::on_day_of_year()@@Base+0x6c> │ │ cdp2 14, 1, cr15, cr2, cr12, {4} │ │ lsls r2, r4, #1 │ │ │ │ 02107990 > >, char, std::__ndk1::chrono::duration > >::on_loc_date(fmt::v11::detail::numeric_system)@@Base>: │ │ mov r2, r1 │ │ ldrb r1, [r0, #4] │ │ cmp r1, #0 │ │ @@ -207981,15 +207981,15 @@ │ │ add r0, sp, #104 @ 0x68 │ │ blx 26ffd60 │ │ blx 26ffb60 │ │ @ instruction: 0xf2de0062 │ │ @ instruction: 0xf3d00062 │ │ @ instruction: 0xf3d00062 │ │ @ instruction: 0xf3560062 │ │ - movs r2, #156 @ 0x9c │ │ + movs r2, #201 @ 0xc9 │ │ mrc2 2, 0, pc, cr2, cr12, {4} │ │ lsls r2, r4, #1 │ │ @ instruction: 0xf28c0062 │ │ @ instruction: 0xf28c0062 │ │ addw r0, sl, #98 @ 0x62 │ │ │ │ 021084b4 > > fmt::v11::detail::write_encoded_tm_str > > >(std::__ndk1::back_insert_iterator > >, fmt::v11::basic_string_view, std::__ndk1::locale const&)@@Base>: │ │ @@ -208227,15 +208227,15 @@ │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ @ instruction: 0xf25a0062 │ │ adcs.w r0, ip, #98 @ 0x62 │ │ movw r0, #8290 @ 0x2062 │ │ sub.w r0, ip, #98 @ 0x62 │ │ - movs r0, #40 @ 0x28 │ │ + movs r0, #85 @ 0x55 │ │ cdp2 0, 1, cr15, cr2, cr8, {1} │ │ lsls r2, r4, #1 │ │ ands.w r0, r8, #98 @ 0x62 │ │ ands.w r0, r8, #98 @ 0x62 │ │ vext.8 q0, q2, q9, #0 │ │ │ │ 02108724 > >::~formatbuf()@@Base>: │ │ @@ -208390,15 +208390,15 @@ │ │ ldr r2, [r2, #0] │ │ blx 26ffc10 │ │ mov r0, r4 │ │ blx 26ffc20 │ │ blx 26ffb60 │ │ vhadd.s q0, q3, q9 │ │ cdp 0, 1, cr0, cr6, cr2, {3} │ │ - subs r0, r6, #1 │ │ + subs r5, r3, #2 │ │ cdp2 14, 1, cr14, cr2, cr4, {3} │ │ lsls r2, r4, #1 │ │ cdp 0, 6, cr0, cr6, cr2, {3} │ │ ldcl 0, cr0, [lr, #392] @ 0x188 │ │ │ │ 021088a8 >::grow(fmt::v11::detail::buffer&, unsigned int)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -209619,15 +209619,15 @@ │ │ b.n 210941c │ │ bl 210b1fc │ │ bl 2088524 >::~basic_teestream()@@Base+0xf0> │ │ b.n 2109ad0 >, float, float)@@Base+0x200> │ │ lsls r2, r4, #1 │ │ b.n 2109aac >, float, float)@@Base+0x1dc> │ │ lsls r2, r4, #1 │ │ - ldmia r3, {r0, r1, r3, r4} │ │ + ldmia r3, {r3, r6} │ │ Address 0x2109572 is out of bounds. │ │ │ │ │ │ 02109574 : │ │ ldrd r3, r2, [r0, #36] @ 0x24 │ │ cmp r3, r2 │ │ beq.n 21095dc │ │ @@ -209904,16 +209904,16 @@ │ │ add r0, sp, #36 @ 0x24 │ │ bl 2109854 │ │ blx 26ffb60 │ │ b.n 2109898 │ │ lsls r2, r4, #1 │ │ b.n 2109a9c >, float, float)@@Base+0x1cc> │ │ lsls r2, r4, #1 │ │ - ldmia r0, {r0, r7} │ │ - vfmsl.f16 q6, d2, d1[2] │ │ + ldmia r0!, {r1, r2, r3, r5, r7} │ │ + vfmsl.f16 d12, s5, s12[1] │ │ cdp2 14, 1, cr13, cr2, cr6, {1} │ │ lsls r2, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ ldr r4, [r0, #0] │ │ movs r1, #0 │ │ str r1, [r0, #0] │ │ @@ -211042,15 +211042,15 @@ │ │ blx 2703fb0 │ │ mov r1, r0 │ │ str r0, [r4, #4] │ │ ldmia.w sp!, {r4, r6, r7, lr} │ │ mov r0, r1 │ │ bx lr │ │ nop │ │ - lsls r4, r7, #6 │ │ + lsls r1, r5, #7 │ │ Address 0x210a556 is out of bounds. │ │ │ │ │ │ 0210a558 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -211226,15 +211226,15 @@ │ │ ittt eq │ │ addeq sp, #8 │ │ ldreq.w fp, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ ldmia r7, {r1, r5, r6, r7} │ │ lsls r2, r4, #1 │ │ - lsls r0, r3, #2 │ │ + lsls r5, r0, #3 │ │ mrc2 0, 0, sp, cr2, cr12, {6} │ │ lsls r2, r4, #1 │ │ ldrb r5, [r2, #4] │ │ cdp2 15, 1, cr12, cr3, cr10, {3} │ │ lsls r2, r4, #1 │ │ │ │ 0210a6ec const&, Eigen::Matrix const&)@@Base>: │ │ @@ -211287,15 +211287,15 @@ │ │ mov r1, r5 │ │ mov r2, r8 │ │ ldmia.w sp!, {r8, r9, fp} │ │ ldmia.w sp!, {r4, r5, r6, r7, lr} │ │ b.w 26fecc0 │ │ ldmia.w sp!, {r8, r9, fp} │ │ pop {r4, r5, r6, r7, pc} │ │ - vcvt.f32.u32 d15, d1, #28 │ │ + @ instruction: 0xffd1fe11 │ │ │ │ 0210a78c : │ │ ldr r0, [r0, #0] │ │ b.w 26feccc │ │ │ │ 0210a792 : │ │ push {r4, r6, r7, lr} │ │ @@ -212130,18 +212130,18 @@ │ │ ldrd pc, lr, [r9, #-76]! @ 0x4c │ │ cmp r7, #218 @ 0xda │ │ lsls r5, r4, #1 │ │ ldmia r1, {r1, r5, r7} │ │ lsls r2, r4, #1 │ │ ldmia r0!, {r2, r3, r5, r6} │ │ lsls r2, r4, #1 │ │ - asrs r4, r2, #21 │ │ + asrs r1, r0, #22 │ │ vfmsl.f16 d12, s2, s13[0] │ │ lsls r2, r4, #1 │ │ - bmi.n 210b0f2 │ │ + bmi.n 210af4c │ │ cdp2 12, 1, cr13, cr2, cr14, {7} │ │ vcmla.f16 q6, q0, d4[0], #90 │ │ lsls r2, r4, #1 │ │ stmia r7!, {r2, r3, r6} │ │ lsls r2, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -215196,34 +215196,34 @@ │ │ beq.n 210d0c2 │ │ ldr r0, [sp, #8] │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ add r1, sp, #768 @ 0x300 │ │ lsls r2, r4, #1 │ │ - asrs r1, r0, #27 │ │ + asrs r6, r5, #27 │ │ mrc2 5, 0, r5, cr1, cr6, {1} │ │ - vfmsl.f16 , d0, d2[0] │ │ + vfmsl.f16 , d0, d7[3] │ │ cdp2 5, 1, cr7, cr2, cr12, {1} │ │ - mrc2 9, 0, r9, cr0, cr11, {1} @ │ │ - mrc2 9, 0, sp, cr1, cr10, {1} @ │ │ + @ instruction: 0xfe109968 │ │ + @ instruction: 0xfe11d967 │ │ cdp2 13, 1, cr11, cr1, cr10, {4} │ │ - vfmsl.f16 , d16, d3[3] │ │ + vselvs.f16 s26, s0, s17 │ │ mrc2 6, 0, sp, cr1, cr12, {5} │ │ cdp2 4, 1, cr7, cr2, cr5, {3} │ │ vfmsl.f16 d12, s1, s13[1] │ │ cdp2 2, 1, cr3, cr3, cr7, {1} │ │ - cdp2 4, 1, cr11, cr3, cr11, {0} │ │ - cdp2 4, 1, cr15, cr2, cr13, {4} │ │ + mrc2 4, 0, fp, cr3, cr8, {1} │ │ + mrc2 4, 0, pc, cr2, cr10, {5} │ │ mrc2 2, 0, pc, cr0, cr8, {4} │ │ - cdp2 4, 1, cr1, cr2, cr9, {6} │ │ - cdp2 4, 1, cr15, cr1, cr12, {1} │ │ - cdp2 4, 1, cr1, cr0, cr10, {4} │ │ - cdp2 3, 1, cr1, cr1, cr8, {4} │ │ - mrc2 15, 0, r8, cr2, cr1, {7} │ │ + mrc2 4, 0, r1, cr2, cr6, {7} │ │ + mrc2 4, 0, pc, cr1, cr9, {2} │ │ + mrc2 4, 0, r1, cr0, cr7, {5} │ │ + mrc2 3, 0, r1, cr1, cr5, {5} │ │ + mrc2 0, 0, r9, cr2, cr14, {0} │ │ @ instruction: 0xfe1289cb │ │ mrc2 14, 0, sl, cr3, cr10, {2} │ │ mrc2 1, 0, pc, cr3, cr5, {4} │ │ cdp2 5, 1, cr10, cr2, cr2, {7} │ │ lsls r2, r4, #1 │ │ │ │ 0210d12c : │ │ @@ -215605,18 +215605,18 @@ │ │ ldr r0, [pc, #24] @ (210d4f0 , std::__ndk1::basic_string_view >, celestia::util::NumberFormat) const@@Base+0x148>) │ │ add r0, pc │ │ bl 2093de8 , std::__ndk1::allocator > fmt::v11::detail::vformat(std::__ndk1::locale const&, fmt::v11::basic_string_view, fmt::v11::detail::vformat_args::type)@@Base+0x140> │ │ add r2, pc, #456 @ (adr r2, 210d6a8 , std::__ndk1::basic_string_view >, unsigned int) const@@Base+0x1b4>) │ │ lsls r2, r4, #1 │ │ ldr r3, [pc, #804] @ (210d808 , fmt::v11::basic_memory_buffer >&, celestia::util::NumberFormat) const@@Base+0xdc>) │ │ mrc2 4, 0, sp, cr3, cr5, {5} │ │ - cdp2 4, 1, cr11, cr0, cr14, {1} │ │ + mrc2 4, 0, fp, cr0, cr11, {2} │ │ mrc2 1, 0, sl, cr1, cr0, {3} │ │ lsls r2, r4, #1 │ │ - lsrs r1, r0, #24 │ │ + lsrs r6, r5, #24 │ │ Address 0x210d4f2 is out of bounds. │ │ │ │ │ │ 0210d4f4 , std::__ndk1::basic_string_view >, unsigned int) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -215833,16 +215833,16 @@ │ │ lsls r3, r4, #21 │ │ movs r0, r0 │ │ bcc.n 210d632 , std::__ndk1::basic_string_view >, unsigned int) const@@Base+0x13e> │ │ mrc2 5, 0, r0, cr0, cr5, {4} │ │ movs r0, r0 │ │ bcs.n 210d676 , std::__ndk1::basic_string_view >, unsigned int) const@@Base+0x182> │ │ mrc2 3, 0, sp, cr0, cr11, {2} │ │ - mrc2 2, 0, fp, cr0, cr10, {5} │ │ - cdp2 2, 1, cr11, cr1, cr14, {1} │ │ + cdp2 2, 1, cr11, cr0, cr7, {7} │ │ + mrc2 2, 0, fp, cr1, cr11, {2} │ │ mrc2 15, 0, r9, cr1, cr12, {1} │ │ lsls r2, r4, #1 │ │ │ │ 0210d72c , fmt::v11::basic_memory_buffer >&, celestia::util::NumberFormat) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -216189,17 +216189,17 @@ │ │ b.n 210d7b4 , fmt::v11::basic_memory_buffer >&, celestia::util::NumberFormat) const@@Base+0x88> │ │ ldr r6, [sp, #968] @ 0x3c8 │ │ lsls r2, r4, #1 │ │ ldr r6, [sp, #192] @ 0xc0 │ │ lsls r2, r4, #1 │ │ bx r9 │ │ mrc2 7, 0, r2, cr3, cr6, {5} │ │ - cdp2 13, 1, cr2, cr3, cr11, {2} │ │ + mrc2 13, 0, r2, cr3, cr8, {3} │ │ mrc2 0, 0, sp, cr1, cr3, {2} │ │ - cdp2 14, 1, cr10, cr0, cr8, {2} │ │ + mrc2 14, 0, sl, cr0, cr5, {3} │ │ mrc2 10, 0, r0, cr1, cr11, {6} @ │ │ mrc2 14, 0, r9, cr3, cr4, {3} │ │ lsls r2, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #48 @ 0x30 │ │ ldr r3, [pc, #176] @ (210db90 , fmt::v11::basic_memory_buffer >&, celestia::util::NumberFormat) const@@Base+0x464>) │ │ @@ -216273,21 +216273,21 @@ │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ ldr r0, [pc, #28] @ (210dba8 , fmt::v11::basic_memory_buffer >&, celestia::util::NumberFormat) const@@Base+0x47c>) │ │ add r0, pc │ │ blx 27025b0 │ │ ldr r3, [sp, #304] @ 0x130 │ │ lsls r2, r4, #1 │ │ - cmp r3, #67 @ 0x43 │ │ + cmp r3, #112 @ 0x70 │ │ vselvs.f16 s0, s2, s14 │ │ cdp2 13, 1, cr12, cr3, cr15, {5} │ │ mrc2 9, 0, r0, cr0, cr3, {1} @ │ │ mrc2 10, 0, r9, cr3, cr6, {5} @ │ │ lsls r2, r4, #1 │ │ - b.n 210d91c , fmt::v11::basic_memory_buffer >&, celestia::util::NumberFormat) const@@Base+0x1f0> │ │ + b.n 210d976 , fmt::v11::basic_memory_buffer >&, celestia::util::NumberFormat) const@@Base+0x24a> │ │ Address 0x210dbaa is out of bounds. │ │ │ │ │ │ 0210dbac >, bool)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -216549,22 +216549,22 @@ │ │ itt ne │ │ ldrne r0, [sp, #32] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ ldr r2, [sp, #456] @ 0x1c8 │ │ lsls r2, r4, #1 │ │ - add r4, sp, #732 @ 0x2dc │ │ + add r4, sp, #912 @ 0x390 │ │ cdp2 0, 1, cr6, cr1, cr6, {2} │ │ cdp2 5, 1, cr6, cr3, cr4, {6} │ │ mrc2 5, 0, r4, cr0, cr3, {3} │ │ mrc2 3, 0, r2, cr0, cr3, {5} │ │ - cdp2 6, 1, cr0, cr3, cr0, {6} │ │ + cdp2 6, 1, cr0, cr3, cr13, {7} │ │ mrc2 9, 0, fp, cr1, cr3, {7} @ │ │ - mrc2 6, 0, r0, cr3, cr12, {0} │ │ + cdp2 6, 1, cr0, cr3, cr9, {2} │ │ mrc2 10, 0, r9, cr1, cr4, {2} @ │ │ lsls r2, r4, #1 │ │ │ │ 0210de74 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -216909,16 +216909,16 @@ │ │ blx 26ffb60 │ │ nop │ │ @ instruction: 0xb8d3 │ │ cdp2 7, 1, cr9, cr3, cr4, {5} │ │ lsls r2, r4, #1 │ │ str r4, [sp, #728] @ 0x2d8 │ │ lsls r2, r4, #1 │ │ - ldrsh r2, [r2, r4] │ │ - mrc2 13, 0, r5, cr2, cr6, {7} │ │ + ldrsh r7, [r7, r4] │ │ + cdp2 14, 1, cr5, cr2, cr3, {1} │ │ Address 0x210e22a is out of bounds. │ │ │ │ │ │ 0210e22c : │ │ vldr d16, [r1] │ │ movs r3, #0 │ │ ldr r2, [r1, #8] │ │ @@ -217092,15 +217092,15 @@ │ │ ldmiaeq.w sp!, {r8, r9, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ bl 207deaa │ │ nop │ │ str r2, [sp, #896] @ 0x380 │ │ lsls r2, r4, #1 │ │ - subs r5, #104 @ 0x68 │ │ + subs r5, #149 @ 0x95 │ │ cdp2 2, 1, cr9, cr2, cr0, {6} │ │ lsls r2, r4, #1 │ │ str r2, [sp, #408] @ 0x198 │ │ lsls r2, r4, #1 │ │ │ │ 0210e3f4 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -217281,19 +217281,19 @@ │ │ ldrb.w r0, [sp, #16] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #24] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ - mrc2 14, 3, pc, cr6, cr1, {0} │ │ + mcr2 14, 5, pc, cr3, cr1, {0} @ │ │ str r1, [sp, #440] @ 0x1b8 │ │ lsls r2, r4, #1 │ │ - udf #188 @ 0xbc │ │ - mrc2 15, 0, pc, cr0, cr4, {0} │ │ + udf #233 @ 0xe9 │ │ + cdp2 15, 1, cr15, cr0, cr1, {2} │ │ mrc2 0, 0, r9, cr0, cr2, {5} │ │ lsls r2, r4, #1 │ │ │ │ 0210e5e4 >)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -217454,15 +217454,15 @@ │ │ subs r4, r3, #2 │ │ lsls r1, r4, #1 │ │ subs r4, r0, #4 │ │ lsls r1, r4, #1 │ │ subs r6, r5, #6 │ │ lsls r1, r4, #1 │ │ ldr r1, [sp, #256] @ 0x100 │ │ - vselvs.f64 d15, d20, d7 │ │ + mrc2 11, 0, pc, cr4, cr4, {5} @ │ │ Address 0x210e782 is out of bounds. │ │ │ │ │ │ 0210e784 >)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ @@ -217706,15 +217706,15 @@ │ │ adds r4, r1, #1 │ │ lsls r1, r4, #1 │ │ adds r6, r0, #4 │ │ lsls r1, r4, #1 │ │ adds r2, r1, #5 │ │ lsls r1, r4, #1 │ │ str r6, [sp, #880] @ 0x370 │ │ - mrc2 9, 0, pc, cr4, cr15, {0} @ │ │ + @ instruction: 0xfe14f94c │ │ Address 0x210e9ea is out of bounds. │ │ │ │ │ │ 0210e9ec : │ │ ldr r0, [pc, #8] @ (210e9f8 ) │ │ add r0, pc │ │ ldr r0, [r0, #0] │ │ @@ -221106,15 +221106,15 @@ │ │ itt ne │ │ ldrne.w r0, [r8, #8] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ ldr r2, [r4, #4] │ │ lsls r2, r4, #1 │ │ - str r7, [r7, r5] │ │ + str r4, [r5, r6] │ │ mrc2 7, 0, r6, cr2, cr10, {1} │ │ lsls r2, r4, #1 │ │ │ │ 02110f2c >)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -221270,15 +221270,15 @@ │ │ lsls r4, r4, #1 │ │ str r6, [r5, #108] @ 0x6c │ │ lsls r2, r4, #1 │ │ ldmia r4, {r1, r2, r4, r6, r7} │ │ lsls r4, r4, #1 │ │ ldmia r4, {r1, r2, r3, r4, r5} │ │ lsls r4, r4, #1 │ │ - ldr r7, [pc, #100] @ (2111138 >, std::__ndk1::basic_string_view >)@@Base+0x3a>) │ │ + ldr r7, [pc, #280] @ (21111ec >, std::__ndk1::basic_string_view >) const@@Base+0x10>) │ │ cdp2 12, 1, cr12, cr2, cr4, {5} │ │ lsls r4, r4, #1 │ │ ldmia r5, {r1, r3, r5, r6} │ │ lsls r4, r4, #1 │ │ str r4, [r1, #92] @ 0x5c │ │ lsls r2, r4, #1 │ │ │ │ @@ -222820,15 +222820,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #40] @ 0x28 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ ldrh r6, [r6, r3] │ │ lsls r2, r4, #1 │ │ - ldrd pc, lr, [r2], #68 @ 0x44 │ │ + ldmdb pc, {r0, r4, r9, sl, fp, ip, sp, lr, pc} │ │ b.n 2111ec8 │ │ lsls r0, r4, #1 │ │ b.n 2111df4 │ │ lsls r0, r4, #1 │ │ ldrsb r0, [r4, r4] │ │ lsls r2, r4, #1 │ │ │ │ @@ -224585,15 +224585,15 @@ │ │ ldr r1, [pc, #16] @ (21131b8 , std::__ndk1::allocator >&)@@Base+0xac>) │ │ mov r0, r4 │ │ add r1, pc │ │ ldr.w fp, [sp], #4 │ │ ldmia.w sp!, {r4, r5, r6, r7, lr} │ │ b.w 26fecfc │ │ nop │ │ - bmi.n 2113230 >, std::__ndk1::basic_string_view >)@@Base+0x74> │ │ + bmi.n 211328a >, std::__ndk1::basic_string_view >)@@Base+0xce> │ │ Address 0x21131ba is out of bounds. │ │ │ │ │ │ 021131bc >, std::__ndk1::basic_string_view >)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -225355,18 +225355,18 @@ │ │ ldr r0, [sp, #24] │ │ mov.w r1, #4194304 @ 0x400000 │ │ b.w 2113934 >, unsigned long long, std::__ndk1::less > >, std::__ndk1::allocator > const, unsigned long long> > >&)@@Base+0x424> │ │ adcs r2, r4 │ │ lsls r2, r4, #1 │ │ ldrsb r1, [r7, r1] │ │ cdp2 12, 1, cr8, cr0, cr13, {3} │ │ - cdp2 2, 1, cr1, cr2, cr2, {2} │ │ + cdp2 2, 1, cr1, cr2, cr15, {3} │ │ mrc2 15, 0, r6, cr1, cr0, {3} │ │ mrc2 15, 0, fp, cr2, cr0, {4} │ │ - mrc2 1, 0, sp, cr3, cr5, {6} │ │ + cdp2 2, 1, cr13, cr3, cr2, {0} │ │ cdp2 12, 1, cr14, cr0, cr6, {4} │ │ cdp2 7, 0, cr0, cr15, cr12, {0} │ │ cdp2 12, 1, cr14, cr3, cr6, {2} │ │ mcr2 6, 0, r4, cr15, cr2, {1} │ │ mov r3, r5 │ │ strd r1, sl, [r0, #24] │ │ mov r1, r4 │ │ @@ -225495,30 +225495,30 @@ │ │ cdp2 14, 1, cr11, cr3, cr13, {4} │ │ mrc2 11, 0, lr, cr3, cr0, {5} @ │ │ mcr2 2, 0, sl, cr15, cr14, {2} │ │ cdp2 2, 1, cr8, cr3, cr9, {4} │ │ cdp2 2, 1, cr10, cr3, cr2, {1} │ │ vfmsl.f16 q7, d3, d5[0] │ │ cdp2 2, 1, cr2, cr2, cr9, {0} │ │ - @ instruction: 0xfe13e96f │ │ - mrc2 9, 0, lr, cr1, cr2, {2} @ │ │ - mrc2 11, 0, r8, cr1, cr13, {3} @ │ │ - cdp2 14, 1, cr14, cr0, cr11, {1} │ │ + mrc2 9, 0, lr, cr3, cr12, {4} @ │ │ + mrc2 9, 0, lr, cr1, cr15, {3} @ │ │ + vselvs.f64 d8, d17, d26 │ │ + mrc2 14, 0, lr, cr0, cr8, {2} │ │ cdp2 1, 1, cr8, cr0, cr3, {3} │ │ - mrc2 15, 0, ip, cr3, cr1, {1} │ │ + mrc2 15, 0, ip, cr3, cr14, {2} │ │ mrc2 11, 0, sl, cr0, cr9, {4} @ │ │ cdp2 7, 1, cr14, cr2, cr7, {0} │ │ mrc2 9, 0, r0, cr2, cr2, {5} @ │ │ - mrc2 5, 0, r0, cr0, cr6, {1} │ │ + cdp2 5, 1, cr0, cr0, cr3, {3} │ │ vfmsl.f16 q4, d2, d6[0] │ │ vselvs.f16 s28, s4, s30 │ │ mcr2 11, 0, r6, cr15, cr13, {2} @ │ │ @ instruction: 0xfe126b41 │ │ - vselvs.f16 s20, s4, s5 │ │ - cdp2 14, 1, cr4, cr1, cr2, {4} │ │ + @ instruction: 0xfe12a94f │ │ + cdp2 14, 1, cr4, cr1, cr15, {5} │ │ @ instruction: 0xfe113bc6 │ │ lsls r2, r4, #1 │ │ │ │ 02113ae8 >, unsigned int, std::__ndk1::less > >, std::__ndk1::allocator > const, unsigned int> > >&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -225762,15 +225762,15 @@ │ │ vfmal.f16 q5, d31, d0[1] │ │ mrc2 7, 0, lr, cr2, cr2, {0} │ │ mcr2 13, 0, r1, cr15, cr5, {7} │ │ vselvs.f16 s22, s7, s14 │ │ mrc2 9, 0, r6, cr3, cr8, {0} @ │ │ mrc2 13, 0, r9, cr2, cr6, {2} │ │ mrc2 9, 0, fp, cr3, cr4, {0} @ │ │ - mrc2 11, 0, ip, cr3, cr13, {2} @ │ │ + vselvs.f64 d12, d19, d10 │ │ cdp2 12, 1, cr2, cr0, cr1, {0} │ │ vfmsl.f16 q3, d0, d5[3] │ │ vcmla.f16 q3, q1, d1[1], #90 │ │ cdp2 3, 1, cr14, cr2, cr8, {0} │ │ vselvs.f16 s6, s4, s28 │ │ lsls r2, r4, #1 │ │ │ │ @@ -225942,22 +225942,22 @@ │ │ blx 26ffb50 │ │ nop │ │ subs r0, #248 @ 0xf8 │ │ lsls r2, r4, #1 │ │ b.n 2114432 >, unsigned long long, std::__ndk1::less > >, std::__ndk1::allocator > const, unsigned long long> > >&)@@Base+0x4e2> │ │ vfmsl.f16 d3, s5, s8[0] │ │ lsls r2, r4, #1 │ │ - ldmia r0!, {r1, r3, r4} │ │ + ldmia r0, {r0, r1, r2, r6} │ │ cdp2 6, 1, cr10, cr1, cr2, {4} │ │ vselvs.f32 s4, s5, s22 │ │ cdp2 15, 1, cr15, cr0, cr1, {1} │ │ - vcmla.f16 q3, q9, d1[1], #90 │ │ - cdp2 4, 1, cr4, cr1, cr15, {3} │ │ + vselvs.f16 s12, s4, s28 │ │ + mrc2 4, 0, r4, cr1, cr12, {4} │ │ mrc2 15, 0, r3, cr2, cr4, {6} │ │ - mrc2 4, 0, r4, cr3, cr10, {1} │ │ + cdp2 4, 1, cr4, cr3, cr7, {3} │ │ mrc2 9, 0, r9, cr2, cr4, {5} @ │ │ cdp2 7, 1, cr3, cr3, cr8, {1} │ │ lsls r2, r4, #1 │ │ │ │ 02113f50 >, unsigned long long, std::__ndk1::less > >, std::__ndk1::allocator > const, unsigned long long> > >&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -226346,39 +226346,39 @@ │ │ mov r2, r6 │ │ mov r3, r5 │ │ strd r1, sl, [r0, #24] │ │ b.w 21143b8 >, unsigned long long, std::__ndk1::less > >, std::__ndk1::allocator > const, unsigned long long> > >&)@@Base+0x468> │ │ adds r7, #34 @ 0x22 │ │ lsls r2, r4, #1 │ │ b.n 2114a2a >, unsigned int, std::__ndk1::less > >, std::__ndk1::allocator > const, unsigned int> > >&)@@Base+0x16> │ │ - mcr2 9, 0, r8, cr15, cr2, {4} @ │ │ - cdp2 3, 1, cr4, cr1, cr13, {1} │ │ + mcr2 9, 0, r8, cr15, cr15, {5} @ │ │ + mrc2 3, 0, r4, cr1, cr10, {2} │ │ mrc2 11, 0, r4, cr2, cr0, {5} @ │ │ vselvs.f16 s18, s1, s6 │ │ - cdp2 3, 1, cr10, cr3, cr15, {0} │ │ + mrc2 3, 0, sl, cr3, cr12, {1} │ │ cdp2 4, 1, cr6, cr1, cr6, {7} │ │ cdp2 6, 1, cr5, cr2, cr12, {7} │ │ mrc2 15, 0, sp, cr3, cr10, {3} │ │ - mrc2 7, 0, ip, cr2, cr4, {0} │ │ - mrc2 13, 0, pc, cr0, cr11, {5} │ │ - mrc2 5, 0, lr, cr1, cr3, {3} │ │ - cdp2 6, 1, cr6, cr0, cr3, {0} │ │ - cdp2 4, 1, cr12, cr1, cr14, {4} │ │ + cdp2 7, 1, cr12, cr2, cr1, {2} │ │ + cdp2 13, 1, cr15, cr0, cr8, {7} │ │ + cdp2 5, 1, cr14, cr1, cr0, {5} │ │ + mrc2 6, 0, r6, cr0, cr0, {1} │ │ + mrc2 4, 0, ip, cr1, cr11, {5} │ │ mrc2 12, 0, r3, cr1, cr4, {7} │ │ - cdp2 4, 1, cr14, cr3, cr9, {7} │ │ + mrc2 5, 0, lr, cr3, cr6, {0} │ │ mrc2 3, 0, r6, cr0, cr7, {3} │ │ mrc2 15, 0, r7, cr2, cr2, {7} │ │ mrc2 3, 0, fp, cr2, cr6, {2} │ │ cdp2 2, 1, cr10, cr3, cr13, {1} │ │ cdp2 7, 1, cr1, cr2, cr3, {3} │ │ - mrc2 0, 0, sl, cr3, cr14, {5} │ │ + cdp2 0, 1, cr10, cr3, cr11, {7} │ │ cdp2 6, 1, cr6, cr1, cr5, {5} │ │ cdp2 5, 1, cr2, cr0, cr11, {6} │ │ - cdp2 6, 1, cr8, cr0, cr6, {2} │ │ - cdp2 15, 1, cr3, cr1, cr3, {7} │ │ + mrc2 6, 0, r8, cr0, cr3, {3} │ │ + mrc2 0, 0, r4, cr1, cr0, {0} │ │ cdp2 6, 1, cr4, cr2, cr1, {1} │ │ ldr r0, [pc, #1012] @ (21147b0 >, unsigned long long, std::__ndk1::less > >, std::__ndk1::allocator > const, unsigned long long> > >&)@@Base+0x860>) │ │ str r6, [sp, #20] │ │ add r0, pc │ │ str r0, [sp, #8] │ │ movs r0, #8 │ │ strd r9, r8, [sp] │ │ @@ -226754,28 +226754,28 @@ │ │ str r6, [sp, #20] │ │ strd r9, r8, [sp] │ │ blx 2704540 │ │ ldr r0, [sp, #24] │ │ mov.w r1, #1048576 @ 0x100000 │ │ b.w 21147e8 >, unsigned long long, std::__ndk1::less > >, std::__ndk1::allocator > const, unsigned long long> > >&)@@Base+0x898> │ │ nop │ │ - add r0, pc, #396 @ (adr r0, 2114940 >, unsigned long long, std::__ndk1::less > >, std::__ndk1::allocator > const, unsigned long long> > >&)@@Base+0x9f0>) │ │ - mrc2 15, 0, r9, cr0, cr4, {3} │ │ - mrc2 2, 0, lr, cr1, cr5, {4} │ │ - cdp2 15, 1, cr9, cr0, cr10, {1} │ │ - mrc2 4, 0, r4, cr1, cr7, {3} │ │ - cdp2 2, 1, cr14, cr1, cr9, {1} │ │ - mrc2 11, 0, r1, cr0, cr6, {2} @ │ │ - mrc2 1, 0, ip, cr2, cr0, {1} │ │ + add r0, pc, #576 @ (adr r0, 21149f4 >, unsigned long long, std::__ndk1::less > >, std::__ndk1::allocator > const, unsigned long long> > >&)@@Base+0xaa4>) │ │ + cdp2 15, 1, cr9, cr0, cr1, {5} │ │ + cdp2 2, 1, cr14, cr1, cr2, {6} │ │ + mrc2 15, 0, r9, cr0, cr7, {2} │ │ + cdp2 4, 1, cr4, cr1, cr4, {5} │ │ + mrc2 2, 0, lr, cr1, cr6, {2} │ │ + vselvs.f64 d1, d16, d3 │ │ + mrc2 1, 0, ip, cr2, cr13, {2} │ │ cdp2 12, 1, cr11, cr1, cr10, {0} │ │ - cdp2 2, 1, cr0, cr2, cr10, {6} │ │ + mrc2 2, 0, r0, cr2, cr7, {7} │ │ @ instruction: 0xfe11394e │ │ cdp2 2, 1, cr5, cr3, cr1, {1} │ │ - cdp2 0, 1, cr12, cr3, cr6, {4} │ │ - mrc2 1, 0, r2, cr1, cr2, {3} │ │ + mrc2 0, 0, ip, cr3, cr3, {5} │ │ + mrc2 1, 0, r2, cr1, cr15, {4} │ │ mrc2 6, 0, r4, cr1, cr2, {1} │ │ mov r3, r5 │ │ strd sl, r1, [r0, #24] │ │ mov r1, r4 │ │ ldr r0, [pc, #496] @ (21149e4 >, unsigned long long, std::__ndk1::less > >, std::__ndk1::allocator > const, unsigned long long> > >&)@@Base+0xa94>) │ │ str r6, [sp, #20] │ │ add r0, pc │ │ @@ -226946,31 +226946,31 @@ │ │ lsls r2, r4, #1 │ │ bl 20b55d8 │ │ bl 209d5dc ::operator()(char const*)@@Base+0x1e3c> │ │ strb r7, [r3, #15] │ │ cdp2 15, 1, cr10, cr3, cr5, {2} │ │ mrc2 14, 0, r9, cr3, cr13, {0} │ │ mrc2 14, 0, r5, cr2, cr2, {6} │ │ - cdp2 12, 1, cr3, cr2, cr11, {3} │ │ - cdp2 12, 1, cr7, cr2, cr11, {7} │ │ - cdp2 15, 1, cr11, cr0, cr11, {0} │ │ + mrc2 12, 0, r3, cr2, cr8, {4} │ │ + mrc2 13, 0, r7, cr2, cr8, {0} │ │ + mrc2 15, 0, fp, cr0, cr8, {1} │ │ cdp2 0, 1, cr5, cr1, cr0, {3} │ │ cdp2 4, 1, cr4, cr3, cr9, {3} │ │ mrc2 4, 0, r4, cr0, cr0, {2} │ │ - mrc2 1, 0, r8, cr0, cr11, {5} │ │ + cdp2 1, 1, cr8, cr0, cr8, {7} │ │ mrc2 3, 0, r4, cr1, cr0, {6} │ │ vcmla.f16 , q8, d5[1], #90 │ │ - mrc2 0, 0, r4, cr2, cr0, {4} │ │ + mrc2 0, 0, r4, cr2, cr13, {5} │ │ cdp2 3, 1, cr4, cr1, cr2, {3} │ │ cdp2 0, 1, cr6, cr0, cr14, {6} │ │ - vselvs.f64 d7, d0, d11 │ │ - cdp2 13, 1, cr13, cr0, cr12, {6} │ │ + mrc2 11, 0, r7, cr0, cr8, {1} @ │ │ + mrc2 13, 0, sp, cr0, cr9, {7} │ │ cdp2 15, 1, cr1, cr0, cr9, {5} │ │ cdp2 0, 1, cr7, cr0, cr5, {6} │ │ - cdp2 13, 1, cr1, cr3, cr0, {6} │ │ + cdp2 13, 1, cr1, cr3, cr13, {7} │ │ mrc2 5, 0, r3, cr1, cr5, {0} │ │ mrc2 12, 0, r2, cr3, cr6, {4} │ │ lsls r2, r4, #1 │ │ │ │ 02114a14 >, unsigned int, std::__ndk1::less > >, std::__ndk1::allocator > const, unsigned int> > >&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -227051,19 +227051,19 @@ │ │ ittt eq │ │ addeq sp, #36 @ 0x24 │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ cmp r4, #96 @ 0x60 │ │ lsls r2, r4, #1 │ │ - adds r5, r5, #3 │ │ + adds r2, r3, #4 │ │ mrc2 11, 0, r2, cr1, cr12, {7} @ │ │ lsls r2, r4, #1 │ │ adcs r7, r5 │ │ - mrc2 5, 0, r1, cr0, cr8, {3} │ │ + cdp2 5, 1, cr1, cr0, cr5, {5} │ │ mrc2 10, 0, sl, cr2, cr11, {6} @ │ │ @ instruction: 0xfe132b62 │ │ lsls r2, r4, #1 │ │ │ │ 02114afc >, unsigned int, std::__ndk1::less > >, std::__ndk1::allocator > const, unsigned int> > >&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -227498,15 +227498,15 @@ │ │ lsls r2, r4, #1 │ │ subs r5, r7, r5 │ │ @ instruction: 0xfe102a60 │ │ lsls r2, r4, #1 │ │ add r0, sp, #168 @ 0xa8 │ │ mrc2 10, 0, r2, cr3, cr14, {1} @ │ │ lsls r2, r4, #1 │ │ - rev16 r5, r5 │ │ + hlt 0x001a │ │ mrc2 10, 0, r2, cr0, cr14, {0} @ │ │ lsls r2, r4, #1 │ │ ldrsb r5, [r5, r6] │ │ mrc2 9, 0, r2, cr2, cr8, {7} @ │ │ lsls r2, r4, #1 │ │ ldrsb r3, [r1, r6] │ │ mrc2 9, 0, r2, cr2, cr4, {6} @ │ │ @@ -227519,18 +227519,18 @@ │ │ lsls r2, r4, #1 │ │ bne.n 2114efe >, Color*, std::__ndk1::less > >, std::__ndk1::allocator > const, Color*> > >&)@@Base+0x342> │ │ mrc2 9, 0, r2, cr2, cr4, {3} @ │ │ lsls r2, r4, #1 │ │ bl 1dc5b72 │ │ cmp r1, #84 @ 0x54 │ │ lsls r2, r4, #1 │ │ - bl 214db7e │ │ + bl 217ab7e >&, StarDatabase const&)@@Base+0x40a> │ │ cmp r1, #52 @ 0x34 │ │ lsls r2, r4, #1 │ │ - str r5, [sp, #632] @ 0x278 │ │ + str r5, [sp, #812] @ 0x32c │ │ mrc2 9, 0, r2, cr0, cr4, {0} @ │ │ lsls r2, r4, #1 │ │ movs r7, #122 @ 0x7a │ │ lsls r2, r4, #1 │ │ │ │ 02114f6c >, Color*, std::__ndk1::less > >, std::__ndk1::allocator > const, Color*> > >&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -227846,15 +227846,15 @@ │ │ movs r7, #8 │ │ lsls r2, r4, #1 │ │ bl 2494e7a │ │ movs r6, #164 @ 0xa4 │ │ lsls r2, r4, #1 │ │ cmp r0, #10 │ │ lsls r2, r4, #1 │ │ - strb r3, [r1, #16] │ │ + strb r0, [r7, #16] │ │ cdp2 7, 1, cr2, cr0, cr8, {7} │ │ lsls r2, r4, #1 │ │ blx r4 │ │ cdp2 7, 1, cr2, cr3, cr6, {6} │ │ lsls r2, r4, #1 │ │ blxns r1 │ │ cdp2 7, 1, cr2, cr3, cr6, {5} │ │ @@ -227864,45 +227864,45 @@ │ │ lsls r2, r4, #1 │ │ bl 23c9ea6 │ │ movs r7, #96 @ 0x60 │ │ lsls r2, r4, #1 │ │ strb r1, [r7, #5] │ │ mrc2 7, 0, r2, cr2, cr14, {1} │ │ lsls r2, r4, #1 │ │ - lsrs r2, r5, #29 │ │ + lsrs r7, r2, #30 │ │ mrc2 7, 0, r2, cr2, cr12, {0} │ │ lsls r2, r4, #1 │ │ strb r4, [r3, r1] │ │ mrc2 6, 0, r2, cr2, cr12, {7} │ │ lsls r2, r4, #1 │ │ - beq.n 2115390 │ │ + beq.n 21151ea >, Color*, std::__ndk1::less > >, std::__ndk1::allocator > const, Color*> > >&)@@Base+0x27e> │ │ mrc2 6, 0, r2, cr1, cr12, {6} │ │ lsls r2, r4, #1 │ │ str r3, [sp, #332] @ 0x14c │ │ mrc2 6, 0, r2, cr2, cr8, {5} │ │ lsls r2, r4, #1 │ │ ldmia r6, {r0, r6, r7} │ │ mrc2 6, 0, r2, cr2, cr8, {4} │ │ lsls r2, r4, #1 │ │ bl 22adede │ │ movs r6, #120 @ 0x78 │ │ lsls r2, r4, #1 │ │ - stc 14, cr15, [r0, #-68]! @ 0xffffffbc │ │ + stcl 14, cr15, [sp, #-68] @ 0xffffffbc │ │ movs r6, #88 @ 0x58 │ │ lsls r2, r4, #1 │ │ - str r2, [sp, #536] @ 0x218 │ │ + str r2, [sp, #716] @ 0x2cc │ │ mrc2 6, 0, r2, cr0, cr6, {1} │ │ lsls r2, r4, #1 │ │ strh r4, [r3, #62] @ 0x3e │ │ mrc2 6, 0, r2, cr3, cr4, {0} │ │ lsls r2, r4, #1 │ │ - adds r6, #214 @ 0xd6 │ │ + adds r7, #3 │ │ mrc2 5, 0, r2, cr1, cr2, {7} │ │ lsls r2, r4, #1 │ │ - adds r6, #199 @ 0xc7 │ │ + adds r6, #244 @ 0xf4 │ │ mrc2 5, 0, r2, cr1, cr2, {6} │ │ lsls r2, r4, #1 │ │ movs r3, #240 @ 0xf0 │ │ lsls r2, r4, #1 │ │ │ │ 021152f0 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -229027,16 +229027,16 @@ │ │ subs r4, r7, r3 │ │ lsls r2, r4, #1 │ │ pop {r1, r2, r3, r7, pc} │ │ mrc2 4, 0, ip, cr3, cr14, {3} │ │ mrc2 3, 0, r3, cr3, cr1, {0} │ │ cdp2 14, 1, cr10, cr4, cr14, {3} │ │ lsls r0, r4, #1 │ │ - strh r3, [r7, #58] @ 0x3a │ │ - mrc2 7, 0, r8, cr0, cr15, {2} │ │ + strh r0, [r5, #60] @ 0x3c │ │ + cdp2 7, 1, cr8, cr0, cr12, {4} │ │ mrc2 15, 0, sl, cr0, cr14, {4} │ │ lsls r0, r4, #1 │ │ add r7, sp, #544 @ 0x220 │ │ lsls r0, r4, #1 │ │ adds r4, r3, r3 │ │ lsls r2, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ @@ -229261,19 +229261,19 @@ │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ stmia r1!, {r3, r5} │ │ mrc2 7, 0, r1, cr2, cr14, {0} │ │ lsls r2, r4, #1 │ │ cbnz r0, 21160f6 │ │ - cdp2 4, 1, cr2, cr3, cr5, {0} │ │ - mrc2 3, 0, r2, cr2, cr9, {2} │ │ - mrc2 3, 0, r6, cr2, cr1, {7} │ │ + mrc2 4, 0, r2, cr3, cr2, {1} │ │ + cdp2 3, 1, cr2, cr2, cr6, {4} │ │ + mrc2 4, 0, r6, cr2, cr14, {0} │ │ mrc2 9, 0, r5, cr0, cr10, {7} @ │ │ - vselvs.f16 s12, s6, s27 │ │ + mrc2 9, 0, r6, cr3, cr10, {2} @ │ │ mrc2 6, 0, r1, cr1, cr10, {3} │ │ lsls r2, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ vpush {d8-d12} │ │ sub sp, #56 @ 0x38 │ │ @@ -229373,16 +229373,16 @@ │ │ nop │ │ movs r0, r0 │ │ movs r0, r0 │ │ cmp r1, #15 │ │ mrc2 5, 0, r1, cr0, cr10, {3} │ │ lsls r2, r4, #1 │ │ @ instruction: 0xf927fe12 │ │ - stmia r0!, {r0, r3, r7} │ │ - mrc2 3, 0, r8, cr1, cr11, {1} │ │ + stmia r0!, {r1, r2, r4, r5, r7} │ │ + cdp2 3, 1, cr8, cr1, cr8, {3} │ │ cdp2 4, 1, cr1, cr0, cr2, {5} │ │ lsls r2, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8} │ │ @@ -229582,17 +229582,17 @@ │ │ movs r0, r0 │ │ movs r0, r0 │ │ @ instruction: 0x4796 │ │ cdp2 4, 1, cr1, cr0, cr4, {2} │ │ lsls r2, r4, #1 │ │ muls r5, r1 │ │ cdp2 14, 1, cr9, cr2, cr8, {5} │ │ - cdp2 0, 1, cr2, cr2, cr14, {5} │ │ - cdp2 5, 1, cr10, cr2, cr5, {0} │ │ - mrc2 4, 0, r4, cr0, cr11, {1} │ │ + mrc2 0, 0, r2, cr2, cr11, {6} │ │ + mrc2 5, 0, sl, cr2, cr2, {1} │ │ + cdp2 4, 1, cr4, cr0, cr8, {3} │ │ cdp2 2, 1, cr1, cr1, cr2, {3} │ │ lsls r2, r4, #1 │ │ pop {r1, r3, r4, r5, pc} │ │ mrc2 5, 0, fp, cr3, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #16 │ │ @@ -229670,15 +229670,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #8] │ │ blxne 26ffb40 │ │ mov r0, r5 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ - pop {r0, r3, r6, pc} │ │ + pop {r1, r2, r4, r5, r6, pc} │ │ cdp2 1, 1, cr1, cr1, cr4, {7} │ │ lsls r2, r4, #1 │ │ cbz r0, 211651e │ │ mrc2 1, 0, r1, cr3, cr6, {2} │ │ lsls r2, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -230010,23 +230010,23 @@ │ │ strb r4, [r0, r1] │ │ movs r1, #251 @ 0xfb │ │ ands r1, r1 │ │ movs r4, #135 @ 0x87 │ │ mrc2 0, 0, r1, cr0, cr2, {7} │ │ lsls r2, r4, #1 │ │ ldr r3, [sp, #752] @ 0x2f0 │ │ - cdp2 3, 1, cr2, cr2, cr2, {3} │ │ - cdp2 13, 1, cr1, cr1, cr14, {3} │ │ - cdp2 3, 1, cr6, cr2, cr7, {4} │ │ - @ instruction: 0xfe11b9c8 │ │ + cdp2 3, 1, cr2, cr2, cr15, {4} │ │ + mrc2 13, 0, r1, cr1, cr11, {4} │ │ + mrc2 3, 0, r6, cr2, cr4, {5} │ │ + mrc2 9, 0, fp, cr1, cr5, {7} @ │ │ cdp2 1, 1, cr15, cr1, cr10, {7} │ │ mrc2 2, 0, r5, cr2, cr4, {0} │ │ mrc2 9, 0, r5, cr3, cr6, {4} @ │ │ - vselvs.f64 d7, d18, d24 │ │ - cdp2 0, 1, cr2, cr0, cr8, {2} │ │ + mrc2 11, 0, r7, cr2, cr5, {6} @ │ │ + mrc2 0, 0, r2, cr0, cr5, {3} │ │ cdp2 12, 1, cr8, cr1, cr12, {6} │ │ cdp2 13, 1, cr0, cr3, cr14, {3} │ │ lsls r2, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ sub sp, #16 │ │ @@ -230228,19 +230228,19 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #8] │ │ blxne 26ffb40 │ │ mov r0, r5 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ - @ instruction: 0xb71d │ │ + @ instruction: 0xb74a │ │ mrc2 11, 0, r0, cr1, cr6, {5} @ │ │ lsls r2, r4, #1 │ │ add r3, sp, #720 @ 0x2d0 │ │ - mrc2 9, 0, r7, cr3, cr10, {6} @ │ │ + vselvs.f32 s14, s6, s14 │ │ mrc2 10, 0, r0, cr0, cr12, {7} @ │ │ lsls r2, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ vpush {d8-d11} │ │ sub sp, #48 @ 0x30 │ │ @@ -230309,15 +230309,15 @@ │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ ldr r0, [r5, #116] @ 0x74 │ │ ldrh r1, [r7, #0] │ │ ldrsh r7, [r4, r6] │ │ subs r6, #124 @ 0x7c │ │ - ldr r3, [r5, r1] │ │ + ldr r0, [r3, r2] │ │ mrc2 10, 0, r0, cr0, cr10, {4} @ │ │ lsls r2, r4, #1 │ │ ldrsb r7, [r1, r2] │ │ mrc2 10, 0, r0, cr2, cr2, {0} @ │ │ lsls r2, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -230448,16 +230448,16 @@ │ │ ands r1, r1 │ │ movs r0, r0 │ │ movs r0, r0 │ │ adds r5, r1, #5 │ │ mrc2 9, 0, r0, cr0, cr8, {5} @ │ │ lsls r2, r4, #1 │ │ stcl 14, cr15, [r5, #-72]! @ 0xffffffb8 │ │ - strb r5, [r7, #30] │ │ - @ instruction: 0xfe103a6a │ │ + strb r2, [r5, #31] │ │ + mrc2 10, 0, r3, cr0, cr7, {4} @ │ │ vcmla.f16 , , d0[1], #90 │ │ vfmsl.f16 d0, s5, s8[1] │ │ lsls r2, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ movs r0, #4 │ │ @@ -230663,21 +230663,21 @@ │ │ eors r6, r4 │ │ cmp r5, #24 │ │ strb r4, [r0, r1] │ │ movs r1, #251 @ 0xfb │ │ ands r1, r1 │ │ movs r0, r0 │ │ movs r0, r0 │ │ - bl 2009c58 │ │ + bl 2036c58 │ │ lsls r2, r3, #31 │ │ lsls r2, r4, #1 │ │ uxth r4, r6 │ │ cdp2 3, 0, cr5, cr15, cr2, {0} │ │ - mrc2 5, 0, r7, cr2, cr4, {0} │ │ - mrc2 9, 0, r1, cr0, cr4, {5} @ │ │ + cdp2 5, 1, cr7, cr2, cr1, {2} │ │ + @ instruction: 0xfe1019e1 │ │ mrc2 6, 0, r8, cr1, cr12, {1} │ │ mrc2 6, 0, r0, cr3, cr10, {1} │ │ lsls r2, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #56 @ 0x38 │ │ @@ -230836,21 +230836,21 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #24] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ blx 26ffb60 │ │ nop │ │ - cbz r1, 211721a │ │ + cbz r6, 2117224 │ │ cdp2 5, 1, cr0, cr1, cr2, {6} │ │ lsls r2, r4, #1 │ │ add r0, sp, #568 @ 0x238 │ │ cdp2 4, 1, cr0, cr3, cr2, {3} │ │ lsls r2, r4, #1 │ │ - @ instruction: 0xef99fe11 │ │ + vmov.i8 d31, #97 @ 0x61 │ │ add r5, pc, #24 @ (adr r5, 211723c ) │ │ mrc2 4, 0, r3, cr3, cr5, {5} │ │ vselvs.f32 s20, s5, s28 │ │ mrc2 5, 0, fp, cr3, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #16 │ │ @@ -230929,15 +230929,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #8] │ │ blxne 26ffb40 │ │ mov r0, r5 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ - add r7, sp, #324 @ 0x144 │ │ + add r7, sp, #504 @ 0x1f8 │ │ cdp2 3, 1, cr0, cr1, cr12, {7} │ │ lsls r2, r4, #1 │ │ add r1, sp, #600 @ 0x258 │ │ mrc2 3, 0, r0, cr3, cr10, {2} │ │ lsls r2, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -231027,15 +231027,15 @@ │ │ blx 26ffb50 │ │ mov r0, r5 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ ldc2l 3, cr4, [r1, #-508]! @ 0xfffffe04 │ │ movs r0, r0 │ │ movs r0, r0 │ │ - stc 14, cr15, [r3, #-68] @ 0xffffffbc │ │ + ldc 14, cr15, [r0, #-68]! @ 0xffffffbc │ │ lsls r0, r1, #12 │ │ lsls r2, r4, #1 │ │ lsls r4, r3, #8 │ │ lsls r2, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -231183,15 +231183,15 @@ │ │ movs r0, r0 │ │ movs r0, r0 │ │ ldc2l 3, cr4, [r1, #-508]! @ 0xfffffe04 │ │ str r2, [r4, #84] @ 0x54 │ │ mrc2 1, 0, r0, cr3, cr6, {6} │ │ lsls r2, r4, #1 │ │ add r7, pc, #608 @ (adr r7, 2117864 ) │ │ - mrc2 11, 0, lr, cr3, cr7, {5} @ │ │ + @ instruction: 0xfe13ebe4 │ │ cdp2 0, 1, cr0, cr1, cr12, {3} │ │ lsls r2, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #48 @ 0x30 │ │ mov r6, r1 │ │ @@ -231337,15 +231337,15 @@ │ │ movs r0, r0 │ │ movs r0, r0 │ │ ldc2l 3, cr4, [r1, #-508]! @ 0xfffffe04 │ │ str r6, [r2, #56] @ 0x38 │ │ cdp2 0, 1, cr0, cr3, cr10, {0} │ │ lsls r2, r4, #1 │ │ add r3, sp, #560 @ 0x230 │ │ - @ instruction: 0xfe13e9eb │ │ + mrc2 10, 0, lr, cr3, cr8, {0} @ │ │ cdp2 14, 1, cr15, cr1, cr0, {5} │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ vpush {d8} │ │ sub sp, #72 @ 0x48 │ │ @@ -231446,18 +231446,18 @@ │ │ lsls r0, r0, #31 │ │ beq.n 21178f4 │ │ ldr r0, [sp, #52] @ 0x34 │ │ b.n 21178f0 │ │ mov r0, r5 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ - ldr r4, [pc, #80] @ (211794c ) │ │ + ldr r4, [pc, #260] @ (2117a00 ) │ │ mrc2 14, 0, pc, cr0, cr10, {1} │ │ lsls r1, r4, #1 │ │ - lsrs r3, r6, #12 │ │ + lsrs r0, r4, #13 │ │ cdp2 5, 1, cr10, cr2, cr10, {0} │ │ cdp2 7, 1, cr10, cr3, cr5, {7} │ │ mrc2 13, 0, pc, cr2, cr10, {4} │ │ lsls r1, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ vpush {d8} │ │ @@ -231594,15 +231594,15 @@ │ │ cmp r0, #0 │ │ itttt ne │ │ ldrbne.w r0, [sp, #20] │ │ movsne.w r0, r0, lsl #31 │ │ ldrne r0, [sp, #28] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ - cmp r5, #183 @ 0xb7 │ │ + cmp r5, #228 @ 0xe4 │ │ cdp2 12, 1, cr15, cr1, cr10, {4} │ │ lsls r1, r4, #1 │ │ add r7, pc, #512 @ (adr r7, 2117c90 ) │ │ cdp2 3, 1, cr12, cr3, cr0, {7} │ │ @ instruction: 0xfe12fbe4 │ │ lsls r1, r4, #1 │ │ push {r4, r5, r7, lr} │ │ @@ -231645,15 +231645,15 @@ │ │ vpopeq {d8} │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ mov r0, r5 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ - ldcl 14, cr15, [r2], #-64 @ 0xffffffc0 │ │ + ldc 14, cr15, [pc], {16} │ │ @ instruction: 0xfb800061 │ │ @ instruction: 0xfb420061 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ vpush {d8} │ │ sub sp, #24 │ │ ldr r2, [pc, #104] @ (2117b8c ) │ │ @@ -231764,15 +231764,15 @@ │ │ ldr.w r8, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ mov r0, r6 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ asrs r7, r1, #1 │ │ cdp2 4, 1, cr10, cr0, cr2, {4} │ │ - cdp2 7, 1, cr0, cr2, cr5, {3} │ │ + mrc2 7, 0, r0, cr2, cr2, {4} │ │ mrc2 5, 0, r8, cr2, cr13, {0} │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #16 │ │ mov r2, r1 │ │ ldr r1, [pc, #200] @ (2117d28 ) │ │ @@ -231966,15 +231966,15 @@ │ │ ldrb.w r0, [sp, #8] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ - ldmia r2, {r1, r2, r6, r7} │ │ + ldmia r2!, {r0, r1, r4, r5, r6, r7} │ │ vfmsl.f16 , d16, d2[1] │ │ lsls r1, r4, #1 │ │ stmia r0!, {r5} │ │ cdp2 3, 1, cr8, cr2, cr0, {4} │ │ vfmsl.f16 d15, s4, s12[0] │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ @@ -232024,15 +232024,15 @@ │ │ pop {r4, r5, r6, r7, pc} │ │ mov r0, r6 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ add r4, pc, #336 @ (adr r4, 2118044 ) │ │ cdp2 2, 0, cr8, cr15, cr12, {4} │ │ - mrc2 0, 0, ip, cr2, cr4, {0} │ │ + cdp2 0, 1, cr12, cr2, cr1, {2} │ │ cdp2 2, 1, cr8, cr1, cr8, {3} │ │ mrc2 5, 0, fp, cr2, cr0, {5} │ │ add r7, sp, #8 │ │ vpush {d8} │ │ sub sp, #24 │ │ ldr r2, [pc, #104] @ (2117f74 ) │ │ mov r4, r0 │ │ @@ -232070,15 +232070,15 @@ │ │ vpopeq {d8} │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ mov r0, r5 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ - add pc, ip │ │ + cmp r4, r2 │ │ mrc2 7, 0, pc, cr0, cr8, {0} │ │ lsls r1, r4, #1 │ │ @ instruction: 0xf6da0061 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #16 │ │ @@ -232520,24 +232520,24 @@ │ │ bne.n 2118474 │ │ vldr d16, [r0] │ │ ldr r0, [r0, #8] │ │ str r0, [sp, #24] │ │ vstr d16, [sp, #16] │ │ b.n 211847e │ │ nop │ │ - add r0, pc, #980 @ (adr r0, 2118828 ) │ │ + add r1, pc, #136 @ (adr r1, 21184dc ) │ │ @ instruction: 0xfe11396d │ │ - mrc2 15, 0, sp, cr3, cr7, {2} │ │ + cdp2 15, 1, cr13, cr3, cr4, {4} │ │ mrc2 6, 0, r9, cr1, cr10, {5} │ │ cdp2 0, 1, cr0, cr3, cr0, {0} │ │ movs r0, r0 │ │ ldr r2, [r1, r2] │ │ cdp2 6, 1, cr6, cr3, cr6, {3} │ │ subs r7, #102 @ 0x66 │ │ - lsls r2, r7, #7 │ │ + lsls r7, r4, #8 │ │ mrc2 13, 0, pc, cr2, cr1, {3} │ │ muls r7, r7 │ │ ldrd r2, r1, [r0, #4] │ │ add r0, sp, #16 │ │ bl 207d390 │ │ add r0, sp, #32 │ │ add r1, sp, #16 │ │ @@ -232609,23 +232609,23 @@ │ │ nop │ │ movs r0, r0 │ │ movs r0, r0 │ │ @ instruction: 0xf58e0061 │ │ adc.w r0, r4, #97 @ 0x61 │ │ ldrsb r0, [r5, r6] │ │ @ instruction: 0xfe13bb67 │ │ - mrc2 15, 0, r9, cr2, cr10, {1} │ │ - cdp2 15, 1, cr9, cr1, cr1, {1} │ │ + cdp2 15, 1, cr9, cr2, cr7, {3} │ │ + cdp2 15, 1, cr9, cr1, cr14, {2} │ │ mrc2 12, 0, pc, cr1, cr8, {0} │ │ - cdp2 14, 1, cr9, cr2, cr2, {3} │ │ - mrc2 6, 0, r4, cr1, cr12, {4} │ │ - mrc2 3, 0, r8, cr1, cr4, {0} │ │ + cdp2 14, 1, cr9, cr2, cr15, {4} │ │ + cdp2 6, 1, cr4, cr1, cr9, {6} │ │ + cdp2 3, 1, cr8, cr1, cr1, {2} │ │ cdp2 2, 1, cr7, cr1, cr4, {4} │ │ - cdp2 4, 1, cr2, cr3, cr12, {1} │ │ - mrc2 14, 0, r9, cr1, cr0, {2} │ │ + mrc2 4, 0, r2, cr3, cr9, {2} │ │ + mrc2 14, 0, r9, cr1, cr13, {3} │ │ cdp2 2, 1, cr2, cr1, cr8, {0} │ │ mrc2 2, 0, pc, cr2, cr0, {4} │ │ lsls r1, r4, #1 │ │ ldrb r6, [r6, #19] │ │ cdp2 4, 1, cr14, cr2, cr6, {2} │ │ mcr2 5, 0, fp, cr15, cr0, {7} │ │ add r7, sp, #12 │ │ @@ -232657,15 +232657,15 @@ │ │ strb r5, [r0, #4] │ │ str.w r8, [r4, #12] │ │ str r0, [r4, #0] │ │ str r1, [r0, #0] │ │ ldr.w r8, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ - cbnz r6, 21185e2 │ │ + cbnz r3, 21185ee │ │ mrc2 2, 0, pc, cr1, cr6, {3} │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8-d13} │ │ @@ -232894,19 +232894,19 @@ │ │ ldrh r1, [r7, #0] │ │ ldrsh r7, [r4, r6] │ │ subs r6, #124 @ 0x7c │ │ movs r0, r0 │ │ movs r0, r0 │ │ strh r0, [r0, #36] @ 0x24 │ │ asrs r6, r5 │ │ - lsls r2, r7, #5 │ │ + lsls r7, r4, #6 │ │ mrc2 0, 0, pc, cr1, cr6, {1} │ │ lsls r1, r4, #1 │ │ bl 20134b0 │ │ - ldr r2, [sp, #736] @ 0x2e0 │ │ + ldr r2, [sp, #916] @ 0x394 │ │ mrc2 2, 0, sp, cr1, cr10, {6} │ │ cdp2 3, 1, cr3, cr2, cr4, {0} │ │ mrc2 15, 0, r8, cr3, cr6, {2} │ │ mrc2 14, 0, lr, cr3, cr0, {3} │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -232948,19 +232948,19 @@ │ │ addeq sp, #24 │ │ ldreq.w fp, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ mov r0, r6 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ - ittt vs │ │ - mrc2vs 13, 0, lr, cr0, cr8, {3} │ │ - lslvs r1, r4, #1 │ │ - ldcvs 0, cr0, [ip, #-388]! @ 0xfffffe7c │ │ - push {r4, r6, r7, lr} │ │ + iteee hi │ │ + mrc2hi 13, 0, lr, cr0, cr8, {3} │ │ + lslls r1, r4, #1 │ │ + ldcls 0, cr0, [ip, #-388]! @ 0xfffffe7c │ │ + pushls {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ movs r0, #4 │ │ blx 26ffbf0 │ │ ldr r1, [pc, #16] @ (211893c ) │ │ movs r2, #0 │ │ str r2, [r4, #12] │ │ @@ -233186,32 +233186,32 @@ │ │ ldrne r0, [sp, #32] │ │ blxne 26ffb40 │ │ mov r0, r4 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ ldr r0, [r5, #48] @ 0x30 │ │ ldr r6, [pc, #440] @ (2118d34 ) │ │ - adds r0, r4, #6 │ │ + adds r5, r1, #7 │ │ mrc2 12, 0, lr, cr1, cr0, {6} │ │ lsls r1, r4, #1 │ │ str r5, [sp, #352] @ 0x160 │ │ - vselvs.f32 s6, s7, s10 │ │ - cdp2 13, 1, cr1, cr0, cr10, {5} │ │ + mrc2 10, 0, r3, cr3, cr2, {5} @ │ │ + mrc2 13, 0, r1, cr0, cr7, {6} │ │ mrc2 13, 0, r0, cr1, cr3, {5} │ │ mrc2 11, 0, r1, cr3, cr1, {3} @ │ │ - cdp2 7, 1, cr9, cr2, cr13, {1} │ │ + mrc2 7, 0, r9, cr2, cr10, {2} │ │ cdp2 2, 1, cr8, cr1, cr8, {5} │ │ lsls r0, r4, #1 │ │ strh r2, [r1, #20] │ │ lsls r0, r4, #1 │ │ ldmia r7!, {r1, r2, r4, r6} │ │ - cdp2 5, 1, cr13, cr2, cr13, {4} │ │ + mrc2 5, 0, sp, cr2, cr10, {5} │ │ mrc2 10, 0, lr, cr1, cr4, {7} @ │ │ lsls r1, r4, #1 │ │ - ldrsb r7, [r7, r5] │ │ + ldrsb r4, [r5, r6] │ │ mrc2 5, 0, fp, cr1, cr0, {5} │ │ add r7, sp, #8 │ │ vpush {d8} │ │ sub sp, #24 │ │ ldr r2, [pc, #104] @ (2118c28 ) │ │ mov r4, r0 │ │ ldr r0, [pc, #104] @ (2118c2c ) │ │ @@ -233248,15 +233248,15 @@ │ │ vpopeq {d8} │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ mov r0, r5 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ - blt.n 2118cd8 │ │ + blt.n 2118b32 │ │ @ instruction: 0xfe10ea64 │ │ lsls r1, r4, #1 │ │ bic.w r0, r6, r1, asr #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ vpush {d8-d11} │ │ @@ -233554,26 +233554,26 @@ │ │ vcvt.u32.f32 s4, s12 │ │ vcvt.u32.f32 s6, s8 │ │ vmov r3, s0 │ │ vmov r2, s2 │ │ vmov r1, s4 │ │ vmov r0, s6 │ │ b.n 2119038 │ │ - adds r7, #173 @ 0xad │ │ - mrc2 10, 0, r1, cr0, cr12, {7} @ │ │ + adds r7, #218 @ 0xda │ │ + vselvs.f64 d1, d0, d25 │ │ cdp2 0, 1, cr0, cr1, cr0, {0} │ │ movs r0, r0 │ │ cmp r5, #140 @ 0x8c │ │ cdp2 13, 1, cr4, cr3, cr0, {0} │ │ - vselvs.f32 s2, s7, s2 │ │ - cdp2 3, 1, cr13, cr1, cr2, {2} │ │ - cdp2 3, 1, cr13, cr1, cr8, {1} │ │ + vselvs.f32 s2, s7, s29 │ │ + cdp2 3, 1, cr13, cr1, cr15, {3} │ │ + mrc2 3, 0, sp, cr1, cr5, {2} │ │ cdp2 7, 1, cr8, cr1, cr8, {6} │ │ mrc2 3, 0, r9, cr3, cr12, {6} │ │ - mrc2 2, 0, sp, cr3, cr11, {3} │ │ + cdp2 2, 1, cr13, cr3, cr8, {5} │ │ vfmsl.f16 d14, s3, s5[0] │ │ lsls r1, r4, #1 │ │ strh r1, [r0, #4] │ │ subs r3, #128 @ 0x80 │ │ ldc2l 3, cr4, [r1, #-508]! @ 0xfffffe04 │ │ cmp r3, #84 @ 0x54 │ │ vcmla.f16 d9, d3, d8[0], #90 │ │ @@ -233837,17 +233837,17 @@ │ │ vcvt.u32.f32 s6, s8 │ │ vmov r2, s0 │ │ vmov r3, s2 │ │ vmov r1, s4 │ │ vmov r0, s6 │ │ b.n 21193d0 │ │ nop │ │ - asrs r6, r5, #28 │ │ + asrs r3, r3, #29 │ │ cdp2 12, 1, cr10, cr1, cr14, {1} │ │ - mrc2 3, 0, r7, cr2, cr1, {3} │ │ + mrc2 3, 0, r7, cr2, cr14, {4} │ │ vcmla.f16 d9, d1, d8[0], #90 │ │ lsrs r2, r0, #24 │ │ lsrs r3, r0, #16 │ │ lsrs r1, r0, #8 │ │ uxtb r3, r3 │ │ uxtb r1, r1 │ │ lsls r3, r3, #16 │ │ @@ -234106,15 +234106,15 @@ │ │ nop │ │ movs r0, r0 │ │ movs r0, r0 │ │ strh r1, [r0, #4] │ │ subs r3, #128 @ 0x80 │ │ ldc2l 3, cr4, [r1, #-508]! @ 0xfffffe04 │ │ ldrd r0, r0, [ip, #388] @ 0x184 │ │ - ldr r7, [pc, #660] @ (21199a4 ) │ │ + ldr r7, [pc, #840] @ (2119a58 ) │ │ mrc2 15, 0, r4, cr1, cr3, {3} │ │ mrc2 10, 0, r8, cr2, cr0, {0} @ │ │ cdp2 15, 1, cr13, cr2, cr0, {4} │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -234162,15 +234162,15 @@ │ │ mov r0, r4 │ │ blx r1 │ │ blx 26ffb60 │ │ nop │ │ b.n 2119960 │ │ lsls r1, r4, #1 │ │ ldrh r4, [r3, #28] │ │ - cdp2 7, 0, cr10, cr15, cr2, {3} │ │ + cdp2 7, 0, cr10, cr15, cr15, {4} │ │ mrc2 5, 0, fp, cr1, cr0, {6} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ movs r0, #4 │ │ blx 26ffbf0 │ │ ldr r1, [pc, #16] @ (21197bc ) │ │ movs r2, #0 │ │ @@ -234276,15 +234276,15 @@ │ │ eors r6, r4 │ │ cmp r5, #24 │ │ strb r4, [r0, r1] │ │ movs r1, #251 @ 0xfb │ │ ands r1, r1 │ │ movs r0, r0 │ │ movs r0, r0 │ │ - cmp r4, #35 @ 0x23 │ │ + cmp r4, #80 @ 0x50 │ │ mrc2 14, 0, sp, cr0, cr2, {2} │ │ lsls r1, r4, #1 │ │ rors r1, r0 │ │ mrc2 9, 0, r8, cr3, cr6, {0} @ │ │ mcr2 13, 0, sp, cr15, cr0, {4} │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ @@ -234430,19 +234430,19 @@ │ │ ldr r1, [r0, #4] │ │ mov r0, r4 │ │ blx r1 │ │ blx 26ffb60 │ │ nop │ │ bgt.n 21199cc │ │ lsls r1, r4, #1 │ │ - stmia r6!, {r0, r3, r4, r7} │ │ + stmia r6!, {r1, r2, r6, r7} │ │ mrc2 14, 0, sp, cr1, cr6, {4} │ │ lsls r1, r4, #1 │ │ ldrh r0, [r5, #6] │ │ - mcr2 4, 0, sl, cr15, cr6, {5} │ │ + cdp2 4, 0, cr10, cr15, cr3, {7} │ │ mrc2 11, 0, sp, cr1, cr12, {7} @ │ │ lsls r1, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ movs r0, #4 │ │ blx 26ffbf0 │ │ @@ -234553,15 +234553,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #8] │ │ blxne 26ffb40 │ │ mov r0, r5 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ - strh r5, [r0, #54] @ 0x36 │ │ + strh r2, [r6, #54] @ 0x36 │ │ @ instruction: 0xfe11db60 │ │ lsls r1, r4, #1 │ │ ldrb r4, [r2, #27] │ │ mrc2 10, 0, sp, cr3, cr2, {6} @ │ │ lsls r1, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ @@ -234620,15 +234620,15 @@ │ │ addeq sp, #24 │ │ ldreq.w fp, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ mov r0, r6 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ - add r4, sp, #264 @ 0x108 │ │ + add r4, sp, #444 @ 0x1bc │ │ mrc2 10, 0, sp, cr0, cr8, {2} @ │ │ lsls r1, r4, #1 │ │ bge.n 2119c74 │ │ lsls r1, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ @@ -234857,15 +234857,15 @@ │ │ eors r6, r4 │ │ cmp r5, #24 │ │ strb r4, [r0, r1] │ │ movs r1, #251 @ 0xfb │ │ ands r1, r1 │ │ movs r0, r0 │ │ movs r0, r0 │ │ - movs r6, #91 @ 0x5b │ │ + movs r6, #136 @ 0x88 │ │ vcmla.f16 d13, d16, d10[0], #90 │ │ lsls r1, r4, #1 │ │ subs r3, #249 @ 0xf9 │ │ cdp2 3, 1, cr8, cr3, cr14, {2} │ │ cdp2 7, 0, cr13, cr15, cr8, {6} │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ @@ -234928,15 +234928,15 @@ │ │ blx 26ffb50 │ │ mov r0, r5 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ subs r2, #243 @ 0xf3 │ │ cdp2 7, 1, cr13, cr3, cr2, {3} │ │ lsls r1, r4, #1 │ │ - movs r5, #17 │ │ + movs r5, #62 @ 0x3e │ │ mrc2 6, 0, sp, cr0, cr4, {7} │ │ lsls r1, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ movs r0, #4 │ │ blx 26ffbf0 │ │ @@ -235021,17 +235021,17 @@ │ │ add sp, #8 │ │ ldmia.w sp!, {r8, r9, sl} │ │ pop {r4, r5, r6, r7, pc} │ │ mov r0, r4 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ strh r2, [r2, #24] │ │ - mcr2 9, 0, lr, cr15, cr1, {1} @ │ │ - cdp2 14, 1, cr9, cr0, cr14, {6} │ │ - vselvs.f16 s28, s2, s18 │ │ + mcr2 9, 0, lr, cr15, cr14, {2} @ │ │ + mrc2 14, 0, r9, cr0, cr11, {7} │ │ + mrc2 9, 0, lr, cr1, cr6, {1} @ │ │ mrc2 5, 0, fp, cr0, cr0, {7} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ mov r5, r1 │ │ ldr r1, [pc, #112] @ (211a0cc ) │ │ mov r6, r2 │ │ mov r4, r0 │ │ @@ -235074,17 +235074,17 @@ │ │ ldr.w r8, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ mov r0, r6 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ strh r0, [r7, #18] │ │ - vcmla.f16 d14, d31, d10[0], #0 │ │ - mrc2 14, 0, r9, cr0, cr8, {1} │ │ - vcmla.f16 q7, , d6[1], #90 │ │ + vfmal.f16 d14, s31, s15[0] │ │ + cdp2 14, 1, cr9, cr0, cr5, {3} │ │ + vfmsl.f16 d14, s3, s6[0] │ │ mrc2 5, 0, fp, cr0, cr0, {5} │ │ add r7, sp, #8 │ │ mov r5, r0 │ │ ldr r0, [pc, #164] @ (211a188 ) │ │ mov r4, r1 │ │ movs r1, #8 │ │ add r0, pc │ │ @@ -235155,21 +235155,21 @@ │ │ pop {r4, r5, r7, pc} │ │ movs r0, #1 │ │ pop {r4, r5, r7, pc} │ │ movs r0, #0 │ │ pop {r4, r5, r7, pc} │ │ movs r0, #5 │ │ pop {r4, r5, r7, pc} │ │ - b.n 211a61e │ │ + b.n 211a678 │ │ mrc2 4, 0, r5, cr1, cr6, {4} │ │ cdp2 1, 1, cr4, cr3, cr10, {6} │ │ mrc2 13, 0, r7, cr2, cr1, {3} │ │ cdp2 13, 1, cr5, cr2, cr13, {7} │ │ mrc2 15, 0, r7, cr2, cr10, {7} │ │ - mcr2 2, 0, r4, cr15, cr8, {1} │ │ + cdp2 2, 0, cr4, cr15, cr5, {3} │ │ cdp2 1, 1, cr4, cr1, cr5, {4} │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ sub sp, #32 │ │ mov r8, r0 │ │ ldr r0, [pc, #196] @ (211a27c ) │ │ @@ -235620,15 +235620,15 @@ │ │ blx 2701ca0 │ │ add r0, sp, #28 │ │ blx 27048f0 │ │ blx 26ffb60 │ │ nop │ │ bne.n 211a57c │ │ lsls r1, r4, #1 │ │ - cbnz r1, 211a674 │ │ + cbnz r6, 211a67e │ │ cdp2 3, 1, cr13, cr1, cr10, {4} │ │ lsls r1, r4, #1 │ │ bcs.n 211a6d4 │ │ lsls r1, r4, #1 │ │ bne.n 211a6a0 │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ @@ -236383,16 +236383,16 @@ │ │ blx 2701ca0 │ │ add r0, sp, #36 @ 0x24 │ │ blx 27048f0 │ │ blx 26ffb60 │ │ nop │ │ ldmia r2, {r2, r3, r4} │ │ lsls r1, r4, #1 │ │ - cbz r5, 211ae38 │ │ - cdp2 2, 1, cr11, cr1, cr9, {6} │ │ + cbz r2, 211ae44 │ │ + mrc2 2, 0, fp, cr1, cr6, {7} │ │ mrc2 11, 0, ip, cr1, cr10, {7} @ │ │ lsls r1, r4, #1 │ │ ldmia r2, {r1, r2, r3, r4, r5, r7} │ │ lsls r1, r4, #1 │ │ ldmia r1, {r1, r5, r7} │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ @@ -236574,15 +236574,15 @@ │ │ blx 2701ca0 │ │ add r0, sp, #28 │ │ blx 27048f0 │ │ blx 26ffb60 │ │ nop │ │ ldmia r0!, {r3, r5} │ │ lsls r1, r4, #1 │ │ - cbz r1, 211afd4 │ │ + cbz r6, 211afde │ │ vselvs.f32 s24, s2, s20 │ │ lsls r1, r4, #1 │ │ ldmia r0!, {r1, r2, r3, r6, r7} │ │ lsls r1, r4, #1 │ │ stmia r7!, {r1, r4, r5, r7} │ │ lsls r1, r4, #1 │ │ ldr r1, [r2, #0] │ │ @@ -238471,15 +238471,15 @@ │ │ pop {r4, r5, r6, r7, pc} │ │ movs r0, r0 │ │ orrs r4, r6 │ │ lsrs r3, r3, #31 │ │ eors r1, r1 │ │ b.n 211bc1e │ │ mrc2 9, 0, r9, cr1, cr6, {2} @ │ │ - cdp2 2, 1, cr2, cr2, cr14, {6} │ │ + mrc2 2, 0, r2, cr2, cr11, {7} │ │ vselvs.f16 s18, s2, s25 │ │ mrc2 10, 0, ip, cr2, cr8, {7} @ │ │ Address 0x211c236 is out of bounds. │ │ │ │ │ │ 0211c238 , std::__ndk1::allocator >, celestia::MarkerRepresentation, bool)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -238845,15 +238845,15 @@ │ │ mov r0, r5 │ │ blx r1 │ │ add.w r1, r4, #16 │ │ mov r2, r6 │ │ ldr.w fp, [sp], #4 │ │ ldmia.w sp!, {r4, r5, r6, r7, lr} │ │ b.w 26fee1c │ │ - str r0, [r2, #24] │ │ + str r5, [r7, #24] │ │ vfmsl.f16 , d0, d1[2] │ │ Address 0x211c582 is out of bounds. │ │ │ │ │ │ 0211c584 : │ │ ldr r2, [pc, #12] @ (211c594 ) │ │ add r2, pc │ │ @@ -242555,15 +242555,15 @@ │ │ ldrh r4, [r0, #62] @ 0x3e │ │ lsls r1, r4, #1 │ │ blt.n 211e770 │ │ mrc2 14, 0, r8, cr1, cr8, {7} │ │ lsls r1, r4, #1 │ │ ldrh r2, [r1, #52] @ 0x34 │ │ lsls r1, r4, #1 │ │ - ldr r4, [sp, #124] @ 0x7c │ │ + ldr r4, [sp, #304] @ 0x130 │ │ Address 0x211e80a is out of bounds. │ │ │ │ │ │ 0211e80c : │ │ bx lr │ │ │ │ 0211e80e : │ │ @@ -242777,21 +242777,21 @@ │ │ lsls r1, r4, #1 │ │ beq.n 211e9a2 │ │ cdp2 0, 1, cr0, cr2, cr5, {7} │ │ movs r0, r0 │ │ add r6, sp, #160 @ 0xa0 │ │ mrc2 1, 0, r0, cr2, cr3, {5} │ │ movs r0, r0 │ │ - pop {r2, r3, r4, r5, r6, r7, pc} │ │ + bkpt 0x0029 │ │ cdp2 2, 1, cr0, cr0, cr5, {2} │ │ movs r0, r0 │ │ ldr r0, [r6, r6] │ │ mcr2 3, 0, r0, cr15, cr3, {7} │ │ movs r0, r0 │ │ - subs r6, r7, #0 │ │ + subs r3, r5, #1 │ │ cdp2 4, 1, cr0, cr0, cr1, {6} │ │ movs r0, r0 │ │ cbnz r2, 211eab4 │ │ mrc2 5, 0, r0, cr1, cr11, {3} │ │ movs r0, r0 │ │ bhi.n 211e986 │ │ mrc2 6, 0, r0, cr1, cr5, {2} │ │ @@ -242881,15 +242881,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #24] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ ldrh r2, [r0, #30] │ │ lsls r1, r4, #1 │ │ - strb r0, [r2, r1] │ │ + strb r5, [r7, r1] │ │ cdp2 14, 1, cr10, cr1, cr6, {4} │ │ @ instruction: 0xfe13f9e3 │ │ mrc2 11, 0, r8, cr1, cr2, {1} @ │ │ lsls r1, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ @@ -242950,15 +242950,15 @@ │ │ itt eq │ │ addeq sp, #8 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ ldrh r2, [r5, #22] │ │ lsls r1, r4, #1 │ │ - strh r0, [r7, r5] │ │ + strh r5, [r4, r6] │ │ mrc2 13, 0, sl, cr1, cr0, {7} │ │ mrc2 10, 0, r8, cr3, cr8, {3} @ │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ sub sp, #32 │ │ @@ -243120,19 +243120,19 @@ │ │ itt ne │ │ ldrne r0, [sp, #20] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ ldrh r6, [r0, #18] │ │ lsls r1, r4, #1 │ │ - strh r4, [r2, r3] │ │ + strh r1, [r0, r4] │ │ mrc2 13, 0, sl, cr1, cr14, {1} │ │ - mrc2 11, 0, r1, cr3, cr15, {6} @ │ │ - mrc2 11, 0, r1, cr0, cr5, {5} @ │ │ - vselvs.f32 s2, s0, s31 │ │ + cdp2 12, 1, cr1, cr3, cr12, {0} │ │ + @ instruction: 0xfe101be2 │ │ + mrc2 10, 0, r1, cr0, cr12, {2} @ │ │ mrc2 10, 0, r8, cr0, cr12, {0} @ │ │ lsls r1, r4, #1 │ │ ldrh r6, [r7, #6] │ │ lsls r1, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ @@ -243212,20 +243212,20 @@ │ │ cmp r2, r1 │ │ itt eq │ │ addeq sp, #8 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ ldrh r6, [r1, #4] │ │ lsls r1, r4, #1 │ │ - str r4, [r3, r4] │ │ + str r1, [r1, r5] │ │ vselvs.f64 d10, d17, d0 │ │ - mrc2 5, 0, pc, cr3, cr6, {6} │ │ + cdp2 6, 1, cr15, cr3, cr3, {0} │ │ mrc2 9, 0, r8, cr0, cr2, {0} @ │ │ lsls r1, r4, #1 │ │ - bl 1e8fa88 │ │ + bl 1ebca88 │ │ ldrh r2, [r4, #6] │ │ lsls r1, r4, #1 │ │ strh r6, [r5, #62] @ 0x3e │ │ lsls r1, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ @@ -243298,18 +243298,18 @@ │ │ itt eq │ │ addeq sp, #8 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ strh r2, [r6, #60] @ 0x3c │ │ lsls r1, r4, #1 │ │ - str r0, [r0, r1] │ │ + str r5, [r5, r1] │ │ vselvs.f32 s20, s3, s9 │ │ - cdp2 3, 1, cr3, cr3, cr11, {0} │ │ - mrc2 2, 0, r3, cr1, cr7, {5} │ │ + mrc2 3, 0, r3, cr3, cr8, {1} │ │ + cdp2 2, 1, cr3, cr1, cr4, {7} │ │ vfmsl.f16 d8, s2, s13[0] │ │ lsls r1, r4, #1 │ │ strh r4, [r4, #56] @ 0x38 │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -243392,15 +243392,15 @@ │ │ ittt eq │ │ addeq sp, #16 │ │ ldreq.w fp, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ strh r6, [r4, #54] @ 0x36 │ │ lsls r1, r4, #1 │ │ - ldr r7, [pc, #464] @ (211f1e4 (int, FatalErrors, char const*)@@Base+0xc>) │ │ + ldr r7, [pc, #644] @ (211f298 (lua_State*)@@Base+0x50>) │ │ mrc2 9, 0, sl, cr1, cr6, {6} @ │ │ mrc2 9, 0, r8, cr3, cr4, {0} @ │ │ lsls r1, r4, #1 │ │ strh r6, [r6, #48] @ 0x30 │ │ lsls r1, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ @@ -243463,22 +243463,22 @@ │ │ blx 26ffb50 │ │ ldr r1, [pc, #32] @ (211f0cc ) │ │ mov r0, sp │ │ add r1, pc │ │ blx 2704bc0 │ │ strh r2, [r0, #48] @ 0x30 │ │ lsls r1, r4, #1 │ │ - ldr r6, [pc, #576] @ (211f2fc *> >(std::__ndk1::__hash_const_iterator*>, std::__ndk1::__hash_const_iterator*>)@@Base+0x18>) │ │ + ldr r6, [pc, #756] @ (211f3b0 (lua_State*)@@Base+0x34>) │ │ vcmla.f16 q5, , d8[1], #90 │ │ vselvs.f16 s28, s7, s22 │ │ cdp2 6, 1, cr8, cr2, cr6, {4} │ │ lsls r1, r4, #1 │ │ strh r4, [r2, #44] @ 0x2c │ │ lsls r1, r4, #1 │ │ - ldrsb r3, [r5, r5] │ │ + ldrsb r0, [r3, r6] │ │ mrc2 5, 0, fp, cr0, cr0, {5} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r1, r0 │ │ ldr r0, [pc, #120] @ (211f154 ) │ │ mov r5, sp │ │ add r0, pc │ │ @@ -243529,21 +243529,21 @@ │ │ blx 26ffb50 │ │ ldr r1, [pc, #28] @ (211f168 ) │ │ mov r0, sp │ │ add r1, pc │ │ blx 2704bc0 │ │ strh r0, [r2, #42] @ 0x2a │ │ lsls r1, r4, #1 │ │ - ldr r5, [pc, #888] @ (211f4d4 ) │ │ + ldr r6, [pc, #44] @ (211f188 ) │ │ vfmsl.f16 q7, d17, d5[1] │ │ mrc2 5, 0, r8, cr2, cr8, {6} │ │ lsls r1, r4, #1 │ │ strh r6, [r6, #38] @ 0x26 │ │ lsls r1, r4, #1 │ │ - ldrsb r3, [r1, r3] │ │ + ldrsb r0, [r7, r3] │ │ cdp2 5, 1, cr11, cr0, cr0, {4} │ │ mov r7, sp │ │ sub sp, #8 │ │ mov r1, r0 │ │ ldr r0, [pc, #80] @ (211f1c8 ) │ │ add r0, pc │ │ ldr r0, [r0, #0] │ │ @@ -243578,15 +243578,15 @@ │ │ cmp r2, r1 │ │ itt eq │ │ addeq sp, #8 │ │ popeq {r7, pc} │ │ blx 26ffb50 │ │ strh r6, [r6, #36] @ 0x24 │ │ lsls r1, r4, #1 │ │ - ldr r5, [pc, #272] @ (211f2e0 (lua_State*)@@Base+0x98>) │ │ + ldr r5, [pc, #452] @ (211f394 (lua_State*)@@Base+0x18>) │ │ cdp2 7, 1, cr10, cr1, cr10, {6} │ │ mrc2 4, 0, r8, cr3, cr6, {3} │ │ lsls r1, r4, #1 │ │ │ │ 0211f1d8 (int, FatalErrors, char const*)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -244157,15 +244157,15 @@ │ │ blx 2700d00 │ │ movs r0, #0 │ │ add sp, #20 │ │ ldmia.w sp!, {r8, r9, sl, fp} │ │ pop {r4, r5, r6, r7, pc} │ │ strb r1, [r2, #9] │ │ @ instruction: 0xfe0f29e9 │ │ - cdp2 13, 1, cr14, cr2, cr3, {5} │ │ + mrc2 13, 0, lr, cr2, cr0, {6} │ │ cdp2 2, 0, cr7, cr15, cr0, {2} │ │ mcr2 14, 0, sl, cr15, cr0, {5} │ │ Address 0x211f752 is out of bounds. │ │ │ │ │ │ 0211f754 : │ │ push {r4, r6, r7, lr} │ │ @@ -244606,225 +244606,225 @@ │ │ ldr r1, [pc, #576] @ (211fd8c ) │ │ mov r0, r4 │ │ ldr r2, [pc, #576] @ (211fd90 ) │ │ b.w 211fd94 │ │ stmia r2!, {r0, r1, r4, r6, r7} │ │ mrc2 9, 0, r0, cr2, cr13, {6} @ │ │ movs r0, r0 │ │ - asrs r0, r6, #2 │ │ + asrs r5, r3, #3 │ │ @ instruction: 0xfe1009e3 │ │ movs r0, r0 │ │ - ldrh r3, [r4, #28] │ │ + ldrh r0, [r2, #30] │ │ vselvs.f64 d0, d1, d9 │ │ movs r0, r0 │ │ mcr2 14, 2, pc, cr14, cr2, {0} @ │ │ lsrs r3, r0, #17 │ │ movs r0, r0 │ │ add r0, pc, #72 @ (adr r0, 211fbc0 ) │ │ cdp2 13, 1, cr0, cr2, cr13, {1} │ │ movs r0, r0 │ │ - bne.n 211fb30 │ │ + bcs.n 211fb8a │ │ mrc2 13, 0, r0, cr0, cr11, {4} │ │ movs r0, r0 │ │ strb r6, [r4, #6] │ │ cdp2 15, 0, cr0, cr15, cr9, {0} │ │ movs r0, r0 │ │ - ldr r6, [r3, #116] @ 0x74 │ │ + ldr r3, [r1, #120] @ 0x78 │ │ mrc2 15, 0, r0, cr0, cr11, {3} │ │ movs r0, r0 │ │ - ldcl 14, cr15, [sl], {15} │ │ + stc 14, cr15, [r7, #-60] @ 0xffffffc4 │ │ lsrs r5, r6, #30 │ │ movs r0, r0 │ │ lsrs r2, r1, #5 │ │ mrc2 15, 0, r0, cr2, cr11, {7} │ │ movs r0, r0 │ │ - lsrs r7, r6, #24 │ │ + lsrs r4, r4, #25 │ │ cdp2 0, 1, cr1, cr1, cr9, {3} │ │ movs r0, r0 │ │ ldr r7, [sp, #756] @ 0x2f4 │ │ cdp2 1, 1, cr1, cr2, cr3, {7} │ │ movs r0, r0 │ │ ldc2l 14, cr15, [sp, #72] @ 0x48 │ │ asrs r1, r7, #10 │ │ movs r0, r0 │ │ strh r2, [r5, #6] │ │ lsls r1, r4, #1 │ │ - asrs r6, r1, #32 │ │ + asrs r3, r7, #32 │ │ mrc2 0, 0, r8, cr0, cr14, {6} │ │ lsls r1, r4, #1 │ │ - @ instruction: 0xebb3fe10 │ │ + @ instruction: 0xebe0fe10 │ │ strh r2, [r2, #6] │ │ lsls r1, r4, #1 │ │ lsrs r7, r7, #3 │ │ cdp2 0, 1, cr8, cr2, cr6, {6} │ │ lsls r1, r4, #1 │ │ - bne.n 211fc56 │ │ + bne.n 211fcb0 │ │ mrc2 3, 0, r9, cr0, cr0, {5} │ │ mcr2 4, 0, r1, cr15, cr7, {5} │ │ movs r0, r0 │ │ - mov r0, pc │ │ + mov sp, r4 │ │ mrc2 5, 0, r1, cr1, cr5, {0} │ │ movs r0, r0 │ │ cmp r5, fp │ │ cdp2 6, 1, cr1, cr2, cr15, {2} │ │ movs r0, r0 │ │ - ldr r2, [r6, #104] @ 0x68 │ │ + ldr r7, [r3, #108] @ 0x6c │ │ cdp2 7, 1, cr1, cr0, cr13, {4} │ │ movs r0, r0 │ │ - stc 14, cr15, [r9], #-60 @ 0xffffffc4 │ │ + mrrc 14, 0, pc, r6, cr15 @ │ │ adds r7, r1, r3 │ │ movs r0, r0 │ │ cbz r5, 211fc0e │ │ @ instruction: 0xfe0f196d │ │ movs r0, r0 │ │ - ldc 14, cr15, [fp], {15} │ │ + mcrr 14, 0, pc, r8, cr15 @ │ │ subs r3, r4, r5 │ │ movs r0, r0 │ │ strh r7, [r7, #46] @ 0x2e │ │ cdp2 12, 1, cr1, cr2, cr1, {0} │ │ movs r0, r0 │ │ - ldr r7, [pc, #384] @ (211fda0 ) │ │ + ldr r7, [pc, #564] @ (211fe54 ) │ │ cdp2 13, 1, cr1, cr0, cr7, {7} │ │ movs r0, r0 │ │ - ldr r7, [pc, #404] @ (211fdbc ) │ │ + ldr r7, [pc, #584] @ (211fe70 ) │ │ cdp2 15, 1, cr1, cr0, cr13, {0} │ │ movs r0, r0 │ │ movs r7, #243 @ 0xf3 │ │ mrc2 0, 0, r2, cr2, cr3, {1} │ │ movs r0, r0 │ │ ldmia r1, {r0, r1, r3} │ │ mrc2 2, 0, r2, cr1, cr5, {3} │ │ movs r0, r0 │ │ movs r7, #237 @ 0xed │ │ cdp2 4, 1, cr2, cr2, cr7, {6} │ │ movs r0, r0 │ │ - @ instruction: 0xea67fe10 │ │ + @ instruction: 0xea94fe10 │ │ movs r6, #93 @ 0x5d │ │ movs r0, r0 │ │ - add r6, sp, #472 @ 0x1d8 │ │ + add r6, sp, #652 @ 0x28c │ │ vcmla.f16 d2, d16, d15[1], #90 │ │ movs r0, r0 │ │ - @ instruction: 0xea3efe10 │ │ + @ instruction: 0xea6bfe10 │ │ cmp r2, #73 @ 0x49 │ │ movs r0, r0 │ │ - @ instruction: 0xeb9dfe0f │ │ + @ instruction: 0xebcafe0f │ │ cmp r3, #195 @ 0xc3 │ │ movs r0, r0 │ │ lsrs r3, r0, #32 │ │ mrc2 12, 0, r2, cr2, cr13, {2} │ │ movs r0, r0 │ │ - ldr r6, [pc, #1000] @ (2120058 ) │ │ + ldr r7, [pc, #156] @ (211fd0c ) │ │ mrc2 12, 0, r2, cr0, cr7, {7} │ │ movs r0, r0 │ │ - add r6, sp, #244 @ 0xf4 │ │ + add r6, sp, #424 @ 0x1a8 │ │ mrc2 14, 0, r2, cr0, cr5, {6} │ │ movs r0, r0 │ │ add r3, sp │ │ mrc2 15, 0, r2, cr2, cr11, {1} │ │ movs r0, r0 │ │ strh r1, [r1, #42] @ 0x2a │ │ mrc2 0, 0, r3, cr2, cr5, {0} │ │ movs r0, r0 │ │ ldmia r0!, {r5, r7} │ │ mrc2 0, 0, r3, cr1, cr7, {1} │ │ movs r0, r0 │ │ str r2, [sp, #516] @ 0x204 │ │ mcr2 0, 0, r3, cr15, cr9, {4} │ │ movs r0, r0 │ │ - cmp r1, r9 │ │ + cmp r6, lr │ │ mrc2 1, 0, r3, cr1, cr3, {0} │ │ movs r0, r0 │ │ - ldrh r4, [r7, #12] │ │ + ldrh r1, [r5, #14] │ │ mrc2 1, 0, r3, cr1, cr13, {2} │ │ movs r0, r0 │ │ - cmp r0, #35 @ 0x23 │ │ + cmp r0, #80 @ 0x50 │ │ cdp2 1, 1, cr3, cr1, cr7, {5} │ │ movs r0, r0 │ │ ldmia r0, {r0, r1, r3, r4, r7} │ │ mrc2 2, 0, r3, cr1, cr13, {2} │ │ movs r0, r0 │ │ - cmp r4, #234 @ 0xea │ │ + cmp r5, #23 │ │ cdp2 2, 1, cr3, cr0, cr11, {6} │ │ movs r0, r0 │ │ add r2, sp, #904 @ 0x388 │ │ mrc2 3, 0, r3, cr1, cr13, {3} │ │ movs r0, r0 │ │ cmp r0, #227 @ 0xe3 │ │ mcr2 3, 0, r3, cr15, cr7, {7} │ │ movs r0, r0 │ │ - ldr r5, [pc, #980] @ (21200ac ) │ │ + ldr r6, [pc, #136] @ (211fd60 ) │ │ cdp2 4, 1, cr3, cr0, cr9, {7} │ │ movs r0, r0 │ │ - ldr r5, [pc, #952] @ (2120098 ) │ │ + ldr r6, [pc, #108] @ (211fd4c ) │ │ cdp2 5, 1, cr3, cr0, cr15, {2} │ │ movs r0, r0 │ │ stmia r0!, {r1, r3, r4} │ │ cdp2 5, 1, cr3, cr2, cr9, {4} │ │ movs r0, r0 │ │ ldmia r0!, {r1, r2, r6} │ │ cdp2 5, 1, cr3, cr1, cr11, {6} │ │ movs r0, r0 │ │ - add r9, r8 │ │ + add lr, sp │ │ mrc2 6, 0, r3, cr1, cr1, {1} │ │ movs r0, r0 │ │ it │ │ cdp2 6, 1, cr3, cr2, cr15, {3} │ │ movs r0, r0 │ │ movs r6, #157 @ 0x9d │ │ mrc2 7, 0, r3, cr2, cr1, {0} │ │ movs r0, r0 │ │ @ instruction: 0xfb8afe12 │ │ adds r7, #107 @ 0x6b │ │ movs r0, r0 │ │ str r1, [sp, #716] @ 0x2cc │ │ cdp2 7, 0, cr3, cr15, cr9, {5} │ │ movs r0, r0 │ │ - ldmia r1!, {r0, r3, r4, r5, r6} │ │ + ldmia r1, {r1, r2, r5, r7} │ │ cdp2 7, 0, cr3, cr15, cr11, {7} │ │ movs r0, r0 │ │ ldr r0, [pc, #812] @ (2120054 ) │ │ vfmal.f16 , d15, d1[0] │ │ movs r0, r0 │ │ - strd pc, lr, [sl, #-64] @ 0x40 │ │ + ldrd pc, lr, [r7, #-64]! @ 0x40 │ │ subs r0, #175 @ 0xaf │ │ movs r0, r0 │ │ ldrsh r2, [r4, r6] │ │ @ instruction: 0xfe12394d │ │ movs r0, r0 │ │ ldr r5, [sp, #32] │ │ vselvs.f16 s6, s5, s23 │ │ movs r0, r0 │ │ - ldrh r0, [r6, #4] │ │ + ldrh r5, [r3, #6] │ │ @ instruction: 0xfe113a49 │ │ movs r0, r0 │ │ - str r6, [r6, #84] @ 0x54 │ │ + str r3, [r4, #88] @ 0x58 │ │ vselvs.f32 s6, s3, s15 │ │ movs r0, r0 │ │ ldrsh r4, [r7, r5] │ │ mrc2 11, 0, r3, cr2, cr9, {1} @ │ │ movs r0, r0 │ │ ldrsh r3, [r0, r6] │ │ mrc2 11, 0, r3, cr2, cr7, {4} @ │ │ movs r0, r0 │ │ - ldr r5, [pc, #364] @ (211fed4 ) │ │ + ldr r5, [pc, #544] @ (211ff88 ) │ │ mrc2 12, 0, r3, cr0, cr9, {0} │ │ movs r0, r0 │ │ - strd pc, lr, [r5], #64 @ 0x40 │ │ + ldmdb r2, {r4, r9, sl, fp, ip, sp, lr, pc} │ │ subs r4, #155 @ 0x9b │ │ movs r0, r0 │ │ add r6, sp, #668 @ 0x29c │ │ mcr2 13, 0, r3, cr15, cr9, {3} │ │ movs r0, r0 │ │ ldrsh r0, [r4, r5] │ │ cdp2 14, 1, cr3, cr2, cr7, {0} │ │ movs r0, r0 │ │ udf #176 @ 0xb0 │ │ cdp2 15, 1, cr3, cr2, cr13, {0} │ │ movs r0, r0 │ │ - movs r3, #222 @ 0xde │ │ + movs r4, #11 │ │ cdp2 13, 1, cr3, cr1, cr7, {1} │ │ movs r0, r0 │ │ add r1, pc │ │ add r2, pc │ │ blx 2704e00 │ │ ldr r1, [pc, #600] @ (211fff8 ) │ │ mov r0, r4 │ │ @@ -245079,36 +245079,36 @@ │ │ add r2, pc │ │ blx 2704e00 │ │ mov r0, r4 │ │ mvn.w r1, #1 │ │ ldmia.w sp!, {r4, r6, r7, lr} │ │ b.w 26feeac │ │ nop │ │ - ldr r2, [pc, #832] @ (212033c ) │ │ + ldr r2, [pc, #1012] @ (21203f0 ) │ │ mrc2 13, 0, r3, cr0, cr1, {5} │ │ movs r0, r0 │ │ - ldr r2, [r2, #24] │ │ + ldr r7, [r7, #24] │ │ cdp2 15, 1, cr3, cr0, cr11, {1} │ │ movs r0, r0 │ │ pop {r2, r4, r7} │ │ cdp2 0, 1, cr4, cr2, cr9, {3} │ │ movs r0, r0 │ │ - lsrs r1, r6, #9 │ │ + lsrs r6, r3, #10 │ │ cdp2 1, 1, cr4, cr0, cr3, {7} │ │ movs r0, r0 │ │ - add r1, sp, #880 @ 0x370 │ │ + add r2, sp, #36 @ 0x24 │ │ cdp2 3, 1, cr4, cr0, cr1, {1} │ │ movs r0, r0 │ │ add r3, sp, #968 @ 0x3c8 │ │ cdp2 3, 0, cr4, cr15, cr15, {4} │ │ movs r0, r0 │ │ - stmia r6!, {r2, r3, r4} │ │ + stmia r6!, {r0, r3, r6} │ │ mcr2 3, 0, r4, cr15, cr1, {7} │ │ movs r0, r0 │ │ - ldr r2, [pc, #488] @ (212021c ) │ │ + ldr r2, [pc, #668] @ (21202d0 ) │ │ cdp2 4, 1, cr4, cr0, cr7, {2} │ │ movs r0, r0 │ │ movs r2, #253 @ 0xfd │ │ mrc2 4, 0, r4, cr2, cr9, {7} │ │ movs r0, r0 │ │ cmp r0, sl │ │ cdp2 5, 0, cr4, cr15, cr15, {5} │ │ @@ -245118,69 +245118,69 @@ │ │ movs r0, r0 │ │ cmp r5, r7 │ │ mcr2 7, 0, r4, cr15, cr11, {7} │ │ movs r0, r0 │ │ blt.n 211ffd6 │ │ @ instruction: 0xfe124969 │ │ movs r0, r0 │ │ - strh r2, [r7, #40] @ 0x28 │ │ + strh r7, [r4, #42] @ 0x2a │ │ vselvs.f64 d4, d1, d3 │ │ movs r0, r0 │ │ - ldrh r2, [r5, #20] │ │ + ldrh r7, [r2, #22] │ │ @ instruction: 0xfe104b45 │ │ movs r0, r0 │ │ - stmia r5!, {r1, r3, r5, r7} │ │ + stmia r5!, {r0, r1, r2, r4, r6, r7} │ │ mcr2 11, 0, r4, cr15, cr15, {7} @ │ │ movs r0, r0 │ │ - stmia r5!, {r0, r1, r3, r5, r7} │ │ + stmia r5!, {r3, r4, r6, r7} │ │ mcr2 0, 0, r5, cr15, cr9, {0} │ │ movs r0, r0 │ │ cbnz r3, 21200f6 │ │ mrc2 0, 0, r5, cr2, cr15, {1} │ │ movs r0, r0 │ │ blt.n 2120176 │ │ mrc2 0, 0, r5, cr2, cr9, {3} │ │ movs r0, r0 │ │ - ldr r4, [r4, #8] │ │ + ldr r1, [r2, #12] │ │ cdp2 0, 1, cr5, cr0, cr3, {6} │ │ movs r0, r0 │ │ add fp, r9 │ │ cdp2 1, 0, cr5, cr15, cr9, {7} │ │ movs r0, r0 │ │ - b.n 211fce0 │ │ + b.n 211fd3a │ │ cdp2 2, 0, cr5, cr15, cr3, {4} │ │ movs r0, r0 │ │ bge.n 2120014 │ │ mrc2 2, 0, r5, cr2, cr5, {7} │ │ movs r0, r0 │ │ - ands r4, r5 │ │ + eors r1, r3 │ │ mrc2 3, 0, r5, cr1, cr7, {0} │ │ movs r0, r0 │ │ - b.n 211fcc4 │ │ + b.n 211fd1e │ │ mcr2 3, 0, r5, cr15, cr9, {1} │ │ movs r0, r0 │ │ - ldr r0, [pc, #940] @ (2120470 ) │ │ + ldr r1, [pc, #96] @ (2120124 ) │ │ mrc2 3, 0, r5, cr0, cr3, {3} │ │ movs r0, r0 │ │ stmia r3!, {r0} │ │ cdp2 3, 1, cr5, cr1, cr5, {6} │ │ movs r0, r0 │ │ - str r2, [r1, #20] │ │ + str r7, [r6, #20] │ │ cdp2 4, 1, cr5, cr1, cr7, {2} │ │ movs r0, r0 │ │ - movs r7, #136 @ 0x88 │ │ + movs r7, #181 @ 0xb5 │ │ mrc2 5, 0, r5, cr0, cr9, {3} │ │ movs r0, r0 │ │ ldr r6, [r2, #24] │ │ vcmla.f16 d5, d31, d15[0], #0 │ │ movs r0, r0 │ │ ldrh r0, [r4, #36] @ 0x24 │ │ vfmal.f16 , d31, d1[2] │ │ movs r0, r0 │ │ - ldmia r2, {r0, r1, r2, r6} │ │ + ldmia r2, {r2, r4, r5, r6} │ │ vselvs.f64 d5, d16, d7 │ │ movs r0, r0 │ │ stmia r3!, {r2, r5} │ │ cdp2 12, 1, cr5, cr1, cr13, {0} │ │ movs r0, r0 │ │ revsh r7, r7 │ │ mrc2 14, 0, r5, cr2, cr15, {1} │ │ @@ -245193,34 +245193,34 @@ │ │ movs r0, r0 │ │ subs r6, #88 @ 0x58 │ │ cdp2 15, 1, cr5, cr2, cr1, {6} │ │ movs r0, r0 │ │ revsh r3, r2 │ │ mrc2 0, 0, r6, cr2, cr11, {4} │ │ movs r0, r0 │ │ - stmia r4!, {r0, r1, r2, r7} │ │ + stmia r4!, {r2, r4, r5, r7} │ │ cdp2 1, 0, cr6, cr15, cr9, {4} │ │ movs r0, r0 │ │ - b.n 211fbc2 │ │ + b.n 211fc1c │ │ cdp2 2, 0, cr6, cr15, cr15, {3} │ │ movs r0, r0 │ │ b.n 211fae6 │ │ mrc2 3, 0, r6, cr1, cr1, {1} │ │ movs r0, r0 │ │ - lsls r6, r1, #25 │ │ + lsls r3, r7, #25 │ │ mrc2 3, 0, r6, cr1, cr3, {7} │ │ movs r0, r0 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r1, [pc, #8] @ (2120158 ) │ │ add r1, pc │ │ blx 2704bb0 │ │ movs r0, #1 │ │ pop {r7, pc} │ │ - lsls r0, r5, #19 │ │ + lsls r5, r2, #20 │ │ mrc2 5, 0, fp, cr1, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ vpush {d8-d9} │ │ sub sp, #24 │ │ ldr r3, [pc, #268] @ (2120278 ) │ │ mov r6, r0 │ │ @@ -245326,15 +245326,15 @@ │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ ldr r1, [r7, r4] │ │ mrc2 4, 0, r7, cr2, cr6, {5} │ │ lsls r1, r4, #1 │ │ ldr r3, [r4, r2] │ │ cdp2 6, 1, cr9, cr2, cr12, {1} │ │ - cdp2 3, 1, cr14, cr2, cr4, {3} │ │ + mrc2 3, 0, lr, cr2, cr1, {4} │ │ cdp2 3, 0, cr7, cr15, cr10, {7} │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8-d13} │ │ @@ -245441,15 +245441,15 @@ │ │ add sp, #4 │ │ ldmia.w sp!, {r8, r9, sl, fp} │ │ pop {r4, r5, r6, r7, pc} │ │ @ instruction: 0xb7f1 │ │ mrc2 7, 0, r5, cr2, cr13, {3} │ │ mrc2 14, 0, pc, cr2, cr10, {4} │ │ cdp2 6, 1, cr6, cr1, cr10, {4} │ │ - mcr2 5, 0, r4, cr15, cr2, {4} │ │ + mcr2 5, 0, r4, cr15, cr15, {5} │ │ mrc2 2, 0, sl, cr0, cr9, {6} │ │ cdp2 2, 1, cr15, cr1, cr1, {7} │ │ @ instruction: 0xfe127bc2 │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ vpush {d8-d11} │ │ @@ -245526,19 +245526,19 @@ │ │ blx 2700dc0 │ │ movs r0, #0 │ │ add sp, #16 │ │ vpop {d8-d11} │ │ ldmia.w sp!, {r8, r9, sl} │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ - stmia r0!, {r0, r1, r3, r4, r6} │ │ + stmia r0!, {r3, r7} │ │ mcr2 6, 0, r5, cr15, cr3, {1} │ │ mrc2 13, 0, pc, cr2, cr0, {2} │ │ cdp2 5, 1, cr6, cr1, cr0, {2} │ │ - cdp2 4, 0, cr4, cr15, cr10, {2} │ │ + mcr2 4, 0, r4, cr15, cr7, {3} │ │ cdp2 1, 1, cr10, cr0, cr15, {4} │ │ mrc2 5, 0, fp, cr1, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ ldr r3, [pc, #100] @ (2120540 ) │ │ movs r1, #2 │ │ movs r2, #2 │ │ @@ -245576,15 +245576,15 @@ │ │ vcvt.f64.s32 d16, s0 │ │ vmov r2, r3, d16 │ │ blx 2704db0 │ │ movs r0, #1 │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ - movs r2, #0 │ │ + movs r2, #45 @ 0x2d │ │ cdp2 5, 1, cr5, cr0, cr5, {2} │ │ mrc2 5, 0, r5, cr2, cr6, {6} │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #28 │ │ ldr r3, [pc, #352] @ (21206b8 ) │ │ @@ -245779,15 +245779,15 @@ │ │ movs r0, #0 │ │ pop {r4, r5, r7, pc} │ │ ldr r1, [pc, #16] @ (2120744 ) │ │ mov r0, r4 │ │ add r1, pc │ │ blx 2704d80 │ │ nop │ │ - udf #133 @ 0x85 │ │ + udf #178 @ 0xb2 │ │ mcr2 3, 0, sp, cr15, cr2, {0} │ │ cdp2 3, 1, cr5, cr2, cr15, {0} │ │ mrc2 5, 0, fp, cr2, cr0, {6} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #56] @ (2120788 ) │ │ movs r1, #1 │ │ movs r2, #1 │ │ @@ -245888,15 +245888,15 @@ │ │ movle r1, #1 │ │ blx 27012f0 │ │ movs r0, #0 │ │ add sp, #8 │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ - bgt.n 2120880 │ │ + bgt.n 21208da │ │ mrc2 10, 0, fp, cr0, cr7, {4} @ │ │ mrc2 2, 0, r5, cr1, cr7, {0} │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #28 │ │ ldr r3, [pc, #364] @ (21209d8 ) │ │ @@ -246043,15 +246043,15 @@ │ │ mov r0, r5 │ │ movs r1, #2 │ │ blx 2700990 │ │ movs r0, #0 │ │ add sp, #28 │ │ ldmia.w sp!, {r8, r9, sl, fp} │ │ pop {r4, r5, r6, r7, pc} │ │ - stmia r1!, {r1, r2, r4, r5} │ │ + stmia r1!, {r0, r1, r5, r6} │ │ cdp2 1, 1, cr5, cr0, cr15, {5} │ │ mrc2 6, 0, r7, cr2, cr2, {3} │ │ mrc2 1, 0, sp, cr2, cr15, {0} │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ ldr r3, [pc, #204] @ (2120ac0 ) │ │ @@ -246129,15 +246129,15 @@ │ │ blx 2704c90 │ │ mov r0, r4 │ │ mvn.w r1, #2 │ │ blx 2704e50 │ │ movs r0, #1 │ │ ldmia.w sp!, {r8, r9, sl} │ │ pop {r4, r5, r6, r7, pc} │ │ - ldr r5, [sp, #816] @ 0x330 │ │ + ldr r5, [sp, #996] @ 0x3e4 │ │ cdp2 0, 1, cr5, cr0, cr9, {1} │ │ mrc2 15, 0, ip, cr2, cr3, {4} │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #52 @ 0x34 │ │ ldr r3, [pc, #540] @ (2120cf4 ) │ │ @@ -246358,19 +246358,19 @@ │ │ b.n 2120cac │ │ strh r1, [r5, #10] │ │ @ instruction: 0xfe0f6b4a │ │ lsls r1, r4, #1 │ │ ldr r7, [pc, #236] @ (2120dec ) │ │ cdp2 14, 1, cr10, cr2, cr8, {1} │ │ cdp2 14, 1, cr12, cr2, cr1, {7} │ │ - mrc2 9, 0, sp, cr2, cr12, {3} @ │ │ + vselvs.f16 s26, s5, s19 │ │ mcr2 9, 0, r6, cr15, cr12, {2} @ │ │ lsls r1, r4, #1 │ │ ldrh r6, [r4, #24] │ │ - vcmla.f16 d13, d18, d6[1], #90 │ │ + vfmsl.f16 , d18, d3[0] │ │ mcr2 5, 0, fp, cr15, cr0, {6} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #80] @ (2120d70 ) │ │ movs r1, #1 │ │ movs r2, #1 │ │ mov r4, r0 │ │ add r3, pc │ │ @@ -246402,18 +246402,18 @@ │ │ add r3, pc │ │ it eq │ │ moveq r1, r3 │ │ blx 2704bb0 │ │ movs r0, #1 │ │ pop {r4, r6, r7, pc} │ │ nop │ │ - pop {r0, r4, r5, r7} │ │ + pop {r1, r2, r3, r4, r6, r7} │ │ vcmla.f16 q7, q8, d15[1], #90 │ │ mrc2 12, 0, r7, cr2, cr6, {1} │ │ - vcmla.f16 , , d4[0], #0 │ │ + vfmal.f16 , d15, d1[2] │ │ cdp2 13, 1, cr4, cr0, cr1, {0} │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #20 │ │ ldr r3, [pc, #284] @ (2120eac ) │ │ mov r9, r0 │ │ @@ -246531,17 +246531,17 @@ │ │ blx 26ffb60 │ │ nop │ │ strb r3, [r1, #7] │ │ vfmsl.f16 d6, s5, s4[0] │ │ lsls r1, r4, #1 │ │ ldr r4, [pc, #508] @ (21210b4 ) │ │ cdp2 4, 1, cr15, cr2, cr5, {0} │ │ - cdp2 7, 1, cr3, cr1, cr2, {3} │ │ + cdp2 7, 1, cr3, cr1, cr15, {4} │ │ mrc2 11, 0, r7, cr0, cr12, {1} @ │ │ - vseleq.f64 d11, d31, d31 │ │ + mcr2 11, 0, fp, cr15, cr12, {6} @ │ │ cdp2 7, 1, cr6, cr0, cr14, {5} │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #20 │ │ ldr r3, [pc, #308] @ (212100c ) │ │ @@ -246664,17 +246664,17 @@ │ │ b.n 2120f5a │ │ cmp r4, sl │ │ it cc │ │ movcc r8, r9 │ │ ldr.w sl, [sp, #4] │ │ b.n 2120f5a │ │ nop │ │ - ldrb r5, [r1, #9] │ │ + ldrb r2, [r7, #9] │ │ @ instruction: 0xfe104b45 │ │ - mrc2 5, 0, fp, cr2, cr10, {1} │ │ + cdp2 5, 1, cr11, cr2, cr7, {3} │ │ mcr2 5, 0, fp, cr15, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #20 │ │ ldr r3, [pc, #312] @ (212115c ) │ │ movs r1, #1 │ │ mov.w r2, #1000 @ 0x3e8 │ │ @@ -246798,15 +246798,15 @@ │ │ blx 2700990 │ │ movs r0, #0 │ │ add sp, #20 │ │ ldmia.w sp!, {r8, r9, sl, fp} │ │ pop {r4, r5, r6, r7, pc} │ │ cmp r6, #1 │ │ mrc2 9, 0, r4, cr2, cr9, {7} @ │ │ - cdp2 4, 1, cr11, cr2, cr8, {2} │ │ + mrc2 4, 0, fp, cr2, cr5, {3} │ │ mcr2 5, 0, fp, cr15, cr0, {7} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ ldr r3, [pc, #152] @ (212120c ) │ │ movs r1, #1 │ │ movs r2, #1 │ │ mov r4, r0 │ │ @@ -246866,15 +246866,15 @@ │ │ cmp r1, r5 │ │ mov r5, r0 │ │ bne.n 21211f8 │ │ b.n 21211c0 │ │ movs r0, #1 │ │ ldr.w r8, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ - asrs r0, r4, #22 │ │ + asrs r5, r1, #23 │ │ vcmla.f16 d4, d16, d13[1], #90 │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #44 @ 0x2c │ │ ldr r3, [pc, #472] @ (21213f8 ) │ │ mov r8, r0 │ │ @@ -247062,20 +247062,20 @@ │ │ ldr r1, [pc, #32] @ (2121414 ) │ │ add r1, pc │ │ b.n 21213b2 │ │ bcs.n 2121378 │ │ cdp2 4, 1, cr6, cr1, cr2, {0} │ │ lsls r1, r4, #1 │ │ @ instruction: 0x47f3 │ │ - mrc2 3, 0, r5, cr2, cr7, {5} │ │ - cdp2 2, 1, cr13, cr0, cr4, {2} │ │ + cdp2 3, 1, cr5, cr2, cr4, {7} │ │ + mrc2 2, 0, sp, cr0, cr1, {3} │ │ mcr2 2, 0, r6, cr15, cr8, {2} │ │ lsls r1, r4, #1 │ │ - strh r6, [r5, r6] │ │ - vselvs.f64 d2, d0, d17 │ │ + strh r3, [r3, r7] │ │ + @ instruction: 0xfe102b4e │ │ mrc2 5, 0, fp, cr1, cr0, {7} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ ldr r3, [pc, #152] @ (21214bc ) │ │ movs r1, #1 │ │ movs r2, #1 │ │ mov r4, r0 │ │ @@ -247135,15 +247135,15 @@ │ │ cmp r1, r5 │ │ mov r5, r0 │ │ bne.n 21214a8 │ │ b.n 2121470 │ │ movs r0, #1 │ │ ldr.w r8, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ - beq.n 21214e8 │ │ + beq.n 2121542 │ │ mrc2 5, 0, r4, cr0, cr13, {7} │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #44 @ 0x2c │ │ ldr r3, [pc, #456] @ (2121698 ) │ │ mov r8, r0 │ │ @@ -247328,15 +247328,15 @@ │ │ b.n 212165a │ │ nop │ │ stmia r5!, {r2, r3, r4, r7} │ │ mrc2 1, 0, r6, cr2, cr2, {2} │ │ lsls r1, r4, #1 │ │ cmp r3, r8 │ │ cdp2 4, 1, cr12, cr2, cr13, {2} │ │ - mrc2 15, 0, ip, cr2, cr12, {4} │ │ + cdp2 15, 1, cr12, cr2, cr9, {6} │ │ mcr2 15, 0, r5, cr15, cr10, {5} │ │ lsls r1, r4, #1 │ │ stmia r4!, {r1, r2, r3, r6} │ │ cdp2 14, 1, cr12, cr2, cr5, {4} │ │ mrc2 5, 0, fp, cr1, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -247449,15 +247449,15 @@ │ │ addeq sp, #12 │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ lsrs r0, r3, #17 │ │ mcr2 15, 0, r5, cr15, cr14, {2} │ │ lsls r1, r4, #1 │ │ - ldmia r4!, {r0, r6, r7} │ │ + ldmia r4!, {r1, r2, r3, r5, r6, r7} │ │ cdp2 14, 1, cr5, cr0, cr12, {3} │ │ lsls r1, r4, #1 │ │ muls r1, r5 │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #12 │ │ @@ -247569,15 +247569,15 @@ │ │ addeq sp, #12 │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ udf #93 @ 0x5d │ │ cdp2 14, 1, cr5, cr2, cr10, {1} │ │ lsls r1, r4, #1 │ │ - add r4, sp, #48 @ 0x30 │ │ + add r4, sp, #228 @ 0xe4 │ │ mcr2 13, 0, r5, cr15, cr8, {1} │ │ lsls r1, r4, #1 │ │ add r2, pc, #128 @ (adr r2, 21219a0 ) │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ @@ -247768,21 +247768,21 @@ │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ ldc2l 3, cr4, [r1, #-508]! @ 0xfffffe04 │ │ movs r0, r0 │ │ movs r0, r0 │ │ - lsrs r0, r0, #3 │ │ + lsrs r5, r5, #3 │ │ mrc2 12, 0, r5, cr1, cr0, {7} │ │ lsls r1, r4, #1 │ │ - add r3, sp, #776 @ 0x308 │ │ + add r3, sp, #956 @ 0x3bc │ │ mcr2 7, 0, r0, cr15, cr2, {4} │ │ - cdp2 5, 1, cr2, cr2, cr6, {6} │ │ - cdp2 15, 1, cr10, cr1, cr13, {0} │ │ + mrc2 5, 0, r2, cr2, cr3, {7} │ │ + mrc2 15, 0, sl, cr1, cr10, {1} │ │ cdp2 14, 1, cr4, cr0, cr11, {4} │ │ vseleq.f64 d5, d15, d6 │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #36 @ 0x24 │ │ @@ -247994,17 +247994,17 @@ │ │ nop │ │ ldc2l 3, cr4, [r1, #-508]! @ 0xfffffe04 │ │ movs r0, r0 │ │ movs r0, r0 │ │ ldrh r2, [r1, #52] @ 0x34 │ │ vseleq.f32 s10, s31, s13 │ │ lsls r1, r4, #1 │ │ - str r2, [r1, #124] @ 0x7c │ │ + str r7, [r6, #124] @ 0x7c │ │ mrc2 13, 0, r3, cr1, cr6, {5} │ │ - mrc2 9, 0, ip, cr2, cr5, {2} @ │ │ + vselvs.f16 s24, s5, s4 │ │ vfmal.f16 d5, s31, s0[1] │ │ lsls r1, r4, #1 │ │ subs r6, #119 @ 0x77 │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ @@ -248158,15 +248158,15 @@ │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ strh r1, [r0, #4] │ │ subs r3, #128 @ 0x80 │ │ ldr r4, [pc, #40] @ (2121f88 ) │ │ vcmla.f16 , , d0[0], #0 │ │ lsls r1, r4, #1 │ │ - cmp r2, #194 @ 0xc2 │ │ + cmp r2, #239 @ 0xef │ │ vselvs.f64 d3, d0, d10 │ │ mrc2 6, 0, r5, cr2, cr2, {7} │ │ lsls r1, r4, #1 │ │ subs r4, #23 │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -248381,15 +248381,15 @@ │ │ movs r0, r0 │ │ movs r0, r0 │ │ lsls r1, r3, #15 │ │ cdp2 6, 0, cr5, cr15, cr2, {5} │ │ lsls r1, r4, #1 │ │ bvs.n 2122140 │ │ cdp2 13, 1, cr1, cr2, cr5, {2} │ │ - vfmsl.f16 q1, d2, d6[1] │ │ + vcmla.f16 d2, d18, d11[0], #90 │ │ mrc2 4, 0, r5, cr0, cr4, {4} │ │ lsls r1, r4, #1 │ │ subs r2, #115 @ 0x73 │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ @@ -248542,15 +248542,15 @@ │ │ addeq sp, #4 │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ it eq │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ strh r1, [r0, #4] │ │ subs r3, #128 @ 0x80 │ │ - b.n 212201c │ │ + b.n 2122076 │ │ mcr2 4, 0, r5, cr15, cr12, {1} │ │ lsls r1, r4, #1 │ │ vacge.f16 d31, d5, d1 │ │ subs r5, r2, r2 │ │ cdp2 2, 1, cr5, cr2, cr10, {7} │ │ lsls r1, r4, #1 │ │ subs r0, #19 │ │ @@ -248737,15 +248737,15 @@ │ │ blx 2704db0 │ │ movs r0, #3 │ │ vpop {d8} │ │ pop {r4, r5, r7, pc} │ │ nop │ │ strh r1, [r0, #4] │ │ subs r3, #128 @ 0x80 │ │ - ldrsh r0, [r1, r3] │ │ + ldrsh r5, [r6, r3] │ │ mrc2 5, 0, r3, cr1, cr1, {0} │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ ldr r3, [pc, #148] @ (212264c ) │ │ movs r1, #1 │ │ movs r2, #1 │ │ @@ -248991,24 +248991,24 @@ │ │ ldr r1, [pc, #36] @ (2122838 ) │ │ add r1, pc │ │ b.n 21227e6 │ │ ldr r1, [pc, #32] @ (212283c ) │ │ add r1, pc │ │ b.n 21227e6 │ │ nop │ │ - @ instruction: 0xfbd7fe10 │ │ + stc2 14, cr15, [r4], {16} │ │ ldr r7, [pc, #776] @ (2122b30 ) │ │ lsls r1, r4, #1 │ │ adds r3, #179 @ 0xb3 │ │ mrc2 10, 0, sp, cr2, cr0, {1} @ │ │ - mrc2 14, 0, fp, cr1, cr0, {0} │ │ + mrc2 14, 0, fp, cr1, cr13, {1} │ │ mcr2 14, 0, r4, cr15, cr2, {1} │ │ lsls r1, r4, #1 │ │ - subs r0, #89 @ 0x59 │ │ - cdp2 1, 1, cr2, cr1, cr11, {0} │ │ + subs r0, #134 @ 0x86 │ │ + mrc2 1, 0, r2, cr1, cr8, {1} │ │ mrc2 5, 0, fp, cr0, cr0, {5} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #100] @ (21228ac ) │ │ movs r1, #1 │ │ movs r2, #1 │ │ mov r4, r0 │ │ add r3, pc │ │ @@ -249120,15 +249120,15 @@ │ │ blx 27008a0 │ │ mov r0, r4 │ │ blx 2700320 │ │ movs r0, #0 │ │ add sp, #8 │ │ vpop {d8-d9} │ │ pop {r4, r5, r7, pc} │ │ - ldrb r2, [r6, #28] │ │ + ldrb r7, [r3, #29] │ │ mrc2 1, 0, r3, cr0, cr15, {2} │ │ mrc2 9, 0, r9, cr2, cr12, {6} @ │ │ mrc2 5, 0, fp, cr1, cr0, {6} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #36] @ (21229c8 ) │ │ movs r1, #1 │ │ movs r2, #1 │ │ @@ -249139,15 +249139,15 @@ │ │ vmov s0, r0 │ │ mov r0, r4 │ │ vcvt.f64.f32 d16, s0 │ │ vmov r2, r3, d16 │ │ blx 2704db0 │ │ movs r0, #1 │ │ pop {r4, r6, r7, pc} │ │ - ldrh r4, [r6, r0] │ │ + ldrh r1, [r4, r1] │ │ mrc2 5, 0, fp, cr1, cr0, {6} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ ldr r3, [pc, #96] @ (2122a34 ) │ │ movs r1, #2 │ │ movs r2, #2 │ │ mov r4, r0 │ │ @@ -249177,15 +249177,15 @@ │ │ blx 27049d0 │ │ movs r0, #0 │ │ add sp, #8 │ │ pop {r4, r6, r7, pc} │ │ nop │ │ movs r0, r0 │ │ movs r0, r0 │ │ - subs r5, r2, #6 │ │ + subs r2, r0, #7 │ │ cdp2 14, 1, cr6, cr0, cr10, {3} │ │ mrc2 5, 0, fp, cr2, cr0, {5} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ ldr r3, [pc, #116] @ (2122ab8 ) │ │ movs r1, #2 │ │ movs r2, #2 │ │ @@ -249227,17 +249227,17 @@ │ │ mov r1, r4 │ │ blx 2704e70 │ │ movs r0, #0 │ │ add sp, #8 │ │ pop {r4, r5, r7, pc} │ │ movs r0, r0 │ │ movs r0, r0 │ │ - udf #46 @ 0x2e │ │ + udf #91 @ 0x5b │ │ mcr2 15, 0, r2, cr15, cr11, {6} │ │ - cdp2 5, 1, cr1, cr2, cr4, {1} │ │ + mrc2 5, 0, r1, cr2, cr1, {2} │ │ mrc2 5, 0, fp, cr1, cr0, {6} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #72] @ (2122b14 ) │ │ movs r1, #1 │ │ movs r2, #1 │ │ mov r4, r0 │ │ add r3, pc │ │ @@ -249261,15 +249261,15 @@ │ │ mov r0, r4 │ │ vcvt.f64.f32 d16, s0 │ │ vmov r2, r3, d16 │ │ blx 2704db0 │ │ movs r0, #1 │ │ pop {r4, r6, r7, pc} │ │ nop │ │ - cbnz r1, 2122b4e │ │ + rev r6, r0 │ │ mrc2 15, 0, r2, cr0, cr5, {2} │ │ mrc2 5, 0, fp, cr2, cr0, {6} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #72] @ (2122b6c ) │ │ movs r1, #1 │ │ movs r2, #1 │ │ mov r4, r0 │ │ @@ -249296,15 +249296,15 @@ │ │ blx 2704e90 │ │ movs r0, #1 │ │ pop {r4, r6, r7, pc} │ │ mov r0, r4 │ │ blx 2704c50 │ │ movs r0, #1 │ │ pop {r4, r6, r7, pc} │ │ - ldr r4, [r5, r3] │ │ + ldr r1, [r3, r4] │ │ mrc2 14, 0, r2, cr1, cr13, {7} │ │ mrc2 5, 0, fp, cr2, cr0, {5} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ ldr r3, [pc, #172] @ (2122c28 ) │ │ mov r4, r0 │ │ ldr r0, [pc, #172] @ (2122c2c ) │ │ @@ -249501,15 +249501,15 @@ │ │ ldr r2, [r2, #0] │ │ cmp r2, r1 │ │ ittt eq │ │ addeq sp, #16 │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ - cbnz r3, 2122d78 │ │ + cbnz r0, 2122d84 │ │ @ instruction: 0xfe0f4962 │ │ lsls r1, r4, #1 │ │ strh r2, [r2, r2] │ │ vcmla.f16 q2, q9, d2[1], #90 │ │ lsls r1, r4, #1 │ │ cmp r5, #73 @ 0x49 │ │ mrc2 5, 0, fp, cr2, cr0, {5} │ │ @@ -249560,15 +249560,15 @@ │ │ ldr r1, [r1, #0] │ │ cmp r1, r0 │ │ ittt eq │ │ moveq r0, #0 │ │ addeq sp, #16 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ - adds r5, r4, #0 │ │ + adds r2, r2, #1 │ │ vcmla.f16 d4, d16, d6[1], #90 │ │ lsls r1, r4, #1 │ │ ldr r0, [pc, #336] @ (2122f48 ) │ │ lsls r1, r4, #1 │ │ cmp r4, #151 @ 0x97 │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ @@ -249658,15 +249658,15 @@ │ │ ldrb.w r0, [sp, #24] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #32] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ - adds r2, #167 @ 0xa7 │ │ + adds r2, #212 @ 0xd4 │ │ vfmsl.f16 d4, s2, s4[1] │ │ lsls r1, r4, #1 │ │ ldr r0, [pc, #120] @ (2122f68 ) │ │ lsls r1, r4, #1 │ │ cmp r4, #185 @ 0xb9 │ │ mrc2 7, 0, r4, cr2, cr4, {3} │ │ lsls r1, r4, #1 │ │ @@ -249770,15 +249770,15 @@ │ │ mov r2, r0 │ │ mov r0, r4 │ │ mov r3, r1 │ │ blx 2704db0 │ │ movs r0, #1 │ │ pop {r4, r6, r7, pc} │ │ nop │ │ - strb r1, [r0, r2] │ │ + strb r6, [r5, r2] │ │ @ instruction: 0xfe112a61 │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #8 │ │ ldr r3, [pc, #92] @ (2123070 ) │ │ movs r1, #2 │ │ @@ -249815,15 +249815,15 @@ │ │ mov r2, r4 │ │ mov r3, r6 │ │ blx 26fff10 │ │ movs r0, #0 │ │ add sp, #8 │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ - bl 2054c92 │ │ + bl 2081c92 │ │ cmp r2, #11 │ │ cdp2 15, 1, cr4, cr2, cr14, {3} │ │ mrc2 5, 0, fp, cr2, cr0, {6} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #60] @ (21230c0 ) │ │ movs r1, #1 │ │ movs r2, #1 │ │ @@ -249846,15 +249846,15 @@ │ │ blx 2700da0 │ │ blx 2700110 │ │ mov r1, r0 │ │ mov r0, r4 │ │ blx 2704c90 │ │ movs r0, #1 │ │ pop {r4, r6, r7, pc} │ │ - adds r3, r1, r5 │ │ + adds r0, r7, r5 │ │ mrc2 9, 0, r2, cr0, cr13, {4} @ │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ ldr r3, [pc, #152] @ (212316c ) │ │ movs r1, #1 │ │ movs r2, #2 │ │ @@ -249912,15 +249912,15 @@ │ │ mov r0, r4 │ │ add r1, pc │ │ blx 2704d80 │ │ movs r0, #0 │ │ ldr.w r8, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ - str r4, [sp, #592] @ 0x250 │ │ + str r4, [sp, #772] @ 0x304 │ │ @ instruction: 0xfe0f294d │ │ cdp2 1, 1, cr13, cr2, cr3, {1} │ │ mrc2 5, 0, fp, cr1, cr0, {5} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ ldr r3, [pc, #84] @ (21231d4 ) │ │ movs r1, #2 │ │ @@ -249986,15 +249986,15 @@ │ │ blx 2700da0 │ │ blx 2704f00 │ │ mov r1, r0 │ │ mov r0, r4 │ │ blx 2704c90 │ │ movs r0, #1 │ │ pop {r4, r6, r7, pc} │ │ - adds r2, r3, r0 │ │ + adds r7, r0, r1 │ │ vfmsl.f16 d2, s0, s3[1] │ │ mrc2 5, 0, fp, cr2, cr0, {6} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #64] @ (2123274 ) │ │ movs r1, #1 │ │ movs r2, #1 │ │ mov r4, r0 │ │ @@ -250018,15 +250018,15 @@ │ │ mov r2, r0 │ │ mov r0, r4 │ │ mov r3, r1 │ │ blx 2704db0 │ │ movs r0, #1 │ │ pop {r4, r6, r7, pc} │ │ nop │ │ - adds r3, r1, r0 │ │ + adds r0, r7, r0 │ │ cdp2 7, 1, cr2, cr0, cr13, {7} │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #8 │ │ ldr r3, [pc, #92] @ (21232e4 ) │ │ movs r1, #2 │ │ @@ -250065,15 +250065,15 @@ │ │ blx 27006b0 │ │ movs r0, #0 │ │ add sp, #8 │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ ldrh r6, [r4, #8] │ │ mrc2 7, 0, r2, cr2, cr7, {4} │ │ - mrc2 7, 0, r1, cr2, cr12, {5} │ │ + cdp2 7, 1, cr1, cr2, cr9, {7} │ │ mrc2 5, 0, fp, cr0, cr0, {6} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #88] @ (2123350 ) │ │ movs r1, #1 │ │ movs r2, #1 │ │ mov r4, r0 │ │ add r3, pc │ │ @@ -250104,16 +250104,16 @@ │ │ ldr r1, [pc, #16] @ (2123354 ) │ │ mov r0, r4 │ │ add r1, pc │ │ blx 2704d80 │ │ movs r0, #0 │ │ pop {r4, r6, r7, pc} │ │ nop │ │ - str r3, [r7, r5] │ │ - cdp2 3, 1, cr11, cr1, cr8, {0} │ │ + str r0, [r5, r6] │ │ + mrc2 3, 0, fp, cr1, cr5, {1} │ │ cdp2 7, 0, cr2, cr15, cr9, {1} │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #8 │ │ ldr r3, [pc, #148] @ (21233fc ) │ │ movs r1, #2 │ │ @@ -250208,15 +250208,15 @@ │ │ mov r0, r4 │ │ add r1, pc │ │ blx 2704d80 │ │ movs r0, #0 │ │ pop {r4, r6, r7, pc} │ │ nop │ │ lsrs r3, r0, #31 │ │ - mcr2 1, 0, fp, cr15, cr0, {7} │ │ + mcr2 2, 0, fp, cr15, cr13, {0} │ │ mcr2 6, 0, r2, cr15, cr1, {0} │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #8 │ │ ldr r3, [pc, #148] @ (2123514 ) │ │ movs r1, #2 │ │ @@ -250310,15 +250310,15 @@ │ │ mov r0, r4 │ │ add r1, pc │ │ blx 2704d80 │ │ movs r0, #0 │ │ pop {r4, r6, r7, pc} │ │ nop │ │ add r6, pc, #148 @ (adr r6, 2123618 ) │ │ - mrc2 0, 0, fp, cr2, cr8, {6} │ │ + cdp2 1, 1, cr11, cr2, cr5, {0} │ │ mcr2 4, 0, r2, cr15, cr9, {7} │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #8 │ │ ldr r3, [pc, #132] @ (212361c ) │ │ movs r1, #2 │ │ @@ -250369,16 +250369,16 @@ │ │ blx 2704d80 │ │ movs r0, #0 │ │ add sp, #8 │ │ ldr.w r8, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ movs r5, #245 @ 0xf5 │ │ cdp2 4, 1, cr2, cr2, cr7, {4} │ │ - cdp2 2, 1, cr13, cr2, cr1, {7} │ │ - cdp2 0, 0, cr11, cr15, cr0, {2} │ │ + cdp2 3, 1, cr13, cr2, cr14, {0} │ │ + cdp2 0, 0, cr11, cr15, cr13, {3} │ │ mcr2 5, 0, fp, cr15, cr0, {6} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #88] @ (212368c ) │ │ movs r1, #1 │ │ movs r2, #1 │ │ mov r4, r0 │ │ add r3, pc │ │ @@ -250409,16 +250409,16 @@ │ │ ldr r1, [pc, #16] @ (2123690 ) │ │ mov r0, r4 │ │ add r1, pc │ │ blx 2704d80 │ │ movs r0, #0 │ │ pop {r4, r6, r7, pc} │ │ nop │ │ - bl 226a2ae │ │ - add r7, sp, #816 @ 0x330 │ │ + bl 22972ae │ │ + add r7, sp, #996 @ 0x3e4 │ │ cdp2 3, 0, cr2, cr15, cr13, {7} │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #8 │ │ ldr r3, [pc, #116] @ (2123718 ) │ │ movs r1, #2 │ │ @@ -250465,16 +250465,16 @@ │ │ movs r0, #0 │ │ add sp, #8 │ │ ldr.w r8, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ add r4, pc, #864 @ (adr r4, 2123a7c ) │ │ mrc2 3, 0, r2, cr2, cr11, {3} │ │ - cdp2 15, 1, cr12, cr2, cr7, {3} │ │ - cdp2 15, 1, cr10, cr0, cr6, {2} │ │ + mrc2 15, 0, ip, cr2, cr4, {4} │ │ + mrc2 15, 0, sl, cr0, cr3, {3} │ │ mcr2 5, 0, fp, cr15, cr0, {6} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #108] @ (212379c ) │ │ movs r1, #1 │ │ movs r2, #1 │ │ mov r4, r0 │ │ add r3, pc │ │ @@ -250518,19 +250518,19 @@ │ │ ldr r1, [pc, #32] @ (21237b0 ) │ │ add r1, pc │ │ mov r0, r4 │ │ blx 2704bb0 │ │ movs r0, #1 │ │ pop {r4, r6, r7, pc} │ │ nop │ │ - asrs r3, r7, #13 │ │ - mrc2 14, 0, sl, cr0, cr6, {6} │ │ - mcr2 1, 0, r5, cr15, cr0, {6} │ │ - cdp2 14, 1, cr8, cr0, cr2, {1} │ │ - cdp2 14, 0, cr10, cr15, cr9, {7} │ │ + asrs r0, r5, #14 │ │ + cdp2 15, 1, cr10, cr0, cr3, {0} │ │ + mcr2 1, 0, r5, cr15, cr13, {7} │ │ + cdp2 14, 1, cr8, cr0, cr15, {2} │ │ + mcr2 15, 0, sl, cr15, cr6, {0} │ │ vseleq.f64 d12, d15, d17 │ │ mrc2 2, 0, r2, cr1, cr1, {7} │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ ldr r3, [pc, #196] @ (2123888 ) │ │ movs r1, #2 │ │ @@ -250608,20 +250608,20 @@ │ │ mov r0, r8 │ │ movs r1, #0 │ │ blx 2700710 │ │ b.n 2123866 │ │ movs r1, #2 │ │ blx 2700710 │ │ b.n 2123866 │ │ - ldmia r6!, {r1, r2, r4, r5, r7} │ │ + ldmia r6, {r0, r1, r5, r6, r7} │ │ mrc2 2, 0, r2, cr0, cr9, {2} │ │ - mrc2 0, 0, r7, cr2, cr4, {1} │ │ - cdp2 14, 1, cr10, cr0, cr6, {0} │ │ - mcr2 1, 0, r5, cr15, cr12, {0} │ │ - mrc2 13, 0, r8, cr0, cr4, {3} │ │ + cdp2 0, 1, cr7, cr2, cr1, {3} │ │ + mrc2 14, 0, sl, cr0, cr3, {1} │ │ + cdp2 1, 0, cr5, cr15, cr9, {2} │ │ + cdp2 13, 1, cr8, cr0, cr1, {5} │ │ mcr2 5, 0, r0, cr15, cr15, {7} │ │ mrc2 5, 0, fp, cr2, cr0, {6} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #116] @ (2123920 ) │ │ movs r1, #1 │ │ movs r2, #1 │ │ mov r4, r0 │ │ @@ -250669,17 +250669,17 @@ │ │ ldr r1, [pc, #36] @ (2123938 ) │ │ add r1, pc │ │ mov r0, r4 │ │ blx 2704bb0 │ │ movs r0, #1 │ │ pop {r4, r6, r7, pc} │ │ nop │ │ - ldr r3, [pc, #972] @ (2123cf0 ) │ │ - mrc2 13, 0, sl, cr1, cr8, {2} │ │ - mcr2 15, 0, ip, cr15, cr11, {7} │ │ + ldr r4, [pc, #128] @ (21239a4 ) │ │ + cdp2 13, 1, cr10, cr1, cr5, {4} │ │ + cdp2 0, 0, cr13, cr15, cr8, {1} │ │ mcr2 15, 0, r5, cr15, cr1, {5} │ │ mrc2 13, 0, r6, cr2, cr9, {2} │ │ cdp2 5, 1, cr0, cr1, cr11, {3} │ │ mrc2 13, 0, r6, cr2, cr0, {2} │ │ mrc2 1, 0, r2, cr1, cr5, {3} │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ @@ -250777,18 +250777,18 @@ │ │ mov r0, r8 │ │ movs r1, #2 │ │ blx 2700820 │ │ b.n 2123a0a │ │ nop │ │ pop {r0, r1, r7, pc} │ │ mrc2 0, 0, r2, cr2, cr1, {6} │ │ - mrc2 1, 0, r1, cr2, cr9, {2} │ │ - cdp2 12, 1, cr10, cr0, cr8, {4} │ │ + cdp2 1, 1, cr1, cr2, cr6, {4} │ │ + mrc2 12, 0, sl, cr0, cr5, {5} │ │ cdp2 15, 0, cr5, cr15, cr15, {0} │ │ - mrc2 14, 0, ip, cr2, cr13, {7} │ │ + cdp2 15, 1, cr12, cr2, cr10, {1} │ │ cdp2 12, 0, cr6, cr15, cr1, {3} │ │ mrc2 4, 0, r0, cr1, cr15, {4} │ │ mrc2 2, 0, r8, cr2, cr5, {0} │ │ mrc2 5, 0, fp, cr2, cr0, {6} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #88] @ (2123ab4 ) │ │ movs r1, #1 │ │ @@ -250823,15 +250823,15 @@ │ │ mov r0, r4 │ │ add r1, pc │ │ blx 2704d80 │ │ movs r0, #0 │ │ pop {r4, r6, r7, pc} │ │ nop │ │ ldr r4, [r2, #64] @ 0x40 │ │ - vselvs.f64 d10, d17, d20 │ │ + mrc2 11, 0, sl, cr1, cr1, {6} @ │ │ cdp2 15, 0, cr1, cr15, cr5, {6} │ │ mrc2 5, 0, fp, cr2, cr0, {7} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #8 │ │ ldr r3, [pc, #124] @ (2123b48 ) │ │ movs r1, #2 │ │ @@ -250882,15 +250882,15 @@ │ │ add sp, #8 │ │ ldr.w r8, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ b.n 21238c8 │ │ mrc2 15, 0, r1, cr1, cr3, {2} │ │ mrc2 3, 0, r0, cr2, cr9, {3} │ │ - mrc2 11, 0, sl, cr2, cr6, {0} @ │ │ + @ instruction: 0xfe12ab43 │ │ mcr2 5, 0, fp, cr15, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8-d10} │ │ sub sp, #64 @ 0x40 │ │ ldr r3, [pc, #332] @ (2123cb8 ) │ │ @@ -251014,23 +251014,23 @@ │ │ blx 26ffb50 │ │ ldrb.w r0, [sp, #36] @ 0x24 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #44] @ 0x2c │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ - cmp r4, #111 @ 0x6f │ │ + cmp r4, #156 @ 0x9c │ │ mrc2 10, 0, r3, cr0, cr8, {5} @ │ │ lsls r1, r4, #1 │ │ subs r1, r5, #2 │ │ mrc2 14, 0, r2, cr2, cr5, {5} │ │ @ instruction: 0xfe0f6aee │ │ mrc2 0, 0, r8, cr1, cr3, {2} │ │ cdp2 6, 1, cr12, cr2, cr5, {6} │ │ - mrc2 9, 0, r8, cr1, cr0, {5} @ │ │ + mrc2 9, 0, r8, cr1, cr13, {6} @ │ │ mcr2 14, 0, r6, cr15, cr11, {0} │ │ vseleq.f16 s6, s31, s13 │ │ lsls r1, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #64 @ 0x40 │ │ ldr r3, [pc, #280] @ (2123e00 ) │ │ @@ -251144,15 +251144,15 @@ │ │ adds r3, r5, #4 │ │ cdp2 1, 1, cr0, cr2, cr14, {4} │ │ mrc2 1, 0, r0, cr2, cr11, {4} │ │ mrc2 9, 0, fp, cr2, cr12, {4} @ │ │ mrc2 14, 0, r9, cr2, cr13, {1} │ │ mrc2 6, 0, r0, cr2, cr8, {3} │ │ @ instruction: 0xfe0fb960 │ │ - cdp2 7, 1, cr2, cr2, cr2, {5} │ │ + cdp2 7, 1, cr2, cr2, cr15, {6} │ │ vfmsl.f16 , d0, d4[0] │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8-d10} │ │ @@ -251278,22 +251278,22 @@ │ │ blx 26ffb50 │ │ ldrb.w r0, [sp, #36] @ 0x24 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #44] @ 0x2c │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ - lsls r4, r2, #6 │ │ + lsls r1, r0, #7 │ │ cdp2 7, 1, cr3, cr1, cr4, {7} │ │ lsls r1, r4, #1 │ │ subs r5, r2, r7 │ │ - mrc2 7, 0, sl, cr2, cr10, {7} │ │ - cdp2 6, 0, cr4, cr15, cr1, {2} │ │ - @ instruction: 0xfe11296e │ │ - mrc2 7, 0, ip, cr0, cr13, {6} │ │ + vcmla.f16 d10, d2, d7[1], #90 │ │ + cdp2 6, 0, cr4, cr15, cr14, {3} │ │ + mrc2 9, 0, r2, cr1, cr11, {4} @ │ │ + vcmla.f16 d12, d0, d10[0], #90 │ │ vselvs.f64 d6, d16, d22 │ │ cdp2 0, 0, cr4, cr15, cr13, {7} │ │ mrc2 6, 0, r3, cr2, cr2, {6} │ │ lsls r1, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #64 @ 0x40 │ │ @@ -251408,15 +251408,15 @@ │ │ subs r7, r2, r1 │ │ mrc2 10, 0, r2, cr2, cr4, {4} @ │ │ cdp2 14, 0, cr15, cr15, cr7, {6} │ │ cdp2 6, 1, cr11, cr1, cr8, {6} │ │ @ instruction: 0xfe129b69 │ │ cdp2 3, 1, cr0, cr2, cr4, {5} │ │ cdp2 6, 0, cr11, cr15, cr12, {4} │ │ - cdp2 4, 1, cr2, cr2, cr14, {6} │ │ + mrc2 4, 0, r2, cr2, cr11, {7} │ │ cdp2 5, 1, cr3, cr0, cr0, {4} │ │ lsls r1, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #56 @ 0x38 │ │ ldr r3, [pc, #104] @ (2124170 ) │ │ mov r4, r0 │ │ @@ -251457,15 +251457,15 @@ │ │ blx 26ffb50 │ │ ldrb.w r0, [sp, #28] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #36] @ 0x24 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ - ldrh r7, [r2, #10] │ │ + ldrh r4, [r0, #12] │ │ mrc2 5, 0, r3, cr0, cr10, {0} │ │ lsls r1, r4, #1 │ │ adds r4, #226 @ 0xe2 │ │ lsls r1, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #96] @ (21241e4 ) │ │ @@ -251689,15 +251689,15 @@ │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ subs r5, #36 @ 0x24 │ │ cdp2 3, 1, cr3, cr2, cr6, {0} │ │ lsls r1, r4, #1 │ │ asrs r7, r6, #27 │ │ - cdp2 13, 1, cr1, cr2, cr7, {4} │ │ + mrc2 13, 0, r1, cr2, cr4, {5} │ │ cdp2 2, 1, cr3, cr1, cr6, {4} │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #32 │ │ ldr r3, [pc, #368] @ (2124550 ) │ │ @@ -251853,16 +251853,16 @@ │ │ blx 2703810 │ │ blx 26ffb60 │ │ b.n 212466e │ │ cdp2 2, 0, cr3, cr14, cr2, {2} │ │ lsls r1, r4, #1 │ │ asrs r3, r5, #24 │ │ cdp2 2, 1, cr11, cr2, cr9, {7} │ │ - cdp2 12, 1, cr1, cr2, cr5, {4} │ │ - mrc2 3, 0, r2, cr1, cr0, {3} │ │ + mrc2 12, 0, r1, cr2, cr2, {5} │ │ + mrc2 3, 0, r2, cr1, cr13, {4} │ │ cdp2 1, 1, cr3, cr0, cr0, {0} │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ sub sp, #40 @ 0x28 │ │ ldr r3, [pc, #168] @ (2124620 ) │ │ @@ -251936,16 +251936,16 @@ │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ str r6, [sp, #252] @ 0xfc │ │ cdp2 0, 1, cr3, cr2, cr10, {5} │ │ lsls r1, r4, #1 │ │ asrs r3, r3, #18 │ │ - cdp2 2, 1, cr2, cr2, cr5, {6} │ │ - mrc2 0, 0, sl, cr0, cr12, {6} │ │ + mrc2 2, 0, r2, cr2, cr2, {7} │ │ + cdp2 1, 1, cr10, cr0, cr9, {0} │ │ mcr2 13, 0, r7, cr15, cr14, {2} │ │ cdp2 0, 1, cr3, cr1, cr6, {1} │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ vpush {d8-d11} │ │ @@ -252088,15 +252088,15 @@ │ │ blx 26ffb50 │ │ strh r1, [r7, r1] │ │ mrc2 15, 0, r2, cr2, cr6, {6} │ │ lsls r1, r4, #1 │ │ asrs r7, r0, #15 │ │ cdp2 14, 1, cr2, cr2, cr2, {5} │ │ lsls r1, r4, #1 │ │ - pld [r2, #3600] @ 0xe10 │ │ + pldw [pc, #3600] @ 21255c8 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8-d10} │ │ sub sp, #80 @ 0x50 │ │ mov r4, sp │ │ @@ -252234,21 +252234,21 @@ │ │ ldr r1, [pc, #32] @ (2124958 ) │ │ mov r0, r4 │ │ add r1, pc │ │ blx 2704d80 │ │ movs r0, #0 │ │ b.n 212490e │ │ nop │ │ - ittet eq │ │ - mrc2eq 14, 0, r2, cr0, cr0, {2} │ │ - lsleq r1, r4, #1 │ │ - asrne r1, r0, #9 │ │ - cdp2eq 2, 1, cr8, cr2, cr1, {4} │ │ + itee cc │ │ + mrc2cc 14, 0, r2, cr0, cr0, {2} │ │ + lslcs r1, r4, #1 │ │ + asrcs r1, r0, #9 │ │ + cdp2 2, 1, cr8, cr2, cr14, {5} │ │ mrc2 2, 0, r2, cr0, cr0, {1} │ │ - mcr2 15, 0, fp, cr15, cr8, {5} │ │ + cdp2 15, 0, cr11, cr15, cr5, {7} │ │ mcr2 13, 0, r2, cr15, cr10, {0} │ │ lsls r1, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #64] @ (21249a8 ) │ │ movs r1, #1 │ │ movs r2, #1 │ │ @@ -252710,15 +252710,15 @@ │ │ beq.n 2124e3a │ │ ldr r0, [sp, #48] @ 0x30 │ │ b.n 2124e36 │ │ b.n 2124e48 │ │ b.n 2124e3a │ │ b.n 2124e48 │ │ nop │ │ - bkpt 0x008b │ │ + bkpt 0x00b8 │ │ vfmal.f16 d15, s31, s10[1] │ │ lsls r0, r1, #1 │ │ lsls r0, r0, #31 │ │ beq.n 2124e3a │ │ ldr r0, [sp, #80] @ 0x50 │ │ blx 26ffb40 │ │ ldrb.w r0, [sp, #88] @ 0x58 │ │ @@ -252740,21 +252740,21 @@ │ │ ldr r1, [sp, #616] @ 0x268 │ │ ldr r1, [sp, #612] @ 0x264 │ │ ldr r1, [sp, #612] @ 0x264 │ │ ittee lt │ │ cmplt r3, #150 @ 0x96 │ │ lsllt r1, r4, #1 │ │ lsrge r3, r0, #30 │ │ - mrc2ge 9, 0, r9, cr2, cr10, {7} @ │ │ + vselvsge.f32 s18, s4, s15 @ │ │ mrc2 9, 0, pc, cr0, cr11, {0} @ │ │ - mcr2 11, 0, fp, cr14, cr9, {3} @ │ │ + vseleq.f64 d11, d30, d22 │ │ cdp2 2, 0, cr15, cr15, cr5, {5} │ │ mrc2 3, 0, sp, cr1, cr11, {5} │ │ - mrc2 13, 0, r3, cr1, cr0, {0} │ │ - mrc2 12, 0, r3, cr0, cr12, {6} │ │ + mrc2 13, 0, r3, cr1, cr13, {1} │ │ + cdp2 13, 1, cr3, cr0, cr9, {0} │ │ cdp2 14, 1, cr1, cr0, cr10, {3} │ │ cdp2 14, 0, cr1, cr15, cr6, {2} │ │ vcmla.f16 q1, , d0[1], #0 │ │ lsls r1, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #36] @ (2124ecc ) │ │ @@ -252769,15 +252769,15 @@ │ │ movs r2, #3 │ │ add r3, pc │ │ blx 2704e10 │ │ mov r1, r0 │ │ mov r0, r4 │ │ ldmia.w sp!, {r4, r6, r7, lr} │ │ b.w 26feeb8 │ │ - @ instruction: 0xb860 │ │ + @ instruction: 0xb88d │ │ mrc2 0, 0, pc, cr0, cr1, {6} │ │ mrc2 5, 0, fp, cr1, cr0, {6} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #56] @ (2124f14 ) │ │ movs r1, #1 │ │ movs r2, #2 │ │ mov r4, r0 │ │ @@ -252831,15 +252831,15 @@ │ │ blx 2704bb0 │ │ movw r1, #55536 @ 0xd8f0 │ │ mov r0, r4 │ │ movt r1, #65535 @ 0xffff │ │ blx 2705040 │ │ movs r0, #1 │ │ pop {r4, r6, r7, pc} │ │ - str r5, [sp, #972] @ 0x3cc │ │ + str r6, [sp, #128] @ 0x80 │ │ mrc2 10, 0, r0, cr0, cr13, {7} @ │ │ mrc2 4, 0, pc, cr2, cr11, {7} │ │ mcr2 5, 0, fp, cr14, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #48 @ 0x30 │ │ ldr r3, [pc, #276] @ (2125094 ) │ │ @@ -252951,15 +252951,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #40] @ 0x28 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ ldrsb r7, [r1, r6] │ │ cdp2 6, 1, cr2, cr1, cr2, {5} │ │ lsls r1, r4, #1 │ │ - str r7, [sp, #224] @ 0xe0 │ │ + str r7, [sp, #404] @ 0x194 │ │ mcr2 10, 0, r0, cr15, cr13, {3} @ │ │ cdp2 5, 1, cr2, cr2, cr6, {7} │ │ lsls r1, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #140] @ (212513c ) │ │ movs r1, #3 │ │ @@ -253014,16 +253014,16 @@ │ │ ldr r1, [pc, #28] @ (212514c ) │ │ add r1, pc │ │ mov r0, r4 │ │ blx 2704d80 │ │ movs r0, #0 │ │ pop {r4, r6, r7, pc} │ │ nop │ │ - @ instruction: 0xb89b │ │ - mcr2 0, 0, r1, cr15, cr9, {0} │ │ + @ instruction: 0xb8c8 │ │ + cdp2 0, 0, cr1, cr15, cr6, {2} │ │ @ instruction: 0xfe110ae9 │ │ vfmsl.f16 d2, s4, s13[0] │ │ lsls r1, r4, #1 │ │ bl 2456d6c │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ ldr r3, [pc, #104] @ (21251c0 ) │ │ @@ -253134,15 +253134,15 @@ │ │ blx 2704d80 │ │ blx 2700d70 │ │ mov r1, r0 │ │ mov r0, r4 │ │ blx 2704c90 │ │ movs r0, #1 │ │ pop {r4, r6, r7, pc} │ │ - beq.n 21252e6 │ │ + beq.n 2125340 │ │ cdp2 7, 1, cr0, cr0, cr9, {7} │ │ mrc2 5, 0, fp, cr2, cr0, {5} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ ldr r3, [pc, #76] @ (21252cc ) │ │ movs r1, #2 │ │ movs r2, #2 │ │ @@ -253175,15 +253175,15 @@ │ │ mov r0, r5 │ │ blx 2700d80 │ │ movs r0, #0 │ │ add sp, #8 │ │ pop {r4, r5, r7, pc} │ │ str r3, [sp, #32] │ │ mrc2 7, 0, r0, cr1, cr15, {4} │ │ - mrc2 5, 0, r1, cr2, cr8, {7} │ │ + cdp2 6, 1, cr1, cr2, cr5, {1} │ │ mrc2 5, 0, fp, cr0, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ ldr r3, [pc, #120] @ (212535c ) │ │ movs r1, #2 │ │ movs r2, #3 │ │ mov r5, r0 │ │ @@ -253229,17 +253229,17 @@ │ │ mov r2, r0 │ │ mov r0, r4 │ │ mov r1, r6 │ │ blx 2700b00 │ │ movs r0, #0 │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ - strb r6, [r6, #11] │ │ + strb r3, [r4, #12] │ │ mcr2 7, 0, r0, cr15, cr13, {1} │ │ - cdp2 5, 1, cr5, cr2, cr13, {2} │ │ + mrc2 5, 0, r5, cr2, cr10, {3} │ │ mrc2 5, 0, fp, cr0, cr0, {5} │ │ add r7, sp, #8 │ │ sub.w sp, sp, #512 @ 0x200 │ │ mov r4, sp │ │ bfc r4, #0, #4 │ │ mov sp, r4 │ │ ldr r3, [pc, #284] @ (2125498 ) │ │ @@ -253622,16 +253622,16 @@ │ │ movs r0, r0 │ │ movs r0, r0 │ │ lsls r3, r2, #29 │ │ cdp2 1, 1, cr2, cr2, cr10, {3} │ │ lsls r1, r4, #1 │ │ lsls r7, r2, #21 │ │ cdp2 7, 1, cr0, cr2, cr12, {2} │ │ - cdp2 1, 1, cr9, cr2, cr8, {7} │ │ - mcr2 5, 0, pc, cr15, cr6, {7} @ │ │ + mrc2 2, 0, r9, cr2, cr5, {0} │ │ + cdp2 6, 0, cr15, cr15, cr3, {1} │ │ cdp2 7, 0, cr6, cr15, cr12, {7} │ │ cdp2 3, 1, cr4, cr2, cr13, {6} │ │ cdp2 6, 1, cr3, cr2, cr11, {7} │ │ cdp2 0, 0, cr2, cr15, cr10, {3} │ │ lsls r1, r4, #1 │ │ subs r4, r3, #3 │ │ lsls r1, r4, #1 │ │ @@ -253671,17 +253671,17 @@ │ │ vcvt.s32.f64 s0, d16 │ │ vmov r1, s0 │ │ blx 2700870 │ │ movs r0, #0 │ │ add sp, #8 │ │ pop {r4, r5, r7, pc} │ │ nop │ │ - asrs r1, r2, #4 │ │ + asrs r6, r7, #4 │ │ cdp2 2, 1, cr0, cr0, cr11, {2} │ │ - cdp2 13, 1, cr8, cr2, cr3, {2} │ │ + mrc2 13, 0, r8, cr2, cr0, {3} │ │ mrc2 5, 0, fp, cr0, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8-d10} │ │ sub sp, #40 @ 0x28 │ │ ldr r3, [pc, #612] @ (2125ab4 ) │ │ @@ -253899,25 +253899,25 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #32] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ movs r0, r0 │ │ movs r0, r0 │ │ - @ instruction: 0xe800fe10 │ │ + @ instruction: 0xe82dfe10 │ │ adds r4, r2, #7 │ │ lsls r1, r4, #1 │ │ - b.n 2125aa4 │ │ - vfmsl.f16 d14, s0, s4[0] │ │ - cdp2 1, 1, cr0, cr0, cr3, {4} │ │ - mrc2 2, 0, pc, cr2, cr9, {3} │ │ - vfmal.f16 d0, s31, s2[1] │ │ + @ instruction: 0xe81ffe10 │ │ + @ instruction: 0xe83ffe10 │ │ + lsls r3, r0, #6 │ │ + cdp2 2, 1, cr15, cr2, cr6, {5} │ │ + vcmla.f16 q0, , d6[0], #0 │ │ mrc2 6, 0, lr, cr1, cr11, {3} │ │ cdp2 12, 1, cr8, cr1, cr12, {2} │ │ - cdp2 1, 1, cr7, cr1, cr0, {3} │ │ + cdp2 1, 1, cr7, cr1, cr13, {4} │ │ mrc2 11, 0, r1, cr0, cr0, {5} @ │ │ lsls r1, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ ldr r3, [pc, #124] @ (2125b64 ) │ │ movs r1, #2 │ │ @@ -253966,16 +253966,16 @@ │ │ mov r0, r4 │ │ blx 2704c90 │ │ movs r0, #1 │ │ add sp, #8 │ │ pop {r4, r5, r7, pc} │ │ nop │ │ strh r3, [r7, #6] │ │ - mrc2 13, 0, r0, cr2, cr8, {7} │ │ - mrc2 14, 0, r0, cr0, cr8, {0} │ │ + cdp2 14, 1, cr0, cr2, cr5, {1} │ │ + cdp2 14, 1, cr0, cr0, cr5, {2} │ │ mrc2 14, 0, pc, cr0, cr11, {7} │ │ mrc2 5, 0, fp, cr1, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8-d13} │ │ sub sp, #40 @ 0x28 │ │ @@ -254164,22 +254164,22 @@ │ │ movs r0, r0 │ │ movs r0, r0 │ │ b.n 2125668 │ │ mrc2 10, 0, r1, cr1, cr12, {4} @ │ │ lsls r1, r4, #1 │ │ lsls r1, r7, #2 │ │ mrc2 0, 0, r0, cr2, cr9, {6} │ │ - cdp2 13, 1, cr10, cr2, cr4, {5} │ │ + mrc2 13, 0, sl, cr2, cr1, {6} │ │ vcmla.f16 , , d2[1], #0 │ │ lsls r1, r4, #1 │ │ movs r4, #126 @ 0x7e │ │ cdp2 7, 1, cr10, cr2, cr15, {4} │ │ - vfmsl.f16 q1, d17, d6[0] │ │ - vselvs.f16 s16, s2, s15 │ │ - vfmsl.f16 d2, s1, s8[0] │ │ + vselvs.f16 s4, s2, s6 │ │ + mrc2 9, 0, r8, cr1, cr4, {2} @ │ │ + vcmla.f16 q1, q8, d1[0], #90 │ │ mrc2 13, 0, pc, cr1, cr11, {2} │ │ mrc2 5, 0, fp, cr1, cr0, {5} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ ldr r3, [pc, #124] @ (2125e38 ) │ │ movs r1, #2 │ │ movs r2, #2 │ │ @@ -254280,15 +254280,15 @@ │ │ blx 2704d80 │ │ mov r1, r5 │ │ blx 2701610 │ │ movs r0, #0 │ │ add sp, #8 │ │ pop {r4, r5, r7, pc} │ │ nop │ │ - stmia r4!, {r1, r2, r4, r6} │ │ + stmia r4!, {r0, r1, r7} │ │ cdp2 5, 1, cr10, cr0, cr8, {2} │ │ cdp2 5, 1, cr10, cr1, cr8, {3} │ │ mrc2 11, 0, pc, cr1, cr3, {4} @ │ │ mrc2 5, 0, fp, cr1, cr0, {5} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ ldr r3, [pc, #116] @ (2125f50 ) │ │ @@ -254334,17 +254334,17 @@ │ │ blx 2704d80 │ │ mov r1, r5 │ │ blx 27015d0 │ │ movs r0, #0 │ │ add sp, #8 │ │ pop {r4, r5, r7, pc} │ │ nop │ │ - b.n 212630c │ │ - @ instruction: 0xfe100a40 │ │ - @ instruction: 0xfe100a60 │ │ + b.n 2126366 │ │ + @ instruction: 0xfe100a6d │ │ + vselvs.f32 s0, s1, s26 │ │ vselvs.f64 d15, d0, d7 │ │ mrc2 5, 0, fp, cr1, cr0, {5} │ │ add r7, sp, #8 │ │ vpush {d8} │ │ sub sp, #8 │ │ ldr r3, [pc, #196] @ (2126030 ) │ │ movs r1, #3 │ │ @@ -254417,17 +254417,17 @@ │ │ mov r1, r0 │ │ mov r0, r4 │ │ blx 2704c90 │ │ movs r0, #1 │ │ add sp, #8 │ │ vpop {d8} │ │ pop {r4, r5, r7, pc} │ │ - ldr r1, [pc, #144] @ (21260c4 ) │ │ - mrc2 11, 0, r6, cr0, cr11, {3} @ │ │ - mrc2 11, 0, r6, cr0, cr11, {4} @ │ │ + ldr r1, [pc, #324] @ (2126178 ) │ │ + vselvs.f64 d6, d16, d24 │ │ + @ instruction: 0xfe106bc8 │ │ cdp2 7, 1, cr9, cr0, cr15, {1} │ │ mrc2 7, 0, r9, cr2, cr1, {3} │ │ @ instruction: 0xfe12fa43 │ │ mrc2 5, 0, fp, cr1, cr0, {5} │ │ add r7, sp, #8 │ │ vpush {d8} │ │ sub sp, #8 │ │ @@ -254507,15 +254507,15 @@ │ │ movs r0, #0 │ │ add sp, #8 │ │ vpop {d8} │ │ pop {r4, r5, r7, pc} │ │ nop │ │ movs r0, r0 │ │ movs r0, r0 │ │ - strh r0, [r5, #42] @ 0x2a │ │ + strh r5, [r2, #44] @ 0x2c │ │ mrc2 6, 0, r9, cr0, cr13, {6} │ │ mrc2 6, 0, r9, cr2, cr13, {7} │ │ mrc2 12, 0, r5, cr2, cr15, {1} │ │ mrc2 12, 0, r5, cr2, cr9, {4} │ │ @ instruction: 0xfe12f943 │ │ mrc2 5, 0, fp, cr1, cr0, {5} │ │ add r7, sp, #8 │ │ @@ -254595,16 +254595,16 @@ │ │ mov r1, r5 │ │ blx 2701640 │ │ movs r0, #0 │ │ add sp, #8 │ │ vpop {d8} │ │ pop {r4, r5, r7, pc} │ │ subs r0, r3, #5 │ │ - cdp2 15, 1, cr13, cr2, cr0, {3} │ │ - cdp2 15, 1, cr13, cr0, cr0, {4} │ │ + cdp2 15, 1, cr13, cr2, cr13, {4} │ │ + cdp2 15, 1, cr13, cr0, cr13, {5} │ │ cdp2 7, 1, cr3, cr0, cr12, {3} │ │ cdp2 7, 1, cr3, cr2, cr4, {6} │ │ vcmla.f16 , q1, d9[0], #90 │ │ mrc2 5, 0, fp, cr1, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #8 │ │ @@ -254674,19 +254674,19 @@ │ │ mov r1, r5 │ │ mov r2, r6 │ │ blx 2701650 │ │ movs r0, #0 │ │ add sp, #8 │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ - strh r4, [r7, #38] @ 0x26 │ │ - cdp2 7, 0, cr0, cr15, cr15, {0} │ │ - cdp2 7, 1, cr0, cr0, cr15, {1} │ │ - mrc2 6, 0, r0, cr0, cr15, {7} │ │ - cdp2 7, 1, cr0, cr0, cr13, {1} │ │ + strh r1, [r5, #40] @ 0x28 │ │ + mcr2 7, 0, r0, cr15, cr12, {1} │ │ + mrc2 7, 0, r0, cr0, cr12, {2} │ │ + cdp2 7, 1, cr0, cr0, cr12, {1} │ │ + mrc2 7, 0, r0, cr0, cr10, {2} │ │ mrc2 7, 0, pc, cr0, cr15, {3} │ │ mrc2 5, 0, fp, cr1, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #8 │ │ ldr r3, [pc, #172] @ (21263c0 ) │ │ movs r1, #3 │ │ @@ -254757,16 +254757,16 @@ │ │ movs r0, #0 │ │ add sp, #8 │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ b.n 21266f6 │ │ mcr2 10, 0, r5, cr14, cr2, {1} @ │ │ mrc2 10, 0, r5, cr2, cr2, {2} @ │ │ - mrc2 4, 0, ip, cr2, cr6, {0} │ │ - cdp2 4, 0, cr12, cr15, cr4, {2} │ │ + cdp2 4, 1, cr12, cr2, cr3, {2} │ │ + mcr2 4, 0, ip, cr15, cr1, {3} │ │ cdp2 6, 0, cr15, cr15, cr15, {5} │ │ cdp2 5, 1, cr11, cr1, cr0, {4} │ │ mov r7, sp │ │ ldr r1, [pc, #8] @ (21263e8 ) │ │ add r1, pc │ │ blx 2704bb0 │ │ movs r0, #1 │ │ @@ -254961,45 +254961,45 @@ │ │ asrs r2, r2, #7 │ │ lsls r1, r4, #1 │ │ cmp r7, ip │ │ mcr2 10, 0, r1, cr15, cr14, {1} @ │ │ cdp2 1, 1, cr9, cr2, cr1, {3} │ │ mrc2 1, 0, r0, cr2, cr5, {3} │ │ movs r0, r0 │ │ - lsls r6, r3, #10 │ │ + lsls r3, r1, #11 │ │ cdp2 1, 1, cr0, cr0, cr7, {6} │ │ movs r0, r0 │ │ bkpt 0x0022 │ │ mcr2 2, 0, r0, cr14, cr5, {2} │ │ movs r0, r0 │ │ strb r2, [r6, r6] │ │ mrc2 2, 0, r0, cr2, cr3, {7} │ │ movs r0, r0 │ │ subs r5, r0, r0 │ │ cdp2 3, 1, cr0, cr2, cr13, {4} │ │ movs r0, r0 │ │ - stmia r1!, {r0, r1, r2, r3, r4, r6, r7} │ │ + stmia r2!, {r2, r3} │ │ mcr2 4, 0, r0, cr15, cr3, {4} │ │ movs r0, r0 │ │ strb r7, [r3, #20] │ │ mrc2 5, 0, r0, cr2, cr9, {4} │ │ movs r0, r0 │ │ movs r7, #46 @ 0x2e │ │ mcr2 7, 0, r0, cr15, cr15, {6} │ │ movs r0, r0 │ │ - b.n 2126cc0 │ │ + b.n 2126d1a │ │ vseleq.f16 s0, s30, s11 │ │ movs r0, r0 │ │ - movs r3, #244 @ 0xf4 │ │ + movs r4, #33 @ 0x21 │ │ @ instruction: 0xfe100acb │ │ movs r0, r0 │ │ adds r1, r7, r6 │ │ mrc2 11, 0, r0, cr2, cr1, {3} @ │ │ movs r0, r0 │ │ - ldrb r0, [r2, #31] │ │ + ldrb r5, [r7, #31] │ │ mcr2 12, 0, r0, cr15, cr7, {0} │ │ movs r0, r0 │ │ ldr r4, [sp, #40] @ 0x28 │ │ mrc2 12, 0, r0, cr1, cr1, {2} │ │ movs r0, r0 │ │ add sl, r2 │ │ cdp2 12, 0, cr0, cr15, cr11, {4} │ │ @@ -255037,15 +255037,15 @@ │ │ add r1, pc │ │ bl 2094bc4 ::InfoType* std::__ndk1::vector::InfoType, std::__ndk1::allocator::InfoType> >::__emplace_back_slow_path(WarpMeshInfo const&)@@Base+0x24c> │ │ mov r0, r5 │ │ blx 27050d0 │ │ movs r0, #0 │ │ pop {r4, r5, r7, pc} │ │ nop │ │ - lsls r5, r2, #15 │ │ + lsls r2, r0, #16 │ │ cdp2 1, 1, cr4, cr0, cr0, {0} │ │ cdp2 0, 1, cr1, cr1, cr12, {0} │ │ lsls r1, r4, #1 │ │ subs r4, #228 @ 0xe4 │ │ mrc2 4, 0, sp, cr1, cr4, {6} │ │ bmi.n 2126632 │ │ push {r4, r6, r7, lr} │ │ @@ -255098,15 +255098,15 @@ │ │ vpop {d8} │ │ pop {r4, r6, r7, pc} │ │ nop │ │ ldr r1, [sp, #616] @ 0x268 │ │ ldr r1, [sp, #612] @ 0x264 │ │ ldr r1, [sp, #612] @ 0x264 │ │ subs r7, #185 @ 0xb9 │ │ - add r3, pc, #148 @ (adr r3, 21267b0 ) │ │ + add r3, pc, #328 @ (adr r3, 2126864 ) │ │ cdp2 2, 0, cr3, cr15, cr12, {5} │ │ mrc2 14, 0, fp, cr2, cr7, {1} │ │ mcr2 5, 0, fp, cr14, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ ldr r3, [pc, #148] @ (21267c4 ) │ │ movs r1, #2 │ │ @@ -255163,15 +255163,15 @@ │ │ movw r1, #55536 @ 0xd8f0 │ │ mov r0, r4 │ │ movt r1, #65535 @ 0xffff │ │ blx 2704e50 │ │ movs r0, #0 │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ - ldrb r6, [r0, #27] │ │ + ldrb r3, [r6, #27] │ │ mrc2 2, 0, pc, cr0, cr1, {7} │ │ cdp2 13, 1, cr11, cr1, cr10, {5} │ │ mcr2 5, 0, fp, cr14, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ ldr r3, [pc, #140] @ (2126868 ) │ │ movs r1, #2 │ │ @@ -255229,16 +255229,16 @@ │ │ blx 2704bb0 │ │ movs r0, #1 │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ nop │ │ subs r7, #146 @ 0x92 │ │ cdp2 2, 1, cr15, cr1, cr5, {2} │ │ - mrc2 9, 0, sp, cr1, cr11, {0} @ │ │ - cdp2 14, 1, cr9, cr0, cr1, {1} │ │ + @ instruction: 0xfe11d948 │ │ + cdp2 14, 1, cr9, cr0, cr14, {2} │ │ mcr2 5, 0, fp, cr15, cr0, {5} │ │ add r7, sp, #8 │ │ sub sp, #24 │ │ mov r4, r0 │ │ ldr r0, [pc, #252] @ (2126980 ) │ │ mov r1, r4 │ │ add r0, pc │ │ @@ -255448,15 +255448,15 @@ │ │ bl 2086830 │ │ add r0, sp, #8 │ │ bl 2086830 │ │ blx 26ffb60 │ │ nop │ │ lsrs r4, r2, #18 │ │ lsls r1, r4, #1 │ │ - cbnz r3, 2126aa8 │ │ + cbnz r0, 2126ab4 │ │ @ instruction: 0xfe100bc4 │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #60 @ 0x3c │ │ mov r4, r0 │ │ @@ -255676,21 +255676,21 @@ │ │ blx r1 │ │ b.n 2126ca6 │ │ nop │ │ lsrs r2, r7, #13 │ │ lsls r1, r4, #1 │ │ strh r1, [r7, r3] │ │ vfmsl.f16 d5, s5, s14[0] │ │ - cdp2 12, 1, cr9, cr1, cr1, {2} │ │ + cdp2 12, 1, cr9, cr1, cr14, {3} │ │ vcmla.f16 , q8, d12[0], #90 │ │ - mrc2 0, 0, lr, cr1, cr4, {2} │ │ + cdp2 0, 1, cr14, cr1, cr1, {4} │ │ mcr2 9, 0, sp, cr15, cr8, {4} @ │ │ - mcr2 12, 0, r7, cr14, cr6, {0} │ │ - mcr2 6, 0, pc, cr15, cr10, {1} @ │ │ - cdp2 5, 1, cr13, cr0, cr2, {6} │ │ + cdp2 12, 0, cr7, cr14, cr3, {2} │ │ + cdp2 6, 0, cr15, cr15, cr7, {3} │ │ + cdp2 5, 1, cr13, cr0, cr15, {7} │ │ mrc2 9, 0, r0, cr0, cr8, {6} @ │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #48 @ 0x30 │ │ mov r4, r0 │ │ @@ -255815,15 +255815,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #24] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ lsrs r6, r4, #4 │ │ lsls r1, r4, #1 │ │ - push {r0, r2, r3, r4, r5, r6, r7, lr} │ │ + @ instruction: 0xb62a │ │ vcmla.f16 , q8, d0[1], #90 │ │ vcmla.f16 d0, d1, d14[1], #90 │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ sub sp, #88 @ 0x58 │ │ @@ -255983,15 +255983,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #24] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ lsls r6, r2, #31 │ │ lsls r1, r4, #1 │ │ add r3, sp, #872 @ 0x368 │ │ - mrc2 7, 0, r9, cr2, cr9, {5} │ │ + cdp2 7, 1, cr9, cr2, cr6, {7} │ │ cdp2 7, 0, cr0, cr15, cr6, {5} │ │ lsls r1, r4, #1 │ │ lsls r0, r1, #26 │ │ lsls r1, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #64 @ 0x40 │ │ @@ -256424,15 +256424,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #8] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ lsls r2, r0, #12 │ │ lsls r1, r4, #1 │ │ - sxth r0, r2 │ │ + sxth r5, r7 │ │ mcr2 2, 0, r0, cr15, cr0, {2} │ │ lsls r1, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ sub sp, #16 │ │ mov r4, r0 │ │ @@ -257008,15 +257008,15 @@ │ │ mov r0, r4 │ │ mvn.w r1, #1 │ │ blx 2704b70 │ │ mov r0, r6 │ │ ldr.w r8, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ stc2 0, cr0, [lr], {96} @ 0x60 │ │ - str r2, [r3, r6] │ │ + str r7, [r0, r7] │ │ mrc2 13, 0, r9, cr0, cr2, {1} │ │ lsls r7, r3, #1 │ │ │ │ 021279ec : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r1 │ │ @@ -257250,15 +257250,15 @@ │ │ nop │ │ @ instruction: 0xfb3e0060 │ │ b.n 2128006 │ │ mrc2 15, 0, r2, cr1, cr12, {6} │ │ cdp2 15, 0, cr2, cr15, cr4, {5} │ │ mcr2 13, 0, pc, cr15, cr8, {3} @ │ │ lsls r0, r4, #1 │ │ - ldr r7, [pc, #528] @ (2127e5c ) │ │ + ldr r7, [pc, #708] @ (2127f10 ) │ │ mrc2 10, 0, pc, cr0, cr0, {0} @ │ │ lsls r0, r4, #1 │ │ │ │ 02127c50 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ @@ -257392,22 +257392,22 @@ │ │ it eq │ │ beq.w 26fef00 │ │ b.n 2127d7a │ │ nop │ │ ldmia r0!, {r3, r4, r5, r6} │ │ @ instruction: 0xfe0ef96e │ │ lsls r0, r4, #1 │ │ - lsrs r0, r7, #17 │ │ - mrc2 12, 0, r8, cr0, cr13, {6} │ │ + lsrs r5, r4, #18 │ │ + cdp2 13, 1, cr8, cr0, cr10, {0} │ │ vcmla.f16 d15, d31, d0[1], #0 │ │ lsls r0, r4, #1 │ │ @ instruction: 0xff83ffff │ │ - lsrs r4, r3, #17 │ │ + lsrs r1, r1, #18 │ │ mrc2 13, 0, r2, cr0, cr14, {7} │ │ - cdp2 12, 0, cr0, cr15, cr2, {2} │ │ + cdp2 12, 0, cr0, cr15, cr15, {3} │ │ vcmla.f16 , q8, d4[0], #90 │ │ lsls r0, r4, #1 │ │ │ │ 02127dd4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -257760,31 +257760,31 @@ │ │ moveq r0, r5 │ │ addeq sp, #40 @ 0x28 │ │ ldmiaeq.w sp!, {r8, r9, sl} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ @ instruction: 0xf7740060 │ │ - bkpt 0x0053 │ │ - mrc2 14, 0, fp, cr0, cr15, {1} │ │ + bkpt 0x0080 │ │ + cdp2 14, 1, cr11, cr0, cr12, {3} │ │ mrc2 9, 0, pc, cr0, cr2, {2} @ │ │ lsls r0, r4, #1 │ │ - stmia r1!, {r0, r2, r4, r7} │ │ + stmia r1!, {r1, r6, r7} │ │ mrc2 9, 0, pc, cr0, cr2, {1} @ │ │ lsls r0, r4, #1 │ │ - ldr r3, [pc, #720] @ (212845c ) │ │ + ldr r3, [pc, #900] @ (2128510 ) │ │ mrc2 9, 0, pc, cr0, cr2, {0} @ │ │ lsls r0, r4, #1 │ │ ldrh r4, [r7, r7] │ │ mrc2 12, 0, sp, cr2, cr11, {5} │ │ mrc2 4, 0, ip, cr1, cr0, {0} │ │ - cdp2 5, 0, cr8, cr14, cr9, {7} │ │ + mcr2 6, 0, r8, cr14, cr6, {0} │ │ vseleq.f32 s4, s31, s0 │ │ @ instruction: 0xfe0f2a48 │ │ - mcr2 7, 0, r2, cr15, cr7, {4} │ │ + cdp2 7, 0, cr2, cr15, cr4, {6} │ │ @ instruction: 0xfe10f9e6 │ │ lsls r0, r4, #1 │ │ lsrs r1, r7, #20 │ │ mcr2 4, 0, pc, cr15, cr6, {6} @ │ │ lsls r0, r4, #1 │ │ │ │ 021281b8 : │ │ @@ -257945,15 +257945,15 @@ │ │ blt.n 21283ce │ │ cdp2 4, 1, cr15, cr1, cr0, {3} │ │ lsls r0, r4, #1 │ │ @ instruction: 0xf6fc0060 │ │ ldr r5, [r1, r4] │ │ cdp2 6, 1, cr15, cr2, cr14, {7} │ │ lsls r0, r4, #1 │ │ - add r0, pc, #772 @ (adr r0, 2128690 ) │ │ + add r0, pc, #952 @ (adr r0, 2128744 ) │ │ @ instruction: 0xfe103b43 │ │ mrc2 2, 0, pc, cr2, cr2, {7} │ │ lsls r0, r4, #1 │ │ │ │ 02128394 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -258152,16 +258152,16 @@ │ │ mrc2 2, 0, pc, cr1, cr12, {3} │ │ lsls r0, r4, #1 │ │ adds.w r0, r6, #14680064 @ 0xe00000 │ │ ldrsb r5, [r6, r2] │ │ cdp2 5, 1, cr15, cr2, cr8, {0} │ │ lsls r0, r4, #1 │ │ add.w r0, r8, #14680064 @ 0xe00000 │ │ - pop {r0, r1, r3, r4, r5, r6, r7} │ │ - mrc2 12, 0, r9, cr0, cr8, {3} │ │ + pop {r3, r5, pc} │ │ + cdp2 12, 1, cr9, cr0, cr5, {5} │ │ cdp2 4, 1, cr13, cr0, cr0, {4} │ │ vcmla.f16 , , d11[1], #90 │ │ mrc2 0, 0, pc, cr2, cr10, {4} │ │ lsls r0, r4, #1 │ │ │ │ 02128600 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -258328,16 +258328,16 @@ │ │ ands.w r0, lr, #96 @ 0x60 │ │ bvs.n 2128752 │ │ cdp2 2, 1, cr15, cr1, cr14, {5} │ │ lsls r0, r4, #1 │ │ strb r1, [r2, r3] │ │ mrc2 2, 0, pc, cr2, cr0, {5} │ │ lsls r0, r4, #1 │ │ - blt.n 21287fe >&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x32> │ │ - mrc2 3, 0, lr, cr0, cr4, {0} │ │ + blt.n 2128858 >&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x8c> │ │ + cdp2 3, 1, cr14, cr0, cr1, {2} │ │ mcr2 14, 0, lr, cr15, cr8, {5} │ │ lsls r0, r4, #1 │ │ │ │ 021287cc >&, std::__ndk1::__fs::filesystem::path const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ @@ -258482,15 +258482,15 @@ │ │ ldrb.w r0, [sp] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #8] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ - stmia r3!, {r4, r5, r7} │ │ + stmia r3!, {r0, r2, r3, r4, r6, r7} │ │ cdp2 14, 0, cr14, cr15, cr8, {2} │ │ lsls r0, r4, #1 │ │ pop {r0, r2, r3} │ │ cdp2 0, 0, cr0, cr14, cr15, {5} │ │ movs r0, r0 │ │ stcl 0, cr0, [r8, #-384]! @ 0xfffffe80 │ │ subs r2, #191 @ 0xbf │ │ @@ -258603,15 +258603,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #8] │ │ blxne 26ffb40 │ │ add r0, sp, #16 │ │ blx 27048f0 │ │ blx 26ffb60 │ │ stcl 0, cr0, [r4], #-384 @ 0xfffffe80 │ │ - stmia r1!, {r2, r4, r5, r7} │ │ + stmia r1!, {r0, r5, r6, r7} │ │ mcr2 14, 0, lr, cr15, cr8, {1} │ │ lsls r0, r4, #1 │ │ ldcl 0, cr0, [ip], #384 @ 0x180 │ │ rsbs r0, lr, r0, asr #1 │ │ │ │ 02128a94 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -258877,16 +258877,16 @@ │ │ ldrb.w r0, [sp, #16] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #24] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ @ instruction: 0xe9920060 │ │ - ldc2 14, cr15, [r0], #60 @ 0x3c │ │ - ldrb r5, [r6, #20] │ │ + ldc2l 14, cr15, [sp], {15} │ │ + ldrb r2, [r4, #21] │ │ mcr2 9, 0, lr, cr15, cr0, {0} @ │ │ lsls r0, r4, #1 │ │ │ │ 02128d54 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -259076,16 +259076,16 @@ │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ @ instruction: 0xe8c60060 │ │ ldmia r7!, {r0, r2, r4, r5, r6} │ │ mrc2 6, 0, fp, cr1, cr12, {0} │ │ vdot.bf16 , q7, d0[1] │ │ vdot.bf16 , , d2[0] │ │ - mcr2 7, 0, r3, cr15, cr0, {6} │ │ - vcmla.f16 d5, d31, d4[1], #0 │ │ + mcr2 7, 0, r3, cr15, cr13, {7} │ │ + vfmal.f16 , d31, d1[0] │ │ mcr2 6, 0, lr, cr15, cr10, {6} │ │ lsls r0, r4, #1 │ │ │ │ 02128f8c : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #32 │ │ @@ -259187,18 +259187,18 @@ │ │ addeq sp, #32 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ b.n 2128da8 │ │ lsls r0, r4, #1 │ │ ldrd r0, r0, [lr, #-384] @ 0x180 │ │ - cbz r1, 21290ac │ │ + cbz r6, 21290b6 │ │ mrc2 9, 0, lr, cr0, cr14, {1} @ │ │ lsls r0, r4, #1 │ │ - subs r3, #192 @ 0xc0 │ │ + subs r3, #237 @ 0xed │ │ mrc2 9, 0, lr, cr0, cr14, {0} @ │ │ lsls r0, r4, #1 │ │ ldr r4, [pc, #32] @ (21290b4 ) │ │ cdp2 14, 1, cr2, cr2, cr14, {0} │ │ cdp2 5, 1, cr14, cr2, cr8, {6} │ │ lsls r0, r4, #1 │ │ │ │ @@ -259298,20 +259298,20 @@ │ │ pop {r4, r5, r7, pc} │ │ movs r0, #200 @ 0xc8 │ │ pop {r4, r5, r7, pc} │ │ movs r0, #5 │ │ pop {r4, r5, r7, pc} │ │ nop │ │ str r0, [sp, #368] @ 0x170 │ │ - mcr2 7, 0, pc, cr14, cr10, {6} @ │ │ + vcmla.f16 d15, d14, d7[0], #0 │ │ mcr2 13, 0, r8, cr15, cr3, {4} │ │ cdp2 4, 1, cr6, cr1, cr8, {4} │ │ cdp2 15, 1, cr14, cr2, cr7, {6} │ │ - cdp2 2, 1, cr15, cr1, cr5, {0} │ │ - cdp2 2, 1, cr5, cr0, cr10, {2} │ │ + mrc2 2, 0, pc, cr1, cr2, {1} │ │ + mrc2 2, 0, r5, cr0, cr7, {3} │ │ mrc2 1, 0, r5, cr0, cr7, {4} │ │ Address 0x2129196 is out of bounds. │ │ │ │ │ │ 02129198 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -259350,16 +259350,16 @@ │ │ add r1, pc │ │ mov r0, r4 │ │ blx 2704d80 │ │ movs r0, #0 │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ cbz r0, 212926a >&)@@Base+0x34> │ │ - vfmal.f16 d7, s28, s4[0] │ │ - mcr2 4, 0, r5, cr15, cr6, {1} │ │ + vfmal.f16 d7, s28, s15[1] │ │ + cdp2 4, 0, cr5, cr15, cr3, {3} │ │ Address 0x212920e is out of bounds. │ │ │ │ │ │ 02129210 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ ldr.w r0, [r0, #652] @ 0x28c │ │ @@ -259649,15 +259649,15 @@ │ │ ldreq.w r8, [sp], #4 │ │ it eq │ │ popeq {r4, r5, r6, r7, pc} │ │ b.n 21294b8 │ │ nop │ │ b.n 21298d0 │ │ lsls r0, r4, #1 │ │ - @ instruction: 0xb71f │ │ + @ instruction: 0xb74c │ │ mcr2 1, 0, lr, cr15, cr12, {2} │ │ lsls r0, r4, #1 │ │ b.n 212982c │ │ lsls r0, r4, #1 │ │ │ │ 02129500 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -259727,15 +259727,15 @@ │ │ moveq r0, r4 │ │ addeq sp, #32 │ │ ldmiaeq.w sp!, {r8, r9, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ b.n 21297e4 │ │ lsls r0, r4, #1 │ │ - adds r1, #163 @ 0xa3 │ │ + adds r1, #208 @ 0xd0 │ │ cdp2 0, 0, cr14, cr15, cr0, {5} │ │ lsls r0, r4, #1 │ │ │ │ 021295b0 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -260026,37 +260026,37 @@ │ │ ldr r7, [pc, #124] @ (2129910 ) │ │ lsrs r7, r7, #13 │ │ adcs r2, r4 │ │ b.n 2129f30 │ │ lsls r0, r4, #1 │ │ b.n 212990c │ │ lsls r0, r4, #1 │ │ - strb r1, [r5, #1] │ │ + strb r6, [r2, #2] │ │ mcr2 3, 0, lr, cr15, cr10, {0} │ │ lsls r0, r4, #1 │ │ - str r7, [r3, r0] │ │ + str r4, [r1, r1] │ │ mrc2 2, 0, lr, cr0, cr10, {7} │ │ lsls r0, r4, #1 │ │ cmp r5, #104 @ 0x68 │ │ mrc2 2, 0, lr, cr1, cr10, {6} │ │ lsls r0, r4, #1 │ │ - push {r1, r2, r4, lr} │ │ + push {r0, r1, r6, lr} │ │ cdp2 2, 0, cr14, cr15, cr14, {4} │ │ lsls r0, r4, #1 │ │ - add r2, sp, #836 @ 0x344 │ │ - cdp2 14, 1, cr14, cr0, cr7, {5} │ │ + add r2, sp, #1016 @ 0x3f8 │ │ + mrc2 14, 0, lr, cr0, cr4, {6} │ │ mrc2 1, 0, r8, cr0, cr14, {3} │ │ cdp2 15, 1, cr13, cr2, cr8, {0} │ │ lsls r0, r4, #1 │ │ bmi.n 21298f0 │ │ mcr2 4, 0, sp, cr14, cr13, {0} │ │ mcr2 1, 0, lr, cr14, cr6, {6} │ │ lsls r0, r4, #1 │ │ bmi.n 2129904 │ │ - mcr2 2, 0, sp, cr14, cr15, {2} │ │ + cdp2 2, 0, cr13, cr14, cr12, {4} │ │ cdp2 4, 0, cr12, cr15, cr9, {7} │ │ cdp2 13, 1, cr10, cr1, cr12, {0} │ │ mcr2 0, 0, lr, cr14, cr8, {6} │ │ lsls r0, r4, #1 │ │ ble.n 2129884 │ │ lsls r0, r4, #1 │ │ │ │ @@ -260097,16 +260097,16 @@ │ │ mvn.w r1, #1 │ │ ldr.w fp, [sp], #4 │ │ ldmia.w sp!, {r4, r5, r6, r7, lr} │ │ b.w 26feeac │ │ nop │ │ b.n 2129998 , std::__ndk1::allocator > const&)@@Base+0x30> │ │ lsls r0, r4, #1 │ │ - add r0, sp, #380 @ 0x17c │ │ - mrc2 12, 0, lr, cr0, cr7, {1} │ │ + add r0, sp, #560 @ 0x230 │ │ + cdp2 12, 1, cr14, cr0, cr4, {3} │ │ Address 0x2129966 is out of bounds. │ │ │ │ │ │ 02129968 , std::__ndk1::allocator > const&)@@Base>: │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ ldr r2, [pc, #64] @ (21299b0 , std::__ndk1::allocator > const&)@@Base+0x48>) │ │ @@ -260130,15 +260130,15 @@ │ │ add r2, pc │ │ blx 2705370 │ │ ldr r0, [r4, #16] │ │ mvn.w r1, #1 │ │ ldmia.w sp!, {r4, r5, r7, lr} │ │ b.w 26feeac │ │ nop │ │ - add r7, pc, #996 @ (adr r7, 2129d98 ) │ │ + add r0, sp, #152 @ 0x98 │ │ mrc2 11, 0, r0, cr0, cr13, {6} @ │ │ Address 0x21299b6 is out of bounds. │ │ │ │ │ │ 021299b8 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -260189,18 +260189,18 @@ │ │ movs r2, #0 │ │ blx 27052a0 │ │ movs r0, #4 │ │ str r0, [r4, #40] @ 0x28 │ │ pop {r4, r5, r7, pc} │ │ svc 92 @ 0x5c │ │ lsls r0, r4, #1 │ │ - add r7, pc, #636 @ (adr r7, 2129cb4 ) │ │ + add r7, pc, #816 @ (adr r7, 2129d68 ) │ │ mrc2 15, 0, sp, cr0, cr12, {1} │ │ lsls r0, r4, #1 │ │ - adds r1, #190 @ 0xbe │ │ + adds r1, #235 @ 0xeb │ │ mrc2 15, 0, sp, cr0, cr12, {0} │ │ lsls r0, r4, #1 │ │ tst r6, r0 │ │ Address 0x2129a46 is out of bounds. │ │ │ │ │ │ 02129a48 : │ │ @@ -261672,16 +261672,16 @@ │ │ b.n 212a91c │ │ ldr r1, [pc, #16] @ (212a92c ) │ │ add r1, pc │ │ blx 2704d80 │ │ movs r0, #0 │ │ pop {r4, r5, r7, pc} │ │ ldr r4, [sp, #392] @ 0x188 │ │ - cdp2 0, 0, cr6, cr14, cr12, {7} │ │ - mcr2 13, 0, r3, cr15, cr0, {0} │ │ + mcr2 1, 0, r6, cr14, cr9, {0} │ │ + mcr2 13, 0, r3, cr15, cr13, {1} │ │ Address 0x212a92e is out of bounds. │ │ │ │ │ │ 0212a930 >::__push_back_slow_path(Value&&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -261901,27 +261901,27 @@ │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ ldmia r3, {r1, r3, r7} │ │ lsls r0, r4, #1 │ │ lsrs r5, r7, #29 │ │ mrc2 0, 0, r0, cr2, cr7, {5} │ │ movs r0, r0 │ │ - bge.n 212aab6 │ │ + bge.n 212ab10 │ │ mrc2 0, 0, r0, cr0, cr1, {7} │ │ movs r0, r0 │ │ - svc 15 │ │ + svc 60 @ 0x3c │ │ cdp2 1, 0, cr0, cr15, cr11, {3} │ │ movs r0, r0 │ │ - ldrsh r1, [r5, r6] │ │ + ldrsh r6, [r2, r7] │ │ mcr2 2, 0, r0, cr15, cr13, {4} │ │ movs r0, r0 │ │ adds r1, #122 @ 0x7a │ │ cdp2 3, 1, cr0, cr2, cr15, {6} │ │ movs r0, r0 │ │ - ldrsh r2, [r2, r6] │ │ + ldrsh r7, [r7, r6] │ │ cdp2 4, 0, cr0, cr15, cr1, {7} │ │ movs r0, r0 │ │ subs r3, #85 @ 0x55 │ │ mrc2 5, 0, r0, cr1, cr3, {3} │ │ movs r0, r0 │ │ ldmia r3!, {r1, r2} │ │ lsls r0, r4, #1 │ │ @@ -261950,15 +261950,15 @@ │ │ moveq r0, #1 │ │ addeq sp, #8 │ │ popeq {r7, pc} │ │ blx 26ffb50 │ │ nop │ │ ldmia r2!, {r1, r3, r5, r7} │ │ lsls r0, r4, #1 │ │ - bls.n 212aba0 │ │ + bge.n 212abfa │ │ vselvs.f32 s24, s1, s28 │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ mov r4, r0 │ │ ldr r0, [pc, #112] @ (212ac3c ) │ │ @@ -262007,15 +262007,15 @@ │ │ ittt eq │ │ moveq r0, #0 │ │ addeq sp, #16 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ ldmia r2!, {r5, r6} │ │ lsls r0, r4, #1 │ │ - subs r5, r0, #7 │ │ + subs r2, r6, #7 │ │ vselvs.f32 s24, s0, s8 │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #72 @ 0x48 │ │ mov r4, sp │ │ @@ -262131,15 +262131,15 @@ │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ ldmia r1!, {r2, r3, r6, r7} │ │ lsls r0, r4, #1 │ │ bmi.n 212ae74 │ │ - mrc2 15, 0, r1, cr1, cr13, {0} │ │ + cdp2 15, 1, cr1, cr1, cr10, {2} │ │ mrc2 6, 0, r5, cr0, cr0, {7} │ │ cdp2 4, 1, cr13, cr1, cr9, {1} │ │ vfmsl.f16 q6, d17, d0[1] │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -262257,16 +262257,16 @@ │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ ldmia r0!, {r2, r3, r7} │ │ lsls r0, r4, #1 │ │ bcc.n 212adde │ │ - mrc2 13, 0, r1, cr1, cr13, {6} │ │ - mrc2 11, 0, sp, cr0, cr14, {3} @ │ │ + cdp2 14, 1, cr1, cr1, cr10, {0} │ │ + vselvs.f64 d13, d16, d27 │ │ mcr2 7, 0, r9, cr15, cr15, {0} │ │ mcr2 7, 0, ip, cr14, cr8, {4} │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #24 │ │ mov r4, r0 │ │ @@ -262365,22 +262365,22 @@ │ │ itt ne │ │ ldrne r0, [sp, #8] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ stmia r7!, {r3, r4, r6} │ │ lsls r0, r4, #1 │ │ - lsr.w lr, r5, pc @ │ │ - adds r1, r5, #2 │ │ - cdp2 3, 1, cr13, cr0, cr13, {7} │ │ + asrs.w lr, r2, pc @ │ │ + adds r6, r2, #3 │ │ + mrc2 4, 0, sp, cr0, cr10, {0} │ │ cdp2 2, 1, cr7, cr0, cr14, {0} │ │ - vseleq.f16 s26, s29, s24 │ │ + mcr2 9, 0, sp, cr14, cr9, {5} @ │ │ mcr2 15, 0, r6, cr15, cr15, {1} │ │ mrc2 6, 0, r4, cr1, cr8, {1} │ │ - cdp2 4, 1, cr3, cr2, cr4, {1} │ │ + mrc2 4, 0, r3, cr2, cr1, {2} │ │ cdp2 3, 1, cr3, cr0, cr13, {4} │ │ mrc2 13, 0, r2, cr1, cr8, {1} │ │ mrc2 6, 0, ip, cr2, cr12, {4} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #32 │ │ @@ -262441,15 +262441,15 @@ │ │ moveq r0, #1 │ │ addeq sp, #32 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ stmia r6!, {r3, r4, r5} │ │ lsls r0, r4, #1 │ │ bl 20ccca0 │ │ - subs r1, r1, r6 │ │ + subs r6, r6, r6 │ │ cdp2 5, 1, cr12, cr0, cr8, {6} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #24 │ │ mov r4, r0 │ │ ldr r0, [pc, #128] @ (212b114 ) │ │ @@ -262506,15 +262506,15 @@ │ │ addeq sp, #24 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ stmia r5!, {r3, r4, r7} │ │ lsls r0, r4, #1 │ │ cmp r3, #226 @ 0xe2 │ │ - @ instruction: 0xfe121ae9 │ │ + mrc2 11, 0, r1, cr2, cr6, {0} @ │ │ cdp2 5, 1, cr12, cr0, cr14, {1} │ │ lsls r0, r4, #1 │ │ │ │ 0212b124 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -262772,80 +262772,80 @@ │ │ addeq sp, #8 │ │ ldreq.w fp, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ stmia r4!, {r1, r2, r4, r5, r6, r7} │ │ lsls r0, r4, #1 │ │ - bhi.n 212b36a │ │ + bls.n 212b3c4 │ │ cdp2 3, 0, cr0, cr15, cr7, {2} │ │ movs r0, r0 │ │ rev r2, r7 │ │ mcr2 4, 0, r0, cr14, cr5, {3} │ │ movs r0, r0 │ │ - ldr r2, [sp, #464] @ 0x1d0 │ │ + ldr r2, [sp, #644] @ 0x284 │ │ cdp2 5, 0, cr0, cr15, cr3, {5} │ │ movs r0, r0 │ │ - bmi.n 212b3f4 │ │ + bmi.n 212b44e │ │ cdp2 6, 1, cr0, cr0, cr9, {4} │ │ movs r0, r0 │ │ - adds r4, #204 @ 0xcc │ │ + adds r4, #249 @ 0xf9 │ │ mrc2 6, 0, r0, cr0, cr11, {7} │ │ movs r0, r0 │ │ rev r0, r1 │ │ mcr2 7, 0, r0, cr14, cr1, {4} │ │ movs r0, r0 │ │ - bcc.n 212b3cc │ │ + bmi.n 212b426 │ │ vcmla.f16 q0, q0, d7[1], #90 │ │ movs r0, r0 │ │ - ldr r2, [sp, #208] @ 0xd0 │ │ + ldr r2, [sp, #388] @ 0x184 │ │ vfmal.f16 q0, d31, d5[3] │ │ movs r0, r0 │ │ mov r5, r1 │ │ mrc2 9, 0, r0, cr2, cr3, {4} @ │ │ movs r0, r0 │ │ - bl 209d022 ::operator()(char const*)@@Base+0x1882> │ │ + bl 20ca022 │ │ lsrs r5, r6, #8 │ │ movs r0, r0 │ │ ldmia r7, {r1, r2, r4, r7} │ │ mrc2 10, 0, r0, cr1, cr11, {4} @ │ │ movs r0, r0 │ │ - ldr r3, [r6, r2] │ │ + ldr r0, [r4, r3] │ │ mcr2 10, 0, r0, cr15, cr9, {6} @ │ │ movs r0, r0 │ │ add r3, sp, #124 @ 0x7c │ │ mrc2 11, 0, r0, cr1, cr15, {1} @ │ │ movs r0, r0 │ │ lsrs r7, r0, #18 │ │ vselvs.f64 d0, d18, d21 │ │ movs r0, r0 │ │ cmp r2, #158 @ 0x9e │ │ cdp2 12, 1, cr0, cr2, cr11, {0} │ │ movs r0, r0 │ │ - strb r7, [r5, #4] │ │ + strb r4, [r3, #5] │ │ cdp2 12, 1, cr0, cr0, cr9, {2} │ │ movs r0, r0 │ │ - asrs r3, r5, #19 │ │ + asrs r0, r3, #20 │ │ cdp2 12, 0, cr0, cr15, cr7, {4} │ │ movs r0, r0 │ │ - asrs r4, r4, #19 │ │ + asrs r1, r2, #20 │ │ mcr2 9, 0, fp, cr15, cr9, {2} @ │ │ - cdp2 15, 0, cr8, cr14, cr14, {1} │ │ + mcr2 15, 0, r8, cr14, cr11, {2} │ │ cdp2 15, 1, cr6, cr0, cr3, {3} │ │ cdp2 3, 1, cr7, cr1, cr5, {1} │ │ - cdp2 5, 0, cr5, cr14, cr11, {0} │ │ - mrc2 14, 0, r8, cr0, cr9, {7} │ │ - mrc2 7, 0, fp, cr0, cr10, {5} │ │ - mcr2 14, 0, r8, cr15, cr15, {6} │ │ - cdp2 5, 1, cr3, cr0, cr15, {4} │ │ + mcr2 5, 0, r5, cr14, cr8, {1} │ │ + cdp2 15, 1, cr8, cr0, cr6, {1} │ │ + cdp2 7, 1, cr11, cr0, cr7, {7} │ │ + cdp2 15, 0, cr8, cr15, cr12, {0} │ │ + mrc2 5, 0, r3, cr0, cr12, {5} │ │ mcr2 4, 0, pc, cr15, cr4, {7} @ │ │ cdp2 2, 1, cr9, cr0, cr11, {4} │ │ - cdp2 6, 0, cr15, cr14, cr3, {2} │ │ + mcr2 6, 0, pc, cr14, cr0, {3} @ │ │ vcmla.f16 d11, d31, d0[1], #0 │ │ - mcr2 5, 0, r3, cr14, cr15, {1} │ │ + cdp2 5, 0, cr3, cr14, cr12, {3} │ │ mcr2 14, 0, r6, cr15, cr15, {4} │ │ cdp2 14, 1, cr12, cr1, cr14, {1} │ │ cdp2 14, 1, cr6, cr1, cr5, {4} │ │ mrc2 6, 0, lr, cr1, cr0, {3} │ │ mrc2 11, 0, r0, cr1, cr1, {4} @ │ │ movs r0, r0 │ │ add r7, sl │ │ @@ -262954,21 +262954,21 @@ │ │ ldmiaeq.w sp!, {r8, r9, sl} │ │ it eq │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ stmia r1!, {r3, r4, r5, r6} │ │ lsls r0, r4, #1 │ │ - strh r5, [r3, r3] │ │ - mrc2 2, 0, r5, cr0, cr7, {7} │ │ + strh r2, [r1, r4] │ │ + cdp2 3, 1, cr5, cr0, cr4, {1} │ │ mrc2 15, 0, r4, cr0, cr1, {3} │ │ cdp2 2, 1, cr4, cr1, cr1, {7} │ │ - cdp2 4, 1, cr15, cr2, cr4, {2} │ │ - mcr2 3, 0, r3, cr15, cr9, {1} │ │ - mcr2 12, 0, sl, cr15, cr2, {4} │ │ + mrc2 4, 0, pc, cr2, cr1, {3} │ │ + cdp2 3, 0, cr3, cr15, cr6, {3} │ │ + mcr2 12, 0, sl, cr15, cr15, {5} │ │ mrc2 0, 0, ip, cr0, cr4, {4} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ vpush {d8-d10} │ │ sub sp, #16 │ │ @@ -263072,15 +263072,15 @@ │ │ stmia r0!, {r2, r3, r4, r5} │ │ lsls r0, r4, #1 │ │ lsrs r0, r3, #2 │ │ cdp2 6, 1, cr13, cr2, cr2, {7} │ │ mcr2 5, 0, fp, cr14, cr9, {4} │ │ cdp2 6, 0, cr10, cr14, cr5, {7} │ │ mrc2 5, 0, fp, cr1, cr3, {4} │ │ - mcr2 11, 0, sl, cr14, cr8, {4} @ │ │ + @ instruction: 0xfe0eabc5 │ │ vfmsl.f16 d0, s0, s1[1] │ │ mrc2 15, 0, fp, cr2, cr8, {2} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ vpush {d8-d10} │ │ @@ -263158,18 +263158,18 @@ │ │ ldmiaeq.w sp!, {r8, r9, fp} │ │ it eq │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ bkpt 0x00fe │ │ lsls r0, r4, #1 │ │ ldr r4, [r4, #40] @ 0x28 │ │ - mrc2 3, 0, r5, cr1, cr8, {2} │ │ - mcr2 14, 0, ip, cr15, cr11, {1} │ │ + cdp2 3, 1, cr5, cr1, cr5, {4} │ │ + cdp2 14, 0, cr12, cr15, cr8, {3} │ │ vfmsl.f16 q4, d16, d7[2] │ │ - vselvs.f32 s16, s2, s19 │ │ + mrc2 10, 0, r8, cr1, cr6, {2} @ │ │ mrc2 14, 0, fp, cr0, cr10, {2} │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ mov r1, r0 │ │ ldr r0, [pc, #96] @ (212b878 ) │ │ @@ -263211,15 +263211,15 @@ │ │ moveq r0, #0 │ │ addeq sp, #16 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ bkpt 0x0014 │ │ lsls r0, r4, #1 │ │ - str r3, [sp, #800] @ 0x320 │ │ + str r3, [sp, #980] @ 0x3d4 │ │ mcr2 1, 0, lr, cr15, cr1, {5} │ │ mrc2 0, 0, ip, cr1, cr14, {7} │ │ lsls r0, r4, #1 │ │ pop {r1, r3, r6, r7, pc} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -263274,17 +263274,17 @@ │ │ addeq sp, #16 │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ pop {r1, r2, r3, r7, pc} │ │ lsls r0, r4, #1 │ │ - lsrs r6, r7, #25 │ │ - mcr2 15, 0, r2, cr15, cr9, {6} │ │ - mcr2 15, 0, r6, cr15, cr15, {0} │ │ + lsrs r3, r5, #26 │ │ + cdp2 0, 0, cr3, cr15, cr6, {0} │ │ + cdp2 15, 0, cr6, cr15, cr12, {2} │ │ vdot.bf16 d11, d15, d10[1] │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ vpush {d8-d9} │ │ sub sp, #16 │ │ @@ -263356,16 +263356,16 @@ │ │ ldreq.w r8, [sp], #4 │ │ it eq │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ pop {r1, r2, r5, r6, r7} │ │ lsls r0, r4, #1 │ │ b.n 212bb7e │ │ - cdp2 0, 1, cr13, cr1, cr11, {6} │ │ - cdp2 0, 0, cr13, cr15, cr6, {7} │ │ + mrc2 0, 0, sp, cr1, cr8, {7} │ │ + mcr2 1, 0, sp, cr15, cr3, {0} │ │ cdp2 3, 0, cr13, cr15, cr8, {4} │ │ cdp2 15, 0, cr11, cr14, cr6, {5} │ │ lsls r0, r4, #1 │ │ pop {r1, r4, r6} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -263421,15 +263421,15 @@ │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ pop {r1, r2} │ │ lsls r0, r4, #1 │ │ ldr r3, [r6, #52] @ 0x34 │ │ - mcr2 15, 0, lr, cr14, cr14, {1} │ │ + cdp2 15, 0, cr14, cr14, cr11, {3} │ │ cdp2 0, 0, cr15, cr15, cr10, {7} │ │ vseleq.f64 d11, d30, d18 │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #16 │ │ @@ -263549,17 +263549,17 @@ │ │ moveq r0, #0 │ │ addeq sp, #16 │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ hlt 0x003e │ │ lsls r0, r4, #1 │ │ - strh r7, [r1, #50] @ 0x32 │ │ - cdp2 15, 1, cr12, cr0, cr1, {0} │ │ - cdp2 0, 0, cr1, cr15, cr5, {1} │ │ + strh r4, [r7, #50] @ 0x32 │ │ + cdp2 15, 1, cr12, cr0, cr14, {1} │ │ + mcr2 0, 0, r1, cr15, cr2, {2} │ │ mrc2 13, 0, fp, cr0, cr6, {4} │ │ lsls r0, r4, #1 │ │ rev16 r0, r2 │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ @@ -263773,15 +263773,15 @@ │ │ moveq r0, #0 │ │ addeq sp, #16 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ @ instruction: 0xb86c │ │ lsls r0, r4, #1 │ │ - ldr r2, [r1, #36] @ 0x24 │ │ + ldr r7, [r6, #36] @ 0x24 │ │ mcr2 4, 0, r6, cr15, cr5, {2} │ │ vcmla.f16 d11, d1, d10[1], #90 │ │ lsls r0, r4, #1 │ │ push {r7, lr} │ │ mov r7, sp │ │ sub sp, #8 │ │ mov r1, r0 │ │ @@ -264018,20 +264018,20 @@ │ │ itt eq │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ @ instruction: 0xb708 │ │ lsls r0, r4, #1 │ │ strh r2, [r3, #50] @ 0x32 │ │ - vcmla.f16 d4, d30, d5[0], #0 │ │ + vfmal.f16 d4, s29, s5[0] │ │ mrc2 4, 0, r4, cr0, cr7, {7} │ │ vcmla.f16 , , d9[1], #90 │ │ - @ instruction: 0xfe12e9cc │ │ - vcmla.f16 q1, , d7[0], #0 │ │ - cdp2 2, 0, cr10, cr15, cr2, {1} │ │ + mrc2 9, 0, lr, cr2, cr9, {7} @ │ │ + vfmal.f16 q1, d31, d4[2] │ │ + cdp2 2, 0, cr10, cr15, cr15, {2} │ │ cdp2 5, 1, cr11, cr0, cr12, {5} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ vpush {d8-d10} │ │ sub sp, #16 │ │ @@ -264338,16 +264338,16 @@ │ │ mov r0, r6 │ │ blx r1 │ │ add r0, sp, #28 │ │ blx 27048f0 │ │ blx 26ffb60 │ │ push {r1, r2, r3, r6} │ │ lsls r0, r4, #1 │ │ - stmia r6!, {r5, r6, r7} │ │ - cdp2 7, 0, cr4, cr15, cr1, {3} │ │ + stmia r7!, {r0, r2, r3} │ │ + cdp2 7, 0, cr4, cr15, cr14, {4} │ │ cdp2 5, 0, cr11, cr15, cr2, {0} │ │ lsls r0, r4, #1 │ │ cbz r6, 212c474 │ │ lsls r0, r4, #1 │ │ uxth r4, r3 │ │ lsls r0, r4, #1 │ │ │ │ @@ -264402,27 +264402,27 @@ │ │ lsls r0, r4, #1 │ │ bl 1f3809e │ │ lsls r1, r4, #1 │ │ movs r0, r0 │ │ ldrb r0, [r0, r3] │ │ cdp2 0, 0, cr0, cr14, cr7, {3} │ │ movs r0, r0 │ │ - stmia r1!, {r0, r1, r2, r4, r5} │ │ + stmia r1!, {r2, r5, r6} │ │ cdp2 0, 1, cr0, cr0, cr5, {7} │ │ movs r0, r0 │ │ cbz r4, 212c4c6 │ │ lsls r0, r4, #1 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r1, [pc, #8] @ (212c4a4 ) │ │ add r1, pc │ │ blx 2704bb0 │ │ movs r0, #1 │ │ pop {r7, pc} │ │ - mov r1, r9 │ │ + mov r6, lr │ │ mcr2 5, 0, fp, cr15, cr0, {5} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r1, r0 │ │ ldr r0, [pc, #116] @ (212c528 ) │ │ mov r4, sp │ │ add r0, pc │ │ @@ -264465,15 +264465,15 @@ │ │ ittt eq │ │ moveq r0, #1 │ │ addeq sp, #8 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ cbz r0, 212c54a │ │ lsls r0, r4, #1 │ │ - ldrb r6, [r0, #8] │ │ + ldrb r3, [r6, #8] │ │ mrc2 1, 0, fp, cr0, cr8, {0} │ │ lsls r0, r4, #1 │ │ push {r7, lr} │ │ mov r7, sp │ │ sub sp, #8 │ │ mov r1, r0 │ │ ldr r0, [pc, #60] @ (212c57c ) │ │ @@ -264503,15 +264503,15 @@ │ │ ittt eq │ │ moveq r0, #0 │ │ addeq sp, #8 │ │ popeq {r7, pc} │ │ blx 26ffb50 │ │ sub sp, #440 @ 0x1b8 │ │ lsls r0, r4, #1 │ │ - ldrb r4, [r7, #5] │ │ + ldrb r1, [r5, #6] │ │ cdp2 0, 1, cr11, cr0, cr4, {6} │ │ lsls r0, r4, #1 │ │ │ │ 0212c588 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ @@ -264600,30 +264600,30 @@ │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ sub sp, #96 @ 0x60 │ │ lsls r0, r4, #1 │ │ bl 1db827e │ │ lsls r1, r7, #3 │ │ movs r0, r0 │ │ - ittet gt │ │ - mrc2gt 1, 0, r0, cr0, cr3, {1} │ │ - movgt r0, r0 │ │ - tstle r5, r5 │ │ - mrc2gt 1, 0, r0, cr0, cr9, {4} │ │ + itee │ │ + mrc2 1, 0, r0, cr0, cr3, {1} │ │ + moval r0, r0 │ │ + negal r2, r3 │ │ + mrc2 1, 0, r0, cr0, cr9, {4} │ │ movs r0, r0 │ │ - stmia r3!, {r0, r4, r5} │ │ + stmia r3!, {r1, r2, r3, r4, r6} │ │ cdp2 1, 0, cr0, cr15, cr15, {7} │ │ movs r0, r0 │ │ ldrb r5, [r2, #31] │ │ cdp2 3, 0, cr0, cr14, cr5, {0} │ │ movs r0, r0 │ │ - add ip, fp │ │ + cmp r1, r1 │ │ mcr2 3, 0, r0, cr15, cr11, {2} │ │ movs r0, r0 │ │ - add pc, sl │ │ + cmp r4, r0 │ │ mcr2 3, 0, r0, cr15, cr9, {6} │ │ movs r0, r0 │ │ subs r6, #157 @ 0x9d │ │ cdp2 4, 1, cr0, cr1, cr3, {2} │ │ movs r0, r0 │ │ b.n 212ca78 │ │ cdp2 4, 1, cr0, cr0, cr13, {5} │ │ @@ -264707,15 +264707,15 @@ │ │ ittt eq │ │ moveq r0, #0 │ │ addeq sp, #8 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ add r7, sp, #184 @ 0xb8 │ │ lsls r0, r4, #1 │ │ - strb r4, [r7, #30] │ │ + strb r1, [r5, #31] │ │ cdp2 14, 1, cr10, cr0, cr4, {7} │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r1, r0 │ │ ldr r0, [pc, #72] @ (212c7bc ) │ │ @@ -264749,16 +264749,16 @@ │ │ moveq r0, #0 │ │ addeq sp, #8 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ add r6, sp, #736 @ 0x2e0 │ │ lsls r0, r4, #1 │ │ - add r2, pc, #948 @ (adr r2, 212cb78 ) │ │ - mcr2 7, 0, r7, cr15, cr8, {1} │ │ + add r3, pc, #104 @ (adr r3, 212c82c ) │ │ + cdp2 7, 0, cr7, cr15, cr5, {3} │ │ cdp2 14, 1, cr10, cr0, cr6, {4} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #352 @ 0x160 │ │ mov r4, sp │ │ bfc r4, #0, #4 │ │ @@ -264860,17 +264860,17 @@ │ │ b.n 212c8d0 │ │ add r0, sp, #16 │ │ blx 2705870 │ │ blx 26ffb60 │ │ nop │ │ add r6, sp, #304 @ 0x130 │ │ lsls r0, r4, #1 │ │ - str r4, [r2, #4] │ │ + str r1, [r0, #8] │ │ cdp2 7, 0, cr15, cr15, cr13, {0} │ │ - mrc2 6, 0, r7, cr1, cr14, {5} │ │ + cdp2 6, 1, cr7, cr1, cr11, {7} │ │ mrc2 13, 0, sl, cr0, cr6, {3} │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r1, r0 │ │ ldr r0, [pc, #72] @ (212c944 ) │ │ @@ -264904,16 +264904,16 @@ │ │ moveq r0, #0 │ │ addeq sp, #8 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ add r5, sp, #192 @ 0xc0 │ │ lsls r0, r4, #1 │ │ - strh r5, [r1, #24] │ │ - mcr2 5, 0, r7, cr15, cr0, {5} │ │ + strh r2, [r7, #24] │ │ + mcr2 5, 0, r7, cr15, cr13, {6} │ │ mrc2 12, 0, sl, cr0, cr14, {7} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r1, r0 │ │ ldr r0, [pc, #108] @ (212c9cc ) │ │ @@ -264964,15 +264964,15 @@ │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ add r4, sp, #816 @ 0x330 │ │ lsls r0, r4, #1 │ │ cmp r6, #195 @ 0xc3 │ │ mrc2 0, 0, sp, cr2, cr2, {7} │ │ - mrc2 5, 0, r7, cr1, cr14, {1} │ │ + cdp2 5, 1, cr7, cr1, cr11, {3} │ │ mrc2 12, 0, sl, cr0, cr6, {3} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #92] @ (212ca48 ) │ │ @@ -265013,15 +265013,15 @@ │ │ addeq sp, #8 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ add r4, sp, #248 @ 0xf8 │ │ lsls r0, r4, #1 │ │ str r3, [sp, #636] @ 0x27c │ │ - mrc2 4, 0, r7, cr1, cr14, {5} │ │ + cdp2 4, 1, cr7, cr1, cr11, {7} │ │ mrc2 11, 0, sl, cr0, cr10, {7} @ │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #92] @ (212cac0 ) │ │ @@ -265061,16 +265061,16 @@ │ │ moveq r0, #1 │ │ addeq sp, #8 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ add r3, sp, #792 @ 0x318 │ │ lsls r0, r4, #1 │ │ - add r0, pc, #132 @ (adr r0, 212cb4c ) │ │ - cdp2 4, 0, cr7, cr15, cr6, {2} │ │ + add r0, pc, #312 @ (adr r0, 212cc00 ) │ │ + mcr2 4, 0, r7, cr15, cr3, {3} │ │ vselvs.f64 d10, d16, d2 │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #92] @ (212cb38 ) │ │ @@ -265110,16 +265110,16 @@ │ │ moveq r0, #1 │ │ addeq sp, #8 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ add r3, sp, #312 @ 0x138 │ │ lsls r0, r4, #1 │ │ - subs r7, #253 @ 0xfd │ │ - cdp2 3, 0, cr7, cr15, cr14, {6} │ │ + ands r2, r5 │ │ + mcr2 3, 0, r7, cr15, cr11, {7} │ │ vselvs.f64 d10, d0, d10 │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #8 │ │ mov r4, r0 │ │ @@ -265173,16 +265173,16 @@ │ │ addeq sp, #8 │ │ ldreq.w fp, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ add r2, sp, #840 @ 0x348 │ │ lsls r0, r4, #1 │ │ - umlal pc, lr, r9, lr @ │ │ - strb r0, [r2, #13] │ │ + ldc2 14, cr15, [r6], {14} │ │ + strb r5, [r7, #13] │ │ @ instruction: 0xfe101ae9 │ │ mrc2 10, 0, sl, cr1, cr2, {3} @ │ │ lsls r0, r4, #1 │ │ │ │ 0212cbe8 : │ │ movs r0, #10 │ │ bx lr │ │ @@ -265235,18 +265235,18 @@ │ │ blx 26ffb50 │ │ nop │ │ add r2, sp, #208 @ 0xd0 │ │ lsls r0, r4, #1 │ │ mcr 14, 1, pc, cr7, cr1, {0} @ │ │ lsls r1, r4, #1 │ │ movs r0, r0 │ │ - subs r6, #185 @ 0xb9 │ │ + subs r6, #230 @ 0xe6 │ │ cdp2 1, 0, cr0, cr15, cr3, {0} │ │ movs r0, r0 │ │ - subs r6, #162 @ 0xa2 │ │ + subs r6, #207 @ 0xcf │ │ cdp2 1, 0, cr0, cr15, cr1, {3} │ │ movs r0, r0 │ │ add r1, sp, #928 @ 0x3a0 │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #56 @ 0x38 │ │ @@ -265309,15 +265309,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #24] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ add r1, sp, #680 @ 0x2a8 │ │ lsls r0, r4, #1 │ │ - strb r0, [r7, #8] │ │ + strb r5, [r4, #9] │ │ @ instruction: 0xfe10db62 │ │ mrc2 9, 0, sl, cr0, cr12, {1} @ │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r1, r0 │ │ @@ -265355,16 +265355,16 @@ │ │ moveq r0, #1 │ │ addeq sp, #8 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ add r0, sp, #992 @ 0x3e0 │ │ lsls r0, r4, #1 │ │ - subs r4, r7, r5 │ │ - mcr2 1, 0, r7, cr15, cr8, {3} │ │ + subs r1, r5, r6 │ │ + cdp2 1, 0, cr7, cr15, cr5, {5} │ │ vfmsl.f16 d10, s1, s13[1] │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r1, r0 │ │ ldr r0, [pc, #80] @ (212cdf0 ) │ │ @@ -265401,16 +265401,16 @@ │ │ moveq r0, #1 │ │ addeq sp, #8 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ add r0, sp, #560 @ 0x230 │ │ lsls r0, r4, #1 │ │ - ldrh r2, [r7, r2] │ │ - cdp2 1, 0, cr7, cr15, cr12, {0} │ │ + ldrh r7, [r4, r3] │ │ + mcr2 1, 0, r7, cr15, cr9, {1} │ │ vfmsl.f16 q5, d0, d2[0] │ │ lsls r0, r4, #1 │ │ │ │ 0212ce00 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ @@ -265463,21 +265463,21 @@ │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ add r0, sp, #128 @ 0x80 │ │ lsls r0, r4, #1 │ │ ldc 14, cr15, [r3], {17} │ │ lsls r5, r6, #1 │ │ movs r0, r0 │ │ - subs r4, #165 @ 0xa5 │ │ + subs r4, #210 @ 0xd2 │ │ mcr2 1, 0, r0, cr15, cr7, {0} │ │ movs r0, r0 │ │ - subs r4, #142 @ 0x8e │ │ + subs r4, #187 @ 0xbb │ │ mcr2 1, 0, r0, cr15, cr5, {3} │ │ movs r0, r0 │ │ - subs r1, #167 @ 0xa7 │ │ + subs r1, #212 @ 0xd4 │ │ mrc2 1, 0, r0, cr0, cr3, {6} │ │ movs r0, r0 │ │ add r7, pc, #792 @ (adr r7, 212d1b8 (int, FatalErrors, char const*)@@Base>) │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #56 @ 0x38 │ │ @@ -265540,16 +265540,16 @@ │ │ itt ne │ │ ldrne r0, [sp, #24] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ add r7, pc, #520 @ (adr r7, 212d14c * CelxLua::safeGetClass >(int, FatalErrors, char const*)@@Base+0x50>) │ │ lsls r0, r4, #1 │ │ - strb r0, [r2, #0] │ │ - cdp2 7, 1, cr1, cr0, cr1, {4} │ │ + strb r5, [r7, #0] │ │ + cdp2 7, 1, cr1, cr0, cr14, {5} │ │ mrc2 7, 0, sl, cr0, cr4, {0} │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r1, r0 │ │ ldr r0, [pc, #80] @ (212cfac ) │ │ @@ -265586,16 +265586,16 @@ │ │ moveq r0, #1 │ │ addeq sp, #8 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ add r6, pc, #832 @ (adr r6, 212d2f0 >&)@@Base+0x58>) │ │ lsls r0, r4, #1 │ │ - strh r2, [r6, r7] │ │ - mrc2 15, 0, r6, cr0, cr0, {2} │ │ + strb r7, [r3, r0] │ │ + mrc2 15, 0, r6, cr0, cr13, {3} │ │ mrc2 6, 0, sl, cr0, cr6, {4} │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r1, r0 │ │ ldr r0, [pc, #80] @ (212d018 ) │ │ @@ -265632,16 +265632,16 @@ │ │ moveq r0, #1 │ │ addeq sp, #8 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ add r6, pc, #400 @ (adr r6, 212d1ac ) │ │ lsls r0, r4, #1 │ │ - asrs r5, r2, #26 │ │ - cdp2 14, 1, cr6, cr0, cr4, {7} │ │ + asrs r2, r0, #27 │ │ + mrc2 15, 0, r6, cr0, cr1, {0} │ │ cdp2 6, 1, cr10, cr0, cr10, {1} │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r1, r0 │ │ ldr r0, [pc, #72] @ (212d07c ) │ │ @@ -265677,15 +265677,15 @@ │ │ moveq r0, #0 │ │ addeq sp, #8 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ add r5, pc, #992 @ (adr r5, 212d460 ) │ │ lsls r0, r4, #1 │ │ blt.n 212d122 * CelxLua::safeGetClass >(int, FatalErrors, char const*)@@Base+0x26> │ │ - mcr2 14, 0, r6, cr14, cr8, {3} │ │ + cdp2 14, 0, cr6, cr14, cr5, {5} │ │ cdp2 5, 1, cr10, cr0, cr4, {6} │ │ lsls r0, r4, #1 │ │ │ │ 0212d08c (int, FatalErrors, char const*)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -266063,15 +266063,15 @@ │ │ bl 211e3d4 │ │ blx 26ffb60 │ │ add r6, pc, #696 @ (adr r6, 212d6c8 ) │ │ lsls r0, r4, #1 │ │ add r3, pc, #496 @ (adr r3, 212d604 ) │ │ lsls r0, r4, #1 │ │ ldrh r6, [r5, #18] │ │ - vcmla.f16 , , d1[0], #90 │ │ + vcmla.f16 , , d14[1], #90 │ │ cdp2 2, 0, cr10, cr15, cr12, {3} │ │ lsls r0, r4, #1 │ │ │ │ 0212d420 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -266507,72 +266507,72 @@ │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ add r0, pc, #168 @ (adr r0, 212d8cc ) │ │ lsls r0, r4, #1 │ │ b.n 212d062 │ │ mrc2 3, 0, r0, cr1, cr15, {0} │ │ movs r0, r0 │ │ - ldr r4, [r3, #8] │ │ + ldr r1, [r1, #12] │ │ cdp2 3, 1, cr0, cr0, cr5, {1} │ │ movs r0, r0 │ │ ldr r2, [r1, #40] @ 0x28 │ │ mrc2 3, 0, r0, cr1, cr11, {4} │ │ movs r0, r0 │ │ movs r2, #25 │ │ mrc2 4, 0, r0, cr2, cr5, {1} │ │ movs r0, r0 │ │ ldr r4, [pc, #72] @ (212d890 ) │ │ mrc2 4, 0, r0, cr1, cr11, {5} │ │ movs r0, r0 │ │ - asrs r6, r1, #10 │ │ + asrs r3, r7, #10 │ │ mcr2 5, 0, r0, cr15, cr1, {2} │ │ movs r0, r0 │ │ - strh r1, [r5, r0] │ │ + strh r6, [r2, r1] │ │ cdp2 6, 0, cr0, cr15, cr15, {7} │ │ movs r0, r0 │ │ - str r4, [sp, #300] @ 0x12c │ │ + str r4, [sp, #480] @ 0x1e0 │ │ mcr2 7, 0, r0, cr15, cr1, {4} │ │ movs r0, r0 │ │ cmp r6, #46 @ 0x2e │ │ @ instruction: 0xfe110963 │ │ movs r0, r0 │ │ - push {r0, r1, r5} │ │ + push {r4, r6} │ │ cdp2 1, 0, cr1, cr15, cr9, {7} │ │ movs r0, r0 │ │ - lsrs r0, r0, #23 │ │ + lsrs r5, r5, #23 │ │ cdp2 2, 0, cr1, cr15, cr15, {5} │ │ movs r0, r0 │ │ str r0, [r1, #108] @ 0x6c │ │ cdp2 3, 1, cr1, cr1, cr9, {1} │ │ movs r0, r0 │ │ str r2, [r3, #108] @ 0x6c │ │ cdp2 4, 1, cr1, cr1, cr3, {1} │ │ movs r0, r0 │ │ - asrs r4, r5, #8 │ │ + asrs r1, r3, #9 │ │ mcr2 5, 0, r1, cr15, cr5, {5} │ │ movs r0, r0 │ │ strh r5, [r1, #56] @ 0x38 │ │ cdp2 6, 1, cr1, cr1, cr11, {2} │ │ movs r0, r0 │ │ - bcs.n 212d822 │ │ + bcs.n 212d87c │ │ mcr2 15, 0, r1, cr15, cr13, {0} │ │ movs r0, r0 │ │ strh r1, [r7, #54] @ 0x36 │ │ cdp2 0, 1, cr2, cr1, cr15, {3} │ │ movs r0, r0 │ │ ldr r1, [pc, #160] @ (212d950 ) │ │ mrc2 0, 0, r2, cr1, cr9, {7} │ │ movs r0, r0 │ │ ldr r2, [r5, #104] @ 0x68 │ │ mcr2 2, 0, r2, cr14, cr7, {2} │ │ movs r0, r0 │ │ ldr r3, [pc, #756] @ (212dbb4 ) │ │ mcr2 3, 0, r2, cr14, cr5, {5} │ │ movs r0, r0 │ │ - strb r7, [r1, #3] │ │ + strb r4, [r7, #3] │ │ vseleq.f16 s4, s31, s15 │ │ movs r0, r0 │ │ strh r2, [r7, #52] @ 0x34 │ │ vselvs.f32 s4, s2, s11 │ │ movs r0, r0 │ │ ldmia r6, {r1, r3, r6} │ │ mrc2 10, 0, r2, cr0, cr3, {6} @ │ │ @@ -266585,33 +266585,33 @@ │ │ movs r0, r0 │ │ str r4, [sp, #808] @ 0x328 │ │ mcr2 13, 0, r2, cr14, cr13, {2} │ │ movs r0, r0 │ │ ldr r2, [pc, #984] @ (212dcd0 ) │ │ mrc2 14, 0, r2, cr1, cr7, {0} │ │ movs r0, r0 │ │ - cbz r3, 212d94e │ │ + cbz r0, 212d95a │ │ cdp2 15, 0, cr2, cr15, cr13, {1} │ │ movs r0, r0 │ │ ldr r0, [r5, #96] @ 0x60 │ │ cdp2 0, 0, cr3, cr14, cr3, {2} │ │ movs r0, r0 │ │ - ldrh r0, [r0, #20] │ │ + ldrh r5, [r5, #20] │ │ mrc2 1, 0, r3, cr0, cr1, {0} │ │ movs r0, r0 │ │ ldr r5, [r2, #96] @ 0x60 │ │ cdp2 1, 0, cr3, cr14, cr3, {3} │ │ movs r0, r0 │ │ strh r2, [r1, #16] │ │ cdp2 2, 1, cr3, cr1, cr13, {2} │ │ movs r0, r0 │ │ b.n 212d7ec │ │ cdp2 3, 1, cr3, cr1, cr11, {5} │ │ movs r0, r0 │ │ - ldr r3, [pc, #664] @ (212dbc8 ) │ │ + ldr r3, [pc, #844] @ (212dc7c ) │ │ cdp2 4, 1, cr3, cr0, cr13, {3} │ │ movs r0, r0 │ │ ldr r2, [pc, #580] @ (212db7c ) │ │ mrc2 4, 0, r3, cr1, cr7, {7} │ │ movs r0, r0 │ │ ldr r6, [sp, #120] @ 0x78 │ │ lsls r0, r4, #1 │ │ @@ -267015,15 +267015,15 @@ │ │ movs r0, r0 │ │ movs r0, r0 │ │ ldr r2, [sp, #384] @ 0x180 │ │ lsls r0, r4, #1 │ │ str r0, [sp, #500] @ 0x1f4 │ │ mcr2 15, 0, ip, cr14, cr10, {5} │ │ mcr2 1, 0, r8, cr14, cr4, {7} │ │ - mrc2 11, 0, lr, cr1, cr11, {2} @ │ │ + vselvs.f64 d14, d17, d8 │ │ mcr2 0, 0, r0, cr14, cr0, {4} │ │ vselvs.f16 s18, s4, s24 │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ mov r4, r0 │ │ @@ -267085,15 +267085,15 @@ │ │ moveq r0, #1 │ │ addeq sp, #16 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ ldr r0, [sp, #752] @ 0x2f0 │ │ lsls r0, r4, #1 │ │ - ldrh r0, [r3, #42] @ 0x2a │ │ + ldrh r5, [r0, #44] @ 0x2c │ │ mcr2 14, 0, ip, cr15, cr6, {0} │ │ cdp2 15, 0, cr5, cr14, cr3, {6} │ │ mrc2 14, 0, sl, cr1, cr10, {0} │ │ @ instruction: 0xfe0e8ae7 │ │ vcmla.f16 , q7, d10[0], #0 │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ @@ -267273,22 +267273,22 @@ │ │ itt ne │ │ ldrne r0, [sp, #40] @ 0x28 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ ldr r0, [sp, #32] │ │ lsls r0, r4, #1 │ │ ldmia r5!, {r0, r1, r2, r3, r6, r7} │ │ - mcr2 14, 0, r6, cr14, cr9, {0} │ │ + cdp2 14, 0, cr6, cr14, cr6, {2} │ │ vdot.bf16 q6, , d14[0] │ │ cdp2 7, 0, cr9, cr14, cr10, {3} │ │ lsls r0, r4, #1 │ │ str r6, [sp, #544] @ 0x220 │ │ lsls r0, r4, #1 │ │ - ldr r6, [r1, #84] @ 0x54 │ │ - vdot.bf16 d6, d15, d12[1] │ │ + ldr r3, [r7, #84] @ 0x54 │ │ + mcr2 13, 0, r6, cr15, cr9, {2} │ │ mcr2 5, 0, fp, cr15, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8-d9} │ │ sub sp, #56 @ 0x38 │ │ mov r4, r0 │ │ @@ -267656,30 +267656,30 @@ │ │ cmp r5, #0 │ │ strb.w r0, [sp, #32] │ │ add r0, sp, #32 │ │ add.w r4, r0, #1 │ │ bne.w 212e4f2 │ │ b.n 212e4fc │ │ ldc2l 14, cr15, [r6], {17} │ │ - @ instruction: 0xebbffe0f │ │ + @ instruction: 0xebecfe0f │ │ ldmia r3!, {r2, r5, r6} │ │ mcr2 13, 0, r5, cr14, cr4, {1} │ │ - mrc2 5, 0, r2, cr1, cr7, {7} │ │ + cdp2 6, 1, cr2, cr1, cr4, {1} │ │ vseleq.f16 s26, s31, s10 │ │ cdp2 12, 1, cr10, cr1, cr15, {4} │ │ - cdp2 15, 0, cr7, cr14, cr7, {0} │ │ + mcr2 15, 0, r7, cr14, cr4, {1} │ │ mrc2 6, 0, ip, cr0, cr7, {7} │ │ - cdp2 5, 1, cr2, cr0, cr5, {0} │ │ + mrc2 5, 0, r2, cr0, cr2, {1} │ │ cdp2 12, 0, cr5, cr15, cr15, {0} │ │ mrc2 15, 0, r5, cr1, cr12, {2} │ │ cdp2 4, 0, cr12, cr14, cr12, {7} │ │ cdp2 0, 0, cr12, cr14, cr14, {4} │ │ - mrc2 10, 0, r5, cr0, cr0, {5} @ │ │ - mrc2 12, 0, r7, cr0, cr1, {0} │ │ - mrc2 5, 0, lr, cr0, cr15, {1} │ │ + mrc2 10, 0, r5, cr0, cr13, {6} @ │ │ + mrc2 12, 0, r7, cr0, cr14, {1} │ │ + cdp2 5, 1, cr14, cr0, cr12, {3} │ │ cdp2 0, 0, cr15, cr14, cr5, {2} │ │ movs r7, r1 │ │ mov r8, r6 │ │ adds r6, r0, #1 │ │ mov r0, r6 │ │ blx 26ffbf0 │ │ mov r4, r0 │ │ @@ -268098,15 +268098,15 @@ │ │ blx 26ffb60 │ │ nop │ │ str r6, [sp, #128] @ 0x80 │ │ lsls r0, r4, #1 │ │ ldrh r6, [r1, #52] @ 0x34 │ │ lsls r0, r4, #1 │ │ push {r0, r2, r4, lr} │ │ - cdp2 14, 1, cr3, cr1, cr4, {1} │ │ + mrc2 14, 0, r3, cr1, cr1, {2} │ │ mcr2 5, 0, fp, cr15, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #20 │ │ mov r4, r0 │ │ ldr r0, [pc, #176] @ (212e948 ) │ │ mov r1, r4 │ │ @@ -268236,15 +268236,15 @@ │ │ moveq r0, #1 │ │ addeq sp, #16 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ ldrh r4, [r0, #38] @ 0x26 │ │ lsls r0, r4, #1 │ │ - movs r1, #162 @ 0xa2 │ │ + movs r1, #207 @ 0xcf │ │ mcr2 2, 0, ip, cr15, cr14, {0} │ │ cdp2 12, 0, cr8, cr14, cr14, {3} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ vpush {d8-d9} │ │ @@ -268488,31 +268488,31 @@ │ │ add r1, pc │ │ b.n 212ebb8 │ │ nop │ │ ldrh r4, [r6, #24] │ │ lsls r0, r4, #1 │ │ adds r7, #243 @ 0xf3 │ │ cdp2 0, 1, cr12, cr1, cr14, {4} │ │ - mcr2 12, 0, r9, cr14, cr1, {4} │ │ + mcr2 12, 0, r9, cr14, cr14, {5} │ │ mcr2 0, 0, ip, cr15, cr3, {6} │ │ mcr2 12, 0, r0, cr14, cr6, {3} │ │ cdp2 7, 1, cr3, cr2, cr1, {2} │ │ - mrc2 14, 0, r9, cr1, cr6, {6} │ │ + cdp2 15, 1, cr9, cr1, cr3, {0} │ │ mcr2 11, 0, pc, cr15, cr6, {0} @ │ │ cdp2 0, 1, cr8, cr0, cr2, {4} │ │ cdp2 2, 0, cr7, cr14, cr14, {1} │ │ - mrc2 5, 0, r5, cr1, cr1, {7} │ │ + mrc2 6, 0, r5, cr1, cr14, {0} │ │ mrc2 6, 0, r3, cr0, cr0, {5} │ │ - cdp2 0, 0, cr6, cr14, cr13, {5} │ │ - mcr2 10, 0, pc, cr15, cr6, {3} @ │ │ - cdp2 15, 0, cr1, cr15, cr0, {1} │ │ - mcr2 15, 0, r1, cr15, cr8, {4} │ │ - mcr2 15, 0, r9, cr15, cr5, {4} │ │ - mcr2 13, 0, r3, cr15, cr11, {2} │ │ - mcr2 15, 0, r1, cr15, cr14, {4} │ │ + mcr2 0, 0, r6, cr14, cr10, {6} │ │ + vseleq.f32 s30, s31, s7 │ │ + cdp2 15, 0, cr1, cr15, cr13, {2} │ │ + cdp2 15, 0, cr1, cr15, cr5, {6} │ │ + cdp2 15, 0, cr9, cr15, cr2, {6} │ │ + vdot.bf16 d3, d31, d8[0] │ │ + cdp2 15, 0, cr1, cr15, cr11, {6} │ │ mcr2 11, 0, r2, cr15, cr10, {5} @ │ │ lsls r7, r3, #1 │ │ ldrh r2, [r5, #18] │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #32 │ │ @@ -268933,37 +268933,37 @@ │ │ mov r3, r1 │ │ bne.n 212f0b2 │ │ b.n 212f090 │ │ nop │ │ cbnz r3, 212f104 │ │ mrc2 14, 0, fp, cr0, cr6, {1} │ │ mcr2 15, 0, r4, cr14, cr8, {7} │ │ - vselvs.f32 s18, s2, s15 │ │ + mrc2 10, 0, r9, cr1, cr4, {2} @ │ │ cdp2 2, 0, cr3, cr15, cr10, {2} │ │ mrc2 5, 0, r3, cr1, cr0, {1} │ │ - cdp2 14, 1, cr5, cr1, cr13, {5} │ │ - cdp2 14, 0, cr5, cr15, cr8, {5} │ │ - mcr2 13, 0, sp, cr15, cr13, {6} │ │ - mcr2 5, 0, pc, cr15, cr14, {7} @ │ │ + mrc2 14, 0, r5, cr1, cr10, {6} │ │ + mcr2 14, 0, r5, cr15, cr5, {6} │ │ + cdp2 14, 0, cr13, cr15, cr10, {0} │ │ + cdp2 6, 0, cr15, cr15, cr11, {1} │ │ cdp2 4, 0, cr3, cr14, cr8, {6} │ │ - mrc2 12, 0, r1, cr1, cr8, {5} │ │ + cdp2 12, 1, cr1, cr1, cr5, {7} │ │ mcr2 7, 0, pc, cr15, cr9, {7} @ │ │ - mrc2 13, 0, sp, cr0, cr14, {2} │ │ - mcr2 12, 0, r9, cr15, cr2, {0} │ │ + cdp2 13, 1, cr13, cr0, cr11, {4} │ │ + mcr2 12, 0, r9, cr15, cr15, {1} │ │ vdot.bf16 d11, d15, d3[0] │ │ cdp2 7, 0, cr15, cr14, cr6, {1} │ │ cdp2 7, 1, cr2, cr0, cr2, {6} │ │ lsls r7, r3, #1 │ │ ldr r5, [pc, #912] @ (212f49c ) │ │ - vselvs.f64 d9, d1, d27 │ │ + mrc2 11, 0, r9, cr1, cr8, {2} @ │ │ mcr2 0, 0, r3, cr15, cr0, {2} │ │ vselvs.f32 s24, s2, s15 │ │ - cdp2 7, 1, cr1, cr1, cr4, {7} │ │ + vfmsl.f16 d1, s2, s2[0] │ │ cdp2 13, 1, cr9, cr0, cr15, {2} │ │ - mcr2 6, 0, pc, cr14, cr2, {1} @ │ │ + mcr2 6, 0, pc, cr14, cr15, {2} @ │ │ mcr2 5, 0, pc, cr15, cr0, {5} @ │ │ ldr r0, [r0, #112] @ 0x70 │ │ blt.n 212f20e │ │ beq.w 212f286 │ │ cmp.w r0, #4096 @ 0x1000 │ │ beq.w 212f280 │ │ cmp.w r0, #8192 @ 0x2000 │ │ @@ -269244,16 +269244,16 @@ │ │ movs r1, #2 │ │ strd r1, r6, [r0] │ │ mov r0, r4 │ │ b.n 212f46e │ │ nop │ │ adds r1, #237 @ 0xed │ │ mrc2 12, 0, r4, cr1, cr4, {2} │ │ - mrc2 7, 0, r3, cr1, cr13, {2} │ │ - mcr2 9, 0, r1, cr15, cr8, {7} @ │ │ + cdp2 7, 1, cr3, cr1, cr10, {4} │ │ + vseleq.f32 s2, s30, s11 │ │ cdp2 12, 0, cr4, cr15, cr0, {2} │ │ mrc2 14, 0, r2, cr1, cr12, {4} │ │ vcmla.f16 d6, d1, d6[0], #90 │ │ mov r0, fp │ │ blx 2704bb0 │ │ add r4, sp, #24 │ │ mov r1, fp │ │ @@ -269367,49 +269367,49 @@ │ │ itt ne │ │ ldrne r0, [sp, #36] @ 0x24 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ adds r1, #132 @ 0x84 │ │ cdp2 4, 1, cr3, cr1, cr13, {2} │ │ @ instruction: 0xfe0eba6a │ │ - @ instruction: 0xfe0e5ae6 │ │ - mcr2 2, 0, pc, cr15, cr14, {2} @ │ │ - cdp2 4, 0, cr15, cr14, cr2, {4} │ │ + mcr2 11, 0, r5, cr14, cr3, {0} @ │ │ + cdp2 2, 0, cr15, cr15, cr11, {4} │ │ + cdp2 4, 0, cr15, cr14, cr15, {5} │ │ mcr2 6, 0, lr, cr15, cr0, {3} │ │ vcmla.f16 q4, , d10[1], #90 │ │ lsls r0, r4, #1 │ │ lsls r0, r3, #25 │ │ - vfmsl.f16 , d2, d6[2] │ │ + vcmla.f16 d9, d18, d3[1], #90 │ │ vseleq.f32 s14, s30, s5 │ │ @ instruction: 0xfe0e6bce │ │ - mrc2 15, 0, r4, cr1, cr1, {4} │ │ + mrc2 15, 0, r4, cr1, cr14, {5} │ │ mrc2 0, 0, r3, cr0, cr0, {2} │ │ - @ instruction: 0xfe0e5a4d │ │ - mcr2 4, 0, pc, cr15, cr6, {0} @ │ │ - vcmla.f16 , , d0[0], #0 │ │ + mcr2 10, 0, r5, cr14, cr10, {3} @ │ │ + cdp2 4, 0, cr15, cr15, cr3, {2} │ │ + vcmla.f16 , , d13[1], #0 │ │ vseleq.f64 d4, d15, d10 │ │ mrc2 13, 0, r2, cr1, cr12, {3} │ │ - mrc2 0, 0, r3, cr1, cr10, {5} │ │ - cdp2 3, 1, cr3, cr0, cr9, {5} │ │ - vcmla.f16 , , d13[0], #0 │ │ + cdp2 0, 1, cr3, cr1, cr7, {7} │ │ + mrc2 3, 0, r3, cr0, cr6, {6} │ │ + vfmal.f16 , d15, d2[3] │ │ cdp2 2, 0, cr3, cr15, cr6, {7} │ │ mcr2 5, 0, fp, cr14, cr10, {1} │ │ mrc2 10, 0, r9, cr0, cr7, {0} @ │ │ - cdp2 0, 0, cr15, cr14, cr2, {7} │ │ - mcr2 7, 0, r1, cr14, cr6, {5} │ │ + cdp2 1, 0, cr15, cr14, cr15, {0} │ │ + cdp2 7, 0, cr1, cr14, cr3, {7} │ │ mcr2 6, 0, sl, cr15, cr8, {7} │ │ - cdp2 1, 1, cr9, cr1, cr6, {7} │ │ - mrc2 6, 0, r9, cr0, cr10, {7} │ │ - vcmla.f16 , , d6[1], #0 │ │ - cdp2 6, 0, cr1, cr15, cr8, {4} │ │ - cdp2 7, 0, cr13, cr15, cr8, {2} │ │ - mcr2 0, 0, r9, cr15, cr8, {6} │ │ - cdp2 5, 1, cr7, cr0, cr8, {7} │ │ + mrc2 2, 0, r9, cr1, cr3, {0} │ │ + cdp2 7, 1, cr9, cr0, cr7, {1} │ │ + vfmal.f16 d5, s31, s6[0] │ │ + mcr2 6, 0, r1, cr15, cr5, {5} │ │ + mcr2 7, 0, sp, cr15, cr5, {3} │ │ + cdp2 1, 0, cr9, cr15, cr5, {0} │ │ + mrc2 6, 0, r7, cr0, cr5, {0} │ │ cdp2 12, 0, cr8, cr15, cr11, {4} │ │ - vfmsl.f16 d9, s3, s13[1] │ │ + vcmla.f16 , , d11[1], #90 │ │ cdp2 0, 0, cr8, cr15, cr4, {7} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ sub sp, #16 │ │ mov r4, r0 │ │ @@ -269537,17 +269537,17 @@ │ │ blx 2704db0 │ │ b.n 212f6fe │ │ nop │ │ strh r2, [r1, #0] │ │ lsls r0, r4, #1 │ │ add r4, pc, #712 @ (adr r4, 212fa20 ) │ │ mrc2 5, 0, fp, cr1, cr10, {2} │ │ - mcr2 4, 0, r9, cr14, cr1, {4} │ │ + mcr2 4, 0, r9, cr14, cr14, {5} │ │ mcr2 0, 0, pc, cr15, cr9, {1} @ │ │ - cdp2 1, 1, cr1, cr0, cr5, {3} │ │ + mrc2 1, 0, r1, cr0, cr2, {4} │ │ cdp2 15, 1, cr4, cr0, cr12, {1} │ │ cdp2 15, 0, cr7, cr14, cr10, {1} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ mov r4, r0 │ │ @@ -269886,15 +269886,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #8] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ ldrb r0, [r5, #18] │ │ lsls r0, r4, #1 │ │ - ldc 14, cr15, [ip, #-60] @ 0xffffffc4 │ │ + stcl 14, cr15, [r9, #-60] @ 0xffffffc4 │ │ sxth r0, r0 │ │ cdp2 0, 0, cr9, cr14, cr14, {6} │ │ mcr2 11, 0, r7, cr14, cr0, {4} @ │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -270154,23 +270154,23 @@ │ │ movs r1, #8 │ │ b.n 212fdc2 │ │ movs r1, #9 │ │ b.n 212fdc2 │ │ cmp r3, #25 │ │ cdp2 0, 0, cr11, cr14, cr10, {4} │ │ mcr2 13, 0, pc, cr14, cr3, {1} @ │ │ - cdp2 0, 1, cr1, cr1, cr5, {0} │ │ + mrc2 0, 0, r1, cr1, cr2, {1} │ │ mcr2 13, 0, sp, cr15, cr8, {6} │ │ mrc2 1, 0, r4, cr1, cr5, {4} │ │ - cdp2 5, 1, cr2, cr1, cr6, {3} │ │ - cdp2 5, 1, cr2, cr0, cr11, {2} │ │ + mrc2 5, 0, r2, cr1, cr3, {4} │ │ + mrc2 5, 0, r2, cr0, cr8, {3} │ │ cdp2 2, 1, cr8, cr0, cr4, {2} │ │ - cdp2 4, 1, cr2, cr1, cr14, {4} │ │ - cdp2 12, 1, cr12, cr0, cr6, {6} │ │ - mcr2 9, 0, r0, cr15, cr12, {1} @ │ │ + mrc2 4, 0, r2, cr1, cr11, {5} │ │ + mrc2 12, 0, ip, cr0, cr3, {7} │ │ + @ instruction: 0xfe0f0969 │ │ vcmla.f16 d15, d16, d10[1], #90 │ │ cdp2 1, 1, cr2, cr1, cr10, {0} │ │ ldrb.w r0, [sp, #48] @ 0x30 │ │ mov r4, r1 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #56] @ 0x38 │ │ @@ -270421,24 +270421,24 @@ │ │ strh r1, [r0, #4] │ │ subs r3, #128 @ 0x80 │ │ movs r0, r0 │ │ movs r0, r0 │ │ ldc2l 3, cr4, [r1, #-508]! @ 0xfffffe04 │ │ ldrb r4, [r6, #12] │ │ lsls r0, r4, #1 │ │ - add r2, sp, #336 @ 0x150 │ │ - mcr2 4, 0, r2, cr15, cr8, {3} │ │ + add r2, sp, #516 @ 0x204 │ │ + cdp2 4, 0, cr2, cr15, cr5, {5} │ │ vcmla.f16 d10, d0, d10[1], #90 │ │ - vfmsl.f16 d8, s0, s2[1] │ │ + vcmla.f16 q4, q0, d6[0], #90 │ │ mrc2 3, 0, r8, cr0, cr10, {6} │ │ vfmsl.f16 d7, s2, s5[1] │ │ lsls r0, r4, #1 │ │ movs r7, #249 @ 0xf9 │ │ - cdp2 12, 0, cr6, cr14, cr14, {5} │ │ - cdp2 7, 0, cr0, cr15, cr15, {6} │ │ + mcr2 12, 0, r6, cr14, cr11, {6} │ │ + mcr2 7, 0, r0, cr15, cr12, {7} │ │ cdp2 5, 0, cr7, cr15, cr4, {7} │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ mov r4, r0 │ │ ldr r0, [pc, #112] @ (213015c ) │ │ @@ -270486,15 +270486,15 @@ │ │ ittt eq │ │ moveq r0, #0 │ │ addeq sp, #16 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ strb r0, [r0, #21] │ │ lsls r0, r4, #1 │ │ - lsls r3, r1, #28 │ │ + lsls r0, r7, #28 │ │ mrc2 10, 0, sl, cr0, cr10, {4} @ │ │ cdp2 4, 0, cr7, cr14, cr4, {7} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #72 @ 0x48 │ │ @@ -270560,17 +270560,17 @@ │ │ addeq sp, #72 @ 0x48 │ │ ldreq.w fp, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ strb r0, [r6, #18] │ │ lsls r0, r4, #1 │ │ - str r1, [r5, #8] │ │ + str r6, [r2, #12] │ │ vselvs.f32 s20, s0, s20 │ │ - cdp2 5, 0, cr14, cr14, cr15, {0} │ │ + mcr2 5, 0, lr, cr14, cr12, {1} │ │ mcr2 4, 0, r7, cr15, cr2, {1} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ sub sp, #16 │ │ mov r9, r0 │ │ @@ -270836,15 +270836,15 @@ │ │ blx 26ffb50 │ │ add r0, sp, #12 │ │ blx 2703810 │ │ blx 26ffb60 │ │ nop │ │ strb r4, [r1, #8] │ │ lsls r0, r4, #1 │ │ - b.n 212fe82 │ │ + b.n 212fedc │ │ cdp2 7, 0, cr10, cr14, cr6, {3} │ │ cdp2 1, 0, cr7, cr14, cr0, {4} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #40 @ 0x28 │ │ mov r4, r0 │ │ @@ -270917,15 +270917,15 @@ │ │ blx 26ffb50 │ │ add r0, sp, #12 │ │ blx 2703810 │ │ blx 26ffb60 │ │ nop │ │ strb r4, [r0, #5] │ │ lsls r0, r4, #1 │ │ - stmia r7!, {r1, r2, r6} │ │ + stmia r7!, {r0, r1, r4, r5, r6} │ │ mcr2 6, 0, sl, cr15, cr14, {4} │ │ mcr2 0, 0, r7, cr14, cr8, {5} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #40 @ 0x28 │ │ mov r4, r0 │ │ @@ -271032,15 +271032,15 @@ │ │ b.n 21306a8 │ │ add r0, sp, #8 │ │ blx 2703810 │ │ blx 26ffb60 │ │ nop │ │ strb r4, [r7, #1] │ │ lsls r0, r4, #1 │ │ - b.n 2130da8 │ │ + b.n 2130e02 │ │ mcr2 5, 0, sl, cr14, cr6, {6} │ │ @ instruction: 0xfe0eb941 │ │ mrc2 15, 0, r6, cr1, cr10, {4} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #40 @ 0x28 │ │ @@ -271238,15 +271238,15 @@ │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ ldr r0, [r6, #96] @ 0x60 │ │ lsls r0, r4, #1 │ │ bl 21d34de >, std::__ndk1::__unordered_map_hasher >, celestia::util::PathHasher, std::__ndk1::equal_to, true>, std::__ndk1::__unordered_map_equal >, std::__ndk1::equal_to, celestia::util::PathHasher, true>, std::__ndk1::allocator > > >::__do_rehash(unsigned int)@@Base+0x4> │ │ add r3, pc, #552 @ (adr r3, 2130ae8 ) │ │ - mcr2 4, 0, r4, cr14, cr13, {4} │ │ + cdp2 4, 0, cr4, cr14, cr10, {6} │ │ mcr2 13, 0, r6, cr15, cr0, {4} │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #72] @ (213091c ) │ │ @@ -271516,19 +271516,19 @@ │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ ldr r4, [r7, #60] @ 0x3c │ │ lsls r0, r4, #1 │ │ strb r7, [r7, #30] │ │ mrc2 1, 0, sl, cr1, cr6, {2} │ │ mcr2 1, 0, sl, cr14, cr15, {5} │ │ - mcr2 12, 0, fp, cr14, cr4, {5} │ │ + cdp2 12, 0, cr11, cr14, cr1, {7} │ │ mcr2 10, 0, r6, cr14, cr12, {7} @ │ │ lsls r0, r4, #1 │ │ add r1, pc, #668 @ (adr r1, 2130e24 ) │ │ - mcr2 11, 0, pc, cr14, cr3, {5} @ │ │ + @ instruction: 0xfe0efbe0 │ │ mcr2 5, 0, fp, cr14, cr0, {6} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ mov r4, r0 │ │ ldr r0, [pc, #180] @ (2130c4c ) │ │ mov r1, r4 │ │ add r0, pc │ │ @@ -271599,15 +271599,15 @@ │ │ cmp r2, r1 │ │ itt eq │ │ addeq sp, #16 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ ldr r4, [r2, #40] @ 0x28 │ │ lsls r0, r4, #1 │ │ - adds r2, r0, #4 │ │ + adds r7, r5, #4 │ │ cdp2 15, 0, cr9, cr15, cr14, {7} │ │ mcr2 9, 0, r6, cr14, cr2, {7} @ │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ mov r4, r0 │ │ @@ -271661,15 +271661,15 @@ │ │ cmp r2, r1 │ │ itt eq │ │ addeq sp, #16 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ ldr r4, [r0, #28] │ │ lsls r0, r4, #1 │ │ - ldrb r5, [r4, #6] │ │ + ldrb r2, [r2, #7] │ │ mrc2 15, 0, r9, cr0, cr14, {0} │ │ mcr2 9, 0, r6, cr14, cr10, {2} @ │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ mov r4, r0 │ │ @@ -271723,15 +271723,15 @@ │ │ cmp r2, r1 │ │ itt eq │ │ addeq sp, #16 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ ldr r4, [r5, #16] │ │ lsls r0, r4, #1 │ │ - subs r2, r3, r6 │ │ + subs r7, r0, r7 │ │ cdp2 14, 0, cr9, cr15, cr6, {4} │ │ vcmla.f16 q3, q15, d2[0], #0 │ │ lsls r0, r4, #1 │ │ │ │ 02130d8c : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ @@ -271814,24 +271814,24 @@ │ │ blx 26ffb50 │ │ ldr r4, [r2, #8] │ │ lsls r0, r4, #1 │ │ ldr r2, [r0, #8] │ │ lsls r0, r4, #1 │ │ ldr r4, [sp, #92] @ 0x5c │ │ cdp2 0, 0, cr7, cr14, cr14, {7} │ │ - mrc2 12, 0, r7, cr1, cr15, {6} │ │ + cdp2 13, 1, cr7, cr1, cr12, {0} │ │ cdp2 0, 0, cr0, cr15, cr1, {4} │ │ movs r0, r0 │ │ - bvc.n 2130e84 │ │ + bvc.n 2130ede │ │ cdp2 4, 0, cr0, cr14, cr7, {4} │ │ movs r0, r0 │ │ bl 1fe2a94 │ │ lsls r5, r5, #21 │ │ movs r0, r0 │ │ - strb r7, [r3, #30] │ │ + strb r4, [r1, #31] │ │ cdp2 6, 1, cr0, cr0, cr7, {1} │ │ movs r0, r0 │ │ str r6, [r5, #124] @ 0x7c │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -272185,32 +272185,32 @@ │ │ b.n 2130f64 │ │ nop │ │ ldc2l 3, cr4, [r1, #-508]! @ 0xfffffe04 │ │ movs r0, r0 │ │ movs r0, r0 │ │ str r2, [r2, #120] @ 0x78 │ │ lsls r0, r4, #1 │ │ - strb r2, [r4, #30] │ │ + strb r7, [r1, #31] │ │ cdp2 4, 1, cr11, cr0, cr14, {6} │ │ cdp2 12, 1, cr9, cr0, cr0, {7} │ │ mcr2 5, 0, fp, cr14, cr7, {1} │ │ @ instruction: 0xfe108be2 │ │ cdp2 13, 1, cr9, cr1, cr12, {1} │ │ cdp2 7, 0, cr3, cr14, cr1, {0} │ │ - mcr2 9, 0, r1, cr14, cr4, {4} @ │ │ + @ instruction: 0xfe0e19c1 │ │ cdp2 7, 0, cr1, cr15, cr12, {1} │ │ - mcr2 12, 0, pc, cr14, cr7, {2} @ │ │ + cdp2 12, 0, cr15, cr14, cr4, {4} │ │ cdp2 3, 0, cr7, cr14, cr11, {1} │ │ cdp2 0, 1, cr7, cr1, cr8, {0} │ │ mrc2 0, 0, r7, cr1, cr3, {4} │ │ - vselvs.f64 d5, d1, d0 │ │ - mcr2 9, 0, r5, cr15, cr14, {1} @ │ │ - vcmla.f16 d1, d31, d7[0], #0 │ │ - vfmal.f16 , d15, d7[2] │ │ - cdp2 6, 0, cr13, cr15, cr6, {2} │ │ + vselvs.f64 d5, d1, d29 │ │ + @ instruction: 0xfe0f596b │ │ + vfmal.f16 d1, s31, s9[0] │ │ + vcmla.f16 d1, d31, d4[1], #0 │ │ + mcr2 6, 0, sp, cr15, cr3, {3} │ │ mcr2 6, 0, r6, cr14, cr14, {5} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #16 │ │ mov r1, r0 │ │ @@ -272295,16 +272295,16 @@ │ │ ittt eq │ │ addeq sp, #16 │ │ ldreq.w fp, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ str r6, [r0, #56] @ 0x38 │ │ lsls r0, r4, #1 │ │ - cmp r4, #20 │ │ - cdp2 5, 1, cr11, cr0, cr14, {0} │ │ + cmp r4, #65 @ 0x41 │ │ + mrc2 5, 0, fp, cr0, cr11, {1} │ │ mcr2 4, 0, r6, cr14, cr0, {1} │ │ lsls r0, r4, #1 │ │ str r4, [r5, #88] @ 0x58 │ │ lsls r0, r4, #1 │ │ str r6, [r1, #44] @ 0x2c │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ @@ -272379,16 +272379,16 @@ │ │ blx 26ffb50 │ │ ldr r0, [sp, #0] │ │ movs r1, #0 │ │ b.n 2131414 │ │ nop │ │ str r2, [r2, #40] @ 0x28 │ │ lsls r0, r4, #1 │ │ - cmp r3, #32 │ │ - mrc2 4, 0, fp, cr0, cr6, {1} │ │ + cmp r3, #77 @ 0x4d │ │ + cdp2 4, 1, cr11, cr0, cr3, {3} │ │ mcr2 3, 0, r6, cr14, cr2, {1} │ │ lsls r0, r4, #1 │ │ bl 2259070 │ │ str r6, [r1, #32] │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -272462,16 +272462,16 @@ │ │ blx 26ffb50 │ │ ldr r0, [sp, #0] │ │ movs r1, #0 │ │ b.n 21314dc │ │ nop │ │ str r2, [r1, #28] │ │ lsls r0, r4, #1 │ │ - cmp r2, #88 @ 0x58 │ │ - cdp2 3, 1, cr11, cr0, cr14, {3} │ │ + cmp r2, #133 @ 0x85 │ │ + mrc2 3, 0, fp, cr0, cr11, {4} │ │ cdp2 2, 0, cr6, cr14, cr10, {3} │ │ lsls r0, r4, #1 │ │ bl 2191138 const&, double, double, Eigen::Matrix const*, double, double, double, Eigen::Matrix const&, double, double) const@@Base+0x7ec> │ │ str r6, [r0, #20] │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -272821,15 +272821,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #28] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ ldrsh r4, [r2, r0] │ │ lsls r0, r4, #1 │ │ - strh r3, [r1, r4] │ │ + strh r0, [r7, r4] │ │ vdot.bf16 d5, d31, d0[1] │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #48 @ 0x30 │ │ mov r4, r0 │ │ @@ -272932,15 +272932,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #28] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ ldrb r4, [r2, r5] │ │ lsls r0, r4, #1 │ │ - ldr r4, [r7, #76] @ 0x4c │ │ + ldr r1, [r5, #80] @ 0x50 │ │ cdp2 12, 1, cr5, cr0, cr6, {3} │ │ lsls r0, r4, #1 │ │ │ │ 021319fc const&)@@Base>: │ │ vmov.f32 s0, #112 @ 0x3f800000 1.0 │ │ vldr s2, [r1] │ │ vldr s6, [r1, #8] │ │ @@ -273457,142 +273457,142 @@ │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ ldr r2, [r2, r7] │ │ lsls r0, r4, #1 │ │ ldr r5, [sp, #788] @ 0x314 │ │ cdp2 3, 1, cr0, cr1, cr3, {5} │ │ movs r0, r0 │ │ - ldr r6, [pc, #976] @ (21322b0 ) │ │ + ldr r7, [pc, #132] @ (2131f64 ) │ │ cdp2 3, 0, cr0, cr15, cr9, {5} │ │ movs r0, r0 │ │ - ldrd pc, lr, [fp, #-60]! @ 0x3c │ │ + @ instruction: 0xe9a8fe0f │ │ lsls r3, r5, #16 │ │ movs r0, r0 │ │ - movs r5, #97 @ 0x61 │ │ + movs r5, #142 @ 0x8e │ │ mrc2 15, 0, r6, cr0, cr15, {1} │ │ @ instruction: 0xfe0e0a6b │ │ movs r0, r0 │ │ lsrs r3, r1, #7 │ │ mcr2 11, 0, r0, cr14, cr1, {7} @ │ │ movs r0, r0 │ │ movs r4, #5 │ │ mrc2 12, 0, r0, cr1, cr15, {5} │ │ movs r0, r0 │ │ - add r7, sp, #636 @ 0x27c │ │ + add r7, sp, #816 @ 0x330 │ │ mcr2 13, 0, r0, cr15, cr5, {6} │ │ movs r0, r0 │ │ - add r7, sp, #628 @ 0x274 │ │ + add r7, sp, #808 @ 0x328 │ │ mcr2 14, 0, r0, cr15, cr3, {3} │ │ movs r0, r0 │ │ str r2, [r7, #24] │ │ mrc2 14, 0, r0, cr1, cr9, {5} │ │ movs r0, r0 │ │ cmp r1, #82 @ 0x52 │ │ cdp2 15, 0, cr0, cr14, cr3, {1} │ │ movs r0, r0 │ │ movs r0, #122 @ 0x7a │ │ cdp2 2, 1, cr1, cr1, cr13, {1} │ │ movs r0, r0 │ │ - add r7, sp, #448 @ 0x1c0 │ │ + add r7, sp, #628 @ 0x274 │ │ mcr2 2, 0, r1, cr15, cr7, {4} │ │ movs r0, r0 │ │ - lsls r3, r6, #25 │ │ + lsls r0, r4, #26 │ │ mrc2 2, 0, r1, cr0, cr9, {7} │ │ movs r0, r0 │ │ lsrs r2, r3, #5 │ │ cdp2 3, 0, cr1, cr14, cr3, {3} │ │ movs r0, r0 │ │ - add r7, sp, #340 @ 0x154 │ │ + add r7, sp, #520 @ 0x208 │ │ cdp2 3, 0, cr1, cr15, cr5, {7} │ │ movs r0, r0 │ │ - cmp r7, #206 @ 0xce │ │ + cmp r7, #251 @ 0xfb │ │ mcr2 4, 0, r1, cr15, cr15, {1} │ │ movs r0, r0 │ │ add r4, pc, #720 @ (adr r4, 213222c ) │ │ cdp2 4, 1, cr1, cr0, cr9, {7} │ │ movs r0, r0 │ │ - ldr r6, [r1, #56] @ 0x38 │ │ + ldr r3, [r7, #56] @ 0x38 │ │ cdp2 5, 0, cr1, cr15, cr3, {4} │ │ movs r0, r0 │ │ - lsls r5, r5, #15 │ │ + lsls r2, r3, #16 │ │ cdp2 6, 1, cr1, cr0, cr5, {1} │ │ movs r0, r0 │ │ - ldmia r1, {r0, r1, r3, r7} │ │ + ldmia r1!, {r3, r4, r5, r7} │ │ cdp2 6, 0, cr1, cr15, cr15, {5} │ │ movs r0, r0 │ │ - stmia r5!, {r0, r1, r3, r6, r7} │ │ + stmia r5!, {r3, r4, r5, r6, r7} │ │ mcr2 7, 0, r1, cr15, cr9, {1} │ │ movs r0, r0 │ │ - ldrh r1, [r4, #12] │ │ + ldrh r6, [r1, #14] │ │ cdp2 7, 0, cr1, cr15, cr3, {5} │ │ movs r0, r0 │ │ stmia r5!, {r0, r2, r3, r5} │ │ vcmla.f16 d1, d0, d13[0], #90 │ │ movs r0, r0 │ │ - stmia r5!, {r1, r6, r7} │ │ + stmia r5!, {r0, r1, r2, r3, r5, r6, r7} │ │ vfmal.f16 , d15, d7[2] │ │ movs r0, r0 │ │ - add r5, pc, #460 @ (adr r5, 2132168 ) │ │ + add r5, pc, #640 @ (adr r5, 213221c ) │ │ vcmla.f16 , q15, d1[1], #0 │ │ movs r0, r0 │ │ - ldmia r3, {r0, r1, r2, r3, r7} │ │ + ldmia r3, {r2, r3, r4, r5, r7} │ │ mcr2 9, 0, r1, cr14, cr11, {2} @ │ │ movs r0, r0 │ │ - lsrs r7, r0, #12 │ │ + lsrs r4, r6, #12 │ │ mcr2 9, 0, r1, cr15, cr1, {5} @ │ │ movs r0, r0 │ │ - ldr r3, [r7, #80] @ 0x50 │ │ + ldr r0, [r5, #84] @ 0x54 │ │ vseleq.f32 s2, s30, s14 │ │ movs r0, r0 │ │ - str r2, [r2, #80] @ 0x50 │ │ + str r7, [r7, #80] @ 0x50 │ │ vselvs.f32 s2, s1, s3 │ │ movs r0, r0 │ │ ldr r4, [sp, #176] @ 0xb0 │ │ mrc2 11, 0, r1, cr1, cr11, {5} @ │ │ movs r0, r0 │ │ subs r7, #214 @ 0xd6 │ │ cdp2 12, 1, cr1, cr1, cr13, {0} │ │ movs r0, r0 │ │ ldrh r5, [r0, #50] @ 0x32 │ │ cdp2 12, 0, cr1, cr14, cr3, {3} │ │ movs r0, r0 │ │ - movs r0, #115 @ 0x73 │ │ + movs r0, #160 @ 0xa0 │ │ mrc2 12, 0, r1, cr0, cr9, {5} │ │ movs r0, r0 │ │ - stmia r6!, {r0, r1, r3} │ │ + stmia r6!, {r3, r4, r5} │ │ mcr2 13, 0, r1, cr14, cr11, {4} │ │ movs r0, r0 │ │ lsls r1, r1, #7 │ │ mrc2 14, 0, r1, cr1, cr5, {4} │ │ movs r0, r0 │ │ b.n 213252a │ │ mrc2 14, 0, r1, cr0, cr3, {7} │ │ movs r0, r0 │ │ - ldr r6, [r0, #76] @ 0x4c │ │ + ldr r3, [r6, #76] @ 0x4c │ │ mcr2 15, 0, r1, cr15, cr1, {2} │ │ movs r0, r0 │ │ movs r7, #209 @ 0xd1 │ │ cdp2 15, 0, cr1, cr14, cr15, {5} │ │ movs r0, r0 │ │ lsls r0, r0, #19 │ │ mrc2 0, 0, r2, cr1, cr13, {6} │ │ movs r0, r0 │ │ - lsrs r4, r3, #9 │ │ + lsrs r1, r1, #10 │ │ cdp2 3, 0, cr2, cr15, cr11, {2} │ │ movs r0, r0 │ │ ldrsb r2, [r6, r5] │ │ lsls r0, r4, #1 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r1, [pc, #8] @ (213202c ) │ │ add r1, pc │ │ blx 2704bb0 │ │ movs r0, #1 │ │ pop {r7, pc} │ │ - @ instruction: 0xeb94fe0e │ │ + @ instruction: 0xebc1fe0e │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #16 │ │ mov r4, r0 │ │ ldr r0, [pc, #112] @ (21320b0 ) │ │ mov r1, r4 │ │ @@ -273641,15 +273641,15 @@ │ │ addeq sp, #16 │ │ ldreq.w fp, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ strb r4, [r5, r7] │ │ lsls r0, r4, #1 │ │ - lsrs r1, r6, #2 │ │ + lsrs r6, r3, #3 │ │ mcr2 5, 0, r5, cr15, cr6, {4} │ │ lsls r0, r4, #1 │ │ bmi.n 2132068 │ │ bmi.n 213206a │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -274055,18 +274055,18 @@ │ │ bne.n 2132584 │ │ ldr r1, [pc, #412] @ (2132704 ) │ │ add r0, sp, #60 @ 0x3c │ │ add r1, pc │ │ blx 2704bc0 │ │ b.n 2132698 │ │ nop │ │ - add r1, pc, #764 @ (adr r1, 2132874 ) │ │ - cdp2 4, 0, cr14, cr14, cr11, {0} │ │ - vcmla.f16 d14, d14, d5[0], #0 │ │ - mcr2 7, 0, r6, cr14, cr15, {0} │ │ + add r1, pc, #944 @ (adr r1, 2132928 ) │ │ + mcr2 4, 0, lr, cr14, cr8, {1} │ │ + vfmal.f16 d14, s28, s5[0] │ │ + cdp2 7, 0, cr6, cr14, cr12, {2} │ │ cdp2 6, 0, cr9, cr15, cr14, {0} │ │ vmov.f64 d16, #20 @ 0x40a00000 5.0 │ │ str r0, [sp, #44] @ 0x2c │ │ add r4, sp, #60 @ 0x3c │ │ ldr r3, [pc, #376] @ (2132708 ) │ │ movs r1, #3 │ │ mov r0, r4 │ │ @@ -274173,39 +274173,39 @@ │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ b.n 21326c2 │ │ add r0, sp, #80 @ 0x50 │ │ bl 20958dc │ │ blx 26ffb60 │ │ - str r3, [r5, #56] @ 0x38 │ │ + str r0, [r3, #60] @ 0x3c │ │ cdp2 0, 1, cr0, cr0, cr0, {0} │ │ movs r0, r0 │ │ movs r0, r0 │ │ subs r7, #208 @ 0xd0 │ │ movs r0, r0 │ │ movs r0, r0 │ │ movs r0, r0 │ │ subs r7, #232 @ 0xe8 │ │ ldr r1, [sp, #616] @ 0x268 │ │ ldr r1, [sp, #612] @ 0x264 │ │ ldr r1, [sp, #612] @ 0x264 │ │ subs r7, #185 @ 0xb9 │ │ strb r4, [r1, r5] │ │ lsls r0, r4, #1 │ │ - add r1, sp, #360 @ 0x168 │ │ + add r1, sp, #540 @ 0x21c │ │ mcr2 15, 0, pc, cr15, cr11, {6} @ │ │ - mrc2 2, 0, lr, cr0, cr5, {6} │ │ + cdp2 3, 1, cr14, cr0, cr2, {0} │ │ mcr2 13, 0, r1, cr14, cr2, {0} │ │ - vselvs.f16 s4, s2, s31 │ │ + mrc2 9, 0, r2, cr1, cr12, {2} @ │ │ mcr2 0, 0, lr, cr15, cr3, {0} │ │ - mrc2 4, 0, r8, cr0, cr12, {2} │ │ - cdp2 1, 0, cr12, cr15, cr13, {4} │ │ + cdp2 4, 1, cr8, cr0, cr9, {4} │ │ + mcr2 1, 0, ip, cr15, cr10, {5} │ │ mcr2 6, 0, r8, cr15, cr8, {6} │ │ - cdp2 1, 0, cr12, cr14, cr8, {5} │ │ + mcr2 1, 0, ip, cr14, cr5, {6} │ │ mcr2 1, 0, ip, cr15, cr2, {0} │ │ mrc2 15, 0, r4, cr0, cr0, {4} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ @@ -274340,21 +274340,21 @@ │ │ itt eq │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ ldr r6, [pc, #992] @ (2132c70 ) │ │ lsls r0, r4, #1 │ │ - b.n 2132186 │ │ + b.n 21321e0 │ │ vseleq.f64 d15, d14, d18 │ │ - cdp2 0, 1, cr14, cr0, cr7, {6} │ │ + mrc2 0, 0, lr, cr0, cr4, {7} │ │ mcr2 1, 0, sp, cr15, cr0, {3} │ │ - cdp2 15, 1, cr5, cr1, cr4, {1} │ │ + mrc2 15, 0, r5, cr1, cr1, {2} │ │ mrc2 9, 0, r1, cr0, cr13, {1} @ │ │ - cdp2 15, 1, cr11, cr1, cr10, {1} │ │ + mrc2 15, 0, fp, cr1, cr7, {2} │ │ vdot.bf16 q2, , d2[0] │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ vpush {d8} │ │ sub sp, #64 @ 0x40 │ │ @@ -274536,17 +274536,17 @@ │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ ldr r4, [pc, #568] @ (2132cd0 ) │ │ lsls r0, r4, #1 │ │ stc2l 14, cr15, [r9], #52 @ 0x34 │ │ - pop {r3, r4, r6, pc} │ │ - cdp2 0, 0, cr8, cr15, cr2, {1} │ │ - vseleq.f16 s30, s31, s25 │ │ + pop {r0, r2, r7, pc} │ │ + cdp2 0, 0, cr8, cr15, cr15, {2} │ │ + mcr2 9, 0, pc, cr15, cr9, {6} @ │ │ mcr2 14, 0, r7, cr15, cr5, {1} │ │ mrc2 11, 0, r4, cr0, cr2, {5} @ │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #16 │ │ @@ -274607,17 +274607,17 @@ │ │ addeq sp, #16 │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ ldr r3, [pc, #424] @ (2132cf4 ) │ │ lsls r0, r4, #1 │ │ - ldr r5, [sp, #340] @ 0x154 │ │ + ldr r5, [sp, #520] @ 0x208 │ │ mcr2 14, 0, ip, cr14, cr12, {0} │ │ - mrc2 1, 0, sl, cr1, cr11, {5} │ │ + cdp2 1, 1, cr10, cr1, cr8, {7} │ │ mcr2 10, 0, r4, cr15, cr14, {7} @ │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #60] @ (2132ba4 ) │ │ @@ -274645,15 +274645,15 @@ │ │ ittt eq │ │ moveq r0, #0 │ │ addeq sp, #8 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ ldr r2, [pc, #784] @ (2132eb8 ) │ │ lsls r0, r4, #1 │ │ - ldrt pc, [lr, #15] │ │ + strb.w pc, [fp, #3599] @ 0xe0f │ │ ldr r2, [pc, #624] @ (2132e20 ) │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #92] @ (2132c18 ) │ │ @@ -274695,15 +274695,15 @@ │ │ moveq r0, #0 │ │ addeq sp, #8 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ ldr r2, [pc, #440] @ (2132dd4 ) │ │ lsls r0, r4, #1 │ │ - asrs r2, r7, #24 │ │ + asrs r7, r4, #25 │ │ cdp2 15, 1, cr6, cr0, cr2, {1} │ │ vselvs.f32 s8, s2, s21 │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ @@ -274956,16 +274956,16 @@ │ │ ldr r7, [pc, #124] @ (2132fa0 ) │ │ lsrs r7, r7, #13 │ │ adcs r2, r4 │ │ ldr r1, [pc, #920] @ (21332c4 ) │ │ lsls r0, r4, #1 │ │ hlt 0x0018 │ │ vcmla.f16 , q0, d3[0], #90 │ │ - @ instruction: 0xfe0dfbee │ │ - mcr2 12, 0, r3, cr14, cr4, {7} │ │ + mcr2 12, 0, pc, cr13, cr11, {0} @ │ │ + vdot.bf16 d3, d14, d1[1] │ │ mcr2 7, 0, r4, cr15, cr6, {1} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #92] @ (2132fa8 ) │ │ @@ -275007,16 +275007,16 @@ │ │ moveq r0, #0 │ │ addeq sp, #8 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ mov lr, fp │ │ lsls r0, r4, #1 │ │ - ldr r0, [sp, #1020] @ 0x3fc │ │ - mcr2 9, 0, fp, cr14, cr8, {7} @ │ │ + ldr r1, [sp, #176] @ 0xb0 │ │ + vseleq.f32 s22, s28, s11 │ │ mcr2 6, 0, r4, cr14, cr10, {4} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #64 @ 0x40 │ │ mov r4, sp │ │ bfc r4, #0, #4 │ │ @@ -275203,15 +275203,15 @@ │ │ moveq r0, #1 │ │ addeq sp, #8 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ add r8, lr │ │ lsls r0, r4, #1 │ │ - @ instruction: 0xb6a2 │ │ + @ instruction: 0xb6cf │ │ mcr2 4, 0, r4, cr15, cr6, {5} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ mov r4, r0 │ │ ldr r0, [pc, #156] @ (2133240 ) │ │ @@ -275274,15 +275274,15 @@ │ │ subs r6, #242 @ 0xf2 │ │ strb r5, [r4, #13] │ │ subs r0, #45 @ 0x2d │ │ stmia r1!, {r1, r4, r6} │ │ ands r0, r0 │ │ add lr, r0 │ │ lsls r0, r4, #1 │ │ - bvs.n 21331b2 │ │ + bvs.n 213320c │ │ mcr2 11, 0, sl, cr15, cr4, {4} @ │ │ mrc2 4, 0, r4, cr1, cr2, {0} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #48 @ 0x30 │ │ mov r4, sp │ │ @@ -275339,15 +275339,15 @@ │ │ moveq sp, r4 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ mvns r6, r0 │ │ lsls r0, r4, #1 │ │ bl 2267f10 │ │ - strb r3, [r6, #29] │ │ + strb r0, [r4, #30] │ │ mcr2 3, 0, r4, cr15, cr14, {2} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #48 @ 0x30 │ │ mov r4, sp │ │ bfc r4, #0, #4 │ │ @@ -275406,15 +275406,15 @@ │ │ moveq sp, r4 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ orrs r6, r3 │ │ lsls r0, r4, #1 │ │ bl 21e0fc0 const&, Eigen::Quaternion const&)@@Base+0x1f0> │ │ - adds r4, r7, r7 │ │ + subs r1, r5, r0 │ │ cdp2 2, 0, cr4, cr15, cr14, {5} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ mov r4, r0 │ │ ldr r0, [pc, #120] @ (213342c ) │ │ @@ -275531,15 +275531,15 @@ │ │ addeq sp, #16 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ rors r6, r3 │ │ lsls r0, r4, #1 │ │ str r0, [sp, #40] @ 0x28 │ │ - vcmla.f16 , q0, d3[0], #90 │ │ + vfmsl.f16 , d0, d0[2] │ │ mcr2 2, 0, r1, cr15, cr9, {0} │ │ mcr2 1, 0, r4, cr14, cr14, {3} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r4, r0 │ │ @@ -275583,15 +275583,15 @@ │ │ addeq sp, #8 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ adcs r6, r0 │ │ lsls r0, r4, #1 │ │ ldr r7, [r7, r2] │ │ - mcr2 2, 0, fp, cr14, cr12, {7} │ │ + cdp2 3, 0, cr11, cr14, cr9, {1} │ │ cdp2 1, 0, cr4, cr15, cr2, {0} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #92] @ (21335b8 ) │ │ @@ -275633,16 +275633,16 @@ │ │ moveq r0, #0 │ │ addeq sp, #8 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ lsrs r6, r1 │ │ lsls r0, r4, #1 │ │ - lsrs r3, r7, #18 │ │ - cdp2 6, 1, cr13, cr0, cr0, {3} │ │ + lsrs r0, r5, #19 │ │ + cdp2 6, 1, cr13, cr0, cr13, {4} │ │ cdp2 0, 0, cr4, cr14, cr10, {4} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #92] @ (2133630 ) │ │ @@ -275735,15 +275735,15 @@ │ │ moveq r0, #0 │ │ addeq sp, #8 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ subs r7, #222 @ 0xde │ │ lsls r0, r4, #1 │ │ - lsrs r2, r7, #15 │ │ + lsrs r7, r4, #16 │ │ cdp2 6, 1, cr3, cr0, cr7, {6} │ │ mcr2 15, 0, r3, cr14, cr10, {4} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ mov r5, r0 │ │ @@ -275792,15 +275792,15 @@ │ │ ittt eq │ │ moveq r0, #0 │ │ addeq sp, #16 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ subs r7, #104 @ 0x68 │ │ lsls r0, r4, #1 │ │ - lsrs r4, r5, #14 │ │ + lsrs r1, r3, #15 │ │ mrc2 12, 0, lr, cr0, cr13, {6} │ │ mrc2 15, 0, r3, cr0, cr0, {0} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ mov r4, r0 │ │ @@ -276056,18 +276056,18 @@ │ │ mov r0, r5 │ │ blx 27010d0 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ subs r5, #106 @ 0x6a │ │ lsls r0, r4, #1 │ │ - lsrs r7, r2, #7 │ │ + lsrs r4, r0, #8 │ │ cdp2 0, 1, cr4, cr0, cr2, {3} │ │ lsls r0, r4, #1 │ │ - add r6, sp, #824 @ 0x338 │ │ + add r6, sp, #1004 @ 0x3ec │ │ cdp2 12, 0, cr3, cr15, cr0, {5} │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #72] @ (2133a2c ) │ │ @@ -276100,15 +276100,15 @@ │ │ moveq r0, #1 │ │ addeq sp, #8 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ subs r4, #72 @ 0x48 │ │ lsls r0, r4, #1 │ │ - add r7, sp, #764 @ 0x2fc │ │ + add r7, sp, #944 @ 0x3b0 │ │ mcr2 12, 0, r3, cr14, cr6, {0} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #56 @ 0x38 │ │ mov r4, r0 │ │ ldr r0, [pc, #76] @ (2133a90 ) │ │ @@ -276143,15 +276143,15 @@ │ │ ittt eq │ │ moveq r0, #1 │ │ addeq sp, #56 @ 0x38 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ subs r3, #230 @ 0xe6 │ │ lsls r0, r4, #1 │ │ - adds r1, #92 @ 0x5c │ │ + adds r1, #137 @ 0x89 │ │ mcr2 11, 0, r3, cr15, cr0, {5} @ │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #76] @ (2133af4 ) │ │ @@ -276186,15 +276186,15 @@ │ │ ittt eq │ │ moveq r0, #1 │ │ addeq sp, #8 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ subs r3, #132 @ 0x84 │ │ lsls r0, r4, #1 │ │ - ldr r2, [r5, #120] @ 0x78 │ │ + ldr r7, [r2, #124] @ 0x7c │ │ @ instruction: 0xfe0f3b4c │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ sub sp, #24 │ │ mov r4, r0 │ │ @@ -276278,15 +276278,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #12] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ subs r3, #28 │ │ lsls r0, r4, #1 │ │ - cdp 14, 5, cr15, cr2, cr14, {0} │ │ + cdp 14, 7, cr15, cr15, cr14, {0} │ │ subs r2, #126 @ 0x7e │ │ lsls r0, r4, #1 │ │ bmi.n 2133b98 │ │ bmi.n 2133b9a │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -276382,15 +276382,15 @@ │ │ ldmia r4!, {r2, r3, r6, r7} │ │ subs r7, #236 @ 0xec │ │ subs r2, #42 @ 0x2a │ │ lsls r0, r4, #1 │ │ ldr r0, [r0, #76] @ 0x4c │ │ mrc2 12, 0, r6, cr0, cr9, {6} │ │ cdp2 13, 1, cr9, cr0, cr4, {4} │ │ - mrc2 12, 0, ip, cr1, cr14, {1} │ │ + cdp2 12, 1, cr12, cr1, cr11, {3} │ │ mcr2 9, 0, r3, cr15, cr4, {3} @ │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #84] @ (2133d58 ) │ │ @@ -276520,15 +276520,15 @@ │ │ ittt eq │ │ moveq r0, #0 │ │ addeq sp, #8 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ subs r0, #78 @ 0x4e │ │ lsls r0, r4, #1 │ │ - movs r4, #121 @ 0x79 │ │ + movs r4, #166 @ 0xa6 │ │ vfmsl.f16 d3, s0, s0[0] │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #20 │ │ mov r4, r0 │ │ @@ -276642,15 +276642,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #8] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ adds r7, #220 @ 0xdc │ │ lsls r0, r4, #1 │ │ - b.n 2133aba │ │ + b.n 2133b14 │ │ cdp2 6, 0, cr3, cr15, cr14, {7} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #92 @ 0x5c │ │ mov r4, r0 │ │ @@ -276875,22 +276875,22 @@ │ │ itt ne │ │ ldrne r0, [sp, #64] @ 0x40 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ adds r6, #164 @ 0xa4 │ │ lsls r0, r4, #1 │ │ - @ instruction: 0xea09fe0e │ │ - b.n 2134742 │ │ + @ instruction: 0xea36fe0e │ │ + b.n 213479c │ │ mcr2 9, 0, fp, cr15, cr7, {4} @ │ │ mrc2 4, 0, r8, cr1, cr7, {0} │ │ mrc2 5, 0, r3, cr0, cr12, {5} │ │ lsls r0, r4, #1 │ │ - add r4, pc, #664 @ (adr r4, 2134484 , 3, 3>::run >(Eigen::QuaternionBase >&, Eigen::Matrix const&)@@Base+0x17c>) │ │ - mcr2 4, 0, sl, cr14, cr14, {3} │ │ + add r4, pc, #844 @ (adr r4, 2134538 const&)@@Base+0xc>) │ │ + cdp2 4, 0, cr10, cr14, cr11, {5} │ │ cdp2 4, 0, cr3, cr14, cr12, {4} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #16 │ │ mov r4, r0 │ │ @@ -276998,15 +276998,15 @@ │ │ itt eq │ │ addeq sp, #16 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ adds r3, #144 @ 0x90 │ │ lsls r0, r4, #1 │ │ - lsrs r7, r2, #9 │ │ + lsrs r4, r0, #10 │ │ cdp2 3, 0, cr3, cr15, cr4, {2} │ │ lsls r0, r4, #1 │ │ │ │ 02134308 , 3, 3>::run >(Eigen::QuaternionBase >&, Eigen::Matrix const&)@@Base>: │ │ vldr s4, [r1, #16] │ │ vldr s0, [r1, #32] │ │ vldr s2, [r1] │ │ @@ -277304,30 +277304,30 @@ │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ adds r0, #138 @ 0x8a │ │ lsls r0, r4, #1 │ │ strb r5, [r7, #17] │ │ mrc2 0, 0, r0, cr1, cr7, {5} │ │ movs r0, r0 │ │ - subs r7, #183 @ 0xb7 │ │ + subs r7, #228 @ 0xe4 │ │ mrc2 0, 0, r0, cr0, cr13, {5} │ │ movs r0, r0 │ │ - cmp r7, lr │ │ + cmp ip, r4 │ │ cdp2 1, 0, cr0, cr15, cr11, {5} │ │ movs r0, r0 │ │ bgt.n 2134588 const&)@@Base+0x5c> │ │ cdp2 2, 1, cr0, cr0, cr9, {4} │ │ movs r0, r0 │ │ - add sp, fp │ │ + cmp r2, r1 │ │ mcr2 3, 0, r0, cr15, cr7, {6} │ │ movs r0, r0 │ │ asrs r2, r7, #31 │ │ cdp2 4, 1, cr0, cr1, cr1, {7} │ │ movs r0, r0 │ │ - strh r4, [r7, #50] @ 0x32 │ │ + strh r1, [r5, #52] @ 0x34 │ │ cdp2 6, 0, cr0, cr15, cr11, {2} │ │ movs r0, r0 │ │ adds r0, #6 │ │ lsls r0, r4, #1 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r1, [pc, #8] @ (2134688 ) │ │ @@ -277426,17 +277426,17 @@ │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ mov r0, sp │ │ bl 2134e14 │ │ blx 26ffb60 │ │ cmp r7, #148 @ 0x94 │ │ lsls r0, r4, #1 │ │ - pld [r2, #15] │ │ - lsls r1, r0, #28 │ │ - cdp2 6, 0, cr0, cr15, cr1, {4} │ │ + pldw [pc, #-3599] @ 213396d │ │ + lsls r6, r5, #28 │ │ + cdp2 6, 0, cr0, cr15, cr14, {5} │ │ mcr2 14, 0, r2, cr15, cr6, {6} │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #48 @ 0x30 │ │ mov r4, r0 │ │ ldr r0, [pc, #204] @ (2134860 ) │ │ @@ -277519,16 +277519,16 @@ │ │ add r0, sp, #32 │ │ bl 2134e14 │ │ blx 26ffb60 │ │ nop │ │ cmp r6, #152 @ 0x98 │ │ lsls r0, r4, #1 │ │ sxth r7, r1 │ │ - cdp2 7, 1, cr15, cr1, cr10, {0} │ │ - mcr2 5, 0, r0, cr15, cr9, {7} │ │ + mrc2 7, 0, pc, cr1, cr7, {1} │ │ + cdp2 6, 0, cr0, cr15, cr6, {1} │ │ vdot.bf16 q1, , d12[1] │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #48 @ 0x30 │ │ mov r4, r0 │ │ ldr r0, [pc, #316] @ (21349bc ) │ │ @@ -277654,16 +277654,16 @@ │ │ bl 2134ec0 * CelxLua::safeGetClass >(int, FatalErrors, char const*)@@Base+0x70> │ │ add r0, sp, #32 │ │ bl 2134e14 │ │ blx 26ffb60 │ │ cmp r5, #172 @ 0xac │ │ lsls r0, r4, #1 │ │ str r3, [r7, #68] @ 0x44 │ │ - mcr2 6, 0, pc, cr14, cr14, {0} @ │ │ - cdp2 5, 0, cr0, cr15, cr13, {0} │ │ + cdp2 6, 0, cr15, cr14, cr11, {2} │ │ + mcr2 5, 0, r0, cr15, cr10, {1} │ │ mcr2 12, 0, r2, cr15, cr12, {4} │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #40 @ 0x28 │ │ mov r4, r0 │ │ ldr r0, [pc, #244] @ (2134ad0 ) │ │ @@ -277762,16 +277762,16 @@ │ │ add r0, sp, #20 │ │ bl 2134e14 │ │ blx 26ffb60 │ │ nop │ │ cmp r4, #80 @ 0x50 │ │ lsls r0, r4, #1 │ │ strb r1, [r7, #22] │ │ - cdp2 4, 1, cr15, cr1, cr2, {6} │ │ - mcr2 3, 0, r0, cr15, cr1, {5} │ │ + cdp2 4, 1, cr15, cr1, cr15, {7} │ │ + mcr2 3, 0, r0, cr15, cr14, {6} │ │ vseleq.f64 d2, d31, d4 │ │ lsls r0, r4, #1 │ │ bmi.n 2134a90 │ │ bmi.n 2134a92 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ vpush {d8-d10} │ │ @@ -277899,16 +277899,16 @@ │ │ ldr r0, [r5, #116] @ 0x74 │ │ ldrh r1, [r7, #0] │ │ ldrsh r7, [r4, r6] │ │ subs r6, #124 @ 0x7c │ │ cmp r3, #52 @ 0x34 │ │ lsls r0, r4, #1 │ │ asrs r7, r5, #13 │ │ - cdp2 3, 1, cr15, cr1, cr6, {5} │ │ - mcr2 2, 0, r0, cr15, cr5, {4} │ │ + mrc2 3, 0, pc, cr1, cr3, {6} │ │ + cdp2 2, 0, cr0, cr15, cr2, {6} │ │ mcr2 5, 0, pc, cr15, cr13, {7} @ │ │ mrc2 10, 0, r2, cr0, cr6, {0} @ │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #136 @ 0x88 │ │ @@ -278050,16 +278050,16 @@ │ │ b.n 2134df2 │ │ add r0, sp, #20 │ │ bl 2134e14 │ │ blx 26ffb60 │ │ cmp r1, #180 @ 0xb4 │ │ lsls r0, r4, #1 │ │ cbnz r0, 2134e22 │ │ - cdp2 2, 1, cr15, cr0, cr6, {1} │ │ - mcr2 1, 0, r0, cr15, cr5, {0} │ │ + mrc2 2, 0, pc, cr0, cr3, {2} │ │ + cdp2 1, 0, cr0, cr15, cr2, {2} │ │ cdp2 0, 0, cr2, cr15, cr8, {5} │ │ vfmal.f16 q1, d14, d2[1] │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ ldr r4, [r0, #4] │ │ cbz r4, 2134e4c │ │ @@ -278347,30 +278347,30 @@ │ │ movs r0, r0 │ │ str r7, [sp, #364] @ 0x16c │ │ mrc2 2, 0, r0, cr0, cr15, {3} │ │ movs r0, r0 │ │ ldr r3, [pc, #320] @ (21351f8 ) │ │ mrc2 3, 0, r0, cr1, cr13, {4} │ │ movs r0, r0 │ │ - asrs r2, r2, #10 │ │ + asrs r7, r7, #10 │ │ mrc2 5, 0, r0, cr0, cr7, {5} │ │ movs r0, r0 │ │ ldr r3, [pc, #264] @ (21351d0 ) │ │ mrc2 6, 0, r0, cr1, cr5, {7} │ │ movs r0, r0 │ │ - ldr r1, [sp, #740] @ 0x2e4 │ │ + ldr r1, [sp, #920] @ 0x398 │ │ vfmal.f16 d0, s29, s7[1] │ │ movs r0, r0 │ │ ldr r1, [pc, #672] @ (2135378 ) │ │ vselvs.f32 s0, s3, s19 │ │ movs r0, r0 │ │ subs r5, #159 @ 0x9f │ │ cdp2 12, 0, cr0, cr14, cr3, {0} │ │ movs r0, r0 │ │ - bls.n 2134ffa │ │ + bls.n 2135054 │ │ vdot.bf16 d0, d30, d9[0] │ │ movs r0, r0 │ │ push {r0, r1, r4, r6, r7, lr} │ │ cdp2 14, 1, cr0, cr0, cr3, {0} │ │ movs r0, r0 │ │ bcc.n 2135062 │ │ mrc2 14, 0, r0, cr0, cr13, {3} │ │ @@ -278795,15 +278795,15 @@ │ │ nop │ │ str r5, [r0, #28] │ │ ldr r7, [pc, #124] @ (2135628 ) │ │ lsrs r7, r7, #13 │ │ adcs r2, r4 │ │ movs r2, #116 @ 0x74 │ │ lsls r0, r4, #1 │ │ - push {r1, lr} │ │ + push {r0, r1, r2, r3, r5, lr} │ │ cdp2 7, 0, cr5, cr15, cr10, {6} │ │ mcr2 4, 0, sl, cr14, cr7, {3} │ │ vfmsl.f16 d8, s2, s10[0] │ │ cdp2 0, 1, cr2, cr1, cr4, {5} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -278916,15 +278916,15 @@ │ │ addeq sp, #4 │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ it eq │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ movs r0, #78 @ 0x4e │ │ lsls r0, r4, #1 │ │ - adds r1, #3 │ │ + adds r1, #48 @ 0x30 │ │ mrc2 4, 0, r5, cr0, cr2, {7} │ │ mcr2 14, 0, r6, cr14, cr10, {6} │ │ cdp2 15, 1, cr1, cr0, cr10, {2} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -279083,15 +279083,15 @@ │ │ itt eq │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ subs r2, r0, #4 │ │ lsls r0, r4, #1 │ │ - ldmia r5, {r0, r1, r2, r4, r5} │ │ + ldmia r5, {r2, r5, r6} │ │ vfmal.f16 q7, d31, d0[1] │ │ mrc2 13, 0, r1, cr0, cr6, {3} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ @@ -279265,15 +279265,15 @@ │ │ itt eq │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ adds r6, r5, #4 │ │ lsls r0, r4, #1 │ │ str r5, [r6, r0] │ │ - cdp2 13, 1, cr6, cr0, cr0, {7} │ │ + cdp2 14, 1, cr6, cr0, cr13, {0} │ │ mcr2 11, 0, r1, cr14, cr8, {3} @ │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #28 │ │ mov sl, r0 │ │ @@ -279407,15 +279407,15 @@ │ │ blx 26ffb60 │ │ nop │ │ subs r0, r7, r4 │ │ lsls r0, r4, #1 │ │ movs r7, #231 @ 0xe7 │ │ cdp2 0, 1, cr5, cr1, cr14, {4} │ │ mcr2 11, 0, ip, cr14, cr1, {6} @ │ │ - cdp2 15, 0, cr2, cr13, cr2, {4} │ │ + cdp2 15, 0, cr2, cr13, cr15, {5} │ │ vseleq.f32 s2, s30, s13 │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ sub sp, #48 @ 0x30 │ │ mov r4, r0 │ │ @@ -279730,15 +279730,15 @@ │ │ moveq r0, #1 │ │ addeq sp, #16 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ asrs r0, r6, #28 │ │ lsls r0, r4, #1 │ │ - ldmia r2!, {r4, r6, r7} │ │ + ldmia r2, {r0, r2, r3, r4, r5, r6, r7} │ │ cdp2 12, 0, cr4, cr14, cr10, {4} │ │ mcr2 6, 0, r1, cr14, cr10, {6} │ │ lsls r0, r4, #1 │ │ │ │ 02135f78 , 3, 3>::run >(Eigen::QuaternionBase >&, Eigen::Matrix const&)@@Base>: │ │ vldr d18, [r1, #32] │ │ vldr d16, [r1, #64] @ 0x40 │ │ @@ -280014,27 +280014,27 @@ │ │ itt eq │ │ addeq sp, #8 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ asrs r6, r5, #17 │ │ lsls r0, r4, #1 │ │ - ldmia r0!, {r1, r4, r5} │ │ + ldmia r0, {r0, r1, r2, r3, r4, r6} │ │ mcr2 0, 0, r0, cr14, cr11, {7} │ │ movs r0, r0 │ │ lsrs r7, r0, #16 │ │ mcr2 1, 0, r0, cr14, cr5, {3} │ │ movs r0, r0 │ │ add r4, pc, #444 @ (adr r4, 2136454 ) │ │ mrc2 1, 0, r0, cr0, cr3, {7} │ │ movs r0, r0 │ │ - cmp r1, #125 @ 0x7d │ │ + cmp r1, #170 @ 0xaa │ │ cdp2 3, 0, cr0, cr15, cr1, {1} │ │ movs r0, r0 │ │ - add r2, sp, #132 @ 0x84 │ │ + add r2, sp, #312 @ 0x138 │ │ mcr2 4, 0, r0, cr14, cr3, {1} │ │ movs r0, r0 │ │ ldr r3, [r3, r0] │ │ cdp2 6, 1, cr0, cr1, cr5, {1} │ │ movs r0, r0 │ │ subs r1, #48 @ 0x30 │ │ mrc2 6, 0, r0, cr1, cr15, {2} │ │ @@ -280357,18 +280357,18 @@ │ │ moveq r0, #0 │ │ addeq sp, #40 @ 0x28 │ │ vpopeq {d8-d10} │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ asrs r4, r6, #3 │ │ lsls r0, r4, #1 │ │ - movs r1, #215 @ 0xd7 │ │ + movs r2, #4 │ │ vfmsl.f16 q1, d0, d0[3] │ │ - mcr2 7, 0, r6, cr14, cr6, {0} │ │ - vcmla.f16 q7, , d9[0], #0 │ │ + cdp2 7, 0, cr6, cr14, cr3, {2} │ │ + vfmal.f16 q7, d15, d6[2] │ │ mcr2 0, 0, r1, cr14, cr8, {0} │ │ lsls r0, r4, #1 │ │ bmi.n 21365f0 │ │ bmi.n 21365f2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -280527,18 +280527,18 @@ │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ @ instruction: 0xfffeffff │ │ vqrdmlsh.s , , d31[0] │ │ lsrs r6, r1, #31 │ │ lsls r0, r4, #1 │ │ - add r2, pc, #568 @ (adr r2, 2136a70 ) │ │ + add r2, pc, #748 @ (adr r2, 2136b24 ) │ │ mcr2 7, 0, r2, cr15, cr2, {2} │ │ cdp2 7, 0, cr15, cr14, cr9, {1} │ │ - cdp2 3, 1, cr8, cr0, cr3, {1} │ │ + mrc2 3, 0, r8, cr0, cr0, {2} │ │ cdp2 14, 0, cr0, cr14, cr4, {1} │ │ lsls r0, r4, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #48] @ (2136884 ) │ │ @@ -280562,15 +280562,15 @@ │ │ ittt eq │ │ moveq r0, #1 │ │ addeq sp, #8 │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ lsrs r0, r3, #23 │ │ lsls r0, r4, #1 │ │ - asr.w lr, r2, pc @ │ │ + ror.w lr, pc, pc │ │ lsrs r4, r7, #22 │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ vpush {d8-d15} │ │ sub sp, #16 │ │ mov r4, r0 │ │ @@ -280641,15 +280641,15 @@ │ │ moveq r0, #1 │ │ addeq sp, #16 │ │ vpopeq {d8-d15} │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ lsrs r4, r1, #22 │ │ lsls r0, r4, #1 │ │ - subs r2, r4, #2 │ │ + subs r7, r1, #3 │ │ cdp2 14, 1, cr7, cr0, cr0, {3} │ │ mrc2 12, 0, r0, cr0, cr0, {7} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ vpush {d8-d15} │ │ @@ -280971,18 +280971,18 @@ │ │ cmp r5, #0 │ │ itt ne │ │ ldrne r0, [sp, #12] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ lsrs r4, r2, #10 │ │ lsls r0, r4, #1 │ │ - str r2, [r4, #24] │ │ + str r7, [r1, #28] │ │ mcr2 2, 0, r2, cr15, cr4, {0} │ │ vseleq.f32 s10, s28, s5 │ │ - mrc2 14, 0, r1, cr0, cr8, {6} │ │ + cdp2 15, 1, cr1, cr0, cr5, {0} │ │ mcr2 9, 0, r0, cr15, cr8, {3} @ │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ vpush {d8-d11} │ │ sub sp, #32 │ │ @@ -281124,15 +281124,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ lsrs r0, r4, #4 │ │ lsls r0, r4, #1 │ │ - str r6, [r5, #0] │ │ + str r3, [r3, #4] │ │ cdp2 0, 0, cr2, cr15, cr0, {5} │ │ vcmla.f16 d5, d30, d14[1], #0 │ │ mrc2 0, 0, r2, cr0, cr7, {2} │ │ mcr2 7, 0, r5, cr14, cr14, {7} │ │ mrc2 7, 0, r0, cr0, cr6, {7} │ │ lsls r0, r4, #1 │ │ │ │ @@ -281323,54 +281323,54 @@ │ │ lsls r0, r4, #1 │ │ ldr r2, [pc, #708] @ (2137318 ) │ │ cdp2 1, 1, cr0, cr1, cr7, {1} │ │ movs r0, r0 │ │ cmp r3, #198 @ 0xc6 │ │ cdp2 1, 1, cr0, cr1, cr13, {1} │ │ movs r0, r0 │ │ - ldrb r5, [r7, #8] │ │ + ldrb r2, [r5, #9] │ │ mcr2 2, 0, r0, cr14, cr7, {5} │ │ movs r0, r0 │ │ push {r1, r2, r4, r5, r6} │ │ cdp2 3, 1, cr0, cr0, cr1, {2} │ │ movs r0, r0 │ │ strb r4, [r7, #30] │ │ cdp2 5, 1, cr0, cr0, cr11, {1} │ │ movs r0, r0 │ │ cmp r2, #16 │ │ mrc2 5, 0, r0, cr1, cr9, {6} │ │ movs r0, r0 │ │ subs r7, r0, #0 │ │ mcr2 7, 0, r0, cr14, cr3, {1} │ │ movs r0, r0 │ │ - cbnz r1, 21370c8 │ │ + rev r6, r3 │ │ vcmla.f16 d0, d30, d1[0], #0 │ │ movs r0, r0 │ │ str r6, [sp, #236] @ 0xec │ │ vfmsl.f16 q0, d16, d3[3] │ │ movs r0, r0 │ │ push {r0, r2, r3, r4} │ │ mrc2 9, 0, r0, cr0, cr5, {3} @ │ │ movs r0, r0 │ │ - udf #3 │ │ + udf #48 @ 0x30 │ │ @ instruction: 0xfe0e09ef │ │ movs r0, r0 │ │ subs r1, #121 @ 0x79 │ │ vselvs.f32 s0, s1, s11 │ │ movs r0, r0 │ │ lsls r4, r6, #23 │ │ lsls r0, r4, #1 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r1, [pc, #8] @ (21370c4 ) │ │ add r1, pc │ │ blx 2704bb0 │ │ movs r0, #1 │ │ pop {r7, pc} │ │ - ldrsb r2, [r5, r7] │ │ + ldr r7, [r2, r0] │ │ mcr2 5, 0, fp, cr14, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8-d11} │ │ sub sp, #136 @ 0x88 │ │ mov r1, r0 │ │ @@ -281506,16 +281506,16 @@ │ │ itt eq │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ lsls r6, r1, #21 │ │ lsls r0, r4, #1 │ │ - cbz r3, 21372b8 │ │ - vfmal.f16 , d15, d1[2] │ │ + cbz r0, 21372c4 │ │ + vfmal.f16 d3, s31, s12[1] │ │ mcr2 3, 0, r0, cr15, cr14, {7} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #40 @ 0x28 │ │ mov r1, r0 │ │ ldr r0, [pc, #124] @ (21372e8 ) │ │ @@ -281567,15 +281567,15 @@ │ │ moveq r0, #1 │ │ addeq sp, #40 @ 0x28 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ lsls r0, r0, #15 │ │ lsls r0, r4, #1 │ │ - subs r0, #42 @ 0x2a │ │ + subs r0, #87 @ 0x57 │ │ mcr2 4, 0, r7, cr15, cr14, {6} │ │ mrc2 3, 0, r0, cr0, cr10, {2} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ vpush {d8} │ │ @@ -281745,15 +281745,15 @@ │ │ itt eq │ │ ldreq.w fp, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ lsls r6, r2, #12 │ │ lsls r0, r4, #1 │ │ bmi.n 2137542 │ │ - mcr2 3, 0, r5, cr13, cr9, {7} │ │ + cdp2 4, 0, cr5, cr13, cr6, {1} │ │ cdp2 1, 0, cr0, cr14, cr14, {3} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #40 @ 0x28 │ │ mov r1, r0 │ │ ldr r0, [pc, #160] @ (213759c ) │ │ @@ -281817,15 +281817,15 @@ │ │ addeq sp, #40 @ 0x28 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ lsls r0, r6, #4 │ │ lsls r0, r4, #1 │ │ bcs.n 2137632 │ │ - mcr2 3, 0, r5, cr13, cr1, {1} │ │ + mcr2 3, 0, r5, cr13, cr14, {2} │ │ cdp2 0, 0, cr0, cr14, cr6, {5} │ │ lsls r0, r4, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #28 │ │ mov r9, r0 │ │ @@ -281957,15 +281957,15 @@ │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ lsls r0, r6, #1 │ │ lsls r0, r4, #1 │ │ strht pc, [r2, #13] │ │ adds r1, r5, r0 │ │ mcr2 0, 0, r5, cr14, cr13, {0} │ │ - mrc2 4, 0, r1, cr0, cr6, {5} │ │ + cdp2 4, 1, cr1, cr0, cr3, {7} │ │ mcr2 15, 0, pc, cr15, cr12, {2} @ │ │ lsls r7, r3, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ sub sp, #32 │ │ mov r4, r0 │ │ @@ -282090,15 +282090,15 @@ │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ vqadd.u8 q0, q4, │ │ bl 1ff2476 │ │ asrs r1, r0, #27 │ │ mcr2 14, 0, r4, cr14, cr5, {5} │ │ - cdp2 4, 1, cr15, cr0, cr6, {1} │ │ + mrc2 4, 0, pc, cr0, cr3, {2} │ │ cdp2 14, 0, cr4, cr14, cr11, {1} │ │ cdp2 14, 1, cr15, cr0, cr10, {0} │ │ lsls r7, r3, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ mov r4, r0 │ │ @@ -282198,15 +282198,15 @@ │ │ ittt eq │ │ moveq r0, #1 │ │ addeq sp, #16 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ stc2 0, cr0, [r8, #-380]! @ 0xfffffe84 │ │ - asrs r4, r6, #9 │ │ + asrs r1, r4, #10 │ │ cdp2 4, 0, cr1, cr15, cr5, {7} │ │ mcr2 12, 0, pc, cr14, cr2, {6} @ │ │ lsls r7, r3, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ mov r4, r0 │ │ @@ -282323,15 +282323,15 @@ │ │ cmp r1, r0 │ │ ittt eq │ │ moveq r0, #1 │ │ addeq sp, #40 @ 0x28 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ ldc2 0, cr0, [r8], {95} @ 0x5f │ │ - ldmia r0, {r0, r1, r4, r5, r7} │ │ + ldmia r0!, {r5, r6, r7} │ │ mcr2 3, 0, r1, cr15, cr3, {6} │ │ vseleq.f64 d15, d30, d4 │ │ lsls r7, r3, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ mov r4, r0 │ │ @@ -283504,15 +283504,15 @@ │ │ asrs r6, r2, #17 │ │ cdp2 6, 1, cr1, cr2, cr2, {5} │ │ mrc2 6, 0, r1, cr2, cr14, {3} │ │ cdp2 6, 1, cr1, cr2, cr14, {3} │ │ mrc2 3, 0, pc, cr2, cr14, {3} │ │ lsls r7, r3, #1 │ │ subs r1, #247 @ 0xf7 │ │ - mrc2 3, 0, r8, cr1, cr10, {0} │ │ + cdp2 3, 1, cr8, cr1, cr7, {2} │ │ mcr2 1, 0, ip, cr15, cr12, {2} │ │ cdp2 4, 0, cr1, cr13, cr4, {5} │ │ mrc2 4, 0, r1, cr1, cr12, {4} │ │ vcmla.f16 d5, d17, d0[1], #90 │ │ lsls r2, r4, #1 │ │ ldr r0, [r4, r2] │ │ lsls r2, r4, #1 │ │ @@ -284019,16 +284019,16 @@ │ │ ldrb.w r0, [sp, #16] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #24] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ eors.w r0, r8, pc, lsr #1 │ │ - adds r7, #158 @ 0x9e │ │ - cdp2 7, 0, cr5, cr14, cr1, {7} │ │ + adds r7, #203 @ 0xcb │ │ + vcmla.f16 d5, d14, d14[0], #0 │ │ vseleq.f16 s28, s29, s21 │ │ lsls r7, r3, #1 │ │ │ │ 02138ce8 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -284247,16 +284247,16 @@ │ │ str r4, [r4, r2] │ │ vselvs.f16 s28, s2, s25 │ │ lsls r7, r3, #1 │ │ b.n 2138f00 │ │ lsls r7, r3, #1 │ │ b.n 2138e28 │ │ lsls r7, r3, #1 │ │ - bl 1eceb52 │ │ - bmi.n 2138eb6 │ │ + bl 1efbb52 │ │ + bmi.n 2138f10 │ │ Address 0x2138f36 is out of bounds. │ │ │ │ │ │ 02138f38 : │ │ mov r2, r1 │ │ ldrd r1, r0, [r0, #4] │ │ b.w 26ff044 │ │ @@ -284680,15 +284680,15 @@ │ │ cmp r0, #0 │ │ beq.n 2139366 │ │ b.n 2139420 │ │ nop │ │ ldrh r0, [r0, #24] │ │ cdp2 6, 1, cr14, cr1, cr12, {3} │ │ lsls r7, r3, #1 │ │ - str r0, [sp, #88] @ 0x58 │ │ + str r0, [sp, #268] @ 0x10c │ │ cdp2 1, 0, cr15, cr15, cr6, {6} │ │ b.n 2138e32 │ │ ldr r1, [r0, #8] │ │ cmp r1, #4 │ │ blt.n 21393b6 │ │ ldr r1, [pc, #472] @ (2139568 ) │ │ add r1, pc │ │ @@ -284863,23 +284863,23 @@ │ │ blx 26ffb60 │ │ ldr r1, [sp, #616] @ 0x268 │ │ ldr r1, [sp, #612] @ 0x264 │ │ ldr r1, [sp, #612] @ 0x264 │ │ subs r7, #185 @ 0xb9 │ │ b.n 2139234 │ │ lsls r7, r3, #1 │ │ - ldr r2, [r7, r0] │ │ + ldr r7, [r4, r1] │ │ cdp2 3, 0, cr14, cr14, cr14, {3} │ │ lsls r7, r3, #1 │ │ lsrs r0, r0, #4 │ │ vcmla.f16 q0, , d14[1], #90 │ │ - vselvs.f16 s30, s2, s4 │ │ - mcr2 7, 0, r1, cr14, cr4, {1} │ │ - cdp2 7, 0, cr1, cr15, cr2, {1} │ │ - mcr2 14, 0, ip, cr15, cr11, {7} │ │ + vselvs.f16 s30, s2, s31 │ │ + cdp2 7, 0, cr1, cr14, cr1, {3} │ │ + cdp2 7, 0, cr1, cr15, cr15, {2} │ │ + cdp2 15, 0, cr12, cr15, cr8, {1} │ │ cdp2 6, 0, cr14, cr15, cr10, {2} │ │ lsls r7, r3, #1 │ │ b.n 213989c │ │ lsls r7, r3, #1 │ │ │ │ 0213957c : │ │ b.w 26fe954 │ │ @@ -285093,15 +285093,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #24] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ b.n 2139808 │ │ lsls r7, r3, #1 │ │ - strh r5, [r0, r6] │ │ + strh r2, [r6, r6] │ │ cdp2 14, 0, cr13, cr14, cr10, {7} │ │ lsls r7, r3, #1 │ │ │ │ 021397a8 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -285235,15 +285235,15 @@ │ │ beq.n 2139908 │ │ ldr r0, [sp, #4] │ │ ldr r0, [r0, #8] │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ udf #116 @ 0x74 │ │ lsls r7, r3, #1 │ │ - add r3, sp, #160 @ 0xa0 │ │ + add r3, sp, #340 @ 0x154 │ │ mcr2 13, 0, sp, cr15, cr12, {3} │ │ lsls r7, r3, #1 │ │ │ │ 02139918 , std::__ndk1::allocator >::__count_unique(std::__ndk1::__fs::filesystem::path const&) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -287790,16 +287790,16 @@ │ │ blx 26ffb40 │ │ add r0, sp, #52 @ 0x34 │ │ bl 213b38c │ │ blx 26ffb60 │ │ nop │ │ ldmia r1!, {r2, r3, r5} │ │ lsls r7, r3, #1 │ │ - asrs r4, r4, #24 │ │ - cdp2 6, 0, cr1, cr14, cr2, {0} │ │ + asrs r1, r2, #25 │ │ + cdp2 6, 0, cr1, cr14, cr15, {1} │ │ cdp2 3, 0, cr12, cr14, cr4, {0} │ │ lsls r7, r3, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ ldr r5, [r0, #0] │ │ mov r4, r0 │ │ @@ -292313,16 +292313,16 @@ │ │ b.n 213e428 │ │ add r0, sp, #20 │ │ bl 213d654 │ │ blx 26ffb60 │ │ nop │ │ str r4, [sp, #384] @ 0x180 │ │ lsls r7, r3, #1 │ │ - ldrh r4, [r2, #4] │ │ - vfmal.f16 q4, d14, d2[2] │ │ + ldrh r1, [r0, #6] │ │ + vfmal.f16 d8, s29, s14[1] │ │ mcr2 2, 0, r9, cr14, cr0, {1} │ │ lsls r7, r3, #1 │ │ │ │ 0213e444 : │ │ bx lr │ │ │ │ 0213e446 : │ │ @@ -295880,26 +295880,26 @@ │ │ mov r0, r5 │ │ blx r1 │ │ blx 26ffb60 │ │ nop │ │ ldr r6, [r2, #76] @ 0x4c │ │ lsls r7, r3, #1 │ │ udf #35 @ 0x23 │ │ - cdp2 3, 0, cr12, cr15, cr15, {6} │ │ + mcr2 3, 0, ip, cr15, cr12, {7} │ │ mcr2 14, 0, r0, cr14, cr4, {4} │ │ lsls r6, r3, #1 │ │ lsrs r4, r1, #24 │ │ lsls r6, r3, #1 │ │ add r3, pc, #824 @ (adr r3, 2140e78 >&, std::__ndk1::function)@@Base+0x2d4>) │ │ cdp2 14, 0, cr0, cr13, cr10, {3} │ │ lsls r6, r3, #1 │ │ lsrs r2, r7, #24 │ │ lsls r6, r3, #1 │ │ - cdp2 14, 9, cr15, cr9, cr14, {0} │ │ - cdp2 14, 7, cr15, cr9, cr14, {0} │ │ + cdp2 14, 12, cr15, cr6, cr14, {0} │ │ + cdp2 14, 10, cr15, cr6, cr14, {0} │ │ str r1, [sp, #736] @ 0x2e0 │ │ @ instruction: 0xfe106b46 │ │ lsls r7, r3, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ ldr r5, [r0, #0] │ │ @@ -296361,27 +296361,27 @@ │ │ strb r0, [r2, #2] │ │ ldr r0, [sp, #48] @ 0x30 │ │ strh r1, [r2, #0] │ │ strb.w sl, [sp, #72] @ 0x48 │ │ strd r6, r0, [sp, #76] @ 0x4c │ │ ldr r6, [sp, #36] @ 0x24 │ │ b.n 21410de >&, std::__ndk1::function)@@Base+0x53a> │ │ - ldc2 14, cr15, [r9], #56 @ 0x38 │ │ + stc2l 14, cr15, [r6], #56 @ 0x38 │ │ lsrs r2, r5, #14 │ │ lsls r6, r3, #1 │ │ - asrs r7, r5, #30 │ │ - mcr2 14, 0, r7, cr15, cr8, {6} │ │ + asrs r4, r3, #31 │ │ + cdp2 15, 0, cr7, cr15, cr5, {0} │ │ cdp2 12, 0, cr9, cr14, cr13, {5} │ │ - mcr2 12, 0, sp, cr15, cr15, {0} │ │ + cdp2 12, 0, cr13, cr15, cr12, {2} │ │ mcr2 9, 0, sp, cr13, cr10, {2} @ │ │ mcr2 14, 0, r9, cr15, cr5, {7} │ │ mcr2 15, 0, ip, cr13, cr8, {1} │ │ mrc2 7, 0, fp, cr0, cr15, {4} │ │ mcr2 3, 0, r3, cr15, cr8, {0} │ │ - mrc2 12, 0, r7, cr0, cr14, {7} │ │ + cdp2 13, 1, cr7, cr0, cr11, {1} │ │ cdp2 6, 0, cr15, cr14, cr14, {6} │ │ mcr2 2, 0, r3, cr15, cr9, {0} │ │ vfmsl.f16 , d16, d1[1] │ │ str r0, [sp, #128] @ 0x80 │ │ ldr r0, [pc, #696] @ (2141328 >&, std::__ndk1::function)@@Base+0x784>) │ │ add r0, pc │ │ movs r1, #18 │ │ @@ -296655,38 +296655,38 @@ │ │ movs r2, #4 │ │ add r1, pc │ │ b.n 2141390 >&, std::__ndk1::function)@@Base+0x7ec> │ │ ldr r1, [pc, #100] @ (2141388 >&, std::__ndk1::function)@@Base+0x7e4>) │ │ add r1, pc │ │ b.n 2141390 >&, std::__ndk1::function)@@Base+0x7ec> │ │ bl 1f7ef4a │ │ - adds r1, r1, r6 │ │ + adds r6, r6, r6 │ │ mcr2 1, 0, r3, cr14, cr11, {1} │ │ cdp2 5, 1, cr15, cr0, cr13, {5} │ │ cdp2 5, 0, cr15, cr15, cr2, {4} │ │ - vcmla.f16 , , d5[1], #0 │ │ + mcr2 9, 0, r1, cr15, cr2, {0} @ │ │ cdp2 0, 0, cr3, cr14, cr3, {6} │ │ mrc2 1, 0, r9, cr0, cr14, {5} │ │ - cdp2 2, 0, cr1, cr15, cr1, {7} │ │ + cdp2 3, 0, cr1, cr15, cr14, {0} │ │ cdp2 5, 0, cr3, cr15, cr4, {5} │ │ - cdp2 6, 0, cr13, cr13, cr12, {2} │ │ + mcr2 6, 0, sp, cr13, cr9, {3} │ │ cdp2 4, 0, cr15, cr14, cr7, {1} │ │ - mcr2 7, 0, r1, cr15, cr1, {4} │ │ - cdp2 6, 0, cr15, cr14, cr12, {5} │ │ - @ instruction: 0xfe0ebacc │ │ + mcr2 7, 0, r1, cr15, cr14, {5} │ │ + mcr2 6, 0, pc, cr14, cr9, {6} @ │ │ + mcr2 10, 0, fp, cr14, cr9, {7} @ │ │ cdp2 4, 0, cr15, cr14, cr7, {0} │ │ mcr2 10, 0, r9, cr15, cr7, {6} @ │ │ - vfmal.f16 d9, s26, s12[0] │ │ + vcmla.f16 , , d3[0], #0 │ │ mcr2 3, 0, pc, cr14, cr11, {7} @ │ │ - mcr2 11, 0, r3, cr15, cr8, {2} @ │ │ + vseleq.f64 d3, d31, d5 │ │ cdp2 7, 0, cr14, cr14, cr2, {3} │ │ - mrc2 7, 0, r1, cr0, cr11, {1} │ │ + cdp2 7, 1, cr1, cr0, cr8, {3} │ │ mcr2 12, 0, sl, cr14, cr1, {7} │ │ vselvs.f32 s18, s1, s18 │ │ - cdp2 5, 0, cr13, cr13, cr12, {3} │ │ + mcr2 5, 0, sp, cr13, cr9, {4} │ │ @ instruction: 0xfe0e49c3 │ │ add r1, pc │ │ blx 2706200 │ │ ldr.w r0, [r9, #32] │ │ ldr r1, [r0, #0] │ │ ldr.w r1, [r1, #-12] │ │ add r1, r0 │ │ @@ -296981,16 +296981,16 @@ │ │ subs r2, r2, r1 │ │ mov.w r3, #4294967295 @ 0xffffffff │ │ add.w r2, r3, r2, asr #2 │ │ cmp r4, r2 │ │ bne.n 21416b0 >&, std::__ndk1::function)@@Base+0xb0c> │ │ movs r2, #10 │ │ b.n 21416b2 >&, std::__ndk1::function)@@Base+0xb0e> │ │ - bl 1f1b2bc │ │ - asrs r3, r2, #26 │ │ + bl 1f482bc │ │ + asrs r0, r0, #27 │ │ mcr2 15, 0, r8, cr14, cr4, {3} │ │ cdp2 3, 0, cr1, cr15, cr5, {3} │ │ vseleq.f32 s10, s26, s10 │ │ cdp2 2, 0, cr2, cr13, cr0, {1} │ │ adds r3, r1, r5 │ │ ldr r1, [pc, #368] @ (2141828 >&, std::__ndk1::function)@@Base+0xc84>) │ │ strb.w r2, [sp, #72] @ 0x48 │ │ @@ -297095,32 +297095,32 @@ │ │ beq.n 21417ba >&, std::__ndk1::function)@@Base+0xc16> │ │ ldr r0, [sp, #48] @ 0x30 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ ldr r6, [r0, #24] │ │ lsls r7, r3, #1 │ │ str r4, [sp, #540] @ 0x21c │ │ - mcr2 0, 0, r1, cr13, cr8, {3} │ │ - mcr2 2, 0, r7, cr14, cr5, {5} │ │ + cdp2 0, 0, cr1, cr13, cr5, {5} │ │ + cdp2 2, 0, cr7, cr14, cr2, {7} │ │ vseleq.f64 d10, d15, d23 │ │ mrc2 11, 0, sl, cr0, cr13, {2} @ │ │ cdp2 14, 1, cr8, cr0, cr12, {0} │ │ mcr2 13, 0, r8, cr15, cr14, {6} │ │ mcr2 12, 0, r8, cr15, cr8, {2} │ │ - vfmal.f16 , d15, d4[3] │ │ + vcmla.f16 d3, d31, d9[1], #0 │ │ vcmla.f16 d5, d30, d6[0], #0 │ │ - cdp2 3, 0, cr15, cr13, cr2, {4} │ │ - mcr2 14, 0, r0, cr14, cr12, {6} │ │ - mcr2 6, 0, r7, cr15, cr6, {0} │ │ + cdp2 3, 0, cr15, cr13, cr15, {5} │ │ + cdp2 15, 0, cr0, cr14, cr9, {0} │ │ + cdp2 6, 0, cr7, cr15, cr3, {2} │ │ mcr2 4, 0, sl, cr14, cr12, {1} │ │ - mrc2 12, 0, r4, cr0, cr4, {7} │ │ + cdp2 13, 1, cr4, cr0, cr1, {1} │ │ mcr2 0, 0, fp, cr15, cr2, {3} │ │ - cdp2 4, 0, cr13, cr15, cr10, {2} │ │ - cdp2 14, 0, cr0, cr13, cr11, {4} │ │ - mcr2 1, 0, r7, cr15, cr12, {7} │ │ + mcr2 4, 0, sp, cr15, cr7, {3} │ │ + mcr2 14, 0, r0, cr13, cr8, {5} │ │ + cdp2 2, 0, cr7, cr15, cr9, {1} │ │ mcr2 3, 0, lr, cr14, cr6, {0} │ │ cdp2 12, 1, cr8, cr0, cr4, {0} │ │ mcr2 9, 0, r6, cr15, cr14, {2} @ │ │ lsls r7, r3, #1 │ │ │ │ 02141838 >&, std::__ndk1::function)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -298456,29 +298456,29 @@ │ │ b.n 21426ea >&, std::__ndk1::function)@@Base+0xeb2> │ │ movs r5, #1 │ │ b.n 214269a >&, std::__ndk1::function)@@Base+0xe62> │ │ movs r0, r0 │ │ movs r0, r0 │ │ ldrh r5, [r0, #18] │ │ vseleq.f32 s16, s26, s14 │ │ - vfmal.f16 q2, d13, d2[1] │ │ + vcmla.f16 d4, d29, d7[0], #0 │ │ mcr2 7, 0, r7, cr14, cr6, {4} │ │ vselvs.f16 s2, s0, s19 │ │ cdp2 13, 1, cr1, cr0, cr12, {4} │ │ vselvs.f16 s12, s0, s6 │ │ mcr2 2, 0, r0, cr13, cr2, {6} │ │ vseleq.f16 s8, s27, s2 │ │ vdot.bf16 , , d5[1] │ │ vfmal.f16 d6, s30, s14[1] │ │ - cdp2 15, 0, cr15, cr13, cr6, {1} │ │ - cdp2 15, 0, cr15, cr14, cr6, {0} │ │ - mcr2 2, 0, ip, cr14, cr0, {5} │ │ - mcr2 4, 0, r8, cr14, cr10, {7} │ │ + mcr2 15, 0, pc, cr13, cr3, {2} @ │ │ + mcr2 15, 0, pc, cr14, cr3, {1} @ │ │ + mcr2 2, 0, ip, cr14, cr13, {6} │ │ + cdp2 5, 0, cr8, cr14, cr7, {1} │ │ cdp2 0, 0, cr14, cr14, cr12, {4} │ │ - vcmla.f16 d2, d15, d15[0], #0 │ │ + vfmal.f16 d2, s30, s9[1] │ │ mcr2 7, 0, r4, cr14, cr15, {6} │ │ cdp2 5, 0, cr2, cr13, cr2, {0} │ │ mov r0, r8 │ │ blx 2701c70 │ │ add r0, sp, #104 @ 0x68 │ │ mov r1, r8 │ │ blx 2701e00 │ │ @@ -298853,27 +298853,27 @@ │ │ b.n 21428c0 >&, std::__ndk1::function)@@Base+0x1088> │ │ movs r4, #3 │ │ cmp r6, #16 │ │ bne.n 2142b08 >&, std::__ndk1::function)@@Base+0x12d0> │ │ b.n 2142d66 >&, std::__ndk1::function)@@Base+0x152e> │ │ @ instruction: 0xef40fe10 │ │ strb r6, [r4, #17] │ │ - mrc2 4, 0, lr, cr0, cr11, {6} │ │ + cdp2 5, 1, cr14, cr0, cr8, {0} │ │ cdp2 6, 0, cr15, cr13, cr2, {4} │ │ mrc2 14, 0, r1, cr0, cr1, {7} │ │ mcr2 4, 0, r1, cr13, cr11, {3} │ │ - cdp2 1, 1, cr12, cr0, cr10, {1} │ │ - vseleq.f64 d15, d29, d13 │ │ + mrc2 1, 0, ip, cr0, cr7, {2} │ │ + mcr2 11, 0, pc, cr13, cr10, {5} @ │ │ mcr2 7, 0, sp, cr14, cr12, {6} │ │ cdp2 4, 0, cr8, cr15, cr6, {1} │ │ cdp2 5, 0, cr3, cr13, cr4, {3} │ │ - vselvs.f16 s2, s1, s25 │ │ - cdp2 2, 0, cr6, cr15, cr4, {2} │ │ - mcr2 0, 0, ip, cr14, cr13, {4} │ │ - mcr2 0, 0, r0, cr13, cr11, {2} │ │ + mrc2 9, 0, r1, cr0, cr9, {6} @ │ │ + mcr2 2, 0, r6, cr15, cr1, {3} │ │ + cdp2 0, 0, cr12, cr14, cr10, {6} │ │ + cdp2 0, 0, cr0, cr13, cr8, {4} │ │ mcr2 13, 0, pc, cr14, cr2, {4} @ │ │ cdp2 4, 0, cr4, cr12, cr5, {2} │ │ mcr2 4, 0, r4, cr13, cr3, {1} │ │ cdp2 4, 0, cr2, cr13, cr5, {0} │ │ cmp r6, #16 │ │ bne.n 2142b08 >&, std::__ndk1::function)@@Base+0x12d0> │ │ b.n 2142d66 >&, std::__ndk1::function)@@Base+0x152e> │ │ @@ -299899,22 +299899,22 @@ │ │ str r1, [sp, #88] @ 0x58 │ │ add r1, sp, #88 @ 0x58 │ │ mov r0, r3 │ │ blx r2 │ │ ldr.w r8, [sp, #60] @ 0x3c │ │ b.n 2143630 >&, std::__ndk1::function)@@Base+0x1df8> │ │ @ instruction: 0xe8ccfe10 │ │ - bvs.n 2143698 >&, std::__ndk1::function)@@Base+0x1e60> │ │ + bvs.n 21434f2 >&, std::__ndk1::function)@@Base+0x1cba> │ │ cdp2 7, 0, cr8, cr14, cr4, {1} │ │ mrc2 11, 0, r5, cr0, cr6, {2} @ │ │ vseleq.f64 d3, d13, d28 │ │ - cdp2 1, 0, cr15, cr13, cr10, {4} │ │ - vcmla.f16 d5, d30, d2[1], #0 │ │ - mcr2 10, 0, r1, cr14, cr12, {6} @ │ │ - mcr2 15, 0, r2, cr14, cr14, {3} │ │ + mcr2 1, 0, pc, cr13, cr7, {5} @ │ │ + vcmla.f16 , q15, d15[0], #0 │ │ + vseleq.f64 d1, d14, d9 │ │ + cdp2 15, 0, cr2, cr14, cr11, {5} │ │ cdp2 3, 0, cr9, cr15, cr8, {0} │ │ mcr2 2, 0, r9, cr15, cr6, {7} │ │ cdp2 0, 0, cr14, cr15, cr2, {6} │ │ mrc2 0, 0, r2, cr0, cr0, {1} │ │ blx 26ffbf0 │ │ ldr r1, [pc, #948] @ (21439a8 >&, std::__ndk1::function)@@Base+0x2170>) │ │ ldr r3, [sp, #64] @ 0x40 │ │ @@ -300291,16 +300291,16 @@ │ │ blx 26ffb40 │ │ b.n 2143a88 >&, std::__ndk1::function)@@Base+0x2250> │ │ nop │ │ @ instruction: 0xea5efe10 │ │ b.n 2143b44 >&, std::__ndk1::function)@@Base+0x230c> │ │ mrc2 4, 0, lr, cr0, cr12, {6} │ │ mrc2 0, 0, lr, cr0, cr6, {7} │ │ - @ instruction: 0xfe100bc5 │ │ - mcr2 11, 0, r0, cr15, cr5, {5} @ │ │ + mrc2 11, 0, r0, cr0, cr2, {7} @ │ │ + @ instruction: 0xfe0f0be2 │ │ cdp2 1, 0, cr14, cr15, cr8, {0} │ │ cdp2 3, 1, cr14, cr0, cr0, {5} │ │ cdp2 13, 1, cr13, cr0, cr8, {3} │ │ mrc2 0, 0, lr, cr0, cr12, {2} │ │ b.n 2143a50 >&, std::__ndk1::function)@@Base+0x2218> │ │ b.n 2143b4a >&, std::__ndk1::function)@@Base+0x2312> │ │ b.n 2143a88 >&, std::__ndk1::function)@@Base+0x2250> │ │ @@ -300527,15 +300527,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #28] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ subs r2, #188 @ 0xbc │ │ lsls r7, r3, #1 │ │ - ldr r3, [pc, #848] @ (2143f50 >&, std::__ndk1::function)@@Base+0x2718>) │ │ + ldr r4, [pc, #4] @ (2143c04 >&, std::__ndk1::function)@@Base+0x23cc>) │ │ mcr2 10, 0, r3, cr15, cr14, {2} @ │ │ lsls r7, r3, #1 │ │ udf #254 @ 0xfe │ │ adds r0, #4 │ │ b.w 26fe90c │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -301286,16 +301286,16 @@ │ │ beq.n 21443ee >&, std::__ndk1::function)@@Base+0x2bb6> │ │ b.n 21444b6 >&, std::__ndk1::function)@@Base+0x2c7e> │ │ nop │ │ svc 194 @ 0xc2 │ │ cdp2 6, 1, cr13, cr0, cr8, {1} │ │ mrc2 15, 0, sp, cr0, cr6, {3} │ │ cdp2 5, 1, cr13, cr0, cr2, {4} │ │ - cdp2 7, 1, cr14, cr0, cr15, {1} │ │ - mcr2 7, 0, lr, cr13, cr11, {0} │ │ + mrc2 7, 0, lr, cr0, cr12, {2} │ │ + cdp2 7, 0, cr14, cr13, cr8, {2} │ │ cdp2 12, 0, cr2, cr13, cr3, {0} │ │ bhi.n 21444b2 >&, std::__ndk1::function)@@Base+0x2c7a> │ │ ldr r0, [sp, #76] @ 0x4c │ │ ldr r0, [r0, #40] @ 0x28 │ │ add r1, sp, #424 @ 0x1a8 │ │ movs r2, #4 │ │ blx 27043b0 │ │ @@ -302038,15 +302038,15 @@ │ │ blxne 26ffb40 │ │ ldrsh.w r0, [sp, #108] @ 0x6c │ │ movs r4, #1 │ │ ldr r1, [sp, #32] │ │ str.w r6, [r1, r0, lsl #2] │ │ b.n 21449e4 >&, std::__ndk1::function)@@Base+0x31ac> │ │ bne.n 2144cb0 >&, std::__ndk1::function)@@Base+0x3478> │ │ - mrc2 11, 0, fp, cr0, cr9, {0} @ │ │ + @ instruction: 0xfe10bb46 │ │ mcr2 0, 0, r2, cr13, cr0, {1} │ │ blx 26ffbf0 │ │ ldr r1, [pc, #920] @ (2144fc0 >&, std::__ndk1::function)@@Base+0x3788>) │ │ movs r3, #15 │ │ mov r2, r0 │ │ str r0, [sp, #144] @ 0x90 │ │ add r1, pc │ │ @@ -304327,19 +304327,19 @@ │ │ cmp r0, #12 │ │ bcs.n 21462ec │ │ movs r1, #0 │ │ mov r0, r4 │ │ b.n 2146328 │ │ movs r1, #0 │ │ b.n 2146332 │ │ - lsls r4, r1, #14 │ │ + lsls r1, r7, #14 │ │ cdp2 0, 0, cr6, cr15, cr3, {5} │ │ - cdp2 5, 1, cr12, cr0, cr0, {2} │ │ - mcr2 13, 0, r6, cr14, cr15, {6} │ │ - mcr2 7, 0, r2, cr14, cr8, {5} │ │ + cdp2 5, 1, cr12, cr0, cr13, {3} │ │ + cdp2 14, 0, cr6, cr14, cr12, {0} │ │ + cdp2 7, 0, cr2, cr14, cr5, {7} │ │ cdp2 0, 0, cr0, cr15, cr0, {0} │ │ movs r0, r0 │ │ movs r1, #1 │ │ add.w r2, r1, r0, lsr #2 │ │ movw r0, #65532 @ 0xfffc │ │ vmov.i32 q8, #0 @ 0x00000000 │ │ movt r0, #32767 @ 0x7fff │ │ @@ -317499,20 +317499,20 @@ │ │ blx 26ffb60 │ │ nop │ │ stcl 0, cr0, [ip, #-384]! @ 0xfffffe80 │ │ ldrb r4, [r5, #30] │ │ lsls r6, r3, #1 │ │ ldcl 0, cr0, [r6, #-384] @ 0xfffffe80 │ │ adds r0, #228 @ 0xe4 │ │ - mcr2 1, 0, sp, cr12, cr12, {5} │ │ - cdp2 1, 0, cr13, cr12, cr2, {5} │ │ - cdp2 6, 0, cr13, cr12, cr2, {0} │ │ + cdp2 1, 0, cr13, cr12, cr9, {7} │ │ + cdp2 1, 0, cr13, cr12, cr15, {6} │ │ + cdp2 6, 0, cr13, cr12, cr15, {1} │ │ cdp2 6, 0, cr11, cr13, cr6, {0} │ │ - mcr2 4, 0, r1, cr12, cr15, {4} │ │ - mcr2 4, 0, r1, cr13, cr1, {4} │ │ + cdp2 4, 0, cr1, cr12, cr12, {6} │ │ + mcr2 4, 0, r1, cr13, cr14, {5} │ │ cdp2 14, 0, cr7, cr13, cr0, {4} │ │ lsls r6, r3, #1 │ │ ldrb r2, [r5, #19] │ │ lsls r6, r3, #1 │ │ ldrh r6, [r7, #32] │ │ cdp2 12, 0, cr8, cr15, cr8, {1} │ │ vseleq.f64 d2, d15, d8 │ │ @@ -341732,15 +341732,15 @@ │ │ addeq sp, #32 │ │ ldreq.w fp, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ str r6, [r6, #52] @ 0x34 │ │ lsls r5, r3, #1 │ │ - bvc.n 21612ca │ │ + bhi.n 2161324 │ │ cdp2 3, 0, cr6, cr11, cr8, {4} │ │ lsls r5, r3, #1 │ │ str r4, [r5, #48] @ 0x30 │ │ lsls r5, r3, #1 │ │ │ │ 02161328 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -341787,15 +341787,15 @@ │ │ addeq sp, #32 │ │ ldreq.w fp, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ str r6, [r6, #44] @ 0x2c │ │ lsls r5, r3, #1 │ │ - @ instruction: 0xb606 │ │ + @ instruction: 0xb633 │ │ cdp2 3, 0, cr6, cr11, cr8, {0} │ │ lsls r5, r3, #1 │ │ str r4, [r5, #40] @ 0x28 │ │ lsls r5, r3, #1 │ │ │ │ 021613a8 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -341842,15 +341842,15 @@ │ │ addeq sp, #32 │ │ ldreq.w fp, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ str r6, [r6, #36] @ 0x24 │ │ lsls r5, r3, #1 │ │ - ldr.w pc, [r0, #3595] @ 0xe0b │ │ + ldr??.w pc, [sp, #3595] @ 0xe0b │ │ str r0, [r1, #40] @ 0x28 │ │ lsls r5, r3, #1 │ │ str r4, [r5, #32] │ │ lsls r5, r3, #1 │ │ │ │ 02161428 >&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -345596,15 +345596,15 @@ │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ subs r3, #188 @ 0xbc │ │ lsls r5, r3, #1 │ │ stcl 14, cr15, [r6], #40 @ 0x28 │ │ subs r3, #156 @ 0x9c │ │ lsls r5, r3, #1 │ │ - lsls r5, r6, #31 │ │ + lsrs r2, r4, #32 │ │ mcr2 10, 0, r3, cr13, cr8, {7} @ │ │ lsls r5, r3, #1 │ │ lsls r3, r1, #27 │ │ movs r0, r0 │ │ mrc2 0, 5, r0, cr0, cr11, {2} │ │ subs r2, #208 @ 0xd0 │ │ lsls r5, r3, #1 │ │ @@ -346104,16 +346104,16 @@ │ │ nop │ │ adds r5, #240 @ 0xf0 │ │ lsls r5, r3, #1 │ │ lsls r1, r1, #8 │ │ cdp2 5, 0, cr3, cr14, cr14, {6} │ │ lsls r5, r3, #1 │ │ bkpt 0x0008 │ │ - mcr2 13, 0, r8, cr15, cr4, {2} │ │ - mcr2 11, 0, r4, cr12, cr7, {1} @ │ │ + vdot.bf16 d8, d31, d1[0] │ │ + @ instruction: 0xfe0c4b64 │ │ mcr2 5, 0, r3, cr12, cr0, {2} │ │ lsls r5, r3, #1 │ │ lsls r4, r4, #5 │ │ cdp2 5, 0, cr3, cr14, cr6, {1} │ │ lsls r5, r3, #1 │ │ b.n 2163e60 , bool (*)(std::__ndk1::basic_istream >&, double&, Eigen::Matrix&)>(std::__ndk1::basic_istream >&, std::__ndk1::__fs::filesystem::path const&, std::__ndk1::vector >&, std::__ndk1::vector, std::__ndk1::allocator > >&, bool (*)(std::__ndk1::basic_istream >&, double&, Eigen::Matrix&))@@Base+0xec8> │ │ cdp2 4, 0, cr3, cr10, cr0, {7} │ │ @@ -347121,15 +347121,15 @@ │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ cmp r3, #148 @ 0x94 │ │ lsls r5, r3, #1 │ │ bgt.n 2164bd0 , bool (*)(std::__ndk1::basic_istream >&, double&, Eigen::Matrix&)>(std::__ndk1::basic_istream >&, std::__ndk1::__fs::filesystem::path const&, std::__ndk1::vector >&, std::__ndk1::vector, std::__ndk1::allocator > >&, bool (*)(std::__ndk1::basic_istream >&, double&, Eigen::Matrix&))@@Base+0x1c38> │ │ mcr2 11, 0, r2, cr10, cr4, {3} @ │ │ lsls r5, r3, #1 │ │ - bl 2132874 │ │ + bl 215f874 const&, double, double, double)@@Base+0x32c> │ │ cmp r2, #208 @ 0xd0 │ │ lsls r5, r3, #1 │ │ lsls r3, r7, #21 │ │ movs r0, r0 │ │ mrc 0, 5, r0, cr0, cr11, {2} │ │ cmp r2, #168 @ 0xa8 │ │ lsls r5, r3, #1 │ │ @@ -352442,26 +352442,26 @@ │ │ b.n 21689bc │ │ ldrb r0, [r4, #0] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [r4, #8] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ - @ instruction: 0xffbcfe0b │ │ + vmull.p64 , d9, d11 │ │ stc 0, cr0, [lr, #-368]! @ 0xfffffe90 │ │ ldrb r4, [r3, r4] │ │ lsls r7, r3, #1 │ │ ldrb r6, [r1, r4] │ │ lsls r7, r3, #1 │ │ ldrb r2, [r5, r2] │ │ lsls r7, r3, #1 │ │ ldrb r2, [r2, r2] │ │ lsls r7, r3, #1 │ │ - ldr r3, [sp, #1000] @ 0x3e8 │ │ - cdp2 15, 0, cr15, cr12, cr2, {4} │ │ + ldr r4, [sp, #156] @ 0x9c │ │ + cdp2 15, 0, cr15, cr12, cr15, {5} │ │ mcr2 12, 0, lr, cr11, cr10, {5} │ │ lsls r4, r3, #1 │ │ ldrb r2, [r0, r2] │ │ lsls r7, r3, #1 │ │ │ │ 021689f4 , std::__ndk1::allocator > const&)@@Base>: │ │ push {r4, r5, r7, lr} │ │ @@ -353000,15 +353000,15 @@ │ │ blx 27038a0 │ │ mov r0, r5 │ │ mvn.w r1, #1 │ │ blx 2704b70 │ │ b.n 2169034 , std::__ndk1::allocator > const*, std::__ndk1::basic_string, std::__ndk1::allocator > const&, AssociativeArray const&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x498> │ │ nop │ │ lsrs r3, r3, #31 │ │ - mcr2 2, 0, ip, cr14, cr11, {0} │ │ + cdp2 2, 0, cr12, cr14, cr8, {2} │ │ vseleq.f64 d9, d11, d24 │ │ vcmla.f16 d9, d10, d6[0], #0 │ │ vmov d10, r6, r0 │ │ vcmp.f64 d10, #0.0 │ │ vmrs APSR_nzcv, fpscr │ │ bls.n 2169028 , std::__ndk1::allocator > const*, std::__ndk1::basic_string, std::__ndk1::allocator > const&, AssociativeArray const&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x48c> │ │ movs r0, #136 @ 0x88 │ │ @@ -353076,26 +353076,26 @@ │ │ ldrb.w r0, [sp, #40] @ 0x28 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #48] @ 0x30 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ orns r0, r6, ip, lsr #1 │ │ - ldrb r6, [r3, r6] │ │ + ldrb r3, [r1, r7] │ │ cdp2 6, 0, cr14, cr11, cr12, {6} │ │ lsls r4, r3, #1 │ │ lsrs r3, r2, #27 │ │ mcr2 12, 0, r1, cr14, cr10, {6} │ │ mcr2 12, 0, r6, cr13, cr7, {7} │ │ - vdot.bf16 , q7, d1[1] │ │ - mcr2 5, 0, fp, cr11, cr6, {3} │ │ + vdot.bf16 d13, d30, d14[0] │ │ + cdp2 5, 0, cr11, cr11, cr3, {5} │ │ vcmla.f16 d9, d28, d0[0], #0 │ │ mcr2 15, 0, r8, cr10, cr4, {7} │ │ - vcmla.f16 d15, d30, d15[1], #0 │ │ - mcr2 9, 0, r7, cr12, cr13, {3} @ │ │ + vfmal.f16 , d30, d4[1] │ │ + vseleq.f16 s14, s25, s21 │ │ mcr2 1, 0, fp, cr12, cr12, {5} │ │ lsls r3, r3, #1 │ │ cbz r4, 21690ea , std::__ndk1::allocator > const*, std::__ndk1::basic_string, std::__ndk1::allocator > const&, AssociativeArray const&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x54e> │ │ lsls r3, r3, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ ldr r4, [r0, #4] │ │ @@ -353665,15 +353665,15 @@ │ │ addeq sp, #4 │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ it eq │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ lsrs r3, r2, #2 │ │ - mcr2 15, 0, sl, cr14, cr5, {7} │ │ + cdp2 0, 0, cr11, cr14, cr2, {1} │ │ cdp2 0, 0, cr2, cr12, cr0, {4} │ │ movs r1, #16 │ │ blx 26ffc50 │ │ ldr r1, [sp, #20] │ │ vmov.f64 d17, #112 @ 0x3f800000 1.0 │ │ vmov d16, r6, r1 │ │ ldr r1, [pc, #192] @ (216979c , std::__ndk1::allocator > const*, std::__ndk1::basic_string, std::__ndk1::allocator > const&, AssociativeArray const&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x4b8>) │ │ @@ -353725,22 +353725,22 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #48] @ 0x30 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ b.n 2169dd0 , std::__ndk1::allocator > const&)@@Base+0x3c> │ │ lsls r4, r3, #1 │ │ - strb r4, [r4, #23] │ │ + strb r1, [r2, #24] │ │ @ instruction: 0xfe0c49c7 │ │ cdp2 15, 0, cr13, cr14, cr12, {4} │ │ lsls r4, r3, #1 │ │ lsls r3, r1, #30 │ │ mcr2 5, 0, r1, cr14, cr2, {4} │ │ - mcr2 6, 0, r5, cr13, cr10, {0} │ │ - vcmla.f16 d11, d11, d10[0], #0 │ │ + cdp2 6, 0, cr5, cr13, cr7, {2} │ │ + vfmal.f16 d11, s22, s15[0] │ │ vcmla.f16 q4, , d8[1], #0 │ │ vcmla.f16 , q7, d7[1], #0 │ │ vfmal.f16 , d10, d3[1] │ │ @ instruction: 0xfe0aab40 │ │ lsls r3, r3, #1 │ │ add r3, sp, #40 @ 0x28 │ │ lsls r3, r3, #1 │ │ @@ -353985,15 +353985,15 @@ │ │ ldr r2, [pc, #16] @ (2169a34 ) │ │ add r0, pc │ │ add r2, pc │ │ blx 2706670 │ │ movs r0, #1 │ │ pop {r7, pc} │ │ nop │ │ - ldr r1, [r5, #124] @ 0x7c │ │ + strb r6, [r2, #0] │ │ mcr2 6, 0, r2, cr12, cr2, {1} │ │ Address 0x2169a36 is out of bounds. │ │ │ │ │ │ 02169a38 , std::__ndk1::allocator > const&, int*)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -354058,15 +354058,15 @@ │ │ itt eq │ │ ldreq.w fp, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ blt.n 2169a94 , std::__ndk1::allocator > const&, int*)@@Base+0x5c> │ │ lsls r4, r3, #1 │ │ - push {r0, r2, r4, r5} │ │ + push {r1, r5, r6} │ │ vseleq.f64 d13, d27, d6 │ │ lsls r4, r3, #1 │ │ │ │ 02169ad4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -354211,15 +354211,15 @@ │ │ lsls r7, r3, #1 │ │ ldr r2, [pc, #160] @ (2169cec , std::__ndk1::allocator >, std::__ndk1::basic_string, std::__ndk1::allocator >, double, double)@@Base+0x10>) │ │ lsls r7, r3, #1 │ │ add r4, sp, #476 @ 0x1dc │ │ cdp2 15, 0, cr0, cr10, cr6, {6} │ │ @ instruction: 0xfe0bdac0 │ │ lsls r4, r3, #1 │ │ - cbz r4, 2169ca2 , std::__ndk1::allocator >, std::__ndk1::basic_string, std::__ndk1::allocator >, double, double, double, double)@@Base+0x42> │ │ + cbz r1, 2169cae , std::__ndk1::allocator >, std::__ndk1::basic_string, std::__ndk1::allocator >, double, double, double, double)@@Base+0x4e> │ │ @ instruction: 0xfe0bda60 │ │ lsls r4, r3, #1 │ │ │ │ 02169c60 , std::__ndk1::allocator >, std::__ndk1::basic_string, std::__ndk1::allocator >, double, double, double, double)@@Base>: │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ ldr r4, [pc, #112] @ (2169cd8 , std::__ndk1::allocator >, std::__ndk1::basic_string, std::__ndk1::allocator >, double, double, double, double)@@Base+0x78>) │ │ @@ -354779,29 +354779,29 @@ │ │ stmia r1!, {r1, r6} │ │ movs r0, r0 │ │ movs r0, r0 │ │ adds r0, r0, r0 │ │ lsrs r5, r6 │ │ bvc.n 216a29c , std::__ndk1::allocator > >(char const*, std::__ndk1::basic_string, std::__ndk1::allocator > const&) const@@Base> │ │ lsls r4, r3, #1 │ │ - stmia r2!, {r0, r1, r2, r3, r4, r6, r7} │ │ + stmia r3!, {r2, r3} │ │ cdp2 14, 0, cr14, cr12, cr7, {2} │ │ - mcr2 15, 0, sl, cr10, cr2, {4} │ │ + mcr2 15, 0, sl, cr10, cr15, {5} │ │ cdp2 14, 0, cr10, cr11, cr14, {2} │ │ lsls r5, r3, #1 │ │ - add r7, sp, #448 @ 0x1c0 │ │ + add r7, sp, #628 @ 0x274 │ │ mcr2 14, 0, sl, cr11, cr2, {1} │ │ lsls r5, r3, #1 │ │ add r5, sp, #960 @ 0x3c0 │ │ lsls r5, r3, #1 │ │ stc2 14, cr15, [ip], {13} │ │ - movs r7, #81 @ 0x51 │ │ + movs r7, #126 @ 0x7e │ │ mcr2 12, 0, sl, cr11, cr2, {5} │ │ lsls r5, r3, #1 │ │ - ldrh r6, [r7, #6] │ │ + ldrh r3, [r5, #8] │ │ cdp2 6, 0, cr10, cr11, cr5, {0} │ │ mcr2 9, 0, r0, cr10, cr4, {2} @ │ │ mcr2 5, 0, sp, cr11, cr2, {4} │ │ lsls r4, r3, #1 │ │ │ │ 0216a29c , std::__ndk1::allocator > >(char const*, std::__ndk1::basic_string, std::__ndk1::allocator > const&) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -354953,15 +354953,15 @@ │ │ movs r0, r0 │ │ adds r0, r0, r0 │ │ lsrs r5, r6 │ │ bcc.n 216a434 │ │ lsls r4, r3, #1 │ │ bcs.n 216a48c │ │ lsls r4, r3, #1 │ │ - strh r4, [r2, #56] @ 0x38 │ │ + strh r1, [r0, #58] @ 0x3a │ │ cdp2 4, 0, cr10, cr11, cr9, {1} │ │ mcr2 7, 0, r0, cr10, cr4, {3} │ │ mcr2 4, 0, sp, cr11, cr4, {6} │ │ bmi.n 216a3f2 │ │ │ │ 0216a448 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -355065,15 +355065,15 @@ │ │ movs r0, r0 │ │ adds r0, r0, r0 │ │ stmia r0!, {r0, r2, r4, r5, r6, r7} │ │ bne.n 216a514 │ │ lsls r4, r3, #1 │ │ beq.n 216a554 │ │ lsls r4, r3, #1 │ │ - strh r4, [r3, #46] @ 0x2e │ │ + strh r1, [r1, #48] @ 0x30 │ │ mcr2 2, 0, sl, cr11, cr5, {7} │ │ cdp2 6, 0, cr0, cr10, cr0, {2} │ │ Address 0x216a58a is out of bounds. │ │ │ │ │ │ 0216a58c : │ │ vldr d16, [r0, #128] @ 0x80 │ │ @@ -359354,16 +359354,16 @@ │ │ pop {r4, r5, r6, r7, pc} │ │ b.n 216d840 │ │ b.n 216d840 │ │ mov r0, r5 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ - ldr r7, [r1, #40] @ 0x28 │ │ - cdp2 2, 0, cr15, cr12, cr13, {1} │ │ + ldr r4, [r7, #40] @ 0x28 │ │ + mcr2 2, 0, pc, cr12, cr10, {2} @ │ │ Address 0x216d852 is out of bounds. │ │ │ │ │ │ 0216d854 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ @@ -360514,15 +360514,15 @@ │ │ subs r7, #128 @ 0x80 │ │ movs r0, r0 │ │ movs r0, r0 │ │ strh r1, [r0, #4] │ │ subs r3, #128 @ 0x80 │ │ ldr r5, [sp, #496] @ 0x1f0 │ │ lsls r4, r3, #1 │ │ - ldrb r7, [r2, #8] │ │ + ldrb r4, [r0, #9] │ │ cdp2 12, 0, cr5, cr12, cr6, {0} │ │ mcr2 12, 0, r9, cr13, cr1, {5} │ │ mcr2 2, 0, r9, cr13, cr12, {2} │ │ lsls r4, r3, #1 │ │ str r2, [sp, #216] @ 0xd8 │ │ lsls r4, r3, #1 │ │ ldrh r0, [r5, #54] @ 0x36 │ │ @@ -361193,22 +361193,22 @@ │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ bmi.n 216ef60 │ │ vcmla.f16 q4, q9, d6[1], #90 │ │ lsls r4, r3, #1 │ │ - adds r7, #225 @ 0xe1 │ │ - mcr2 6, 0, r5, cr12, cr15, {0} │ │ - vdot.bf16 , q6, d15[1] │ │ - mcr2 15, 0, r7, cr11, cr9, {0} │ │ + subs r0, #14 │ │ + cdp2 6, 0, cr5, cr12, cr12, {2} │ │ + mcr2 13, 0, fp, cr12, cr12, {4} │ │ + cdp2 15, 0, cr7, cr11, cr6, {2} │ │ mcr2 12, 0, ip, cr11, cr13, {0} │ │ cdp2 2, 0, cr3, cr13, cr12, {2} │ │ cdp2 12, 0, cr11, cr13, cr0, {0} │ │ - mcr2 6, 0, r3, cr12, cr2, {6} │ │ + mcr2 6, 0, r3, cr12, cr15, {7} │ │ vfmal.f16 q4, d11, d0[2] │ │ lsls r4, r3, #1 │ │ strh r4, [r7, #56] @ 0x38 │ │ lsls r4, r3, #1 │ │ │ │ 0216ef3c : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -361376,20 +361376,20 @@ │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ strh r2, [r3, #54] @ 0x36 │ │ lsls r4, r3, #1 │ │ adds r6, #177 @ 0xb1 │ │ - cdp2 4, 0, cr5, cr10, cr3, {1} │ │ - mcr2 11, 0, fp, cr12, cr5, {3} @ │ │ - mcr2 13, 0, r7, cr11, cr15, {0} │ │ + mcr2 4, 0, r5, cr10, cr0, {2} │ │ + vseleq.f64 d11, d28, d18 │ │ + vdot.bf16 , , d12[0] │ │ mcr2 10, 0, ip, cr11, cr15, {0} @ │ │ cdp2 0, 0, cr3, cr13, cr14, {2} │ │ - cdp2 5, 0, cr3, cr13, cr14, {3} │ │ + mcr2 5, 0, r3, cr13, cr11, {4} │ │ mcr2 6, 0, r8, cr11, cr4, {4} │ │ lsls r4, r3, #1 │ │ strh r0, [r4, #42] @ 0x2a │ │ lsls r4, r3, #1 │ │ │ │ 0216f110 &, Eigen::Matrix&, int&) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -362042,17 +362042,17 @@ │ │ strh.w r3, [r4, #-2] │ │ add.w r3, sl, r2 │ │ cmp r3, ip │ │ bne.n 216f8b4 │ │ add.w sl, r1, r2 │ │ b.n 216f91a │ │ nop │ │ - bl 1f6b504 │ │ + bl 1f98504 │ │ adds r3, #13 │ │ - cdp2 4, 0, cr13, cr10, cr15, {2} │ │ + mcr2 4, 0, sp, cr10, cr12, {3} │ │ cdp2 15, 0, cr15, cr10, cr0, {0} │ │ bx pc │ │ cmp r1, #75 @ 0x4b │ │ subs r7, #37 @ 0x25 │ │ mcr2 6, 0, r4, cr0, cr15, {7} │ │ nop │ │ nop │ │ @@ -363220,23 +363220,23 @@ │ │ add r0, sp, #96 @ 0x60 │ │ ldr r4, [sp, #68] @ 0x44 │ │ blx 2703ed0 │ │ add r0, sp, #76 @ 0x4c │ │ blx 2703ec0 │ │ b.n 2170646 │ │ b.n 2170644 │ │ - ldmia.w r9!, {r1, r3, r9, sl, fp, ip, sp, lr, pc} │ │ + strd pc, lr, [r6], #40 @ 0x28 │ │ ldr r4, [sp, #68] @ 0x44 │ │ cmp r4, #0 │ │ itt ne │ │ movne r0, r4 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ movs r5, #201 @ 0xc9 │ │ - cdp2 7, 0, cr12, cr10, cr11, {0} │ │ + mcr2 7, 0, ip, cr10, cr8, {1} │ │ cdp2 15, 0, cr11, cr10, cr0, {0} │ │ nop │ │ mcr2 6, 0, r4, cr0, cr15, {7} │ │ mcr2 6, 0, r4, cr0, cr15, {7} │ │ vaba.u8 q2, q0, │ │ cmp r1, #75 @ 0x4b │ │ subs r7, #37 @ 0x25 │ │ @@ -363784,15 +363784,15 @@ │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ ldr r6, [r5, #40] @ 0x28 │ │ lsls r4, r3, #1 │ │ adds r1, r2, #3 │ │ - mcr2 14, 0, r9, cr10, cr7, {0} │ │ + cdp2 14, 0, cr9, cr10, cr4, {2} │ │ mcr2 11, 0, r6, cr11, cr6, {4} @ │ │ lsls r4, r3, #1 │ │ adds r5, r7, r6 │ │ movs r0, r0 │ │ ldr r0, [r7, #24] │ │ lsls r4, r3, #1 │ │ push {r4, r5, r7, lr} │ │ @@ -364647,20 +364647,20 @@ │ │ bl 2170ca4 │ │ mov r5, r0 │ │ ldr.w r0, [r0, #736] @ 0x2e0 │ │ ldr.w r9, [sp, #84] @ 0x54 │ │ cbnz r0, 2171732 │ │ b.n 21716e8 │ │ nop │ │ - ldrsb r5, [r6, r2] │ │ + ldrsb r2, [r4, r3] │ │ mcr2 10, 0, r0, cr11, cr12, {0} @ │ │ - vcmla.f16 d3, d29, d14[0], #0 │ │ - mcr2 5, 0, r7, cr11, cr6, {7} │ │ - mcr2 4, 0, r9, cr11, cr7, {4} │ │ - vdot.bf16 d2, d11, d3[1] │ │ + vfmal.f16 d3, s27, s7[1] │ │ + cdp2 6, 0, cr7, cr11, cr3, {1} │ │ + cdp2 4, 0, cr9, cr11, cr4, {6} │ │ + mcr2 13, 0, r2, cr11, cr0, {2} │ │ vcmla.f16 d4, d12, d9[0], #0 │ │ movs r1, #2 │ │ movs r2, #128 @ 0x80 │ │ movw r3, #6409 @ 0x1909 │ │ add r0, pc │ │ stmia.w sp, {r0, r1, r6} │ │ add r0, sp, #288 @ 0x120 │ │ @@ -365105,21 +365105,21 @@ │ │ movs r0, r0 │ │ ldmia r4!, {r0, r2, r3, r6, r7} │ │ subs r7, #76 @ 0x4c │ │ movs r0, r0 │ │ cmn r0, r0 │ │ ldr r2, [r7, #12] │ │ lsls r4, r3, #1 │ │ - lsrs r0, r2, #12 │ │ + lsrs r5, r7, #12 │ │ cdp2 2, 0, cr6, cr11, cr2, {5} │ │ mcr2 5, 0, r0, cr13, cr14, {5} │ │ - mcr2 4, 0, r3, cr13, cr0, {1} │ │ - mcr2 1, 0, r7, cr11, cr2, {4} │ │ - cdp2 0, 0, cr9, cr11, cr1, {1} │ │ - mcr2 12, 0, r6, cr11, cr4, {7} │ │ + mcr2 4, 0, r3, cr13, cr13, {2} │ │ + mcr2 1, 0, r7, cr11, cr15, {5} │ │ + cdp2 0, 0, cr9, cr11, cr14, {2} │ │ + vdot.bf16 d6, d11, d1[1] │ │ mcr2 10, 0, r5, cr12, cr4, {4} @ │ │ lsls r4, r3, #1 │ │ ldr r0, [pc, #32] @ (2171ca0 ) │ │ add r0, pc │ │ ldr r0, [r0, #0] │ │ ldrb r1, [r0, #0] │ │ lsls r1, r1, #31 │ │ @@ -366268,18 +366268,18 @@ │ │ subs r3, #128 @ 0x80 │ │ strh r1, [r0, #4] │ │ subs r3, #128 @ 0x80 │ │ strh r1, [r0, #4] │ │ subs r3, #128 @ 0x80 │ │ ldr r5, [pc, #376] @ (2172bac ) │ │ lsls r4, r3, #1 │ │ - str r6, [r1, #56] @ 0x38 │ │ - mcr2 14, 0, r5, cr11, cr8, {6} │ │ - cdp2 6, 0, cr3, cr12, cr7, {6} │ │ - cdp2 7, 0, cr15, cr12, cr13, {7} │ │ + str r3, [r7, #56] @ 0x38 │ │ + cdp2 15, 0, cr5, cr11, cr5, {0} │ │ + mcr2 6, 0, r3, cr12, cr4, {7} │ │ + vfmal.f16 d15, s24, s4[1] │ │ vdot.bf16 d9, d11, d1[0] │ │ mcr2 5, 0, r3, cr12, cr1, {1} │ │ mcr2 12, 0, r4, cr13, cr6, {1} │ │ lsls r4, r3, #1 │ │ │ │ 02172a50 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -374379,16 +374379,16 @@ │ │ movs r0, r0 │ │ movs r0, r0 │ │ eors r1, r3 │ │ cmp r5, #24 │ │ strb r4, [r0, r1] │ │ movs r1, #251 @ 0xfb │ │ ands r1, r1 │ │ - strh r5, [r4, #6] │ │ - mcr2 0, 0, r8, cr11, cr5, {6} │ │ + strh r2, [r2, #8] │ │ + cdp2 1, 0, cr8, cr11, cr2, {0} │ │ cdp2 2, 0, cr15, cr11, cr3, {2} │ │ movs r6, r0 │ │ mov.w sl, #0 │ │ movt r0, #45250 @ 0xb0c2 │ │ str r0, [sp, #96] @ 0x60 │ │ ldr r0, [sp, #76] @ 0x4c │ │ cmp r0, #0 │ │ @@ -374696,25 +374696,25 @@ │ │ b.n 2178d7c const&, Color const&, int) const@@Base+0x71c> │ │ b.n 2178d7c const&, Color const&, int) const@@Base+0x71c> │ │ b.n 2178d7c const&, Color const&, int) const@@Base+0x71c> │ │ b.n 2178d7c const&, Color const&, int) const@@Base+0x71c> │ │ b.n 2178d7c const&, Color const&, int) const@@Base+0x71c> │ │ b.n 2178d7c const&, Color const&, int) const@@Base+0x71c> │ │ b.n 2178d7c const&, Color const&, int) const@@Base+0x71c> │ │ - strh r6, [r5, #2] │ │ + strh r3, [r3, #4] │ │ vfmal.f16 d15, s23, s10[1] │ │ lsls r0, r4, #1 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #104] @ 0x68 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ orns r0, r2, #91 @ 0x5b │ │ - strh r4, [r7, #0] │ │ + strh r1, [r5, #2] │ │ cdp2 15, 0, cr11, cr11, cr0, {0} │ │ nop │ │ nop │ │ nop │ │ movs r0, r0 │ │ strh r0, [r0, #0] │ │ movs r0, r0 │ │ @@ -375056,15 +375056,15 @@ │ │ movs r0, #34 @ 0x22 │ │ mov.w r9, #39 @ 0x27 │ │ add r4, pc │ │ movt r1, #19775 @ 0x4d3f │ │ str r0, [sp, #104] @ 0x68 │ │ b.n 21791b0 const&, celestia::engine::SkyGrid const&, int) const@@Base+0x3e0> │ │ nop │ │ - asrs r5, r1, #18 │ │ + asrs r2, r7, #18 │ │ vfmal.f16 , d27, d3[1] │ │ movs r4, r5 │ │ ldr.w fp, [sp, #96] @ 0x60 │ │ cmp.w fp, #0 │ │ it mi │ │ addmi fp, r1 │ │ cmp r0, #1 │ │ @@ -375382,19 +375382,19 @@ │ │ blx 2707260 │ │ ldr r0, [sp, #100] @ 0x64 │ │ vldr s0, [r0, #8] │ │ vldr s2, [r0, #20] │ │ vldr s4, [r0, #32] │ │ b.n 21795cc const&, celestia::engine::SkyGrid const&, int) const@@Base+0x7fc> │ │ nop │ │ - bl 20541cc │ │ - ldrsb r3, [r6, r2] │ │ + bl 20811cc │ │ + ldrsb r0, [r4, r3] │ │ vfmal.f16 d14, s22, s12[0] │ │ lsls r3, r3, #1 │ │ - ldrsb r3, [r7, r1] │ │ + ldrsb r0, [r5, r2] │ │ @ instruction: 0xfe0b1b4e │ │ vfmal.f16 , d26, d5[1] │ │ add sp, #352 @ 0x160 │ │ vldr s10, [sp, #160] @ 0xa0 │ │ vldr s8, [sp, #156] @ 0x9c │ │ vmul.f32 s4, s10, s4 │ │ vldr s6, [sp, #152] @ 0x98 │ │ @@ -377111,15 +377111,15 @@ │ │ ldrb r0, [r5, #0] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [r5, #8] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ - ldr r6, [sp, #88] @ 0x58 │ │ + ldr r6, [sp, #268] @ 0x10c │ │ mcr2 5, 0, fp, cr11, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ ldr r5, [r0, #0] │ │ mov r4, r0 │ │ cbz r5, 217a6de , std::__ndk1::allocator >&&, std::__ndk1::vector, std::__ndk1::allocator > >, std::__ndk1::allocator, std::__ndk1::allocator > > > >&&)@@Base+0x186> │ │ ldr r1, [r4, #4] │ │ @@ -377642,15 +377642,15 @@ │ │ add r2, sp, #40 @ 0x28 │ │ mov r0, r8 │ │ blx 2707380 │ │ str.w r0, [r8, #4] │ │ mov.w r8, #1 │ │ b.n 217ab5c >&, StarDatabase const&)@@Base+0x3e8> │ │ nop │ │ - ldr r3, [sp, #320] @ 0x140 │ │ + ldr r3, [sp, #500] @ 0x1f4 │ │ cdp2 1, 0, cr15, cr11, cr5, {4} │ │ b.n 217ae32 , std::__ndk1::allocator > >* std::__ndk1::vector, std::__ndk1::allocator > >, std::__ndk1::allocator, std::__ndk1::allocator > > > >::__push_back_slow_path, std::__ndk1::allocator > > >(std::__ndk1::vector, std::__ndk1::allocator > >&&)@@Base+0x116> │ │ mov r4, r0 │ │ ldr r0, [r0, #8] │ │ cmp r0, #0 │ │ bmi.n 217ac28 >&, StarDatabase const&)@@Base+0x4b4> │ │ ldr r0, [pc, #236] @ (217acf4 >&, StarDatabase const&)@@Base+0x580>) │ │ @@ -377745,21 +377745,21 @@ │ │ add r0, sp, #88 @ 0x58 │ │ blx 2701ca0 │ │ ldr r0, [sp, #20] │ │ bl 208835c │ │ blx 26ffb60 │ │ ldmia r6!, {r2, r5, r7} │ │ lsls r3, r3, #1 │ │ - str r5, [r7, #8] │ │ - mcr2 0, 0, r6, cr10, cr1, {5} │ │ - mcr2 3, 0, sl, cr10, cr0, {5} │ │ - cdp2 0, 0, cr0, cr10, cr0, {2} │ │ + str r2, [r5, #12] │ │ + mcr2 0, 0, r6, cr10, cr14, {6} │ │ + mcr2 3, 0, sl, cr10, cr13, {6} │ │ + cdp2 0, 0, cr0, cr10, cr13, {3} │ │ cdp2 12, 0, cr1, cr11, cr8, {3} │ │ - mcr2 0, 0, r4, cr12, cr15, {4} │ │ - cdp2 0, 0, cr4, cr10, cr15, {4} │ │ + cdp2 0, 0, cr4, cr12, cr12, {6} │ │ + mcr2 0, 0, r4, cr10, cr12, {5} │ │ cdp2 4, 0, cr1, cr10, cr3, {6} │ │ cdp2 4, 0, cr1, cr13, cr5, {5} │ │ mcr2 9, 0, ip, cr13, cr10, {7} @ │ │ lsls r3, r3, #1 │ │ │ │ 0217ad1c , std::__ndk1::allocator > >* std::__ndk1::vector, std::__ndk1::allocator > >, std::__ndk1::allocator, std::__ndk1::allocator > > > >::__push_back_slow_path, std::__ndk1::allocator > > >(std::__ndk1::vector, std::__ndk1::allocator > >&&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -389880,15 +389880,15 @@ │ │ movs r2, #0 │ │ ldr.w r8, [sp], #4 │ │ ldmia.w sp!, {r4, r5, r6, r7, lr} │ │ b.w 26ff134 │ │ mov r0, r5 │ │ bl 2093dd8 , std::__ndk1::allocator > fmt::v11::detail::vformat(std::__ndk1::locale const&, fmt::v11::basic_string_view, fmt::v11::detail::vformat_args::type)@@Base+0x130> │ │ bl 207deaa │ │ - lsrs r4, r7, #24 │ │ + lsrs r1, r5, #25 │ │ Address 0x21835e6 is out of bounds. │ │ │ │ │ │ 021835e8 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -394918,15 +394918,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #32] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ lsrs r2, r5, #21 │ │ lsls r3, r3, #1 │ │ - bge.n 2186a0c , std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > >&, std::__ndk1::basic_string_view >, bool) const@@Base+0x15c> │ │ + bge.n 2186a66 , std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > >&, std::__ndk1::basic_string_view >, bool) const@@Base+0x1b6> │ │ @ instruction: 0xfe0a0b66 │ │ lsls r3, r3, #1 │ │ │ │ 02186b10 : │ │ ldrb.w r3, [r1, #224] @ 0xe0 │ │ lsls r3, r3, #30 │ │ it pl │ │ @@ -401728,16 +401728,16 @@ │ │ blxne 26ffb40 │ │ add r0, sp, #56 @ 0x38 │ │ bl 217a6a8 , std::__ndk1::allocator >&&, std::__ndk1::vector, std::__ndk1::allocator > >, std::__ndk1::allocator, std::__ndk1::allocator > > > >&&)@@Base+0x150> │ │ blx 26ffb60 │ │ nop │ │ ldmia r0!, {r3, r5} │ │ lsls r2, r3, #1 │ │ - adds r1, #45 @ 0x2d │ │ - cdp2 12, 0, cr3, cr10, cr5, {1} │ │ + adds r1, #90 @ 0x5a │ │ + mcr2 12, 0, r3, cr10, cr2, {2} │ │ cdp2 4, 0, cr12, cr9, cr4, {5} │ │ lsls r2, r3, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ ldr r2, [pc, #172] @ (218b2c0 >&)@@Base+0x4d0>) │ │ add r2, pc │ │ @@ -401810,15 +401810,15 @@ │ │ ldr r0, [pc, #12] @ (218b2c8 >&)@@Base+0x4d8>) │ │ add r0, pc │ │ bl 2093de8 , std::__ndk1::allocator > fmt::v11::detail::vformat(std::__ndk1::locale const&, fmt::v11::basic_string_view, fmt::v11::detail::vformat_args::type)@@Base+0x140> │ │ stmia r4!, {r3, r4} │ │ lsls r2, r3, #1 │ │ stmia r3!, {r2, r5, r6, r7} │ │ lsls r2, r3, #1 │ │ - adds r0, #29 │ │ + adds r0, #74 @ 0x4a │ │ Address 0x218b2ca is out of bounds. │ │ │ │ │ │ 0218b2cc , std::__ndk1::allocator > >* std::__ndk1::vector, std::__ndk1::allocator > >, std::__ndk1::allocator, std::__ndk1::allocator > > > >::__emplace_back_slow_path, std::__ndk1::allocator > > >(std::__ndk1::vector, std::__ndk1::allocator > >&&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -407319,16 +407319,16 @@ │ │ ldr r0, [pc, #20] @ (218eaa0 >)@@Base+0xdc>) │ │ add r0, pc │ │ bl 2093de8 , std::__ndk1::allocator > fmt::v11::detail::vformat(std::__ndk1::locale const&, fmt::v11::basic_string_view, fmt::v11::detail::vformat_args::type)@@Base+0x140> │ │ nop │ │ ldrh r2, [r0, r5] │ │ lsls r1, r3, #1 │ │ bls.n 218ea1c >)@@Base+0x58> │ │ - mrc2 9, 0, r5, cr0, cr1, {6} @ │ │ - vcmla.f16 , q5, d11[0], #0 │ │ + mrc2 9, 0, r5, cr0, cr14, {7} @ │ │ + vfmal.f16 , d10, d0[3] │ │ vcmla.f16 q3, , d1[0], #0 │ │ cmp r1, #0 │ │ it eq │ │ bxeq lr │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ str r1, [r0, #8] │ │ @@ -412282,23 +412282,23 @@ │ │ movs r1, #251 @ 0xfb │ │ ands r1, r1 │ │ movs r0, r0 │ │ movs r0, r0 │ │ lsls r3, r3, #4 │ │ mcr2 14, 0, r4, cr8, cr4, {6} │ │ lsls r2, r3, #1 │ │ - ldrsh r2, [r2, r7] │ │ - cdp2 3, 0, cr8, cr9, cr4, {5} │ │ + ldrsh r7, [r7, r7] │ │ + mcr2 3, 0, r8, cr9, cr1, {6} │ │ cdp2 14, 0, cr6, cr9, cr13, {7} │ │ cdp2 1, 0, cr8, cr11, cr7, {7} │ │ - mcr2 5, 0, sl, cr10, cr8, {3} │ │ - mcr2 0, 0, sl, cr9, cr1, {5} │ │ - cdp2 3, 0, cr4, cr8, cr5, {4} │ │ - cdp2 14, 0, cr5, cr9, cr14, {4} │ │ - cdp2 1, 0, cr12, cr10, cr7, {6} │ │ + cdp2 5, 0, cr10, cr10, cr5, {5} │ │ + mcr2 0, 0, sl, cr9, cr14, {6} │ │ + mcr2 3, 0, r4, cr8, cr2, {5} │ │ + mcr2 14, 0, r5, cr9, cr11, {5} │ │ + mcr2 1, 0, ip, cr10, cr4, {7} │ │ vdot.bf16 d9, d8, d1[0] │ │ mcr2 12, 0, r4, cr10, cr8, {1} │ │ lsls r2, r3, #1 │ │ │ │ 02192a60 , std::__ndk1::allocator > const&, std::__ndk1::__fs::filesystem::path const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -412456,15 +412456,15 @@ │ │ mov r0, r9 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ ldr r3, [pc, #744] @ (2192ed0 ) │ │ lsls r2, r3, #1 │ │ strh r1, [r2, #24] │ │ - mcr2 13, 0, r5, cr8, cr6, {1} │ │ + vdot.bf16 , q4, d3[1] │ │ mcr2 10, 0, r4, cr10, cr12, {3} @ │ │ lsls r2, r3, #1 │ │ │ │ 02192bf4 : │ │ ldr r1, [pc, #40] @ (2192c20 ) │ │ ldrb.w r2, [r0, #60] @ 0x3c │ │ add r1, pc │ │ @@ -412776,15 +412776,15 @@ │ │ pop {r4, r5, r6, r7, pc} │ │ mov r0, r9 │ │ bl 207d3d8 │ │ mov r0, sl │ │ bl 2093dd8 , std::__ndk1::allocator > fmt::v11::detail::vformat(std::__ndk1::locale const&, fmt::v11::basic_string_view, fmt::v11::detail::vformat_args::type)@@Base+0x130> │ │ bl 207deaa │ │ nop │ │ - asrs r6, r7, #21 │ │ + asrs r3, r5, #22 │ │ Address 0x2192ef6 is out of bounds. │ │ │ │ │ │ 02192ef8 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -412854,15 +412854,15 @@ │ │ ldrb r0, [r4, #0] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [r4, #8] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ - asrs r6, r3, #18 │ │ + asrs r3, r1, #19 │ │ cdp2 1, 0, cr9, cr10, cr13, {4} │ │ Address 0x2192faa is out of bounds. │ │ │ │ │ │ 02192fac >, double>&, Eigen::Matrix const&, Eigen::Quaternion const&, float, float, float) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -413547,21 +413547,21 @@ │ │ strd fp, fp, [sp] │ │ blx 26ffe60 │ │ movs r4, #2 │ │ b.n 2193856 >&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x4f2> │ │ nop │ │ ldr r7, [r1, #4] │ │ mcr2 14, 0, r4, cr11, cr3, {7} │ │ - mcr2 14, 0, r2, cr11, cr2, {4} │ │ + mcr2 14, 0, r2, cr11, cr15, {5} │ │ mcr2 3, 0, r1, cr10, cr8, {0} │ │ - mcr2 0, 0, pc, cr8, cr7, {3} @ │ │ + cdp2 0, 0, cr15, cr8, cr4, {5} │ │ vcmla.f16 d7, d25, d15[1], #0 │ │ vcmla.f16 d7, d24, d3[1], #0 │ │ - mcr2 9, 0, r1, cr8, cr13, {5} @ │ │ - mcr2 9, 0, r1, cr9, cr15, {4} @ │ │ + @ instruction: 0xfe0819ea │ │ + @ instruction: 0xfe0919cc │ │ mcr2 9, 0, lr, cr9, cr6, {6} @ │ │ movs r1, #1 │ │ add r6, sp, #104 @ 0x68 │ │ mov r0, r6 │ │ bl 207d390 │ │ mov r0, r5 │ │ mov r1, r4 │ │ @@ -413752,17 +413752,17 @@ │ │ lsls r2, r3, #1 │ │ add r6, pc │ │ lsls r2, r3, #1 │ │ add r2, r4 │ │ lsls r2, r3, #1 │ │ strb r1, [r6, #27] │ │ cdp2 6, 0, cr7, cr8, cr5, {7} │ │ - cdp2 3, 0, cr15, cr8, cr3, {0} │ │ - mcr2 2, 0, pc, cr8, cr7, {7} @ │ │ - mcr2 10, 0, sl, cr8, cr15, {0} @ │ │ + mcr2 3, 0, pc, cr8, cr0, {1} @ │ │ + cdp2 3, 0, cr15, cr8, cr4, {1} │ │ + @ instruction: 0xfe08aa4c │ │ mcr2 13, 0, r3, cr9, cr6, {4} │ │ lsls r2, r3, #1 │ │ bmi.n 2193910 >&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x5ac> │ │ bmi.n 2193912 >&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x5ae> │ │ bmi.n 2193914 >&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x5b0> │ │ bmi.n 2193916 >&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x5b2> │ │ bmi.n 2193918 >&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x5b4> │ │ @@ -414944,16 +414944,16 @@ │ │ mov.w r8, #0 │ │ mov fp, sl │ │ str r5, [sp, #92] @ 0x5c │ │ adds r0, #1 │ │ str r0, [sp, #96] @ 0x60 │ │ str r1, [sp, #84] @ 0x54 │ │ b.n 21946e8 │ │ - b.n 2194a66 │ │ - mcr2 1, 0, lr, cr9, cr11, {5} │ │ + b.n 2194ac0 │ │ + cdp2 1, 0, cr14, cr9, cr8, {7} │ │ cdp2 12, 0, cr3, cr9, cr4, {5} │ │ lsls r2, r3, #1 │ │ ldr r0, [sp, #96] @ 0x60 │ │ strd r9, r0, [r6], #8 │ │ str r6, [sp, #172] @ 0xac │ │ add.w r8, r8, #4 │ │ cmp.w r8, #32 │ │ @@ -423291,15 +423291,15 @@ │ │ blx 26ffb50 │ │ ldr r0, [sp, #28] │ │ cmp r0, r9 │ │ it ne │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ - add r6, sp, #944 @ 0x3b0 │ │ + add r7, sp, #100 @ 0x64 │ │ cdp2 5, 0, cr13, cr8, cr6, {6} │ │ lsls r1, r3, #1 │ │ bvs.n 219a188 const&, double&, double&) const@@Base+0x4c> │ │ lsls r1, r3, #1 │ │ bpl.n 219a194 const&, double&, double&) const@@Base+0x58> │ │ lsls r1, r3, #1 │ │ │ │ @@ -423629,15 +423629,15 @@ │ │ ldrb.w r0, [sp, #32] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #40] @ 0x28 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ - add lr, r7 │ │ + add fp, sp │ │ mcr2 2, 0, sp, cr9, cr10, {0} │ │ lsls r1, r3, #1 │ │ ldrsb r4, [r3, r2] │ │ vseleq.f32 s6, s22, s16 │ │ cdp2 1, 0, cr13, cr11, cr14, {2} │ │ lsls r1, r3, #1 │ │ │ │ @@ -424684,15 +424684,15 @@ │ │ str r1, [sp, #52] @ 0x34 │ │ adds r0, #28 │ │ b.n 219b134 │ │ ldmia r5!, {r3, r4, r6} │ │ lsls r1, r3, #1 │ │ ldr r1, [sp, #936] @ 0x3a8 │ │ mcr2 0, 0, lr, cr7, cr13, {3} │ │ - cdp2 4, 0, cr11, cr7, cr9, {1} │ │ + mcr2 4, 0, fp, cr7, cr6, {2} │ │ vseleq.f64 d4, d9, d31 │ │ vseleq.f16 s20, s22, s22 │ │ mov r0, r5 │ │ blx 27082b0 │ │ ldrb.w r1, [sp, #68] @ 0x44 │ │ str r0, [r5, #4] │ │ cmp r1, #0 │ │ @@ -424915,18 +424915,18 @@ │ │ strne r0, [sp, #36] @ 0x24 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ ldrh r4, [r3, #58] @ 0x3a │ │ subs r7, #66 @ 0x42 │ │ ldmia r4, {r1, r2, r4, r5, r7} │ │ lsls r1, r3, #1 │ │ - ldr r7, [sp, #188] @ 0xbc │ │ - vfmal.f16 d3, s16, s2[0] │ │ + ldr r7, [sp, #368] @ 0x170 │ │ + vfmal.f16 d3, s16, s13[1] │ │ cdp2 5, 0, cr1, cr9, cr3, {4} │ │ - cdp2 3, 0, cr7, cr10, cr1, {6} │ │ + cdp2 3, 0, cr7, cr10, cr14, {7} │ │ cdp2 3, 0, cr12, cr9, cr8, {2} │ │ lsls r1, r3, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ ldr r5, [r0, #0] │ │ mov r4, r0 │ │ @@ -425443,15 +425443,15 @@ │ │ vmov r2, s0 │ │ vmul.f32 s2, s2, s21 │ │ vdiv.f32 s29, s2, s23 │ │ b.n 219bb8e │ │ nop │ │ stmia r3!, {r5} │ │ lsls r1, r3, #1 │ │ - ldr r1, [r3, #104] @ 0x68 │ │ + ldr r6, [r0, #108] @ 0x6c │ │ cdp2 2, 0, cr12, cr9, cr14, {2} │ │ lsls r1, r3, #1 │ │ asrs r7, r5, #9 │ │ subs r4, #3 │ │ movs r0, r0 │ │ subs r3, #128 @ 0x80 │ │ adds r3, #51 @ 0x33 │ │ @@ -428089,34 +428089,34 @@ │ │ itttt eq │ │ moveq r0, #1 │ │ addeq sp, #24 │ │ ldmiaeq.w sp!, {r8, r9, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ bl 207deaa │ │ - bmi.n 219d97a , std::__ndk1::allocator > >)@@Base+0x2a2> │ │ + bmi.n 219d7d4 , std::__ndk1::allocator > >)@@Base+0xfc> │ │ cdp2 15, 0, cr9, cr8, cr0, {2} │ │ lsls r1, r3, #1 │ │ add r3, pc, #344 @ (adr r3, 219d9f8 , std::__ndk1::allocator > >)@@Base+0x320>) │ │ lsls r1, r3, #1 │ │ - ldrh r1, [r4, #34] @ 0x22 │ │ - cdp2 4, 0, cr1, cr9, cr11, {3} │ │ + ldrh r6, [r1, #36] @ 0x24 │ │ + mcr2 4, 0, r1, cr9, cr8, {4} │ │ cdp2 4, 0, cr10, cr8, cr4, {0} │ │ lsls r1, r3, #1 │ │ stmia r5!, {r1, r3, r4, r6} │ │ cdp2 1, 0, cr1, cr10, cr0, {0} │ │ cdp2 3, 0, cr10, cr10, cr2, {7} │ │ lsls r1, r3, #1 │ │ movs r3, #163 @ 0xa3 │ │ mcr2 3, 0, sl, cr11, cr2, {6} │ │ lsls r1, r3, #1 │ │ - asrs r2, r0, #6 │ │ + asrs r7, r5, #6 │ │ cdp2 3, 0, cr10, cr9, cr2, {6} │ │ lsls r1, r3, #1 │ │ - sub sp, #200 @ 0xc8 │ │ + sub sp, #380 @ 0x17c │ │ cdp2 6, 0, cr13, cr9, cr6, {6} │ │ cdp2 3, 0, cr10, cr7, cr0, {5} │ │ lsls r1, r3, #1 │ │ strd pc, lr, [pc], #40 @ 219d900 , std::__ndk1::allocator > >)@@Base+0x228> @ 0x28 │ │ add r3, pc, #560 @ (adr r3, 219db0c ) │ │ lsls r1, r3, #1 │ │ add r3, pc, #216 @ (adr r3, 219d9b8 , std::__ndk1::allocator > >)@@Base+0x2e0>) │ │ @@ -428129,16 +428129,16 @@ │ │ lsls r1, r3, #1 │ │ ldr r7, [sp, #416] @ 0x1a0 │ │ lsls r1, r3, #1 │ │ add r3, pc, #240 @ (adr r3, 219d9e4 , std::__ndk1::allocator > >)@@Base+0x30c>) │ │ lsls r1, r3, #1 │ │ add r3, pc, #208 @ (adr r3, 219d9c8 , std::__ndk1::allocator > >)@@Base+0x2f0>) │ │ lsls r1, r3, #1 │ │ - ldrh r1, [r3, #26] │ │ - mcr2 3, 0, sp, cr9, cr6, {1} │ │ + ldrh r6, [r0, #28] │ │ + cdp2 3, 0, cr13, cr9, cr3, {3} │ │ mcr2 1, 0, sp, cr8, cr4, {6} │ │ cdp2 0, 0, cr1, cr9, cr0, {5} │ │ lsls r4, r3, #1 │ │ ldr r5, [sp, #720] @ 0x2d0 │ │ lsls r1, r3, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -429183,22 +429183,22 @@ │ │ ldc2l 3, cr4, [r1, #-508]! @ 0xfffffe04 │ │ movs r0, r0 │ │ movs r0, r0 │ │ str r7, [sp, #632] @ 0x278 │ │ lsls r1, r3, #1 │ │ str r5, [sp, #224] @ 0xe0 │ │ lsls r1, r3, #1 │ │ - ldrb r5, [r3, #18] │ │ + ldrb r2, [r1, #19] │ │ mcr2 0, 0, r4, cr9, cr3, {6} │ │ - vseleq.f64 d6, d26, d14 │ │ - mcr2 1, 0, r4, cr8, cr1, {3} │ │ + mcr2 11, 0, r6, cr10, cr11, {5} @ │ │ + mcr2 1, 0, r4, cr8, cr14, {4} │ │ mcr2 3, 0, r2, cr8, cr5, {1} │ │ cdp2 0, 0, cr4, cr10, cr1, {4} │ │ mcr2 10, 0, pc, cr10, cr3, {2} @ │ │ - vfmal.f16 d2, s21, s1[0] │ │ + vfmal.f16 q1, d26, d5[1] │ │ mcr2 1, 0, r9, cr8, cr6, {5} │ │ lsls r1, r3, #1 │ │ bmi.n 219e4c4 │ │ bmi.n 219e4c6 │ │ bmi.n 219e4c8 │ │ bmi.n 219e4ca │ │ │ │ @@ -429410,19 +429410,19 @@ │ │ lsrs r3, r3, #31 │ │ eors r1, r1 │ │ movs r0, r0 │ │ cmn r0, r1 │ │ ldrh r6, [r7, #10] │ │ cdp2 0, 0, cr9, cr7, cr10, {7} │ │ lsls r1, r3, #1 │ │ - ldrb r1, [r5, #9] │ │ - cdp2 14, 0, cr15, cr9, cr2, {3} │ │ + ldrb r6, [r2, #10] │ │ + cdp2 14, 0, cr15, cr9, cr15, {4} │ │ mcr2 0, 0, lr, cr7, cr12, {3} │ │ mcr2 3, 0, pc, cr9, cr14, {1} @ │ │ - mcr2 14, 0, r7, cr10, cr4, {4} │ │ + cdp2 14, 0, cr7, cr10, cr1, {6} │ │ cdp2 14, 0, cr8, cr8, cr0, {7} │ │ lsls r1, r3, #1 │ │ bmi.n 219e754 │ │ bmi.n 219e756 │ │ bmi.n 219e758 │ │ bmi.n 219e75a │ │ │ │ @@ -429593,15 +429593,15 @@ │ │ lsls r1, r3, #1 │ │ │ │ 0219e970 : │ │ ldr r0, [pc, #4] @ (219e978 ) │ │ add r0, pc │ │ bx lr │ │ nop │ │ - ldrb r0, [r3, #7] │ │ + ldrb r5, [r0, #8] │ │ Address 0x219e97a is out of bounds. │ │ │ │ │ │ 0219e97c , std::__ndk1::allocator > const&)@@Base>: │ │ bx lr │ │ bmi.n 219e92a │ │ │ │ @@ -429704,15 +429704,15 @@ │ │ ldr r1, [r1, #0] │ │ ldr r1, [r1, #0] │ │ cmp r1, r0 │ │ itt eq │ │ addeq sp, #8 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ - svc 118 @ 0x76 │ │ + svc 163 @ 0xa3 │ │ mcr2 11, 0, r8, cr7, cr0, {6} @ │ │ lsls r1, r3, #1 │ │ ldrh r6, [r5, #28] │ │ lsls r1, r3, #1 │ │ │ │ 0219ea9c , std::__ndk1::allocator > fmt::v11::sprintf(char* const&, float const&, float const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -430074,17 +430074,17 @@ │ │ negs r0, r6 │ │ movs r0, r0 │ │ orrs r4, r6 │ │ lsrs r3, r3, #31 │ │ eors r1, r1 │ │ ldrh r4, [r4, #6] │ │ lsls r1, r3, #1 │ │ - pacg lr, r8, r8 │ │ + @ instruction: 0xfb95fe08 │ │ bcc.n 219eeee │ │ - @ instruction: 0xfe0afb46 │ │ + mcr2 11, 0, pc, cr10, cr3, {3} @ │ │ mcr2 7, 0, r8, cr8, cr2, {4} │ │ lsls r1, r3, #1 │ │ │ │ 0219eee0 : │ │ mov.w r0, #1048576 @ 0x100000 │ │ movs r1, #0 │ │ bx lr │ │ @@ -430830,15 +430830,15 @@ │ │ nop │ │ strh r6, [r0, #62] @ 0x3e │ │ lsls r1, r3, #1 │ │ strh r4, [r2, #18] │ │ lsls r1, r3, #1 │ │ strh r2, [r7, #58] @ 0x3a │ │ lsls r1, r3, #1 │ │ - adds r6, r0, r1 │ │ + adds r3, r6, r1 │ │ cdp2 7, 0, cr8, cr8, cr4, {3} │ │ lsls r1, r3, #1 │ │ strh r6, [r1, #60] @ 0x3c │ │ lsls r1, r3, #1 │ │ strh r2, [r3, #58] @ 0x3a │ │ lsls r1, r3, #1 │ │ strh r4, [r1, #58] @ 0x3a │ │ @@ -431032,15 +431032,15 @@ │ │ lsls r1, r3, #1 │ │ strh r0, [r2, #0] │ │ lsls r1, r3, #1 │ │ strh r4, [r7, #42] @ 0x2a │ │ lsls r1, r3, #1 │ │ strh r0, [r1, #42] @ 0x2a │ │ lsls r1, r3, #1 │ │ - bl 1ee32f6 │ │ + bl 1f102f6 │ │ ldrb r2, [r0, #30] │ │ lsls r1, r3, #1 │ │ │ │ 0219f6ec , std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const&, GLGeometryShader**)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -431129,15 +431129,15 @@ │ │ lsls r1, r3, #1 │ │ ldrb r0, [r5, #28] │ │ lsls r1, r3, #1 │ │ strh r0, [r3, #36] @ 0x24 │ │ lsls r1, r3, #1 │ │ strh r0, [r4, #34] @ 0x22 │ │ lsls r1, r3, #1 │ │ - ldr r4, [r7, #64] @ 0x40 │ │ + ldr r1, [r5, #68] @ 0x44 │ │ mcr2 14, 0, r7, cr9, cr10, {4} │ │ lsls r1, r3, #1 │ │ │ │ 0219f7d4 , std::__ndk1::allocator > const&, GLVertexShader**)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -433805,15 +433805,15 @@ │ │ pop {r4, r5, r6, r7, pc} │ │ mov r0, r8 │ │ movs r1, #0 │ │ movs r2, #0 │ │ ldr.w r8, [sp], #4 │ │ ldmia.w sp!, {r4, r5, r6, r7, lr} │ │ b.w 26ff134 │ │ - adds r2, #54 @ 0x36 │ │ + adds r2, #99 @ 0x63 │ │ Address 0x21a11fe is out of bounds. │ │ │ │ │ │ 021a1200 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -438632,15 +438632,15 @@ │ │ lsls r1, r3, #1 │ │ adds r5, #116 @ 0x74 │ │ lsls r1, r3, #1 │ │ ldrb r5, [r2, #8] │ │ cdp2 15, 0, cr2, cr10, cr4, {6} │ │ lsls r1, r3, #1 │ │ ldrb r5, [r0, #8] │ │ - cdp2 2, 0, cr10, cr10, cr1, {1} │ │ + cdp2 2, 0, cr10, cr10, cr14, {2} │ │ cdp2 15, 0, cr2, cr8, cr0, {2} │ │ lsls r1, r3, #1 │ │ cbz r6, 21a49e6 │ │ cdp2 12, 0, cr3, cr10, cr12, {0} │ │ mcr2 14, 0, r2, cr10, cr8, {5} │ │ lsls r1, r3, #1 │ │ subs r3, #242 @ 0xf2 │ │ @@ -440501,28 +440501,28 @@ │ │ vpopeq {d8-d11} │ │ addeq sp, #4 │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ it eq │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ - lsrs r5, r0, #2 │ │ - vfmal.f16 q0, d9, d1[3] │ │ + lsrs r2, r6, #2 │ │ + vcmla.f16 d0, d25, d6[1], #0 │ │ mcr2 3, 0, r3, cr9, cr4, {0} │ │ mcr2 10, 0, r1, cr7, cr4, {1} @ │ │ lsls r1, r3, #1 │ │ adds r3, #4 │ │ vseleq.f32 s2, s14, s24 │ │ lsls r1, r3, #1 │ │ adds r6, r2, r6 │ │ lsls r1, r3, #1 │ │ adds r2, r0, #1 │ │ lsls r1, r3, #1 │ │ add r1, sp, #888 @ 0x378 │ │ - mcr2 12, 0, sl, cr9, cr9, {2} │ │ + cdp2 12, 0, cr10, cr9, cr6, {4} │ │ vfmal.f16 , d8, d0[2] │ │ lsls r1, r3, #1 │ │ add r0, sp, #112 @ 0x70 │ │ add r1, sp, #232 @ 0xe8 │ │ blx 2701cb0 │ │ ldrb.w r0, [sp, #112] @ 0x70 │ │ cmp r0, #4 │ │ @@ -440838,19 +440838,19 @@ │ │ b.n 21a62d6 │ │ nop │ │ b.n 21a5a66 │ │ cdp2 12, 0, cr9, cr9, cr5, {1} │ │ mcr2 7, 0, r1, cr10, cr6, {2} │ │ lsls r1, r3, #1 │ │ ldr r4, [sp, #84] @ 0x54 │ │ - mcr2 0, 0, pc, cr10, cr2, {0} @ │ │ - mcr2 5, 0, lr, cr7, cr11, {2} │ │ + mcr2 0, 0, pc, cr10, cr15, {1} @ │ │ + cdp2 5, 0, cr14, cr7, cr8, {4} │ │ cdp2 0, 0, cr0, cr8, cr0, {0} │ │ movs r0, r0 │ │ - add r2, sp, #484 @ 0x1e4 │ │ + add r2, sp, #664 @ 0x298 │ │ mcr2 14, 0, r0, cr8, cr0, {6} │ │ mcr2 7, 0, lr, cr7, cr13, {6} │ │ vcmla.f16 d10, d6, d15[1], #0 │ │ bl 21a6b40 ::InfoType>::construct[abi:ne180000]::InfoType, TextureInfo const&>(ResourceManager::InfoType*, TextureInfo const&)@@Base+0x15c> │ │ b.n 21a62a6 │ │ b.n 21a625e │ │ b.n 21a625e │ │ @@ -442971,15 +442971,15 @@ │ │ ldrb.w r0, [sp] │ │ lsls r0, r0, #31 │ │ beq.n 21a77a4 │ │ ldr r0, [sp, #8] │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ vshr.u32 q8, q4, #14 │ │ - asrs r0, r6, #23 │ │ + asrs r5, r3, #24 │ │ @ instruction: 0xfe08daea │ │ lsls r7, r2, #1 │ │ mcr2 0, 7, r0, cr0, cr8, {2} │ │ │ │ 021a77b8 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -443253,26 +443253,26 @@ │ │ b.n 21a7a72 │ │ add r0, sp, #28 │ │ blx 26ffe80 │ │ blx 26ffb60 │ │ mcr2 0, 3, r0, cr4, cr8, {2} │ │ ldc2 0, cr0, [sl], {88} @ 0x58 │ │ stc2 0, cr0, [lr], #-352 @ 0xfffffea0 │ │ - ldmia r4, {r0, r1, r4, r5, r6, r7} │ │ - cdp2 12, 0, cr12, cr8, cr7, {7} │ │ + ldmia r5, {r5} │ │ + mcr2 13, 0, ip, cr8, cr4, {0} │ │ cdp2 12, 0, cr10, cr8, cr10, {0} │ │ mcr2 11, 0, sl, cr9, cr12, {7} @ │ │ - mcr2 12, 0, ip, cr9, cr11, {4} │ │ - cdp2 12, 0, cr12, cr8, cr15, {4} │ │ + cdp2 12, 0, cr12, cr9, cr8, {6} │ │ + mcr2 12, 0, ip, cr8, cr12, {5} │ │ mcr2 5, 0, r6, cr8, cr0, {6} │ │ cdp2 5, 0, cr6, cr10, cr4, {6} │ │ - cdp2 14, 0, cr0, cr10, cr12, {5} │ │ - cdp2 14, 0, cr0, cr9, cr0, {5} │ │ - mcr2 15, 0, r4, cr9, cr0, {7} │ │ - mcr2 15, 0, r4, cr7, cr10, {6} │ │ + mcr2 14, 0, r0, cr10, cr9, {6} │ │ + cdp2 14, 0, cr0, cr9, cr13, {6} │ │ + mcr2 0, 0, r5, cr9, cr13, {0} │ │ + cdp2 0, 0, cr5, cr7, cr7, {0} │ │ Address 0x21a7ab6 is out of bounds. │ │ │ │ │ │ 021a7ab8 ::~ResourceManager()@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -443844,15 +443844,15 @@ │ │ strne r0, [sp, #48] @ 0x30 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ ldr??.w r0, [r6, r8, lsl #1] │ │ ldrh r2, [r0, r0] │ │ @ instruction: 0xfe0f59ec │ │ - cdp2 3, 0, cr14, cr15, cr7, {6} │ │ + mcr2 3, 0, lr, cr15, cr4, {7} │ │ mcr2 5, 0, pc, cr8, cr0, {6} @ │ │ lsls r0, r3, #1 │ │ │ │ 021a80c4 : │ │ ldr r0, [r0, #4] │ │ ldrb r0, [r0, #28] │ │ bx lr │ │ @@ -445420,15 +445420,15 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ b.n 21a8fbc >)@@Base+0x140> │ │ lsls r0, r3, #1 │ │ b.n 21a903c >)@@Base+0x1c0> │ │ lsls r0, r3, #1 │ │ - push {r1, r2, r3, r5, r6, r7} │ │ + push {r0, r1, r3, r4, lr} │ │ mcr2 5, 0, lr, cr8, cr6, {7} │ │ lsls r0, r3, #1 │ │ │ │ 021a9088 : │ │ push {r7, lr} │ │ mov r7, sp │ │ sub sp, #8 │ │ @@ -457350,15 +457350,15 @@ │ │ bmi.n 21b1bf6 >::~__shared_ptr_emplace()@@Base+0x1a> │ │ │ │ 021b1c4c : │ │ ldr r0, [pc, #4] @ (21b1c54 ) │ │ add r0, pc │ │ bx lr │ │ nop │ │ - strb r1, [r7, #0] │ │ + strb r6, [r4, #1] │ │ Address 0x21b1c56 is out of bounds. │ │ │ │ │ │ 021b1c58 , std::__ndk1::allocator > const&)@@Base>: │ │ bx lr │ │ bmi.n 21b1c06 >::~__shared_ptr_emplace()@@Base+0x2a> │ │ │ │ @@ -457394,15 +457394,15 @@ │ │ blx 26fe3a0 │ │ movs r0, #0 │ │ strb r0, [r4, r5] │ │ ldr.w r8, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ mov r0, r4 │ │ bl 207d3d8 │ │ - strb r7, [r3, #0] │ │ + strb r4, [r1, #1] │ │ Address 0x21b1cba is out of bounds. │ │ │ │ │ │ 021b1cbc : │ │ movs r0, #3 │ │ bx lr │ │ │ │ @@ -458768,33 +458768,33 @@ │ │ cdp2 15, 0, cr11, cr9, cr0, {0} │ │ nop │ │ str r6, [r4, #100] @ 0x64 │ │ ldrb r6, [r4, r5] │ │ bpl.n 21b2b9a │ │ sbcs r1, r4 │ │ ldr r0, [sp, #512] @ 0x200 │ │ - mcr2 13, 0, r7, cr9, cr8, {3} │ │ + vdot.bf16 d7, d25, d5[1] │ │ mcr2 6, 0, r3, cr7, cr12, {7} │ │ - vseleq.f64 d3, d25, d18 │ │ - mcr2 4, 0, lr, cr8, cr11, {3} │ │ - mcr2 3, 0, ip, cr6, cr15, {0} │ │ + @ instruction: 0xfe093bcf │ │ + cdp2 4, 0, cr14, cr8, cr8, {5} │ │ + cdp2 3, 0, cr12, cr6, cr12, {2} │ │ cdp2 14, 0, cr9, cr6, cr2, {3} │ │ mcr2 5, 0, fp, cr8, cr6, {6} │ │ cdp2 5, 0, cr11, cr9, cr10, {6} │ │ - mcr2 0, 0, sl, cr9, cr8, {6} │ │ + cdp2 1, 0, cr10, cr9, cr5, {0} │ │ cdp2 5, 0, cr8, cr6, cr15, {2} │ │ cdp2 5, 0, cr8, cr6, cr3, {2} │ │ cdp2 14, 0, cr15, cr6, cr14, {7} │ │ cdp2 14, 0, cr15, cr5, cr2, {7} │ │ - mcr2 0, 0, sl, cr5, cr4, {5} │ │ - cdp2 0, 0, cr10, cr6, cr8, {5} │ │ + cdp2 0, 0, cr10, cr5, cr1, {7} │ │ + mcr2 0, 0, sl, cr6, cr5, {6} │ │ mcr2 14, 0, fp, cr6, cr0, {4} │ │ cdp2 14, 0, cr11, cr8, cr4, {4} │ │ - mcr2 3, 0, sl, cr8, cr9, {7} │ │ - cdp2 3, 0, cr10, cr7, cr13, {7} │ │ + cdp2 4, 0, cr10, cr8, cr6, {1} │ │ + mcr2 4, 0, sl, cr7, cr10, {0} │ │ cdp2 0, 0, cr2, cr7, cr0, {0} │ │ cmp.w r9, #0 │ │ mov r6, fp │ │ strd r0, r0, [sp, #48] @ 0x30 │ │ strd r0, r0, [sp, #96] @ 0x60 │ │ beq.n 21b2b6e │ │ add.w r0, r9, #4 │ │ @@ -459169,37 +459169,37 @@ │ │ ldr r2, [pc, #104] @ (21b2f74 ) │ │ movs r1, #0 │ │ add r3, sp, #96 @ 0x60 │ │ strd r3, r1, [sp, #8] │ │ add r2, pc │ │ movs r3, #51 @ 0x33 │ │ b.n 21b2f90 │ │ - stmia r0!, {r0, r1, r2, r4, r5, r6} │ │ + stmia r0!, {r2, r5, r7} │ │ mcr2 11, 0, r9, cr6, cr0, {5} @ │ │ - mcr2 10, 0, pc, cr8, cr12, {0} @ │ │ + @ instruction: 0xfe08fa49 │ │ mcr2 9, 0, pc, cr7, cr4, {0} @ │ │ - cdp2 0, 0, cr6, cr8, cr14, {2} │ │ - cdp2 0, 0, cr6, cr7, cr2, {2} │ │ - cdp2 1, 0, cr10, cr7, cr12, {4} │ │ - cdp2 1, 0, cr10, cr7, cr0, {4} │ │ - vcmla.f16 , , d12[1], #0 │ │ + mcr2 0, 0, r6, cr8, cr11, {3} │ │ + cdp2 0, 0, cr6, cr7, cr15, {3} │ │ + mcr2 1, 0, sl, cr7, cr9, {5} │ │ + cdp2 1, 0, cr10, cr7, cr13, {5} │ │ + mcr2 9, 0, pc, cr7, cr9, {0} @ │ │ vdot.bf16 , , d3[1] │ │ - mcr2 13, 0, r9, cr8, cr0, {5} │ │ + mcr2 13, 0, r9, cr8, cr13, {6} │ │ vseleq.f64 d11, d6, d7 │ │ - mcr2 11, 0, fp, cr8, cr14, {6} @ │ │ - cdp2 15, 0, cr3, cr7, cr1, {3} │ │ + cdp2 12, 0, cr11, cr8, cr11, {0} │ │ + cdp2 15, 0, cr3, cr7, cr14, {4} │ │ mcr2 10, 0, pc, cr7, cr12, {7} @ │ │ mcr2 10, 0, fp, cr5, cr14, {7} @ │ │ cdp2 7, 0, cr15, cr8, cr8, {1} │ │ cdp2 12, 0, cr7, cr8, cr8, {5} │ │ mcr2 13, 0, ip, cr8, cr10, {2} │ │ mcr2 13, 0, ip, cr9, cr8, {1} │ │ - @ instruction: 0xfe09dbcf │ │ + mcr2 11, 0, sp, cr9, cr12, {7} @ │ │ mcr2 12, 0, ip, cr7, cr15, {3} │ │ - mcr2 6, 0, pc, cr9, cr2, {6} @ │ │ + mcr2 6, 0, pc, cr9, cr15, {7} @ │ │ cdp2 15, 0, cr7, cr7, cr13, {3} │ │ cdp2 1, 0, cr15, cr6, cr12, {2} │ │ b.n 21b2e32 │ │ ldr r1, [r0, #8] │ │ cmp r1, #0 │ │ bmi.n 21b2f98 │ │ ldr r2, [pc, #832] @ (21b32c4 ) │ │ @@ -459510,27 +459510,27 @@ │ │ str r6, [r4, #100] @ 0x64 │ │ ldrb r6, [r4, r5] │ │ bpl.n 21b337a , std::__ndk1::allocator > >(char const*, std::__ndk1::basic_string, std::__ndk1::allocator > const&) const@@Base+0x76> │ │ sbcs r1, r4 │ │ ldr r6, [pc, #912] @ (21b3654 , std::__ndk1::allocator > >(char const*, std::__ndk1::basic_string, std::__ndk1::allocator > const&) const@@Base+0x350>) │ │ lsls r0, r3, #1 │ │ cbnz r6, 21b32d2 │ │ - cdp2 7, 0, cr5, cr8, cr6, {7} │ │ - mcr2 7, 0, r5, cr8, cr10, {6} │ │ - mcr2 9, 0, sp, cr8, cr12, {6} @ │ │ + vfmal.f16 d5, s16, s6[0] │ │ + vcmla.f16 d5, d8, d7[0], #0 │ │ + vseleq.f32 s26, s16, s18 │ │ mcr2 14, 0, r2, cr7, cr1, {3} │ │ mcr2 14, 0, r2, cr9, cr15, {1} │ │ - cdp2 7, 0, cr5, cr9, cr3, {2} │ │ - cdp2 7, 0, cr5, cr8, cr1, {1} │ │ + mcr2 7, 0, r5, cr9, cr0, {3} │ │ + cdp2 7, 0, cr5, cr8, cr14, {2} │ │ cdp2 4, 0, cr5, cr8, cr2, {0} │ │ - mcr2 13, 0, r3, cr9, cr5, {0} │ │ + vdot.bf16 , , d2[0] │ │ @ instruction: 0xfe0779e0 │ │ - mcr2 5, 0, pc, cr8, cr14, {6} @ │ │ - cdp2 5, 0, cr15, cr7, cr14, {5} │ │ - mcr2 2, 0, r3, cr7, cr4, {0} │ │ + cdp2 6, 0, cr15, cr8, cr11, {0} │ │ + mcr2 5, 0, pc, cr7, cr11, {6} @ │ │ + cdp2 2, 0, cr3, cr7, cr1, {2} │ │ mcr2 13, 0, r2, cr8, cr10, {1} │ │ cdp2 6, 0, cr4, cr9, cr6, {4} │ │ lsls r0, r3, #1 │ │ │ │ 021b3304 , std::__ndk1::allocator > >(char const*, std::__ndk1::basic_string, std::__ndk1::allocator > const&) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -459889,27 +459889,27 @@ │ │ movs r1, #251 @ 0xfb │ │ ands r1, r1 │ │ ldrb r3, [r3, #13] │ │ mcr2 2, 0, r4, cr6, cr0, {4} │ │ lsls r0, r3, #1 │ │ bcc.n 21b35fa , std::__ndk1::allocator > >(char const*, std::__ndk1::basic_string, std::__ndk1::allocator > const&) const@@Base+0x2f6> │ │ cdp2 1, 0, cr15, cr8, cr7, {0} │ │ - cdp2 15, 0, cr2, cr8, cr15, {6} │ │ + mcr2 15, 0, r2, cr8, cr12, {7} │ │ cdp2 3, 0, cr13, cr8, cr12, {1} │ │ - vfmal.f16 , d8, d7[2] │ │ + vcmla.f16 d13, d24, d4[1], #0 │ │ cdp2 0, 0, cr15, cr6, cr12, {2} │ │ cdp2 3, 0, cr11, cr8, cr8, {2} │ │ - mcr2 5, 0, r9, cr8, cr3, {5} │ │ + cdp2 5, 0, cr9, cr8, cr0, {7} │ │ cdp2 0, 0, cr15, cr6, cr14, {3} │ │ - vseleq.f16 s18, s16, s5 │ │ - mcr2 6, 0, fp, cr7, cr3, {4} │ │ - mcr2 14, 0, r2, cr6, cr5, {4} │ │ - mcr2 4, 0, sp, cr8, cr10, {6} │ │ - cdp2 6, 0, cr11, cr7, cr1, {1} │ │ - cdp2 3, 0, cr11, cr6, cr13, {3} │ │ + @ instruction: 0xfe08994f │ │ + cdp2 6, 0, cr11, cr7, cr0, {6} │ │ + cdp2 14, 0, cr2, cr6, cr2, {6} │ │ + cdp2 5, 0, cr13, cr8, cr7, {0} │ │ + cdp2 6, 0, cr11, cr7, cr14, {2} │ │ + mcr2 3, 0, fp, cr6, cr10, {4} │ │ cdp2 1, 0, cr4, cr7, cr2, {7} │ │ lsls r0, r3, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ mov r5, r0 │ │ movs r0, #48 @ 0x30 │ │ @@ -460110,26 +460110,26 @@ │ │ ldrb r6, [r4, r5] │ │ bpl.n 21b39f2 │ │ sbcs r1, r4 │ │ movs r0, r0 │ │ movs r0, r0 │ │ strh r0, [r0, #0] │ │ eors r6, r4 │ │ - bcs.n 21b3934 , std::__ndk1::allocator > >(char const*, std::__ndk1::basic_string, std::__ndk1::allocator > const&) const@@Base+0x630> │ │ + bcc.n 21b398e , std::__ndk1::allocator > >(char const*, std::__ndk1::basic_string, std::__ndk1::allocator > const&) const@@Base+0x68a> │ │ cdp2 14, 0, cr3, cr7, cr4, {3} │ │ lsls r0, r3, #1 │ │ muls r2, r5 │ │ lsls r0, r3, #1 │ │ subs r5, #36 @ 0x24 │ │ lsls r0, r3, #1 │ │ - cbz r3, 21b39d2 , std::__ndk1::allocator > >(char const*, std::__ndk1::basic_string, std::__ndk1::allocator > const&) const@@Base+0x6ce> │ │ - cdp2 7, 0, cr1, cr6, cr15, {0} │ │ + push {r3, r5} │ │ + mcr2 7, 0, r1, cr6, cr12, {1} │ │ mcr2 11, 0, r4, cr7, cr2, {5} @ │ │ cdp2 6, 0, cr5, cr9, cr2, {3} │ │ - mcr2 3, 0, r5, cr6, cr1, {6} │ │ + mcr2 3, 0, r5, cr6, cr14, {7} │ │ mcr2 5, 0, fp, cr7, cr0, {7} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ mov r8, r0 │ │ movs r0, #48 @ 0x30 │ │ mov r6, r2 │ │ mov r5, r1 │ │ @@ -460461,34 +460461,34 @@ │ │ ldr r0, [sp, #80] @ 0x50 │ │ str r5, [sp, #84] @ 0x54 │ │ blx 26ffb40 │ │ cbz r4, 21b3d14 │ │ strd r4, sl, [fp] │ │ b.n 21b43d4 │ │ nop │ │ - bl 22898d4 │ │ - asrs r0, r6, #19 │ │ - mcr2 14, 0, sl, cr7, cr4, {4} │ │ + bl 22b68d4 │ │ + asrs r5, r3, #20 │ │ + cdp2 14, 0, cr10, cr7, cr1, {6} │ │ mcr2 5, 0, r8, cr7, cr10, {7} │ │ cdp2 5, 0, cr8, cr9, cr8, {7} │ │ mcr2 10, 0, fp, cr9, cr9, {4} @ │ │ - mcr2 9, 0, r2, cr9, cr8, {2} @ │ │ + vseleq.f16 s4, s19, s10 │ │ mcr2 9, 0, lr, cr8, cr15, {4} @ │ │ - cdp2 0, 0, cr11, cr8, cr12, {7} │ │ - cdp2 0, 0, cr11, cr6, cr0, {7} │ │ - cdp2 15, 0, cr8, cr6, cr9, {2} │ │ - mcr2 15, 0, r8, cr6, cr13, {1} │ │ - mcr2 14, 0, lr, cr6, cr6, {7} │ │ - mcr2 1, 0, sp, cr6, cr11, {3} │ │ - cdp2 0, 0, cr11, cr6, cr13, {0} │ │ + mcr2 1, 0, fp, cr8, cr9, {0} │ │ + cdp2 1, 0, cr11, cr6, cr13, {0} │ │ + mcr2 15, 0, r8, cr6, cr6, {3} │ │ + cdp2 15, 0, cr8, cr6, cr10, {3} │ │ + cdp2 15, 0, cr14, cr6, cr3, {1} │ │ + cdp2 1, 0, cr13, cr6, cr8, {5} │ │ + mcr2 0, 0, fp, cr6, cr10, {1} │ │ mcr2 11, 0, r8, cr6, cr0, {2} @ │ │ cdp2 3, 0, cr10, cr8, cr13, {0} │ │ cdp2 3, 0, cr10, cr9, cr1, {0} │ │ - mcr2 14, 0, r8, cr9, cr3, {4} │ │ - cdp2 14, 0, cr8, cr6, cr7, {4} │ │ + cdp2 14, 0, cr8, cr9, cr0, {6} │ │ + mcr2 14, 0, r8, cr6, cr4, {5} │ │ mcr2 1, 0, pc, cr6, cr10, {5} @ │ │ lsrs r0, r0, #28 │ │ beq.n 21b3d46 │ │ add.w r0, sl, #4 │ │ dmb ish │ │ ldrex r1, [r0] │ │ subs r2, r1, #1 │ │ @@ -460841,33 +460841,33 @@ │ │ bl 21b46a0 │ │ b.n 21b43d4 │ │ blx 26ffe30 │ │ ldr r1, [pc, #100] @ (21b415c ) │ │ add r1, pc │ │ b.n 21b43c6 │ │ nop │ │ - ldmia r5!, {r1, r3} │ │ - mcr2 10, 0, r4, cr7, cr12, {7} @ │ │ + ldmia r5, {r0, r1, r2, r4, r5} │ │ + vseleq.f64 d4, d7, d25 │ │ vdot.bf16 q3, q4, d3[0] │ │ - mcr2 13, 0, r8, cr8, cr0, {0} │ │ + mcr2 13, 0, r8, cr8, cr13, {1} │ │ cdp2 1, 0, cr2, cr6, cr0, {2} │ │ mcr2 11, 0, sl, cr9, cr3, {0} @ │ │ mcr2 4, 0, r0, cr8, cr10, {6} │ │ cdp2 12, 0, cr6, cr9, cr11, {1} │ │ cdp2 12, 0, cr6, cr8, cr5, {0} │ │ - mcr2 12, 0, sl, cr8, cr5, {5} │ │ - cdp2 12, 0, cr10, cr6, cr9, {5} │ │ + cdp2 12, 0, cr10, cr8, cr2, {7} │ │ + mcr2 12, 0, sl, cr6, cr6, {6} │ │ mcr2 12, 0, fp, cr6, cr5, {0} │ │ - vfmal.f16 q2, d25, d5[3] │ │ - vdot.bf16 d12, d24, d7[0] │ │ - mcr2 0, 0, r1, cr6, cr4, {1} │ │ - @ instruction: 0xfe07cac8 │ │ + vseleq.f16 s8, s18, s21 │ │ + mcr2 13, 0, ip, cr8, cr4, {5} │ │ + cdp2 0, 0, cr1, cr6, cr1, {3} │ │ + mcr2 10, 0, ip, cr7, cr5, {7} @ │ │ cdp2 5, 0, cr14, cr7, cr0, {4} │ │ - cdp2 14, 0, cr8, cr8, cr2, {2} │ │ - mcr2 11, 0, r6, cr7, cr10, {1} @ │ │ + cdp2 14, 0, cr8, cr8, cr15, {3} │ │ + @ instruction: 0xfe076b67 │ │ cdp2 0, 0, cr0, cr7, cr0, {0} │ │ movs r0, r0 │ │ strh r0, [r0, #0] │ │ eors r6, r4 │ │ cmp r5, #24 │ │ strb r4, [r0, r1] │ │ movs r1, #251 @ 0xfb │ │ @@ -461204,16 +461204,16 @@ │ │ movs r0, #0 │ │ strd r0, r0, [sp, #96] @ 0x60 │ │ mov r0, r4 │ │ bl 21b4e9c │ │ b.n 21b43d4 │ │ subs r2, #118 @ 0x76 │ │ lsls r0, r3, #1 │ │ - ldmia r0!, {r2, r3, r4, r6, r7} │ │ - vcmla.f16 q4, , d2[1], #0 │ │ + ldmia r1!, {r0, r3} │ │ + vcmla.f16 d8, d23, d15[0], #0 │ │ mcr2 9, 0, r3, cr6, cr0, {7} @ │ │ lsls r0, r3, #1 │ │ vcmp.f64 d16, #0.0 │ │ vmrs APSR_nzcv, fpscr │ │ bne.n 21b4552 │ │ add r0, sp, #32 │ │ add r1, sp, #40 @ 0x28 │ │ @@ -461306,27 +461306,27 @@ │ │ stmia r0!, {r1, r2, r4, r5, r6} │ │ movs r0, r0 │ │ orrs r4, r6 │ │ lsrs r3, r3, #31 │ │ eors r1, r1 │ │ subs r4, #30 │ │ lsls r0, r3, #1 │ │ - add r1, sp, #380 @ 0x17c │ │ + add r1, sp, #560 @ 0x230 │ │ mcr2 11, 0, r6, cr6, cr4, {6} @ │ │ @ instruction: 0xfe066bc8 │ │ mcr2 4, 0, r8, cr6, cr8, {4} │ │ vseleq.f64 d2, d8, d17 │ │ cdp2 4, 0, cr0, cr6, cr7, {7} │ │ - mcr2 12, 0, r0, cr6, cr11, {5} │ │ + cdp2 12, 0, cr0, cr6, cr8, {7} │ │ vseleq.f64 d2, d7, d29 │ │ - vcmla.f16 d6, d6, d1[1], #0 │ │ - vseleq.f16 s4, s15, s14 │ │ + vcmla.f16 q3, q3, d14[0], #0 │ │ + mcr2 9, 0, r2, cr7, cr4, {5} @ │ │ mcr2 15, 0, r3, cr7, cr2, {6} │ │ cdp2 7, 0, cr11, cr9, cr0, {3} │ │ - vseleq.f16 s16, s19, s21 │ │ + mcr2 9, 0, r8, cr9, cr7, {6} @ │ │ mcr2 3, 0, r0, cr7, cr13, {3} │ │ mcr2 2, 0, r3, cr6, cr4, {2} │ │ lsls r0, r3, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ ldr r4, [r0, #4] │ │ cbz r4, 21b4698 │ │ @@ -461495,21 +461495,21 @@ │ │ movs r0, r0 │ │ strh r0, [r0, #0] │ │ eors r6, r4 │ │ cmp r5, #24 │ │ strb r4, [r0, r1] │ │ movs r1, #251 @ 0xfb │ │ ands r1, r1 │ │ - stmia r6!, {r0, r4, r5, r6} │ │ + stmia r6!, {r1, r2, r3, r4, r7} │ │ cdp2 15, 0, cr2, cr6, cr14, {3} │ │ lsls r0, r3, #1 │ │ - lsrs r4, r1, #4 │ │ - cdp2 3, 0, cr12, cr7, cr0, {5} │ │ + lsrs r1, r7, #4 │ │ + cdp2 3, 0, cr12, cr7, cr13, {6} │ │ mcr2 14, 0, sp, cr7, cr8, {2} │ │ - mcr2 7, 0, r8, cr8, cr10, {0} │ │ + cdp2 7, 0, cr8, cr8, cr7, {2} │ │ cdp2 4, 0, cr3, cr7, cr10, {1} │ │ lsls r0, r3, #1 │ │ cmp r6, #22 │ │ lsls r0, r3, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -461689,19 +461689,19 @@ │ │ strb r4, [r0, r1] │ │ moval r1, #251 @ 0xfb │ │ andal r1, r1 │ │ movs r0, r0 │ │ movs r0, r0 │ │ movs r0, r0 │ │ strh r0, [r0, #0] │ │ - lsls r0, r7, #29 │ │ + lsls r5, r4, #30 │ │ mcr2 13, 0, r2, cr7, cr6, {4} │ │ lsls r0, r3, #1 │ │ bgt.n 21b4a44 │ │ - cdp2 5, 0, cr8, cr8, cr14, {4} │ │ + mcr2 5, 0, r8, cr8, cr11, {5} │ │ cdp2 15, 0, cr2, cr7, cr14, {5} │ │ lsls r0, r3, #1 │ │ cmp r3, #226 @ 0xe2 │ │ lsls r0, r3, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -461880,16 +461880,16 @@ │ │ movs r0, r0 │ │ movs r0, r0 │ │ movs r0, r0 │ │ strh r0, [r0, #0] │ │ add lr, r6 │ │ @ instruction: 0xfe062b46 │ │ lsls r0, r3, #1 │ │ - add r1, pc, #428 @ (adr r1, 21b4ea8 ) │ │ - cdp2 3, 0, cr8, cr6, cr12, {2} │ │ + add r1, pc, #608 @ (adr r1, 21b4f5c ) │ │ + mcr2 3, 0, r8, cr6, cr9, {3} │ │ vdot.bf16 q1, , d0[1] │ │ lsls r0, r3, #1 │ │ cmp r1, #148 @ 0x94 │ │ lsls r0, r3, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ vpush {d8-d11} │ │ @@ -462792,23 +462792,23 @@ │ │ mov r0, r5 │ │ bl 21b6204 >::~__shared_ptr_emplace()@@Base+0xb0> │ │ b.n 21b5566 │ │ lsrs r5, r4, #18 │ │ vcmla.f16 d2, d25, d8[1], #0 │ │ lsls r0, r3, #1 │ │ bl 1e7e2b2 │ │ - bcs.n 21b5602 │ │ + bcs.n 21b565c │ │ cdp2 1, 0, cr13, cr7, cr8, {7} │ │ - cdp2 5, 0, cr9, cr8, cr7, {4} │ │ + mcr2 5, 0, r9, cr8, cr4, {5} │ │ mcr2 7, 0, r2, cr7, cr0, {5} │ │ lsls r0, r3, #1 │ │ - strb r1, [r1, #27] │ │ + strb r6, [r6, #27] │ │ mcr2 10, 0, r1, cr6, cr8, {6} @ │ │ mcr2 14, 0, lr, cr6, cr5, {3} │ │ - mcr2 4, 0, r3, cr8, cr4, {0} │ │ + cdp2 4, 0, cr3, cr8, cr1, {2} │ │ mcr2 4, 0, r9, cr8, cr11, {1} │ │ cdp2 2, 0, cr7, cr8, cr9, {0} │ │ cdp2 0, 0, cr13, cr8, cr8, {0} │ │ vseleq.f16 s2, s17, s13 │ │ mcr2 4, 0, r5, cr6, cr12, {5} │ │ cdp2 5, 0, cr2, cr8, cr8, {5} │ │ lsls r0, r3, #1 │ │ @@ -463139,29 +463139,29 @@ │ │ blx 27010d0 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ movs r3, #64 @ 0x40 │ │ lsls r0, r3, #1 │ │ adds r7, r2, r1 │ │ - mcr2 14, 0, ip, cr6, cr7, {7} │ │ - vdot.bf16 q7, , d11[0] │ │ + cdp2 15, 0, cr12, cr6, cr4, {1} │ │ + mcr2 13, 0, lr, cr7, cr8, {7} │ │ cdp2 3, 0, cr4, cr7, cr14, {6} │ │ cdp2 5, 0, cr5, cr9, cr14, {6} │ │ - vfmal.f16 , d22, d2[2] │ │ + mcr2 9, 0, pc, cr6, cr15, {0} @ │ │ vfmal.f16 d6, s12, s1[1] │ │ - mcr2 13, 0, r4, cr9, cr4, {7} │ │ + cdp2 14, 0, cr4, cr9, cr1, {1} │ │ mcr2 10, 0, r2, cr7, cr6, {4} @ │ │ mcr2 12, 0, r2, cr9, cr10, {1} │ │ - mcr2 0, 0, r3, cr9, cr2, {5} │ │ + mcr2 0, 0, r3, cr9, cr15, {6} │ │ mcr2 1, 0, r5, cr8, cr9, {6} │ │ - cdp2 0, 0, cr3, cr8, cr13, {2} │ │ + mcr2 0, 0, r3, cr8, cr10, {3} │ │ mcr2 12, 0, r2, cr8, cr9, {2} │ │ - cdp2 3, 0, cr13, cr9, cr0, {4} │ │ - mcr2 4, 0, r7, cr6, cr11, {7} │ │ + cdp2 3, 0, cr13, cr9, cr13, {5} │ │ + cdp2 5, 0, cr7, cr6, cr8, {1} │ │ mcr2 3, 0, r4, cr7, cr0, {2} │ │ cdp2 0, 0, cr2, cr9, cr0, {6} │ │ lsls r0, r3, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ mov r9, r3 │ │ @@ -464131,15 +464131,15 @@ │ │ addeq sp, #40 @ 0x28 │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ lsrs r0, r1, #17 │ │ mcr2 3, 0, r1, cr6, cr6, {0} │ │ lsls r0, r3, #1 │ │ - str r6, [r5, #124] @ 0x7c │ │ + ldr r3, [r3, #0] │ │ mcr2 4, 0, sl, cr6, cr11, {0} │ │ mcr2 2, 0, r1, cr8, cr14, {2} │ │ lsls r0, r3, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #32 │ │ @@ -464311,24 +464311,24 @@ │ │ mvn.w r5, #1 │ │ b.n 21b6572 >::~__shared_ptr_emplace()@@Base+0x41e> │ │ nop │ │ mov r7, r4 │ │ cdp2 2, 0, cr1, cr8, cr4, {1} │ │ lsls r0, r3, #1 │ │ adds r7, #179 @ 0xb3 │ │ - mcr2 12, 0, fp, cr9, cr0, {7} │ │ - cdp2 6, 0, cr12, cr7, cr5, {5} │ │ + mcr2 13, 0, fp, cr9, cr13, {0} │ │ + mcr2 6, 0, ip, cr7, cr2, {6} │ │ mcr2 4, 0, pc, cr6, cr12, {6} @ │ │ cdp2 5, 0, cr8, cr8, cr14, {0} │ │ mcr2 4, 0, r5, cr8, cr8, {6} │ │ mcr2 10, 0, r7, cr9, cr11, {4} @ │ │ - cdp2 0, 0, cr14, cr9, cr15, {3} │ │ + mcr2 0, 0, lr, cr9, cr12, {4} │ │ @ instruction: 0xfe077a60 │ │ vfmal.f16 d3, s18, s2[0] │ │ - vseleq.f64 d14, d9, d4 │ │ + mcr2 11, 0, lr, cr9, cr1, {1} @ │ │ mcr2 0, 0, r1, cr6, cr6, {5} │ │ lsls r0, r3, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ sub sp, #112 @ 0x70 │ │ mov r6, r1 │ │ @@ -464638,16 +464638,16 @@ │ │ add r0, sp, #48 @ 0x30 │ │ blx 2708cc0 │ │ blx 26ffb60 │ │ nop │ │ lsrs r2, r4, #6 │ │ mcr2 0, 0, r1, cr6, cr10, {1} │ │ lsls r0, r3, #1 │ │ - movs r6, #152 @ 0x98 │ │ - cdp2 4, 0, cr10, cr7, cr8, {3} │ │ + movs r6, #197 @ 0xc5 │ │ + mcr2 4, 0, sl, cr7, cr5, {4} │ │ cdp2 1, 0, cr14, cr7, cr0, {7} │ │ vseleq.f64 d13, d21, d7 │ │ mcr2 13, 0, r8, cr8, cr9, {4} │ │ mcr2 9, 0, r5, cr9, cr15, {7} @ │ │ mcr2 14, 0, r0, cr9, cr4, {3} │ │ lsls r0, r3, #1 │ │ push {r4, r5, r6, r7, lr} │ │ @@ -464795,18 +464795,18 @@ │ │ cmp r1, r0 │ │ ittt eq │ │ addeq sp, #40 @ 0x28 │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ - subs r0, r3, #3 │ │ + subs r5, r0, #4 │ │ mcr2 12, 0, r0, cr8, cr0, {0} │ │ lsls r0, r3, #1 │ │ - add r0, pc, #324 @ (adr r0, 21b6c14 >::~__shared_ptr_emplace()@@Base+0x10>) │ │ + add r0, pc, #504 @ (adr r0, 21b6cc8 ) │ │ vseleq.f64 d0, d23, d0 │ │ lsls r0, r3, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #40 @ 0x28 │ │ mov r6, r1 │ │ @@ -464888,18 +464888,18 @@ │ │ ldr r1, [r1, #0] │ │ cmp r1, r0 │ │ ittt eq │ │ addeq sp, #40 @ 0x28 │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ - subs r2, #236 @ 0xec │ │ + subs r3, #25 │ │ @ instruction: 0xfe070b44 │ │ lsls r0, r3, #1 │ │ - bge.n 21b6c08 >::~__shared_ptr_emplace()@@Base+0x4> │ │ + bge.n 21b6c62 >::~__shared_ptr_emplace()@@Base+0xa> │ │ mcr2 13, 0, fp, cr7, cr3, {1} │ │ mcr2 10, 0, r0, cr5, cr2, {4} @ │ │ lsls r0, r3, #1 │ │ │ │ 021b6bc4 >::~__shared_ptr_emplace()@@Base>: │ │ ldr r1, [pc, #12] @ (21b6bd4 >::~__shared_ptr_emplace()@@Base+0x10>) │ │ add r1, pc │ │ @@ -466550,15 +466550,15 @@ │ │ blx 26ffb60 │ │ nop │ │ movs r0, r0 │ │ strh r0, [r0, #0] │ │ push {r2, r3, r5} │ │ adcs r2, r0 │ │ @ instruction: 0xfaaa0057 │ │ - mov ip, r1 │ │ + mov r9, r7 │ │ @ instruction: 0xfe06f9e2 │ │ lsls r7, r2, #1 │ │ bmi.n 21b7c38 │ │ bmi.n 21b7c3a │ │ │ │ 021b7c90 const&, float, double, Matrices const&) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -467562,15 +467562,15 @@ │ │ mov.w r8, #69 @ 0x45 │ │ vmov r0, s0 │ │ rsb r0, r0, #360 @ 0x168 │ │ b.n 21b89aa const&, float, double, Matrices const&) const@@Base+0xd1a> │ │ movs r0, #0 │ │ mov.w r8, #69 @ 0x45 │ │ b.n 21b89aa const&, float, double, Matrices const&) const@@Base+0xd1a> │ │ - lsls r6, r0, #10 │ │ + lsls r3, r6, #10 │ │ cdp2 0, 0, cr0, cr7, cr0, {0} │ │ movs r0, r0 │ │ strh r0, [r0, #0] │ │ eors r6, r4 │ │ movs r0, r0 │ │ movs r0, r0 │ │ movs r0, #0 │ │ @@ -467711,17 +467711,17 @@ │ │ movs r0, r0 │ │ subs r7, #128 @ 0x80 │ │ movs r0, r0 │ │ movs r0, r0 │ │ ldr??.w r0, [r6, r7, lsl #1] │ │ @ instruction: 0xf3120057 │ │ sbcs.w r0, sl, r7, lsr #1 │ │ - vcge.f32 d15, d0, d6 │ │ - cdp2 14, 10, cr15, cr12, cr6, {0} │ │ - cdp2 14, 9, cr15, cr2, cr6, {0} │ │ + vcgt.f32 d15, d13, d6 │ │ + cdp2 14, 13, cr15, cr9, cr6, {0} │ │ + cdp2 14, 11, cr15, cr15, cr6, {0} │ │ │ │ 021b8b58 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8-d9} │ │ @@ -469085,15 +469085,15 @@ │ │ ldr r1, [pc, #12] @ (21b9c44 ) │ │ add r1, pc │ │ blx 2703fb0 │ │ str r0, [r4, #28] │ │ movs r0, #1 │ │ strb r0, [r4, #20] │ │ pop {r4, r6, r7, pc} │ │ - @ instruction: 0xeb9bfe06 │ │ + @ instruction: 0xebc8fe06 │ │ │ │ 021b9c48 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #24 │ │ mov r4, r0 │ │ ldr r0, [pc, #64] @ (21b9c94 ) │ │ @@ -469229,15 +469229,15 @@ │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ svc 54 @ 0x36 │ │ lsls r7, r2, #1 │ │ bls.n 21b9de0 │ │ lsls r7, r2, #1 │ │ - @ instruction: 0xeabafe07 │ │ + @ instruction: 0xeae7fe07 │ │ udf #208 @ 0xd0 │ │ lsls r7, r2, #1 │ │ bhi.n 21b9d0c │ │ lsls r7, r2, #1 │ │ │ │ 021b9d9c : │ │ push {r7, lr} │ │ @@ -481837,15 +481837,15 @@ │ │ nop {15} │ │ movs r0, r0 │ │ movs r0, r0 │ │ ldr r1, [pc, #272] @ (21c30c8 ) │ │ lsls r7, r2, #1 │ │ mov sl, r7 │ │ lsls r7, r2, #1 │ │ - bhi.n 21c2f22 > const&, Observer const&, double)@@Base+0x252> │ │ + bhi.n 21c2f7c > const&, Observer const&, double)@@Base+0x2ac> │ │ Address 0x21c2fbe is out of bounds. │ │ │ │ │ │ 021c2fc0 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -482174,18 +482174,18 @@ │ │ lsls r7, r2, #1 │ │ cpsid │ │ lsls r4, r3, #1 │ │ mov r8, sl │ │ lsls r7, r2, #1 │ │ @ instruction: 0xb836 │ │ lsls r4, r3, #1 │ │ - bpl.n 21c33be │ │ + bpl.n 21c3418 │ │ cdp2 7, 0, cr11, cr5, cr10, {1} │ │ lsls r4, r3, #1 │ │ - bcc.n 21c337e │ │ + bmi.n 21c33d8 │ │ cdp2 3, 0, cr4, cr5, cr2, {2} │ │ lsls r7, r2, #1 │ │ │ │ 021c33b0 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -490801,19 +490801,19 @@ │ │ mov r4, r0 │ │ cmp r5, #0 │ │ bne.n 21c9d3e , std::__ndk1::allocator >, std::__ndk1::basic_string, std::__ndk1::allocator >, std::__ndk1::less, std::__ndk1::allocator > >, std::__ndk1::allocator, std::__ndk1::allocator > const, std::__ndk1::basic_string, std::__ndk1::allocator > > > >&) const@@Base+0x5a2> │ │ movs r0, #40 @ 0x28 │ │ blx 26ffbf0 │ │ b.n 21c9cf4 , std::__ndk1::allocator >, std::__ndk1::basic_string, std::__ndk1::allocator >, std::__ndk1::less, std::__ndk1::allocator > >, std::__ndk1::allocator, std::__ndk1::allocator > const, std::__ndk1::basic_string, std::__ndk1::allocator > > > >&) const@@Base+0x558> │ │ nop │ │ - asrs r6, r4, #2 │ │ + asrs r3, r2, #3 │ │ cdp2 15, 0, cr7, cr6, cr8, {5} │ │ cdp2 15, 0, cr13, cr8, cr12, {1} │ │ lsls r6, r2, #1 │ │ - strb r0, [r5, #4] │ │ + strb r5, [r2, #5] │ │ mcr2 13, 0, r7, cr5, cr6, {0} │ │ mcr2 9, 0, lr, cr8, cr13, {6} @ │ │ movs r0, #10 │ │ ldr r1, [pc, #36] @ (21c9cac , std::__ndk1::allocator >, std::__ndk1::basic_string, std::__ndk1::allocator >, std::__ndk1::less, std::__ndk1::allocator > >, std::__ndk1::allocator, std::__ndk1::allocator > const, std::__ndk1::basic_string, std::__ndk1::allocator > > > >&) const@@Base+0x510>) │ │ str r0, [sp, #96] @ 0x60 │ │ movw r0, #273 @ 0x111 │ │ stmia.w sp, {r0, r4, r8} │ │ @@ -491689,15 +491689,15 @@ │ │ blx 26ffb60 │ │ nop │ │ udf #128 @ 0x80 │ │ lsls r6, r2, #1 │ │ ldrb r2, [r2, #7] │ │ mcr2 7, 0, sp, cr8, cr12, {4} │ │ lsls r6, r2, #1 │ │ - stmia r0!, {r5, r7} │ │ + stmia r0!, {r0, r2, r3, r6, r7} │ │ mcr2 1, 0, r7, cr6, cr4, {4} │ │ vseleq.f16 s14, s16, s24 │ │ cdp2 0, 0, cr13, cr8, cr6, {7} │ │ lsls r6, r2, #1 │ │ │ │ 021ca5ec : │ │ ldr.w r0, [r0, #944] @ 0x3b0 │ │ @@ -491763,15 +491763,15 @@ │ │ blx 26ffb50 │ │ mov r0, r5 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ beq.n 21ca6ec │ │ lsls r6, r2, #1 │ │ - str r1, [r3, #76] @ 0x4c │ │ + str r6, [r0, #80] @ 0x50 │ │ mcr2 15, 0, ip, cr6, cr6, {5} │ │ lsls r6, r2, #1 │ │ │ │ 021ca6a0 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ ldr r2, [pc, #68] @ (21ca6ec ) │ │ @@ -503428,18 +503428,18 @@ │ │ nop │ │ @ instruction: 0x47b2 │ │ lsls r6, r2, #1 │ │ cmp r2, #96 @ 0x60 │ │ vseleq.f32 s4, s15, s16 │ │ cdp2 7, 0, cr4, cr7, cr8, {1} │ │ lsls r6, r2, #1 │ │ - adds r4, #153 @ 0x99 │ │ + adds r4, #198 @ 0xc6 │ │ cdp2 6, 0, cr4, cr6, cr2, {4} │ │ lsls r6, r2, #1 │ │ - adds r4, #131 @ 0x83 │ │ + adds r4, #176 @ 0xb0 │ │ cdp2 5, 0, cr4, cr6, cr2, {7} │ │ lsls r6, r2, #1 │ │ │ │ 021d3150 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ ldr r0, [pc, #80] @ (21d31a8 ) │ │ @@ -505110,22 +505110,22 @@ │ │ nop │ │ adds r6, #116 @ 0x74 │ │ lsls r6, r2, #1 │ │ subs r0, #208 @ 0xd0 │ │ lsls r6, r2, #1 │ │ ldrb r5, [r0, #29] │ │ cdp2 5, 0, cr14, cr7, cr8, {5} │ │ - vfmal.f16 q6, d6, d2[1] │ │ + vcmla.f16 d12, d22, d7[0], #0 │ │ mcr2 1, 0, r5, cr5, cr0, {1} │ │ - @ instruction: 0xfe04ea6a │ │ - mcr2 10, 0, ip, cr4, cr12, {6} @ │ │ + mcr2 10, 0, lr, cr4, cr7, {4} @ │ │ + vseleq.f64 d12, d4, d9 │ │ mcr2 6, 0, r0, cr5, cr2, {3} │ │ @ instruction: 0xfe04a960 │ │ - cdp2 12, 0, cr10, cr6, cr14, {1} │ │ - mcr2 12, 0, r6, cr4, cr1, {5} │ │ + mcr2 12, 0, sl, cr6, cr11, {2} │ │ + mcr2 12, 0, r6, cr4, cr14, {6} │ │ mcr2 10, 0, fp, cr5, cr9, {3} @ │ │ mcr2 10, 0, fp, cr7, cr15, {6} @ │ │ mcr2 5, 0, r3, cr7, cr2, {5} │ │ lsls r6, r2, #1 │ │ │ │ 021d41b8 >, std::__ndk1::basic_string_view >, std::__ndk1::basic_string_view >)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -505488,32 +505488,32 @@ │ │ ldr r5, [pc, #240] @ (21d45f4 >)@@Base+0x90>) │ │ mcr2 5, 0, r1, cr4, cr10, {5} │ │ lsls r5, r2, #1 │ │ bvc.n 21d451c >, std::__ndk1::basic_string_view >)@@Base+0x264> │ │ mcr2 13, 0, r4, cr7, cr12, {1} │ │ vdot.bf16 d1, d4, d11[1] │ │ vcmla.f16 , , d2[0], #0 │ │ - cdp2 3, 0, cr12, cr7, cr9, {1} │ │ + mcr2 3, 0, ip, cr7, cr6, {2} │ │ vcmla.f16 d11, d20, d10[1], #0 │ │ vcmla.f16 d3, d7, d0[1], #0 │ │ lsls r6, r2, #1 │ │ - mov r3, r2 │ │ - mcr2 10, 0, r2, cr6, cr14, {4} @ │ │ + mov r0, r8 │ │ + @ instruction: 0xfe062acb │ │ mcr2 5, 0, r3, cr5, cr14, {4} │ │ lsls r6, r2, #1 │ │ ldrb r7, [r2, #16] │ │ mcr2 2, 0, lr, cr7, cr12, {3} │ │ - mcr2 5, 0, ip, cr6, cr0, {1} │ │ + mcr2 5, 0, ip, cr6, cr13, {2} │ │ cdp2 14, 0, cr4, cr5, cr8, {0} │ │ - cdp2 7, 0, cr14, cr4, cr4, {2} │ │ - mcr2 7, 0, ip, cr4, cr8, {5} │ │ + mcr2 7, 0, lr, cr4, cr1, {3} │ │ + cdp2 7, 0, cr12, cr4, cr5, {7} │ │ mcr2 3, 0, r0, cr5, cr0, {2} │ │ cdp2 6, 0, cr10, cr4, cr0, {2} │ │ - mcr2 9, 0, sl, cr6, cr0, {0} @ │ │ - mcr2 9, 0, r6, cr4, cr5, {4} @ │ │ + mcr2 9, 0, sl, cr6, cr13, {1} @ │ │ + @ instruction: 0xfe0469c2 │ │ mcr2 7, 0, fp, cr5, cr15, {2} │ │ cdp2 7, 0, cr11, cr7, cr7, {6} │ │ mcr2 1, 0, r3, cr7, cr6, {3} │ │ lsls r6, r2, #1 │ │ │ │ 021d4564 >)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -505872,22 +505872,22 @@ │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ adds r0, #184 @ 0xb8 │ │ lsls r6, r2, #1 │ │ cmp r5, #254 @ 0xfe │ │ lsls r6, r2, #1 │ │ - subs r1, r2, #2 │ │ - mcr2 7, 0, r2, cr6, cr12, {0} │ │ - cdp2 7, 0, cr2, cr5, cr10, {0} │ │ - mcr2 13, 0, r1, cr5, cr15, {7} │ │ - vdot.bf16 , q11, d15[1] │ │ - cdp2 6, 0, cr12, cr6, cr10, {2} │ │ + subs r6, r7, #2 │ │ + cdp2 7, 0, cr2, cr6, cr9, {2} │ │ + mcr2 7, 0, r2, cr5, cr7, {1} │ │ + cdp2 14, 0, cr1, cr5, cr12, {1} │ │ + mcr2 14, 0, r1, cr6, cr12, {0} │ │ + mcr2 6, 0, ip, cr6, cr7, {3} │ │ @ instruction: 0xfe047a4e │ │ - cdp2 6, 0, cr12, cr7, cr10, {1} │ │ + mcr2 6, 0, ip, cr7, cr7, {2} │ │ vseleq.f32 s14, s8, s29 │ │ mcr2 15, 0, r2, cr7, cr8, {0} │ │ lsls r6, r2, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ sub sp, #224 @ 0xe0 │ │ @@ -506491,19 +506491,19 @@ │ │ ldr r0, [sp, #120] @ 0x78 │ │ blx 26ffb40 │ │ b.n 21d4f0e >, ShaderManager::GeomShaderParams const*)@@Base+0x3e2> │ │ ldr r0, [sp, #152] @ 0x98 │ │ blx 26ffb40 │ │ b.n 21d4ec8 >, ShaderManager::GeomShaderParams const*)@@Base+0x39c> │ │ b.n 21d4ffc >, ShaderManager::GeomShaderParams const*)@@Base+0x4d0> │ │ - adds r5, r0, r3 │ │ - mcr2 1, 0, r2, cr6, cr0, {2} │ │ - mcr2 1, 0, r2, cr5, cr14, {1} │ │ - vfmal.f16 d1, s10, s7[0] │ │ - vcmla.f16 d1, d6, d3[1], #0 │ │ + adds r2, r6, r3 │ │ + mcr2 1, 0, r2, cr6, cr13, {3} │ │ + cdp2 1, 0, cr2, cr5, cr11, {3} │ │ + vcmla.f16 , , d0[1], #0 │ │ + vfmal.f16 , d6, d0[0] │ │ mcr2 14, 0, r5, cr6, cr9, {1} │ │ cdp2 14, 0, cr5, cr6, cr7, {1} │ │ vfmal.f16 d15, s13, s10[1] │ │ lsls r4, r3, #2 │ │ cmp r0, #0 │ │ itt ne │ │ ldrbne.w r0, [sp, #144] @ 0x90 │ │ @@ -506609,19 +506609,19 @@ │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ cmp r2, #236 @ 0xec │ │ lsls r6, r2, #1 │ │ movs r6, #218 @ 0xda │ │ lsls r6, r2, #1 │ │ - stmia r0!, {r2, r7} │ │ + stmia r0!, {r0, r4, r5, r7} │ │ cdp2 4, 0, cr7, cr4, cr8, {4} │ │ - cdp2 0, 0, cr12, cr7, cr4, {3} │ │ + mcr2 0, 0, ip, cr7, cr1, {4} │ │ cdp2 4, 0, cr7, cr4, cr8, {3} │ │ - cdp2 15, 0, cr11, cr7, cr14, {2} │ │ + mcr2 15, 0, fp, cr7, cr11, {3} │ │ mcr2 3, 0, r7, cr4, cr2, {2} │ │ cdp2 7, 0, cr2, cr7, cr2, {5} │ │ lsls r6, r2, #1 │ │ │ │ 021d50dc >, std::__ndk1::basic_string_view >, std::__ndk1::basic_string_view >, ShaderManager::GeomShaderParams const*)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -507031,53 +507031,53 @@ │ │ ldrne r0, [sp, #72] @ 0x48 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ movs r5, #54 @ 0x36 │ │ lsls r6, r2, #1 │ │ ldr r1, [sp, #340] @ 0x154 │ │ mcr2 7, 0, fp, cr6, cr13, {5} │ │ - cdp2 0, 0, cr0, cr6, cr6, {2} │ │ - @ instruction: 0xfe059b41 │ │ + mcr2 0, 0, r0, cr6, cr3, {3} │ │ + @ instruction: 0xfe059b6e │ │ @ instruction: 0xfe058b4a │ │ mcr2 11, 0, r8, cr7, cr4, {0} @ │ │ mcr2 14, 0, r8, cr7, cr0, {4} │ │ cdp2 7, 0, cr0, cr12, cr6, {3} │ │ lsls r5, r2, #1 │ │ lsrs r7, r2, #27 │ │ @ instruction: 0xfe07aa44 │ │ mcr2 14, 0, r3, cr7, cr6, {2} │ │ mcr2 15, 0, r0, cr4, cr0, {0} │ │ vseleq.f32 s20, s14, s13 │ │ cdp2 14, 0, cr3, cr7, cr4, {3} │ │ - mcr2 9, 0, fp, cr4, cr5, {5} @ │ │ + @ instruction: 0xfe04b9e2 │ │ cdp2 6, 0, cr0, cr5, cr10, {4} │ │ lsls r5, r2, #1 │ │ lsls r4, r1, #26 │ │ lsls r5, r2, #1 │ │ - cbnz r7, 21d5528 >, std::__ndk1::basic_string_view >, std::__ndk1::basic_string_view >, ShaderManager::GeomShaderParams const*)@@Base+0x44c> │ │ + cbnz r4, 21d5534 >, std::__ndk1::basic_string_view >, std::__ndk1::basic_string_view >, ShaderManager::GeomShaderParams const*)@@Base+0x458> │ │ @ instruction: 0xfe05a96e │ │ mcr2 9, 0, sl, cr7, cr12, {2} @ │ │ - cdp2 3, 0, cr11, cr7, cr7, {6} │ │ + mcr2 3, 0, fp, cr7, cr4, {7} │ │ vcmla.f16 q1, q10, d4[0], #0 │ │ lsls r6, r2, #1 │ │ - adds r6, #183 @ 0xb7 │ │ + adds r6, #228 @ 0xe4 │ │ mcr2 6, 0, sp, cr6, cr9, {6} │ │ - mcr2 11, 0, r1, cr3, cr12, {0} @ │ │ + @ instruction: 0xfe031b49 │ │ mcr2 6, 0, r2, cr5, cr10, {0} │ │ lsls r6, r2, #1 │ │ ldr r3, [r2, #72] @ 0x48 │ │ mcr2 2, 0, sp, cr7, cr8, {7} │ │ - cdp2 5, 0, cr11, cr6, cr12, {5} │ │ + mcr2 5, 0, fp, cr6, cr9, {6} │ │ cdp2 14, 0, cr3, cr5, cr4, {4} │ │ - cdp2 7, 0, cr13, cr4, cr0, {6} │ │ - vfmal.f16 d11, s8, s9[0] │ │ + cdp2 7, 0, cr13, cr4, cr13, {7} │ │ + vcmla.f16 , q2, d1[1], #0 │ │ cdp2 3, 0, cr15, cr5, cr12, {6} │ │ mcr2 6, 0, r9, cr3, cr12, {5} │ │ - vseleq.f16 s18, s13, s24 │ │ - mcr2 10, 0, r5, cr4, cr1, {0} @ │ │ + mcr2 9, 0, r9, cr6, cr9, {5} @ │ │ + mcr2 10, 0, r5, cr4, cr14, {1} @ │ │ mcr2 7, 0, sl, cr5, cr11, {6} │ │ vcmla.f16 q5, , d3[0], #0 │ │ mcr2 1, 0, r2, cr7, cr6, {6} │ │ lsls r6, r2, #1 │ │ │ │ 021d5560 >, std::__ndk1::basic_string_view >)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -507326,32 +507326,32 @@ │ │ subs r2, #148 @ 0x94 │ │ mcr2 3, 0, r0, cr4, cr2, {0} │ │ lsls r5, r2, #1 │ │ lsrs r6, r7, #12 │ │ mcr2 10, 0, r3, cr7, cr4, {4} @ │ │ vseleq.f32 s0, s9, s6 │ │ mcr2 6, 0, sl, cr7, cr10, {0} │ │ - cdp2 0, 0, cr11, cr7, cr1, {4} │ │ + cdp2 0, 0, cr11, cr7, cr14, {5} │ │ cdp2 6, 0, cr10, cr4, cr2, {0} │ │ mcr2 5, 0, r2, cr7, cr8, {3} │ │ lsls r6, r2, #1 │ │ - adds r3, #107 @ 0x6b │ │ - mcr2 7, 0, r1, cr6, cr6, {7} │ │ + adds r3, #152 @ 0x98 │ │ + vcmla.f16 d1, d6, d3[1], #0 │ │ mcr2 2, 0, r2, cr5, cr6, {7} │ │ lsls r6, r2, #1 │ │ ldr r7, [r5, #20] │ │ mcr2 15, 0, ip, cr7, cr4, {6} │ │ - cdp2 2, 0, cr11, cr6, cr8, {4} │ │ + mcr2 2, 0, fp, cr6, cr5, {5} │ │ @ instruction: 0xfe053b60 │ │ - mcr2 4, 0, sp, cr4, cr12, {4} │ │ - mcr2 5, 0, fp, cr4, cr0, {0} │ │ + cdp2 4, 0, cr13, cr4, cr9, {6} │ │ + mcr2 5, 0, fp, cr4, cr13, {1} │ │ cdp2 0, 0, cr15, cr5, cr8, {5} │ │ mcr2 3, 0, r9, cr3, cr8, {4} │ │ - cdp2 6, 0, cr9, cr6, cr8, {3} │ │ - cdp2 6, 0, cr5, cr4, cr13, {7} │ │ + mcr2 6, 0, r9, cr6, cr5, {4} │ │ + mcr2 7, 0, r5, cr4, cr10, {0} │ │ mcr2 4, 0, sl, cr5, cr7, {5} │ │ mcr2 5, 0, sl, cr7, cr15, {0} │ │ cdp2 14, 0, cr1, cr7, cr14, {6} │ │ lsls r6, r2, #1 │ │ │ │ 021d580c >, std::__ndk1::basic_string_view >, std::__ndk1::basic_string_view >, std::__ndk1::basic_string_view >)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -507839,36 +507839,36 @@ │ │ cmp r0, #1 │ │ beq.n 21d5d7c │ │ cmp r0, #128 @ 0x80 │ │ beq.n 21d5d7c │ │ b.n 21d5d8e │ │ stmia r0!, {r3, r6, r7} │ │ mcr2 14, 0, r6, cr7, cr12, {1} │ │ - cdp2 3, 0, cr1, cr6, cr3, {6} │ │ - mcr2 2, 0, r5, cr5, cr1, {1} │ │ - mcr2 1, 0, r5, cr5, cr15, {5} │ │ - @ instruction: 0xfe050a4c │ │ + mcr2 3, 0, r1, cr6, cr0, {7} │ │ + mcr2 2, 0, r5, cr5, cr14, {2} │ │ + cdp2 1, 0, cr5, cr5, cr12, {7} │ │ + mcr2 10, 0, r0, cr5, cr9, {3} @ │ │ cdp2 14, 0, cr15, cr6, cr10, {1} │ │ lsls r4, r2, #1 │ │ mcr2 0, 1, r0, cr4, cr4, {2} │ │ mrc2 0, 0, r0, cr14, cr4, {2} │ │ mrc2 0, 0, r0, cr0, cr4, {2} │ │ lsls r0, r7, #21 │ │ - mcr2 3, 0, fp, cr7, cr15, {1} │ │ - vseleq.f32 s28, s9, s18 │ │ - vseleq.f64 d12, d5, d11 │ │ + cdp2 3, 0, cr11, cr7, cr12, {3} │ │ + mcr2 10, 0, lr, cr4, cr6, {5} @ │ │ + mcr2 11, 0, ip, cr5, cr8, {1} @ │ │ vfmal.f16 d14, s10, s15[0] │ │ cdp2 1, 0, cr14, cr6, cr13, {6} │ │ - mcr2 9, 0, r0, cr6, cr2, {4} @ │ │ + mcr2 9, 0, r0, cr6, cr15, {5} @ │ │ mcr2 15, 0, r9, cr6, cr9, {5} │ │ cdp2 7, 0, cr14, cr7, cr15, {4} │ │ cdp2 1, 0, cr5, cr6, cr8, {1} │ │ - mcr2 2, 0, r7, cr4, cr13, {3} │ │ + cdp2 2, 0, cr7, cr4, cr10, {5} │ │ cdp2 7, 0, cr14, cr5, cr7, {1} │ │ - cdp2 0, 0, cr1, cr6, cr7, {5} │ │ + mcr2 0, 0, r1, cr6, cr4, {6} │ │ mcr2 5, 0, pc, cr5, cr0, {5} @ │ │ ldr r0, [r0, #120] @ 0x78 │ │ it ne │ │ cmpne.w r0, #256 @ 0x100 │ │ bne.n 21d5d8e │ │ ldrb.w r0, [fp, #5] │ │ lsls r0, r0, #26 │ │ @@ -508195,30 +508195,30 @@ │ │ blxne 26ffb40 │ │ ldr r0, [sp, #44] @ 0x2c │ │ ldrh r0, [r0, #0] │ │ b.n 21d6056 │ │ nop │ │ b.n 21d5d9a │ │ cdp2 3, 0, cr10, cr6, cr0, {4} │ │ - mcr2 0, 0, fp, cr6, cr11, {2} │ │ - mcr2 15, 0, r0, cr4, cr6, {3} │ │ - cdp2 0, 0, cr11, cr5, cr11, {0} │ │ - cdp2 15, 0, cr10, cr4, cr3, {0} │ │ - mcr2 15, 0, sl, cr4, cr11, {5} │ │ - mcr2 13, 0, r8, cr4, cr5, {7} │ │ - cdp2 15, 0, cr10, cr4, cr9, {3} │ │ - cdp2 6, 0, cr14, cr4, cr3, {6} │ │ + cdp2 0, 0, cr11, cr6, cr8, {4} │ │ + cdp2 15, 0, cr0, cr4, cr3, {5} │ │ + mcr2 0, 0, fp, cr5, cr8, {1} │ │ + mcr2 15, 0, sl, cr4, cr0, {1} │ │ + cdp2 15, 0, cr10, cr4, cr8, {7} │ │ + cdp2 14, 0, cr8, cr4, cr2, {1} │ │ + mcr2 15, 0, sl, cr4, cr6, {4} │ │ + mcr2 6, 0, lr, cr4, cr0, {7} │ │ cdp2 4, 0, cr14, cr5, cr13, {5} │ │ - mcr2 13, 0, r8, cr6, cr13, {2} │ │ - mcr2 14, 0, sl, cr4, cr5, {5} │ │ - @ instruction: 0xfe046bee │ │ - cdp2 14, 0, cr10, cr4, cr3, {3} │ │ - mcr2 11, 0, sl, cr4, cr11, {2} @ │ │ - mcr2 6, 0, ip, cr5, cr10, {1} │ │ - cdp2 6, 0, cr12, cr5, cr14, {0} │ │ + vdot.bf16 d8, d22, d10[0] │ │ + cdp2 14, 0, cr10, cr4, cr2, {7} │ │ + mcr2 12, 0, r6, cr4, cr11, {0} │ │ + mcr2 14, 0, sl, cr4, cr0, {4} │ │ + vseleq.f64 d10, d20, d8 │ │ + cdp2 6, 0, cr12, cr5, cr7, {3} │ │ + mcr2 6, 0, ip, cr5, cr11, {1} │ │ cdp2 3, 0, cr14, cr5, cr7, {2} │ │ vcmla.f16 d9, d6, d11[0], #0 │ │ add.w r8, sp, #144 @ 0x90 │ │ ldr r0, [r0, #4] │ │ lsls r1, r0, #21 │ │ bpl.n 21d61b0 │ │ ldr r0, [pc, #936] @ (21d6504 ) │ │ @@ -508580,36 +508580,36 @@ │ │ strd r8, r0, [sp, #8] │ │ strd r2, r0, [sp] │ │ add r0, sp, #112 @ 0x70 │ │ movs r2, #16 │ │ bl 221a63c │ │ b.n 21d6638 │ │ adds r0, #49 @ 0x31 │ │ - cdp2 12, 0, cr10, cr4, cr9, {7} │ │ + mcr2 13, 0, sl, cr4, cr6, {0} │ │ @ instruction: 0xfe049a62 │ │ - mcr2 3, 0, r0, cr7, cr4, {6} │ │ - mcr2 11, 0, r8, cr6, cr0, {4} @ │ │ - mcr2 3, 0, r0, cr4, cr14, {3} │ │ - @ instruction: 0xfe064bcf │ │ - @ instruction: 0xfe05abe7 │ │ - @ instruction: 0xfe04a967 │ │ - mcr2 11, 0, sl, cr5, cr7, {4} @ │ │ - mcr2 10, 0, r4, cr4, cr9, {7} @ │ │ + cdp2 4, 0, cr0, cr7, cr1, {0} │ │ + mcr2 11, 0, r8, cr6, cr13, {5} @ │ │ + cdp2 3, 0, cr0, cr4, cr11, {5} │ │ + mcr2 11, 0, r4, cr6, cr12, {7} @ │ │ + mcr2 12, 0, sl, cr5, cr4, {0} │ │ + mcr2 9, 0, sl, cr4, cr4, {4} @ │ │ + @ instruction: 0xfe05abc4 │ │ + vseleq.f64 d4, d4, d22 │ │ cdp2 5, 0, cr15, cr5, cr0, {4} │ │ lsls r4, r2, #1 │ │ sbcs.w r0, r4, #13893632 @ 0xd40000 │ │ - strh r0, [r2, #50] @ 0x32 │ │ + strh r5, [r7, #50] @ 0x32 │ │ mcr2 5, 0, lr, cr5, cr1, {0} │ │ cdp2 15, 0, cr13, cr3, cr13, {6} │ │ - mcr2 12, 0, lr, cr6, cr3, {6} │ │ + vdot.bf16 d14, d6, d0[0] │ │ mcr2 11, 0, r0, cr4, cr7, {6} @ │ │ cdp2 15, 0, cr13, cr4, cr10, {5} │ │ mcr2 6, 0, r8, cr6, cr10, {2} │ │ - cdp2 0, 0, cr0, cr6, cr14, {6} │ │ - mcr2 12, 0, lr, cr6, cr12, {3} │ │ + mcr2 0, 0, r0, cr6, cr11, {7} │ │ + cdp2 12, 0, cr14, cr6, cr9, {5} │ │ mcr2 3, 0, sl, cr4, cr13, {3} │ │ @ instruction: 0xfe063944 │ │ vseleq.f16 s6, s14, s5 │ │ @ instruction: 0xfe0749c6 │ │ movs r0, #0 │ │ str r0, [sp, #160] @ 0xa0 │ │ add r1, pc │ │ @@ -508983,24 +508983,24 @@ │ │ strd r2, r0, [sp] │ │ movs r2, #16 │ │ strd r8, r0, [sp, #8] │ │ add r0, sp, #112 @ 0x70 │ │ bl 221a63c │ │ b.n 21d69c8 │ │ nop │ │ - stmia r0!, {r1, r2, r3, r4, r6, r7} │ │ + stmia r1!, {r0, r1, r3} │ │ cdp2 2, 0, cr10, cr5, cr2, {5} │ │ - mcr2 6, 0, r4, cr6, cr1, {4} │ │ + mcr2 6, 0, r4, cr6, cr14, {5} │ │ @ instruction: 0xfe0509ee │ │ - cdp2 0, 0, cr12, cr4, cr14, {1} │ │ - cdp2 4, 0, cr12, cr5, cr14, {5} │ │ + mcr2 0, 0, ip, cr4, cr11, {2} │ │ + mcr2 4, 0, ip, cr5, cr11, {6} │ │ cdp2 7, 0, cr3, cr4, cr2, {2} │ │ vseleq.f16 s0, s14, s5 │ │ - mcr2 4, 0, r6, cr4, cr3, {4} │ │ - cdp2 3, 0, cr12, cr4, cr0, {7} │ │ + cdp2 4, 0, cr6, cr4, cr0, {6} │ │ + cdp2 4, 0, cr12, cr4, cr13, {0} │ │ mcr2 6, 0, r3, cr4, cr4, {3} │ │ vfmal.f16 q0, d7, d4[0] │ │ cdp2 5, 0, cr3, cr4, cr10, {3} │ │ mcr2 0, 0, sl, cr7, cr6, {2} │ │ cdp2 5, 0, cr3, cr6, cr6, {5} │ │ mcr2 7, 0, r0, cr7, cr12, {3} │ │ mcr2 15, 0, sp, cr4, cr8, {6} │ │ @@ -509371,29 +509371,29 @@ │ │ mov r0, r6 │ │ blx 2701ed0 │ │ ldr r0, [sp, #44] @ 0x2c │ │ ldrh r0, [r0, #0] │ │ b.n 21d6cca │ │ nop │ │ lsls r0, r4, #25 │ │ - cdp2 15, 0, cr7, cr4, cr8, {7} │ │ + mcr2 0, 0, r8, cr4, cr5, {0} │ │ cdp2 14, 0, cr9, cr5, cr2, {3} │ │ - mcr2 2, 0, r2, cr6, cr15, {3} │ │ + cdp2 2, 0, cr2, cr6, cr12, {5} │ │ mcr2 5, 0, r2, cr5, cr10, {1} │ │ mcr2 15, 0, r7, cr4, cr2, {4} │ │ mcr2 9, 0, r1, cr6, cr10, {6} @ │ │ - mcr2 10, 0, pc, cr7, cr6, {0} @ │ │ + @ instruction: 0xfe07fa43 │ │ cdp2 15, 0, cr7, cr5, cr2, {2} │ │ vcmla.f16 , q3, d4[0], #0 │ │ mcr2 13, 0, fp, cr6, cr11, {2} │ │ - mcr2 2, 0, sl, cr3, cr9, {3} │ │ - vdot.bf16 , q10, d0[0] │ │ + cdp2 2, 0, cr10, cr3, cr6, {5} │ │ + vdot.bf16 , q10, d13[1] │ │ mcr2 1, 0, r3, cr5, cr14, {3} │ │ mcr2 2, 0, r7, cr7, cr13, {5} │ │ - mcr2 9, 0, fp, cr7, cr2, {7} @ │ │ + mcr2 10, 0, fp, cr7, cr15, {0} @ │ │ mcr2 6, 0, sp, cr5, cr12, {4} │ │ mcr2 2, 0, pc, cr6, cr14, {4} @ │ │ mcr2 2, 0, r2, cr6, cr15, {2} │ │ @ instruction: 0xfe0449c5 │ │ ldr r0, [sp, #24] │ │ add r1, pc │ │ str r0, [sp, #160] @ 0xa0 │ │ @@ -509714,15 +509714,15 @@ │ │ ldrb.w r0, [sp, #96] @ 0x60 │ │ lsls r0, r0, #31 │ │ beq.n 21d7162 │ │ ldr r0, [sp, #104] @ 0x68 │ │ blx 26ffb40 │ │ b.n 21d7162 │ │ lsls r0, r5, #8 │ │ - cdp2 15, 0, cr9, cr4, cr10, {2} │ │ + mcr2 15, 0, r9, cr4, cr7, {3} │ │ vseleq.f32 s18, s8, s13 │ │ vfmal.f16 d15, s13, s10[1] │ │ movs r0, r6 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #56] @ 0x38 │ │ blxne 26ffb40 │ │ @@ -509759,26 +509759,26 @@ │ │ ldrb.w r0, [sp, #84] @ 0x54 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #92] @ 0x5c │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ rev16 r7, r7 │ │ - cdp2 15, 0, cr9, cr3, cr2, {4} │ │ + cdp2 15, 0, cr9, cr3, cr15, {5} │ │ mcr2 1, 0, r7, cr4, cr2, {1} │ │ mcr2 9, 0, lr, cr7, cr8, {4} @ │ │ lsls r4, r2, #1 │ │ @ instruction: 0xe9980054 │ │ movs r0, #173 @ 0xad │ │ mcr2 12, 0, r0, cr4, cr8, {2} │ │ lsls r6, r2, #1 │ │ - subs r3, r1, r1 │ │ + subs r0, r7, r1 │ │ mcr2 6, 0, r0, cr6, cr10, {4} │ │ lsls r6, r2, #1 │ │ - subs r6, r5, #4 │ │ + subs r3, r3, #5 │ │ vseleq.f64 d11, d5, d4 │ │ mcr2 5, 0, fp, cr3, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #220 @ 0xdc │ │ mov r4, r0 │ │ ldr.w r0, [pc, #1328] @ 21d76e0 │ │ @@ -510229,16 +510229,16 @@ │ │ adds r1, r0, #4 │ │ add r0, sp, #64 @ 0x40 │ │ blx 26ffd00 │ │ b.n 21d768c │ │ nop │ │ ldrh r5, [r0, #12] │ │ mcr2 9, 0, r8, cr7, cr5, {3} @ │ │ - cdp2 3, 0, cr11, cr7, cr3, {7} │ │ - mcr2 11, 0, r9, cr5, cr15, {3} @ │ │ + mcr2 4, 0, fp, cr7, cr0, {0} │ │ + vseleq.f64 d9, d21, d28 │ │ vcmla.f16 d9, d4, d9[0], #0 │ │ blx 26ffd10 │ │ blx 26ffb60 │ │ b.n 21d76ac │ │ b.n 21d76ac │ │ b.n 21d76ac │ │ b.n 21d76ba │ │ @@ -510268,30 +510268,30 @@ │ │ add r0, sp, #64 @ 0x40 │ │ blx 2703800 │ │ blx 26ffb60 │ │ nop │ │ lsls r4, r7, #17 │ │ lsls r6, r2, #1 │ │ vshr.u16 q8, , #10 │ │ - ldrh r5, [r4, r7] │ │ - mcr2 11, 0, r5, cr5, cr5, {6} @ │ │ - @ instruction: 0xfe059aef │ │ + ldrb r2, [r2, r0] │ │ + cdp2 12, 0, cr5, cr5, cr2, {0} │ │ + mcr2 11, 0, r9, cr5, cr12, {0} @ │ │ vfmal.f16 d3, s8, s10[0] │ │ vcmla.f16 d3, d6, d5[0], #0 │ │ - mcr2 10, 0, r9, cr6, cr5, {2} @ │ │ - @ instruction: 0xfe04396c │ │ - mcr2 9, 0, r3, cr5, cr12, {2} @ │ │ - @ instruction: 0xfe0599c5 │ │ + vseleq.f32 s18, s13, s4 │ │ + mcr2 9, 0, r3, cr4, cr9, {4} @ │ │ + vseleq.f16 s6, s11, s18 │ │ + mcr2 9, 0, r9, cr5, cr2, {7} @ │ │ vseleq.f16 s4, s8, s24 │ │ vfmal.f16 q1, d23, d4[3] │ │ - vseleq.f16 s18, s14, s11 │ │ + mcr2 9, 0, r9, cr7, cr2, {2} @ │ │ mcr2 2, 0, r9, cr4, cr8, {7} │ │ cdp2 2, 0, cr9, cr6, cr8, {7} │ │ @ instruction: 0xfe06eac0 │ │ - vcmla.f16 d9, d22, d7[0], #0 │ │ + vfmal.f16 d9, s13, s9[0] │ │ mcr2 5, 0, fp, cr4, cr0, {7} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #16 │ │ mov r5, r1 │ │ ldr r1, [pc, #640] @ (21d79b8 ) │ │ ldr r4, [pc, #644] @ (21d79bc ) │ │ @@ -510553,15 +510553,15 @@ │ │ nop │ │ lsls r5, r4, #16 │ │ movs r0, r0 │ │ subs r2, #115 @ 0x73 │ │ movs r0, r0 │ │ mcr2 0, 7, r0, cr10, cr5, {2} │ │ ldr r4, [sp, #912] @ 0x390 │ │ - cdp2 4, 0, cr3, cr7, cr3, {7} │ │ + mcr2 5, 0, r3, cr7, cr0, {0} │ │ cdp2 6, 0, cr3, cr5, cr15, {7} │ │ mcr2 12, 0, pc, cr4, cr0, {6} @ │ │ lsls r5, r2, #1 │ │ ldr r6, [sp, #216] @ 0xd8 │ │ cdp2 15, 0, cr9, cr7, cr12, {2} │ │ cdp2 15, 0, cr9, cr7, cr2, {0} │ │ cdp2 5, 0, cr10, cr7, cr0, {3} │ │ @@ -510692,22 +510692,22 @@ │ │ b.n 21d7b30 │ │ ldrb r0, [r4, #0] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [r4, #8] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ - strb r7, [r2, #0] │ │ + strb r4, [r0, #1] │ │ mcr2 6, 0, lr, cr5, cr14, {3} │ │ mcr2 9, 0, ip, cr6, cr9, {6} @ │ │ cdp2 12, 0, cr15, cr6, cr4, {1} │ │ lsls r5, r2, #1 │ │ - str r3, [sp, #924] @ 0x39c │ │ + str r4, [sp, #80] @ 0x50 │ │ cdp2 5, 0, cr6, cr4, cr9, {5} │ │ - mcr2 10, 0, lr, cr7, cr14, {6} @ │ │ + vseleq.f64 d14, d7, d11 │ │ mcr2 1, 0, r8, cr5, cr9, {3} │ │ vseleq.f64 d15, d7, d26 │ │ lsls r5, r2, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #40 @ 0x28 │ │ ldr r5, [pc, #92] @ (21d7bc8 ) │ │ @@ -510746,15 +510746,15 @@ │ │ ldr r1, [r1, #0] │ │ cmp r1, r0 │ │ itt eq │ │ addeq sp, #40 @ 0x28 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ @ instruction: 0xfabe0055 │ │ - ldrh r0, [r0, #62] @ 0x3e │ │ + ldrh r5, [r5, #62] @ 0x3e │ │ cdp2 4, 0, cr6, cr4, cr8, {4} │ │ mcr2 13, 0, sp, cr12, cr14, {2} │ │ lsls r4, r2, #1 │ │ ldmia r0, {r0, r1, r2, r6} │ │ mcr2 10, 0, pc, cr6, cr6, {3} @ │ │ lsls r5, r2, #1 │ │ │ │ @@ -510796,15 +510796,15 @@ │ │ cdp2 15, 0, cr15, cr7, cr10, {1} │ │ lsls r5, r2, #1 │ │ ldr r1, [pc, #8] @ (21d7c44 ) │ │ add r1, pc │ │ add r0, sp, #140 @ 0x8c │ │ blx 2701ed0 │ │ b.n 21d7c48 │ │ - bl 2310850 │ │ + bl 233d850 │ │ ldr r0, [pc, #12] @ (21d7c58 ) │ │ add r0, pc │ │ ldrd r1, r2, [r0] │ │ add r0, sp, #140 @ 0x8c │ │ blx 26ffbe0 │ │ b.n 21d7c5c │ │ bgt.n 21d7cd0 │ │ @@ -511265,35 +511265,35 @@ │ │ ldrne r0, [sp, #160] @ 0xa0 │ │ blxne 26ffb40 │ │ ldrh.w r0, [r9, #2] │ │ cmp r0, #128 @ 0x80 │ │ bne.n 21d8190 │ │ movs r0, #128 @ 0x80 │ │ b.n 21d8200 │ │ - bl 22aad48 │ │ - str r0, [sp, #860] @ 0x35c │ │ + bl 22d7d48 │ │ + str r1, [sp, #16] │ │ mcr2 10, 0, r8, cr4, cr10, {7} @ │ │ - mcr2 0, 0, r9, cr6, cr13, {3} │ │ + cdp2 0, 0, cr9, cr6, cr10, {5} │ │ cdp2 4, 0, cr4, cr4, cr6, {0} │ │ - cdp2 0, 0, cr9, cr7, cr3, {1} │ │ - mcr2 15, 0, r2, cr4, cr0, {4} │ │ - cdp2 15, 0, cr8, cr5, cr9, {6} │ │ + mcr2 0, 0, r9, cr7, cr0, {2} │ │ + mcr2 15, 0, r2, cr4, cr13, {5} │ │ + mcr2 15, 0, r8, cr5, cr6, {7} │ │ vseleq.f32 s24, s8, s3 │ │ - cdp2 15, 0, cr8, cr3, cr15, {3} │ │ + mcr2 15, 0, r8, cr3, cr12, {4} │ │ mcr2 15, 0, r1, cr4, cr8, {0} │ │ - mcr2 15, 0, r8, cr7, cr5, {0} │ │ - mcr2 12, 0, sl, cr4, cr5, {0} │ │ - mcr2 14, 0, r8, cr4, cr11, {5} │ │ + cdp2 15, 0, cr8, cr7, cr2, {2} │ │ + cdp2 12, 0, cr10, cr4, cr2, {2} │ │ + cdp2 14, 0, cr8, cr4, cr8, {7} │ │ cdp2 5, 0, cr0, cr4, cr5, {2} │ │ - cdp2 6, 0, cr10, cr7, cr13, {1} │ │ - vdot.bf16 q4, , d13[0] │ │ - cdp2 12, 0, cr8, cr4, cr1, {7} │ │ + mcr2 6, 0, sl, cr7, cr10, {2} │ │ + mcr2 13, 0, r8, cr5, cr10, {7} │ │ + vdot.bf16 d8, d4, d14[0] │ │ cdp2 15, 0, cr13, cr4, cr10, {5} │ │ - vdot.bf16 q4, q3, d7[1] │ │ - vseleq.f16 s12, s8, s9 │ │ + mcr2 13, 0, r8, cr6, cr4, {4} │ │ + mcr2 9, 0, r6, cr4, cr1, {2} @ │ │ mcr2 9, 0, r4, cr5, cr11, {6} @ │ │ movs r2, #6 │ │ ldr r0, [pc, #876] @ (21d8504 ) │ │ add r1, pc │ │ add r0, pc │ │ strd r0, r2, [sp, #224] @ 0xe0 │ │ movs r0, #4 │ │ @@ -511619,29 +511619,29 @@ │ │ mov.w fp, #0 │ │ mov.w r9, #0 │ │ b.n 21d8578 │ │ stmia r2!, {r0, r3, r6} │ │ mcr2 11, 0, fp, cr6, cr15, {6} @ │ │ cdp2 1, 0, cr12, cr6, cr7, {6} │ │ mcr2 14, 0, r7, cr6, cr12, {7} │ │ - mcr2 12, 0, r4, cr6, cr3, {5} │ │ + cdp2 12, 0, cr4, cr6, cr0, {7} │ │ mcr2 1, 0, ip, cr5, cr13, {2} │ │ - mcr2 10, 0, lr, cr6, cr13, {6} @ │ │ - vseleq.f64 d8, d20, d5 │ │ + vseleq.f64 d14, d6, d10 │ │ + mcr2 11, 0, r8, cr4, cr2, {5} @ │ │ cdp2 2, 0, cr0, cr4, cr2, {0} │ │ - mcr2 11, 0, r8, cr7, cr3, {1} @ │ │ + @ instruction: 0xfe078b60 │ │ @ instruction: 0xfe040a61 │ │ cdp2 0, 0, cr12, cr4, cr13, {3} │ │ vseleq.f32 s4, s12, s12 │ │ - mcr2 10, 0, r8, cr4, cr15, {3} @ │ │ - mcr2 9, 0, lr, cr4, cr3, {6} @ │ │ - vseleq.f32 s16, s8, s22 │ │ + vseleq.f32 s16, s9, s25 │ │ + vseleq.f32 s28, s8, s0 │ │ + mcr2 10, 0, r8, cr4, cr8, {1} @ │ │ cdp2 4, 0, cr10, cr4, cr14, {5} │ │ cdp2 15, 0, cr11, cr3, cr9, {2} │ │ - mcr2 7, 0, r6, cr6, cr9, {7} │ │ + vcmla.f16 d6, d6, d6[1], #0 │ │ vfmal.f16 d15, s9, s10[1] │ │ lsls r0, r3, #2 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #160] @ 0xa0 │ │ blxne 26ffb40 │ │ ldrb.w r0, [sp, #256] @ 0x100 │ │ @@ -511946,27 +511946,27 @@ │ │ b.n 21d8b64 │ │ add r4, sp, #140 @ 0x8c │ │ mov.w sl, #221 @ 0xdd │ │ movw fp, #557 @ 0x22d │ │ mov.w r8, #0 │ │ mov.w r9, #0 │ │ b.n 21d88ce │ │ - lsls r6, r5, #12 │ │ - cdp2 7, 0, cr2, cr5, cr15, {1} │ │ - vfmal.f16 d8, s11, s10[0] │ │ - vfmal.f16 d8, s8, s7[1] │ │ - cdp2 15, 0, cr13, cr4, cr7, {0} │ │ - mcr2 0, 0, sl, cr5, cr8, {1} │ │ - cdp2 0, 0, cr10, cr5, cr12, {1} │ │ + lsls r3, r3, #13 │ │ + mcr2 7, 0, r2, cr5, cr12, {2} │ │ + vcmla.f16 q4, , d2[0], #0 │ │ + vcmla.f16 q4, q2, d8[1], #0 │ │ + mcr2 15, 0, sp, cr4, cr4, {1} │ │ + cdp2 0, 0, cr10, cr5, cr5, {3} │ │ + mcr2 0, 0, sl, cr5, cr9, {2} │ │ vdot.bf16 , , d1[1] │ │ mcr2 12, 0, fp, cr6, cr11, {5} │ │ - mcr2 2, 0, r6, cr6, cr1, {7} │ │ - cdp2 6, 0, cr8, cr5, cr15, {6} │ │ + mcr2 3, 0, r6, cr6, cr14, {0} │ │ + mcr2 6, 0, r8, cr5, cr12, {7} │ │ cdp2 2, 0, cr6, cr4, cr7, {1} │ │ - mcr2 5, 0, r6, cr6, cr12, {4} │ │ + cdp2 5, 0, cr6, cr6, cr9, {6} │ │ mcr2 10, 0, pc, cr4, cr12, {1} @ │ │ lsls r5, r2, #1 │ │ add.w r9, r9, #1 │ │ cmp r9, r1 │ │ bcs.w 21d8432 │ │ mov.w r2, r9, lsl #3 │ │ str r2, [sp, #44] @ 0x2c │ │ @@ -512245,33 +512245,33 @@ │ │ cmp r0, #255 @ 0xff │ │ bgt.n 21d8c00 │ │ cmp r0, #1 │ │ it ne │ │ cmpne r0, #128 @ 0x80 │ │ beq.n 21d8c0e │ │ b.w 21da892 │ │ - str r2, [r4, #20] │ │ - mcr2 14, 0, r9, cr5, cr2, {1} │ │ - mcr2 5, 0, r8, cr5, cr5, {0} │ │ - cdp2 4, 0, cr6, cr4, cr0, {4} │ │ + str r7, [r1, #24] │ │ + mcr2 14, 0, r9, cr5, cr15, {2} │ │ + cdp2 5, 0, cr8, cr5, cr2, {2} │ │ + cdp2 4, 0, cr6, cr4, cr13, {5} │ │ cdp2 15, 0, cr11, cr4, cr15, {5} │ │ - mcr2 5, 0, r8, cr3, cr9, {1} │ │ - cdp2 3, 0, cr6, cr4, cr12, {7} │ │ - vseleq.f64 d13, d20, d15 │ │ - cdp2 4, 0, cr8, cr5, cr5, {5} │ │ - mcr2 3, 0, r6, cr4, cr8, {2} │ │ + cdp2 5, 0, cr8, cr3, cr6, {3} │ │ + mcr2 4, 0, r6, cr4, cr9, {0} │ │ + mcr2 11, 0, sp, cr4, cr12, {5} @ │ │ + mcr2 4, 0, r8, cr5, cr2, {6} │ │ + cdp2 3, 0, cr6, cr4, cr5, {4} │ │ cdp2 5, 0, cr14, cr4, cr3, {5} │ │ - mcr2 4, 0, r8, cr3, cr1, {0} │ │ - cdp2 2, 0, cr6, cr4, cr4, {6} │ │ - mcr2 5, 0, ip, cr4, cr6, {7} │ │ - mcr2 3, 0, r8, cr4, cr13, {3} │ │ + mcr2 4, 0, r8, cr3, cr14, {1} │ │ + mcr2 2, 0, r6, cr4, cr1, {7} │ │ + cdp2 6, 0, cr12, cr4, cr3, {1} │ │ + cdp2 3, 0, cr8, cr4, cr10, {5} │ │ mcr2 4, 0, r5, cr4, cr2, {0} │ │ mcr2 4, 0, sp, cr7, cr11, {3} │ │ - cdp2 2, 0, cr14, cr6, cr7, {1} │ │ - mcr2 15, 0, r7, cr4, cr11, {5} │ │ + mcr2 2, 0, lr, cr6, cr4, {2} │ │ + cdp2 15, 0, cr7, cr4, cr8, {7} │ │ mcr2 5, 0, pc, cr5, cr0, {5} @ │ │ ldrb r0, [r0, #30] │ │ it ne │ │ cmpne.w r0, #1024 @ 0x400 │ │ bne.w 21da892 │ │ ldrh r0, [r5, #0] │ │ cmp r0, #0 │ │ @@ -512535,23 +512535,23 @@ │ │ mov r0, r6 │ │ blx 2701ed0 │ │ b.n 21d8f86 │ │ adds r6, #22 │ │ mcr2 13, 0, r9, cr7, cr3, {5} │ │ mcr2 2, 0, lr, cr3, cr3, {7} │ │ cdp2 12, 0, cr9, cr3, cr3, {6} │ │ - mcr2 14, 0, r7, cr3, cr11, {2} │ │ + cdp2 14, 0, cr7, cr3, cr8, {4} │ │ mcr2 3, 0, r3, cr5, cr6, {6} │ │ - mcr2 15, 0, r7, cr7, cr6, {7} │ │ + cdp2 0, 0, cr8, cr7, cr3, {1} │ │ mcr2 14, 0, r6, cr4, cr14, {0} │ │ - mcr2 15, 0, pc, cr7, cr1, {0} @ │ │ + mcr2 15, 0, pc, cr7, cr14, {1} @ │ │ mcr2 2, 0, r9, cr4, cr6, {2} │ │ cdp2 5, 0, cr9, cr6, cr5, {1} │ │ vfmal.f16 , d6, d4[3] │ │ - cdp2 0, 0, cr8, cr6, cr7, {2} │ │ + mcr2 0, 0, r8, cr6, cr4, {3} │ │ mcr2 11, 0, r9, cr4, cr3, {5} @ │ │ vseleq.f32 s14, s6, s3 │ │ cdp2 1, 0, cr13, cr6, cr14, {7} │ │ @ instruction: 0xfe0649c9 │ │ movs r2, #9 │ │ ldr r0, [pc, #804] @ (21d9210 ) │ │ add r1, pc │ │ @@ -512844,24 +512844,24 @@ │ │ moveq r1, r3 │ │ lsreq r2, r0, #1 │ │ mov r0, r6 │ │ blx 26ffbe0 │ │ b.n 21d9288 │ │ ldrh r0, [r3, r5] │ │ mcr2 4, 0, fp, cr6, cr8, {4} │ │ - vdot.bf16 , q3, d15[1] │ │ + mcr2 13, 0, r5, cr6, cr12, {4} │ │ mcr2 10, 0, r5, cr5, cr8, {5} @ │ │ cdp2 0, 0, cr5, cr6, cr14, {4} │ │ cdp2 1, 0, cr0, cr7, cr6, {6} │ │ - mcr2 6, 0, r9, cr4, cr4, {4} │ │ + cdp2 6, 0, cr9, cr4, cr1, {6} │ │ mcr2 1, 0, r0, cr5, cr4, {2} │ │ mcr2 1, 0, r3, cr4, cr0, {5} │ │ mcr2 2, 0, fp, cr7, cr4, {6} │ │ mcr2 9, 0, r5, cr6, cr0, {4} @ │ │ - mcr2 4, 0, fp, cr6, cr11, {6} │ │ + cdp2 5, 0, cr11, cr6, cr8, {0} │ │ cdp2 14, 0, cr4, cr5, cr10, {6} │ │ cdp2 0, 0, cr0, cr7, cr2, {0} │ │ cdp2 12, 0, cr0, cr4, cr14, {2} │ │ vseleq.f16 s18, s14, s28 │ │ mov r0, r9 │ │ mov r2, r5 │ │ bl 21e1a98 const&, Eigen::Matrix const&)@@Base+0x1d4> │ │ @@ -513146,22 +513146,22 @@ │ │ mov sl, r0 │ │ b.n 21d959c │ │ lsrs r0, r2, #15 │ │ cdp2 7, 0, cr5, cr7, cr10, {4} │ │ @ instruction: 0xfe066966 │ │ mcr2 5, 0, r7, cr7, cr8, {2} │ │ mcr2 6, 0, r5, cr6, cr4, {5} │ │ - cdp2 2, 0, cr11, cr6, cr6, {0} │ │ + mcr2 2, 0, fp, cr6, cr3, {1} │ │ mcr2 10, 0, r0, cr5, cr9, {4} @ │ │ cdp2 6, 0, cr5, cr7, cr12, {0} │ │ mcr2 7, 0, r6, cr6, cr13, {4} │ │ mcr2 7, 0, r1, cr7, cr2, {4} │ │ - mcr2 7, 0, r1, cr6, cr7, {7} │ │ - mcr2 7, 0, r5, cr5, cr12, {5} │ │ - mcr2 6, 0, r3, cr4, cr9, {5} │ │ + vcmla.f16 d1, d6, d4[1], #0 │ │ + cdp2 7, 0, cr5, cr5, cr9, {7} │ │ + cdp2 6, 0, cr3, cr4, cr6, {7} │ │ cdp2 2, 0, cr3, cr4, cr6, {5} │ │ mcr2 5, 0, r5, cr6, cr0, {0} │ │ cdp2 2, 0, cr3, cr6, cr3, {5} │ │ vfmal.f16 d15, s13, s10[1] │ │ lsls r4, r0, #1 │ │ lsls r0, r0, #31 │ │ itt ne │ │ @@ -513320,16 +513320,16 @@ │ │ add.w fp, sp, #184 @ 0xb8 │ │ add.w r8, sl, #1 │ │ mov.w r9, #0 │ │ movs r2, #0 │ │ movs r4, #0 │ │ b.n 21d9784 │ │ strb r6, [r7, #8] │ │ - mcr2 7, 0, r1, cr6, cr4, {3} │ │ - mcr2 15, 0, r6, cr5, cr7, {7} │ │ + cdp2 7, 0, cr1, cr6, cr1, {5} │ │ + cdp2 0, 0, cr7, cr5, cr4, {1} │ │ vdot.bf16 d10, d4, d1[0] │ │ cdp2 2, 0, cr9, cr6, cr6, {2} │ │ vfmal.f16 d4, s7, s10[0] │ │ cdp2 0, 0, cr3, cr7, cr8, {5} │ │ vfmal.f16 d15, s13, s10[1] │ │ lsls r0, r3, #3 │ │ lsls r0, r0, #31 │ │ @@ -513743,33 +513743,33 @@ │ │ add r0, sp, #168 @ 0xa8 │ │ movs r4, #0 │ │ mov.w fp, #0 │ │ movs r5, #0 │ │ adds r0, #1 │ │ str r0, [sp, #36] @ 0x24 │ │ b.n 21d9c50 │ │ - add r5, sp, #672 @ 0x2a0 │ │ - mcr2 5, 0, sp, cr5, cr13, {5} │ │ + add r5, sp, #852 @ 0x354 │ │ + cdp2 5, 0, cr13, cr5, cr10, {7} │ │ mcr2 2, 0, r5, cr4, cr2, {0} │ │ cdp2 15, 0, cr6, cr6, cr10, {6} │ │ mcr2 1, 0, r5, cr6, cr12, {1} │ │ - mcr2 12, 0, ip, cr6, cr10, {2} │ │ + cdp2 12, 0, cr12, cr6, cr7, {4} │ │ vfmal.f16 q1, d5, d3[1] │ │ - cdp2 1, 0, cr5, cr7, cr7, {0} │ │ + mcr2 1, 0, r5, cr7, cr4, {1} │ │ cdp2 2, 0, cr6, cr5, cr15, {2} │ │ - cdp2 2, 0, cr3, cr7, cr11, {0} │ │ + mcr2 2, 0, r3, cr7, cr8, {1} │ │ mcr2 0, 0, r5, cr4, cr12, {3} │ │ mcr2 14, 0, r6, cr6, cr2, {1} │ │ - cdp2 3, 0, cr1, cr6, cr4, {2} │ │ + mcr2 3, 0, r1, cr6, cr1, {3} │ │ cdp2 5, 0, cr12, cr5, cr1, {7} │ │ mcr2 5, 0, r4, cr6, cr8, {1} │ │ mcr2 6, 0, r2, cr7, cr11, {1} │ │ mcr2 6, 0, r2, cr7, cr10, {1} │ │ - cdp2 14, 0, cr4, cr7, cr13, {7} │ │ - cdp2 3, 0, cr3, cr5, cr13, {1} │ │ + mcr2 15, 0, r4, cr7, cr10, {0} │ │ + mcr2 3, 0, r3, cr5, cr10, {2} │ │ vfmal.f16 d10, s10, s5[0] │ │ vfmal.f16 d15, s13, s10[1] │ │ lsls r0, r3, #2 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #160] @ 0xa0 │ │ blxne 26ffb40 │ │ @@ -514131,27 +514131,27 @@ │ │ mov.w r0, r8, lsl #1 │ │ cmp.w r8, #0 │ │ mov.w r4, #0 │ │ strb.w r0, [sp, #152] @ 0x98 │ │ bne.n 21da076 │ │ b.n 21da080 │ │ movs r5, #224 @ 0xe0 │ │ - cdp2 0, 0, cr5, cr7, cr10, {2} │ │ - mcr2 14, 0, r8, cr4, cr2, {4} │ │ + mcr2 0, 0, r5, cr7, cr7, {3} │ │ + mcr2 14, 0, r8, cr4, cr15, {5} │ │ mcr2 5, 0, r2, cr4, cr4, {1} │ │ - vfmal.f16 d12, s14, s5[1] │ │ - mcr2 13, 0, r8, cr5, cr7, {7} │ │ + vcmla.f16 q6, , d7[1], #0 │ │ + cdp2 14, 0, cr8, cr5, cr4, {1} │ │ cdp2 4, 0, cr2, cr4, cr12, {7} │ │ - cdp2 7, 0, cr12, cr7, cr14, {5} │ │ - cdp2 7, 0, cr12, cr5, cr8, {0} │ │ + mcr2 7, 0, ip, cr7, cr11, {6} │ │ + mcr2 7, 0, ip, cr5, cr5, {1} │ │ cdp2 4, 0, cr2, cr5, cr8, {0} │ │ - cdp2 2, 0, cr11, cr7, cr3, {3} │ │ - cdp2 6, 0, cr12, cr4, cr0, {7} │ │ + mcr2 2, 0, fp, cr7, cr0, {4} │ │ + cdp2 7, 0, cr12, cr4, cr13, {0} │ │ @ instruction: 0xfe054b6e │ │ - cdp2 14, 0, cr14, cr6, cr6, {1} │ │ + mcr2 14, 0, lr, cr6, cr3, {2} │ │ mcr2 9, 0, r6, cr4, cr10, {1} @ │ │ mcr2 15, 0, ip, cr6, cr7, {7} │ │ cdp2 0, 0, cr15, cr3, cr8, {2} │ │ movs r7, r1 │ │ add.w sl, r0, #1 │ │ mov r0, sl │ │ blx 26ffbf0 │ │ @@ -514467,34 +514467,34 @@ │ │ bmi.n 21da3fc │ │ lsls r0, r0, #30 │ │ bmi.w 21da522 │ │ ldr r1, [pc, #80] @ (21da3f8 ) │ │ add r1, pc │ │ b.n 21da400 │ │ nop │ │ - add r5, pc, #176 @ (adr r5, 21da460 ) │ │ - vdot.bf16 q6, , d3[0] │ │ + add r5, pc, #356 @ (adr r5, 21da514 ) │ │ + mcr2 13, 0, ip, cr5, cr0, {3} │ │ mcr2 9, 0, r4, cr4, cr2, {4} @ │ │ cdp2 7, 0, cr6, cr6, cr4, {2} │ │ cdp2 0, 0, cr2, cr6, cr4, {5} │ │ mcr2 5, 0, r2, cr7, cr10, {7} │ │ - mcr2 14, 0, sl, cr6, cr8, {6} │ │ - @ instruction: 0xfe04696e │ │ + cdp2 15, 0, cr10, cr6, cr5, {0} │ │ + mcr2 9, 0, r6, cr4, cr11, {4} @ │ │ mcr2 9, 0, r5, cr5, cr11, {5} @ │ │ - mcr2 9, 0, r2, cr7, cr7, {3} @ │ │ + vseleq.f16 s4, s15, s9 │ │ cdp2 7, 0, cr4, cr4, cr6, {7} │ │ mcr2 5, 0, r6, cr6, cr14, {4} │ │ - cdp2 6, 0, cr14, cr6, cr14, {1} │ │ + mcr2 6, 0, lr, cr6, cr11, {2} │ │ mcr2 12, 0, r0, cr4, cr4, {2} │ │ - cdp2 6, 0, cr4, cr4, cr11, {7} │ │ + mcr2 7, 0, r4, cr4, cr8, {0} │ │ cdp2 2, 0, cr8, cr5, cr2, {3} │ │ - mcr2 9, 0, lr, cr6, cr1, {5} @ │ │ - vdot.bf16 q5, q2, d6[1] │ │ + mcr2 9, 0, lr, cr6, cr14, {6} @ │ │ + mcr2 13, 0, sl, cr4, cr3, {4} │ │ mcr2 12, 0, lr, cr4, cr9, {2} │ │ - vdot.bf16 d10, d19, d3[0] │ │ + mcr2 13, 0, sl, cr3, cr0, {5} │ │ @ instruction: 0xfe044962 │ │ add r1, pc │ │ add r0, sp, #140 @ 0x8c │ │ blx 2701ed0 │ │ ldr r0, [r5, #4] │ │ lsls r1, r0, #28 │ │ bpl.w 21da68c │ │ @@ -514636,15 +514636,15 @@ │ │ b.n 21da406 │ │ nop │ │ subs r3, #172 @ 0xac │ │ mcr2 12, 0, r3, cr7, cr2, {0} │ │ vseleq.f64 d0, d23, d0 │ │ mcr2 10, 0, r0, cr4, cr7, {5} @ │ │ @ instruction: 0xfe040ac7 │ │ - mcr2 7, 0, r4, cr4, cr14, {4} │ │ + cdp2 7, 0, cr4, cr4, cr11, {6} │ │ mcr2 10, 0, ip, cr4, cr4, {5} @ │ │ vcmla.f16 d3, d3, d1[0], #0 │ │ ldr r1, [pc, #996] @ (21da98c ) │ │ and.w r0, r0, #3 │ │ ldr r2, [sp, #20] │ │ add r1, pc │ │ ldrb r0, [r2, r0] │ │ @@ -515015,37 +515015,37 @@ │ │ bl 207d3d8 │ │ b.n 21dadac │ │ b.n 21dad52 │ │ b.n 21dadac │ │ b.n 21dad52 │ │ subs r2, #142 @ 0x8e │ │ mcr2 2, 0, r6, cr7, cr6, {3} │ │ - mcr2 9, 0, r4, cr6, cr3, {1} @ │ │ - mcr2 6, 0, r0, cr4, cr0, {5} │ │ - mcr2 11, 0, sl, cr5, cr6, {0} @ │ │ + @ instruction: 0xfe064960 │ │ + mcr2 6, 0, r0, cr4, cr13, {6} │ │ + @ instruction: 0xfe05ab43 │ │ mcr2 1, 0, r6, cr4, cr6, {5} │ │ vfmal.f16 q0, d22, d5[2] │ │ mcr2 2, 0, r8, cr4, cr9, {6} │ │ - cdp2 6, 0, cr14, cr3, cr13, {3} │ │ + mcr2 6, 0, lr, cr3, cr10, {4} │ │ cdp2 2, 0, cr8, cr4, cr7, {4} │ │ @ instruction: 0xfe031a4d │ │ - cdp2 5, 0, cr14, cr7, cr9, {5} │ │ + mcr2 5, 0, lr, cr7, cr6, {6} │ │ vcmla.f16 d14, d4, d13[0], #0 │ │ mcr2 3, 0, sp, cr3, cr8, {5} │ │ lsls r5, r2, #1 │ │ - stmia r6!, {r2, r3, r4, r6} │ │ + stmia r6!, {r0, r3, r7} │ │ mcr2 1, 0, r8, cr4, cr13, {1} │ │ - vdot.bf16 , , d11[1] │ │ - mcr2 13, 0, r7, cr5, cr3, {4} │ │ - cdp2 12, 0, cr9, cr5, cr11, {6} │ │ + mcr2 14, 0, r7, cr3, cr8, {0} │ │ + vdot.bf16 , , d0[0] │ │ + mcr2 12, 0, r9, cr5, cr8, {7} │ │ mcr2 6, 0, lr, cr5, cr0, {7} │ │ - mcr2 2, 0, r6, cr3, cr5, {1} │ │ - mcr2 3, 0, lr, cr5, cr9, {5} │ │ + cdp2 2, 0, cr6, cr3, cr2, {3} │ │ + cdp2 3, 0, cr14, cr5, cr6, {7} │ │ mcr2 6, 0, r3, cr4, cr15, {1} │ │ - cdp2 15, 0, cr13, cr7, cr3, {6} │ │ + mcr2 15, 0, sp, cr7, cr0, {7} │ │ mcr2 1, 0, lr, cr5, cr14, {6} │ │ b.n 21dab10 │ │ b.n 21dad52 │ │ b.n 21dadac │ │ b.n 21dab10 │ │ b.n 21dad52 │ │ b.n 21dadac │ │ @@ -515794,35 +515794,35 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [r4, #8] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ b.n 21db148 │ │ nop │ │ - @ instruction: 0xb765 │ │ - vcmla.f16 d7, d21, d9[0], #0 │ │ - cdp2 0, 0, cr6, cr5, cr9, {1} │ │ + @ instruction: 0xb792 │ │ + vfmal.f16 d7, s11, s13[0] │ │ + mcr2 0, 0, r6, cr5, cr6, {2} │ │ vcmla.f16 d12, d4, d8[0], #0 │ │ lsls r5, r2, #1 │ │ cbz r6, 21db1ae │ │ - cdp2 15, 0, cr5, cr6, cr5, {6} │ │ - cdp2 0, 0, cr2, cr4, cr0, {4} │ │ - mcr2 15, 0, r5, cr5, cr5, {3} │ │ - mcr2 14, 0, r3, cr4, cr7, {3} │ │ - cdp2 15, 0, cr5, cr4, cr5, {1} │ │ - mcr2 14, 0, sp, cr4, cr11, {4} │ │ - mcr2 14, 0, r5, cr4, cr5, {6} │ │ + mcr2 15, 0, r5, cr6, cr2, {7} │ │ + cdp2 0, 0, cr2, cr4, cr13, {5} │ │ + cdp2 15, 0, cr5, cr5, cr2, {5} │ │ + cdp2 14, 0, cr3, cr4, cr4, {5} │ │ + mcr2 15, 0, r5, cr4, cr2, {2} │ │ + cdp2 14, 0, cr13, cr4, cr8, {6} │ │ + cdp2 15, 0, cr5, cr4, cr2, {0} │ │ cdp2 0, 0, cr3, cr4, cr9, {4} │ │ - cdp2 14, 0, cr5, cr7, cr5, {4} │ │ - cdp2 14, 0, cr11, cr4, cr10, {3} │ │ - mcr2 14, 0, r5, cr4, cr5, {1} │ │ - vdot.bf16 , q10, d4[0] │ │ - vdot.bf16 , q10, d5[1] │ │ + mcr2 14, 0, r5, cr7, cr2, {5} │ │ + mcr2 14, 0, fp, cr4, cr7, {4} │ │ + cdp2 14, 0, cr5, cr4, cr2, {3} │ │ + mcr2 13, 0, r5, cr4, cr1, {7} │ │ + mcr2 14, 0, r5, cr4, cr2, {0} │ │ vseleq.f64 d4, d20, d18 │ │ - mcr2 13, 0, r5, cr7, cr5, {4} │ │ + vdot.bf16 , , d2[0] │ │ cdp2 7, 0, cr5, cr4, cr0, {6} │ │ cdp2 5, 0, cr12, cr6, cr8, {1} │ │ lsls r5, r2, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #40 @ 0x28 │ │ ldr r5, [pc, #92] @ (21db218 ) │ │ @@ -515862,15 +515862,15 @@ │ │ cmp r1, r0 │ │ itt eq │ │ addeq sp, #40 @ 0x28 │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ stmia r4!, {r1, r2, r3, r5, r6} │ │ lsls r5, r2, #1 │ │ - ldr r0, [r6, r5] │ │ + ldr r5, [r3, r6] │ │ mcr2 14, 0, r2, cr4, cr8, {1} │ │ cdp2 7, 0, cr10, cr12, cr14, {0} │ │ lsls r4, r2, #1 │ │ str r1, [sp, #988] @ 0x3dc │ │ cdp2 4, 0, cr12, cr6, cr6, {1} │ │ lsls r5, r2, #1 │ │ push {r4, r5, r6, r7, lr} │ │ @@ -516123,24 +516123,24 @@ │ │ itt eq │ │ addeq r1, r5, #1 │ │ lsreq r2, r0, #1 │ │ mov r0, fp │ │ blx 26ffbe0 │ │ b.n 21db584 │ │ nop │ │ - ldrb r1, [r0, r0] │ │ + ldrb r6, [r5, r0] │ │ mcr2 13, 0, r2, cr4, cr6, {6} │ │ vdot.bf16 d2, d23, d14[1] │ │ cdp2 5, 0, cr5, cr7, cr8, {5} │ │ - vseleq.f32 s10, s13, s3 │ │ + @ instruction: 0xfe065ace │ │ mcr2 13, 0, sl, cr4, cr6, {1} │ │ cdp2 6, 0, cr7, cr6, cr7, {4} │ │ mcr2 12, 0, fp, cr3, cr2, {7} │ │ mcr2 5, 0, r7, cr3, cr11, {4} │ │ - mcr2 13, 0, r9, cr3, cr1, {5} │ │ + mcr2 13, 0, r9, cr3, cr14, {6} │ │ cdp2 4, 0, cr5, cr4, cr14, {3} │ │ cdp2 6, 0, cr12, cr6, cr6, {7} │ │ lsls r5, r2, #1 │ │ movs r2, #13 │ │ str.w r8, [sp, #72] @ 0x48 │ │ strd r0, r2, [sp, #64] @ 0x40 │ │ movs r0, #0 │ │ @@ -516410,28 +516410,28 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne.w r0, [fp, #8] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ stmia r3!, {r3, r5, r6, r7} │ │ lsls r5, r2, #1 │ │ - asrs r0, r1, #30 │ │ + asrs r5, r6, #30 │ │ mcr2 6, 0, ip, cr4, cr10, {6} │ │ lsls r5, r2, #1 │ │ - ldrt pc, [sp, #4] │ │ - bmi.n 21db8a8 │ │ - vseleq.f32 s10, s8, s0 │ │ + strb.w pc, [sl, #3588] @ 0xe04 │ │ + bmi.n 21db702 │ │ + vseleq.f32 s10, s8, s27 │ │ vdot.bf16 d0, d20, d6[1] │ │ vseleq.f32 s26, s14, s31 │ │ - cdp2 0, 0, cr7, cr3, cr0, {7} │ │ + cdp2 1, 0, cr7, cr3, cr13, {0} │ │ mcr2 14, 0, r8, cr5, cr9, {0} │ │ - cdp2 0, 0, cr9, cr6, cr10, {0} │ │ + mcr2 0, 0, r9, cr6, cr7, {1} │ │ cdp2 15, 0, cr11, cr5, cr6, {0} │ │ lsls r5, r2, #1 │ │ - asrs r5, r4, #27 │ │ + asrs r2, r2, #28 │ │ mcr2 12, 0, r0, cr4, cr14, {7} │ │ mcr2 5, 0, fp, cr7, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ sub sp, #128 @ 0x80 │ │ mov r9, r1 │ │ ldr r1, [pc, #852] @ (21dbb88 ) │ │ @@ -516757,37 +516757,37 @@ │ │ movs r7, #61 @ 0x3d │ │ @ instruction: 0xfe07d96a │ │ mcr2 3, 0, pc, cr3, cr15, {5} @ │ │ cdp2 3, 0, cr4, cr5, cr10, {7} │ │ cdp2 7, 0, cr11, cr7, cr6, {7} │ │ cdp2 0, 0, cr1, cr3, cr5, {3} │ │ vfmal.f16 d11, s12, s6[0] │ │ - vdot.bf16 d10, d19, d9[1] │ │ + mcr2 13, 0, sl, cr3, cr6, {6} │ │ cdp2 1, 0, cr3, cr5, cr6, {5} │ │ @ instruction: 0xfe068ae6 │ │ vcmla.f16 d11, d6, d13[0], #0 │ │ - mcr2 7, 0, r9, cr3, cr14, {5} │ │ + cdp2 7, 0, cr9, cr3, cr11, {7} │ │ mcr2 15, 0, r4, cr4, cr5, {2} │ │ cdp2 15, 0, cr0, cr6, cr15, {5} │ │ - cdp2 5, 0, cr15, cr6, cr14, {0} │ │ - vdot.bf16 q3, q2, d15[1] │ │ + mcr2 5, 0, pc, cr6, cr11, {1} @ │ │ + mcr2 13, 0, r6, cr4, cr12, {4} │ │ vfmal.f16 , d5, d0[3] │ │ cdp2 15, 0, cr0, cr3, cr14, {5} │ │ mcr2 12, 0, r6, cr6, cr3, {4} │ │ mcr2 6, 0, r2, cr6, cr15, {5} │ │ mcr2 10, 0, r8, cr7, cr6, {4} @ │ │ - cdp2 0, 0, cr13, cr6, cr12, {0} │ │ + mcr2 0, 0, sp, cr6, cr9, {1} │ │ cdp2 6, 0, cr2, cr5, cr1, {5} │ │ cdp2 0, 0, cr3, cr7, cr8, {4} │ │ - cdp2 6, 0, cr10, cr6, cr5, {3} │ │ + mcr2 6, 0, sl, cr6, cr2, {4} │ │ mcr2 7, 0, fp, cr5, cr4, {0} │ │ - mcr2 13, 0, r6, cr3, cr3, {0} │ │ - mcr2 12, 0, r6, cr5, cr6, {6} │ │ + vdot.bf16 q3, , d0[0] │ │ + vdot.bf16 d6, d5, d3[0] │ │ mcr2 3, 0, lr, cr5, cr9, {7} │ │ - mcr2 12, 0, r6, cr6, cr0, {7} │ │ + mcr2 13, 0, r6, cr6, cr13, {0} │ │ @ instruction: 0xfe056bcf │ │ vfmal.f16 q4, d22, d6[3] │ │ mcr2 3, 0, lr, cr6, cr9, {6} │ │ vseleq.f16 s8, s13, s15 │ │ movs r0, #9 │ │ strd sl, r0, [sp, #112] @ 0x70 │ │ movs r0, #0 │ │ @@ -517037,20 +517037,20 @@ │ │ pop {r1, r4, r5, r6, r7, pc} │ │ lsls r5, r2, #1 │ │ ldr r5, [pc, #264] @ (21dbfac ) │ │ cdp2 2, 0, cr13, cr6, cr7, {4} │ │ vfmal.f16 d11, s7, s13[0] │ │ lsls r5, r2, #1 │ │ cmp r6, #44 @ 0x2c │ │ - cdp2 0, 0, cr1, cr6, cr11, {1} │ │ - mcr2 4, 0, r9, cr4, cr2, {2} │ │ - mcr2 11, 0, r6, cr4, cr5, {1} @ │ │ + mcr2 0, 0, r1, cr6, cr8, {2} │ │ + mcr2 4, 0, r9, cr4, cr15, {3} │ │ + @ instruction: 0xfe046b62 │ │ @ instruction: 0xfe05c9c0 │ │ - mcr2 10, 0, r6, cr6, cr10, {3} @ │ │ - vseleq.f32 s12, s11, s10 │ │ + vseleq.f32 s12, s13, s15 │ │ + mcr2 10, 0, r6, cr5, cr2, {5} @ │ │ mcr2 11, 0, r4, cr5, cr8, {1} @ │ │ Address 0x21dbeca is out of bounds. │ │ │ │ │ │ 021dbecc : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -517124,16 +517124,16 @@ │ │ movs r2, #15 │ │ strd r6, r0, [sp, #8] │ │ mov r0, r4 │ │ bl 221a63c │ │ b.n 21dbf94 │ │ nop │ │ add r1, pc, #152 @ (adr r1, 21dc024 ) │ │ - cdp2 14, 0, cr4, cr6, cr13, {7} │ │ - cdp2 14, 0, cr10, cr4, cr8, {0} │ │ + mcr2 15, 0, r4, cr6, cr10, {0} │ │ + mcr2 14, 0, sl, cr4, cr5, {1} │ │ vfmal.f16 d15, s9, s10[1] │ │ lsls r0, r2, #1 │ │ ldrd r2, r1, [sp, #84] @ 0x54 │ │ ands.w r3, r0, #1 │ │ itt eq │ │ addeq r1, r4, #1 │ │ lsreq r2, r0, #1 │ │ @@ -517158,16 +517158,16 @@ │ │ strd r6, r0, [sp, #8] │ │ strd r2, r0, [sp] │ │ mov r0, r4 │ │ movs r2, #15 │ │ bl 221a63c │ │ b.n 21dbff0 │ │ nop │ │ - ldr r6, [pc, #556] @ (21dc218 ) │ │ - vdot.bf16 d4, d20, d3[0] │ │ + ldr r6, [pc, #736] @ (21dc2cc ) │ │ + mcr2 13, 0, r4, cr4, cr0, {5} │ │ vfmal.f16 d15, s9, s10[1] │ │ lsls r0, r2, #1 │ │ ldrd r2, r1, [sp, #84] @ 0x54 │ │ ands.w r3, r0, #1 │ │ itt eq │ │ addeq r1, r4, #1 │ │ lsreq r2, r0, #1 │ │ @@ -517564,27 +517564,27 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #128] @ 0x80 │ │ blxne 26ffb40 │ │ b.n 21dc430 │ │ nop │ │ lsrs r2, r0 │ │ - mcr2 6, 0, r6, cr6, cr9, {2} │ │ + cdp2 6, 0, cr6, cr6, cr6, {4} │ │ cdp2 3, 0, cr8, cr5, cr13, {4} │ │ vfmal.f16 d15, s13, s10[1] │ │ lsls r0, r2, #1 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #88] @ 0x58 │ │ blxne 26ffb40 │ │ b.n 21dc458 │ │ - lsrs r7, r5, #25 │ │ + lsrs r4, r3, #26 │ │ cdp2 3, 0, cr8, cr5, cr11, {1} │ │ vseleq.f16 s4, s12, s26 │ │ - mcr2 5, 0, r6, cr6, cr6, {4} │ │ + cdp2 5, 0, cr6, cr6, cr3, {6} │ │ cdp2 2, 0, cr8, cr5, cr15, {6} │ │ cdp2 4, 0, cr5, cr6, cr10, {4} │ │ vfmal.f16 d15, s15, s10[1] │ │ lsls r0, r0, #1 │ │ lsls r0, r0, #31 │ │ beq.n 21dc4e8 │ │ ldr r0, [sp, #72] @ 0x48 │ │ @@ -517652,30 +517652,30 @@ │ │ nop │ │ @ instruction: 0xb74e │ │ lsls r5, r2, #1 │ │ str r7, [sp, #304] @ 0x130 │ │ lsls r4, r2, #1 │ │ str r7, [sp, #248] @ 0xf8 │ │ lsls r4, r2, #1 │ │ - cmp r0, #28 │ │ + cmp r0, #73 @ 0x49 │ │ mcr2 12, 0, sp, cr5, cr8, {3} │ │ - mcr2 4, 0, r6, cr6, cr8, {5} │ │ + cdp2 4, 0, cr6, cr6, cr5, {7} │ │ mcr2 6, 0, r4, cr5, cr12, {3} │ │ - mcr2 7, 0, ip, cr6, cr12, {0} │ │ + cdp2 7, 0, cr12, cr6, cr9, {2} │ │ cdp2 15, 0, cr12, cr5, cr8, {5} │ │ - mcr2 11, 0, r4, cr3, cr13, {7} @ │ │ - cdp2 3, 0, cr10, cr4, cr11, {0} │ │ + cdp2 12, 0, cr4, cr3, cr10, {1} │ │ + mcr2 3, 0, sl, cr4, cr8, {1} │ │ mcr2 1, 0, r8, cr5, cr8, {0} │ │ mcr2 7, 0, r2, cr6, cr4, {6} │ │ - mcr2 13, 0, r8, cr6, cr12, {4} │ │ - @ instruction: 0xfe04aa45 │ │ + vdot.bf16 q4, q11, d9[0] │ │ + mcr2 10, 0, sl, cr4, cr2, {3} @ │ │ cdp2 12, 0, cr12, cr4, cr5, {2} │ │ mcr2 7, 0, fp, cr3, cr0, {7} │ │ lsls r5, r2, #1 │ │ - stmia r5!, {r0, r1, r5, r6, r7} │ │ + stmia r6!, {r4} │ │ mcr2 2, 0, fp, cr5, cr2, {1} │ │ lsls r5, r2, #1 │ │ │ │ 021dc548 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -517937,28 +517937,28 @@ │ │ mov.w r9, #0 │ │ mov.w sl, #0 │ │ ldr r0, [r0, #12] │ │ b.n 21dc85a │ │ strb r6, [r2, r2] │ │ mcr2 3, 0, r9, cr7, cr2, {0} │ │ lsls r4, r2, #1 │ │ - str r7, [r0, #16] │ │ - vcmla.f16 d4, d21, d7[1], #0 │ │ + str r4, [r6, #16] │ │ + vfmal.f16 q2, d21, d4[0] │ │ cdp2 15, 0, cr11, cr4, cr4, {1} │ │ - vcmla.f16 d4, d6, d3[1], #0 │ │ - mcr2 7, 0, r4, cr4, cr9, {1} │ │ + vfmal.f16 q2, d6, d0[0] │ │ + cdp2 7, 0, cr4, cr4, cr6, {3} │ │ vdot.bf16 , q2, d7[1] │ │ mcr2 10, 0, r3, cr6, cr12, {4} @ │ │ - mcr2 15, 0, r5, cr6, cr12, {6} │ │ + cdp2 0, 0, cr6, cr6, cr9, {0} │ │ vdot.bf16 d7, d5, d11[0] │ │ cdp2 14, 0, cr4, cr6, cr6, {6} │ │ - mcr2 7, 0, sl, cr7, cr6, {0} │ │ - cdp2 7, 0, cr4, cr4, cr3, {1} │ │ + cdp2 7, 0, cr10, cr7, cr3, {2} │ │ + mcr2 7, 0, r4, cr4, cr0, {2} │ │ cdp2 1, 0, cr4, cr4, cr6, {2} │ │ - cdp2 7, 0, cr0, cr6, cr3, {5} │ │ + mcr2 7, 0, r0, cr6, cr0, {6} │ │ vfmal.f16 , d21, d6[3] │ │ cdp2 12, 0, cr7, cr6, cr13, {2} │ │ cdp2 2, 0, cr2, cr6, cr15, {1} │ │ cdp2 1, 0, cr15, cr6, cr10, {0} │ │ lsrs r1, r0, #8 │ │ cmp sl, r1 │ │ bcs.w 21dcb24 │ │ @@ -518200,26 +518200,26 @@ │ │ and.w r1, r1, #3 │ │ cmp r8, r1 │ │ bcc.w 21dc86c │ │ ldr r1, [sp, #32] │ │ ldrh r1, [r1, #0] │ │ b.n 21dc850 │ │ nop │ │ - movs r4, #242 @ 0xf2 │ │ + movs r5, #31 │ │ mcr2 0, 0, r8, cr4, cr15, {0} │ │ - cdp2 5, 0, cr4, cr3, cr7, {5} │ │ - mcr2 4, 0, r2, cr4, cr8, {2} │ │ - mcr2 11, 0, r9, cr4, cr9, {7} @ │ │ - cdp2 5, 0, cr4, cr5, cr13, {0} │ │ - mcr2 3, 0, r2, cr4, cr14, {5} │ │ + mcr2 5, 0, r4, cr3, cr4, {6} │ │ + cdp2 4, 0, cr2, cr4, cr5, {4} │ │ + cdp2 12, 0, cr9, cr4, cr6, {1} │ │ + mcr2 5, 0, r4, cr5, cr10, {1} │ │ + cdp2 3, 0, cr2, cr4, cr11, {7} │ │ cdp2 6, 0, cr10, cr4, cr7, {0} │ │ - mcr2 4, 0, r4, cr3, cr3, {3} │ │ - cdp2 3, 0, cr2, cr4, cr4, {1} │ │ - mcr2 6, 0, r8, cr4, cr4, {2} │ │ - mcr2 3, 0, r4, cr4, cr9, {6} │ │ + cdp2 4, 0, cr4, cr3, cr0, {5} │ │ + mcr2 3, 0, r2, cr4, cr1, {2} │ │ + cdp2 6, 0, cr8, cr4, cr1, {4} │ │ + cdp2 4, 0, cr4, cr4, cr6, {0} │ │ vseleq.f16 s8, s9, s25 │ │ add r1, pc │ │ add r0, sp, #76 @ 0x4c │ │ blx 2701ed0 │ │ add r5, sp, #104 @ 0x68 │ │ ldr r1, [pc, #680] @ (21dcddc ) │ │ add r1, pc │ │ @@ -518476,34 +518476,34 @@ │ │ add.w r8, sp, #48 @ 0x30 │ │ add.w fp, sp, #76 @ 0x4c │ │ add r4, pc │ │ mov.w r9, #0 │ │ mov.w sl, #0 │ │ movs r6, #0 │ │ b.n 21dce66 │ │ - subs r0, r7, #1 │ │ + subs r5, r4, #2 │ │ vdot.bf16 , , d3[1] │ │ mcr2 2, 0, sp, cr3, cr4, {0} │ │ cdp2 14, 0, cr5, cr6, cr11, {4} │ │ - mcr2 4, 0, r9, cr3, cr9, {6} │ │ + cdp2 5, 0, cr9, cr3, cr6, {0} │ │ mcr2 4, 0, lr, cr5, cr8, {0} │ │ mcr2 3, 0, lr, cr3, cr10, {7} │ │ - cdp2 5, 0, cr8, cr3, cr12, {5} │ │ + mcr2 5, 0, r8, cr3, cr9, {6} │ │ mcr2 4, 0, r1, cr4, cr3, {5} │ │ - mcr2 15, 0, r3, cr7, cr13, {7} │ │ + cdp2 0, 0, cr4, cr7, cr10, {1} │ │ mcr2 13, 0, r5, cr5, cr9, {5} │ │ - cdp2 2, 0, cr0, cr3, cr1, {6} │ │ + cdp2 2, 0, cr0, cr3, cr14, {7} │ │ vdot.bf16 , , d7[1] │ │ - cdp2 1, 0, cr12, cr3, cr6, {2} │ │ + mcr2 1, 0, ip, cr3, cr3, {3} │ │ mcr2 13, 0, r5, cr4, cr5, {0} │ │ vdot.bf16 d1, d3, d14[0] │ │ cdp2 12, 0, cr5, cr6, cr3, {6} │ │ - cdp2 0, 0, cr4, cr3, cr11, {5} │ │ + mcr2 0, 0, r4, cr3, cr8, {6} │ │ mcr2 12, 0, r5, cr4, cr1, {3} │ │ - mcr2 15, 0, sp, cr3, cr11, {4} │ │ + cdp2 15, 0, cr13, cr3, cr8, {6} │ │ mcr2 5, 0, r7, cr4, cr10, {5} │ │ vfmal.f16 d15, s13, s10[1] │ │ lsls r0, r0, #1 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #72] @ 0x48 │ │ blxne 26ffb40 │ │ @@ -518885,16 +518885,16 @@ │ │ nop │ │ subs r4, r2, r7 │ │ mcr2 14, 0, ip, cr6, cr10, {7} │ │ mcr2 5, 0, r7, cr6, cr2, {1} │ │ mcr2 11, 0, r1, cr6, cr2, {1} @ │ │ cdp2 0, 0, cr1, cr6, cr5, {6} │ │ cdp2 0, 0, cr12, cr7, cr13, {6} │ │ - mcr2 13, 0, sp, cr3, cr13, {2} │ │ - cdp2 14, 0, cr3, cr4, cr5, {0} │ │ + vdot.bf16 d13, d19, d10[0] │ │ + mcr2 14, 0, r3, cr4, cr2, {1} │ │ cdp2 0, 0, cr14, cr4, cr12, {0} │ │ b.n 21dd322 │ │ b.n 21dd278 │ │ b.n 21dd322 │ │ b.n 21dd278 │ │ b.n 21dd322 │ │ b.n 21dd278 │ │ @@ -518984,26 +518984,26 @@ │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ b.n 21dd322 │ │ b.n 21dd314 │ │ sub sp, #336 @ 0x150 │ │ lsls r5, r2, #1 │ │ stmia r1!, {r1, r3, r4, r5, r6, r7} │ │ - mcr2 14, 0, r3, cr3, cr3, {2} │ │ + cdp2 14, 0, cr3, cr3, cr0, {4} │ │ cdp2 15, 0, cr8, cr4, cr13, {7} │ │ vseleq.f16 s2, s13, s1 │ │ mcr2 9, 0, r1, cr6, cr8, {4} @ │ │ mcr2 2, 0, r5, cr6, cr15, {3} │ │ mcr2 12, 0, ip, cr6, cr3, {6} │ │ cdp2 7, 0, cr3, cr6, cr4, {3} │ │ vfmal.f16 d1, s12, s7[1] │ │ mcr2 14, 0, fp, cr6, cr7, {1} │ │ @ instruction: 0xfe03a9e2 │ │ lsls r5, r2, #1 │ │ - ldr r4, [sp, #536] @ 0x218 │ │ + ldr r4, [sp, #716] @ 0x2cc │ │ cdp2 4, 0, cr10, cr4, cr4, {1} │ │ lsls r5, r2, #1 │ │ adds r2, r3, r4 │ │ cdp2 2, 0, cr5, cr6, cr1, {0} │ │ mcr2 4, 0, r5, cr6, cr11, {4} │ │ cdp2 6, 0, cr3, cr6, cr6, {7} │ │ mcr2 5, 0, fp, cr6, cr0, {7} │ │ @@ -519338,31 +519338,31 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne.w r0, [r8, #8] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ strb r1, [r0, #20] │ │ - @ instruction: 0xfe0319cc │ │ + mcr2 9, 0, r1, cr3, cr9, {7} @ │ │ mcr2 2, 0, sl, cr4, cr2, {4} │ │ lsls r5, r2, #1 │ │ asrs r7, r7, #25 │ │ - @ instruction: 0xfe06fb4e │ │ - vseleq.f16 s2, s8, s24 │ │ - cdp2 0, 0, cr9, cr4, cr15, {5} │ │ + mcr2 11, 0, pc, cr6, cr11, {3} @ │ │ + mcr2 9, 0, r1, cr4, cr9, {1} @ │ │ + mcr2 0, 0, r9, cr4, cr12, {6} │ │ mcr2 12, 0, r8, cr5, cr3, {1} │ │ - vseleq.f32 s30, s13, s5 │ │ - vcmla.f16 , q2, d6[1], #0 │ │ + @ instruction: 0xfe06facf │ │ + vfmal.f16 d1, s9, s6[0] │ │ mcr2 10, 0, r9, cr4, cr1, {5} @ │ │ - mcr2 10, 0, pc, cr3, cr10, {0} @ │ │ + @ instruction: 0xfe03fa47 │ │ vseleq.f64 d8, d20, d20 │ │ - mcr2 11, 0, r7, cr6, cr10, {1} @ │ │ - vcmla.f16 d1, d4, d14[0], #0 │ │ - mcr2 10, 0, r7, cr4, cr0, {7} @ │ │ - vcmla.f16 d9, d4, d7[1], #0 │ │ + @ instruction: 0xfe067b67 │ │ + vfmal.f16 d1, s8, s7[1] │ │ + mcr2 11, 0, r7, cr4, cr13, {0} @ │ │ + vfmal.f16 , d4, d4[0] │ │ cdp2 15, 0, cr9, cr4, cr8, {7} │ │ lsls r5, r2, #1 │ │ │ │ 021dd754 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -519637,45 +519637,45 @@ │ │ itt ne │ │ ldrne r0, [sp, #36] @ 0x24 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ ldr r6, [sp, #800] @ 0x320 │ │ lsls r5, r2, #1 │ │ cmp r6, r1 │ │ - cdp2 2, 0, cr1, cr7, cr7, {7} │ │ + mcr2 3, 0, r1, cr7, cr4, {0} │ │ cdp2 0, 0, cr8, cr5, cr0, {7} │ │ lsls r4, r2, #1 │ │ strh r2, [r3, #6] │ │ lsls r4, r2, #1 │ │ strh r4, [r2, #6] │ │ lsls r4, r2, #1 │ │ strh r6, [r0, #6] │ │ lsls r4, r2, #1 │ │ - ldr r6, [pc, #572] @ (21ddc7c ) │ │ - cdp2 6, 0, cr3, cr5, cr15, {1} │ │ - cdp2 5, 0, cr3, cr4, cr5, {2} │ │ + ldr r6, [pc, #752] @ (21ddd30 ) │ │ + mcr2 6, 0, r3, cr5, cr12, {2} │ │ + mcr2 5, 0, r3, cr4, cr2, {3} │ │ mcr2 11, 0, r6, cr4, cr3, {3} @ │ │ vcmla.f16 d2, d22, d8[1], #0 │ │ vseleq.f64 d6, d6, d19 │ │ mcr2 4, 0, r6, cr6, cr9, {5} │ │ mcr2 15, 0, r7, cr6, cr14, {4} │ │ lsls r4, r2, #1 │ │ ldrb r4, [r2, #30] │ │ lsls r4, r2, #1 │ │ - asrs r0, r6, #1 │ │ - cdp2 4, 0, cr9, cr5, cr3, {6} │ │ + asrs r5, r3, #2 │ │ + mcr2 4, 0, r9, cr5, cr0, {7} │ │ mcr2 0, 0, r1, cr4, cr5, {6} │ │ cdp2 15, 0, cr7, cr6, cr2, {3} │ │ lsls r4, r2, #1 │ │ ldrb r6, [r4, #29] │ │ lsls r4, r2, #1 │ │ @ instruction: 0xb67b │ │ cdp2 2, 0, cr10, cr3, cr6, {1} │ │ lsls r5, r2, #1 │ │ - add sp, #100 @ 0x64 │ │ + add sp, #280 @ 0x118 │ │ cdp2 12, 0, cr9, cr5, cr8, {3} │ │ lsls r5, r2, #1 │ │ │ │ 021dda84 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -519746,17 +519746,17 @@ │ │ add r4, sp, #40 @ 0x28 │ │ strd r2, r0, [sp] │ │ movs r2, #15 │ │ mov r0, r4 │ │ bl 221a63c │ │ b.n 21ddb50 │ │ nop │ │ - ldr r3, [pc, #580] @ (21ddd8c ) │ │ - mcr2 3, 0, r3, cr5, cr1, {1} │ │ - cdp2 2, 0, cr3, cr4, cr5, {2} │ │ + ldr r3, [pc, #760] @ (21dde40 ) │ │ + mcr2 3, 0, r3, cr5, cr14, {2} │ │ + mcr2 2, 0, r3, cr4, cr2, {3} │ │ vfmal.f16 d15, s9, s10[1] │ │ movs r0, r5 │ │ ldrd r2, r1, [sp, #44] @ 0x2c │ │ ands.w r3, r0, #1 │ │ itt eq │ │ addeq r1, r4, #1 │ │ lsreq r2, r0, #1 │ │ @@ -520235,19 +520235,19 @@ │ │ blx 26ffb40 │ │ b.n 21de0ec │ │ b.n 21de0ec │ │ b.n 21de0fa │ │ nop │ │ ldr r1, [pc, #924] @ (21de3f4 ) │ │ mcr2 13, 0, r4, cr6, cr11, {2} │ │ - cdp2 12, 0, cr0, cr3, cr12, {4} │ │ + mcr2 12, 0, r0, cr3, cr9, {5} │ │ mcr2 2, 0, r0, cr5, cr12, {2} │ │ - cdp2 0, 0, cr3, cr7, cr9, {2} │ │ - mcr2 0, 0, r3, cr4, cr12, {2} │ │ - mcr2 15, 0, sl, cr4, cr9, {5} │ │ + mcr2 0, 0, r3, cr7, cr6, {3} │ │ + cdp2 0, 0, cr3, cr4, cr9, {4} │ │ + cdp2 15, 0, cr10, cr4, cr6, {7} │ │ mcr2 3, 0, r8, cr4, cr8, {1} │ │ cdp2 12, 0, cr4, cr6, cr9, {4} │ │ mcr2 10, 0, r2, cr3, cr7, {7} @ │ │ cdp2 0, 0, cr14, cr6, cr4, {2} │ │ b.n 21de0da │ │ ldrb.w r0, [sp, #40] @ 0x28 │ │ lsls r0, r0, #31 │ │ @@ -520312,31 +520312,31 @@ │ │ ldrne r0, [sp, #60] @ 0x3c │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ ldr r3, [sp, #608] @ 0x260 │ │ lsls r5, r2, #1 │ │ ldr r4, [pc, #220] @ (21de200 ) │ │ - cdp2 15, 0, cr10, cr3, cr11, {6} │ │ + mcr2 15, 0, sl, cr3, cr8, {7} │ │ mcr2 7, 0, r4, cr4, cr12, {6} │ │ mcr2 13, 0, ip, cr6, cr8, {0} │ │ cdp2 12, 0, cr0, cr5, cr0, {0} │ │ cdp2 5, 0, cr6, cr6, cr0, {2} │ │ - mcr2 14, 0, r0, cr6, cr2, {4} │ │ - mcr2 2, 0, r7, cr4, cr14, {0} │ │ - vseleq.f16 s8, s8, s2 │ │ + mcr2 14, 0, r0, cr6, cr15, {5} │ │ + cdp2 2, 0, cr7, cr4, cr11, {2} │ │ + vseleq.f16 s8, s8, s29 │ │ cdp2 7, 0, cr10, cr5, cr12, {4} │ │ cdp2 7, 0, cr4, cr6, cr15, {1} │ │ mcr2 12, 0, ip, cr6, cr15, {0} │ │ vcmla.f16 q1, , d12[1], #0 │ │ - mcr2 13, 0, r0, cr6, cr1, {2} │ │ + mcr2 13, 0, r0, cr6, cr14, {3} │ │ mcr2 0, 0, fp, cr4, cr9, {0} │ │ @ instruction: 0xfe039bc4 │ │ lsls r5, r2, #1 │ │ - ldrh r0, [r5, #50] @ 0x32 │ │ + ldrh r5, [r2, #52] @ 0x34 │ │ cdp2 6, 0, cr9, cr4, cr6, {0} │ │ lsls r5, r2, #1 │ │ │ │ 021de168 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -520662,30 +520662,30 @@ │ │ strb r6, [r1, #27] │ │ lsls r4, r2, #1 │ │ strb r0, [r1, #27] │ │ lsls r4, r2, #1 │ │ strb r4, [r7, #26] │ │ lsls r4, r2, #1 │ │ ldrb r6, [r1, #26] │ │ - mcr2 12, 0, r2, cr6, cr5, {2} │ │ + cdp2 12, 0, cr2, cr6, cr2, {4} │ │ vseleq.f64 d10, d20, d3 │ │ - mcr2 4, 0, r4, cr3, cr13, {2} │ │ - mcr2 11, 0, r2, cr5, cr13, {7} @ │ │ + cdp2 4, 0, cr4, cr3, cr10, {4} │ │ + cdp2 12, 0, cr2, cr5, cr10, {1} │ │ mcr2 11, 0, fp, cr4, cr1, {3} @ │ │ - cdp2 12, 0, cr14, cr6, cr11, {2} │ │ + mcr2 12, 0, lr, cr6, cr8, {3} │ │ cdp2 1, 0, cr6, cr4, cr7, {0} │ │ vseleq.f32 s6, s13, s21 │ │ - mcr2 3, 0, r4, cr7, cr10, {3} │ │ + cdp2 3, 0, cr4, cr7, cr7, {5} │ │ mcr2 0, 0, r6, cr5, cr3, {5} │ │ vdot.bf16 d7, d6, d9[0] │ │ cdp2 5, 0, cr7, cr6, cr14, {1} │ │ lsls r4, r2, #1 │ │ strb r4, [r4, #20] │ │ lsls r4, r2, #1 │ │ - lsls r2, r0, #24 │ │ + lsls r7, r5, #24 │ │ mcr2 0, 0, r2, cr5, cr0, {0} │ │ blx 26ffbf0 │ │ ldr r1, [pc, #592] @ (21de75c ) │ │ movs r2, #12 │ │ movs r3, #17 │ │ str r2, [sp, #36] @ 0x24 │ │ add r1, pc │ │ @@ -520913,37 +520913,37 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #68] @ 0x44 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ str r4, [sp, #712] @ 0x2c8 │ │ lsls r5, r2, #1 │ │ - @ instruction: 0xea70fe04 │ │ + @ instruction: 0xea9dfe04 │ │ adds r4, #34 @ 0x22 │ │ mcr2 12, 0, r8, cr7, cr2, {1} │ │ mcr2 10, 0, fp, cr3, cr2, {2} @ │ │ - vseleq.f32 s16, s12, s13 │ │ + mcr2 10, 0, r8, cr6, cr3, {2} @ │ │ mcr2 4, 0, r2, cr4, cr6, {1} │ │ cdp2 14, 0, cr3, cr6, cr1, {5} │ │ mcr2 5, 0, r0, cr6, cr2, {5} │ │ - vseleq.f16 s28, s13, s25 │ │ + mcr2 9, 0, lr, cr6, cr9, {6} @ │ │ mcr2 3, 0, r4, cr4, cr9, {3} │ │ - vfmal.f16 q1, d3, d4[3] │ │ + vcmla.f16 d2, d19, d9[1], #0 │ │ vseleq.f32 s30, s8, s25 │ │ mcr2 2, 0, r7, cr6, cr0, {4} │ │ lsls r4, r2, #1 │ │ strb r4, [r2, #10] │ │ lsls r4, r2, #1 │ │ add r1, sp, #676 @ 0x2a4 │ │ mcr2 5, 0, r9, cr3, cr4, {2} │ │ lsls r5, r2, #1 │ │ - add r3, pc, #284 @ (adr r3, 21de8b8 ) │ │ + add r3, pc, #464 @ (adr r3, 21de96c ) │ │ mcr2 15, 0, r8, cr5, cr6, {4} │ │ lsls r5, r2, #1 │ │ - add r0, sp, #160 @ 0xa0 │ │ + add r0, sp, #340 @ 0x154 │ │ mcr2 3, 0, r4, cr4, cr14, {7} │ │ Address 0x21de7a6 is out of bounds. │ │ │ │ │ │ 021de7a8 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -521326,41 +521326,41 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #52] @ 0x34 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ ldrh r4, [r6, #50] @ 0x32 │ │ lsls r5, r2, #1 │ │ - strh r4, [r6, #48] @ 0x30 │ │ - cdp2 6, 0, cr2, cr4, cr1, {2} │ │ + strh r1, [r4, #50] @ 0x32 │ │ + cdp2 6, 0, cr2, cr4, cr14, {3} │ │ cdp2 0, 0, cr2, cr4, cr4, {3} │ │ vfmal.f16 d7, s12, s8[1] │ │ mcr2 11, 0, r5, cr6, cr7, {3} @ │ │ - cdp2 1, 0, cr0, cr6, cr13, {5} │ │ - cdp2 6, 0, cr14, cr5, cr5, {3} │ │ + mcr2 1, 0, r0, cr6, cr10, {6} │ │ + mcr2 6, 0, lr, cr5, cr2, {4} │ │ vseleq.f64 d5, d4, d17 │ │ cdp2 4, 0, cr3, cr6, cr4, {6} │ │ - mcr2 13, 0, r3, cr7, cr2, {4} │ │ + mcr2 13, 0, r3, cr7, cr15, {5} │ │ @ instruction: 0xfe055acb │ │ cdp2 7, 0, cr7, cr6, cr1, {1} │ │ - mcr2 0, 0, r0, cr6, cr12, {1} │ │ - mcr2 1, 0, r4, cr5, cr12, {4} │ │ + cdp2 0, 0, cr0, cr6, cr9, {3} │ │ + cdp2 1, 0, cr4, cr5, cr9, {6} │ │ cdp2 14, 0, cr13, cr4, cr15, {2} │ │ - mcr2 6, 0, r7, cr5, cr11, {3} │ │ - cdp2 12, 0, cr3, cr5, cr14, {4} │ │ + cdp2 6, 0, cr7, cr5, cr8, {5} │ │ + mcr2 12, 0, r3, cr5, cr11, {5} │ │ cdp2 1, 0, cr12, cr5, cr4, {5} │ │ cdp2 5, 0, cr10, cr5, cr1, {2} │ │ cdp2 0, 0, cr9, cr3, cr12, {7} │ │ lsls r5, r2, #1 │ │ - strh r0, [r2, #28] │ │ + strh r5, [r7, #28] │ │ vseleq.f64 d8, d4, d16 │ │ lsls r5, r2, #1 │ │ - movs r7, r7 │ │ - mcr2 12, 0, r3, cr5, cr6, {6} │ │ - mcr2 4, 0, r2, cr5, cr2, {0} │ │ + lsls r4, r5, #1 │ │ + vdot.bf16 d3, d5, d3[0] │ │ + mcr2 4, 0, r2, cr5, cr15, {1} │ │ Address 0x21debfe is out of bounds. │ │ │ │ │ │ 021dec00 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -521836,43 +521836,43 @@ │ │ blx 2700e60 │ │ b.n 21df0e6 │ │ add r0, sp, #40 @ 0x28 │ │ blx 2703800 │ │ blx 26ffb60 │ │ ldrh r4, [r0, #16] │ │ lsls r5, r2, #1 │ │ - subs r1, #63 @ 0x3f │ │ - mcr2 0, 0, r2, cr5, cr15, {6} │ │ - mcr2 15, 0, r1, cr4, cr5, {7} │ │ - cdp2 1, 0, cr14, cr4, cr11, {1} │ │ + subs r1, #108 @ 0x6c │ │ + cdp2 1, 0, cr2, cr5, cr12, {0} │ │ + cdp2 0, 0, cr2, cr4, cr2, {1} │ │ + mcr2 1, 0, lr, cr4, cr8, {2} │ │ cdp2 5, 0, cr5, cr4, cr7, {7} │ │ cdp2 15, 0, cr2, cr6, cr10, {4} │ │ mcr2 5, 0, r5, cr7, cr1, {4} │ │ cdp2 2, 0, cr1, cr6, cr6, {6} │ │ vseleq.f32 s12, s12, s28 │ │ lsls r4, r2, #1 │ │ ldr r4, [r0, #32] │ │ lsls r4, r2, #1 │ │ - ssub16 lr, lr, r4 │ │ + mul.w lr, fp, r4 │ │ bcs.n 21df0e0 │ │ mcr2 14, 0, sl, cr6, cr8, {7} │ │ mcr2 9, 0, r3, cr6, cr5, {7} @ │ │ - mcr2 14, 0, r1, cr3, cr8, {7} │ │ + cdp2 15, 0, cr1, cr3, cr5, {1} │ │ cdp2 0, 0, cr15, cr4, cr8, {5} │ │ vseleq.f16 s12, s12, s20 │ │ lsls r4, r2, #1 │ │ ldr r6, [r1, #16] │ │ lsls r4, r2, #1 │ │ add r0, pc, #140 @ (adr r0, 21df1cc ) │ │ @ instruction: 0xfe038bc2 │ │ lsls r5, r2, #1 │ │ - ldr r1, [sp, #724] @ 0x2d4 │ │ + ldr r1, [sp, #904] @ 0x388 │ │ mcr2 5, 0, r8, cr5, cr6, {5} │ │ lsls r5, r2, #1 │ │ - ldr r6, [sp, #840] @ 0x348 │ │ + ldr r6, [sp, #1020] @ 0x3fc │ │ vseleq.f32 s6, s9, s17 │ │ Address 0x21df152 is out of bounds. │ │ │ │ │ │ 021df154 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -522100,23 +522100,23 @@ │ │ lsls r5, r2, #1 │ │ strh r6, [r3, #44] @ 0x2c │ │ lsls r5, r2, #1 │ │ cmp r0, #50 @ 0x32 │ │ mcr2 5, 0, r8, cr7, cr10, {1} │ │ lsls r5, r2, #1 │ │ ldr r6, [sp, #208] @ 0xd0 │ │ - mcr2 12, 0, r7, cr3, cr4, {1} │ │ - cdp2 12, 0, cr1, cr4, cr1, {2} │ │ + cdp2 12, 0, cr7, cr3, cr1, {3} │ │ + cdp2 12, 0, cr1, cr4, cr14, {3} │ │ cdp2 6, 0, cr1, cr4, cr4, {3} │ │ cdp2 14, 0, cr6, cr6, cr2, {1} │ │ mcr2 1, 0, r5, cr6, cr3, {3} │ │ - cdp2 7, 0, cr15, cr6, cr9, {5} │ │ - mcr2 12, 0, sp, cr4, cr11, {2} │ │ - mcr2 3, 0, r3, cr4, cr3, {6} │ │ - mcr2 11, 0, r1, cr5, cr3, {3} @ │ │ + mcr2 7, 0, pc, cr6, cr6, {6} @ │ │ + cdp2 12, 0, cr13, cr4, cr8, {4} │ │ + cdp2 4, 0, cr3, cr4, cr0, {0} │ │ + vseleq.f64 d1, d21, d16 │ │ mcr2 1, 0, r9, cr4, cr0, {7} │ │ cdp2 0, 0, cr5, cr6, cr11, {5} │ │ vdot.bf16 q0, q11, d0[1] │ │ cdp2 1, 0, cr15, cr6, cr8, {0} │ │ lsrs r1, r0, #32 │ │ cmp r8, r1 │ │ bcs.w 21df68a │ │ @@ -522494,19 +522494,19 @@ │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ b.n 21df80c │ │ b.n 21df870 │ │ b.n 21df80c │ │ b.n 21df870 │ │ - ldr??t pc, [sl, #3] │ │ + vst3. {d15[0],d16[0],d17[0]}, [r7], r3 │ │ strb r7, [r0, r2] │ │ - vseleq.f32 s2, s6, s30 │ │ - vcmla.f16 , q10, d0[0], #0 │ │ - cdp2 0, 0, cr7, cr3, cr1, {3} │ │ + mcr2 10, 0, r1, cr3, cr12, {1} @ │ │ + vcmla.f16 , q10, d13[1], #0 │ │ + cdp2 0, 0, cr7, cr3, cr14, {4} │ │ cdp2 0, 0, cr14, cr5, cr4, {0} │ │ b.n 21df870 │ │ b.n 21df80c │ │ b.n 21df870 │ │ b.n 21df830 │ │ b.n 21df870 │ │ ldrb.w r0, [sp, #68] @ 0x44 │ │ @@ -522551,30 +522551,30 @@ │ │ blx 26ffb40 │ │ add r0, sp, #80 @ 0x50 │ │ blx 2703800 │ │ blx 26ffb60 │ │ nop │ │ strh r2, [r6, #36] @ 0x24 │ │ lsls r5, r2, #1 │ │ - adds r5, r6, r5 │ │ - vcmla.f16 d15, d4, d6[1], #0 │ │ + adds r2, r4, r6 │ │ + vfmal.f16 , d4, d3[0] │ │ @ instruction: 0xfe037a6f │ │ - vfmal.f16 , d19, d3[1] │ │ - cdp2 7, 0, cr15, cr4, cr12, {4} │ │ - mcr2 10, 0, r5, cr3, cr12, {5} @ │ │ - vcmla.f16 , q2, d1[0], #0 │ │ + vseleq.f16 s2, s6, s16 │ │ + mcr2 7, 0, pc, cr4, cr9, {5} @ │ │ + @ instruction: 0xfe035ae9 │ │ + vcmla.f16 , q2, d14[1], #0 │ │ vdot.bf16 q2, q2, d15[0] │ │ mcr2 6, 0, r2, cr6, cr2, {7} │ │ - mcr2 2, 0, pc, cr7, cr10, {5} @ │ │ - mcr2 6, 0, fp, cr4, cr15, {2} │ │ - mcr2 6, 0, fp, cr4, cr6, {4} │ │ + cdp2 2, 0, cr15, cr7, cr7, {7} │ │ + cdp2 6, 0, cr11, cr4, cr12, {4} │ │ + cdp2 6, 0, cr11, cr4, cr3, {6} │ │ vfmal.f16 , d20, d1[0] │ │ cdp2 4, 0, cr8, cr3, cr14, {3} │ │ lsls r5, r2, #1 │ │ - strb r2, [r2, #28] │ │ + strb r7, [r7, #28] │ │ cdp2 14, 0, cr7, cr4, cr0, {3} │ │ lsls r5, r2, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #92 @ 0x5c │ │ str r0, [sp, #20] │ │ @@ -522782,33 +522782,33 @@ │ │ cdp2 15, 0, cr5, cr3, cr12, {6} │ │ lsls r4, r2, #1 │ │ str r7, [sp, #256] @ 0x100 │ │ mcr2 15, 0, r5, cr3, cr12, {5} │ │ lsls r4, r2, #1 │ │ movs r1, #26 │ │ mcr2 7, 0, r6, cr7, cr3, {2} │ │ - cdp2 4, 0, cr1, cr6, cr14, {7} │ │ + mcr2 5, 0, r1, cr6, cr11, {0} │ │ vdot.bf16 d7, d4, d12[1] │ │ lsls r5, r2, #1 │ │ lsls r4, r6, #10 │ │ vfmal.f16 d12, s15, s8[0] │ │ - mcr2 13, 0, r0, cr6, cr9, {0} │ │ + vdot.bf16 q0, q3, d6[0] │ │ mcr2 2, 0, r0, cr4, cr10, {4} │ │ cdp2 15, 0, cr7, cr7, cr0, {7} │ │ lsls r5, r2, #1 │ │ stmia r6!, {r0, r3, r4, r6} │ │ mcr2 12, 0, r2, cr6, cr14, {5} │ │ - mcr2 15, 0, r0, cr6, cr2, {3} │ │ + mcr2 15, 0, r0, cr6, cr15, {4} │ │ vcmla.f16 , , d10[0], #0 │ │ - cdp2 1, 0, cr3, cr3, cr6, {4} │ │ - mcr2 1, 0, r1, cr4, cr10, {7} │ │ + mcr2 1, 0, r3, cr3, cr3, {5} │ │ + cdp2 2, 0, cr1, cr4, cr7, {1} │ │ mcr2 13, 0, r4, cr5, cr2, {4} │ │ cdp2 0, 0, cr15, cr3, cr2, {4} │ │ - mcr2 3, 0, pc, cr5, cr2, {2} @ │ │ - mcr2 3, 0, fp, cr3, cr7, {6} │ │ + mcr2 3, 0, pc, cr5, cr15, {3} @ │ │ + cdp2 4, 0, cr11, cr3, cr4, {0} │ │ cdp2 1, 0, cr0, cr4, cr1, {5} │ │ cdp2 2, 0, cr0, cr7, cr9, {0} │ │ cdp2 1, 0, cr8, cr7, cr2, {3} │ │ lsls r5, r2, #1 │ │ lsrs r5, r4, #26 │ │ @ instruction: 0xfe067bc2 │ │ lsls r5, r2, #1 │ │ @@ -522904,16 +522904,16 @@ │ │ mov.w r8, #0 │ │ mov.w r9, #0 │ │ b.n 21dfc34 │ │ nop │ │ push {r1, r2, r4, r5, r6} │ │ mcr2 4, 0, fp, cr3, cr0, {3} │ │ mcr2 15, 0, r9, cr3, cr8, {5} │ │ - cdp2 0, 0, cr1, cr6, cr13, {0} │ │ - mcr2 1, 0, fp, cr5, cr9, {6} │ │ + mcr2 0, 0, r1, cr6, cr10, {1} │ │ + cdp2 2, 0, cr11, cr5, cr6, {0} │ │ vcmla.f16 d9, d4, d4[0], #0 │ │ add.w r9, r9, #1 │ │ mov.w fp, #210 @ 0xd2 │ │ adds r0, #48 @ 0x30 │ │ str r0, [sp, #16] │ │ ldrh.w r0, [r4, #456] @ 0x1c8 │ │ cmp r9, r0 │ │ @@ -523284,29 +523284,29 @@ │ │ b.n 21dfc1c │ │ nop │ │ stc 14, cr15, [r8, #20]! │ │ movs r6, #141 @ 0x8d │ │ mcr2 13, 0, lr, cr6, cr4, {2} │ │ mcr2 9, 0, r0, cr5, cr6, {4} @ │ │ vdot.bf16 d14, d6, d4[0] │ │ - vcmla.f16 d6, d5, d0[1], #0 │ │ + vcmla.f16 q3, , d13[0], #0 │ │ cdp2 12, 0, cr14, cr5, cr14, {5} │ │ mcr2 2, 0, r2, cr5, cr14, {5} │ │ mcr2 12, 0, lr, cr6, cr0, {2} │ │ - cdp2 2, 0, cr6, cr5, cr13, {1} │ │ - @ instruction: 0xfe058a64 │ │ - cdp2 14, 0, cr10, cr4, cr5, {3} │ │ - cdp2 14, 0, cr14, cr4, cr6, {5} │ │ + mcr2 2, 0, r6, cr5, cr10, {2} │ │ + mcr2 10, 0, r8, cr5, cr1, {4} @ │ │ + mcr2 14, 0, sl, cr4, cr2, {4} │ │ + mcr2 14, 0, lr, cr4, cr3, {6} │ │ mcr2 9, 0, r4, cr3, cr3, {6} @ │ │ - cdp2 14, 0, cr14, cr3, cr14, {2} │ │ - cdp2 5, 0, cr6, cr3, cr15, {7} │ │ - mcr2 13, 0, lr, cr5, cr6, {7} │ │ + mcr2 14, 0, lr, cr3, cr11, {3} │ │ + mcr2 6, 0, r6, cr3, cr12, {0} │ │ + cdp2 14, 0, cr14, cr5, cr3, {1} │ │ mcr2 0, 0, r7, cr3, cr15, {1} │ │ - mcr2 13, 0, lr, cr3, cr14, {4} │ │ - cdp2 0, 0, cr5, cr3, cr14, {6} │ │ + vdot.bf16 q7, , d11[0] │ │ + mcr2 0, 0, r5, cr3, cr11, {7} │ │ vfmal.f16 d15, s9, s8[0] │ │ lsls r6, r1, #7 │ │ lsls r0, r0, #29 │ │ bpl.n 21e0136 │ │ add r0, sp, #40 @ 0x28 │ │ add.w r8, sp, #24 │ │ adds r6, r0, #1 │ │ @@ -523669,42 +523669,42 @@ │ │ beq.n 21e0452 │ │ ldr r0, [sp, #32] │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ ldrb r0, [r0, #11] │ │ lsls r5, r2, #1 │ │ - @ instruction: 0xea15fe04 │ │ - ldr r1, [r3, #68] @ 0x44 │ │ - @ instruction: 0xfe040be1 │ │ + @ instruction: 0xea42fe04 │ │ + ldr r6, [r0, #72] @ 0x48 │ │ + cdp2 12, 0, cr0, cr4, cr14, {0} │ │ @ instruction: 0xfe048be5 │ │ cdp2 3, 0, cr8, cr3, cr0, {1} │ │ - @ instruction: 0xfe066b6c │ │ - mcr2 11, 0, r0, cr4, cr3, {1} @ │ │ - mcr2 10, 0, lr, cr4, cr15, {2} @ │ │ - cdp2 3, 0, cr4, cr3, cr9, {3} │ │ - mcr2 11, 0, r6, cr5, cr10, {4} @ │ │ - @ instruction: 0xfe040b61 │ │ - cdp2 3, 0, cr4, cr4, cr5, {2} │ │ - mcr2 7, 0, r0, cr5, cr5, {3} │ │ - cdp2 7, 0, cr12, cr5, cr0, {5} │ │ + mcr2 11, 0, r6, cr6, cr9, {4} @ │ │ + @ instruction: 0xfe040b60 │ │ + vseleq.f32 s28, s9, s24 │ │ + mcr2 3, 0, r4, cr3, cr6, {4} │ │ + @ instruction: 0xfe056bc7 │ │ + vseleq.f64 d0, d20, d14 │ │ + mcr2 3, 0, r4, cr4, cr2, {3} │ │ + cdp2 7, 0, cr0, cr5, cr2, {5} │ │ + cdp2 7, 0, cr12, cr5, cr13, {6} │ │ cdp2 7, 0, cr15, cr3, cr0, {6} │ │ - cdp2 12, 0, cr12, cr6, cr10, {4} │ │ - mcr2 10, 0, lr, cr4, cr11, {5} @ │ │ - mcr2 11, 0, r8, cr3, cr9, {0} @ │ │ + mcr2 12, 0, ip, cr6, cr7, {5} │ │ + @ instruction: 0xfe04eae8 │ │ + @ instruction: 0xfe038b46 │ │ vdot.bf16 , q2, d1[0] │ │ - mcr2 11, 0, r6, cr6, cr12, {2} @ │ │ - mcr2 2, 0, r6, cr4, cr5, {4} │ │ - mcr2 10, 0, r0, cr5, cr10, {6} @ │ │ + vseleq.f64 d6, d22, d9 │ │ + cdp2 2, 0, cr6, cr4, cr2, {6} │ │ + vseleq.f64 d0, d5, d7 │ │ vfmal.f16 , d20, d2[2] │ │ cdp2 5, 0, cr0, cr6, cr10, {2} │ │ - mcr2 6, 0, lr, cr6, cr14, {5} │ │ + cdp2 6, 0, cr14, cr6, cr11, {7} │ │ cdp2 12, 0, cr13, cr4, cr3, {5} │ │ - vcmla.f16 q0, q3, d3[0], #0 │ │ - vseleq.f32 s20, s10, s30 │ │ + vfmal.f16 q0, d6, d0[2] │ │ + mcr2 10, 0, sl, cr5, cr12, {1} @ │ │ mcr2 2, 0, r7, cr4, cr12, {3} │ │ lsls r5, r2, #1 │ │ │ │ 021e04d0 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -523893,30 +523893,30 @@ │ │ lsls r5, r2, #1 │ │ lsls r6, r6, #13 │ │ mcr2 6, 0, r7, cr6, cr0, {3} │ │ lsls r5, r2, #1 │ │ pop {r1, r2, r3, r5, r7} │ │ cdp2 6, 0, cr7, cr6, cr2, {2} │ │ lsls r5, r2, #1 │ │ - add r0, sp, #416 @ 0x1a0 │ │ + add r0, sp, #596 @ 0x254 │ │ mcr2 6, 0, r7, cr4, cr8, {0} │ │ lsls r5, r2, #1 │ │ orrs r1, r5 │ │ cdp2 5, 0, cr7, cr3, cr14, {7} │ │ lsls r5, r2, #1 │ │ ldr r0, [sp, #320] @ 0x140 │ │ cdp2 5, 0, cr7, cr6, cr4, {6} │ │ lsls r5, r2, #1 │ │ - movs r5, #125 @ 0x7d │ │ + movs r5, #170 @ 0xaa │ │ mcr2 5, 0, r7, cr4, cr10, {4} │ │ lsls r5, r2, #1 │ │ movs r2, #246 @ 0xf6 │ │ mcr2 5, 0, r7, cr3, cr0, {3} │ │ lsls r5, r2, #1 │ │ - ldrsh r5, [r6, r3] │ │ + ldrsh r2, [r4, r4] │ │ cdp2 5, 0, cr7, cr5, cr6, {2} │ │ lsls r5, r2, #1 │ │ ldrb r1, [r1, #26] │ │ mcr2 5, 0, r7, cr6, cr12, {0} │ │ lsls r5, r2, #1 │ │ │ │ 021e06bc : │ │ @@ -523991,16 +523991,16 @@ │ │ popeq {r4, r5, r7, pc} │ │ blx 26ffb50 │ │ ldr r0, [r4, #116] @ 0x74 │ │ lsls r5, r2, #1 │ │ add r1, sp, #32 │ │ vfmal.f16 q5, d19, d6[2] │ │ mcr2 4, 0, r9, cr3, cr14, {1} │ │ - mcr2 4, 0, r0, cr6, cr3, {4} │ │ - mcr2 6, 0, sl, cr5, cr15, {2} │ │ + cdp2 4, 0, cr0, cr6, cr0, {6} │ │ + cdp2 6, 0, cr10, cr5, cr12, {4} │ │ cdp2 14, 0, cr6, cr4, cr12, {6} │ │ lsls r5, r2, #1 │ │ │ │ 021e0790 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ @@ -524062,16 +524062,16 @@ │ │ blx 26ffb50 │ │ nop │ │ ldr r2, [r2, #104] @ 0x68 │ │ lsls r5, r2, #1 │ │ add r0, sp, #288 @ 0x120 │ │ vcmla.f16 q5, , d2[0], #0 │ │ cdp2 3, 0, cr9, cr3, cr10, {4} │ │ - mcr2 3, 0, r0, cr6, cr15, {6} │ │ - cdp2 5, 0, cr10, cr5, cr11, {5} │ │ + cdp2 4, 0, cr0, cr6, cr12, {0} │ │ + mcr2 5, 0, sl, cr5, cr8, {6} │ │ mcr2 14, 0, r6, cr4, cr8, {0} │ │ lsls r5, r2, #1 │ │ │ │ 021e0844 : │ │ ldr.w r1, [r0, #452] @ 0x1c4 │ │ cmp r1, #0 │ │ it eq │ │ @@ -525737,15 +525737,15 @@ │ │ ldrh r6, [r0, r6] │ │ lsls r5, r2, #1 │ │ ldmia r7, {r1, r7} │ │ vcmla.f16 q0, , d9[1], #0 │ │ vfmal.f16 q1, d22, d3[3] │ │ vseleq.f32 s10, s13, s17 │ │ lsls r5, r2, #1 │ │ - bl 25197d6 │ │ + bl 25467d6 │ │ stmia r5!, {r2, r4} │ │ mcr2 6, 0, r7, cr6, cr14, {2} │ │ vseleq.f16 s4, s6, s0 │ │ it eq │ │ bxeq lr │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -529311,15 +529311,15 @@ │ │ movs r0, #1 │ │ str r0, [sp, #68] @ 0x44 │ │ movs r0, #0 │ │ str r0, [sp, #76] @ 0x4c │ │ b.n 21e3e94 >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x164> │ │ nop │ │ ldmia r2, {r0, r1, r2, r6, r7} │ │ - vfmal.f16 d2, s10, s6[0] │ │ + vcmla.f16 q1, , d0[0], #0 │ │ cdp2 12, 0, cr10, cr5, cr15, {0} │ │ vfmal.f16 , d5, d6[1] │ │ mcr2 14, 0, sp, cr6, cr6, {2} │ │ vcmla.f16 d13, d6, d2[0], #0 │ │ vcmla.f16 d9, d6, d11[1], #0 │ │ cmp r2, #0 │ │ ldr r1, [pc, #912] @ (21e455c >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x82c>) │ │ @@ -529652,26 +529652,26 @@ │ │ mov r2, sl │ │ blx 2705930 │ │ blx 27013f0 │ │ mov r1, r6 │ │ movs r2, #1 │ │ blx 2705920 │ │ b.w 21e5732 >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x1a02> │ │ - ldr r6, [r6, #72] @ 0x48 │ │ + ldr r3, [r4, #76] @ 0x4c │ │ mcr2 15, 0, r4, cr4, cr7, {4} │ │ cdp2 12, 0, cr1, cr3, cr14, {3} │ │ mcr2 5, 0, r0, cr6, cr14, {3} │ │ - vseleq.f32 s8, s7, s30 │ │ + mcr2 10, 0, r4, cr3, cr12, {5} @ │ │ mcr2 4, 0, r0, cr4, cr4, {7} │ │ mcr2 14, 0, r7, cr3, cr4, {2} │ │ mcr2 14, 0, r7, cr6, cr4, {1} │ │ - vfmal.f16 q5, d6, d5[1] │ │ - mcr2 6, 0, sl, cr4, cr7, {4} │ │ + vcmla.f16 d10, d22, d10[0], #0 │ │ + cdp2 6, 0, cr10, cr4, cr4, {6} │ │ cdp2 1, 0, cr8, cr3, cr15, {6} │ │ - vseleq.f16 s24, s11, s11 │ │ + mcr2 9, 0, ip, cr5, cr2, {6} @ │ │ vfmal.f16 , d19, d5[1] │ │ str r0, [sp, #288] @ 0x120 │ │ mov r6, r4 │ │ cbz r0, 21e45b2 >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x882> │ │ ldr r0, [sp, #44] @ 0x2c │ │ add r1, sp, #88 @ 0x58 │ │ blx 2707950 │ │ @@ -529991,23 +529991,23 @@ │ │ vstr s2, [sp, #212] @ 0xd4 │ │ vstr s4, [sp, #208] @ 0xd0 │ │ mov r0, r6 │ │ mov r1, sl │ │ blx 2704a20 │ │ b.n 21e4a44 >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0xd14> │ │ nop │ │ - strh r1, [r7, #30] │ │ + strh r6, [r4, #32] │ │ mcr2 12, 0, pc, cr3, cr5, {1} @ │ │ - cdp2 4, 0, cr12, cr5, cr13, {7} │ │ + mcr2 5, 0, ip, cr5, cr10, {0} │ │ cdp2 3, 0, cr11, cr4, cr14, {5} │ │ - vseleq.f32 s0, s13, s20 │ │ + mcr2 10, 0, r0, cr6, cr7, {5} @ │ │ vcmla.f16 , q10, d0[1], #0 │ │ cdp2 14, 0, cr3, cr6, cr5, {4} │ │ - mcr2 9, 0, r0, cr6, cr10, {1} @ │ │ - cdp2 5, 0, cr2, cr4, cr7, {6} │ │ + @ instruction: 0xfe060967 │ │ + mcr2 5, 0, r2, cr4, cr4, {7} │ │ vfmal.f16 , d20, d4[0] │ │ lsls r5, r2, #1 │ │ orr.w r0, r5, #15 │ │ adds r4, r0, #1 │ │ mov r0, r4 │ │ blx 26ffbf0 │ │ mov r6, r0 │ │ @@ -530294,32 +530294,32 @@ │ │ vmrs APSR_nzcv, fpscr │ │ bhi.n 21e4cb8 >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0xf88> │ │ vmov r1, s16 │ │ mov r0, r6 │ │ blx 2707790 │ │ b.n 21e4cf4 >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0xfc4> │ │ ror.w lr, lr, r5 │ │ - ble.n 21e4c72 >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0xf42> │ │ + udf #38 @ 0x26 │ │ mcr2 5, 0, r9, cr4, cr12, {5} │ │ cdp2 14, 0, cr0, cr11, cr4, {4} │ │ lsls r4, r2, #1 │ │ str r6, [sp, #544] @ 0x220 │ │ cdp2 15, 0, cr11, cr11, cr0, {0} │ │ nop │ │ movs r0, r0 │ │ movs r0, r0 │ │ ands r0, r0 │ │ lsls r7, r1 │ │ ldr r1, [sp, #616] @ 0x268 │ │ ldr r1, [sp, #612] @ 0x264 │ │ ldr r1, [sp, #612] @ 0x264 │ │ subs r7, #185 @ 0xb9 │ │ - subs r4, #248 @ 0xf8 │ │ + subs r5, #37 @ 0x25 │ │ mcr2 14, 0, fp, cr5, cr5, {2} │ │ - cdp2 15, 0, cr13, cr5, cr11, {7} │ │ + mcr2 0, 0, lr, cr5, cr8, {0} │ │ mcr2 4, 0, r6, cr3, cr11, {3} │ │ mcr2 6, 0, r7, cr3, cr1, {4} │ │ vdot.bf16 , q3, d15[0] │ │ mcr2 1, 0, pc, cr5, cr11, {0} @ │ │ b.n 21e4e32 >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x1102> │ │ mov r4, r0 │ │ ldr r0, [pc, #888] @ (21e5038 >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x1308>) │ │ @@ -530639,28 +530639,28 @@ │ │ vldr d16, [r9] │ │ ldr.w r0, [r9, #8] │ │ str r0, [r1, #8] │ │ vstr d16, [r1] │ │ b.n 21e507e >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x134e> │ │ strb r7, [r6, #23] │ │ mcr2 3, 0, r6, cr6, cr12, {1} │ │ - @ instruction: 0xfe031964 │ │ + mcr2 9, 0, r1, cr3, cr1, {4} @ │ │ mcr2 9, 0, r3, cr5, cr8, {1} @ │ │ cdp2 12, 0, cr13, cr6, cr13, {4} │ │ - mcr2 13, 0, sp, cr2, cr10, {7} │ │ - mcr2 10, 0, sp, cr3, cr7, {2} @ │ │ + cdp2 14, 0, cr13, cr2, cr7, {1} │ │ + vseleq.f32 s26, s7, s8 │ │ vseleq.f64 d11, d20, d6 │ │ cdp2 0, 0, cr1, cr5, cr10, {4} │ │ - mcr2 14, 0, r9, cr6, cr10, {1} │ │ + cdp2 14, 0, cr9, cr6, cr7, {3} │ │ mcr2 15, 0, r1, cr4, cr11, {5} │ │ cdp2 15, 0, cr1, cr3, cr15, {5} │ │ cdp2 0, 0, cr0, cr3, cr0, {0} │ │ movs r0, r0 │ │ - bl 2050c78 │ │ - ldrb r6, [r7, #18] │ │ + bl 207dc78 │ │ + ldrb r3, [r5, #19] │ │ mcr2 9, 0, lr, cr3, cr9, {6} @ │ │ movs r1, #1 │ │ ldr r0, [sp, #20] │ │ bl 207d390 │ │ orr.w r0, r5, r6 │ │ strb.w r0, [sp, #344] @ 0x158 │ │ mov.w r0, #1065353216 @ 0x3f800000 │ │ @@ -530980,34 +530980,34 @@ │ │ str.w fp, [sp, #352] @ 0x160 │ │ cmp r0, #0 │ │ beq.n 21e54ae >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x177e> │ │ blx 26ffb40 │ │ b.n 21e54ae >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x177e> │ │ nop │ │ ldrh r3, [r6, r5] │ │ - cdp2 6, 0, cr13, cr5, cr9, {6} │ │ - mcr2 12, 0, r3, cr4, cr8, {5} │ │ + mcr2 6, 0, sp, cr5, cr6, {7} │ │ + cdp2 12, 0, cr3, cr4, cr5, {7} │ │ mcr2 14, 0, r8, cr4, cr3, {5} │ │ - mcr2 13, 0, r7, cr6, cr7, {4} │ │ - mcr2 12, 0, r1, cr4, cr14, {3} │ │ - cdp2 15, 0, cr15, cr4, cr4, {5} │ │ + vdot.bf16 , q11, d4[0] │ │ + cdp2 12, 0, cr1, cr4, cr11, {5} │ │ + mcr2 15, 0, pc, cr4, cr1, {6} @ │ │ mcr2 4, 0, sp, cr3, cr6, {1} │ │ cdp2 2, 0, cr15, cr5, cr2, {1} │ │ cdp2 2, 0, cr15, cr5, cr15, {0} │ │ mcr2 6, 0, r7, cr5, cr10, {6} │ │ mcr2 3, 0, sp, cr5, cr5, {4} │ │ - mcr2 11, 0, r5, cr5, cr15, {4} @ │ │ + @ instruction: 0xfe055bcc │ │ cdp2 0, 0, cr0, cr4, cr0, {0} │ │ orrs r4, r6 │ │ lsrs r3, r3, #31 │ │ eors r1, r1 │ │ - cbnz r4, 21e54ca >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x179a> │ │ + cbnz r1, 21e54d6 >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x17a6> │ │ cdp2 15, 0, cr6, cr3, cr14, {5} │ │ - mcr2 14, 0, pc, cr6, cr12, {1} @ │ │ - vfmal.f16 d13, s6, s11[0] │ │ + cdp2 14, 0, cr15, cr6, cr9, {3} │ │ + vcmla.f16 , , d2[1], #0 │ │ vcmla.f16 d5, d19, d2[1], #0 │ │ mcr2 1, 0, pc, cr5, cr10, {0} @ │ │ b.n 21e4e32 >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x1102> │ │ mov r4, r0 │ │ ldr r0, [pc, #948] @ (21e5834 >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x1b04>) │ │ add r0, pc │ │ blx 26ffe40 │ │ @@ -531361,29 +531361,29 @@ │ │ addeq sp, #4 │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ it eq │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ add r0, sp, #208 @ 0xd0 │ │ bl 2093dd8 , std::__ndk1::allocator > fmt::v11::detail::vformat(std::__ndk1::locale const&, fmt::v11::basic_string_view, fmt::v11::detail::vformat_args::type)@@Base+0x130> │ │ - ldrh r1, [r2, r0] │ │ + ldrh r6, [r7, r0] │ │ cdp2 3, 0, cr15, cr4, cr15, {2} │ │ - vseleq.f16 s6, s5, s9 │ │ + mcr2 9, 0, r3, cr2, cr1, {6} @ │ │ cdp2 0, 0, cr0, cr4, cr0, {0} │ │ movs r0, r0 │ │ subs r5, #28 │ │ mcr2 13, 0, r6, cr3, cr3, {2} │ │ mcr2 6, 0, sl, cr6, cr5, {5} │ │ - mcr2 5, 0, pc, cr6, cr12, {5} @ │ │ + cdp2 5, 0, cr15, cr6, cr9, {7} │ │ cdp2 0, 0, cr3, cr3, cr14, {3} │ │ - mcr2 15, 0, lr, cr6, cr13, {6} │ │ + cdp2 0, 0, cr15, cr6, cr10, {0} │ │ mcr2 3, 0, sp, cr4, cr1, {4} │ │ cdp2 0, 0, cr7, cr2, cr15, {0} │ │ - mcr2 4, 0, r9, cr5, cr3, {4} │ │ - cdp2 7, 0, cr11, cr3, cr3, {6} │ │ + cdp2 4, 0, cr9, cr5, cr0, {6} │ │ + mcr2 7, 0, fp, cr3, cr0, {7} │ │ vfmal.f16 d10, s6, s9[0] │ │ bl 207d3d8 │ │ add r0, sp, #208 @ 0xd0 │ │ bl 207d3d8 │ │ add r0, sp, #208 @ 0xd0 │ │ bl 207d3d8 │ │ b.n 21e5950 >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x1c20> │ │ @@ -531652,15 +531652,15 @@ │ │ ittt eq │ │ addeq sp, #40 @ 0x28 │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ subs r4, r3, r6 │ │ lsls r5, r2, #1 │ │ - lsrs r2, r3, #15 │ │ + lsrs r7, r0, #16 │ │ mcr2 11, 0, r1, cr5, cr10, {1} @ │ │ lsls r5, r2, #1 │ │ │ │ 021e5b14 : │ │ ldr r0, [r0, #4] │ │ bx lr │ │ push {r4, r5, r6, r7, lr} │ │ @@ -532000,33 +532000,33 @@ │ │ cmp r0, #0 │ │ itttt ne │ │ ldrbne.w r0, [sp, #88] @ 0x58 │ │ movsne.w r0, r0, lsl #31 │ │ ldrne r0, [sp, #96] @ 0x60 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ - bl 229caca │ │ + bl 22c9aca │ │ subs r2, r7, r3 │ │ lsls r5, r2, #1 │ │ - strb r5, [r5, #16] │ │ + strb r2, [r3, #17] │ │ cdp2 5, 0, cr1, cr4, cr15, {4} │ │ - mcr2 2, 0, r1, cr3, cr5, {7} │ │ + cdp2 3, 0, cr1, cr3, cr2, {1} │ │ mcr2 10, 0, r2, cr4, cr12, {7} @ │ │ cdp2 3, 0, cr4, cr6, cr6, {1} │ │ - cdp2 14, 0, cr2, cr6, cr6, {1} │ │ - mcr2 10, 0, lr, cr5, cr14, {3} @ │ │ + mcr2 14, 0, r2, cr6, cr3, {2} │ │ + vseleq.f32 s28, s11, s23 │ │ cdp2 0, 0, cr5, cr4, cr1, {5} │ │ mcr2 10, 0, r2, cr5, cr14, {6} @ │ │ cdp2 3, 0, cr4, cr6, cr13, {0} │ │ - mcr2 15, 0, ip, cr6, cr7, {7} │ │ - mcr2 3, 0, r7, cr3, cr3, {4} │ │ + cdp2 0, 0, cr13, cr6, cr4, {1} │ │ + cdp2 3, 0, cr7, cr3, cr0, {6} │ │ vseleq.f32 s24, s9, s26 │ │ - cdp2 5, 0, cr15, cr5, cr1, {6} │ │ - mcr2 0, 0, r9, cr3, cr11, {7} │ │ - mcr2 2, 0, r3, cr4, cr4, {2} │ │ + cdp2 5, 0, cr15, cr5, cr14, {7} │ │ + cdp2 1, 0, cr9, cr3, cr8, {1} │ │ + cdp2 2, 0, cr3, cr4, cr1, {4} │ │ mcr2 6, 0, r6, cr4, cr2, {6} │ │ mcr2 4, 0, r1, cr6, cr1, {5} │ │ cdp2 4, 0, cr1, cr3, cr12, {5} │ │ vcmla.f16 d1, d3, d0[1], #0 │ │ lsls r5, r2, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -532488,22 +532488,22 @@ │ │ ldr r0, [r0, #4] │ │ cmp sl, r0 │ │ bne.w 21e619c │ │ b.w 21e6e28 │ │ subs r0, r5, r4 │ │ lsls r5, r2, #1 │ │ ldr r0, [r3, #0] │ │ - @ instruction: 0xfe058a69 │ │ + mcr2 10, 0, r8, cr5, cr6, {4} @ │ │ cdp2 0, 0, cr0, cr3, cr0, {0} │ │ movs r0, r0 │ │ movs r0, r0 │ │ - vcvt.f16.u16 d18, d27, #16 │ │ + vqdmulh.s q9, q0, d24[0] │ │ cdp2 5, 0, cr6, cr4, cr12, {2} │ │ mcr2 7, 0, sl, cr5, cr3, {0} │ │ - @ instruction: 0xfe0589e9 │ │ + mcr2 10, 0, r8, cr5, cr6, {0} @ │ │ mcr2 6, 0, r6, cr4, cr13, {2} │ │ cdp2 6, 0, cr6, cr5, cr13, {1} │ │ mcr2 9, 0, lr, cr5, cr13, {6} @ │ │ lsls r4, r2, #4 │ │ cbz r1, 21e63ee │ │ adds r2, r1, #4 │ │ ldrex r3, [r2] │ │ @@ -532800,15 +532800,15 @@ │ │ ldr r0, [r4, #0] │ │ ldr r1, [r0, #8] │ │ mov r0, r4 │ │ blx r1 │ │ mov r0, r4 │ │ blx 27002e0 │ │ b.n 21e6566 │ │ - add r7, pc, #756 @ (adr r7, 21e69f4 ) │ │ + add r7, pc, #936 @ (adr r7, 21e6aa8 ) │ │ cdp2 3, 0, cr10, cr4, cr14, {5} │ │ cdp2 3, 0, cr10, cr5, cr2, {5} │ │ cdp2 1, 0, cr2, cr5, cr0, {0} │ │ movs r0, #0 │ │ ldr.w fp, [r7, #12] │ │ movt r1, #65520 @ 0xfff0 │ │ strd r0, r1, [sp, #104] @ 0x68 │ │ @@ -533211,15 +533211,15 @@ │ │ blx r1 │ │ mov r0, r4 │ │ blx 27002e0 │ │ b.n 21e6a10 │ │ add r0, pc, #748 @ (adr r0, 21e6e20 ) │ │ cdp2 15, 0, cr9, cr5, cr13, {7} │ │ cdp2 15, 0, cr9, cr5, cr1, {7} │ │ - cdp2 2, 0, cr10, cr5, cr9, {4} │ │ + mcr2 2, 0, sl, cr5, cr6, {5} │ │ cdp2 5, 0, cr1, cr4, cr2, {6} │ │ lsls r5, r2, #1 │ │ ldr r0, [sp, #120] @ 0x78 │ │ mov r5, fp │ │ mov fp, r4 │ │ cmp r0, #0 │ │ beq.w 21e6e54 │ │ @@ -533554,21 +533554,21 @@ │ │ add r0, sp, #52 @ 0x34 │ │ bl 21839a4 │ │ add r0, sp, #56 @ 0x38 │ │ bl 2134e14 │ │ b.n 21e6f3c │ │ pop {r1, r5, r7, pc} │ │ mcr2 13, 0, fp, cr2, cr14, {3} │ │ - mcr2 15, 0, r7, cr2, cr13, {2} │ │ + cdp2 15, 0, cr7, cr2, cr10, {4} │ │ mcr2 10, 0, r5, cr3, cr14, {4} @ │ │ mcr2 13, 0, r7, cr5, cr5, {1} │ │ @ instruction: 0xfe059bcc │ │ @ instruction: 0xfe059bc0 │ │ - mcr2 1, 0, r8, cr5, cr7, {7} │ │ - cdp2 1, 0, cr8, cr3, cr7, {6} │ │ + cdp2 2, 0, cr8, cr5, cr4, {1} │ │ + mcr2 1, 0, r8, cr3, cr4, {7} │ │ cdp2 0, 0, cr3, cr3, cr4, {0} │ │ mcr2 1, 0, pc, cr6, cr8, {0} @ │ │ b.n 21e6e32 │ │ mov r4, r0 │ │ ldr r0, [r0, #8] │ │ cmp r0, #0 │ │ bmi.n 21e6f1a │ │ @@ -533920,16 +533920,16 @@ │ │ bl 2134ec0 * CelxLua::safeGetClass >(int, FatalErrors, char const*)@@Base+0x70> │ │ add r0, sp, #80 @ 0x50 │ │ bl 2134ec0 * CelxLua::safeGetClass >(int, FatalErrors, char const*)@@Base+0x70> │ │ blx 26ffb60 │ │ nop │ │ lsls r4, r1, #20 │ │ lsls r5, r2, #1 │ │ - subs r2, r3, #1 │ │ - mcr2 14, 0, r1, cr4, cr6, {1} │ │ + subs r7, r0, #2 │ │ + cdp2 14, 0, cr1, cr4, cr3, {3} │ │ mcr2 5, 0, fp, cr4, cr0, {7} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #32 │ │ mov r4, r0 │ │ ldr r0, [pc, #152] @ (21e732c ) │ │ add r0, pc │ │ @@ -544868,22 +544868,22 @@ │ │ lsls r4, r2, #1 │ │ add r5, sp, #668 @ 0x29c │ │ vfmal.f16 d6, s10, s12[0] │ │ lsls r3, r2, #1 │ │ ldr r4, [r4, #8] │ │ lsls r3, r2, #1 │ │ add r5, sp, #508 @ 0x1fc │ │ - mcr2 4, 0, r5, cr5, cr5, {5} │ │ + cdp2 4, 0, cr5, cr5, cr2, {7} │ │ cdp2 7, 0, cr6, cr4, cr12, {6} │ │ lsls r3, r2, #1 │ │ ldr r6, [r5, #8] │ │ lsls r3, r2, #1 │ │ ldr r2, [r1, #4] │ │ lsls r3, r2, #1 │ │ - strb r1, [r1, r2] │ │ + strb r6, [r6, r2] │ │ mcr2 9, 0, r1, cr4, cr0, {4} @ │ │ mcr2 1, 0, r1, cr11, cr14, {3} │ │ mcr2 13, 0, r0, cr11, cr8, {7} │ │ mcr2 14, 0, r0, cr11, cr6, {3} │ │ cdp2 15, 0, cr0, cr11, cr6, {0} │ │ mcr2 15, 0, r0, cr11, cr4, {2} │ │ cdp2 15, 0, cr0, cr11, cr6, {6} │ │ @@ -545091,15 +545091,15 @@ │ │ ldrne r0, [sp, #28] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ strh r0, [r0, #0] │ │ mov r5, r3 │ │ str r0, [r5, #80] @ 0x50 │ │ lsls r3, r2, #1 │ │ - str r3, [sp, #104] @ 0x68 │ │ + str r3, [sp, #284] @ 0x11c │ │ cdp2 4, 0, cr6, cr3, cr6, {4} │ │ lsls r3, r2, #1 │ │ strh r4, [r2, #4] │ │ lsls r4, r2, #1 │ │ lsrs r4, r2, #10 │ │ @ instruction: 0xfe0b0a62 │ │ mcr2 15, 0, r7, cr11, cr0, {6} │ │ @@ -547968,18 +547968,18 @@ │ │ mov r0, r6 │ │ bl 2093dd8 , std::__ndk1::allocator > fmt::v11::detail::vformat(std::__ndk1::locale const&, fmt::v11::basic_string_view, fmt::v11::detail::vformat_args::type)@@Base+0x130> │ │ bl 207deaa │ │ nop │ │ str r6, [r5, #60] @ 0x3c │ │ lsls r4, r2, #1 │ │ ldrh r7, [r5, #32] │ │ - cdp2 1, 0, cr3, cr5, cr2, {2} │ │ + cdp2 1, 0, cr3, cr5, cr15, {3} │ │ cdp2 2, 0, cr6, cr4, cr12, {4} │ │ lsls r4, r2, #1 │ │ - bls.n 21f13da │ │ + bge.n 21f1434 │ │ Address 0x21f13da is out of bounds. │ │ │ │ │ │ 021f13dc : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -548358,24 +548358,24 @@ │ │ ldr r0, [sp, #28] │ │ ldr r0, [r0, #8] │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ str r4, [r7, #32] │ │ lsls r4, r2, #1 │ │ - cmp r7, #124 @ 0x7c │ │ + cmp r7, #169 @ 0xa9 │ │ @ instruction: 0xfe04abcb │ │ mcr2 9, 0, r8, cr4, cr9, {5} @ │ │ - cdp2 7, 0, cr13, cr5, cr7, {4} │ │ + mcr2 7, 0, sp, cr5, cr4, {5} │ │ @ instruction: 0xfe03aac1 │ │ mcr2 10, 0, r4, cr4, cr1, {5} @ │ │ vseleq.f32 s8, s11, s7 │ │ vseleq.f32 s20, s10, s19 │ │ - mcr2 5, 0, r1, cr4, cr7, {1} │ │ - cdp2 5, 0, cr1, cr3, cr9, {1} │ │ + cdp2 5, 0, cr1, cr4, cr4, {3} │ │ + mcr2 5, 0, r1, cr3, cr6, {2} │ │ mcr2 9, 0, sl, cr3, cr3, {4} @ │ │ cdp2 14, 0, cr5, cr4, cr14, {6} │ │ lsls r4, r2, #1 │ │ │ │ 021f17fc &, Eigen::Matrix const&, Eigen::Quaternion const&, float, float, float) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -549299,15 +549299,15 @@ │ │ movs r6, #0 │ │ str r3, [sp, #36] @ 0x24 │ │ ldr r4, [r0, #24] │ │ b.n 21f21e8 >&)@@Base+0x3e8> │ │ lsrs r4, r5, #1 │ │ cdp2 0, 0, cr0, cr5, cr0, {0} │ │ subs r3, #128 @ 0x80 │ │ - lsrs r0, r5, #2 │ │ + lsrs r5, r2, #3 │ │ vcmla.f16 , q2, d4[0], #0 │ │ ldrh r4, [r0, r4] │ │ ldr r0, [sp, #28] │ │ adds r6, #1 │ │ cmp r6, r3 │ │ str r4, [r0, #24] │ │ beq.w 21f2304 >&)@@Base+0x504> │ │ @@ -549460,16 +549460,16 @@ │ │ movs r0, r0 │ │ movs r2, r1 │ │ movs r0, r0 │ │ ldr r4, [r2, r0] │ │ lsls r4, r2, #1 │ │ ldrsb r4, [r1, r7] │ │ lsls r4, r2, #1 │ │ - add r4, sp, #364 @ 0x16c │ │ - cdp2 12, 0, cr10, cr2, cr3, {2} │ │ + add r4, sp, #544 @ 0x220 │ │ + mcr2 12, 0, sl, cr2, cr0, {3} │ │ mcr2 0, 0, r5, cr2, cr0, {5} │ │ Address 0x21f2392 is out of bounds. │ │ │ │ │ │ 021f2394 ::emplace_back&>(unsigned int&, boost::intrusive_ptr&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -549981,15 +549981,15 @@ │ │ ldr r0, [r4, #0] │ │ blx 2707f60 │ │ add.w r0, r5, #11 │ │ cmp r0, r8 │ │ bne.n 21f28a6 >&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x402> │ │ b.n 21f2528 >&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x84> │ │ nop │ │ - lsrs r7, r7 │ │ + asrs r4, r5 │ │ cdp2 5, 0, cr12, cr4, cr7, {0} │ │ cdp2 3, 0, cr14, cr4, cr1, {4} │ │ @ instruction: 0xfe048a68 │ │ vcmla.f16 q2, q1, d12[1], #0 │ │ add r0, pc │ │ blx 26ffe40 │ │ mov r4, r0 │ │ @@ -550154,27 +550154,27 @@ │ │ ldrne r0, [sp, #72] @ 0x48 │ │ blxne 26ffb40 │ │ add r0, sp, #84 @ 0x54 │ │ blx 2701ca0 │ │ blx 26ffb60 │ │ str r4, [r6, r5] │ │ lsls r4, r2, #1 │ │ - cmp r1, #18 │ │ - cdp2 14, 0, cr3, cr3, cr13, {0} │ │ + cmp r1, #63 @ 0x3f │ │ + mcr2 14, 0, r3, cr3, cr10, {1} │ │ mcr2 3, 0, r5, cr4, cr4, {3} │ │ lsls r4, r2, #1 │ │ - @ instruction: 0xb895 │ │ - cdp2 3, 0, cr10, cr3, cr6, {1} │ │ + @ instruction: 0xb8c2 │ │ + mcr2 3, 0, sl, cr3, cr3, {2} │ │ mcr2 12, 0, r4, cr2, cr2, {5} │ │ lsls r4, r2, #1 │ │ ldr r4, [r0, #4] │ │ - vdot.bf16 d3, d2, d5[0] │ │ + mcr2 13, 0, r3, cr2, cr2, {1} │ │ cdp2 2, 0, cr5, cr4, cr12, {3} │ │ lsls r4, r2, #1 │ │ - b.n 21f282e >&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x38a> │ │ + b.n 21f2888 >&, std::__ndk1::__fs::filesystem::path const&)@@Base+0x3e4> │ │ Address 0x21f2aba is out of bounds. │ │ │ │ │ │ 021f2abc : │ │ adds r2, r1, #1 │ │ itt eq │ │ moveq r0, #0 │ │ @@ -550558,36 +550558,36 @@ │ │ movs r0, #1 │ │ movs r5, #0 │ │ movs r1, #1 │ │ cmp.w r9, #0 │ │ bne.w 21f3080 │ │ b.n 21f31a8 │ │ nop │ │ - subs r4, r2, r4 │ │ + subs r1, r0, r5 │ │ mcr2 10, 0, r4, cr4, cr0, {6} @ │ │ lsls r4, r2, #1 │ │ - b.n 21f2f40 │ │ - @ instruction: 0xfe033aef │ │ + b.n 21f2f9a │ │ + mcr2 11, 0, r3, cr3, cr12, {0} @ │ │ mcr2 0, 0, r5, cr4, cr4, {2} │ │ lsls r4, r2, #1 │ │ ldr r5, [sp, #296] @ 0x128 │ │ - cdp2 2, 0, cr14, cr4, cr11, {6} │ │ + mcr2 2, 0, lr, cr4, cr8, {7} │ │ mcr2 15, 0, r4, cr2, cr10, {7} │ │ lsls r4, r2, #1 │ │ - strh r0, [r1, #10] │ │ - @ instruction: 0xfe03396f │ │ + strh r5, [r6, #10] │ │ + mcr2 9, 0, r3, cr3, cr12, {4} @ │ │ mcr2 14, 0, r4, cr4, cr6, {6} │ │ lsls r4, r2, #1 │ │ - subs r6, #243 @ 0xf3 │ │ - mcr2 14, 0, r9, cr3, cr15, {6} │ │ - cdp2 0, 0, cr4, cr2, cr6, {5} │ │ + subs r7, #32 │ │ + cdp2 15, 0, cr9, cr3, cr12, {0} │ │ + mcr2 0, 0, r4, cr2, cr3, {6} │ │ cdp2 5, 0, cr12, cr3, cr12, {5} │ │ adds r7, #39 @ 0x27 │ │ - lsls r1, r0 │ │ - cdp2 0, 0, cr14, cr3, cr9, {6} │ │ + lsls r6, r5 │ │ + mcr2 0, 0, lr, cr3, cr6, {7} │ │ mcr2 13, 0, r4, cr2, cr10, {7} │ │ lsls r4, r2, #1 │ │ cmp.w r9, #0 │ │ beq.n 21f2f6e │ │ ldr r0, [pc, #936] @ (21f32c0 ) │ │ add r0, pc │ │ blx 26ffe40 │ │ @@ -550911,30 +550911,30 @@ │ │ vmla.f32 s2, s4, s0 │ │ vsub.f32 s0, s20, s2 │ │ vsub.f32 s20, s0, s22 │ │ cmp.w sl, #0 │ │ bne.w 21f30ee │ │ b.n 21f2fe2 │ │ nop │ │ - subs r7, #159 @ 0x9f │ │ - cdp2 0, 0, cr14, cr3, cr15, {0} │ │ + subs r7, #204 @ 0xcc │ │ + mcr2 0, 0, lr, cr3, cr12, {1} │ │ mcr2 13, 0, r4, cr2, cr14, {1} │ │ lsls r4, r2, #1 │ │ movs r0, r0 │ │ movs r0, r0 │ │ cbz r2, 21f32d8 │ │ - cdp2 15, 0, cr13, cr5, cr9, {5} │ │ + mcr2 15, 0, sp, cr5, cr6, {6} │ │ mcr2 12, 0, r4, cr2, cr6, {6} │ │ lsls r4, r2, #1 │ │ ldr r0, [r0, #108] @ 0x6c │ │ - mcr2 14, 0, sp, cr5, cr7, {4} │ │ + cdp2 14, 0, cr13, cr5, cr4, {6} │ │ @ instruction: 0xfe024bc6 │ │ lsls r4, r2, #1 │ │ - ldr r3, [sp, #248] @ 0xf8 │ │ - mcr2 5, 0, r3, cr2, cr11, {1} │ │ + ldr r3, [sp, #428] @ 0x1ac │ │ + cdp2 5, 0, cr3, cr2, cr8, {3} │ │ vseleq.f32 s8, s9, s1 │ │ lsls r4, r2, #1 │ │ pop {r1, r2, r4, r5, r6, pc} │ │ eors r0, r2 │ │ mov r9, r6 │ │ str.w sl, [r6, #20] │ │ movs r4, #1 │ │ @@ -551319,28 +551319,28 @@ │ │ ldr r0, [sp, #20] │ │ add r1, sp, #112 @ 0x70 │ │ blx 27099f0 │ │ b.n 21f3788 │ │ nop │ │ cmp r2, #250 @ 0xfa │ │ @ instruction: 0xfe056aef │ │ - vseleq.f32 s26, s11, s3 │ │ + @ instruction: 0xfe05dace │ │ cdp2 7, 0, cr4, cr2, cr14, {6} │ │ lsls r4, r2, #1 │ │ bmi.n 21f36ac │ │ - cdp2 2, 0, cr3, cr4, cr13, {0} │ │ + mcr2 2, 0, r3, cr4, cr10, {1} │ │ mcr2 7, 0, r4, cr4, cr4, {3} │ │ lsls r4, r2, #1 │ │ str r6, [r6, r3] │ │ - vcmla.f16 d5, d21, d3[0], #0 │ │ - mcr2 9, 0, sp, cr3, cr15, {0} @ │ │ + vfmal.f16 d5, s11, s1[0] │ │ + @ instruction: 0xfe03d94c │ │ cdp2 6, 0, cr4, cr2, cr14, {2} │ │ lsls r4, r2, #1 │ │ - ldrb r3, [r0, #2] │ │ - cdp2 0, 0, cr3, cr3, cr13, {4} │ │ + ldrb r0, [r6, #2] │ │ + mcr2 0, 0, r3, cr3, cr10, {5} │ │ mcr2 5, 0, r4, cr4, cr4, {7} │ │ lsls r4, r2, #1 │ │ ldr r0, [pc, #752] @ (21f3a24 ) │ │ add r0, pc │ │ blx 26ffe40 │ │ mov r4, r0 │ │ blx 26ffea0 │ │ @@ -551606,33 +551606,33 @@ │ │ vcvt.f32.f64 s0, d16 │ │ vmov r1, s0 │ │ ldr r0, [sp, #20] │ │ blx 27099a0 │ │ b.n 21f3abe │ │ nop │ │ bl 250c62a │ │ - bvc.n 21f3a16 │ │ + bhi.n 21f3a70 │ │ cdp2 5, 0, cr4, cr2, cr4, {1} │ │ lsls r4, r2, #1 │ │ ldr r6, [pc, #924] @ (21f3dd0 ) │ │ cdp2 0, 0, cr1, cr5, cr1, {5} │ │ - cdp2 6, 0, cr13, cr2, cr5, {7} │ │ + mcr2 7, 0, sp, cr2, cr2, {0} │ │ mcr2 4, 0, r4, cr2, cr4, {0} │ │ lsls r4, r2, #1 │ │ cmp r0, #95 @ 0x5f │ │ - cdp2 6, 0, cr13, cr5, cr13, {4} │ │ + mcr2 6, 0, sp, cr5, cr10, {5} │ │ mcr2 3, 0, r4, cr2, cr12, {5} │ │ lsls r4, r2, #1 │ │ - str r0, [sp, #828] @ 0x33c │ │ + str r0, [sp, #1008] @ 0x3f0 │ │ mcr2 9, 0, r8, cr2, cr3, {7} @ │ │ - mcr2 5, 0, sp, cr5, cr1, {7} │ │ + mcr2 6, 0, sp, cr5, cr14, {0} │ │ cdp2 3, 0, cr4, cr2, cr0, {1} │ │ lsls r4, r2, #1 │ │ str r6, [r0, #96] @ 0x60 │ │ - mcr2 5, 0, sp, cr5, cr9, {4} │ │ + cdp2 5, 0, cr13, cr5, cr6, {6} │ │ cdp2 2, 0, cr4, cr2, cr8, {6} │ │ lsls r4, r2, #1 │ │ ldr r0, [pc, #892] @ (21f3de8 ) │ │ add r0, pc │ │ blx 26ffe40 │ │ mov r4, r0 │ │ blx 26ffea0 │ │ @@ -551945,32 +551945,32 @@ │ │ stmia r0!, {r0, r1, r2, r3} │ │ ldrb r5, [r2, #3] │ │ movs r6, #233 @ 0xe9 │ │ lsrs r1, r6, #32 │ │ itt le │ │ suble r1, #12 │ │ lslle r4, r2, #1 │ │ - ldmia r7, {r0, r3, r4, r6, r7} │ │ - mcr2 10, 0, r2, cr3, cr13, {3} @ │ │ + beq.n 21f3dec │ │ + vseleq.f32 s4, s7, s21 │ │ cdp2 15, 0, cr3, cr4, cr4, {7} │ │ lsls r4, r2, #1 │ │ stmia r2!, {r0, r1, r2, r3, r4, r5, r6} │ │ - mcr2 4, 0, sp, cr5, cr13, {5} │ │ + cdp2 4, 0, cr13, cr5, cr10, {7} │ │ cdp2 1, 0, cr4, cr2, cr12, {7} │ │ lsls r4, r2, #1 │ │ ldr r3, [pc, #920] @ (21f4190 ) │ │ mcr2 14, 0, lr, cr5, cr0, {7} │ │ - mcr2 3, 0, sp, cr1, cr11, {4} │ │ + cdp2 3, 0, cr13, cr1, cr8, {6} │ │ cdp2 0, 0, cr4, cr2, cr10, {6} │ │ lsls r4, r2, #1 │ │ lsrs r2, r4, #20 │ │ - cdp2 3, 0, cr13, cr2, cr3, {2} │ │ + mcr2 3, 0, sp, cr2, cr0, {3} │ │ mcr2 0, 0, r4, cr2, cr2, {3} │ │ lsls r4, r2, #1 │ │ - ldr r3, [pc, #856] @ (21f416c ) │ │ + ldr r4, [pc, #12] @ (21f3e20 , std::__ndk1::allocator > const&)@@Base+0xc>) │ │ Address 0x21f3e12 is out of bounds. │ │ │ │ │ │ 021f3e14 , std::__ndk1::allocator > const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -552541,15 +552541,15 @@ │ │ ldr r0, [r4, #44] @ 0x2c │ │ vadd.f32 s22, s0, s20 │ │ cmp r6, r0 │ │ bcs.n 21f4414 │ │ vstmia r6!, {s22} │ │ ldr r0, [sp, #72] @ 0x48 │ │ b.n 21f44b0 │ │ - ldr r1, [pc, #360] @ (21f4578 ) │ │ + ldr r1, [pc, #540] @ (21f462c ) │ │ vcmla.f16 q5, q10, d1[0], #0 │ │ subs r7, #192 @ 0xc0 │ │ mov.w fp, sl, asr #2 │ │ add.w r9, fp, #1 │ │ cmp.w r9, #1073741824 @ 0x40000000 │ │ str r1, [sp, #96] @ 0x60 │ │ bcs.w 21f51d2 │ │ @@ -554411,17 +554411,17 @@ │ │ ldr r1, [r0, #8] │ │ mov r0, r4 │ │ blx r1 │ │ mov r0, r4 │ │ blx 27002e0 │ │ b.n 21f59a0 >&, std::__ndk1::optional&, std::__ndk1::shared_ptr&) const@@Base+0x4a8> │ │ nop │ │ - ldrsb r4, [r1, r0] │ │ + ldrsb r1, [r7, r0] │ │ mcr2 1, 0, r4, cr3, cr11, {2} │ │ - cdp2 1, 0, cr3, cr5, cr12, {6} │ │ + mcr2 1, 0, r3, cr5, cr9, {7} │ │ mcr2 13, 0, r2, cr3, cr3, {7} │ │ str r5, [sp, #596] @ 0x254 │ │ cmp r6, #147 @ 0x93 │ │ subs r7, #202 @ 0xca │ │ movs r0, r0 │ │ movs r0, r0 │ │ movs r0, r0 │ │ @@ -554590,27 +554590,27 @@ │ │ ldmia r0, {r0, r1, r7} │ │ ldr r1, [r1, #92] @ 0x5c │ │ ldrsh r0, [r6, r4] │ │ subs r7, #212 @ 0xd4 │ │ movs r1, #20 │ │ lsls r4, r2, #1 │ │ lsrs r4, r5, #4 │ │ - mcr2 14, 0, r0, cr5, cr15, {7} │ │ + cdp2 15, 0, cr0, cr5, cr12, {1} │ │ cdp2 4, 0, cr2, cr4, cr4, {3} │ │ lsls r4, r2, #1 │ │ - str r6, [sp, #224] @ 0xe0 │ │ - vfmal.f16 d11, s6, s6[1] │ │ + str r6, [sp, #404] @ 0x194 │ │ + vcmla.f16 , , d8[0], #0 │ │ cdp2 5, 0, cr2, cr2, cr14, {2} │ │ lsls r4, r2, #1 │ │ - push {r0, r6, r7, lr} │ │ - mcr2 5, 0, fp, cr2, cr13, {6} │ │ + push {r1, r2, r3, r5, r6, r7, lr} │ │ + cdp2 6, 0, cr11, cr2, cr10, {0} │ │ cdp2 3, 0, cr2, cr2, cr14, {0} │ │ lsls r4, r2, #1 │ │ @ instruction: 0xebb8fe04 │ │ - lsrs r1, r0, #24 │ │ + lsrs r6, r5, #24 │ │ cdp2 3, 0, cr2, cr4, cr10, {3} │ │ lsls r4, r2, #1 │ │ adds r6, r2, #1 │ │ lsls r4, r2, #1 │ │ │ │ 021f5ae0 ::emplace_back&>(unsigned int const&, boost::intrusive_ptr&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -554971,24 +554971,24 @@ │ │ cmp r1, r8 │ │ bne.n 21f5e28 >&, std::__ndk1::optional&) const@@Base+0x238> │ │ mov r1, r8 │ │ b.n 21f5e30 >&, std::__ndk1::optional&) const@@Base+0x240> │ │ nop │ │ subs r0, r5, r0 │ │ lsls r4, r2, #1 │ │ - lsrs r4, r2, #10 │ │ - mcr2 14, 0, sl, cr4, cr8, {4} │ │ - vseleq.f16 s0, s7, s18 │ │ + lsrs r1, r0, #11 │ │ + cdp2 14, 0, cr10, cr4, cr5, {6} │ │ + mcr2 9, 0, r0, cr3, cr6, {5} @ │ │ mcr2 14, 0, r1, cr4, cr4, {7} │ │ lsls r4, r2, #1 │ │ - asrs r2, r2, #8 │ │ - mcr2 2, 0, fp, cr3, cr7, {1} │ │ + asrs r7, r7, #8 │ │ + cdp2 2, 0, cr11, cr3, cr4, {3} │ │ cdp2 15, 0, cr1, cr2, cr12, {3} │ │ lsls r4, r2, #1 │ │ - lsrs r2, r5, #6 │ │ + lsrs r7, r2, #7 │ │ mcr2 3, 0, r1, cr4, cr15, {7} │ │ vcmla.f16 d1, d2, d2[1], #0 │ │ lsls r4, r2, #1 │ │ │ │ 021f5e94 , std::__ndk1::allocator > const&, std::__ndk1::basic_string, std::__ndk1::allocator > const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -555615,16 +555615,16 @@ │ │ cdp2 3, 0, cr1, cr4, cr4, {1} │ │ lsls r4, r2, #1 │ │ asrs r4, r2, #10 │ │ lsls r4, r2, #1 │ │ stmia r2!, {r0, r1, r4, r5, r6, r7} │ │ mcr2 2, 0, r2, cr4, cr9, {7} │ │ cdp2 2, 0, cr2, cr5, cr9, {7} │ │ - mcr2 9, 0, r8, cr5, cr12, {2} @ │ │ - @ instruction: 0xfe038940 │ │ + vseleq.f16 s16, s11, s18 │ │ + @ instruction: 0xfe03896d │ │ mcr2 1, 0, r1, cr3, cr12, {5} │ │ lsls r4, r2, #1 │ │ cmp r1, #0 │ │ it eq │ │ bxeq lr │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -559490,15 +559490,15 @@ │ │ nop │ │ stc 0, cr0, [r6], #-332 @ 0xfffffeb4 │ │ sbc.w r0, r8, r3, lsr #1 │ │ @ instruction: 0xeaea0053 │ │ ldr r2, [r2, #120] @ 0x78 │ │ vseleq.f32 s28, s11, s20 │ │ lsls r3, r2, #1 │ │ - adds r5, r6, r1 │ │ + adds r2, r4, r2 │ │ cdp2 5, 0, cr3, cr3, cr6, {5} │ │ vcmla.f16 q7, , d8[1], #0 │ │ lsls r3, r2, #1 │ │ │ │ 021f8e80 >, bool) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -560668,20 +560668,20 @@ │ │ blx 26ffb60 │ │ b.n 21fa244 >&)@@Base+0x290> │ │ lsls r3, r2, #1 │ │ str r6, [r4, #68] @ 0x44 │ │ mcr2 13, 0, sp, cr5, cr10, {3} │ │ lsls r3, r2, #1 │ │ str r6, [r5, #64] @ 0x40 │ │ - cdp2 15, 0, cr8, cr5, cr12, {3} │ │ - mcr2 15, 0, r8, cr3, cr8, {2} │ │ - cdp2 6, 0, cr3, cr3, cr11, {1} │ │ - mcr2 6, 0, r3, cr3, cr9, {0} │ │ - mcr2 4, 0, pc, cr3, cr1, {7} @ │ │ - cdp2 4, 0, cr15, cr2, cr1, {7} │ │ + mcr2 15, 0, r8, cr5, cr9, {4} │ │ + cdp2 15, 0, cr8, cr3, cr5, {4} │ │ + mcr2 6, 0, r3, cr3, cr8, {2} │ │ + cdp2 6, 0, cr3, cr3, cr6, {2} │ │ + mcr2 5, 0, pc, cr3, cr14, {0} @ │ │ + cdp2 5, 0, cr15, cr2, cr14, {0} │ │ cdp2 2, 0, cr14, cr2, cr6, {6} │ │ lsls r3, r2, #1 │ │ blt.n 21f9a80 >, std::__ndk1::basic_string_view >, std::__ndk1::basic_string_view >, bool) const@@Base+0x1f0> │ │ lsls r3, r2, #1 │ │ │ │ 021f9aa4 >, unsigned int, std::__ndk1::basic_string_view >, std::__ndk1::basic_string_view >, bool) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -560795,16 +560795,16 @@ │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ b.n 21f9f70 >&)@@Base+0x3a4> │ │ lsls r3, r2, #1 │ │ blt.n 21f9ca4 >&)@@Base+0xd8> │ │ lsls r3, r2, #1 │ │ - strh r4, [r3, r2] │ │ - cdp2 2, 0, cr5, cr3, cr10, {4} │ │ + strh r1, [r1, r3] │ │ + mcr2 2, 0, r5, cr3, cr7, {5} │ │ mcr2 10, 0, sp, cr3, cr14, {4} @ │ │ lsls r3, r2, #1 │ │ │ │ 021f9bcc >&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -561162,16 +561162,16 @@ │ │ nop │ │ bge.n 21fa030 >&)@@Base+0x7c> │ │ lsls r3, r2, #1 │ │ bls.n 21f9f9c >&)@@Base+0x3d0> │ │ lsls r3, r2, #1 │ │ bhi.n 21f9fa0 >&)@@Base+0x3d4> │ │ lsls r3, r2, #1 │ │ - muls r5, r7 │ │ - cdp2 3, 0, cr4, cr3, cr5, {4} │ │ + bics r2, r5 │ │ + mcr2 3, 0, r4, cr3, cr2, {5} │ │ mcr2 6, 0, sp, cr3, cr10, {7} │ │ lsls r3, r2, #1 │ │ │ │ 021f9fb4 >&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -561535,15 +561535,15 @@ │ │ subs r2, r1, r0 │ │ it ne │ │ subne.w r2, r6, r3, lsl #1 │ │ movs r3, #1 │ │ bl 21faa2c >::__assign_with_size[abi:ne180000](StarNameDatabase::CrossIndexEntry const*, StarNameDatabase::CrossIndexEntry const*, int)@@Base+0xd0> │ │ b.n 21fa3fa >&)@@Base+0x446> │ │ ldrh r6, [r3, #20] │ │ - cdp2 14, 0, cr0, cr1, cr13, {7} │ │ + mcr2 15, 0, r0, cr1, cr10, {0} │ │ cdp2 1, 0, cr15, cr3, cr5, {0} │ │ b.n 21f9e32 >&)@@Base+0x266> │ │ mov r4, r0 │ │ ldr r0, [pc, #124] @ (21fa438 >&)@@Base+0x484>) │ │ add r0, pc │ │ blx 26ffe40 │ │ mov r6, r0 │ │ @@ -561586,16 +561586,16 @@ │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ bvs.n 21fa4f4 >&)@@Base+0x540> │ │ lsls r3, r2, #1 │ │ movs r0, #155 @ 0x9b │ │ cdp2 3, 0, cr13, cr5, cr8, {2} │ │ lsls r3, r2, #1 │ │ - add r3, pc, #476 @ (adr r3, 21fa614 >&)@@Base+0x660>) │ │ - mcr2 6, 0, lr, cr3, cr9, {2} │ │ + add r3, pc, #656 @ (adr r3, 21fa6c8 >&)@@Base+0x714>) │ │ + cdp2 6, 0, cr14, cr3, cr6, {4} │ │ mcr2 12, 0, pc, cr3, cr9, {2} @ │ │ cdp2 12, 0, cr15, cr4, cr9, {2} │ │ mcr2 5, 0, fp, cr4, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ ldrd r8, r4, [r0] │ │ mov r0, r1 │ │ @@ -564427,15 +564427,15 @@ │ │ lsls r0, r0, #31 │ │ beq.n 21fc292 │ │ ldr r0, [sp, #32] │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ bl 207deaa │ │ nop │ │ - ldmia r5, {r1, r2, r4, r5, r6} │ │ + ldmia r5, {r0, r1, r5, r7} │ │ vfmal.f16 d15, s5, s10[1] │ │ movs r0, r7 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #64] @ 0x40 │ │ blxne 26ffb40 │ │ ldrb.w r0, [sp, #40] @ 0x28 │ │ @@ -564544,18 +564544,18 @@ │ │ ldmiaeq.w sp!, {r8, r9, sl} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ cbz r6, 21fc3fe │ │ lsls r3, r2, #1 │ │ cbz r2, 21fc402 │ │ lsls r3, r2, #1 │ │ - cmp r2, #82 @ 0x52 │ │ + cmp r2, #127 @ 0x7f │ │ cdp2 3, 0, cr11, cr3, cr2, {0} │ │ lsls r3, r2, #1 │ │ - lsrs r3, r0, #17 │ │ + lsrs r0, r6, #17 │ │ mcr2 2, 0, fp, cr3, cr10, {4} │ │ lsls r3, r2, #1 │ │ cmp r1, #0 │ │ it eq │ │ bxeq lr │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -565472,15 +565472,15 @@ │ │ ldrne r0, [sp, #24] │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ add r2, sp, #480 @ 0x1e0 │ │ lsls r3, r2, #1 │ │ add r1, sp, #368 @ 0x170 │ │ lsls r3, r2, #1 │ │ - asrs r5, r5, #23 │ │ + asrs r2, r3, #24 │ │ mcr2 5, 0, fp, cr3, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #12 │ │ mov r6, r0 │ │ ldrb r0, [r1, #0] │ │ mov r9, r1 │ │ @@ -568619,15 +568619,15 @@ │ │ ldrh r2, [r7, #32] │ │ lsls r3, r2, #1 │ │ ldrh r4, [r2, #24] │ │ lsls r3, r2, #1 │ │ udf #99 @ 0x63 │ │ mcr2 9, 0, r8, cr3, cr12, {7} @ │ │ lsls r3, r2, #1 │ │ - eors r6, r0 │ │ + eors r3, r6 │ │ Address 0x21fec7e is out of bounds. │ │ │ │ │ │ 021fec80 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -572815,15 +572815,15 @@ │ │ add r0, pc │ │ bl 2093de8 , std::__ndk1::allocator > fmt::v11::detail::vformat(std::__ndk1::locale const&, fmt::v11::basic_string_view, fmt::v11::detail::vformat_args::type)@@Base+0x140> │ │ nop │ │ ldrsh r0, [r1, r1] │ │ lsls r3, r2, #1 │ │ ldrsh r6, [r1, r0] │ │ lsls r3, r2, #1 │ │ - ldmia r2, {r0, r1, r2} │ │ + ldmia r2, {r2, r4, r5} │ │ Address 0x22018e2 is out of bounds. │ │ │ │ │ │ 022018e4 , std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > >&, std::__ndk1::basic_string_view >, celestia::util::array_view, bool) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -573251,15 +573251,15 @@ │ │ lsls r3, r2, #1 │ │ ldrh r0, [r1, r2] │ │ lsls r3, r2, #1 │ │ ldr r0, [r7, r5] │ │ lsls r3, r2, #1 │ │ ldr r4, [r3, r7] │ │ lsls r3, r2, #1 │ │ - stmia r5!, {r0, r3, r5, r6, r7} │ │ + stmia r6!, {r1, r2, r4} │ │ mcr2 4, 0, sp, cr2, cr4, {6} │ │ bmi.n 2201cca , std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > >&, std::__ndk1::basic_string_view >, celestia::util::array_view, bool) const@@Base+0x172> │ │ │ │ 02201d20 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ vpush {d8-d10} │ │ @@ -574949,18 +574949,18 @@ │ │ itttt eq │ │ moveq r0, r4 │ │ addeq sp, #8 │ │ ldmiaeq.w sp!, {r8, r9, sl} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ - str r0, [r5, r7] │ │ + strh r5, [r2, r0] │ │ cdp2 6, 0, cr4, cr3, cr14, {3} │ │ lsls r3, r2, #1 │ │ - subs r7, #42 @ 0x2a │ │ + subs r7, #87 @ 0x57 │ │ mcr2 10, 0, r4, cr2, cr12, {7} @ │ │ lsls r3, r2, #1 │ │ ble.n 2202fb8 │ │ mcr2 5, 0, r4, cr9, cr10, {7} │ │ lsls r3, r2, #1 │ │ │ │ 02203064 : │ │ @@ -575198,16 +575198,16 @@ │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ adds r4, #50 @ 0x32 │ │ cdp2 4, 0, cr4, cr1, cr0, {2} │ │ lsls r3, r2, #1 │ │ - subs r4, #244 @ 0xf4 │ │ - vdot.bf16 d13, d2, d0[1] │ │ + subs r5, #33 @ 0x21 │ │ + vdot.bf16 , q1, d13[0] │ │ vfmal.f16 d4, s3, s8[1] │ │ lsls r3, r2, #1 │ │ blt.n 2203364 │ │ mcr2 3, 0, r4, cr9, cr10, {4} │ │ lsls r3, r2, #1 │ │ │ │ 022032d0 : │ │ @@ -575586,16 +575586,16 @@ │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ asrs r6, r0 │ │ lsls r3, r2, #1 │ │ bx pc │ │ lsls r3, r2, #1 │ │ - strb r0, [r2, r2] │ │ - cdp2 4, 0, cr5, cr3, cr8, {3} │ │ + strb r5, [r7, r2] │ │ + mcr2 4, 0, r5, cr3, cr5, {4} │ │ mcr2 15, 0, r3, cr3, cr6, {7} │ │ lsls r3, r2, #1 │ │ │ │ 022036ac : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -575959,15 +575959,15 @@ │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ add r0, sp, #128 @ 0x80 │ │ bl 207d3d8 │ │ b.n 2203ade │ │ nop │ │ - ldr r0, [sp, #908] @ 0x38c │ │ + ldr r1, [sp, #64] @ 0x40 │ │ vcmla.f16 d10, d2, d13[0], #0 │ │ bl 2204100 >, unsigned int, unsigned int, unsigned int)@@Base+0xcc> │ │ b.n 2203ade │ │ b.n 2203af0 │ │ b.n 2203aae │ │ ldrb.w r0, [sp, #112] @ 0x70 │ │ lsls r0, r0, #31 │ │ @@ -576005,15 +576005,15 @@ │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ subs r7, #104 @ 0x68 │ │ lsls r3, r2, #1 │ │ subs r3, #188 @ 0xbc │ │ lsls r3, r2, #1 │ │ - bcc.n 2203b3a │ │ + bcc.n 2203b94 │ │ Address 0x2203b0e is out of bounds. │ │ │ │ │ │ 02203b10 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -576501,17 +576501,17 @@ │ │ lsls r0, r0, #31 │ │ beq.n 2203fdc │ │ ldr r0, [sp, #72] @ 0x48 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ subs r0, #216 @ 0xd8 │ │ lsls r3, r2, #1 │ │ - add r7, sp, #984 @ 0x3d8 │ │ - mcr2 1, 0, r9, cr1, cr15, {6} │ │ - cdp2 1, 0, cr9, cr2, cr13, {6} │ │ + add sp, #140 @ 0x8c │ │ + cdp2 2, 0, cr9, cr1, cr12, {0} │ │ + mcr2 1, 0, r9, cr2, cr10, {7} │ │ cdp2 7, 0, cr3, cr2, cr6, {0} │ │ lsls r3, r2, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ ldrb r0, [r1, #0] │ │ mov r5, r2 │ │ @@ -577001,18 +577001,18 @@ │ │ itt ne │ │ ldrne r0, [sp, #80] @ 0x50 │ │ blxne 26ffb40 │ │ b.n 220452c │ │ b.n 220452c │ │ b.n 220453c │ │ nop │ │ - @ instruction: 0xeac0fe01 │ │ + @ instruction: 0xeaedfe01 │ │ adds r4, #226 @ 0xe2 │ │ lsls r3, r2, #1 │ │ - @ instruction: 0xeab0fe01 │ │ + @ instruction: 0xeaddfe01 │ │ ldrb.w r0, [sp, #84] @ 0x54 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #92] @ 0x5c │ │ blxne 26ffb40 │ │ b.n 220453c │ │ ldrb.w r0, [sp, #288] @ 0x120 │ │ @@ -577048,25 +577048,25 @@ │ │ adds r4, #232 @ 0xe8 │ │ lsls r3, r2, #1 │ │ adds r4, #8 │ │ lsls r3, r2, #1 │ │ adds r3, #154 @ 0x9a │ │ lsls r3, r2, #1 │ │ add r0, sp, #588 @ 0x24c │ │ - mcr2 5, 0, r4, cr3, cr12, {7} │ │ - mcr2 5, 0, r4, cr3, cr0, {7} │ │ - mcr2 12, 0, r8, cr3, cr15, {7} │ │ + cdp2 6, 0, cr4, cr3, cr9, {1} │ │ + mcr2 6, 0, r4, cr3, cr13, {0} │ │ + vdot.bf16 d8, d3, d12[1] │ │ vdot.bf16 d2, d2, d10[0] │ │ cdp2 7, 0, cr14, cr1, cr14, {6} │ │ cdp2 5, 0, cr12, cr0, cr11, {1} │ │ cdp2 3, 0, cr4, cr3, cr3, {6} │ │ - mcr2 10, 0, r8, cr4, cr14, {7} @ │ │ + vseleq.f64 d8, d4, d27 │ │ mcr2 5, 0, lr, cr2, cr12, {7} │ │ - cdp2 12, 0, cr8, cr0, cr5, {2} │ │ - mcr2 10, 0, sl, cr2, cr6, {0} @ │ │ + mcr2 12, 0, r8, cr0, cr2, {3} │ │ + @ instruction: 0xfe02aa43 │ │ mcr2 13, 0, r1, cr2, cr6, {5} │ │ mcr2 9, 0, fp, cr4, cr4, {3} @ │ │ Address 0x22045ca is out of bounds. │ │ │ │ │ │ 022045cc : │ │ push {r4, r6, r7, lr} │ │ @@ -579150,18 +579150,18 @@ │ │ mcr2 12, 0, r1, cr0, cr6, {0} │ │ lsls r3, r2, #1 │ │ beq.n 2205c68 │ │ mcr2 5, 0, r5, cr0, cr13, {3} │ │ vseleq.f64 d1, d17, d6 │ │ lsls r3, r2, #1 │ │ strb r5, [r5, r5] │ │ - mcr2 4, 0, fp, cr1, cr6, {2} │ │ + cdp2 4, 0, cr11, cr1, cr3, {4} │ │ @ instruction: 0xfe011b48 │ │ lsls r3, r2, #1 │ │ - push {r1, r2, r6} │ │ + push {r0, r1, r4, r5, r6} │ │ vseleq.f64 d1, d1, d24 │ │ lsls r3, r2, #1 │ │ movs r3, #4 │ │ cmp r6, #4 │ │ it ls │ │ movls r6, r3 │ │ strd r4, r9, [sp] │ │ @@ -579326,16 +579326,16 @@ │ │ subs r2, r7, r2 │ │ lsls r3, r2, #1 │ │ asrs r2, r3, #23 │ │ cdp2 2, 0, cr5, cr1, cr8, {0} │ │ cdp2 7, 0, cr1, cr1, cr14, {7} │ │ lsls r3, r2, #1 │ │ str r0, [r7, r7] │ │ - mcr2 11, 0, r0, cr1, cr2, {1} @ │ │ - mcr2 11, 0, r0, cr3, cr14, {0} @ │ │ + mcr2 11, 0, r0, cr1, cr15, {2} @ │ │ + @ instruction: 0xfe030b4b │ │ mcr2 14, 0, r1, cr3, cr6, {5} │ │ lsls r3, r2, #1 │ │ ldmia r0, {r0, r3, r7} │ │ cdp2 6, 0, cr6, cr3, cr14, {3} │ │ Address 0x2205f12 is out of bounds. │ │ │ │ │ │ @@ -580948,18 +580948,18 @@ │ │ ittt eq │ │ addeq sp, #32 │ │ ldmiaeq.w sp!, {r8, r9, sl} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ lsls r0, r4, #29 │ │ lsls r3, r2, #1 │ │ - strh r3, [r1, #8] │ │ + strh r0, [r7, #8] │ │ cdp2 7, 0, cr0, cr1, cr8, {3} │ │ lsls r3, r2, #1 │ │ - add r0, pc, #284 @ (adr r0, 22070e4 ) │ │ + add r0, pc, #464 @ (adr r0, 2207198 ) │ │ cdp2 7, 0, cr0, cr1, cr2, {0} │ │ lsls r3, r2, #1 │ │ lsls r2, r1, #26 │ │ lsls r3, r2, #1 │ │ │ │ 02206fd0 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -581077,15 +581077,15 @@ │ │ blx 26ffb50 │ │ mov r0, r5 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ lsls r6, r1, #25 │ │ lsls r3, r2, #1 │ │ - str r5, [sp, #232] @ 0xe8 │ │ + str r5, [sp, #412] @ 0x19c │ │ mcr2 0, 0, r0, cr2, cr5, {7} │ │ movs r0, r0 │ │ lsls r0, r3, #21 │ │ lsls r3, r2, #1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ ldr r4, [r0, #0] │ │ @@ -581549,25 +581549,25 @@ │ │ mov r0, r5 │ │ b.n 2207412 │ │ mov r0, r5 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ lsls r2, r4, #11 │ │ lsls r3, r2, #1 │ │ - str r1, [sp, #832] @ 0x340 │ │ + str r1, [sp, #1012] @ 0x3f4 │ │ vfmal.f16 d3, s5, s11[1] │ │ mcr2 2, 0, r0, cr3, cr4, {3} │ │ lsls r3, r2, #1 │ │ cmp r4, #68 @ 0x44 │ │ cdp2 2, 0, cr0, cr4, cr0, {6} │ │ lsls r3, r2, #1 │ │ - ldr r0, [sp, #240] @ 0xf0 │ │ + ldr r0, [sp, #420] @ 0x1a4 │ │ vfmal.f16 q0, d2, d0[3] │ │ lsls r3, r2, #1 │ │ - sadd16 lr, sl, r1 │ │ + ssub8 lr, r7, r1 │ │ lsls r1, r7, #4 │ │ movs r0, r0 │ │ ldr r1, [sp, #648] @ 0x288 │ │ mcr2 2, 0, r0, cr9, cr6, {0} │ │ lsls r3, r2, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -581969,22 +581969,22 @@ │ │ blx 26ffb60 │ │ nop │ │ vqadd.u64 q8, q1, q1 │ │ adds r2, #33 @ 0x21 │ │ mcr2 12, 0, ip, cr1, cr15, {1} │ │ mcr2 13, 0, pc, cr3, cr2, {5} @ │ │ lsls r2, r2, #1 │ │ - str r4, [sp, #496] @ 0x1f0 │ │ + str r4, [sp, #676] @ 0x2a4 │ │ mcr2 2, 0, fp, cr2, cr4, {1} │ │ cdp2 2, 0, cr11, cr0, cr8, {1} │ │ vseleq.f32 s8, s1, s10 │ │ mcr2 10, 0, r4, cr4, cr9, {3} @ │ │ cdp2 4, 0, cr0, cr4, cr2, {5} │ │ lsls r3, r2, #1 │ │ - ldmia r6, {r0, r1, r4, r6} │ │ + ldmia r6!, {r7} │ │ cdp2 14, 0, cr15, cr2, cr10, {0} │ │ lsls r2, r2, #1 │ │ lsls r3, r2, #3 │ │ movs r0, r0 │ │ ldc2l 0, cr0, [r0], #-328 @ 0xfffffeb8 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -583768,16 +583768,16 @@ │ │ add r0, sp, #24 │ │ str r6, [sp, #24] │ │ bl 21a6d70 ::InfoType>::construct[abi:ne180000]::InfoType, TextureInfo const&>(ResourceManager::InfoType*, TextureInfo const&)@@Base+0x38c> │ │ mov r0, r6 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ orns r0, r6, r2, lsr #1 │ │ - bge.n 2208c6c >&)@@Base+0xc8> │ │ - mcr2 3, 0, r6, cr2, cr13, {2} │ │ + bge.n 2208cc6 >&)@@Base+0x122> │ │ + cdp2 3, 0, cr6, cr2, cr10, {4} │ │ vcmla.f16 , , d2[1], #0 │ │ mcr2 2, 0, r0, cr3, cr5, {4} │ │ movs r0, r0 │ │ @ instruction: 0xe9a00052 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -583961,17 +583961,17 @@ │ │ movs r0, #1 │ │ b.n 2208ea2 >&)@@Base+0x2fe> │ │ ldmdb r2, {r1, r4, r6} │ │ lsrs r7, r7, #3 │ │ movs r0, r0 │ │ b.n 2208810 >::__push_back_slow_path(M3DTriangleMesh&&)@@Base+0x20c> │ │ vseleq.f16 s30, s0, s24 │ │ - cdp2 1, 0, cr14, cr3, cr13, {1} │ │ - cdp2 15, 0, cr5, cr1, cr5, {4} │ │ - mcr2 0, 0, lr, cr2, cr14, {7} │ │ + mcr2 1, 0, lr, cr3, cr10, {2} │ │ + mcr2 15, 0, r5, cr1, cr2, {5} │ │ + cdp2 1, 0, cr14, cr2, cr11, {1} │ │ mcr2 2, 0, r5, cr1, cr7, {1} │ │ vcmla.f16 d15, d20, d14[0], #0 │ │ cdp2 7, 0, cr14, cr3, cr6, {4} │ │ lsls r2, r2, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -584030,15 +584030,15 @@ │ │ beq.w 22090a4 │ │ b.n 2208f50 >&)@@Base+0x3ac> │ │ nop │ │ b.n 2208de4 >&)@@Base+0x240> │ │ lsls r2, r2, #1 │ │ b.n 2208d24 >&)@@Base+0x180> │ │ lsls r2, r2, #1 │ │ - ldr r1, [sp, #476] @ 0x1dc │ │ + ldr r1, [sp, #656] @ 0x290 │ │ cdp2 2, 0, cr0, cr2, cr1, {2} │ │ movs r0, r0 │ │ b.n 2208d64 >&)@@Base+0x1c0> │ │ lsls r2, r2, #1 │ │ │ │ 02208f88 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -584228,15 +584228,15 @@ │ │ b.n 2208c5c >&)@@Base+0xb8> │ │ lsls r2, r2, #1 │ │ lsls r3, r3, #21 │ │ movs r0, r0 │ │ push {r1, r3, r4, r5} │ │ cdp2 5, 0, cr0, cr3, cr5, {0} │ │ movs r0, r0 │ │ - subs r6, #220 @ 0xdc │ │ + subs r7, #9 │ │ cdp2 4, 0, cr14, cr2, cr2, {7} │ │ lsls r2, r2, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8-d9} │ │ @@ -584582,15 +584582,15 @@ │ │ movs r3, #17 │ │ strd r3, r1, [sp] │ │ add r3, sp, #80 @ 0x50 │ │ strd r3, r1, [sp, #8] │ │ movs r3, #63 @ 0x3f │ │ blx 26ffe60 │ │ b.n 2209550 │ │ - push {r2, r5, r6, r7} │ │ + push {r0, r4, lr} │ │ vfmal.f16 d10, s4, s8[0] │ │ blx 2708920 │ │ blx 26ffe30 │ │ ldr r1, [r0, #8] │ │ cmp r1, #4 │ │ blt.n 2209550 │ │ ldr r2, [pc, #220] @ (2209618 ) │ │ @@ -584661,33 +584661,33 @@ │ │ ldr r0, [sp, #64] @ 0x40 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ b.n 2208f14 >&)@@Base+0x370> │ │ lsls r2, r2, #1 │ │ bl 24941fa │ │ - bge.n 220954a │ │ + bge.n 22095a4 │ │ cdp2 3, 0, cr0, cr1, cr3, {5} │ │ movs r0, r0 │ │ svc 74 @ 0x4a │ │ mcr2 1, 0, r0, cr0, cr9, {3} │ │ movs r0, r0 │ │ - ldr r1, [r6, r3] │ │ - mcr2 10, 0, sp, cr2, cr0, {3} @ │ │ + ldr r6, [r3, r4] │ │ + mcr2 10, 0, sp, cr2, cr13, {4} @ │ │ vseleq.f64 d4, d17, d21 │ │ cdp2 14, 0, cr4, cr4, cr5, {0} │ │ mcr2 7, 0, r0, cr4, cr9, {2} │ │ movs r0, r0 │ │ bl 23f0222 │ │ b.n 2209750 │ │ lsls r2, r2, #1 │ │ ldmia r5!, {r1, r3, r4, r6, r7} │ │ cdp2 4, 0, cr1, cr3, cr11, {5} │ │ movs r0, r0 │ │ - uxtb r4, r6 │ │ + cbz r1, 2209674 │ │ mcr2 2, 0, lr, cr2, cr6, {0} │ │ lsls r2, r2, #1 │ │ push {r7, lr} │ │ mov r7, sp │ │ sub sp, #40 @ 0x28 │ │ ldr r1, [pc, #68] @ (220967c ) │ │ movs r3, #2 │ │ @@ -584717,15 +584717,15 @@ │ │ itt eq │ │ addeq sp, #40 @ 0x28 │ │ popeq {r7, pc} │ │ blx 26ffb50 │ │ nop │ │ svc 238 @ 0xee │ │ lsls r2, r2, #1 │ │ - bl 1e27288 │ │ + bl 1e54288 │ │ svc 196 @ 0xc4 │ │ lsls r2, r2, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #32 │ │ mov r6, r0 │ │ @@ -584807,15 +584807,15 @@ │ │ addeq sp, #32 │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ svc 148 @ 0x94 │ │ lsls r2, r2, #1 │ │ - add sp, #24 │ │ + add sp, #204 @ 0xcc │ │ mcr2 14, 0, sp, cr2, cr8, {7} │ │ lsls r2, r2, #1 │ │ │ │ 02209758 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ ldr r5, [r0, #12] │ │ @@ -585119,17 +585119,17 @@ │ │ movs r0, #1 │ │ b.n 2209a12 │ │ ble.n 2209978 │ │ lsls r2, r2, #1 │ │ stc2 15, cr15, [pc, #1020] @ 2209e34 │ │ bls.n 2209aa0 │ │ mcr2 13, 0, lr, cr0, cr12, {4} │ │ - mcr2 5, 0, sp, cr3, cr13, {5} │ │ - mcr2 4, 0, r5, cr1, cr5, {0} │ │ - cdp2 5, 0, cr13, cr2, cr14, {4} │ │ + cdp2 5, 0, cr13, cr3, cr10, {7} │ │ + cdp2 4, 0, cr5, cr1, cr2, {2} │ │ + mcr2 5, 0, sp, cr2, cr11, {5} │ │ cdp2 6, 0, cr4, cr1, cr7, {6} │ │ mcr2 13, 0, lr, cr4, cr14, {0} │ │ mcr2 12, 0, sp, cr3, cr6, {0} │ │ lsls r2, r2, #1 │ │ bmi.n 2209a04 │ │ bmi.n 2209a06 │ │ bmi.n 2209a08 │ │ @@ -585478,27 +585478,27 @@ │ │ vstr s0, [sp, #108] @ 0x6c │ │ blx 270a490 │ │ add.w sl, sl, #1 │ │ cmp r6, sl │ │ bne.n 2209d98 │ │ ldr r0, [sp, #20] │ │ b.n 2209e98 │ │ - asrs r5, r4, #17 │ │ - cdp2 12, 0, cr10, cr2, cr13, {1} │ │ + asrs r2, r2, #18 │ │ + mcr2 12, 0, sl, cr2, cr10, {2} │ │ cdp2 5, 0, cr0, cr2, cr1, {0} │ │ - cdp2 1, 0, cr7, cr4, cr5, {2} │ │ + mcr2 1, 0, r7, cr4, cr2, {3} │ │ cdp2 15, 0, cr8, cr2, cr0, {7} │ │ - cdp2 6, 0, cr11, cr0, cr13, {4} │ │ + mcr2 6, 0, fp, cr0, cr10, {5} │ │ cdp2 6, 0, cr15, cr1, cr2, {7} │ │ cdp2 4, 0, cr0, cr0, cr4, {5} │ │ mcr2 14, 0, r4, cr4, cr2, {5} │ │ - mcr2 1, 0, r5, cr3, cr12, {2} │ │ - cdp2 15, 0, cr8, cr2, cr0, {6} │ │ - mcr2 11, 0, r8, cr1, cr12, {5} @ │ │ - vdot.bf16 q7, q1, d14[0] │ │ + cdp2 1, 0, cr5, cr3, cr9, {4} │ │ + cdp2 15, 0, cr8, cr2, cr13, {7} │ │ + @ instruction: 0xfe018be9 │ │ + mcr2 13, 0, lr, cr2, cr11, {3} │ │ mcr2 2, 0, r0, cr2, cr9, {6} │ │ cdp2 0, 0, cr9, cr4, cr4, {0} │ │ cbz r6, 2209e96 │ │ add.w r8, sp, #32 │ │ mov.w r9, #0 │ │ add.w sl, r8, #4 │ │ add.w r0, r8, #8 │ │ @@ -585815,22 +585815,22 @@ │ │ b.n 2209e9a │ │ nop │ │ ... │ │ movs r0, r0 │ │ subs r7, #128 @ 0x80 │ │ blt.n 220a0e8 │ │ lsls r2, r2, #1 │ │ - cmp r5, #140 @ 0x8c │ │ + cmp r5, #185 @ 0xb9 │ │ vdot.bf16 d0, d1, d1[0] │ │ mcr2 9, 0, sl, cr3, cr12, {6} @ │ │ cdp2 2, 0, cr0, cr0, cr13, {4} │ │ movs r0, r0 │ │ bpl.n 220a1ec │ │ lsls r2, r2, #1 │ │ - ldmia r6!, {r0, r1, r2, r3, r7} │ │ + ldmia r6!, {r2, r3, r4, r5, r7} │ │ @ instruction: 0xfe01da4e │ │ lsls r2, r2, #1 │ │ │ │ 0220a1a0 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ @@ -586249,16 +586249,16 @@ │ │ mcr2 0, 0, r2, cr0, cr8, {2} │ │ cdp2 0, 0, cr2, cr4, cr12, {2} │ │ cdp2 4, 0, cr6, cr4, cr6, {6} │ │ mcr2 4, 0, r6, cr3, cr8, {5} │ │ mcr2 0, 0, r2, cr3, cr10, {0} │ │ cdp2 0, 0, cr2, cr4, cr8, {0} │ │ mcr2 14, 0, r3, cr4, cr14, {3} │ │ - mcr2 12, 0, r4, cr4, cr3, {5} │ │ - mcr2 9, 0, r6, cr1, cr7, {7} @ │ │ + cdp2 12, 0, cr4, cr4, cr0, {7} │ │ + vseleq.f32 s12, s2, s9 │ │ cdp2 0, 0, cr13, cr2, cr8, {5} │ │ lsls r2, r2, #1 │ │ bcc.n 220a698 │ │ lsls r2, r2, #1 │ │ │ │ 0220a5f8 : │ │ push {r4, r5, r7, lr} │ │ @@ -586485,17 +586485,17 @@ │ │ movs r0, #1 │ │ b.n 220a7fe │ │ ldmia r7, {r1, r2, r4, r5, r7} │ │ lsls r2, r2, #1 │ │ @ instruction: 0xefa3ffff │ │ ldmia r3!, {r1, r2, r6} │ │ mcr2 15, 0, sp, cr0, cr0, {5} │ │ - mcr2 7, 0, ip, cr3, cr1, {6} │ │ - cdp2 6, 0, cr4, cr1, cr9, {1} │ │ - cdp2 7, 0, cr12, cr2, cr2, {5} │ │ + mcr2 7, 0, ip, cr3, cr14, {7} │ │ + mcr2 6, 0, r4, cr1, cr6, {2} │ │ + cdp2 7, 0, cr12, cr2, cr15, {6} │ │ vfmal.f16 , d17, d3[1] │ │ mcr2 15, 0, sp, cr4, cr2, {1} │ │ cdp2 14, 0, cr12, cr3, cr10, {1} │ │ lsls r2, r2, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -586764,24 +586764,24 @@ │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ movs r0, r0 │ │ stmia r2!, {r3, r6, r7} │ │ ldmia r5!, {r1, r2, r4, r6, r7} │ │ lsls r2, r2, #1 │ │ - ldr r6, [sp, #364] @ 0x16c │ │ - cdp2 4, 0, cr2, cr2, cr14, {5} │ │ - mcr2 7, 0, r4, cr1, cr3, {1} │ │ + ldr r6, [sp, #544] @ 0x220 │ │ + mcr2 4, 0, r2, cr2, cr11, {6} │ │ + cdp2 7, 0, cr4, cr1, cr0, {3} │ │ cdp2 1, 0, cr0, cr1, cr13, {7} │ │ movs r0, r0 │ │ ldmia r3, {r1, r2, r3, r4, r6} │ │ lsls r2, r2, #1 │ │ - pop {r0, r2, r5, r6, r7, pc} │ │ + bkpt 0x0012 │ │ mcr2 6, 0, r0, cr2, cr15, {1} │ │ - mcr2 6, 0, r2, cr1, cr11, {2} │ │ + cdp2 6, 0, cr2, cr1, cr8, {4} │ │ mcr2 1, 0, r8, cr2, cr14, {0} │ │ mcr2 12, 0, ip, cr0, cr6, {3} │ │ lsls r2, r2, #1 │ │ │ │ 0220ab28 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ @@ -586878,15 +586878,15 @@ │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ ldmia r2!, {r1, r4, r6, r7} │ │ lsls r2, r2, #1 │ │ ldmia r2!, {r3, r4, r5, r6} │ │ lsls r2, r2, #1 │ │ - lsls r6, r7, #14 │ │ + lsls r3, r5, #15 │ │ @ instruction: 0xfe02ca46 │ │ lsls r2, r2, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #44 @ 0x2c │ │ mov r6, r0 │ │ @@ -587066,17 +587066,17 @@ │ │ movs r0, #1 │ │ b.n 220adb6 │ │ ldmia r1, {r1, r2, r3, r4, r5, r6, r7} │ │ lsls r2, r2, #1 │ │ strd pc, pc, [r9, #1020]! @ 0x3fc │ │ stmia r5!, {r2, r3, r7} │ │ mcr2 9, 0, sp, cr0, cr8, {7} @ │ │ - mcr2 2, 0, ip, cr3, cr9, {0} │ │ - mcr2 0, 0, r4, cr1, cr1, {3} │ │ - cdp2 1, 0, cr12, cr2, cr10, {7} │ │ + cdp2 2, 0, cr12, cr3, cr6, {2} │ │ + mcr2 0, 0, r4, cr1, cr14, {4} │ │ + mcr2 2, 0, ip, cr2, cr7, {0} │ │ cdp2 3, 0, cr3, cr1, cr3, {1} │ │ mcr2 9, 0, sp, cr4, cr10, {3} @ │ │ vfmal.f16 q6, d3, d2[2] │ │ lsls r2, r2, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -587294,22 +587294,22 @@ │ │ b.n 220b020 │ │ nop │ │ movs r0, r0 │ │ muls r7, r7 │ │ ldmia r0!, {r1, r2, r3, r4} │ │ lsls r2, r2, #1 │ │ ldrb r5, [r7, #20] │ │ - cdp2 14, 0, cr5, cr0, cr4, {6} │ │ + mcr2 14, 0, r5, cr0, cr1, {7} │ │ mcr2 4, 0, r1, cr2, cr4, {7} │ │ mcr2 13, 0, r7, cr4, cr3, {0} │ │ mcr2 12, 0, r7, cr0, cr1, {7} │ │ - mcr2 0, 0, ip, cr0, cr15, {6} │ │ + cdp2 1, 0, cr12, cr0, cr12, {0} │ │ mcr2 10, 0, r5, cr1, cr14, {3} @ │ │ mcr2 7, 0, lr, cr3, cr15, {1} │ │ - vcvt.f32.u32 d21, d3, #1 │ │ + vqrdmlah.s , , d0[0] │ │ cdp2 6, 0, cr12, cr2, cr4, {3} │ │ lsls r2, r2, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #44 @ 0x2c │ │ mov r6, r0 │ │ @@ -587489,17 +587489,17 @@ │ │ movs r0, #1 │ │ b.n 220b1f6 │ │ stmia r5!, {r1, r2, r3, r4, r5, r7} │ │ lsls r2, r2, #1 │ │ b.n 220ad6e │ │ @ instruction: 0xffffc14c │ │ mcr2 5, 0, sp, cr0, cr8, {5} │ │ - mcr2 13, 0, fp, cr3, cr9, {6} │ │ - mcr2 12, 0, r3, cr1, cr1, {1} │ │ - vdot.bf16 d11, d18, d10[1] │ │ + cdp2 14, 0, cr11, cr3, cr6, {0} │ │ + mcr2 12, 0, r3, cr1, cr14, {2} │ │ + mcr2 13, 0, fp, cr2, cr7, {6} │ │ cdp2 14, 0, cr2, cr1, cr3, {7} │ │ mcr2 5, 0, sp, cr4, cr10, {1} │ │ mcr2 4, 0, ip, cr3, cr2, {1} │ │ lsls r2, r2, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -587676,22 +587676,22 @@ │ │ ittt eq │ │ addeq sp, #40 @ 0x28 │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ stmia r3!, {r1, r2, r3, r4, r6, r7} │ │ lsls r2, r2, #1 │ │ - pop {r0, r2, r3, r4, r6, pc} │ │ - vdot.bf16 , , d10[0] │ │ + pop {r1, r3, r7, pc} │ │ + mcr2 13, 0, r1, cr1, cr7, {7} │ │ mcr2 14, 0, fp, cr2, cr13, {7} │ │ cdp2 4, 0, cr13, cr0, cr15, {3} │ │ mcr2 10, 0, r4, cr3, cr1, {2} @ │ │ @ instruction: 0xfe04f967 │ │ mcr2 2, 0, lr, cr2, cr1, {3} │ │ - vrsra.u64 d27, d30, #1 │ │ + @ instruction: 0xffffb3eb │ │ cdp2 2, 0, cr12, cr2, cr2, {2} │ │ lsls r2, r2, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ ldr r5, [r0, #0] │ │ mov r4, r0 │ │ @@ -590979,100 +590979,100 @@ │ │ moveq r0, r8 │ │ addeq sp, #8 │ │ ldmiaeq.w sp!, {r8, r9, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ ldr r6, [sp, #832] @ 0x340 │ │ lsls r2, r2, #1 │ │ - asrs r6, r4, #25 │ │ + asrs r3, r2, #26 │ │ mcr2 5, 0, sl, cr2, cr10, {1} │ │ lsls r2, r2, #1 │ │ asrs r6, r5, #13 │ │ mcr2 5, 0, sl, cr3, cr14, {0} │ │ lsls r2, r2, #1 │ │ bl 24666f8 │ │ - uxtb r7, r5 │ │ + cbz r4, 220db3e │ │ cdp2 5, 0, cr10, cr2, cr2, {0} │ │ lsls r2, r2, #1 │ │ adds r2, #126 @ 0x7e │ │ cdp2 4, 0, cr10, cr3, cr4, {7} │ │ lsls r2, r2, #1 │ │ add r4, pc, #840 @ (adr r4, 220de50 ) │ │ lsls r2, r2, #1 │ │ - ldr r7, [r2, #116] @ 0x74 │ │ + ldr r4, [r0, #120] @ 0x78 │ │ mcr2 4, 0, sl, cr2, cr4, {5} │ │ lsls r2, r2, #1 │ │ add r4, pc, #648 @ (adr r4, 220dd9c ) │ │ lsls r2, r2, #1 │ │ lsrs r0, r4, #3 │ │ cdp2 4, 0, cr10, cr4, cr6, {4} │ │ lsls r2, r2, #1 │ │ add r6, sp, #956 @ 0x3bc │ │ mcr2 4, 0, sl, cr3, cr0, {3} │ │ lsls r2, r2, #1 │ │ @ instruction: 0xebd9fe03 │ │ add r4, pc, #336 @ (adr r4, 220dc7c ) │ │ lsls r2, r2, #1 │ │ - ldrb r4, [r2, #6] │ │ + ldrb r1, [r0, #7] │ │ mcr2 4, 0, sl, cr1, cr10, {1} │ │ lsls r2, r2, #1 │ │ - bl 21e473a >&, Universe&, std::__ndk1::__fs::filesystem::path const&)@@Base+0xa0a> │ │ + strbt pc, [r3, #1] │ │ add r4, pc, #128 @ (adr r4, 220dbbc ) │ │ lsls r2, r2, #1 │ │ strh r4, [r0, r3] │ │ - cdp2 5, 0, cr11, cr0, cr12, {6} │ │ + mcr2 5, 0, fp, cr0, cr9, {7} │ │ cdp2 4, 0, cr10, cr1, cr2, {0} │ │ lsls r2, r2, #1 │ │ - bl 1e6a74c │ │ + bl 1e9774c │ │ add r3, pc, #928 @ (adr r3, 220def0 ) │ │ lsls r2, r2, #1 │ │ strb r1, [r1, #1] │ │ cdp2 3, 0, cr10, cr0, cr14, {6} │ │ lsls r2, r2, #1 │ │ ldr r1, [sp, #64] @ 0x40 │ │ mcr2 3, 0, sl, cr0, cr4, {5} │ │ lsls r2, r2, #1 │ │ ldr r7, [r4, #60] @ 0x3c │ │ mcr2 3, 0, sl, cr3, cr8, {4} │ │ lsls r2, r2, #1 │ │ ldr r0, [sp, #868] @ 0x364 │ │ cdp2 3, 0, cr10, cr0, cr2, {4} │ │ lsls r2, r2, #1 │ │ - adds r6, #37 @ 0x25 │ │ + adds r6, #82 @ 0x52 │ │ cdp2 3, 0, cr10, cr1, cr6, {3} │ │ lsls r2, r2, #1 │ │ asrs r3, r5, #5 │ │ mcr2 3, 0, sl, cr3, cr0, {2} │ │ lsls r2, r2, #1 │ │ - adds r2, #97 @ 0x61 │ │ - vcmla.f16 , , d15[1], #0 │ │ + adds r2, #142 @ 0x8e │ │ + vfmal.f16 d7, s3, s8[1] │ │ mcr2 3, 0, sl, cr1, cr6, {1} │ │ lsls r2, r2, #1 │ │ - adds r5, #225 @ 0xe1 │ │ + adds r6, #14 │ │ mcr2 3, 0, sl, cr1, cr10, {0} │ │ lsls r2, r2, #1 │ │ bvs.n 220db36 │ │ cdp2 3, 0, cr10, cr0, cr4, {0} │ │ lsls r2, r2, #1 │ │ - ldr r4, [r3, #84] @ 0x54 │ │ + ldr r1, [r1, #88] @ 0x58 │ │ cdp2 6, 0, cr12, cr2, cr10, {3} │ │ cdp2 2, 0, cr10, cr3, cr10, {7} │ │ lsls r2, r2, #1 │ │ - bl 206e7ae │ │ + bl 209b7ae ::operator()(char const*)@@Base+0xe> │ │ add r2, pc, #824 @ (adr r2, 220dee8 ) │ │ lsls r2, r2, #1 │ │ vmull.p64 , d11, d2 │ │ - str r5, [sp, #516] @ 0x204 │ │ + str r5, [sp, #696] @ 0x2b8 │ │ mcr2 2, 0, sl, cr1, cr2, {5} │ │ lsls r2, r2, #1 │ │ - asrs r7, r4, #13 │ │ + asrs r4, r2, #14 │ │ cdp2 15, 0, cr2, cr2, cr9, {7} │ │ mcr2 2, 0, sl, cr3, cr6, {4} │ │ lsls r2, r2, #1 │ │ - push {r1, r3} │ │ + push {r0, r1, r2, r4, r5} │ │ mcr2 2, 0, sl, cr1, cr14, {3} │ │ lsls r2, r2, #1 │ │ ldr r3, [sp, #416] @ 0x1a0 │ │ lsls r2, r2, #1 │ │ │ │ 0220dbd4 : │ │ push {r7, lr} │ │ @@ -591148,15 +591148,15 @@ │ │ mov r0, r4 │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ subs r0, #140 @ 0x8c │ │ lsls r0, r3, #1 │ │ ldr r3, [r6, #16] │ │ - mcr2 1, 0, r3, cr3, cr9, {0} │ │ + cdp2 1, 0, cr3, cr3, cr6, {2} │ │ cdp2 0, 0, cr10, cr2, cr4, {7} │ │ lsls r2, r2, #1 │ │ │ │ 0220dc90 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -591490,15 +591490,15 @@ │ │ b.n 220dfe0 │ │ add r0, sp, #36 @ 0x24 │ │ bl 20a6b1e ::loadExtras(celestia::util::array_view)@@Base+0x35a> │ │ blx 26ffb60 │ │ nop │ │ ldr r0, [sp, #168] @ 0xa8 │ │ lsls r2, r2, #1 │ │ - ldr r2, [pc, #848] @ (220e344 ) │ │ + ldr r3, [pc, #4] @ (220dff8 ) │ │ mcr2 3, 0, r8, cr2, cr4, {3} │ │ cdp2 15, 0, cr9, cr3, cr12, {0} │ │ lsls r2, r2, #1 │ │ str r6, [sp, #568] @ 0x238 │ │ lsls r2, r2, #1 │ │ │ │ 0220e000 : │ │ @@ -592379,31 +592379,31 @@ │ │ itt ne │ │ ldrne r0, [sp, #76] @ 0x4c │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ str r0, [sp, #920] @ 0x398 │ │ lsls r2, r2, #1 │ │ - lsrs r3, r1, #2 │ │ - mcr2 9, 0, r8, cr2, cr13, {7} @ │ │ - mcr2 7, 0, r0, cr1, cr4, {5} │ │ + lsrs r0, r7, #2 │ │ + vseleq.f32 s16, s4, s21 │ │ + cdp2 7, 0, cr0, cr1, cr1, {7} │ │ mcr2 15, 0, r5, cr2, cr4, {3} │ │ cdp2 12, 0, cr8, cr3, cr8, {1} │ │ - cdp2 3, 0, cr10, cr0, cr2, {7} │ │ - mcr2 3, 0, sl, cr2, cr12, {5} │ │ - cdp2 2, 0, cr8, cr2, cr1, {6} │ │ - mcr2 2, 0, r8, cr1, cr5, {5} │ │ + cdp2 4, 0, cr10, cr0, cr15, {0} │ │ + cdp2 3, 0, cr10, cr2, cr9, {7} │ │ + cdp2 2, 0, cr8, cr2, cr14, {7} │ │ + cdp2 2, 0, cr8, cr1, cr2, {7} │ │ mcr2 2, 0, r2, cr1, cr3, {6} │ │ - cdp2 12, 0, cr5, cr3, cr10, {0} │ │ - mcr2 11, 0, r5, cr2, cr14, {7} @ │ │ + mcr2 12, 0, r5, cr3, cr7, {1} │ │ + cdp2 12, 0, cr5, cr2, cr11, {1} │ │ mcr2 2, 0, r2, cr2, cr13, {5} │ │ mcr2 13, 0, r5, cr3, cr10, {5} │ │ vdot.bf16 d5, d19, d14[1] │ │ cdp2 2, 0, cr2, cr3, cr7, {5} │ │ - mcr2 2, 0, r8, cr3, cr15, {3} │ │ + cdp2 2, 0, cr8, cr3, cr12, {5} │ │ cdp2 14, 0, cr8, cr1, cr2, {1} │ │ lsls r2, r2, #1 │ │ │ │ 0220e8b0 : │ │ ldr r0, [pc, #16] @ (220e8c4 ) │ │ add r0, pc │ │ ldrb r1, [r0, #0] │ │ @@ -592463,15 +592463,15 @@ │ │ mov r2, r9 │ │ ldr.w r3, [r0, #680] @ 0x2a8 │ │ mov r0, r5 │ │ blx r3 │ │ mov r0, r6 │ │ ldmia.w sp!, {r8, r9, sl} │ │ pop {r4, r5, r6, r7, pc} │ │ - adds r5, r5, #5 │ │ + adds r2, r3, #6 │ │ Address 0x220e93e is out of bounds. │ │ │ │ │ │ 0220e940 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -592590,15 +592590,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #36] @ 0x24 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ ldrh r2, [r3, #38] @ 0x26 │ │ lsls r2, r2, #1 │ │ - adds r7, r6, #1 │ │ + adds r4, r4, #2 │ │ mcr2 10, 0, r0, cr1, cr0, {0} @ │ │ mcr2 11, 0, r8, cr4, cr4, {7} @ │ │ lsls r2, r2, #1 │ │ │ │ 0220ea74 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -596160,17 +596160,17 @@ │ │ b.n 2210c42 │ │ ldr r1, [pc, #20] @ (2210c54 ) │ │ mov r0, r5 │ │ add r1, pc │ │ ldr.w fp, [sp], #4 │ │ ldmia.w sp!, {r4, r5, r6, r7, lr} │ │ bx r2 │ │ - ldrsh r7, [r0, r1] │ │ + ldrsh r4, [r6, r1] │ │ mcr2 11, 0, r8, cr1, cr13, {1} @ │ │ - mcr2 11, 0, r5, cr3, cr3, {2} @ │ │ + vseleq.f64 d5, d19, d0 │ │ Address 0x2210c56 is out of bounds. │ │ │ │ │ │ 02210c58 : │ │ ldr r1, [sp, #0] │ │ mov r0, r2 │ │ b.w 26ff638 │ │ @@ -598206,18 +598206,18 @@ │ │ bcs.n 2212020 │ │ adds r6, r0, #1 │ │ lsls r1, r5, #1 │ │ strb.w r1, [sp, #108] @ 0x6c │ │ cbnz r5, 2212038 │ │ b.n 2212042 │ │ ldrb.w r0, [r2, r7, lsl #1] │ │ - cmp r1, #214 @ 0xd6 │ │ + cmp r2, #3 │ │ cdp2 12, 0, cr12, cr2, cr12, {7} │ │ mcr2 3, 0, r7, cr2, cr3, {6} │ │ - cdp2 0, 0, cr9, cr0, cr2, {0} │ │ + cdp2 0, 0, cr9, cr0, cr15, {1} │ │ cdp2 0, 0, cr15, cr1, cr5, {2} │ │ movs r7, r1 │ │ adds r4, r0, #1 │ │ mov r0, r4 │ │ blx 26ffbf0 │ │ mov r6, r0 │ │ orr.w r0, r4, #1 │ │ @@ -598533,16 +598533,16 @@ │ │ beq.n 22122ec │ │ ldr r0, [sp, #352] @ 0x160 │ │ blx 26ffb40 │ │ b.n 22122ec │ │ nop │ │ ldrsh r0, [r2, r1] │ │ lsls r2, r2, #1 │ │ - lsrs r1, r5, #4 │ │ - cdp2 2, 0, cr6, cr2, cr13, {3} │ │ + lsrs r6, r2, #5 │ │ + mcr2 2, 0, r6, cr2, cr10, {4} │ │ cdp2 4, 0, cr5, cr2, cr2, {5} │ │ lsls r2, r2, #1 │ │ │ │ 02212380 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void>::operator[](std::__ndk1::basic_string, std::__ndk1::allocator >)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -600176,16 +600176,16 @@ │ │ add.w sl, sp, #376 @ 0x178 │ │ mov.w r9, #0 │ │ strd r9, r9, [sp, #320] @ 0x140 │ │ b.n 22134da │ │ b.n 2213bd0 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void>::json_value::destroy(nlohmann::json_abi_v3_11_3::detail::value_t)@@Base+0x2bc> │ │ lsls r7, r2, #1 │ │ str r3, [r3, #4] │ │ - mcr2 6, 0, pc, cr0, cr15, {1} @ │ │ - mcr2 15, 0, r4, cr1, cr7, {4} │ │ + cdp2 6, 0, cr15, cr0, cr12, {3} │ │ + cdp2 15, 0, cr4, cr1, cr4, {6} │ │ vcmla.f16 d2, d2, d0[0], #0 │ │ itt ne │ │ ldrne r0, [sp, #312] @ 0x138 │ │ blxne 26ffb40 │ │ add.w r8, r8, #4 │ │ cmp r8, r4 │ │ beq.n 221357e │ │ @@ -600508,15 +600508,15 @@ │ │ blx 26ffb40 │ │ b.n 22137c0 │ │ nop │ │ ldr r0, [pc, #920] @ (2213bc8 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void>::json_value::destroy(nlohmann::json_abi_v3_11_3::detail::value_t)@@Base+0x2b4>) │ │ lsls r2, r2, #1 │ │ subs r7, #194 @ 0xc2 │ │ lsls r2, r2, #1 │ │ - adds r3, r3, #3 │ │ + adds r0, r1, #4 │ │ Address 0x2213836 is out of bounds. │ │ │ │ │ │ 02213838 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #48 @ 0x30 │ │ @@ -601400,15 +601400,15 @@ │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ bvc.n 2214098 <_ZN8nlohmann16json_abi_v3_11_36detail10type_error6createIPNS0_10basic_jsonINSt6__ndk13mapENS5_6vectorENS5_12basic_stringIcNS5_11char_traitsIcEENS5_9allocatorIcEEEEbxydSB_NS0_14adl_serializerENS7_IhNSB_IhEEEEvEETnNS5_9enable_ifIXsr21is_basic_json_contextIT_EE5valueEiE4typeELi0EEES2_iRKSD_SK_@@Base+0xa0> │ │ mcr2 6, 0, r3, cr3, cr14, {0} │ │ lsls r2, r2, #1 │ │ strh r6, [r6, #32] │ │ - mcr2 10, 0, r4, cr3, cr4, {3} @ │ │ + vseleq.f32 s8, s7, s3 │ │ cdp2 12, 0, cr3, cr2, cr10, {5} │ │ lsls r2, r2, #1 │ │ subs r4, #140 @ 0x8c │ │ lsls r2, r2, #1 │ │ adds r5, #66 @ 0x42 │ │ lsls r2, r2, #1 │ │ │ │ @@ -601456,15 +601456,15 @@ │ │ add r1, pc │ │ ldr.w r0, [r1, r0, lsl #2] │ │ bx lr │ │ ldr r0, [pc, #4] @ (22141e4 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void>::type_name() const@@Base+0x18>) │ │ add r0, pc │ │ bx lr │ │ nop │ │ - b.n 2214062 <_ZN8nlohmann16json_abi_v3_11_36detail10type_error6createIPNS0_10basic_jsonINSt6__ndk13mapENS5_6vectorENS5_12basic_stringIcNS5_11char_traitsIcEENS5_9allocatorIcEEEEbxydSB_NS0_14adl_serializerENS7_IhNSB_IhEEEEvEETnNS5_9enable_ifIXsr21is_basic_json_contextIT_EE5valueEiE4typeELi0EEES2_iRKSD_SK_@@Base+0x6a> │ │ + b.n 22140bc <_ZN8nlohmann16json_abi_v3_11_36detail10type_error6createIPNS0_10basic_jsonINSt6__ndk13mapENS5_6vectorENS5_12basic_stringIcNS5_11char_traitsIcEENS5_9allocatorIcEEEEbxydSB_NS0_14adl_serializerENS7_IhNSB_IhEEEEvEETnNS5_9enable_ifIXsr21is_basic_json_contextIT_EE5valueEiE4typeELi0EEES2_iRKSD_SK_@@Base+0xc4> │ │ vdot.bf16 , , d4[0] │ │ lsls r1, r2, #1 │ │ │ │ 022141ec : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ @@ -603073,27 +603073,27 @@ │ │ cmp r4, r0 │ │ beq.w 22153d8 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> >::dump(nlohmann::json_abi_v3_11_3::basic_json, std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> const&, bool, bool, unsigned int, unsigned int)@@Base+0x5f0> │ │ ldr r6, [r6, #0] │ │ add.w r5, r8, #8 │ │ mov.w r9, #41 @ 0x29 │ │ mov.w sl, #100 @ 0x64 │ │ b.n 2215238 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> >::dump(nlohmann::json_abi_v3_11_3::basic_json, std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> const&, bool, bool, unsigned int, unsigned int)@@Base+0x450> │ │ - bge.n 22150ee , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> >::dump(nlohmann::json_abi_v3_11_3::basic_json, std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> const&, bool, bool, unsigned int, unsigned int)@@Base+0x306> │ │ - cdp2 3, 0, cr9, cr0, cr10, {5} │ │ + bge.n 2215148 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> >::dump(nlohmann::json_abi_v3_11_3::basic_json, std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> const&, bool, bool, unsigned int, unsigned int)@@Base+0x360> │ │ + mcr2 3, 0, r9, cr0, cr7, {6} │ │ mcr2 9, 0, r3, cr1, cr9, {1} @ │ │ - cdp2 0, 0, cr4, cr3, cr11, {2} │ │ - mcr2 0, 0, r4, cr1, cr8, {0} │ │ + mcr2 0, 0, r4, cr3, cr8, {3} │ │ + cdp2 0, 0, cr4, cr1, cr5, {2} │ │ cdp2 15, 0, cr8, cr1, cr3, {6} │ │ mcr2 13, 0, sl, cr3, cr2, {2} │ │ cdp2 12, 0, cr2, cr3, cr12, {5} │ │ lsls r2, r2, #1 │ │ ldrh r5, [r6, #52] @ 0x34 │ │ mcr2 11, 0, r5, cr3, cr10, {7} @ │ │ - cdp2 12, 0, cr7, cr2, cr1, {2} │ │ - cdp2 14, 0, cr9, cr0, cr6, {7} │ │ + cdp2 12, 0, cr7, cr2, cr14, {3} │ │ + mcr2 15, 0, r9, cr0, cr3, {0} │ │ vfmal.f16 , d16, d0[1] │ │ movs r0, r0 │ │ ldr r1, [r0, #0] │ │ ldr r2, [r1, #0] │ │ movs r1, #48 @ 0x30 │ │ blx r2 │ │ ldr.w r0, [r8] │ │ @@ -603472,18 +603472,18 @@ │ │ ldr r2, [r0, #0] │ │ ldr r3, [r2, #4] │ │ mov r2, r9 │ │ b.n 22157ac , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> >::dump(nlohmann::json_abi_v3_11_3::basic_json, std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> const&, bool, bool, unsigned int, unsigned int)@@Base+0x9c4> │ │ ldmia r6!, {r1, r4, r5, r7} │ │ ldc2l 7, cr15, [pc, #84]! @ 2215648 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> >::dump(nlohmann::json_abi_v3_11_3::basic_json, std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> const&, bool, bool, unsigned int, unsigned int)@@Base+0x860> │ │ ldc2l 6, cr5, [pc, #460]! @ 22157c4 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> >::dump(nlohmann::json_abi_v3_11_3::basic_json, std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> const&, bool, bool, unsigned int, unsigned int)@@Base+0x9dc> │ │ - @ instruction: 0xfe00d941 │ │ + @ instruction: 0xfe00d96e │ │ vseleq.f16 s20, s1, s20 │ │ - @ instruction: 0xfe033ac8 │ │ - cdp2 7, 0, cr13, cr1, cr9, {7} │ │ + mcr2 10, 0, r3, cr3, cr5, {7} @ │ │ + vfmal.f16 d13, s2, s12[0] │ │ cdp2 7, 0, cr2, cr0, cr6, {7} │ │ lsls r2, r2, #1 │ │ movs r7, #154 @ 0x9a │ │ lsls r2, r2, #1 │ │ uxtb r2, r0 │ │ movs r3, #41 @ 0x29 │ │ muls r2, r3 │ │ @@ -603814,25 +603814,25 @@ │ │ b.w 2214e98 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> >::dump(nlohmann::json_abi_v3_11_3::basic_json, std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> const&, bool, bool, unsigned int, unsigned int)@@Base+0xb0> │ │ add.w r0, r8, #592 @ 0x250 │ │ lsls r1, r1, #1 │ │ movs r2, #32 │ │ blx 2703720 │ │ b.w 2214fd4 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> >::dump(nlohmann::json_abi_v3_11_3::basic_json, std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> const&, bool, bool, unsigned int, unsigned int)@@Base+0x1ec> │ │ nop │ │ - ldc2 14, cr15, [r9], {-0} │ │ + mcrr2 14, 0, pc, r6, cr0 @ │ │ adds r4, r4, #0 │ │ mcr2 5, 0, r2, cr0, cr12, {0} │ │ lsls r2, r2, #1 │ │ movs r4, #202 @ 0xca │ │ lsls r2, r2, #1 │ │ - bne.n 22159ba , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> >::dump(nlohmann::json_abi_v3_11_3::basic_json, std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> const&, bool, bool, unsigned int, unsigned int)@@Base+0xbd2> │ │ + bcs.n 2215a14 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> >::~serializer()@@Base+0x34> │ │ mcr2 9, 0, r8, cr0, cr13, {6} @ │ │ mcr2 4, 0, r2, cr3, cr2, {3} │ │ lsls r2, r2, #1 │ │ - lsrs r6, r5, #31 │ │ + asrs r3, r3, #32 │ │ Address 0x22159de is out of bounds. │ │ │ │ │ │ 022159e0 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> >::~serializer()@@Base>: │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ ldrb.w r1, [r0, #592] @ 0x250 │ │ @@ -604328,36 +604328,36 @@ │ │ blx 26ffb60 │ │ nop │ │ subs r6, r2, r6 │ │ lsls r2, r2, #1 │ │ ldr r1, [r0, #0] │ │ mcr2 5, 0, r3, cr3, cr13, {7} │ │ mcr2 12, 0, r2, cr0, cr2, {1} │ │ - vseleq.f32 s28, s0, s4 │ │ - cdp2 3, 0, cr9, cr1, cr1, {0} │ │ + vseleq.f32 s28, s0, s31 │ │ + cdp2 3, 0, cr9, cr1, cr14, {1} │ │ mcr2 15, 0, r1, cr0, cr8, {3} │ │ lsls r2, r2, #1 │ │ subs r2, r7, #5 │ │ lsls r2, r2, #1 │ │ adds r2, r2, r5 │ │ lsls r2, r2, #1 │ │ cmp r3, #182 @ 0xb6 │ │ - mcr2 9, 0, lr, cr0, cr13, {4} @ │ │ + @ instruction: 0xfe00e9ca │ │ mcr2 14, 0, r1, cr1, cr12, {7} │ │ lsls r2, r2, #1 │ │ subs r6, r7, #3 │ │ lsls r2, r2, #1 │ │ adds r2, r0, r4 │ │ lsls r2, r2, #1 │ │ adds r4, r3, r3 │ │ lsls r2, r2, #1 │ │ strh r3, [r1, r6] │ │ vcmla.f16 , q8, d6[0], #0 │ │ lsls r2, r2, #1 │ │ - add r0, sp, #440 @ 0x1b8 │ │ + add r0, sp, #620 @ 0x26c │ │ vseleq.f16 s2, s2, s9 │ │ lsls r2, r2, #1 │ │ │ │ 02215f04 <_ZN8nlohmann16json_abi_v3_11_36detail10serializerINS0_10basic_jsonINSt6__ndk13mapENS4_6vectorENS4_12basic_stringIcNS4_11char_traitsIcEENS4_9allocatorIcEEEEbxydSA_NS0_14adl_serializerENS6_IhNSA_IhEEEEvEEE12dump_integerIxTnNS4_9enable_ifIXoooooosr3std11is_integralIT_EE5valuesr3std7is_sameISK_yEE5valuesr3std7is_sameISK_xEE5valuesr3std7is_sameISK_hEE5valueEiE4typeELi0EEEvSK_@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -604618,15 +604618,15 @@ │ │ movs r0, r0 │ │ movs r0, r0 │ │ ldrb r0, [r6, #31] │ │ asrs r4, r5, #20 │ │ lsls r2, r2, #1 │ │ asrs r0, r6, #19 │ │ lsls r2, r2, #1 │ │ - stmia r7!, {r0, r1, r2, r3, r4, r6} │ │ + stmia r7!, {r2, r3, r7} │ │ mcr2 4, 0, r1, cr0, cr4, {3} │ │ lsls r2, r2, #1 │ │ push {r7, lr} │ │ mov r7, sp │ │ sub sp, #16 │ │ mov ip, r1 │ │ ldr r1, [pc, #48] @ (2216224 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> >::dump_float(double)@@Base+0x134>) │ │ @@ -604787,15 +604787,15 @@ │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ push {r1, r2, r3, r5, r6, lr} │ │ cdp2 3, 0, cr1, cr3, cr10, {7} │ │ lsls r2, r2, #1 │ │ str r2, [r0, #32] │ │ - vcmla.f16 q1, , d0[0], #0 │ │ + vcmla.f16 q1, , d13[1], #0 │ │ mcr2 10, 0, r1, cr2, cr6, {3} @ │ │ lsls r2, r2, #1 │ │ subs r0, r3, r1 │ │ lsls r2, r2, #1 │ │ asrs r6, r1, #12 │ │ lsls r2, r2, #1 │ │ │ │ @@ -608201,17 +608201,17 @@ │ │ itt ne │ │ strne r0, [sp, #160] @ 0xa0 │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ bl 207deaa │ │ nop │ │ orr.w r0, r0, #13697024 @ 0xd10000 │ │ - beq.n 22184a2 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void>& nlohmann::json_abi_v3_11_3::basic_json, std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void>::operator[](char const*)@@Base+0x22> │ │ - mcr2 0, 0, sp, cr0, cr12, {0} │ │ - vdot.bf16 d14, d16, d7[1] │ │ + beq.n 22184fc , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void>& nlohmann::json_abi_v3_11_3::basic_json, std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void>::operator[](char const*)@@Base+0x7c> │ │ + cdp2 0, 0, cr13, cr0, cr9, {2} │ │ + mcr2 13, 0, lr, cr0, cr4, {6} │ │ mcr2 14, 0, r5, cr0, cr2, {7} │ │ cdp2 2, 0, cr15, cr3, cr8, {2} │ │ lsls r1, r2, #1 │ │ │ │ 02218480 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void>& nlohmann::json_abi_v3_11_3::basic_json, std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void>::operator[](char const*)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -608372,15 +608372,15 @@ │ │ blxne 26ffb40 │ │ cbnz r6, 2218606 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void>::push_back(nlohmann::json_abi_v3_11_3::basic_json, std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> const&)@@Base+0xd6> │ │ blx 26ffb60 │ │ mov r0, r4 │ │ blx 26ffc20 │ │ blx 26ffb60 │ │ @ instruction: 0xf0f00051 │ │ - ldr r3, [pc, #56] @ (2218650 ) │ │ + ldr r3, [pc, #236] @ (2218704 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void>::basic_json(std::initializer_list, std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void> > >, bool, nlohmann::json_abi_v3_11_3::detail::value_t)@@Base+0x50>) │ │ cdp2 7, 0, cr15, cr1, cr14, {3} │ │ lsls r1, r2, #1 │ │ @ instruction: 0xf7700051 │ │ eors.w r0, sl, #81 @ 0x51 │ │ │ │ 02218624 : │ │ ldrb r0, [r0, #4] │ │ @@ -608733,15 +608733,15 @@ │ │ cbnz r6, 2218992 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void>::operator[](unsigned int) const@@Base+0x92> │ │ b.n 2218998 , std::__ndk1::allocator >, bool, long long, unsigned long long, double, std::__ndk1::allocator, nlohmann::json_abi_v3_11_3::adl_serializer, std::__ndk1::vector >, void>::operator[](unsigned int) const@@Base+0x98> │ │ mov r0, r4 │ │ blx 26ffc20 │ │ blx 26ffb60 │ │ stc 0, cr0, [r0, #-324]! @ 0xfffffebc │ │ stc 0, cr0, [sl, #-324] @ 0xfffffebc │ │ - lsls r1, r6, #5 │ │ + lsls r6, r3, #6 │ │ mcr2 3, 0, pc, cr2, cr10, {6} @ │ │ lsls r1, r2, #1 │ │ @ instruction: 0xf3dc0051 │ │ │ │ 022189b0 <_ZN8nlohmann16json_abi_v3_11_36detail10type_error6createIPKNS0_10basic_jsonINSt6__ndk13mapENS5_6vectorENS5_12basic_stringIcNS5_11char_traitsIcEENS5_9allocatorIcEEEEbxydSB_NS0_14adl_serializerENS7_IhNSB_IhEEEEvEETnNS5_9enable_ifIXsr21is_basic_json_contextIT_EE5valueEiE4typeELi0EEES2_iRKSD_SL_@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -608873,15 +608873,15 @@ │ │ blx 26ffb40 │ │ blx 26ffb60 │ │ nop │ │ ldrh r2, [r5, #46] @ 0x2e │ │ cdp2 12, 0, cr14, cr3, cr6, {3} │ │ lsls r1, r2, #1 │ │ subs r2, #126 @ 0x7e │ │ - mcr2 0, 0, r0, cr3, cr12, {5} │ │ + cdp2 0, 0, cr0, cr3, cr9, {7} │ │ mcr2 2, 0, pc, cr2, cr2, {7} @ │ │ lsls r1, r2, #1 │ │ @ instruction: 0xf2d40051 │ │ @ instruction: 0xeb8a0051 │ │ │ │ 02218b24 , std::__ndk1::allocator > nlohmann::json_abi_v3_11_3::detail::concat, std::__ndk1::allocator >, char const (&) [52], char const*>(char const (&) [52], char const*&&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -610047,73 +610047,73 @@ │ │ mov r0, r4 │ │ blx 270aa80 │ │ b.n 22195ea │ │ @ instruction: 0xead80051 │ │ @ instruction: 0xeac40051 │ │ @ instruction: 0xeaa20051 │ │ orns r0, sl, r1, lsr #1 │ │ - bmi.n 2219730 │ │ + bmi.n 221958a │ │ mcr2 1, 0, r3, cr1, cr8, {4} │ │ mcr2 3, 0, lr, cr3, cr6, {4} │ │ lsls r1, r2, #1 │ │ strh r0, [r6, #54] @ 0x36 │ │ cdp2 7, 0, cr8, cr8, cr10, {1} │ │ - cdp2 4, 0, cr13, cr8, cr8, {1} │ │ + mcr2 4, 0, sp, cr8, cr5, {2} │ │ mcr2 15, 0, pc, cr1, cr12, {1} @ │ │ ldc2l 9, cr14, [pc, #488]! @ 221983c @ │ │ lsls r1, r2, #1 │ │ strd r0, r0, [r4], #324 @ 0x144 │ │ - bcs.n 2219628 │ │ + bcc.n 2219682 │ │ mcr2 13, 0, sp, cr1, cr2, {7} │ │ ldc2l 9, cr14, [pc, #456]! @ 221982c @ │ │ lsls r1, r2, #1 │ │ @ instruction: 0xe8c80051 │ │ - bcs.n 2219604 │ │ + bcs.n 221965e │ │ cdp2 6, 0, cr5, cr1, cr8, {3} │ │ - cdp2 6, 0, cr9, cr2, cr12, {7} │ │ + mcr2 7, 0, r9, cr2, cr9, {0} │ │ mcr2 7, 0, lr, cr0, cr8, {6} │ │ lsls r1, r2, #1 │ │ b.n 2219640 │ │ lsls r1, r2, #1 │ │ b.n 22195fc │ │ lsls r1, r2, #1 │ │ b.n 2219618 │ │ lsls r1, r2, #1 │ │ ldrd r0, r0, [r4, #324] @ 0x144 │ │ strd r0, r0, [ip, #324] @ 0x144 │ │ b.n 221959c │ │ lsls r1, r2, #1 │ │ - bne.n 22195a0 │ │ + bne.n 22195fa │ │ mcr2 14, 0, r2, cr1, cr14, {3} │ │ vcmla.f16 d14, d3, d10[1], #0 │ │ lsls r1, r2, #1 │ │ - bcs.n 22196fc │ │ + bcs.n 2219756 │ │ cdp2 12, 0, cr12, cr1, cr0, {2} │ │ vfmal.f16 d14, s4, s8[0] │ │ lsls r1, r2, #1 │ │ - bcs.n 22196dc │ │ + bcs.n 2219736 │ │ mcr2 15, 0, r2, cr1, cr0, {0} │ │ vcmla.f16 d14, d19, d6[1], #0 │ │ lsls r1, r2, #1 │ │ strh r6, [r4, #44] @ 0x2c │ │ vcmla.f16 q7, q4, d0[1], #0 │ │ lsls r1, r2, #1 │ │ - bcs.n 2219784 │ │ + bcs.n 22195de │ │ mcr2 12, 0, ip, cr1, cr11, {4} │ │ - mcr2 7, 0, r9, cr2, cr8, {1} │ │ + cdp2 7, 0, cr9, cr2, cr5, {3} │ │ vcmla.f16 d14, d0, d6[1], #0 │ │ lsls r1, r2, #1 │ │ stmdb r6!, {r0, r4, r6} │ │ stmdb r2, {r0, r4, r6} │ │ stmdb lr, {r0, r4, r6} │ │ ldrd r0, r0, [r6, #-324] @ 0x144 │ │ - bcc.n 2219790 │ │ + bcc.n 22195ea │ │ cdp2 12, 0, cr1, cr1, cr8, {5} │ │ - vcmla.f16 d9, d0, d14[1], #0 │ │ - mcr2 9, 0, r9, cr0, cr2, {2} @ │ │ + vfmal.f16 , d0, d3[1] │ │ + mcr2 9, 0, r9, cr0, cr15, {3} @ │ │ mcr2 0, 0, lr, cr0, cr12, {1} │ │ lsls r1, r2, #1 │ │ │ │ 022196f4 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ ldr r1, [pc, #92] @ (2219758 ) │ │ @@ -610156,16 +610156,16 @@ │ │ ldr r1, [r1, #0] │ │ blx r1 │ │ movs r0, #0 │ │ strd r0, r0, [r4, #64] @ 0x40 │ │ strd r0, r0, [r4, #16] │ │ str r0, [r4, #24] │ │ pop {r4, r6, r7, pc} │ │ - beq.n 2219694 │ │ - cdp2 5, 0, cr9, cr1, cr2, {4} │ │ + beq.n 22196ee │ │ + cdp2 5, 0, cr9, cr1, cr15, {5} │ │ cdp2 6, 0, cr14, cr0, cr14, {3} │ │ lsls r1, r2, #1 │ │ b.n 2219450 │ │ lsls r1, r2, #1 │ │ b.n 221940c │ │ lsls r1, r2, #1 │ │ b.n 2219428 │ │ @@ -610352,15 +610352,15 @@ │ │ lsls r1, r2, #1 │ │ b.n 2219470 │ │ lsls r1, r2, #1 │ │ b.n 2219364 │ │ lsls r1, r2, #1 │ │ b.n 2219280 │ │ lsls r1, r2, #1 │ │ - ldmia r6!, {r1, r3, r5, r7} │ │ + ldmia r6, {r0, r1, r2, r4, r6, r7} │ │ cdp2 2, 0, cr9, cr1, cr10, {6} │ │ Address 0x2219932 is out of bounds. │ │ │ │ │ │ 02219934 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -610464,16 +610464,16 @@ │ │ ldr.w r8, [sp], #4 │ │ ldmia.w sp!, {r4, r5, r6, r7, lr} │ │ b.w 26fea38 │ │ b.n 221a198 │ │ lsls r1, r2, #1 │ │ b.n 221a184 │ │ lsls r1, r2, #1 │ │ - ldmia r5, {r1, r2, r5, r7} │ │ - mcr2 2, 0, r9, cr1, cr15, {4} │ │ + ldmia r5!, {r0, r1, r4, r6, r7} │ │ + cdp2 2, 0, cr9, cr1, cr12, {6} │ │ Address 0x2219a3e is out of bounds. │ │ │ │ │ │ 02219a40 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -610592,19 +610592,19 @@ │ │ ldr r0, [r4, #0] │ │ ldr r1, [r2, #0] │ │ ldr.w r2, [r0, #876] @ 0x36c │ │ mov r0, r4 │ │ ldr.w fp, [sp], #4 │ │ ldmia.w sp!, {r4, r5, r6, r7, lr} │ │ bx r2 │ │ - adds r2, #76 @ 0x4c │ │ - mcr2 7, 0, fp, cr0, cr11, {2} │ │ + adds r2, #121 @ 0x79 │ │ + cdp2 7, 0, cr11, cr0, cr8, {4} │ │ cdp2 2, 0, cr14, cr0, cr6, {4} │ │ lsls r1, r2, #1 │ │ - bmi.n 2219b1e │ │ + bpl.n 2219b78 │ │ cdp2 5, 0, cr1, cr0, cr3, {5} │ │ cdp2 2, 0, cr14, cr0, cr12, {3} │ │ lsls r1, r2, #1 │ │ b.n 221a048 │ │ lsls r1, r2, #1 │ │ │ │ 02219b84 : │ │ @@ -610648,16 +610648,16 @@ │ │ movs r1, #0 │ │ mov r3, r4 │ │ add r0, pc │ │ ldr r2, [r0, #0] │ │ add.w r0, r4, #44 @ 0x2c │ │ ldmia.w sp!, {r4, r6, r7, lr} │ │ b.w 26ff6ec │ │ - ldmia r3, {r3, r5, r6, r7} │ │ - vdot.bf16 q4, , d12[1] │ │ + ldmia r4, {r0, r2, r4} │ │ + mcr2 13, 0, r8, cr1, cr9, {4} │ │ cdp2 1, 0, cr14, cr1, cr12, {6} │ │ lsls r1, r2, #1 │ │ │ │ 02219bfc : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -610687,16 +610687,16 @@ │ │ movs r0, #4 │ │ mov r1, r4 │ │ add r2, pc │ │ blx 270aa70 │ │ ldr.w fp, [sp], #4 │ │ ldmia.w sp!, {r4, r5, r6, r7, lr} │ │ b.w 26ff710 │ │ - ldmia r3!, {r4, r7} │ │ - mcr2 3, 0, r1, cr1, cr8, {2} │ │ + ldmia r3, {r0, r2, r3, r4, r5, r7} │ │ + cdp2 3, 0, cr1, cr1, cr5, {4} │ │ mcr2 15, 0, r8, cr1, cr10, {4} │ │ Address 0x2219c62 is out of bounds. │ │ │ │ │ │ 02219c64 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -611155,16 +611155,16 @@ │ │ lsls r7, r2, #1 │ │ bhi.n 221a190 │ │ lsls r1, r2, #1 │ │ strb r2, [r4, #27] │ │ lsls r7, r2, #1 │ │ bvc.n 221a024 │ │ lsls r1, r2, #1 │ │ - add r0, sp, #424 @ 0x1a8 │ │ - vfmal.f16 q5, d1, d6[0] │ │ + add r0, sp, #604 @ 0x25c │ │ + vcmla.f16 d10, d17, d3[0], #0 │ │ cdp2 12, 0, cr13, cr1, cr14, {5} │ │ lsls r1, r2, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #68 @ 0x44 │ │ mov r6, r0 │ │ @@ -612026,15 +612026,15 @@ │ │ bl 221be70 │ │ b.n 221a908 │ │ ldr r0, [pc, #8] @ (221aa08 ) │ │ add r0, pc │ │ bl 221a388 │ │ ldmia r5, {r2, r5, r6} │ │ lsls r1, r2, #1 │ │ - subs r0, #195 @ 0xc3 │ │ + subs r0, #240 @ 0xf0 │ │ vdot.bf16 d12, d0, d0[1] │ │ lsls r1, r2, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub.w sp, sp, #560 @ 0x230 │ │ mov r4, r0 │ │ @@ -612110,15 +612110,15 @@ │ │ cmp r0, r6 │ │ it ne │ │ blxne 26ffb40 │ │ blx 26ffb60 │ │ str r3, [sp, #396] @ 0x18c │ │ vmull.u32 q14, d7, d2 │ │ lsls r1, r2, #1 │ │ - movs r2, #224 @ 0xe0 │ │ + movs r3, #13 │ │ mcr2 3, 0, sp, cr0, cr0, {0} │ │ lsls r1, r2, #1 │ │ bcc.n 221ab04 │ │ lsls r1, r2, #1 │ │ ldmia r3!, {r1, r2, r4, r5, r7} │ │ lsls r1, r2, #1 │ │ push {r4, r6, r7, lr} │ │ @@ -613560,15 +613560,15 @@ │ │ pop {r4, r5, r6, r7, pc} │ │ ldr.w r2, [r9, #16] │ │ add.w r1, sl, r4 │ │ mov r0, sl │ │ ldmia.w sp!, {r8, r9, sl} │ │ ldmia.w sp!, {r4, r5, r6, r7, lr} │ │ b.w 209b634 │ │ - bl 1e6b7b4 │ │ + bl 1e987b4 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #60] @ (221bbf8 ) │ │ ldrb.w r1, [r4, #32] │ │ add r0, pc │ │ adds r0, #8 │ │ @@ -613739,15 +613739,15 @@ │ │ movs r0, r0 │ │ movs r0, #0 │ │ movs r0, r0 │ │ lsls r0, r0, #4 │ │ ldr r2, [r1, #16] │ │ mcr2 9, 0, fp, cr3, cr8, {3} @ │ │ lsls r1, r2, #1 │ │ - ldmdb r6!, {r9, sl, fp, ip, sp, lr, pc} │ │ + strd pc, lr, [r3, #-0]! │ │ stmia r0!, {r1, r2, r3, r4, r6} │ │ vfmal.f16 , d18, d6[2] │ │ lsls r1, r2, #1 │ │ bmi.n 221bd20 │ │ bmi.n 221bd22 │ │ bmi.n 221bd24 │ │ bmi.n 221bd26 │ │ @@ -613834,15 +613834,15 @@ │ │ movs r0, r0 │ │ movs r0, #0 │ │ movs r0, r0 │ │ lsls r0, r0, #4 │ │ ldr r6, [r2, #0] │ │ vcmla.f16 d11, d19, d4[0], #0 │ │ lsls r1, r2, #1 │ │ - tt lr, r8 │ │ + ldrd pc, lr, [r5], #-0 │ │ ite vs │ │ vcmlavs.f16 d11, d2, d2[0], #0 │ │ lslvc r1, r2, #1 │ │ bmi.n 221be10 │ │ bmi.n 221be12 │ │ bmi.n 221be14 │ │ bmi.n 221be16 │ │ @@ -613929,15 +613929,15 @@ │ │ movs r0, r0 │ │ movs r0, #0 │ │ movs r0, r0 │ │ lsls r0, r0, #4 │ │ str r6, [r4, #112] @ 0x70 │ │ mcr2 7, 0, fp, cr3, cr4, {4} │ │ lsls r1, r2, #1 │ │ - b.n 221bdfc │ │ + b.n 221be56 │ │ mcr2 14, 0, fp, cr0, cr12, {3} │ │ mcr2 7, 0, fp, cr2, cr2, {0} │ │ lsls r1, r2, #1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ cbz r1, 221bf72 │ │ ldr r5, [r0, #0] │ │ @@ -617443,26 +617443,26 @@ │ │ @ instruction: 0xffffffff │ │ movs r0, r0 │ │ movs r0, #0 │ │ movs r0, r0 │ │ lsls r0, r0, #4 │ │ str r7, [sp, #360] @ 0x168 │ │ lsls r1, r2, #1 │ │ - @ instruction: 0xff33fdff │ │ + @ instruction: 0xff60fdff │ │ muls r4, r6 │ │ - cdp2 3, 0, cr12, cr3, cr12, {5} │ │ + mcr2 3, 0, ip, cr3, cr9, {6} │ │ mcr2 10, 0, r9, cr0, cr4, {6} @ │ │ mcr2 5, 0, r4, cr2, cr10, {2} │ │ - mcr2 5, 0, ip, cr3, cr12, {4} │ │ + cdp2 5, 0, cr12, cr3, cr9, {6} │ │ cdp2 12, 0, cr9, cr0, cr0, {6} │ │ mcr2 6, 0, r6, cr2, cr0, {0} │ │ ldc2l 2, cr9, [pc, #768]! @ 221e6e4 │ │ lsls r1, r2, #1 │ │ - cdp2 14, 1, cr15, cr10, cr0, {0} │ │ - add r3, pc, #520 @ (adr r3, 221e5f8 ) │ │ + cdp2 14, 4, cr15, cr7, cr0, {0} │ │ + add r3, pc, #700 @ (adr r3, 221e6ac ) │ │ @ instruction: 0xfe00c965 │ │ mcr2 5, 0, fp, cr1, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #92 @ 0x5c │ │ mov r4, r0 │ │ ldr.w r0, [pc, #984] @ 221e7dc │ │ @@ -617828,15 +617828,15 @@ │ │ bl 221a388 │ │ ldr r0, [pc, #36] @ (221e7f8 ) │ │ add r0, pc │ │ bl 221a388 │ │ nop │ │ str r2, [sp, #160] @ 0xa0 │ │ lsls r1, r2, #1 │ │ - @ instruction: 0xfafdfdff │ │ + @ instruction: 0xfb2afdff │ │ subs r7, #158 @ 0x9e │ │ mcr2 15, 0, r3, cr3, cr2, {7} │ │ cdp2 14, 0, cr3, cr3, cr10, {6} │ │ cdp2 1, 0, cr9, cr3, cr0, {5} │ │ lsls r1, r2, #1 │ │ str r2, [r4, #28] │ │ ldc2l 5, cr12, [pc, #220]! @ 221e8d4 │ │ @@ -617987,17 +617987,17 @@ │ │ pop {r4, r5, r6, r7, pc} │ │ ldr r0, [pc, #16] @ (221e98c ) │ │ add r0, pc │ │ bl 221a388 │ │ ldr r0, [pc, #12] @ (221e990 ) │ │ add r0, pc │ │ bl 221a388 │ │ - ldr??.w pc, [r7, #3583] @ 0xdff │ │ - strht pc, [r6] │ │ - cbnz r6, 221ea10 │ │ + @ instruction: 0xfa24fdff │ │ + ldrt pc, [r3] │ │ + pop {r0, r1, r5} │ │ mcr2 5, 0, fp, cr0, cr0, {7} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ sub sp, #80 @ 0x50 │ │ mov r6, r0 │ │ ldr r0, [pc, #308] @ (221ead8 ) │ │ mov r4, r1 │ │ @@ -809696,21 +809696,21 @@ │ │ cdp2 1, 0, cr11, cr1, cr12, {2} │ │ cdp2 1, 0, cr11, cr1, cr0, {5} │ │ mcr2 0, 0, fp, cr1, cr12, {0} │ │ mcr2 0, 0, fp, cr1, cr4, {4} │ │ mcr2 0, 0, fp, cr1, cr8, {3} │ │ cdp2 12, 0, cr3, cr1, cr8, {2} │ │ lsls r3, r1, #1 │ │ - bl 265937c │ │ + bl 268637c │ │ lsrs r4, r4, #7 │ │ lsls r3, r1, #1 │ │ stmia r0!, {r1, r2, r3, r5, r7} │ │ - cdp2 3, 0, cr13, cr2, cr8, {7} │ │ + mcr2 4, 0, sp, cr2, cr5, {0} │ │ ldc2l 3, cr12, [sl, #904]! @ 0x388 │ │ - mcr2 10, 0, r1, cr2, cr2, {3} @ │ │ + mcr2 10, 0, r1, cr2, cr15, {4} @ │ │ ldc2l 8, cr4, [sl, #192]! @ 0xc0 │ │ stmdb sp!, {r3, ip, sp, pc} │ │ b.n 2287cc0 │ │ movs r0, #64 @ 0x40 │ │ b.n 22872e8 │ │ eors r0, r0 │ │ b.n 22872ec │ │ @@ -817256,21 +817256,21 @@ │ │ adds.w ip, r1, sl, asr #12 │ │ mcr2 12, 0, r3, cr3, cr8, {4} │ │ mcr2 13, 0, r2, cr3, cr0, {6} │ │ vdot.bf16 d2, d19, d12[0] │ │ vfmal.f16 , d3, d0[0] │ │ lsls r2, r1, #1 │ │ @ instruction: 0xf784004a │ │ - add r7, sp, #100 @ 0x64 │ │ + add r7, sp, #280 @ 0x118 │ │ ldc2l 5, cr12, [sl, #176]! @ 0xb0 │ │ lsls r2, r1, #1 │ │ subs r2, #34 @ 0x22 │ │ - mcr2 15, 0, r8, cr3, cr0, {1} │ │ + mcr2 15, 0, r8, cr3, cr13, {2} │ │ ldc2l 10, cr3, [sl, #560]! @ 0x230 @ │ │ - mcr2 5, 0, sp, cr3, cr14, {5} │ │ + cdp2 5, 0, cr13, cr3, cr11, {7} │ │ Address 0x228b93e is out of bounds. │ │ │ │ │ │ 0228b940 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #8 │ │ @@ -817381,15 +817381,15 @@ │ │ ldr r0, [r0] │ │ bl 270ac10 │ │ bl 2707fc0 │ │ mov r0, #0 │ │ sub sp, fp, #8 │ │ pop {r4, sl, fp, pc} │ │ ldrdeq ip, [sl], #-8 │ │ - ldc2l 5, cr5, [r9, #212]! @ 0xd4 │ │ + ldc2l 5, cr5, [r9, #392]! @ 0x188 │ │ ldc2l 1, cr7, [r8, #96]! @ 0x60 │ │ ldrdeq ip, [sl], #-40 @ 0xffffffd8 │ │ │ │ 0228bb0c : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #8 │ │ @@ -817437,15 +817437,15 @@ │ │ add r1, pc, r1 │ │ ldr r0, [pc, r0] │ │ ldr r0, [r0] │ │ bl 270ac10 │ │ bl 2707fc0 │ │ subseq r5, r0, ip, asr sl │ │ subeq ip, sl, r8 │ │ - ldc2l 4, cr5, [r9, #404]! @ 0x194 │ │ + ldc2l 4, cr5, [r9, #584]! @ 0x248 │ │ ldc2l 0, cr7, [r8, #224]! @ 0xe0 │ │ strdeq ip, [sl], #-24 @ 0xffffffe8 │ │ │ │ 0228bbe4 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #8 │ │ @@ -817526,17 +817526,17 @@ │ │ ldr r0, [pc, #44] @ 228bd4c │ │ add r1, pc, r1 │ │ ldr r0, [pc, r0] │ │ ldr r0, [r0] │ │ bl 270ac10 │ │ bl 2707fc0 │ │ subeq fp, sl, ip, asr #30 │ │ - ldc2l 3, cr5, [r9, #692]! @ 0x2b4 │ │ - ldc2l 3, cr11, [r9, #712]! @ 0x2c8 │ │ - ldc2l 3, cr5, [r9, #180]! @ 0xb4 │ │ + ldc2l 3, cr5, [r9, #872]! @ 0x368 │ │ + ldc2l 3, cr11, [r9, #892]! @ 0x37c │ │ + ldc2l 3, cr5, [r9, #360]! @ 0x168 │ │ ldc2l 14, cr6, [r8, #992]! @ 0x3e0 │ │ strheq ip, [sl], #-8 │ │ ldc2l 14, cr6, [r8, #864]! @ 0x360 │ │ umaaleq ip, sl, r8, r0 │ │ │ │ 0228bd50 : │ │ mov r1, #0 │ │ @@ -817684,15 +817684,15 @@ │ │ ldr r0, [pc, #36] @ 228bf9c │ │ add r1, pc, r1 │ │ ldr r0, [pc, r0] │ │ ldr r0, [r0] │ │ bl 270ac10 │ │ bl 2707fc0 │ │ subeq fp, sl, r0, asr #26 │ │ - ldc2l 1, cr5, [r9, #644]! @ 0x284 │ │ + ldc2l 1, cr5, [r9, #824]! @ 0x338 │ │ subeq fp, sl, ip, asr #24 │ │ umaaleq sp, sl, r0, r0 │ │ ldc2l 12, cr6, [r8, #512]! @ 0x200 │ │ subeq fp, sl, r0, asr #28 │ │ │ │ 0228bfa0 : │ │ ldr r1, [pc, #24] @ 228bfc0 │ │ @@ -817801,15 +817801,15 @@ │ │ add r1, pc, r1 │ │ ldr r0, [pc, r0] │ │ ldr r0, [r0] │ │ bl 270ac10 │ │ bl 2707fc0 │ │ subseq r5, r0, ip, lsr #9 │ │ ldc2l 6, cr12, [fp, #756]! @ 0x2f4 │ │ - ldc2l 13, cr12, [r9, #900]! @ 0x384 │ │ + ldc2l 14, cr12, [r9, #56]! @ 0x38 │ │ subeq fp, sl, r8, lsl #25 │ │ │ │ 0228c150 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ ldr r5, [pc, #196] @ 228c224 │ │ mov r4, r0 │ │ @@ -817863,15 +817863,15 @@ │ │ bl 270ac10 │ │ bl 2707fc0 │ │ subseq r5, r0, r8, lsl r4 │ │ ldc2l 6, cr12, [fp, #20]! │ │ subeq fp, sl, r0, asr #23 │ │ ldc2l 7, cr8, [r8, #716]! @ 0x2cc │ │ ldc2l 5, cr12, [fp, #484]! @ 0x1e4 │ │ - ldc2l 13, cr12, [r9, #212]! @ 0xd4 │ │ + ldc2l 13, cr12, [r9, #392]! @ 0x188 │ │ ldrdeq fp, [sl], #-188 @ 0xffffff44 │ │ │ │ 0228c240 : │ │ mov r0, #0 │ │ bx lr │ │ │ │ 0228c248 : │ │ @@ -817927,19 +817927,19 @@ │ │ add r1, pc, r1 │ │ add r2, pc, r2 │ │ ldr r0, [pc, r0] │ │ ldr r0, [r0] │ │ bl 270ac10 │ │ bl 2707fc0 │ │ subseq r5, r0, r0, lsr #6 │ │ - ldc2l 8, cr12, [sl, #364]! @ 0x16c │ │ + vcmla.f32 d28, d26, d8, #270 │ │ ldc2l 6, cr8, [r8, #836]! @ 0x344 │ │ - ldc2l 7, cr12, [sl, #908]! @ 0x38c │ │ + ldc2l 8, cr12, [sl, #64]! @ 0x40 │ │ subeq fp, sl, r4, lsr #21 │ │ - ldc2l 12, cr12, [r9, #132]! @ 0x84 │ │ + ldc2l 12, cr12, [r9, #312]! @ 0x138 │ │ subeq fp, sl, r8, asr #21 │ │ │ │ 0228c340 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ ldr r5, [pc, #180] @ 228c404 │ │ mov r4, r0 │ │ @@ -817985,19 +817985,19 @@ │ │ ldr r2, [pc, #32] @ 228c414 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ add r2, pc, r2 │ │ bl 270ac10 │ │ bl 2707fc0 │ │ subseq r5, r0, r8, lsr #4 │ │ - ldc2l 13, cr2, [r9, #168]! @ 0xa8 │ │ + ldc2l 13, cr2, [r9, #348]! @ 0x15c │ │ subeq fp, sl, r0, ror #19 │ │ ldc2l 5, cr8, [r8, #844]! @ 0x34c │ │ - ldc2l 12, cr2, [r9, #696]! @ 0x2b8 │ │ - ldc2l 11, cr12, [r9, #308]! @ 0x134 @ │ │ + ldc2l 12, cr2, [r9, #876]! @ 0x36c │ │ + ldc2l 11, cr12, [r9, #488]! @ 0x1e8 @ │ │ strdeq fp, [sl], #-148 @ 0xffffff6c │ │ │ │ 0228c420 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r4, r0 │ │ @@ -818092,19 +818092,19 @@ │ │ ldr r2, [pc, #32] @ 228c5b0 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ add r2, pc, r2 │ │ bl 270ac10 │ │ bl 2707fc0 │ │ subseq r5, r0, ip, lsl #1 │ │ - ldc2l 5, cr12, [sl, #876]! @ 0x36c │ │ + ldc2l 6, cr12, [sl, #32]! │ │ subeq fp, sl, r4, asr #16 │ │ ldc2l 4, cr8, [r8, #220]! @ 0xdc │ │ - ldc2l 5, cr12, [sl, #380]! @ 0x17c │ │ - ldc2l 9, cr12, [r9, #354]! @ 0x162 @ │ │ + ldc2l 5, cr12, [sl, #560]! @ 0x230 │ │ + ldc2l 9, cr12, [r9, #444]! @ 0x1bc @ │ │ subeq fp, sl, r8, asr r8 │ │ │ │ 0228c5bc : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ ldr r5, [pc, #268] @ 228c6dc │ │ @@ -818173,15 +818173,15 @@ │ │ ldr r0, [pc, r0] │ │ ldr r0, [r0] │ │ blx r0 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ subseq r4, r0, r8, lsr #31 │ │ - ldc2l 4, cr12, [sl, #988]! @ 0x3dc │ │ + ldc2l 5, cr12, [sl, #144]! @ 0x90 │ │ subeq lr, sl, r8, lsr #21 │ │ subeq lr, sl, r4, lsr sl │ │ subeq lr, sl, ip, lsl sl │ │ subeq fp, sl, r4, asr #13 │ │ subeq lr, sl, r0, lsl sl │ │ │ │ 0228c6f8 : │ │ @@ -818434,15 +818434,15 @@ │ │ mov r0, #0 │ │ mov sp, fp │ │ pop {fp, pc} │ │ subeq lr, sl, ip, asr r6 │ │ subeq lr, sl, r4, lsl #14 │ │ ldc2l 10, cr15, [fp, #460]! @ 0x1cc @ │ │ ldc2l 10, cr7, [fp, #968]! @ 0x3c8 @ │ │ - ldc2l 4, cr12, [r9, #516]! @ 0x204 │ │ + ldc2l 4, cr12, [r9, #696]! @ 0x2b8 │ │ ldc2l 7, cr9, [fp, #344]! @ 0x158 │ │ │ │ 0228cadc : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #8 │ │ ldr r1, [pc, #112] @ 228cb60 │ │ @@ -818474,15 +818474,15 @@ │ │ bl 270ad80 │ │ mov r0, #0 │ │ mov sp, fp │ │ pop {fp, pc} │ │ subeq lr, sl, ip, asr r6 │ │ ldc2l 9, cr15, [fp, #406]! @ 0x196 @ │ │ ldc2l 10, cr7, [fp, #296]! @ 0x128 @ │ │ - ldc2l 3, cr12, [r9, #868]! @ 0x364 │ │ + ldc2l 4, cr12, [r9, #24]! │ │ ldc2l 6, cr9, [fp, #696]! @ 0x2b8 │ │ │ │ 0228cb74 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #80] @ 228cbd8 │ │ @@ -820052,15 +820052,15 @@ │ │ b 228d47c │ │ ldr r2, [pc, #2276] @ 228eca8 │ │ add r2, pc, r2 │ │ b 228d47c │ │ ldr r2, [pc, #2296] @ 228ecc8 │ │ add r2, pc, r2 │ │ b 228d47c │ │ - ldc2l 2, cr3, [r9, #580]! @ 0x244 │ │ + ldc2l 2, cr3, [r9, #760]! @ 0x2f8 │ │ ldr r2, [pc, #2284] @ 228eccc │ │ add r2, pc, r2 │ │ b 228d47c │ │ ldr r2, [pc, #2280] @ 228ecd4 │ │ add r2, pc, r2 │ │ b 228d47c │ │ ldr r2, [pc, #2232] @ 228ecb0 │ │ @@ -820071,15 +820071,15 @@ │ │ b 228d47c │ │ ldr r2, [pc, #2216] @ 228ecb8 │ │ add r2, pc, r2 │ │ b 228d47c │ │ ldr r2, [pc, #2208] @ 228ecbc │ │ add r2, pc, r2 │ │ b 228d47c │ │ - ldc2l 2, cr3, [r9, #308]! @ 0x134 │ │ + ldc2l 2, cr3, [r9, #488]! @ 0x1e8 │ │ ldr r0, [fp, #-148] @ 0xffffff6c │ │ ldr r2, [r7, #40] @ 0x28 │ │ cmp r0, #0 │ │ beq 228e43c │ │ ldr r0, [r7, #44] @ 0x2c │ │ b 228e448 │ │ ldr r1, [r7, #44] @ 0x2c │ │ @@ -820337,15 +820337,15 @@ │ │ add sl, ip, r1 │ │ add r1, r2, #4 │ │ cmn r3, #1 │ │ bne 228e868 │ │ ldr r1, [r1] │ │ rev r1, r1 │ │ b 228e934 │ │ - ldc2l 11, cr14, [r8, #632]! @ 0x278 @ │ │ + ldc2l 11, cr14, [r8, #812]! @ 0x32c @ │ │ mov r2, ip │ │ ldr r1, [r2, r1]! │ │ ldr r3, [r2, #8] │ │ add sl, ip, r1 │ │ add r1, r2, #4 │ │ cmn r3, #1 │ │ beq 228e930 │ │ @@ -820477,15 +820477,15 @@ │ │ ldr ip, [fp, #-144] @ 0xffffff70 │ │ add lr, lr, #1 │ │ ldr r0, [fp, #-172] @ 0xffffff54 │ │ ldr r1, [fp, #-188] @ 0xffffff44 │ │ ldr r8, [fp, #-208] @ 0xffffff30 │ │ ldr r7, [fp, #-168] @ 0xffffff58 │ │ b 228e734 │ │ - ldc2l 5, cr3, [r9, #444]! @ 0x1bc │ │ + ldc2l 5, cr3, [r9, #624]! @ 0x270 │ │ ldc2l 8, cr6, [fp, #744]! @ 0x2e8 │ │ ldr r0, [fp, #-196] @ 0xffffff3c │ │ cmp lr, r0 │ │ bne 228ebf8 │ │ ldr r4, [fp, #-176] @ 0xffffff50 │ │ ldr r6, [fp, #-212] @ 0xffffff2c │ │ ldr r0, [r4] │ │ @@ -820591,83 +820591,83 @@ │ │ bl 2707fc0 │ │ bl 2707fc0 │ │ bl 2707fc0 │ │ bl 2707fc0 │ │ bl 2707fc0 │ │ ldc2l 5, cr11, [r8, #864]! @ 0x360 │ │ ldc2l 12, cr6, [r8, #828]! @ 0x33c │ │ - ldc2l 0, cr1, [sl, #896]! @ 0x380 │ │ + ldc2l 1, cr1, [sl, #52]! @ 0x34 │ │ ldc2l 1, cr0, [ip, #540]! @ 0x21c │ │ - ldc2l 4, cr4, [sl, #40]! @ 0x28 │ │ + ldc2l 4, cr4, [sl, #220]! @ 0xdc │ │ ldc2l 12, cr6, [r8, #300]! @ 0x12c │ │ - ldc2l 0, cr1, [sl, #320]! @ 0x140 │ │ + ldc2l 0, cr1, [sl, #500]! @ 0x1f4 │ │ ldc2l 1, cr0, [ip, #108]! @ 0x6c │ │ - ldc2l 3, cr4, [sl, #584]! @ 0x248 │ │ + ldc2l 3, cr4, [sl, #764]! @ 0x2fc │ │ ldc2l 6, cr6, [fp, #968]! @ 0x3c8 │ │ ldc2l 12, cr6, [r8, #636]! @ 0x27c │ │ - ldc2l 0, cr1, [sl, #704]! @ 0x2c0 │ │ + ldc2l 0, cr1, [sl, #884]! @ 0x374 │ │ ldc2l 1, cr0, [ip, #348]! @ 0x15c │ │ - ldc2l 3, cr4, [sl, #872]! @ 0x368 │ │ + ldc2l 4, cr4, [sl, #28]! │ │ ldc2l 5, cr11, [r8, #176]! @ 0xb0 │ │ - ldc2l 15, cr14, [r8, #988]! @ 0x3dc │ │ - ldc2l 13, cr10, [sl, #320]! @ 0x140 │ │ - ldc2l 2, cr3, [r9, #508]! @ 0x1fc │ │ - ldc2l 10, cr6, [sl, #448]! @ 0x1c0 @ │ │ + ldc2l 0, cr15, [r8, #144]! @ 0x90 │ │ + ldc2l 13, cr10, [sl, #500]! @ 0x1f4 │ │ + ldc2l 2, cr3, [r9, #688]! @ 0x2b0 │ │ + ldc2l 10, cr6, [sl, #628]! @ 0x274 @ │ │ ldc2l 1, cr6, [fp, #360]! @ 0x168 │ │ ldc2l 6, cr6, [r8, #476]! @ 0x1dc │ │ - ldc2l 10, cr0, [sl, #544]! @ 0x220 @ │ │ + ldc2l 10, cr0, [sl, #724]! @ 0x2d4 @ │ │ ldc2l 11, cr15, [fp, #188]! @ 0xbc @ │ │ - ldc2l 13, cr3, [sl, #712]! @ 0x2c8 │ │ + ldc2l 13, cr3, [sl, #892]! @ 0x37c │ │ ldc2l 15, cr10, [r8, #592]! @ 0x250 │ │ ldc2l 6, cr6, [r8, #332]! @ 0x14c │ │ - ldc2l 10, cr0, [sl, #400]! @ 0x190 @ │ │ + ldc2l 10, cr0, [sl, #580]! @ 0x244 @ │ │ ldc2l 10, cr15, [fp, #876]! @ 0x36c @ │ │ - ldc2l 13, cr3, [sl, #376]! @ 0x178 │ │ + ldc2l 13, cr3, [sl, #556]! @ 0x22c │ │ ldc2l 2, cr6, [fp, #72]! @ 0x48 │ │ ldc2l 5, cr6, [r8, #1004]! @ 0x3ec │ │ - ldc2l 10, cr0, [sl, #48]! @ 0x30 @ │ │ + ldc2l 10, cr0, [sl, #228]! @ 0xe4 @ │ │ ldc2l 10, cr15, [fp, #524]! @ 0x20c @ │ │ - ldc2l 13, cr3, [sl, #24]! │ │ + ldc2l 13, cr3, [sl, #204]! @ 0xcc │ │ ldc2l 0, cr11, [r8, #304]! @ 0x130 │ │ ldc2l 7, cr10, [fp, #92]! @ 0x5c │ │ - ldc2l 9, cr14, [r8, #390]! @ 0x186 @ │ │ - ldc2l 7, cr10, [sl, #144]! @ 0x90 │ │ - ldc2l 12, cr2, [r9, #348]! @ 0x15c │ │ - ldc2l 4, cr6, [sl, #32]! │ │ - ldc2l 14, cr2, [r9, #844]! @ 0x34c │ │ + ldc2l 9, cr14, [r8, #480]! @ 0x1e0 @ │ │ + ldc2l 7, cr10, [sl, #324]! @ 0x144 │ │ + ldc2l 12, cr2, [r9, #528]! @ 0x210 │ │ + ldc2l 4, cr6, [sl, #212]! @ 0xd4 │ │ + ldc2l 15, cr2, [r9] │ │ ldc2l 3, cr6, [fp, #1000]! @ 0x3e8 │ │ ldc2l 7, cr6, [r8, #220]! @ 0xdc │ │ - ldc2l 11, cr0, [sl, #288]! @ 0x120 @ │ │ + ldc2l 11, cr0, [sl, #468]! @ 0x1d4 @ │ │ ldc2l 11, cr15, [fp, #956]! @ 0x3bc @ │ │ - ldc2l 14, cr3, [sl, #456]! @ 0x1c8 │ │ + ldc2l 14, cr3, [sl, #636]! @ 0x27c │ │ ldc2l 2, cr11, [r8, #208]! @ 0xd0 │ │ ldc2l 7, cr6, [r8, #28]! │ │ - ldc2l 11, cr0, [sl, #96]! @ 0x60 @ │ │ + ldc2l 11, cr0, [sl, #276]! @ 0x114 @ │ │ ldc2l 11, cr15, [fp, #572]! @ 0x23c @ │ │ - ldc2l 14, cr3, [sl, #72]! @ 0x48 │ │ + ldc2l 14, cr3, [sl, #252]! @ 0xfc │ │ ldc2l 4, cr6, [fp, #712]! @ 0x2c8 │ │ ldc2l 6, cr6, [r8, #764]! @ 0x2fc │ │ - ldc2l 10, cr0, [sl, #736]! @ 0x2e0 @ │ │ + ldc2l 10, cr0, [sl, #916]! @ 0x394 @ │ │ ldc2l 11, cr15, [fp, #332]! @ 0x14c @ │ │ - ldc2l 13, cr3, [sl, #856]! @ 0x358 │ │ + ldc2l 14, cr3, [sl, #12]! │ │ ldc2l 2, cr11, [r8, #944]! @ 0x3b0 │ │ ldc2l 9, cr10, [fp, #350]! @ 0x15e @ │ │ - ldc2l 10, cr14, [r8, #476]! @ 0x1dc @ │ │ - ldc2l 7, cr10, [sl, #880]! @ 0x370 │ │ - ldc2l 13, cr2, [r9, #92]! @ 0x5c │ │ - ldc2l 5, cr6, [sl, #80]! @ 0x50 │ │ - ldc2l 1, cr3, [r9, #444]! @ 0x1bc │ │ + ldc2l 10, cr14, [r8, #656]! @ 0x290 @ │ │ + vcmla.f32 d26, d10, d9, #270 │ │ + ldc2l 13, cr2, [r9, #272]! @ 0x110 │ │ + ldc2l 5, cr6, [sl, #260]! @ 0x104 │ │ + ldc2l 1, cr3, [r9, #624]! @ 0x270 │ │ ldc2l 0, cr12, [fp, #652]! @ 0x28c │ │ - ldc2l 13, cr2, [sl, #192]! @ 0xc0 │ │ - ldc2l 12, cr4, [r9, #740]! @ 0x2e4 │ │ - ldc2l 7, cr8, [sl, #724]! @ 0x2d4 │ │ + ldc2l 13, cr2, [sl, #372]! @ 0x174 │ │ + ldc2l 12, cr4, [r9, #920]! @ 0x398 │ │ + ldc2l 7, cr8, [sl, #904]! @ 0x388 │ │ ldc2l 9, cr6, [r8, #358]! @ 0x166 @ │ │ - ldc2l 13, cr0, [sl, #736]! @ 0x2e0 │ │ + ldc2l 13, cr0, [sl, #916]! @ 0x394 │ │ ldc2l 14, cr15, [fp, #524]! @ 0x20c │ │ - ldc2l 0, cr4, [sl, #1000]! @ 0x3e8 │ │ + ldc2l 1, cr4, [sl, #156]! @ 0x9c │ │ ldrb r1, [r0] │ │ cmp r1, #0 │ │ beq 228ed8c │ │ add r2, r0, #1 │ │ mov r0, #0 │ │ mov ip, #240 @ 0xf0 │ │ add r0, r1, r0, lsl #4 │ │ @@ -821291,15 +821291,15 @@ │ │ bl 2707fc0 │ │ bl 2707fc0 │ │ bl 2707fc0 │ │ @ instruction: 0x0050269c │ │ subeq r9, fp, r4, lsl #10 │ │ ldc2l 1, cr15, [fp, #1000]! @ 0x3e8 │ │ subeq r7, r9, ip, lsr r0 │ │ - ldc2l 6, cr1, [r9, #996]! @ 0x3e4 │ │ + ldc2l 7, cr1, [r9, #152]! @ 0x98 │ │ subseq r2, r0, r0, lsr r6 │ │ subseq r2, r0, ip, lsl r6 │ │ ldrdeq r0, [r0], -ip │ │ ldrsheq r2, [r0], #-84 @ 0xffffffac │ │ subeq ip, sl, r4, lsl #4 │ │ subseq r2, r0, r8, lsl r0 │ │ subseq r2, r0, r4, ror #10 │ │ @@ -822170,15 +822170,15 @@ │ │ bl 2707fc0 │ │ ldr r4, [r0, #4] │ │ b 22904a4 <_nl_expand_alias@@Base+0x114> │ │ bl 2707fc0 │ │ subseq r1, r0, r8, asr #4 │ │ subseq r1, r0, ip, lsr #4 │ │ subseq r1, r0, ip, lsl r2 │ │ - ldc2l 2, cr0, [r9, #660]! @ 0x294 │ │ + ldc2l 2, cr0, [r9, #840]! @ 0x348 │ │ andeq r0, r0, r4, lsl r1 │ │ subseq r1, r0, r8, lsl #4 │ │ ldrsheq r1, [r0], #-20 @ 0xffffffec │ │ ldrsbeq r1, [r0], #-16 │ │ subseq r1, r0, r0, asr r1 │ │ subseq r1, r0, r4, asr #2 │ │ ldr r1, [r1] │ │ @@ -822672,16 +822672,16 @@ │ │ str r0, [sp, #4] │ │ add r0, sp, #4 │ │ bl 2290cc0 <_nl_expand_alias@@Base+0x930> │ │ cmp r0, #0 │ │ bne 2290c20 <_nl_expand_alias@@Base+0x890> │ │ ldr r0, [sp, #8] │ │ b 2290c30 <_nl_expand_alias@@Base+0x8a0> │ │ - ldc2l 4, cr0, [r9, #56]! @ 0x38 │ │ - ldc2l 11, cr3, [sl, #1004]! @ 0x3ec @ │ │ + ldc2l 4, cr0, [r9, #236]! @ 0xec │ │ + ldc2l 12, cr3, [sl, #160]! @ 0xa0 │ │ subeq r5, r9, r8, ror r3 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #12 │ │ sub sp, sp, #1024 @ 0x400 │ │ str r0, [sp, #20] │ │ sub r0, fp, #232 @ 0xe8 │ │ @@ -823444,18 +823444,18 @@ │ │ subeq pc, pc, r0, lsl pc @ │ │ subeq pc, pc, r0, lsl #30 │ │ ldrdeq pc, [pc], #-236 @ │ │ ldc2l 11, cr7, [r8, #512]! @ 0x200 @ │ │ strheq pc, [pc], #-224 @ │ │ ldc2l 11, cr5, [r8, #312]! @ 0x138 @ │ │ ldc2l 9, cr9, [r8, #166]! @ 0xa6 @ │ │ - ldc2l 8, cr11, [r9, #964]! @ 0x3c4 │ │ + ldc2l 9, cr11, [r9, #60]! @ 0x3c @ │ │ vcmla.f32 q12, , , #270 │ │ ldc2l 9, cr12, [fp, #34]! @ 0x22 @ │ │ - ldc2l 7, cr15, [r8, #632]! @ 0x278 │ │ + ldc2l 7, cr15, [r8, #812]! @ 0x32c │ │ subeq pc, pc, r4, lsl #27 │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ mov r4, r0 │ │ mov r6, r1 │ │ mov r0, #34 @ 0x22 │ │ mov r1, r4 │ │ @@ -823530,15 +823530,15 @@ │ │ add r1, pc, r1 │ │ add r4, pc, r4 │ │ movne r4, r1 │ │ mov r0, r4 │ │ pop {r4, sl, fp, pc} │ │ bl 2707fc0 │ │ ldc2l 6, cr10, [sl, #272]! @ 0x110 │ │ - ldc2l 6, cr11, [r9, #932]! @ 0x3a4 │ │ + ldc2l 7, cr11, [r9, #88]! @ 0x58 │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ cmp r0, #6 │ │ beq 2291a88 <_nl_expand_alias@@Base+0x16f8> │ │ ldr r0, [pc, #84] @ 2291a8c <_nl_expand_alias@@Base+0x16fc> │ │ mov r4, r1 │ │ add r0, pc, r0 │ │ @@ -823558,16 +823558,16 @@ │ │ bl 2704290 │ │ cmp r0, #0 │ │ ldrbne r1, [r0] │ │ cmpne r1, #0 │ │ moveq r0, #0 │ │ pop {r4, sl, fp, pc} │ │ bl 2707fc0 │ │ - ldc2l 13, cr2, [sl, #752]! @ 0x2f0 │ │ - ldc2l 3, cr13, [r9, #588]! @ 0x24c │ │ + ldc2l 13, cr2, [sl, #932]! @ 0x3a4 │ │ + ldc2l 3, cr13, [r9, #768]! @ 0x300 │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ ldr r0, [pc, #80] @ 2291af4 <_nl_expand_alias@@Base+0x1764> │ │ mov r4, r1 │ │ add r0, pc, r0 │ │ bl 2704290 │ │ cmp r0, #0 │ │ @@ -823584,16 +823584,16 @@ │ │ add r0, pc, r0 │ │ bl 2704290 │ │ cmp r0, #0 │ │ ldrbne r1, [r0] │ │ cmpne r1, #0 │ │ moveq r0, #0 │ │ pop {r4, sl, fp, pc} │ │ - ldc2l 13, cr2, [sl, #320]! @ 0x140 │ │ - ldc2l 3, cr13, [r9, #156]! @ 0x9c │ │ + ldc2l 13, cr2, [sl, #500]! @ 0x1f4 │ │ + ldc2l 3, cr13, [r9, #336]! @ 0x150 │ │ ldr r0, [pc, #4] @ 2291b08 <_nl_expand_alias@@Base+0x1778> │ │ add r0, pc, r0 │ │ bx lr │ │ ldc2l 5, cr10, [sl, #272]! @ 0x110 │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ cmp r0, #6 │ │ @@ -823636,17 +823636,17 @@ │ │ cmp r0, #0 │ │ add r1, pc, r1 │ │ movne r1, r0 │ │ mov r0, r1 │ │ pop {r4, sl, fp, pc} │ │ bl 2707fc0 │ │ ldc2l 5, cr10, [sl] │ │ - ldc2l 5, cr11, [r9, #660]! @ 0x294 │ │ - ldc2l 12, cr2, [sl, #624]! @ 0x270 │ │ - ldc2l 2, cr13, [r9, #460]! @ 0x1cc │ │ + ldc2l 5, cr11, [r9, #840]! @ 0x348 │ │ + ldc2l 12, cr2, [sl, #804]! @ 0x324 │ │ + ldc2l 2, cr13, [r9, #640]! @ 0x280 │ │ ldc2l 4, cr10, [sl, #608]! @ 0x260 │ │ push {fp, lr} │ │ mov fp, sp │ │ cmp r0, #6 │ │ beq 2291c00 <_nl_expand_alias@@Base+0x1870> │ │ bl 22919cc <_nl_expand_alias@@Base+0x163c> │ │ cmp r0, #0 │ │ @@ -855579,16 +855579,16 @@ │ │ mcr2 0, 0, r8, cr1, cr3, {4} │ │ cdp2 0, 0, cr8, cr1, cr12, {5} │ │ cdp2 0, 0, cr8, cr1, cr11, {5} │ │ cdp2 0, 0, cr8, cr1, cr11, {3} │ │ cdp2 0, 0, cr8, cr1, cr8, {3} │ │ mcr2 1, 0, r8, cr1, cr5, {0} │ │ mcr2 1, 0, r8, cr1, cr2, {0} │ │ - cdp2 14, 0, cr0, cr1, cr8, {0} │ │ - ldc2l 9, cr15, [r9, #52]! @ 0x34 @ │ │ + mcr2 4, 0, r3, cr1, cr13, {0} │ │ + ldc2l 9, cr15, [r7, #52]! @ 0x34 @ │ │ lsls r0, r1, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ ldr.w r5, [r0, #332] @ 0x14c │ │ mov r4, r0 │ │ ldr r0, [r5, #24] │ │ @@ -894340,15 +894340,15 @@ │ │ popeq {r4, r6, r7, pc} │ │ blx 26ffb50 │ │ nop │ │ mov sl, r8 │ │ lsls r7, r0, #1 │ │ ldr r6, [pc, #240] @ (22c309c ) │ │ lsls r7, r0, #1 │ │ - ldr r6, [sp, #84] @ 0x54 │ │ + ldr r6, [sp, #264] @ 0x108 │ │ ldc2l 6, cr4, [r5, #624]! @ 0x270 │ │ lsls r7, r0, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #32 │ │ ldr r0, [r0, #0] │ │ @@ -894715,15 +894715,15 @@ │ │ lsls r7, r7, #11 │ │ movs r0, r0 │ │ lsls r7, r6, #8 │ │ movs r0, r0 │ │ lsls r7, r3, #3 │ │ movs r0, r0 │ │ ldmia r3!, {r0, r1, r2, r4, r5} │ │ - ldc2l 5, cr1, [r8, #760]! @ 0x2f8 │ │ + ldc2l 5, cr1, [r8, #940]! @ 0x3ac │ │ ldc2l 2, cr4, [r7, #672]! @ 0x2a0 │ │ lsls r7, r0, #1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #12 │ │ ldr.w sl, [r0, #4] │ │ @@ -899748,15 +899748,15 @@ │ │ nop │ │ subs r4, r1, #1 │ │ lsls r0, r1, #1 │ │ asrs r2, r5, #32 │ │ lsls r7, r0, #1 │ │ stmia r1!, {r2, r4, r5, r6} │ │ ldc2l 4, cr14, [r7, #960]! @ 0x3c0 │ │ - ldc2l 9, cr10, [r4, #506]! @ 0x1fa @ │ │ + ldc2l 10, cr10, [r4, #168]! @ 0xa8 @ │ │ ldc2l 13, cr1, [r5, #488]! @ 0x1e8 │ │ lsls r0, r1, #1 │ │ lsrs r0, r1, #29 │ │ lsls r7, r0, #1 │ │ │ │ 022c6714 : │ │ push {r7, lr} │ │ @@ -954581,15 +954581,15 @@ │ │ pop {r4, r5, fp, pc} │ │ mov r0, #1 │ │ pop {r4, r5, fp, pc} │ │ mov r0, r5 │ │ bl 27030a0 │ │ mov r0, #81 @ 0x51 │ │ pop {r4, r5, fp, pc} │ │ - ldc2l 4, cr2, [r4, #56]! @ 0x38 │ │ + ldc2l 4, cr2, [r4, #236]! @ 0xec │ │ strheq r0, [r0], -r0 @ │ │ andeq r0, r0, ip, lsr #32 │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ cmp r3, #0 │ │ bne 22ee1e4 │ │ ldr r6, [r0, #4] │ │ @@ -955510,16 +955510,16 @@ │ │ mov r1, r4 │ │ ldr r0, [r0, #4] │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ b 22f6538 │ │ mov r7, #6 │ │ b 22ee7d0 │ │ - ldc2l 10, cr7, [r4, #1020]! @ 0x3fc @ │ │ - ldc2l 3, cr14, [r3, #20]! │ │ + ldc2l 11, cr7, [r4, #176]! @ 0xb0 @ │ │ + ldc2l 3, cr14, [r3, #200]! @ 0xc8 │ │ │ │ 022ef024 : │ │ add r0, r0, r0, asr #31 │ │ add r0, r0, #32768 @ 0x8000 │ │ bfc r0, #0, #16 │ │ bx lr │ │ │ │ @@ -956908,30 +956908,30 @@ │ │ cmp r2, #0 │ │ beq 22f057c │ │ ldr r1, [pc, #12] @ 22f0584 │ │ add r1, pc, r1 │ │ bx r2 │ │ mov r0, #0 │ │ bx lr │ │ - ldc2l 3, cr6, [r4, #444]! @ 0x1bc │ │ + ldc2l 3, cr6, [r4, #624]! @ 0x270 │ │ │ │ 022f0588 : │ │ cmp r0, #0 │ │ beq 22f05b0 │ │ ldr r0, [r0, #96] @ 0x60 │ │ ldr r1, [r0] │ │ ldr r2, [r1, #32] │ │ cmp r2, #0 │ │ beq 22f05b0 │ │ ldr r1, [pc, #12] @ 22f05b8 │ │ add r1, pc, r1 │ │ bx r2 │ │ mov r0, #0 │ │ bx lr │ │ - ldc2l 3, cr6, [r4, #236]! @ 0xec │ │ + ldc2l 3, cr6, [r4, #416]! @ 0x1a0 │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ ldr r2, [r0, #4] │ │ mov r4, r1 │ │ mov r1, #96 @ 0x60 │ │ mov r5, r0 │ │ blx r2 │ │ @@ -960329,15 +960329,15 @@ │ │ mov r2, r6 │ │ b 22f38a8 │ │ nop {0} │ │ nop {0} │ │ andeq r0, r1, r0 │ │ ... │ │ andeq r0, r1, r0 │ │ - ldc2l 7, cr3, [r4, #732]! @ 0x2dc │ │ + ldc2l 7, cr3, [r4, #912]! @ 0x390 │ │ subeq r3, r3, r0, rrx │ │ umaaleq r2, r3, r8, pc @ │ │ │ │ 022f3a8c : │ │ cmp r1, #0 │ │ moveq r0, #6 │ │ bxeq lr │ │ @@ -962847,15 +962847,15 @@ │ │ str r2, [r3, #28] │ │ cmp r1, #0 │ │ ldrne r1, [r1] │ │ cmpne r1, #0 │ │ beq 22f6064 │ │ pop {r4, sl, fp, lr} │ │ bx r1 │ │ - ldc2l 15, cr4, [r3, #176]! @ 0xb0 │ │ + ldc2l 15, cr4, [r3, #356]! @ 0x164 │ │ │ │ 022f60dc : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ cmp r0, #0 │ │ ldrbne r2, [r0, #8] │ │ tstne r2, #8 │ │ @@ -962878,15 +962878,15 @@ │ │ cmp r0, #0 │ │ beq 22f60f4 │ │ mov r1, r5 │ │ mov r0, r4 │ │ ldr r2, [r2, #4] │ │ pop {r4, r5, fp, lr} │ │ bx r2 │ │ - ldc2l 13, cr8, [r3, #712]! @ 0x2c8 │ │ + ldc2l 13, cr8, [r3, #892]! @ 0x37c │ │ │ │ 022f6150 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ mov ip, r0 │ │ cmp ip, #0 │ │ @@ -962922,15 +962922,15 @@ │ │ mov r3, r5 │ │ str r9, [fp, #8] │ │ mov r0, sl │ │ mov ip, r7 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ bx ip │ │ - ldc2l 13, cr8, [r3, #152]! @ 0x98 │ │ + ldc2l 13, cr8, [r3, #332]! @ 0x14c │ │ │ │ 022f61f8 : │ │ mov ip, r0 │ │ mov r0, #35 @ 0x23 │ │ cmp ip, #0 │ │ bxeq lr │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ @@ -962965,15 +962965,15 @@ │ │ mov r0, r8 │ │ mov r5, r6 │ │ str r6, [sp] │ │ blx r7 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, lr} │ │ bx lr │ │ - ldc2l 12, cr8, [r3, #552]! @ 0x228 │ │ + ldc2l 12, cr8, [r3, #732]! @ 0x2dc │ │ │ │ 022f629c : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #8 │ │ mov r4, r0 │ │ cmp r4, #0 │ │ @@ -964260,15 +964260,15 @@ │ │ mov r0, r6 │ │ add r1, pc, r1 │ │ blx r2 │ │ cmp r0, #0 │ │ ldrne r8, [r0] │ │ mov r0, r8 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ - ldc2l 2, cr15, [r3, #1004]! @ 0x3ec │ │ + ldc2l 3, cr15, [r3, #160]! @ 0xa0 │ │ ldc2l 11, cr6, [r5, #656]! @ 0x290 @ │ │ │ │ 022f765c : │ │ mov ip, r0 │ │ mov r0, #6 │ │ cmp ip, #0 │ │ bxeq lr │ │ @@ -965915,17 +965915,17 @@ │ │ bic r0, r0, r0, asr #31 │ │ str r0, [r9, #68] @ 0x44 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ ldc2l 15, cr7, [r4, #380]! @ 0x17c │ │ ldc2l 7, cr14, [r1, #140]! @ 0x8c │ │ - ldc2l 2, cr14, [r2, #736]! @ 0x2e0 │ │ - ldc2l 12, cr13, [r3, #560]! @ 0x230 │ │ - ldc2l 3, cr2, [r3, #324]! @ 0x144 │ │ + ldc2l 2, cr14, [r2, #916]! @ 0x394 │ │ + ldc2l 12, cr13, [r3, #740]! @ 0x2e4 │ │ + ldc2l 3, cr2, [r3, #504]! @ 0x1f8 │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r6, r1 │ │ ldr r1, [pc, #188] @ 22f908c │ │ mov r5, r0 │ │ mov r0, r6 │ │ add r1, pc, r1 │ │ @@ -965972,15 +965972,15 @@ │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldrb r0, [r5, #32] │ │ strb r0, [r4] │ │ mov r0, #0 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldc2l 11, cr7, [r4, #764]! @ 0x2fc @ │ │ ldc2l 3, cr14, [r1, #540]! @ 0x21c │ │ - ldc2l 8, cr13, [r3, #960]! @ 0x3c0 │ │ + ldc2l 9, cr13, [r3, #58]! @ 0x3a @ │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #60 @ 0x3c │ │ ldr r7, [r1, #20] │ │ mov r4, r3 │ │ mov r6, r2 │ │ mov r5, r1 │ │ @@ -969024,16 +969024,16 @@ │ │ uxtb r1, r0 │ │ cmp r1, #2 │ │ beq 22fbb2c │ │ b 22fbb60 │ │ mov r0, #64 @ 0x40 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 13, cr6, [r2, #688]! @ 0x2b0 │ │ - ldc2l 14, cr0, [r2, #336]! @ 0x150 │ │ + ldc2l 13, cr6, [r2, #868]! @ 0x364 │ │ + ldc2l 14, cr0, [r2, #516]! @ 0x204 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #44 @ 0x2c │ │ mov r5, r0 │ │ ldr r4, [fp, #8] │ │ ldr r7, [r5] │ │ mov r0, #0 │ │ @@ -969609,18 +969609,18 @@ │ │ mov r2, r9 │ │ mov r3, #0 │ │ strd r0, [sp] │ │ mov r0, sl │ │ mov r1, r7 │ │ bl 22fbfd4 │ │ b 22fc444 │ │ - ldc2l 5, cr0, [r2, #512]! @ 0x200 │ │ - ldc2l 0, cr10, [r3, #140]! @ 0x8c │ │ + ldc2l 5, cr0, [r2, #692]! @ 0x2b4 │ │ + ldc2l 0, cr10, [r3, #320]! @ 0x140 │ │ ldc2l 3, cr12, [r3, #176]! @ 0xb0 │ │ - ldc2l 0, cr10, [r3, #220]! @ 0xdc │ │ + ldc2l 0, cr10, [r3, #400]! @ 0x190 │ │ mov r0, #0 │ │ cmp r1, #0 │ │ ldr r2, [sp] │ │ str r0, [r3] │ │ moveq r0, #81 @ 0x51 │ │ bxeq lr │ │ movw r3, #5639 @ 0x1607 │ │ @@ -969694,15 +969694,15 @@ │ │ cmp r7, #0 │ │ bne 22fc9b8 │ │ mov r7, #0 │ │ str r5, [r8] │ │ b 22fc9d0 │ │ mov r7, #81 @ 0x51 │ │ b 22fc9b8 │ │ - ldc2l 9, cr8, [r2, #234]! @ 0xea @ │ │ + ldc2l 9, cr8, [r2, #324]! @ 0x144 @ │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ mov r7, r0 │ │ mov r0, r2 │ │ mov r4, r3 │ │ mov r5, r2 │ │ bl 26ffea0 │ │ @@ -969793,15 +969793,15 @@ │ │ mov r1, r0 │ │ mov r0, #0 │ │ str r1, [r4] │ │ str r0, [r2] │ │ pop {r4, sl, fp, pc} │ │ mov r0, #64 @ 0x40 │ │ pop {r4, sl, fp, pc} │ │ - ldc2l 4, cr12, [r2, #652]! @ 0x28c │ │ + ldc2l 4, cr12, [r2, #832]! @ 0x340 │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ mov r1, r2 │ │ ldr r2, [pc, #52] @ 22fcc1c │ │ ldr r0, [r0] │ │ mov r4, r3 │ │ add r2, pc, r2 │ │ @@ -969812,15 +969812,15 @@ │ │ mov r1, r0 │ │ mov r0, #0 │ │ str r1, [r4] │ │ str r0, [r2] │ │ pop {r4, sl, fp, pc} │ │ mov r0, #64 @ 0x40 │ │ pop {r4, sl, fp, pc} │ │ - ldc2l 5, cr0, [r3, #64]! @ 0x40 │ │ + ldc2l 5, cr0, [r3, #244]! @ 0xf4 │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #40 @ 0x28 │ │ mov r1, r2 │ │ ldr r2, [pc, #212] @ 22fcd0c │ │ ldr r4, [r0] │ │ mov r6, r0 │ │ @@ -969932,15 +969932,15 @@ │ │ cmp r7, #0 │ │ bne 22fcd70 │ │ mov r7, #0 │ │ str r5, [r8] │ │ b 22fcd88 │ │ mov r7, #81 @ 0x51 │ │ b 22fcd70 │ │ - ldc2l 5, cr8, [r2, #768]! @ 0x300 │ │ + ldc2l 5, cr8, [r2, #948]! @ 0x3b4 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #12 │ │ mov r8, r2 │ │ ldrd r2, [r0, #4] │ │ mov r5, r0 │ │ add r0, r3, #3 │ │ @@ -977058,15 +977058,15 @@ │ │ ldr r1, [fp, #-36] @ 0xffffffdc │ │ mov r0, r1 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 11, cr13, [fp, #560]! @ 0x230 @ │ │ ldc2l 9, cr13, [fp, #232]! @ 0xe8 @ │ │ ldc2l 5, cr15, [r0, #16]! │ │ - vcmla.f32 , , , #270 │ │ + ldc2l 8, cr11, [r1, #584]! @ 0x248 │ │ ldc2l 15, cr4, [r4, #640]! @ 0x280 │ │ ldc2l 3, cr13, [r3, #384]! @ 0x180 │ │ ldc2l 15, cr4, [r4, #504]! @ 0x1f8 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #12 │ │ ldr r8, [r0, #740] @ 0x2e4 │ │ @@ -980928,15 +980928,15 @@ │ │ cmp r0, #38 @ 0x26 │ │ mov r0, #7 │ │ bne 2307964 │ │ mov r0, #40 @ 0x28 │ │ str r0, [r4, #64] @ 0x40 │ │ mov r0, #0 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2l 3, cr11, [r1, #920]! @ 0x398 │ │ + ldc2l 4, cr11, [r1, #76]! @ 0x4c │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r2 │ │ mov r2, r1 │ │ ldr r1, [pc, #40] @ 2307a00 │ │ mov r5, r0 │ │ mov r0, r2 │ │ @@ -980945,15 +980945,15 @@ │ │ mov r1, r0 │ │ mov r0, #12 │ │ cmp r1, #0 │ │ ldreq r0, [r5, #64] @ 0x40 │ │ streq r0, [r4] │ │ moveq r0, #0 │ │ pop {r4, r5, fp, pc} │ │ - ldc2l 3, cr11, [r1, #344]! @ 0x158 │ │ + ldc2l 3, cr11, [r1, #524]! @ 0x20c │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ mov ip, r1 │ │ ldrb r1, [r0, #292] @ 0x124 │ │ ldr lr, [fp, #8] │ │ cmp r1, #0 │ │ beq 2307a40 │ │ @@ -986293,15 +986293,15 @@ │ │ beq 230cd50 │ │ ldr r2, [r5] │ │ cmp r2, #0 │ │ beq 230cd50 │ │ mov r0, r4 │ │ pop {r4, r5, fp, lr} │ │ bx r2 │ │ - ldc2l 5, cr8, [r1, #824]! @ 0x338 │ │ + ldc2l 5, cr8, [r1, #1004]! @ 0x3ec │ │ │ │ 0230cd8c : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ mov r0, #6 │ │ cmp r1, #0 │ │ @@ -986344,15 +986344,15 @@ │ │ beq 230ce14 │ │ ldr r2, [r5, #16] │ │ cmp r2, #0 │ │ beq 230ce14 │ │ mov r0, r4 │ │ pop {r4, r5, fp, lr} │ │ bx r2 │ │ - ldc2l 5, cr8, [r1, #40]! @ 0x28 │ │ + ldc2l 5, cr8, [r1, #220]! @ 0xdc │ │ │ │ 0230ce50 : │ │ cmp r0, #0 │ │ moveq r0, #33 @ 0x21 │ │ bxeq lr │ │ push {fp, lr} │ │ mov fp, sp │ │ @@ -986430,15 +986430,15 @@ │ │ ldr r0, [r6, #116] @ 0x74 │ │ blx r1 │ │ mov r0, #0 │ │ str r0, [r6, #116] @ 0x74 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 4, cr8, [r1, #88]! @ 0x58 │ │ + ldc2l 4, cr8, [r1, #268]! @ 0x10c │ │ │ │ 0230cf98 : │ │ mov r3, r0 │ │ mov r0, #6 │ │ cmp r1, #0 │ │ beq 230cfb0 │ │ cmp r2, #0 │ │ @@ -986505,15 +986505,15 @@ │ │ ldr r0, [r6, #116] @ 0x74 │ │ blx r1 │ │ mov r0, #0 │ │ str r0, [r6, #116] @ 0x74 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 2, cr8, [r1, #968]! @ 0x3c8 │ │ + ldc2l 3, cr8, [r1, #124]! @ 0x7c │ │ │ │ 0230d0bc : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ mov r0, #6 │ │ cmp r1, #0 │ │ @@ -986561,15 +986561,15 @@ │ │ beq 230d0dc │ │ ldr r3, [r6, #40] @ 0x28 │ │ cmp r3, #0 │ │ beq 230d0dc │ │ mov r0, r4 │ │ pop {r4, r5, r6, sl, fp, lr} │ │ bx r3 │ │ - ldc2l 1, cr8, [r1, #808]! @ 0x328 │ │ + ldc2l 1, cr8, [r1, #988]! @ 0x3dc │ │ │ │ 0230d194 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ mov r0, #6 │ │ cmp r1, #0 │ │ @@ -986688,15 +986688,15 @@ │ │ mov r4, r1 │ │ blx r2 │ │ mov r0, #0 │ │ str r0, [r4, #116] @ 0x74 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 0, cr8, [r1, #984]! @ 0x3d8 │ │ + ldc2l 1, cr8, [r1, #140]! @ 0x8c │ │ ldc2l 2, cr15, [r3, #576]! @ 0x240 │ │ │ │ 0230d38c : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ mov r0, #6 │ │ @@ -986742,15 +986742,15 @@ │ │ beq 230d41c │ │ ldr r3, [r6, #24] │ │ cmp r3, #0 │ │ beq 230d41c │ │ mov r0, r4 │ │ pop {r4, r5, r6, sl, fp, lr} │ │ bx r3 │ │ - ldc2l 15, cr7, [r1, #24]! │ │ + ldc2l 15, cr7, [r1, #204]! @ 0xcc │ │ │ │ 0230d458 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ mov r0, #6 │ │ cmp r1, #0 │ │ @@ -986869,15 +986869,15 @@ │ │ mov r4, r1 │ │ blx r2 │ │ mov r0, #0 │ │ str r0, [r4, #116] @ 0x74 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 14, cr7, [r1, #200]! @ 0xc8 │ │ + ldc2l 14, cr7, [r1, #380]! @ 0x17c │ │ ldc2l 15, cr14, [r3, #816]! @ 0x330 │ │ │ │ 0230d650 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ mov r0, #6 │ │ @@ -986997,15 +986997,15 @@ │ │ mov r4, r1 │ │ blx r2 │ │ mov r0, #0 │ │ str r0, [r4, #116] @ 0x74 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 12, cr7, [r1, #232]! @ 0xe8 │ │ + ldc2l 12, cr7, [r1, #412]! @ 0x19c │ │ ldc2l 13, cr14, [r3, #848]! @ 0x350 │ │ │ │ 0230d848 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ mov r0, #6 │ │ @@ -987051,15 +987051,15 @@ │ │ beq 230d8d8 │ │ ldr r3, [r6, #12] │ │ cmp r3, #0 │ │ beq 230d8d8 │ │ mov r0, r4 │ │ pop {r4, r5, r6, sl, fp, lr} │ │ bx r3 │ │ - ldc2l 10, cr7, [r1, #296]! @ 0x128 @ │ │ + ldc2l 10, cr7, [r1, #476]! @ 0x1dc @ │ │ │ │ 0230d914 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ mov r0, #6 │ │ cmp r2, #0 │ │ @@ -987104,15 +987104,15 @@ │ │ beq 230d9a4 │ │ ldr r3, [r6, #12] │ │ cmp r3, #0 │ │ beq 230d9a4 │ │ mov r0, r4 │ │ pop {r4, r5, r6, sl, fp, lr} │ │ bx r3 │ │ - ldc2l 9, cr7, [r1, #252]! @ 0xfc @ │ │ + ldc2l 9, cr7, [r1, #342]! @ 0x156 @ │ │ │ │ 0230d9e0 : │ │ mov ip, r0 │ │ cmp ip, #0 │ │ mov r0, #6 │ │ cmpne r2, #0 │ │ bne 230d9f8 │ │ @@ -987235,15 +987235,15 @@ │ │ mov r4, r1 │ │ blx r2 │ │ mov r0, #0 │ │ str r0, [r4, #116] @ 0x74 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ mov r0, #0 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - vcmla.f32 d23, d17, d6, #270 │ │ + ldc2l 8, cr7, [r1, #716]! @ 0x2cc │ │ ldc2l 10, cr14, [r3, #208]! @ 0xd0 @ │ │ │ │ 0230dbe0 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ cmp r0, #0 │ │ beq 230dc64 │ │ @@ -987289,15 +987289,15 @@ │ │ cmp r3, #0 │ │ beq 230dca0 │ │ mov r0, r2 │ │ pop {r4, r5, fp, lr} │ │ bx r3 │ │ mov r0, #0 │ │ pop {r4, r5, fp, pc} │ │ - ldc2l 6, cr7, [r1, #744]! @ 0x2e8 │ │ + ldc2l 6, cr7, [r1, #924]! @ 0x39c │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ sub sp, sp, #8 │ │ add r1, pc, #116 @ 0x74 │ │ mov r3, sp │ │ vld1.64 {d16-d17}, [r1 :128] │ │ add r1, pc, #120 @ 0x78 │ │ vld1.64 {d18-d19}, [r1 :128] │ │ @@ -988380,15 +988380,15 @@ │ │ cmp r9, r8 │ │ bne 230ed7c │ │ ldr r3, [sp, #32] │ │ mov r5, #0 │ │ ldr r6, [pc, #172] @ 230ee5c │ │ add r6, pc, r6 │ │ b 230ed3c │ │ - ldc2l 3, cr15, [r1, #188]! @ 0xbc │ │ + ldc2l 3, cr15, [r1, #368]! @ 0x170 │ │ ldr r0, [r4, #384] @ 0x180 │ │ ldr r1, [r4, #388] @ 0x184 │ │ add r0, r0, r7, lsl #1 │ │ str r5, [r1, r7, lsl #2] │ │ mov r1, r5 │ │ strh r8, [r0] │ │ ldr r6, [pc, #128] @ 230ee58 │ │ @@ -988426,15 +988426,15 @@ │ │ ldc2l 5, cr11, [r0, #176]! @ 0xb0 │ │ ldc2l 14, cr5, [r0, #232]! @ 0xe8 │ │ ldc2l 13, cr5, [r0, #520]! @ 0x208 │ │ ldc2l 13, cr5, [r0, #680]! @ 0x2a8 │ │ ldc2l 12, cr12, [r2, #792]! @ 0x318 │ │ ldc2l 12, cr12, [r2, #24]! │ │ ldc2l 2, cr11, [r0, #220]! @ 0xdc │ │ - ldc2l 15, cr14, [r1, #352]! @ 0x160 │ │ + ldc2l 15, cr14, [r1, #532]! @ 0x214 │ │ andeq r3, r0, r0, asr #9 │ │ cmp r0, #0 │ │ bxeq lr │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ ldr r1, [r0, #548] @ 0x224 │ │ mov r4, r0 │ │ @@ -988576,15 +988576,15 @@ │ │ blx r3 │ │ cmp r0, #0 │ │ ldreq r1, [r4, #40] @ 0x28 │ │ ldreq r2, [sp, #4] │ │ streq r2, [r1] │ │ sub sp, fp, #8 │ │ pop {r4, r5, fp, pc} │ │ - ldc2l 0, cr14, [r1, #748]! @ 0x2ec │ │ + ldc2l 0, cr14, [r1, #928]! @ 0x3a0 │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [r0, #40] @ 0x28 │ │ ldr r0, [r0] │ │ cmp r0, #0 │ │ beq 230f124 │ │ @@ -988609,15 +988609,15 @@ │ │ cmp r0, #0 │ │ beq 230f118 │ │ ldr r1, [r4, #40] @ 0x28 │ │ ldr r2, [r0, #8] │ │ ldr r0, [r1] │ │ blx r2 │ │ b 230f118 │ │ - ldc2l 0, cr14, [r1, #60]! @ 0x3c │ │ + ldc2l 0, cr14, [r1, #240]! @ 0xf0 │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [r0, #4] │ │ ldr r5, [r0, #552] @ 0x228 │ │ cmp r5, #0 │ │ beq 230f190 │ │ @@ -988629,15 +988629,15 @@ │ │ beq 230f190 │ │ ldr r1, [r5, #4] │ │ blx r1 │ │ ldr r1, [r4, #156] @ 0x9c │ │ str r0, [r1, #36] @ 0x24 │ │ mov r0, #0 │ │ pop {r4, r5, fp, pc} │ │ - ldc2l 15, cr13, [r1, #604]! @ 0x25c │ │ + ldc2l 15, cr13, [r1, #784]! @ 0x310 │ │ ldr r0, [r0, #156] @ 0x9c │ │ cmp r0, #0 │ │ movne r1, #0 │ │ strne r1, [r0, #36] @ 0x24 │ │ bx lr │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -989295,15 +989295,15 @@ │ │ mov r1, r2 │ │ mov r2, r3 │ │ mov r3, #0 │ │ blx r7 │ │ mov r0, r4 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 5, cr13, [r1, #540]! @ 0x21c │ │ + ldc2l 5, cr13, [r1, #720]! @ 0x2d0 │ │ ldr r0, [r0, #364] @ 0x16c │ │ bx lr │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r0, [r0, #424] @ 0x1a8 │ │ ldr r1, [r0, r1, lsl #2] │ │ mov r0, r2 │ │ @@ -990379,15 +990379,15 @@ │ │ ldr r1, [sp, #4] │ │ ldr r2, [sp, #12] │ │ str r2, [r1] │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 1, cr2, [r0, #16]! │ │ ldc2l 12, cr7, [r3, #768]! @ 0x300 │ │ - ldc2l 5, cr14, [r0, #548]! @ 0x224 │ │ + ldc2l 5, cr14, [r0, #728]! @ 0x2d8 │ │ ldc2l 0, cr0, [r3, #32]! │ │ ldc2l 12, cr7, [r3, #504]! @ 0x1f8 │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #16 │ │ mov r4, r1 │ │ mov r5, r0 │ │ @@ -991905,15 +991905,15 @@ │ │ mov r0, #3 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 9, cr5, [r0, #268]! @ 0x10c @ │ │ ldc2l 5, cr12, [r3, #384]! @ 0x180 │ │ ldc2l 13, cr0, [r3, #560]! @ 0x230 │ │ subeq r4, r1, r8, lsr r3 │ │ - ldc2l 12, cr8, [r1, #932]! @ 0x3a4 │ │ + ldc2l 13, cr8, [r1, #88]! @ 0x58 │ │ ldc2l 15, cr4, [r0, #184]! @ 0xb8 │ │ ldc2l 0, cr5, [r0, #472]! @ 0x1d8 │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r6, r1 │ │ mov r1, #0 │ │ @@ -992453,15 +992453,15 @@ │ │ add r9, r7, #1 │ │ str r9, [r4] │ │ mov r0, #1 │ │ b 2312934 │ │ ldc2l 1, cr2, [r0, #904]! @ 0x388 │ │ ldc2l 6, cr8, [r2, #24]! │ │ ldc2l 9, cr7, [r3, #398]! @ 0x18e @ │ │ - ldc2l 7, cr12, [r1, #68]! @ 0x44 │ │ + ldc2l 7, cr12, [r1, #248]! @ 0xf8 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #28 │ │ mov r4, r1 │ │ ldr r6, [r1, #16] │ │ ldr r1, [r1, #28] │ │ mov r5, r0 │ │ @@ -992702,16 +992702,16 @@ │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ cmp r7, #0 │ │ bne 2312dd8 │ │ mov r0, #3 │ │ str r0, [r4, #12] │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 1, cr14, [r0, #532]! @ 0x214 │ │ - ldc2l 7, cr1, [r2, #440]! @ 0x1b8 │ │ + ldc2l 1, cr14, [r0, #712]! @ 0x2c8 │ │ + ldc2l 7, cr1, [r2, #620]! @ 0x26c │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #52 @ 0x34 │ │ mov r8, r1 │ │ ldr sl, [r1, #16] │ │ ldr r5, [r1] │ │ mov r9, r0 │ │ @@ -994850,22 +994850,22 @@ │ │ ldr r0, [r4, #20] │ │ mov r1, r5 │ │ bl 2319ee0 │ │ mov r0, r5 │ │ b 2314ee8 │ │ ldc2l 6, cr6, [r2, #116]! @ 0x74 │ │ ldc2l 11, cr1, [r3, #152]! @ 0x98 @ │ │ - ldc2l 9, cr8, [r1, #230]! @ 0xe6 @ │ │ + ldc2l 9, cr8, [r1, #320]! @ 0x140 @ │ │ ldc2l 15, cr13, [r2, #968]! @ 0x3c8 │ │ ldc2l 13, cr7, [r3, #956]! @ 0x3bc │ │ ldc2l 14, cr5, [r2, #616]! @ 0x268 │ │ ldc2l 4, cr4, [r0, #332]! @ 0x14c │ │ - ldc2l 1, cr8, [r1, #464]! @ 0x1d0 │ │ + ldc2l 1, cr8, [r1, #644]! @ 0x284 │ │ ldc2l 3, cr4, [r0, #428]! @ 0x1ac │ │ - ldc2l 0, cr8, [r1, #544]! @ 0x220 │ │ + ldc2l 0, cr8, [r1, #724]! @ 0x2d4 │ │ ldrdeq r1, [r1], #-180 @ 0xffffff4c │ │ subeq r1, r1, ip, ror #21 │ │ cmp r0, #0 │ │ bxeq lr │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ mov r9, r0 │ │ @@ -995151,15 +995151,15 @@ │ │ ldr r4, [fp, #-36] @ 0xffffffdc │ │ b 2315634 │ │ ldr r0, [r9, #40] @ 0x28 │ │ mvn r1, #0 │ │ str r1, [r9, #44] @ 0x2c │ │ str r7, [r0] │ │ b 2315634 │ │ - ldc2l 10, cr7, [r1, #988]! @ 0x3dc @ │ │ + ldc2l 11, cr7, [r1, #144]! @ 0x90 @ │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ ldr r1, [r0, #40] @ 0x28 │ │ ldr r4, [r1] │ │ cmp r4, #0 │ │ beq 23157e8 │ │ ldr r0, [r0] │ │ @@ -995193,15 +995193,15 @@ │ │ beq 23157d8 │ │ ldr r0, [r4, r7, lsl #2] │ │ ldr r1, [r6, #8] │ │ blx r1 │ │ subs r7, r7, #1 │ │ bne 2315814 │ │ b 23157d8 │ │ - ldc2l 9, cr7, [r1, #166]! @ 0xa6 @ │ │ + ldc2l 9, cr7, [r1, #256]! @ 0x100 @ │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [r0, #4] │ │ ldr r0, [r0, #716] @ 0x2cc │ │ ldr r5, [r0, #3080] @ 0xc08 │ │ cmp r5, #0 │ │ @@ -995214,15 +995214,15 @@ │ │ beq 2315878 │ │ ldr r1, [r5, #8] │ │ blx r1 │ │ ldr r1, [r4, #156] @ 0x9c │ │ str r0, [r1, #36] @ 0x24 │ │ mov r0, #0 │ │ pop {r4, r5, fp, pc} │ │ - vcmla.f32 d23, d17, d31, #270 │ │ + ldc2l 8, cr7, [r1, #880]! @ 0x370 │ │ ldr r0, [r0, #156] @ 0x9c │ │ cmp r0, #0 │ │ movne r1, #0 │ │ strne r1, [r0, #36] @ 0x24 │ │ bx lr │ │ nop {0} │ │ nop {0} │ │ @@ -996229,15 +996229,15 @@ │ │ ldr r1, [sp, #16] │ │ mov r0, r4 │ │ bl 2316864 │ │ mov r7, #0 │ │ mov r0, r7 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 9, cr6, [r1, #398]! @ 0x18e @ │ │ + ldc2l 9, cr6, [r1, #488]! @ 0x1e8 @ │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #12 │ │ mov r4, r0 │ │ ldr r0, [r0] │ │ str r1, [r4, #44] @ 0x2c │ │ bl 22f45d4 │ │ @@ -996307,15 +996307,15 @@ │ │ mov r7, r0 │ │ ldr r0, [r4, #20] │ │ mov r1, r8 │ │ mov r2, r5 │ │ bl 270b920 │ │ mov r2, r0 │ │ b 2316924 │ │ - ldc2l 8, cr6, [r1, #476]! @ 0x1dc │ │ + vcmla.f32 d22, d17, d20, #270 │ │ ldr r2, [r0, #716] @ 0x2cc │ │ movw r3, #65535 @ 0xffff │ │ ldr r0, [r2, #1188] @ 0x4a4 │ │ add r0, r0, r1, lsl #1 │ │ ldrh r1, [r0] │ │ mov r0, #0 │ │ cmp r1, r3 │ │ @@ -996683,16 +996683,16 @@ │ │ cmp r7, #22 │ │ bhi 2316f6c │ │ tst lr, r3, lsl r7 │ │ bne 2316f3c │ │ mov r2, #0 │ │ strh r2, [r0] │ │ b 2316e48 │ │ - ldc2l 10, cr11, [r1, #924]! @ 0x39c @ │ │ - ldc2l 2, cr6, [r1, #232]! @ 0xe8 │ │ + ldc2l 11, cr11, [r1, #80]! @ 0x50 @ │ │ + ldc2l 2, cr6, [r1, #412]! @ 0x19c │ │ ldr r0, [r0, #8] │ │ ubfx r0, r0, #9, #1 │ │ bx lr │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ ldr r5, [r0, #716] @ 0x2cc │ │ @@ -996718,15 +996718,15 @@ │ │ ldrne r1, [r0] │ │ cmpne r1, #0 │ │ beq 2316fb0 │ │ mov r0, r4 │ │ pop {r4, r5, fp, lr} │ │ bx r1 │ │ ldc2l 13, cr3, [r2, #676]! @ 0x2a4 │ │ - ldc2l 15, cr3, [r1, #912]! @ 0x390 │ │ + ldc2l 0, cr4, [r1, #68]! @ 0x44 │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r2 │ │ ldr r2, [r0, #716] @ 0x2cc │ │ mov r4, r3 │ │ ldrb r3, [r2, #24] │ │ cmp r3, #2 │ │ @@ -1002212,26 +1002212,26 @@ │ │ mov r0, r5 │ │ bl 231d2d8 │ │ b 231c4e8 │ │ mov r0, #160 @ 0xa0 │ │ str r0, [sp, #52] @ 0x34 │ │ b 231c420 │ │ ldc2l 13, cr6, [r2, #120]! @ 0x78 │ │ - ldc2l 6, cr1, [r1, #348]! @ 0x15c │ │ - ldc2l 5, cr11, [r0, #756]! @ 0x2f4 │ │ - ldc2l 2, cr3, [r1, #140]! @ 0x8c │ │ - ldc2l 2, cr13, [r0, #676]! @ 0x2a4 │ │ - ldc2l 14, cr2, [r1, #636]! @ 0x27c │ │ - ldc2l 14, cr2, [r1, #196]! @ 0xc4 │ │ - ldc2l 15, cr12, [r0, #868]! @ 0x364 │ │ - ldc2l 8, cr6, [r1, #348]! @ 0x15c │ │ + ldc2l 6, cr1, [r1, #528]! @ 0x210 │ │ + ldc2l 5, cr11, [r0, #936]! @ 0x3a8 │ │ + ldc2l 2, cr3, [r1, #320]! @ 0x140 │ │ + ldc2l 2, cr13, [r0, #856]! @ 0x358 │ │ + ldc2l 14, cr2, [r1, #816]! @ 0x330 │ │ + ldc2l 14, cr2, [r1, #376]! @ 0x178 │ │ + ldc2l 0, cr13, [r0, #24]! │ │ + vcmla.f32 d22, d17, d4, #270 │ │ ldrdeq fp, [r0], #-88 @ 0xffffffa8 │ │ ldc2l 1, cr15, [r1, #536]! @ 0x218 │ │ stc2l 5, cr13, [pc, #540]! @ 231c82c │ │ - ldc2l 2, cr1, [r1, #672]! @ 0x2a0 │ │ + ldc2l 2, cr1, [r1, #852]! @ 0x354 │ │ cmp r0, #0 │ │ bxeq lr │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ ldr r1, [r0, #316] @ 0x13c │ │ mov r4, r0 │ │ ldr r5, [r0, #100] @ 0x64 │ │ @@ -1002355,15 +1002355,15 @@ │ │ blx r5 │ │ cmp r0, #0 │ │ ldreq r1, [r4, #40] @ 0x28 │ │ ldreq r2, [sp, #4] │ │ streq r2, [r1] │ │ sub sp, fp, #8 │ │ pop {r4, r5, fp, pc} │ │ - ldc2l 9, cr0, [r1, #222]! @ 0xde @ │ │ + ldc2l 9, cr0, [r1, #312]! @ 0x138 @ │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [r0, #40] @ 0x28 │ │ ldr r0, [r0] │ │ cmp r0, #0 │ │ beq 231c87c │ │ @@ -1002388,15 +1002388,15 @@ │ │ cmp r0, #0 │ │ beq 231c870 │ │ ldr r1, [r4, #40] @ 0x28 │ │ ldr r2, [r0, #8] │ │ ldr r0, [r1] │ │ blx r2 │ │ b 231c870 │ │ - ldc2l 8, cr0, [r1, #732]! @ 0x2dc │ │ + vcmla.f32 q8, , q10, #270 │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [r0, #4] │ │ ldr r5, [r0, #320] @ 0x140 │ │ cmp r5, #0 │ │ beq 231c8e8 │ │ @@ -1002408,15 +1002408,15 @@ │ │ beq 231c8e8 │ │ ldr r1, [r5, #4] │ │ blx r1 │ │ ldr r1, [r4, #156] @ 0x9c │ │ str r0, [r1, #36] @ 0x24 │ │ mov r0, #0 │ │ pop {r4, r5, fp, pc} │ │ - ldc2l 8, cr0, [r1, #252]! @ 0xfc │ │ + vcmla.f32 q8, , q14, #270 │ │ ldr r0, [r0, #156] @ 0x9c │ │ cmp r0, #0 │ │ movne r1, #0 │ │ strne r1, [r0, #36] @ 0x24 │ │ bx lr │ │ nop {0} │ │ nop {0} │ │ @@ -1002746,15 +1002746,15 @@ │ │ mov r1, r2 │ │ mov r2, r3 │ │ mov r3, #0 │ │ blx r6 │ │ mov r0, r5 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2l 3, cr0, [r1, #268]! @ 0x10c │ │ + ldc2l 3, cr0, [r1, #448]! @ 0x1c0 │ │ ldr r1, [r0, #140] @ 0x8c │ │ cmp r1, #0 │ │ moveq r0, #0 │ │ bxeq lr │ │ mov r0, r1 │ │ ldrb r2, [r0], #1 │ │ cmp r2, #47 @ 0x2f │ │ @@ -1007269,15 +1007269,15 @@ │ │ bl 270b960 │ │ cmp r0, #0 │ │ moveq r0, #11 │ │ ldrne r0, [r0] │ │ strne r0, [r4, #28] │ │ movne r0, #0 │ │ pop {r4, sl, fp, pc} │ │ - ldc2l 4, cr5, [r1, #156]! @ 0x9c │ │ + ldc2l 4, cr5, [r1, #336]! @ 0x150 │ │ bx lr │ │ ldr r0, [pc, #4] @ 23214fc │ │ add r0, pc, r0 │ │ b 22f1a28 │ │ umaaleq r6, r0, r4, ip │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -1007945,23 +1007945,23 @@ │ │ mov r9, r0 │ │ b 2321e90 │ │ cmp r3, #0 │ │ streq r1, [sl, #24] │ │ b 2321cd8 │ │ ldc2l 13, cr4, [r2, #536]! @ 0x218 │ │ ldc2l 2, cr1, [r2, #296]! @ 0x128 │ │ - vcmla.f32 , q8, , #270 │ │ + ldc2l 9, cr13, [r0, #48]! @ 0x30 @ │ │ stc2l 12, cr5, [pc, #312]! @ 23220bc │ │ - ldc2l 5, cr1, [r0, #768]! @ 0x300 │ │ + ldc2l 5, cr1, [r0, #948]! @ 0x3b4 │ │ subeq r6, r0, r0, lsr #19 │ │ stc2l 1, cr3, [pc, #424]! @ 2322138 │ │ stc2l 0, cr3, [pc, #728]! @ 232226c │ │ stc2l 0, cr3, [pc, #872]! @ 2322300 │ │ ldc2l 1, cr9, [r1, #344]! @ 0x158 │ │ - ldc2l 11, cr4, [r1, #988]! @ 0x3dc @ │ │ + ldc2l 12, cr4, [r1, #144]! @ 0x90 │ │ cmp r0, #0 │ │ bxeq lr │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ ldr r5, [r0, #100] @ 0x64 │ │ ldr r0, [r0, #504] @ 0x1f8 │ │ @@ -1008667,15 +1008667,15 @@ │ │ str r6, [r4] │ │ str r0, [sl, #368] @ 0x170 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ stc2l 3, cr2, [pc, #136]! @ 2322b44 │ │ ldc2l 7, cr8, [r1, #120]! @ 0x78 │ │ ldc2l 10, cr7, [r2, #892]! @ 0x37c @ │ │ - vcmla.f32 d28, d0, d25, #270 │ │ + ldc2l 8, cr12, [r0, #344]! @ 0x158 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ mov r4, r1 │ │ ldr r9, [r1, #8] │ │ ldr r7, [r1, #16] │ │ ldr r1, [r1, #28] │ │ @@ -1010086,15 +1010086,15 @@ │ │ ldc2l 2, cr14, [r9, #928]! @ 0x3a0 │ │ ldc2l 2, cr14, [r9, #512]! @ 0x200 │ │ ldc2l 2, cr14, [r9, #48]! @ 0x30 │ │ ldc2l 1, cr14, [r9, #512]! @ 0x200 │ │ ldc2l 1, cr14, [r9, #224]! @ 0xe0 │ │ subeq r4, r0, ip, asr #24 │ │ ldc2l 3, cr7, [r1, #584]! @ 0x248 │ │ - ldc2l 7, cr1, [r0, #384]! @ 0x180 │ │ + ldc2l 7, cr1, [r0, #564]! @ 0x234 │ │ vcmla.f16 d21, d15, d15, #270 │ │ ldc2l 14, cr4, [r2, #168]! @ 0xa8 │ │ cmp r0, #0 │ │ bxeq lr │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ ldr r6, [r0, #132] @ 0x84 │ │ @@ -1010536,19 +1010536,19 @@ │ │ str r0, [sp, #8] │ │ movw r0, #3 │ │ movt r0, #1 │ │ str r0, [sp, #12] │ │ movw r0, #26979 @ 0x6963 │ │ movt r0, #30062 @ 0x756e │ │ b 23246ec │ │ - ldc2l 1, cr0, [r1, #916]! @ 0x394 │ │ - stc2l 10, cr6, [pc, #660]! @ 2324a94 @ │ │ - ldc2l 14, cr15, [r0, #952]! @ 0x3b8 │ │ + ldc2l 2, cr0, [r1, #72]! @ 0x48 │ │ + stc2l 10, cr6, [pc, #840]! @ 2324b48 @ │ │ + ldc2l 15, cr15, [r0, #108]! @ 0x6c │ │ ldc2l 9, cr5, [r2, #498]! @ 0x1f2 @ │ │ - ldc2l 8, cr4, [r0, #752]! @ 0x2f0 │ │ + vcmla.f32 q10, q8, , #270 │ │ subeq r3, r0, r4, lsr #30 │ │ cmp r0, #0 │ │ bxeq lr │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ ldr sl, [r0, #100] @ 0x64 │ │ @@ -1011912,15 +1011912,15 @@ │ │ ldc2l 3, cr13, [r9, #208]! @ 0xd0 │ │ ldc2l 15, cr12, [r9] │ │ ldc2l 15, cr12, [r9, #128]! @ 0x80 │ │ ldc2l 14, cr12, [r9, #528]! @ 0x210 │ │ ldc2l 14, cr12, [r9, #624]! @ 0x270 │ │ ldc2l 14, cr12, [r9, #320]! @ 0x140 │ │ ldc2l 2, cr3, [r1, #152]! @ 0x98 │ │ - stc2l 3, cr7, [pc, #628]! @ 2325ff0 │ │ + stc2l 3, cr7, [pc, #808]! @ 23260a4 │ │ stc2l 8, cr1, [pc, #592]! @ 2325fd0 │ │ ldc2l 7, cr0, [r2, #300]! @ 0x12c │ │ ldc2l 15, cr6, [r1, #236]! @ 0xec │ │ ldc2l 11, cr12, [r1, #748]! @ 0x2ec @ │ │ ldc2l 15, cr8, [r1, #692]! @ 0x2b4 │ │ ldc2l 4, cr4, [r2, #728]! @ 0x2d8 │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ @@ -1012712,18 +1012712,18 @@ │ │ mov r7, r0 │ │ mov r1, r5 │ │ b 2326538 │ │ ldc2l 10, cr4, [r1, #728]! @ 0x2d8 @ │ │ ldc2l 8, cr6, [r1, #96]! @ 0x60 │ │ ldc2l 4, cr2, [r2, #184]! @ 0xb8 │ │ ldc2l 2, cr14, [r1, #80]! @ 0x50 │ │ - ldc2l 10, cr10, [r0, #384]! @ 0x180 @ │ │ + ldc2l 10, cr10, [r0, #564]! @ 0x234 @ │ │ stc2l 13, cr2, [pc, #908]! @ 2326d8c │ │ ldc2l 7, cr2, [r1, #616]! @ 0x268 │ │ - stc2l 14, cr14, [pc, #448]! @ 2326bc8 │ │ + stc2l 14, cr14, [pc, #628]! @ 2326c7c │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #8 │ │ cmp r1, #255 @ 0xff │ │ bhi 2326a40 │ │ ldr r4, [pc, #148] @ 2326ab4 │ │ tst r1, #4 │ │ @@ -1014110,36 +1014110,36 @@ │ │ movw r0, #3 │ │ movt r0, #1 │ │ str r0, [sp, #60] @ 0x3c │ │ movw r0, #26979 @ 0x6963 │ │ movt r0, #30062 @ 0x756e │ │ str r0, [sp, #56] @ 0x38 │ │ b 2327ee4 │ │ - stc2l 11, cr5, [pc, #972]! @ 23283a0 @ │ │ + stc2l 12, cr5, [pc, #128]! @ 2328054 │ │ ldc2l 9, cr1, [r1, #364]! @ 0x16c @ │ │ ldc2l 12, cr3, [r1, #440]! @ 0x1b8 │ │ ldc2l 9, cr5, [r1, #288]! @ 0x120 @ │ │ ldc2l 3, cr1, [r2, #104]! @ 0x68 │ │ ldc2l 1, cr13, [r1] │ │ - ldc2l 12, cr9, [r0, #944]! @ 0x3b0 │ │ + ldc2l 13, cr9, [r0, #100]! @ 0x64 │ │ stc2l 1, cr2, [pc, #780]! @ 23282fc │ │ vcmla.f32 , , q15, #270 │ │ - stc2l 15, cr13, [pc, #960]! @ 23283b8 │ │ - stc2l 3, cr5, [pc, #452]! @ 23281c0 │ │ + stc2l 0, cr14, [pc, #116]! @ 232806c │ │ + stc2l 3, cr5, [pc, #632]! @ 2328274 │ │ stc2l 8, cr15, [lr, #592]! @ 0x250 │ │ ldc2l 6, cr14, [r1, #892]! @ 0x37c │ │ ldc2l 14, cr4, [r1, #892]! @ 0x37c │ │ ldc2l 11, cr10, [r1, #380]! @ 0x17c @ │ │ ldc2l 14, cr6, [r1, #820]! @ 0x334 │ │ ldc2l 3, cr2, [r2, #856]! @ 0x358 │ │ - ldc2l 10, cr12, [r0, #116]! @ 0x74 @ │ │ - stc2l 2, cr3, [pc, #884]! @ 2328390 │ │ - ldc2l 7, cr12, [r0, #152]! @ 0x98 │ │ + ldc2l 10, cr12, [r0, #296]! @ 0x128 @ │ │ + stc2l 3, cr3, [pc, #40]! @ 2328044 │ │ + ldc2l 7, cr12, [r0, #332]! @ 0x14c │ │ ldc2l 2, cr2, [r2, #180]! @ 0xb4 │ │ - ldc2l 0, cr1, [r0, #960]! @ 0x3c0 │ │ + ldc2l 1, cr1, [r0, #116]! @ 0x74 │ │ ldrdeq r0, [r0], #-120 @ 0xffffff88 │ │ ldrdeq r0, [r0], #-132 @ 0xffffff7c │ │ cmp r0, #0 │ │ bxeq lr │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ ldr r1, [r0, #140] @ 0x8c │ │ @@ -1015112,25 +1015112,25 @@ │ │ str r0, [r8] │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 3, cr10, [r1, #432]! @ 0x1b0 │ │ ldc2l 6, cr4, [r1, #488]! @ 0x1e8 │ │ eorseq pc, pc, r4, lsr #28 │ │ - ldc2l 3, cr12, [r0, #156]! @ 0x9c │ │ - ldc2l 4, cr8, [r0, #576]! @ 0x240 │ │ + ldc2l 3, cr12, [r0, #336]! @ 0x150 │ │ + ldc2l 4, cr8, [r0, #756]! @ 0x2f4 │ │ ldc2l 3, cr8, [r2, #816]! @ 0x330 │ │ ldc2l 4, cr9, [r9, #724]! @ 0x2d4 │ │ andeq r0, r0, r4, lsr r7 │ │ ldc2l 7, cr2, [r1, #544]! @ 0x220 │ │ - ldc2l 3, cr8, [r0, #336]! @ 0x150 │ │ + ldc2l 3, cr8, [r0, #516]! @ 0x204 │ │ ldc2l 6, cr6, [r1, #296]! @ 0x128 │ │ - ldc2l 2, cr8, [r0, #224]! @ 0xe0 │ │ + ldc2l 2, cr8, [r0, #404]! @ 0x194 │ │ stc2l 6, cr10, [lr, #120]! @ 0x78 │ │ - ldc2l 0, cr8, [r0, #656]! @ 0x290 │ │ + ldc2l 0, cr8, [r0, #836]! @ 0x344 │ │ ldc2l 7, cr7, [r2, #876]! @ 0x36c │ │ ldc2l 10, cr5, [r2, #784]! @ 0x310 @ │ │ stc2l 12, cr0, [pc, #580]! @ 23291f4 │ │ ldc2l 10, cr5, [r2, #512]! @ 0x200 @ │ │ ldc2l 6, cr7, [r2, #708]! @ 0x2c4 │ │ strdeq r2, [r0], -r0 │ │ cmp r0, #0 │ │ @@ -1015880,18 +1015880,18 @@ │ │ stc2l 10, cr15, [lr, #500]! @ 0x1f4 @ │ │ ldc2l 11, cr4, [r2, #112]! @ 0x70 @ │ │ stc2l 12, cr15, [lr, #932]! @ 0x3a4 │ │ ldc2l 4, cr6, [r2, #404]! @ 0x194 │ │ ldc2l 8, cr4, [r2, #336]! @ 0x150 │ │ ldc2l 4, cr6, [r2, #532]! @ 0x214 │ │ muleq r0, ip, pc @ │ │ - ldc2l 3, cr11, [r0, #344]! @ 0x158 │ │ + ldc2l 3, cr11, [r0, #524]! @ 0x20c │ │ ldc2l 1, cr9, [r1, #768]! @ 0x300 │ │ eorseq lr, pc, r0, asr #25 │ │ - ldc2l 4, cr7, [r0, #272]! @ 0x110 │ │ + ldc2l 4, cr7, [r0, #452]! @ 0x1c4 │ │ vcmla.f32 d24, d9, d28, #270 │ │ cmp r0, #0 │ │ mov r1, #0 │ │ ldrbne r3, [r0] │ │ cmpne r3, #0 │ │ bne 2329ba4 │ │ uxth r0, r1 │ │ @@ -1016789,18 +1016789,18 @@ │ │ eorseq lr, pc, r8, lsl #11 │ │ ldc2l 0, cr7, [r2, #320]! @ 0x140 │ │ ldc2l 1, cr8, [r9, #52]! @ 0x34 │ │ ldc2l 15, cr6, [r2, #736]! @ 0x2e0 │ │ ldc2l 0, cr8, [r9, #644]! @ 0x284 │ │ ldc2l 15, cr6, [r2, #576]! @ 0x240 │ │ ldc2l 3, cr8, [r1, #416]! @ 0x1a0 │ │ - stc2l 14, cr10, [pc, #116]! @ 232aa24 │ │ + stc2l 14, cr10, [pc, #296]! @ 232aad8 │ │ stc2l 14, cr14, [lr, #548]! @ 0x224 │ │ ldc2l 8, cr5, [r2, #836]! @ 0x344 │ │ - stc2l 8, cr2, [pc, #460]! @ 232ab88 │ │ + vcmla.f16 d18, d31, d16, #270 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #28 │ │ ldr r6, [fp, #8] │ │ mov r9, r1 │ │ mov r4, r0 │ │ mov r2, #7 │ │ @@ -1017856,34 +1017856,34 @@ │ │ cmp r0, #0 │ │ bne 232b108 │ │ ldr r1, [r6] │ │ mov r0, #0 │ │ str r0, [r6, #8] │ │ orr r1, r1, #2048 @ 0x800 │ │ b 232b9cc │ │ - ldc2l 1, cr6, [r0, #832]! @ 0x340 │ │ + ldc2l 1, cr6, [r0, #1012]! @ 0x3f4 │ │ ldc2l 15, cr5, [r2, #464]! @ 0x1d0 │ │ ldc2l 0, cr7, [r9, #372]! @ 0x174 │ │ ldc2l 6, cr3, [r2, #664]! @ 0x298 │ │ andeq r0, r0, r8, lsr fp │ │ andeq r0, r0, ip, lsr fp │ │ - ldc2l 13, cr9, [r0, #752]! @ 0x2f0 │ │ + ldc2l 13, cr9, [r0, #932]! @ 0x3a4 │ │ vcmla.f16 d30, d14, d24, #270 │ │ - ldc2l 15, cr5, [r0, #176]! @ 0xb0 │ │ + ldc2l 15, cr5, [r0, #356]! @ 0x164 │ │ ldc2l 2, cr5, [r2, #508]! @ 0x1fc │ │ - ldc2l 12, cr5, [r0, #160]! @ 0xa0 │ │ + ldc2l 12, cr5, [r0, #340]! @ 0x154 │ │ ldc2l 1, cr6, [r2, #16]! │ │ ldc2l 1, cr7, [r9, #340]! @ 0x154 │ │ ldc2l 4, cr8, [r2, #736]! @ 0x2e0 │ │ - stc2l 12, cr7, [pc, #60]! @ 232bad0 │ │ - ldc2l 10, cr5, [r0, #432]! @ 0x1b0 @ │ │ + stc2l 12, cr7, [pc, #240]! @ 232bb84 │ │ + ldc2l 10, cr5, [r0, #612]! @ 0x264 @ │ │ ldc2l 6, cr7, [r1, #516]! @ 0x204 │ │ - ldc2l 9, cr5, [r0, #288]! @ 0x120 @ │ │ - vcmla.f32 , q0, , #270 │ │ - vcmla.f32 , q0, q6, #270 │ │ + ldc2l 9, cr5, [r0, #378]! @ 0x17a @ │ │ + ldc2l 8, cr7, [r0, #584]! @ 0x248 │ │ + ldc2l 8, cr5, [r0, #484]! @ 0x1e4 │ │ ldc2l 6, cr13, [r1, #604]! @ 0x25c │ │ mov r1, r0 │ │ cmp r1, #0 │ │ ldrbne ip, [r1] │ │ mov r0, #0 │ │ cmpne ip, #0 │ │ bne 232bac4 │ │ @@ -1021788,17 +1021788,17 @@ │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ mov r2, r5 │ │ mov r3, r0 │ │ mov ip, sl │ │ b 232f474 │ │ ldc2l 4, cr12, [r0, #548]! @ 0x224 │ │ ldc2l 9, cr7, [r1, #284]! @ 0x11c @ │ │ - ldc2l 15, cr7, [r0, #732]! @ 0x2dc │ │ - stc2l 9, cr6, [pc, #356]! @ 232f934 @ │ │ - ldc2l 15, cr7, [r0, #540]! @ 0x21c │ │ + ldc2l 15, cr7, [r0, #912]! @ 0x390 │ │ + stc2l 9, cr6, [pc, #446]! @ 232f98e @ │ │ + ldc2l 15, cr7, [r0, #720]! @ 0x2d0 │ │ ldc2l 12, cr13, [r1, #48]! @ 0x30 │ │ ldc2l 11, cr13, [r1, #912]! @ 0x390 @ │ │ ldc2l 2, cr3, [r9, #96]! @ 0x60 │ │ ldc2l 9, cr3, [r9, #416]! @ 0x1a0 @ │ │ ldrdeq r6, [r0], -ip │ │ andeq r6, r0, r0, lsr #19 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ @@ -1042530,19 +1042530,19 @@ │ │ ldr r0, [sp, #8] │ │ add r1, pc, r1 │ │ strd r0, [r5, #116] @ 0x74 │ │ b 23438c0 │ │ stc2l 4, cr1, [sp, #60]! @ 0x3c │ │ ldc2l 13, cr0, [r8, #32]! │ │ eorseq r5, lr, r0, lsr #27 │ │ - stc2l 6, cr9, [sp, #624]! @ 0x270 │ │ + stc2l 6, cr9, [sp, #804]! @ 0x324 │ │ stc2l 6, cr7, [pc, #72]! @ 2343bf4 │ │ @ instruction: 0xfffff940 │ │ stc2l 3, cr13, [pc, #620]! @ 2343e20 │ │ - stc2l 0, cr3, [pc, #928]! @ 2343f58 │ │ + stc2l 1, cr3, [pc, #84]! @ 2343c0c │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r6, r1 │ │ ldr r1, [pc, #468] @ 2343da0 │ │ mov r5, r0 │ │ mov r0, r6 │ │ @@ -1042658,23 +1042658,23 @@ │ │ cmp r0, #0 │ │ bne 2343c64 │ │ ldr r1, [pc, #36] @ 2343db8 │ │ ldr r0, [sp, #4] │ │ add r1, pc, r1 │ │ strd r0, [r6, #116] @ 0x74 │ │ b 2343cd8 │ │ - stc2l 4, cr7, [lr, #280]! @ 0x118 │ │ + stc2l 4, cr7, [lr, #460]! @ 0x1cc │ │ @ instruction: 0xfffff7b8 │ │ stc2l 15, cr0, [sp, #812]! @ 0x32c │ │ eorseq r5, lr, r4, asr r9 │ │ - stc2l 2, cr9, [sp, #384]! @ 0x180 │ │ + stc2l 2, cr9, [sp, #564]! @ 0x234 │ │ stc2l 1, cr7, [pc, #856]! @ 2344114 │ │ @ instruction: 0xfffff734 │ │ stc2l 15, cr12, [pc, #380]! @ 2343f40 │ │ - stc2l 12, cr2, [pc, #688]! @ 2344078 │ │ + stc2l 12, cr2, [pc, #868]! @ 234412c │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #236 @ 0xec │ │ mov r7, r3 │ │ ldrh r3, [r1, #2] │ │ mov r8, #0 │ │ cmp r3, #0 │ │ @@ -1050850,15 +1050850,15 @@ │ │ mov r0, #1 │ │ vld1.32 {d16-d17}, [r5] │ │ strb r0, [r4, #65] @ 0x41 │ │ add r0, r4, #68 @ 0x44 │ │ vst1.32 {d16-d17}, [r0] │ │ mov r0, #0 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - stc2l 3, cr13, [sp, #424]! @ 0x1a8 │ │ + stc2l 3, cr13, [sp, #604]! @ 0x25c │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r2 │ │ mov r2, r1 │ │ ldr r1, [pc, #48] @ 234bdd8 │ │ mov r5, r0 │ │ mov r0, r2 │ │ @@ -1050869,15 +1050869,15 @@ │ │ cmp r1, #0 │ │ popne {r4, r5, fp, pc} │ │ add r0, r5, #68 @ 0x44 │ │ vld1.32 {d16-d17}, [r0] │ │ mov r0, #0 │ │ vst1.32 {d16-d17}, [r4] │ │ pop {r4, r5, fp, pc} │ │ - stc2l 2, cr13, [sp, #888]! @ 0x378 │ │ + stc2l 3, cr13, [sp, #44]! @ 0x2c │ │ mov r1, #0 │ │ strb r1, [r0, #70] @ 0x46 │ │ strh r1, [r0, #68] @ 0x44 │ │ mov r1, #8 │ │ str r1, [r0, #64] @ 0x40 │ │ mov r0, #0 │ │ bx lr │ │ @@ -1051465,15 +1051465,15 @@ │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldrb r0, [r5] │ │ strb r0, [r4, #70] @ 0x46 │ │ mov r0, #0 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ stc2l 6, cr12, [lr, #68]! @ 0x44 │ │ stc2l 6, cr6, [ip, #168]! @ 0xa8 │ │ - vcmla.f16 d18, d30, d28, #270 │ │ + stc2l 8, cr2, [lr, #868]! @ 0x364 │ │ stc2l 5, cr4, [pc, #472]! @ 234c90c │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r6, r1 │ │ ldr r1, [pc, #148] @ 234c7d8 │ │ mov r5, r0 │ │ mov r0, r6 │ │ @@ -1051511,15 +1051511,15 @@ │ │ b 234c7cc │ │ ldrb r0, [r5, #70] @ 0x46 │ │ str r0, [r4] │ │ mov r0, #0 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ stc2l 5, cr12, [lr, #132]! @ 0x84 │ │ stc2l 5, cr6, [ip, #232]! @ 0xe8 │ │ - stc2l 7, cr2, [lr, #752]! @ 0x2f0 │ │ + stc2l 7, cr2, [lr, #932]! @ 0x3a4 │ │ stc2l 4, cr4, [pc, #536]! @ 234ca04 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #32 │ │ mov lr, #6 │ │ cmp r1, #0 │ │ beq 234ca5c │ │ @@ -1054729,15 +1054729,15 @@ │ │ add r1, pc, r1 │ │ str r2, [r4, #8] │ │ strd r0, [r4, #20] │ │ ldr r0, [sp, #4] │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ strdeq r0, [r0], -r4 │ │ - stc2l 0, cr5, [lr, #912]! @ 0x390 │ │ + stc2l 1, cr5, [lr, #68]! @ 0x44 │ │ andeq r0, r0, r0, lsl #12 │ │ andeq r0, r0, r0, asr r3 │ │ andeq r0, r0, r8, asr #5 │ │ andeq r0, r0, r8, asr #6 │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #8 │ │ @@ -1054999,15 +1054999,15 @@ │ │ ldrls r1, [pc, #28] @ 234fe58 │ │ addls r1, pc, r1 │ │ ldrls r4, [r1, r0, lsl #2] │ │ b 234fd80 │ │ mov r4, #10 │ │ b 234fd80 │ │ strheq r0, [r0], -ip │ │ - stc2l 11, cr4, [lr, #816]! @ 0x330 @ │ │ + stc2l 11, cr4, [lr, #996]! @ 0x3e4 @ │ │ andeq r0, r0, ip, asr #1 │ │ ldc2l 4, cr1, [r0, #672]! @ 0x2a0 │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #8 │ │ mul r1, r2, r1 │ │ add r2, sp, #4 │ │ @@ -1060757,15 +1060757,15 @@ │ │ b 235560c │ │ mov r7, #0 │ │ b 2355838 │ │ mov r7, r8 │ │ mov r0, r7 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - stc2l 10, cr8, [sp, #16]! @ │ │ + stc2l 10, cr8, [sp, #196]! @ 0xc4 @ │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r5, r0 │ │ bl 2355988 │ │ ldr r1, [r5, #12] │ │ mov r0, #0 │ │ cmp r1, #0 │ │ @@ -1071273,15 +1071273,15 @@ │ │ cmp r3, #0 │ │ addne r3, r0, r3, lsl #3 │ │ add r1, pc, r1 │ │ mov r0, r4 │ │ bl 236aca0 │ │ add sp, sp, #8 │ │ pop {r4, pc} │ │ - stc2l 10, cr0, [ip, #116]! @ 0x74 @ │ │ + stc2l 10, cr0, [ip, #296]! @ 0x128 @ │ │ │ │ 0235fc70 : │ │ sub sp, sp, #16 │ │ str r2, [sp, #8] │ │ add r2, sp, #8 │ │ mov r4, r0 │ │ str r3, [sp, #12] │ │ @@ -1078006,15 +1078006,15 @@ │ │ cmp r0, #0 │ │ beq 2366554 │ │ mov r0, #1 │ │ pop {r4, r5, r6, r7, r8, pc} │ │ mov r0, r8 │ │ pop {r4, r5, r6, r7, r8, pc} │ │ vcmla.f32 , q3, q1, #270 │ │ - stc2l 11, cr2, [ip, #368]! @ 0x170 @ │ │ + stc2l 11, cr2, [ip, #548]! @ 0x224 @ │ │ cmn r1, #-67108862 @ 0xfc000002 │ │ bxhi lr │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ sub sp, sp, #12 │ │ ldr fp, [r0, #8] │ │ mov r7, r1 │ │ ldrb r1, [fp, #17] │ │ @@ -1080598,15 +1080598,15 @@ │ │ add r1, r8, r7, lsl #2 │ │ add r5, r5, r6 │ │ add r7, r7, #1 │ │ cmp r4, #0 │ │ str r0, [r1, #288] @ 0x120 │ │ bne 2368dd0 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ - stc2l 1, cr6, [ip, #568]! @ 0x238 │ │ + stc2l 1, cr6, [ip, #748]! @ 0x2ec │ │ push {r4, r5, fp, lr} │ │ mov r5, r1 │ │ mov r1, r2 │ │ mov r4, r0 │ │ bl 2367a00 │ │ cmp r0, #0 │ │ ldrne r1, [r0, #4] │ │ @@ -1082101,15 +1082101,15 @@ │ │ bne 236a570 │ │ subs r1, r1, #1 │ │ bxeq lr │ │ b 236a570 │ │ ldr r0, [pc, #4] @ 236a594 │ │ add r0, pc, r0 │ │ bx lr │ │ - stc2l 0, cr6, [fp, #932]! @ 0x3a4 │ │ + stc2l 1, cr6, [fp, #88]! @ 0x58 │ │ push {r4, lr} │ │ ldr lr, [r0, #4] │ │ mov ip, r0 │ │ mov r0, #0 │ │ cmn lr, #9 │ │ bne 236a634 │ │ ldr ip, [ip] │ │ @@ -1082145,16 +1082145,16 @@ │ │ bne 236a620 │ │ subs r1, r1, #1 │ │ bne 236a620 │ │ pop {r4, pc} │ │ ldr r0, [pc, #4] @ 236a644 │ │ add r0, pc, r0 │ │ pop {r4, pc} │ │ - stc2l 0, cr6, [fp, #228]! @ 0xe4 │ │ - stc2l 0, cr6, [fp, #612]! @ 0x264 │ │ + stc2l 0, cr6, [fp, #408]! @ 0x198 │ │ + stc2l 0, cr6, [fp, #792]! @ 0x318 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ sub sp, sp, #20 │ │ str r3, [sp, #4] │ │ mov r4, r1 │ │ str r2, [sp, #12] │ │ add sl, r0, #64 @ 0x40 │ │ add r6, sp, #16 │ │ @@ -1082323,20 +1082323,20 @@ │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldr r0, [pc, #24] @ 236a914 │ │ add r0, pc, r0 │ │ add sp, sp, #20 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 9, cr11, [r6, #96]! @ 0x60 @ │ │ vcmla.f32 d27, d22, d24, #270 │ │ - stc2l 9, cr1, [fp, #482]! @ 0x1e2 @ │ │ - vcmla.f16 d30, d27, d3, #270 │ │ + stc2l 10, cr1, [fp, #120]! @ 0x78 @ │ │ + stc2l 8, cr14, [fp, #704]! @ 0x2c0 │ │ stc2l 3, cr4, [sp, #704]! @ 0x2c0 │ │ - stc2l 13, cr5, [fp, #612]! @ 0x264 │ │ + stc2l 13, cr5, [fp, #792]! @ 0x318 │ │ stc2l 13, cr9, [sp, #424]! @ 0x1a8 │ │ - stc2l 6, cr6, [ip, #100]! @ 0x64 │ │ + stc2l 6, cr6, [ip, #280]! @ 0x118 │ │ push {r4, r5, r6, r7, r8, lr} │ │ mov r8, r2 │ │ mov r2, r1 │ │ ldr r1, [r0, #28] │ │ mov r4, #0 │ │ cmp r1, r2 │ │ bcs 236aa10 │ │ @@ -1082391,15 +1082391,15 @@ │ │ ldr r4, [pc, #20] @ 236aa1c │ │ add r0, r0, #20 │ │ str r0, [r8] │ │ add r4, pc, r4 │ │ mov r0, r4 │ │ pop {r4, r5, r6, r7, r8, pc} │ │ ldc2l 6, cr11, [r6, #64]! @ 0x40 │ │ - vcmla.f16 q8, , q9, #270 │ │ + vcmla.f16 d16, d27, d15, #270 │ │ push {r4, r5, r6, lr} │ │ ldrb r3, [r1, #6] │ │ mov ip, r0 │ │ mvn r0, #0 │ │ cmp r3, #0 │ │ popne {r4, r5, r6, pc} │ │ cmp r2, #0 │ │ @@ -1082548,17 +1082548,17 @@ │ │ cmn r6, #1 │ │ ldr r1, [pc, #28] @ 236ac9c │ │ add r2, pc, r2 │ │ add r1, pc, r1 │ │ movne r1, r2 │ │ pop {r4, r5, r6, lr} │ │ b 270ae50 │ │ - stc2l 13, cr9, [ip, #444]! @ 0x1bc │ │ + stc2l 13, cr9, [ip, #624]! @ 0x270 │ │ stc2l 0, cr6, [sp, #28]! │ │ - stc2l 4, cr6, [fp, #668]! @ 0x29c │ │ + stc2l 4, cr6, [fp, #848]! @ 0x350 │ │ stc2l 15, cr13, [ip, #960]! @ 0x3c0 │ │ push {r4, r5, r6, r7, fp, lr} │ │ sub sp, sp, #64 @ 0x40 │ │ mov r4, r1 │ │ cmp r2, #0 │ │ beq 236acc4 │ │ ldr r5, [r2] │ │ @@ -1082622,15 +1082622,15 @@ │ │ str r4, [sp] │ │ bl 237140c │ │ add sp, sp, #64 @ 0x40 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ ldr r1, [r7, r1, lsl #2] │ │ b 236ad2c │ │ stc2l 14, cr9, [sl, #200]! @ 0xc8 │ │ - stc2l 4, cr2, [ip, #468]! @ 0x1d4 │ │ + stc2l 4, cr2, [ip, #648]! @ 0x288 │ │ push {r4, r5, r6, lr} │ │ ldrd r4, [r1, #40] @ 0x28 │ │ mov r3, #0 │ │ ldr r6, [r1, #8] │ │ ldr ip, [r4, #16] │ │ cmp r6, r2 │ │ bcc 236ae30 │ │ @@ -1082924,15 +1082924,15 @@ │ │ subs r1, r1, #1 │ │ bne 236b240 │ │ b 236b1cc │ │ ldr r9, [sp, #4] │ │ b 236b1cc │ │ stc2l 6, cr7, [sp, #120]! @ 0x78 │ │ ldc2l 14, cr10, [r6, #768]! @ 0x300 │ │ - stc2l 11, cr7, [fp, #884]! @ 0x374 @ │ │ + stc2l 12, cr7, [fp, #40]! @ 0x28 │ │ │ │ 0236b26c : │ │ push {r4, lr} │ │ sub sp, sp, #8 │ │ mov r3, r2 │ │ mov r4, r0 │ │ mov r0, #0 │ │ @@ -1083245,19 +1083245,19 @@ │ │ cmp r1, r3 │ │ bcc 236b658 │ │ mov r0, r5 │ │ bl 236c958 │ │ mov r0, #1 │ │ add sp, sp, #20 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - stc2l 9, cr5, [ip, #238]! @ 0xee @ │ │ + stc2l 9, cr5, [ip, #328]! @ 0x148 @ │ │ stc2l 13, cr10, [sp, #608]! @ 0x260 │ │ stc2l 11, cr0, [sp, #944]! @ 0x3b0 @ │ │ stc2l 14, cr2, [lr, #96]! @ 0x60 │ │ - stc2l 1, cr5, [fp, #900]! @ 0x384 │ │ + stc2l 2, cr5, [fp, #56]! @ 0x38 │ │ │ │ 0236b778 : │ │ mov r3, #0 │ │ b 236b2bc │ │ │ │ 0236b780 : │ │ push {r4, r5, r6, r7, r8, lr} │ │ @@ -1083669,15 +1083669,15 @@ │ │ pop {r4, r6, r7, pc} │ │ mov r0, r4 │ │ mov r1, #1 │ │ bl 2365a38 │ │ mov r1, r4 │ │ b 236bda4 │ │ stc2l 14, cr4, [sp, #652]! @ 0x28c │ │ - stc2l 3, cr5, [fp, #408]! @ 0x198 │ │ + stc2l 3, cr5, [fp, #588]! @ 0x24c │ │ │ │ 0236bdf8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ sub sp, sp, #108 @ 0x6c │ │ mov r5, r1 │ │ mov r8, r0 │ │ ldrd r0, [r0, #16] │ │ @@ -1083929,22 +1083929,22 @@ │ │ sub r0, r1, r0 │ │ ldr r1, [sp, #4] │ │ rsb r1, r1, r0, asr #3 │ │ mov r0, r8 │ │ bl 270bc60 │ │ add sp, sp, #108 @ 0x6c │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - stc2l 15, cr0, [fp, #444]! @ 0x1bc │ │ - stc2l 2, cr13, [fp, #488]! @ 0x1e8 │ │ - stc2l 15, cr2, [ip, #788]! @ 0x314 │ │ - stc2l 3, cr15, [sl, #324]! @ 0x144 │ │ + stc2l 15, cr0, [fp, #624]! @ 0x270 │ │ + stc2l 2, cr13, [fp, #668]! @ 0x29c │ │ + stc2l 15, cr2, [ip, #968]! @ 0x3c8 │ │ + stc2l 3, cr15, [sl, #504]! @ 0x1f8 │ │ stc2l 4, cr0, [lr, #524]! @ 0x20c │ │ stc2l 6, cr8, [sp, #968]! @ 0x3c8 │ │ stc2l 4, cr11, [sl, #704]! @ 0x2c0 │ │ - stc2l 15, cr4, [ip, #272]! @ 0x110 │ │ + stc2l 15, cr4, [ip, #452]! @ 0x1c4 │ │ stc2l 2, cr13, [sl, #932]! @ 0x3a4 │ │ stc2l 10, cr12, [ip, #792]! @ 0x318 @ │ │ stc2l 2, cr11, [sl, #464]! @ 0x1d0 │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ add r1, pc, #168 @ 0xa8 │ │ vld1.64 {d18-d19}, [r0] │ │ @@ -1086196,15 +1086196,15 @@ │ │ add r0, pc, r0 │ │ ldr r1, [r8] │ │ bl 270bcd0 │ │ ldr r1, [r8] │ │ mov r0, #10 │ │ bl 270ac20 │ │ b 236e4a0 │ │ - stc2l 11, cr12, [fp, #480]! @ 0x1e0 @ │ │ + stc2l 11, cr12, [fp, #660]! @ 0x294 @ │ │ eorseq r9, ip, r0, ror #17 │ │ stc2l 6, cr10, [sl, #312]! @ 0x138 │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ push {fp, lr} │ │ vpush {d8} │ │ ldr ip, [sp, #16] │ │ vmov d8, r0, r1 │ │ @@ -1089033,15 +1089033,15 @@ │ │ mov r0, r9 │ │ mov r1, r8 │ │ bl 23669d4 │ │ add sp, sp, #32 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ stc2l 12, cr1, [sl, #656]! @ 0x290 │ │ stc2l 1, cr1, [sl, #120]! @ 0x78 │ │ - stc2l 1, cr13, [fp, #720]! @ 0x2d0 │ │ + stc2l 1, cr13, [fp, #900]! @ 0x384 │ │ ldrshteq r8, [fp], -ip │ │ stc2l 11, cr6, [sp, #1008]! @ 0x3f0 @ │ │ push {r4, r5, fp, lr} │ │ sub sp, sp, #16 │ │ add r5, sp, #5 │ │ mov r4, r0 │ │ mov r0, r5 │ │ @@ -1090198,15 +1090198,15 @@ │ │ ldr r1, [r8, r1, lsl #2] │ │ ldr r2, [sp, #224] @ 0xe0 │ │ cmp r1, r2 │ │ bne 23725a4 │ │ sub r4, r4, #9 │ │ b 23723c0 │ │ stc2l 6, cr3, [sl, #816]! @ 0x330 │ │ - stc2l 12, cr5, [fp, #492]! @ 0x1ec │ │ + stc2l 12, cr5, [fp, #672]! @ 0x2a0 │ │ mov r3, r1 │ │ mov r0, ip │ │ str r4, [sp, #88] @ 0x58 │ │ ldr r1, [r0] │ │ movw r0, #15241 @ 0x3b89 │ │ ldr r2, [r8, r3, lsl #2] │ │ movt r0, #21990 @ 0x55e6 │ │ @@ -1099279,15 +1099279,15 @@ │ │ strd r0, [r4, #52] @ 0x34 │ │ b 237ae40 │ │ ldr r2, [pc, #12] @ 237aec0 │ │ mov r0, r4 │ │ mov r1, #67108864 @ 0x4000000 │ │ add r2, pc, r2 │ │ bl 237d8f4 │ │ - stc2l 3, cr0, [sl, #792]! @ 0x318 │ │ + stc2l 3, cr0, [sl, #972]! @ 0x3cc │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ sub sp, sp, #124 @ 0x7c │ │ mov r4, r0 │ │ ldr r0, [r0, #108] @ 0x6c │ │ add r0, r0, #1 │ │ str r0, [r4, #108] @ 0x6c │ │ cmp r0, #199 @ 0xc7 │ │ @@ -1101911,15 +1101911,15 @@ │ │ add r2, r6, r2 │ │ ldr r7, [r3], #8 │ │ subs r1, r1, #1 │ │ sub r7, r7, r0 │ │ str r7, [r2], #4 │ │ bne 237d7c8 │ │ b 237d6a8 │ │ - stc2l 12, cr1, [sl, #944]! @ 0x3b0 │ │ + stc2l 13, cr1, [sl, #100]! @ 0x64 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ sub sp, sp, #4 │ │ cmn r1, #1 │ │ beq 237d8e0 │ │ ldr ip, [sp, #40] @ 0x28 │ │ movw r9, #32768 @ 0x8000 │ │ ldr r6, [r0, #52] @ 0x34 │ │ @@ -1106358,15 +1106358,15 @@ │ │ mov r1, #200 @ 0xc8 │ │ ldr r0, [r5] │ │ add r2, pc, r2 │ │ bl 237d8f4 │ │ ldr r0, [r7, #4] │ │ movw r1, #2426 @ 0x97a │ │ bl 237d938 │ │ - stc2l 12, cr0, [fp, #884]! @ 0x374 │ │ + stc2l 13, cr0, [fp, #40]! @ 0x28 │ │ │ │ 02381d60 : │ │ push {r4, r5, r6, lr} │ │ sub sp, sp, #120 @ 0x78 │ │ mov r4, r0 │ │ ldr r0, [pc, #132] @ 2381df8 │ │ ldr r5, [pc, #132] @ 2381dfc │ │ @@ -1106620,16 +1106620,16 @@ │ │ mov r0, r8 │ │ add sp, sp, #1152 @ 0x480 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ mov r0, r4 │ │ bl 2364364 │ │ b 23820c0 │ │ stc2l 8, cr0, [ip, #480]! @ 0x1e0 │ │ - stc2l 5, cr14, [sl, #264]! @ 0x108 │ │ - stc2l 10, cr0, [fp, #80]! @ 0x50 @ │ │ + stc2l 5, cr14, [sl, #444]! @ 0x1bc │ │ + stc2l 10, cr0, [fp, #260]! @ 0x104 @ │ │ stc2l 2, cr12, [ip, #312]! @ 0x138 │ │ eorseq r9, fp, r4, lsr r3 │ │ andeq r0, r0, ip, lsl r1 │ │ @ instruction: 0xfffffd94 │ │ stc2l 10, cr6, [r9, #1000]! @ 0x3e8 @ │ │ stc2l 3, cr5, [r9, #232]! @ 0xe8 │ │ push {r4, r5, fp, lr} │ │ @@ -1109289,15 +1109289,15 @@ │ │ ldrh r2, [r0, #72] @ 0x48 │ │ strh r2, [r4, #72] @ 0x48 │ │ add r1, r1, #1 │ │ strh r1, [r0, #60] @ 0x3c │ │ strh r8, [r0, #72] @ 0x48 │ │ b 2384918 │ │ stc2l 8, cr1, [ip, #1008]! @ 0x3f0 │ │ - stc2l 4, cr0, [fp, #36]! @ 0x24 │ │ + stc2l 4, cr0, [fp, #216]! @ 0xd8 │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ mov r6, r1 │ │ mov r4, r0 │ │ mov r7, #126 @ 0x7e │ │ movw r5, #1532 @ 0x5fc │ │ bl 2702870 │ │ mov r9, r0 │ │ @@ -1147580,15 +1147580,15 @@ │ │ b 23a62a4 │ │ add r0, r6, r1, lsl #3 │ │ ldrsb r0, [r0, #6] │ │ cmn r0, #1 │ │ ble 23aab94 │ │ uxtb r8, r0 │ │ b 23aaba8 │ │ - stc2l 14, cr15, [r7, #908]! @ 0x38c │ │ + stc2l 15, cr15, [r7, #64]! @ 0x40 │ │ add r0, sp, #112 @ 0x70 │ │ movw r1, #8191 @ 0x1fff │ │ bl 23adfd8 │ │ mov r8, r0 │ │ mov r0, #1 │ │ lsl r0, r0, r8 │ │ ldr r1, [sp, #260] @ 0x104 │ │ @@ -1148261,15 +1148261,15 @@ │ │ cmp r2, #0 │ │ bmi 23aabe4 │ │ uxtb r1, r2 │ │ bic r0, r7, r0, lsl r1 │ │ str r0, [sp, #264] @ 0x108 │ │ ldrb r0, [r5, #6] │ │ b 23ab3c0 │ │ - stc2l 4, cr15, [r7, #716]! @ 0x2cc │ │ + stc2l 4, cr15, [r7, #896]! @ 0x380 │ │ lsl r9, r0, r8 │ │ ldrh r0, [r5, #2] │ │ ldr r2, [sp, #328] @ 0x148 │ │ cmp r2, r0 │ │ bcs 23ab3b0 │ │ sxth r2, r0 │ │ cmp r2, #0 │ │ @@ -1158764,17 +1158764,17 @@ │ │ movt r2, #25964 @ 0x656c │ │ str r2, [r1, #4] │ │ str r1, [sp, #48] @ 0x30 │ │ tst r0, #33554432 @ 0x2000000 │ │ beq 23b4f90 │ │ b 23b4f38 │ │ stc2l 12, cr3, [r6, #8]! │ │ - stc2l 7, cr2, [r7, #736]! @ 0x2e0 │ │ + stc2l 7, cr2, [r7, #916]! @ 0x394 │ │ stc2l 4, cr11, [r9, #844]! @ 0x34c │ │ - stc2l 14, cr1, [r8, #648]! @ 0x288 │ │ + stc2l 14, cr1, [r8, #828]! @ 0x33c │ │ push {r4, r5, r6, r7, r8, r9, sl, lr} │ │ sub sp, sp, #24 │ │ ldr r1, [sp, #56] @ 0x38 │ │ movw r6, #19532 @ 0x4c4c │ │ mov ip, sp │ │ strh r6, [sp, #22] │ │ cmp r1, #0 │ │ @@ -1159002,16 +1159002,16 @@ │ │ mvn r1, #4 │ │ strd r0, [r6] │ │ mov r1, #247 @ 0xf7 │ │ ldr r0, [r4, #8] │ │ strb r1, [r5, #6] │ │ str r5, [r0, #440] @ 0x1b8 │ │ pop {r4, r5, r6, pc} │ │ - stc2l 6, cr13, [r7, #908]! @ 0x38c │ │ - stc2l 0, cr0, [r7, #72]! @ 0x48 │ │ + stc2l 7, cr13, [r7, #64]! @ 0x40 │ │ + stc2l 0, cr0, [r7, #252]! @ 0xfc │ │ push {r4, r5, r6, r7, fp, lr} │ │ ldr r4, [r0, #252] @ 0xfc │ │ cmp r4, #0 │ │ beq 23b5444 │ │ mov r5, r0 │ │ mov r0, r4 │ │ bl 23b7de0 │ │ @@ -1164747,15 +1164747,15 @@ │ │ b 23bac44 │ │ eorseq pc, r6, r4, lsr r9 @ │ │ ldc2l 1, cr11, [r1, #40]! @ 0x28 │ │ stc2l 15, cr13, [r7, #900]! @ 0x384 │ │ stc2l 7, cr14, [r5, #640]! @ 0x280 │ │ mlaseq r8, ip, r7, sp │ │ eorseq sp, r8, ip, ror #14 │ │ - stc2l 4, cr12, [r6, #600]! @ 0x258 │ │ + stc2l 4, cr12, [r6, #780]! @ 0x30c │ │ mov r2, r1 │ │ cmp r1, #256 @ 0x100 │ │ blt 23bad9c │ │ ldr r0, [pc, #64] @ 23badd0 │ │ add r0, pc, r0 │ │ add r0, r0, r2, lsl #2 │ │ ldr r0, [r0, #-1024] @ 0xfffffc00 │ │ @@ -1169240,15 +1169240,15 @@ │ │ str r2, [r7, #12] │ │ str r7, [r3, #36] @ 0x24 │ │ b 23bf040 │ │ mov r0, sl │ │ movw r1, #1993 @ 0x7c9 │ │ mov r2, r7 │ │ bl 235f99c │ │ - stc2l 10, cr5, [r7, #204]! @ 0xcc @ │ │ + stc2l 10, cr5, [r7, #384]! @ 0x180 @ │ │ push {r4, r5, fp, lr} │ │ mov r4, r2 │ │ mov r2, r3 │ │ mov r5, r0 │ │ bl 2704cb0 │ │ ldr r0, [r5, #20] │ │ ldr r0, [r0, #-8] │ │ @@ -1171627,15 +1171627,15 @@ │ │ ldr r0, [r4, #8] │ │ ldr r1, [r0, #616] @ 0x268 │ │ bic r1, r1, #16 │ │ str r1, [r0, #616] @ 0x268 │ │ mov r0, #3 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ stc2l 4, cr1, [r5, #92]! @ 0x5c │ │ - vcmla.f16 d27, d22, d9, #270 │ │ + stc2l 8, cr11, [r6, #728]! @ 0x2d8 │ │ │ │ 023c18f4 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ mov r4, r0 │ │ adds r0, r1, #1 │ │ bcc 23c1968 │ │ bl 2702870 │ │ @@ -1171699,15 +1171699,15 @@ │ │ add r1, r0, #8 │ │ str r1, [r4, #20] │ │ strd r6, [r0] │ │ mov r0, #3 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ stc2l 14, cr0, [r8, #784]! @ 0x310 │ │ stc2l 11, cr13, [r8, #844]! @ 0x34c @ │ │ - vcmla.f16 d27, d6, d13, #270 │ │ + stc2l 8, cr11, [r6, #232]! @ 0xe8 │ │ │ │ 023c1a0c : │ │ push {r4, r5, r6, r7, r8, lr} │ │ mov r8, r3 │ │ mov r6, r2 │ │ mov r4, r0 │ │ bl 2705050 │ │ @@ -1171816,15 +1171816,15 @@ │ │ mvn r1, #1 │ │ pop {r4, r5, r6, r7, fp, lr} │ │ b 2705010 │ │ mov r0, r4 │ │ movw r1, #1993 @ 0x7c9 │ │ mov r2, r5 │ │ bl 235f99c │ │ - stc2l 14, cr2, [r7, #412]! @ 0x19c │ │ + stc2l 14, cr2, [r7, #592]! @ 0x250 │ │ │ │ 023c1bd0 : │ │ push {r4, r5, r6, lr} │ │ mov r4, r3 │ │ mov r5, r2 │ │ mov r6, r0 │ │ cmp r1, #0 │ │ @@ -1171892,15 +1171892,15 @@ │ │ subs r4, r4, #1 │ │ bne 23c1cc4 │ │ b 23c1c8c │ │ mvn r1, r9 │ │ mov r0, r5 │ │ pop {r4, r5, r6, r7, r8, r9, fp, lr} │ │ b 2704b70 │ │ - stc2l 13, cr4, [r7, #172]! @ 0xac │ │ + stc2l 13, cr4, [r7, #352]! @ 0x160 │ │ │ │ 023c1cf0 : │ │ push {r4, r5, fp, lr} │ │ mov r5, r2 │ │ mov r4, r0 │ │ cmp r1, #0 │ │ beq 23c1d40 │ │ @@ -1171942,15 +1171942,15 @@ │ │ add r5, r5, #8 │ │ cmp r0, #0 │ │ bne 23c1d6c │ │ mov r0, r4 │ │ mvn r1, #0 │ │ pop {r4, r5, fp, lr} │ │ b 2704b70 │ │ - stc2l 12, cr4, [r7, #236]! @ 0xec │ │ + stc2l 12, cr4, [r7, #416]! @ 0x1a0 │ │ │ │ 023c1db0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ sub sp, sp, #20 │ │ sub sp, sp, #1024 @ 0x400 │ │ mov r8, r0 │ │ mov r0, r2 │ │ @@ -1172554,18 +1172554,18 @@ │ │ ldr r3, [pc, #52] @ 23c2704 │ │ add r1, pc, r1 │ │ add r2, pc, r2 │ │ add r3, pc, r3 │ │ bl 23bef14 │ │ mov r0, #2 │ │ pop {r4, r5, r6, r8, r9, pc} │ │ - stc2l 12, cr8, [r5, #640]! @ 0x280 │ │ - stc2l 8, cr14, [r6, #976]! @ 0x3d0 │ │ - stc2l 3, cr0, [r7, #988]! @ 0x3dc │ │ - stc2l 9, cr12, [r6, #222]! @ 0xde @ │ │ + stc2l 12, cr8, [r5, #820]! @ 0x334 │ │ + stc2l 9, cr14, [r6, #66]! @ 0x42 @ │ │ + stc2l 4, cr0, [r7, #144]! @ 0x90 │ │ + stc2l 9, cr12, [r6, #312]! @ 0x138 @ │ │ ldc2l 2, cr5, [r1, #400]! @ 0x190 │ │ ldrsbteq r7, [r6], -ip │ │ stc2l 12, cr3, [r8, #308]! @ 0x134 │ │ ldc2l 3, cr5, [r1, #520]! @ 0x208 │ │ eorseq r7, r6, r4, lsl pc │ │ mov r1, #1 │ │ mov r4, r0 │ │ @@ -1173714,18 +1173714,18 @@ │ │ mov r0, #1 │ │ pop {fp, pc} │ │ mov r1, #1 │ │ movw r2, #566 @ 0x236 │ │ bl 235faec │ │ stc2l 11, cr5, [r5, #760]! @ 0x2f8 @ │ │ stc2l 3, cr5, [r7, #992]! @ 0x3e0 │ │ - stc2l 5, cr9, [r5, #820]! @ 0x334 │ │ + stc2l 5, cr9, [r5, #1000]! @ 0x3e8 │ │ stc2l 4, cr0, [r8, #764]! @ 0x2fc │ │ stc2l 3, cr5, [r7, #688]! @ 0x2b0 │ │ - stc2l 5, cr9, [r5, #724]! @ 0x2d4 │ │ + stc2l 5, cr9, [r5, #904]! @ 0x388 │ │ push {r4, lr} │ │ mov r4, r0 │ │ bl 270bdb0 │ │ cmp r0, #0 │ │ ldrne r0, [r4, #20] │ │ addne r1, r0, #8 │ │ strne r1, [r4, #20] │ │ @@ -1173911,15 +1173911,15 @@ │ │ sbcsge r7, r2, r7, asr r7 │ │ stclpl 6, cr10, [sl, #-316] @ 0xfffffec4 │ │ strbvc r2, [sl], -ip, ror #18 │ │ streq sp, [sl, -sl, lsr #29] │ │ @ instruction: 0x51220704 │ │ ldrge fp, [r7, r7, lsr #18]! │ │ bcs 2d89ae8 <_nl_msg_cat_cntr@@Base+0x5f8548> │ │ - stc2l 10, cr10, [r6, #524]! @ 0x20c @ │ │ + stc2l 10, cr10, [r6, #704]! @ 0x2c0 @ │ │ ldc2l 14, cr3, [r1, #732]! @ 0x2dc │ │ eorseq r6, r6, ip, lsr #20 │ │ push {fp, lr} │ │ mov r1, #1 │ │ bl 23bf5c8 │ │ mov r0, #0 │ │ pop {fp, pc} │ │ @@ -1174205,15 +1174205,15 @@ │ │ ldr r1, [pc, #32] @ 23c40ac │ │ ldr r2, [pc, #32] @ 23c40b0 │ │ add r1, pc, r1 │ │ ldr r2, [pc, r2] │ │ bl 23bf3e0 │ │ mov r0, #1 │ │ pop {r4, r5, fp, pc} │ │ - stc2l 11, cr0, [r6, #424]! @ 0x1a8 @ │ │ + stc2l 11, cr0, [r6, #604]! @ 0x25c @ │ │ ldc2l 11, cr3, [r1, #292]! @ 0x124 @ │ │ ldrshteq r6, [r6], -r8 │ │ stc2l 3, cr5, [r5, #824]! @ 0x338 │ │ ldrsbteq r7, [r7], -ip │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ mov r1, #1 │ │ mov r4, r0 │ │ @@ -1174738,15 +1174738,15 @@ │ │ bl 235f99c │ │ mov r0, r7 │ │ mov r1, #3 │ │ mov r2, #656 @ 0x290 │ │ bl 235faec │ │ movw r1, #1909 @ 0x775 │ │ bl 235f9d8 │ │ - stc2l 12, cr6, [r5, #236]! @ 0xec │ │ + stc2l 12, cr6, [r5, #416]! @ 0x1a0 │ │ ldc2l 6, cr1, [r1, #472]! @ 0x1d8 │ │ push {r4, r5, fp, lr} │ │ mov r4, r0 │ │ mov r0, #0 │ │ ldr r5, [r4, #8] │ │ rsb r3, r0, #0 │ │ mov r0, r4 │ │ @@ -1174931,16 +1174931,16 @@ │ │ bl 23c5660 │ │ add r7, r7, #1 │ │ cmp r5, r7 │ │ bne 23c4bcc │ │ mov r0, r5 │ │ add sp, sp, #292 @ 0x124 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - stc2l 7, cr6, [r5, #796]! @ 0x31c │ │ - stc2l 6, cr6, [r5, #940]! @ 0x3ac │ │ + stc2l 7, cr6, [r5, #976]! @ 0x3d0 │ │ + stc2l 7, cr6, [r5, #96]! @ 0x60 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ sub sp, sp, #12 │ │ mov r9, r0 │ │ ldr r0, [r0, #16] │ │ mov r8, r1 │ │ cmp r0, #199 @ 0xc7 │ │ add r1, r0, #1 │ │ @@ -1175696,15 +1175696,15 @@ │ │ bl 23c5660 │ │ add r7, r7, #1 │ │ cmp r6, r7 │ │ bne 23c57c0 │ │ mov r0, r6 │ │ add sp, sp, #280 @ 0x118 │ │ pop {r4, r5, r6, r7, r8, r9, sl, pc} │ │ - stc2l 10, cr5, [r5, #1020]! @ 0x3fc @ │ │ + stc2l 11, cr5, [r5, #176]! @ 0xb0 @ │ │ │ │ 023c57f0 : │ │ push {r4, lr} │ │ ldr r1, [pc, #96] @ 23c585c │ │ mov r4, r0 │ │ ldr r2, [pc, #92] @ 23c5860 │ │ ldr r3, [pc, #92] @ 23c5864 │ │ @@ -1175729,15 +1175729,15 @@ │ │ mov r0, r4 │ │ bl 23bf3e0 │ │ mov r0, #1 │ │ pop {r4, pc} │ │ stc2l 11, cr6, [r7, #736]! @ 0x2e0 @ │ │ ldc2l 3, cr2, [r1, #828]! @ 0x33c │ │ eorseq r4, r6, r4, asr #28 │ │ - stc2l 9, cr11, [r5, #22]! @ │ │ + stc2l 9, cr11, [r5, #112]! @ 0x70 @ │ │ andeq r0, r0, r8, asr #32 │ │ stc2l 12, cr3, [r5, #144]! @ 0x90 │ │ andeq r0, r0, r8, asr #32 │ │ ldr r1, [pc, #16] @ 23c5890 │ │ mov r2, #94 @ 0x5e │ │ ldr r3, [pc, #12] @ 23c5894 │ │ add r1, pc, r1 │ │ @@ -1175748,15 +1175748,15 @@ │ │ ldr r1, [pc, #16] @ 23c58b0 │ │ mov r2, #95 @ 0x5f │ │ ldr r3, [pc, #12] @ 23c58b4 │ │ add r1, pc, r1 │ │ add r3, pc, r3 │ │ b 23bf44c │ │ andeq r0, r0, r4, lsl #16 │ │ - stc2l 6, cr14, [r6, #80]! @ 0x50 │ │ + stc2l 6, cr14, [r6, #260]! @ 0x104 │ │ push {r4, lr} │ │ mov r1, #1 │ │ mov r4, r0 │ │ bl 23bf854 │ │ ldr r2, [r0, #8] │ │ ldr r1, [r0, #24] │ │ sub r2, r2, #4 │ │ @@ -1176357,15 +1176357,15 @@ │ │ mvn r1, #1 │ │ bl 2705370 │ │ mov r0, #1 │ │ pop {r4, r5, r6, r7, r8, pc} │ │ ldc2l 12, cr1, [r1, #988]! @ 0x3dc │ │ eorseq r4, r6, r0, lsl #11 │ │ stc2l 7, cr2, [r8, #656]! @ 0x290 │ │ - stc2l 10, cr6, [r6, #544]! @ 0x220 @ │ │ + stc2l 10, cr6, [r6, #724]! @ 0x2d4 @ │ │ ldc2l 12, cr1, [r1, #960]! @ 0x3c0 │ │ eorseq r4, r6, r4, asr r5 │ │ eorseq r5, r7, r8, lsr #4 │ │ stc2l 11, cr8, [r7, #304]! @ 0x130 @ │ │ eorseq r1, r7, ip, lsr ip │ │ stc2l 4, cr6, [r8, #572]! @ 0x23c │ │ eorseq r1, r7, r0, ror #23 │ │ @@ -1176421,15 +1176421,15 @@ │ │ str r2, [r3, #4] │ │ mov r2, #26 │ │ bl 2704e40 │ │ mov r0, #2 │ │ pop {r4, r5, fp, pc} │ │ movw r1, #1531 @ 0x5fb │ │ bl 235f9d8 │ │ - stc2l 14, cr10, [r5, #164]! @ 0xa4 │ │ + stc2l 14, cr10, [r5, #344]! @ 0x158 │ │ stc2l 6, cr2, [r8, #176]! @ 0xb0 │ │ push {fp, lr} │ │ ldrd r2, [r0, #16] │ │ cmp r2, r3 │ │ bcs 23c6360 │ │ ldr r1, [r2, #4] │ │ cmn r1, #13 │ │ @@ -1176569,15 +1176569,15 @@ │ │ mov r0, r4 │ │ movw r1, #1531 @ 0x5fb │ │ bl 235f9d8 │ │ mov r0, r4 │ │ mov r1, #3 │ │ mov r2, #3 │ │ bl 235fbfc │ │ - stc2l 12, cr6, [r6, #552]! @ 0x228 │ │ + stc2l 12, cr6, [r6, #732]! @ 0x2dc │ │ stc2l 4, cr2, [r8, #64]! @ 0x40 │ │ push {r4, r5, r6, lr} │ │ ldrd r2, [r0, #16] │ │ cmp r2, r3 │ │ bcs 23c65b0 │ │ ldr r1, [r2, #4] │ │ cmn r1, #13 │ │ @@ -1176612,15 +1176612,15 @@ │ │ mov r2, #0 │ │ lsr r1, r0, #5 │ │ mov r0, r5 │ │ pop {r4, r5, r6, lr} │ │ b 270bf50 │ │ movw r1, #1531 @ 0x5fb │ │ bl 235f9d8 │ │ - stc2l 10, cr8, [r6, #120]! @ 0x78 @ │ │ + stc2l 10, cr8, [r6, #300]! @ 0x12c @ │ │ stc2l 2, cr2, [r8, #992]! @ 0x3e0 │ │ push {r5, lr} │ │ ldr r2, [r0, #16] │ │ ldr r5, [r0, #20] │ │ cmp r2, r5 │ │ bcs 23c6660 │ │ ldr r1, [r2, #4] │ │ @@ -1176702,15 +1176702,15 @@ │ │ mvn r2, #0 │ │ add r1, pc, r1 │ │ str r2, [r3, #4] │ │ mov r2, #26 │ │ bl 2704e40 │ │ mov r0, #0 │ │ pop {r4, r5, fp, pc} │ │ - stc2l 9, cr10, [r5, #378]! @ 0x17a @ │ │ + stc2l 9, cr10, [r5, #468]! @ 0x1d4 @ │ │ stc2l 1, cr2, [r8, #800]! @ 0x320 │ │ push {fp, lr} │ │ ldrd r2, [r0, #16] │ │ cmp r2, r3 │ │ bcs 23c67c4 │ │ ldr r1, [r2, #4] │ │ cmn r1, #13 │ │ @@ -1176733,15 +1176733,15 @@ │ │ ldr r1, [pc, #20] @ 23c6810 │ │ mov r2, #13 │ │ add r1, pc, r1 │ │ bl 2704e40 │ │ mov r0, #1 │ │ pop {fp, pc} │ │ stc2l 4, cr8, [r7, #932]! @ 0x3a4 │ │ - stc2l 9, cr6, [r6, #190]! @ 0xbe @ │ │ + stc2l 9, cr6, [r6, #280]! @ 0x118 @ │ │ stc2l 0, cr2, [r8, #912]! @ 0x390 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ sub sp, sp, #20 │ │ ldr fp, [r1] │ │ mov r4, r0 │ │ ldrd r6, [r0, #16] │ │ mov sl, r2 │ │ @@ -1176937,15 +1176937,15 @@ │ │ mov r0, r4 │ │ mov r2, #1184 @ 0x4a0 │ │ bl 235faec │ │ add r1, sl, #1 │ │ mov r0, r4 │ │ movw r2, #1219 @ 0x4c3 │ │ bl 235faec │ │ - stc2l 10, cr4, [r5, #68]! @ 0x44 @ │ │ + stc2l 10, cr4, [r5, #248]! @ 0xf8 @ │ │ stc2l 3, cr14, [r4, #260]! @ 0x104 │ │ stc2l 1, cr14, [r4, #84]! @ 0x54 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ sub sp, sp, #4 │ │ mov sl, r1 │ │ mov r1, #1024 @ 0x400 │ │ mov r4, r2 │ │ @@ -1177147,15 +1177147,15 @@ │ │ movw r1, #1531 @ 0x5fb │ │ bl 235f9d8 │ │ ldr r0, [r4, #20] │ │ ldr r0, [r0, #-16] │ │ add r1, r0, #20 │ │ mov r0, r4 │ │ bl 235f8e0 │ │ - stc2l 2, cr10, [r5, #948]! @ 0x3b4 │ │ + stc2l 3, cr10, [r5, #104]! @ 0x68 │ │ push {r4, r5, r6, r7, r8, lr} │ │ mov r1, #1 │ │ mov r4, r0 │ │ mov r8, #1 │ │ bl 23bf51c │ │ mov r5, r0 │ │ mov r0, r4 │ │ @@ -1177466,15 +1177466,15 @@ │ │ mov r0, r4 │ │ mov r2, #11 │ │ add r1, pc, r1 │ │ bl 2704e40 │ │ mov r0, #1 │ │ pop {r4, pc} │ │ stc2l 3, cr5, [r8, #120]! @ 0x78 │ │ - stc2l 10, cr11, [r5, #264]! @ 0x108 @ │ │ + stc2l 10, cr11, [r5, #444]! @ 0x1bc @ │ │ push {r4, r5, r6, r7, r8, lr} │ │ mov r7, r1 │ │ mov r1, #1 │ │ mov r4, r0 │ │ mov r8, #1 │ │ bl 23bf51c │ │ mov r6, r0 │ │ @@ -1177909,22 +1177909,22 @@ │ │ bl 2365930 │ │ mov fp, r0 │ │ ldrd r0, [r9, #132] @ 0x84 │ │ sub r1, r0, r1 │ │ b 23c77f0 │ │ stc2l 6, cr1, [r7, #4]! │ │ stc2l 5, cr7, [r7, #924]! @ 0x39c │ │ - stc2l 6, cr9, [r6, #496]! @ 0x1f0 │ │ + stc2l 6, cr9, [r6, #676]! @ 0x2a4 │ │ stc2l 6, cr1, [r5, #872]! @ 0x368 │ │ stc2l 11, cr12, [r4, #152]! @ 0x98 @ │ │ stc2l 2, cr6, [r8, #724]! @ 0x2d4 │ │ stc2l 13, cr7, [r8, #872]! @ 0x368 │ │ stc2l 5, cr12, [r7, #620]! @ 0x26c │ │ - stc2l 5, cr9, [r6, #704]! @ 0x2c0 │ │ - stc2l 9, cr3, [r5, #80]! @ 0x50 @ │ │ + stc2l 5, cr9, [r6, #884]! @ 0x374 │ │ + stc2l 9, cr3, [r5, #170]! @ 0xaa @ │ │ stc2l 11, cr15, [r4, #56]! @ 0x38 @ │ │ push {r4, r5, r6, lr} │ │ sub sp, sp, #48 @ 0x30 │ │ mov r1, #1 │ │ mov r4, r0 │ │ bl 2704bd0 │ │ cmp r0, #0 │ │ @@ -1178096,15 +1178096,15 @@ │ │ add r2, pc, r2 │ │ b 23c7d48 │ │ ldr r2, [pc, #44] @ 23c7d74 │ │ add r2, pc, r2 │ │ mov r0, r4 │ │ movw r1, #1621 @ 0x655 │ │ bl 235f99c │ │ - stc2l 4, cr9, [r6, #304]! @ 0x130 │ │ + stc2l 4, cr9, [r6, #484]! @ 0x1e4 │ │ stc2l 4, cr1, [r5, #488]! @ 0x1e8 │ │ stc2l 8, cr12, [r4, #632]! @ 0x278 │ │ stc2l 15, cr5, [r8, #900]! @ 0x384 │ │ stc2l 14, cr5, [r8, #548]! @ 0x224 │ │ stc2l 10, cr7, [r8, #904]! @ 0x388 @ │ │ stc2l 9, cr7, [r8, #396]! @ 0x18c @ │ │ stc2l 2, cr12, [r7, #508]! @ 0x1fc │ │ @@ -1178307,35 +1178307,35 @@ │ │ bl 270bf80 │ │ mov r0, r4 │ │ mvn r1, #1 │ │ bl 2704b70 │ │ mov r0, #1 │ │ add sp, sp, #8 │ │ pop {r4, r5, r6, pc} │ │ - stc2l 0, cr9, [r6, #916]! @ 0x394 │ │ + stc2l 1, cr9, [r6, #72]! @ 0x48 │ │ muleq r0, r8, r2 │ │ - stc2l 7, cr0, [r7, #68]! @ 0x44 │ │ - stc2l 2, cr12, [r6, #948]! @ 0x3b4 │ │ + stc2l 7, cr0, [r7, #248]! @ 0xf8 │ │ + stc2l 3, cr12, [r6, #104]! @ 0x68 │ │ eorseq r2, r6, r8, asr r8 │ │ andeq r0, r0, r8, lsl #18 │ │ andeq r0, r0, ip, lsl sl │ │ andeq r0, r0, r4, lsl #22 │ │ strdeq r0, [r0], -r4 │ │ stc2l 12, cr4, [r7, #352]! @ 0x160 │ │ stc2l 13, cr10, [r4, #320]! @ 0x140 │ │ stc2l 5, cr2, [r7, #796]! @ 0x31c │ │ - stc2l 9, cr14, [r6, #482]! @ 0x1e2 @ │ │ - stc2l 10, cr10, [r6, #628]! @ 0x274 @ │ │ - stc2l 0, cr7, [r6, #240]! @ 0xf0 │ │ - stc2l 1, cr1, [r6, #80]! @ 0x50 │ │ + stc2l 10, cr14, [r6, #120]! @ 0x78 @ │ │ + stc2l 10, cr10, [r6, #808]! @ 0x328 @ │ │ + stc2l 0, cr7, [r6, #420]! @ 0x1a4 │ │ + stc2l 1, cr1, [r6, #260]! @ 0x104 │ │ stc2l 13, cr6, [r7, #8]! │ │ stc2l 14, cr7, [r8, #964]! @ 0x3c4 │ │ stc2l 2, cr6, [r8, #532]! @ 0x214 │ │ - stc2l 9, cr12, [r6, #254]! @ 0xfe @ │ │ - stc2l 1, cr5, [r6, #244]! @ 0xf4 │ │ + stc2l 9, cr12, [r6, #344]! @ 0x158 @ │ │ + stc2l 1, cr5, [r6, #424]! @ 0x1a8 │ │ stc2l 1, cr2, [r8, #804]! @ 0x324 │ │ stc2l 4, cr15, [r4, #480]! @ 0x1e0 │ │ eorseq r2, r6, r4, lsl #13 │ │ push {r4, lr} │ │ ldr r2, [pc, #40] @ 23c812c │ │ mov r1, #1 │ │ add r2, pc, r2 │ │ @@ -1178344,15 +1178344,15 @@ │ │ ldr r0, [r0] │ │ cmp r0, #0 │ │ beq 23c8120 │ │ bl 2702a20 │ │ mov r0, #0 │ │ str r0, [r4] │ │ pop {r4, pc} │ │ - stc2l 14, cr8, [r6, #132]! @ 0x84 │ │ + stc2l 14, cr8, [r6, #312]! @ 0x138 │ │ push {r4, r5, r6, lr} │ │ mov r5, r0 │ │ mov r0, r2 │ │ mov r6, r3 │ │ mov r4, r1 │ │ bl 2704290 │ │ mov r1, r0 │ │ @@ -1178381,15 +1178381,15 @@ │ │ mov r1, r6 │ │ bl 2704bb0 │ │ mov r0, r5 │ │ mvn r1, #1 │ │ mov r2, r4 │ │ pop {r4, r5, r6, lr} │ │ b 2705370 │ │ - stc2l 14, cr2, [r6, #996]! @ 0x3e4 │ │ + stc2l 15, cr2, [r6, #152]! @ 0x98 │ │ stc2l 10, cr12, [r4, #516]! @ 0x204 @ │ │ stc2l 4, cr4, [r8, #876]! @ 0x36c │ │ push {r4, r5, r6, lr} │ │ mov r1, #1 │ │ mov r2, #0 │ │ mov r4, r0 │ │ mov r5, #1 │ │ @@ -1178419,16 +1178419,16 @@ │ │ add r1, pc, r1 │ │ movne r1, r0 │ │ mov r0, r4 │ │ bl 2704bb0 │ │ mov r5, #3 │ │ mov r0, r5 │ │ pop {r4, r5, r6, pc} │ │ - stc2l 7, cr12, [r6, #412]! @ 0x19c │ │ - stc2l 0, cr3, [r5, #532]! @ 0x214 │ │ + stc2l 7, cr12, [r6, #592]! @ 0x250 │ │ + stc2l 0, cr3, [r5, #712]! @ 0x2c8 │ │ push {r4, r5, r6, r7, r8, lr} │ │ sub sp, sp, #8 │ │ mov r1, #1 │ │ mov r2, #0 │ │ mov r4, r0 │ │ mov r8, #1 │ │ bl 270bd80 │ │ @@ -1178464,16 +1178464,16 @@ │ │ mov r0, r4 │ │ mvn r1, #1 │ │ bl 270bd00 │ │ mov r8, #2 │ │ mov r0, r8 │ │ add sp, sp, #8 │ │ pop {r4, r5, r6, r7, r8, pc} │ │ - stc2l 14, cr8, [r5, #720]! @ 0x2d0 │ │ - stc2l 14, cr6, [r5, #660]! @ 0x294 │ │ + stc2l 14, cr8, [r5, #900]! @ 0x384 │ │ + stc2l 14, cr6, [r5, #840]! @ 0x348 │ │ push {r4, lr} │ │ mov r1, #1 │ │ mov r2, #5 │ │ mov r4, r0 │ │ bl 270bd20 │ │ mov r0, r4 │ │ mov r1, #1 │ │ @@ -1178672,23 +1178672,23 @@ │ │ mov r1, r5 │ │ mvn r2, #0 │ │ mov r3, r9 │ │ bl 270bed0 │ │ cmp r0, #0 │ │ movwne r0, #3 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ - stc2l 12, cr6, [r6, #296]! @ 0x128 │ │ + stc2l 12, cr6, [r6, #476]! @ 0x1dc │ │ stc2l 4, cr0, [r8, #864]! @ 0x360 │ │ - stc2l 10, cr8, [r6, #884]! @ 0x374 @ │ │ + stc2l 11, cr8, [r6, #40]! @ 0x28 @ │ │ stc2l 4, cr0, [r8, #336]! @ 0x150 │ │ - stc2l 12, cr8, [r5, #320]! @ 0x140 │ │ - stc2l 9, cr11, [r6, #264]! @ 0x108 @ │ │ - stc2l 14, cr12, [r5, #540]! @ 0x21c │ │ - stc2l 11, cr8, [r5, #560]! @ 0x230 @ │ │ - vcmla.f16 , q11, q0, #270 │ │ + stc2l 12, cr8, [r5, #500]! @ 0x1f4 │ │ + stc2l 9, cr11, [r6, #354]! @ 0x162 @ │ │ + stc2l 14, cr12, [r5, #720]! @ 0x2d0 │ │ + stc2l 11, cr8, [r5, #740]! @ 0x2e4 @ │ │ + vcmla.f16 , q11, , #270 │ │ stc2l 6, cr8, [r7, #312]! @ 0x138 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ sub sp, sp, #20 │ │ sub sp, sp, #1024 @ 0x400 │ │ mov r5, r1 │ │ add r1, sp, #8 │ │ mov r7, r3 │ │ @@ -1178844,17 +1178844,17 @@ │ │ mov r0, r4 │ │ mov r2, r5 │ │ add r1, pc, r1 │ │ bl 270bc50 │ │ mov r0, #1 │ │ pop {r4, r5, r6, pc} │ │ stc2l 12, cr14, [r4, #864]! @ 0x360 │ │ - stc2l 6, cr4, [r5, #440]! @ 0x1b8 │ │ - vcmla.f16 q12, , q8, #270 │ │ - stc2l 6, cr11, [r6, #64]! @ 0x40 │ │ + stc2l 6, cr4, [r5, #620]! @ 0x26c │ │ + stc2l 9, cr8, [r5, #26]! @ │ │ + stc2l 6, cr11, [r6, #244]! @ 0xf4 │ │ stc2l 3, cr8, [r7, #632]! @ 0x278 │ │ stc2l 3, cr8, [r7, #348]! @ 0x15c │ │ push {r4, r5, r6, lr} │ │ sub sp, sp, #8 │ │ mov r1, #1 │ │ mov r2, #0 │ │ mov r4, r0 │ │ @@ -1178912,19 +1178912,19 @@ │ │ add r1, pc, r1 │ │ mov r3, r5 │ │ bl 270bbd0 │ │ mov r0, #1 │ │ add sp, sp, #8 │ │ pop {r4, r5, r6, pc} │ │ stc2l 12, cr1, [r7, #236]! @ 0xec │ │ - stc2l 5, cr8, [r6, #820]! @ 0x334 │ │ + stc2l 5, cr8, [r6, #1000]! @ 0x3e8 │ │ stc2l 12, cr1, [r7, #12]! │ │ - stc2l 7, cr8, [r5, #816]! @ 0x330 │ │ - stc2l 7, cr6, [r5, #852]! @ 0x354 │ │ - stc2l 15, cr13, [r6, #744]! @ 0x2e8 │ │ + stc2l 7, cr8, [r5, #996]! @ 0x3e4 │ │ + vcmla.f16 d22, d5, d2, #270 │ │ + stc2l 15, cr13, [r6, #924]! @ 0x39c │ │ push {r4, r5, r6, lr} │ │ sub sp, sp, #8 │ │ mov r1, #1 │ │ mov r2, #0 │ │ mov r4, r0 │ │ bl 270bd80 │ │ ldr r2, [pc, #224] @ 23c8b20 │ │ @@ -1178981,20 +1178981,20 @@ │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ mov r3, r6 │ │ bl 270bbd0 │ │ mov r0, #1 │ │ add sp, sp, #8 │ │ pop {r4, r5, r6, pc} │ │ - stc2l 5, cr6, [r6, #768]! @ 0x300 │ │ - stc2l 4, cr8, [r6, #756]! @ 0x2f4 │ │ - stc2l 5, cr6, [r6, #544]! @ 0x220 │ │ - stc2l 6, cr8, [r5, #752]! @ 0x2f0 │ │ - stc2l 6, cr6, [r5, #788]! @ 0x314 │ │ - stc2l 14, cr13, [r6, #648]! @ 0x288 │ │ + stc2l 5, cr6, [r6, #948]! @ 0x3b4 │ │ + stc2l 4, cr8, [r6, #936]! @ 0x3a8 │ │ + stc2l 5, cr6, [r6, #724]! @ 0x2d4 │ │ + stc2l 6, cr8, [r5, #932]! @ 0x3a4 │ │ + stc2l 6, cr6, [r5, #968]! @ 0x3c8 │ │ + stc2l 14, cr13, [r6, #828]! @ 0x33c │ │ push {r4, r5, r6, r7, r8, lr} │ │ sub sp, sp, #8 │ │ mov r1, #1 │ │ mov r2, #0 │ │ mov r4, r0 │ │ mov r6, #0 │ │ bl 270bd80 │ │ @@ -1179074,20 +1179074,20 @@ │ │ mov r2, r5 │ │ mov r3, r7 │ │ add r1, pc, r1 │ │ bl 270bc50 │ │ mov r0, r6 │ │ add sp, sp, #8 │ │ pop {r4, r5, r6, r7, r8, pc} │ │ - stc2l 4, cr6, [r6, #448]! @ 0x1c0 │ │ - stc2l 3, cr8, [r6, #436]! @ 0x1b4 │ │ - stc2l 4, cr6, [r6, #224]! @ 0xe0 │ │ - stc2l 5, cr8, [r5, #432]! @ 0x1b0 │ │ - stc2l 5, cr6, [r5, #468]! @ 0x1d4 │ │ - stc2l 13, cr13, [r6, #280]! @ 0x118 │ │ + stc2l 4, cr6, [r6, #628]! @ 0x274 │ │ + stc2l 3, cr8, [r6, #616]! @ 0x268 │ │ + stc2l 4, cr6, [r6, #404]! @ 0x194 │ │ + stc2l 5, cr8, [r5, #612]! @ 0x264 │ │ + stc2l 5, cr6, [r5, #648]! @ 0x288 │ │ + stc2l 13, cr13, [r6, #460]! @ 0x1cc │ │ stc2l 0, cr10, [r4, #312]! @ 0x138 │ │ push {r4, r5, r6, r7, r8, lr} │ │ sub sp, sp, #104 @ 0x68 │ │ mov r1, #1 │ │ mov r2, #0 │ │ mov r4, r0 │ │ bl 270bd80 │ │ @@ -1179353,19 +1179353,19 @@ │ │ bl 2705050 │ │ mov r0, r4 │ │ mov r1, #2 │ │ mov r2, r5 │ │ bl 2705370 │ │ mov r0, #1 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ - stc2l 10, cr11, [r6, #860]! @ 0x35c @ │ │ + stc2l 11, cr11, [r6, #16]! @ │ │ stc2l 12, cr3, [r7, #716]! @ 0x2cc │ │ stc2l 12, cr3, [r7, #512]! @ 0x200 │ │ - stc2l 3, cr2, [r5, #424]! @ 0x1a8 │ │ - stc2l 7, cr7, [r5, #20]! │ │ + stc2l 3, cr2, [r5, #604]! @ 0x25c │ │ + stc2l 7, cr7, [r5, #200]! @ 0xc8 │ │ stc2l 8, cr9, [r7, #1016]! @ 0x3f8 │ │ │ │ 023c9108 : │ │ push {fp, lr} │ │ ldr r1, [pc, #28] @ 23c9130 │ │ ldr r2, [pc, #28] @ 23c9134 │ │ ldr r3, [pc, #28] @ 23c9138 │ │ @@ -1179715,28 +1179715,28 @@ │ │ mov r1, r8 │ │ mov r2, #1184 @ 0x4a0 │ │ bl 235faec │ │ mov r0, r4 │ │ mov r1, r7 │ │ movw r2, #629 @ 0x275 │ │ bl 235faec │ │ - stc2l 7, cr11, [r6, #176]! @ 0xb0 │ │ - stc2l 14, cr3, [r6, #464]! @ 0x1d0 │ │ - stc2l 12, cr5, [r6, #688]! @ 0x2b0 │ │ + stc2l 7, cr11, [r6, #356]! @ 0x164 │ │ + stc2l 14, cr3, [r6, #644]! @ 0x284 │ │ + stc2l 12, cr5, [r6, #868]! @ 0x364 │ │ stc2l 5, cr15, [r7, #332]! @ 0x14c │ │ - stc2l 13, cr15, [r5, #528]! @ 0x210 │ │ + stc2l 13, cr15, [r5, #708]! @ 0x2c4 │ │ stc2l 0, cr0, [r5, #880]! @ 0x370 │ │ - stc2l 13, cr15, [r5, #232]! @ 0xe8 │ │ - stc2l 8, cr9, [r6, #76]! @ 0x4c │ │ - stc2l 9, cr9, [r5, #396]! @ 0x18c @ │ │ + stc2l 13, cr15, [r5, #412]! @ 0x19c │ │ + vcmla.f16 , q3, q0, #270 │ │ + stc2l 9, cr9, [r5, #486]! @ 0x1e6 @ │ │ stc2l 14, cr4, [r8, #464]! @ 0x1d0 │ │ stc2l 0, cr3, [r8, #1012]! @ 0x3f4 │ │ stc2l 10, cr8, [r7, #664]! @ 0x298 @ │ │ stc2l 13, cr12, [r7, #492]! @ 0x1ec │ │ - stc2l 10, cr15, [r5, #996]! @ 0x3e4 @ │ │ + stc2l 11, cr15, [r5, #152]! @ 0x98 @ │ │ stc2l 5, cr11, [r4, #648]! @ 0x288 │ │ push {r4, r5, r6, r7, fp, lr} │ │ sub sp, sp, #104 @ 0x68 │ │ mov r4, r0 │ │ ldrd r0, [r0, #16] │ │ mov r7, #0 │ │ cmp r0, r1 │ │ @@ -1180129,15 +1180129,15 @@ │ │ mov r1, r0 │ │ mov r0, r4 │ │ bl 2704ca0 │ │ mov r0, #3 │ │ add sp, sp, #8 │ │ pop {r4, r5, fp, pc} │ │ andeq r0, r0, r0, asr #5 │ │ - stc2l 7, cr11, [r5, #184]! @ 0xb8 │ │ + stc2l 7, cr11, [r5, #364]! @ 0x16c │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ sub sp, sp, #260 @ 0x104 │ │ mov r4, r0 │ │ ldr r0, [pc, #292] @ 23c9e44 │ │ ldr r7, [pc, #292] @ 23c9e48 │ │ mov r1, #11 │ │ add r0, pc, r0 │ │ @@ -1180212,15 +1180212,15 @@ │ │ mov r0, #0 │ │ add sp, sp, #260 @ 0x104 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ stc2l 1, cr6, [r8, #784]! @ 0x310 │ │ eorseq lr, r6, ip, lsl #1 │ │ eorseq r1, r7, r4, lsr #12 │ │ stc2l 15, cr14, [r6, #144]! @ 0x90 │ │ - stc2l 3, cr7, [r5, #920]! @ 0x398 │ │ + stc2l 4, cr7, [r5, #76]! @ 0x4c │ │ stc2l 1, cr6, [r8, #464]! @ 0x1d0 │ │ stc2l 14, cr10, [r4, #556]! @ 0x22c │ │ push {r4, r5, r6, r7, fp, lr} │ │ mov r4, r0 │ │ ldrd r0, [r0, #16] │ │ mov r7, #0 │ │ cmp r0, r1 │ │ @@ -1180412,19 +1180412,19 @@ │ │ pop {r4, r5, r6, r7, fp, pc} │ │ ldc2l 15, cr13, [r0, #508]! @ 0x1fc │ │ eorseq r0, r6, r8, lsl #15 │ │ ldc2l 15, cr13, [r0, #920]! @ 0x398 │ │ eorseq r0, r6, r4, lsr #15 │ │ ldc2l 15, cr13, [r0, #872]! @ 0x368 │ │ eorseq r0, r6, ip, lsl #15 │ │ - stc2l 2, cr1, [r5, #448]! @ 0x1c0 │ │ + stc2l 2, cr1, [r5, #628]! @ 0x274 │ │ stc2l 13, cr4, [r7, #28]! │ │ ldc2l 15, cr13, [r0, #488]! @ 0x1e8 │ │ eorseq r0, r6, ip, lsl r7 │ │ - stc2l 8, cr10, [r6, #844]! @ 0x34c │ │ + stc2l 9, cr10, [r6] @ │ │ stc2l 11, cr14, [r6, #600]! @ 0x258 @ │ │ push {r4, r5, fp, lr} │ │ sub sp, sp, #16 │ │ mov r4, r0 │ │ ldr r0, [r0, #8] │ │ ldr r5, [r0, #252] @ 0xfc │ │ mov r0, #0 │ │ @@ -1180781,15 +1180781,15 @@ │ │ mov r0, r4 │ │ bl 2364364 │ │ b 23ca650 │ │ mov r0, r4 │ │ mov r1, #1 │ │ mov r2, #10 │ │ bl 235fbfc │ │ - stc2l 4, cr10, [r6, #312]! @ 0x138 │ │ + stc2l 4, cr10, [r6, #492]! @ 0x1ec │ │ stc2l 5, cr2, [r7, #440]! @ 0x1b8 │ │ stc2l 5, cr6, [r7, #592]! @ 0x250 │ │ stc2l 5, cr6, [r7, #896]! @ 0x380 │ │ mov r1, #20 │ │ b 23cac00 │ │ mov r1, #21 │ │ b 23cac00 │ │ @@ -1181042,15 +1181042,15 @@ │ │ mov r1, r0 │ │ mov r0, sl │ │ bl 235f37c │ │ mov r0, sl │ │ mov r1, #2 │ │ movw r2, #551 @ 0x227 │ │ bl 235faec │ │ - stc2l 14, cr11, [r6, #800]! @ 0x320 │ │ + stc2l 14, cr11, [r6, #980]! @ 0x3d4 │ │ push {r4, r5, fp, lr} │ │ sub sp, sp, #88 @ 0x58 │ │ ldrd r4, [r0, #16] │ │ cmp r4, r5 │ │ bcs 23cabe0 │ │ ldr r3, [r4, #4] │ │ cmn r3, #11 │ │ @@ -1181088,15 +1181088,15 @@ │ │ ldr r2, [pc, #20] @ 23cabfc │ │ mov r1, #1 │ │ add r2, pc, r2 │ │ bl 235fb00 │ │ mov r1, #1 │ │ movw r2, #3176 @ 0xc68 │ │ bl 235faec │ │ - stc2l 13, cr11, [r6, #960]! @ 0x3c0 │ │ + stc2l 14, cr11, [r6, #116]! @ 0x74 │ │ push {r4, r5, r6, lr} │ │ mov r4, r0 │ │ ldr r0, [r0, #8] │ │ ldrd r2, [r4, #16] │ │ ldr r0, [r0, #252] @ 0xfc │ │ cmp r2, r3 │ │ str r4, [r0, #12] │ │ @@ -1181536,15 +1181536,15 @@ │ │ mov r0, sl │ │ mov r1, #1 │ │ add r2, pc, r2 │ │ bl 235fb00 │ │ mov r1, r0 │ │ mov r0, sl │ │ bl 235f37c │ │ - stc2l 6, cr11, [r6, #960]! @ 0x3c0 │ │ + stc2l 7, cr11, [r6, #116]! @ 0x74 │ │ push {r4, r5, r6, lr} │ │ mov r4, r0 │ │ ldr r0, [r0, #8] │ │ ldr r1, [r4, #16] │ │ ldr r5, [r0, #252] @ 0xfc │ │ add r2, r1, #8 │ │ mov r0, r4 │ │ @@ -1181801,15 +1181801,15 @@ │ │ mov r0, r4 │ │ mov r1, #1 │ │ add r2, pc, r2 │ │ bl 235fb00 │ │ mov r1, r0 │ │ mov r0, r4 │ │ bl 235f37c │ │ - stc2l 2, cr11, [r6, #816]! @ 0x330 │ │ + stc2l 2, cr11, [r6, #996]! @ 0x3e4 │ │ push {r4, r5, r6, lr} │ │ sub sp, sp, #88 @ 0x58 │ │ ldr r1, [r0, #8] │ │ mov r4, r0 │ │ ldr r3, [r0, #20] │ │ ldr r0, [r0, #16] │ │ ldr r5, [r1, #252] @ 0xfc │ │ @@ -1181905,15 +1181905,15 @@ │ │ mov r1, r0 │ │ mov r0, r4 │ │ bl 235f37c │ │ mov r0, r4 │ │ mov r1, #2 │ │ movw r2, #551 @ 0x227 │ │ bl 235faec │ │ - stc2l 1, cr11, [r6, #240]! @ 0xf0 │ │ + stc2l 1, cr11, [r6, #420]! @ 0x1a4 │ │ push {r4, r5, fp, lr} │ │ sub sp, sp, #88 @ 0x58 │ │ ldr r1, [r0, #8] │ │ mov r4, r0 │ │ ldr r3, [r0, #20] │ │ ldr r0, [r0, #16] │ │ ldr r5, [r1, #252] @ 0xfc │ │ @@ -1181964,15 +1181964,15 @@ │ │ mov r0, r4 │ │ mov r1, #1 │ │ add r2, pc, r2 │ │ bl 235fb00 │ │ mov r1, r0 │ │ mov r0, r4 │ │ bl 235f37c │ │ - stc2l 0, cr11, [r6, #256]! @ 0x100 │ │ + stc2l 0, cr11, [r6, #436]! @ 0x1b4 │ │ push {r4, r5, r6, r7, fp, lr} │ │ sub sp, sp, #88 @ 0x58 │ │ ldr r1, [r0, #8] │ │ mov r4, r0 │ │ ldr r3, [r0, #20] │ │ ldr r0, [r0, #16] │ │ ldr r5, [r1, #252] @ 0xfc │ │ @@ -1182064,15 +1182064,15 @@ │ │ mov r0, r4 │ │ mov r1, #1 │ │ add r2, pc, r2 │ │ bl 235fb00 │ │ mov r1, r0 │ │ mov r0, r4 │ │ bl 235f37c │ │ - stc2l 14, cr10, [r6, #704]! @ 0x2c0 │ │ + stc2l 14, cr10, [r6, #884]! @ 0x374 │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ sub sp, sp, #8 │ │ mov r4, r0 │ │ bl 2702870 │ │ ldrd r8, [r4, #16] │ │ ldr r6, [r0] │ │ cmp r9, r8 │ │ @@ -1182325,15 +1182325,15 @@ │ │ cmn r0, #1 │ │ mvngt r2, #2 │ │ str r2, [r1, #-4] │ │ ldr r0, [r4, #8] │ │ str r2, [r0, #156] @ 0x9c │ │ mov r0, #1 │ │ pop {r4, pc} │ │ - stc2l 4, cr9, [r5, #624]! @ 0x270 │ │ + stc2l 4, cr9, [r5, #804]! @ 0x324 │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ sub sp, sp, #88 @ 0x58 │ │ ldr r1, [r0, #8] │ │ mov r4, r0 │ │ ldr r3, [r0, #20] │ │ ldr r0, [r0, #16] │ │ ldr r6, [r1, #252] @ 0xfc │ │ @@ -1182437,15 +1182437,15 @@ │ │ bl 235fb00 │ │ mov r0, r4 │ │ movw r1, #951 @ 0x3b7 │ │ bl 235f9d8 │ │ mov r1, r0 │ │ mov r0, r4 │ │ bl 235f37c │ │ - vcmla.f16 q13, q11, q12, #270 │ │ + stc2l 9, cr10, [r6, #42]! @ 0x2a @ │ │ push {r4, r5, r6, lr} │ │ mov r4, r0 │ │ ldrd r0, [r0, #16] │ │ cmp r0, r1 │ │ bcs 23cc1ac │ │ ldr r1, [r0, #4] │ │ cmn r1, #11 │ │ @@ -1182756,18 +1182756,18 @@ │ │ movne r1, r9 │ │ bl 235f8e0 │ │ mov r9, #0 │ │ b 23cc5e0 │ │ bl 270ad50 │ │ mov r9, r0 │ │ b 23cc5e0 │ │ - stc2l 12, cr14, [r5, #448]! @ 0x1c0 │ │ + stc2l 12, cr14, [r5, #628]! @ 0x274 │ │ stc2l 2, cr8, [r7, #256]! @ 0x100 │ │ stc2l 6, cr2, [r7, #764]! @ 0x2fc │ │ - stc2l 4, cr8, [r6, #800]! @ 0x320 │ │ + stc2l 4, cr8, [r6, #980]! @ 0x3d4 │ │ stc2l 12, cr1, [r8, #660]! @ 0x294 │ │ ldr r1, [r0] │ │ add r2, r1, #1 │ │ cmp r2, #2 │ │ bcc 23cc648 │ │ push {r4, lr} │ │ mov r4, r0 │ │ @@ -1182842,15 +1182842,15 @@ │ │ mov r0, r4 │ │ bl 23669d4 │ │ add r0, r0, #20 │ │ pop {r4, r5, fp, pc} │ │ mov r0, #0 │ │ pop {r4, r5, fp, pc} │ │ stc2l 15, cr15, [r7, #740]! @ 0x2e4 │ │ - stc2l 5, cr6, [r6, #76]! @ 0x4c │ │ + stc2l 5, cr6, [r6, #256]! @ 0x100 │ │ │ │ 023cc768 : │ │ push {r4, lr} │ │ ldr r2, [pc, #96] @ 23cc7d4 │ │ mov r1, #0 │ │ ldr r3, [pc, #92] @ 23cc7d8 │ │ mov r4, r0 │ │ @@ -1182875,15 +1182875,15 @@ │ │ add r3, pc, r3 │ │ bl 23bef14 │ │ mov r0, #1 │ │ pop {r4, pc} │ │ ldc2l 9, cr11, [r0, #84]! @ 0x54 @ │ │ eorseq lr, r5, r8, lsl #1 │ │ stc2l 2, cr15, [r7, #644]! @ 0x284 │ │ - stc2l 4, cr6, [r6, #340]! @ 0x154 │ │ + stc2l 4, cr6, [r6, #520]! @ 0x208 │ │ ldc2l 9, cr11, [r0, #212]! @ 0xd4 @ │ │ eorseq lr, r5, r4, lsl #1 │ │ push {r4, r5, r7, lr} │ │ ldrd r2, [r0, #16] │ │ cmp r2, r3 │ │ bcs 23cc814 │ │ ldr r1, [r2, #4] │ │ @@ -1183216,15 +1183216,15 @@ │ │ mov r0, r4 │ │ add r2, pc, r2 │ │ bl 235fb00 │ │ add r1, r5, #1 │ │ mov r0, r4 │ │ movw r2, #3762 @ 0xeb2 │ │ bl 235faec │ │ - stc2l 12, cr9, [r6, #780]! @ 0x30c │ │ + stc2l 12, cr9, [r6, #960]! @ 0x3c0 │ │ stc2l 0, cr0, [r7, #688]! @ 0x2b0 │ │ push {r4, lr} │ │ mov r4, r0 │ │ ldrd r0, [r0, #16] │ │ cmp r0, r1 │ │ bcs 23ccd68 │ │ ldr r1, [r0, #4] │ │ @@ -1183398,15 +1183398,15 @@ │ │ add sp, sp, #8 │ │ pop {r4, r5, fp, pc} │ │ ldr r2, [pc, #12] @ 23cd00c │ │ mov r0, r4 │ │ mov r1, #2 │ │ add r2, pc, r2 │ │ bl 235fb00 │ │ - stc2l 9, cr9, [r6, #244]! @ 0xf4 @ │ │ + stc2l 9, cr9, [r6, #334]! @ 0x14e @ │ │ stc2l 12, cr15, [r6, #624]! @ 0x270 │ │ push {r4, r5, r6, r7, fp, lr} │ │ mov r4, r0 │ │ ldrd r0, [r0, #16] │ │ cmp r0, r1 │ │ bcs 23cd040 │ │ ldr r1, [r0, #4] │ │ @@ -1184112,16 +1184112,16 @@ │ │ mov r0, r4 │ │ mov r1, r7 │ │ bl 270c140 │ │ mov r0, r6 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ stc2l 3, cr13, [r6, #636]! @ 0x27c │ │ - stc2l 15, cr8, [r6, #224]! @ 0xe0 │ │ - stc2l 1, cr3, [r6, #592]! @ 0x250 │ │ + stc2l 15, cr8, [r6, #404]! @ 0x194 │ │ + stc2l 1, cr3, [r6, #772]! @ 0x304 │ │ nop {0} │ │ nop {0} │ │ nop {0} │ │ │ │ 023cdb10 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ @@ -1184759,27 +1184759,27 @@ │ │ pop {r4, r5, fp, pc} │ │ stc2l 14, cr7, [r7, #628]! @ 0x274 │ │ │ │ 023ce4ac : │ │ ldr r0, [pc, #4] @ 23ce4b8 │ │ add r0, pc, r0 │ │ bx lr │ │ - stc2l 12, cr2, [r5, #732]! @ 0x2dc │ │ + stc2l 12, cr2, [r5, #912]! @ 0x390 │ │ │ │ 023ce4bc : │ │ ldr r0, [pc, #4] @ 23ce4c8 │ │ add r0, pc, r0 │ │ bx lr │ │ - stc2l 7, cr2, [r6, #688]! @ 0x2b0 │ │ + stc2l 7, cr2, [r6, #868]! @ 0x364 │ │ │ │ 023ce4cc : │ │ ldr r0, [pc, #4] @ 23ce4d8 │ │ add r0, pc, r0 │ │ bx lr │ │ - stc2l 7, cr2, [r6, #624]! @ 0x270 │ │ + stc2l 7, cr2, [r6, #804]! @ 0x324 │ │ │ │ 023ce4dc : │ │ ldr r0, [pc, #4] @ 23ce4e8 │ │ add r0, pc, r0 │ │ bx lr │ │ stc2l 14, cr7, [r7, #436]! @ 0x1b4 │ │ nop {0} │ │ @@ -1184940,15 +1184940,15 @@ │ │ ldr r1, [r2, r1, lsl #2] │ │ str r1, [r0, #348] @ 0x15c │ │ bx lr │ │ ldr r1, [pc, #8] @ 23ce744 │ │ add r1, pc, r1 │ │ str r1, [r0, #348] @ 0x15c │ │ bx lr │ │ - stc2l 7, cr14, [r4, #496]! @ 0x1f0 │ │ + stc2l 7, cr14, [r4, #676]! @ 0x2a4 │ │ eorseq ip, r5, r0, lsr r1 │ │ nop {0} │ │ │ │ 023ce750 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ movw r3, #16831 @ 0x41bf │ │ @@ -1185041,17 +1185041,17 @@ │ │ b 270c290 │ │ andeq r0, r0, r0 │ │ rscsmi r6, r8, r0, lsl #20 │ │ @ instruction: 0xffc00000 │ │ ldrshmi pc, [pc, #255] @ 23ce9cb @ │ │ andeq r0, r0, r0 │ │ mvngt r0, r0 │ │ - stc2l 10, cr2, [r5, #808]! @ 0x328 @ │ │ + stc2l 10, cr2, [r5, #988]! @ 0x3dc @ │ │ stc2l 14, cr13, [r7, #72]! @ 0x48 │ │ - stc2l 1, cr6, [r6, #404]! @ 0x194 │ │ + stc2l 1, cr6, [r6, #584]! @ 0x248 │ │ stc2l 4, cr4, [r4, #592]! @ 0x250 │ │ │ │ 023ce8e0 : │ │ ldrsh r2, [r1, #114] @ 0x72 │ │ ldr r3, [r1, #8] │ │ cmn r2, #1 │ │ ble 23ce920 │ │ @@ -1185224,17 +1185224,17 @@ │ │ ldrh r0, [r4, #74] @ 0x4a │ │ ldr r1, [pc, #24] @ 23ceb9c │ │ orr r0, r0, #32768 @ 0x8000 │ │ strh r0, [r4, #74] @ 0x4a │ │ add r1, pc, r1 │ │ mov r0, r8 │ │ bl 270c120 │ │ - stc2l 6, cr8, [r5, #612]! @ 0x264 │ │ - stc2l 7, cr2, [r5, #108]! @ 0x6c │ │ - stc2l 0, cr4, [r6, #576]! @ 0x240 │ │ + stc2l 6, cr8, [r5, #792]! @ 0x318 │ │ + stc2l 7, cr2, [r5, #288]! @ 0x120 │ │ + stc2l 0, cr4, [r6, #756]! @ 0x2f4 │ │ ldc2l 6, cr9, [r0, #752]! @ 0x2f0 │ │ nop {0} │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d12} │ │ sub sp, sp, #72 @ 0x48 │ │ @@ -1186265,17 +1186265,17 @@ │ │ bl 270c120 │ │ andeq r0, r0, r0 │ │ rscsmi r6, r8, r0, lsl #20 │ │ @ instruction: 0xffc00000 │ │ ldrshmi pc, [pc, #255] @ 23cfccb @ │ │ andeq r0, r0, r0 │ │ mvngt r0, r0 │ │ - stc2l 6, cr7, [r5, #564]! @ 0x234 │ │ - stc2l 10, cr11, [r5, #440]! @ 0x1b8 @ │ │ - stc2l 0, cr3, [r6, #416]! @ 0x1a0 │ │ + stc2l 6, cr7, [r5, #744]! @ 0x2e8 │ │ + stc2l 10, cr11, [r5, #620]! @ 0x26c @ │ │ + stc2l 0, cr3, [r6, #596]! @ 0x254 │ │ ldc2l 10, cr8, [r0, #672]! @ 0x2a0 @ │ │ │ │ 023cfbe0 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ mov r4, r2 │ │ @@ -1186406,15 +1186406,15 @@ │ │ @ instruction: 0xffc00000 │ │ ldrshmi pc, [pc, #255] @ 23cfeeb @ │ │ andeq r0, r0, r0 │ │ mvngt r0, r0 │ │ stc2l 12, cr2, [r7, #540]! @ 0x21c │ │ vcmla.f16 , q2, , #270 │ │ stc2l 10, cr2, [r7, #860]! @ 0x35c @ │ │ - stc2l 3, cr7, [r5, #992]! @ 0x3e0 │ │ + stc2l 4, cr7, [r5, #148]! @ 0x94 │ │ stc2l 0, cr11, [r6, #664]! @ 0x298 │ │ ldc2l 5, cr8, [r0, #304]! @ 0x130 │ │ stc2l 6, cr14, [r7, #92]! @ 0x5c │ │ ldc2l 5, cr8, [r0, #32]! │ │ stc2l 0, cr3, [r4, #16]! │ │ ldc2l 4, cr8, [r0, #144]! @ 0x90 │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ @@ -1186545,17 +1186545,17 @@ │ │ cmp r0, #95 @ 0x5f │ │ strb r3, [r2, #4] │ │ movcc r4, ip │ │ strb r1, [r2, #3] │ │ strb r4, [r2, #1] │ │ add r2, r6, #8 │ │ b 23cff7c │ │ - stc2l 11, cr4, [r6, #624]! @ 0x270 @ │ │ + stc2l 11, cr4, [r6, #804]! @ 0x324 @ │ │ stc2l 3, cr10, [r7, #840]! @ 0x348 │ │ - stc2l 2, cr15, [r4, #88]! @ 0x58 │ │ + stc2l 2, cr15, [r4, #268]! @ 0x10c │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ ldr lr, [r1, #24] │ │ mov ip, r0 │ │ ldr r3, [r0, #24] │ │ mov r0, #0 │ │ sub r4, lr, r2 │ │ @@ -1186645,15 +1186645,15 @@ │ │ str ip, [sp] │ │ bl 23cfe18 │ │ mov ip, #0 │ │ mov r0, ip │ │ mov sp, fp │ │ pop {fp, pc} │ │ stc2l 12, cr14, [r6, #368]! @ 0x170 │ │ - stc2l 15, cr8, [r5, #516]! @ 0x204 │ │ + stc2l 15, cr8, [r5, #696]! @ 0x2b8 │ │ │ │ 023d01b4 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ ldr r6, [fp, #8] │ │ ldr r7, [r6] │ │ @@ -1186848,28 +1186848,28 @@ │ │ b 23d01f0 │ │ ldr r3, [pc, #68] @ 23d0508 │ │ add r3, pc, r3 │ │ str r3, [sp] │ │ movw r3, #28267 @ 0x6e6b │ │ movt r3, #27753 @ 0x6c69 │ │ b 23d0240 │ │ - stc2l 10, cr2, [r6, #268]! @ 0x10c @ │ │ - stc2l 14, cr10, [r5, #596]! @ 0x254 │ │ + stc2l 10, cr2, [r6, #448]! @ 0x1c0 @ │ │ + stc2l 14, cr10, [r5, #776]! @ 0x308 │ │ stc2l 10, cr8, [r6, #692]! @ 0x2b4 @ │ │ stc2l 9, cr4, [r4, #400]! @ 0x190 @ │ │ stc2l 2, cr9, [r4, #68]! @ 0x44 │ │ stc2l 9, cr8, [r6, #290]! @ 0x122 @ │ │ ldc2l 14, cr7, [r0, #992]! @ 0x3e0 │ │ stc2l 3, cr12, [r7, #688]! @ 0x2b0 │ │ - stc2l 11, cr12, [r4, #528]! @ 0x210 @ │ │ - stc2l 13, cr12, [r5, #640]! @ 0x280 │ │ - stc2l 12, cr14, [r5, #468]! @ 0x1d4 │ │ + stc2l 11, cr12, [r4, #708]! @ 0x2c4 @ │ │ + stc2l 13, cr12, [r5, #820]! @ 0x334 │ │ + stc2l 12, cr14, [r5, #648]! @ 0x288 │ │ stc2l 10, cr15, [r7, #752]! @ 0x2f0 @ │ │ - stc2l 11, cr0, [r6, #176]! @ 0xb0 @ │ │ - stc2l 11, cr10, [r5, #832]! @ 0x340 @ │ │ + stc2l 11, cr0, [r6, #356]! @ 0x164 @ │ │ + stc2l 11, cr10, [r5, #1012]! @ 0x3f4 @ │ │ stc2l 13, cr9, [r7, #824]! @ 0x338 │ │ stc2l 7, cr4, [r4, #612]! @ 0x264 │ │ │ │ 023d0514 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #12 │ │ @@ -1187047,15 +1187047,15 @@ │ │ rev r2, r2 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ b 270c2f0 │ │ ldc2l 3, cr8, [r0, #560]! @ 0x230 │ │ stc2l 4, cr12, [r6, #528]! @ 0x210 │ │ stc2l 1, cr2, [r7, #96]! @ 0x60 │ │ - stc2l 9, cr8, [r5, #402]! @ 0x192 @ │ │ + stc2l 9, cr8, [r5, #492]! @ 0x1ec @ │ │ │ │ 023d07e4 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ ldrsh r7, [r1, #74] @ 0x4a │ │ mov r4, #0 │ │ @@ -1187276,15 +1187276,15 @@ │ │ andeq r0, r0, r0 │ │ rscmi r0, r0, r0 │ │ andeq r0, r0, r0 │ │ mvngt r0, r0 │ │ @ instruction: 0xffc00000 │ │ ldrshmi pc, [pc, #255] @ 23d0c63 @ │ │ stc2l 11, cr11, [r7, #504]! @ 0x1f8 @ │ │ - stc2l 6, cr6, [r5, #668]! @ 0x29c │ │ + stc2l 6, cr6, [r5, #848]! @ 0x350 │ │ │ │ 023d0b68 : │ │ cmp r3, #0 │ │ moveq r0, #0 │ │ bxeq lr │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ @@ -1187483,29 +1187483,29 @@ │ │ add r1, pc, r1 │ │ bl 270c140 │ │ ldr r1, [pc, #68] @ 23d0ec8 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ stc2l 15, cr3, [r4, #964]! @ 0x3c4 │ │ - stc2l 2, cr12, [r4, #716]! @ 0x2cc │ │ + stc2l 2, cr12, [r4, #896]! @ 0x380 │ │ stc2l 10, cr11, [r7, #496]! @ 0x1f0 @ │ │ stc2l 15, cr3, [r4, #932]! @ 0x3a4 │ │ stc2l 0, cr14, [r6, #908]! @ 0x38c │ │ - stc2l 6, cr10, [r4, #200]! @ 0xc8 │ │ - stc2l 3, cr14, [r5, #452]! @ 0x1c4 │ │ + stc2l 6, cr10, [r4, #380]! @ 0x17c │ │ + stc2l 3, cr14, [r5, #632]! @ 0x278 │ │ stc2l 0, cr10, [r6, #348]! @ 0x15c │ │ - stc2l 1, cr12, [r4, #924]! @ 0x39c │ │ - stc2l 14, cr1, [r6, #868]! @ 0x364 │ │ - stc2l 14, cr1, [r6, #936]! @ 0x3a8 │ │ - stc2l 3, cr14, [r4, #652]! @ 0x28c │ │ - stc2l 3, cr8, [r5, #32]! │ │ + stc2l 2, cr12, [r4, #80]! @ 0x50 │ │ + stc2l 15, cr1, [r6, #24]! │ │ + stc2l 15, cr1, [r6, #92]! @ 0x5c │ │ + stc2l 3, cr14, [r4, #832]! @ 0x340 │ │ + stc2l 3, cr8, [r5, #212]! @ 0xd4 │ │ stc2l 6, cr6, [r4, #664]! @ 0x298 │ │ stc2l 13, cr11, [r6, #648]! @ 0x288 │ │ - stc2l 14, cr1, [r6, #172]! @ 0xac │ │ + stc2l 14, cr1, [r6, #352]! @ 0x160 │ │ │ │ 023d0ecc : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ ldr ip, [r3] │ │ ldr lr, [r2] │ │ cmp ip, r1 │ │ @@ -1188311,15 +1188311,15 @@ │ │ mov r0, ip │ │ pop {r4, sl, fp, pc} │ │ nop {0} │ │ @ instruction: 0xffc00000 │ │ ldrshmi pc, [pc, #255] @ 23d1c4b @ │ │ andeq r0, r0, r0 │ │ mvngt r0, r0 │ │ - stc2l 4, cr11, [r4, #56]! @ 0x38 │ │ + stc2l 4, cr11, [r4, #236]! @ 0xec │ │ nop {0} │ │ │ │ 023d1b58 : │ │ push {fp, lr} │ │ mov fp, sp │ │ vmov s0, r0 │ │ vldr d17, [pc, #76] @ 23d1bb8 │ │ @@ -1189397,15 +1189397,15 @@ │ │ mvngt r0, r0 │ │ @ instruction: 0xffc00000 │ │ ldrshmi pc, [pc, #255] @ 23d2cfb @ │ │ andcs r0, r0, r0 │ │ andmi sl, r2, #95 @ 0x5f │ │ andeq r0, r0, r0 │ │ rsbmi lr, pc, r0 │ │ - stc2l 0, cr9, [r5, #576]! @ 0x240 │ │ + stc2l 0, cr9, [r5, #756]! @ 0x2f4 │ │ nop {0} │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d11} │ │ sub sp, sp, #16 │ │ mov r4, r2 │ │ @@ -1189942,15 +1189942,15 @@ │ │ bl 270ac10 │ │ ldr r1, [r5] │ │ mov r0, #10 │ │ bl 270ac20 │ │ mov r0, r4 │ │ mov r1, #1 │ │ bl 270c4b0 │ │ - stc2l 12, cr11, [r5, #308]! @ 0x134 │ │ + stc2l 12, cr11, [r5, #488]! @ 0x1e8 │ │ stc2l 8, cr1, [r4, #448]! @ 0x1c0 │ │ eorseq r4, r6, r0, ror r9 │ │ │ │ 023d3478 : │ │ mov ip, r2 │ │ cmp r0, #0 │ │ beq 23d34b0 │ │ @@ -1190502,15 +1190502,15 @@ │ │ cmp r8, #191 @ 0xbf │ │ bcc 23d3c20 │ │ mov r2, #0 │ │ strb r2, [r1, r8] │ │ bl 270c140 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ - stc2l 4, cr7, [r5, #808]! @ 0x328 │ │ + stc2l 4, cr7, [r5, #988]! @ 0x3dc │ │ │ │ 023d3cf8 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #216 @ 0xd8 │ │ mov r2, r1 │ │ ldrb r3, [r0, #314] @ 0x13a │ │ @@ -1192129,15 +1192129,15 @@ │ │ str r0, [sp] │ │ mov r0, r4 │ │ bl 270c3c0 │ │ str r0, [r6] │ │ mov r0, #16384 @ 0x4000 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - stc2l 13, cr9, [r4, #408]! @ 0x198 │ │ + stc2l 13, cr9, [r4, #588]! @ 0x24c │ │ stc2l 15, cr0, [r7, #312]! @ 0x138 │ │ │ │ 023d5478 : │ │ mov ip, r0 │ │ mov r0, #0 │ │ cmp ip, #0 │ │ bxeq lr │ │ @@ -1192466,15 +1192466,15 @@ │ │ bl 26fe3b4 │ │ mov r0, r6 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldr r1, [pc, #8] @ 23d5904 │ │ mov r0, r5 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 13, cr14, [r4, #792]! @ 0x318 │ │ + stc2l 13, cr14, [r4, #972]! @ 0x3cc │ │ │ │ 023d5908 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ cmp r0, #0 │ │ beq 23d593c │ │ mov r4, r0 │ │ @@ -1192492,15 +1192492,15 @@ │ │ bl 2701990 │ │ cmp r0, #0 │ │ popne {r4, sl, fp, pc} │ │ ldr r1, [pc, #8] @ 23d5964 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 13, cr14, [r4, #408]! @ 0x198 │ │ + stc2l 13, cr14, [r4, #588]! @ 0x24c │ │ │ │ 023d5968 : │ │ cmp r1, #0 │ │ moveq r0, #0 │ │ bxeq lr │ │ cmp r0, #0 │ │ ldrne r2, [r0, #800] @ 0x320 │ │ @@ -1192531,15 +1192531,15 @@ │ │ bx lr │ │ bx r2 │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r1, [pc, #4] @ 23d59f0 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 2, cr13, [r5, #868]! @ 0x364 │ │ + stc2l 3, cr13, [r5, #24]! │ │ │ │ 023d59f4 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ cmp r2, #0 │ │ bmi 23d5acc │ │ cmp r3, #1 │ │ @@ -1192644,15 +1192644,15 @@ │ │ ldr r1, [pc, #20] @ 23d5b9c │ │ mov r0, r2 │ │ add r1, pc, r1 │ │ bl 270c140 │ │ mov r0, #0 │ │ pop {r4, sl, fp, lr} │ │ bx lr │ │ - stc2l 11, cr14, [r4, #232]! @ 0xe8 @ │ │ + stc2l 11, cr14, [r4, #412]! @ 0x19c @ │ │ │ │ 023d5ba0 : │ │ cmp r0, #0 │ │ cmpne r1, #0 │ │ bxeq lr │ │ mov r0, r1 │ │ b 2701950 │ │ @@ -1193025,16 +1193025,16 @@ │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ ldr r1, [pc, #16] @ 23d6164 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ stc2l 11, cr2, [r7, #780]! @ 0x30c @ │ │ - stc2l 0, cr7, [r5, #360]! @ 0x168 │ │ - stc2l 0, cr1, [r5, #788]! @ 0x314 │ │ + stc2l 0, cr7, [r5, #540]! @ 0x21c │ │ + stc2l 0, cr1, [r5, #968]! @ 0x3c8 │ │ │ │ 023d6168 : │ │ cmp r0, #0 │ │ bxeq lr │ │ ldrb r2, [r0, #312] @ 0x138 │ │ tst r2, #64 @ 0x40 │ │ bne 23d61a0 │ │ @@ -1193046,27 +1193046,27 @@ │ │ mov r0, r4 │ │ mov r1, r5 │ │ pop {r4, r5, fp, lr} │ │ b 270c750 │ │ ldr r1, [pc, #4] @ 23d61ac │ │ add r1, pc, r1 │ │ b 270c520 │ │ - stc2l 15, cr8, [r4, #964]! @ 0x3c4 │ │ + stc2l 0, cr9, [r4, #120]! @ 0x78 │ │ │ │ 023d61b0 : │ │ cmp r0, #0 │ │ bxeq lr │ │ ldrb r1, [r0, #312] @ 0x138 │ │ tst r1, #64 @ 0x40 │ │ bne 23d61c8 │ │ b 270c740 │ │ ldr r1, [pc, #4] @ 23d61d4 │ │ add r1, pc, r1 │ │ b 270c520 │ │ - stc2l 0, cr1, [r5, #408]! @ 0x198 │ │ + stc2l 0, cr1, [r5, #588]! @ 0x24c │ │ │ │ 023d61d8 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #16 │ │ cmp r0, #0 │ │ beq 23d65f0 │ │ @@ -1193338,17 +1193338,17 @@ │ │ add r1, pc, r1 │ │ bl 270c120 │ │ ldr r1, [pc, #8] @ 23d6628 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ stc2l 9, cr9, [r7, #34]! @ 0x22 @ │ │ - stc2l 7, cr12, [r4, #824]! @ 0x338 │ │ + stc2l 7, cr12, [r4, #1004]! @ 0x3ec │ │ stc2l 6, cr10, [r6, #376]! @ 0x178 │ │ - stc2l 10, cr6, [r4, #188]! @ 0xbc @ │ │ + stc2l 10, cr6, [r4, #368]! @ 0x170 @ │ │ │ │ 023d6638 : │ │ cmp r0, #0 │ │ bxeq lr │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ cmp r1, #0 │ │ @@ -1193452,15 +1193452,15 @@ │ │ bl 270c760 │ │ subs r7, r7, #1 │ │ bne 23d67bc │ │ b 23d67a0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ bx lr │ │ - stc2l 10, cr0, [r5, #696]! @ 0x2b8 @ │ │ + stc2l 10, cr0, [r5, #876]! @ 0x36c @ │ │ stc2l 12, cr15, [r6, #344]! @ 0x158 │ │ │ │ 023d67ec : │ │ cmp r0, #0 │ │ bxeq lr │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -1193781,15 +1193781,15 @@ │ │ mov r3, #0 │ │ b 23d6944 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ bx lr │ │ stc2l 12, cr0, [r4, #948]! @ 0x3b4 │ │ stc2l 11, cr2, [r4, #676]! @ 0x2a4 @ │ │ - stc2l 8, cr4, [r5, #448]! @ 0x1c0 │ │ + stc2l 8, cr4, [r5, #628]! @ 0x274 │ │ │ │ 023d6d04 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ cmp r0, #0 │ │ ldrne r4, [r0] │ │ movne r5, r0 │ │ @@ -1194043,15 +1194043,15 @@ │ │ orr r0, r0, #64 @ 0x40 │ │ str r0, [r5, #244] @ 0xf4 │ │ b 23d6fd4 │ │ ldr r1, [pc, #12] @ 23d7104 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 1, cr8, [r4, #932]! @ 0x3a4 │ │ + stc2l 2, cr8, [r4, #88]! @ 0x58 │ │ stc2l 12, cr11, [r3, #492]! @ 0x1ec │ │ │ │ 023d7108 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ cmp r0, #0 │ │ beq 23d7164 │ │ @@ -1194082,15 +1194082,15 @@ │ │ b 270c4a0 │ │ ldr r1, [pc, #12] @ 23d7190 │ │ add r1, pc, r1 │ │ pop {r4, r5, fp, lr} │ │ b 270c4a0 │ │ andeq r0, r0, r8, asr #3 │ │ stc2l 11, cr13, [r3, #216]! @ 0xd8 @ │ │ - stc2l 0, cr8, [r4, #380]! @ 0x17c │ │ + stc2l 0, cr8, [r4, #560]! @ 0x230 │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #24 │ │ mov r4, r0 │ │ ldr r0, [r0] │ │ cmp r0, #0 │ │ beq 23d71cc │ │ @@ -1194177,15 +1194177,15 @@ │ │ bl 270a2a0 │ │ ldr r1, [pc, #28] @ 23d731c │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c4a0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - stc2l 10, cr9, [r5, #560]! @ 0x230 @ │ │ + stc2l 10, cr9, [r5, #740]! @ 0x2e4 @ │ │ mlaseq r6, ip, r1, r4 │ │ mlaseq r6, r8, r1, r4 │ │ stc2l 10, cr1, [r6, #28]! @ │ │ stc2l 10, cr9, [r6, #816]! @ 0x330 @ │ │ push {r4, r6, r7, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ @@ -1194291,17 +1194291,17 @@ │ │ mov r0, r4 │ │ pop {r4, r5, fp, lr} │ │ b 270c4a0 │ │ mov r0, r5 │ │ bl 27030a0 │ │ mov r0, #0 │ │ pop {r4, r5, fp, pc} │ │ - stc2l 0, cr9, [r5, #1000]! @ 0x3e8 │ │ + stc2l 1, cr9, [r5, #156]! @ 0x9c │ │ @ instruction: 0xfffffea8 │ │ - stc2l 15, cr13, [r4, #264]! @ 0x108 │ │ + stc2l 15, cr13, [r4, #444]! @ 0x1bc │ │ stc2l 13, cr2, [r7, #856]! @ 0x358 │ │ │ │ 023d74e0 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ cmp r0, #0 │ │ beq 23d7578 │ │ @@ -1194339,16 +1194339,16 @@ │ │ str r4, [r3, #288] @ 0x120 │ │ pop {r4, r5, r6, sl, fp, lr} │ │ b 270c550 │ │ mov r0, #0 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ andeq r0, r0, r8, lsr r0 │ │ @ instruction: 0xfffffdc4 │ │ - stc2l 7, cr11, [r5, #804]! @ 0x324 │ │ - stc2l 11, cr7, [r5, #456]! @ 0x1c8 @ │ │ + stc2l 7, cr11, [r5, #984]! @ 0x3d8 │ │ + stc2l 11, cr7, [r5, #636]! @ 0x27c @ │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ cmp r0, #0 │ │ beq 23d75f4 │ │ ldr r3, [r0, #288] @ 0x120 │ │ cmp r3, #0 │ │ ldrne r6, [r3] │ │ @@ -1194370,15 +1194370,15 @@ │ │ sub r1, r7, r5 │ │ add r0, r4, r5 │ │ strd r0, [r6, #12] │ │ pop {r4, r5, r6, r7, fp, pc} │ │ ldr r1, [pc, #4] @ 23d7604 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 9, cr9, [r5, #308]! @ 0x134 @ │ │ + stc2l 9, cr9, [r5, #398]! @ 0x18e @ │ │ stc2l 8, cr3, [r6, #996]! @ 0x3e4 │ │ │ │ 023d760c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #52 @ 0x34 │ │ cmp r0, #0 │ │ @@ -1194498,15 +1194498,15 @@ │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ andeq r0, r0, ip, asr r0 │ │ andeq r1, r0, r0, lsr r5 │ │ strdeq r1, [r0], -r0 │ │ stc2l 6, cr7, [r6, #788]! @ 0x314 │ │ stc2l 1, cr1, [r7, #816]! @ 0x330 │ │ stc2l 1, cr11, [r6, #1020]! @ 0x3fc │ │ - stc2l 11, cr7, [r4, #608]! @ 0x260 @ │ │ + stc2l 11, cr7, [r4, #788]! @ 0x314 @ │ │ stc2l 12, cr6, [r7, #200]! @ 0xc8 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #76 @ 0x4c │ │ ldr r3, [r0] │ │ mov r8, r0 │ │ mov r7, #2 │ │ @@ -1195805,15 +1195805,15 @@ │ │ add r1, pc, r1 │ │ bl 270c120 │ │ ldrhteq r2, [r6], -r8 │ │ mlaseq r6, r8, r8, r2 │ │ eorseq r2, r6, ip, asr #22 │ │ eorseq r2, r6, ip, lsr #22 │ │ stc2l 0, cr8, [r6, #784]! @ 0x310 │ │ - stc2l 3, cr4, [r4, #856]! @ 0x358 │ │ + stc2l 4, cr4, [r4, #12]! │ │ eorseq r2, r6, ip, lsl #25 │ │ eorseq r2, r6, r4, ror #20 │ │ eorseq r2, r6, r4, asr #20 │ │ eorseq r3, r6, r8, lsl #7 │ │ eorseq r3, r6, r0, ror #6 │ │ eorseq r3, r6, ip, lsl #5 │ │ eorseq r3, r6, r8, asr r2 │ │ @@ -1195827,25 +1195827,25 @@ │ │ stc2l 2, cr10, [r3, #288]! @ 0x120 │ │ ldrhteq r3, [r6], -r4 │ │ mlaseq r6, ip, r5, r3 │ │ eorseq r3, r6, r0, lsr #10 │ │ eorseq r3, r6, r8, lsl #10 │ │ mlaseq r6, r8, r4, r3 │ │ eorseq r3, r6, r0, lsl #9 │ │ - stc2l 4, cr8, [r5, #72]! @ 0x48 │ │ + stc2l 4, cr8, [r5, #252]! @ 0xfc │ │ stc2l 2, cr6, [r6, #784]! @ 0x310 │ │ - stc2l 6, cr8, [r4, #984]! @ 0x3d8 │ │ - stc2l 14, cr11, [r5, #248]! @ 0xf8 │ │ - stc2l 1, cr10, [r5, #208]! @ 0xd0 │ │ - stc2l 6, cr14, [r4, #640]! @ 0x280 │ │ - stc2l 1, cr10, [r5, #32]! │ │ + stc2l 7, cr8, [r4, #140]! @ 0x8c │ │ + stc2l 14, cr11, [r5, #428]! @ 0x1ac │ │ + stc2l 1, cr10, [r5, #388]! @ 0x184 │ │ + stc2l 6, cr14, [r4, #820]! @ 0x334 │ │ + stc2l 1, cr10, [r5, #212]! @ 0xd4 │ │ stc2l 12, cr9, [r6, #652]! @ 0x28c │ │ - stc2l 6, cr6, [r4, #240]! @ 0xf0 │ │ - stc2l 6, cr2, [r4, #956]! @ 0x3bc │ │ - stc2l 4, cr6, [r5, #800]! @ 0x320 │ │ + stc2l 6, cr6, [r4, #420]! @ 0x1a4 │ │ + stc2l 7, cr2, [r4, #112]! @ 0x70 │ │ + stc2l 4, cr6, [r5, #980]! @ 0x3d4 │ │ stc2l 9, cr14, [r3, #84]! @ 0x54 @ │ │ stc2l 1, cr0, [r6, #612]! @ 0x264 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ ldr r9, [r0] │ │ mov sl, r0 │ │ @@ -1195999,15 +1195999,15 @@ │ │ mov r0, r8 │ │ mov r1, r6 │ │ bl 270c160 │ │ mov r0, r5 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ stc2l 13, cr15, [pc, #480]! @ 23d9154 │ │ - stc2l 4, cr6, [r4, #20]! │ │ + stc2l 4, cr6, [r4, #200]! @ 0xc8 │ │ stc2l 8, cr11, [r6, #100]! @ 0x64 │ │ andeq r1, r0, ip, lsr #32 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #44 @ 0x2c │ │ ldr r1, [r0] │ │ mov r4, r0 │ │ @@ -1196368,15 +1196368,15 @@ │ │ add r1, pc, r1 │ │ bl 270c120 │ │ ldr r1, [pc, #36] @ 23d954c │ │ mov r0, r8 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ vcmla.f16 , , q12, #270 │ │ - stc2l 14, cr5, [r4, #932]! @ 0x3a4 │ │ + stc2l 15, cr5, [r4, #88]! @ 0x58 │ │ stc2l 9, cr15, [r5, #32]! @ │ │ andeq r0, r0, ip, lsl pc │ │ muleq r0, ip, r1 │ │ stc2l 3, cr15, [r6, #972]! @ 0x3cc │ │ stc2l 15, cr0, [r7, #792]! @ 0x318 │ │ stc2l 3, cr9, [r6, #940]! @ 0x3ac │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ @@ -1196779,16 +1196779,16 @@ │ │ eorseq r1, r6, r8, ror fp │ │ eorseq r1, r6, r8, asr fp │ │ eorseq r1, r6, ip, ror sp │ │ ldrsbteq r1, [r6], -r8 │ │ eorseq r1, r6, r0, asr #23 │ │ mlaseq r6, r8, sl, r1 │ │ eorseq r1, r6, r0, ror sl │ │ - stc2l 5, cr5, [r5, #580]! @ 0x244 │ │ - stc2l 6, cr15, [r4, #100]! @ 0x64 │ │ + stc2l 5, cr5, [r5, #760]! @ 0x2f8 │ │ + stc2l 6, cr15, [r4, #280]! @ 0x118 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #12 │ │ mov r4, r0 │ │ mov r5, #0 │ │ mov r8, #115 @ 0x73 │ │ movw r9, #7093 @ 0x1bb5 │ │ @@ -1197239,15 +1197239,15 @@ │ │ mov r0, #1 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldr r1, [pc, #8] @ 23da2d0 │ │ ldr r0, [sp, #32] │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 10, cr8, [r5, #584]! @ 0x248 @ │ │ + stc2l 10, cr8, [r5, #764]! @ 0x2fc @ │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #44 @ 0x2c │ │ str r0, [sp, #32] │ │ mov r2, #1 │ │ ldr r0, [r0] │ │ str r2, [sp, #4] │ │ @@ -1197443,15 +1197443,15 @@ │ │ eorseq r1, r6, r8, lsr #32 │ │ mlaseq r6, ip, lr, r0 │ │ eorseq r0, r6, r0, lsl #29 │ │ eorseq r0, r6, r0, asr #28 │ │ eorseq r0, r6, r4, lsr #28 │ │ eorseq r0, r6, ip, ror #27 │ │ ldrsbteq r0, [r6], -r0 │ │ - stc2l 7, cr8, [r5, #504]! @ 0x1f8 │ │ + stc2l 7, cr8, [r5, #684]! @ 0x2ac │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #76 @ 0x4c │ │ ldr r4, [r0] │ │ str r0, [fp, #-48] @ 0xffffffd0 │ │ ldr r0, [r4] │ │ ldr r1, [r0] │ │ @@ -1197856,29 +1197856,29 @@ │ │ eorseq r0, r6, r0, asr #21 │ │ ldrhteq r0, [r6], -ip │ │ mlaseq r6, r4, fp, r0 │ │ mlaseq r6, r0, fp, r0 │ │ stc2l 0, cr10, [r3, #944]! @ 0x3b0 │ │ stc2l 10, cr9, [r6, #732]! @ 0x2dc @ │ │ vcmla.f16 q15, , , #270 │ │ - stc2l 13, cr11, [r5, #932]! @ 0x3a4 │ │ - stc2l 1, cr8, [r5, #120]! @ 0x78 │ │ + stc2l 14, cr11, [r5, #88]! @ 0x58 │ │ + stc2l 1, cr8, [r5, #300]! @ 0x12c │ │ stc2l 0, cr2, [r6, #76]! @ 0x4c │ │ │ │ 023dac80 : │ │ ldr r3, [r0, #284] @ 0x11c │ │ cmp r3, #0 │ │ beq 23dac90 │ │ bx r3 │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r1, [pc, #4] @ 23daca4 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 13, cr9, [r5, #516]! @ 0x204 │ │ + stc2l 13, cr9, [r5, #696]! @ 0x2b8 │ │ │ │ 023daca8 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ cmp r0, #0 │ │ beq 23dace8 │ │ ldr r3, [r0, #288] @ 0x120 │ │ @@ -1197890,15 +1197890,15 @@ │ │ cmp r0, r5 │ │ popeq {r4, r5, fp, pc} │ │ ldr r1, [pc, #12] @ 23dacec │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ pop {r4, r5, fp, pc} │ │ - stc2l 4, cr0, [r5, #76]! @ 0x4c │ │ + stc2l 4, cr0, [r5, #256]! @ 0x100 │ │ │ │ 023dacf0 : │ │ cmp r0, #0 │ │ bxeq lr │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ @@ -1197918,15 +1197918,15 @@ │ │ add r1, pc, r1 │ │ bl 270c140 │ │ mov r0, #0 │ │ str r0, [r4, #568] @ 0x238 │ │ pop {r4, sl, fp, lr} │ │ bx lr │ │ eorseq r0, r6, r4, lsl #13 │ │ - stc2l 0, cr8, [r4, #732]! @ 0x2dc │ │ + stc2l 0, cr8, [r4, #912]! @ 0x390 │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ │ │ 023dad60 : │ │ cmp r0, #0 │ │ bxeq lr │ │ sub r1, r1, #2 │ │ @@ -1198089,15 +1198089,15 @@ │ │ b 270c520 │ │ ldr r1, [pc, #24] @ 23daff0 │ │ mov r0, r7 │ │ add r1, pc, r1 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, lr} │ │ b 270c140 │ │ - stc2l 1, cr4, [r5, #968]! @ 0x3c8 │ │ + stc2l 2, cr4, [r5, #124]! @ 0x7c │ │ stc2l 15, cr15, [r5, #20]! │ │ stc2l 13, cr9, [r3, #132]! @ 0x84 │ │ │ │ 023daff4 : │ │ cmp r0, #0 │ │ bxeq lr │ │ ldr r1, [r0, #312] @ 0x138 │ │ @@ -1198267,18 +1198267,18 @@ │ │ ldr r1, [pc, #24] @ 23db294 │ │ mov r0, r6 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ ldr r1, [pc, #4] @ 23db290 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 7, cr9, [r5, #704]! @ 0x2c0 │ │ - stc2l 11, cr7, [r4, #732]! @ 0x2dc @ │ │ + stc2l 7, cr9, [r5, #884]! @ 0x374 │ │ + stc2l 11, cr7, [r4, #912]! @ 0x390 @ │ │ stc2l 13, cr15, [r5, #756]! @ 0x2f4 │ │ - stc2l 7, cr9, [r5, #956]! @ 0x3bc │ │ + stc2l 8, cr9, [r5, #112]! @ 0x70 │ │ │ │ 023db2a0 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ vldr d18, [pc, #144] @ 23db340 │ │ vmov d17, r2, r3 │ │ vldr d16, [pc, #128] @ 23db338 │ │ @@ -1198319,15 +1198319,15 @@ │ │ rscsmi r6, r8, r0, lsl #20 │ │ andeq r0, r0, r0 │ │ rsbmi r0, r0, r0 │ │ @ instruction: 0xffc00000 │ │ ldrshmi pc, [pc, #255] @ 23db453 @ │ │ @ instruction: 0xffc00000 │ │ ldrshgt pc, [pc, #255] @ 23db45b @ │ │ - stc2l 13, cr15, [r4, #824]! @ 0x338 │ │ + stc2l 13, cr15, [r4, #1004]! @ 0x3ec │ │ │ │ 023db35c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #60 @ 0x3c │ │ cmp r0, #0 │ │ str r1, [sp, #24] │ │ @@ -1199053,15 +1199053,15 @@ │ │ rscsmi r6, r8, r0, lsl #20 │ │ andeq r0, r0, r0 │ │ rsbmi r0, r0, r0 │ │ @ instruction: 0xffc00000 │ │ ldrshmi pc, [pc, #255] @ 23dbfb3 @ │ │ @ instruction: 0xffc00000 │ │ ldrshgt pc, [pc, #255] @ 23dbfbb @ │ │ - stc2l 2, cr15, [r4, #456]! @ 0x1c8 │ │ + stc2l 2, cr15, [r4, #636]! @ 0x27c │ │ │ │ 023dbebc : │ │ cmp r0, #0 │ │ bxeq lr │ │ ldr r1, [r0, #312] @ 0x138 │ │ tst r1, #64 @ 0x40 │ │ bne 23dbeec │ │ @@ -1199242,17 +1199242,17 @@ │ │ movteq r0, #23434 @ 0x5b8a │ │ streq r0, [r6] │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldr r1, [pc, #4] @ 23dc170 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ stc2l 13, cr2, [r6, #80]! @ 0x50 │ │ - stc2l 15, cr2, [r5, #948]! @ 0x3b4 │ │ + stc2l 0, cr3, [r5, #104]! @ 0x68 │ │ stc2l 14, cr14, [r5, #340]! @ 0x154 │ │ - stc2l 1, cr1, [r5, #492]! @ 0x1ec │ │ + stc2l 1, cr1, [r5, #672]! @ 0x2a0 │ │ │ │ 023dc180 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r5, r0 │ │ ldr r0, [pc, #76] @ 23dc1e4 │ │ @@ -1200065,16 +1200065,16 @@ │ │ ldr r0, [sl, #316] @ 0x13c │ │ bic r0, r0, #128 @ 0x80 │ │ b 23dcd10 │ │ ldr r1, [pc, #12] @ 23dce3c │ │ mov r0, sl │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 8, cr2, [r5, #880]! @ 0x370 │ │ - stc2l 3, cr2, [r5, #372]! @ 0x174 │ │ + stc2l 9, cr2, [r5, #18]! @ │ │ + stc2l 3, cr2, [r5, #552]! @ 0x228 │ │ │ │ 023dce40 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ ldr r2, [r0, #316] @ 0x13c │ │ tst r2, #4096 @ 0x1000 │ │ beq 23dce94 │ │ @@ -1202605,15 +1202605,15 @@ │ │ cmp sl, #0 │ │ beq 23deb70 │ │ cmp r0, #0 │ │ beq 23dd9e8 │ │ rsb ip, r0, #0 │ │ mov r1, #0 │ │ b 23df614 │ │ - stc2l 9, cr2, [r5, #82]! @ 0x52 @ │ │ + stc2l 9, cr2, [r5, #172]! @ 0xac @ │ │ ldr r2, [sp, #44] @ 0x2c │ │ ldrh r0, [r2, #32] │ │ ldrh r6, [r2, #30] │ │ ldrh r7, [r2, #34] @ 0x22 │ │ rev16 r0, r0 │ │ strh r0, [r3, #3] │ │ lsr r0, r6, #8 │ │ @@ -1203166,15 +1203166,15 @@ │ │ ldr r1, [pc, #16] @ 23dfe98 │ │ mov r0, r8 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ stc2l 14, cr12, [r5, #244]! @ 0xf4 │ │ stc2l 7, cr7, [r3, #264]! @ 0x108 │ │ stc2l 6, cr9, [r3, #624]! @ 0x270 │ │ - stc2l 3, cr13, [r4, #252]! @ 0xfc │ │ + stc2l 3, cr13, [r4, #432]! @ 0x1b0 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ ldrb r3, [r0, #8] │ │ ldr r9, [r0] │ │ cmp r3, #0 │ │ beq 23dff68 │ │ @@ -1203564,15 +1203564,15 @@ │ │ movgt r0, r1 │ │ bxgt lr │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r1, [pc, #4] @ 23e04cc │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 11, cr0, [r5, #152]! @ 0x98 @ │ │ + stc2l 11, cr0, [r5, #332]! @ 0x14c @ │ │ │ │ 023e04d0 : │ │ ldr r0, [r0] │ │ rev r0, r0 │ │ bx lr │ │ │ │ 023e04dc : │ │ @@ -1203634,15 +1203634,15 @@ │ │ add r1, pc, r1 │ │ bl 270c120 │ │ ldr r1, [pc, #12] @ 23e05c4 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ stc2l 3, cr8, [r6, #568]! @ 0x238 │ │ - vcmla.f16 d18, d20, d14, #270 │ │ + stc2l 8, cr2, [r4, #748]! @ 0x2ec │ │ │ │ 023e05c8 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ mov r4, r0 │ │ mov r0, #33 @ 0x21 │ │ @@ -1203751,16 +1203751,16 @@ │ │ mov r0, r8 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ ldr r1, [pc, #12] @ 23e0794 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 10, cr12, [r4, #760]! @ 0x2f8 @ │ │ - vcmla.f16 q8, , q9, #270 │ │ + stc2l 10, cr12, [r4, #940]! @ 0x3ac @ │ │ + vcmla.f16 d16, d21, d15, #270 │ │ stc2l 2, cr2, [r6, #716]! @ 0x2cc │ │ │ │ 023e079c : │ │ mvn r2, #122 @ 0x7a │ │ uxtab r2, r2, r1 │ │ cmn r2, #58 @ 0x3a │ │ mvncs r2, #90 @ 0x5a │ │ @@ -1203849,15 +1203849,15 @@ │ │ cmp r7, r8 │ │ bcs 23e08e4 │ │ ldr r1, [pc, #12] @ 23e0908 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ pop {r4, r5, r6, r7, r8, sl, fp, lr} │ │ b 270c2d0 │ │ - stc2l 9, cr12, [r4, #76]! @ 0x4c @ │ │ + stc2l 9, cr12, [r4, #166]! @ 0xa6 @ │ │ │ │ 023e090c : │ │ cmp r0, #0 │ │ bxeq lr │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ @@ -1203935,16 +1203935,16 @@ │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ tst r0, #512 @ 0x200 │ │ beq 23e0a1c │ │ ldr r1, [pc, #8] @ 23e0a50 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ - stc2l 15, cr5, [r5, #948]! @ 0x3b4 │ │ - stc2l 0, cr6, [r5, #68]! @ 0x44 │ │ + stc2l 0, cr6, [r5, #104]! @ 0x68 │ │ + stc2l 0, cr6, [r5, #248]! @ 0xf8 │ │ │ │ 023e0a58 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r4, r0 │ │ ldr r5, [r0, #312] @ 0x138 │ │ @@ -1204078,15 +1204078,15 @@ │ │ ldr r1, [pc, #16] @ 23e0c70 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ stc2l 15, cr7, [pc, #976]! @ 23e1040 │ │ stc2l 0, cr4, [r3, #872]! @ 0x368 │ │ stc2l 0, cr13, [r6, #120]! @ 0x78 │ │ - stc2l 4, cr0, [r5, #280]! @ 0x118 │ │ + stc2l 4, cr0, [r5, #460]! @ 0x1cc │ │ │ │ 023e0c78 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #780 @ 0x30c │ │ ldr r3, [r0, #308] @ 0x134 │ │ mov r4, r0 │ │ @@ -1204230,18 +1204230,18 @@ │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ stc2l 0, cr4, [r3, #296]! @ 0x128 │ │ stc2l 10, cr11, [r6, #316]! @ 0x13c @ │ │ stc2l 14, cr12, [r6, #456]! @ 0x1c8 │ │ stc2l 4, cr13, [r6, #652]! @ 0x28c │ │ - stc2l 5, cr4, [r4, #688]! @ 0x2b0 │ │ - stc2l 3, cr14, [r4, #140]! @ 0x8c │ │ + stc2l 5, cr4, [r4, #868]! @ 0x364 │ │ + stc2l 3, cr14, [r4, #320]! @ 0x140 │ │ stc2l 5, cr13, [r6, #12]! │ │ - stc2l 5, cr4, [r4, #412]! @ 0x19c │ │ + stc2l 5, cr4, [r4, #592]! @ 0x250 │ │ stc2l 7, cr11, [r6, #920]! @ 0x398 │ │ │ │ 023e0ee0 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [r0, #308] @ 0x134 │ │ @@ -1204325,15 +1204325,15 @@ │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldr r1, [pc, #12] @ 23e1038 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ stc2l 13, cr3, [r3, #696]! @ 0x2b8 │ │ stc2l 12, cr12, [r6, #616]! @ 0x268 │ │ - stc2l 3, cr4, [r4, #908]! @ 0x38c │ │ + stc2l 4, cr4, [r4, #64]! @ 0x40 │ │ │ │ 023e103c : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ ldr r3, [r0, #308] @ 0x134 │ │ tst r3, #1 │ │ @@ -1204467,15 +1204467,15 @@ │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ ldr r1, [pc, #16] @ 23e1268 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ stc2l 12, cr3, [r3, #760]! @ 0x2f8 │ │ stc2l 5, cr11, [r6, #232]! @ 0xe8 │ │ stc2l 10, cr12, [r6, #248]! @ 0xf8 @ │ │ - stc2l 1, cr4, [r4, #732]! @ 0x2dc │ │ + stc2l 1, cr4, [r4, #912]! @ 0x390 │ │ stc2l 11, cr12, [r6, #296]! @ 0x128 @ │ │ │ │ 023e1270 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #64 @ 0x40 │ │ ldr r3, [r0, #308] @ 0x134 │ │ @@ -1204599,15 +1204599,15 @@ │ │ ldr r1, [pc, #20] @ 23e1470 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ stc2l 10, cr3, [r3, #552]! @ 0x228 @ │ │ stc2l 9, cr12, [r6, #236]! @ 0xec @ │ │ stc2l 5, cr1, [r6, #444]! @ 0x1bc │ │ stc2l 2, cr11, [r6, #312]! @ 0x138 │ │ - stc2l 15, cr3, [r4, #716]! @ 0x2cc │ │ + stc2l 15, cr3, [r4, #896]! @ 0x380 │ │ │ │ 023e1474 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [r0, #308] @ 0x134 │ │ @@ -1204678,16 +1204678,16 @@ │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldr r1, [pc, #20] @ 23e15a8 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ vcmla.f16 d19, d19, d2, #270 │ │ stc2l 7, cr12, [r6, #456]! @ 0x1c8 │ │ - stc2l 14, cr3, [r4, #700]! @ 0x2bc │ │ - stc2l 14, cr3, [r4, #476]! @ 0x1dc │ │ + stc2l 14, cr3, [r4, #880]! @ 0x370 │ │ + stc2l 14, cr3, [r4, #656]! @ 0x290 │ │ │ │ 023e15ac : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #260 @ 0x104 │ │ sub sp, sp, #1024 @ 0x400 │ │ ldr r3, [r0, #308] @ 0x134 │ │ @@ -1205002,22 +1205002,22 @@ │ │ add r7, pc, r7 │ │ b 23e16c0 │ │ ldr r1, [pc, #40] @ 23e1ac8 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ stc2l 7, cr3, [r3, #280]! @ 0x118 │ │ stc2l 7, cr13, [r5, #784]! @ 0x310 │ │ - stc2l 13, cr3, [r4, #476]! @ 0x1dc │ │ + stc2l 13, cr3, [r4, #656]! @ 0x290 │ │ stc2l 15, cr10, [r6, #752]! @ 0x2f0 │ │ - stc2l 9, cr9, [r4, #412]! @ 0x19c @ │ │ + stc2l 9, cr9, [r4, #502]! @ 0x1f6 @ │ │ stc2l 9, cr8, [r6, #402]! @ 0x192 @ │ │ - stc2l 1, cr3, [r5, #72]! @ 0x48 │ │ - stc2l 0, cr3, [r5, #920]! @ 0x398 │ │ + stc2l 1, cr3, [r5, #252]! @ 0xfc │ │ + stc2l 1, cr3, [r5, #76]! @ 0x4c │ │ vcmla.f16 d24, d6, d29, #270 │ │ - stc2l 9, cr3, [r4, #222]! @ 0xde @ │ │ + stc2l 9, cr3, [r4, #312]! @ 0x138 @ │ │ stc2l 7, cr13, [r5, #192]! @ 0xc0 │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #64 @ 0x40 │ │ mov r4, r0 │ │ ldr r0, [r0, #320] @ 0x140 │ │ mov r5, r1 │ │ @@ -1205074,16 +1205074,16 @@ │ │ bl 270c270 │ │ b 23e1bc0 │ │ str r5, [r4, #320] @ 0x140 │ │ mov r6, #0 │ │ mov r0, r6 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - stc2l 3, cr1, [r4, #472]! @ 0x1d8 │ │ - stc2l 13, cr2, [r5, #976]! @ 0x3d0 │ │ + stc2l 3, cr1, [r4, #652]! @ 0x28c │ │ + stc2l 14, cr2, [r5, #132]! @ 0x84 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ mov r4, r0 │ │ mov r8, r1 │ │ ldr r0, [r0, #320] @ 0x140 │ │ ldr r1, [r4, #476] @ 0x1dc │ │ @@ -1205172,15 +1205172,15 @@ │ │ add r0, r3, r0 │ │ str r0, [r9] │ │ mov r0, r4 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ b 270c270 │ │ stc2l 15, cr14, [r5, #888]! @ 0x378 │ │ - stc2l 0, cr1, [r5, #532]! @ 0x214 │ │ + stc2l 0, cr1, [r5, #712]! @ 0x2c8 │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ ldr r4, [r0, #868] @ 0x364 │ │ mov r7, r2 │ │ mov r6, r1 │ │ mov r5, r0 │ │ cmp r4, #0 │ │ @@ -1205214,15 +1205214,15 @@ │ │ cmp r7, #0 │ │ add r1, pc, r1 │ │ beq 23e1df8 │ │ bl 270c500 │ │ mov r0, r4 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ bl 270c4f0 │ │ - stc2l 3, cr7, [r4, #928]! @ 0x3a0 │ │ + stc2l 4, cr7, [r4, #84]! @ 0x54 │ │ │ │ 023e1e00 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ mov r4, r0 │ │ ldr r0, [r0, #836] @ 0x344 │ │ @@ -1205405,20 +1205405,20 @@ │ │ ldrb r7, [r3, #3] │ │ add r3, r3, #4 │ │ b 23e2098 │ │ ldr r1, [pc, #28] @ 23e2104 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ - stc2l 0, cr1, [r4, #84]! @ 0x54 │ │ + stc2l 0, cr1, [r4, #264]! @ 0x108 │ │ stc2l 14, cr2, [r3, #40]! @ 0x28 │ │ stc2l 7, cr2, [r6, #72]! @ 0x48 │ │ - stc2l 11, cr2, [r5, #64]! @ 0x40 @ │ │ + stc2l 11, cr2, [r5, #244]! @ 0xf4 @ │ │ stc2l 2, cr8, [r6, #892]! @ 0x37c │ │ - stc2l 3, cr3, [r4, #140]! @ 0x8c │ │ + stc2l 3, cr3, [r4, #320]! @ 0x140 │ │ stc2l 3, cr8, [r6, #68]! @ 0x44 │ │ stc2l 2, cr8, [r6, #556]! @ 0x22c │ │ │ │ 023e2110 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #272 @ 0x110 │ │ @@ -1205560,15 +1205560,15 @@ │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ stc2l 10, cr2, [r3, #792]! @ 0x318 @ │ │ stc2l 4, cr10, [r6, #888]! @ 0x378 │ │ stc2l 10, cr11, [r6, #264]! @ 0x108 @ │ │ stc2l 9, cr11, [r6, #404]! @ 0x194 @ │ │ stc2l 0, cr8, [r6, #492]! @ 0x1ec │ │ - stc2l 0, cr3, [r4, #844]! @ 0x34c │ │ + stc2l 1, cr3, [r4] │ │ │ │ 023e2358 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #16 │ │ ldr r7, [r0, #308] @ 0x134 │ │ tst r7, #1 │ │ @@ -1205724,15 +1205724,15 @@ │ │ bl 270c4f0 │ │ stc2l 9, cr2, [r3, #60]! @ 0x3c @ │ │ stc2l 2, cr10, [r6, #328]! @ 0x148 │ │ vcmla.f16 , q3, q7, #270 │ │ stc2l 14, cr3, [r6, #724]! @ 0x2d4 │ │ stc2l 8, cr14, [r5, #348]! @ 0x15c │ │ vcmla.f16 q15, , q1, #270 │ │ - stc2l 14, cr2, [r4, #316]! @ 0x13c │ │ + stc2l 14, cr2, [r4, #496]! @ 0x1f0 │ │ │ │ 023e25e0 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ mov r4, r0 │ │ ldrb r0, [r0, #308] @ 0x134 │ │ @@ -1205859,16 +1205859,16 @@ │ │ ldr r1, [pc, #24] @ 23e27f4 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ stc2l 7, cr12, [r5, #704]! @ 0x2c0 │ │ stc2l 15, cr9, [r6, #168]! @ 0xa8 │ │ stc2l 10, cr7, [r6, #964]! @ 0x3c4 @ │ │ - stc2l 8, cr14, [r4, #464]! @ 0x1d0 │ │ - stc2l 12, cr2, [r4, #188]! @ 0xbc │ │ + vcmla.f16 d30, d20, d17, #270 │ │ + stc2l 12, cr2, [r4, #368]! @ 0x170 │ │ │ │ 023e27f8 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #520 @ 0x208 │ │ mov r4, r0 │ │ ldr r0, [r0, #308] @ 0x134 │ │ @@ -1205945,15 +1205945,15 @@ │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ ldr r1, [pc, #16] @ 23e2940 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ stc2l 4, cr2, [r3, #376]! @ 0x178 │ │ stc2l 13, cr9, [r6, #632]! @ 0x278 │ │ - stc2l 10, cr2, [r4, #876]! @ 0x36c @ │ │ + stc2l 11, cr2, [r4, #32]! @ │ │ stc2l 3, cr11, [r6, #616]! @ 0x268 │ │ │ │ 023e2948 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #16 │ │ ldr r3, [r0, #308] @ 0x134 │ │ @@ -1206019,15 +1206019,15 @@ │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldr r1, [pc, #16] @ 23e2a60 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ stc2l 3, cr2, [r3, #328]! @ 0x148 │ │ stc2l 12, cr9, [r6, #584]! @ 0x248 │ │ stc2l 2, cr11, [r6, #568]! @ 0x238 │ │ - stc2l 9, cr2, [r4, #382]! @ 0x17e @ │ │ + stc2l 9, cr2, [r4, #472]! @ 0x1d8 @ │ │ │ │ 023e2a64 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #16 │ │ ldr r3, [r0, #308] @ 0x134 │ │ tst r3, #1 │ │ @@ -1206132,15 +1206132,15 @@ │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldr r1, [pc, #16] @ 23e2c1c │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ stc2l 2, cr2, [r3, #216]! @ 0xd8 │ │ stc2l 11, cr9, [r6, #472]! @ 0x1d8 @ │ │ stc2l 1, cr11, [r6, #456]! @ 0x1c8 │ │ - vcmla.f16 d18, d4, d3, #270 │ │ + stc2l 8, cr2, [r4, #192]! @ 0xc0 │ │ │ │ 023e2c20 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #36 @ 0x24 │ │ mov r4, r0 │ │ ldr r0, [r0, #308] @ 0x134 │ │ @@ -1206354,18 +1206354,18 @@ │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ stc2l 0, cr2, [r3, #136]! @ 0x88 │ │ stc2l 9, cr9, [r6, #220]! @ 0xdc @ │ │ stc2l 15, cr10, [r6, #120]! @ 0x78 │ │ stc2l 15, cr15, [r2, #352]! @ 0x160 │ │ - stc2l 3, cr10, [r4, #444]! @ 0x1bc │ │ + stc2l 3, cr10, [r4, #624]! @ 0x270 │ │ stc2l 5, cr7, [r6, #276]! @ 0x114 │ │ stc2l 9, cr15, [r5, #460]! @ 0x1cc @ │ │ - stc2l 4, cr2, [r4, #604]! @ 0x25c │ │ + stc2l 4, cr2, [r4, #784]! @ 0x310 │ │ │ │ 023e2f9c : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #16 │ │ mov r4, r0 │ │ ldr r0, [r0, #308] @ 0x134 │ │ @@ -1206527,19 +1206527,19 @@ │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ stc2l 13, cr1, [r3, #168]! @ 0xa8 │ │ stc2l 5, cr9, [r6, #808]! @ 0x328 │ │ stc2l 12, cr10, [r6, #600]! @ 0x258 │ │ stc2l 13, cr11, [r5, #144]! @ 0x90 │ │ - stc2l 1, cr8, [r3, #960]! @ 0x3c0 │ │ - stc2l 0, cr4, [r4, #616]! @ 0x268 │ │ - stc2l 0, cr4, [r4, #644]! @ 0x284 │ │ + stc2l 2, cr8, [r3, #116]! @ 0x74 │ │ + stc2l 0, cr4, [r4, #796]! @ 0x31c │ │ + stc2l 0, cr4, [r4, #824]! @ 0x338 │ │ stc2l 11, cr1, [r3, #156]! @ 0x9c @ │ │ - stc2l 1, cr2, [r4, #940]! @ 0x3ac │ │ + stc2l 2, cr2, [r4, #96]! @ 0x60 │ │ stc2l 1, cr7, [r6, #388]! @ 0x184 │ │ │ │ 023e3250 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #16 │ │ mov r4, r0 │ │ @@ -1206602,15 +1206602,15 @@ │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldr r1, [pc, #16] @ 23e335c │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ stc2l 3, cr9, [r6, #632]! @ 0x278 │ │ stc2l 9, cr10, [r6, #308]! @ 0x134 @ │ │ - stc2l 0, cr2, [r4, #764]! @ 0x2fc │ │ + stc2l 0, cr2, [r4, #944]! @ 0x3b0 │ │ │ │ 023e3360 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #32 │ │ mov r4, r0 │ │ ldr r0, [r0, #836] @ 0x344 │ │ @@ -1206721,18 +1206721,18 @@ │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, r9, fp, lr} │ │ b 270c530 │ │ ldr r1, [pc, #16] @ 23e3538 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ - stc2l 15, cr7, [r3, #532]! @ 0x214 │ │ + stc2l 15, cr7, [r3, #712]! @ 0x2c8 │ │ vcmla.f16 , , , #270 │ │ - stc2l 14, cr1, [r4, #908]! @ 0x38c │ │ - stc2l 12, cr5, [r4, #816]! @ 0x330 │ │ + stc2l 15, cr1, [r4, #64]! @ 0x40 │ │ + stc2l 12, cr5, [r4, #996]! @ 0x3e4 │ │ stc2l 13, cr6, [r6, #708]! @ 0x2c4 │ │ │ │ 023e3544 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #32 │ │ mov r4, r0 │ │ @@ -1206883,21 +1206883,21 @@ │ │ bl 270c530 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ ldr r1, [pc, #32] @ 23e37c8 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ - stc2l 13, cr7, [r3, #644]! @ 0x284 │ │ + stc2l 13, cr7, [r3, #824]! @ 0x338 │ │ stc2l 0, cr9, [r6, #832]! @ 0x340 │ │ - stc2l 3, cr3, [r5, #412]! @ 0x19c │ │ - stc2l 10, cr5, [r4, #828]! @ 0x33c @ │ │ + stc2l 3, cr3, [r5, #592]! @ 0x250 │ │ + stc2l 10, cr5, [r4, #1008]! @ 0x3f0 @ │ │ stc2l 13, cr5, [r3, #796]! @ 0x31c │ │ stc2l 6, cr11, [r5, #172]! @ 0xac │ │ - stc2l 12, cr1, [r4, #396]! @ 0x18c │ │ + stc2l 12, cr1, [r4, #576]! @ 0x240 │ │ stc2l 12, cr6, [r6, #4]! │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ mov r5, r2 │ │ ldr r2, [r0, #840] @ 0x348 │ │ mov r7, r3 │ │ @@ -1207015,15 +1207015,15 @@ │ │ mov r0, r4 │ │ mvn r1, #3 │ │ bl 270c270 │ │ mvn r0, #3 │ │ str sl, [r4, #320] @ 0x140 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - stc2l 1, cr1, [r5, #72]! @ 0x48 │ │ + stc2l 1, cr1, [r5, #252]! @ 0xfc │ │ │ │ 023e39c4 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #36 @ 0x24 │ │ mov r4, r0 │ │ ldr r0, [r0, #836] @ 0x344 │ │ @@ -1207225,22 +1207225,22 @@ │ │ cmp r2, #0 │ │ bne 23e3c8c │ │ b 23e3c0c │ │ ldr r1, [pc, #32] @ 23e3d18 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ - stc2l 9, cr7, [r3, #66]! @ 0x42 @ │ │ + stc2l 9, cr7, [r3, #156]! @ 0x9c @ │ │ stc2l 12, cr8, [r6, #304]! @ 0x130 │ │ - stc2l 14, cr2, [r5, #892]! @ 0x37c │ │ - stc2l 4, cr9, [r3, #124]! @ 0x7c │ │ - stc2l 13, cr2, [r5, #540]! @ 0x21c │ │ + stc2l 15, cr2, [r5, #48]! @ 0x30 │ │ + stc2l 4, cr9, [r3, #304]! @ 0x130 │ │ + stc2l 13, cr2, [r5, #720]! @ 0x2d0 │ │ stc2l 1, cr11, [r5, #156]! @ 0x9c │ │ - stc2l 7, cr1, [r4, #76]! @ 0x4c │ │ - stc2l 6, cr5, [r4, #576]! @ 0x240 │ │ + stc2l 7, cr1, [r4, #256]! @ 0x100 │ │ + stc2l 6, cr5, [r4, #756]! @ 0x2f4 │ │ stc2l 7, cr6, [r6, #420]! @ 0x1a4 │ │ │ │ 023e3d24 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ ldr r0, [r0, #760] @ 0x2f8 │ │ @@ -1207344,17 +1207344,17 @@ │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ ldr r1, [pc, #20] @ 23e3ee0 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ - stc2l 5, cr13, [r3, #100]! @ 0x64 │ │ - stc2l 4, cr11, [r4, #88]! @ 0x58 │ │ - stc2l 4, cr7, [r3, #980]! @ 0x3d4 │ │ + stc2l 5, cr13, [r3, #280]! @ 0x118 │ │ + stc2l 4, cr11, [r4, #268]! @ 0x10c │ │ + stc2l 5, cr7, [r3, #136]! @ 0x88 │ │ stc2l 13, cr8, [r5, #868]! @ 0x364 │ │ stc2l 6, cr5, [r3, #716]! @ 0x2cc │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r1 │ │ ldr r1, [r0, #852] @ 0x354 │ │ mov r4, r0 │ │ @@ -1208281,19 +1208281,19 @@ │ │ bl 270c120 │ │ ldr r1, [pc, #32] @ 23e4d68 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c4f0 │ │ mov r0, r4 │ │ bl 270c4f0 │ │ - stc2l 2, cr12, [r4, #972]! @ 0x3cc │ │ + stc2l 3, cr12, [r4, #128]! @ 0x80 │ │ stc2l 0, cr12, [r5, #440]! @ 0x1b8 │ │ stc2l 6, cr5, [r6, #248]! @ 0xf8 │ │ - stc2l 0, cr14, [r4, #468]! @ 0x1d4 │ │ - stc2l 4, cr4, [r4, #528]! @ 0x210 │ │ + stc2l 0, cr14, [r4, #648]! @ 0x288 │ │ + stc2l 4, cr4, [r4, #708]! @ 0x2c4 │ │ │ │ 023e4d6c : │ │ ldrb r1, [r0, #312] @ 0x138 │ │ tst r1, #8 │ │ bne 23e4dc0 │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ @@ -1208751,15 +1208751,15 @@ │ │ mov r1, r2 │ │ mov r4, r2 │ │ bl 270c270 │ │ mov r0, r4 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ vcmla.f16 , , q5, #270 │ │ - stc2l 10, cr13, [r4, #340]! @ 0x154 @ │ │ + stc2l 10, cr13, [r4, #520]! @ 0x208 @ │ │ ldrb r3, [r0, #11] │ │ ldr r2, [r0, #4] │ │ add r0, r3, #7 │ │ cmp r2, r0, lsr #3 │ │ bxls lr │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ @@ -1209369,22 +1209369,22 @@ │ │ ldrhne r0, [r4, #114] @ 0x72 │ │ orrne r0, r0, #16 │ │ strhne r0, [r4, #114] @ 0x72 │ │ mov r0, r5 │ │ bl 270c2a0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - stc2l 5, cr7, [r4, #488]! @ 0x1e8 │ │ + stc2l 5, cr7, [r4, #668]! @ 0x29c │ │ stc2l 12, cr2, [r6, #500]! @ 0x1f4 │ │ - stc2l 13, cr0, [r5, #252]! @ 0xfc │ │ - stc2l 5, cr7, [r4, #156]! @ 0x9c │ │ + stc2l 13, cr0, [r5, #432]! @ 0x1b0 │ │ + stc2l 5, cr7, [r4, #336]! @ 0x150 │ │ stc2l 15, cr10, [r5, #1008]! @ 0x3f0 │ │ stc2l 0, cr13, [r2, #628]! @ 0x274 │ │ - stc2l 4, cr3, [r4, #440]! @ 0x1b8 │ │ - stc2l 5, cr11, [r3, #156]! @ 0x9c │ │ + stc2l 4, cr3, [r4, #620]! @ 0x26c │ │ + stc2l 5, cr11, [r3, #336]! @ 0x150 │ │ │ │ 023e5e40 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #52 @ 0x34 │ │ mov r5, r0 │ │ ldr r0, [pc, #388] @ 23e5fdc │ │ @@ -1209482,23 +1209482,23 @@ │ │ ldrhne r0, [r4, #114] @ 0x72 │ │ orrne r0, r0, #16 │ │ strhne r0, [r4, #114] @ 0x72 │ │ mov r0, r5 │ │ bl 270c2a0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - stc2l 11, cr0, [r5, #924]! @ 0x39c @ │ │ - stc2l 3, cr7, [r4, #828]! @ 0x33c │ │ - stc2l 3, cr9, [r4, #456]! @ 0x1c8 │ │ + stc2l 12, cr0, [r5, #80]! @ 0x50 │ │ + stc2l 3, cr7, [r4, #1008]! @ 0x3f0 │ │ + stc2l 3, cr9, [r4, #636]! @ 0x27c │ │ stc2l 14, cr10, [r5, #528]! @ 0x210 │ │ stc2l 15, cr12, [r2, #148]! @ 0x94 │ │ stc2l 14, cr14, [r2, #600]! @ 0x258 │ │ - stc2l 2, cr3, [r4, #856]! @ 0x358 │ │ - stc2l 3, cr11, [r3, #572]! @ 0x23c │ │ - stc2l 0, cr11, [r4, #932]! @ 0x3a4 │ │ + stc2l 3, cr3, [r4, #12]! │ │ + stc2l 3, cr11, [r3, #752]! @ 0x2f0 │ │ + stc2l 1, cr11, [r4, #88]! @ 0x58 │ │ │ │ 023e6000 : │ │ ldr r1, [pc, #4] @ 23e600c │ │ add r1, pc, r1 │ │ b 270c140 │ │ stc2l 9, cr2, [r6, #204]! @ 0xcc @ │ │ │ │ @@ -1209582,15 +1209582,15 @@ │ │ mov r0, r5 │ │ bl 270c280 │ │ mov r0, r5 │ │ mov r1, r4 │ │ sub sp, fp, #8 │ │ pop {r4, r5, fp, lr} │ │ b 270c2a0 │ │ - stc2l 1, cr11, [r3, #828]! @ 0x33c │ │ + stc2l 1, cr11, [r3, #1008]! @ 0x3f0 │ │ │ │ 023e6150 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ cmp r0, #0 │ │ cmpne r1, #0 │ │ bne 23e6168 │ │ @@ -1209633,16 +1209633,16 @@ │ │ str r2, [r1, #244] @ 0xf4 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ ldr r1, [pc, #16] @ 23e6214 │ │ mov r0, r6 │ │ add r1, pc, r1 │ │ pop {r4, r5, r6, r7, fp, lr} │ │ b 270c140 │ │ - stc2l 1, cr11, [r3, #384]! @ 0x180 │ │ - stc2l 0, cr7, [r4, #312]! @ 0x138 │ │ + stc2l 1, cr11, [r3, #564]! @ 0x234 │ │ + stc2l 0, cr7, [r4, #492]! @ 0x1ec │ │ │ │ 023e6218 : │ │ cmp r0, #0 │ │ bxeq lr │ │ push {r4, r6, r7, r8, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #16 │ │ @@ -1209875,20 +1209875,20 @@ │ │ ldr r1, [pc, #40] @ 23e65d4 │ │ add r1, pc, r1 │ │ mov r0, r9 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ b 270c140 │ │ stc2l 11, cr9, [r6, #644]! @ 0x284 @ │ │ - stc2l 14, cr8, [r3, #636]! @ 0x27c │ │ + stc2l 14, cr8, [r3, #816]! @ 0x330 │ │ stc2l 1, cr14, [r5, #524]! @ 0x20c │ │ - stc2l 12, cr8, [r4, #644]! @ 0x284 │ │ + stc2l 12, cr8, [r4, #824]! @ 0x338 │ │ stc2l 14, cr15, [r5, #684]! @ 0x2ac │ │ - stc2l 11, cr4, [r4, #532]! @ 0x214 @ │ │ - stc2l 13, cr10, [r3, #408]! @ 0x198 │ │ + stc2l 11, cr4, [r4, #712]! @ 0x2c8 @ │ │ + stc2l 13, cr10, [r3, #588]! @ 0x24c │ │ │ │ 023e65d8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ cmp r0, #0 │ │ movne r4, r1 │ │ @@ -1209982,16 +1209982,16 @@ │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ b 270c140 │ │ ldr r1, [pc, #16] @ 23e676c │ │ mov r0, r9 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 3, cr0, [r5, #168]! @ 0xa8 │ │ - stc2l 3, cr0, [r5, #40]! @ 0x28 │ │ + stc2l 3, cr0, [r5, #348]! @ 0x15c │ │ + stc2l 3, cr0, [r5, #220]! @ 0xdc │ │ stc2l 2, cr2, [r6, #244]! @ 0xf4 │ │ stc2l 7, cr12, [r2, #792]! @ 0x318 │ │ vcmla.f16 d24, d5, d17, #270 │ │ │ │ 023e6778 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ @@ -1210036,16 +1210036,16 @@ │ │ b 23e6824 │ │ ldr r1, [pc, #20] @ 23e6838 │ │ add r1, pc, r1 │ │ sub sp, fp, #32 │ │ vpop {d8} │ │ pop {r4, r5, r6, r7, r8, sl, fp, lr} │ │ b 270c140 │ │ - stc2l 10, cr0, [r4, #652]! @ 0x28c @ │ │ - stc2l 10, cr8, [r4, #104]! @ 0x68 @ │ │ + stc2l 10, cr0, [r4, #832]! @ 0x340 @ │ │ + stc2l 10, cr8, [r4, #284]! @ 0x11c @ │ │ │ │ 023e683c : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #40 @ 0x28 │ │ cmp r3, #0 │ │ ble 23e68b0 │ │ @@ -1210077,16 +1210077,16 @@ │ │ add r1, pc, r1 │ │ b 23e68c4 │ │ ldr r1, [pc, #16] @ 23e68d4 │ │ add r1, pc, r1 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, r9, fp, lr} │ │ b 270c140 │ │ - stc2l 10, cr0, [r4, #12]! @ │ │ - stc2l 9, cr8, [r4, #244]! @ 0xf4 @ │ │ + stc2l 10, cr0, [r4, #192]! @ 0xc0 @ │ │ + stc2l 9, cr8, [r4, #334]! @ 0x14e @ │ │ │ │ 023e68d8 : │ │ cmp r0, #0 │ │ cmpne r1, #0 │ │ ldrne r0, [sp] │ │ strbne r0, [r1, #200] @ 0xc8 │ │ ldrne r0, [r1, #8] │ │ @@ -1210307,17 +1210307,17 @@ │ │ bl 270c160 │ │ ldr r1, [pc, #24] @ 23e6c40 │ │ add r1, pc, r1 │ │ mov r0, r5 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ b 270c2d0 │ │ - stc2l 6, cr4, [r4, #116]! @ 0x74 │ │ + stc2l 6, cr4, [r4, #296]! @ 0x128 │ │ stc2l 11, cr13, [r5, #4]! @ │ │ - stc2l 6, cr8, [r4, #200]! @ 0xc8 │ │ + stc2l 6, cr8, [r4, #380]! @ 0x17c │ │ │ │ 023e6c44 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ bl 270caa0 │ │ cmp r0, #0 │ │ @@ -1210519,17 +1210519,17 @@ │ │ ldr r0, [sp, #12] │ │ add r1, pc, r1 │ │ mov r2, #1 │ │ bl 270c290 │ │ mov r0, #1 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - stc2l 11, cr13, [r4, #440]! @ 0x1b8 @ │ │ + stc2l 11, cr13, [r4, #620]! @ 0x26c @ │ │ stc2l 9, cr5, [r6, #480]! @ 0x1e0 @ │ │ - stc2l 2, cr4, [r4, #20]! │ │ + stc2l 2, cr4, [r4, #200]! @ 0xc8 │ │ │ │ 023e6f84 : │ │ cmp r0, #0 │ │ beq 23e6f98 │ │ cmp r1, #0 │ │ cmpne r2, #0 │ │ bne 23e6f9c │ │ @@ -1210651,15 +1210651,15 @@ │ │ str r1, [r4, #244] @ 0xf4 │ │ pop {r4, r5, r6, r7, r8, r9, fp, lr} │ │ bx lr │ │ ldrh r1, [r9, #6] │ │ cmp r1, r0 │ │ bhi 23e7118 │ │ b 23e7128 │ │ - stc2l 1, cr8, [r3, #352]! @ 0x160 │ │ + stc2l 1, cr8, [r3, #532]! @ 0x214 │ │ │ │ 023e717c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ cmp r2, #0 │ │ beq 23e71a4 │ │ @@ -1210757,17 +1210757,17 @@ │ │ ldr r1, [pc, #28] @ 23e7320 │ │ add r1, pc, r1 │ │ mov r0, r9 │ │ mov r2, #1 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ b 270c290 │ │ - stc2l 11, cr11, [r3, #692]! @ 0x2b4 @ │ │ + stc2l 11, cr11, [r3, #872]! @ 0x368 @ │ │ stc2l 3, cr2, [r3, #756]! @ 0x2f4 │ │ - stc2l 13, cr9, [r4, #308]! @ 0x134 │ │ + stc2l 13, cr9, [r4, #488]! @ 0x1e8 │ │ │ │ 023e7324 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ cmp r2, #0 │ │ beq 23e734c │ │ @@ -1210866,16 +1210866,16 @@ │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ b 270c290 │ │ ldr r1, [pc, #20] @ 23e74cc │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ stc2l 9, cr1, [r5, #234]! @ 0xea @ │ │ - stc2l 14, cr7, [r3, #136]! @ 0x88 │ │ - stc2l 13, cr5, [r4, #872]! @ 0x368 │ │ + stc2l 14, cr7, [r3, #316]! @ 0x13c │ │ + stc2l 14, cr5, [r4, #28]! │ │ stc2l 14, cr2, [r6, #800]! @ 0x320 │ │ │ │ 023e74d0 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ cmp r0, #0 │ │ cmpne r1, #0 │ │ @@ -1211085,18 +1211085,18 @@ │ │ mov r0, r5 │ │ str r4, [r0, #772] @ 0x304 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ mov r4, #0 │ │ mov r1, #0 │ │ b 23e77dc │ │ - stc2l 4, cr13, [r4, #796]! @ 0x31c │ │ + stc2l 4, cr13, [r4, #976]! @ 0x3d0 │ │ stc2l 5, cr1, [pc, #660]! @ 23e7ab8 │ │ stc2l 0, cr5, [r6, #968]! @ 0x3c8 │ │ - stc2l 7, cr11, [r4, #444]! @ 0x1bc │ │ + stc2l 7, cr11, [r4, #624]! @ 0x270 │ │ │ │ 023e7828 : │ │ cmp r0, #0 │ │ strne r1, [r0, #756] @ 0x2f4 │ │ strne r2, [r0, #760] @ 0x2f8 │ │ bx lr │ │ │ │ @@ -1211161,15 +1211161,15 @@ │ │ bl 270cb00 │ │ str r5, [r4, #384] @ 0x180 │ │ pop {r4, r5, fp, pc} │ │ ldr r1, [pc, #4] @ 23e792c │ │ add r1, pc, r1 │ │ bl 270c120 │ │ stc2l 14, cr12, [r5, #76]! @ 0x4c │ │ - stc2l 9, cr7, [r3, #502]! @ 0x1f6 @ │ │ + stc2l 10, cr7, [r3, #160]! @ 0xa0 @ │ │ stc2l 12, cr15, [r2, #976]! @ 0x3d0 │ │ │ │ 023e7938 : │ │ cmp r0, #0 │ │ cmpne r1, #0 │ │ ldrne r0, [r1, #8] │ │ bicne r0, r0, r2 │ │ @@ -1211297,16 +1211297,16 @@ │ │ mov r1, r4 │ │ add r2, pc, r2 │ │ bl 270c4e0 │ │ mov r8, r5 │ │ mov r0, r8 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ - stc2l 7, cr5, [r4, #888]! @ 0x378 │ │ - stc2l 8, cr9, [r3, #212]! @ 0xd4 │ │ + vcmla.f16 d21, d4, d11, #270 │ │ + vcmla.f16 , , q9, #270 │ │ │ │ 023e7b20 : │ │ cmp r0, #0 │ │ ldrne r1, [r0, #316] @ 0x13c │ │ orrne r1, r1, #1 │ │ strne r1, [r0, #316] @ 0x13c │ │ bx lr │ │ @@ -1211402,15 +1211402,15 @@ │ │ ldr r1, [pc, #20] @ 23e7c84 │ │ add r1, pc, r1 │ │ b 270c520 │ │ ldr r1, [pc, #4] @ 23e7c80 │ │ add r1, pc, r1 │ │ b 270c520 │ │ stc2l 7, cr2, [r6, #204]! @ 0xcc │ │ - stc2l 5, cr3, [r4, #76]! @ 0x4c │ │ + stc2l 5, cr3, [r4, #256]! @ 0x100 │ │ │ │ 023e7c88 : │ │ cmp r0, #0 │ │ bxeq lr │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ ldrb r3, [r0, #309] @ 0x135 │ │ @@ -1211452,15 +1211452,15 @@ │ │ ldr r1, [r0, #316] @ 0x13c │ │ tst r1, #32768 @ 0x8000 │ │ pop {r4, sl, fp, lr} │ │ orrne r1, r1, #16777216 @ 0x1000000 │ │ strne r1, [r0, #316] @ 0x13c │ │ bx lr │ │ stc2l 6, cr2, [r6, #588]! @ 0x24c │ │ - stc2l 4, cr3, [r4, #460]! @ 0x1cc │ │ + stc2l 4, cr3, [r4, #640]! @ 0x280 │ │ │ │ 023e7d48 : │ │ cmp r0, #0 │ │ ldrne r1, [r0, #316] @ 0x13c │ │ orrne r1, r1, #131072 @ 0x20000 │ │ strne r1, [r0, #316] @ 0x13c │ │ bx lr │ │ @@ -1211987,15 +1211987,15 @@ │ │ beq 23e851c │ │ bx r3 │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r1, [pc, #4] @ 23e8530 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 13, cr6, [r3, #888]! @ 0x378 │ │ + stc2l 14, cr6, [r3, #44]! @ 0x2c │ │ │ │ 023e8534 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ cmp r0, #0 │ │ beq 23e8574 │ │ ldr r3, [r0, #288] @ 0x120 │ │ @@ -1212046,15 +1212046,15 @@ │ │ mov r2, #0 │ │ str r2, [r0, #284] @ 0x11c │ │ add r1, pc, r1 │ │ b 270c140 │ │ bx lr │ │ eorseq r2, r5, ip, ror #27 │ │ ldrsbteq r2, [r5], -r4 │ │ - vcmla.f16 d26, d3, d7, #270 │ │ + stc2l 8, cr10, [r3, #208]! @ 0xd0 │ │ │ │ 023e8600 : │ │ cmp r0, #0 │ │ bxeq lr │ │ push {r4, r5, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #16 │ │ @@ -1212150,15 +1212150,15 @@ │ │ ldr r1, [pc, #20] @ 23e8794 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c140 │ │ mov r0, #0 │ │ str r0, [r4, #788] @ 0x314 │ │ b 23e864c │ │ - stc2l 9, cr0, [r4, #344]! @ 0x158 @ │ │ + stc2l 9, cr0, [r4, #434]! @ 0x1b2 @ │ │ stc2l 15, cr14, [r2, #152]! @ 0x98 │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ mov r5, r0 │ │ ldr r0, [r1, #252] @ 0xfc │ │ cmp r0, #0 │ │ beq 23e885c │ │ @@ -1212201,15 +1212201,15 @@ │ │ b 23e87d8 │ │ mov r0, r5 │ │ mov r1, r8 │ │ bl 270c140 │ │ ldr r3, [r6, #12] │ │ b 23e87e4 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - stc2l 11, cr14, [r3, #220]! @ 0xdc @ │ │ + stc2l 11, cr14, [r3, #400]! @ 0x190 @ │ │ │ │ 023e8864 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ cmp r0, #0 │ │ movne r5, r1 │ │ @@ -1212550,16 +1212550,16 @@ │ │ b 270ccc0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldr r1, [pc, #12] @ 23e8dc8 │ │ mov r0, sl │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 6, cr6, [r3, #872]! @ 0x368 │ │ - stc2l 0, cr10, [r3, #888]! @ 0x378 │ │ + stc2l 7, cr6, [r3, #28]! │ │ + stc2l 1, cr10, [r3, #44]! @ 0x2c │ │ │ │ 023e8dcc : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ ldm r1, {ip, lr} │ │ ldr r2, [r1, #8] │ │ ldr r3, [r1, #12] │ │ @@ -1212940,16 +1212940,16 @@ │ │ blx r3 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldr r1, [pc, #8] @ 23e93ac │ │ mov r0, r6 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 14, cr1, [r4, #16]! │ │ - stc2l 0, cr2, [r4, #676]! @ 0x2a4 │ │ + stc2l 14, cr1, [r4, #196]! @ 0xc4 │ │ + stc2l 0, cr2, [r4, #856]! @ 0x358 │ │ │ │ 023e93b4 : │ │ cmp r0, #0 │ │ bxeq lr │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ mov r4, r1 │ │ @@ -1213158,15 +1213158,15 @@ │ │ strb r5, [r4, #526] @ 0x20e │ │ pop {r4, r5, r6, r7, fp, pc} │ │ ldr r1, [pc, #16] @ 23e96f0 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ stc2l 3, cr15, [r5, #988]! @ 0x3dc │ │ - stc2l 7, cr9, [r4, #616]! @ 0x268 │ │ + stc2l 7, cr9, [r4, #796]! @ 0x31c │ │ stc2l 13, cr0, [r6, #12]! │ │ │ │ 023e96f4 : │ │ bx lr │ │ │ │ 023e96f8 : │ │ bx lr │ │ @@ -1213209,15 +1213209,15 @@ │ │ add r1, pc, r1 │ │ mov r0, r4 │ │ bl 270c140 │ │ str r5, [r4, #396] @ 0x18c │ │ pop {r4, r5, fp, lr} │ │ bx lr │ │ stc2l 0, cr3, [r6, #236]! @ 0xec │ │ - vcmla.f16 , , q6, #270 │ │ + stc2l 8, cr3, [r3, #484]! @ 0x1e4 │ │ │ │ 023e978c : │ │ cmp r0, #0 │ │ bxeq lr │ │ cmp r1, #8 │ │ beq 23e97c8 │ │ push {r4, r5, fp, lr} │ │ @@ -1213229,15 +1213229,15 @@ │ │ mov r1, r2 │ │ bl 270c140 │ │ mov r0, r4 │ │ mov r1, r5 │ │ pop {r4, r5, fp, lr} │ │ str r1, [r0, #392] @ 0x188 │ │ bx lr │ │ - stc2l 11, cr7, [r3, #672]! @ 0x2a0 @ │ │ + stc2l 11, cr7, [r3, #852]! @ 0x354 @ │ │ │ │ 023e97d4 : │ │ cmp r0, #0 │ │ strne r1, [r0, #408] @ 0x198 │ │ bx lr │ │ │ │ 023e97e0 : │ │ @@ -1213270,15 +1213270,15 @@ │ │ add r1, pc, r1 │ │ mov r0, r4 │ │ bl 270c140 │ │ str r5, [r4, #416] @ 0x1a0 │ │ pop {r4, r5, fp, lr} │ │ bx lr │ │ stc2l 15, cr2, [r6, #444]! @ 0x1bc │ │ - stc2l 7, cr3, [r3, #512]! @ 0x200 │ │ + stc2l 7, cr3, [r3, #692]! @ 0x2b4 │ │ │ │ 023e9858 : │ │ cmp r0, #0 │ │ bxeq lr │ │ cmp r1, #8 │ │ beq 23e9894 │ │ push {r4, r5, fp, lr} │ │ @@ -1213290,15 +1213290,15 @@ │ │ mov r1, r2 │ │ bl 270c140 │ │ mov r0, r4 │ │ mov r1, r5 │ │ pop {r4, r5, fp, lr} │ │ str r1, [r0, #412] @ 0x19c │ │ bx lr │ │ - stc2l 10, cr7, [r3, #880]! @ 0x370 @ │ │ + stc2l 11, cr7, [r3, #36]! @ 0x24 @ │ │ │ │ 023e98a0 : │ │ cmp r0, #0 │ │ strne r1, [r0, #644] @ 0x284 │ │ bx lr │ │ │ │ 023e98ac : │ │ @@ -1213583,15 +1213583,15 @@ │ │ @ instruction: 0xffffffff │ │ andeq r0, r0, r8 │ │ andeq r0, r0, pc │ │ andeq r0, r0, r8 │ │ andeq r0, r0, r1 │ │ @ instruction: 0xffffffff │ │ andeq r0, r0, r8 │ │ - stc2l 0, cr7, [r4, #544]! @ 0x220 │ │ + stc2l 0, cr7, [r4, #724]! @ 0x2d4 │ │ mlaseq r5, r8, r7, r1 │ │ mlaseq r5, r4, r7, r1 │ │ stc2l 9, cr15, [r2, #16]! @ │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [r0] │ │ @@ -1213660,15 +1213660,15 @@ │ │ mov r0, r5 │ │ bl 270c490 │ │ mov r0, r4 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ andeq r0, r0, r8, lsr r0 │ │ stc2l 0, cr11, [r2, #644]! @ 0x284 │ │ - stc2l 2, cr7, [r4, #752]! @ 0x2f0 │ │ + stc2l 2, cr7, [r4, #932]! @ 0x3a4 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #140 @ 0x8c │ │ sub sp, sp, #1024 @ 0x400 │ │ ldr sl, [r0] │ │ mov r9, r0 │ │ mov r4, #0 │ │ @@ -1214385,17 +1214385,17 @@ │ │ ldr r0, [r0] │ │ add r1, pc, r1 │ │ bl 270c120 │ │ ldr r1, [pc, #84] @ 23ea9dc │ │ mov r0, r7 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 9, cr12, [r3, #354]! @ 0x162 @ │ │ + stc2l 9, cr12, [r3, #444]! @ 0x1bc @ │ │ stc2l 10, cr15, [r5, #624]! @ 0x270 @ │ │ - vcmla.f16 d30, d19, d26, #270 │ │ + stc2l 8, cr14, [r3, #860]! @ 0x35c │ │ ldrhteq r1, [r5], -r0 │ │ eorseq r1, r5, ip, ror r0 │ │ eorseq r1, r5, r8, rrx │ │ eorseq r0, r5, ip, lsl pc │ │ eorseq r0, r5, r0, lsl #30 │ │ eorseq r0, r5, r0, ror pc │ │ eorseq r0, r5, r4, asr #30 │ │ @@ -1214523,17 +1214523,17 @@ │ │ bl 2702870 │ │ ldr r7, [r0] │ │ b 23eab40 │ │ mov r6, #1 │ │ b 23eab78 │ │ stc2l 14, cr15, [r2, #612]! @ 0x264 │ │ @ instruction: 0xfffff388 │ │ - stc2l 5, cr6, [r4, #400]! @ 0x190 │ │ - stc2l 8, cr2, [r4, #576]! @ 0x240 │ │ - stc2l 8, cr12, [r3, #712]! @ 0x2c8 │ │ + stc2l 5, cr6, [r4, #580]! @ 0x244 │ │ + stc2l 8, cr2, [r4, #756]! @ 0x2f4 │ │ + stc2l 8, cr12, [r3, #892]! @ 0x37c │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ ldr r4, [r0, #288] @ 0x120 │ │ ldr r3, [r4, #40] @ 0x28 │ │ adds r5, r3, r2 │ │ bcs 23eac00 │ │ cmp r2, #0 │ │ @@ -1215876,20 +1215876,20 @@ │ │ ldr r1, [pc, #12] @ 23ec07c │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ stc2l 7, cr13, [r2, #880]! @ 0x370 │ │ stc2l 3, cr14, [r5, #696]! @ 0x2b8 │ │ stc2l 11, cr6, [r5, #184]! @ 0xb8 @ │ │ - stc2l 1, cr5, [r4, #1016]! @ 0x3f8 │ │ + stc2l 2, cr5, [r4, #172]! @ 0xac │ │ stc2l 5, cr14, [r5, #984]! @ 0x3d8 │ │ - stc2l 2, cr3, [r3, #944]! @ 0x3b0 │ │ + stc2l 3, cr3, [r3, #100]! @ 0x64 │ │ stc2l 7, cr11, [r2, #480]! @ 0x1e0 │ │ stc2l 13, cr0, [r5, #784]! @ 0x310 │ │ - stc2l 4, cr15, [r2, #84]! @ 0x54 │ │ + stc2l 4, cr15, [r2, #264]! @ 0x108 │ │ │ │ 023ec09c : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #16 │ │ mov r4, r0 │ │ ldrb r0, [r0, #527] @ 0x20f │ │ @@ -1215986,16 +1215986,16 @@ │ │ pop {r4, r5, r6, r7, fp, pc} │ │ ldr r1, [pc, #20] @ 23ec238 │ │ add r1, pc, r1 │ │ mov r0, r4 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, lr} │ │ b 270c140 │ │ - stc2l 13, cr6, [r4, #60]! @ 0x3c │ │ - stc2l 11, cr6, [r4, #876]! @ 0x36c @ │ │ + stc2l 13, cr6, [r4, #240]! @ 0xf0 │ │ + stc2l 12, cr6, [r4, #32]! │ │ stc2l 3, cr10, [r5, #280]! @ 0x118 │ │ │ │ 023ec240 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #12 │ │ mov r4, r0 │ │ @@ -1216237,15 +1216237,15 @@ │ │ eor r0, r0, #31 │ │ strb r0, [r9, #5] │ │ b 23ec4f8 │ │ ldr r1, [pc, #8] @ 23ec618 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 4, cr10, [r4, #420]! @ 0x1a4 │ │ + stc2l 4, cr10, [r4, #600]! @ 0x258 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #84 @ 0x54 │ │ mov r4, r0 │ │ ldr r0, [r0, #320] @ 0x140 │ │ movw r6, #16724 @ 0x4154 │ │ mov r8, r2 │ │ @@ -1216392,18 +1216392,18 @@ │ │ ldreq r0, [r4, #440] @ 0x1b8 │ │ cmpeq r0, r3 │ │ bne 23ec790 │ │ ldr r0, [r4, #444] @ 0x1bc │ │ cmp r0, sl │ │ bne 23ec790 │ │ b 23ec7cc │ │ - stc2l 7, cr6, [r3, #968]! @ 0x3c8 │ │ - stc2l 11, cr10, [r3, #752]! @ 0x2f0 @ │ │ - stc2l 1, cr8, [r4, #432]! @ 0x1b0 │ │ - stc2l 12, cr0, [r4, #120]! @ 0x78 │ │ + stc2l 8, cr6, [r3, #124]! @ 0x7c │ │ + stc2l 11, cr10, [r3, #932]! @ 0x3a4 @ │ │ + stc2l 1, cr8, [r4, #612]! @ 0x264 │ │ + stc2l 12, cr0, [r4, #300]! @ 0x12c │ │ ldr r3, [r0, #464] @ 0x1d0 │ │ mov r1, r0 │ │ lsrs r0, r3, #15 │ │ mvn r0, #0 │ │ bxne lr │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ @@ -1216707,17 +1216707,17 @@ │ │ mov r0, r9 │ │ bl 270c120 │ │ ldr r1, [pc, #24] @ 23ecd5c │ │ mov r0, r9 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ stc2l 1, cr6, [r2, #148]! @ 0x94 │ │ - stc2l 6, cr10, [r3, #224]! @ 0xe0 │ │ + stc2l 6, cr10, [r3, #404]! @ 0x194 │ │ stc2l 1, cr14, [r4, #992]! @ 0x3e0 │ │ - stc2l 7, cr8, [r3, #84]! @ 0x54 │ │ + stc2l 7, cr8, [r3, #264]! @ 0x108 │ │ stc2l 0, cr6, [r2, #972]! @ 0x3cc │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ mov r9, r2 │ │ ldr r2, [r2, #4] │ │ mov sl, r3 │ │ @@ -1217079,15 +1217079,15 @@ │ │ add r3, r3, #1 │ │ movw r1, #18772 @ 0x4954 │ │ add r2, sp, #4 │ │ movt r1, #29506 @ 0x7342 │ │ bl 23ebc5c │ │ sub sp, fp, #8 │ │ pop {r4, sl, fp, pc} │ │ - stc2l 15, cr11, [r3, #228]! @ 0xe4 │ │ + stc2l 15, cr11, [r3, #408]! @ 0x198 │ │ │ │ 023ed314 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #32 │ │ mov r6, r1 │ │ ldr r1, [r1, #24] │ │ @@ -1217196,18 +1217196,18 @@ │ │ movw ip, #20051 @ 0x4e53 │ │ mov r2, r1 │ │ movt ip, #29778 @ 0x7452 │ │ mov r1, ip │ │ mov sp, fp │ │ pop {fp, lr} │ │ b 23ebc5c │ │ - stc2l 15, cr1, [r3, #508]! @ 0x1fc │ │ + stc2l 15, cr1, [r3, #688]! @ 0x2b0 │ │ stc2l 5, cr11, [r5, #140]! @ 0x8c │ │ - stc2l 15, cr3, [r3, #264]! @ 0x108 │ │ - stc2l 9, cr5, [r4, #318]! @ 0x13e @ │ │ + stc2l 15, cr3, [r3, #444]! @ 0x1bc │ │ + stc2l 9, cr5, [r4, #408]! @ 0x198 @ │ │ │ │ 023ed4e4 : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #8 │ │ cmp r2, #3 │ │ bne 23ed52c │ │ @@ -1217276,15 +1217276,15 @@ │ │ add r2, sp, #2 │ │ mov r3, #1 │ │ bl 23ebc5c │ │ mov sp, fp │ │ pop {fp, pc} │ │ stc2l 1, cr10, [r2, #252]! @ 0xfc │ │ stc2l 4, cr11, [r5, #364]! @ 0x16c │ │ - stc2l 10, cr15, [r2, #100]! @ 0x64 @ │ │ + stc2l 10, cr15, [r2, #280]! @ 0x118 @ │ │ │ │ 023ed610 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #16 │ │ mov r5, r2 │ │ mov r6, r1 │ │ @@ -1217521,16 +1217521,16 @@ │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ ldr r1, [pc, #12] @ 23ed9cc │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 9, cr9, [r3, #332]! @ 0x14c @ │ │ - stc2l 9, cr15, [r3, #28]! @ │ │ + stc2l 9, cr9, [r3, #422]! @ 0x1a6 @ │ │ + stc2l 9, cr15, [r3, #118]! @ 0x76 @ │ │ │ │ 023ed9d0 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #1136 @ 0x470 │ │ mov r6, r2 │ │ mov r9, r0 │ │ @@ -1217662,16 +1217662,16 @@ │ │ ldr r1, [r9, #348] @ 0x15c │ │ mov r0, r9 │ │ bl 270c120 │ │ ldr r1, [pc, #16] @ 23edbfc │ │ mov r0, r9 │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 6, cr1, [r4, #776]! @ 0x308 │ │ - stc2l 7, cr1, [r3, #824]! @ 0x338 │ │ + stc2l 6, cr1, [r4, #956]! @ 0x3bc │ │ + stc2l 7, cr1, [r3, #1004]! @ 0x3ec │ │ stc2l 2, cr5, [r2, #300]! @ 0x12c │ │ │ │ 023edc00 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #132 @ 0x84 │ │ sub sp, sp, #1024 @ 0x400 │ │ @@ -1217895,19 +1217895,19 @@ │ │ mov r0, sl │ │ add r1, pc, r1 │ │ bl 270c120 │ │ ldr r1, [pc, #12] @ 23edf94 │ │ mov r0, sl │ │ add r1, pc, r1 │ │ bl 270c120 │ │ - stc2l 10, cr2, [r3, #84]! @ 0x54 @ │ │ + stc2l 10, cr2, [r3, #264]! @ 0x108 @ │ │ stc2l 14, cr4, [r2, #700]! @ 0x2bc │ │ - stc2l 4, cr1, [r3, #416]! @ 0x1a0 │ │ + stc2l 4, cr1, [r3, #596]! @ 0x254 │ │ stc2l 5, cr12, [r5, #12]! │ │ - stc2l 0, cr15, [r2, #708]! @ 0x2c4 │ │ + stc2l 0, cr15, [r2, #888]! @ 0x378 │ │ │ │ 023edfa4 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #16 │ │ mov r5, r3 │ │ mov r6, r2 │ │ @@ -1218155,15 +1218155,15 @@ │ │ mov r0, r8 │ │ movt r1, #29507 @ 0x7343 │ │ mov r2, sl │ │ mov r3, r6 │ │ bl 23ebc5c │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - stc2l 7, cr8, [r4, #448]! @ 0x1c0 │ │ + stc2l 7, cr8, [r4, #628]! @ 0x274 │ │ │ │ 023ee38c : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #16 │ │ mov r6, r3 │ │ mov r5, r2 │ │ @@ -1218193,15 +1218193,15 @@ │ │ mov r3, #9 │ │ strb r6, [sp, #15] │ │ strb r5, [sp, #14] │ │ strb r4, [sp, #10] │ │ bl 23ebc5c │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - stc2l 11, cr4, [r3, #4]! @ │ │ + stc2l 11, cr4, [r3, #184]! @ 0xb8 @ │ │ │ │ 023ee41c : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #8 │ │ ldrb r2, [r1, #2] │ │ sub r3, r2, #13 │ │ @@ -1218234,15 +1218234,15 @@ │ │ mov r3, #7 │ │ strb ip, [sp, #5] │ │ strb r4, [sp, #4] │ │ strb lr, [sp, #7] │ │ bl 23ebc5c │ │ sub sp, fp, #8 │ │ pop {r4, sl, fp, pc} │ │ - stc2l 10, cr4, [r3, #492]! @ 0x1ec @ │ │ + stc2l 10, cr4, [r3, #672]! @ 0x2a0 @ │ │ │ │ 023ee4b8 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ ldrb r0, [r0, #532] @ 0x214 │ │ ldrb r1, [r4, #529] @ 0x211 │ │ @@ -1220798,22 +1220798,22 @@ │ │ ldr r0, [pc, #32] @ 23f0c50 │ │ add r0, pc, r0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, lr} │ │ b 270ce40 │ │ stc2l 2, cr2, [r2, #940]! @ 0x3ac │ │ vcmla.f16 d25, d21, d21, #270 │ │ - stc2l 3, cr2, [r3, #116]! @ 0x74 │ │ + stc2l 3, cr2, [r3, #296]! @ 0x128 │ │ stc2l 4, cr1, [r5, #280]! @ 0x118 │ │ stc2l 14, cr1, [r5, #20]! │ │ stc2l 2, cr2, [r2, #236]! @ 0xec │ │ - stc2l 6, cr10, [r3, #8]! │ │ - stc2l 2, cr2, [r3, #964]! @ 0x3c4 │ │ + stc2l 6, cr10, [r3, #188]! @ 0xbc │ │ + stc2l 3, cr2, [r3, #120]! @ 0x78 │ │ stc2l 4, cr1, [r5, #104]! @ 0x68 │ │ - stc2l 7, cr10, [r2, #360]! @ 0x168 │ │ + stc2l 7, cr10, [r2, #540]! @ 0x21c │ │ stc2l 2, cr2, [r2, #684]! @ 0x2ac │ │ │ │ 023f0c68 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ mov r4, r3 │ │ mov r5, r2 │ │ @@ -1220835,15 +1220835,15 @@ │ │ mov r3, r4 │ │ bl 270cea0 │ │ mov r0, r8 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - stc2l 6, cr12, [r3, #340]! @ 0x154 │ │ + stc2l 6, cr12, [r3, #520]! @ 0x208 │ │ │ │ 023f0cd4 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ bl 270cf40 │ │ cmp r0, #0 │ │ @@ -1220926,25 +1220926,25 @@ │ │ add r0, pc, r0 │ │ bl 270ce70 │ │ ldr r0, [pc, #44] @ 23f0e54 │ │ add r0, pc, r0 │ │ bl 270ce40 │ │ ldr r0, [r6] │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - stc2l 5, cr8, [r3, #216]! @ 0xd8 │ │ + stc2l 5, cr8, [r3, #396]! @ 0x18c │ │ stc2l 15, cr11, [r4, #280]! @ 0x118 │ │ - stc2l 1, cr2, [r3, #180]! @ 0xb4 │ │ - stc2l 6, cr4, [r3, #460]! @ 0x1cc │ │ - stc2l 4, cr8, [r3, #280]! @ 0x118 │ │ + stc2l 1, cr2, [r3, #360]! @ 0x168 │ │ + stc2l 6, cr4, [r3, #640]! @ 0x280 │ │ + stc2l 4, cr8, [r3, #460]! @ 0x1cc │ │ stc2l 0, cr4, [r2, #576]! @ 0x240 │ │ - stc2l 0, cr2, [r3, #980]! @ 0x3d4 │ │ + stc2l 1, cr2, [r3, #136]! @ 0x88 │ │ stc2l 12, cr7, [r5, #204]! @ 0xcc │ │ - stc2l 4, cr8, [r3, #56]! @ 0x38 │ │ + stc2l 4, cr8, [r3, #236]! @ 0xec │ │ stc2l 15, cr15, [r4, #856]! @ 0x358 │ │ - stc2l 1, cr2, [r3, #356]! @ 0x164 │ │ + stc2l 1, cr2, [r3, #536]! @ 0x218 │ │ │ │ 023f0e60 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ cmp r0, #0 │ │ beq 23f0e94 │ │ ldrb r1, [r0] │ │ @@ -1220985,24 +1220985,24 @@ │ │ bl 270ce60 │ │ ldr r0, [pc, #52] @ 23f0f3c │ │ add r0, pc, r0 │ │ bl 270ce70 │ │ mov r0, r4 │ │ pop {r4, sl, fp, lr} │ │ b 270ce40 │ │ - stc2l 0, cr2, [r3, #428]! @ 0x1ac │ │ + stc2l 0, cr2, [r3, #608]! @ 0x260 │ │ stc2l 5, cr9, [r5, #836]! @ 0x344 │ │ - stc2l 0, cr2, [r3, #292]! @ 0x124 │ │ + stc2l 0, cr2, [r3, #472]! @ 0x1d8 │ │ stc2l 3, cr9, [r5, #444]! @ 0x1bc │ │ stc2l 11, cr1, [r5, #196]! @ 0xc4 @ │ │ - stc2l 0, cr2, [r3, #188]! @ 0xbc │ │ - stc2l 3, cr10, [r3, #120]! @ 0x78 │ │ - stc2l 0, cr2, [r3, #52]! @ 0x34 │ │ + stc2l 0, cr2, [r3, #368]! @ 0x170 │ │ + stc2l 3, cr10, [r3, #300]! @ 0x12c │ │ + stc2l 0, cr2, [r3, #232]! @ 0xe8 │ │ stc2l 3, cr9, [r5, #204]! @ 0xcc │ │ - stc2l 4, cr10, [r2, #472]! @ 0x1d8 │ │ + stc2l 4, cr10, [r2, #652]! @ 0x28c │ │ │ │ 023f0f40 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ cmp r0, #0 │ │ beq 23f0f74 │ │ mov r4, r0 │ │ @@ -1221035,18 +1221035,18 @@ │ │ bl 26ffea0 │ │ mov r1, r0 │ │ mov r0, r4 │ │ pop {r4, r5, r6, sl, fp, lr} │ │ b 270ceb0 │ │ stc2l 10, cr1, [r5, #500]! @ 0x1f4 @ │ │ stc2l 4, cr9, [r5, #996]! @ 0x3e4 │ │ - stc2l 4, cr10, [r2, #72]! @ 0x48 │ │ - stc2l 2, cr10, [r3, #600]! @ 0x258 │ │ - stc2l 4, cr0, [r3, #248]! @ 0xf8 │ │ - stc2l 15, cr1, [r3, #372]! @ 0x174 │ │ + stc2l 4, cr10, [r2, #252]! @ 0xfc │ │ + stc2l 2, cr10, [r3, #780]! @ 0x30c │ │ + stc2l 4, cr0, [r3, #428]! @ 0x1ac │ │ + stc2l 15, cr1, [r3, #552]! @ 0x228 │ │ stc2l 2, cr9, [r5, #524]! @ 0x20c │ │ │ │ 023f0fec : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r2 │ │ mov r6, r1 │ │ @@ -1221168,39 +1221168,39 @@ │ │ mov r0, r5 │ │ mov r1, r4 │ │ bl 270d980 │ │ mov r0, r6 │ │ mov r1, r4 │ │ bl 270d990 │ │ b 23f1160 │ │ - stc2l 3, cr6, [r3, #480]! @ 0x1e0 │ │ + stc2l 3, cr6, [r3, #660]! @ 0x294 │ │ stc2l 3, cr9, [r5, #964]! @ 0x3c4 │ │ - stc2l 14, cr1, [r3, #420]! @ 0x1a4 │ │ - stc2l 2, cr10, [r2, #964]! @ 0x3c4 │ │ + stc2l 14, cr1, [r3, #600]! @ 0x258 │ │ + stc2l 3, cr10, [r2, #120]! @ 0x78 │ │ vcmla.f16 d17, d21, d17, #270 │ │ - stc2l 1, cr10, [r3, #360]! @ 0x168 │ │ - stc2l 14, cr1, [r3, #292]! @ 0x124 │ │ - stc2l 2, cr10, [r2, #836]! @ 0x344 │ │ - stc2l 2, cr10, [r2, #712]! @ 0x2c8 │ │ - stc2l 9, cr15, [r3, #422]! @ 0x1a6 @ │ │ + stc2l 1, cr10, [r3, #540]! @ 0x21c │ │ + stc2l 14, cr1, [r3, #472]! @ 0x1d8 │ │ + stc2l 2, cr10, [r2, #1016]! @ 0x3f8 │ │ + stc2l 2, cr10, [r2, #892]! @ 0x37c │ │ + stc2l 10, cr15, [r3] @ │ │ stc2l 3, cr9, [r5, #260]! @ 0x104 │ │ - stc2l 13, cr1, [r3, #740]! @ 0x2e4 │ │ - stc2l 12, cr1, [r4, #1000]! @ 0x3e8 │ │ - stc2l 0, cr10, [r3, #568]! @ 0x238 │ │ - stc2l 13, cr1, [r3, #500]! @ 0x1f4 │ │ - stc2l 12, cr1, [r4, #760]! @ 0x2f8 │ │ + stc2l 13, cr1, [r3, #920]! @ 0x398 │ │ + stc2l 13, cr1, [r4, #156]! @ 0x9c │ │ + stc2l 0, cr10, [r3, #748]! @ 0x2ec │ │ + stc2l 13, cr1, [r3, #680]! @ 0x2a8 │ │ + stc2l 12, cr1, [r4, #940]! @ 0x3ac │ │ stc2l 7, cr11, [r5, #100]! @ 0x64 │ │ - stc2l 15, cr11, [r2, #312]! @ 0x138 │ │ - stc2l 13, cr1, [r3, #980]! @ 0x3d4 │ │ - stc2l 13, cr1, [r4, #216]! @ 0xd8 │ │ + stc2l 15, cr11, [r2, #492]! @ 0x1ec │ │ + stc2l 14, cr1, [r3, #136]! @ 0x88 │ │ + stc2l 13, cr1, [r4, #396]! @ 0x18c │ │ stc2l 3, cr5, [r5, #424]! @ 0x1a8 │ │ stc2l 11, cr11, [r4, #616]! @ 0x268 @ │ │ - stc2l 13, cr1, [r3, #372]! @ 0x174 │ │ - stc2l 2, cr14, [r2, #104]! @ 0x68 │ │ - stc2l 2, cr6, [r3, #144]! @ 0x90 │ │ + stc2l 13, cr1, [r3, #552]! @ 0x228 │ │ + stc2l 2, cr14, [r2, #284]! @ 0x11c │ │ + stc2l 2, cr6, [r3, #324]! @ 0x144 │ │ │ │ 023f1248 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ cmp r0, #0 │ │ beq 23f12c0 │ │ mov r4, r1 │ │ @@ -1221300,21 +1221300,21 @@ │ │ mov r0, r2 │ │ bl 270d9a0 │ │ cmp r0, #0 │ │ movwne r0, #1 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ stc2l 12, cr13, [r4, #308]! @ 0x134 │ │ stc2l 1, cr9, [r5, #660]! @ 0x294 │ │ - stc2l 12, cr1, [r3, #116]! @ 0x74 │ │ + stc2l 12, cr1, [r3, #296]! @ 0x128 │ │ stc2l 15, cr7, [r2, #912]! @ 0x390 │ │ stc2l 6, cr1, [r5, #852]! @ 0x354 │ │ stc2l 12, cr13, [r4, #116]! @ 0x74 │ │ stc2l 1, cr9, [r5, #468]! @ 0x1d4 │ │ - stc2l 11, cr1, [r3, #948]! @ 0x3b4 @ │ │ - stc2l 11, cr1, [r3, #972]! @ 0x3cc @ │ │ + stc2l 12, cr1, [r3, #104]! @ 0x68 │ │ + stc2l 12, cr1, [r3, #128]! @ 0x80 │ │ │ │ 023f1408 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #112 @ 0x70 │ │ mov r7, r0 │ │ ldr r0, [pc, #580] @ 23f1664 │ │ @@ -1221460,29 +1221460,29 @@ │ │ mov r0, r4 │ │ mov r1, #73 @ 0x49 │ │ bl 270da00 │ │ ldr r0, [pc, #48] @ 23f168c │ │ mov r1, #20 │ │ add r0, pc, r0 │ │ b 23f1514 │ │ - stc2l 15, cr13, [r2, #760]! @ 0x2f8 │ │ + stc2l 15, cr13, [r2, #940]! @ 0x3ac │ │ stc2l 3, cr11, [r5, #516]! @ 0x204 │ │ stc2l 9, cr3, [r2, #252]! @ 0xfc @ │ │ stc2l 15, cr8, [r5, #424]! @ 0x1a8 │ │ eorseq r6, r5, r0, lsl #30 │ │ - stc2l 5, cr15, [r3, #476]! @ 0x1dc │ │ + stc2l 5, cr15, [r3, #656]! @ 0x290 │ │ ldrsbteq r6, [r5], -r0 │ │ eorseq r6, r5, r4, lsr #29 │ │ eorseq r6, r5, r8, asr lr │ │ - stc2l 4, cr3, [r4, #884]! @ 0x374 │ │ - stc2l 11, cr7, [r3, #884]! @ 0x374 @ │ │ + stc2l 5, cr3, [r4, #40]! @ 0x28 │ │ + stc2l 12, cr7, [r3, #40]! @ 0x28 │ │ eorseq r6, r5, r4, lsr #31 │ │ - stc2l 14, cr11, [r3, #144]! @ 0x90 │ │ - stc2l 14, cr13, [r2, #744]! @ 0x2e8 │ │ - stc2l 14, cr13, [r2, #8]! │ │ + stc2l 14, cr11, [r3, #324]! @ 0x144 │ │ + stc2l 14, cr13, [r2, #924]! @ 0x39c │ │ + stc2l 14, cr13, [r2, #188]! @ 0xbc │ │ │ │ 023f16a0 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ cmp r0, #0 │ │ beq 23f1700 │ │ ldrb r2, [r0] │ │ @@ -1221558,32 +1221558,32 @@ │ │ bl 270ce60 │ │ ldr r0, [pc, #52] @ 23f1808 │ │ add r0, pc, r0 │ │ bl 270ce70 │ │ mov r0, r4 │ │ pop {r4, r5, r6, sl, fp, lr} │ │ b 270ce40 │ │ - stc2l 4, cr3, [r4, #240]! @ 0xf0 │ │ + stc2l 4, cr3, [r4, #420]! @ 0x1a4 │ │ stc2l 13, cr8, [r5, #404]! @ 0x194 │ │ - stc2l 7, cr1, [r3, #884]! @ 0x374 │ │ - stc2l 10, cr9, [r3, #984]! @ 0x3d8 @ │ │ + vcmla.f16 d17, d3, d10, #270 │ │ + stc2l 11, cr9, [r3, #140]! @ 0x8c @ │ │ stc2l 2, cr1, [r5, #404]! @ 0x194 │ │ - stc2l 4, cr3, [r4, #48]! @ 0x30 │ │ - stc2l 10, cr9, [r3, #760]! @ 0x2f8 @ │ │ - stc2l 7, cr1, [r3, #692]! @ 0x2b4 │ │ - stc2l 10, cr9, [r3, #792]! @ 0x318 @ │ │ - stc2l 11, cr9, [r2, #680]! @ 0x2a8 @ │ │ - stc2l 3, cr3, [r4, #880]! @ 0x370 │ │ + stc2l 4, cr3, [r4, #228]! @ 0xe4 │ │ + stc2l 10, cr9, [r3, #940]! @ 0x3ac @ │ │ + stc2l 7, cr1, [r3, #872]! @ 0x368 │ │ + stc2l 10, cr9, [r3, #972]! @ 0x3cc @ │ │ + stc2l 11, cr9, [r2, #860]! @ 0x35c @ │ │ + stc2l 4, cr3, [r4, #36]! @ 0x24 │ │ stc2l 13, cr8, [r5, #20]! │ │ - stc2l 7, cr1, [r3, #500]! @ 0x1f4 │ │ - stc2l 4, cr3, [r3, #24]! │ │ - stc2l 3, cr3, [r4, #640]! @ 0x280 │ │ - stc2l 10, cr9, [r3, #328]! @ 0x148 @ │ │ - stc2l 7, cr1, [r3, #260]! @ 0x104 │ │ - stc2l 3, cr3, [r3, #808]! @ 0x328 │ │ + stc2l 7, cr1, [r3, #680]! @ 0x2a8 │ │ + stc2l 4, cr3, [r3, #204]! @ 0xcc │ │ + stc2l 3, cr3, [r4, #820]! @ 0x334 │ │ + stc2l 10, cr9, [r3, #508]! @ 0x1fc @ │ │ + stc2l 7, cr1, [r3, #440]! @ 0x1b8 │ │ + stc2l 3, cr3, [r3, #988]! @ 0x3dc │ │ │ │ 023f182c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #644 @ 0x284 │ │ sub sp, sp, #3072 @ 0xc00 │ │ mov r9, r3 │ │ @@ -1221898,24 +1221898,24 @@ │ │ ldr r0, [pc, #56] @ 23f1d30 │ │ add r0, pc, r0 │ │ bl 270ce70 │ │ mov r0, r4 │ │ sub sp, fp, #8 │ │ pop {r4, sl, fp, lr} │ │ b 270ce40 │ │ - stc2l 7, cr15, [r2, #284]! @ 0x11c │ │ + stc2l 7, cr15, [r2, #464]! @ 0x1d0 │ │ stc2l 7, cr8, [r5, #900]! @ 0x384 │ │ - stc2l 2, cr1, [r3, #356]! @ 0x164 │ │ - stc2l 5, cr9, [r3, #456]! @ 0x1c8 │ │ + stc2l 2, cr1, [r3, #536]! @ 0x218 │ │ + stc2l 5, cr9, [r3, #636]! @ 0x27c │ │ stc2l 13, cr0, [r5, #260]! @ 0x104 │ │ - stc2l 7, cr15, [r2, #44]! @ 0x2c │ │ - stc2l 5, cr9, [r3, #184]! @ 0xb8 │ │ - stc2l 2, cr1, [r3, #116]! @ 0x74 │ │ - stc2l 5, cr9, [r3, #216]! @ 0xd8 │ │ - stc2l 6, cr9, [r2, #536]! @ 0x218 │ │ + stc2l 7, cr15, [r2, #224]! @ 0xe0 │ │ + stc2l 5, cr9, [r3, #364]! @ 0x16c │ │ + stc2l 2, cr1, [r3, #296]! @ 0x128 │ │ + stc2l 5, cr9, [r3, #396]! @ 0x18c │ │ + stc2l 6, cr9, [r2, #716]! @ 0x2cc │ │ │ │ 023f1d34 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #652 @ 0x28c │ │ sub sp, sp, #3072 @ 0xc00 │ │ mov r5, r2 │ │ @@ -1222142,24 +1222142,24 @@ │ │ ldr r0, [pc, #52] @ 23f20dc │ │ add r0, pc, r0 │ │ bl 270ce70 │ │ ldr r0, [pc, #44] @ 23f20e0 │ │ add r0, pc, r0 │ │ pop {r4, sl, fp, lr} │ │ b 270ce40 │ │ - stc2l 3, cr5, [r3, #452]! @ 0x1c4 │ │ + stc2l 3, cr5, [r3, #632]! @ 0x278 │ │ stc2l 4, cr8, [r5, #132]! @ 0x84 │ │ - stc2l 14, cr0, [r3, #612]! @ 0x264 │ │ + stc2l 14, cr0, [r3, #792]! @ 0x318 │ │ stc2l 5, cr10, [r5, #968]! @ 0x3c8 │ │ stc2l 9, cr0, [r5, #258]! @ 0x102 @ │ │ - stc2l 1, cr9, [r3, #504]! @ 0x1f8 │ │ - stc2l 14, cr0, [r3, #436]! @ 0x1b4 │ │ + stc2l 1, cr9, [r3, #684]! @ 0x2ac │ │ + stc2l 14, cr0, [r3, #616]! @ 0x268 │ │ stc2l 5, cr10, [r5, #792]! @ 0x318 │ │ - stc2l 2, cr9, [r2, #856]! @ 0x358 │ │ - stc2l 2, cr5, [r3, #900]! @ 0x384 │ │ + stc2l 3, cr9, [r2, #12]! │ │ + stc2l 3, cr5, [r3, #56]! @ 0x38 │ │ │ │ 023f20e4 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r6, r0 │ │ ldr r0, [pc, #288] @ 23f2218 │ │ mov r5, r2 │ │ @@ -1222233,26 +1222233,26 @@ │ │ bl 270dd40 │ │ mov r0, r4 │ │ mov r1, r5 │ │ bl 270d990 │ │ b 23f21dc │ │ stc2l 13, cr2, [r2, #800]! @ 0x320 │ │ stc2l 3, cr8, [r5, #68]! @ 0x44 │ │ - stc2l 13, cr0, [r3, #548]! @ 0x224 │ │ - stc2l 9, cr4, [r4, #136]! @ 0x88 @ │ │ + stc2l 13, cr0, [r3, #728]! @ 0x2d8 │ │ + stc2l 9, cr4, [r4, #226]! @ 0xe2 @ │ │ vcmla.f16 d16, d5, d21, #270 │ │ - stc2l 0, cr9, [r3, #488]! @ 0x1e8 │ │ - stc2l 13, cr0, [r3, #420]! @ 0x1a4 │ │ - stc2l 9, cr4, [r4, #72]! @ 0x48 @ │ │ - stc2l 1, cr9, [r2, #840]! @ 0x348 │ │ + stc2l 0, cr9, [r3, #668]! @ 0x29c │ │ + stc2l 13, cr0, [r3, #600]! @ 0x258 │ │ + stc2l 9, cr4, [r4, #162]! @ 0xa2 @ │ │ + stc2l 1, cr9, [r2, #1020]! @ 0x3fc │ │ stc2l 2, cr8, [r5, #788]! @ 0x314 │ │ - stc2l 13, cr0, [r3, #244]! @ 0xf4 │ │ + stc2l 13, cr0, [r3, #424]! @ 0x1a8 │ │ stc2l 4, cr5, [r2, #904]! @ 0x388 │ │ - stc2l 15, cr10, [r2, #120]! @ 0x78 │ │ - stc2l 13, cr0, [r3, #788]! @ 0x314 │ │ + stc2l 15, cr10, [r2, #300]! @ 0x12c │ │ + stc2l 13, cr0, [r3, #968]! @ 0x3c8 │ │ stc2l 5, cr5, [r2, #424]! @ 0x1a8 │ │ stc2l 3, cr4, [r5, #232]! @ 0xe8 │ │ stc2l 12, cr2, [r2, #912]! @ 0x390 │ │ │ │ 023f225c : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ @@ -1222342,18 +1222342,18 @@ │ │ mov r0, r5 │ │ mov r1, r8 │ │ bl 270da80 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ stc2l 3, cr7, [r2, #772]! @ 0x304 │ │ - stc2l 0, cr9, [r2, #784]! @ 0x310 │ │ + stc2l 0, cr9, [r2, #964]! @ 0x3c4 │ │ stc2l 10, cr14, [r4, #920]! @ 0x398 @ │ │ eorseq r6, r5, r0, ror #2 │ │ - stc2l 13, cr14, [r3, #584]! @ 0x248 │ │ + stc2l 13, cr14, [r3, #764]! @ 0x2fc │ │ stc2l 3, cr5, [r2, #264]! @ 0x108 │ │ │ │ 023f23e0 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r1 │ │ ldr r1, [pc, #2544] @ 23f2de4 │ │ @@ -1222991,109 +1222991,109 @@ │ │ ldr r1, [pc, #404] @ 23f2f68 │ │ mov r0, r5 │ │ mov r2, r4 │ │ mov r3, #25 │ │ add r1, pc, r1 │ │ b 23f2b38 │ │ stc2l 0, cr8, [r5, #760]! @ 0x2f8 │ │ - stc2l 9, cr4, [r3, #220]! @ 0xdc @ │ │ + stc2l 9, cr4, [r3, #310]! @ 0x136 @ │ │ stc2l 2, cr5, [r2, #656]! @ 0x290 │ │ - stc2l 9, cr8, [r2, #168]! @ 0xa8 @ │ │ + stc2l 9, cr8, [r2, #258]! @ 0x102 @ │ │ stc2l 14, cr11, [r5, #776]! @ 0x308 │ │ stc2l 3, cr14, [r4, #444]! @ 0x1bc │ │ stc2l 0, cr8, [r5, #424]! @ 0x1a8 │ │ - stc2l 7, cr8, [r3, #660]! @ 0x294 │ │ - stc2l 14, cr12, [r3, #132]! @ 0x84 │ │ + stc2l 7, cr8, [r3, #840]! @ 0x348 │ │ + stc2l 14, cr12, [r3, #312]! @ 0x138 │ │ stc2l 13, cr9, [r5, #420]! @ 0x1a4 │ │ stc2l 0, cr4, [r5, #48]! @ 0x30 │ │ - stc2l 7, cr8, [r3, #696]! @ 0x2b8 │ │ - stc2l 15, cr4, [r3, #72]! @ 0x48 │ │ + stc2l 7, cr8, [r3, #876]! @ 0x36c │ │ + stc2l 15, cr4, [r3, #252]! @ 0xfc │ │ stc2l 10, cr3, [r5, #36]! @ 0x24 @ │ │ stc2l 10, cr12, [r4, #228]! @ 0xe4 @ │ │ - stc2l 7, cr6, [r3, #488]! @ 0x1e8 │ │ + stc2l 7, cr6, [r3, #668]! @ 0x29c │ │ stc2l 5, cr6, [r5, #404]! @ 0x194 │ │ - stc2l 7, cr8, [r3, #536]! @ 0x218 │ │ - stc2l 6, cr2, [r4, #160]! @ 0xa0 │ │ - stc2l 8, cr4, [r3, #968]! @ 0x3c8 │ │ - stc2l 14, cr14, [r2, #608]! @ 0x260 │ │ + stc2l 7, cr8, [r3, #716]! @ 0x2cc │ │ + stc2l 6, cr2, [r4, #340]! @ 0x154 │ │ + stc2l 9, cr4, [r3, #62]! @ 0x3e @ │ │ + stc2l 14, cr14, [r2, #788]! @ 0x314 │ │ stc2l 2, cr10, [r4, #412]! @ 0x19c │ │ vcmla.f16 d22, d20, d9, #270 │ │ - stc2l 8, cr10, [r3, #108]! @ 0x6c │ │ - stc2l 14, cr14, [r2, #444]! @ 0x1bc │ │ + vcmla.f16 q13, , q4, #270 │ │ + stc2l 14, cr14, [r2, #624]! @ 0x270 │ │ stc2l 4, cr13, [r5, #240]! @ 0xf0 │ │ stc2l 4, cr6, [r5, #888]! @ 0x378 │ │ stc2l 2, cr14, [r4, #688]! @ 0x2b0 │ │ - stc2l 14, cr8, [r2, #24]! │ │ - stc2l 3, cr0, [r3, #692]! @ 0x2b4 │ │ - stc2l 12, cr6, [r3, #356]! @ 0x164 │ │ - stc2l 15, cr1, [r4, #916]! @ 0x394 │ │ + stc2l 14, cr8, [r2, #204]! @ 0xcc │ │ + stc2l 3, cr0, [r3, #872]! @ 0x368 │ │ + stc2l 12, cr6, [r3, #536]! @ 0x218 │ │ + stc2l 0, cr2, [r4, #72]! @ 0x48 │ │ stc2l 13, cr11, [r5, #100]! @ 0x64 │ │ - stc2l 6, cr6, [r3, #984]! @ 0x3d8 │ │ - stc2l 13, cr4, [r3, #1020]! @ 0x3fc │ │ + stc2l 7, cr6, [r3, #140]! @ 0x8c │ │ + stc2l 14, cr4, [r3, #176]! @ 0xb0 │ │ stc2l 11, cr4, [r2, #196]! @ 0xc4 @ │ │ - stc2l 14, cr2, [r3, #152]! @ 0x98 │ │ + stc2l 14, cr2, [r3, #332]! @ 0x14c │ │ stc2l 3, cr12, [r4, #436]! @ 0x1b4 │ │ - stc2l 7, cr0, [r4, #948]! @ 0x3b4 │ │ - stc2l 6, cr6, [r3, #912]! @ 0x390 │ │ - stc2l 7, cr0, [r4, #900]! @ 0x384 │ │ - stc2l 2, cr0, [r4, #580]! @ 0x244 │ │ + stc2l 8, cr0, [r4, #104]! @ 0x68 │ │ + stc2l 7, cr6, [r3, #68]! @ 0x44 │ │ + vcmla.f16 d16, d4, d14, #270 │ │ + stc2l 2, cr0, [r4, #760]! @ 0x2f8 │ │ stc2l 7, cr14, [r4, #520]! @ 0x208 │ │ vcmla.f16 , , q14, #270 │ │ - stc2l 11, cr12, [r3, #980]! @ 0x3d4 @ │ │ + stc2l 12, cr12, [r3, #136]! @ 0x88 │ │ stc2l 1, cr6, [r4, #988]! @ 0x3dc │ │ stc2l 15, cr4, [r2, #824]! @ 0x338 │ │ stc2l 2, cr2, [r2, #740]! @ 0x2e4 │ │ - stc2l 12, cr12, [r2, #808]! @ 0x328 │ │ - stc2l 3, cr0, [r3, #100]! @ 0x64 │ │ - stc2l 13, cr2, [r3, #380]! @ 0x17c │ │ - stc2l 7, cr14, [r2, #868]! @ 0x364 │ │ + stc2l 12, cr12, [r2, #988]! @ 0x3dc │ │ + stc2l 3, cr0, [r3, #280]! @ 0x118 │ │ + stc2l 13, cr2, [r3, #560]! @ 0x230 │ │ + vcmla.f16 d30, d2, d6, #270 │ │ stc2l 13, cr7, [r5, #752]! @ 0x2f0 │ │ - stc2l 7, cr4, [r3, #968]! @ 0x3c8 │ │ - stc2l 11, cr8, [r3, #244]! @ 0xf4 @ │ │ + stc2l 8, cr4, [r3, #124]! @ 0x7c │ │ + stc2l 11, cr8, [r3, #424]! @ 0x1a8 @ │ │ stc2l 6, cr11, [r5, #848]! @ 0x350 │ │ - stc2l 11, cr12, [r3, #304]! @ 0x130 @ │ │ - stc2l 15, cr1, [r4, #56]! @ 0x38 │ │ + stc2l 11, cr12, [r3, #484]! @ 0x1e4 @ │ │ + stc2l 15, cr1, [r4, #236]! @ 0xec │ │ stc2l 13, cr7, [r5, #468]! @ 0x1d4 │ │ stc2l 1, cr10, [r4, #120]! @ 0x78 │ │ stc2l 6, cr10, [r4, #68]! @ 0x44 │ │ - stc2l 7, cr4, [r3, #900]! @ 0x384 │ │ - stc2l 10, cr8, [r3, #856]! @ 0x358 @ │ │ + vcmla.f16 d20, d3, d14, #270 │ │ + stc2l 11, cr8, [r3, #12]! @ │ │ stc2l 2, cr13, [r5, #900]! @ 0x384 │ │ stc2l 7, cr13, [r5, #716]! @ 0x2cc │ │ stc2l 2, cr2, [r2, #292]! @ 0x124 │ │ stc2l 5, cr10, [r4, #780]! @ 0x30c │ │ stc2l 2, cr12, [r4, #632]! @ 0x278 │ │ - stc2l 10, cr6, [r3, #644]! @ 0x284 @ │ │ + stc2l 10, cr6, [r3, #824]! @ 0x338 @ │ │ stc2l 8, cr3, [r5, #104]! @ 0x68 │ │ stc2l 7, cr13, [r5, #412]! @ 0x19c │ │ stc2l 2, cr12, [r4, #560]! @ 0x230 │ │ stc2l 1, cr0, [r5, #560]! @ 0x230 │ │ stc2l 6, cr11, [r5, #364]! @ 0x16c │ │ stc2l 5, cr6, [r4, #524]! @ 0x20c │ │ stc2l 6, cr11, [r5, #472]! @ 0x1d8 │ │ - stc2l 10, cr10, [r3, #608]! @ 0x260 @ │ │ - stc2l 5, cr12, [r3, #740]! @ 0x2e4 │ │ - stc2l 7, cr10, [r2, #580]! @ 0x244 │ │ + stc2l 10, cr10, [r3, #788]! @ 0x314 @ │ │ + stc2l 5, cr12, [r3, #920]! @ 0x398 │ │ + stc2l 7, cr10, [r2, #760]! @ 0x2f8 │ │ stc2l 10, cr9, [r5, #884]! @ 0x374 @ │ │ - stc2l 11, cr4, [r3, #712]! @ 0x2c8 @ │ │ + stc2l 11, cr4, [r3, #892]! @ 0x37c @ │ │ stc2l 0, cr10, [r4, #680]! @ 0x2a8 │ │ stc2l 1, cr6, [r5, #468]! @ 0x1d4 │ │ - stc2l 6, cr12, [r2, #580]! @ 0x244 │ │ + stc2l 6, cr12, [r2, #760]! @ 0x2f8 │ │ stc2l 6, cr13, [r5, #636]! @ 0x27c │ │ stc2l 1, cr8, [r4, #836]! @ 0x344 │ │ - stc2l 7, cr10, [r2, #168]! @ 0xa8 │ │ - stc2l 5, cr12, [r3, #632]! @ 0x278 │ │ - stc2l 10, cr8, [r2, #380]! @ 0x17c @ │ │ - stc2l 7, cr4, [r3, #196]! @ 0xc4 │ │ - stc2l 9, cr6, [r3, #174]! @ 0xae @ │ │ + stc2l 7, cr10, [r2, #348]! @ 0x15c │ │ + stc2l 5, cr12, [r3, #812]! @ 0x32c │ │ + stc2l 10, cr8, [r2, #560]! @ 0x230 @ │ │ + stc2l 7, cr4, [r3, #376]! @ 0x178 │ │ + stc2l 9, cr6, [r3, #264]! @ 0x108 @ │ │ stc2l 7, cr3, [r5, #544]! @ 0x220 │ │ stc2l 6, cr12, [r4, #8]! │ │ stc2l 8, cr6, [r2, #748]! @ 0x2ec │ │ - stc2l 7, cr14, [r3, #420]! @ 0x1a4 │ │ - stc2l 7, cr4, [r3, #172]! @ 0xac │ │ + stc2l 7, cr14, [r3, #600]! @ 0x258 │ │ + stc2l 7, cr4, [r3, #352]! @ 0x160 │ │ stc2l 14, cr9, [r5, #360]! @ 0x168 │ │ stc2l 1, cr2, [r2, #300]! @ 0x12c │ │ stc2l 4, cr4, [r2, #172]! @ 0xac │ │ │ │ 023f2f70 : │ │ mov ip, #0 │ │ cmp r2, r3 │ │ @@ -1223226,19 +1223226,19 @@ │ │ mov r2, r8 │ │ bl 270d9e0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ stc2l 14, cr3, [r2, #316]! @ 0x13c │ │ stc2l 14, cr5, [lr, #604]! @ 0x25c │ │ - stc2l 10, cr1, [r4, #964]! @ 0x3c4 @ │ │ - stc2l 1, cr8, [r3, #700]! @ 0x2bc │ │ + stc2l 11, cr1, [r4, #120]! @ 0x78 @ │ │ + stc2l 1, cr8, [r3, #880]! @ 0x370 │ │ stc2l 15, cr5, [lr, #92]! @ 0x5c │ │ - stc2l 2, cr8, [r3, #220]! @ 0xdc │ │ - stc2l 11, cr1, [r4, #164]! @ 0xa4 @ │ │ + stc2l 2, cr8, [r3, #400]! @ 0x190 │ │ + stc2l 11, cr1, [r4, #344]! @ 0x158 @ │ │ │ │ 023f3190 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ ldr r4, [r1] │ │ cmp r4, #1 │ │ blt 23f31e4 │ │ @@ -1223296,18 +1223296,18 @@ │ │ bl 270ce70 │ │ mov r0, r4 │ │ bl 270ce40 │ │ mov r0, #0 │ │ pop {r4, sl, fp, pc} │ │ mov r0, #1 │ │ pop {r4, sl, fp, pc} │ │ - stc2l 1, cr8, [r2, #772]! @ 0x304 │ │ + stc2l 1, cr8, [r2, #952]! @ 0x3b8 │ │ stc2l 2, cr7, [r5, #212]! @ 0xd4 │ │ - stc2l 12, cr15, [r2, #692]! @ 0x2b4 │ │ - stc2l 9, cr1, [r3, #108]! @ 0x6c @ │ │ + stc2l 12, cr15, [r2, #872]! @ 0x368 │ │ + stc2l 9, cr1, [r3, #198]! @ 0xc6 @ │ │ stc2l 7, cr15, [r4, #596]! @ 0x254 │ │ │ │ 023f3298 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #52 @ 0x34 │ │ mov r8, r0 │ │ @@ -1223467,44 +1223467,44 @@ │ │ ldr r2, [sp, #36] @ 0x24 │ │ add r0, pc, r0 │ │ ldr r1, [fp, #-36] @ 0xffffffdc │ │ str r1, [r2] │ │ bl 270ce40 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - stc2l 2, cr4, [r3, #364]! @ 0x16c │ │ + stc2l 2, cr4, [r3, #544]! @ 0x220 │ │ stc2l 1, cr7, [r5, #372]! @ 0x174 │ │ - stc2l 11, cr15, [r2, #852]! @ 0x354 @ │ │ - stc2l 0, cr14, [r2, #1000]! @ 0x3e8 │ │ + stc2l 12, cr15, [r2, #8]! │ │ + stc2l 1, cr14, [r2, #156]! @ 0x9c │ │ stc2l 5, cr15, [r4, #596]! @ 0x254 │ │ - stc2l 0, cr4, [r3, #636]! @ 0x27c │ │ - stc2l 14, cr7, [r3, #792]! @ 0x318 │ │ - stc2l 11, cr15, [r2, #724]! @ 0x2d4 @ │ │ - stc2l 0, cr14, [r2, #872]! @ 0x368 │ │ - stc2l 0, cr8, [r2, #120]! @ 0x78 │ │ + stc2l 0, cr4, [r3, #816]! @ 0x330 │ │ + stc2l 14, cr7, [r3, #972]! @ 0x3cc │ │ + stc2l 11, cr15, [r2, #904]! @ 0x388 @ │ │ + stc2l 1, cr14, [r2, #28]! │ │ + stc2l 0, cr8, [r2, #300]! @ 0x12c │ │ stc2l 1, cr7, [r5, #68]! @ 0x44 │ │ - stc2l 11, cr15, [r2, #548]! @ 0x224 @ │ │ + stc2l 11, cr15, [r2, #728]! @ 0x2d8 @ │ │ stc2l 2, cr9, [r5, #904]! @ 0x388 │ │ - stc2l 13, cr9, [r2, #376]! @ 0x178 │ │ - stc2l 12, cr15, [r2, #20]! │ │ + stc2l 13, cr9, [r2, #556]! @ 0x22c │ │ + stc2l 12, cr15, [r2, #200]! @ 0xc8 │ │ stc2l 3, cr9, [r5, #376]! @ 0x178 │ │ stc2l 0, cr3, [r5, #376]! @ 0x178 │ │ stc2l 0, cr7, [r5, #692]! @ 0x2b4 │ │ - stc2l 11, cr15, [r2, #148]! @ 0x94 @ │ │ + stc2l 11, cr15, [r2, #328]! @ 0x148 @ │ │ stc2l 10, cr5, [r4, #336]! @ 0x150 @ │ │ - stc2l 12, cr9, [r2, #696]! @ 0x2b8 │ │ - stc2l 11, cr15, [r2, #340]! @ 0x154 @ │ │ + stc2l 12, cr9, [r2, #876]! @ 0x36c │ │ + stc2l 11, cr15, [r2, #520]! @ 0x208 @ │ │ stc2l 10, cr5, [r4, #528]! @ 0x210 @ │ │ stc2l 0, cr7, [r5, #212]! @ 0xd4 │ │ - stc2l 10, cr15, [r2, #692]! @ 0x2b4 @ │ │ + stc2l 10, cr15, [r2, #872]! @ 0x368 @ │ │ stc2l 2, cr6, [r2, #312]! @ 0x138 │ │ - stc2l 12, cr9, [r2, #264]! @ 0x108 │ │ - stc2l 10, cr15, [r2, #932]! @ 0x3a4 @ │ │ + stc2l 12, cr9, [r2, #444]! @ 0x1bc │ │ + stc2l 11, cr15, [r2, #88]! @ 0x58 @ │ │ stc2l 2, cr6, [r2, #552]! @ 0x228 │ │ - stc2l 15, cr3, [r3, #1020]! @ 0x3fc │ │ + stc2l 0, cr4, [r3, #176]! @ 0xb0 │ │ │ │ 023f35a0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #220 @ 0xdc │ │ sub sp, sp, #1024 @ 0x400 │ │ sub r0, r0, #1 │ │ @@ -1224493,15 +1224493,15 @@ │ │ ldr r4, [pc, #3712] @ 23f5394 │ │ add r5, pc, r5 │ │ ldr r6, [pc, #3708] @ 23f5398 │ │ mov r8, #0 │ │ add r4, pc, r4 │ │ add r6, pc, r6 │ │ b 23f45f8 │ │ - stc2l 11, cr13, [r3, #236]! @ 0xec @ │ │ + stc2l 11, cr13, [r3, #416]! @ 0x1a0 @ │ │ eorseq lr, r9, r8, lsr r4 │ │ ldr r0, [pc, #3684] @ 23f539c │ │ mov r1, r8 │ │ mov r2, r6 │ │ movw r3, #3260 @ 0xcbc │ │ add r0, pc, r0 │ │ bl 270da30 │ │ @@ -1224565,22 +1224565,22 @@ │ │ add r0, pc, r0 │ │ str sl, [r0, r8, lsl #2] │ │ b 23f45cc │ │ subeq sp, lr, ip, lsr r6 │ │ mov r0, #0 │ │ str r0, [r1] │ │ b 23f6e38 │ │ - stc2l 10, cr9, [r2, #296]! @ 0x128 @ │ │ - stc2l 14, cr3, [r3, #636]! @ 0x27c │ │ - stc2l 4, cr3, [r4, #220]! @ 0xdc │ │ + stc2l 10, cr9, [r2, #476]! @ 0x1dc @ │ │ + stc2l 14, cr3, [r3, #816]! @ 0x330 │ │ + stc2l 4, cr3, [r4, #400]! @ 0x190 │ │ ldrhteq lr, [r9], -ip │ │ - stc2l 10, cr13, [r3, #684]! @ 0x2ac @ │ │ + stc2l 10, cr13, [r3, #864]! @ 0x360 @ │ │ eorseq r4, r5, ip, ror #27 │ │ - stc2l 4, cr1, [r4, #804]! @ 0x324 │ │ - stc2l 7, cr15, [r2, #948]! @ 0x3b4 │ │ + stc2l 4, cr1, [r4, #984]! @ 0x3d8 │ │ + stc2l 8, cr15, [r2, #104]! @ 0x68 │ │ ldr r0, [pc, #3412] @ 23f53c4 │ │ mov r1, r5 │ │ ldr r6, [pc, #3408] @ 23f53c8 │ │ movw r3, #2949 @ 0xb85 │ │ add r0, pc, r0 │ │ add r6, pc, r6 │ │ mov r2, r6 │ │ @@ -1224623,38 +1224623,38 @@ │ │ bl 270da30 │ │ mov r1, r0 │ │ rsb r1, r1, r1, lsl #8 │ │ ldr r0, [fp, #20] │ │ add r1, r9, r1 │ │ mov r2, sl │ │ b 23f534c │ │ - stc2l 12, cr11, [r3, #280]! @ 0x118 │ │ + stc2l 12, cr11, [r3, #460]! @ 0x1cc │ │ ldr r3, [sp, #48] @ 0x30 │ │ b 23f4d2c │ │ eorseq r4, r5, r4, asr sp │ │ ldr r0, [pc, #4004] @ 23f56ec │ │ ldr r1, [pc, #4004] @ 23f56f0 │ │ ldr r2, [fp, #8] │ │ add r0, pc, r0 │ │ ldr r1, [pc, r1] │ │ str r1, [r2] │ │ b 23f6e30 │ │ stc2l 6, cr5, [r4, #860]! @ 0x35c │ │ - stc2l 9, cr13, [r3, #470]! @ 0x1d6 @ │ │ - stc2l 4, cr1, [r4, #720]! @ 0x2d0 │ │ + stc2l 10, cr13, [r3, #96]! @ 0x60 @ │ │ + stc2l 4, cr1, [r4, #900]! @ 0x384 │ │ ldrsbteq lr, [r9], -r0 │ │ subeq sp, lr, r0, lsr r5 │ │ - stc2l 7, cr15, [r2, #660]! @ 0x294 │ │ + stc2l 7, cr15, [r2, #840]! @ 0x348 │ │ stc2l 7, cr9, [r4, #280]! @ 0x118 │ │ strheq r7, [pc], #-172 @ │ │ - stc2l 10, cr7, [r3, #800]! @ 0x320 @ │ │ - stc2l 12, cr7, [r2, #712]! @ 0x2c8 │ │ + stc2l 10, cr7, [r3, #980]! @ 0x3d4 @ │ │ + stc2l 12, cr7, [r2, #892]! @ 0x37c │ │ stc2l 13, cr2, [r5, #616]! @ 0x268 │ │ stc2l 1, cr15, [r4, #276]! @ 0x114 │ │ - stc2l 12, cr3, [r3, #548]! @ 0x224 │ │ + stc2l 12, cr3, [r3, #728]! @ 0x2d8 │ │ stc2l 11, cr6, [r5, #952]! @ 0x3b8 @ │ │ subeq r7, pc, r8, lsr r9 @ │ │ stc2l 11, cr6, [r5, #728]! @ 0x2d8 @ │ │ stc2l 11, cr6, [r5, #568]! @ 0x238 @ │ │ ldrdeq r7, [pc], #-136 @ │ │ stc2l 11, cr6, [r5, #344]! @ 0x158 @ │ │ subeq r7, pc, r0, lsr #17 │ │ @@ -1224886,20 +1224886,20 @@ │ │ mov r1, #17 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #4072] @ 23f5b2c │ │ add r0, pc, r0 │ │ b 23f6e30 │ │ stc2l 9, cr6, [r5, #402]! @ 0x192 @ │ │ - stc2l 9, cr7, [r2, #172]! @ 0xac @ │ │ - stc2l 9, cr3, [r3, #362]! @ 0x16a @ │ │ + stc2l 9, cr7, [r2, #262]! @ 0x106 @ │ │ + stc2l 9, cr3, [r3, #452]! @ 0x1c4 @ │ │ stc2l 13, cr14, [r4, #948]! @ 0x3b4 │ │ stc2l 2, cr9, [r4, #656]! @ 0x290 │ │ stc2l 9, cr2, [r5, #268]! @ 0x10c @ │ │ - stc2l 5, cr7, [r3, #1008]! @ 0x3f0 │ │ + stc2l 6, cr7, [r3, #164]! @ 0xa4 │ │ ldr r1, [fp, #24] │ │ mov r0, #1 │ │ ldr r5, [sp, #32] │ │ movw sl, #5300 @ 0x14b4 │ │ ldr r6, [fp, #32] │ │ str r0, [r1] │ │ ldr r0, [r5] │ │ @@ -1225022,23 +1225022,23 @@ │ │ bl 270df10 │ │ ldr r0, [pc, #3900] @ 23f5c98 │ │ add r0, pc, r0 │ │ b 23f6e30 │ │ ldrsbteq sp, [r9], -ip │ │ ldrsbteq sp, [r9], -ip │ │ stc2l 1, cr9, [r4, #104]! @ 0x68 │ │ - stc2l 1, cr15, [r2, #452]! @ 0x1c4 │ │ + stc2l 1, cr15, [r2, #632]! @ 0x278 │ │ subeq ip, lr, r4, ror #29 │ │ subeq r7, pc, r0, ror #8 │ │ subeq r7, lr, ip, lsl #23 │ │ eorseq sp, r9, r8, lsl ip │ │ stc2l 12, cr4, [r5, #264]! @ 0x108 │ │ stc2l 5, cr6, [r5, #1012]! @ 0x3f4 │ │ - stc2l 5, cr7, [r2, #568]! @ 0x238 │ │ - stc2l 5, cr3, [r3, #948]! @ 0x3b4 │ │ + stc2l 5, cr7, [r2, #748]! @ 0x2ec │ │ + stc2l 6, cr3, [r3, #104]! @ 0x68 │ │ stc2l 10, cr14, [r4, #132]! @ 0x84 @ │ │ stc2l 14, cr8, [r4, #848]! @ 0x350 │ │ stc2l 5, cr2, [r5, #712]! @ 0x2c8 │ │ ldr r1, [sp, #48] @ 0x30 │ │ movw r0, #5301 @ 0x14b5 │ │ sub r2, r1, #1 │ │ cmp r1, r0 │ │ @@ -1225227,15 +1225227,15 @@ │ │ bl 270d9d0 │ │ cmp r0, #0 │ │ mov r2, r8 │ │ addne r9, r9, #1 │ │ b 23f50ac │ │ mov r5, r2 │ │ b 23f50ac │ │ - stc2l 2, cr7, [r3, #144]! @ 0x90 │ │ + stc2l 2, cr7, [r3, #324]! @ 0x144 │ │ mov r2, r8 │ │ mov r5, r8 │ │ ldr r1, [pc, #3968] @ 23f6034 │ │ add r0, sl, #1 │ │ ldr r1, [pc, r1] │ │ cmp sl, r1 │ │ bge 23f50cc │ │ @@ -1225243,19 +1225243,19 @@ │ │ mov sl, r0 │ │ blt 23f4f80 │ │ str r5, [fp, #-40] @ 0xffffffd8 │ │ ldr r4, [pc, #3936] @ 23f6038 │ │ add r4, pc, r4 │ │ b 23f53e8 │ │ stc2l 14, cr11, [r5, #980]! @ 0x3d4 │ │ - stc2l 3, cr11, [r2, #216]! @ 0xd8 │ │ + stc2l 3, cr11, [r2, #396]! @ 0x18c │ │ eorseq sp, r9, ip, lsr #18 │ │ eorseq sp, r9, r0, lsl r9 │ │ - stc2l 1, cr5, [r3, #676]! @ 0x2a4 │ │ - stc2l 13, cr14, [r2, #1012]! @ 0x3f4 │ │ + stc2l 1, cr5, [r3, #856]! @ 0x358 │ │ + stc2l 14, cr14, [r2, #168]! @ 0xa8 │ │ ldr r2, [fp, #24] │ │ mov r1, #1 │ │ ldr r0, [fp, #-68] @ 0xffffffbc │ │ movw r5, #5300 @ 0x14b4 │ │ str r1, [r2] │ │ sub r1, r0, #1 │ │ cmp r1, r5 │ │ @@ -1225334,21 +1225334,21 @@ │ │ bl 270db90 │ │ cmp r0, #0 │ │ beq 23f5774 │ │ ldr r0, [pc, #4004] @ 23f61e8 │ │ add r0, pc, r0 │ │ b 23f6e30 │ │ stc2l 12, cr8, [r4, #664]! @ 0x298 │ │ - stc2l 12, cr14, [r2, #1012]! @ 0x3f4 │ │ - stc2l 2, cr7, [r2, #552]! @ 0x228 │ │ + stc2l 13, cr14, [r2, #168]! @ 0xa8 │ │ + stc2l 2, cr7, [r2, #732]! @ 0x2dc │ │ stc2l 12, cr8, [r4, #312]! @ 0x138 │ │ - stc2l 12, cr14, [r2, #660]! @ 0x294 │ │ - stc2l 2, cr3, [r3, #804]! @ 0x324 │ │ + stc2l 12, cr14, [r2, #840]! @ 0x348 │ │ + stc2l 2, cr3, [r3, #984]! @ 0x3d8 │ │ stc2l 11, cr8, [r4, #984]! @ 0x3d8 @ │ │ - stc2l 12, cr14, [r2, #308]! @ 0x134 │ │ + stc2l 12, cr14, [r2, #488]! @ 0x1e8 │ │ stc2l 6, cr14, [r4, #948]! @ 0x3b4 │ │ ldr r0, [pc, #3960] @ 23f61ec │ │ movw r3, #2602 @ 0xa2a │ │ ldr r2, [pc, #3956] @ 23f61f0 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1225402,47 +1225402,47 @@ │ │ mov r2, sl │ │ add r1, r4, r0 │ │ mov r0, r5 │ │ mov r3, #255 @ 0xff │ │ bl 270d9e0 │ │ b 23f6e38 │ │ stc2l 11, cr8, [r4, #632]! @ 0x278 @ │ │ - stc2l 11, cr14, [r2, #980]! @ 0x3d4 @ │ │ + stc2l 12, cr14, [r2, #136]! @ 0x88 │ │ stc2l 11, cr8, [r4, #528]! @ 0x210 @ │ │ stc2l 11, cr8, [r4, #280]! @ 0x118 @ │ │ - stc2l 11, cr14, [r2, #628]! @ 0x274 @ │ │ + stc2l 11, cr14, [r2, #808]! @ 0x328 @ │ │ stc2l 2, cr2, [r5, #328]! @ 0x148 │ │ stc2l 10, cr8, [r4, #936]! @ 0x3a8 @ │ │ - stc2l 11, cr14, [r2, #260]! @ 0x104 @ │ │ - stc2l 14, cr6, [r3, #656]! @ 0x290 │ │ + stc2l 11, cr14, [r2, #440]! @ 0x1b8 @ │ │ + stc2l 14, cr6, [r3, #836]! @ 0x344 │ │ stc2l 10, cr8, [r4, #568]! @ 0x238 @ │ │ - stc2l 10, cr14, [r2, #916]! @ 0x394 @ │ │ + stc2l 11, cr14, [r2, #72]! @ 0x48 @ │ │ stc2l 11, cr11, [r5, #372]! @ 0x174 @ │ │ stc2l 5, cr4, [r5, #824]! @ 0x338 │ │ eorseq sp, r9, ip, ror r5 │ │ eorseq sp, r9, ip, asr r5 │ │ stc2l 9, cr2, [r2, #94]! @ 0x5e @ │ │ - stc2l 10, cr14, [r2, #260]! @ 0x104 @ │ │ - stc2l 13, cr4, [r3, #804]! @ 0x324 │ │ + stc2l 10, cr14, [r2, #440]! @ 0x1b8 @ │ │ + stc2l 13, cr4, [r3, #984]! @ 0x3d8 │ │ eorseq sp, r9, r4, lsl r5 │ │ stc2l 15, cr5, [r5, #728]! @ 0x2d8 │ │ strdeq r6, [pc], #-204 @ │ │ - stc2l 6, cr0, [r4, #632]! @ 0x278 │ │ + stc2l 6, cr0, [r4, #812]! @ 0x32c │ │ subeq r7, lr, r8, lsl #8 │ │ stc2l 9, cr8, [r4, #140]! @ 0x8c @ │ │ subeq ip, lr, ip, lsl #14 │ │ subeq r6, pc, r8, ror #24 │ │ subeq r7, lr, ip, lsl #7 │ │ stc2l 14, cr5, [r5, #728]! @ 0x2d8 │ │ - vcmla.f16 q15, q9, , #270 │ │ + stc2l 9, cr14, [r2, #36]! @ 0x24 @ │ │ strdeq r6, [pc], #-180 @ │ │ - stc2l 5, cr0, [r4, #584]! @ 0x248 │ │ + stc2l 5, cr0, [r4, #764]! @ 0x2fc │ │ subeq r7, lr, r4, lsl #6 │ │ - stc2l 5, cr0, [r4, #408]! @ 0x198 │ │ - vcmla.f16 d30, d18, d9, #270 │ │ + stc2l 5, cr0, [r4, #588]! @ 0x24c │ │ + stc2l 8, cr14, [r2, #728]! @ 0x2d8 │ │ mov r9, #0 │ │ mov r0, #1 │ │ str r0, [sp, #428] @ 0x1ac │ │ sub r0, r9, #1 │ │ clz r0, r0 │ │ lsr r9, r0, #5 │ │ ldr r1, [sp, #48] @ 0x30 │ │ @@ -1225628,16 +1225628,16 @@ │ │ str r1, [sp, #32] │ │ add sl, pc, sl │ │ str r1, [sp, #28] │ │ str r1, [sp, #24] │ │ str r1, [sp, #36] @ 0x24 │ │ b 23f594c │ │ ldrdeq r7, [lr], #-32 @ 0xffffffe0 │ │ - stc2l 11, cr4, [r3, #1012]! @ 0x3f4 @ │ │ - stc2l 8, cr14, [r2, #324]! @ 0x144 │ │ + stc2l 12, cr4, [r3, #168]! @ 0xa8 │ │ + stc2l 8, cr14, [r2, #504]! @ 0x1f8 │ │ stc2l 3, cr4, [r5, #376]! @ 0x178 │ │ eorseq sp, r9, r8, lsl r3 │ │ mov r0, #0 │ │ mov r7, #1 │ │ cmp r9, #0 │ │ str r0, [sp, #44] @ 0x2c │ │ beq 23f574c │ │ @@ -1225661,17 +1225661,17 @@ │ │ mov r5, #1 │ │ mov r4, #1 │ │ mov r6, #1 │ │ mov sl, #1 │ │ b 23f64e0 │ │ eorseq sp, r9, r4, ror r2 │ │ stc2l 6, cr8, [r4, #856]! @ 0x358 │ │ - stc2l 7, cr14, [r2, #180]! @ 0xb4 │ │ + stc2l 7, cr14, [r2, #360]! @ 0x168 │ │ umaaleq ip, lr, ip, r4 │ │ - stc2l 12, cr6, [r2, #712]! @ 0x2c8 │ │ + stc2l 12, cr6, [r2, #892]! @ 0x37c │ │ ldr r0, [pc, #4076] @ 23f6768 │ │ movw r4, #5300 @ 0x14b4 │ │ ldr r3, [pc, #4072] @ 23f676c │ │ add r0, pc, r0 │ │ ldr r3, [pc, r3] │ │ str r3, [fp, #-36] @ 0xffffffdc │ │ cmp r3, r4 │ │ @@ -1225725,17 +1225725,17 @@ │ │ bhi 23f6220 │ │ ldr r0, [pc, #4048] @ 23f6828 │ │ str r1, [fp, #-36] @ 0xffffffdc │ │ add r0, pc, r0 │ │ str r4, [r0, r1, lsl #2] │ │ b 23f627c │ │ stc2l 6, cr8, [r4, #472]! @ 0x1d8 │ │ - stc2l 6, cr14, [r2, #820]! @ 0x334 │ │ + stc2l 6, cr14, [r2, #1000]! @ 0x3e8 │ │ subeq ip, lr, ip, lsr r4 │ │ - stc2l 12, cr2, [r3, #932]! @ 0x3a4 │ │ + stc2l 13, cr2, [r3, #88]! @ 0x58 │ │ mov r5, #1 │ │ mov r7, #0 │ │ cmp r9, #0 │ │ beq 23f58c8 │ │ ldr r1, [sp, #48] @ 0x30 │ │ movw r0, #5301 @ 0x14b5 │ │ str r8, [fp, #-36] @ 0xffffffdc │ │ @@ -1225753,36 +1225753,36 @@ │ │ add r0, pc, r0 │ │ add r0, r0, r8, lsl #2 │ │ bl 270d040 │ │ mov r4, #1 │ │ mov r6, #1 │ │ b 23f64d4 │ │ stc2l 6, cr8, [r4, #88]! @ 0x58 │ │ - stc2l 6, cr14, [r2, #436]! @ 0x1b4 │ │ + stc2l 6, cr14, [r2, #616]! @ 0x268 │ │ ldrdeq ip, [lr], #-60 @ 0xffffffc4 │ │ stc2l 1, cr14, [r4, #20]! │ │ stc2l 5, cr8, [r4, #712]! @ 0x2c8 │ │ - stc2l 6, cr14, [r2, #36]! @ 0x24 │ │ + stc2l 6, cr14, [r2, #216]! @ 0xd8 │ │ subeq ip, lr, r8, ror r3 │ │ stc2l 5, cr8, [r4, #576]! @ 0x240 │ │ stc2l 5, cr8, [r4, #328]! @ 0x148 │ │ - stc2l 5, cr14, [r2, #676]! @ 0x2a4 │ │ + stc2l 5, cr14, [r2, #856]! @ 0x358 │ │ subeq ip, lr, r8, lsl r3 │ │ stc2l 12, cr1, [r5, #344]! @ 0x158 │ │ stc2l 4, cr8, [r4, #952]! @ 0x3b8 │ │ - stc2l 5, cr14, [r2, #276]! @ 0x114 │ │ + stc2l 5, cr14, [r2, #456]! @ 0x1c8 │ │ strheq ip, [lr], #-36 @ 0xffffffdc │ │ - vcmla.f16 d22, d19, d16, #270 │ │ + vcmla.f16 q11, , , #270 │ │ stc2l 4, cr8, [r4, #568]! @ 0x238 │ │ - stc2l 4, cr14, [r2, #916]! @ 0x394 │ │ + stc2l 5, cr14, [r2, #72]! @ 0x48 │ │ subeq ip, lr, r4, asr r2 │ │ stc2l 5, cr11, [r5, #340]! @ 0x154 │ │ eorseq ip, r9, r0, ror pc │ │ - stc2l 8, cr6, [r2, #968]! @ 0x3c8 │ │ - stc2l 3, cr14, [r2, #900]! @ 0x384 │ │ + stc2l 9, cr6, [r2, #62]! @ 0x3e @ │ │ + stc2l 4, cr14, [r2, #56]! @ 0x38 │ │ eorseq r3, r5, r8, lsl #19 │ │ mov r1, r0 │ │ ldr r2, [fp, #-36] @ 0xffffffdc │ │ sub r0, r1, #1 │ │ str r0, [sp, #428] @ 0x1ac │ │ cmp r1, r2 │ │ ble 23f7768 │ │ @@ -1225901,24 +1225901,24 @@ │ │ ldr r0, [pc, #4012] @ 23f6ac0 │ │ ldr r0, [pc, r0] │ │ cmp r0, #1 │ │ blt 23f5cc4 │ │ mov r5, #1 │ │ mov r9, #0 │ │ b 23f5b8c │ │ - stc2l 7, cr6, [r3, #616]! @ 0x268 │ │ - stc2l 6, cr12, [r3, #108]! @ 0x6c │ │ - stc2l 7, cr4, [r3, #420]! @ 0x1a4 │ │ - stc2l 3, cr14, [r2, #756]! @ 0x2f4 │ │ + stc2l 7, cr6, [r3, #796]! @ 0x31c │ │ + stc2l 6, cr12, [r3, #288]! @ 0x120 │ │ + stc2l 7, cr4, [r3, #600]! @ 0x258 │ │ + stc2l 3, cr14, [r2, #936]! @ 0x3a8 │ │ eorseq ip, r9, ip, lsr #29 │ │ stc2l 3, cr8, [r4, #56]! @ 0x38 │ │ - stc2l 3, cr14, [r2, #404]! @ 0x194 │ │ + stc2l 3, cr14, [r2, #584]! @ 0x248 │ │ ldrdeq ip, [lr], #-8 │ │ vcmla.f16 , , q11, #270 │ │ - stc2l 3, cr14, [r2, #84]! @ 0x54 │ │ + stc2l 3, cr14, [r2, #264]! @ 0x108 │ │ subeq r6, pc, ip, lsr #12 │ │ ldr r1, [pc, #3944] @ 23f6ac4 │ │ add r0, r8, r6, lsl #3 │ │ mov r2, #8 │ │ mov r3, #4 │ │ add r1, pc, r1 │ │ bl 270d9d0 │ │ @@ -1225984,34 +1225984,34 @@ │ │ mov r1, r6 │ │ mov r2, sl │ │ movw r3, #3988 @ 0xf94 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r6, r0 │ │ b 23f5b54 │ │ - stc2l 15, cr15, [r3, #712]! @ 0x2c8 │ │ - stc2l 2, cr14, [r2, #852]! @ 0x354 │ │ + stc2l 15, cr15, [r3, #892]! @ 0x37c │ │ + stc2l 3, cr14, [r2, #8]! │ │ subeq r6, lr, ip, lsl sp │ │ - stc2l 15, cr15, [r3, #424]! @ 0x1a8 │ │ - stc2l 2, cr14, [r2, #564]! @ 0x234 │ │ - stc2l 6, cr4, [r3, #36]! @ 0x24 │ │ - stc2l 2, cr14, [r2, #372]! @ 0x174 │ │ + stc2l 15, cr15, [r3, #604]! @ 0x25c │ │ + stc2l 2, cr14, [r2, #744]! @ 0x2e8 │ │ + stc2l 6, cr4, [r3, #216]! @ 0xd8 │ │ + stc2l 2, cr14, [r2, #552]! @ 0x228 │ │ eorseq ip, r9, r0, lsr sp │ │ - stc2l 4, cr12, [r3, #108]! @ 0x6c │ │ - stc2l 14, cr15, [r3, #928]! @ 0x3a0 │ │ + stc2l 4, cr12, [r3, #288]! @ 0x120 │ │ + stc2l 15, cr15, [r3, #84]! @ 0x54 │ │ stc2l 1, cr8, [r4, #232]! @ 0xe8 │ │ - stc2l 1, cr14, [r2, #580]! @ 0x244 │ │ + stc2l 1, cr14, [r2, #760]! @ 0x2f8 │ │ subeq fp, lr, r0, lsl #30 │ │ - stc2l 4, cr6, [r3, #976]! @ 0x3d0 │ │ + stc2l 5, cr6, [r3, #132]! @ 0x84 │ │ stc2l 0, cr8, [r4, #888]! @ 0x378 │ │ - stc2l 1, cr14, [r2, #212]! @ 0xd4 │ │ - stc2l 6, cr6, [r2, #776]! @ 0x308 │ │ + stc2l 1, cr14, [r2, #392]! @ 0x188 │ │ + stc2l 6, cr6, [r2, #956]! @ 0x3bc │ │ stc2l 0, cr8, [r4, #536]! @ 0x218 │ │ - stc2l 0, cr14, [r2, #884]! @ 0x374 │ │ - stc2l 7, cr2, [r3, #4]! │ │ + stc2l 1, cr14, [r2, #40]! @ 0x28 │ │ + stc2l 7, cr2, [r3, #184]! @ 0xb8 │ │ mov r9, #0 │ │ sub r0, r9, #1 │ │ ldr r4, [pc, #3892] @ 23f6c08 │ │ clz r0, r0 │ │ add r4, pc, r4 │ │ lsr r9, r0, #5 │ │ ldr r0, [sp, #428] @ 0x1ac │ │ @@ -1226128,15 +1226128,15 @@ │ │ mov r1, r0 │ │ add r0, r7, r1, lsl #2 │ │ bl 270d850 │ │ ldr r4, [pc, #4084] @ 23f6ea0 │ │ add r4, pc, r4 │ │ b 23f6064 │ │ stc2l 0, cr8, [r4, #200]! @ 0xc8 │ │ - stc2l 0, cr14, [r2, #548]! @ 0x224 │ │ + stc2l 0, cr14, [r2, #728]! @ 0x2d8 │ │ stc2l 11, cr13, [r4, #164]! @ 0xa4 @ │ │ mov r0, #1 │ │ cmp r9, #0 │ │ str r0, [sp, #40] @ 0x28 │ │ beq 23f6064 │ │ ldr r0, [sp, #428] @ 0x1ac │ │ sub r1, r0, #1 │ │ @@ -1226150,15 +1226150,15 @@ │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ add r0, r7, r1, lsl #2 │ │ bl 270df30 │ │ b 23f6064 │ │ stc2l 15, cr7, [r4, #888]! @ 0x378 │ │ - stc2l 0, cr14, [r2, #212]! @ 0xd4 │ │ + stc2l 0, cr14, [r2, #392]! @ 0x188 │ │ cmp r9, #0 │ │ beq 23f5fd0 │ │ ldr r0, [sp, #428] @ 0x1ac │ │ sub r1, r0, #1 │ │ movw r0, #5300 @ 0x14b4 │ │ cmp r1, r0 │ │ str r1, [fp, #-40] @ 0xffffffd8 │ │ @@ -1226177,15 +1226177,15 @@ │ │ str r1, [fp, #-40] @ 0xffffffd8 │ │ bcs 23f603c │ │ mov r0, #1 │ │ str r0, [sp, #32] │ │ b 23f605c │ │ subeq r6, pc, ip, lsl #6 │ │ stc2l 5, cr5, [r5, #568]! @ 0x238 │ │ - stc2l 15, cr13, [r2, #756]! @ 0x2f4 │ │ + stc2l 15, cr13, [r2, #936]! @ 0x3a8 │ │ mov r0, #1 │ │ cmp r9, #0 │ │ str r0, [sp, #28] │ │ beq 23f6064 │ │ ldr r0, [sp, #428] @ 0x1ac │ │ sub r1, r0, #1 │ │ movw r0, #5300 @ 0x14b4 │ │ @@ -1226198,20 +1226198,20 @@ │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ add r0, r7, r1, lsl #2 │ │ bl 270df50 │ │ b 23f6064 │ │ stc2l 5, cr5, [r5, #360]! @ 0x168 │ │ - stc2l 15, cr13, [r2, #548]! @ 0x224 │ │ + stc2l 15, cr13, [r2, #728]! @ 0x2d8 │ │ mov r0, #1 │ │ str r0, [sp, #36] @ 0x24 │ │ b 23f6064 │ │ stc2l 14, cr7, [r4, #1000]! @ 0x3e8 │ │ - stc2l 15, cr13, [r2, #324]! @ 0x144 │ │ + stc2l 15, cr13, [r2, #504]! @ 0x1f8 │ │ mov r0, #1 │ │ mov r2, sl │ │ str r0, [sp, #36] @ 0x24 │ │ movw r3, #4017 @ 0xfb1 │ │ ldr r0, [pc, #4084] @ 23f6ff0 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ @@ -1226221,15 +1226221,15 @@ │ │ b 23f6064 │ │ mov r0, #1 │ │ str r0, [sp, #32] │ │ b 23f6064 │ │ subeq fp, lr, r4, asr #25 │ │ stc2l 15, cr10, [r5, #788]! @ 0x314 │ │ stc2l 14, cr7, [r4, #680]! @ 0x2a8 │ │ - stc2l 15, cr13, [r2, #4]! │ │ + stc2l 15, cr13, [r2, #184]! @ 0xb8 │ │ subeq fp, lr, r4, ror ip │ │ stc2l 14, cr7, [r4, #560]! @ 0x230 │ │ ldrhteq ip, [r9], -r4 │ │ subeq fp, lr, r4, lsl ip │ │ mov r0, #1 │ │ mov r2, sl │ │ str r0, [sp, #32] │ │ @@ -1226278,16 +1226278,16 @@ │ │ ldr r0, [pc, #3856] @ 23f7008 │ │ ldr r0, [pc, r0] │ │ str r0, [fp, #-40] @ 0xffffffd8 │ │ cmp r1, r0 │ │ bgt 23f61d0 │ │ sub r6, r1, #1 │ │ b 23f6130 │ │ - stc2l 1, cr4, [r3, #932]! @ 0x3a4 │ │ - stc2l 14, cr13, [r2, #244]! @ 0xf4 │ │ + stc2l 2, cr4, [r3, #88]! @ 0x58 │ │ + stc2l 14, cr13, [r2, #424]! @ 0x1a8 │ │ eorseq ip, r9, ip, lsr #18 │ │ sub r1, r5, #1 │ │ str r1, [r4, r0, lsl #2] │ │ ldr r0, [fp, #-40] @ 0xffffffd8 │ │ add r6, r6, #1 │ │ cmp r6, r0 │ │ bge 23f61cc │ │ @@ -1226298,15 +1226298,15 @@ │ │ ldr r5, [r4, r6, lsl #2] │ │ ldr r0, [sp, #428] @ 0x1ac │ │ cmp r5, r0 │ │ mov r0, r6 │ │ bgt 23f6118 │ │ b 23f6120 │ │ stc2l 13, cr7, [r4, #616]! @ 0x268 │ │ - stc2l 13, cr13, [r2, #964]! @ 0x3c4 │ │ + stc2l 14, cr13, [r2, #120]! @ 0x78 │ │ subeq fp, lr, r4, ror #22 │ │ ldrdeq r6, [pc], #-4 @ │ │ ldr r0, [pc, #3988] @ 23f7104 │ │ mov r1, r6 │ │ mov r2, sl │ │ movw r3, #4068 @ 0xfe4 │ │ add r0, pc, r0 │ │ @@ -1226329,32 +1226329,32 @@ │ │ movw r3, #4073 @ 0xfe9 │ │ str r6, [fp, #-44] @ 0xffffffd4 │ │ bl 270da30 │ │ b 23f6118 │ │ ldr r1, [sp, #428] @ 0x1ac │ │ ldr r9, [sp, #44] @ 0x2c │ │ b 23f5938 │ │ - stc2l 15, cr11, [r3, #476]! @ 0x1dc │ │ + stc2l 15, cr11, [r3, #656]! @ 0x290 │ │ str r0, [sp, #24] │ │ b 23f6064 │ │ stc2l 12, cr3, [r4, #344]! @ 0x158 │ │ - stc2l 15, cr11, [r3, #108]! @ 0x6c │ │ + stc2l 15, cr11, [r3, #288]! @ 0x120 │ │ stc2l 2, cr5, [r5, #728]! @ 0x2d8 │ │ - stc2l 12, cr13, [r2, #916]! @ 0x394 │ │ + stc2l 13, cr13, [r2, #72]! @ 0x48 │ │ strdeq r5, [pc], #-252 @ │ │ - stc2l 9, cr15, [r3, #260]! @ 0x104 @ │ │ - stc2l 12, cr13, [r2, #660]! @ 0x294 │ │ + stc2l 9, cr15, [r3, #350]! @ 0x15e @ │ │ + stc2l 12, cr13, [r2, #840]! @ 0x348 │ │ subeq r6, lr, ip, ror #13 │ │ - stc2l 9, cr15, [r3, #124]! @ 0x7c @ │ │ - stc2l 12, cr13, [r2, #388]! @ 0x184 │ │ - stc2l 15, cr3, [r3, #884]! @ 0x374 │ │ - stc2l 12, cr13, [r2, #196]! @ 0xc4 │ │ + stc2l 9, cr15, [r3, #214]! @ 0xd6 @ │ │ + stc2l 12, cr13, [r2, #568]! @ 0x238 │ │ + stc2l 0, cr4, [r3, #40]! @ 0x28 │ │ + stc2l 12, cr13, [r2, #376]! @ 0x178 │ │ stc2l 10, cr7, [r4, #936]! @ 0x3a8 @ │ │ - stc2l 11, cr13, [r2, #260]! @ 0x104 @ │ │ - stc2l 14, cr5, [r3, #656]! @ 0x290 │ │ + stc2l 11, cr13, [r2, #440]! @ 0x1b8 @ │ │ + stc2l 14, cr5, [r3, #836]! @ 0x344 │ │ ldr r0, [pc, #3960] @ 23f71a0 │ │ movw r3, #1471 @ 0x5bf │ │ ldr r2, [pc, #3956] @ 23f71a4 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #3944] @ 23f71a8 │ │ @@ -1226483,27 +1226483,27 @@ │ │ mov r1, #19 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #3784] @ 23f7300 │ │ add r0, pc, r0 │ │ b 23f6e30 │ │ stc2l 10, cr7, [r4, #568]! @ 0x238 @ │ │ - stc2l 10, cr13, [r2, #916]! @ 0x394 @ │ │ - stc2l 0, cr6, [r2, #472]! @ 0x1d8 │ │ + stc2l 11, cr13, [r2, #72]! @ 0x48 @ │ │ + stc2l 0, cr6, [r2, #652]! @ 0x28c │ │ stc2l 10, cr7, [r4, #216]! @ 0xd8 @ │ │ - stc2l 10, cr13, [r2, #564]! @ 0x234 @ │ │ - stc2l 0, cr2, [r3, #724]! @ 0x2d4 │ │ + stc2l 10, cr13, [r2, #744]! @ 0x2e8 @ │ │ + stc2l 0, cr2, [r3, #904]! @ 0x388 │ │ stc2l 9, cr7, [r4, #444]! @ 0x1bc @ │ │ - stc2l 10, cr13, [r2, #212]! @ 0xd4 @ │ │ + stc2l 10, cr13, [r2, #392]! @ 0x188 @ │ │ stc2l 0, cr1, [r5, #952]! @ 0x3b8 │ │ stc2l 9, cr7, [r4, #268]! @ 0x10c @ │ │ - stc2l 9, cr13, [r2, #442]! @ 0x1ba @ │ │ + stc2l 10, cr13, [r2, #40]! @ 0x28 @ │ │ stc2l 4, cr13, [r4, #516]! @ 0x204 │ │ stc2l 9, cr7, [r4, #92]! @ 0x5c @ │ │ - stc2l 9, cr13, [r2, #266]! @ 0x10a @ │ │ + stc2l 9, cr13, [r2, #356]! @ 0x164 @ │ │ stc2l 10, cr10, [r5, #4]! @ │ │ mov r6, #0 │ │ mov r7, #1 │ │ cmp r9, #0 │ │ beq 23f64cc │ │ ldr r1, [sp, #48] @ 0x30 │ │ movw r0, #5301 @ 0x14b5 │ │ @@ -1226597,22 +1226597,22 @@ │ │ add r7, pc, r7 │ │ ldr r8, [pc, #4052] @ 23f75cc │ │ add r9, pc, r9 │ │ add sl, pc, sl │ │ add r8, pc, r8 │ │ b 23f6658 │ │ stc2l 8, cr7, [r4, #888]! @ 0x378 │ │ - stc2l 9, cr13, [r2, #106]! @ 0x6a @ │ │ + stc2l 9, cr13, [r2, #196]! @ 0xc4 @ │ │ vcmla.f16 , q10, q2, #270 │ │ eorseq ip, r9, ip, ror #7 │ │ strdeq r6, [lr], #-40 @ 0xffffffd8 │ │ subeq r5, pc, r4, asr #23 │ │ - stc2l 8, cr13, [r2, #596]! @ 0x254 │ │ + vcmla.f16 , q9, q1, #270 │ │ stc2l 14, cr4, [r5, #8]! │ │ - stc2l 8, cr13, [r2, #196]! @ 0xc4 │ │ + stc2l 8, cr13, [r2, #376]! @ 0x178 │ │ subeq r5, pc, r8, asr #22 │ │ ldr r0, [pc, #4084] @ 23f7628 │ │ add r1, sp, #416 @ 0x1a0 │ │ mov r2, #6 │ │ add r0, pc, r0 │ │ bl 270df10 │ │ ldr r1, [fp, #-68] @ 0xffffffbc │ │ @@ -1226687,16 +1226687,16 @@ │ │ cmp r0, #0 │ │ bne 23f6640 │ │ mov r0, #1 │ │ str r0, [sp, #428] @ 0x1ac │ │ b 23f6798 │ │ eorseq ip, r9, r8, ror #5 │ │ eorseq ip, r9, r4, ror #5 │ │ - stc2l 11, cr3, [r3, #356]! @ 0x164 @ │ │ - stc2l 7, cr13, [r2, #692]! @ 0x2b4 │ │ + stc2l 11, cr3, [r3, #536]! @ 0x218 @ │ │ + stc2l 7, cr13, [r2, #872]! @ 0x368 │ │ add r0, r7, r1, lsl #5 │ │ mov r1, #32 │ │ bl 270dfd0 │ │ ldr r1, [sp, #428] @ 0x1ac │ │ add r0, r1, #1 │ │ cmp r1, #3 │ │ str r0, [sp, #428] @ 0x1ac │ │ @@ -1226710,15 +1226710,15 @@ │ │ movw r3, #4135 @ 0x1027 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 23f6778 │ │ mlaseq r9, ip, r2, ip │ │ eorseq ip, r9, r4, lsl #5 │ │ stc2l 7, cr7, [r4, #8]! │ │ - stc2l 7, cr13, [r2, #356]! @ 0x164 │ │ + stc2l 7, cr13, [r2, #536]! @ 0x218 │ │ subeq fp, lr, r8, asr #9 │ │ ldr r0, [sp, #44] @ 0x2c │ │ cmp r0, #0 │ │ bne 23f6918 │ │ ldr r0, [pc, #4040] @ 23f77b0 │ │ mov r1, #1 │ │ ldr r0, [pc, r0] │ │ @@ -1226735,15 +1226735,15 @@ │ │ add r7, pc, r7 │ │ movw r8, #5299 @ 0x14b3 │ │ add sl, pc, sl │ │ b 23f687c │ │ eorseq ip, r9, r0, lsr r2 │ │ subeq r5, pc, r0, lsr sl @ │ │ stc2l 12, cr4, [r5, #536]! @ 0x218 │ │ - stc2l 6, cr13, [r2, #724]! @ 0x2d4 │ │ + stc2l 6, cr13, [r2, #904]! @ 0x388 │ │ subeq r5, pc, ip, asr #19 │ │ str r4, [fp, #-44] @ 0xffffffd4 │ │ mov r1, r4 │ │ ldr r2, [pc, #4084] @ 23f783c │ │ rsb r0, r4, r4, lsl #8 │ │ add r2, pc, r2 │ │ add r0, r2, r0 │ │ @@ -1226792,15 +1226792,15 @@ │ │ ldr r0, [pc, #4032] @ 23f78c0 │ │ mov r2, r7 │ │ movw r3, #4156 @ 0x103c │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 23f6840 │ │ - stc2l 2, cr15, [r3, #824]! @ 0x338 │ │ + stc2l 2, cr15, [r3, #1004]! @ 0x3ec │ │ ldr r0, [sp, #36] @ 0x24 │ │ ldr r5, [sp, #48] @ 0x30 │ │ cmp r0, #0 │ │ bne 23f6a64 │ │ ldr r0, [pc, #4060] @ 23f790c │ │ mov r1, #1 │ │ ldr r0, [pc, r0] │ │ @@ -1226816,17 +1226816,17 @@ │ │ add r6, pc, r6 │ │ ldr sl, [pc, #4024] @ 23f791c │ │ add r9, pc, r9 │ │ add r7, pc, r7 │ │ add sl, pc, sl │ │ b 23f69c4 │ │ stc2l 5, cr7, [r4, #360]! @ 0x168 │ │ - stc2l 9, cr5, [r3, #48]! @ 0x30 @ │ │ + stc2l 9, cr5, [r3, #138]! @ 0x8a @ │ │ stc2l 5, cr7, [r4, #40]! @ 0x28 │ │ - stc2l 10, cr5, [r2, #968]! @ 0x3c8 @ │ │ + stc2l 11, cr5, [r2, #124]! @ 0x7c @ │ │ stc2l 4, cr7, [r4, #760]! @ 0x2f8 │ │ mov r1, r4 │ │ ldr r2, [pc, #4088] @ 23f7988 │ │ rsb r0, r4, r4, lsl #8 │ │ add r2, pc, r2 │ │ add r0, r2, r0 │ │ ldr r2, [pc, #4076] @ 23f798c │ │ @@ -1226873,15 +1226873,15 @@ │ │ ldr r0, [pc, #3920] @ 23f7994 │ │ mov r2, r7 │ │ movw r3, #4170 @ 0x104a │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 23f6988 │ │ - stc2l 11, cr1, [r3, #244]! @ 0xf4 @ │ │ + stc2l 11, cr1, [r3, #424]! @ 0x1a8 @ │ │ stc2l 4, cr7, [r4, #456]! @ 0x1c8 │ │ stc2l 15, cr12, [r4, #436]! @ 0x1b4 │ │ ldr r0, [sp, #32] │ │ cmp r0, #0 │ │ bne 23f6ba8 │ │ ldr r0, [pc, #3872] @ 23f7998 │ │ mov r1, #1 │ │ @@ -1227036,15 +1227036,15 @@ │ │ mov r2, r7 │ │ movw r3, #4200 @ 0x1068 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 23f6c10 │ │ stc2l 2, cr7, [r4, #40]! @ 0x28 │ │ - stc2l 5, cr5, [r3, #800]! @ 0x320 │ │ + stc2l 5, cr5, [r3, #980]! @ 0x3d4 │ │ cmp r5, #0 │ │ ldr r5, [pc, #3576] @ 23f7aec │ │ add r5, pc, r5 │ │ bne 23f6e28 │ │ ldr r0, [pc, #3568] @ 23f7af0 │ │ mov r1, #1 │ │ ldr r0, [pc, r0] │ │ @@ -1227060,17 +1227060,17 @@ │ │ add r6, pc, r6 │ │ ldr sl, [pc, #3532] @ 23f7b00 │ │ add r9, pc, r9 │ │ add r7, pc, r7 │ │ add sl, pc, sl │ │ b 23f6d98 │ │ stc2l 1, cr7, [r4, #744]! @ 0x2e8 │ │ - stc2l 7, cr5, [r2, #648]! @ 0x288 │ │ + stc2l 7, cr5, [r2, #828]! @ 0x33c │ │ stc2l 1, cr7, [r4, #440]! @ 0x1b8 │ │ - stc2l 7, cr1, [r3, #948]! @ 0x3b4 │ │ + stc2l 8, cr1, [r3, #104]! @ 0x68 │ │ stc2l 1, cr7, [r4, #136]! @ 0x88 │ │ stc2l 8, cr0, [r5, #200]! @ 0xc8 │ │ mov r1, r4 │ │ ldr r2, [pc, #3492] @ 23f7b08 │ │ rsb r0, r4, r4, lsl #8 │ │ add r2, pc, r2 │ │ add r0, r2, r0 │ │ @@ -1227300,16 +1227300,16 @@ │ │ mov r3, #255 @ 0xff │ │ add r1, pc, r1 │ │ bl 270e020 │ │ cmp r0, #1 │ │ blt 23f7320 │ │ mov sl, r0 │ │ b 23f7170 │ │ - stc2l 10, cr14, [r3, #776]! @ 0x308 @ │ │ - stc2l 10, cr14, [r3, #616]! @ 0x268 @ │ │ + stc2l 10, cr14, [r3, #956]! @ 0x3bc @ │ │ + stc2l 10, cr14, [r3, #796]! @ 0x31c @ │ │ ldr r2, [fp, #-64] @ 0xffffffc0 │ │ sub r0, fp, #340 @ 0x154 │ │ str r3, [sp, #8] │ │ mov r3, r5 │ │ add r1, r2, r1 │ │ str r1, [fp, #-36] @ 0xffffffdc │ │ sub r1, fp, #64 @ 0x40 │ │ @@ -1227340,15 +1227340,15 @@ │ │ str r1, [fp, #-60] @ 0xffffffc4 │ │ mov r1, #1 │ │ str sl, [fp, #-64] @ 0xffffffc0 │ │ str r0, [fp, #-36] @ 0xffffffdc │ │ bge 23f71fc │ │ b 23f713c │ │ stc2l 3, cr4, [r5, #8]! │ │ - stc2l 13, cr12, [r2, #196]! @ 0xc4 │ │ + stc2l 13, cr12, [r2, #376]! @ 0x178 │ │ subeq r5, pc, ip, asr #32 │ │ eorseq fp, r9, r0, lsr #16 │ │ sub r0, fp, #40 @ 0x28 │ │ str r0, [sp] │ │ sub r0, fp, #44 @ 0x2c │ │ sub r2, fp, #76 @ 0x4c │ │ sub r3, fp, #340 @ 0x154 │ │ @@ -1227388,19 +1227388,19 @@ │ │ add r3, r1, #1 │ │ add r1, r1, r0 │ │ str r3, [fp, #-40] @ 0xffffffd8 │ │ str r1, [fp, #-44] @ 0xffffffd4 │ │ bgt 23f71b0 │ │ ldr r1, [fp, #-68] @ 0xffffffbc │ │ b 23f71e8 │ │ - stc2l 9, cr14, [r3, #412]! @ 0x19c @ │ │ - stc2l 12, cr12, [r2, #964]! @ 0x3c4 │ │ + stc2l 9, cr14, [r3, #502]! @ 0x1f6 @ │ │ + stc2l 13, cr12, [r2, #120]! @ 0x78 │ │ subeq r5, lr, r0, lsr r7 │ │ - stc2l 14, cr10, [r3, #828]! @ 0x33c │ │ - stc2l 2, cr1, [r3, #348]! @ 0x15c │ │ + stc2l 14, cr10, [r3, #1008]! @ 0x3f0 │ │ + stc2l 2, cr1, [r3, #528]! @ 0x210 │ │ ldr r0, [sp, #52] @ 0x34 │ │ mov r1, #1 │ │ cmp r0, #1 │ │ blt 23f713c │ │ add r0, sp, #56 @ 0x38 │ │ str r0, [sp, #4] │ │ mov r0, #11 │ │ @@ -1227419,25 +1227419,25 @@ │ │ ldr r3, [fp, #-72] @ 0xffffffb8 │ │ ldr r1, [fp, #-60] @ 0xffffffc4 │ │ add r2, r3, r2 │ │ sub r2, r1, r2 │ │ cmn r2, #256 @ 0x100 │ │ bge 23f710c │ │ b 23f76ec │ │ - stc2l 7, cr0, [r4, #780]! @ 0x30c │ │ + stc2l 7, cr0, [r4, #960]! @ 0x3c0 │ │ stc2l 3, cr3, [r2, #644]! @ 0x284 │ │ - stc2l 7, cr0, [r4, #460]! @ 0x1cc │ │ + stc2l 7, cr0, [r4, #640]! @ 0x280 │ │ stc2l 3, cr3, [r2, #340]! @ 0x154 │ │ subeq sl, lr, r8, lsl #18 │ │ - stc2l 0, cr9, [r2, #168]! @ 0xa8 │ │ - stc2l 10, cr12, [r2, #1012]! @ 0x3f4 @ │ │ + stc2l 0, cr9, [r2, #348]! @ 0x15c │ │ + stc2l 11, cr12, [r2, #168]! @ 0xa8 @ │ │ stc2l 4, cr6, [r5, #780]! @ 0x30c │ │ - stc2l 13, cr10, [r3, #156]! @ 0x9c │ │ + stc2l 13, cr10, [r3, #336]! @ 0x150 │ │ stc2l 0, cr4, [r5, #520]! @ 0x208 │ │ - stc2l 10, cr12, [r2, #708]! @ 0x2c4 @ │ │ + stc2l 10, cr12, [r2, #888]! @ 0x378 @ │ │ subeq r4, pc, r8, asr #27 │ │ eorseq r1, r5, r8, lsr #31 │ │ eorseq fp, r9, r0, ror #10 │ │ eorseq fp, r9, r8, asr r5 │ │ subeq sl, lr, r8, lsr #15 │ │ ldr r1, [pc, #1760] @ 23f7a08 │ │ add r5, sp, #428 @ 0x1ac │ │ @@ -1227604,16 +1227604,16 @@ │ │ add r0, r0, r8, lsl #2 │ │ bl 270df50 │ │ mov r5, #1 │ │ b 23f58cc │ │ eorseq fp, r9, ip, lsr #9 │ │ stc2l 9, cr6, [r4, #80]! @ 0x50 @ │ │ umaaleq sl, lr, ip, r6 │ │ - stc2l 7, cr12, [r2, #368]! @ 0x170 │ │ - stc2l 9, cr12, [r2, #210]! @ 0xd2 @ │ │ + stc2l 7, cr12, [r2, #548]! @ 0x224 │ │ + stc2l 9, cr12, [r2, #300]! @ 0x12c @ │ │ stc2l 9, cr6, [r4, #20]! @ │ │ mov r5, #0 │ │ mov r7, #1 │ │ cmp r9, #0 │ │ beq 23f58c8 │ │ ldr r1, [sp, #48] @ 0x30 │ │ movw r0, #5301 @ 0x14b5 │ │ @@ -1227629,15 +1227629,15 @@ │ │ bl 270da30 │ │ mov r8, r0 │ │ ldr r0, [pc, #1168] @ 23f7aac │ │ add r0, pc, r0 │ │ add r0, r0, r8, lsl #2 │ │ bl 270d850 │ │ b 23f58c8 │ │ - stc2l 11, cr10, [r3, #140]! @ 0x8c @ │ │ + stc2l 11, cr10, [r3, #320]! @ 0x140 @ │ │ mov r2, #1 │ │ str r2, [fp, #-68] @ 0xffffffbc │ │ ldr r5, [pc, #1100] @ 23f7a88 │ │ ldr r4, [pc, #1100] @ 23f7a8c │ │ ldr r6, [pc, #1100] @ 23f7a90 │ │ add r5, pc, r5 │ │ add r4, pc, r4 │ │ @@ -1227676,15 +1227676,15 @@ │ │ mov r7, #1 │ │ mov r5, #1 │ │ mov r4, #1 │ │ mov r6, #1 │ │ b 23f64dc │ │ mov r5, #1 │ │ b 23f58cc │ │ - stc2l 12, cr2, [r3, #84]! @ 0x54 │ │ + stc2l 12, cr2, [r3, #264]! @ 0x108 │ │ eorseq fp, r9, r4, ror #6 │ │ ldr r0, [pc, #776] @ 23f79fc │ │ mov r1, #205 @ 0xcd │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #764] @ 23f7a00 │ │ mov r2, #1 │ │ @@ -1227728,16 +1227728,16 @@ │ │ clz r0, r0 │ │ lsr r7, r0, #5 │ │ ldr r0, [sp, #40] @ 0x28 │ │ clz r0, r0 │ │ lsr r0, r0, #5 │ │ b 23f64dc │ │ eorseq fp, r9, r0, lsl #5 │ │ - stc2l 10, cr4, [r3, #832]! @ 0x340 @ │ │ - stc2l 7, cr12, [r2, #308]! @ 0x134 │ │ + stc2l 10, cr4, [r3, #1012]! @ 0x3f4 @ │ │ + stc2l 7, cr12, [r2, #488]! @ 0x1e8 │ │ stc2l 6, cr6, [r4, #936]! @ 0x3a8 │ │ ldr r0, [pc, #484] @ 23f79ac │ │ mov r1, #115 @ 0x73 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #472] @ 23f79b0 │ │ mov r2, #1 │ │ @@ -1227794,15 +1227794,15 @@ │ │ ldr r6, [pc, #376] @ 23f7a20 │ │ ldr r4, [pc, #376] @ 23f7a24 │ │ ldr r7, [pc, #376] @ 23f7a28 │ │ add r6, pc, r6 │ │ add r4, pc, r4 │ │ add r7, pc, r7 │ │ b 23f78e4 │ │ - stc2l 10, cr2, [r3, #196]! @ 0xc4 @ │ │ + stc2l 10, cr2, [r3, #376]! @ 0x178 @ │ │ stc2l 12, cr3, [r5, #168]! @ 0xa8 │ │ add r0, r6, r1, lsl #5 │ │ mov r1, #32 │ │ bl 270dfd0 │ │ ldr r1, [fp, #-68] @ 0xffffffbc │ │ add r0, r1, #1 │ │ cmp r1, #3 │ │ @@ -1227815,17 +1227815,17 @@ │ │ mov r0, r4 │ │ mov r2, r7 │ │ movw r3, #1722 @ 0x6ba │ │ bl 270da30 │ │ mov r1, r0 │ │ b 23f78c4 │ │ eorseq fp, r9, r8, lsr r1 │ │ - stc2l 11, cr4, [r2, #712]! @ 0x2c8 @ │ │ - stc2l 9, cr2, [r3, #338]! @ 0x152 @ │ │ - stc2l 5, cr12, [r2, #1012]! @ 0x3f4 │ │ + stc2l 11, cr4, [r2, #892]! @ 0x37c @ │ │ + stc2l 9, cr2, [r3, #428]! @ 0x1ac @ │ │ + stc2l 6, cr12, [r2, #168]! @ 0xa8 │ │ stc2l 5, cr6, [r4, #632]! @ 0x278 │ │ ldr r4, [pc, #260] @ 23f7a2c │ │ add r1, sp, #416 @ 0x1a0 │ │ mov r2, #6 │ │ add r4, pc, r4 │ │ mov r0, r4 │ │ bl 270df10 │ │ @@ -1227850,108 +1227850,108 @@ │ │ add r0, pc, r0 │ │ b 23f41f4 │ │ ldrsbteq fp, [r9], -ip │ │ subeq r4, pc, ip, ror #17 │ │ strdeq sl, [lr], #-44 @ 0xffffffd4 │ │ stc2l 10, cr3, [r5, #920]! @ 0x398 @ │ │ ldrshteq sl, [r9], -r0 │ │ - stc2l 11, cr0, [r3, #4]! @ │ │ - vcmla.f16 q9, , , #270 │ │ - stc2l 4, cr12, [r2, #724]! @ 0x2d4 │ │ + stc2l 11, cr0, [r3, #184]! @ 0xb8 @ │ │ + vcmla.f16 d18, d19, d14, #270 │ │ + stc2l 4, cr12, [r2, #904]! @ 0x388 │ │ stc2l 4, cr6, [r4, #344]! @ 0x158 │ │ stc2l 0, cr5, [r5, #700]! @ 0x2bc │ │ - stc2l 7, cr11, [r2, #148]! @ 0x94 │ │ + stc2l 7, cr11, [r2, #328]! @ 0x148 │ │ mlaseq r5, r0, ip, r0 │ │ - stc2l 12, cr13, [r2, #432]! @ 0x1b0 │ │ - stc2l 9, cr9, [r3, #78]! @ 0x4e @ │ │ + stc2l 12, cr13, [r2, #612]! @ 0x264 │ │ + stc2l 9, cr9, [r3, #168]! @ 0xa8 @ │ │ eorseq sl, r9, r4, lsr fp │ │ stc2l 15, cr5, [r4, #680]! @ 0x2a8 │ │ - stc2l 0, cr12, [r2, #4]! │ │ + stc2l 0, cr12, [r2, #184]! @ 0xb8 │ │ stc2l 15, cr5, [r4, #576]! @ 0x240 │ │ - stc2l 1, cr6, [r2, #40]! @ 0x28 │ │ + stc2l 1, cr6, [r2, #220]! @ 0xdc │ │ stc2l 7, cr2, [r2, #68]! @ 0x44 │ │ eorseq r1, r5, r8, asr #9 │ │ - stc2l 12, cr15, [r2, #864]! @ 0x360 │ │ - stc2l 6, cr11, [r2, #644]! @ 0x284 │ │ + stc2l 13, cr15, [r2, #20]! │ │ + stc2l 6, cr11, [r2, #824]! @ 0x338 │ │ ldrhteq sl, [r9], -r0 │ │ - stc2l 8, cr5, [r2, #120]! @ 0x78 │ │ - stc2l 2, cr6, [r3, #528]! @ 0x210 │ │ - stc2l 2, cr0, [r3, #972]! @ 0x3cc │ │ - stc2l 8, cr15, [r3, #76]! @ 0x4c │ │ + vcmla.f16 , q1, , #270 │ │ + stc2l 2, cr6, [r3, #708]! @ 0x2c4 │ │ + stc2l 3, cr0, [r3, #128]! @ 0x80 │ │ + vcmla.f16 , , q0, #270 │ │ stc2l 3, cr2, [r2, #980]! @ 0x3d4 │ │ stc2l 14, cr14, [r4, #448]! @ 0x1c0 │ │ - stc2l 7, cr11, [r2, #996]! @ 0x3e4 │ │ - stc2l 2, cr6, [r3, #80]! @ 0x50 │ │ + vcmla.f16 d27, d2, d22, #270 │ │ + stc2l 2, cr6, [r3, #260]! @ 0x104 │ │ stc2l 4, cr13, [r4, #636]! @ 0x27c │ │ - stc2l 0, cr8, [r3, #72]! @ 0x48 │ │ - stc2l 3, cr5, [r3, #940]! @ 0x3ac │ │ - stc2l 15, cr7, [r3, #904]! @ 0x388 │ │ + stc2l 0, cr8, [r3, #252]! @ 0xfc │ │ + stc2l 4, cr5, [r3, #96]! @ 0x60 │ │ + stc2l 0, cr8, [r3, #60]! @ 0x3c │ │ stc2l 12, cr8, [r5, #84]! @ 0x54 │ │ - stc2l 13, cr9, [r3, #380]! @ 0x17c │ │ + stc2l 13, cr9, [r3, #560]! @ 0x230 │ │ ldrdeq r9, [lr], #-60 @ 0xffffffc4 │ │ - stc2l 4, cr11, [r2, #640]! @ 0x280 │ │ - stc2l 6, cr11, [r2, #692]! @ 0x2b4 │ │ - vcmla.f16 d25, d3, d31, #270 │ │ + stc2l 4, cr11, [r2, #820]! @ 0x334 │ │ + stc2l 6, cr11, [r2, #872]! @ 0x368 │ │ + stc2l 8, cr9, [r3, #368]! @ 0x170 │ │ stc2l 13, cr1, [r2, #444]! @ 0x1bc │ │ - stc2l 5, cr11, [r2, #692]! @ 0x2b4 │ │ - stc2l 11, cr3, [r2, #456]! @ 0x1c8 @ │ │ + stc2l 5, cr11, [r2, #872]! @ 0x368 │ │ + stc2l 11, cr3, [r2, #636]! @ 0x27c @ │ │ eorseq sl, r9, r4, asr r6 │ │ eorseq sl, r9, r4, asr #12 │ │ strheq r9, [lr], #-128 @ 0xffffff80 │ │ - stc2l 14, cr1, [r3, #756]! @ 0x2f4 │ │ - stc2l 11, cr11, [r2, #68]! @ 0x44 @ │ │ + stc2l 14, cr1, [r3, #936]! @ 0x3a8 │ │ + stc2l 11, cr11, [r2, #248]! @ 0xf8 @ │ │ eorseq sl, r9, r0, lsl #12 │ │ eorseq sl, r9, r8, ror #11 │ │ stc2l 10, cr5, [r4, #392]! @ 0x188 @ │ │ - stc2l 10, cr11, [r2, #740]! @ 0x2e4 @ │ │ + stc2l 10, cr11, [r2, #920]! @ 0x398 @ │ │ mlaseq r9, r8, r5, sl │ │ subeq r4, pc, r4, ror r2 @ │ │ stc2l 0, cr3, [r5, #232]! @ 0xe8 │ │ - stc2l 10, cr11, [r2, #420]! @ 0x1a4 @ │ │ + stc2l 10, cr11, [r2, #600]! @ 0x258 @ │ │ subeq r3, pc, r0, lsl #27 │ │ eorseq sl, r9, r4, asr r5 │ │ - stc2l 7, cr13, [r3, #8]! │ │ + stc2l 7, cr13, [r3, #188]! @ 0xbc │ │ subeq r4, lr, r0, ror r9 │ │ - stc2l 0, cr6, [r2, #120]! @ 0x78 │ │ + stc2l 0, cr6, [r2, #300]! @ 0x12c │ │ stc2l 6, cr2, [r2, #164]! @ 0xa4 │ │ subeq r9, lr, r8, asr #12 │ │ - stc2l 7, cr11, [r2, #48]! @ 0x30 │ │ - stc2l 9, cr11, [r2, #50]! @ 0x32 @ │ │ - stc2l 10, cr9, [r3, #716]! @ 0x2cc @ │ │ + stc2l 7, cr11, [r2, #228]! @ 0xe4 │ │ + stc2l 9, cr11, [r2, #140]! @ 0x8c @ │ │ + stc2l 10, cr9, [r3, #896]! @ 0x380 @ │ │ stc2l 15, cr2, [r5, #632]! @ 0x278 │ │ - stc2l 9, cr11, [r2, #410]! @ 0x19a @ │ │ + stc2l 9, cr11, [r2, #500]! @ 0x1f4 @ │ │ subeq r3, pc, r4, ror #25 │ │ stc2l 15, cr2, [r5, #168]! @ 0xa8 │ │ - stc2l 9, cr11, [r2, #178]! @ 0xb2 @ │ │ + stc2l 9, cr11, [r2, #268]! @ 0x10c @ │ │ subeq r3, pc, r0, ror ip @ │ │ - stc2l 13, cr13, [r3, #904]! @ 0x388 │ │ - stc2l 1, cr12, [r2, #20]! │ │ + stc2l 14, cr13, [r3, #60]! @ 0x3c │ │ + stc2l 1, cr12, [r2, #200]! @ 0xc8 │ │ strheq sl, [lr], #-20 @ 0xffffffec │ │ stc2l 9, cr3, [r5, #316]! @ 0x13c @ │ │ mlaseq r9, r4, pc, sl @ │ │ subeq r4, pc, r4, lsr #15 │ │ eorseq sl, r9, ip, lsr #29 │ │ stc2l 10, cr15, [r4, #312]! @ 0x138 @ │ │ - stc2l 7, cr2, [r3, #116]! @ 0x74 │ │ - stc2l 3, cr12, [r2, #452]! @ 0x1c4 │ │ + stc2l 7, cr2, [r3, #296]! @ 0x128 │ │ + stc2l 3, cr12, [r2, #632]! @ 0x278 │ │ stc2l 3, cr6, [r4, #72]! @ 0x48 │ │ subeq sl, lr, r4, ror r0 │ │ stc2l 8, cr3, [r5, #376]! @ 0x178 │ │ eorseq sl, r9, r4, asr lr │ │ subeq r4, pc, r4, ror #12 │ │ strdeq r9, [lr], #-248 @ 0xffffff08 │ │ eorseq sl, r9, r8, ror #26 │ │ stc2l 12, cr11, [r4, #980]! @ 0x3d4 │ │ - stc2l 5, cr2, [r3, #868]! @ 0x364 │ │ - stc2l 2, cr12, [r2, #180]! @ 0xb4 │ │ + stc2l 6, cr2, [r3, #24]! │ │ + stc2l 2, cr12, [r2, #360]! @ 0x168 │ │ stc2l 1, cr6, [r4, #824]! @ 0x338 │ │ stc2l 7, cr3, [r5, #104]! @ 0x68 │ │ eorseq sl, r9, r8, lsl #26 │ │ subeq r4, pc, r8, lsl r5 @ │ │ - stc2l 6, cr8, [r2, #232]! @ 0xe8 │ │ + stc2l 6, cr8, [r2, #412]! @ 0x19c │ │ │ │ 023f7b14 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ ldr r4, [pc, #64] @ 23f7b64 │ │ mov r1, #6 │ │ add r4, pc, r4 │ │ @@ -1229355,15 +1229355,15 @@ │ │ ldr r1, [pc, #3336] @ 23f9dd4 │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ b 23f831c │ │ ldr r1, [pc, #3324] @ 23f9dd8 │ │ ldr r1, [pc, r1] │ │ b 23f9124 │ │ - stc2l 4, cr3, [r2, #148]! @ 0x94 │ │ + stc2l 4, cr3, [r2, #328]! @ 0x148 │ │ ldrhteq r0, [r5], -r4 │ │ stc2l 5, cr14, [r4, #200]! @ 0xc8 │ │ subeq r8, pc, r8, asr #8 │ │ subseq r0, r1, r8, lsl #22 │ │ sbcseq r5, sl, ip, asr pc │ │ strdeq r8, [pc], #-56 @ │ │ subseq r0, r1, ip, asr #21 │ │ @@ -1229435,18 +1229435,18 @@ │ │ mov r3, #12 │ │ bl 270d9e0 │ │ mov r0, #0 │ │ str r0, [sp, #4] │ │ b 23f8320 │ │ stc2l 3, cr2, [r5, #4]! │ │ stc2l 2, cr2, [r5, #836]! @ 0x344 │ │ - stc2l 8, cr14, [r3, #252]! @ 0xfc │ │ - stc2l 8, cr14, [r3, #92]! @ 0x5c │ │ - stc2l 0, cr5, [r3, #584]! @ 0x248 │ │ - stc2l 2, cr15, [r2, #708]! @ 0x2c4 │ │ + vcmla.f16 q15, , q14, #270 │ │ + vcmla.f16 q15, , q2, #270 │ │ + stc2l 0, cr5, [r3, #764]! @ 0x2fc │ │ + stc2l 2, cr15, [r2, #888]! @ 0x378 │ │ eorseq r0, r5, r8, lsr #3 │ │ stc2l 11, cr10, [r1, #384]! @ 0x180 @ │ │ ldr r0, [pc, #4068] @ 23fa224 │ │ add r0, pc, r0 │ │ bl 270d340 │ │ bl 270db90 │ │ cmp r0, #0 │ │ @@ -1229503,15 +1229503,15 @@ │ │ add r0, r0, #1 │ │ str r0, [sp, #4] │ │ b 23f8320 │ │ eorseq r0, r5, r4, lsl #3 │ │ stc2l 2, cr2, [r5, #44]! @ 0x2c │ │ eorseq r0, r5, r0, ror r1 │ │ stc2l 7, cr0, [r2, #1016]! @ 0x3f8 │ │ - vcmla.f16 q14, , , #270 │ │ + stc2l 9, cr12, [r3, #40]! @ 0x28 @ │ │ ldr r0, [pc, #3852] @ 23fa248 │ │ mov r2, #40 @ 0x28 │ │ ldr r1, [pc, #3848] @ 23fa24c │ │ mov r3, #1 │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ bl 270d9e0 │ │ @@ -1229524,18 +1229524,18 @@ │ │ str r1, [fp, #-56] @ 0xffffffc8 │ │ add r2, pc, r2 │ │ ldr r4, [r2, r1, lsl #2] │ │ b 23f9b08 │ │ stc2l 10, cr10, [r1, #848]! @ 0x350 @ │ │ stc2l 4, cr1, [r2, #200]! @ 0xc8 │ │ stc2l 6, cr10, [r4, #272]! @ 0x110 │ │ - stc2l 15, cr6, [r3, #524]! @ 0x20c │ │ + stc2l 15, cr6, [r3, #704]! @ 0x2c0 │ │ stc2l 3, cr12, [r4, #1008]! @ 0x3f0 │ │ - stc2l 8, cr12, [r3, #216]! @ 0xd8 │ │ - stc2l 12, cr4, [r2, #868]! @ 0x364 │ │ + vcmla.f16 q14, , , #270 │ │ + stc2l 13, cr4, [r2, #24]! │ │ ldr r0, [pc, #4032] @ 23fa35c │ │ mov r2, sl │ │ movw r3, #3023 @ 0xbcf │ │ add r0, pc, r0 │ │ bl 270da30 │ │ ldr r1, [pc, #4016] @ 23fa360 │ │ add r1, pc, r1 │ │ @@ -1229583,25 +1229583,25 @@ │ │ bl 270da30 │ │ ldr r2, [pc, #3960] @ 23fa3d8 │ │ mov r1, r0 │ │ ldr r2, [pc, r2] │ │ b 23f8ff4 │ │ stc2l 5, cr10, [r4, #696]! @ 0x2b8 │ │ stc2l 5, cr10, [r4, #612]! @ 0x264 │ │ - stc2l 12, cr8, [r3, #664]! @ 0x298 │ │ - stc2l 10, cr10, [r2, #564]! @ 0x234 @ │ │ + stc2l 12, cr8, [r3, #844]! @ 0x34c │ │ + stc2l 10, cr10, [r2, #744]! @ 0x2e8 @ │ │ stc2l 10, cr6, [r4, #908]! @ 0x38c @ │ │ - stc2l 15, cr2, [r2, #988]! @ 0x3dc │ │ + stc2l 0, cr3, [r2, #144]! @ 0x90 │ │ smlaleq r9, r6, r0, r0 │ │ stc2l 10, cr2, [r4, #252]! @ 0xfc @ │ │ eorseq pc, r4, r0, asr #30 │ │ rsceq r9, r6, r0, asr #32 │ │ rsceq r9, r6, r4, lsr r0 │ │ addseq pc, r5, r4, ror #29 │ │ - stc2l 14, cr12, [r2, #964]! @ 0x3c4 │ │ + stc2l 15, cr12, [r2, #120]! @ 0x78 │ │ umaaleq r7, pc, r0, pc @ │ │ ldr r0, [pc, #4076] @ 23fa494 │ │ add r0, pc, r0 │ │ ldrb r0, [r0] │ │ cmp r0, #1 │ │ bne 23f955c │ │ bl 270d730 │ │ @@ -1229673,15 +1229673,15 @@ │ │ mov r2, #40 @ 0x28 │ │ ldr r1, [pc, #4036] @ 23fa58c │ │ mov r3, #8 │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ b 23f831c │ │ addeq r5, lr, r4, lsl #27 │ │ - stc2l 4, cr14, [r3, #892]! @ 0x37c │ │ + stc2l 5, cr14, [r3, #48]! @ 0x30 │ │ addseq r6, r5, r4, lsr r2 │ │ addseq pc, r5, r8, ror #28 │ │ stc2l 4, cr0, [r5, #484]! @ 0x1e4 │ │ addseq pc, r5, r8, lsr lr @ │ │ addseq pc, r5, r0, lsr lr @ │ │ subseq fp, r0, r4, lsl #15 │ │ stc2l 15, cr13, [r4, #728]! @ 0x2d8 │ │ @@ -1229783,35 +1229783,35 @@ │ │ addseq sl, r5, r0, asr #29 │ │ strheq r7, [pc], #-216 @ │ │ subeq r7, pc, r4, lsr #27 │ │ umullseq sl, r5, r0, lr │ │ addseq r6, r5, ip, asr r0 │ │ umullseq pc, r5, r0, ip @ │ │ addseq pc, r5, r0, lsl #25 │ │ - stc2l 12, cr12, [r2, #564]! @ 0x234 │ │ + stc2l 12, cr12, [r2, #744]! @ 0x2e8 │ │ addseq pc, r5, ip, asr #24 │ │ addeq r5, lr, r0, lsr #22 │ │ - stc2l 2, cr14, [r3, #492]! @ 0x1ec │ │ - stc2l 2, cr14, [r3, #332]! @ 0x14c │ │ + stc2l 2, cr14, [r3, #672]! @ 0x2a0 │ │ + stc2l 2, cr14, [r3, #512]! @ 0x200 │ │ @ instruction: 0x0095fbf0 │ │ addseq r5, r5, r0, lsr #31 │ │ - stc2l 11, cr12, [r2, #964]! @ 0x3c4 @ │ │ + stc2l 12, cr12, [r2, #120]! @ 0x78 │ │ addeq r5, lr, ip, lsl #21 │ │ addseq pc, r5, r4, lsr #23 │ │ stc2l 12, cr1, [r5, #260]! @ 0x104 │ │ subseq r0, r1, ip, lsr #6 │ │ eorseq pc, r4, ip, lsl #23 │ │ stc2l 14, cr0, [r2, #776]! @ 0x308 │ │ addseq sl, r5, r4, lsl sp │ │ addseq sl, r5, ip, lsl #26 │ │ - stc2l 1, cr14, [r3, #292]! @ 0x124 │ │ + stc2l 1, cr14, [r3, #472]! @ 0x1d8 │ │ @ instruction: 0x0095acbc │ │ - stc2l 1, cr14, [r3, #116]! @ 0x74 │ │ + stc2l 1, cr14, [r3, #296]! @ 0x128 │ │ addseq sl, r5, ip, lsl #25 │ │ - stc2l 10, cr12, [r2, #684]! @ 0x2ac @ │ │ + stc2l 10, cr12, [r2, #864]! @ 0x360 @ │ │ addseq sl, r5, r0, asr ip │ │ subseq fp, r0, r0, lsl #8 │ │ sbcseq r5, sl, ip, asr r6 │ │ addseq sl, r5, r0, lsl #24 │ │ addseq pc, r5, ip, lsl sl @ │ │ rsceq r8, r6, r8, asr #22 │ │ umullseq r0, r5, r8, pc @ │ │ @@ -1229975,18 +1229975,18 @@ │ │ mov r3, #3504 @ 0xdb0 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 23f9620 │ │ stc2l 5, cr6, [r4, #208]! @ 0xd0 │ │ addseq r0, r5, r0, ror #30 │ │ - stc2l 0, cr14, [r3, #68]! @ 0x44 │ │ + stc2l 0, cr14, [r3, #248]! @ 0xf8 │ │ addseq sl, r5, r4, lsl #23 │ │ subeq r7, pc, r8, ror sl @ │ │ - stc2l 15, cr13, [r3, #844]! @ 0x34c │ │ + stc2l 0, cr14, [r3] │ │ addseq r5, r5, r0, lsr #26 │ │ ldr r7, [pc, #3896] @ 23fa9e4 │ │ mov r2, sl │ │ movw r3, #3240 @ 0xca8 │ │ add r7, pc, r7 │ │ mov r0, r7 │ │ bl 270da30 │ │ @@ -1230009,36 +1230009,36 @@ │ │ ldr r7, [pc, #3824] @ 23fa9f4 │ │ movw r8, #4999 @ 0x1387 │ │ add r7, pc, r7 │ │ ldr r0, [sp, #4] │ │ add r0, r4, r0 │ │ str r0, [r2, r1, lsl #2] │ │ b 23f8320 │ │ - stc2l 9, cr12, [r2, #234]! @ 0xea @ │ │ + stc2l 9, cr12, [r2, #324]! @ 0x144 @ │ │ bl 270de10 │ │ mov r5, r0 │ │ ldr r0, [pc, #3788] @ 23fa9f8 │ │ ldr r0, [pc, r0] │ │ str r0, [fp, #-56] @ 0xffffffc8 │ │ cmp r0, #1 │ │ blt 23fa250 │ │ mov r4, #0 │ │ mov r8, #0 │ │ b 23f9bac │ │ addeq r5, lr, r4, lsl r8 │ │ subeq r7, pc, ip, lsl #20 │ │ - stc2l 15, cr13, [r3, #412]! @ 0x19c │ │ + stc2l 15, cr13, [r3, #592]! @ 0x250 │ │ @ instruction: 0x00955cb4 │ │ subseq fp, r0, r4, ror r2 │ │ addseq ip, r4, r0, asr r0 │ │ addseq pc, r5, ip, asr #17 │ │ @ instruction: 0x0095f8b8 │ │ stc2l 3, cr2, [r4, #596]! @ 0x254 │ │ @ instruction: 0x0094bff8 │ │ - stc2l 8, cr12, [r2, #604]! @ 0x25c │ │ + vcmla.f16 q14, q9, q2, #270 │ │ subseq fp, r0, r8, ror #3 │ │ ldr r0, [pc, #3712] @ 23fa9fc │ │ clz r2, r8 │ │ mov r1, #0 │ │ add r0, pc, r0 │ │ lsr r2, r2, #5 │ │ ldr r0, [r0, r7, lsl #2] │ │ @@ -1230081,15 +1230081,15 @@ │ │ mov r8, r4 │ │ add r1, pc, r1 │ │ ldr r5, [r1, r0, lsl #2] │ │ b 23f9ba0 │ │ stc2l 14, cr15, [r4, #468]! @ 0x1d4 │ │ addseq pc, r5, r4, lsr r8 @ │ │ addseq pc, r5, ip, lsl r8 @ │ │ - stc2l 4, cr4, [r2, #760]! @ 0x2f8 │ │ + stc2l 4, cr4, [r2, #940]! @ 0x3ac │ │ sbcseq r0, sl, ip, ror #11 │ │ ldr r0, [pc, #3928] @ 23faba0 │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ cmp r1, r6 │ │ bcc 23f9c6c │ │ ldr r0, [pc, #3912] @ 23faba4 │ │ @@ -1230150,61 +1230150,61 @@ │ │ str r1, [fp, #-56] @ 0xffffffc8 │ │ add r0, pc, r0 │ │ str r4, [r0, r1, lsl #2] │ │ b 23fa60c │ │ subseq r1, r0, r0, ror #8 │ │ stc2l 6, cr5, [r5, #460]! @ 0x1cc │ │ sbcseq r5, r6, r4, ror #22 │ │ - stc2l 6, cr8, [r2, #604]! @ 0x25c │ │ + stc2l 6, cr8, [r2, #784]! @ 0x310 │ │ smullseq fp, r9, r8, r6 │ │ stc2l 11, cr3, [r5, #252]! @ 0xfc @ │ │ sbcseq sl, r6, r0, lsr r9 │ │ stc2l 0, cr14, [r1, #412]! @ 0x19c │ │ - stc2l 5, cr6, [r3, #416]! @ 0x1a0 │ │ + stc2l 5, cr6, [r3, #596]! @ 0x254 │ │ sbcseq r5, sl, r0, ror #4 │ │ sbcseq r4, r3, ip, ror sp │ │ eorseq pc, r4, ip, lsr #13 │ │ eorseq pc, r4, ip, ror #12 │ │ stc2l 11, cr9, [r4, #848]! @ 0x350 @ │ │ rsceq r8, r6, r8, asr #14 │ │ rsceq r8, r6, r0, lsr r7 │ │ eorseq pc, r4, ip, lsr #12 │ │ eorseq pc, r4, ip, lsr #12 │ │ ldrdeq r8, [r6], #108 @ 0x6c @ │ │ vcmla.f16 q8, q9, q9, #270 │ │ - stc2l 2, cr4, [r2, #68]! @ 0x44 │ │ - stc2l 11, cr13, [r3, #228]! @ 0xe4 @ │ │ + stc2l 2, cr4, [r2, #248]! @ 0xf8 │ │ + stc2l 11, cr13, [r3, #408]! @ 0x198 @ │ │ @ instruction: 0x0095f4d4 │ │ addseq sl, r5, r4, lsr #13 │ │ smullseq r0, sl, ip, r2 │ │ addseq sl, r5, ip, ror r6 │ │ sbcseq r0, sl, ip, ror r2 │ │ addseq pc, r5, ip, lsl #9 │ │ - stc2l 4, cr12, [r2, #556]! @ 0x22c │ │ + stc2l 4, cr12, [r2, #736]! @ 0x2e0 │ │ addseq pc, r5, r4, asr r4 @ │ │ ldrsbeq sl, [r0], #-220 @ 0xffffff24 │ │ - stc2l 10, cr13, [r3, #532]! @ 0x214 @ │ │ + stc2l 10, cr13, [r3, #712]! @ 0x2c8 @ │ │ addseq pc, r5, r0, lsl r4 @ │ │ addseq sl, r5, r0, ror #11 │ │ - stc2l 4, cr12, [r2, #44]! @ 0x2c │ │ + stc2l 4, cr12, [r2, #224]! @ 0xe0 │ │ subseq sl, r0, ip, asr sp │ │ eorseq pc, r4, ip, ror #7 │ │ stc2l 7, cr11, [r4, #304]! @ 0x130 │ │ subeq r7, pc, r4, lsl #9 │ │ addseq r5, r5, r0, lsr r7 │ │ addseq pc, r5, r4, ror #6 │ │ addseq pc, r5, r4, asr r3 @ │ │ stc2l 14, cr1, [r4, #180]! @ 0xb4 │ │ addseq pc, r5, ip, lsl r3 @ │ │ addseq fp, r4, r8, lsl #21 │ │ - stc2l 9, cr13, [r3, #150]! @ 0x96 @ │ │ + stc2l 9, cr13, [r3, #240]! @ 0xf0 @ │ │ stc2l 3, cr1, [r5, #452]! @ 0x1c4 │ │ subseq pc, r0, ip, asr sl @ │ │ ldrhteq pc, [r4], -ip @ │ │ - stc2l 1, cr6, [r3, #524]! @ 0x20c │ │ + stc2l 1, cr6, [r3, #704]! @ 0x2c0 │ │ ldr r7, [pc, #3508] @ 23fabc4 │ │ cmp r8, #0 │ │ add r7, pc, r7 │ │ beq 23fa250 │ │ sub r5, r8, #1 │ │ movw r0, #5001 @ 0x1389 │ │ cmp r8, r0 │ │ @@ -1230465,15 +1230465,15 @@ │ │ str r5, [fp, #-56] @ 0xffffffc8 │ │ b 23fb334 │ │ rsceq r8, r6, r0, lsl #7 │ │ rsceq r8, r6, r8, ror #6 │ │ eorseq pc, r4, r4, ror #4 │ │ eorseq pc, r4, r4, ror #4 │ │ rsceq r8, r6, r4, lsl r3 │ │ - stc2l 0, cr6, [r3, #684]! @ 0x2ac │ │ + stc2l 0, cr6, [r3, #864]! @ 0x360 │ │ stc2l 7, cr9, [r4, #248]! @ 0xf8 │ │ ldrhteq pc, [r4], -r0 @ │ │ stc2l 12, cr5, [r4, #860]! @ 0x35c │ │ eorseq pc, r4, r0, ror r1 @ │ │ stc2l 8, cr15, [r1, #72]! @ 0x48 │ │ ldr r0, [pc, #3908] @ 23fb19c │ │ ldr r0, [pc, r0] │ │ @@ -1230538,15 +1230538,15 @@ │ │ mov r0, #0 │ │ str r1, [fp, #-56] @ 0xffffffc8 │ │ str r0, [r4, r1, lsl #2] │ │ mov r4, #0 │ │ b 23fa7e8 │ │ addseq pc, r5, ip, lsr #2 │ │ addseq sl, r5, ip, ror #5 │ │ - stc2l 13, cr3, [r2, #568]! @ 0x238 │ │ + stc2l 13, cr3, [r2, #748]! @ 0x2ec │ │ ldrheq pc, [r9], #236 @ 0xec @ │ │ ldr r0, [pc, #3892] @ 23fb2a0 │ │ mov r2, sl │ │ movw r3, #3342 @ 0xd0e │ │ add r0, pc, r0 │ │ bl 270da30 │ │ ldr r1, [pc, #3876] @ 23fb2a4 │ │ @@ -1230562,18 +1230562,18 @@ │ │ add r2, pc, r2 │ │ ldr r0, [r2, r1, lsl #2] │ │ add r4, r0, r3 │ │ str r4, [r2, r1, lsl #2] │ │ str r1, [fp, #-56] @ 0xffffffc8 │ │ b 23f90a8 │ │ addseq pc, r5, r4, asr #1 │ │ - stc2l 6, cr13, [r3, #1012]! @ 0x3f4 │ │ + stc2l 7, cr13, [r3, #168]! @ 0xa8 │ │ addseq sl, r5, r0, ror r2 │ │ addseq pc, r5, ip, lsl #1 │ │ - stc2l 13, cr3, [r2, #104]! @ 0x68 │ │ + stc2l 13, cr3, [r2, #284]! @ 0x11c │ │ sbcseq pc, r9, r4, asr #28 │ │ addseq pc, r5, r0, asr r0 @ │ │ stc2l 6, cr15, [r4, #388]! @ 0x184 │ │ addseq pc, r5, r0, lsr #32 │ │ mov r0, r5 │ │ bl 270e0c0 │ │ cmp r0, #0 │ │ @@ -1230956,15 +1230956,15 @@ │ │ ldr r4, [r3, r1, lsl #2] │ │ b 23faa58 │ │ subseq r4, r1, r4, lsl #1 │ │ addseq lr, r5, r8, lsl #21 │ │ stc2l 5, cr1, [r4, #372]! @ 0x174 │ │ rsbeq sl, r9, r8, lsl sl │ │ stc2l 13, cr10, [r4, #684]! @ 0x2ac │ │ - stc2l 0, cr13, [r3, #164]! @ 0xa4 │ │ + stc2l 0, cr13, [r3, #344]! @ 0x158 │ │ addseq lr, r5, r0, asr #19 │ │ addseq r9, r5, r8, lsl #23 │ │ addseq r9, r5, r0, ror #22 │ │ addseq lr, r5, r8, ror r9 │ │ subeq r6, pc, r8, lsr sl @ │ │ @ instruction: 0x00959ad8 │ │ mov r2, sl │ │ @@ -1231063,29 +1231063,29 @@ │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #3908] @ 23fbacc │ │ add r0, pc, r0 │ │ b 23facf4 │ │ addseq lr, r5, r8, asr #17 │ │ - stc2l 14, cr12, [r3, #1012]! @ 0x3f4 │ │ + stc2l 15, cr12, [r3, #168]! @ 0xa8 │ │ addseq r9, r5, r0, ror sl │ │ - stc2l 14, cr12, [r3, #804]! @ 0x324 │ │ + stc2l 14, cr12, [r3, #984]! @ 0x3d8 │ │ addseq r9, r5, r8, lsr sl │ │ addseq lr, r5, r8, lsr r8 │ │ - stc2l 14, cr12, [r3, #460]! @ 0x1cc │ │ + stc2l 14, cr12, [r3, #640]! @ 0x280 │ │ addseq lr, r5, r0, lsl r8 │ │ addseq r4, r5, r0, asr #23 │ │ addseq sl, r4, r4, ror #30 │ │ addseq lr, r5, r4, lsr #15 │ │ vcmla.f16 q8, , , #270 │ │ subseq lr, r0, r4, lsl pc │ │ addeq r9, lr, r4, asr #8 │ │ addseq lr, r5, ip, ror #12 │ │ - stc2l 6, cr11, [r2, #412]! @ 0x19c │ │ + stc2l 6, cr11, [r2, #592]! @ 0x250 │ │ subseq r9, r0, r4, asr #31 │ │ ldr r0, [fp, #-68] @ 0xffffffbc │ │ ldr r1, [pc, #3828] @ 23fbad0 │ │ add r1, pc, r1 │ │ vldr d8, [r1] │ │ mvn r1, #1 │ │ add r1, r1, r0, lsl #1 │ │ @@ -1231269,32 +1231269,32 @@ │ │ add r1, pc, r1 │ │ b 23f831c │ │ stc2l 1, cr5, [r4, #64]! @ 0x40 │ │ addseq pc, r4, r0, asr #22 │ │ stc2l 0, cr5, [r4, #848]! @ 0x350 │ │ addseq pc, r4, ip, lsl #22 │ │ subeq r6, pc, r8, asr #12 │ │ - stc2l 11, cr12, [r3, #660]! @ 0x294 @ │ │ + stc2l 11, cr12, [r3, #840]! @ 0x348 @ │ │ addseq r9, r5, r8, lsl #14 │ │ - stc2l 11, cr12, [r3, #420]! @ 0x1a4 @ │ │ + stc2l 11, cr12, [r3, #600]! @ 0x258 @ │ │ @ instruction: 0x009596dc │ │ ldrdeq r6, [pc], #-88 @ │ │ - stc2l 5, cr11, [r2, #36]! @ 0x24 │ │ + stc2l 5, cr11, [r2, #216]! @ 0xd8 │ │ addeq r4, lr, r0, lsr #7 │ │ - stc2l 4, cr11, [r2, #820]! @ 0x334 │ │ + stc2l 4, cr11, [r2, #1000]! @ 0x3e8 │ │ addeq r4, lr, ip, ror #6 │ │ subeq r6, pc, r8, ror #10 │ │ stc2l 15, cr0, [r4, #420]! @ 0x1a4 │ │ @ instruction: 0x0094abd0 │ │ stc2l 15, cr0, [r4, #180]! @ 0xb4 │ │ umullseq sl, r4, ip, fp │ │ strdeq r6, [pc], #-72 @ │ │ - stc2l 4, cr11, [r2, #140]! @ 0x8c │ │ + stc2l 4, cr11, [r2, #320]! @ 0x140 │ │ subseq r9, r0, r8, ror sp │ │ - stc2l 3, cr11, [r2, #924]! @ 0x39c │ │ + stc2l 4, cr11, [r2, #80]! @ 0x50 │ │ subseq r9, r0, r4, asr #26 │ │ subeq r6, pc, r8, lsl #9 │ │ stc2l 5, cr12, [r4, #312]! @ 0x138 │ │ ldr r0, [pc, #4080] @ 23fbf14 │ │ mov r2, sl │ │ movw r3, #3757 @ 0xead │ │ add r0, pc, r0 │ │ @@ -1231448,15 +1231448,15 @@ │ │ add r1, pc, r1 │ │ cmp r0, #1 │ │ str r0, [r1] │ │ bge 23fb1bc │ │ b 23fbc54 │ │ strdeq pc, [pc], #-248 @ │ │ umaaleq r6, pc, r0, r3 @ │ │ - stc2l 2, cr7, [r2, #268]! @ 0x10c │ │ + stc2l 2, cr7, [r2, #448]! @ 0x1c0 │ │ sbcseq sl, r9, r8, asr #4 │ │ rsceq r7, r6, ip, ror #6 │ │ stc2l 13, cr0, [r4, #108]! @ 0x6c │ │ ldr r0, [r5, r1, lsl #2] │ │ ldr r1, [pc, #3604] @ 23fbfc4 │ │ add r1, pc, r1 │ │ cmp r0, #0 │ │ @@ -1231512,35 +1231512,35 @@ │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 23fb1a4 │ │ sbcseq r3, sl, ip, ror #27 │ │ stc2l 7, cr8, [r4, #552]! @ 0x228 │ │ addseq lr, r5, r0, asr #3 │ │ - stc2l 1, cr11, [r2, #796]! @ 0x31c │ │ + stc2l 1, cr11, [r2, #976]! @ 0x3d0 │ │ subseq r9, r0, r0, lsr #22 │ │ addseq lr, r5, r4, asr r1 │ │ stc2l 12, cr0, [r4, #52]! @ 0x34 │ │ addseq sl, r4, ip, ror r8 │ │ ldrsheq lr, [r5], r8 │ │ @ instruction: 0x009592b8 │ │ addseq lr, r5, r0, lsl #1 │ │ stc2l 1, cr0, [r5, #116]! @ 0x74 │ │ ldrsheq lr, [r0], #-112 @ 0xffffff90 │ │ addeq r8, lr, r0, lsr #26 │ │ addseq lr, r5, r8, lsl r0 │ │ sbcseq lr, r9, r0, ror #27 │ │ - stc2l 12, cr2, [r2, #564]! @ 0x234 │ │ - stc2l 6, cr12, [r3, #20]! │ │ + stc2l 12, cr2, [r2, #744]! @ 0x2e8 │ │ + stc2l 6, cr12, [r3, #200]! @ 0xc8 │ │ addseq r9, r5, r8, ror r1 │ │ umullseq sp, r5, r4, pc @ │ │ - stc2l 5, cr12, [r3, #788]! @ 0x314 │ │ + stc2l 5, cr12, [r3, #968]! @ 0x3c8 │ │ addseq r9, r5, r8, lsr r1 │ │ addseq sp, r5, r4, asr pc │ │ - stc2l 15, cr10, [r2, #364]! @ 0x16c │ │ + stc2l 15, cr10, [r2, #544]! @ 0x220 │ │ eorseq sp, r4, r8, asr #30 │ │ stc2l 4, cr8, [r4, #788]! @ 0x314 │ │ ldr r0, [pc, #3312] @ 23fbfe8 │ │ mov r1, r5 │ │ mov r2, sl │ │ movw r3, #3662 @ 0xe4e │ │ add r0, pc, r0 │ │ @@ -1231716,15 +1231716,15 @@ │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ bl 270d9e0 │ │ ldr r5, [pc, #3784] @ 23fc484 │ │ movw r8, #4999 @ 0x1387 │ │ add r5, pc, r5 │ │ b 23f8320 │ │ - stc2l 6, cr10, [r3, #492]! @ 0x1ec │ │ + stc2l 6, cr10, [r3, #672]! @ 0x2a0 │ │ umulleq r8, lr, r4, fp │ │ stc2l 4, cr14, [r4, #736]! @ 0x2e0 │ │ ldr r2, [pc, #3760] @ 23fc488 │ │ mov r4, #0 │ │ ldr r2, [pc, r2] │ │ ldr r0, [pc, #3752] @ 23fc48c │ │ cmp r2, #1 │ │ @@ -1231762,20 +1231762,20 @@ │ │ stc2l 8, cr0, [r4, #996]! @ 0x3e4 │ │ ldrheq r3, [r1], #-56 @ 0xffffffc8 │ │ rsbeq r9, r9, ip, lsr #27 │ │ eorseq sp, r4, r4, lsr #28 │ │ eorseq sp, r4, r4, lsr #28 │ │ addseq sp, r5, r0, lsr #27 │ │ smullseq r3, sl, r4, r9 │ │ - stc2l 13, cr10, [r2, #636]! @ 0x27c │ │ + stc2l 13, cr10, [r2, #816]! @ 0x330 │ │ ldrsheq r9, [r0], #-100 @ 0xffffff9c │ │ addseq sp, r5, ip, asr #26 │ │ - stc2l 13, cr10, [r2, #332]! @ 0x14c │ │ + stc2l 13, cr10, [r2, #512]! @ 0x200 │ │ subseq r9, r0, ip, lsr #13 │ │ - stc2l 13, cr10, [r2, #12]! │ │ + stc2l 13, cr10, [r2, #192]! @ 0xc0 │ │ ldr r7, [pc, #3596] @ 23fc4a8 │ │ mov r2, sl │ │ movw r3, #4078 @ 0xfee │ │ add r7, pc, r7 │ │ mov r0, r7 │ │ bl 270da30 │ │ ldr r1, [pc, #3576] @ 23fc4ac │ │ @@ -1231842,18 +1231842,18 @@ │ │ add r0, r2, r1, lsl #3 │ │ vldr d16, [r0] │ │ vcmp.f64 d16, d8 │ │ vmrs APSR_nzcv, fpscr │ │ vmovge.f64 d8, d16 │ │ b 23fb944 │ │ addseq sp, r5, r4, asr #25 │ │ - stc2l 2, cr12, [r3, #1012]! @ 0x3f4 │ │ + stc2l 3, cr12, [r3, #168]! @ 0xa8 │ │ addseq r8, r5, ip, ror #28 │ │ subeq r5, pc, r4, ror #26 │ │ - stc2l 2, cr12, [r3, #764]! @ 0x2fc │ │ + stc2l 2, cr12, [r3, #944]! @ 0x3b0 │ │ vldr d8, [sp, #40] @ 0x28 │ │ vcmp.f64 d16, d8 │ │ vmrs APSR_nzcv, fpscr │ │ bpl 23fb94c │ │ ldr r0, [pc, #4016] @ 23fc794 │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ @@ -1231866,18 +1231866,18 @@ │ │ vldr d16, [r0] │ │ vcmp.f64 d16, d8 │ │ vmrs APSR_nzcv, fpscr │ │ vmovls.f64 d8, d16 │ │ b 23fb944 │ │ addseq sp, r5, ip, asr ip │ │ addseq r4, r5, ip │ │ - stc2l 12, cr10, [r2, #372]! @ 0x174 │ │ + stc2l 12, cr10, [r2, #552]! @ 0x228 │ │ strdeq r3, [lr], r8 │ │ strdeq r5, [pc], #-192 @ │ │ - stc2l 2, cr12, [r3, #300]! @ 0x12c │ │ + stc2l 2, cr12, [r3, #480]! @ 0x1e0 │ │ addseq r3, r5, r0, lsr #31 │ │ @ instruction: 0x0095dbdc │ │ mov r8, r5 │ │ ldr r5, [pc, #4060] @ 23fc81c │ │ mov r2, sl │ │ movw r3, #4105 @ 0x1009 │ │ add r5, pc, r5 │ │ @@ -1231907,18 +1231907,18 @@ │ │ add r2, pc, r2 │ │ b 23fb940 │ │ stc2l 6, cr0, [r4, #740]! @ 0x2e4 │ │ addseq sl, r4, ip, lsl r3 │ │ eorseq sp, r4, r4, asr #23 │ │ stc2l 1, cr8, [r4, #176]! @ 0xb0 │ │ strhteq r6, [r6], #204 @ 0xcc │ │ - vcmla.f16 d18, d2, d2, #270 │ │ + vcmla.f16 d18, d2, d31, #270 │ │ ldrsbeq lr, [r0], #-36 @ 0xffffffdc │ │ strdeq r5, [pc], #-176 @ │ │ - stc2l 7, cr2, [r2, #664]! @ 0x298 │ │ + stc2l 7, cr2, [r2, #844]! @ 0x34c │ │ addseq r2, r6, r8, lsl #18 │ │ ldr r8, [pc, #4080] @ 23fc8cc │ │ mov r2, sl │ │ movw r3, #4114 @ 0x1012 │ │ add r8, pc, r8 │ │ mov r0, r8 │ │ bl 270da30 │ │ @@ -1232263,15 +1232263,15 @@ │ │ mov r1, sl │ │ mov r2, r4 │ │ mov r3, #2048 @ 0x800 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ b 23fbda4 │ │ stc2l 11, cr7, [r4, #712]! @ 0x2c8 @ │ │ - stc2l 13, cr9, [r3, #904]! @ 0x388 │ │ + stc2l 14, cr9, [r3, #60]! @ 0x3c │ │ eorseq sp, r4, ip, lsl #12 │ │ stc2l 1, cr4, [r4, #204]! @ 0xcc │ │ ldr r1, [pc, #3756] @ 23fcd10 │ │ add r1, pc, r1 │ │ str r8, [r1, r0, lsl #2] │ │ mov r0, r6 │ │ mov r1, r6 │ │ @@ -1232312,15 +1232312,15 @@ │ │ ldr r0, [pc, #3612] @ 23fcd1c │ │ add r0, pc, r0 │ │ ldr r0, [r0, sl, lsl #2] │ │ cmp r9, r0 │ │ mov r0, sl │ │ beq 23fbe5c │ │ b 23fbe68 │ │ - stc2l 13, cr9, [r3, #124]! @ 0x7c │ │ + stc2l 13, cr9, [r3, #304]! @ 0x130 │ │ addeq r8, lr, r8, lsr r2 │ │ stc2l 11, cr13, [r4, #368]! @ 0x170 @ │ │ ldr r0, [pc, #3576] @ 23fcd20 │ │ mov r1, sl │ │ mov r2, r4 │ │ movw r3, #2028 @ 0x7ec │ │ add r0, pc, r0 │ │ @@ -1232343,50 +1232343,50 @@ │ │ stc2l 15, cr15, [r3, #628]! @ 0x274 │ │ subseq r2, r1, ip, asr sl │ │ rsbeq r9, r9, r0, asr r4 │ │ eorseq sp, r4, r8, asr #9 │ │ eorseq sp, r4, r8, asr #9 │ │ addseq sp, r5, r4, asr #8 │ │ sbcseq r3, sl, r8, lsr r0 │ │ - stc2l 4, cr10, [r2, #268]! @ 0x10c │ │ + stc2l 4, cr10, [r2, #448]! @ 0x1c0 │ │ @ instruction: 0x00508d9c │ │ @ instruction: 0x0095d3f8 │ │ - stc2l 3, cr10, [r2, #1020]! @ 0x3fc │ │ + stc2l 4, cr10, [r2, #176]! @ 0xb0 │ │ subseq r8, r0, r8, asr sp │ │ eorseq sp, r4, r4, asr #7 │ │ - stc2l 4, cr0, [r2, #124]! @ 0x7c │ │ - stc2l 0, cr2, [r2, #56]! @ 0x38 │ │ + stc2l 4, cr0, [r2, #304]! @ 0x130 │ │ + stc2l 0, cr2, [r2, #236]! @ 0xec │ │ sbcseq lr, r9, r8, lsr r1 │ │ addseq sp, r5, r4, asr #6 │ │ - stc2l 3, cr10, [r2, #300]! @ 0x12c │ │ + stc2l 3, cr10, [r2, #480]! @ 0x1e0 │ │ subseq r8, r0, r4, lsr #25 │ │ ldrheq sp, [r0], #-168 @ 0xffffff58 │ │ subseq sp, r0, r4, lsl #21 │ │ - stc2l 10, cr9, [r3, #396]! @ 0x18c @ │ │ + stc2l 10, cr9, [r3, #576]! @ 0x240 @ │ │ addseq sp, r5, r8, lsl #5 │ │ addeq r7, lr, ip, ror pc │ │ stc2l 3, cr15, [r4, #116]! @ 0x74 │ │ subseq sp, r0, r8, lsl #20 │ │ ldrsheq sp, [r0], #-148 @ 0xffffff6c │ │ sbcseq r2, sl, r8, lsr #28 │ │ stc2l 5, cr9, [r4, #684]! @ 0x2ac │ │ - stc2l 1, cr6, [r2, #188]! @ 0xbc │ │ + stc2l 1, cr6, [r2, #368]! @ 0x170 │ │ sbcseq r9, r9, r0, lsr r1 │ │ stc2l 5, cr1, [r5, #860]! @ 0x35c │ │ subeq r5, pc, r8, lsr #4 │ │ stc2l 5, cr1, [r5, #684]! @ 0x2ac │ │ smullseq r8, r6, r8, r3 │ │ ldrdeq r5, [pc], #-24 @ │ │ stc2l 0, cr3, [r5, #236]! @ 0xec │ │ sbcseq r3, r6, r0, lsr r5 │ │ stc2l 15, cr2, [r5, #1020]! @ 0x3fc │ │ ldrsheq r3, [r6], #76 @ 0x4c │ │ subeq r5, pc, r8, ror #2 │ │ stc2l 6, cr13, [r4, #628]! @ 0x274 │ │ - stc2l 13, cr1, [r2, #24]! │ │ + stc2l 13, cr1, [r2, #204]! @ 0xcc │ │ addseq sp, r5, r4, asr r0 │ │ ldr r0, [pc, #3988] @ 23fcfc0 │ │ ldr r0, [pc, r0] │ │ ldr r1, [sp, #4] │ │ cmp r1, r0 │ │ beq 23fc6dc │ │ sub r1, r0, #1 │ │ @@ -1232643,41 +1232643,41 @@ │ │ cmp sl, r1 │ │ bcs 23fc4c4 │ │ str r8, [r0, sl, lsl #2] │ │ mov r8, sl │ │ str sl, [fp, #-56] @ 0xffffffc8 │ │ b 23fc504 │ │ stc2l 6, cr13, [r4, #356]! @ 0x164 │ │ - stc2l 12, cr1, [r2, #808]! @ 0x328 │ │ + stc2l 12, cr1, [r2, #988]! @ 0x3dc │ │ addseq sp, r5, r8, lsl r0 │ │ subeq r5, pc, r8, ror #1 │ │ sbcseq sp, r9, r4, asr #27 │ │ - stc2l 12, cr1, [r2, #392]! @ 0x188 │ │ + stc2l 12, cr1, [r2, #572]! @ 0x23c │ │ sbcseq sp, r9, ip, lsl #27 │ │ subeq r5, pc, r8, ror r0 @ │ │ - stc2l 14, cr3, [r3, #400]! @ 0x190 │ │ - stc2l 14, cr3, [r3, #224]! @ 0xe0 │ │ + stc2l 14, cr3, [r3, #580]! @ 0x244 │ │ + stc2l 14, cr3, [r3, #404]! @ 0x194 │ │ sbcseq r2, r3, r8, asr r6 │ │ eorseq ip, r4, r4, lsl #31 │ │ strdeq r4, [pc], #-244 @ │ │ addseq ip, r5, r4, lsl #30 │ │ @ instruction: 0x0095cef4 │ │ subeq r4, pc, r8, asr #31 │ │ eorseq ip, r4, ip, lsl #30 │ │ - stc2l 15, cr15, [r1, #412]! @ 0x19c │ │ + stc2l 15, cr15, [r1, #592]! @ 0x250 │ │ sbcseq r2, sl, ip, asr #21 │ │ addseq ip, r5, r4, lsr #29 │ │ - stc2l 11, cr1, [r2, #296]! @ 0x128 @ │ │ + stc2l 11, cr1, [r2, #476]! @ 0x1dc @ │ │ rsceq r5, r6, ip, asr #31 │ │ strhteq r5, [r6], #240 @ 0xf0 │ │ rsceq r5, r6, r4, lsr #31 │ │ addseq r1, r6, ip, ror ip │ │ addseq ip, r5, r4, asr #28 │ │ sbcseq sp, r9, r4, lsl ip │ │ - stc2l 10, cr1, [r2, #568]! @ 0x238 @ │ │ + stc2l 10, cr1, [r2, #748]! @ 0x2ec @ │ │ @ instruction: 0x0095cdd0 │ │ sbcseq sp, r9, r8, lsr #23 │ │ sbcseq sp, r9, r0, lsl #23 │ │ addseq ip, r5, ip, lsl #27 │ │ eorseq ip, r4, r8, asr #27 │ │ eorseq ip, r4, r8, asr #27 │ │ mov r9, r0 │ │ @@ -1232972,20 +1232972,20 @@ │ │ add sl, pc, sl │ │ add r9, pc, r9 │ │ b 23fc998 │ │ ldrheq r8, [r0], #-68 @ 0xffffffbc │ │ @ instruction: 0x00508490 │ │ @ instruction: 0x0095caf0 │ │ @ instruction: 0x0095cab8 │ │ - stc2l 7, cr1, [r2, #392]! @ 0x188 │ │ + stc2l 7, cr1, [r2, #572]! @ 0x23c │ │ stc2l 11, cr14, [r4, #228]! @ 0xe4 @ │ │ subseq sp, r0, r4, lsr #4 │ │ smlaleq r5, r6, ip, fp │ │ addseq ip, r5, r0, asr sl │ │ - stc2l 6, cr1, [r2, #984]! @ 0x3d8 │ │ + stc2l 7, cr1, [r2, #140]! @ 0x8c │ │ addseq ip, r5, ip, lsr sl │ │ ldr r0, [fp, #-56] @ 0xffffffc8 │ │ add r1, r4, #1 │ │ str r8, [sl, r5, lsl #2] │ │ cmp r4, r0 │ │ mov r4, r1 │ │ bge 23fcaa0 │ │ @@ -1233050,15 +1233050,15 @@ │ │ strb r2, [r1] │ │ b 23fe218 │ │ @ instruction: 0x0095c9f8 │ │ str r0, [fp, #-56] @ 0xffffffc8 │ │ ldr r0, [pc, #4000] @ 23fda38 │ │ add r0, pc, r0 │ │ b 23fe218 │ │ - stc2l 9, cr9, [r2, #510]! @ 0x1fe @ │ │ + stc2l 10, cr9, [r2, #176]! @ 0xb0 @ │ │ ldr r0, [pc, #3988] @ 23fda3c │ │ ldr r0, [pc, r0] │ │ cmp r0, #1 │ │ blt 23fd0cc │ │ ldr r9, [pc, #3976] @ 23fda40 │ │ movw r5, #34464 @ 0x86a0 │ │ ldr r4, [pc, #3972] @ 23fda44 │ │ @@ -1233067,18 +1233067,18 @@ │ │ mov r1, #1 │ │ add r4, pc, r4 │ │ movt r5, #1 │ │ b 23fcb24 │ │ smullseq r2, sl, ip, r5 │ │ subeq r4, pc, ip, asr sl @ │ │ addseq ip, r5, r8, ror r9 │ │ - stc2l 9, cr9, [r2, #246]! @ 0xf6 @ │ │ + stc2l 9, cr9, [r2, #336]! @ 0x150 @ │ │ ldrsbeq r8, [r0], #-36 @ 0xffffffdc │ │ addseq ip, r5, r0, lsr r9 │ │ - stc2l 9, cr9, [r2, #110]! @ 0x6e @ │ │ + stc2l 9, cr9, [r2, #200]! @ 0xc8 @ │ │ subseq r8, r0, ip, lsl #5 │ │ addseq ip, r5, r4, ror #17 │ │ ldr r1, [pc, #3912] @ 23fda48 │ │ add r1, pc, r1 │ │ ldr r0, [r1, r0, lsl #2] │ │ cmp r0, #0 │ │ ble 23fcd2c │ │ @@ -1233124,17 +1233124,17 @@ │ │ stc2l 10, cr10, [r4, #536]! @ 0x218 @ │ │ subeq r4, pc, r8, lsr #19 │ │ umullseq ip, r5, r4, r8 │ │ stc2l 3, cr3, [r4, #824]! @ 0x338 │ │ umaaleq lr, pc, r8, r5 @ │ │ sbcseq r2, sl, r8, asr r4 │ │ eorseq ip, r4, r0, ror r8 │ │ - stc2l 5, cr5, [r3, #104]! @ 0x68 │ │ + stc2l 5, cr5, [r3, #284]! @ 0x11c │ │ eorseq ip, r4, r0, asr r8 │ │ - stc2l 3, cr7, [r2, #4]! │ │ + stc2l 3, cr7, [r2, #184]! @ 0xb8 │ │ ldr r1, [pc, #3724] @ 23fda64 │ │ add r1, pc, r1 │ │ str r6, [r1, r0, lsl #2] │ │ cmp r6, #0 │ │ str r6, [fp, #-68] @ 0xffffffbc │ │ ble 23fcb74 │ │ mov r0, r7 │ │ @@ -1233204,24 +1233204,24 @@ │ │ sbcseq r2, sl, r4, ror #6 │ │ stc2l 1, cr9, [r1, #964]! @ 0x3c4 │ │ strdeq r4, [pc], #-124 @ │ │ sbcseq r2, sl, r4, lsl #6 │ │ stc2l 10, cr8, [r4, #524]! @ 0x20c @ │ │ subseq r8, r0, r8, rrx │ │ umaaleq r4, pc, ip, r7 @ │ │ - stc2l 6, cr9, [r2, #684]! @ 0x2ac │ │ + stc2l 6, cr9, [r2, #864]! @ 0x360 │ │ subseq r8, r0, r8 │ │ - stc2l 6, cr9, [r2, #412]! @ 0x19c │ │ + stc2l 6, cr9, [r2, #592]! @ 0x250 │ │ ldrheq r7, [r0], #-240 @ 0xffffff10 │ │ - stc2l 13, cr8, [r3, #540]! @ 0x21c │ │ + stc2l 13, cr8, [r3, #720]! @ 0x2d0 │ │ addeq r7, lr, r8, lsr #5 │ │ subseq r7, r0, r4, lsl pc │ │ - stc2l 5, cr9, [r2, #476]! @ 0x1dc │ │ + stc2l 5, cr9, [r2, #656]! @ 0x290 │ │ ldrsbeq r7, [r0], #-228 @ 0xffffff1c │ │ - stc2l 5, cr9, [r2, #284]! @ 0x11c │ │ + stc2l 5, cr9, [r2, #464]! @ 0x1d0 │ │ ldr r0, [pc, #3412] @ 23fda88 │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ movw r0, #5000 @ 0x1388 │ │ cmp r1, r0 │ │ bcc 23fcd60 │ │ ldr r0, [pc, #3392] @ 23fda8c │ │ @@ -1233440,20 +1233440,20 @@ │ │ add r1, pc, r1 │ │ bl 270db00 │ │ ldr r0, [pc, #4084] @ 23fe09c │ │ mov r1, #21 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ b 23fbd4c │ │ - stc2l 10, cr10, [r3, #68]! @ 0x44 @ │ │ + stc2l 10, cr10, [r3, #248]! @ 0xf8 @ │ │ addseq r7, r5, ip, ror r5 │ │ - stc2l 9, cr10, [r3, #426]! @ 0x1aa @ │ │ + stc2l 10, cr10, [r3, #8]! @ │ │ addseq r7, r5, r8, asr #10 │ │ subeq r4, pc, r4, asr #8 │ │ - stc2l 3, cr9, [r2, #452]! @ 0x1c4 │ │ + stc2l 3, cr9, [r2, #632]! @ 0x278 │ │ ldr r4, [pc, #4044] @ 23fe0a0 │ │ ldr r4, [pc, r4] │ │ bl 270de10 │ │ sub r0, r0, #1 │ │ cmp r4, r0 │ │ bge 23fd14c │ │ ldr r8, [pc, #4024] @ 23fe0a4 │ │ @@ -1233477,15 +1233477,15 @@ │ │ bhi 23fd3c0 │ │ ldr r0, [pc, #3964] @ 23fe0b4 │ │ str r1, [fp, #-56] @ 0xffffffc8 │ │ add r0, pc, r0 │ │ str r5, [r0, r1, lsl #2] │ │ b 23fd424 │ │ addeq r2, lr, r8, lsl #4 │ │ - stc2l 3, cr9, [r2, #212]! @ 0xd4 │ │ + stc2l 3, cr9, [r2, #392]! @ 0x188 │ │ ldr r0, [pc, #3940] @ 23fe0b8 │ │ ldr r0, [pc, r0] │ │ str r0, [fp, #-56] @ 0xffffffc8 │ │ cmp r0, #1 │ │ blt 23fd43c │ │ ldr r9, [pc, #3924] @ 23fe0bc │ │ mov r8, #1 │ │ @@ -1233499,17 +1233499,17 @@ │ │ ldrdeq r2, [lr], r4 │ │ ldrdeq r4, [pc], #-48 @ │ │ stc2l 13, cr14, [r3, #820]! @ 0x334 │ │ addseq r8, r4, r4, lsr sl │ │ stc2l 13, cr14, [r3, #580]! @ 0x244 │ │ addseq r8, r4, r0, lsl #20 │ │ subeq r4, pc, ip, asr r3 @ │ │ - stc2l 2, cr9, [r2, #524]! @ 0x20c │ │ + stc2l 2, cr9, [r2, #704]! @ 0x2c0 │ │ ldrsbeq r7, [r0], #-184 @ 0xffffff48 │ │ - stc2l 2, cr9, [r2, #284]! @ 0x11c │ │ + stc2l 2, cr9, [r2, #464]! @ 0x1d0 │ │ subseq r7, r0, r4, lsr #23 │ │ subeq r4, pc, r8, ror #5 │ │ ldr r7, [pc, #3852] @ 23fe0c8 │ │ mov r1, sl │ │ ldr r2, [pc, #3848] @ 23fe0cc │ │ movw r3, #1667 @ 0x683 │ │ add r7, pc, r7 │ │ @@ -1233633,15 +1233633,15 @@ │ │ mov r0, #0 │ │ mov r4, r7 │ │ str r0, [r5, sl, lsl #2] │ │ b 23fd234 │ │ stc2l 0, cr2, [r5, #76]! @ 0x4c │ │ sbcseq r2, r6, r0, lsl r5 │ │ subeq r4, pc, ip, ror r1 @ │ │ - stc2l 0, cr5, [r2, #172]! @ 0xac │ │ + stc2l 0, cr5, [r2, #352]! @ 0x160 │ │ sbcseq r8, r9, r0, lsr r0 │ │ ldr r0, [pc, #3928] @ 23fe320 │ │ movw r3, #1711 @ 0x6af │ │ ldr r2, [pc, #3924] @ 23fe324 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1233700,49 +1233700,49 @@ │ │ bl 270da30 │ │ ldr r1, [fp, #-56] @ 0xffffffc8 │ │ mov r2, r0 │ │ b 23fd47c │ │ ldr r0, [pc, #3984] @ 23fe450 │ │ add r0, pc, r0 │ │ b 23fe218 │ │ - stc2l 15, cr4, [r2, #364]! @ 0x16c │ │ + stc2l 15, cr4, [r2, #544]! @ 0x220 │ │ ldr r6, [pc, #3972] @ 23fe454 │ │ add r6, pc, r6 │ │ mov r8, r6 │ │ b 23fd0fc │ │ stc2l 4, cr0, [r5, #28]! │ │ subeq r4, pc, r8, asr r0 @ │ │ stc2l 3, cr0, [r5, #860]! @ 0x35c │ │ sbcseq r7, r6, r4, asr #3 │ │ subeq r4, pc, r4 │ │ stc2l 5, cr12, [r4, #212]! @ 0xd4 │ │ @ instruction: 0x0095bef4 │ │ stc2l 4, cr12, [r4, #996]! @ 0x3e4 │ │ addseq fp, r5, r0, asr #29 │ │ umaaleq r3, pc, r0, pc @ │ │ - stc2l 11, cr0, [r2, #248]! @ 0xf8 @ │ │ + stc2l 11, cr0, [r2, #428]! @ 0x1ac @ │ │ sbcseq ip, r9, r4, ror #24 │ │ - stc2l 11, cr0, [r2, #8]! @ │ │ + stc2l 11, cr0, [r2, #188]! @ 0xbc @ │ │ sbcseq ip, r9, r0, lsr ip │ │ subeq r3, pc, ip, lsl pc @ │ │ - stc2l 13, cr2, [r3, #16]! │ │ - stc2l 12, cr2, [r3, #848]! @ 0x350 │ │ + stc2l 13, cr2, [r3, #196]! @ 0xc4 │ │ + stc2l 13, cr2, [r3, #4]! │ │ ldrsheq r1, [r3], #68 @ 0x44 │ │ eorseq fp, r4, r0, lsr #28 │ │ umaaleq r3, pc, r0, lr @ │ │ subeq r3, pc, r0, lsl #29 │ │ stc2l 3, cr12, [r4, #644]! @ 0x284 │ │ stc2l 0, cr8, [r4, #988]! @ 0x3dc │ │ - stc2l 13, cr4, [r2, #76]! @ 0x4c │ │ + stc2l 13, cr4, [r2, #256]! @ 0x100 │ │ addseq fp, r5, ip, asr #26 │ │ addseq fp, r5, r4, lsr #26 │ │ ldrsbeq r7, [r9], #192 @ 0xc0 │ │ @ instruction: 0x0095bcd0 │ │ sbcseq r7, r9, ip, ror #24 │ │ - stc2l 12, cr14, [r1, #996]! @ 0x3e4 │ │ + stc2l 13, cr14, [r1, #152]! @ 0x98 │ │ addseq fp, r5, r8, asr #24 │ │ mvn r1, #1 │ │ movw r2, #3392 @ 0xd40 │ │ add r1, r1, r0, lsl #1 │ │ movt r2, #3 │ │ cmp r1, r2 │ │ str r1, [fp, #-56] @ 0xffffffc8 │ │ @@ -1233925,28 +1233925,28 @@ │ │ bhi 23fdde0 │ │ ldr r0, [pc, #4008] @ 23fe7e0 │ │ add r0, pc, r0 │ │ add r0, r0, r1, lsl #3 │ │ vstr d9, [r0] │ │ b 23fde3c │ │ addseq fp, r5, r0, lsr #24 │ │ - stc2l 11, cr0, [r3] @ │ │ + stc2l 11, cr0, [r3, #180]! @ 0xb4 @ │ │ sub r1, r2, #1 │ │ movw r0, #4999 @ 0x1387 │ │ cmp r1, r0 │ │ str r1, [fp, #-56] @ 0xffffffc8 │ │ bhi 23fd8c4 │ │ ldr r0, [pc, #4060] @ 23fe844 │ │ str r1, [fp, #-56] @ 0xffffffc8 │ │ add r0, pc, r0 │ │ ldr r5, [fp, #28] │ │ ldr r0, [r0, r1, lsl #2] │ │ str r0, [r9] │ │ b 23fd928 │ │ - stc2l 12, cr8, [r2, #880]! @ 0x370 │ │ + stc2l 13, cr8, [r2, #36]! @ 0x24 │ │ stc2l 15, cr7, [r4, #504]! @ 0x1f8 │ │ stc2l 7, cr3, [r5, #328]! @ 0x148 │ │ stc2l 13, cr9, [r4, #572]! @ 0x23c │ │ stc2l 0, cr0, [r5, #264]! @ 0x108 │ │ subeq r3, pc, r4, ror ip @ │ │ subseq ip, r0, r8, asr #6 │ │ addseq fp, r5, r0, lsl #23 │ │ @@ -1233955,15 +1233955,15 @@ │ │ addseq fp, r5, ip, asr #22 │ │ @ instruction: 0x00951ef0 │ │ stc2l 14, cr7, [r4, #764]! @ 0x2fc │ │ stc2l 11, cr13, [r4, #532]! @ 0x214 @ │ │ subseq ip, r0, ip, ror #4 │ │ stc2l 11, cr13, [r4, #324]! @ 0x144 @ │ │ subseq ip, r0, ip, lsr r2 │ │ - stc2l 0, cr10, [r3, #748]! @ 0x2ec │ │ + stc2l 0, cr10, [r3, #928]! @ 0x3a0 │ │ ldr r0, [pc, #3964] @ 23fe848 │ │ mov r3, #2992 @ 0xbb0 │ │ ldr r2, [pc, #3960] @ 23fe84c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #3948] @ 23fe850 │ │ @@ -1234044,38 +1234044,38 @@ │ │ add r1, pc, r1 │ │ mov r2, #40 @ 0x28 │ │ mov r3, #10 │ │ bl 270d9e0 │ │ ldr r0, [pc, #3972] @ 23fe9a4 │ │ add r0, pc, r0 │ │ b 23fe218 │ │ - stc2l 0, cr10, [r3, #604]! @ 0x25c │ │ + stc2l 0, cr10, [r3, #784]! @ 0x310 │ │ eorseq fp, r4, r4, asr sl │ │ - stc2l 1, cr8, [r3, #1020]! @ 0x3fc │ │ + stc2l 2, cr8, [r3, #176]! @ 0xb0 │ │ addseq r0, r6, ip, lsr #16 │ │ stc2l 13, cr7, [r4, #600]! @ 0x258 │ │ - stc2l 10, cr14, [r1, #484]! @ 0x1e4 @ │ │ + stc2l 10, cr14, [r1, #664]! @ 0x298 @ │ │ strheq r3, [pc], #-172 @ │ │ sbcseq r1, sl, r8, asr #11 │ │ @ instruction: 0x008e66b0 │ │ subseq r7, r0, r4, lsl r3 │ │ subeq r3, pc, r8, asr #20 │ │ - stc2l 9, cr8, [r2, #174]! @ 0xae @ │ │ + stc2l 9, cr8, [r2, #264]! @ 0x108 @ │ │ stc2l 12, cr7, [r4, #732]! @ 0x2dc │ │ ldrheq r7, [r0], #-32 @ 0xffffffe0 │ │ - stc2l 9, cr8, [r2, #30]! @ │ │ + stc2l 9, cr8, [r2, #120]! @ 0x78 @ │ │ stc2l 12, cr7, [r4, #444]! @ 0x1bc │ │ subseq r7, r0, ip, lsr r2 │ │ - stc2l 0, cr8, [r3, #188]! @ 0xbc │ │ + stc2l 0, cr8, [r3, #368]! @ 0x170 │ │ stc2l 11, cr7, [r4, #956]! @ 0x3bc @ │ │ subseq r7, r0, ip, lsr #3 │ │ - vcmla.f16 d24, d2, d15, #270 │ │ + stc2l 8, cr8, [r2, #240]! @ 0xf0 │ │ stc2l 11, cr7, [r4, #444]! @ 0x1bc @ │ │ subseq r7, r0, r8, ror #2 │ │ - stc2l 7, cr8, [r2, #876]! @ 0x36c │ │ + vcmla.f16 d24, d2, d8, #270 │ │ stc2l 11, cr7, [r4, #236]! @ 0xec @ │ │ subeq r3, pc, r0, lsr r8 @ │ │ stc2l 2, cr2, [r4, #528]! @ 0x210 │ │ stc2l 10, cr7, [r4, #732]! @ 0x2dc @ │ │ @ instruction: 0x0094ccb0 │ │ stc2l 2, cr2, [r4, #272]! @ 0x110 │ │ stc2l 10, cr7, [r4, #476]! @ 0x1dc @ │ │ @@ -1234267,25 +1234267,25 @@ │ │ ldr r0, [pc, #3988] @ 23fed20 │ │ add r0, pc, r0 │ │ add r0, r0, r1, lsl #3 │ │ vstr d9, [r0] │ │ b 23fe3a0 │ │ addseq ip, r4, r8, ror ip │ │ strheq r3, [pc], #-116 @ │ │ - stc2l 13, cr9, [r3, #52]! @ 0x34 │ │ + stc2l 13, cr9, [r3, #232]! @ 0xe8 │ │ stc2l 10, cr7, [r4, #236]! @ 0xec @ │ │ addseq r6, r5, r4, ror r8 │ │ - stc2l 12, cr9, [r3, #820]! @ 0x334 │ │ + stc2l 12, cr9, [r3, #1000]! @ 0x3e8 │ │ stc2l 9, cr7, [r4, #502]! @ 0x1f6 @ │ │ addseq r6, r5, ip, lsr r8 │ │ subeq r3, pc, r8, lsr r7 @ │ │ - stc2l 6, cr8, [r2, #404]! @ 0x194 │ │ + stc2l 6, cr8, [r2, #584]! @ 0x248 │ │ stc2l 9, cr7, [r4, #382]! @ 0x17e @ │ │ strdeq r1, [lr], r8 │ │ - stc2l 6, cr8, [r2, #148]! @ 0x94 │ │ + stc2l 6, cr8, [r2, #328]! @ 0x148 │ │ stc2l 9, cr7, [r4, #254]! @ 0xfe @ │ │ addeq r1, lr, r0, asr #9 │ │ strheq r3, [pc], #-108 @ │ │ stc2l 0, cr14, [r3, #740]! @ 0x2e4 │ │ stc2l 9, cr7, [r4, #134]! @ 0x86 @ │ │ ldr r0, [pc, #3900] @ 23fed24 │ │ movw r3, #3464 @ 0xd88 │ │ @@ -1234349,15 +1234349,15 @@ │ │ vstr d8, [r0] │ │ b 23fdf34 │ │ addseq r7, r4, ip, lsl sp │ │ stc2l 0, cr14, [r3, #484]! @ 0x1e4 │ │ stc2l 9, cr7, [r4, #6]! @ │ │ addseq r7, r4, r4, ror #25 │ │ subeq r3, pc, r0, asr #12 │ │ - stc2l 5, cr8, [r2, #412]! @ 0x19c │ │ + stc2l 5, cr8, [r2, #592]! @ 0x250 │ │ vcmla.f16 , q10, , #270 │ │ ldr r0, [pc, #3676] @ 23fed54 │ │ movw r3, #3465 @ 0xd89 │ │ ldr r2, [pc, #3672] @ 23fed58 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1234376,31 +1234376,31 @@ │ │ ldr r0, [pc, #3624] @ 23fed68 │ │ add r5, pc, r5 │ │ str r1, [fp, #-56] @ 0xffffffc8 │ │ add r0, pc, r0 │ │ str r4, [r0, r1, lsl #2] │ │ b 23fe000 │ │ ldrheq r6, [r0], #-232 @ 0xffffff18 │ │ - stc2l 5, cr8, [r2, #172]! @ 0xac │ │ + stc2l 5, cr8, [r2, #352]! @ 0x160 │ │ vcmla.f16 d23, d20, d11, #270 │ │ subseq r6, r0, ip, ror lr │ │ subeq r3, pc, r0, asr #11 │ │ strheq r3, [pc], #-84 @ │ │ stc2l 10, cr11, [r4, #900]! @ 0x384 @ │ │ stc2l 8, cr7, [r4, #220]! @ 0xdc │ │ addseq fp, r5, r0, lsr #9 │ │ umullseq fp, r5, r0, r4 │ │ - stc2l 1, cr0, [r2, #120]! @ 0x78 │ │ + stc2l 1, cr0, [r2, #300]! @ 0x12c │ │ stc2l 7, cr7, [r4, #988]! @ 0x3dc │ │ sbcseq ip, r9, r0, asr #4 │ │ vcmla.f16 , q10, q7, #270 │ │ addseq r0, r6, r8, ror #4 │ │ strdeq r3, [pc], #-72 @ │ │ - stc2l 4, cr8, [r2, #204]! @ 0xcc │ │ - stc2l 14, cr5, [r2, #436]! @ 0x1b4 │ │ + stc2l 4, cr8, [r2, #384]! @ 0x180 │ │ + stc2l 14, cr5, [r2, #616]! @ 0x268 │ │ eorseq fp, r4, r8, asr #8 │ │ ldr r0, [pc, #3528] @ 23fed6c │ │ movw r3, #3471 @ 0xd8f │ │ ldr r2, [pc, #3524] @ 23fed70 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1234458,15 +1234458,15 @@ │ │ ldr r2, [pc, #3348] @ 23fed9c │ │ add r0, r0, r0, lsl #2 │ │ sub r3, r0, #5 │ │ str r3, [fp, #-56] @ 0xffffffc8 │ │ add r2, pc, r2 │ │ str r4, [r2, r1, lsl #2] │ │ b 23fe14c │ │ - stc2l 11, cr7, [r3, #660]! @ 0x294 @ │ │ + stc2l 11, cr7, [r3, #840]! @ 0x348 @ │ │ umaaleq r3, pc, r4, r4 @ │ │ subeq r3, pc, ip, ror r4 @ │ │ subeq r3, pc, r8, ror #8 │ │ subeq r3, pc, r4, ror #8 │ │ subeq r3, pc, r8, asr r4 @ │ │ ldrsheq fp, [r0], #-172 @ 0xffffff54 │ │ subeq r3, pc, r0, lsl r4 @ │ │ @@ -1234562,18 +1234562,18 @@ │ │ mov r0, #0 │ │ sub sp, fp, #48 @ 0x30 │ │ vpop {d8-d9} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ strdeq r3, [pc], #-32 @ │ │ addseq r1, r5, r8, asr #11 │ │ - stc2l 1, cr8, [r2, #996]! @ 0x3e4 │ │ + stc2l 2, cr8, [r2, #152]! @ 0x98 │ │ umaaleq r3, pc, r0, r2 @ │ │ addseq r1, r5, r8, ror #10 │ │ - stc2l 1, cr8, [r2, #756]! @ 0x2f4 │ │ + stc2l 1, cr8, [r2, #936]! @ 0x3a8 │ │ ldr r0, [pc, #3196] @ 23feed0 │ │ add r3, sp, #16 │ │ ldr r1, [pc, #3192] @ 23feed4 │ │ ldr r2, [fp, #20] │ │ add r0, pc, r0 │ │ str r2, [sp] │ │ add r1, pc, r1 │ │ @@ -1234618,21 +1234618,21 @@ │ │ mov r0, r1 │ │ b 23fe730 │ │ subeq r3, pc, r4, asr #4 │ │ addseq r1, r5, ip, lsl r5 │ │ addseq r7, r4, r8, asr #17 │ │ stc2l 4, cr7, [r4, #860]! @ 0x35c │ │ stc2l 4, cr7, [r4, #636]! @ 0x27c │ │ - stc2l 1, cr8, [r2, #116]! @ 0x74 │ │ + stc2l 1, cr8, [r2, #296]! @ 0x128 │ │ stc2l 1, cr13, [r4, #436]! @ 0x1b4 │ │ stc2l 4, cr7, [r4, #236]! @ 0xec │ │ subseq fp, r0, r8, asr r8 │ │ subeq r3, pc, r4, ror r1 @ │ │ subeq r3, pc, r4, ror #2 │ │ - stc2l 6, cr9, [r3, #764]! @ 0x2fc │ │ + stc2l 6, cr9, [r3, #944]! @ 0x3b0 │ │ stc2l 3, cr7, [r4, #972]! @ 0x3cc │ │ addseq r1, r5, ip, lsl #8 │ │ stc2l 11, cr7, [r1, #68]! @ 0x44 @ │ │ ldr r0, [pc, #2712] @ 23fede4 │ │ movw r3, #3971 @ 0xf83 │ │ ldr r2, [pc, #2708] @ 23fede8 │ │ add r0, pc, r0 │ │ @@ -1234693,15 +1234693,15 @@ │ │ add r0, pc, r0 │ │ add r0, r0, r1, lsl #3 │ │ vstr d8, [r0] │ │ b 23fe4a0 │ │ subeq r3, pc, ip, lsl r1 @ │ │ @ instruction: 0x009513d4 │ │ strdeq r3, [pc], #-0 @ │ │ - stc2l 6, cr9, [r3, #396]! @ 0x18c │ │ + stc2l 6, cr9, [r3, #576]! @ 0x240 │ │ stc2l 3, cr7, [r4, #604]! @ 0x25c │ │ stc2l 4, cr15, [r4, #296]! @ 0x128 │ │ umaaleq r3, pc, r0, r0 @ │ │ ldr r0, [pc, #2484] @ 23fee14 │ │ movw r3, #3972 @ 0xf84 │ │ ldr r2, [pc, #2480] @ 23fee18 │ │ add r0, pc, r0 │ │ @@ -1234816,15 +1234816,15 @@ │ │ bhi 23fe650 │ │ ldr r2, [pc, #2136] @ 23fee7c │ │ mov r0, #1 │ │ add r2, pc, r2 │ │ str r0, [r2, r1, lsl #2] │ │ b 23fe68c │ │ addseq pc, r5, sp, asr ip @ │ │ - stc2l 5, cr7, [r3, #828]! @ 0x33c │ │ + stc2l 5, cr7, [r3, #1008]! @ 0x3f0 │ │ stc2l 1, cr7, [r4, #572]! @ 0x23c │ │ addeq r5, lr, ip, ror #21 │ │ @ instruction: 0x0095fbfc │ │ subseq r6, r0, r4, lsr r7 │ │ stc2l 8, cr13, [r3, #588]! @ 0x24c │ │ stc2l 1, cr7, [r4, #92]! @ 0x5c │ │ ldr r0, [pc, #2088] @ 23fee80 │ │ @@ -1234949,15 +1234949,15 @@ │ │ ldr r2, [pc, #1544] @ 23fee3c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 23fe4b0 │ │ sbcseq r6, r9, r0, ror #23 │ │ - stc2l 11, cr3, [r2, #380]! @ 0x17c @ │ │ + stc2l 11, cr3, [r2, #560]! @ 0x230 @ │ │ stc2l 15, cr6, [r4, #220]! @ 0xdc │ │ sbcseq r6, r9, r4, ror #22 │ │ umullseq sl, r5, r0, fp │ │ ldr r0, [pc, #1588] @ 23fee94 │ │ movw r3, #3988 @ 0xf94 │ │ ldr r2, [pc, #1584] @ 23fee98 │ │ add r0, pc, r0 │ │ @@ -1234997,15 +1234997,15 @@ │ │ bl 270da30 │ │ mov r1, r0 │ │ b 23fe6a8 │ │ stc2l 15, cr14, [r4, #924]! @ 0x39c │ │ stc2l 14, cr6, [r4, #956]! @ 0x3bc │ │ ldrsbeq r5, [r6], #208 @ 0xd0 │ │ addseq sl, r5, r0, lsr fp │ │ - stc2l 9, cr1, [r3, #504]! @ 0x1f8 @ │ │ + stc2l 10, cr1, [r3, #164]! @ 0xa4 @ │ │ stc2l 14, cr6, [r4, #556]! @ 0x22c │ │ ldr r0, [pc, #1532] @ 23fef14 │ │ movw r3, #4147 @ 0x1033 │ │ ldr r2, [pc, #1528] @ 23fef18 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1235030,15 +1235030,15 @@ │ │ add r0, pc, r0 │ │ add r0, r0, r1, lsl #3 │ │ vstr d8, [r0] │ │ b 23fe9f0 │ │ eorseq sl, r4, ip, asr #22 │ │ sbcseq r0, r3, ip, lsl #4 │ │ addseq sl, r5, ip, asr #21 │ │ - stc2l 10, cr7, [r2, #844]! @ 0x34c @ │ │ + stc2l 11, cr7, [r2] @ │ │ stc2l 14, cr6, [r4, #204]! @ 0xcc │ │ subseq r6, r0, r4, lsr #8 │ │ subeq r2, pc, r8, ror fp @ │ │ ldrhteq sl, [r4], -r4 │ │ stc2l 14, cr6, [r4, #64]! @ 0x40 │ │ stc2l 14, cr14, [r4, #936]! @ 0x3a8 │ │ ldr r0, [pc, #1400] @ 23fef28 │ │ @@ -1235138,15 +1235138,15 @@ │ │ b 23feb80 │ │ ldrhteq sl, [r4], -r0 │ │ eorseq sl, r4, ip, lsr #19 │ │ rsbeq r6, r9, r4, lsl r9 │ │ stc2l 15, cr10, [r4, #272]! @ 0x110 │ │ stc2l 12, cr6, [r4, #588]! @ 0x24c │ │ addseq pc, r5, r1, lsl r7 @ │ │ - stc2l 0, cr7, [r3, #524]! @ 0x20c │ │ + stc2l 0, cr7, [r3, #704]! @ 0x2c0 │ │ stc2l 12, cr6, [r4, #268]! @ 0x10c │ │ ldr r0, [pc, #1084] @ 23fef88 │ │ mov r3, #4160 @ 0x1040 │ │ ldr r2, [pc, #1080] @ 23fef8c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1235278,15 +1235278,15 @@ │ │ strdeq ip, [pc], #-36 @ │ │ stc2l 0, cr1, [r4, #888]! @ 0x378 │ │ stc2l 9, cr6, [r4, #22]! @ │ │ subeq ip, pc, r8, lsr #5 │ │ addseq sl, r5, r0, ror #10 │ │ sbcseq r0, sl, ip, asr #2 │ │ sbcseq r6, r9, r4, lsl #10 │ │ - stc2l 4, cr3, [r2, #540]! @ 0x21c │ │ + stc2l 4, cr3, [r2, #720]! @ 0x2d0 │ │ stc2l 8, cr6, [r4, #380]! @ 0x17c │ │ smullseq r6, r9, r0, r4 │ │ @ instruction: 0x0095a4bc │ │ stc2l 9, cr14, [r4, #46]! @ 0x2e @ │ │ stc2l 8, cr6, [r4, #124]! @ 0x7c │ │ sbcseq r0, sl, ip, lsl #1 │ │ ldrsheq r5, [r6], #104 @ 0x68 │ │ @@ -1235295,15 +1235295,15 @@ │ │ addseq sl, r5, r4, lsr #8 │ │ strdeq r6, [r9], #-52 @ 0xffffffcc @ │ │ sbcseq r0, r6, r8, asr r8 │ │ stc2l 2, cr0, [r5, #956]! @ 0x3bc │ │ stc2l 7, cr6, [r4, #92]! @ 0x5c │ │ sbcseq r0, r6, r8, ror #15 │ │ addseq sl, r5, r4, ror r3 │ │ - stc2l 2, cr1, [r3, #240]! @ 0xf0 │ │ + stc2l 2, cr1, [r3, #420]! @ 0x1a4 │ │ stc2l 6, cr6, [r4, #812]! @ 0x32c │ │ mlaseq r4, r0, r3, sl │ │ sbcseq pc, r2, r0, asr sl @ │ │ addseq sl, r5, r4, lsl r3 │ │ stc2l 9, cr10, [r4, #66]! @ 0x42 @ │ │ stc2l 6, cr6, [r4, #476]! @ 0x1dc │ │ @ instruction: 0x0095a2dc │ │ @@ -1235325,15 +1235325,15 @@ │ │ addseq sl, r5, ip, ror r0 │ │ subeq fp, pc, ip, lsl #27 │ │ stc2l 11, cr0, [r4, #472]! @ 0x1d8 @ │ │ stc2l 3, cr6, [r4, #652]! @ 0x28c │ │ subeq fp, pc, ip, lsr sp @ │ │ @ instruction: 0x00959ff4 │ │ sbcseq r5, r9, r0, lsr #31 │ │ - stc2l 12, cr2, [r2, #252]! @ 0xfc │ │ + stc2l 12, cr2, [r2, #432]! @ 0x1b0 │ │ stc2l 0, cr6, [r4, #92]! @ 0x5c │ │ sbcseq r5, r9, r8, asr #24 │ │ addseq r9, r5, r4, ror ip │ │ stc2l 0, cr14, [r4, #828]! @ 0x33c │ │ stc2l 15, cr5, [r4, #860]! @ 0x35c │ │ sbcseq r5, r6, r8, asr #4 │ │ stc2l 10, cr12, [r3, #548]! @ 0x224 @ │ │ @@ -1235341,35 +1235341,35 @@ │ │ addseq r9, r5, ip, ror #30 │ │ rsbeq r5, r9, ip, lsr pc │ │ sbcseq r0, r6, r0, lsr #7 │ │ stc2l 14, cr15, [r4, #348]! @ 0x15c │ │ stc2l 2, cr6, [r4, #508]! @ 0x1fc │ │ sbcseq r0, r6, r0, asr r3 │ │ @ instruction: 0x00959edc │ │ - stc2l 13, cr0, [r3, #656]! @ 0x290 │ │ + stc2l 13, cr0, [r3, #836]! @ 0x344 │ │ stc2l 2, cr6, [r4, #204]! @ 0xcc │ │ ldrshteq r9, [r4], -r8 │ │ ldrheq pc, [r2], #88 @ 0x58 @ │ │ addseq r9, r5, r8, ror lr │ │ addseq r9, r5, r0, ror #28 │ │ stc2l 4, cr10, [r4, #340]! @ 0x154 │ │ stc2l 1, cr6, [r4, #684]! @ 0x2ac │ │ addseq r9, r5, r4, lsl lr │ │ addseq r9, r5, r4, lsl #28 │ │ addseq r4, r5, r8, asr #31 │ │ - stc2l 2, cr8, [r3, #468]! @ 0x1d4 │ │ + stc2l 2, cr8, [r3, #648]! @ 0x288 │ │ stc2l 15, cr5, [r4, #652]! @ 0x28c │ │ addseq r9, r5, ip, lsl #24 │ │ @ instruction: 0x00954dd8 │ │ sbcseq sl, r9, ip, asr #23 │ │ - vcmla.f16 d30, d17, d14, #270 │ │ + stc2l 8, cr14, [r1, #748]! @ 0x2ec │ │ stc2l 15, cr5, [r4, #412]! @ 0x19c │ │ ldrheq sl, [r9], #152 @ 0x98 │ │ @ instruction: 0x00959bbc │ │ - stc2l 1, cr8, [r3, #980]! @ 0x3d4 │ │ + stc2l 2, cr8, [r3, #136]! @ 0x88 │ │ stc2l 15, cr5, [r4, #140]! @ 0x8c │ │ addseq r4, r5, ip, lsr #31 │ │ ldrsbeq pc, [r9], #144 @ 0x90 @ │ │ stc2l 1, cr6, [r4, #220]! @ 0xdc │ │ stc2l 1, cr6, [r4, #108]! @ 0x6c │ │ eorseq sl, r4, ip, lsl #5 │ │ eorseq sl, r4, r8, lsl #5 │ │ @@ -1235394,48 +1235394,48 @@ │ │ subeq fp, pc, r4, ror r8 @ │ │ subeq fp, pc, r8, asr #16 │ │ stc2l 6, cr0, [r4, #152]! @ 0x98 │ │ stc2l 14, cr5, [r4, #332]! @ 0x14c │ │ subeq fp, pc, ip, ror #15 │ │ addseq r9, r5, r4, lsr #21 │ │ sbcseq r5, r9, r0, asr sl │ │ - stc2l 8, cr2, [r2, #236]! @ 0xec │ │ + vcmla.f16 q9, q1, q12, #270 │ │ stc2l 12, cr5, [r4, #76]! @ 0x4c │ │ sbcseq r5, r9, r4, asr #16 │ │ addseq r9, r5, r0, ror r8 │ │ stc2l 12, cr13, [r4, #812]! @ 0x32c │ │ stc2l 11, cr5, [r4, #844]! @ 0x34c @ │ │ ldrsheq r4, [r6], #200 @ 0xc8 │ │ addseq r9, r5, r4, asr sl │ │ smullseq pc, r5, r8, lr @ │ │ stc2l 9, cr15, [r4, #198]! @ 0xc6 @ │ │ stc2l 13, cr5, [r4, #556]! @ 0x22c │ │ sbcseq pc, r5, ip, asr lr @ │ │ addseq r9, r5, r8, ror #19 │ │ - stc2l 8, cr0, [r3, #704]! @ 0x2c0 │ │ + stc2l 8, cr0, [r3, #884]! @ 0x374 │ │ stc2l 13, cr5, [r4, #252]! @ 0xfc │ │ eorseq r9, r4, r4, lsl #20 │ │ sbcseq pc, r2, r4, asr #1 │ │ addseq r9, r5, r4, lsl #19 │ │ addseq r9, r5, ip, ror #18 │ │ stc2l 15, cr9, [r4, #388]! @ 0x184 │ │ stc2l 12, cr5, [r4, #732]! @ 0x2dc │ │ addseq r9, r5, r0, lsr #18 │ │ addseq r9, r5, r0, lsl r9 │ │ @ instruction: 0x00954ad4 │ │ - stc2l 14, cr7, [r3, #388]! @ 0x184 │ │ + stc2l 14, cr7, [r3, #568]! @ 0x238 │ │ stc2l 11, cr5, [r4, #572]! @ 0x23c @ │ │ @ instruction: 0x009597f8 │ │ addseq r4, r5, r4, asr #19 │ │ ldrsbeq sl, [r9], #100 @ 0x64 │ │ - stc2l 4, cr14, [r1, #488]! @ 0x1e8 │ │ + stc2l 4, cr14, [r1, #668]! @ 0x29c │ │ stc2l 11, cr5, [r4, #332]! @ 0x14c @ │ │ sbcseq sl, r9, r4, lsr #11 │ │ addseq r9, r5, r8, lsr #15 │ │ - stc2l 13, cr7, [r3, #900]! @ 0x384 │ │ + stc2l 14, cr7, [r3, #56]! @ 0x38 │ │ stc2l 11, cr5, [r4, #60]! @ 0x3c @ │ │ @ instruction: 0x00954ab4 │ │ rsceq r2, r6, ip, lsl #20 │ │ stc2l 13, cr13, [r4, #264]! @ 0x108 │ │ @ instruction: 0x0095e6dc │ │ │ │ 023fefd8 : │ │ @@ -1235456,16 +1235456,16 @@ │ │ add r0, pc, r0 │ │ bl 270da10 │ │ mov r0, r4 │ │ mov r1, #5 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, sl, fp, pc} │ │ - stc2l 3, cr14, [r2, #472]! @ 0x1d8 │ │ - stc2l 5, cr8, [r2, #596]! @ 0x254 │ │ + stc2l 3, cr14, [r2, #652]! @ 0x28c │ │ + stc2l 5, cr8, [r2, #776]! @ 0x308 │ │ │ │ 023ff034 : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #32 │ │ mov r3, r1 │ │ mov r1, r0 │ │ @@ -1236647,16 +1236647,16 @@ │ │ cmp r1, r6 │ │ str r5, [r8, r2, lsl #2] │ │ bcs 24002a0 │ │ mov r0, r1 │ │ b 24002bc │ │ ldrsbteq r9, [r4], -ip │ │ rsceq r6, r7, r4, ror #9 │ │ - stc2l 14, cr13, [r1, #568]! @ 0x238 │ │ - stc2l 0, cr12, [r2, #160]! @ 0xa0 │ │ + stc2l 14, cr13, [r1, #748]! @ 0x2ec │ │ + stc2l 0, cr12, [r2, #340]! @ 0x154 │ │ stc2l 4, cr8, [r1, #164]! @ 0xa4 │ │ stc2l 7, cr3, [r4, #380]! @ 0x17c │ │ ldr r0, [pc, #4004] @ 240124c │ │ mov r2, r7 │ │ movw r3, #3597 @ 0xe0d │ │ add r0, pc, r0 │ │ bl 270da30 │ │ @@ -1236693,20 +1236693,20 @@ │ │ ldr r5, [r4, r0, lsl #2] │ │ sub r2, r1, #1 │ │ cmp r2, r6 │ │ bcs 2400158 │ │ mov r0, r1 │ │ b 240017c │ │ rsceq fp, r7, r0, ror #4 │ │ - stc2l 13, cr13, [r1, #776]! @ 0x308 │ │ + stc2l 13, cr13, [r1, #956]! @ 0x3bc │ │ rsceq fp, r7, r0, lsl r2 │ │ stc2l 11, cr11, [r3, #964]! @ 0x3c4 @ │ │ stc2l 12, cr0, [r5, #644]! @ 0x284 │ │ - stc2l 11, cr3, [r2, #180]! @ 0xb4 @ │ │ - stc2l 0, cr6, [r2, #620]! @ 0x26c │ │ + stc2l 11, cr3, [r2, #360]! @ 0x168 @ │ │ + stc2l 0, cr6, [r2, #800]! @ 0x320 │ │ stc2l 10, cr3, [r1, #504]! @ 0x1f8 @ │ │ rsceq r2, r6, r0, asr #3 │ │ ldr ip, [pc, #3828] @ 2401264 │ │ mov r0, #8 │ │ ldr lr, [pc, #3824] @ 2401268 │ │ mov r8, #60 @ 0x3c │ │ ldr r6, [pc, #3820] @ 240126c │ │ @@ -1236796,15 +1236796,15 @@ │ │ b 2400b38 │ │ rsceq r1, r7, r4, ror #6 │ │ rsceq r6, r7, r0, ror r1 │ │ rsceq r2, r6, r8, asr #17 │ │ ldrdeq r2, [r6], #4 @ │ │ rsceq r2, r6, r4, asr #17 │ │ rsceq r2, r6, ip, lsr #17 │ │ - stc2l 13, cr11, [r2, #908]! @ 0x38c │ │ + stc2l 14, cr11, [r2, #64]! @ 0x40 │ │ stc2l 2, cr5, [r4, #888]! @ 0x378 │ │ rsceq r2, r6, r0, ror r0 │ │ ldr r0, [pc, #4060] @ 24014d4 │ │ movw r3, #1394 @ 0x572 │ │ ldr r2, [pc, #4056] @ 24014d8 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1236831,15 +1236831,15 @@ │ │ add r0, pc, r0 │ │ str r3, [r2, r1, lsl #2] │ │ b 2400b38 │ │ ldrshteq r8, [r4], -r8 │ │ rsceq r6, r7, r0, lsl #4 │ │ rsceq r2, r6, r0, asr #32 │ │ stc2l 3, cr13, [r4, #504]! @ 0x1f8 │ │ - stc2l 9, cr3, [r2, #154]! @ 0x9a @ │ │ + stc2l 9, cr3, [r2, #244]! @ 0xf4 @ │ │ ldrhteq r8, [r4], -r0 │ │ ldr r1, [r4] │ │ mov r3, r4 │ │ sub r2, r1, #251 @ 0xfb │ │ cmn r2, #250 @ 0xfa │ │ bhi 24009ac │ │ ldr r0, [pc, #4008] @ 240153c │ │ @@ -1236857,17 +1236857,17 @@ │ │ mov r0, r5 │ │ add r1, pc, r1 │ │ mov r2, #1 │ │ bl 270db00 │ │ ldr r0, [pc, #3956] @ 2401548 │ │ add r0, pc, r0 │ │ b 2400608 │ │ - stc2l 6, cr5, [r3, #640]! @ 0x280 │ │ + stc2l 6, cr5, [r3, #820]! @ 0x334 │ │ stc2l 2, cr5, [r4, #248]! @ 0xf8 │ │ - stc2l 12, cr11, [r2, #880]! @ 0x370 │ │ + stc2l 13, cr11, [r2, #36]! @ 0x24 │ │ ldr r1, [pc, #4088] @ 24015e4 │ │ ldr r0, [pc, #4088] @ 24015e8 │ │ add r1, pc, r1 │ │ add r0, pc, r0 │ │ str r3, [r1] │ │ mov r1, #46 @ 0x2e │ │ bl 270da00 │ │ @@ -1236879,17 +1236879,17 @@ │ │ add r0, pc, r0 │ │ b 2400b38 │ │ rsceq r1, r6, r8, lsr #31 │ │ eorseq r8, r4, r0, lsr pc │ │ rsceq r6, r7, r8, lsr r1 │ │ rsceq r1, r6, r8, ror pc │ │ stc2l 2, cr13, [r4, #712]! @ 0x2c8 │ │ - vcmla.f16 d19, d18, d1, #270 │ │ + vcmla.f16 d19, d18, d30, #270 │ │ eorseq r8, r4, r4, ror #29 │ │ - stc2l 5, cr5, [r3, #848]! @ 0x350 │ │ + stc2l 6, cr5, [r3, #4]! │ │ ldr r1, [pc, #4088] @ 240163c │ │ mov r0, r6 │ │ ldr r2, [pc, #4084] @ 2401640 │ │ mov r3, #3 │ │ add r1, pc, r1 │ │ add r2, pc, r2 │ │ bl 270e1b0 │ │ @@ -1236912,42 +1236912,42 @@ │ │ ldr r0, [pc, #4016] @ 2401650 │ │ mov r1, #21 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #4004] @ 2401654 │ │ add r0, pc, r0 │ │ b 2400b38 │ │ - stc2l 12, cr11, [r2, #192]! @ 0xc0 │ │ + stc2l 12, cr11, [r2, #372]! @ 0x174 │ │ stc2l 7, cr3, [r1, #708]! @ 0x2c4 │ │ rsceq r1, r7, r4, asr r1 │ │ rsceq r1, r7, r0, asr #2 │ │ rsceq r5, r7, ip, asr #30 │ │ rsceq r2, r6, r4, lsr #13 │ │ strhteq r1, [r6], #224 @ 0xe0 │ │ rsceq r2, r6, r0, lsr #13 │ │ rsceq r2, r6, r8, lsl #13 │ │ - stc2l 13, cr11, [r1, #792]! @ 0x318 │ │ - stc2l 7, cr3, [r2, #612]! @ 0x264 │ │ + stc2l 13, cr11, [r1, #972]! @ 0x3cc │ │ + stc2l 7, cr3, [r2, #792]! @ 0x318 │ │ stc2l 8, cr15, [r3, #348]! @ 0x15c │ │ rsceq r1, r6, ip, lsr #28 │ │ ldrhteq r8, [r4], -r4 │ │ strhteq r5, [r7], #252 @ 0xfc │ │ strdeq r1, [r6], #216 @ 0xd8 @ │ │ stc2l 1, cr13, [r4, #200]! @ 0xc8 │ │ - stc2l 7, cr3, [r2, #4]! │ │ + stc2l 7, cr3, [r2, #184]! @ 0xb8 │ │ eorseq r8, r4, r4, ror #26 │ │ - stc2l 4, cr5, [r3, #320]! @ 0x140 │ │ + stc2l 4, cr5, [r3, #500]! @ 0x1f4 │ │ stc2l 7, cr15, [r3, #700]! @ 0x2bc │ │ - stc2l 9, cr1, [r3, #66]! @ 0x42 @ │ │ + stc2l 9, cr1, [r3, #156]! @ 0x9c @ │ │ rsceq r1, r6, r4, ror #26 │ │ rsceq ip, r6, r8, lsr #3 │ │ rsceq r5, r7, r0, ror #29 │ │ rsceq r2, r6, ip, lsr #10 │ │ stc2l 14, cr7, [r1, #388]! @ 0x184 │ │ - stc2l 10, cr11, [r2, #16]! @ │ │ + stc2l 10, cr11, [r2, #196]! @ 0xc4 @ │ │ ldr r0, [r7] │ │ cmn r0, #1 │ │ ble 2400e48 │ │ ldr r0, [fp, #36] @ 0x24 │ │ mov r4, #3 │ │ ldr r1, [pc, #4032] @ 2401700 │ │ ldr r2, [pc, #4032] @ 2401704 │ │ @@ -1237050,20 +1237050,20 @@ │ │ bl 270db90 │ │ cmp r0, #0 │ │ beq 2401034 │ │ ldr r0, [pc, #4044] @ 24018a0 │ │ add r0, pc, r0 │ │ b 2400b38 │ │ mlaseq r4, ip, ip, r8 │ │ - stc2l 10, cr9, [r2, #12]! @ │ │ + stc2l 10, cr9, [r2, #192]! @ 0xc0 @ │ │ strhteq r1, [r6], #192 @ 0xc0 │ │ eorseq r8, r4, r8, lsr ip │ │ rsceq r5, r7, r0, asr #28 │ │ rsceq r5, r7, r8, lsr #28 │ │ - stc2l 9, cr9, [r2, #366]! @ 0x16e @ │ │ + stc2l 9, cr9, [r2, #456]! @ 0x1c8 @ │ │ stc2l 4, cr1, [r4, #904]! @ 0x388 │ │ ldrdeq r5, [r7], #196 @ 0xc4 @ │ │ rsceq r2, r6, ip, lsr #8 │ │ rsceq r1, r6, r4, lsr ip │ │ ldr r0, [pc, #3992] @ 24018a4 │ │ movw r3, #1973 @ 0x7b5 │ │ ldr r2, [pc, #3988] @ 24018a8 │ │ @@ -1237163,15 +1237163,15 @@ │ │ add r0, pc, r0 │ │ b 2400b38 │ │ rsceq r5, r7, r4, ror #25 │ │ rsceq sl, r7, r0, lsl #22 │ │ stc2l 4, cr11, [r3, #900]! @ 0x384 │ │ rsceq r2, r6, r0, lsl #6 │ │ stc2l 5, cr15, [r3, #248]! @ 0xf8 │ │ - stc2l 4, cr3, [r2, #84]! @ 0x54 │ │ + stc2l 4, cr3, [r2, #264]! @ 0x108 │ │ rsceq r5, r7, r8, asr fp │ │ stc2l 4, cr5, [r1, #368]! @ 0x170 │ │ stc2l 3, cr7, [r1, #108]! @ 0x6c │ │ ldr r0, [pc, #3596] @ 24018c4 │ │ movw r3, #1432 @ 0x598 │ │ ldr r2, [pc, #3592] @ 24018c8 │ │ add r0, pc, r0 │ │ @@ -1237254,40 +1237254,40 @@ │ │ ldr r2, [pc, #3424] @ 2401958 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2400964 │ │ stc2l 7, cr14, [r4, #760]! @ 0x2f8 │ │ - stc2l 2, cr3, [r2, #788]! @ 0x314 │ │ + stc2l 2, cr3, [r2, #968]! @ 0x3c8 │ │ eorseq r8, r4, r4, lsr #18 │ │ stc2l 7, cr14, [r4, #488]! @ 0x1e8 │ │ - stc2l 2, cr3, [r2, #516]! @ 0x204 │ │ + stc2l 2, cr3, [r2, #696]! @ 0x2b8 │ │ eorseq r8, r4, r0, ror #17 │ │ stc2l 2, cr11, [r3, #932]! @ 0x3a4 │ │ - stc2l 6, cr11, [r2, #192]! @ 0xc0 │ │ + stc2l 6, cr11, [r2, #372]! @ 0x174 │ │ stc2l 3, cr15, [r3, #44]! @ 0x2c │ │ stc2l 2, cr5, [r1, #364]! @ 0x16c │ │ - stc2l 2, cr3, [r2, #4]! │ │ + stc2l 2, cr3, [r2, #184]! @ 0xb8 │ │ stc2l 2, cr15, [r3, #956]! @ 0x3bc │ │ stc2l 1, cr1, [r4, #232]! @ 0xe8 │ │ stc2l 2, cr0, [r5, #968]! @ 0x3c8 │ │ - stc2l 1, cr3, [r2, #724]! @ 0x2d4 │ │ + stc2l 1, cr3, [r2, #904]! @ 0x388 │ │ stc2l 12, cr12, [r4, #236]! @ 0xec │ │ stc2l 2, cr5, [r1, #20]! │ │ - stc2l 5, cr11, [r2, #444]! @ 0x1bc │ │ - stc2l 1, cr3, [r2, #468]! @ 0x1d4 │ │ + stc2l 5, cr11, [r2, #624]! @ 0x270 │ │ + stc2l 1, cr3, [r2, #648]! @ 0x288 │ │ stc2l 0, cr1, [r4, #628]! @ 0x274 │ │ stc2l 0, cr3, [r1, #836]! @ 0x344 │ │ rsceq r1, r6, r8, lsl #16 │ │ rsceq fp, r6, ip, asr #24 │ │ rsceq r5, r7, r0, lsl #19 │ │ rsceq r0, r7, ip, lsr sl │ │ stc2l 11, cr12, [r4, #376]! @ 0x178 @ │ │ - stc2l 0, cr3, [r2, #868]! @ 0x364 │ │ + stc2l 1, cr3, [r2, #24]! │ │ ldr r0, [fp, #16] │ │ ldr r0, [r0] │ │ cmn r0, #1 │ │ ble 2400f5c │ │ ldr r0, [fp, #36] @ 0x24 │ │ mov sl, #3 │ │ ldr r1, [pc, #3308] @ 2401980 │ │ @@ -1237393,17 +1237393,17 @@ │ │ bl 270db90 │ │ cmp r0, #0 │ │ beq 24012ac │ │ ldr r0, [pc, #2904] @ 2401988 │ │ add r0, pc, r0 │ │ b 2400b38 │ │ stc2l 1, cr15, [r3, #796]! @ 0x31c │ │ - stc2l 3, cr1, [r3, #196]! @ 0xc4 │ │ + stc2l 3, cr1, [r3, #376]! @ 0x178 │ │ stc2l 0, cr5, [r1, #972]! @ 0x3cc │ │ - stc2l 0, cr3, [r2, #612]! @ 0x264 │ │ + stc2l 0, cr3, [r2, #792]! @ 0x318 │ │ stc2l 1, cr15, [r3, #540]! @ 0x21c │ │ ldr r0, [pc, #3168] @ 2401ab0 │ │ mov r1, #64 @ 0x40 │ │ mov r4, r7 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #3152] @ 2401ab4 │ │ @@ -1237414,22 +1237414,22 @@ │ │ ldr r0, [pc, #3136] @ 2401ab8 │ │ add r0, pc, r0 │ │ b 23ff6ac │ │ stc2l 11, cr2, [r4, #892]! @ 0x37c @ │ │ stc2l 15, cr0, [r4, #652]! @ 0x28c │ │ stc2l 10, cr12, [r4, #472]! @ 0x1d8 @ │ │ strhteq r5, [r7], #128 @ 0x80 │ │ - stc2l 4, cr13, [r2, #928]! @ 0x3a0 │ │ + stc2l 5, cr13, [r2, #84]! @ 0x54 │ │ stc2l 10, cr12, [r4, #216]! @ 0xd8 @ │ │ rsceq r1, r6, r4, ror #29 │ │ rsceq r5, r7, ip, ror #16 │ │ stc2l 10, cr12, [r4, #20]! @ │ │ stc2l 9, cr12, [r4, #500]! @ 0x1f4 @ │ │ rsceq r6, r6, r4, asr #25 │ │ - stc2l 2, cr1, [r3, #244]! @ 0xf4 │ │ + stc2l 2, cr1, [r3, #424]! @ 0x1a8 │ │ ldr r0, [pc, #2600] @ 24018dc │ │ movw r3, #1433 @ 0x599 │ │ ldr r2, [pc, #2596] @ 24018e0 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #2584] @ 24018e4 │ │ @@ -1237463,33 +1237463,33 @@ │ │ movw r3, #1435 @ 0x59b │ │ ldr r2, [pc, #2504] @ 2401908 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2400b0c │ │ - stc2l 6, cr5, [r2, #116]! @ 0x74 │ │ - stc2l 15, cr2, [r2, #580]! @ 0x244 │ │ + stc2l 6, cr5, [r2, #296]! @ 0x128 │ │ + stc2l 15, cr2, [r2, #760]! @ 0x2f8 │ │ ldrshteq r8, [r4], -r0 │ │ ldr r0, [pc, #2576] @ 2401974 │ │ mov r1, #64 @ 0x40 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #2564] @ 2401978 │ │ mov r2, #1 │ │ ldr r1, [fp, #16] │ │ add r0, pc, r0 │ │ bl 270db00 │ │ ldr r0, [pc, #2548] @ 240197c │ │ add r0, pc, r0 │ │ b 23ff5e0 │ │ - stc2l 4, cr1, [r2, #632]! @ 0x278 │ │ - stc2l 3, cr11, [r2, #272]! @ 0x110 │ │ + stc2l 4, cr1, [r2, #812]! @ 0x32c │ │ + stc2l 3, cr11, [r2, #452]! @ 0x1c4 │ │ stc2l 9, cr12, [r4, #332]! @ 0x14c @ │ │ - stc2l 11, cr6, [r3, #108]! @ 0x6c @ │ │ + stc2l 11, cr6, [r3, #288]! @ 0x120 @ │ │ stc2l 8, cr4, [r4, #360]! @ 0x168 │ │ rsceq fp, r6, r4, lsr #20 │ │ rsceq r0, r7, r0, asr #16 │ │ rsceq sl, r7, ip, asr #11 │ │ rsceq r5, r7, r8, ror #14 │ │ strhteq r1, [r6], #220 @ 0xdc │ │ rsceq r0, r7, r4, lsr #16 │ │ @@ -1237501,15 +1237501,15 @@ │ │ smlaleq fp, r6, r0, r9 │ │ rsceq sl, r7, r0, lsr r5 │ │ stc2l 13, cr0, [r4, #604]! @ 0x25c │ │ vcmla.f16 q14, q2, q13, #270 │ │ rsceq r5, r7, r8, lsr #13 │ │ stc2l 13, cr0, [r4, #396]! @ 0x18c │ │ stc2l 8, cr12, [r4, #216]! @ 0xd8 │ │ - stc2l 1, cr11, [r2, #896]! @ 0x380 │ │ + stc2l 2, cr11, [r2, #52]! @ 0x34 │ │ rsceq sl, r7, r0, lsl #10 │ │ strdeq fp, [r6], #132 @ 0x84 @ │ │ rsceq r5, r7, r4, asr #12 │ │ rsceq r1, r6, r4, lsr #9 │ │ rsceq r1, r6, r4, lsl #25 │ │ rsceq r6, r6, r0, lsr #21 │ │ stc2l 7, cr12, [r4, #776]! @ 0x308 │ │ @@ -1237654,33 +1237654,33 @@ │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #2224] @ 2401af0 │ │ add r0, pc, r0 │ │ b 2400b38 │ │ stc2l 11, cr0, [r4, #876]! @ 0x36c @ │ │ smlaleq fp, r6, ip, r7 │ │ - stc2l 1, cr13, [r2, #80]! @ 0x50 │ │ + stc2l 1, cr13, [r2, #260]! @ 0x104 │ │ rsceq fp, r6, r4, asr r7 │ │ - stc2l 0, cr13, [r2, #912]! @ 0x390 │ │ + stc2l 1, cr13, [r2, #68]! @ 0x44 │ │ rsceq fp, r6, r0, lsr #14 │ │ stc2l 5, cr12, [r4, #1012]! @ 0x3f4 │ │ rsceq fp, r6, r4, ror #13 │ │ smlaleq fp, r6, r4, r6 │ │ strhteq r0, [r7], #64 @ 0x40 │ │ rsceq sl, r7, ip, lsr r2 │ │ ldrdeq r5, [r7], #56 @ 0x38 @ │ │ rsceq r1, r6, ip, lsr #20 │ │ smlaleq r0, r7, r4, r4 │ │ rsceq sl, r7, r4, lsl r2 │ │ rsceq sl, r7, ip, asr #4 │ │ rsceq r0, r7, ip, asr r4 │ │ ldrdeq r1, [r6], #28 @ │ │ strhteq sl, [r7], #16 │ │ - stc2l 10, cr2, [r3, #404]! @ 0x194 @ │ │ - stc2l 10, cr2, [r2, #628]! @ 0x274 @ │ │ + stc2l 10, cr2, [r3, #584]! @ 0x248 @ │ │ + stc2l 10, cr2, [r2, #808]! @ 0x328 @ │ │ ldrshteq r8, [r4], -r4 │ │ rsceq r1, r6, r0, lsr r1 │ │ rsceq r1, r6, r4, lsr #2 │ │ strhteq r5, [r7], #44 @ 0x2c │ │ stc2l 9, cr2, [r1, #364]! @ 0x16c @ │ │ ldr r0, [fp, #16] │ │ ldr r0, [r0] │ │ @@ -1237842,18 +1237842,18 @@ │ │ ldr r4, [pc, #1540] @ 2401b2c │ │ ldr r4, [pc, r4] │ │ b 2401590 │ │ stc2l 9, cr0, [r4, #14]! @ │ │ stc2l 3, cr12, [r4, #872]! @ 0x368 │ │ rsceq r0, r7, ip, ror #5 │ │ stc2l 1, cr7, [r1, #756]! @ 0x2f4 │ │ - stc2l 15, cr4, [r2, #900]! @ 0x384 │ │ - stc2l 9, cr2, [r2, #170]! @ 0xaa @ │ │ + stc2l 0, cr5, [r2, #56]! @ 0x38 │ │ + stc2l 9, cr2, [r2, #260]! @ 0x104 @ │ │ ldrhteq r7, [r4], -r4 │ │ - stc2l 14, cr0, [r2, #408]! @ 0x198 │ │ + stc2l 14, cr0, [r2, #588]! @ 0x24c │ │ ldr r0, [pc, #1500] @ 2401b30 │ │ movw r3, #3170 @ 0xc62 │ │ ldr r2, [pc, #1496] @ 2401b34 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #1484] @ 2401b38 │ │ @@ -1237885,15 +1237885,15 @@ │ │ mov r1, r2 │ │ ldr r0, [fp, #20] │ │ bl 270de00 │ │ ldr r0, [pc, #1444] @ 2401b84 │ │ add r0, pc, r0 │ │ b 2400b38 │ │ rsceq fp, r6, r0, lsr #8 │ │ - stc2l 14, cr14, [r1, #500]! @ 0x1f4 │ │ + stc2l 14, cr14, [r1, #680]! @ 0x2a8 │ │ stc2l 1, cr9, [r1, #988]! @ 0x3dc │ │ stc2l 2, cr4, [r4, #88]! @ 0x58 │ │ ldr r0, [pc, #1100] @ 2401a48 │ │ movw r5, #4999 @ 0x1387 │ │ ldr r1, [pc, #1096] @ 2401a4c │ │ add r0, pc, r0 │ │ ldr r1, [pc, r1] │ │ @@ -1237906,20 +1237906,20 @@ │ │ bhi 240171c │ │ ldr r0, [pc, #1060] @ 2401a50 │ │ add r0, pc, r0 │ │ str r4, [r0, r1, lsl #2] │ │ ldr r4, [pc, #1052] @ 2401a54 │ │ ldr r4, [pc, r4] │ │ b 2401760 │ │ - stc2l 12, cr10, [r2, #608]! @ 0x260 │ │ + stc2l 12, cr10, [r2, #788]! @ 0x314 │ │ strhteq r9, [r7], #248 @ 0xf8 │ │ stc2l 14, cr9, [r4, #928]! @ 0x3a0 │ │ - vcmla.f16 d18, d18, d9, #270 │ │ + stc2l 8, cr2, [r2, #728]! @ 0x2d8 │ │ rsceq r9, r7, ip, lsl pc │ │ - stc2l 13, cr0, [r2, #316]! @ 0x13c │ │ + stc2l 13, cr0, [r2, #496]! @ 0x1f0 │ │ stc2l 9, cr14, [r3, #118]! @ 0x76 @ │ │ ldr r0, [pc, #1260] @ 2401b4c │ │ movw r3, #3171 @ 0xc63 │ │ ldr r2, [pc, #1256] @ 2401b50 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1237956,15 +1237956,15 @@ │ │ ldr r2, [pc, #1160] @ 2401b78 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 24015b4 │ │ stc2l 12, cr13, [r4, #776]! @ 0x308 │ │ - stc2l 11, cr10, [r2, #592]! @ 0x250 @ │ │ + stc2l 11, cr10, [r2, #772]! @ 0x304 @ │ │ rsceq r9, r7, r8, asr #28 │ │ rsceq r9, r7, ip, lsr #28 │ │ rsceq r9, r7, r4, ror #28 │ │ rsceq r0, r7, r4, lsl #1 │ │ rsceq fp, r6, r8, asr r2 │ │ ldr r0, [pc, #820] @ 2401a58 │ │ movw r3, #2612 @ 0xa34 │ │ @@ -1238007,18 +1238007,18 @@ │ │ rsceq r0, r6, r0, lsl lr │ │ stc2l 6, cr6, [r1, #492]! @ 0x1ec │ │ mlaseq r4, r4, sp, r7 │ │ ldrdeq r1, [r6], #20 @ │ │ eorseq r7, r4, r0, lsl #27 │ │ rsceq r1, r6, r4, asr #11 │ │ rsceq r0, r7, ip, lsr #32 │ │ - stc2l 10, cr10, [r2, #720]! @ 0x2d0 @ │ │ + stc2l 10, cr10, [r2, #900]! @ 0x384 @ │ │ ldrdeq r9, [r7], #212 @ 0xd4 @ │ │ rsceq r9, r7, r8, asr #27 │ │ - vcmla.f16 q14, , , #270 │ │ + stc2l 9, cr12, [r1, #40]! @ 0x28 @ │ │ strdeq r4, [r7], #236 @ 0xec @ │ │ rsceq r9, r7, r4, lsl #27 │ │ stc2l 14, cr6, [r1, #576]! @ 0x240 │ │ rsceq r9, r7, r0, lsr sp │ │ rsceq r9, r7, ip, ror #26 │ │ rsceq r9, r7, r8, lsr #26 │ │ ldr r0, [pc, #628] @ 2401a74 │ │ @@ -1238059,30 +1238059,30 @@ │ │ movw r3, #2615 @ 0xa37 │ │ ldr r2, [pc, #528] @ 2401aa0 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2401784 │ │ - stc2l 10, cr10, [r2, #96]! @ 0x60 @ │ │ + stc2l 10, cr10, [r2, #276]! @ 0x114 @ │ │ stc2l 12, cr9, [r4, #164]! @ 0xa4 │ │ stc2l 15, cr11, [r4, #1016]! @ 0x3f8 │ │ - vcmla.f16 d26, d18, d24, #270 │ │ + stc2l 8, cr10, [r2, #852]! @ 0x354 │ │ rsceq r9, r7, r8, asr #23 │ │ stc2l 10, cr9, [r4, #992]! @ 0x3e0 @ │ │ - stc2l 4, cr2, [r2, #612]! @ 0x264 │ │ - stc2l 9, cr0, [r2, #238]! @ 0xee @ │ │ + stc2l 4, cr2, [r2, #792]! @ 0x318 │ │ + stc2l 9, cr0, [r2, #328]! @ 0x148 @ │ │ stc2l 12, cr6, [r1, #564]! @ 0x234 │ │ stc2l 10, cr9, [r4, #500]! @ 0x1f4 @ │ │ stc2l 14, cr11, [r4, #328]! @ 0x148 │ │ strdeq r0, [r6], #172 @ 0xac @ │ │ rsceq r9, r7, r0, ror #21 │ │ ldrdeq r1, [r6], #44 @ 0x2c @ │ │ rsceq r9, r7, r4, lsl #22 │ │ - stc2l 5, cr12, [r2, #32]! │ │ + stc2l 5, cr12, [r2, #212]! @ 0xd4 │ │ stc2l 10, cr11, [r4, #344]! @ 0x158 @ │ │ rsceq r0, r6, r0, lsl #30 │ │ strdeq r0, [r6], #100 @ 0x64 @ │ │ rsceq r9, r7, r4, lsl r7 │ │ rsceq r6, r6, r8, ror #1 │ │ stc2l 10, cr11, [r4, #100]! @ 0x64 @ │ │ stc2l 10, cr11, [r4, #56]! @ 0x38 @ │ │ @@ -1238094,70 +1238094,70 @@ │ │ rsceq r4, r7, r8, asr ip │ │ stc2l 11, cr6, [r1, #884]! @ 0x374 @ │ │ strdeq fp, [r6], #4 @ │ │ rsceq r0, r6, r0, lsr #25 │ │ rsceq r9, r7, r4, lsl #25 │ │ rsceq r1, r6, r4, lsl #9 │ │ rsceq r9, r7, ip, lsr #25 │ │ - vcmla.f16 q14, q1, q6, #270 │ │ + stc2l 8, cr12, [r2, #484]! @ 0x1e4 │ │ stc2l 13, cr11, [r4, #616]! @ 0x268 │ │ rsceq r1, r6, r8, asr #4 │ │ rsceq r0, r6, ip, lsr sl │ │ rsceq r9, r7, ip, asr sl │ │ smlaleq r6, r6, r0, r2 @ │ │ stc2l 13, cr11, [r4, #388]! @ 0x184 │ │ stc2l 13, cr11, [r4, #344]! @ 0x158 │ │ rsceq r6, r6, r4, lsr #32 │ │ strdeq r0, [r6], #152 @ 0x98 @ │ │ stc2l 2, cr0, [r4, #284]! @ 0x11c │ │ stc2l 13, cr11, [r4, #104]! @ 0x68 │ │ rsceq pc, r6, ip, asr #29 │ │ rsceq r4, r7, r0, lsl #28 │ │ stc2l 6, cr14, [r3, #364]! @ 0x16c │ │ - stc2l 4, cr2, [r3, #916]! @ 0x394 │ │ - stc2l 5, cr2, [r2, #116]! @ 0x74 │ │ + stc2l 5, cr2, [r3, #72]! @ 0x48 │ │ + stc2l 5, cr2, [r2, #296]! @ 0x128 │ │ eorseq r7, r4, r4, ror fp │ │ - stc2l 15, cr1, [r3, #456]! @ 0x1c8 │ │ - stc2l 15, cr1, [r2, #548]! @ 0x224 │ │ + stc2l 15, cr1, [r3, #636]! @ 0x27c │ │ + stc2l 15, cr1, [r2, #728]! @ 0x2d8 │ │ stc2l 0, cr14, [r3, #424]! @ 0x1a8 │ │ stc2l 7, cr13, [r4, #456]! @ 0x1c8 │ │ - stc2l 6, cr10, [r2, #272]! @ 0x110 │ │ + stc2l 6, cr10, [r2, #452]! @ 0x1c4 │ │ stc2l 9, cr3, [r4, #508]! @ 0x1fc @ │ │ strdeq r9, [r7], #132 @ 0x84 @ │ │ ldrdeq r9, [r7], #136 @ 0x88 @ │ │ rsceq r9, r7, r0, lsl r9 │ │ rsceq pc, r6, r0, lsr fp @ │ │ rsceq sl, r6, r4, lsl #26 │ │ strhteq r0, [r6], #136 @ 0x88 │ │ stc2l 1, cr6, [r1, #140]! @ 0x8c │ │ eorseq r7, r4, ip, lsr r8 │ │ rsceq r0, r6, ip, ror ip │ │ eorseq r7, r4, r8, lsr #16 │ │ rsceq r1, r6, ip, rrx │ │ ldrdeq pc, [r6], #164 @ 0xa4 @ │ │ - stc2l 5, cr10, [r2, #368]! @ 0x170 │ │ + stc2l 5, cr10, [r2, #548]! @ 0x224 │ │ rsceq r9, r7, ip, ror r8 │ │ rsceq r9, r7, r0, ror r8 │ │ rsceq sl, r6, r0, asr ip │ │ - stc2l 3, cr12, [r1, #540]! @ 0x21c │ │ + stc2l 3, cr12, [r1, #720]! @ 0x2d0 │ │ smlaleq r4, r7, ip, r9 │ │ rsceq r9, r7, r0, lsr #16 │ │ rsceq r4, r7, r0, lsl #19 │ │ rsceq r9, r7, ip, asr #15 │ │ rsceq r9, r7, r8, lsl #16 │ │ rsceq r9, r7, r4, asr #15 │ │ rsceq r0, r6, r4, lsl r3 │ │ ldrshteq r7, [r4], -r4 │ │ rsceq r9, r7, ip, lsr #5 │ │ eorseq r7, r4, ip, ror r2 │ │ rsceq r9, r7, r4, ror #5 │ │ - stc2l 14, cr9, [r2, #480]! @ 0x1e0 │ │ + stc2l 14, cr9, [r2, #660]! @ 0x294 │ │ eorseq r7, r4, r4, lsl r1 │ │ - stc2l 10, cr1, [r3, #604]! @ 0x25c @ │ │ - stc2l 10, cr1, [r2, #436]! @ 0x1b4 @ │ │ + stc2l 10, cr1, [r3, #784]! @ 0x310 @ │ │ + stc2l 10, cr1, [r2, #616]! @ 0x268 @ │ │ strdeq r9, [r7], #12 @ │ │ stc2l 5, cr1, [r4, #572]! @ 0x23c │ │ stc2l 3, cr3, [r4, #376]! @ 0x178 │ │ smlaleq sl, r6, r8, r6 │ │ eorseq r7, r4, r4, ror r1 │ │ rsceq r9, r7, r0, ror r2 │ │ smlaleq pc, r6, r4, r4 @ │ │ @@ -1238176,46 +1238176,46 @@ │ │ stc2l 14, cr8, [r4, #68]! @ 0x44 │ │ stc2l 1, cr11, [r4, #920]! @ 0x398 │ │ ldrdeq sl, [r6], #44 @ 0x2c @ │ │ rsceq pc, r5, r8, lsl #29 │ │ rsceq r8, r7, r8, ror #28 │ │ rsceq r0, r6, r8, ror #12 │ │ smlaleq r8, r7, r0, lr │ │ - stc2l 11, cr11, [r2, #752]! @ 0x2f0 @ │ │ + stc2l 11, cr11, [r2, #932]! @ 0x3a4 @ │ │ stc2l 1, cr11, [r4, #40]! @ 0x28 │ │ strhteq r0, [r6], #88 @ 0x58 │ │ rsceq pc, r5, ip, lsr #27 │ │ rsceq r8, r7, r8, asr #27 │ │ rsceq r5, r6, r0, ror r4 │ │ stc2l 0, cr11, [r4, #820]! @ 0x334 │ │ stc2l 0, cr11, [r4, #776]! @ 0x308 │ │ smlaleq r5, r6, r0, r3 │ │ rsceq pc, r5, r4, ror #26 │ │ stc2l 5, cr15, [r3, #700]! @ 0x2bc │ │ stc2l 0, cr11, [r4, #520]! @ 0x208 │ │ rsceq pc, r6, ip, lsr #1 │ │ rsceq r3, r7, r0, ror #31 │ │ stc2l 0, cr3, [r4, #504]! @ 0x1f8 │ │ - stc2l 0, cr2, [r3, #520]! @ 0x208 │ │ - stc2l 0, cr2, [r2, #612]! @ 0x264 │ │ + stc2l 0, cr2, [r3, #700]! @ 0x2bc │ │ + stc2l 0, cr2, [r2, #792]! @ 0x318 │ │ stc2l 1, cr14, [r3, #488]! @ 0x1e8 │ │ rsceq r9, r7, ip, ror #10 │ │ rsceq r0, r6, r8, lsl #11 │ │ rsceq sl, r6, r8, lsr #19 │ │ eorseq r7, r4, r4, lsr #9 │ │ ldrshteq r7, [r4], -r4 │ │ rsceq r0, r6, r8, asr #10 │ │ rsceq r9, r7, r8, ror #10 │ │ - stc2l 1, cr10, [r2, #32]! │ │ + stc2l 1, cr10, [r2, #212]! @ 0xd4 │ │ eorseq r7, r4, r4, lsr #7 │ │ - stc2l 13, cr1, [r3, #156]! @ 0x9c │ │ - stc2l 12, cr1, [r2, #1012]! @ 0x3f4 │ │ + stc2l 13, cr1, [r3, #336]! @ 0x150 │ │ + stc2l 13, cr1, [r2, #168]! @ 0xa8 │ │ rsceq r9, r7, ip, lsl #7 │ │ stc2l 8, cr1, [r4, #124]! @ 0x7c │ │ - stc2l 0, cr10, [r2, #688]! @ 0x2b0 │ │ + stc2l 0, cr10, [r2, #868]! @ 0x364 │ │ rsceq sl, r6, r0, lsr #18 │ │ eorseq r7, r4, r8, lsr r4 │ │ strdeq r9, [r7], #72 @ 0x48 @ │ │ rsceq pc, r6, ip, lsl r7 @ │ │ eorseq r7, r4, r0, asr #8 │ │ rsceq r0, r6, r0, lsl #17 │ │ eorseq r7, r4, r8, ror #7 │ │ @@ -1238230,29 +1238230,29 @@ │ │ stc2l 15, cr8, [r4, #900]! @ 0x384 │ │ stc2l 3, cr11, [r4, #728]! @ 0x2d8 │ │ rsceq sl, r6, ip, lsr #9 │ │ rsceq r0, r6, r8, asr r0 │ │ rsceq r9, r7, r8, lsr r0 │ │ rsceq r0, r6, r8, lsr r8 │ │ rsceq r9, r7, r0, rrx │ │ - stc2l 13, cr11, [r2, #368]! @ 0x170 │ │ + stc2l 13, cr11, [r2, #548]! @ 0x224 │ │ stc2l 2, cr11, [r4, #680]! @ 0x2a8 │ │ rsceq r0, r6, r8, asr r7 │ │ rsceq pc, r5, ip, asr #30 │ │ rsceq r8, r7, r8, ror #30 │ │ rsceq r5, r6, r0, asr #12 │ │ stc2l 2, cr11, [r4, #436]! @ 0x1b4 │ │ stc2l 2, cr11, [r4, #392]! @ 0x188 │ │ rsceq r5, r6, r0, lsr r5 │ │ rsceq pc, r5, r4, lsl #30 │ │ stc2l 7, cr15, [r3, #316]! @ 0x13c │ │ stc2l 2, cr11, [r4, #136]! @ 0x88 │ │ rsceq pc, r6, ip, ror r2 @ │ │ strhteq r4, [r7], #16 │ │ - stc2l 13, cr9, [r2, #48]! @ 0x30 │ │ + stc2l 13, cr9, [r2, #228]! @ 0xe4 │ │ │ │ 02401b88 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ beq 2401ba4 │ │ @@ -1238460,15 +1238460,15 @@ │ │ mov r0, r6 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ vcmla.f16 , , , #270 │ │ - stc2l 4, cr9, [r2, #448]! @ 0x1c0 │ │ + stc2l 4, cr9, [r2, #628]! @ 0x274 │ │ eorseq r6, r4, r8, lsl #14 │ │ │ │ 02401eac : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #48 @ 0x30 │ │ mov r2, #0 │ │ @@ -1238571,20 +1238571,20 @@ │ │ bl 270d220 │ │ ldr r0, [pc, #36] @ 2402054 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, fp, pc} │ │ - stc2l 3, cr7, [r2, #188]! @ 0xbc │ │ + stc2l 3, cr7, [r2, #368]! @ 0x170 │ │ ldrdeq pc, [r5], #92 @ 0x5c @ │ │ eorseq r6, r4, r4, ror #10 │ │ rsceq r3, r7, ip, ror #14 │ │ rsceq r3, r7, r4, asr r7 │ │ - stc2l 2, cr7, [r2, #892]! @ 0x37c │ │ + stc2l 3, cr7, [r2, #48]! @ 0x30 │ │ │ │ 02402058 : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #48 @ 0x30 │ │ mov r3, #0 │ │ str r2, [sp, #40] @ 0x28 │ │ @@ -1238966,26 +1238966,26 @@ │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ eorseq r9, r3, r0, asr #3 │ │ eorseq r9, r3, r4, ror #2 │ │ eorseq r9, r3, r8, ror #1 │ │ stc2l 11, cr10, [r3, #468]! @ 0x1d4 @ │ │ - stc2l 15, cr6, [r2, #456]! @ 0x1c8 │ │ + stc2l 15, cr6, [r2, #636]! @ 0x27c │ │ stc2l 15, cr7, [r3, #708]! @ 0x2c4 │ │ stc2l 13, cr15, [r0, #376]! @ 0x178 │ │ stc2l 13, cr15, [r0, #200]! @ 0xc8 │ │ stc2l 15, cr7, [r3, #260]! @ 0x104 │ │ stc2l 12, cr15, [r0, #536]! @ 0x218 │ │ stc2l 10, cr6, [r3, #20]! @ │ │ - stc2l 6, cr4, [r3, #192]! @ 0xc0 │ │ + stc2l 6, cr4, [r3, #372]! @ 0x174 │ │ stc2l 14, cr7, [r3, #596]! @ 0x254 │ │ stc2l 14, cr7, [r3, #420]! @ 0x1a4 │ │ stc2l 12, cr15, [r0, #280]! @ 0x118 │ │ - stc2l 15, cr8, [r1, #492]! @ 0x1ec │ │ + stc2l 15, cr8, [r1, #672]! @ 0x2a0 │ │ vcmla.f16 , , , #270 │ │ vcmla.f16 d16, d17, d20, #270 │ │ │ │ 0240268c : │ │ push {fp, lr} │ │ mov fp, sp │ │ bl 2703110 │ │ @@ -1239118,43 +1239118,43 @@ │ │ bl 270ac10 │ │ ldr r0, [pc, #128] @ 2402914 │ │ mov r1, #1 │ │ add r0, pc, r0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, lr} │ │ b 270e250 │ │ - stc2l 12, cr10, [r2, #1008]! @ 0x3f0 │ │ + stc2l 13, cr10, [r2, #164]! @ 0xa4 │ │ ldrsbteq r5, [r3], -r0 │ │ ldrhteq r5, [r3], -ip │ │ - stc2l 12, cr8, [r2, #144]! @ 0x90 │ │ - stc2l 14, cr4, [r2, #700]! @ 0x2bc │ │ + stc2l 12, cr8, [r2, #324]! @ 0x144 │ │ + stc2l 14, cr4, [r2, #880]! @ 0x370 │ │ mlaseq r3, r4, ip, r8 │ │ eorseq r5, r3, r0, lsl #13 │ │ eorseq r8, r3, r8, ror ip │ │ eorseq r8, r3, r0, asr ip │ │ stc2l 12, cr11, [r4, #672]! @ 0x2a0 │ │ stc2l 12, cr11, [r4, #680]! @ 0x2a8 │ │ vcmla.f16 q14, , q12, #270 │ │ stc2l 9, cr12, [r3, #140]! @ 0x8c @ │ │ eorseq r8, r3, r0, lsl #24 │ │ - stc2l 11, cr12, [r2, #704]! @ 0x2c0 @ │ │ - stc2l 13, cr2, [r2, #692]! @ 0x2b4 │ │ - stc2l 12, cr14, [r1, #448]! @ 0x1c0 │ │ + stc2l 11, cr12, [r2, #884]! @ 0x374 @ │ │ + stc2l 13, cr2, [r2, #872]! @ 0x368 │ │ + stc2l 12, cr14, [r1, #628]! @ 0x274 │ │ eorseq r8, r3, ip, asr #23 │ │ eorseq r8, r3, r4, asr #23 │ │ ldrhteq r8, [r3], -ip │ │ eorseq r8, r3, ip, lsr #23 │ │ - stc2l 3, cr4, [r3, #12]! │ │ + stc2l 3, cr4, [r3, #192]! @ 0xc0 │ │ stc2l 14, cr3, [r4, #164]! @ 0xa4 │ │ - stc2l 7, cr0, [r2, #132]! @ 0x84 │ │ + stc2l 7, cr0, [r2, #312]! @ 0x138 │ │ stc2l 6, cr10, [r3, #808]! @ 0x328 │ │ - stc2l 6, cr0, [r3, #928]! @ 0x3a0 │ │ + stc2l 7, cr0, [r3, #84]! @ 0x54 │ │ stc2l 15, cr1, [r4, #740]! @ 0x2e4 │ │ - stc2l 10, cr6, [r2, #808]! @ 0x328 @ │ │ - stc2l 10, cr6, [r2, #804]! @ 0x324 @ │ │ + stc2l 10, cr6, [r2, #988]! @ 0x3dc @ │ │ + stc2l 10, cr6, [r2, #984]! @ 0x3d8 @ │ │ │ │ 02402918 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ ldr r0, [pc, #164] @ 24029cc │ │ mov r5, #1 │ │ ldr r0, [pc, r0] │ │ @@ -1239415,18 +1239415,18 @@ │ │ vld1.32 {d16-d17}, [r3]! │ │ subs r1, r1, #4 │ │ vst1.32 {d16-d17}, [r2]! │ │ bne 2402d04 │ │ cmp r0, ip │ │ bne 2402c70 │ │ b 2402c94 │ │ - stc2l 9, cr4, [r2, #350]! @ 0x15e @ │ │ - stc2l 6, cr8, [r2, #548]! @ 0x224 │ │ - stc2l 5, cr12, [r2, #852]! @ 0x354 │ │ - stc2l 8, cr4, [r2, #1004]! @ 0x3ec │ │ + stc2l 9, cr4, [r2, #440]! @ 0x1b8 @ │ │ + stc2l 6, cr8, [r2, #728]! @ 0x2d8 │ │ + stc2l 6, cr12, [r2, #8]! │ │ + stc2l 9, cr4, [r2, #80]! @ 0x50 @ │ │ │ │ 02402d30 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r0 │ │ bl 270ce80 │ │ mov r4, #0 │ │ @@ -1239490,20 +1239490,20 @@ │ │ mov r1, #5 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, r4 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ vcmla.f16 d23, d4, d24, #270 │ │ stc2l 15, cr9, [r3, #280]! @ 0x118 │ │ - stc2l 1, cr0, [r2, #164]! @ 0xa4 │ │ - stc2l 6, cr2, [r2, #428]! @ 0x1ac │ │ + stc2l 1, cr0, [r2, #344]! @ 0x158 │ │ + stc2l 6, cr2, [r2, #608]! @ 0x260 │ │ stc2l 0, cr2, [r1, #592]! @ 0x250 │ │ - stc2l 0, cr0, [r2, #996]! @ 0x3e4 │ │ + stc2l 1, cr0, [r2, #152]! @ 0x98 │ │ stc2l 10, cr6, [r1, #524]! @ 0x20c @ │ │ - stc2l 1, cr0, [r2, #372]! @ 0x174 │ │ + stc2l 1, cr0, [r2, #552]! @ 0x228 │ │ stc2l 12, cr5, [r4, #188]! @ 0xbc │ │ stc2l 7, cr7, [r4, #352]! @ 0x160 │ │ │ │ 02402e64 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #328 @ 0x148 │ │ @@ -1239592,23 +1239592,23 @@ │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ vcmla.f16 d20, d17, d27, #270 │ │ - stc2l 5, cr12, [r1, #932]! @ 0x3a4 │ │ + stc2l 6, cr12, [r1, #88]! @ 0x58 │ │ eorseq r5, r4, r0, lsr r7 │ │ stc2l 9, cr1, [r4, #128]! @ 0x80 @ │ │ eorseq r5, r4, r4, lsl #14 │ │ stc2l 7, cr3, [r4, #268]! @ 0x10c │ │ eorseq r5, r4, r8, asr #13 │ │ vcmla.f16 , q10, q14, #270 │ │ eorseq r5, r4, r8, lsr #13 │ │ - stc2l 1, cr14, [r1, #752]! @ 0x2f0 │ │ + stc2l 1, cr14, [r1, #932]! @ 0x3a4 │ │ rsceq r8, r7, ip, lsl #19 │ │ stc2l 15, cr3, [r1, #204]! @ 0xcc │ │ stc2l 7, cr4, [r1, #508]! @ 0x1fc │ │ │ │ 02403004 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ @@ -1239771,21 +1239771,21 @@ │ │ bl 270da10 │ │ mov r0, r4 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ stc2l 13, cr15, [r0, #68]! @ 0x44 │ │ - stc2l 3, cr8, [r1, #884]! @ 0x374 │ │ - stc2l 13, cr15, [r1, #372]! @ 0x174 │ │ - stc2l 1, cr12, [r2, #852]! @ 0x354 │ │ + stc2l 4, cr8, [r1, #40]! @ 0x28 │ │ + stc2l 13, cr15, [r1, #552]! @ 0x228 │ │ + stc2l 2, cr12, [r2, #8]! │ │ stc2l 13, cr9, [r3, #52]! @ 0x34 │ │ - stc2l 3, cr2, [r2, #424]! @ 0x1a8 │ │ - stc2l 12, cr15, [r1, #708]! @ 0x2c4 │ │ - stc2l 1, cr12, [r2, #244]! @ 0xf4 │ │ + stc2l 3, cr2, [r2, #604]! @ 0x25c │ │ + stc2l 12, cr15, [r1, #888]! @ 0x378 │ │ + stc2l 1, cr12, [r2, #424]! @ 0x1a8 │ │ │ │ 0240329c : │ │ push {fp, lr} │ │ mov fp, sp │ │ mov r3, r2 │ │ mov r2, r1 │ │ mov r1, r0 │ │ @@ -1239887,19 +1239887,19 @@ │ │ ldr r0, [pc, #36] @ 2403448 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - stc2l 9, cr1, [r3, #310]! @ 0x136 @ │ │ - stc2l 13, cr9, [r1, #396]! @ 0x18c │ │ - stc2l 10, cr15, [r1, #1012]! @ 0x3f4 @ │ │ + stc2l 9, cr1, [r3, #400]! @ 0x190 @ │ │ + stc2l 13, cr9, [r1, #576]! @ 0x240 │ │ + stc2l 11, cr15, [r1, #168]! @ 0xa8 @ │ │ stc2l 10, cr5, [r3, #60]! @ 0x3c @ │ │ - stc2l 8, cr1, [r3, #492]! @ 0x1ec │ │ + vcmla.f16 d17, d19, d24, #270 │ │ │ │ 0240344c : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #528] @ 2403670 │ │ ldr r0, [pc, r0] │ │ @@ -1240042,17 +1240042,17 @@ │ │ eorseq r7, r3, r8, lsr #30 │ │ eorseq r7, r3, r8, lsl #30 │ │ ldrshteq r7, [r3], -r8 │ │ stc2l 2, cr4, [r1, #24]! │ │ ldrshteq r7, [r3], -r0 │ │ ldrsbteq r7, [r3], -r0 │ │ stc2l 3, cr1, [r4] │ │ - stc2l 15, cr7, [r1, #792]! @ 0x318 │ │ - stc2l 15, cr7, [r1, #376]! @ 0x178 │ │ - stc2l 15, cr7, [r1, #232]! @ 0xe8 │ │ + stc2l 15, cr7, [r1, #972]! @ 0x3cc │ │ + stc2l 15, cr7, [r1, #556]! @ 0x22c │ │ + stc2l 15, cr7, [r1, #412]! @ 0x19c │ │ stc2l 2, cr1, [r4] │ │ │ │ 024036ac : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ ldr r1, [pc, #124] @ 2403738 │ │ mov r4, r0 │ │ @@ -1240124,15 +1240124,15 @@ │ │ ldr r0, [r4] │ │ add r1, pc, r1 │ │ bl 270d930 │ │ ldr r0, [r4] │ │ pop {r4, r5, fp, pc} │ │ eorseq r7, r3, r4, ror ip │ │ eorseq r7, r3, r8, asr #24 │ │ - stc2l 4, cr1, [r3, #936]! @ 0x3a8 │ │ + stc2l 5, cr1, [r3, #92]! @ 0x5c │ │ │ │ 024037d8 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ ldr r4, [pc, #164] @ 240388c │ │ ldr r4, [pc, r4] │ │ ldr r0, [r4] │ │ @@ -1240176,15 +1240176,15 @@ │ │ bl 270d930 │ │ mov r0, #200 @ 0xc8 │ │ pop {r4, r5, fp, pc} │ │ ldrsbteq r7, [r3], -r8 │ │ eorseq r7, r3, ip, lsl #24 │ │ eorseq r7, r3, r0, asr #23 │ │ mlaseq r3, r8, fp, r7 │ │ - stc2l 11, cr11, [r2, #216]! @ 0xd8 @ │ │ + stc2l 11, cr11, [r2, #396]! @ 0x18c @ │ │ │ │ 024038a0 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ ldr r4, [pc, #164] @ 2403954 │ │ ldr r4, [pc, r4] │ │ ldr r0, [r4] │ │ @@ -1240228,15 +1240228,15 @@ │ │ bl 270d930 │ │ mov r0, #200 @ 0xc8 │ │ pop {r4, r5, fp, pc} │ │ eorseq r7, r3, r0, lsl fp │ │ eorseq r7, r3, r4, asr #22 │ │ ldrshteq r7, [r3], -r8 │ │ ldrsbteq r7, [r3], -r0 │ │ - stc2l 10, cr11, [r2, #440]! @ 0x1b8 @ │ │ + stc2l 10, cr11, [r2, #620]! @ 0x26c @ │ │ │ │ 02403968 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #28 │ │ mov r5, r3 │ │ mov r7, r2 │ │ @@ -1241274,24 +1241274,24 @@ │ │ bcc 2404e60 │ │ ldr r0, [pc, #4048] @ 2405974 │ │ movw r3, #2691 @ 0xa83 │ │ ldr r2, [pc, #4044] @ 2405978 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ b 2404e50 │ │ - stc2l 11, cr1, [r2, #916]! @ 0x394 @ │ │ - stc2l 7, cr9, [r1, #312]! @ 0x138 │ │ - stc2l 11, cr1, [r2, #724]! @ 0x2d4 @ │ │ - stc2l 7, cr13, [r2, #336]! @ 0x150 │ │ + stc2l 12, cr1, [r2, #72]! @ 0x48 │ │ + stc2l 7, cr9, [r1, #492]! @ 0x1ec │ │ + stc2l 11, cr1, [r2, #904]! @ 0x388 @ │ │ + stc2l 7, cr13, [r2, #516]! @ 0x204 │ │ orreq r8, r2, r4, asr lr │ │ ldrsbteq r4, [r4], -r0 │ │ stc2l 11, cr6, [r4, #120]! @ 0x78 @ │ │ - stc2l 10, cr11, [r1, #328]! @ 0x148 @ │ │ + stc2l 10, cr11, [r1, #508]! @ 0x1fc @ │ │ smlaleq sp, r7, r8, r4 │ │ - stc2l 6, cr9, [r1, #728]! @ 0x2d8 │ │ + stc2l 6, cr9, [r1, #908]! @ 0x38c │ │ ldr sl, [pc, #4072] @ 24059cc │ │ mov r0, #1 │ │ add sl, pc, sl │ │ str r0, [sl] │ │ ldr r0, [pc, #4060] @ 24059d0 │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #4056] @ 24059d4 │ │ @@ -1241333,31 +1241333,31 @@ │ │ bcc 2405448 │ │ ldr r0, [pc, #4020] @ 2405a44 │ │ movw r3, #1687 @ 0x697 │ │ ldr r2, [pc, #4016] @ 2405a48 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ b 2405438 │ │ - stc2l 6, cr13, [r2, #848]! @ 0x350 │ │ + stc2l 7, cr13, [r2, #4]! │ │ stc2l 15, cr8, [r4, #8]! │ │ @ instruction: 0x01828dbc │ │ eorseq r4, r4, r8, lsr fp │ │ stc2l 10, cr6, [r4, #536]! @ 0x218 @ │ │ - stc2l 9, cr11, [r1, #372]! @ 0x174 @ │ │ + stc2l 9, cr11, [r1, #462]! @ 0x1ce @ │ │ rsceq sp, r7, r0, lsl #8 │ │ - stc2l 6, cr9, [r1, #120]! @ 0x78 │ │ + stc2l 6, cr9, [r1, #300]! @ 0x12c │ │ stc2l 14, cr8, [r4, #520]! @ 0x208 │ │ - stc2l 10, cr7, [r1, #236]! @ 0xec @ │ │ - stc2l 5, cr9, [r1, #856]! @ 0x358 │ │ - stc2l 10, cr7, [r1, #44]! @ 0x2c @ │ │ + stc2l 10, cr7, [r1, #416]! @ 0x1a0 @ │ │ + stc2l 6, cr9, [r1, #12]! │ │ + stc2l 10, cr7, [r1, #224]! @ 0xe0 @ │ │ stc2l 2, cr13, [r3, #756]! @ 0x2f4 │ │ ldrdeq r8, [r2, ip] │ │ eorseq r4, r4, r8, asr sl │ │ stc2l 9, cr6, [r4, #316]! @ 0x13c @ │ │ - stc2l 8, cr11, [r1, #840]! @ 0x348 │ │ + stc2l 8, cr11, [r1, #1020]! @ 0x3fc │ │ ldr r1, [pc, #4040] @ 2405ab4 │ │ mov r0, #1 │ │ add r1, pc, r1 │ │ str r0, [r1] │ │ ldr r0, [pc, #4028] @ 2405ab8 │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #4024] @ 2405abc │ │ @@ -1241420,18 +1241420,18 @@ │ │ add r0, pc, r0 │ │ mov r1, #5 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ rsceq sp, r7, r8, lsl r3 │ │ - stc2l 5, cr9, [r1, #216]! @ 0xd8 │ │ + stc2l 5, cr9, [r1, #396]! @ 0x18c │ │ orreq r8, r2, r8, asr ip │ │ orreq sp, r3, r4, ror #3 │ │ - stc2l 3, cr15, [r1, #100]! @ 0x64 │ │ + stc2l 3, cr15, [r1, #280]! @ 0x118 │ │ orreq r8, r2, r4, lsl ip │ │ mlaseq r4, r0, r9, r4 │ │ ldr r0, [pc, #4048] @ 2405bec │ │ movw r3, #3238 @ 0xca6 │ │ ldr r2, [pc, #4044] @ 2405bf0 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1241454,25 +1241454,25 @@ │ │ cmp r0, #0 │ │ ble 2405a4c │ │ ldr r0, [pc, #3980] @ 2405c04 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ b 2404be8 │ │ stc2l 8, cr6, [r4, #888]! @ 0x378 │ │ - stc2l 8, cr11, [r1, #72]! @ 0x48 │ │ + stc2l 8, cr11, [r1, #252]! @ 0xfc │ │ rsceq sp, r7, r8, asr r2 │ │ stc2l 2, cr7, [r3, #804]! @ 0x324 │ │ - stc2l 2, cr15, [r1, #612]! @ 0x264 │ │ - vcmla.f16 , q9, q6, #270 │ │ + stc2l 2, cr15, [r1, #792]! @ 0x318 │ │ + stc2l 8, cr1, [r2, #996]! @ 0x3e4 │ │ orreq r8, r2, r4, ror fp │ │ ldrshteq r4, [r4], -r0 │ │ stc2l 8, cr6, [r4, #248]! @ 0xf8 │ │ - stc2l 7, cr11, [r1, #456]! @ 0x1c8 │ │ + stc2l 7, cr11, [r1, #636]! @ 0x27c │ │ strhteq sp, [r7], #24 │ │ - stc2l 3, cr9, [r1, #856]! @ 0x358 │ │ + stc2l 4, cr9, [r1, #12]! │ │ ldr r0, [pc, #3920] @ 2405c08 │ │ movw r3, #2227 @ 0x8b3 │ │ ldr r2, [pc, #3916] @ 2405c0c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r4, [pc, #3904] @ 2405c10 │ │ @@ -1241523,34 +1241523,34 @@ │ │ b 2407224 │ │ strdeq r8, [r2, r8] │ │ orreq sp, r3, r4, lsl #1 │ │ stc2l 10, cr5, [r1, #692]! @ 0x2b4 @ │ │ @ instruction: 0x01828ab4 │ │ eorseq r4, r4, r0, lsr r8 │ │ stc2l 7, cr6, [r4, #504]! @ 0x1f8 │ │ - stc2l 6, cr11, [r1, #712]! @ 0x2c8 │ │ + stc2l 6, cr11, [r1, #892]! @ 0x37c │ │ strdeq sp, [r7], #8 @ │ │ - stc2l 3, cr9, [r1, #88]! @ 0x58 │ │ + stc2l 3, cr9, [r1, #268]! @ 0x10c │ │ stc2l 10, cr5, [r1, #180]! @ 0xb4 @ │ │ stc2l 12, cr14, [r3, #68]! @ 0x44 │ │ orreq r8, r2, ip, lsl sl │ │ mlaseq r4, r8, r7, r4 │ │ stc2l 6, cr6, [r4, #920]! @ 0x398 │ │ - stc2l 6, cr11, [r1, #104]! @ 0x68 │ │ + stc2l 6, cr11, [r1, #284]! @ 0x11c │ │ rsceq sp, r7, r0, rrx │ │ - stc2l 2, cr9, [r1, #504]! @ 0x1f8 │ │ + stc2l 2, cr9, [r1, #684]! @ 0x2ac │ │ stc2l 11, cr14, [r3, #580]! @ 0x244 @ │ │ stc2l 7, cr2, [r4, #568]! @ 0x238 │ │ - stc2l 2, cr9, [r1, #216]! @ 0xd8 │ │ + stc2l 2, cr9, [r1, #396]! @ 0x18c │ │ orreq r8, r2, ip, asr r9 │ │ rsceq r1, r8, r8, lsl #28 │ │ orreq fp, r4, r4, asr r9 │ │ eorseq r4, r4, ip, asr #13 │ │ strhteq ip, [r7], #244 @ 0xf4 │ │ - stc2l 5, cr11, [r1, #328]! @ 0x148 │ │ + stc2l 5, cr11, [r1, #508]! @ 0x1fc │ │ stc2l 6, cr6, [r4, #88]! @ 0x58 │ │ ldr r0, [pc, #3900] @ 2405d30 │ │ movw r3, #2802 @ 0xaf2 │ │ ldr r2, [pc, #3896] @ 2405d34 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1241648,15 +1241648,15 @@ │ │ b 2405164 │ │ orreq r8, r2, r0, ror #17 │ │ stc2l 8, cr0, [r4, #348]! @ 0x15c │ │ orreq r8, r3, r0, lsr r0 │ │ orreq fp, r4, r0, lsr #17 │ │ stc2l 15, cr0, [r1, #820]! @ 0x334 │ │ stc2l 0, cr7, [r3, #68]! @ 0x44 │ │ - stc2l 3, cr9, [r2, #772]! @ 0x304 │ │ + stc2l 3, cr9, [r2, #952]! @ 0x3b8 │ │ orreq r8, r2, r0, asr #16 │ │ ldrhteq r4, [r4], -ip │ │ stc2l 5, cr6, [r4, #40]! @ 0x28 │ │ ldr r0, [pc, #3876] @ 2405ec8 │ │ movw r4, #5000 @ 0x1388 │ │ ldr r0, [pc, r0] │ │ sub r3, r0, #1 │ │ @@ -1241708,45 +1241708,45 @@ │ │ add r1, pc, r1 │ │ bl 270da60 │ │ ldr r0, [pc, #3968] @ 2405ff0 │ │ mov r1, #21 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ b 2403b80 │ │ - stc2l 4, cr11, [r1, #248]! @ 0xf8 │ │ + stc2l 4, cr11, [r1, #428]! @ 0x1ac │ │ rsceq ip, r7, r4, lsl #29 │ │ stc2l 14, cr6, [r3, #980]! @ 0x3d4 │ │ - stc2l 3, cr9, [r2, #260]! @ 0x104 │ │ - stc2l 2, cr7, [r2, #456]! @ 0x1c8 │ │ + stc2l 3, cr9, [r2, #440]! @ 0x1b8 │ │ + stc2l 2, cr7, [r2, #636]! @ 0x27c │ │ stc2l 3, cr6, [r4, #904]! @ 0x388 │ │ stc2l 14, cr0, [r1, #884]! @ 0x374 │ │ stc2l 15, cr6, [r3, #132]! @ 0x84 │ │ - stc2l 0, cr13, [r2, #384]! @ 0x180 │ │ + stc2l 0, cr13, [r2, #564]! @ 0x234 │ │ stc2l 14, cr0, [r1, #708]! @ 0x2c4 │ │ stc2l 14, cr6, [r3, #980]! @ 0x3d4 │ │ stc2l 8, cr8, [r4, #488]! @ 0x1e8 │ │ ldrdeq r7, [r7], #124 @ 0x7c @ │ │ eorseq r4, r4, r4, lsr #9 │ │ orreq lr, r2, r4, asr #4 │ │ orreq r8, r2, r4, lsl #14 │ │ orreq r7, r3, r8, ror lr │ │ - stc2l 3, cr11, [r1, #168]! @ 0xa8 │ │ + stc2l 3, cr11, [r1, #348]! @ 0x15c │ │ stc2l 6, cr0, [r4, #284]! @ 0x11c │ │ orreq r8, r2, r0, lsr #13 │ │ stc2l 13, cr0, [r1, #900]! @ 0x384 │ │ stc2l 14, cr6, [r3, #148]! @ 0x94 │ │ stc2l 13, cr0, [r1, #756]! @ 0x2f4 │ │ stc2l 14, cr6, [r3, #4]! │ │ - stc2l 13, cr14, [r1, #276]! @ 0x114 │ │ + stc2l 13, cr14, [r1, #456]! @ 0x1c8 │ │ rsceq r7, r7, r8, ror #13 │ │ ldrhteq r4, [r4], -r0 │ │ orreq lr, r2, r0, asr r1 │ │ orreq r8, r2, r0, lsl r6 │ │ orreq r7, r3, r4, lsl #27 │ │ - stc2l 2, cr11, [r1, #216]! @ 0xd8 │ │ + stc2l 2, cr11, [r1, #396]! @ 0x18c │ │ stc2l 5, cr0, [r4, #332]! @ 0x14c │ │ ldr r0, [pc, #3824] @ 2405ff4 │ │ movw r3, #2838 @ 0xb16 │ │ ldr r2, [pc, #3820] @ 2405ff8 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1241898,38 +1241898,38 @@ │ │ ldr r2, [pc, #3912] @ 24062a8 │ │ add r3, r4, #1 │ │ ldr r0, [pc, #3908] @ 24062ac │ │ add r2, pc, r2 │ │ add r0, pc, r0 │ │ b 240595c │ │ stc2l 12, cr6, [r3, #724]! @ 0x2d4 │ │ - stc2l 0, cr9, [r2, #468]! @ 0x1d4 │ │ + stc2l 0, cr9, [r2, #648]! @ 0x288 │ │ strdeq r8, [r2, r8] │ │ stc2l 7, cr4, [r4, #216]! @ 0xd8 │ │ - stc2l 1, cr11, [r1, #40]! @ 0x28 │ │ + stc2l 1, cr11, [r1, #220]! @ 0xdc │ │ orreq ip, r3, r4, ror #20 │ │ @ instruction: 0x018284b4 │ │ @ instruction: 0x01828490 │ │ stc2l 6, cr4, [r4, #824]! @ 0x338 │ │ - stc2l 0, cr11, [r1, #648]! @ 0x288 │ │ + stc2l 0, cr11, [r1, #828]! @ 0x33c │ │ strdeq ip, [r3, ip] │ │ orreq r8, r2, ip, asr #8 │ │ orreq r8, r2, r8, lsr #8 │ │ stc2l 6, cr4, [r4, #408]! @ 0x198 │ │ - stc2l 0, cr11, [r1, #232]! @ 0xe8 │ │ + stc2l 0, cr11, [r1, #412]! @ 0x19c │ │ @ instruction: 0x0183c994 │ │ orreq r8, r2, r4, ror #7 │ │ orreq r8, r2, r0, asr #7 │ │ stc2l 5, cr4, [r4, #1016]! @ 0x3f8 │ │ - stc2l 15, cr10, [r1, #840]! @ 0x348 │ │ + stc2l 15, cr10, [r1, #1020]! @ 0x3fc │ │ orreq ip, r3, ip, lsr #18 │ │ orreq r8, r2, ip, ror r3 │ │ orreq r8, r2, r8, asr r3 │ │ stc2l 0, cr6, [r4, #216]! @ 0xd8 │ │ - stc2l 15, cr10, [r1, #424]! @ 0x1a8 │ │ + stc2l 15, cr10, [r1, #604]! @ 0x25c │ │ ldr r0, [pc, #3796] @ 24062b0 │ │ movw r3, #1798 @ 0x706 │ │ ldr r2, [pc, #3792] @ 24062b4 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #3780] @ 24062b8 │ │ @@ -1242023,27 +1242023,27 @@ │ │ str r4, [r2, r1, lsl #2] │ │ ldr r4, [pc, #3524] @ 240631c │ │ ldr r4, [pc, r4] │ │ b 2405768 │ │ stc2l 5, cr14, [r3, #4]! │ │ orreq r8, r2, r0, lsl r3 │ │ stc2l 5, cr4, [r4, #312]! @ 0x138 │ │ - stc2l 15, cr10, [r1, #136]! @ 0x88 │ │ + stc2l 15, cr10, [r1, #316]! @ 0x13c │ │ orreq ip, r3, ip, ror r8 │ │ orreq r8, r2, ip, asr #5 │ │ eorseq r4, r4, ip, lsl r0 │ │ rsceq r7, r7, ip, lsr #6 │ │ orreq r8, r2, r4, ror r2 │ │ rsceq r1, r8, r0, lsr #14 │ │ orreq fp, r4, ip, ror #4 │ │ eorseq r3, r4, r4, ror #31 │ │ rsceq ip, r7, r8, asr #17 │ │ orreq r7, r3, ip, lsr #19 │ │ stc2l 1, cr0, [r4, #748]! @ 0x2ec │ │ - stc2l 14, cr10, [r1, #344]! @ 0x158 │ │ + stc2l 14, cr10, [r1, #524]! @ 0x20c │ │ stc2l 15, cr5, [r4, #104]! @ 0x68 │ │ ldr r0, [pc, #4068] @ 240658c │ │ movw r4, #5000 @ 0x1388 │ │ ldr r0, [pc, r0] │ │ sub r3, r0, #1 │ │ cmp r3, r4 │ │ bcc 24055d8 │ │ @@ -1242113,15 +1242113,15 @@ │ │ orreq r8, r2, ip, ror #1 │ │ smlaleq r1, r8, r8, r5 │ │ orreq fp, r4, r4, ror #1 │ │ eorseq r3, r4, ip, asr lr │ │ rsceq ip, r7, r0, asr #14 │ │ orreq r7, r3, r4, lsr #16 │ │ stc2l 0, cr0, [r4, #204]! @ 0xcc │ │ - stc2l 12, cr10, [r1, #824]! @ 0x338 │ │ + stc2l 12, cr10, [r1, #1004]! @ 0x3ec │ │ stc2l 13, cr5, [r4, #584]! @ 0x248 │ │ orreq r8, r2, ip, asr r0 │ │ rsceq r1, r8, r8, lsl #10 │ │ orreq r8, r2, r4, lsr #32 │ │ orreq fp, r4, r8, lsl r0 │ │ orreq fp, r4, r0 │ │ eorseq r3, r4, ip, ror #26 │ │ @@ -1242250,15 +1242250,15 @@ │ │ str r4, [r0, r1, lsl #2] │ │ b 2405938 │ │ eorseq r3, r4, r4, lsr #26 │ │ strexeq sl, r8, [r4] │ │ orreq r7, r2, r8, lsl #31 │ │ eorseq r3, r4, r0, lsl #26 │ │ stc2l 14, cr15, [r3, #956]! @ 0x3bc │ │ - stc2l 11, cr10, [r1, #552]! @ 0x228 @ │ │ + stc2l 11, cr10, [r1, #732]! @ 0x2dc @ │ │ strdeq r1, [r8], #56 @ 0x38 @ │ │ stc2l 14, cr15, [r3, #748]! @ 0x2ec │ │ ldr r0, [pc, #4084] @ 24068fc │ │ movw r3, #1843 @ 0x733 │ │ ldr r2, [pc, #4080] @ 2406900 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1242279,19 +1242279,19 @@ │ │ mov r3, #0 │ │ ldr r0, [pc, #4028] @ 2406914 │ │ add r2, pc, r2 │ │ add r0, pc, r0 │ │ str r3, [r2, r1, lsl #2] │ │ mov r1, #6 │ │ b 2404be8 │ │ - stc2l 11, cr10, [r1, #344]! @ 0x158 @ │ │ + stc2l 11, cr10, [r1, #524]! @ 0x20c @ │ │ orreq r7, r2, r8, lsl #30 │ │ eorseq r3, r4, r8, ror ip │ │ stc2l 14, cr15, [r3, #492]! @ 0x1ec │ │ - stc2l 11, cr10, [r1, #88]! @ 0x58 @ │ │ + stc2l 11, cr10, [r1, #268]! @ 0x10c @ │ │ movw r0, #5000 @ 0x1388 │ │ cmp r1, r0 │ │ bcc 24059a4 │ │ ldr r0, [pc, #4072] @ 2406978 │ │ movw r3, #3668 @ 0xe54 │ │ ldr r2, [pc, #4068] @ 240697c │ │ add r0, pc, r0 │ │ @@ -1242308,15 +1242308,15 @@ │ │ mov r1, #65 @ 0x41 │ │ add r0, pc, r0 │ │ b 2405ce4 │ │ orreq sl, r4, ip, lsr #29 │ │ stlexeq r7, ip, [r2] │ │ eorseq r3, r4, r4, lsl ip │ │ stc2l 14, cr15, [r3, #12]! │ │ - stc2l 10, cr10, [r1, #632]! @ 0x278 @ │ │ + stc2l 10, cr10, [r1, #812]! @ 0x32c @ │ │ movw r0, #5000 @ 0x1388 │ │ cmp r1, r0 │ │ bcc 2405a08 │ │ ldr r0, [pc, #3988] @ 2406988 │ │ movw r3, #5067 @ 0x13cb │ │ ldr r2, [pc, #3984] @ 240698c │ │ add r0, pc, r0 │ │ @@ -1242331,19 +1242331,19 @@ │ │ bl 270d2d0 │ │ ldr r0, [pc, #4092] @ 2406a24 │ │ mov r1, #65 @ 0x41 │ │ add r0, pc, r0 │ │ b 2405f94 │ │ rsceq r1, r8, ip, lsl #6 │ │ stc2l 13, cr15, [r3, #828]! @ 0x33c │ │ - stc2l 10, cr10, [r1, #424]! @ 0x1a8 @ │ │ + stc2l 10, cr10, [r1, #604]! @ 0x25c @ │ │ orreq r7, r2, ip, lsl lr │ │ eorseq r3, r4, ip, lsl #23 │ │ stc2l 13, cr15, [r3, #572]! @ 0x23c │ │ - stc2l 10, cr10, [r1, #168]! @ 0xa8 @ │ │ + stc2l 10, cr10, [r1, #348]! @ 0x15c @ │ │ ldr r0, [pc, #4052] @ 2406a28 │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ movw r0, #5000 @ 0x1388 │ │ cmp r1, r0 │ │ bcc 2405a80 │ │ ldr r0, [pc, #4032] @ 2406a2c │ │ @@ -1242386,19 +1242386,19 @@ │ │ mov r1, r4 │ │ bl 270d2d0 │ │ ldr r0, [pc, #3988] @ 2406a9c │ │ mov r1, #65 @ 0x41 │ │ add r0, pc, r0 │ │ b 2406248 │ │ stc2l 12, cr15, [r3, #1004]! @ 0x3ec │ │ - stc2l 9, cr10, [r1, #300]! @ 0x12c @ │ │ + stc2l 9, cr10, [r1, #390]! @ 0x186 @ │ │ rsceq r1, r8, r4, lsl #4 │ │ orreq r7, r3, r8, asr #9 │ │ stc2l 12, cr15, [r3, #764]! @ 0x2fc │ │ - stc2l 9, cr10, [r1, #180]! @ 0xb4 @ │ │ + stc2l 9, cr10, [r1, #270]! @ 0x10e @ │ │ movw r0, #5000 @ 0x1388 │ │ cmp r1, r0 │ │ bcc 2405b50 │ │ ldr r0, [pc, #4088] @ 2406b34 │ │ movw r3, #3934 @ 0xf5e │ │ ldr r2, [pc, #4084] @ 2406b38 │ │ add r0, pc, r0 │ │ @@ -1242415,15 +1242415,15 @@ │ │ mov r1, #65 @ 0x41 │ │ add r0, pc, r0 │ │ b 240667c │ │ @ instruction: 0x01837490 │ │ orreq r7, r2, r4, lsl #26 │ │ eorseq r3, r4, r4, ror sl │ │ stc2l 12, cr15, [r3, #476]! @ 0x1dc │ │ - stc2l 9, cr10, [r1, #36]! @ 0x24 @ │ │ + stc2l 9, cr10, [r1, #126]! @ 0x7e @ │ │ orreq r7, r2, ip, asr #25 │ │ eorseq r3, r4, r0, asr #20 │ │ orreq r7, r3, ip, lsr r4 │ │ stc2l 10, cr1, [r4, #664]! @ 0x298 @ │ │ movw r0, #5000 @ 0x1388 │ │ cmp r1, r0 │ │ bcc 2405bc4 │ │ @@ -1242441,22 +1242441,22 @@ │ │ mov r1, r4 │ │ bl 270d2d0 │ │ ldr r0, [pc, #4044] @ 2406bb0 │ │ mov r1, #65 @ 0x41 │ │ add r0, pc, r0 │ │ b 2406834 │ │ stc2l 14, cr3, [r4, #808]! @ 0x328 │ │ - stc2l 8, cr10, [r1, #632]! @ 0x278 │ │ + vcmla.f16 q13, , , #270 │ │ strdeq ip, [r3, ip] │ │ orreq r7, r2, ip, asr #24 │ │ ldrdeq ip, [r3, r8] │ │ orreq ip, r3, ip, asr #3 │ │ stc2l 1, cr12, [r3, #916]! @ 0x394 │ │ stc2l 14, cr3, [r4, #184]! @ 0xb8 │ │ - vcmla.f16 d26, d1, d2, #270 │ │ + vcmla.f16 d26, d1, d31, #270 │ │ orreq ip, r3, r0, ror #2 │ │ @ instruction: 0x01827bb0 │ │ orreq ip, r3, ip, lsr r1 │ │ orreq ip, r3, r0, lsr r1 │ │ orreq r8, r2, ip, lsl #17 │ │ ldr r0, [pc, #3976] @ 2406bb4 │ │ movw r3, #3677 @ 0xe5d │ │ @@ -1242518,25 +1242518,25 @@ │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #4024] @ 2406cd0 │ │ add r0, pc, r0 │ │ b 2404be4 │ │ orreq r7, r2, r0, ror fp │ │ stc2l 11, cr15, [r3, #192]! @ 0xc0 @ │ │ - stc2l 7, cr10, [r1, #520]! @ 0x208 │ │ + stc2l 7, cr10, [r1, #700]! @ 0x2bc │ │ orreq r5, r4, ip, lsl sp │ │ orreq r7, r2, r4, lsr #22 │ │ stc2l 10, cr15, [r3, #172]! @ 0xac @ │ │ - stc2l 6, cr10, [r1, #792]! @ 0x318 │ │ + stc2l 6, cr10, [r1, #972]! @ 0x3cc │ │ orreq r7, r3, r0, lsl #4 │ │ ldrshteq r3, [r4], -r8 │ │ orreq r7, r2, r8, ror #20 │ │ ldrsbteq r3, [r4], -r8 │ │ stc2l 9, cr15, [r3, #438]! @ 0x1b6 @ │ │ - stc2l 6, cr10, [r1, #472]! @ 0x1d8 │ │ + stc2l 6, cr10, [r1, #652]! @ 0x28c │ │ orreq r7, r2, r0, lsr sl │ │ orreq r7, r3, r4, lsr #3 │ │ eorseq r3, r4, r0, lsr #15 │ │ strdeq r7, [r2, r0] │ │ @ instruction: 0x018285b8 │ │ @ instruction: 0x018286b4 │ │ movw r6, #5000 @ 0x1388 │ │ @@ -1242614,26 +1242614,26 @@ │ │ add r0, pc, r0 │ │ b 2404be4 │ │ @ instruction: 0x018286b0 │ │ orreq r7, r2, ip, ror #19 │ │ rsceq fp, r7, r4, lsr #17 │ │ @ instruction: 0x018279bc │ │ stc2l 15, cr3, [r3, #944]! @ 0x3b0 │ │ - stc2l 5, cr10, [r1, #824]! @ 0x338 │ │ + stc2l 5, cr10, [r1, #1004]! @ 0x3ec │ │ orreq r7, r2, r4, lsl #19 │ │ eorseq r3, r4, r0, lsl #14 │ │ eorseq r3, r4, r0, lsl #14 │ │ teqeq r4, ip, ror #18 │ │ orreq sl, r4, ip, asr r9 │ │ orreq r7, r2, r4, asr #18 │ │ rsceq fp, r7, r0, asr #31 │ │ orreq r7, r2, r4, lsr #18 │ │ orreq r7, r2, r8, ror #17 │ │ stc2l 5, cr5, [r4, #792]! @ 0x318 │ │ - stc2l 4, cr10, [r1, #1000]! @ 0x3e8 │ │ + stc2l 5, cr10, [r1, #156]! @ 0x9c │ │ ldr r0, [pc, #4028] @ 2406e98 │ │ movw r3, #5076 @ 0x13d4 │ │ ldr r2, [pc, #4024] @ 2406e9c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #4012] @ 2406ea0 │ │ @@ -1242693,21 +1242693,21 @@ │ │ add r0, pc, r0 │ │ b 2404be4 │ │ rsceq fp, r7, r0, asr #30 │ │ orreq r8, r2, r8, ror #8 │ │ stc2l 15, cr5, [r3, #764]! @ 0x2fc │ │ orreq r7, r2, r8, lsl #17 │ │ vcmla.f16 , , q6, #270 │ │ - stc2l 4, cr10, [r1, #632]! @ 0x278 │ │ + stc2l 4, cr10, [r1, #812]! @ 0x32c │ │ orreq r5, r4, r0, lsr sl │ │ - stc2l 14, cr13, [r1, #772]! @ 0x304 │ │ + stc2l 14, cr13, [r1, #952]! @ 0x3b8 │ │ orreq r8, r2, ip, ror #7 │ │ stc2l 14, cr3, [r3, #452]! @ 0x1c4 │ │ stc2l 4, cr5, [r4, #520]! @ 0x208 │ │ - stc2l 3, cr10, [r1, #728]! @ 0x2d8 │ │ + stc2l 3, cr10, [r1, #908]! @ 0x38c │ │ rsceq fp, r7, r4, lsl #28 │ │ orreq r7, r2, r4, ror #14 │ │ orreq r7, r2, r8, asr r7 │ │ movw r5, #5000 @ 0x1388 │ │ cmp r3, r5 │ │ bcc 2406034 │ │ ldr r0, [pc, #4036] @ 2406fe0 │ │ @@ -1242781,30 +1242781,30 @@ │ │ ldr r0, [pc, #4012] @ 24070d8 │ │ ldr r0, [pc, r0] │ │ sub r4, r0, #1 │ │ cmp r4, r5 │ │ bcs 2407010 │ │ mov r1, r4 │ │ b 2407068 │ │ - stc2l 3, cr10, [r1, #500]! @ 0x1f4 │ │ - stc2l 3, cr10, [r1, #456]! @ 0x1c8 │ │ + stc2l 3, cr10, [r1, #680]! @ 0x2a8 │ │ + stc2l 3, cr10, [r1, #636]! @ 0x27c │ │ orreq r7, r2, ip, lsr #14 │ │ orreq r2, r3, r4, lsl #1 │ │ stc2l 13, cr3, [r3, #320]! @ 0x140 │ │ - stc2l 3, cr10, [r1, #200]! @ 0xc8 │ │ + stc2l 3, cr10, [r1, #380]! @ 0x17c │ │ orreq r7, r2, ip, ror #13 │ │ stc2l 6, cr15, [r3, #624]! @ 0x270 │ │ - stc2l 2, cr10, [r1, #952]! @ 0x3b8 │ │ + stc2l 3, cr10, [r1, #108]! @ 0x6c │ │ orreq r7, r2, r8, lsr #13 │ │ orreq r5, r4, r0, lsl #17 │ │ stc2l 12, cr3, [r3, #816]! @ 0x330 │ │ - stc2l 2, cr10, [r1, #696]! @ 0x2b8 │ │ + stc2l 2, cr10, [r1, #876]! @ 0x36c │ │ orreq r7, r2, r8, ror #12 │ │ stc2l 12, cr3, [r3, #652]! @ 0x28c │ │ - stc2l 2, cr10, [r1, #424]! @ 0x1a8 │ │ + stc2l 2, cr10, [r1, #604]! @ 0x25c │ │ orreq r7, r2, r4, lsr #12 │ │ ldrdeq r0, [r4, ip] │ │ ldr r0, [pc, #3916] @ 24070dc │ │ movw r3, #4499 @ 0x1193 │ │ ldr r2, [pc, #4092] @ 2407194 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1242862,45 +1242862,45 @@ │ │ mov r1, #21 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #3912] @ 24071c4 │ │ add r0, pc, r0 │ │ b 2404be4 │ │ stc2l 12, cr3, [r3, #288]! @ 0x120 │ │ - stc2l 2, cr10, [r1, #168]! @ 0xa8 │ │ + stc2l 2, cr10, [r1, #348]! @ 0x15c │ │ orreq r7, r2, r4, ror #11 │ │ orreq r8, r2, r4, asr #5 │ │ stc2l 7, cr13, [r3, #360]! @ 0x168 │ │ - stc2l 1, cr10, [r1, #696]! @ 0x2b8 │ │ + stc2l 1, cr10, [r1, #876]! @ 0x36c │ │ orreq r8, r2, r4, ror r2 │ │ orreq r7, r2, r0, ror #10 │ │ strdeq r6, [r7], #80 @ 0x50 @ │ │ orreq r8, r2, r4, asr #4 │ │ orreq fp, r3, r8, asr #21 │ │ - stc2l 2, cr6, [r1, #172]! @ 0xac │ │ + stc2l 2, cr6, [r1, #352]! @ 0x160 │ │ stc2l 4, cr15, [r3, #268]! @ 0x10c │ │ - stc2l 0, cr10, [r1, #888]! @ 0x378 │ │ + stc2l 1, cr10, [r1, #44]! @ 0x2c │ │ orreq r6, r3, r8, lsl ip │ │ eorseq r3, r4, r0, lsl r2 │ │ orreq r7, r2, r0, lsl #9 │ │ ldrshteq r3, [r4], -r0 │ │ stc2l 3, cr15, [r3, #972]! @ 0x3cc │ │ - stc2l 0, cr10, [r1, #568]! @ 0x238 │ │ + stc2l 0, cr10, [r1, #748]! @ 0x2ec │ │ orreq r7, r2, r8, asr #8 │ │ @ instruction: 0x01836bbc │ │ ldrhteq r3, [r4], -r8 │ │ orreq r7, r2, r8, lsl #16 │ │ ldrdeq r7, [r2, r0] │ │ orreq r8, r2, ip, asr #1 │ │ orreq r8, r2, r8, asr #1 │ │ orreq r7, r2, r4, lsl #8 │ │ strhteq fp, [r7], #44 @ 0x2c │ │ ldrdeq r7, [r2, r4] │ │ stc2l 10, cr3, [r3, #16]! @ │ │ - stc2l 15, cr9, [r1, #920]! @ 0x398 │ │ + stc2l 0, cr10, [r1, #76]! @ 0x4c │ │ orreq r7, r2, r4, lsl #15 │ │ eorseq r3, r4, r8, lsl r1 │ │ eorseq r3, r4, r8, lsl r1 │ │ teqeq r4, r4, lsl #7 │ │ orreq sl, r4, r4, ror r3 │ │ orreq r7, r2, ip, asr r3 │ │ ldrdeq fp, [r7], #152 @ 0x98 @ │ │ @@ -1243058,23 +1243058,23 @@ │ │ str r4, [sp, #24] │ │ cmp r4, r5 │ │ bcs 24070e0 │ │ mov r1, r4 │ │ b 2407138 │ │ orreq r7, r2, r4, ror #5 │ │ stc2l 15, cr4, [r4, #776]! @ 0x308 │ │ - stc2l 14, cr9, [r1, #984]! @ 0x3d8 │ │ + stc2l 15, cr9, [r1, #140]! @ 0x8c │ │ rsceq fp, r7, ip, lsr r9 │ │ orreq r7, r2, r4, ror #28 │ │ stc2l 9, cr5, [r3, #374]! @ 0x176 @ │ │ orreq r7, r2, r4, lsl #5 │ │ stc2l 2, cr15, [r3, #288]! @ 0x120 │ │ - stc2l 14, cr9, [r1, #616]! @ 0x268 │ │ + stc2l 14, cr9, [r1, #796]! @ 0x31c │ │ orreq r5, r4, ip, lsr #8 │ │ - stc2l 8, cr13, [r1, #756]! @ 0x2f4 │ │ + vcmla.f16 , , q13, #270 │ │ orreq r7, r2, r8, ror #27 │ │ vcmla.f16 , , , #270 │ │ ldr r0, [pc, #4040] @ 2407590 │ │ movw r3, #3943 @ 0xf67 │ │ ldr r2, [pc, #4036] @ 2407594 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1243131,15 +1243131,15 @@ │ │ mov r1, #21 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #4044] @ 240767c │ │ add r0, pc, r0 │ │ b 2404be4 │ │ stc2l 14, cr4, [r4, #504]! @ 0x1f8 │ │ - stc2l 13, cr9, [r1, #712]! @ 0x2c8 │ │ + stc2l 13, cr9, [r1, #892]! @ 0x37c │ │ rsceq fp, r7, r0, lsl #16 │ │ orreq r7, r2, r0, ror #2 │ │ movw r2, #5000 @ 0x1388 │ │ cmp r1, r2 │ │ bcc 24066f4 │ │ ldr r0, [pc, #4008] @ 2407680 │ │ movw r3, #3961 @ 0xf79 │ │ @@ -1243163,30 +1243163,30 @@ │ │ mov r3, r1 │ │ add r0, pc, r0 │ │ ldr r0, [r0, r1, lsl #2] │ │ add r0, r0, #1 │ │ str r0, [sp, #20] │ │ b 2407fa8 │ │ orreq r7, r2, ip, lsr r5 │ │ - stc2l 13, cr9, [r1, #484]! @ 0x1e4 │ │ - stc2l 13, cr9, [r1, #440]! @ 0x1b8 │ │ + stc2l 13, cr9, [r1, #664]! @ 0x298 │ │ + stc2l 13, cr9, [r1, #620]! @ 0x26c │ │ orreq r7, r2, r8, lsr #2 │ │ orreq r1, r3, r0, lsl #21 │ │ stc2l 7, cr3, [r3, #304]! @ 0x130 │ │ - stc2l 13, cr9, [r1, #184]! @ 0xb8 │ │ + stc2l 13, cr9, [r1, #364]! @ 0x16c │ │ orreq r7, r2, r8, ror #1 │ │ stc2l 0, cr15, [r3, #608]! @ 0x260 │ │ - stc2l 12, cr9, [r1, #936]! @ 0x3a8 │ │ + stc2l 13, cr9, [r1, #92]! @ 0x5c │ │ orreq r7, r2, r4, lsr #1 │ │ orreq r5, r4, ip, ror r2 │ │ stc2l 6, cr3, [r3, #800]! @ 0x320 │ │ - stc2l 12, cr9, [r1, #680]! @ 0x2a8 │ │ + stc2l 12, cr9, [r1, #860]! @ 0x35c │ │ orreq r7, r2, r4, rrx │ │ stc2l 6, cr3, [r3, #636]! @ 0x27c │ │ - stc2l 12, cr9, [r1, #408]! @ 0x198 │ │ + stc2l 12, cr9, [r1, #588]! @ 0x24c │ │ ldr r0, [pc, #4064] @ 2407760 │ │ movw r3, #4785 @ 0x12b1 │ │ ldr r2, [pc, #4060] @ 2407764 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #4048] @ 2407768 │ │ @@ -1243243,15 +1243243,15 @@ │ │ bl 270da10 │ │ ldr r0, [pc, #4028] @ 2407824 │ │ add r0, pc, r0 │ │ b 2404be4 │ │ orreq r7, r2, r0, lsr #32 │ │ ldrdeq r0, [r4, r8] │ │ stc2l 6, cr3, [r3, #272]! @ 0x110 │ │ - stc2l 12, cr9, [r1, #152]! @ 0x98 │ │ + stc2l 12, cr9, [r1, #332]! @ 0x14c │ │ orreq r6, r2, r0, ror #31 │ │ orreq r7, r2, r0, asr #25 │ │ movw r2, #5000 @ 0x1388 │ │ cmp r1, r2 │ │ bcc 24068b4 │ │ ldr r0, [pc, #4060] @ 2407874 │ │ movw r3, #4804 @ 0x12c4 │ │ @@ -1243277,20 +1243277,20 @@ │ │ mov r3, r1 │ │ add r0, pc, r0 │ │ ldr r0, [r0, r1, lsl #2] │ │ add r0, r0, #1 │ │ str r0, [sp, #20] │ │ b 2408230 │ │ stc2l 1, cr13, [r3, #376]! @ 0x178 │ │ - stc2l 11, cr9, [r1, #712]! @ 0x2c8 @ │ │ + stc2l 11, cr9, [r1, #892]! @ 0x37c @ │ │ orreq r7, r2, r8, ror ip │ │ orreq r6, r2, r4, ror #30 │ │ strdeq r5, [r7], #244 @ 0xf4 @ │ │ ldrdeq fp, [r3, r8] │ │ - stc2l 12, cr15, [r1, #436]! @ 0x1b4 │ │ + stc2l 12, cr15, [r1, #616]! @ 0x268 │ │ ldr r0, [pc, #3948] @ 240788c │ │ add r0, pc, r0 │ │ bl 270d2e0 │ │ ldr r0, [pc, #3940] @ 2407890 │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #3936] @ 2407894 │ │ cmn r0, #1 │ │ @@ -1243308,19 +1243308,19 @@ │ │ add r5, pc, r5 │ │ ldr r7, [pc, #3900] @ 24078a8 │ │ add r9, pc, r9 │ │ add r6, pc, r6 │ │ add r7, pc, r7 │ │ b 24069b0 │ │ stc2l 11, cr4, [r4, #984]! @ 0x3d8 @ │ │ - stc2l 11, cr9, [r1, #168]! @ 0xa8 @ │ │ + stc2l 11, cr9, [r1, #348]! @ 0x15c @ │ │ @ instruction: 0x01827a9c │ │ - stc2l 11, cr9, [r1, #48]! @ 0x30 @ │ │ + stc2l 11, cr9, [r1, #228]! @ 0xe4 @ │ │ stc2l 11, cr4, [r4, #584]! @ 0x248 @ │ │ - stc2l 10, cr9, [r1, #792]! @ 0x318 @ │ │ + stc2l 10, cr9, [r1, #972]! @ 0x3cc @ │ │ orreq r7, r2, r8, lsr sl │ │ add r0, r6, r1, lsl #2 │ │ ldr r0, [r0] │ │ ldr r1, [pc, #3848] @ 24078ac │ │ cmn r0, #1 │ │ add r1, pc, r1 │ │ str r0, [r1] │ │ @@ -1243350,18 +1243350,18 @@ │ │ ldr r0, [pc, #3756] @ 24078bc │ │ mov r2, r7 │ │ movw r3, #2728 @ 0xaa8 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2406994 │ │ - stc2l 10, cr9, [r1, #672]! @ 0x2a0 @ │ │ + stc2l 10, cr9, [r1, #852]! @ 0x354 @ │ │ orreq r6, r2, ip, lsr lr │ │ stc2l 4, cr3, [r3, #540]! @ 0x21c │ │ - stc2l 10, cr9, [r1, #312]! @ 0x138 @ │ │ + stc2l 10, cr9, [r1, #492]! @ 0x1ec @ │ │ orreq r0, r4, r8, asr #3 │ │ cmp r1, r8 │ │ bcc 2406a60 │ │ ldr r0, [pc, #3704] @ 24078c0 │ │ mov r2, r7 │ │ mov r3, #2752 @ 0xac0 │ │ add r0, pc, r0 │ │ @@ -1243378,17 +1243378,17 @@ │ │ cmp r2, r0 │ │ bne 2406aa0 │ │ ldr r0, [pc, #3656] @ 24078d0 │ │ add r0, pc, r0 │ │ b 2406ad8 │ │ strdeq r6, [r2, r0] │ │ stc2l 10, cr4, [r4, #712]! @ 0x2c8 @ │ │ - stc2l 9, cr9, [r1, #460]! @ 0x1cc @ │ │ + stc2l 10, cr9, [r1, #76]! @ 0x4c @ │ │ orreq r7, r2, r8, asr r9 │ │ - stc2l 9, cr9, [r1, #400]! @ 0x190 @ │ │ + stc2l 9, cr9, [r1, #490]! @ 0x1ea @ │ │ ldr r0, [pc, #4076] @ 2407a94 │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ cmp r1, r8 │ │ bcc 2406ad4 │ │ ldr r0, [pc, #4060] @ 2407a98 │ │ mov r2, r7 │ │ @@ -1243419,17 +1243419,17 @@ │ │ str r2, [r0] │ │ ldr r0, [pc, #4076] @ 2407b14 │ │ ldr r5, [pc, #4076] @ 2407b18 │ │ add r0, pc, r0 │ │ add r5, pc, r5 │ │ b 2406998 │ │ stc2l 10, cr4, [r4, #296]! @ 0x128 @ │ │ - stc2l 9, cr9, [r1, #252]! @ 0xfc @ │ │ + stc2l 9, cr9, [r1, #342]! @ 0x156 @ │ │ strdeq r7, [r2, r0] │ │ - stc2l 9, cr9, [r1, #192]! @ 0xc0 @ │ │ + stc2l 9, cr9, [r1, #282]! @ 0x11a @ │ │ ldr r0, [pc, #4048] @ 2407b1c │ │ add r0, pc, r0 │ │ bl 270d2e0 │ │ ldr r0, [pc, #4040] @ 2407b20 │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #4036] @ 2407b24 │ │ cmn r0, #1 │ │ @@ -1243447,19 +1243447,19 @@ │ │ add r5, pc, r5 │ │ ldr r7, [pc, #4000] @ 2407b38 │ │ add r9, pc, r9 │ │ add r6, pc, r6 │ │ add r7, pc, r7 │ │ b 2406bdc │ │ stc2l 9, cr4, [r4, #428]! @ 0x1ac @ │ │ - stc2l 9, cr9, [r1, #20]! @ │ │ + stc2l 9, cr9, [r1, #110]! @ 0x6e @ │ │ orreq r7, r2, ip, ror r8 │ │ - vcmla.f16 , , q14, #270 │ │ + stc2l 9, cr9, [r1, #50]! @ 0x32 @ │ │ stc2l 14, cr2, [r4, #744]! @ 0x2e8 │ │ - vcmla.f16 d25, d17, d14, #270 │ │ + stc2l 8, cr9, [r1, #748]! @ 0x2ec │ │ orreq r6, r2, ip, asr #24 │ │ add r0, r6, r1, lsl #2 │ │ ldr r0, [r0] │ │ ldr r1, [pc, #4044] @ 2407b9c │ │ cmn r0, #1 │ │ add r1, pc, r1 │ │ str r0, [r1] │ │ @@ -1243490,19 +1243490,19 @@ │ │ mov r2, r7 │ │ movw r3, #1724 @ 0x6bc │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2406bc0 │ │ stc2l 14, cr12, [r3, #24]! │ │ - stc2l 8, cr9, [r1, #360]! @ 0x168 │ │ + vcmla.f16 d25, d17, d7, #270 │ │ orreq r7, r2, ip, lsl r9 │ │ orreq r6, r2, r4, lsl #24 │ │ stc2l 8, cr4, [r4, #872]! @ 0x368 │ │ - vcmla.f16 d25, d1, d14, #270 │ │ + stc2l 8, cr9, [r1, #236]! @ 0xec │ │ sub r1, r2, #1 │ │ cmp r1, r8 │ │ bcc 2406c94 │ │ ldr r0, [pc, #3892] @ 2407bb0 │ │ mov r2, r7 │ │ movw r3, #1748 @ 0x6d4 │ │ add r0, pc, r0 │ │ @@ -1243518,18 +1243518,18 @@ │ │ ldr r0, [pc, r0] │ │ cmp r2, r0 │ │ bne 2406cd4 │ │ ldr r0, [pc, #3844] @ 2407bc0 │ │ add r0, pc, r0 │ │ b 2406d0c │ │ orreq r7, r2, r0, lsl #15 │ │ - stc2l 2, cr13, [r2, #480]! @ 0x1e0 │ │ - stc2l 2, cr13, [r1, #36]! @ 0x24 │ │ + stc2l 2, cr13, [r2, #660]! @ 0x294 │ │ + stc2l 2, cr13, [r1, #216]! @ 0xd8 │ │ stc2l 12, cr6, [r4, #656]! @ 0x290 │ │ - stc2l 4, cr11, [r2, #416]! @ 0x1a0 │ │ + stc2l 4, cr11, [r2, #596]! @ 0x254 │ │ ldr r0, [pc, #3816] @ 2407bc4 │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ cmp r1, r8 │ │ bcc 2406d08 │ │ ldr r0, [pc, #3800] @ 2407bc8 │ │ mov r2, r7 │ │ @@ -1243560,23 +1243560,23 @@ │ │ str r2, [r0] │ │ ldr r0, [pc, #3716] @ 2407be0 │ │ ldr r5, [pc, #3716] @ 2407be4 │ │ add r0, pc, r0 │ │ add r5, pc, r5 │ │ b 2406bc4 │ │ vcmla.f16 d20, d4, d6, #270 │ │ - stc2l 7, cr9, [r1, #232]! @ 0xe8 │ │ + stc2l 7, cr9, [r1, #412]! @ 0x19c │ │ orreq r7, r2, r8, lsr #13 │ │ orreq r7, r2, r8, lsr #15 │ │ ldrdeq r9, [r4, r8] │ │ @ instruction: 0x01827794 │ │ orreq r7, r2, r0, lsl #13 │ │ @ instruction: 0x01826ab4 │ │ stc2l 12, cr2, [r4, #984]! @ 0x3d8 │ │ - stc2l 6, cr9, [r1, #808]! @ 0x328 │ │ + stc2l 6, cr9, [r1, #988]! @ 0x3dc │ │ orreq r6, r2, r4, lsl #21 │ │ orreq r9, r4, ip, ror sl │ │ orreq r7, r2, r8, ror #14 │ │ ldr r0, [pc, #3652] @ 2407be8 │ │ movw r3, #2843 @ 0xb1b │ │ ldr r2, [pc, #3648] @ 2407bec │ │ add r0, pc, r0 │ │ @@ -1243610,18 +1243610,18 @@ │ │ ldr r2, [pc, #4024] @ 2407dd8 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2405358 │ │ stc2l 0, cr3, [r3, #528]! @ 0x210 │ │ - stc2l 6, cr9, [r1, #408]! @ 0x198 │ │ + stc2l 6, cr9, [r1, #588]! @ 0x24c │ │ teqeq r4, r4, lsl sl │ │ orreq r9, r4, r4, lsl sl │ │ - stc2l 2, cr11, [r2, #976]! @ 0x3d0 │ │ + stc2l 3, cr11, [r2, #132]! @ 0x84 │ │ ldr r0, [pc, #3984] @ 2407ddc │ │ movw r3, #3238 @ 0xca6 │ │ ldr r2, [pc, #4092] @ 2407e50 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r4, [r6, r0, lsl #2] │ │ @@ -1243636,18 +1243636,18 @@ │ │ ldr r2, [pc, #4052] @ 2407e5c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2404c5c │ │ stc2l 12, cr2, [r4, #40]! @ 0x28 │ │ - stc2l 5, cr9, [r1, #888]! @ 0x378 │ │ + stc2l 6, cr9, [r1, #44]! @ 0x2c │ │ @ instruction: 0x0182699c │ │ stc2l 11, cr12, [r3, #344]! @ 0x158 @ │ │ - stc2l 5, cr9, [r1, #680]! @ 0x2a8 │ │ + stc2l 5, cr9, [r1, #860]! @ 0x35c │ │ orreq r7, r2, ip, ror #12 │ │ orreq r6, r2, r4, asr r9 │ │ ldr r0, [pc, #4004] @ 2407e60 │ │ movw r3, #2227 @ 0x8b3 │ │ ldr r2, [pc, #4000] @ 2407e64 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1243677,18 +1243677,18 @@ │ │ ldr r2, [pc, #4064] @ 2407f0c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2404d04 │ │ stc2l 6, cr4, [r4, #168]! @ 0xa8 │ │ - stc2l 5, cr9, [r1, #376]! @ 0x178 │ │ + stc2l 5, cr9, [r1, #556]! @ 0x22c │ │ ldrdeq r7, [r2, r0] │ │ - stc2l 15, cr12, [r2, #800]! @ 0x320 │ │ - stc2l 15, cr12, [r1, #356]! @ 0x164 │ │ + stc2l 15, cr12, [r2, #980]! @ 0x3d4 │ │ + stc2l 15, cr12, [r1, #536]! @ 0x218 │ │ ldr r0, [pc, #4024] @ 2407f10 │ │ movw r3, #1844 @ 0x734 │ │ ldr r2, [pc, #4020] @ 2407f14 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #4008] @ 2407f18 │ │ @@ -1243718,23 +1243718,23 @@ │ │ sub r1, r0, #1 │ │ movw r0, #4999 @ 0x1387 │ │ cmp r1, r0 │ │ bhi 240760c │ │ ldr r4, [r9, r1, lsl #2] │ │ b 240765c │ │ stc2l 5, cr4, [r4, #408]! @ 0x198 │ │ - stc2l 4, cr9, [r1, #616]! @ 0x268 │ │ + stc2l 4, cr9, [r1, #796]! @ 0x31c │ │ orreq r7, r2, r8, lsl #8 │ │ orreq r7, r2, r8, lsl #10 │ │ orreq r9, r4, r8, lsr r8 │ │ strdeq r7, [r2, r4] │ │ orreq r7, r2, r0, ror #7 │ │ orreq r6, r2, r4, lsl r8 │ │ stc2l 10, cr2, [r4, #344]! @ 0x158 @ │ │ - stc2l 4, cr9, [r1, #168]! @ 0xa8 │ │ + stc2l 4, cr9, [r1, #348]! @ 0x15c │ │ orreq r6, r2, r4, ror #15 │ │ ldrdeq r9, [r4, ip] │ │ ldr r0, [pc, #3860] @ 2407f2c │ │ mov r1, r4 │ │ ldr r2, [pc, #3856] @ 2407f30 │ │ movw r3, #5106 @ 0x13f2 │ │ add r0, pc, r0 │ │ @@ -1243776,15 +1243776,15 @@ │ │ mov r1, r5 │ │ bl 270d420 │ │ ldr r0, [pc, #4072] @ 24080a8 │ │ add r0, pc, r0 │ │ b 2404be4 │ │ orreq r7, r2, r0, asr #9 │ │ stc2l 13, cr2, [r3, #912]! @ 0x390 │ │ - stc2l 3, cr9, [r1, #792]! @ 0x318 │ │ + stc2l 3, cr9, [r1, #972]! @ 0x3cc │ │ teqeq r4, r4, ror r7 │ │ orreq r9, r4, r4, ror r7 │ │ orreq r6, r2, r4, ror #14 │ │ stc2l 9, cr2, [r4, #172]! @ 0xac @ │ │ ldr r0, [pc, #4036] @ 24080ac │ │ mov r1, r4 │ │ ldr r2, [pc, #4032] @ 24080b0 │ │ @@ -1243826,27 +1243826,27 @@ │ │ add r2, r8, r3, lsl #3 │ │ mov r0, r4 │ │ mov r1, r5 │ │ bl 270d420 │ │ ldr r0, [pc, #4088] @ 2408188 │ │ add r0, pc, r0 │ │ b 2404be4 │ │ - stc2l 3, cr9, [r1, #168]! @ 0xa8 │ │ + stc2l 3, cr9, [r1, #348]! @ 0x15c │ │ orreq r6, r2, r8, ror #13 │ │ vcmla.f16 d28, d19, d18, #270 │ │ - stc2l 2, cr9, [r1, #984]! @ 0x3d8 │ │ + stc2l 3, cr9, [r1, #140]! @ 0x8c │ │ @ instruction: 0x018273b8 │ │ orreq r6, r2, r0, lsr #13 │ │ stc2l 3, cr4, [r4, #472]! @ 0x1d8 │ │ - stc2l 2, cr9, [r1, #680]! @ 0x2a8 │ │ + stc2l 2, cr9, [r1, #860]! @ 0x35c │ │ orreq r7, r2, ip, lsl r2 │ │ - stc2l 13, cr12, [r2, #80]! @ 0x50 │ │ - stc2l 12, cr12, [r1, #660]! @ 0x294 │ │ + stc2l 13, cr12, [r2, #260]! @ 0x104 │ │ + stc2l 12, cr12, [r1, #840]! @ 0x348 │ │ stc2l 7, cr6, [r4, #256]! @ 0x100 │ │ - stc2l 13, cr12, [r1, #36]! @ 0x24 │ │ + stc2l 13, cr12, [r1, #216]! @ 0xd8 │ │ ldr r0, [pc, #4028] @ 240818c │ │ mov r1, r4 │ │ ldr r2, [pc, #4024] @ 2408190 │ │ movw r3, #2257 @ 0x8d1 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1243929,28 +1243929,28 @@ │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ str r4, [r5, r1, lsl #2] │ │ b 2404c70 │ │ stc2l 2, cr4, [r4, #312]! @ 0x138 │ │ - stc2l 1, cr9, [r1, #520]! @ 0x208 │ │ + stc2l 1, cr9, [r1, #700]! @ 0x2bc │ │ strdeq r7, [r2, r0] │ │ strdeq r7, [r2, r0] │ │ orreq r9, r4, r0, lsr #10 │ │ ldrdeq r7, [r2, ip] │ │ orreq r7, r2, r8, asr #1 │ │ strdeq r6, [r2, ip] │ │ stc2l 7, cr2, [r4, #248]! @ 0xf8 │ │ - stc2l 1, cr9, [r1, #72]! @ 0x48 │ │ + stc2l 1, cr9, [r1, #252]! @ 0xfc │ │ orreq r6, r2, ip, asr #9 │ │ orreq r9, r4, r4, asr #9 │ │ @ instruction: 0x018271b0 │ │ stc2l 10, cr2, [r3, #816]! @ 0x330 @ │ │ - stc2l 0, cr9, [r1, #696]! @ 0x2b8 │ │ + stc2l 0, cr9, [r1, #876]! @ 0x36c │ │ teqeq r4, ip, asr r4 │ │ orreq r9, r4, ip, asr r4 │ │ orreq r6, r2, r0, lsr ip │ │ strdeq r6, [r2, r4] │ │ strdeq r7, [r2, r4] │ │ strdeq sl, [r7], #40 @ 0x28 @ │ │ rsceq sl, r7, ip, asr #13 │ │ @@ -1244026,15 +1244026,15 @@ │ │ str r3, [r0, r1, lsl #2] │ │ b 2407c4c │ │ orreq r7, r2, ip, lsl #1 │ │ orreq r6, r2, r4, lsl #23 │ │ orreq r6, r2, ip, lsl #7 │ │ orreq r7, r2, r4, lsl #1 │ │ stc2l 9, cr2, [r3, #344]! @ 0x158 @ │ │ - stc2l 15, cr8, [r1, #568]! @ 0x238 │ │ + stc2l 15, cr8, [r1, #748]! @ 0x2ec │ │ ldrdeq sl, [r7], #148 @ 0x94 @ │ │ orreq r6, r2, r4, lsl fp │ │ orreq r9, r4, r4, lsr r3 │ │ teqeq r4, ip, lsr #6 │ │ orreq r6, r2, ip, lsl r3 │ │ movw r4, #5000 @ 0x1388 │ │ cmp r1, r4 │ │ @@ -1244082,15 +1244082,15 @@ │ │ bl 270da60 │ │ ldr r0, [pc, #4032] @ 2408544 │ │ mov r1, #21 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ b 2407b00 │ │ stc2l 5, cr2, [r4, #120]! @ 0x78 │ │ - stc2l 14, cr8, [r1, #968]! @ 0x3c8 │ │ + stc2l 15, cr8, [r1, #124]! @ 0x7c │ │ @ instruction: 0x018262b0 │ │ ldr r0, [pc, #4004] @ 2408548 │ │ movw r3, #2280 @ 0x8e8 │ │ ldr r2, [pc, #4000] @ 240854c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1244106,19 +1244106,19 @@ │ │ sub r1, r2, #1 │ │ add r5, pc, r5 │ │ cmp r1, r4 │ │ bhi 24078d4 │ │ ldr r4, [sl, r1, lsl #2] │ │ b 240792c │ │ stc2l 4, cr12, [r3, #424]! @ 0x1a8 │ │ - stc2l 14, cr8, [r1, #760]! @ 0x2f8 │ │ + stc2l 14, cr8, [r1, #940]! @ 0x3ac │ │ orreq r6, r2, r0, lsl #31 │ │ orreq r6, r2, r8, ror #4 │ │ stc2l 15, cr3, [r4, #264]! @ 0x108 │ │ - stc2l 14, cr8, [r1, #472]! @ 0x1d8 │ │ + stc2l 14, cr8, [r1, #652]! @ 0x28c │ │ orreq r6, r2, r8, ror #27 │ │ ldr r0, [pc, #3848] @ 240851c │ │ movw r3, #2242 @ 0x8c2 │ │ ldr r2, [pc, #3844] @ 2408520 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1244137,20 +1244137,20 @@ │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #3788] @ 2408530 │ │ add r2, r4, #1 │ │ add r0, pc, r0 │ │ str r2, [r0, r1, lsl #2] │ │ b 2407b00 │ │ - vcmla.f16 q14, q9, q8, #270 │ │ - stc2l 8, cr12, [r1, #452]! @ 0x1c4 │ │ + stc2l 9, cr12, [r2, #26]! @ │ │ + stc2l 8, cr12, [r1, #632]! @ 0x278 │ │ stc2l 3, cr6, [r4, #48]! @ 0x30 │ │ stc2l 1, cr3, [r1, #804]! @ 0x324 │ │ - stc2l 5, cr14, [r2, #856]! @ 0x358 │ │ - stc2l 13, cr8, [r1, #904]! @ 0x388 │ │ + stc2l 6, cr14, [r2, #12]! │ │ + stc2l 14, cr8, [r1, #60]! @ 0x3c │ │ @ instruction: 0x0182619c │ │ rsceq r5, r7, ip, lsr r2 │ │ orreq r0, r3, ip, asr #21 │ │ movw r4, #5000 @ 0x1388 │ │ cmp r1, r4 │ │ bcc 24076bc │ │ ldr r0, [pc, #3896] @ 24085e0 │ │ @@ -1244198,15 +1244198,15 @@ │ │ bl 270da60 │ │ ldr r0, [pc, #3764] @ 2408608 │ │ mov r1, #21 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ b 2404c70 │ │ stc2l 3, cr2, [r4, #408]! @ 0x198 │ │ - stc2l 13, cr8, [r1, #232]! @ 0xe8 │ │ + stc2l 13, cr8, [r1, #412]! @ 0x19c │ │ strdeq r6, [r2, r8] │ │ ldr r0, [pc, #3736] @ 240860c │ │ movw r3, #3291 @ 0xcdb │ │ ldr r2, [pc, #3732] @ 2408610 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1244218,19 +1244218,19 @@ │ │ ldr r2, [pc, r2] │ │ sub r1, r2, #1 │ │ cmp r1, r4 │ │ bhi 2407bf4 │ │ ldr r4, [r9, r1, lsl #2] │ │ b 2407c4c │ │ stc2l 2, cr12, [r3, #712]! @ 0x2c8 │ │ - stc2l 13, cr8, [r1, #24]! │ │ + stc2l 13, cr8, [r1, #204]! @ 0xcc │ │ orreq r6, r2, r8, asr #27 │ │ strheq r6, [r2, r0] │ │ stc2l 13, cr3, [r4, #552]! @ 0x228 │ │ - stc2l 12, cr8, [r1, #760]! @ 0x2f8 │ │ + stc2l 12, cr8, [r1, #940]! @ 0x3ac │ │ ldr r0, [pc, #3820] @ 24086bc │ │ movw r3, #3963 @ 0xf7b │ │ ldr r2, [pc, #3816] @ 24086c0 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #3804] @ 24086c4 │ │ @@ -1244243,18 +1244243,18 @@ │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ cmp r1, r4 │ │ bcs 2407f50 │ │ mov r3, r1 │ │ b 2407fa8 │ │ orreq r6, r2, r0, lsr ip │ │ - stc2l 7, cr12, [r2, #160]! @ 0xa0 │ │ - stc2l 6, cr12, [r1, #740]! @ 0x2e4 │ │ + stc2l 7, cr12, [r2, #340]! @ 0x154 │ │ + stc2l 6, cr12, [r1, #920]! @ 0x398 │ │ stc2l 1, cr6, [r4, #336]! @ 0x150 │ │ - stc2l 11, cr6, [r2, #612]! @ 0x264 @ │ │ + stc2l 11, cr6, [r2, #792]! @ 0x318 @ │ │ ldr r0, [pc, #3860] @ 2408744 │ │ movw r3, #4806 @ 0x12c6 │ │ ldr r2, [pc, #3856] @ 2408748 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #3844] @ 240874c │ │ @@ -1244266,28 +1244266,28 @@ │ │ ldr r0, [pc, #3824] @ 2408750 │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ cmp r1, r4 │ │ bcs 24081d8 │ │ mov r3, r1 │ │ b 2408230 │ │ - stc2l 4, cr14, [r2, #88]! @ 0x58 │ │ - stc2l 12, cr8, [r1, #136]! @ 0x88 │ │ + stc2l 4, cr14, [r2, #268]! @ 0x10c │ │ + stc2l 12, cr8, [r1, #316]! @ 0x13c │ │ ldrdeq r5, [r2, ip] │ │ rsceq r5, r7, ip, ror r0 │ │ rsceq pc, r7, r0, lsl #9 │ │ orreq r0, r3, r4, lsl #18 │ │ @ instruction: 0x0182ba98 │ │ eorseq r1, r4, r4, ror #25 │ │ orreq r5, r2, r8, asr pc │ │ strdeq pc, [r7], #60 @ 0x3c @ │ │ rsceq sl, r7, r0, asr #11 │ │ orreq fp, r2, ip, asr #20 │ │ orreq r5, r3, r0, lsr #13 │ │ - stc2l 11, cr8, [r1, #328]! @ 0x148 @ │ │ + stc2l 11, cr8, [r1, #508]! @ 0x1fc @ │ │ orreq r5, r2, r8, ror #29 │ │ stc2l 11, cr3, [r4, #776]! @ 0x308 @ │ │ orreq r5, r2, r4, lsr #29 │ │ rsceq pc, r7, r4, asr #6 │ │ stc2l 14, cr13, [r3, #60]! @ 0x3c │ │ stc2l 13, cr13, [r3, #860]! @ 0x35c │ │ orreq r5, r2, r0, lsr lr │ │ @@ -1244443,15 +1244443,15 @@ │ │ orreq fp, r2, ip, ror #16 │ │ ldrhteq r1, [r4], -r8 │ │ orreq r5, r2, ip, lsr #26 │ │ ldrdeq pc, [r7], #16 @ │ │ smlaleq sl, r7, r4, r3 │ │ orreq fp, r2, r0, lsr #16 │ │ orreq r5, r3, r4, ror r4 │ │ - stc2l 9, cr8, [r1, #76]! @ 0x4c @ │ │ + stc2l 9, cr8, [r1, #166]! @ 0xa6 @ │ │ ldr r0, [pc, #2692] @ 24085c8 │ │ movw r3, #2286 @ 0x8ee │ │ ldr r2, [pc, #2688] @ 24085cc │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #2676] @ 24085d0 │ │ @@ -1244487,16 +1244487,16 @@ │ │ orreq r5, r2, r8, lsl #23 │ │ eorseq r1, r4, ip, ror #17 │ │ stc2l 10, cr13, [r3, #972]! @ 0x3cc @ │ │ orreq r5, r2, ip, asr #22 │ │ ldrhteq r1, [r4], -ip │ │ orreq r6, r2, r8, lsl #6 │ │ rsceq sl, r7, r0, asr #3 │ │ - stc2l 15, cr13, [r2, #40]! @ 0x28 │ │ - stc2l 7, cr8, [r1, #88]! @ 0x58 │ │ + stc2l 15, cr13, [r2, #220]! @ 0xdc │ │ + stc2l 7, cr8, [r1, #268]! @ 0x10c │ │ rsceq r4, r7, r8, ror fp │ │ ldr r0, [pc, #2592] @ 240861c │ │ movw r3, #3293 @ 0xcdd │ │ ldr r2, [pc, #2588] @ 2408620 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1244608,18 +1244608,18 @@ │ │ bhi 2407de0 │ │ ldr r0, [pc, #2236] @ 2408678 │ │ add r0, pc, r0 │ │ str r4, [r0, r1, lsl #2] │ │ b 2407e18 │ │ orreq r5, r2, r4, asr #21 │ │ stc2l 12, cr11, [r3, #520]! @ 0x208 │ │ - stc2l 6, cr8, [r1, #856]! @ 0x358 │ │ + stc2l 7, cr8, [r1, #12]! │ │ @ instruction: 0x01825a94 │ │ stc2l 12, cr1, [r4, #824]! @ 0x338 │ │ - stc2l 6, cr8, [r1, #648]! @ 0x288 │ │ + stc2l 6, cr8, [r1, #828]! @ 0x33c │ │ stc2l 12, cr1, [r4, #616]! @ 0x268 │ │ ldr r0, [pc, #2196] @ 240867c │ │ mov r3, #3296 @ 0xce0 │ │ ldr r2, [pc, #2192] @ 2408680 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1244641,23 +1244641,23 @@ │ │ add r0, pc, r0 │ │ ldr r0, [r0, r1, lsl #2] │ │ mov r1, #0 │ │ cmp r0, #0 │ │ movwgt r1, #1 │ │ str r1, [r8] │ │ b 2404c70 │ │ - stc2l 6, cr8, [r1, #440]! @ 0x1b8 │ │ + stc2l 6, cr8, [r1, #620]! @ 0x26c │ │ orreq r5, r2, r8, lsr #20 │ │ stc2l 12, cr1, [r4, #408]! @ 0x198 │ │ - stc2l 6, cr8, [r1, #232]! @ 0xe8 │ │ + stc2l 6, cr8, [r1, #412]! @ 0x19c │ │ stc2l 12, cr1, [r4, #168]! @ 0xa8 │ │ - stc2l 5, cr8, [r1, #1016]! @ 0x3f8 │ │ + stc2l 6, cr8, [r1, #172]! @ 0xac │ │ @ instruction: 0x018259b8 │ │ stc2l 11, cr1, [r4, #984]! @ 0x3d8 @ │ │ - stc2l 5, cr8, [r1, #808]! @ 0x328 │ │ + stc2l 5, cr8, [r1, #988]! @ 0x3dc │ │ ldr r0, [pc, #2072] @ 2408694 │ │ movw r3, #3297 @ 0xce1 │ │ ldr r2, [pc, #2068] @ 2408698 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #2056] @ 240869c │ │ @@ -1244688,31 +1244688,31 @@ │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2407e30 │ │ orreq r5, r2, r8, lsl #19 │ │ stc2l 11, cr11, [r3, #264]! @ 0x108 @ │ │ - stc2l 5, cr8, [r1, #600]! @ 0x258 │ │ - stc2l 13, cr13, [r2, #344]! @ 0x158 │ │ - stc2l 5, cr8, [r1, #392]! @ 0x188 │ │ + stc2l 5, cr8, [r1, #780]! @ 0x30c │ │ + stc2l 13, cr13, [r2, #524]! @ 0x20c │ │ + stc2l 5, cr8, [r1, #572]! @ 0x23c │ │ rsceq r4, r7, r4, asr #19 │ │ orreq r5, r2, r0, lsl r9 │ │ stc2l 11, cr1, [r4, #312]! @ 0x138 @ │ │ - stc2l 5, cr8, [r1, #136]! @ 0x88 │ │ + stc2l 5, cr8, [r1, #316]! @ 0x13c │ │ orreq r5, r2, r8, asr #17 │ │ stc2l 5, cr3, [r4, #424]! @ 0x1a8 │ │ - stc2l 4, cr8, [r1, #632]! @ 0x278 │ │ + stc2l 4, cr8, [r1, #812]! @ 0x32c │ │ orreq r5, r2, r8, asr r8 │ │ - stc2l 4, cr8, [r1, #484]! @ 0x1e4 │ │ - stc2l 4, cr8, [r1, #440]! @ 0x1b8 │ │ + stc2l 4, cr8, [r1, #664]! @ 0x298 │ │ + stc2l 4, cr8, [r1, #620]! @ 0x26c │ │ orreq r5, r2, r8, lsr #16 │ │ orreq r0, r3, r4, ror r1 │ │ stc2l 14, cr1, [r3, #272]! @ 0x110 │ │ - stc2l 4, cr8, [r1, #152]! @ 0x98 │ │ + stc2l 4, cr8, [r1, #332]! @ 0x14c │ │ ldr r0, [pc, #1908] @ 24086cc │ │ movw r3, #3963 @ 0xf7b │ │ ldr r2, [pc, #1904] @ 24086d0 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ @@ -1244793,15 +1244793,15 @@ │ │ sub r1, r0, #1 │ │ cmp r1, r4 │ │ bcs 24080b8 │ │ mov r0, r1 │ │ b 24080e4 │ │ stc2l 9, cr5, [r4, #12]! @ │ │ stc2l 4, cr3, [r4, #616]! @ 0x268 │ │ - stc2l 3, cr8, [r1, #824]! @ 0x338 │ │ + stc2l 3, cr8, [r1, #1004]! @ 0x3ec │ │ orreq r5, r2, r8, lsl #15 │ │ ldr r0, [pc, #1624] @ 2408718 │ │ movw r3, #3980 @ 0xf8c │ │ ldr r2, [pc, #1620] @ 240871c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1244817,20 +1244817,20 @@ │ │ mul r4, r0, r2 │ │ movw r0, #5000 @ 0x1388 │ │ cmp r1, r0 │ │ str r4, [r3] │ │ bcs 2408128 │ │ mov r0, r4 │ │ b 2408154 │ │ - stc2l 3, cr8, [r1, #676]! @ 0x2a4 │ │ - stc2l 3, cr8, [r1, #632]! @ 0x278 │ │ + stc2l 3, cr8, [r1, #856]! @ 0x358 │ │ + stc2l 3, cr8, [r1, #812]! @ 0x32c │ │ orreq r5, r2, r8, asr r7 │ │ orreq r0, r3, r4, lsr #1 │ │ stc2l 13, cr1, [r3, #464]! @ 0x1d0 │ │ - stc2l 3, cr8, [r1, #344]! @ 0x158 │ │ + stc2l 3, cr8, [r1, #524]! @ 0x20c │ │ ldr r0, [pc, #1532] @ 240872c │ │ movw r3, #3982 @ 0xf8e │ │ ldr r2, [pc, #1528] @ 2408730 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r2, [pc, #1516] @ 2408734 │ │ @@ -1244847,34 +1244847,34 @@ │ │ mov r0, r5 │ │ mov r2, r9 │ │ add r1, r1, r4 │ │ bl 270d9e0 │ │ ldr r0, [pc, #1468] @ 2408740 │ │ add r0, pc, r0 │ │ b 2404be4 │ │ - stc2l 13, cr11, [r1, #980]! @ 0x3d4 │ │ + stc2l 14, cr11, [r1, #136]! @ 0x88 │ │ stc2l 3, cr3, [r4, #712]! @ 0x2c8 │ │ - stc2l 2, cr8, [r1, #920]! @ 0x398 │ │ + stc2l 3, cr8, [r1, #76]! @ 0x4c │ │ orreq r5, r2, r0, lsr #13 │ │ stc2l 6, cr13, [r3, #384]! @ 0x180 │ │ - stc2l 2, cr8, [r1, #712]! @ 0x2c8 │ │ + stc2l 2, cr8, [r1, #892]! @ 0x37c │ │ orreq r5, r2, ip, ror #12 │ │ stc2l 12, cr1, [r3, #560]! @ 0x230 │ │ - stc2l 2, cr8, [r1, #440]! @ 0x1b8 │ │ + stc2l 2, cr8, [r1, #620]! @ 0x26c │ │ eorseq r1, r4, r8, lsr #7 │ │ eorseq r1, r4, r4, lsr #7 │ │ teqeq r4, r0, lsl r6 │ │ orreq r8, r4, r0, lsl r6 │ │ strdeq r5, [r2, r0] │ │ orreq r8, r4, r8, ror #11 │ │ rsceq r4, r7, r8, ror #12 │ │ teqeq r4, r8, lsr #11 │ │ @ instruction: 0x01825598 │ │ stc2l 7, cr1, [r4, #856]! @ 0x358 │ │ - stc2l 1, cr8, [r1, #680]! @ 0x2a8 │ │ + stc2l 1, cr8, [r1, #860]! @ 0x35c │ │ ldr r0, [pc, #1396] @ 2408754 │ │ movw r3, #4806 @ 0x12c6 │ │ ldr r2, [pc, #1392] @ 2408758 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ @@ -1244974,21 +1244974,21 @@ │ │ movw r0, #5000 @ 0x1388 │ │ cmp r1, r0 │ │ str r4, [r3] │ │ bcs 24083a0 │ │ mov r3, r4 │ │ b 24083cc │ │ stc2l 1, cr3, [r4, #952]! @ 0x3b8 │ │ - stc2l 1, cr8, [r1, #136]! @ 0x88 │ │ + stc2l 1, cr8, [r1, #316]! @ 0x13c │ │ ldrdeq r5, [r2, ip] │ │ stc2l 11, cr1, [r3, #156]! @ 0x9c @ │ │ - stc2l 0, cr8, [r1, #952]! @ 0x3b8 │ │ + stc2l 1, cr8, [r1, #108]! @ 0x6c │ │ orreq r5, r2, r8, lsr #9 │ │ stc2l 10, cr1, [r3, #800]! @ 0x320 @ │ │ - stc2l 0, cr8, [r1, #680]! @ 0x2a8 │ │ + stc2l 0, cr8, [r1, #860]! @ 0x35c │ │ ldr r0, [pc, #1032] @ 24087b0 │ │ movw r3, #4825 @ 0x12d9 │ │ ldr r2, [pc, #1028] @ 24087b4 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r2, [pc, #1016] @ 24087b8 │ │ @@ -1245040,15 +1245040,15 @@ │ │ sub r1, r0, #1 │ │ cmp r1, r4 │ │ bcs 2408494 │ │ mov r3, r1 │ │ b 24084ec │ │ rsceq r4, r7, r0, lsr #9 │ │ stc2l 0, cr3, [r4, #664]! @ 0x298 │ │ - stc2l 15, cr7, [r1, #872]! @ 0x368 │ │ + stc2l 0, cr8, [r1, #28]! │ │ orreq r5, r2, r0, asr pc │ │ ldr r0, [pc, #828] @ 24087d8 │ │ movw r3, #4830 @ 0x12de │ │ ldr r2, [pc, #824] @ 24087dc │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1245075,196 +1245075,196 @@ │ │ mov r3, #1000 @ 0x3e8 │ │ bl 270d430 │ │ ldr r0, [pc, #736] @ 24087ec │ │ add r0, pc, r0 │ │ b 2404be4 │ │ stc2l 10, cr3, [r3, #652]! @ 0x28c @ │ │ orreq r5, r2, ip, ror #6 │ │ - stc2l 10, cr13, [r1, #784]! @ 0x310 @ │ │ + stc2l 10, cr13, [r1, #964]! @ 0x3c4 @ │ │ stc2l 4, cr11, [r3, #328]! @ 0x148 │ │ - stc2l 14, cr7, [r1, #664]! @ 0x298 │ │ + stc2l 14, cr7, [r1, #844]! @ 0x34c │ │ orreq r5, r2, r4, ror #4 │ │ stc2l 4, cr1, [r4, #632]! @ 0x278 │ │ - stc2l 14, cr7, [r1, #456]! @ 0x1c8 │ │ + stc2l 14, cr7, [r1, #636]! @ 0x27c │ │ orreq r9, r3, r8, asr #15 │ │ stc2l 3, cr13, [r3, #192]! @ 0xc0 │ │ - stc2l 15, cr7, [r1, #520]! @ 0x208 │ │ - stc2l 9, cr11, [r1, #338]! @ 0x152 @ │ │ + stc2l 15, cr7, [r1, #700]! @ 0x2bc │ │ + stc2l 9, cr11, [r1, #428]! @ 0x1ac @ │ │ ldrdeq r5, [r2, r8] │ │ stc2l 9, cr1, [r3, #186]! @ 0xba @ │ │ - stc2l 7, cr13, [r2, #40]! @ 0x28 │ │ - stc2l 15, cr7, [r1, #88]! @ 0x58 │ │ + stc2l 7, cr13, [r2, #220]! @ 0xdc │ │ + stc2l 15, cr7, [r1, #268]! @ 0x10c │ │ rsceq r4, r7, r4, ror r3 │ │ @ instruction: 0x018252bc │ │ teqeq r4, ip, lsr #5 │ │ stc2l 15, cr12, [r3, #560]! @ 0x230 │ │ - stc2l 11, cr7, [r1, #888]! @ 0x378 @ │ │ + stc2l 12, cr7, [r1, #44]! @ 0x2c │ │ strexeq r4, ip, [r2] │ │ - stc2l 11, cr7, [r1, #724]! @ 0x2d4 @ │ │ - stc2l 11, cr7, [r1, #680]! @ 0x2a8 @ │ │ + stc2l 11, cr7, [r1, #904]! @ 0x388 @ │ │ + stc2l 11, cr7, [r1, #860]! @ 0x35c @ │ │ orreq r4, r2, r4, ror #30 │ │ @ instruction: 0x0182f8bc │ │ stc2l 5, cr1, [r3, #544]! @ 0x220 │ │ - stc2l 11, cr7, [r1, #424]! @ 0x1a8 @ │ │ + stc2l 11, cr7, [r1, #604]! @ 0x25c @ │ │ orreq r4, r2, r4, lsr #30 │ │ stc2l 14, cr12, [r3, #848]! @ 0x350 │ │ - stc2l 11, cr7, [r1, #152]! @ 0x98 @ │ │ + stc2l 11, cr7, [r1, #332]! @ 0x14c @ │ │ orreq r4, r2, r0, ror #29 │ │ stc2l 5, cr1, [r3, #48]! @ 0x30 │ │ - stc2l 10, cr7, [r1, #952]! @ 0x3b8 @ │ │ + stc2l 11, cr7, [r1, #108]! @ 0x6c @ │ │ orreq r4, r2, r8, lsr #29 │ │ stc2l 4, cr1, [r3, #908]! @ 0x38c │ │ - stc2l 10, cr7, [r1, #680]! @ 0x2a8 @ │ │ + stc2l 10, cr7, [r1, #860]! @ 0x35c @ │ │ orreq r4, r2, r4, ror #28 │ │ orreq lr, r3, ip, lsl r2 │ │ stc2l 4, cr1, [r3, #544]! @ 0x220 │ │ - stc2l 10, cr7, [r1, #424]! @ 0x1a8 @ │ │ + stc2l 10, cr7, [r1, #604]! @ 0x25c @ │ │ orreq r4, r2, r4, lsr #28 │ │ stc2l 15, cr10, [r3, #712]! @ 0x2c8 │ │ - stc2l 10, cr7, [r1, #24]! @ │ │ + stc2l 10, cr7, [r1, #204]! @ 0xcc @ │ │ orreq r4, r2, r0, asr #27 │ │ orreq r9, r3, r8, asr #6 │ │ stc2l 15, cr0, [r4, #648]! @ 0x288 │ │ - stc2l 9, cr7, [r1, #236]! @ 0xec @ │ │ + stc2l 9, cr7, [r1, #326]! @ 0x146 @ │ │ ldrdeq r9, [r3, r0] │ │ orreq r4, r2, r4, lsr #26 │ │ stc2l 14, cr10, [r3, #904]! @ 0x388 │ │ - stc2l 9, cr7, [r1, #108]! @ 0x6c @ │ │ + stc2l 9, cr7, [r1, #198]! @ 0xc6 @ │ │ stc2l 14, cr2, [r4, #888]! @ 0x378 │ │ - stc2l 14, cr7, [r1, #72]! @ 0x48 │ │ + stc2l 14, cr7, [r1, #252]! @ 0xfc │ │ orreq r5, r2, r8, lsl #27 │ │ stc2l 8, cr3, [r3, #876]! @ 0x36c │ │ orreq r5, r2, r4, lsr #3 │ │ stc2l 1, cr13, [r3, #416]! @ 0x1a0 │ │ - stc2l 13, cr7, [r1, #744]! @ 0x2e8 │ │ + stc2l 13, cr7, [r1, #924]! @ 0x39c │ │ orreq r3, r4, ip, asr #6 │ │ - stc2l 7, cr11, [r1, #884]! @ 0x374 │ │ + vcmla.f16 d27, d1, d10, #270 │ │ orreq r5, r2, r8, lsl #26 │ │ stc2l 7, cr1, [r3, #564]! @ 0x234 │ │ - stc2l 5, cr13, [r2, #232]! @ 0xe8 │ │ - stc2l 13, cr7, [r1, #280]! @ 0x118 │ │ + stc2l 5, cr13, [r2, #412]! @ 0x19c │ │ + stc2l 13, cr7, [r1, #460]! @ 0x1cc │ │ rsceq r4, r7, r8, lsr #3 │ │ strdeq r5, [r2, r4] │ │ stc2l 2, cr1, [r3, #988]! @ 0x3dc │ │ - stc2l 8, cr7, [r1, #760]! @ 0x2f8 │ │ + vcmla.f16 , , , #270 │ │ orreq r4, r2, ip, ror ip │ │ - stc2l 8, cr7, [r1, #596]! @ 0x254 │ │ - vcmla.f16 d23, d17, d10, #270 │ │ + vcmla.f16 , , q1, #270 │ │ + stc2l 8, cr7, [r1, #732]! @ 0x2dc │ │ orreq r4, r2, r4, asr #24 │ │ @ instruction: 0x0182f594 │ │ stc2l 2, cr1, [r3, #384]! @ 0x180 │ │ - vcmla.f16 , , q1, #270 │ │ + vcmla.f16 , , , #270 │ │ strdeq r4, [r2, ip] │ │ stc2l 11, cr12, [r3, #688]! @ 0x2b0 @ │ │ - stc2l 7, cr7, [r1, #1016]! @ 0x3f8 │ │ + vcmla.f16 d23, d1, d27, #270 │ │ @ instruction: 0x01824bb8 │ │ @ instruction: 0x01842d90 │ │ stc2l 1, cr1, [r3, #880]! @ 0x370 │ │ - stc2l 7, cr7, [r1, #760]! @ 0x2f8 │ │ + stc2l 7, cr7, [r1, #940]! @ 0x3ac │ │ orreq r4, r2, r8, ror fp │ │ stc2l 1, cr1, [r3, #716]! @ 0x2cc │ │ - stc2l 7, cr7, [r1, #488]! @ 0x1e8 │ │ + stc2l 7, cr7, [r1, #668]! @ 0x29c │ │ orreq r4, r2, r4, lsr fp │ │ stc2l 1, cr1, [r3, #384]! @ 0x180 │ │ - stc2l 7, cr7, [r1, #264]! @ 0x108 │ │ + stc2l 7, cr7, [r1, #444]! @ 0x1bc │ │ strdeq r4, [r2, ip] │ │ ldrdeq r5, [r2, ip] │ │ stc2l 12, cr10, [r3, #504]! @ 0x1f8 │ │ - stc2l 6, cr7, [r1, #840]! @ 0x348 │ │ + stc2l 6, cr7, [r1, #1020]! @ 0x3fc │ │ @ instruction: 0x01825798 │ │ orreq r4, r2, r4, lsl #21 │ │ orreq r9, r3, ip │ │ orreq r5, r2, r0, ror r7 │ │ stc2l 11, cr10, [r3, #936]! @ 0x3a8 @ │ │ - stc2l 6, cr7, [r1, #248]! @ 0xf8 │ │ + stc2l 6, cr7, [r1, #428]! @ 0x1ac │ │ strdeq r4, [r2, ip] │ │ orreq r8, r3, r8, lsl #31 │ │ stc2l 12, cr0, [r4, #184]! @ 0xb8 │ │ - stc2l 6, cr7, [r1, #8]! │ │ + stc2l 6, cr7, [r1, #188]! @ 0xbc │ │ @ instruction: 0x018249bc │ │ stc2l 11, cr10, [r3, #488]! @ 0x1e8 @ │ │ - stc2l 5, cr7, [r1, #824]! @ 0x338 │ │ + stc2l 5, cr7, [r1, #1004]! @ 0x3ec │ │ orreq r5, r2, r0, ror #14 │ │ - stc2l 12, cr7, [r1, #980]! @ 0x3d4 │ │ - stc2l 12, cr7, [r1, #936]! @ 0x3a8 │ │ + stc2l 13, cr7, [r1, #136]! @ 0x88 │ │ + stc2l 13, cr7, [r1, #92]! @ 0x5c │ │ orreq pc, r2, r4, lsl #20 │ │ @ instruction: 0x01825090 │ │ stc2l 6, cr2, [r4, #184]! @ 0xb8 │ │ - stc2l 5, cr7, [r1, #392]! @ 0x188 │ │ + stc2l 5, cr7, [r1, #572]! @ 0x23c │ │ orreq r4, r2, ip, lsl r9 │ │ stc2l 11, cr0, [r4, #388]! @ 0x184 @ │ │ - stc2l 5, cr7, [r1, #168]! @ 0xa8 │ │ + stc2l 5, cr7, [r1, #348]! @ 0x15c │ │ smlaleq sp, r7, r4, sp │ │ @ instruction: 0x018248bc │ │ - stc2l 12, cr12, [r2, #792]! @ 0x318 │ │ - stc2l 4, cr7, [r1, #840]! @ 0x348 │ │ + stc2l 12, cr12, [r2, #972]! @ 0x3cc │ │ + stc2l 4, cr7, [r1, #1020]! @ 0x3fc │ │ orreq r4, r2, ip, lsl #17 │ │ stc2l 5, cr2, [r4, #376]! @ 0x178 │ │ - stc2l 4, cr7, [r1, #584]! @ 0x248 │ │ + stc2l 4, cr7, [r1, #764]! @ 0x2fc │ │ orreq r5, r2, r0, lsl #8 │ │ orreq r5, r2, r0, lsl #10 │ │ orreq r5, r2, r0, lsr r5 │ │ orreq r7, r4, r8, lsr #16 │ │ orreq r5, r2, r4, ror #9 │ │ ldrdeq r5, [r2, r0] │ │ strdeq r4, [r2, ip] │ │ stc2l 10, cr0, [r4, #152]! @ 0x98 @ │ │ - stc2l 3, cr7, [r1, #1000]! @ 0x3e8 │ │ + stc2l 4, cr7, [r1, #156]! @ 0x9c │ │ @ instruction: 0x018247b8 │ │ @ instruction: 0x018254b0 │ │ @ instruction: 0x0182549c │ │ stc2l 9, cr0, [r4, #378]! @ 0x17a @ │ │ - stc2l 3, cr7, [r1, #552]! @ 0x228 │ │ + stc2l 3, cr7, [r1, #732]! @ 0x2dc │ │ orreq r5, r2, r8, asr #8 │ │ orreq r5, r2, ip, lsr r4 │ │ rsceq sp, r7, r4, ror #23 │ │ stc2l 6, cr1, [r1, #980]! @ 0x3d4 │ │ - stc2l 12, cr7, [r1, #596]! @ 0x254 │ │ - stc2l 12, cr7, [r1, #552]! @ 0x228 │ │ + stc2l 12, cr7, [r1, #776]! @ 0x308 │ │ + stc2l 12, cr7, [r1, #732]! @ 0x2dc │ │ orreq pc, r2, r4, lsr #19 │ │ orreq r5, r2, r0, lsr r0 │ │ stc2l 3, cr2, [r4, #664]! @ 0x298 │ │ - stc2l 2, cr7, [r1, #872]! @ 0x368 │ │ + stc2l 3, cr7, [r1, #28]! │ │ @ instruction: 0x01824694 │ │ stc2l 8, cr0, [r4, #868]! @ 0x364 │ │ - stc2l 2, cr7, [r1, #648]! @ 0x288 │ │ + stc2l 2, cr7, [r1, #828]! @ 0x33c │ │ orreq r4, r2, ip, lsr r6 │ │ - stc2l 10, cr12, [r2, #280]! @ 0x118 @ │ │ - stc2l 2, cr7, [r1, #328]! @ 0x148 │ │ + stc2l 10, cr12, [r2, #460]! @ 0x1cc @ │ │ + stc2l 2, cr7, [r1, #508]! @ 0x1fc │ │ orreq r4, r2, ip, lsl #12 │ │ stc2l 2, cr2, [r4, #888]! @ 0x378 │ │ - stc2l 2, cr7, [r1, #72]! @ 0x48 │ │ + stc2l 2, cr7, [r1, #252]! @ 0xfc │ │ orreq r5, r2, r0, lsl #3 │ │ orreq r5, r2, r0, lsl #5 │ │ @ instruction: 0x018252b0 │ │ orreq r7, r4, r8, lsr #11 │ │ orreq r5, r2, r4, ror #4 │ │ orreq r5, r2, r0, asr r1 │ │ orreq r4, r2, ip, ror r5 │ │ stc2l 7, cr0, [r4, #728]! @ 0x2d8 │ │ - stc2l 1, cr7, [r1, #552]! @ 0x228 │ │ + stc2l 1, cr7, [r1, #732]! @ 0x2dc │ │ orreq r4, r2, r8, asr #10 │ │ orreq r5, r2, r0, asr #4 │ │ orreq r5, r2, ip, lsr #4 │ │ stc2l 7, cr0, [r4, #276]! @ 0x114 │ │ - stc2l 1, cr7, [r1, #72]! @ 0x48 │ │ + stc2l 1, cr7, [r1, #252]! @ 0xfc │ │ ldrdeq r5, [r2, r0] │ │ orreq r5, r2, r4, asr #3 │ │ @ instruction: 0x0182449c │ │ orreq lr, r2, r0, ror #27 │ │ - stc2l 0, cr7, [r1, #532]! @ 0x214 │ │ - stc2l 0, cr7, [r1, #488]! @ 0x1e8 │ │ + stc2l 0, cr7, [r1, #712]! @ 0x2c8 │ │ + stc2l 0, cr7, [r1, #668]! @ 0x29c │ │ @ instruction: 0x0182ed94 │ │ orreq r4, r2, r0, lsr #8 │ │ stc2l 0, cr2, [r4, #936]! @ 0x3a8 │ │ - stc2l 0, cr7, [r1, #120]! @ 0x78 │ │ + stc2l 0, cr7, [r1, #300]! @ 0x12c │ │ ldrdeq r4, [r2, r8] │ │ stc2l 6, cr0, [r4, #116]! @ 0x74 │ │ - stc2l 15, cr6, [r1, #920]! @ 0x398 │ │ - stc2l 14, cr4, [r2, #980]! @ 0x3d4 │ │ + stc2l 0, cr7, [r1, #76]! @ 0x4c │ │ + stc2l 15, cr4, [r2, #136]! @ 0x88 │ │ │ │ 024087f0 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ beq 240880c │ │ @@ -1245280,15 +1245280,15 @@ │ │ add r0, pc, r0 │ │ bl 270da10 │ │ mov r0, r4 │ │ mov r1, #5 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, sl, fp, pc} │ │ - stc2l 11, cr2, [r2, #200]! @ 0xc8 @ │ │ + stc2l 11, cr2, [r2, #380]! @ 0x17c @ │ │ stc2l 12, cr1, [r4, #648]! @ 0x288 │ │ │ │ 0240884c : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #8 │ │ mov r1, r0 │ │ @@ -1245529,18 +1245529,18 @@ │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ stc2l 10, cr1, [r4, #780]! @ 0x30c @ │ │ stc2l 3, cr14, [r0, #412]! @ 0x19c │ │ - stc2l 6, cr4, [r1, #280]! @ 0x118 │ │ + stc2l 6, cr4, [r1, #460]! @ 0x1cc │ │ stc2l 3, cr0, [r3, #616]! @ 0x268 │ │ - stc2l 8, cr8, [r1, #996]! @ 0x3e4 │ │ - stc2l 7, cr2, [r2, #768]! @ 0x300 │ │ + stc2l 9, cr8, [r1, #76]! @ 0x4c @ │ │ + stc2l 7, cr2, [r2, #948]! @ 0x3b4 │ │ stc2l 2, cr10, [r0, #992]! @ 0x3e0 │ │ stc2l 9, cr1, [r4, #454]! @ 0x1c6 @ │ │ │ │ 02408be0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #36 @ 0x24 │ │ @@ -1246507,148 +1246507,148 @@ │ │ stc2l 2, cr10, [r0, #132]! @ 0x84 │ │ stc2l 3, cr12, [r0, #308]! @ 0x134 │ │ orreq r6, r4, r8, ror #26 │ │ orreq r6, r4, r8, asr #23 │ │ eorseq pc, r3, r0, lsr r9 @ │ │ orreq r6, r4, r0, lsr #29 │ │ eorseq pc, r3, r0, lsl #18 │ │ - stc2l 6, cr4, [r2, #732]! @ 0x2dc │ │ + stc2l 6, cr4, [r2, #912]! @ 0x390 │ │ stc2l 7, cr5, [r4, #48]! @ 0x30 │ │ orreq r6, r4, r4, ror #31 │ │ stc2l 10, cr9, [r0, #436]! @ 0x1b4 @ │ │ stc2l 0, cr5, [r4, #112]! @ 0x70 │ │ orreq r6, r4, r4, asr #11 │ │ stc2l 7, cr11, [r0, #20]! │ │ stc2l 11, cr4, [r4, #368]! @ 0x170 @ │ │ orreq r6, r4, r0, lsl r1 │ │ - stc2l 3, cr11, [r2, #532]! @ 0x214 │ │ + stc2l 3, cr11, [r2, #712]! @ 0x2c8 │ │ stc2l 11, cr4, [r4, #144]! @ 0x90 @ │ │ @ instruction: 0x0185ffb4 │ │ strexeq pc, ip, [r5] @ │ │ strexeq pc, r8, [r5] @ │ │ stc2l 9, cr9, [r0, #442]! @ 0x1ba @ │ │ stc2l 15, cr4, [r4, #560]! @ 0x230 │ │ stc2l 11, cr11, [r0, #20]! @ │ │ stc2l 15, cr4, [r4, #368]! @ 0x170 │ │ orreq r6, r4, r8, lsl r5 │ │ eorseq pc, r3, r0, lsl #2 │ │ - stc2l 14, cr3, [r2, #492]! @ 0x1ec │ │ + stc2l 14, cr3, [r2, #672]! @ 0x2a0 │ │ stc2l 14, cr4, [r4, #832]! @ 0x340 │ │ orreq r6, r4, r8, lsr #15 │ │ eorseq pc, r3, r0, rrx │ │ strdeq r6, [r4, r8] │ │ orreq pc, r5, r8, lsl #15 │ │ orreq pc, r5, ip, ror #14 │ │ - stc2l 6, cr11, [r2, #788]! @ 0x314 │ │ + stc2l 6, cr11, [r2, #968]! @ 0x3c8 │ │ stc2l 14, cr4, [r4, #400]! @ 0x190 │ │ @ instruction: 0x0184699c │ │ stc2l 5, cr5, [r4, #368]! @ 0x170 │ │ stc2l 15, cr9, [r0, #436]! @ 0x1b4 │ │ stc2l 0, cr12, [r0, #612]! @ 0x264 │ │ @ instruction: 0x01846ab4 │ │ orreq r6, r4, r4, lsl r9 │ │ eorseq pc, r3, ip, ror r6 @ │ │ orreq r6, r4, ip, ror #23 │ │ eorseq pc, r3, ip, asr #12 │ │ - stc2l 3, cr4, [r2, #972]! @ 0x3cc │ │ + stc2l 4, cr4, [r2, #128]! @ 0x80 │ │ stc2l 4, cr5, [r4, #288]! @ 0x120 │ │ orreq r6, r4, r0, lsr #26 │ │ stc2l 10, cr9, [r0, #148]! @ 0x94 @ │ │ stc2l 15, cr4, [r4, #848]! @ 0x350 │ │ orreq r6, r4, ip, ror r5 │ │ stc2l 6, cr11, [r0, #692]! @ 0x2b4 │ │ stc2l 11, cr4, [r4, #16]! @ │ │ strheq r6, [r4, r8] │ │ - stc2l 3, cr11, [r2, #180]! @ 0xb4 │ │ + stc2l 3, cr11, [r2, #360]! @ 0x168 │ │ stc2l 10, cr4, [r4, #816]! @ 0x330 @ │ │ orreq pc, r5, r4, ror #25 │ │ orreq pc, r5, ip, asr #25 │ │ orreq pc, r5, r8, asr #25 │ │ stc2l 8, cr9, [r0, #628]! @ 0x274 │ │ stc2l 14, cr4, [r4, #304]! @ 0x130 │ │ stc2l 9, cr11, [r0, #394]! @ 0x18a @ │ │ stc2l 14, cr4, [r4, #112]! @ 0x70 │ │ ldrdeq r6, [r4, r8] │ │ eorseq lr, r3, r0, asr #31 │ │ - stc2l 13, cr3, [r2, #236]! @ 0xec │ │ + stc2l 13, cr3, [r2, #416]! @ 0x1a0 │ │ stc2l 13, cr4, [r4, #576]! @ 0x240 │ │ orreq r6, r4, r8, ror #12 │ │ eorseq lr, r3, r0, lsr #30 │ │ @ instruction: 0x018464b8 │ │ orreq pc, r5, r8, asr #12 │ │ orreq pc, r5, ip, lsr #12 │ │ - stc2l 5, cr11, [r2, #532]! @ 0x214 │ │ + stc2l 5, cr11, [r2, #712]! @ 0x2c8 │ │ stc2l 13, cr4, [r4, #144]! @ 0x90 │ │ orreq r6, r4, r4, lsr #15 │ │ stc2l 3, cr5, [r4, #400]! @ 0x190 │ │ stc2l 13, cr9, [r0, #692]! @ 0x2b4 │ │ stc2l 14, cr11, [r0, #548]! @ 0x224 │ │ @ instruction: 0x0184689c │ │ eorseq pc, r3, r0, lsl #9 │ │ strdeq r6, [r4, r8] │ │ eorseq pc, r3, r8, asr r4 @ │ │ - stc2l 2, cr4, [r2, #60]! @ 0x3c │ │ + stc2l 2, cr4, [r2, #240]! @ 0xf0 │ │ stc2l 2, cr5, [r4, #400]! @ 0x190 │ │ orreq r6, r4, ip, lsr fp │ │ stc2l 7, cr9, [r0, #372]! @ 0x174 │ │ stc2l 13, cr4, [r4, #48]! @ 0x30 │ │ @ instruction: 0x018462b4 │ │ stc2l 6, cr11, [r0, #340]! @ 0x154 │ │ stc2l 10, cr4, [r4, #688]! @ 0x2b0 @ │ │ orreq r6, r4, r0, rrx │ │ - stc2l 2, cr11, [r2, #852]! @ 0x354 │ │ + stc2l 3, cr11, [r2, #8]! │ │ stc2l 10, cr4, [r4, #464]! @ 0x1d0 @ │ │ orreq pc, r5, r8, lsl #22 │ │ strdeq pc, [r5, r0] │ │ orreq pc, r5, ip, ror #21 │ │ stc2l 7, cr9, [r0, #84]! @ 0x54 │ │ stc2l 12, cr4, [r4, #784]! @ 0x310 │ │ stc2l 8, cr11, [r0, #244]! @ 0xf4 │ │ stc2l 12, cr4, [r4, #592]! @ 0x250 │ │ orreq r6, r4, r0, asr r2 │ │ eorseq lr, r3, r8, lsr lr │ │ - stc2l 11, cr3, [r2, #700]! @ 0x2bc @ │ │ + stc2l 11, cr3, [r2, #880]! @ 0x370 @ │ │ stc2l 12, cr4, [r4, #16]! │ │ ldrdeq r6, [r4, ip] │ │ mlaseq r3, r4, sp, lr │ │ orreq r6, r4, ip, lsr #6 │ │ @ instruction: 0x0185f4bc │ │ orreq pc, r5, r0, lsr #9 │ │ - stc2l 3, cr11, [r2, #996]! @ 0x3e4 │ │ + stc2l 4, cr11, [r2, #152]! @ 0x98 │ │ stc2l 11, cr4, [r4, #608]! @ 0x260 @ │ │ stc2l 6, cr1, [r4, #968]! @ 0x3c8 │ │ orreq r6, r4, r0, lsl #12 │ │ orreq r6, r4, ip, lsl #15 │ │ - stc2l 15, cr1, [r2, #992]! @ 0x3e0 │ │ + stc2l 0, cr2, [r2, #148]! @ 0x94 │ │ orreq pc, r5, r0, ror #20 │ │ eorseq pc, r3, r4, lsl r3 @ │ │ ldrshteq pc, [r3], -r8 @ │ │ - stc2l 0, cr4, [r2, #444]! @ 0x1bc │ │ + stc2l 0, cr4, [r2, #624]! @ 0x270 │ │ stc2l 0, cr5, [r4, #784]! @ 0x310 │ │ @ instruction: 0x0184699c │ │ eorseq pc, r3, r0, lsl #5 │ │ stc2l 4, cr9, [r0, #660]! @ 0x294 │ │ stc2l 10, cr4, [r4, #336]! @ 0x150 @ │ │ stc2l 5, cr11, [r0, #404]! @ 0x194 │ │ stc2l 9, cr4, [r4, #376]! @ 0x178 @ │ │ - stc2l 1, cr11, [r2, #964]! @ 0x3c4 │ │ + stc2l 2, cr11, [r2, #120]! @ 0x78 │ │ stc2l 9, cr4, [r4, #288]! @ 0x120 @ │ │ orreq r6, r4, r0, lsl #3 │ │ stc2l 11, cr0, [r4, #340]! @ 0x154 @ │ │ - stc2l 4, cr9, [r1, #660]! @ 0x294 │ │ - stc2l 9, cr5, [r2, #168]! @ 0xa8 @ │ │ + stc2l 4, cr9, [r1, #840]! @ 0x348 │ │ + stc2l 9, cr5, [r2, #258]! @ 0x102 @ │ │ stc2l 11, cr0, [r4, #120]! @ 0x78 @ │ │ orreq pc, r5, r0, ror #30 │ │ orreq pc, r5, r8, asr pc @ │ │ - stc2l 5, cr6, [r2, #420]! @ 0x1a4 │ │ + stc2l 5, cr6, [r2, #600]! @ 0x258 │ │ vcmla.f16 q15, q8, q11, #270 │ │ - stc2l 0, cr10, [r1, #548]! @ 0x224 │ │ + stc2l 0, cr10, [r1, #728]! @ 0x2d8 │ │ vcmla.f16 d29, d3, d11, #270 │ │ eorseq pc, r3, r4, lsl r5 @ │ │ - stc2l 2, cr4, [r1, #920]! @ 0x398 │ │ + stc2l 3, cr4, [r1, #76]! @ 0x4c │ │ stc2l 15, cr7, [r3, #592]! @ 0x250 │ │ │ │ 02409d24 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ @@ -1246825,17 +1246825,17 @@ │ │ mov r0, r5 │ │ mov r2, r4 │ │ mov r3, #255 @ 0xff │ │ bl 270da60 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - stc2l 3, cr1, [r2, #988]! @ 0x3dc │ │ + stc2l 4, cr1, [r2, #144]! @ 0x90 │ │ eorseq lr, r3, r4, asr #13 │ │ - stc2l 4, cr7, [r1, #912]! @ 0x390 │ │ + stc2l 5, cr7, [r1, #68]! @ 0x44 │ │ @ instruction: 0x0185edbc │ │ │ │ 02409fd0 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #16 │ │ ldr r1, [r1] │ │ @@ -1247098,27 +1247098,27 @@ │ │ ldr r0, [pc, #68] @ 240a414 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - stc2l 0, cr15, [r1, #868]! @ 0x364 │ │ - stc2l 14, cr2, [r1, #664]! @ 0x298 │ │ + stc2l 1, cr15, [r1, #24]! │ │ + stc2l 14, cr2, [r1, #844]! @ 0x34c │ │ stc2l 2, cr0, [r4, #296]! @ 0x128 │ │ stc2l 12, cr0, [r3, #624]! @ 0x270 │ │ - stc2l 0, cr1, [r2, #64]! @ 0x40 │ │ + stc2l 0, cr1, [r2, #244]! @ 0xf4 │ │ orreq lr, r5, r4, ror #28 │ │ eorseq lr, r3, r0, asr #6 │ │ eorseq lr, r3, r8, lsr #6 │ │ stc2l 12, cr10, [r0, #716]! @ 0x2cc │ │ - stc2l 11, cr8, [r1, #612]! @ 0x264 @ │ │ + stc2l 11, cr8, [r1, #792]! @ 0x318 @ │ │ stc2l 12, cr0, [r3, #900]! @ 0x384 │ │ - stc2l 11, cr8, [r1, #308]! @ 0x134 @ │ │ - stc2l 15, cr14, [r1, #580]! @ 0x244 │ │ + stc2l 11, cr8, [r1, #488]! @ 0x1e8 @ │ │ + stc2l 15, cr14, [r1, #760]! @ 0x2f8 │ │ │ │ 0240a418 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #16 │ │ mov r4, r3 │ │ mov r5, r2 │ │ @@ -1247206,27 +1247206,27 @@ │ │ ldr r0, [pc, #68] @ 240a5bc │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - stc2l 15, cr2, [r2, #772]! @ 0x304 │ │ - stc2l 14, cr0, [r2, #528]! @ 0x210 │ │ + stc2l 15, cr2, [r2, #952]! @ 0x3b8 │ │ + stc2l 14, cr0, [r2, #708]! @ 0x2c4 │ │ ldrdeq lr, [r5, ip] │ │ stc2l 11, cr0, [r3, #84]! @ 0x54 @ │ │ - stc2l 14, cr0, [r2, #232]! @ 0xe8 │ │ - stc2l 9, cr8, [r1, #354]! @ 0x162 @ │ │ + stc2l 14, cr0, [r2, #412]! @ 0x19c │ │ + stc2l 9, cr8, [r1, #444]! @ 0x1bc @ │ │ stc2l 10, cr0, [r3, #880]! @ 0x370 @ │ │ ldrhteq lr, [r3], -r0 │ │ mlaseq r3, r8, r1, lr │ │ - stc2l 0, cr11, [r1, #860]! @ 0x35c │ │ - stc2l 9, cr8, [r1, #482]! @ 0x1e2 @ │ │ + stc2l 1, cr11, [r1, #16]! │ │ + stc2l 10, cr8, [r1, #120]! @ 0x78 @ │ │ stc2l 5, cr8, [r3, #188]! @ 0xbc │ │ - stc2l 14, cr2, [r2, #580]! @ 0x244 │ │ + stc2l 14, cr2, [r2, #760]! @ 0x2f8 │ │ │ │ 0240a5c0 : │ │ vldr d16, [pc, #8] @ 240a5d0 │ │ vmov r0, r1, d16 │ │ bx lr │ │ nop {0} │ │ @ instruction: 0xffffffff │ │ @@ -1248203,15 +1248203,15 @@ │ │ eorseq pc, r3, r4, lsl pc @ │ │ @ instruction: 0x01916198 │ │ eorseq pc, r3, r4, lsl #30 │ │ @ instruction: 0x0188d894 │ │ orreq lr, r5, r0, asr #20 │ │ orreq lr, r5, r0, asr #20 │ │ stc2l 3, cr14, [r3, #696]! @ 0x2b8 │ │ - stc2l 14, cr10, [r1, #668]! @ 0x29c │ │ + stc2l 14, cr10, [r1, #848]! @ 0x350 │ │ ldrdeq lr, [r5, ip] │ │ @ instruction: 0x0187d9bc │ │ orreq pc, r7, r8, asr #18 │ │ @ instruction: 0x0185e9b0 │ │ mov r7, r2 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ @@ -1248376,15 +1248376,15 @@ │ │ str r2, [r0] │ │ mov r0, #1 │ │ strb r0, [r1] │ │ b 2413cc8 │ │ orreq sp, r8, r0, asr #28 │ │ orreq sp, r8, ip, asr #15 │ │ stc2l 14, cr15, [r3, #264]! @ 0x108 │ │ - stc2l 13, cr4, [r1, #216]! @ 0xd8 │ │ + stc2l 13, cr4, [r1, #396]! @ 0x18c │ │ bl 270ce80 │ │ cmp r0, #0 │ │ bne 2413258 │ │ ldr r4, [pc, #4056] @ 240c7ac │ │ mov r1, #6 │ │ add r4, pc, r4 │ │ mov r0, r4 │ │ @@ -1248393,16 +1248393,16 @@ │ │ mov r1, #17 │ │ add r0, pc, r0 │ │ b 2410458 │ │ stc2l 0, cr10, [r3, #708]! @ 0x2c4 │ │ orreq lr, r5, r8, ror #17 │ │ orreq sp, r7, ip, lsl r9 │ │ @ instruction: 0x0187d5b0 │ │ - stc2l 3, cr12, [r2, #200]! @ 0xc8 │ │ - stc2l 12, cr4, [r1, #280]! @ 0x118 │ │ + stc2l 3, cr12, [r2, #380]! @ 0x17c │ │ + stc2l 12, cr4, [r1, #460]! @ 0x1cc │ │ orreq sp, r7, ip, lsl #14 │ │ orreq sp, r7, r4, ror #16 │ │ ldr r0, [pc, #4068] @ 240c7fc │ │ ldr r1, [pc, #4068] @ 240c800 │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ bl 270e110 │ │ @@ -1248458,29 +1248458,29 @@ │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #4088] @ 240c8f0 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ b 2413254 │ │ stc2l 14, cr12, [r0, #684]! @ 0x2ac │ │ - stc2l 12, cr4, [r1, #8]! │ │ + stc2l 12, cr4, [r1, #188]! @ 0xbc │ │ orreq sp, r7, r8, lsr r5 │ │ orreq r4, r6, r8, asr #27 │ │ stc2l 5, cr6, [r3, #224]! @ 0xe0 │ │ - stc2l 11, cr4, [r1, #744]! @ 0x2e8 @ │ │ + stc2l 11, cr4, [r1, #924]! @ 0x39c @ │ │ @ instruction: 0x0187d5b8 │ │ orreq r4, r6, r4, lsl #27 │ │ orreq sp, r7, r8, asr #15 │ │ stc2l 5, cr14, [r2, #916]! @ 0x394 │ │ - stc2l 11, cr4, [r1, #456]! @ 0x1c8 @ │ │ + stc2l 11, cr4, [r1, #636]! @ 0x27c @ │ │ orreq r4, r6, r4, asr #26 │ │ @ instruction: 0x0187d79c │ │ orreq sp, r7, r4, lsl #15 │ │ stc2l 5, cr2, [r3, #748]! @ 0x2ec │ │ - stc2l 11, cr4, [r1, #168]! @ 0xa8 @ │ │ + stc2l 11, cr4, [r1, #348]! @ 0x15c @ │ │ ldr r0, [pc, #4012] @ 240c8f4 │ │ ldr r1, [pc, #4012] @ 240c8f8 │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ bl 270e110 │ │ ldr r0, [pc, #4088] @ 240c954 │ │ ldr r1, [pc, #4088] @ 240c958 │ │ @@ -1248522,15 +1248522,15 @@ │ │ ldr r0, [pc, #4072] @ 240c9d8 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ b 2413254 │ │ @ instruction: 0x0191acd0 │ │ orreq r4, r6, r8, ror #25 │ │ stc2l 5, cr2, [r3, #476]! @ 0x1dc │ │ - stc2l 10, cr4, [r1, #920]! @ 0x398 @ │ │ + stc2l 11, cr4, [r1, #76]! @ 0x4c @ │ │ @ instruction: 0x0187f694 │ │ orreq r1, r9, r8, ror #26 │ │ ldrdeq r8, [r8, r0] │ │ orreq fp, r8, r8, lsr #25 │ │ strdeq r1, [r7, r0] │ │ eorseq lr, r3, r8, lsl #23 │ │ orreq sl, r8, r4, ror r9 │ │ @@ -1248662,15 +1248662,15 @@ │ │ ldr r0, [pc, #3932] @ 240cb7c │ │ mov r1, #5 │ │ add r0, pc, r0 │ │ b 2413254 │ │ orreq sp, r8, r4, asr r3 │ │ @ instruction: 0x0187f4bc │ │ stc2l 9, cr15, [r3, #332]! @ 0x14c @ │ │ - stc2l 8, cr4, [r1, #616]! @ 0x268 │ │ + vcmla.f16 q10, , , #270 │ │ orreq sp, r8, r8, ror #18 │ │ orreq sp, r7, ip, lsr #9 │ │ str r4, [fp, #-40] @ 0xffffffd8 │ │ str r6, [fp, #-36] @ 0xffffffdc │ │ ldr r6, [pc, #3888] @ 240cb80 │ │ add r6, pc, r6 │ │ ldr r4, [pc, #3884] @ 240cb84 │ │ @@ -1248694,17 +1248694,17 @@ │ │ ldr r4, [pc, #4048] @ 240cc70 │ │ ldr r5, [pc, #4048] @ 240cc74 │ │ ldr sl, [pc, #4048] @ 240cc78 │ │ add r4, pc, r4 │ │ add r5, pc, r5 │ │ add sl, pc, sl │ │ b 240bd84 │ │ - stc2l 6, cr4, [r2, #1012]! @ 0x3f4 │ │ - stc2l 2, cr8, [r1, #52]! @ 0x34 │ │ - stc2l 1, cr8, [r2, #372]! @ 0x174 │ │ + stc2l 7, cr4, [r2, #168]! @ 0xa8 │ │ + stc2l 2, cr8, [r1, #232]! @ 0xe8 │ │ + stc2l 1, cr8, [r2, #552]! @ 0x228 │ │ orreq lr, r5, ip, lsr #8 │ │ orreq sp, r7, r0, ror #8 │ │ orreq sp, r7, r0, lsl #2 │ │ orreq pc, r7, r8, ror r3 @ │ │ orreq r6, r9, ip, ror #16 │ │ orreq r1, r9, r4, asr #20 │ │ orreq r8, r8, ip, lsr #7 │ │ @@ -1248716,15 +1248716,15 @@ │ │ orreq ip, r8, r0, lsr #18 │ │ @ instruction: 0x01881290 │ │ orreq r0, r7, r8, ror #9 │ │ orreq sl, r8, r0, asr r6 │ │ orreq r6, r9, r8, lsr #22 │ │ orreq pc, r7, r0, ror #5 │ │ strdeq pc, [r7, r4] │ │ - stc2l 7, cr0, [r1, #900]! @ 0x384 │ │ + vcmla.f16 d16, d1, d14, #270 │ │ orreq lr, r5, r8, lsl r3 │ │ orreq pc, r7, r0, lsr #5 │ │ orreq pc, r7, r0, lsl #5 │ │ orreq lr, r5, r4, ror #5 │ │ ldr r1, [pc, #3924] @ 240cc7c │ │ mov r2, #64 @ 0x40 │ │ mov r3, #64 @ 0x40 │ │ @@ -1248809,15 +1248809,15 @@ │ │ ldr r6, [pc, #4076] @ 240ce58 │ │ add r6, pc, r6 │ │ bne 240bd68 │ │ b 240f964 │ │ strdeq r1, [r8, r4] │ │ orreq sp, r8, r0, lsr r0 │ │ stc2l 6, cr15, [r3, #692]! @ 0x2b4 │ │ - stc2l 6, cr4, [r1, #376]! @ 0x178 │ │ + stc2l 6, cr4, [r1, #556]! @ 0x22c │ │ ldr r0, [pc, #4048] @ 240ce5c │ │ ldr r0, [pc, r0] │ │ sub r7, r0, #1 │ │ cmp r7, #10 │ │ mov r0, r7 │ │ bcc 240bd20 │ │ ldr r0, [pc, #4028] @ 240ce60 │ │ @@ -1248869,15 +1248869,15 @@ │ │ ldr r8, [pc, #3952] @ 240cecc │ │ add sl, pc, sl │ │ add r8, pc, r8 │ │ b 240bfa4 │ │ orreq sp, r8, r0, lsl #13 │ │ orreq sp, r8, ip │ │ stc2l 6, cr15, [r3, #488]! @ 0x1e8 │ │ - stc2l 5, cr4, [r1, #440]! @ 0x1b8 │ │ + stc2l 5, cr4, [r1, #620]! @ 0x26c │ │ ldr r0, [pc, #3924] @ 240ced0 │ │ mov r1, r6 │ │ add r0, pc, r0 │ │ add r2, r0, r4, lsl #2 │ │ ldr r0, [fp, #12] │ │ bl 270e390 │ │ ldr r4, [pc, #3904] @ 240ced4 │ │ @@ -1248928,24 +1248928,24 @@ │ │ orreq r6, r9, ip, ror #16 │ │ eorseq pc, r3, r4, asr #10 │ │ orrseq r5, r1, r8, asr #15 │ │ eorseq pc, r3, r4, lsr r5 @ │ │ orreq ip, r8, r4, asr #29 │ │ orreq lr, r5, r4, ror r0 │ │ orreq lr, r5, r0, ror r0 │ │ - stc2l 11, cr9, [r2, #1000]! @ 0x3e8 @ │ │ + stc2l 12, cr9, [r2, #156]! @ 0x9c │ │ orreq r1, r7, r0, ror r1 │ │ stc2l 6, cr11, [r3, #220]! @ 0xdc │ │ orreq ip, r7, r8, lsr sp │ │ stc2l 15, cr15, [r2, #348]! @ 0x15c │ │ orreq r0, r7, r0, lsl #3 │ │ @ instruction: 0x0187efb4 │ │ orreq r1, r7, ip, lsl r1 │ │ orrseq r0, r2, r8, asr #23 │ │ - stc2l 3, cr4, [r1, #616]! @ 0x268 │ │ + stc2l 3, cr4, [r1, #796]! @ 0x31c │ │ orrseq r0, r2, r8, lsr #28 │ │ orreq lr, r7, ip, asr #30 │ │ ldr r8, [pc, #3996] @ 240d030 │ │ ldr r0, [pc, #3996] @ 240d034 │ │ add r8, pc, r8 │ │ ldr r0, [pc, r0] │ │ str r0, [r8] │ │ @@ -1249043,15 +1249043,15 @@ │ │ mov r1, #34 @ 0x22 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #3984] @ 240d1b0 │ │ mov r1, #20 │ │ add r0, pc, r0 │ │ b 2410694 │ │ - stc2l 2, cr6, [r1, #284]! @ 0x11c │ │ + stc2l 2, cr6, [r1, #464]! @ 0x1d0 │ │ orreq sp, r5, ip, ror #29 │ │ ldr r0, [pc, #3964] @ 240d1b4 │ │ mov r1, #74 @ 0x4a │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #3952] @ 240d1b8 │ │ mov r2, #1 │ │ @@ -1249080,16 +1249080,16 @@ │ │ add r5, pc, r5 │ │ add r1, pc, r1 │ │ mov r0, r5 │ │ bl 270db00 │ │ mov r0, r5 │ │ mov r1, r8 │ │ b 2410444 │ │ - stc2l 9, cr11, [r2, #108]! @ 0x6c @ │ │ - stc2l 2, cr4, [r1, #296]! @ 0x128 │ │ + stc2l 9, cr11, [r2, #198]! @ 0xc6 @ │ │ + stc2l 2, cr4, [r1, #476]! @ 0x1dc │ │ orreq ip, r7, r0, lsl sp │ │ orreq ip, r7, r8, ror #28 │ │ ldr r0, [pc, #4020] @ 240d288 │ │ mov r1, #74 @ 0x4a │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #4008] @ 240d28c │ │ @@ -1249099,15 +1249099,15 @@ │ │ add r1, pc, r1 │ │ mov r0, r4 │ │ bl 270db00 │ │ mov r0, r4 │ │ mov r1, r8 │ │ b 2410628 │ │ stc2l 4, cr12, [r0, #684]! @ 0x2ac │ │ - stc2l 2, cr4, [r1, #8]! │ │ + stc2l 2, cr4, [r1, #188]! @ 0xbc │ │ orreq ip, r7, r8, lsr fp │ │ orreq r4, r6, r8, asr #7 │ │ stc2l 11, cr5, [r3, #240]! @ 0xf0 @ │ │ ldr r0, [pc, #3956] @ 240d294 │ │ mov r1, #74 @ 0x4a │ │ add r0, pc, r0 │ │ bl 270da00 │ │ @@ -1249117,20 +1249117,20 @@ │ │ add r4, pc, r4 │ │ add r1, pc, r1 │ │ mov r0, r4 │ │ bl 270db00 │ │ mov r0, r4 │ │ mov r1, r8 │ │ b 2410680 │ │ - stc2l 1, cr4, [r1, #760]! @ 0x2f8 │ │ + stc2l 1, cr4, [r1, #940]! @ 0x3ac │ │ @ instruction: 0x0187cbbc │ │ orreq r4, r6, r8, lsl #7 │ │ orreq ip, r7, ip, asr #27 │ │ stc2l 11, cr13, [r2, #932]! @ 0x3a4 @ │ │ - stc2l 1, cr4, [r1, #472]! @ 0x1d8 │ │ + stc2l 1, cr4, [r1, #652]! @ 0x28c │ │ orreq r4, r6, r8, asr #6 │ │ orreq ip, r7, r0, lsr #27 │ │ orreq ip, r7, r8, lsl #27 │ │ ldr r5, [pc, #3876] @ 240d2a0 │ │ ldr r5, [pc, r5] │ │ ldr r0, [pc, #3872] @ 240d2a4 │ │ mov r2, #0 │ │ @@ -1249152,15 +1249152,15 @@ │ │ add r8, pc, r8 │ │ ldr r5, [pc, #4072] @ 240d3b4 │ │ add r9, pc, r9 │ │ add r7, pc, r7 │ │ add r5, pc, r5 │ │ b 240c450 │ │ stc2l 11, cr1, [r3, #764]! @ 0x2fc @ │ │ - stc2l 1, cr4, [r1, #184]! @ 0xb8 │ │ + stc2l 1, cr4, [r1, #364]! @ 0x16c │ │ @ instruction: 0x0191a2d4 │ │ ldrdeq lr, [r7, r4] │ │ orreq r6, r9, ip, asr #3 │ │ orreq r1, r9, r4, lsr #7 │ │ orreq r7, r8, r0, lsl sp │ │ orreq r9, sl, ip, lsl #27 │ │ orreq r0, r7, r8, lsr #28 │ │ @@ -1249236,34 +1249236,34 @@ │ │ add r0, pc, r0 │ │ add r3, r0, ip, lsl #2 │ │ b 240c5e8 │ │ stc2l 5, cr7, [r3, #592]! @ 0x250 │ │ orreq sp, r5, r0, lsl #24 │ │ orreq ip, r7, r4, lsr ip │ │ orreq ip, r7, r8, asr #17 │ │ - stc2l 6, cr11, [r2, #296]! @ 0x128 │ │ - stc2l 15, cr3, [r1, #376]! @ 0x178 │ │ + stc2l 6, cr11, [r2, #476]! @ 0x1dc │ │ + stc2l 15, cr3, [r1, #556]! @ 0x22c │ │ orreq ip, r7, r4, lsr #20 │ │ orreq ip, r7, ip, ror fp │ │ stc2l 1, cr12, [r0, #764]! @ 0x2fc │ │ - stc2l 15, cr3, [r1, #88]! @ 0x58 │ │ + stc2l 15, cr3, [r1, #268]! @ 0x10c │ │ orreq ip, r7, ip, asr #16 │ │ ldrdeq r4, [r6, ip] │ │ stc2l 8, cr5, [r3, #320]! @ 0x140 │ │ - stc2l 14, cr3, [r1, #840]! @ 0x348 │ │ + stc2l 14, cr3, [r1, #1020]! @ 0x3fc │ │ ldrdeq ip, [r7, r0] │ │ @ instruction: 0x0186409c │ │ orreq ip, r7, r0, ror #21 │ │ stc2l 8, cr13, [r2, #1012]! @ 0x3f4 │ │ - stc2l 14, cr3, [r1, #552]! @ 0x228 │ │ + stc2l 14, cr3, [r1, #732]! @ 0x2dc │ │ orreq r4, r6, ip, asr r0 │ │ @ instruction: 0x0187cab4 │ │ @ instruction: 0x0187ca9c │ │ stc2l 8, cr1, [r3, #844]! @ 0x34c │ │ - stc2l 14, cr3, [r1, #264]! @ 0x108 │ │ + stc2l 14, cr3, [r1, #444]! @ 0x1bc │ │ orrseq r9, r1, r8, ror #31 │ │ orreq lr, r7, r8, ror #19 │ │ strheq r1, [r9, ip] │ │ orreq r7, r8, r4, lsr #20 │ │ strdeq sl, [r8, ip] │ │ orreq r0, r7, r4, asr #22 │ │ ldrsbteq sp, [r3], -ip │ │ @@ -1249396,15 +1249396,15 @@ │ │ add r1, pc, r1 │ │ add lr, r1, r0, lsl #2 │ │ lsr r0, ip, #3 │ │ cmp r0, #124 @ 0x7c │ │ bhi 240c7b4 │ │ ldr r3, [fp, #-68] @ 0xffffffbc │ │ b 240c5f8 │ │ - stc2l 7, cr7, [r2, #804]! @ 0x324 │ │ + stc2l 7, cr7, [r2, #984]! @ 0x3d8 │ │ stc2l 12, cr14, [r3, #904]! @ 0x388 │ │ str lr, [fp, #-76] @ 0xffffffb4 │ │ mov r1, ip │ │ ldr r0, [pc, #3984] @ 240d754 │ │ mov r2, sl │ │ movw r3, #5057 @ 0x13c1 │ │ add r0, pc, r0 │ │ @@ -1249453,16 +1249453,16 @@ │ │ ldr lr, [fp, #-76] @ 0xffffffb4 │ │ ldr r6, [fp, #-80] @ 0xffffffb0 │ │ b 240c610 │ │ orreq sp, r5, r0, asr #17 │ │ orreq lr, r7, r0, asr r8 │ │ @ instruction: 0x0187c8b8 │ │ stc2l 0, cr9, [r3, #96]! @ 0x60 │ │ - stc2l 6, cr7, [r1, #164]! @ 0xa4 │ │ - stc2l 2, cr11, [r2, #1008]! @ 0x3f0 │ │ + stc2l 6, cr7, [r1, #344]! @ 0x158 │ │ + stc2l 3, cr11, [r2, #164]! @ 0xa4 │ │ str r7, [sp, #84] @ 0x54 │ │ mov r1, ip │ │ ldr r0, [pc, #4080] @ 240d898 │ │ mov r2, r4 │ │ movw r3, #5057 @ 0x13c1 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ @@ -1249477,15 +1249477,15 @@ │ │ cmp r0, #124 @ 0x7c │ │ bhi 240c8fc │ │ ldr r3, [fp, #-68] @ 0xffffffbc │ │ ldr lr, [fp, #-76] @ 0xffffffb4 │ │ ldr r6, [fp, #-80] @ 0xffffffb0 │ │ ldr r7, [sp, #84] @ 0x54 │ │ b 240c620 │ │ - stc2l 13, cr9, [r1, #92]! @ 0x5c │ │ + stc2l 13, cr9, [r1, #272]! @ 0x110 │ │ mlaseq r3, ip, ip, lr │ │ orreq ip, r8, ip, ror #10 │ │ str r5, [sp, #80] @ 0x50 │ │ mov r1, ip │ │ ldr r0, [pc, #3992] @ 240d8a4 │ │ mov r2, r4 │ │ movw r3, #5057 @ 0x13c1 │ │ @@ -1249534,15 +1249534,15 @@ │ │ bhi 240c9dc │ │ ldr r3, [fp, #-68] @ 0xffffffbc │ │ ldr lr, [fp, #-76] @ 0xffffffb4 │ │ ldr r6, [fp, #-80] @ 0xffffffb0 │ │ ldr r7, [sp, #84] @ 0x54 │ │ ldr r5, [sp, #80] @ 0x50 │ │ b 240c638 │ │ - stc2l 11, cr9, [r1, #528]! @ 0x210 @ │ │ + stc2l 11, cr9, [r1, #708]! @ 0x2c4 @ │ │ stc2l 14, cr13, [r0, #584]! @ 0x248 │ │ ldr r0, [pc, #3800] @ 240d8bc │ │ mov r1, ip │ │ mov r2, r4 │ │ movw r3, #5057 @ 0x13c1 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ @@ -1249638,16 +1249638,16 @@ │ │ eorseq lr, r3, ip, asr sl │ │ orreq ip, r8, ip, ror #7 │ │ @ instruction: 0x0185d594 │ │ @ instruction: 0x0185d590 │ │ orreq lr, r7, r0, lsr #10 │ │ orreq ip, r7, r8, lsl #11 │ │ stc2l 12, cr8, [r3, #960]! @ 0x3c0 │ │ - stc2l 3, cr7, [r1, #4]! │ │ - stc2l 15, cr10, [r2, #848]! @ 0x350 │ │ + stc2l 3, cr7, [r1, #184]! @ 0xb8 │ │ + stc2l 0, cr11, [r2, #4]! │ │ stc2l 11, cr10, [r3, #164]! @ 0xa4 @ │ │ orreq lr, r7, ip, lsr #9 │ │ eorseq lr, r3, r4, lsr #19 │ │ orrseq r0, r2, r8, lsr #14 │ │ ldr r0, [pc, #4016] @ 240db44 │ │ add r0, pc, r0 │ │ add r0, r0, r1, lsl #2 │ │ @@ -1249702,15 +1249702,15 @@ │ │ ldr r0, [r2, r1, lsl #2] │ │ add r0, r0, #3 │ │ str r0, [fp, #-48] @ 0xffffffd0 │ │ b 240cd10 │ │ orreq ip, r7, r4, ror #9 │ │ orreq r0, r7, r4, ror #11 │ │ orreq ip, r7, ip, lsr #9 │ │ - vcmla.f16 , , q13, #270 │ │ + stc2l 8, cr3, [r1, #604]! @ 0x25c │ │ ldrdeq ip, [r8, ip] │ │ orrseq r0, r2, ip, lsl #5 │ │ orrseq r0, r2, r0, asr r6 │ │ orreq ip, r7, r0, lsl r4 │ │ @ instruction: 0x0187e394 │ │ orreq lr, r7, ip, lsl #7 │ │ orreq sp, r5, r0, asr #7 │ │ @@ -1249851,23 +1249851,23 @@ │ │ orreq fp, r8, r8, ror #15 │ │ @ instruction: 0x0187c294 │ │ stc2l 0, cr1, [r3, #616]! @ 0x268 │ │ orreq r7, r8, r0, lsr #4 │ │ ldrsbteq lr, [r3], -r8 │ │ orreq sl, r8, ip, lsl #16 │ │ strdeq r7, [r8, r0] │ │ - stc2l 6, cr9, [r1, #760]! @ 0x2f8 │ │ - stc2l 5, cr3, [r1, #728]! @ 0x2d8 │ │ + stc2l 6, cr9, [r1, #940]! @ 0x3ac │ │ + stc2l 5, cr3, [r1, #908]! @ 0x38c │ │ orreq sl, r8, r0, asr #15 │ │ orreq lr, r7, r8, ror #2 │ │ stc2l 10, cr0, [r4, #152]! @ 0x98 @ │ │ - stc2l 5, cr9, [r1, #528]! @ 0x210 │ │ - stc2l 12, cr10, [r2, #36]! @ 0x24 │ │ + stc2l 5, cr9, [r1, #708]! @ 0x2c4 │ │ + stc2l 12, cr10, [r2, #216]! @ 0xd8 │ │ stc2l 9, cr0, [r4, #468]! @ 0x1d4 @ │ │ - stc2l 5, cr9, [r1, #288]! @ 0x120 │ │ + stc2l 5, cr9, [r1, #468]! @ 0x1d4 │ │ ldr r4, [pc, #3972] @ 240de78 │ │ mov r2, sl │ │ movw r3, #5111 @ 0x13f7 │ │ add r4, pc, r4 │ │ mov r0, r4 │ │ bl 270da30 │ │ ldr r2, [pc, #3952] @ 240de7c │ │ @@ -1249946,21 +1249946,21 @@ │ │ str r0, [r2, r1, lsl #2] │ │ b 240ec44 │ │ orreq lr, r7, r4, rrx │ │ strheq sp, [r5, r0] │ │ orreq r0, r8, r4, asr #5 │ │ strdeq fp, [r8, ip] │ │ stc2l 4, cr14, [r3, #484]! @ 0x1e4 │ │ - stc2l 4, cr3, [r1, #312]! @ 0x138 │ │ - stc2l 0, cr1, [r1, #88]! @ 0x58 │ │ + stc2l 4, cr3, [r1, #492]! @ 0x1ec │ │ + stc2l 0, cr1, [r1, #268]! @ 0x10c │ │ orreq fp, r8, r0, lsl #27 │ │ orreq sl, r7, r8, lsr #26 │ │ strdeq pc, [r8, r8] │ │ stc2l 13, cr0, [r3, #768]! @ 0x300 │ │ - stc2l 13, cr6, [r1, #452]! @ 0x1c4 │ │ + stc2l 13, cr6, [r1, #632]! @ 0x278 │ │ ldr r1, [r3, r1, lsl #2] │ │ add r0, r1, r0 │ │ sub r1, fp, #52 @ 0x34 │ │ add r0, r0, #1 │ │ str r0, [fp, #-52] @ 0xffffffcc │ │ ldr r2, [pc, #4012] @ 240e028 │ │ sub r0, fp, #44 @ 0x2c │ │ @@ -1250031,25 +1250031,25 @@ │ │ ldr r0, [pc, r0] │ │ str r0, [fp, #-40] @ 0xffffffd8 │ │ cmp r0, #1 │ │ blt 240d5a0 │ │ mov r1, #0 │ │ mov r0, #1 │ │ b 240d210 │ │ - stc2l 3, cr15, [r0, #968]! @ 0x3c8 │ │ + stc2l 4, cr15, [r0, #124]! @ 0x7c │ │ stc2l 8, cr0, [r4, #216]! @ 0xd8 │ │ - stc2l 3, cr9, [r1, #592]! @ 0x250 │ │ + stc2l 3, cr9, [r1, #772]! @ 0x304 │ │ vcmla.f16 d16, d4, d14, #270 │ │ - stc2l 3, cr9, [r1, #432]! @ 0x1b0 │ │ + stc2l 3, cr9, [r1, #612]! @ 0x264 │ │ stc2l 7, cr0, [r4, #920]! @ 0x398 │ │ - stc2l 3, cr9, [r1, #272]! @ 0x110 │ │ - stc2l 10, cr8, [r2, #788]! @ 0x314 @ │ │ - stc2l 12, cr6, [r1, #724]! @ 0x2d4 │ │ + stc2l 3, cr9, [r1, #452]! @ 0x1c4 │ │ + stc2l 10, cr8, [r2, #968]! @ 0x3c8 @ │ │ + stc2l 12, cr6, [r1, #904]! @ 0x388 │ │ orreq fp, r7, r8, asr #30 │ │ - stc2l 9, cr10, [r2, #274]! @ 0x112 @ │ │ + stc2l 9, cr10, [r2, #364]! @ 0x16c @ │ │ ldr r2, [pc, #3976] @ 240e154 │ │ mov r0, #0 │ │ str r1, [fp, #-44] @ 0xffffffd4 │ │ add r2, pc, r2 │ │ str r0, [r2, r1, lsl #2] │ │ ldr r0, [pc, #3960] @ 240e158 │ │ add r0, pc, r0 │ │ @@ -1250088,22 +1250088,22 @@ │ │ cmp r0, #124 @ 0x7c │ │ bhi 240d2ac │ │ ldr r0, [pc, #4076] @ 240e25c │ │ str r1, [fp, #-48] @ 0xffffffd0 │ │ add r0, pc, r0 │ │ str r4, [r0, r1, lsl #2] │ │ b 240d2e8 │ │ - stc2l 10, cr8, [r2, #452]! @ 0x1c4 @ │ │ - stc2l 12, cr6, [r1, #388]! @ 0x184 │ │ + stc2l 10, cr8, [r2, #632]! @ 0x278 @ │ │ + stc2l 12, cr6, [r1, #568]! @ 0x238 │ │ strdeq fp, [r7, r4] │ │ - stc2l 10, cr8, [r2, #164]! @ 0xa4 @ │ │ - stc2l 12, cr6, [r1, #100]! @ 0x64 │ │ + stc2l 10, cr8, [r2, #344]! @ 0x158 @ │ │ + stc2l 12, cr6, [r1, #280]! @ 0x118 │ │ orreq fp, r7, ip, lsr #29 │ │ - stc2l 9, cr8, [r2, #442]! @ 0x1ba @ │ │ - stc2l 11, cr6, [r1, #820]! @ 0x334 @ │ │ + stc2l 10, cr8, [r2, #40]! @ 0x28 @ │ │ + stc2l 11, cr6, [r1, #1000]! @ 0x3e8 @ │ │ orreq fp, r7, r0, ror #28 │ │ @ instruction: 0x01886dbc │ │ orreq lr, r7, ip, lsl sp │ │ orreq sl, r7, r8, ror #21 │ │ ldr r0, [pc, #4012] @ 240e260 │ │ mov r2, sl │ │ movw r3, #5143 @ 0x1417 │ │ @@ -1250162,15 +1250162,15 @@ │ │ cmp r0, #124 @ 0x7c │ │ bhi 240d4ec │ │ ldr r0, [pc, #4004] @ 240e33c │ │ str r1, [fp, #-48] @ 0xffffffd0 │ │ add r0, pc, r0 │ │ ldr r4, [r0, r1, lsl #2] │ │ b 240d53c │ │ - stc2l 1, cr3, [r1, #360]! @ 0x168 │ │ + stc2l 1, cr3, [r1, #540]! @ 0x21c │ │ eorseq lr, r3, r8, asr #4 │ │ orreq r3, r8, r4, lsl #29 │ │ orreq sp, r7, r4, lsr sp │ │ orreq sp, r7, r4, lsr sp │ │ lsr r0, r1, #3 │ │ cmp r0, #124 @ 0x7c │ │ bls 240d1c4 │ │ @@ -1250195,17 +1250195,17 @@ │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #3888] @ 240e34c │ │ add r0, pc, r0 │ │ b 240d1e0 │ │ orreq sl, r7, ip, asr #20 │ │ orreq sl, r7, ip, lsr sl │ │ - stc2l 0, cr3, [r1, #808]! @ 0x328 │ │ + stc2l 0, cr3, [r1, #988]! @ 0x3dc │ │ orreq r6, r8, r0, ror #25 │ │ - stc2l 1, cr9, [r1, #616]! @ 0x268 │ │ + stc2l 1, cr9, [r1, #796]! @ 0x31c │ │ @ instruction: 0x0188a2b0 │ │ @ instruction: 0x018622b0 │ │ orreq lr, r7, r0, lsl #24 │ │ strdeq lr, [r7, r0] │ │ orreq sp, r7, r8, lsr ip │ │ orreq sp, r7, r0, lsr #24 │ │ ldr r0, [pc, #3836] @ 240e350 │ │ @@ -1250322,15 +1250322,15 @@ │ │ orreq r4, r8, r0, asr #22 │ │ orreq lr, r7, r4, lsl #20 │ │ orrseq pc, r1, r8, lsr #24 │ │ strdeq sp, [r7, r8] │ │ orreq sp, r7, r8, ror #19 │ │ ldrdeq sp, [r7, ip] │ │ ldrdeq sp, [r7, r8] │ │ - stc2l 13, cr2, [r1, #888]! @ 0x378 │ │ + stc2l 14, cr2, [r1, #44]! @ 0x2c │ │ ldrsbteq sp, [r3], -r0 │ │ orreq r3, r8, r0, lsl fp │ │ ldr r0, [pc, #4024] @ 240e5f0 │ │ ldr r2, [pc, #4024] @ 240e5f4 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ add r0, r0, r4, lsl #2 │ │ @@ -1250442,15 +1250442,15 @@ │ │ ldr r0, [pc, #4072] @ 240e7d8 │ │ mov r2, sl │ │ movw r3, #5203 @ 0x1453 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 240d630 │ │ - stc2l 10, cr0, [r1, #164]! @ 0xa4 @ │ │ + stc2l 10, cr0, [r1, #344]! @ 0x158 @ │ │ ldr r0, [pc, #4044] @ 240e7dc │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ str r1, [fp, #-40] @ 0xffffffd8 │ │ cmp r1, #199 @ 0xc7 │ │ bhi 240d84c │ │ add r0, r0, r0, lsl #1 │ │ @@ -1250479,27 +1250479,27 @@ │ │ str r4, [fp, #-48] @ 0xffffffd0 │ │ ldr r2, [pc, #4072] @ 240e870 │ │ add r2, pc, r2 │ │ add r0, r2, r0, lsl #2 │ │ bhi 240d8cc │ │ str r1, [fp, #-44] @ 0xffffffd4 │ │ b 240d928 │ │ - stc2l 7, cr6, [r1, #228]! @ 0xe4 │ │ + stc2l 7, cr6, [r1, #408]! @ 0x198 │ │ orreq sp, r7, r0, asr #16 │ │ orreq sl, r7, r8, ror #11 │ │ stc2l 1, cr12, [r3, #944]! @ 0x3b0 │ │ orreq r8, r8, r8, lsr fp │ │ ldrdeq sp, [r7, r0] │ │ stc2l 7, cr8, [r0, #216]! @ 0xd8 │ │ @ instruction: 0x01887ab8 │ │ orreq sp, r7, r0, asr r7 │ │ stc2l 6, cr2, [r3, #1016]! @ 0x3f8 │ │ orreq sp, r7, r0, lsl r7 │ │ strdeq sp, [r7, r4] │ │ - vcmla.f16 d16, d1, d29, #270 │ │ + stc2l 8, cr0, [r1, #360]! @ 0x168 │ │ mov r8, r0 │ │ ldr r0, [pc, #4084] @ 240e8cc │ │ mov r1, r4 │ │ mov r2, sl │ │ add r0, pc, r0 │ │ movw r3, #5210 @ 0x145a │ │ bl 270da30 │ │ @@ -1250587,17 +1250587,17 @@ │ │ ldr r0, [pc, r0] │ │ ldr r4, [pc, #4040] @ 240ea00 │ │ ldr r9, [pc, #4040] @ 240ea04 │ │ add r4, pc, r4 │ │ add r9, pc, r9 │ │ b 240dad4 │ │ orreq sp, r7, r4, lsr #13 │ │ - stc2l 9, cr14, [r1, #60]! @ 0x3c @ │ │ + stc2l 9, cr14, [r1, #150]! @ 0x96 @ │ │ orreq sp, r7, r4, asr #12 │ │ - stc2l 8, cr12, [r1, #592]! @ 0x250 │ │ + vcmla.f16 q14, , , #270 │ │ @ instruction: 0x0187e5b0 │ │ orreq pc, r6, ip, asr r7 @ │ │ orreq sl, r8, r0, asr #23 │ │ stc2l 3, cr4, [r3, #320]! @ 0x140 │ │ mov r0, #1 │ │ str r0, [r9] │ │ mov r0, #0 │ │ @@ -1250749,15 +1250749,15 @@ │ │ orreq pc, r6, r4, lsr #11 │ │ ldrdeq lr, [r7, r8] │ │ orreq pc, r6, r4, ror #10 │ │ orreq lr, r7, r4, lsl #7 │ │ stc2l 2, cr12, [r2, #196]! @ 0xc4 │ │ strdeq fp, [r7, r8] │ │ ldrdeq fp, [r7, r8] │ │ - stc2l 7, cr2, [r1, #552]! @ 0x228 │ │ + stc2l 7, cr2, [r1, #732]! @ 0x2dc │ │ orreq lr, r6, r8, lsl r5 │ │ orreq fp, r8, r0, lsr r5 │ │ orreq sp, r7, r8, lsr r3 │ │ @ instruction: 0x0191f9bc │ │ ldrdeq lr, [r6, r8] │ │ orreq pc, r8, r0, ror #6 │ │ orreq lr, r6, r4, lsr #9 │ │ @@ -1250862,15 +1250862,15 @@ │ │ stc2l 15, cr3, [r3, #544]! @ 0x220 │ │ orreq pc, r6, r8, ror #6 │ │ @ instruction: 0x0187e19c │ │ orreq r3, r8, ip, lsl r3 │ │ orreq pc, r6, r0, lsr #6 │ │ orreq lr, r6, r0, asr r3 │ │ orreq fp, r7, ip, asr #3 │ │ - stc2l 5, cr2, [r1, #520]! @ 0x208 │ │ + stc2l 5, cr2, [r1, #700]! @ 0x2bc │ │ orreq fp, r8, r0, lsr r3 │ │ orreq r9, r7, ip, asr #29 │ │ orreq sl, r7, r8, lsl #29 │ │ orreq fp, r7, r0, ror #1 │ │ orreq fp, r7, r0, ror r1 │ │ orreq lr, r7, r4, asr #1 │ │ orreq fp, r7, r0, asr r1 │ │ @@ -1251018,15 +1251018,15 @@ │ │ bl 270da30 │ │ mov r1, r0 │ │ b 240dcf4 │ │ orreq r4, r9, r0, lsl r8 │ │ stc2l 13, cr3, [r3, #464]! @ 0x1d0 │ │ orreq r9, r7, r8, ror #26 │ │ orreq pc, r6, r8, asr #2 │ │ - stc2l 0, cr4, [r2, #584]! @ 0x248 │ │ + stc2l 0, cr4, [r2, #764]! @ 0x2fc │ │ orreq fp, r7, r8 │ │ ldr r0, [pc, #4080] @ 240f104 │ │ ldr r0, [pc, r0] │ │ cmp r0, #1 │ │ blt 240e874 │ │ ldr r0, [pc, #4068] @ 240f108 │ │ ldr r0, [pc, r0] │ │ @@ -1251248,15 +1251248,15 @@ │ │ b 240e58c │ │ @ instruction: 0x0187bc94 │ │ orreq ip, r7, r4, asr #24 │ │ stc2l 1, cr13, [r3, #428]! @ 0x1ac │ │ stc2l 1, cr13, [r3, #284]! @ 0x11c │ │ strdeq ip, [r7, r4] │ │ strdeq ip, [r6, ip] │ │ - stc2l 10, cr5, [r1, #724]! @ 0x2d4 @ │ │ + stc2l 10, cr5, [r1, #904]! @ 0x388 @ │ │ orreq r9, r7, r0, ror r9 │ │ @ instruction: 0x018943b8 │ │ @ instruction: 0x0187cb9c │ │ stc2l 9, cr3, [r3, #18]! @ │ │ orreq sl, r7, r0, lsl ip │ │ eorseq sp, r3, r4, rrx │ │ orreq r2, r6, r4, lsl #3 │ │ @@ -1251458,15 +1251458,15 @@ │ │ bl 270da30 │ │ mov lr, r6 │ │ mov r6, r0 │ │ b 240e4c4 │ │ stc2l 2, cr15, [r3, #148]! @ 0x94 │ │ orreq sl, r7, r8, lsr #17 │ │ orreq r5, r8, r0, lsl #18 │ │ - stc2l 3, cr7, [r2, #956]! @ 0x3bc │ │ + stc2l 4, cr7, [r2, #112]! @ 0x70 │ │ orreq sl, r7, ip, asr #16 │ │ ldr r1, [pc, #3972] @ 240f778 │ │ ldr r1, [pc, r1] │ │ ldr r9, [pc, #3968] @ 240f77c │ │ cmp r0, #0 │ │ sub r6, fp, #44 @ 0x2c │ │ cmpne r1, #0 │ │ @@ -1251516,17 +1251516,17 @@ │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ str r1, [fp, #-40] @ 0xffffffd8 │ │ cmp r1, #10 │ │ bcs 240eb18 │ │ mov r0, r1 │ │ b 240eb34 │ │ - stc2l 10, cr13, [r1, #864]! @ 0x360 @ │ │ + stc2l 11, cr13, [r1, #20]! @ │ │ orreq sl, r7, r4, asr #15 │ │ - stc2l 12, cr1, [r1, #68]! @ 0x44 │ │ + stc2l 12, cr1, [r1, #248]! @ 0xf8 │ │ eorseq ip, r3, r4, ror #25 │ │ orreq fp, r5, r4, lsr #16 │ │ orreq r5, r8, r4, lsr #22 │ │ strdeq fp, [r7, ip] │ │ @ instruction: 0x01861db4 │ │ orreq r1, r6, r8, lsr #27 │ │ @ instruction: 0x01861d94 │ │ @@ -1251597,15 +1251597,15 @@ │ │ ldrdeq ip, [r7, ip] │ │ orreq ip, r7, r4, asr #13 │ │ ldrdeq r1, [r6, r0] │ │ stc2l 4, cr3, [r3, #288]! @ 0x120 │ │ orreq r2, r8, r0, lsl r8 │ │ orreq ip, r7, r0, ror r6 │ │ orreq sl, r7, r4, lsr r6 │ │ - stc2l 10, cr1, [r1, #516]! @ 0x204 @ │ │ + stc2l 10, cr1, [r1, #696]! @ 0x2b8 @ │ │ @ instruction: 0x01882798 │ │ orreq r3, r9, r0, lsl r8 │ │ orreq r1, r6, r8, lsr ip │ │ stc2l 3, cr3, [r3, #704]! @ 0x2c0 │ │ orreq r9, r7, ip, lsr #7 │ │ ldrdeq sp, [r6, ip] │ │ orreq lr, r6, r4, ror r7 │ │ @@ -1251818,15 +1251818,15 @@ │ │ mov r0, r4 │ │ mov r2, sl │ │ movw r3, #5464 @ 0x1558 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 240cb8c │ │ orreq ip, r7, r8, ror r3 │ │ - stc2l 4, cr3, [r2, #120]! @ 0x78 │ │ + stc2l 4, cr3, [r2, #300]! @ 0x12c │ │ orreq fp, r7, ip, lsl #7 │ │ orreq lr, r6, r4, lsr #9 │ │ @ instruction: 0x0186e498 │ │ ldrdeq sl, [r7, r8] │ │ stc2l 2, cr2, [r4, #712]! @ 0x2c8 │ │ ldrdeq r3, [r9, ip] │ │ ldrdeq ip, [r7, ip] │ │ @@ -1252053,15 +1252053,15 @@ │ │ orreq lr, r6, r4, lsl #2 │ │ orreq ip, r7, r0, lsr #30 │ │ orreq ip, r7, r0, lsl pc │ │ stc2l 12, cr2, [r3, #848]! @ 0x350 │ │ strdeq r9, [r7, ip] │ │ orreq fp, r7, ip, lsl pc │ │ orreq r8, r7, r0, lsr #25 │ │ - stc2l 10, cr6, [r2, #316]! @ 0x13c @ │ │ + stc2l 10, cr6, [r2, #496]! @ 0x1f0 @ │ │ orreq r4, r8, r4, lsr #30 │ │ orreq r1, r6, r8, ror #9 │ │ stlexeq ip, r0, [r7] │ │ orreq r8, r7, r0, asr #24 │ │ ldr r0, [pc, #3868] @ 2410068 │ │ mov r2, sl │ │ movw r3, #5493 @ 0x1575 │ │ @@ -1252121,15 +1252121,15 @@ │ │ mov r3, #5504 @ 0x1580 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ ldr r3, [pc, #3680] @ 2410098 │ │ mov r1, r0 │ │ add r3, pc, r3 │ │ b 240f014 │ │ - stc2l 9, cr6, [r2, #366]! @ 0x16e @ │ │ + stc2l 9, cr6, [r2, #456]! @ 0x1c8 @ │ │ ldr r0, [pc, #4092] @ 2410248 │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #4088] @ 241024c │ │ cmp r0, #2 │ │ add r1, pc, r1 │ │ moveq r1, r3 │ │ ldr r1, [r1] │ │ @@ -1252154,15 +1252154,15 @@ │ │ ldr r4, [pc, r4] │ │ ldr r0, [pc, #4012] @ 2410260 │ │ add r0, pc, r0 │ │ str r4, [r0] │ │ mov r0, #2 │ │ str r0, [r1] │ │ b 240f2dc │ │ - stc2l 0, cr13, [r1, #928]! @ 0x3a0 │ │ + stc2l 1, cr13, [r1, #84]! @ 0x54 │ │ orreq r4, r8, r4, asr lr │ │ orreq lr, r8, r0, ror #9 │ │ @ instruction: 0x0187cdb8 │ │ ldr r4, [pc, #3976] @ 2410264 │ │ ldr r4, [pc, r4] │ │ ldr r1, [pc, #3972] @ 2410268 │ │ ldr r1, [pc, r1] │ │ @@ -1252170,17 +1252170,17 @@ │ │ cmp r1, #200 @ 0xc8 │ │ add r0, r1, #1 │ │ str r0, [r2] │ │ bcs 240f310 │ │ mov r0, r4 │ │ b 240f330 │ │ @ instruction: 0x01879db0 │ │ - stc2l 8, cr6, [r2, #876]! @ 0x36c │ │ + stc2l 9, cr6, [r2, #16]! @ │ │ orreq r9, r7, r4, lsr sp │ │ - stc2l 0, cr13, [r1, #48]! @ 0x30 │ │ + stc2l 0, cr13, [r1, #228]! @ 0xe4 │ │ ldr r0, [pc, #3924] @ 241026c │ │ mov r2, sl │ │ movw r3, #5543 @ 0x15a7 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #3904] @ 2410270 │ │ @@ -1252262,20 +1252262,20 @@ │ │ orreq r1, r6, r8, lsr #4 │ │ ldrshteq ip, [r3], -ip │ │ orreq sp, r6, r8, ror sp │ │ orreq r8, r7, r0, asr r9 │ │ orreq fp, r7, r4, lsr #23 │ │ @ instruction: 0x0187bb94 │ │ @ instruction: 0x0187bb94 │ │ - stc2l 15, cr0, [r1, #632]! @ 0x278 │ │ + stc2l 15, cr0, [r1, #812]! @ 0x32c │ │ stc2l 8, cr2, [r3, #836]! @ 0x344 │ │ strdeq r9, [r7, r0] │ │ - stc2l 6, cr6, [r2, #108]! @ 0x6c │ │ + stc2l 6, cr6, [r2, #288]! @ 0x120 │ │ orreq r9, r7, r4, ror sl │ │ - stc2l 13, cr12, [r1, #288]! @ 0x120 │ │ + stc2l 13, cr12, [r1, #468]! @ 0x1d4 │ │ ldr r2, [pc, #4052] @ 2410468 │ │ add r2, pc, r2 │ │ str r8, [r2, r1, lsl #2] │ │ ldr r6, [pc, #4044] @ 241046c │ │ ldr r6, [pc, r6] │ │ ldr r2, [pc, #4040] @ 2410470 │ │ str r1, [fp, #-36] @ 0xffffffdc │ │ @@ -1252393,20 +1252393,20 @@ │ │ cmp r0, #0 │ │ beq 240f5e8 │ │ cmp r0, #0 │ │ bne 240f6ac │ │ b 241047c │ │ orreq fp, r7, r0, lsl #21 │ │ stc2l 3, cr14, [r3, #436]! @ 0x1b4 │ │ - stc2l 14, cr0, [r1, #376]! @ 0x178 │ │ + stc2l 14, cr0, [r1, #556]! @ 0x22c │ │ orreq fp, r7, r8, lsr sl │ │ - stc2l 11, cr14, [r0, #516]! @ 0x204 @ │ │ + stc2l 11, cr14, [r0, #696]! @ 0x2b8 @ │ │ @ instruction: 0x018799b8 │ │ - stc2l 5, cr6, [r2, #44]! @ 0x2c │ │ - stc2l 13, cr0, [r1, #840]! @ 0x348 │ │ + stc2l 5, cr6, [r2, #224]! @ 0xe0 │ │ + stc2l 13, cr0, [r1, #1020]! @ 0x3fc │ │ orreq r9, r7, ip, asr r9 │ │ mov r0, #1 │ │ strb r0, [r6] │ │ ldr r8, [pc, #4092] @ 24106a8 │ │ ldr r8, [pc, r8] │ │ ldr r0, [pc, #4088] @ 24106ac │ │ ldr r0, [pc, r0] │ │ @@ -1252451,18 +1252451,18 @@ │ │ movw r3, #5615 @ 0x15ef │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #4052] @ 2410738 │ │ ldr r0, [pc, r0] │ │ b 240f4b8 │ │ - stc2l 12, cr12, [r1, #208]! @ 0xd0 │ │ + stc2l 12, cr12, [r1, #388]! @ 0x184 │ │ orreq fp, r7, ip, ror #18 │ │ stc2l 2, cr14, [r3, #400]! @ 0x190 │ │ - stc2l 13, cr0, [r1, #312]! @ 0x138 │ │ + stc2l 13, cr0, [r1, #492]! @ 0x1ec │ │ strdeq r8, [r8, r4] │ │ orreq r1, r8, r8, asr #20 │ │ ldr r1, [pc, #4020] @ 241073c │ │ ldr r1, [pc, r1] │ │ ldr r0, [pc, #4016] @ 2410740 │ │ cmp r1, #0 │ │ add r0, pc, r0 │ │ @@ -1252573,15 +1252573,15 @@ │ │ movw r3, #5630 @ 0x15fe │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 240f840 │ │ orreq r9, r7, r4, ror #14 │ │ orreq fp, r7, r4, lsl #15 │ │ - stc2l 2, cr6, [r2, #780]! @ 0x30c │ │ + stc2l 2, cr6, [r2, #960]! @ 0x3c0 │ │ orreq r4, r8, r0, lsr #15 │ │ orreq r0, r6, ip, asr sp │ │ orreq ip, r7, r4, lsl #14 │ │ ldrdeq r8, [r7, r0] │ │ ldr r0, [pc, #4092] @ 2410968 │ │ mov r1, #36 @ 0x24 │ │ add r0, pc, r0 │ │ @@ -1252607,15 +1252607,15 @@ │ │ mov r2, #1 │ │ bl 270da60 │ │ ldr r0, [pc, #4020] @ 2410980 │ │ mov r1, #23 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ b 2410720 │ │ - stc2l 2, cr6, [r2, #28]! │ │ + stc2l 2, cr6, [r2, #208]! @ 0xd0 │ │ orreq r9, r7, r0, ror #12 │ │ mov r0, #1 │ │ strb r0, [r8] │ │ mov r0, #0 │ │ str r0, [sl] │ │ ldr r0, [pc, #3980] @ 2410984 │ │ ldr r0, [pc, r0] │ │ @@ -1252645,15 +1252645,15 @@ │ │ str r0, [sl] │ │ mov r0, r4 │ │ bl 270e120 │ │ cmp r0, #0 │ │ str r0, [r4] │ │ bgt 240fa48 │ │ b 240b8f0 │ │ - stc2l 9, cr12, [r1, #112]! @ 0x70 @ │ │ + stc2l 9, cr12, [r1, #202]! @ 0xca @ │ │ orreq r4, r8, r8, lsr #13 │ │ orreq sp, r8, r4, lsr sp │ │ orreq ip, r7, r8, lsl #12 │ │ ldrdeq r8, [r7, r4] │ │ orreq ip, r7, ip, ror #11 │ │ orreq r9, r7, r4, ror #12 │ │ orreq ip, r7, r8, lsl #11 │ │ @@ -1252727,18 +1252727,18 @@ │ │ ble 24104d8 │ │ ldr r2, [pc, #4036] @ 2410b6c │ │ mov r7, #1 │ │ mov r1, #1 │ │ add r2, pc, r2 │ │ str r1, [r2] │ │ b 240fbe8 │ │ - stc2l 9, cr0, [r1, #72]! @ 0x48 @ │ │ + stc2l 9, cr0, [r1, #162]! @ 0xa2 @ │ │ orreq ip, r7, r4, lsr #9 │ │ orreq r7, r8, ip, asr #15 │ │ - stc2l 8, cr0, [r1, #856]! @ 0x358 │ │ + stc2l 9, cr0, [r1, #6]! @ │ │ orreq sp, r6, r0, lsr r6 │ │ stc2l 2, cr2, [r3, #208]! @ 0xd0 │ │ orreq r7, r8, r4, lsl #15 │ │ orreq ip, r7, ip, lsr #8 │ │ ldr r1, [pc, #3984] @ 2410b70 │ │ add r7, r7, #1 │ │ add r1, pc, r1 │ │ @@ -1252841,15 +1252841,15 @@ │ │ sub r9, r1, #20 │ │ cmp r9, #2000 @ 0x7d0 │ │ bcs 240fd8c │ │ lsl r1, r0, #2 │ │ mov r0, r9 │ │ b 240fdbc │ │ stc2l 0, cr2, [r3, #816]! @ 0x330 │ │ - stc2l 7, cr0, [r1, #360]! @ 0x168 │ │ + stc2l 7, cr0, [r1, #540]! @ 0x21c │ │ orreq sp, r6, r4, lsr #9 │ │ ldrdeq ip, [r7, r8] │ │ ldr r0, [pc, #4072] @ 2410d7c │ │ mov r1, r9 │ │ mov r2, r8 │ │ movw r3, #2977 @ 0xba1 │ │ add r0, pc, r0 │ │ @@ -1252877,15 +1252877,15 @@ │ │ cmp r1, #99 @ 0x63 │ │ bhi 240fe14 │ │ ldr r0, [r6, r1, lsl #2] │ │ sub r7, r0, #1 │ │ str r7, [r6, r1, lsl #2] │ │ b 240fff0 │ │ orreq ip, r7, r0, lsr #5 │ │ - stc2l 6, cr0, [r1, #960]! @ 0x3c0 │ │ + stc2l 7, cr0, [r1, #116]! @ 0x74 │ │ mov r0, r9 │ │ mov r2, r8 │ │ movw r3, #2981 @ 0xba5 │ │ bl 270da30 │ │ ldr r0, [r6, r0, lsl #2] │ │ sub r7, r0, #1 │ │ ldr r0, [pc, #4084] @ 2410e28 │ │ @@ -1253031,15 +1253031,15 @@ │ │ orreq fp, r7, ip, lsr #32 │ │ orreq fp, r6, r8, lsr #4 │ │ @ instruction: 0x0187bfb4 │ │ stc2l 4, cr11, [r3, #956]! @ 0x3bc │ │ @ instruction: 0x0186b1b4 │ │ orreq fp, r7, r4, asr #30 │ │ orreq sl, r7, r4, lsl #31 │ │ - stc2l 14, cr3, [r1, #324]! @ 0x144 │ │ + stc2l 14, cr3, [r1, #504]! @ 0x1f8 │ │ orreq fp, r7, r8, lsl #30 │ │ orreq sp, r6, r4, asr #1 │ │ strdeq r7, [r7, r8] │ │ orreq fp, r7, ip, ror #29 │ │ orreq fp, r7, r0, ror #29 │ │ strdeq sl, [r7, r0] │ │ stc2l 12, cr1, [r3, #372]! @ 0x174 │ │ @@ -1253253,15 +1253253,15 @@ │ │ add r0, pc, r0 │ │ b 240bc14 │ │ @ instruction: 0x01878db8 │ │ orreq sl, r7, r8, lsl #26 │ │ orreq r8, r7, r8, asr sl │ │ orrseq ip, r1, r0, lsl #18 │ │ ldrdeq r0, [r6, r0] │ │ - stc2l 0, cr0, [r1, #936]! @ 0x3a8 │ │ + stc2l 1, cr0, [r1, #92]! @ 0x5c │ │ orrseq r1, r1, ip, asr #8 │ │ ldrdeq sl, [r7, r0] │ │ ldr r4, [pc, #3904] @ 2411344 │ │ mov r1, #6 │ │ add r4, pc, r4 │ │ mov r0, r4 │ │ bl 270ce90 │ │ @@ -1253354,15 +1253354,15 @@ │ │ ldr r0, [pc, #4092] @ 241156c │ │ mov r1, r7 │ │ add r0, pc, r0 │ │ b 2410680 │ │ orreq sl, r7, r4, ror #22 │ │ ldrdeq r8, [r7, r8] │ │ @ instruction: 0x01878bb8 │ │ - stc2l 14, cr15, [r1, #152]! @ 0x98 │ │ + stc2l 14, cr15, [r1, #332]! @ 0x14c │ │ orreq sl, r8, r8, lsr r9 │ │ orreq sl, r7, r4, lsr #22 │ │ ldr r0, [pc, #4056] @ 2411570 │ │ mov r1, #55 @ 0x37 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #4044] @ 2411574 │ │ @@ -1253462,15 +1253462,15 @@ │ │ add r1, pc, r1 │ │ str r2, [r1] │ │ ldr r0, [pc, #4052] @ 24116fc │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ b 2413254 │ │ orreq r8, r7, ip, lsl #20 │ │ - stc2l 4, cr7, [r2, #680]! @ 0x2a8 │ │ + stc2l 4, cr7, [r2, #860]! @ 0x35c │ │ @ instruction: 0x0187a998 │ │ orreq fp, r6, r4, lsr fp │ │ orreq sl, r7, r4, ror #18 │ │ orreq sl, r7, r4, lsr r9 │ │ orreq sl, r7, r0, lsr #18 │ │ ldr r0, [pc, #4012] @ 2411700 │ │ ldr r0, [pc, r0] │ │ @@ -1253507,25 +1253507,25 @@ │ │ ldr sl, [pc, #3924] @ 2411728 │ │ add r8, pc, r8 │ │ add r5, pc, r5 │ │ add sl, pc, sl │ │ b 241086c │ │ orrseq ip, r1, r8, asr fp │ │ orrseq ip, r1, r4, lsr #10 │ │ - stc2l 13, cr15, [r0, #104]! @ 0x68 │ │ + stc2l 13, cr15, [r0, #284]! @ 0x11c │ │ ldrdeq r5, [r8, r8] │ │ orreq r6, r8, r4, asr #29 │ │ @ instruction: 0x01885b98 │ │ orreq sl, r7, r8, ror #16 │ │ orreq sl, r7, r4, asr r8 │ │ stc2l 8, cr15, [r2, #112]! @ 0x70 │ │ orreq sl, r7, r4, lsl r8 │ │ - vcmla.f16 , q9, q12, #270 │ │ + stc2l 9, cr1, [r2, #42]! @ 0x2a @ │ │ orreq sl, r7, r0, ror #15 │ │ - stc2l 10, cr11, [r1, #576]! @ 0x240 @ │ │ + stc2l 10, cr11, [r1, #756]! @ 0x2f4 @ │ │ ldr r0, [pc, #3856] @ 241172c │ │ mov r2, #80 @ 0x50 │ │ mov r3, #17 │ │ mov r7, r6 │ │ add r0, pc, r0 │ │ str r4, [r0, r1, lsl #2] │ │ mov r0, r9 │ │ @@ -1253606,18 +1253606,18 @@ │ │ bl 270d9d0 │ │ cmp r0, #0 │ │ bne 2410850 │ │ b 24141c0 │ │ stc2l 15, cr4, [r3, #432]! @ 0x1b0 │ │ orreq sl, r7, r0, lsl #15 │ │ stc2l 4, cr1, [r3, #916]! @ 0x394 │ │ - stc2l 11, cr15, [r0, #488]! @ 0x1e8 @ │ │ + stc2l 11, cr15, [r0, #668]! @ 0x29c @ │ │ orrseq ip, r1, r8, lsl #12 │ │ - stc2l 5, cr3, [r1, #292]! @ 0x124 │ │ - stc2l 7, cr1, [r2, #872]! @ 0x368 │ │ + stc2l 5, cr3, [r1, #472]! @ 0x1d8 │ │ + vcmla.f16 d17, d2, d7, #270 │ │ orreq r8, r7, ip, asr r7 │ │ ldr r4, [pc, #4000] @ 2411930 │ │ mov r6, r7 │ │ ldr sl, [pc, #3996] @ 2411934 │ │ add r4, pc, r4 │ │ add sl, pc, sl │ │ mov r0, r4 │ │ @@ -1253642,16 +1253642,16 @@ │ │ movw r3, #1707 @ 0x6ab │ │ ldr r2, [pc, #4052] @ 24119c8 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2410814 │ │ - stc2l 9, cr15, [r1, #396]! @ 0x18c @ │ │ - stc2l 10, cr15, [r0, #1016]! @ 0x3f8 @ │ │ + stc2l 9, cr15, [r1, #486]! @ 0x1e6 @ │ │ + stc2l 11, cr15, [r0, #172]! @ 0xac @ │ │ ldrdeq sl, [r8, r0] │ │ orreq pc, r5, r4, asr #25 │ │ orrseq r0, r1, r4, lsr lr │ │ orreq sl, r7, r0, asr #12 │ │ orreq sl, r7, r8, asr #12 │ │ @ instruction: 0x01859690 │ │ orreq sl, r7, ip, lsr #12 │ │ @@ -1253659,15 +1253659,15 @@ │ │ orreq r9, r5, r8, ror #12 │ │ orreq sl, r7, r4, lsl #12 │ │ orreq r8, r8, r0, asr #7 │ │ orreq r8, r7, r4, asr #12 │ │ orreq r9, r5, ip, lsr r6 │ │ @ instruction: 0x0188c494 │ │ orreq sl, r7, r4, asr #11 │ │ - stc2l 9, cr15, [r0, #420]! @ 0x1a4 @ │ │ + stc2l 9, cr15, [r0, #510]! @ 0x1fe @ │ │ stc2l 5, cr11, [r2, #168]! @ 0xa8 │ │ ldr sl, [pc, #4020] @ 2411a0c │ │ mov r5, #32 │ │ ldr r6, [pc, #4016] @ 2411a10 │ │ mov r8, r9 │ │ add sl, pc, sl │ │ add r6, pc, r6 │ │ @@ -1253736,15 +1253736,15 @@ │ │ orreq r8, r8, r0, ror r7 │ │ orreq r8, r7, ip, asr #11 │ │ orreq r8, r8, r0, lsl #8 │ │ orreq sl, r7, ip, asr #10 │ │ orreq sl, r7, r8, lsl r5 │ │ orreq r8, r7, ip, lsr #10 │ │ orreq sl, r7, r8, asr #9 │ │ - stc2l 7, cr13, [r1, #768]! @ 0x300 │ │ + stc2l 7, cr13, [r1, #948]! @ 0x3b4 │ │ strdeq r8, [r7, r0] │ │ @ instruction: 0x0187a490 │ │ orreq sl, r8, r8, lsl r4 │ │ ldr r0, [pc, #4080] @ 2411b84 │ │ mov r8, r7 │ │ mov r1, #0 │ │ ldr r0, [pc, r0] │ │ @@ -1253822,15 +1253822,15 @@ │ │ add r5, pc, r5 │ │ ldr r6, [pc, #3956] @ 2411c38 │ │ add sl, pc, sl │ │ add r7, pc, r7 │ │ add r6, pc, r6 │ │ b 2410850 │ │ orreq sl, r7, r4, lsr #8 │ │ - stc2l 7, cr13, [r1, #16]! │ │ + stc2l 7, cr13, [r1, #196]! @ 0xc4 │ │ orreq sl, r7, r4, ror #7 │ │ orreq r8, r7, ip, lsr #8 │ │ orreq sl, r8, r8, asr r3 │ │ mov r0, sl │ │ bl 270e0c0 │ │ cmp r0, #0 │ │ beq 24118f8 │ │ @@ -1253864,15 +1253864,15 @@ │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ cmp r1, #100 @ 0x64 │ │ bcs 241193c │ │ ldr r7, [pc, #4028] @ 2411d34 │ │ add r7, pc, r7 │ │ b 241195c │ │ - stc2l 6, cr13, [r1, #464]! @ 0x1d0 │ │ + stc2l 6, cr13, [r1, #644]! @ 0x284 │ │ orreq r8, r7, r8, lsr #7 │ │ orreq sl, r7, ip, asr #6 │ │ orreq sl, r8, r0, asr #5 │ │ stc2l 2, cr11, [r2, #520]! @ 0x208 │ │ mov r0, #1 │ │ strb r0, [sl] │ │ ldr r0, [pc, #3992] @ 2411d38 │ │ @@ -1253909,35 +1253909,35 @@ │ │ ldr r0, [pc, #3892] @ 2411d50 │ │ str r1, [fp, #-36] @ 0xffffffdc │ │ add r0, pc, r0 │ │ str r4, [r0, r2, lsl #2] │ │ b 2412660 │ │ orreq r8, r7, r0, lsr #6 │ │ @ instruction: 0x018782b0 │ │ - stc2l 5, cr15, [r1, #72]! @ 0x48 │ │ + stc2l 5, cr15, [r1, #252]! @ 0xfc │ │ orreq sl, r8, r4, lsr #32 │ │ orreq r8, r7, r8, ror #4 │ │ orrseq r0, r1, r0, lsl #19 │ │ strdeq sl, [r7, r8] │ │ orreq r9, r5, r8, lsr #4 │ │ orreq r8, r7, r4, lsr #4 │ │ orreq r8, r8, r4, asr r0 │ │ orreq r9, r5, r8, lsl #4 │ │ strdeq r8, [r7, ip] │ │ orreq r8, r8, r4, lsr #32 │ │ ldrdeq r8, [r7, r4] │ │ stc2l 0, cr11, [r2, #952]! @ 0x3b8 │ │ orreq r8, r7, r8, lsl #3 │ │ - stc2l 5, cr15, [r0, #216]! @ 0xd8 │ │ + stc2l 5, cr15, [r0, #396]! @ 0x18c │ │ strheq r8, [r7, ip] │ │ ldrdeq r8, [r8, ip] │ │ orreq r8, r7, ip, lsr r1 │ │ - stc2l 4, cr15, [r0, #904]! @ 0x388 │ │ + stc2l 5, cr15, [r0, #60]! @ 0x3c │ │ strheq ip, [r8, r4] │ │ - stc2l 11, cr4, [r2, #476]! @ 0x1dc @ │ │ + stc2l 11, cr4, [r2, #656]! @ 0x290 @ │ │ ldr r0, [pc, #4004] @ 2411e30 │ │ add r0, pc, r0 │ │ ldrb r0, [r0] │ │ cmp r0, #1 │ │ bne 2411cfc │ │ ldr r0, [pc, #3988] @ 2411e34 │ │ ldr r0, [pc, r0] │ │ @@ -1254122,20 +1254122,20 @@ │ │ mov r2, #80 @ 0x50 │ │ ldr r1, [pc, #3524] @ 2411f38 │ │ mov r3, #14 │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ bl 270d9e0 │ │ b 2411638 │ │ - stc2l 3, cr15, [r0, #568]! @ 0x238 │ │ + stc2l 3, cr15, [r0, #748]! @ 0x2ec │ │ orreq r8, r8, ip, lsr r1 │ │ orreq r7, r7, r0, lsl #30 │ │ orreq fp, r8, r0, lsr #31 │ │ orreq r7, r7, r8, lsl #31 │ │ - stc2l 3, cr15, [r0, #216]! @ 0xd8 │ │ + stc2l 3, cr15, [r0, #396]! @ 0x18c │ │ orreq r8, r8, r4, ror #1 │ │ @ instruction: 0x01877eb0 │ │ orreq fp, r8, r0, asr pc │ │ orreq r7, r7, ip, lsr #30 │ │ orreq r7, r7, r4, lsl pc │ │ stc2l 14, cr10, [r2, #184]! @ 0xb8 │ │ ldr r0, [pc, #3456] @ 2411f3c │ │ @@ -1254180,16 +1254180,16 @@ │ │ str r1, [fp, #-48] @ 0xffffffd0 │ │ bcs 2411284 │ │ ldr r6, [pc, #3328] @ 2411f60 │ │ add r6, pc, r6 │ │ b 24112a4 │ │ @ instruction: 0x01877eb0 │ │ orreq r9, r7, ip, asr #28 │ │ - stc2l 1, cr15, [r1, #40]! @ 0x28 │ │ - stc2l 2, cr15, [r0, #264]! @ 0x108 │ │ + stc2l 1, cr15, [r1, #220]! @ 0xdc │ │ + stc2l 2, cr15, [r0, #444]! @ 0x1bc │ │ orreq r9, r8, r0, lsl ip │ │ orreq pc, r5, r4, lsl #8 │ │ orrseq r0, r1, r4, ror r5 │ │ orreq r9, r7, r8, ror #27 │ │ ldr r0, [pc, #3288] @ 2411f64 │ │ movw r3, #1941 @ 0x795 │ │ ldr r6, [pc, #3284] @ 2411f68 │ │ @@ -1254228,35 +1254228,35 @@ │ │ cmp r0, #500 @ 0x1f4 │ │ sub r1, r1, #8 │ │ str r1, [fp, #-56] @ 0xffffffc8 │ │ bcs 2411380 │ │ ldr r6, [pc, #3164] @ 2411f84 │ │ add r6, pc, r6 │ │ b 24113a0 │ │ - stc2l 12, cr2, [r1, #288]! @ 0x120 │ │ - stc2l 11, cr2, [r1, #580]! @ 0x244 @ │ │ + stc2l 12, cr2, [r1, #468]! @ 0x1d4 │ │ + stc2l 11, cr2, [r1, #760]! @ 0x2f8 @ │ │ @ instruction: 0x0191bfd0 │ │ orreq r9, r7, r8, ror #26 │ │ orreq r9, r7, r4, asr #26 │ │ - stc2l 10, cr2, [r2, #564]! @ 0x234 @ │ │ - stc2l 7, cr6, [r2, #1012]! @ 0x3f4 │ │ + stc2l 10, cr2, [r2, #744]! @ 0x2e8 @ │ │ + vcmla.f16 d22, d2, d26, #270 │ │ stc2l 3, cr7, [r0, #664]! @ 0x298 │ │ - stc2l 10, cr2, [r1, #852]! @ 0x354 @ │ │ + stc2l 11, cr2, [r1, #8]! @ │ │ orreq fp, r6, ip, lsr #28 │ │ - stc2l 10, cr2, [r2, #52]! @ 0x34 @ │ │ - stc2l 13, cr0, [r2, #260]! @ 0x104 │ │ - stc2l 10, cr2, [r1, #404]! @ 0x194 @ │ │ + stc2l 10, cr2, [r2, #232]! @ 0xe8 @ │ │ + stc2l 13, cr0, [r2, #440]! @ 0x1b8 │ │ + stc2l 10, cr2, [r1, #584]! @ 0x248 @ │ │ orrseq fp, r1, r8, ror r8 │ │ @ instruction: 0x01877c90 │ │ stc2l 12, cr14, [r2, #92]! @ 0x5c │ │ - stc2l 14, cr10, [r1, #776]! @ 0x308 │ │ - stc2l 9, cr2, [r1, #458]! @ 0x1ca @ │ │ - stc2l 14, cr10, [r1, #600]! @ 0x258 │ │ - stc2l 9, cr2, [r1, #370]! @ 0x172 @ │ │ - stc2l 14, cr10, [r1, #440]! @ 0x1b8 │ │ + stc2l 14, cr10, [r1, #956]! @ 0x3bc │ │ + stc2l 10, cr2, [r1, #72]! @ 0x48 @ │ │ + stc2l 14, cr10, [r1, #780]! @ 0x30c │ │ + stc2l 9, cr2, [r1, #460]! @ 0x1cc @ │ │ + stc2l 14, cr10, [r1, #620]! @ 0x26c │ │ ldr r0, [pc, #3072] @ 2411f88 │ │ movw r3, #1941 @ 0x795 │ │ ldr r6, [pc, #3068] @ 2411f8c │ │ add r0, pc, r0 │ │ add r6, pc, r6 │ │ mov r2, r6 │ │ bl 270da30 │ │ @@ -1254372,27 +1254372,27 @@ │ │ add r0, r0, r1, lsl #2 │ │ ldr r1, [pc, #3996] @ 24124f8 │ │ ldr r2, [pc, #3996] @ 24124fc │ │ add r1, pc, r1 │ │ add r2, pc, r2 │ │ bl 270e0e0 │ │ b 2411780 │ │ - stc2l 9, cr2, [r1, #290]! @ 0x122 @ │ │ + stc2l 9, cr2, [r1, #380]! @ 0x17c @ │ │ stc2l 2, cr7, [r0, #152]! @ 0x98 │ │ - stc2l 9, cr2, [r1, #170]! @ 0xaa @ │ │ + stc2l 9, cr2, [r1, #260]! @ 0x104 @ │ │ orreq fp, r6, ip, lsr #25 │ │ - vcmla.f16 d18, d18, d13, #270 │ │ + stc2l 8, cr2, [r2, #744]! @ 0x2e8 │ │ stc2l 3, cr4, [r3, #116]! @ 0x74 │ │ stc2l 1, cr7, [r0, #776]! @ 0x308 │ │ - stc2l 8, cr2, [r1, #964]! @ 0x3c4 │ │ + stc2l 9, cr2, [r1, #60]! @ 0x3c @ │ │ orreq fp, r6, r8, asr #24 │ │ - vcmla.f16 d18, d2, d25, #270 │ │ - stc2l 14, cr0, [r1, #300]! @ 0x12c │ │ + stc2l 8, cr2, [r2, #344]! @ 0x158 │ │ + stc2l 14, cr0, [r1, #480]! @ 0x1e0 │ │ stc2l 1, cr7, [r0, #424]! @ 0x1a8 │ │ - stc2l 8, cr2, [r1, #612]! @ 0x264 │ │ + vcmla.f16 q9, , q3, #270 │ │ ldr r0, [pc, #3928] @ 2412500 │ │ mov r4, sl │ │ ldr r0, [pc, r0] │ │ sub r0, r0, #1 │ │ str r0, [fp, #-68] @ 0xffffffbc │ │ ldr r7, [pc, #3912] @ 2412504 │ │ cmp r0, #500 @ 0x1f4 │ │ @@ -1254440,15 +1254440,15 @@ │ │ add r5, pc, r5 │ │ add r1, pc, r1 │ │ mov r0, r5 │ │ bl 270e120 │ │ str r0, [r5] │ │ b 241168c │ │ strdeq fp, [r6, r0] │ │ - stc2l 7, cr2, [r2, #836]! @ 0x344 │ │ + stc2l 7, cr2, [r2, #1016]! @ 0x3f8 │ │ stc2l 4, cr2, [r3, #176]! @ 0xb0 │ │ ldr r0, [pc, #3988] @ 2412620 │ │ ldr r0, [pc, r0] │ │ cmp r0, #0 │ │ ble 241294c │ │ mov r0, r9 │ │ mov r1, r8 │ │ @@ -1254456,15 +1254456,15 @@ │ │ mov r3, #5 │ │ bl 270d9d0 │ │ cmp r0, #0 │ │ mov r5, r4 │ │ bne 2410f20 │ │ b 2412950 │ │ stc2l 13, cr13, [r3, #624]! @ 0x270 │ │ - vcmla.f16 d18, d1, d21, #270 │ │ + stc2l 8, cr2, [r1, #328]! @ 0x148 │ │ stc2l 2, cr12, [r3, #848]! @ 0x350 │ │ mov r0, r9 │ │ mov r1, r8 │ │ mov r2, #80 @ 0x50 │ │ mov r3, #5 │ │ bl 270d9e0 │ │ ldr r0, [pc, #4044] @ 24126ac │ │ @@ -1254477,23 +1254477,23 @@ │ │ b 241182c │ │ orreq r9, r7, r4, asr #19 │ │ stc2l 15, cr9, [r3, #64]! @ 0x40 │ │ orreq r6, r7, r4, lsr r7 │ │ orreq r7, r7, r4, asr #18 │ │ orreq r3, r8, r8, lsl #25 │ │ stc2l 2, cr12, [r3, #412]! @ 0x19c │ │ - stc2l 12, cr0, [r1, #952]! @ 0x3b8 │ │ + stc2l 13, cr0, [r1, #108]! @ 0x6c │ │ orreq r3, r8, r4, asr #24 │ │ - stc2l 7, cr2, [r1, #796]! @ 0x31c │ │ - stc2l 12, cr0, [r1, #776]! @ 0x308 │ │ - stc2l 7, cr2, [r2, #848]! @ 0x350 │ │ + stc2l 7, cr2, [r1, #976]! @ 0x3d0 │ │ + stc2l 12, cr0, [r1, #956]! @ 0x3bc │ │ + vcmla.f16 d18, d2, d1, #270 │ │ stc2l 8, cr10, [r2, #616]! @ 0x268 │ │ @ instruction: 0x018877b0 │ │ orreq fp, r7, r4, asr fp │ │ - stc2l 12, cr0, [r1, #280]! @ 0x118 │ │ + stc2l 12, cr0, [r1, #460]! @ 0x1cc │ │ vcmla.f16 d26, d2, d22, #270 │ │ orreq r7, r8, ip, lsr r7 │ │ ldr r0, [pc, #4076] @ 2412730 │ │ ldr r0, [pc, r0] │ │ ldr r4, [pc, #4072] @ 2412734 │ │ sub r1, r0, #1 │ │ cmp r1, #200 @ 0xc8 │ │ @@ -1254558,15 +1254558,15 @@ │ │ add r7, pc, r7 │ │ ldr r5, [pc, #4088] @ 241283c │ │ add r6, pc, r6 │ │ add sl, pc, sl │ │ add r5, pc, r5 │ │ b 2411638 │ │ stc2l 1, cr12, [r3, #396]! @ 0x18c │ │ - stc2l 2, cr6, [r2, #588]! @ 0x24c │ │ + stc2l 2, cr6, [r2, #768]! @ 0x300 │ │ stc2l 7, cr10, [r2, #628]! @ 0x274 │ │ stc2l 7, cr14, [r2, #816]! @ 0x330 │ │ ldr r0, [pc, #4056] @ 2412840 │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ cmp r1, #100 @ 0x64 │ │ @@ -1254651,15 +1254651,15 @@ │ │ ldr r2, [pc, #4084] @ 24129a8 │ │ add r1, pc, r1 │ │ add r2, pc, r2 │ │ bl 270e0e0 │ │ b 2411be0 │ │ orreq sl, r6, r8, ror #17 │ │ stc2l 11, cr9, [r3, #292]! @ 0x124 @ │ │ - stc2l 11, cr14, [r0, #120]! @ 0x78 @ │ │ + stc2l 11, cr14, [r0, #300]! @ 0x12c @ │ │ ldr r0, [pc, #4056] @ 24129ac │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #4052] @ 24129b0 │ │ ldr r1, [pc, r1] │ │ cmp r0, r1 │ │ bge 2412804 │ │ ldr r1, [pc, #4040] @ 24129b4 │ │ @@ -1254668,15 +1254668,15 @@ │ │ mov r3, #17 │ │ add r1, pc, r1 │ │ str r0, [r1] │ │ mov r0, r9 │ │ mov r1, r7 │ │ bl 270d9e0 │ │ b 2410850 │ │ - stc2l 0, cr6, [r2, #940]! @ 0x3ac │ │ + stc2l 1, cr6, [r2, #96]! @ 0x60 │ │ orreq fp, r7, r4, ror #18 │ │ orreq r8, r5, r4, ror #13 │ │ orreq r7, r7, r4, lsr #12 │ │ @ instruction: 0x0191b8b0 │ │ orreq r7, r7, ip, lsl r6 │ │ orreq r3, r8, r4, asr #18 │ │ ldr r0, [pc, #3976] @ 24129b8 │ │ @@ -1254716,17 +1254716,17 @@ │ │ ldr r0, [pc, #4004] @ 2412a5c │ │ add r0, pc, r0 │ │ str r4, [r0, r2, lsl #2] │ │ b 2411b10 │ │ eorseq r9, r3, ip, lsr #22 │ │ orrseq r7, r1, r0, lsl r3 │ │ orreq r3, r8, r0, ror #17 │ │ - stc2l 4, cr2, [r2, #448]! @ 0x1c0 │ │ + stc2l 4, cr2, [r2, #628]! @ 0x274 │ │ orrseq fp, r1, r8, asr #14 │ │ - stc2l 1, cr4, [r2, #428]! @ 0x1ac │ │ + stc2l 1, cr4, [r2, #608]! @ 0x260 │ │ ldr r0, [pc, #3968] @ 2412a60 │ │ mov r1, r2 │ │ mov r2, r7 │ │ movw r3, #1837 @ 0x72d │ │ add r0, pc, r0 │ │ bl 270da30 │ │ ldr r1, [pc, #3948] @ 2412a64 │ │ @@ -1254765,15 +1254765,15 @@ │ │ ldr r1, [pc, #3852] @ 2412a88 │ │ add r1, pc, r1 │ │ bl 270d9e0 │ │ b 2410850 │ │ @ instruction: 0x018585b4 │ │ orreq r7, r7, ip, lsr #11 │ │ orreq r9, r7, r0, asr #10 │ │ - stc2l 9, cr14, [r0, #164]! @ 0xa4 @ │ │ + stc2l 9, cr14, [r0, #254]! @ 0xfe @ │ │ orreq r7, r8, r4, lsr sl │ │ stc2l 10, cr9, [r3, #184]! @ 0xb8 @ │ │ orrseq fp, r1, r4, asr #14 │ │ ldr r0, [pc, #3812] @ 2412a8c │ │ ldr r0, [pc, r0] │ │ ldr r4, [pc, #3808] @ 2412a90 │ │ sub r1, r0, #1 │ │ @@ -1254800,22 +1254800,22 @@ │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ add r2, pc, r2 │ │ str r4, [r2, r1, lsl #2] │ │ b 2411c70 │ │ orreq r7, r8, ip, ror #6 │ │ stc2l 4, cr10, [r2, #116]! @ 0x74 │ │ orreq r7, r8, r8, lsl r3 │ │ - stc2l 3, cr2, [r2, #176]! @ 0xb0 │ │ - vcmla.f16 d16, d1, d14, #270 │ │ + stc2l 3, cr2, [r2, #356]! @ 0x164 │ │ + stc2l 8, cr0, [r1, #236]! @ 0xec │ │ stc2l 3, cr10, [r2, #952]! @ 0x3b8 │ │ - stc2l 2, cr2, [r2, #1008]! @ 0x3f0 │ │ + stc2l 3, cr2, [r2, #164]! @ 0xa4 │ │ stc2l 3, cr10, [r2, #728]! @ 0x2d8 │ │ orreq r7, r8, r8, asr #5 │ │ - stc2l 2, cr2, [r1, #780]! @ 0x30c │ │ - stc2l 7, cr0, [r1, #776]! @ 0x308 │ │ + stc2l 2, cr2, [r1, #960]! @ 0x3c0 │ │ + stc2l 7, cr0, [r1, #956]! @ 0x3bc │ │ ldr r0, [pc, #3996] @ 2412be0 │ │ mov r2, r7 │ │ movw r3, #1887 @ 0x75f │ │ add r0, pc, r0 │ │ bl 270da30 │ │ ldr r1, [pc, #3980] @ 2412be4 │ │ add r1, pc, r1 │ │ @@ -1254870,15 +1254870,15 @@ │ │ blt 2412968 │ │ ldr r5, [fp, #-32] @ 0xffffffe0 │ │ b 2411dc4 │ │ orreq r7, r7, r0, lsr #8 │ │ orreq fp, r8, r8, lsl #8 │ │ orreq r6, r8, r8, lsl #19 │ │ strdeq r7, [r7, r0] │ │ - stc2l 7, cr14, [r0, #632]! @ 0x278 │ │ + stc2l 7, cr14, [r0, #812]! @ 0x32c │ │ @ instruction: 0x018773b4 │ │ orreq r3, r8, ip, asr #12 │ │ vcmla.f16 , , , #270 │ │ @ instruction: 0x01887694 │ │ stc2l 2, cr10, [r2, #568]! @ 0x238 │ │ orreq r7, r7, ip, asr r3 │ │ orreq r9, r8, ip, ror #4 │ │ @@ -1254935,16 +1254935,16 @@ │ │ ldr r5, [pc, #3988] @ 2412db8 │ │ ldr r7, [pc, #3988] @ 2412dbc │ │ add r5, pc, r5 │ │ add r7, pc, r7 │ │ b 2411e68 │ │ orreq r9, r7, r8, ror #4 │ │ @ instruction: 0x018772b4 │ │ - stc2l 5, cr14, [r1, #104]! @ 0x68 │ │ - stc2l 6, cr14, [r0, #328]! @ 0x148 │ │ + stc2l 5, cr14, [r1, #284]! @ 0x11c │ │ + stc2l 6, cr14, [r0, #508]! @ 0x1fc │ │ ldr r0, [pc, #3960] @ 2412dc0 │ │ movw r3, #2074 @ 0x81a │ │ ldr r7, [pc, #3956] @ 2412dc4 │ │ add r0, pc, r0 │ │ add r7, pc, r7 │ │ mov r2, r7 │ │ bl 270da30 │ │ @@ -1254973,15 +1254973,15 @@ │ │ add r0, r0, r1, lsl #2 │ │ ldr r1, [pc, #3868] @ 2412ddc │ │ add r1, pc, r1 │ │ bl 270e0e0 │ │ b 2412008 │ │ orreq r9, r8, r8, lsr #32 │ │ orreq r9, r7, r4, lsr #4 │ │ - stc2l 5, cr14, [r0, #1016]! @ 0x3f8 │ │ + stc2l 6, cr14, [r0, #172]! @ 0xac │ │ orreq r7, r8, r0, ror #13 │ │ ldrdeq r9, [r7, ip] │ │ stc2l 0, cr8, [r2, #176]! @ 0xb0 │ │ orrseq r0, r1, ip, ror #17 │ │ orreq r3, r8, ip, lsl #9 │ │ orreq fp, r7, r8, asr r4 │ │ orreq r9, r7, r4, lsl #3 │ │ @@ -1254993,56 +1254993,56 @@ │ │ strdeq r9, [r7, r0] │ │ strheq r9, [r7, r0] │ │ stc2l 9, cr11, [r3, #294]! @ 0x126 @ │ │ @ instruction: 0x01879098 │ │ stc2l 15, cr3, [r0, #648]! @ 0x288 │ │ orreq r6, r8, ip, asr #12 │ │ orreq r9, r7, r0, asr r0 │ │ - stc2l 4, cr14, [r0, #248]! @ 0xf8 │ │ + stc2l 4, cr14, [r0, #428]! @ 0x1ac │ │ orreq r9, r7, r0 │ │ stc2l 14, cr7, [r2, #288]! @ 0x120 │ │ orrseq r0, r1, ip, lsl #14 │ │ @ instruction: 0x0191abd0 │ │ orrseq fp, r1, r4, lsr #2 │ │ - stc2l 2, cr12, [r1, #636]! @ 0x27c │ │ + stc2l 2, cr12, [r1, #816]! @ 0x330 │ │ vcmla.f16 d27, d3, d31, #270 │ │ - stc2l 3, cr14, [r0, #312]! @ 0x138 │ │ + stc2l 3, cr14, [r0, #492]! @ 0x1ec │ │ orreq r7, r5, ip, ror pc │ │ orreq r8, r7, r0, lsr #30 │ │ stc2l 13, cr11, [r2, #620]! @ 0x26c │ │ - stc2l 2, cr0, [r1, #456]! @ 0x1c8 │ │ + stc2l 2, cr0, [r1, #636]! @ 0x27c │ │ orrseq r4, r1, ip, lsr #9 │ │ ldrdeq r7, [r8, r0] │ │ orreq r8, r7, r8, asr #29 │ │ - stc2l 2, cr14, [r0, #728]! @ 0x2d8 │ │ + stc2l 2, cr14, [r0, #908]! @ 0x38c │ │ stc2l 7, cr11, [r3, #380]! @ 0x17c │ │ - stc2l 2, cr14, [r0, #504]! @ 0x1f8 │ │ + stc2l 2, cr14, [r0, #684]! @ 0x2ac │ │ orreq r7, r5, ip, lsr #29 │ │ orreq r8, r7, r0, asr lr │ │ stc2l 5, cr8, [r0, #668]! @ 0x29c │ │ - stc2l 1, cr0, [r1, #648]! @ 0x288 │ │ + stc2l 1, cr0, [r1, #828]! @ 0x33c │ │ orrseq r4, r1, ip, lsr #23 │ │ orreq r8, r7, r0, lsl #28 │ │ - stc2l 1, cr14, [r0, #952]! @ 0x3b8 │ │ + stc2l 2, cr14, [r0, #108]! @ 0x6c │ │ stc2l 6, cr11, [r3, #396]! @ 0x18c │ │ - stc2l 1, cr14, [r0, #520]! @ 0x208 │ │ + stc2l 1, cr14, [r0, #700]! @ 0x2bc │ │ @ instruction: 0x01857db0 │ │ orreq r8, r7, r4, asr sp │ │ stc2l 11, cr7, [r2, #652]! @ 0x28c @ │ │ - stc2l 0, cr0, [r1, #664]! @ 0x298 │ │ + stc2l 0, cr0, [r1, #844]! @ 0x34c │ │ orrseq r5, r1, r0, lsl #5 │ │ orreq r8, r7, r4, lsl #26 │ │ ldrdeq r8, [r7, r8] │ │ - stc2l 11, cr1, [r1, #484]! @ 0x1e4 @ │ │ - stc2l 0, cr14, [r0, #952]! @ 0x3b8 │ │ + stc2l 11, cr1, [r1, #664]! @ 0x298 @ │ │ + stc2l 1, cr14, [r0, #108]! @ 0x6c │ │ orrseq r5, r1, r4, lsl #20 │ │ @ instruction: 0x01878cb4 │ │ @ instruction: 0x01878c90 │ │ stc2l 12, cr14, [r3, #276]! @ 0x114 │ │ - stc2l 0, cr14, [r0, #632]! @ 0x278 │ │ + stc2l 0, cr14, [r0, #812]! @ 0x32c │ │ ldr r0, [pc, #4008] @ 2412f78 │ │ ldr r0, [pc, r0] │ │ ldr r4, [pc, #4004] @ 2412f7c │ │ sub r1, r0, #1 │ │ cmp r1, #100 @ 0x64 │ │ ldr r4, [pc, r4] │ │ bcc 2411ffc │ │ @@ -1255336,17 +1255336,17 @@ │ │ add r0, pc, r0 │ │ add r0, r0, r1, lsl #2 │ │ ldr r1, [pc, #4004] @ 2413414 │ │ add r1, pc, r1 │ │ bl 270e0e0 │ │ b 2412554 │ │ orrseq r6, r1, r4, lsl #3 │ │ - stc2l 15, cr15, [r0, #968]! @ 0x3c8 │ │ + stc2l 0, cr0, [r1, #124]! @ 0x7c │ │ orreq r2, r8, r0, ror #30 │ │ - stc2l 11, cr1, [r2] @ │ │ + stc2l 11, cr1, [r2, #180]! @ 0xb4 @ │ │ orreq r0, r9, r8, asr r4 │ │ orreq r0, r9, r0, asr #8 │ │ orreq r2, r8, r4, lsl #31 │ │ mov r0, r9 │ │ mov r1, r8 │ │ mov r2, #80 @ 0x50 │ │ mov r3, #5 │ │ @@ -1255361,24 +1255361,24 @@ │ │ ldr sl, [pc, #3924] @ 2413420 │ │ ldr r7, [pc, #3924] @ 2413424 │ │ add sl, pc, sl │ │ add r7, pc, r7 │ │ b 2411d84 │ │ orreq r6, r8, r4, lsl #4 │ │ stc2l 11, cr14, [r3, #744]! @ 0x2e8 @ │ │ - stc2l 0, cr14, [r0, #104]! @ 0x68 │ │ + stc2l 0, cr14, [r0, #284]! @ 0x11c │ │ orreq r0, r9, r0, ror #1 │ │ orreq r6, r8, r0, asr #3 │ │ stc2l 11, cr14, [r3, #472]! @ 0x1d8 @ │ │ - stc2l 15, cr13, [r0, #856]! @ 0x358 │ │ + stc2l 0, cr14, [r0, #12]! │ │ @ instruction: 0x0189009c │ │ strdeq r2, [r8, r4] │ │ orreq r0, r9, r8, lsr #7 │ │ orreq r8, r7, r8, asr fp │ │ - stc2l 15, cr13, [r0, #344]! @ 0x158 │ │ + stc2l 15, cr13, [r0, #524]! @ 0x20c │ │ stc2l 9, cr7, [r2, #304]! @ 0x130 @ │ │ orrseq r0, r1, r0, ror #4 │ │ orrseq sl, r1, r4, lsr #14 │ │ ldr r0, [pc, #3852] @ 2413428 │ │ ldr r0, [pc, r0] │ │ ldr r4, [pc, #3848] @ 241342c │ │ sub r1, r0, #1 │ │ @@ -1255512,19 +1255512,19 @@ │ │ bhi 24128c8 │ │ ldr r7, [pc, #3980] @ 24136b8 │ │ add r7, pc, r7 │ │ b 2411b3c │ │ strexeq r5, ip, [r8] │ │ orreq r2, r8, r0, lsl #26 │ │ stc2l 9, cr14, [r3, #148]! @ 0x94 @ │ │ - stc2l 13, cr13, [r0, #680]! @ 0x2a8 │ │ + stc2l 13, cr13, [r0, #860]! @ 0x35c │ │ orreq pc, r8, r0, ror lr @ │ │ orreq r8, r7, ip, ror r9 │ │ stc2l 2, cr11, [r3, #236]! @ 0xec │ │ - stc2l 13, cr13, [r0, #360]! @ 0x168 │ │ + stc2l 13, cr13, [r0, #540]! @ 0x21c │ │ orreq r2, r8, r0, lsl #25 │ │ stc2l 8, cr3, [r0, #244]! @ 0xf4 │ │ ldr r0, [pc, #3932] @ 24136bc │ │ mov r2, r7 │ │ mov r3, #1888 @ 0x760 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ @@ -1255559,36 +1255559,36 @@ │ │ sub r1, r0, #1 │ │ cmp r1, #199 @ 0xc7 │ │ bhi 24129c8 │ │ ldr r6, [pc, #4036] @ 24137b4 │ │ add r6, pc, r6 │ │ mov r7, sl │ │ b 2411c8c │ │ - stc2l 13, cr13, [r0, #88]! @ 0x58 │ │ + stc2l 13, cr13, [r0, #268]! @ 0x10c │ │ orreq r7, r5, r8, asr #18 │ │ orreq r3, sl, r4, lsr #19 │ │ mov r0, r9 │ │ mov r1, r6 │ │ mov r2, #80 @ 0x50 │ │ mov r3, #4 │ │ bl 270d9e0 │ │ b 2410850 │ │ ldrsbteq r8, [r3], -r8 │ │ str r5, [fp, #-32] @ 0xffffffe0 │ │ ldr r5, [pc, #3980] @ 24137b8 │ │ add r5, pc, r5 │ │ b 2412968 │ │ - stc2l 12, cr13, [r0, #872]! @ 0x368 │ │ - stc2l 12, cr15, [r0, #296]! @ 0x128 │ │ + stc2l 13, cr13, [r0, #28]! │ │ + stc2l 12, cr15, [r0, #476]! @ 0x1dc │ │ @ instruction: 0x01886db4 │ │ vcmla.f16 d25, d2, d22, #270 │ │ orreq r6, r7, ip, ror #17 │ │ stc2l 14, cr4, [r3, #148]! @ 0x94 │ │ orreq r6, r8, r4, ror #13 │ │ - stc2l 6, cr1, [r2, #1008]! @ 0x3f0 │ │ + stc2l 7, cr1, [r2, #164]! @ 0xa4 │ │ @ instruction: 0x01886bbc │ │ mov r0, r5 │ │ mov r2, r6 │ │ movw r3, #1784 @ 0x6f8 │ │ bl 270da30 │ │ ldr r1, [pc, #3920] @ 24137bc │ │ ldr r1, [pc, r1] │ │ @@ -1255608,17 +1255608,17 @@ │ │ ldr r2, [pc, #3872] @ 24137c8 │ │ mov r1, r0 │ │ add r2, pc, r2 │ │ b 2412678 │ │ orreq r3, r8, r0, asr #22 │ │ @ instruction: 0x0191a9bc │ │ stc2l 1, cr1, [r3, #604]! @ 0x25c │ │ - stc2l 11, cr15, [r0, #632]! @ 0x278 @ │ │ + stc2l 11, cr15, [r0, #812]! @ 0x32c @ │ │ orrseq sl, r1, ip, ror r9 │ │ - stc2l 12, cr5, [r1, #756]! @ 0x2f4 │ │ + stc2l 12, cr5, [r1, #936]! @ 0x3a8 │ │ ldr r0, [pc, #4072] @ 24138b8 │ │ mov r2, r7 │ │ movw r3, #1845 @ 0x735 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ ldr r1, [pc, #4056] @ 24138bc │ │ mov r2, #0 │ │ @@ -1255639,19 +1255639,19 @@ │ │ mov r1, r0 │ │ ldr sl, [pc, #4004] @ 24138cc │ │ mov r0, #0 │ │ ldr r7, [pc, #4000] @ 24138d0 │ │ add sl, pc, sl │ │ add r7, pc, r7 │ │ b 2411b5c │ │ - stc2l 11, cr13, [r0, #840]! @ 0x348 @ │ │ - stc2l 11, cr13, [r0, #792]! @ 0x318 @ │ │ + stc2l 11, cr13, [r0, #1020]! @ 0x3fc @ │ │ + stc2l 11, cr13, [r0, #972]! @ 0x3cc @ │ │ orreq r6, r8, r8, ror r9 │ │ ldrdeq r6, [r7, ip] │ │ - stc2l 11, cr13, [r0, #552]! @ 0x228 @ │ │ + stc2l 11, cr13, [r0, #732]! @ 0x2dc @ │ │ mov r5, r4 │ │ ldr r0, [fp, #-68] @ 0xffffffbc │ │ str r0, [fp, #-32] @ 0xffffffe0 │ │ ldr sl, [pc, #3956] @ 24138d4 │ │ ldr r7, [pc, #3956] @ 24138d8 │ │ add sl, pc, sl │ │ add r7, pc, r7 │ │ @@ -1255673,15 +1255673,15 @@ │ │ orreq r5, r8, ip, lsr #26 │ │ orreq sl, r8, r4, lsr #15 │ │ orreq r6, r7, r4, ror #13 │ │ orreq r5, r7, ip, lsr #9 │ │ orreq r6, r7, r0, asr #13 │ │ orreq r6, r7, r4, lsr #14 │ │ orreq r7, r5, r8, lsl r7 │ │ - stc2l 10, cr13, [r0, #792]! @ 0x318 @ │ │ + stc2l 10, cr13, [r0, #972]! @ 0x3cc @ │ │ orreq r6, r8, r8, lsr #23 │ │ ldr r0, [pc, #3856] @ 24138e0 │ │ mov r2, r7 │ │ movw r3, #1891 @ 0x763 │ │ mov r6, sl │ │ add r0, pc, r0 │ │ bl 270da30 │ │ @@ -1255713,28 +1255713,28 @@ │ │ add r8, pc, r8 │ │ add r5, pc, r5 │ │ b 2411cac │ │ stc2l 11, cr8, [r3, #728]! @ 0x2d8 @ │ │ orrseq sl, r1, r8, asr #17 │ │ @ instruction: 0x018766b8 │ │ ldrdeq r8, [r8, r4] │ │ - stc2l 9, cr11, [r1, #80]! @ 0x50 @ │ │ + stc2l 9, cr11, [r1, #170]! @ 0xaa @ │ │ @ instruction: 0x01888594 │ │ orreq r6, r7, r0, asr r6 │ │ @ instruction: 0x0188a4b0 │ │ ldrdeq r2, [r8, r4] │ │ - stc2l 4, cr1, [r1, #348]! @ 0x15c │ │ + stc2l 4, cr1, [r1, #528]! @ 0x210 │ │ orreq r6, r8, r4, lsr r9 │ │ @ instruction: 0x018883b0 │ │ orreq r6, r8, r0, lsr r4 │ │ orreq r6, r8, r4, ror r7 │ │ stc2l 5, cr13, [r2, #304]! @ 0x130 │ │ orreq r6, r7, ip, lsr #11 │ │ orreq r5, r8, r8, lsr #22 │ │ - stc2l 9, cr13, [r0, #164]! @ 0xa4 @ │ │ + stc2l 9, cr13, [r0, #254]! @ 0xfe @ │ │ ldr r1, [pc, #3936] @ 2413a00 │ │ add r1, pc, r1 │ │ ldrb r1, [r1] │ │ cmp r1, #1 │ │ bne 24132b4 │ │ ldr r4, [pc, #3920] @ 2413a04 │ │ ldr r1, [pc, #3920] @ 2413a08 │ │ @@ -1255809,29 +1255809,29 @@ │ │ ldr r2, [r5, r1, lsl #2] │ │ add r0, pc, r0 │ │ str r2, [r0] │ │ b 2412c7c │ │ orreq r6, r8, r0, lsl #14 │ │ strdeq r5, [r8, r4] │ │ orreq r1, r8, r4, lsr r5 │ │ - stc2l 15, cr2, [r2, #1020]! @ 0x3fc │ │ + stc2l 0, cr3, [r2, #176]! @ 0xb0 │ │ orreq r1, r8, r4, ror #9 │ │ orreq r5, r8, ip, ror sl │ │ orreq r6, r7, r4, asr #8 │ │ orreq pc, r8, r4, asr #12 │ │ orreq pc, r8, r0, asr r9 @ │ │ ldrdeq r6, [r8, r4] │ │ orreq sl, r8, r0, lsl fp │ │ strdeq r6, [r7, r0] │ │ eorseq r8, r3, ip, lsr #18 │ │ stc2l 1, cr1, [r0, #812]! @ 0x32c │ │ orreq r8, r7, r0, lsl #8 │ │ orreq r2, r8, r8, ror #13 │ │ orrseq sl, r1, r0, lsr #10 │ │ - stc2l 15, cr2, [r2, #388]! @ 0x184 │ │ + stc2l 15, cr2, [r2, #568]! @ 0x238 │ │ orreq r8, r7, r4, ror #6 │ │ ldr r0, [pc, #3916] @ 2413b74 │ │ movw r3, #6249 @ 0x1869 │ │ ldr r2, [pc, #3912] @ 2413b78 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1255928,21 +1255928,21 @@ │ │ b 2412e40 │ │ orreq r8, r7, r8, asr r3 │ │ orreq r2, r8, r0, asr #12 │ │ @ instruction: 0x0190ea94 │ │ orreq r2, r8, ip, asr #12 │ │ orreq r6, r7, r4, asr #6 │ │ orreq r7, r5, r4, lsr r3 │ │ - stc2l 6, cr13, [r0, #936]! @ 0x3a8 │ │ - stc2l 5, cr13, [r1, #552]! @ 0x228 │ │ - stc2l 6, cr13, [r0, #776]! @ 0x308 │ │ + stc2l 7, cr13, [r0, #92]! @ 0x5c │ │ + stc2l 5, cr13, [r1, #732]! @ 0x2dc │ │ + stc2l 6, cr13, [r0, #956]! @ 0x3bc │ │ strdeq r7, [r5, r4] │ │ orreq r8, r8, ip, lsl #1 │ │ ldrdeq r6, [r7, r0] │ │ - stc2l 5, cr13, [r1, #232]! @ 0xe8 │ │ + stc2l 5, cr13, [r1, #412]! @ 0x19c │ │ orreq r8, r8, r8, asr #32 │ │ @ instruction: 0x01882590 │ │ ldr r0, [pc, #4044] @ 2413db4 │ │ mov r1, r4 │ │ ldr r2, [pc, #4040] @ 2413db8 │ │ movw r3, #6259 @ 0x1873 │ │ add r0, pc, r0 │ │ @@ -1256041,20 +1256041,20 @@ │ │ ldr r0, [pc, #4044] @ 2413f38 │ │ add r0, pc, r0 │ │ ldr r0, [r0, r1, lsl #2] │ │ str r0, [r5, #4] │ │ b 241370c │ │ orreq r6, r7, r4, lsl #3 │ │ orreq r2, r8, r0, ror r4 │ │ - stc2l 3, cr13, [r1, #920]! @ 0x398 │ │ + stc2l 4, cr13, [r1, #76]! @ 0x4c │ │ strdeq r7, [r8, r8] │ │ orreq r2, r8, r0, asr #8 │ │ stc2l 15, cr6, [r2, #256]! @ 0x100 │ │ orreq r8, r7, r8, asr #1 │ │ - stc2l 5, cr5, [r1, #596]! @ 0x254 │ │ + stc2l 5, cr5, [r1, #776]! @ 0x308 │ │ @ instruction: 0x0190f7d8 │ │ orreq sl, r7, r4, asr r3 │ │ ldr r0, [pc, #3988] @ 2413f3c │ │ mov r1, #25 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #3976] @ 2413f40 │ │ @@ -1256245,26 +1256245,26 @@ │ │ mov r0, r5 │ │ bl 270d800 │ │ ldr r0, [pc, #4076] @ 2414290 │ │ mov r1, #19 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ b 240a740 │ │ - stc2l 12, cr0, [r1, #836]! @ 0x344 │ │ + stc2l 12, cr0, [r1, #1016]! @ 0x3f8 │ │ ldr r1, [pc, #4056] @ 2414294 │ │ mov r0, r8 │ │ ldr r2, [pc, #4052] @ 2414298 │ │ add r1, pc, r1 │ │ add r2, pc, r2 │ │ b 2412aec │ │ orrseq r4, r1, r0, ror #22 │ │ orreq r7, r7, r0, lsr #28 │ │ stc2l 6, cr10, [r3, #908]! @ 0x38c │ │ orreq r2, r8, r4, lsr r1 │ │ - stc2l 0, cr9, [r1, #540]! @ 0x21c │ │ + stc2l 0, cr9, [r1, #720]! @ 0x2d0 │ │ orreq r7, r7, r0, asr #27 │ │ stc2l 6, cr10, [r3, #524]! @ 0x20c │ │ orreq r2, r8, r0, asr #1 │ │ stc2l 13, cr13, [r3, #20]! │ │ orrseq r5, r1, ip, asr #4 │ │ orreq pc, r8, r0, asr #10 │ │ orreq r2, r8, ip, rrx │ │ @@ -1256338,15 +1256338,15 @@ │ │ orreq r5, r8, ip, lsr #5 │ │ stc2l 12, cr13, [r3, #392]! @ 0x188 │ │ orreq pc, r8, r8, lsl #3 │ │ orreq r1, r8, r4, ror #31 │ │ orrseq r9, r1, r0, ror #27 │ │ stc2l 10, cr0, [r0, #52]! @ 0x34 @ │ │ @ instruction: 0x01885abc │ │ - stc2l 10, cr0, [r1, #732]! @ 0x2dc @ │ │ + stc2l 10, cr0, [r1, #912]! @ 0x390 @ │ │ orreq r5, r8, r4, asr #3 │ │ orreq r1, r8, r8, lsr #30 │ │ stc2l 11, cr13, [r3, #456]! @ 0x1c8 @ │ │ @ instruction: 0x0188f09c │ │ orreq r7, r7, r8, lsr #23 │ │ ldr r0, [pc, #4012] @ 24143f0 │ │ movw r3, #8093 @ 0x1f9d │ │ @@ -1256424,25 +1256424,25 @@ │ │ mvn r1, #23 │ │ add r1, r1, r0, lsl #3 │ │ str r1, [fp, #-36] @ 0xffffffdc │ │ b 241360c │ │ stc2l 4, cr10, [r3, #412]! @ 0x19c │ │ @ instruction: 0x01881eb0 │ │ stc2l 10, cr2, [r0, #436]! @ 0x1b4 @ │ │ - stc2l 9, cr0, [r1, #334]! @ 0x14e @ │ │ + stc2l 9, cr0, [r1, #424]! @ 0x1a8 @ │ │ orreq r6, r5, r4, ror fp │ │ ldrdeq r2, [sl, r0] │ │ eorseq r8, r3, r4 │ │ orreq r5, r8, r4, lsl #19 │ │ - stc2l 13, cr10, [r1, #880]! @ 0x370 │ │ + stc2l 14, cr10, [r1, #36]! @ 0x24 │ │ orreq r7, r8, r8, asr #20 │ │ orreq r5, r7, r4, lsl #22 │ │ - stc2l 9, cr0, [r2, #120]! @ 0x78 @ │ │ + stc2l 9, cr0, [r2, #210]! @ 0xd2 @ │ │ orreq r9, r8, r8, asr r9 │ │ - stc2l 13, cr14, [r0, #984]! @ 0x3d8 │ │ + stc2l 14, cr14, [r0, #140]! @ 0x8c │ │ stc2l 10, cr12, [r2, #176]! @ 0xb0 @ │ │ ldr r0, [pc, #3988] @ 2414548 │ │ mov r1, r4 │ │ ldr r2, [pc, #4092] @ 24145b8 │ │ movw r3, #8105 @ 0x1fa9 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1256503,19 +1256503,19 @@ │ │ orreq r5, r8, r4, ror #17 │ │ strdeq r9, [r8, ip] │ │ orreq r5, r7, r8, ror sl │ │ orreq r1, r8, r0, lsl sp │ │ stc2l 15, cr3, [r3, #692]! @ 0x2b4 │ │ orreq r5, r8, r0, ror #26 │ │ orreq r5, r7, ip, lsr sl │ │ - stc2l 8, cr0, [r1, #380]! @ 0x17c │ │ - stc2l 5, cr2, [r2, #456]! @ 0x1c8 │ │ + vcmla.f16 d16, d17, d12, #270 │ │ + stc2l 5, cr2, [r2, #636]! @ 0x27c │ │ orreq r4, r8, ip, ror #30 │ │ orreq r5, r7, r0, asr #18 │ │ - stc2l 13, cr12, [r0, #548]! @ 0x224 │ │ + stc2l 13, cr12, [r0, #728]! @ 0x2d8 │ │ ldr r0, [pc, #4068] @ 24146b8 │ │ movw r3, #4658 @ 0x1232 │ │ ldr r2, [pc, #4064] @ 24146bc │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #4052] @ 24146c0 │ │ @@ -1256564,21 +1256564,21 @@ │ │ add r0, pc, r0 │ │ mvneq r4, #0 │ │ mov r1, #5 │ │ str r4, [r5, #20] │ │ b 2413254 │ │ orreq lr, r8, r4, lsr #22 │ │ orreq r4, r8, ip, lsr #30 │ │ - stc2l 14, cr2, [r1, #240]! @ 0xf0 │ │ + stc2l 14, cr2, [r1, #420]! @ 0x1a4 │ │ orreq r4, r8, r4, lsl #30 │ │ - stc2l 12, cr14, [r0, #632]! @ 0x278 │ │ + stc2l 12, cr14, [r0, #812]! @ 0x32c │ │ vcmla.f16 q12, q1, q3, #270 │ │ orreq r5, r7, r8, ror #17 │ │ orreq r9, r8, r0, asr r7 │ │ - stc2l 7, cr0, [r2, #112]! @ 0x70 │ │ + stc2l 7, cr0, [r2, #292]! @ 0x124 │ │ orreq r9, r8, r0, lsr #14 │ │ ldr r0, [pc, #3860] @ 24146e8 │ │ mov r1, #25 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #3848] @ 24146ec │ │ ldr r0, [pc, r0] │ │ @@ -1256631,23 +1256631,23 @@ │ │ add r0, pc, r0 │ │ mov r2, #1 │ │ bl 270da60 │ │ ldr r0, [pc, #3692] @ 241471c │ │ mov r1, #18 │ │ add r0, pc, r0 │ │ b 24105d8 │ │ - stc2l 11, cr12, [r1, #8]! @ │ │ + stc2l 11, cr12, [r1, #188]! @ 0xbc @ │ │ orreq r7, r8, r4, lsl r6 │ │ orreq r5, r7, r0, ror #16 │ │ - stc2l 12, cr12, [r0, #40]! @ 0x28 │ │ - stc2l 11, cr12, [r0, #1016]! @ 0x3f8 @ │ │ + stc2l 12, cr12, [r0, #220]! @ 0xdc │ │ + stc2l 12, cr12, [r0, #172]! @ 0xac │ │ orreq r5, r8, ip, asr r6 │ │ - stc2l 6, cr0, [r1, #348]! @ 0x15c │ │ + stc2l 6, cr0, [r1, #528]! @ 0x210 │ │ orreq r5, r8, r8, lsr #12 │ │ - stc2l 6, cr0, [r1, #140]! @ 0x8c │ │ + stc2l 6, cr0, [r1, #320]! @ 0x140 │ │ stc2l 0, cr0, [r3, #1000]! @ 0x3e8 │ │ stc2l 6, cr13, [r3, #856]! @ 0x358 │ │ ldr r0, [pc, #4044] @ 24148b8 │ │ add r0, pc, r0 │ │ ldrb r0, [r0] │ │ cmp r0, #1 │ │ bne 2414158 │ │ @@ -1256708,18 +1256708,18 @@ │ │ ldr r0, [pc, #3856] @ 24148e8 │ │ ldr r2, [r5, r1, lsl #2] │ │ add r0, pc, r0 │ │ str r2, [r0] │ │ b 2413a88 │ │ orreq lr, r8, r0, lsl #24 │ │ orreq r4, r8, r4, ror #25 │ │ - stc2l 9, cr8, [r1, #296]! @ 0x128 @ │ │ - stc2l 10, cr12, [r0, #952]! @ 0x3b8 @ │ │ - stc2l 10, cr14, [r0, #296]! @ 0x128 @ │ │ - stc2l 5, cr0, [r2, #384]! @ 0x180 │ │ + stc2l 9, cr8, [r1, #386]! @ 0x182 @ │ │ + stc2l 11, cr12, [r0, #108]! @ 0x6c @ │ │ + stc2l 10, cr14, [r0, #476]! @ 0x1dc @ │ │ + stc2l 5, cr0, [r2, #564]! @ 0x234 │ │ stc2l 6, cr8, [r2, #152]! @ 0x98 │ │ orreq r7, r7, r8, asr r6 │ │ orreq r7, r7, r4, asr #12 │ │ orreq r9, r6, r8, lsr #15 │ │ orreq r5, r7, r4, ror r3 │ │ orreq r5, r7, r8, asr r6 │ │ orreq r4, r7, r8, lsl #7 │ │ @@ -1256801,25 +1256801,25 @@ │ │ cmp r4, #199 @ 0xc7 │ │ bhi 2413b8c │ │ add r0, r0, r0, lsl #1 │ │ mvn r1, #23 │ │ add r1, r1, r0, lsl #3 │ │ str r1, [fp, #-36] @ 0xffffffdc │ │ b 2413bec │ │ - stc2l 0, cr4, [r2, #456]! @ 0x1c8 │ │ - stc2l 9, cr12, [r0, #268]! @ 0x10c @ │ │ + stc2l 0, cr4, [r2, #636]! @ 0x27c │ │ + stc2l 9, cr12, [r0, #358]! @ 0x166 @ │ │ orreq r5, r7, ip, asr #8 │ │ orreq r5, r7, r4, lsr #11 │ │ @ instruction: 0x018742b8 │ │ - stc2l 15, cr3, [r2, #880]! @ 0x370 │ │ - vcmla.f16 q14, q8, q9, #270 │ │ + stc2l 0, cr4, [r2, #36]! @ 0x24 │ │ + stc2l 9, cr12, [r0, #30]! @ │ │ orreq r4, r7, r0, asr #4 │ │ strdeq r5, [r7, ip] │ │ - stc2l 7, cr10, [r1, #744]! @ 0x2e8 │ │ - vcmla.f16 d28, d16, d18, #270 │ │ + stc2l 7, cr10, [r1, #924]! @ 0x39c │ │ + vcmla.f16 q14, q8, , #270 │ │ ldr r0, [pc, #3792] @ 2414a64 │ │ mov r1, r4 │ │ ldr r2, [pc, #3788] @ 2414a68 │ │ movw r3, #8937 @ 0x22e9 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1256873,20 +1256873,20 @@ │ │ mov r1, r5 │ │ stmib sp, {r6, sl} │ │ str r9, [sp, #12] │ │ bl 270e500 │ │ b 2410640 │ │ orreq r5, r7, r0, lsr r4 │ │ stc2l 11, cr4, [r0, #44]! @ 0x2c @ │ │ - vcmla.f16 q14, q0, q9, #270 │ │ + vcmla.f16 d28, d16, d15, #270 │ │ strdeq r5, [r7, r4] │ │ @ instruction: 0x01875190 │ │ orreq ip, r5, r0, lsr #20 │ │ stc2l 3, cr13, [r3, #728]! @ 0x2d8 │ │ - stc2l 8, cr12, [r0, #88]! @ 0x58 │ │ + vcmla.f16 q14, q0, , #270 │ │ orreq ip, r5, r4, ror #19 │ │ orreq lr, r8, r8, asr #17 │ │ ldrdeq r7, [r7, r4] │ │ orreq ip, r5, r8, asr #19 │ │ orreq lr, r8, r0, asr #23 │ │ @ instruction: 0x01877394 │ │ orreq r5, r7, r8, lsr r3 │ │ @@ -1256950,28 +1256950,28 @@ │ │ cmp r1, #9 │ │ bhi 2413df8 │ │ ldr r0, [pc, #4072] @ 2414d90 │ │ ldr r2, [r5, r1, lsl #2] │ │ add r0, pc, r0 │ │ str r2, [r0] │ │ b 2413e54 │ │ - stc2l 14, cr1, [r2, #348]! @ 0x15c │ │ - stc2l 7, cr12, [r0, #120]! @ 0x78 │ │ + stc2l 14, cr1, [r2, #528]! @ 0x210 │ │ + stc2l 7, cr12, [r0, #300]! @ 0x12c │ │ orreq r5, r7, ip, lsr #5 │ │ - stc2l 5, cr8, [r1, #528]! @ 0x210 │ │ - stc2l 6, cr12, [r0, #888]! @ 0x378 │ │ + stc2l 5, cr8, [r1, #708]! @ 0x2c4 │ │ + stc2l 7, cr12, [r0, #44]! @ 0x2c │ │ orreq ip, r5, r8, lsr #17 │ │ orreq r9, r8, ip, ror #18 │ │ ldrdeq r0, [r8, r8] │ │ stc2l 1, cr2, [r0, #676]! @ 0x2a4 │ │ - stc2l 6, cr12, [r0, #520]! @ 0x208 │ │ + stc2l 6, cr12, [r0, #700]! @ 0x2bc │ │ orreq r2, sl, r4, lsl r3 │ │ ldrdeq r3, [r7, r4] │ │ stc2l 0, cr6, [r2, #576]! @ 0x240 │ │ - stc2l 6, cr12, [r0, #200]! @ 0xc8 │ │ + stc2l 6, cr12, [r0, #380]! @ 0x17c │ │ orrseq lr, r0, r0, asr r9 │ │ orreq ip, r5, r0, ror #15 │ │ stc2l 1, cr2, [r0, #8]! │ │ ldr r0, [pc, #4092] @ 2414dfc │ │ movw r3, #7082 @ 0x1baa │ │ ldr r2, [pc, #4088] @ 2414e00 │ │ add r0, pc, r0 │ │ @@ -1257044,31 +1257044,31 @@ │ │ cmp r4, #199 @ 0xc7 │ │ bhi 2413f70 │ │ add r0, r0, r0, lsl #1 │ │ mvn r1, #23 │ │ add r1, r1, r0, lsl #3 │ │ str r1, [fp, #-36] @ 0xffffffdc │ │ b 2413fd0 │ │ - stc2l 5, cr12, [r0, #904]! @ 0x388 │ │ + stc2l 6, cr12, [r0, #60]! @ 0x3c │ │ orreq r4, r8, r8, lsr #15 │ │ orreq ip, r5, r0, lsr #15 │ │ orrseq r2, r1, r0, ror #14 │ │ - stc2l 13, cr1, [r2, #640]! @ 0x280 │ │ + stc2l 13, cr1, [r2, #820]! @ 0x334 │ │ orreq ip, r5, r0, asr #14 │ │ stc2l 15, cr5, [r2, #624]! @ 0x270 │ │ - stc2l 5, cr12, [r0, #248]! @ 0xf8 │ │ + stc2l 5, cr12, [r0, #428]! @ 0x1ac │ │ orrseq lr, r0, ip, asr r8 │ │ - stc2l 15, cr15, [r0, #52]! @ 0x34 │ │ + stc2l 15, cr15, [r0, #232]! @ 0xe8 │ │ strdeq ip, [r5, r0] │ │ stc2l 15, cr9, [r2, #508]! @ 0x1fc │ │ - stc2l 4, cr12, [r0, #952]! @ 0x3b8 │ │ - stc2l 2, cr10, [r0, #156]! @ 0x9c │ │ - stc2l 4, cr12, [r0, #776]! @ 0x308 │ │ + stc2l 5, cr12, [r0, #108]! @ 0x6c │ │ + stc2l 2, cr10, [r0, #336]! @ 0x150 │ │ + stc2l 4, cr12, [r0, #956]! @ 0x3bc │ │ eorseq r7, r3, ip, ror #10 │ │ - stc2l 14, cr15, [r0, #580]! @ 0x244 │ │ + stc2l 14, cr15, [r0, #760]! @ 0x2f8 │ │ ldr r0, [pc, #4008] @ 2414f20 │ │ mov r1, r4 │ │ ldr r2, [pc, #4004] @ 2414f24 │ │ movw r3, #7094 @ 0x1bb6 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1257133,23 +1257133,23 @@ │ │ stc2l 7, cr4, [r0, #456]! @ 0x1c8 │ │ ldr r1, [pc, #3800] @ 2414f58 │ │ mov r0, r8 │ │ ldr r2, [pc, #3796] @ 2414f5c │ │ add r1, pc, r1 │ │ add r2, pc, r2 │ │ b 2413358 │ │ - stc2l 12, cr1, [r2, #528]! @ 0x210 │ │ + stc2l 12, cr1, [r2, #708]! @ 0x2c4 │ │ orreq ip, r5, r4, lsr #12 │ │ stc2l 14, cr5, [r2, #512]! @ 0x200 │ │ - stc2l 4, cr12, [r0, #136]! @ 0x88 │ │ + stc2l 4, cr12, [r0, #316]! @ 0x13c │ │ orrseq lr, r0, r0, asr #14 │ │ - stc2l 13, cr15, [r0, #964]! @ 0x3c4 │ │ + stc2l 14, cr15, [r0, #120]! @ 0x78 │ │ ldrdeq ip, [r5, r4] │ │ stc2l 14, cr9, [r2, #396]! @ 0x18c │ │ - stc2l 3, cr12, [r0, #840]! @ 0x348 │ │ + stc2l 3, cr12, [r0, #1020]! @ 0x3fc │ │ ldr r0, [pc, #3748] @ 2414f60 │ │ movw r3, #4659 @ 0x1233 │ │ ldr r2, [pc, #3744] @ 2414f64 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #3732] @ 2414f68 │ │ @@ -1257181,24 +1257181,24 @@ │ │ movw r3, #4662 @ 0x1236 │ │ ldr r2, [pc, #3652] @ 2414f84 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 241372c │ │ - stc2l 1, cr10, [r0, #44]! @ 0x2c │ │ - stc2l 3, cr12, [r0, #664]! @ 0x298 │ │ + stc2l 1, cr10, [r0, #224]! @ 0xe0 │ │ + stc2l 3, cr12, [r0, #844]! @ 0x34c │ │ ldr r1, [pc, #3624] @ 2414f88 │ │ mov r0, r8 │ │ ldr r2, [pc, #3620] @ 2414f8c │ │ add r1, pc, r1 │ │ add r2, pc, r2 │ │ b 241393c │ │ eorseq r7, r3, r0, asr r4 │ │ - stc2l 13, cr15, [r0, #468]! @ 0x1d4 │ │ + stc2l 13, cr15, [r0, #648]! @ 0x288 │ │ ldr r1, [pc, #3600] @ 2414f90 │ │ mov r0, r8 │ │ ldr r2, [pc, #3596] @ 2414f94 │ │ add r1, pc, r1 │ │ add r2, pc, r2 │ │ b 2413d0c │ │ stc2l 6, cr4, [r0, #344]! @ 0x158 │ │ @@ -1257243,17 +1257243,17 @@ │ │ ldr r6, [pc, #3512] @ 2414fec │ │ ldr r7, [pc, #3512] @ 2414ff0 │ │ ldr sl, [pc, #3512] @ 2414ff4 │ │ add r6, pc, r6 │ │ add r7, pc, r7 │ │ add sl, pc, sl │ │ b 2414278 │ │ - stc2l 3, cr8, [r0, #756]! @ 0x2f4 │ │ - stc2l 15, cr13, [r1, #40]! @ 0x28 │ │ - stc2l 12, cr15, [r0, #468]! @ 0x1d4 │ │ + stc2l 3, cr8, [r0, #936]! @ 0x3a8 │ │ + stc2l 15, cr13, [r1, #220]! @ 0xdc │ │ + stc2l 12, cr15, [r0, #648]! @ 0x288 │ │ ldr r4, [pc, #3860] @ 2415170 │ │ ldr r1, [pc, #3860] @ 2415174 │ │ add r4, pc, r4 │ │ add r1, pc, r1 │ │ mov r0, r4 │ │ bl 270e120 │ │ cmp r0, #0 │ │ @@ -1257261,15 +1257261,15 @@ │ │ ble 2414b14 │ │ mov r1, #1 │ │ mov r5, #1 │ │ str r1, [r8] │ │ ldr r4, [pc, #3436] @ 2414ff8 │ │ add r4, pc, r4 │ │ b 24142b8 │ │ - stc2l 1, cr14, [r0, #840]! @ 0x348 │ │ + stc2l 1, cr14, [r0, #1020]! @ 0x3fc │ │ @ instruction: 0x01874b98 │ │ orreq r4, r7, ip, ror lr │ │ strdeq r6, [r7, r0] │ │ ldrdeq r6, [r7, r8] │ │ orreq r8, r6, ip, lsr pc │ │ orreq r4, r7, r8, lsl #22 │ │ orreq r4, r7, ip, ror #27 │ │ @@ -1257349,16 +1257349,16 @@ │ │ str r3, [r1] │ │ bge 24144f8 │ │ ldr r6, [pc, #3136] @ 2415024 │ │ sub r5, r0, #1 │ │ add r6, pc, r6 │ │ b 2414444 │ │ orreq r3, r7, ip, lsl #21 │ │ - stc2l 7, cr3, [r2, #768]! @ 0x300 │ │ - stc2l 0, cr12, [r0, #792]! @ 0x318 │ │ + stc2l 7, cr3, [r2, #948]! @ 0x3b4 │ │ + stc2l 0, cr12, [r0, #972]! @ 0x3cc │ │ orreq r3, r7, r4, lsr #20 │ │ ldr r0, [pc, #3128] @ 241503c │ │ movw r3, #2282 @ 0x8ea │ │ ldr r2, [pc, #3124] @ 2415040 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1257379,19 +1257379,19 @@ │ │ sub sl, r1, #20 │ │ cmp sl, #2000 @ 0x7d0 │ │ bcs 241447c │ │ lsl r1, r0, #2 │ │ mov r0, sl │ │ b 24144b0 │ │ orreq r4, r7, r0, ror #25 │ │ - stc2l 15, cr9, [r1, #632]! @ 0x278 │ │ - stc2l 0, cr12, [r0, #536]! @ 0x218 │ │ + stc2l 15, cr9, [r1, #812]! @ 0x32c │ │ + stc2l 0, cr12, [r0, #716]! @ 0x2cc │ │ orreq r4, r7, r4, lsl ip │ │ stc2l 11, cr12, [r3, #936]! @ 0x3a8 @ │ │ - stc2l 0, cr12, [r0, #296]! @ 0x128 │ │ + stc2l 0, cr12, [r0, #476]! @ 0x1dc │ │ ldr r0, [pc, #2980] @ 2415028 │ │ mov r1, sl │ │ ldr r2, [pc, #2976] @ 241502c │ │ movw r3, #2282 @ 0x8ea │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1257435,15 +1257435,15 @@ │ │ ldr r6, [pc, #2864] @ 2415064 │ │ add sl, pc, sl │ │ add r8, pc, r8 │ │ str r4, [r2, r1, lsl #2] │ │ add r6, pc, r6 │ │ b 2414664 │ │ orreq r4, r7, ip, ror #22 │ │ - stc2l 6, cr1, [r2, #556]! @ 0x22c │ │ + stc2l 6, cr1, [r2, #736]! @ 0x2e0 │ │ ldr r0, [pc, #2836] @ 2415068 │ │ movw r3, #2286 @ 0x8ee │ │ ldr r2, [pc, #2832] @ 241506c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r0, [r6, r0, lsl #2] │ │ @@ -1257463,23 +1257463,23 @@ │ │ add sl, pc, sl │ │ ldr r2, [pc, #2784] @ 2415088 │ │ add r8, pc, r8 │ │ add r6, pc, r6 │ │ add r2, pc, r2 │ │ str r4, [r2, r1, lsl #2] │ │ b 2414664 │ │ - stc2l 15, cr11, [r0, #328]! @ 0x148 │ │ + stc2l 15, cr11, [r0, #508]! @ 0x1fc │ │ orreq r4, r7, r0, ror #21 │ │ - stc2l 13, cr7, [r1, #736]! @ 0x2e0 │ │ - stc2l 15, cr11, [r0, #72]! @ 0x48 │ │ + stc2l 13, cr7, [r1, #916]! @ 0x394 │ │ + stc2l 15, cr11, [r0, #252]! @ 0xfc │ │ orreq r6, r7, r8, ror #21 │ │ orreq r9, r8, r0, lsr #3 │ │ orreq pc, r7, ip, lsl #22 │ │ stc2l 9, cr1, [r0, #442]! @ 0x1ba @ │ │ - stc2l 14, cr11, [r0, #728]! @ 0x2d8 │ │ + stc2l 14, cr11, [r0, #908]! @ 0x38c │ │ orreq r3, r7, r0, lsl r8 │ │ orreq r1, sl, r0, asr #22 │ │ stc2l 2, cr1, [r3, #420]! @ 0x1a4 │ │ ldr r0, [pc, #2716] @ 241508c │ │ movw r3, #2286 @ 0x8ee │ │ ldr r2, [pc, #2712] @ 2415090 │ │ add r0, pc, r0 │ │ @@ -1257528,38 +1257528,38 @@ │ │ ldr r7, [pc, #2668] @ 2415114 │ │ ldr sl, [pc, #2668] @ 2415118 │ │ add r6, pc, r6 │ │ add r7, pc, r7 │ │ add sl, pc, sl │ │ b 241491c │ │ vcmla.f16 , q9, , #270 │ │ - stc2l 14, cr11, [r0, #216]! @ 0xd8 │ │ + stc2l 14, cr11, [r0, #396]! @ 0x18c │ │ orrseq r1, r1, r0, ror #31 │ │ strdeq fp, [r5, r8] │ │ orrseq r2, r1, r8, lsl #15 │ │ orrseq r2, r1, r8, asr #30 │ │ orrseq r3, r1, r4, lsl #14 │ │ orreq fp, r5, r0, lsr #31 │ │ stc2l 9, cr12, [r3, #146]! @ 0x92 @ │ │ - stc2l 13, cr11, [r0, #648]! @ 0x288 │ │ + stc2l 13, cr11, [r0, #828]! @ 0x33c │ │ orrseq r3, r1, r8, lsl #29 │ │ stc2l 15, cr2, [r3, #740]! @ 0x2e4 │ │ - stc2l 5, cr1, [r2, #464]! @ 0x1d0 │ │ + stc2l 5, cr1, [r2, #644]! @ 0x284 │ │ orreq fp, r5, r4, lsl pc │ │ stc2l 7, cr5, [r2, #448]! @ 0x1c0 │ │ - stc2l 13, cr11, [r0, #72]! @ 0x48 │ │ + stc2l 13, cr11, [r0, #252]! @ 0xfc │ │ orrseq lr, r0, r0, lsr r0 │ │ - stc2l 6, cr15, [r0, #900]! @ 0x384 │ │ + stc2l 7, cr15, [r0, #56]! @ 0x38 │ │ orreq fp, r5, r4, asr #29 │ │ stc2l 7, cr9, [r2, #332]! @ 0x14c │ │ - stc2l 12, cr11, [r0, #776]! @ 0x308 │ │ - stc2l 9, cr9, [r0, #502]! @ 0x1f6 @ │ │ - stc2l 12, cr11, [r0, #600]! @ 0x258 │ │ + stc2l 12, cr11, [r0, #956]! @ 0x3bc │ │ + stc2l 10, cr9, [r0, #160]! @ 0xa0 @ │ │ + stc2l 12, cr11, [r0, #780]! @ 0x30c │ │ eorseq r6, r3, r0, asr #26 │ │ - stc2l 6, cr15, [r0, #404]! @ 0x194 │ │ + stc2l 6, cr15, [r0, #584]! @ 0x248 │ │ stc2l 15, cr3, [r0, #280]! @ 0x118 │ │ mov r0, r6 │ │ mov r1, r4 │ │ bl 270e120 │ │ cmp r0, #0 │ │ str r0, [r6] │ │ ble 2414684 │ │ @@ -1257746,40 +1257746,40 @@ │ │ ldr r9, [pc, #1876] @ 2415164 │ │ ldr r8, [pc, #1876] @ 2415168 │ │ ldr r7, [pc, #1876] @ 241516c │ │ add r9, pc, r9 │ │ add r8, pc, r8 │ │ add r7, pc, r7 │ │ b 241426c │ │ - stc2l 1, cr3, [r2, #832]! @ 0x340 │ │ - stc2l 10, cr11, [r0, #856]! @ 0x358 @ │ │ + stc2l 1, cr3, [r2, #1012]! @ 0x3f4 │ │ + stc2l 11, cr11, [r0, #12]! @ │ │ orreq r3, r7, r4, lsr r4 │ │ strdeq r4, [r7, r0] │ │ - stc2l 9, cr9, [r1, #348]! @ 0x15c @ │ │ - stc2l 10, cr11, [r0, #600]! @ 0x258 @ │ │ + stc2l 9, cr9, [r1, #438]! @ 0x1b6 @ │ │ + stc2l 10, cr11, [r0, #780]! @ 0x30c @ │ │ orreq r4, r7, r4, lsr #12 │ │ stc2l 5, cr12, [r3, #1000]! @ 0x3e8 │ │ - stc2l 10, cr11, [r0, #360]! @ 0x168 @ │ │ + stc2l 10, cr11, [r0, #540]! @ 0x21c @ │ │ orreq sp, r8, r8, lsl fp │ │ orreq r6, r7, r4, lsr #12 │ │ orreq r6, r7, r4, lsr #12 │ │ orreq fp, r5, r0, lsl #24 │ │ orreq sp, r8, r4, lsl #28 │ │ ldrdeq r6, [r7, r8] │ │ orreq r4, r7, ip, ror r5 │ │ - stc2l 0, cr1, [r2, #684]! @ 0x2ac │ │ - stc2l 9, cr11, [r0, #228]! @ 0xe4 @ │ │ + stc2l 0, cr1, [r2, #864]! @ 0x360 │ │ + stc2l 9, cr11, [r0, #318]! @ 0x13e @ │ │ orreq r4, r7, r0, lsl #10 │ │ - stc2l 7, cr7, [r1, #864]! @ 0x360 │ │ - stc2l 9, cr11, [r0, #100]! @ 0x64 @ │ │ + vcmla.f16 d23, d1, d5, #270 │ │ + stc2l 9, cr11, [r0, #190]! @ 0xbe @ │ │ orreq r6, r7, r8, lsl #10 │ │ orreq r8, r8, r4, asr #23 │ │ orreq pc, r7, r8, lsr #10 │ │ stc2l 3, cr1, [r0, #1012]! @ 0x3f4 │ │ - stc2l 8, cr11, [r0, #856]! @ 0x358 │ │ + stc2l 9, cr11, [r0, #6]! @ │ │ orreq r1, sl, r8, ror #10 │ │ orreq r3, r7, r4, lsr #4 │ │ ldr r0, [pc, #1288] @ 2414fa4 │ │ ldr r1, [pc, #1288] @ 2414fa8 │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ bl 270e110 │ │ @@ -1257992,36 +1257992,36 @@ │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ bl 270db00 │ │ ldr r0, [pc, #1004] @ 24151e0 │ │ mov r1, #20 │ │ add r0, pc, r0 │ │ b 2414d7c │ │ - stc2l 14, cr2, [r2, #16]! │ │ - stc2l 7, cr11, [r0, #40]! @ 0x28 │ │ + stc2l 14, cr2, [r2, #196]! @ 0xc4 │ │ + stc2l 7, cr11, [r0, #220]! @ 0xdc │ │ orreq r3, r7, r8, rrx │ │ orreq r4, r7, r4, lsr #6 │ │ - stc2l 5, cr9, [r1, #904]! @ 0x388 │ │ + stc2l 6, cr9, [r1, #60]! @ 0x3c │ │ ldr r0, [pc, #980] @ 24151ec │ │ mov r1, #100 @ 0x64 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #968] @ 24151f0 │ │ mov r2, #1 │ │ ldr r1, [fp, #32] │ │ add r0, pc, r0 │ │ bl 270daf0 │ │ ldr r0, [pc, #952] @ 24151f4 │ │ mov r1, #23 │ │ add r0, pc, r0 │ │ b 2414d7c │ │ - stc2l 6, cr11, [r0, #808]! @ 0x328 │ │ + stc2l 6, cr11, [r0, #988]! @ 0x3dc │ │ orreq r4, r7, r8, asr r2 │ │ stc2l 2, cr12, [r3, #184]! @ 0xb8 │ │ - stc2l 6, cr11, [r0, #568]! @ 0x238 │ │ + stc2l 6, cr11, [r0, #748]! @ 0x2ec │ │ ldr r0, [pc, #932] @ 2415200 │ │ mov r1, #116 @ 0x74 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #920] @ 2415204 │ │ mov r2, #1 │ │ ldr r1, [fp, #32] │ │ @@ -1258065,40 +1258065,40 @@ │ │ mov r2, #1 │ │ add r1, pc, r1 │ │ bl 270db00 │ │ ldr r0, [pc, #784] @ 2415228 │ │ mov r1, #22 │ │ add r0, pc, r0 │ │ b 2414d7c │ │ - stc2l 12, cr0, [r2, #796]! @ 0x31c │ │ - stc2l 5, cr11, [r0, #568]! @ 0x238 │ │ + stc2l 12, cr0, [r2, #976]! @ 0x3d0 │ │ + stc2l 5, cr11, [r0, #748]! @ 0x2ec │ │ orreq r4, r7, ip, lsl r1 │ │ - stc2l 3, cr7, [r1, #976]! @ 0x3d0 │ │ - stc2l 5, cr11, [r0, #312]! @ 0x138 │ │ + stc2l 4, cr7, [r1, #132]! @ 0x84 │ │ + stc2l 5, cr11, [r0, #492]! @ 0x1ec │ │ orreq r6, r7, r0, lsr #2 │ │ ldrdeq r8, [r8, r8] │ │ orreq pc, r7, r4, asr #2 │ │ stc2l 0, cr1, [r0, #84]! @ 0x54 │ │ - stc2l 4, cr11, [r0, #952]! @ 0x3b8 │ │ + stc2l 5, cr11, [r0, #108]! @ 0x6c │ │ orreq r2, r7, r4, asr #28 │ │ orreq r1, sl, r8, ror r1 │ │ orreq sp, r7, r4, lsr #3 │ │ stc2l 10, cr14, [r2, #368]! @ 0x170 @ │ │ ldrdeq r3, [r7, r4] │ │ strheq r4, [r7, r8] │ │ stc2l 7, cr5, [r0, #748]! @ 0x2ec │ │ - stc2l 4, cr11, [r0, #312]! @ 0x138 │ │ + stc2l 4, cr11, [r0, #492]! @ 0x1ec │ │ orrseq r1, r1, r8, asr #27 │ │ orreq fp, r5, r0, lsl r6 │ │ stc2l 14, cr4, [r2, #460]! @ 0x1cc │ │ - stc2l 4, cr11, [r0, #56]! @ 0x38 │ │ + stc2l 4, cr11, [r0, #236]! @ 0xec │ │ orrseq r2, r1, r8, asr r5 │ │ ldrdeq fp, [r5, r0] │ │ - stc2l 14, cr14, [r0, #372]! @ 0x174 │ │ - stc2l 3, cr11, [r0, #840]! @ 0x348 │ │ + stc2l 14, cr14, [r0, #552]! @ 0x228 │ │ + stc2l 3, cr11, [r0, #1020]! @ 0x3fc │ │ strdeq r3, [r7, r4] │ │ ldrdeq r3, [r7, r8] │ │ ldrdeq r3, [r7, r4] │ │ @ instruction: 0x01873fb8 │ │ orreq r7, r6, r8, ror #1 │ │ orreq r3, r8, ip, ror #25 │ │ orreq r4, r5, ip, ror #30 │ │ @@ -1258117,159 +1258117,159 @@ │ │ orreq r7, r6, r0, asr #1 │ │ orreq r3, r8, r4, asr #25 │ │ orreq r4, r5, r8, asr #30 │ │ orreq r3, r7, r0, asr #30 │ │ orreq r5, r8, r8, ror #28 │ │ ldrdeq r5, [r7, r4] │ │ orreq r5, r7, r8, lsr #29 │ │ - stc2l 1, cr9, [r1, #848]! @ 0x350 │ │ - stc2l 2, cr11, [r0, #840]! @ 0x348 │ │ + stc2l 2, cr9, [r1, #4]! │ │ + stc2l 2, cr11, [r0, #1020]! @ 0x3fc │ │ stc2l 13, cr6, [r2, #920]! @ 0x398 │ │ orreq r7, r8, ip, ror #25 │ │ orreq r3, r7, r4, asr lr │ │ strdeq r5, [r7, r0] │ │ orreq r3, r7, ip, lsl lr │ │ @ instruction: 0x01875dbc │ │ orreq r3, r7, r8, asr #27 │ │ orreq r3, r7, r0, lsr #27 │ │ orreq r7, r8, r0, lsl ip │ │ orreq r5, r7, r4, lsr sp │ │ orreq r5, r7, r0, lsr sp │ │ orreq r5, r7, ip, lsl sp │ │ - stc2l 15, cr8, [r1, #528]! @ 0x210 │ │ - stc2l 0, cr11, [r0, #520]! @ 0x208 │ │ + stc2l 15, cr8, [r1, #708]! @ 0x2c4 │ │ + stc2l 0, cr11, [r0, #700]! @ 0x2bc │ │ @ instruction: 0x01873cb4 │ │ orreq r5, r7, r8, asr ip │ │ orreq r5, r8, ip, asr #23 │ │ - stc2l 0, cr9, [r1, #32]! │ │ - stc2l 1, cr11, [r0, #24]! │ │ + stc2l 0, cr9, [r1, #212]! @ 0xd4 │ │ + stc2l 1, cr11, [r0, #204]! @ 0xcc │ │ orreq r5, r7, r4, ror #25 │ │ orreq r3, r7, ip, lsr #26 │ │ orreq r5, r8, r8, asr ip │ │ ldrdeq r7, [r8, r4] │ │ orreq r5, r8, r8, ror #22 │ │ @ instruction: 0x01883db0 │ │ orreq lr, r7, r8, lsl #24 │ │ orreq r5, r7, r4, asr #23 │ │ @ instruction: 0x0185b1bc │ │ stc2l 11, cr6, [r2, #88]! @ 0x58 @ │ │ - stc2l 15, cr10, [r0, #728]! @ 0x2d8 │ │ + stc2l 15, cr10, [r0, #908]! @ 0x38c │ │ orreq r3, r7, r0, ror #23 │ │ strdeq r5, [r8, ip] │ │ orreq r3, r8, r4, asr #26 │ │ @ instruction: 0x0187eb9c │ │ orreq r5, r7, r4, asr fp │ │ orreq fp, r5, r0, asr r1 │ │ orreq r7, r8, ip, lsl sl │ │ stc2l 10, cr6, [r2, #488]! @ 0x1e8 @ │ │ - stc2l 15, cr10, [r0, #104]! @ 0x68 │ │ + stc2l 15, cr10, [r0, #284]! @ 0x11c │ │ orreq r7, r8, r4, asr #19 │ │ orreq r3, r7, r0, asr #22 │ │ - stc2l 14, cr10, [r0, #952]! @ 0x3b8 │ │ - stc2l 14, cr10, [r0, #904]! @ 0x388 │ │ + stc2l 15, cr10, [r0, #108]! @ 0x6c │ │ + stc2l 15, cr10, [r0, #60]! @ 0x3c │ │ orreq r5, r8, r0, asr #20 │ │ orreq r3, r8, r8, lsl #25 │ │ orreq lr, r7, r0, ror #21 │ │ @ instruction: 0x01875a9c │ │ @ instruction: 0x0185b098 │ │ @ instruction: 0x0188d29c │ │ ldrdeq r7, [r8, ip] │ │ - stc2l 4, cr0, [r2, #988]! @ 0x3dc │ │ - stc2l 13, cr10, [r0, #760]! @ 0x2f8 │ │ + stc2l 5, cr0, [r2, #144]! @ 0x90 │ │ + stc2l 13, cr10, [r0, #940]! @ 0x3ac │ │ orreq sl, r5, r0, lsl #31 │ │ stc2l 9, cr11, [r3, #52]! @ 0x34 @ │ │ - stc2l 13, cr10, [r0, #488]! @ 0x1e8 │ │ + stc2l 13, cr10, [r0, #668]! @ 0x29c │ │ orreq ip, r8, r0, asr #28 │ │ orreq r5, r7, ip, asr #18 │ │ orreq r5, r7, ip, lsr #18 │ │ orreq r3, r7, r4, ror #18 │ │ strdeq sl, [r5, ip] │ │ - stc2l 13, cr10, [r0, #40]! @ 0x28 │ │ - stc2l 12, cr10, [r0, #1016]! @ 0x3f8 │ │ + stc2l 13, cr10, [r0, #220]! @ 0xdc │ │ + stc2l 13, cr10, [r0, #172]! @ 0xac │ │ orreq r7, r8, ip, lsr #18 │ │ orreq r3, r7, r8, lsl #18 │ │ - stc2l 12, cr10, [r0, #728]! @ 0x2d8 │ │ - stc2l 12, cr10, [r0, #680]! @ 0x2a8 │ │ + stc2l 12, cr10, [r0, #908]! @ 0x38c │ │ + stc2l 12, cr10, [r0, #860]! @ 0x35c │ │ orreq r3, r8, r0, ror #20 │ │ @ instruction: 0x018738b4 │ │ @ instruction: 0x0187389c │ │ orreq r3, r7, r8, asr #21 │ │ orreq r5, r7, r8, lsr sl │ │ - stc2l 13, cr8, [r1, #400]! @ 0x190 │ │ - stc2l 14, cr10, [r0, #392]! @ 0x188 │ │ - stc2l 12, cr10, [r0, #136]! @ 0x88 │ │ - stc2l 12, cr10, [r0, #88]! @ 0x58 │ │ + stc2l 13, cr8, [r1, #580]! @ 0x244 │ │ + stc2l 14, cr10, [r0, #572]! @ 0x23c │ │ + stc2l 12, cr10, [r0, #316]! @ 0x13c │ │ + stc2l 12, cr10, [r0, #268]! @ 0x10c │ │ orreq r5, r7, ip, asr #15 │ │ - stc2l 10, cr8, [r1, #992]! @ 0x3e0 @ │ │ + stc2l 11, cr8, [r1, #148]! @ 0x94 @ │ │ orreq r3, r7, r4, lsr #16 │ │ - stc2l 10, cr10, [r1, #552]! @ 0x228 @ │ │ + stc2l 10, cr10, [r1, #732]! @ 0x2dc @ │ │ @ instruction: 0x0188559c │ │ @ instruction: 0x01875798 │ │ @ instruction: 0x0190bef8 │ │ orreq r5, r7, r0, ror r7 │ │ orreq r4, r5, r4, lsr #15 │ │ orreq r3, r7, r0, lsr #15 │ │ @ instruction: 0x01873794 │ │ orreq r3, r8, r8, asr #11 │ │ orreq r4, r5, r8, ror r7 │ │ orreq r3, r7, ip, ror #14 │ │ @ instruction: 0x01883594 │ │ orreq r3, r7, r8, asr #14 │ │ orreq r5, r8, r4, ror r6 │ │ orreq r5, r7, r0, ror #13 │ │ - stc2l 9, cr8, [r1, #488]! @ 0x1e8 @ │ │ + stc2l 10, cr8, [r1, #132]! @ 0x84 @ │ │ strdeq r3, [r7, r4] │ │ orreq r3, r8, r8, lsr #26 │ │ orrseq r7, r1, r4, ror r7 │ │ - stc2l 10, cr2, [r1, #724]! @ 0x2d4 @ │ │ - stc2l 5, cr8, [r0, #436]! @ 0x1b4 │ │ - stc2l 2, cr14, [r0, #532]! @ 0x214 │ │ - stc2l 5, cr8, [r0, #688]! @ 0x2b0 │ │ + stc2l 10, cr2, [r1, #904]! @ 0x388 @ │ │ + stc2l 5, cr8, [r0, #616]! @ 0x268 │ │ + stc2l 2, cr14, [r0, #712]! @ 0x2c8 │ │ + stc2l 5, cr8, [r0, #868]! @ 0x364 │ │ orrseq r7, r1, r0, asr r7 │ │ - stc2l 1, cr0, [r2, #460]! @ 0x1cc │ │ - stc2l 9, cr6, [r0, #32]! @ │ │ - stc2l 2, cr14, [r0, #308]! @ 0x134 │ │ + stc2l 1, cr0, [r2, #640]! @ 0x280 │ │ + stc2l 9, cr6, [r0, #122]! @ 0x7a @ │ │ + stc2l 2, cr14, [r0, #488]! @ 0x1e8 │ │ strdeq r3, [r7, r0] │ │ orrseq r7, r1, r0, ror #11 │ │ stc2l 13, cr13, [r2, #140]! @ 0x8c │ │ orrseq r7, r1, ip, lsr #14 │ │ stc2l 15, cr13, [r2, #28]! │ │ stc2l 3, cr0, [r0, #256]! @ 0x100 │ │ - stc2l 1, cr14, [r0, #964]! @ 0x3c4 │ │ + stc2l 2, cr14, [r0, #120]! @ 0x78 │ │ ldrdeq pc, [r7, r0] │ │ orreq r3, r7, r8, ror r3 │ │ @ instruction: 0x018806b0 │ │ orrseq r7, r1, r8, lsl #14 │ │ stc2l 5, cr11, [r3, #160]! @ 0xa0 │ │ stc2l 7, cr9, [r3, #152]! @ 0x98 │ │ - stc2l 1, cr14, [r0, #324]! @ 0x144 │ │ + stc2l 1, cr14, [r0, #504]! @ 0x1f8 │ │ orrseq r6, r1, ip, asr #30 │ │ stc2l 2, cr10, [r2, #1012]! @ 0x3f4 │ │ ldrdeq r3, [r7, r0] │ │ stc2l 12, cr13, [r2, #764]! @ 0x2fc │ │ orrseq r7, r1, r4, ror #13 │ │ ldc2l 3, cr14, [pc, #68] @ 2415234 │ │ stc2l 10, cr15, [r2, #364]! @ 0x16c @ │ │ - stc2l 0, cr14, [r0, #852]! @ 0x354 │ │ - stc2l 13, cr1, [r2, #104]! @ 0x68 │ │ + stc2l 1, cr14, [r0, #8]! │ │ + stc2l 13, cr1, [r2, #284]! @ 0x11c │ │ orrseq r7, r1, r0, asr #13 │ │ - stc2l 1, cr0, [r2, #4]! │ │ - stc2l 7, cr2, [r1, #604]! @ 0x25c │ │ - stc2l 0, cr14, [r0, #580]! @ 0x244 │ │ - stc2l 3, cr8, [r0, #828]! @ 0x33c │ │ + stc2l 1, cr0, [r2, #184]! @ 0xb8 │ │ + stc2l 7, cr2, [r1, #784]! @ 0x310 │ │ + stc2l 0, cr14, [r0, #760]! @ 0x2f8 │ │ + stc2l 3, cr8, [r0, #1008]! @ 0x3f0 │ │ @ instruction: 0x0191769c │ │ - stc2l 8, cr8, [r1, #92]! @ 0x5c │ │ - stc2l 12, cr1, [r2, #776]! @ 0x308 │ │ - stc2l 0, cr14, [r0, #260]! @ 0x104 │ │ + vcmla.f16 q12, , q2, #270 │ │ + stc2l 12, cr1, [r2, #956]! @ 0x3bc │ │ + stc2l 0, cr14, [r0, #440]! @ 0x1b8 │ │ orrseq r6, r1, ip, lsr lr │ │ orrseq r7, r1, r4, asr r4 │ │ orreq r3, r7, ip, lsr #3 │ │ stc2l 7, cr5, [r3, #36]! @ 0x24 │ │ stc2l 10, cr1, [r3, #608]! @ 0x260 @ │ │ - stc2l 2, cr14, [r0, #852]! @ 0x354 │ │ + stc2l 3, cr14, [r0, #8]! │ │ orrseq r7, r1, r0, asr r6 │ │ stc2l 4, cr10, [r2, #540]! @ 0x21c │ │ │ │ 0241523c : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ bl 270ce80 │ │ @@ -1258287,15 +1258287,15 @@ │ │ add r0, pc, r0 │ │ bl 270da10 │ │ mov r0, r4 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, sl, fp, pc} │ │ - stc2l 13, cr13, [r1, #244]! @ 0xf4 │ │ + stc2l 13, cr13, [r1, #424]! @ 0x1a8 │ │ stc2l 2, cr5, [r3, #344]! @ 0x158 │ │ │ │ 02415298 : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #104 @ 0x68 │ │ mov r3, #0 │ │ @@ -1258788,15 +1258788,15 @@ │ │ ldr r0, [pc, #24] @ 2415a08 │ │ mov r1, #5 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ stc2l 6, cr7, [r2, #28]! │ │ - stc2l 7, cr7, [r0, #392]! @ 0x188 │ │ + stc2l 7, cr7, [r0, #572]! @ 0x23c │ │ stc2l 5, cr7, [r2, #796]! @ 0x31c │ │ │ │ 02415a0c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #148 @ 0x94 │ │ mov r8, r3 │ │ @@ -1259861,16 +1259861,16 @@ │ │ ldr r0, [pc, #3844] @ 24179b0 │ │ add r0, pc, r0 │ │ b 2419f54 │ │ @ instruction: 0x0191bafc │ │ eorseq lr, r3, r4, asr #15 │ │ @ instruction: 0x0191be94 │ │ orrseq sl, r6, ip, lsr #12 │ │ - stc2l 6, cr7, [r0, #248]! @ 0xf8 │ │ - stc2l 10, cr9, [r0, #136]! @ 0x88 @ │ │ + stc2l 6, cr7, [r0, #428]! @ 0x1ac │ │ + stc2l 10, cr9, [r0, #316]! @ 0x13c @ │ │ stc2l 3, cr11, [r2, #364]! @ 0x16c │ │ ldc2l 3, cr13, [pc, #584] @ 2416d1c │ │ orrseq fp, r1, ip, asr #20 │ │ eorseq lr, r3, r4, lsl r7 │ │ orrseq fp, r1, r4, ror #27 │ │ orrseq sl, r6, ip, ror r5 │ │ @ instruction: 0x0196f394 │ │ @@ -1259962,37 +1259962,37 @@ │ │ mov r1, #22 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #3984] @ 2417bdc │ │ add r0, pc, r0 │ │ b 2419f54 │ │ stc2l 11, cr0, [r3, #28]! @ │ │ - stc2l 2, cr13, [r0, #596]! @ 0x254 │ │ - stc2l 10, cr1, [r1, #256]! @ 0x100 @ │ │ + stc2l 2, cr13, [r0, #776]! @ 0x308 │ │ + stc2l 10, cr1, [r1, #436]! @ 0x1b4 @ │ │ stc2l 11, cr3, [r0, #948]! @ 0x3b4 @ │ │ orrseq fp, r1, r4, lsl #18 │ │ eorseq lr, r3, ip, asr #11 │ │ @ instruction: 0x0191bc9c │ │ orrseq sl, r6, r4, lsr r4 │ │ orrseq r5, r2, ip, ror #17 │ │ @ instruction: 0x019258dc │ │ stc2l 3, cr10, [r3, #784]! @ 0x310 │ │ - stc2l 1, cr13, [r0, #820]! @ 0x334 │ │ - stc2l 6, cr3, [r1, #468]! @ 0x1d4 │ │ + stc2l 1, cr13, [r0, #1000]! @ 0x3e8 │ │ + stc2l 6, cr3, [r1, #648]! @ 0x288 │ │ stc2l 11, cr3, [r0, #228]! @ 0xe4 @ │ │ stc2l 3, cr9, [r2, #568]! @ 0x238 │ │ orrseq fp, r1, r8, lsr r8 │ │ eorseq lr, r3, r0, lsl #10 │ │ @ instruction: 0x0191bbd0 │ │ orrseq sl, r6, r8, ror #6 │ │ orrseq fp, r1, r8, lsr #23 │ │ @ instruction: 0x01969ddc │ │ - stc2l 4, cr7, [r0, #616]! @ 0x268 │ │ - stc2l 6, cr7, [r1, #164]! @ 0xa4 │ │ - stc2l 7, cr9, [r0, #136]! @ 0x88 │ │ + stc2l 4, cr7, [r0, #796]! @ 0x31c │ │ + stc2l 6, cr7, [r1, #344]! @ 0x158 │ │ + stc2l 7, cr9, [r0, #316]! @ 0x13c │ │ cmp r0, #0 │ │ bne 2419f5c │ │ ldr r7, [pc, #4016] @ 2417c70 │ │ add r7, pc, r7 │ │ ldrb r0, [r7] │ │ cmp r0, #0 │ │ bne 2416d20 │ │ @@ -1260080,25 +1260080,25 @@ │ │ bl 270db00 │ │ ldr r0, [pc, #4040] @ 2417de4 │ │ mov r1, #22 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ mov r0, r4 │ │ b 2419f54 │ │ - stc2l 6, cr9, [r0, #984]! @ 0x3d8 │ │ + stc2l 7, cr9, [r0, #140]! @ 0x8c │ │ orrseq pc, r6, ip, asr #2 │ │ orrseq pc, r6, r8, lsl r1 @ │ │ - stc2l 2, cr7, [r0, #924]! @ 0x39c │ │ + stc2l 3, cr7, [r0, #80]! @ 0x50 │ │ orrseq sl, r6, ip, lsl #5 │ │ orrseq sl, r6, r4, lsr r2 │ │ orrseq r9, r6, r8, lsr #26 │ │ orrseq sl, r6, r4, asr r2 │ │ ldrsbeq pc, [r6, ip] @ │ │ stc2l 2, cr9, [r2, #104]! @ 0x68 │ │ - stc2l 3, cr7, [r0, #948]! @ 0x3b4 │ │ + stc2l 4, cr7, [r0, #104]! @ 0x68 │ │ orrseq fp, r1, r8, lsr #13 │ │ eorseq lr, r3, r0, ror r3 │ │ orrseq fp, r1, r0, asr #20 │ │ ldr r1, [pc, #3964] @ 2417de8 │ │ ldr r4, [fp, #8] │ │ add r1, pc, r1 │ │ mov r0, r4 │ │ @@ -1260147,15 +1260147,15 @@ │ │ cmp r1, #0 │ │ bne 2417ca8 │ │ cmp r0, #0 │ │ bgt 2416ed0 │ │ b 2417ca8 │ │ @ instruction: 0x0196a1d8 │ │ orrseq sl, r6, r0, asr #3 │ │ - stc2l 3, cr7, [r0, #564]! @ 0x234 │ │ + stc2l 3, cr7, [r0, #744]! @ 0x2e8 │ │ stc2l 1, cr9, [r2, #548]! @ 0x224 │ │ orrseq fp, r1, ip, lsr #12 │ │ ldr r0, [pc, #3964] @ 2417ec8 │ │ mov r1, #292 @ 0x124 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #3952] @ 2417ecc │ │ @@ -1260191,16 +1260191,16 @@ │ │ mov r1, #20 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #4092] @ 2417fdc │ │ add r0, pc, r0 │ │ b 2419f54 │ │ ldc2l 0, cr15, [pc, #1004] @ 24173d8 │ │ - stc2l 15, cr12, [r0, #4]! │ │ - stc2l 13, cr14, [r1, #328]! @ 0x148 │ │ + stc2l 15, cr12, [r0, #184]! @ 0xb8 │ │ + stc2l 13, cr14, [r1, #508]! @ 0x1fc │ │ stc2l 0, cr9, [r2, #900]! @ 0x384 │ │ stc2l 6, cr4, [r3, #56]! @ 0x38 │ │ orrseq fp, r1, r8, ror #10 │ │ eorseq lr, r3, r0, lsr r2 │ │ orrseq fp, r1, r0, lsl #18 │ │ @ instruction: 0x0196a098 │ │ stc2l 13, cr0, [r0, #732]! @ 0x2dc │ │ @@ -1260309,18 +1260309,18 @@ │ │ cmp r1, r5 │ │ bhi 2419368 │ │ ldr r2, [pc, #3932] @ 2418110 │ │ add r2, pc, r2 │ │ str r4, [r2, r1, lsl #2] │ │ b 24193a0 │ │ stc2l 2, cr8, [r3, #232]! @ 0xe8 │ │ - stc2l 3, cr9, [r0, #360]! @ 0x168 │ │ + stc2l 3, cr9, [r0, #540]! @ 0x21c │ │ orrseq lr, r6, r8, lsl #27 │ │ orrseq lr, r6, r4, asr sp │ │ - stc2l 15, cr6, [r0, #140]! @ 0x8c │ │ + stc2l 15, cr6, [r0, #320]! @ 0x140 │ │ orrseq r9, r6, ip, asr #29 │ │ ldr r0, [pc, #3896] @ 2418114 │ │ mov r1, #59 @ 0x3b │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #3884] @ 2418118 │ │ mov r2, #1 │ │ @@ -1260409,26 +1260409,26 @@ │ │ ldr r0, [r4, r1, lsl #2] │ │ sub r5, r0, #1 │ │ str r5, [r4, r1, lsl #2] │ │ b 2417c30 │ │ stc2l 10, cr0, [r0, #1004]! @ 0x3ec @ │ │ @ instruction: 0x0191b5f8 │ │ stc2l 0, cr8, [r3, #504]! @ 0x1f8 │ │ - stc2l 1, cr9, [r0, #632]! @ 0x278 │ │ + stc2l 1, cr9, [r0, #812]! @ 0x32c │ │ orrseq lr, r6, ip, asr #23 │ │ @ instruction: 0x0196eb98 │ │ - stc2l 13, cr6, [r0, #380]! @ 0x17c │ │ + stc2l 13, cr6, [r0, #560]! @ 0x230 │ │ orrseq r9, r6, r4, lsl #26 │ │ orrseq r9, r6, ip, lsr #25 │ │ @ instruction: 0x01969cd0 │ │ stc2l 6, cr12, [r2, #656]! @ 0x290 │ │ orrseq lr, r6, r0, lsl fp │ │ orrseq lr, r6, r8, lsr fp │ │ stc2l 6, cr12, [r2, #324]! @ 0x144 │ │ - stc2l 15, cr2, [r1, #120]! @ 0x78 │ │ + stc2l 15, cr2, [r1, #300]! @ 0x12c │ │ orrseq fp, r1, ip, lsl #2 │ │ ldrsbteq sp, [r3], -r4 │ │ orrseq fp, r1, r4, lsr #9 │ │ orrseq r9, r6, ip, lsr ip │ │ orrseq lr, r6, r4, asr sl │ │ ldrsheq r5, [r2, r0] │ │ ldrheq fp, [r1, r8] │ │ @@ -1260541,25 +1260541,25 @@ │ │ ldr r5, [pc, #4004] @ 24184f0 │ │ ldr r6, [pc, #4004] @ 24184f4 │ │ add r5, pc, r5 │ │ add r6, pc, r6 │ │ b 24175ec │ │ orrseq r5, r2, ip, rrx │ │ ldc2l 9, cr14, [pc, #342] @ 24176ba @ │ │ - stc2l 9, cr12, [r0, #162]! @ 0xa2 @ │ │ - stc2l 0, cr15, [r0, #684]! @ 0x2ac │ │ - stc2l 13, cr2, [r1, #920]! @ 0x398 │ │ + stc2l 9, cr12, [r0, #252]! @ 0xfc @ │ │ + stc2l 0, cr15, [r0, #864]! @ 0x360 │ │ + stc2l 14, cr2, [r1, #76]! @ 0x4c │ │ ldc2l 10, cr14, [pc, #912] @ 2417904 @ │ │ @ instruction: 0x0191afb8 │ │ eorseq sp, r3, r0, lsl #25 │ │ orrseq fp, r1, r0, asr r3 │ │ orrseq r9, r6, r8, ror #21 │ │ orrseq fp, r1, r8, lsr #6 │ │ stc2l 9, cr4, [r2, #106]! @ 0x6a @ │ │ - stc2l 14, cr8, [r0, #808]! @ 0x328 │ │ + stc2l 14, cr8, [r0, #988]! @ 0x3dc │ │ orrseq lr, r6, r0, asr #17 │ │ orrseq r9, r6, r0, ror #20 │ │ orrseq r9, r6, r4, lsl sl │ │ orrseq r9, r6, r8, lsl #20 │ │ @ instruction: 0x019694f4 │ │ @ instruction: 0x0196e898 │ │ orrseq fp, r1, ip, ror r2 │ │ @@ -1260759,15 +1260759,15 @@ │ │ ldr r0, [pc, #4044] @ 2418880 │ │ add r0, pc, r0 │ │ mov r1, #20 │ │ bl 270da10 │ │ ldr r0, [pc, #4032] @ 2418884 │ │ add r0, pc, r0 │ │ b 2419f54 │ │ - stc2l 8, cr6, [r0, #328]! @ 0x148 │ │ + stc2l 8, cr6, [r0, #508]! @ 0x1fc │ │ orrseq lr, r6, ip, asr r6 │ │ stc2l 6, cr4, [r2, #516]! @ 0x204 │ │ stc2l 7, cr9, [r3, #196]! @ 0xc4 │ │ ldr r0, [pc, #4008] @ 2418888 │ │ mov r1, #59 @ 0x3b │ │ add r0, pc, r0 │ │ bl 270da00 │ │ @@ -1260786,17 +1260786,17 @@ │ │ ldr r0, [pc, #3956] @ 2418894 │ │ mov r1, #16 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #3944] @ 2418898 │ │ add r0, pc, r0 │ │ b 2419f54 │ │ - stc2l 5, cr12, [r0, #756]! @ 0x2f4 │ │ - stc2l 11, cr14, [r0, #172]! @ 0xac @ │ │ - stc2l 10, cr8, [r1, #640]! @ 0x280 @ │ │ + stc2l 5, cr12, [r0, #936]! @ 0x3a8 │ │ + stc2l 11, cr14, [r0, #352]! @ 0x160 @ │ │ + stc2l 10, cr8, [r1, #820]! @ 0x334 @ │ │ ldr r0, [pc, #3924] @ 241889c │ │ mov r1, #45 @ 0x2d │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #3912] @ 24188a0 │ │ mov r1, r4 │ │ mov r2, #1 │ │ @@ -1260814,19 +1260814,19 @@ │ │ orrseq r4, r2, r4, lsl ip │ │ @ instruction: 0x0191abdc │ │ @ instruction: 0x01915d94 │ │ orrseq sl, r1, r0, ror #30 │ │ stc2l 11, cr3, [r3, #212]! @ 0xd4 @ │ │ ldc2l 4, cr12, [pc, #860] @ 2417d00 │ │ @ instruction: 0x01924b90 │ │ - stc2l 10, cr8, [r0, #772]! @ 0x304 @ │ │ - stc2l 4, cr12, [r0, #468]! @ 0x1d4 │ │ - stc2l 11, cr14, [r0, #828]! @ 0x33c @ │ │ - stc2l 9, cr8, [r1, #208]! @ 0xd0 @ │ │ - stc2l 9, cr6, [r1, #74]! @ 0x4a @ │ │ + stc2l 10, cr8, [r0, #952]! @ 0x3b8 @ │ │ + stc2l 4, cr12, [r0, #648]! @ 0x288 │ │ + stc2l 11, cr14, [r0, #1008]! @ 0x3f0 @ │ │ + stc2l 9, cr8, [r1, #298]! @ 0x12a @ │ │ + stc2l 9, cr6, [r1, #164]! @ 0xa4 @ │ │ @ instruction: 0x0191aa90 │ │ eorseq sp, r3, r8, asr r7 │ │ orrseq sl, r1, r8, lsr #28 │ │ orrseq r9, r6, r0, asr #11 │ │ @ instruction: 0x0196e3d8 │ │ orrseq r4, r2, r4, ror sl │ │ orrseq sl, r1, ip, lsr sl │ │ @@ -1260953,18 +1260953,18 @@ │ │ bhi 241a0f0 │ │ str r4, [sl, r1, lsl #2] │ │ lsl r0, r0, #1 │ │ sub r1, r0, #13 │ │ ldr r4, [r5] │ │ b 241a138 │ │ @ instruction: 0x019249f0 │ │ - stc2l 9, cr8, [r0, #66]! @ 0x42 @ │ │ - stc2l 2, cr12, [r0, #852]! @ 0x354 │ │ - stc2l 10, cr14, [r0, #188]! @ 0xbc @ │ │ - stc2l 7, cr6, [r1, #948]! @ 0x3b4 │ │ + stc2l 9, cr8, [r0, #156]! @ 0x9c @ │ │ + stc2l 3, cr12, [r0, #8]! │ │ + stc2l 10, cr14, [r0, #368]! @ 0x170 @ │ │ + stc2l 8, cr6, [r1, #104]! @ 0x68 │ │ ldr r0, [pc, #3776] @ 2418aa8 │ │ movw r3, #4586 @ 0x11ea │ │ ldr r2, [pc, #3772] @ 2418aac │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r5, [r4, r0, lsl #2] │ │ @@ -1260994,15 +1260994,15 @@ │ │ bl 270db90 │ │ cmp r0, #0 │ │ beq 2418cd4 │ │ ldr r0, [pc, #3672] @ 2418ac4 │ │ add r0, pc, r0 │ │ b 2419f54 │ │ @ instruction: 0x0191a8f0 │ │ - stc2l 6, cr6, [r0, #40]! @ 0x28 │ │ + stc2l 6, cr6, [r0, #220]! @ 0xdc │ │ eorseq sp, r3, r4, lsr #11 │ │ orrseq sl, r1, r4, ror ip │ │ orrseq r9, r6, ip, lsl #8 │ │ orrseq lr, r6, r4, lsl r2 │ │ @ instruction: 0x019248b0 │ │ orrseq sl, r1, r8, ror r8 │ │ orrseq r5, r1, r0, lsr sl │ │ @@ -1261083,18 +1261083,18 @@ │ │ cmp r1, r5 │ │ bhi 2418084 │ │ ldr r0, [pc, #4072] @ 2418db4 │ │ add r0, pc, r0 │ │ ldr r0, [r0, r1, lsl #2] │ │ add r4, r0, #1 │ │ b 24180c0 │ │ - stc2l 4, cr6, [r0, #1000]! @ 0x3e8 │ │ + stc2l 5, cr6, [r0, #156]! @ 0x9c │ │ ldc2l 1, cr14, [pc, #316] @ 2417f20 │ │ - stc2l 0, cr12, [r0, #980]! @ 0x3d4 │ │ - vcmla.f16 q15, q0, , #270 │ │ + stc2l 1, cr12, [r0, #136]! @ 0x88 │ │ + stc2l 8, cr14, [r0, #496]! @ 0x1f0 │ │ orrseq r9, r6, r0, lsr #5 │ │ ldrheq lr, [r6, r4] │ │ orrseq r4, r2, r0, asr r7 │ │ orrseq sl, r1, r8, lsl r7 │ │ @ instruction: 0x019158d0 │ │ ldr r0, [pc, #4020] @ 2418db8 │ │ movw r3, #2295 @ 0x8f7 │ │ @@ -1261143,18 +1261143,18 @@ │ │ ldr r4, [pc, #3976] @ 2418e3c │ │ ldr r4, [pc, r4] │ │ b 2417f24 │ │ @ instruction: 0x0191aa9c │ │ stc2l 6, cr3, [r3, #452]! @ 0x1c4 │ │ ldc2l 0, cr12, [pc, #76] @ 2417f14 │ │ orrseq r4, r2, ip, asr #13 │ │ - stc2l 5, cr10, [r0, #288]! @ 0x120 │ │ - stc2l 15, cr11, [r0, #644]! @ 0x284 │ │ + stc2l 5, cr10, [r0, #468]! @ 0x1d4 │ │ + stc2l 15, cr11, [r0, #824]! @ 0x338 │ │ eorseq sp, r3, r8, lsr #6 │ │ - stc2l 3, cr2, [r1, #1000]! @ 0x3e8 │ │ + stc2l 4, cr2, [r1, #156]! @ 0x9c │ │ stc2l 1, cr8, [r2, #472]! @ 0x1d8 │ │ ldr r0, [pc, #3932] @ 2418e40 │ │ movw r3, #2309 @ 0x905 │ │ ldr r2, [pc, #3928] @ 2418e44 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1261192,17 +1261192,17 @@ │ │ bl 270db90 │ │ cmp r0, #0 │ │ beq 24183f4 │ │ ldr r0, [pc, #4060] @ 2418f60 │ │ add r0, pc, r0 │ │ b 2419f54 │ │ stc2l 15, cr1, [r2, #960]! @ 0x3c0 │ │ - stc2l 0, cr12, [r1, #24]! │ │ + stc2l 0, cr12, [r1, #204]! @ 0xcc │ │ stc2l 15, cr1, [r2, #800]! @ 0x320 │ │ - stc2l 15, cr11, [r1, #872]! @ 0x368 │ │ + stc2l 0, cr12, [r1, #28]! │ │ ldr r0, [pc, #4036] @ 2418f64 │ │ mov r1, #71 @ 0x47 │ │ mov r7, ip │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #4020] @ 2418f68 │ │ mov r1, r7 │ │ @@ -1261291,24 +1261291,24 @@ │ │ orrseq r8, r6, r0, lsl #21 │ │ orrseq sl, r1, r0, lsl #16 │ │ orrseq sp, r6, ip, lsl lr │ │ orrseq sl, r1, r0, lsr r4 │ │ orrseq sp, r6, ip, ror #27 │ │ @ instruction: 0x019155dc │ │ stc2l 7, cr5, [r3, #264]! @ 0x108 │ │ - stc2l 13, cr11, [r0, #68]! @ 0x44 │ │ + stc2l 13, cr11, [r0, #248]! @ 0xf8 │ │ mlaseq r3, r8, r0, sp │ │ - stc2l 1, cr2, [r1, #328]! @ 0x148 │ │ + stc2l 1, cr2, [r1, #508]! @ 0x1fc │ │ ldc2l 14, cr13, [pc, #656] @ 24183bc │ │ @ instruction: 0x0196dcf8 │ │ stc2l 14, cr3, [r2, #192]! @ 0xc0 │ │ ldc2l 12, cr11, [pc, #444] @ 24182f4 │ │ eorseq r3, r3, r8, lsl #7 │ │ - stc2l 14, cr5, [r0, #648]! @ 0x288 │ │ - stc2l 2, cr8, [r0, #392]! @ 0x188 │ │ + stc2l 14, cr5, [r0, #828]! @ 0x33c │ │ + stc2l 2, cr8, [r0, #572]! @ 0x23c │ │ @ instruction: 0x0196dcb4 │ │ orrseq sp, r6, r0, lsl #25 │ │ ldr r0, [pc, #4024] @ 2419108 │ │ ldr r1, [pc, #4024] @ 241910c │ │ add r0, pc, r0 │ │ ldr r1, [pc, r1] │ │ str r1, [r0, #4] │ │ @@ -1261410,15 +1261410,15 @@ │ │ mov r2, #1 │ │ add r1, pc, r1 │ │ bl 270db00 │ │ ldr r0, [pc, #3980] @ 2419278 │ │ mov r1, #18 │ │ add r0, pc, r0 │ │ b 24165c4 │ │ - stc2l 0, cr2, [r1, #760]! @ 0x2f8 │ │ + stc2l 0, cr2, [r1, #940]! @ 0x3ac │ │ orrseq sp, r6, ip, lsr #24 │ │ eorseq r8, r3, r4, lsl #2 │ │ orrseq sp, r6, ip, lsl #23 │ │ ldr r4, [pc, #3952] @ 241927c │ │ ldr r5, [pc, #3952] @ 2419280 │ │ add r4, pc, r4 │ │ add r5, pc, r5 │ │ @@ -1261583,15 +1261583,15 @@ │ │ mov r0, r8 │ │ mov r2, r4 │ │ movw r3, #2367 @ 0x93f │ │ bl 270da30 │ │ ldr r2, [fp, #8] │ │ mov r1, r0 │ │ b 24184f8 │ │ - stc2l 12, cr5, [r0, #812]! @ 0x32c │ │ + stc2l 12, cr5, [r0, #992]! @ 0x3e0 │ │ orrseq r4, r2, r4 │ │ ldr r7, [pc, #3908] @ 24194fc │ │ ldr r7, [pc, r7] │ │ ldr r0, [pc, #3904] @ 2419500 │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #3900] @ 2419504 │ │ rsb r0, r0, r0, lsl #3 │ │ @@ -1261602,15 +1261602,15 @@ │ │ movt r0, #1 │ │ cmp r1, r0 │ │ bcs 2418600 │ │ mov r0, r7 │ │ b 2418620 │ │ orrseq sp, r6, r4, asr r9 │ │ @ instruction: 0x01923fb4 │ │ - stc2l 15, cr9, [r0, #484]! @ 0x1e4 │ │ + stc2l 15, cr9, [r0, #664]! @ 0x298 │ │ orrseq r3, r2, r4, lsl #31 │ │ orrseq sp, r6, r4, ror #17 │ │ ldr r0, [pc, #3840] @ 2419508 │ │ mov r2, r4 │ │ movw r3, #2383 @ 0x94f │ │ add r0, pc, r0 │ │ bl 270da30 │ │ @@ -1261635,26 +1261635,26 @@ │ │ bcc 2418704 │ │ ldr r0, [pc, #4028] @ 2419624 │ │ mov r2, r4 │ │ movw r3, #2386 @ 0x952 │ │ add r0, pc, r0 │ │ b 24186fc │ │ orrseq r3, r2, r4, asr #30 │ │ - stc2l 15, cr13, [r0, #720]! @ 0x2d0 │ │ + stc2l 15, cr13, [r0, #900]! @ 0x384 │ │ orrseq r3, r2, r4, lsl pc │ │ orrseq sp, r6, r4, ror r8 │ │ @ instruction: 0x01923ed4 │ │ orrseq r3, r2, ip, lsl #29 │ │ - stc2l 13, cr7, [r0, #760]! @ 0x2f8 │ │ + stc2l 13, cr7, [r0, #940]! @ 0x3ac │ │ orrseq sp, r6, r0, lsl r8 │ │ @ instruction: 0x0196d7dc │ │ orrseq sp, r6, r8, lsr #15 │ │ - stc2l 12, cr5, [r1, #308]! @ 0x134 │ │ + stc2l 12, cr5, [r1, #488]! @ 0x1e8 │ │ orrseq r3, r2, ip, ror #27 │ │ - stc2l 13, cr7, [r0, #136]! @ 0x88 │ │ + stc2l 13, cr7, [r0, #316]! @ 0x13c │ │ eorseq ip, r3, ip, lsl #21 │ │ stc2l 7, cr3, [r2, #388]! @ 0x184 │ │ ldc2l 6, cr11, [pc, #664] @ 2418950 │ │ stc2l 5, cr9, [r2, #860]! @ 0x35c │ │ ldc2l 6, cr11, [pc, #476] @ 241889c │ │ ldr r0, [pc, #3940] @ 2419628 │ │ mov r7, #0 │ │ @@ -1261765,23 +1261765,23 @@ │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ mov r7, #1 │ │ b 2418b50 │ │ orrseq sp, r6, r8, asr #13 │ │ ldc2l 15, cr15, [pc, #404] @ 2418a18 │ │ - stc2l 2, cr15, [r1, #188]! @ 0xbc │ │ + stc2l 2, cr15, [r1, #368]! @ 0x170 │ │ stc2l 13, cr2, [r3, #536]! @ 0x218 │ │ stc2l 0, cr5, [r3, #248]! @ 0xf8 │ │ - stc2l 6, cr11, [r0, #52]! @ 0x34 │ │ + stc2l 6, cr11, [r0, #232]! @ 0xe8 │ │ mlaseq r3, r4, r9, ip │ │ - stc2l 10, cr1, [r1, #312]! @ 0x138 @ │ │ + stc2l 10, cr1, [r1, #492]! @ 0x1ec @ │ │ stc2l 1, cr11, [r2, #644]! @ 0x284 │ │ stc2l 6, cr5, [r2, #492]! @ 0x1ec │ │ - stc2l 5, cr11, [r0, #660]! @ 0x294 │ │ + stc2l 5, cr11, [r0, #840]! @ 0x348 │ │ ldr r0, [r5, r1, lsl #2] │ │ ldr r1, [pc, #3884] @ 24197dc │ │ cmp r0, #0 │ │ ldr r1, [pc, r1] │ │ rsbmi r0, r0, #0 │ │ ldr r2, [pc, #3872] @ 24197e0 │ │ add r2, pc, r2 │ │ @@ -1261823,15 +1261823,15 @@ │ │ movw r3, #2427 @ 0x97b │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #3740] @ 2419800 │ │ add r0, pc, r0 │ │ b 24189b4 │ │ - stc2l 12, cr13, [r0, #1020]! @ 0x3fc │ │ + stc2l 13, cr13, [r0, #176]! @ 0xb0 │ │ orrseq sp, r6, ip, asr r5 │ │ stc2l 6, cr3, [r2, #592]! @ 0x250 │ │ ldc2l 4, cr11, [pc, #844] @ 2418cc8 │ │ ldrshteq r2, [r3], -r0 │ │ orrseq sp, r6, ip, lsl #10 │ │ stc2l 5, cr5, [r2, #356]! @ 0x164 │ │ ldc2l 4, cr11, [pc, #476] @ 2418b68 │ │ @@ -1261908,15 +1261908,15 @@ │ │ ldc2l 3, cr11, [pc, #428] @ 2418c54 │ │ orrseq sp, r6, r8, lsr #7 │ │ stc2l 2, cr9, [r2, #316]! @ 0x13c │ │ ldc2l 2, cr11, [pc, #956] @ 2418e70 │ │ orrseq sp, r6, r4, asr #6 │ │ stc2l 2, cr9, [r2, #108]! @ 0x6c │ │ ldc2l 2, cr11, [pc, #748] @ 2418dac │ │ - vcmla.f16 , q8, q9, #270 │ │ + stc2l 9, cr7, [r0, #30]! @ │ │ orrseq sp, r6, r8, lsr r3 │ │ stc2l 13, cr4, [r3, #764]! @ 0x2fc │ │ @ instruction: 0x0196d2b4 │ │ ldr r0, [pc, #4040] @ 2419a9c │ │ movw r2, #4464 @ 0x1170 │ │ movt r2, #1 │ │ mov r7, #1 │ │ @@ -1262039,15 +1262039,15 @@ │ │ add r0, pc, r0 │ │ b 2419f54 │ │ stc2l 2, cr3, [r2, #868]! @ 0x364 │ │ orrseq sp, r6, r4, ror r2 │ │ stc2l 3, cr3, [r2, #688]! @ 0x2b0 │ │ ldc2l 1, cr11, [pc, #940] @ 2419074 │ │ eorseq r2, r3, ip, lsl #18 │ │ - vcmla.f16 d23, d0, d10, #270 │ │ + stc2l 8, cr7, [r0, #220]! @ 0xdc │ │ orrseq sp, r6, ip, asr r2 │ │ orrseq sp, r6, ip, lsr #4 │ │ ldr r0, [pc, #4024] @ 2419c94 │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #4020] @ 2419c98 │ │ ldr r1, [pc, r1] │ │ cmp r1, r0 │ │ @@ -1262070,15 +1262070,15 @@ │ │ ldr r0, [fp, #8] │ │ add r1, pc, r1 │ │ bl 270e1c0 │ │ ldr r0, [pc, #3960] @ 2419cb4 │ │ add r0, pc, r0 │ │ b 2419f54 │ │ stc2l 2, cr1, [r2, #360]! @ 0x168 │ │ - stc2l 1, cr11, [r0, #644]! @ 0x284 │ │ + stc2l 1, cr11, [r0, #824]! @ 0x338 │ │ stc2l 2, cr1, [r2, #356]! @ 0x164 │ │ stc2l 2, cr1, [r2, #404]! @ 0x194 │ │ orrseq r3, r2, r0, asr #16 │ │ ldr r0, [pc, #3932] @ 2419cb8 │ │ mov r1, #59 @ 0x3b │ │ add r0, pc, r0 │ │ bl 270da00 │ │ @@ -1262182,15 +1262182,15 @@ │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2417e60 │ │ @ instruction: 0x019196b0 │ │ orrseq sp, r6, r4, asr #32 │ │ orrseq r8, r6, r4, lsl #3 │ │ orrseq r7, r6, r0, ror ip │ │ - stc2l 5, cr7, [r0, #872]! @ 0x368 │ │ + stc2l 6, cr7, [r0, #28]! │ │ orrseq sp, r6, ip, lsr #32 │ │ @ instruction: 0x0196cff8 │ │ ldr r0, [pc, #4008] @ 2419ec0 │ │ movw r3, #2310 @ 0x906 │ │ ldr r2, [pc, #4004] @ 2419ec4 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1262206,20 +1262206,20 @@ │ │ ldr r4, [pc, r4] │ │ cmp r2, r3 │ │ add r1, r1, r0, lsl #1 │ │ bhi 24191f4 │ │ lsl r0, r0, #1 │ │ b 2417f34 │ │ ldc2l 1, cr13, [pc, #304] @ 2419098 │ │ - stc2l 6, cr13, [r0, #480]! @ 0x1e0 │ │ - stc2l 15, cr10, [r0, #292]! @ 0x124 │ │ - stc2l 4, cr3, [r1, #164]! @ 0xa4 │ │ + stc2l 6, cr13, [r0, #660]! @ 0x294 │ │ + stc2l 15, cr10, [r0, #472]! @ 0x1d8 │ │ + stc2l 4, cr3, [r1, #344]! @ 0x158 │ │ stc2l 6, cr2, [r3, #456]! @ 0x1c8 │ │ orrseq r3, r2, ip, ror #11 │ │ - stc2l 3, cr1, [r1, #600]! @ 0x258 │ │ + stc2l 3, cr1, [r1, #780]! @ 0x30c │ │ ldr r0, [pc, #4068] @ 2419f68 │ │ ldr r4, [pc, #4068] @ 2419f6c │ │ add r0, pc, r0 │ │ add r4, pc, r4 │ │ mov r1, r4 │ │ bl 270d1b0 │ │ ldr r0, [pc, #4052] @ 2419f70 │ │ @@ -1262247,15 +1262247,15 @@ │ │ bl 270d1d0 │ │ ldr r0, [pc, #4084] @ 2419fec │ │ add r0, pc, r0 │ │ b 2419f54 │ │ stc2l 7, cr1, [r0, #988]! @ 0x3dc │ │ stc2l 6, cr2, [r3, #216]! @ 0xd8 │ │ stc2l 15, cr0, [r2, #424]! @ 0x1a8 │ │ - stc2l 14, cr10, [r0, #708]! @ 0x2c4 │ │ + stc2l 14, cr10, [r0, #888]! @ 0x378 │ │ ldr r0, [pc, #4060] @ 2419ff0 │ │ movw r3, #1580 @ 0x62c │ │ ldr r2, [pc, #4056] @ 2419ff4 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r4, [r6, r0, lsl #2] │ │ @@ -1262399,16 +1262399,16 @@ │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r7, r0 │ │ b 2417f44 │ │ eorseq ip, r3, r8, lsr #32 │ │ orrseq r9, r1, r8, lsr r3 │ │ - stc2l 15, cr4, [r0, #920]! @ 0x398 │ │ - stc2l 12, cr10, [r0, #260]! @ 0x104 │ │ + stc2l 0, cr5, [r0, #76]! @ 0x4c │ │ + stc2l 12, cr10, [r0, #440]! @ 0x1b8 │ │ @ instruction: 0x0196cc98 │ │ orrseq ip, r6, ip, ror #24 │ │ stc2l 3, cr2, [r3, #388]! @ 0x184 │ │ orrseq r9, r1, r4, asr r6 │ │ orrseq ip, r6, r0, ror ip │ │ orrseq r9, r1, r4, lsl #5 │ │ ldr r0, [pc, #3880] @ 241a1b8 │ │ @@ -1262462,15 +1262462,15 @@ │ │ eorseq fp, r3, r8, lsl #30 │ │ orrseq r9, r1, ip, lsl #4 │ │ @ instruction: 0x019143d4 │ │ @ instruction: 0x019231d0 │ │ orrseq r9, r1, r0, lsr #3 │ │ @ instruction: 0x01967898 │ │ orrseq ip, r6, ip, lsr fp │ │ - stc2l 1, cr7, [r0, #40]! @ 0x28 │ │ + stc2l 1, cr7, [r0, #220]! @ 0xdc │ │ ldr r0, [pc, #4060] @ 241a34c │ │ movw r3, #1626 @ 0x65a │ │ ldr r2, [pc, #4056] @ 241a350 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #4044] @ 241a354 │ │ @@ -1262513,15 +1262513,15 @@ │ │ sub r1, r0, #13 │ │ ldr r4, [pc, #4028] @ 241a3dc │ │ ldr r4, [pc, r4] │ │ b 2419488 │ │ ldc2l 10, cr10, [pc, #716] @ 24196f8 @ │ │ orrseq r7, r6, ip, ror ip │ │ orrseq ip, r6, r0, lsl fp │ │ - stc2l 2, cr15, [r0, #32]! │ │ + stc2l 2, cr15, [r0, #212]! @ 0xd4 │ │ orrseq r3, r2, r0, ror #2 │ │ orrseq r3, r2, r0, asr #2 │ │ orrseq ip, r6, ip, lsl #21 │ │ ldr r0, [pc, #3992] @ 241a3e0 │ │ movw r3, #1640 @ 0x668 │ │ ldr r2, [pc, #3988] @ 241a3e4 │ │ add r0, pc, r0 │ │ @@ -1262704,15 +1262704,15 @@ │ │ movt r0, #1 │ │ cmp r1, r0 │ │ bcs 2419738 │ │ mov r0, r7 │ │ b 2419758 │ │ @ instruction: 0x01922e98 │ │ orrseq r9, r1, ip, lsl r2 │ │ - stc2l 4, cr14, [r1, #524]! @ 0x20c │ │ + stc2l 4, cr14, [r1, #704]! @ 0x2c0 │ │ orrseq r9, r1, r0, asr #3 │ │ stc2l 7, cr0, [ip, #832]! @ 0x340 │ │ ldr r0, [pc, #4016] @ 241a6f0 │ │ mov r2, r4 │ │ movw r3, #1703 @ 0x6a7 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ @@ -1262747,26 +1262747,26 @@ │ │ orrseq ip, r6, r8, ror r7 │ │ @ instruction: 0x01918db8 │ │ orrseq r2, r2, ip, asr #27 │ │ stc2l 7, cr4, [r2, #612]! @ 0x264 │ │ @ instruction: 0x01922d9c │ │ orrseq r7, r6, r0, ror r3 │ │ orrseq r2, r2, r4, lsr #27 │ │ - stc2l 14, cr14, [r0, #16]! │ │ + stc2l 14, cr14, [r0, #196]! @ 0xc4 │ │ @ instruction: 0x0196c6b4 │ │ orrseq ip, r6, ip, lsr #13 │ │ orrseq r7, r6, r4, ror #5 │ │ @ instruction: 0x019672d8 │ │ orrseq ip, r6, r8, ror r6 │ │ orrseq r9, r1, r4, ror r0 │ │ orrseq ip, r6, r4, lsl #13 │ │ orrseq ip, r6, r8, lsr r6 │ │ stc2l 2, cr8, [r2, #884]! @ 0x374 │ │ stc2l 6, cr0, [ip, #48]! @ 0x30 │ │ - stc2l 2, cr14, [r1, #444]! @ 0x1bc │ │ + stc2l 2, cr14, [r1, #624]! @ 0x270 │ │ stc2l 5, cr0, [ip, #800]! @ 0x320 │ │ ldr r0, [pc, #4088] @ 241a80c │ │ mov r7, #0 │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #4080] @ 241a810 │ │ rsb r0, r0, r0, lsl #3 │ │ ldr r1, [pc, r1] │ │ @@ -1262869,15 +1262869,15 @@ │ │ cmp r1, #3 │ │ bcs 241950c │ │ ldr r7, [pc, #3864] @ 241a8cc │ │ add r7, pc, r7 │ │ b 241952c │ │ orrseq ip, r6, r4, lsr #11 │ │ orrseq r2, r2, r4, lsl #24 │ │ - stc2l 9, cr0, [r1, #286]! @ 0x11e @ │ │ + stc2l 9, cr0, [r1, #376]! @ 0x178 @ │ │ orrseq ip, r6, r4, lsl #11 │ │ stc2l 5, cr0, [ip, #496]! @ 0x1f0 │ │ orrseq r8, r1, ip, lsl pc │ │ orrseq ip, r6, r4, lsr r5 │ │ orrseq ip, r6, ip, lsl #10 │ │ ldr r0, [r5, r1, lsl #2] │ │ ldr r1, [pc, #3820] @ 241a8d0 │ │ @@ -1262929,25 +1262929,25 @@ │ │ add r0, pc, r0 │ │ b 2419b10 │ │ @ instruction: 0x01918ad4 │ │ orrseq r2, r2, r8, ror #21 │ │ stc2l 4, cr4, [r2, #724]! @ 0x2d4 │ │ @ instruction: 0x01922ab8 │ │ orrseq r2, r2, r4, asr #21 │ │ - stc2l 11, cr14, [r0, #144]! @ 0x90 @ │ │ + stc2l 11, cr14, [r0, #324]! @ 0x144 @ │ │ orrseq r2, r2, r4, lsl #21 │ │ orrseq r2, r2, r0, ror sl │ │ orrseq r2, r2, r0, ror #20 │ │ orrseq r2, r2, r8, ror #20 │ │ orrseq r8, r1, r0, lsr sl │ │ orrseq r2, r2, r0, asr #20 │ │ ldrshteq fp, [r3], -r4 │ │ orrseq ip, r6, r8, lsr #7 │ │ @ instruction: 0x0196c3d4 │ │ - stc2l 5, cr4, [r0, #520]! @ 0x208 │ │ + stc2l 5, cr4, [r0, #700]! @ 0x2bc │ │ @ instruction: 0x0196c398 │ │ orrseq r7, r6, ip, ror #9 │ │ orrseq ip, r6, r0, lsl #7 │ │ cmp r1, #3 │ │ bcc 2419b08 │ │ ldr r0, [pc, #3584] @ 241a8f8 │ │ mov r2, r4 │ │ @@ -1263006,15 +1263006,15 @@ │ │ mov r2, r4 │ │ movw r3, #1756 @ 0x6dc │ │ bl 270da30 │ │ ldr r7, [pc, #4032] @ 241ab9c │ │ mov r1, r0 │ │ ldr r7, [pc, r7] │ │ b 24199d8 │ │ - stc2l 5, cr4, [r0, #248]! @ 0xf8 │ │ + stc2l 5, cr4, [r0, #428]! @ 0x1ac │ │ orrseq ip, r6, r4, asr r3 │ │ orrseq r8, r1, r4, ror r9 │ │ @ instruction: 0x0196c2fc │ │ orrseq r8, r1, ip, asr r9 │ │ stc2l 3, cr4, [r2, #228]! @ 0xe4 │ │ ldc2l 2, cr10, [pc, #348] @ 2419d60 │ │ ldr r0, [pc, #3992] @ 241aba0 │ │ @@ -1263060,15 +1263060,15 @@ │ │ orrseq r8, r1, r8, ror #24 │ │ orrseq r8, r1, ip, lsr #17 │ │ orrseq ip, r6, r0, lsr r2 │ │ orrseq r8, r1, r8, asr #24 │ │ orrseq r7, r6, r0, ror #7 │ │ stc2l 12, cr3, [r3, #956]! @ 0x3bc │ │ stc2l 11, cr3, [r3, #776]! @ 0x308 @ │ │ - stc2l 1, cr10, [r0, #580]! @ 0x244 │ │ + stc2l 1, cr10, [r0, #760]! @ 0x2f8 │ │ eorseq fp, r3, r8, lsl r5 │ │ ldr r4, [pc, #4004] @ 241ac70 │ │ ldr r5, [pc, #4004] @ 241ac74 │ │ add r4, pc, r4 │ │ add r5, pc, r5 │ │ mov r0, r4 │ │ mov r1, r5 │ │ @@ -1263110,20 +1263110,20 @@ │ │ sub r1, r0, #1 │ │ cmp r1, r6 │ │ bhi 2419ed0 │ │ ldr r2, [pc, #3864] @ 241ac94 │ │ add r2, pc, r2 │ │ str r5, [r2, r1, lsl #2] │ │ b 2419f08 │ │ - stc2l 5, cr0, [r1, #840]! @ 0x348 │ │ + stc2l 5, cr0, [r1, #1020]! @ 0x3fc │ │ stc2l 0, cr8, [r2, #940]! @ 0x3ac │ │ stc2l 11, cr3, [r3, #328]! @ 0x148 @ │ │ - stc2l 1, cr10, [r0, #132]! @ 0x84 │ │ + stc2l 1, cr10, [r0, #312]! @ 0x138 │ │ eorseq fp, r3, r8, lsr #9 │ │ - stc2l 5, cr0, [r1, #392]! @ 0x188 │ │ + stc2l 5, cr0, [r1, #572]! @ 0x23c │ │ vcmla.f16 d17, d3, d30, #270 │ │ ldr r0, [pc, #3480] @ 241ab40 │ │ movw r3, #1627 @ 0x65b │ │ ldr r2, [pc, #3476] @ 241ab44 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1263370,15 +1263370,15 @@ │ │ movt r8, #1 │ │ str r0, [r6] │ │ ldr r4, [pc, #3056] @ 241ad78 │ │ ldr r5, [pc, #3056] @ 241ad7c │ │ add r4, pc, r4 │ │ add r5, pc, r5 │ │ b 241a214 │ │ - stc2l 3, cr6, [r0, #456]! @ 0x1c8 │ │ + stc2l 3, cr6, [r0, #636]! @ 0x27c │ │ eorseq fp, r3, r0, ror #1 │ │ stc2l 4, cr1, [r3, #488]! @ 0x1e8 │ │ stc2l 13, cr3, [r2, #756]! @ 0x2f4 │ │ ldc2l 12, cr9, [pc, #876] @ 241a518 │ │ @ instruction: 0x01918398 │ │ orrseq r6, r6, r8, lsl #19 │ │ stc2l 13, cr3, [r2, #452]! @ 0x1c4 │ │ @@ -1263561,17 +1263561,17 @@ │ │ b 2419f54 │ │ orrseq r6, r6, r0, lsr #24 │ │ orrseq r6, r6, ip, lsl #14 │ │ orrseq r2, r2, r8, lsl r1 │ │ orrseq r8, r1, r8, ror #1 │ │ orrseq r6, r6, r0, ror #15 │ │ orrseq fp, r6, r4, lsl #21 │ │ - stc2l 0, cr6, [r0, #328]! @ 0x148 │ │ + stc2l 0, cr6, [r0, #508]! @ 0x1fc │ │ ldc2l 9, cr9, [pc, #502] @ 241a692 @ │ │ - stc2l 1, cr14, [r0, #320]! @ 0x140 │ │ + stc2l 1, cr14, [r0, #500]! @ 0x1f4 │ │ orrseq r8, r1, ip, lsl #1 │ │ orrseq r2, r2, r8, lsr #1 │ │ @ instruction: 0x01922094 │ │ orrseq r2, r2, r4, lsl #1 │ │ @ instruction: 0x01922090 │ │ orrseq r6, r6, ip, asr #22 │ │ orrseq fp, r6, r0, ror #19 │ │ @@ -1263619,15 +1263619,15 @@ │ │ sub r1, r0, #1 │ │ cmp r1, r6 │ │ bhi 241a5e8 │ │ ldr r2, [pc, #1704] @ 241ac18 │ │ add r2, pc, r2 │ │ str r5, [r2, r1, lsl #2] │ │ b 241a620 │ │ - stc2l 0, cr14, [r0, #864]! @ 0x360 │ │ + stc2l 1, cr14, [r0, #20]! │ │ orrseq r2, r2, r0, lsr r0 │ │ orrseq r2, r2, r0, lsl r0 │ │ ldr r0, [pc, #1980] @ 241ad48 │ │ movw r3, #5653 @ 0x1615 │ │ ldr r2, [pc, #1976] @ 241ad4c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1263818,15 +1263818,15 @@ │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r3, r0 │ │ b 241a66c │ │ orrseq r1, r2, r4, asr #26 │ │ @ instruction: 0x01918098 │ │ - stc2l 3, cr13, [r1, #188]! @ 0xbc │ │ + stc2l 3, cr13, [r1, #368]! @ 0x170 │ │ orrseq r8, r1, ip, rrx │ │ stc2l 6, cr15, [fp, #496]! @ 0x1f0 │ │ orrseq r7, r1, ip, lsr #25 │ │ @ instruction: 0x0196629c │ │ orrseq fp, r6, r8, ror #12 │ │ orrseq fp, r6, r0, asr #12 │ │ orrseq fp, r6, r4, lsr #12 │ │ @@ -1263843,15 +1263843,15 @@ │ │ orrseq r6, r6, r4, lsr #3 │ │ orrseq fp, r6, r4, asr #10 │ │ orrseq r7, r1, r0, asr #30 │ │ orrseq fp, r6, r0, asr r5 │ │ orrseq fp, r6, r4, lsl #10 │ │ stc2l 1, cr7, [r2, #676]! @ 0x2a4 │ │ stc2l 4, cr15, [fp, #864]! @ 0x360 │ │ - stc2l 1, cr13, [r1, #76]! @ 0x4c │ │ + stc2l 1, cr13, [r1, #256]! @ 0x100 │ │ stc2l 4, cr15, [fp, #432]! @ 0x1b0 │ │ orrseq fp, r6, r8, asr #8 │ │ orrseq r1, r2, r8, lsr #21 │ │ ldr r0, [pc, #976] @ 241ace0 │ │ ldr r1, [pc, #976] @ 241ace4 │ │ add r0, pc, r0 │ │ ldr r1, [pc, r1] │ │ @@ -1263986,15 +1263986,15 @@ │ │ mov r2, #1 │ │ add r1, pc, r1 │ │ bl 270db00 │ │ ldr r0, [pc, #524] @ 241ad38 │ │ mov r1, #19 │ │ add r0, pc, r0 │ │ b 24165c4 │ │ - stc2l 8, cr15, [r0, #204]! @ 0xcc │ │ + vcmla.f16 , q0, q8, #270 │ │ orrseq fp, r6, r8, lsr #8 │ │ stc2l 4, cr15, [fp, #128]! @ 0x80 │ │ stc2l 2, cr1, [r2, #960]! @ 0x3c0 │ │ ldc2l 1, cr9, [pc, #188] @ 241ac08 │ │ eorseq r0, r3, ip, asr #16 │ │ orrseq r7, r1, r0, ror #15 │ │ stc2l 0, cr7, [r2, #316]! @ 0x13c │ │ @@ -1264019,15 +1264019,15 @@ │ │ orrseq fp, r6, r8, lsr #7 │ │ orrseq r7, r1, r4, lsr #19 │ │ @ instruction: 0x019219b8 │ │ orrseq r7, r1, ip, lsl #19 │ │ stc2l 3, cr3, [r2, #500]! @ 0x1f4 │ │ orrseq r1, r2, r0, lsl #19 │ │ orrseq r1, r2, ip, lsl #19 │ │ - stc2l 9, cr13, [r0, #472]! @ 0x1d8 @ │ │ + stc2l 10, cr13, [r0, #100]! @ 0x64 @ │ │ orrseq r1, r2, r8, ror #4 │ │ eorseq r9, r3, ip, lsl pc │ │ @ instruction: 0x0196abd0 │ │ @ instruction: 0x0196abfc │ │ orrseq r5, r6, r4, lsr #26 │ │ @ instruction: 0x0196abb8 │ │ @ instruction: 0x019171b8 │ │ @@ -1264109,18 +1264109,18 @@ │ │ eorseq r9, r3, r4, asr #17 │ │ eorseq r9, r3, r4, lsr #17 │ │ orrseq r5, r6, r0, lsl #14 │ │ eorseq r9, r3, r0, lsl #17 │ │ @ instruction: 0x01916b90 │ │ orrseq r5, r6, r0, asr r1 │ │ orrseq sl, r6, ip, ror #9 │ │ - stc2l 10, cr4, [r0, #408]! @ 0x198 @ │ │ + stc2l 10, cr4, [r0, #588]! @ 0x24c @ │ │ @ instruction: 0x0196a4bc │ │ - stc2l 11, cr12, [r0, #536]! @ 0x218 @ │ │ - stc2l 4, cr8, [r0, #4]! │ │ + stc2l 11, cr12, [r0, #716]! @ 0x2cc @ │ │ + stc2l 4, cr8, [r0, #184]! @ 0xb8 │ │ ldrheq r5, [r6, r0] │ │ orrseq sl, r6, ip, lsr #8 │ │ ldc2l 5, cr10, [pc, #668] @ 241afdc │ │ stc2l 14, cr2, [r2, #772]! @ 0x304 │ │ ldc2l 13, cr8, [pc, #892] @ 241b0c4 │ │ orrseq sl, r6, r0, lsr lr │ │ stc2l 10, cr2, [r2, #180]! @ 0xb4 @ │ │ @@ -1264133,23 +1264133,23 @@ │ │ ldc2l 7, cr8, [pc, #188] @ 241ae28 │ │ orrseq sl, r6, ip, ror r7 │ │ stc2l 7, cr2, [r2, #804]! @ 0x324 │ │ ldc2l 6, cr8, [pc, #924] @ 241b114 │ │ orrseq r1, r2, r0, ror #8 │ │ stc2l 14, cr2, [r2, #212]! @ 0xd4 │ │ ldc2l 13, cr8, [pc, #332] @ 241aed0 │ │ - stc2l 3, cr7, [r0, #564]! @ 0x234 │ │ + stc2l 3, cr7, [r0, #744]! @ 0x2e8 │ │ @ instruction: 0x01921394 │ │ @ instruction: 0x0196acfc │ │ orrseq r1, r2, r8, asr r3 │ │ - stc2l 3, cr11, [r0, #800]! @ 0x320 │ │ + stc2l 3, cr11, [r0, #980]! @ 0x3d4 │ │ orrseq r1, r2, r8, lsr #6 │ │ orrseq sl, r6, ip, lsl #25 │ │ orrseq r1, r2, r8, ror #5 │ │ - stc2l 15, cr2, [r0, #508]! @ 0x1fc │ │ + stc2l 15, cr2, [r0, #688]! @ 0x2b0 │ │ @ instruction: 0x019212b8 │ │ orrseq sl, r6, ip, lsl ip │ │ @ instruction: 0x019213dc │ │ │ │ 0241adb0 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ @@ -1264568,21 +1264568,21 @@ │ │ bl 270d220 │ │ ldr r0, [pc, #40] @ 241b3f4 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - stc2l 15, cr1, [r0, #500]! @ 0x1f4 │ │ + stc2l 15, cr1, [r0, #680]! @ 0x2a8 │ │ orrseq r6, r1, r8, lsr r2 │ │ eorseq r8, r3, r0, lsl #30 │ │ @ instruction: 0x019165d0 │ │ orrseq r4, r6, r8, ror #26 │ │ orrseq r4, r6, r0, asr sp │ │ - stc2l 15, cr1, [r0, #100]! @ 0x64 │ │ + stc2l 15, cr1, [r0, #280]! @ 0x118 │ │ │ │ 0241b3f8 : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #64 @ 0x40 │ │ mov r3, #0 │ │ str r1, [sp, #44] @ 0x2c │ │ @@ -1264799,32 +1264799,32 @@ │ │ bl 270da60 │ │ ldr r0, [pc, #84] @ 241b79c │ │ mov r1, #25 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ mov r0, r4 │ │ b 241b6f0 │ │ - stc2l 12, cr1, [r0, #72]! @ 0x48 │ │ + stc2l 12, cr1, [r0, #252]! @ 0xfc │ │ eorseq r8, r3, ip, asr sp │ │ eorseq r8, r3, r8, asr sp │ │ ldc2l 2, cr12, [pc, #504] @ 241b964 │ │ stc2l 4, cr1, [r3, #472]! @ 0x1d8 │ │ - stc2l 9, cr7, [r0, #106]! @ 0x6a @ │ │ + stc2l 9, cr7, [r0, #196]! @ 0xc4 @ │ │ ldc2l 11, cr9, [pc, #60] @ 241b7b4 @ │ │ stc2l 9, cr15, [r1, #250]! @ 0xfa @ │ │ eorseq r8, r3, ip, lsl #25 │ │ eorseq r8, r3, r4, ror ip │ │ ldc2l 1, cr12, [pc, #616] @ 241b9f0 │ │ ldc2l 10, cr9, [pc, #560] @ 241b9bc @ │ │ - stc2l 8, cr7, [r0, #324]! @ 0x144 │ │ + stc2l 8, cr7, [r0, #504]! @ 0x1f8 │ │ stc2l 10, cr3, [r2, #128]! @ 0x80 @ │ │ ldc2l 1, cr12, [pc, #88] @ 241b7f0 │ │ - stc2l 8, cr7, [r1, #636]! @ 0x27c │ │ - stc2l 7, cr7, [r0, #804]! @ 0x324 │ │ - stc2l 4, cr11, [r1, #816]! @ 0x330 │ │ + vcmla.f16 , , q6, #270 │ │ + stc2l 7, cr7, [r0, #984]! @ 0x3d8 │ │ + stc2l 4, cr11, [r1, #996]! @ 0x3e4 │ │ │ │ 0241b7a0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ mov r5, r3 │ │ mov r9, r2 │ │ @@ -1265049,17 +1265049,17 @@ │ │ cmp r0, #0 │ │ beq 241bb08 │ │ bl 27030a0 │ │ mov r0, #0 │ │ sub sp, fp, #8 │ │ pop {r4, sl, fp, pc} │ │ eorseq pc, r1, ip, lsr r9 @ │ │ - ldc2l 11, cr15, [pc, #220] @ 241bbfc @ │ │ + ldc2l 11, cr15, [pc, #400] @ 241bcb0 @ │ │ eorseq pc, r1, r8, asr r9 @ │ │ - stc2l 11, cr5, [r0] @ │ │ + stc2l 11, cr5, [r0, #180]! @ 0xb4 @ │ │ │ │ 0241bb24 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ ldr r1, [r0, #4] │ │ mov r4, #0 │ │ @@ -1265203,15 +1265203,15 @@ │ │ eorseq pc, r1, r0, lsl #17 │ │ eorseq pc, r1, r8, lsr #16 │ │ eorseq pc, r1, r4, lsl #17 │ │ ldrsbteq pc, [r1], -r0 @ │ │ ldrsbteq pc, [r1], -r8 @ │ │ eorseq pc, r1, r4, ror r7 @ │ │ eorseq pc, r1, ip, lsl #15 │ │ - vcmla.f16 d21, d16, d0, #270 │ │ + vcmla.f16 d21, d16, d29, #270 │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ sub sp, sp, #1024 @ 0x400 │ │ add r9, sp, #4 │ │ mov r8, r2 │ │ mov r4, r1 │ │ @@ -1265298,17 +1265298,17 @@ │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ vcmla.f16 d30, d2, d28, #270 │ │ - stc2l 7, cr5, [r0, #176]! @ 0xb0 │ │ + stc2l 7, cr5, [r0, #356]! @ 0x164 │ │ stc2l 2, cr3, [r2, #164]! @ 0xa4 │ │ - stc2l 3, cr3, [r1, #884]! @ 0x374 │ │ + stc2l 4, cr3, [r1, #40]! @ 0x28 │ │ stc2l 7, cr14, [r2, #560]! @ 0x230 │ │ │ │ 0241befc : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r5, r1 │ │ @@ -1265381,24 +1265381,24 @@ │ │ ldr r0, [pc, #56] @ 241c054 │ │ mov r1, #5 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, r4 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2l 6, cr15, [pc, #976] @ 241c408 │ │ + ldc2l 7, cr15, [pc, #132] @ 241c0bc │ │ stc2l 13, cr0, [r2, #344]! @ 0x158 │ │ - stc2l 15, cr6, [r0, #228]! @ 0xe4 │ │ - stc2l 4, cr9, [r0, #492]! @ 0x1ec │ │ + stc2l 15, cr6, [r0, #408]! @ 0x198 │ │ + stc2l 4, cr9, [r0, #672]! @ 0x2a0 │ │ ldc2l 14, cr8, [pc, #656] @ 241c2d8 │ │ - stc2l 15, cr6, [r0, #36]! @ 0x24 │ │ + stc2l 15, cr6, [r0, #216]! @ 0xd8 │ │ ldc2l 8, cr13, [pc, #588] @ 241c29c │ │ - stc2l 15, cr6, [r0, #436]! @ 0x1b4 │ │ + stc2l 15, cr6, [r0, #616]! @ 0x268 │ │ stc2l 10, cr12, [r2, #252]! @ 0xfc @ │ │ - ldc2l 6, cr15, [pc] @ 241c05c │ │ + ldc2l 6, cr15, [pc, #180] @ 241c110 │ │ │ │ 0241c058 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ mov r6, r3 │ │ mov r4, r2 │ │ @@ -1265496,18 +1265496,18 @@ │ │ mov r0, r4 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ vcmla.f16 q12, q1, q0, #270 │ │ - ldc2l 5, cr15, [pc, #264] @ 241c304 │ │ + ldc2l 5, cr15, [pc, #444] @ 241c3b8 │ │ stc2l 7, cr8, [r2, #304]! @ 0x130 │ │ stc2l 15, cr2, [r2, #312]! @ 0x138 │ │ - stc2l 15, cr6, [r1, #276]! @ 0x114 │ │ + stc2l 15, cr6, [r1, #456]! @ 0x1c8 │ │ │ │ 0241c204 : │ │ push {fp, lr} │ │ mov fp, sp │ │ mov r3, r2 │ │ mov r2, r1 │ │ mov r1, r0 │ │ @@ -1265575,19 +1265575,19 @@ │ │ ldr r0, [pc, #36] @ 241c320 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - stc2l 0, cr1, [r0, #464]! @ 0x1d0 │ │ - stc2l 15, cr4, [r1, #184]! @ 0xb8 │ │ + stc2l 0, cr1, [r0, #644]! @ 0x284 │ │ + stc2l 15, cr4, [r1, #364]! @ 0x16c │ │ stc2l 14, cr2, [r2, #4]! │ │ - stc2l 15, cr2, [r1, #724]! @ 0x2d4 │ │ - stc2l 15, cr0, [r0, #960]! @ 0x3c0 │ │ + stc2l 15, cr2, [r1, #904]! @ 0x388 │ │ + stc2l 0, cr1, [r0, #116]! @ 0x74 │ │ │ │ 0241c324 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #16 │ │ mov r4, r0 │ │ bl 270ce80 │ │ @@ -1265626,15 +1265626,15 @@ │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, r5 │ │ sub sp, fp, #8 │ │ pop {r4, r5, fp, pc} │ │ stc2l 7, cr12, [r2, #728]! @ 0x2d8 │ │ - stc2l 13, cr0, [r0, #904]! @ 0x388 │ │ + stc2l 14, cr0, [r0, #60]! @ 0x3c │ │ eorseq r7, r3, ip, asr pc │ │ stc2l 7, cr12, [r2, #280]! @ 0x118 │ │ │ │ 0241c3e0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #36 @ 0x24 │ │ @@ -1266762,28 +1266762,28 @@ │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #2672] @ 241dfec │ │ add r0, pc, r0 │ │ str r4, [r0, r1, lsl #2] │ │ b 241c6ec │ │ - stc2l 0, cr5, [r0, #352]! @ 0x160 │ │ + stc2l 0, cr5, [r0, #532]! @ 0x214 │ │ stc2l 0, cr14, [r2, #684]! @ 0x2ac │ │ - stc2l 9, cr6, [r0, #98]! @ 0x62 @ │ │ - stc2l 13, cr12, [r0, #872]! @ 0x368 │ │ + stc2l 9, cr6, [r0, #188]! @ 0xbc @ │ │ + stc2l 14, cr12, [r0, #28]! │ │ @ instruction: 0x01968990 │ │ orrseq r8, r6, r4, lsl #21 │ │ orrseq r8, r6, ip, asr sl │ │ orrseq r8, r6, r8, asr #20 │ │ orrseq r8, r6, r0, lsr sl │ │ orrseq r8, r6, r4, lsr #20 │ │ orrseq r8, r6, r4, ror r9 │ │ orrseq r8, r6, r0, lsl #20 │ │ stc2l 2, cr8, [r2, #300]! @ 0x12c │ │ - stc2l 0, cr11, [r0, #36]! @ 0x24 │ │ + stc2l 0, cr11, [r0, #216]! @ 0xd8 │ │ orrseq r8, r6, r4, asr #17 │ │ @ instruction: 0x019689b0 │ │ ldr r0, [pc, #2916] @ 241e130 │ │ ldr r0, [pc, r0] │ │ ldr r1, [sp, #28] │ │ add r0, r0, #1 │ │ str r0, [r1] │ │ @@ -1266853,19 +1266853,19 @@ │ │ ldr r6, [pc, #2700] @ 241e168 │ │ add r7, pc, r7 │ │ add r6, pc, r6 │ │ b 241d758 │ │ orrseq r8, r6, r4, lsr #19 │ │ orrseq r8, r6, r0, lsr #19 │ │ stc2l 1, cr8, [r2, #1000]! @ 0x3e8 │ │ - stc2l 15, cr10, [r0, #708]! @ 0x2c4 │ │ + stc2l 15, cr10, [r0, #888]! @ 0x378 │ │ orrseq r8, r6, r0, lsl r9 │ │ orrseq r8, r6, r0, asr r9 │ │ ldc2l 1, cr13, [pc, #144] @ 241d794 │ │ - stc2l 15, cr10, [r0, #388]! @ 0x184 │ │ + stc2l 15, cr10, [r0, #568]! @ 0x238 │ │ orrseq r8, r6, ip, lsl r9 │ │ mlaseq r3, r0, ip, r7 │ │ orrseq r8, r6, r4, lsr #18 │ │ orrseq r8, r6, r4, ror #26 │ │ orrseq r8, r6, r8, asr #26 │ │ orrseq r8, r6, r4, lsr sp │ │ orrseq r8, r6, r4, asr #26 │ │ @@ -1266912,30 +1266912,30 @@ │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #2508] @ 241e19c │ │ add r0, pc, r0 │ │ b 241d848 │ │ orrseq r8, r6, ip, lsr #17 │ │ ldc2l 9, cr8, [pc, #224] @ 241d8c0 @ │ │ - stc2l 14, cr10, [r0, #804]! @ 0x324 │ │ + stc2l 14, cr10, [r0, #984]! @ 0x3d8 │ │ orrseq r8, r6, ip, lsr #17 │ │ orrseq r8, r6, r8, ror #25 │ │ orrseq r8, r6, r8, ror #16 │ │ stc2l 15, cr9, [r2, #292]! @ 0x124 │ │ - stc2l 14, cr10, [r0, #532]! @ 0x214 │ │ + stc2l 14, cr10, [r0, #712]! @ 0x2c8 │ │ eorseq r7, r3, r4, ror fp │ │ orrseq r8, r6, r0, lsr r8 │ │ orrseq r8, r6, r8, lsl r8 │ │ ldc2l 15, cr12, [pc, #960] @ 241dbc8 │ │ - stc2l 14, cr10, [r0, #180]! @ 0xb4 │ │ + stc2l 14, cr10, [r0, #360]! @ 0x168 │ │ eorseq r7, r3, r8, ror #22 │ │ orrseq r8, r6, r4, lsr #24 │ │ orrseq r8, r6, r8, asr #15 │ │ stc2l 0, cr8, [r2, #60]! @ 0x3c │ │ - stc2l 13, cr10, [r0, #820]! @ 0x334 │ │ + stc2l 13, cr10, [r0, #1000]! @ 0x3e8 │ │ orrseq r8, r6, r8, lsl #13 │ │ cmp r1, #3 │ │ bcc 241d840 │ │ ldr r0, [pc, #2416] @ 241e1a0 │ │ mov r2, r7 │ │ movw r3, #1174 @ 0x496 │ │ add r0, pc, r0 │ │ @@ -1266996,26 +1266996,26 @@ │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #2208] @ 241e1c0 │ │ ldr r0, [pc, r0] │ │ b 241d724 │ │ orrseq r8, r6, r4, ror #14 │ │ stc2l 7, cr3, [r3, #780]! @ 0x30c │ │ - stc2l 13, cr10, [r0, #484]! @ 0x1e4 │ │ + stc2l 13, cr10, [r0, #664]! @ 0x298 │ │ orrseq r8, r6, ip, lsr #14 │ │ eorseq r7, r3, r8, ror #18 │ │ stc2l 7, cr3, [r3, #488]! @ 0x1e8 │ │ - stc2l 13, cr10, [r0, #164]! @ 0xa4 │ │ + stc2l 13, cr10, [r0, #344]! @ 0x158 │ │ eorseq r7, r3, r4, asr fp │ │ - stc2l 9, cr12, [r0, #310]! @ 0x136 @ │ │ - stc2l 12, cr10, [r0, #932]! @ 0x3a4 │ │ + stc2l 9, cr12, [r0, #400]! @ 0x190 @ │ │ + stc2l 13, cr10, [r0, #88]! @ 0x58 │ │ stc2l 5, cr12, [fp, #688]! @ 0x2b0 │ │ orrseq r8, r6, r0, asr #13 │ │ - stc2l 9, cr12, [r0, #94]! @ 0x5e @ │ │ - stc2l 12, cr10, [r0, #500]! @ 0x1f4 │ │ + stc2l 9, cr12, [r0, #184]! @ 0xb8 @ │ │ + stc2l 12, cr10, [r0, #680]! @ 0x2a8 │ │ stc2l 5, cr12, [fp, #240]! @ 0xf0 │ │ ldr r2, [pc, #1676] @ 241dff4 │ │ ldr r0, [pc, #1676] @ 241dff8 │ │ add r2, pc, r2 │ │ add r0, pc, r0 │ │ ldr r0, [r0, #32] │ │ ldr r1, [pc, #1664] @ 241dffc │ │ @@ -1267078,22 +1267078,22 @@ │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #1480] @ 241e034 │ │ add r0, pc, r0 │ │ b 241dac4 │ │ ldc2l 6, cr8, [pc, #720] @ 241dd48 │ │ - stc2l 12, cr10, [r0, #52]! @ 0x34 │ │ + stc2l 12, cr10, [r0, #232]! @ 0xe8 │ │ orrseq r8, r6, r4, lsl r5 │ │ - stc2l 11, cr4, [r0, #128]! @ 0x80 @ │ │ + stc2l 11, cr4, [r0, #308]! @ 0x134 @ │ │ stc2l 14, cr7, [r2, #132]! @ 0x84 │ │ - stc2l 3, cr6, [r0, #964]! @ 0x3c4 │ │ + stc2l 4, cr6, [r0, #120]! @ 0x78 │ │ ldrsbteq r7, [r3], -r4 │ │ @ instruction: 0x01968994 │ │ - stc2l 11, cr10, [r0, #436]! @ 0x1b4 @ │ │ + stc2l 11, cr10, [r0, #616]! @ 0x268 @ │ │ ldr r6, [pc, #1436] @ 241e038 │ │ cmp r1, #3 │ │ add r6, pc, r6 │ │ bcc 241dabc │ │ ldr r0, [pc, #1424] @ 241e03c │ │ mov r2, r7 │ │ movw r3, #938 @ 0x3aa │ │ @@ -1267151,23 +1267151,23 @@ │ │ sub r1, r0, #4 │ │ cmp r1, #59 @ 0x3b │ │ bhi 241dbc0 │ │ str r4, [r9, r1, lsl #2] │ │ b 241dbf8 │ │ orrseq r8, r6, r4, lsl #10 │ │ stc2l 11, cr9, [r2, #916]! @ 0x394 @ │ │ - stc2l 11, cr10, [r0, #132]! @ 0x84 @ │ │ + stc2l 11, cr10, [r0, #312]! @ 0x138 @ │ │ eorseq r7, r3, r8, lsl #16 │ │ @ instruction: 0x019684f8 │ │ @ instruction: 0x019684d4 │ │ eorseq r7, r3, r0, lsl sl │ │ - stc2l 7, cr12, [r0, #396]! @ 0x18c │ │ - stc2l 10, cr10, [r0, #708]! @ 0x2c4 @ │ │ - stc2l 7, cr12, [r0, #204]! @ 0xcc │ │ - stc2l 10, cr10, [r0, #500]! @ 0x1f4 @ │ │ + stc2l 7, cr12, [r0, #576]! @ 0x240 │ │ + stc2l 10, cr10, [r0, #888]! @ 0x378 @ │ │ + stc2l 7, cr12, [r0, #384]! @ 0x180 │ │ + stc2l 10, cr10, [r0, #680]! @ 0x2a8 @ │ │ orrseq r8, r6, r4, lsr #8 │ │ mov r0, r6 │ │ mov r2, r7 │ │ movw r3, #943 @ 0x3af │ │ bl 270da30 │ │ str r4, [r9, r0, lsl #2] │ │ ldr r0, [pc, #1168] @ 241e06c │ │ @@ -1267216,15 +1267216,15 @@ │ │ bge 241dd94 │ │ cmp r5, r0 │ │ ble 241d9fc │ │ b 241dd94 │ │ orrseq r8, r6, r8, lsl #6 │ │ @ instruction: 0x019683f0 │ │ stc2l 12, cr7, [r2, #344]! @ 0x158 │ │ - stc2l 10, cr10, [r0, #52]! @ 0x34 @ │ │ + stc2l 10, cr10, [r0, #232]! @ 0xe8 @ │ │ orrseq r8, r6, ip, ror #6 │ │ orrseq r8, r6, ip, lsr #7 │ │ stc2l 10, cr9, [r2, #548]! @ 0x224 @ │ │ mov r0, r6 │ │ mov r2, r7 │ │ mov r3, #944 @ 0x3b0 │ │ bl 270da30 │ │ @@ -1267242,15 +1267242,15 @@ │ │ ldr r2, [pc, r2] │ │ add r0, r2, r0 │ │ sub r1, r0, #4 │ │ cmp r1, #59 @ 0x3b │ │ bhi 241dd24 │ │ ldr r5, [r8, r1, lsl #2] │ │ b 241dc18 │ │ - stc2l 9, cr10, [r0, #394]! @ 0x18a @ │ │ + stc2l 9, cr10, [r0, #484]! @ 0x1e4 @ │ │ ldrhteq r7, [r3], -r0 │ │ orrseq r8, r6, r4, lsl #7 │ │ orrseq r8, r6, r8, lsr #7 │ │ ldrsbteq r7, [r3], -r0 │ │ eorseq r7, r3, ip, asr #17 │ │ @ instruction: 0x01968798 │ │ orrseq r8, r6, ip, lsr #6 │ │ @@ -1267277,15 +1267277,15 @@ │ │ mov r1, r0 │ │ ldr r2, [pc, r2] │ │ b 241dc18 │ │ orrseq r8, r6, r4, lsl #15 │ │ orrseq r8, r6, r0, lsl #6 │ │ eorseq r7, r3, ip, ror r6 │ │ ldc2l 10, cr12, [pc, #928] @ 241e134 @ │ │ - stc2l 9, cr10, [r0, #74]! @ 0x4a @ │ │ + stc2l 9, cr10, [r0, #164]! @ 0xa4 @ │ │ ldr r6, [sp, #24] │ │ cmp r5, r0 │ │ str r4, [fp, #-32] @ 0xffffffe0 │ │ mov r4, #0 │ │ movwle r4, #1 │ │ b 241ddb8 │ │ orrseq r8, r6, r8, asr #14 │ │ @@ -1267312,15 +1267312,15 @@ │ │ b 241c874 │ │ orrseq r8, r6, r4, lsl #5 │ │ orrseq r8, r6, ip, lsl #5 │ │ orrseq r8, r6, r8, ror r2 │ │ mlaseq r3, r0, r4, r7 │ │ ldrhteq r7, [r3], -r8 │ │ eorseq r7, r3, r4, asr #11 │ │ - stc2l 8, cr10, [r0, #452]! @ 0x1c4 │ │ + stc2l 8, cr10, [r0, #632]! @ 0x278 │ │ orrseq r8, r6, ip, lsr r2 │ │ ldc2l 2, cr8, [pc, #880] @ 241e19c │ │ orrseq r8, r6, r4, lsl #4 │ │ orrseq r8, r6, ip, lsr r1 │ │ ldc2l 2, cr8, [pc, #624] @ 241e0a8 │ │ orrseq r8, r6, r8, lsl #2 │ │ orrseq r8, r6, r0, asr #3 │ │ @@ -1267421,134 +1267421,134 @@ │ │ orrseq r7, r6, r0, lsr #24 │ │ orrseq r7, r6, ip, lsr #24 │ │ @ instruction: 0x01967bfc │ │ orrseq r7, r6, r0, asr #22 │ │ orrseq r7, r6, r0, ror #21 │ │ @ instruction: 0x01967bb4 │ │ ldc2l 12, cr7, [pc, #480] @ 241e1b4 │ │ - stc2l 1, cr10, [r0, #836]! @ 0x344 │ │ + stc2l 1, cr10, [r0, #1016]! @ 0x3f8 │ │ @ instruction: 0x01967adc │ │ orrseq r7, r6, r0, lsr #23 │ │ - ldc2l 12, cr15, [pc, #56] @ 241e01c │ │ + ldc2l 12, cr15, [pc, #236] @ 241e0d0 │ │ orrseq r7, r6, ip, asr #22 │ │ stc2l 3, cr7, [r2, #712]! @ 0x2c8 │ │ - stc2l 1, cr10, [r0, #420]! @ 0x1a4 │ │ + stc2l 1, cr10, [r0, #600]! @ 0x258 │ │ orrseq r7, r6, r8, asr #21 │ │ orrseq r7, r6, r4, lsr #23 │ │ orrseq r7, r6, r4, ror #14 │ │ orrseq r7, r6, r4, ror r7 │ │ orrseq r7, r6, r0, lsr r7 │ │ - stc2l 2, cr9, [r1, #460]! @ 0x1cc │ │ - stc2l 13, cr9, [r0, #196]! @ 0xc4 │ │ + stc2l 2, cr9, [r1, #640]! @ 0x280 │ │ + stc2l 13, cr9, [r0, #376]! @ 0x178 │ │ stc2l 5, cr11, [fp, #896]! @ 0x380 │ │ orrseq r7, r6, ip, lsl r7 │ │ orrseq r7, r6, r8, asr #22 │ │ orrseq r7, r6, ip, lsr #22 │ │ - stc2l 12, cr9, [r0, #884]! @ 0x374 │ │ + stc2l 13, cr9, [r0, #40]! @ 0x28 │ │ eorseq r6, r3, r8, lsl fp │ │ - stc2l 11, cr1, [r0, #136]! @ 0x88 @ │ │ + stc2l 11, cr1, [r0, #316]! @ 0x13c @ │ │ orrseq r7, r6, r0, asr #13 │ │ orrseq r7, r6, r0, ror #21 │ │ stc2l 6, cr2, [r3, #872]! @ 0x368 │ │ stc2l 1, cr3, [r2, #852]! @ 0x354 │ │ stc2l 5, cr11, [fp, #160]! @ 0xa0 │ │ stc2l 6, cr2, [r3, #520]! @ 0x208 │ │ - stc2l 1, cr9, [r1, #380]! @ 0x17c │ │ + stc2l 1, cr9, [r1, #560]! @ 0x230 │ │ stc2l 4, cr11, [fp, #880]! @ 0x370 │ │ orrseq r7, r6, r0, asr #20 │ │ orrseq r7, r6, r0, lsr sl │ │ orrseq r7, r6, ip, lsr #11 │ │ @ instruction: 0x019675d4 │ │ stc2l 6, cr2, [r3, #12]! │ │ ldrhteq r6, [r3], -ip │ │ orrseq r7, r6, ip, lsr #11 │ │ - stc2l 9, cr1, [r0, #460]! @ 0x1cc @ │ │ + stc2l 10, cr1, [r0, #76]! @ 0x4c @ │ │ orrseq r7, r6, r8, lsr r5 │ │ @ instruction: 0x0196799c │ │ @ instruction: 0x019674bc │ │ orrseq r7, r6, r8, lsr #18 │ │ orrseq r7, r6, ip, asr #9 │ │ @ instruction: 0x019674bc │ │ orrseq r7, r6, r8, lsl #8 │ │ @ instruction: 0x019673fc │ │ @ instruction: 0x019673b8 │ │ orrseq r7, r6, r4, lsr #16 │ │ ldc2l 11, cr11, [pc, #384] @ 241e214 @ │ │ orrseq r7, r6, r8, asr r3 │ │ orrseq r7, r6, r4, asr #15 │ │ @ instruction: 0x01967794 │ │ - stc2l 7, cr11, [r0, #268]! @ 0x10c │ │ + stc2l 7, cr11, [r0, #448]! @ 0x1c0 │ │ stc2l 3, cr11, [fp, #384]! @ 0x180 │ │ orrseq r7, r6, r8, lsl #9 │ │ orrseq r7, r6, r8, ror r4 │ │ @ instruction: 0x01967898 │ │ @ instruction: 0x019672d4 │ │ orrseq r7, r6, ip, asr #5 │ │ stc2l 11, cr6, [r2, #172]! @ 0xac @ │ │ - vcmla.f16 , q8, , #270 │ │ + stc2l 9, cr9, [r0, #44]! @ 0x2c @ │ │ orrseq r7, r6, r8, lsr #3 │ │ - stc2l 10, cr9, [r1, #24]! @ │ │ - stc2l 4, cr10, [r0, #660]! @ 0x294 │ │ + stc2l 10, cr9, [r1, #204]! @ 0xcc @ │ │ + stc2l 4, cr10, [r0, #840]! @ 0x348 │ │ eorseq r7, r3, r4, asr #7 │ │ - stc2l 9, cr9, [r1, #404]! @ 0x194 @ │ │ - stc2l 4, cr10, [r0, #420]! @ 0x1a4 │ │ + stc2l 9, cr9, [r1, #494]! @ 0x1ee @ │ │ + stc2l 4, cr10, [r0, #600]! @ 0x258 │ │ eorseq r7, r3, r8, lsl #7 │ │ orrseq r7, r6, r4, lsr #28 │ │ eorseq r7, r3, ip, ror #6 │ │ - stc2l 9, cr9, [r1, #252]! @ 0xfc @ │ │ - stc2l 4, cr10, [r0, #116]! @ 0x74 │ │ + stc2l 9, cr9, [r1, #342]! @ 0x156 @ │ │ + stc2l 4, cr10, [r0, #296]! @ 0x128 │ │ @ instruction: 0x019681dc │ │ orrseq r8, r6, r8, asr #3 │ │ orrseq r7, r6, ip, lsl #27 │ │ orrseq r7, r6, r0, lsl #27 │ │ eorseq r7, r3, r0, asr #6 │ │ eorseq r7, r3, ip, lsl #5 │ │ eorseq r7, r3, r8, asr r2 │ │ orrseq r7, r6, ip, ror ip │ │ ldc2l 13, cr7, [pc, #256] @ 241e214 │ │ - stc2l 2, cr10, [r0, #612]! @ 0x264 │ │ + stc2l 2, cr10, [r0, #792]! @ 0x318 │ │ orrseq r7, r6, r8, ror #25 │ │ eorseq r7, r3, r4, asr #4 │ │ eorseq r7, r3, r4, asr #4 │ │ orrseq r7, r6, r0, lsl sp │ │ orrseq r7, r6, r8, lsr #25 │ │ ldc2l 13, cr7, [pc, #432] @ 241e2e0 │ │ - stc2l 2, cr10, [r0, #788]! @ 0x314 │ │ + stc2l 2, cr10, [r0, #968]! @ 0x3c8 │ │ orrseq r7, r6, r0, ror #21 │ │ - stc2l 6, cr9, [r1, #216]! @ 0xd8 │ │ - stc2l 0, cr10, [r0, #852]! @ 0x354 │ │ + stc2l 6, cr9, [r1, #396]! @ 0x18c │ │ + stc2l 1, cr10, [r0, #8]! │ │ ldrshteq r6, [r3], -r4 │ │ - stc2l 15, cr1, [r0, #24]! │ │ - stc2l 0, cr10, [r0, #644]! @ 0x284 │ │ + stc2l 15, cr1, [r0, #204]! @ 0xcc │ │ + stc2l 0, cr10, [r0, #824]! @ 0x338 │ │ orrseq r7, r6, r0, lsl #21 │ │ - stc2l 5, cr9, [r1, #588]! @ 0x24c │ │ - stc2l 0, cr10, [r0, #324]! @ 0x144 │ │ + stc2l 5, cr9, [r1, #768]! @ 0x300 │ │ + stc2l 0, cr10, [r0, #504]! @ 0x1f8 │ │ stc2l 9, cr11, [fp] @ │ │ orrseq r7, r6, ip, lsr sl │ │ orrseq r7, r6, r8, ror #28 │ │ orrseq r7, r6, r4, lsl #20 │ │ - stc2l 15, cr9, [r0, #996]! @ 0x3e4 │ │ - stc2l 14, cr1, [r0, #344]! @ 0x158 │ │ + stc2l 0, cr10, [r0, #152]! @ 0x98 │ │ + stc2l 14, cr1, [r0, #524]! @ 0x20c │ │ orrseq r7, r6, r0, asr r2 │ │ ldc2l 3, cr7, [pc, #80] @ 241e1c8 │ │ - vcmla.f16 , q0, , #270 │ │ + stc2l 8, cr9, [r0, #616]! @ 0x268 │ │ orrseq r7, r6, r0, ror r1 │ │ - stc2l 7, cr3, [r0, #496]! @ 0x1f0 │ │ - ldc2l 4, cr15, [pc, #332] @ 241e2d4 │ │ - stc2l 0, cr5, [r0, #308]! @ 0x134 │ │ + stc2l 7, cr3, [r0, #676]! @ 0x2a4 │ │ + ldc2l 4, cr15, [pc, #512] @ 241e388 │ │ + stc2l 0, cr5, [r0, #488]! @ 0x1e8 │ │ @ instruction: 0x019671f0 │ │ @ instruction: 0x019671d8 │ │ - stc2l 0, cr5, [r1, #880]! @ 0x370 │ │ + stc2l 1, cr5, [r1, #36]! @ 0x24 │ │ orrseq r7, r6, r4, ror sp │ │ stc2l 4, cr3, [r2, #452]! @ 0x1c4 │ │ stc2l 7, cr11, [fp, #784]! @ 0x310 │ │ - stc2l 3, cr9, [r1, #876]! @ 0x36c │ │ + stc2l 4, cr9, [r1, #32]! │ │ stc2l 7, cr11, [fp, #352]! @ 0x160 │ │ @ instruction: 0x01967cb4 │ │ - stc2l 10, cr11, [r0, #988]! @ 0x3dc @ │ │ + stc2l 11, cr11, [r0, #144]! @ 0x90 @ │ │ orrseq r7, r6, r4, asr #16 │ │ stc2l 7, cr11, [fp, #32]! │ │ @ instruction: 0x019677f0 │ │ orrseq r7, r6, r8, ror #15 │ │ orrseq r7, r6, r0, asr #15 │ │ orrseq r7, r6, ip, ror r9 │ │ │ │ @@ -1268564,17 +1268564,17 @@ │ │ add r0, pc, r0 │ │ b 241e6c4 │ │ @ instruction: 0x019672f0 │ │ eorseq r8, r3, r0, ror #23 │ │ orrseq ip, r6, r4, ror #9 │ │ orrseq ip, r6, r0, asr r5 │ │ orrseq ip, r6, r0, asr #8 │ │ - stc2l 13, cr4, [r1, #396]! @ 0x18c │ │ - stc2l 13, cr4, [r0, #224]! @ 0xe0 │ │ - stc2l 12, cr4, [r0, #228]! @ 0xe4 │ │ + stc2l 13, cr4, [r1, #576]! @ 0x240 │ │ + stc2l 13, cr4, [r0, #404]! @ 0x194 │ │ + stc2l 12, cr4, [r0, #408]! @ 0x198 │ │ ldr r5, [pc, #4064] @ 2420198 │ │ add r5, pc, r5 │ │ ldrb r0, [r5] │ │ cmp r0, #0 │ │ bne 241f204 │ │ ldr r6, [pc, #4048] @ 242019c │ │ ldr r1, [pc, #4048] @ 24201a0 │ │ @@ -1268660,15 +1268660,15 @@ │ │ ldr r1, [pc, r1] │ │ ldr r5, [sp, #12] │ │ add r1, r1, #1 │ │ str r1, [r0] │ │ b 241fb20 │ │ stc2l 12, cr12, [r1, #404]! @ 0x194 │ │ stc2l 12, cr10, [r1, #720]! @ 0x2d0 │ │ - stc2l 3, cr9, [r0, #564]! @ 0x234 │ │ + stc2l 3, cr9, [r0, #744]! @ 0x2e8 │ │ ldr r0, [pc, #4084] @ 2420324 │ │ ldr r0, [pc, r0] │ │ cmp r0, #9 │ │ bgt 241fc34 │ │ ldr r0, [pc, #4072] @ 2420328 │ │ ldr r1, [pc, #4072] @ 242032c │ │ add r0, pc, r0 │ │ @@ -1268699,26 +1268699,26 @@ │ │ ldr r1, [pc, r1] │ │ ldr sl, [sp, #12] │ │ add r1, r1, #1 │ │ str r1, [r0] │ │ b 2421790 │ │ orrseq ip, r6, r4, ror #7 │ │ @ instruction: 0x0196c2d4 │ │ - stc2l 1, cr1, [r0, #232]! @ 0xe8 │ │ + stc2l 1, cr1, [r0, #412]! @ 0x19c │ │ orrseq ip, r6, r0, lsr r4 │ │ eorseq r6, r3, ip, lsl r2 │ │ - stc2l 2, cr9, [r0, #852]! @ 0x354 │ │ + stc2l 3, cr9, [r0, #8]! │ │ ldrsheq r7, [r6, r0] │ │ eorseq r8, r3, r0, ror #19 │ │ orrseq ip, r6, r4, ror #5 │ │ orrseq ip, r6, r0, asr r3 │ │ orrseq ip, r6, r0, asr #4 │ │ - stc2l 8, cr6, [r1, #840]! @ 0x348 │ │ - stc2l 11, cr4, [r0, #176]! @ 0xb0 @ │ │ - stc2l 10, cr4, [r0, #180]! @ 0xb4 @ │ │ + stc2l 8, cr6, [r1, #1020]! @ 0x3fc │ │ + stc2l 11, cr4, [r0, #356]! @ 0x164 @ │ │ + stc2l 10, cr4, [r0, #360]! @ 0x168 @ │ │ eorseq r8, r3, r8, lsr #18 │ │ eorseq r8, r3, r8, lsr #18 │ │ ldr r0, [pc, #4064] @ 24203e0 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ce90 │ │ ldr r0, [pc, #4052] @ 24203e4 │ │ @@ -1268795,20 +1268795,20 @@ │ │ stc2l 11, cr12, [r1, #80]! @ 0x50 @ │ │ orrseq r6, r6, r0, ror pc │ │ eorseq r8, r3, r0, ror #16 │ │ orrseq ip, r6, r4, ror #2 │ │ @ instruction: 0x0196c1d0 │ │ orrseq ip, r6, r0, asr #1 │ │ ldc2l 2, cr11, [pc, #460] @ 241f710 │ │ - stc2l 9, cr4, [r0, #360]! @ 0x168 @ │ │ - stc2l 8, cr4, [r0, #724]! @ 0x2d4 │ │ + stc2l 9, cr4, [r0, #450]! @ 0x1c2 @ │ │ + vcmla.f16 q10, q8, q9, #270 │ │ ldrhteq r8, [r3], -r0 │ │ eorseq r8, r3, ip, lsr #15 │ │ - stc2l 9, cr4, [r1, #164]! @ 0xa4 @ │ │ - stc2l 14, cr0, [r0, #460]! @ 0x1cc │ │ + stc2l 9, cr4, [r1, #254]! @ 0xfe @ │ │ + stc2l 14, cr0, [r0, #640]! @ 0x280 │ │ vcmla.f16 d28, d17, d13, #270 │ │ ldr r0, [pc, #4064] @ 2420544 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ce90 │ │ ldr r0, [pc, #4052] @ 2420548 │ │ ldr r0, [pc, r0] │ │ @@ -1268913,31 +1268913,31 @@ │ │ add r3, r2, r7, lsl #3 │ │ mov r2, r6 │ │ bl 270d550 │ │ bl 270db90 │ │ cmp r0, #0 │ │ bne 24203d4 │ │ b 2420378 │ │ - stc2l 14, cr0, [r0, #268]! @ 0x10c │ │ + stc2l 14, cr0, [r0, #448]! @ 0x1c0 │ │ vcmla.f16 q13, , , #270 │ │ vcmla.f16 q14, , , #270 │ │ stc2l 8, cr10, [r1, #620]! @ 0x26c │ │ ldc2l 7, cr4, [pc, #420] @ 241f8d4 │ │ stc2l 13, cr11, [r2, #200]! @ 0xc8 │ │ - stc2l 12, cr14, [r0, #512]! @ 0x200 │ │ + stc2l 12, cr14, [r0, #692]! @ 0x2b4 │ │ stc2l 7, cr12, [r1, #788]! @ 0x314 │ │ - stc2l 12, cr14, [r0, #336]! @ 0x150 │ │ + stc2l 12, cr14, [r0, #516]! @ 0x204 │ │ @ instruction: 0x0196be98 │ │ orrseq r6, r6, r8, lsr #28 │ │ orrseq r6, r6, ip, lsl sp │ │ - vcmla.f16 d20, d0, d28, #270 │ │ + stc2l 8, cr4, [r0, #356]! @ 0x164 │ │ orrseq fp, r6, r0, ror lr │ │ vcmla.f16 q14, , , #270 │ │ orrseq fp, r6, r8, lsr #28 │ │ - stc2l 7, cr4, [r0, #688]! @ 0x2b0 │ │ + stc2l 7, cr4, [r0, #868]! @ 0x364 │ │ @ instruction: 0x0196bddc │ │ orrseq fp, r6, r4, lsl #27 │ │ vcmla.f16 d16, d2, d28, #270 │ │ ldr r0, [pc, #3820] @ 242065c │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ce90 │ │ @@ -1269046,30 +1269046,30 @@ │ │ cmp r0, #0 │ │ mov r7, r8 │ │ bne 2420494 │ │ b 2420434 │ │ orrseq fp, r6, r4, ror sp │ │ orrseq r6, r6, r8, lsl #26 │ │ orrseq r6, r6, ip, lsl ip │ │ - stc2l 7, cr4, [r0, #16]! │ │ + stc2l 7, cr4, [r0, #196]! @ 0xc4 │ │ @ instruction: 0x0196bdd0 │ │ - ldc2l 12, cr12, [pc, #668] @ 241fbd8 │ │ + ldc2l 12, cr12, [pc, #848] @ 241fc8c │ │ orrseq fp, r6, r4, lsl #26 │ │ ldc2l 14, cr8, [pc, #324] @ 241fa88 │ │ @ instruction: 0x0196bcb8 │ │ orrseq fp, r6, r8, lsl #25 │ │ - stc2l 9, cr10, [r0, #376]! @ 0x178 @ │ │ + stc2l 9, cr10, [r0, #466]! @ 0x1d2 @ │ │ orrseq fp, r6, r0, asr ip │ │ orrseq r6, r6, r8, ror #23 │ │ orrseq r6, r6, r4, lsr #22 │ │ - stc2l 5, cr4, [r0, #912]! @ 0x390 │ │ + stc2l 6, cr4, [r0, #68]! @ 0x44 │ │ orrseq fp, r6, r0, lsr sp │ │ stc2l 5, cr12, [r1, #984]! @ 0x3d8 │ │ orrseq fp, r6, r4, ror #23 │ │ - stc2l 11, cr2, [r0, #92]! @ 0x5c @ │ │ + stc2l 11, cr2, [r0, #272]! @ 0x110 @ │ │ orrseq fp, r6, r0, lsr #23 │ │ orrseq r6, r6, r4, lsl sl │ │ ldc2l 12, cr8, [pc, #992] @ 241fd5c │ │ orrseq r6, r6, r8, asr #19 │ │ ldrhteq r8, [r3], -r8 │ │ @ instruction: 0x0196bbbc │ │ orrseq fp, r6, r8, lsr #24 │ │ @@ -1269213,38 +1269213,38 @@ │ │ bhi 24204bc │ │ ldr r0, [pc, #4036] @ 2420b7c │ │ mov r2, #1 │ │ add r0, pc, r0 │ │ str r2, [r0, r1, lsl #2] │ │ ldr r4, [r4] │ │ b 24204fc │ │ - stc2l 4, cr4, [r0, #544]! @ 0x220 │ │ + stc2l 4, cr4, [r0, #724]! @ 0x2d4 │ │ @ instruction: 0x0196bbd4 │ │ stc2l 4, cr12, [r1, #600]! @ 0x258 │ │ orrseq fp, r6, r4, lsl #21 │ │ - stc2l 9, cr2, [r0, #374]! @ 0x176 @ │ │ + stc2l 9, cr2, [r0, #464]! @ 0x1d0 @ │ │ orrseq fp, r6, r4, asr #20 │ │ @ instruction: 0x019668b8 │ │ ldc2l 11, cr8, [pc, #640] @ 241fe6c @ │ │ orrseq r6, r6, r0, ror r8 │ │ eorseq r8, r3, r0, ror #2 │ │ orrseq fp, r6, r4, ror #20 │ │ @ instruction: 0x0196bad0 │ │ orrseq fp, r6, r0, asr #19 │ │ orrseq fp, r6, r0, lsr #19 │ │ orrseq r6, r6, r4, lsr r9 │ │ orrseq r6, r6, r8, asr #16 │ │ - stc2l 3, cr4, [r0, #192]! @ 0xc0 │ │ + stc2l 3, cr4, [r0, #372]! @ 0x174 │ │ @ instruction: 0x0196b9fc │ │ - ldc2l 8, cr12, [pc, #844] @ 241ff64 │ │ + ldc2l 9, cr12, [pc] @ 241fc18 @ │ │ orrseq fp, r6, r0, lsr r9 │ │ ldc2l 10, cr8, [pc, #500] @ 241fe14 @ │ │ orrseq fp, r6, r4, ror #17 │ │ @ instruction: 0x0196b8b4 │ │ - stc2l 5, cr10, [r0, #928]! @ 0x3a0 │ │ + stc2l 6, cr10, [r0, #84]! @ 0x54 │ │ orrseq r6, r6, r8, lsl #14 │ │ ldrshteq r7, [r3], -r8 │ │ @ instruction: 0x0196b8fc │ │ ldr r0, [pc, #3908] @ 2420b80 │ │ ldr r6, [pc, #3908] @ 2420b84 │ │ add r0, pc, r0 │ │ add r6, pc, r6 │ │ @@ -1269372,19 +1269372,19 @@ │ │ mov r2, #1 │ │ add r0, pc, r0 │ │ str r2, [r0, r1, lsl #2] │ │ ldr r4, [r4] │ │ b 24205a4 │ │ orrseq fp, r6, r8, ror #18 │ │ orrseq fp, r6, r8, asr r8 │ │ - stc2l 1, cr4, [r0, #384]! @ 0x180 │ │ - stc2l 0, cr4, [r0, #388]! @ 0x184 │ │ + stc2l 1, cr4, [r0, #564]! @ 0x234 │ │ + stc2l 0, cr4, [r0, #568]! @ 0x238 │ │ eorseq r7, r3, ip, asr pc │ │ eorseq r7, r3, r0, asr pc │ │ - stc2l 0, cr4, [r1, #1016]! @ 0x3f8 │ │ + stc2l 1, cr4, [r1, #172]! @ 0xac │ │ stc2l 1, cr12, [r1, #608]! @ 0x260 │ │ @ instruction: 0x019665f0 │ │ eorseq r7, r3, r0, ror #29 │ │ orrseq fp, r6, r4, ror #15 │ │ orrseq fp, r6, r0, asr r8 │ │ orrseq fp, r6, r0, asr #14 │ │ ldr r0, [pc, #3856] @ 2420d88 │ │ @@ -1269449,15 +1269449,15 @@ │ │ bcs 24216f0 │ │ mov r8, r4 │ │ mov r3, r6 │ │ b 2421748 │ │ orrseq fp, r6, r0, lsr #14 │ │ @ instruction: 0x019666b0 │ │ orrseq r6, r6, r0, lsr #11 │ │ - stc2l 0, cr4, [r0, #704]! @ 0x2c0 │ │ + stc2l 0, cr4, [r0, #884]! @ 0x374 │ │ @ instruction: 0x0196b6fc │ │ ldr r8, [pc, #4040] @ 2420f50 │ │ ldr r0, [pc, #4040] @ 2420f54 │ │ add r8, pc, r8 │ │ ldr r0, [pc, r0] │ │ str r0, [r8] │ │ cmp r0, #1 │ │ @@ -1269467,28 +1269467,28 @@ │ │ ldr r5, [pc, #4016] @ 2420f5c │ │ add r6, pc, r6 │ │ add r5, pc, r5 │ │ b 242000c │ │ orrseq fp, r6, r4, ror #13 │ │ stc2l 0, cr12, [r1, #756]! @ 0x2f4 │ │ orrseq fp, r6, r4, lsr #13 │ │ - stc2l 0, cr4, [r0, #208]! @ 0xd0 │ │ + stc2l 0, cr4, [r0, #388]! @ 0x184 │ │ orrseq fp, r6, r4, ror #12 │ │ orrseq fp, r6, ip, lsl #12 │ │ stc2l 0, cr0, [r2, #768]! @ 0x300 │ │ @ instruction: 0x01966494 │ │ eorseq r7, r3, r4, lsl #27 │ │ orrseq fp, r6, r8, lsl #13 │ │ @ instruction: 0x0196b6f4 │ │ orrseq fp, r6, r4, ror #11 │ │ - stc2l 14, cr3, [r0, #960]! @ 0x3c0 │ │ - stc2l 13, cr3, [r0, #964]! @ 0x3c4 │ │ + stc2l 15, cr3, [r0, #116]! @ 0x74 │ │ + stc2l 14, cr3, [r0, #120]! @ 0x78 │ │ eorseq r7, r3, ip, ror #25 │ │ ldrsbteq r7, [r3], -ip │ │ - stc2l 14, cr3, [r1, #568]! @ 0x238 │ │ + stc2l 14, cr3, [r1, #748]! @ 0x2ec │ │ stc2l 14, cr9, [r1, #492]! @ 0x1ec │ │ ldr r0, [r5, r1, lsl #2] │ │ str r0, [r8] │ │ cmp r0, #0 │ │ ble 24205f8 │ │ mov sl, r4 │ │ ldr r4, [r4] │ │ @@ -1269602,20 +1269602,20 @@ │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 241fffc │ │ orrseq fp, r6, r4, asr #11 │ │ @ instruction: 0x0196b4b4 │ │ - stc2l 13, cr3, [r1, #932]! @ 0x3a4 │ │ - stc2l 12, cr3, [r0, #724]! @ 0x2d4 │ │ + stc2l 14, cr3, [r1, #88]! @ 0x58 │ │ + stc2l 12, cr3, [r0, #904]! @ 0x388 │ │ ldrhteq r7, [r3], -r0 │ │ eorseq r7, r3, r8, lsr #23 │ │ - stc2l 13, cr3, [r1, #328]! @ 0x148 │ │ - stc2l 1, cr14, [r0, #480]! @ 0x1e0 │ │ + stc2l 13, cr3, [r1, #508]! @ 0x1fc │ │ + stc2l 1, cr14, [r0, #660]! @ 0x294 │ │ orrseq r6, r6, ip, ror #6 │ │ @ instruction: 0x0196b4b8 │ │ orrseq fp, r6, ip, lsr #7 │ │ orrseq r6, r6, r4, asr #6 │ │ orrseq r6, r6, r0, asr #6 │ │ ldr r0, [pc, #3992] @ 24211a8 │ │ ldr r1, [pc, #3992] @ 24211ac │ │ @@ -1269731,21 +1269731,21 @@ │ │ bl 270e5d0 │ │ bl 270db90 │ │ cmp r0, #0 │ │ beq 24212dc │ │ ldr r0, [pc, #3948] @ 2421348 │ │ add r0, pc, r0 │ │ b 241e6c4 │ │ - stc2l 9, cr5, [r1, #252]! @ 0xfc @ │ │ + stc2l 9, cr5, [r1, #342]! @ 0x156 @ │ │ orrseq r6, r6, r4, lsr r2 │ │ orrseq r6, r6, r4, lsl r2 │ │ orrseq fp, r6, r4, lsl #5 │ │ orrseq fp, r6, r8, asr r2 │ │ - stc2l 9, cr5, [r1, #66]! @ 0x42 @ │ │ - stc2l 11, cr3, [r0, #960]! @ 0x3c0 @ │ │ + stc2l 9, cr5, [r1, #156]! @ 0x9c @ │ │ + stc2l 12, cr3, [r0, #116]! @ 0x74 │ │ orrseq r6, r6, r0, asr #2 │ │ orrseq fp, r6, r0, lsl r2 │ │ ldr r0, [pc, #4080] @ 24213fc │ │ ldr r1, [pc, #4080] @ 2421400 │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ bl 270e0d0 │ │ @@ -1269780,16 +1269780,16 @@ │ │ bl 270db90 │ │ cmp r0, #0 │ │ beq 2420f00 │ │ ldr r0, [pc, #3968] @ 242141c │ │ add r0, pc, r0 │ │ b 241e6c4 │ │ stc2l 11, cr11, [r1, #996]! @ 0x3e4 @ │ │ - stc2l 11, cr3, [r0, #656]! @ 0x290 @ │ │ - stc2l 0, cr0, [r0, #376]! @ 0x178 │ │ + stc2l 11, cr3, [r0, #836]! @ 0x344 @ │ │ + stc2l 0, cr0, [r0, #556]! @ 0x22c │ │ orrseq fp, r6, r0, asr r3 │ │ eorseq r5, r3, r0, asr #2 │ │ orrseq r6, r6, r0, rrx │ │ orrseq fp, r6, ip, lsr #3 │ │ ldr r0, [pc, #3932] @ 2421420 │ │ movw r3, #2357 @ 0x935 │ │ ldr r2, [pc, #3928] @ 2421424 │ │ @@ -1269820,21 +1269820,21 @@ │ │ str r5, [r3, r1, lsl #2] │ │ add r2, pc, r2 │ │ mov r1, r4 │ │ bl 270e0e0 │ │ ldr r0, [pc, #4024] @ 24214f8 │ │ add r0, pc, r0 │ │ b 24218ac │ │ - stc2l 10, cr3, [r1, #636]! @ 0x27c @ │ │ + stc2l 10, cr3, [r1, #816]! @ 0x330 @ │ │ ldrsbeq r6, [r6, r4] │ │ ldrheq r6, [r6, r4] │ │ orrseq fp, r6, r0, lsr #3 │ │ ldrsheq fp, [r6, r4] │ │ - stc2l 7, cr5, [r1, #700]! @ 0x2bc │ │ - stc2l 10, cr3, [r0, #560]! @ 0x230 @ │ │ + stc2l 7, cr5, [r1, #880]! @ 0x370 │ │ + stc2l 10, cr3, [r0, #740]! @ 0x2e4 @ │ │ orrseq r6, r6, r4 │ │ ldr r0, [pc, #3984] @ 24214fc │ │ movw r3, #2005 @ 0x7d5 │ │ ldr r2, [pc, #3980] @ 2421500 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1269863,48 +1269863,48 @@ │ │ add r2, pc, r2 │ │ mov r1, r4 │ │ bl 270e0e0 │ │ ldr r0, [pc, #4076] @ 24215d4 │ │ add r0, pc, r0 │ │ b 24218ac │ │ orrseq fp, r6, ip, lsr #1 │ │ - ldc2l 0, cr12, [pc, #124] @ 2420674 │ │ - stc2l 10, cr3, [r0, #256]! @ 0x100 @ │ │ + ldc2l 0, cr12, [pc, #304] @ 2420728 │ │ + stc2l 10, cr3, [r0, #436]! @ 0x1b4 @ │ │ ldr r0, [pc, #4056] @ 24215d8 │ │ ldr r0, [pc, r0] │ │ str r0, [r8] │ │ cmp r0, #1 │ │ blt 2420c58 │ │ ldr r6, [pc, #4040] @ 24215dc │ │ mov r7, #10 │ │ ldr r5, [pc, #4036] @ 24215e0 │ │ add r6, pc, r6 │ │ add r5, pc, r5 │ │ b 2420694 │ │ - ldc2l 14, cr15, [pc, #1000] @ 2420a14 │ │ + ldc2l 15, cr15, [pc, #156] @ 24206c8 │ │ orrseq fp, r6, ip, ror #3 │ │ ldrsbteq r4, [r3], -ip │ │ orrseq r5, r6, r4, lsr #30 │ │ orrseq fp, r6, ip, lsr r0 │ │ ldc2l 1, cr8, [pc, #660] @ 24208d4 │ │ - stc2l 9, cr3, [r0, #416]! @ 0x1a0 @ │ │ + stc2l 9, cr3, [r0, #506]! @ 0x1fa @ │ │ orrseq fp, r6, r8 │ │ orrseq sl, r6, ip, asr #31 │ │ - stc2l 15, cr5, [r0, #728]! @ 0x2d8 │ │ - stc2l 9, cr3, [r0, #272]! @ 0x110 @ │ │ + stc2l 15, cr5, [r0, #908]! @ 0x38c │ │ + stc2l 9, cr3, [r0, #362]! @ 0x16a @ │ │ vcmla.f16 d27, d17, d25, #270 │ │ eorseq r4, r3, ip, lsr #30 │ │ orrseq r5, r6, r8, asr pc │ │ ldc2l 1, cr10, [pc, #156] @ 2420700 │ │ orrseq r5, r6, ip, asr #29 │ │ orrseq r5, r6, ip, lsr #29 │ │ orrseq fp, r6, r4, lsl r0 │ │ orrseq sl, r6, r8, ror #29 │ │ - stc2l 12, cr11, [r0, #196]! @ 0xc4 │ │ - vcmla.f16 d19, d16, d0, #270 │ │ + stc2l 12, cr11, [r0, #376]! @ 0x178 │ │ + vcmla.f16 d19, d16, d29, #270 │ │ orrseq r5, r6, r0, lsr #28 │ │ @ instruction: 0x0196ae9c │ │ stc2l 8, cr11, [r1, #504]! @ 0x1f8 │ │ ldr r0, [r5, r1, lsl #2] │ │ str r0, [r8] │ │ cmp r0, #0 │ │ ble 2420c58 │ │ @@ -1270003,16 +1270003,16 @@ │ │ ldr r2, [pc, #4092] @ 2421808 │ │ sub r1, r1, #1 │ │ add r2, pc, r2 │ │ str r1, [r2] │ │ cmp r0, #0 │ │ bgt 2420694 │ │ b 2420c58 │ │ - stc2l 8, cr3, [r0, #192]! @ 0xc0 │ │ - ldc2l 12, cr15, [pc, #936] @ 2420bd4 │ │ + stc2l 8, cr3, [r0, #372]! @ 0x174 │ │ + ldc2l 13, cr15, [pc, #92] @ 2420888 │ │ @ instruction: 0x0196afdc │ │ eorseq r4, r3, ip, asr #27 │ │ orrseq r5, r6, ip, lsr sp │ │ add r1, r7, r0, lsl #1 │ │ mov r4, sl │ │ cmp r1, #32 │ │ bcc 2420684 │ │ @@ -1270021,16 +1270021,16 @@ │ │ ldr r2, [pc, #4028] @ 2421810 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2420684 │ │ orrseq sl, r6, r8, lsr lr │ │ - stc2l 13, cr1, [r0, #508]! @ 0x1fc │ │ - stc2l 7, cr3, [r0, #816]! @ 0x330 │ │ + stc2l 13, cr1, [r0, #688]! @ 0x2b0 │ │ + stc2l 7, cr3, [r0, #996]! @ 0x3e4 │ │ orrseq sl, r6, r4, lsl #28 │ │ orrseq r5, r6, ip, ror #24 │ │ cmp r2, r0 │ │ bcc 241e598 │ │ ldr r1, [pc, #3980] @ 2421814 │ │ mov r4, sl │ │ ldr r0, [pc, #3976] @ 2421818 │ │ @@ -1270044,15 +1270044,15 @@ │ │ ldr r7, [pc, #3952] @ 2421820 │ │ ldr r9, [pc, #3952] @ 2421824 │ │ add sl, pc, sl │ │ add r7, pc, r7 │ │ add r9, pc, r9 │ │ b 24208ec │ │ stc2l 2, cr3, [r2, #52]! @ 0x34 │ │ - stc2l 7, cr3, [r0, #528]! @ 0x210 │ │ + stc2l 7, cr3, [r0, #708]! @ 0x2c4 │ │ stc2l 6, cr11, [r1, #660]! @ 0x294 │ │ eorseq r4, r3, r8, lsr #26 │ │ orrseq r8, r6, r4, asr r5 │ │ ldr r0, [r9, r1, lsl #2] │ │ ldr r1, [pc, #4060] @ 24218bc │ │ add r1, pc, r1 │ │ cmp r0, #0 │ │ @@ -1270101,16 +1270101,16 @@ │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 24208d4 │ │ @ instruction: 0x01965c9c │ │ orrseq sl, r6, r4, lsl #28 │ │ @ instruction: 0x0196acd8 │ │ - stc2l 10, cr11, [r0, #132]! @ 0x84 @ │ │ - stc2l 6, cr3, [r0, #448]! @ 0x1c0 │ │ + stc2l 10, cr11, [r0, #312]! @ 0x138 @ │ │ + stc2l 6, cr3, [r0, #628]! @ 0x274 │ │ cmp r1, r0 │ │ bcc 241e764 │ │ str r8, [sp, #12] │ │ mov r4, sl │ │ ldr r9, [pc, #3948] @ 2421934 │ │ ldr r0, [pc, #3948] @ 2421938 │ │ add r9, pc, r9 │ │ @@ -1270125,26 +1270125,26 @@ │ │ add r8, pc, r8 │ │ add r6, pc, r6 │ │ add r7, pc, r7 │ │ b 2420a54 │ │ orrseq r5, r6, r0, lsl ip │ │ @ instruction: 0x0196ac90 │ │ stc2l 6, cr11, [r1, #456]! @ 0x1c8 │ │ - stc2l 6, cr3, [r0, #144]! @ 0x90 │ │ - ldc2l 10, cr15, [pc, #888] @ 2420d8c @ │ │ + stc2l 6, cr3, [r0, #324]! @ 0x144 │ │ + ldc2l 11, cr15, [pc, #44] @ 2420a40 @ │ │ @ instruction: 0x0196add0 │ │ eorseq r4, r3, r0, asr #23 │ │ orrseq r5, r6, r0, lsr fp │ │ orrseq sl, r6, ip, lsr #24 │ │ - stc2l 11, cr1, [r0, #460]! @ 0x1cc @ │ │ - stc2l 5, cr3, [r0, #768]! @ 0x300 │ │ + stc2l 11, cr1, [r0, #640]! @ 0x280 @ │ │ + stc2l 5, cr3, [r0, #948]! @ 0x3b4 │ │ @ instruction: 0x0196abf8 │ │ orrseq r5, r6, r4, ror #20 │ │ stc2l 0, cr3, [r2, #20]! │ │ - stc2l 5, cr3, [r0, #496]! @ 0x1f0 │ │ + stc2l 5, cr3, [r0, #676]! @ 0x2a4 │ │ stc2l 4, cr11, [r1, #628]! @ 0x274 │ │ eorseq r4, r3, r0, lsr #22 │ │ orrseq r8, r6, ip, asr #6 │ │ ldr r0, [r7, r1, lsl #2] │ │ str r0, [r9] │ │ cmp r0, #0 │ │ ble 2421bb4 │ │ @@ -1270191,15 +1270191,15 @@ │ │ movw r3, #3066 @ 0xbfa │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2420a44 │ │ orrseq sl, r6, r8, ror fp │ │ stc2l 15, cr2, [r2, #596]! @ 0x254 │ │ - stc2l 5, cr3, [r0, #48]! @ 0x30 │ │ + stc2l 5, cr3, [r0, #228]! @ 0xe4 │ │ @ instruction: 0x019682f0 │ │ eorseq r7, r3, r0, asr #5 │ │ cmp r2, r0 │ │ bcc 241e7e4 │ │ str r8, [sp, #12] │ │ mov r4, sl │ │ ldr r1, [pc, #3948] @ 2421aa0 │ │ @@ -1270214,15 +1270214,15 @@ │ │ mov r9, #10 │ │ ldr r7, [pc, #3920] @ 2421aac │ │ ldr r6, [pc, #3920] @ 2421ab0 │ │ add sl, pc, sl │ │ add r7, pc, r7 │ │ add r6, pc, r6 │ │ b 2420b98 │ │ - ldc2l 9, cr15, [pc, #340] @ 2420cc8 @ │ │ + ldc2l 9, cr15, [pc, #430] @ 2420d22 @ │ │ orrseq sl, r6, r0, lsr #25 │ │ eorseq r4, r3, r8, lsl #21 │ │ orrseq sl, r6, r0, lsl #22 │ │ orrseq r5, r6, r4, asr sl │ │ @ instruction: 0x019659fc │ │ orrseq sl, r6, r8, ror #21 │ │ ldr r0, [r6, r1, lsl #2] │ │ @@ -1270271,16 +1270271,16 @@ │ │ mov r2, r7 │ │ movw r3, #3931 @ 0xf5b │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2420b88 │ │ orrseq sl, r6, ip, lsr sl │ │ - stc2l 0, cr5, [r1, #988]! @ 0x3dc │ │ - stc2l 3, cr3, [r0, #848]! @ 0x350 │ │ + stc2l 1, cr5, [r1, #144]! @ 0x90 │ │ + stc2l 4, cr3, [r0, #4]! │ │ ldr r0, [pc, #4076] @ 2421c4c │ │ ldr r0, [pc, r0] │ │ str r0, [r8] │ │ cmp r0, #1 │ │ blt 241e418 │ │ ldr r7, [pc, #4060] @ 2421c50 │ │ mov r9, #10 │ │ @@ -1270288,17 +1270288,17 @@ │ │ ldr r6, [pc, #4056] @ 2421c58 │ │ add r7, pc, r7 │ │ add r5, pc, r5 │ │ add r6, pc, r6 │ │ b 2420cc0 │ │ orrseq r5, r6, ip, asr #18 │ │ @ instruction: 0x0196a9f4 │ │ - ldc2l 9, cr11, [pc, #206] @ 2420d6a @ │ │ - stc2l 3, cr3, [r0, #544]! @ 0x220 │ │ - vcadd.f32 , , q1, #270 │ │ + ldc2l 9, cr11, [pc, #296] @ 2420dc4 @ │ │ + stc2l 3, cr3, [r0, #724]! @ 0x2d4 │ │ + vcadd.f32 , , , #270 │ │ orrseq sl, r6, r4, lsr fp │ │ eorseq r4, r3, r4, lsr #18 │ │ orrseq r5, r6, ip, ror #16 │ │ @ instruction: 0x0196a990 │ │ ldr r0, [r5, r1, lsl #2] │ │ str r0, [r8] │ │ cmp r0, #0 │ │ @@ -1270323,46 +1270323,46 @@ │ │ mov r8, r5 │ │ cmp r9, #10 │ │ mov r4, sl │ │ bcs 2420da4 │ │ mov r1, r9 │ │ b 2420df0 │ │ ldc2l 10, cr7, [pc, #996] @ 2421108 @ │ │ - stc2l 3, cr3, [r0, #144]! @ 0x90 │ │ + stc2l 3, cr3, [r0, #324]! @ 0x144 │ │ orrseq sl, r6, ip, asr r9 │ │ orrseq sl, r6, r4, lsr #18 │ │ add r1, r9, r0, lsl #1 │ │ mov r4, sl │ │ cmp r1, #32 │ │ bcc 2420cb0 │ │ ldr r0, [pc, #4064] @ 2421d24 │ │ mov r2, r6 │ │ movw r3, #4681 @ 0x1249 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2420cb0 │ │ - stc2l 9, cr5, [r0, #28]! @ │ │ - stc2l 2, cr3, [r0, #896]! @ 0x380 │ │ + stc2l 9, cr5, [r0, #118]! @ 0x76 @ │ │ + stc2l 3, cr3, [r0, #52]! @ 0x34 │ │ stc2l 2, cr11, [r1, #4]! │ │ eorseq r4, r3, r4, lsl #17 │ │ @ instruction: 0x019658b0 │ │ @ instruction: 0x0196a8dc │ │ - stc2l 8, cr5, [r0, #632]! @ 0x278 │ │ - stc2l 2, cr3, [r0, #448]! @ 0x1c0 │ │ + vcmla.f16 , q8, , #270 │ │ + stc2l 2, cr3, [r0, #628]! @ 0x274 │ │ orrseq r5, r6, r4, asr r8 │ │ eorseq r7, r3, r0, lsr #32 │ │ orrseq sl, r6, ip, lsl #17 │ │ @ instruction: 0x019657b8 │ │ @ instruction: 0x019657bc │ │ orrseq sl, r6, ip, lsr #16 │ │ orrseq sl, r6, r0, lsl r8 │ │ @ instruction: 0x0196a7fc │ │ - stc2l 14, cr4, [r1, #788]! @ 0x314 │ │ - stc2l 1, cr3, [r0, #592]! @ 0x250 │ │ + stc2l 14, cr4, [r1, #968]! @ 0x3c8 │ │ + stc2l 1, cr3, [r0, #772]! @ 0x304 │ │ orrseq r5, r6, r4, ror #13 │ │ ldr r0, [pc, #4052] @ 2421d80 │ │ mov r1, r9 │ │ mov r2, r6 │ │ movw r3, #4649 @ 0x1229 │ │ add r0, pc, r0 │ │ mov r5, r6 │ │ @@ -1270438,16 +1270438,16 @@ │ │ add r2, pc, r2 │ │ str r1, [r2] │ │ cmp r0, #0 │ │ bgt 2420cc0 │ │ b 241e418 │ │ @ instruction: 0x0196a7b4 │ │ stc2l 1, cr11, [r1, #628]! @ 0x274 │ │ - stc2l 1, cr3, [r0, #288]! @ 0x120 │ │ - ldc2l 6, cr15, [pc, #8] @ 2420f00 │ │ + stc2l 1, cr3, [r0, #468]! @ 0x1d4 │ │ + ldc2l 6, cr15, [pc, #188] @ 2420fb4 │ │ @ instruction: 0x0196a8f4 │ │ eorseq r4, r3, r4, ror #13 │ │ orrseq r5, r6, r4, lsl #12 │ │ ldr r0, [pc, #4016] @ 2421eb8 │ │ ldr r8, [pc, #4016] @ 2421ebc │ │ ldr r2, [pc, #4016] @ 2421ec0 │ │ add r0, pc, r0 │ │ @@ -1270467,16 +1270467,16 @@ │ │ ldr r4, [r5] │ │ b 2421af0 │ │ orrseq sl, r6, r0, asr r7 │ │ orrseq sl, r6, r8, lsl r7 │ │ orrseq r5, r6, ip, lsr #13 │ │ orrseq r5, r6, r4, asr #11 │ │ orrseq sl, r6, ip, ror r7 │ │ - ldc2l 6, cr11, [pc, #28] @ 2420f84 │ │ - stc2l 0, cr3, [r0, #160]! @ 0xa0 │ │ + ldc2l 6, cr11, [pc, #208] @ 2421038 │ │ + stc2l 0, cr3, [r0, #340]! @ 0x154 │ │ orrseq sl, r6, r8, asr r6 │ │ mvn r1, #255 @ 0xff │ │ add r3, r1, r0, lsl #8 │ │ cmp r3, #2560 @ 0xa00 │ │ bcc 2420f9c │ │ ldr r0, [pc, #4008] @ 2421f2c │ │ mov r1, r3 │ │ @@ -1270532,25 +1270532,25 @@ │ │ ldr r0, [pc, #3856] @ 2421f60 │ │ ldr r0, [pc, r0] │ │ str r0, [r6] │ │ ldr r0, [pc, #3848] @ 2421f64 │ │ add r0, pc, r0 │ │ b 241e6c4 │ │ ldc2l 7, cr7, [pc, #740] @ 242134c │ │ - stc2l 15, cr2, [r0, #912]! @ 0x390 │ │ + stc2l 0, cr3, [r0, #68]! @ 0x44 │ │ orrseq sl, r6, ip, lsl r6 │ │ - stc2l 5, cr5, [r0, #888]! @ 0x378 │ │ - stc2l 15, cr2, [r0, #704]! @ 0x2c0 │ │ + stc2l 6, cr5, [r0, #44]! @ 0x2c │ │ + stc2l 15, cr2, [r0, #884]! @ 0x374 │ │ orrseq sl, r6, r0, asr #11 │ │ orrseq r5, r6, r4, lsl #11 │ │ stc2l 14, cr10, [r1, #740]! @ 0x2e4 │ │ eorseq r4, r3, ip, lsr r5 │ │ orrseq sl, r6, r4, lsr #11 │ │ - stc2l 2, cr9, [r0, #816]! @ 0x330 │ │ - stc2l 15, cr2, [r0, #240]! @ 0xf0 │ │ + stc2l 2, cr9, [r0, #996]! @ 0x3e4 │ │ + stc2l 15, cr2, [r0, #420]! @ 0x1a4 │ │ orrseq sl, r6, r4, ror r5 │ │ orrseq sl, r6, ip, ror #10 │ │ @ instruction: 0x019654f4 │ │ orrseq r5, r6, r4, ror #9 │ │ orrseq sl, r6, r8, lsr r5 │ │ orrseq r5, r6, ip, asr #9 │ │ orrseq r5, r6, r0, asr #9 │ │ @@ -1270611,27 +1270611,27 @@ │ │ bl 270e0e0 │ │ ldr r0, [pc, #3596] @ 2421f9c │ │ ldr r0, [pc, r0] │ │ str r0, [r6] │ │ ldr r0, [pc, #3588] @ 2421fa0 │ │ add r0, pc, r0 │ │ b 241e6c4 │ │ - stc2l 2, cr9, [r0, #144]! @ 0x90 │ │ - stc2l 14, cr2, [r0, #592]! @ 0x250 │ │ + stc2l 2, cr9, [r0, #324]! @ 0x144 │ │ + stc2l 14, cr2, [r0, #772]! @ 0x304 │ │ @ instruction: 0x0196a498 │ │ orrseq sl, r6, ip, lsl #9 │ │ orrseq r5, r6, ip, lsl r4 │ │ orrseq r5, r6, r8, lsl r4 │ │ - ldc2l 2, cr15, [pc, #920] @ 2421558 │ │ + ldc2l 3, cr15, [pc, #76] @ 242120c │ │ @ instruction: 0x0196a5dc │ │ eorseq r4, r3, r4, asr #7 │ │ orrseq sl, r6, r8, lsr r4 │ │ ldc2l 12, cr2, [pc, #432] @ 2421380 │ │ - stc2l 13, cr2, [r0, #816]! @ 0x330 │ │ - ldc2l 14, cr12, [pc, #600] @ 2421430 │ │ + stc2l 13, cr2, [r0, #996]! @ 0x3e4 │ │ + ldc2l 14, cr12, [pc, #780] @ 24214e4 │ │ eorseq r4, r3, r8, ror #6 │ │ eorseq r4, r3, r8, ror #6 │ │ sub r1, r0, #1 │ │ cmp r1, #10 │ │ bcc 2421204 │ │ ldr r0, [pc, #4072] @ 24221d8 │ │ movw r3, #2626 @ 0xa42 │ │ @@ -1270714,18 +1270714,18 @@ │ │ ldr r4, [r5] │ │ b 2421ca0 │ │ @ instruction: 0x0196a3d8 │ │ orrseq sl, r6, ip, asr #6 │ │ orrseq r5, r6, r0, ror #5 │ │ @ instruction: 0x019652dc │ │ orrseq sl, r6, r0, lsr #6 │ │ - stc2l 2, cr5, [r0, #920]! @ 0x398 │ │ - stc2l 12, cr2, [r0, #736]! @ 0x2e0 │ │ + stc2l 3, cr5, [r0, #76]! @ 0x4c │ │ + stc2l 12, cr2, [r0, #916]! @ 0x394 │ │ @ instruction: 0x01965298 │ │ - stc2l 12, cr2, [r1, #172]! @ 0xac │ │ + stc2l 12, cr2, [r1, #352]! @ 0x160 │ │ ldr r1, [pc, #3792] @ 2422224 │ │ ldr r1, [pc, r1] │ │ cmp r0, r1 │ │ beq 24213a0 │ │ ldr r7, [pc, #3780] @ 2422228 │ │ ldr r5, [pc, #3780] @ 242222c │ │ add r7, pc, r7 │ │ @@ -1270768,19 +1270768,19 @@ │ │ b 241e6cc │ │ @ instruction: 0x0196a39c │ │ @ instruction: 0x0196a290 │ │ orrseq r5, r6, r8, lsr #4 │ │ orrseq r5, r6, r4, lsr #4 │ │ orrseq sl, r6, r0, ror #4 │ │ stc2l 6, cr2, [r2, #516]! @ 0x204 │ │ - stc2l 11, cr2, [r0, #992]! @ 0x3e0 @ │ │ + stc2l 12, cr2, [r0, #148]! @ 0x94 │ │ @ instruction: 0x019679d8 │ │ ldc2l 3, cr9, [pc, #1020] @ 2421820 │ │ - stc2l 15, cr10, [r0, #244]! @ 0xf4 │ │ - stc2l 11, cr2, [r0, #560]! @ 0x230 @ │ │ + stc2l 15, cr10, [r0, #424]! @ 0x1a8 │ │ + stc2l 11, cr2, [r0, #740]! @ 0x2e4 @ │ │ orrseq r5, r6, r0, lsr r1 │ │ ldr r1, [pc, #3600] @ 2422244 │ │ ldr r1, [pc, r1] │ │ cmp r0, r1 │ │ beq 2421480 │ │ ldr r4, [pc, #3588] @ 2422248 │ │ ldr r5, [pc, #3588] @ 242224c │ │ @@ -1270826,16 +1270826,16 @@ │ │ @ instruction: 0x0196a1b8 │ │ @ instruction: 0x01965094 │ │ orrseq r5, r6, r4 │ │ orrseq r5, r6, ip, lsl r1 │ │ orrseq sl, r6, ip, ror r1 │ │ orrseq sl, r6, ip, ror r2 │ │ stc2l 10, cr8, [r1, #768]! @ 0x300 @ │ │ - vcmla.f16 d20, d1, d7, #270 │ │ - stc2l 10, cr2, [r0, #912]! @ 0x390 @ │ │ + stc2l 8, cr4, [r1, #208]! @ 0xd0 │ │ + stc2l 11, cr2, [r0, #68]! @ 0x44 @ │ │ orrseq r5, r6, r0, rrx │ │ orrseq sl, r6, r0, lsl r1 │ │ orrseq r4, r6, r4, asr #31 │ │ ldrheq sl, [r6, r8] │ │ orrseq r5, r6, r0, ror r0 │ │ ldrsbeq sl, [r6, r4] │ │ orrseq sl, r6, r4, asr r1 │ │ @@ -1270931,28 +1270931,28 @@ │ │ ldr r2, [pc, #4024] @ 2422644 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 24205b4 │ │ stc2l 9, cr10, [r1, #476]! @ 0x1dc @ │ │ - stc2l 9, cr2, [r0, #320]! @ 0x140 @ │ │ + stc2l 9, cr2, [r0, #410]! @ 0x19a @ │ │ @ instruction: 0x01969fd0 │ │ - stc2l 15, cr0, [r0, #60]! @ 0x3c │ │ - stc2l 9, cr2, [r0, #184]! @ 0xb8 @ │ │ + stc2l 15, cr0, [r0, #240]! @ 0xf0 │ │ + stc2l 9, cr2, [r0, #274]! @ 0x112 @ │ │ @ instruction: 0x01969f94 │ │ stc2l 3, cr2, [r2, #708]! @ 0x2c4 │ │ - stc2l 9, cr2, [r0, #80]! @ 0x50 @ │ │ + stc2l 9, cr2, [r0, #170]! @ 0xaa @ │ │ @ instruction: 0x01964ddc │ │ @ instruction: 0x019676fc │ │ stc2l 8, cr10, [r1, #196]! @ 0xc4 │ │ ldrhteq r3, [r3], -r4 │ │ orrseq r9, r6, ip, lsl pc │ │ ldc2l 0, cr7, [pc, #576] @ 2421918 │ │ - stc2l 8, cr2, [r0, #720]! @ 0x2d0 │ │ + vcmla.f16 q9, q8, , #270 │ │ orrseq r9, r6, ip, ror #29 │ │ orrseq r9, r6, r4, ror #29 │ │ orrseq r4, r6, r0, ror lr │ │ orrseq r4, r6, r0, ror #28 │ │ @ instruction: 0x01969eb0 │ │ orrseq r4, r6, r8, asr #28 │ │ ldr r0, [pc, #3920] @ 2422648 │ │ @@ -1271023,19 +1271023,19 @@ │ │ mov r2, #1 │ │ add r0, pc, r0 │ │ str r2, [r0, r1, lsl #2] │ │ ldr r4, [r4] │ │ b 2421868 │ │ orrseq r4, r6, ip, lsr lr │ │ ldc2l 15, cr6, [pc, #896] @ 2421b94 │ │ - vcmla.f16 d18, d0, d4, #270 │ │ + stc2l 8, cr2, [r0, #196]! @ 0xc4 │ │ orrseq r9, r6, r4, lsl lr │ │ orrseq r4, r6, ip, lsr #27 │ │ orrseq r4, r6, r4, ror #25 │ │ - stc2l 7, cr2, [r0, #656]! @ 0x290 │ │ + stc2l 7, cr2, [r0, #836]! @ 0x344 │ │ @ instruction: 0x01969ef0 │ │ ldr r0, [pc, #3936] @ 2422790 │ │ movw r3, #2708 @ 0xa94 │ │ ldr r2, [pc, #3932] @ 2422794 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1271092,22 +1271092,22 @@ │ │ movw r3, #2710 @ 0xa96 │ │ ldr r2, [pc, #4036] @ 24228d8 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2421878 │ │ - stc2l 12, cr0, [r0, #764]! @ 0x2fc │ │ + stc2l 12, cr0, [r0, #944]! @ 0x3b0 │ │ orrseq r9, r6, r8, asr #26 │ │ @ instruction: 0x01964bbc │ │ ldc2l 14, cr6, [pc, #656] @ 2421bc8 │ │ @ instruction: 0x01969cd8 │ │ orrseq r4, r6, ip, ror #24 │ │ orrseq r4, r6, r0, lsl #23 │ │ - stc2l 6, cr2, [r0, #416]! @ 0x1a0 │ │ + stc2l 6, cr2, [r0, #596]! @ 0x254 │ │ orrseq r9, r6, r4, lsr sp │ │ ldr r0, [pc, #3980] @ 24228dc │ │ mov r1, r6 │ │ ldr r2, [pc, #3976] @ 24228e0 │ │ movw r3, #1609 @ 0x649 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1271144,15 +1271144,15 @@ │ │ bl 270db90 │ │ cmp r0, #0 │ │ mov r4, r8 │ │ beq 2420238 │ │ ldr r0, [pc, #3856] @ 2422900 │ │ add r0, pc, r0 │ │ b 241e6c4 │ │ - ldc2l 11, cr10, [pc, #764] @ 2421cf8 @ │ │ + ldc2l 11, cr10, [pc, #944] @ 2421dac @ │ │ orrseq r9, r6, ip, lsl ip │ │ ldr r0, [pc, #3840] @ 2422904 │ │ movw r3, #1654 @ 0x676 │ │ ldr r2, [pc, #3836] @ 2422908 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1271186,19 +1271186,19 @@ │ │ bl 270d9e0 │ │ ldr r0, [pc, #3992] @ 2422a24 │ │ add r0, pc, r0 │ │ b 241e6c4 │ │ ldc2l 13, cr6, [pc, #468] @ 2421c6c │ │ @ instruction: 0x01969bdc │ │ orrseq r9, r6, ip, lsr #23 │ │ - vcmla.f16 q12, q8, q14, #270 │ │ + stc2l 9, cr8, [r0, #50]! @ 0x32 @ │ │ orrseq r9, r6, ip, ror #22 │ │ @ instruction: 0x01964afc │ │ orrseq r4, r6, r8, ror #19 │ │ - stc2l 4, cr2, [r0, #992]! @ 0x3e0 │ │ + stc2l 5, cr2, [r0, #148]! @ 0x94 │ │ orrseq r9, r6, r4, asr #22 │ │ ldr r0, [pc, #3948] @ 2422a28 │ │ movw r3, #1258 @ 0x4ea │ │ ldr r2, [pc, #3944] @ 2422a2c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1271255,15 +1271255,15 @@ │ │ add r0, pc, r0 │ │ ldr r1, [pc, r1] │ │ add r1, r1, #1 │ │ str r1, [r0] │ │ b 2422130 │ │ stc2l 4, cr10, [r1, #964]! @ 0x3c4 │ │ @ instruction: 0x01969ad8 │ │ - stc2l 4, cr2, [r0, #416]! @ 0x1a0 │ │ + stc2l 4, cr2, [r0, #596]! @ 0x254 │ │ ldr r0, [pc, #3744] @ 2422a5c │ │ ldr r0, [pc, r0] │ │ cmp r0, #9 │ │ bgt 2422258 │ │ ldr r0, [pc, #3732] @ 2422a60 │ │ ldr r1, [pc, #3732] @ 2422a64 │ │ add r0, pc, r0 │ │ @@ -1271297,15 +1271297,15 @@ │ │ ldr r9, [sp, #12] │ │ add r1, r1, #1 │ │ str r1, [r0] │ │ b 2422b14 │ │ @ instruction: 0x019649d8 │ │ orrseq r4, r6, r8, asr #17 │ │ orrseq r9, r6, r8, lsr #20 │ │ - stc2l 3, cr2, [r0, #848]! @ 0x350 │ │ + stc2l 4, cr2, [r0, #4]! │ │ stc2l 3, cr10, [r1, #804]! @ 0x324 │ │ orrseq r9, r6, r8, lsr #19 │ │ ldr r0, [pc, #4004] @ 2422c10 │ │ mov r3, #852 @ 0x354 │ │ ldr r2, [pc, #4000] @ 2422c14 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1271371,15 +1271371,15 @@ │ │ ldr r0, [pc, #3984] @ 2422cfc │ │ mov r2, r4 │ │ add r0, pc, r0 │ │ add r0, r0, r1, lsl #3 │ │ add r1, sp, #16 │ │ bl 270e100 │ │ b 241e6cc │ │ - stc2l 2, cr2, [r0, #688]! @ 0x2b0 │ │ + stc2l 2, cr2, [r0, #868]! @ 0x364 │ │ @ instruction: 0x019698d8 │ │ ldc2l 1, cr2, [pc, #64] @ 2421dd0 │ │ sub r2, r2, r1 │ │ add r0, r1, r0, lsl #8 │ │ movw r1, #257 @ 0x101 │ │ ldr r4, [fp, #28] │ │ sub r1, r0, r1 │ │ @@ -1271479,35 +1271479,35 @@ │ │ mov r1, r0 │ │ ldr r0, [pc, #4060] @ 2422efc │ │ ldr r0, [pc, r0] │ │ b 2421afc │ │ orrseq r9, r6, r8, ror r7 │ │ orrseq r4, r6, r8, asr r6 │ │ stc2l 11, cr1, [r2, #324]! @ 0x144 @ │ │ - stc2l 0, cr2, [r0, #800]! @ 0x320 │ │ + stc2l 0, cr2, [r0, #980]! @ 0x3d4 │ │ orrseq r6, r6, ip, lsr #29 │ │ eorseq r5, r3, ip, ror lr │ │ orrseq r9, r6, r4, ror #13 │ │ - stc2l 4, cr10, [r0, #180]! @ 0xb4 │ │ - stc2l 0, cr2, [r0, #496]! @ 0x1f0 │ │ + stc2l 4, cr10, [r0, #360]! @ 0x168 │ │ + stc2l 0, cr2, [r0, #676]! @ 0x2a4 │ │ @ instruction: 0x019696b4 │ │ orrseq r4, r6, r4, lsl r6 │ │ orrseq r4, r6, r8, lsr r6 │ │ orrseq r9, r6, r8, lsl #13 │ │ orrseq r9, r6, ip, lsl #15 │ │ orrseq r4, r6, r0, lsl #12 │ │ orrseq r9, r6, r4, asr r6 │ │ stc2l 15, cr7, [r1, #656]! @ 0x290 │ │ - stc2l 5, cr4, [r0, #728]! @ 0x2d8 │ │ - stc2l 15, cr1, [r0, #544]! @ 0x220 │ │ + stc2l 5, cr4, [r0, #908]! @ 0x38c │ │ + stc2l 15, cr1, [r0, #724]! @ 0x2d4 │ │ orrseq r4, r6, ip, ror #10 │ │ eorseq r5, r3, ip, lsr sp │ │ orrseq r9, r6, r4, lsr #11 │ │ - stc2l 12, cr3, [r1, #380]! @ 0x17c │ │ - stc2l 15, cr1, [r0, #240]! @ 0xf0 │ │ + stc2l 12, cr3, [r1, #560]! @ 0x230 │ │ + stc2l 15, cr1, [r0, #420]! @ 0x1a4 │ │ orrseq r9, r6, r4, ror r5 │ │ orrseq r4, r6, ip, lsr #9 │ │ @ instruction: 0x019644f4 │ │ orrseq r9, r6, r8, asr #10 │ │ orrseq r9, r6, ip, asr #11 │ │ @ instruction: 0x019644bc │ │ orrseq r9, r6, r4, lsl r5 │ │ @@ -1271650,39 +1271650,39 @@ │ │ bhi 2422c28 │ │ ldr r2, [pc, #4088] @ 24231c4 │ │ add r2, pc, r2 │ │ str r4, [r2, r1, lsl #2] │ │ ldr r4, [r8] │ │ b 2422c64 │ │ ldc2l 13, cr1, [pc] @ 24221e0 │ │ - stc2l 14, cr1, [r0, #384]! @ 0x180 │ │ + stc2l 14, cr1, [r0, #564]! @ 0x234 │ │ eorseq r3, r3, r0, lsl r4 │ │ orrseq r9, r6, ip, ror r4 │ │ - stc2l 11, cr3, [r1, #276]! @ 0x114 @ │ │ - stc2l 14, cr1, [r0, #80]! @ 0x50 │ │ + stc2l 11, cr3, [r1, #456]! @ 0x1c8 @ │ │ + stc2l 14, cr1, [r0, #260]! @ 0x104 │ │ orrseq r9, r6, ip, asr #8 │ │ orrseq r4, r6, ip, asr r3 │ │ orrseq r4, r6, r8, asr #7 │ │ orrseq r9, r6, r0, lsr #8 │ │ orrseq r9, r6, r4, lsr #8 │ │ @ instruction: 0x01964390 │ │ orrseq r9, r6, ip, ror #7 │ │ - ldc2l 2, cr14, [pc, #652] @ 24224a0 │ │ + ldc2l 2, cr14, [pc, #832] @ 2422554 │ │ @ instruction: 0x019693b8 │ │ orrseq r4, r6, ip, asr #6 │ │ orrseq r9, r6, r8, lsr r4 │ │ @ instruction: 0x0196939c │ │ orrseq r4, r6, r4, asr r2 │ │ orrseq r4, r6, r4, ror #5 │ │ orrseq r9, r6, ip, lsr r3 │ │ orrseq r9, r6, r0, asr #6 │ │ orrseq r4, r6, ip, lsr #5 │ │ orrseq r9, r6, r8, lsl #6 │ │ ldc2l 11, cr1, [pc, #240] @ 2422330 @ │ │ - stc2l 12, cr1, [r0, #624]! @ 0x270 │ │ + stc2l 12, cr1, [r0, #804]! @ 0x324 │ │ eorseq r3, r3, r8, asr #4 │ │ orrseq r4, r6, r8, lsl #4 │ │ orrseq r9, r6, ip, asr r2 │ │ orrseq r9, r6, r0, ror #5 │ │ @ instruction: 0x019641d0 │ │ orrseq r9, r6, r8, lsr #4 │ │ ldr r0, [pc, #3692] @ 24230cc │ │ @@ -1271822,16 +1271822,16 @@ │ │ cmp r1, #9 │ │ bhi 2422d08 │ │ ldr r2, [pc, #3272] @ 2423148 │ │ add r2, pc, r2 │ │ str r4, [r2, r1, lsl #2] │ │ ldr r4, [r5] │ │ b 2422d44 │ │ - stc2l 1, cr4, [r0, #808]! @ 0x328 │ │ - stc2l 11, cr1, [r0, #624]! @ 0x270 @ │ │ + stc2l 1, cr4, [r0, #988]! @ 0x3dc │ │ + stc2l 11, cr1, [r0, #804]! @ 0x324 @ │ │ orrseq r4, r6, r4, lsl #3 │ │ orrseq r4, r6, r4, lsl r1 │ │ orrseq r9, r6, r4, ror #2 │ │ orrseq r9, r6, r8, ror #4 │ │ ldrsbeq r4, [r6, ip] │ │ orrseq r9, r6, r0, lsr r1 │ │ ldr r0, [pc, #3468] @ 2423240 │ │ @@ -1271894,21 +1271894,21 @@ │ │ sub r6, r0, #1 │ │ cmp r6, #10 │ │ bcs 2422a70 │ │ mov r8, r4 │ │ mov r3, r6 │ │ b 2422ac8 │ │ stc2l 5, cr1, [r2, #180]! @ 0xb4 │ │ - stc2l 10, cr1, [r0, #656]! @ 0x290 @ │ │ + stc2l 10, cr1, [r0, #836]! @ 0x344 @ │ │ orrseq r6, r6, ip, lsl #17 │ │ stc2l 10, cr9, [r1, #712]! @ 0x2c8 @ │ │ - stc2l 10, cr1, [r0, #400]! @ 0x190 @ │ │ + stc2l 10, cr1, [r0, #580]! @ 0x244 @ │ │ @ instruction: 0x01963f94 │ │ @ instruction: 0x01969094 │ │ - ldc2l 15, cr15, [pc, #876] @ 2422938 │ │ + stc2l 0, cr0, [r0, #32]! │ │ ldr r0, [pc, #2728] @ 2423078 │ │ movw r3, #853 @ 0x355 │ │ ldr r2, [pc, #2724] @ 242307c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #2712] @ 2423080 │ │ @@ -1271926,26 +1271926,26 @@ │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #2664] @ 2423090 │ │ ldr r0, [pc, r0] │ │ b 2421cb0 │ │ - stc2l 10, cr1, [r0, #160]! @ 0xa0 @ │ │ - ldc2l 15, cr9, [pc, #924] @ 24229d4 │ │ - stc2l 10, cr1, [r0, #32]! @ │ │ + stc2l 10, cr1, [r0, #340]! @ 0x154 @ │ │ + ldc2l 0, cr10, [pc, #80] @ 2422688 │ │ + stc2l 10, cr1, [r0, #212]! @ 0xd4 @ │ │ orrseq r3, r6, r0, lsl pc │ │ orrseq r9, r6, r8, lsr r0 │ │ ldc2l 1, cr6, [pc, #644] @ 24228cc │ │ - stc2l 9, cr1, [r0, #408]! @ 0x198 @ │ │ - stc2l 9, cr1, [r0, #192]! @ 0xc0 @ │ │ - stc2l 9, cr1, [r0, #168]! @ 0xa8 @ │ │ + stc2l 9, cr1, [r0, #498]! @ 0x1f2 @ │ │ + stc2l 9, cr1, [r0, #282]! @ 0x11a @ │ │ + stc2l 9, cr1, [r0, #258]! @ 0x102 @ │ │ orrseq r8, r6, r8, lsl #31 │ │ ldc2l 7, cr1, [pc, #752] @ 242294c │ │ - stc2l 9, cr1, [r0, #56]! @ 0x38 @ │ │ + stc2l 9, cr1, [r0, #146]! @ 0x92 @ │ │ stc2l 8, cr9, [r1, #228]! @ 0xe4 │ │ ldrhteq r2, [r3], -r8 │ │ ldrhteq r2, [r3], -r8 │ │ orrseq r8, r6, r0, ror #29 │ │ ldr r1, [fp, #16] │ │ ldr r2, [fp, #20] │ │ ldr r1, [r1] │ │ @@ -1272011,28 +1272011,28 @@ │ │ ldr r0, [pc, r0] │ │ str r0, [r6] │ │ ldr r0, [pc, #2636] @ 24231c0 │ │ add r0, pc, r0 │ │ b 241e6c4 │ │ orrseq r8, r6, ip, lsl #30 │ │ ldc2l 7, cr1, [pc, #272] @ 2422894 │ │ - vcmla.f16 d17, d16, d20, #270 │ │ + stc2l 8, cr1, [r0, #836]! @ 0x344 │ │ eorseq r2, r3, r4, asr lr │ │ orrseq r8, r6, r0, asr #29 │ │ orrseq r3, r6, r4, asr #27 │ │ - stc2l 5, cr3, [r1, #324]! @ 0x144 │ │ - vcmla.f16 d17, d0, d16, #270 │ │ + stc2l 5, cr3, [r1, #504]! @ 0x1f8 │ │ + vcmla.f16 , q0, , #270 │ │ orrseq r3, r6, r4, ror sp │ │ orrseq r8, r6, ip, asr #28 │ │ @ instruction: 0x01963cd8 │ │ orrseq r8, r6, ip, asr #27 │ │ orrseq r3, r6, r8, lsr #27 │ │ orrseq r8, r6, r0, lsl lr │ │ orrseq r8, r6, r0, lsl lr │ │ - ldc2l 12, cr13, [pc, #748] @ 2422aa8 │ │ + ldc2l 12, cr13, [pc, #928] @ 2422b5c │ │ @ instruction: 0x01968df0 │ │ ldr r1, [fp, #16] │ │ ldr r2, [fp, #20] │ │ ldr r1, [r1] │ │ ldr r2, [r2] │ │ add r0, r1, r0, lsl #7 │ │ sub r2, r2, r1 │ │ @@ -1272093,31 +1272093,31 @@ │ │ ldr r0, [pc, #2064] @ 24230c4 │ │ ldr r0, [pc, r0] │ │ str r0, [r6] │ │ ldr r0, [pc, #2056] @ 24230c8 │ │ add r0, pc, r0 │ │ b 241e6c4 │ │ stc2l 7, cr9, [r1, #852]! @ 0x354 │ │ - stc2l 7, cr1, [r0, #512]! @ 0x200 │ │ + stc2l 7, cr1, [r0, #692]! @ 0x2b4 │ │ orrseq r3, r6, r0, ror #24 │ │ @ instruction: 0x01968db0 │ │ - stc2l 7, cr1, [r0, #320]! @ 0x140 │ │ - stc2l 7, cr1, [r0, #272]! @ 0x110 │ │ - stc2l 7, cr1, [r0, #32]! │ │ - stc2l 6, cr1, [r0, #1008]! @ 0x3f0 │ │ + stc2l 7, cr1, [r0, #500]! @ 0x1f4 │ │ + stc2l 7, cr1, [r0, #452]! @ 0x1c4 │ │ + stc2l 7, cr1, [r0, #212]! @ 0xd4 │ │ + stc2l 7, cr1, [r0, #164]! @ 0xa4 │ │ orrseq r8, r6, r0, lsr sp │ │ ldc2l 5, cr1, [pc, #400] @ 2422a80 │ │ - stc2l 6, cr1, [r0, #784]! @ 0x310 │ │ + stc2l 6, cr1, [r0, #964]! @ 0x3c4 │ │ stc2l 5, cr9, [r1, #900]! @ 0x384 │ │ eorseq r2, r3, r0, ror #24 │ │ eorseq r2, r3, r0, ror #24 │ │ orrseq r8, r6, r8, lsl #25 │ │ - stc2l 3, cr3, [r1, #584]! @ 0x248 │ │ + stc2l 3, cr3, [r1, #764]! @ 0x2fc │ │ stc2l 6, cr9, [r1, #644]! @ 0x284 │ │ - stc2l 6, cr1, [r0, #304]! @ 0x130 │ │ + stc2l 6, cr1, [r0, #484]! @ 0x1e4 │ │ sub r6, r0, #1 │ │ cmp r6, #10 │ │ bcc 2422938 │ │ ldr r0, [pc, #2280] @ 2423208 │ │ mov r1, r6 │ │ ldr r2, [pc, #2276] @ 242320c │ │ movw r3, #3906 @ 0xf42 │ │ @@ -1272180,23 +1272180,23 @@ │ │ ldr r0, [pc, #2092] @ 242323c │ │ add r0, pc, r0 │ │ b 241e6c4 │ │ orrseq r3, r6, ip, lsr #22 │ │ orrseq r8, r6, ip, ror ip │ │ orrseq r8, r6, r4, lsl ip │ │ orrseq r3, r6, ip, ror #22 │ │ - stc2l 2, cr3, [r1, #984]! @ 0x3d8 │ │ + stc2l 3, cr3, [r1, #140]! @ 0x8c │ │ stc2l 5, cr9, [r1, #904]! @ 0x388 │ │ - stc2l 5, cr1, [r0, #592]! @ 0x250 │ │ + stc2l 5, cr1, [r0, #772]! @ 0x304 │ │ orrseq r3, r6, r4, asr #21 │ │ orrseq r8, r6, r4, asr #23 │ │ orrseq r3, r6, r8, lsr #20 │ │ orrseq r3, r6, r4, lsl #22 │ │ stc2l 15, cr0, [r2, #612]! @ 0x264 │ │ - stc2l 5, cr1, [r0, #64]! @ 0x40 │ │ + stc2l 5, cr1, [r0, #244]! @ 0xf4 │ │ ldc2l 13, cr7, [pc, #188] @ 2422b0c │ │ @ instruction: 0x01963ad4 │ │ orrseq r8, r6, r4, lsr #24 │ │ @ instruction: 0x01963ab4 │ │ @ instruction: 0x01963ab0 │ │ orrseq r3, r6, ip, lsl #21 │ │ orrseq r8, r6, ip, asr fp │ │ @@ -1272303,16 +1272303,16 @@ │ │ ldr r4, [r9] │ │ b 2422e24 │ │ orrseq r3, r6, r8, lsr sl │ │ orrseq r8, r6, ip, lsl #21 │ │ orrseq r8, r6, r0, lsl #21 │ │ orrseq r3, r6, r0, lsl sl │ │ orrseq r3, r6, r8, lsl #20 │ │ - ldc2l 9, cr9, [pc, #390] @ 2422d9e @ │ │ - stc2l 3, cr1, [r0, #912]! @ 0x390 │ │ + ldc2l 9, cr9, [pc, #480] @ 2422df8 @ │ │ + stc2l 4, cr1, [r0, #68]! @ 0x44 │ │ orrseq r3, r6, ip, ror #17 │ │ orrseq r8, r6, r4, lsl sl │ │ @ instruction: 0x019689d0 │ │ orrseq r3, r6, r8, lsr #18 │ │ ldr r0, [pc, #1432] @ 24231c8 │ │ movw r3, #3564 @ 0xdec │ │ ldr r2, [pc, #1428] @ 24231cc │ │ @@ -1272357,22 +1272357,22 @@ │ │ ldr r0, [fp, #28] │ │ add r2, r6, r1, lsl #2 │ │ add r1, sp, #16 │ │ bl 270e2d0 │ │ ldr r0, [pc, #1312] @ 2423204 │ │ add r0, pc, r0 │ │ b 241e6c4 │ │ - stc2l 9, cr3, [r0, #276]! @ 0x114 @ │ │ - stc2l 3, cr1, [r0, #368]! @ 0x170 │ │ - stc2l 2, cr1, [r1, #924]! @ 0x39c │ │ - stc2l 9, cr3, [r0, #92]! @ 0x5c @ │ │ - stc2l 3, cr1, [r0] │ │ + stc2l 9, cr3, [r0, #366]! @ 0x16e @ │ │ + stc2l 3, cr1, [r0, #548]! @ 0x224 │ │ + stc2l 3, cr1, [r1, #80]! @ 0x50 │ │ + stc2l 9, cr3, [r0, #182]! @ 0xb6 @ │ │ + stc2l 3, cr1, [r0, #180]! @ 0xb4 │ │ orrseq r3, r6, r4, ror #17 │ │ stc2l 13, cr0, [r2, #132]! @ 0x84 │ │ - stc2l 2, cr1, [r0, #608]! @ 0x260 │ │ + stc2l 2, cr1, [r0, #788]! @ 0x314 │ │ ldr r0, [pc, #1084] @ 242314c │ │ mov r3, #3136 @ 0xc40 │ │ ldr r2, [pc, #1080] @ 2423150 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #1068] @ 2423154 │ │ @@ -1272414,20 +1272414,20 @@ │ │ add r1, sp, #16 │ │ mov r0, r4 │ │ bl 270e100 │ │ ldr r0, [pc, #964] @ 2423188 │ │ add r0, pc, r0 │ │ b 241e6c4 │ │ orrseq r6, r6, ip, ror r0 │ │ - stc2l 2, cr1, [r0, #256]! @ 0x100 │ │ - stc2l 2, cr1, [r0, #208]! @ 0xd0 │ │ + stc2l 2, cr1, [r0, #436]! @ 0x1b4 │ │ + stc2l 2, cr1, [r0, #388]! @ 0x184 │ │ orrseq r8, r6, r0, lsr #16 │ │ orrseq r8, r6, r4, ror #16 │ │ - stc2l 15, cr2, [r1, #180]! @ 0xb4 │ │ - stc2l 1, cr1, [r0, #1008]! @ 0x3f0 │ │ + stc2l 15, cr2, [r1, #360]! @ 0x168 │ │ + stc2l 2, cr1, [r0, #164]! @ 0xa4 │ │ orrseq r3, r6, r0, asr r7 │ │ ldr r0, [pc, #1252] @ 24232d4 │ │ movw r3, #4001 @ 0xfa1 │ │ ldr r2, [pc, #1248] @ 24232d8 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1272459,17 +1272459,17 @@ │ │ ldr r3, [fp, #40] @ 0x28 │ │ bl 270d9e0 │ │ ldr r0, [pc, #1184] @ 2423314 │ │ add r0, pc, r0 │ │ b 241e6c4 │ │ orrseq r8, r6, r8, lsr #16 │ │ ldc2l 0, cr1, [pc, #368] @ 2422ff4 │ │ - stc2l 1, cr1, [r0, #752]! @ 0x2f0 │ │ - ldc2l 7, cr15, [pc, #220] @ 2422f68 │ │ - stc2l 1, cr1, [r0, #528]! @ 0x210 │ │ + stc2l 1, cr1, [r0, #932]! @ 0x3a4 │ │ + ldc2l 7, cr15, [pc, #400] @ 242301c │ │ + stc2l 1, cr1, [r0, #708]! @ 0x2c4 │ │ orrseq r3, r6, ip, lsr r6 │ │ @ instruction: 0x019687b4 │ │ ldr r0, [pc, #832] @ 24231dc │ │ movw r3, #3565 @ 0xded │ │ ldr r2, [pc, #828] @ 24231e0 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1272488,16 +1272488,16 @@ │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #772] @ 24231f4 │ │ ldr r0, [pc, r0] │ │ b 2422c70 │ │ - stc2l 4, cr9, [r0, #1012]! @ 0x3f4 │ │ - stc2l 1, cr1, [r0, #304]! @ 0x130 │ │ + stc2l 5, cr9, [r0, #168]! @ 0xa8 │ │ + stc2l 1, cr1, [r0, #484]! @ 0x1e4 │ │ orrseq r8, r6, r4, lsl #15 │ │ ldr r0, [pc, #600] @ 2423160 │ │ movw r3, #3137 @ 0xc41 │ │ ldr r2, [pc, #596] @ 2423164 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1272519,16 +1272519,16 @@ │ │ ldr r0, [pc, #540] @ 2423178 │ │ ldr r0, [pc, r0] │ │ b 2422d50 │ │ @ instruction: 0x01963690 │ │ @ instruction: 0x019687f8 │ │ @ instruction: 0x019686dc │ │ orrseq r8, r6, r8, asr #13 │ │ - stc2l 4, cr9, [r0, #68]! @ 0x44 │ │ - stc2l 0, cr1, [r0, #384]! @ 0x180 │ │ + stc2l 4, cr9, [r0, #248]! @ 0xf8 │ │ + stc2l 0, cr1, [r0, #564]! @ 0x234 │ │ orrseq r3, r6, r4, lsl #12 │ │ ldr r0, [pc, #868] @ 24232e8 │ │ movw r3, #4002 @ 0xfa2 │ │ ldr r2, [pc, #864] @ 24232ec │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1272562,205 +1272562,205 @@ │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2422e44 │ │ orrseq r8, r6, r4, lsl #13 │ │ stc2l 0, cr9, [r1, #408]! @ 0x198 │ │ - stc2l 0, cr1, [r0, #96]! @ 0x60 │ │ - ldc2l 4, cr13, [pc, #840] @ 2423370 │ │ + stc2l 0, cr1, [r0, #276]! @ 0x114 │ │ + ldc2l 4, cr13, [pc, #1020] @ 2423424 │ │ orrseq r8, r6, r4, asr #15 │ │ ldrhteq r2, [r3], -r4 │ │ orrseq r3, r6, r4, lsr #10 │ │ orrseq r8, r6, r0, lsr #12 │ │ - ldc2l 5, cr15, [pc, #412] @ 24231d8 │ │ - stc2l 15, cr0, [r0, #720]! @ 0x2d0 │ │ + ldc2l 5, cr15, [pc, #592] @ 242328c │ │ + stc2l 15, cr0, [r0, #900]! @ 0x384 │ │ orrseq r8, r6, ip, ror #11 │ │ orrseq r3, r6, r4, asr r4 │ │ stc2l 9, cr0, [r2, #490]! @ 0x1ea @ │ │ - stc2l 15, cr0, [r0, #432]! @ 0x1b0 │ │ + stc2l 15, cr0, [r0, #612]! @ 0x264 │ │ stc2l 14, cr8, [r1, #564]! @ 0x234 │ │ eorseq r2, r3, r0, lsl r5 │ │ orrseq r5, r6, ip, lsr sp │ │ orrseq r8, r6, r8, ror #10 │ │ stc2l 9, cr0, [r2, #274]! @ 0x112 @ │ │ - stc2l 15, cr0, [r0] │ │ + stc2l 15, cr0, [r0, #180]! @ 0xb4 │ │ orrseq r5, r6, r0, ror #25 │ │ orrseq r8, r6, r8, lsl #10 │ │ orrseq r3, r6, r0, lsr #9 │ │ orrseq r8, r6, r8, lsl #12 │ │ orrseq r8, r6, ip, ror #9 │ │ ldc2l 2, cr5, [pc, #340] @ 24231d4 │ │ - stc2l 10, cr0, [r0, #512]! @ 0x200 @ │ │ + stc2l 10, cr0, [r0, #692]! @ 0x2b4 @ │ │ @ instruction: 0x01968090 │ │ orrseq r8, r6, ip, lsr #1 │ │ - stc2l 7, cr2, [r1, #412]! @ 0x19c │ │ - stc2l 10, cr0, [r0, #272]! @ 0x110 @ │ │ + stc2l 7, cr2, [r1, #592]! @ 0x250 │ │ + stc2l 10, cr0, [r0, #452]! @ 0x1c4 @ │ │ orrseq r8, r6, ip, ror r0 │ │ - stc2l 14, cr2, [r0, #568]! @ 0x238 │ │ - vcmla.f16 q8, q0, q8, #270 │ │ + stc2l 14, cr2, [r0, #748]! @ 0x2ec │ │ + vcmla.f16 d16, d16, d13, #270 │ │ orrseq r2, r6, r4, asr #28 │ │ orrseq r7, r6, r0, lsl #29 │ │ - stc2l 5, cr2, [r1, #236]! @ 0xec │ │ - stc2l 8, cr0, [r0, #96]! @ 0x60 │ │ + stc2l 5, cr2, [r1, #416]! @ 0x1a0 │ │ + vcmla.f16 q8, q0, , #270 │ │ orrseq r7, r6, r0, asr lr │ │ orrseq r2, r6, r8, lsl #27 │ │ @ instruction: 0x01962dd0 │ │ orrseq r7, r6, r4, lsr #28 │ │ orrseq r7, r6, r8, lsr #29 │ │ @ instruction: 0x01962d98 │ │ @ instruction: 0x01967df0 │ │ stc2l 7, cr6, [r1, #284]! @ 0x11c │ │ @ instruction: 0x019633d8 │ │ orrseq r8, r6, r4, asr #9 │ │ orrseq r8, r6, r8, lsl r4 │ │ - stc2l 10, cr2, [r1, #844]! @ 0x34c @ │ │ - stc2l 13, cr0, [r0, #704]! @ 0x2c0 │ │ + stc2l 11, cr2, [r1] @ │ │ + stc2l 13, cr0, [r0, #884]! @ 0x374 │ │ orrseq r3, r6, r8, lsr #6 │ │ @ instruction: 0x019683d0 │ │ - ldc2l 3, cr9, [pc, #268] @ 24231fc │ │ - stc2l 13, cr0, [r0, #400]! @ 0x190 │ │ - ldc2l 2, cr13, [pc, #120] @ 2423170 │ │ + ldc2l 3, cr9, [pc, #448] @ 24232b0 │ │ + stc2l 13, cr0, [r0, #580]! @ 0x244 │ │ + ldc2l 2, cr13, [pc, #300] @ 2423224 │ │ orrseq r8, r6, r0, lsl r5 │ │ eorseq r2, r3, r0, lsl #6 │ │ orrseq r3, r6, r8, asr #4 │ │ orrseq r8, r6, ip, ror #6 │ │ ldc2l 4, cr5, [pc, #852] @ 2423460 │ │ - stc2l 13, cr0, [r0] │ │ + stc2l 13, cr0, [r0, #180]! @ 0xb4 │ │ orrseq r8, r6, r8, lsr r3 │ │ @ instruction: 0x019682fc │ │ - stc2l 2, cr3, [r0, #920]! @ 0x398 │ │ - stc2l 12, cr0, [r0, #736]! @ 0x2e0 │ │ + stc2l 3, cr3, [r0, #76]! @ 0x4c │ │ + stc2l 12, cr0, [r0, #916]! @ 0x394 │ │ stc2l 11, cr8, [r1, #868]! @ 0x364 @ │ │ eorseq r2, r3, ip, asr r2 │ │ orrseq r3, r6, r8, lsl #5 │ │ @ instruction: 0x019682b4 │ │ - stc2l 2, cr3, [r0, #488]! @ 0x1e8 │ │ - stc2l 12, cr0, [r0, #304]! @ 0x130 │ │ + stc2l 2, cr3, [r0, #668]! @ 0x29c │ │ + stc2l 12, cr0, [r0, #484]! @ 0x1e4 │ │ orrseq r3, r6, ip, lsr #4 │ │ orrseq r8, r6, r4, asr r2 │ │ orrseq r3, r6, r8, ror #3 │ │ @ instruction: 0x019682d4 │ │ orrseq r8, r6, r8, lsr r2 │ │ ldrsheq r3, [r6, r0] │ │ - ldc2l 9, cr8, [pc, #62] @ 2423192 @ │ │ - stc2l 3, cr0, [r0, #256]! @ 0x100 │ │ + ldc2l 9, cr8, [pc, #152] @ 24231ec @ │ │ + stc2l 3, cr0, [r0, #436]! @ 0x1b4 │ │ orrseq r2, r6, r8, asr #16 │ │ orrseq r7, r6, r0, ror r9 │ │ orrseq r7, r6, r0, lsr r9 │ │ ldc2l 9, cr4, [pc, #58] @ 24231a2 @ │ │ - stc2l 1, cr0, [r0, #288]! @ 0x120 │ │ + stc2l 1, cr0, [r0, #468]! @ 0x1d4 │ │ orrseq r7, r6, ip, asr r7 │ │ orrseq r7, r6, r8, ror r7 │ │ - stc2l 14, cr1, [r1, #204]! @ 0xcc │ │ - stc2l 1, cr0, [r0, #64]! @ 0x40 │ │ + stc2l 14, cr1, [r1, #384]! @ 0x180 │ │ + stc2l 1, cr0, [r0, #244]! @ 0xf4 │ │ orrseq r7, r6, r8, asr #14 │ │ orrseq r2, r6, r8, lsl #17 │ │ - vcmla.f16 q9, q8, q11, #270 │ │ - stc2l 2, cr0, [r0, #736]! @ 0x2e0 │ │ + stc2l 9, cr2, [r0, #38]! @ 0x26 @ │ │ + stc2l 2, cr0, [r0, #916]! @ 0x394 │ │ stc2l 2, cr6, [r1, #268]! @ 0x10c │ │ stc2l 4, cr0, [r2, #212]! @ 0xd4 │ │ - stc2l 9, cr0, [r0, #344]! @ 0x158 @ │ │ + stc2l 9, cr0, [r0, #434]! @ 0x1b2 @ │ │ @ instruction: 0x01965790 │ │ orrseq r7, r6, ip, asr #31 │ │ - stc2l 13, cr8, [r0, #84]! @ 0x54 │ │ - stc2l 9, cr0, [r0, #200]! @ 0xc8 @ │ │ + stc2l 13, cr8, [r0, #264]! @ 0x108 │ │ + stc2l 9, cr0, [r0, #290]! @ 0x122 @ │ │ @ instruction: 0x01967f9c │ │ @ instruction: 0x01962efc │ │ orrseq r2, r6, r0, lsr #30 │ │ orrseq r7, r6, r0, ror pc │ │ orrseq r8, r6, r4, ror r0 │ │ orrseq r2, r6, r8, ror #29 │ │ orrseq r7, r6, ip, lsr pc │ │ stc2l 9, cr8, [r1, #128]! @ 0x80 @ │ │ orrseq r3, r6, ip, asr #7 │ │ stc2l 4, cr8, [r1, #440]! @ 0x1b8 │ │ - stc2l 4, cr0, [r0, #128]! @ 0x80 │ │ + stc2l 4, cr0, [r0, #308]! @ 0x134 │ │ orrseq r2, r6, r0, asr r9 │ │ orrseq r7, r6, r0, asr sl │ │ @ instruction: 0x019628b4 │ │ - ldc2l 7, cr14, [pc, #412] @ 2423380 │ │ - stc2l 1, cr0, [r0, #720]! @ 0x2d0 │ │ + ldc2l 7, cr14, [pc, #592] @ 2423434 │ │ + stc2l 1, cr0, [r0, #900]! @ 0x384 │ │ orrseq r2, r6, ip, ror #12 │ │ orrseq r7, r6, r4, ror #15 │ │ - stc2l 5, cr8, [r0, #180]! @ 0xb4 │ │ - stc2l 1, cr0, [r0, #496]! @ 0x1f0 │ │ + stc2l 5, cr8, [r0, #360]! @ 0x168 │ │ + stc2l 1, cr0, [r0, #676]! @ 0x2a4 │ │ @ instruction: 0x019677b4 │ │ @ instruction: 0x01962990 │ │ stc2l 14, cr15, [r1, #132]! @ 0x84 │ │ - stc2l 3, cr0, [r0, #608]! @ 0x260 │ │ + stc2l 3, cr0, [r0, #788]! @ 0x314 │ │ stc2l 3, cr8, [r1, #832]! @ 0x340 │ │ ldc2l 5, cr0, [pc, #816] @ 2423540 │ │ - stc2l 7, cr0, [r0, #176]! @ 0xb0 │ │ + stc2l 7, cr0, [r0, #356]! @ 0x164 │ │ ldrsbteq r1, [r3], -r8 │ │ orrseq r7, r6, r0, lsr sp │ │ - stc2l 3, cr2, [r1, #996]! @ 0x3e4 │ │ - stc2l 6, cr0, [r0, #800]! @ 0x320 │ │ + stc2l 4, cr2, [r1, #152]! @ 0x98 │ │ + stc2l 6, cr0, [r0, #980]! @ 0x3d4 │ │ orrseq r7, r6, r0, lsl #26 │ │ orrseq r2, r6, r0, lsl ip │ │ orrseq r2, r6, ip, ror ip │ │ @ instruction: 0x01967cd4 │ │ @ instruction: 0x01967cd8 │ │ orrseq r2, r6, r4, asr #24 │ │ orrseq r7, r6, r0, lsr #25 │ │ - stc2l 10, cr10, [r0, #192]! @ 0xc0 @ │ │ + stc2l 10, cr10, [r0, #372]! @ 0x174 @ │ │ orrseq r3, r6, r0, lsl #3 │ │ @ instruction: 0x019681f0 │ │ orrseq r8, r6, r4, asr #3 │ │ - vcmla.f16 d18, d17, d13, #270 │ │ - stc2l 11, cr0, [r0, #368]! @ 0x170 @ │ │ + stc2l 8, cr2, [r1, #744]! @ 0x2e8 │ │ + stc2l 11, cr0, [r0, #548]! @ 0x224 @ │ │ orrseq r3, r6, r8, lsr #1 │ │ orrseq r8, r6, r8, ror r1 │ │ stc2l 11, cr8, [r1, #388]! @ 0x184 @ │ │ - stc2l 11, cr0, [r0, #48]! @ 0x30 @ │ │ - ldc2l 15, cr12, [pc, #792] @ 2423584 │ │ + stc2l 11, cr0, [r0, #228]! @ 0xe4 @ │ │ + ldc2l 15, cr12, [pc, #972] @ 2423638 │ │ @ instruction: 0x019682b8 │ │ eorseq r2, r3, r8, lsr #1 │ │ orrseq r2, r6, r8, asr #31 │ │ orrseq r8, r6, r4, lsl r1 │ │ - stc2l 5, cr0, [r0, #896]! @ 0x380 │ │ - stc2l 5, cr0, [r0, #848]! @ 0x350 │ │ + stc2l 6, cr0, [r0, #52]! @ 0x34 │ │ + stc2l 6, cr0, [r0, #4]! │ │ orrseq r7, r6, r8, lsl #24 │ │ ldc2l 4, cr0, [pc, #240] @ 242337c │ │ - stc2l 5, cr0, [r0, #624]! @ 0x270 │ │ + stc2l 5, cr0, [r0, #804]! @ 0x324 │ │ stc2l 4, cr8, [r1, #740]! @ 0x2e4 │ │ eorseq r1, r3, r8, lsr fp │ │ eorseq r1, r3, r8, lsr fp │ │ orrseq r7, r6, r0, ror #22 │ │ - ldc2l 10, cr12, [pc, #40] @ 24232cc @ │ │ + ldc2l 10, cr12, [pc, #220] @ 2423380 @ │ │ orrseq r7, r6, r0, lsl #26 │ │ eorseq r1, r3, r8, ror #21 │ │ orrseq r7, r6, ip, asr fp │ │ ldc2l 3, cr0, [pc, #576] @ 24234f4 │ │ - stc2l 4, cr0, [r0, #960]! @ 0x3c0 │ │ - ldc2l 5, cr10, [pc, #744] @ 24235a4 │ │ + stc2l 5, cr0, [r0, #116]! @ 0x74 │ │ + ldc2l 5, cr10, [pc, #924] @ 2423658 │ │ eorseq r1, r3, ip, lsl #21 │ │ eorseq r1, r3, ip, lsl #21 │ │ orrseq r7, r6, r4, ror #21 │ │ orrseq r2, r6, r4, ror sl │ │ orrseq r7, r6, r4, ror #21 │ │ orrseq r7, r6, r8, asr #21 │ │ orrseq r2, r6, r8, asr r9 │ │ stc2l 2, cr8, [r1, #724]! @ 0x2d4 │ │ - stc2l 2, cr0, [r0, #384]! @ 0x180 │ │ + stc2l 2, cr0, [r0, #564]! @ 0x234 │ │ orrseq r2, r6, r0, asr #14 │ │ @ instruction: 0x01967890 │ │ orrseq r7, r6, r8, lsr #16 │ │ - stc2l 0, cr0, [r0, #864]! @ 0x360 │ │ - stc2l 0, cr0, [r0, #816]! @ 0x330 │ │ + stc2l 1, cr0, [r0, #20]! │ │ + stc2l 0, cr0, [r0, #996]! @ 0x3e4 │ │ @ instruction: 0x019676b8 │ │ @ instruction: 0x019676fc │ │ orrseq r2, r6, r0, lsl #15 │ │ - stc2l 13, cr1, [r1, #788]! @ 0x314 │ │ - stc2l 0, cr0, [r0, #592]! @ 0x250 │ │ + stc2l 13, cr1, [r1, #968]! @ 0x3c8 │ │ + stc2l 0, cr0, [r0, #772]! @ 0x304 │ │ orrseq r2, r6, r8, ror #11 │ │ orrseq r7, r6, r0, asr #13 │ │ ldc2l 14, cr15, [lr, #976] @ 0x3d0 │ │ - stc2l 0, cr0, [r0, #336]! @ 0x150 │ │ - stc2l 5, cr10, [r0, #816]! @ 0x330 │ │ + stc2l 0, cr0, [r0, #516]! @ 0x204 │ │ + stc2l 5, cr10, [r0, #996]! @ 0x3e4 │ │ │ │ 02423318 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ beq 2423334 │ │ @@ -1273164,32 +1273164,32 @@ │ │ bl 270da60 │ │ ldr r0, [pc, #84] @ 2423968 │ │ mov r1, #25 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ mov r0, r4 │ │ b 24238bc │ │ - ldc2l 10, cr9, [pc, #280] @ 2423a44 @ │ │ + ldc2l 10, cr9, [pc, #460] @ 2423af8 @ │ │ eorseq r3, r3, ip, lsl r7 │ │ eorseq r3, r3, r8, lsl r7 │ │ stc2l 13, cr10, [r2, #1004]! @ 0x3ec │ │ - stc2l 12, cr5, [r0, #408]! @ 0x198 │ │ - ldc2l 7, cr15, [pc, #420] @ 2423ae4 │ │ + stc2l 12, cr5, [r0, #588]! @ 0x24c │ │ + ldc2l 7, cr15, [pc, #600] @ 2423b98 │ │ ldc2l 9, cr1, [pc, #134] @ 24239ca @ │ │ stc2l 7, cr7, [r1, #708]! @ 0x2c4 │ │ eorseq r3, r3, ip, asr #12 │ │ eorseq r3, r3, r4, lsr r6 │ │ stc2l 13, cr10, [r2, #92]! @ 0x5c │ │ - ldc2l 11, cr9, [pc, #332] @ 2423aa4 @ │ │ - ldc2l 6, cr15, [pc, #532] @ 2423b70 │ │ + ldc2l 11, cr9, [pc, #512] @ 2423b58 @ │ │ + ldc2l 6, cr15, [pc, #712] @ 2423c24 │ │ stc2l 8, cr11, [r1, #336]! @ 0x150 │ │ stc2l 12, cr10, [r2, #588]! @ 0x24c │ │ - stc2l 6, cr15, [r0, #844]! @ 0x34c │ │ - ldc2l 5, cr15, [pc, #1012] @ 2423d60 │ │ - stc2l 3, cr3, [r1] │ │ + stc2l 7, cr15, [r0] │ │ + ldc2l 6, cr15, [pc, #168] @ 2423a14 │ │ + stc2l 3, cr3, [r1, #180]! @ 0xb4 │ │ │ │ 0242396c : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ mov r6, r3 │ │ mov r4, r2 │ │ @@ -1273336,32 +1273336,32 @@ │ │ bl 270da60 │ │ ldr r0, [pc, #84] @ 2423c10 │ │ mov r1, #25 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ mov r0, r4 │ │ b 2423b64 │ │ - ldc2l 7, cr9, [pc, #632] @ 2423e4c │ │ + ldc2l 7, cr9, [pc, #812] @ 2423f00 │ │ eorseq r3, r3, r0, lsr #9 │ │ mlaseq r3, ip, r4, r3 │ │ stc2l 0, cr15, [r1, #816]! @ 0x330 │ │ stc2l 6, cr12, [r2, #996]! @ 0x3e4 │ │ - ldc2l 4, cr15, [pc, #772] @ 2423eec │ │ + ldc2l 4, cr15, [pc, #952] @ 2423fa0 │ │ ldc2l 6, cr1, [pc, #620] @ 2423e58 │ │ stc2l 5, cr7, [r1, #36]! @ 0x24 │ │ ldrsbteq r3, [r3], -r0 │ │ ldrhteq r3, [r3], -r8 │ │ stc2l 15, cr14, [r1, #928]! @ 0x3a0 │ │ - stc2l 9, cr5, [r0, #92]! @ 0x5c @ │ │ - ldc2l 3, cr15, [pc, #884] @ 2423f78 │ │ + stc2l 9, cr5, [r0, #182]! @ 0xb6 @ │ │ + ldc2l 4, cr15, [pc, #40] @ 2423c2c │ │ stc2l 5, cr11, [r1, #688]! @ 0x2b0 │ │ stc2l 15, cr14, [r1, #400]! @ 0x190 │ │ - stc2l 4, cr15, [r0, #172]! @ 0xac │ │ - ldc2l 3, cr15, [pc, #340] @ 2423d68 │ │ - stc2l 0, cr3, [r1, #352]! @ 0x160 │ │ + stc2l 4, cr15, [r0, #352]! @ 0x160 │ │ + ldc2l 3, cr15, [pc, #520] @ 2423e1c │ │ + stc2l 0, cr3, [r1, #532]! @ 0x214 │ │ │ │ 02423c14 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ @@ -1273504,26 +1273504,26 @@ │ │ pop {r4, r5, fp, pc} │ │ ldr r0, [sp, #8] │ │ cmp r0, #0 │ │ beq 2423d24 │ │ mov r0, r4 │ │ bl 270d660 │ │ b 2423d24 │ │ - stc2l 15, cr2, [r1, #676]! @ 0x2a4 │ │ + stc2l 15, cr2, [r1, #856]! @ 0x358 │ │ @ instruction: 0x01966b94 │ │ ldrsbteq r3, [r3], -ip │ │ orrseq r6, r6, ip, ror fp │ │ orrseq r6, r6, r8, ror #22 │ │ - stc2l 3, cr15, [r0, #488]! @ 0x1e8 │ │ - ldc2l 7, cr11, [pc, #920] @ 2424214 │ │ + stc2l 3, cr15, [r0, #668]! @ 0x29c │ │ + ldc2l 8, cr11, [pc, #76] @ 2423ec8 │ │ orrseq fp, r6, r8, lsl r9 │ │ ldc2l 3, cr1, [pc, #648] @ 242410c │ │ - ldc2l 1, cr15, [pc, #84] @ 2423edc │ │ + ldc2l 1, cr15, [pc, #264] @ 2423f90 │ │ ldc2l 0, cr15, [lr, #876] @ 0x36c │ │ - stc2l 14, cr2, [r1, #20]! │ │ + stc2l 14, cr2, [r1, #200]! @ 0xc8 │ │ │ │ 02423e8c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #180 @ 0xb4 │ │ sub sp, sp, #6144 @ 0x1800 │ │ mov r4, r0 │ │ @@ -1274513,15 +1274513,15 @@ │ │ str r0, [sp] │ │ sub r2, fp, #36 @ 0x24 │ │ ldr r0, [pc, #412] @ 2424fa8 │ │ add r3, sp, #1152 @ 0x480 │ │ add r0, pc, r0 │ │ bl 270d550 │ │ b 2424e40 │ │ - stc2l 14, cr0, [r1, #864]! @ 0x360 │ │ + stc2l 15, cr0, [r1, #20]! │ │ stc2l 0, cr7, [r1, #820]! @ 0x334 │ │ mov r0, #5 │ │ sub r1, fp, #3136 @ 0xc40 │ │ str r0, [sp] │ │ sub r2, fp, #36 @ 0x24 │ │ ldr r0, [pc, #372] @ 2424fac │ │ add r3, sp, #124 @ 0x7c │ │ @@ -1274568,74 +1274568,74 @@ │ │ b 2423f70 │ │ ldr r0, [sp, #36] @ 0x24 │ │ add r3, sp, #48 @ 0x30 │ │ cmp r8, r0 │ │ blt 2424a7c │ │ ldr r1, [sp, #20] │ │ b 24244d4 │ │ - stc2l 14, cr0, [r1, #80]! @ 0x50 │ │ + stc2l 14, cr0, [r1, #260]! @ 0x104 │ │ eorseq r2, r3, r8, ror pc │ │ ldrshteq r2, [r3], -r8 │ │ - ldc2l 2, cr9, [pc, #780] @ 2425214 │ │ - ldc2l 4, cr9, [pc, #272] @ 242501c │ │ - stc2l 6, cr1, [r0, #592]! @ 0x250 │ │ + ldc2l 2, cr9, [pc, #960] @ 24252c8 │ │ + ldc2l 4, cr9, [pc, #452] @ 24250d0 │ │ + stc2l 6, cr1, [r0, #772]! @ 0x304 │ │ eorseq r2, r3, r4, asr #27 │ │ eorseq r2, r3, r0, asr #27 │ │ eorseq r2, r3, r8, ror sp │ │ - ldc2l 2, cr9, [pc, #736] @ 2425200 │ │ - stc2l 10, cr2, [r1, #652]! @ 0x28c @ │ │ - ldc2l 2, cr9, [pc, #640] @ 24251a8 │ │ + ldc2l 2, cr9, [pc, #916] @ 24252b4 │ │ + stc2l 10, cr2, [r1, #832]! @ 0x340 @ │ │ + ldc2l 2, cr9, [pc, #820] @ 242525c │ │ ldc2l 6, cr5, [pc, #968] @ 24252f4 │ │ ldc2l 2, cr3, [pc, #832] @ 2425270 │ │ - ldc2l 2, cr9, [pc, #16] @ 2424f44 │ │ - ldc2l 1, cr9, [pc, #608] @ 2425198 │ │ + ldc2l 2, cr9, [pc, #196] @ 2424ff8 │ │ + ldc2l 1, cr9, [pc, #788] @ 242524c │ │ ldc2l 2, cr3, [pc, #304] @ 242506c │ │ - ldc2l 1, cr9, [pc, #512] @ 2425140 │ │ + ldc2l 1, cr9, [pc, #692] @ 24251f4 │ │ ldc2l 2, cr3, [pc, #96] @ 2424fa4 │ │ eorseq r2, r3, r4, lsr #23 │ │ ldc2l 5, cr5, [pc, #440] @ 2425104 │ │ vcmla.f16 q14, , , #270 │ │ stc2l 12, cr4, [fp, #240]! @ 0xf0 │ │ ldc2l 4, cr5, [pc, #1016] @ 2425350 │ │ eorseq r2, r3, r8, ror #21 │ │ - vcmla.f16 d18, d1, d31, #270 │ │ + stc2l 8, cr2, [r1, #368]! @ 0x170 │ │ stc2l 11, cr4, [fp, #832]! @ 0x340 @ │ │ stc2l 11, cr4, [fp, #576]! @ 0x240 @ │ │ eorseq r2, r3, ip, asr #20 │ │ eorseq r2, r3, r4, lsr #20 │ │ @ instruction: 0x0196b1f4 │ │ ldrhteq r2, [r3], -r8 │ │ ldc2l 3, cr5, [pc, #600] @ 24251d4 │ │ - ldc2l 15, cr8, [pc, #16] @ 2424f90 │ │ - ldc2l 0, cr13, [pc, #676] @ 2425228 │ │ - ldc2l 6, cr8, [pc, #280] @ 24250a0 │ │ - ldc2l 6, cr8, [pc, #136] @ 2425014 │ │ - ldc2l 5, cr8, [pc, #1016] @ 2425388 │ │ - ldc2l 4, cr8, [pc, #744] @ 242527c │ │ + ldc2l 15, cr8, [pc, #196] @ 2425044 │ │ + ldc2l 0, cr13, [pc, #856] @ 24252dc │ │ + ldc2l 6, cr8, [pc, #460] @ 2425154 │ │ + ldc2l 6, cr8, [pc, #316] @ 24250c8 │ │ + ldc2l 6, cr8, [pc, #172] @ 242503c │ │ + ldc2l 4, cr8, [pc, #924] @ 2425330 │ │ stc2l 2, cr6, [r1, #852]! @ 0x354 │ │ - ldc2l 4, cr8, [pc, #344] @ 24250f4 │ │ + ldc2l 4, cr8, [pc, #524] @ 24251a8 │ │ stc2l 2, cr6, [r1, #484]! @ 0x1e4 │ │ - ldc2l 3, cr8, [pc, #1000] @ 242538c │ │ + ldc2l 4, cr8, [pc, #156] @ 2425040 │ │ stc2l 2, cr6, [r1, #100]! @ 0x64 │ │ stc2l 1, cr6, [r1, #692]! @ 0x2b4 │ │ stc2l 1, cr6, [r1, #548]! @ 0x224 │ │ stc2l 1, cr6, [r1, #372]! @ 0x174 │ │ - ldc2l 14, cr8, [pc, #192] @ 2425078 │ │ - ldc2l 15, cr12, [pc, #644] @ 2425240 │ │ + ldc2l 14, cr8, [pc, #372] @ 242512c │ │ + ldc2l 15, cr12, [pc, #824] @ 24252f4 │ │ ldc2l 13, cr2, [pc, #880] @ 2425330 │ │ - stc2l 14, cr0, [r0, #640]! @ 0x280 │ │ - ldc2l 10, cr8, [pc, #604] @ 2425224 @ │ │ + stc2l 14, cr0, [r0, #820]! @ 0x334 │ │ + ldc2l 10, cr8, [pc, #784] @ 24252d8 @ │ │ stc2l 5, cr12, [r1, #724]! @ 0x2d4 │ │ stc2l 9, cr4, [fp, #80]! @ 0x50 @ │ │ ldc2l 14, cr2, [pc, #128] @ 2425054 │ │ ldc2l 1, cr5, [pc, #728] @ 24252b0 │ │ ldc2l 13, cr2, [pc, #560] @ 242520c │ │ ldc2l 1, cr5, [pc, #120] @ 2425058 │ │ - stc2l 14, cr0, [r0, #256]! @ 0x100 │ │ - ldc2l 10, cr8, [pc, #220] @ 24250c4 @ │ │ + stc2l 14, cr0, [r0, #436]! @ 0x1b4 │ │ + ldc2l 10, cr8, [pc, #400] @ 2425178 @ │ │ stc2l 6, cr6, [r1, #964]! @ 0x3c4 │ │ │ │ 02424fe8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #116 @ 0x74 │ │ mov r5, r2 │ │ @@ -1275420,54 +1275420,54 @@ │ │ ldr r2, [pc, #140] @ 2425cac │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2425b68 │ │ stc2l 15, cr10, [r2, #340]! @ 0x154 │ │ - ldc2l 3, cr12, [pc, #196] @ 2425d00 │ │ + ldc2l 3, cr12, [pc, #376] @ 2425db4 │ │ stc2l 14, cr10, [r2, #960]! @ 0x3c0 │ │ - stc2l 3, cr0, [r0, #688]! @ 0x2b0 │ │ + stc2l 3, cr0, [r0, #868]! @ 0x364 │ │ stc2l 14, cr10, [r2, #768]! @ 0x300 │ │ - stc2l 0, cr8, [r0, #604]! @ 0x25c │ │ - ldc2l 11, cr13, [pc, #260] @ 2425d54 @ │ │ - stc2l 15, cr3, [r0, #1016]! @ 0x3f8 │ │ - stc2l 10, cr15, [r0, #124]! @ 0x7c @ │ │ - ldc2l 11, cr13, [pc, #484] @ 2425e40 @ │ │ + stc2l 0, cr8, [r0, #784]! @ 0x310 │ │ + ldc2l 11, cr13, [pc, #440] @ 2425e08 @ │ │ + stc2l 0, cr4, [r0, #172]! @ 0xac │ │ + stc2l 10, cr15, [r0, #304]! @ 0x130 @ │ │ + ldc2l 11, cr13, [pc, #664] @ 2425ef4 @ │ │ stc2l 5, cr15, [r1, #772]! @ 0x304 │ │ eorseq r1, r3, ip, ror #22 │ │ - ldc2l 15, cr11, [pc, #676] @ 2425f0c │ │ + ldc2l 15, cr11, [pc, #856] @ 2425fc0 │ │ stc2l 11, cr10, [r2, #416]! @ 0x1a0 @ │ │ - ldc2l 0, cr12, [pc, #244] @ 2425d64 │ │ + ldc2l 0, cr12, [pc, #424] @ 2425e18 │ │ stc2l 11, cr10, [r2, #1008]! @ 0x3f0 @ │ │ eorseq r1, r3, r0, ror #15 │ │ - ldc2l 13, cr11, [pc, #260] @ 2425d80 │ │ + ldc2l 13, cr11, [pc, #440] @ 2425e34 │ │ stc2l 9, cr10, [r2] @ │ │ - ldc2l 13, cr15, [pc, #304] @ 2425db4 │ │ + ldc2l 13, cr15, [pc, #484] @ 2425e68 │ │ vcmla.f16 q13, q1, q8, #270 │ │ - ldc2l 9, cr7, [pc, #126] @ 2425d0a @ │ │ + ldc2l 9, cr7, [pc, #216] @ 2425d64 @ │ │ vcmla.f16 d26, d2, d28, #270 │ │ stc2l 2, cr11, [r1, #116]! @ 0x74 │ │ stc2l 7, cr10, [r2, #416]! @ 0x1a0 │ │ stc2l 5, cr3, [fp, #624]! @ 0x270 │ │ - ldc2l 10, cr11, [pc, #564] @ 2425ed4 @ │ │ + ldc2l 10, cr11, [pc, #744] @ 2425f88 @ │ │ stc2l 6, cr10, [r2, #304]! @ 0x130 │ │ - ldc2l 10, cr15, [pc, #512] @ 2425ea8 @ │ │ + ldc2l 10, cr15, [pc, #692] @ 2425f5c @ │ │ stc2l 5, cr10, [r2, #592]! @ 0x250 │ │ - ldc2l 6, cr7, [pc, #444] @ 2425e6c │ │ + ldc2l 6, cr7, [pc, #624] @ 2425f20 │ │ stc2l 5, cr10, [r2, #368]! @ 0x170 │ │ eorseq r1, r3, r0, lsr #6 │ │ eorseq r1, r3, r8, lsl #6 │ │ ldrshteq r1, [r3], -r4 │ │ ldrsbteq r1, [r3], -r8 │ │ - ldc2l 12, cr11, [pc, #980] @ 242609c │ │ + ldc2l 13, cr11, [pc, #136] @ 2425d50 │ │ stc2l 8, cr10, [r2, #720]! @ 0x2d0 │ │ - ldc2l 13, cr15, [pc] @ 2425cd0 │ │ + ldc2l 13, cr15, [pc, #180] @ 2425d84 │ │ stc2l 8, cr10, [r2, #80]! @ 0x50 │ │ - ldc2l 8, cr7, [pc, #972] @ 24260a4 │ │ + ldc2l 9, cr7, [pc, #64] @ 2425d18 @ │ │ stc2l 7, cr10, [r2, #896]! @ 0x380 │ │ stc2l 7, cr10, [r2, #612]! @ 0x264 │ │ │ │ 02425cdc : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #44 @ 0x2c │ │ @@ -1275598,15 +1275598,15 @@ │ │ ldr r1, [pc, #32] @ 2425f00 │ │ mov r0, r6 │ │ add r1, pc, r1 │ │ bl 270d440 │ │ b 2425e44 │ │ stc2l 13, cr12, [r1, #892]! @ 0x37c │ │ stc2l 9, cr4, [r2, #128]! @ 0x80 @ │ │ - ldc2l 1, cr13, [pc, #660] @ 2426190 │ │ + ldc2l 1, cr13, [pc, #840] @ 2426244 │ │ stc2l 7, cr8, [r2, #904]! @ 0x388 │ │ ldrsbteq r1, [r3], -r4 │ │ ldrsbteq r0, [r3], -r0 │ │ stc2l 13, cr12, [r1, #300]! @ 0x12c │ │ │ │ 02425f08 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ @@ -1275645,15 +1275645,15 @@ │ │ str r1, [r5] │ │ mov r1, #6 │ │ str r2, [r4] │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - stc2l 13, cr0, [r1, #16]! │ │ + stc2l 13, cr0, [r1, #196]! @ 0xc4 │ │ │ │ 02425fac : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r7, r1 │ │ ldr r1, [fp, #8] │ │ mov r4, r3 │ │ @@ -1275758,24 +1275758,24 @@ │ │ bl 270ce60 │ │ ldr r0, [pc, #52] @ 2426180 │ │ add r0, pc, r0 │ │ bl 270ce70 │ │ mov r0, r4 │ │ pop {r4, r5, fp, lr} │ │ b 270ce40 │ │ - ldc2l 4, cr9, [pc, #568] @ 242639c │ │ + ldc2l 4, cr9, [pc, #748] @ 2426450 │ │ stc2l 3, cr4, [r2, #564]! @ 0x234 │ │ - ldc2l 14, cr12, [pc, #20] @ 2426180 │ │ - ldc2l 3, cr11, [pc, #168] @ 2426218 │ │ + ldc2l 14, cr12, [pc, #200] @ 2426234 │ │ + ldc2l 3, cr11, [pc, #348] @ 24262cc │ │ vcmla.f16 q14, , , #270 │ │ - ldc2l 4, cr9, [pc, #328] @ 24262c0 │ │ - stc2l 0, cr5, [r0, #872]! @ 0x368 │ │ - ldc2l 13, cr12, [pc, #804] @ 24264a4 │ │ - ldc2l 2, cr11, [pc, #952] @ 242653c │ │ - ldc2l 2, cr5, [pc, #200] @ 2426250 │ │ + ldc2l 4, cr9, [pc, #508] @ 2426374 │ │ + stc2l 1, cr5, [r0, #28]! │ │ + ldc2l 13, cr12, [pc, #984] @ 2426558 │ │ + ldc2l 3, cr11, [pc, #108] @ 24261f0 │ │ + ldc2l 2, cr5, [pc, #380] @ 2426304 │ │ │ │ 02426184 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r6, r1 │ │ ldr r1, [pc, #80] @ 24261e8 │ │ mov r2, r6 │ │ @@ -1275973,17 +1275973,17 @@ │ │ bl 270da10 │ │ mov r0, r4 │ │ mov r1, #5 │ │ bl 270ceb0 │ │ pop {r4, sl, fp, lr} │ │ mov r0, #0 │ │ bx lr │ │ - ldc2l 12, cr12, [pc, #44] @ 24264d4 │ │ - stc2l 13, cr10, [r0, #776]! @ 0x308 │ │ - stc2l 14, cr10, [r0, #4]! │ │ + ldc2l 12, cr12, [pc, #224] @ 2426588 │ │ + stc2l 13, cr10, [r0, #956]! @ 0x3bc │ │ + stc2l 14, cr10, [r0, #184]! @ 0xb8 │ │ │ │ 024264ac : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ mov r5, r2 │ │ ldr r2, [r0] │ │ mov r9, r1 │ │ @@ -1276167,25 +1276167,25 @@ │ │ add r0, r3, r0 │ │ str r2, [r1, #40] @ 0x28 │ │ ldr r1, [r6] │ │ str r0, [r5, #44] @ 0x2c │ │ mov r0, #0 │ │ str r1, [r5, #32] │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ - stc2l 13, cr10, [r0, #704]! @ 0x2c0 │ │ + stc2l 13, cr10, [r0, #884]! @ 0x374 │ │ stc2l 11, cr2, [r1, #72]! @ 0x48 @ │ │ - ldc2l 9, cr12, [pc, #490] @ 242699a @ │ │ - ldc2l 1, cr15, [pc, #292] @ 24268d8 │ │ - stc2l 11, cr10, [r0, #1008]! @ 0x3f0 @ │ │ - ldc2l 14, cr8, [pc, #796] @ 2426ad8 │ │ - vcadd.f32 q14, , , #270 │ │ - ldc2l 15, cr4, [pc, #344] @ 242691c │ │ - stc2l 13, cr10, [r0] │ │ - ldc2l 10, cr12, [pc, #788] @ 2426ae0 @ │ │ - ldc2l 9, cr12, [pc, #138] @ 242685a @ │ │ + ldc2l 10, cr12, [pc, #136] @ 2426838 @ │ │ + ldc2l 1, cr15, [pc, #472] @ 242698c │ │ + stc2l 12, cr10, [r0, #164]! @ 0xa4 │ │ + ldc2l 14, cr8, [pc, #976] @ 2426b8c │ │ + vcadd.f32 q14, , q15, #270 │ │ + ldc2l 15, cr4, [pc, #524] @ 24269d0 │ │ + stc2l 13, cr10, [r0, #180]! @ 0xb4 │ │ + ldc2l 10, cr12, [pc, #968] @ 2426b94 @ │ │ + ldc2l 9, cr12, [pc, #228] @ 24268b4 @ │ │ orrseq r9, r6, ip, lsr #8 │ │ stc2l 9, cr6, [r1, #314]! @ 0x13a @ │ │ │ │ 024267d4 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ mov r9, r1 │ │ @@ -1276313,20 +1276313,20 @@ │ │ rsb r0, r0, #11 │ │ str r4, [r2, r0, lsl #2] │ │ add r0, r2, r1, lsl #3 │ │ str r3, [r0, #40] @ 0x28 │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ ldc2l 7, cr12, [lr, #32] │ │ - ldc2l 13, cr8, [pc, #608] @ 2426c48 │ │ - ldc2l 6, cr12, [pc, #836] @ 2426d30 │ │ - ldc2l 14, cr14, [pc, #148] @ 2426a84 │ │ + ldc2l 13, cr8, [pc, #788] @ 2426cfc │ │ + ldc2l 6, cr12, [pc, #1016] @ 2426de4 │ │ + ldc2l 14, cr14, [pc, #328] @ 2426b38 │ │ ldc2l 6, cr12, [lr, #336] @ 0x150 │ │ stc2l 7, cr4, [r1, #924]! @ 0x39c │ │ - ldc2l 6, cr12, [pc, #116] @ 2426a70 │ │ + ldc2l 6, cr12, [pc, #296] @ 2426b24 │ │ orrseq r9, r6, r8, lsl #2 │ │ stc2l 6, cr6, [r1, #468]! @ 0x1d4 │ │ │ │ 02426a00 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ mov r4, r0 │ │ @@ -1276454,21 +1276454,21 @@ │ │ mov r0, #10 │ │ rsb r3, r6, #0 │ │ sub r0, r0, r1, lsl #1 │ │ str r3, [r2, r0, lsl #2] │ │ str r1, [r7, #44] @ 0x2c │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - ldc2l 6, cr12, [pc, #860] @ 2426f70 │ │ - stc2l 6, cr12, [r0, #308]! @ 0x134 │ │ - ldc2l 4, cr12, [pc, #660] @ 2426eb0 │ │ - ldc2l 11, cr14, [pc, #996] @ 2427004 @ │ │ - ldc2l 6, cr12, [pc, #140] @ 2426cb0 │ │ - stc2l 7, cr10, [r0, #636]! @ 0x27c │ │ - ldc2l 3, cr12, [pc, #964] @ 2426ff0 │ │ + ldc2l 7, cr12, [pc, #16] @ 2426c24 │ │ + stc2l 6, cr12, [r0, #488]! @ 0x1e8 │ │ + ldc2l 4, cr12, [pc, #840] @ 2426f64 │ │ + ldc2l 12, cr14, [pc, #152] @ 2426cb8 │ │ + ldc2l 6, cr12, [pc, #320] @ 2426d64 │ │ + stc2l 7, cr10, [r0, #816]! @ 0x330 │ │ + ldc2l 4, cr12, [pc, #120] @ 2426ca4 │ │ orrseq r8, r6, r0, ror #29 │ │ stc2l 4, cr6, [r1, #292]! @ 0x124 │ │ │ │ 02426c30 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ @@ -1276553,18 +1276553,18 @@ │ │ nop {0} │ │ nop {0} │ │ nop {0} │ │ andeq r0, r0, r1 │ │ andeq r0, r0, r2 │ │ andeq r0, r0, r3 │ │ andeq r0, r0, r4 │ │ - ldc2l 9, cr8, [pc, #32] @ 2426db8 @ │ │ + ldc2l 9, cr8, [pc, #122] @ 2426e12 @ │ │ stc2l 10, cr15, [r1, #760]! @ 0x2f8 @ │ │ - ldc2l 2, cr12, [pc, #20] @ 2426db4 │ │ - stc2l 6, cr4, [r0, #916]! @ 0x394 │ │ + ldc2l 2, cr12, [pc, #200] @ 2426e68 │ │ + stc2l 7, cr4, [r0, #72]! @ 0x48 │ │ │ │ 02426da0 : │ │ ldr r0, [r0, #44] @ 0x2c │ │ bx lr │ │ │ │ 02426da8 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ @@ -1276644,20 +1276644,20 @@ │ │ add r1, pc, r1 │ │ bl 270db00 │ │ ldr r0, [pc, #40] @ 2426f08 │ │ mov r1, #22 │ │ add r0, pc, r0 │ │ b 2426e28 │ │ ldc2l 1, cr12, [lr, #252] @ 0xfc │ │ - stc2l 15, cr13, [r0, #820]! @ 0x334 │ │ - ldc2l 1, cr12, [pc, #4] @ 2426efc │ │ - vcadd.f32 q15, , , #270 │ │ + stc2l 15, cr13, [r0, #1000]! @ 0x3e8 │ │ + ldc2l 1, cr12, [pc, #184] @ 2426fb0 │ │ + ldc2l 8, cr14, [pc, #584] @ 2427144 │ │ ldc2l 0, cr12, [lr, #732] @ 0x2dc │ │ - stc2l 5, cr6, [r0, #920]! @ 0x398 │ │ - ldc2l 0, cr12, [pc, #484] @ 24270ec │ │ + stc2l 6, cr6, [r0, #76]! @ 0x4c │ │ + ldc2l 0, cr12, [pc, #664] @ 24271a0 │ │ orrseq r8, r6, ip, lsr #23 │ │ stc2l 1, cr6, [r1, #68]! @ 0x44 │ │ │ │ 02426f0c : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r0 │ │ @@ -1276732,20 +1276732,20 @@ │ │ add r1, pc, r1 │ │ bl 270db00 │ │ ldr r0, [pc, #40] @ 2427060 │ │ mov r1, #22 │ │ add r0, pc, r0 │ │ b 2426f88 │ │ ldc2l 15, cr11, [lr, #904] @ 0x388 │ │ - stc2l 14, cr13, [r0, #436]! @ 0x1b4 │ │ - ldc2l 15, cr11, [pc, #644] @ 24272d4 │ │ - ldc2l 7, cr14, [pc, #20] @ 2427068 │ │ + stc2l 14, cr13, [r0, #616]! @ 0x268 │ │ + ldc2l 15, cr11, [pc, #824] @ 2427388 │ │ + ldc2l 7, cr14, [pc, #200] @ 242711c │ │ ldc2l 15, cr11, [lr, #392] @ 0x188 │ │ - stc2l 4, cr6, [r0, #568]! @ 0x238 │ │ - ldc2l 15, cr11, [pc, #132] @ 24270e4 │ │ + stc2l 4, cr6, [r0, #748]! @ 0x2ec │ │ + ldc2l 15, cr11, [pc, #312] @ 2427198 │ │ orrseq r8, r6, r8, asr sl │ │ stc2l 15, cr5, [r1, #740]! @ 0x2e4 │ │ ldc2l 15, cr11, [lr, #552] @ 0x228 │ │ │ │ 02427068 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ @@ -1276831,20 +1276831,20 @@ │ │ ldr r0, [pc, #52] @ 24271e8 │ │ mov r1, #5 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, r4 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ stc2l 0, cr4, [r1, #740]! @ 0x2e4 │ │ - stc2l 13, cr13, [r0, #52]! @ 0x34 │ │ - ldc2l 14, cr11, [pc, #260] @ 24272d8 │ │ - ldc2l 5, cr14, [pc, #660] @ 242746c │ │ + stc2l 13, cr13, [r0, #232]! @ 0xe8 │ │ + ldc2l 14, cr11, [pc, #440] @ 242738c │ │ + ldc2l 5, cr14, [pc, #840] @ 2427520 │ │ stc2l 0, cr4, [r1, #180]! @ 0xb4 │ │ - stc2l 3, cr6, [r0, #136]! @ 0x88 │ │ - ldc2l 13, cr11, [pc, #724] @ 24274b8 │ │ + stc2l 3, cr6, [r0, #316]! @ 0x13c │ │ + ldc2l 13, cr11, [pc, #904] @ 242756c │ │ @ instruction: 0x019688f0 │ │ stc2l 14, cr5, [r1, #308]! @ 0x134 │ │ stc2l 15, cr3, [r1, #644]! @ 0x284 │ │ │ │ 024271ec : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ @@ -1277023,23 +1277023,23 @@ │ │ add r0, r5, r0, lsl #3 │ │ rsb r1, r1, #0 │ │ str r1, [r0, #40] @ 0x28 │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ stc2l 7, cr13, [r1, #304]! @ 0x130 │ │ stc2l 13, cr1, [r1, #840]! @ 0x348 │ │ - ldc2l 12, cr11, [pc, #724] @ 242779c │ │ - ldc2l 4, cr14, [pc, #36] @ 24274f0 │ │ + ldc2l 12, cr11, [pc, #904] @ 2427850 │ │ + ldc2l 4, cr14, [pc, #216] @ 24275a4 │ │ stc2l 5, cr13, [r1, #640]! @ 0x280 │ │ - ldc2l 1, cr8, [pc, #572] @ 2427710 │ │ - ldc2l 11, cr11, [pc, #36] @ 24274fc @ │ │ - ldc2l 2, cr4, [pc, #120] @ 2427554 │ │ + ldc2l 1, cr8, [pc, #752] @ 24277c4 │ │ + ldc2l 11, cr11, [pc, #216] @ 24275b0 @ │ │ + ldc2l 2, cr4, [pc, #300] @ 2427608 │ │ stc2l 6, cr13, [r1, #624]! @ 0x270 │ │ - ldc2l 13, cr11, [pc, #532] @ 24276f8 │ │ - ldc2l 12, cr11, [pc, #20] @ 24274fc │ │ + ldc2l 13, cr11, [pc, #712] @ 24277ac │ │ + ldc2l 12, cr11, [pc, #200] @ 24275b0 │ │ orrseq r8, r6, r4, lsl #14 │ │ stc2l 12, cr5, [r1, #372]! @ 0x174 │ │ │ │ 024274ec : │ │ ldr r3, [r1] │ │ mov ip, r0 │ │ mov r0, #0 │ │ @@ -1277363,15 +1277363,15 @@ │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ eorseq r3, r1, r4, lsr #24 │ │ eorseq r3, r1, r0, lsr #24 │ │ eorseq r3, r1, r0, lsl #25 │ │ ldrhteq pc, [r2], -r0 @ │ │ orrseq r8, r6, r8, asr r2 │ │ - ldc2l 14, cr13, [pc, #128] @ 2427a50 │ │ + ldc2l 14, cr13, [pc, #308] @ 2427b04 │ │ eorseq pc, r2, r4, asr #12 │ │ mlaseq r2, r8, r5, pc @ │ │ eorseq r3, r1, r0, lsl #21 │ │ │ │ 024279d8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -1277461,15 +1277461,15 @@ │ │ strb sl, [r8, r1] │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ eorseq r3, r1, r4, lsr #21 │ │ eorseq r3, r1, r4, lsl sl │ │ eorseq pc, r2, r8, asr #9 │ │ orrseq r8, r6, ip, rrx │ │ - ldc2l 12, cr13, [pc, #208] @ 2427c20 │ │ + ldc2l 12, cr13, [pc, #388] @ 2427cd4 │ │ eorseq pc, r2, r8, asr r4 @ │ │ ldrhteq pc, [r2], -r4 @ │ │ │ │ 02427b54 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #276 @ 0x114 │ │ @@ -1277848,29 +1277848,29 @@ │ │ mov r0, #129 @ 0x81 │ │ mov r2, sl │ │ add r1, pc, r1 │ │ bl 2428188 │ │ mov r0, #129 @ 0x81 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 6, cr3, [pc, #260] @ 2428258 │ │ + ldc2l 6, cr3, [pc, #440] @ 242830c │ │ eorseq r3, r1, r0, asr #16 │ │ eorseq r3, r1, r8, lsl #16 │ │ ldrshteq r3, [r1], -r0 │ │ - ldc2l 3, cr3, [pc, #148] @ 24281f8 │ │ - ldc2l 8, cr3, [pc, #748] @ 2428454 │ │ - ldc2l 3, cr3, [pc, #900] @ 24284f0 │ │ - ldc2l 2, cr3, [pc, #116] @ 24281e4 │ │ - ldc2l 1, cr3, [pc, #676] @ 2428418 │ │ + ldc2l 3, cr3, [pc, #328] @ 24282ac │ │ + vcadd.f32 , , q12, #270 │ │ + ldc2l 4, cr3, [pc, #56] @ 24281a4 │ │ + ldc2l 2, cr3, [pc, #296] @ 2428298 │ │ + ldc2l 1, cr3, [pc, #856] @ 24284cc │ │ eorseq r3, r1, r4, ror #11 │ │ ldc2l 2, cr13, [lr, #260] @ 0x104 │ │ eorseq r3, r1, r0, lsl r5 │ │ ldrshteq r3, [r1], -r4 │ │ - ldc2l 1, cr3, [pc, #836] @ 24284cc │ │ - ldc2l 1, cr3, [pc, #548] @ 24283b0 │ │ + ldc2l 1, cr3, [pc, #1016] @ 2428580 │ │ + ldc2l 1, cr3, [pc, #728] @ 2428464 │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ ldr r8, [r2, #8] │ │ cmp r8, #0 │ │ beq 2428290 │ │ ldr ip, [pc, #244] @ 2428298 │ │ ldr ip, [pc, ip] │ │ @@ -1277934,15 +1277934,15 @@ │ │ mov r1, r7 │ │ mov r0, r6 │ │ pop {r4, r5, r6, r7, r8, r9, fp, lr} │ │ b 270d930 │ │ ldrshteq r3, [r1], -r0 │ │ eorseq lr, r2, ip, lsl sp │ │ @ instruction: 0x019678bc │ │ - ldc2l 4, cr13, [pc, #416] @ 242844c │ │ + ldc2l 4, cr13, [pc, #596] @ 2428500 │ │ eorseq lr, r2, ip, lsl #25 │ │ eorseq lr, r2, r0, ror ip │ │ eorseq r3, r1, r8, asr #2 │ │ │ │ 024282b4 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ @@ -1277981,18 +1277981,18 @@ │ │ mov r0, sp │ │ str r1, [sp, #32] │ │ str r6, [sp, #28] │ │ str r7, [sp, #24] │ │ bl 270e8a0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 3, cr3, [pc, #268] @ 242846c │ │ + ldc2l 3, cr3, [pc, #448] @ 2428520 │ │ stc2l 0, cr12, [r1, #344]! @ 0x158 │ │ stc2l 9, cr0, [r1, #244]! @ 0xf4 @ │ │ - ldc2l 12, cr12, [pc, #368] @ 24284dc │ │ + ldc2l 12, cr12, [pc, #548] @ 2428590 │ │ stc2l 11, cr5, [r2, #460]! @ 0x1cc @ │ │ │ │ 0242836c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d9} │ │ @@ -1278934,15 +1278934,15 @@ │ │ ldr r0, [pc, #4028] @ 242a1dc │ │ movw r3, #1250 @ 0x4e2 │ │ ldr r2, [pc, #4024] @ 242a1e0 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ b 242910c │ │ - ldc2l 2, cr7, [pc, #400] @ 24293cc │ │ + ldc2l 2, cr7, [pc, #580] @ 2429480 │ │ orrseq r7, r6, r4, asr r8 │ │ orrseq r7, r6, r0, asr #16 │ │ @ instruction: 0x019679d4 │ │ orrseq r7, sl, r8, lsl #5 │ │ orrseq r7, r6, r0, lsl #16 │ │ orrseq r7, r6, r0, lsl #17 │ │ orrseq r7, sl, r4, lsr #11 │ │ @@ -1279100,38 +1279100,38 @@ │ │ sub r0, r0, #1 │ │ add r2, pc, r2 │ │ str r0, [r2] │ │ cmp r1, r0 │ │ ble 2429090 │ │ b 2429738 │ │ stc2l 0, cr2, [r2, #420]! @ 0x1a4 │ │ - ldc2l 1, cr13, [pc, #904] @ 242985c │ │ + ldc2l 2, cr13, [pc, #60] @ 2429510 │ │ ldr r1, [pc, #3972] @ 242a45c │ │ mov r7, r0 │ │ add r0, sp, #86 @ 0x56 │ │ mov r2, #15 │ │ add r1, pc, r1 │ │ mov r3, #8 │ │ b 2429d18 │ │ orrseq r7, r6, r4, lsr r7 │ │ orrseq r2, sl, r4, ror r3 │ │ stc2l 15, cr1, [r2, #964]! @ 0x3c4 │ │ - ldc2l 1, cr13, [pc, #424] @ 24296a8 │ │ + ldc2l 1, cr13, [pc, #604] @ 242975c │ │ stc2l 15, cr1, [r2, #772]! @ 0x304 │ │ - ldc2l 1, cr13, [pc, #232] @ 24295f0 │ │ - stc2l 5, cr14, [r0, #172]! @ 0xac │ │ - ldc2l 1, cr13, [pc, #40] @ 2429538 │ │ - stc2l 5, cr14, [r0, #12]! │ │ - ldc2l 0, cr13, [pc, #904] @ 24298a0 │ │ + ldc2l 1, cr13, [pc, #412] @ 24296a4 │ │ + stc2l 5, cr14, [r0, #352]! @ 0x160 │ │ + ldc2l 1, cr13, [pc, #220] @ 24295ec │ │ + stc2l 5, cr14, [r0, #192]! @ 0xc0 │ │ + ldc2l 1, cr13, [pc, #60] @ 2429554 │ │ stc2l 1, cr14, [r1, #820]! @ 0x334 │ │ orrseq r7, r6, ip, lsl r6 │ │ orrseq r7, sl, r4, ror r0 │ │ - ldc2l 0, cr13, [pc, #508] @ 2429724 │ │ - ldc2l 0, cr13, [pc, #520] @ 2429734 │ │ - ldc2l 15, cr2, [pc, #816] @ 2429860 │ │ + ldc2l 0, cr13, [pc, #688] @ 24297d8 │ │ + ldc2l 0, cr13, [pc, #700] @ 24297e8 │ │ + ldc2l 15, cr2, [pc, #996] @ 2429914 │ │ stc2l 14, cr1, [r2, #200]! @ 0xc8 │ │ ldr r0, [pc, #3880] @ 242a460 │ │ mov r1, r4 │ │ ldr r2, [pc, #3876] @ 242a464 │ │ movw r3, #2071 @ 0x817 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1279226,15 +1279226,15 @@ │ │ b 242cd1c │ │ orrseq r7, r6, r0, ror r5 │ │ eorseq lr, r2, ip, lsl #16 │ │ orrseq r8, sp, r4, asr #8 │ │ stc2l 0, cr14, [r1, #852]! @ 0x354 │ │ orrseq r7, r6, r4, lsr #10 │ │ @ instruction: 0x019d83f4 │ │ - ldc2l 15, cr12, [pc, #600] @ 2429924 │ │ + ldc2l 15, cr12, [pc, #780] @ 24299d8 │ │ ldr r1, [pc, #4088] @ 242a6c8 │ │ movw r0, #5000 @ 0x1388 │ │ ldr r1, [pc, r1] │ │ cmp r1, r0 │ │ bne 2429738 │ │ mov r0, r6 │ │ bl 270d2b0 │ │ @@ -1279301,15 +1279301,15 @@ │ │ ldr r5, [pc, #4052] @ 242a7b0 │ │ ldr r4, [pc, #4052] @ 242a7b4 │ │ add r8, pc, r8 │ │ add r5, pc, r5 │ │ add r4, pc, r4 │ │ mov r6, r5 │ │ b 24298a8 │ │ - stc2l 4, cr12, [r0, #108]! @ 0x6c │ │ + stc2l 4, cr12, [r0, #288]! @ 0x120 │ │ @ instruction: 0x0196c494 │ │ orrseq r7, r6, ip, lsl #10 │ │ ldc2l 6, cr10, [lr, #612] @ 0x264 │ │ @ instruction: 0x019674d8 │ │ ldc2l 6, cr10, [lr, #420] @ 0x1a4 │ │ orrseq r7, r6, r8, asr r3 │ │ ldr r7, [pc, #4004] @ 242a7b8 │ │ @@ -1279536,27 +1279536,27 @@ │ │ str r4, [fp, #-52] @ 0xffffffcc │ │ b 2429cf4 │ │ ldc2l 3, cr10, [lr, #604] @ 0x25c │ │ orrseq r7, r6, ip, ror r0 │ │ stc2l 9, cr5, [r2, #404]! @ 0x194 @ │ │ orrseq r6, sl, r4, lsr lr │ │ stc2l 9, cr5, [r2, #268]! @ 0x10c @ │ │ - stc2l 8, cr4, [r0, #472]! @ 0x1d8 │ │ + vcmla.f16 d20, d16, d19, #270 │ │ orrseq r6, r6, ip, ror #31 │ │ - vcmla.f16 q10, q0, q3, #270 │ │ + stc2l 8, cr4, [r0, #460]! @ 0x1cc │ │ orrseq r6, sl, ip, ror #27 │ │ @ instruction: 0x01966f98 │ │ - ldc2l 10, cr12, [pc, #28] @ 2429bd4 @ │ │ + ldc2l 10, cr12, [pc, #208] @ 2429c88 @ │ │ orrseq r6, sl, r0, ror #19 │ │ - ldc2l 9, cr12, [pc, #414] @ 2429d5e @ │ │ + ldc2l 9, cr12, [pc, #504] @ 2429db8 @ │ │ @ instruction: 0x019a69b4 │ │ orrseq r6, r6, ip, lsr #30 │ │ - ldc2l 9, cr12, [pc, #340] @ 2429d20 @ │ │ + ldc2l 9, cr12, [pc, #430] @ 2429d7a @ │ │ @ instruction: 0x019d7d94 │ │ - ldc2l 9, cr12, [pc, #228] @ 2429cb8 @ │ │ + ldc2l 9, cr12, [pc, #318] @ 2429d12 @ │ │ orrseq r7, sp, r8, ror #26 │ │ orrseq r6, r6, r0, asr #29 │ │ ldr r0, [pc, #4092] @ 242abdc │ │ mov r1, r4 │ │ ldr sl, [pc, #4088] @ 242abe0 │ │ movw r3, #2111 @ 0x83f │ │ add r0, pc, r0 │ │ @@ -1279660,26 +1279660,26 @@ │ │ stc2l 2, cr4, [r1, #480]! @ 0x1e0 │ │ stc2l 2, cr4, [r1, #320]! @ 0x140 │ │ orrseq r6, sl, r8, lsr #18 │ │ eorseq lr, r2, r0, lsl #2 │ │ orrseq r6, r6, r0, asr #28 │ │ orrseq r6, r6, r4, lsr lr │ │ orrseq r6, sl, r4, lsl #24 │ │ - vcadd.f32 d28, d31, d7, #270 │ │ - vcadd.f32 d28, d31, d10, #270 │ │ + ldc2l 8, cr12, [pc, #720] @ 242a064 │ │ + ldc2l 8, cr12, [pc, #732] @ 242a074 │ │ stc2l 7, cr5, [r2, #376]! @ 0x178 │ │ orrseq r6, sl, r4, ror #16 │ │ orrseq r6, sl, ip, lsr r8 │ │ @ instruction: 0x019a67fc │ │ orrseq r6, r6, ip, lsl sp │ │ orrseq r6, r6, r8, lsl #30 │ │ @ instruction: 0x01966cf4 │ │ @ instruction: 0x01966cf0 │ │ orrseq r1, sl, ip, lsr #18 │ │ - ldc2l 7, cr12, [pc, #376] @ 2429f38 │ │ + ldc2l 7, cr12, [pc, #556] @ 2429fec │ │ stc2l 5, cr1, [r2, #676]! @ 0x2a4 │ │ orrseq r6, r6, r0, ror lr │ │ ldr r1, [pc, #4016] @ 242ad7c │ │ add r4, sp, #86 @ 0x56 │ │ add r1, pc, r1 │ │ mov r0, r4 │ │ mov r2, #15 │ │ @@ -1279796,16 +1279796,16 @@ │ │ bl 270d9d0 │ │ cmp r0, #0 │ │ beq 242c320 │ │ add r4, sp, #86 @ 0x56 │ │ b 2429de0 │ │ stc2l 5, cr1, [r2, #452]! @ 0x1c4 │ │ orrseq r6, r6, r8, lsr lr │ │ - stc2l 10, cr13, [r0, #876]! @ 0x36c @ │ │ - stc2l 10, cr13, [r0, #716]! @ 0x2cc @ │ │ + stc2l 11, cr13, [r0, #32]! @ │ │ + stc2l 10, cr13, [r0, #896]! @ 0x380 @ │ │ @ instruction: 0x01966bf0 │ │ @ instruction: 0x019d7abc │ │ sub r1, r7, #1 │ │ str r1, [fp, #-52] @ 0xffffffcc │ │ cmp r1, #20 │ │ bcc 2429fe4 │ │ ldr r0, [pc, #3844] @ 242aed8 │ │ @@ -1279855,18 +1279855,18 @@ │ │ b 242a278 │ │ orrseq r6, r6, r0, lsr #23 │ │ sub r6, r7, #1 │ │ mov sl, r7 │ │ mov r9, #0 │ │ b 242a0dc │ │ ldc2l 14, cr9, [lr, #436] @ 0x1b4 │ │ - ldc2l 5, cr12, [pc, #1000] @ 242a488 │ │ + ldc2l 6, cr12, [pc, #156] @ 242a13c │ │ orrseq r6, r6, r8, lsr #25 │ │ ldc2l 14, cr9, [lr, #164] @ 0xa4 │ │ - ldc2l 5, cr12, [pc, #728] @ 242a384 │ │ + ldc2l 5, cr12, [pc, #908] @ 242a438 │ │ orrseq r6, r6, r0, ror #24 │ │ ldr r0, [pc, #3948] @ 242b020 │ │ mov r1, r9 │ │ mov r2, r8 │ │ movw r3, #2303 @ 0x8ff │ │ add r0, pc, r0 │ │ bl 270da30 │ │ @@ -1279895,22 +1279895,22 @@ │ │ bhi 242a0ac │ │ ldr r0, [pc, #3848] @ 242b030 │ │ add r0, pc, r0 │ │ ldr r5, [r0, r9, lsl #2] │ │ cmp r4, r5 │ │ bge 242a0d8 │ │ b 242a804 │ │ - stc2l 10, cr11, [r0, #972]! @ 0x3cc @ │ │ + stc2l 11, cr11, [r0, #128]! @ 0x80 @ │ │ str r4, [fp, #-52] @ 0xffffffcc │ │ mov r6, #1 │ │ ldr r7, [pc, #3816] @ 242b034 │ │ mov r5, #1 │ │ ldr r7, [pc, r7] │ │ b 242a178 │ │ - ldc2l 5, cr12, [pc, #376] @ 242a2d4 │ │ + ldc2l 5, cr12, [pc, #556] @ 242a388 │ │ orrseq r6, r6, r4, asr #23 │ │ ldr r0, [r9, r4, lsl #2] │ │ cmp r0, r7 │ │ movlt r5, r6 │ │ movlt r7, r0 │ │ ldr r0, [fp, #-52] @ 0xffffffcc │ │ cmp r6, r0 │ │ @@ -1279934,21 +1279934,21 @@ │ │ movw r3, #2216 @ 0x8a8 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ ldr r7, [r9, r0, lsl #2] │ │ mov r5, r6 │ │ b 242a16c │ │ ldc2l 13, cr9, [lr, #292] @ 0x124 │ │ - ldc2l 4, cr12, [pc, #856] @ 242a534 │ │ + ldc2l 5, cr12, [pc, #12] @ 242a1e8 │ │ orrseq r6, r6, ip, ror fp │ │ ldc2l 13, cr9, [lr, #4] │ │ - ldc2l 4, cr12, [pc, #568] @ 242a420 │ │ + ldc2l 4, cr12, [pc, #748] @ 242a4d4 │ │ orrseq r6, r6, r4, asr #19 │ │ stc2l 8, cr9, [r1, #472]! @ 0x1d8 │ │ - ldc2l 4, cr12, [pc, #216] @ 242a2cc │ │ + ldc2l 4, cr12, [pc, #396] @ 242a380 │ │ orrseq r6, r6, r8, lsr #22 │ │ sub r4, r5, #1 │ │ mov r6, r5 │ │ cmp r4, #20 │ │ str r4, [fp, #-52] @ 0xffffffcc │ │ mov r0, r4 │ │ bcc 242a224 │ │ @@ -1279987,36 +1279987,36 @@ │ │ ldr r0, [pc, #3980] @ 242b220 │ │ str r4, [fp, #-52] @ 0xffffffcc │ │ add r0, pc, r0 │ │ str r5, [r0, r4, lsl #2] │ │ mov r0, r4 │ │ b 242a348 │ │ stc2l 8, cr9, [r1, #232]! @ 0xe8 │ │ - ldc2l 3, cr12, [pc, #1000] @ 242a698 │ │ + ldc2l 4, cr12, [pc, #156] @ 242a34c │ │ @ instruction: 0x01966af8 │ │ orrseq r6, r6, r0, asr r9 │ │ stc2l 14, cr6, [r2, #592]! @ 0x250 │ │ - ldc2l 3, cr12, [pc, #776] @ 242a5c8 │ │ + ldc2l 3, cr12, [pc, #956] @ 242a67c │ │ orrseq r0, r7, r4, ror #15 │ │ stc2l 14, cr6, [r2, #352]! @ 0x160 │ │ - ldc2l 3, cr12, [pc, #536] @ 242a4e4 │ │ + ldc2l 3, cr12, [pc, #716] @ 242a598 │ │ @ instruction: 0x019707b4 │ │ @ instruction: 0x019668dc │ │ ldc2l 14, cr11, [lr, #648] @ 0x288 │ │ - ldc2l 3, cr12, [pc, #312] @ 242a414 │ │ + ldc2l 3, cr12, [pc, #492] @ 242a4c8 │ │ @ instruction: 0x0196b8b0 │ │ ldc2l 14, cr11, [lr, #408] @ 0x198 │ │ - ldc2l 3, cr12, [pc, #72] @ 242a330 │ │ + ldc2l 3, cr12, [pc, #252] @ 242a3e4 │ │ orrseq fp, r6, r0, lsl #17 │ │ orrseq r6, r6, r8, ror #16 │ │ stc2l 1, cr5, [r2, #704]! @ 0x2c0 │ │ - ldc2l 2, cr12, [pc, #872] @ 242a660 │ │ + ldc2l 3, cr12, [pc, #28] @ 242a314 │ │ orrseq fp, r6, ip, lsl #17 │ │ stc2l 1, cr5, [r2, #464]! @ 0x1d0 │ │ - ldc2l 2, cr12, [pc, #632] @ 242a57c │ │ + ldc2l 2, cr12, [pc, #812] @ 242a630 │ │ orrseq fp, r6, ip, asr r8 │ │ @ instruction: 0x019667f4 │ │ ldr r0, [pc, #4060] @ 242b2ec │ │ mov r1, r4 │ │ mov r2, r8 │ │ mov r3, #2240 @ 0x8c0 │ │ add r0, pc, r0 │ │ @@ -1280089,27 +1280089,27 @@ │ │ ldr r0, [pc, #4020] @ 242b3e0 │ │ str r4, [fp, #-52] @ 0xffffffcc │ │ add r0, pc, r0 │ │ str r7, [r0, r4, lsl #2] │ │ mov r0, r4 │ │ b 242a508 │ │ ldc2l 10, cr9, [lr, #868] @ 0x364 @ │ │ - ldc2l 2, cr12, [pc, #408] @ 242a5e0 │ │ + ldc2l 2, cr12, [pc, #588] @ 242a694 │ │ orrseq r6, r6, r8, lsl #18 │ │ ldc2l 10, cr9, [lr, #644] @ 0x284 @ │ │ - ldc2l 2, cr12, [pc, #184] @ 242a50c │ │ + ldc2l 2, cr12, [pc, #364] @ 242a5c0 │ │ @ instruction: 0x019668d4 │ │ orrseq r6, r6, ip, ror r7 │ │ orrseq r6, r6, r0, ror r7 │ │ - ldc2l 15, cr15, [pc, #700] @ 242a720 │ │ - ldc2l 1, cr12, [pc, #444] @ 242a624 │ │ - ldc2l 1, cr12, [pc, #456] @ 242a634 │ │ + ldc2l 15, cr15, [pc, #880] @ 242a7d4 │ │ + ldc2l 1, cr12, [pc, #624] @ 242a6d8 │ │ + ldc2l 1, cr12, [pc, #636] @ 242a6e8 │ │ orrseq r6, sl, r0, asr r1 │ │ stc2l 9, cr7, [r1, #76]! @ 0x4c @ │ │ - ldc2l 1, cr12, [pc, #248] @ 242a570 │ │ + ldc2l 1, cr12, [pc, #428] @ 242a624 │ │ orrseq r6, r6, r8, lsr #13 │ │ ldr r0, [pc, #4088] @ 242b478 │ │ mov r1, r4 │ │ mov r2, r8 │ │ movw r3, #2243 @ 0x8c3 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ @@ -1280177,26 +1280177,26 @@ │ │ str r4, [fp, #-52] @ 0xffffffcc │ │ add r6, pc, r6 │ │ add r0, r6, r4, lsl #3 │ │ vstr d8, [r0] │ │ mov r0, r4 │ │ b 242a640 │ │ ldc2l 9, cr9, [lr, #246] @ 0xf6 @ │ │ - ldc2l 0, cr12, [pc, #1016] @ 242a9a0 │ │ + ldc2l 1, cr12, [pc, #172] @ 242a654 │ │ orrseq r6, r6, ip, lsl #14 │ │ stc2l 15, cr4, [r2, #648]! @ 0x288 │ │ - ldc2l 0, cr12, [pc, #792] @ 242a8cc │ │ + ldc2l 0, cr12, [pc, #972] @ 242a980 │ │ orrseq r6, sl, ip, lsl #8 │ │ - stc2l 14, cr3, [r0, #552]! @ 0x228 │ │ + stc2l 14, cr3, [r0, #732]! @ 0x2dc │ │ orrseq r6, sl, r4, lsr #8 │ │ stc2l 9, cr3, [r1, #312]! @ 0x138 @ │ │ - ldc2l 0, cr12, [pc, #280] @ 242a6e0 │ │ + ldc2l 0, cr12, [pc, #460] @ 242a794 │ │ orrseq r6, sl, ip, rrx │ │ eorseq sp, r2, ip, asr #16 │ │ - ldc2l 15, cr5, [pc, #512] @ 242a7d4 │ │ + ldc2l 15, cr5, [pc, #692] @ 242a888 │ │ ldr r0, [pc, #4032] @ 242b598 │ │ mov r1, r4 │ │ mov r2, r8 │ │ movw r3, #2264 @ 0x8d8 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ ldr r6, [pc, #4012] @ 242b59c │ │ @@ -1280252,18 +1280252,18 @@ │ │ bl 270d1a0 │ │ ldr r1, [pc, #3848] @ 242b5c4 │ │ add r4, sp, #86 @ 0x56 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ b 2429dd4 │ │ orrseq r6, r6, r0, asr r5 │ │ - ldc2l 14, cr5, [pc, #1020] @ 242aad0 │ │ - vcadd.f32 d25, d15, d1, #270 │ │ + ldc2l 15, cr5, [pc, #176] @ 242a784 │ │ + vcadd.f32 d25, d15, d30, #270 │ │ ldrsbteq sp, [r2], -r0 │ │ - stc2l 13, cr5, [r0, #12]! │ │ + stc2l 13, cr5, [r0, #192]! @ 0xc0 │ │ stc2l 0, cr13, [r1, #676]! @ 0x2a4 │ │ orrseq r6, r6, ip, ror #9 │ │ @ instruction: 0x019664d4 │ │ orrseq r6, r6, r0, asr #9 │ │ @ instruction: 0x019664bc │ │ @ instruction: 0x019664b4 │ │ orrseq r6, r6, ip, ror #12 │ │ @@ -1280310,23 +1280310,23 @@ │ │ mov r2, #15 │ │ mov r3, #12 │ │ add r1, pc, r1 │ │ b 242aa7c │ │ orrseq r6, r6, r8, ror #8 │ │ orrseq fp, r6, r4, lsr #9 │ │ orrseq fp, r6, r0, asr r4 │ │ - ldc2l 14, cr11, [pc, #840] @ 242ab04 │ │ + ldc2l 14, cr11, [pc, #1020] @ 242abb8 │ │ stc2l 13, cr4, [r2, #432]! @ 0x1b0 │ │ - ldc2l 14, cr11, [pc, #600] @ 242aa1c │ │ + ldc2l 14, cr11, [pc, #780] @ 242aad0 │ │ orrseq fp, r6, r8, asr #8 │ │ orrseq r6, r6, r0, ror #7 │ │ orrseq r1, sl, ip, lsr r0 │ │ - ldc2l 14, cr11, [pc, #328] @ 242a91c │ │ + ldc2l 14, cr11, [pc, #508] @ 242a9d0 │ │ orrseq fp, r6, r0, lsl #8 │ │ - ldc2l 14, cr11, [pc, #200] @ 242a8a4 │ │ + ldc2l 14, cr11, [pc, #380] @ 242a958 │ │ orrseq r6, r6, r0, ror #6 │ │ @ instruction: 0x019a0fbc │ │ ldr r0, [pc, #3904] @ 242b728 │ │ mov r1, r9 │ │ mov r2, r8 │ │ movw r3, #2307 @ 0x903 │ │ add r0, pc, r0 │ │ @@ -1280390,15 +1280390,15 @@ │ │ ldc2l 8, cr11, [lr, #1016] @ 0x3f8 │ │ orrseq r6, r6, r0, lsl #6 │ │ orrseq r0, sl, ip, asr pc │ │ vcadd.f32 , q15, q1, #270 │ │ @ instruction: 0x019662b8 │ │ orrseq r0, sl, r4, lsl pc │ │ orrseq fp, r6, r0, lsl #6 │ │ - ldc2l 13, cr11, [pc, #200] @ 242a9c4 │ │ + ldc2l 13, cr11, [pc, #380] @ 242aa78 │ │ ldr r0, [pc, #3664] @ 242b750 │ │ mov r1, r6 │ │ mov r2, r8 │ │ movw r3, #2403 @ 0x963 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ ldr r2, [sp, #28] │ │ @@ -1280432,23 +1280432,23 @@ │ │ add r0, r0, r2, lsl #2 │ │ ldr r0, [r0, #-4] │ │ cmp r5, r0 │ │ ble 242a928 │ │ sub r0, r2, #1 │ │ str r0, [fp, #-52] @ 0xffffffcc │ │ b 242ab14 │ │ - ldc2l 12, cr11, [pc, #1016] @ 242ad9c │ │ + ldc2l 13, cr11, [pc, #172] @ 242aa50 │ │ vcadd.f32 d27, d14, d26, #270 │ │ stc2l 11, cr0, [r2, #116]! @ 0x74 @ │ │ - ldc2l 12, cr11, [pc, #600] @ 242ac08 │ │ + ldc2l 12, cr11, [pc, #780] @ 242acbc │ │ orrseq r6, r6, r4, ror #7 │ │ orrseq r6, r6, r8, ror #3 │ │ @ instruction: 0x019661d8 │ │ - stc2l 0, cr13, [r0, #444]! @ 0x1bc │ │ - ldc2l 12, cr11, [pc, #312] @ 242aafc │ │ + stc2l 0, cr13, [r0, #624]! @ 0x270 │ │ + ldc2l 12, cr11, [pc, #492] @ 242abb0 │ │ orrseq r0, sl, r4, lsl #28 │ │ stc2l 13, cr12, [r1, #292]! @ 0x124 │ │ orrseq r6, r6, ip, ror r1 │ │ add r0, sp, #40 @ 0x28 │ │ bl 270d340 │ │ bl 270db90 │ │ cmp r0, #0 │ │ @@ -1280502,16 +1280502,16 @@ │ │ ldr r0, [sp, #20] │ │ add r4, sp, #86 @ 0x56 │ │ add r0, r0, #1 │ │ str r0, [sp, #20] │ │ b 2429de0 │ │ @ instruction: 0x019a0db8 │ │ orrseq r6, r6, r0, asr r1 │ │ - stc2l 15, cr12, [r0, #1020]! @ 0x3fc │ │ - ldc2l 11, cr11, [pc, #888] @ 242ae38 @ │ │ + stc2l 0, cr13, [r0, #176]! @ 0xb0 │ │ + ldc2l 12, cr11, [pc, #44] @ 242aaec │ │ ldr r1, [pc, #3252] @ 242b778 │ │ add r0, sp, #86 @ 0x56 │ │ mov r2, #15 │ │ mov r3, #1 │ │ add r1, pc, r1 │ │ bl 270d9e0 │ │ sub r4, r7, #1 │ │ @@ -1280577,17 +1280577,17 @@ │ │ ldr r6, [pc, #3892] @ 242bb00 │ │ add r6, pc, r6 │ │ add r0, r6, r4, lsl #3 │ │ vstr d8, [r0] │ │ mov r0, r4 │ │ b 242ae3c │ │ stc2l 5, cr6, [r2, #624]! @ 0x270 │ │ - ldc2l 10, cr11, [pc, #808] @ 242af10 @ │ │ + ldc2l 10, cr11, [pc, #988] @ 242afc4 @ │ │ orrseq pc, r6, r4, ror #29 │ │ - ldc2l 10, cr11, [pc, #680] @ 242ae98 @ │ │ + ldc2l 10, cr11, [pc, #860] @ 242af4c @ │ │ orrseq r6, sp, ip, lsl #29 │ │ stc2l 5, cr6, [r2, #256]! @ 0x100 │ │ str r7, [sp, #8] │ │ mov r7, sl │ │ mov sl, r6 │ │ ldr r6, [pc, #3836] @ 242bb04 │ │ mov r1, r4 │ │ @@ -1280609,36 +1280609,36 @@ │ │ mov r4, r0 │ │ ldr r0, [sp, #20] │ │ add r0, r5, r0 │ │ str r0, [r9, r4, lsl #2] │ │ add r4, sp, #86 @ 0x56 │ │ b 2429de0 │ │ orrseq r5, sl, ip, lsr sl │ │ - ldc2l 10, cr11, [pc, #204] @ 242ad34 @ │ │ + ldc2l 10, cr11, [pc, #384] @ 242ade8 @ │ │ bl 270de10 │ │ mov r4, r0 │ │ ldr r0, [pc, #3732] @ 242bb08 │ │ ldr r0, [pc, r0] │ │ str r0, [fp, #-52] @ 0xffffffcc │ │ cmp r0, #1 │ │ blt 242b310 │ │ mov sl, r7 │ │ sub r7, r7, #1 │ │ mov r9, #0 │ │ mov r3, #0 │ │ b 242acfc │ │ ldc2l 2, cr9, [lr, #500] @ 0x1f4 │ │ - ldc2l 10, cr11, [pc, #24] @ 242acb8 @ │ │ + ldc2l 10, cr11, [pc, #204] @ 242ad6c @ │ │ ldrheq r6, [r6, r0] │ │ stc2l 4, cr6, [r2, #656]! @ 0x290 │ │ - ldc2l 9, cr11, [pc, #412] @ 242ae48 @ │ │ + ldc2l 9, cr11, [pc, #502] @ 242aea2 @ │ │ @ instruction: 0x0196fdf4 │ │ ldc2l 14, cr14, [lr, #280] @ 0x118 │ │ stc2l 8, cr0, [r2, #76]! @ 0x4c │ │ - ldc2l 9, cr11, [pc, #196] @ 242ad80 @ │ │ + ldc2l 9, cr11, [pc, #286] @ 242adda @ │ │ @ instruction: 0x0196fd94 │ │ orrseq r5, r6, r0, ror pc │ │ ldc2l 10, cr15, [lr, #536] @ 0x218 @ │ │ ldr r0, [pc, #4088] @ 242bcc4 │ │ clz r2, r3 │ │ mov r1, #0 │ │ add r0, pc, r0 │ │ @@ -1280707,18 +1280707,18 @@ │ │ ldr r0, [pc, #4020] @ 242bd88 │ │ str r4, [fp, #-52] @ 0xffffffcc │ │ add r0, pc, r0 │ │ str r6, [r0, r4, lsl #2] │ │ b 242b444 │ │ stc2l 7, cr0, [r2, #316]! @ 0x13c │ │ ldc2l 13, cr14, [lr, #296] @ 0x128 │ │ - ldc2l 6, cr15, [pc, #380] @ 242af6c │ │ + ldc2l 6, cr15, [pc, #560] @ 242b020 │ │ ldc2l 0, cr9, [lr, #128] @ 0x80 │ │ stc2l 11, cr8, [r1, #592]! @ 0x250 @ │ │ - stc2l 4, cr5, [r0, #844]! @ 0x34c │ │ + stc2l 5, cr5, [r0] │ │ ldr r0, [pc, #3980] @ 242bd8c │ │ mov r1, r4 │ │ mov r2, r8 │ │ movw r3, #2501 @ 0x9c5 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ ldr r6, [pc, #3960] @ 242bd90 │ │ @@ -1280761,20 +1280761,20 @@ │ │ add r4, sp, #86 @ 0x56 │ │ mov r2, #15 │ │ mov r3, #8 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ b 2429ddc │ │ stc2l 9, cr10, [r1, #152]! @ 0x98 @ │ │ - stc2l 13, cr10, [r0, #536]! @ 0x218 │ │ - ldc2l 2, cr3, [pc, #164] @ 242af70 │ │ + stc2l 13, cr10, [r0, #716]! @ 0x2cc │ │ + ldc2l 2, cr3, [pc, #344] @ 242b024 │ │ stc2l 10, cr8, [r1, #1016]! @ 0x3f8 @ │ │ - ldc2l 0, cr9, [pc, #116] @ 242af48 │ │ + ldc2l 0, cr9, [pc, #296] @ 242affc │ │ stc2l 0, cr5, [r1, #460]! @ 0x1cc │ │ - ldc2l 5, cr1, [pc, #540] @ 242b0f8 │ │ + ldc2l 5, cr1, [pc, #720] @ 242b1ac │ │ ldc2l 2, cr11, [lr, #184] @ 0xb8 │ │ orrseq r5, r6, r8, lsr ip │ │ orrseq sl, r6, r0, asr #24 │ │ ldr r0, [pc, #4032] @ 242beac │ │ add r0, pc, r0 │ │ ldr r0, [r0, r1, lsl #2] │ │ str r0, [fp, #-64] @ 0xffffffc0 │ │ @@ -1280844,20 +1280844,20 @@ │ │ movw r3, #2511 @ 0x9cf │ │ add r0, pc, r0 │ │ bl 270da30 │ │ ldr r1, [pc, #4092] @ 242c000 │ │ add r1, pc, r1 │ │ add r0, r1, r0, lsl #3 │ │ b 242b13c │ │ - stc2l 10, cr12, [r0, #764]! @ 0x2fc @ │ │ + stc2l 10, cr12, [r0, #944]! @ 0x3b0 @ │ │ orrseq r0, sl, ip, asr r8 │ │ stc2l 7, cr10, [r1, #832]! @ 0x340 │ │ orrseq r5, r6, r8, asr #23 │ │ @ instruction: 0x01965bb0 │ │ - stc2l 10, cr12, [r0, #92]! @ 0x5c @ │ │ + stc2l 10, cr12, [r0, #272]! @ 0x110 @ │ │ @ instruction: 0x019a07b8 │ │ ldc2l 1, cr11, [lr, #40] @ 0x28 │ │ orrseq sl, r6, r4, lsr #22 │ │ orrseq r0, sl, ip, asr r7 │ │ orrseq pc, r6, r4, lsr #19 │ │ ldr r1, [fp, #8] │ │ movw r2, #5000 @ 0x1388 │ │ @@ -1281032,15 +1281032,15 @@ │ │ mov r5, r3 │ │ mov sl, r3 │ │ b 242c2dc │ │ stc2l 7, cr8, [r1, #872]! @ 0x368 │ │ @ instruction: 0x01965a90 │ │ stc2l 14, cr5, [r2, #272]! @ 0x110 │ │ @ instruction: 0x019658d0 │ │ - stc2l 7, cr12, [r0, #396]! @ 0x18c │ │ + stc2l 7, cr12, [r0, #576]! @ 0x240 │ │ @ instruction: 0x019a04f8 │ │ ldc2l 14, cr10, [lr, #376] @ 0x178 │ │ orrseq sl, r6, ip, ror r8 │ │ orrseq r5, r6, r0, ror #16 │ │ ldr r0, [sp, #16] │ │ sub r1, r0, #1 │ │ str r1, [fp, #-52] @ 0xffffffcc │ │ @@ -1281085,15 +1281085,15 @@ │ │ ldr r0, [pc, #4088] @ 242c3b4 │ │ mov r5, #0 │ │ str r4, [fp, #-52] @ 0xffffffcc │ │ add r0, pc, r0 │ │ str r5, [r0, r4, lsl #2] │ │ mov r0, r4 │ │ b 242bbac │ │ - stc2l 6, cr12, [r0, #972]! @ 0x3cc │ │ + stc2l 7, cr12, [r0, #128]! @ 0x80 │ │ orrseq r0, sl, r4, lsl #9 │ │ orrseq r5, r6, r0, ror #18 │ │ orrseq sl, r6, r4, ror #16 │ │ orrseq r5, sl, r4, ror r2 │ │ ldr r0, [pc, #4044] @ 242c3b8 │ │ mov r1, r4 │ │ mov r2, r8 │ │ @@ -1281131,17 +1281131,17 @@ │ │ ldr r6, [pc, #3996] @ 242c410 │ │ add r6, pc, r6 │ │ b 2429de0 │ │ stc2l 1, cr4, [r2] │ │ orrseq sl, r6, r0, ror #15 │ │ ldc2l 10, cr8, [lr, #468] @ 0x1d4 @ │ │ orrseq r5, r6, r8, lsr #17 │ │ - ldc2l 1, cr11, [pc, #860] @ 242b7ec │ │ + ldc2l 2, cr11, [pc, #16] @ 242b4a0 │ │ @ instruction: 0x019a51b0 │ │ - ldc2l 1, cr11, [pc, #760] @ 242b790 │ │ + ldc2l 1, cr11, [pc, #940] @ 242b844 │ │ @ instruction: 0x019d65b4 │ │ ldr r4, [pc, #3956] @ 242c414 │ │ add r4, pc, r4 │ │ mov r0, r4 │ │ bl 270e0c0 │ │ cmp r0, #0 │ │ beq 242bd34 │ │ @@ -1281203,15 +1281203,15 @@ │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ b 242c368 │ │ ldc2l 9, cr8, [lr, #150] @ 0x96 @ │ │ @ instruction: 0x019656d8 │ │ stc2l 15, cr3, [r2, #520]! @ 0x208 │ │ orrseq r5, sl, ip, ror #7 │ │ - stc2l 14, cr2, [r0, #408]! @ 0x198 │ │ + stc2l 14, cr2, [r0, #588]! @ 0x24c │ │ orrseq r5, sl, r0, lsl r4 │ │ ldc2l 7, cr12, [lr, #940] @ 0x3ac │ │ orrseq pc, r6, r4, ror r4 @ │ │ stc2l 9, cr2, [r1, #240]! @ 0xf0 @ │ │ orrseq r5, sl, r0, asr r0 │ │ eorseq ip, r2, ip, lsr #16 │ │ stc2l 3, cr8, [r1, #384]! @ 0x180 │ │ @@ -1281298,33 +1281298,33 @@ │ │ add r0, sp, #86 @ 0x56 │ │ add r1, pc, r1 │ │ str r5, [r1, r4, lsl #2] │ │ mov r4, r0 │ │ b 242c3f4 │ │ eorseq ip, r2, r0, lsr #15 │ │ mlaseq r2, r8, r7, ip │ │ - ldc2l 9, cr2, [pc, #298] @ 242b856 @ │ │ - stc2l 2, cr12, [r0, #908]! @ 0x38c │ │ + ldc2l 9, cr2, [pc, #388] @ 242b8b0 @ │ │ + stc2l 3, cr12, [r0, #64]! @ 0x40 │ │ orrseq r0, sl, r4, lsl #1 │ │ ldc2l 9, cr10, [lr, #460] @ 0x1cc @ │ │ @ instruction: 0x0196a3fc │ │ stc2l 12, cr15, [r1, #884]! @ 0x374 │ │ orrseq r5, r6, r8, lsr #11 │ │ orrseq r5, r6, r0, asr r4 │ │ ldc2l 15, cr14, [lr, #312] @ 0x138 │ │ orrseq pc, r6, r0, lsr r2 @ │ │ orrseq r5, r6, r0, asr r3 │ │ - stc2l 1, cr12, [r0, #812]! @ 0x32c │ │ + stc2l 1, cr12, [r0, #992]! @ 0x3e0 │ │ orrseq pc, r9, r8, ror #30 │ │ stc2l 12, cr3, [r2, #224]! @ 0xe0 │ │ orrseq sl, r6, ip, lsl r3 │ │ orrseq pc, r9, r4, lsl #30 │ │ eorseq ip, r2, ip, asr #9 │ │ eorseq ip, r2, r4, asr #9 │ │ - stc2l 9, cr4, [r0, #62]! @ 0x3e @ │ │ + stc2l 9, cr4, [r0, #152]! @ 0x98 @ │ │ stc2l 15, cr7, [r1, #712]! @ 0x2c8 │ │ stc2l 5, cr4, [r1, #316]! @ 0x13c │ │ ldc2l 0, cr14, [lr, #568] @ 0x238 │ │ sub r1, r0, #1 │ │ cmp r1, #20 │ │ bcc 242b7a4 │ │ ldr r0, [pc, #3964] @ 242c70c │ │ @@ -1281542,15 +1281542,15 @@ │ │ mov r6, r4 │ │ str r5, [r0, r4, lsl #2] │ │ str r4, [fp, #-52] @ 0xffffffcc │ │ b 242c10c │ │ stc2l 10, cr15, [r1, #180]! @ 0xb4 @ │ │ @ instruction: 0x019652f8 │ │ orrseq r5, r6, r0, lsr #3 │ │ - stc2l 8, cr4, [r0, #220]! @ 0xdc │ │ + vcmla.f16 q10, q0, q10, #270 │ │ stc2l 3, cr6, [r1, #24]! │ │ orrseq r5, r6, ip, lsl #1 │ │ orrseq r5, r6, r8, lsl #2 │ │ stc2l 5, cr5, [r2, #480]! @ 0x1e0 │ │ @ instruction: 0x01964fb4 │ │ ldr r0, [pc, #4044] @ 242cae0 │ │ mov r1, r4 │ │ @@ -1281705,15 +1281705,15 @@ │ │ ldr r1, [pc, #4068] @ 242cd50 │ │ add r4, sp, #86 @ 0x56 │ │ mov r2, #15 │ │ mov r3, #7 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ b 2429ddc │ │ - stc2l 13, cr11, [r0, #204]! @ 0xcc │ │ + stc2l 13, cr11, [r0, #384]! @ 0x180 │ │ orrseq pc, r9, r4, asr #21 │ │ orrseq r9, r6, ip, lsr #29 │ │ ldc2l 1, cr8, [lr, #140] @ 0x8c │ │ @ instruction: 0x01964eb0 │ │ ldc2l 0, cr8, [lr, #964] @ 0x3c4 │ │ orrseq r4, r6, r0, lsr pc │ │ @ instruction: 0x0196ec9c │ │ @@ -1282201,17 +1282201,17 @@ │ │ ble 242c868 │ │ cmp sl, #19 │ │ bhi 242c550 │ │ ldr r4, [r9, sl, lsl #2] │ │ mov r0, sl │ │ b 242c588 │ │ orrseq r5, sp, r8, ror #10 │ │ - ldc2l 11, cr1, [pc, #756] @ 242c83c @ │ │ - ldc2l 9, cr7, [pc, #434] @ 242c6fe @ │ │ - stc2l 6, cr9, [r0, #460]! @ 0x1cc │ │ + ldc2l 11, cr1, [pc, #936] @ 242c8f0 @ │ │ + ldc2l 10, cr7, [pc, #24] @ 242c564 @ │ │ + stc2l 6, cr9, [r0, #640]! @ 0x280 │ │ orrseq r9, r6, ip, ror #13 │ │ ldr r5, [pc, #3912] @ 242d4a0 │ │ mov r1, sl │ │ mov r2, r8 │ │ movw r3, #2922 @ 0xb6a │ │ add r5, pc, r5 │ │ mov r0, r5 │ │ @@ -1282620,21 +1282620,21 @@ │ │ bne 242cd14 │ │ cmp r9, #1 │ │ mov r9, r7 │ │ mov r7, r5 │ │ mov r2, #0 │ │ bgt 242c8cc │ │ b 242cbf4 │ │ - stc2l 14, cr10, [r0, #1020]! @ 0x3fc │ │ + stc2l 15, cr10, [r0, #176]! @ 0xb0 │ │ orrseq r4, r6, r4, ror #1 │ │ orrseq lr, r9, ip, lsl #25 │ │ ldc2l 5, cr9, [lr, #968] @ 0x3c8 │ │ orrseq r9, r6, r0, lsl r0 │ │ @ instruction: 0x01963ff4 │ │ - stc2l 14, cr10, [r0, #540]! @ 0x21c │ │ + stc2l 14, cr10, [r0, #720]! @ 0x2d0 │ │ orrseq lr, r9, ip, lsl ip │ │ ldr r7, [sp, #8] │ │ ldr r4, [sp, #12] │ │ cmp r4, #20 │ │ str r4, [fp, #-52] @ 0xffffffcc │ │ str r2, [sp, #28] │ │ bcc 242cc20 │ │ @@ -1282716,29 +1282716,29 @@ │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ stc2l 12, cr6, [r1, #920]! @ 0x398 │ │ ldr r7, [pc, #3456] @ 242dac4 │ │ add r7, pc, r7 │ │ mov r8, r7 │ │ b 2429768 │ │ - stc2l 15, cr8, [r0, #88]! @ 0x58 │ │ + stc2l 15, cr8, [r0, #268]! @ 0x10c │ │ stc2l 2, cr3, [r1, #412]! @ 0x19c │ │ - stc2l 14, cr8, [r0, #556]! @ 0x22c │ │ + stc2l 14, cr8, [r0, #736]! @ 0x2e0 │ │ orrseq r8, r6, r4, lsl #30 │ │ stc2l 11, cr8, [r1, #492]! @ 0x1ec @ │ │ orrseq sp, r6, r4, lsr sp │ │ ldrhteq fp, [r2], -ip │ │ stc2l 12, cr12, [r1, #448]! @ 0x1c0 │ │ orrseq r3, sl, r4, lsr #30 │ │ ldc2l 0, cr7, [lr, #628] @ 0x274 │ │ @ instruction: 0x01963edc │ │ - ldc2l 7, cr9, [pc, #1000] @ 242d168 │ │ + vcadd.f32 d25, d15, d23, #270 │ │ orrseq r4, sp, r4, ror #23 │ │ ldc2l 0, cr7, [lr, #212] @ 0xd4 │ │ - stc2l 13, cr8, [r0, #252]! @ 0xfc │ │ + stc2l 13, cr8, [r0, #432]! @ 0x1b0 │ │ orrseq r3, r6, r4, ror #28 │ │ ldr r0, [fp, #-64] @ 0xffffffc0 │ │ mov r8, r7 │ │ movw r5, #5000 @ 0x1388 │ │ add r1, r0, r0, lsl #2 │ │ sub r0, r0, #1 │ │ sub r3, r1, #5 │ │ @@ -1282906,17 +1282906,17 @@ │ │ add r0, r0, r4, lsl #3 │ │ vstr d9, [r0] │ │ mov r0, r4 │ │ b 242d0d0 │ │ orrseq r3, r6, ip, lsl sp │ │ @ instruction: 0x019d4ab0 │ │ stc2l 4, cr2, [r2, #712]! @ 0x2c8 │ │ - stc2l 3, cr1, [r0, #632]! @ 0x278 │ │ + stc2l 3, cr1, [r0, #812]! @ 0x32c │ │ orrseq r3, r6, r4, lsl fp │ │ - stc2l 3, cr1, [r0, #456]! @ 0x1c8 │ │ + stc2l 3, cr1, [r0, #636]! @ 0x27c │ │ ldr r0, [pc, #2764] @ 242db24 │ │ mov r1, r4 │ │ ldr r5, [pc, #2760] @ 242db28 │ │ movw r3, #2534 @ 0x9e6 │ │ add r0, pc, r0 │ │ add r5, pc, r5 │ │ mov r2, r5 │ │ @@ -1282966,15 +1282966,15 @@ │ │ ldr r0, [fp, #12] │ │ mov r1, r3 │ │ bl 270e100 │ │ str r4, [fp, #-52] @ 0xffffffcc │ │ b 242d198 │ │ orrseq r3, sl, r8, lsl r9 │ │ orrseq r3, r6, r4, asr #21 │ │ - ldc2l 5, cr9, [pc, #264] @ 242d244 │ │ + ldc2l 5, cr9, [pc, #444] @ 242d2f8 │ │ orrseq r3, r6, ip, lsr fp │ │ orrseq r4, sp, r0, lsr #18 │ │ ldr r0, [pc, #2568] @ 242db50 │ │ movw r3, #2542 @ 0x9ee │ │ ldr r5, [pc, #2564] @ 242db54 │ │ add r0, pc, r0 │ │ add r5, pc, r5 │ │ @@ -1282998,20 +1282998,20 @@ │ │ ldr r0, [pc, #2500] @ 242db64 │ │ mov r1, #1 │ │ ldr r2, [pc, #2496] @ 242db68 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ str r1, [r2, r4, lsl #2] │ │ b 242cd1c │ │ - ldc2l 4, cr9, [pc, #1016] @ 242d5b4 │ │ + ldc2l 5, cr9, [pc, #172] @ 242d268 │ │ @ instruction: 0x019d48f0 │ │ orrseq r3, r6, r8, asr #20 │ │ - ldc2l 4, cr9, [pc, #732] @ 242d4a4 │ │ + ldc2l 4, cr9, [pc, #912] @ 242d558 │ │ orrseq r3, sl, ip, lsl #9 │ │ - ldc2l 4, cr9, [pc, #508] @ 242d3cc │ │ + ldc2l 4, cr9, [pc, #688] @ 242d480 │ │ orrseq r3, sl, r0, ror #8 │ │ @ instruction: 0x019639d8 │ │ stc2l 13, cr0, [r1, #576]! @ 0x240 │ │ stc2l 13, cr0, [r1, #400]! @ 0x190 │ │ ldr r0, [fp, #16] │ │ ldr r1, [fp, #28] │ │ bl 270d360 │ │ @@ -1283065,15 +1283065,15 @@ │ │ vmovge.f64 d16, d18 │ │ vstr d16, [r7] │ │ b 242d8fc │ │ orrseq r3, sl, ip, lsr r4 │ │ eorseq sl, r2, r4, lsl ip │ │ orrseq r3, r6, r4, asr r9 │ │ orrseq r3, r6, ip, lsr r9 │ │ - ldc2l 2, cr15, [lr, #92] @ 0x5c │ │ + ldc2l 2, cr15, [lr, #272] @ 0x110 │ │ ldc2l 4, cr13, [lr, #888] @ 0x378 │ │ str r5, [sp, #28] │ │ mov r5, r1 │ │ ldr r0, [pc, #2200] @ 242db70 │ │ mov r1, r4 │ │ ldr r6, [pc, #2196] @ 242db74 │ │ mov r3, #2944 @ 0xb80 │ │ @@ -1283095,15 +1283095,15 @@ │ │ mov r1, r5 │ │ str r5, [fp, #-52] @ 0xffffffcc │ │ bl 270da30 │ │ b 242d36c │ │ stc2l 12, cr14, [r0, #284]! @ 0x11c │ │ @ instruction: 0x019639d4 │ │ orrseq r3, r6, ip, lsl #19 │ │ - ldc2l 1, cr15, [lr, #76] @ 0x4c │ │ + ldc2l 1, cr15, [lr, #256] @ 0x100 │ │ ldc2l 10, cr6, [lr, #964] @ 0x3c4 @ │ │ orrseq r3, r6, r8, lsr #18 │ │ ldc2l 10, cr6, [lr, #740] @ 0x2e4 @ │ │ @ instruction: 0x019638f4 │ │ str r5, [sp, #28] │ │ ldr r1, [pc, #2068] @ 242db6c │ │ ldr r2, [fp, #12] │ │ @@ -1283185,15 +1283185,15 @@ │ │ add r0, r0, r5, lsl #3 │ │ vstr d9, [r0] │ │ b 242d4f4 │ │ stc2l 9, cr4, [r1, #468]! @ 0x1d4 @ │ │ orrseq r3, r6, r0, ror r7 │ │ ldc2l 10, cr6, [lr, #204] @ 0xcc @ │ │ orrseq r3, r6, r8, asr #15 │ │ - ldc2l 1, cr9, [pc, #376] @ 242d620 │ │ + ldc2l 1, cr9, [pc, #556] @ 242d6d4 │ │ ldr r0, [pc, #1792] @ 242dbac │ │ mov r1, r5 │ │ ldr r4, [pc, #1788] @ 242dbb0 │ │ movw r3, #2953 @ 0xb89 │ │ add r0, pc, r0 │ │ add r4, pc, r4 │ │ mov r2, r4 │ │ @@ -1283393,15 +1283393,15 @@ │ │ ldc2l 7, cr6, [lr, #156] @ 0x9c │ │ @ instruction: 0x019d42f8 │ │ stc2l 15, cr7, [r1, #908]! @ 0x38c │ │ orrseq r3, r6, r4, lsl #7 │ │ orrseq r3, r6, r0, lsl r4 │ │ orrseq r3, r6, ip, lsr #6 │ │ orrseq r4, sp, r8, ror r1 │ │ - ldc2l 13, cr8, [pc, #184] @ 242d8a0 │ │ + ldc2l 13, cr8, [pc, #364] @ 242d954 │ │ ldr r5, [pc, #1096] @ 242dc34 │ │ movw r3, #3063 @ 0xbf7 │ │ ldr r4, [pc, #1092] @ 242dc38 │ │ ldr r7, [sp, #12] │ │ add r5, pc, r5 │ │ add r4, pc, r4 │ │ mov r0, r5 │ │ @@ -1283571,146 +1283571,146 @@ │ │ str r6, [r1, r2, lsl #2] │ │ b 242cd1c │ │ orrseq r3, r6, r0, lsl #4 │ │ ldc2l 4, cr6, [lr, #204] @ 0xcc │ │ @ instruction: 0x019631b4 │ │ stc2l 9, cr13, [r1, #362]! @ 0x16a @ │ │ orrseq r3, r6, ip, ror r2 │ │ - ldc2l 10, cr8, [pc, #680] @ 242dd58 @ │ │ + ldc2l 10, cr8, [pc, #860] @ 242de0c @ │ │ @ instruction: 0x01963098 │ │ ldc2l 11, cr12, [lr, #712] @ 0x2c8 @ │ │ orrseq r3, sp, r0, lsl #29 │ │ vcmla.f16 , , , #270 │ │ @ instruction: 0x0196ce90 │ │ orrseq r2, sl, r4, lsl #20 │ │ orrseq r2, r6, r0, ror #29 │ │ stc2l 11, cr7, [r1, #732]! @ 0x2dc @ │ │ - ldc2l 8, cr8, [pc, #968] @ 242de9c │ │ + ldc2l 9, cr8, [pc, #62] @ 242db12 @ │ │ ldrshteq sl, [r2], -r8 │ │ orrseq ip, r6, ip, asr sp │ │ stc2l 12, cr11, [r1, #624]! @ 0x270 │ │ - ldc2l 8, cr8, [pc, #600] @ 242dd3c │ │ + vcadd.f32 q12, , , #270 │ │ orrseq r2, sl, r4, asr #30 │ │ - stc2l 13, cr7, [r0, #860]! @ 0x35c │ │ - vcadd.f32 q12, , q1, #270 │ │ + stc2l 14, cr7, [r0, #16]! │ │ + vcadd.f32 q12, , , #270 │ │ orrseq r7, r6, r8, asr #28 │ │ stc2l 15, cr3, [r1, #920]! @ 0x398 │ │ - ldc2l 7, cr8, [pc, #1016] @ 242def4 │ │ + vcadd.f32 d24, d15, d27, #270 │ │ orrseq r2, r6, r8, ror #26 │ │ stc2l 10, cr7, [r1, #508]! @ 0x1fc @ │ │ - ldc2l 7, cr8, [pc, #744] @ 242ddf0 │ │ + ldc2l 7, cr8, [pc, #924] @ 242dea4 │ │ orrseq ip, r6, r0, lsr ip │ │ stc2l 15, cr3, [r1, #200]! @ 0xc8 │ │ - ldc2l 7, cr8, [pc, #296] @ 242dc3c │ │ + ldc2l 7, cr8, [pc, #476] @ 242dcf0 │ │ ldc2l 15, cr5, [lr, #652] @ 0x28c │ │ orrseq r2, r6, ip, lsr #26 │ │ stc2l 9, cr7, [r1, #326]! @ 0x146 @ │ │ - ldc2l 6, cr8, [pc, #888] @ 242de9c │ │ + ldc2l 7, cr8, [pc, #44] @ 242db50 │ │ orrseq ip, r6, r4, asr fp │ │ ldc2l 14, cr5, [lr, #812] @ 0x32c │ │ - ldc2l 6, cr8, [pc, #328] @ 242dc78 │ │ + ldc2l 6, cr8, [pc, #508] @ 242dd2c │ │ stc2l 5, cr1, [r2, #56]! @ 0x38 │ │ orrseq r2, r6, r8, asr #24 │ │ - stc2l 3, cr0, [r0, #952]! @ 0x3b8 │ │ + stc2l 4, cr0, [r0, #108]! @ 0x6c │ │ orrseq r2, sl, r8, asr r9 │ │ @ instruction: 0x019a29fc │ │ orrseq r2, r6, ip, lsr #25 │ │ orrseq r2, sl, r0, lsl #19 │ │ eorseq r9, r2, ip, asr #27 │ │ orrseq r2, sl, r0, ror #11 │ │ stc2l 14, cr15, [r0, #752]! @ 0x2f0 │ │ - ldc2l 5, cr8, [pc, #408] @ 242dcf4 │ │ + ldc2l 5, cr8, [pc, #588] @ 242dda8 │ │ eorseq r9, r2, r4, ror sp │ │ orrseq r2, sl, r8, lsl #11 │ │ - ldc2l 5, cr8, [pc, #156] @ 242dc04 │ │ - ldc2l 4, cr2, [pc, #512] @ 242dd6c │ │ + ldc2l 5, cr8, [pc, #336] @ 242dcb8 │ │ + ldc2l 4, cr2, [pc, #692] @ 242de20 │ │ @ instruction: 0x019a24f8 │ │ eorseq r9, r2, r0, lsl #23 │ │ stc2l 6, cr7, [r1, #604]! @ 0x25c │ │ - ldc2l 3, cr8, [pc, #824] @ 242deb4 │ │ + ldc2l 3, cr8, [pc, #1004] @ 242df68 │ │ ldrsbteq r9, [r2], -r8 │ │ stc2l 7, cr11, [r1, #640]! @ 0x280 │ │ @ instruction: 0x019a29fc │ │ - vcmla.f16 d23, d16, d11, #270 │ │ - ldc2l 2, cr8, [pc, #984] @ 242df68 │ │ + stc2l 8, cr7, [r0, #736]! @ 0x2e0 │ │ + ldc2l 3, cr8, [pc, #140] @ 242dc1c │ │ orrseq r7, r6, r0, lsl #18 │ │ stc2l 10, cr3, [r1, #616]! @ 0x268 @ │ │ - ldc2l 2, cr8, [pc, #712] @ 242de64 │ │ + ldc2l 2, cr8, [pc, #892] @ 242df18 │ │ orrseq r2, r6, r0, lsr #16 │ │ orrseq r2, r6, r8, lsr #17 │ │ stc2l 5, cr7, [r1, #220]! @ 0xdc │ │ - ldc2l 2, cr8, [pc, #456] @ 242dd74 │ │ + ldc2l 2, cr8, [pc, #636] @ 242de28 │ │ orrseq ip, r6, r8, ror #13 │ │ stc2l 9, cr3, [r1, #460]! @ 0x1cc @ │ │ - ldc2l 1, cr8, [pc, #1016] @ 242dfb0 │ │ + ldc2l 2, cr8, [pc, #172] @ 242dc64 │ │ ldc2l 10, cr5, [lr, #364] @ 0x16c @ │ │ orrseq r2, r6, ip, asr r7 │ │ @ instruction: 0x019627b0 │ │ stc2l 4, cr7, [r1, #380]! @ 0x17c │ │ - ldc2l 1, cr8, [pc, #616] @ 242de34 │ │ + ldc2l 1, cr8, [pc, #796] @ 242dee8 │ │ orrseq ip, r6, ip, lsl #12 │ │ ldc2l 9, cr5, [lr, #270] @ 0x10e @ │ │ - ldc2l 1, cr8, [pc, #56] @ 242dc10 │ │ + ldc2l 1, cr8, [pc, #236] @ 242dcc4 │ │ stc2l 15, cr0, [r2, #808]! @ 0x328 │ │ - ldc2l 14, cr15, [pc, #696] @ 242de98 │ │ + ldc2l 14, cr15, [pc, #876] @ 242df4c │ │ orrseq r2, sl, r8, lsl r4 │ │ orrseq r2, sl, ip, lsr #9 │ │ orrseq r2, sl, r0, asr #8 │ │ eorseq r9, r2, ip, lsl #17 │ │ orrseq r2, sl, r0, lsr #1 │ │ orrseq ip, r6, r4, lsl #9 │ │ orrseq r3, sp, r8, asr #8 │ │ orrseq r2, sl, r8, lsl r0 │ │ stc2l 9, cr15, [r0, #128]! @ 0x80 @ │ │ - ldc2l 15, cr7, [pc, #936] @ 242dfb0 │ │ + ldc2l 0, cr8, [pc, #92] @ 242dc64 │ │ ldrshteq r9, [r2], -r8 │ │ orrseq r2, sl, ip │ │ - ldc2l 15, cr7, [pc, #684] @ 242dec0 │ │ + ldc2l 15, cr7, [pc, #864] @ 242df74 │ │ stc2l 10, cr2, [r2, #400]! @ 0x190 @ │ │ orrseq r1, sl, ip, ror pc │ │ - ldc2l 15, cr7, [pc, #456] @ 242dde8 │ │ + ldc2l 15, cr7, [pc, #636] @ 242de9c │ │ orrseq ip, r6, r0, lsr #7 │ │ orrseq r3, sp, ip, asr #6 │ │ orrseq r3, sp, r4, ror r3 │ │ stc2l 3, cr13, [r1, #132]! @ 0x84 │ │ - ldc2l 4, cr8, [pc, #616] @ 242de9c │ │ + ldc2l 4, cr8, [pc, #796] @ 242df50 │ │ orrseq r2, r6, r4, ror #23 │ │ stc2l 6, cr3, [r1, #664]! @ 0x298 │ │ - ldc2l 14, cr7, [pc, #760] @ 242df38 │ │ + ldc2l 14, cr7, [pc, #940] @ 242dfec │ │ orrseq r2, r6, ip, lsl #8 │ │ ldc2l 6, cr5, [lr, #860] @ 0x35c │ │ orrseq r2, r6, r0, asr r4 │ │ stc2l 12, cr0, [r2, #888]! @ 0x378 │ │ - ldc2l 11, cr15, [pc, #776] @ 242df5c @ │ │ + ldc2l 11, cr15, [pc, #956] @ 242e010 @ │ │ orrseq r2, sl, ip, lsr #2 │ │ orrseq r2, sl, r8, lsl #15 │ │ orrseq r2, sl, r4, asr r1 │ │ mlaseq r2, ip, r5, r9 │ │ @ instruction: 0x019a1db0 │ │ @ instruction: 0x0196c190 │ │ orrseq r3, sp, r4, asr r1 │ │ orrseq r1, sl, r4, lsr #26 │ │ stc2l 6, cr15, [r0, #368]! @ 0x170 │ │ - ldc2l 13, cr7, [pc, #24] @ 242dc94 │ │ + ldc2l 13, cr7, [pc, #204] @ 242dd48 │ │ eorseq r9, r2, r4, lsl r5 │ │ orrseq r1, sl, r8, lsr #26 │ │ - ldc2l 12, cr7, [pc, #796] @ 242dfa4 │ │ + ldc2l 12, cr7, [pc, #976] @ 242e058 │ │ stc2l 7, cr2, [r2, #496]! @ 0x1f0 │ │ @ instruction: 0x019a1c94 │ │ - ldc2l 12, cr7, [pc, #568] @ 242decc │ │ + ldc2l 12, cr7, [pc, #748] @ 242df80 │ │ ldrheq ip, [r6, ip] │ │ orrseq r3, sp, r4, rrx │ │ - ldc2l 11, cr1, [pc, #640] @ 242df20 @ │ │ + ldc2l 11, cr1, [pc, #820] @ 242dfd4 @ │ │ orrseq ip, r6, r8, rrx │ │ - ldc2l 9, cr8, [pc, #478] @ 242de86 @ │ │ - ldc2l 9, cr8, [pc, #484] @ 242de90 @ │ │ - ldc2l 9, cr8, [pc, #452] @ 242de74 @ │ │ + ldc2l 10, cr8, [pc, #112] @ 242dd18 @ │ │ + ldc2l 10, cr8, [pc, #124] @ 242dd28 @ │ │ + ldc2l 10, cr8, [pc, #60] @ 242dcec @ │ │ @ instruction: 0x019a29bc │ │ @ instruction: 0x019d3db4 │ │ - ldc2l 9, cr2, [pc, #24] @ 242dcd4 @ │ │ + ldc2l 9, cr2, [pc, #114] @ 242dd2e @ │ │ │ │ 0242dcb8 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ beq 242dcd4 │ │ @@ -1283726,15 +1283726,15 @@ │ │ add r0, pc, r0 │ │ bl 270da10 │ │ mov r0, r4 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, sl, fp, pc} │ │ - ldc2l 9, cr13, [lr, #232] @ 0xe8 @ │ │ + ldc2l 9, cr13, [lr, #322] @ 0x142 @ │ │ stc2l 7, cr12, [r1, #872]! @ 0x368 │ │ │ │ 0242dd14 : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #24 │ │ mov r3, r1 │ │ @@ -1284844,15 +1284844,15 @@ │ │ cmp r0, #0 │ │ beq 2431860 │ │ movw r0, #26003 @ 0x6593 │ │ str r0, [r6] │ │ ldr r0, [pc, #3792] @ 242fd30 │ │ add r0, pc, r0 │ │ b 2433bc4 │ │ - ldc2l 5, cr15, [pc, #1012] @ 242f260 │ │ + ldc2l 6, cr15, [pc, #168] @ 242ef14 │ │ eorseq r9, r2, ip, lsr #32 │ │ adceq r9, r5, #28, 22 @ 0x7000 │ │ rsbeq r1, r6, #52, 30 @ 0xd0 │ │ @ instruction: 0x0324944c │ │ rsceq r1, r5, #164, 14 @ 0x2900000 │ │ movteq r2, #5768 @ 0x1688 │ │ movteq r2, #5836 @ 0x16cc │ │ @@ -1284872,22 +1284872,22 @@ │ │ eorseq r8, r2, r8, asr #30 │ │ eorseq r8, r2, r4, asr #30 │ │ movteq r2, #5548 @ 0x15ac │ │ orrseq ip, sp, r4, lsr r8 │ │ mvnseq sp, r4, ror #27 │ │ mvneq r9, r4, lsr #10 │ │ ldc2l 14, cr8, [lr, #284] @ 0x11c │ │ - ldc2l 6, cr7, [pc, #756] @ 242f1d0 │ │ + ldc2l 6, cr7, [pc, #936] @ 242f284 │ │ mvnseq r4, r4, ror r7 │ │ @ instruction: 0x019dc7d8 │ │ orrseq ip, sp, r8, asr #15 │ │ stc2l 5, cr0, [r2, #148]! @ 0x94 │ │ mvnseq r4, r4, lsl r7 │ │ @ instruction: 0x019dc790 │ │ - ldc2l 3, cr15, [pc, #1008] @ 242f2e8 │ │ + ldc2l 4, cr15, [pc, #164] @ 242ef9c │ │ orrseq ip, sp, r8, asr r7 │ │ stc2l 10, cr4, [r1, #112]! @ 0x70 @ │ │ stc2l 7, cr8, [r1, #396]! @ 0x18c │ │ ldrsbteq r8, [r2], -r4 │ │ adceq r9, r5, #196, 16 @ 0xc40000 │ │ rsbeq r1, r6, #220, 24 @ 0xdc00 │ │ @ instruction: 0x032491f4 │ │ @@ -1285086,29 +1285086,29 @@ │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 242f1a0 │ │ movteq r2, #4948 @ 0x1354 │ │ movteq r2, #4988 @ 0x137c │ │ stc2l 3, cr0, [r2, #212]! @ 0xd4 │ │ - ldc2l 4, cr7, [pc, #388] @ 242f3b8 │ │ + ldc2l 4, cr7, [pc, #568] @ 242f46c │ │ mvnseq r4, ip, lsl r5 │ │ movteq r2, #4908 @ 0x132c │ │ stc2l 2, cr0, [r2, #948]! @ 0x3b4 │ │ - ldc2l 4, cr7, [pc, #100] @ 242f2a8 │ │ + ldc2l 4, cr7, [pc, #280] @ 242f35c │ │ @ instruction: 0x019dc5b0 │ │ stc2l 8, cr4, [r1, #96]! @ 0x60 │ │ - ldc2l 3, cr7, [pc, #900] @ 242f5d4 │ │ + ldc2l 4, cr7, [pc, #56] @ 242f288 │ │ mvneq r9, r8, lsr #4 │ │ mvnseq r7, r4, lsl #2 │ │ - ldc2l 3, cr7, [pc, #612] @ 242f4c0 │ │ + ldc2l 3, cr7, [pc, #792] @ 242f574 │ │ orrseq ip, sp, ip, lsl r5 │ │ stc2l 2, cr0, [r2, #176]! @ 0xb0 │ │ stc2l 7, cr4, [r1, #336]! @ 0x150 │ │ - ldc2l 1, cr11, [pc, #852] @ 242f5c0 │ │ + ldc2l 2, cr11, [pc, #8] @ 242f274 │ │ eorseq r8, r2, ip, lsl #22 │ │ adceq r9, r5, #252, 10 @ 0x3f000000 │ │ rsbeq r1, r6, #20, 20 @ 0x14000 │ │ @ instruction: 0x03248f2c │ │ rsceq r1, r5, #132, 4 @ 0x40000008 │ │ movteq r2, #4456 @ 0x1168 │ │ movteq r2, #4524 @ 0x11ac │ │ @@ -1285291,16 +1285291,16 @@ │ │ b 242f584 │ │ mvnseq sp, r4, ror r8 │ │ strheq r8, [pc, #248] @ 242f64c │ │ ldrheq r6, [pc, #224] @ 242f638 │ │ mvnseq r4, r4, lsl r2 │ │ movteq r2, #4112 @ 0x1010 │ │ movteq fp, #9840 @ 0x2670 │ │ - ldc2l 15, cr10, [pc, #884] @ 242f8dc │ │ - ldc2l 11, cr4, [pc, #168] @ 242f614 @ │ │ + ldc2l 0, cr11, [pc, #40] @ 242f590 │ │ + ldc2l 11, cr4, [pc, #348] @ 242f6c8 @ │ │ ldr r0, [fp, #-72] @ 0xffffffb8 │ │ add r1, r7, r1, lsl #5 │ │ ldr r2, [fp, #80] @ 0x50 │ │ mov r3, #32 │ │ bl 270d9d0 │ │ cmp r0, #0 │ │ beq 2432918 │ │ @@ -1285328,39 +1285328,39 @@ │ │ movw r3, #4576 @ 0x11e0 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 242f568 │ │ movteq r1, #8108 @ 0x1fac │ │ stc2l 10, cr14, [r0, #248]! @ 0xf8 @ │ │ - ldc2l 14, cr2, [pc, #196] @ 242f6c0 │ │ + ldc2l 14, cr2, [pc, #376] @ 242f774 │ │ ldrhteq r8, [r2], -r8 │ │ - ldc2l 12, cr12, [pc, #976] @ 242f9d4 │ │ + ldc2l 13, cr12, [pc, #132] @ 242f688 │ │ movteq r1, #8040 @ 0x1f68 │ │ - stc2l 12, cr2, [r0, #816]! @ 0x330 │ │ - ldc2l 15, cr12, [lr, #916] @ 0x394 │ │ - ldc2l 10, cr4, [pc, #520] @ 242f81c @ │ │ - stc2l 10, cr4, [r0, #112]! @ 0x70 @ │ │ + stc2l 12, cr2, [r0, #996]! @ 0x3e4 │ │ + ldc2l 0, cr13, [lr, #72] @ 0x48 │ │ + ldc2l 10, cr4, [pc, #700] @ 242f8d0 @ │ │ + stc2l 10, cr4, [r0, #292]! @ 0x124 @ │ │ stc2l 4, cr4, [r1, #204]! @ 0xcc │ │ movteq r1, #7884 @ 0x1ecc │ │ ldrshteq r8, [r2], -ip │ │ orrseq ip, sp, r8, asr r1 │ │ - ldc2l 13, cr10, [pc, #224] @ 242f70c │ │ + ldc2l 13, cr10, [pc, #404] @ 242f7c0 │ │ ldc2l 6, cr8, [lr, #924] @ 0x39c │ │ movteq r1, #7748 @ 0x1e44 │ │ - ldc2l 11, cr10, [pc, #476] @ 242f814 @ │ │ - stc2l 9, cr4, [r0, #128]! @ 0x80 @ │ │ + ldc2l 11, cr10, [pc, #656] @ 242f8c8 @ │ │ + stc2l 9, cr4, [r0, #218]! @ 0xda @ │ │ vcmla.f16 d26, d16, d6, #270 │ │ movteq r1, #7648 @ 0x1de0 │ │ stc2l 8, cr14, [r0, #456]! @ 0x1c8 │ │ - ldc2l 12, cr2, [pc, #404] @ 242f7e0 │ │ + ldc2l 12, cr2, [pc, #584] @ 242f894 │ │ eorseq r8, r2, ip, ror #13 │ │ - ldc2l 11, cr12, [pc, #160] @ 242f6f4 @ │ │ + ldc2l 11, cr12, [pc, #340] @ 242f7a8 @ │ │ movteq r1, #7580 @ 0x1d9c │ │ - stc2l 11, cr2, [r0] @ │ │ + stc2l 11, cr2, [r0, #180]! @ 0xb4 @ │ │ bl 270ce80 │ │ cmp r0, #0 │ │ bne 2433bcc │ │ ldr r0, [pc, #3592] @ 2430474 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ce90 │ │ @@ -1285475,15 +1285475,15 @@ │ │ beq 2431920 │ │ ldr r1, [fp, #76] @ 0x4c │ │ mov r0, sl │ │ bl 270ea40 │ │ ldr r0, [pc, #4040] @ 2430804 │ │ add r0, pc, r0 │ │ b 2433bc4 │ │ - ldc2l 14, cr12, [lr, #100] @ 0x64 │ │ + ldc2l 14, cr12, [lr, #280] @ 0x118 │ │ stc2l 7, cr10, [r0, #888]! @ 0x378 │ │ stc2l 1, cr6, [r1, #48]! @ 0x30 │ │ eorseq r8, r2, ip, asr r6 │ │ rsbeq r1, r6, #108, 10 @ 0x1b000000 │ │ @ instruction: 0x03248a84 │ │ rsceq r0, r5, #220, 26 @ 0x3700 │ │ movteq r1, #7360 @ 0x1cc0 │ │ @@ -1285502,22 +1285502,22 @@ │ │ @ instruction: 0x019dbefc │ │ eorseq r8, r2, ip, ror r5 │ │ eorseq r8, r2, r8, ror r5 │ │ eorseq r8, r2, r8, ror r5 │ │ eorseq r8, r2, r4, ror r5 │ │ movteq r1, #7176 @ 0x1c08 │ │ stc2l 11, cr15, [r1, #772]! @ 0x304 @ │ │ - ldc2l 12, cr6, [pc, #948] @ 242fc68 │ │ + ldc2l 13, cr6, [pc, #104] @ 242f91c │ │ mvnseq r3, r8, lsr #27 │ │ movteq r1, #7096 @ 0x1bb8 │ │ stc2l 11, cr15, [r1, #484]! @ 0x1e4 @ │ │ - ldc2l 12, cr6, [pc, #660] @ 242fb58 │ │ + ldc2l 12, cr6, [pc, #840] @ 242fc0c │ │ orrseq fp, sp, r4, asr sp │ │ stc2l 0, cr4, [r1, #640]! @ 0x280 │ │ - ldc2l 12, cr6, [pc, #420] @ 242fa74 │ │ + ldc2l 12, cr6, [pc, #600] @ 242fb28 │ │ mvneq r8, ip, lsr #21 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ bne 2433bcc │ │ ldr r0, [pc, #3876] @ 2430808 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ @@ -1285618,15 +1285618,15 @@ │ │ str r1, [r0] │ │ mov r0, #1 │ │ ldr r4, [pc, #3584] @ 2430870 │ │ ldr r5, [fp, #-72] @ 0xffffffb8 │ │ add r4, pc, r4 │ │ b 242faac │ │ mvnseq r6, ip, lsl #19 │ │ - ldc2l 12, cr6, [pc, #132] @ 242fb08 │ │ + ldc2l 12, cr6, [pc, #312] @ 242fbbc │ │ @ instruction: 0x019dbcbc │ │ stc2l 10, cr15, [r1, #720]! @ 0x2d0 @ │ │ ldr r1, [pc, #3556] @ 2430874 │ │ ldr r1, [pc, r1] │ │ ldr r2, [pc, #3552] @ 2430878 │ │ add r0, r1, #1 │ │ add r2, pc, r2 │ │ @@ -1285673,15 +1285673,15 @@ │ │ orrseq fp, sp, ip, lsr #24 │ │ eorseq r8, r2, ip, lsr #5 │ │ eorseq r8, r2, r8, lsr #5 │ │ eorseq r8, r2, r8, lsr #5 │ │ eorseq r8, r2, r4, lsr #5 │ │ movteq r1, #6456 @ 0x1938 │ │ stc2l 8, cr15, [r1, #964]! @ 0x3c4 │ │ - ldc2l 10, cr6, [pc, #116] @ 242fbd4 @ │ │ + ldc2l 10, cr6, [pc, #296] @ 242fc88 @ │ │ ldrsbeq r3, [ip, #168]! @ 0xa8 │ │ movteq r1, #6376 @ 0x18e8 │ │ ldr r0, [pc, #3976] @ 2430af4 │ │ add r0, pc, r0 │ │ ldr r0, [r0, r1, lsl #2] │ │ str r0, [r4] │ │ cmp r0, #0 │ │ @@ -1285769,37 +1285769,37 @@ │ │ ldr r2, [pc, #4012] @ 2430c70 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 242fb64 │ │ vcmla.f16 d31, d17, d25, #270 │ │ - ldc2l 9, cr6, [pc, #426] @ 242fe8a @ │ │ + ldc2l 10, cr6, [pc, #8] @ 242fce8 @ │ │ bl 270ce80 │ │ cmp r0, #0 │ │ bne 2433bcc │ │ ldr r0, [pc, #3972] @ 2430c74 │ │ mov r2, r4 │ │ ldr r1, [fp, #72] @ 0x48 │ │ add r0, pc, r0 │ │ bl 270ea50 │ │ b 2433bcc │ │ orrseq fp, sp, r4, lsl #21 │ │ stc2l 13, cr3, [r1, #848]! @ 0x350 │ │ - ldc2l 9, cr6, [pc, #314] @ 242fe4a @ │ │ + ldc2l 9, cr6, [pc, #404] @ 242fea4 @ │ │ mvneq r8, r0, ror #15 │ │ mvnseq r6, r0, asr #13 │ │ - ldc2l 9, cr6, [pc, #170] @ 242fdc6 @ │ │ + ldc2l 9, cr6, [pc, #260] @ 242fe20 @ │ │ @ instruction: 0x019db9f0 │ │ stc2l 7, cr15, [r1, #928]! @ 0x3a0 │ │ orrseq fp, sp, r0, asr #19 │ │ stc2l 13, cr3, [r1, #32]! │ │ - ldc2l 3, cr4, [pc, #4] @ 242fd34 │ │ + ldc2l 3, cr4, [pc, #184] @ 242fde8 │ │ ldc2l 10, cr10, [lr, #444] @ 0x1bc @ │ │ - ldc2l 2, cr4, [pc, #756] @ 243002c │ │ + ldc2l 2, cr4, [pc, #936] @ 24300e0 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ bne 2433bcc │ │ ldr r0, [pc, #4036] @ 2430d0c │ │ mov r1, #6 │ │ ldr r8, [fp, #12] │ │ add r0, pc, r0 │ │ @@ -1285908,15 +1285908,15 @@ │ │ cmp r0, #0 │ │ bne 242febc │ │ ldr r0, [pc, #4076] @ 2430ee4 │ │ ldr r0, [pc, r0] │ │ add r0, r0, #1 │ │ str r0, [r9] │ │ b 242febc │ │ - ldc2l 7, cr8, [pc, #800] @ 243022c │ │ + ldc2l 7, cr8, [pc, #980] @ 24302e0 │ │ eorseq r7, r2, r4, lsr #31 │ │ rsbeq r0, r6, #172, 28 @ 0xac0 │ │ @ instruction: 0x032483c4 │ │ rsceq r0, r5, #12, 14 @ 0x300000 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ bne 2433bcc │ │ @@ -1286004,25 +1286004,25 @@ │ │ add r0, pc, r0 │ │ mov r1, #17 │ │ bl 270da10 │ │ ldr r0, [pc, #3808] @ 2430f5c │ │ add r0, pc, r0 │ │ b 2433bc4 │ │ stc2l 5, cr15, [r1, #20]! │ │ - ldc2l 6, cr6, [pc, #196] @ 2430150 │ │ + ldc2l 6, cr6, [pc, #376] @ 2430204 │ │ mvnseq r3, ip, ror #13 │ │ movteq r1, #5372 @ 0x14fc │ │ stc2l 4, cr15, [r1, #756]! @ 0x2f4 │ │ - ldc2l 5, cr6, [pc, #932] @ 2430440 │ │ + ldc2l 6, cr6, [pc, #88] @ 24300f4 │ │ @ instruction: 0x019db698 │ │ stc2l 9, cr3, [r1, #464]! @ 0x1d0 @ │ │ - ldc2l 5, cr6, [pc, #708] @ 243036c │ │ + ldc2l 5, cr6, [pc, #888] @ 2430420 │ │ strdeq r8, [pc, #56] @ 24300e4 │ │ ldrsbeq r6, [pc, #36] @ 24300d4 │ │ - ldc2l 5, cr6, [pc, #420] @ 2430258 │ │ + ldc2l 5, cr6, [pc, #600] @ 243030c │ │ orrseq fp, sp, r8, asr #11 │ │ stc2l 3, cr15, [r1, #768]! @ 0x300 │ │ vcmla.f16 , , q12, #270 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ bne 2433bcc │ │ ldr r0, [pc, #4024] @ 2431088 │ │ @@ -1286112,15 +1286112,15 @@ │ │ mov r2, r5 │ │ mov r3, #32 │ │ add r1, pc, r1 │ │ bl 270ea60 │ │ ldr r0, [pc, #3924] @ 2431184 │ │ add r0, pc, r0 │ │ b 2433bc4 │ │ - ldc2l 3, cr12, [lr, #424] @ 0x1a8 │ │ + ldc2l 3, cr12, [lr, #604] @ 0x25c │ │ eorseq r7, r2, r0, ror #23 │ │ rsbeq r0, r6, #232, 20 @ 0xe8000 │ │ @ instruction: 0x03248000 │ │ rsceq r0, r5, #72, 6 @ 0x20000001 │ │ movteq r1, #4676 @ 0x1244 │ │ movteq r1, #4744 @ 0x1288 │ │ teqeq r4, #236, 28 @ 0xec0 │ │ @@ -1286241,25 +1286241,25 @@ │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #4072] @ 2431414 │ │ add r0, pc, r0 │ │ b 2433bc4 │ │ movteq r1, #4464 @ 0x1170 │ │ stc2l 1, cr15, [r1, #164]! @ 0xa4 │ │ - ldc2l 2, cr6, [pc, #340] @ 2430594 │ │ + ldc2l 2, cr6, [pc, #520] @ 2430648 │ │ mvnseq r3, r0, lsl r3 │ │ movteq r1, #4384 @ 0x1120 │ │ stc2l 0, cr15, [r1, #900]! @ 0x384 │ │ - ldc2l 2, cr6, [pc, #52] @ 2430484 │ │ + ldc2l 2, cr6, [pc, #232] @ 2430538 │ │ @ instruction: 0x019db2bc │ │ stc2l 6, cr3, [r1, #48]! @ 0x30 │ │ - ldc2l 1, cr6, [pc, #852] @ 24307b0 │ │ + ldc2l 2, cr6, [pc, #8] @ 2430464 │ │ mvneq r8, r8, lsl r0 │ │ ldrsheq r5, [pc, #228] @ 2430548 │ │ - ldc2l 1, cr6, [pc, #564] @ 243069c │ │ + ldc2l 1, cr6, [pc, #744] @ 2430750 │ │ stc2l 0, cr15, [r1, #368]! @ 0x170 │ │ orrseq fp, sp, r0, lsl #4 │ │ @ instruction: 0x019db1d4 │ │ stc2l 5, cr3, [r1, #112]! @ 0x70 │ │ stc2l 9, cr13, [r0, #326]! @ 0x146 @ │ │ eorseq r7, r2, r8, ror #16 │ │ rsbeq r0, r6, #120, 14 @ 0x1e00000 │ │ @@ -1286485,15 +1286485,15 @@ │ │ movw r3, #5816 @ 0x16b8 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2430780 │ │ movteq sl, #9220 @ 0x2404 │ │ stc2l 7, cr13, [r0, #860]! @ 0x35c │ │ - stc2l 8, cr3, [r0, #68]! @ 0x44 │ │ + stc2l 8, cr3, [r0, #248]! @ 0xf8 │ │ ldrshteq r7, [r2], -r0 │ │ rsbeq r0, r6, #0, 10 │ │ @ instruction: 0x03247a18 │ │ rsceq pc, r4, #112, 26 @ 0x1c00 │ │ movteq r0, #7252 @ 0x1c54 │ │ movteq r0, #7320 @ 0x1c98 │ │ teqeq r4, #0, 18 │ │ @@ -1286515,15 +1286515,15 @@ │ │ orrseq sl, sp, r8, ror #27 │ │ orrseq sl, sp, r8, ror #27 │ │ @ instruction: 0x019dadd8 │ │ orrseq sl, sp, r8, asr #27 │ │ @ instruction: 0x019dad94 │ │ orrseq sl, sp, r8, lsl #27 │ │ stc2l 10, cr14, [r1, #836]! @ 0x344 @ │ │ - ldc2l 11, cr5, [pc, #1012] @ 2430c7c @ │ │ + ldc2l 12, cr5, [pc, #168] @ 2430930 │ │ ldrheq r2, [ip, #200]! @ 0xc8 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ bne 2433bcc │ │ ldr r0, [pc, #4092] @ 2431898 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ @@ -1286706,22 +1286706,22 @@ │ │ mov r2, r5 │ │ movw r3, #4983 @ 0x1377 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2430af8 │ │ stc2l 15, cr2, [r1, #400]! @ 0x190 │ │ - ldc2l 11, cr5, [pc, #180] @ 2430c38 @ │ │ + ldc2l 11, cr5, [pc, #360] @ 2430cec @ │ │ mvneq r7, r8, ror #18 │ │ stc2l 5, cr15, [r0, #100]! @ 0x64 │ │ vcadd.f32 d25, d14, d13, #270 │ │ orrseq sl, sp, r4, lsr ip │ │ orrseq sl, sp, r8, lsl ip │ │ stc2l 14, cr2, [r1, #736]! @ 0x2e0 │ │ - ldc2l 10, cr5, [pc, #516] @ 2430da4 @ │ │ + ldc2l 10, cr5, [pc, #696] @ 2430e58 @ │ │ mvneq r7, r4, asr #17 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ bne 2433bcc │ │ ldr r4, [pc, #4060] @ 2431b90 │ │ mov r1, #8 │ │ ldr r8, [fp, #104] @ 0x68 │ │ @@ -1286767,15 +1286767,15 @@ │ │ str r8, [sp] │ │ bl 270e4b0 │ │ mov r0, r4 │ │ mov r1, #8 │ │ b 2433bc8 │ │ @ instruction: 0x019dab98 │ │ stc2l 8, cr14, [r1, #880]! @ 0x370 │ │ - ldc2l 10, cr5, [pc, #4] @ 2430c7c @ │ │ + ldc2l 10, cr5, [pc, #184] @ 2430d30 @ │ │ movteq r0, #6276 @ 0x1884 │ │ ldr r0, [pc, #3884] @ 2431bac │ │ ldr r1, [pc, #3884] @ 2431bb0 │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ bl 270e110 │ │ ldr r0, [pc, #3872] @ 2431bb4 │ │ @@ -1286948,20 +1286948,20 @@ │ │ add r7, pc, r7 │ │ b 2430f98 │ │ ldc2l 15, cr2, [lr, #960] @ 0x3c0 │ │ stc2l 5, cr10, [r1, #488]! @ 0x1e8 │ │ stc2l 14, cr0, [r1, #956]! @ 0x3bc │ │ movteq r0, #5572 @ 0x15c4 │ │ stc2l 0, cr13, [r0, #344]! @ 0x158 │ │ - ldc2l 4, cr1, [pc, #292] @ 2431070 │ │ + ldc2l 4, cr1, [pc, #472] @ 2431124 │ │ ldrsbteq r6, [r2], -r0 │ │ - ldc2l 3, cr11, [pc, #48] @ 2430f84 │ │ + ldc2l 3, cr11, [pc, #228] @ 2431038 │ │ movteq r0, #5504 @ 0x1580 │ │ - stc2l 2, cr1, [r0, #912]! @ 0x390 │ │ - ldc2l 5, cr11, [lr, #1012] @ 0x3f4 │ │ + stc2l 3, cr1, [r0, #68]! @ 0x44 │ │ + ldc2l 6, cr11, [lr, #168] @ 0xa8 │ │ stc2l 14, cr0, [r1, #284]! @ 0x11c │ │ ldr r0, [pc, #4036] @ 2431f2c │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #4032] @ 2431f30 │ │ add r0, r0, #1 │ │ add r1, pc, r1 │ │ str r0, [r1] │ │ @@ -1287029,15 +1287029,15 @@ │ │ mov r2, #1 │ │ add r1, pc, r1 │ │ bl 270db00 │ │ ldr r0, [pc, #3884] @ 2431fac │ │ mov r1, #21 │ │ add r0, pc, r0 │ │ b 243112c │ │ - stc2l 0, cr3, [r0, #40]! @ 0x28 │ │ + stc2l 0, cr3, [r0, #220]! @ 0xdc │ │ eorseq r6, r2, r4, lsl #28 │ │ rsbeq pc, r5, #20, 26 @ 0x500 │ │ @ instruction: 0x0324722c │ │ rsceq pc, r4, #132, 10 @ 0x21000000 │ │ movteq r0, #5224 @ 0x1468 │ │ movteq r0, #5292 @ 0x14ac │ │ ldr r0, [pc, #3844] @ 2431fb0 │ │ @@ -1287092,15 +1287092,15 @@ │ │ orrseq sl, sp, r4, lsr #13 │ │ eorseq r6, r2, r4, lsr #26 │ │ eorseq r6, r2, r0, lsr #26 │ │ eorseq r6, r2, r0, lsr #26 │ │ eorseq r6, r2, ip, lsl sp │ │ adceq r7, r5, #252, 14 @ 0x3f00000 │ │ adceq r7, r5, #208, 14 @ 0x3400000 │ │ - stc2l 14, cr2, [r0, #696]! @ 0x2b8 │ │ + stc2l 14, cr2, [r0, #876]! @ 0x36c │ │ stc2l 14, cr12, [r0, #376]! @ 0x178 │ │ eorseq r6, r2, r0, lsr ip │ │ adceq r7, r5, #32, 14 @ 0x800000 │ │ rsbeq pc, r5, #56, 22 @ 0xe000 │ │ ldr r7, [pc, #3636] @ 2431fd4 │ │ ldr r0, [pc, #3636] @ 2431fd8 │ │ ldr r1, [pc, #3636] @ 2431fdc │ │ @@ -1287199,15 +1287199,15 @@ │ │ @ instruction: 0x019da4d0 │ │ eorseq r6, r2, r0, asr fp │ │ eorseq r6, r2, ip, asr #22 │ │ eorseq r6, r2, ip, asr #22 │ │ eorseq r6, r2, r8, asr #22 │ │ adceq r7, r5, #28, 12 @ 0x1c00000 │ │ stc2l 2, cr10, [r1, #820]! @ 0x334 │ │ - ldc2l 10, cr2, [pc, #980] @ 243170c @ │ │ + ldc2l 11, cr2, [pc, #136] @ 24313c0 @ │ │ ldr r0, [pc, #3788] @ 2432208 │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ movw r0, #26003 @ 0x6593 │ │ cmp r1, r0 │ │ bcc 2431368 │ │ ldr r0, [pc, #3768] @ 243220c │ │ @@ -1287255,15 +1287255,15 @@ │ │ ldr r5, [pc, #4084] @ 24323f0 │ │ add r8, pc, r8 │ │ add sl, pc, sl │ │ movt r4, #12 │ │ add r5, pc, r5 │ │ mov r9, #10 │ │ b 2431430 │ │ - stc2l 15, cr0, [r0, #156]! @ 0x9c │ │ + stc2l 15, cr0, [r0, #336]! @ 0x150 │ │ stc2l 12, cr12, [r0, #872]! @ 0x368 │ │ ldr r0, [sl, r1, lsl #2] │ │ ldr r1, [pc, #4048] @ 24323f4 │ │ add r1, pc, r1 │ │ cmp r0, #0 │ │ str r0, [r1] │ │ ble 24328fc │ │ @@ -1287297,15 +1287297,15 @@ │ │ ldr r0, [pc, #3936] @ 2432404 │ │ mov r2, r5 │ │ movw r3, #2299 @ 0x8fb │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2431418 │ │ - ldc2l 15, cr12, [pc, #992] @ 24318a0 │ │ + ldc2l 0, cr13, [pc, #148] @ 2431554 │ │ eorseq r6, r2, r0, lsl #20 │ │ rsbeq pc, r5, #8, 18 @ 0x20000 │ │ @ instruction: 0x03246e20 │ │ rsceq pc, r4, #104, 2 │ │ movteq r0, #4196 @ 0x1064 │ │ movteq r0, #4264 @ 0x10a8 │ │ ldr r0, [pc, #3884] @ 2432408 │ │ @@ -1287396,15 +1287396,15 @@ │ │ add r5, pc, r5 │ │ add r8, pc, r8 │ │ mov r4, #10 │ │ add r9, pc, r9 │ │ b 2431660 │ │ movteq pc, #3952 @ 0xf70 @ │ │ stc2l 15, cr13, [r1, #164]! @ 0xa4 │ │ - ldc2l 0, cr5, [pc, #340] @ 24317a0 │ │ + ldc2l 0, cr5, [pc, #520] @ 2431854 │ │ mvnseq r2, r0, lsl r1 │ │ movteq pc, #3872 @ 0xf20 @ │ │ ldr r0, [r5, r1, lsl #2] │ │ str r0, [r6] │ │ cmp r0, #0 │ │ ble 24330e0 │ │ ldr r1, [fp, #20] │ │ @@ -1287422,21 +1287422,21 @@ │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2431650 │ │ ldr r5, [pc, #3944] @ 243260c │ │ add r5, pc, r5 │ │ b 2431764 │ │ stc2l 14, cr13, [r1, #900]! @ 0x384 │ │ - ldc2l 0, cr5, [pc, #52] @ 24316e8 │ │ + ldc2l 0, cr5, [pc, #232] @ 243179c │ │ ldrheq sl, [sp, ip] │ │ stc2l 4, cr2, [r1, #48]! @ 0x30 │ │ - ldc2l 15, cr4, [pc, #852] @ 2431a14 │ │ + ldc2l 0, cr5, [pc, #8] @ 24316c8 │ │ mvneq r6, r8, lsl lr │ │ ldrsheq r4, [pc, #200] @ 2431790 │ │ - ldc2l 15, cr4, [pc, #580] @ 2431910 │ │ + ldc2l 15, cr4, [pc, #760] @ 24319c4 │ │ orrseq r9, sp, r8, ror #31 │ │ stc2l 13, cr13, [r1, #896]! @ 0x380 │ │ stc2l 3, cr2, [r1, #32]! │ │ add r0, sp, #32 │ │ str sl, [sp, #48] @ 0x30 │ │ stm r0, {r6, r9, sl} │ │ mov r0, #80 @ 0x50 │ │ @@ -1287598,22 +1287598,22 @@ │ │ @ instruction: 0x019d9ed0 │ │ eorseq r6, r2, r0, asr r5 │ │ eorseq r6, r2, ip, asr #10 │ │ eorseq r6, r2, ip, asr #10 │ │ eorseq r6, r2, r8, asr #10 │ │ movteq pc, #3012 @ 0xbc4 @ │ │ stc2l 11, cr13, [r1, #500]! @ 0x1f4 @ │ │ - ldc2l 12, cr4, [pc, #676] @ 2431c18 │ │ + ldc2l 12, cr4, [pc, #856] @ 2431ccc │ │ mvnseq r1, r4, ror #26 │ │ movteq pc, #2932 @ 0xb74 @ │ │ stc2l 11, cr13, [r1, #212]! @ 0xd4 @ │ │ - ldc2l 12, cr4, [pc, #388] @ 2431b08 │ │ + ldc2l 12, cr4, [pc, #568] @ 2431bbc │ │ orrseq r9, sp, r0, lsl sp │ │ stc2l 0, cr2, [r1, #384]! @ 0x180 │ │ - ldc2l 12, cr4, [pc, #164] @ 2431a34 │ │ + ldc2l 12, cr4, [pc, #344] @ 2431ae8 │ │ mvneq r6, ip, ror #20 │ │ str r7, [sp, #32] │ │ mov r1, r4 │ │ ldr r0, [pc, #4088] @ 2432998 │ │ mov r2, r6 │ │ mov r3, r8 │ │ add r0, pc, r0 │ │ @@ -1287683,15 +1287683,15 @@ │ │ ldr r3, [pc, #3872] @ 24329cc │ │ add r2, pc, r2 │ │ add r3, pc, r3 │ │ bl 270ea70 │ │ b 2431990 │ │ @ instruction: 0x019d9cbc │ │ mvnseq r4, r4, asr #18 │ │ - ldc2l 11, cr4, [pc, #868] @ 2431e2c @ │ │ + ldc2l 12, cr4, [pc, #24] @ 2431ae0 │ │ ldr r0, [pc, #4076] @ 2432ab8 │ │ mov r1, #119 @ 0x77 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #4064] @ 2432abc │ │ mov r1, r6 │ │ mov r2, #1 │ │ @@ -1287735,15 +1287735,15 @@ │ │ ldr r9, [pc, #3944] @ 2432ae4 │ │ add r6, pc, r6 │ │ ldr sl, [pc, #3940] @ 2432ae8 │ │ add r8, pc, r8 │ │ add r9, pc, r9 │ │ add sl, pc, sl │ │ b 2431c70 │ │ - ldc2l 8, cr14, [pc, #892] @ 2431f14 │ │ + ldc2l 9, cr14, [pc, #24] @ 2431bb0 @ │ │ teqeq r4, #116, 12 @ 0x7400000 │ │ movteq pc, #2496 @ 0x9c0 @ │ │ @ instruction: 0x019d9bf0 │ │ @ instruction: 0x03246704 │ │ rsbeq pc, r5, #196, 2 @ 0x31 │ │ eorseq r6, r2, r4, lsr #5 │ │ eorseq r6, r2, r4, ror #4 │ │ @@ -1287861,25 +1287861,25 @@ │ │ ldr r0, [pc, #3844] @ 2432c78 │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #3840] @ 2432c7c │ │ add r1, pc, r1 │ │ str r0, [r1] │ │ b 2431cfc │ │ stc2l 9, cr9, [r1, #22]! @ │ │ - ldc2l 9, cr4, [pc, #42] @ 2431dba @ │ │ - ldc2l 6, cr12, [pc, #820] @ 24320c8 │ │ + ldc2l 9, cr4, [pc, #132] @ 2431e14 @ │ │ + ldc2l 6, cr12, [pc, #1000] @ 243217c │ │ teqeq r4, #52, 8 @ 0x34000000 │ │ orrseq r9, sp, r8, ror #19 │ │ orrseq r9, sp, r0, lsr r9 │ │ - vcadd.f32 q10, , , #270 │ │ - ldc2l 0, cr2, [pc, #532] @ 2431fbc │ │ + ldc2l 8, cr4, [pc, #576] @ 2431fe4 │ │ + ldc2l 0, cr2, [pc, #712] @ 2432070 │ │ @ instruction: 0x019d99b0 │ │ orrseq r9, sp, ip, ror #17 │ │ stc2l 6, cr13, [r1, #860]! @ 0x35c │ │ - stc2l 2, cr2, [r0, #100]! @ 0x64 │ │ + stc2l 2, cr2, [r0, #280]! @ 0x118 │ │ movteq pc, #1712 @ 0x6b0 @ │ │ ldr r0, [pc, #3776] @ 2432c80 │ │ ldr r0, [pc, r0] │ │ cmp r0, #1 │ │ blt 2431c40 │ │ sub r1, r0, #1 │ │ cmp r0, r7 │ │ @@ -1287996,22 +1287996,22 @@ │ │ rsbeq lr, r5, #100, 28 @ 0x640 │ │ teqeq r4, #148, 4 @ 0x40000009 │ │ orrseq r9, sp, r0, lsl #15 │ │ orrseq r9, sp, r4, ror r7 │ │ orrseq r9, sp, r8, asr r8 │ │ ldc2l 15, cr1, [lr, #660] @ 0x294 │ │ @ instruction: 0x019d97d0 │ │ - ldc2l 14, cr1, [pc, #692] @ 2432260 │ │ + ldc2l 14, cr1, [pc, #872] @ 2432314 │ │ eorseq r5, r2, r0, lsl #29 │ │ stc2l 0, cr14, [r0, #740]! @ 0x2e4 │ │ @ instruction: 0x03246288 │ │ orrseq r9, sp, ip, ror r7 │ │ orrseq r9, sp, r4, asr #13 │ │ stc2l 0, cr15, [r1, #748]! @ 0x2ec │ │ - ldc2l 14, cr1, [pc, #100] @ 243202c │ │ + ldc2l 14, cr1, [pc, #280] @ 24320e0 │ │ orrseq r9, sp, r4, asr #14 │ │ orrseq r9, sp, r0, lsl #13 │ │ stc2l 13, cr15, [r0, #476]! @ 0x1dc │ │ stc2l 0, cr10, [r0, #188]! @ 0xbc │ │ mvnseq r4, r4, lsl #5 │ │ movteq pc, #1036 @ 0x40c @ │ │ @ instruction: 0x019d96bc │ │ @@ -1288137,33 +1288137,33 @@ │ │ cmp r0, #0 │ │ beq 2433bf4 │ │ ldr r0, [pc, #3920] @ 243311c │ │ add r0, pc, r0 │ │ b 2433bc4 │ │ orrseq r9, sp, ip, lsl #13 │ │ stc2l 8, cr1, [r1, #960]! @ 0x3c0 │ │ - ldc2l 4, cr4, [pc, #740] @ 24324c4 │ │ + ldc2l 4, cr4, [pc, #920] @ 2432578 │ │ ldc2l 12, cr5, [lr, #140] @ 0x8c │ │ teqeq r4, #20 │ │ orrseq r9, sp, r8, lsl r6 │ │ rsbeq lr, r5, #160, 22 @ 0x28000 │ │ teqeq r4, #224, 30 @ 0x380 │ │ movteq pc, #840 @ 0x348 @ │ │ rsceq lr, r4, #8, 8 @ 0x8000000 │ │ adceq r6, r5, #96, 14 @ 0x1800000 │ │ @ instruction: 0x03246090 │ │ stc2l 5, cr5, [r1, #620]! @ 0x26c │ │ stc2l 5, cr5, [r1, #524]! @ 0x20c │ │ orrseq r9, sp, r0, asr r4 │ │ - ldc2l 1, cr12, [pc, #336] @ 2432364 │ │ - ldc2l 3, cr4, [pc, #420] @ 24323bc │ │ + ldc2l 1, cr12, [pc, #516] @ 2432418 │ │ + ldc2l 3, cr4, [pc, #600] @ 2432470 │ │ mvnseq sl, ip, ror #20 │ │ @ instruction: 0x019d93f0 │ │ - ldc2l 0, cr12, [pc, #976] @ 24325f4 │ │ - ldc2l 3, cr4, [pc, #36] @ 243224c │ │ + ldc2l 1, cr12, [pc, #132] @ 24322a8 │ │ + ldc2l 3, cr4, [pc, #216] @ 2432300 │ │ @ instruction: 0x019d93b4 │ │ ldr r0, [pc, #3824] @ 2433120 │ │ ldr r0, [pc, r0] │ │ cmp r0, #0 │ │ beq 2432348 │ │ ldr r8, [pc, #3812] @ 2433124 │ │ mov r5, #32 │ │ @@ -1288271,28 +1288271,28 @@ │ │ cmp r0, #0 │ │ beq 2433cac │ │ ldr r0, [pc, #3956] @ 2433358 │ │ add r0, pc, r0 │ │ b 2433bc4 │ │ eorseq r1, r5, #24, 12 @ 0x1800000 │ │ andeq r4, r4, #228, 2 @ 0x39 │ │ - ldc2l 2, cr4, [pc, #772] @ 24326fc │ │ + ldc2l 2, cr4, [pc, #952] @ 24327b0 │ │ orrseq r9, sp, r8, ror #6 │ │ orrseq r9, sp, ip, lsr r3 │ │ ldc2l 11, cr1, [lr, #408] @ 0x198 @ │ │ orrseq r9, sp, ip, lsl #6 │ │ - stc2l 12, cr1, [r0, #116]! @ 0x74 │ │ + stc2l 12, cr1, [r0, #296]! @ 0x128 │ │ @ instruction: 0x019d92b0 │ │ - ldc2l 15, cr11, [pc, #720] @ 24326e4 │ │ - ldc2l 1, cr4, [pc, #804] @ 243273c │ │ + ldc2l 15, cr11, [pc, #900] @ 2432798 │ │ + ldc2l 1, cr4, [pc, #984] @ 24327f0 │ │ mvnseq sl, r8, asr #17 │ │ - ldc2l 1, cr6, [pc, #848] @ 2432770 │ │ + ldc2l 2, cr6, [pc, #4] @ 2432424 │ │ orrseq r9, sp, ip, lsl #4 │ │ - ldc2l 15, cr11, [pc, #64] @ 2432468 │ │ - ldc2l 1, cr4, [pc, #148] @ 24324c0 │ │ + ldc2l 15, cr11, [pc, #244] @ 243251c │ │ + ldc2l 1, cr4, [pc, #328] @ 2432574 │ │ mvnseq sl, r4, lsr #16 │ │ @ instruction: 0x019d9290 │ │ stc2l 7, cr6, [r1, #20]! │ │ ldr r0, [pc, #3872] @ 243335c │ │ ldr r0, [pc, r0] │ │ cmp r0, #0 │ │ beq 2432544 │ │ @@ -1288403,16 +1288403,16 @@ │ │ cmp r0, #0 │ │ beq 2433df0 │ │ ldr r0, [pc, #4092] @ 24335f0 │ │ add r0, pc, r0 │ │ b 2433bc4 │ │ orrseq r9, sp, r0, asr r2 │ │ andeq r3, r4, #184, 30 @ 0x2e0 │ │ - stc2l 10, cr1, [r0, #612]! @ 0x264 @ │ │ - ldc2l 0, cr4, [pc, #580] @ 2432850 │ │ + stc2l 10, cr1, [r0, #792]! @ 0x318 @ │ │ + ldc2l 0, cr4, [pc, #760] @ 2432904 │ │ orrseq r9, sp, r4, lsl r1 │ │ teqeq r4, #184, 22 @ 0x2e000 │ │ mvneq r5, r0, lsr lr │ │ ldrsbeq sl, [sp, #108]! @ 0x6c │ │ andeq r3, r4, #212, 28 @ 0xd40 │ │ eorseq r1, r5, #248, 4 @ 0x8000000f │ │ andeq r6, r2, #204, 18 @ 0x330000 │ │ @@ -1288492,24 +1288492,24 @@ │ │ rsbeq lr, r5, #84, 12 @ 0x5400000 │ │ ldrheq r9, [sp, r8] │ │ rsceq sp, r4, #188, 28 @ 0xbc0 │ │ adceq r6, r5, #12, 4 @ 0xc0000000 │ │ movteq lr, #3524 @ 0xdc4 │ │ @ instruction: 0x03245b28 │ │ stc2l 2, cr1, [r1, #936]! @ 0x3a8 │ │ - ldc2l 6, cr1, [pc, #836] @ 2432ab0 │ │ - vcmla.f16 d17, d16, d17, #270 │ │ + ldc2l 6, cr1, [pc, #1016] @ 2432b64 │ │ + vcmla.f16 , q8, q7, #270 │ │ stc2l 1, cr3, [r1, #224]! @ 0xe0 │ │ stc2l 1, cr3, [r1, #148]! @ 0x94 │ │ stc2l 2, cr11, [r1, #76]! @ 0x4c │ │ - vcadd.f32 d17, d31, d9, #270 │ │ - ldc2l 14, cr5, [pc, #352] @ 24328e4 │ │ + ldc2l 8, cr1, [pc, #728] @ 2432a58 │ │ + ldc2l 14, cr5, [pc, #532] @ 2432998 │ │ stc2l 2, cr1, [r1, #248]! @ 0xf8 │ │ - ldc2l 6, cr1, [pc, #148] @ 2432820 │ │ - stc2l 7, cr1, [r0, #980]! @ 0x3d4 │ │ + ldc2l 6, cr1, [pc, #328] @ 24328d4 │ │ + vcmla.f16 d17, d0, d18, #270 │ │ ldr r0, [pc, #4076] @ 2433780 │ │ add r0, pc, r0 │ │ ldr r0, [r0, r1, lsl #2] │ │ str r0, [r6] │ │ cmp r0, #0 │ │ ble 2431848 │ │ ldr r1, [pc, #4056] @ 2433784 │ │ @@ -1288593,15 +1288593,15 @@ │ │ ldr r0, [pc, #3940] @ 2433848 │ │ mov r2, r5 │ │ movw r3, #5469 @ 0x155d │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 243278c │ │ - ldc2l 13, cr9, [lr, #408] @ 0x198 │ │ + ldc2l 13, cr9, [lr, #588] @ 0x24c │ │ ldr r0, [pc, #4076] @ 24338f0 │ │ add r0, pc, r0 │ │ b 2433bc4 │ │ ldrsheq r3, [pc, #172] @ 24329bc │ │ strdeq r5, [pc, #176] @ 24329c4 │ │ mvnseq sl, r4, lsr #9 │ │ teqeq r4, #28, 18 @ 0x70000 │ │ @@ -1288706,26 +1288706,26 @@ │ │ ldr r1, [fp, #24] │ │ add r4, pc, r4 │ │ add r8, pc, r8 │ │ mov sl, #10 │ │ sub r7, r1, #8 │ │ b 2432b04 │ │ stc2l 0, cr1, [r1, #232]! @ 0xe8 │ │ - ldc2l 4, cr1, [pc, #132] @ 2432b48 │ │ - stc2l 5, cr1, [r0, #964]! @ 0x3c4 │ │ - stc2l 5, cr1, [r0, #996]! @ 0x3e4 │ │ + ldc2l 4, cr1, [pc, #312] @ 2432bfc │ │ + stc2l 6, cr1, [r0, #120]! @ 0x78 │ │ + stc2l 6, cr1, [r0, #152]! @ 0x98 │ │ movteq lr, #2660 @ 0xa64 │ │ adceq r5, r5, #196, 28 @ 0xc40 │ │ @ instruction: 0x019d8cd8 │ │ teqeq r4, #20, 14 @ 0x500000 │ │ movteq lr, #2636 @ 0xa4c │ │ orrseq r8, sp, r0, lsl ip │ │ rsbeq lr, r5, #144, 4 │ │ @ instruction: 0x032457ac │ │ - ldc2l 11, cr3, [pc, #244] @ 2432be4 @ │ │ + ldc2l 11, cr3, [pc, #424] @ 2432c98 @ │ │ ldr r0, [r4, r1, lsl #2] │ │ ldr r1, [pc, #3872] @ 2433a18 │ │ add r1, pc, r1 │ │ cmp r0, #0 │ │ str r0, [r1] │ │ ble 2433efc │ │ ldr r1, [pc, #3856] @ 2433a1c │ │ @@ -1288816,19 +1288816,19 @@ │ │ b 2432d08 │ │ teqeq r4, #248, 10 @ 0x3e000000 │ │ @ instruction: 0x019d8b98 │ │ stc2l 13, cr10, [r1, #880]! @ 0x370 │ │ movteq lr, #2320 @ 0x910 │ │ orrseq r8, sp, r0, lsr #23 │ │ movteq lr, #2200 @ 0x898 │ │ - ldc2l 5, cr15, [pc, #980] @ 2433050 │ │ + ldc2l 6, cr15, [pc, #136] @ 2432d04 │ │ orrseq r8, sp, r8, lsl sl │ │ @ instruction: 0x019d8af0 │ │ orrseq r8, sp, ip, lsr #21 │ │ - ldc2l 5, cr15, [pc, #356] @ 2432df0 │ │ + ldc2l 5, cr15, [pc, #536] @ 2432ea4 │ │ ldc2l 0, cr5, [lr, #316] @ 0x13c │ │ orrseq r8, sp, r0, lsl sl │ │ stc2l 12, cr10, [r1, #336]! @ 0x150 │ │ movteq lr, #1936 @ 0x790 │ │ orrseq r8, sp, r4, lsr #20 │ │ orrseq r8, sp, r0, lsl sl │ │ @ instruction: 0x019d89b0 │ │ @@ -1288963,16 +1288963,16 @@ │ │ movteq lr, #1796 @ 0x704 │ │ teqeq r4, #140, 6 @ 0x30000002 │ │ orrseq r8, sp, r0, lsr #19 │ │ orrseq r8, sp, r4, lsr r9 │ │ stc2l 7, cr8, [r1, #716]! @ 0x2cc │ │ stc2l 1, cr11, [r0, #888]! @ 0x378 │ │ stc2l 11, cr0, [r1, #808]! @ 0x328 @ │ │ - ldc2l 15, cr0, [pc, #708] @ 243318c │ │ - stc2l 1, cr1, [r0, #516]! @ 0x204 │ │ + ldc2l 15, cr0, [pc, #888] @ 2433240 │ │ + stc2l 1, cr1, [r0, #696]! @ 0x2b8 │ │ stc2l 15, cr14, [r0, #304]! @ 0x130 │ │ stc2l 10, cr2, [r1, #32]! @ │ │ eorseq r4, r2, ip, ror #29 │ │ mov r0, r5 │ │ mov r1, #32 │ │ bl 270cf70 │ │ str r0, [fp, #-44] @ 0xffffffd4 │ │ @@ -1289114,15 +1289114,15 @@ │ │ movteq lr, #1128 @ 0x468 │ │ orrseq r8, sp, r8, lsl r7 │ │ andeq r3, r4, #116, 8 @ 0x74000000 │ │ mvnseq r0, ip, lsl r6 │ │ mvnseq r3, ip, lsr #5 │ │ mvneq r5, r0, lsr #7 │ │ mvnseq r9, r4, asr ip │ │ - ldc2l 15, cr0, [pc, #296] @ 243324c │ │ + ldc2l 15, cr0, [pc, #476] @ 2433300 │ │ ldrhteq r4, [r2], -r4 │ │ adceq r5, r5, #164, 14 @ 0x2900000 │ │ rsbeq sp, r5, #188, 22 @ 0x2f000 │ │ @ instruction: 0x032450d4 │ │ rsceq sp, r4, #44, 8 @ 0x2c000000 │ │ movteq lr, #784 @ 0x310 │ │ movteq lr, #852 @ 0x354 │ │ @@ -1289443,24 +1289443,24 @@ │ │ ldr r0, [pc, #3932] @ 2434588 │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ cmp r1, r4 │ │ bcs 243366c │ │ mov r0, r1 │ │ b 24336a0 │ │ - ldc2l 14, cr10, [pc, #384] @ 24337c8 │ │ - ldc2l 0, cr3, [pc, #468] @ 2433820 │ │ + ldc2l 14, cr10, [pc, #564] @ 243387c │ │ + ldc2l 0, cr3, [pc, #648] @ 24338d4 │ │ mvnseq r9, r4, ror r7 │ │ orrseq r8, sp, r0, ror #3 │ │ movteq r7, #9584 @ 0x2570 │ │ orrseq r8, sp, ip, asr r1 │ │ orrseq r8, sp, ip, asr #2 │ │ orrseq r8, sp, ip, asr r1 │ │ orrseq r8, sp, r8, asr r1 │ │ - ldc2l 15, cr2, [pc, #628] @ 24338e0 │ │ + ldc2l 15, cr2, [pc, #808] @ 2433994 │ │ eorseq r0, r5, #228, 4 @ 0x4000000e │ │ ldr r0, [pc, #4064] @ 2434654 │ │ movw r3, #3146 @ 0xc4a │ │ ldr r2, [pc, #4060] @ 2434658 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1289573,15 +1289573,15 @@ │ │ add r1, pc, r1 │ │ b 2433868 │ │ ldc2l 7, cr0, [lr, #568] @ 0x238 │ │ movteq r7, #9160 @ 0x23c8 │ │ orrseq r7, sp, r8, lsl pc │ │ ldc2l 7, cr0, [lr, #264] @ 0x108 │ │ orrseq r7, sp, r8, asr #29 │ │ - stc2l 7, cr0, [r0, #884]! @ 0x374 │ │ + vcmla.f16 d16, d0, d10, #270 │ │ ldr r0, [pc, #3944] @ 24347bc │ │ ldr r0, [pc, r0] │ │ cmp r0, #0 │ │ beq 24339dc │ │ ldr r1, [pc, #3932] @ 24347c0 │ │ mov r0, r6 │ │ add r1, pc, r1 │ │ @@ -1289617,19 +1289617,19 @@ │ │ mov r2, #8 │ │ ldr r1, [pc, #4044] @ 24348b4 │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ b 2433964 │ │ stc2l 0, cr2, [r1, #500]! @ 0x1f4 │ │ orrseq r7, sp, ip, ror #28 │ │ - ldc2l 11, cr10, [pc, #448] @ 2433ac0 @ │ │ - ldc2l 13, cr2, [pc, #532] @ 2433b18 │ │ + ldc2l 11, cr10, [pc, #628] @ 2433b74 @ │ │ + ldc2l 13, cr2, [pc, #712] @ 2433bcc │ │ mvnseq r9, r4, lsl #9 │ │ @ instruction: 0x019d7ef0 │ │ - ldc2l 12, cr8, [lr, #840] @ 0x348 │ │ + ldc2l 12, cr8, [lr, #1020] @ 0x3fc │ │ ldr r0, [pc, #4060] @ 24348f0 │ │ add r0, pc, r0 │ │ str r0, [fp, #-56] @ 0xffffffc8 │ │ sub r0, fp, #68 @ 0x44 │ │ bl 270ea00 │ │ cmp r0, #0 │ │ str r0, [r5] │ │ @@ -1289673,30 +1289673,30 @@ │ │ bl 270d9e0 │ │ ldr r0, [pc, #3912] @ 2434910 │ │ ldr r0, [pc, r0] │ │ cmp r0, #0 │ │ bgt 2433480 │ │ b 2433a2c │ │ @ instruction: 0x019d7db4 │ │ - ldc2l 10, cr10, [pc, #736] @ 2433cc0 @ │ │ + ldc2l 10, cr10, [pc, #916] @ 2433d74 @ │ │ ldr r1, [pc, #4092] @ 24349e0 │ │ mov r0, r6 │ │ mov r2, #2 │ │ mov r3, #1 │ │ add r1, pc, r1 │ │ b 2433870 │ │ - ldc2l 12, cr2, [pc, #820] @ 2433d30 │ │ + ldc2l 12, cr2, [pc, #1000] @ 2433de4 │ │ mvnseq r9, ip, asr #7 │ │ orrseq r7, sp, r8, lsr lr │ │ @ instruction: 0x019d7dd8 │ │ orrseq r7, sp, ip, asr #27 │ │ orrseq r7, sp, r0, ror #27 │ │ orrseq r7, sp, r4, lsl #26 │ │ andeq r2, r4, #60, 22 @ 0xf000 │ │ - ldc2l 12, cr2, [pc, #116] @ 2433a90 │ │ + ldc2l 12, cr2, [pc, #296] @ 2433b44 │ │ @ instruction: 0x019d7c94 │ │ orrseq r7, sp, r8, lsl sp │ │ orrseq r7, sp, r0, lsl sp │ │ orrseq r7, sp, r8, asr #24 │ │ ldc2l 4, cr0, [lr, #456] @ 0x1c8 │ │ ldr r0, [pc, #4016] @ 24349e4 │ │ mov r1, #10 │ │ @@ -1289789,16 +1289789,16 @@ │ │ ldr r0, [pc, #3932] @ 2434af0 │ │ add r0, pc, r0 │ │ b 2433bc4 │ │ @ instruction: 0x019d7bf0 │ │ ldr r0, [pc, #3920] @ 2434af4 │ │ add r0, pc, r0 │ │ b 2433bb8 │ │ - stc2l 5, cr0, [r0, #68]! @ 0x44 │ │ - ldc2l 10, cr8, [lr, #584] @ 0x248 @ │ │ + stc2l 5, cr0, [r0, #248]! @ 0xf8 │ │ + ldc2l 10, cr8, [lr, #764] @ 0x2fc @ │ │ ldr r0, [pc, #3904] @ 2434af8 │ │ add r0, pc, r0 │ │ mov r1, #0 │ │ ldr r2, [fp, #28] │ │ str r1, [r2] │ │ mov r1, #6 │ │ bl 270ceb0 │ │ @@ -1289926,23 +1289926,23 @@ │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #3840] @ 2434cc0 │ │ ldr r2, [fp, #24] │ │ ldr r0, [pc, r0] │ │ b 2433d80 │ │ stc2l 12, cr9, [r1, #592]! @ 0x250 │ │ - ldc2l 8, cr2, [pc, #868] @ 2434138 │ │ + ldc2l 9, cr2, [pc, #12] @ 2433de0 @ │ │ movteq sp, #1996 @ 0x7cc │ │ orrseq r7, sp, r8, ror r9 │ │ @ instruction: 0x03244518 │ │ orrseq r7, sp, ip, ror #18 │ │ @ instruction: 0x019d79d0 │ │ orrseq r7, sp, r0, lsr r9 │ │ - ldc2l 4, cr14, [pc, #724] @ 24340c4 │ │ - ldc2l 8, cr2, [pc, #244] @ 2433ee8 │ │ + ldc2l 4, cr14, [pc, #904] @ 2434178 │ │ + vcadd.f32 q9, , q13, #270 │ │ ldr r0, [pc, #3788] @ 2434cc4 │ │ add r0, pc, r0 │ │ mov r6, r0 │ │ bl 270e0c0 │ │ ldr r1, [pc, #3776] @ 2434cc8 │ │ add r1, pc, r1 │ │ str r0, [r1] │ │ @@ -1290049,16 +1290049,16 @@ │ │ str r0, [r5] │ │ ble 2434774 │ │ ldr r0, [pc, #4072] @ 2434f94 │ │ add r0, pc, r0 │ │ b 2433bc4 │ │ orrseq r7, sp, r4, ror #16 │ │ orrseq r7, sp, r4, asr #15 │ │ - ldc2l 3, cr14, [pc, #292] @ 24340e4 │ │ - ldc2l 6, cr2, [pc, #836] @ 2434308 │ │ + ldc2l 3, cr14, [pc, #472] @ 2434198 │ │ + ldc2l 6, cr2, [pc, #1016] @ 24343bc │ │ ldr r0, [pc, #4048] @ 2434f98 │ │ mov r1, #214 @ 0xd6 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ mov r0, r4 │ │ mov r1, r5 │ │ bl 270df20 │ │ @@ -1290080,15 +1290080,15 @@ │ │ mov r1, #0 │ │ ldr r0, [pc, #3972] @ 2434fa8 │ │ add r0, pc, r0 │ │ str r1, [r2] │ │ b 2433bbc │ │ stc2l 1, cr8, [r0, #172]! @ 0xac │ │ stc2l 9, cr1, [r1, #114]! @ 0x72 @ │ │ - ldc2l 6, cr4, [pc, #672] @ 24342dc │ │ + ldc2l 6, cr4, [pc, #852] @ 2434390 │ │ ldr r0, [pc, #3948] @ 2434fac │ │ mov r1, #0 │ │ ldr r2, [pc, #3944] @ 2434fb0 │ │ add r0, pc, r0 │ │ ldr r2, [pc, r2] │ │ cmp r2, #0 │ │ movwgt r1, #1 │ │ @@ -1290109,15 +1290109,15 @@ │ │ bl 270da60 │ │ ldr r0, [pc, #4040] @ 2435060 │ │ mov r1, #10 │ │ add r0, pc, r0 │ │ b 2431844 │ │ stc2l 15, cr8, [r0, #544]! @ 0x220 │ │ orrseq r7, sp, r8, lsl #15 │ │ - ldc2l 3, cr10, [pc, #912] @ 2434440 │ │ + ldc2l 4, cr10, [pc, #68] @ 24340f4 │ │ ldr r0, [pc, #4016] @ 2435064 │ │ mov r1, #214 @ 0xd6 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ mov r0, r4 │ │ mov r1, r5 │ │ bl 270df20 │ │ @@ -1290177,15 +1290177,15 @@ │ │ beq 24348b8 │ │ mov r0, #80 @ 0x50 │ │ str r0, [r6] │ │ ldr r0, [pc, #4076] @ 243519c │ │ add r0, pc, r0 │ │ b 2433bc4 │ │ stc2l 3, cr11, [r1, #756]! @ 0x2f4 │ │ - ldc2l 4, cr2, [pc, #932] @ 2434564 │ │ + ldc2l 5, cr2, [pc, #88] @ 2434218 │ │ orrseq r7, sp, r0, lsr #11 │ │ ldr r1, [pc, #4056] @ 24351a0 │ │ ldr r5, [fp, #20] │ │ ldr r1, [pc, r1] │ │ add r0, r1, r0 │ │ ldr r1, [pc, #4044] @ 24351a4 │ │ add r1, pc, r1 │ │ @@ -1290194,15 +1290194,15 @@ │ │ ldr r9, [pc, #4036] @ 24351ac │ │ add r8, pc, r8 │ │ add r9, pc, r9 │ │ b 243446c │ │ @ instruction: 0x01fbf59c │ │ orrseq r7, sp, r8, lsr r6 │ │ vcmla.f16 , q8, q6, #270 │ │ - ldc2l 4, cr2, [pc, #596] @ 2434458 │ │ + ldc2l 4, cr2, [pc, #776] @ 243450c │ │ ldr r1, [pc, #4008] @ 24351b0 │ │ ldr r7, [fp, #80] @ 0x50 │ │ ldr r1, [pc, r1] │ │ add r0, r1, r0 │ │ ldr r1, [pc, #3996] @ 24351b4 │ │ ldr r5, [fp, #-72] @ 0xffffffb8 │ │ add r1, pc, r1 │ │ @@ -1290219,16 +1290219,16 @@ │ │ ldrdeq r4, [pc, #40] @ 2434274 │ │ ldr r5, [fp, #20] │ │ ldr r2, [fp, #24] │ │ b 243446c │ │ ldr r2, [fp, #48] @ 0x30 │ │ b 2434594 │ │ @ instruction: 0x019d75d4 │ │ - ldc2l 2, cr10, [pc, #160] @ 2434308 │ │ - ldc2l 4, cr2, [pc, #244] @ 2434360 │ │ + ldc2l 2, cr10, [pc, #340] @ 24343bc │ │ + ldc2l 4, cr2, [pc, #424] @ 2434414 │ │ mvnseq r8, r0, asr #22 │ │ orrseq r7, sp, ip, lsr #11 │ │ ldr r0, [pc, #4064] @ 2435258 │ │ mov r1, #214 @ 0xd6 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ mov r0, r4 │ │ @@ -1290244,16 +1290244,16 @@ │ │ mov r1, #10 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #4008] @ 2435264 │ │ add r0, pc, r0 │ │ b 2433bc4 │ │ @ instruction: 0x019d7594 │ │ - ldc2l 13, cr15, [pc, #772] @ 24345d0 │ │ - ldc2l 3, cr2, [pc, #756] @ 24345c4 │ │ + ldc2l 13, cr15, [pc, #952] @ 2434684 │ │ + ldc2l 3, cr2, [pc, #936] @ 2434678 │ │ orrseq r7, sp, r0, ror r4 │ │ andeq r2, r4, #192, 4 │ │ ldr r9, [pc, #3980] @ 2435268 │ │ rsb r1, r2, #0 │ │ ldr r8, [pc, #3976] @ 243526c │ │ mov r0, #0 │ │ add r9, pc, r9 │ │ @@ -1290311,16 +1290311,16 @@ │ │ mov r0, r4 │ │ mov r2, #1 │ │ add r1, pc, r1 │ │ bl 270db00 │ │ ldr r0, [pc, #4060] @ 24353a8 │ │ add r0, pc, r0 │ │ b 242e684 │ │ - ldc2l 12, cr15, [pc, #972] @ 24347a4 │ │ - ldc2l 2, cr2, [pc, #900] @ 2434760 │ │ + ldc2l 13, cr15, [pc, #128] @ 2434458 │ │ + ldc2l 3, cr2, [pc, #56] @ 2434414 │ │ @ instruction: 0x019d7394 │ │ andeq r4, r2, #244, 24 @ 0xf400 │ │ movteq r6, #10232 @ 0x27f8 │ │ ldr r4, [fp, #-72] @ 0xffffffb8 │ │ cmp r1, #0 │ │ beq 2434c54 │ │ ldr r0, [pc, #4020] @ 24353ac │ │ @@ -1290340,20 +1290340,20 @@ │ │ movteq r6, #10200 @ 0x27d8 │ │ stc2l 6, cr9, [r1, #132]! @ 0x84 │ │ orrseq r7, sp, r8, asr #7 │ │ @ instruction: 0x019d73b8 │ │ movteq sp, #264 @ 0x108 │ │ orrseq r7, sp, r0, ror #7 │ │ ldc2l 11, cr15, [sp, #136] @ 0x88 @ │ │ - ldc2l 2, cr2, [pc, #84] @ 24344a0 │ │ + ldc2l 2, cr2, [pc, #264] @ 2434554 │ │ orrseq r7, sp, ip, ror #6 │ │ eorseq pc, r4, #72, 10 @ 0x12000000 │ │ movteq sp, #208 @ 0xd0 │ │ - ldc2l 11, cr15, [pc, #756] @ 2434750 @ │ │ - ldc2l 1, cr2, [pc, #740] @ 2434744 │ │ + ldc2l 11, cr15, [pc, #936] @ 2434804 @ │ │ + ldc2l 1, cr2, [pc, #920] @ 24347f8 │ │ andeq r2, r4, #196 @ 0xc4 │ │ ldr r0, [pc, #4092] @ 2435464 │ │ ldr r5, [fp, #20] │ │ ldr r0, [pc, r0] │ │ ldr r6, [r5] │ │ ldr r1, [pc, #4080] @ 2435468 │ │ cmp r0, r6 │ │ @@ -1290397,15 +1290397,15 @@ │ │ mov r0, r4 │ │ mov r2, #1 │ │ add r1, pc, r1 │ │ bl 270db00 │ │ ldr r0, [pc, #3952] @ 2435494 │ │ add r0, pc, r0 │ │ b 242e850 │ │ - ldc2l 0, cr14, [lr, #664] @ 0x298 │ │ + ldc2l 0, cr14, [lr, #844] @ 0x34c │ │ cmp r1, #0 │ │ beq 243501c │ │ ldr r0, [pc, #3932] @ 2435498 │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ movw r0, #26002 @ 0x6592 │ │ cmp r1, r0 │ │ @@ -1290415,16 +1290415,16 @@ │ │ add r2, pc, r2 │ │ add r3, pc, r3 │ │ ldr r0, [r3, r1, lsl #2] │ │ str r0, [r2] │ │ b 2434a7c │ │ orrseq r7, sp, r0, lsr #5 │ │ orrseq r7, sp, r4, lsr #5 │ │ - ldc2l 0, cr8, [lr, #700] @ 0x2bc │ │ - ldc2l 1, cr2, [pc, #100] @ 24345e0 │ │ + ldc2l 0, cr8, [lr, #880] @ 0x370 │ │ + ldc2l 1, cr2, [pc, #280] @ 2434694 │ │ orrseq r7, sp, r4, asr #4 │ │ orrseq r7, sp, ip, lsr r2 │ │ orrseq r7, sp, r0, lsl r2 │ │ orrseq r7, sp, r0, lsl #4 │ │ orrseq r7, sp, r4, lsl #4 │ │ ldr r0, [pc, #3856] @ 24354a4 │ │ ldr r0, [pc, r0] │ │ @@ -1290472,16 +1290472,16 @@ │ │ mov r0, r4 │ │ mov r2, #1 │ │ add r1, pc, r1 │ │ bl 270db00 │ │ ldr r0, [pc, #3988] @ 24355e4 │ │ add r0, pc, r0 │ │ b 243006c │ │ - ldc2l 15, cr7, [lr, #892] @ 0x37c │ │ - ldc2l 0, cr2, [pc, #292] @ 2434784 │ │ + ldc2l 0, cr8, [lr, #48] @ 0x30 │ │ + ldc2l 0, cr2, [pc, #472] @ 2434838 │ │ orrseq r7, sp, r4, lsr #3 │ │ orrseq r7, sp, r8, lsl #3 │ │ orrseq r7, sp, ip, ror r1 │ │ cmp r1, #0 │ │ beq 2435430 │ │ ldr r0, [pc, #3952] @ 24355e8 │ │ ldr r0, [pc, r0] │ │ @@ -1290493,22 +1290493,22 @@ │ │ ldr r0, [sl, r1, lsl #2] │ │ add r2, pc, r2 │ │ ldr r4, [fp, #20] │ │ str r0, [r2] │ │ ldr r5, [pc, #4060] @ 2435680 │ │ add r5, pc, r5 │ │ b 2434b6c │ │ - ldc2l 15, cr7, [lr, #540] @ 0x21c │ │ - ldc2l 15, cr1, [pc, #964] @ 2434a78 │ │ + ldc2l 15, cr7, [lr, #720] @ 0x2d0 │ │ + ldc2l 0, cr2, [pc, #120] @ 243472c │ │ orrseq r7, sp, r4, lsr r1 │ │ orrseq r7, sp, ip, lsr #2 │ │ orrseq r7, sp, ip, lsl #2 │ │ orrseq r7, sp, r0, lsl r1 │ │ - ldc2l 15, cr7, [lr, #76] @ 0x4c │ │ - ldc2l 15, cr1, [pc, #500] @ 24348c0 │ │ + ldc2l 15, cr7, [lr, #256] @ 0x100 │ │ + ldc2l 15, cr1, [pc, #680] @ 2434974 │ │ orrseq r7, sp, r0, asr #1 │ │ ldrheq r7, [sp, r8] │ │ ldr r0, [pc, #4012] @ 2435684 │ │ mov r1, #118 @ 0x76 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r5, [pc, #4000] @ 2435688 │ │ @@ -1290555,25 +1290555,25 @@ │ │ ldr r9, [pc, #4032] @ 243574c │ │ add r8, pc, r8 │ │ add sl, pc, sl │ │ add r9, pc, r9 │ │ b 24347e4 │ │ orrseq r7, sp, r0, ror r0 │ │ orrseq r7, sp, r0, ror r0 │ │ - ldc2l 8, cr15, [pc, #972] @ 2434b74 │ │ - ldc2l 14, cr1, [pc, #900] @ 2434b30 │ │ + ldc2l 9, cr15, [pc, #64] @ 24347e8 @ │ │ + ldc2l 15, cr1, [pc, #56] @ 24347e4 │ │ movteq ip, #3508 @ 0xdb4 │ │ andeq r4, r2, #236, 16 @ 0xec0000 │ │ orrseq r7, sp, r0, lsr #32 │ │ movteq ip, #3440 @ 0xd70 │ │ - ldc2l 5, cr9, [lr, #244] @ 0xf4 │ │ + ldc2l 5, cr9, [lr, #424] @ 0x1a8 │ │ movteq r6, #9156 @ 0x23c4 │ │ stc2l 8, cr11, [r0, #840]! @ 0x348 │ │ @ instruction: 0x019d6fdc │ │ - stc2l 5, cr1, [r0, #272]! @ 0x110 │ │ + stc2l 5, cr1, [r0, #452]! @ 0x1c4 │ │ ldr r0, [r8, r1, lsl #2] │ │ ldr r1, [pc, #4076] @ 24357c4 │ │ add r1, pc, r1 │ │ cmp r0, #0 │ │ str r0, [r1] │ │ ble 2433fa4 │ │ ldr r1, [pc, #4060] @ 24357c8 │ │ @@ -1290702,15 +1290702,15 @@ │ │ bl 270da30 │ │ mov r1, r0 │ │ add r0, sl, r1, lsl #2 │ │ b 2434c2c │ │ ldc2l 4, cr3, [lr, #380] @ 0x17c │ │ orrseq r6, sp, r4, lsl #28 │ │ stc2l 11, cr10, [r1, #272]! @ 0x110 @ │ │ - ldc2l 12, cr1, [pc, #420] @ 2434b98 │ │ + ldc2l 12, cr1, [pc, #600] @ 2434c4c │ │ orrseq r6, sp, ip, lsl sp │ │ ldrheq r1, [pc, #148] @ 2434a90 │ │ @ instruction: 0x019d6db8 │ │ orrseq r6, sp, ip, lsl #27 │ │ orrseq r6, sp, r0, lsl #27 │ │ stc2l 0, cr15, [r0, #204]! @ 0xcc │ │ ldr r0, [pc, #4000] @ 24359b0 │ │ @@ -1290767,16 +1290767,16 @@ │ │ b 2434ff0 │ │ stc2l 15, cr14, [r0, #1020]! @ 0x3fc │ │ ldrsbteq r3, [r2], -r4 │ │ mvnseq lr, ip, asr ip │ │ movteq ip, #2680 @ 0xa78 │ │ movteq ip, #2656 @ 0xa60 │ │ stc2l 5, cr7, [r0, #984]! @ 0x3d8 │ │ - ldc2l 5, cr15, [lr, #548] @ 0x224 │ │ - ldc2l 10, cr7, [lr, #760] @ 0x2f8 @ │ │ + ldc2l 5, cr15, [lr, #728] @ 0x2d8 │ │ + ldc2l 10, cr7, [lr, #940] @ 0x3ac @ │ │ stc2l 3, cr13, [r0, #16]! │ │ ldr r0, [pc, #3804] @ 24359e0 │ │ movw r3, #7389 @ 0x1cdd │ │ ldr r2, [pc, #3800] @ 24359e4 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1290825,16 +1290825,16 @@ │ │ add r0, r6, r1, lsl #2 │ │ mov r5, r6 │ │ b 24353fc │ │ andeq r4, r2, #248, 8 @ 0xf8000000 │ │ orrseq r6, sp, ip, lsr #24 │ │ orrseq r6, sp, r4, lsr ip │ │ orrseq r6, sp, r8, asr #24 │ │ - vcadd.f32 , , q10, #270 │ │ - ldc2l 10, cr1, [pc, #484] @ 2434dc8 @ │ │ + ldc2l 8, cr9, [pc, #580] @ 2434e24 │ │ + ldc2l 10, cr1, [pc, #664] @ 2434e7c @ │ │ mvnseq r8, r8, ror r1 │ │ orrseq r6, sp, ip, ror #23 │ │ @ instruction: 0x019d6bb4 │ │ rsb r2, r0, #0 │ │ str r2, [r1] │ │ mov r1, #11 │ │ sub r1, r1, r0, lsl #1 │ │ @@ -1290875,22 +1290875,22 @@ │ │ add r7, pc, r7 │ │ add r4, pc, r4 │ │ b 2434d1c │ │ andeq r1, r4, #48, 18 @ 0xc0000 │ │ orrseq r6, sp, r4, ror fp │ │ orrseq r6, sp, ip, ror fp │ │ @ instruction: 0x019d6b94 │ │ - ldc2l 7, cr9, [pc, #704] @ 2434f68 │ │ - ldc2l 9, cr1, [pc, #394] @ 2434e36 @ │ │ + ldc2l 7, cr9, [pc, #884] @ 243501c │ │ + ldc2l 9, cr1, [pc, #484] @ 2434e90 @ │ │ orrseq r6, sp, ip, lsr fp │ │ mvnseq r8, r0, asr #1 │ │ orrseq r6, sp, r8, asr #20 │ │ movteq ip, #2172 @ 0x87c │ │ - ldc2l 3, cr15, [pc, #388] @ 2434e44 │ │ - ldc2l 9, cr1, [pc, #178] @ 2434d76 @ │ │ + ldc2l 3, cr15, [pc, #568] @ 2434ef8 │ │ + ldc2l 9, cr1, [pc, #268] @ 2434dd0 @ │ │ movteq ip, #2048 @ 0x800 │ │ andeq r1, r4, #236, 14 @ 0x3b00000 │ │ orrseq r6, sp, r0, lsr sl │ │ ldr r0, [pc, #3544] @ 2435aac │ │ mov r3, r8 │ │ ldr r1, [fp, #44] @ 0x2c │ │ ldr r0, [pc, r0] │ │ @@ -1290969,21 +1290969,21 @@ │ │ add r0, pc, r0 │ │ str r1, [r0] │ │ mov r1, r7 │ │ bl 270e0f0 │ │ b 2434e7c │ │ orrseq r6, sp, r8, lsr sl │ │ orrseq r6, sp, r0, asr sl │ │ - ldc2l 6, cr9, [pc, #432] @ 2434fd0 │ │ - vcadd.f32 d17, d31, d1, #270 │ │ + ldc2l 6, cr9, [pc, #612] @ 2435084 │ │ + vcadd.f32 d17, d31, d30, #270 │ │ @ instruction: 0x019d69f8 │ │ orrseq r6, sp, ip, lsl #18 │ │ movteq ip, #1856 @ 0x740 │ │ - ldc2l 2, cr15, [pc, #148] @ 2434ec8 │ │ - ldc2l 8, cr1, [pc, #116] @ 2434eac │ │ + ldc2l 2, cr15, [pc, #328] @ 2434f7c │ │ + vcadd.f32 , , q5, #270 │ │ ldr r0, [pc, #3136] @ 2435a7c │ │ ldr r0, [pc, r0] │ │ ldr sl, [pc, #3132] @ 2435a80 │ │ sub r1, r0, #1 │ │ cmp r1, r5 │ │ ldr sl, [pc, sl] │ │ bcc 2434e70 │ │ @@ -1291064,21 +1291064,21 @@ │ │ ldr r0, [pc, #2792] @ 2435a68 │ │ mov r1, #21 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #2780] @ 2435a6c │ │ add r0, pc, r0 │ │ b 2433bc4 │ │ - ldc2l 6, cr7, [lr, #728] @ 0x2d8 │ │ - ldc2l 4, cr5, [pc, #1016] @ 2435398 │ │ - ldc2l 15, cr14, [lr, #84] @ 0x54 │ │ + ldc2l 6, cr7, [lr, #908] @ 0x38c │ │ + ldc2l 5, cr5, [pc, #172] @ 243504c │ │ + ldc2l 15, cr14, [lr, #264] @ 0x108 │ │ stc2l 0, cr11, [r0, #908]! @ 0x38c │ │ - ldc2l 4, cr9, [pc, #768] @ 24352ac │ │ + ldc2l 4, cr9, [pc, #948] @ 2435360 │ │ stc2l 14, cr12, [r0, #608]! @ 0x260 │ │ - ldc2l 0, cr15, [pc, #708] @ 2435278 │ │ + ldc2l 0, cr15, [pc, #888] @ 243532c │ │ orrseq r6, sp, ip, asr #15 │ │ rsb r2, r0, #0 │ │ str r2, [r1] │ │ mov r1, #11 │ │ sub r1, r1, r0, lsl #1 │ │ movw r0, #30012 @ 0x753c │ │ cmp r1, r0 │ │ @@ -1291113,24 +1291113,24 @@ │ │ ldr r4, [pc, #2740] @ 2435af8 │ │ movw sl, #26003 @ 0x6593 │ │ ldr r7, [pc, #2736] @ 2435afc │ │ add r5, pc, r5 │ │ add r4, pc, r4 │ │ add r7, pc, r7 │ │ b 24350a8 │ │ - ldc2l 4, cr5, [pc, #392] @ 24351e8 │ │ - ldc2l 14, cr14, [lr, #484] @ 0x1e4 │ │ + ldc2l 4, cr5, [pc, #572] @ 243529c │ │ + ldc2l 14, cr14, [lr, #664] @ 0x298 │ │ stc2l 0, cr11, [r0, #284]! @ 0x11c │ │ - ldc2l 4, cr5, [pc, #72] @ 24350b4 │ │ - ldc2l 14, cr14, [lr, #164] @ 0xa4 │ │ + ldc2l 4, cr5, [pc, #252] @ 2435168 │ │ + ldc2l 14, cr14, [lr, #344] @ 0x158 │ │ stc2l 15, cr10, [r0, #988]! @ 0x3dc │ │ stc2l 13, cr12, [r0, #784]! @ 0x310 │ │ andeq r3, r2, #224, 30 @ 0x380 │ │ - ldc2l 15, cr14, [pc, #764] @ 243537c │ │ - ldc2l 5, cr1, [pc, #692] @ 2435338 │ │ + ldc2l 15, cr14, [pc, #944] @ 2435430 │ │ + ldc2l 5, cr1, [pc, #872] @ 24353ec │ │ orrseq r6, sp, r4, asr #12 │ │ stc2l 8, cr8, [r1, #1000]! @ 0x3e8 │ │ ldr r3, [pc, #2780] @ 2435b6c │ │ add r1, r8, r1, lsl #3 │ │ cmp r0, r6 │ │ add r2, r0, #1 │ │ add r3, pc, r3 │ │ @@ -1291194,15 +1291194,15 @@ │ │ rsb r1, r0, #0 │ │ ldr r0, [pc, #2508] @ 2435b58 │ │ add r0, pc, r0 │ │ str r1, [r0] │ │ mov r1, r4 │ │ bl 270e0f0 │ │ b 2435208 │ │ - ldc2l 15, cr14, [lr, #436] @ 0x1b4 │ │ + ldc2l 15, cr14, [lr, #616] @ 0x268 │ │ orrseq r6, sp, ip, ror #12 │ │ orrseq r6, sp, r0, ror #12 │ │ eorseq lr, r4, #44, 16 @ 0x2c0000 │ │ andeq r3, r2, #8, 30 │ │ orrseq r6, sp, ip, lsr #12 │ │ orrseq r6, sp, ip, lsl r6 │ │ eorseq lr, r4, #232, 14 @ 0x3a00000 │ │ @@ -1291241,18 +1291241,18 @@ │ │ movw r3, #6933 @ 0x1b15 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #2324] @ 2435b68 │ │ ldr r0, [pc, r0] │ │ b 2435088 │ │ - ldc2l 2, cr5, [pc, #312] @ 2435398 │ │ - ldc2l 12, cr14, [lr, #404] @ 0x194 │ │ + ldc2l 2, cr5, [pc, #492] @ 243544c │ │ + ldc2l 12, cr14, [lr, #584] @ 0x248 │ │ stc2l 14, cr10, [r0, #204]! @ 0xcc │ │ - ldc2l 3, cr7, [lr, #664] @ 0x298 │ │ + ldc2l 3, cr7, [lr, #844] @ 0x34c │ │ orrseq r6, sp, r4, lsr #9 │ │ movteq ip, #724 @ 0x2d4 │ │ orrseq r6, sp, ip, lsr #10 │ │ ldr r1, [pc, #2292] @ 2435b70 │ │ mov r3, #32 │ │ ldr r7, [fp, #-72] @ 0xffffffb8 │ │ mov r4, #32 │ │ @@ -1291297,15 +1291297,15 @@ │ │ movteq ip, #628 @ 0x274 │ │ orrseq r6, sp, r4, lsr #10 │ │ mvnseq lr, ip, lsr r4 │ │ mvnseq r7, r0, lsl #21 │ │ andeq r3, r2, #144, 26 @ 0x2400 │ │ andeq r1, r4, #120, 4 @ 0x80000007 │ │ stc2l 4, cr2, [r1, #336]! @ 0x150 │ │ - ldc2l 11, cr14, [lr, #452] @ 0x1c4 @ │ │ + ldc2l 11, cr14, [lr, #632] @ 0x278 @ │ │ ldr r0, [pc, #1980] @ 2435b00 │ │ ldr r1, [pc, #1980] @ 2435b04 │ │ ldr r2, [pc, #1980] @ 2435b08 │ │ add r0, pc, r0 │ │ ldr r3, [pc, #1976] @ 2435b0c │ │ add r1, pc, r1 │ │ ldr r7, [pc, #1972] @ 2435b10 │ │ @@ -1291325,15 +1291325,15 @@ │ │ mov r1, #21 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #1920] @ 2435b20 │ │ add r0, pc, r0 │ │ b 2433bc4 │ │ orrseq r6, sp, r8, ror r4 │ │ - ldc2l 15, cr6, [pc, #24] @ 24353c8 │ │ + ldc2l 15, cr6, [pc, #204] @ 243547c │ │ orrseq r6, sp, ip, ror r4 │ │ orrseq r6, sp, r4, asr #8 │ │ mvnseq r7, r8, asr #19 │ │ ldr r2, [pc, #2004] @ 2435b94 │ │ rsb r1, r0, #0 │ │ add r2, pc, r2 │ │ str r1, [r2] │ │ @@ -1291382,17 +1291382,17 @@ │ │ @ instruction: 0x019d63d4 │ │ mvnseq lr, ip, ror #5 │ │ mvnseq r7, r0, lsr r9 │ │ andeq r3, r2, #60, 24 @ 0x3c00 │ │ andeq r1, r4, #40, 2 │ │ mvnseq r0, r8, ror #30 │ │ stc2l 2, cr2, [r1, #1008]! @ 0x3f0 │ │ - ldc2l 10, cr14, [lr, #100] @ 0x64 @ │ │ + ldc2l 10, cr14, [lr, #280] @ 0x118 @ │ │ orrseq r6, sp, r0, lsr #6 │ │ - ldc2l 13, cr6, [pc, #696] @ 2435754 │ │ + ldc2l 13, cr6, [pc, #876] @ 2435808 │ │ orrseq r6, sp, r8, lsr r3 │ │ orrseq r6, sp, r0, lsl #6 │ │ mvnseq r7, r4, lsl #17 │ │ orrseq r6, sp, r4, lsr #5 │ │ orrseq r6, sp, r4, lsr #5 │ │ movteq fp, #4088 @ 0xff8 │ │ orrseq r6, sp, r8, lsr #5 │ │ @@ -1291466,17 +1291466,17 @@ │ │ bl 270e0f0 │ │ b 243562c │ │ mvnseq r7, r4, lsl #16 │ │ andeq r3, r2, #16, 22 @ 0x4000 │ │ andeq r0, r4, #252, 30 @ 0x3f0 │ │ mvnseq r0, ip, lsr lr │ │ stc2l 1, cr2, [r1, #832]! @ 0x340 │ │ - vcadd.f32 q15, q15, , #270 │ │ + ldc2l 9, cr14, [lr, #52] @ 0x34 @ │ │ @ instruction: 0x019d61f4 │ │ - ldc2l 12, cr6, [pc, #520] @ 24357f4 │ │ + ldc2l 12, cr6, [pc, #700] @ 24358a8 │ │ @ instruction: 0x019d61fc │ │ ldr r0, [pc, #1532] @ 2435bf0 │ │ ldr r0, [pc, r0] │ │ ldr r4, [pc, #1528] @ 2435bf4 │ │ sub r1, r0, #1 │ │ cmp r1, r8 │ │ ldr r4, [pc, r4] │ │ @@ -1291508,16 +1291508,16 @@ │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #1452] @ 2435c24 │ │ ldr r0, [pc, r0] │ │ b 24354b8 │ │ orrseq r6, sp, r4, asr #3 │ │ andeq r3, r2, #80, 20 @ 0x50000 │ │ - ldc2l 15, cr10, [lr, #332] @ 0x14c │ │ - ldc2l 8, cr14, [lr, #84] @ 0x54 │ │ + ldc2l 15, cr10, [lr, #512] @ 0x200 │ │ + vcadd.f32 q15, q7, q1, #270 │ │ orrseq r6, sp, r0, lsr r1 │ │ orrseq r6, sp, r4, rrx │ │ ldr r1, [pc, #1424] @ 2435c2c │ │ mov r3, #32 │ │ ldr r7, [fp, #-72] @ 0xffffffb8 │ │ mov r4, #32 │ │ ldr r5, [fp, #80] @ 0x50 │ │ @@ -1291553,19 +1291553,19 @@ │ │ str r4, [sp, #24] │ │ str r4, [sp, #28] │ │ bl 270ea70 │ │ ldr r0, [pc, #1308] @ 2435c4c │ │ add r0, pc, r0 │ │ b 2433bc4 │ │ vcadd.f32 d30, d29, d14, #270 │ │ - ldc2l 15, cr0, [pc, #516] @ 2435944 │ │ - ldc2l 7, cr14, [lr, #660] @ 0x294 │ │ - ldc2l 13, cr8, [pc, #284] @ 2435864 │ │ + ldc2l 15, cr0, [pc, #696] @ 24359f8 │ │ + ldc2l 7, cr14, [lr, #840] @ 0x348 │ │ + ldc2l 13, cr8, [pc, #464] @ 2435918 │ │ andeq r3, r2, #104, 18 @ 0x1a0000 │ │ - ldc2l 15, cr0, [pc, #228] @ 2435834 │ │ + ldc2l 15, cr0, [pc, #408] @ 24358e8 │ │ bicseq sp, ip, r4, lsl lr │ │ ldr r0, [pc, #1128] @ 2435bc0 │ │ ldr r1, [pc, #1128] @ 2435bc4 │ │ ldr r2, [pc, #1128] @ 2435bc8 │ │ add r0, pc, r0 │ │ ldr r3, [pc, #1124] @ 2435bcc │ │ add r1, pc, r1 │ │ @@ -1291611,34 +1291611,34 @@ │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #548] @ 2435a40 │ │ ldr r0, [pc, r0] │ │ b 24357d4 │ │ - ldc2l 14, cr6, [lr, #124] @ 0x7c │ │ + ldc2l 14, cr6, [lr, #304] @ 0x130 │ │ ldr r1, [pc, #1060] @ 2435c50 │ │ mov r0, r4 │ │ mov r2, r5 │ │ mov r3, #6 │ │ add r1, pc, r1 │ │ bl 270d900 │ │ cmp r0, #0 │ │ beq 2435958 │ │ mov r0, #32 │ │ str r0, [r6] │ │ ldr r0, [pc, #1024] @ 2435c54 │ │ add r0, pc, r0 │ │ b 2433bc4 │ │ orrseq r5, sp, ip, lsl #30 │ │ - ldc2l 8, cr14, [pc, #236] @ 2435950 │ │ + vcadd.f32 q15, , q12, #270 │ │ stc2l 1, cr8, [r1, #804]! @ 0x324 │ │ - ldc2l 8, cr14, [lr, #196] @ 0xc4 │ │ - ldc2l 11, cr8, [pc, #560] @ 2435aa0 @ │ │ - ldc2l 13, cr0, [pc, #644] @ 2435af8 │ │ + ldc2l 8, cr14, [lr, #376] @ 0x178 │ │ + ldc2l 11, cr8, [pc, #740] @ 2435b54 @ │ │ + ldc2l 13, cr0, [pc, #824] @ 2435bac │ │ orrseq r5, sp, r0, lsr #30 │ │ mvnseq r7, r4, lsr #9 │ │ ldr r0, [pc, #388] @ 2435a04 │ │ mov r1, #83 @ 0x53 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #376] @ 2435a08 │ │ @@ -1291685,16 +1291685,16 @@ │ │ mov r2, #1 │ │ bl 270da60 │ │ ldr r0, [pc, #248] @ 2435a34 │ │ mov r1, #10 │ │ add r0, pc, r0 │ │ b 242e784 │ │ orrseq r5, sp, r4, lsr #30 │ │ - ldc2l 11, cr8, [pc, #272] @ 2435a60 @ │ │ - ldc2l 13, cr0, [pc, #356] @ 2435ab8 │ │ + ldc2l 11, cr8, [pc, #452] @ 2435b14 @ │ │ + ldc2l 13, cr0, [pc, #536] @ 2435b6c │ │ @ instruction: 0x019d5ed8 │ │ mvnseq r7, r8, asr r4 │ │ ldr r1, [pc, #760] @ 2435c58 │ │ mov r0, r4 │ │ mov r2, r5 │ │ mov r3, #6 │ │ add r1, pc, r1 │ │ @@ -1291709,122 +1291709,122 @@ │ │ orrseq r5, sp, r8, ror #27 │ │ mov r0, #0 │ │ str r0, [r6] │ │ str r0, [r7] │ │ ldr r0, [pc, #700] @ 2435c60 │ │ add r0, pc, r0 │ │ b 2433bc4 │ │ - ldc2l 6, cr14, [pc, #1012] @ 2435da4 │ │ - ldc2l 12, cr0, [pc, #996] @ 2435d98 │ │ - ldc2l 10, cr8, [pc, #608] @ 2435c18 @ │ │ - ldc2l 12, cr0, [pc, #692] @ 2435c70 │ │ + ldc2l 7, cr14, [pc, #168] @ 2435a58 │ │ + ldc2l 13, cr0, [pc, #152] @ 2435a4c │ │ + ldc2l 10, cr8, [pc, #788] @ 2435ccc @ │ │ + ldc2l 12, cr0, [pc, #872] @ 2435d24 │ │ orrseq r5, sp, ip, lsr #28 │ │ ldrheq r7, [sp, #48]! @ 0x30 │ │ orrseq r5, sp, r0, lsr lr │ │ - ldc2l 10, cr8, [pc, #320] @ 2435b0c @ │ │ - ldc2l 12, cr0, [pc, #404] @ 2435b64 │ │ + ldc2l 10, cr8, [pc, #500] @ 2435bc0 @ │ │ + ldc2l 12, cr0, [pc, #584] @ 2435c18 │ │ orrseq r5, sp, r4, ror #27 │ │ mvnseq r7, r4, ror #6 │ │ @ instruction: 0x019d5cf4 │ │ - ldc2l 6, cr14, [pc, #36] @ 2435a04 │ │ - ldc2l 12, cr0, [pc, #20] @ 24359f8 │ │ - ldc2l 9, cr8, [pc, #328] @ 2435b30 @ │ │ - ldc2l 11, cr0, [pc, #740] @ 2435cd0 @ │ │ + ldc2l 6, cr14, [pc, #216] @ 2435ab8 │ │ + ldc2l 12, cr0, [pc, #200] @ 2435aac │ │ + ldc2l 9, cr8, [pc, #418] @ 2435b8a @ │ │ + ldc2l 11, cr0, [pc, #920] @ 2435d84 @ │ │ orrseq r5, sp, r4, lsr sp │ │ orrseq r5, sp, r0, asr #26 │ │ andeq r3, r2, #180, 10 @ 0x2d000000 │ │ - ldc2l 9, cr8, [pc, #176] @ 2435aac @ │ │ - ldc2l 11, cr0, [pc, #436] @ 2435bb4 @ │ │ + ldc2l 9, cr8, [pc, #266] @ 2435b06 @ │ │ + ldc2l 11, cr0, [pc, #616] @ 2435c68 @ │ │ orrseq r5, sp, ip, ror #25 │ │ orrseq r5, sp, r0, lsl #24 │ │ stc2l 7, cr7, [r0, #600]! @ 0x258 │ │ orrseq r4, sp, r8, lsr #31 │ │ stc2l 2, cr13, [r0, #304]! @ 0x130 │ │ - ldc2l 14, cr15, [lr, #84] @ 0x54 │ │ + ldc2l 14, cr15, [lr, #264] @ 0x108 │ │ mvneq r1, r4, ror #24 │ │ orrseq r4, sp, ip, asr #30 │ │ orrseq r4, sp, r4, asr pc │ │ stc2l 1, cr13, [r0, #992]! @ 0x3e0 │ │ - ldc2l 13, cr15, [lr, #772] @ 0x304 │ │ + ldc2l 13, cr15, [lr, #952] @ 0x3b8 │ │ orrseq r4, sp, r0, lsl pc │ │ - ldc2l 5, cr13, [lr, #900] @ 0x384 │ │ + ldc2l 6, cr13, [lr, #56] @ 0x38 │ │ mvneq r1, r0, lsl #24 │ │ stc2l 7, cr9, [r0, #652]! @ 0x28c │ │ - vcadd.f32 , , , #270 │ │ - ldc2l 14, cr15, [lr, #756] @ 0x2f4 │ │ + ldc2l 8, cr13, [pc, #1008] @ 2435e30 │ │ + ldc2l 14, cr15, [lr, #936] @ 0x3a8 │ │ movteq sl, #3496 @ 0xda8 │ │ - ldc2l 4, cr14, [pc, #764] @ 2435d48 │ │ - ldc2l 10, cr0, [pc, #692] @ 2435d04 @ │ │ + ldc2l 4, cr14, [pc, #944] @ 2435dfc │ │ + ldc2l 10, cr0, [pc, #872] @ 2435db8 @ │ │ @ instruction: 0x019d5bd8 │ │ orrseq r5, sp, r0, asr #22 │ │ @ instruction: 0x019d5bb4 │ │ andeq r3, r2, #112, 8 @ 0x70000000 │ │ orrseq r5, sp, r8, ror #23 │ │ - ldc2l 10, cr0, [pc, #244] @ 2435b5c @ │ │ - ldc2l 4, cr10, [pc, #764] @ 2435d68 │ │ - ldc2l 5, cr10, [pc, #4] @ 2435a74 │ │ - ldc2l 1, cr14, [lr, #536] @ 0x218 │ │ + ldc2l 10, cr0, [pc, #424] @ 2435c10 @ │ │ + ldc2l 4, cr10, [pc, #944] @ 2435e1c │ │ + ldc2l 5, cr10, [pc, #184] @ 2435b28 │ │ + ldc2l 1, cr14, [lr, #716] @ 0x2cc │ │ orrseq r5, sp, r4, lsr fp │ │ - ldc2l 7, cr8, [pc, #336] @ 2435bcc │ │ + ldc2l 7, cr8, [pc, #516] @ 2435c80 │ │ mvnseq r7, r4, ror r0 │ │ orrseq r5, sp, r8, lsr sl │ │ orrseq r5, sp, r4, lsr #20 │ │ - ldc2l 6, cr8, [pc, #320] @ 2435bcc │ │ + ldc2l 6, cr8, [pc, #500] @ 2435c80 │ │ mvnseq r6, r0, ror pc │ │ @ instruction: 0x019d5af4 │ │ - ldc2l 7, cr8, [pc, #80] @ 2435ae8 │ │ + ldc2l 7, cr8, [pc, #260] @ 2435b9c │ │ mvnseq r7, r4, lsr r0 │ │ orrseq r5, sp, ip, asr #19 │ │ - ldc2l 2, cr14, [pc, #972] @ 2435e70 │ │ + ldc2l 3, cr14, [pc, #128] @ 2435b24 │ │ orrseq r5, sp, r4, lsl sl │ │ orrseq r5, sp, ip, ror #19 │ │ - ldc2l 7, cr6, [lr, #716] @ 0x2cc │ │ + ldc2l 7, cr6, [lr, #896] @ 0x380 │ │ orrseq r5, sp, r0, asr #22 │ │ ldrheq sp, [ip, #136] @ 0x88 │ │ orrseq r5, sp, r8, lsl fp │ │ orrseq r5, sp, r8, lsl #22 │ │ teqeq r4, #128, 6 │ │ orrseq r5, sp, r4, lsl #19 │ │ rsbeq sl, r5, #12, 30 @ 0x30 │ │ teqeq r4, #76, 6 @ 0x30000001 │ │ movteq fp, #1716 @ 0x6b4 │ │ rsceq sl, r4, #116, 14 @ 0x1d00000 │ │ adceq r2, r5, #204, 20 @ 0xcc000 │ │ @ instruction: 0x032423fc │ │ - ldc2l 1, cr14, [lr, #744] @ 0x2e8 │ │ - ldc2l 0, cr14, [pc, #988] @ 2435ec4 │ │ - ldc2l 6, cr0, [pc, #916] @ 2435e80 │ │ + ldc2l 1, cr14, [lr, #924] @ 0x39c │ │ + ldc2l 1, cr14, [pc, #144] @ 2435b78 │ │ + ldc2l 7, cr0, [pc, #72] @ 2435b34 │ │ orrseq r5, sp, r4, lsl r8 │ │ orrseq r5, sp, ip, ror r7 │ │ @ instruction: 0x019d57f0 │ │ andeq r0, r4, #152, 10 @ 0x26000000 │ │ orrseq r5, sp, r0, lsr r8 │ │ - ldc2l 6, cr0, [pc, #468] @ 2435cd8 │ │ + ldc2l 6, cr0, [pc, #648] @ 2435d8c │ │ movteq fp, #624 @ 0x270 │ │ orrseq r5, sp, r0, lsr #10 │ │ mvnseq sp, r8, lsr r4 │ │ mvnseq r6, ip, ror sl │ │ andeq r2, r2, #140, 26 @ 0x2300 │ │ ldrheq r0, [pc, #12] @ 2435b28 │ │ - vcmla.f16 , q8, , #270 │ │ - ldc2l 0, cr10, [pc, #964] @ 2435ee8 │ │ + stc2l 8, cr1, [r0, #960]! @ 0x3c0 │ │ + ldc2l 1, cr10, [pc, #120] @ 2435b9c │ │ stc2l 12, cr3, [r0, #632]! @ 0x278 │ │ orrseq r5, sp, r8, lsr #15 │ │ - ldc2l 3, cr8, [pc, #800] @ 2435e50 │ │ + ldc2l 3, cr8, [pc, #980] @ 2435f04 │ │ mvnseq r6, r8, ror #25 │ │ orrseq r5, sp, ip, lsr #13 │ │ orrseq r5, sp, r8, lsr #13 │ │ - ldc2l 2, cr8, [pc, #784] @ 2435e50 │ │ + ldc2l 2, cr8, [pc, #964] @ 2435f04 │ │ mvnseq r6, r4, ror #23 │ │ eorseq sp, r4, #12, 16 @ 0xc0000 │ │ orrseq r5, sp, r8, ror #14 │ │ - ldc2l 3, cr8, [pc, #544] @ 2435d70 │ │ + ldc2l 3, cr8, [pc, #724] @ 2435e24 │ │ mvnseq r6, r8, lsr #25 │ │ orrseq r5, sp, r0, asr #12 │ │ - ldc2l 15, cr13, [pc, #356] @ 2435cc0 │ │ + ldc2l 15, cr13, [pc, #536] @ 2435d74 │ │ orrseq r5, sp, r8, lsl #13 │ │ orrseq r5, sp, ip, lsl #12 │ │ orrseq r5, sp, r4, ror #12 │ │ ldc2l 13, cr13, [sp, #568] @ 0x238 │ │ orrseq r5, sp, r8, asr #11 │ │ orrseq r5, sp, r0, lsl #15 │ │ teqeq r3, #208, 30 @ 0x340 @ │ │ @@ -1291833,44 +1291833,44 @@ │ │ teqeq r3, #156, 30 @ 0x270 @ │ │ movteq fp, #772 @ 0x304 │ │ rsceq sl, r4, #196, 6 @ 0x10000003 │ │ adceq r2, r5, #28, 14 @ 0x700000 │ │ @ instruction: 0x0324204c │ │ stc2l 13, cr3, [r0, #184]! @ 0xb8 │ │ orrseq r5, sp, r0, asr #7 │ │ - ldc2l 12, cr13, [pc, #940] @ 2435f4c │ │ - ldc2l 2, cr0, [pc, #868] @ 2435f08 │ │ - ldc2l 5, cr14, [pc, #100] @ 2435c0c │ │ - ldc2l 11, cr0, [pc, #84] @ 2435c00 @ │ │ + ldc2l 13, cr13, [pc, #96] @ 2435c00 │ │ + ldc2l 3, cr0, [pc, #24] @ 2435bbc │ │ + ldc2l 5, cr14, [pc, #280] @ 2435cc0 │ │ + ldc2l 11, cr0, [pc, #264] @ 2435cb4 @ │ │ orrseq r5, sp, r4, ror r3 │ │ orrseq r5, sp, r0, lsl #8 │ │ eorseq sp, r4, #228, 10 @ 0x39000000 │ │ @ instruction: 0x019d53dc │ │ andeq r0, r4, #136, 2 @ 0x22 │ │ - ldc2l 2, cr0, [pc, #420] @ 2435d68 │ │ + ldc2l 2, cr0, [pc, #600] @ 2435e1c │ │ movteq sl, #3676 @ 0xe5c │ │ orrseq r5, sp, ip, lsl #2 │ │ mvnseq sp, r4, lsr #32 │ │ mvnseq r6, r8, ror #12 │ │ andeq r2, r2, #120, 18 @ 0x1e0000 │ │ mvnseq pc, r8, lsr #25 │ │ - stc2l 4, cr1, [r0, #700]! @ 0x2bc │ │ - ldc2l 12, cr9, [pc, #884] @ 2435f58 │ │ + stc2l 4, cr1, [r0, #880]! @ 0x370 │ │ + ldc2l 13, cr9, [pc, #40] @ 2435c0c │ │ stc2l 7, cr11, [r0, #60]! @ 0x3c │ │ orrseq r5, sp, r8, lsl #7 │ │ orrseq r5, sp, r0, ror r3 │ │ - ldc2l 15, cr7, [pc, #576] @ 2435e34 │ │ + ldc2l 15, cr7, [pc, #756] @ 2435ee8 │ │ orrseq r5, sp, r0, lsl #5 │ │ orrseq r5, sp, ip, ror r2 │ │ - ldc2l 14, cr7, [pc, #608] @ 2435e60 │ │ + ldc2l 14, cr7, [pc, #788] @ 2435f14 │ │ eorseq sp, r4, #232, 6 @ 0xa0000003 │ │ orrseq r5, sp, r8, lsr r3 │ │ - ldc2l 15, cr7, [pc, #352] @ 2435d6c │ │ + ldc2l 15, cr7, [pc, #532] @ 2435e20 │ │ orrseq r5, sp, r8, lsl r2 │ │ - ldc2l 11, cr13, [pc, #196] @ 2435cd8 @ │ │ + ldc2l 11, cr13, [pc, #376] @ 2435d8c @ │ │ orrseq r5, sp, r0, ror #4 │ │ orrseq r5, sp, r0, asr #5 │ │ orrseq r5, sp, r0, ror #3 │ │ orrseq r5, sp, r4, lsr r2 │ │ ldc2l 9, cr13, [sp, #212] @ 0xd4 @ │ │ orrseq r5, sp, r4, lsr #3 │ │ orrseq r5, sp, r0, asr r3 │ │ @@ -1291880,18 +1291880,18 @@ │ │ teqeq r3, #124, 22 @ 0x1f000 @ │ │ movteq sl, #3812 @ 0xee4 │ │ rsceq r9, r4, #164, 30 @ 0x290 │ │ adceq r2, r5, #252, 4 @ 0xc000000f │ │ @ instruction: 0x03241c2c │ │ stc2l 7, cr11, [r0, #588]! @ 0x24c │ │ stc2l 3, cr13, [r0, #296]! @ 0x128 │ │ - vcadd.f32 , q15, , #270 │ │ + ldc2l 8, cr13, [lr, #984] @ 0x3d8 │ │ stc2l 5, cr11, [r0, #376]! @ 0x178 │ │ - ldc2l 7, cr13, [lr, #596] @ 0x254 │ │ - ldc2l 7, cr13, [lr, #484] @ 0x1e4 │ │ + ldc2l 7, cr13, [lr, #776] @ 0x308 │ │ + ldc2l 7, cr13, [lr, #664] @ 0x298 │ │ │ │ 02435c64 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ beq 2435c80 │ │ @@ -1292733,15 +1292733,15 @@ │ │ bl 270e4b0 │ │ mov r0, r8 │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 12, cr8, [pc, #284] @ 2436a24 │ │ + ldc2l 12, cr8, [pc, #464] @ 2436ad8 │ │ teqeq r3, #236, 18 @ 0x3b0000 │ │ movteq r9, #3384 @ 0xd38 │ │ orrseq r3, sp, r8, ror #30 │ │ @ instruction: 0x03240a7c │ │ rsbeq r9, r5, #60, 10 @ 0xf000000 │ │ eorseq r0, r2, ip, lsl r6 │ │ │ │ @@ -1294137,15 +1294137,15 @@ │ │ eorseq r3, r0, r4, lsl #21 │ │ stc2l 13, cr2, [r1, #840]! @ 0x348 │ │ eorseq r3, r0, r4, asr #20 │ │ stc2l 13, cr2, [r1, #568]! @ 0x238 │ │ eorseq r3, r0, r0, lsl #20 │ │ stc2l 13, cr2, [r1, #104]! @ 0x68 │ │ eorseq r3, r0, ip, lsl #19 │ │ - ldc2l 3, cr4, [pc, #576] @ 2438160 │ │ + ldc2l 3, cr4, [pc, #756] @ 2438214 │ │ stc2l 11, cr2, [r1, #488]! @ 0x1e8 @ │ │ eorseq r3, r0, ip, ror #15 │ │ eorseq r0, r0, ip, asr #3 │ │ stc2l 11, cr2, [r1, #744]! @ 0x2e8 @ │ │ eorseq r3, r0, ip, lsr #16 │ │ stc2l 11, cr2, [r1, #1016]! @ 0x3f8 @ │ │ eorseq r3, r0, r0, ror r8 │ │ @@ -1294451,15 +1294451,15 @@ │ │ eorseq r3, r0, ip, ror #8 │ │ eorseq r3, r0, r8, ror #8 │ │ eorseq r3, r0, r0, lsr r4 │ │ stc2l 8, cr10, [r0, #68]! @ 0x44 │ │ eorseq r3, r0, ip, asr #32 │ │ eoreq pc, pc, r4, lsr sl @ │ │ eorseq r3, r0, r0, asr r0 │ │ - ldc2l 8, cr14, [pc, #844] @ 243874c │ │ + ldc2l 9, cr14, [pc] @ 2438400 @ │ │ eorseq r3, r0, ip, ror r1 │ │ mlaseq r0, ip, r1, r3 │ │ eorseq r3, r0, ip, lsr r1 │ │ eorseq r3, r0, r0, asr #1 │ │ stc2l 3, cr2, [r1, #920]! @ 0x398 │ │ eorseq r3, r0, r4, asr #5 │ │ ldrhteq r3, [r0], -r4 │ │ @@ -1294597,22 +1294597,22 @@ │ │ bl 270e2a0 │ │ add r0, sp, #16 │ │ mov r1, #320 @ 0x140 │ │ bl 270da00 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 8, cr12, [pc, #848] @ 2438980 │ │ + ldc2l 9, cr12, [pc, #2] @ 2438632 @ │ │ ldrhteq lr, [r1], -r8 │ │ - ldc2l 11, cr8, [lr, #848] @ 0x350 @ │ │ + ldc2l 12, cr8, [lr, #4] │ │ movteq r2, #10696 @ 0x29c8 │ │ stc2l 4, cr4, [r1, #944]! @ 0x3b0 │ │ eorseq lr, r1, r0, asr r9 │ │ eorseq lr, r1, ip, lsl r9 │ │ - ldc2l 11, cr8, [lr, #336] @ 0x150 @ │ │ + ldc2l 11, cr8, [lr, #516] @ 0x204 @ │ │ movteq r2, #10568 @ 0x2948 │ │ │ │ 0243864c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #44 @ 0x2c │ │ ldr r6, [fp, #8] │ │ @@ -1295130,21 +1295130,21 @@ │ │ andeq r0, r0, r5, asr r0 │ │ andeq r0, r0, r6, asr r0 │ │ andeq r0, r0, r7, asr r0 │ │ andeq r0, r0, r8, asr r0 │ │ movteq r2, #9096 @ 0x2388 │ │ movteq r2, #8948 @ 0x22f4 │ │ movteq r2, #8948 @ 0x22f4 │ │ - ldc2l 10, cr14, [lr, #492] @ 0x1ec @ │ │ - ldc2l 10, cr14, [lr, #504] @ 0x1f8 @ │ │ + ldc2l 10, cr14, [lr, #672] @ 0x2a0 @ │ │ + ldc2l 10, cr14, [lr, #684] @ 0x2ac @ │ │ movteq r2, #8844 @ 0x228c │ │ movteq r2, #9064 @ 0x2368 │ │ movteq r2, #9048 @ 0x2358 │ │ - ldc2l 10, cr14, [lr, #988] @ 0x3dc @ │ │ - ldc2l 10, cr14, [lr, #1000] @ 0x3e8 @ │ │ + ldc2l 11, cr14, [lr, #144] @ 0x90 @ │ │ + ldc2l 11, cr14, [lr, #156] @ 0x9c @ │ │ movteq r2, #8968 @ 0x2308 │ │ movteq r2, #8736 @ 0x2220 │ │ movteq r2, #8732 @ 0x221c │ │ │ │ 02438e94 : │ │ push {fp, lr} │ │ mov fp, sp │ │ @@ -1295203,15 +1295203,15 @@ │ │ mov r1, #5 │ │ bl 270ceb0 │ │ mov r0, r4 │ │ cmp r4, #0 │ │ movwne r0, #1 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - ldc2l 6, cr0, [pc, #544] @ 24391a0 │ │ + ldc2l 6, cr0, [pc, #724] @ 2439254 │ │ │ │ 02438f7c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ push {r2} @ (str r2, [sp, #-4]!) │ │ ldr r4, [r1] │ │ mov r7, r0 │ │ @@ -1295479,18 +1295479,18 @@ │ │ mov r1, #5 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ vcadd.f32 q8, q7, q5, #270 │ │ - ldc2l 0, cr2, [pc, #180] @ 243946c │ │ - ldc2l 15, cr5, [pc, #484] @ 24395a0 │ │ + ldc2l 0, cr2, [pc, #360] @ 2439520 │ │ + ldc2l 15, cr5, [pc, #664] @ 2439654 │ │ stc2l 13, cr3, [r0, #804]! @ 0x324 │ │ - ldc2l 11, cr9, [lr, #628] @ 0x274 @ │ │ + ldc2l 11, cr9, [lr, #808] @ 0x328 @ │ │ stc2l 14, cr6, [r1, #672]! @ 0x2a0 │ │ ldc2l 5, cr0, [lr, #72] @ 0x48 │ │ │ │ 024393c8 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ @@ -1295691,15 +1295691,15 @@ │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ stc2l 9, cr7, [r0, #178]! @ 0xb2 @ │ │ stc2l 15, cr4, [r1, #256]! @ 0x100 │ │ stc2l 10, cr5, [r0, #308]! @ 0x134 @ │ │ - ldc2l 7, cr9, [pc, #772] @ 24399dc │ │ + ldc2l 7, cr9, [pc, #952] @ 2439a90 │ │ stc2l 8, cr7, [r0, #116]! @ 0x74 │ │ │ │ 024396d8 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ mov r8, r3 │ │ mov r4, r2 │ │ @@ -1295767,19 +1295767,19 @@ │ │ bl 270da10 │ │ ldr r0, [pc, #32] @ 2439808 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ - ldc2l 15, cr1, [lr, #428] @ 0x1ac │ │ + ldc2l 15, cr1, [lr, #608] @ 0x260 │ │ stc2l 14, cr4, [r1, #32]! │ │ stc2l 9, cr5, [r0, #42]! @ 0x2a @ │ │ - ldc2l 6, cr9, [pc, #548] @ 2439a30 │ │ - ldc2l 14, cr1, [lr, #572] @ 0x23c │ │ + ldc2l 6, cr9, [pc, #728] @ 2439ae4 │ │ + ldc2l 14, cr1, [lr, #752] @ 0x2f0 │ │ │ │ 0243980c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #36 @ 0x24 │ │ mov r4, r3 │ │ mov r6, r2 │ │ @@ -1295891,16 +1295891,16 @@ │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 0, cr0, [lr, #464] @ 0x1d0 │ │ - ldc2l 7, cr3, [lr, #764] @ 0x2fc │ │ - ldc2l 5, cr9, [lr, #356] @ 0x164 │ │ + ldc2l 7, cr3, [lr, #944] @ 0x3b0 │ │ + ldc2l 5, cr9, [lr, #536] @ 0x218 │ │ ldc2l 4, cr15, [pc, #428] @ 2439b9c │ │ ldc2l 14, cr15, [sp, #928] @ 0x3a0 │ │ │ │ 024399f0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ @@ -1296412,30 +1296412,30 @@ │ │ strbcc r8, [r0, r0]! │ │ movtmi ip, #4985 @ 0x1379 │ │ ldmibls r9, {r1, r3, r4, r7, r8, fp, ip, pc} │ │ svccc 0x00b99999 │ │ ldc2l 0, cr13, [sp, #924] @ 0x39c │ │ stc2l 2, cr15, [r9, #528]! @ 0x210 │ │ stc2l 1, cr15, [r9, #960]! @ 0x3c0 │ │ - ldc2l 2, cr9, [pc, #48] @ 243a21c │ │ + ldc2l 2, cr9, [pc, #228] @ 243a2d0 │ │ ldc2l 3, cr11, [sp, #96] @ 0x60 │ │ - ldc2l 14, cr10, [pc, #964] @ 243a5b8 │ │ + ldc2l 15, cr10, [pc, #120] @ 243a26c │ │ ldc2l 2, cr11, [sp, #864] @ 0x360 │ │ stc2l 1, cr15, [r9, #208]! @ 0xd0 │ │ - ldc2l 2, cr1, [pc, #860] @ 243a55c │ │ + ldc2l 3, cr1, [pc, #16] @ 243a210 │ │ ldc2l 2, cr11, [sp, #96] @ 0x60 │ │ ldc2l 8, cr13, [sp, #104] @ 0x68 │ │ stc2l 0, cr15, [r9, #864]! @ 0x360 │ │ ldc2l 1, cr11, [sp, #592] @ 0x250 │ │ ldc2l 7, cr13, [sp, #744] @ 0x2e8 │ │ - ldc2l 2, cr1, [pc, #204] @ 243a2e4 │ │ + ldc2l 2, cr1, [pc, #384] @ 243a398 │ │ stc2l 9, cr2, [r1, #330]! @ 0x14a @ │ │ - ldc2l 11, cr12, [pc, #456] @ 243a3e8 @ │ │ + ldc2l 11, cr12, [pc, #636] @ 243a49c @ │ │ ldrhteq ip, [r1], -ip │ │ - ldc2l 15, cr10, [pc, #528] @ 243a438 │ │ + ldc2l 15, cr10, [pc, #708] @ 243a4ec │ │ stc2l 13, cr8, [r0, #32]! │ │ ldrhteq sp, [r1], -r4 │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ │ │ 0243a230 : │ │ push {fp, lr} │ │ mov fp, sp │ │ @@ -1296761,31 +1296761,31 @@ │ │ add r0, pc, r0 │ │ bl 270ce70 │ │ ldr r0, [pc, #32] @ 243a6fc │ │ add r0, pc, r0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r8, r9, sl, fp, lr} │ │ b 270ce40 │ │ - ldc2l 0, cr7, [lr, #368] @ 0x170 │ │ + ldc2l 0, cr7, [lr, #548] @ 0x224 │ │ stc2l 14, cr15, [r0, #228]! @ 0xe4 │ │ - ldc2l 8, cr8, [lr, #708] @ 0x2c4 │ │ - ldc2l 4, cr6, [lr, #220] @ 0xdc │ │ + ldc2l 8, cr8, [lr, #888] @ 0x378 │ │ + ldc2l 4, cr6, [lr, #400] @ 0x190 │ │ stc2l 3, cr8, [r0, #356]! @ 0x164 │ │ - ldc2l 15, cr6, [lr, #224] @ 0xe0 │ │ - ldc2l 11, cr0, [pc, #648] @ 243a990 @ │ │ - ldc2l 8, cr8, [lr, #580] @ 0x244 │ │ - ldc2l 4, cr6, [lr, #92] @ 0x5c │ │ - ldc2l 12, cr0, [lr, #696] @ 0x2b8 │ │ + ldc2l 15, cr6, [lr, #404] @ 0x194 │ │ + ldc2l 11, cr0, [pc, #828] @ 243aa44 @ │ │ + ldc2l 8, cr8, [lr, #760] @ 0x2f8 │ │ + ldc2l 4, cr6, [lr, #272] @ 0x110 │ │ + ldc2l 12, cr0, [lr, #876] @ 0x36c │ │ stc2l 13, cr15, [r0, #996]! @ 0x3e4 │ │ - ldc2l 8, cr8, [lr, #452] @ 0x1c4 │ │ - ldc2l 3, cr14, [lr, #316] @ 0x13c │ │ - ldc2l 11, cr0, [pc, #344] @ 243a87c @ │ │ - vcadd.f32 q12, q7, , #270 │ │ - ldc2l 3, cr14, [lr, #140] @ 0x8c │ │ - ldc2l 15, cr6, [lr, #912] @ 0x390 │ │ + ldc2l 8, cr8, [lr, #632] @ 0x278 │ │ + ldc2l 3, cr14, [lr, #496] @ 0x1f0 │ │ + ldc2l 11, cr0, [pc, #524] @ 243a930 @ │ │ + ldc2l 8, cr8, [lr, #456] @ 0x1c8 │ │ + ldc2l 3, cr14, [lr, #320] @ 0x140 │ │ + ldc2l 0, cr7, [lr, #68] @ 0x44 │ │ │ │ 0243a72c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ mov r5, r3 │ │ mov r7, r2 │ │ @@ -1296901,20 +1296901,20 @@ │ │ movteq r0, #11256 @ 0x2bf8 │ │ movteq r0, #11212 @ 0x2bcc │ │ movteq r0, #11232 @ 0x2be0 │ │ movteq r0, #11216 @ 0x2bd0 │ │ movteq r0, #11180 @ 0x2bac │ │ movteq r0, #11133 @ 0x2b7d │ │ movteq r0, #11180 @ 0x2bac │ │ - ldc2l 11, cr0, [pc, #1020] @ 243ad14 @ │ │ - ldc2l 6, cr8, [lr, #836] @ 0x344 │ │ + ldc2l 12, cr0, [pc, #176] @ 243a9c8 │ │ + ldc2l 6, cr8, [lr, #1016] @ 0x3f8 │ │ ldc2l 15, cr12, [sp, #644] @ 0x284 │ │ - ldc2l 6, cr8, [lr, #308] @ 0x134 │ │ + ldc2l 6, cr8, [lr, #488] @ 0x1e8 │ │ ldc2l 15, cr12, [sp, #756] @ 0x2f4 │ │ - ldc2l 6, cr8, [lr, #468] @ 0x1d4 │ │ + ldc2l 6, cr8, [lr, #648] @ 0x288 │ │ ldc2l 9, cr10, [sp, #158] @ 0x9e @ │ │ stc2l 2, cr8, [r0, #852]! @ 0x354 │ │ │ │ 0243a930 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ @@ -1297414,37 +1297414,37 @@ │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ str r1, [r2] │ │ mov r1, #255 @ 0xff │ │ bl 270ea40 │ │ b 243aad4 │ │ stc2l 13, cr11, [r0, #984]! @ 0x3d8 │ │ - ldc2l 9, cr2, [lr, #288] @ 0x120 @ │ │ + ldc2l 9, cr2, [lr, #378] @ 0x17a @ │ │ stc2l 10, cr15, [r0, #200]! @ 0xc8 @ │ │ - ldc2l 10, cr2, [lr, #508] @ 0x1fc @ │ │ + ldc2l 10, cr2, [lr, #688] @ 0x2b0 @ │ │ movteq r0, #10620 @ 0x297c │ │ movteq r0, #10528 @ 0x2920 │ │ - ldc2l 10, cr14, [lr, #728] @ 0x2d8 @ │ │ + ldc2l 10, cr14, [lr, #908] @ 0x38c @ │ │ movteq r0, #10510 @ 0x290e │ │ - ldc2l 9, cr4, [pc, #288] @ 243b250 @ │ │ + ldc2l 9, cr4, [pc, #378] @ 243b2aa @ │ │ eorseq ip, r1, ip, ror #24 │ │ eorseq ip, r1, ip, lsl #25 │ │ movteq r0, #10356 @ 0x2874 │ │ movteq r0, #10452 @ 0x28d4 │ │ movteq r0, #10436 @ 0x28c4 │ │ movteq r0, #9780 @ 0x2634 │ │ movteq r0, #9756 @ 0x261c │ │ movteq r0, #9852 @ 0x267c │ │ movteq r0, #9824 @ 0x2660 │ │ movteq r0, #9684 @ 0x25d4 │ │ movteq r0, #9760 @ 0x2620 │ │ movteq r0, #9092 @ 0x2384 │ │ movteq r0, #9756 @ 0x261c │ │ eorseq ip, r1, r8, lsl #12 │ │ - ldc2l 3, cr2, [lr, #940] @ 0x3ac │ │ + ldc2l 4, cr2, [lr, #96] @ 0x60 │ │ ldc2l 14, cr14, [sp, #812] @ 0x32c │ │ movteq r0, #10796 @ 0x2a2c │ │ ldc2l 14, cr14, [sp, #668] @ 0x29c │ │ ldc2l 3, cr12, [sp, #572] @ 0x23c │ │ mlaseq r1, r4, r9, ip │ │ mlaseq r1, r0, r8, ip │ │ movteq r0, #9720 @ 0x25f8 │ │ @@ -1297486,15 +1297486,15 @@ │ │ bl 270da10 │ │ mov r0, r4 │ │ mov r1, #5 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, sl, fp, pc} │ │ stc2l 6, cr11, [r0, #552]! @ 0x228 │ │ - ldc2l 2, cr2, [lr, #144] @ 0x90 │ │ + ldc2l 2, cr2, [lr, #324] @ 0x144 │ │ stc2l 2, cr15, [r0, #792]! @ 0x318 │ │ │ │ 0243b22c : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #16 │ │ mov r2, r0 │ │ @@ -1297984,59 +1297984,59 @@ │ │ mov r1, r0 │ │ ldr r0, [pc, #100] @ 243ba20 │ │ ldr r0, [pc, r0] │ │ str r4, [r8, r1, lsl #2] │ │ ldr r4, [sp, #4] │ │ str r0, [sl] │ │ b 243b650 │ │ - ldc2l 15, cr1, [lr, #808] @ 0x328 │ │ + ldc2l 15, cr1, [lr, #988] @ 0x3dc │ │ ldrhteq ip, [r1], -ip │ │ eorseq ip, r1, r4, ror #3 │ │ vcadd.f32 , , , #270 │ │ movteq pc, #8128 @ 0x1fc0 @ │ │ - ldc2l 11, cr7, [pc, #488] @ 243bbd0 @ │ │ - ldc2l 9, cr7, [lr, #194] @ 0xc2 @ │ │ + ldc2l 11, cr7, [pc, #668] @ 243bc84 @ │ │ + ldc2l 9, cr7, [lr, #284] @ 0x11c @ │ │ ldc2l 9, cr7, [sp, #110] @ 0x6e @ │ │ movteq pc, #7688 @ 0x1e08 @ │ │ movteq pc, #7692 @ 0x1e0c @ │ │ movteq pc, #7664 @ 0x1df0 @ │ │ movteq pc, #7076 @ 0x1ba4 @ │ │ vcmla.f16 d17, d16, d30, #270 │ │ - ldc2l 10, cr1, [pc, #672] @ 243bca8 @ │ │ + ldc2l 10, cr1, [pc, #852] @ 243bd5c @ │ │ vcadd.f32 , , , #270 │ │ stc2l 1, cr1, [r1, #448]! @ 0x1c0 │ │ - ldc2l 5, cr7, [lr, #628] @ 0x274 │ │ + ldc2l 5, cr7, [lr, #808] @ 0x328 │ │ ldc2l 4, cr13, [pc, #484] @ 243bbfc │ │ movteq pc, #6828 @ 0x1aac @ │ │ stc2l 1, cr1, [r1, #168]! @ 0xa8 │ │ ldc2l 7, cr15, [pc, #820] @ 243bd58 │ │ movteq pc, #6776 @ 0x1a78 @ │ │ eorseq ip, r1, r4, ror #2 │ │ movteq pc, #7624 @ 0x1dc8 @ │ │ stc2l 4, cr1, [r1, #280]! @ 0x118 │ │ ldc2l 10, cr15, [pc, #932] @ 243bddc @ │ │ movteq pc, #7960 @ 0x1f18 @ │ │ - ldc2l 10, cr7, [pc, #448] @ 243bc00 @ │ │ + ldc2l 10, cr7, [pc, #628] @ 243bcb4 @ │ │ ldrsbteq ip, [r1], -ip │ │ movteq pc, #7456 @ 0x1d20 @ │ │ stc2l 3, cr1, [r1, #616]! @ 0x268 │ │ ldc2l 10, cr15, [pc, #244] @ 243bb44 @ │ │ movteq pc, #7404 @ 0x1cec @ │ │ movteq pc, #7376 @ 0x1cd0 @ │ │ movteq pc, #7364 @ 0x1cc4 @ │ │ stc2l 3, cr1, [r1, #312]! @ 0x138 │ │ ldc2l 9, cr15, [pc, #482] @ 243bc46 @ │ │ movteq pc, #7236 @ 0x1c44 @ │ │ movteq pc, #7216 @ 0x1c30 @ │ │ ldc2l 6, cr11, [sp, #268] @ 0x10c │ │ mlaseq r1, r8, pc, fp @ │ │ - ldc2l 12, cr1, [lr, #456] @ 0x1c8 │ │ - ldc2l 4, cr11, [pc, #292] @ 243bba0 │ │ - ldc2l 6, cr7, [lr, #596] @ 0x254 │ │ - ldc2l 11, cr5, [lr, #476] @ 0x1dc @ │ │ + ldc2l 12, cr1, [lr, #636] @ 0x27c │ │ + ldc2l 4, cr11, [pc, #472] @ 243bc54 │ │ + ldc2l 6, cr7, [lr, #776] @ 0x308 │ │ + ldc2l 11, cr5, [lr, #656] @ 0x290 @ │ │ stc2l 14, cr1, [r0, #428]! @ 0x1ac │ │ movteq r0, #8368 @ 0x20b0 │ │ movteq r0, #8372 @ 0x20b4 │ │ movteq r0, #8344 @ 0x2098 │ │ stc2l 7, cr1, [r1, #24]! │ │ ldc2l 13, cr15, [pc, #676] @ 243bd40 │ │ movteq r0, #8260 @ 0x2044 │ │ @@ -1298139,15 +1298139,15 @@ │ │ sub sp, fp, #8 │ │ pop {r4, sl, fp, pc} │ │ ldc2l 13, cr13, [sp, #408] @ 0x198 │ │ ldc2l 5, cr15, [pc, #660] @ 243beac │ │ stc2l 9, cr14, [r0, #90]! @ 0x5a @ │ │ ldc2l 12, cr13, [sp, #808] @ 0x328 │ │ stc2l 12, cr10, [r0, #944]! @ 0x3b0 │ │ - ldc2l 3, cr7, [lr, #388] @ 0x184 │ │ + ldc2l 3, cr7, [lr, #568] @ 0x238 │ │ ldc2l 3, cr7, [sp, #284] @ 0x11c │ │ ldc2l 12, cr13, [sp, #984] @ 0x3d8 │ │ │ │ 0243bc2c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #108 @ 0x6c │ │ @@ -1298604,73 +1298604,73 @@ │ │ str r1, [r0] │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ movteq pc, #6520 @ 0x1978 @ │ │ movteq pc, #6240 @ 0x1860 @ │ │ movteq pc, #6240 @ 0x1860 @ │ │ - ldc2l 15, cr10, [pc, #208] @ 243c434 │ │ - ldc2l 7, cr1, [lr, #228] @ 0xe4 │ │ + ldc2l 15, cr10, [pc, #388] @ 243c4e8 │ │ + ldc2l 7, cr1, [lr, #408] @ 0x198 │ │ movteq pc, #6172 @ 0x181c @ │ │ stc2l 1, cr13, [r9, #464]! @ 0x1d0 │ │ - ldc2l 6, cr3, [lr, #744] @ 0x2e8 │ │ - ldc2l 4, cr1, [lr, #836] @ 0x344 │ │ + ldc2l 6, cr3, [lr, #924] @ 0x39c │ │ + ldc2l 4, cr1, [lr, #1016] @ 0x3f8 │ │ movteq pc, #5556 @ 0x15b4 @ │ │ eorseq fp, r1, ip, ror r8 │ │ - ldc2l 12, cr10, [pc, #240] @ 243c474 │ │ - ldc2l 4, cr1, [lr, #260] @ 0x104 │ │ + ldc2l 12, cr10, [pc, #420] @ 243c528 │ │ + ldc2l 4, cr1, [lr, #440] @ 0x1b8 │ │ movteq pc, #5812 @ 0x16b4 @ │ │ movteq pc, #5324 @ 0x14cc @ │ │ movteq pc, #4920 @ 0x1338 @ │ │ movteq pc, #5172 @ 0x1434 @ │ │ movteq pc, #5784 @ 0x1698 @ │ │ - ldc2l 11, cr10, [pc, #992] @ 243c780 @ │ │ - ldc2l 3, cr1, [lr, #1012] @ 0x3f4 │ │ + ldc2l 12, cr10, [pc, #148] @ 243c434 │ │ + ldc2l 4, cr1, [lr, #168] @ 0xa8 │ │ movteq pc, #5348 @ 0x14e4 @ │ │ movteq pc, #5284 @ 0x14a4 @ │ │ movteq pc, #5588 @ 0x15d4 @ │ │ mlaseq r1, r8, r5, fp │ │ movteq pc, #4748 @ 0x128c @ │ │ eorseq fp, r1, ip, asr #11 │ │ movteq pc, #5548 @ 0x15ac @ │ │ - ldc2l 3, cr1, [lr, #68] @ 0x44 │ │ - ldc2l 10, cr10, [pc, #832] @ 243c708 @ │ │ + ldc2l 3, cr1, [lr, #248] @ 0xf8 │ │ + ldc2l 10, cr10, [pc, #1012] @ 243c7bc @ │ │ movteq pc, #5124 @ 0x1404 @ │ │ movteq pc, #5056 @ 0x13c0 @ │ │ movteq pc, #4964 @ 0x1364 @ │ │ movteq pc, #5356 @ 0x14ec @ │ │ eorseq fp, r1, r4, asr r6 │ │ movteq pc, #6360 @ 0x18d8 @ │ │ movteq pc, #6344 @ 0x18c8 @ │ │ - ldc2l 15, cr10, [pc, #720] @ 243c6b8 │ │ - ldc2l 7, cr1, [lr, #740] @ 0x2e4 │ │ + ldc2l 15, cr10, [pc, #900] @ 243c76c │ │ + ldc2l 7, cr1, [lr, #920] @ 0x398 │ │ movteq pc, #6300 @ 0x189c @ │ │ stc2l 2, cr13, [r9, #128]! @ 0x80 │ │ - ldc2l 7, cr3, [lr, #408] @ 0x198 │ │ - ldc2l 5, cr1, [lr, #500] @ 0x1f4 │ │ + ldc2l 7, cr3, [lr, #588] @ 0x24c │ │ + ldc2l 5, cr1, [lr, #680] @ 0x2a8 │ │ movteq pc, #5728 @ 0x1660 @ │ │ movteq pc, #5660 @ 0x161c @ │ │ movteq pc, #5636 @ 0x1604 @ │ │ movteq pc, #6484 @ 0x1954 @ │ │ movteq pc, #6468 @ 0x1944 @ │ │ - ldc2l 0, cr11, [pc, #192] @ 243c4d4 │ │ - ldc2l 8, cr1, [lr, #212] @ 0xd4 │ │ + ldc2l 0, cr11, [pc, #372] @ 243c588 │ │ + vcadd.f32 , q7, q9, #270 │ │ movteq pc, #6424 @ 0x1918 @ │ │ stc2l 3, cr13, [r9, #432]! @ 0x1b0 │ │ - ldc2l 8, cr3, [lr, #712] @ 0x2c8 │ │ - ldc2l 6, cr1, [lr, #804] @ 0x324 │ │ + ldc2l 8, cr3, [lr, #892] @ 0x37c │ │ + ldc2l 6, cr1, [lr, #984] @ 0x3d8 │ │ movteq pc, #6060 @ 0x17ac @ │ │ movteq pc, #5992 @ 0x1768 @ │ │ movteq pc, #5964 @ 0x174c @ │ │ stc2l 2, cr13, [r9, #832]! @ 0x340 │ │ - ldc2l 8, cr3, [lr, #88] @ 0x58 │ │ - ldc2l 6, cr1, [lr, #180] @ 0xb4 │ │ + vcadd.f32 , q7, , #270 │ │ + ldc2l 6, cr1, [lr, #360] @ 0x168 │ │ movteq pc, #5880 @ 0x16f8 @ │ │ - ldc2l 13, cr10, [pc, #752] @ 243c738 │ │ - ldc2l 5, cr1, [lr, #772] @ 0x304 │ │ + ldc2l 13, cr10, [pc, #932] @ 243c7ec │ │ + ldc2l 5, cr1, [lr, #952] @ 0x3b8 │ │ movteq pc, #5812 @ 0x16b4 @ │ │ │ │ 0243c44c : │ │ push {fp, lr} │ │ mov fp, sp │ │ mov r1, r0 │ │ mov r0, #0 │ │ @@ -1299354,47 +1299354,47 @@ │ │ movw r3, #383 @ 0x17f │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 243cc84 │ │ ldc2l 13, cr8, [sp, #316] @ 0x13c │ │ stc2l 11, cr0, [r0, #872]! @ 0x368 @ │ │ - ldc2l 9, cr6, [lr, #178] @ 0xb2 @ │ │ + ldc2l 9, cr6, [lr, #268] @ 0x10c @ │ │ ldc2l 12, cr8, [sp, #348] @ 0x15c │ │ stc2l 9, cr0, [r0, #204]! @ 0xcc @ │ │ - ldc2l 6, cr6, [lr, #916] @ 0x394 │ │ - ldc2l 14, cr14, [lr, #880] @ 0x370 │ │ + ldc2l 7, cr6, [lr, #72] @ 0x48 │ │ + ldc2l 15, cr14, [lr, #36] @ 0x24 │ │ stc2l 1, cr14, [r0, #844]! @ 0x34c │ │ stc2l 11, cr0, [r0, #508]! @ 0x1fc @ │ │ - ldc2l 13, cr14, [lr, #144] @ 0x90 │ │ + ldc2l 13, cr14, [lr, #324] @ 0x144 │ │ stc2l 0, cr14, [r0, #108]! @ 0x6c │ │ - ldc2l 12, cr14, [lr, #928] @ 0x3a0 │ │ + ldc2l 13, cr14, [lr, #84] @ 0x54 │ │ stc2l 15, cr13, [r0, #892]! @ 0x37c │ │ stc2l 10, cr13, [r0, #908]! @ 0x38c @ │ │ stc2l 5, cr0, [r0, #220]! @ 0xdc │ │ - ldc2l 7, cr14, [lr, #656] @ 0x290 │ │ - ldc2l 7, cr14, [lr, #48] @ 0x30 │ │ + ldc2l 7, cr14, [lr, #836] @ 0x344 │ │ + ldc2l 7, cr14, [lr, #228] @ 0xe4 │ │ eorseq sl, r1, r8, lsr #22 │ │ - ldc2l 5, cr14, [lr, #736] @ 0x2e0 │ │ - ldc2l 5, cr14, [lr, #528] @ 0x210 │ │ - ldc2l 12, cr14, [lr, #656] @ 0x290 │ │ + ldc2l 5, cr14, [lr, #916] @ 0x394 │ │ + ldc2l 5, cr14, [lr, #708] @ 0x2c4 │ │ + ldc2l 12, cr14, [lr, #836] @ 0x344 │ │ stc2l 15, cr13, [r0, #620]! @ 0x26c │ │ - ldc2l 13, cr14, [sp, #488] @ 0x1e8 │ │ + ldc2l 13, cr14, [sp, #668] @ 0x29c │ │ stc2l 14, cr13, [r0, #332]! @ 0x14c │ │ - ldc2l 11, cr14, [sp, #840] @ 0x348 @ │ │ + ldc2l 11, cr14, [sp, #1020] @ 0x3fc @ │ │ stc2l 12, cr13, [r0, #684]! @ 0x2ac │ │ stc2l 12, cr13, [r0, #476]! @ 0x1dc │ │ - ldc2l 11, cr14, [sp, #408] @ 0x198 @ │ │ + ldc2l 11, cr14, [sp, #588] @ 0x24c @ │ │ stc2l 12, cr13, [r0, #252]! @ 0xfc │ │ - ldc2l 11, cr14, [sp, #216] @ 0xd8 @ │ │ + ldc2l 11, cr14, [sp, #396] @ 0x18c @ │ │ stc2l 12, cr13, [r0, #60]! @ 0x3c │ │ - ldc2l 12, cr14, [lr, #80] @ 0x50 │ │ + ldc2l 12, cr14, [lr, #260] @ 0x104 │ │ stc2l 15, cr13, [r0, #44]! @ 0x2c │ │ stc2l 9, cr3, [r1, #312]! @ 0x138 @ │ │ - ldc2l 10, cr14, [sp, #472] @ 0x1d8 @ │ │ + ldc2l 10, cr14, [sp, #652] @ 0x28c @ │ │ stc2l 11, cr13, [r0, #316]! @ 0x13c @ │ │ stc2l 5, cr0, [r0, #492]! @ 0x1ec │ │ stc2l 11, cr13, [r0, #124]! @ 0x7c @ │ │ ldc2l 12, cr8, [sp, #364] @ 0x16c │ │ │ │ 0243cf88 : │ │ vmov.f64 d16, #112 @ 0x3f800000 1.0 │ │ @@ -1300452,16 +1300452,16 @@ │ │ ldr r0, [fp, #16] │ │ ldr r0, [r0] │ │ ldr r1, [pc, #3884] @ 243ef2c │ │ ldr r1, [pc, r1] │ │ cmp r1, r0 │ │ bne 243dea4 │ │ b 243fc64 │ │ - ldc2l 7, cr8, [lr, #176] @ 0xb0 │ │ - ldc2l 13, cr7, [pc, #800] @ 243e338 │ │ + ldc2l 7, cr8, [lr, #356] @ 0x164 │ │ + ldc2l 13, cr7, [pc, #980] @ 243e3ec │ │ stc2l 6, cr13, [r0, #940]! @ 0x3ac │ │ movteq lr, #5840 @ 0x16d0 │ │ ldr r0, [pc, #4080] @ 243f014 │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #4076] @ 243f018 │ │ ldr r1, [pc, r1] │ │ add r0, r1, r0 │ │ @@ -1300514,15 +1300514,15 @@ │ │ movteq sp, #18856 @ 0x49a8 │ │ movteq r8, #18376 @ 0x47c8 │ │ movteq r0, #44864 @ 0xaf40 │ │ movteq sp, #27700 @ 0x6c34 │ │ movteq r1, #41352 @ 0xa188 │ │ movteq pc, #6636 @ 0x19ec @ │ │ movteq pc, #6620 @ 0x19dc @ │ │ - ldc2l 2, cr2, [pc, #428] @ 243e2b8 │ │ + ldc2l 2, cr2, [pc, #608] @ 243e36c │ │ stc2l 3, cr1, [r1, #544]! @ 0x220 │ │ movteq r2, #41944 @ 0xa3d8 │ │ ldc2l 6, cr12, [sp, #276] @ 0x114 │ │ stc2l 3, cr1, [r1, #288]! @ 0x120 │ │ movteq sp, #18568 @ 0x4888 │ │ stc2l 15, cr2, [r1, #672]! @ 0x2a0 │ │ movteq lr, #5260 @ 0x148c │ │ @@ -1300660,15 +1300660,15 @@ │ │ eorseq sl, r1, r8, lsr r5 │ │ eorseq sl, r1, r4, lsr r5 │ │ movteq lr, #5037 @ 0x13ad │ │ movteq sp, #18284 @ 0x476c │ │ movteq lr, #4972 @ 0x136c │ │ movteq fp, #39841 @ 0x9ba1 │ │ ldc2l 4, cr10, [sp, #820] @ 0x334 │ │ - ldc2l 10, cr5, [lr, #868] @ 0x364 @ │ │ + ldc2l 11, cr5, [lr, #24] @ │ │ ldr r1, [pc, #4040] @ 243f320 │ │ mov r0, r5 │ │ ldr r2, [pc, #4036] @ 243f324 │ │ mov r3, #36 @ 0x24 │ │ add r1, pc, r1 │ │ add r2, pc, r2 │ │ bl 270ce00 │ │ @@ -1300766,15 +1300766,15 @@ │ │ str r0, [r4] │ │ b 243e75c │ │ movteq r0, #44108 @ 0xac4c │ │ movteq sp, #26944 @ 0x6940 │ │ movteq r0, #44692 @ 0xae94 │ │ movteq pc, #5880 @ 0x16f8 @ │ │ movteq pc, #5860 @ 0x16e4 @ │ │ - ldc2l 15, cr1, [pc, #460] @ 243e6c8 │ │ + ldc2l 15, cr1, [pc, #640] @ 243e77c │ │ stc2l 0, cr1, [r1, #576]! @ 0x240 │ │ ldr r0, [pc, #4056] @ 243f4dc │ │ mov r7, #32 │ │ ldr r1, [pc, #4052] @ 243f4e0 │ │ ldr r3, [pc, #4052] @ 243f4e4 │ │ add r0, pc, r0 │ │ ldr r2, [pc, #4048] @ 243f4e8 │ │ @@ -1300897,15 +1300897,15 @@ │ │ str r0, [sl] │ │ ldr r0, [pc, #3876] @ 243f614 │ │ add r0, pc, r0 │ │ b 243fbf4 │ │ movteq sp, #17436 @ 0x441c │ │ movteq fp, #38997 @ 0x9855 │ │ ldc2l 1, cr10, [sp, #516] @ 0x204 │ │ - ldc2l 7, cr5, [lr, #580] @ 0x244 │ │ + ldc2l 7, cr5, [lr, #760] @ 0x2f8 │ │ ldr r0, [pc, #3852] @ 243f618 │ │ movw r3, #3079 @ 0xc07 │ │ ldr r2, [pc, #3848] @ 243f61c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #3836] @ 243f620 │ │ @@ -1300942,15 +1300942,15 @@ │ │ movteq pc, #5752 @ 0x1678 @ │ │ movteq r8, #16788 @ 0x4194 │ │ movteq r0, #43292 @ 0xa91c │ │ movteq sp, #26128 @ 0x6610 │ │ movteq r0, #43876 @ 0xab64 │ │ movteq pc, #5064 @ 0x13c8 @ │ │ movteq pc, #5040 @ 0x13b0 @ │ │ - ldc2l 12, cr1, [pc, #252] @ 243e8b8 │ │ + ldc2l 12, cr1, [pc, #432] @ 243e96c │ │ stc2l 13, cr0, [r1, #368]! @ 0x170 │ │ movteq r1, #44460 @ 0xadac │ │ movteq r8, #16616 @ 0x40e8 │ │ movteq pc, #4936 @ 0x1348 @ │ │ ldc2l 15, cr11, [sp, #996] @ 0x3e4 │ │ stc2l 12, cr0, [r1, #1008]! @ 0x3f0 │ │ ldr r0, [pc, #3980] @ 243f764 │ │ @@ -1301019,15 +1301019,15 @@ │ │ mov r0, #1 │ │ str r0, [r2] │ │ ldr r0, [pc, #4040] @ 243f8a4 │ │ add r0, pc, r0 │ │ b 243fbf4 │ │ movteq sp, #16956 @ 0x423c │ │ ldc2l 5, cr9, [sp, #332] @ 0x14c │ │ - ldc2l 14, cr7, [lr, #272] @ 0x110 │ │ + ldc2l 14, cr7, [lr, #452] @ 0x1c4 │ │ ldc2l 6, cr11, [pc, #992] @ 243ecd4 │ │ movteq sp, #7672 @ 0x1df8 │ │ movteq pc, #4752 @ 0x1290 @ │ │ movteq sp, #26412 @ 0x672c │ │ movteq fp, #38472 @ 0x9648 │ │ eorseq r9, r1, ip, lsr pc │ │ movteq r8, #25400 @ 0x6338 │ │ @@ -1301109,23 +1301109,23 @@ │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #4056] @ 243fa1c │ │ add r0, pc, r0 │ │ ldr r0, [r0, r1, lsl #2] │ │ b 243fb30 │ │ movteq pc, #5084 @ 0x13dc @ │ │ - ldc2l 12, cr9, [lr, #436] @ 0x1b4 │ │ + ldc2l 12, cr9, [lr, #616] @ 0x268 │ │ stc2l 11, cr0, [r1, #160]! @ 0xa0 @ │ │ stc2l 2, cr6, [r0, #968]! @ 0x3c8 │ │ movteq pc, #4968 @ 0x1368 @ │ │ movteq pc, #4912 @ 0x1330 @ │ │ ldc2l 6, cr13, [pc, #376] @ 243ebe4 │ │ - ldc2l 9, cr13, [lr, #28] @ │ │ + ldc2l 9, cr13, [lr, #118] @ 0x76 @ │ │ stc2l 9, cr12, [r0, #196]! @ 0xc4 @ │ │ - ldc2l 11, cr1, [lr, #116] @ 0x74 @ │ │ + ldc2l 11, cr1, [lr, #296] @ 0x128 @ │ │ movteq sp, #7100 @ 0x1bbc │ │ movteq fp, #37908 @ 0x9414 │ │ eorseq r9, r1, r8, lsl #26 │ │ movteq r8, #24836 @ 0x6104 │ │ movteq r8, #23740 @ 0x5cbc │ │ mov r0, #1 │ │ ldr sl, [fp, #-32] @ 0xffffffe0 │ │ @@ -1301226,16 +1301226,16 @@ │ │ movteq sp, #25680 @ 0x6450 │ │ movteq lr, #8092 @ 0x1f9c │ │ movteq r7, #23900 @ 0x5d5c │ │ eorseq r9, r1, r0, ror #24 │ │ eorseq r9, r1, ip, asr ip │ │ movteq sp, #6869 @ 0x1ad5 │ │ movteq ip, #20116 @ 0x4e94 │ │ - ldc2l 9, cr1, [lr, #498] @ 0x1f2 @ │ │ - vcadd.f32 d31, d13, d5, #270 │ │ + ldc2l 10, cr1, [lr, #152] @ 0x98 @ │ │ + ldc2l 8, cr15, [sp, #200] @ 0xc8 │ │ movteq sp, #6792 @ 0x1a88 │ │ movteq fp, #37600 @ 0x92e0 │ │ ldrsbteq r9, [r1], -r4 │ │ movteq r7, #28624 @ 0x6fd0 │ │ movteq r8, #23432 @ 0x5b88 │ │ movteq fp, #37556 @ 0x92b4 │ │ movteq sp, #26084 @ 0x65e4 │ │ @@ -1301251,15 +1301251,15 @@ │ │ movteq sp, #25372 @ 0x631c │ │ movteq lr, #7784 @ 0x1e68 │ │ movteq r7, #23592 @ 0x5c28 │ │ eorseq r9, r1, ip, lsr #22 │ │ eorseq r9, r1, r8, lsr #22 │ │ movteq sp, #6561 @ 0x19a1 │ │ movteq ip, #19808 @ 0x4d60 │ │ - ldc2l 6, cr15, [sp, #868] @ 0x364 │ │ + ldc2l 7, cr15, [sp, #24] │ │ ldr r0, [pc, #3956] @ 243fc08 │ │ ldr r1, [pc, #3956] @ 243fc0c │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ bl 270eaf0 │ │ ldr r0, [pc, #3944] @ 243fc10 │ │ ldr r0, [pc, r0] │ │ @@ -1301414,15 +1301414,15 @@ │ │ b 243eff4 │ │ movteq lr, #8032 @ 0x1f60 │ │ movteq r1, #43956 @ 0xabb4 │ │ movteq fp, #37008 @ 0x9090 │ │ movteq lr, #7968 @ 0x1f20 │ │ ldc2l 9, cr11, [sp, #216] @ 0xd8 @ │ │ stc2l 6, cr0, [r1, #416]! @ 0x1a0 │ │ - ldc2l 2, cr5, [lr, #164] @ 0xa4 │ │ + ldc2l 2, cr5, [lr, #344] @ 0x158 │ │ movteq r1, #43836 @ 0xab3c │ │ movteq r7, #21860 @ 0x5564 │ │ movteq r1, #43800 @ 0xab18 │ │ movteq lr, #7836 @ 0x1e9c │ │ movteq r1, #43760 @ 0xaaf0 │ │ movteq r7, #21784 @ 0x5518 │ │ ldr r0, [pc, #3856] @ 243fe48 │ │ @@ -1301552,22 +1301552,22 @@ │ │ ldr r0, [pc, #3940] @ 244008c │ │ add r0, pc, r0 │ │ b 243fbf4 │ │ movteq ip, #18900 @ 0x49d4 │ │ movteq ip, #18888 @ 0x49c8 │ │ movteq ip, #18876 @ 0x49bc │ │ ldc2l 7, cr9, [sp, #404] @ 0x194 │ │ - ldc2l 13, cr4, [lr, #484] @ 0x1e4 │ │ + ldc2l 13, cr4, [lr, #664] @ 0x298 │ │ movteq ip, #18824 @ 0x4988 │ │ movteq ip, #18788 @ 0x4964 │ │ movteq lr, #7352 @ 0x1cb8 │ │ movteq sl, #40424 @ 0x9de8 │ │ movteq ip, #18764 @ 0x494c │ │ stc2l 8, cr14, [r0, #976]! @ 0x3d0 │ │ - ldc2l 13, cr4, [lr, #4] │ │ + ldc2l 13, cr4, [lr, #184] @ 0xb8 │ │ ldr r1, [pc, #4088] @ 244015c │ │ mov r0, r5 │ │ ldr r2, [pc, #4084] @ 2440160 │ │ ldr r3, [pc, #4084] @ 2440164 │ │ add r1, pc, r1 │ │ add r2, pc, r2 │ │ add r3, pc, r3 │ │ @@ -1301616,15 +1301616,15 @@ │ │ mov r1, #1 │ │ b 243fe0c │ │ movteq pc, #40700 @ 0x9efc @ │ │ movteq ip, #27632 @ 0x6bf0 │ │ movteq r0, #41284 @ 0xa144 │ │ movteq lr, #6564 @ 0x19a4 │ │ movteq lr, #6544 @ 0x1990 │ │ - ldc2l 2, cr1, [pc, #108] @ 243f2b0 │ │ + ldc2l 2, cr1, [pc, #288] @ 243f364 │ │ stc2l 3, cr0, [r1, #224]! @ 0xe0 │ │ movteq r1, #41864 @ 0xa388 │ │ ldc2l 5, cr11, [sp, #964] @ 0x3c4 │ │ stc2l 2, cr0, [r1, #976]! @ 0x3d0 │ │ movteq ip, #18484 @ 0x4834 │ │ ldr r6, [pc, #4076] @ 2440248 │ │ mov r2, #32 │ │ @@ -1301677,15 +1301677,15 @@ │ │ ldr r0, [pc, #3928] @ 2440274 │ │ add r0, pc, r0 │ │ b 243fbf4 │ │ movteq ip, #19540 @ 0x4c54 │ │ movteq ip, #18348 @ 0x47ac │ │ movteq ip, #18336 @ 0x47a0 │ │ ldc2l 5, cr9, [sp, #292] @ 0x124 │ │ - ldc2l 11, cr4, [lr, #372] @ 0x174 @ │ │ + ldc2l 11, cr4, [lr, #552] @ 0x228 @ │ │ movteq ip, #19464 @ 0x4c08 │ │ movteq ip, #18220 @ 0x472c │ │ movteq lr, #6784 @ 0x1a80 │ │ movteq sl, #39856 @ 0x9bb0 │ │ ldr r0, [pc, #4092] @ 2440348 │ │ ldr r1, [pc, #4092] @ 244034c │ │ ldr r2, [pc, #4092] @ 2440350 │ │ @@ -1301867,15 +1301867,15 @@ │ │ stc2l 15, cr15, [r0] │ │ movteq sp, #21292 @ 0x532c │ │ stc2l 0, cr12, [r0, #476]! @ 0x1dc │ │ ldc2l 1, cr11, [sp, #724] @ 0x2d4 │ │ stc2l 14, cr15, [r0, #736]! @ 0x2e0 │ │ movteq ip, #17404 @ 0x43fc │ │ movteq lr, #5944 @ 0x1738 │ │ - ldc2l 10, cr3, [pc, #108] @ 243f69c @ │ │ + ldc2l 10, cr3, [pc, #288] @ 243f750 @ │ │ stc2l 14, cr15, [r0, #496]! @ 0x1f0 │ │ ldr r0, [pc, #3836] @ 2440534 │ │ mov r2, r4 │ │ ldr r1, [pc, #3832] @ 2440538 │ │ mov r3, #6 │ │ add r0, pc, r0 │ │ str r5, [sp] │ │ @@ -1302129,15 +1302129,15 @@ │ │ movteq r6, #23140 @ 0x5a64 │ │ movteq ip, #17064 @ 0x42a8 │ │ movteq lr, #4404 @ 0x1134 │ │ movteq lr, #4388 @ 0x1124 │ │ stc2l 0, cr4, [r0, #736]! @ 0x2e0 │ │ stc2l 10, cr15, [r0, #832]! @ 0x340 @ │ │ movteq ip, #17612 @ 0x44cc │ │ - ldc2l 6, cr3, [pc, #188] @ 243fb04 │ │ + ldc2l 6, cr3, [pc, #368] @ 243fbb8 │ │ stc2l 10, cr15, [r0, #576]! @ 0x240 @ │ │ ldr r0, [pc, #3680] @ 24408b0 │ │ ldr r1, [pc, #3680] @ 24408b4 │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ bl 270eaf0 │ │ ldr r0, [pc, #3668] @ 24408b8 │ │ @@ -1302207,15 +1302207,15 @@ │ │ mov r3, #1 │ │ add r1, pc, r1 │ │ b 243f004 │ │ stc2l 2, cr5, [r0, #120]! @ 0x78 │ │ stc2l 10, cr15, [r0, #304]! @ 0x130 @ │ │ movteq lr, #4208 @ 0x1070 │ │ movteq lr, #4180 @ 0x1054 │ │ - ldc2l 11, cr8, [lr, #308] @ 0x134 @ │ │ + ldc2l 11, cr8, [lr, #488] @ 0x1e8 @ │ │ stc2l 10, cr15, [r0, #32]! @ │ │ movteq ip, #25804 @ 0x64cc │ │ ldr r0, [pc, #3564] @ 2440978 │ │ mov r1, #132 @ 0x84 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #3552] @ 244097c │ │ @@ -1302255,19 +1302255,19 @@ │ │ movteq ip, #26176 @ 0x6640 │ │ movteq r6, #28660 @ 0x6ff4 │ │ movteq r7, #23468 @ 0x5bac │ │ movteq r6, #28632 @ 0x6fd8 │ │ movteq r7, #23440 @ 0x5b90 │ │ movteq ip, #17736 @ 0x4548 │ │ movteq sp, #7912 @ 0x1ee8 │ │ - ldc2l 7, cr14, [sp, #592] @ 0x250 │ │ + ldc2l 7, cr14, [sp, #772] @ 0x304 │ │ stc2l 8, cr15, [r0, #576]! @ 0x240 │ │ movteq r6, #19544 @ 0x4c58 │ │ movteq sp, #7828 @ 0x1e94 │ │ - ldc2l 3, cr4, [lr, #640] @ 0x280 │ │ + ldc2l 3, cr4, [lr, #820] @ 0x334 │ │ vcmla.f16 , q0, q4, #270 │ │ movteq r1, #28120 @ 0x6dd8 │ │ movteq sp, #7760 @ 0x1e50 │ │ stc2l 1, cr2, [r0, #64]! @ 0x40 │ │ vcmla.f16 d31, d0, d4, #270 │ │ movteq r1, #21976 @ 0x55d8 │ │ ldr r0, [pc, #3356] @ 2440988 │ │ @@ -1302363,15 +1302363,15 @@ │ │ bl 270db90 │ │ cmp r0, #0 │ │ bne 243fbec │ │ ldr r1, [fp, #20] │ │ mov r0, #1 │ │ str r0, [r1] │ │ b 243fbec │ │ - ldc2l 8, cr0, [lr, #740] @ 0x2e4 │ │ + vcadd.f32 q8, q15, q11, #270 │ │ ldr r1, [pc, #2872] @ 244092c │ │ mov r0, r7 │ │ mov r2, r6 │ │ mov r3, #1 │ │ add r1, pc, r1 │ │ bl 270d9e0 │ │ mov r1, #0 │ │ @@ -1302402,15 +1302402,15 @@ │ │ movteq r6, #27956 @ 0x6d34 │ │ movteq r7, #22764 @ 0x58ec │ │ movteq ip, #17060 @ 0x42a4 │ │ movteq sp, #7236 @ 0x1c44 │ │ ldc2l 0, cr4, [sp, #516] @ 0x204 │ │ stc2l 5, cr15, [r0, #944]! @ 0x3b0 │ │ movteq sp, #7804 @ 0x1e7c │ │ - ldc2l 4, cr14, [sp, #740] @ 0x2e4 │ │ + ldc2l 4, cr14, [sp, #920] @ 0x398 │ │ movteq r6, #18756 @ 0x4944 │ │ vcadd.f32 d24, d13, d25, #270 │ │ ldr r0, [pc, #2332] @ 24407b4 │ │ mov r2, #80 @ 0x50 │ │ ldr r5, [pc, #2328] @ 24407b8 │ │ mov r3, #32 │ │ add r0, pc, r0 │ │ @@ -1302520,27 +1302520,27 @@ │ │ bhi 2440554 │ │ ldr r0, [pc, #1976] @ 2440804 │ │ add r0, pc, r0 │ │ str r4, [r0, r1, lsl #2] │ │ ldr r0, [fp, #12] │ │ ldr r4, [r0] │ │ b 2440594 │ │ - ldc2l 14, cr3, [lr, #596] @ 0x254 │ │ + ldc2l 14, cr3, [lr, #776] @ 0x308 │ │ eorseq r8, r1, r8, asr #16 │ │ eorseq r8, r1, r4, asr #16 │ │ movteq sp, #6353 @ 0x18d1 │ │ movteq fp, #19048 @ 0x4a68 │ │ movteq sp, #7608 @ 0x1db8 │ │ movteq fp, #19016 @ 0x4a48 │ │ movteq sp, #7568 @ 0x1d90 │ │ ldc2l 7, cr8, [sp, #616] @ 0x268 │ │ - ldc2l 13, cr3, [lr, #1012] @ 0x3f4 │ │ + ldc2l 14, cr3, [lr, #168] @ 0xa8 │ │ movteq r6, #18564 @ 0x4884 │ │ ldc2l 0, cr12, [pc, #580] @ 24402d4 │ │ - ldc2l 5, cr0, [lr, #532] @ 0x214 │ │ + ldc2l 5, cr0, [lr, #712] @ 0x2c8 │ │ ldr r0, [pc, #1764] @ 244077c │ │ ldr r0, [pc, r0] │ │ cmp r0, #1 │ │ bne 2440358 │ │ ldr r0, [pc, #1752] @ 2440780 │ │ ldr r0, [pc, r0] │ │ cmp r0, #0 │ │ @@ -1302645,24 +1302645,24 @@ │ │ ldr r1, [fp, #-36] @ 0xffffffdc │ │ mov r3, r7 │ │ add r0, pc, r0 │ │ bl 270d9b0 │ │ b 243f878 │ │ movteq r6, #18216 @ 0x4728 │ │ ldc2l 6, cr8, [sp, #52] @ 0x34 │ │ - ldc2l 12, cr3, [lr, #484] @ 0x1e4 │ │ + ldc2l 12, cr3, [lr, #664] @ 0x298 │ │ eorseq r8, r1, r0, lsr r6 │ │ eorseq r8, r1, ip, lsr #12 │ │ movteq sp, #5817 @ 0x16b9 │ │ movteq fp, #18512 @ 0x4850 │ │ movteq sp, #7072 @ 0x1ba0 │ │ movteq sp, #7048 @ 0x1b88 │ │ movteq fp, #18464 @ 0x4820 │ │ movteq sp, #5737 @ 0x1669 │ │ - ldc2l 1, cr14, [sp, #692] @ 0x2b4 │ │ + ldc2l 1, cr14, [sp, #872] @ 0x368 │ │ ldr r4, [pc, #1648] @ 24408f0 │ │ mov r2, #32 │ │ ldr r1, [pc, #1644] @ 24408f4 │ │ mov r3, #12 │ │ add r4, pc, r4 │ │ mov r5, #32 │ │ add r1, pc, r1 │ │ @@ -1302806,39 +1302806,39 @@ │ │ bl 270d9e0 │ │ mov r0, #0 │ │ ldr r1, [fp, #20] │ │ str r0, [r1] │ │ ldr r0, [pc, #1112] @ 2440928 │ │ add r0, pc, r0 │ │ b 243fbf4 │ │ - ldc2l 12, cr3, [lr, #204] @ 0xcc │ │ + ldc2l 12, cr3, [lr, #384] @ 0x180 │ │ ldr r0, [pc, #1280] @ 24409e0 │ │ mov r1, #118 @ 0x76 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #1268] @ 24409e4 │ │ mov r1, r6 │ │ mov r2, #1 │ │ mov r3, r9 │ │ add r0, pc, r0 │ │ b 243fbd8 │ │ movteq sp, #6500 @ 0x1964 │ │ ldc2l 3, cr10, [sp, #704] @ 0x2c0 │ │ stc2l 0, cr15, [r0, #688]! @ 0x2b0 │ │ - ldc2l 2, cr6, [lr, #136] @ 0x88 │ │ + ldc2l 2, cr6, [lr, #316] @ 0x13c │ │ movteq r0, #42372 @ 0xa584 │ │ movteq r6, #17456 @ 0x4430 │ │ eorseq r8, r1, r8, ror #6 │ │ eorseq r8, r1, r4, ror #6 │ │ movteq sp, #6372 @ 0x18e4 │ │ movteq fp, #27996 @ 0x6d5c │ │ movteq fp, #17796 @ 0x4584 │ │ stc2l 1, cr11, [r0, #732]! @ 0x2dc │ │ stc2l 12, cr0, [r1, #640]! @ 0x280 │ │ - ldc2l 1, cr6, [lr, #200] @ 0xc8 │ │ + ldc2l 1, cr6, [lr, #380] @ 0x17c │ │ movteq r0, #42128 @ 0xa490 │ │ eorseq r8, r1, r0, lsl #5 │ │ eorseq r8, r1, ip, ror r2 │ │ movteq sp, #6144 @ 0x1800 │ │ movteq fp, #27764 @ 0x6c74 │ │ movteq sp, #6104 @ 0x17d8 │ │ movteq fp, #17520 @ 0x4470 │ │ @@ -1302992,39 +1302992,39 @@ │ │ ldc2l 15, cr8, [pc, #52] @ 24407dc │ │ stc2l 4, cr14, [r0, #592]! @ 0x250 │ │ movteq fp, #22720 @ 0x58c0 │ │ stc2l 6, cr10, [r0, #60]! @ 0x3c │ │ ldc2l 2, cr7, [sp, #940] @ 0x3ac │ │ movteq ip, #6869 @ 0x1ad5 │ │ movteq fp, #17284 @ 0x4384 │ │ - ldc2l 6, cr11, [lr, #448] @ 0x1c0 │ │ + ldc2l 6, cr11, [lr, #628] @ 0x274 │ │ movteq fp, #17204 @ 0x4334 │ │ stc2l 3, cr0, [r1, #376]! @ 0x178 │ │ ldrsbteq r7, [r1], -r4 │ │ movteq fp, #25552 @ 0x63d0 │ │ movteq fp, #25508 @ 0x63a4 │ │ - ldc2l 6, cr1, [lr, #756] @ 0x2f4 │ │ + ldc2l 6, cr1, [lr, #936] @ 0x3a8 │ │ movteq fp, #25456 @ 0x6370 │ │ movteq r5, #27960 @ 0x6d38 │ │ movteq r6, #22764 @ 0x58ec │ │ movteq fp, #17064 @ 0x42a8 │ │ movteq ip, #7248 @ 0x1c50 │ │ movteq ip, #7216 @ 0x1c30 │ │ ldc2l 0, cr3, [sp, #420] @ 0x1a4 │ │ stc2l 5, cr14, [r0, #848]! @ 0x350 │ │ movteq ip, #7772 @ 0x1e5c │ │ movteq fp, #16916 @ 0x4214 │ │ movteq ip, #7108 @ 0x1bc4 │ │ movteq r5, #18788 @ 0x4964 │ │ - ldc2l 15, cr12, [sp, #432] @ 0x1b0 │ │ + ldc2l 15, cr12, [sp, #612] @ 0x264 │ │ stc2l 0, cr14, [r0, #416]! @ 0x1a0 │ │ movteq r5, #17468 @ 0x443c │ │ movteq ip, #5752 @ 0x1678 │ │ movteq r0, #26068 @ 0x65d4 │ │ - ldc2l 10, cr2, [lr, #336] @ 0x150 @ │ │ + ldc2l 10, cr2, [lr, #516] @ 0x204 @ │ │ stc2l 14, cr13, [r0, #1008]! @ 0x3f0 │ │ movteq r0, #25744 @ 0x6490 │ │ movteq ip, #5388 @ 0x150c │ │ stc2l 7, cr0, [r0, #784]! @ 0x310 │ │ stc2l 14, cr13, [r0, #736]! @ 0x2e0 │ │ movteq pc, #19964 @ 0x4dfc @ │ │ movteq r8, #39444 @ 0x9a14 │ │ @@ -1303032,15 +1303032,15 @@ │ │ movteq pc, #28336 @ 0x6eb0 @ │ │ movteq sl, #19544 @ 0x4c58 │ │ movteq ip, #5624 @ 0x15f8 │ │ ldc2l 10, cr8, [pc, #68] @ 2440898 @ │ │ stc2l 15, cr13, [r0, #608]! @ 0x260 │ │ movteq fp, #21444 @ 0x53c4 │ │ ldc2l 6, cr11, [pc, #516] @ 2440a64 │ │ - ldc2l 14, cr5, [lr, #520] @ 0x208 │ │ + ldc2l 14, cr5, [lr, #700] @ 0x2bc │ │ movteq r0, #41440 @ 0xa1e0 │ │ ldrsbteq r7, [r1], -r0 │ │ eorseq r7, r1, ip, asr #31 │ │ movteq sp, #5456 @ 0x1550 │ │ movteq fp, #27076 @ 0x69c4 │ │ movteq sp, #5412 @ 0x1524 │ │ movteq fp, #16828 @ 0x41bc │ │ @@ -1303071,15 +1303071,15 @@ │ │ movteq fp, #26656 @ 0x6820 │ │ movteq sp, #4392 @ 0x1128 │ │ ldc2l 5, cr3, [sp, #404] @ 0x194 │ │ stc2l 10, cr14, [r0, #832]! @ 0x340 @ │ │ movteq sp, #4948 @ 0x1354 │ │ movteq r5, #18180 @ 0x4704 │ │ ldc2l 5, cr7, [sp, #932] @ 0x3a4 │ │ - ldc2l 12, cr2, [lr, #340] @ 0x154 │ │ + ldc2l 12, cr2, [lr, #520] @ 0x208 │ │ movteq fp, #24624 @ 0x6030 │ │ eorseq r7, r1, r8, lsl #12 │ │ eorseq r7, r1, r4, lsl #12 │ │ movteq ip, #5781 @ 0x1695 │ │ movteq ip, #7040 @ 0x1b80 │ │ movteq ip, #7016 @ 0x1b68 │ │ movteq sl, #18432 @ 0x4800 │ │ @@ -1303090,56 +1303090,56 @@ │ │ ldc2l 12, cr10, [pc, #980] @ 2440d04 │ │ ldc2l 0, cr7, [sp, #316] @ 0x13c │ │ ldc2l 3, cr11, [pc, #692] @ 2440bec │ │ ldc2l 10, cr6, [sp, #396] @ 0x18c @ │ │ stc2l 14, cr15, [r0, #384]! @ 0x180 │ │ movteq r5, #18420 @ 0x47f4 │ │ ldc2l 6, cr7, [sp, #868] @ 0x364 │ │ - ldc2l 13, cr2, [lr, #276] @ 0x114 │ │ + ldc2l 13, cr2, [lr, #456] @ 0x1c8 │ │ movteq fp, #24864 @ 0x6120 │ │ ldrshteq r7, [r1], -r8 │ │ ldrshteq r7, [r1], -r4 │ │ movteq ip, #6021 @ 0x1785 │ │ movteq ip, #7280 @ 0x1c70 │ │ movteq ip, #7256 @ 0x1c58 │ │ movteq sl, #18672 @ 0x48f0 │ │ movteq ip, #5945 @ 0x1739 │ │ ldc2l 10, cr6, [sp, #108] @ 0x6c @ │ │ movteq sl, #28336 @ 0x6eb0 │ │ - ldc2l 3, cr3, [lr, #212] @ 0xd4 │ │ - ldc2l 5, cr3, [lr, #792] @ 0x318 │ │ + ldc2l 3, cr3, [lr, #392] @ 0x188 │ │ + ldc2l 5, cr3, [lr, #972] @ 0x3cc │ │ stc2l 6, cr0, [r1, #892]! @ 0x37c │ │ movteq sp, #4812 @ 0x12cc │ │ ldc2l 13, cr9, [sp, #96] @ 0x60 │ │ stc2l 10, cr14, [r0, #80]! @ 0x50 @ │ │ movteq sp, #4604 @ 0x11fc │ │ ldc2l 12, cr9, [sp, #272] @ 0x110 │ │ stc2l 9, cr14, [r0, #128]! @ 0x80 @ │ │ - ldc2l 9, cr15, [sp, #496] @ 0x1f0 @ │ │ + ldc2l 10, cr15, [sp, #148] @ 0x94 @ │ │ ldc2l 0, cr3, [sp, #176] @ 0xb0 │ │ movteq sp, #4480 @ 0x1180 │ │ movteq r5, #24372 @ 0x5f34 │ │ eorseq r7, r1, r4, ror #23 │ │ movteq sp, #4452 @ 0x1164 │ │ movteq pc, #40388 @ 0x9dc4 @ │ │ movteq pc, #40368 @ 0x9db0 @ │ │ - ldc2l 2, cr9, [lr, #228] @ 0xe4 │ │ + ldc2l 2, cr9, [lr, #408] @ 0x198 │ │ movteq ip, #6876 @ 0x1adc │ │ ldc2l 5, cr9, [sp, #160] @ 0xa0 │ │ stc2l 2, cr14, [r0, #144]! @ 0x90 │ │ movteq r5, #22608 @ 0x5850 │ │ - ldc2l 11, cr2, [lr, #260] @ 0x104 @ │ │ - ldc2l 10, cr5, [lr, #120] @ 0x78 @ │ │ + ldc2l 11, cr2, [lr, #440] @ 0x1b8 @ │ │ + ldc2l 10, cr5, [lr, #300] @ 0x12c @ │ │ movteq pc, #40316 @ 0x9d7c @ │ │ eorseq r7, r1, ip, ror #22 │ │ movteq sp, #4336 @ 0x10f0 │ │ movteq pc, #40248 @ 0x9d38 @ │ │ ldc2l 4, cr7, [sp, #16] │ │ - ldc2l 10, cr2, [lr, #36] @ 0x24 @ │ │ - ldc2l 7, cr11, [lr, #512] @ 0x200 │ │ + ldc2l 10, cr2, [lr, #216] @ 0xd8 @ │ │ + ldc2l 7, cr11, [lr, #692] @ 0x2b4 │ │ ldc2l 4, cr9, [pc, #352] @ 2440b54 │ │ │ │ 024409f0 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ ldr r4, [pc, #64] @ 2440a40 │ │ mov r1, #6 │ │ @@ -1303156,15 +1303156,15 @@ │ │ bl 270da10 │ │ mov r0, r4 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, sl, fp, pc} │ │ ldc2l 7, cr10, [pc, #648] @ 2440cd0 │ │ - ldc2l 10, cr10, [lr, #328] @ 0x148 @ │ │ + ldc2l 10, cr10, [lr, #508] @ 0x1fc @ │ │ stc2l 10, cr9, [r0, #664]! @ 0x298 @ │ │ │ │ 02440a4c : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #24 │ │ mov ip, r1 │ │ @@ -1303312,15 +1303312,15 @@ │ │ mov r3, r4 │ │ bl 270ee00 │ │ mov r0, r8 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - ldc2l 9, cr8, [lr, #472] @ 0x1d8 @ │ │ + ldc2l 10, cr8, [lr, #100] @ 0x64 @ │ │ │ │ 02440c80 : │ │ ldr r1, [r1] │ │ cmp r1, #1 │ │ movlt r0, #0 │ │ bxlt lr │ │ push {r4, r5, r6, r7, fp, lr} │ │ @@ -1303420,17 +1303420,17 @@ │ │ ldr r1, [r8] │ │ sub r9, r1, r0 │ │ str r9, [r8] │ │ b 2440d60 │ │ stc2l 11, cr5, [r0, #472]! @ 0x1d8 @ │ │ vcmla.f16 d29, d16, d8, #270 │ │ ldc2l 3, cr14, [pc, #596] @ 2441074 │ │ - ldc2l 1, cr2, [pc, #36] @ 2440e48 │ │ - ldc2l 7, cr12, [lr, #220] @ 0xdc │ │ - ldc2l 9, cr4, [lr, #418] @ 0x1a2 @ │ │ + ldc2l 1, cr2, [pc, #216] @ 2440efc │ │ + ldc2l 7, cr12, [lr, #400] @ 0x190 │ │ + ldc2l 9, cr4, [lr, #508] @ 0x1fc @ │ │ stc2l 11, cr5, [r0, #120]! @ 0x78 @ │ │ │ │ 02440e2c : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r3 │ │ mov r6, r2 │ │ @@ -1303498,21 +1303498,21 @@ │ │ str r2, [r0], #4 │ │ bcc 2440f24 │ │ ldr r0, [r5] │ │ ldr r1, [r4] │ │ sub r3, r1, r0 │ │ str r3, [r4] │ │ b 2440eb0 │ │ - vcadd.f32 d26, d13, d19, #270 │ │ + ldc2l 8, cr10, [sp, #320] @ 0x140 │ │ stc2l 7, cr13, [r0, #224]! @ 0xe0 │ │ ldc2l 2, cr14, [pc, #276] @ 2441070 │ │ - ldc2l 15, cr1, [pc, #740] @ 2441244 │ │ - ldc2l 5, cr12, [lr, #940] @ 0x3ac │ │ - vcadd.f32 d20, d30, d5, #270 │ │ - ldc2l 7, cr10, [sp, #812] @ 0x32c │ │ + ldc2l 15, cr1, [pc, #920] @ 24412f8 │ │ + ldc2l 6, cr12, [lr, #96] @ 0x60 │ │ + ldc2l 8, cr4, [lr, #712] @ 0x2c8 │ │ + ldc2l 7, cr10, [sp, #992] @ 0x3e0 │ │ │ │ 02440f68 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #12 │ │ mov r4, r3 │ │ mov r6, r2 │ │ @@ -1303567,16 +1303567,16 @@ │ │ ldr r0, [pc, #24] @ 244105c │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 14, cr3, [pc, #600] @ 24412b8 │ │ - ldc2l 13, cr3, [pc, #936] @ 244140c │ │ + ldc2l 14, cr3, [pc, #780] @ 244136c │ │ + ldc2l 14, cr3, [pc, #92] @ 24410c0 │ │ │ │ 02441060 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r4, r1 │ │ mov r5, r0 │ │ @@ -1303933,20 +1303933,20 @@ │ │ ldr r0, [pc, #40] @ 2441604 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 3, cr6, [lr, #64] @ 0x40 │ │ + ldc2l 3, cr6, [lr, #244] @ 0xf4 │ │ ldc2l 4, cr6, [sp, #124] @ 0x7c │ │ - ldc2l 9, cr1, [lr, #346] @ 0x15a @ │ │ + ldc2l 9, cr1, [lr, #436] @ 0x1b4 @ │ │ ldc2l 12, cr9, [pc, #400] @ 2441794 │ │ ldc2l 9, cr5, [sp, #446] @ 0x1be @ │ │ - ldc2l 1, cr6, [lr, #224] @ 0xe0 │ │ + ldc2l 1, cr6, [lr, #404] @ 0x194 │ │ │ │ 02441608 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #156 @ 0x9c │ │ mov r9, r1 │ │ ldr r1, [pc, #584] @ 2441868 │ │ @@ -1304094,29 +1304094,29 @@ │ │ add r0, pc, r0 │ │ str r2, [sp] │ │ add r1, pc, r1 │ │ mov r2, r6 │ │ bl 270e2a0 │ │ b 2441808 │ │ vcadd.f32 d21, d13, d23, #270 │ │ - ldc2l 0, cr6, [lr, #444] @ 0x1bc │ │ + ldc2l 0, cr6, [lr, #624] @ 0x270 │ │ stc2l 14, cr12, [r0, #216]! @ 0xd8 │ │ ldc2l 11, cr9, [pc, #28] @ 2441898 @ │ │ stc2l 0, cr5, [r0, #852]! @ 0x354 │ │ - ldc2l 7, cr3, [pc, #260] @ 2441988 │ │ + ldc2l 7, cr3, [pc, #440] @ 2441a3c │ │ ldc2l 9, cr11, [pc, #462] @ 2441a56 @ │ │ - ldc2l 5, cr5, [pc, #664] @ 2441b24 │ │ + ldc2l 5, cr5, [pc, #844] @ 2441bd8 │ │ stc2l 14, cr12, [r0, #48]! @ 0x30 │ │ - ldc2l 9, cr1, [pc, #496] @ 2441a84 @ │ │ + ldc2l 10, cr1, [pc, #148] @ 2441928 @ │ │ ldc2l 1, cr6, [sp, #576] @ 0x240 │ │ stc2l 4, cr1, [r0, #436]! @ 0x1b4 │ │ ldc2l 9, cr11, [pc, #402] @ 2441a32 @ │ │ stc2l 4, cr1, [r0, #328]! @ 0x148 │ │ - ldc2l 14, cr5, [lr, #924] @ 0x39c │ │ - ldc2l 13, cr13, [lr, #72] @ 0x48 │ │ + ldc2l 15, cr5, [lr, #80] @ 0x50 │ │ + ldc2l 13, cr13, [lr, #252] @ 0xfc │ │ stc2l 4, cr8, [r0, #280]! @ 0x118 │ │ movteq lr, #37508 @ 0x9284 │ │ │ │ 024418b0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #28 │ │ @@ -1304311,20 +1304311,20 @@ │ │ ldr r1, [pc, #68] @ 2441bf8 │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ bl 270e2a0 │ │ mov r0, #0 │ │ str r0, [sp, #12] │ │ b 2441b18 │ │ - ldc2l 12, cr9, [sp, #284] @ 0x11c │ │ + ldc2l 12, cr9, [sp, #464] @ 0x1d0 │ │ ldc2l 15, cr7, [sp, #684] @ 0x2ac │ │ ldc2l 5, cr5, [sp, #396] @ 0x18c │ │ ldc2l 5, cr5, [sp, #60] @ 0x3c │ │ - ldc2l 12, cr7, [lr, #412] @ 0x19c │ │ - ldc2l 12, cr13, [sp, #588] @ 0x24c │ │ + ldc2l 12, cr7, [lr, #592] @ 0x250 │ │ + ldc2l 12, cr13, [sp, #768] @ 0x300 │ │ ldc2l 7, cr11, [pc, #364] @ 2441d54 │ │ eorseq r5, r1, sp, asr lr │ │ stc2l 0, cr1, [r0, #804]! @ 0x324 │ │ ldrsbteq r5, [r1], -ip │ │ eorseq r5, r1, ip, ror sp │ │ stc2l 4, cr0, [r0, #156]! @ 0x9c │ │ movteq sp, #40748 @ 0x9f2c │ │ @@ -1304767,23 +1304767,23 @@ │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ stc2l 10, cr2, [r0, #252]! @ 0xfc @ │ │ - ldc2l 7, cr5, [lr, #188] @ 0xbc │ │ - ldc2l 14, cr0, [lr, #980] @ 0x3d4 │ │ + ldc2l 7, cr5, [lr, #368] @ 0x170 │ │ + ldc2l 15, cr0, [lr, #136] @ 0x88 │ │ stc2l 10, cr10, [r0, #760]! @ 0x2f8 @ │ │ ldc2l 15, cr14, [pc, #188] @ 24423a8 │ │ - ldc2l 15, cr0, [lr, #260] @ 0x104 │ │ - ldc2l 7, cr3, [lr, #692] @ 0x2b4 │ │ + ldc2l 15, cr0, [lr, #440] @ 0x1b8 │ │ + ldc2l 7, cr3, [lr, #872] @ 0x368 │ │ ldc2l 0, cr7, [pc, #76] @ 2442344 │ │ - ldc2l 14, cr0, [lr, #708] @ 0x2c4 │ │ - ldc2l 7, cr3, [lr, #188] @ 0xbc │ │ + ldc2l 14, cr0, [lr, #888] @ 0x378 │ │ + ldc2l 7, cr3, [lr, #368] @ 0x170 │ │ eorseq r5, r1, ip, lsr r9 │ │ ldc2l 11, cr4, [sp, #620] @ 0x26c @ │ │ stc2l 6, cr2, [r0, #812]! @ 0x32c │ │ │ │ 02442308 : │ │ b 270ee90 │ │ │ │ @@ -1304989,21 +1304989,21 @@ │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r8, r9, sl, fp, pc} │ │ stc2l 1, cr12, [r0, #984]! @ 0x3d8 │ │ eorseq r5, r1, r4, ror r5 │ │ mlaseq r1, r8, r5, r5 │ │ - ldc2l 2, cr3, [lr, #464] @ 0x1d0 │ │ + ldc2l 2, cr3, [lr, #644] @ 0x284 │ │ eorseq r5, r1, r4, asr #9 │ │ eorseq r5, r1, ip, ror #8 │ │ - ldc2l 0, cr15, [sp, #520] @ 0x208 │ │ - ldc2l 9, cr0, [lr, #138] @ 0x8a @ │ │ + ldc2l 0, cr15, [sp, #700] @ 0x2bc │ │ + ldc2l 9, cr0, [lr, #228] @ 0xe4 @ │ │ eorseq r5, r1, r8, lsl #8 │ │ - ldc2l 11, cr0, [pc, #232] @ 2442730 @ │ │ + ldc2l 11, cr0, [pc, #412] @ 24427e4 @ │ │ mlaseq r1, ip, r4, r5 │ │ stc2l 15, cr11, [r0, #920]! @ 0x398 │ │ │ │ 0244264c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #28 │ │ @@ -1305509,15 +1305509,15 @@ │ │ add r0, r3, r0, lsl #3 │ │ sub r0, r0, #72 @ 0x48 │ │ bl 270e7f0 │ │ b 2442da8 │ │ ldc2l 5, cr12, [pc, #220] @ 2442f18 │ │ stc2l 8, cr7, [r0, #632]! @ 0x278 │ │ movteq sp, #37968 @ 0x9450 │ │ - ldc2l 14, cr10, [lr, #172] @ 0xac │ │ + ldc2l 14, cr10, [lr, #352] @ 0x160 │ │ movteq sp, #37956 @ 0x9444 │ │ movteq sp, #37956 @ 0x9444 │ │ movteq sp, #37932 @ 0x942c │ │ movteq sp, #37888 @ 0x9400 │ │ movteq sp, #39488 @ 0x9a40 │ │ vcadd.f32 d30, d15, d9, #270 │ │ stc2l 2, cr2, [r0, #184]! @ 0xb8 │ │ @@ -1305563,40 +1305563,40 @@ │ │ movteq sp, #37540 @ 0x92a4 │ │ stc2l 0, cr2, [r0, #952]! @ 0x3b8 │ │ movteq sp, #37472 @ 0x9260 │ │ stc2l 0, cr2, [r0, #680]! @ 0x2a8 │ │ movteq sp, #37888 @ 0x9400 │ │ eorseq r5, r1, r0, lsl ip │ │ movteq sp, #37872 @ 0x93f0 │ │ - vcadd.f32 q13, q7, , #270 │ │ + ldc2l 8, cr10, [lr, #576] @ 0x240 │ │ movteq ip, #40524 @ 0x9e4c │ │ - vcadd.f32 d26, d14, d23, #270 │ │ + ldc2l 8, cr10, [lr, #336] @ 0x150 │ │ ldc2l 5, cr2, [sp, #296] @ 0x128 │ │ - ldc2l 2, cr0, [lr, #36] @ 0x24 │ │ - ldc2l 3, cr0, [pc, #728] @ 244320c │ │ - ldc2l 7, cr10, [lr, #764] @ 0x2fc │ │ + ldc2l 2, cr0, [lr, #216] @ 0xd8 │ │ + ldc2l 3, cr0, [pc, #908] @ 24432c0 │ │ + ldc2l 7, cr10, [lr, #944] @ 0x3b0 │ │ ldc2l 4, cr2, [sp, #904] @ 0x388 │ │ - ldc2l 1, cr0, [lr, #644] @ 0x284 │ │ + ldc2l 1, cr0, [lr, #824] @ 0x338 │ │ movteq sp, #37840 @ 0x93d0 │ │ eorseq r5, r1, r8, ror #10 │ │ movteq ip, #40228 @ 0x9d24 │ │ - ldc2l 11, cr2, [lr, #784] @ 0x310 @ │ │ - ldc2l 2, cr2, [pc, #384] @ 24430d4 │ │ + ldc2l 11, cr2, [lr, #964] @ 0x3c4 @ │ │ + ldc2l 2, cr2, [pc, #564] @ 2443188 │ │ stc2l 12, cr3, [r0, #688]! @ 0x2b0 │ │ movteq ip, #40704 @ 0x9f00 │ │ eorseq r5, r1, r4, asr r5 │ │ eorseq r4, r1, r4, lsl ip │ │ - ldc2l 1, cr4, [pc, #764] @ 2443264 │ │ + ldc2l 1, cr4, [pc, #944] @ 2443318 │ │ ldc2l 3, cr4, [sp, #140] @ 0x8c │ │ ldrhteq r4, [r1], -r0 │ │ - ldc2l 0, cr4, [pc, #332] @ 24430c0 │ │ + ldc2l 0, cr4, [pc, #512] @ 2443174 │ │ stc2l 14, cr1, [r0, #352]! @ 0x160 │ │ - ldc2l 9, cr10, [lr, #316] @ 0x13c @ │ │ - ldc2l 3, cr0, [lr, #564] @ 0x234 │ │ - ldc2l 5, cr0, [pc, #792] @ 244329c │ │ + ldc2l 9, cr10, [lr, #406] @ 0x196 @ │ │ + ldc2l 3, cr0, [lr, #744] @ 0x2e8 │ │ + ldc2l 5, cr0, [pc, #972] @ 2443350 │ │ movteq ip, #40580 @ 0x9e84 │ │ stc2l 13, cr1, [r0, #80]! @ 0x50 │ │ │ │ 02442f88 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ bl 270ce80 │ │ @@ -1305687,18 +1305687,18 @@ │ │ bl 270d9e0 │ │ ldr r0, [pc, #28] @ 24430f4 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2l 12, cr3, [pc, #252] @ 24431ec │ │ + ldc2l 12, cr3, [pc, #432] @ 24432a0 │ │ ldc2l 13, cr3, [sp, #652] @ 0x28c │ │ eorseq r4, r1, r8, asr #18 │ │ - ldc2l 11, cr3, [pc, #924] @ 2443498 @ │ │ + ldc2l 12, cr3, [pc, #80] @ 244314c │ │ │ │ 024430f8 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ @@ -1305733,17 +1305733,17 @@ │ │ ldr r0, [pc, #36] @ 24431a8 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, sl, fp, pc} │ │ stc2l 8, cr1, [r0, #480]! @ 0x1e0 │ │ - ldc2l 3, cr10, [lr, #760] @ 0x2f8 │ │ - ldc2l 13, cr15, [sp, #692] @ 0x2b4 │ │ - ldc2l 15, cr15, [lr, #920] @ 0x398 │ │ + ldc2l 3, cr10, [lr, #940] @ 0x3ac │ │ + ldc2l 13, cr15, [sp, #872] @ 0x368 │ │ + ldc2l 0, cr0, [pc, #76] @ 24431f4 │ │ movteq ip, #39304 @ 0x9988 │ │ stc2l 8, cr1, [r0, #80]! @ 0x50 │ │ │ │ 024431ac : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ vpush {d8-d10} │ │ @@ -1307133,23 +1307133,23 @@ │ │ add r0, pc, r0 │ │ vstr d16, [r0] │ │ b 2444974 │ │ movteq ip, #39484 @ 0x9a3c │ │ movteq sp, #37021 @ 0x909d │ │ stc2l 0, cr3, [r0, #992]! @ 0x3e0 │ │ movteq sp, #37384 @ 0x9208 │ │ - ldc2l 13, cr9, [sp, #56] @ 0x38 │ │ + ldc2l 13, cr9, [sp, #236] @ 0xec │ │ movteq sp, #37845 @ 0x93d5 │ │ stc2l 3, cr9, [r0, #88]! @ 0x58 │ │ movteq sp, #37657 @ 0x9319 │ │ ldc2l 9, cr11, [pc, #180] @ 244481c @ │ │ movteq sp, #37100 @ 0x90ec │ │ - ldc2l 12, cr11, [lr, #636] @ 0x27c │ │ + ldc2l 12, cr11, [lr, #816] @ 0x330 │ │ movteq sp, #37441 @ 0x9241 │ │ - ldc2l 9, cr15, [sp, #290] @ 0x122 @ │ │ + ldc2l 9, cr15, [sp, #380] @ 0x17c @ │ │ movteq ip, #40308 @ 0x9d74 │ │ movteq ip, #39276 @ 0x996c │ │ movteq ip, #40812 @ 0x9f6c │ │ vcmp.f64 d16, #0.0 │ │ vmrs APSR_nzcv, fpscr │ │ ble 24449d4 │ │ vmov.f64 d17, #36 @ 0x41200000 10.0 │ │ @@ -1307438,15 +1307438,15 @@ │ │ movteq ip, #39804 @ 0x9b7c │ │ movteq ip, #39688 @ 0x9b08 │ │ movteq ip, #39696 @ 0x9b10 │ │ movteq ip, #39720 @ 0x9b28 │ │ movteq ip, #37220 @ 0x9164 │ │ movteq ip, #37224 @ 0x9168 │ │ ldc2l 5, cr4, [pc, #848] @ 2444f68 │ │ - ldc2l 14, cr2, [lr, #332] @ 0x14c │ │ + ldc2l 14, cr2, [lr, #512] @ 0x200 │ │ movteq ip, #37040 @ 0x90b0 │ │ eorseq r3, r1, r8, lsl sl │ │ movteq fp, #40592 @ 0x9e90 │ │ movteq ip, #40072 @ 0x9c88 │ │ movteq ip, #39044 @ 0x9884 │ │ movteq ip, #39544 @ 0x9a78 │ │ movteq ip, #39808 @ 0x9b80 │ │ @@ -1307521,15 +1307521,15 @@ │ │ movteq ip, #39292 @ 0x997c │ │ movteq ip, #39736 @ 0x9b38 │ │ movteq ip, #39268 @ 0x9964 │ │ movteq ip, #39264 @ 0x9960 │ │ movteq fp, #40388 @ 0x9dc4 │ │ movteq fp, #40392 @ 0x9dc8 │ │ ldc2l 2, cr4, [pc, #192] @ 2444e24 │ │ - ldc2l 12, cr2, [lr, #892] @ 0x37c │ │ + ldc2l 13, cr2, [lr, #48] @ 0x30 │ │ movteq ip, #37157 @ 0x9125 │ │ movteq ip, #39228 @ 0x993c │ │ movteq ip, #39172 @ 0x9904 │ │ movteq ip, #39140 @ 0x98e4 │ │ movteq ip, #39156 @ 0x98f4 │ │ movteq ip, #39148 @ 0x98ec │ │ movteq ip, #39392 @ 0x99e0 │ │ @@ -1307551,15 +1307551,15 @@ │ │ stc2l 9, cr2, [r0] @ │ │ ldc2l 1, cr11, [pc, #572] @ 2445004 │ │ movteq ip, #38900 @ 0x97f4 │ │ movteq fp, #40176 @ 0x9cf0 │ │ movteq fp, #40160 @ 0x9ce0 │ │ ldc2l 1, cr4, [pc, #336] @ 2444f28 │ │ movteq fp, #40100 @ 0x9ca4 │ │ - ldc2l 11, cr2, [lr, #988] @ 0x3dc @ │ │ + ldc2l 12, cr2, [lr, #144] @ 0x90 │ │ movteq fp, #40861 @ 0x9f9d │ │ movteq ip, #38672 @ 0x9710 │ │ ldc2l 0, cr7, [pc, #812] @ 2445118 │ │ ldc2l 0, cr11, [pc, #492] @ 2444fdc │ │ movteq ip, #38596 @ 0x96c4 │ │ movteq ip, #38608 @ 0x96d0 │ │ movteq ip, #38016 @ 0x9480 │ │ @@ -1307967,51 +1307967,51 @@ │ │ andeq r0, r0, r0, lsl r0 │ │ andeq r0, r0, r6 │ │ andeq r0, r0, r8 │ │ andeq r0, r0, r0, lsr #32 │ │ andeq r0, r0, r0, lsl r0 │ │ andeq r0, r0, r5, lsl r0 │ │ andeq r0, r0, r0, lsl r0 │ │ - ldc2l 5, cr8, [sp, #452] @ 0x1c4 │ │ + ldc2l 5, cr8, [sp, #632] @ 0x278 │ │ movteq fp, #40100 @ 0x9ca4 │ │ eorseq r3, r1, r4, ror #10 │ │ eorseq r3, r1, r0, lsl #14 │ │ eorseq r3, r1, r8, lsl r3 │ │ vcadd.f32 q9, , , #270 │ │ ldc2l 2, cr0, [sp, #244] @ 0xf4 │ │ eorseq r3, r1, r0, lsl #13 │ │ ldc2l 15, cr3, [pc, #884] @ 24457dc │ │ - ldc2l 4, cr0, [lr, #608] @ 0x260 │ │ - ldc2l 0, cr12, [lr, #224] @ 0xe0 │ │ + ldc2l 4, cr0, [lr, #788] @ 0x314 │ │ + ldc2l 0, cr12, [lr, #404] @ 0x194 │ │ ldrshteq r3, [r1], -r8 │ │ - ldc2l 0, cr2, [lr, #872] @ 0x368 │ │ + ldc2l 1, cr2, [lr, #28] │ │ ldc2l 14, cr7, [pc, #304] @ 24455ac │ │ - ldc2l 15, cr11, [lr, #816] @ 0x330 │ │ + ldc2l 15, cr11, [lr, #996] @ 0x3e4 │ │ eorseq r3, r1, r8, lsl #7 │ │ ldc2l 12, cr14, [pc, #536] @ 24456a0 │ │ ldc2l 0, cr8, [pc, #808] @ 24457b4 │ │ ldrshteq r3, [r1], -r4 │ │ ldc2l 12, cr14, [pc, #248] @ 244558c │ │ ldc2l 0, cr8, [pc, #520] @ 24456a0 │ │ - ldc2l 6, cr0, [lr, #196] @ 0xc4 │ │ - ldc2l 11, cr1, [pc, #152] @ 2445538 @ │ │ + ldc2l 6, cr0, [lr, #376] @ 0x178 │ │ + ldc2l 11, cr1, [pc, #332] @ 24455ec @ │ │ ldc2l 11, cr14, [pc, #840] @ 24457ec @ │ │ ldc2l 0, cr8, [pc, #88] @ 2445500 │ │ ldc2l 14, cr3, [pc, #748] @ 2445798 │ │ ldc2l 11, cr14, [pc, #504] @ 24456a8 @ │ │ ldc2l 15, cr7, [pc, #776] @ 24457bc │ │ ldrshteq r3, [r1], -r4 │ │ - ldc2l 15, cr11, [sp, #64] @ 0x40 │ │ - ldc2l 1, cr6, [sp, #280] @ 0x118 │ │ - ldc2l 3, cr6, [sp, #920] @ 0x398 │ │ + ldc2l 15, cr11, [sp, #244] @ 0xf4 │ │ + ldc2l 1, cr6, [sp, #460] @ 0x1cc │ │ + ldc2l 4, cr6, [sp, #76] @ 0x4c │ │ ldc2l 15, cr7, [pc, #232] @ 24455b0 │ │ eorseq r3, r1, ip, ror r2 │ │ - ldc2l 3, cr6, [sp, #680] @ 0x2a8 │ │ + ldc2l 3, cr6, [sp, #860] @ 0x35c │ │ ldc2l 14, cr7, [pc, #1016] @ 24458cc │ │ - ldc2l 1, cr8, [sp, #228] @ 0xe4 │ │ + ldc2l 1, cr8, [sp, #408] @ 0x198 │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ │ │ 024454d8 : │ │ ldr r0, [pc, #64] @ 2445520 │ │ add r0, pc, r0 │ │ vldr d16, [r0] │ │ vcmp.f64 d16, #0.0 │ │ @@ -1308236,19 +1308236,19 @@ │ │ ldr r0, [pc, #36] @ 2445864 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 6, cr1, [pc, #324] @ 24459a0 │ │ - ldc2l 0, cr2, [lr, #500] @ 0x1f4 │ │ + ldc2l 6, cr1, [pc, #504] @ 2445a54 │ │ + ldc2l 0, cr2, [lr, #680] @ 0x2a8 │ │ eorseq r2, r1, r4, lsr pc │ │ eorseq r2, r1, r4, lsr pc │ │ - ldc2l 4, cr1, [pc, #772] @ 2445b70 │ │ + ldc2l 4, cr1, [pc, #952] @ 2445c24 │ │ │ │ 02445868 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #44 @ 0x2c │ │ mov r7, r3 │ │ mov r9, r2 │ │ @@ -1309085,184 +1309085,184 @@ │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 10, cr15, [ip, #360] @ 0x168 @ │ │ movteq fp, #37840 @ 0x93d0 │ │ movteq ip, #37004 @ 0x908c │ │ movteq fp, #37928 @ 0x9428 │ │ - ldc2l 9, cr13, [sp, #48] @ 0x30 @ │ │ - ldc2l 8, cr13, [lr, #460] @ 0x1cc │ │ + ldc2l 9, cr13, [sp, #138] @ 0x8a @ │ │ + vcadd.f32 d29, d30, d16, #270 │ │ movteq fp, #37888 @ 0x9400 │ │ eorseq r2, r1, ip, lsl #28 │ │ movteq fp, #37820 @ 0x93bc │ │ movteq fp, #37772 @ 0x938c │ │ ldrsbteq r2, [r1], -r8 │ │ movteq fp, #38972 @ 0x983c │ │ movteq fp, #37588 @ 0x92d4 │ │ movteq ip, #37012 @ 0x9094 │ │ movteq fp, #38816 @ 0x97a0 │ │ movteq fp, #37572 @ 0x92c4 │ │ - ldc2l 13, cr15, [sp, #960] @ 0x3c0 │ │ - ldc2l 7, cr13, [lr, #476] @ 0x1dc │ │ + ldc2l 14, cr15, [sp, #116] @ 0x74 │ │ + ldc2l 7, cr13, [lr, #656] @ 0x290 │ │ movteq fp, #37516 @ 0x928c │ │ - ldc2l 7, cr13, [sp, #896] @ 0x380 │ │ - ldc2l 7, cr13, [lr, #236] @ 0xec │ │ + vcadd.f32 d29, d13, d13, #270 │ │ + ldc2l 7, cr13, [lr, #416] @ 0x1a0 │ │ movteq fp, #38660 @ 0x9704 │ │ movteq fp, #37424 @ 0x9230 │ │ movteq fp, #38640 @ 0x96f0 │ │ movteq fp, #37332 @ 0x91d4 │ │ stc2l 11, cr8, [r0, #180]! @ 0xb4 @ │ │ - ldc2l 6, cr13, [lr, #572] @ 0x23c │ │ + ldc2l 6, cr13, [lr, #752] @ 0x2f0 │ │ movteq fp, #37284 @ 0x91a4 │ │ movteq fp, #38623 @ 0x96df │ │ - ldc2l 11, cr9, [sp, #748] @ 0x2ec @ │ │ - ldc2l 6, cr13, [lr, #332] @ 0x14c │ │ + ldc2l 11, cr9, [sp, #928] @ 0x3a0 @ │ │ + ldc2l 6, cr13, [lr, #512] @ 0x200 │ │ eorseq r2, r1, ip, lsr #24 │ │ movteq fp, #37328 @ 0x91d0 │ │ movteq fp, #38296 @ 0x9598 │ │ movteq fp, #38276 @ 0x9584 │ │ movteq fp, #37160 @ 0x9128 │ │ stc2l 10, cr8, [r0, #516]! @ 0x204 @ │ │ - ldc2l 5, cr13, [lr, #908] @ 0x38c │ │ + ldc2l 6, cr13, [lr, #64] @ 0x40 │ │ movteq fp, #37112 @ 0x90f8 │ │ ldc2l 6, cr7, [pc, #264] @ 244672c │ │ - ldc2l 5, cr13, [lr, #700] @ 0x2bc │ │ + ldc2l 5, cr13, [lr, #880] @ 0x370 │ │ eorseq r2, r1, r4, lsl #23 │ │ movteq fp, #37164 @ 0x912c │ │ movteq fp, #37040 @ 0x90b0 │ │ ldc2l 6, cr15, [ip, #952] @ 0x3b8 │ │ movteq fp, #38476 @ 0x964c │ │ movteq fp, #37352 @ 0x91e8 │ │ movteq fp, #36968 @ 0x9068 │ │ movteq fp, #36936 @ 0x9048 │ │ - ldc2l 11, cr15, [sp, #528] @ 0x210 @ │ │ - ldc2l 5, cr13, [lr, #44] @ 0x2c │ │ + ldc2l 11, cr15, [sp, #708] @ 0x2c4 @ │ │ + ldc2l 5, cr13, [lr, #224] @ 0xe0 │ │ ldc2l 1, cr1, [sp, #892] @ 0x37c │ │ movteq fp, #36864 @ 0x9000 │ │ - ldc2l 11, cr15, [sp, #192] @ 0xc0 @ │ │ - ldc2l 4, cr13, [lr, #732] @ 0x2dc │ │ + ldc2l 11, cr15, [sp, #372] @ 0x174 @ │ │ + ldc2l 4, cr13, [lr, #912] @ 0x390 │ │ movteq fp, #38020 @ 0x9484 │ │ movteq sl, #40888 @ 0x9fb8 │ │ - ldc2l 10, cr15, [sp, #944] @ 0x3b0 @ │ │ - ldc2l 4, cr13, [lr, #460] @ 0x1cc │ │ + ldc2l 11, cr15, [sp, #100] @ 0x64 @ │ │ + ldc2l 4, cr13, [lr, #640] @ 0x280 │ │ movteq sl, #40828 @ 0x9f7c │ │ - ldc2l 10, cr15, [sp, #696] @ 0x2b8 @ │ │ - ldc2l 4, cr13, [lr, #188] @ 0xbc │ │ + ldc2l 10, cr15, [sp, #876] @ 0x36c @ │ │ + ldc2l 4, cr13, [lr, #368] @ 0x170 │ │ movteq sl, #40748 @ 0x9f2c │ │ movteq fp, #37880 @ 0x93f8 │ │ movteq sl, #40736 @ 0x9f20 │ │ stc2l 8, cr8, [r0, #484]! @ 0x1e4 │ │ - ldc2l 3, cr13, [lr, #876] @ 0x36c │ │ + ldc2l 4, cr13, [lr, #32] │ │ movteq fp, #37927 @ 0x9427 │ │ movteq sl, #40660 @ 0x9ed4 │ │ vcmla.f16 d24, d0, d25, #270 │ │ - ldc2l 3, cr13, [lr, #556] @ 0x22c │ │ - ldc2l 8, cr9, [sp, #868] @ 0x364 │ │ + ldc2l 3, cr13, [lr, #736] @ 0x2e0 │ │ + ldc2l 9, cr9, [sp, #12] @ │ │ movteq fp, #40120 @ 0x9cb8 │ │ eorseq r2, r1, r8, lsr r9 │ │ movteq sl, #40548 @ 0x9e64 │ │ stc2l 7, cr8, [r0, #756]! @ 0x2f4 │ │ - ldc2l 3, cr13, [lr, #124] @ 0x7c │ │ + ldc2l 3, cr13, [lr, #304] @ 0x130 │ │ movteq sl, #40500 @ 0x9e34 │ │ - ldc2l 9, cr15, [sp, #192] @ 0xc0 @ │ │ - ldc2l 2, cr13, [lr, #924] @ 0x39c │ │ + ldc2l 9, cr15, [sp, #282] @ 0x11a @ │ │ + ldc2l 3, cr13, [lr, #80] @ 0x50 │ │ eorseq r2, r1, r4, asr #17 │ │ movteq sl, #40408 @ 0x9dd8 │ │ stc2l 7, cr8, [r0, #196]! @ 0xc4 │ │ - ldc2l 2, cr13, [lr, #588] @ 0x24c │ │ + ldc2l 2, cr13, [lr, #768] @ 0x300 │ │ movteq sl, #40360 @ 0x9da8 │ │ stc2l 6, cr8, [r0, #996]! @ 0x3e4 │ │ - ldc2l 2, cr13, [lr, #364] @ 0x16c │ │ + ldc2l 2, cr13, [lr, #544] @ 0x220 │ │ movteq sl, #40276 @ 0x9d54 │ │ stc2l 6, cr8, [r0, #676]! @ 0x2a4 │ │ - ldc2l 2, cr13, [lr, #44] @ 0x2c │ │ + ldc2l 2, cr13, [lr, #224] @ 0xe0 │ │ stc2l 9, cr0, [r0, #310]! @ 0x136 @ │ │ movteq fp, #39736 @ 0x9b38 │ │ movteq sl, #40188 @ 0x9cfc │ │ stc2l 6, cr8, [r0, #324]! @ 0x144 │ │ - ldc2l 1, cr13, [lr, #716] @ 0x2cc │ │ + ldc2l 1, cr13, [lr, #896] @ 0x380 │ │ stc2l 11, cr6, [r0, #424]! @ 0x1a8 @ │ │ movteq fp, #39648 @ 0x9ae0 │ │ movteq sl, #40100 @ 0x9ca4 │ │ - ldc2l 7, cr15, [sp, #864] @ 0x360 │ │ - ldc2l 1, cr13, [lr, #380] @ 0x17c │ │ + vcadd.f32 d31, d13, d5, #270 │ │ + ldc2l 1, cr13, [lr, #560] @ 0x230 │ │ movteq sl, #40052 @ 0x9c74 │ │ stc2l 5, cr8, [r0, #772]! @ 0x304 │ │ - ldc2l 1, cr13, [lr, #140] @ 0x8c │ │ + ldc2l 1, cr13, [lr, #320] @ 0x140 │ │ eorseq r2, r1, r0, lsl #14 │ │ movteq sl, #39960 @ 0x9c18 │ │ - ldc2l 7, cr15, [sp, #288] @ 0x120 │ │ - ldc2l 0, cr13, [lr, #828] @ 0x33c │ │ + ldc2l 7, cr15, [sp, #468] @ 0x1d4 │ │ + ldc2l 0, cr13, [lr, #1008] @ 0x3f0 │ │ movteq fp, #37020 @ 0x909c │ │ movteq sl, #39884 @ 0x9bcc │ │ stc2l 5, cr8, [r0, #148]! @ 0x94 │ │ - ldc2l 0, cr13, [lr, #540] @ 0x21c │ │ + ldc2l 0, cr13, [lr, #720] @ 0x2d0 │ │ movteq sl, #39836 @ 0x9b9c │ │ - ldc2l 5, cr9, [sp, #732] @ 0x2dc │ │ - ldc2l 0, cr13, [lr, #316] @ 0x13c │ │ + ldc2l 5, cr9, [sp, #912] @ 0x390 │ │ + ldc2l 0, cr13, [lr, #496] @ 0x1f0 │ │ eorseq r2, r1, r8, lsr #12 │ │ movteq sl, #39884 @ 0x9bcc │ │ movteq sl, #40852 @ 0x9f94 │ │ movteq sl, #40836 @ 0x9f84 │ │ movteq sl, #39720 @ 0x9b28 │ │ stc2l 4, cr8, [r0, #516]! @ 0x204 │ │ - ldc2l 15, cr12, [lr, #908] @ 0x38c │ │ + ldc2l 0, cr13, [lr, #64] @ 0x40 │ │ movteq sl, #39672 @ 0x9af8 │ │ ldc2l 0, cr7, [pc, #264] @ 2446878 │ │ - ldc2l 15, cr12, [lr, #700] @ 0x2bc │ │ + ldc2l 15, cr12, [lr, #880] @ 0x370 │ │ eorseq r2, r1, r8, lsl #11 │ │ movteq sl, #39728 @ 0x9b30 │ │ movteq sl, #39604 @ 0x9ab4 │ │ movteq sl, #39548 @ 0x9a7c │ │ ldc2l 0, cr15, [ip, #952] @ 0x3b8 │ │ movteq sl, #39520 @ 0x9a60 │ │ movteq sl, #40600 @ 0x9e98 │ │ movteq fp, #38912 @ 0x9800 │ │ movteq sl, #39488 @ 0x9a40 │ │ - ldc2l 5, cr15, [sp, #488] @ 0x1e8 │ │ - ldc2l 14, cr12, [lr, #1004] @ 0x3ec │ │ + ldc2l 5, cr15, [sp, #668] @ 0x29c │ │ + ldc2l 15, cr12, [lr, #160] @ 0xa0 │ │ movteq sl, #39432 @ 0x9a08 │ │ - ldc2l 4, cr15, [sp, #1016] @ 0x3f8 │ │ - ldc2l 14, cr12, [lr, #508] @ 0x1fc │ │ + ldc2l 5, cr15, [sp, #172] @ 0xac │ │ + ldc2l 14, cr12, [lr, #688] @ 0x2b0 │ │ movteq sl, #39296 @ 0x9980 │ │ - ldc2l 3, cr9, [sp, #652] @ 0x28c │ │ - ldc2l 14, cr12, [lr, #236] @ 0xec │ │ - ldc2l 3, cr9, [sp, #1020] @ 0x3fc │ │ - ldc2l 14, cr12, [lr, #604] @ 0x25c │ │ + ldc2l 3, cr9, [sp, #832] @ 0x340 │ │ + ldc2l 14, cr12, [lr, #416] @ 0x1a0 │ │ + ldc2l 4, cr9, [sp, #176] @ 0xb0 │ │ + ldc2l 14, cr12, [lr, #784] @ 0x310 │ │ movteq sl, #40344 @ 0x9d98 │ │ movteq sl, #40320 @ 0x9d80 │ │ movteq sl, #39212 @ 0x992c │ │ - ldc2l 4, cr15, [sp, #408] @ 0x198 │ │ - ldc2l 13, cr12, [lr, #924] @ 0x39c │ │ + ldc2l 4, cr15, [sp, #588] @ 0x24c │ │ + ldc2l 14, cr12, [lr, #80] @ 0x50 │ │ movteq sl, #39156 @ 0x98f4 │ │ - ldc2l 3, cr15, [sp, #936] @ 0x3a8 │ │ - ldc2l 13, cr12, [lr, #428] @ 0x1ac │ │ + ldc2l 4, cr15, [sp, #92] @ 0x5c │ │ + ldc2l 13, cr12, [lr, #608] @ 0x260 │ │ movteq sl, #39044 @ 0x9884 │ │ ldc2l 13, cr6, [pc, #824] @ 2446b20 │ │ - ldc2l 13, cr12, [lr, #236] @ 0xec │ │ + ldc2l 13, cr12, [lr, #416] @ 0x1a0 │ │ movteq sl, #38984 @ 0x9848 │ │ ldc2l 14, cr6, [pc, #184] @ 24468ac │ │ - ldc2l 13, cr12, [lr, #620] @ 0x26c │ │ + ldc2l 13, cr12, [lr, #800] @ 0x320 │ │ movteq sl, #39088 @ 0x98b0 │ │ movteq sl, #40284 @ 0x9d5c │ │ - ldc2l 14, cr4, [lr, #496] @ 0x1f0 │ │ + ldc2l 14, cr4, [lr, #676] @ 0x2a4 │ │ movteq sl, #38808 @ 0x9798 │ │ ldc2l 12, cr6, [pc, #920] @ 2446ba4 │ │ - ldc2l 12, cr12, [lr, #332] @ 0x14c │ │ + ldc2l 12, cr12, [lr, #512] @ 0x200 │ │ movteq sl, #38764 @ 0x976c │ │ movteq sl, #40248 @ 0x9d38 │ │ - ldc2l 2, cr1, [lr, #836] @ 0x344 │ │ + ldc2l 2, cr1, [lr, #1016] @ 0x3f8 │ │ movteq sl, #38748 @ 0x975c │ │ - ldc2l 1, cr9, [sp, #508] @ 0x1fc │ │ - ldc2l 12, cr12, [lr, #92] @ 0x5c │ │ + ldc2l 1, cr9, [sp, #688] @ 0x2b0 │ │ + ldc2l 12, cr12, [lr, #272] @ 0x110 │ │ movteq sl, #39796 @ 0x9b74 │ │ ldc2l 13, cr14, [ip, #584] @ 0x248 │ │ ldc2l 4, cr3, [sp, #208] @ 0xd0 │ │ - ldc2l 10, cr12, [sp, #260] @ 0x104 @ │ │ - ldc2l 0, cr9, [lr, #204] @ 0xcc │ │ + ldc2l 10, cr12, [sp, #440] @ 0x1b8 @ │ │ + ldc2l 0, cr9, [lr, #384] @ 0x180 │ │ ldc2l 14, cr14, [ip, #88] @ 0x58 │ │ │ │ 0244683c : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ ldr r7, [r0] │ │ cmp r7, #1 │ │ @@ -1309635,15 +1309635,15 @@ │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 5, cr2, [pc, #192] @ 2446ec0 │ │ eorseq r1, r1, r0, asr #23 │ │ eorseq r1, r1, r0, asr #23 │ │ ldc2l 14, cr11, [pc, #212] @ 2446ee0 │ │ - ldc2l 1, cr12, [sp, #308] @ 0x134 │ │ + ldc2l 1, cr12, [sp, #488] @ 0x1e8 │ │ stc2l 5, cr9, [r0, #252]! @ 0xfc │ │ ldc2l 2, cr2, [pc, #784] @ 2447128 │ │ │ │ 02446e14 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ @@ -1309861,26 +1309861,26 @@ │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #40 @ 0x28 │ │ vpop {d8} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 9, cr14, [sp, #276] @ 0x114 @ │ │ + ldc2l 9, cr14, [sp, #366] @ 0x16e @ │ │ ldrshteq r1, [r1], -r8 │ │ ldrshteq r1, [r1], -r4 │ │ - ldc2l 6, cr6, [lr, #448] @ 0x1c0 │ │ - ldc2l 0, cr12, [sp, #52] @ 0x34 │ │ - ldc2l 7, cr10, [sp, #936] @ 0x3a8 │ │ + ldc2l 6, cr6, [lr, #628] @ 0x274 │ │ + ldc2l 0, cr12, [sp, #232] @ 0xe8 │ │ + ldc2l 8, cr10, [sp, #92] @ 0x5c │ │ ldc2l 11, cr5, [pc, #320] @ 24472e8 @ │ │ ldc2l 15, cr11, [ip, #668] @ 0x29c │ │ ldc2l 10, cr5, [pc, #944] @ 2447560 @ │ │ ldc2l 15, cr11, [ip, #268] @ 0x10c │ │ - ldc2l 6, cr14, [sp, #440] @ 0x1b8 │ │ - ldc2l 7, cr4, [sp, #868] @ 0x364 │ │ + ldc2l 6, cr14, [sp, #620] @ 0x26c │ │ + vcadd.f32 d20, d13, d6, #270 │ │ ldc2l 10, cr0, [sp, #864] @ 0x360 @ │ │ │ │ 024471bc : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #44 @ 0x2c │ │ mov r7, r3 │ │ @@ -1310009,23 +1310009,23 @@ │ │ sub r0, r1, r0 │ │ mov r1, r4 │ │ add r0, r0, #1 │ │ str r0, [fp, #-32] @ 0xffffffe0 │ │ sub r0, fp, #32 │ │ bl 270d1a0 │ │ b 24472fc │ │ - ldc2l 5, cr14, [sp, #528] @ 0x210 │ │ + ldc2l 5, cr14, [sp, #708] @ 0x2c4 │ │ ldc2l 15, cr3, [pc, #484] @ 24475c0 │ │ - ldc2l 12, cr11, [sp, #516] @ 0x204 │ │ + ldc2l 12, cr11, [sp, #696] @ 0x2b8 │ │ ldc2l 15, cr3, [pc, #484] @ 24475c8 │ │ - ldc2l 5, cr14, [sp, #880] @ 0x370 │ │ - ldc2l 4, cr4, [sp, #692] @ 0x2b4 │ │ - ldc2l 12, cr11, [sp, #868] @ 0x364 │ │ + ldc2l 6, cr14, [sp, #36] @ 0x24 │ │ + ldc2l 4, cr4, [sp, #872] @ 0x368 │ │ + ldc2l 13, cr11, [sp, #24] │ │ ldc2l 15, cr5, [pc, #652] @ 2447680 │ │ - ldc2l 5, cr14, [sp, #256] @ 0x100 │ │ + ldc2l 5, cr14, [sp, #436] @ 0x1b4 │ │ │ │ 024473f4 : │ │ ldr r1, [r1] │ │ mov r3, r0 │ │ mov r0, #0 │ │ cmp r1, #1 │ │ blt 2447474 │ │ @@ -1310976,70 +1310976,70 @@ │ │ mov r0, #1 │ │ str r5, [ip] │ │ vstr d11, [r3] │ │ str r0, [r2] │ │ vstr d16, [r6] │ │ vstr d17, [r1] │ │ b 2447810 │ │ - ldc2l 12, cr9, [lr, #164] @ 0xa4 │ │ + ldc2l 12, cr9, [lr, #344] @ 0x158 │ │ eorseq r1, r1, r4, lsr #32 │ │ eorseq r1, r1, r4, lsr #32 │ │ vcadd.f32 , , q5, #270 │ │ vcadd.f32 , , , #270 │ │ - ldc2l 5, cr15, [lr] │ │ + ldc2l 5, cr15, [lr, #180] @ 0xb4 │ │ ldc2l 1, cr13, [pc, #976] @ 24486b4 │ │ ldc2l 9, cr7, [pc, #50] @ 244831a @ │ │ ldc2l 1, cr13, [pc, #532] @ 2448500 │ │ - ldc2l 8, cr11, [sp, #876] @ 0x36c │ │ - ldc2l 5, cr11, [sp, #788] @ 0x314 │ │ - ldc2l 10, cr9, [lr, #172] @ 0xac @ │ │ - ldc2l 11, cr3, [lr, #924] @ 0x39c @ │ │ + ldc2l 9, cr11, [sp, #16] @ │ │ + ldc2l 5, cr11, [sp, #968] @ 0x3c8 │ │ + ldc2l 10, cr9, [lr, #352] @ 0x160 @ │ │ + ldc2l 12, cr3, [lr, #80] @ 0x50 │ │ stc2l 12, cr10, [r0, #576]! @ 0x240 │ │ ldc2l 15, cr14, [pc, #980] @ 24486d8 │ │ - ldc2l 5, cr11, [sp, #468] @ 0x1d4 │ │ - ldc2l 11, cr3, [lr, #716] @ 0x2cc @ │ │ - ldc2l 5, cr11, [sp, #4] │ │ - ldc2l 11, cr5, [lr, #448] @ 0x1c0 @ │ │ - ldc2l 13, cr7, [sp, #340] @ 0x154 │ │ - ldc2l 4, cr13, [lr, #316] @ 0x13c │ │ - ldc2l 12, cr9, [sp, #268] @ 0x10c │ │ + ldc2l 5, cr11, [sp, #648] @ 0x288 │ │ + ldc2l 11, cr3, [lr, #896] @ 0x380 @ │ │ + ldc2l 5, cr11, [sp, #184] @ 0xb8 │ │ + ldc2l 11, cr5, [lr, #628] @ 0x274 @ │ │ + ldc2l 13, cr7, [sp, #520] @ 0x208 │ │ + ldc2l 4, cr13, [lr, #496] @ 0x1f0 │ │ + ldc2l 12, cr9, [sp, #448] @ 0x1c0 │ │ ldc2l 7, cr3, [pc, #348] @ 2448480 │ │ - ldc2l 10, cr9, [sp, #1020] @ 0x3fc @ │ │ + ldc2l 11, cr9, [sp, #176] @ 0xb0 @ │ │ ldc2l 6, cr3, [pc, #76] @ 2448378 │ │ - ldc2l 10, cr9, [sp, #700] @ 0x2bc @ │ │ + ldc2l 10, cr9, [sp, #880] @ 0x370 @ │ │ ldc2l 5, cr3, [pc, #780] @ 2448640 │ │ - ldc2l 10, cr9, [sp, #428] @ 0x1ac @ │ │ + ldc2l 10, cr9, [sp, #608] @ 0x260 @ │ │ ldc2l 5, cr3, [pc, #508] @ 2448538 │ │ - ldc2l 9, cr9, [sp, #390] @ 0x186 @ │ │ + ldc2l 9, cr9, [sp, #480] @ 0x1e0 @ │ │ ldc2l 4, cr3, [pc, #860] @ 24486a0 │ │ - ldc2l 9, cr9, [sp, #302] @ 0x12e @ │ │ + ldc2l 9, cr9, [sp, #392] @ 0x188 @ │ │ ldc2l 4, cr3, [pc, #684] @ 24485f8 │ │ movteq r9, #40240 @ 0x9d30 │ │ eorseq r0, r1, r8, asr #19 │ │ eorseq r0, r1, r0, asr #19 │ │ ldrhteq r0, [r1], -r8 │ │ mlaseq r1, r0, r7, r0 │ │ eorseq r0, r1, ip, ror r7 │ │ - ldc2l 7, cr3, [lr, #588] @ 0x24c │ │ + ldc2l 7, cr3, [lr, #768] @ 0x300 │ │ ldc2l 3, cr3, [pc, #796] @ 2448688 │ │ - ldc2l 6, cr3, [lr, #460] @ 0x1cc │ │ + ldc2l 6, cr3, [lr, #640] @ 0x280 │ │ ldc2l 2, cr3, [pc, #668] @ 2448610 │ │ - ldc2l 5, cr3, [lr, #796] @ 0x31c │ │ + ldc2l 5, cr3, [lr, #976] @ 0x3d0 │ │ ldc2l 1, cr3, [pc, #1004] @ 2448768 │ │ - ldc2l 5, cr3, [lr, #540] @ 0x21c │ │ + ldc2l 5, cr3, [lr, #720] @ 0x2d0 │ │ ldc2l 1, cr3, [pc, #748] @ 2448670 │ │ - ldc2l 4, cr9, [sp, #860] @ 0x35c │ │ + ldc2l 5, cr9, [sp, #16] │ │ ldc2l 15, cr2, [pc, #940] @ 2448738 │ │ movteq r9, #39000 @ 0x9858 │ │ ldrshteq r0, [r1], -ip │ │ ldrshteq r0, [r1], -r4 │ │ ldrshteq r0, [r1], -r8 │ │ ldrshteq r0, [r1], -r4 │ │ ldrsbteq r0, [r1], -r8 │ │ - ldc2l 11, cr9, [lr, #340] @ 0x154 @ │ │ + ldc2l 11, cr9, [lr, #520] @ 0x208 @ │ │ │ │ 024483a4 : │ │ vldr d17, [r2] │ │ vldr d18, [r1] │ │ vldr d16, [r0] │ │ vcmp.f64 d18, d17 │ │ vmrs APSR_nzcv, fpscr │ │ @@ -1311771,55 +1311771,55 @@ │ │ mov r0, #0 │ │ sub sp, fp, #64 @ 0x40 │ │ vpop {d8-d11} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ add r0, sp, #2944 @ 0xb80 │ │ b 244894c │ │ - ldc2l 2, cr15, [sp, #600] @ 0x258 │ │ - ldc2l 6, cr10, [sp, #732] @ 0x2dc │ │ - ldc2l 3, cr10, [sp, #644] @ 0x284 │ │ - vcadd.f32 d24, d14, d7, #270 │ │ + ldc2l 2, cr15, [sp, #780] @ 0x30c │ │ + ldc2l 6, cr10, [sp, #912] @ 0x390 │ │ + ldc2l 3, cr10, [sp, #824] @ 0x338 │ │ + ldc2l 8, cr8, [lr, #208] @ 0xd0 │ │ eorseq r0, r1, r8, lsr #2 │ │ eorseq r0, r1, r8, lsl #2 │ │ eorseq r0, r1, ip, ror #1 │ │ - ldc2l 6, cr10, [sp, #732] @ 0x2dc │ │ - ldc2l 3, cr10, [sp, #404] @ 0x194 │ │ - ldc2l 11, cr12, [sp, #684] @ 0x2ac @ │ │ + ldc2l 6, cr10, [sp, #912] @ 0x390 │ │ + ldc2l 3, cr10, [sp, #584] @ 0x248 │ │ + ldc2l 11, cr12, [sp, #864] @ 0x360 @ │ │ eorseq r0, r1, r0, lsl #4 │ │ - ldc2l 12, cr10, [sp, #64] @ 0x40 │ │ + ldc2l 12, cr10, [sp, #244] @ 0xf4 │ │ ldc2l 4, cr10, [pc, #340] @ 244909c │ │ - ldc2l 11, cr10, [sp, #912] @ 0x390 @ │ │ + ldc2l 12, cr10, [sp, #68] @ 0x44 │ │ ldc2l 4, cr10, [pc, #164] @ 2448ff4 │ │ eorseq pc, r0, r0, lsr #31 │ │ ldc2l 14, cr14, [ip, #592] @ 0x250 │ │ - ldc2l 3, cr10, [sp, #836] @ 0x344 │ │ - ldc2l 9, cr4, [sp, #472] @ 0x1d8 @ │ │ + ldc2l 3, cr10, [sp, #1016] @ 0x3f8 │ │ + ldc2l 10, cr4, [sp, #100] @ 0x64 @ │ │ eorseq pc, r0, r8, ror pc @ │ │ eorseq pc, r0, r0, ror r9 @ │ │ - ldc2l 10, cr10, [sp, #688] @ 0x2b0 @ │ │ + ldc2l 10, cr10, [sp, #868] @ 0x364 @ │ │ ldc2l 2, cr10, [pc, #964] @ 2449334 │ │ eorseq pc, r0, r4, ror #28 │ │ ldc2l 2, cr10, [pc, #20] @ 2448f8c │ │ ldc2l 15, cr13, [pc, #236] @ 2449068 │ │ ldc2l 15, cr13, [pc, #44] @ 2448fac │ │ - ldc2l 8, cr10, [sp, #1008] @ 0x3f0 │ │ + ldc2l 9, cr10, [sp, #82] @ 0x52 @ │ │ ldc2l 1, cr10, [pc, #260] @ 244908c │ │ - ldc2l 8, cr10, [sp, #864] @ 0x360 │ │ + ldc2l 9, cr10, [sp, #10] @ │ │ ldc2l 1, cr10, [pc, #116] @ 2449004 │ │ mlaseq r0, r4, ip, pc @ │ │ eorseq pc, r0, r8, lsr fp @ │ │ ldc2l 14, cr9, [pc, #916] @ 2449330 │ │ ldc2l 12, cr13, [pc, #108] @ 244900c │ │ ldc2l 11, cr13, [pc, #940] @ 2449350 @ │ │ - ldc2l 9, cr2, [sp, #56] @ 0x38 @ │ │ + ldc2l 9, cr2, [sp, #146] @ 0x92 @ │ │ ldc2l 14, cr9, [pc, #132] @ 2449030 │ │ - ldc2l 8, cr2, [sp, #992] @ 0x3e0 │ │ + ldc2l 9, cr2, [sp, #74] @ 0x4a @ │ │ ldc2l 13, cr9, [pc, #1012] @ 24493a8 │ │ - ldc2l 8, cr14, [sp, #456] @ 0x1c8 │ │ + ldc2l 8, cr14, [sp, #636] @ 0x27c │ │ │ │ 02448fb4 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d15} │ │ sub sp, sp, #64 @ 0x40 │ │ @@ -1312227,31 +1312227,31 @@ │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #96 @ 0x60 │ │ vpop {d8-d15} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 6, cr14, [sp, #960] @ 0x3c0 │ │ + ldc2l 7, cr14, [sp, #116] @ 0x74 │ │ stc2l 10, cr3, [r0, #764]! @ 0x2fc @ │ │ stc2l 2, cr7, [r0, #492]! @ 0x1ec │ │ stc2l 10, cr3, [r0, #556]! @ 0x22c @ │ │ stc2l 2, cr7, [r0, #1004]! @ 0x3ec │ │ stc2l 11, cr3, [r0, #44]! @ 0x2c @ │ │ ldc2l 8, cr14, [ip, #116] @ 0x74 │ │ stc2l 9, cr3, [r0, #238]! @ 0xee @ │ │ ldc2l 7, cr14, [ip, #900] @ 0x384 │ │ stc2l 9, cr3, [r0, #118]! @ 0x76 @ │ │ stc2l 13, cr6, [r0, #800]! @ 0x320 │ │ ldc2l 4, cr11, [pc, #460] @ 2449828 │ │ - ldc2l 9, cr9, [sp, #274] @ 0x112 @ │ │ + ldc2l 9, cr9, [sp, #364] @ 0x16c @ │ │ ldc2l 4, cr14, [ip, #36] @ 0x24 │ │ stc2l 5, cr3, [r0, #396]! @ 0x18c │ │ - ldc2l 9, cr9, [sp, #42] @ 0x2a @ │ │ - ldc2l 15, cr3, [sp, #176] @ 0xb0 │ │ + ldc2l 9, cr9, [sp, #132] @ 0x84 @ │ │ + ldc2l 15, cr3, [sp, #356] @ 0x164 │ │ stc2l 13, cr6, [r0, #80]! @ 0x50 │ │ ldc2l 7, cr14, [ip, #644] @ 0x284 │ │ stc2l 8, cr3, [r0, #1004]! @ 0x3ec │ │ ldc2l 7, cr14, [ip, #276] @ 0x114 │ │ stc2l 8, cr3, [r0, #636]! @ 0x27c │ │ stc2l 0, cr7, [r0, #188]! @ 0xbc │ │ stc2l 8, cr3, [r0, #252]! @ 0xfc │ │ @@ -1312266,16 +1312266,16 @@ │ │ stc2l 6, cr3, [r0, #844]! @ 0x34c │ │ stc2l 14, cr6, [r0, #268]! @ 0x10c │ │ stc2l 6, cr3, [r0, #332]! @ 0x14c │ │ stc2l 13, cr6, [r0, #1020]! @ 0x3fc │ │ stc2l 6, cr3, [r0, #60]! @ 0x3c │ │ stc2l 14, cr6, [r0, #640]! @ 0x280 │ │ ldc2l 10, cr7, [pc, #588] @ 2449914 @ │ │ - ldc2l 10, cr9, [sp, #372] @ 0x174 @ │ │ - ldc2l 15, cr11, [sp, #636] @ 0x27c │ │ + ldc2l 10, cr9, [sp, #552] @ 0x228 @ │ │ + ldc2l 15, cr11, [sp, #816] @ 0x330 │ │ │ │ 024496cc : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ vpush {d8} │ │ sub sp, sp, #8 │ │ mov r9, r3 │ │ @@ -1312414,22 +1312414,22 @@ │ │ vld1.64 {d16-d17}, [r6]! │ │ subs r3, r3, #2 │ │ vst1.64 {d16-d17}, [r7]! │ │ bne 24498f0 │ │ cmp lr, r1 │ │ bne 244971c │ │ b 2449744 │ │ - ldc2l 6, cr11, [lr, #380] @ 0x17c │ │ + ldc2l 6, cr11, [lr, #560] @ 0x230 │ │ ldc2l 1, cr11, [pc, #492] @ 2449b04 │ │ - ldc2l 6, cr9, [sp, #580] @ 0x244 │ │ - ldc2l 12, cr3, [sp, #448] @ 0x1c0 │ │ - ldc2l 7, cr11, [lr, #300] @ 0x12c │ │ + ldc2l 6, cr9, [sp, #760] @ 0x2f8 │ │ + ldc2l 12, cr3, [sp, #628] @ 0x274 │ │ + ldc2l 7, cr11, [lr, #480] @ 0x1e0 │ │ ldc2l 7, cr7, [pc, #716] @ 2449bf4 │ │ - ldc2l 7, cr9, [sp, #500] @ 0x1f4 │ │ - ldc2l 12, cr11, [sp, #764] @ 0x2fc │ │ + ldc2l 7, cr9, [sp, #680] @ 0x2a8 │ │ + ldc2l 12, cr11, [sp, #944] @ 0x3b0 │ │ │ │ 0244992c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d15} │ │ sub sp, sp, #56 @ 0x38 │ │ @@ -1313267,35 +1313267,35 @@ │ │ mov r0, #0 │ │ sub sp, fp, #96 @ 0x60 │ │ vpop {d8-d15} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 10, cr12, [pc, #984] @ 244aa30 @ │ │ ldc2l 0, cr7, [pc, #492] @ 244a848 │ │ - ldc2l 0, cr9, [sp, #276] @ 0x114 │ │ - ldc2l 5, cr11, [sp, #540] @ 0x21c │ │ + ldc2l 0, cr9, [sp, #456] @ 0x1c8 │ │ + ldc2l 5, cr11, [sp, #720] @ 0x2d0 │ │ stc2l 14, cr0, [r0, #64]! @ 0x40 │ │ stc2l 9, cr6, [r0, #246]! @ 0xf6 @ │ │ - ldc2l 13, cr13, [sp, #480] @ 0x1e0 │ │ + ldc2l 13, cr13, [sp, #660] @ 0x294 │ │ vcmla.f16 q11, q8, , #270 │ │ ldc2l 15, cr13, [ip, #164] @ 0xa4 │ │ stc2l 12, cr0, [r0, #1008]! @ 0x3f0 │ │ ldc2l 14, cr13, [ip, #964] @ 0x3c4 │ │ stc2l 12, cr0, [r0, #784]! @ 0x310 │ │ ldc2l 14, cr13, [ip, #772] @ 0x304 │ │ stc2l 12, cr0, [r0, #592]! @ 0x250 │ │ ldc2l 14, cr13, [ip, #580] @ 0x244 │ │ stc2l 12, cr0, [r0, #400]! @ 0x190 │ │ ldc2l 10, cr12, [pc, #600] @ 244a8f0 @ │ │ ldc2l 10, cr10, [pc, #844] @ 244a9e8 @ │ │ - ldc2l 15, cr8, [sp, #932] @ 0x3a4 │ │ + ldc2l 0, cr9, [sp, #88] @ 0x58 │ │ ldc2l 10, cr13, [ip, #452] @ 0x1c4 @ │ │ vcmla.f16 q8, q0, q2, #270 │ │ - vcadd.f32 q12, , , #270 │ │ - ldc2l 15, cr2, [sp, #16] │ │ + ldc2l 9, cr8, [sp, #52] @ 0x34 @ │ │ + ldc2l 15, cr2, [sp, #196] @ 0xc4 │ │ ldc2l 3, cr12, [pc, #360] @ 244a81c │ │ stc2l 12, cr0, [r0, #16]! │ │ stc2l 11, cr0, [r0, #800]! @ 0x320 @ │ │ stc2l 11, cr0, [r0, #448]! @ 0x1c0 @ │ │ stc2l 11, cr0, [r0, #128]! @ 0x80 @ │ │ stc2l 10, cr0, [r0, #896]! @ 0x380 @ │ │ stc2l 10, cr0, [r0, #640]! @ 0x280 @ │ │ @@ -1313324,15 +1313324,15 @@ │ │ stc2l 5, cr0, [r0, #176]! @ 0xb0 │ │ ldc2l 7, cr13, [ip, #164] @ 0xa4 │ │ stc2l 4, cr0, [r0, #1008]! @ 0x3f0 │ │ ldc2l 6, cr13, [ip, #996] @ 0x3e4 │ │ stc2l 4, cr0, [r0, #816]! @ 0x330 │ │ ldc2l 3, cr12, [pc, #1000] @ 244ab24 │ │ ldc2l 4, cr10, [pc, #204] @ 244a80c │ │ - ldc2l 9, cr8, [sp, #146] @ 0x92 @ │ │ + ldc2l 9, cr8, [sp, #236] @ 0xec @ │ │ ldc2l 3, cr13, [ip, #900] @ 0x384 │ │ stc2l 1, cr0, [r0, #720]! @ 0x2d0 │ │ stc2l 15, cr5, [r0, #860]! @ 0x35c │ │ stc2l 4, cr0, [r0, #384]! @ 0x180 │ │ stc2l 15, cr5, [r0, #636]! @ 0x27c │ │ stc2l 4, cr0, [r0, #160]! @ 0xa0 │ │ stc2l 15, cr5, [r0, #396]! @ 0x18c │ │ @@ -1314122,21 +1314122,21 @@ │ │ mov r1, r5 │ │ bl 270e100 │ │ vldr d16, [r8] │ │ mov r0, #1 │ │ str r0, [r9] │ │ vstr d16, [r4, #128] @ 0x80 │ │ b 244aa0c │ │ - ldc2l 4, cr12, [lr, #220] @ 0xdc │ │ + ldc2l 4, cr12, [lr, #400] @ 0x190 │ │ eorseq sp, r0, ip, asr #29 │ │ eorseq sp, r0, r8, asr #29 │ │ ldc2l 2, cr8, [pc, #768] @ 244b6b0 │ │ - ldc2l 5, cr8, [sp, #660] @ 0x294 │ │ - ldc2l 13, cr6, [sp, #520] @ 0x208 │ │ - ldc2l 12, cr0, [sp, #996] @ 0x3e4 │ │ + ldc2l 5, cr8, [sp, #840] @ 0x348 │ │ + ldc2l 13, cr6, [sp, #700] @ 0x2bc │ │ + ldc2l 13, cr0, [sp, #152] @ 0x98 │ │ ldc2l 15, cr12, [ip, #992] @ 0x3e0 │ │ ldc2l 0, cr2, [pc, #144] @ 244b454 │ │ ldc2l 14, cr9, [pc, #28] @ 244b3e4 │ │ ldc2l 11, cr1, [pc, #544] @ 244b5ec @ │ │ ldc2l 9, cr9, [pc, #214] @ 244b4a6 @ │ │ ldc2l 11, cr1, [pc, #304] @ 244b504 @ │ │ ldc2l 9, cr9, [pc, #94] @ 244b436 @ │ │ @@ -1314159,15 +1314159,15 @@ │ │ ldc2l 10, cr1, [pc, #32] @ 244b43c @ │ │ ldc2l 7, cr9, [pc, #940] @ 244b7cc │ │ eorseq sp, r0, ip, lsl #11 │ │ eorseq sp, r0, r8, lsl #11 │ │ movteq r6, #39048 @ 0x9888 │ │ eorseq sp, r0, r0, lsl #11 │ │ eorseq sp, r0, r4, asr r5 │ │ - ldc2l 3, cr12, [lr, #28] │ │ + ldc2l 3, cr12, [lr, #208] @ 0xd0 │ │ │ │ 0244b434 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d10} │ │ sub sp, sp, #464 @ 0x1d0 │ │ @@ -1314554,17 +1314554,17 @@ │ │ vneg.f64 d19, d20 │ │ vstr d19, [r4] │ │ vstr d17, [r4, #8] │ │ vstr d18, [r4, #16] │ │ vstr d16, [r4, #24] │ │ pop {r4, r5, fp, pc} │ │ ldrshteq ip, [r0], -r0 │ │ - vcadd.f32 d23, d30, d31, #270 │ │ - ldc2l 5, cr9, [lr, #920] @ 0x398 │ │ - ldc2l 15, cr9, [sp, #136] @ 0x88 │ │ + ldc2l 8, cr7, [lr, #880] @ 0x370 │ │ + ldc2l 6, cr9, [lr, #76] @ 0x4c │ │ + ldc2l 15, cr9, [sp, #316] @ 0x13c │ │ │ │ 0244ba48 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ vpush {d8-d10} │ │ sub sp, sp, #152 @ 0x98 │ │ mov r4, r2 │ │ @@ -1314690,22 +1314690,22 @@ │ │ vcmp.f64 d8, d16 │ │ vmrs APSR_nzcv, fpscr │ │ movweq r6, #1 │ │ and r0, r7, r6 │ │ sub sp, fp, #48 @ 0x30 │ │ vpop {d8-d10} │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - ldc2l 6, cr7, [lr, #924] @ 0x39c │ │ - vcadd.f32 , q15, , #270 │ │ - ldc2l 4, cr7, [sp, #324] @ 0x144 │ │ + ldc2l 7, cr7, [lr, #80] @ 0x50 │ │ + ldc2l 9, cr5, [lr, #40] @ 0x28 @ │ │ + ldc2l 4, cr7, [sp, #504] @ 0x1f8 │ │ ldc2l 14, cr8, [pc, #404] @ 244bdfc │ │ - ldc2l 6, cr7, [lr, #396] @ 0x18c │ │ - ldc2l 10, cr1, [lr, #784] @ 0x310 @ │ │ - ldc2l 4, cr7, [sp, #132] @ 0x84 │ │ - ldc2l 5, cr7, [lr, #236] @ 0xec │ │ + ldc2l 6, cr7, [lr, #576] @ 0x240 │ │ + ldc2l 10, cr1, [lr, #964] @ 0x3c4 @ │ │ + ldc2l 4, cr7, [sp, #312] @ 0x138 │ │ + ldc2l 5, cr7, [lr, #416] @ 0x1a0 │ │ │ │ 0244bc74 : │ │ vldr d16, [r0, #64] @ 0x40 │ │ vldmia r0, {d17-d24} │ │ vmul.f64 d25, d21, d16 │ │ vmul.f64 d16, d18, d16 │ │ vmls.f64 d25, d22, d24 │ │ @@ -1315022,17 +1315022,17 @@ │ │ bl 270f110 │ │ vmov.f64 d8, d9 │ │ b 244c03c │ │ stc2l 5, cr4, [r0, #688]! @ 0x2b0 │ │ eorseq ip, r0, r4, asr sl │ │ eorseq ip, r0, r0, asr sl │ │ stc2l 4, cr4, [r0, #168]! @ 0xa8 │ │ - ldc2l 15, cr6, [sp, #932] @ 0x3a4 │ │ - ldc2l 7, cr5, [sp, #792] @ 0x318 │ │ - ldc2l 7, cr15, [ip, #356] @ 0x164 │ │ + ldc2l 0, cr7, [sp, #88] @ 0x58 │ │ + ldc2l 7, cr5, [sp, #972] @ 0x3cc │ │ + ldc2l 7, cr15, [ip, #536] @ 0x218 │ │ ldc2l 10, cr11, [ip, #352] @ 0x160 @ │ │ mlaseq r0, r8, r7, ip │ │ mlaseq r0, ip, r7, ip │ │ stc2l 3, cr4, [r0, #832]! @ 0x340 │ │ │ │ 0244c188 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ @@ -1315088,15 +1315088,15 @@ │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ ldc2l 7, cr13, [ip, #676] @ 0x2a4 │ │ eorseq ip, r0, r4, lsr r6 │ │ eorseq ip, r0, r0, lsr r6 │ │ ldc2l 0, cr15, [lr, #56] @ 0x38 │ │ - ldc2l 12, cr6, [sp, #868] @ 0x364 │ │ + ldc2l 13, cr6, [sp, #24] │ │ ldc2l 7, cr11, [ip, #668] @ 0x29c │ │ eorseq ip, r0, ip, lsl #12 │ │ ldc2l 7, cr13, [ip, #84] @ 0x54 │ │ │ │ 0244c27c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -1315597,17 +1315597,17 @@ │ │ add r0, r7, r0, lsl #3 │ │ add r5, r5, #1 │ │ vldr d16, [r0] │ │ b 244c948 │ │ stc2l 0, cr2, [r0, #704]! @ 0x2c0 │ │ eorseq ip, r0, ip, lsr #5 │ │ eorseq ip, r0, r8, lsr #5 │ │ - ldc2l 13, cr4, [lr, #84] @ 0x54 │ │ - ldc2l 8, cr6, [sp, #340] @ 0x154 │ │ - ldc2l 0, cr5, [sp, #200] @ 0xc8 │ │ + ldc2l 13, cr4, [lr, #264] @ 0x108 │ │ + vcadd.f32 d22, d29, d2, #270 │ │ + ldc2l 0, cr5, [sp, #380] @ 0x17c │ │ ldc2l 3, cr0, [pc, #784] @ 244cd6c │ │ ldc2l 9, cr2, [pc, #178] @ 244cb12 @ │ │ ldc2l 2, cr0, [pc, #880] @ 244cdd4 │ │ ldc2l 8, cr2, [pc, #452] @ 244cc2c │ │ ldc2l 3, cr0, [pc, #512] @ 244cc6c │ │ ldc2l 9, cr2, [pc, #42] @ 244ca9a @ │ │ ldc2l 2, cr0, [pc, #64] @ 244cab4 │ │ @@ -1315677,17 +1315677,17 @@ │ │ mov r1, #5 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #32 │ │ vpop {d8} │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ - ldc2l 12, cr14, [ip, #264] @ 0x108 │ │ + ldc2l 12, cr14, [ip, #444] @ 0x1bc │ │ eorseq fp, r0, r0, asr #26 │ │ - ldc2l 11, cr14, [ip, #600] @ 0x258 @ │ │ + ldc2l 11, cr14, [ip, #780] @ 0x30c @ │ │ │ │ 0244cb8c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8} │ │ sub sp, sp, #1016 @ 0x3f8 │ │ @@ -1316657,15 +1316657,15 @@ │ │ ldr r1, [fp, #16] │ │ mov r0, #1 │ │ str r0, [r1] │ │ ldr r1, [pc, #260] @ 244dbc4 │ │ add r1, pc, r1 │ │ strb r0, [r1] │ │ b 244cd84 │ │ - ldc2l 11, cr14, [ip, #240] @ 0xf0 @ │ │ + ldc2l 11, cr14, [ip, #420] @ 0x1a4 @ │ │ movteq r4, #40688 @ 0x9ef0 │ │ movteq r4, #40672 @ 0x9ee0 │ │ eorseq fp, r0, r4, lsr ip │ │ eorseq fp, r0, r4, lsr ip │ │ ldc2l 4, cr2, [pc, #944] @ 244de94 │ │ ldc2l 12, cr10, [ip, #848] @ 0x350 │ │ ldc2l 13, cr7, [pc, #128] @ 244db6c │ │ @@ -1316676,41 +1316676,41 @@ │ │ eorseq fp, r0, r4, asr #20 │ │ movteq r4, #40188 @ 0x9cfc │ │ eorseq fp, r0, r4, ror #20 │ │ movteq r4, #40152 @ 0x9cd8 │ │ eorseq fp, r0, r8, lsl sl │ │ ldc2l 13, cr11, [pc, #408] @ 244dcac │ │ ldc2l 3, cr2, [pc, #100] @ 244db7c │ │ - ldc2l 15, cr9, [lr, #224] @ 0xe0 │ │ + ldc2l 15, cr9, [lr, #404] @ 0x194 │ │ eorseq fp, r0, ip, asr #15 │ │ ldrsbteq fp, [r0], -r0 │ │ eorseq fp, r0, r8, asr #15 │ │ mlaseq r0, r8, r7, fp │ │ mlaseq r0, ip, r7, fp │ │ eorseq fp, r0, ip, ror r7 │ │ eorseq fp, r0, ip, ror r7 │ │ eorseq fp, r0, r4, ror r7 │ │ ldc2l 12, cr15, [lr, #992] @ 0x3e0 │ │ ldc2l 1, cr6, [ip, #344] @ 0x158 │ │ ldc2l 12, cr5, [pc, #32] @ 244db68 │ │ - ldc2l 11, cr5, [sp, #548] @ 0x224 @ │ │ + ldc2l 11, cr5, [sp, #728] @ 0x2d8 @ │ │ ldc2l 13, cr1, [pc, #348] @ 244dcac │ │ ldc2l 9, cr15, [lr, #384] @ 0x180 @ │ │ ldc2l 14, cr5, [ip, #120] @ 0x78 │ │ ldc2l 4, cr13, [pc, #380] @ 244dcd8 │ │ vcadd.f32 d19, d15, d17, #270 │ │ - ldc2l 7, cr5, [sp, #772] @ 0x304 │ │ + ldc2l 7, cr5, [sp, #952] @ 0x3b8 │ │ stc2l 11, cr2, [r0, #1000]! @ 0x3e8 @ │ │ stc2l 13, cr4, [r0, #560]! @ 0x230 │ │ stc2l 14, cr4, [r0, #32]! │ │ ldc2l 15, cr12, [pc, #904] @ 244defc │ │ - ldc2l 7, cr5, [sp, #20] │ │ - ldc2l 11, cr5, [sp, #984] @ 0x3d8 @ │ │ - ldc2l 7, cr5, [sp, #164] @ 0xa4 │ │ - ldc2l 13, cr15, [sp, #256] @ 0x100 │ │ + ldc2l 7, cr5, [sp, #200] @ 0xc8 │ │ + ldc2l 12, cr5, [sp, #140] @ 0x8c │ │ + ldc2l 7, cr5, [sp, #344] @ 0x158 │ │ + ldc2l 13, cr15, [sp, #436] @ 0x1b4 │ │ eorseq sl, r0, ip, asr #31 │ │ movteq r4, #37456 @ 0x9250 │ │ movteq r4, #37436 @ 0x923c │ │ eorseq sl, r0, r4, lsl #31 │ │ eorseq sl, r0, r0, ror pc │ │ eorseq sl, r0, r0, ror #30 │ │ eorseq sl, r0, r4, ror pc │ │ @@ -1316721,15 +1316721,15 @@ │ │ eorseq sl, r0, r0, asr #30 │ │ eorseq sl, r0, r0, lsl #30 │ │ eorseq sl, r0, r0, lsl #30 │ │ eorseq sl, r0, r4, lsl #30 │ │ ldc2l 10, cr15, [lr, #768] @ 0x300 @ │ │ ldc2l 15, cr5, [ip, #120] @ 0x78 │ │ movteq r4, #36892 @ 0x901c │ │ - ldc2l 9, cr14, [ip, #240] @ 0xf0 @ │ │ + ldc2l 9, cr14, [ip, #330] @ 0x14a @ │ │ │ │ 0244dbcc : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ mov r4, r3 │ │ mov r5, r2 │ │ @@ -1316929,26 +1316929,26 @@ │ │ mov r0, #0 │ │ sub sp, fp, #72 @ 0x48 │ │ vpop {d8-d12} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ stc2l 5, cr11, [r8, #272]! @ 0x110 │ │ ldc2l 10, cr12, [pc, #624] @ 244e16c @ │ │ - ldc2l 9, cr3, [sp, #228] @ 0xe4 @ │ │ - ldc2l 7, cr15, [sp, #1016] @ 0x3f8 │ │ + ldc2l 9, cr3, [sp, #318] @ 0x13e @ │ │ + vcadd.f32 d31, d13, d27, #270 │ │ ldc2l 10, cr12, [pc, #224] @ 244dfe8 @ │ │ - ldc2l 9, cr3, [sp, #28] @ │ │ + ldc2l 9, cr3, [sp, #118] @ 0x76 @ │ │ ldc2l 10, cr12, [pc] @ 244df10 @ │ │ - ldc2l 8, cr3, [sp, #856] @ 0x358 │ │ - ldc2l 7, cr15, [sp, #312] @ 0x138 │ │ - ldc2l 8, cr3, [sp, #616] @ 0x268 │ │ + ldc2l 9, cr3, [sp, #6] @ │ │ + ldc2l 7, cr15, [sp, #492] @ 0x1ec │ │ + vcadd.f32 , , , #270 │ │ ldc2l 9, cr12, [pc, #296] @ 244e048 @ │ │ ldc2l 11, cr12, [pc, #176] @ 244dfd4 @ │ │ - ldc2l 10, cr3, [sp, #8] @ │ │ - vcadd.f32 d31, d29, d2, #270 │ │ + ldc2l 10, cr3, [sp, #188] @ 0xbc @ │ │ + vcadd.f32 d31, d29, d31, #270 │ │ mlaseq r0, r4, r9, sl │ │ │ │ 0244df2c : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ ldr r4, [pc, #144] @ 244dfcc │ │ ldr r4, [pc, r4] │ │ @@ -1318137,29 +1318137,29 @@ │ │ eoreq ip, lr, ip, asr #28 │ │ strdeq ip, [lr], -r4 @ │ │ eoreq ip, lr, r0, ror #27 │ │ eoreq ip, lr, ip, asr #27 │ │ eoreq ip, lr, r4, lsl #27 │ │ ldrdeq ip, [lr], -r8 @ │ │ ldc2l 14, cr11, [pc, #312] @ 244f2d4 │ │ - ldc2l 12, cr6, [sp, #376] @ 0x178 │ │ + ldc2l 12, cr6, [sp, #556] @ 0x22c │ │ eoreq r9, lr, r4, lsl #4 │ │ strdeq ip, [lr], -ip @ │ │ ldrdeq ip, [lr], -r4 @ │ │ eoreq ip, lr, r8, ror sl │ │ eoreq ip, lr, r4, lsr #19 │ │ eoreq ip, lr, r8, ror r9 │ │ eoreq ip, lr, r0, lsr sl │ │ strhteq ip, [lr], -r4 │ │ strhteq ip, [lr], -ip │ │ strhteq ip, [lr], -r8 │ │ eoreq ip, lr, ip, ror #14 │ │ eoreq ip, lr, r8, lsl #10 │ │ strhteq ip, [lr], -ip │ │ - ldc2l 4, cr12, [sp, #696] @ 0x2b8 │ │ + ldc2l 4, cr12, [sp, #876] @ 0x36c │ │ mlaeq lr, r4, r3, ip │ │ movteq r3, #37664 @ 0x9320 │ │ mlaeq lr, ip, fp, ip │ │ eoreq ip, lr, r4, ror r4 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #84 @ 0x54 │ │ @@ -1319096,19 +1319096,19 @@ │ │ cmp r1, #0 │ │ cmpne r1, #32 │ │ beq 244fb08 │ │ cmp r1, #95 @ 0x5f │ │ movne r0, #32 │ │ strbne r1, [fp, #-33] @ 0xffffffdf │ │ b 244fb08 │ │ - ldc2l 3, cr5, [lr, #428] @ 0x1ac │ │ + ldc2l 3, cr5, [lr, #608] @ 0x260 │ │ eoreq r8, lr, r0, asr r2 │ │ - ldc2l 10, cr11, [sp, #108] @ 0x6c @ │ │ - ldc2l 10, cr0, [sp, #580] @ 0x244 @ │ │ - vcadd.f32 , , , #270 │ │ + ldc2l 10, cr11, [sp, #288] @ 0x120 @ │ │ + ldc2l 10, cr0, [sp, #760] @ 0x2f8 @ │ │ + ldc2l 8, cr3, [sp, #616] @ 0x268 │ │ │ │ 02450068 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ ldr r7, [r1] │ │ mov r4, #0 │ │ cmp r7, #1 │ │ @@ -1319312,17 +1319312,17 @@ │ │ mov r0, #0 │ │ mov r1, r4 │ │ bl 270cf50 │ │ cmp r5, #0 │ │ moveq r0, #1 │ │ streq r0, [r4, #16] │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 14, cr2, [lr, #340] @ 0x154 │ │ + ldc2l 14, cr2, [lr, #520] @ 0x208 │ │ ldc2l 5, cr10, [pc, #44] @ 24503cc │ │ - ldc2l 11, cr2, [sp, #804] @ 0x324 @ │ │ + ldc2l 11, cr2, [sp, #984] @ 0x3d8 @ │ │ ldc2l 6, cr8, [pc, #988] @ 2450784 │ │ │ │ 024503a4 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r5, r2 │ │ @@ -1319368,16 +1319368,16 @@ │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldc2l 6, cr7, [ip, #152] @ 0x98 │ │ - ldc2l 2, cr11, [sp, #88] @ 0x58 │ │ - ldc2l 10, cr2, [sp, #820] @ 0x334 @ │ │ + ldc2l 2, cr11, [sp, #268] @ 0x10c │ │ + ldc2l 10, cr2, [sp, #1000] @ 0x3e8 @ │ │ ldc2l 6, cr8, [pc, #28] @ 2450498 │ │ ldc2l 5, cr7, [ip, #648] @ 0x288 │ │ │ │ 0245047c : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r5, r1 │ │ @@ -1319414,19 +1319414,19 @@ │ │ str r0, [r5, #20] │ │ ldr r0, [pc, #32] @ 245052c │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, fp, pc} │ │ - ldc2l 10, cr4, [lr, #668] @ 0x29c @ │ │ - ldc2l 1, cr11, [sp, #408] @ 0x198 │ │ - ldc2l 10, cr2, [sp, #116] @ 0x74 @ │ │ + ldc2l 10, cr4, [lr, #848] @ 0x350 @ │ │ + ldc2l 1, cr11, [sp, #588] @ 0x24c │ │ + ldc2l 10, cr2, [sp, #296] @ 0x128 @ │ │ ldc2l 5, cr8, [pc, #348] @ 245068c │ │ - ldc2l 10, cr4, [lr, #268] @ 0x10c @ │ │ + ldc2l 10, cr4, [lr, #448] @ 0x1c0 @ │ │ │ │ 02450530 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r5, r2 │ │ mov r6, r1 │ │ @@ -1319469,16 +1319469,16 @@ │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldc2l 4, cr6, [pc, #212] @ 24506c4 │ │ ldc2l 13, cr15, [pc, #912] @ 2450984 │ │ - ldc2l 9, cr2, [sp, #170] @ 0xaa @ │ │ - ldc2l 13, cr0, [lr, #700] @ 0x2bc │ │ + ldc2l 9, cr2, [sp, #260] @ 0x104 @ │ │ + ldc2l 13, cr0, [lr, #880] @ 0x370 │ │ ldc2l 3, cr6, [pc, #756] @ 24508f4 │ │ │ │ 024505fc : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d10} │ │ @@ -1320605,15 +1320605,15 @@ │ │ sub r1, r6, #1 │ │ cmp r1, #10 │ │ bcs 24516e8 │ │ mov r0, r1 │ │ b 2451704 │ │ movteq r1, #38712 @ 0x9738 │ │ ldc2l 9, cr8, [lr, #120] @ 0x78 @ │ │ - ldc2l 9, cr2, [lr, #402] @ 0x192 @ │ │ + ldc2l 9, cr2, [lr, #492] @ 0x1ec @ │ │ movteq r1, #37880 @ 0x93f8 │ │ ldr r6, [pc, #3912] @ 2452700 │ │ ldr r6, [pc, r6] │ │ ldr r1, [pc, #3908] @ 2452704 │ │ mov r0, #1 │ │ cmp r6, #1 │ │ str r6, [fp, #-60] @ 0xffffffc4 │ │ @@ -1320654,16 +1320654,16 @@ │ │ movteq r1, #38436 @ 0x9624 │ │ eorseq r8, r0, r4, asr #1 │ │ cmneq r0, #200, 18 @ 0x320000 │ │ cmneq r0, #36, 24 @ 0x2400 │ │ cmneq r0, #116, 12 @ 0x7400000 │ │ cmneq r0, #8, 16 @ 0x80000 │ │ movteq r1, #37580 @ 0x92cc │ │ - vcadd.f32 q9, q7, , #270 │ │ - ldc2l 13, cr0, [sp, #740] @ 0x2e4 │ │ + ldc2l 8, cr2, [lr, #600] @ 0x258 │ │ + ldc2l 13, cr0, [sp, #920] @ 0x398 │ │ movteq r1, #37500 @ 0x927c │ │ cmneq r0, #240, 10 @ 0x3c000000 │ │ cmneq r0, #128, 14 @ 0x2000000 │ │ cmneq r0, #32, 18 @ 0x80000 │ │ vmov d16, r6, r9 │ │ ldr r3, [fp, #-60] @ 0xffffffc4 │ │ vcvt.s32.f64 s0, d16 │ │ @@ -1320751,15 +1320751,15 @@ │ │ movteq r1, #38056 @ 0x94a8 │ │ eorseq r7, r0, r8, asr #30 │ │ cmneq r0, #76, 16 @ 0x4c0000 │ │ cmneq r0, #168, 20 @ 0xa8000 │ │ cmneq r0, #248, 8 @ 0xf8000000 │ │ cmneq r0, #140, 12 @ 0x8c00000 │ │ movteq r1, #37196 @ 0x914c │ │ - ldc2l 12, cr0, [sp, #356] @ 0x164 │ │ + ldc2l 12, cr0, [sp, #536] @ 0x218 │ │ ldr r6, [pc, #3940] @ 2452960 │ │ ldr r6, [pc, r6] │ │ ldr r8, [sp, #72] @ 0x48 │ │ ldr sl, [pc, #3932] @ 2452964 │ │ add sl, pc, sl │ │ ldr r0, [pc, #3928] @ 2452968 │ │ ldr r1, [pc, #3928] @ 245296c │ │ @@ -1320898,15 +1320898,15 @@ │ │ strb r1, [r2] │ │ mov r1, #16 │ │ bl 270da00 │ │ b 2452378 │ │ ldc2l 0, cr2, [pc, #112] @ 2451ca8 │ │ ldc2l 13, cr5, [pc, #268] @ 2451d48 │ │ vcadd.f32 , , q9, #270 │ │ - ldc2l 10, cr0, [sp, #504] @ 0x1f8 @ │ │ + ldc2l 10, cr0, [sp, #684] @ 0x2ac @ │ │ movteq r0, #40776 @ 0x9f48 │ │ cmneq r0, #188, 4 @ 0xc000000b │ │ cmneq r0, #76, 8 @ 0x4c000000 │ │ cmneq r0, #236, 10 @ 0x3b000000 │ │ ldrsbteq r7, [r0], -ip │ │ ldrsbteq r7, [r0], -ip │ │ movteq r0, #40720 @ 0x9f10 │ │ @@ -1320987,15 +1320987,15 @@ │ │ eorseq r7, r0, r8, lsl ip │ │ cmneq r0, #24, 10 @ 0x6000000 │ │ cmneq r0, #120, 14 @ 0x1e00000 │ │ cmneq r0, #200, 2 @ 0x32 │ │ cmneq r0, #88, 6 @ 0x60000001 │ │ movteq r1, #37156 @ 0x9124 │ │ movteq r1, #37124 @ 0x9104 │ │ - ldc2l 9, cr0, [sp, #44] @ 0x2c @ │ │ + ldc2l 9, cr0, [sp, #134] @ 0x86 @ │ │ ldc2l 13, cr11, [pc, #296] @ 2451ed4 │ │ movteq r0, #40388 @ 0x9dc4 │ │ cmneq r0, #56, 2 │ │ cmneq r0, #200, 4 @ 0x8000000c │ │ cmneq r0, #104, 8 @ 0x68000000 │ │ eorseq r7, r0, r8, asr fp │ │ eorseq r7, r0, r8, asr fp │ │ @@ -1321008,15 +1321008,15 @@ │ │ cmneq r0, #80, 4 │ │ cmneq r0, #240, 6 @ 0xc0000003 │ │ eorseq r7, r0, r0, ror #21 │ │ eorseq r7, r0, r0, ror #21 │ │ movteq r0, #40212 @ 0x9d14 │ │ cmneq r0, #84, 10 @ 0x15000000 │ │ ldc2l 11, cr3, [pc, #108] @ 2451e64 @ │ │ - ldc2l 15, cr1, [sp, #884] @ 0x374 │ │ + ldc2l 0, cr2, [sp, #40] @ 0x28 │ │ eorseq r7, r0, r4, lsl #21 │ │ movteq r0, #40136 @ 0x9cc8 │ │ movteq r0, #40132 @ 0x9cc4 │ │ movteq r0, #40096 @ 0x9ca0 │ │ ldr r1, [pc, #4064] @ 2452df0 │ │ mov r0, #3 │ │ ldr r2, [pc, #4060] @ 2452df4 │ │ @@ -1321167,15 +1321167,15 @@ │ │ vmrs APSR_nzcv, fpscr │ │ bpl 2451fa8 │ │ str r3, [r4] │ │ mov r2, r3 │ │ ldr r1, [pc, #3656] @ 2452eb4 │ │ ldr r1, [pc, r1] │ │ b 2451fb8 │ │ - ldc2l 4, cr2, [sp, #140] @ 0x8c │ │ + ldc2l 4, cr2, [sp, #320] @ 0x140 │ │ movteq r0, #39752 @ 0x9b48 │ │ movteq r0, #39736 @ 0x9b38 │ │ ldrshteq r7, [r0], -ip │ │ cmneq r0, #172, 28 @ 0xac0 │ │ cmneq r0, #60 @ 0x3c │ │ cmneq r0, #224, 2 @ 0x38 │ │ ldrsbteq r7, [r0], -r0 │ │ @@ -1321263,24 +1321263,24 @@ │ │ ldr r5, [pc, #3972] @ 2453160 │ │ movt r6, #4 │ │ ldr r7, [pc, #3968] @ 2453164 │ │ add r4, pc, r4 │ │ add r5, pc, r5 │ │ add r7, pc, r7 │ │ b 2452254 │ │ - ldc2l 2, cr2, [sp, #780] @ 0x30c │ │ + ldc2l 2, cr2, [sp, #960] @ 0x3c0 │ │ movteq r0, #39400 @ 0x99e8 │ │ ldc2l 9, cr11, [pc, #76] @ 245224c @ │ │ cmneq r0, #224, 4 │ │ cmneq r0, #164, 4 @ 0x4000000a │ │ cmneq r0, #128, 4 │ │ movteq r0, #39288 @ 0x9978 │ │ movteq r0, #39276 @ 0x996c │ │ ldc2l 3, cr13, [pc, #336] @ 2452368 │ │ - ldc2l 1, cr2, [sp, #916] @ 0x394 │ │ + ldc2l 2, cr2, [sp, #72] @ 0x48 │ │ mov r0, r4 │ │ mov r2, r5 │ │ mov r3, #992 @ 0x3e0 │ │ bl 270da30 │ │ ldr r8, [pc, #4024] @ 24531e8 │ │ ldr r8, [pc, r8] │ │ sub r1, r8, #1 │ │ @@ -1321369,19 +1321369,19 @@ │ │ mov r1, #24 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #4028] @ 245334c │ │ add r0, pc, r0 │ │ b 2451208 │ │ ldc2l 2, cr13, [pc, #384] @ 245251c │ │ - ldc2l 0, cr2, [sp, #964] @ 0x3c4 │ │ + ldc2l 1, cr2, [sp, #120] @ 0x78 │ │ eorseq r7, r0, r0, ror r4 │ │ movteq r0, #38884 @ 0x97e4 │ │ - ldc2l 10, cr1, [sp, #884] @ 0x374 @ │ │ - ldc2l 13, cr1, [lr, #308] @ 0x134 │ │ + ldc2l 11, cr1, [sp, #40] @ 0x28 @ │ │ + ldc2l 13, cr1, [lr, #488] @ 0x1e8 │ │ ldr r1, [pc, #4080] @ 24533a4 │ │ cmp r6, #1 │ │ mov r0, #1 │ │ add r1, pc, r1 │ │ str r0, [r1] │ │ blt 245370c │ │ ldr r5, [pc, #4060] @ 24533a8 │ │ @@ -1321414,15 +1321414,15 @@ │ │ ldr r0, [pc, r0] │ │ sub r7, r0, #1 │ │ cmp r7, #10 │ │ bcs 2452520 │ │ mov r1, r7 │ │ b 2452568 │ │ ldc2l 5, cr3, [pc, #52] @ 2452484 │ │ - ldc2l 2, cr0, [sp, #772] @ 0x304 │ │ + ldc2l 2, cr0, [sp, #952] @ 0x3b8 │ │ cmneq r0, #196 @ 0xc4 │ │ cmneq r0, #144 @ 0x90 │ │ ldc2l 9, cr5, [ip, #342] @ 0x156 @ │ │ movteq r0, #39468 @ 0x9a2c │ │ movteq r0, #39440 @ 0x9a10 │ │ ldr r0, [pc, #4088] @ 2453464 │ │ movw r2, #57874 @ 0xe212 │ │ @@ -1321459,22 +1321459,22 @@ │ │ vstr d8, [r0] │ │ b 2452598 │ │ movteq r0, #38640 @ 0x96f0 │ │ movteq r0, #38612 @ 0x96d4 │ │ ldc2l 6, cr11, [pc, #248] @ 24525f4 │ │ movteq r0, #38584 @ 0x96b8 │ │ ldc2l 0, cr13, [pc, #784] @ 2452814 │ │ - ldc2l 15, cr1, [sp, #340] @ 0x154 │ │ + ldc2l 15, cr1, [sp, #520] @ 0x208 │ │ movteq r0, #38560 @ 0x96a0 │ │ movteq r0, #38512 @ 0x9670 │ │ ldc2l 0, cr13, [pc, #480] @ 24526f4 │ │ - ldc2l 15, cr1, [sp, #36] @ 0x24 │ │ + ldc2l 15, cr1, [sp, #216] @ 0xd8 │ │ movteq r0, #38488 @ 0x9658 │ │ movteq r0, #38476 @ 0x964c │ │ - ldc2l 14, cr1, [sp, #860] @ 0x35c │ │ + ldc2l 15, cr1, [sp, #16] │ │ ldr r0, [pc, #4024] @ 24534e0 │ │ mov r1, r7 │ │ mov r2, r8 │ │ movw r3, #1032 @ 0x408 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r7, r0 │ │ @@ -1321518,22 +1321518,22 @@ │ │ vldr d16, [r2] │ │ ldr r2, [pc, #4000] @ 245357c │ │ add r2, pc, r2 │ │ vstr d16, [r2] │ │ b 245267c │ │ movteq r0, #38392 @ 0x95f8 │ │ ldc2l 5, cr11, [pc, #424] @ 2452798 │ │ - ldc2l 0, cr10, [sp, #420] @ 0x1a4 │ │ - ldc2l 14, cr1, [sp, #612] @ 0x264 │ │ + ldc2l 0, cr10, [sp, #600] @ 0x258 │ │ + ldc2l 14, cr1, [sp, #792] @ 0x318 │ │ movteq r0, #39100 @ 0x98bc │ │ movteq r0, #39076 @ 0x98a4 │ │ movteq r0, #38336 @ 0x95c0 │ │ cmneq r0, #28, 28 @ 0x1c0 │ │ - ldc2l 0, cr10, [sp, #68] @ 0x44 │ │ - ldc2l 14, cr1, [sp, #260] @ 0x104 │ │ + ldc2l 0, cr10, [sp, #248] @ 0xf8 │ │ + ldc2l 14, cr1, [sp, #440] @ 0x1b8 │ │ ldc2l 15, cr12, [pc, #672] @ 24528b4 │ │ mov r4, r8 │ │ ldr r8, [pc, #3940] @ 2453580 │ │ mov r2, r4 │ │ mov r3, #1056 @ 0x420 │ │ add r8, pc, r8 │ │ mov r0, r8 │ │ @@ -1321590,15 +1321590,15 @@ │ │ movteq r0, #38156 @ 0x950c │ │ movteq r0, #38132 @ 0x94f4 │ │ movteq r0, #38068 @ 0x94b4 │ │ movteq r0, #38016 @ 0x9480 │ │ movteq r0, #38700 @ 0x972c │ │ movteq r0, #37952 @ 0x9440 │ │ cmneq r0, #72, 26 @ 0x1200 │ │ - ldc2l 12, cr1, [sp, #788] @ 0x314 │ │ + ldc2l 12, cr1, [sp, #968] @ 0x3c8 │ │ ldc2l 14, cr12, [pc, #144] @ 24527a8 │ │ mov r7, r6 │ │ ldr r6, [pc, #4072] @ 2453708 │ │ mov r2, r8 │ │ movw r3, #1057 @ 0x421 │ │ add r6, pc, r6 │ │ mov r4, r5 │ │ @@ -1321811,25 +1321811,25 @@ │ │ str r1, [fp, #-60] @ 0xffffffc4 │ │ blt 24530bc │ │ ldr r8, [pc, #3960] @ 24539ec │ │ sub r9, fp, #72 @ 0x48 │ │ mov r1, #0 │ │ add r8, pc, r8 │ │ b 2452af8 │ │ - ldc2l 4, cr1, [sp, #468] @ 0x1d4 │ │ + ldc2l 4, cr1, [sp, #648] @ 0x288 │ │ movteq r0, #37504 @ 0x9280 │ │ - ldc2l 10, cr11, [ip, #480] @ 0x1e0 @ │ │ + ldc2l 10, cr11, [ip, #660] @ 0x294 @ │ │ ldc2l 14, cr2, [pc, #776] @ 2452d9c │ │ movteq r0, #37040 @ 0x90b0 │ │ - ldc2l 3, cr1, [sp, #692] @ 0x2b4 │ │ + ldc2l 3, cr1, [sp, #872] @ 0x368 │ │ ldc2l 13, cr2, [pc, #980] @ 2452e74 │ │ - ldc2l 11, cr15, [ip, #648] @ 0x288 @ │ │ + ldc2l 11, cr15, [ip, #828] @ 0x33c @ │ │ movteq r0, #36968 @ 0x9068 │ │ ldc2l 4, cr1, [ip, #704] @ 0x2c0 │ │ - ldc2l 3, cr1, [sp, #132] @ 0x84 │ │ + ldc2l 3, cr1, [sp, #312] @ 0x138 │ │ cmneq r0, #100, 16 @ 0x640000 │ │ ldr r0, [pc, #3896] @ 24539f0 │ │ add r0, pc, r0 │ │ add r0, r0, r1, lsl #3 │ │ vstr d8, [r0] │ │ add r1, sl, r1, lsl #3 │ │ mov r0, r6 │ │ @@ -1321903,19 +1321903,19 @@ │ │ ldr r0, [pc, #3648] @ 2453a1c │ │ mov r2, r8 │ │ movw r3, #1531 @ 0x5fb │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2452ac0 │ │ - ldc2l 6, cr9, [sp, #676] @ 0x2a4 │ │ + ldc2l 6, cr9, [sp, #856] @ 0x358 │ │ ldc2l 15, cr10, [pc, #392] @ 2452d84 │ │ ldc2l 0, cr1, [pc, #172] @ 2452cac │ │ movteq pc, #36812 @ 0x8fcc @ │ │ - vcadd.f32 d27, d28, d25, #270 │ │ + ldc2l 8, cr11, [ip, #856] @ 0x358 │ │ ldc2l 4, cr7, [lr, #456] @ 0x1c8 │ │ cmneq r0, #80, 16 @ 0x500000 │ │ ldr r0, [pc, #4048] @ 2453be4 │ │ movw r4, #21846 @ 0x5556 │ │ movt r4, #21845 @ 0x5555 │ │ ldr r0, [pc, r0] │ │ ldr r5, [pc, #4036] @ 2453be8 │ │ @@ -1321963,15 +1321963,15 @@ │ │ ldr sl, [pc, #3904] @ 2453c0c │ │ add r8, pc, r8 │ │ add sl, pc, sl │ │ b 2452d04 │ │ eorseq r6, r0, r0, ror #25 │ │ movteq pc, #36604 @ 0x8efc @ │ │ ldc2l 9, cr12, [pc, #16] @ 2452cf4 @ │ │ - ldc2l 7, cr1, [sp, #612] @ 0x264 │ │ + ldc2l 7, cr1, [sp, #792] @ 0x318 │ │ str r3, [r4] │ │ mov r1, r3 │ │ ldr r2, [pc, #3868] @ 2453c10 │ │ ldr r2, [pc, r2] │ │ vorr d8, d16, d16 │ │ sub r3, r2, #1 │ │ cmp r1, r3 │ │ @@ -1321985,15 +1321985,15 @@ │ │ sub r1, r1, #2 │ │ cmp r1, r9 │ │ bcs 2452d40 │ │ vorr d16, d8, d8 │ │ b 2452d64 │ │ eorseq r6, r0, ip, lsr #22 │ │ movteq pc, #36512 @ 0x8ea0 @ │ │ - ldc2l 1, cr1, [sp, #612] @ 0x264 │ │ + ldc2l 1, cr1, [sp, #792] @ 0x318 │ │ ldc2l 12, cr7, [ip, #456] @ 0x1c8 │ │ ldr r0, [pc, #3788] @ 2453c14 │ │ mov r2, sl │ │ movw r3, #3140 @ 0xc44 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ @@ -1322031,15 +1322031,15 @@ │ │ ldr r2, [pc, #4048] @ 2453dac │ │ ldr r2, [pc, r2] │ │ ldr r5, [pc, #4044] @ 2453db0 │ │ ldr r6, [pc, #4044] @ 2453db4 │ │ add r5, pc, r5 │ │ add r6, pc, r6 │ │ b 2452e24 │ │ - ldc2l 7, cr11, [ip, #212] @ 0xd4 │ │ + ldc2l 7, cr11, [ip, #392] @ 0x188 │ │ ldc2l 2, cr7, [lr, #1000] @ 0x3e8 │ │ cmneq r0, #224, 12 @ 0xe000000 │ │ eorseq r6, r0, r4, ror fp │ │ movteq pc, #36240 @ 0x8d90 @ │ │ add r1, sl, r1, lsl #3 │ │ cmp r0, #2 │ │ mov r0, r3 │ │ @@ -1322062,28 +1322062,28 @@ │ │ ldr r0, [pc, r0] │ │ vldr d16, [r7] │ │ ldr r2, [pc, #4064] @ 2453e40 │ │ sub r3, r0, #1 │ │ ldr r2, [pc, r2] │ │ b 2452e04 │ │ ldc2l 7, cr12, [pc, #624] @ 24530e0 │ │ - ldc2l 6, cr1, [sp, #180] @ 0xb4 │ │ + ldc2l 6, cr1, [sp, #360] @ 0x168 │ │ movteq r0, #36904 @ 0x9028 │ │ cmneq r0, #80, 12 @ 0x5000000 │ │ movteq pc, #36128 @ 0x8d20 @ │ │ ldc2l 7, cr12, [pc, #160] @ 2452f24 │ │ - ldc2l 5, cr1, [sp, #740] @ 0x2e4 │ │ + ldc2l 5, cr1, [sp, #920] @ 0x398 │ │ movteq pc, #36796 @ 0x8fbc @ │ │ movteq pc, #36084 @ 0x8cf4 @ │ │ movteq pc, #36324 @ 0x8de4 @ │ │ cmneq r0, #192, 10 @ 0x30000000 │ │ movteq pc, #35988 @ 0x8c94 @ │ │ movteq pc, #36284 @ 0x8dbc @ │ │ ldc2l 6, cr12, [pc, #688] @ 2453154 │ │ - ldc2l 5, cr1, [sp, #244] @ 0xf4 │ │ + ldc2l 5, cr1, [sp, #424] @ 0x1a8 │ │ movteq pc, #36200 @ 0x8d68 @ │ │ cmneq r0, #224, 8 @ 0xe0000000 │ │ movteq pc, #35764 @ 0x8bb4 @ │ │ movteq pc, #36056 @ 0x8cd8 @ │ │ movteq pc, #35776 @ 0x8bc0 @ │ │ ldr r1, [pc, #3972] @ 2453e44 │ │ ldr r1, [pc, r1] │ │ @@ -1322192,30 +1322192,30 @@ │ │ cmp r0, #1 │ │ ldr r2, [pc, #3636] @ 2453e98 │ │ ldr r0, [fp, #12] │ │ add r2, pc, r2 │ │ bne 245451c │ │ vstr d16, [r0] │ │ b 24544e8 │ │ - ldc2l 0, cr1, [lr, #896] @ 0x380 │ │ + ldc2l 1, cr1, [lr, #52] @ 0x34 │ │ ldr r0, [pc, #3612] @ 2453e9c │ │ mov r1, #0 │ │ ldr r2, [pc, #3608] @ 2453ea0 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ strb r1, [r2] │ │ mov r1, #18 │ │ bl 270da00 │ │ b 2451444 │ │ movteq pc, #35656 @ 0x8b48 @ │ │ - ldc2l 14, cr0, [sp, #276] @ 0x114 │ │ + ldc2l 14, cr0, [sp, #456] @ 0x1c8 │ │ cmneq r0, #104, 8 @ 0x68000000 │ │ - ldc2l 0, cr1, [lr, #352] @ 0x160 │ │ + ldc2l 0, cr1, [lr, #532] @ 0x214 │ │ movteq pc, #35520 @ 0x8ac0 @ │ │ - ldc2l 13, cr0, [sp, #756] @ 0x2f4 │ │ + ldc2l 13, cr0, [sp, #936] @ 0x3a8 │ │ ldr r0, [pc, #4052] @ 2454090 │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #4048] @ 2454094 │ │ movw r2, #57874 @ 0xe212 │ │ movt r2, #4 │ │ ldr r1, [pc, r1] │ │ add r1, r1, r0 │ │ @@ -1322245,21 +1322245,21 @@ │ │ ldr r2, [pc, #4092] @ 2454130 │ │ str r0, [fp, #-60] @ 0xffffffc4 │ │ add r2, pc, r2 │ │ add r1, r2, r1, lsl #3 │ │ vstr d8, [r1] │ │ b 24531b4 │ │ cmneq r0, #224, 6 @ 0x80000003 │ │ - ldc2l 4, cr9, [sp, #964] @ 0x3c4 │ │ - ldc2l 3, cr1, [sp, #132] @ 0x84 │ │ + ldc2l 5, cr9, [sp, #120] @ 0x78 │ │ + ldc2l 3, cr1, [sp, #312] @ 0x138 │ │ movteq pc, #36164 @ 0x8d44 @ │ │ movteq pc, #35412 @ 0x8a54 @ │ │ cmneq r0, #176, 4 │ │ - ldc2l 4, cr9, [sp, #628] @ 0x274 │ │ - ldc2l 2, cr1, [sp, #820] @ 0x334 │ │ + ldc2l 4, cr9, [sp, #808] @ 0x328 │ │ + ldc2l 2, cr1, [sp, #1000] @ 0x3e8 │ │ ldc2l 4, cr12, [pc, #208] @ 245323c │ │ ldr r0, [pc, #4036] @ 2454134 │ │ movw r3, #1535 @ 0x5ff │ │ ldr r2, [pc, #4032] @ 2454138 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1322371,15 +1322371,15 @@ │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 245321c │ │ movteq pc, #35756 @ 0x8bac @ │ │ ldc2l 2, cr12, [pc, #860] @ 245369c │ │ movteq pc, #34968 @ 0x8898 @ │ │ - ldc2l 11, cr0, [sp, #596] @ 0x254 @ │ │ + ldc2l 11, cr0, [sp, #776] @ 0x308 @ │ │ movteq pc, #34976 @ 0x88a0 @ │ │ ldc2l 15, cr2, [ip, #484] @ 0x1e4 │ │ ldc2l 13, cr6, [lr, #480] @ 0x1e0 │ │ ldr r0, [pc, #3944] @ 24542c0 │ │ mov r1, #1 │ │ add r0, pc, r0 │ │ str r1, [r0] │ │ @@ -1322398,15 +1322398,15 @@ │ │ add r4, pc, r4 │ │ add r5, pc, r5 │ │ mov r0, #1 │ │ add r7, pc, r7 │ │ b 24533e8 │ │ movteq pc, #34896 @ 0x8850 @ │ │ cmneq r0, #228 @ 0xe4 │ │ - ldc2l 0, cr1, [sp, #852] @ 0x354 │ │ + ldc2l 1, cr1, [sp, #8] │ │ movteq pc, #34892 @ 0x884c @ │ │ cmneq r0, #80, 2 │ │ ldc2l 8, cr0, [pc, #352] @ 2453520 │ │ ldc2l 10, cr4, [ip, #188] @ 0xbc @ │ │ movteq pc, #34776 @ 0x87d8 @ │ │ ldr r2, [fp, #-60] @ 0xffffffc4 │ │ ldr r1, [pc, #4056] @ 24543a8 │ │ @@ -1322628,16 +1322628,16 @@ │ │ add r0, pc, r0 │ │ b 2454080 │ │ movteq pc, #33992 @ 0x84c8 @ │ │ movteq pc, #33984 @ 0x84c0 @ │ │ movteq pc, #33916 @ 0x847c @ │ │ movteq pc, #33900 @ 0x846c @ │ │ movteq pc, #33868 @ 0x844c @ │ │ - ldc2l 14, cr8, [sp, #628] @ 0x274 │ │ - ldc2l 12, cr0, [sp, #820] @ 0x334 │ │ + ldc2l 14, cr8, [sp, #808] @ 0x328 │ │ + ldc2l 12, cr0, [sp, #1000] @ 0x3e8 │ │ vcadd.f32 d16, d28, d9, #270 │ │ movteq pc, #33788 @ 0x83fc @ │ │ movteq pc, #33756 @ 0x83dc @ │ │ movteq pc, #33708 @ 0x83ac @ │ │ movteq pc, #34368 @ 0x8640 @ │ │ movteq pc, #33596 @ 0x833c @ │ │ eorseq r6, r0, r8, lsl #2 │ │ @@ -1322729,15 +1322729,15 @@ │ │ ldr r2, [pc, r2] │ │ ldr r5, [pc, #3744] @ 2454768 │ │ ldr r6, [pc, #3744] @ 245476c │ │ add r5, pc, r5 │ │ add r6, pc, r6 │ │ b 2453914 │ │ ldc2l 13, cr11, [pc, #240] @ 24539cc │ │ - ldc2l 11, cr0, [sp, #820] @ 0x334 @ │ │ + ldc2l 11, cr0, [sp, #1000] @ 0x3e8 @ │ │ movteq pc, #34256 @ 0x85d0 @ │ │ movteq pc, #33544 @ 0x8308 @ │ │ movteq pc, #33784 @ 0x83f8 @ │ │ eorseq r6, r0, ip, lsl #1 │ │ movteq pc, #33452 @ 0x82ac @ │ │ movteq pc, #33756 @ 0x83dc @ │ │ add r1, r7, r1, lsl #3 │ │ @@ -1322790,35 +1322790,35 @@ │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #3464] @ 245474c │ │ add r1, r7, r1, lsl #3 │ │ add r0, pc, r0 │ │ b 2453bc0 │ │ - ldc2l 10, cr0, [sp, #900] @ 0x384 @ │ │ + ldc2l 11, cr0, [sp, #56] @ 0x38 @ │ │ eorseq r5, r0, r8, ror #31 │ │ movteq pc, #33288 @ 0x8208 @ │ │ movteq pc, #33580 @ 0x832c @ │ │ movteq pc, #33300 @ 0x8214 @ │ │ cmneq r0, #32, 24 @ 0x2000 │ │ movteq pc, #33212 @ 0x81bc @ │ │ movteq pc, #33928 @ 0x8488 @ │ │ - ldc2l 10, cr0, [sp, #228] @ 0xe4 @ │ │ + ldc2l 10, cr0, [sp, #408] @ 0x198 @ │ │ cmneq r0, #4, 20 @ 0x4000 │ │ movteq pc, #33072 @ 0x8130 @ │ │ movteq pc, #33056 @ 0x8120 @ │ │ - ldc2l 11, cr8, [sp, #452] @ 0x1c4 @ │ │ + ldc2l 11, cr8, [sp, #632] @ 0x278 @ │ │ movteq pc, #32964 @ 0x80c4 @ │ │ movteq pc, #32948 @ 0x80b4 @ │ │ ldc2l 10, cr11, [pc, #704] @ 2453cd0 @ │ │ movteq pc, #32908 @ 0x808c @ │ │ ldc2l 4, cr0, [ip, #804] @ 0x324 │ │ cmneq r0, #4, 18 @ 0x10000 │ │ movteq pc, #32836 @ 0x8044 @ │ │ - ldc2l 10, cr8, [sp, #628] @ 0x274 @ │ │ + ldc2l 10, cr8, [sp, #808] @ 0x328 @ │ │ ldr r0, [pc, #3408] @ 2454778 │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #3404] @ 245477c │ │ add r0, r0, r0, lsl #1 │ │ ldr r1, [pc, r1] │ │ add r0, r1, r0 │ │ sub r1, r0, #1 │ │ @@ -1322928,21 +1322928,21 @@ │ │ ldr r0, [pc, #2932] @ 2454754 │ │ add r0, pc, r0 │ │ b 2451208 │ │ movteq pc, #33476 @ 0x82c4 @ │ │ cmneq r0, #236, 16 @ 0xec0000 │ │ movteq lr, #36788 @ 0x8fb4 │ │ ldc2l 9, cr11, [pc, #384] @ 2453d78 @ │ │ - ldc2l 8, cr0, [sp, #324] @ 0x144 │ │ + ldc2l 8, cr0, [sp, #504] @ 0x1f8 │ │ movteq pc, #33364 @ 0x8254 @ │ │ movteq lr, #36748 @ 0x8f8c │ │ movteq pc, #32892 @ 0x807c @ │ │ movteq lr, #36660 @ 0x8f34 │ │ movteq pc, #32864 @ 0x8060 @ │ │ - ldc2l 7, cr0, [sp, #916] @ 0x394 │ │ + ldc2l 8, cr0, [sp, #72] @ 0x48 │ │ movteq pc, #32812 @ 0x802c @ │ │ ldc2l 8, cr11, [pc, #832] @ 2453f5c │ │ movteq lr, #36496 @ 0x8e90 │ │ movteq lr, #36788 @ 0x8fb4 │ │ movteq lr, #36508 @ 0x8e9c │ │ movteq pc, #33092 @ 0x8144 @ │ │ ldr r0, [pc, #2520] @ 2454608 │ │ @@ -1323040,15 +1323040,15 @@ │ │ add r6, pc, r6 │ │ b 2453dd8 │ │ movteq lr, #36484 @ 0x8e84 │ │ cmneq r0, #104, 14 @ 0x1a00000 │ │ movteq pc, #33052 @ 0x811c @ │ │ movteq lr, #36388 @ 0x8e24 │ │ ldc2l 8, cr11, [pc, #224] @ 2453e98 │ │ - ldc2l 6, cr0, [sp, #804] @ 0x324 │ │ + ldc2l 6, cr0, [sp, #984] @ 0x3d8 │ │ add r1, r5, r1, lsl #3 │ │ cmp r0, #2 │ │ mov r0, r3 │ │ str r3, [sl] │ │ vldr d17, [r1] │ │ vmul.f64 d16, d17, d16 │ │ vstr d16, [r4] │ │ @@ -1323079,30 +1323079,30 @@ │ │ bl 270da00 │ │ b 24540f4 │ │ movteq lr, #36280 @ 0x8db8 │ │ movteq lr, #36252 @ 0x8d9c │ │ movteq lr, #36204 @ 0x8d6c │ │ movteq lr, #36136 @ 0x8d28 │ │ ldc2l 7, cr11, [pc, #192] @ 2453f14 │ │ - ldc2l 5, cr0, [sp, #772] @ 0x304 │ │ + ldc2l 5, cr0, [sp, #952] @ 0x3b8 │ │ ldrhteq r5, [r0], -r0 │ │ movteq lr, #36048 @ 0x8cd0 │ │ movteq lr, #36092 @ 0x8cfc │ │ ldc2l 6, cr11, [pc, #784] @ 2454178 │ │ - ldc2l 5, cr0, [sp, #340] @ 0x154 │ │ + ldc2l 5, cr0, [sp, #520] @ 0x208 │ │ movteq lr, #36028 @ 0x8cbc │ │ movteq lr, #35960 @ 0x8c78 │ │ cmneq r0, #112, 2 │ │ ldc2l 6, cr11, [pc, #416] @ 245401c │ │ - ldc2l 4, cr0, [sp, #996] @ 0x3e4 │ │ + ldc2l 5, cr0, [sp, #152] @ 0x98 │ │ movteq lr, #35936 @ 0x8c60 │ │ movteq lr, #35868 @ 0x8c1c │ │ movteq lr, #35892 @ 0x8c34 │ │ ldc2l 6, cr11, [pc, #64] @ 2453ed0 │ │ - ldc2l 4, cr0, [sp, #644] @ 0x284 │ │ + ldc2l 4, cr0, [sp, #824] @ 0x338 │ │ cmneq r0, #216, 8 @ 0xd8000000 │ │ cmneq r0, #224, 8 @ 0xe0000000 │ │ movteq lr, #35720 @ 0x8b88 │ │ ldc2l 0, cr6, [lr, #540] @ 0x21c │ │ movteq lr, #35680 @ 0x8b60 │ │ ldr r0, [pc, #2000] @ 245467c │ │ ldr r0, [pc, r0] │ │ @@ -1323226,15 +1323226,15 @@ │ │ ldr r2, [pc, #1332] @ 24545bc │ │ add r2, pc, r2 │ │ str r1, [r2] │ │ b 2451208 │ │ movteq lr, #36392 @ 0x8e28 │ │ movteq lr, #35640 @ 0x8b38 │ │ ldc2l 5, cr11, [pc, #208] @ 2454170 │ │ - ldc2l 3, cr0, [sp, #788] @ 0x314 │ │ + ldc2l 3, cr0, [sp, #968] @ 0x3c8 │ │ movteq lr, #36324 @ 0x8de4 │ │ ldr r0, [pc, #1588] @ 24546e0 │ │ mov r1, #0 │ │ ldr r2, [pc, #1584] @ 24546e4 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ strb r1, [r2] │ │ @@ -1323265,23 +1323265,23 @@ │ │ ldr r7, [pc, #1432] @ 24546bc │ │ mov r1, #1 │ │ add r6, pc, r6 │ │ add r7, pc, r7 │ │ b 245419c │ │ cmneq r0, #132, 6 @ 0x10000002 │ │ ldc2l 14, cr15, [fp, #1012] @ 0x3f4 │ │ - ldc2l 3, cr0, [sp, #228] @ 0xe4 │ │ + ldc2l 3, cr0, [sp, #408] @ 0x198 │ │ movteq lr, #35456 @ 0x8a80 │ │ cmneq r0, #36, 6 @ 0x90000000 │ │ movteq lr, #36156 @ 0x8d3c │ │ cmneq r0, #108, 6 @ 0xb0000001 │ │ movteq lr, #36076 @ 0x8cec │ │ - ldc2l 15, cr13, [ip, #496] @ 0x1f0 │ │ + ldc2l 15, cr13, [ip, #676] @ 0x2a4 │ │ cmneq r0, #84, 6 @ 0x50000001 │ │ - ldc2l 2, cr0, [sp, #836] @ 0x344 │ │ + ldc2l 2, cr0, [sp, #1016] @ 0x3f8 │ │ add r0, r5, r1, lsl #3 │ │ vldr d17, [r8] │ │ vldr d16, [r0] │ │ mov r0, r4 │ │ vsub.f64 d16, d8, d16 │ │ vadd.f64 d16, d16, d17 │ │ vstr d16, [fp, #-72] @ 0xffffffb8 │ │ @@ -1323413,15 +1323413,15 @@ │ │ add r2, pc, r2 │ │ add r1, r2, r1, lsl #3 │ │ mov r2, #1 │ │ bl 270dad0 │ │ b 2452378 │ │ ldc2l 6, cr13, [lr, #104] @ 0x68 │ │ cmneq r0, #212, 4 @ 0x4000000d │ │ - ldc2l 1, cr0, [sp, #84] @ 0x54 │ │ + ldc2l 1, cr0, [sp, #264] @ 0x108 │ │ ldr r6, [pc, #1056] @ 24547b4 │ │ sub sl, fp, #72 @ 0x48 │ │ ldr r5, [pc, #1052] @ 24547b8 │ │ mov r1, #1 │ │ add r6, pc, r6 │ │ add r5, pc, r5 │ │ b 2454408 │ │ @@ -1323508,20 +1323508,20 @@ │ │ ldr r1, [r5] │ │ ldr r0, [pc, #236] @ 24545e0 │ │ str r1, [r2] │ │ add r0, pc, r0 │ │ b 2451208 │ │ movteq lr, #34560 @ 0x8700 │ │ movteq lr, #35276 @ 0x89cc │ │ - ldc2l 1, cr14, [ip, #904] @ 0x388 │ │ + ldc2l 2, cr14, [ip, #60] @ 0x3c │ │ eorseq r5, r0, ip, ror #8 │ │ eorseq r5, r0, r4, ror r4 │ │ - ldc2l 15, cr15, [ip, #340] @ 0x154 │ │ + ldc2l 15, cr15, [ip, #520] @ 0x208 │ │ cmneq r0, #8, 2 │ │ - ldc2l 0, cr6, [sp, #892] @ 0x37c │ │ + ldc2l 1, cr6, [sp, #48] @ 0x30 │ │ ldr r0, [pc, #212] @ 24545f8 │ │ mov r1, #0 │ │ ldr r2, [pc, #208] @ 24545fc │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ strb r1, [r2] │ │ mov r1, #48 @ 0x30 │ │ @@ -1323540,166 +1323540,166 @@ │ │ b 2451444 │ │ movteq lr, #34396 @ 0x865c │ │ movteq lr, #34380 @ 0x864c │ │ ldc2l 7, cr3, [ip, #820] @ 0x334 │ │ movteq sp, #35252 @ 0x89b4 │ │ movteq sp, #35264 @ 0x89c0 │ │ ldc2l 9, cr14, [lr, #480] @ 0x1e0 @ │ │ - ldc2l 2, cr15, [ip, #292] @ 0x124 │ │ - ldc2l 12, cr14, [ip, #500] @ 0x1f4 │ │ + ldc2l 2, cr15, [ip, #472] @ 0x1d8 │ │ + ldc2l 12, cr14, [ip, #680] @ 0x2a8 │ │ ldc2l 6, cr5, [ip, #584] @ 0x248 │ │ movteq sp, #35084 @ 0x890c │ │ - ldc2l 12, cr14, [ip, #36] @ 0x24 │ │ + ldc2l 12, cr14, [ip, #216] @ 0xd8 │ │ movteq sp, #35084 @ 0x890c │ │ msreq SPSR_fsxc, #4, 4 @ 0x40000000 │ │ movteq sp, #35048 @ 0x88e8 │ │ movteq sp, #35032 @ 0x88d8 │ │ ldc2l 2, cr10, [pc, #816] @ 24548e0 │ │ - ldc2l 1, cr15, [ip, #372] @ 0x174 │ │ - ldc2l 11, cr14, [ip, #612] @ 0x264 @ │ │ + ldc2l 1, cr15, [ip, #552] @ 0x228 │ │ + ldc2l 11, cr14, [ip, #792] @ 0x318 @ │ │ movteq sp, #35708 @ 0x8b7c │ │ ldc2l 9, cr5, [lr, #440] @ 0x1b8 @ │ │ movteq sp, #35688 @ 0x8b68 │ │ movteq lr, #34644 @ 0x8754 │ │ movteq lr, #34508 @ 0x86cc │ │ movteq lr, #34184 @ 0x8588 │ │ ldc2l 5, cr15, [lr, #736] @ 0x2e0 │ │ movteq lr, #34108 @ 0x853c │ │ ldc2l 5, cr15, [lr, #384] @ 0x180 │ │ movteq lr, #34312 @ 0x8608 │ │ ldc2l 6, cr15, [lr, #208] @ 0xd0 │ │ - ldc2l 2, cr13, [ip, #148] @ 0x94 │ │ + ldc2l 2, cr13, [ip, #328] @ 0x148 │ │ msreq SPSR_fsxc, #108 @ 0x6c │ │ ldc2l 12, cr4, [lr, #472] @ 0x1d8 │ │ - ldc2l 0, cr9, [ip, #644] @ 0x284 │ │ + ldc2l 0, cr9, [ip, #824] @ 0x338 │ │ movteq sp, #34588 @ 0x871c │ │ - ldc2l 2, cr13, [ip, #244] @ 0xf4 │ │ - ldc2l 12, cr14, [sp, #336] @ 0x150 │ │ + ldc2l 2, cr13, [ip, #424] @ 0x1a8 │ │ + ldc2l 12, cr14, [sp, #516] @ 0x204 │ │ movteq sp, #34492 @ 0x86bc │ │ - ldc2l 9, cr14, [ip, #370] @ 0x172 @ │ │ + ldc2l 9, cr14, [ip, #460] @ 0x1cc @ │ │ msreq SPSR_fsxc, #220, 30 @ 0x370 │ │ movteq lr, #33456 @ 0x82b0 │ │ movteq sp, #36844 @ 0x8fec │ │ msreq SPSR_fsxc, #192, 16 @ 0xc00000 │ │ movteq sp, #36764 @ 0x8f9c │ │ ldc2l 9, cr10, [pc, #320] @ 2454760 @ │ │ - ldc2l 8, cr15, [ip, #196] @ 0xc4 │ │ + ldc2l 8, cr15, [ip, #376] @ 0x178 │ │ movteq sp, #36760 @ 0x8f98 │ │ movteq sp, #36692 @ 0x8f54 │ │ msreq SPSR_fsxc, #120, 16 @ 0x780000 │ │ eorseq r4, r0, ip, lsl #26 │ │ ldc2l 9, cr10, [pc, #120] @ 24546b0 @ │ │ - ldc2l 7, cr15, [ip, #820] @ 0x334 │ │ + ldc2l 7, cr15, [ip, #1000] @ 0x3e8 │ │ movteq sp, #36660 @ 0x8f34 │ │ movteq sp, #36592 @ 0x8ef0 │ │ movteq sp, #36620 @ 0x8f0c │ │ vcadd.f32 q13, , q12, #270 │ │ - ldc2l 7, cr15, [ip, #484] @ 0x1e4 │ │ + ldc2l 7, cr15, [ip, #664] @ 0x298 │ │ ldc2l 2, cr5, [lr, #924] @ 0x39c │ │ movteq sp, #36288 @ 0x8dc0 │ │ ldc2l 8, cr0, [pc, #372] @ 24547d0 │ │ ldc2l 11, cr14, [lr, #320] @ 0x140 @ │ │ msreq SPSR_fsxc, #188, 14 @ 0x2f00000 │ │ movteq sp, #36512 @ 0x8ea0 │ │ movteq lr, #33132 @ 0x816c │ │ movteq sp, #36468 @ 0x8e74 │ │ vcadd.f32 d26, d31, d8, #270 │ │ - ldc2l 7, cr15, [ip, #100] @ 0x64 │ │ + ldc2l 7, cr15, [ip, #280] @ 0x118 │ │ movteq sp, #36360 @ 0x8e08 │ │ movteq sp, #36332 @ 0x8dec │ │ movteq sp, #36224 @ 0x8d80 │ │ movteq sp, #36156 @ 0x8d3c │ │ ldc2l 7, cr10, [pc, #272] @ 245479c │ │ - ldc2l 5, cr15, [ip, #852] @ 0x354 │ │ + ldc2l 6, cr15, [ip, #8] │ │ msreq SPSR_fsxc, #40, 12 @ 0x2800000 │ │ mlaseq r0, ip, sl, r4 │ │ movteq sp, #36036 @ 0x8cc4 │ │ ldc2l 6, cr10, [pc, #784] @ 24549b0 │ │ - ldc2l 5, cr15, [ip, #340] @ 0x154 │ │ + ldc2l 5, cr15, [ip, #520] @ 0x208 │ │ eorseq r4, r0, ip, asr sl │ │ movteq sp, #35964 @ 0x8c7c │ │ ldc2l 6, cr10, [pc, #512] @ 24548b0 │ │ - ldc2l 5, cr15, [ip, #68] @ 0x44 │ │ + ldc2l 5, cr15, [ip, #248] @ 0xf8 │ │ msreq SPSR_fsxc, #64, 10 @ 0x10000000 │ │ movteq sp, #35900 @ 0x8c3c │ │ ldc2l 4, cr10, [pc, #992] @ 2454aa0 │ │ - ldc2l 3, cr15, [ip, #548] @ 0x224 │ │ + ldc2l 3, cr15, [ip, #728] @ 0x2d8 │ │ movteq sp, #35416 @ 0x8a58 │ │ movteq sp, #35392 @ 0x8a40 │ │ movteq sp, #35360 @ 0x8a20 │ │ movteq sp, #35456 @ 0x8a80 │ │ eorseq r4, r0, r8, asr #19 │ │ movteq sp, #35816 @ 0x8be8 │ │ ldc2l 5, cr10, [pc, #928] @ 2454a80 │ │ - ldc2l 4, cr15, [ip, #484] @ 0x1e4 │ │ + ldc2l 4, cr15, [ip, #664] @ 0x298 │ │ eorseq r4, r0, r0, asr #15 │ │ movteq sp, #35636 @ 0x8b34 │ │ - ldc2l 14, cr14, [ip, #180] @ 0xb4 │ │ + ldc2l 14, cr14, [ip, #360] @ 0x168 │ │ ldc2l 9, cr5, [ip, #12] @ │ │ ldc2l 11, cr14, [lr, #880] @ 0x370 @ │ │ movteq lr, #34672 @ 0x8770 │ │ movteq lr, #33968 @ 0x84b0 │ │ movteq lr, #33892 @ 0x8464 │ │ ldc2l 14, cr10, [pc, #432] @ 24548b8 │ │ - ldc2l 12, cr15, [ip, #1012] @ 0x3f4 │ │ + ldc2l 13, cr15, [ip, #168] @ 0xa8 │ │ movteq lr, #33892 @ 0x8464 │ │ movteq lr, #33824 @ 0x8420 │ │ msreq SPSR_fsxc, #68, 26 @ 0x1100 │ │ ldrsbteq r5, [r0], -r8 │ │ ldc2l 14, cr10, [pc, #32] @ 2454740 │ │ - ldc2l 12, cr15, [ip, #612] @ 0x264 │ │ + ldc2l 12, cr15, [ip, #792] @ 0x318 │ │ movteq lr, #33792 @ 0x8400 │ │ movteq lr, #33724 @ 0x83bc │ │ movteq lr, #33752 @ 0x83d8 │ │ ldc2l 13, cr10, [pc, #720] @ 2454a04 │ │ - ldc2l 12, cr15, [ip, #276] @ 0x114 │ │ + ldc2l 12, cr15, [ip, #456] @ 0x1c8 │ │ ldc2l 9, cr1, [ip, #340] @ 0x154 @ │ │ movteq lr, #33404 @ 0x827c │ │ movteq lr, #33448 @ 0x82a8 │ │ movteq lr, #33380 @ 0x8264 │ │ ldc2l 12, cr10, [pc, #448] @ 245490c │ │ - ldc2l 11, cr15, [ip, #4] @ │ │ - ldc2l 5, cr15, [ip, #244] @ 0xf4 │ │ + ldc2l 11, cr15, [ip, #184] @ 0xb8 @ │ │ + ldc2l 5, cr15, [ip, #424] @ 0x1a8 │ │ ldc2l 13, cr0, [pc, #548] @ 245497c │ │ - ldc2l 5, cr15, [sp, #836] @ 0x344 │ │ + ldc2l 5, cr15, [sp, #1016] @ 0x3f8 │ │ msreq SPSR_fsxc, #136, 24 @ 0x8800 │ │ movteq lr, #33644 @ 0x836c │ │ movteq lr, #34360 @ 0x8638 │ │ movteq lr, #33600 @ 0x8340 │ │ ldc2l 13, cr10, [pc, #336] @ 24548c0 │ │ - ldc2l 11, cr15, [ip, #916] @ 0x394 @ │ │ + ldc2l 12, cr15, [ip, #72] @ 0x48 │ │ movteq lr, #33484 @ 0x82cc │ │ movteq lr, #33456 @ 0x82b0 │ │ movteq lr, #33284 @ 0x8204 │ │ movteq lr, #33216 @ 0x81c0 │ │ ldc2l 11, cr10, [pc, #816] @ 2454ab8 @ │ │ - ldc2l 10, cr15, [ip, #372] @ 0x174 @ │ │ + ldc2l 10, cr15, [ip, #552] @ 0x228 @ │ │ msreq SPSR_fsxc, #176, 20 @ 0xb0000 │ │ eorseq r4, r0, r0, lsr pc │ │ movteq lr, #33112 @ 0x8158 │ │ ldc2l 11, cr10, [pc, #352] @ 24548fc @ │ │ - ldc2l 9, cr15, [ip, #466] @ 0x1d2 @ │ │ + ldc2l 10, cr15, [ip, #88] @ 0x58 @ │ │ ldrshteq r4, [r0], -r0 │ │ movteq lr, #33040 @ 0x8110 │ │ ldc2l 11, cr10, [pc, #80] @ 24547fc @ │ │ - ldc2l 9, cr15, [ip, #330] @ 0x14a @ │ │ + ldc2l 9, cr15, [ip, #420] @ 0x1a4 @ │ │ msreq SPSR_fsxc, #204, 18 @ 0x330000 │ │ movteq lr, #32972 @ 0x80cc │ │ ldc2l 2, cr10, [pc, #512] @ 24549bc │ │ - ldc2l 1, cr15, [ip, #68] @ 0x44 │ │ + ldc2l 1, cr15, [ip, #248] @ 0xf8 │ │ movteq sp, #34796 @ 0x87ec │ │ movteq sp, #34772 @ 0x87d4 │ │ movteq sp, #34740 @ 0x87b4 │ │ movteq sp, #34840 @ 0x8818 │ │ movteq lr, #32896 @ 0x8080 │ │ eorseq r4, r0, ip, ror #25 │ │ movteq lr, #32864 @ 0x8060 │ │ - ldc2l 3, cr15, [ip, #356] @ 0x164 │ │ + ldc2l 3, cr15, [ip, #536] @ 0x218 │ │ ldc2l 14, cr5, [ip, #200] @ 0xc8 │ │ - ldc2l 13, cr14, [sp, #180] @ 0xb4 │ │ + ldc2l 13, cr14, [sp, #360] @ 0x168 │ │ │ │ 024547e4 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ beq 2454800 │ │ @@ -1324257,15 +1324257,15 @@ │ │ bl 270f1e0 │ │ mov r0, r5 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ ldr r0, [sp, #4] │ │ sub sp, fp, #8 │ │ pop {r4, r5, fp, pc} │ │ - ldc2l 12, cr1, [lr, #996] @ 0x3e4 │ │ + ldc2l 13, cr1, [lr, #152] @ 0x98 │ │ │ │ 0245505c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #124 @ 0x7c │ │ mov r5, r3 │ │ mov r6, r2 │ │ @@ -1324452,21 +1324452,21 @@ │ │ str r1, [r2] │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 11, cr1, [ip, #828] @ 0x33c @ │ │ - ldc2l 6, cr10, [ip, #572] @ 0x23c │ │ + ldc2l 6, cr10, [ip, #752] @ 0x2f0 │ │ eorseq r3, r0, ip, lsl #18 │ │ ldc2l 11, cr1, [ip, #668] @ 0x29c @ │ │ - ldc2l 4, cr10, [ip, #524] @ 0x20c │ │ + ldc2l 4, cr10, [ip, #704] @ 0x2c0 │ │ ldc2l 12, cr1, [ip, #1020] @ 0x3fc │ │ eorseq r3, r0, r4, lsl r8 │ │ - ldc2l 4, cr10, [ip, #28] │ │ + ldc2l 4, cr10, [ip, #208] @ 0xd0 │ │ │ │ 02455378 : │ │ cmp r0, #1 │ │ ldreq r0, [pc, #32] @ 24553a4 │ │ ldreq r0, [pc, r0] │ │ bxeq lr │ │ ldr r0, [pc, #16] @ 24553a0 │ │ @@ -1324552,22 +1324552,22 @@ │ │ add r0, pc, r0 │ │ bl 270ce70 │ │ mov r0, r4 │ │ pop {r4, sl, fp, lr} │ │ b 270ce40 │ │ ldc2l 5, cr2, [ip, #984] @ 0x3d8 │ │ ldc2l 0, cr5, [pc, #180] @ 245557c │ │ - ldc2l 10, cr13, [ip, #660] @ 0x294 @ │ │ + ldc2l 10, cr13, [ip, #840] @ 0x348 @ │ │ ldc2l 2, cr2, [ip, #296] @ 0x128 │ │ ldc2l 5, cr13, [lr, #564] @ 0x234 │ │ ldc2l 5, cr2, [ip, #744] @ 0x2e8 │ │ - ldc2l 13, cr5, [sp, #488] @ 0x1e8 │ │ - ldc2l 10, cr13, [ip, #420] @ 0x1a4 @ │ │ + ldc2l 13, cr5, [sp, #668] @ 0x29c │ │ + ldc2l 10, cr13, [ip, #600] @ 0x258 @ │ │ ldc2l 2, cr2, [ip, #56] @ 0x38 │ │ - ldc2l 14, cr5, [ip, #840] @ 0x348 │ │ + ldc2l 14, cr5, [ip, #1020] @ 0x3fc │ │ │ │ 024554e4 : │ │ push {fp, lr} │ │ mov fp, sp │ │ bl 270dbf0 │ │ ldr r2, [pc, #12] @ 2455504 │ │ mov r1, #0 │ │ @@ -1324935,29 +1324935,29 @@ │ │ b 2455780 │ │ nop {0} │ │ nop {0} │ │ andeq r0, r0, r1 │ │ andeq r0, r0, r2 │ │ andeq r0, r0, r3 │ │ andeq r0, r0, r4 │ │ - ldc2l 11, cr13, [sp, #208] @ 0xd0 @ │ │ + ldc2l 11, cr13, [sp, #388] @ 0x184 @ │ │ eorseq r3, r0, r0, asr #6 │ │ eorseq r3, r0, ip, lsr #6 │ │ eorseq r3, r0, r8, lsl r3 │ │ eorseq r3, r0, r4, lsl #6 │ │ ldrshteq r3, [r0], -r0 │ │ vcadd.f32 , q7, q14, #270 │ │ - ldc2l 7, cr13, [ip, #756] @ 0x2f4 │ │ + ldc2l 7, cr13, [ip, #936] @ 0x3a8 │ │ ldc2l 9, cr3, [lr, #340] @ 0x154 @ │ │ ldc2l 11, cr10, [pc, #924] @ 2455e68 @ │ │ - ldc2l 7, cr13, [ip, #260] @ 0x104 │ │ + ldc2l 7, cr13, [ip, #440] @ 0x1b8 │ │ ldc2l 0, cr5, [pc, #636] @ 2455d50 │ │ eorseq r3, r0, r4, ror #3 │ │ ldrsbteq r3, [r0], -r0 │ │ - ldc2l 10, cr13, [sp, #176] @ 0xb0 @ │ │ + ldc2l 10, cr13, [sp, #356] @ 0x164 @ │ │ │ │ 02455adc : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d9} │ │ sub sp, sp, #864 @ 0x360 │ │ @@ -1325521,22 +1325521,22 @@ │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ add r0, sp, #40 @ 0x28 │ │ sub r4, r4, #1 │ │ b 24562bc │ │ - ldc2l 10, cr7, [sp, #688] @ 0x2b0 @ │ │ + ldc2l 10, cr7, [sp, #868] @ 0x364 @ │ │ cmneq pc, #84, 22 @ 0x15000 │ │ eorseq r2, r0, r0, lsr #29 │ │ eorseq r2, r0, ip, lsl #29 │ │ eorseq r2, r0, r8, ror lr │ │ eorseq r2, r0, r4, ror #28 │ │ ldc2l 4, cr13, [fp, #928] @ 0x3a0 │ │ - ldc2l 3, cr13, [ip, #164] @ 0xa4 │ │ + ldc2l 3, cr13, [ip, #344] @ 0x158 │ │ cmneq pc, #136, 20 @ 0x88000 │ │ eorseq r2, r0, r0, lsl #28 │ │ ldc2l 7, cr15, [fp, #92] @ 0x5c │ │ eorseq r2, r0, r0, asr #27 │ │ eorseq r2, r0, ip, lsr #27 │ │ ldc2l 14, cr6, [lr, #992] @ 0x3e0 │ │ ldc2l 3, cr11, [lr, #160] @ 0xa0 │ │ @@ -1325555,17 +1325555,17 @@ │ │ ldc2l 10, cr6, [lr, #352] @ 0x160 @ │ │ ldc2l 14, cr10, [lr, #544] @ 0x220 │ │ ldc2l 10, cr6, [lr, #96] @ 0x60 @ │ │ ldc2l 14, cr10, [lr, #288] @ 0x120 │ │ ldc2l 9, cr6, [lr, #192] @ 0xc0 @ │ │ ldc2l 13, cr10, [lr, #576] @ 0x240 │ │ ldc2l 10, cr1, [ip, #540] @ 0x21c @ │ │ - ldc2l 15, cr12, [ip, #228] @ 0xe4 │ │ - ldc2l 7, cr9, [ip, #456] @ 0x1c8 │ │ - ldc2l 2, cr7, [sp, #864] @ 0x360 │ │ + ldc2l 15, cr12, [ip, #408] @ 0x198 │ │ + ldc2l 7, cr9, [ip, #636] @ 0x27c │ │ + ldc2l 3, cr7, [sp, #20] │ │ │ │ 02456454 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #180 @ 0xb4 │ │ mov sl, r3 │ │ mov r8, r2 │ │ @@ -1325915,55 +1325915,55 @@ │ │ eorseq r2, r0, r0, ror r5 │ │ cmneq pc, #224, 2 @ 0x38 │ │ cmneq pc, #48, 4 │ │ cmneq pc, #32, 4 │ │ cmneq pc, #164, 2 @ 0x29 │ │ eorseq r2, r0, ip, lsl r5 │ │ cmneq pc, #208, 2 @ 0x34 │ │ - ldc2l 1, cr5, [sp, #368] @ 0x170 │ │ + ldc2l 1, cr5, [sp, #548] @ 0x224 │ │ ldc2l 4, cr3, [ip, #628] @ 0x274 │ │ - ldc2l 9, cr12, [ip, #338] @ 0x152 @ │ │ + ldc2l 9, cr12, [ip, #428] @ 0x1ac @ │ │ ldc2l 12, cr6, [lr, #616] @ 0x268 │ │ - ldc2l 15, cr8, [ip, #956] @ 0x3bc │ │ + ldc2l 0, cr9, [ip, #112] @ 0x70 │ │ ldc2l 2, cr0, [pc, #176] @ 2456aac │ │ cmneq pc, #24, 30 @ 0x60 │ │ - ldc2l 1, cr5, [sp, #16] │ │ + ldc2l 1, cr5, [sp, #196] @ 0xc4 │ │ cmneq pc, #240 @ 0xf0 │ │ - ldc2l 15, cr4, [sp, #288] @ 0x120 │ │ + ldc2l 15, cr4, [sp, #468] @ 0x1d4 │ │ cmneq pc, #124 @ 0x7c │ │ cmneq pc, #108 @ 0x6c │ │ cmneq pc, #12 │ │ cmneq pc, #224, 30 @ 0x380 │ │ eorseq r2, r0, r8, asr r3 │ │ cmneq pc, #188, 30 @ 0x2f0 │ │ eorseq r2, r0, ip, ror r2 │ │ eorseq r2, r0, r4, ror #8 │ │ cmneq pc, #12, 2 │ │ - ldc2l 0, cr3, [sp, #332] @ 0x14c │ │ - ldc2l 8, cr12, [ip, #996] @ 0x3e4 │ │ + ldc2l 0, cr3, [sp, #512] @ 0x200 │ │ + ldc2l 9, cr12, [ip, #76] @ 0x4c @ │ │ cmneq pc, #216 @ 0xd8 │ │ ldrshteq r2, [r0], -r4 │ │ - ldc2l 13, cr10, [sp, #692] @ 0x2b4 │ │ + ldc2l 13, cr10, [sp, #872] @ 0x368 │ │ cmneq pc, #48, 30 @ 0xc0 │ │ cmneq pc, #216, 28 @ 0xd80 │ │ ldc2l 1, cr0, [pc, #800] @ 2456d70 │ │ - ldc2l 14, cr2, [sp, #748] @ 0x2ec │ │ - ldc2l 15, cr8, [ip, #300] @ 0x12c │ │ + ldc2l 14, cr2, [sp, #928] @ 0x3a0 │ │ + ldc2l 15, cr8, [ip, #480] @ 0x1e0 │ │ cmneq pc, #144, 28 @ 0x900 │ │ - ldc2l 14, cr8, [ip, #108] @ 0x6c │ │ + ldc2l 14, cr8, [ip, #288] @ 0x120 │ │ ldc2l 0, cr0, [pc, #352] @ 2456bc4 │ │ cmneq pc, #36, 28 @ 0x240 │ │ cmneq pc, #12, 28 @ 0xc0 │ │ ldc2l 0, cr3, [ip, #948] @ 0x3b4 │ │ - ldc2l 5, cr12, [ip, #996] @ 0x3e4 │ │ + ldc2l 6, cr12, [ip, #152] @ 0x98 │ │ vcadd.f32 q11, q15, q15, #270 │ │ - ldc2l 13, cr4, [sp, #384] @ 0x180 │ │ - ldc2l 13, cr8, [ip, #780] @ 0x30c │ │ + ldc2l 13, cr4, [sp, #564] @ 0x234 │ │ + ldc2l 13, cr8, [ip, #960] @ 0x3c0 │ │ ldc2l 0, cr0, [pc] @ 2456a84 │ │ - ldc2l 12, cr4, [sp, #832] @ 0x340 │ │ + ldc2l 12, cr4, [sp, #1012] @ 0x3f4 │ │ │ │ 02456a84 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ mov r4, r1 │ │ ldr r1, [fp, #8] │ │ @@ -1326060,15 +1326060,15 @@ │ │ bl 270d1e0 │ │ ldr r0, [r5] │ │ bl 270b460 │ │ mov r0, #6 │ │ mov r1, #0 │ │ bl 270f2d0 │ │ bl 2707fc0 │ │ - ldc2l 1, cr6, [ip, #780] @ 0x30c │ │ + ldc2l 1, cr6, [ip, #960] @ 0x3c0 │ │ eoreq r1, lr, r4, ror #3 │ │ │ │ 02456c1c : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r6, r0 │ │ ldr r0, [pc, #192] @ 2456cf0 │ │ @@ -1326126,15 +1326126,15 @@ │ │ cmneq pc, #156, 20 @ 0x9c000 │ │ eorseq r1, r0, r4, lsl #28 │ │ ldrhteq r1, [r0], -r4 │ │ eorseq r1, r0, r8, lsl #27 │ │ cmneq pc, #80, 20 @ 0x50000 │ │ cmneq pc, #56, 20 @ 0x38000 │ │ cmneq pc, #32, 20 @ 0x20000 │ │ - ldc2l 10, cr10, [ip, #256] @ 0x100 @ │ │ + ldc2l 10, cr10, [ip, #436] @ 0x1b4 @ │ │ │ │ 02456d18 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #428 @ 0x1ac │ │ sub sp, sp, #4096 @ 0x1000 │ │ ldr r2, [pc, #3148] @ 245797c │ │ @@ -1326924,61 +1326924,61 @@ │ │ mov r3, #80 @ 0x50 │ │ bl 270f2f0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ cmneq pc, #192, 18 @ 0x300000 │ │ cmneq pc, #168, 18 @ 0x2a0000 │ │ - ldc2l 9, cr0, [sp, #460] @ 0x1cc @ │ │ + ldc2l 10, cr0, [sp, #76] @ 0x4c @ │ │ eorseq r1, r0, r8, lsr #28 │ │ vcadd.f32 d18, d28, d29, #270 │ │ - ldc2l 6, cr12, [ip, #696] @ 0x2b8 │ │ - ldc2l 9, cr10, [ip, #40] @ 0x28 @ │ │ - ldc2l 5, cr4, [ip, #192] @ 0xc0 │ │ + ldc2l 6, cr12, [ip, #876] @ 0x36c │ │ + ldc2l 9, cr10, [ip, #130] @ 0x82 @ │ │ + ldc2l 5, cr4, [ip, #372] @ 0x174 │ │ ldc2l 15, cr9, [lr, #328] @ 0x148 │ │ - ldc2l 7, cr4, [sp, #940] @ 0x3ac │ │ + ldc2l 8, cr4, [sp, #96] @ 0x60 │ │ ldc2l 9, cr15, [lr, #424] @ 0x1a8 @ │ │ - ldc2l 3, cr8, [sp, #756] @ 0x2f4 │ │ + ldc2l 3, cr8, [sp, #936] @ 0x3a8 │ │ ldc2l 15, cr15, [fp, #236] @ 0xec │ │ - ldc2l 9, cr14, [ip, #4] @ │ │ + ldc2l 9, cr14, [ip, #94] @ 0x5e @ │ │ ldc2l 12, cr5, [pc, #164] @ 2457a60 │ │ - ldc2l 5, cr12, [ip, #360] @ 0x168 │ │ - ldc2l 7, cr10, [ip, #768] @ 0x300 │ │ + ldc2l 5, cr12, [ip, #540] @ 0x21c │ │ + ldc2l 7, cr10, [ip, #948] @ 0x3b4 │ │ eorseq r1, r0, r4, lsl ip │ │ ldc2l 6, cr2, [ip, #676] @ 0x2a4 │ │ ldc2l 6, cr2, [ip, #324] @ 0x144 │ │ - ldc2l 3, cr4, [ip, #176] @ 0xb0 │ │ + ldc2l 3, cr4, [ip, #356] @ 0x164 │ │ ldc2l 13, cr9, [lr, #168] @ 0xa8 │ │ ldc2l 7, cr15, [lr, #528] @ 0x210 │ │ ldc2l 13, cr11, [fp, #352] @ 0x160 │ │ - ldc2l 5, cr4, [sp, #716] @ 0x2cc │ │ + ldc2l 5, cr4, [sp, #896] @ 0x380 │ │ ldc2l 12, cr15, [fp, #988] @ 0x3dc │ │ cmneq pc, #128, 10 @ 0x20000000 │ │ - ldc2l 5, cr10, [ip, #544] @ 0x220 │ │ + ldc2l 5, cr10, [ip, #724] @ 0x2d4 │ │ ldc2l 6, cr3, [pc, #848] @ 2457d44 │ │ eorseq r1, r0, r0, ror #19 │ │ ldc2l 4, cr2, [ip, #276] @ 0x114 │ │ - ldc2l 0, cr4, [ip, #640] @ 0x280 │ │ + ldc2l 0, cr4, [ip, #820] @ 0x334 │ │ ldc2l 15, cr3, [lr, #148] @ 0x94 │ │ eorseq r1, r0, ip, asr #16 │ │ ldc2l 4, cr2, [ip, #164] @ 0xa4 │ │ - ldc2l 1, cr4, [ip] │ │ + ldc2l 1, cr4, [ip, #180] @ 0xb4 │ │ ldc2l 10, cr15, [fp, #620] @ 0x26c @ │ │ ldc2l 10, cr9, [lr, #24] @ │ │ ldc2l 10, cr15, [fp, #252] @ 0xfc @ │ │ ldc2l 10, cr15, [fp, #28] @ │ │ ldc2l 7, cr15, [fp, #972] @ 0x3cc │ │ ldc2l 7, cr15, [fp, #748] @ 0x2ec │ │ - ldc2l 15, cr3, [sp, #876] @ 0x36c │ │ - ldc2l 6, cr15, [sp, #256] @ 0x100 │ │ + ldc2l 0, cr4, [sp, #32] │ │ + ldc2l 6, cr15, [sp, #436] @ 0x1b4 │ │ ldc2l 7, cr15, [fp, #284] @ 0x11c │ │ cmneq pc, #252, 30 @ 0x3f0 │ │ - ldc2l 14, cr3, [sp, #900] @ 0x384 │ │ + ldc2l 15, cr3, [sp, #56] @ 0x38 │ │ eorseq r1, r0, r4, lsl #8 │ │ - ldc2l 14, cr3, [sp, #484] @ 0x1e4 │ │ + ldc2l 14, cr3, [sp, #664] @ 0x298 │ │ ldrsbteq r1, [r0], -ip │ │ ldc2l 5, cr15, [fp, #860] @ 0x35c │ │ ldc2l 5, cr15, [fp, #636] @ 0x27c │ │ ldc2l 15, cr14, [lr, #800] @ 0x320 │ │ eorseq r1, r0, r4, lsl #3 │ │ ldc2l 4, cr15, [fp, #1020] @ 0x3fc │ │ cmneq pc, #148, 26 @ 0x2500 │ │ @@ -1327346,26 +1327346,26 @@ │ │ cmneq pc, #140, 16 @ 0x8c0000 │ │ cmneq pc, #116, 16 @ 0x740000 │ │ cmneq pc, #96, 16 @ 0x600000 │ │ cmneq pc, #76, 16 @ 0x4c0000 │ │ cmneq pc, #56, 16 @ 0x380000 │ │ ldc2l 9, cr1, [ip, #10] @ │ │ cmneq pc, #192, 14 @ 0x3000000 │ │ - ldc2l 6, cr3, [ip, #32] │ │ + ldc2l 6, cr3, [ip, #212] @ 0xd4 │ │ cmneq pc, #184, 14 @ 0x2e00000 │ │ ldc2l 0, cr9, [lr, #168] @ 0xa8 │ │ cmneq pc, #176, 14 @ 0x2c00000 │ │ - vcadd.f32 , , , #270 │ │ + ldc2l 8, cr3, [sp, #960] @ 0x3c0 │ │ cmneq pc, #168, 14 @ 0x2a00000 │ │ ldc2l 10, cr14, [lr, #688] @ 0x2b0 @ │ │ cmneq pc, #160, 14 @ 0x2800000 │ │ ldc2l 8, cr15, [fp, #584] @ 0x248 │ │ ldc2l 0, cr15, [fp, #92] @ 0x5c │ │ eorseq r0, r0, r8, asr lr │ │ - ldc2l 6, cr11, [ip, #352] @ 0x160 │ │ + ldc2l 6, cr11, [ip, #532] @ 0x214 │ │ │ │ 02458024 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #256 @ 0x100 │ │ add r4, sp, #1 │ │ mov r1, #255 @ 0xff │ │ @@ -1327542,15 +1327542,15 @@ │ │ bl 270d900 │ │ cmp r0, #0 │ │ bne 24582d4 │ │ mov r0, #1 │ │ bl 27049a0 │ │ mov r0, #0 │ │ bl 27049a0 │ │ - ldc2l 1, cr9, [sp, #224] @ 0xe0 │ │ + ldc2l 1, cr9, [sp, #404] @ 0x194 │ │ │ │ 024582e0 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ cmp r0, #0 │ │ beq 2458314 │ │ ldrb r1, [r0] │ │ @@ -1327593,22 +1327593,22 @@ │ │ add r0, pc, r0 │ │ bl 270ce70 │ │ mov r0, r4 │ │ pop {r4, sl, fp, lr} │ │ b 270ce40 │ │ ldc2l 15, cr6, [lr, #292] @ 0x124 │ │ ldc2l 1, cr2, [pc, #324] @ 24584e8 │ │ - ldc2l 11, cr10, [ip, #804] @ 0x324 @ │ │ + ldc2l 11, cr10, [ip, #984] @ 0x3d8 @ │ │ ldc2l 3, cr15, [fp, #440] @ 0x1b8 │ │ ldc2l 6, cr10, [lr, #708] @ 0x2c4 │ │ ldc2l 15, cr6, [lr, #52] @ 0x34 │ │ - ldc2l 14, cr2, [sp, #632] @ 0x278 │ │ - ldc2l 11, cr10, [ip, #564] @ 0x234 @ │ │ + ldc2l 14, cr2, [sp, #812] @ 0x32c │ │ + ldc2l 11, cr10, [ip, #744] @ 0x2e8 @ │ │ ldc2l 3, cr15, [fp, #200] @ 0xc8 │ │ - ldc2l 15, cr2, [ip, #984] @ 0x3d8 │ │ + ldc2l 0, cr3, [ip, #140] @ 0x8c │ │ │ │ 024583c0 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r5, r1 │ │ mov r6, r0 │ │ @@ -1327682,20 +1327682,20 @@ │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, r4 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldc2l 14, cr10, [fp, #48] @ 0x30 │ │ ldc2l 8, cr4, [lr, #584] @ 0x248 │ │ - ldc2l 10, cr10, [ip, #468] @ 0x1d4 @ │ │ - ldc2l 15, cr12, [ip, #732] @ 0x2dc │ │ + ldc2l 10, cr10, [ip, #648] @ 0x288 @ │ │ + ldc2l 15, cr12, [ip, #912] @ 0x390 │ │ ldc2l 9, cr12, [fp, #448] @ 0x1c0 @ │ │ - ldc2l 10, cr10, [ip, #276] @ 0x114 @ │ │ + ldc2l 10, cr10, [ip, #456] @ 0x1c8 @ │ │ ldc2l 3, cr1, [ip, #828] @ 0x33c │ │ - ldc2l 10, cr10, [ip, #676] @ 0x2a4 @ │ │ + ldc2l 10, cr10, [ip, #856] @ 0x358 @ │ │ ldc2l 5, cr0, [pc, #492] @ 2458708 │ │ ldc2l 13, cr10, [fp, #96] @ 0x60 │ │ │ │ 0245851c : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r0 │ │ @@ -1327759,24 +1327759,24 @@ │ │ bl 270da10 │ │ ldr r0, [pc, #52] @ 245864c │ │ mov r1, #5 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, r4 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - vcadd.f32 d30, d13, d21, #270 │ │ + ldc2l 8, cr14, [sp, #328] @ 0x148 │ │ ldc2l 7, cr4, [lr, #360] @ 0x168 │ │ - ldc2l 9, cr10, [ip, #122] @ 0x7a @ │ │ - ldc2l 14, cr12, [ip, #508] @ 0x1fc │ │ + ldc2l 9, cr10, [ip, #212] @ 0xd4 @ │ │ + ldc2l 14, cr12, [ip, #688] @ 0x2b0 │ │ vcadd.f32 d28, d27, d24, #270 │ │ - ldc2l 9, cr10, [ip, #26] @ │ │ + ldc2l 9, cr10, [ip, #116] @ 0x74 @ │ │ ldc2l 2, cr1, [ip, #604] @ 0x25c │ │ - ldc2l 9, cr10, [ip, #226] @ 0xe2 @ │ │ + ldc2l 9, cr10, [ip, #316] @ 0x13c @ │ │ ldc2l 4, cr0, [pc, #268] @ 245875c │ │ - ldc2l 7, cr14, [sp, #340] @ 0x154 │ │ + ldc2l 7, cr14, [sp, #520] @ 0x208 │ │ │ │ 02458650 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d9} │ │ sub sp, sp, #192 @ 0xc0 │ │ @@ -1328777,36 +1328777,36 @@ │ │ ldr r0, [pc, #4068] @ 245a5d8 │ │ movw r3, #1190 @ 0x4a6 │ │ ldr r2, [pc, #4064] @ 245a5dc │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ b 2459508 │ │ - ldc2l 8, cr12, [sp, #712] @ 0x2c8 │ │ + ldc2l 8, cr12, [sp, #892] @ 0x37c │ │ cmneq pc, #176 @ 0xb0 │ │ cmneq pc, #156 @ 0x9c │ │ cmneq r2, #224, 26 @ 0x3800 │ │ @ instruction: 0x03b8fe70 │ │ cmneq pc, #88 @ 0x58 │ │ cmneq r0, #188, 16 @ 0xbc0000 @ │ │ biceq ip, r5, #92, 30 @ 0x170 │ │ - ldc2l 15, cr2, [sp, #116] @ 0x74 │ │ + ldc2l 15, cr2, [sp, #296] @ 0x128 │ │ cmneq pc, #208, 30 @ 0x340 │ │ cmneq r3, #92, 18 @ 0x170000 │ │ ldc2l 13, cr1, [pc, #436] @ 24597f0 │ │ ldc2l 12, cr7, [pc, #44] @ 245966c │ │ cmneq pc, #120, 30 @ 0x1e0 │ │ @ instruction: 0x03b8af48 │ │ ldc2l 12, cr1, [pc, #980] @ 2459a20 │ │ ldc2l 11, cr7, [pc, #588] @ 245989c @ │ │ ldc2l 12, cr1, [pc, #788] @ 2459968 │ │ ldc2l 11, cr7, [pc, #396] @ 24597e4 @ │ │ - ldc2l 2, cr14, [sp, #188] @ 0xbc │ │ + ldc2l 2, cr14, [sp, #368] @ 0x170 │ │ ldc2l 11, cr7, [pc, #204] @ 245972c @ │ │ - ldc2l 2, cr14, [sp, #28] │ │ + ldc2l 2, cr14, [sp, #208] @ 0xd0 │ │ ldc2l 11, cr7, [pc, #44] @ 2459694 @ │ │ ldc2l 10, cr12, [fp, #272] @ 0x110 @ │ │ ldr r0, [pc, #3984] @ 245a600 │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ movw r0, #10000 @ 0x2710 │ │ cmp r1, r0 │ │ @@ -1328974,15 +1328974,15 @@ │ │ ldr r1, [pc, #3812] @ 245a7ec │ │ add r0, sp, #90 @ 0x5a │ │ mov r2, #15 │ │ mov r3, #8 │ │ add r1, pc, r1 │ │ b 245a140 │ │ @ instruction: 0x03b8fc48 │ │ - ldc2l 13, cr12, [ip, #524] @ 0x20c │ │ + ldc2l 13, cr12, [ip, #704] @ 0x2c0 │ │ ldc2l 10, cr7, [pc, #668] @ 2459bc4 @ │ │ ldc2l 8, cr2, [lr, #968] @ 0x3c8 │ │ ldc2l 11, cr1, [pc, #200] @ 24599f8 @ │ │ cmneq pc, #176, 26 @ 0x2c00 │ │ eorseq r0, r0, r0, lsl #6 │ │ streq r0, [r4], #-3688 @ 0xfffff198 │ │ ldc2l 9, cr12, [fp, #144] @ 0x90 @ │ │ @@ -1329086,15 +1329086,15 @@ │ │ bl 270e100 │ │ ldr r0, [pc, #3784] @ 245a994 │ │ mov r1, #1 │ │ str r1, [r6] │ │ add r0, pc, r0 │ │ b 245d554 │ │ cmneq r2, #152, 26 @ 0x2600 │ │ - ldc2l 1, cr12, [sp, #60] @ 0x3c │ │ + ldc2l 1, cr12, [sp, #240] @ 0xf0 │ │ ldr r1, [pc, #4080] @ 245aad8 │ │ movw r0, #5000 @ 0x1388 │ │ ldr r1, [pc, r1] │ │ cmp r1, r0 │ │ bne 2459b54 │ │ ldr r0, [sp, #36] @ 0x24 │ │ bl 270d2b0 │ │ @@ -1329375,15 +1329375,15 @@ │ │ mov r2, r5 │ │ movw r3, #1337 @ 0x539 │ │ bl 270da30 │ │ ldr r1, [fp, #-56] @ 0xffffffc8 │ │ mov r2, r0 │ │ b 2459f20 │ │ ldc2l 6, cr5, [pc, #8] @ 2459f6c │ │ - ldc2l 4, cr4, [sp, #968] @ 0x3c8 │ │ + ldc2l 5, cr4, [sp, #124] @ 0x7c │ │ ldr r0, [pc, #3996] @ 245af08 │ │ mov r1, #0 │ │ ldr ip, [pc, #3992] @ 245af0c │ │ add r0, pc, r0 │ │ add ip, pc, ip │ │ ldr r2, [r0, r4, lsl #2] │ │ ldr r3, [ip, r4, lsl #2] │ │ @@ -1329398,25 +1329398,25 @@ │ │ add r0, pc, r0 │ │ ldr r0, [r0, r4, lsl #2] │ │ cmp r0, #0 │ │ bne 245a12c │ │ str r4, [fp, #-56] @ 0xffffffc8 │ │ b 245a11c │ │ cmneq pc, #168, 14 @ 0x2a00000 │ │ - ldc2l 4, cr4, [sp, #760] @ 0x2f8 │ │ + ldc2l 4, cr4, [sp, #940] @ 0x3ac │ │ @ instruction: 0x03bfac34 │ │ cmneq pc, #80, 14 @ 0x1400000 │ │ - ldc2l 6, cr12, [ip, #492] @ 0x1ec │ │ + ldc2l 6, cr12, [ip, #672] @ 0x2a0 │ │ @ instruction: 0x03b8f528 │ │ - ldc2l 6, cr12, [ip, #252] @ 0xfc │ │ + ldc2l 6, cr12, [ip, #432] @ 0x1b0 │ │ @ instruction: 0x03b8f4f4 │ │ cmneq pc, #220, 12 @ 0xdc00000 │ │ - ldc2l 6, cr12, [ip, #88] @ 0x58 │ │ + ldc2l 6, cr12, [ip, #268] @ 0x10c │ │ streq r6, [r3], #-2868 @ 0xfffff4cc │ │ - ldc2l 5, cr12, [ip, #872] @ 0x368 │ │ + ldc2l 6, cr12, [ip, #28] │ │ streq r6, [r3], #-2816 @ 0xfffff500 │ │ cmneq pc, #104, 12 @ 0x6800000 │ │ ldc2l 14, cr3, [lr, #880] @ 0x370 │ │ ldc2l 14, cr3, [lr, #688] @ 0x2b0 │ │ @ instruction: 0x03b99044 │ │ eoreq pc, pc, r0, asr fp @ │ │ ldr r0, [pc, #4076] @ 245aff4 │ │ @@ -1329515,37 +1329515,37 @@ │ │ ldr r8, [pc, #4084] @ 245b170 │ │ add sl, pc, sl │ │ str r0, [sp, #16] │ │ add r8, pc, r8 │ │ b 245a224 │ │ cmneq pc, #220, 10 @ 0x37000000 │ │ cmneq pc, #204, 10 @ 0x33000000 │ │ - ldc2l 4, cr12, [ip, #924] @ 0x39c │ │ + ldc2l 5, cr12, [ip, #80] @ 0x50 │ │ ldc2l 2, cr7, [pc, #60] @ 245a1d8 │ │ ldc2l 3, cr5, [pc, #744] @ 245a488 │ │ @ instruction: 0x03b8f390 │ │ @ instruction: 0x03b8f368 │ │ biceq ip, r5, #144, 8 @ 0x90000000 │ │ @ instruction: 0x03b8f320 │ │ biceq ip, r5, #56, 8 @ 0x38000000 │ │ - ldc2l 3, cr2, [sp, #932] @ 0x3a4 │ │ + ldc2l 4, cr2, [sp, #88] @ 0x58 │ │ cmneq pc, #156, 8 @ 0x9c000000 │ │ cmneq r3, #40, 28 @ 0x280 │ │ cmneq pc, #116, 8 @ 0x74000000 │ │ cmneq pc, #112, 8 @ 0x70000000 │ │ @ instruction: 0x03b8a43c │ │ ldc2l 0, cr7, [pc, #780] @ 245a4dc │ │ ldc2l 1, cr1, [pc, #932] @ 245a578 │ │ cmneq r3, #144, 26 @ 0x2400 │ │ ldc2l 1, cr1, [pc, #708] @ 245a4a0 │ │ cmneq r3, #88, 26 @ 0x1600 │ │ - ldc2l 7, cr13, [sp, #108] @ 0x6c │ │ - ldc2l 6, cr13, [sp, #972] @ 0x3cc │ │ + ldc2l 7, cr13, [sp, #288] @ 0x120 │ │ + ldc2l 7, cr13, [sp, #128] @ 0x80 │ │ ldc2l 14, cr9, [fp, #24] │ │ - ldc2l 1, cr12, [ip, #368] @ 0x170 │ │ + ldc2l 1, cr12, [ip, #548] @ 0x224 │ │ ldr r1, [pc, #3968] @ 245b174 │ │ mov r0, r6 │ │ add r1, pc, r1 │ │ mov r2, #15 │ │ mov r3, #9 │ │ bl 270d9e0 │ │ ldr r1, [pc, #4076] @ 245b1f8 │ │ @@ -1329676,15 +1329676,15 @@ │ │ add r2, pc, r2 │ │ bl 270da30 │ │ rsb r0, r0, r0, lsl #4 │ │ sub r1, fp, #113 @ 0x71 │ │ add r1, r1, r0 │ │ mov r0, r6 │ │ b 245c484 │ │ - ldc2l 2, cr2, [sp, #500] @ 0x1f4 │ │ + ldc2l 2, cr2, [sp, #680] @ 0x2a8 │ │ cmneq pc, #60, 6 @ 0xf0000000 │ │ streq r0, [r4], #-1004 @ 0xfffffc14 │ │ cmneq r4, #68, 6 @ 0x10000001 │ │ cmneq r2, #20, 8 @ 0x14000000 │ │ cmneq pc, #236, 4 @ 0xc000000e │ │ ldc2l 10, cr9, [fp, #468] @ 0x1d4 @ │ │ ldc2l 15, cr6, [pc, #156] @ 245a4d4 │ │ @@ -1329745,15 +1329745,15 @@ │ │ add r1, pc, r1 │ │ add r7, pc, r7 │ │ b 245a76c │ │ sub r6, r7, #1 │ │ mov sl, r7 │ │ mov r8, #0 │ │ b 245a570 │ │ - ldc2l 6, cr11, [sp, #988] @ 0x3dc │ │ + ldc2l 7, cr11, [sp, #144] @ 0x90 │ │ ldc2l 14, cr6, [pc, #540] @ 245a750 │ │ cmneq r2, #212, 4 @ 0x4000000d │ │ ldc2l 9, cr9, [fp, #194] @ 0xc2 @ │ │ ldc2l 14, cr6, [pc, #76] @ 245a58c │ │ ldr r0, [pc, #3936] @ 245b4a4 │ │ mov r1, r8 │ │ ldr r2, [pc, #3932] @ 245b4a8 │ │ @@ -1329922,15 +1329922,15 @@ │ │ ldc2l 11, cr6, [pc, #364] @ 245a944 @ │ │ cmneq r2, #220, 30 @ 0x370 │ │ ldc2l 6, cr9, [fp, #436] @ 0x1b4 │ │ ldc2l 11, cr6, [pc, #124] @ 245a860 @ │ │ cmneq r2, #160, 30 @ 0x280 │ │ cmneq pc, #136, 28 @ 0x880 │ │ cmneq pc, #124, 28 @ 0x7c0 │ │ - ldc2l 11, cr15, [ip, #508] @ 0x1fc @ │ │ + ldc2l 11, cr15, [ip, #688] @ 0x2b0 @ │ │ ldr r0, [pc, #3992] @ 245b790 │ │ mov r1, r4 │ │ ldr r5, [pc, #3988] @ 245b794 │ │ movw r3, #2373 @ 0x945 │ │ add r0, pc, r0 │ │ add r5, pc, r5 │ │ mov r2, r5 │ │ @@ -1330010,33 +1330010,33 @@ │ │ str r6, [r0, r4, lsl #2] │ │ ldr r0, [pc, #4060] @ 245b918 │ │ str r4, [fp, #-56] @ 0xffffffc8 │ │ add r0, pc, r0 │ │ str r1, [r0, r4, lsl #2] │ │ mov r0, r4 │ │ b 245aa40 │ │ - ldc2l 13, cr11, [ip, #268] @ 0x10c │ │ + ldc2l 13, cr11, [ip, #448] @ 0x1c0 │ │ ldc2l 10, cr6, [pc, #428] @ 245ab04 @ │ │ @ instruction: 0x03b8ebf4 │ │ ldc2l 4, cr7, [lr, #1016] @ 0x3f8 │ │ ldc2l 10, cr6, [pc, #220] @ 245aa40 @ │ │ cmneq pc, #192, 26 @ 0x3000 │ │ ldc2l 5, cr9, [fp, #332] @ 0x14c │ │ ldc2l 9, cr6, [pc, #502] @ 245ab66 @ │ │ cmneq r0, #4, 12 @ 0x400000 │ │ ldc2l 11, cr4, [pc, #488] @ 245ab60 @ │ │ ldc2l 9, cr6, [pc, #390] @ 245ab02 @ │ │ biceq fp, r5, #132, 24 @ 0x8400 │ │ - ldc2l 10, cr3, [sp, #392] @ 0x188 @ │ │ + ldc2l 10, cr3, [sp, #572] @ 0x23c @ │ │ @ instruction: 0x03bfa1cc │ │ ldc2l 5, cr3, [lr, #448] @ 0x1c0 │ │ ldc2l 9, cr6, [pc, #126] @ 245aa0e @ │ │ @ instruction: 0x03b98700 │ │ eoreq pc, pc, r4, lsl r2 @ │ │ - ldc2l 4, cr11, [sp, #536] @ 0x218 │ │ + ldc2l 4, cr11, [sp, #716] @ 0x2cc │ │ ldr r0, [pc, #3964] @ 245b91c │ │ mov r5, sl │ │ ldr sl, [pc, #3960] @ 245b920 │ │ mov r1, r4 │ │ add r0, pc, r0 │ │ movw r3, #2376 @ 0x948 │ │ add sl, pc, sl │ │ @@ -1330110,16 +1330110,16 @@ │ │ str r4, [fp, #-56] @ 0xffffffc8 │ │ add r0, pc, r0 │ │ add r0, r0, r4, lsl #3 │ │ vstr d8, [r0] │ │ mov r0, r4 │ │ b 245ab90 │ │ cmneq pc, #120, 24 @ 0x7800 │ │ - ldc2l 10, cr5, [ip, #924] @ 0x39c @ │ │ - ldc2l 3, cr9, [ip, #932] @ 0x3a4 │ │ + ldc2l 11, cr5, [ip, #80] @ 0x50 @ │ │ + ldc2l 4, cr9, [ip, #88] @ 0x58 │ │ eoreq pc, pc, ip, lsr #3 │ │ ldc2l 0, cr15, [lr, #204] @ 0xcc │ │ vcadd.f32 d27, d11, d4, #270 │ │ cmneq pc, #16, 24 @ 0x1000 │ │ cmneq pc, #248, 22 @ 0x3e000 │ │ cmneq pc, #228, 22 @ 0x39000 │ │ cmneq pc, #224, 22 @ 0x38000 │ │ @@ -1330327,22 +1330327,22 @@ │ │ ldr r6, [pc, r6] │ │ b 245ae90 │ │ ldc2l 6, cr0, [pc, #900] @ 245b1b8 │ │ ldc2l 5, cr6, [pc, #508] @ 245b034 │ │ cmneq r3, #136, 4 @ 0x80000008 │ │ cmneq pc, #236, 16 @ 0xec0000 │ │ cmneq pc, #220, 16 @ 0xdc0000 │ │ - ldc2l 12, cr12, [sp, #204] @ 0xcc │ │ + ldc2l 12, cr12, [sp, #384] @ 0x180 │ │ ldc2l 5, cr6, [pc, #220] @ 245af28 │ │ @ instruction: 0x03b89898 │ │ ldc2l 4, cr11, [fp, #512] @ 0x200 │ │ cmneq pc, #136, 16 @ 0x880000 │ │ @ instruction: 0x03b89854 │ │ cmneq pc, #92, 16 @ 0x5c0000 │ │ - ldc2l 11, cr12, [sp, #812] @ 0x32c @ │ │ + ldc2l 11, cr12, [sp, #992] @ 0x3e0 @ │ │ ldr r0, [pc, #3920] @ 245bdb8 │ │ mov r1, r6 │ │ ldr r2, [pc, #3916] @ 245bdbc │ │ movw r3, #2536 @ 0x9e8 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1330439,15 +1330439,15 @@ │ │ ldr r0, [sp, #32] │ │ add r0, r0, #1 │ │ str r0, [sp, #32] │ │ b 245a204 │ │ ldc2l 1, cr6, [pc, #464] @ 245b1cc │ │ ldc2l 3, cr6, [pc, #796] @ 245b31c │ │ cmneq sl, #224, 2 @ 0x38 @ │ │ - ldc2l 6, cr11, [ip, #536] @ 0x218 │ │ + ldc2l 6, cr11, [ip, #716] @ 0x2cc │ │ ldr r1, [pc, #3548] @ 245bde8 │ │ mov r0, r6 │ │ mov r2, #15 │ │ mov r3, #1 │ │ add r1, pc, r1 │ │ bl 270d9e0 │ │ sub r4, r7, #1 │ │ @@ -1330457,16 +1330457,16 @@ │ │ ldr r1, [pc, #3512] @ 245bdec │ │ str r4, [fp, #-56] @ 0xffffffc8 │ │ add r1, pc, r1 │ │ ldr r6, [r1, r4, lsl #2] │ │ b 245b1e4 │ │ streq r5, [r3], #-2964 @ 0xfffff46c │ │ ldc2l 1, cr6, [pc, #96] @ 245b0ac │ │ - ldc2l 6, cr11, [ip, #200] @ 0xc8 │ │ - ldc2l 6, cr11, [ip, #44] @ 0x2c │ │ + ldc2l 6, cr11, [ip, #380] @ 0x17c │ │ + ldc2l 6, cr11, [ip, #224] @ 0xe0 │ │ @ instruction: 0x03b8e4b4 │ │ sub r1, r5, #1 │ │ str r1, [fp, #-56] @ 0xffffffc8 │ │ ldr r0, [pc, #3468] @ 245bdf0 │ │ movw r3, #2540 @ 0x9ec │ │ ldr r2, [pc, #3464] @ 245bdf4 │ │ add r0, pc, r0 │ │ @@ -1330581,19 +1330581,19 @@ │ │ add r3, pc, r3 │ │ blt 245b930 │ │ ldr r0, [sp, #24] │ │ mov r8, #0 │ │ mov r9, #0 │ │ sub r7, r0, #1 │ │ b 245b280 │ │ - ldc2l 2, cr15, [ip, #236] @ 0xec │ │ + ldc2l 2, cr15, [ip, #416] @ 0x1a0 │ │ ldc2l 11, cr8, [fp, #1008] @ 0x3f0 @ │ │ ldc2l 5, cr15, [fp, #360] @ 0x168 │ │ ldc2l 7, cr8, [lr, #432] @ 0x1b0 │ │ - ldc2l 0, cr5, [sp, #684] @ 0x2ac │ │ + ldc2l 0, cr5, [sp, #864] @ 0x360 │ │ ldc2l 5, cr10, [lr, #128] @ 0x80 │ │ ldr r0, [r3, r6, lsl #2] │ │ clz r2, r9 │ │ mov r1, #0 │ │ lsr r2, r2, #5 │ │ cmp r0, r4 │ │ movwlt r1, #1 │ │ @@ -1330632,18 +1330632,18 @@ │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r3, [pc, #3864] @ 245c210 │ │ mov r9, r8 │ │ add r3, pc, r3 │ │ ldr r4, [r3, r0, lsl #2] │ │ b 245b274 │ │ - ldc2l 9, cr10, [sp, #180] @ 0xb4 @ │ │ - ldc2l 13, cr2, [ip, #1012] @ 0x3f4 │ │ + ldc2l 9, cr10, [sp, #270] @ 0x10e @ │ │ + ldc2l 14, cr2, [ip, #168] @ 0xa8 │ │ ldc2l 6, cr8, [lr, #840] @ 0x348 │ │ - ldc2l 11, cr8, [ip, #948] @ 0x3b4 @ │ │ + ldc2l 12, cr8, [ip, #104] @ 0x68 │ │ sub r1, r5, #1 │ │ movw r0, #5000 @ 0x1388 │ │ mov r8, r7 │ │ cmp r1, r0 │ │ bcc 245b344 │ │ ldr r0, [pc, #3812] @ 245c214 │ │ movw r3, #2585 @ 0xa19 │ │ @@ -1330665,15 +1330665,15 @@ │ │ ldr r6, [r1, r4, lsl #2] │ │ ldr r0, [pc, #3756] @ 245c224 │ │ str r4, [fp, #-56] @ 0xffffffc8 │ │ add r0, pc, r0 │ │ str r7, [r0, r4, lsl #2] │ │ b 245baa0 │ │ ldc2l 12, cr4, [lr, #268] @ 0x10c │ │ - ldc2l 1, cr1, [ip, #348] @ 0x15c │ │ + ldc2l 1, cr1, [ip, #528] @ 0x210 │ │ ldc2l 11, cr0, [lr, #620] @ 0x26c @ │ │ ldc2l 15, cr5, [pc, #908] @ 245b724 │ │ ldc2l 13, cr10, [fp, #696] @ 0x2b8 │ │ ldc2l 15, cr5, [pc, #508] @ 245b59c │ │ cmneq pc, #244, 4 @ 0x4000000f │ │ cmneq r3, #156, 20 @ 0x9c000 │ │ ldr r0, [pc, #3708] @ 245c228 │ │ @@ -1330728,23 +1330728,23 @@ │ │ bgt 245ac14 │ │ ldr r1, [pc, #4016] @ 245c424 │ │ mov r0, r6 │ │ mov r2, #15 │ │ mov r3, #8 │ │ add r1, pc, r1 │ │ b 245a200 │ │ - ldc2l 6, cr12, [sp, #236] @ 0xec │ │ + ldc2l 6, cr12, [sp, #416] @ 0x1a0 │ │ ldc2l 15, cr5, [pc, #252] @ 245b58c │ │ @ instruction: 0x03b892a4 │ │ ldc2l 3, cr10, [lr, #304] @ 0x130 │ │ cmneq pc, #124, 4 @ 0xc0000007 │ │ cmneq pc, #104, 4 @ 0x80000006 │ │ cmneq sl, #4, 26 @ 0x100 │ │ streq r5, [r3], #-1760 @ 0xfffff920 │ │ - ldc2l 5, cr12, [sp, #540] @ 0x21c │ │ + ldc2l 5, cr12, [sp, #720] @ 0x2d0 │ │ ldc2l 14, cr5, [pc, #556] @ 245b6dc │ │ @ instruction: 0x03b891f4 │ │ ldc2l 12, cr10, [fp, #456] @ 0x1c8 │ │ ldc2l 14, cr5, [pc, #268] @ 245b5c8 │ │ cmneq r3, #104, 18 @ 0x1a0000 │ │ @ instruction: 0x03b89190 │ │ cmneq sl, #32, 24 @ 0x2000 │ │ @@ -1330966,22 +1330966,22 @@ │ │ str r4, [r2, r1, lsl #2] │ │ sub r1, r0, #5 │ │ str r1, [fp, #-56] @ 0xffffffc8 │ │ b 245bc98 │ │ ldc2l 9, cr5, [pc, #168] @ 245b8e0 @ │ │ cmneq sl, #212, 18 @ 0x350000 │ │ cmneq pc, #20, 30 @ 0x50 │ │ - ldc2l 2, cr12, [sp, #412] @ 0x19c │ │ + ldc2l 2, cr12, [sp, #592] @ 0x250 │ │ ldc2l 11, cr5, [pc, #428] @ 245b9f4 @ │ │ @ instruction: 0x03b88ecc │ │ ldc2l 9, cr10, [fp, #180] @ 0xb4 @ │ │ ldc2l 11, cr5, [pc, #172] @ 245b900 @ │ │ cmneq r3, #84, 12 @ 0x5400000 │ │ cmneq pc, #152, 28 @ 0x980 │ │ - ldc2l 1, cr12, [sp, #940] @ 0x3ac │ │ + ldc2l 2, cr12, [sp, #96] @ 0x60 │ │ ldc2l 10, cr5, [pc, #956] @ 245bc20 @ │ │ @ instruction: 0x03b88e50 │ │ add r6, sp, #90 @ 0x5a │ │ cmp r9, #0 │ │ beq 245b930 │ │ sub r4, r9, #1 │ │ ldr r7, [sp, #24] │ │ @@ -1331077,17 +1331077,17 @@ │ │ mov r2, sl │ │ bl 270e0a0 │ │ mov r6, #0 │ │ str r4, [fp, #-56] @ 0xffffffc8 │ │ str r6, [r5, r4, lsl #2] │ │ mov r0, r4 │ │ b 245c2e0 │ │ - ldc2l 12, cr10, [ip, #668] @ 0x29c │ │ + ldc2l 12, cr10, [ip, #848] @ 0x350 │ │ @ instruction: 0x03b8db50 │ │ - ldc2l 12, cr10, [ip, #552] @ 0x228 │ │ + ldc2l 12, cr10, [ip, #732] @ 0x2dc │ │ ldc2l 4, cr6, [lr, #152] @ 0x98 │ │ ldc2l 9, cr5, [pc, #198] @ 245bad6 @ │ │ cmneq pc, #232, 24 @ 0xe800 │ │ biceq sl, r5, #252, 22 @ 0x3f000 │ │ cmneq r0, #44, 10 @ 0xb000000 │ │ ldr r0, [pc, #3652] @ 245c864 │ │ mov r9, r5 │ │ @@ -1331175,15 +1331175,15 @@ │ │ add r0, r0, r0, lsl #2 │ │ add r6, sp, #90 @ 0x5a │ │ add r2, pc, r2 │ │ str r4, [r2, r1, lsl #2] │ │ sub r1, r0, #5 │ │ str r1, [fp, #-56] @ 0xffffffc8 │ │ b 245c570 │ │ - ldc2l 9, cr2, [sp, #44] @ 0x2c @ │ │ + ldc2l 9, cr2, [sp, #134] @ 0x86 @ │ │ @ instruction: 0x03bf9090 │ │ ldc2l 2, cr12, [fp, #588] @ 0x24c │ │ str r5, [sp, #8] │ │ sub r5, r7, #1 │ │ movw r0, #10000 @ 0x2710 │ │ cmp r5, r0 │ │ str r5, [fp, #-56] @ 0xffffffc8 │ │ @@ -1331211,16 +1331211,16 @@ │ │ b 245c484 │ │ @ instruction: 0x03b975b0 │ │ eoreq lr, pc, r0, asr #1 │ │ ldc2l 14, cr7, [lr, #16] │ │ eoreq lr, pc, r0, asr #32 │ │ eoreq lr, pc, r0, asr #32 │ │ ldc2l 11, cr14, [fp, #56] @ 0x38 @ │ │ - ldc2l 4, cr2, [ip, #244] @ 0xf4 │ │ - ldc2l 13, cr11, [sp, #636] @ 0x27c │ │ + ldc2l 4, cr2, [ip, #424] @ 0x1a8 │ │ + ldc2l 13, cr11, [sp, #816] @ 0x330 │ │ ldc2l 6, cr5, [pc, #652] @ 245beac │ │ @ instruction: 0x03b88a0c │ │ ldc2l 4, cr10, [fp, #616] @ 0x268 │ │ ldc2l 6, cr5, [pc, #428] @ 245bdd8 │ │ cmneq r3, #140, 2 @ 0x23 │ │ ldr r0, [pc, #3924] @ 245cb88 │ │ movw r3, #2903 @ 0xb57 │ │ @@ -1331317,32 +1331317,32 @@ │ │ ldc2l 7, cr15, [lr, #564] @ 0x234 │ │ ldc2l 6, cr5, [pc, #172] @ 245be54 │ │ cmneq r3, #52, 6 @ 0xd0000000 │ │ ldc2l 10, cr14, [fp, #24] @ │ │ cmneq fp, #72 @ 0x48 │ │ streq lr, [r3], #-2596 @ 0xfffff5dc │ │ cmneq pc, #60, 18 @ 0xf0000 │ │ - ldc2l 12, cr11, [sp, #396] @ 0x18c │ │ + ldc2l 12, cr11, [sp, #576] @ 0x240 │ │ ldc2l 5, cr5, [pc, #412] @ 245bf60 │ │ @ instruction: 0x03b888d0 │ │ ldc2l 6, cr3, [pc, #832] @ 245c10c │ │ ldc2l 5, cr5, [pc, #124] @ 245be4c │ │ cmneq r4, #132, 24 @ 0x8400 │ │ @ instruction: 0x03b8886c │ │ eoreq sp, pc, r4, ror sp @ │ │ eoreq sp, pc, r4, ror sp @ │ │ - ldc2l 3, cr4, [sp, #844] @ 0x34c │ │ + ldc2l 4, cr4, [sp] │ │ ldc2l 10, cr7, [lr, #408] @ 0x198 @ │ │ ldc2l 0, cr4, [lr, #12] │ │ ldc2l 11, cr13, [fp, #280] @ 0x118 @ │ │ cmneq sl, #220, 2 @ 0x37 │ │ ldc2l 4, cr15, [lr, #836] @ 0x344 │ │ ldc2l 3, cr5, [pc, #444] @ 245bfb8 │ │ cmneq r3, #120 @ 0x78 │ │ - ldc2l 2, cr4, [sp, #876] @ 0x36c │ │ + ldc2l 3, cr4, [sp, #32] │ │ cmneq fp, #148, 26 @ 0x2500 │ │ ldc2l 13, cr5, [lr, #504] @ 0x1f8 │ │ ldc2l 2, cr5, [pc, #748] @ 245c0fc │ │ cmneq pc, #64, 12 @ 0x4000000 │ │ cmneq r0, #152, 28 @ 0x980 │ │ ldc2l 15, cr4, [pc, #1008] @ 245c20c │ │ ldc2l 2, cr5, [pc, #300] @ 245bf4c │ │ @@ -1331596,15 +1331596,15 @@ │ │ cmneq sl, #244, 30 @ 0x3d0 │ │ ldc2l 14, cr4, [pc, #864] @ 245c564 │ │ ldc2l 1, cr5, [pc, #172] @ 245c2b4 │ │ cmneq sl, #84, 30 @ 0x150 │ │ ldc2l 14, cr4, [pc, #640] @ 245c490 │ │ ldc2l 0, cr5, [pc, #972] @ 245c5e0 │ │ cmneq sl, #24, 30 @ 0x60 │ │ - ldc2l 7, cr11, [sp, #636] @ 0x27c │ │ + ldc2l 7, cr11, [sp, #816] @ 0x330 │ │ ldc2l 0, cr5, [pc, #652] @ 245c4ac │ │ @ instruction: 0x03b88400 │ │ cmneq sl, #168, 28 @ 0xa80 │ │ cmneq r4, #216, 14 @ 0x3600000 │ │ ldc2l 11, cr7, [fp, #476] @ 0x1dc @ │ │ ldc2l 0, cr5, [pc, #124] @ 245c2b0 │ │ cmneq r0, #24, 24 @ 0x1800 │ │ @@ -1332199,17 +1332199,17 @@ │ │ bl 270da30 │ │ ldr sl, [pc, #4076] @ 245db5c │ │ mov r4, r0 │ │ mov r5, r9 │ │ add sl, pc, sl │ │ b 245bd88 │ │ streq r4, [r3], #-60 @ 0xffffffc4 │ │ - ldc2l 5, cr1, [ip, #372] @ 0x174 │ │ - ldc2l 3, cr7, [ip, #484] @ 0x1e4 │ │ - ldc2l 0, cr9, [sp, #44] @ 0x2c │ │ + ldc2l 5, cr1, [ip, #552] @ 0x228 │ │ + ldc2l 3, cr7, [ip, #664] @ 0x298 │ │ + ldc2l 0, cr9, [sp, #224] @ 0xe0 │ │ ldc2l 7, cr4, [pc, #620] @ 245ce00 │ │ cmneq r4, #60, 22 @ 0xf000 │ │ ldc2l 12, cr8, [lr, #988] @ 0x3dc │ │ streq sp, [r3], #-2972 @ 0xfffff464 │ │ ldr r0, [pc, #4028] @ 245db60 │ │ mov r1, r5 │ │ ldr r2, [pc, #4024] @ 245db64 │ │ @@ -1332671,15 +1332671,15 @@ │ │ vcmp.f64 d16, d8 │ │ vmrs APSR_nzcv, fpscr │ │ vmovge.f64 d8, d16 │ │ b 245d3a4 │ │ ldc2l 14, cr3, [pc, #688] @ 245d58c │ │ cmneq sl, #44, 30 @ 0xb0 │ │ cmneq pc, #112, 8 @ 0x70000000 │ │ - ldc2l 7, cr10, [sp, #780] @ 0x30c │ │ + ldc2l 7, cr10, [sp, #960] @ 0x3c0 │ │ ldc2l 0, cr4, [pc, #796] @ 245d608 │ │ @ instruction: 0x03b87424 │ │ vldr d8, [sp, #72] @ 0x48 │ │ vcmp.f64 d16, d8 │ │ vmrs APSR_nzcv, fpscr │ │ bpl 245da78 │ │ movw r0, #9999 @ 0x270f │ │ @@ -1332695,15 +1332695,15 @@ │ │ vmrs APSR_nzcv, fpscr │ │ vmovls.f64 d8, d16 │ │ b 245d14c │ │ ldc2l 14, cr8, [fp, #712] @ 0x2c8 │ │ ldc2l 0, cr4, [pc, #524] @ 245d548 │ │ cmneq r3, #172, 22 @ 0x2b000 │ │ cmneq pc, #240, 6 @ 0xc0000003 │ │ - ldc2l 7, cr10, [sp, #268] @ 0x10c │ │ + ldc2l 7, cr10, [sp, #448] @ 0x1c0 │ │ ldc2l 0, cr4, [pc, #284] @ 245d468 │ │ @ instruction: 0x03b873a8 │ │ ldr r8, [pc, #3876] @ 245e278 │ │ mov r1, r5 │ │ ldr r6, [pc, #3872] @ 245e27c │ │ movw r3, #3177 @ 0xc69 │ │ add r8, pc, r8 │ │ @@ -1332781,30 +1332781,30 @@ │ │ mov r1, #0 │ │ add r8, pc, r8 │ │ mov sl, r9 │ │ add r0, pc, r0 │ │ str r1, [r0, r2, lsl #2] │ │ b 245b46c │ │ ldc2l 5, cr6, [lr, #552] @ 0x228 │ │ - ldc2l 7, cr8, [sp, #744] @ 0x2e8 │ │ + ldc2l 7, cr8, [sp, #924] @ 0x39c │ │ ldc2l 11, cr2, [lr, #60] @ 0x3c @ │ │ cmp r7, #1 │ │ blt 245d54c │ │ sub r4, r7, #1 │ │ movw r0, #10001 @ 0x2711 │ │ cmp r7, r0 │ │ str r4, [fp, #-56] @ 0xffffffc8 │ │ bcs 245d4e8 │ │ ldr r1, [pc, #3784] @ 245e38c │ │ mov r0, #0 │ │ str r4, [fp, #-56] @ 0xffffffc8 │ │ add r1, pc, r1 │ │ str r0, [r1, r4, lsl #2] │ │ b 245d53c │ │ - ldc2l 7, cr8, [sp, #220] @ 0xdc │ │ + ldc2l 7, cr8, [sp, #400] @ 0x190 │ │ ldc2l 14, cr3, [pc, #796] @ 245d7fc │ │ cmneq r4, #104, 4 @ 0x80000006 │ │ ldc2l 4, cr8, [lr, #140] @ 0x8c │ │ streq sp, [r3], #-708 @ 0xfffffd3c │ │ ldr r0, [pc, #3744] @ 245e390 │ │ mov r1, r4 │ │ ldr r5, [pc, #3740] @ 245e394 │ │ @@ -1332845,19 +1332845,19 @@ │ │ mov r8, r7 │ │ b 2459b84 │ │ ldc2l 5, cr12, [lr, #48] @ 0x30 │ │ ldc2l 14, cr3, [pc, #172] @ 245d63c │ │ biceq r2, r6, #44, 26 @ 0xb00 │ │ ldc2l 9, cr6, [fp, #98] @ 0x62 @ │ │ cmneq r1, #112, 4 @ │ │ - ldc2l 0, cr9, [ip, #568] @ 0x238 │ │ + ldc2l 0, cr9, [ip, #748] @ 0x2ec │ │ ldc2l 13, cr3, [pc, #668] @ 245d840 │ │ streq r3, [r3], #-1440 @ 0xfffffa60 │ │ vcadd.f32 q11, , , #270 │ │ - ldc2l 5, cr8, [sp, #812] @ 0x32c │ │ + ldc2l 5, cr8, [sp, #992] @ 0x3e0 │ │ cmneq r1, #240, 2 @ 0x3c @ │ │ ldc2l 12, cr3, [pc, #908] @ 245d944 │ │ cmneq r4, #136 @ 0x88 │ │ ldc2l 14, cr13, [lr, #36] @ 0x24 │ │ ldc2l 12, cr3, [pc, #668] @ 245d860 │ │ cmneq r3, #176, 18 @ 0x2c0000 │ │ ldc2l 0, cr8, [lr, #684] @ 0x2ac │ │ @@ -1332979,15 +1332979,15 @@ │ │ vstr d9, [r0] │ │ mov r0, r4 │ │ b 245d808 │ │ ldc2l 12, cr3, [pc, #188] @ 245d864 │ │ cmneq r1, #176 @ 0xb0 @ │ │ streq sp, [r3], #-60 @ 0xffffffc4 │ │ cmneq r1, #112 @ 0x70 @ │ │ - ldc2l 12, cr14, [fp, #892] @ 0x37c │ │ + ldc2l 13, cr14, [fp, #48] @ 0x30 │ │ ldc2l 12, cr1, [pc, #984] @ 245db94 │ │ ldc2l 11, cr3, [pc, #236] @ 245d8ac @ │ │ ldr r0, [pc, #3112] @ 245e3ec │ │ mov r1, r4 │ │ ldr r5, [pc, #3108] @ 245e3f0 │ │ movw r3, #2666 @ 0xa6a │ │ add r0, pc, r0 │ │ @@ -1333040,24 +1333040,24 @@ │ │ add r1, pc, r1 │ │ str r0, [r1, r4, lsl #2] │ │ add r0, r6, r4, lsl #3 │ │ vstr d8, [r0] │ │ mov r0, r4 │ │ b 245d958 │ │ cmneq fp, #136, 10 @ 0x22000000 │ │ - ldc2l 11, cr0, [sp, #824] @ 0x338 @ │ │ + ldc2l 11, cr0, [sp, #1004] @ 0x3ec @ │ │ cmneq pc, #132, 28 @ 0x840 │ │ - ldc2l 11, cr0, [sp, #632] @ 0x278 @ │ │ + ldc2l 11, cr0, [sp, #812] @ 0x32c @ │ │ ldc2l 10, cr3, [pc, #860] @ 245dc14 @ │ │ @ instruction: 0x03bf7310 │ │ cmneq pc, #44, 28 @ 0x2c0 │ │ - ldc2l 13, cr8, [ip, #408] @ 0x198 │ │ + ldc2l 13, cr8, [ip, #588] @ 0x24c │ │ ldc2l 10, cr3, [pc, #508] @ 245dac4 @ │ │ streq r3, [r3], #-640 @ 0xfffffd80 │ │ - ldc2l 13, cr8, [ip, #152] @ 0x98 │ │ + ldc2l 13, cr8, [ip, #332] @ 0x14c │ │ ldc2l 10, cr3, [pc, #252] @ 245d9d0 @ │ │ streq r3, [r3], #-584 @ 0xfffffdb8 │ │ cmneq pc, #176, 26 @ 0x2c00 │ │ ldr r0, [pc, #2860] @ 245e40c │ │ mov r1, r4 │ │ ldr r5, [pc, #2856] @ 245e410 │ │ movw r3, #2667 @ 0xa6b │ │ @@ -1333110,18 +1333110,18 @@ │ │ add r0, pc, r0 │ │ add r2, r0, r1, lsl #3 │ │ ldr r0, [fp, #12] │ │ mov r1, r3 │ │ bl 270e100 │ │ str r4, [fp, #-56] @ 0xffffffc8 │ │ b 245da30 │ │ - ldc2l 12, cr8, [ip, #876] @ 0x36c │ │ + ldc2l 13, cr8, [ip, #32] │ │ ldc2l 10, cr3, [pc, #12] @ 245d9d4 @ │ │ @ instruction: 0x03b8bb84 │ │ - ldc2l 12, cr8, [ip, #636] @ 0x27c │ │ + ldc2l 12, cr8, [ip, #816] @ 0x330 │ │ ldc2l 9, cr3, [pc, #398] @ 245db62 @ │ │ @ instruction: 0x03b8bb4c │ │ cmneq pc, #52, 26 @ 0xd00 │ │ ldr r0, [pc, #2640] @ 245e430 │ │ movw r3, #2675 @ 0xa73 │ │ ldr r5, [pc, #2636] @ 245e434 │ │ add r0, pc, r0 │ │ @@ -1333154,15 +1333154,15 @@ │ │ ldc2l 9, cr3, [pc, #238] @ 245db46 @ │ │ ldc2l 5, cr0, [lr, #480] @ 0x1e0 │ │ ldc2l 9, cr3, [pc, #142] @ 245daee @ │ │ @ instruction: 0x03b9570c │ │ eoreq ip, pc, r8, lsl r2 @ │ │ cmneq pc, #164, 24 @ 0xa400 │ │ cmneq pc, #144, 24 @ 0x9000 │ │ - ldc2l 10, cr14, [fp, #172] @ 0xac @ │ │ + ldc2l 10, cr14, [fp, #352] @ 0x160 @ │ │ cmneq r0, #208, 8 @ 0xd0000000 │ │ cmneq r1, #68, 26 @ 0x1100 │ │ ldr r0, [fp, #16] │ │ ldr r1, [fp, #28] │ │ bl 270d360 │ │ bl 270db90 │ │ cmp r0, #0 │ │ @@ -1333253,15 +1333253,15 @@ │ │ cmneq r1, #124, 24 @ 0x7c00 │ │ ldc2l 2, cr4, [lr, #440] @ 0x1b8 │ │ ldc2l 7, cr3, [pc, #684] @ 245de98 │ │ cmneq pc, #48, 22 @ 0xc000 │ │ ldc2l 2, cr6, [fp, #700] @ 0x2bc │ │ ldc2l 7, cr3, [pc, #364] @ 245dd64 │ │ streq r2, [r3], #-3888 @ 0xfffff0d0 │ │ - ldc2l 9, cr8, [ip, #364] @ 0x16c @ │ │ + ldc2l 9, cr8, [ip, #454] @ 0x1c6 @ │ │ ldc2l 6, cr3, [pc, #828] @ 245df40 │ │ streq r2, [r3], #-3784 @ 0xfffff138 │ │ ldr r1, [pc, #2112] @ 245e44c │ │ mov sl, r9 │ │ ldr r2, [fp, #12] │ │ add r1, pc, r1 │ │ bl 270e100 │ │ @@ -1333557,15 +1333557,15 @@ │ │ mov r2, r4 │ │ bl 270e0a0 │ │ b 245d54c │ │ cmneq pc, #140, 12 @ 0x8c00000 │ │ cmneq r0, #252, 28 @ 0xfc0 │ │ streq r2, [r3], #-2792 @ 0xfffff518 │ │ cmneq pc, #48, 12 @ 0x3000000 │ │ - ldc2l 4, cr8, [ip, #984] @ 0x3d8 │ │ + ldc2l 5, cr8, [ip, #140] @ 0x8c │ │ ldc2l 2, cr3, [pc, #60] @ 245e100 │ │ eoreq fp, pc, ip, lsr #21 │ │ eoreq fp, pc, ip, lsr #21 │ │ ldr r5, [pc, #1112] @ 245e528 │ │ movw r3, #3196 @ 0xc7c │ │ ldr r4, [pc, #1108] @ 245e52c │ │ ldr r7, [sp, #20] │ │ @@ -1333734,34 +1333734,34 @@ │ │ add r1, pc, r1 │ │ str r6, [r1, r2, lsl #2] │ │ b 245d554 │ │ cmneq r0, #104, 24 @ 0x6800 │ │ ldc2l 1, cr13, [lr, #324] @ 0x144 │ │ ldc2l 15, cr2, [pc, #956] @ 245e738 │ │ cmneq r3, #244, 24 @ 0xf400 │ │ - ldc2l 2, cr8, [ip, #376] @ 0x178 │ │ + ldc2l 2, cr8, [ip, #556] @ 0x22c │ │ ldc2l 15, cr2, [pc, #476] @ 245e564 │ │ cmneq fp, #208, 18 @ 0x340000 │ │ streq r2, [r3], #-1896 @ 0xfffff898 │ │ @ instruction: 0x03b8b0a8 │ │ - ldc2l 1, cr8, [ip, #732] @ 0x2dc │ │ + ldc2l 1, cr8, [ip, #912] @ 0x390 │ │ ldc2l 14, cr2, [pc, #892] @ 245e718 │ │ - ldc2l 1, cr8, [ip, #680] @ 0x2a8 │ │ + ldc2l 1, cr8, [ip, #860] @ 0x35c │ │ @ instruction: 0x03b8b054 │ │ streq r2, [r3], #-1708 @ 0xfffff954 │ │ - ldc2l 10, cr7, [sp, #24] @ │ │ + ldc2l 10, cr7, [sp, #204] @ 0xcc @ │ │ cmneq pc, #232, 2 @ 0x3a │ │ ldc2l 3, cr7, [lr, #508] @ 0x1fc │ │ ldc2l 13, cr2, [pc, #892] @ 245e734 │ │ strhteq fp, [pc], -r8 │ │ cmneq fp, #56, 16 @ 0x380000 │ │ ldc2l 4, cr11, [lr, #400] @ 0x190 │ │ ldc2l 13, cr2, [pc, #524] @ 245e5d4 │ │ biceq r1, r6, #124, 24 @ 0x7c00 │ │ - ldc2l 5, cr7, [sp, #620] @ 0x26c │ │ + ldc2l 5, cr7, [sp, #800] @ 0x320 │ │ ldc2l 13, cr2, [pc, #172] @ 245e480 │ │ cmneq r4, #196 @ 0xc4 │ │ ldc2l 7, cr3, [lr, #600] @ 0x258 │ │ ldc2l 12, cr2, [pc, #844] @ 245e72c │ │ cmneq pc, #80 @ 0x50 │ │ ldc2l 2, cr7, [lr, #172] @ 0xac │ │ ldc2l 12, cr2, [pc, #556] @ 245e618 │ │ @@ -1333773,35 +1333773,35 @@ │ │ cmneq pc, #228, 30 @ 0x390 │ │ ldc2l 1, cr7, [lr, #236] @ 0xec │ │ ldc2l 11, cr2, [pc, #620] @ 245e678 @ │ │ cmneq fp, #252, 10 @ 0x3f000000 │ │ ldc2l 6, cr5, [fp, #268] @ 0x10c │ │ ldc2l 10, cr2, [pc, #956] @ 245e7d4 @ │ │ ldc2l 12, cr0, [pc, #536] @ 245e634 │ │ - ldc2l 11, cr15, [ip, #408] @ 0x198 @ │ │ + ldc2l 11, cr15, [ip, #588] @ 0x24c @ │ │ biceq r7, r5, #112, 26 @ 0x1c00 │ │ biceq r7, r5, #40, 28 @ 0x280 │ │ @ instruction: 0x03bf62c8 │ │ eoreq fp, pc, r0, lsr r3 @ │ │ @ instruction: 0x03b94810 │ │ ldc2l 6, cr15, [sp, #144] @ 0x90 │ │ ldc2l 9, cr2, [pc, #486] @ 245e622 @ │ │ ldrdeq fp, [pc], -r0 @ │ │ @ instruction: 0x03b947b0 │ │ - ldc2l 12, cr7, [ip, #572] @ 0x23c │ │ - ldc2l 5, cr7, [sp, #104] @ 0x68 │ │ + ldc2l 12, cr7, [ip, #752] @ 0x2f0 │ │ + ldc2l 5, cr7, [sp, #284] @ 0x11c │ │ @ instruction: 0x03b8ab30 │ │ strhteq fp, [pc], -ip │ │ ldc2l 13, cr6, [lr, #1004] @ 0x3ec │ │ ldc2l 8, cr2, [pc, #348] @ 245e5b8 │ │ eoreq fp, pc, r0, lsr r1 @ │ │ cmneq fp, #176, 4 │ │ ldc2l 14, cr10, [lr, #992] @ 0x3e0 │ │ biceq r1, r6, #184, 12 @ 0xb800000 │ │ - ldc2l 15, cr6, [sp, #892] @ 0x37c │ │ + ldc2l 0, cr7, [sp, #48] @ 0x30 │ │ ldc2l 7, cr2, [pc, #444] @ 245e630 │ │ cmneq r4, #16, 22 @ 0x4000 │ │ ldc2l 1, cr3, [lr, #888] @ 0x378 │ │ ldc2l 7, cr2, [pc, #108] @ 245e4ec │ │ cmneq pc, #160, 20 @ 0xa0000 │ │ ldc2l 12, cr6, [lr, #540] @ 0x21c │ │ ldc2l 6, cr2, [pc, #924] @ 245e828 │ │ @@ -1333815,63 +1333815,63 @@ │ │ ldc2l 11, cr6, [lr, #652] @ 0x28c @ │ │ ldc2l 6, cr2, [pc, #12] @ 245e4bc │ │ cmneq fp, #92 @ 0x5c │ │ ldc2l 0, cr5, [fp, #668] @ 0x29c │ │ ldc2l 5, cr2, [pc, #332] @ 245e608 │ │ ldc2l 6, cr0, [pc, #936] @ 245e868 │ │ cmneq r0, #68, 2 │ │ - ldc2l 5, cr15, [ip, #808] @ 0x328 │ │ + ldc2l 5, cr15, [ip, #988] @ 0x3dc │ │ biceq r7, r5, #212, 14 @ 0x3500000 │ │ biceq r7, r5, #136, 16 @ 0x880000 │ │ cmneq r0, #184, 2 @ 0x2e │ │ @ instruction: 0x03bf5d2c │ │ mlaeq pc, r8, sp, sl @ │ │ @ instruction: 0x03b94278 │ │ cmneq sl, #188, 4 @ 0xc000000b │ │ streq r1, [r3], #-3216 @ 0xfffff370 │ │ @ instruction: 0x03b8a600 │ │ ldc2l 0, cr15, [sp, #352] @ 0x160 │ │ ldc2l 4, cr2, [pc, #156] @ 245e590 │ │ eoreq sl, pc, r4, lsl #26 │ │ @ instruction: 0x03b941e4 │ │ - ldc2l 6, cr7, [ip, #780] @ 0x30c │ │ + ldc2l 6, cr7, [ip, #960] @ 0x3c0 │ │ ldc2l 1, cr2, [pc, #496] @ 245e6f4 │ │ @ instruction: 0x03b8a564 │ │ - ldc2l 6, cr7, [ip, #552] @ 0x228 │ │ + ldc2l 6, cr7, [ip, #732] @ 0x2dc │ │ cmneq sl, #216, 2 @ 0x36 │ │ streq r1, [r3], #-2964 @ 0xfffff46c │ │ streq fp, [r3], #-1964 @ 0xfffff854 │ │ @ instruction: 0x03bf6190 │ │ @ instruction: 0x03b94708 │ │ ldc2l 10, cr12, [lr, #484] @ 0x1e4 @ │ │ ldc2l 9, cr2, [pc, #46] @ 245e556 @ │ │ cmneq r3, #28, 12 @ 0x1c00000 │ │ ldc2l 13, cr2, [lr, #776] @ 0x308 │ │ ldc2l 2, cr2, [pc, #1020] @ 245e930 │ │ cmneq pc, #104, 12 @ 0x6800000 │ │ ldc2l 13, cr4, [fp, #972] @ 0x3cc │ │ cmneq r0, #140, 28 @ 0x8c0 │ │ ldc2l 3, cr0, [pc, #1000] @ 245e92c │ │ - ldc2l 2, cr15, [ip, #888] @ 0x378 │ │ + ldc2l 3, cr15, [ip, #44] @ 0x2c │ │ biceq r7, r5, #232, 8 @ 0xe8000000 │ │ biceq r7, r5, #124, 22 @ 0x1f000 │ │ eoreq sl, pc, r8, lsr #21 │ │ cmneq sl, #212, 30 @ 0x350 │ │ streq r1, [r3], #-2472 @ 0xfffff658 │ │ @ instruction: 0x03b8a318 │ │ ldc2l 13, cr14, [sp, #496] @ 0x1f0 │ │ ldc2l 1, cr2, [pc, #300] @ 245e694 │ │ eoreq sl, pc, r4, lsr #20 │ │ - ldc2l 3, cr7, [ip, #956] @ 0x3bc │ │ + ldc2l 4, cr7, [ip, #112] @ 0x70 │ │ ldc2l 14, cr1, [pc, #656] @ 245e804 │ │ @ instruction: 0x03b8a28c │ │ - ldc2l 3, cr7, [ip, #728] @ 0x2d8 │ │ + ldc2l 3, cr7, [ip, #908] @ 0x38c │ │ cmneq sl, #4, 30 │ │ streq r1, [r3], #-2236 @ 0xfffff744 │ │ - ldc2l 11, cr6, [sp, #1000] @ 0x3e8 @ │ │ + ldc2l 12, cr6, [sp, #156] @ 0x9c │ │ cmneq sl, #176, 28 @ 0xb00 │ │ │ │ 0245e588 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ @@ -1334055,27 +1334055,27 @@ │ │ ldr r0, [pc, #32] @ 245e864 │ │ add r0, pc, r0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, lr} │ │ b 270ce40 │ │ ldc2l 3, cr6, [lr, #192] @ 0xc0 │ │ ldc2l 12, cr11, [lr, #932] @ 0x3a4 │ │ - ldc2l 7, cr4, [ip, #388] @ 0x184 │ │ + ldc2l 7, cr4, [ip, #568] @ 0x238 │ │ ldc2l 14, cr15, [lr, #668] @ 0x29c │ │ ldc2l 2, cr4, [lr, #292] @ 0x124 │ │ ldc2l 1, cr6, [lr, #928] @ 0x3a0 │ │ - ldc2l 10, cr12, [ip, #280] @ 0x118 @ │ │ - ldc2l 7, cr4, [ip, #212] @ 0xd4 │ │ + ldc2l 10, cr12, [ip, #460] @ 0x1cc @ │ │ + ldc2l 7, cr4, [ip, #392] @ 0x188 │ │ ldc2l 14, cr15, [lr, #492] @ 0x1ec │ │ - ldc2l 11, cr12, [fp, #632] @ 0x278 @ │ │ + ldc2l 11, cr12, [fp, #812] @ 0x32c @ │ │ ldc2l 3, cr10, [lr, #572] @ 0x23c │ │ - ldc2l 7, cr4, [ip, #36] @ 0x24 │ │ - ldc2l 12, cr2, [sp, #68] @ 0x44 │ │ + ldc2l 7, cr4, [ip, #216] @ 0xd8 │ │ + ldc2l 12, cr2, [sp, #248] @ 0xf8 │ │ eoreq ip, ip, ip, rrx │ │ - ldc2l 11, cr2, [sp, #848] @ 0x350 @ │ │ + ldc2l 12, cr2, [sp, #4] │ │ ldc2l 9, cr14, [sp, #458] @ 0x1ca @ │ │ ldc2l 2, cr6, [lr, #688] @ 0x2b0 │ │ │ │ 0245e894 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #268 @ 0x10c │ │ @@ -1334237,30 +1334237,30 @@ │ │ mov r1, r8 │ │ mov r2, r4 │ │ bl 270f370 │ │ b 245eab0 │ │ add r0, sp, #92 @ 0x5c │ │ bl 270d2b0 │ │ b 245ea44 │ │ - ldc2l 11, cr2, [sp, #316] @ 0x13c @ │ │ - ldc2l 13, cr10, [ip, #660] @ 0x294 │ │ - ldc2l 13, cr12, [fp, #504] @ 0x1f8 │ │ - ldc2l 5, cr4, [ip, #372] @ 0x174 │ │ - ldc2l 14, cr6, [ip, #640] @ 0x280 │ │ - ldc2l 9, cr12, [ip, #376] @ 0x178 @ │ │ - ldc2l 11, cr4, [ip, #876] @ 0x36c @ │ │ - ldc2l 5, cr4, [ip, #676] @ 0x2a4 │ │ + ldc2l 11, cr2, [sp, #496] @ 0x1f0 @ │ │ + ldc2l 13, cr10, [ip, #840] @ 0x348 │ │ + ldc2l 13, cr12, [fp, #684] @ 0x2ac │ │ + ldc2l 5, cr4, [ip, #552] @ 0x228 │ │ + ldc2l 14, cr6, [ip, #820] @ 0x334 │ │ + ldc2l 9, cr12, [ip, #466] @ 0x1d2 @ │ │ + ldc2l 12, cr4, [ip, #32] │ │ + ldc2l 5, cr4, [ip, #856] @ 0x358 │ │ ldc2l 8, cr14, [sp, #708] @ 0x2c4 │ │ - ldc2l 8, cr12, [ip, #1008] @ 0x3f0 │ │ + ldc2l 9, cr12, [ip, #82] @ 0x52 @ │ │ ldc2l 7, cr10, [sp, #256] @ 0x100 │ │ - ldc2l 4, cr4, [ip, #948] @ 0x3b4 │ │ + ldc2l 5, cr4, [ip, #104] @ 0x68 │ │ ldc2l 15, cr7, [lr, #1020] @ 0x3fc │ │ eoreq sl, pc, ip, ror #3 │ │ eoreq sl, pc, ip, ror #3 │ │ - ldc2l 9, cr2, [sp, #398] @ 0x18e @ │ │ + ldc2l 9, cr2, [sp, #488] @ 0x1e8 @ │ │ │ │ 0245eb68 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #436 @ 0x1b4 │ │ mov r5, r3 │ │ mov r8, r2 │ │ @@ -1334807,63 +1334807,63 @@ │ │ mov r2, r9 │ │ mov r3, #3 │ │ add r1, pc, r1 │ │ bl 270d9e0 │ │ ldr r1, [pc, #184] @ 245f4bc │ │ add r1, pc, r1 │ │ b 245f364 │ │ - ldc2l 10, cr4, [ip, #876] @ 0x36c @ │ │ + ldc2l 11, cr4, [ip, #32] @ │ │ ldc2l 2, cr8, [fp, #620] @ 0x26c │ │ - ldc2l 10, cr12, [fp, #664] @ 0x298 @ │ │ - ldc2l 2, cr4, [sp, #408] @ 0x198 │ │ - ldc2l 10, cr12, [fp, #232] @ 0xe8 @ │ │ - ldc2l 1, cr4, [ip, #212] @ 0xd4 │ │ + ldc2l 10, cr12, [fp, #844] @ 0x34c @ │ │ + ldc2l 2, cr4, [sp, #588] @ 0x24c │ │ + ldc2l 10, cr12, [fp, #412] @ 0x19c @ │ │ + ldc2l 1, cr4, [ip, #392] @ 0x188 │ │ ldc2l 13, cr8, [fp, #100] @ 0x64 │ │ ldc2l 3, cr6, [fp, #316] @ 0x13c │ │ - ldc2l 14, cr3, [ip, #980] @ 0x3d4 │ │ + ldc2l 15, cr3, [ip, #136] @ 0x88 │ │ ldc2l 10, cr8, [fp, #948] @ 0x3b4 @ │ │ ldc2l 3, cr0, [lr, #408] @ 0x198 │ │ - ldc2l 15, cr3, [ip, #916] @ 0x394 │ │ + ldc2l 0, cr4, [ip, #72] @ 0x48 │ │ ldc2l 11, cr10, [fp, #140] @ 0x8c @ │ │ ldc2l 15, cr11, [sp, #164] @ 0xa4 │ │ ldc2l 12, cr13, [sp, #788] @ 0x314 │ │ - ldc2l 0, cr10, [ip, #536] @ 0x218 │ │ + ldc2l 0, cr10, [ip, #716] @ 0x2cc │ │ vcadd.f32 d25, d27, d6, #270 │ │ - ldc2l 8, cr0, [sp, #832] @ 0x340 │ │ + ldc2l 8, cr0, [sp, #1012] @ 0x3f4 │ │ streq lr, [pc], #-244 @ 245f458 │ │ eoreq sl, pc, r4, asr r0 @ │ │ eoreq sl, pc, r0, asr #32 │ │ ldc2l 6, cr6, [fp, #492] @ 0x1ec │ │ - ldc2l 1, cr4, [ip, #1012] @ 0x3f4 │ │ - ldc2l 6, cr2, [ip, #812] @ 0x32c │ │ + ldc2l 2, cr4, [ip, #168] @ 0xa8 │ │ + ldc2l 6, cr2, [ip, #992] @ 0x3e0 │ │ ldc2l 3, cr12, [sp, #388] @ 0x184 │ │ - ldc2l 4, cr10, [ip, #1016] @ 0x3f8 │ │ + ldc2l 5, cr10, [ip, #172] @ 0xac │ │ ldc2l 13, cr9, [fp, #8] │ │ ldc2l 10, cr11, [lr, #168] @ 0xa8 @ │ │ - ldc2l 0, cr4, [ip, #404] @ 0x194 │ │ + ldc2l 0, cr4, [ip, #584] @ 0x248 │ │ ldc2l 15, cr9, [sp, #180] @ 0xb4 │ │ - ldc2l 1, cr4, [sp, #960] @ 0x3c0 │ │ - ldc2l 14, cr3, [sp, #32] │ │ + ldc2l 2, cr4, [sp, #116] @ 0x74 │ │ + ldc2l 14, cr3, [sp, #212] @ 0xd4 │ │ eoreq r9, pc, r8, lsl #27 │ │ ldc2l 11, cr9, [fp, #744] @ 0x2e8 @ │ │ - ldc2l 1, cr4, [sp, #860] @ 0x35c │ │ - ldc2l 6, cr6, [ip, #932] @ 0x3a4 │ │ - ldc2l 3, cr10, [ip, #788] @ 0x314 │ │ + ldc2l 2, cr4, [sp, #16] │ │ + ldc2l 7, cr6, [ip, #88] @ 0x58 │ │ + ldc2l 3, cr10, [ip, #968] @ 0x3c8 │ │ ldc2l 9, cr8, [fp, #194] @ 0xc2 @ │ │ - ldc2l 3, cr10, [ip, #692] @ 0x2b4 │ │ - ldc2l 2, cr0, [ip, #136] @ 0x88 │ │ - ldc2l 6, cr6, [ip, #688] @ 0x2b0 │ │ + ldc2l 3, cr10, [ip, #872] @ 0x368 │ │ + ldc2l 2, cr0, [ip, #316] @ 0x13c │ │ + ldc2l 6, cr6, [ip, #868] @ 0x364 │ │ ldc2l 7, cr10, [fp, #92] @ 0x5c │ │ - ldc2l 15, cr11, [ip, #528] @ 0x210 │ │ + ldc2l 15, cr11, [ip, #708] @ 0x2c4 │ │ ldc2l 8, cr3, [lr, #864] @ 0x360 │ │ - ldc2l 1, cr0, [ip, #232] @ 0xe8 │ │ + ldc2l 1, cr0, [ip, #412] @ 0x19c │ │ ldc2l 0, cr6, [fp, #20] │ │ - ldc2l 15, cr11, [ip, #384] @ 0x180 │ │ + ldc2l 15, cr11, [ip, #564] @ 0x234 │ │ ldc2l 7, cr9, [fp, #728] @ 0x2d8 │ │ - ldc2l 7, cr4, [ip, #652] @ 0x28c │ │ + ldc2l 7, cr4, [ip, #832] @ 0x340 │ │ │ │ 0245f4cc : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ mov r4, r3 │ │ mov sl, r2 │ │ @@ -1335075,41 +1335075,41 @@ │ │ ldr r0, [pc, #124] @ 245f898 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 12, cr3, [sp, #948] @ 0x3b4 │ │ + ldc2l 13, cr3, [sp, #104] @ 0x68 │ │ ldc2l 9, cr7, [fp, #94] @ 0x5e @ │ │ ldc2l 4, cr9, [fp, #680] @ 0x2a8 │ │ ldc2l 9, cr7, [fp, #22] @ │ │ - ldc2l 11, cr15, [fp, #964] @ 0x3c4 @ │ │ + ldc2l 12, cr15, [fp, #120] @ 0x78 │ │ eoreq r9, pc, r0, lsl #15 │ │ ldc2l 4, cr9, [fp, #600] @ 0x258 │ │ - ldc2l 13, cr11, [ip, #96] @ 0x60 │ │ - ldc2l 11, cr11, [ip, #1008] @ 0x3f0 @ │ │ + ldc2l 13, cr11, [ip, #276] @ 0x114 │ │ + ldc2l 12, cr11, [ip, #164] @ 0xa4 │ │ ldc2l 7, cr7, [fp, #156] @ 0x9c │ │ - ldc2l 15, cr15, [fp, #264] @ 0x108 │ │ - ldc2l 14, cr15, [fp, #184] @ 0xb8 │ │ - ldc2l 15, cr15, [ip, #68] @ 0x44 │ │ - ldc2l 14, cr15, [ip, #164] @ 0xa4 │ │ - ldc2l 1, cr0, [ip, #208] @ 0xd0 │ │ - ldc2l 15, cr13, [fp, #68] @ 0x44 │ │ - ldc2l 14, cr13, [fp, #68] @ 0x44 │ │ + ldc2l 15, cr15, [fp, #444] @ 0x1bc │ │ + ldc2l 14, cr15, [fp, #364] @ 0x16c │ │ + ldc2l 15, cr15, [ip, #248] @ 0xf8 │ │ + ldc2l 14, cr15, [ip, #344] @ 0x158 │ │ + ldc2l 1, cr0, [ip, #388] @ 0x184 │ │ + ldc2l 15, cr13, [fp, #248] @ 0xf8 │ │ + ldc2l 14, cr13, [fp, #248] @ 0xf8 │ │ ldc2l 11, cr13, [sp, #864] @ 0x360 @ │ │ - ldc2l 11, cr11, [ip, #512] @ 0x200 @ │ │ - ldc2l 15, cr9, [ip, #180] @ 0xb4 │ │ - ldc2l 10, cr11, [ip, #960] @ 0x3c0 @ │ │ + ldc2l 11, cr11, [ip, #692] @ 0x2b4 @ │ │ + ldc2l 15, cr9, [ip, #360] @ 0x168 │ │ + ldc2l 11, cr11, [ip, #116] @ 0x74 @ │ │ ldc2l 3, cr9, [fp, #344] @ 0x158 │ │ - ldc2l 13, cr15, [fp, #552] @ 0x228 │ │ - ldc2l 13, cr15, [fp, #424] @ 0x1a8 │ │ + ldc2l 13, cr15, [fp, #732] @ 0x2dc │ │ + ldc2l 13, cr15, [fp, #604] @ 0x25c │ │ ldc2l 12, cr5, [fp, #164] @ 0xa4 │ │ ldc2l 4, cr9, [fp, #824] @ 0x338 │ │ - ldc2l 9, cr3, [sp, #418] @ 0x1a2 @ │ │ + ldc2l 9, cr3, [sp, #508] @ 0x1fc @ │ │ │ │ 0245f89c : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #32 │ │ ldr r1, [pc, #220] @ 245f98c │ │ str r0, [fp, #-20] @ 0xffffffec │ │ @@ -1335164,25 +1335164,25 @@ │ │ add r0, pc, r0 │ │ bl 270ce70 │ │ ldr r0, [pc, #32] @ 245f9a0 │ │ add r0, pc, r0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, lr} │ │ b 270ce40 │ │ - ldc2l 6, cr5, [sp, #692] @ 0x2b4 │ │ + ldc2l 6, cr5, [sp, #872] @ 0x368 │ │ ldc2l 11, cr10, [lr, #340] @ 0x154 @ │ │ - ldc2l 5, cr3, [ip, #820] @ 0x334 │ │ + ldc2l 5, cr3, [ip, #1000] @ 0x3e8 │ │ ldc2l 15, cr6, [fp, #624] @ 0x270 │ │ ldc2l 0, cr3, [lr, #724] @ 0x2d4 │ │ - ldc2l 5, cr5, [sp, #900] @ 0x384 │ │ - ldc2l 8, cr11, [ip, #712] @ 0x2c8 │ │ - ldc2l 5, cr3, [ip, #644] @ 0x284 │ │ + ldc2l 6, cr5, [sp, #56] @ 0x38 │ │ + ldc2l 8, cr11, [ip, #892] @ 0x37c │ │ + ldc2l 5, cr3, [ip, #824] @ 0x338 │ │ ldc2l 15, cr6, [fp, #448] @ 0x1c0 │ │ - ldc2l 10, cr11, [fp, #40] @ 0x28 @ │ │ - ldc2l 6, cr5, [sp, #308] @ 0x134 │ │ + ldc2l 10, cr11, [fp, #220] @ 0xdc @ │ │ + ldc2l 6, cr5, [sp, #488] @ 0x1e8 │ │ │ │ 0245f9b8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8} │ │ sub sp, sp, #936 @ 0x3a8 │ │ @@ -1336212,15 +1336212,15 @@ │ │ ldr r0, [pc, #1424] @ 2460f60 │ │ mov r1, #20 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #1412] @ 2460f64 │ │ add r0, pc, r0 │ │ b 2460ed0 │ │ - ldc2l 11, cr13, [ip, #828] @ 0x33c @ │ │ + ldc2l 11, cr13, [ip, #1008] @ 0x3f0 @ │ │ streq sp, [pc], #-864 @ 24609f0 │ │ streq sp, [pc], #-880 @ 24609f4 │ │ eoreq r9, pc, ip, lsr #5 │ │ ldr r1, [pc, #1292] @ 2460f08 │ │ mov r0, r8 │ │ mov r2, r5 │ │ mov r3, #1 │ │ @@ -1336242,15 +1336242,15 @@ │ │ mov r1, #19 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ bl 270db90 │ │ cmp r0, #0 │ │ bne 2460e24 │ │ b 245facc │ │ - ldc2l 11, cr13, [ip, #412] @ 0x19c @ │ │ + ldc2l 11, cr13, [ip, #592] @ 0x250 @ │ │ streq sp, [pc], #-780 @ 2460a68 │ │ streq sp, [pc], #-741 @ 2460a6c │ │ streq sp, [pc], #-776 @ 2460a70 │ │ eoreq r9, pc, ip, lsl r2 @ │ │ ldc2l 5, cr1, [lr, #824] @ 0x338 │ │ ldr r0, [pc, #1424] @ 246100c │ │ mov r1, sl │ │ @@ -1336284,15 +1336284,15 @@ │ │ bl 270e800 │ │ ldr r1, [sp, #24] │ │ add r2, r4, #24 │ │ mov r0, r9 │ │ add r4, sp, #688 @ 0x2b0 │ │ bl 270e800 │ │ b 2460bbc │ │ - ldc2l 10, cr15, [ip, #36] @ 0x24 @ │ │ + ldc2l 10, cr15, [ip, #216] @ 0xd8 @ │ │ ldc2l 14, cr10, [lr, #556] @ 0x22c │ │ ldc2l 7, cr15, [sp, #208] @ 0xd0 │ │ ldr r0, [sp, #584] @ 0x248 │ │ sub r0, r0, #1 │ │ cmp r0, #20 │ │ bhi 2460c10 │ │ cmp r5, #0 │ │ @@ -1336539,103 +1336539,103 @@ │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldr r0, [pc, #24] @ 2460f0c │ │ mov r1, #137 @ 0x89 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ b 2460a3c │ │ - ldc2l 6, cr15, [ip, #4] │ │ + ldc2l 6, cr15, [ip, #184] @ 0xb8 │ │ ldc2l 4, cr2, [lr, #188] @ 0xbc │ │ ldc2l 4, cr6, [fp, #284] @ 0x11c │ │ ldc2l 1, cr0, [lr, #320] @ 0x140 │ │ ldc2l 14, cr9, [lr, #780] @ 0x30c │ │ - ldc2l 4, cr2, [ip, #820] @ 0x334 │ │ + ldc2l 4, cr2, [ip, #1000] @ 0x3e8 │ │ ldc2l 7, cr4, [fp, #828] @ 0x33c │ │ - ldc2l 7, cr12, [ip, #636] @ 0x27c │ │ + ldc2l 7, cr12, [ip, #816] @ 0x330 │ │ ldc2l 1, cr1, [lr, #680] @ 0x2a8 │ │ strhteq r8, [pc], -ip │ │ eoreq r8, pc, r4, asr #23 │ │ eoreq r8, pc, ip, lsr ip @ │ │ ldc2l 4, cr8, [lr, #256] @ 0x100 │ │ streq ip, [pc], #-1580 @ 2460f3c │ │ - ldc2l 15, cr8, [ip, #180] @ 0xb4 │ │ - ldc2l 7, cr2, [ip, #356] @ 0x164 │ │ + ldc2l 15, cr8, [ip, #360] @ 0x168 │ │ + ldc2l 7, cr2, [ip, #536] @ 0x218 │ │ ldc2l 2, cr8, [lr, #704] @ 0x2c0 │ │ streq ip, [pc], #-1180 @ 2460f4c │ │ - ldc2l 13, cr8, [ip, #628] @ 0x274 │ │ - ldc2l 5, cr2, [ip, #804] @ 0x324 │ │ - ldc2l 14, cr14, [fp] │ │ + ldc2l 13, cr8, [ip, #808] @ 0x328 │ │ + ldc2l 5, cr2, [ip, #984] @ 0x3d8 │ │ + ldc2l 14, cr14, [fp, #180] @ 0xb4 │ │ ldc2l 10, cr4, [fp, #484] @ 0x1e4 @ │ │ - ldc2l 12, cr12, [ip, #152] @ 0x98 │ │ - ldc2l 5, cr2, [ip, #260] @ 0x104 │ │ - ldc2l 12, cr8, [ip, #924] @ 0x39c │ │ - ldc2l 11, cr12, [ip, #940] @ 0x3ac @ │ │ - ldc2l 3, cr15, [ip, #340] @ 0x154 │ │ + ldc2l 12, cr12, [ip, #332] @ 0x14c │ │ + ldc2l 5, cr2, [ip, #440] @ 0x1b8 │ │ + ldc2l 13, cr8, [ip, #80] @ 0x50 │ │ + ldc2l 12, cr12, [ip, #96] @ 0x60 │ │ + ldc2l 3, cr15, [ip, #520] @ 0x208 │ │ ldc2l 14, cr0, [lr, #1016] @ 0x3f8 │ │ - ldc2l 2, cr15, [ip, #276] @ 0x114 │ │ + ldc2l 2, cr15, [ip, #456] @ 0x1c8 │ │ ldc2l 14, cr0, [lr, #104] @ 0x68 │ │ ldc2l 11, cr0, [lr, #888] @ 0x378 @ │ │ ldc2l 4, cr10, [lr, #780] @ 0x30c │ │ ldc2l 11, cr0, [lr, #792] @ 0x318 @ │ │ ldc2l 7, cr10, [lr, #892] @ 0x37c │ │ strdeq r8, [pc], -ip @ │ │ ldc2l 7, cr10, [lr, #652] @ 0x28c │ │ strhteq r8, [pc], -r4 │ │ ldc2l 10, cr0, [lr, #72] @ 0x48 @ │ │ - ldc2l 2, cr15, [ip, #84] @ 0x54 │ │ + ldc2l 2, cr15, [ip, #264] @ 0x108 │ │ ldc2l 13, cr0, [lr, #760] @ 0x2f8 │ │ - ldc2l 1, cr15, [ip, #916] @ 0x394 │ │ + ldc2l 2, cr15, [ip, #72] @ 0x48 │ │ ldc2l 10, cr0, [lr, #952] @ 0x3b8 @ │ │ - ldc2l 1, cr15, [ip, #692] @ 0x2b4 │ │ + ldc2l 1, cr15, [ip, #872] @ 0x368 │ │ ldc2l 13, cr0, [lr, #344] @ 0x158 │ │ - ldc2l 1, cr15, [ip, #500] @ 0x1f4 │ │ - ldc2l 1, cr15, [ip, #340] @ 0x154 │ │ - ldc2l 15, cr14, [ip, #116] @ 0x74 │ │ + ldc2l 1, cr15, [ip, #680] @ 0x2a8 │ │ + ldc2l 1, cr15, [ip, #520] @ 0x208 │ │ + ldc2l 15, cr14, [ip, #296] @ 0x128 │ │ ldc2l 3, cr10, [lr, #540] @ 0x21c │ │ ldc2l 3, cr10, [lr, #316] @ 0x13c │ │ ldc2l 2, cr10, [lr, #908] @ 0x38c │ │ eoreq r8, pc, r0, lsl #12 │ │ ldc2l 2, cr10, [lr, #668] @ 0x29c │ │ - ldc2l 1, cr15, [ip, #116] @ 0x74 │ │ - ldc2l 0, cr15, [ip, #1012] @ 0x3f4 │ │ + ldc2l 1, cr15, [ip, #296] @ 0x128 │ │ + ldc2l 1, cr15, [ip, #168] @ 0xa8 │ │ ldc2l 5, cr10, [lr, #348] @ 0x15c │ │ eoreq r8, pc, r0, ror r8 @ │ │ ldc2l 4, cr10, [lr, #364] @ 0x16c │ │ ldc2l 11, cr0, [lr, #376] @ 0x178 @ │ │ ldc2l 4, cr10, [lr, #156] @ 0x9c │ │ ldc2l 11, cr0, [lr, #168] @ 0xa8 @ │ │ - ldc2l 2, cr15, [ip, #740] @ 0x2e4 │ │ + ldc2l 2, cr15, [ip, #920] @ 0x398 │ │ ldc2l 14, cr0, [lr, #392] @ 0x188 │ │ ldc2l 1, cr10, [lr, #268] @ 0x10c │ │ vcadd.f32 q8, q7, q3, #270 │ │ eoreq r8, pc, r8, asr r4 @ │ │ - ldc2l 12, cr14, [ip, #868] @ 0x364 │ │ + ldc2l 13, cr14, [ip, #24] │ │ vcadd.f32 d16, d30, d2, #270 │ │ - ldc2l 10, cr14, [ip, #628] @ 0x274 @ │ │ + ldc2l 10, cr14, [ip, #808] @ 0x328 @ │ │ ldc2l 6, cr0, [lr, #280] @ 0x118 │ │ eoreq r8, pc, r0, asr r1 @ │ │ ldc2l 13, cr9, [lr, #908] @ 0x38c │ │ ldc2l 4, cr0, [lr, #920] @ 0x398 │ │ strdeq r8, [pc], -r8 @ │ │ - vcadd.f32 q15, q14, , #270 │ │ + ldc2l 9, cr14, [ip, #52] @ 0x34 @ │ │ ldc2l 4, cr0, [lr, #600] @ 0x258 │ │ - vcadd.f32 q15, q14, , #270 │ │ + vcadd.f32 q15, q14, q15, #270 │ │ ldc2l 4, cr0, [lr, #424] @ 0x1a8 │ │ - ldc2l 8, cr14, [ip, #596] @ 0x254 │ │ + vcadd.f32 q15, q14, q1, #270 │ │ ldc2l 4, cr0, [lr, #248] @ 0xf8 │ │ ldc2l 13, cr9, [lr, #12] │ │ ldrdeq r7, [pc], -r8 @ │ │ - ldc2l 7, cr14, [ip, #916] @ 0x394 │ │ + ldc2l 8, cr14, [ip, #72] @ 0x48 │ │ ldc2l 3, cr0, [lr, #568] @ 0x238 │ │ ldc2l 12, cr9, [lr, #220] @ 0xdc │ │ ldc2l 3, cr0, [lr, #232] @ 0xe8 │ │ eoreq r7, pc, ip, asr #30 │ │ eoreq r7, pc, r4, ror lr @ │ │ eoreq r7, pc, r8, asr lr @ │ │ - ldc2l 6, cr12, [ip, #1020] @ 0x3fc │ │ + ldc2l 7, cr12, [ip, #176] @ 0xb0 │ │ │ │ 02461064 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d13} │ │ sub sp, sp, #760 @ 0x2f8 │ │ @@ -1337584,16 +1337584,16 @@ │ │ add r0, r0, r1, lsl #3 │ │ ldr r1, [pc, #556] @ 2462168 │ │ add r1, pc, r1 │ │ bl 270f4d0 │ │ mvn r4, #71 @ 0x47 │ │ mov r6, r5 │ │ b 2461f70 │ │ - ldc2l 5, cr12, [ip, #200] @ 0xc8 │ │ - ldc2l 5, cr12, [ip, #56] @ 0x38 │ │ + ldc2l 5, cr12, [ip, #380] @ 0x17c │ │ + ldc2l 5, cr12, [ip, #236] @ 0xec │ │ add r0, sp, #2800 @ 0xaf0 │ │ add r4, r4, #1 │ │ add r0, r0, r1, lsl #3 │ │ add r6, r6, #8 │ │ cmn r4, #66 @ 0x42 │ │ vstr d8, [r0] │ │ beq 24620cc │ │ @@ -1337705,66 +1337705,66 @@ │ │ mov r0, r8 │ │ mov r2, sl │ │ movw r3, #515 @ 0x203 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2461e1c │ │ ldc2l 14, cr11, [sp, #968] @ 0x3c8 │ │ - ldc2l 12, cr1, [ip, #452] @ 0x1c4 │ │ + ldc2l 12, cr1, [ip, #632] @ 0x278 │ │ ldc2l 15, cr3, [fp, #444] @ 0x1bc │ │ ldc2l 12, cr11, [sp, #488] @ 0x1e8 │ │ - ldc2l 9, cr1, [ip, #498] @ 0x1f2 @ │ │ - ldc2l 1, cr10, [ip, #976] @ 0x3d0 │ │ - ldc2l 4, cr6, [ip, #1008] @ 0x3f0 │ │ + ldc2l 10, cr1, [ip, #152] @ 0x98 @ │ │ + ldc2l 2, cr10, [ip, #132] @ 0x84 │ │ + ldc2l 5, cr6, [ip, #164] @ 0xa4 │ │ ldc2l 6, cr3, [lr, #472] @ 0x1d8 │ │ - ldc2l 0, cr10, [ip, #272] @ 0x110 │ │ - ldc2l 3, cr6, [ip, #304] @ 0x130 │ │ - ldc2l 0, cr10, [ip, #48] @ 0x30 │ │ - ldc2l 3, cr6, [ip, #80] @ 0x50 │ │ - ldc2l 6, cr9, [ip, #336] @ 0x150 │ │ - ldc2l 9, cr5, [ip, #184] @ 0xb8 @ │ │ + ldc2l 0, cr10, [ip, #452] @ 0x1c4 │ │ + ldc2l 3, cr6, [ip, #484] @ 0x1e4 │ │ + ldc2l 0, cr10, [ip, #228] @ 0xe4 │ │ + ldc2l 3, cr6, [ip, #260] @ 0x104 │ │ + ldc2l 6, cr9, [ip, #516] @ 0x204 │ │ + ldc2l 9, cr5, [ip, #274] @ 0x112 @ │ │ ldc2l 11, cr2, [lr, #504] @ 0x1f8 @ │ │ eoreq r6, pc, r8, asr #27 │ │ - ldc2l 15, cr9, [ip, #784] @ 0x310 │ │ - ldc2l 2, cr6, [ip, #816] @ 0x330 │ │ + ldc2l 15, cr9, [ip, #964] @ 0x3c4 │ │ + ldc2l 2, cr6, [ip, #996] @ 0x3e4 │ │ ldc2l 11, cr13, [sp, #1016] @ 0x3f8 @ │ │ - ldc2l 0, cr6, [ip, #864] @ 0x360 │ │ + ldc2l 1, cr6, [ip, #20] │ │ ldc2l 10, cr13, [sp, #168] @ 0xa8 @ │ │ - ldc2l 15, cr5, [ip, #16] │ │ + ldc2l 15, cr5, [ip, #196] @ 0xc4 │ │ ldc2l 9, cr13, [sp, #492] @ 0x1ec @ │ │ ldc2l 9, cr13, [sp, #380] @ 0x17c @ │ │ - ldc2l 14, cr5, [ip, #608] @ 0x260 │ │ + ldc2l 14, cr5, [ip, #788] @ 0x314 │ │ ldc2l 9, cr13, [sp, #268] @ 0x10c @ │ │ - ldc2l 14, cr5, [ip, #384] @ 0x180 │ │ + ldc2l 14, cr5, [ip, #564] @ 0x234 │ │ vcadd.f32 d29, d29, d6, #270 │ │ - ldc2l 13, cr5, [ip, #384] @ 0x180 │ │ + ldc2l 13, cr5, [ip, #564] @ 0x234 │ │ ldc2l 7, cr13, [sp, #904] @ 0x388 │ │ - ldc2l 12, cr5, [ip, #752] @ 0x2f0 │ │ + ldc2l 12, cr5, [ip, #932] @ 0x3a4 │ │ ldc2l 7, cr13, [sp, #136] @ 0x88 │ │ - ldc2l 11, cr5, [ip, #1008] @ 0x3f0 @ │ │ + ldc2l 12, cr5, [ip, #164] @ 0xa4 │ │ ldc2l 6, cr13, [sp, #744] @ 0x2e8 │ │ - ldc2l 11, cr5, [ip, #592] @ 0x250 @ │ │ + ldc2l 11, cr5, [ip, #772] @ 0x304 @ │ │ ldc2l 6, cr13, [sp, #536] @ 0x218 │ │ - ldc2l 11, cr5, [ip, #384] @ 0x180 @ │ │ + ldc2l 11, cr5, [ip, #564] @ 0x234 @ │ │ ldc2l 6, cr13, [sp, #328] @ 0x148 │ │ - ldc2l 11, cr5, [ip, #176] @ 0xb0 @ │ │ + ldc2l 11, cr5, [ip, #356] @ 0x164 @ │ │ ldc2l 6, cr13, [sp, #120] @ 0x78 │ │ - ldc2l 10, cr5, [ip, #992] @ 0x3e0 @ │ │ + ldc2l 11, cr5, [ip, #148] @ 0x94 @ │ │ ldc2l 5, cr13, [sp, #936] @ 0x3a8 │ │ - ldc2l 10, cr5, [ip, #784] @ 0x310 @ │ │ + ldc2l 10, cr5, [ip, #964] @ 0x3c4 @ │ │ ldc2l 5, cr13, [sp, #712] @ 0x2c8 │ │ - ldc2l 10, cr5, [ip, #560] @ 0x230 @ │ │ - ldc2l 15, cr9, [ip, #160] @ 0xa0 │ │ - ldc2l 2, cr6, [ip, #192] @ 0xc0 │ │ + ldc2l 10, cr5, [ip, #740] @ 0x2e4 @ │ │ + ldc2l 15, cr9, [ip, #340] @ 0x154 │ │ + ldc2l 2, cr6, [ip, #372] @ 0x174 │ │ ldc2l 12, cr14, [lr, #704] @ 0x2c0 │ │ ldc2l 4, cr13, [sp, #984] @ 0x3d8 │ │ - ldc2l 9, cr5, [ip, #416] @ 0x1a0 @ │ │ + ldc2l 9, cr5, [ip, #506] @ 0x1fa @ │ │ ldc2l 11, cr2, [lr, #808] @ 0x328 @ │ │ - ldc2l 9, cr5, [ip, #320] @ 0x140 @ │ │ - ldc2l 3, cr12, [ip, #136] @ 0x88 │ │ + ldc2l 9, cr5, [ip, #410] @ 0x19a @ │ │ + ldc2l 3, cr12, [ip, #316] @ 0x13c │ │ │ │ 02462200 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #316 @ 0x13c │ │ ldr r9, [fp, #8] │ │ mov r5, r0 │ │ @@ -1338066,21 +1338066,21 @@ │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 7, cr8, [lr, #580] @ 0x244 │ │ streq sl, [pc], #-2896 @ 24626c0 │ │ eoreq r6, pc, ip, lsr #21 │ │ streq sl, [pc], #-2876 @ 24626c8 │ │ strdeq r6, [pc], -r8 @ │ │ eoreq r6, pc, r8, lsl sl @ │ │ - ldc2l 1, cr3, [ip, #880] @ 0x370 │ │ + ldc2l 2, cr3, [ip, #36] @ 0x24 │ │ eoreq r6, pc, r0, asr #14 │ │ eoreq r6, pc, r8, ror #13 │ │ - ldc2l 7, cr4, [sp, #276] @ 0x114 │ │ - vcadd.f32 d16, d28, d29, #270 │ │ + ldc2l 7, cr4, [sp, #456] @ 0x1c8 │ │ + ldc2l 8, cr0, [ip, #872] @ 0x368 │ │ eoreq r6, pc, r4, lsl #13 │ │ - ldc2l 10, cr0, [sp, #648] @ 0x288 @ │ │ + ldc2l 10, cr0, [sp, #828] @ 0x33c @ │ │ eoreq r6, pc, r8, lsl r7 @ │ │ ldc2l 3, cr8, [lr, #180] @ 0xb4 │ │ │ │ 024626f0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #588 @ 0x24c │ │ @@ -1338205,19 +1338205,19 @@ │ │ ldr r0, [pc, #36] @ 2462900 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 14, cr10, [fp, #180] @ 0xb4 │ │ - ldc2l 0, cr5, [ip, #52] @ 0x34 │ │ + ldc2l 14, cr10, [fp, #360] @ 0x168 │ │ + ldc2l 0, cr5, [ip, #232] @ 0xe8 │ │ eoreq r6, pc, r8, lsl #9 │ │ eoreq r6, pc, r8, lsl #9 │ │ - ldc2l 12, cr10, [fp, #532] @ 0x214 │ │ + ldc2l 12, cr10, [fp, #712] @ 0x2c8 │ │ │ │ 02462904 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #144 @ 0x90 │ │ vldr d16, [r0] │ │ mov r4, r2 │ │ @@ -1338405,17 +1338405,17 @@ │ │ b 2462b54 │ │ mov r0, #0 │ │ sub sp, fp, #48 @ 0x30 │ │ vpop {d8-d9} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 12, cr7, [lr, #608] @ 0x260 │ │ - ldc2l 2, cr4, [sp, #692] @ 0x2b4 │ │ - ldc2l 12, cr12, [fp, #48] @ 0x30 │ │ - ldc2l 2, cr4, [sp, #484] @ 0x1e4 │ │ + ldc2l 2, cr4, [sp, #872] @ 0x368 │ │ + ldc2l 12, cr12, [fp, #228] @ 0xe4 │ │ + ldc2l 2, cr4, [sp, #664] @ 0x298 │ │ │ │ 02462c04 : │ │ vldmia r1, {d16-d18} │ │ vldmia r0, {d19-d26} │ │ vmul.f64 d24, d24, d17 │ │ vmul.f64 d23, d23, d17 │ │ vmul.f64 d17, d22, d17 │ │ @@ -1339067,54 +1339067,54 @@ │ │ streq sl, [pc], #-836 @ 2463624 │ │ streq sl, [pc], #-788 @ 2463628 │ │ streq sl, [pc], #-488 @ 246362c │ │ streq sl, [pc], #-848 @ 2463630 │ │ streq sl, [pc], #-860 @ 2463634 │ │ mlaeq pc, r8, r0, r6 @ │ │ eoreq r6, pc, r0 │ │ - ldc2l 10, cr4, [ip, #208] @ 0xd0 @ │ │ + ldc2l 10, cr4, [ip, #388] @ 0x184 @ │ │ ldc2l 15, cr15, [sp, #964] @ 0x3c4 │ │ ldrdeq r5, [pc], -r4 @ │ │ eoreq r6, pc, r4, asr r0 @ │ │ - ldc2l 1, cr2, [sp, #952] @ 0x3b8 │ │ + ldc2l 2, cr2, [sp, #108] @ 0x6c │ │ ldc2l 15, cr15, [sp, #740] @ 0x2e4 │ │ eoreq r6, pc, r0, lsr #32 │ │ stc2l 4, cr6, [r7, #320]! @ 0x140 │ │ streq sl, [pc], #-616 @ 2463660 │ │ streq sl, [pc], #-520 @ 2463664 │ │ streq sl, [pc], #-112 @ 2463668 │ │ streq sl, [pc], #-300 @ 246366c │ │ streq sl, [pc], #-392 @ 2463670 │ │ - vcadd.f32 q10, q14, , #270 │ │ + ldc2l 9, cr4, [ip, #32] @ │ │ streq sl, [pc], #-336 @ 2463678 │ │ ldc2l 11, cr3, [lr, #504] @ 0x1f8 @ │ │ streq sl, [pc], #-280 @ 2463680 │ │ ldc2l 15, cr3, [fp, #284] @ 0x11c │ │ streq sl, [pc], #-216 @ 2463688 │ │ streq sl, [pc], #-188 @ 246368c │ │ streq sl, [pc], #-16 @ 2463690 │ │ streq r9, [pc], #-4008 @ 2463694 │ │ streq r9, [pc], #-3884 @ 2463698 │ │ eoreq r5, pc, r8, ror #25 │ │ eoreq r5, pc, ip, asr ip @ │ │ streq r9, [pc], #-3864 @ 24636a4 │ │ streq r9, [pc], #-3840 @ 24636a8 │ │ - ldc2l 6, cr4, [ip, #448] @ 0x1c0 │ │ + ldc2l 6, cr4, [ip, #628] @ 0x274 │ │ ldc2l 12, cr15, [sp, #180] @ 0xb4 │ │ streq r9, [pc], #-3796 @ 24636b4 │ │ mlaeq pc, r0, ip, r5 @ │ │ eoreq r5, pc, r4, lsr ip @ │ │ streq r9, [pc], #-3776 @ 24636c0 │ │ streq r9, [pc], #-3752 @ 24636c4 │ │ ldc2l 1, cr12, [sp, #228] @ 0xe4 │ │ ldc2l 11, cr15, [sp, #852] @ 0x354 @ │ │ streq r9, [pc], #-3812 @ 24636d0 │ │ streq r9, [pc], #-3724 @ 24636d4 │ │ streq r9, [pc], #-3744 @ 24636d8 │ │ - ldc2l 4, cr10, [ip, #148] @ 0x94 │ │ + ldc2l 4, cr10, [ip, #328] @ 0x148 │ │ streq r9, [pc], #-3544 @ 24636e0 │ │ streq r9, [pc], #-3520 @ 24636e4 │ │ streq r9, [pc], #-3692 @ 24636e8 │ │ ldc2l 4, cr11, [lr, #424] @ 0x1a8 │ │ streq r9, [pc], #-3648 @ 24636f0 │ │ ldc2l 12, cr3, [fp, #220] @ 0xdc │ │ streq r9, [pc], #-3448 @ 24636f8 │ │ @@ -1339125,15 +1339125,15 @@ │ │ streq r9, [pc], #-3260 @ 246370c │ │ streq r9, [pc], #-3440 @ 2463710 │ │ streq r9, [pc], #-3236 @ 2463714 │ │ ldc2l 6, cr13, [sp, #632] @ 0x278 │ │ streq r9, [pc], #-3392 @ 246371c │ │ streq r9, [pc], #-3276 @ 2463720 │ │ streq r9, [pc], #-3188 @ 2463724 │ │ - ldc2l 0, cr14, [ip, #824] @ 0x338 │ │ + ldc2l 0, cr14, [ip, #1004] @ 0x3ec │ │ streq r9, [pc], #-3260 @ 246372c │ │ streq r9, [pc], #-3232 @ 2463730 │ │ streq r9, [pc], #-3104 @ 2463734 │ │ streq r9, [pc], #-3076 @ 2463738 │ │ streq r9, [pc], #-3080 @ 246373c │ │ ldc2l 10, cr3, [fp, #540] @ 0x21c @ │ │ streq r9, [pc], #-3112 @ 2463744 │ │ @@ -1339145,15 +1339145,15 @@ │ │ streq r9, [pc], #-2900 @ 246375c │ │ streq r9, [pc], #-3004 @ 2463760 │ │ streq r9, [pc], #-2872 @ 2463764 │ │ streq r9, [pc], #-2924 @ 2463768 │ │ streq r9, [pc], #-2876 @ 246376c │ │ ldc2l 13, cr9, [sp, #468] @ 0x1d4 │ │ ldc2l 8, cr15, [sp, #372] @ 0x174 │ │ - ldc2l 12, cr15, [ip, #976] @ 0x3d0 │ │ + ldc2l 13, cr15, [ip, #132] @ 0x84 │ │ eoreq r5, pc, ip, ror r8 @ │ │ streq r9, [pc], #-2488 @ 2463780 │ │ streq r9, [pc], #-2684 @ 2463784 │ │ eoreq r5, pc, r8, ror r8 @ │ │ eoreq r5, pc, r4, lsr r8 @ │ │ │ │ 02463788 : │ │ @@ -1339319,22 +1339319,22 @@ │ │ ldr r0, [pc, #32] @ 2463a0c │ │ add r0, pc, r0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, lr} │ │ b 270ce40 │ │ ldc2l 9, cr15, [sl, #96] @ 0x60 @ │ │ ldc2l 10, cr6, [lr, #932] @ 0x3a4 @ │ │ - ldc2l 5, cr15, [fp, #388] @ 0x184 │ │ + ldc2l 5, cr15, [fp, #568] @ 0x238 │ │ ldc2l 15, cr2, [fp, #192] @ 0xc0 │ │ ldc2l 0, cr15, [sp, #292] @ 0x124 │ │ vcadd.f32 , q5, q10, #270 │ │ - vcadd.f32 , q6, q3, #270 │ │ - ldc2l 5, cr15, [fp, #212] @ 0xd4 │ │ + ldc2l 8, cr7, [ip, #460] @ 0x1cc │ │ + ldc2l 5, cr15, [fp, #392] @ 0x188 │ │ ldc2l 15, cr2, [fp, #16] │ │ - ldc2l 9, cr7, [fp, #316] @ 0x13c @ │ │ + ldc2l 9, cr7, [fp, #406] @ 0x196 @ │ │ ldc2l 8, cr15, [sl, #832] @ 0x340 │ │ │ │ 02463a24 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8} │ │ @@ -1340435,15 +1340435,15 @@ │ │ add r1, r2, r1, lsl #1 │ │ add r0, pc, r0 │ │ mov r2, r4 │ │ bl 270da30 │ │ add r1, r9, r0, lsl #3 │ │ add r0, sp, #128 @ 0x80 │ │ b 2464bec │ │ - ldc2l 9, cr11, [ip, #346] @ 0x15a @ │ │ + ldc2l 9, cr11, [ip, #436] @ 0x1b4 @ │ │ ldc2l 14, cr6, [lr, #188] @ 0xbc │ │ ldc2l 6, cr11, [sp, #864] @ 0x360 │ │ ldc2l 6, cr11, [sp, #256] @ 0x100 │ │ ldr r0, [pc, #636] @ 2464dfc │ │ movw r3, #1061 @ 0x425 │ │ ldr r2, [pc, #632] @ 2464e00 │ │ ldr r1, [sp, #16] │ │ @@ -1340538,77 +1340538,77 @@ │ │ add r0, pc, r0 │ │ bl 270da00 │ │ b 2464938 │ │ ldc2l 4, cr8, [lr, #312] @ 0x138 │ │ ldc2l 5, cr2, [fp, #300] @ 0x12c │ │ ldc2l 3, cr12, [sp, #368] @ 0x170 │ │ ldc2l 15, cr5, [lr, #796] @ 0x31c │ │ - ldc2l 5, cr14, [fp, #836] @ 0x344 │ │ + ldc2l 5, cr14, [fp, #1016] @ 0x3f8 │ │ ldc2l 8, cr0, [fp, #844] @ 0x34c │ │ ldc2l 15, cr7, [lr, #204] @ 0xcc │ │ eoreq r4, pc, r0, lsr pc @ │ │ ldc2l 3, cr11, [sp, #800] @ 0x320 │ │ ldc2l 12, cr3, [fp, #368] @ 0x170 │ │ - ldc2l 6, cr11, [ip, #84] @ 0x54 │ │ + ldc2l 6, cr11, [ip, #264] @ 0x108 │ │ ldc2l 12, cr3, [fp, #64] @ 0x40 │ │ eoreq r4, pc, ip, asr #31 │ │ ldc2l 5, cr4, [lr, #256] @ 0x100 │ │ streq r8, [pc], #-2604 @ 2464d34 │ │ - ldc2l 0, cr5, [ip, #180] @ 0xb4 │ │ - ldc2l 8, cr14, [fp, #356] @ 0x164 │ │ + ldc2l 0, cr5, [ip, #360] @ 0x168 │ │ + vcadd.f32 d30, d27, d6, #270 │ │ ldc2l 3, cr4, [lr, #656] @ 0x290 │ │ streq r8, [pc], #-2192 @ 2464d44 │ │ - ldc2l 14, cr4, [ip, #580] @ 0x244 │ │ - ldc2l 6, cr14, [fp, #756] @ 0x2f4 │ │ + ldc2l 14, cr4, [ip, #760] @ 0x2f8 │ │ + ldc2l 6, cr14, [fp, #936] @ 0x3a8 │ │ ldc2l 11, cr0, [fp, #632] @ 0x278 @ │ │ ldc2l 11, cr0, [fp, #436] @ 0x1b4 @ │ │ - ldc2l 13, cr8, [ip, #104] @ 0x68 │ │ - ldc2l 6, cr14, [fp, #212] @ 0xd4 │ │ - ldc2l 13, cr4, [ip, #876] @ 0x36c │ │ + ldc2l 13, cr8, [ip, #284] @ 0x11c │ │ + ldc2l 6, cr14, [fp, #392] @ 0x188 │ │ + ldc2l 14, cr4, [ip, #32] │ │ ldc2l 2, cr8, [lr, #636] @ 0x27c │ │ - ldc2l 3, cr11, [ip, #980] @ 0x3d4 │ │ + ldc2l 4, cr11, [ip, #136] @ 0x88 │ │ ldc2l 9, cr3, [fp, #16] @ │ │ - ldc2l 2, cr11, [ip, #964] @ 0x3c4 │ │ + ldc2l 3, cr11, [ip, #120] @ 0x78 │ │ ldc2l 9, cr3, [fp, #72] @ 0x48 @ │ │ ldc2l 5, cr6, [lr, #540] @ 0x21c │ │ vcadd.f32 d22, d30, d3, #270 │ │ ldc2l 9, cr3, [fp, #432] @ 0x1b0 @ │ │ - ldc2l 2, cr11, [ip, #724] @ 0x2d4 │ │ - ldc2l 2, cr11, [ip, #308] @ 0x134 │ │ - ldc2l 2, cr11, [ip, #132] @ 0x84 │ │ - ldc2l 1, cr11, [ip, #996] @ 0x3e4 │ │ - ldc2l 15, cr10, [ip, #996] @ 0x3e4 │ │ + ldc2l 2, cr11, [ip, #904] @ 0x388 │ │ + ldc2l 2, cr11, [ip, #488] @ 0x1e8 │ │ + ldc2l 2, cr11, [ip, #312] @ 0x138 │ │ + ldc2l 2, cr11, [ip, #152] @ 0x98 │ │ + ldc2l 0, cr11, [ip, #152] @ 0x98 │ │ ldc2l 4, cr6, [lr, #412] @ 0x19c │ │ ldc2l 3, cr6, [lr, #876] @ 0x36c │ │ ldc2l 5, cr3, [fp, #192] @ 0xc0 │ │ ldc2l 3, cr6, [lr, #668] @ 0x29c │ │ - ldc2l 1, cr11, [ip, #740] @ 0x2e4 │ │ - ldc2l 1, cr11, [ip, #612] @ 0x264 │ │ + ldc2l 1, cr11, [ip, #920] @ 0x398 │ │ + ldc2l 1, cr11, [ip, #792] @ 0x318 │ │ ldc2l 5, cr6, [lr, #988] @ 0x3dc │ │ ldc2l 5, cr6, [lr, #204] @ 0xcc │ │ ldc2l 6, cr3, [fp, #544] @ 0x220 │ │ ldc2l 4, cr6, [lr, #1020] @ 0x3fc │ │ eoreq r4, pc, r0, lsr #24 │ │ - ldc2l 3, cr11, [ip, #356] @ 0x164 │ │ + ldc2l 3, cr11, [ip, #536] @ 0x218 │ │ ldc2l 2, cr6, [lr, #172] @ 0xac │ │ ldc2l 3, cr3, [fp, #512] @ 0x200 │ │ - ldc2l 13, cr10, [ip, #804] @ 0x324 │ │ + ldc2l 13, cr10, [ip, #984] @ 0x3d8 │ │ ldc2l 3, cr3, [fp, #784] @ 0x310 │ │ - ldc2l 11, cr10, [ip, #740] @ 0x2e4 @ │ │ + ldc2l 11, cr10, [ip, #920] @ 0x398 @ │ │ ldc2l 1, cr3, [fp, #720] @ 0x2d0 │ │ ldc2l 15, cr5, [lr, #332] @ 0x14c │ │ ldc2l 0, cr3, [fp, #672] @ 0x2a0 │ │ - ldc2l 10, cr10, [ip, #340] @ 0x154 @ │ │ + ldc2l 10, cr10, [ip, #520] @ 0x208 @ │ │ ldc2l 0, cr3, [fp, #320] @ 0x140 │ │ - ldc2l 10, cr10, [ip, #180] @ 0xb4 @ │ │ + ldc2l 10, cr10, [ip, #360] @ 0x168 @ │ │ ldc2l 0, cr3, [fp, #160] @ 0xa0 │ │ - ldc2l 10, cr10, [ip, #20] @ │ │ + ldc2l 10, cr10, [ip, #200] @ 0xc8 @ │ │ ldc2l 0, cr3, [fp] │ │ ldc2l 14, cr5, [lr, #476] @ 0x1dc │ │ - ldc2l 9, cr10, [ip, #306] @ 0x132 @ │ │ + ldc2l 9, cr10, [ip, #396] @ 0x18c @ │ │ ldc2l 15, cr2, [fp, #592] @ 0x250 │ │ ldc2l 13, cr5, [lr, #972] @ 0x3cc │ │ ldc2l 15, cr2, [fp, #288] @ 0x120 │ │ eoreq r4, pc, r0, lsr #2 │ │ ldc2l 14, cr7, [lr, #812] @ 0x32c │ │ │ │ 02464e14 : │ │ @@ -1340900,26 +1340900,26 @@ │ │ mov r3, r8 │ │ bl 270f630 │ │ mov r0, r9 │ │ mov r1, r8 │ │ mov r2, r5 │ │ bl 270f430 │ │ b 246525c │ │ - ldc2l 9, cr6, [fp, #426] @ 0x1aa @ │ │ + ldc2l 10, cr6, [fp, #8] @ │ │ eoreq r3, pc, ip, asr pc @ │ │ eoreq r3, pc, r8, asr pc @ │ │ eoreq r3, pc, r4, asr ip @ │ │ - ldc2l 12, cr1, [sp, #588] @ 0x24c │ │ - ldc2l 13, cr13, [fp, #196] @ 0xc4 │ │ + ldc2l 12, cr1, [sp, #768] @ 0x300 │ │ + ldc2l 13, cr13, [fp, #376] @ 0x178 │ │ eoreq r3, pc, r4, ror #23 │ │ ldc2l 4, cr9, [lr, #404] @ 0x194 │ │ - ldc2l 3, cr8, [fp, #224] @ 0xe0 │ │ - ldc2l 12, cr13, [fp, #756] @ 0x2f4 │ │ + ldc2l 3, cr8, [fp, #404] @ 0x194 │ │ + ldc2l 12, cr13, [fp, #936] @ 0x3a8 │ │ ldc2l 0, cr10, [sp, #304] @ 0x130 │ │ - ldc2l 5, cr6, [fp, #756] @ 0x2f4 │ │ + ldc2l 5, cr6, [fp, #936] @ 0x3a8 │ │ │ │ 024652d4 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d12} │ │ sub sp, sp, #8 │ │ @@ -1341644,15 +1341644,15 @@ │ │ streq r7, [pc], #-3200 @ 2465e28 │ │ streq r7, [pc], #-3152 @ 2465e2c │ │ streq r7, [pc], #-3276 @ 2465e30 │ │ eoreq r3, pc, ip, ror #17 │ │ streq r7, [pc], #-3068 @ 2465e38 │ │ streq r7, [pc], #-3428 @ 2465e3c │ │ streq r7, [pc], #-3792 @ 2465e40 │ │ - ldc2l 2, cr2, [ip, #276] @ 0x114 │ │ + ldc2l 2, cr2, [ip, #456] @ 0x1c8 │ │ streq r7, [pc], #-3152 @ 2465e48 │ │ streq r7, [pc], #-3516 @ 2465e4c │ │ streq r7, [pc], #-2984 @ 2465e50 │ │ streq r7, [pc], #-2940 @ 2465e54 │ │ streq r7, [pc], #-3076 @ 2465e58 │ │ streq r7, [pc], #-2912 @ 2465e5c │ │ ldc2l 2, cr3, [lr, #936] @ 0x3a8 │ │ @@ -1341666,30 +1341666,30 @@ │ │ ldc2l 5, cr3, [lr, #208] @ 0xd0 │ │ streq r7, [pc], #-3304 @ 2465e84 │ │ streq r7, [pc], #-3288 @ 2465e88 │ │ streq r7, [pc], #-2552 @ 2465e8c │ │ eoreq r3, pc, r8, lsr #13 │ │ streq r7, [pc], #-3228 @ 2465e94 │ │ streq r7, [pc], #-2480 @ 2465e98 │ │ - ldc2l 15, cr1, [ip, #980] @ 0x3d4 │ │ + ldc2l 0, cr2, [ip, #136] @ 0x88 │ │ streq r7, [pc], #-2420 @ 2465ea0 │ │ streq r7, [pc], #-2924 @ 2465ea4 │ │ streq r7, [pc], #-3028 @ 2465ea8 │ │ streq r7, [pc], #-2976 @ 2465eac │ │ streq r7, [pc], #-2336 @ 2465eb0 │ │ streq r7, [pc], #-2280 @ 2465eb4 │ │ streq r7, [pc], #-3412 @ 2465eb8 │ │ streq r7, [pc], #-3400 @ 2465ebc │ │ streq r7, [pc], #-3320 @ 2465ec0 │ │ streq r7, [pc], #-2260 @ 2465ec4 │ │ streq r7, [pc], #-2952 @ 2465ec8 │ │ ldc2l 0, cr3, [lr, #376] @ 0x178 │ │ ldc2l 8, cr11, [sp, #488] @ 0x1e8 │ │ - ldc2l 9, cr0, [sp, #242] @ 0xf2 @ │ │ - ldc2l 13, cr7, [ip, #208] @ 0xd0 │ │ + ldc2l 9, cr0, [sp, #332] @ 0x14c @ │ │ + ldc2l 13, cr7, [ip, #388] @ 0x184 │ │ streq r7, [pc], #-2756 @ 2465edc │ │ streq r7, [pc], #-2012 @ 2465ee0 │ │ streq r7, [pc], #-1960 @ 2465ee4 │ │ streq r7, [pc], #-2576 @ 2465ee8 │ │ streq r7, [pc], #-1900 @ 2465eec │ │ streq r7, [pc], #-2096 @ 2465ef0 │ │ streq r7, [pc], #-2220 @ 2465ef4 │ │ @@ -1341698,50 +1341698,50 @@ │ │ streq r7, [pc], #-2536 @ 2465f00 │ │ streq r7, [pc], #-1848 @ 2465f04 │ │ streq r7, [pc], #-1980 @ 2465f08 │ │ ldc2l 0, cr15, [sp, #132] @ 0x84 │ │ streq r7, [pc], #-1780 @ 2465f10 │ │ streq r7, [pc], #-1916 @ 2465f14 │ │ streq r7, [pc], #-2404 @ 2465f18 │ │ - ldc2l 9, cr13, [fp, #192] @ 0xc0 @ │ │ + ldc2l 9, cr13, [fp, #282] @ 0x11a @ │ │ streq r7, [pc], #-1704 @ 2465f20 │ │ streq r7, [pc], #-2184 @ 2465f24 │ │ streq r7, [pc], #-2332 @ 2465f28 │ │ ldc2l 14, cr2, [lr, #152] @ 0x98 │ │ ldc2l 6, cr11, [sp, #264] @ 0x108 │ │ ldc2l 0, cr3, [lr, #688] @ 0x2b0 │ │ streq r7, [pc], #-1552 @ 2465f38 │ │ eoreq r3, pc, r0, asr #5 │ │ streq r7, [pc], #-2228 @ 2465f40 │ │ streq r7, [pc], #-1480 @ 2465f44 │ │ - ldc2l 12, cr1, [ip, #52] @ 0x34 │ │ + ldc2l 12, cr1, [ip, #232] @ 0xe8 │ │ streq r7, [pc], #-1420 @ 2465f4c │ │ streq r7, [pc], #-1924 @ 2465f50 │ │ streq r7, [pc], #-2028 @ 2465f54 │ │ streq r7, [pc], #-1976 @ 2465f58 │ │ streq r7, [pc], #-1336 @ 2465f5c │ │ streq r7, [pc], #-1628 @ 2465f60 │ │ streq r7, [pc], #-1288 @ 2465f64 │ │ streq r7, [pc], #-1912 @ 2465f68 │ │ streq r7, [pc], #-1900 @ 2465f6c │ │ ldc2l 12, cr2, [lr, #520] @ 0x208 │ │ ldc2l 4, cr11, [sp, #632] @ 0x278 │ │ - ldc2l 5, cr0, [sp, #628] @ 0x274 │ │ - ldc2l 9, cr7, [ip, #184] @ 0xb8 @ │ │ + ldc2l 5, cr0, [sp, #808] @ 0x328 │ │ + ldc2l 9, cr7, [ip, #274] @ 0x112 @ │ │ streq r7, [pc], #-1772 @ 2465f80 │ │ streq r7, [pc], #-944 @ 2465f84 │ │ streq r7, [pc], #-892 @ 2465f88 │ │ streq r7, [pc], #-1508 @ 2465f8c │ │ streq r7, [pc], #-832 @ 2465f90 │ │ streq r7, [pc], #-1108 @ 2465f94 │ │ ldc2l 13, cr14, [sp, #356] @ 0x164 │ │ streq r7, [pc], #-1060 @ 2465f9c │ │ streq r7, [pc], #-1196 @ 2465fa0 │ │ streq r7, [pc], #-1696 @ 2465fa4 │ │ - ldc2l 6, cr13, [fp, #592] @ 0x250 │ │ + ldc2l 6, cr13, [fp, #772] @ 0x304 │ │ streq r7, [pc], #-988 @ 2465fac │ │ streq r7, [pc], #-1200 @ 2465fb0 │ │ │ │ 02465fac : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ @@ -1342351,39 +1342351,39 @@ │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #48 @ 0x30 │ │ vpop {d8-d9} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 7, cr9, [fp, #988] @ 0x3dc │ │ - ldc2l 0, cr11, [fp, #176] @ 0xb0 │ │ - ldc2l 7, cr12, [fp, #900] @ 0x384 │ │ - ldc2l 14, cr6, [ip, #320] @ 0x140 │ │ + vcadd.f32 d25, d11, d20, #270 │ │ + ldc2l 0, cr11, [fp, #356] @ 0x164 │ │ + vcadd.f32 d28, d11, d14, #270 │ │ + ldc2l 14, cr6, [ip, #500] @ 0x1f4 │ │ ldc2l 7, cr0, [lr, #492] @ 0x1ec │ │ - ldc2l 4, cr7, [fp, #52] @ 0x34 │ │ + ldc2l 4, cr7, [fp, #232] @ 0xe8 │ │ ldc2l 6, cr0, [lr, #652] @ 0x28c │ │ - ldc2l 3, cr7, [fp, #228] @ 0xe4 │ │ + ldc2l 3, cr7, [fp, #408] @ 0x198 │ │ ldc2l 5, cr0, [lr, #812] @ 0x32c │ │ - ldc2l 2, cr7, [fp, #388] @ 0x184 │ │ + ldc2l 2, cr7, [fp, #568] @ 0x238 │ │ ldc2l 4, cr0, [lr, #972] @ 0x3cc │ │ - ldc2l 1, cr7, [fp, #548] @ 0x224 │ │ + ldc2l 1, cr7, [fp, #728] @ 0x2d8 │ │ ldc2l 4, cr0, [lr, #124] @ 0x7c │ │ - ldc2l 0, cr7, [fp, #724] @ 0x2d4 │ │ + ldc2l 0, cr7, [fp, #904] @ 0x388 │ │ ldc2l 3, cr0, [lr, #268] @ 0x10c │ │ - ldc2l 15, cr6, [fp, #868] @ 0x364 │ │ - ldc2l 2, cr13, [fp, #80] @ 0x50 │ │ - ldc2l 4, cr7, [fp, #468] @ 0x1d4 │ │ + ldc2l 0, cr7, [fp, #24] │ │ + ldc2l 2, cr13, [fp, #260] @ 0x104 │ │ + ldc2l 4, cr7, [fp, #648] @ 0x288 │ │ ldc2l 9, cr0, [lr, #62] @ 0x3e @ │ │ - ldc2l 5, cr7, [fp, #708] @ 0x2c4 │ │ + ldc2l 5, cr7, [fp, #888] @ 0x378 │ │ ldc2l 1, cr0, [lr, #956] @ 0x3bc │ │ - ldc2l 14, cr6, [fp, #532] @ 0x214 │ │ + ldc2l 14, cr6, [fp, #712] @ 0x2c8 │ │ ldc2l 1, cr0, [lr, #92] @ 0x5c │ │ - ldc2l 13, cr6, [fp, #692] @ 0x2b4 │ │ - ldc2l 14, cr8, [fp, #732] @ 0x2dc │ │ + ldc2l 13, cr6, [fp, #872] @ 0x368 │ │ + ldc2l 14, cr8, [fp, #912] @ 0x390 │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ │ │ 024669a8 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ vpush {d8-d13} │ │ sub sp, sp, #280 @ 0x118 │ │ @@ -1342711,37 +1342711,37 @@ │ │ mov r0, r7 │ │ mov r2, r4 │ │ add r1, pc, r1 │ │ bl 270e100 │ │ b 2466b5c │ │ stmiahi r3!, {r0, r4, r5, r6, r7, fp, sp, lr}^ │ │ mcrcc 8, 7, pc, cr4, cr5, {5} @ │ │ - ldc2l 5, cr14, [ip, #592] @ 0x250 │ │ - ldc2l 4, cr0, [sp, #624] @ 0x270 │ │ - ldc2l 4, cr12, [fp, #436] @ 0x1b4 │ │ - ldc2l 12, cr10, [fp, #816] @ 0x330 │ │ - ldc2l 13, cr0, [ip, #240] @ 0xf0 │ │ - ldc2l 4, cr12, [fp, #628] @ 0x274 │ │ + ldc2l 5, cr14, [ip, #772] @ 0x304 │ │ + ldc2l 4, cr0, [sp, #804] @ 0x324 │ │ + ldc2l 4, cr12, [fp, #616] @ 0x268 │ │ + ldc2l 12, cr10, [fp, #996] @ 0x3e4 │ │ + ldc2l 13, cr0, [ip, #420] @ 0x1a4 │ │ + ldc2l 4, cr12, [fp, #808] @ 0x328 │ │ ldc2l 0, cr1, [fp, #736] @ 0x2e0 │ │ - ldc2l 11, cr12, [fp, #616] @ 0x268 @ │ │ - ldc2l 4, cr12, [fp, #52] @ 0x34 │ │ - ldc2l 11, cr2, [ip, #816] @ 0x330 @ │ │ - ldc2l 11, cr6, [fp, #340] @ 0x154 @ │ │ - ldc2l 4, cr0, [sp, #328] @ 0x148 │ │ - ldc2l 8, cr10, [ip, #996] @ 0x3e4 │ │ + ldc2l 11, cr12, [fp, #796] @ 0x31c @ │ │ + ldc2l 4, cr12, [fp, #232] @ 0xe8 │ │ + ldc2l 11, cr2, [ip, #996] @ 0x3e4 @ │ │ + ldc2l 11, cr6, [fp, #520] @ 0x208 @ │ │ + ldc2l 4, cr0, [sp, #508] @ 0x1fc │ │ + ldc2l 9, cr10, [ip, #76] @ 0x4c @ │ │ ldc2l 8, cr9, [lr, #636] @ 0x27c │ │ ldc2l 6, cr6, [sp, #768] @ 0x300 │ │ - ldc2l 3, cr12, [fp, #372] @ 0x174 │ │ + ldc2l 3, cr12, [fp, #552] @ 0x228 │ │ ldc2l 5, cr10, [sp, #184] @ 0xb8 │ │ - ldc2l 10, cr2, [ip, #716] @ 0x2cc @ │ │ - ldc2l 2, cr12, [fp, #740] @ 0x2e4 │ │ + ldc2l 10, cr2, [ip, #896] @ 0x380 @ │ │ + ldc2l 2, cr12, [fp, #920] @ 0x398 │ │ ldc2l 4, cr10, [sp, #604] @ 0x25c │ │ ldrdeq r1, [pc], -r8 @ │ │ eoreq r1, pc, r8, lsl #31 │ │ - ldc2l 4, cr14, [ip, #32] │ │ + ldc2l 4, cr14, [ip, #212] @ 0xd4 │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ │ │ 02466f38 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d10} │ │ @@ -1343778,15 +1343778,15 @@ │ │ ldc2l 13, cr11, [sp, #784] @ 0x310 │ │ streq r6, [pc], #-1728 @ 2467f6c │ │ streq r6, [pc], #-1188 @ 2467f70 │ │ streq r6, [pc], #-1688 @ 2467f74 │ │ streq r6, [pc], #-1072 @ 2467f78 │ │ eoreq r1, pc, r8, ror lr @ │ │ streq r6, [pc], #-1440 @ 2467f80 │ │ - ldc2l 7, cr8, [fp, #1016] @ 0x3f8 │ │ + vcadd.f32 d24, d11, d27, #270 │ │ ldc2l 12, cr5, [lr, #496] @ 0x1f0 │ │ streq r6, [pc], #-1088 @ 2467f8c │ │ ldc2l 2, cr2, [sp, #348] @ 0x15c │ │ streq r6, [pc], #-1040 @ 2467f94 │ │ streq r6, [pc], #-952 @ 2467f98 │ │ streq r6, [pc], #-872 @ 2467f9c │ │ streq r6, [pc], #-792 @ 2467fa0 │ │ @@ -1343919,21 +1343919,21 @@ │ │ vmov.f64 d16, d18 │ │ vstr d17, [sp, #32] │ │ vstr d18, [sp, #24] │ │ vmovls.f64 d16, d17 │ │ b 2468210 │ │ streq r6, [pc], #-632 @ 24681b0 │ │ streq r6, [pc], #-556 @ 24681b4 │ │ - ldc2l 5, cr10, [fp, #328] @ 0x148 │ │ + ldc2l 5, cr10, [fp, #508] @ 0x1fc │ │ streq r6, [pc], #-732 @ 24681bc │ │ streq r6, [pc], #-464 @ 24681c0 │ │ streq r6, [pc], #-368 @ 24681c4 │ │ streq r6, [pc], #-936 @ 24681c8 │ │ vcadd.f32 d16, d27, d3, #270 │ │ - ldc2l 4, cr2, [ip] │ │ + ldc2l 4, cr2, [ip, #180] @ 0xb4 │ │ bl 270d720 │ │ bl 2702c30 │ │ vldr d16, [r4] │ │ vmov d17, r0, r1 │ │ vmov r2, r3, d16 │ │ vldr d16, [pc, #968] @ 24685b0 │ │ vadd.f64 d8, d17, d16 │ │ @@ -1343993,15 +1343993,15 @@ │ │ ldr r4, [pc, #2148] @ 2468b28 │ │ ldr r5, [pc, #2148] @ 2468b2c │ │ add r4, pc, r4 │ │ add r5, pc, r5 │ │ b 246831c │ │ streq r6, [pc], #-344 @ 24682d8 │ │ ldc2l 15, cr1, [sp, #412] @ 0x19c │ │ - ldc2l 4, cr8, [fp, #888] @ 0x378 │ │ + ldc2l 5, cr8, [fp, #44] @ 0x2c │ │ streq r6, [pc], #-296 @ 24682e4 │ │ streq r6, [pc], #-504 @ 24682e8 │ │ streq r6, [pc], #-268 @ 24682ec │ │ mov r0, r4 │ │ mov r2, r5 │ │ movw r3, #953 @ 0x3b9 │ │ bl 270da30 │ │ @@ -1344016,15 +1344016,15 @@ │ │ ble 2468388 │ │ sub r2, r1, #2 │ │ cmp r1, #5 │ │ bcs 246833c │ │ mov r3, r1 │ │ b 246835c │ │ ldc2l 15, cr1, [sp, #140] @ 0x8c │ │ - ldc2l 4, cr8, [fp, #616] @ 0x268 │ │ + ldc2l 4, cr8, [fp, #796] @ 0x31c │ │ streq r6, [pc], #-216 @ 2468340 │ │ mov r1, r2 │ │ mov r0, r4 │ │ mov r2, r5 │ │ movw r3, #953 @ 0x3b9 │ │ bl 270da30 │ │ ldr r3, [pc, #2008] @ 2468b30 │ │ @@ -1344062,16 +1344062,16 @@ │ │ lsl r0, r0, #1 │ │ sub r3, r0, #5 │ │ vstr d8, [r2] │ │ vldr d8, [r5, #8] │ │ b 246849c │ │ streq r6, [pc], #-20 @ 24683ec │ │ streq r6, [pc], #-632 @ 24683f0 │ │ - ldc2l 3, cr2, [ip, #120] @ 0x78 │ │ - ldc2l 3, cr8, [fp, #728] @ 0x2d8 │ │ + ldc2l 3, cr2, [ip, #300] @ 0x12c │ │ + ldc2l 3, cr8, [fp, #908] @ 0x38c │ │ streq r5, [pc], #-4052 @ 24683fc │ │ streq r6, [pc], #-572 @ 2468400 │ │ streq r5, [pc], #-4072 @ 2468404 │ │ streq r6, [pc], #-216 @ 2468408 │ │ streq r5, [pc], #-4072 @ 246840c │ │ streq r6, [pc], #-404 @ 2468410 │ │ streq r6, [pc], #-60 @ 2468414 │ │ @@ -1344471,38 +1344471,38 @@ │ │ streq r5, [pc], #-2644 @ 2468a3c │ │ streq r5, [pc], #-2500 @ 2468a40 │ │ streq r5, [pc], #-2544 @ 2468a44 │ │ streq r5, [pc], #-2504 @ 2468a48 │ │ streq r5, [pc], #-2876 @ 2468a4c │ │ streq r5, [pc], #-2860 @ 2468a50 │ │ eoreq r1, pc, r8, lsr r3 @ │ │ - ldc2l 12, cr3, [fp, #912] @ 0x390 │ │ - ldc2l 12, cr7, [fp, #616] @ 0x268 │ │ + ldc2l 13, cr3, [fp, #68] @ 0x44 │ │ + ldc2l 12, cr7, [fp, #796] @ 0x31c │ │ streq r5, [pc], #-2544 @ 2468a60 │ │ streq r5, [pc], #-2304 @ 2468a64 │ │ streq r5, [pc], #-2252 @ 2468a68 │ │ ldc2l 0, cr5, [lr, #892] @ 0x37c │ │ - ldc2l 12, cr7, [fp, #328] @ 0x148 │ │ + ldc2l 12, cr7, [fp, #508] @ 0x1fc │ │ streq r5, [pc], #-2688 @ 2468a74 │ │ streq r5, [pc], #-2344 @ 2468a78 │ │ streq r5, [pc], #-2180 @ 2468a7c │ │ ldc2l 6, cr1, [sp, #616] @ 0x268 │ │ - ldc2l 12, cr7, [fp, #40] @ 0x28 │ │ + ldc2l 12, cr7, [fp, #220] @ 0xdc │ │ streq r5, [pc], #-2688 @ 2468a88 │ │ streq r5, [pc], #-2440 @ 2468a8c │ │ streq r5, [pc], #-2108 @ 2468a90 │ │ ldc2l 14, cr14, [sp, #252] @ 0xfc │ │ - ldc2l 11, cr7, [fp, #776] @ 0x308 @ │ │ + ldc2l 11, cr7, [fp, #956] @ 0x3bc @ │ │ streq r5, [pc], #-2232 @ 2468a9c │ │ streq r5, [pc], #-2032 @ 2468aa0 │ │ streq r5, [pc], #-2036 @ 2468aa4 │ │ ldc2l 13, cr1, [fp, #1004] @ 0x3ec │ │ - ldc2l 11, cr7, [fp, #472] @ 0x1d8 @ │ │ + ldc2l 11, cr7, [fp, #652] @ 0x28c @ │ │ streq r5, [pc], #-2868 @ 2468ab0 │ │ - ldc2l 10, cr5, [ip, #812] @ 0x32c @ │ │ + ldc2l 10, cr5, [ip, #992] @ 0x3e0 @ │ │ streq r5, [pc], #-2232 @ 2468ab8 │ │ streq r5, [pc], #-1820 @ 2468abc │ │ streq r5, [pc], #-2184 @ 2468ac0 │ │ streq r5, [pc], #-1868 @ 2468ac4 │ │ streq r5, [pc], #-1560 @ 2468ac8 │ │ streq r5, [pc], #-1720 @ 2468acc │ │ ldc2l 13, cr15, [sl, #236] @ 0xec │ │ @@ -1344520,105 +1344520,105 @@ │ │ streq r5, [pc], #-1044 @ 2468b00 │ │ streq r5, [pc], #-580 @ 2468b04 │ │ eoreq r0, pc, r8, lsr ip @ │ │ eoreq r0, pc, r4, lsr ip @ │ │ streq r5, [pc], #-428 @ 2468b10 │ │ streq r5, [pc], #-392 @ 2468b14 │ │ ldc2l 15, cr0, [sp, #956] @ 0x3bc │ │ - ldc2l 5, cr7, [fp, #408] @ 0x198 │ │ + ldc2l 5, cr7, [fp, #588] @ 0x24c │ │ streq r5, [pc], #-340 @ 2468b20 │ │ strhteq r0, [pc], -r4 │ │ streq r5, [pc], #-640 @ 2468b28 │ │ streq r5, [pc], #-392 @ 2468b2c │ │ ldc2l 15, cr0, [sp, #652] @ 0x28c │ │ - ldc2l 5, cr7, [fp, #104] @ 0x68 │ │ + ldc2l 5, cr7, [fp, #284] @ 0x11c │ │ streq r5, [pc], #-224 @ 2468b38 │ │ streq r5, [pc], #-316 @ 2468b3c │ │ streq r5, [pc], #-296 @ 2468b40 │ │ streq r5, [pc], #-404 @ 2468b44 │ │ streq r5, [pc], #-160 @ 2468b48 │ │ streq r5, [pc], #-444 @ 2468b4c │ │ vcadd.f32 d20, d14, d8, #270 │ │ - ldc2l 3, cr7, [fp, #520] @ 0x208 │ │ + ldc2l 3, cr7, [fp, #700] @ 0x2bc │ │ streq r4, [pc], #-4036 @ 2468b58 │ │ ldc2l 6, cr4, [lr, #624] @ 0x270 │ │ - ldc2l 2, cr7, [fp, #88] @ 0x58 │ │ + ldc2l 2, cr7, [fp, #268] @ 0x10c │ │ streq r4, [pc], #-3672 @ 2468b64 │ │ ldc2l 6, cr4, [lr, #192] @ 0xc0 │ │ - ldc2l 1, cr7, [fp, #680] @ 0x2a8 │ │ + ldc2l 1, cr7, [fp, #860] @ 0x35c │ │ streq r4, [pc], #-3564 @ 2468b70 │ │ ldc2l 5, cr4, [lr, #816] @ 0x330 │ │ - ldc2l 1, cr7, [fp, #280] @ 0x118 │ │ + ldc2l 1, cr7, [fp, #460] @ 0x1cc │ │ streq r4, [pc], #-3464 @ 2468b7c │ │ ldc2l 5, cr4, [lr, #288] @ 0x120 │ │ - ldc2l 0, cr7, [fp, #776] @ 0x308 │ │ + ldc2l 0, cr7, [fp, #956] @ 0x3bc │ │ streq r4, [pc], #-3332 @ 2468b88 │ │ ldc2l 4, cr4, [lr, #1008] @ 0x3f0 │ │ - ldc2l 0, cr7, [fp, #472] @ 0x1d8 │ │ + ldc2l 0, cr7, [fp, #652] @ 0x28c │ │ streq r4, [pc], #-3260 @ 2468b94 │ │ streq r4, [pc], #-3892 @ 2468b98 │ │ streq r4, [pc], #-4044 @ 2468b9c │ │ streq r5, [pc], #-372 @ 2468ba0 │ │ streq r4, [pc], #-3920 @ 2468ba4 │ │ streq r5, [pc], #-20 @ 2468ba8 │ │ - ldc2l 15, cr8, [fp, #888] @ 0x378 │ │ - ldc2l 0, cr7, [fp, #216] @ 0xd8 │ │ + ldc2l 0, cr9, [fp, #44] @ 0x2c │ │ + ldc2l 0, cr7, [fp, #396] @ 0x18c │ │ streq r4, [pc], #-3436 @ 2468bb4 │ │ streq r4, [pc], #-3772 @ 2468bb8 │ │ streq r4, [pc], #-3176 @ 2468bbc │ │ streq r4, [pc], #-3128 @ 2468bc0 │ │ streq r4, [pc], #-3284 @ 2468bc4 │ │ streq r4, [pc], #-3168 @ 2468bc8 │ │ streq r4, [pc], #-3812 @ 2468bcc │ │ - ldc2l 15, cr0, [ip, #104] @ 0x68 │ │ - ldc2l 15, cr6, [fp, #712] @ 0x2c8 │ │ + ldc2l 15, cr0, [ip, #284] @ 0x11c │ │ + ldc2l 15, cr6, [fp, #892] @ 0x37c │ │ streq r4, [pc], #-3024 @ 2468bd8 │ │ streq r4, [pc], #-3096 @ 2468bdc │ │ streq r4, [pc], #-3044 @ 2468be0 │ │ streq r4, [pc], #-3000 @ 2468be4 │ │ streq r4, [pc], #-3156 @ 2468be8 │ │ streq r5, [pc], #-8 @ 2468bec │ │ - ldc2l 15, cr2, [fp, #512] @ 0x200 │ │ - ldc2l 15, cr6, [fp, #216] @ 0xd8 │ │ + ldc2l 15, cr2, [fp, #692] @ 0x2b4 │ │ + ldc2l 15, cr6, [fp, #396] @ 0x18c │ │ streq r4, [pc], #-3212 @ 2468bf8 │ │ streq r4, [pc], #-3084 @ 2468bfc │ │ streq r4, [pc], #-2920 @ 2468c00 │ │ streq r4, [pc], #-2880 @ 2468c04 │ │ streq r5, [pc], #-204 @ 2468c08 │ │ ldc2l 3, cr4, [lr, #364] @ 0x16c │ │ - ldc2l 14, cr6, [fp, #824] @ 0x338 │ │ + ldc2l 14, cr6, [fp, #1004] @ 0x3ec │ │ streq r4, [pc], #-3324 @ 2468c14 │ │ streq r4, [pc], #-2824 @ 2468c18 │ │ streq r4, [pc], #-2784 @ 2468c1c │ │ streq r5, [pc], #-256 @ 2468c20 │ │ ldc2l 8, cr0, [sp, #1000] @ 0x3e8 │ │ - ldc2l 14, cr6, [fp, #424] @ 0x1a8 │ │ + ldc2l 14, cr6, [fp, #604] @ 0x25c │ │ streq r4, [pc], #-3296 @ 2468c2c │ │ streq r4, [pc], #-2724 @ 2468c30 │ │ streq r4, [pc], #-2684 @ 2468c34 │ │ streq r4, [pc], #-3948 @ 2468c38 │ │ ldc2l 0, cr14, [sp, #572] @ 0x23c │ │ - ldc2l 14, cr6, [fp, #72] @ 0x48 │ │ + ldc2l 14, cr6, [fp, #252] @ 0xfc │ │ streq r4, [pc], #-2824 @ 2468c44 │ │ streq r4, [pc], #-2632 @ 2468c48 │ │ streq r4, [pc], #-2628 @ 2468c4c │ │ ldc2l 0, cr1, [fp, #300] @ 0x12c │ │ - ldc2l 13, cr6, [fp, #792] @ 0x318 │ │ + ldc2l 13, cr6, [fp, #972] @ 0x3cc │ │ streq r4, [pc], #-3952 @ 2468c58 │ │ streq r5, [pc], #-2036 @ 2468c5c │ │ streq r5, [pc], #-2044 @ 2468c60 │ │ streq r5, [pc], #-2012 @ 2468c64 │ │ streq r5, [pc], #-2016 @ 2468c68 │ │ streq r5, [pc], #-2052 @ 2468c6c │ │ streq r5, [pc], #-2464 @ 2468c70 │ │ streq r5, [pc], #-2176 @ 2468c74 │ │ streq r5, [pc], #-1884 @ 2468c78 │ │ streq r5, [pc], #-1936 @ 2468c7c │ │ ldc2l 14, cr0, [lr, #556] @ 0x22c │ │ - ldc2l 1, cr11, [fp, #692] @ 0x2b4 │ │ + ldc2l 1, cr11, [fp, #872] @ 0x368 │ │ ldc2l 15, cr10, [sp, #764] @ 0x2fc │ │ streq r5, [pc], #-1692 @ 2468c8c │ │ streq r5, [pc], #-2104 @ 2468c90 │ │ streq r5, [pc], #-1572 @ 2468c94 │ │ streq r5, [pc], #-1800 @ 2468c98 │ │ streq r5, [pc], #-1456 @ 2468c9c │ │ streq r5, [pc], #-1600 @ 2468ca0 │ │ @@ -1345013,33 +1345013,33 @@ │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #48 @ 0x30 │ │ vpop {d8-d9} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 2, cr12, [ip, #124] @ 0x7c │ │ - ldc2l 5, cr10, [fp, #368] @ 0x170 │ │ + ldc2l 2, cr12, [ip, #304] @ 0x130 │ │ + ldc2l 5, cr10, [fp, #548] @ 0x224 │ │ ldc2l 2, cr8, [sp, #652] @ 0x28c │ │ ldc2l 2, cr8, [sp, #316] @ 0x13c │ │ ldc2l 10, cr13, [sp, #572] @ 0x23c @ │ │ ldc2l 10, cr13, [sp, #380] @ 0x17c @ │ │ ldc2l 1, cr8, [sp, #444] @ 0x1bc │ │ ldc2l 9, cr13, [sp, #350] @ 0x15e @ │ │ ldc2l 9, cr13, [sp, #254] @ 0xfe @ │ │ ldc2l 0, cr8, [sp, #556] @ 0x22c │ │ vcadd.f32 , , , #270 │ │ ldc2l 8, cr13, [sp, #620] @ 0x26c │ │ ldc2l 15, cr7, [sp, #700] @ 0x2bc │ │ ldc2l 7, cr13, [sp, #492] @ 0x1ec │ │ ldc2l 7, cr13, [sp, #300] @ 0x12c │ │ - ldc2l 12, cr11, [ip, #892] @ 0x37c │ │ + ldc2l 13, cr11, [ip, #48] @ 0x30 │ │ ldc2l 10, cr9, [sp, #988] @ 0x3dc @ │ │ - ldc2l 12, cr9, [fp, #564] @ 0x234 │ │ - ldc2l 2, cr4, [ip, #1008] @ 0x3f0 │ │ + ldc2l 12, cr9, [fp, #744] @ 0x2e8 │ │ + ldc2l 3, cr4, [ip, #164] @ 0xa4 │ │ │ │ 024692fc : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #16 │ │ mov r5, r2 │ │ mov r6, r1 │ │ @@ -1345150,21 +1345150,21 @@ │ │ bl 270da10 │ │ mov r0, r4 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ - ldc2l 4, cr6, [fp, #600] @ 0x258 │ │ + ldc2l 4, cr6, [fp, #780] @ 0x30c │ │ ldc2l 1, cr7, [lr, #12] │ │ - ldc2l 11, cr9, [fp, #532] @ 0x214 @ │ │ - ldc2l 0, cr2, [ip, #404] @ 0x194 │ │ - ldc2l 3, cr6, [fp, #472] @ 0x1d8 │ │ + ldc2l 11, cr9, [fp, #712] @ 0x2c8 @ │ │ + ldc2l 0, cr2, [ip, #584] @ 0x248 │ │ + ldc2l 3, cr6, [fp, #652] @ 0x28c │ │ ldc2l 5, cr0, [fp, #904] @ 0x388 │ │ - ldc2l 10, cr9, [fp, #404] @ 0x194 @ │ │ + ldc2l 10, cr9, [fp, #584] @ 0x248 @ │ │ ldc2l 13, cr9, [sl, #676] @ 0x2a4 │ │ │ │ 024694ec : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #584 @ 0x248 │ │ sub sp, sp, #1024 @ 0x400 │ │ @@ -1345337,22 +1345337,22 @@ │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ nop {0} │ │ stclgt 12, cr12, [ip], {205} @ 0xcd │ │ svccc 0x00eccccc │ │ - ldc2l 1, cr2, [fp, #588] @ 0x24c │ │ + ldc2l 1, cr2, [fp, #768] @ 0x300 │ │ ldc2l 3, cr13, [sp, #168] @ 0xa8 │ │ - ldc2l 7, cr9, [fp, #740] @ 0x2e4 │ │ - ldc2l 0, cr2, [fp, #888] @ 0x378 │ │ - ldc2l 0, cr10, [fp, #4] │ │ - ldc2l 7, cr9, [fp, #964] @ 0x3c4 │ │ + ldc2l 7, cr9, [fp, #920] @ 0x398 │ │ + ldc2l 1, cr2, [fp, #44] @ 0x2c │ │ + ldc2l 0, cr10, [fp, #184] @ 0xb8 │ │ + ldc2l 8, cr9, [fp, #120] @ 0x78 │ │ ldc2l 4, cr14, [sl, #32] │ │ - ldc2l 0, cr2, [fp, #668] @ 0x29c │ │ + ldc2l 0, cr2, [fp, #848] @ 0x350 │ │ │ │ 024697c8 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ vpush {d8-d15} │ │ sub sp, sp, #384 @ 0x180 │ │ mov r4, r3 │ │ @@ -1345636,20 +1345636,20 @@ │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ nop {0} │ │ stclgt 12, cr12, [ip], {205} @ 0xcd │ │ svccc 0x00eccccc │ │ ldc2l 2, cr0, [fp, #616] @ 0x268 │ │ streq r3, [pc], #-3712 @ 2469c4c │ │ streq r3, [pc], #-3688 @ 2469c50 │ │ - ldc2l 14, cr9, [fp, #752] @ 0x2f0 │ │ - ldc2l 6, cr9, [fp, #100] @ 0x64 │ │ - ldc2l 15, cr1, [fp, #248] @ 0xf8 │ │ + ldc2l 14, cr9, [fp, #932] @ 0x3a4 │ │ + ldc2l 6, cr9, [fp, #280] @ 0x118 │ │ + ldc2l 15, cr1, [fp, #428] @ 0x1ac │ │ ldc2l 12, cr11, [sl, #80] @ 0x50 │ │ - ldc2l 6, cr9, [fp, #468] @ 0x1d4 │ │ - ldc2l 6, cr13, [ip, #972] @ 0x3cc │ │ + ldc2l 6, cr9, [fp, #648] @ 0x288 │ │ + ldc2l 7, cr13, [ip, #128] @ 0x80 │ │ streq r3, [pc], #-3192 @ 2469c6c │ │ mlaeq lr, r8, r2, pc @ │ │ ldc2l 14, cr15, [sl, #488] @ 0x1e8 │ │ │ │ 02469c70 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ @@ -1345717,18 +1345717,18 @@ │ │ vmov r0, r1, d16 │ │ sub sp, fp, #40 @ 0x28 │ │ vpop {d8-d10} │ │ pop {r4, r5, r6, r7, fp, pc} │ │ nop {0} │ │ frdnez f5, f0, #4.0 │ │ svccc 0x00e9eb85 │ │ - ldc2l 2, cr11, [ip, #520] @ 0x208 │ │ + ldc2l 2, cr11, [ip, #700] @ 0x2bc │ │ ldc2l 9, cr4, [lr, #202] @ 0xca @ │ │ - ldc2l 1, cr9, [fp, #900] @ 0x384 │ │ - ldc2l 10, cr7, [fp, #228] @ 0xe4 @ │ │ + ldc2l 2, cr9, [fp, #56] @ 0x38 │ │ + ldc2l 10, cr7, [fp, #408] @ 0x198 @ │ │ │ │ 02469d98 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ vpush {d8-d15} │ │ sub sp, sp, #120 @ 0x78 │ │ vldr d10, [r0, #8] │ │ @@ -1345898,18 +1345898,18 @@ │ │ vmla.f64 d9, d10, d16 │ │ vdiv.f64 d16, d18, d9 │ │ vsub.f64 d12, d12, d16 │ │ vmov r0, r1, d12 │ │ sub sp, fp, #88 @ 0x58 │ │ vpop {d8-d15} │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - ldc2l 8, cr3, [fp, #752] @ 0x2f0 │ │ + vcadd.f32 , , , #270 │ │ ldc2l 14, cr14, [sp, #328] @ 0x148 │ │ - ldc2l 0, cr9, [fp, #916] @ 0x394 │ │ - vcadd.f32 , q6, q4, #270 │ │ + ldc2l 1, cr9, [fp, #72] @ 0x48 │ │ + ldc2l 8, cr1, [ip, #468] @ 0x1d4 │ │ │ │ 0246a064 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #16 │ │ mov r8, r2 │ │ mov r5, r1 │ │ @@ -1346000,21 +1346000,21 @@ │ │ bl 270da10 │ │ mov r0, r4 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ - ldc2l 6, cr15, [fp, #576] @ 0x240 │ │ + ldc2l 6, cr15, [fp, #756] @ 0x2f4 │ │ ldc2l 3, cr6, [lr, #620] @ 0x26c │ │ - ldc2l 14, cr8, [fp, #116] @ 0x74 │ │ - ldc2l 2, cr1, [ip, #1012] @ 0x3f4 │ │ - ldc2l 5, cr15, [fp, #768] @ 0x300 │ │ + ldc2l 14, cr8, [fp, #296] @ 0x128 │ │ + ldc2l 3, cr1, [ip, #168] @ 0xa8 │ │ + ldc2l 5, cr15, [fp, #948] @ 0x3b4 │ │ vcadd.f32 , q13, q5, #270 │ │ - ldc2l 13, cr8, [fp, #308] @ 0x134 │ │ + ldc2l 13, cr8, [fp, #488] @ 0x1e8 │ │ ldc2l 0, cr9, [sl, #580] @ 0x244 │ │ │ │ 0246a204 : │ │ push {fp, lr} │ │ mov fp, sp │ │ vldmia r2, {d16-d17} │ │ vldr d18, [r3] │ │ @@ -1346478,22 +1346478,22 @@ │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #48 @ 0x30 │ │ vpop {d8-d9} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 0, cr15, [fp, #1020] @ 0x3fc │ │ + ldc2l 1, cr15, [fp, #176] @ 0xb0 │ │ ldc2l 2, cr12, [sp, #908] @ 0x38c │ │ ldc2l 11, cr8, [sl, #776] @ 0x308 @ │ │ ldc2l 2, cr12, [sp, #12] │ │ ldc2l 10, cr8, [sl, #920] @ 0x398 @ │ │ ldc2l 1, cr12, [sp, #124] @ 0x7c │ │ ldc2l 10, cr8, [sl, #8] @ │ │ - ldc2l 14, cr14, [fp, #172] @ 0xac │ │ + ldc2l 14, cr14, [fp, #352] @ 0x160 │ │ │ │ 0246a964 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d15} │ │ sub sp, sp, #40 @ 0x28 │ │ @@ -1347165,25 +1347165,25 @@ │ │ mov r0, #0 │ │ sub sp, fp, #96 @ 0x60 │ │ vpop {d8-d15} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 11, cr10, [sl, #636] @ 0x27c @ │ │ ldc2l 5, cr6, [sp, #92] @ 0x5c │ │ - ldc2l 4, cr8, [fp, #900] @ 0x384 │ │ - ldc2l 10, cr10, [fp, #140] @ 0x8c @ │ │ + ldc2l 5, cr8, [fp, #56] @ 0x38 │ │ + ldc2l 10, cr10, [fp, #320] @ 0x140 @ │ │ ldc2l 11, cr10, [sl, #876] @ 0x36c @ │ │ vcadd.f32 q10, , q9, #270 │ │ - ldc2l 10, cr6, [ip, #772] @ 0x304 @ │ │ + ldc2l 10, cr6, [ip, #952] @ 0x3b8 @ │ │ ldc2l 3, cr8, [sp, #8] │ │ vcadd.f32 d21, d30, d11, #270 │ │ - ldc2l 12, cr12, [fp, #560] @ 0x230 │ │ + ldc2l 12, cr12, [fp, #740] @ 0x2e4 │ │ ldc2l 2, cr8, [sp, #376] @ 0x178 │ │ ldc2l 7, cr5, [lr, #924] @ 0x39c │ │ - ldc2l 11, cr12, [fp, #912] @ 0x390 @ │ │ + ldc2l 12, cr12, [fp, #68] @ 0x44 │ │ ldc2l 1, cr8, [sp, #248] @ 0xf8 │ │ ldc2l 6, cr5, [lr, #716] @ 0x2cc │ │ ldc2l 6, cr5, [lr, #492] @ 0x1ec │ │ ldc2l 6, cr5, [lr, #156] @ 0x9c │ │ ldc2l 5, cr5, [lr, #892] @ 0x37c │ │ ldc2l 5, cr5, [lr, #652] @ 0x28c │ │ ldc2l 5, cr5, [lr, #412] @ 0x19c │ │ @@ -1347296,16 +1347296,16 @@ │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 5, cr14, [sl, #740] @ 0x2e4 │ │ ldc2l 15, cr4, [lr, #300] @ 0x12c │ │ - ldc2l 9, cr7, [fp, #410] @ 0x19a @ │ │ - ldc2l 14, cr15, [fp, #692] @ 0x2b4 │ │ + ldc2l 9, cr7, [fp, #500] @ 0x1f4 @ │ │ + ldc2l 14, cr15, [fp, #872] @ 0x368 │ │ ldc2l 4, cr14, [sl, #756] @ 0x2f4 │ │ │ │ 0246b608 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r6, r3 │ │ mov r7, r2 │ │ @@ -1347445,21 +1347445,21 @@ │ │ vstr d16, [ip] │ │ vldr d16, [r0] │ │ vldr d17, [r4] │ │ vmul.f64 d16, d17, d16 │ │ vstr d16, [r0] │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 0, cr2, [fp, #60] @ 0x3c │ │ + ldc2l 0, cr2, [fp, #240] @ 0xf0 │ │ ldc2l 11, cr1, [sp, #972] @ 0x3cc @ │ │ - ldc2l 8, cr7, [fp, #196] @ 0xc4 │ │ + ldc2l 8, cr7, [fp, #376] @ 0x178 │ │ ldc2l 13, cr4, [lr, #860] @ 0x35c │ │ - ldc2l 15, cr1, [fp, #812] @ 0x32c │ │ + ldc2l 15, cr1, [fp, #992] @ 0x3e0 │ │ ldc2l 3, cr14, [sl, #424] @ 0x1a8 │ │ - ldc2l 7, cr7, [fp, #948] @ 0x3b4 │ │ + ldc2l 8, cr7, [fp, #104] @ 0x68 │ │ ldc2l 11, cr7, [sl, #212] @ 0xd4 @ │ │ │ │ 0246b868 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d12} │ │ @@ -1348284,97 +1348284,97 @@ │ │ bl 270da30 │ │ ldr r2, [pc, #536] @ 246c764 │ │ mov r1, r0 │ │ ldr r2, [pc, r2] │ │ sub r0, r2, #1 │ │ b 246c4b0 │ │ streq r2, [pc], #-1540 @ 246c560 │ │ - ldc2l 15, cr15, [sl, #580] @ 0x244 │ │ - ldc2l 15, cr9, [fp, #812] @ 0x32c │ │ - ldc2l 6, cr7, [fp, #148] @ 0x94 │ │ + ldc2l 15, cr15, [sl, #760] @ 0x2f8 │ │ + ldc2l 15, cr9, [fp, #992] @ 0x3e0 │ │ + ldc2l 6, cr7, [fp, #328] @ 0x148 │ │ streq r2, [pc], #-1480 @ 246c570 │ │ eoreq sp, lr, r0, asr r6 │ │ ldc2l 1, cr11, [sp, #872] @ 0x368 │ │ eoreq sp, lr, ip, lsr #12 │ │ streq r2, [pc], #-1388 @ 246c580 │ │ streq r2, [pc], #-1392 @ 246c584 │ │ streq r2, [pc], #-116 @ 246c588 │ │ streq r2, [pc], #-1392 @ 246c58c │ │ streq r2, [pc], #-1356 @ 246c590 │ │ streq r2, [pc], #-1344 @ 246c594 │ │ streq r2, [pc], #-220 @ 246c598 │ │ - vcadd.f32 d26, d12, d17, #270 │ │ - ldc2l 11, cr3, [ip, #432] @ 0x1b0 @ │ │ + vcadd.f32 q13, q6, q7, #270 │ │ + ldc2l 11, cr3, [ip, #612] @ 0x264 @ │ │ streq r2, [pc], #-1180 @ 246c5a4 │ │ streq r2, [pc], #-412 @ 246c5a8 │ │ streq r2, [pc], #-148 @ 246c5ac │ │ streq r2, [pc], #-132 @ 246c5b0 │ │ streq r2, [pc], #-1136 @ 246c5b4 │ │ streq r2, [pc], #-1064 @ 246c5b8 │ │ streq r2, [pc], #-224 @ 246c5bc │ │ streq r1, [pc], #-4084 @ 246c5c0 │ │ streq r2, [pc], #-1008 @ 246c5c4 │ │ streq r2, [pc], #-192 @ 246c5c8 │ │ streq r2, [pc], #-1028 @ 246c5cc │ │ streq r2, [pc], #-1000 @ 246c5d0 │ │ streq r2, [pc], #-728 @ 246c5d4 │ │ - ldc2l 10, cr3, [ip, #240] @ 0xf0 @ │ │ + ldc2l 10, cr3, [ip, #420] @ 0x1a4 @ │ │ ldc2l 11, cr2, [lr, #508] @ 0x1fc @ │ │ streq r1, [pc], #-3684 @ 246c5e0 │ │ - ldc2l 11, cr15, [sl, #660] @ 0x294 @ │ │ + ldc2l 11, cr15, [sl, #840] @ 0x348 @ │ │ ldc2l 13, cr8, [sp, #528] @ 0x210 │ │ - ldc2l 2, cr7, [fp, #228] @ 0xe4 │ │ + ldc2l 2, cr7, [fp, #408] @ 0x198 │ │ streq r1, [pc], #-3504 @ 246c5f0 │ │ ldc2l 15, cr12, [sp, #944] @ 0x3b0 │ │ - ldc2l 11, cr15, [sl, #372] @ 0x174 @ │ │ + ldc2l 11, cr15, [sl, #552] @ 0x228 @ │ │ streq r1, [pc], #-3860 @ 246c5fc │ │ streq r1, [pc], #-3812 @ 246c600 │ │ streq r1, [pc], #-3596 @ 246c604 │ │ ldc2l 15, cr12, [sp, #880] @ 0x370 │ │ streq r1, [pc], #-3752 @ 246c60c │ │ mlaeq lr, ip, r2, sp │ │ streq r1, [pc], #-3680 @ 246c614 │ │ streq r1, [pc], #-3460 @ 246c618 │ │ - ldc2l 11, cr11, [fp, #228] @ 0xe4 @ │ │ + ldc2l 11, cr11, [fp, #408] @ 0x198 @ │ │ streq r1, [pc], #-3604 @ 246c620 │ │ streq r1, [pc], #-3560 @ 246c624 │ │ streq r1, [pc], #-3748 @ 246c628 │ │ streq r1, [pc], #-3664 @ 246c62c │ │ streq r1, [pc], #-3424 @ 246c630 │ │ ldc2l 11, cr12, [sp, #504] @ 0x1f8 @ │ │ - ldc2l 7, cr3, [ip, #944] @ 0x3b0 │ │ + ldc2l 8, cr3, [ip, #100] @ 0x64 │ │ streq r1, [pc], #-3360 @ 246c63c │ │ streq r2, [pc], #-244 @ 246c640 │ │ streq r2, [pc], #-312 @ 246c644 │ │ streq r2, [pc], #-216 @ 246c648 │ │ eoreq sp, lr, ip, lsr #1 │ │ streq r1, [pc], #-4068 @ 246c650 │ │ ldc2l 10, cr12, [sp, #856] @ 0x358 @ │ │ - ldc2l 7, cr3, [ip, #272] @ 0x110 │ │ + ldc2l 7, cr3, [ip, #452] @ 0x1c4 │ │ streq r2, [pc], #-116 @ 246c65c │ │ streq r2, [pc], #-100 @ 246c660 │ │ ldc2l 13, cr12, [sp, #112] @ 0x70 │ │ streq r1, [pc], #-3048 @ 246c668 │ │ streq r2, [pc], #-60 @ 246c66c │ │ streq r1, [pc], #-2984 @ 246c670 │ │ - vcadd.f32 d27, d27, d5, #270 │ │ + ldc2l 8, cr11, [fp, #712] @ 0x2c8 │ │ streq r1, [pc], #-2924 @ 246c678 │ │ streq r1, [pc], #-3948 @ 246c67c │ │ streq r1, [pc], #-3896 @ 246c680 │ │ streq r1, [pc], #-2848 @ 246c684 │ │ streq r1, [pc], #-2792 @ 246c688 │ │ streq r2, [pc], #-240 @ 246c68c │ │ streq r2, [pc], #-228 @ 246c690 │ │ streq r2, [pc], #-132 @ 246c694 │ │ streq r1, [pc], #-2768 @ 246c698 │ │ streq r1, [pc], #-3884 @ 246c69c │ │ ldc2l 8, cr12, [sp, #968] @ 0x3c8 │ │ - ldc2l 5, cr3, [ip, #384] @ 0x180 │ │ - ldc2l 2, cr10, [ip, #52] @ 0x34 │ │ - ldc2l 5, cr1, [ip, #800] @ 0x320 │ │ + ldc2l 5, cr3, [ip, #564] @ 0x234 │ │ + ldc2l 2, cr10, [ip, #232] @ 0xe8 │ │ + ldc2l 5, cr1, [ip, #980] @ 0x3d4 │ │ streq r1, [pc], #-3672 @ 246c6b0 │ │ streq r1, [pc], #-2520 @ 246c6b4 │ │ streq r1, [pc], #-2472 @ 246c6b8 │ │ streq r1, [pc], #-2696 @ 246c6bc │ │ streq r1, [pc], #-3488 @ 246c6c0 │ │ streq r1, [pc], #-2404 @ 246c6c4 │ │ streq r1, [pc], #-2604 @ 246c6c8 │ │ @@ -1348384,51 +1348384,51 @@ │ │ streq r1, [pc], #-3464 @ 246c6d8 │ │ streq r1, [pc], #-2352 @ 246c6dc │ │ streq r1, [pc], #-2564 @ 246c6e0 │ │ ldc2l 8, cr8, [sp, #708] @ 0x2c4 │ │ streq r1, [pc], #-2284 @ 246c6e8 │ │ streq r1, [pc], #-2500 @ 246c6ec │ │ streq r1, [pc], #-3332 @ 246c6f0 │ │ - ldc2l 1, cr7, [fp, #960] @ 0x3c0 │ │ + ldc2l 2, cr7, [fp, #116] @ 0x74 │ │ streq r1, [pc], #-2208 @ 246c6f8 │ │ streq r1, [pc], #-2692 @ 246c6fc │ │ streq r1, [pc], #-3244 @ 246c700 │ │ streq r1, [pc], #-3004 @ 246c704 │ │ ldc2l 6, cr12, [sp, #696] @ 0x2b8 │ │ - ldc2l 3, cr3, [ip, #112] @ 0x70 │ │ + ldc2l 3, cr3, [ip, #292] @ 0x124 │ │ ldc2l 9, cr12, [sp, #104] @ 0x68 @ │ │ streq r1, [pc], #-2048 @ 246c714 │ │ strdeq ip, [lr], -r8 @ │ │ streq r1, [pc], #-3148 @ 246c71c │ │ streq r1, [pc], #-1976 @ 246c720 │ │ - ldc2l 4, cr11, [fp, #596] @ 0x254 │ │ + ldc2l 4, cr11, [fp, #776] @ 0x308 │ │ streq r1, [pc], #-1916 @ 246c728 │ │ streq r1, [pc], #-2940 @ 246c72c │ │ streq r1, [pc], #-2888 @ 246c730 │ │ streq r1, [pc], #-1840 @ 246c734 │ │ streq r1, [pc], #-2124 @ 246c738 │ │ streq r1, [pc], #-1788 @ 246c73c │ │ streq r1, [pc], #-2820 @ 246c740 │ │ streq r1, [pc], #-2808 @ 246c744 │ │ ldc2l 5, cr12, [sp, #56] @ 0x38 │ │ - ldc2l 1, cr3, [ip, #496] @ 0x1f0 │ │ - ldc2l 14, cr9, [ip, #164] @ 0xa4 │ │ - ldc2l 1, cr1, [ip, #928] @ 0x3a0 │ │ + ldc2l 1, cr3, [ip, #676] @ 0x2a4 │ │ + ldc2l 14, cr9, [ip, #344] @ 0x158 │ │ + ldc2l 2, cr1, [ip, #84] @ 0x54 │ │ streq r1, [pc], #-2680 @ 246c758 │ │ streq r1, [pc], #-1444 @ 246c75c │ │ streq r1, [pc], #-1396 @ 246c760 │ │ streq r1, [pc], #-1620 @ 246c764 │ │ streq r1, [pc], #-2412 @ 246c768 │ │ streq r1, [pc], #-1328 @ 246c76c │ │ streq r1, [pc], #-1608 @ 246c770 │ │ ldc2l 5, cr8, [sp, #916] @ 0x394 │ │ streq r1, [pc], #-1560 @ 246c778 │ │ streq r1, [pc], #-1776 @ 246c77c │ │ streq r1, [pc], #-2620 @ 246c780 │ │ - ldc2l 15, cr6, [fp, #128] @ 0x80 │ │ + ldc2l 15, cr6, [fp, #308] @ 0x134 │ │ streq r1, [pc], #-1488 @ 246c788 │ │ streq r1, [pc], #-1700 @ 246c78c │ │ │ │ 0246c788 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ vpush {d8-d10} │ │ @@ -1348678,23 +1348678,23 @@ │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ eoreq ip, lr, r4, asr #11 │ │ streq r1, [pc], #-2952 @ 246cb70 │ │ streq r1, [pc], #-1320 @ 246cb74 │ │ ldc2l 15, cr9, [sp, #556] @ 0x22c │ │ - ldc2l 13, cr4, [fp, #668] @ 0x29c │ │ + ldc2l 13, cr4, [fp, #848] @ 0x350 │ │ ldc2l 15, cr9, [sp, #252] @ 0xfc │ │ - ldc2l 13, cr4, [fp, #364] @ 0x16c │ │ + ldc2l 13, cr4, [fp, #544] @ 0x220 │ │ ldc2l 14, cr9, [sp, #972] @ 0x3cc │ │ - ldc2l 13, cr4, [fp, #60] @ 0x3c │ │ + ldc2l 13, cr4, [fp, #240] @ 0xf0 │ │ ldc2l 14, cr9, [sp, #668] @ 0x29c │ │ - ldc2l 12, cr4, [fp, #780] @ 0x30c │ │ + ldc2l 12, cr4, [fp, #960] @ 0x3c0 │ │ ldc2l 14, cr9, [sp, #364] @ 0x16c │ │ - ldc2l 12, cr4, [fp, #476] @ 0x1dc │ │ + ldc2l 12, cr4, [fp, #656] @ 0x290 │ │ │ │ 0246cb98 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ vpush {d8} │ │ mov r8, r3 │ │ mov r7, r2 │ │ @@ -1348820,21 +1348820,21 @@ │ │ vld1.64 {d20-d21}, [r4]! │ │ subs r3, r3, #2 │ │ vst1.64 {d20-d21}, [r7]! │ │ bne 246cd88 │ │ cmp r1, r2 │ │ bne 246cc90 │ │ b 246ccb8 │ │ - ldc2l 13, cr8, [fp, #188] @ 0xbc │ │ + ldc2l 13, cr8, [fp, #368] @ 0x170 │ │ ldc2l 2, cr4, [sp, #972] @ 0x3cc │ │ - ldc2l 2, cr6, [fp, #756] @ 0x2f4 │ │ - ldc2l 7, cr8, [fp, #1020] @ 0x3fc │ │ - ldc2l 13, cr8, [fp, #396] @ 0x18c │ │ + ldc2l 2, cr6, [fp, #936] @ 0x3a8 │ │ + vcadd.f32 d24, d11, d28, #270 │ │ + ldc2l 13, cr8, [fp, #576] @ 0x240 │ │ ldc2l 6, cr2, [sp, #728] @ 0x2d8 │ │ - ldc2l 8, cr4, [ip, #596] @ 0x254 │ │ + vcadd.f32 q10, q14, q1, #270 │ │ │ │ 0246cdc0 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #16 │ │ mov r4, r3 │ │ mov r5, r2 │ │ @@ -1348928,19 +1348928,19 @@ │ │ str r0, [sp, #4] │ │ mov r0, r6 │ │ bl 270d370 │ │ b 246cea8 │ │ ldc2l 12, cr12, [sl, #720] @ 0x2d0 │ │ eoreq ip, lr, r4, asr r1 │ │ eoreq ip, lr, r0, asr #2 │ │ - ldc2l 8, cr14, [fp, #376] @ 0x178 │ │ - ldc2l 0, cr6, [fp, #596] @ 0x254 │ │ + vcadd.f32 d30, d27, d11, #270 │ │ + ldc2l 0, cr6, [fp, #776] @ 0x308 │ │ ldc2l 2, cr12, [ip, #520] @ 0x208 │ │ ldc2l 12, cr9, [sp, #152] @ 0x98 │ │ - ldc2l 0, cr6, [fp, #100] @ 0x64 │ │ + ldc2l 0, cr6, [fp, #280] @ 0x118 │ │ ldc2l 9, cr13, [sp, #238] @ 0xee @ │ │ ldc2l 11, cr12, [sl, #976] @ 0x3d0 @ │ │ │ │ 0246cf68 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ @@ -1349467,15 +1349467,15 @@ │ │ bl 270d370 │ │ mov r0, r8 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ - ldc2l 0, cr12, [fp, #616] @ 0x268 │ │ + ldc2l 0, cr12, [fp, #796] @ 0x31c │ │ mlaeq lr, r4, r8, fp │ │ mlaeq lr, r0, r8, fp │ │ │ │ 0246d7a4 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #64 @ 0x40 │ │ @@ -1349873,32 +1349873,32 @@ │ │ add r4, pc, r4 │ │ mov r1, r4 │ │ bl 270e100 │ │ add r2, r9, #48 @ 0x30 │ │ mov r0, r6 │ │ mov r1, r4 │ │ b 246dd04 │ │ - ldc2l 14, cr13, [fp, #444] @ 0x1bc │ │ + ldc2l 14, cr13, [fp, #624] @ 0x270 │ │ eoreq fp, lr, r0, lsl #13 │ │ eoreq fp, lr, ip, ror r6 │ │ ldc2l 8, cr13, [ip, #852] @ 0x354 │ │ - ldc2l 5, cr5, [fp, #276] @ 0x114 │ │ - ldc2l 12, cr15, [sl, #968] @ 0x3c8 │ │ + ldc2l 5, cr5, [fp, #456] @ 0x1c8 │ │ + ldc2l 13, cr15, [sl, #124] @ 0x7c │ │ ldrdeq fp, [lr], -r8 @ │ │ ldc2l 11, cr7, [sp, #944] @ 0x3b0 @ │ │ ldc2l 14, cr9, [sl, #212] @ 0xd4 │ │ ldc2l 11, cr7, [sp, #688] @ 0x2b0 @ │ │ ldc2l 13, cr9, [sl, #980] @ 0x3d4 │ │ eoreq fp, lr, r0, asr #3 │ │ ldc2l 12, cr7, [sp, #800] @ 0x320 │ │ ldc2l 15, cr9, [sl, #68] @ 0x44 │ │ ldc2l 12, cr7, [sp, #544] @ 0x220 │ │ ldc2l 14, cr9, [sl, #836] @ 0x344 │ │ eoreq fp, lr, r8, lsl #5 │ │ - ldc2l 10, cr13, [fp, #284] @ 0x11c @ │ │ + ldc2l 10, cr13, [fp, #464] @ 0x1d0 @ │ │ │ │ 0246de28 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d9} │ │ sub sp, sp, #112 @ 0x70 │ │ @@ -1350050,22 +1350050,22 @@ │ │ mov r0, #0 │ │ sub sp, fp, #48 @ 0x30 │ │ vpop {d8-d9} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ eoreq fp, lr, r4, lsr #2 │ │ eoreq fp, lr, r0, lsr #2 │ │ - ldc2l 2, cr5, [ip, #728] @ 0x2d8 │ │ + ldc2l 2, cr5, [ip, #908] @ 0x38c │ │ ldc2l 13, cr14, [sp, #164] @ 0xa4 │ │ - ldc2l 15, cr4, [fp, #612] @ 0x264 │ │ - ldc2l 7, cr15, [sl, #280] @ 0x118 │ │ - ldc2l 2, cr5, [ip, #424] @ 0x1a8 │ │ - vcadd.f32 d19, d11, d11, #270 │ │ - ldc2l 15, cr4, [fp, #308] @ 0x134 │ │ - ldc2l 7, cr3, [fp, #996] @ 0x3e4 │ │ + ldc2l 15, cr4, [fp, #792] @ 0x318 │ │ + ldc2l 7, cr15, [sl, #460] @ 0x1cc │ │ + ldc2l 2, cr5, [ip, #604] @ 0x25c │ │ + ldc2l 8, cr3, [fp, #224] @ 0xe0 │ │ + ldc2l 15, cr4, [fp, #488] @ 0x1e8 │ │ + vcadd.f32 d19, d11, d22, #270 │ │ │ │ 0246e0bc : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d9} │ │ sub sp, sp, #920 @ 0x398 │ │ @@ -1350384,28 +1350384,28 @@ │ │ mov r0, #0 │ │ sub sp, fp, #48 @ 0x30 │ │ vpop {d8-d9} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ mlaeq lr, r8, lr, sl │ │ mlaeq lr, r4, lr, sl │ │ - ldc2l 5, cr3, [fp, #352] @ 0x160 │ │ + ldc2l 5, cr3, [fp, #532] @ 0x214 │ │ ldc2l 7, cr6, [sp, #780] @ 0x30c │ │ - ldc2l 12, cr4, [fp, #228] @ 0xe4 │ │ - ldc2l 3, cr15, [sl, #920] @ 0x398 │ │ - ldc2l 5, cr3, [fp, #48] @ 0x30 │ │ - ldc2l 4, cr3, [fp, #684] @ 0x2ac │ │ - ldc2l 11, cr4, [fp, #948] @ 0x3b4 @ │ │ - ldc2l 4, cr3, [fp, #612] @ 0x264 │ │ + ldc2l 12, cr4, [fp, #408] @ 0x198 │ │ + ldc2l 4, cr15, [sl, #76] @ 0x4c │ │ + ldc2l 5, cr3, [fp, #228] @ 0xe4 │ │ + ldc2l 4, cr3, [fp, #864] @ 0x360 │ │ + ldc2l 12, cr4, [fp, #104] @ 0x68 │ │ + ldc2l 4, cr3, [fp, #792] @ 0x318 │ │ ldc2l 9, cr14, [ip, #408] @ 0x198 @ │ │ - ldc2l 2, cr3, [ip, #480] @ 0x1e0 │ │ + ldc2l 2, cr3, [ip, #660] @ 0x294 │ │ ldc2l 7, cr14, [ip, #656] @ 0x290 │ │ - ldc2l 0, cr3, [ip, #320] @ 0x140 │ │ + ldc2l 0, cr3, [ip, #500] @ 0x1f4 │ │ ldc2l 7, cr14, [ip, #320] @ 0x140 │ │ - ldc2l 15, cr2, [ip, #1008] @ 0x3f0 │ │ + ldc2l 0, cr3, [ip, #164] @ 0xa4 │ │ │ │ 0246e604 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ mov r4, r3 │ │ mov r7, r2 │ │ @@ -1350552,15 +1350552,15 @@ │ │ mov r3, r4 │ │ bl 270f610 │ │ mov r0, r8 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - ldc2l 12, cr2, [ip, #608] @ 0x260 │ │ + ldc2l 12, cr2, [ip, #788] @ 0x314 │ │ │ │ 0246e860 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ mov r4, r3 │ │ mov r5, r2 │ │ mov r6, r1 │ │ @@ -1350581,15 +1350581,15 @@ │ │ mov r3, r4 │ │ bl 270f590 │ │ mov r0, r8 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - ldc2l 14, cr14, [sl, #248] @ 0xf8 │ │ + ldc2l 14, cr14, [sl, #428] @ 0x1ac │ │ │ │ 0246e8cc : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #32 │ │ mov r6, r3 │ │ mov r5, r2 │ │ @@ -1350661,20 +1350661,20 @@ │ │ ldr r0, [pc, #40] @ 246ea14 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - ldc2l 0, cr7, [fp, #344] @ 0x158 │ │ - ldc2l 14, cr2, [fp, #492] @ 0x1ec │ │ - ldc2l 5, cr4, [fp, #756] @ 0x2f4 │ │ - ldc2l 14, cr2, [fp, #420] @ 0x1a4 │ │ + ldc2l 0, cr7, [fp, #524] @ 0x20c │ │ + ldc2l 14, cr2, [fp, #672] @ 0x2a0 │ │ + ldc2l 5, cr4, [fp, #936] @ 0x3a8 │ │ + ldc2l 14, cr2, [fp, #600] @ 0x258 │ │ eoreq sl, lr, r8, lsl r6 │ │ - ldc2l 15, cr6, [fp, #408] @ 0x198 │ │ + ldc2l 15, cr6, [fp, #588] @ 0x24c │ │ │ │ 0246ea18 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #64 @ 0x40 │ │ mov r4, r3 │ │ mov r6, r1 │ │ @@ -1350747,19 +1350747,19 @@ │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldc2l 8, cr12, [ip, #496] @ 0x1f0 │ │ eoreq sl, lr, r4, asr r5 │ │ eoreq sl, lr, r0, asr r5 │ │ ldc2l 7, cr10, [ip, #760] @ 0x2f8 │ │ - ldc2l 4, cr4, [fp, #196] @ 0xc4 │ │ - ldc2l 11, cr14, [sl, #888] @ 0x378 @ │ │ - ldc2l 7, cr4, [ip, #52] @ 0x34 │ │ - ldc2l 3, cr4, [fp, #996] @ 0x3e4 │ │ - ldc2l 9, cr2, [ip, #342] @ 0x156 @ │ │ + ldc2l 4, cr4, [fp, #376] @ 0x178 │ │ + ldc2l 12, cr14, [sl, #44] @ 0x2c │ │ + ldc2l 7, cr4, [ip, #232] @ 0xe8 │ │ + ldc2l 4, cr4, [fp, #152] @ 0x98 │ │ + ldc2l 9, cr2, [ip, #432] @ 0x1b0 @ │ │ ldc2l 7, cr12, [ip, #592] @ 0x250 │ │ │ │ 0246eb68 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #64 @ 0x40 │ │ mov r4, r3 │ │ @@ -1350839,20 +1350839,20 @@ │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldc2l 7, cr10, [ip, #168] @ 0xa8 │ │ eoreq sl, lr, ip, lsl #8 │ │ eoreq sl, lr, r8, lsl #8 │ │ ldc2l 14, cr10, [sl, #636] @ 0x27c │ │ - ldc2l 2, cr4, [fp, #900] @ 0x384 │ │ - ldc2l 10, cr14, [sl, #568] @ 0x238 @ │ │ + ldc2l 3, cr4, [fp, #56] @ 0x38 │ │ + ldc2l 10, cr14, [sl, #748] @ 0x2ec @ │ │ ldc2l 6, cr4, [sl, #200] @ 0xc8 │ │ - ldc2l 2, cr4, [fp, #676] @ 0x2a4 │ │ + ldc2l 2, cr4, [fp, #856] @ 0x358 │ │ eoreq sl, lr, ip, asr #6 │ │ - vcadd.f32 q9, q6, , #270 │ │ + ldc2l 8, cr2, [ip, #448] @ 0x1c0 │ │ ldc2l 6, cr10, [ip, #168] @ 0xa8 │ │ │ │ 0246ecd4 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #940 @ 0x3ac │ │ mov sl, r3 │ │ @@ -1351198,42 +1351198,42 @@ │ │ sub r0, r0, #1 │ │ str r0, [fp, #-40] @ 0xffffffd8 │ │ mov r0, r4 │ │ add r3, r6, r2, lsl #3 │ │ sub r2, fp, #40 @ 0x28 │ │ bl 270d370 │ │ b 246ee94 │ │ - ldc2l 11, cr12, [sl, #304] @ 0x130 @ │ │ + ldc2l 11, cr12, [sl, #484] @ 0x1e4 @ │ │ eoreq sl, lr, r8, lsr #5 │ │ eoreq sl, lr, r4, lsr #5 │ │ ldc2l 4, cr0, [sp, #744] @ 0x2e8 │ │ ldc2l 2, cr0, [sp, #756] @ 0x2f4 │ │ - ldc2l 8, cr14, [sl, #584] @ 0x248 │ │ - ldc2l 9, cr2, [fp, #206] @ 0xce @ │ │ - ldc2l 0, cr4, [fp, #676] @ 0x2a4 │ │ - ldc2l 9, cr2, [fp, #170] @ 0xaa @ │ │ - ldc2l 10, cr2, [fp, #140] @ 0x8c @ │ │ - ldc2l 1, cr4, [fp, #68] @ 0x44 │ │ + ldc2l 8, cr14, [sl, #764] @ 0x2fc │ │ + ldc2l 9, cr2, [fp, #296] @ 0x128 @ │ │ + ldc2l 0, cr4, [fp, #856] @ 0x358 │ │ + ldc2l 9, cr2, [fp, #260] @ 0x104 @ │ │ + ldc2l 10, cr2, [fp, #320] @ 0x140 @ │ │ + ldc2l 1, cr4, [fp, #248] @ 0xf8 │ │ ldc2l 12, cr5, [sp, #804] @ 0x324 │ │ ldc2l 3, cr12, [ip, #604] @ 0x25c │ │ - ldc2l 15, cr3, [fp, #772] @ 0x304 │ │ - ldc2l 9, cr2, [fp, #144] @ 0x90 @ │ │ - ldc2l 15, cr3, [fp, #564] @ 0x234 │ │ + ldc2l 15, cr3, [fp, #952] @ 0x3b8 │ │ + ldc2l 9, cr2, [fp, #234] @ 0xea @ │ │ + ldc2l 15, cr3, [fp, #744] @ 0x2e8 │ │ ldc2l 11, cr7, [sp, #572] @ 0x23c @ │ │ - ldc2l 15, cr3, [fp, #52] @ 0x34 │ │ - ldc2l 5, cr14, [fp, #496] @ 0x1f0 │ │ - ldc2l 9, cr2, [fp, #156] @ 0x9c @ │ │ + ldc2l 15, cr3, [fp, #232] @ 0xe8 │ │ + ldc2l 5, cr14, [fp, #676] @ 0x2a4 │ │ + ldc2l 9, cr2, [fp, #246] @ 0xf6 @ │ │ ldc2l 3, cr14, [ip] │ │ ldc2l 13, cr13, [sp, #220] @ 0xdc │ │ - ldc2l 3, cr2, [ip, #844] @ 0x34c │ │ + ldc2l 4, cr2, [ip] │ │ ldc2l 11, cr13, [ip, #432] @ 0x1b0 @ │ │ ldc2l 2, cr10, [ip, #148] @ 0x94 │ │ - ldc2l 9, cr12, [sl, #360] @ 0x168 @ │ │ - ldc2l 9, cr12, [sl, #158] @ 0x9e @ │ │ - ldc2l 15, cr3, [fp, #916] @ 0x394 │ │ + ldc2l 9, cr12, [sl, #450] @ 0x1c2 @ │ │ + ldc2l 9, cr12, [sl, #248] @ 0xf8 @ │ │ + ldc2l 0, cr4, [fp, #72] @ 0x48 │ │ │ │ 0246f2bc : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #964 @ 0x3c4 │ │ mov r9, r3 │ │ mov r6, r2 │ │ @@ -1352021,52 +1352021,52 @@ │ │ strb r0, [r1] │ │ b 246f688 │ │ ldc2l 0, cr0, [sp, #120] @ 0x78 │ │ streq pc, [lr], #-2164 @ 0xfffff78c │ │ streq pc, [lr], #-2164 @ 0xfffff78c │ │ ldrdeq r9, [lr], -r0 @ │ │ eoreq r9, lr, ip, asr #25 │ │ - ldc2l 1, cr2, [fp, #668] @ 0x29c │ │ - vcadd.f32 , , , #270 │ │ - ldc2l 1, cr2, [fp, #596] @ 0x254 │ │ + ldc2l 1, cr2, [fp, #848] @ 0x350 │ │ + ldc2l 9, cr3, [fp, #44] @ 0x2c @ │ │ + ldc2l 1, cr2, [fp, #776] @ 0x308 │ │ streq pc, [lr], #-2048 @ 0xfffff800 │ │ eoreq r9, lr, r8, asr ip │ │ eoreq r9, lr, r8, asr r9 │ │ streq pc, [lr], #-1244 @ 0xfffffb24 │ │ eoreq r9, lr, r8, lsr r9 │ │ streq pc, [lr], #-1212 @ 0xfffffb44 │ │ strdeq r9, [lr], -r8 @ │ │ ldc2l 3, cr11, [sp, #480] @ 0x1e0 │ │ ldc2l 10, cr15, [ip, #436] @ 0x1b4 @ │ │ - ldc2l 0, cr14, [sl, #264] @ 0x108 │ │ + ldc2l 0, cr14, [sl, #444] @ 0x1bc │ │ strhteq r9, [lr], -r0 │ │ eoreq r9, lr, r8, lsr #17 │ │ eoreq r9, lr, r4, lsl #17 │ │ eoreq r9, lr, r8, lsl #17 │ │ eoreq r9, lr, r8, ror #16 │ │ eoreq r9, lr, r8, ror #16 │ │ eoreq r9, lr, r4, ror #16 │ │ ldc2l 7, cr13, [ip, #288] @ 0x120 │ │ ldc2l 6, cr5, [sp, #84] @ 0x54 │ │ ldc2l 6, cr3, [sp, #288] @ 0x120 │ │ - ldc2l 4, cr3, [fp, #772] @ 0x304 │ │ + ldc2l 4, cr3, [fp, #952] @ 0x3b8 │ │ ldc2l 6, cr15, [ip, #572] @ 0x23c │ │ ldc2l 3, cr13, [ip] │ │ ldc2l 1, cr5, [sp, #820] @ 0x334 │ │ ldc2l 13, cr10, [sp, #604] @ 0x25c │ │ ldc2l 15, cr9, [sl, #364] @ 0x16c │ │ - ldc2l 3, cr3, [fp, #356] @ 0x164 │ │ - ldc2l 7, cr1, [ip, #684] @ 0x2ac │ │ + ldc2l 3, cr3, [fp, #536] @ 0x218 │ │ + ldc2l 7, cr1, [ip, #864] @ 0x360 │ │ stc2l 6, cr9, [r6, #208]! @ 0xd0 │ │ stc2l 6, cr9, [r6, #224]! @ 0xe0 │ │ ldc2l 13, cr10, [sp, #864] @ 0x360 │ │ - ldc2l 2, cr3, [fp, #692] @ 0x2b4 │ │ + ldc2l 2, cr3, [fp, #872] @ 0x368 │ │ ldc2l 1, cr13, [sp, #120] @ 0x78 │ │ - ldc2l 2, cr3, [fp, #836] @ 0x344 │ │ - vcadd.f32 , , q14, #270 │ │ + ldc2l 2, cr3, [fp, #1016] @ 0x3f8 │ │ + ldc2l 9, cr13, [fp, #50] @ 0x32 @ │ │ eoreq r9, lr, r4, lsl #6 │ │ streq lr, [lr], #-3716 @ 0xfffff17c │ │ streq lr, [lr], #-3720 @ 0xfffff178 │ │ eoreq r9, lr, r0, asr #5 │ │ streq lr, [lr], #-3696 @ 0xfffff190 │ │ ldrdeq r9, [lr], -r0 @ │ │ mlaeq lr, r4, r2, r9 │ │ @@ -1352367,21 +1352367,21 @@ │ │ add r0, r3, r2 │ │ adds r1, r1, #1 │ │ vldr d16, [r0] │ │ vstmia r3!, {d16} │ │ bcc 2470454 │ │ str r9, [r4] │ │ b 247037c │ │ - ldc2l 2, cr15, [fp, #16] │ │ + ldc2l 2, cr15, [fp, #196] @ 0xc4 │ │ ldc2l 2, cr14, [sp, #432] @ 0x1b0 │ │ ldc2l 13, cr14, [ip, #484] @ 0x1e4 │ │ - ldc2l 10, cr2, [ip, #948] @ 0x3b4 @ │ │ - ldc2l 1, cr13, [fp, #124] @ 0x7c │ │ - ldc2l 3, cr5, [fp, #740] @ 0x2e4 │ │ - ldc2l 1, cr15, [fp, #688] @ 0x2b0 │ │ + ldc2l 11, cr2, [ip, #104] @ 0x68 @ │ │ + ldc2l 1, cr13, [fp, #304] @ 0x130 │ │ + ldc2l 3, cr5, [fp, #920] @ 0x398 │ │ + ldc2l 1, cr15, [fp, #868] @ 0x364 │ │ │ │ 0247048c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #908 @ 0x38c │ │ mov r8, r3 │ │ mov sl, r2 │ │ @@ -1352597,23 +1352597,23 @@ │ │ ldr r0, [pc, #52] @ 2470820 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 3, cr15, [sl, #212] @ 0xd4 │ │ + ldc2l 3, cr15, [sl, #392] @ 0x188 │ │ eoreq r8, lr, r8, asr #22 │ │ eoreq r8, lr, r4, asr #22 │ │ - ldc2l 3, cr5, [fp, #316] @ 0x13c │ │ - ldc2l 9, cr2, [fp, #338] @ 0x152 @ │ │ + ldc2l 3, cr5, [fp, #496] @ 0x1f0 │ │ + ldc2l 9, cr2, [fp, #428] @ 0x1ac @ │ │ strhteq r8, [lr], -r4 │ │ ldc2l 5, cr6, [sp, #392] @ 0x188 │ │ eoreq r8, lr, ip, lsl #17 │ │ - ldc2l 0, cr15, [sl, #20] │ │ + ldc2l 0, cr15, [sl, #200] @ 0xc8 │ │ │ │ 02470824 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r2 │ │ mov r5, r1 │ │ mov r6, r0 │ │ @@ -1352674,17 +1352674,17 @@ │ │ ldr r0, [pc, #36] @ 247093c │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldc2l 10, cr12, [ip, #944] @ 0x3b0 @ │ │ - ldc2l 6, cr6, [ip, #912] @ 0x390 │ │ - ldc2l 6, cr2, [fp, #36] @ 0x24 │ │ - ldc2l 11, cr4, [fp, #300] @ 0x12c @ │ │ + ldc2l 7, cr6, [ip, #68] @ 0x44 │ │ + ldc2l 6, cr2, [fp, #216] @ 0xd8 │ │ + ldc2l 11, cr4, [fp, #480] @ 0x1e0 @ │ │ streq lr, [lr], #-776 @ 0xfffffcf8 │ │ ldc2l 10, cr12, [ip, #160] @ 0xa0 @ │ │ │ │ 02470940 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r5, r1 │ │ @@ -1352723,17 +1352723,17 @@ │ │ ldr r0, [pc, #32] @ 24709f4 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, fp, pc} │ │ ldc2l 1, cr4, [sp, #468] @ 0x1d4 │ │ - ldc2l 6, cr6, [ip, #160] @ 0xa0 │ │ - ldc2l 5, cr2, [fp, #308] @ 0x134 │ │ - ldc2l 10, cr4, [fp, #572] @ 0x23c @ │ │ + ldc2l 6, cr6, [ip, #340] @ 0x154 │ │ + ldc2l 5, cr2, [fp, #488] @ 0x1e8 │ │ + ldc2l 10, cr4, [fp, #752] @ 0x2f0 @ │ │ ldc2l 1, cr4, [sp, #52] @ 0x34 │ │ │ │ 024709f8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d9} │ │ @@ -1352992,16 +1352992,16 @@ │ │ @ instruction: 0xfefa39ef │ │ svccc 0x00e62e42 │ │ streq lr, [lr], #-380 @ 0xfffffe84 │ │ streq lr, [lr], #-524 @ 0xfffffdf4 │ │ streq lr, [lr], #-340 @ 0xfffffeac │ │ streq lr, [lr], #-424 @ 0xfffffe58 │ │ ldc2l 7, cr10, [ip, #860] @ 0x35c │ │ - ldc2l 7, cr2, [ip, #264] @ 0x108 │ │ - ldc2l 3, cr2, [fp, #708] @ 0x2c4 │ │ + ldc2l 7, cr2, [ip, #444] @ 0x1bc │ │ + ldc2l 3, cr2, [fp, #888] @ 0x378 │ │ streq lr, [lr], #-236 @ 0xffffff14 │ │ ldc2l 13, cr3, [sp, #900] @ 0x384 │ │ streq sp, [lr], #-4004 @ 0xfffff05c │ │ │ │ 02470e28 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -1353208,21 +1353208,21 @@ │ │ str r1, [r2] │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 13, cr5, [sl, #620] @ 0x26c │ │ - ldc2l 6, cr14, [fp, #780] @ 0x30c │ │ + ldc2l 6, cr14, [fp, #960] @ 0x3c0 │ │ eoreq r8, lr, r8, lsl r1 │ │ ldc2l 13, cr5, [sl, #108] @ 0x6c │ │ - ldc2l 3, cr14, [fp, #956] @ 0x3bc │ │ + ldc2l 4, cr14, [fp, #112] @ 0x70 │ │ ldc2l 14, cr5, [sl, #796] @ 0x31c │ │ eoreq r8, lr, r8, lsr r0 │ │ - ldc2l 4, cr14, [fp, #124] @ 0x7c │ │ + ldc2l 4, cr14, [fp, #304] @ 0x130 │ │ │ │ 02471188 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ ldr r7, [fp, #8] │ │ mov r4, r1 │ │ mov r9, r0 │ │ @@ -1353336,16 +1353336,16 @@ │ │ ldr r0, [pc, #24] @ 2471350 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - ldc2l 13, cr5, [ip, #224] @ 0xe0 │ │ - ldc2l 12, cr5, [ip, #832] @ 0x340 │ │ + ldc2l 13, cr5, [ip, #404] @ 0x194 │ │ + ldc2l 12, cr5, [ip, #1012] @ 0x3f4 │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ │ │ 02471358 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d11} │ │ @@ -1354396,15 +1354396,15 @@ │ │ movw r3, #1547 @ 0x60b │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #3868] @ 24732ec │ │ ldr r0, [pc, r0] │ │ b 24722a8 │ │ - ldc2l 3, cr4, [fp, #528] @ 0x210 │ │ + ldc2l 3, cr4, [fp, #708] @ 0x2c4 │ │ streq r0, [pc], #-548 @ 24723e0 │ │ streq sp, [lr], #-2896 @ 0xfffff4b0 │ │ streq sp, [lr], #-2936 @ 0xfffff488 │ │ ldreq sl, [lr], #-3600 @ 0xfffff1f0 │ │ streq pc, [lr], #-1156 @ 0xfffffb7c │ │ streq sp, [lr], #-2676 @ 0xfffff58c │ │ streq sp, [lr], #-2652 @ 0xfffff5a4 │ │ @@ -1354459,19 +1354459,19 @@ │ │ cmp r1, r2 │ │ bcs 2472504 │ │ mov r4, r9 │ │ b 2472528 │ │ streq sp, [lr], #-2716 @ 0xfffff564 │ │ streq sp, [lr], #-2592 @ 0xfffff5e0 │ │ streq pc, [lr], #-1048 @ 0xfffffbe8 │ │ - ldc2l 11, cr5, [ip, #156] @ 0x9c @ │ │ - ldc2l 2, cr8, [fp, #468] @ 0x1d4 │ │ + ldc2l 11, cr5, [ip, #336] @ 0x150 @ │ │ + ldc2l 2, cr8, [fp, #648] @ 0x288 │ │ ldc2l 14, cr13, [ip, #132] @ 0x84 │ │ streq sp, [lr], #-2660 @ 0xfffff59c │ │ - ldc2l 4, cr2, [fp, #860] @ 0x35c │ │ + ldc2l 5, cr2, [fp, #16] │ │ streq sp, [lr], #-2604 @ 0xfffff5d4 │ │ streq sp, [lr], #-2592 @ 0xfffff5e0 │ │ streq sp, [lr], #-2524 @ 0xfffff624 │ │ streq sp, [lr], #-2512 @ 0xfffff630 │ │ streq sp, [lr], #-2448 @ 0xfffff670 │ │ streq sp, [lr], #-2440 @ 0xfffff678 │ │ streq sp, [lr], #-2384 @ 0xfffff6b0 │ │ @@ -1354557,16 +1354557,16 @@ │ │ ldreq sl, [lr], #-764 @ 0xfffffd04 │ │ ldreq r9, [lr], #-2944 @ 0xfffff480 │ │ ldreq sl, [lr], #-740 @ 0xfffffd1c │ │ ldreq r9, [lr], #-2916 @ 0xfffff49c │ │ streq r2, [pc], #-368 @ 2472654 │ │ streq r1, [pc], #-2820 @ 2472658 │ │ streq r1, [pc], #-2800 @ 247265c │ │ - ldc2l 15, cr11, [sl, #980] @ 0x3d4 │ │ - ldc2l 9, cr5, [ip, #78] @ 0x4e @ │ │ + ldc2l 0, cr12, [sl, #136] @ 0x88 │ │ + ldc2l 9, cr5, [ip, #168] @ 0xa8 @ │ │ streq sp, [lr], #-1360 @ 0xfffffab0 │ │ streq r1, [pc], #-2720 @ 247266c │ │ ldr r0, [pc, #3732] @ 2473504 │ │ mov r2, r7 │ │ movw r3, #1578 @ 0x62a │ │ add r0, pc, r0 │ │ bl 270da30 │ │ @@ -1354606,16 +1354606,16 @@ │ │ bl 270da30 │ │ ldr r2, [pc, #3608] @ 2473524 │ │ mov r1, r0 │ │ ldr r2, [pc, r2] │ │ b 2472048 │ │ mov r4, #3 │ │ b 24727ac │ │ - ldc2l 13, cr15, [fp, #716] @ 0x2cc │ │ - ldc2l 8, cr5, [ip, #892] @ 0x37c │ │ + ldc2l 13, cr15, [fp, #896] @ 0x380 │ │ + ldc2l 9, cr5, [ip, #24] @ │ │ streq r3, [pc], #-528 @ 247272c │ │ streq sp, [lr], #-2092 @ 0xfffff7d4 │ │ streq sp, [lr], #-2040 @ 0xfffff808 │ │ streq r1, [pc], #-2612 @ 2472738 │ │ streq r1, [pc], #-2616 @ 247273c │ │ streq r1, [pc], #-2580 @ 2472740 │ │ streq r2, [pc], #-728 @ 2472744 │ │ @@ -1354650,24 +1354650,24 @@ │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ cmp r1, #157 @ 0x9d │ │ bcs 24727f4 │ │ mov r6, r4 │ │ b 2472814 │ │ streq sp, [lr], #-1764 @ 0xfffff91c │ │ - ldc2l 1, cr0, [fp, #112] @ 0x70 │ │ - ldc2l 6, cr1, [fp, #948] @ 0x3b4 │ │ + ldc2l 1, cr0, [fp, #292] @ 0x124 │ │ + ldc2l 7, cr1, [fp, #104] @ 0x68 │ │ streq sp, [lr], #-1672 @ 0xfffff978 │ │ streq r3, [pc], #-1540 @ 24727e0 │ │ streq pc, [lr], #-1852 @ 0xfffff8c4 │ │ streq sp, [lr], #-1640 @ 0xfffff998 │ │ streq sp, [lr], #-1828 @ 0xfffff8dc │ │ streq sp, [lr], #-1612 @ 0xfffff9b4 │ │ - ldc2l 14, cr11, [sl, #336] @ 0x150 │ │ - ldc2l 6, cr1, [fp, #340] @ 0x154 │ │ + ldc2l 14, cr11, [sl, #516] @ 0x204 │ │ + ldc2l 6, cr1, [fp, #520] @ 0x208 │ │ ldr r0, [pc, #3392] @ 247353c │ │ mov r2, r9 │ │ movw r3, #1560 @ 0x618 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ ldr r6, [pc, #3376] @ 2473540 │ │ mov r1, r0 │ │ @@ -1354706,16 +1354706,16 @@ │ │ mov r2, r9 │ │ movw r3, #1567 @ 0x61f │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2472740 │ │ streq sp, [lr], #-1652 @ 0xfffff98c │ │ - ldc2l 14, cr11, [sl, #168] @ 0xa8 │ │ - ldc2l 6, cr1, [fp, #52] @ 0x34 │ │ + ldc2l 14, cr11, [sl, #348] @ 0x15c │ │ + ldc2l 6, cr1, [fp, #232] @ 0xe8 │ │ eoreq r7, lr, r0, lsr r7 │ │ strteq r6, [r6], #-1804 @ 0xfffff8f4 │ │ streq r3, [pc], #-1320 @ 24728c4 │ │ streq sp, [lr], #-1440 @ 0xfffffa60 │ │ streq sp, [lr], #-1420 @ 0xfffffa74 │ │ ldr r0, [pc, #3952] @ 2473840 │ │ mov r2, r7 │ │ @@ -1354760,27 +1354760,27 @@ │ │ cmp r3, #157 @ 0x9d │ │ sub r4, r1, #200 @ 0xc8 │ │ str r4, [sp, #56] @ 0x38 │ │ bcs 24729c0 │ │ ldr r8, [pc, #4028] @ 247393c │ │ add r8, pc, r8 │ │ b 2472a1c │ │ - ldc2l 15, cr3, [fp, #836] @ 0x344 │ │ - ldc2l 5, cr1, [fp, #388] @ 0x184 │ │ + ldc2l 15, cr3, [fp, #1016] @ 0x3f8 │ │ + ldc2l 5, cr1, [fp, #568] @ 0x238 │ │ streq sp, [lr], #-1328 @ 0xfffffad0 │ │ streq sp, [lr], #-1408 @ 0xfffffa80 │ │ ldc2l 0, cr9, [sp, #716] @ 0x2cc │ │ streq sp, [lr], #-1304 @ 0xfffffae8 │ │ streq pc, [lr], #-3124 @ 0xfffff3cc │ │ streq pc, [lr], #-3040 @ 0xfffff420 │ │ streq lr, [lr], #-3828 @ 0xfffff10c │ │ ldreq fp, [lr], #-1544 @ 0xfffff9f8 │ │ streq sp, [lr], #-1356 @ 0xfffffab4 │ │ - ldc2l 13, cr7, [fp, #180] @ 0xb4 │ │ - ldc2l 5, cr5, [ip, #844] @ 0x34c │ │ + ldc2l 13, cr7, [fp, #360] @ 0x168 │ │ + ldc2l 6, cr5, [ip] │ │ ldc2l 2, cr7, [sp, #636] @ 0x27c │ │ streq sp, [lr], #-1300 @ 0xfffffaec │ │ ldr r0, [pc, #3960] @ 2473940 │ │ mov r1, r4 │ │ ldr r2, [pc, #3956] @ 2473944 │ │ movw r3, #1589 @ 0x635 │ │ add r0, pc, r0 │ │ @@ -1354927,52 +1354927,52 @@ │ │ vstr d16, [r2] │ │ sub r4, r1, #200 @ 0xc8 │ │ str r4, [sp, #56] @ 0x38 │ │ bhi 2472cc0 │ │ str r3, [sp, #60] @ 0x3c │ │ b 2472d18 │ │ ldc2l 6, cr9, [ip, #872] @ 0x368 │ │ - ldc2l 3, cr5, [ip, #892] @ 0x37c │ │ + ldc2l 4, cr5, [ip, #48] @ 0x30 │ │ streq r1, [pc], #-1392 @ 2472c2c │ │ streq r0, [pc], #-1636 @ 2472c30 │ │ streq r0, [pc], #-1628 @ 2472c34 │ │ - ldc2l 8, cr15, [fp, #104] @ 0x68 │ │ - ldc2l 3, cr5, [ip, #252] @ 0xfc │ │ + vcadd.f32 , , , #270 │ │ + ldc2l 3, cr5, [ip, #432] @ 0x1b0 │ │ streq r1, [pc], #-1232 @ 2472c40 │ │ strteq r5, [r6], #-3560 @ 0xfffff218 │ │ ldreq r8, [lr], #-1544 @ 0xfffff9f8 │ │ - ldc2l 2, cr3, [ip, #172] @ 0xac │ │ - ldc2l 2, cr5, [ip, #620] @ 0x26c │ │ + ldc2l 2, cr3, [ip, #352] @ 0x160 │ │ + ldc2l 2, cr5, [ip, #800] @ 0x320 │ │ streq r1, [pc], #-1068 @ 2472c54 │ │ streq sp, [lr], #-456 @ 0xfffffe38 │ │ ldc2l 5, cr9, [ip, #104] @ 0x68 │ │ - ldc2l 2, cr5, [ip, #124] @ 0x7c │ │ + ldc2l 2, cr5, [ip, #304] @ 0x130 │ │ streq r1, [pc], #-944 @ 2472c64 │ │ ldc2l 4, cr9, [ip, #824] @ 0x338 │ │ - ldc2l 1, cr5, [ip, #844] @ 0x34c │ │ + ldc2l 2, cr5, [ip] │ │ streq r1, [pc], #-868 @ 2472c70 │ │ streq sp, [lr], #-292 @ 0xfffffedc │ │ strteq r6, [r6], #-400 @ 0xfffffe70 │ │ - ldc2l 6, cr15, [fp, #312] @ 0x138 │ │ - ldc2l 1, cr5, [ip, #460] @ 0x1cc │ │ + ldc2l 6, cr15, [fp, #492] @ 0x1ec │ │ + ldc2l 1, cr5, [ip, #640] @ 0x280 │ │ streq r1, [pc], #-772 @ 2472c84 │ │ - ldc2l 6, cr15, [fp, #8] │ │ - ldc2l 1, cr5, [ip, #156] @ 0x9c │ │ + ldc2l 6, cr15, [fp, #188] @ 0xbc │ │ + ldc2l 1, cr5, [ip, #336] @ 0x150 │ │ streq r1, [pc], #-696 @ 2472c90 │ │ streq sp, [lr], #-120 @ 0xffffff88 │ │ strteq r3, [sl], #-2224 @ 0xfffff750 │ │ - ldc2l 0, cr3, [ip, #332] @ 0x14c │ │ - ldc2l 0, cr5, [ip, #780] @ 0x30c │ │ + ldc2l 0, cr3, [ip, #512] @ 0x200 │ │ + ldc2l 0, cr5, [ip, #960] @ 0x3c0 │ │ streq r1, [pc], #-596 @ 2472ca4 │ │ - ldc2l 0, cr3, [ip, #28] │ │ - ldc2l 0, cr5, [ip, #476] @ 0x1dc │ │ + ldc2l 0, cr3, [ip, #208] @ 0xd0 │ │ + ldc2l 0, cr5, [ip, #656] @ 0x290 │ │ streq r1, [pc], #-520 @ 2472cb0 │ │ streq r1, [pc], #-2108 @ 2472cb4 │ │ ldc2l 11, cr5, [sl, #548] @ 0x224 @ │ │ - ldc2l 0, cr5, [ip, #140] @ 0x8c │ │ + ldc2l 0, cr5, [ip, #320] @ 0x140 │ │ ldreq r9, [lr], #-1172 @ 0xfffffb6c │ │ streq ip, [lr], #-3936 @ 0xfffff0a0 │ │ ldr r0, [pc, #3960] @ 2473c40 │ │ mov r1, r4 │ │ ldr r2, [pc, #3956] @ 2473c44 │ │ movw r3, #1593 @ 0x639 │ │ add r0, pc, r0 │ │ @@ -1355184,20 +1355184,20 @@ │ │ add r1, pc, r1 │ │ str r0, [sp] │ │ mov r0, r4 │ │ mov r3, r1 │ │ bl 270f7b0 │ │ b 2471470 │ │ streq ip, [lr], #-3904 @ 0xfffff0c0 │ │ - ldc2l 15, cr4, [ip, #860] @ 0x35c │ │ + ldc2l 0, cr5, [ip, #16] │ │ ldreq fp, [lr], #-40 @ 0xffffffd8 │ │ streq ip, [lr], #-3852 @ 0xfffff0f4 │ │ ldreq r9, [lr], #-2964 @ 0xfffff46c │ │ streq r1, [pc], #-304 @ 247303c │ │ - vcadd.f32 d31, d26, d1, #270 │ │ + vcadd.f32 d31, d26, d30, #270 │ │ ldr r0, [pc, #3416] @ 2473d9c │ │ movw r3, #1507 @ 0x5e3 │ │ ldr r2, [pc, #3412] @ 2473da0 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #3400] @ 2473da4 │ │ @@ -1355293,15 +1355293,15 @@ │ │ b 2471db8 │ │ ldc2l 3, cr3, [sl, #776] @ 0x308 │ │ streq ip, [lr], #-3484 @ 0xfffff264 │ │ streq r2, [pc], #-3144 @ 24731d0 │ │ ldreq r8, [lr], #-4064 @ 0xfffff020 │ │ streq lr, [lr], #-1712 @ 0xfffff950 │ │ streq r0, [pc], #-3940 @ 24731dc │ │ - ldc2l 6, cr15, [sl, #724] @ 0x2d4 │ │ + ldc2l 6, cr15, [sl, #904] @ 0x388 │ │ ldreq r9, [lr], #-1172 @ 0xfffffb6c │ │ streq ip, [lr], #-3300 @ 0xfffff31c │ │ streq r0, [pc], #-3856 @ 24731ec │ │ streq r2, [pc], #-2968 @ 24731f0 │ │ ldr r0, [pc, #3868] @ 2474110 │ │ ldr r2, [pc, #3868] @ 2474114 │ │ ldr r3, [pc, #3868] @ 2474118 │ │ @@ -1355354,26 +1355354,26 @@ │ │ mov r3, #35 @ 0x23 │ │ add r1, pc, r1 │ │ bl 270da60 │ │ b 24738f4 │ │ streq lr, [lr], #-1576 @ 0xfffff9d8 │ │ streq ip, [lr], #-3228 @ 0xfffff364 │ │ streq ip, [lr], #-3212 @ 0xfffff374 │ │ - ldc2l 5, cr15, [sl, #980] @ 0x3d4 │ │ + ldc2l 6, cr15, [sl, #136] @ 0x88 │ │ streq ip, [lr], #-3124 @ 0xfffff3cc │ │ ldreq r9, [lr], #-968 @ 0xfffffc38 │ │ streq ip, [lr], #-3096 @ 0xfffff3e8 │ │ streq ip, [lr], #-3084 @ 0xfffff3f4 │ │ streq ip, [lr], #-3048 @ 0xfffff418 │ │ streq r0, [pc], #-3616 @ 24732ec │ │ ldc2l 1, cr3, [sl, #936] @ 0x3a8 │ │ streq r0, [pc], #-3556 @ 24732f4 │ │ streq lr, [lr], #-1232 @ 0xfffffb30 │ │ streq r0, [pc], #-3460 @ 24732fc │ │ - ldc2l 4, cr15, [sl, #852] @ 0x354 │ │ + ldc2l 5, cr15, [sl, #8] │ │ streq r0, [pc], #-3416 @ 2473304 │ │ ldreq r8, [lr], #-3476 @ 0xfffff26c │ │ ldreq r9, [lr], #-668 @ 0xfffffd64 │ │ streq ip, [lr], #-2796 @ 0xfffff514 │ │ streq ip, [lr], #-2784 @ 0xfffff520 │ │ ldr r2, [pc, #4076] @ 2474304 │ │ mov r4, #32 │ │ @@ -1355487,38 +1355487,38 @@ │ │ add r0, pc, r0 │ │ mov r1, #25 │ │ b 2473900 │ │ ldc2l 0, cr3, [sl, #584] @ 0x248 │ │ streq r0, [pc], #-3212 @ 24734dc │ │ streq ip, [lr], #-2656 @ 0xfffff5a0 │ │ streq r2, [pc], #-2316 @ 24734e4 │ │ - ldc2l 3, cr15, [sl, #724] @ 0x2d4 │ │ + ldc2l 3, cr15, [sl, #904] @ 0x388 │ │ ldreq r9, [lr], #-404 @ 0xfffffe6c │ │ streq ip, [lr], #-2532 @ 0xfffff61c │ │ streq r0, [pc], #-3072 @ 24734f4 │ │ ldreq sl, [lr], #-2724 @ 0xfffff55c │ │ streq lr, [lr], #-788 @ 0xfffffcec │ │ ldreq sl, [lr], #-2656 @ 0xfffff5a0 │ │ streq ip, [lr], #-2404 @ 0xfffff69c │ │ streq lr, [lr], #-2412 @ 0xfffff694 │ │ - ldc2l 0, cr11, [sl, #628] @ 0x274 │ │ + ldc2l 0, cr11, [sl, #808] @ 0x328 │ │ streq lr, [lr], #-2308 @ 0xfffff6fc │ │ streq ip, [lr], #-2260 @ 0xfffff72c │ │ ldreq r8, [lr], #-2904 @ 0xfffff4a8 │ │ streq lr, [lr], #-648 @ 0xfffffd78 │ │ streq ip, [lr], #-2204 @ 0xfffff764 │ │ ldreq r9, [lr], #-2920 @ 0xfffff498 │ │ ldc2l 12, cr10, [ip, #300] @ 0x12c │ │ streq ip, [lr], #-2140 @ 0xfffff7a4 │ │ streq r2, [pc], #-1780 @ 2473530 │ │ streq ip, [lr], #-2080 @ 0xfffff7e0 │ │ streq ip, [lr], #-2020 @ 0xfffff81c │ │ streq ip, [lr], #-2004 @ 0xfffff82c │ │ streq r0, [pc], #-2560 @ 2473540 │ │ - ldc2l 1, cr15, [sl, #116] @ 0x74 │ │ + ldc2l 1, cr15, [sl, #296] @ 0x128 │ │ streq ip, [lr], #-1884 @ 0xfffff8a4 │ │ ldreq r8, [lr], #-3828 @ 0xfffff10c │ │ streq ip, [lr], #-1860 @ 0xfffff8bc │ │ ldr r0, [pc, #3568] @ 2474344 │ │ ldr r1, [pc, #3568] @ 2474348 │ │ ldr r3, [pc, #3568] @ 247434c │ │ add r0, pc, r0 │ │ @@ -1355768,38 +1355768,38 @@ │ │ streq ip, [lr], #-1592 @ 0xfffff9c8 │ │ mov sl, r5 │ │ mov r4, #2 │ │ b 24739c0 │ │ streq r0, [pc], #-2132 @ 2473940 │ │ streq pc, [lr], #-2420 @ 0xfffff68c │ │ ldc2l 2, cr4, [sp, #256] @ 0x100 │ │ - ldc2l 6, cr4, [ip, #236] @ 0xec │ │ + ldc2l 6, cr4, [ip, #416] @ 0x1a0 │ │ streq r0, [pc], #-1996 @ 2473950 │ │ streq pc, [lr], #-2304 @ 0xfffff700 │ │ - ldc2l 12, cr10, [fp, #432] @ 0x1b0 │ │ - ldc2l 5, cr4, [ip, #1020] @ 0x3fc │ │ + ldc2l 12, cr10, [fp, #612] @ 0x264 │ │ + ldc2l 6, cr4, [ip, #176] @ 0xb0 │ │ ldreq sl, [lr], #-1648 @ 0xfffff990 │ │ strteq r5, [r6], #-248 @ 0xffffff08 │ │ streq lr, [lr], #-1364 @ 0xfffffaac │ │ streq r0, [pc], #-1888 @ 247396c │ │ ldc2l 2, cr0, [sp, #936] @ 0x3a8 │ │ - ldc2l 5, cr4, [ip, #316] @ 0x13c │ │ + ldc2l 5, cr4, [ip, #496] @ 0x1f0 │ │ streq r0, [pc], #-1760 @ 2473978 │ │ - ldc2l 7, cr0, [ip, #824] @ 0x338 │ │ - ldc2l 5, cr4, [ip, #92] @ 0x5c │ │ + ldc2l 7, cr0, [ip, #1004] @ 0x3ec │ │ + ldc2l 5, cr4, [ip, #272] @ 0x110 │ │ strteq r7, [r2], #-2760 @ 0xfffff538 │ │ strteq r5, [r6], #-644 @ 0xfffffd7c │ │ streq sp, [lr], #-3620 @ 0xfffff1dc │ │ strteq r4, [r6], #-4068 @ 0xfffff01c │ │ streq r0, [pc], #-1644 @ 2473994 │ │ ldc2l 0, cr5, [sl, #16] │ │ - ldc2l 4, cr4, [ip, #604] @ 0x25c │ │ + ldc2l 4, cr4, [ip, #784] @ 0x310 │ │ streq r0, [pc], #-1576 @ 24739a0 │ │ - ldc2l 10, cr10, [fp, #848] @ 0x350 @ │ │ - ldc2l 4, cr4, [ip, #396] @ 0x18c │ │ + ldc2l 11, cr10, [fp, #4] @ │ │ + ldc2l 4, cr4, [ip, #576] @ 0x240 │ │ strteq r5, [r6], #-1116 @ 0xfffffba4 │ │ strteq r2, [sl], #-2464 @ 0xfffff660 │ │ streq lr, [lr], #-952 @ 0xfffffc48 │ │ streq ip, [lr], #-948 @ 0xfffffc4c │ │ streq r0, [pc], #-1468 @ 24739bc │ │ add r4, r0, #1 │ │ mov sl, r5 │ │ @@ -1355960,17 +1355960,17 @@ │ │ str r1, [sp, #60] @ 0x3c │ │ add r1, sp, #60 @ 0x3c │ │ bl 270db00 │ │ ldr r0, [pc, #2152] @ 24744a4 │ │ add r0, pc, r0 │ │ b 24734c8 │ │ ldc2l 15, cr3, [sp, #256] @ 0x100 │ │ - ldc2l 3, cr4, [ip, #236] @ 0xec │ │ + ldc2l 3, cr4, [ip, #416] @ 0x1a0 │ │ streq r0, [pc], #-1228 @ 2473c50 │ │ - ldc2l 9, cr10, [fp, #224] @ 0xe0 @ │ │ + ldc2l 9, cr10, [fp, #314] @ 0x13a @ │ │ ldr r0, [pc, #2128] @ 24744a8 │ │ ldr r1, [pc, #2128] @ 24744ac │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ bl 270f7c0 │ │ ldr r0, [pc, #2116] @ 24744b0 │ │ ldr r0, [pc, r0] │ │ @@ -1356008,34 +1356008,34 @@ │ │ ldr r2, [pc, #2028] @ 24744dc │ │ add r2, pc, r2 │ │ add r2, r2, r1, lsl #3 │ │ vstr d8, [r2] │ │ ldr r4, [pc, #2016] @ 24744e0 │ │ ldr r4, [pc, r4] │ │ b 2473e04 │ │ - ldc2l 3, cr4, [ip, #12] │ │ + ldc2l 3, cr4, [ip, #192] @ 0xc0 │ │ ldreq r9, [lr], #-1316 @ 0xfffffadc │ │ ldreq sl, [lr], #-880 @ 0xfffffc90 │ │ strteq r4, [r6], #-3576 @ 0xfffff208 │ │ strteq r5, [r6], #-716 @ 0xfffffd34 │ │ streq r0, [pc], #-1116 @ 2473d20 │ │ ldc2l 0, cr0, [sp, #136] @ 0x88 │ │ - ldc2l 2, cr4, [ip, #540] @ 0x21c │ │ + ldc2l 2, cr4, [ip, #720] @ 0x2d0 │ │ streq r0, [pc], #-1048 @ 2473d2c │ │ - ldc2l 5, cr0, [ip, #40] @ 0x28 │ │ - ldc2l 2, cr4, [ip, #332] @ 0x14c │ │ + ldc2l 5, cr0, [ip, #220] @ 0xdc │ │ + ldc2l 2, cr4, [ip, #512] @ 0x200 │ │ ldreq r8, [lr], #-3628 @ 0xfffff1d4 │ │ strteq r4, [r6], #-4032 @ 0xfffff040 │ │ strteq r2, [sl], #-2548 @ 0xfffff60c │ │ streq r0, [pc], #-948 @ 2473d44 │ │ ldc2l 13, cr4, [sl, #304] @ 0x130 │ │ - ldc2l 1, cr4, [ip, #892] @ 0x37c │ │ + ldc2l 2, cr4, [ip, #48] @ 0x30 │ │ streq r0, [pc], #-880 @ 2473d50 │ │ - ldc2l 8, cr10, [fp, #112] @ 0x70 │ │ - ldc2l 1, cr4, [ip, #684] @ 0x2ac │ │ + vcadd.f32 q13, , , #270 │ │ + ldc2l 1, cr4, [ip, #864] @ 0x360 │ │ ldreq r9, [lr], #-972 @ 0xfffffc34 │ │ streq r0, [pc], #-2428 @ 2473d60 │ │ strteq r4, [r6], #-3164 @ 0xfffff3a4 │ │ streq ip, [lr], #-192 @ 0xffffff40 │ │ strteq r5, [r6], #-284 @ 0xfffffee4 │ │ strteq r2, [sl], #-1540 @ 0xfffff9fc │ │ streq r0, [pc], #-2188 @ 2473d74 │ │ @@ -1356047,21 +1356047,21 @@ │ │ ldreq sl, [lr], #-12 │ │ streq r0, [pc], #-2080 @ 2473d90 │ │ streq r0, [pc], #-2084 @ 2473d94 │ │ streq fp, [lr], #-3800 @ 0xfffff128 │ │ eoreq r6, lr, r4, lsr r0 │ │ eoreq r6, lr, r4, lsr r0 │ │ ldc2l 2, cr8, [ip, #760] @ 0x2f8 │ │ - ldc2l 15, cr3, [ip, #780] @ 0x30c │ │ + ldc2l 15, cr3, [ip, #960] @ 0x3c0 │ │ streq r0, [pc], #-340 @ 2473dac │ │ ldc2l 2, cr8, [ip, #504] @ 0x1f8 │ │ - ldc2l 15, cr3, [ip, #524] @ 0x20c │ │ + ldc2l 15, cr3, [ip, #704] @ 0x2c0 │ │ streq r0, [pc], #-276 @ 2473db8 │ │ - ldc2l 4, cr14, [fp, #72] @ 0x48 │ │ - ldc2l 15, cr3, [ip, #220] @ 0xdc │ │ + ldc2l 4, cr14, [fp, #252] @ 0xfc │ │ + ldc2l 15, cr3, [ip, #400] @ 0x190 │ │ streq r0, [pc], #-200 @ 2473dc4 │ │ ldr r0, [pc, #1820] @ 24744e4 │ │ movw r3, #1473 @ 0x5c1 │ │ ldr r2, [pc, #1816] @ 24744e8 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1356258,34 +1356258,34 @@ │ │ add r2, pc, r2 │ │ add r0, pc, r0 │ │ add r2, r2, r3, lsl #3 │ │ add r1, pc, r1 │ │ bl 270e100 │ │ ldr r6, [sp, #16] │ │ b 2471704 │ │ - ldc2l 3, cr14, [fp, #840] @ 0x348 │ │ - ldc2l 14, cr3, [ip, #988] @ 0x3dc │ │ + ldc2l 3, cr14, [fp, #1020] @ 0x3fc │ │ + ldc2l 15, cr3, [ip, #144] @ 0x90 │ │ streq r0, [pc], #-136 @ 24740fc │ │ - ldc2l 14, cr1, [ip, #252] @ 0xfc │ │ - ldc2l 14, cr3, [ip, #700] @ 0x2bc │ │ + ldc2l 14, cr1, [ip, #432] @ 0x1b0 │ │ + ldc2l 14, cr3, [ip, #880] @ 0x370 │ │ streq r0, [pc], #-64 @ 2474108 │ │ - ldc2l 13, cr1, [ip, #1020] @ 0x3fc │ │ - ldc2l 14, cr3, [ip, #444] @ 0x1bc │ │ + ldc2l 14, cr1, [ip, #176] @ 0xb0 │ │ + ldc2l 14, cr3, [ip, #624] @ 0x270 │ │ streq r0, [pc], #-0 @ 2474114 │ │ eoreq r5, lr, ip, lsr lr │ │ streq r1, [pc], #-1864 @ 247411c │ │ ldreq r9, [lr], #-1668 @ 0xfffff97c │ │ streq fp, [lr], #-3272 @ 0xfffff338 │ │ ldreq r9, [lr], #-3660 @ 0xfffff1b4 │ │ ldreq r9, [lr], #-1644 @ 0xfffff994 │ │ - ldc2l 5, cr0, [fp, #856] @ 0x358 │ │ + ldc2l 6, cr0, [fp, #12] │ │ streq fp, [lr], #-3184 @ 0xfffff390 │ │ ldreq r9, [lr], #-1604 @ 0xfffff9bc │ │ - ldc2l 12, cr15, [sl, #532] @ 0x214 │ │ - ldc2l 5, cr4, [fp, #604] @ 0x25c │ │ + ldc2l 12, cr15, [sl, #712] @ 0x2c8 │ │ + ldc2l 5, cr4, [fp, #784] @ 0x310 │ │ ldreq r9, [lr], #-1516 @ 0xfffffa14 │ │ ldreq r9, [lr], #-3516 @ 0xfffff244 │ │ ldr r0, [pc, #948] @ 2474500 │ │ movw r3, #1474 @ 0x5c2 │ │ ldr r2, [pc, #944] @ 2474504 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1356385,34 +1356385,34 @@ │ │ ldr r2, [pc, #712] @ 247459c │ │ movw r3, #1481 @ 0x5c9 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r3, r0 │ │ b 2473e84 │ │ - ldc2l 6, cr15, [sl, #628] @ 0x274 │ │ + ldc2l 6, cr15, [sl, #808] @ 0x328 │ │ ldrdeq r5, [lr], -r0 @ │ │ ldreq r9, [lr], #-56 @ 0xffffffc8 │ │ vcadd.f32 , q6, , #270 │ │ ldreq r9, [lr], #-1964 @ 0xfffff854 │ │ ldc2l 2, cr3, [sp, #844] @ 0x34c │ │ ldc2l 14, cr10, [sp, #252] @ 0xfc │ │ streq lr, [lr], #-832 @ 0xfffffcc0 │ │ streq fp, [lr], #-3096 @ 0xfffff3e8 │ │ eoreq r5, lr, ip, lsl #26 │ │ strteq r4, [r6], #-3300 @ 0xfffff31c │ │ streq lr, [lr], #-792 @ 0xfffffce8 │ │ streq fp, [lr], #-2920 @ 0xfffff498 │ │ - ldc2l 1, cr12, [fp, #824] @ 0x338 │ │ - ldc2l 11, cr15, [sl, #468] @ 0x1d4 @ │ │ + ldc2l 1, cr12, [fp, #1004] @ 0x3ec │ │ + ldc2l 11, cr15, [sl, #648] @ 0x288 @ │ │ streq fp, [lr], #-3092 @ 0xfffff3ec │ │ - ldc2l 12, cr3, [ip, #380] @ 0x17c │ │ - ldc2l 11, cr15, [sl, #148] @ 0x94 @ │ │ + ldc2l 12, cr3, [ip, #560] @ 0x230 │ │ + ldc2l 11, cr15, [sl, #328] @ 0x148 @ │ │ streq fp, [lr], #-2784 @ 0xfffff520 │ │ - ldc2l 11, cr15, [sl, #4] @ │ │ + ldc2l 11, cr15, [sl, #184] @ 0xb8 @ │ │ eoreq r5, lr, r4, lsr #24 │ │ strteq r4, [r6], #-3068 @ 0xfffff404 │ │ streq fp, [lr], #-2704 @ 0xfffff570 │ │ streq fp, [lr], #-2536 @ 0xfffff618 │ │ ldrdeq r5, [lr], -ip @ │ │ strteq r4, [r6], #-2740 @ 0xfffff54c │ │ streq fp, [lr], #-2376 @ 0xfffff6b8 │ │ @@ -1356436,75 +1356436,75 @@ │ │ ldreq r8, [lr], #-1304 @ 0xfffffae8 │ │ streq fp, [lr], #-2028 @ 0xfffff814 │ │ ldreq r9, [lr], #-2332 @ 0xfffff6e4 │ │ ldc2l 0, cr11, [sp, #352] @ 0x160 │ │ streq lr, [lr], #-3040 @ 0xfffff420 │ │ streq fp, [lr], #-2172 @ 0xfffff784 │ │ streq fp, [lr], #-2036 @ 0xfffff80c │ │ - ldc2l 2, cr0, [fp, #664] @ 0x298 │ │ + ldc2l 2, cr0, [fp, #844] @ 0x34c │ │ streq fp, [lr], #-2112 @ 0xfffff7c0 │ │ streq fp, [lr], #-2804 @ 0xfffff50c │ │ streq fp, [lr], #-2668 @ 0xfffff594 │ │ strteq r4, [r6], #-3008 @ 0xfffff440 │ │ streq sp, [lr], #-2848 @ 0xfffff4e0 │ │ streq fp, [lr], #-2644 @ 0xfffff5ac │ │ - ldc2l 4, cr2, [fp, #868] @ 0x364 │ │ - ldc2l 10, cr15, [sl, #420] @ 0x1a4 @ │ │ + ldc2l 5, cr2, [fp, #24] │ │ + ldc2l 10, cr15, [sl, #600] @ 0x258 @ │ │ streq fp, [lr], #-2616 @ 0xfffff5c8 │ │ streq fp, [lr], #-2696 @ 0xfffff578 │ │ - ldc2l 11, cr3, [ip, #424] @ 0x1a8 @ │ │ + ldc2l 11, cr3, [ip, #604] @ 0x25c @ │ │ streq fp, [lr], #-2084 @ 0xfffff7dc │ │ streq fp, [lr], #-1972 @ 0xfffff84c │ │ eoreq r5, lr, r4, lsr #17 │ │ strteq r4, [r6], #-2176 @ 0xfffff780 │ │ streq sp, [lr], #-340 @ 0xfffffeac │ │ strteq r4, [r6], #-876 @ 0xfffffc94 │ │ - ldc2l 13, cr11, [fp, #544] @ 0x220 │ │ - ldc2l 7, cr15, [sl, #116] @ 0x74 │ │ + ldc2l 13, cr11, [fp, #724] @ 0x2d4 │ │ + ldc2l 7, cr15, [sl, #296] @ 0x128 │ │ streq fp, [lr], #-1984 @ 0xfffff840 │ │ eoreq r5, lr, ip, lsr r8 │ │ strteq r4, [r6], #-780 @ 0xfffffcf4 │ │ - ldc2l 0, cr8, [sl, #440] @ 0x1b8 │ │ + ldc2l 0, cr8, [sl, #620] @ 0x26c │ │ streq fp, [lr], #-1500 @ 0xfffffa24 │ │ streq fp, [lr], #-1280 @ 0xfffffb00 │ │ eoreq r5, lr, r4, ror #12 │ │ ldreq r8, [lr], #-536 @ 0xfffffde8 │ │ streq fp, [lr], #-1504 @ 0xfffffa20 │ │ ldreq r8, [lr], #-500 @ 0xfffffe0c │ │ ldreq r9, [lr], #-1532 @ 0xfffffa04 │ │ streq fp, [lr], #-1196 @ 0xfffffb54 │ │ - ldc2l 11, cr9, [fp, #796] @ 0x31c @ │ │ + ldc2l 11, cr9, [fp, #976] @ 0x3d0 @ │ │ streq fp, [lr], #-1136 @ 0xfffffb90 │ │ ldrdeq r5, [lr], -r8 @ │ │ streq lr, [lr], #-2168 @ 0xfffff788 │ │ streq sp, [lr], #-3060 @ 0xfffff40c │ │ streq fp, [lr], #-1080 @ 0xfffffbc8 │ │ ldc2l 0, cr1, [sp, #288] @ 0x120 │ │ streq fp, [lr], #-1024 @ 0xfffffc00 │ │ eoreq r5, lr, r8, ror #10 │ │ streq lr, [lr], #-2060 @ 0xfffff7f4 │ │ streq lr, [lr], #-452 @ 0xfffffe3c │ │ streq fp, [lr], #-968 @ 0xfffffc38 │ │ - ldc2l 13, cr7, [sl, #616] @ 0x268 │ │ + ldc2l 13, cr7, [sl, #796] @ 0x31c │ │ streq fp, [lr], #-912 @ 0xfffffc70 │ │ strdeq r5, [lr], -r8 @ │ │ streq r1, [pc], #-752 @ 2474478 │ │ streq pc, [lr], #-1652 @ 0xfffff98c │ │ streq lr, [lr], #-1912 @ 0xfffff888 │ │ streq lr, [lr], #-1908 @ 0xfffff88c │ │ streq r1, [pc], #-696 @ 2474488 │ │ ldreq r7, [lr], #-2300 @ 0xfffff704 │ │ - ldc2l 10, cr9, [fp, #348] @ 0x15c @ │ │ + ldc2l 10, cr9, [fp, #528] @ 0x210 @ │ │ ldc2l 5, cr11, [ip, #116] @ 0x74 │ │ - ldc2l 3, cr15, [sl, #180] @ 0xb4 │ │ + ldc2l 3, cr15, [sl, #360] @ 0x168 │ │ ldreq r7, [lr], #-2216 @ 0xfffff758 │ │ streq lr, [lr], #-1772 @ 0xfffff914 │ │ streq lr, [lr], #-1768 @ 0xfffff918 │ │ streq r1, [pc], #-552 @ 24744a8 │ │ - ldc2l 3, cr1, [ip, #292] @ 0x124 │ │ + ldc2l 3, cr1, [ip, #472] @ 0x1d8 │ │ ldreq r7, [lr], #-1456 @ 0xfffffa50 │ │ streq fp, [lr], #-848 @ 0xfffffcb0 │ │ streq fp, [lr], #-836 @ 0xfffffcbc │ │ strhteq r5, [lr], -r0 │ │ ldreq r7, [lr], #-3324 @ 0xfffff304 │ │ ldreq r7, [lr], #-1408 @ 0xfffffa80 │ │ ldreq r7, [lr], #-3300 @ 0xfffff31c │ │ @@ -1356512,97 +1356512,97 @@ │ │ streq pc, [lr], #-2924 @ 0xfffff494 │ │ strteq r1, [sl], #-2860 @ 0xfffff4d4 │ │ streq pc, [lr], #-1276 @ 0xfffffb04 │ │ streq r1, [pc], #-364 @ 24744dc │ │ streq pc, [lr], #-1240 @ 0xfffffb28 │ │ streq r0, [pc], #-3172 @ 24744e4 │ │ streq ip, [lr], #-3020 @ 0xfffff434 │ │ - ldc2l 7, cr13, [fp, #76] @ 0x4c │ │ - ldc2l 2, cr3, [ip, #252] @ 0xfc │ │ + ldc2l 7, cr13, [fp, #256] @ 0x100 │ │ + ldc2l 2, cr3, [ip, #432] @ 0x1b0 │ │ streq r0, [pc], #-2932 @ 24744f4 │ │ streq pc, [lr], #-964 @ 0xfffffc3c │ │ streq ip, [lr], #-2764 @ 0xfffff534 │ │ streq sl, [lr], #-3648 @ 0xfffff1c0 │ │ ldreq r7, [lr], #-1664 @ 0xfffff980 │ │ - ldc2l 5, cr9, [sl, #548] @ 0x224 │ │ - ldc2l 14, cr2, [ip, #748] @ 0x2ec │ │ + ldc2l 5, cr9, [sl, #728] @ 0x2d8 │ │ + ldc2l 14, cr2, [ip, #928] @ 0x3a0 │ │ streq sl, [lr], #-2792 @ 0xfffff518 │ │ streq pc, [lr], #-68 @ 0xffffffbc │ │ ldreq r7, [lr], #-792 @ 0xfffffce8 │ │ ldreq r7, [lr], #-1656 @ 0xfffff988 │ │ ldreq r9, [lr], #-476 @ 0xfffffe24 │ │ ldc2l 9, cr3, [sl, #450] @ 0x1c2 @ │ │ - ldc2l 14, cr2, [ip, #492] @ 0x1ec │ │ + ldc2l 14, cr2, [ip, #672] @ 0x2a0 │ │ ldreq r7, [lr], #-760 @ 0xfffffd08 │ │ streq pc, [lr], #-4 │ │ ldreq r8, [lr], #-3660 @ 0xfffff1b4 │ │ ldreq r7, [lr], #-2264 @ 0xfffff728 │ │ streq lr, [lr], #-1192 @ 0xfffffb58 │ │ - ldc2l 7, cr13, [sl, #308] @ 0x134 │ │ - ldc2l 14, cr2, [ip, #236] @ 0xec │ │ + ldc2l 7, cr13, [sl, #488] @ 0x1e8 │ │ + ldc2l 14, cr2, [ip, #416] @ 0x1a0 │ │ ldreq r7, [lr], #-1324 @ 0xfffffad4 │ │ streq lr, [lr], #-4036 @ 0xfffff03c │ │ streq lr, [lr], #-236 @ 0xffffff14 │ │ strteq r3, [r6], #-3292 @ 0xfffff324 │ │ streq lr, [lr], #-1176 @ 0xfffffb68 │ │ - ldc2l 4, cr9, [fp, #416] @ 0x1a0 │ │ - ldc2l 13, cr2, [ip, #1004] @ 0x3ec │ │ + ldc2l 4, cr9, [fp, #596] @ 0x254 │ │ + ldc2l 14, cr2, [ip, #160] @ 0xa0 │ │ strteq r3, [r6], #-2308 @ 0xfffff6fc │ │ streq lr, [lr], #-3972 @ 0xfffff07c │ │ streq lr, [lr], #-176 @ 0xffffff50 │ │ strteq r3, [r6], #-3896 @ 0xfffff0c8 │ │ streq r0, [pc], #-4052 @ 2474574 │ │ - ldc2l 0, cr15, [fp, #456] @ 0x1c8 │ │ - ldc2l 13, cr2, [ip, #748] @ 0x2ec │ │ + ldc2l 0, cr15, [fp, #636] @ 0x27c │ │ + ldc2l 13, cr2, [ip, #928] @ 0x3a0 │ │ strteq r3, [r6], #-2872 @ 0xfffff4c8 │ │ streq lr, [lr], #-3908 @ 0xfffff0bc │ │ streq r0, [pc], #-3012 @ 2474588 │ │ strteq r1, [sl], #-1772 @ 0xfffff914 │ │ - ldc2l 3, cr9, [fp, #944] @ 0x3b0 │ │ - ldc2l 13, cr2, [ip, #492] @ 0x1ec │ │ + ldc2l 4, cr9, [fp, #100] @ 0x64 │ │ + ldc2l 13, cr2, [ip, #672] @ 0x2a0 │ │ strteq r1, [sl], #-712 @ 0xfffffd38 │ │ streq lr, [lr], #-3844 @ 0xfffff0fc │ │ ldc2l 0, cr7, [ip, #200] @ 0xc8 │ │ - ldc2l 13, cr2, [ip, #220] @ 0xdc │ │ + ldc2l 13, cr2, [ip, #400] @ 0x190 │ │ streq pc, [lr], #-3072 @ 0xfffff400 │ │ streq fp, [lr], #-284 @ 0xfffffee4 │ │ eoreq r5, lr, r0, lsr #3 │ │ streq pc, [lr], #-776 @ 0xfffffcf8 │ │ - ldc2l 6, cr13, [fp, #72] @ 0x48 │ │ - ldc2l 1, cr3, [ip, #220] @ 0xdc │ │ + ldc2l 6, cr13, [fp, #252] @ 0xfc │ │ + ldc2l 1, cr3, [ip, #400] @ 0x190 │ │ streq lr, [lr], #-1032 @ 0xfffffbf8 │ │ streq fp, [lr], #-132 @ 0xffffff7c │ │ eoreq r5, lr, r0, asr #2 │ │ streq pc, [lr], #-680 @ 0xfffffd58 │ │ - ldc2l 0, cr1, [ip, #428] @ 0x1ac │ │ - ldc2l 0, cr3, [ip, #876] @ 0x36c │ │ + ldc2l 0, cr1, [ip, #608] @ 0x260 │ │ + ldc2l 1, cr3, [ip, #32] │ │ ldreq r6, [lr], #-1020 @ 0xfffffc04 │ │ streq ip, [lr], #-2432 @ 0xfffff680 │ │ eoreq r5, lr, r4, ror #1 │ │ streq pc, [lr], #-580 @ 0xfffffdbc │ │ ldreq r9, [lr], #-144 @ 0xffffff70 │ │ ldc2l 6, cr1, [sl, #24] │ │ - ldc2l 0, cr3, [ip, #428] @ 0x1ac │ │ + ldc2l 0, cr3, [ip, #608] @ 0x260 │ │ streq r0, [pc], #-3728 @ 24745f4 │ │ streq fp, [lr], #-8 │ │ streq pc, [lr], #-480 @ 0xfffffe20 │ │ ldc2l 12, cr2, [sp, #96] @ 0x60 │ │ - ldc2l 0, cr3, [ip, #76] @ 0x4c │ │ + ldc2l 0, cr3, [ip, #256] @ 0x100 │ │ ldreq r9, [lr], #-132 @ 0xffffff7c │ │ streq sp, [lr], #-1616 @ 0xfffff9b0 │ │ eoreq r5, lr, r4, lsr #32 │ │ streq pc, [lr], #-388 @ 0xfffffe7c │ │ ldc2l 13, cr14, [ip, #312] @ 0x138 │ │ - ldc2l 15, cr2, [ip, #716] @ 0x2cc │ │ + ldc2l 15, cr2, [ip, #896] @ 0x380 │ │ strteq r6, [r2], #-1380 @ 0xfffffa9c │ │ streq sp, [lr], #-3120 @ 0xfffff3d0 │ │ eoreq r4, lr, r4, asr #31 │ │ streq pc, [lr], #-292 @ 0xfffffedc │ │ ldc2l 10, cr3, [sl, #784] @ 0x310 @ │ │ - ldc2l 15, cr2, [ip, #348] @ 0x15c │ │ + ldc2l 15, cr2, [ip, #528] @ 0x210 │ │ strteq r3, [r6], #-3920 @ 0xfffff0b0 │ │ streq pc, [lr], #-244 @ 0xffffff0c │ │ eoreq r4, lr, r8, ror #30 │ │ ldc2l 4, cr9, [sp, #592] @ 0x250 │ │ │ │ 02474640 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ @@ -1356763,15 +1356763,15 @@ │ │ bl 270e930 │ │ b 2474878 │ │ ldc2l 7, cr8, [sp, #188] @ 0xbc │ │ eoreq r4, lr, r4, asr r9 │ │ eoreq r4, lr, r4, asr r9 │ │ strdeq r4, [lr], -r0 @ │ │ ldc2l 11, cr10, [ip, #452] @ 0x1c4 @ │ │ - ldc2l 7, cr14, [sl, #260] @ 0x104 │ │ + ldc2l 7, cr14, [sl, #440] @ 0x1b8 │ │ eoreq r4, lr, r0, lsl #17 │ │ ldc2l 13, cr0, [sl, #788] @ 0x314 │ │ eoreq r4, lr, r8, lsl #16 │ │ strdeq r4, [lr], -ip @ │ │ ldc2l 6, cr8, [sp, #924] @ 0x39c │ │ │ │ 024748e0 : │ │ @@ -1356837,15 +1356837,15 @@ │ │ bl 270d370 │ │ mov r0, r8 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ - ldc2l 7, cr2, [ip, #224] @ 0xe0 │ │ + ldc2l 7, cr2, [ip, #404] @ 0x194 │ │ eoreq r4, lr, r0, lsr r7 │ │ eoreq r4, lr, ip, lsr #14 │ │ │ │ 024749f4 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ @@ -1356872,15 +1356872,15 @@ │ │ strd r0, [r4, #16] │ │ mov r0, r5 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 15, cr0, [fp, #720] @ 0x2d0 │ │ + ldc2l 15, cr0, [fp, #900] @ 0x384 │ │ │ │ 02474a70 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d15} │ │ sub sp, sp, #104 @ 0x68 │ │ @@ -1357091,15 +1357091,15 @@ │ │ strd r0, [r4, #16] │ │ mov r0, r5 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 10, cr10, [sl, #496] @ 0x1f0 @ │ │ + ldc2l 10, cr10, [sl, #676] @ 0x2a4 @ │ │ │ │ 02474dcc : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #32 │ │ mov r6, r3 │ │ mov r5, r2 │ │ @@ -1357171,20 +1357171,20 @@ │ │ ldr r0, [pc, #40] @ 2474f14 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - ldc2l 1, cr0, [ip, #664] @ 0x298 │ │ - ldc2l 9, cr12, [sl, #246] @ 0xf6 @ │ │ - ldc2l 0, cr14, [sl, #756] @ 0x2f4 │ │ - ldc2l 9, cr12, [sl, #210] @ 0xd2 @ │ │ + ldc2l 1, cr0, [ip, #844] @ 0x34c │ │ + ldc2l 9, cr12, [sl, #336] @ 0x150 @ │ │ + ldc2l 0, cr14, [sl, #936] @ 0x3a8 │ │ + ldc2l 9, cr12, [sl, #300] @ 0x12c @ │ │ eoreq r4, lr, r0, ror #3 │ │ - ldc2l 0, cr0, [ip, #728] @ 0x2d8 │ │ + ldc2l 0, cr0, [ip, #908] @ 0x38c │ │ │ │ 02474f18 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #252 @ 0xfc │ │ mov r4, r2 │ │ mov r5, r1 │ │ @@ -1357388,18 +1357388,18 @@ │ │ vstr d17, [r4, #136] @ 0x88 │ │ ldr r0, [pc, #28] @ 2475268 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 5, cr12, [fp, #676] @ 0x2a4 │ │ + ldc2l 5, cr12, [fp, #856] @ 0x358 │ │ eoreq r3, lr, ip, lsr #31 │ │ eoreq r3, lr, r8, lsr #31 │ │ - ldc2l 2, cr12, [fp, #660] @ 0x294 │ │ + ldc2l 2, cr12, [fp, #840] @ 0x348 │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ │ │ 02475270 : │ │ ldr r0, [pc, #64] @ 24752b8 │ │ add r0, pc, r0 │ │ vldr d16, [r0] │ │ vcmp.f64 d16, #0.0 │ │ @@ -1357512,19 +1357512,19 @@ │ │ bl 270ef50 │ │ mov r0, r5 │ │ mov r1, r7 │ │ mov r2, r4 │ │ mov r3, sl │ │ bl 270ef50 │ │ b 24753d4 │ │ - ldc2l 3, cr8, [sl, #860] @ 0x35c │ │ - ldc2l 12, cr1, [ip, #812] @ 0x32c │ │ - ldc2l 11, cr13, [sl, #420] @ 0x1a4 @ │ │ + ldc2l 4, cr8, [sl, #16] │ │ + ldc2l 12, cr1, [ip, #992] @ 0x3e0 │ │ + ldc2l 11, cr13, [sl, #600] @ 0x258 @ │ │ ldc2l 1, cr0, [sl, #992] @ 0x3e0 │ │ - ldc2l 3, cr8, [sl, #236] @ 0xec │ │ + ldc2l 3, cr8, [sl, #416] @ 0x1a0 │ │ │ │ 02475448 : │ │ ldr r1, [r1] │ │ cmp r1, #0 │ │ beq 24754b0 │ │ vldr d16, [r0] │ │ cmn r1, #1 │ │ @@ -1357689,25 +1357689,25 @@ │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 7, cr1, [sp, #160] @ 0xa0 │ │ - ldc2l 2, cr6, [fp, #360] @ 0x168 │ │ + ldc2l 2, cr6, [fp, #540] @ 0x21c │ │ strteq r0, [sl], #-704 @ 0xfffffd40 │ │ - ldc2l 9, cr14, [fp, #104] @ 0x68 @ │ │ - ldc2l 1, cr4, [fp, #220] @ 0xdc │ │ - ldc2l 8, cr13, [sl, #740] @ 0x2e4 │ │ - ldc2l 12, cr5, [fp, #276] @ 0x114 │ │ - ldc2l 2, cr12, [sl, #736] @ 0x2e0 │ │ - ldc2l 8, cr13, [sl, #500] @ 0x1f4 │ │ + ldc2l 9, cr14, [fp, #194] @ 0xc2 @ │ │ + ldc2l 1, cr4, [fp, #400] @ 0x190 │ │ + vcadd.f32 , q13, q11, #270 │ │ + ldc2l 12, cr5, [fp, #456] @ 0x1c8 │ │ + ldc2l 2, cr12, [sl, #916] @ 0x394 │ │ + vcadd.f32 d29, d26, d26, #270 │ │ ldc2l 11, cr7, [ip, #532] @ 0x214 @ │ │ - ldc2l 2, cr10, [sl, #188] @ 0xbc │ │ - ldc2l 9, cr13, [sl, #50] @ 0x32 @ │ │ + ldc2l 2, cr10, [sl, #368] @ 0x170 │ │ + ldc2l 9, cr13, [sl, #140] @ 0x8c @ │ │ ldc2l 4, cr15, [ip, #868] @ 0x364 │ │ ldrdeq r3, [lr], -r0 @ │ │ ldc2l 5, cr1, [sp, #272] @ 0x110 │ │ │ │ 02475720 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -1357769,18 +1357769,18 @@ │ │ mov r0, r8 │ │ mov r1, #6 │ │ ldr r7, [sp, #44] @ 0x2c │ │ bl 270ceb0 │ │ mov r0, r7 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 15, cr7, [sl, #820] @ 0x334 │ │ - ldc2l 15, cr5, [fp, #968] @ 0x3c8 │ │ + ldc2l 15, cr7, [sl, #1000] @ 0x3e8 │ │ + ldc2l 0, cr6, [fp, #124] @ 0x7c │ │ strteq r0, [sl], #-92 @ 0xffffffa4 │ │ - ldc2l 6, cr14, [fp, #816] @ 0x330 │ │ + ldc2l 6, cr14, [fp, #996] @ 0x3e4 │ │ │ │ 02475830 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8} │ │ sub sp, sp, #72 @ 0x48 │ │ @@ -1358804,26 +1358804,26 @@ │ │ bl 270e110 │ │ mov r0, #0 │ │ str r0, [r7] │ │ b 2475f98 │ │ strteq r3, [sl], #-2836 @ 0xfffff4ec │ │ eoreq r3, lr, r4, lsl r8 │ │ strteq r4, [sl], #-36 @ 0xffffffdc │ │ - ldc2l 15, cr9, [sl, #904] @ 0x388 │ │ + ldc2l 0, cr10, [sl, #60] @ 0x3c │ │ strteq r3, [sl], #-4072 @ 0xfffff018 │ │ strteq r3, [sl], #-4048 @ 0xfffff030 │ │ strteq r3, [sl], #-2692 @ 0xfffff57c │ │ strteq pc, [r9], #-3860 @ 0xfffff0ec │ │ strteq r3, [sl], #-4016 @ 0xfffff050 │ │ - ldc2l 14, cr3, [fp, #564] @ 0x234 │ │ + ldc2l 14, cr3, [fp, #744] @ 0x2e8 │ │ ldc2l 3, cr1, [sp, #28] │ │ strteq r4, [sl], #-1548 @ 0xfffff9f4 │ │ strteq r4, [sl], #-1724 @ 0xfffff944 │ │ - ldc2l 14, cr5, [fp, #124] @ 0x7c │ │ - ldc2l 5, cr13, [sl, #628] @ 0x274 │ │ + ldc2l 14, cr5, [fp, #304] @ 0x130 │ │ + ldc2l 5, cr13, [sl, #808] @ 0x328 │ │ strteq r3, [sl], #-3848 @ 0xfffff0f8 │ │ strteq r4, [sl], #-1672 @ 0xfffff978 │ │ strteq pc, [r9], #-3688 @ 0xfffff198 │ │ eoreq r3, lr, ip, ror #13 │ │ strteq r3, [sl], #-2504 @ 0xfffff638 │ │ strteq r3, [sl], #-3828 @ 0xfffff10c │ │ strteq r3, [sl], #-3808 @ 0xfffff120 │ │ @@ -1358967,17 +1358967,17 @@ │ │ strteq pc, [r9], #-3204 @ 0xfffff37c │ │ eoreq r3, lr, ip, asr #9 │ │ strteq r3, [sl], #-3296 @ 0xfffff320 │ │ ldc2l 10, cr15, [r9, #40] @ 0x28 @ │ │ ldc2l 15, cr14, [ip, #168] @ 0xa8 │ │ mlaeq lr, r8, r4, r3 │ │ strteq r3, [sl], #-3244 @ 0xfffff354 │ │ - ldc2l 9, cr9, [fp, #316] @ 0x13c @ │ │ - ldc2l 2, cr13, [sl, #932] @ 0x3a4 │ │ - ldc2l 12, cr9, [sl, #356] @ 0x164 │ │ + ldc2l 9, cr9, [fp, #406] @ 0x196 @ │ │ + ldc2l 3, cr13, [sl, #88] @ 0x58 │ │ + ldc2l 12, cr9, [sl, #536] @ 0x218 │ │ strteq r4, [sl], #-996 @ 0xfffffc1c │ │ mov r1, r8 │ │ ldr r0, [pc, #4048] @ 2477abc │ │ mov r3, #32 │ │ ldr r2, [pc, #4044] @ 2477ac0 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1359083,15 +1359083,15 @@ │ │ strteq r4, [sl], #-784 @ 0xfffffcf0 │ │ strteq r4, [sl], #-392 @ 0xfffffe78 │ │ strteq r4, [sl], #-376 @ 0xfffffe88 │ │ ldc2l 11, cr7, [sp, #816] @ 0x330 @ │ │ strteq r3, [sl], #-2252 @ 0xfffff734 │ │ strteq r4, [sl], #-420 @ 0xfffffe5c │ │ strteq r4, [sl], #-288 @ 0xfffffee0 │ │ - ldc2l 8, cr7, [sl, #960] @ 0x3c0 │ │ + ldc2l 9, cr7, [sl, #58] @ 0x3a @ │ │ strteq r4, [sl], #-352 @ 0xfffffea0 │ │ strteq r4, [sl], #-340 @ 0xfffffeac │ │ strteq r4, [sl], #-328 @ 0xfffffeb8 │ │ strteq r4, [sl], #-180 @ 0xffffff4c │ │ ldc2l 11, cr7, [sp, #48] @ 0x30 @ │ │ str r7, [sp, #40] @ 0x28 │ │ mov r1, sl │ │ @@ -1359213,16 +1359213,16 @@ │ │ mov r0, r4 │ │ mov r1, r6 │ │ bl 270ec40 │ │ ldr r7, [sp, #52] @ 0x34 │ │ ldr r5, [sp, #44] @ 0x2c │ │ b 2477388 │ │ strteq r4, [sl], #-132 @ 0xffffff7c │ │ - ldc2l 8, cr7, [sl, #336] @ 0x150 │ │ - ldc2l 9, cr9, [sl, #268] @ 0x10c @ │ │ + vcadd.f32 d23, d26, d1, #270 │ │ + ldc2l 9, cr9, [sl, #358] @ 0x166 @ │ │ strteq r3, [sl], #-2000 @ 0xfffff830 │ │ ldc2l 4, cr5, [ip, #36] @ 0x24 │ │ ldc2l 1, cr6, [ip, #192] @ 0xc0 │ │ eoreq r3, lr, ip, ror r1 │ │ ldr r0, [pc, #3796] @ 2477d9c │ │ ldr r1, [pc, #3796] @ 2477da0 │ │ add r0, pc, r0 │ │ @@ -1359249,33 +1359249,33 @@ │ │ mov r2, #1 │ │ mov r3, #32 │ │ bl 270da60 │ │ ldr r1, [pc, #3708] @ 2477dac │ │ mov r0, r6 │ │ add r1, pc, r1 │ │ b 2476080 │ │ - ldc2l 9, cr9, [sl, #84] @ 0x54 @ │ │ + ldc2l 9, cr9, [sl, #174] @ 0xae @ │ │ ldc2l 3, cr5, [ip, #740] @ 0x2e4 │ │ eoreq r3, lr, r8, lsl #2 │ │ strteq r3, [sl], #-2332 @ 0xfffff6e4 │ │ eoreq r3, lr, r0, ror #1 │ │ strteq r3, [sl], #-2292 @ 0xfffff70c │ │ - vcadd.f32 , q13, q4, #270 │ │ + ldc2l 8, cr9, [sl, #980] @ 0x3d4 │ │ strteq r3, [sl], #-3932 @ 0xfffff0a4 │ │ ldc2l 9, cr7, [sp, #368] @ 0x170 @ │ │ ldc2l 12, cr0, [sp, #124] @ 0x7c │ │ - ldc2l 14, cr12, [sl, #948] @ 0x3b4 │ │ + ldc2l 15, cr12, [sl, #104] @ 0x68 │ │ strteq r3, [sl], #-1716 @ 0xfffff94c │ │ strteq r3, [sl], #-3852 @ 0xfffff0f4 │ │ - ldc2l 6, cr7, [sl, #880] @ 0x370 │ │ + ldc2l 7, cr7, [sl, #36] @ 0x24 │ │ ldc2l 11, cr0, [sp, #828] @ 0x33c @ │ │ - ldc2l 14, cr12, [sl, #644] @ 0x284 │ │ + ldc2l 14, cr12, [sl, #824] @ 0x338 │ │ strteq r3, [sl], #-3904 @ 0xfffff0c0 │ │ - ldc2l 15, cr0, [ip, #616] @ 0x268 │ │ - ldc2l 7, cr9, [sl, #872] @ 0x368 │ │ + ldc2l 15, cr0, [ip, #796] @ 0x31c │ │ + vcadd.f32 d25, d10, d7, #270 │ │ ldc2l 6, cr8, [sp, #608] @ 0x260 │ │ ldc2l 11, cr0, [sp, #300] @ 0x12c @ │ │ strteq pc, [r9], #-1812 @ 0xfffff8ec │ │ ldr r0, [pc, #3684] @ 2477dfc │ │ mov r4, #1 │ │ ldr r2, [pc, #3680] @ 2477e00 │ │ mov r6, #32 │ │ @@ -1359403,16 +1359403,16 @@ │ │ bl 270da30 │ │ ldr r2, [pc, #3268] @ 2477e54 │ │ mov r1, r0 │ │ ldr r2, [pc, r2] │ │ b 2477100 │ │ ldrdeq r2, [lr], -ip @ │ │ strteq r3, [sl], #-1776 @ 0xfffff910 │ │ - ldc2l 6, cr9, [sl, #696] @ 0x2b8 │ │ - ldc2l 6, cr9, [sl, #616] @ 0x268 │ │ + ldc2l 6, cr9, [sl, #876] @ 0x36c │ │ + ldc2l 6, cr9, [sl, #796] @ 0x31c │ │ ldc2l 5, cr8, [sp, #448] @ 0x1c0 │ │ ldc2l 10, cr0, [sp, #140] @ 0x8c @ │ │ strteq pc, [r9], #-1520 @ 0xfffffa10 │ │ ldc2l 5, cr8, [sp, #192] @ 0xc0 │ │ ldc2l 9, cr0, [sp, #454] @ 0x1c6 @ │ │ strteq pc, [r9], #-1456 @ 0xfffffa50 │ │ ldc2l 4, cr8, [sp, #960] @ 0x3c0 │ │ @@ -1359550,51 +1359550,51 @@ │ │ eoreq r2, lr, ip, ror ip │ │ strteq r3, [sl], #-2852 @ 0xfffff4dc │ │ strteq r3, [sl], #-656 @ 0xfffffd70 │ │ strteq r3, [sl], #-3204 @ 0xfffff37c │ │ strteq r3, [sl], #-568 @ 0xfffffdc8 │ │ eoreq r2, lr, r0, ror #23 │ │ strteq r3, [sl], #-1012 @ 0xfffffc0c │ │ - ldc2l 13, cr12, [fp, #1000] @ 0x3e8 │ │ - ldc2l 10, cr12, [sl, #116] @ 0x74 @ │ │ + ldc2l 14, cr12, [fp, #156] @ 0x9c │ │ + ldc2l 10, cr12, [sl, #296] @ 0x128 @ │ │ strteq r3, [sl], #-420 @ 0xfffffe5c │ │ ldc2l 14, cr8, [ip, #656] @ 0x290 │ │ eoreq r2, lr, ip, ror #22 │ │ strteq r3, [sl], #-896 @ 0xfffffc80 │ │ - ldc2l 11, cr0, [ip, #208] @ 0xd0 @ │ │ - ldc2l 9, cr12, [sl, #362] @ 0x16a @ │ │ + ldc2l 11, cr0, [ip, #388] @ 0x184 @ │ │ + ldc2l 9, cr12, [sl, #452] @ 0x1c4 @ │ │ strteq r3, [sl], #-292 @ 0xfffffedc │ │ ldc2l 8, cr6, [sp, #216] @ 0xd8 │ │ strteq r3, [sl], #-284 @ 0xfffffee4 │ │ - ldc2l 4, cr9, [sl, #4] │ │ + ldc2l 4, cr9, [sl, #184] @ 0xb8 │ │ strteq r3, [sl], #-220 @ 0xffffff24 │ │ ldc2l 5, cr1, [sl, #680] @ 0x2a8 │ │ strteq r3, [sl], #-180 @ 0xffffff4c │ │ ldc2l 7, cr6, [sp, #824] @ 0x338 │ │ eoreq r2, lr, r4, ror sl │ │ strteq r3, [sl], #-648 @ 0xfffffd78 │ │ ldc2l 12, cr4, [ip, #844] @ 0x34c │ │ - vcadd.f32 d28, d26, d29, #270 │ │ + ldc2l 8, cr12, [sl, #872] @ 0x368 │ │ strteq r3, [sl], #-116 @ 0xffffff8c │ │ strteq r3, [sl], #-56 @ 0xffffffc8 │ │ ldc2l 0, cr8, [sp, #920] @ 0x398 │ │ - ldc2l 0, cr5, [fp, #724] @ 0x2d4 │ │ + ldc2l 0, cr5, [fp, #904] @ 0x388 │ │ eoreq r2, lr, r4, ror #19 │ │ strteq r3, [sl], #-2180 @ 0xfffff77c │ │ strteq r3, [sl], #-2164 @ 0xfffff78c │ │ strteq r3, [sl], #-2240 @ 0xfffff740 │ │ strteq r3, [sl], #-2328 @ 0xfffff6e8 │ │ strteq r3, [sl], #-2448 @ 0xfffff670 │ │ strteq r3, [sl], #-2160 @ 0xfffff790 │ │ strteq r3, [sl], #-2040 @ 0xfffff808 │ │ strteq r3, [sl], #-1988 @ 0xfffff83c │ │ strteq r3, [sl], #-2116 @ 0xfffff7bc │ │ strteq r3, [sl], #-2096 @ 0xfffff7d0 │ │ strteq r3, [sl], #-2084 @ 0xfffff7dc │ │ - ldc2l 0, cr9, [sl, #680] @ 0x2a8 │ │ + ldc2l 0, cr9, [sl, #860] @ 0x35c │ │ ldc2l 11, cr4, [ip, #212] @ 0xd4 @ │ │ strhteq r2, [lr], -r4 │ │ ldc2l 5, cr1, [sp, #84] @ 0x54 │ │ mlaeq lr, r8, r8, r2 │ │ strteq r3, [sl], #-2200 @ 0xfffff768 │ │ eoreq r2, lr, r8, ror #16 │ │ strteq r3, [sl], #-124 @ 0xffffff84 │ │ @@ -1360032,15 +1360032,15 @@ │ │ vldr d8, [r1, #32] │ │ sub r1, r0, #5 │ │ bhi 2477b84 │ │ add r7, sp, #44 @ 0x2c │ │ ldm r7, {r5, r6, r7} │ │ b 2477550 │ │ strteq r3, [sl], #-964 @ 0xfffffc3c │ │ - ldc2l 11, cr6, [sl, #592] @ 0x250 @ │ │ + ldc2l 11, cr6, [sl, #772] @ 0x304 @ │ │ strteq r3, [sl], #-1280 @ 0xfffffb00 │ │ strteq r3, [sl], #-1012 @ 0xfffffc0c │ │ strteq r3, [sl], #-1000 @ 0xfffffc18 │ │ ldr r0, [pc, #820] @ 2477ec0 │ │ movw r3, #1058 @ 0x422 │ │ ldr r2, [pc, #816] @ 2477ec4 │ │ add r0, pc, r0 │ │ @@ -1360059,15 +1360059,15 @@ │ │ bhi 2477be4 │ │ add r7, sp, #44 @ 0x2c │ │ ldm r7, {r5, r6, r7} │ │ b 2477568 │ │ strteq r3, [sl], #-852 @ 0xfffffcac │ │ ldc2l 13, cr6, [sp, #688] @ 0x2b0 │ │ strteq r3, [sl], #-804 @ 0xfffffcdc │ │ - ldc2l 10, cr6, [sl, #976] @ 0x3d0 @ │ │ + ldc2l 11, cr6, [sl, #132] @ 0x84 @ │ │ ldr r0, [pc, #740] @ 2477ed0 │ │ movw r3, #1059 @ 0x423 │ │ ldr r2, [pc, #736] @ 2477ed4 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ add r0, r8, r0, lsl #3 │ │ @@ -1360100,15 +1360100,15 @@ │ │ cmp r3, #199 @ 0xc7 │ │ vldr d8, [r1, #56] @ 0x38 │ │ sub r1, r0, #2 │ │ bhi 2477c90 │ │ add r7, sp, #44 @ 0x2c │ │ ldm r7, {r5, r6, r7} │ │ b 2477598 │ │ - ldc2l 9, cr6, [fp, #312] @ 0x138 @ │ │ + ldc2l 9, cr6, [fp, #402] @ 0x192 @ │ │ strhteq r2, [lr], -r4 │ │ strteq r3, [sl], #-600 @ 0xfffffda8 │ │ ldr r0, [pc, #600] @ 2477ef0 │ │ movw r3, #1061 @ 0x425 │ │ ldr r2, [pc, #596] @ 2477ef4 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1360160,77 +1360160,77 @@ │ │ b 24775c4 │ │ strteq r3, [sl], #-576 @ 0xfffffdc0 │ │ strteq r3, [sl], #-456 @ 0xfffffe38 │ │ strteq r3, [sl], #-404 @ 0xfffffe6c │ │ strteq r3, [sl], #-536 @ 0xfffffde8 │ │ strteq r3, [sl], #-520 @ 0xfffffdf8 │ │ strteq r3, [sl], #-508 @ 0xfffffe04 │ │ - ldc2l 10, cr8, [sl, #536] @ 0x218 @ │ │ + ldc2l 10, cr8, [sl, #716] @ 0x2cc @ │ │ ldc2l 5, cr4, [ip, #68] @ 0x44 │ │ eoreq r2, lr, r0, lsr #5 │ │ ldc2l 14, cr0, [sp, #964] @ 0x3c4 │ │ eoreq r2, lr, r4, ror r2 │ │ strteq r3, [sl], #-584 @ 0xfffffdb8 │ │ eoreq r2, lr, r4, asr #4 │ │ eoreq r2, lr, r4, asr r2 │ │ strteq r3, [sl], #-228 @ 0xffffff1c │ │ strteq r3, [sl], #-584 @ 0xfffffdb8 │ │ eoreq r2, lr, r0, asr #3 │ │ strteq r2, [sl], #-2516 @ 0xfffff62c │ │ - ldc2l 9, cr8, [sl, #336] @ 0x150 @ │ │ - ldc2l 15, cr11, [sl, #996] @ 0x3e4 │ │ + ldc2l 9, cr8, [sl, #426] @ 0x1aa @ │ │ + ldc2l 0, cr12, [sl, #152] @ 0x98 │ │ strteq r3, [sl], #-140 @ 0xffffff74 │ │ strteq r2, [sl], #-3424 @ 0xfffff2a0 │ │ eoreq r1, lr, r4, lsr #27 │ │ eoreq r1, lr, r8, lsr #27 │ │ strteq r2, [sl], #-3144 @ 0xfffff3b8 │ │ eoreq r1, lr, ip, asr #26 │ │ eoreq r1, lr, r8, lsl sp │ │ strhteq r1, [lr], -r4 │ │ strteq r2, [sl], #-1736 @ 0xfffff938 │ │ - ldc2l 6, cr8, [sl, #624] @ 0x270 │ │ + ldc2l 6, cr8, [sl, #804] @ 0x324 │ │ strteq r2, [sl], #-3376 @ 0xfffff2d0 │ │ ldc2l 7, cr6, [sp, #560] @ 0x230 │ │ ldc2l 9, cr15, [ip, #486] @ 0x1e6 @ │ │ strteq r2, [sl], #-1160 @ 0xfffffb78 │ │ strteq r2, [sl], #-3672 @ 0xfffff1a8 │ │ - ldc2l 12, cr11, [sl, #708] @ 0x2c4 │ │ + ldc2l 12, cr11, [sl, #888] @ 0x378 │ │ strteq r2, [sl], #-3288 @ 0xfffff328 │ │ - ldc2l 4, cr6, [sl, #672] @ 0x2a0 │ │ + ldc2l 4, cr6, [sl, #852] @ 0x354 │ │ ldc2l 9, cr15, [ip, #310] @ 0x136 @ │ │ - ldc2l 12, cr11, [sl, #436] @ 0x1b4 │ │ - ldc2l 8, cr8, [sl, #856] @ 0x358 │ │ + ldc2l 12, cr11, [sl, #616] @ 0x268 │ │ + ldc2l 9, cr8, [sl, #6] @ │ │ ldc2l 3, cr4, [ip, #388] @ 0x184 │ │ eoreq r2, lr, ip, ror #1 │ │ ldc2l 13, cr0, [sp, #212] @ 0xd4 │ │ eoreq r2, lr, ip, asr #1 │ │ - vcadd.f32 d24, d26, d6, #270 │ │ + ldc2l 8, cr8, [sl, #716] @ 0x2cc │ │ ldc2l 3, cr4, [ip, #68] @ 0x44 │ │ eoreq r2, lr, r0, lsr #1 │ │ strteq r2, [sl], #-3932 @ 0xfffff0a4 │ │ ldc2l 10, cr5, [sp, #712] @ 0x2c8 @ │ │ strteq r2, [sl], #-3976 @ 0xfffff078 │ │ eoreq r2, lr, ip, lsr #32 │ │ eoreq r2, lr, r8, lsr r0 │ │ strteq r2, [sl], #-3788 @ 0xfffff134 │ │ strteq r3, [sl], #-44 @ 0xffffffd4 │ │ strteq r2, [sl], #-2040 @ 0xfffff808 │ │ strdeq r1, [lr], -r8 @ │ │ strteq r2, [sl], #-3680 @ 0xfffff1a0 │ │ strteq r2, [sl], #-3708 @ 0xfffff184 │ │ - ldc2l 6, cr4, [fp, #532] @ 0x214 │ │ + ldc2l 6, cr4, [fp, #712] @ 0x2c8 │ │ ldc2l 11, cr15, [ip, #156] @ 0x9c @ │ │ strteq r2, [sl], #-3536 @ 0xfffff230 │ │ strteq r2, [sl], #-3496 @ 0xfffff258 │ │ strteq r2, [sl], #-3624 @ 0xfffff1d8 │ │ strteq r1, [sl], #-3520 @ 0xfffff240 │ │ ldrdeq r1, [lr], -r8 @ │ │ strteq r1, [sl], #-3820 @ 0xfffff114 │ │ - ldc2l 14, cr7, [sl, #768] @ 0x300 │ │ - ldc2l 5, cr11, [sl, #68] @ 0x44 │ │ + ldc2l 14, cr7, [sl, #948] @ 0x3b4 │ │ + ldc2l 5, cr11, [sl, #248] @ 0xf8 │ │ strteq r3, [sl], #-156 @ 0xffffff64 │ │ strteq lr, [r9], #-1140 @ 0xfffffb8c │ │ strteq lr, [r9], #-1116 @ 0xfffffba4 │ │ ldc2l 2, cr7, [sp, #608] @ 0x260 │ │ ldc2l 7, cr15, [ip, #300] @ 0x12c │ │ strteq lr, [r9], #-812 @ 0xfffffcd4 │ │ strteq lr, [r9], #-788 @ 0xfffffcec │ │ @@ -1360276,32 +1360276,32 @@ │ │ ldc2l 0, cr14, [r9, #100] @ 0x64 │ │ strteq r2, [sl], #-152 @ 0xffffff68 │ │ strteq r2, [sl], #-2284 @ 0xfffff714 │ │ ldc2l 10, cr9, [ip, #800] @ 0x320 @ │ │ strteq r2, [sl], #-2224 @ 0xfffff750 │ │ ldc2l 13, cr7, [ip, #148] @ 0x94 │ │ strteq r2, [sl], #-2168 @ 0xfffff788 │ │ - ldc2l 0, cr4, [fp, #564] @ 0x234 │ │ + ldc2l 0, cr4, [fp, #744] @ 0x2e8 │ │ strteq r2, [sl], #-2104 @ 0xfffff7c8 │ │ - ldc2l 15, cr5, [fp, #400] @ 0x190 │ │ + ldc2l 15, cr5, [fp, #580] @ 0x244 │ │ strteq r2, [sl], #-2044 @ 0xfffff804 │ │ ldc2l 6, cr5, [sp, #440] @ 0x1b8 │ │ strteq r2, [sl], #-1988 @ 0xfffff83c │ │ ldc2l 5, cr1, [sp, #340] @ 0x154 │ │ strteq r2, [sl], #-2048 @ 0xfffff800 │ │ ldc2l 14, cr13, [r9, #468] @ 0x1d4 │ │ strteq r2, [sl], #-2112 @ 0xfffff7c0 │ │ strteq r2, [sl], #-1976 @ 0xfffff848 │ │ ldc2l 9, cr9, [ip, #80] @ 0x50 @ │ │ strteq r2, [sl], #-1920 @ 0xfffff880 │ │ ldc2l 11, cr7, [ip, #484] @ 0x1e4 @ │ │ strteq r2, [sl], #-1860 @ 0xfffff8bc │ │ - ldc2l 14, cr3, [fp, #932] @ 0x3a4 │ │ + ldc2l 15, cr3, [fp, #88] @ 0x58 │ │ strteq r2, [sl], #-1804 @ 0xfffff8f4 │ │ - ldc2l 13, cr5, [fp, #752] @ 0x2f0 │ │ + ldc2l 13, cr5, [fp, #932] @ 0x3a4 │ │ strteq r2, [sl], #-1744 @ 0xfffff930 │ │ ldc2l 4, cr5, [sp, #792] @ 0x318 │ │ strteq r2, [sl], #-1688 @ 0xfffff968 │ │ ldc2l 3, cr1, [sp, #660] @ 0x294 │ │ eoreq r1, lr, ip, lsr r7 │ │ strteq r2, [sl], #-1496 @ 0xfffffa28 │ │ strteq r2, [sl], #-1684 @ 0xfffff96c │ │ @@ -1360612,22 +1360612,22 @@ │ │ add r0, pc, r0 │ │ str r1, [r4] │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 8, cr3, [sl, #968] @ 0x3c8 │ │ - vcadd.f32 , q5, q13, #270 │ │ + ldc2l 9, cr3, [sl, #62] @ 0x3e @ │ │ + ldc2l 8, cr3, [sl, #604] @ 0x25c │ │ ldc2l 10, cr1, [sl, #160] @ 0xa0 @ │ │ - ldc2l 13, cr10, [sl, #852] @ 0x354 │ │ + ldc2l 14, cr10, [sl, #8] │ │ ldc2l 4, cr13, [r9, #1004] @ 0x3ec │ │ - ldc2l 7, cr3, [sl, #360] @ 0x168 │ │ - ldc2l 6, cr3, [sl, #504] @ 0x1f8 │ │ - ldc2l 4, cr3, [sl, #344] @ 0x158 │ │ + ldc2l 7, cr3, [sl, #540] @ 0x21c │ │ + ldc2l 6, cr3, [sl, #684] @ 0x2ac │ │ + ldc2l 4, cr3, [sl, #524] @ 0x20c │ │ │ │ 0247849c : │ │ ldr r0, [r0, #40] @ 0x28 │ │ bx lr │ │ │ │ 024784a4 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ @@ -1360913,37 +1360913,37 @@ │ │ bl 270da60 │ │ ldr r0, [pc, #108] @ 247897c │ │ mov r1, #18 │ │ add r0, pc, r0 │ │ b 24787e8 │ │ ldc2l 13, cr0, [ip, #964] @ 0x3c4 │ │ ldc2l 12, cr0, [ip, #832] @ 0x340 │ │ - vcadd.f32 q13, q13, , #270 │ │ - ldc2l 1, cr3, [fp, #224] @ 0xe0 │ │ + ldc2l 9, cr10, [sl, #36] @ 0x24 @ │ │ + ldc2l 1, cr3, [fp, #404] @ 0x194 │ │ ldc2l 13, cr2, [ip, #980] @ 0x3d4 │ │ - ldc2l 2, cr3, [fp, #352] @ 0x160 │ │ - ldc2l 15, cr8, [sl, #96] @ 0x60 │ │ + ldc2l 2, cr3, [fp, #532] @ 0x214 │ │ + ldc2l 15, cr8, [sl, #276] @ 0x114 │ │ ldc2l 3, cr0, [sp, #60] @ 0x3c │ │ - ldc2l 2, cr1, [fp, #32] │ │ + ldc2l 2, cr1, [fp, #212] @ 0xd4 │ │ ldc2l 13, cr4, [ip, #652] @ 0x28c │ │ - ldc2l 9, cr10, [sl, #106] @ 0x6a @ │ │ - ldc2l 0, cr5, [fp, #572] @ 0x23c │ │ + ldc2l 9, cr10, [sl, #196] @ 0xc4 @ │ │ + ldc2l 0, cr5, [fp, #752] @ 0x2f0 │ │ ldc2l 14, cr7, [sp, #328] @ 0x148 │ │ - ldc2l 8, cr10, [sl, #340] @ 0x154 │ │ - ldc2l 9, cr14, [fp, #308] @ 0x134 @ │ │ - ldc2l 7, cr10, [sl, #468] @ 0x1d4 │ │ - ldc2l 0, cr3, [sl, #868] @ 0x364 │ │ + vcadd.f32 d26, d26, d2, #270 │ │ + ldc2l 9, cr14, [fp, #398] @ 0x18e @ │ │ + ldc2l 7, cr10, [sl, #648] @ 0x288 │ │ + ldc2l 1, cr3, [sl, #24] │ │ ldc2l 9, cr3, [ip, #32] @ │ │ ldc2l 15, cr12, [r9, #4] │ │ - ldc2l 6, cr10, [sl, #516] @ 0x204 │ │ + ldc2l 6, cr10, [sl, #696] @ 0x2b8 │ │ ldc2l 1, cr2, [sp, #976] @ 0x3d0 │ │ ldc2l 4, cr15, [ip, #740] @ 0x2e4 │ │ - ldc2l 0, cr9, [sl, #996] @ 0x3e4 │ │ + ldc2l 1, cr9, [sl, #152] @ 0x98 │ │ ldc2l 3, cr14, [ip, #332] @ 0x14c │ │ - ldc2l 6, cr10, [sl, #100] @ 0x64 │ │ + ldc2l 6, cr10, [sl, #280] @ 0x118 │ │ ldc2l 14, cr14, [r9, #920] @ 0x398 │ │ ldc2l 10, cr0, [ip, #868] @ 0x364 @ │ │ │ │ 02478984 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ @@ -1360982,16 +1360982,16 @@ │ │ mov r0, r5 │ │ mov r2, r4 │ │ mov r3, #17 │ │ add r1, pc, r1 │ │ bl 270d9e0 │ │ mov r0, #0 │ │ pop {r4, r5, fp, pc} │ │ - ldc2l 13, cr8, [sl, #336] @ 0x150 │ │ - ldc2l 0, cr11, [sl, #68] @ 0x44 │ │ + ldc2l 13, cr8, [sl, #516] @ 0x204 │ │ + ldc2l 0, cr11, [sl, #248] @ 0xf8 │ │ ldc2l 9, cr0, [ip, #364] @ 0x16c @ │ │ │ │ 02478a30 : │ │ ldr r0, [r0] │ │ bx lr │ │ │ │ 02478a38 : │ │ @@ -1361682,116 +1361682,116 @@ │ │ bl 270f2f0 │ │ ldr r1, [pc, #188] @ 24795b0 │ │ mov r0, r4 │ │ mov r2, #255 @ 0xff │ │ mov r3, #73 @ 0x49 │ │ add r1, pc, r1 │ │ b 2478ef0 │ │ - ldc2l 11, cr12, [sl, #972] @ 0x3cc @ │ │ + ldc2l 12, cr12, [sl, #128] @ 0x80 │ │ ldc2l 6, cr1, [sp, #888] @ 0x378 │ │ - ldc2l 11, cr6, [sl, #704] @ 0x2c0 @ │ │ + ldc2l 11, cr6, [sl, #884] @ 0x374 @ │ │ strteq r1, [sl], #-2024 @ 0xfffff818 │ │ strteq r1, [sl], #-1976 @ 0xfffff848 │ │ strteq r1, [sl], #-1952 @ 0xfffff860 │ │ ldc2l 4, cr2, [ip, #604] @ 0x25c │ │ - ldc2l 14, cr6, [sl, #1016] @ 0x3f8 │ │ + ldc2l 15, cr6, [sl, #172] @ 0xac │ │ strteq r1, [sl], #-1880 @ 0xfffff8a8 │ │ strteq r1, [sl], #-384 @ 0xfffffe80 │ │ strteq r1, [sl], #-380 @ 0xfffffe84 │ │ - ldc2l 15, cr3, [sl, #276] @ 0x114 │ │ + ldc2l 15, cr3, [sl, #456] @ 0x1c8 │ │ ldc2l 11, cr13, [ip, #392] @ 0x188 @ │ │ strteq r1, [sl], #-300 @ 0xfffffed4 │ │ strteq r1, [sl], #-296 @ 0xfffffed8 │ │ strteq r1, [sl], #-276 @ 0xfffffeec │ │ strteq r1, [sl], #-264 @ 0xfffffef8 │ │ ldc2l 14, cr4, [sp, #376] @ 0x178 │ │ ldc2l 5, cr1, [sp, #1004] @ 0x3ec │ │ strteq r1, [sl], #-1608 @ 0xfffff9b8 │ │ strteq r1, [sl], #-1608 @ 0xfffff9b8 │ │ strteq r1, [sl], #-252 @ 0xffffff04 │ │ strteq r1, [sl], #-168 @ 0xffffff58 │ │ ldc2l 13, cr1, [ip, #636] @ 0x27c │ │ - vcadd.f32 d22, d10, d10, #270 │ │ + ldc2l 8, cr6, [sl, #220] @ 0xdc │ │ strteq r1, [sl], #-116 @ 0xffffff8c │ │ - ldc2l 6, cr2, [sl, #448] @ 0x1c0 │ │ - ldc2l 15, cr13, [fp, #272] @ 0x110 │ │ - ldc2l 5, cr14, [sl, #576] @ 0x240 │ │ + ldc2l 6, cr2, [sl, #628] @ 0x274 │ │ + ldc2l 15, cr13, [fp, #452] @ 0x1c4 │ │ + ldc2l 5, cr14, [sl, #756] @ 0x2f4 │ │ strteq r0, [sl], #-4048 @ 0xfffff030 │ │ ldc2l 12, cr1, [ip, #796] @ 0x31c │ │ - ldc2l 7, cr6, [sl, #200] @ 0xc8 │ │ + ldc2l 7, cr6, [sl, #380] @ 0x17c │ │ strteq r0, [sl], #-3984 @ 0xfffff070 │ │ ldc2l 12, cr1, [ip, #540] @ 0x21c │ │ - ldc2l 6, cr6, [sl, #968] @ 0x3c8 │ │ + ldc2l 7, cr6, [sl, #124] @ 0x7c │ │ eoreq pc, sp, r4, lsl #27 │ │ - ldc2l 14, cr7, [sl, #160] @ 0xa0 │ │ + ldc2l 14, cr7, [sl, #340] @ 0x154 │ │ strteq r0, [sl], #-3860 @ 0xfffff0ec │ │ ldc2l 12, cr1, [ip, #44] @ 0x2c │ │ - ldc2l 6, cr6, [sl, #472] @ 0x1d8 │ │ + ldc2l 6, cr6, [sl, #652] @ 0x28c │ │ strteq r0, [sl], #-3772 @ 0xfffff144 │ │ strteq r0, [sl], #-3768 @ 0xfffff148 │ │ - ldc2l 14, cr9, [fp, #412] @ 0x19c │ │ + ldc2l 14, cr9, [fp, #592] @ 0x250 │ │ ldc2l 8, cr9, [ip, #720] @ 0x2d0 │ │ strteq r1, [sl], #-1588 @ 0xfffff9cc │ │ strteq r1, [sl], #-1696 @ 0xfffff960 │ │ strteq r1, [sl], #-1688 @ 0xfffff968 │ │ strteq r1, [sl], #-896 @ 0xfffffc80 │ │ strteq r1, [sl], #-888 @ 0xfffffc88 │ │ strteq r1, [sl], #-1684 @ 0xfffff96c │ │ strteq r1, [sl], #-1780 @ 0xfffff90c │ │ strteq r1, [sl], #-1776 @ 0xfffff910 │ │ - ldc2l 0, cr10, [fp, #36] @ 0x24 │ │ - ldc2l 1, cr12, [fp, #148] @ 0x94 │ │ - ldc2l 2, cr8, [sl, #704] @ 0x2c0 │ │ + ldc2l 0, cr10, [fp, #216] @ 0xd8 │ │ + ldc2l 1, cr12, [fp, #328] @ 0x148 │ │ + ldc2l 2, cr8, [sl, #884] @ 0x374 │ │ strdeq r0, [lr], -r4 @ │ │ strteq r2, [sl], #-868 @ 0xfffffc9c │ │ strteq r1, [sl], #-1116 @ 0xfffffba4 │ │ strteq r1, [sl], #-1112 @ 0xfffffba8 │ │ strteq r1, [sl], #-584 @ 0xfffffdb8 │ │ ldc2l 9, cr15, [ip, #16] @ │ │ ldc2l 1, cr14, [r9, #908] @ 0x38c │ │ strteq r1, [sl], #-1492 @ 0xfffffa2c │ │ strteq r2, [sl], #-588 @ 0xfffffdb4 │ │ strteq r2, [sl], #-3780 @ 0xfffff13c │ │ - ldc2l 2, cr2, [fp, #580] @ 0x244 │ │ + ldc2l 2, cr2, [fp, #760] @ 0x2f8 │ │ eoreq pc, sp, ip, lsr #25 │ │ - ldc2l 5, cr12, [sl, #456] @ 0x1c8 │ │ - ldc2l 5, cr6, [sl, #552] @ 0x228 │ │ + ldc2l 5, cr12, [sl, #636] @ 0x27c │ │ + ldc2l 5, cr6, [sl, #732] @ 0x2dc │ │ strteq r1, [sl], #-2784 @ 0xfffff520 │ │ strteq r1, [sl], #-1440 @ 0xfffffa60 │ │ - ldc2l 9, cr2, [fp, #330] @ 0x14a @ │ │ + ldc2l 9, cr2, [fp, #420] @ 0x1a4 @ │ │ strhteq r0, [lr], -ip │ │ strteq r1, [sl], #-1392 @ 0xfffffa90 │ │ strteq r1, [sl], #-1376 @ 0xfffffaa0 │ │ - ldc2l 7, cr2, [fp, #864] @ 0x360 │ │ + vcadd.f32 d18, d11, d5, #270 │ │ strdeq r0, [lr], -r0 @ │ │ strteq r2, [sl], #-2980 @ 0xfffff45c │ │ - ldc2l 5, cr6, [fp, #968] @ 0x3c8 │ │ + ldc2l 6, cr6, [fp, #124] @ 0x7c │ │ strteq r1, [sl], #-860 @ 0xfffffca4 │ │ strteq r1, [sl], #-840 @ 0xfffffcb8 │ │ strteq r2, [sl], #-3136 @ 0xfffff3c0 │ │ eoreq r0, lr, r0, asr r0 │ │ - ldc2l 5, cr2, [fp, #884] @ 0x374 │ │ + ldc2l 6, cr2, [fp, #40] @ 0x28 │ │ ldc2l 14, cr1, [ip, #700] @ 0x2bc │ │ - ldc2l 9, cr6, [sl, #52] @ 0x34 @ │ │ + ldc2l 9, cr6, [sl, #142] @ 0x8e @ │ │ strteq r1, [sl], #-516 @ 0xfffffdfc │ │ strteq r1, [sl], #-808 @ 0xfffffcd8 │ │ - ldc2l 7, cr2, [fp, #132] @ 0x84 │ │ + ldc2l 7, cr2, [fp, #312] @ 0x138 │ │ eoreq r0, lr, r8, lsr r1 │ │ strteq r1, [sl], #-760 @ 0xfffffd08 │ │ strteq r1, [sl], #-744 @ 0xfffffd18 │ │ ldc2l 13, cr3, [sp, #740] @ 0x2e4 │ │ mlaeq lr, r0, r0, r0 │ │ strteq r1, [sl], #-1352 @ 0xfffffab8 │ │ strteq r1, [sl], #-1352 @ 0xfffffab8 │ │ strteq r1, [sl], #-1356 @ 0xfffffab4 │ │ strteq r1, [sl], #-1344 @ 0xfffffac0 │ │ strteq r2, [sl], #-424 @ 0xfffffe58 │ │ strteq r1, [sl], #-1316 @ 0xfffffadc │ │ - ldc2l 12, cr6, [sl, #616] @ 0x268 │ │ - ldc2l 12, cr12, [sl, #408] @ 0x198 │ │ + ldc2l 12, cr6, [sl, #796] @ 0x31c │ │ + ldc2l 12, cr12, [sl, #588] @ 0x24c │ │ ldc2l 1, cr2, [ip, #1004] @ 0x3ec │ │ strteq r1, [sl], #-1660 @ 0xfffff984 │ │ strteq r1, [sl], #-1640 @ 0xfffff998 │ │ strteq r1, [sl], #-1656 @ 0xfffff988 │ │ │ │ 024796ac : │ │ push {r4, sl, fp, lr} │ │ @@ -1361808,17 +1361808,17 @@ │ │ mov r0, r4 │ │ mov r2, #6 │ │ mov r3, #69 @ 0x45 │ │ add r1, pc, r1 │ │ bl 270f2f0 │ │ mov r0, #0 │ │ pop {r4, sl, fp, pc} │ │ - ldc2l 3, cr12, [sl, #92] @ 0x5c │ │ + ldc2l 3, cr12, [sl, #272] @ 0x110 │ │ ldc2l 14, cr0, [sp, #8] │ │ - ldc2l 2, cr6, [sl, #848] @ 0x350 │ │ + ldc2l 3, cr6, [sl, #4] │ │ │ │ 02479700 : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #24 │ │ mov r3, r0 │ │ mov r0, #0 │ │ @@ -1361986,16 +1361986,16 @@ │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ strteq r0, [sl], #-2496 @ 0xfffff640 │ │ strteq r0, [sl], #-2496 @ 0xfffff640 │ │ strteq r0, [sl], #-2500 @ 0xfffff63c │ │ strteq r0, [sl], #-2488 @ 0xfffff648 │ │ strteq r1, [sl], #-1568 @ 0xfffff9e0 │ │ strteq r0, [sl], #-2460 @ 0xfffff664 │ │ - ldc2l 1, cr6, [sl, #72] @ 0x48 │ │ - ldc2l 0, cr12, [sl, #696] @ 0x2b8 │ │ + ldc2l 1, cr6, [sl, #252] @ 0xfc │ │ + ldc2l 0, cr12, [sl, #876] @ 0x36c │ │ ldc2l 6, cr1, [ip, #268] @ 0x10c │ │ │ │ 02479990 : │ │ ldr r0, [pc, #44] @ 24799c4 │ │ mov r3, #0 │ │ ldr r1, [pc, #40] @ 24799c8 │ │ ldr r2, [pc, #40] @ 24799cc │ │ @@ -1362497,19 +1362497,19 @@ │ │ add r1, pc, r1 │ │ bl 270d930 │ │ mvn r0, #0 │ │ pop {r4, sl, fp, pc} │ │ mlaeq ip, r0, r3, r1 │ │ ldrdeq r1, [ip], -r4 @ │ │ eoreq r1, ip, r4, lsl #7 │ │ - ldc2l 3, cr7, [fp, #864] @ 0x360 │ │ + ldc2l 4, cr7, [fp, #20] │ │ eoreq r1, ip, r0, asr r3 │ │ eoreq r1, ip, r4, lsr r3 │ │ eoreq r1, ip, r0, lsl r3 │ │ - ldc2l 3, cr7, [fp, #768] @ 0x300 │ │ + ldc2l 3, cr7, [fp, #948] @ 0x3b4 │ │ │ │ 0247a164 : │ │ ldr r3, [pc, #20] @ 247a180 │ │ ldr r3, [pc, r3] │ │ ldr r3, [r3] │ │ cmp r3, #0 │ │ beq 247a17c │ │ @@ -1363152,111 +1363152,111 @@ │ │ mov r1, #6 │ │ bl 270ceb0 │ │ vmov r0, r1, d8 │ │ sub sp, fp, #80 @ 0x50 │ │ vpop {d8-d13} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 4, cr5, [fp, #192] @ 0xc0 │ │ + ldc2l 4, cr5, [fp, #372] @ 0x174 │ │ strteq r1, [sl], #-2508 @ 0xfffff634 │ │ strteq r1, [sl], #-2644 @ 0xfffff5ac │ │ strteq r1, [sl], #-2628 @ 0xfffff5bc │ │ strteq r1, [sl], #-2792 @ 0xfffff518 │ │ strteq r1, [sl], #-2692 @ 0xfffff57c │ │ - ldc2l 6, cr13, [sl, #24] │ │ + ldc2l 6, cr13, [sl, #204] @ 0xcc │ │ ldc2l 11, cr8, [ip, #648] @ 0x288 @ │ │ ldc2l 14, cr14, [fp, #696] @ 0x2b8 │ │ - ldc2l 13, cr10, [fp, #344] @ 0x158 │ │ + ldc2l 13, cr10, [fp, #524] @ 0x20c │ │ ldc2l 2, cr6, [sp, #1000] @ 0x3e8 │ │ strteq r1, [sl], #-2464 @ 0xfffff660 │ │ ldc2l 7, cr15, [r9, #136] @ 0x88 │ │ vcadd.f32 , , , #270 │ │ ldc2l 11, cr8, [ip, #56] @ 0x38 @ │ │ - ldc2l 2, cr3, [sl, #292] @ 0x124 │ │ + ldc2l 2, cr3, [sl, #472] @ 0x1d8 │ │ eoreq lr, sp, ip, lsr #28 │ │ eoreq lr, sp, r8, lsl lr │ │ eoreq lr, sp, r0, lsl #28 │ │ strteq r1, [sl], #-2164 @ 0xfffff78c │ │ strteq r1, [sl], #-2340 @ 0xfffff6dc │ │ - ldc2l 2, cr5, [fp, #400] @ 0x190 │ │ + ldc2l 2, cr5, [fp, #580] @ 0x244 │ │ eoreq lr, sp, r4, ror #26 │ │ - ldc2l 2, cr5, [fp, #256] @ 0x100 │ │ + ldc2l 2, cr5, [fp, #436] @ 0x1b4 │ │ strteq r1, [sl], #-2276 @ 0xfffff71c │ │ strteq r1, [sl], #-2008 @ 0xfffff828 │ │ ldc2l 1, cr4, [sp, #712] @ 0x2c8 │ │ eoreq lr, sp, r0, lsl #23 │ │ strteq r1, [sl], #-1836 @ 0xfffff8d4 │ │ ldc2l 12, cr8, [r9, #936] @ 0x3a8 │ │ strteq r1, [sl], #-1440 @ 0xfffffa60 │ │ ldc2l 7, cr2, [sp, #732] @ 0x2dc │ │ strteq r1, [sl], #-1540 @ 0xfffff9fc │ │ - ldc2l 1, cr1, [fp, #200] @ 0xc8 │ │ + ldc2l 1, cr1, [fp, #380] @ 0x17c │ │ strdeq lr, [sp], -r0 @ │ │ strteq r1, [sl], #-1356 @ 0xfffffab4 │ │ - ldc2l 15, cr4, [fp, #416] @ 0x1a0 │ │ + ldc2l 15, cr4, [fp, #596] @ 0x254 │ │ strteq r1, [sl], #-1296 @ 0xfffffaf0 │ │ eoreq lr, sp, r4, lsr sl │ │ - ldc2l 14, cr4, [fp, #800] @ 0x320 │ │ + ldc2l 14, cr4, [fp, #980] @ 0x3d4 │ │ eoreq lr, sp, ip, lsl #20 │ │ eoreq lr, sp, r4, asr #19 │ │ strteq r1, [sl], #-1124 @ 0xfffffb9c │ │ strteq r1, [sl], #-1224 @ 0xfffffb38 │ │ ldc2l 5, cr12, [ip, #460] @ 0x1cc │ │ - ldc2l 2, cr9, [sl, #524] @ 0x20c │ │ - ldc2l 0, cr15, [sl, #60] @ 0x3c │ │ - ldc2l 15, cr2, [sl, #560] @ 0x230 │ │ + ldc2l 2, cr9, [sl, #704] @ 0x2c0 │ │ + ldc2l 0, cr15, [sl, #240] @ 0xf0 │ │ + ldc2l 15, cr2, [sl, #740] @ 0x2e4 │ │ ldc2l 5, cr14, [ip, #380] @ 0x17c │ │ ldc2l 12, cr2, [ip, #32] │ │ eoreq lr, sp, r4, lsl #19 │ │ - ldc2l 6, cr8, [sl, #884] @ 0x374 │ │ + ldc2l 7, cr8, [sl, #40] @ 0x28 │ │ mlaeq sp, r0, r8, lr │ │ eoreq lr, sp, r8, ror #16 │ │ - ldc2l 6, cr8, [sl, #692] @ 0x2b4 │ │ + ldc2l 6, cr8, [sl, #872] @ 0x368 │ │ eoreq lr, sp, ip, lsr r8 │ │ - ldc2l 6, cr8, [sl, #516] @ 0x204 │ │ + ldc2l 6, cr8, [sl, #696] @ 0x2b8 │ │ eoreq lr, sp, r0, lsl r8 │ │ - ldc2l 6, cr8, [sl, #340] @ 0x154 │ │ + ldc2l 6, cr8, [sl, #520] @ 0x208 │ │ ldc2l 14, cr10, [r9, #4] │ │ - vcadd.f32 d22, d26, d8, #270 │ │ + ldc2l 8, cr6, [sl, #724] @ 0x2d4 │ │ ldc2l 2, cr13, [r9, #692] @ 0x2b4 │ │ - ldc2l 13, cr4, [fp, #80] @ 0x50 │ │ + ldc2l 13, cr4, [fp, #260] @ 0x104 │ │ strteq r1, [sl], #-568 @ 0xfffffdc8 │ │ eoreq lr, sp, r8, lsr #26 │ │ - ldc2l 3, cr1, [fp, #128] @ 0x80 │ │ + ldc2l 3, cr1, [fp, #308] @ 0x134 │ │ strteq r1, [sl], #-1856 @ 0xfffff8c0 │ │ ldc2l 5, cr15, [r9, #108] @ 0x6c │ │ - ldc2l 8, cr8, [sl, #228] @ 0xe4 │ │ + vcadd.f32 q12, q5, q11, #270 │ │ ldc2l 12, cr14, [fp, #944] @ 0x3b0 │ │ - ldc2l 15, cr4, [fp] │ │ + ldc2l 15, cr4, [fp, #180] @ 0xb4 │ │ strteq r1, [sl], #-2028 @ 0xfffff814 │ │ ldc2l 8, cr8, [ip, #1016] @ 0x3f8 │ │ strteq r1, [sl], #-1032 @ 0xfffffbf8 │ │ - ldc2l 10, cr10, [fp, #760] @ 0x2f8 @ │ │ + ldc2l 10, cr10, [fp, #940] @ 0x3ac @ │ │ strteq r1, [sl], #-896 @ 0xfffffc80 │ │ - ldc2l 2, cr13, [sl, #1000] @ 0x3e8 │ │ + ldc2l 3, cr13, [sl, #156] @ 0x9c │ │ ldc2l 8, cr8, [ip, #632] @ 0x278 │ │ ldc2l 6, cr15, [r9, #276] @ 0x114 │ │ strteq r1, [sl], #-1916 @ 0xfffff884 │ │ strteq r1, [sl], #-1708 @ 0xfffff954 │ │ strteq r1, [sl], #-664 @ 0xfffffd68 │ │ strteq r1, [sl], #-768 @ 0xfffffd00 │ │ strteq r1, [sl], #-596 @ 0xfffffdac │ │ strteq r1, [sl], #-516 @ 0xfffffdfc │ │ strteq r1, [sl], #-620 @ 0xfffffd94 │ │ strteq r1, [sl], #-448 @ 0xfffffe40 │ │ ldc2l 3, cr8, [ip, #616] @ 0x268 │ │ strteq r1, [sl], #-496 @ 0xfffffe10 │ │ - ldc2l 5, cr10, [fp, #376] @ 0x178 │ │ + ldc2l 5, cr10, [fp, #556] @ 0x22c │ │ strteq r1, [sl], #-448 @ 0xfffffe40 │ │ - ldc2l 13, cr12, [sl, #616] @ 0x268 │ │ + ldc2l 13, cr12, [sl, #796] @ 0x31c │ │ ldc2l 3, cr8, [ip, #248] @ 0xf8 │ │ ldc2l 0, cr15, [r9, #916] @ 0x394 │ │ strteq r1, [sl], #-348 @ 0xfffffea4 │ │ strteq r1, [sl], #-524 @ 0xfffffdf4 │ │ - ldc2l 10, cr4, [fp, #656] @ 0x290 @ │ │ + ldc2l 10, cr4, [fp, #836] @ 0x344 @ │ │ │ │ 0247ad00 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #44 @ 0x2c │ │ mov r7, r3 │ │ mov r4, r2 │ │ @@ -1363514,15 +1363514,15 @@ │ │ bl 270d9e0 │ │ add r8, r8, #1 │ │ add r9, r9, #1 │ │ ldr r7, [sp, #4] │ │ b 247aef8 │ │ ldc2l 6, cr4, [ip, #604] @ 0x25c │ │ ldc2l 3, cr2, [ip, #500] @ 0x1f4 │ │ - ldc2l 1, cr8, [sl, #324] @ 0x144 │ │ + ldc2l 1, cr8, [sl, #504] @ 0x1f8 │ │ ldc2l 4, cr5, [sp, #192] @ 0xc0 │ │ ldc2l 4, cr7, [r9, #288] @ 0x120 │ │ ldc2l 15, cr13, [fp, #540] @ 0x21c │ │ ldc2l 5, cr4, [ip, #124] @ 0x7c │ │ │ │ 0247b130 : │ │ push {fp, lr} │ │ @@ -1363804,27 +1363804,27 @@ │ │ ldr r0, [pc, #68] @ 247b5c4 │ │ mov r1, #4 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, r8 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 5, cr2, [fp, #68] @ 0x44 │ │ - ldc2l 5, cr0, [fp, #848] @ 0x350 │ │ + ldc2l 5, cr2, [fp, #248] @ 0xf8 │ │ + ldc2l 6, cr0, [fp, #4] │ │ ldc2l 6, cr13, [ip, #668] @ 0x29c │ │ ldc2l 1, cr0, [ip, #36] @ 0x24 │ │ - ldc2l 13, cr9, [fp, #760] @ 0x2f8 │ │ - ldc2l 2, cr6, [sl, #192] @ 0xc0 │ │ + ldc2l 13, cr9, [fp, #940] @ 0x3ac │ │ + ldc2l 2, cr6, [sl, #372] @ 0x174 │ │ ldc2l 4, cr9, [ip, #12] │ │ - ldc2l 7, cr10, [sl, #404] @ 0x194 │ │ + ldc2l 7, cr10, [sl, #584] @ 0x248 │ │ ldc2l 8, cr15, [ip, #368] @ 0x170 │ │ - ldc2l 5, cr12, [sl, #528] @ 0x210 │ │ + ldc2l 5, cr12, [sl, #708] @ 0x2c4 │ │ ldc2l 14, cr3, [ip, #36] @ 0x24 │ │ - ldc2l 0, cr4, [sl, #920] @ 0x398 │ │ - ldc2l 1, cr2, [fp, #100] @ 0x64 │ │ + ldc2l 1, cr4, [sl, #76] @ 0x4c │ │ + ldc2l 1, cr2, [fp, #280] @ 0x118 │ │ │ │ 0247b5c8 : │ │ ldr r1, [r1] │ │ mov r2, r0 │ │ mov r0, #0 │ │ cmp r1, #1 │ │ bge 247b5e8 │ │ @@ -1364046,19 +1364046,19 @@ │ │ ldr r0, [pc, #36] @ 247b934 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 9, cr11, [fp, #216] @ 0xd8 @ │ │ + ldc2l 9, cr11, [fp, #306] @ 0x132 @ │ │ ldc2l 5, cr7, [ip, #488] @ 0x1e8 │ │ - ldc2l 6, cr7, [sl, #404] @ 0x194 │ │ - ldc2l 11, cr9, [sl, #588] @ 0x24c @ │ │ - vcadd.f32 , , q2, #270 │ │ + ldc2l 6, cr7, [sl, #584] @ 0x248 │ │ + ldc2l 11, cr9, [sl, #768] @ 0x300 @ │ │ + ldc2l 8, cr11, [fp, #964] @ 0x3c4 │ │ │ │ 0247b938 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ mov r8, r0 │ │ ldr r0, [r0] │ │ cmp r0, #2 │ │ @@ -1364452,19 +1364452,19 @@ │ │ mov r1, r0 │ │ b 247bed4 │ │ mov r0, #0 │ │ sub sp, fp, #48 @ 0x30 │ │ vpop {d8-d9} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 10, cr11, [sl, #204] @ 0xcc @ │ │ - ldc2l 9, cr15, [sl, #158] @ 0x9e @ │ │ - ldc2l 1, cr9, [fp, #452] @ 0x1c4 │ │ - ldc2l 1, cr9, [fp, #116] @ 0x74 │ │ - ldc2l 9, cr11, [sl, #318] @ 0x13e @ │ │ + ldc2l 10, cr11, [sl, #384] @ 0x180 @ │ │ + ldc2l 9, cr15, [sl, #248] @ 0xf8 @ │ │ + ldc2l 1, cr9, [fp, #632] @ 0x278 │ │ + ldc2l 1, cr9, [fp, #296] @ 0x128 │ │ + ldc2l 9, cr11, [sl, #408] @ 0x198 @ │ │ │ │ 0247bf38 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ bl 270f0d0 │ │ vmov d16, r0, r1 │ │ @@ -1365131,18 +1365131,18 @@ │ │ add r0, pc, r0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, lr} │ │ b 270ce40 │ │ ldc2l 5, cr10, [ip, #872] @ 0x368 │ │ ldc2l 5, cr10, [ip, #536] @ 0x218 │ │ ldc2l 2, cr12, [ip, #812] @ 0x32c │ │ - ldc2l 6, cr6, [sl, #276] @ 0x114 │ │ - ldc2l 13, cr2, [fp, #284] @ 0x11c │ │ + ldc2l 6, cr6, [sl, #456] @ 0x1c8 │ │ + ldc2l 13, cr2, [fp, #464] @ 0x1d0 │ │ strhteq sp, [sl], -r4 │ │ - ldc2l 11, cr4, [fp, #64] @ 0x40 @ │ │ + ldc2l 11, cr4, [fp, #244] @ 0xf4 @ │ │ ldc2l 9, cr0, [ip, #66] @ 0x42 @ │ │ ldc2l 5, cr10, [ip, #104] @ 0x68 │ │ │ │ 0247c938 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r3 │ │ @@ -1365182,15 +1365182,15 @@ │ │ ldr r0, [pc, #28] @ 247c9ec │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ ldc2l 1, cr14, [ip, #600] @ 0x258 │ │ - ldc2l 13, cr0, [sl, #620] @ 0x26c │ │ + ldc2l 13, cr0, [sl, #800] @ 0x320 │ │ ldc2l 4, cr0, [ip, #164] @ 0xa4 │ │ ldc2l 1, cr14, [ip, #200] @ 0xc8 │ │ │ │ 0247c9f0 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ @@ -1365271,22 +1365271,22 @@ │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, r4 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ ldc2l 4, cr6, [ip, #200] @ 0xc8 │ │ ldc2l 2, cr0, [ip, #408] @ 0x198 │ │ - ldc2l 4, cr6, [sl, #260] @ 0x104 │ │ - ldc2l 9, cr8, [sl, #254] @ 0xfe @ │ │ + ldc2l 4, cr6, [sl, #440] @ 0x1b8 │ │ + ldc2l 9, cr8, [sl, #344] @ 0x158 @ │ │ ldc2l 3, cr8, [r9, #672] @ 0x2a0 │ │ - ldc2l 4, cr6, [sl, #20] │ │ + ldc2l 4, cr6, [sl, #200] @ 0xc8 │ │ ldc2l 15, cr11, [ip, #220] @ 0xdc │ │ ldc2l 3, cr6, [ip, #152] @ 0x98 │ │ ldc2l 13, cr12, [r9, #748] @ 0x2ec │ │ - ldc2l 4, cr6, [sl, #548] @ 0x224 │ │ + ldc2l 4, cr6, [sl, #728] @ 0x2d8 │ │ │ │ 0247cb60 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #16 │ │ ldr r4, [fp, #8] │ │ str r0, [sp, #8] │ │ @@ -1365337,20 +1365337,20 @@ │ │ add r0, pc, r0 │ │ bl 270ce70 │ │ mov r0, r5 │ │ bl 270ce40 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2l 9, cr4, [fp, #100] @ 0x64 @ │ │ + ldc2l 9, cr4, [fp, #190] @ 0xbe @ │ │ ldc2l 15, cr11, [ip, #636] @ 0x27c │ │ - ldc2l 3, cr6, [sl, #100] @ 0x64 │ │ - ldc2l 10, cr2, [fp, #108] @ 0x6c @ │ │ + ldc2l 3, cr6, [sl, #280] @ 0x118 │ │ + ldc2l 10, cr2, [fp, #288] @ 0x120 @ │ │ mlaeq sl, r4, ip, sp │ │ - ldc2l 7, cr4, [fp, #912] @ 0x390 │ │ + ldc2l 8, cr4, [fp, #68] @ 0x44 │ │ ldc2l 5, cr0, [ip, #980] @ 0x3d4 │ │ │ │ 0247cc5c : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r6, r2 │ │ mov r5, r1 │ │ @@ -1365560,22 +1365560,22 @@ │ │ add r3, r3, #16 │ │ ble 247cf70 │ │ str r1, [sp] │ │ mov r0, sp │ │ mov r1, r4 │ │ bl 270f1f0 │ │ b 247ce00 │ │ - ldc2l 9, cr0, [fp, #196] @ 0xc4 @ │ │ - ldc2l 12, cr6, [sl, #804] @ 0x324 │ │ + ldc2l 9, cr0, [fp, #286] @ 0x11e @ │ │ + ldc2l 12, cr6, [sl, #984] @ 0x3d8 │ │ ldc2l 3, cr2, [ip, #340] @ 0x154 │ │ ldc2l 7, cr13, [ip, #56] @ 0x38 │ │ eoreq ip, sp, r0, lsl #7 │ │ - ldc2l 8, cr2, [fp, #124] @ 0x7c │ │ - ldc2l 2, cr0, [sl, #600] @ 0x258 │ │ - ldc2l 8, cr0, [fp, #600] @ 0x258 │ │ + vcadd.f32 q9, , q6, #270 │ │ + ldc2l 2, cr0, [sl, #780] @ 0x30c │ │ + vcadd.f32 q8, , , #270 │ │ │ │ 0247cfcc : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r5, r0 │ │ bl 270ce80 │ │ @@ -1365654,22 +1365654,22 @@ │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, r4 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ ldc2l 3, cr0, [ip, #1012] @ 0x3f4 │ │ ldc2l 12, cr15, [fp, #552] @ 0x228 │ │ - ldc2l 14, cr5, [sl, #404] @ 0x194 │ │ - ldc2l 3, cr8, [sl, #652] @ 0x28c │ │ + ldc2l 14, cr5, [sl, #584] @ 0x248 │ │ + ldc2l 3, cr8, [sl, #832] @ 0x340 │ │ ldc2l 13, cr7, [r9, #816] @ 0x330 │ │ - ldc2l 14, cr5, [sl, #164] @ 0xa4 │ │ + ldc2l 14, cr5, [sl, #344] @ 0x158 │ │ ldc2l 9, cr11, [ip, #182] @ 0xb6 @ │ │ ldc2l 2, cr0, [ip, #964] @ 0x3c4 │ │ ldc2l 7, cr12, [r9, #892] @ 0x37c │ │ - ldc2l 14, cr5, [sl, #692] @ 0x2b4 │ │ + ldc2l 14, cr5, [sl, #872] @ 0x368 │ │ │ │ 0247d13c : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r5, r1 │ │ mov r4, r0 │ │ bl 270ce80 │ │ @@ -1365708,19 +1365708,19 @@ │ │ vstr d16, [r5, #40] @ 0x28 │ │ ldr r0, [pc, #32] @ 247d1fc │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, fp, pc} │ │ - ldc2l 3, cr4, [fp, #620] @ 0x26c │ │ - ldc2l 4, cr14, [sl, #632] @ 0x278 │ │ - ldc2l 13, cr5, [sl, #340] @ 0x154 │ │ + ldc2l 3, cr4, [fp, #800] @ 0x320 │ │ + ldc2l 4, cr14, [sl, #812] @ 0x32c │ │ + ldc2l 13, cr5, [sl, #520] @ 0x208 │ │ vcadd.f32 d27, d28, d15, #270 │ │ - ldc2l 3, cr4, [fp, #156] @ 0x9c │ │ + ldc2l 3, cr4, [fp, #336] @ 0x150 │ │ │ │ 0247d200 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #692 @ 0x2b4 │ │ mov r4, r3 │ │ mov r5, r1 │ │ @@ -1366163,64 +1366163,64 @@ │ │ ldr r2, [pc, #92] @ 247d948 │ │ mov r0, r4 │ │ mov r1, r5 │ │ mov r3, #98 @ 0x62 │ │ add r2, pc, r2 │ │ b 247d48c │ │ ldc2l 11, cr5, [r9, #336] @ 0x150 @ │ │ - ldc2l 6, cr8, [sl, #540] @ 0x21c │ │ - ldc2l 12, cr5, [fp, #416] @ 0x1a0 │ │ + ldc2l 6, cr8, [sl, #720] @ 0x2d0 │ │ + ldc2l 12, cr5, [fp, #596] @ 0x254 │ │ eoreq fp, sp, ip, asr #26 │ │ eoreq fp, sp, r4, ror sp │ │ eoreq fp, sp, ip, lsr lr │ │ eoreq fp, sp, r4, lsr lr │ │ ldc2l 10, cr5, [r9, #924] @ 0x39c @ │ │ eoreq fp, sp, r0, asr sp │ │ - ldc2l 5, cr8, [sl, #668] @ 0x29c │ │ - ldc2l 5, cr6, [sl, #992] @ 0x3e0 │ │ + ldc2l 5, cr8, [sl, #848] @ 0x350 │ │ + ldc2l 6, cr6, [sl, #148] @ 0x94 │ │ eoreq fp, sp, r4, asr #27 │ │ eoreq fp, sp, r4, lsl r9 │ │ strhteq fp, [sp], -r4 │ │ eoreq fp, sp, ip, lsr #19 │ │ ldc2l 12, cr12, [ip, #484] @ 0x1e4 │ │ strdeq fp, [sp], -r0 @ │ │ ldc2l 5, cr9, [r9, #508] @ 0x1fc │ │ ldrdeq fp, [sp], -ip @ │ │ - ldc2l 15, cr9, [sl, #504] @ 0x1f8 │ │ + ldc2l 15, cr9, [sl, #684] @ 0x2ac │ │ ldc2l 14, cr0, [sp, #632] @ 0x278 │ │ eoreq fp, sp, r0, lsr #24 │ │ eoreq fp, sp, r4, lsl #25 │ │ eoreq fp, sp, ip, ror ip │ │ ldc2l 8, cr11, [fp, #116] @ 0x74 │ │ strdeq fp, [sp], -ip @ │ │ vcadd.f32 , , , #270 │ │ ldc2l 13, cr15, [fp, #892] @ 0x37c │ │ - ldc2l 11, cr3, [sl, #16] @ │ │ + ldc2l 11, cr3, [sl, #196] @ 0xc4 @ │ │ strteq lr, [r9], #-1728 @ 0xfffff940 │ │ ldc2l 4, cr15, [ip, #112] @ 0x70 │ │ ldrdeq fp, [sp], -r0 @ │ │ - ldc2l 11, cr5, [fp, #352] @ 0x160 @ │ │ + ldc2l 11, cr5, [fp, #532] @ 0x214 @ │ │ eoreq fp, sp, r8, lsl #22 │ │ - ldc2l 10, cr5, [fp, #112] @ 0x70 @ │ │ + ldc2l 10, cr5, [fp, #292] @ 0x124 @ │ │ strdeq fp, [sp], -ip @ │ │ ldc2l 15, cr7, [r9, #324] @ 0x144 │ │ eoreq fp, sp, r8, lsr #21 │ │ - ldc2l 9, cr3, [sl, #304] @ 0x130 @ │ │ + ldc2l 9, cr3, [sl, #394] @ 0x18a @ │ │ strteq lr, [r9], #-1364 @ 0xfffffaac │ │ ldc2l 2, cr15, [ip, #704] @ 0x2c0 │ │ eoreq fp, sp, r4, ror #20 │ │ - ldc2l 9, cr5, [fp, #480] @ 0x1e0 @ │ │ + ldc2l 10, cr5, [fp, #116] @ 0x74 @ │ │ strhteq fp, [sp], -r0 │ │ eoreq fp, sp, r0, ror #19 │ │ eoreq fp, sp, r0, lsl #31 │ │ mlaeq sp, r4, pc, fp @ │ │ eoreq fp, sp, ip, lsl #31 │ │ ldc2l 12, cr5, [r9, #252] @ 0xfc │ │ eoreq fp, sp, ip, asr pc │ │ - ldc2l 7, cr6, [sl, #536] @ 0x218 │ │ + ldc2l 7, cr6, [sl, #716] @ 0x2cc │ │ │ │ 0247d9c8 : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #8 │ │ mov ip, r2 │ │ mov r2, r1 │ │ @@ -1366442,16 +1366442,16 @@ │ │ ldrdeq sp, [fp], -ip @ │ │ eoreq sp, fp, ip, asr #15 │ │ ldc2l 14, cr12, [ip, #596] @ 0x254 │ │ strdeq sp, [fp], -ip @ │ │ eoreq sp, fp, r4, ror #15 │ │ eoreq sp, fp, r8, lsr #15 │ │ mlaeq fp, r0, r7, sp │ │ - ldc2l 11, cr13, [r9, #988] @ 0x3dc @ │ │ - ldc2l 12, cr13, [r9, #44] @ 0x2c │ │ + ldc2l 12, cr13, [r9, #144] @ 0x90 │ │ + ldc2l 12, cr13, [r9, #224] @ 0xe0 │ │ │ │ 0247dd34 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d9} │ │ sub sp, sp, #24 │ │ @@ -1367605,54 +1367605,54 @@ │ │ eoreq sp, fp, r8, lsr #10 │ │ strdeq sp, [fp], -r0 @ │ │ ldrdeq sp, [fp], -r4 @ │ │ eoreq sp, fp, r4, lsr #8 │ │ eoreq sp, fp, r8, lsr #9 │ │ eoreq sp, fp, r8, ror #8 │ │ eoreq ip, fp, ip, ror r5 │ │ - ldc2l 11, cr6, [sl, #364] @ 0x16c @ │ │ + ldc2l 11, cr6, [sl, #544] @ 0x220 @ │ │ ldrdeq sp, [fp], -r8 @ │ │ eoreq sp, fp, ip, asr r2 │ │ eoreq sp, fp, ip, lsr r2 │ │ eoreq sp, fp, r0, lsl r4 │ │ eoreq ip, fp, ip, asr #30 │ │ ldrdeq ip, [fp], -r0 @ │ │ eoreq ip, fp, r8, asr #30 │ │ eoreq ip, fp, r0, lsr pc │ │ eoreq ip, fp, ip, ror lr │ │ eoreq ip, fp, r0, lsl #30 │ │ eoreq ip, fp, r0, lsl #27 │ │ - ldc2l 0, cr15, [sl, #228] @ 0xe4 │ │ - ldc2l 0, cr15, [sl, #148] @ 0x94 │ │ + ldc2l 0, cr15, [sl, #408] @ 0x198 │ │ + ldc2l 0, cr15, [sl, #328] @ 0x148 │ │ ldrdeq ip, [fp], -r0 @ │ │ - ldc2l 5, cr2, [fp, #888] @ 0x378 │ │ + ldc2l 6, cr2, [fp, #44] @ 0x2c │ │ eoreq ip, fp, r4, ror r8 │ │ ldc2l 2, cr8, [ip, #784] @ 0x310 │ │ ldc2l 2, cr8, [ip, #704] @ 0x2c0 │ │ eoreq ip, fp, r4, lsr lr │ │ strhteq ip, [fp], -r8 │ │ eoreq sp, fp, r8, ror #7 │ │ strdeq sp, [fp], -r0 @ │ │ eoreq sp, fp, ip, lsr r3 │ │ eoreq sp, fp, r0, asr #7 │ │ eoreq sp, fp, r0, lsr #7 │ │ eoreq sp, fp, r4, lsl #7 │ │ - ldc2l 6, cr11, [sl, #952] @ 0x3b8 │ │ + ldc2l 7, cr11, [sl, #108] @ 0x6c │ │ eoreq sp, fp, r4, ror r3 │ │ eoreq sp, fp, r4, ror #6 │ │ eoreq ip, fp, ip, asr #26 │ │ ldrdeq ip, [fp], -r0 @ │ │ - ldc2l 2, cr9, [sl, #148] @ 0x94 │ │ + ldc2l 2, cr9, [sl, #328] @ 0x148 │ │ strhteq ip, [fp], -r0 │ │ eoreq ip, fp, r4, lsr #26 │ │ eoreq ip, fp, r0, lsl #27 │ │ mlaeq fp, r0, r2, sp │ │ eoreq sp, fp, r4, lsl r3 │ │ eoreq sp, fp, ip, ror #5 │ │ - ldc2l 7, cr13, [r9, #380] @ 0x17c │ │ + ldc2l 7, cr13, [r9, #560] @ 0x230 │ │ ldrdeq sp, [fp], -r0 @ │ │ ldrdeq sp, [fp], -r0 @ │ │ ldc2l 5, cr7, [r9, #244] @ 0xf4 │ │ mlaeq fp, r8, r2, sp │ │ mlaeq fp, ip, r2, sp │ │ eoreq sp, fp, ip, lsl #5 │ │ eoreq sp, fp, r0, ror #4 │ │ @@ -1367721,15 +1367721,15 @@ │ │ eoreq ip, fp, r0, lsr #24 │ │ ldrdeq ip, [fp], -r4 @ │ │ eoreq ip, fp, r8, asr #23 │ │ eoreq ip, fp, r0, asr ip │ │ eoreq ip, fp, r0, lsr #24 │ │ eoreq ip, fp, ip, lsl #23 │ │ eoreq ip, fp, r4, lsl r5 │ │ - ldc2l 11, cr6, [sl, #60] @ 0x3c @ │ │ + ldc2l 11, cr6, [sl, #240] @ 0xf0 @ │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #76 @ 0x4c │ │ mov r6, r0 │ │ cmp r0, #0 │ │ beq 247f2ac │ │ str r1, [sp, #4] │ │ @@ -1368001,27 +1368001,27 @@ │ │ eoreq ip, fp, r8, lsr #3 │ │ eoreq ip, fp, ip, lsl r3 │ │ eoreq ip, fp, r8, ror #5 │ │ ldrdeq fp, [fp], -r8 @ │ │ ldc2l 9, cr7, [ip, #22] @ │ │ mlaeq fp, ip, r2, ip │ │ eoreq ip, fp, r0, asr r1 │ │ - ldc2l 5, cr10, [sl, #184] @ 0xb8 │ │ + ldc2l 5, cr10, [sl, #364] @ 0x16c │ │ eoreq ip, fp, r0, lsr r1 │ │ eoreq ip, fp, r0 │ │ - ldc2l 2, cr0, [fp, #104] @ 0x68 │ │ + ldc2l 2, cr0, [fp, #284] @ 0x11c │ │ strhteq fp, [fp], -ip │ │ eoreq ip, fp, r0, asr #32 │ │ - ldc2l 1, cr12, [sl, #504] @ 0x1f8 │ │ + ldc2l 1, cr12, [sl, #684] @ 0x2ac │ │ ldrdeq fp, [fp], -ip @ │ │ strhteq fp, [fp], -ip │ │ eoreq fp, fp, r4, lsl #31 │ │ eoreq fp, fp, r0, ror #30 │ │ mlaeq fp, r8, lr, fp │ │ - ldc2l 10, cr5, [fp, #568] @ 0x238 @ │ │ + ldc2l 10, cr5, [fp, #748] @ 0x2ec @ │ │ │ │ 0247f5b4 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ ldr r1, [pc, #352] @ 247f724 │ │ mov r4, r0 │ │ mov r0, #1 │ │ @@ -1368313,15 +1368313,15 @@ │ │ eoreq fp, fp, r8, asr #23 │ │ eoreq fp, fp, ip, lsl #22 │ │ strhteq fp, [fp], -r8 │ │ ldrdeq fp, [fp], -r0 @ │ │ eoreq fp, fp, r8, ror #21 │ │ strhteq fp, [fp], -r8 │ │ eoreq fp, fp, r4, lsr #21 │ │ - ldc2l 3, cr5, [fp, #104] @ 0x68 │ │ + ldc2l 3, cr5, [fp, #284] @ 0x11c │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ ldr r0, [pc, #104] @ 247fac4 │ │ ldr r0, [pc, r0] │ │ ldr r0, [r0] │ │ cmp r0, #0 │ │ beq 247fa88 │ │ @@ -1368656,15 +1368656,15 @@ │ │ bl 24802e4 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ ldmibls r9, {r1, r3, r4, r7, r8, fp, ip, pc} │ │ svccc 0x00b99999 │ │ eoreq fp, fp, ip, lsr #16 │ │ - ldc2l 11, cr3, [sl, #252] @ 0xfc @ │ │ + ldc2l 11, cr3, [sl, #432] @ 0x1b0 @ │ │ eoreq r7, fp, r0, ror lr │ │ eoreq fp, fp, r8, ror #8 │ │ strdeq fp, [fp], -r4 @ │ │ ldrdeq fp, [fp], -r4 @ │ │ strhteq fp, [fp], -r8 │ │ eoreq fp, fp, r4, ror r5 │ │ eoreq fp, fp, r0, asr #10 │ │ @@ -1368852,15 +1368852,15 @@ │ │ pop {r4, r5, fp, pc} │ │ eoreq fp, fp, r4, asr #8 │ │ strdeq fp, [fp], -r8 @ │ │ strdeq fp, [fp], -ip @ │ │ strdeq fp, [fp], -r8 @ │ │ eoreq fp, fp, r4, ror #5 │ │ eoreq fp, fp, r8, lsl #5 │ │ - ldc2l 8, cr15, [r9, #584] @ 0x248 │ │ + ldc2l 8, cr15, [r9, #764] @ 0x2fc │ │ eoreq fp, fp, r4, lsr #7 │ │ strhteq fp, [fp], -ip │ │ eoreq fp, fp, ip, lsl r2 │ │ vcadd.f32 q13, q14, , #270 │ │ eoreq fp, fp, r8, lsr #7 │ │ eoreq fp, fp, r0, lsl #4 │ │ ldrdeq fp, [fp], -r8 @ │ │ @@ -1369643,15 +1369643,15 @@ │ │ eoreq sl, fp, r4, ror #19 │ │ strhteq sl, [fp], -r4 │ │ ldc2l 0, cr10, [ip, #632] @ 0x278 │ │ eoreq sl, fp, r0, lsl r9 │ │ eoreq sl, fp, r4, ror #17 │ │ strhteq sl, [fp], -r8 │ │ mlaeq fp, r4, r8, sl │ │ - ldc2l 14, cr0, [sl, #184] @ 0xb8 │ │ + ldc2l 14, cr0, [sl, #364] @ 0x16c │ │ eoreq sl, fp, r4, asr r7 │ │ eoreq sl, fp, r4, lsr #14 │ │ eoreq sl, fp, r8, lsr #14 │ │ eoreq sl, fp, r0, lsr #13 │ │ eoreq sl, fp, r8, ror #13 │ │ eoreq sl, fp, r4, lsr r6 │ │ strdeq sl, [fp], -ip @ │ │ @@ -1371130,51 +1371130,51 @@ │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #80 @ 0x50 │ │ vpop {d8-d13} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 6, cr15, [sl, #784] @ 0x310 │ │ + ldc2l 6, cr15, [sl, #964] @ 0x3c4 │ │ ldc2l 4, cr7, [fp, #844] @ 0x34c │ │ - ldc2l 5, cr15, [sl, #988] @ 0x3dc │ │ + ldc2l 6, cr15, [sl, #144] @ 0x90 │ │ stc2l 2, cr7, [r5, #896]! @ 0x380 │ │ - ldc2l 9, cr5, [sl, #220] @ 0xdc @ │ │ - ldc2l 5, cr15, [sl, #652] @ 0x28c │ │ + ldc2l 9, cr5, [sl, #310] @ 0x136 @ │ │ + ldc2l 5, cr15, [sl, #832] @ 0x340 │ │ + ldc2l 5, cr15, [sl, #692] @ 0x2b4 │ │ + ldc2l 9, cr5, [sl, #150] @ 0x96 @ │ │ ldc2l 5, cr15, [sl, #512] @ 0x200 │ │ - ldc2l 9, cr5, [sl, #60] @ 0x3c @ │ │ - ldc2l 5, cr15, [sl, #332] @ 0x14c │ │ - ldc2l 8, cr5, [sl, #840] @ 0x348 │ │ - ldc2l 5, cr15, [sl, #28] │ │ + ldc2l 8, cr5, [sl, #1020] @ 0x3fc │ │ + ldc2l 5, cr15, [sl, #208] @ 0xd0 │ │ ldc2l 6, cr11, [fp, #944] @ 0x3b0 │ │ eoreq r7, sp, r4, lsl #11 │ │ ldc2l 14, cr14, [fp, #244] @ 0xf4 │ │ - ldc2l 7, cr15, [sl, #140] @ 0x8c │ │ + ldc2l 7, cr15, [sl, #320] @ 0x140 │ │ stc2l 4, cr7, [r5, #464]! @ 0x1d0 │ │ ldc2l 13, cr14, [fp, #1012] @ 0x3f4 │ │ - ldc2l 6, cr15, [sl, #908] @ 0x38c │ │ + ldc2l 7, cr15, [sl, #64] @ 0x40 │ │ ldc2l 11, cr14, [fp, #596] @ 0x254 @ │ │ - ldc2l 4, cr15, [sl, #492] @ 0x1ec │ │ + ldc2l 4, cr15, [sl, #672] @ 0x2a0 │ │ ldc2l 3, cr11, [fp, #320] @ 0x140 │ │ ldc2l 2, cr7, [fp, #764] @ 0x2fc │ │ - ldc2l 3, cr15, [sl, #908] @ 0x38c │ │ + ldc2l 4, cr15, [sl, #64] @ 0x40 │ │ stc2l 0, cr7, [r5, #800]! @ 0x320 │ │ - ldc2l 5, cr5, [sl, #888] @ 0x378 │ │ - ldc2l 2, cr15, [sl, #76] @ 0x4c │ │ + ldc2l 6, cr5, [sl, #44] @ 0x2c │ │ + ldc2l 2, cr15, [sl, #256] @ 0x100 │ │ ldc2l 1, cr11, [fp, #64] @ 0x40 │ │ - ldc2l 5, cr5, [sl, #568] @ 0x238 │ │ - ldc2l 1, cr15, [sl, #780] @ 0x30c │ │ - ldc2l 5, cr5, [sl, #296] @ 0x128 │ │ - ldc2l 1, cr15, [sl, #508] @ 0x1fc │ │ - ldc2l 5, cr5, [sl, #24] │ │ - ldc2l 1, cr15, [sl, #236] @ 0xec │ │ - ldc2l 4, cr5, [sl, #792] @ 0x318 │ │ - ldc2l 0, cr15, [sl, #1004] @ 0x3ec │ │ - ldc2l 4, cr5, [sl, #568] @ 0x238 │ │ - ldc2l 0, cr15, [sl, #780] @ 0x30c │ │ + ldc2l 5, cr5, [sl, #748] @ 0x2ec │ │ + ldc2l 1, cr15, [sl, #960] @ 0x3c0 │ │ + ldc2l 5, cr5, [sl, #476] @ 0x1dc │ │ + ldc2l 1, cr15, [sl, #688] @ 0x2b0 │ │ + ldc2l 5, cr5, [sl, #204] @ 0xcc │ │ + ldc2l 1, cr15, [sl, #416] @ 0x1a0 │ │ + ldc2l 4, cr5, [sl, #972] @ 0x3cc │ │ + ldc2l 1, cr15, [sl, #160] @ 0xa0 │ │ + ldc2l 4, cr5, [sl, #748] @ 0x2ec │ │ + ldc2l 0, cr15, [sl, #960] @ 0x3c0 │ │ │ │ 02482698 : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #16 │ │ mov ip, r2 │ │ mov r2, r1 │ │ @@ -1371564,21 +1371564,21 @@ │ │ bl 2702450 │ │ mov r4, r0 │ │ mov r5, r1 │ │ vneg.f64 d16, d10 │ │ vmov r0, r1, d9 │ │ b 2482c00 │ │ ldc2l 0, cr12, [ip, #284] @ 0x11c │ │ - vcadd.f32 q10, , , #270 │ │ - ldc2l 7, cr0, [sl, #388] @ 0x184 │ │ + ldc2l 8, cr4, [fp, #960] @ 0x3c0 │ │ + ldc2l 7, cr0, [sl, #568] @ 0x238 │ │ ldc2l 13, cr2, [r9, #960] @ 0x3c0 │ │ ldc2l 10, cr0, [r9, #924] @ 0x39c @ │ │ eoreq r6, sp, ip, asr #21 │ │ - ldc2l 9, cr4, [fp, #142] @ 0x8e @ │ │ - ldc2l 15, cr2, [sl, #344] @ 0x158 │ │ + ldc2l 9, cr4, [fp, #232] @ 0xe8 @ │ │ + ldc2l 15, cr2, [sl, #524] @ 0x20c │ │ ldc2l 15, cr11, [ip, #716] @ 0x2cc │ │ ldc2l 1, cr14, [fp, #788] @ 0x314 │ │ ldc2l 0, cr8, [ip, #704] @ 0x2c0 │ │ eoreq r6, sp, r0, ror r8 │ │ stc2l 7, cr6, [r5, #912]! @ 0x390 │ │ ldc2l 10, cr13, [ip, #868] @ 0x364 @ │ │ ldc2l 0, cr8, [ip, #304] @ 0x130 │ │ @@ -1371896,39 +1371896,39 @@ │ │ ldr r2, [pc, #104] @ 2483230 │ │ movw r3, #379 @ 0x17b │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ b 24830a4 │ │ ldc2l 13, cr4, [r9, #628] @ 0x274 │ │ - ldc2l 10, cr4, [sl, #820] @ 0x334 @ │ │ - ldc2l 0, cr0, [sl, #852] @ 0x354 │ │ + ldc2l 10, cr4, [sl, #1000] @ 0x3e8 @ │ │ + ldc2l 1, cr0, [sl, #8] │ │ ldc2l 5, cr6, [fp, #740] @ 0x2e4 │ │ ldc2l 13, cr4, [r9, #340] @ 0x154 │ │ - ldc2l 3, cr4, [fp, #620] @ 0x26c │ │ - ldc2l 0, cr0, [sl, #564] @ 0x234 │ │ + ldc2l 3, cr4, [fp, #800] @ 0x320 │ │ + ldc2l 0, cr0, [sl, #744] @ 0x2e8 │ │ ldc2l 12, cr7, [ip, #636] @ 0x27c │ │ ldc2l 13, cr4, [r9, #68] @ 0x44 │ │ ldc2l 13, cr4, [r9, #32] │ │ - ldc2l 0, cr0, [sl, #292] @ 0x124 │ │ - ldc2l 10, cr8, [r9, #228] @ 0xe4 @ │ │ - ldc2l 8, cr8, [r9, #220] @ 0xdc │ │ + ldc2l 0, cr0, [sl, #472] @ 0x1d8 │ │ + ldc2l 10, cr8, [r9, #408] @ 0x198 @ │ │ + vcadd.f32 q12, , q10, #270 │ │ ldc2l 2, cr12, [fp, #976] @ 0x3d0 │ │ ldc2l 6, cr11, [ip, #564] @ 0x234 │ │ - ldc2l 7, cr8, [r9, #924] @ 0x39c │ │ + ldc2l 8, cr8, [r9, #80] @ 0x50 │ │ ldc2l 2, cr12, [fp, #656] @ 0x290 │ │ - ldc2l 7, cr8, [r9, #732] @ 0x2dc │ │ + ldc2l 7, cr8, [r9, #912] @ 0x390 │ │ ldc2l 2, cr12, [fp, #464] @ 0x1d0 │ │ ldc2l 6, cr11, [ip, #36] @ 0x24 │ │ ldc2l 2, cr12, [fp, #272] @ 0x110 │ │ ldc2l 5, cr11, [ip, #836] @ 0x344 │ │ ldc2l 2, cr12, [fp, #48] @ 0x30 │ │ ldc2l 14, cr4, [r9, #20] │ │ ldc2l 0, cr0, [ip, #640] @ 0x280 │ │ - ldc2l 1, cr0, [sl, #244] @ 0xf4 │ │ + ldc2l 1, cr0, [sl, #424] @ 0x1a8 │ │ ldc2l 6, cr6, [fp, #68] @ 0x44 │ │ ldc2l 12, cr4, [r9, #820] @ 0x334 │ │ │ │ 02483248 : │ │ vldr d16, [r0] │ │ vstr d16, [r1] │ │ vldr d16, [r0, #32] │ │ @@ -1373343,15 +1373343,15 @@ │ │ ldrteq r0, [r9], #-456 @ 0xfffffe38 │ │ strbeq r3, [r1], #-3276 @ 0xfffff334 │ │ ldrteq sl, [r6], #-2056 @ 0xfffff7f8 │ │ ldrteq r8, [r8], #-2472 @ 0xfffff658 │ │ strteq r8, [r9], #-1136 @ 0xfffffb90 │ │ strteq r8, [r9], #-1112 @ 0xfffffba8 │ │ ldc2l 10, cr7, [fp, #708] @ 0x2c4 @ │ │ - ldc2l 14, cr7, [sl, #296] @ 0x128 │ │ + ldc2l 14, cr7, [sl, #476] @ 0x1dc │ │ ldrteq sl, [r5], #-708 @ 0xfffffd3c │ │ strteq r8, [r9], #-1052 @ 0xfffffbe4 │ │ ldrteq fp, [r5], #-4 │ │ strteq pc, [fp], #-2092 @ 0xfffff7d4 │ │ strteq r0, [sl], #-2372 @ 0xfffff6bc │ │ strteq r8, [r9], #-1004 @ 0xfffffc14 │ │ strteq r8, [r9], #-984 @ 0xfffffc28 │ │ @@ -1373438,19 +1373438,19 @@ │ │ bls 2484d80 │ │ ldr r0, [pc, #2180] @ 2485238 │ │ movw r3, #1619 @ 0x653 │ │ ldr r2, [pc, #2176] @ 248523c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ b 2484d78 │ │ - ldc2l 15, cr13, [r9, #992] @ 0x3e0 │ │ + ldc2l 0, cr14, [r9, #148] @ 0x94 │ │ ldr r0, [pc, #1956] @ 2485174 │ │ add r0, pc, r0 │ │ b 2484ff4 │ │ - ldc2l 13, cr7, [sl, #808] @ 0x328 │ │ + ldc2l 13, cr7, [sl, #988] @ 0x3dc │ │ strteq r1, [sl], #-1604 @ 0xfffff9bc │ │ ldc2l 1, cr4, [r9, #996] @ 0x3e4 │ │ strteq r8, [r9], #-872 @ 0xfffffc98 │ │ ldc2l 12, cr1, [r9, #984] @ 0x3d8 │ │ strbeq r5, [fp], #-2116 @ 0xfffff7bc │ │ ldrteq r0, [r9], #-148 @ 0xffffff6c │ │ strteq r8, [r9], #-824 @ 0xfffffcc8 │ │ @@ -1373905,31 +1373905,31 @@ │ │ strbeq r6, [sl], #-860 @ 0xfffffca4 │ │ strbeq r3, [r1], #-3608 @ 0xfffff1e8 │ │ strbeq r2, [r2], #-2116 @ 0xfffff7bc │ │ ldrteq pc, [r8], #-1428 @ 0xfffffa6c @ │ │ strteq r7, [r9], #-2152 @ 0xfffff798 │ │ strteq r7, [r9], #-2132 @ 0xfffff7ac │ │ ldc2l 9, cr14, [fp, #330] @ 0x14a @ │ │ - ldc2l 2, cr7, [sl, #280] @ 0x118 │ │ + ldc2l 2, cr7, [sl, #460] @ 0x1cc │ │ ldrteq sl, [r6], #-2320 @ 0xfffff6f0 │ │ - ldc2l 12, cr2, [fp, #728] @ 0x2d8 │ │ - ldc2l 2, cr7, [sl, #56] @ 0x38 │ │ + ldc2l 12, cr2, [fp, #908] @ 0x38c │ │ + ldc2l 2, cr7, [sl, #236] @ 0xec │ │ strteq r1, [sl], #-2012 @ 0xfffff824 │ │ ldc2l 9, cr14, [fp, #128] @ 0x80 @ │ │ strbeq r2, [r1], #-4052 @ 0xfffff02c │ │ ldrteq r9, [r6], #-2832 @ 0xfffff4f0 │ │ ldrteq r7, [r8], #-3244 @ 0xfffff354 │ │ ldrteq pc, [r8], #-1180 @ 0xfffffb64 @ │ │ strteq r7, [r9], #-1904 @ 0xfffff890 │ │ strteq r7, [r9], #-1884 @ 0xfffff8a4 │ │ ldc2l 13, cr6, [fp, #724] @ 0x2d4 │ │ - ldc2l 1, cr7, [sl, #312] @ 0x138 │ │ + ldc2l 1, cr7, [sl, #492] @ 0x1ec │ │ ldrteq r9, [r5], #-1484 @ 0xfffffa34 │ │ - ldc2l 2, cr3, [sl, #600] @ 0x258 │ │ - ldc2l 1, cr7, [sl, #104] @ 0x68 │ │ + ldc2l 2, cr3, [sl, #780] @ 0x30c │ │ + ldc2l 1, cr7, [sl, #284] @ 0x11c │ │ strteq r7, [r9], #-1784 @ 0xfffff908 │ │ strbeq r6, [sl], #-1468 @ 0xfffffa44 │ │ strbeq r4, [fp], #-4056 @ 0xfffff028 │ │ eoreq r5, sp, r8, lsl #1 │ │ strteq r8, [r9], #-2084 @ 0xfffff7dc │ │ strteq lr, [ip], #-1656 @ 0xfffff988 │ │ strteq r7, [r9], #-2756 @ 0xfffff53c │ │ @@ -1373953,100 +1373953,100 @@ │ │ strteq r7, [r9], #-1632 @ 0xfffff9a0 │ │ ldrteq r9, [r7], #-356 @ 0xfffffe9c │ │ ldrteq sl, [r5], #-4000 @ 0xfffff060 │ │ strteq r0, [fp], #-92 @ 0xffffffa4 │ │ strteq r7, [r9], #-1600 @ 0xfffff9c0 │ │ strteq r7, [r9], #-1580 @ 0xfffff9d4 │ │ ldc2l 11, cr14, [r8, #640] @ 0x280 @ │ │ - ldc2l 0, cr7, [sl, #120] @ 0x78 │ │ + ldc2l 0, cr7, [sl, #300] @ 0x12c │ │ strteq pc, [fp], #-1936 @ 0xfffff870 │ │ - ldc2l 14, cr8, [sl, #1008] @ 0x3f0 │ │ - ldc2l 15, cr6, [sl, #920] @ 0x398 │ │ + ldc2l 15, cr8, [sl, #164] @ 0xa4 │ │ + ldc2l 0, cr7, [sl, #76] @ 0x4c │ │ strteq r5, [sp], #-2396 @ 0xfffff6a4 │ │ ldc2l 12, cr6, [fp, #128] @ 0x80 │ │ ldrteq sl, [r5], #-276 @ 0xfffffeec │ │ strteq lr, [fp], #-2364 @ 0xfffff6c4 │ │ strteq pc, [r9], #-2648 @ 0xfffff5a8 │ │ strteq r7, [r9], #-1280 @ 0xfffffb00 │ │ strteq r7, [r9], #-1260 @ 0xfffffb14 │ │ strteq r7, [r9], #-1232 @ 0xfffffb30 │ │ - ldc2l 0, cr13, [r9, #1008] @ 0x3f0 │ │ - ldc2l 14, cr6, [sl, #824] @ 0x338 │ │ + ldc2l 1, cr13, [r9, #164] @ 0xa4 │ │ + ldc2l 14, cr6, [sl, #1004] @ 0x3ec │ │ strteq r0, [sl], #-1864 @ 0xfffff8b8 │ │ ldc2l 12, cr11, [ip, #656] @ 0x290 │ │ - ldc2l 14, cr6, [sl, #600] @ 0x258 │ │ + ldc2l 14, cr6, [sl, #780] @ 0x30c │ │ strbeq r5, [sl], #-3888 @ 0xfffff0d0 │ │ strbeq r3, [r1], #-2540 @ 0xfffff614 │ │ strbeq r2, [r2], #-1048 @ 0xfffffbe8 │ │ strteq lr, [ip], #-0 │ │ strteq r7, [r9], #-1084 @ 0xfffffbc4 │ │ strteq r7, [r9], #-1064 @ 0xfffffbd8 │ │ strteq r7, [r9], #-1044 @ 0xfffffbec │ │ - ldc2l 0, cr13, [r9, #256] @ 0x100 │ │ - ldc2l 14, cr6, [sl, #72] @ 0x48 │ │ - ldc2l 0, cr15, [r9, #920] @ 0x398 │ │ - ldc2l 13, cr6, [sl, #920] @ 0x398 │ │ - ldc2l 12, cr12, [r9, #576] @ 0x240 │ │ - ldc2l 10, cr6, [sl, #392] @ 0x188 @ │ │ + ldc2l 0, cr13, [r9, #436] @ 0x1b4 │ │ + ldc2l 14, cr6, [sl, #252] @ 0xfc │ │ + ldc2l 1, cr15, [r9, #76] @ 0x4c │ │ + ldc2l 14, cr6, [sl, #76] @ 0x4c │ │ + ldc2l 12, cr12, [r9, #756] @ 0x2f4 │ │ + ldc2l 10, cr6, [sl, #572] @ 0x23c @ │ │ strteq r0, [sl], #-732 @ 0xfffffd24 │ │ - ldc2l 13, cr14, [r9, #184] @ 0xb8 │ │ - ldc2l 10, cr6, [sl, #184] @ 0xb8 @ │ │ + ldc2l 13, cr14, [r9, #364] @ 0x16c │ │ + ldc2l 10, cr6, [sl, #364] @ 0x16c @ │ │ strteq r7, [r9], #-3412 @ 0xfffff2ac │ │ ldc2l 6, cr6, [fp, #384] @ 0x180 │ │ - ldc2l 6, cr15, [r9, #836] @ 0x344 │ │ - ldc2l 11, cr14, [r9, #100] @ 0x64 @ │ │ + ldc2l 6, cr15, [r9, #1016] @ 0x3f8 │ │ + ldc2l 11, cr14, [r9, #280] @ 0x118 @ │ │ strteq r7, [r9], #-2456 @ 0xfffff668 │ │ ldc2l 3, cr1, [r9, #204] @ 0xcc │ │ ldc2l 14, cr14, [r8, #572] @ 0x23c │ │ strteq r7, [r9], #-904 @ 0xfffffc78 │ │ strteq r7, [r9], #-852 @ 0xfffffcac │ │ - ldc2l 0, cr15, [r9, #408] @ 0x198 │ │ - ldc2l 13, cr6, [sl, #408] @ 0x198 │ │ + ldc2l 0, cr15, [r9, #588] @ 0x24c │ │ + ldc2l 13, cr6, [sl, #588] @ 0x24c │ │ strteq r8, [r9], #-140 @ 0xffffff74 │ │ ldc2l 8, cr14, [r8, #748] @ 0x2ec │ │ strteq r7, [r9], #-728 @ 0xfffffd28 │ │ ldrteq r9, [r5], #-3788 @ 0xfffff134 │ │ strteq sp, [ip], #-3696 @ 0xfffff190 │ │ strteq r7, [r9], #-700 @ 0xfffffd44 │ │ - ldc2l 12, cr6, [sl, #808] @ 0x328 │ │ - ldc2l 14, cr14, [r9, #1016] @ 0x3f8 │ │ + ldc2l 12, cr6, [sl, #988] @ 0x3dc │ │ + ldc2l 15, cr14, [r9, #172] @ 0xac │ │ strteq r7, [r9], #-468 @ 0xfffffe2c │ │ - ldc2l 14, cr14, [r9, #840] @ 0x348 │ │ + ldc2l 14, cr14, [r9, #1020] @ 0x3fc │ │ strteq r7, [r9], #-3836 @ 0xfffff104 │ │ strteq r7, [r9], #-388 @ 0xfffffe7c │ │ ldc2l 9, cr11, [ip, #280] @ 0x118 @ │ │ strteq r7, [r9], #-340 @ 0xfffffeac │ │ ldc2l 9, cr11, [ip, #192] @ 0xc0 @ │ │ strteq r7, [r9], #-268 @ 0xfffffef4 │ │ - ldc2l 12, cr2, [sl, #536] @ 0x218 │ │ + ldc2l 12, cr2, [sl, #716] @ 0x2cc │ │ strteq r7, [r9], #-224 @ 0xffffff20 │ │ - ldc2l 12, cr2, [sl, #344] @ 0x158 │ │ + ldc2l 12, cr2, [sl, #524] @ 0x20c │ │ strteq r7, [r9], #-176 @ 0xffffff50 │ │ strteq r7, [r9], #-524 @ 0xfffffdf4 │ │ ldrteq r9, [r5], #-2836 @ 0xfffff4ec │ │ strbeq r2, [r1], #-1872 @ 0xfffff8b0 │ │ ldrteq r9, [r6], #-656 @ 0xfffffd70 │ │ ldrteq sl, [r5], #-1356 @ 0xfffffab4 │ │ - ldc2l 4, cr3, [sl, #852] @ 0x354 │ │ - ldc2l 10, cr14, [r9, #628] @ 0x274 @ │ │ + ldc2l 5, cr3, [sl, #8] │ │ + ldc2l 10, cr14, [r9, #808] @ 0x328 @ │ │ ldrteq sl, [r5], #-1288 @ 0xfffffaf8 │ │ vcadd.f32 d20, d28, d30, #270 │ │ ldrteq r9, [r5], #-3216 @ 0xfffff370 │ │ strteq r6, [r9], #-3816 @ 0xfffff118 │ │ - ldc2l 11, cr14, [r9, #968] @ 0x3c8 @ │ │ - ldc2l 8, cr6, [sl, #968] @ 0x3c8 │ │ + ldc2l 12, cr14, [r9, #124] @ 0x7c │ │ + ldc2l 9, cr6, [sl, #62] @ 0x3e @ │ │ strteq r7, [r9], #-3096 @ 0xfffff3e8 │ │ ldrteq r9, [r5], #-2724 @ 0xfffff55c │ │ ldc2l 6, cr11, [ip, #688] @ 0x2b0 │ │ - ldc2l 8, cr6, [sl, #632] @ 0x278 │ │ + vcadd.f32 q11, q13, , #270 │ │ ldrteq lr, [r8], #-2952 @ 0xfffff478 │ │ strteq sp, [ip], #-2584 @ 0xfffff5e8 │ │ ldrteq r9, [r5], #-2628 @ 0xfffff5bc │ │ - ldc2l 9, cr2, [sl, #380] @ 0x17c @ │ │ - vcadd.f32 q11, q5, q1, #270 │ │ + ldc2l 9, cr2, [sl, #470] @ 0x1d6 @ │ │ + vcadd.f32 q11, q5, , #270 │ │ strteq r6, [r9], #-3608 @ 0xfffff1e8 │ │ strteq pc, [r9], #-856 @ 0xfffffca8 │ │ strteq lr, [fp], #-560 @ 0xfffffdd0 │ │ ldrteq r9, [r5], #-2552 @ 0xfffff608 │ │ ldrteq r8, [r5], #-3212 @ 0xfffff374 │ │ strteq r0, [sl], #-144 @ 0xffffff70 │ │ eoreq r4, sp, r4, lsl #7 │ │ @@ -1374454,37 +1374454,37 @@ │ │ add r0, pc, r0 │ │ b 2485740 │ │ ldc2l 7, cr4, [r9, #92] @ 0x5c │ │ strdeq r3, [sp], -r4 @ │ │ eoreq r3, sp, r0, lsl lr │ │ eoreq r3, sp, ip, lsl #28 │ │ eoreq r3, sp, r4, lsl #27 │ │ - ldc2l 0, cr6, [sl, #784] @ 0x310 │ │ - ldc2l 7, cr13, [r9, #996] @ 0x3e4 │ │ + ldc2l 0, cr6, [sl, #964] @ 0x3c4 │ │ + vcadd.f32 d29, d9, d22, #270 │ │ ldc2l 7, cr1, [ip, #32] │ │ eoreq r3, sp, r0, asr sp │ │ eoreq r3, sp, r0, lsl #26 │ │ ldc2l 5, cr4, [r9, #960] @ 0x3c0 │ │ - ldc2l 13, cr11, [r9, #852] @ 0x354 │ │ - ldc2l 12, cr5, [sl, #624] @ 0x270 │ │ - ldc2l 12, cr11, [sl, #496] @ 0x1f0 │ │ + ldc2l 14, cr11, [r9, #8] │ │ + ldc2l 12, cr5, [sl, #804] @ 0x324 │ │ + ldc2l 12, cr11, [sl, #676] @ 0x2a4 │ │ eoreq r3, sp, r4, asr #25 │ │ ldc2l 7, cr7, [ip, #256] @ 0x100 │ │ - ldc2l 15, cr5, [sl, #976] @ 0x3d0 │ │ - ldc2l 6, cr13, [r9, #436] @ 0x1b4 │ │ + ldc2l 0, cr6, [sl, #132] @ 0x84 │ │ + ldc2l 6, cr13, [r9, #616] @ 0x268 │ │ ldc2l 5, cr1, [ip, #632] @ 0x278 │ │ ldc2l 9, cr11, [fp, #356] @ 0x164 @ │ │ ldc2l 6, cr7, [ip, #16] │ │ ldc2l 9, cr11, [fp, #36] @ 0x24 @ │ │ ldc2l 5, cr1, [r9, #1004] @ 0x3ec │ │ - ldc2l 1, cr14, [r9, #516] @ 0x204 │ │ - ldc2l 5, cr13, [r9, #804] @ 0x324 │ │ + ldc2l 1, cr14, [r9, #696] @ 0x2b8 │ │ + ldc2l 5, cr13, [r9, #984] @ 0x3d8 │ │ ldc2l 13, cr15, [r8, #924] @ 0x39c │ │ ldc2l 6, cr7, [ip, #544] @ 0x220 │ │ - ldc2l 13, cr11, [sl, #396] @ 0x18c │ │ + ldc2l 13, cr11, [sl, #576] @ 0x240 │ │ mlaeq sp, r8, fp, r3 │ │ ldc2l 5, cr4, [r9, #140] @ 0x8c │ │ │ │ 024859c8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #36 @ 0x24 │ │ @@ -1374637,25 +1374637,25 @@ │ │ bl 270db00 │ │ ldr r0, [pc, #60] @ 2485c64 │ │ mov r1, #11 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ mov r0, r5 │ │ b 2485a50 │ │ - ldc2l 6, cr15, [sl, #4] │ │ + ldc2l 6, cr15, [sl, #184] @ 0xb8 │ │ ldc2l 3, cr3, [ip, #300] @ 0x12c │ │ - ldc2l 4, cr13, [r9, #900] @ 0x384 │ │ + ldc2l 5, cr13, [r9, #56] @ 0x38 │ │ ldc2l 0, cr15, [fp, #984] @ 0x3d8 │ │ - ldc2l 4, cr15, [sl, #756] @ 0x2f4 │ │ + ldc2l 4, cr15, [sl, #936] @ 0x3a8 │ │ ldc2l 5, cr11, [fp, #992] @ 0x3e0 │ │ - ldc2l 3, cr13, [r9, #612] @ 0x264 │ │ + ldc2l 3, cr13, [r9, #792] @ 0x318 │ │ ldc2l 0, cr2, [r9, #568] @ 0x238 │ │ - ldc2l 4, cr15, [sl, #36] @ 0x24 │ │ + ldc2l 4, cr15, [sl, #216] @ 0xd8 │ │ ldc2l 1, cr4, [r9, #236] @ 0xec │ │ - ldc2l 2, cr13, [r9, #932] @ 0x3a4 │ │ + ldc2l 3, cr13, [r9, #88] @ 0x58 │ │ ldc2l 2, cr1, [ip, #268] @ 0x10c │ │ │ │ 02485c68 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #604 @ 0x25c │ │ sub sp, sp, #5120 @ 0x1400 │ │ @@ -1375067,65 +1375067,65 @@ │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 10, cr4, [ip, #744] @ 0x2e8 @ │ │ ldc2l 4, cr4, [ip, #232] @ 0xe8 │ │ - ldc2l 10, cr9, [r9, #908] @ 0x38c @ │ │ + ldc2l 11, cr9, [r9, #64] @ 0x40 @ │ │ strbeq r3, [fp], #-840 @ 0xfffffcb8 │ │ strbeq r3, [fp], #-800 @ 0xfffffce0 │ │ strbeq r3, [fp], #-3564 @ 0xfffff214 │ │ strbeq r9, [fp], #-3868 @ 0xfffff0e4 │ │ ldc2l 14, cr0, [r9, #764] @ 0x2fc │ │ eoreq r3, sp, r0, lsl #8 │ │ strbeq r3, [fp], #-644 @ 0xfffffd7c │ │ - ldc2l 15, cr14, [sl, #920] @ 0x398 │ │ - ldc2l 14, cr12, [r9, #836] @ 0x344 │ │ + ldc2l 0, cr15, [sl, #76] @ 0x4c │ │ + ldc2l 14, cr12, [r9, #1016] @ 0x3f8 │ │ eoreq r3, sp, r0, ror #6 │ │ ldc2l 0, cr9, [fp, #540] @ 0x21c │ │ - ldc2l 9, cr9, [r9, #342] @ 0x156 @ │ │ + ldc2l 9, cr9, [r9, #432] @ 0x1b0 @ │ │ strbeq r3, [fp], #-2792 @ 0xfffff518 │ │ eoreq r3, sp, r4, lsr #2 │ │ strbeq r9, [fp], #-3080 @ 0xfffff3f8 │ │ strbeq r2, [fp], #-4048 @ 0xfffff030 │ │ - ldc2l 7, cr9, [r9, #284] @ 0x11c │ │ - ldc2l 3, cr15, [sl, #868] @ 0x364 │ │ + ldc2l 7, cr9, [r9, #464] @ 0x1d0 │ │ + ldc2l 4, cr15, [sl, #24] │ │ eoreq r3, sp, r8, lsr #13 │ │ eoreq r3, sp, ip, ror r6 │ │ - ldc2l 9, cr9, [sl, #26] @ │ │ + ldc2l 9, cr9, [sl, #116] @ 0x74 @ │ │ strbeq r3, [fp], #-1308 @ 0xfffffae4 │ │ strbeq r3, [fp], #-4072 @ 0xfffff018 │ │ - ldc2l 9, cr7, [sl, #110] @ 0x6e @ │ │ + ldc2l 9, cr7, [sl, #200] @ 0xc8 @ │ │ ldc2l 13, cr14, [fp, #648] @ 0x288 │ │ ldrdeq r3, [sp], -r0 @ │ │ strbeq r3, [fp], #-1212 @ 0xfffffb44 │ │ ldc2l 0, cr1, [r9, #412] @ 0x19c │ │ - ldc2l 11, cr5, [sl, #508] @ 0x1fc @ │ │ + ldc2l 11, cr5, [sl, #688] @ 0x2b0 @ │ │ ldc2l 15, cr2, [ip, #904] @ 0x388 │ │ - ldc2l 4, cr13, [sl, #728] @ 0x2d8 │ │ + ldc2l 4, cr13, [sl, #908] @ 0x38c │ │ strbeq r3, [fp], #-964 @ 0xfffffc3c │ │ ldc2l 5, cr7, [fp, #348] @ 0x15c │ │ - ldc2l 10, cr15, [r9, #988] @ 0x3dc @ │ │ + ldc2l 11, cr15, [r9, #144] @ 0x90 @ │ │ strbeq r3, [fp], #-3872 @ 0xfffff0e0 │ │ eoreq r3, sp, r8, asr #10 │ │ ldc2l 3, cr5, [fp, #404] @ 0x194 │ │ ldc2l 10, cr14, [fp, #472] @ 0x1d8 @ │ │ eoreq r3, sp, r4, lsr #5 │ │ strbeq r3, [fp], #-3164 @ 0xfffff3a4 │ │ ldc2l 13, cr0, [r9, #220] @ 0xdc │ │ - ldc2l 15, cr14, [sl, #376] @ 0x178 │ │ + ldc2l 15, cr14, [sl, #556] @ 0x22c │ │ ldc2l 12, cr2, [ip, #712] @ 0x2c8 │ │ - ldc2l 1, cr13, [sl, #424] @ 0x1a8 │ │ + ldc2l 1, cr13, [sl, #604] @ 0x25c │ │ strbeq r3, [fp], #-120 @ 0xffffff88 │ │ - ldc2l 7, cr15, [r9, #796] @ 0x31c │ │ + ldc2l 7, cr15, [r9, #976] @ 0x3d0 │ │ ldc2l 2, cr7, [fp, #844] @ 0x34c │ │ strbeq r3, [fp], #-3028 @ 0xfffff42c │ │ strdeq r3, [sp], -ip @ │ │ - ldc2l 14, cr14, [sl, #228] @ 0xe4 │ │ + ldc2l 14, cr14, [sl, #408] @ 0x198 │ │ │ │ 024863b4 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ beq 24863d0 │ │ @@ -1375493,27 +1375493,27 @@ │ │ bgt 2486830 │ │ ldr r1, [pc, #60] @ 248698c │ │ mov r0, r5 │ │ mov r2, r4 │ │ mov r3, #3 │ │ add r1, pc, r1 │ │ b 2486730 │ │ - ldc2l 11, cr0, [fp, #484] @ 0x1e4 @ │ │ + ldc2l 11, cr0, [fp, #664] @ 0x298 @ │ │ ldc2l 4, cr2, [r9, #184] @ 0xb8 │ │ eoreq r2, sp, r8, lsr #24 │ │ eoreq r2, sp, r4, lsr #24 │ │ - ldc2l 12, cr4, [r9, #808] @ 0x328 │ │ + ldc2l 12, cr4, [r9, #988] @ 0x3dc │ │ eoreq r2, sp, r0, ror #23 │ │ eoreq r2, sp, r4, asr #23 │ │ strbeq pc, [fp], #-2056 @ 0xfffff7f8 @ │ │ eoreq r2, sp, ip, asr #22 │ │ eoreq r2, sp, r4, asr #22 │ │ eoreq r2, sp, r4, asr #22 │ │ - ldc2l 9, cr4, [sl, #272] @ 0x110 @ │ │ - ldc2l 11, cr0, [fp, #68] @ 0x44 @ │ │ + ldc2l 9, cr4, [sl, #362] @ 0x16a @ │ │ + ldc2l 11, cr0, [fp, #248] @ 0xf8 @ │ │ │ │ 02486994 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ mov r7, r0 │ │ ldr r0, [pc, #224] @ 2486a8c │ │ @@ -1375570,16 +1375570,16 @@ │ │ ldr r0, [pc, #24] @ 2486a90 │ │ mov r1, #5 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - ldc2l 13, cr6, [r9, #628] @ 0x274 │ │ - ldc2l 12, cr6, [r9, #852] @ 0x354 │ │ + ldc2l 13, cr6, [r9, #808] @ 0x328 │ │ + ldc2l 13, cr6, [r9, #8] │ │ │ │ 02486a94 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r6, r3 │ │ mov r4, r2 │ │ mov r5, r1 │ │ @@ -1375727,31 +1375727,31 @@ │ │ str r0, [r4, #4] │ │ ldr r0, [pc, #84] @ 2486d3c │ │ ldr r0, [pc, r0] │ │ str r0, [r4] │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ ldc2l 2, cr12, [fp, #784] @ 0x310 │ │ - ldc2l 13, cr4, [sl, #272] @ 0x110 │ │ + ldc2l 13, cr4, [sl, #452] @ 0x1c4 │ │ vcadd.f32 , q6, q11, #270 │ │ strbeq pc, [fp], #-1304 @ 0xfffffae8 @ │ │ strbeq pc, [fp], #-1284 @ 0xfffffafc @ │ │ strbeq pc, [fp], #-1272 @ 0xfffffb08 @ │ │ strbeq pc, [fp], #-1248 @ 0xfffffb20 @ │ │ strbeq pc, [fp], #-1004 @ 0xfffffc14 @ │ │ strbeq pc, [fp], #-992 @ 0xfffffc20 @ │ │ strbeq pc, [fp], #-852 @ 0xfffffcac @ │ │ strbeq pc, [fp], #-840 @ 0xfffffcb8 @ │ │ strbeq pc, [fp], #-1224 @ 0xfffffb38 @ │ │ strbeq pc, [fp], #-1204 @ 0xfffffb4c @ │ │ strbeq pc, [fp], #-1192 @ 0xfffffb58 @ │ │ strbeq pc, [fp], #-1164 @ 0xfffffb74 @ │ │ ldc2l 0, cr1, [r9, #520] @ 0x208 │ │ - ldc2l 12, cr2, [sl, #300] @ 0x12c │ │ - ldc2l 14, cr4, [sl, #528] @ 0x210 │ │ + ldc2l 12, cr2, [sl, #480] @ 0x1e0 │ │ + ldc2l 14, cr4, [sl, #708] @ 0x2c4 │ │ strbeq pc, [fp], #-796 @ 0xfffffce4 @ │ │ │ │ 02486d40 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ @@ -1375773,15 +1375773,15 @@ │ │ bl 270da10 │ │ mov r0, r4 │ │ mov r1, #5 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, sl, fp, pc} │ │ ldc2l 1, cr12, [fp, #640] @ 0x280 │ │ - ldc2l 12, cr4, [sl, #128] @ 0x80 │ │ + ldc2l 12, cr4, [sl, #308] @ 0x134 │ │ ldc2l 7, cr3, [ip, #264] @ 0x108 │ │ │ │ 02486db0 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ bl 270ce80 │ │ @@ -1375922,15 +1375922,15 @@ │ │ mov r2, r4 │ │ bl 270df10 │ │ mov r0, r7 │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 2, cr0, [fp, #708] @ 0x2c4 │ │ + ldc2l 2, cr0, [fp, #888] @ 0x378 │ │ │ │ 02486fd8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #316 @ 0x13c │ │ sub sp, sp, #2048 @ 0x800 │ │ mov r5, r3 │ │ @@ -1376168,33 +1376168,33 @@ │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 4, cr6, [fp, #220] @ 0xdc │ │ strbeq lr, [fp], #-4072 @ 0xfffff018 │ │ ldc2l 2, cr12, [r8, #896] @ 0x380 │ │ strbeq lr, [fp], #-4020 @ 0xfffff04c │ │ ldc2l 1, cr10, [fp, #56] @ 0x38 │ │ - ldc2l 0, cr14, [sl, #284] @ 0x11c │ │ - ldc2l 0, cr6, [r9, #508] @ 0x1fc │ │ + ldc2l 0, cr14, [sl, #464] @ 0x1d0 │ │ + ldc2l 0, cr6, [r9, #688] @ 0x2b0 │ │ eoreq r2, sp, r4, ror #5 │ │ strbeq lr, [fp], #-3848 @ 0xfffff0f8 │ │ strbeq lr, [fp], #-3828 @ 0xfffff10c │ │ - ldc2l 3, cr8, [sl, #608] @ 0x260 │ │ - ldc2l 12, cr11, [r9, #260] @ 0x104 │ │ + ldc2l 3, cr8, [sl, #788] @ 0x314 │ │ + ldc2l 12, cr11, [r9, #440] @ 0x1b8 │ │ ldc2l 14, cr7, [fp, #60] @ 0x3c │ │ strbeq lr, [fp], #-3796 @ 0xfffff12c │ │ ldc2l 8, cr13, [fp, #876] @ 0x36c │ │ - ldc2l 12, cr11, [r9, #500] @ 0x1f4 │ │ - ldc2l 7, cr14, [r9, #472] @ 0x1d8 │ │ - ldc2l 1, cr4, [sl, #320] @ 0x140 │ │ + ldc2l 12, cr11, [r9, #680] @ 0x2a8 │ │ + ldc2l 7, cr14, [r9, #652] @ 0x28c │ │ + ldc2l 1, cr4, [sl, #500] @ 0x1f4 │ │ strbeq lr, [fp], #-3728 @ 0xfffff170 │ │ strbeq lr, [fp], #-3656 @ 0xfffff1b8 │ │ eoreq r2, sp, r8, ror #3 │ │ ldrdeq r2, [sp], -ip @ │ │ ldc2l 5, cr14, [r8, #240] @ 0xf0 │ │ - ldc2l 14, cr13, [sl, #604] @ 0x25c │ │ + ldc2l 14, cr13, [sl, #784] @ 0x310 │ │ eoreq r2, sp, ip, ror #1 │ │ ldrdeq r2, [sp], -ip @ │ │ strhteq r2, [sp], -r4 │ │ eoreq r2, sp, r4, lsl #1 │ │ ldc2l 0, cr6, [fp, #812] @ 0x32c │ │ │ │ 02487404 : │ │ @@ -1376510,27 +1376510,27 @@ │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 1, cr9, [ip, #476] @ 0x1dc │ │ strbeq lr, [fp], #-3048 @ 0xfffff418 │ │ ldc2l 14, cr11, [r8, #720] @ 0x2d0 │ │ strbeq lr, [fp], #-2996 @ 0xfffff44c │ │ ldc2l 12, cr9, [fp, #904] @ 0x388 │ │ - ldc2l 5, cr0, [sl, #192] @ 0xc0 │ │ - ldc2l 12, cr5, [r9, #332] @ 0x14c │ │ + ldc2l 5, cr0, [sl, #372] @ 0x174 │ │ + ldc2l 12, cr5, [r9, #512] @ 0x200 │ │ eoreq r1, sp, ip, ror #29 │ │ strbeq lr, [fp], #-2824 @ 0xfffff4f8 │ │ strbeq lr, [fp], #-2804 @ 0xfffff50c │ │ - ldc2l 15, cr7, [sl, #144] @ 0x90 │ │ - ldc2l 7, cr11, [r9, #820] @ 0x334 │ │ + ldc2l 15, cr7, [sl, #324] @ 0x144 │ │ + ldc2l 7, cr11, [r9, #1000] @ 0x3e8 │ │ ldc2l 9, cr7, [fp, #310] @ 0x136 @ │ │ strbeq lr, [fp], #-2772 @ 0xfffff52c │ │ ldc2l 4, cr13, [fp, #412] @ 0x19c │ │ - vcadd.f32 d27, d9, d9, #270 │ │ - ldc2l 3, cr14, [r9, #8] │ │ - ldc2l 13, cr3, [sl, #144] @ 0x90 │ │ + ldc2l 8, cr11, [r9, #216] @ 0xd8 │ │ + ldc2l 3, cr14, [r9, #188] @ 0xbc │ │ + ldc2l 13, cr3, [sl, #324] @ 0x144 │ │ strbeq lr, [fp], #-2704 @ 0xfffff570 │ │ strbeq lr, [fp], #-2632 @ 0xfffff5b8 │ │ strdeq r1, [sp], -r0 @ │ │ strdeq r1, [sp], -ip @ │ │ eoreq r1, sp, r0, ror #27 │ │ eoreq r1, sp, r4, asr #27 │ │ eoreq r1, sp, r8, lsr #27 │ │ @@ -1376940,32 +1376940,32 @@ │ │ str r0, [fp, #-48] @ 0xffffffd0 │ │ bge 2487c38 │ │ sub r1, r0, #1 │ │ cmp r0, #0 │ │ ble 2487f58 │ │ mov r2, r0 │ │ b 2487f70 │ │ - ldc2l 1, cr12, [r9, #600] @ 0x258 │ │ + ldc2l 1, cr12, [r9, #780] @ 0x30c │ │ strbeq lr, [fp], #-1724 @ 0xfffff944 │ │ ldc2l 9, cr11, [r8, #176] @ 0xb0 @ │ │ strbeq lr, [fp], #-2696 @ 0xfffff578 │ │ ldc2l 7, cr9, [fp, #536] @ 0x218 │ │ ldc2l 13, cr6, [ip, #732] @ 0x2dc │ │ - ldc2l 6, cr5, [r9, #988] @ 0x3dc │ │ + ldc2l 7, cr5, [r9, #144] @ 0x90 │ │ eoreq r1, sp, r0, asr #19 │ │ strbeq lr, [fp], #-2524 @ 0xfffff624 │ │ strbeq lr, [fp], #-1480 @ 0xfffffa38 │ │ - ldc2l 9, cr7, [sl, #440] @ 0x1b8 @ │ │ - ldc2l 2, cr11, [r9, #532] @ 0x214 │ │ + ldc2l 10, cr7, [sl, #36] @ 0x24 @ │ │ + ldc2l 2, cr11, [r9, #712] @ 0x2c8 │ │ ldc2l 4, cr7, [fp, #332] @ 0x14c │ │ strbeq lr, [fp], #-1448 @ 0xfffffa58 │ │ ldc2l 15, cr12, [fp, #1004] @ 0x3ec │ │ - ldc2l 3, cr11, [r9, #628] @ 0x274 │ │ - ldc2l 14, cr13, [r9, #600] @ 0x258 │ │ - ldc2l 7, cr3, [sl, #800] @ 0x320 │ │ + ldc2l 3, cr11, [r9, #808] @ 0x328 │ │ + ldc2l 14, cr13, [r9, #780] @ 0x30c │ │ + ldc2l 7, cr3, [sl, #980] @ 0x3d4 │ │ strbeq lr, [fp], #-2404 @ 0xfffff69c │ │ strbeq lr, [fp], #-1240 @ 0xfffffb28 │ │ eoreq r1, sp, r0, lsl #17 │ │ strbeq lr, [fp], #-1180 @ 0xfffffb64 │ │ eoreq r1, sp, r4, ror r8 │ │ ldc2l 11, cr13, [r8, #448] @ 0x1c0 @ │ │ ldc2l 11, cr6, [ip, #780] @ 0x30c @ │ │ @@ -1376984,15 +1376984,15 @@ │ │ vcadd.f32 d22, d28, d7, #270 │ │ strbeq lr, [fp], #-736 @ 0xfffffd20 │ │ ldc2l 7, cr13, [r8, #1008] @ 0x3f0 │ │ vcadd.f32 q11, q6, , #270 │ │ strbeq lr, [fp], #-240 @ 0xffffff10 │ │ strbeq lr, [fp], #-1056 @ 0xfffffbe0 │ │ eoreq r1, sp, r0, lsl #16 │ │ - ldc2l 14, cr11, [r9, #88] @ 0x58 │ │ + ldc2l 14, cr11, [r9, #268] @ 0x10c │ │ │ │ 02488058 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #172 @ 0xac │ │ mov r5, r3 │ │ mov r4, r2 │ │ @@ -1377240,16 +1377240,16 @@ │ │ mlaeq sp, r0, r1, r1 │ │ eoreq r1, sp, r0, ror r1 │ │ strbeq lr, [fp], #-412 @ 0xfffffe64 │ │ eoreq r1, sp, ip, asr #2 │ │ strbeq lr, [fp], #-979 @ 0xfffffc2d │ │ eoreq r1, sp, r8, lsr #2 │ │ strbeq lr, [fp], #-972 @ 0xfffffc34 │ │ - ldc2l 13, cr12, [sl, #260] @ 0x104 │ │ - ldc2l 11, cr10, [r9, #500] @ 0x1f4 @ │ │ + ldc2l 13, cr12, [sl, #440] @ 0x1b8 │ │ + ldc2l 11, cr10, [r9, #680] @ 0x2a8 @ │ │ ldc2l 1, cr6, [ip, #720] @ 0x2d0 │ │ ldc2l 6, cr10, [fp, #508] @ 0x1fc │ │ ldc2l 9, cr1, [r9, #266] @ 0x10a @ │ │ │ │ 02488460 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ @@ -1377406,36 +1377406,36 @@ │ │ mov r3, r5 │ │ str r1, [sp] │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ add r1, sp, #24 │ │ bl 270fa00 │ │ b 2488698 │ │ - ldc2l 5, cr15, [r9, #232] @ 0xe8 │ │ + ldc2l 5, cr15, [r9, #412] @ 0x19c │ │ strbeq lr, [fp], #-932 @ 0xfffffc5c │ │ strbeq lr, [fp], #-916 @ 0xfffffc6c │ │ - ldc2l 0, cr7, [r9, #344] @ 0x158 │ │ + ldc2l 0, cr7, [r9, #524] @ 0x20c │ │ strbeq lr, [fp], #-872 @ 0xfffffc98 │ │ strbeq lr, [fp], #-828 @ 0xfffffcc4 │ │ ldc2l 14, cr4, [fp, #576] @ 0x240 │ │ - ldc2l 9, cr10, [r9, #90] @ 0x5a @ │ │ - ldc2l 4, cr13, [r9, #152] @ 0x98 │ │ + ldc2l 9, cr10, [r9, #180] @ 0xb4 @ │ │ + ldc2l 4, cr13, [r9, #332] @ 0x14c │ │ strbeq lr, [fp], #-768 @ 0xfffffd00 │ │ strbeq lr, [fp], #-764 @ 0xfffffd04 │ │ eoreq r0, sp, r4, lsl pc │ │ eoreq r0, sp, r0, lsl pc │ │ ldc2l 8, cr0, [ip, #352] @ 0x160 │ │ - vcadd.f32 d26, d25, d21, #270 │ │ + ldc2l 8, cr10, [r9, #840] @ 0x348 │ │ ldc2l 10, cr12, [r8, #508] @ 0x1fc @ │ │ mlaeq sp, r0, lr, r0 │ │ eoreq r0, sp, ip, ror lr │ │ ldc2l 13, cr2, [fp, #840] @ 0x348 │ │ strbeq lr, [fp], #-380 @ 0xfffffe84 │ │ eoreq r0, sp, r8, asr #27 │ │ - ldc2l 3, cr15, [r9, #152] @ 0x98 │ │ + ldc2l 3, cr15, [r9, #332] @ 0x14c │ │ │ │ 02488734 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #1312 @ 0x520 │ │ mov r5, r2 │ │ mov r4, r1 │ │ @@ -1377592,30 +1377592,30 @@ │ │ add r2, pc, r2 │ │ add r1, sp, #24 │ │ bl 270fa10 │ │ b 248896c │ │ ldc2l 12, cr6, [fp, #512] @ 0x200 │ │ strbeq lr, [fp], #-224 @ 0xffffff20 │ │ strbeq lr, [fp], #-208 @ 0xffffff30 │ │ - ldc2l 13, cr6, [r9, #520] @ 0x208 │ │ + ldc2l 13, cr6, [r9, #700] @ 0x2bc │ │ strbeq lr, [fp], #-164 @ 0xffffff5c │ │ strbeq lr, [fp], #-120 @ 0xffffff88 │ │ ldc2l 11, cr4, [fp, #752] @ 0x2f0 @ │ │ - ldc2l 6, cr10, [r9, #356] @ 0x164 │ │ - ldc2l 1, cr13, [r9, #328] @ 0x148 │ │ + ldc2l 6, cr10, [r9, #536] @ 0x218 │ │ + ldc2l 1, cr13, [r9, #508] @ 0x1fc │ │ strbeq lr, [fp], #-60 @ 0xffffffc4 │ │ strbeq lr, [fp], #-56 @ 0xffffffc8 │ │ eoreq r0, sp, r0, ror ip │ │ eoreq r0, sp, ip, ror #24 │ │ ldc2l 1, cr4, [ip, #680] @ 0x2a8 │ │ - ldc2l 5, cr10, [r9, #836] @ 0x344 │ │ + ldc2l 5, cr10, [r9, #1016] @ 0x3f8 │ │ ldc2l 7, cr12, [r8, #684] @ 0x2ac │ │ eoreq r0, sp, ip, ror #23 │ │ ldrdeq r0, [sp], -r8 @ │ │ - ldc2l 0, cr3, [r9] │ │ + ldc2l 0, cr3, [r9, #180] @ 0xb4 │ │ strbeq sp, [fp], #-3768 @ 0xfffff148 │ │ eoreq r0, sp, r4, lsr #22 │ │ ldc2l 10, cr6, [fp, #432] @ 0x1b0 @ │ │ │ │ 02488a08 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -1377835,15 +1377835,15 @@ │ │ ldr r0, [pc, #120] @ 2488de4 │ │ mov r1, #8 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 15, cr12, [r9, #912] @ 0x390 │ │ + ldc2l 0, cr13, [r9, #68] @ 0x44 │ │ strbeq sp, [fp], #-3596 @ 0xfffff1f4 │ │ strbeq sp, [fp], #-3580 @ 0xfffff204 │ │ strbeq lr, [fp], #-108 @ 0xffffff94 │ │ strbeq sp, [fp], #-4031 @ 0xfffff041 │ │ eoreq r0, sp, ip, asr #19 │ │ strbeq sp, [fp], #-3376 @ 0xfffff2d0 │ │ eoreq r0, sp, r0, asr r9 │ │ @@ -1377856,19 +1377856,19 @@ │ │ eoreq r0, sp, r0, lsl #17 │ │ eoreq r0, sp, r0, ror #16 │ │ strbeq sp, [fp], #-3040 @ 0xfffff420 │ │ eoreq r0, sp, ip, lsr r8 │ │ strbeq sp, [fp], #-3611 @ 0xfffff1e5 │ │ eoreq r0, sp, r8, lsl r8 │ │ strbeq sp, [fp], #-3608 @ 0xfffff1e8 │ │ - ldc2l 3, cr12, [sl, #724] @ 0x2d4 │ │ - ldc2l 1, cr10, [r9, #964] @ 0x3c4 │ │ + ldc2l 3, cr12, [sl, #904] @ 0x388 │ │ + ldc2l 2, cr10, [r9, #120] @ 0x78 │ │ vcadd.f32 d21, d12, d24, #270 │ │ ldc2l 3, cr12, [r8, #476] @ 0x1dc │ │ - ldc2l 12, cr12, [r9, #720] @ 0x2d0 │ │ + ldc2l 12, cr12, [r9, #900] @ 0x384 │ │ │ │ 02488de8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #28 │ │ sub sp, sp, #1024 @ 0x400 │ │ mov r6, r3 │ │ @@ -1378092,32 +1378092,32 @@ │ │ mov r0, r9 │ │ mov r3, #60 @ 0x3c │ │ bl 270d9e0 │ │ b 248908c │ │ ldc2l 13, cr1, [ip, #140] @ 0x8c │ │ strbeq sp, [fp], #-3564 @ 0xfffff214 │ │ eoreq r0, sp, ip, lsr #13 │ │ - ldc2l 6, cr6, [r9, #792] @ 0x318 │ │ + ldc2l 6, cr6, [r9, #972] @ 0x3cc │ │ strbeq sp, [fp], #-3496 @ 0xfffff258 │ │ eoreq r0, sp, r8, lsl #13 │ │ eoreq r0, sp, r4, lsr r6 │ │ eoreq r0, sp, r0, lsr #12 │ │ eoreq r0, sp, r8, lsr #12 │ │ eoreq r0, sp, r8, lsl #12 │ │ eoreq r0, sp, r8, ror #11 │ │ eoreq r0, sp, r8, asr #11 │ │ eoreq r0, sp, r8, lsr #11 │ │ eoreq r0, sp, r8, lsl #11 │ │ ldc2l 3, cr10, [r8, #480] @ 0x1e0 │ │ - ldc2l 15, cr9, [r9, #196] @ 0xc4 │ │ + ldc2l 15, cr9, [r9, #376] @ 0x178 │ │ ldc2l 0, cr12, [r8, #556] @ 0x22c │ │ eoreq r0, sp, r8, lsl r5 │ │ eoreq r0, sp, ip, lsl #10 │ │ ldc2l 11, cr14, [r8, #892] @ 0x37c @ │ │ - ldc2l 14, cr9, [r9, #708] @ 0x2c4 │ │ + ldc2l 14, cr9, [r9, #888] @ 0x378 │ │ eoreq r0, sp, r8, lsr r4 │ │ ldc2l 10, cr1, [ip, #684] @ 0x2ac @ │ │ │ │ 024891cc : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #16 │ │ @@ -1379304,15 +1379304,15 @@ │ │ b 248b6d4 │ │ eoreq r0, sp, ip, lsl #2 │ │ strbteq fp, [r1], #-3780 @ 0xfffff13c │ │ strhteq r0, [sp], -r4 │ │ strbteq fp, [r1], #-3720 @ 0xfffff178 │ │ strbteq r6, [r1], #-3820 @ 0xfffff114 │ │ strbeq sp, [fp], #-1832 @ 0xfffff8d8 │ │ - ldc2l 11, cr11, [sl, #916] @ 0x394 @ │ │ + ldc2l 12, cr11, [sl, #72] @ 0x48 │ │ ldc2l 15, cr1, [fp, #344] @ 0x158 │ │ strbeq sp, [fp], #-1768 @ 0xfffff918 │ │ strbteq fp, [r1], #-3528 @ 0xfffff238 │ │ strbteq fp, [r1], #-3604 @ 0xfffff1ec │ │ strbteq fp, [r1], #-3612 @ 0xfffff1e4 │ │ strbteq fp, [r1], #-3540 @ 0xfffff22c │ │ strbteq fp, [r1], #-3564 @ 0xfffff214 │ │ @@ -1379445,23 +1379445,23 @@ │ │ mov r2, #1 │ │ mov r3, r8 │ │ bl 270da60 │ │ ldr r0, [pc, #3984] @ 248b618 │ │ mov r1, #22 │ │ add r0, pc, r0 │ │ b 248b5f4 │ │ - ldc2l 3, cr12, [r9, #564] @ 0x234 │ │ + ldc2l 3, cr12, [r9, #744] @ 0x2e8 │ │ strbeq sp, [fp], #-1400 @ 0xfffffa88 │ │ strbteq fp, [r1], #-3168 @ 0xfffff3a0 │ │ strbteq fp, [r1], #-3244 @ 0xfffff354 │ │ strbteq fp, [r1], #-3252 @ 0xfffff34c │ │ strbteq fp, [r1], #-3180 @ 0xfffff394 │ │ strbteq fp, [r1], #-3208 @ 0xfffff378 │ │ strbteq fp, [r1], #-3136 @ 0xfffff3c0 │ │ - ldc2l 3, cr12, [r9, #84] @ 0x54 │ │ + ldc2l 3, cr12, [r9, #264] @ 0x108 │ │ strbeq sp, [fp], #-1260 @ 0xfffffb14 │ │ strbteq fp, [r1], #-3020 @ 0xfffff434 │ │ strbteq fp, [r1], #-3096 @ 0xfffff3e8 │ │ strbteq fp, [r1], #-3104 @ 0xfffff3e0 │ │ strbteq fp, [r1], #-3032 @ 0xfffff428 │ │ strbteq fp, [r1], #-3060 @ 0xfffff40c │ │ strbteq fp, [r1], #-2988 @ 0xfffff454 │ │ @@ -1379530,15 +1379530,15 @@ │ │ add r0, pc, r0 │ │ mov r2, #1 │ │ bl 270da60 │ │ ldr r0, [pc, #3900] @ 248b718 │ │ mov r1, #21 │ │ add r0, pc, r0 │ │ b 248a434 │ │ - ldc2l 14, cr3, [sl, #844] @ 0x34c │ │ + ldc2l 15, cr3, [sl] │ │ ldc2l 11, cr5, [fp, #964] @ 0x3c4 @ │ │ strbteq r6, [r1], #-3048 @ 0xfffff418 │ │ strbeq sp, [fp], #-1012 @ 0xfffffc0c │ │ strbeq r2, [ip], #-544 @ 0xfffffde0 │ │ ldc2l 12, cr0, [ip, #772] @ 0x304 │ │ ldc2l 11, cr5, [fp, #436] @ 0x1b4 @ │ │ strbeq r0, [sp], #-3120 @ 0xfffff3d0 │ │ @@ -1379766,21 +1379766,21 @@ │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #3980] @ 248bb14 │ │ mov r1, #10 │ │ add r0, pc, r0 │ │ b 248b5f4 │ │ strbeq r6, [ip], #-3292 @ 0xfffff324 │ │ - ldc2l 5, cr11, [sl, #804] @ 0x324 │ │ + ldc2l 5, cr11, [sl, #984] @ 0x3d8 │ │ ldc2l 9, cr3, [fp, #74] @ 0x4a @ │ │ vcadd.f32 d21, d11, d5, #270 │ │ strbeq fp, [ip], #-2728 @ 0xfffff558 │ │ - ldc2l 15, cr9, [r9, #580] @ 0x244 │ │ + ldc2l 15, cr9, [r9, #760] @ 0x2f8 │ │ ldc2l 7, cr5, [fp, #852] @ 0x354 │ │ - ldc2l 2, cr9, [r9, #836] @ 0x344 │ │ + ldc2l 2, cr9, [r9, #1016] @ 0x3f8 │ │ movw r0, #5001 @ 0x1389 │ │ cmp r5, r0 │ │ str r9, [fp, #-48] @ 0xffffffd0 │ │ bcc 248abe0 │ │ ldr r0, [pc, #3920] @ 248bb18 │ │ mov r1, r9 │ │ ldr r2, [pc, #3916] @ 248bb1c │ │ @@ -1379807,15 +1379807,15 @@ │ │ add r6, r1, r0 │ │ add r7, pc, r7 │ │ add r8, pc, r8 │ │ b 248acb8 │ │ ldc2l 11, cr4, [ip, #688] @ 0x2b0 @ │ │ ldc2l 7, cr5, [fp, #564] @ 0x234 │ │ strbeq r5, [sp], #-1632 @ 0xfffff9a0 │ │ - ldc2l 2, cr9, [r9, #516] @ 0x204 │ │ + ldc2l 2, cr9, [r9, #696] @ 0x2b8 │ │ ldc2l 0, cr0, [r9, #872] @ 0x368 │ │ strbeq ip, [fp], #-3968 @ 0xfffff080 │ │ strbteq fp, [r1], #-1632 @ 0xfffff9a0 │ │ strbteq fp, [r1], #-1708 @ 0xfffff954 │ │ strbteq fp, [r1], #-1716 @ 0xfffff94c │ │ strbteq fp, [r1], #-1644 @ 0xfffff994 │ │ strbteq fp, [r1], #-1672 @ 0xfffff978 │ │ @@ -1379829,15 +1379829,15 @@ │ │ strbteq fp, [r1], #-1376 @ 0xfffffaa0 │ │ strbteq fp, [r1], #-1452 @ 0xfffffa54 │ │ strbteq fp, [r1], #-1460 @ 0xfffffa4c │ │ strbteq fp, [r1], #-1388 @ 0xfffffa94 │ │ strbteq fp, [r1], #-1416 @ 0xfffffa78 │ │ strbteq fp, [r1], #-1344 @ 0xfffffac0 │ │ ldc2l 9, cr11, [r8, #128] @ 0x80 @ │ │ - vcadd.f32 d19, d26, d6, #270 │ │ + ldc2l 8, cr3, [sl, #716] @ 0x2cc │ │ ldc2l 6, cr0, [ip, #504] @ 0x1f8 │ │ ldc2l 15, cr12, [r8, #892] @ 0x37c │ │ ldr r0, [fp, #-48] @ 0xffffffd0 │ │ add r5, r5, #1 │ │ add r1, r4, r9, lsl #3 │ │ add r6, r6, #255 @ 0xff │ │ cmp r5, r0 │ │ @@ -1379956,15 +1379956,15 @@ │ │ mov r0, r9 │ │ b 248aed0 │ │ ldc2l 6, cr0, [ip, #644] @ 0x284 │ │ ldc2l 5, cr5, [fp, #308] @ 0x134 │ │ strbeq r0, [sp], #-1552 @ 0xfffff9f0 │ │ ldc2l 9, cr4, [ip, #112] @ 0x70 @ │ │ ldc2l 5, cr5, [fp, #84] @ 0x54 │ │ - ldc2l 4, cr9, [sl, #800] @ 0x320 │ │ + ldc2l 4, cr9, [sl, #980] @ 0x3d4 │ │ ldr r0, [pc, #3988] @ 248be2c │ │ mov r1, r9 │ │ mov r2, r8 │ │ movw r3, #1693 @ 0x69d │ │ add r0, pc, r0 │ │ str r6, [sp, #84] @ 0x54 │ │ mov r6, r8 │ │ @@ -1379991,23 +1379991,23 @@ │ │ mov r0, r5 │ │ mov r7, r8 │ │ b 248af8c │ │ strbteq r6, [r1], #-1340 @ 0xfffffac4 │ │ strbeq r5, [sp], #-956 @ 0xfffffc44 │ │ ldc2l 5, cr3, [fp, #804] @ 0x324 │ │ strbeq fp, [ip], #-1860 @ 0xfffff8bc │ │ - ldc2l 2, cr11, [sl, #60] @ 0x3c │ │ + ldc2l 2, cr11, [sl, #240] @ 0xf0 │ │ strbeq ip, [fp], #-3256 @ 0xfffff348 │ │ ldc2l 5, cr1, [fp, #72] @ 0x48 │ │ strbeq r6, [ip], #-2252 @ 0xfffff734 │ │ ldc2l 14, cr12, [r8, #508] @ 0x1fc │ │ ldc2l 5, cr0, [ip, #244] @ 0xf4 │ │ ldc2l 3, cr5, [fp, #932] @ 0x3a4 │ │ strbeq r0, [sp], #-1196 @ 0xfffffb54 │ │ - ldc2l 1, cr11, [sl, #268] @ 0x10c │ │ + ldc2l 1, cr11, [sl, #448] @ 0x1c0 │ │ ldr r0, [pc, #3828] @ 248be38 │ │ mov r1, r5 │ │ mov r2, r8 │ │ movw r3, #1694 @ 0x69e │ │ add r0, pc, r0 │ │ bl 270da30 │ │ rsb r0, r0, r0, lsl #8 │ │ @@ -1380199,15 +1380199,15 @@ │ │ strbeq ip, [fp], #-2456 @ 0xfffff668 │ │ strbteq sl, [r1], #-4048 @ 0xfffff030 │ │ strbeq ip, [fp], #-2452 @ 0xfffff66c │ │ strbteq ip, [r0], #-1172 @ 0xfffffb6c │ │ strbeq ip, [fp], #-2388 @ 0xfffff6ac │ │ ldc2l 13, cr8, [fp, #32] │ │ ldc2l 0, cr5, [fp, #964] @ 0x3c4 │ │ - ldc2l 3, cr3, [sl, #588] @ 0x24c │ │ + ldc2l 3, cr3, [sl, #768] @ 0x300 │ │ ldc2l 0, cr5, [fp, #708] @ 0x2c4 │ │ strbteq r6, [r1], #-168 @ 0xffffff58 │ │ strbteq r6, [r1], #-144 @ 0xffffff70 │ │ strbeq ip, [fp], #-2252 @ 0xfffff734 │ │ ldr r0, [pc, #3964] @ 248c1f0 │ │ ldr r6, [fp, #12] │ │ ldr r0, [pc, r0] │ │ @@ -1380284,20 +1380284,20 @@ │ │ ldr r0, [pc, #4080] @ 248c388 │ │ mov r1, #23 │ │ add r0, pc, r0 │ │ b 248a914 │ │ ldc2l 4, cr4, [ip, #320] @ 0x140 │ │ ldc2l 0, cr5, [fp, #196] @ 0xc4 │ │ strbeq r4, [sp], #-3844 @ 0xfffff0fc │ │ - ldc2l 11, cr8, [r9, #148] @ 0x94 @ │ │ + ldc2l 11, cr8, [r9, #328] @ 0x148 @ │ │ ldc2l 11, cr12, [fp, #472] @ 0x1d8 @ │ │ ldc2l 7, cr0, [ip, #352] @ 0x160 │ │ - ldc2l 10, cr8, [r9, #900] @ 0x384 @ │ │ + ldc2l 11, cr8, [r9, #56] @ 0x38 @ │ │ ldc2l 15, cr8, [r8, #644] @ 0x284 │ │ - ldc2l 5, cr11, [r9, #948] @ 0x3b4 │ │ + ldc2l 6, cr11, [r9, #104] @ 0x68 │ │ ldr r0, [pc, #4076] @ 248c3b8 │ │ mov r1, r4 │ │ ldr r2, [pc, #4072] @ 248c3bc │ │ movw r3, #2422 @ 0x976 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1380346,16 +1380346,16 @@ │ │ strbteq r5, [r1], #-3828 @ 0xfffff10c │ │ strbeq ip, [fp], #-1824 @ 0xfffff8e0 │ │ strbteq ip, [r0], #-636 @ 0xfffffd84 │ │ strbeq ip, [fp], #-1768 @ 0xfffff918 │ │ strbteq sl, [r1], #-3360 @ 0xfffff2e0 │ │ strbteq ip, [r0], #-504 @ 0xfffffe08 │ │ ldc2l 1, cr11, [r8, #848] @ 0x350 │ │ - ldc2l 5, cr9, [r9, #620] @ 0x26c │ │ - ldc2l 9, cr8, [r9, #154] @ 0x9a @ │ │ + ldc2l 5, cr9, [r9, #800] @ 0x320 │ │ + ldc2l 9, cr8, [r9, #244] @ 0xf4 @ │ │ ldr r0, [pc, #3912] @ 248c3fc │ │ mov r1, #8 │ │ add r0, pc, r0 │ │ bl 270ce90 │ │ ldr r0, [pc, #3900] @ 248c400 │ │ mov r1, #95 @ 0x5f │ │ add r0, pc, r0 │ │ @@ -1380421,32 +1380421,32 @@ │ │ ldr r0, [pc, #3956] @ 248c530 │ │ mov r1, #21 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #3944] @ 248c534 │ │ add r0, pc, r0 │ │ b 248b6d4 │ │ - ldc2l 4, cr5, [r9, #240] @ 0xf0 │ │ + ldc2l 4, cr5, [r9, #420] @ 0x1a4 │ │ ldc2l 11, cr6, [fp, #484] @ 0x1e4 @ │ │ ldr r0, [pc, #3928] @ 248c538 │ │ mov r1, #71 @ 0x47 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #3916] @ 248c53c │ │ mov r1, #20 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #3904] @ 248c540 │ │ add r0, pc, r0 │ │ b 248b6d4 │ │ - ldc2l 4, cr5, [r9, #284] @ 0x11c │ │ - vcadd.f32 q12, , , #270 │ │ + ldc2l 4, cr5, [r9, #464] @ 0x1d0 │ │ + ldc2l 9, cr8, [r9, #28] @ │ │ ldc2l 10, cr4, [fp, #700] @ 0x2bc @ │ │ - ldc2l 1, cr3, [r9, #44] @ 0x2c │ │ - vcadd.f32 d24, d25, d17, #270 │ │ + ldc2l 1, cr3, [r9, #224] @ 0xe0 │ │ + vcadd.f32 q12, , q7, #270 │ │ ldc2l 7, cr12, [fp, #956] @ 0x3bc │ │ ldr r0, [pc, #3872] @ 248c544 │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #3868] @ 248c548 │ │ ldr r1, [pc, r1] │ │ cmp r1, r0 │ │ bge 248b6cc │ │ @@ -1380483,42 +1380483,42 @@ │ │ ldr r7, [pc, #3760] @ 248c564 │ │ ldr r8, [pc, #3760] @ 248c568 │ │ ldr r4, [pc, #3760] @ 248c56c │ │ add r7, pc, r7 │ │ add r8, pc, r8 │ │ add r4, pc, r4 │ │ b 248b74c │ │ - ldc2l 2, cr7, [r9, #956] @ 0x3bc │ │ + ldc2l 3, cr7, [r9, #112] @ 0x70 │ │ ldr r0, [pc, #4084] @ 248c6c8 │ │ add r0, pc, r0 │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #40 @ 0x28 │ │ vpop {d8} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 13, cr2, [fp, #948] @ 0x3b4 │ │ ldc2l 12, cr4, [fp, #820] @ 0x334 │ │ - ldc2l 4, cr9, [r9, #388] @ 0x184 │ │ + ldc2l 4, cr9, [r9, #568] @ 0x238 │ │ ldc2l 12, cr4, [fp, #660] @ 0x294 │ │ - ldc2l 7, cr8, [r9, #644] @ 0x284 │ │ + ldc2l 7, cr8, [r9, #824] @ 0x338 │ │ ldc2l 12, cr14, [r8, #372] @ 0x174 │ │ ldc2l 0, cr4, [ip, #400] @ 0x190 │ │ ldc2l 12, cr4, [fp, #276] @ 0x114 │ │ strbeq r4, [sp], #-2840 @ 0xfffff4e8 │ │ - ldc2l 11, cr2, [sl, #672] @ 0x2a0 @ │ │ + ldc2l 11, cr2, [sl, #852] @ 0x354 @ │ │ ldc2l 12, cr0, [fp, #720] @ 0x2d0 │ │ ldc2l 11, cr8, [r8, #348] @ 0x15c @ │ │ ldc2l 12, cr2, [fp, #772] @ 0x304 │ │ ldc2l 11, cr4, [fp, #644] @ 0x284 @ │ │ strbeq sl, [ip], #-3652 @ 0xfffff1bc │ │ - ldc2l 3, cr9, [r9, #180] @ 0xb4 │ │ + ldc2l 3, cr9, [r9, #360] @ 0x168 │ │ ldc2l 11, cr4, [fp, #452] @ 0x1c4 @ │ │ - ldc2l 6, cr8, [r9, #436] @ 0x1b4 │ │ + ldc2l 6, cr8, [r9, #616] @ 0x268 │ │ ldr r0, [fp, #-48] @ 0xffffffd0 │ │ add r6, r6, #1 │ │ str r5, [sl, r9, lsl #2] │ │ cmp r6, r0 │ │ bge 248c1c8 │ │ cmp r6, #23 │ │ mov r0, r6 │ │ @@ -1380605,15 +1380605,15 @@ │ │ bl 270da30 │ │ mov r9, r0 │ │ b 248b738 │ │ ldc2l 11, cr14, [r8, #164] @ 0xa4 @ │ │ ldc2l 15, cr3, [ip, #192] @ 0xc0 │ │ ldc2l 11, cr4, [fp, #68] @ 0x44 @ │ │ strbeq r4, [sp], #-2532 @ 0xfffff61c │ │ - ldc2l 10, cr2, [sl, #464] @ 0x1d0 @ │ │ + ldc2l 10, cr2, [sl, #644] @ 0x284 @ │ │ ldc2l 11, cr0, [fp, #512] @ 0x200 @ │ │ ldc2l 10, cr4, [fp, #1000] @ 0x3e8 @ │ │ ldr r1, [sp, #124] @ 0x7c │ │ mvn r6, r0 │ │ sub r1, r1, #1 │ │ str r1, [fp, #-48] @ 0xffffffd0 │ │ cmp r1, #23 │ │ @@ -1380757,15 +1380757,15 @@ │ │ ldr r2, [fp, #16] │ │ add r0, pc, r0 │ │ ldr r1, [r0, r1, lsl #2] │ │ ldr r0, [pc, #3968] @ 248ca88 │ │ str r1, [r2] │ │ add r0, pc, r0 │ │ b 248b6d4 │ │ - ldc2l 14, cr4, [r9, #740] @ 0x2e4 │ │ + ldc2l 14, cr4, [r9, #920] @ 0x398 │ │ ldc2l 5, cr4, [fp, #348] @ 0x15c │ │ ldc2l 8, cr0, [fp, #856] @ 0x358 │ │ ldc2l 8, cr4, [fp, #84] @ 0x54 │ │ ldr r0, [pc, #3940] @ 248ca8c │ │ mov r1, r5 │ │ ldr r2, [pc, #3936] @ 248ca90 │ │ movw r3, #2071 @ 0x817 │ │ @@ -1380815,17 +1380815,17 @@ │ │ mov r0, r5 │ │ b 248bc58 │ │ strbeq r5, [ip], #-3220 @ 0xfffff36c │ │ strbeq ip, [fp], #-56 @ 0xffffffc8 │ │ strbeq r4, [sp], #-1728 @ 0xfffff940 │ │ ldc2l 7, cr4, [fp, #804] @ 0x324 │ │ strbeq r5, [ip], #-3156 @ 0xfffff3ac │ │ - ldc2l 9, cr2, [sl, #498] @ 0x1f2 @ │ │ + ldc2l 10, cr2, [sl, #152] @ 0x98 @ │ │ strbeq r0, [ip], #-3440 @ 0xfffff290 │ │ - ldc2l 9, cr2, [sl, #394] @ 0x18a @ │ │ + ldc2l 9, cr2, [sl, #484] @ 0x1e4 @ │ │ strbeq r0, [ip], #-3392 @ 0xfffff2c0 │ │ ldc2l 7, cr0, [fp, #440] @ 0x1b8 │ │ ldc2l 7, cr0, [fp, #280] @ 0x118 │ │ ldr r0, [pc, #4004] @ 248cbbc │ │ mov r1, r5 │ │ ldr r4, [pc, #4000] @ 248cbc0 │ │ movw r3, #2074 @ 0x81a │ │ @@ -1380935,17 +1380935,17 @@ │ │ str r1, [fp, #-48] @ 0xffffffd0 │ │ ldr r6, [pc, #4076] @ 248cdb4 │ │ cmp r1, #22 │ │ add r6, pc, r6 │ │ bhi 248c150 │ │ str r4, [r6, r1, lsl #2] │ │ b 248c1a4 │ │ - ldc2l 3, cr10, [sl, #572] @ 0x23c │ │ + ldc2l 3, cr10, [sl, #752] @ 0x2f0 │ │ strbeq fp, [fp], #-3648 @ 0xfffff1c0 │ │ - ldc2l 3, cr10, [sl, #380] @ 0x17c │ │ + ldc2l 3, cr10, [sl, #560] @ 0x230 │ │ cmp r2, #0 │ │ beq 248c200 │ │ ldr r0, [sp, #124] @ 0x7c │ │ mov r1, #1 │ │ str r1, [fp, #-84] @ 0xffffffac │ │ sub r1, r0, #1 │ │ str r1, [fp, #-48] @ 0xffffffd0 │ │ @@ -1380960,22 +1380960,22 @@ │ │ strbeq fp, [fp], #-3600 @ 0xfffff1f0 │ │ ldc2l 6, cr15, [fp, #964] @ 0x3c4 │ │ strbeq pc, [ip], #-1628 @ 0xfffff9a4 @ │ │ ldc2l 6, cr15, [fp, #612] @ 0x264 │ │ ldc2l 9, cr3, [ip, #120] @ 0x78 @ │ │ strbeq r4, [sp], #-1020 @ 0xfffffc04 │ │ ldc2l 8, cr3, [ip, #736] @ 0x2e0 │ │ - ldc2l 4, cr8, [sl, #240] @ 0xf0 │ │ + ldc2l 4, cr8, [sl, #420] @ 0x1a4 │ │ strbteq r5, [r1], #-1208 @ 0xfffffb48 │ │ strbeq r5, [ip], #-2260 @ 0xfffff72c │ │ - ldc2l 4, cr8, [sl, #16] │ │ + ldc2l 4, cr8, [sl, #196] @ 0xc4 │ │ strbteq r5, [r1], #-1152 @ 0xfffffb80 │ │ - ldc2l 9, cr14, [r9, #24] @ │ │ + ldc2l 9, cr14, [r9, #114] @ 0x72 @ │ │ strbteq fp, [r0], #-1972 @ 0xfffff84c │ │ - ldc2l 8, cr14, [r9, #880] @ 0x370 │ │ + ldc2l 9, cr14, [r9, #18] @ │ │ ldr r1, [pc, #4024] @ 248ce1c │ │ add r0, sp, #137 @ 0x89 │ │ mov r2, #255 @ 0xff │ │ mov r3, #14 │ │ add r1, pc, r1 │ │ mov r8, #255 @ 0xff │ │ bl 270d9e0 │ │ @@ -1381095,26 +1381095,26 @@ │ │ mov r3, #255 @ 0xff │ │ add r0, pc, r0 │ │ bl 270da60 │ │ ldr r0, [pc, #4012] @ 248cffc │ │ add r0, pc, r0 │ │ b 248c724 │ │ strbeq fp, [fp], #-3020 @ 0xfffff434 │ │ - ldc2l 2, cr8, [sl, #996] @ 0x3e4 │ │ + ldc2l 3, cr8, [sl, #152] @ 0x98 │ │ ldr r0, [pc, #4060] @ 248d040 │ │ mov r1, #145 @ 0x91 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #4048] @ 248d044 │ │ mov r1, #10 │ │ add r0, pc, r0 │ │ b 248a914 │ │ - ldc2l 14, cr7, [r9, #500] @ 0x1f4 │ │ + ldc2l 14, cr7, [r9, #680] @ 0x2a8 │ │ strbeq fp, [fp], #-2976 @ 0xfffff460 │ │ - ldc2l 7, cr2, [r9, #80] @ 0x50 │ │ + ldc2l 7, cr2, [r9, #260] @ 0x104 │ │ strbeq fp, [fp], #-2884 @ 0xfffff4bc │ │ strbteq sl, [r1], #-380 @ 0xfffffe84 │ │ strbeq fp, [fp], #-2880 @ 0xfffff4c0 │ │ strbteq fp, [r0], #-1592 @ 0xfffff9c8 │ │ strbteq r5, [r1], #-724 @ 0xfffffd2c │ │ strbteq sl, [r1], #-420 @ 0xfffffe5c │ │ cmp r0, #0 │ │ @@ -1381299,15 +1381299,15 @@ │ │ ldr r1, [r1, r0, lsl #2] │ │ ldr r0, [pc, #3916] @ 248d2c4 │ │ str r1, [fp, #-72] @ 0xffffffb8 │ │ mov r1, r5 │ │ add r0, pc, r0 │ │ b 248bc54 │ │ ldc2l 11, cr11, [fp, #444] @ 0x1bc @ │ │ - ldc2l 14, cr9, [sl, #216] @ 0xd8 │ │ + ldc2l 14, cr9, [sl, #396] @ 0x18c │ │ ldr r0, [pc, #3892] @ 248d2c8 │ │ mov r1, #0 │ │ ldr r2, [fp, #16] │ │ add r0, pc, r0 │ │ str r1, [r2] │ │ mov r1, #59 @ 0x3b │ │ bl 270da00 │ │ @@ -1381326,18 +1381326,18 @@ │ │ mov r1, #53 @ 0x35 │ │ add r0, pc, r0 │ │ b 248c57c │ │ strbeq sl, [ip], #-692 @ 0xfffffd4c │ │ ldc2l 0, cr0, [fp, #648] @ 0x288 │ │ ldc2l 15, cr3, [fp, #884] @ 0x374 │ │ strbeq r5, [ip], #-1116 @ 0xfffffba4 │ │ - ldc2l 2, cr2, [sl, #492] @ 0x1ec │ │ + ldc2l 2, cr2, [sl, #672] @ 0x2a0 │ │ ldc2l 15, cr3, [fp, #612] @ 0x264 │ │ ldc2l 12, cr5, [fp, #756] @ 0x2f4 │ │ - ldc2l 5, cr6, [r9, #60] @ 0x3c │ │ + ldc2l 5, cr6, [r9, #240] @ 0xf0 │ │ ldc2l 0, cr2, [fp, #84] @ 0x54 │ │ ldc2l 14, cr3, [fp, #980] @ 0x3d4 │ │ strbeq sl, [ip], #-408 @ 0xfffffe68 │ │ cmp sl, #0 │ │ beq 248c8b0 │ │ ldr r0, [sp, #124] @ 0x7c │ │ sub r1, r0, #1 │ │ @@ -1381397,26 +1381397,26 @@ │ │ mov r1, r0 │ │ ldr r2, [pc, #3160] @ 248d158 │ │ ldr r0, [pc, #3160] @ 248d15c │ │ add r2, pc, r2 │ │ add r0, pc, r0 │ │ add r1, r2, r1, lsl #3 │ │ b 248cfe4 │ │ - ldc2l 6, cr8, [r9, #516] @ 0x204 │ │ + ldc2l 6, cr8, [r9, #696] @ 0x2b8 │ │ ldc2l 14, cr3, [fp, #788] @ 0x314 │ │ - ldc2l 9, cr7, [r9, #386] @ 0x182 @ │ │ + ldc2l 9, cr7, [r9, #476] @ 0x1dc @ │ │ ldc2l 14, cr13, [r8, #500] @ 0x1f4 │ │ ldc2l 2, cr3, [ip, #528] @ 0x210 │ │ ldc2l 14, cr3, [fp, #404] @ 0x194 │ │ strbeq r3, [sp], #-3384 @ 0xfffff2c8 │ │ - ldc2l 13, cr1, [sl, #800] @ 0x320 │ │ + ldc2l 13, cr1, [sl, #980] @ 0x3d4 │ │ ldc2l 14, cr15, [sl, #848] @ 0x350 │ │ ldc2l 11, cr5, [fp, #676] @ 0x2a4 @ │ │ ldc2l 5, cr9, [fp, #976] @ 0x3d0 │ │ - ldc2l 9, cr7, [sl, #372] @ 0x174 @ │ │ + ldc2l 9, cr7, [sl, #462] @ 0x1ce @ │ │ ldc2l 14, cr13, [sl, #172] @ 0xac │ │ strbeq fp, [fp], #-1552 @ 0xfffff9f0 │ │ strbeq fp, [fp], #-1536 @ 0xfffffa00 │ │ strbteq r9, [r1], #-3404 @ 0xfffff2b4 │ │ strbteq fp, [r0], #-268 @ 0xfffffef4 │ │ ldc2l 0, cr10, [r8, #872] @ 0x368 │ │ ldc2l 13, cr3, [fp, #452] @ 0x1c4 │ │ @@ -1381538,16 +1381538,16 @@ │ │ b 248b5f4 │ │ ldc2l 8, cr7, [fp, #592] @ 0x250 │ │ vcadd.f32 , , q12, #270 │ │ ldc2l 4, cr12, [r8, #728] @ 0x2d8 │ │ strbteq sl, [r0], #-3972 @ 0xfffff07c │ │ ldc2l 4, cr12, [r8, #536] @ 0x218 │ │ strbteq sl, [r0], #-3924 @ 0xfffff0ac │ │ - ldc2l 14, cr1, [sl, #684] @ 0x2ac │ │ - ldc2l 14, cr1, [sl, #524] @ 0x20c │ │ + ldc2l 14, cr1, [sl, #864] @ 0x360 │ │ + ldc2l 14, cr1, [sl, #704] @ 0x2c0 │ │ ldr r0, [pc, #2352] @ 248d084 │ │ mov r1, #83 @ 0x53 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #2340] @ 248d088 │ │ add r1, sp, #137 @ 0x89 │ │ mov r2, #1 │ │ @@ -1381644,15 +1381644,15 @@ │ │ str r4, [r5, r3, lsl #2] │ │ clz r0, r0 │ │ lsr r4, r0, #5 │ │ b 248c938 │ │ ldc2l 11, cr3, [fp, #20] @ │ │ ldc2l 14, cr9, [r8, #152] @ 0x98 │ │ ldc2l 10, cr3, [fp, #756] @ 0x2f4 @ │ │ - ldc2l 10, cr1, [sl, #916] @ 0x394 @ │ │ + ldc2l 11, cr1, [sl, #72] @ 0x48 @ │ │ ldc2l 5, cr1, [fp, #756] @ 0x2f4 │ │ strbteq r9, [r1], #-2464 @ 0xfffff660 │ │ ldr r0, [pc, #2240] @ 248d1c0 │ │ mov r1, r3 │ │ ldr r2, [pc, #2236] @ 248d1c4 │ │ movw r3, #1367 @ 0x557 │ │ add r0, pc, r0 │ │ @@ -1381742,20 +1381742,20 @@ │ │ str r1, [fp, #-48] @ 0xffffffd0 │ │ bhi 248ca98 │ │ ldr r0, [pc, #2016] @ 248d248 │ │ str r1, [fp, #-48] @ 0xffffffd0 │ │ add r0, pc, r0 │ │ str r4, [r0, r1, lsl #2] │ │ b 248caf4 │ │ - ldc2l 12, cr1, [sl, #124] @ 0x7c │ │ + ldc2l 12, cr1, [sl, #304] @ 0x130 │ │ ldc2l 9, cr3, [fp, #122] @ 0x7a @ │ │ ldc2l 12, cr9, [r8, #440] @ 0x1b8 │ │ ldc2l 9, cr3, [fp, #10] @ │ │ strbteq r9, [r1], #-2000 @ 0xfffff830 │ │ - ldc2l 15, cr9, [r9, #132] @ 0x84 │ │ + ldc2l 15, cr9, [r9, #312] @ 0x138 │ │ ldc2l 9, cr15, [sl, #236] @ 0xec @ │ │ ldc2l 8, cr3, [fp, #724] @ 0x2d4 │ │ strbeq r4, [ip], #-3384 @ 0xfffff2c8 │ │ ldr r0, [pc, #1964] @ 248d24c │ │ movw r3, #1398 @ 0x576 │ │ ldr r2, [pc, #1960] @ 248d250 │ │ add r0, pc, r0 │ │ @@ -1381824,15 +1381824,15 @@ │ │ add r0, pc, r0 │ │ str r1, [fp, #-48] @ 0xffffffd0 │ │ add r0, r0, r1, lsl #3 │ │ vstr d8, [r0] │ │ b 248cd94 │ │ strbteq r9, [r1], #-1812 @ 0xfffff8ec │ │ strbteq r4, [r1], #-2172 @ 0xfffff784 │ │ - ldc2l 7, cr7, [sl, #640] @ 0x280 │ │ + ldc2l 7, cr7, [sl, #820] @ 0x334 │ │ ldc2l 7, cr3, [fp, #788] @ 0x314 │ │ strbteq r4, [r1], #-2064 @ 0xfffff7f0 │ │ ldr r0, [pc, #1540] @ 248d1d4 │ │ mov r1, r3 │ │ ldr r2, [pc, #1536] @ 248d1d8 │ │ movw r3, #1373 @ 0x55d │ │ add r0, pc, r0 │ │ @@ -1381867,15 +1381867,15 @@ │ │ ldc2l 2, cr1, [fp, #644] @ 0x284 │ │ ldc2l 4, cr15, [sl, #1012] @ 0x3f4 │ │ strbeq r3, [sp], #-1632 @ 0xfffff9a0 │ │ strbeq sl, [fp], #-3952 @ 0xfffff090 │ │ strbteq r9, [r1], #-1452 @ 0xfffffa54 │ │ strbteq sl, [r0], #-2696 @ 0xfffff578 │ │ strbteq r9, [r1], #-1532 @ 0xfffffa04 │ │ - ldc2l 12, cr13, [r9, #104] @ 0x68 │ │ + ldc2l 12, cr13, [r9, #284] @ 0x11c │ │ ldc2l 10, cr2, [ip, #960] @ 0x3c0 @ │ │ ldc2l 6, cr3, [fp, #836] @ 0x344 │ │ ldr r0, [pc, #1424] @ 248d20c │ │ movw r3, #1390 @ 0x56e │ │ ldr r2, [pc, #1420] @ 248d210 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1381912,15 +1381912,15 @@ │ │ mov r3, #1392 @ 0x570 │ │ ldr r2, [pc, #1320] @ 248d234 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 248ca04 │ │ - ldc2l 1, cr7, [r9, #820] @ 0x334 │ │ + ldc2l 1, cr7, [r9, #1000] @ 0x3e8 │ │ strbeq r3, [sp], #-1436 @ 0xfffffa64 │ │ ldc2l 6, cr3, [fp, #588] @ 0x24c │ │ ldc2l 7, cr14, [fp, #644] @ 0x284 │ │ ldc2l 6, cr3, [fp, #308] @ 0x134 │ │ ldr r0, [pc, #1356] @ 248d284 │ │ movw r3, #1401 @ 0x579 │ │ ldr r2, [pc, #1352] @ 248d288 │ │ @@ -1381977,17 +1381977,17 @@ │ │ bl 270da30 │ │ mov r8, r0 │ │ ldr r1, [sl, r8, lsl #2] │ │ ldr r0, [pc, #736] @ 248d0f8 │ │ add r0, pc, r0 │ │ b 2489e18 │ │ ldc2l 5, cr3, [fp, #620] @ 0x26c │ │ - ldc2l 13, cr7, [r9, #4] │ │ + ldc2l 13, cr7, [r9, #184] @ 0xb8 │ │ ldc2l 5, cr3, [fp, #276] @ 0x114 │ │ - ldc2l 0, cr7, [r9, #212] @ 0xd4 │ │ + ldc2l 0, cr7, [r9, #392] @ 0x188 │ │ strbteq r9, [r1], #-1168 @ 0xfffffb70 │ │ ldr r0, [pc, #660] @ 248d0cc │ │ mov r1, #90 @ 0x5a │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r7, [pc, #648] @ 248d0d0 │ │ add r1, sp, #137 @ 0x89 │ │ @@ -1382041,17 +1382041,17 @@ │ │ ldc2l 8, cr9, [r8, #248] @ 0xf8 │ │ ldc2l 4, cr3, [fp, #852] @ 0x354 │ │ ldr r0, [pc, #588] @ 248d160 │ │ mov r1, #195 @ 0xc3 │ │ add r0, pc, r0 │ │ b 248d00c │ │ ldc2l 4, cr3, [fp, #476] @ 0x1dc │ │ - ldc2l 11, cr7, [r9, #900] @ 0x384 @ │ │ + ldc2l 12, cr7, [r9, #56] @ 0x38 │ │ ldc2l 4, cr3, [fp, #148] @ 0x94 │ │ - ldc2l 15, cr6, [r9, #116] @ 0x74 │ │ + ldc2l 15, cr6, [r9, #296] @ 0x128 │ │ ldr r0, [pc, #564] @ 248d168 │ │ mov r1, #241 @ 0xf1 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #552] @ 248d16c │ │ add r1, sp, #137 @ 0x89 │ │ mov r2, #1 │ │ @@ -1382095,15 +1382095,15 @@ │ │ add r1, r4, r1, lsl #3 │ │ add r0, pc, r0 │ │ mov r2, #1 │ │ mov r3, #8 │ │ b 248d024 │ │ strbteq r9, [r1], #-884 @ 0xfffffc8c │ │ ldc2l 4, cr13, [sl, #32] │ │ - ldc2l 14, cr6, [r9, #772] @ 0x304 │ │ + ldc2l 14, cr6, [r9, #952] @ 0x3b8 │ │ ldc2l 10, cr11, [r8, #740] @ 0x2e4 @ │ │ ldr r0, [pc, #260] @ 248d10c │ │ mov r1, #194 @ 0xc2 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #248] @ 248d110 │ │ add r1, sp, #137 @ 0x89 │ │ @@ -1382113,98 +1382113,98 @@ │ │ bl 270da60 │ │ ldr r0, [pc, #352] @ 248d190 │ │ mov r1, #21 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ mov r6, r8 │ │ b 248c604 │ │ - ldc2l 6, cr3, [sl, #668] @ 0x29c │ │ + ldc2l 6, cr3, [sl, #848] @ 0x350 │ │ ldc2l 0, cr3, [fp, #428] @ 0x1ac │ │ ldc2l 11, cr11, [r8, #88] @ 0x58 @ │ │ ldc2l 2, cr3, [fp, #548] @ 0x224 │ │ - ldc2l 5, cr1, [sl, #220] @ 0xdc │ │ + ldc2l 5, cr1, [sl, #400] @ 0x190 │ │ ldc2l 2, cr3, [fp, #340] @ 0x154 │ │ strbteq r9, [r1], #-188 @ 0xffffff44 │ │ strbeq sl, [fp], #-2660 @ 0xfffff59c │ │ strbeq sl, [fp], #-2652 @ 0xfffff5a4 │ │ ldc2l 2, cr3, [fp, #200] @ 0xc8 │ │ ldc2l 13, cr0, [fp, #960] @ 0x3c0 │ │ - vcadd.f32 d22, d9, d1, #270 │ │ + vcadd.f32 d22, d9, d30, #270 │ │ ldc2l 4, cr14, [fp, #160] @ 0xa0 │ │ strbeq sl, [fp], #-2916 @ 0xfffff49c │ │ strbeq pc, [fp], #-2448 @ 0xfffff670 @ │ │ ldc2l 4, cr1, [fp, #20] │ │ ldc2l 2, cr3, [fp, #916] @ 0x394 │ │ - ldc2l 15, cr2, [sl, #396] @ 0x18c │ │ - ldc2l 7, cr6, [r9, #596] @ 0x254 │ │ - ldc2l 4, cr7, [r9, #52] @ 0x34 │ │ + ldc2l 15, cr2, [sl, #576] @ 0x240 │ │ + ldc2l 7, cr6, [r9, #776] @ 0x308 │ │ + ldc2l 4, cr7, [r9, #232] @ 0xe8 │ │ ldc2l 12, cr2, [fp, #324] @ 0x144 │ │ - ldc2l 7, cr6, [r9, #324] @ 0x144 │ │ + ldc2l 7, cr6, [r9, #504] @ 0x1f8 │ │ strbteq r8, [r1], #-2996 @ 0xfffff44c │ │ ldc2l 13, cr0, [fp, #132] @ 0x84 │ │ ldc2l 12, cr2, [fp, #4] │ │ - ldc2l 3, cr7, [r9, #580] @ 0x244 │ │ + ldc2l 3, cr7, [r9, #760] @ 0x2f8 │ │ ldc2l 11, cr2, [fp, #852] @ 0x354 @ │ │ - ldc2l 6, cr6, [r9, #852] @ 0x354 │ │ + ldc2l 7, cr6, [r9, #8] │ │ strbteq r8, [r1], #-2872 @ 0xfffff4c8 │ │ ldc2l 12, cr14, [sl, #288] @ 0x120 │ │ - ldc2l 0, cr13, [r9, #508] @ 0x1fc │ │ - ldc2l 6, cr6, [r9, #548] @ 0x224 │ │ + ldc2l 0, cr13, [r9, #688] @ 0x2b0 │ │ + ldc2l 6, cr6, [r9, #728] @ 0x2d8 │ │ ldc2l 11, cr12, [sl, #788] @ 0x314 @ │ │ ldc2l 6, cr14, [sl, #856] @ 0x358 │ │ ldc2l 6, cr2, [fp, #84] @ 0x54 │ │ ldc2l 9, cr1, [ip, #226] @ 0xe2 @ │ │ - ldc2l 0, cr6, [r9, #708] @ 0x2c4 │ │ + ldc2l 0, cr6, [r9, #888] @ 0x378 │ │ strbteq r8, [r1], #-1244 @ 0xfffffb24 │ │ ldc2l 6, cr14, [sl, #24] │ │ ldc2l 5, cr2, [fp, #276] @ 0x114 │ │ ldc2l 6, cr3, [ip, #960] @ 0x3c0 │ │ ldc2l 5, cr2, [fp, #100] @ 0x64 │ │ - ldc2l 0, cr6, [r9, #84] @ 0x54 │ │ - ldc2l 11, cr2, [r9, #276] @ 0x114 @ │ │ + ldc2l 0, cr6, [r9, #264] @ 0x108 │ │ + ldc2l 11, cr2, [r9, #456] @ 0x1c8 @ │ │ ldc2l 7, cr13, [fp, #260] @ 0x104 │ │ ldc2l 5, cr2, [fp, #932] @ 0x3a4 │ │ ldc2l 6, cr12, [sl, #76] @ 0x4c │ │ ldc2l 3, cr9, [r8, #88] @ 0x58 │ │ ldc2l 15, cr2, [fp, #692] @ 0x2b4 │ │ strbteq r8, [r1], #-3848 @ 0xfffff0f8 │ │ strbteq r8, [r1], #-3828 @ 0xfffff10c │ │ - ldc2l 7, cr0, [r9, #792] @ 0x318 │ │ - ldc2l 14, cr5, [r9, #900] @ 0x384 │ │ + ldc2l 7, cr0, [r9, #972] @ 0x3cc │ │ + ldc2l 15, cr5, [r9, #56] @ 0x38 │ │ ldc2l 12, cr0, [fp, #772] @ 0x304 │ │ ldc2l 15, cr14, [sl, #84] @ 0x54 │ │ ldc2l 5, cr9, [r8, #104] @ 0x68 │ │ ldc2l 1, cr3, [fp, #708] @ 0x2c4 │ │ ldc2l 10, cr10, [fp, #916] @ 0x394 @ │ │ - ldc2l 4, cr11, [r9, #348] @ 0x15c │ │ - ldc2l 13, cr0, [sl, #880] @ 0x370 │ │ + ldc2l 4, cr11, [r9, #528] @ 0x210 │ │ + ldc2l 14, cr0, [sl, #36] @ 0x24 │ │ ldc2l 0, cr4, [ip, #16] │ │ ldc2l 14, cr2, [fp, #180] @ 0xb4 │ │ ldc2l 13, cr12, [r8, #1012] @ 0x3f4 │ │ - ldc2l 9, cr6, [r9, #42] @ 0x2a @ │ │ + ldc2l 9, cr6, [r9, #132] @ 0x84 @ │ │ ldc2l 13, cr2, [fp, #988] @ 0x3dc │ │ strbeq sl, [fp], #-880 @ 0xfffffc90 │ │ - ldc2l 5, cr15, [r9, #656] @ 0x290 │ │ - ldc2l 10, cr6, [r9, #260] @ 0x104 @ │ │ + ldc2l 5, cr15, [r9, #836] @ 0x344 │ │ + ldc2l 10, cr6, [r9, #440] @ 0x1b8 @ │ │ ldc2l 12, cr4, [fp, #520] @ 0x208 │ │ ldc2l 14, cr2, [fp, #1012] @ 0x3f4 │ │ strbteq r8, [r1], #-3624 @ 0xfffff1d8 │ │ - ldc2l 9, cr6, [r9, #506] @ 0x1fa @ │ │ - ldc2l 10, cr10, [r9, #992] @ 0x3e0 @ │ │ + ldc2l 10, cr6, [r9, #168] @ 0xa8 @ │ │ + ldc2l 11, cr10, [r9, #148] @ 0x94 @ │ │ strbteq r8, [r1], #-2688 @ 0xfffff580 │ │ ldc2l 15, cr5, [fp, #856] @ 0x358 │ │ - ldc2l 15, cr5, [r9, #724] @ 0x2d4 │ │ + ldc2l 15, cr5, [r9, #904] @ 0x388 │ │ ldc2l 1, cr4, [fp, #984] @ 0x3d8 │ │ ldc2l 4, cr2, [fp, #452] @ 0x1c4 │ │ strbteq r8, [r1], #-916 @ 0xfffffc6c │ │ - ldc2l 15, cr5, [r9, #420] @ 0x1a4 │ │ + ldc2l 15, cr5, [r9, #600] @ 0x258 │ │ strbteq r8, [r1], #-892 @ 0xfffffc84 │ │ ldc2l 1, cr4, [fp, #648] @ 0x288 │ │ ldc2l 4, cr2, [fp, #116] @ 0x74 │ │ - ldc2l 15, cr5, [r9, #132] @ 0x84 │ │ + ldc2l 15, cr5, [r9, #312] @ 0x138 │ │ ldc2l 6, cr9, [fp, #396] @ 0x18c │ │ ldc2l 15, cr1, [ip, #320] @ 0x140 │ │ ldc2l 1, cr9, [r8, #56] @ 0x38 │ │ ldc2l 13, cr2, [fp, #644] @ 0x284 │ │ strbeq sl, [fp], #-1488 @ 0xfffffa30 │ │ strbteq r3, [r1], #-3468 @ 0xfffff274 │ │ strbeq sl, [fp], #-1440 @ 0xfffffa60 │ │ @@ -1382214,38 +1382214,38 @@ │ │ strbeq sl, [fp], #-1404 @ 0xfffffa84 │ │ strbeq sl, [fp], #-1392 @ 0xfffffa90 │ │ ldc2l 6, cr6, [fp, #976] @ 0x3d0 │ │ ldc2l 10, cr2, [fp, #884] @ 0x374 @ │ │ strbteq r3, [r1], #-2736 @ 0xfffff550 │ │ strbeq sl, [fp], #-740 @ 0xfffffd1c │ │ strbeq sl, [fp], #-728 @ 0xfffffd28 │ │ - ldc2l 10, cr0, [sl, #956] @ 0x3bc @ │ │ + ldc2l 11, cr0, [sl, #112] @ 0x70 @ │ │ vcadd.f32 d18, d11, d13, #270 │ │ strbeq sl, [fp], #-56 @ 0xffffffc8 │ │ strbteq r3, [r1], #-2040 @ 0xfffff808 │ │ strbeq sl, [fp], #-32 @ 0xffffffe0 │ │ ldc2l 0, cr11, [r8, #296] @ 0x128 │ │ ldc2l 7, cr2, [fp, #756] @ 0x2f4 │ │ strbeq r9, [fp], #-4076 @ 0xfffff014 │ │ strbeq pc, [fp], #-216 @ 0xffffff28 @ │ │ - ldc2l 13, cr0, [sl, #116] @ 0x74 │ │ + ldc2l 13, cr0, [sl, #296] @ 0x128 │ │ ldc2l 10, cr2, [fp, #212] @ 0xd4 @ │ │ strbeq pc, [fp], #-152 @ 0xffffff68 @ │ │ strbeq sl, [fp], #-604 @ 0xfffffda4 │ │ strbeq r3, [ip], #-3728 @ 0xfffff170 │ │ vcadd.f32 d30, d10, d22, #270 │ │ ldc2l 7, cr2, [fp, #404] @ 0x194 │ │ strbeq r3, [ip], #-3044 @ 0xfffff41c │ │ strbeq r9, [fp], #-3976 @ 0xfffff078 │ │ strbeq r8, [ip], #-3232 @ 0xfffff360 │ │ vcadd.f32 q8, , , #270 │ │ ldc2l 7, cr2, [fp, #132] @ 0x84 │ │ strbeq r8, [ip], #-2496 @ 0xfffff640 │ │ strbeq r9, [fp], #-3908 @ 0xfffff0bc │ │ - ldc2l 4, cr8, [sl, #444] @ 0x1bc │ │ + ldc2l 4, cr8, [sl, #624] @ 0x270 │ │ ldc2l 6, cr2, [fp, #884] @ 0x374 │ │ strbeq sl, [fp], #-552 @ 0xfffffdd8 │ │ ldc2l 2, cr11, [r8, #264] @ 0x108 │ │ ldc2l 9, cr2, [fp, #362] @ 0x16a @ │ │ strbeq sl, [fp], #-484 @ 0xfffffe1c │ │ strbeq sp, [ip], #-2640 @ 0xfffff5b0 │ │ ldc2l 10, cr13, [fp, #596] @ 0x254 @ │ │ @@ -1382253,37 +1382253,37 @@ │ │ strbeq sp, [ip], #-2564 @ 0xfffff5fc │ │ strbeq sl, [fp], #-360 @ 0xfffffe98 │ │ ldc2l 13, cr1, [ip, #128] @ 0x80 │ │ ldc2l 9, cr2, [fp, #2] @ │ │ strbeq r2, [sp], #-2004 @ 0xfffff82c │ │ strbeq sl, [fp], #-264 @ 0xfffffef8 │ │ strbteq r3, [r1], #-2320 @ 0xfffff6f0 │ │ - ldc2l 8, cr6, [sl, #368] @ 0x170 │ │ + vcadd.f32 d22, d26, d9, #270 │ │ vcadd.f32 d18, d27, d1, #270 │ │ strbteq r3, [r1], #-2260 @ 0xfffff72c │ │ strbeq sl, [fp], #-164 @ 0xffffff5c │ │ strbteq r9, [r0], #-3088 @ 0xfffff3f0 │ │ - ldc2l 11, cr12, [r9, #752] @ 0x2f0 @ │ │ + ldc2l 11, cr12, [r9, #932] @ 0x3a4 @ │ │ ldc2l 6, cr2, [fp, #676] @ 0x2a4 │ │ strbteq r9, [r0], #-2660 @ 0xfffff59c │ │ strbeq r9, [fp], #-3788 @ 0xfffff134 │ │ ldc2l 7, cr13, [fp, #740] @ 0x2e4 │ │ ldc2l 6, cr2, [fp, #404] @ 0x194 │ │ strbeq sp, [ip], #-1824 @ 0xfffff8e0 │ │ ldc2l 6, cr12, [sl, #508] @ 0x1fc │ │ ldc2l 1, cr15, [sl, #872] @ 0x368 │ │ ldc2l 1, cr3, [fp, #84] @ 0x54 │ │ ldc2l 4, cr9, [r8, #248] @ 0xf8 │ │ ldc2l 0, cr3, [fp, #852] @ 0x354 │ │ strbteq r8, [r1], #-4004 @ 0xfffff05c │ │ - ldc2l 0, cr7, [sl, #464] @ 0x1d0 │ │ + ldc2l 0, cr7, [sl, #644] @ 0x284 │ │ ldc2l 0, cr3, [fp, #612] @ 0x264 │ │ strbteq r4, [r1], #-228 @ 0xffffff1c │ │ ldc2l 4, cr2, [ip, #544] @ 0x220 │ │ - ldc2l 4, cr1, [r9, #996] @ 0x3e4 │ │ + ldc2l 5, cr1, [r9, #152] @ 0x98 │ │ ldc2l 13, cr2, [fp, #188] @ 0xbc │ │ │ │ 0248d2d0 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ @@ -1382300,15 +1382300,15 @@ │ │ add r0, pc, r0 │ │ bl 270da10 │ │ mov r0, r4 │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, sl, fp, pc} │ │ - ldc2l 3, cr0, [sl, #808] @ 0x328 │ │ + ldc2l 3, cr0, [sl, #988] @ 0x3dc │ │ ldc2l 1, cr13, [fp, #776] @ 0x308 │ │ │ │ 0248d32c : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #48 @ 0x30 │ │ mov ip, r0 │ │ @@ -1382685,27 +1382685,27 @@ │ │ mov r0, r4 │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 5, cr13, [fp, #112] @ 0x70 │ │ - ldc2l 14, cr1, [sl, #416] @ 0x1a0 │ │ + ldc2l 14, cr1, [sl, #596] @ 0x254 │ │ ldc2l 12, cr5, [r8, #224] @ 0xe0 │ │ - ldc2l 10, cr15, [r8, #60] @ 0x3c @ │ │ + ldc2l 10, cr15, [r8, #240] @ 0xf0 @ │ │ eoreq fp, ip, r8, lsr #28 │ │ - ldc2l 0, cr12, [r9, #776] @ 0x308 │ │ - ldc2l 13, cr1, [sl, #688] @ 0x2b0 │ │ - ldc2l 6, cr5, [r9, #340] @ 0x154 │ │ + ldc2l 0, cr12, [r9, #956] @ 0x3bc │ │ + ldc2l 13, cr1, [sl, #868] @ 0x364 │ │ + ldc2l 6, cr5, [r9, #520] @ 0x208 │ │ vcadd.f32 d17, d11, d19, #270 │ │ ldc2l 6, cr11, [fp, #752] @ 0x2f0 │ │ ldc2l 6, cr9, [r8, #572] @ 0x23c │ │ ldrdeq fp, [ip], -r0 @ │ │ - ldc2l 0, cr12, [r9, #1000] @ 0x3e8 │ │ - ldc2l 1, cr8, [r9, #856] @ 0x358 │ │ + ldc2l 1, cr12, [r9, #156] @ 0x9c │ │ + ldc2l 2, cr8, [r9, #12] │ │ │ │ 0248d914 : │ │ ldr r2, [r1] │ │ cmp r2, #1 │ │ movlt r0, #0 │ │ bxlt lr │ │ push {fp, lr} │ │ @@ -1383103,23 +1383103,23 @@ │ │ ldr r0, [pc, #60] @ 248df80 │ │ add r0, pc, r0 │ │ b 248dab0 │ │ ldc2l 11, cr13, [sl, #232] @ 0xe8 @ │ │ ldc2l 4, cr9, [r8, #252] @ 0xfc │ │ ldc2l 10, cr13, [sl, #152] @ 0x98 @ │ │ ldc2l 13, cr0, [ip, #408] @ 0x198 │ │ - ldc2l 4, cr5, [r9, #244] @ 0xf4 │ │ + ldc2l 4, cr5, [r9, #424] @ 0x1a8 │ │ ldc2l 4, cr5, [r8, #156] @ 0x9c │ │ ldc2l 9, cr13, [sl, #220] @ 0xdc @ │ │ ldc2l 9, cr13, [sl, #76] @ 0x4c @ │ │ ldc2l 9, cr13, [sl, #276] @ 0x114 @ │ │ ldc2l 2, cr15, [sl, #1012] @ 0x3f4 │ │ ldc2l 5, cr13, [sl, #212] @ 0xd4 │ │ - ldc2l 13, cr7, [r9, #996] @ 0x3e4 │ │ - ldc2l 2, cr5, [r9, #180] @ 0xb4 │ │ + ldc2l 14, cr7, [r9, #152] @ 0x98 │ │ + ldc2l 2, cr5, [r9, #360] @ 0x168 │ │ ldc2l 0, cr11, [sl, #964] @ 0x3c4 │ │ vcadd.f32 q8, q14, q5, #270 │ │ ldc2l 10, cr13, [sl, #248] @ 0xf8 @ │ │ │ │ 0248df88 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -1383277,21 +1383277,21 @@ │ │ sub r0, fp, #40 @ 0x28 │ │ str r1, [fp, #-40] @ 0xffffffd8 │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ bl 270d1d0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 7, cr11, [r9, #844] @ 0x34c │ │ + vcadd.f32 d27, d9, d0, #270 │ │ ldc2l 15, cr2, [fp, #920] @ 0x398 │ │ ldc2l 15, cr0, [fp, #236] @ 0xec │ │ - ldc2l 9, cr1, [r9, #446] @ 0x1be @ │ │ - ldc2l 4, cr3, [sl, #264] @ 0x108 │ │ - ldc2l 9, cr1, [r9, #358] @ 0x166 @ │ │ - ldc2l 4, cr3, [sl, #88] @ 0x58 │ │ + ldc2l 10, cr1, [r9, #48] @ 0x30 @ │ │ + ldc2l 4, cr3, [sl, #444] @ 0x1bc │ │ + ldc2l 9, cr1, [r9, #448] @ 0x1c0 @ │ │ + ldc2l 4, cr3, [sl, #268] @ 0x10c │ │ │ │ 0248e224 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ vpush {d8} │ │ sub sp, sp, #288 @ 0x120 │ │ mov r7, r0 │ │ @@ -1383629,26 +1383629,26 @@ │ │ strbteq r7, [r1], #-304 @ 0xfffffed0 │ │ strbteq r7, [r1], #-272 @ 0xfffffef0 │ │ strbteq r7, [r1], #-268 @ 0xfffffef4 │ │ strbteq r7, [r1], #-280 @ 0xfffffee8 │ │ ldrdeq fp, [ip], -r0 @ │ │ eoreq fp, ip, ip, ror #5 │ │ ldrdeq fp, [ip], -r4 @ │ │ - ldc2l 14, cr12, [r9, #976] @ 0x3d0 │ │ + ldc2l 15, cr12, [r9, #132] @ 0x84 │ │ strhteq fp, [ip], -ip │ │ strbteq r6, [r1], #-3652 @ 0xfffff1bc │ │ strbteq r6, [r1], #-3300 @ 0xfffff31c │ │ strbteq r6, [r1], #-3280 @ 0xfffff330 │ │ eoreq sl, ip, r8, asr #29 │ │ ldrdeq sl, [ip], -r0 @ │ │ strhteq sl, [ip], -r4 │ │ mlaeq ip, r4, lr, sl │ │ eoreq sl, ip, r0, ror pc │ │ eoreq sl, ip, ip, asr pc │ │ - ldc2l 1, cr1, [r9, #120] @ 0x78 │ │ + ldc2l 1, cr1, [r9, #300] @ 0x12c │ │ ldc2l 6, cr6, [fp, #944] @ 0x3b0 │ │ │ │ 0248e7b4 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ mov r8, r0 │ │ @@ -1383757,21 +1383757,21 @@ │ │ bl 270ceb0 │ │ b 248e90c │ │ strbteq r6, [r1], #-3032 @ 0xfffff428 │ │ ldc2l 11, cr4, [r8, #964] @ 0x3c4 @ │ │ ldc2l 11, cr4, [r8, #128] @ 0x80 @ │ │ strbteq r6, [r1], #-2972 @ 0xfffff464 │ │ ldc2l 9, cr2, [fp, #156] @ 0x9c @ │ │ - ldc2l 1, cr11, [r9, #208] @ 0xd0 │ │ - ldc2l 8, cr14, [r8, #764] @ 0x2fc │ │ + ldc2l 1, cr11, [r9, #388] @ 0x184 │ │ + vcadd.f32 q15, q12, q14, #270 │ │ eoreq sl, ip, ip, lsl sp │ │ strbteq r6, [r1], #-2800 @ 0xfffff510 │ │ strbteq r6, [r1], #-2780 @ 0xfffff524 │ │ - ldc2l 13, cr0, [sl, #128] @ 0x80 │ │ - ldc2l 5, cr4, [r9, #804] @ 0x324 │ │ + ldc2l 13, cr0, [sl, #308] @ 0x134 │ │ + ldc2l 5, cr4, [r9, #984] @ 0x3d8 │ │ ldc2l 7, cr0, [fp, #604] @ 0x25c │ │ ldc2l 10, cr4, [r8, #548] @ 0x224 @ │ │ ldc2l 10, cr4, [r8, #980] @ 0x3d4 @ │ │ strbteq r6, [r1], #-2748 @ 0xfffff544 │ │ strbteq r6, [r1], #-2732 @ 0xfffff554 │ │ │ │ 0248e9a8 : │ │ @@ -1384279,70 +1384279,70 @@ │ │ mov r0, #2 │ │ b 248f0bc │ │ ldc2l 10, cr0, [fp, #268] @ 0x10c @ │ │ strbteq r6, [r1], #-2540 @ 0xfffff614 │ │ ldc2l 9, cr4, [r8, #48] @ 0x30 @ │ │ strbteq r6, [r1], #-2524 @ 0xfffff624 │ │ ldc2l 7, cr2, [fp, #280] @ 0x118 │ │ - ldc2l 12, cr14, [r9, #684] @ 0x2ac │ │ - ldc2l 10, cr0, [sl, #480] @ 0x1e0 @ │ │ + ldc2l 12, cr14, [r9, #864] @ 0x360 │ │ + ldc2l 10, cr0, [sl, #660] @ 0x294 @ │ │ strbteq r6, [r1], #-2372 @ 0xfffff6bc │ │ - ldc2l 0, cr5, [r9, #980] @ 0x3d4 │ │ - ldc2l 12, cr14, [r9, #140] @ 0x8c │ │ + ldc2l 1, cr5, [r9, #136] @ 0x88 │ │ + ldc2l 12, cr14, [r9, #320] @ 0x140 │ │ strbteq r6, [r1], #-2234 @ 0xfffff746 │ │ strbteq r6, [r1], #-2242 @ 0xfffff73e │ │ strbteq r6, [r1], #-2300 @ 0xfffff704 │ │ strbteq r6, [r1], #-2213 @ 0xfffff75b │ │ strbteq r6, [r1], #-2164 @ 0xfffff78c │ │ - ldc2l 12, cr0, [sl, #52] @ 0x34 │ │ - ldc2l 3, cr4, [r9, #372] @ 0x174 │ │ - ldc2l 15, cr6, [r9, #228] @ 0xe4 │ │ + ldc2l 12, cr0, [sl, #232] @ 0xe8 │ │ + ldc2l 3, cr4, [r9, #552] @ 0x228 │ │ + ldc2l 15, cr6, [r9, #408] @ 0x198 │ │ eoreq sl, ip, r8, lsl sl │ │ eoreq sl, ip, ip, lsl sl │ │ - ldc2l 15, cr12, [r9, #180] @ 0xb4 │ │ - ldc2l 2, cr4, [r9, #836] @ 0x344 │ │ - ldc2l 7, cr2, [r9, #620] @ 0x26c │ │ + ldc2l 15, cr12, [r9, #360] @ 0x168 │ │ + ldc2l 2, cr4, [r9, #1016] @ 0x3f8 │ │ + ldc2l 7, cr2, [r9, #800] @ 0x320 │ │ eoreq sl, ip, r4, asr r9 │ │ strbteq r6, [r1], #-1840 @ 0xfffff8d0 │ │ - ldc2l 4, cr8, [sl, #824] @ 0x338 │ │ - ldc2l 1, cr4, [r9, #372] @ 0x174 │ │ - ldc2l 10, cr0, [sl, #192] @ 0xc0 @ │ │ - ldc2l 13, cr4, [r9, #756] @ 0x2f4 │ │ - vcadd.f32 q15, , , #270 │ │ - ldc2l 0, cr4, [r9, #1012] @ 0x3f4 │ │ - ldc2l 5, cr14, [r9, #352] @ 0x160 │ │ - ldc2l 13, cr4, [r9, #404] @ 0x194 │ │ - ldc2l 8, cr14, [r9, #588] @ 0x24c │ │ + ldc2l 4, cr8, [sl, #1004] @ 0x3ec │ │ + ldc2l 1, cr4, [r9, #552] @ 0x228 │ │ + ldc2l 10, cr0, [sl, #372] @ 0x174 @ │ │ + ldc2l 13, cr4, [r9, #936] @ 0x3a8 │ │ + ldc2l 9, cr14, [r9, #48] @ 0x30 @ │ │ + ldc2l 1, cr4, [r9, #168] @ 0xa8 │ │ + ldc2l 5, cr14, [r9, #532] @ 0x214 │ │ + ldc2l 13, cr4, [r9, #584] @ 0x248 │ │ + vcadd.f32 q15, , q0, #270 │ │ ldc2l 5, cr10, [r8, #484] @ 0x1e4 │ │ - ldc2l 6, cr2, [sl, #784] @ 0x310 │ │ + ldc2l 6, cr2, [sl, #964] @ 0x3c4 │ │ ldc2l 7, cr0, [fp, #748] @ 0x2ec │ │ - ldc2l 14, cr12, [r9, #504] @ 0x1f8 │ │ - ldc2l 14, cr4, [r9, #436] @ 0x1b4 │ │ - ldc2l 9, cr14, [r9, #310] @ 0x136 @ │ │ - ldc2l 6, cr14, [r9, #112] @ 0x70 │ │ - ldc2l 1, cr4, [r9, #612] @ 0x264 │ │ + ldc2l 14, cr12, [r9, #684] @ 0x2ac │ │ + ldc2l 14, cr4, [r9, #616] @ 0x268 │ │ + ldc2l 9, cr14, [r9, #400] @ 0x190 @ │ │ + ldc2l 6, cr14, [r9, #292] @ 0x124 │ │ + ldc2l 1, cr4, [r9, #792] @ 0x318 │ │ ldc2l 2, cr8, [fp, #12] │ │ strbteq r6, [r1], #-1378 @ 0xfffffa9e │ │ eoreq sl, ip, r8, ror r7 │ │ eoreq sl, ip, r4, lsr #14 │ │ strbteq r6, [r1], #-1296 @ 0xfffffaf0 │ │ - ldc2l 6, cr2, [sl, #204] @ 0xcc │ │ - ldc2l 15, cr3, [r9, #868] @ 0x364 │ │ - ldc2l 1, cr14, [r8, #844] @ 0x34c │ │ + ldc2l 6, cr2, [sl, #384] @ 0x180 │ │ + ldc2l 0, cr4, [r9, #24] │ │ + ldc2l 2, cr14, [r8] │ │ eoreq sl, ip, r8, ror #12 │ │ strbteq r6, [r1], #-1100 @ 0xfffffbb4 │ │ - ldc2l 6, cr2, [sl, #12] │ │ + ldc2l 6, cr2, [sl, #192] @ 0xc0 │ │ ldc2l 1, cr0, [fp, #12] │ │ strhteq sl, [ip], -ip │ │ mlaeq ip, r0, r5, sl │ │ ldc2l 14, cr7, [fp, #924] @ 0x39c │ │ ldc2l 11, cr8, [r8, #112] @ 0x70 @ │ │ - ldc2l 13, cr3, [r9, #580] @ 0x244 │ │ + ldc2l 13, cr3, [r9, #760] @ 0x2f8 │ │ ldc2l 5, cr10, [sl, #84] @ 0x54 │ │ - ldc2l 8, cr10, [r9, #104] @ 0x68 │ │ + vcadd.f32 q13, , , #270 │ │ │ │ 0248f278 : │ │ ldrb ip, [r0] │ │ ldrb r0, [r0, #1] │ │ and r3, ip, #240 @ 0xf0 │ │ cmp r3, #128 @ 0x80 │ │ andseq r3, r0, #15 │ │ @@ -1384621,18 +1384621,18 @@ │ │ ldr r2, [sp, #32] │ │ ldr ip, [fp, #12] │ │ ldr r7, [fp, #8] │ │ b 248f554 │ │ ldr r2, [sp, #32] │ │ ldr r7, [fp, #8] │ │ b 248f554 │ │ - ldc2l 7, cr8, [r9, #240] @ 0xf0 │ │ - ldc2l 7, cr0, [r9, #120] @ 0x78 │ │ - ldc2l 11, cr3, [r9, #276] @ 0x114 @ │ │ - ldc2l 12, cr3, [sl, #168] @ 0xa8 │ │ + ldc2l 7, cr8, [r9, #420] @ 0x1a4 │ │ + ldc2l 7, cr0, [r9, #300] @ 0x12c │ │ + ldc2l 11, cr3, [r9, #456] @ 0x1c8 @ │ │ + ldc2l 12, cr3, [sl, #348] @ 0x15c │ │ │ │ 0248f6e8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #492 @ 0x1ec │ │ sub r0, r0, #1 │ │ cmp r0, #4 │ │ @@ -1385662,15 +1385662,15 @@ │ │ strbteq r9, [r2], #-3372 @ 0xfffff2d4 │ │ eoreq r9, ip, r8, lsl #29 │ │ ldc2l 14, cr6, [fp, #664] @ 0x298 │ │ strbteq r5, [r1], #-3224 @ 0xfffff368 │ │ eoreq r9, ip, ip, lsl #29 │ │ streq ip, [r4], #2804 @ 0xaf4 │ │ ldc2l 4, cr5, [fp, #276] @ 0x114 │ │ - ldc2l 2, cr10, [r9, #112] @ 0x70 │ │ + ldc2l 2, cr10, [r9, #292] @ 0x124 │ │ strbteq r9, [r2], #-3204 @ 0xfffff37c │ │ ldr r5, [pc, #3708] @ 24915a0 │ │ ldr r0, [pc, #3708] @ 24915a4 │ │ add r5, pc, r5 │ │ add r0, pc, r0 │ │ ldr r0, [r0, r1, lsl #2] │ │ str r0, [fp, #-48] @ 0xffffffd0 │ │ @@ -1385759,15 +1385759,15 @@ │ │ ldc2l 12, cr6, [fp, #904] @ 0x388 │ │ strbteq r5, [r1], #-2792 @ 0xfffff518 │ │ mlaeq ip, r4, ip, r9 │ │ ldc2l 11, cr10, [fp, #748] @ 0x2ec @ │ │ eoreq r9, ip, r8, ror #24 │ │ ldc2l 1, cr9, [r8, #664] @ 0x298 │ │ strbteq sl, [r1], #-3016 @ 0xfffff438 │ │ - ldc2l 2, cr12, [r9, #524] @ 0x20c │ │ + ldc2l 2, cr12, [r9, #704] @ 0x2c0 │ │ ldc2l 14, cr4, [fp, #320] @ 0x140 │ │ strbteq sl, [r1], #-3800 @ 0xfffff128 │ │ ldc2l 5, cr7, [fp, #976] @ 0x3d0 │ │ strbteq r5, [r1], #-2632 @ 0xfffff5b8 │ │ ldr r0, [pc, #3980] @ 2491840 │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ @@ -1385857,15 +1385857,15 @@ │ │ strbteq r9, [r2], #-2692 @ 0xfffff57c │ │ eoreq r9, ip, r0, ror #23 │ │ ldc2l 11, cr6, [fp, #1016] @ 0x3f8 @ │ │ strbteq r5, [r1], #-2536 @ 0xfffff618 │ │ strbteq r5, [r1], #-3348 @ 0xfffff2ec │ │ strbteq r9, [r2], #-2612 @ 0xfffff5cc │ │ ldc2l 10, cr10, [fp, #676] @ 0x2a4 @ │ │ - ldc2l 1, cr12, [r9, #716] @ 0x2cc │ │ + ldc2l 1, cr12, [r9, #896] @ 0x380 │ │ mov r6, sl │ │ ldr sl, [pc, #4008] @ 24919d8 │ │ mov r2, r8 │ │ movw r3, #2006 @ 0x7d6 │ │ add sl, pc, sl │ │ mov r0, sl │ │ bl 270da30 │ │ @@ -1385903,21 +1385903,21 @@ │ │ ldr r0, [pc, #3884] @ 24919f0 │ │ mov r5, #0 │ │ mov r6, #0 │ │ add r0, pc, r0 │ │ b 2490b30 │ │ strbteq r4, [r2], #-2976 @ 0xfffff460 │ │ ldc2l 10, cr10, [fp, #164] @ 0xa4 @ │ │ - ldc2l 1, cr12, [r9, #204] @ 0xcc │ │ + ldc2l 1, cr12, [r9, #384] @ 0x180 │ │ ldc2l 9, cr10, [fp, #498] @ 0x1f2 @ │ │ - ldc2l 1, cr12, [r9, #12] │ │ - ldc2l 15, cr6, [sl, #396] @ 0x18c │ │ - ldc2l 0, cr12, [r9, #844] @ 0x34c │ │ - ldc2l 15, cr6, [sl, #236] @ 0xec │ │ - ldc2l 0, cr12, [r9, #684] @ 0x2ac │ │ + ldc2l 1, cr12, [r9, #192] @ 0xc0 │ │ + ldc2l 15, cr6, [sl, #576] @ 0x240 │ │ + ldc2l 1, cr12, [r9] │ │ + ldc2l 15, cr6, [sl, #416] @ 0x1a0 │ │ + ldc2l 0, cr12, [r9, #864] @ 0x360 │ │ ldr r0, [pc, #3832] @ 24919f4 │ │ clz r2, r6 │ │ mov r1, #0 │ │ add r0, pc, r0 │ │ lsr r2, r2, #5 │ │ ldr r3, [r0, r7, lsl #2] │ │ ldr r0, [pc, #3812] @ 24919f8 │ │ @@ -1385957,16 +1385957,16 @@ │ │ ldr r1, [pc, #3692] @ 2491a08 │ │ mov r6, r5 │ │ add r1, pc, r1 │ │ ldr r4, [r1, r0, lsl #2] │ │ ldr r0, [pc, #3680] @ 2491a0c │ │ add r0, pc, r0 │ │ b 2490b28 │ │ - ldc2l 6, cr5, [sl, #152] @ 0x98 │ │ - ldc2l 6, cr7, [sl, #1016] @ 0x3f8 │ │ + ldc2l 6, cr5, [sl, #332] @ 0x14c │ │ + ldc2l 7, cr7, [sl, #172] @ 0xac │ │ strbteq sl, [r1], #-2860 @ 0xfffff4d4 │ │ strbteq r5, [r1], #-2116 @ 0xfffff7bc │ │ strbteq r9, [r2], #-2188 @ 0xfffff774 │ │ movw r0, #5000 @ 0x1388 │ │ cmp r1, r0 │ │ bcc 2490be8 │ │ ldr r0, [pc, #3640] @ 2491a10 │ │ @@ -1385988,24 +1385988,24 @@ │ │ str r4, [r0, r1, lsl #2] │ │ b 249150c │ │ strdeq r9, [ip], -r8 @ │ │ ldc2l 14, cr2, [fp] │ │ ldc2l 15, cr8, [r8, #152] @ 0x98 │ │ strbteq sl, [r1], #-2380 @ 0xfffff6b4 │ │ ldc2l 8, cr10, [fp, #972] @ 0x3cc │ │ - vcadd.f32 d25, d9, d7, #270 │ │ + ldc2l 8, cr9, [r9, #208] @ 0xd0 │ │ ldc2l 1, cr3, [r8, #800] @ 0x320 │ │ ldc2l 11, cr9, [r8, #152] @ 0x98 @ │ │ ldc2l 13, cr2, [fp, #224] @ 0xe0 │ │ - ldc2l 6, cr15, [r9, #476] @ 0x1dc │ │ - ldc2l 15, cr4, [sl, #184] @ 0xb8 │ │ - ldc2l 3, cr13, [r8, #836] @ 0x344 │ │ + ldc2l 6, cr15, [r9, #656] @ 0x290 │ │ + ldc2l 15, cr4, [sl, #364] @ 0x16c │ │ + ldc2l 3, cr13, [r8, #1016] @ 0x3f8 │ │ ldc2l 12, cr2, [fp, #664] @ 0x298 │ │ ldc2l 2, cr15, [sl, #236] @ 0xec │ │ - ldc2l 7, cr11, [r8, #316] @ 0x13c │ │ + ldc2l 7, cr11, [r8, #496] @ 0x1f0 │ │ streq pc, [r5], #3464 @ 0xd88 │ │ ldc2l 1, cr11, [sl, #620] @ 0x26c │ │ streq pc, [r5], #3392 @ 0xd40 │ │ ldr r4, [pc, #3512] @ 2491a20 │ │ add r4, pc, r4 │ │ mov r0, r4 │ │ bl 270e0c0 │ │ @@ -1386119,15 +1386119,15 @@ │ │ add r0, pc, r0 │ │ str r4, [r0, r1, lsl #2] │ │ b 2491790 │ │ streq pc, [r5], #3380 @ 0xd34 │ │ strbteq r9, [r2], #-1628 @ 0xfffff9a4 │ │ ldc2l 3, cr5, [r8, #696] @ 0x2b8 │ │ strbteq r5, [r1], #-1480 @ 0xfffffa38 │ │ - ldc2l 12, cr6, [sl, #284] @ 0x11c │ │ + ldc2l 12, cr6, [sl, #464] @ 0x1d0 │ │ strbteq r4, [r2], #-2008 @ 0xfffff828 │ │ ldc2l 15, cr2, [r8, #752] @ 0x2f0 │ │ strbteq r5, [r1], #-1384 @ 0xfffffa98 │ │ strbteq r5, [r1], #-1364 @ 0xfffffaac │ │ strbteq r4, [r2], #-1528 @ 0xfffffa08 │ │ strbteq r9, [r2], #-1440 @ 0xfffffa60 │ │ ldc2l 0, cr3, [r8, #68] @ 0x44 │ │ @@ -1386140,16 +1386140,16 @@ │ │ strbteq r5, [r1], #-1180 @ 0xfffffb64 │ │ strbteq r4, [r2], #-1700 @ 0xfffff95c │ │ strbteq r9, [r2], #-1212 @ 0xfffffb44 │ │ strbteq r9, [r2], #-1196 @ 0xfffffb54 │ │ strbteq r9, [r2], #-1180 @ 0xfffffb64 │ │ ldc2l 1, cr5, [r8, #952] @ 0x3b8 │ │ strbteq r9, [r2], #-1140 @ 0xfffffb8c │ │ - ldc2l 10, cr6, [sl, #540] @ 0x21c @ │ │ - ldc2l 10, cr6, [sl, #364] @ 0x16c @ │ │ + ldc2l 10, cr6, [sl, #720] @ 0x2d0 @ │ │ + ldc2l 10, cr6, [sl, #544] @ 0x220 @ │ │ strbteq r9, [r2], #-1040 @ 0xfffffbf0 │ │ strbteq r4, [r2], #-1508 @ 0xfffffa1c │ │ ldc2l 1, cr5, [r8, #344] @ 0x158 │ │ strbteq r9, [r2], #-972 @ 0xfffffc34 │ │ strbteq r9, [r2], #-968 @ 0xfffffc38 │ │ ldc2l 4, cr10, [fp, #276] @ 0x114 │ │ strbteq r5, [r1], #-1628 @ 0xfffff9a4 │ │ @@ -1386369,32 +1386369,32 @@ │ │ streq pc, [r5], #2292 @ 0x8f4 │ │ strbteq r5, [r1], #-868 @ 0xfffffc9c │ │ vcadd.f32 q9, , q9, #270 │ │ strbteq r5, [r1], #-816 @ 0xfffffcd0 │ │ ldc2l 14, cr15, [fp, #832] @ 0x340 │ │ strbteq r4, [r2], #-548 @ 0xfffffddc │ │ strbteq r5, [r1], #-352 @ 0xfffffea0 │ │ - ldc2l 7, cr6, [sl, #908] @ 0x38c │ │ + ldc2l 8, cr6, [sl, #64] @ 0x40 │ │ strbteq r4, [r2], #-880 @ 0xfffffc90 │ │ ldc2l 14, cr4, [r8, #904] @ 0x388 │ │ strbteq sl, [r1], #-596 @ 0xfffffdac │ │ strbteq r5, [r1], #-244 @ 0xffffff0c │ │ - ldc2l 7, cr6, [sl, #476] @ 0x1dc │ │ + ldc2l 7, cr6, [sl, #656] @ 0x290 │ │ strbteq r4, [r2], #-772 @ 0xfffffcfc │ │ ldc2l 1, cr14, [fp, #992] @ 0x3e0 │ │ strbteq sl, [r1], #-880 @ 0xfffffc90 │ │ ldc2l 11, cr2, [r8, #452] @ 0x1c4 @ │ │ strbteq r9, [r2], #-204 @ 0xffffff34 │ │ strbteq r5, [r1], #-72 @ 0xffffffb8 │ │ strbteq r9, [r2], #-172 @ 0xffffff54 │ │ strbteq r9, [r2], #-156 @ 0xffffff64 │ │ ldc2l 1, cr14, [fp, #448] @ 0x1c0 │ │ strbteq r9, [r2], #-116 @ 0xffffff8c │ │ strbteq sl, [r1], #-740 @ 0xfffffd1c │ │ - ldc2l 6, cr6, [sl, #508] @ 0x1fc │ │ + ldc2l 6, cr6, [sl, #688] @ 0x2b0 │ │ strbteq r4, [r2], #-528 @ 0xfffffdf0 │ │ strbteq r9, [r2], #-36 @ 0xffffffdc │ │ strbteq r9, [r2], #-8 │ │ ldr r0, [pc, #4092] @ 2492278 │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ cmp r1, #2 │ │ @@ -1386538,15 +1386538,15 @@ │ │ mov r2, #40 @ 0x28 │ │ mov r3, #8 │ │ add r1, pc, r1 │ │ bl 270d9e0 │ │ b 248fc3c │ │ strbteq r5, [r1], #-664 @ 0xfffffd68 │ │ streq pc, [r5], #1668 @ 0x684 │ │ - ldc2l 14, cr14, [r9, #556] @ 0x22c │ │ + ldc2l 14, cr14, [r9, #736] @ 0x2e0 │ │ strbteq r8, [r2], #-3976 @ 0xfffff078 │ │ ldc2l 0, cr10, [fp, #20] │ │ strbteq r5, [r1], #-536 @ 0xfffffde8 │ │ streq pc, [r5], #1540 @ 0x604 │ │ ldr r0, [pc, #3588] @ 24922e4 │ │ mov r2, r8 │ │ movw r3, #2127 @ 0x84f │ │ @@ -1386584,27 +1386584,27 @@ │ │ eoreq r9, ip, r8, asr #1 │ │ streq pc, [r5], #1480 @ 0x5c8 │ │ strbteq r8, [r2], #-3832 @ 0xfffff108 │ │ ldc2l 15, cr9, [fp, #468] @ 0x1d4 │ │ strbteq r5, [r1], #-396 @ 0xfffffe74 │ │ streq pc, [r5], #1380 @ 0x564 │ │ ldc2l 1, cr9, [r8, #888] @ 0x378 │ │ - ldc2l 11, cr12, [r8, #52] @ 0x34 @ │ │ + ldc2l 11, cr12, [r8, #232] @ 0xe8 @ │ │ strbteq r8, [r2], #-3680 @ 0xfffff1a0 │ │ strbteq r8, [r2], #-3632 @ 0xfffff1d0 │ │ strbteq r3, [r2], #-3688 @ 0xfffff198 │ │ strbteq r8, [r2], #-3584 @ 0xfffff200 │ │ ldc2l 14, cr13, [fp, #848] @ 0x350 │ │ strbteq sl, [r1], #-80 @ 0xffffffb0 │ │ strbteq r3, [r2], #-4004 @ 0xfffff05c │ │ ldc2l 3, cr2, [fp, #240] @ 0xf0 │ │ strbteq r9, [r1], #-3680 @ 0xfffff1a0 │ │ streq fp, [r4], #2944 @ 0xb80 │ │ - ldc2l 4, cr4, [sl, #940] @ 0x3ac │ │ - ldc2l 15, cr12, [r9, #292] @ 0x124 │ │ + ldc2l 5, cr4, [sl, #96] @ 0x60 │ │ + ldc2l 15, cr12, [r9, #472] @ 0x1d8 │ │ ldr r4, [pc, #4000] @ 2492558 │ │ add r4, pc, r4 │ │ mov r0, r4 │ │ bl 270e0c0 │ │ cmp r0, #0 │ │ beq 24918dc │ │ add r1, sp, #20 │ │ @@ -1386848,15 +1386848,15 @@ │ │ ldr r9, [pc, #4052] @ 249295c │ │ mov r1, #1 │ │ add r5, pc, r5 │ │ movw r7, #10000 @ 0x2710 │ │ add r9, pc, r9 │ │ b 2491c94 │ │ streq pc, [r5], #444 @ 0x1bc │ │ - ldc2l 9, cr14, [r9, #398] @ 0x18e @ │ │ + ldc2l 9, cr14, [r9, #488] @ 0x1e8 @ │ │ ldc2l 0, cr2, [fp, #360] @ 0x168 │ │ ldr r1, [pc, #4084] @ 24929a0 │ │ add r1, pc, r1 │ │ ldr r0, [r1, r0, lsl #2] │ │ cmp r0, #0 │ │ ble 2491a34 │ │ ldr r1, [sp, #12] │ │ @@ -1386877,23 +1386877,23 @@ │ │ strbteq r3, [r2], #-2532 @ 0xfffff61c │ │ ldc2l 6, cr15, [fp, #448] @ 0x1c0 │ │ strbteq r8, [r2], #-2396 @ 0xfffff6a4 │ │ strbteq r3, [r2], #-2432 @ 0xfffff680 │ │ ldc2l 6, cr15, [fp, #80] @ 0x50 │ │ strbteq r3, [r2], #-2376 @ 0xfffff6b8 │ │ ldc2l 5, cr15, [fp, #880] @ 0x370 │ │ - ldc2l 14, cr5, [sl, #988] @ 0x3dc │ │ + ldc2l 15, cr5, [sl, #144] @ 0x90 │ │ strbteq r8, [r2], #-2220 @ 0xfffff754 │ │ strbteq r3, [r2], #-2688 @ 0xfffff580 │ │ strbteq r9, [r1], #-2824 @ 0xfffff4f8 │ │ streq fp, [r4], #1604 @ 0x644 │ │ strbteq r8, [r2], #-2068 @ 0xfffff7ec │ │ ldc2l 8, cr9, [fp, #580] @ 0x244 │ │ strbteq r4, [r1], #-2728 @ 0xfffff558 │ │ - ldc2l 15, cr3, [sl, #412] @ 0x19c │ │ + ldc2l 15, cr3, [sl, #592] @ 0x250 │ │ ldr r0, [pc, #3964] @ 24929b8 │ │ ldr r0, [pc, r0] │ │ ldr r1, [sp, #12] │ │ cmp r1, r0 │ │ beq 2491c80 │ │ sub r1, r0, #1 │ │ cmp r1, #100 @ 0x64 │ │ @@ -1387067,15 +1387067,15 @@ │ │ mov r1, sl │ │ ldr r2, [pc, #4008] @ 2492ca0 │ │ movw r3, #1144 @ 0x478 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ b 24919a4 │ │ - ldc2l 9, cr12, [r9, #394] @ 0x18a @ │ │ + ldc2l 9, cr12, [r9, #484] @ 0x1e4 @ │ │ ldrbteq sp, [pc], #-896 @ 2491d14 │ │ eoreq r8, ip, ip, lsl #18 │ │ vcadd.f32 d28, d10, d0, #270 │ │ strbteq r8, [r2], #-1836 @ 0xfffff8d4 │ │ strhteq r8, [ip], -ip │ │ strbteq r8, [r2], #-1780 @ 0xfffff90c │ │ ldc2l 1, cr2, [r8, #404] @ 0x194 │ │ @@ -1387429,20 +1387429,20 @@ │ │ strbteq r4, [r1], #-312 @ 0xfffffec8 │ │ streq sl, [r4], #3976 @ 0xf88 │ │ strbteq r8, [r2], #-336 @ 0xfffffeb0 │ │ ldc2l 14, cr14, [fp, #128] @ 0x80 │ │ strbteq r3, [r2], #-364 @ 0xfffffe94 │ │ strbteq r4, [r1], #-172 @ 0xffffff54 │ │ strbteq r9, [r1], #-1296 @ 0xfffffaf0 │ │ - ldc2l 7, cr5, [sl, #156] @ 0x9c │ │ + ldc2l 7, cr5, [sl, #336] @ 0x150 │ │ strbteq r8, [r2], #-220 @ 0xffffff24 │ │ strbteq r3, [r2], #-688 @ 0xfffffd50 │ │ ldc2l 14, cr3, [r8, #136] @ 0x88 │ │ strbteq r4, [r1], #-56 @ 0xffffffc8 │ │ - ldc2l 6, cr5, [sl, #748] @ 0x2ec │ │ + ldc2l 6, cr5, [sl, #928] @ 0x3a0 │ │ strbteq r3, [r2], #-588 @ 0xfffffdb4 │ │ strbteq r8, [r2], #-100 @ 0xffffff9c │ │ ldc2l 1, cr13, [fp, #224] @ 0xe0 │ │ strbteq r9, [r1], #-684 @ 0xfffffd54 │ │ ldc2l 5, cr1, [fp, #656] @ 0x290 │ │ streq lr, [r5], #1748 @ 0x6d4 │ │ ldc2l 0, cr9, [fp, #572] @ 0x23c │ │ @@ -1387627,15 +1387627,15 @@ │ │ bl 270da10 │ │ ldr r0, [pc, #2348] @ 2492ee4 │ │ add r0, pc, r0 │ │ b 2492b48 │ │ strbteq r7, [r2], #-3780 @ 0xfffff13c │ │ ldc2l 15, cr8, [fp, #260] @ 0x104 │ │ strbteq r4, [r1], #-344 @ 0xfffffea8 │ │ - ldc2l 6, cr3, [sl, #92] @ 0x5c │ │ + ldc2l 6, cr3, [sl, #272] @ 0x110 │ │ ldr r4, [pc, #2292] @ 2492ec8 │ │ ldr r4, [pc, r4] │ │ bl 270de10 │ │ sub r0, r0, #1 │ │ cmp r4, r0 │ │ bge 2492640 │ │ ldr r8, [pc, #2272] @ 2492ecc │ │ @@ -1387656,15 +1387656,15 @@ │ │ movw r0, #4999 @ 0x1387 │ │ cmp r4, r0 │ │ bhi 249288c │ │ ldr r0, [pc, #2352] @ 2492f64 │ │ add r0, pc, r0 │ │ str r6, [r0, r4, lsl #2] │ │ b 24928f4 │ │ - ldc2l 0, cr12, [r9, #468] @ 0x1d4 │ │ + ldc2l 0, cr12, [r9, #648] @ 0x288 │ │ ldr r0, [pc, #2208] @ 2492ee8 │ │ ldr r0, [pc, r0] │ │ cmp r0, #1 │ │ blt 2492914 │ │ ldr r9, [pc, #2196] @ 2492eec │ │ rsb r5, r0, #0 │ │ ldr r6, [pc, #2192] @ 2492ef0 │ │ @@ -1387683,15 +1387683,15 @@ │ │ strbteq r7, [r2], #-3492 @ 0xfffff25c │ │ ldc2l 8, cr1, [r8, #84] @ 0x54 │ │ strbteq r3, [r1], #-3364 @ 0xfffff2dc │ │ strbteq r7, [r2], #-3428 @ 0xfffff29c │ │ ldc2l 7, cr1, [r8, #852] @ 0x354 │ │ strbteq r3, [r1], #-3296 @ 0xfffff320 │ │ streq sl, [r4], #2880 @ 0xb40 │ │ - ldc2l 13, cr9, [r8, #460] @ 0x1cc │ │ + ldc2l 13, cr9, [r8, #640] @ 0x280 │ │ streq lr, [r5], #932 @ 0x3a4 │ │ streq lr, [r5], #916 @ 0x394 │ │ ldc2l 7, cr9, [sl, #684] @ 0x2ac │ │ ldr r2, [pc, #2116] @ 2492f04 │ │ mov r0, r7 │ │ mov r1, sl │ │ movw r3, #842 @ 0x34a │ │ @@ -1387774,15 +1387774,15 @@ │ │ cmp r0, #0 │ │ bgt 249278c │ │ mov r4, #0 │ │ str r4, [r9] │ │ ldr r7, [pc, #1776] @ 2492f00 │ │ add r7, pc, r7 │ │ b 249286c │ │ - ldc2l 8, cr11, [r8, #1012] @ 0x3f4 │ │ + ldc2l 9, cr11, [r8, #84] @ 0x54 @ │ │ ldc2l 9, cr14, [fp, #104] @ 0x68 @ │ │ strbteq r2, [r2], #-3200 @ 0xfffff380 │ │ strbteq r7, [r2], #-3108 @ 0xfffff3dc │ │ mov r0, r7 │ │ mov r1, sl │ │ mov r2, r5 │ │ movw r3, #877 @ 0x36d │ │ @@ -1387803,15 +1387803,15 @@ │ │ ldr r0, [pc, #1736] @ 2492f3c │ │ add r0, pc, r0 │ │ str r4, [r0, sl, lsl #2] │ │ b 24927a0 │ │ strbteq r7, [r2], #-3068 @ 0xfffff404 │ │ ldc2l 6, cr1, [r8, #436] @ 0x1b4 │ │ ldc2l 1, cr1, [fp, #248] @ 0xf8 │ │ - ldc2l 3, cr3, [sl, #440] @ 0x1b8 │ │ + ldc2l 3, cr3, [sl, #620] @ 0x26c │ │ ldr r0, [pc, #1748] @ 2492f68 │ │ mov r1, r4 │ │ ldr r2, [pc, #1744] @ 2492f6c │ │ mov r3, #904 @ 0x388 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1387881,29 +1387881,29 @@ │ │ ldr r3, [pc, #1432] @ 2492f44 │ │ add r3, pc, r3 │ │ mov r8, r3 │ │ b 24925fc │ │ strbteq r3, [r1], #-2672 @ 0xfffff590 │ │ strbteq r3, [r1], #-2556 @ 0xfffff604 │ │ ldc2l 0, cr1, [fp, #584] @ 0x248 │ │ - ldc2l 1, cr10, [r9, #908] @ 0x38c │ │ + ldc2l 2, cr10, [r9, #64] @ 0x40 │ │ strbteq r3, [r1], #-2908 @ 0xfffff4a4 │ │ ldc2l 0, cr1, [fp, #360] @ 0x168 │ │ - ldc2l 1, cr10, [r9, #684] @ 0x2ac │ │ + ldc2l 1, cr10, [r9, #864] @ 0x360 │ │ strbteq r3, [r1], #-2860 @ 0xfffff4d4 │ │ strbteq r3, [r1], #-2432 @ 0xfffff680 │ │ ldc2l 6, cr14, [fp, #720] @ 0x2d0 │ │ - ldc2l 1, cr10, [r9, #460] @ 0x1cc │ │ + ldc2l 1, cr10, [r9, #640] @ 0x280 │ │ strbteq r2, [r2], #-2556 @ 0xfffff604 │ │ ldc2l 6, cr14, [fp, #496] @ 0x1f0 │ │ - ldc2l 1, cr10, [r9, #236] @ 0xec │ │ + ldc2l 1, cr10, [r9, #416] @ 0x1a0 │ │ strbteq r2, [r2], #-2508 @ 0xfffff634 │ │ strbteq r3, [r1], #-2320 @ 0xfffff6f0 │ │ ldc2l 6, cr3, [r8, #792] @ 0x318 │ │ - ldc2l 1, cr10, [r9, #12] │ │ + ldc2l 1, cr10, [r9, #192] @ 0xc0 │ │ strbteq r8, [r1], #-2604 @ 0xfffff5d4 │ │ mvn r0, #7 │ │ add r3, r0, r1, lsl #3 │ │ movw r0, #14464 @ 0x3880 │ │ movt r0, #1 │ │ cmp r3, r0 │ │ bcc 2492a38 │ │ @@ -1387985,29 +1387985,29 @@ │ │ add r0, pc, r0 │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 6, cr3, [r8, #568] @ 0x238 │ │ - ldc2l 0, cr10, [r9, #812] @ 0x32c │ │ + ldc2l 0, cr10, [r9, #992] @ 0x3e0 │ │ strbteq r8, [r1], #-2556 @ 0xfffff604 │ │ strbteq r3, [r1], #-2208 @ 0xfffff760 │ │ ldc2l 9, cr12, [fp, #432] @ 0x1b0 @ │ │ - ldc2l 0, cr10, [r9, #588] @ 0x24c │ │ + ldc2l 0, cr10, [r9, #768] @ 0x300 │ │ strbteq r8, [r1], #-2892 @ 0xfffff4b4 │ │ ldc2l 9, cr12, [fp, #320] @ 0x140 @ │ │ - ldc2l 0, cr10, [r9, #364] @ 0x16c │ │ + ldc2l 0, cr10, [r9, #544] @ 0x220 │ │ strbteq r8, [r1], #-2844 @ 0xfffff4e4 │ │ strbteq r3, [r1], #-2096 @ 0xfffff7d0 │ │ ldc2l 3, cr1, [r8, #20] │ │ - ldc2l 0, cr10, [r9, #140] @ 0x8c │ │ + ldc2l 0, cr10, [r9, #320] @ 0x140 │ │ strbteq r3, [r1], #-2060 @ 0xfffff7f4 │ │ ldc2l 2, cr1, [r8, #836] @ 0x344 │ │ - ldc2l 15, cr9, [r9, #956] @ 0x3bc │ │ + ldc2l 0, cr10, [r9, #112] @ 0x70 │ │ mov r7, sl │ │ cmp r1, #100 @ 0x64 │ │ bcc 2492bc4 │ │ ldr r0, [pc, #1068] @ 2492fdc │ │ movw r3, #2312 @ 0x908 │ │ ldr r2, [pc, #1064] @ 2492fe0 │ │ add r0, pc, r0 │ │ @@ -1388062,18 +1388062,18 @@ │ │ sub r5, fp, #40 @ 0x28 │ │ ldr sl, [pc, #876] @ 2492ff0 │ │ movw r8, #5000 @ 0x1388 │ │ add r4, pc, r4 │ │ add sl, pc, sl │ │ b 2492cb4 │ │ ldc2l 2, cr1, [r8, #436] @ 0x1b4 │ │ - ldc2l 15, cr9, [r9, #556] @ 0x22c │ │ + ldc2l 15, cr9, [r9, #736] @ 0x2e0 │ │ strbteq r3, [r1], #-1916 @ 0xfffff884 │ │ ldc2l 2, cr1, [r8, #180] @ 0xb4 │ │ - ldc2l 15, cr9, [r9, #300] @ 0x12c │ │ + ldc2l 15, cr9, [r9, #480] @ 0x1e0 │ │ strbteq r3, [r1], #-1816 @ 0xfffff8e8 │ │ cmp r6, #0 │ │ str r6, [fp, #-40] @ 0xffffffd8 │ │ ble 2492bf8 │ │ mov r0, r5 │ │ mov r1, r4 │ │ bl 270e0b0 │ │ @@ -1388114,22 +1388114,22 @@ │ │ ldr r1, [fp, #-40] @ 0xffffffd8 │ │ cmp r1, r0 │ │ ldreq r0, [pc, #684] @ 2493004 │ │ moveq r1, #0 │ │ addeq r0, pc, r0 │ │ streq r1, [r0] │ │ b 2492ca8 │ │ - ldc2l 14, cr2, [sl, #796] @ 0x31c │ │ - ldc2l 14, cr9, [r9, #780] @ 0x30c │ │ + ldc2l 14, cr2, [sl, #976] @ 0x3d0 │ │ + ldc2l 14, cr9, [r9, #960] @ 0x3c0 │ │ strbteq r3, [r1], #-1684 @ 0xfffff96c │ │ ldc2l 1, cr1, [r8, #228] @ 0xe4 │ │ - ldc2l 14, cr9, [r9, #348] @ 0x15c │ │ + ldc2l 14, cr9, [r9, #528] @ 0x210 │ │ strbteq r3, [r1], #-1608 @ 0xfffff9b8 │ │ ldc2l 1, cr1, [r8, #36] @ 0x24 │ │ - ldc2l 14, cr9, [r9, #156] @ 0x9c │ │ + ldc2l 14, cr9, [r9, #336] @ 0x150 │ │ ldc2l 1, cr5, [fp, #688] @ 0x2b0 │ │ ldc2l 1, cr5, [fp, #644] @ 0x284 │ │ ldc2l 6, cr11, [sl, #752] @ 0x2f0 │ │ ldc2l 14, cr5, [r8, #692] @ 0x2b4 │ │ ldc2l 6, cr11, [sl, #604] @ 0x25c │ │ ldc2l 5, cr13, [sl, #656] @ 0x290 │ │ ldc2l 9, cr12, [fp, #314] @ 0x13a @ │ │ @@ -1388138,166 +1388138,166 @@ │ │ strbteq r3, [r1], #-2208 @ 0xfffff760 │ │ strbteq r7, [r2], #-1480 @ 0xfffffa38 │ │ strbteq r3, [r1], #-1344 @ 0xfffffac0 │ │ strbteq r3, [r1], #-1340 @ 0xfffffac4 │ │ strbteq r7, [r2], #-1432 @ 0xfffffa68 │ │ strbteq r2, [r2], #-1884 @ 0xfffff8a4 │ │ ldc2l 5, cr8, [fp, #756] @ 0x2f4 │ │ - ldc2l 12, cr9, [r9, #796] @ 0x31c │ │ + ldc2l 12, cr9, [r9, #976] @ 0x3d0 │ │ strbteq r3, [r1], #-2000 @ 0xfffff830 │ │ ldc2l 5, cr8, [fp, #532] @ 0x214 │ │ - ldc2l 12, cr9, [r9, #572] @ 0x23c │ │ + ldc2l 12, cr9, [r9, #752] @ 0x2f0 │ │ strbteq r3, [r1], #-1948 @ 0xfffff864 │ │ - ldc2l 10, cr4, [sl, #940] @ 0x3ac @ │ │ - ldc2l 12, cr9, [r9, #364] @ 0x16c │ │ - ldc2l 10, cr4, [sl, #764] @ 0x2fc @ │ │ - ldc2l 12, cr9, [r9, #188] @ 0xbc │ │ + ldc2l 11, cr4, [sl, #96] @ 0x60 @ │ │ + ldc2l 12, cr9, [r9, #544] @ 0x220 │ │ + ldc2l 10, cr4, [sl, #944] @ 0x3b0 @ │ │ + ldc2l 12, cr9, [r9, #368] @ 0x170 │ │ strbteq r3, [r1], #-956 @ 0xfffffc44 │ │ streq sl, [r4], #532 @ 0x214 │ │ strbteq r8, [r1], #-2056 @ 0xfffff7f8 │ │ ldc2l 14, cr0, [r8, #84] @ 0x54 │ │ - ldc2l 11, cr9, [r9, #204] @ 0xcc @ │ │ + ldc2l 11, cr9, [r9, #384] @ 0x180 @ │ │ strbteq r3, [r1], #-804 @ 0xfffffcdc │ │ - ldc2l 10, cr2, [sl, #524] @ 0x20c @ │ │ - ldc2l 10, cr9, [r9, #508] @ 0x1fc @ │ │ + ldc2l 10, cr2, [sl, #704] @ 0x2c0 @ │ │ + ldc2l 10, cr9, [r9, #688] @ 0x2b0 @ │ │ strbteq r3, [r1], #-568 @ 0xfffffdc8 │ │ ldc2l 12, cr0, [r8, #964] @ 0x3c4 │ │ - ldc2l 10, cr9, [r9, #60] @ 0x3c @ │ │ + ldc2l 10, cr9, [r9, #240] @ 0xf0 @ │ │ strbteq r3, [r1], #-508 @ 0xfffffe04 │ │ ldc2l 12, cr0, [r8, #756] @ 0x2f4 │ │ - ldc2l 9, cr9, [r9, #438] @ 0x1b6 @ │ │ + ldc2l 10, cr9, [r9, #32] @ │ │ strbteq r3, [r1], #-704 @ 0xfffffd40 │ │ ldc2l 13, cr0, [r8, #852] @ 0x354 │ │ - ldc2l 10, cr9, [r9, #972] @ 0x3cc @ │ │ + ldc2l 11, cr9, [r9, #128] @ 0x80 @ │ │ strbteq r3, [r1], #-896 @ 0xfffffc80 │ │ strbteq r3, [r1], #-308 @ 0xfffffecc │ │ ldc2l 7, cr0, [fp, #856] @ 0x358 │ │ - ldc2l 9, cr9, [r9, #78] @ 0x4e @ │ │ + ldc2l 9, cr9, [r9, #168] @ 0xa8 @ │ │ strbteq r3, [r1], #-672 @ 0xfffffd60 │ │ ldc2l 7, cr0, [fp, #632] @ 0x278 │ │ - vcadd.f32 , , , #270 │ │ + ldc2l 9, cr9, [r9, #56] @ 0x38 @ │ │ strbteq r3, [r1], #-624 @ 0xfffffd90 │ │ strbteq r3, [r1], #-196 @ 0xffffff3c │ │ ldc2l 13, cr13, [fp, #992] @ 0x3e0 │ │ - ldc2l 8, cr9, [r9, #732] @ 0x2dc │ │ + vcadd.f32 , , q10, #270 │ │ strbteq r2, [r2], #-320 @ 0xfffffec0 │ │ ldc2l 13, cr13, [fp, #768] @ 0x300 │ │ - ldc2l 8, cr9, [r9, #508] @ 0x1fc │ │ + vcadd.f32 d25, d25, d28, #270 │ │ strbteq r2, [r2], #-272 @ 0xfffffef0 │ │ strbteq r3, [r1], #-84 @ 0xffffffac │ │ ldc2l 14, cr2, [r8, #40] @ 0x28 │ │ - vcadd.f32 , , , #270 │ │ + ldc2l 8, cr9, [r9, #464] @ 0x1d0 │ │ strbteq r8, [r1], #-368 @ 0xfffffe90 │ │ ldc2l 13, cr2, [r8, #840] @ 0x348 │ │ - vcadd.f32 d25, d9, d15, #270 │ │ + ldc2l 8, cr9, [r9, #240] @ 0xf0 │ │ strbteq r8, [r1], #-320 @ 0xfffffec0 │ │ strbteq r2, [r1], #-4068 @ 0xfffff01c │ │ ldc2l 1, cr12, [fp, #112] @ 0x70 │ │ - ldc2l 7, cr9, [r9, #860] @ 0x35c │ │ + vcadd.f32 d25, d9, d4, #270 │ │ strbteq r8, [r1], #-656 @ 0xfffffd70 │ │ ldc2l 0, cr12, [fp, #912] @ 0x390 │ │ - ldc2l 7, cr9, [r9, #636] @ 0x27c │ │ + ldc2l 7, cr9, [r9, #816] @ 0x330 │ │ strbteq r8, [r1], #-608 @ 0xfffffda0 │ │ strbteq r2, [r1], #-3956 @ 0xfffff08c │ │ ldc2l 10, cr0, [r8, #292] @ 0x124 @ │ │ - ldc2l 7, cr9, [r9, #412] @ 0x19c │ │ + ldc2l 7, cr9, [r9, #592] @ 0x250 │ │ strbteq r2, [r1], #-3920 @ 0xfffff0b0 │ │ ldc2l 10, cr0, [r8, #84] @ 0x54 @ │ │ - ldc2l 7, cr9, [r9, #204] @ 0xcc │ │ + ldc2l 7, cr9, [r9, #384] @ 0x180 │ │ strbteq r2, [r1], #-3868 @ 0xfffff0e4 │ │ strbteq r2, [r1], #-3840 @ 0xfffff100 │ │ strbteq r2, [r1], #-3828 @ 0xfffff10c │ │ strbteq r3, [r1], #-852 @ 0xfffffcac │ │ strbteq r2, [r1], #-3688 @ 0xfffff198 │ │ strbteq r2, [r1], #-3664 @ 0xfffff1b0 │ │ strbteq r2, [r1], #-3788 @ 0xfffff134 │ │ ldc2l 8, cr10, [fp, #712] @ 0x2c8 │ │ - ldc2l 9, cr0, [r9, #218] @ 0xda @ │ │ + ldc2l 9, cr0, [r9, #308] @ 0x134 @ │ │ eoreq r7, ip, r8, lsr #1 │ │ ldc2l 7, cr5, [r8, #344] @ 0x158 │ │ ldc2l 6, cr2, [fp, #452] @ 0x1c4 │ │ strbteq r2, [r1], #-3568 @ 0xfffff210 │ │ strbteq r8, [r1], #-176 @ 0xffffff50 │ │ strbteq r7, [r1], #-3868 @ 0xfffff0e4 │ │ ldc2l 11, cr2, [r8, #600] @ 0x258 @ │ │ strbteq r2, [r1], #-3168 @ 0xfffff3a0 │ │ strbteq r1, [r2], #-3744 @ 0xfffff160 │ │ ldc2l 9, cr2, [r8, #500] @ 0x1f4 @ │ │ - ldc2l 5, cr9, [r9, #508] @ 0x1fc │ │ + ldc2l 5, cr9, [r9, #688] @ 0x2b0 │ │ strbteq r7, [r1], #-3760 @ 0xfffff150 │ │ strbteq r2, [r1], #-3404 @ 0xfffff2b4 │ │ strbteq r1, [r2], #-3980 @ 0xfffff074 │ │ strbteq r8, [r1], #-8 │ │ - ldc2l 5, cr9, [r9, #252] @ 0xfc │ │ + ldc2l 5, cr9, [r9, #432] @ 0x1b0 │ │ strbteq r7, [r1], #-3684 @ 0xfffff19c │ │ ldc2l 14, cr11, [fp, #304] @ 0x130 │ │ strbteq r2, [r1], #-3292 @ 0xfffff324 │ │ strbteq r1, [r2], #-3868 @ 0xfffff0e4 │ │ ldc2l 10, cr2, [r8, #456] @ 0x1c8 @ │ │ strbteq r7, [r1], #-3964 @ 0xfffff084 │ │ strbteq r7, [r1], #-3788 @ 0xfffff134 │ │ ldc2l 9, cr2, [r8, #348] @ 0x15c @ │ │ strbteq r7, [r1], #-3348 @ 0xfffff2ec │ │ strbteq r2, [r1], #-2840 @ 0xfffff4e8 │ │ strbteq r2, [r1], #-2696 @ 0xfffff578 │ │ strbteq r1, [r2], #-3388 @ 0xfffff2c4 │ │ strbteq r2, [r1], #-2800 @ 0xfffff510 │ │ - ldc2l 1, cr4, [sl, #572] @ 0x23c │ │ - ldc2l 2, cr9, [r9, #1020] @ 0x3fc │ │ + ldc2l 1, cr4, [sl, #752] @ 0x2f0 │ │ + ldc2l 3, cr9, [r9, #176] @ 0xb0 │ │ strbteq r2, [r1], #-3644 @ 0xfffff1c4 │ │ strbteq r2, [r1], #-3640 @ 0xfffff1c8 │ │ strbteq r2, [r1], #-3632 @ 0xfffff1d0 │ │ strbteq r3, [r1], #-308 @ 0xfffffecc │ │ ldc2l 12, cr7, [fp, #628] @ 0x274 │ │ - ldc2l 3, cr9, [r9, #668] @ 0x29c │ │ + ldc2l 3, cr9, [r9, #848] @ 0x350 │ │ strbteq r2, [r1], #-3768 @ 0xfffff148 │ │ strbteq r2, [r1], #-2936 @ 0xfffff488 │ │ strbteq r2, [r1], #-2924 @ 0xfffff494 │ │ - ldc2l 1, cr4, [sl, #956] @ 0x3bc │ │ - ldc2l 3, cr9, [r9, #380] @ 0x17c │ │ + ldc2l 2, cr4, [sl, #112] @ 0x70 │ │ + ldc2l 3, cr9, [r9, #560] @ 0x230 │ │ strbteq r1, [r2], #-3448 @ 0xfffff288 │ │ ldc2l 3, cr2, [fp, #148] @ 0x94 │ │ ldrdeq r7, [ip], -r4 @ │ │ - ldc2l 4, cr7, [r9, #300] @ 0x12c │ │ + ldc2l 4, cr7, [r9, #480] @ 0x1e0 │ │ strbteq r3, [r1], #-1000 @ 0xfffffc18 │ │ ldc2l 4, cr11, [sl, #700] @ 0x2bc │ │ ldc2l 6, cr4, [fp, #308] @ 0x134 │ │ - ldc2l 12, cr10, [r9, #724] @ 0x2d4 │ │ - ldc2l 2, cr9, [r9, #108] @ 0x6c │ │ + ldc2l 12, cr10, [r9, #904] @ 0x388 │ │ + ldc2l 2, cr9, [r9, #288] @ 0x120 │ │ eoreq r6, ip, r0, lsl #24 │ │ ldrbteq fp, [pc], #-1632 @ 2492fb4 │ │ ldc2l 10, cr10, [sl, #912] @ 0x390 @ │ │ - ldc2l 1, cr9, [r9, #748] @ 0x2ec │ │ + ldc2l 1, cr9, [r9, #928] @ 0x3a0 │ │ eoreq r6, ip, r4, lsr #23 │ │ strbteq r6, [r2], #-2560 @ 0xfffff600 │ │ - ldc2l 1, cr2, [sl, #476] @ 0x1dc │ │ - ldc2l 1, cr9, [r9, #460] @ 0x1cc │ │ + ldc2l 1, cr2, [sl, #656] @ 0x290 │ │ + ldc2l 1, cr9, [r9, #640] @ 0x280 │ │ ldc2l 13, cr1, [fp, #44] @ 0x2c │ │ - ldc2l 1, cr9, [r9, #172] @ 0xac │ │ + ldc2l 1, cr9, [r9, #352] @ 0x160 │ │ streq r9, [r4], #1912 @ 0x778 │ │ strbteq r2, [r1], #-2316 @ 0xfffff6f4 │ │ ldc2l 4, cr4, [fp, #644] @ 0x284 │ │ ldc2l 3, cr0, [r8, #452] @ 0x1c4 │ │ - ldc2l 0, cr9, [r9, #572] @ 0x23c │ │ + ldc2l 0, cr9, [r9, #752] @ 0x2f0 │ │ strbteq r2, [r1], #-2172 @ 0xfffff784 │ │ streq r9, [r4], #1740 @ 0x6cc │ │ streq r9, [r4], #1572 @ 0x624 │ │ - ldc2l 15, cr8, [r9, #764] @ 0x2fc │ │ - ldc2l 15, cr1, [sl, #396] @ 0x18c │ │ + ldc2l 15, cr8, [r9, #944] @ 0x3b0 │ │ + ldc2l 15, cr1, [sl, #576] @ 0x240 │ │ strbteq r6, [r2], #-1960 @ 0xfffff858 │ │ vcadd.f32 d23, d11, d21, #270 │ │ strbteq r2, [r1], #-2624 @ 0xfffff5c0 │ │ strbteq r2, [r1], #-1756 @ 0xfffff924 │ │ eoreq r6, ip, ip, lsl #20 │ │ ldc2l 9, cr7, [fp, #102] @ 0x66 @ │ │ - ldc2l 13, cr6, [r9, #468] @ 0x1d4 │ │ + ldc2l 13, cr6, [r9, #648] @ 0x288 │ │ streq ip, [r5], #3900 @ 0xf3c │ │ - ldc2l 2, cr0, [r9, #772] @ 0x304 │ │ + ldc2l 2, cr0, [r9, #952] @ 0x3b8 │ │ streq ip, [r5], #3860 @ 0xf14 │ │ - ldc2l 6, cr4, [sl, #588] @ 0x24c │ │ + ldc2l 6, cr4, [sl, #768] @ 0x300 │ │ ldc2l 3, cr4, [fp, #532] @ 0x214 │ │ │ │ 02493028 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ @@ -1388314,16 +1388314,16 @@ │ │ add r0, pc, r0 │ │ bl 270da10 │ │ mov r0, r4 │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, sl, fp, pc} │ │ - ldc2l 1, cr2, [sl, #616] @ 0x268 │ │ - ldc2l 2, cr4, [sl, #456] @ 0x1c8 │ │ + ldc2l 1, cr2, [sl, #796] @ 0x31c │ │ + ldc2l 2, cr4, [sl, #636] @ 0x27c │ │ │ │ 02493084 : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #32 │ │ mov r3, r1 │ │ mov r1, r0 │ │ @@ -1388424,15 +1388424,15 @@ │ │ add r0, pc, r0 │ │ bl 270ea50 │ │ mov r0, r6 │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - vcadd.f32 q11, , q2, #270 │ │ + ldc2l 8, cr6, [r9, #452] @ 0x1c4 │ │ strbteq r6, [r2], #-688 @ 0xfffffd50 │ │ │ │ 02493214 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r4, r2 │ │ @@ -1388519,17 +1388519,17 @@ │ │ ldr r0, [pc, #28] @ 2493380 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2l 6, cr8, [r8, #572] @ 0x23c │ │ + ldc2l 6, cr8, [r8, #752] @ 0x2f0 │ │ eoreq r6, ip, r0, asr #6 │ │ - ldc2l 6, cr8, [r8, #140] @ 0x8c │ │ + ldc2l 6, cr8, [r8, #320] @ 0x140 │ │ │ │ 02493384 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r4, r3 │ │ mov r5, r2 │ │ @@ -1388616,17 +1388616,17 @@ │ │ mov r1, #5 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldc2l 11, cr3, [fp, #628] @ 0x274 @ │ │ - ldc2l 6, cr12, [r8, #704] @ 0x2c0 │ │ - ldc2l 10, cr15, [r8, #468] @ 0x1d4 @ │ │ - ldc2l 3, cr2, [r9, #832] @ 0x340 │ │ + ldc2l 6, cr12, [r8, #884] @ 0x374 │ │ + ldc2l 10, cr15, [r8, #648] @ 0x288 @ │ │ + ldc2l 3, cr2, [r9, #1012] @ 0x3f4 │ │ ldc2l 11, cr3, [fp, #132] @ 0x84 @ │ │ │ │ 024934fc : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #36 @ 0x24 │ │ mov r5, r1 │ │ @@ -1389160,44 +1389160,44 @@ │ │ ldr r0, [pc, #136] @ 2493dc8 │ │ mov r1, #8 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 2, cr8, [r8, #152] @ 0x98 │ │ + ldc2l 2, cr8, [r8, #332] @ 0x14c │ │ ldc2l 15, cr1, [r8, #388] @ 0x184 │ │ - ldc2l 6, cr15, [r8, #1012] @ 0x3f4 │ │ + ldc2l 7, cr15, [r8, #168] @ 0xa8 │ │ ldc2l 11, cr11, [sl, #780] @ 0x30c @ │ │ - ldc2l 6, cr15, [r8, #340] @ 0x154 │ │ + ldc2l 6, cr15, [r8, #520] @ 0x208 │ │ eoreq r5, ip, r8, asr sp │ │ ldc2l 8, cr13, [sl, #584] @ 0x248 │ │ - ldc2l 5, cr15, [r8, #676] @ 0x2a4 │ │ + ldc2l 5, cr15, [r8, #856] @ 0x358 │ │ mlaeq ip, r0, ip, r5 │ │ - ldc2l 9, cr3, [sl, #66] @ 0x42 @ │ │ + ldc2l 9, cr3, [sl, #156] @ 0x9c @ │ │ ldc2l 13, cr1, [r8, #356] @ 0x164 │ │ - ldc2l 5, cr15, [r8, #20] │ │ + ldc2l 5, cr15, [r8, #200] @ 0xc8 │ │ ldc2l 9, cr11, [sl, #422] @ 0x1a6 @ │ │ - ldc2l 4, cr15, [r8, #404] @ 0x194 │ │ + ldc2l 4, cr15, [r8, #584] @ 0x248 │ │ eoreq r5, ip, r4, ror fp │ │ - ldc2l 13, cr13, [r8, #540] @ 0x21c │ │ - ldc2l 2, cr15, [r8, #260] @ 0x104 │ │ - ldc2l 5, cr7, [r9, #436] @ 0x1b4 │ │ + ldc2l 13, cr13, [r8, #720] @ 0x2d0 │ │ + ldc2l 2, cr15, [r8, #440] @ 0x1b8 │ │ + ldc2l 5, cr7, [r9, #616] @ 0x268 │ │ ldc2l 1, cr4, [r8, #340] @ 0x154 │ │ - ldc2l 3, cr15, [r8, #68] @ 0x44 │ │ - ldc2l 12, cr7, [r8, #596] @ 0x254 │ │ + ldc2l 3, cr15, [r8, #248] @ 0xf8 │ │ + ldc2l 12, cr7, [r8, #776] @ 0x308 │ │ eoreq r5, ip, r8, lsr #22 │ │ ldc2l 4, cr3, [fp, #412] @ 0x19c │ │ - ldc2l 3, cr15, [r8, #340] @ 0x154 │ │ + ldc2l 3, cr15, [r8, #520] @ 0x208 │ │ ldc2l 3, cr9, [fp, #200] @ 0xc8 │ │ eoreq r5, ip, r0, lsr #20 │ │ - ldc2l 13, cr7, [r8, #140] @ 0x8c │ │ - ldc2l 2, cr15, [r8, #468] @ 0x1d4 │ │ + ldc2l 13, cr7, [r8, #320] @ 0x140 │ │ + ldc2l 2, cr15, [r8, #648] @ 0x288 │ │ ldc2l 4, cr11, [sl, #268] @ 0x10c │ │ - ldc2l 12, cr7, [r8, #312] @ 0x138 │ │ + ldc2l 12, cr7, [r8, #492] @ 0x1ec │ │ │ │ 02493dcc : │ │ push {r4, r5, r6, r8, r9, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #16 │ │ mov r8, r3 │ │ mov r4, r2 │ │ @@ -1390338,15 +1390338,15 @@ │ │ add r1, pc, r1 │ │ bl 270da60 │ │ ldr r0, [pc, #3116] @ 2495bbc │ │ add r0, pc, r0 │ │ mov r1, #20 │ │ bl 270da10 │ │ b 2494ab4 │ │ - ldc2l 9, cr7, [r8, #342] @ 0x156 @ │ │ + ldc2l 9, cr7, [r8, #432] @ 0x1b0 @ │ │ ldr r1, [pc, #3096] @ 2495bc0 │ │ add lr, sp, #1536 @ 0x600 │ │ add r0, lr, #11 │ │ mov r2, #80 @ 0x50 │ │ add r1, pc, r1 │ │ mov r3, #10 │ │ sub r5, fp, #1120 @ 0x460 │ │ @@ -1390378,22 +1390378,22 @@ │ │ bl 270da00 │ │ ldr r4, [pc, #2980] @ 2495bd0 │ │ add lr, sp, #1536 @ 0x600 │ │ add r1, lr, #11 │ │ add r4, pc, r4 │ │ b 2494ea4 │ │ streq fp, [r5], #2852 @ 0xb24 │ │ - ldc2l 7, cr1, [r9, #64] @ 0x40 │ │ + ldc2l 7, cr1, [r9, #244] @ 0xf4 │ │ streq fp, [r5], #3660 @ 0xe4c │ │ ldc2l 6, cr1, [r8, #956] @ 0x3bc │ │ streq fp, [r5], #2796 @ 0xaec │ │ eoreq r5, ip, r3, asr #12 │ │ eoreq r5, ip, r8, asr #12 │ │ ldc2l 12, cr5, [r8, #856] @ 0x358 │ │ - ldc2l 10, cr1, [r9, #288] @ 0x120 @ │ │ + ldc2l 10, cr1, [r9, #468] @ 0x1d4 @ │ │ streq fp, [r5], #3460 @ 0xd84 │ │ ldr r0, [pc, #2924] @ 2495bd4 │ │ add lr, sp, #1024 @ 0x400 │ │ add r1, lr, #120 @ 0x78 │ │ add r0, pc, r0 │ │ bl 270d1a0 │ │ add r0, sp, #528 @ 0x210 │ │ @@ -1390423,25 +1390423,25 @@ │ │ str r0, [sp, #56] @ 0x38 │ │ mov r0, #1 │ │ vldr d8, [pc, #852] @ 2495438 │ │ str r2, [sp, #40] @ 0x28 │ │ str r1, [sp, #36] @ 0x24 │ │ str r0, [fp, #-1076] @ 0xfffffbcc │ │ b 2495154 │ │ - ldc2l 2, cr15, [r9, #648] @ 0x288 │ │ - ldc2l 8, cr7, [r8, #608] @ 0x260 │ │ - ldc2l 9, cr1, [r9, #316] @ 0x13c @ │ │ + ldc2l 2, cr15, [r9, #828] @ 0x33c │ │ + vcadd.f32 , q12, , #270 │ │ + ldc2l 9, cr1, [r9, #406] @ 0x196 @ │ │ streq fp, [r5], #2732 @ 0xaac │ │ ldc2l 2, cr15, [r7, #304] @ 0x130 │ │ - ldc2l 1, cr15, [r9, #984] @ 0x3d8 │ │ + ldc2l 2, cr15, [r9, #140] @ 0x8c │ │ ldc2l 2, cr15, [r7, #48] @ 0x30 │ │ ldc2l 6, cr10, [fp, #232] @ 0xe8 │ │ streq fp, [r5], #3072 @ 0xc00 │ │ ldc2l 0, cr13, [sl, #268] @ 0x10c │ │ - ldc2l 1, cr15, [r9, #296] @ 0x128 │ │ + ldc2l 1, cr15, [r9, #476] @ 0x1dc │ │ ldc2l 0, cr13, [sl, #12] │ │ ldc2l 1, cr15, [r7, #300] @ 0x12c │ │ add lr, sp, #1024 @ 0x400 │ │ add r0, lr, #120 @ 0x78 │ │ add r2, r0, r1, lsl #3 │ │ ldr r1, [pc, #2720] @ 2495bd8 │ │ sub r0, fp, #1488 @ 0x5d0 │ │ @@ -1390540,15 +1390540,15 @@ │ │ bhi 24952c8 │ │ sub r0, fp, #484 @ 0x1e4 │ │ str r6, [r0, r1, lsl #2] │ │ mov r6, r0 │ │ b 2495318 │ │ streq fp, [r5], #2260 @ 0x8d4 │ │ ldc2l 2, cr9, [sl, #428] @ 0x1ac │ │ - ldc2l 0, cr15, [r9, #632] @ 0x278 │ │ + ldc2l 0, cr15, [r9, #812] @ 0x32c │ │ ldr r0, [pc, #3804] @ 24961ac │ │ movw r3, #1157 @ 0x485 │ │ ldr r2, [pc, #3800] @ 24961b0 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [fp, #-1076] @ 0xfffffbcc │ │ @@ -1390571,19 +1390571,19 @@ │ │ ldr r0, [fp, #-1076] @ 0xfffffbcc │ │ sub r6, r0, #1 │ │ cmp r6, #2 │ │ bcs 2495358 │ │ mov r1, r6 │ │ b 24953a4 │ │ ldc2l 2, cr9, [sl, #172] @ 0xac │ │ - ldc2l 6, cr5, [r9, #756] @ 0x2f4 │ │ + ldc2l 6, cr5, [r9, #936] @ 0x3a8 │ │ streq fp, [r5], #2280 @ 0x8e8 │ │ - vcadd.f32 d27, d8, d1, #270 │ │ - ldc2l 15, cr14, [r9, #968] @ 0x3c8 │ │ - ldc2l 7, cr11, [r8, #772] @ 0x304 │ │ + vcadd.f32 d27, d8, d30, #270 │ │ + ldc2l 0, cr15, [r9, #124] @ 0x7c │ │ + ldc2l 7, cr11, [r8, #952] @ 0x3b8 │ │ ldc2l 7, cr6, [fp, #476] @ 0x1dc │ │ ldr r0, [pc, #3676] @ 24961bc │ │ mov r1, r6 │ │ ldr r2, [pc, #3672] @ 24961c0 │ │ movw r3, #1189 @ 0x4a5 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1390629,17 +1390629,17 @@ │ │ cmp r6, #2 │ │ bcs 2495444 │ │ ldr r4, [pc, #3512] @ 24961d4 │ │ mov r1, r6 │ │ add r4, pc, r4 │ │ b 2495490 │ │ streq fp, [r5], #2300 @ 0x8fc │ │ - ldc2l 5, cr5, [r9, #816] @ 0x330 │ │ - ldc2l 15, cr14, [r9, #280] @ 0x118 │ │ - ldc2l 5, cr5, [r9, #560] @ 0x230 │ │ + ldc2l 5, cr5, [r9, #996] @ 0x3e4 │ │ + ldc2l 15, cr14, [r9, #460] @ 0x1cc │ │ + ldc2l 5, cr5, [r9, #740] @ 0x2e4 │ │ ldc2l 13, cr12, [sl, #920] @ 0x398 │ │ andeq r0, r0, r0 │ │ cdpcc 0, 4, cr0, cr0, cr0, {0} │ │ streq fp, [r5], #2256 @ 0x8d0 │ │ ldr r4, [pc, #3468] @ 24961d8 │ │ mov r1, r6 │ │ ldr r2, [pc, #3464] @ 24961dc │ │ @@ -1390677,46 +1390677,46 @@ │ │ ldr r0, [fp, #-1076] @ 0xfffffbcc │ │ sub r6, r0, #1 │ │ cmp r6, #2 │ │ bcs 2495570 │ │ mov r1, r6 │ │ b 24955b4 │ │ ldc2l 9, cr8, [fp, #494] @ 0x1ee @ │ │ - ldc2l 14, cr14, [r9, #616] @ 0x268 │ │ + ldc2l 14, cr14, [r9, #796] @ 0x31c │ │ ldc2l 9, cr8, [fp, #366] @ 0x16e @ │ │ ldc2l 14, cr14, [r7, #648] @ 0x288 │ │ streq fp, [r5], #1892 @ 0x764 │ │ - ldc2l 4, cr5, [r9, #492] @ 0x1ec │ │ - ldc2l 13, cr14, [r9, #952] @ 0x3b8 │ │ - ldc2l 4, cr5, [r9, #236] @ 0xec │ │ + ldc2l 4, cr5, [r9, #672] @ 0x2a0 │ │ + ldc2l 14, cr14, [r9, #108] @ 0x6c │ │ + ldc2l 4, cr5, [r9, #416] @ 0x1a0 │ │ ldc2l 12, cr12, [sl, #596] @ 0x254 │ │ streq fp, [r5], #1656 @ 0x678 │ │ - ldc2l 4, cr6, [r9, #960] @ 0x3c0 │ │ - ldc2l 13, cr14, [r9, #264] @ 0x108 │ │ - ldc2l 4, cr6, [r9, #704] @ 0x2c0 │ │ - ldc2l 5, cr7, [r9, #564] @ 0x234 │ │ + ldc2l 5, cr6, [r9, #116] @ 0x74 │ │ + ldc2l 13, cr14, [r9, #444] @ 0x1bc │ │ + ldc2l 4, cr6, [r9, #884] @ 0x374 │ │ + ldc2l 5, cr7, [r9, #744] @ 0x2e8 │ │ streq fp, [r5], #1164 @ 0x48c │ │ ldc2l 3, cr5, [r8, #316] @ 0x13c │ │ - ldc2l 12, cr14, [r9, #600] @ 0x258 │ │ + ldc2l 12, cr14, [r9, #780] @ 0x30c │ │ ldc2l 3, cr5, [r8, #60] @ 0x3c │ │ - ldc2l 4, cr7, [r9, #924] @ 0x39c │ │ + ldc2l 5, cr7, [r9, #80] @ 0x50 │ │ streq fp, [r5], #1120 @ 0x460 │ │ - ldc2l 4, cr11, [r8, #8] │ │ - ldc2l 11, cr14, [r9, #936] @ 0x3a8 @ │ │ - ldc2l 3, cr11, [r8, #776] @ 0x308 │ │ - ldc2l 2, cr1, [r9, #948] @ 0x3b4 │ │ + ldc2l 4, cr11, [r8, #188] @ 0xbc │ │ + ldc2l 12, cr14, [r9, #92] @ 0x5c │ │ + ldc2l 3, cr11, [r8, #956] @ 0x3bc │ │ + ldc2l 3, cr1, [r9, #104] @ 0x68 │ │ streq fp, [r5], #1460 @ 0x5b4 │ │ ldc2l 13, cr11, [fp, #380] @ 0x17c │ │ - ldc2l 11, cr14, [r9, #264] @ 0x108 @ │ │ + ldc2l 11, cr14, [r9, #444] @ 0x1bc @ │ │ ldc2l 13, cr11, [fp, #140] @ 0x8c │ │ ldc2l 12, cr8, [sl, #740] @ 0x2e4 │ │ streq fp, [r5], #1168 @ 0x490 │ │ - ldc2l 10, cr14, [r9, #744] @ 0x2e8 @ │ │ - ldc2l 1, cr1, [r9, #912] @ 0x390 │ │ - ldc2l 1, cr3, [r9, #564] @ 0x234 │ │ + ldc2l 10, cr14, [r9, #924] @ 0x39c @ │ │ + ldc2l 2, cr1, [r9, #68] @ 0x44 │ │ + ldc2l 1, cr3, [r9, #744] @ 0x2e8 │ │ streq fp, [r5], #504 @ 0x1f8 │ │ eoreq r4, ip, ip, ror sp │ │ ldr r2, [pc, #3912] @ 24964c0 │ │ mov r0, r4 │ │ mov r1, r6 │ │ movw r3, #1198 @ 0x4ae │ │ add r2, pc, r2 │ │ @@ -1390971,18 +1390971,18 @@ │ │ mov r0, r5 │ │ mov r1, r7 │ │ mov r2, r6 │ │ str r4, [sp] │ │ bl 270f9e0 │ │ b 2496590 │ │ ldc2l 3, cr3, [r8, #852] @ 0x354 │ │ - ldc2l 12, cr8, [r9, #352] @ 0x160 │ │ + ldc2l 12, cr8, [r9, #532] @ 0x214 │ │ eoreq r4, ip, ip, ror #24 │ │ - ldc2l 15, cr6, [r8, #124] @ 0x7c │ │ - ldc2l 12, cr8, [r9, #24] │ │ + ldc2l 15, cr6, [r8, #304] @ 0x130 │ │ + ldc2l 12, cr8, [r9, #204] @ 0xcc │ │ ldc2l 1, cr0, [fp, #40] @ 0x28 │ │ ldrdeq r4, [ip], -r4 @ │ │ cmp r1, #2 │ │ bcc 24959bc │ │ ldr r0, [pc, #3948] @ 2496914 │ │ movw r3, #1208 @ 0x4b8 │ │ ldr r2, [pc, #3944] @ 2496918 │ │ @@ -1391106,31 +1391106,31 @@ │ │ ldc2l 8, cr11, [fp, #80] @ 0x50 │ │ eoreq r4, ip, r0, asr #18 │ │ ldc2l 7, cr6, [sl, #404] @ 0x194 │ │ streq sl, [r5], #3420 @ 0xd5c │ │ streq fp, [r5], #76 @ 0x4c │ │ eoreq r4, ip, r0, lsl #17 │ │ ldc2l 6, cr6, [sl, #924] @ 0x39c │ │ - ldc2l 0, cr14, [r8, #388] @ 0x184 │ │ - ldc2l 4, cr12, [r9, #636] @ 0x27c │ │ + ldc2l 0, cr14, [r8, #568] @ 0x238 │ │ + ldc2l 4, cr12, [r9, #816] @ 0x330 │ │ ldc2l 13, cr15, [sl, #308] @ 0x134 │ │ - ldc2l 0, cr14, [r8, #4] │ │ + ldc2l 0, cr14, [r8, #184] @ 0xb8 │ │ ldc2l 3, cr12, [sl, #756] @ 0x2f4 │ │ - ldc2l 15, cr13, [r8, #836] @ 0x344 │ │ + ldc2l 15, cr13, [r8, #1016] @ 0x3f8 │ │ ldc2l 5, cr4, [sl, #60] @ 0x3c │ │ ldc2l 15, cr7, [fp, #564] @ 0x234 │ │ ldc2l 14, cr3, [fp, #824] @ 0x338 │ │ - ldc2l 9, cr8, [r8, #58] @ 0x3a @ │ │ - ldc2l 10, cr6, [r8, #68] @ 0x44 @ │ │ + ldc2l 9, cr8, [r8, #148] @ 0x94 @ │ │ + ldc2l 10, cr6, [r8, #248] @ 0xf8 @ │ │ ldc2l 14, cr4, [r8, #452] @ 0x1c4 │ │ - ldc2l 3, cr2, [sl, #644] @ 0x284 │ │ - ldc2l 14, cr13, [r8, #836] @ 0x344 │ │ + ldc2l 3, cr2, [sl, #824] @ 0x338 │ │ + ldc2l 14, cr13, [r8, #1016] @ 0x3f8 │ │ mlaeq ip, ip, r6, r4 │ │ eoreq r4, ip, r8, asr #11 │ │ - ldc2l 9, cr0, [r9, #300] @ 0x12c @ │ │ + ldc2l 9, cr0, [r9, #390] @ 0x186 @ │ │ ldc2l 12, cr4, [r8, #104] @ 0x68 │ │ cmp r1, #2 │ │ bcc 2495c08 │ │ ldr r0, [pc, #3412] @ 2496948 │ │ movw r3, #1238 @ 0x4d6 │ │ ldr r2, [pc, #3408] @ 249694c │ │ add r0, pc, r0 │ │ @@ -1391694,23 +1391694,23 @@ │ │ bl 270e810 │ │ b 2496cd0 │ │ ldc2l 9, cr1, [r8, #278] @ 0x116 @ │ │ streq sl, [r5], #2540 @ 0x9ec │ │ vcadd.f32 d20, d8, d10, #270 │ │ ldc2l 7, cr4, [r8, #904] @ 0x388 │ │ ldc2l 7, cr4, [r8, #600] @ 0x258 │ │ - ldc2l 2, cr8, [r8, #752] @ 0x2f0 │ │ + ldc2l 2, cr8, [r8, #932] @ 0x3a4 │ │ ldc2l 7, cr4, [r8, #264] @ 0x108 │ │ ldc2l 10, cr1, [fp, #600] @ 0x258 @ │ │ ldc2l 6, cr4, [r8, #952] @ 0x3b8 │ │ ldc2l 1, cr9, [fp, #592] @ 0x250 │ │ ldc2l 1, cr9, [fp, #388] @ 0x184 │ │ ldc2l 6, cr4, [r8, #600] @ 0x258 │ │ - ldc2l 10, cr15, [r9, #844] @ 0x34c @ │ │ - ldc2l 2, cr4, [r9, #884] @ 0x374 │ │ + ldc2l 11, cr15, [r9] @ │ │ + ldc2l 3, cr4, [r9, #40] @ 0x28 │ │ ldc2l 6, cr4, [r8, #248] @ 0xf8 │ │ streq sl, [r5], #1276 @ 0x4fc │ │ ldc2l 12, cr13, [r7, #348] @ 0x15c │ │ ldc2l 5, cr4, [r8, #856] @ 0x358 │ │ streq sl, [r5], #944 @ 0x3b0 │ │ cmp r0, #0 │ │ beq 249659c │ │ @@ -1391901,15 +1391901,15 @@ │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #4088] @ 24977f8 │ │ add r0, pc, r0 │ │ b 2496974 │ │ eoreq r3, ip, ip, ror #29 │ │ - ldc2l 4, cr14, [r8, #188] @ 0xbc │ │ + ldc2l 4, cr14, [r8, #368] @ 0x170 │ │ ldr r0, [fp, #-1076] @ 0xfffffbcc │ │ sub r1, r0, #1 │ │ cmp r1, #2 │ │ bcc 2496838 │ │ ldr r0, [pc, #4056] @ 24977fc │ │ movw r3, #1748 @ 0x6d4 │ │ ldr r2, [pc, #4052] @ 2497800 │ │ @@ -1391967,28 +1391967,28 @@ │ │ add r8, sp, #920 @ 0x398 │ │ sub r1, r0, #1 │ │ cmp r1, #2 │ │ bcs 2496950 │ │ ldr r0, [pc, #3856] @ 249781c │ │ add r0, pc, r0 │ │ b 2496974 │ │ - ldc2l 14, cr15, [r8, #80] @ 0x50 │ │ + ldc2l 14, cr15, [r8, #260] @ 0x104 │ │ ldc2l 8, cr11, [sl, #1000] @ 0x3e8 │ │ ldc2l 3, cr4, [r8, #872] @ 0x368 │ │ streq sl, [r5], #984 @ 0x3d8 │ │ ldc2l 1, cr5, [fp, #540] @ 0x21c │ │ ldc2l 3, cr4, [r8, #520] @ 0x208 │ │ streq sl, [r5], #768 @ 0x300 │ │ ldc2l 9, cr13, [r7, #342] @ 0x156 @ │ │ ldc2l 3, cr4, [r8, #168] @ 0xa8 │ │ streq sl, [r5], #268 @ 0x10c │ │ eoreq r3, ip, r8, asr #24 │ │ ldc2l 12, cr9, [sl, #280] @ 0x118 │ │ ldc2l 2, cr4, [r8, #648] @ 0x288 │ │ - ldc2l 12, cr15, [r8, #208] @ 0xd0 │ │ + ldc2l 12, cr15, [r8, #388] @ 0x184 │ │ ldc2l 6, cr11, [sl, #696] @ 0x2b8 │ │ ldc2l 1, cr4, [r8, #568] @ 0x238 │ │ ldr r0, [pc, #4064] @ 2497938 │ │ movw r3, #1770 @ 0x6ea │ │ ldr r2, [pc, #4060] @ 249793c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1392167,15 +1392167,15 @@ │ │ ldc2l 15, cr4, [fp, #236] @ 0xec │ │ ldc2l 1, cr4, [r8, #216] @ 0xd8 │ │ streq sl, [r5], #180 @ 0xb4 │ │ ldc2l 7, cr13, [r7, #380] @ 0x17c │ │ ldc2l 0, cr4, [r8, #888] @ 0x378 │ │ streq r9, [r5], #3776 @ 0xec0 │ │ strdeq r3, [ip], -ip @ │ │ - ldc2l 13, cr3, [r9, #4] │ │ + ldc2l 13, cr3, [r9, #184] @ 0xb8 │ │ ldc2l 0, cr4, [r8, #392] @ 0x188 │ │ streq r9, [r5], #3864 @ 0xf18 │ │ cmp r0, #2 │ │ bcc 2496c60 │ │ ldr r0, [pc, #4088] @ 2497c44 │ │ mov r3, #1872 @ 0x750 │ │ ldr r2, [pc, #4084] @ 2497c48 │ │ @@ -1392390,15 +1392390,15 @@ │ │ ldr r7, [pc, #4052] @ 2497f6c │ │ add r8, r1, #8 │ │ sub r9, fp, #472 @ 0x1d8 │ │ sub r4, fp, #1904 @ 0x770 │ │ add r7, pc, r7 │ │ mov r5, #7 │ │ b 2496fec │ │ - ldc2l 7, cr15, [r8] │ │ + ldc2l 7, cr15, [r8, #180] @ 0xb4 │ │ streq r9, [r5], #3592 @ 0xe08 │ │ streq r9, [r5], #3564 @ 0xdec │ │ ldc2l 6, cr9, [sl, #184] @ 0xb8 │ │ add r3, r9, r1, lsl #3 │ │ mov r0, r8 │ │ mov r1, r4 │ │ mov r2, r7 │ │ @@ -1392745,15 +1392745,15 @@ │ │ str r0, [sp] │ │ add r2, r1, #4 │ │ add r3, r1, #8 │ │ sub r0, fp, #472 @ 0x1d8 │ │ bl 270f7b0 │ │ b 24979fc │ │ streq r9, [r5], #2016 @ 0x7e0 │ │ - ldc2l 1, cr15, [r8, #912] @ 0x390 │ │ + ldc2l 2, cr15, [r8, #68] @ 0x44 │ │ ldr r0, [pc, #3200] @ 24981c4 │ │ mov r1, #205 @ 0xcd │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #3188] @ 24981c8 │ │ add lr, sp, #1024 @ 0x400 │ │ add r1, lr, #808 @ 0x328 │ │ @@ -1392819,27 +1392819,27 @@ │ │ cmp r0, r1 │ │ bne 2497e50 │ │ sub lr, fp, #2048 @ 0x800 │ │ mov r1, r4 │ │ sub r0, lr, #152 @ 0x98 │ │ bl 270fc30 │ │ b 2497908 │ │ - ldc2l 5, cr9, [r8, #320] @ 0x140 │ │ + ldc2l 5, cr9, [r8, #500] @ 0x1f4 │ │ ldc2l 9, cr12, [sl, #288] @ 0x120 @ │ │ ldc2l 6, cr14, [sl, #332] @ 0x14c │ │ - ldc2l 4, cr15, [r8, #164] @ 0xa4 │ │ + ldc2l 4, cr15, [r8, #344] @ 0x158 │ │ ldc2l 6, cr3, [r8, #664] @ 0x298 │ │ streq r9, [r5], #1740 @ 0x6cc │ │ eoreq r2, ip, r8, asr #31 │ │ ldc2l 8, cr12, [sl, #864] @ 0x360 │ │ - ldc2l 4, cr5, [r9, #868] @ 0x364 │ │ + ldc2l 5, cr5, [r9, #24] │ │ ldc2l 6, cr3, [r8, #56] @ 0x38 │ │ streq r9, [r5], #960 @ 0x3c0 │ │ eoreq r2, ip, ip, lsr pc │ │ - ldc2l 4, cr5, [r9, #444] @ 0x1bc │ │ + ldc2l 4, cr5, [r9, #624] @ 0x270 │ │ ldc2l 5, cr3, [r8, #632] @ 0x278 │ │ ldr r2, [pc, #2912] @ 2498200 │ │ sub lr, fp, #1024 @ 0x400 │ │ ldr r3, [pc, #2908] @ 2498204 │ │ mov r0, #32 │ │ sub r7, lr, #60 @ 0x3c │ │ add r1, sp, #904 @ 0x388 │ │ @@ -1392922,15 +1392922,15 @@ │ │ mov r0, r5 │ │ mov r2, #1 │ │ mov r3, #13 │ │ add r1, pc, r1 │ │ bl 270da60 │ │ b 2497e1c │ │ streq r9, [r5], #1008 @ 0x3f0 │ │ - ldc2l 2, cr1, [r9, #708] @ 0x2c4 │ │ + ldc2l 2, cr1, [r9, #888] @ 0x378 │ │ ldc2l 5, cr3, [r8, #376] @ 0x178 │ │ streq r9, [r5], #1548 @ 0x60c │ │ mlaeq ip, r0, lr, r2 │ │ ldc2l 11, cr12, [r7, #440] @ 0x1b8 @ │ │ ldc2l 4, cr3, [r8, #920] @ 0x398 │ │ streq r9, [r5], #1048 @ 0x418 │ │ eoreq r2, ip, r4, lsl lr │ │ @@ -1393343,15 +1393343,15 @@ │ │ sub r1, fp, #1072 @ 0x430 │ │ mov r2, #36 @ 0x24 │ │ bl 270db10 │ │ ldr r0, [pc, #756] @ 249817c │ │ mov r1, #212 @ 0xd4 │ │ add r0, pc, r0 │ │ b 24980a0 │ │ - ldc2l 13, cr0, [r9, #124] @ 0x7c │ │ + ldc2l 13, cr0, [r9, #304] @ 0x130 │ │ strhteq r2, [ip], -r7 │ │ ldr r0, [pc, #1024] @ 24982a0 │ │ mov r1, #215 @ 0xd7 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #1012] @ 24982a4 │ │ add lr, sp, #1024 @ 0x400 │ │ @@ -1393381,15 +1393381,15 @@ │ │ ldr r4, [pc, #876] @ 2498280 │ │ ldr r5, [pc, #876] @ 2498284 │ │ ldr r8, [pc, #876] @ 2498288 │ │ add r4, pc, r4 │ │ add r5, pc, r5 │ │ add r8, pc, r8 │ │ b 2497f54 │ │ - ldc2l 12, cr8, [r8, #472] @ 0x1d8 │ │ + ldc2l 12, cr8, [r8, #652] @ 0x28c │ │ strhteq r2, [ip], -r0 │ │ ldr r2, [sp, #72] @ 0x48 │ │ add r0, r9, r7, lsl #3 │ │ add r1, r2, r1, lsl #3 │ │ bl 270f010 │ │ ldr r1, [fp, #-1076] @ 0xfffffbcc │ │ add r0, r1, #1 │ │ @@ -1393416,15 +1393416,15 @@ │ │ bcc 2497f30 │ │ mov r0, r4 │ │ mov r2, r5 │ │ movw r3, #2273 @ 0x8e1 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2497f30 │ │ - ldc2l 11, cr0, [r9, #668] @ 0x29c @ │ │ + ldc2l 11, cr0, [r9, #848] @ 0x350 @ │ │ ldr r0, [pc, #560] @ 24981f0 │ │ movw r1, #322 @ 0x142 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #548] @ 24981f4 │ │ add lr, sp, #1024 @ 0x400 │ │ add r1, lr, #808 @ 0x328 │ │ @@ -1393494,16 +1393494,16 @@ │ │ mov r3, #36 @ 0x24 │ │ mov r1, r5 │ │ bl 270da60 │ │ ldr r1, [pc, #160] @ 2498184 │ │ add r1, pc, r1 │ │ b 24974d4 │ │ ldc2l 12, cr2, [r8, #632] @ 0x278 │ │ - ldc2l 10, cr12, [r8, #576] @ 0x240 @ │ │ - ldc2l 13, cr11, [r8, #836] @ 0x344 │ │ + ldc2l 10, cr12, [r8, #756] @ 0x2f4 @ │ │ + ldc2l 13, cr11, [r8, #1016] @ 0x3f8 │ │ ldc2l 13, cr5, [fp, #756] @ 0x2f4 │ │ ldr r0, [pc, #252] @ 24981fc │ │ add r0, pc, r0 │ │ movw r1, #310 @ 0x136 │ │ bl 270da00 │ │ ldr r4, [pc, #196] @ 24981d4 │ │ add lr, sp, #1024 @ 0x400 │ │ @@ -1393518,101 +1393518,101 @@ │ │ mov r2, #1 │ │ bl 270db00 │ │ ldr r0, [pc, #152] @ 24981d8 │ │ mov r1, #24 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ b 2494ab4 │ │ - ldc2l 9, cr2, [r9, #50] @ 0x32 @ │ │ + ldc2l 9, cr2, [r9, #140] @ 0x8c @ │ │ eoreq r2, ip, r4, lsr r5 │ │ ldc2l 6, cr14, [r7, #1020] @ 0x3fc │ │ ldc2l 3, cr4, [sl, #800] @ 0x320 │ │ ldc2l 9, cr3, [fp, #500] @ 0x1f4 @ │ │ ldc2l 11, cr15, [sl, #648] @ 0x288 @ │ │ - ldc2l 10, cr11, [r8, #372] @ 0x174 @ │ │ + ldc2l 10, cr11, [r8, #552] @ 0x228 @ │ │ ldc2l 0, cr4, [sl, #516] @ 0x204 │ │ - ldc2l 5, cr14, [r8, #172] @ 0xac │ │ + ldc2l 5, cr14, [r8, #352] @ 0x160 │ │ eoreq r2, ip, r8, lsl #2 │ │ - ldc2l 0, cr10, [r9, #300] @ 0x12c │ │ + ldc2l 0, cr10, [r9, #480] @ 0x1e0 │ │ streq r8, [r5], #1320 @ 0x528 │ │ - ldc2l 11, cr1, [r9, #720] @ 0x2d0 @ │ │ - ldc2l 14, cr10, [r8, #308] @ 0x134 │ │ - ldc2l 5, cr9, [r9, #556] @ 0x22c │ │ + ldc2l 11, cr1, [r9, #900] @ 0x384 @ │ │ + ldc2l 14, cr10, [r8, #488] @ 0x1e8 │ │ + ldc2l 5, cr9, [r9, #736] @ 0x2e0 │ │ ldc2l 15, cr11, [r7, #84] @ 0x54 │ │ - ldc2l 14, cr3, [r9, #104] @ 0x68 │ │ - ldc2l 14, cr10, [r8, #804] @ 0x324 │ │ - ldc2l 2, cr14, [r8, #852] @ 0x354 │ │ + ldc2l 14, cr3, [r9, #284] @ 0x11c │ │ + ldc2l 14, cr10, [r8, #984] @ 0x3d8 │ │ + ldc2l 3, cr14, [r8, #8] │ │ eoreq r1, ip, r8, lsr #29 │ │ - ldc2l 13, cr9, [r9, #940] @ 0x3ac │ │ + ldc2l 14, cr9, [r9, #96] @ 0x60 │ │ streq r8, [r5], #712 @ 0x2c8 │ │ - ldc2l 10, cr15, [r8, #272] @ 0x110 @ │ │ + ldc2l 10, cr15, [r8, #452] @ 0x1c4 @ │ │ eoreq r1, ip, r8, lsr lr │ │ eoreq r1, ip, ip, lsl lr │ │ eoreq r1, ip, ip, lsl #28 │ │ - ldc2l 2, cr15, [r9, #972] @ 0x3cc │ │ + ldc2l 3, cr15, [r9, #128] @ 0x80 │ │ eoreq r1, ip, ip, ror #27 │ │ streq r8, [r5], #1252 @ 0x4e4 │ │ eoreq r1, ip, ip, lsl sp │ │ ldc2l 15, cr1, [sl, #256] @ 0x100 │ │ - ldc2l 9, cr11, [r8, #330] @ 0x14a @ │ │ + ldc2l 9, cr11, [r8, #420] @ 0x1a4 @ │ │ ldc2l 15, cr3, [sl, #784] @ 0x310 │ │ ldc2l 5, cr11, [r7, #996] @ 0x3e4 │ │ - ldc2l 13, cr10, [r8, #932] @ 0x3a4 │ │ + ldc2l 14, cr10, [r8, #88] @ 0x58 │ │ ldc2l 5, cr6, [fp, #1004] @ 0x3ec │ │ ldc2l 10, cr13, [r7, #100] @ 0x64 @ │ │ - ldc2l 1, cr11, [r8, #596] @ 0x254 │ │ + ldc2l 1, cr11, [r8, #776] @ 0x308 │ │ ldc2l 7, cr1, [sl, #584] @ 0x248 │ │ - ldc2l 1, cr11, [r8, #164] @ 0xa4 │ │ + ldc2l 1, cr11, [r8, #344] @ 0x158 │ │ ldc2l 7, cr8, [fp, #700] @ 0x2bc │ │ ldc2l 14, cr15, [r7, #328] @ 0x148 │ │ - ldc2l 15, cr10, [r8, #164] @ 0xa4 │ │ - ldc2l 4, cr13, [r8, #492] @ 0x1ec │ │ - ldc2l 10, cr9, [r8, #960] @ 0x3c0 @ │ │ + ldc2l 15, cr10, [r8, #344] @ 0x158 │ │ + ldc2l 4, cr13, [r8, #672] @ 0x2a0 │ │ + ldc2l 11, cr9, [r8, #116] @ 0x74 @ │ │ eoreq r2, ip, pc │ │ eoreq r2, ip, ip, lsr r0 │ │ ldc2l 10, cr15, [sl, #428] @ 0x1ac @ │ │ - ldc2l 7, cr11, [r8, #420] @ 0x1a4 │ │ + ldc2l 7, cr11, [r8, #600] @ 0x258 │ │ vcadd.f32 , q5, q2, #270 │ │ ldc2l 5, cr15, [sl, #780] @ 0x30c │ │ - ldc2l 3, cr11, [r8, #564] @ 0x234 │ │ + ldc2l 3, cr11, [r8, #744] @ 0x2e8 │ │ ldc2l 12, cr6, [fp, #724] @ 0x2d4 │ │ ldc2l 1, cr2, [r8, #936] @ 0x3a8 │ │ - ldc2l 3, cr11, [r8, #276] @ 0x114 │ │ + ldc2l 3, cr11, [r8, #456] @ 0x1c8 │ │ streq r8, [r5], #472 @ 0x1d8 │ │ eoreq r1, ip, ip, lsl #20 │ │ streq r8, [r5], #424 @ 0x1a8 │ │ ldrdeq r1, [ip], -r8 @ │ │ ldc2l 13, cr7, [sl, #884] @ 0x374 │ │ - ldc2l 5, cr11, [r8, #612] @ 0x264 │ │ + ldc2l 5, cr11, [r8, #792] @ 0x318 │ │ ldc2l 3, cr13, [sl, #440] @ 0x1b8 │ │ eoreq r2, ip, r0, lsl r4 │ │ strdeq r2, [ip], -r4 @ │ │ ldc2l 2, cr9, [fp, #772] @ 0x304 │ │ ldc2l 10, cr2, [r8, #376] @ 0x178 @ │ │ ldc2l 11, cr1, [fp, #40] @ 0x28 @ │ │ ldc2l 10, cr2, [r8, #104] @ 0x68 @ │ │ eoreq r2, ip, ip, lsl r3 │ │ eoreq r1, ip, r4, lsr #24 │ │ - vcadd.f32 , , q12, #270 │ │ + ldc2l 9, cr11, [r9, #42] @ 0x2a @ │ │ ldc2l 2, cr2, [r8, #648] @ 0x288 │ │ streq r8, [r5], #716 @ 0x2cc │ │ strdeq r1, [ip], -r8 @ │ │ ldrdeq r1, [ip], -r0 @ │ │ ldc2l 0, cr13, [sl, #940] @ 0x3ac │ │ ldc2l 1, cr2, [r8, #312] @ 0x138 │ │ - ldc2l 4, cr11, [r9, #720] @ 0x2d0 │ │ + ldc2l 4, cr11, [r9, #900] @ 0x384 │ │ ldc2l 14, cr1, [r8, #440] @ 0x1b8 │ │ ldc2l 6, cr8, [fp, #832] @ 0x340 │ │ eoreq r1, ip, ip, asr #25 │ │ - ldc2l 9, cr11, [r9, #288] @ 0x120 @ │ │ + ldc2l 9, cr11, [r9, #378] @ 0x17a @ │ │ ldc2l 3, cr2, [r8, #296] @ 0x128 │ │ ldc2l 2, cr8, [sl, #476] @ 0x1dc │ │ - ldc2l 10, cr11, [r8, #900] @ 0x384 @ │ │ + ldc2l 11, cr11, [r8, #56] @ 0x38 @ │ │ ldc2l 14, cr1, [r8, #976] @ 0x3d0 │ │ - ldc2l 0, cr11, [r8, #292] @ 0x124 │ │ + ldc2l 0, cr11, [r8, #472] @ 0x1d8 │ │ │ │ 024982a8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #148 @ 0x94 │ │ mov r5, r3 │ │ mov sl, r2 │ │ @@ -1394019,43 +1394019,43 @@ │ │ mov r2, #1 │ │ mov r3, #32 │ │ bl 270da60 │ │ ldr r0, [pc, #100] @ 2498974 │ │ mov r1, #20 │ │ add r0, pc, r0 │ │ b 2498894 │ │ - vcadd.f32 , q12, q11, #270 │ │ + ldc2l 9, cr15, [r8, #38] @ 0x26 @ │ │ ldc2l 3, cr13, [r7, #964] @ 0x3c4 │ │ - ldc2l 11, cr10, [r8, #564] @ 0x234 @ │ │ - ldc2l 14, cr12, [r9] │ │ - ldc2l 10, cr10, [r8, #964] @ 0x3c4 @ │ │ + ldc2l 11, cr10, [r8, #744] @ 0x2e8 @ │ │ + ldc2l 14, cr12, [r9, #180] @ 0xb4 │ │ + ldc2l 11, cr10, [r8, #120] @ 0x78 @ │ │ strhteq r1, [ip], -ip │ │ ldc2l 13, cr8, [sl, #232] @ 0xe8 │ │ - ldc2l 10, cr10, [r8, #324] @ 0x144 @ │ │ + ldc2l 10, cr10, [r8, #504] @ 0x1f8 @ │ │ strdeq r1, [ip], -r8 @ │ │ - ldc2l 13, cr14, [r9, #788] @ 0x314 │ │ + ldc2l 13, cr14, [r9, #968] @ 0x3c8 │ │ ldc2l 1, cr13, [r7, #1012] @ 0x3f4 │ │ - ldc2l 9, cr10, [r8, #338] @ 0x152 @ │ │ - ldc2l 12, cr12, [r9, #64] @ 0x40 │ │ - ldc2l 9, cr10, [r8, #2] @ │ │ + ldc2l 9, cr10, [r8, #428] @ 0x1ac @ │ │ + ldc2l 12, cr12, [r9, #244] @ 0xf4 │ │ + ldc2l 9, cr10, [r8, #92] @ 0x5c @ │ │ ldrdeq r1, [ip], -r4 @ │ │ ldc2l 13, cr7, [fp, #884] @ 0x374 │ │ - ldc2l 10, cr2, [r9, #52] @ 0x34 @ │ │ + ldc2l 10, cr2, [r9, #232] @ 0xe8 @ │ │ ldc2l 5, cr15, [r7, #1012] @ 0x3f4 │ │ - ldc2l 7, cr10, [r8, #740] @ 0x2e4 │ │ - ldc2l 1, cr3, [r8, #244] @ 0xf4 │ │ + ldc2l 7, cr10, [r8, #920] @ 0x398 │ │ + ldc2l 1, cr3, [r8, #424] @ 0x1a8 │ │ eoreq r1, ip, r0, lsl #1 │ │ - ldc2l 2, cr1, [r9, #388] @ 0x184 │ │ - ldc2l 6, cr10, [r8, #180] @ 0xb4 │ │ + ldc2l 2, cr1, [r9, #568] @ 0x238 │ │ + ldc2l 6, cr10, [r8, #360] @ 0x168 │ │ ldc2l 5, cr4, [fp, #888] @ 0x378 │ │ eoreq r0, ip, ip, lsl #31 │ │ - ldc2l 1, cr5, [r8, #164] @ 0xa4 │ │ - ldc2l 7, cr10, [r8, #132] @ 0x84 │ │ + ldc2l 1, cr5, [r8, #344] @ 0x158 │ │ + ldc2l 7, cr10, [r8, #312] @ 0x138 │ │ ldc2l 8, cr6, [sl, #860] @ 0x35c │ │ - ldc2l 3, cr15, [r8, #120] @ 0x78 │ │ + ldc2l 3, cr15, [r8, #300] @ 0x12c │ │ │ │ 0249898c : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #336 @ 0x150 │ │ mov r3, #320 @ 0x140 │ │ add r4, sp, #16 │ │ @@ -1394087,15 +1394087,15 @@ │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #8 │ │ pop {r4, sl, fp, pc} │ │ ldc2l 4, cr14, [r7, #556] @ 0x22c │ │ ldc2l 13, cr6, [sl, #804] @ 0x324 │ │ - ldc2l 13, cr4, [r9, #16] │ │ + ldc2l 13, cr4, [r9, #196] @ 0xc4 │ │ │ │ 02498a24 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #24 │ │ mov r4, r3 │ │ mov r6, r2 │ │ @@ -1394130,16 +1394130,16 @@ │ │ mov r1, #8 │ │ vstr d16, [r4] │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - ldc2l 13, cr6, [r9, #1000] @ 0x3e8 │ │ - ldc2l 13, cr6, [r9, #648] @ 0x288 │ │ + ldc2l 14, cr6, [r9, #156] @ 0x9c │ │ + ldc2l 13, cr6, [r9, #828] @ 0x33c │ │ │ │ 02498acc : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #24 │ │ vldr d16, [r3] │ │ vcmp.f64 d16, #0.0 │ │ @@ -1394173,17 +1394173,17 @@ │ │ vdiv.f64 d16, d18, d16 │ │ vstr d17, [sp, #8] │ │ vstr d16, [sp, #16] │ │ bl 270f6b0 │ │ mov r0, #0 │ │ sub sp, fp, #8 │ │ pop {r4, r5, fp, pc} │ │ - ldc2l 2, cr9, [r8, #204] @ 0xcc │ │ - ldc2l 9, cr12, [r9, #80] @ 0x50 @ │ │ - ldc2l 10, cr4, [r8, #80] @ 0x50 @ │ │ + ldc2l 2, cr9, [r8, #384] @ 0x180 │ │ + ldc2l 9, cr12, [r9, #170] @ 0xaa @ │ │ + ldc2l 10, cr4, [r8, #260] @ 0x104 @ │ │ │ │ 02498b74 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ mov r7, r3 │ │ mov r4, r2 │ │ @@ -1395275,16 +1395275,16 @@ │ │ vmov.f64 d15, d8 │ │ vmov.f64 d8, #112 @ 0x3f800000 1.0 │ │ vldr d16, [fp, #-240] @ 0xffffff10 │ │ vstr d16, [fp, #-280] @ 0xfffffee8 │ │ b 2499cc8 │ │ eoreq r0, ip, ip, asr sl │ │ ldc2l 14, cr15, [r7, #424] @ 0x1a8 │ │ - ldc2l 10, cr4, [r9, #112] @ 0x70 @ │ │ - ldc2l 1, cr10, [r8, #996] @ 0x3e4 │ │ + ldc2l 10, cr4, [r9, #292] @ 0x124 @ │ │ + ldc2l 2, cr10, [r8, #152] @ 0x98 │ │ sub r0, fp, #208 @ 0xd0 │ │ add r0, r0, r1, lsl #3 │ │ vldr d16, [r0] │ │ vdiv.f64 d9, d16, d9 │ │ add r0, sp, #144 @ 0x90 │ │ ldr r2, [fp, #-212] @ 0xffffff2c │ │ add r0, r0, r1, lsl #3 │ │ @@ -1395358,18 +1395358,18 @@ │ │ mov r2, r9 │ │ movw r3, #1533 @ 0x5fd │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 2499ca8 │ │ ldc2l 3, cr9, [r7, #48] @ 0x30 │ │ - ldc2l 13, cr12, [r8, #68] @ 0x44 │ │ + ldc2l 13, cr12, [r8, #248] @ 0xf8 │ │ ldc2l 2, cr9, [r7, #656] @ 0x290 │ │ - ldc2l 12, cr12, [r8, #676] @ 0x2a4 │ │ - ldc2l 7, cr3, [r8, #96] @ 0x60 │ │ + ldc2l 12, cr12, [r8, #856] @ 0x358 │ │ + ldc2l 7, cr3, [r8, #276] @ 0x114 │ │ ldr r0, [sp, #92] @ 0x5c │ │ mov r1, #0 │ │ bic r0, r0, #1 │ │ sub r0, r0, #2 │ │ clz r0, r0 │ │ lsr r0, r0, #5 │ │ and r0, r4, r0 │ │ @@ -1395430,16 +1395430,16 @@ │ │ vmrs APSR_nzcv, fpscr │ │ ble 2499f9c │ │ vcmp.f64 d17, #0.0 │ │ vmrs APSR_nzcv, fpscr │ │ vmov.i32 d18, #0 @ 0x00000000 │ │ vmovls.f64 d17, d18 │ │ b 2499f4c │ │ - ldc2l 5, cr3, [r8, #912] @ 0x390 │ │ - ldc2l 11, cr12, [r8, #420] @ 0x1a4 @ │ │ + ldc2l 6, cr3, [r8, #68] @ 0x44 │ │ + ldc2l 11, cr12, [r8, #600] @ 0x258 @ │ │ ldr r0, [sp, #44] @ 0x2c │ │ cmp r0, #0 │ │ beq 2499f9c │ │ vldr d21, [sp, #32] │ │ vdiv.f64 d19, d19, d21 │ │ vldr d21, [sp, #48] @ 0x30 │ │ vstr d19, [sp, #224] @ 0xe0 │ │ @@ -1396060,58 +1396060,58 @@ │ │ bl 270dad0 │ │ add r1, r5, #8 │ │ mov r0, r4 │ │ mov r2, #1 │ │ bl 270dad0 │ │ add r1, r5, #16 │ │ b 249a768 │ │ - ldc2l 15, cr12, [r9, #588] @ 0x24c │ │ + ldc2l 15, cr12, [r9, #768] @ 0x300 │ │ ldc2l 2, cr5, [sl, #736] @ 0x2e0 │ │ - ldc2l 6, cr11, [r8, #228] @ 0xe4 │ │ + ldc2l 6, cr11, [r8, #408] @ 0x198 │ │ ldc2l 11, cr4, [sl, #836] @ 0x344 @ │ │ ldc2l 11, cr7, [r7, #896] @ 0x380 @ │ │ - ldc2l 5, cr11, [r8, #916] @ 0x394 │ │ + ldc2l 6, cr11, [r8, #72] @ 0x48 │ │ ldc2l 11, cr4, [sl, #516] @ 0x204 @ │ │ - ldc2l 6, cr15, [r8, #440] @ 0x1b8 │ │ + ldc2l 6, cr15, [r8, #620] @ 0x26c │ │ ldc2l 14, cr6, [sl, #324] @ 0x144 │ │ ldc2l 1, cr5, [sl, #880] @ 0x370 │ │ - ldc2l 5, cr11, [r8, #372] @ 0x174 │ │ + ldc2l 5, cr11, [r8, #552] @ 0x228 │ │ ldc2l 10, cr4, [sl, #980] @ 0x3d4 @ │ │ eoreq pc, fp, r4, ror #6 │ │ ldc2l 10, cr8, [sl, #104] @ 0x68 @ │ │ - ldc2l 0, cr7, [r9, #280] @ 0x118 │ │ - ldc2l 8, cr8, [r8, #740] @ 0x2e4 │ │ + ldc2l 0, cr7, [r9, #460] @ 0x1cc │ │ + vcadd.f32 q12, q12, q11, #270 │ │ vcadd.f32 d29, d23, d25, #270 │ │ - vcadd.f32 q12, q4, , #270 │ │ + vcadd.f32 q12, q4, q15, #270 │ │ eoreq pc, fp, r4, lsr #5 │ │ eoreq pc, fp, r8, lsl #31 │ │ eoreq pc, fp, ip, ror #30 │ │ ldc2l 6, cr8, [r7, #624] @ 0x270 │ │ ldc2l 10, cr9, [r7, #352] @ 0x160 @ │ │ ldc2l 9, cr9, [r7, #192] @ 0xc0 @ │ │ - ldc2l 12, cr3, [r8, #268] @ 0x10c │ │ - ldc2l 13, cr11, [r8, #948] @ 0x3b4 │ │ + ldc2l 12, cr3, [r8, #448] @ 0x1c0 │ │ + ldc2l 14, cr11, [r8, #104] @ 0x68 │ │ ldc2l 9, cr8, [sl, #448] @ 0x1c0 @ │ │ - ldc2l 8, cr8, [r8, #484] @ 0x1e4 │ │ + vcadd.f32 d24, d24, d22, #270 │ │ ldc2l 9, cr4, [sl, #198] @ 0xc6 @ │ │ ldc2l 6, cr0, [fp, #124] @ 0x7c │ │ - ldc2l 14, cr5, [r8, #240] @ 0xf0 │ │ - ldc2l 11, cr3, [r8, #604] @ 0x25c @ │ │ - ldc2l 4, cr11, [r9, #16] │ │ - vcadd.f32 d19, d24, d11, #270 │ │ + ldc2l 14, cr5, [r8, #420] @ 0x1a4 │ │ + ldc2l 11, cr3, [r8, #784] @ 0x310 @ │ │ + ldc2l 4, cr11, [r9, #196] @ 0xc4 │ │ + ldc2l 8, cr3, [r8, #736] @ 0x2e0 │ │ ldc2l 12, cr9, [sl, #396] @ 0x18c │ │ ldc2l 5, cr15, [r9, #364] @ 0x16c │ │ - ldc2l 2, cr11, [r8, #656] @ 0x290 │ │ - ldc2l 6, cr8, [r8, #340] @ 0x154 │ │ - ldc2l 2, cr11, [r9, #880] @ 0x370 │ │ - ldc2l 7, cr3, [r8, #412] @ 0x19c │ │ + ldc2l 2, cr11, [r8, #836] @ 0x344 │ │ + ldc2l 6, cr8, [r8, #520] @ 0x208 │ │ + ldc2l 3, cr11, [r9, #36] @ 0x24 │ │ + ldc2l 7, cr3, [r8, #592] @ 0x250 │ │ ldc2l 11, cr9, [sl, #284] @ 0x11c @ │ │ ldc2l 4, cr15, [r9, #252] @ 0xfc │ │ ldc2l 12, cr12, [sl, #880] @ 0x370 │ │ - ldc2l 3, cr11, [r8, #404] @ 0x194 │ │ + ldc2l 3, cr11, [r8, #584] @ 0x248 │ │ ldc2l 12, cr6, [sl, #732] @ 0x2dc │ │ ldc2l 15, cr4, [sl, #848] @ 0x350 │ │ ldc2l 3, cr0, [fp, #92] @ 0x5c │ │ │ │ 0249a990 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -1396413,19 +1396413,19 @@ │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ vcadd.f32 q9, q13, q14, #270 │ │ eoreq lr, fp, r4, lsr #24 │ │ - ldc2l 14, cr12, [r8, #236] @ 0xec │ │ + ldc2l 14, cr12, [r8, #416] @ 0x1a0 │ │ eoreq lr, fp, r8, ror #25 │ │ - ldc2l 9, cr2, [r9, #184] @ 0xb8 @ │ │ - ldc2l 1, cr8, [r8, #228] @ 0xe4 │ │ - ldc2l 13, cr14, [r8, #904] @ 0x388 │ │ + ldc2l 9, cr2, [r9, #274] @ 0x112 @ │ │ + ldc2l 1, cr8, [r8, #408] @ 0x198 │ │ + ldc2l 14, cr14, [r8, #60] @ 0x3c │ │ ldc2l 7, cr2, [sl, #464] @ 0x1d0 │ │ │ │ 0249ae40 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #80 @ 0x50 │ │ vldr d16, [r0] │ │ @@ -1397039,19 +1397039,19 @@ │ │ b 249b758 │ │ mov r0, #0 │ │ sub sp, fp, #48 @ 0x30 │ │ vpop {d8-d9} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 1, cr15, [sl, #160] @ 0xa0 │ │ - ldc2l 12, cr7, [r9, #792] @ 0x318 │ │ + ldc2l 12, cr7, [r9, #972] @ 0x3cc │ │ ldc2l 1, cr3, [fp, #712] @ 0x2c8 │ │ - ldc2l 13, cr7, [r9, #88] @ 0x58 │ │ + ldc2l 13, cr7, [r9, #268] @ 0x10c │ │ ldc2l 3, cr9, [sl, #332] @ 0x14c │ │ - ldc2l 13, cr7, [r9, #520] @ 0x208 │ │ + ldc2l 13, cr7, [r9, #700] @ 0x2bc │ │ │ │ 0249b7bc : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #100 @ 0x64 │ │ mov r4, r3 │ │ mov r7, r2 │ │ @@ -1397311,35 +1397311,35 @@ │ │ ldr r0, [pc, #100] @ 249bc30 │ │ mov r1, #8 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 14, cr5, [r9, #688] @ 0x2b0 │ │ + ldc2l 14, cr5, [r9, #868] @ 0x364 │ │ ldc2l 14, cr9, [r7, #868] @ 0x364 │ │ - ldc2l 6, cr7, [r8, #468] @ 0x1d4 │ │ - ldc2l 6, cr7, [r8, #228] @ 0xe4 │ │ + ldc2l 6, cr7, [r8, #648] @ 0x288 │ │ + ldc2l 6, cr7, [r8, #408] @ 0x198 │ │ ldc2l 13, cr9, [r7, #356] @ 0x164 │ │ - ldc2l 5, cr7, [r8, #20] │ │ + ldc2l 5, cr7, [r8, #200] @ 0xc8 │ │ ldc2l 2, cr9, [sl, #664] @ 0x298 │ │ - ldc2l 4, cr7, [r8, #404] @ 0x194 │ │ + ldc2l 4, cr7, [r8, #584] @ 0x248 │ │ ldc2l 15, cr14, [sl, #880] @ 0x370 │ │ ldc2l 8, cr5, [sl, #600] @ 0x258 │ │ - ldc2l 5, cr7, [r8, #692] @ 0x2b4 │ │ + ldc2l 5, cr7, [r8, #872] @ 0x368 │ │ eoreq lr, fp, r0, lsr r1 │ │ - ldc2l 9, cr11, [r9, #66] @ 0x42 @ │ │ + ldc2l 9, cr11, [r9, #156] @ 0x9c @ │ │ ldc2l 4, cr1, [fp, #208] @ 0xd0 │ │ - ldc2l 4, cr7, [r8, #4] │ │ - ldc2l 13, cr15, [r7, #468] @ 0x1d4 │ │ + ldc2l 4, cr7, [r8, #184] @ 0xb8 │ │ + ldc2l 13, cr15, [r7, #648] @ 0x288 │ │ eoreq sp, fp, r0, lsr #31 │ │ - ldc2l 14, cr15, [r7, #12] │ │ - ldc2l 3, cr7, [r8, #340] @ 0x154 │ │ + ldc2l 14, cr15, [r7, #192] @ 0xc0 │ │ + ldc2l 3, cr7, [r8, #520] @ 0x208 │ │ ldc2l 5, cr3, [sl, #140] @ 0x8c │ │ - ldc2l 10, cr5, [r9, #832] @ 0x340 @ │ │ + ldc2l 10, cr5, [r9, #1012] @ 0x3f4 @ │ │ │ │ 0249bc34 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #100 @ 0x64 │ │ mov r5, r3 │ │ mov r7, r2 │ │ @@ -1397607,32 +1397607,32 @@ │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 11, cr4, [fp, #312] @ 0x138 @ │ │ ldc2l 10, cr9, [r7, #372] @ 0x174 @ │ │ - ldc2l 1, cr7, [r8, #996] @ 0x3e4 │ │ - ldc2l 1, cr7, [r8, #740] @ 0x2e4 │ │ + ldc2l 2, cr7, [r8, #152] @ 0x98 │ │ + ldc2l 1, cr7, [r8, #920] @ 0x398 │ │ ldc2l 8, cr9, [r7, #884] @ 0x374 │ │ - ldc2l 0, cr7, [r8, #548] @ 0x224 │ │ - ldc2l 0, cr7, [r8, #228] @ 0xe4 │ │ + ldc2l 0, cr7, [r8, #728] @ 0x2d8 │ │ + ldc2l 0, cr7, [r8, #408] @ 0x198 │ │ ldc2l 6, cr7, [r7, #356] @ 0x164 │ │ - ldc2l 15, cr6, [r8, #868] @ 0x364 │ │ + ldc2l 0, cr7, [r8, #24] │ │ ldc2l 11, cr14, [sl, #320] @ 0x140 @ │ │ ldc2l 4, cr5, [sl, #104] @ 0x68 │ │ - ldc2l 1, cr7, [r8, #196] @ 0xc4 │ │ + ldc2l 1, cr7, [r8, #376] @ 0x178 │ │ strhteq sp, [fp], -ip │ │ - ldc2l 4, cr11, [r9, #660] @ 0x294 │ │ + ldc2l 4, cr11, [r9, #840] @ 0x348 │ │ ldc2l 15, cr0, [fp, #672] @ 0x2a0 │ │ - ldc2l 15, cr6, [r8, #468] @ 0x1d4 │ │ - vcadd.f32 , , , #270 │ │ + ldc2l 15, cr6, [r8, #648] @ 0x288 │ │ + ldc2l 9, cr15, [r7, #36] @ 0x24 @ │ │ eoreq sp, fp, r4, lsl fp │ │ - ldc2l 9, cr15, [r7, #230] @ 0xe6 @ │ │ - ldc2l 14, cr6, [r8, #788] @ 0x314 │ │ + ldc2l 9, cr15, [r7, #320] @ 0x140 @ │ │ + ldc2l 14, cr6, [r8, #968] @ 0x3c8 │ │ ldc2l 0, cr3, [sl, #588] @ 0x24c │ │ ldc2l 7, cr4, [fp, #376] @ 0x178 │ │ │ │ 0249c0c8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ @@ -1398396,15 +1398396,15 @@ │ │ sub r7, fp, #344 @ 0x158 │ │ str r0, [sp, #40] @ 0x28 │ │ mov r6, #0 │ │ mov r0, #0 │ │ str r1, [sp, #32] │ │ str r0, [sp, #52] @ 0x34 │ │ b 249cd04 │ │ - ldc2l 11, cr15, [r8, #956] @ 0x3bc @ │ │ + ldc2l 12, cr15, [r8, #112] @ 0x70 │ │ streq r3, [r5], #3476 @ 0xd94 │ │ ldr r1, [sp, #52] @ 0x34 │ │ add r6, r6, #32 │ │ add r4, r4, #80 @ 0x50 │ │ sub r7, fp, #344 @ 0x158 │ │ add r0, r1, #2 │ │ str r0, [fp, #-340] @ 0xfffffeac │ │ @@ -1398680,20 +1398680,20 @@ │ │ sub r2, lr, #56 @ 0x38 │ │ mov r1, sl │ │ mov r0, r6 │ │ str r4, [sp] │ │ mov sl, r5 │ │ bl 270f9e0 │ │ b 249d7f8 │ │ - ldc2l 6, cr9, [r8, #160] @ 0xa0 │ │ + ldc2l 6, cr9, [r8, #340] @ 0x154 │ │ streq r4, [r5], #184 @ 0xb8 │ │ ldc2l 6, cr9, [r7, #28] │ │ streq r3, [r5], #3416 @ 0xd58 │ │ eoreq sp, fp, r0, lsr #20 │ │ - ldc2l 8, cr15, [r7, #208] @ 0xd0 │ │ + vcadd.f32 , , , #270 │ │ eoreq sp, fp, pc, asr #19 │ │ streq r3, [r5], #3500 @ 0xdac │ │ ldc2l 1, cr7, [r7, #1008] @ 0x3f0 │ │ streq r3, [r5], #3948 @ 0xf6c │ │ ldc2l 0, cr5, [sl, #444] @ 0x1bc │ │ mov r7, #32 │ │ add lr, sp, #1024 @ 0x400 │ │ @@ -1398753,31 +1398753,31 @@ │ │ bl 270db90 │ │ cmp r0, #0 │ │ beq 249dbc0 │ │ b 249c638 │ │ streq r3, [r5], #3248 @ 0xcb0 │ │ ldc2l 3, cr1, [sl, #28] │ │ streq r3, [r5], #3380 @ 0xd34 │ │ - ldc2l 9, cr3, [r8, #26] @ │ │ + ldc2l 9, cr3, [r8, #116] @ 0x74 @ │ │ streq r3, [r5], #3512 @ 0xdb8 │ │ - ldc2l 7, cr13, [r8, #288] @ 0x120 │ │ + ldc2l 7, cr13, [r8, #468] @ 0x1d4 │ │ streq r3, [r5], #3580 @ 0xdfc │ │ ldc2l 11, cr0, [fp, #860] @ 0x35c @ │ │ streq r3, [r5], #3328 @ 0xd00 │ │ - ldc2l 6, cr13, [r8, #812] @ 0x32c │ │ + ldc2l 6, cr13, [r8, #992] @ 0x3e0 │ │ streq r3, [r5], #3204 @ 0xc84 │ │ - ldc2l 7, cr14, [r8, #752] @ 0x2f0 │ │ + ldc2l 7, cr14, [r8, #932] @ 0x3a4 │ │ streq r3, [r5], #2824 @ 0xb08 │ │ ldc2l 6, cr13, [r7, #508] @ 0x1fc │ │ streq r3, [r5], #2892 @ 0xb4c │ │ - ldc2l 7, cr3, [r8, #648] @ 0x288 │ │ + ldc2l 7, cr3, [r8, #828] @ 0x33c │ │ streq r3, [r5], #3344 @ 0xd10 │ │ ldc2l 1, cr4, [fp, #476] @ 0x1dc │ │ streq r3, [r5], #3160 @ 0xc58 │ │ - ldc2l 6, cr9, [r8, #496] @ 0x1f0 │ │ + ldc2l 6, cr9, [r8, #676] @ 0x2a4 │ │ streq r3, [r5], #3356 @ 0xd1c │ │ streq r3, [r5], #2512 @ 0x9d0 │ │ eoreq sp, fp, r4, lsr #13 │ │ mlaeq fp, r0, r6, sp │ │ mov r7, #32 │ │ add lr, sp, #1024 @ 0x400 │ │ str r7, [sp] │ │ @@ -1398940,18 +1398940,18 @@ │ │ mov r0, r6 │ │ mov r2, r7 │ │ mov r6, r5 │ │ add r1, pc, r1 │ │ bl 270e100 │ │ b 249dbc0 │ │ vcadd.f32 , , , #270 │ │ - ldc2l 0, cr1, [r9, #864] @ 0x360 │ │ + ldc2l 1, cr1, [r9, #20] │ │ mlaeq fp, r4, r5, sp │ │ - ldc2l 6, cr15, [r8, #796] @ 0x31c │ │ - ldc2l 0, cr1, [r9, #520] @ 0x208 │ │ + ldc2l 6, cr15, [r8, #976] @ 0x3d0 │ │ + ldc2l 0, cr1, [r9, #700] @ 0x2bc │ │ ldc2l 5, cr8, [sl, #568] @ 0x238 │ │ eoreq sp, fp, r4, lsl #10 │ │ ldc2l 7, cr10, [r7, #380] @ 0x17c │ │ streq r3, [r5], #2836 @ 0xb14 │ │ ldc2l 11, cr4, [sl, #512] @ 0x200 @ │ │ ldc2l 13, cr14, [r9, #860] @ 0x35c │ │ mov r7, #32 │ │ @@ -1399086,16 +1399086,16 @@ │ │ mlaeq fp, ip, r2, sp │ │ ldc2l 12, cr14, [r9, #52] @ 0x34 │ │ streq r3, [r5], #1372 @ 0x55c │ │ eoreq sp, fp, r4, lsr #4 │ │ streq r3, [r5], #2064 @ 0x810 │ │ mlaeq fp, r8, r1, sp │ │ ldc2l 11, cr14, [r9, #348] @ 0x15c @ │ │ - ldc2l 4, cr6, [r8, #836] @ 0x344 │ │ - ldc2l 9, cr4, [r9, #30] @ │ │ + ldc2l 4, cr6, [r8, #1016] @ 0x3f8 │ │ + ldc2l 9, cr4, [r9, #120] @ 0x78 @ │ │ ldc2l 1, cr8, [sl, #756] @ 0x2f4 │ │ ldr sl, [sp, #56] @ 0x38 │ │ cmp r0, #0 │ │ ldr r9, [sp, #64] @ 0x40 │ │ beq 249d804 │ │ mov r0, #32 │ │ sub r4, fp, #408 @ 0x198 │ │ @@ -1399275,17 +1399275,17 @@ │ │ ldr r0, [pc, #4068] @ 249ea50 │ │ add r1, sp, #616 @ 0x268 │ │ ldr r2, [sp, #40] @ 0x28 │ │ add r3, sp, #560 @ 0x230 │ │ add r0, pc, r0 │ │ bl 270e660 │ │ b 249dad4 │ │ - ldc2l 4, cr6, [r8, #452] @ 0x1c4 │ │ - ldc2l 14, cr0, [r8, #116] @ 0x74 │ │ - ldc2l 15, cr14, [r7, #84] @ 0x54 │ │ + ldc2l 4, cr6, [r8, #632] @ 0x278 │ │ + ldc2l 14, cr0, [r8, #296] @ 0x128 │ │ + ldc2l 15, cr14, [r7, #264] @ 0x108 │ │ ldc2l 3, cr13, [r7, #468] @ 0x1d4 │ │ sub r0, fp, #344 @ 0x158 │ │ str r0, [sp] │ │ add r0, sp, #560 @ 0x230 │ │ str r0, [sp, #4] │ │ mov r0, #32 │ │ add lr, sp, #1024 @ 0x400 │ │ @@ -1399305,18 +1399305,18 @@ │ │ ldr r1, [pc, r1] │ │ cmp r0, r1 │ │ bne 249db08 │ │ ldr r1, [sp, #60] @ 0x3c │ │ add r0, sp, #560 @ 0x230 │ │ bl 270f010 │ │ b 249db3c │ │ - vcadd.f32 d26, d25, d21, #270 │ │ - ldc2l 3, cr6, [r8, #852] @ 0x354 │ │ + ldc2l 8, cr10, [r9, #840] @ 0x348 │ │ + ldc2l 4, cr6, [r8, #8] │ │ ldc2l 7, cr4, [sl, #612] @ 0x264 │ │ - ldc2l 3, cr6, [r8, #692] @ 0x2b4 │ │ + ldc2l 3, cr6, [r8, #872] @ 0x368 │ │ ldr r1, [pc, #3912] @ 249ea58 │ │ sub r0, fp, #76 @ 0x4c │ │ add r2, sp, #552 @ 0x228 │ │ add r3, sp, #160 @ 0xa0 │ │ add r1, pc, r1 │ │ bl 270fc60 │ │ bl 270db90 │ │ @@ -1399339,16 +1399339,16 @@ │ │ sub r2, fp, #440 @ 0x1b8 │ │ ldr r1, [sp, #24] │ │ bl 270f6f0 │ │ b 249db9c │ │ vcadd.f32 q14, , , #270 │ │ ldc2l 3, cr0, [fp, #420] @ 0x1a4 │ │ ldc2l 2, cr12, [sl, #664] @ 0x298 │ │ - ldc2l 15, cr6, [r8, #912] @ 0x390 │ │ - ldc2l 3, cr6, [r8, #148] @ 0x94 │ │ + ldc2l 0, cr7, [r8, #68] @ 0x44 │ │ + ldc2l 3, cr6, [r8, #328] @ 0x148 │ │ ldc2l 3, cr0, [fp, #68] @ 0x44 │ │ ldr r0, [sp, #60] @ 0x3c │ │ sub r2, fp, #440 @ 0x1b8 │ │ ldr r1, [sp, #24] │ │ bl 270f6e0 │ │ bl 270db90 │ │ ldr sl, [sp, #56] @ 0x38 │ │ @@ -1399386,15 +1399386,15 @@ │ │ ldc2l 8, cr12, [r7, #756] @ 0x2f4 │ │ eoreq ip, fp, r0, lsr #27 │ │ eoreq ip, fp, r0, lsl #26 │ │ streq r3, [r5], #800 @ 0x320 │ │ eoreq ip, fp, ip, lsr sp │ │ ldc2l 15, cr9, [r7, #652] @ 0x28c │ │ streq r3, [r5], #856 @ 0x358 │ │ - ldc2l 10, cr0, [r8] @ │ │ + ldc2l 10, cr0, [r8, #180] @ 0xb4 @ │ │ ldc2l 2, cr10, [sl, #56] @ 0x38 │ │ ldr r2, [pc, #3640] @ 249ea84 │ │ add lr, sp, #1024 @ 0x400 │ │ ldr r3, [pc, #3636] @ 249ea88 │ │ mov r0, #0 │ │ str r4, [sp, #12] │ │ add r5, lr, #472 @ 0x1d8 │ │ @@ -1399564,19 +1399564,19 @@ │ │ str r1, [sp] │ │ mov r1, r4 │ │ stmib sp, {r0, r8} │ │ mov r0, sl │ │ bl 270db40 │ │ b 249c638 │ │ ldc2l 9, cr1, [fp, #128] @ 0x80 @ │ │ - ldc2l 2, cr8, [r9, #732] @ 0x2dc │ │ + ldc2l 2, cr8, [r9, #912] @ 0x390 │ │ streq r3, [r5], #84 @ 0x54 │ │ streq r2, [r5], #3904 @ 0xf40 │ │ eoreq ip, fp, r0, ror #23 │ │ - ldc2l 12, cr6, [r8, #412] @ 0x19c │ │ + ldc2l 12, cr6, [r8, #592] @ 0x250 │ │ ldr r2, [pc, #2972] @ 249eabc │ │ add lr, sp, #1024 @ 0x400 │ │ ldr r4, [pc, #2968] @ 249eac0 │ │ add r1, lr, #504 @ 0x1f8 │ │ add lr, sp, #1024 @ 0x400 │ │ ldr r7, [sp, #56] @ 0x38 │ │ add r4, pc, r4 │ │ @@ -1399649,15 +1399649,15 @@ │ │ bhi 249e05c │ │ add r1, sp, #756 @ 0x2f4 │ │ mov r0, r6 │ │ mov r2, #32 │ │ bl 270dc80 │ │ b 249e0b0 │ │ streq r2, [r5], #4048 @ 0xfd0 │ │ - ldc2l 6, cr8, [r8, #416] @ 0x1a0 │ │ + ldc2l 6, cr8, [r8, #596] @ 0x254 │ │ ldr r0, [pc, #2676] @ 249ead8 │ │ mov r1, r9 │ │ ldr r5, [pc, #2672] @ 249eadc │ │ movw r3, #2049 @ 0x801 │ │ add r0, pc, r0 │ │ add r5, pc, r5 │ │ mov r2, r5 │ │ @@ -1399768,15 +1399768,15 @@ │ │ mov r2, #1 │ │ mov r3, #36 @ 0x24 │ │ bl 270da60 │ │ ldr r0, [pc, #1976] @ 249e9e4 │ │ mov r1, #23 │ │ add r0, pc, r0 │ │ b 249ca68 │ │ - ldc2l 5, cr8, [r8, #224] @ 0xe0 │ │ + ldc2l 5, cr8, [r8, #404] @ 0x194 │ │ ldr r0, [pc, #2008] @ 249ea18 │ │ mov r1, #205 @ 0xcd │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #1996] @ 249ea1c │ │ add lr, sp, #1024 @ 0x400 │ │ add r1, lr, #472 @ 0x1d8 │ │ @@ -1399887,15 +1399887,15 @@ │ │ mov r3, #13 │ │ add r1, pc, r1 │ │ bl 270da60 │ │ ldr r0, [pc, #1644] @ 249ea74 │ │ mov r1, #21 │ │ add r0, pc, r0 │ │ b 249ca68 │ │ - ldc2l 2, cr8, [r8, #832] @ 0x340 │ │ + ldc2l 2, cr8, [r8, #1012] @ 0x3f4 │ │ streq r2, [r5], #3368 @ 0xd28 │ │ ldr r2, [pc, #1448] @ 249e9c8 │ │ add lr, sp, #1024 @ 0x400 │ │ ldr r3, [pc, #1444] @ 249e9cc │ │ mov r1, #9 │ │ mov r0, #80 @ 0x50 │ │ add r6, lr, #504 @ 0x1f8 │ │ @@ -1400122,15 +1400122,15 @@ │ │ add r0, pc, r0 │ │ b 249e958 │ │ ldr r0, [pc, #576] @ 249e9f0 │ │ mov r1, #168 @ 0xa8 │ │ add r0, pc, r0 │ │ b 249e888 │ │ streq r2, [r5], #2232 @ 0x8b8 │ │ - ldc2l 15, cr7, [r8, #496] @ 0x1f0 │ │ + ldc2l 15, cr7, [r8, #676] @ 0x2a4 │ │ ldr r0, [sp, #48] @ 0x30 │ │ sub r1, fp, #688 @ 0x2b0 │ │ add r2, sp, #72 @ 0x48 │ │ mov r3, #36 @ 0x24 │ │ bl 270ce00 │ │ ldr r0, [sp, #72] @ 0x48 │ │ cmp r0, #0 │ │ @@ -1400169,15 +1400169,15 @@ │ │ bl 270da60 │ │ ldr r0, [pc, #472] @ 249ea40 │ │ mov r1, #20 │ │ add r0, pc, r0 │ │ b 249ca68 │ │ ldc2l 5, cr9, [r7, #828] @ 0x33c │ │ streq r2, [r5], #2436 @ 0x984 │ │ - ldc2l 3, cr2, [r8, #96] @ 0x60 │ │ + ldc2l 3, cr2, [r8, #276] @ 0x114 │ │ ldr r0, [pc, #396] @ 249ea10 │ │ mov r1, #169 @ 0xa9 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #352] @ 249e9f4 │ │ add lr, sp, #1024 @ 0x400 │ │ add r1, lr, #472 @ 0x1d8 │ │ @@ -1400251,91 +1400251,91 @@ │ │ streq r2, [r5], #1684 @ 0x694 │ │ strdeq ip, [fp], -r8 @ │ │ streq r2, [r5], #1356 @ 0x54c │ │ streq r2, [r5], #1544 @ 0x608 │ │ eoreq ip, fp, ip, lsr #3 │ │ ldc2l 0, cr15, [sl, #744] @ 0x2e8 │ │ ldc2l 14, cr8, [sl, #472] @ 0x1d8 │ │ - ldc2l 13, cr4, [r8, #196] @ 0xc4 │ │ + ldc2l 13, cr4, [r8, #376] @ 0x178 │ │ ldc2l 3, cr13, [r9, #340] @ 0x154 │ │ - ldc2l 6, cr7, [r8, #876] @ 0x36c │ │ + ldc2l 7, cr7, [r8, #32] │ │ eoreq fp, fp, r4, ror #14 │ │ - ldc2l 1, cr3, [r9, #988] @ 0x3dc │ │ + ldc2l 2, cr3, [r9, #144] @ 0x90 │ │ streq r1, [r5], #2600 @ 0xa28 │ │ - ldc2l 2, cr11, [r8, #272] @ 0x110 │ │ - ldc2l 5, cr4, [r8, #932] @ 0x3a4 │ │ - ldc2l 13, cr2, [r9, #156] @ 0x9c │ │ + ldc2l 2, cr11, [r8, #452] @ 0x1c4 │ │ + ldc2l 6, cr4, [r8, #88] @ 0x58 │ │ + ldc2l 13, cr2, [r9, #336] @ 0x150 │ │ ldc2l 1, cr5, [r7, #932] @ 0x3a4 │ │ ldc2l 5, cr1, [sl, #300] @ 0x12c │ │ - ldc2l 13, cr4, [r8, #724] @ 0x2d4 │ │ - ldc2l 4, cr13, [r8, #696] @ 0x2b8 │ │ - ldc2l 6, cr4, [r8, #404] @ 0x194 │ │ - ldc2l 5, cr7, [r8, #996] @ 0x3e4 │ │ + ldc2l 13, cr4, [r8, #904] @ 0x388 │ │ + ldc2l 4, cr13, [r8, #876] @ 0x36c │ │ + ldc2l 6, cr4, [r8, #584] @ 0x248 │ │ + ldc2l 6, cr7, [r8, #152] @ 0x98 │ │ mlaeq fp, r4, r6, fp │ │ - ldc2l 1, cr3, [r9, #44] @ 0x2c │ │ + ldc2l 1, cr3, [r9, #224] @ 0xe0 │ │ streq r1, [r5], #2364 @ 0x93c │ │ - ldc2l 1, cr9, [r8, #896] @ 0x380 │ │ + ldc2l 2, cr9, [r8, #52] @ 0x34 │ │ streq r1, [r5], #3160 @ 0xc58 │ │ - ldc2l 10, cr8, [r9, #572] @ 0x23c @ │ │ + ldc2l 10, cr8, [r9, #752] @ 0x2f0 @ │ │ streq r1, [r5], #2984 @ 0xba8 │ │ ldc2l 2, cr11, [r9, #272] @ 0x110 │ │ - ldc2l 12, cr4, [r8, #676] @ 0x2a4 │ │ + ldc2l 12, cr4, [r8, #856] @ 0x358 │ │ ldc2l 2, cr13, [r9, #816] @ 0x330 │ │ ldc2l 12, cr4, [r7, #564] @ 0x234 │ │ - ldc2l 5, cr4, [r8, #580] @ 0x244 │ │ + ldc2l 5, cr4, [r8, #760] @ 0x2f8 │ │ ldc2l 13, cr15, [sl, #652] @ 0x28c │ │ ldc2l 0, cr7, [r7, #148] @ 0x94 │ │ - ldc2l 7, cr4, [r8, #644] @ 0x284 │ │ + ldc2l 7, cr4, [r8, #824] @ 0x338 │ │ ldc2l 5, cr9, [r7, #968] @ 0x3c8 │ │ - ldc2l 6, cr4, [r8, #804] @ 0x324 │ │ - ldc2l 12, cr6, [r8, #92] @ 0x5c │ │ - ldc2l 2, cr3, [r8, #608] @ 0x260 │ │ + ldc2l 6, cr4, [r8, #984] @ 0x3d8 │ │ + ldc2l 12, cr6, [r8, #272] @ 0x110 │ │ + ldc2l 2, cr3, [r8, #788] @ 0x314 │ │ streq r2, [r5], #1800 @ 0x708 │ │ eoreq ip, fp, r0, ror #1 │ │ eoreq ip, fp, r4, asr #2 │ │ streq r2, [r5], #1828 @ 0x724 │ │ streq r2, [r5], #1768 @ 0x6e8 │ │ strhteq fp, [fp], -r8 │ │ eoreq fp, fp, r7, lsr #17 │ │ ldrdeq fp, [fp], -r8 @ │ │ ldc2l 14, cr8, [sl, #380] @ 0x17c │ │ - ldc2l 11, cr4, [r8, #372] @ 0x174 @ │ │ + ldc2l 11, cr4, [r8, #552] @ 0x228 @ │ │ ldc2l 12, cr4, [sl, #224] @ 0xe0 │ │ ldc2l 1, cr2, [fp, #812] @ 0x32c │ │ streq r1, [r5], #2832 @ 0xb10 │ │ mlaeq fp, r8, r4, fp │ │ streq r1, [r5], #2784 @ 0xae0 │ │ ldc2l 7, cr3, [sl, #572] @ 0x23c │ │ eoreq fp, fp, r0, asr #30 │ │ ldc2l 12, cr7, [r7, #392] @ 0x188 │ │ ldrdeq fp, [fp], -r8 @ │ │ eoreq fp, fp, fp, lsl #28 │ │ strhteq fp, [fp], -r4 │ │ eoreq fp, fp, r7, lsl #27 │ │ - ldc2l 14, cr1, [r8, #8] │ │ + ldc2l 14, cr1, [r8, #188] @ 0xbc │ │ eoreq fp, fp, ip, asr #27 │ │ streq r2, [r5], #1028 @ 0x404 │ │ ldc2l 12, cr14, [sl, #696] @ 0x2b8 │ │ streq r2, [r5], #932 @ 0x3a4 │ │ streq r2, [r5], #864 @ 0x360 │ │ ldc2l 12, cr14, [sl, #120] @ 0x78 │ │ - ldc2l 11, cr11, [r8, #836] @ 0x344 @ │ │ + ldc2l 11, cr11, [r8, #1016] @ 0x3f8 @ │ │ mlaeq fp, r4, ip, fp │ │ ldc2l 9, cr7, [r7, #382] @ 0x17e @ │ │ ldc2l 1, cr1, [sl, #244] @ 0xf4 │ │ - ldc2l 8, cr4, [r8, #996] @ 0x3e4 │ │ + ldc2l 9, cr4, [r8, #76] @ 0x4c @ │ │ ldc2l 6, cr6, [sl, #824] @ 0x338 │ │ eoreq fp, fp, r4, ror fp │ │ ldc2l 5, cr2, [fp, #500] @ 0x1f4 │ │ - ldc2l 11, cr11, [r8, #524] @ 0x20c @ │ │ + ldc2l 11, cr11, [r8, #704] @ 0x2c0 @ │ │ ldc2l 13, cr10, [sl, #840] @ 0x348 │ │ mlaeq fp, r4, sl, fp │ │ ldc2l 5, cr11, [r7, #560] @ 0x230 │ │ ldc2l 10, cr8, [sl, #636] @ 0x27c @ │ │ - vcadd.f32 q10, q4, , #270 │ │ + ldc2l 8, cr4, [r8, #600] @ 0x258 │ │ │ │ 0249eaf4 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #76 @ 0x4c │ │ mov r5, r3 │ │ mov r8, r2 │ │ @@ -1400500,27 +1400500,27 @@ │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 11, cr10, [r9, #524] @ 0x20c @ │ │ ldc2l 11, cr10, [r9, #56] @ 0x38 @ │ │ - ldc2l 3, cr4, [r8, #308] @ 0x134 │ │ + ldc2l 3, cr4, [r8, #488] @ 0x1e8 │ │ ldc2l 4, cr14, [sl, #100] @ 0x64 │ │ ldc2l 11, cr10, [r9, #736] @ 0x2e0 @ │ │ - ldc2l 3, cr4, [r8, #532] @ 0x214 │ │ - ldc2l 1, cr3, [r8, #632] @ 0x278 │ │ - ldc2l 1, cr3, [r8, #240] @ 0xf0 │ │ - ldc2l 10, cr2, [r9, #628] @ 0x274 @ │ │ + ldc2l 3, cr4, [r8, #712] @ 0x2c8 │ │ + ldc2l 1, cr3, [r8, #812] @ 0x32c │ │ + ldc2l 1, cr3, [r8, #420] @ 0x1a4 │ │ + ldc2l 10, cr2, [r9, #808] @ 0x328 @ │ │ stc2l 6, cr10, [r3, #448]! @ 0x1c0 │ │ - ldc2l 1, cr3, [r8, #32] │ │ - ldc2l 10, cr2, [r9, #420] @ 0x1a4 @ │ │ + ldc2l 1, cr3, [r8, #212] @ 0xd4 │ │ + ldc2l 10, cr2, [r9, #600] @ 0x258 @ │ │ ldc2l 13, cr5, [sl, #188] @ 0xbc │ │ - ldc2l 10, cr2, [r9, #196] @ 0xc4 @ │ │ - ldc2l 10, cr14, [r8, #28] @ │ │ + ldc2l 10, cr2, [r9, #376] @ 0x178 @ │ │ + ldc2l 10, cr14, [r8, #208] @ 0xd0 @ │ │ ldc2l 7, cr8, [sl, #348] @ 0x15c │ │ eoreq sl, fp, r8, asr lr │ │ ldc2l 9, cr10, [r9, #78] @ 0x4e @ │ │ │ │ 0249eddc : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -1400890,43 +1400890,43 @@ │ │ ldr r0, [pc, #132] @ 249f41c │ │ mov r1, #8 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 6, cr8, [r9, #704] @ 0x2c0 │ │ + ldc2l 6, cr8, [r9, #884] @ 0x374 │ │ vcadd.f32 q11, , , #270 │ │ - ldc2l 0, cr4, [r8, #404] @ 0x194 │ │ - ldc2l 0, cr4, [r8, #164] @ 0xa4 │ │ - ldc2l 5, cr8, [r9, #644] @ 0x284 │ │ - ldc2l 15, cr3, [r8, #788] @ 0x314 │ │ + ldc2l 0, cr4, [r8, #584] @ 0x248 │ │ + ldc2l 0, cr4, [r8, #344] @ 0x158 │ │ + ldc2l 5, cr8, [r9, #824] @ 0x338 │ │ + ldc2l 15, cr3, [r8, #968] @ 0x3c8 │ │ eoreq sl, fp, r8, lsr ip │ │ ldc2l 1, cr2, [sl, #1016] @ 0x3f8 │ │ - ldc2l 15, cr3, [r8, #84] @ 0x54 │ │ + ldc2l 15, cr3, [r8, #264] @ 0x108 │ │ eoreq sl, fp, r8, ror #22 │ │ - ldc2l 2, cr8, [r9, #548] @ 0x224 │ │ + ldc2l 2, cr8, [r9, #728] @ 0x2d8 │ │ ldc2l 6, cr6, [r7, #772] @ 0x304 │ │ - ldc2l 14, cr3, [r8, #436] @ 0x1b4 │ │ - ldc2l 3, cr8, [r9, #660] @ 0x294 │ │ - ldc2l 13, cr3, [r8, #804] @ 0x324 │ │ + ldc2l 14, cr3, [r8, #616] @ 0x268 │ │ + ldc2l 3, cr8, [r9, #840] @ 0x348 │ │ + ldc2l 13, cr3, [r8, #984] @ 0x3d8 │ │ eoreq sl, fp, r8, asr #20 │ │ ldc2l 2, cr1, [fp, #932] @ 0x3a4 │ │ - ldc2l 15, cr11, [r8, #84] @ 0x54 │ │ + ldc2l 15, cr11, [r8, #264] @ 0x108 │ │ ldc2l 11, cr5, [sl, #440] @ 0x1b8 @ │ │ - ldc2l 13, cr3, [r8, #180] @ 0xb4 │ │ + ldc2l 13, cr3, [r8, #360] @ 0x168 │ │ vcadd.f32 d27, d26, d20, #270 │ │ ldc2l 12, cr13, [sl, #992] @ 0x3e0 │ │ - ldc2l 12, cr3, [r8, #788] @ 0x314 │ │ - ldc2l 6, cr12, [r7, #228] @ 0xe4 │ │ + ldc2l 12, cr3, [r8, #968] @ 0x3c8 │ │ + ldc2l 6, cr12, [r7, #408] @ 0x198 │ │ eoreq sl, fp, r0, lsr r9 │ │ - ldc2l 6, cr12, [r7, #780] @ 0x30c │ │ - ldc2l 12, cr3, [r8, #84] @ 0x54 │ │ + ldc2l 6, cr12, [r7, #960] @ 0x3c0 │ │ + ldc2l 12, cr3, [r8, #264] @ 0x108 │ │ ldc2l 13, cr15, [r9, #908] @ 0x38c │ │ - ldc2l 1, cr8, [r9, #144] @ 0x90 │ │ + ldc2l 1, cr8, [r9, #324] @ 0x144 │ │ │ │ 0249f420 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #108 @ 0x6c │ │ mov r4, r3 │ │ mov r8, r2 │ │ @@ -1401291,43 +1401291,43 @@ │ │ ldr r0, [pc, #132] @ 249fa58 │ │ mov r1, #8 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 8, cr2, [r8, #988] @ 0x3dc │ │ + ldc2l 9, cr2, [r8, #72] @ 0x48 @ │ │ ldc2l 2, cr6, [r7, #532] @ 0x214 │ │ - ldc2l 10, cr3, [r8, #132] @ 0x84 @ │ │ - ldc2l 9, cr3, [r8, #458] @ 0x1ca @ │ │ - ldc2l 15, cr7, [r9, #372] @ 0x174 │ │ - ldc2l 9, cr3, [r8, #258] @ 0x102 @ │ │ + ldc2l 10, cr3, [r8, #312] @ 0x138 @ │ │ + ldc2l 10, cr3, [r8, #72] @ 0x48 @ │ │ + ldc2l 15, cr7, [r9, #552] @ 0x228 │ │ + ldc2l 9, cr3, [r8, #348] @ 0x15c @ │ │ strdeq sl, [fp], -ip @ │ │ ldc2l 11, cr1, [sl, #744] @ 0x2e8 @ │ │ - ldc2l 8, cr3, [r8, #836] @ 0x344 │ │ + ldc2l 8, cr3, [r8, #1016] @ 0x3f8 │ │ eoreq sl, fp, ip, lsr #10 │ │ - ldc2l 12, cr7, [r9, #276] @ 0x114 │ │ + ldc2l 12, cr7, [r9, #456] @ 0x1c8 │ │ ldc2l 0, cr6, [r7, #500] @ 0x1f4 │ │ - vcadd.f32 d19, d8, d25, #270 │ │ - ldc2l 13, cr7, [r9, #388] @ 0x184 │ │ - ldc2l 7, cr3, [r8, #532] @ 0x214 │ │ + ldc2l 8, cr3, [r8, #344] @ 0x158 │ │ + ldc2l 13, cr7, [r9, #568] @ 0x238 │ │ + ldc2l 7, cr3, [r8, #712] @ 0x2c8 │ │ eoreq sl, fp, ip, lsl #8 │ │ ldc2l 12, cr0, [fp, #692] @ 0x2b4 │ │ - ldc2l 8, cr11, [r8, #868] @ 0x364 │ │ + ldc2l 9, cr11, [r8, #12] @ │ │ ldc2l 13, cr3, [r7, #420] @ 0x1a4 │ │ - ldc2l 6, cr3, [r8, #932] @ 0x3a4 │ │ + ldc2l 7, cr3, [r8, #88] @ 0x58 │ │ ldc2l 2, cr11, [sl, #384] @ 0x180 │ │ ldc2l 6, cr13, [sl, #720] @ 0x2d0 │ │ - ldc2l 6, cr3, [r8, #516] @ 0x204 │ │ - ldc2l 15, cr11, [r7, #980] @ 0x3d4 │ │ + ldc2l 6, cr3, [r8, #696] @ 0x2b8 │ │ + ldc2l 0, cr12, [r7, #136] @ 0x88 │ │ strdeq sl, [fp], -r8 @ │ │ - ldc2l 0, cr12, [r7, #540] @ 0x21c │ │ - ldc2l 5, cr3, [r8, #868] @ 0x364 │ │ + ldc2l 0, cr12, [r7, #720] @ 0x2d0 │ │ + ldc2l 6, cr3, [r8, #24] │ │ ldc2l 7, cr15, [r9, #668] @ 0x29c │ │ - ldc2l 3, cr2, [r8, #460] @ 0x1cc │ │ + ldc2l 3, cr2, [r8, #640] @ 0x280 │ │ │ │ 0249fa5c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #108 @ 0x6c │ │ mov r4, r3 │ │ mov r8, r2 │ │ @@ -1401694,39 +1401694,39 @@ │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 13, cr0, [fp, #220] @ 0xdc │ │ ldc2l 12, cr5, [r7, #292] @ 0x124 │ │ - ldc2l 3, cr3, [r8, #916] @ 0x394 │ │ - ldc2l 3, cr3, [r8, #676] @ 0x2a4 │ │ - ldc2l 9, cr7, [r9, #66] @ 0x42 @ │ │ - ldc2l 3, cr3, [r8, #276] @ 0x114 │ │ + ldc2l 4, cr3, [r8, #72] @ 0x48 │ │ + ldc2l 3, cr3, [r8, #856] @ 0x358 │ │ + ldc2l 9, cr7, [r9, #156] @ 0x9c @ │ │ + ldc2l 3, cr3, [r8, #456] @ 0x1c8 │ │ eoreq r9, fp, r8, asr #31 │ │ ldc2l 5, cr1, [sl, #504] @ 0x1f8 │ │ - ldc2l 2, cr3, [r8, #596] @ 0x254 │ │ + ldc2l 2, cr3, [r8, #776] @ 0x308 │ │ strdeq r9, [fp], -r8 @ │ │ - ldc2l 6, cr7, [r9, #36] @ 0x24 │ │ + ldc2l 6, cr7, [r9, #216] @ 0xd8 │ │ ldc2l 10, cr5, [r7, #260] @ 0x104 @ │ │ - ldc2l 1, cr3, [r8, #948] @ 0x3b4 │ │ - ldc2l 7, cr7, [r9, #148] @ 0x94 │ │ - ldc2l 1, cr3, [r8, #292] @ 0x124 │ │ + ldc2l 2, cr3, [r8, #104] @ 0x68 │ │ + ldc2l 7, cr7, [r9, #328] @ 0x148 │ │ + ldc2l 1, cr3, [r8, #472] @ 0x1d8 │ │ ldrdeq r9, [fp], -r8 @ │ │ ldc2l 6, cr0, [fp, #452] @ 0x1c4 │ │ - ldc2l 2, cr11, [r8, #628] @ 0x274 │ │ + ldc2l 2, cr11, [r8, #808] @ 0x328 │ │ ldc2l 7, cr13, [r9, #588] @ 0x24c │ │ - ldc2l 0, cr3, [r8, #692] @ 0x2b4 │ │ + ldc2l 0, cr3, [r8, #872] @ 0x368 │ │ ldc2l 12, cr10, [sl, #144] @ 0x90 │ │ ldc2l 0, cr13, [sl, #480] @ 0x1e0 │ │ - ldc2l 0, cr3, [r8, #276] @ 0x114 │ │ - ldc2l 9, cr11, [r7, #370] @ 0x172 @ │ │ + ldc2l 0, cr3, [r8, #456] @ 0x1c8 │ │ + ldc2l 9, cr11, [r7, #460] @ 0x1cc @ │ │ eoreq r9, fp, r4, asr #25 │ │ - ldc2l 10, cr11, [r7, #300] @ 0x12c @ │ │ - ldc2l 15, cr2, [r8, #628] @ 0x274 │ │ + ldc2l 10, cr11, [r7, #480] @ 0x1e0 @ │ │ + ldc2l 15, cr2, [r8, #808] @ 0x328 │ │ ldc2l 1, cr15, [r9, #428] @ 0x1ac │ │ ldc2l 7, cr0, [fp, #716] @ 0x2cc │ │ │ │ 024a0098 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #48 @ 0x30 │ │ @@ -1401814,16 +1401814,16 @@ │ │ mov r0, r5 │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r7, #0 │ │ b 24a00ec │ │ ldc2l 13, cr9, [r7, #144] @ 0x90 │ │ ldc2l 6, cr14, [sl, #996] @ 0x3e4 │ │ - ldc2l 13, cr2, [r8, #484] @ 0x1e4 │ │ - ldc2l 9, cr7, [r8, #470] @ 0x1d6 @ │ │ + ldc2l 13, cr2, [r8, #664] @ 0x298 │ │ + ldc2l 10, cr7, [r8, #96] @ 0x60 @ │ │ │ │ 024a020c : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #24 │ │ ldr r1, [r1, #16] │ │ ldr lr, [pc, #60] @ 24a0260 │ │ @@ -1402103,21 +1402103,21 @@ │ │ b 24a05c8 │ │ ldr r0, [fp, #-36] @ 0xffffffdc │ │ ldr r5, [sp, #36] @ 0x24 │ │ add r0, r0, #1 │ │ str r0, [fp, #-36] @ 0xffffffdc │ │ add r5, r9, r5 │ │ b 24a0550 │ │ - ldc2l 10, cr11, [r8, #432] @ 0x1b0 @ │ │ + ldc2l 10, cr11, [r8, #612] @ 0x264 @ │ │ ldc2l 1, cr1, [sl, #840] @ 0x348 │ │ - ldc2l 12, cr2, [r8, #148] @ 0x94 │ │ - ldc2l 9, cr11, [r8, #296] @ 0x128 @ │ │ + ldc2l 12, cr2, [r8, #328] @ 0x148 │ │ + ldc2l 9, cr11, [r8, #386] @ 0x182 @ │ │ ldc2l 12, cr7, [r7, #544] @ 0x220 │ │ - ldc2l 11, cr2, [r8, #404] @ 0x194 @ │ │ - vcadd.f32 , q12, , #270 │ │ + ldc2l 11, cr2, [r8, #584] @ 0x248 @ │ │ + ldc2l 9, cr9, [r8, #52] @ 0x34 @ │ │ eoreq r9, fp, r0, lsr r8 │ │ eoreq r9, fp, r4, lsr #13 │ │ │ │ 024a069c : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #16 │ │ @@ -1402167,17 +1402167,17 @@ │ │ bl 270da10 │ │ mov r0, r4 │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #8 │ │ pop {r4, sl, fp, pc} │ │ - ldc2l 4, cr7, [r8, #776] @ 0x308 │ │ - ldc2l 15, cr6, [r9, #232] @ 0xe8 │ │ - ldc2l 7, cr2, [r8, #772] @ 0x304 │ │ + ldc2l 4, cr7, [r8, #956] @ 0x3bc │ │ + ldc2l 15, cr6, [r9, #412] @ 0x19c │ │ + ldc2l 7, cr2, [r8, #952] @ 0x3b8 │ │ ldc2l 0, cr7, [r7, #664] @ 0x298 │ │ │ │ 024a0780 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #276 @ 0x114 │ │ mov r9, r0 │ │ @@ -1402722,45 +1402722,45 @@ │ │ sub r1, fp, #124 @ 0x7c │ │ mov r0, r5 │ │ mov r2, #1 │ │ bl 270db00 │ │ ldr r0, [pc, #80] @ 24a1060 │ │ add r0, pc, r0 │ │ b 24a0990 │ │ - ldc2l 4, cr9, [r8, #428] @ 0x1ac │ │ + ldc2l 4, cr9, [r8, #608] @ 0x260 │ │ ldc2l 14, cr12, [r9, #936] @ 0x3a8 │ │ - ldc2l 7, cr2, [r8, #180] @ 0xb4 │ │ + ldc2l 7, cr2, [r8, #360] @ 0x168 │ │ eoreq r9, fp, ip, lsl #8 │ │ - ldc2l 3, cr9, [r8, #44] @ 0x2c │ │ - ldc2l 2, cr7, [r8, #780] @ 0x30c │ │ - ldc2l 5, cr2, [r8, #836] @ 0x344 │ │ + ldc2l 3, cr9, [r8, #224] @ 0xe0 │ │ + ldc2l 2, cr7, [r8, #960] @ 0x3c0 │ │ + ldc2l 5, cr2, [r8, #1016] @ 0x3f8 │ │ eoreq r9, fp, ip, ror r2 │ │ - ldc2l 10, cr10, [r8, #404] @ 0x194 @ │ │ - ldc2l 2, cr9, [r8, #860] @ 0x35c │ │ + ldc2l 10, cr10, [r8, #584] @ 0x248 @ │ │ + ldc2l 3, cr9, [r8, #16] │ │ ldc2l 12, cr10, [r9, #768] @ 0x300 │ │ - ldc2l 5, cr2, [r8, #628] @ 0x274 │ │ - ldc2l 3, cr9, [r8, #332] @ 0x14c │ │ + ldc2l 5, cr2, [r8, #808] @ 0x328 │ │ + ldc2l 3, cr9, [r8, #512] @ 0x200 │ │ ldc2l 0, cr5, [r7, #420] @ 0x1a4 │ │ - ldc2l 6, cr2, [r8, #84] @ 0x54 │ │ + ldc2l 6, cr2, [r8, #264] @ 0x108 │ │ strdeq r9, [fp], -ip @ │ │ - ldc2l 12, cr8, [r8, #444] @ 0x1bc │ │ - ldc2l 4, cr4, [r9, #716] @ 0x2cc │ │ - ldc2l 15, cr1, [r8, #196] @ 0xc4 │ │ - ldc2l 14, cr1, [r9, #340] @ 0x154 │ │ - ldc2l 1, cr9, [r8, #924] @ 0x39c │ │ - ldc2l 13, cr12, [r8, #232] @ 0xe8 │ │ - ldc2l 4, cr2, [r8, #676] @ 0x2a4 │ │ + ldc2l 12, cr8, [r8, #624] @ 0x270 │ │ + ldc2l 4, cr4, [r9, #896] @ 0x380 │ │ + ldc2l 15, cr1, [r8, #376] @ 0x178 │ │ + ldc2l 14, cr1, [r9, #520] @ 0x208 │ │ + ldc2l 2, cr9, [r8, #80] @ 0x50 │ │ + ldc2l 13, cr12, [r8, #412] @ 0x19c │ │ + ldc2l 4, cr2, [r8, #856] @ 0x358 │ │ eoreq r9, fp, r4, ror r1 │ │ streq pc, [r4], #1924 @ 0x784 │ │ eoreq r9, fp, r4, asr #2 │ │ streq pc, [r4], #1816 @ 0x718 │ │ - ldc2l 7, cr12, [r8, #328] @ 0x148 │ │ - ldc2l 7, cr2, [r9] │ │ - ldc2l 13, cr5, [r9, #304] @ 0x130 │ │ - ldc2l 5, cr2, [r9, #16] │ │ + ldc2l 7, cr12, [r8, #508] @ 0x1fc │ │ + ldc2l 7, cr2, [r9, #180] @ 0xb4 │ │ + ldc2l 13, cr5, [r9, #484] @ 0x1e4 │ │ + ldc2l 5, cr2, [r9, #196] @ 0xc4 │ │ │ │ 024a1090 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #188 @ 0xbc │ │ mov r4, r0 │ │ ldr r0, [r0] │ │ @@ -1403128,16 +1403128,16 @@ │ │ add r0, sp, #40 @ 0x28 │ │ sub r2, fp, #48 @ 0x30 │ │ mov r1, r0 │ │ bl 270e3e0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 6, cr5, [r9, #720] @ 0x2d0 │ │ - ldc2l 6, cr6, [r8, #804] @ 0x324 │ │ + ldc2l 6, cr5, [r9, #900] @ 0x384 │ │ + ldc2l 6, cr6, [r8, #984] @ 0x3d8 │ │ │ │ 024a166c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8} │ │ sub sp, sp, #504 @ 0x1f8 │ │ @@ -1404154,15 +1404154,15 @@ │ │ cmn r0, #1 │ │ mov r4, #0 │ │ movwgt r4, #1 │ │ ldr r7, [pc, #2980] @ 24a3200 │ │ mov r8, r4 │ │ add r7, pc, r7 │ │ b 24a2b34 │ │ - ldc2l 5, cr14, [r7, #196] @ 0xc4 │ │ + ldc2l 5, cr14, [r7, #376] @ 0x178 │ │ movw r9, #53392 @ 0xd090 │ │ cmp r7, #84 @ 0x54 │ │ movt r9, #3 │ │ beq 24a2b24 │ │ ldr r7, [pc, #2696] @ 24a3108 │ │ cmp sl, #84 @ 0x54 │ │ ldr sl, [pc, #2692] @ 24a310c │ │ @@ -1404218,15 +1404218,15 @@ │ │ ldr r7, [pc, #2760] @ 24a3218 │ │ ldr sl, [pc, #2760] @ 24a321c │ │ cmp r0, #0 │ │ add r7, pc, r7 │ │ movne r8, r4 │ │ add sl, pc, sl │ │ b 24a2b34 │ │ - ldc2l 12, cr11, [r8, #360] @ 0x168 │ │ + ldc2l 12, cr11, [r8, #540] @ 0x21c │ │ ldc2l 6, cr7, [sl, #692] @ 0x2b4 │ │ ldr r1, [fp, #16] │ │ movw r9, #53392 @ 0xd090 │ │ ldr r0, [fp, #-248] @ 0xffffff08 │ │ movt r9, #3 │ │ ldr r2, [r1] │ │ sub r1, r0, #1 │ │ @@ -1404337,19 +1404337,19 @@ │ │ ldr r0, [pc, #1916] @ 24a30a8 │ │ mov r8, #0 │ │ add r0, pc, r0 │ │ ldr r0, [r0, r1, lsl #2] │ │ cmp r5, r0 │ │ movwle r8, #1 │ │ b 24a2b34 │ │ - ldc2l 10, cr11, [r8, #728] @ 0x2d8 @ │ │ + ldc2l 10, cr11, [r8, #908] @ 0x38c @ │ │ ldc2l 5, cr7, [sl, #36] @ 0x24 │ │ - ldc2l 1, cr5, [r9, #960] @ 0x3c0 │ │ + ldc2l 2, cr5, [r9, #116] @ 0x74 │ │ ldc2l 4, cr7, [sl, #388] @ 0x184 │ │ - ldc2l 1, cr2, [r8, #848] @ 0x350 │ │ + ldc2l 2, cr2, [r8, #4] │ │ ldc2l 3, cr7, [sl, #916] @ 0x394 │ │ ldrbteq pc, [lr], #2392 @ 0x958 @ │ │ ldc2l 5, cr6, [r7, #532] @ 0x214 │ │ ldc2l 3, cr7, [sl, #324] @ 0x144 │ │ streq lr, [r4], #1732 @ 0x6c4 │ │ ldr r0, [pc, #1996] @ 24a313c │ │ movw r3, #829 @ 0x33d │ │ @@ -1404547,16 +1404547,16 @@ │ │ cmp r0, #1 │ │ mov r8, #0 │ │ movwlt r8, #1 │ │ b 24a2b34 │ │ ldc2l 9, cr9, [r9, #444] @ 0x1bc @ │ │ ldc2l 1, cr7, [sl, #852] @ 0x354 │ │ ldc2l 3, cr6, [r7, #728] @ 0x2d8 │ │ - ldc2l 2, cr1, [r8, #180] @ 0xb4 │ │ - ldc2l 7, cr9, [r8, #52] @ 0x34 │ │ + ldc2l 2, cr1, [r8, #360] @ 0x168 │ │ + ldc2l 7, cr9, [r8, #232] @ 0xe8 │ │ strdeq r7, [fp], -r4 @ │ │ ldr r1, [fp, #16] │ │ movw r9, #53392 @ 0xd090 │ │ ldr r0, [fp, #-248] @ 0xffffff08 │ │ movt r9, #3 │ │ ldr r2, [r1] │ │ sub r1, r0, #1 │ │ @@ -1404679,16 +1404679,16 @@ │ │ bcc 24a26f8 │ │ ldr r0, [pc, #728] @ 24a3160 │ │ mov r2, sl │ │ movw r3, #834 @ 0x342 │ │ add r0, pc, r0 │ │ b 24a26f0 │ │ ldrdeq r7, [fp], -r4 @ │ │ - ldc2l 7, cr15, [r8, #116] @ 0x74 │ │ - ldc2l 15, cr0, [r8, #372] @ 0x174 │ │ + ldc2l 7, cr15, [r8, #296] @ 0x128 │ │ + ldc2l 15, cr0, [r8, #552] @ 0x228 │ │ ldr r0, [pc, #544] @ 24a30c8 │ │ movw r3, #787 @ 0x313 │ │ ldr r7, [pc, #540] @ 24a30cc │ │ add r0, pc, r0 │ │ add r7, pc, r7 │ │ mov r2, r7 │ │ bl 270da30 │ │ @@ -1404795,17 +1404795,17 @@ │ │ bl 270db00 │ │ ldr r0, [pc, #28] @ 24a3074 │ │ mov r1, #18 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ b 24a20c0 │ │ ldreq r8, [r0, #-2736]! @ 0xfffff550 │ │ - ldc2l 11, cr13, [r7, #52] @ 0x34 @ │ │ + ldc2l 11, cr13, [r7, #232] @ 0xe8 @ │ │ ldc2l 6, cr8, [r9, #124] @ 0x7c │ │ - ldc2l 14, cr15, [r7, #740] @ 0x2e4 │ │ + ldc2l 14, cr15, [r7, #920] @ 0x398 │ │ ldc2l 7, cr4, [r7, #632] @ 0x278 │ │ ldc2l 13, cr6, [sl, #580] @ 0x244 │ │ ldc2l 5, cr11, [r9, #172] @ 0xac │ │ ldc2l 4, cr11, [r9, #988] @ 0x3dc │ │ ldc2l 4, cr9, [r9, #408] @ 0x198 │ │ streq fp, [ip, #-2216]! @ 0xfffff758 │ │ ldc2l 4, cr9, [r9, #136] @ 0x88 │ │ @@ -1404837,40 +1404837,40 @@ │ │ vcadd.f32 d29, d26, d0, #270 │ │ ldreq r6, [sp, #-2360] @ 0xfffff6c8 │ │ ldreq r7, [r0, #-3056]! @ 0xfffff410 │ │ vcadd.f32 , q5, q0, #270 │ │ ldreq r6, [sp, #-2296] @ 0xfffff708 │ │ ldreq r8, [r0, #-1252]! @ 0xfffffb1c │ │ ldc2l 7, cr6, [sl, #980] @ 0x3d4 │ │ - ldc2l 5, cr1, [r8, #736] @ 0x2e0 │ │ + ldc2l 5, cr1, [r8, #916] @ 0x394 │ │ ldrbteq lr, [lr], #3412 @ 0xd54 │ │ - ldc2l 5, cr1, [r8, #496] @ 0x1f0 │ │ + ldc2l 5, cr1, [r8, #676] @ 0x2a4 │ │ ldrbteq lr, [lr], #3352 @ 0xd18 │ │ ldreq r8, [r0, #-2188]! @ 0xfffff774 │ │ ldc2l 11, cr6, [sl, #628] @ 0x274 @ │ │ - ldc2l 9, cr1, [r8, #192] @ 0xc0 @ │ │ + ldc2l 9, cr1, [r8, #282] @ 0x11a @ │ │ ldrbteq pc, [lr], #252 @ 0xfc @ │ │ - ldc2l 9, cr1, [r8, #72] @ 0x48 @ │ │ + ldc2l 9, cr1, [r8, #162] @ 0xa2 @ │ │ ldrbteq pc, [lr], #196 @ 0xc4 @ │ │ ldc2l 5, cr6, [sl, #964] @ 0x3c4 │ │ - ldc2l 2, cr1, [r8, #976] @ 0x3d0 │ │ + ldc2l 3, cr1, [r8, #132] @ 0x84 │ │ ldc2l 5, cr6, [sl, #20] │ │ ldrbteq lr, [lr], #2696 @ 0xa88 │ │ - ldc2l 2, cr1, [r8, #704] @ 0x2c0 │ │ + ldc2l 2, cr1, [r8, #884] @ 0x374 │ │ ldrbteq lr, [lr], #2640 @ 0xa50 │ │ ldc2l 0, cr6, [sl, #292] @ 0x124 │ │ - ldc2l 14, cr0, [r8, #128] @ 0x80 │ │ + ldc2l 14, cr0, [r8, #308] @ 0x134 │ │ ldrbteq lr, [lr], #1468 @ 0x5bc │ │ ldreq r7, [r0, #-3312]! @ 0xfffff310 │ │ - ldc2l 13, cr0, [r8, #880] @ 0x370 │ │ + ldc2l 14, cr0, [r8, #36] @ 0x24 │ │ ldc2l 1, cr6, [sl, #756] @ 0x2f4 │ │ - ldc2l 15, cr0, [r8, #592] @ 0x250 │ │ + ldc2l 15, cr0, [r8, #772] @ 0x304 │ │ ldrbteq lr, [lr], #1840 @ 0x730 │ │ ldreq r7, [r0, #-3684]! @ 0xfffff19c │ │ - ldc2l 15, cr0, [r8, #320] @ 0x140 │ │ + ldc2l 15, cr0, [r8, #500] @ 0x1f4 │ │ ldrbteq lr, [lr], #1772 @ 0x6ec │ │ ldc2l 4, cr5, [r7, #948] @ 0x3b4 │ │ ldc2l 2, cr6, [sl, #740] @ 0x2e4 │ │ streq sp, [r4], #1596 @ 0x63c │ │ ldc2l 4, cr5, [r7, #644] @ 0x284 │ │ ldc2l 2, cr6, [sl, #436] @ 0x1b4 │ │ streq sp, [r4], #1520 @ 0x5f0 │ │ @@ -1405949,22 +1405949,22 @@ │ │ str r3, [fp, #-36] @ 0xffffffdc │ │ ldr r0, [pc, #4076] @ 24a5244 │ │ add r0, pc, r0 │ │ add r2, r0, r1, lsl #2 │ │ b 24a44a0 │ │ ldreq fp, [pc, #-2876]! @ 24a372c │ │ ldreq fp, [pc, #-2896]! @ 24a371c │ │ - ldc2l 8, cr2, [r8, #864] @ 0x360 │ │ + ldc2l 9, cr2, [r8, #10] @ │ │ ldc2l 13, cr15, [r9, #760] @ 0x2f8 │ │ ldreq fp, [pc, #-2764]! @ 24a37ac │ │ ldc2l 13, cr15, [r9, #552] @ 0x228 │ │ ldc2l 5, cr11, [sl, #860] @ 0x35c │ │ ldc2l 1, cr7, [sl, #696] @ 0x2b8 │ │ strbeq r3, [r0, #-2072] @ 0xfffff7e8 │ │ - vcadd.f32 d18, d8, d16, #270 │ │ + vcadd.f32 q9, q4, , #270 │ │ ldreq fp, [pc, #-2692]! @ 24a380c │ │ ldreq fp, [pc, #-3516]! @ 24a34d8 │ │ ldreq fp, [pc, #-2664]! @ 24a3830 │ │ ldreq fp, [pc, #-2608]! @ 24a386c │ │ strbeq r2, [r0, #-1624] @ 0xfffff9a8 │ │ ldr r0, [pc, #4004] @ 24a5248 │ │ mov r1, r2 │ │ @@ -1406060,15 +1406060,15 @@ │ │ ldreq lr, [pc, #-1160]! @ 24a3f88 │ │ ldreq fp, [pc, #-2180]! @ 24a3b90 │ │ ldreq fp, [pc, #-2144]! @ 24a3bb8 │ │ ldreq fp, [pc, #-2148]! @ 24a3bb8 │ │ ldreq fp, [pc, #-2120]! @ 24a3bd8 │ │ eoreq r6, fp, r8, ror r6 │ │ strbeq r0, [r0, #-2872] @ 0xfffff4c8 │ │ - ldc2l 5, cr2, [r8, #688] @ 0x2b0 │ │ + ldc2l 5, cr2, [r8, #868] @ 0x364 │ │ ldc2l 0, cr8, [r9, #692] @ 0x2b4 │ │ ldreq fp, [pc, #-2848]! @ 24a3914 │ │ ldreq fp, [pc, #-2032]! @ 24a3c48 │ │ ldreq fp, [pc, #-2856]! @ 24a3914 │ │ strbeq r2, [r0, #-1028] @ 0xfffffbfc │ │ ldreq fp, [pc, #-2804]! @ 24a3950 │ │ ldreq fp, [pc, #-2812]! @ 24a394c │ │ @@ -1406306,19 +1406306,19 @@ │ │ str r4, [r5, r1, lsl #2] │ │ b 24a46cc │ │ ldc2l 6, cr1, [sl, #40] @ 0x28 │ │ ldreq fp, [pc, #-1896]! @ 24a408c │ │ ldreq fp, [pc, #-1436]! @ 24a425c │ │ ldreq fp, [pc, #-1416]! @ 24a4274 │ │ ldreq fp, [pc, #-2276]! @ 24a3f1c │ │ - ldc2l 1, cr10, [r7, #88] @ 0x58 │ │ + ldc2l 1, cr10, [r7, #268] @ 0x10c │ │ strbeq r0, [r0, #-2592] @ 0xfffff5e0 │ │ ldreq fp, [pc, #-1356]! @ 24a42c0 │ │ ldreq fp, [pc, #-2208]! @ 24a3f70 │ │ - ldc2l 1, cr8, [r7, #364] @ 0x16c │ │ + ldc2l 1, cr8, [r7, #544] @ 0x220 │ │ ldreq fp, [pc, #-2156]! @ 24a3fac │ │ strbeq r0, [r0, #-2104] @ 0xfffff7c8 │ │ strbeq r1, [r0, #-24] @ 0xffffffe8 │ │ strbeq r0, [r0, #-2484] @ 0xfffff64c │ │ ldr r0, [pc, #4016] @ 24a57d8 │ │ mov r2, r9 │ │ mov r3, #1280 @ 0x500 │ │ @@ -1406483,19 +1406483,19 @@ │ │ cmp r1, #99 @ 0x63 │ │ bhi 24a4ad4 │ │ mov r2, r9 │ │ ldr r9, [pc, #3500] @ 24a5864 │ │ add r9, pc, r9 │ │ b 24a44c0 │ │ ldreq fp, [pc, #-788]! @ 24a47b0 │ │ - ldc2l 1, cr12, [r7, #40] @ 0x28 │ │ + ldc2l 1, cr12, [r7, #220] @ 0xdc │ │ ldreq sp, [pc, #-3424]! @ 24a3d6c │ │ strbeq r0, [r0, #-1524] @ 0xfffffa0c │ │ - ldc2l 1, cr6, [r8] │ │ - ldc2l 0, cr2, [r8, #288] @ 0x120 │ │ + ldc2l 1, cr6, [r8, #180] @ 0xb4 │ │ + ldc2l 0, cr2, [r8, #468] @ 0x1d4 │ │ ldr r0, [pc, #3468] @ 24a5868 │ │ mov sl, r3 │ │ mov r1, r7 │ │ mov r2, r6 │ │ add r0, pc, r0 │ │ movw r3, #1227 @ 0x4cb │ │ bl 270da30 │ │ @@ -1406510,15 +1406510,15 @@ │ │ mov r2, r9 │ │ ldr r9, [pc, #4092] @ 24a5b18 │ │ mov r3, sl │ │ add r9, pc, r9 │ │ b 24a44cc │ │ strbeq r0, [r0, #-1452] @ 0xfffffa54 │ │ ldc2l 14, cr8, [sl, #784] @ 0x310 │ │ - ldc2l 0, cr2, [r8, #48] @ 0x30 │ │ + ldc2l 0, cr2, [r8, #228] @ 0xe4 │ │ ldreq fp, [pc, #-568]! @ 24a4900 │ │ ldr r0, [pc, #4064] @ 24a5b1c │ │ mov r2, r6 │ │ movw r3, #1227 @ 0x4cb │ │ add r0, pc, r0 │ │ bl 270da30 │ │ ldr r1, [pc, #4048] @ 24a5b20 │ │ @@ -1406534,15 +1406534,15 @@ │ │ bhi 24a4bb8 │ │ mov r2, r9 │ │ ldr r9, [pc, #4088] @ 24a5b78 │ │ mov r3, sl │ │ add r9, pc, r9 │ │ b 24a44e4 │ │ ldreq fp, [pc, #-572]! @ 24a4954 │ │ - ldc2l 15, cr1, [r8, #816] @ 0x330 │ │ + ldc2l 15, cr1, [r8, #996] @ 0x3e4 │ │ ldreq fp, [pc, #-1388]! @ 24a462c │ │ ldreq fp, [pc, #-544]! @ 24a497c │ │ ldreq fp, [pc, #-532]! @ 24a498c │ │ ldreq fp, [pc, #-512]! @ 24a49a4 │ │ ldreq fp, [pc, #-1324]! @ 24a467c │ │ strbeq r0, [r0, #-2904] @ 0xfffff4a8 │ │ ldreq fp, [pc, #-504]! @ 24a49b8 │ │ @@ -1406641,15 +1406641,15 @@ │ │ ldreq fp, [pc, #-144]! @ 24a4c94 │ │ ldreq fp, [pc, #-972]! @ 24a495c │ │ ldreq fp, [pc, #-932]! @ 24a4988 │ │ strbeq r0, [r0, #-2496] @ 0xfffff640 │ │ ldreq fp, [pc, #-912]! @ 24a49a4 │ │ ldc2l 7, cr13, [r9, #220] @ 0xdc │ │ strbeq r2, [r0, #-3480] @ 0xfffff268 │ │ - ldc2l 13, cr1, [r8, #672] @ 0x2a0 │ │ + ldc2l 13, cr1, [r8, #852] @ 0x354 │ │ mov r0, r2 │ │ ldr r1, [fp, #-56] @ 0xffffffc8 │ │ add r2, r0, #1 │ │ str r2, [r5] │ │ cmp r0, r1 │ │ bge 24a5198 │ │ sub r1, r2, #1 │ │ @@ -1406708,15 +1406708,15 @@ │ │ vcadd.f32 d23, d9, d21, #270 │ │ ldreq sl, [pc, #-3904]! @ 24a3ef4 │ │ ldreq fp, [pc, #-664]! @ 24a4ba0 │ │ ldreq fp, [pc, #-228]! @ 24a4d58 │ │ ldreq sl, [pc, #-3864]! @ 24a3f28 │ │ strbeq r0, [r0, #-972] @ 0xfffffc34 │ │ strbeq r0, [r0, #-1756] @ 0xfffff924 │ │ - ldc2l 12, cr1, [r8, #640] @ 0x280 │ │ + ldc2l 12, cr1, [r8, #820] @ 0x334 │ │ ldc2l 15, cr0, [sl, #168] @ 0xa8 │ │ ldreq fp, [pc, #-136]! @ 24a4dcc │ │ ldreq sl, [pc, #-3772]! @ 24a3f9c │ │ ldreq sl, [pc, #-3752]! @ 24a3fb4 │ │ ldreq fp, [pc, #-516]! @ 24a4c5c │ │ ldr r0, [pc, #4080] @ 24a5e54 │ │ mov r2, r4 │ │ @@ -1406762,19 +1406762,19 @@ │ │ ldr r5, [pc, #3952] @ 24a5e78 │ │ ldr r5, [pc, r5] │ │ bcs 24a4f98 │ │ ldr r9, [pc, #3944] @ 24a5e7c │ │ add r9, pc, r9 │ │ b 24a4fb8 │ │ ldc2l 5, cr13, [r9, #700] @ 0x2bc │ │ - ldc2l 10, cr9, [r7, #168] @ 0xa8 @ │ │ + ldc2l 10, cr9, [r7, #348] @ 0x15c @ │ │ strbeq r0, [r0, #-820] @ 0xfffffccc │ │ ldreq sl, [pc, #-3680]! @ 24a40cc │ │ ldreq fp, [pc, #-436]! @ 24a4d7c │ │ - ldc2l 10, cr7, [r7, #444] @ 0x1bc @ │ │ + ldc2l 10, cr7, [r7, #624] @ 0x270 @ │ │ ldreq fp, [pc, #-384]! @ 24a4db8 │ │ ldc2l 5, cr13, [r9, #252] @ 0xfc │ │ ldreq sl, [pc, #-3628]! @ 24a4114 │ │ ldreq sl, [pc, #-3580]! @ 24a4148 │ │ ldreq sl, [pc, #-3592]! @ 24a4140 │ │ strbeq r1, [r0, #-2584] @ 0xfffff5e8 │ │ ldreq sl, [pc, #-3544]! @ 24a4178 │ │ @@ -1407016,24 +1407016,24 @@ │ │ ldr r0, [r7] │ │ add r1, pc, r1 │ │ str r0, [r2] │ │ ldr r0, [fp, #16] │ │ ldr r0, [r0] │ │ str r0, [r1] │ │ b 24a5bd4 │ │ - ldc2l 8, cr11, [r7, #728] @ 0x2d8 │ │ + vcadd.f32 , , , #270 │ │ mov r0, #1 │ │ cmp r7, #1 │ │ str r0, [r5] │ │ blt 24a5274 │ │ mov r0, #0 │ │ b 24a5358 │ │ ldreq sp, [pc, #-1292]! @ 24a4e2c │ │ ldreq pc, [pc, #-3488]! @ 24a459c │ │ - ldc2l 8, cr5, [r8, #720] @ 0x2d0 │ │ + vcadd.f32 , q12, , #270 │ │ ldreq pc, [pc, #-3428]! @ 24a45e0 │ │ ldc2l 6, cr8, [sl, #496] @ 0x1f0 │ │ add r1, r0, #2 │ │ add r0, r0, #1 │ │ cmp r0, r7 │ │ str r1, [r5] │ │ bge 24a5dac │ │ @@ -1407326,18 +1407326,18 @@ │ │ sub r0, r0, r7 │ │ b 24a5898 │ │ ldc2l 5, cr0, [sl, #888] @ 0x378 │ │ ldreq sl, [pc, #-1852]! @ 24a50a8 │ │ ldreq sl, [pc, #-1392]! @ 24a5278 │ │ ldreq sl, [pc, #-1372]! @ 24a5290 │ │ ldreq sl, [pc, #-2232]! @ 24a4f38 │ │ - ldc2l 0, cr9, [r7, #936] @ 0x3a8 │ │ + ldc2l 1, cr9, [r7, #92] @ 0x5c │ │ ldreq sl, [pc, #-1320]! @ 24a52d0 │ │ ldreq sl, [pc, #-2172]! @ 24a4f80 │ │ - ldc2l 1, cr7, [r7, #220] @ 0xdc │ │ + ldc2l 1, cr7, [r7, #400] @ 0x190 │ │ ldreq sl, [pc, #-2120]! @ 24a4fbc │ │ ldreq pc, [pc, #-1984]! @ 24a5048 │ │ ldreq pc, [pc, #-4000]! @ 24a486c │ │ ldreq pc, [pc, #-1556]! @ 24a51fc │ │ ldreq pc, [pc, #-2752]! @ 24a4d54 │ │ ldreq ip, [pc, #-3820]! @ 24a492c │ │ ldreq sp, [pc, #-112]! @ 24a57ac │ │ @@ -1407530,15 +1407530,15 @@ │ │ mov r2, #1 │ │ ldr r5, [pc, #1324] @ 24a6038 │ │ add r6, pc, r6 │ │ add r9, pc, r9 │ │ add r5, pc, r5 │ │ b 24a5b60 │ │ ldreq sl, [pc, #-700]! @ 24a5864 │ │ - ldc2l 0, cr11, [r7, #632] @ 0x278 │ │ + ldc2l 0, cr11, [r7, #812] @ 0x32c │ │ ldreq ip, [pc, #-3316]! @ 24a4e34 │ │ ldreq pc, [pc, #-1416]! @ 24a55a4 │ │ mov r0, r9 │ │ mov r2, r5 │ │ movw r3, #939 @ 0x3ab │ │ bl 270da30 │ │ mov r1, r0 │ │ @@ -1407554,15 +1407554,15 @@ │ │ ldr r7, [r4, r1, lsl #2] │ │ cmp r1, #100 @ 0x64 │ │ str r1, [fp, #-36] @ 0xffffffdc │ │ bcs 24a5b28 │ │ mov r3, r2 │ │ b 24a5b48 │ │ ldreq sl, [pc, #-600]! @ 24a5928 │ │ - ldc2l 0, cr5, [r8, #352] @ 0x160 │ │ + ldc2l 0, cr5, [r8, #532] @ 0x214 │ │ ldreq pc, [pc, #-1288]! @ 24a5680 │ │ ldc2l 14, cr7, [sl, #128] @ 0x80 │ │ ldreq sl, [pc, #-448]! @ 24a59d0 │ │ ldr r0, [pc, #1196] @ 24a6040 │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ @@ -1407707,15 +1407707,15 @@ │ │ mov r2, #0 │ │ ldr sl, [pc, #272] @ 24a5ee0 │ │ ldr r9, [pc, #272] @ 24a5ee4 │ │ add r4, pc, r4 │ │ add sl, pc, sl │ │ add r9, pc, r9 │ │ b 24a5e08 │ │ - ldc2l 13, cr0, [r8, #544] @ 0x220 │ │ + ldc2l 13, cr0, [r8, #724] @ 0x2d4 │ │ ldreq sl, [pc, #-832]! @ 24a5aac │ │ ldreq r9, [pc, #-4040]! @ 24a4e28 │ │ ldreq sl, [pc, #-776]! @ 24a5aec │ │ mov r2, r1 │ │ add r1, r1, #1 │ │ cmp r2, r7 │ │ str r5, [r4, r0, lsl #2] │ │ @@ -1407736,51 +1407736,51 @@ │ │ ldr r1, [pc, r1] │ │ b 24a5df0 │ │ str r6, [fp, #-36] @ 0xffffffdc │ │ ldr r6, [fp, #32] │ │ ldr r2, [sp, #44] @ 0x2c │ │ ldr r9, [sp, #48] @ 0x30 │ │ b 24a5274 │ │ - ldc2l 13, cr10, [r7, #472] @ 0x1d8 │ │ + ldc2l 13, cr10, [r7, #652] @ 0x28c │ │ ldreq sl, [pc, #-668]! @ 24a5bc4 │ │ ldreq ip, [pc, #-2496]! @ 24a54a4 │ │ ldreq r9, [pc, #-3876]! @ 24a4f44 │ │ ldc2l 6, cr2, [sl, #44] @ 0x2c │ │ - ldc2l 12, cr0, [r8, #736] @ 0x2e0 │ │ + ldc2l 12, cr0, [r8, #916] @ 0x394 │ │ ldreq sl, [pc, #-1012]! @ 24a5a80 │ │ eoreq r4, fp, ip, lsr #26 │ │ ldreq sl, [pc, #-552]! @ 24a5c54 │ │ ldreq r9, [pc, #-3780]! @ 24a4fbc │ │ - ldc2l 12, cr0, [r8, #368] @ 0x170 │ │ - ldc2l 12, cr4, [r8, #496] @ 0x1f0 │ │ - ldc2l 11, cr0, [r8, #784] @ 0x310 @ │ │ + ldc2l 12, cr0, [r8, #548] @ 0x224 │ │ + ldc2l 12, cr4, [r8, #676] @ 0x2a4 │ │ + ldc2l 11, cr0, [r8, #964] @ 0x3c4 @ │ │ ldreq ip, [pc, #-2568]! @ 24a5488 │ │ eoreq r4, fp, r0, lsr ip │ │ ldreq r9, [pc, #-3544]! @ 24a50c0 │ │ ldreq sl, [pc, #-280]! @ 24a5d84 │ │ ldreq sl, [pc, #-236]! @ 24a5db4 │ │ ldreq sl, [pc, #-208]! @ 24a5dd4 │ │ ldc2l 9, cr7, [sl, #346] @ 0x15a @ │ │ ldreq pc, [pc, #-2120]! @ 24a5664 │ │ eoreq r4, fp, r4, ror fp │ │ ldreq r9, [pc, #-3364]! @ 24a5190 │ │ ldreq sl, [pc, #-88]! @ 24a5e60 │ │ ldreq sl, [pc, #-36]! @ 24a5e98 │ │ ldreq sl, [pc, #-8]! @ 24a5eb8 │ │ vcadd.f32 , q13, q14, #270 │ │ - ldc2l 10, cr0, [r8, #208] @ 0xd0 @ │ │ + ldc2l 10, cr0, [r8, #388] @ 0x184 @ │ │ strbeq r0, [r0, #-2240] @ 0xfffff740 │ │ eoreq r4, fp, ip, lsr #21 │ │ ldreq r9, [pc, #-3996]! @ 24a4f38 │ │ ldreq r9, [pc, #-3988]! @ 24a4f44 │ │ ldreq r9, [pc, #-3060]! @ 24a52e8 │ │ ldreq r9, [pc, #-3908]! @ 24a4f9c │ │ ldreq lr, [pc, #-2416]! @ 24a5574 │ │ ldc2l 7, cr11, [r9, #12] │ │ - ldc2l 13, cr15, [r7, #592] @ 0x250 │ │ + ldc2l 13, cr15, [r7, #772] @ 0x304 │ │ ldreq r9, [pc, #-724]! @ 24a5c1c │ │ ldreq r9, [pc, #-3744]! @ 24a5054 │ │ ldreq r9, [pc, #-3736]! @ 24a5060 │ │ ldreq r9, [pc, #-3712]! @ 24a507c │ │ ldreq r9, [pc, #-3696]! @ 24a5090 │ │ ldreq r9, [pc, #-3652]! @ 24a50c0 │ │ ldreq r9, [pc, #-3636]! @ 24a50d4 │ │ @@ -1407857,28 +1407857,28 @@ │ │ ldreq r9, [pc, #-1724]! @ 24a5968 │ │ mlaeq fp, r8, r1, r4 │ │ strbeq r1, [r0, #-200] @ 0xffffff38 │ │ ldreq r9, [pc, #-820]! @ 24a5cfc │ │ ldreq r9, [pc, #-824]! @ 24a5cfc │ │ ldreq lr, [pc, #-3128]! @ 24a5400 │ │ ldc2l 9, cr11, [r9, #406] @ 0x196 @ │ │ - ldc2l 0, cr0, [r8, #368] @ 0x170 │ │ + ldc2l 0, cr0, [r8, #548] @ 0x224 │ │ ldreq r9, [pc, #-1480]! @ 24a5a7c │ │ ldreq lr, [pc, #-1364]! @ 24a5af4 │ │ ldc2l 9, cr11, [r9, #78] @ 0x4e @ │ │ - ldc2l 15, cr15, [r7, #736] @ 0x2e0 │ │ + ldc2l 15, cr15, [r7, #916] @ 0x394 │ │ ldreq lr, [pc, #-2932]! @ 24a54e0 │ │ ldreq r9, [pc, #-464]! @ 24a5e88 │ │ ldreq lr, [pc, #-1272]! @ 24a5b64 │ │ strbeq r0, [r0, #-3924] @ 0xfffff0ac │ │ strbeq r0, [r0, #-3888] @ 0xfffff0d0 │ │ ldreq r9, [pc, #-408]! @ 24a5ed0 │ │ ldreq lr, [pc, #-1976]! @ 24a58b4 │ │ ldreq r9, [pc, #-796]! @ 24a5d54 │ │ - ldc2l 15, cr15, [r7, #64] @ 0x40 │ │ + ldc2l 15, cr15, [r7, #244] @ 0xf4 │ │ ldc2l 9, cr5, [r9, #378] @ 0x17a @ │ │ ldreq r9, [pc, #-1080]! @ 24a5c44 │ │ ldc2l 3, cr13, [r9, #556] @ 0x22c │ │ ldreq r9, [pc, #-1016]! @ 24a5c8c │ │ ldc2l 0, cr15, [r9, #840] @ 0x348 │ │ ldreq r9, [pc, #-964]! @ 24a5cc8 │ │ ldreq r9, [pc, #-96]! @ 24a6030 │ │ @@ -1408469,26 +1408469,26 @@ │ │ str r0, [r1] │ │ mov r0, #0 │ │ ldr r1, [fp, #60] @ 0x3c │ │ str r0, [r1] │ │ b 24a6874 │ │ ldc2l 4, cr5, [r9, #76] @ 0x4c │ │ ldc2l 5, cr9, [r9, #120] @ 0x78 │ │ - ldc2l 12, cr12, [r7, #340] @ 0x154 │ │ + ldc2l 12, cr12, [r7, #520] @ 0x208 │ │ eoreq r3, fp, ip, asr r9 │ │ - ldc2l 1, cr5, [r8, #116] @ 0x74 │ │ + ldc2l 1, cr5, [r8, #296] @ 0x128 │ │ ldc2l 3, cr5, [r9, #668] @ 0x29c │ │ eoreq r3, fp, r8, lsl r9 │ │ ldc2l 13, cr1, [r7, #120] @ 0x78 │ │ - ldc2l 7, cr15, [r7, #440] @ 0x1b8 │ │ - ldc2l 4, cr9, [r8, #700] @ 0x2bc │ │ + ldc2l 7, cr15, [r7, #620] @ 0x26c │ │ + ldc2l 4, cr9, [r8, #880] @ 0x370 │ │ ldc2l 13, cr4, [r9, #252] @ 0xfc │ │ - ldc2l 6, cr15, [r7, #728] @ 0x2d8 │ │ + ldc2l 6, cr15, [r7, #908] @ 0x38c │ │ ldc2l 11, cr1, [r7, #952] @ 0x3b8 @ │ │ - ldc2l 15, cr8, [r8, #748] @ 0x2ec │ │ + ldc2l 15, cr8, [r8, #928] @ 0x3a0 │ │ vcadd.f32 d17, d7, d14, #270 │ │ eoreq r3, fp, r8, asr r3 │ │ ldc2l 13, cr4, [r9, #172] @ 0xac │ │ │ │ 024a69e4 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ @@ -1408599,21 +1408599,21 @@ │ │ ldr r0, [pc, #44] @ 24a6bc0 │ │ mov r1, #8 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ ldr r0, [fp, #-20] @ 0xffffffec │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 12, cr0, [r9, #436] @ 0x1b4 │ │ + ldc2l 12, cr0, [r9, #616] @ 0x268 │ │ ldc2l 12, cr6, [r9, #232] @ 0xe8 │ │ - ldc2l 4, cr12, [r7, #276] @ 0x114 │ │ + ldc2l 4, cr12, [r7, #456] @ 0x1c8 │ │ ldc2l 3, cr2, [sl, #524] @ 0x20c │ │ - ldc2l 3, cr12, [r7, #948] @ 0x3b4 │ │ - ldc2l 9, cr14, [r7, #86] @ 0x56 @ │ │ - ldc2l 10, cr0, [r9, #980] @ 0x3d4 @ │ │ + ldc2l 4, cr12, [r7, #104] @ 0x68 │ │ + ldc2l 9, cr14, [r7, #176] @ 0xb0 @ │ │ + ldc2l 11, cr0, [r9, #136] @ 0x88 @ │ │ │ │ 024a6bc4 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #40 @ 0x28 │ │ mov r6, r0 │ │ mov r0, #0 │ │ @@ -1408721,21 +1408721,21 @@ │ │ ldr r0, [pc, #44] @ 24a6da0 │ │ mov r1, #8 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ ldr r0, [fp, #-20] @ 0xffffffec │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 15, cr8, [r7, #928] @ 0x3a0 │ │ + ldc2l 0, cr9, [r7, #84] @ 0x54 │ │ ldc2l 10, cr6, [r9, #360] @ 0x168 @ │ │ - ldc2l 2, cr12, [r7, #404] @ 0x194 │ │ + ldc2l 2, cr12, [r7, #584] @ 0x248 │ │ ldc2l 1, cr2, [sl, #652] @ 0x28c │ │ - ldc2l 2, cr12, [r7, #52] @ 0x34 │ │ - ldc2l 7, cr14, [r7, #300] @ 0x12c │ │ - ldc2l 14, cr8, [r7, #448] @ 0x1c0 │ │ + ldc2l 2, cr12, [r7, #232] @ 0xe8 │ │ + ldc2l 7, cr14, [r7, #480] @ 0x1e0 │ │ + ldc2l 14, cr8, [r7, #628] @ 0x274 │ │ │ │ 024a6da4 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r5, r1 │ │ mov r4, r0 │ │ @@ -1408975,19 +1408975,19 @@ │ │ ldr r3, [fp, #12] │ │ mov r0, r5 │ │ mov r1, r4 │ │ bl 270e400 │ │ b 24a7004 │ │ ldc2l 1, cr1, [r7, #508] @ 0x1fc │ │ ldc2l 1, cr12, [r9, #260] @ 0x104 │ │ - ldc2l 15, cr11, [r7, #612] @ 0x264 │ │ + ldc2l 15, cr11, [r7, #792] @ 0x318 │ │ ldc2l 7, cr6, [r9, #600] @ 0x258 │ │ ldc2l 1, cr1, [r7, #108] @ 0x6c │ │ - ldc2l 10, cr4, [r7, #260] @ 0x104 @ │ │ - ldc2l 15, cr11, [r7, #212] @ 0xd4 │ │ + ldc2l 10, cr4, [r7, #440] @ 0x1b8 @ │ │ + ldc2l 15, cr11, [r7, #392] @ 0x188 │ │ vcadd.f32 d16, d7, d6, #270 │ │ ldreq pc, [pc, #-3240]! @ 24a64e8 │ │ ldreq pc, [pc, #-3240]! @ 24a64ec │ │ ldreq pc, [pc, #-3236]! @ 24a64f4 │ │ eoreq r2, fp, ip, asr sp │ │ eoreq r2, fp, r4, asr sp │ │ eoreq r2, fp, r0, lsl #24 │ │ @@ -1409218,21 +1409218,21 @@ │ │ ldr r2, [fp, #8] │ │ str r0, [r2] │ │ ldr r3, [fp, #12] │ │ mov r0, r5 │ │ mov r1, r4 │ │ bl 270e400 │ │ b 24a73c0 │ │ - ldc2l 8, cr14, [r7, #596] @ 0x254 │ │ + vcadd.f32 q15, , q1, #270 │ │ ldc2l 13, cr11, [r9, #596] @ 0x254 │ │ - ldc2l 11, cr11, [r7, #948] @ 0x3b4 @ │ │ + ldc2l 12, cr11, [r7, #104] @ 0x68 │ │ ldc2l 3, cr6, [r9, #936] @ 0x3a8 │ │ - vcadd.f32 d30, d7, d17, #270 │ │ - ldc2l 9, cr10, [r7, #448] @ 0x1c0 @ │ │ - ldc2l 11, cr11, [r7, #484] @ 0x1e4 @ │ │ + vcadd.f32 q15, , q7, #270 │ │ + ldc2l 10, cr10, [r7, #52] @ 0x34 @ │ │ + ldc2l 11, cr11, [r7, #664] @ 0x298 @ │ │ ldc2l 4, cr0, [r7, #296] @ 0x128 │ │ ldc2l 11, cr15, [r6, #1004] @ 0x3ec @ │ │ ldreq pc, [pc, #-2328]! @ 24a6c48 │ │ ldreq pc, [pc, #-2324]! @ 24a6c50 │ │ ldrdeq r2, [fp], -r4 @ │ │ eoreq r2, fp, ip, asr #19 │ │ eoreq r2, fp, r0, asr #19 │ │ @@ -1409461,21 +1409461,21 @@ │ │ ldr r2, [fp, #8] │ │ str r0, [r2] │ │ ldr r3, [fp, #12] │ │ mov r0, r5 │ │ mov r1, r4 │ │ bl 270e400 │ │ b 24a7784 │ │ - ldc2l 5, cr8, [r7, #196] @ 0xc4 │ │ + ldc2l 5, cr8, [r7, #376] @ 0x178 │ │ ldc2l 9, cr11, [r9, #386] @ 0x182 @ │ │ - ldc2l 8, cr11, [r7, #100] @ 0x64 │ │ + vcadd.f32 , , q3, #270 │ │ ldc2l 0, cr6, [r9, #88] @ 0x58 │ │ - ldc2l 4, cr8, [r7, #820] @ 0x334 │ │ + ldc2l 4, cr8, [r7, #1000] @ 0x3e8 │ │ ldc2l 7, cr1, [sl, #468] @ 0x1d4 │ │ - ldc2l 7, cr11, [r7, #724] @ 0x2d4 │ │ + ldc2l 7, cr11, [r7, #904] @ 0x388 │ │ ldc2l 0, cr0, [r7, #536] @ 0x218 │ │ vcadd.f32 d31, d6, d19, #270 │ │ ldreq pc, [pc, #-1352]! @ 24a73dc │ │ ldreq pc, [pc, #-1352]! @ 24a73e0 │ │ eoreq r2, fp, r8, lsl #12 │ │ eoreq r2, fp, r4, lsl #12 │ │ mlaeq fp, r8, r4, r2 │ │ @@ -1409696,19 +1409696,19 @@ │ │ ldr r3, [fp, #12] │ │ mov r0, r5 │ │ mov r1, r4 │ │ bl 270e400 │ │ b 24a7b30 │ │ ldc2l 3, cr13, [r9, #672] @ 0x2a0 │ │ ldc2l 6, cr11, [r9, #84] @ 0x54 │ │ - ldc2l 4, cr11, [r7, #436] @ 0x1b4 │ │ + ldc2l 4, cr11, [r7, #616] @ 0x268 │ │ ldc2l 12, cr5, [r9, #424] @ 0x1a8 │ │ ldc2l 3, cr13, [r9, #272] @ 0x110 │ │ - ldc2l 15, cr3, [r7, #84] @ 0x54 │ │ - ldc2l 4, cr11, [r7, #36] @ 0x24 │ │ + ldc2l 15, cr3, [r7, #264] @ 0x108 │ │ + ldc2l 4, cr11, [r7, #216] @ 0xd8 │ │ ldc2l 12, cr15, [r6, #872] @ 0x368 │ │ ldreq pc, [pc, #-420]! @ 24a7b18 │ │ ldreq pc, [pc, #-420]! @ 24a7b1c │ │ ldreq pc, [pc, #-416]! @ 24a7b24 │ │ eoreq r2, fp, r8, asr r2 │ │ eoreq r2, fp, r0, asr r2 │ │ strdeq r2, [fp], -ip @ │ │ @@ -1409934,21 +1409934,21 @@ │ │ ldr r2, [fp, #8] │ │ str r0, [r2] │ │ ldr r3, [fp, #12] │ │ mov r0, r5 │ │ mov r1, r4 │ │ bl 270e400 │ │ b 24a7ee8 │ │ - vcadd.f32 d31, d24, d2, #270 │ │ + vcadd.f32 d31, d24, d31, #270 │ │ ldc2l 2, cr11, [r9, #436] @ 0x1b4 │ │ - ldc2l 0, cr11, [r7, #788] @ 0x314 │ │ + ldc2l 0, cr11, [r7, #968] @ 0x3c8 │ │ vcadd.f32 , , q1, #270 │ │ - vcadd.f32 d31, d8, d14, #270 │ │ - ldc2l 14, cr9, [r7, #736] @ 0x2e0 │ │ - ldc2l 0, cr11, [r7, #324] @ 0x144 │ │ + ldc2l 8, cr15, [r8, #236] @ 0xec │ │ + ldc2l 14, cr9, [r7, #916] @ 0x394 │ │ + ldc2l 0, cr11, [r7, #504] @ 0x1f8 │ │ ldc2l 9, cr15, [r6, #68] @ 0x44 @ │ │ ldc2l 0, cr15, [r6, #828] @ 0x33c │ │ ldreq lr, [pc, #-3604]! @ 24a7264 │ │ ldreq lr, [pc, #-3600]! @ 24a726c │ │ eoreq r1, fp, ip, asr #29 │ │ eoreq r1, fp, r8, asr #29 │ │ eoreq r1, fp, ip, asr sp │ │ @@ -1410180,19 +1410180,19 @@ │ │ ldr r3, [fp, #12] │ │ mov r0, r5 │ │ mov r1, r4 │ │ bl 270e400 │ │ b 24a8290 │ │ ldc2l 6, cr7, [r9, #136] @ 0x88 │ │ ldc2l 14, cr10, [r9, #724] @ 0x2d4 │ │ - ldc2l 13, cr10, [r7, #52] @ 0x34 │ │ + ldc2l 13, cr10, [r7, #232] @ 0xe8 │ │ ldc2l 5, cr5, [r9, #40] @ 0x28 │ │ ldc2l 5, cr7, [r9, #760] @ 0x2f8 │ │ ldc2l 12, cr0, [sl, #420] @ 0x1a4 │ │ - ldc2l 12, cr10, [r7, #676] @ 0x2a4 │ │ + ldc2l 12, cr10, [r7, #856] @ 0x358 │ │ ldc2l 5, cr15, [r6, #488] @ 0x1e8 │ │ ldc2l 13, cr14, [r6, #92] @ 0x5c │ │ ldreq lr, [pc, #-2660]! @ 24a79dc │ │ ldreq lr, [pc, #-2660]! @ 24a79e0 │ │ eoreq r1, fp, r4, lsr #22 │ │ eoreq r1, fp, ip, lsl fp │ │ eoreq r1, fp, ip, lsl #22 │ │ @@ -1410358,28 +1410358,28 @@ │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ ldc2l 12, cr15, [r6, #192] @ 0xc0 │ │ strhteq r1, [fp], -r0 │ │ ldc2l 15, cr14, [r9, #68] @ 0x44 │ │ - ldc2l 9, cr10, [r7, #122] @ 0x7a @ │ │ + ldc2l 9, cr10, [r7, #212] @ 0xd4 @ │ │ mlaeq fp, r0, r6, r1 │ │ ldc2l 8, cr12, [r9, #116] @ 0x74 │ │ mlaeq fp, r4, r7, r1 │ │ eoreq r1, fp, r0, lsl #15 │ │ eoreq r1, fp, ip, ror #14 │ │ ldc2l 11, cr15, [r6, #372] @ 0x174 @ │ │ - ldc2l 9, cr10, [r7, #250] @ 0xfa @ │ │ - ldc2l 1, cr13, [r7, #768] @ 0x300 │ │ + ldc2l 9, cr10, [r7, #340] @ 0x154 @ │ │ + ldc2l 1, cr13, [r7, #948] @ 0x3b4 │ │ ldc2l 10, cr15, [r6, #32] @ │ │ - ldc2l 6, cr3, [r8, #1020] @ 0x3fc │ │ - ldc2l 8, cr10, [r7, #852] @ 0x354 │ │ + ldc2l 7, cr3, [r8, #176] @ 0xb0 │ │ + ldc2l 9, cr10, [r7, #4] @ │ │ ldc2l 0, cr3, [r9, #172] @ 0xac │ │ - vcadd.f32 d26, d23, d9, #270 │ │ + ldc2l 8, cr10, [r7, #728] @ 0x2d8 │ │ │ │ 024a8714 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #16 │ │ mov r4, r1 │ │ ldr r1, [pc, #356] @ 24a8890 │ │ @@ -1410472,22 +1410472,22 @@ │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldc2l 13, cr14, [r9, #980] @ 0x3d4 │ │ ldc2l 1, cr6, [sl] │ │ ldc2l 3, cr2, [sl, #692] @ 0x2b4 │ │ - ldc2l 3, cr7, [r7, #936] @ 0x3a8 │ │ - ldc2l 5, cr12, [r8, #552] @ 0x228 │ │ + ldc2l 4, cr7, [r7, #92] @ 0x5c │ │ + ldc2l 5, cr12, [r8, #732] @ 0x2dc │ │ vcadd.f32 d20, d9, d22, #270 │ │ ldc2l 13, cr8, [r9, #280] @ 0x118 │ │ ldc2l 0, cr6, [sl, #784] @ 0x310 │ │ ldc2l 15, cr6, [r9, #748] @ 0x2ec │ │ - ldc2l 6, cr10, [r7, #724] @ 0x2d4 │ │ - ldc2l 5, cr10, [r8, #964] @ 0x3c4 │ │ + ldc2l 6, cr10, [r7, #904] @ 0x388 │ │ + ldc2l 6, cr10, [r8, #120] @ 0x78 │ │ │ │ 024a88bc : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #12 │ │ mov r4, r1 │ │ ldr r1, [pc, #952] @ 24a8c8c │ │ @@ -1410726,24 +1410726,24 @@ │ │ mov r0, r4 │ │ mov r1, r8 │ │ mov r2, r7 │ │ mov r3, #1 │ │ str r5, [r6] │ │ bl 270d9e0 │ │ b 24a8a40 │ │ - ldc2l 13, cr14, [r8, #780] @ 0x30c │ │ + ldc2l 13, cr14, [r8, #960] @ 0x3c0 │ │ ldc2l 14, cr7, [sl, #168] @ 0xa8 │ │ ldc2l 12, cr10, [r6, #568] @ 0x238 │ │ ldc2l 4, cr1, [r7, #740] @ 0x2e4 │ │ ldc2l 11, cr8, [r9, #808] @ 0x328 @ │ │ - ldc2l 3, cr12, [r8, #792] @ 0x318 │ │ + ldc2l 3, cr12, [r8, #972] @ 0x3cc │ │ ldc2l 13, cr7, [sl, #984] @ 0x3d8 │ │ - ldc2l 2, cr15, [r7, #220] @ 0xdc │ │ - ldc2l 4, cr10, [r7, #996] @ 0x3e4 │ │ - ldc2l 4, cr10, [r8, #212] @ 0xd4 │ │ + ldc2l 2, cr15, [r7, #400] @ 0x190 │ │ + ldc2l 5, cr10, [r7, #152] @ 0x98 │ │ + ldc2l 4, cr10, [r8, #392] @ 0x188 │ │ ldc2l 3, cr14, [r6, #988] @ 0x3dc │ │ ldc2l 2, cr14, [r6, #844] @ 0x34c │ │ ldc2l 1, cr14, [r6, #972] @ 0x3cc │ │ │ │ 024a8cc0 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ @@ -1410963,35 +1410963,35 @@ │ │ ldr r0, [r9, #16] │ │ b 24a902c │ │ mov r0, #0 │ │ str r0, [r6] │ │ str r0, [r4] │ │ b 24a8f00 │ │ vcadd.f32 q15, , , #270 │ │ - ldc2l 6, cr12, [r8, #392] @ 0x188 │ │ + ldc2l 6, cr12, [r8, #572] @ 0x23c │ │ ldc2l 13, cr1, [sl, #196] @ 0xc4 │ │ - ldc2l 13, cr6, [r7, #440] @ 0x1b8 │ │ + ldc2l 13, cr6, [r7, #620] @ 0x26c │ │ ldc2l 3, cr2, [r9, #460] @ 0x1cc │ │ - ldc2l 6, cr12, [r8, #152] @ 0x98 │ │ + ldc2l 6, cr12, [r8, #332] @ 0x14c │ │ ldc2l 1, cr4, [sl, #308] @ 0x134 │ │ - ldc2l 0, cr10, [r7, #228] @ 0xe4 │ │ - ldc2l 15, cr9, [r8, #468] @ 0x1d4 │ │ - ldc2l 15, cr11, [r8, #680] @ 0x2a8 │ │ + ldc2l 0, cr10, [r7, #408] @ 0x198 │ │ + ldc2l 15, cr9, [r8, #648] @ 0x288 │ │ + ldc2l 15, cr11, [r8, #860] @ 0x35c │ │ ldc2l 2, cr4, [r9, #280] @ 0x118 │ │ ldc2l 7, cr8, [r9, #408] @ 0x198 │ │ ldc2l 3, cr15, [r6, #416] @ 0x1a0 │ │ - ldc2l 6, cr12, [r8, #824] @ 0x338 │ │ + ldc2l 6, cr12, [r8, #1004] @ 0x3ec │ │ ldc2l 2, cr15, [r6, #996] @ 0x3e4 │ │ - ldc2l 0, cr10, [r7, #900] @ 0x384 │ │ + ldc2l 1, cr10, [r7, #56] @ 0x38 │ │ ldc2l 2, cr6, [r9, #556] @ 0x22c │ │ - ldc2l 5, cr12, [r8, #376] @ 0x178 │ │ + ldc2l 5, cr12, [r8, #556] @ 0x22c │ │ ldc2l 9, cr5, [sl, #234] @ 0xea @ │ │ - ldc2l 15, cr9, [r7, #452] @ 0x1c4 │ │ + ldc2l 15, cr9, [r7, #632] @ 0x278 │ │ ldc2l 14, cr13, [r6, #604] @ 0x25c │ │ - ldc2l 4, cr12, [r8, #892] @ 0x37c │ │ + ldc2l 5, cr12, [r8, #48] @ 0x30 │ │ │ │ 024a908c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #52 @ 0x34 │ │ mov r7, r1 │ │ ldr r1, [pc, #932] @ 24a9448 │ │ @@ -1411226,36 +1411226,36 @@ │ │ ldr r0, [r8, #20] │ │ b 24a9440 │ │ mov r0, #0 │ │ str r0, [r7] │ │ str r0, [r9] │ │ b 24a9300 │ │ ldc2l 4, cr14, [r9, #500] @ 0x1f4 │ │ - ldc2l 9, cr0, [r8, #388] @ 0x184 @ │ │ + ldc2l 9, cr0, [r8, #478] @ 0x1de @ │ │ ldc2l 9, cr1, [sl, #98] @ 0x62 @ │ │ - ldc2l 9, cr6, [r7, #220] @ 0xdc @ │ │ + ldc2l 9, cr6, [r7, #310] @ 0x136 @ │ │ ldc2l 6, cr13, [r9, #428] @ 0x1ac │ │ - ldc2l 9, cr0, [r8, #268] @ 0x10c @ │ │ + ldc2l 9, cr0, [r8, #358] @ 0x166 @ │ │ ldc2l 13, cr3, [sl, #308] @ 0x134 │ │ - ldc2l 12, cr9, [r7, #228] @ 0xe4 │ │ - ldc2l 11, cr9, [r8, #468] @ 0x1d4 @ │ │ - ldc2l 11, cr11, [r8, #888] @ 0x378 @ │ │ + ldc2l 12, cr9, [r7, #408] @ 0x198 │ │ + ldc2l 11, cr9, [r8, #648] @ 0x288 @ │ │ + ldc2l 12, cr11, [r8, #44] @ 0x2c │ │ ldc2l 14, cr3, [r9, #472] @ 0x1d8 │ │ ldc2l 3, cr8, [r9, #600] @ 0x258 │ │ ldc2l 15, cr1, [r9, #172] @ 0xac │ │ ldc2l 15, cr14, [r6, #512] @ 0x200 │ │ - ldc2l 10, cr0, [r8, #184] @ 0xb8 @ │ │ + ldc2l 10, cr0, [r8, #364] @ 0x16c @ │ │ ldc2l 14, cr14, [r6, #996] @ 0x3e4 │ │ - ldc2l 12, cr9, [r7, #900] @ 0x384 │ │ + ldc2l 13, cr9, [r7, #56] @ 0x38 │ │ ldc2l 14, cr5, [r9, #556] @ 0x22c │ │ - vcadd.f32 d16, d24, d30, #270 │ │ + ldc2l 8, cr0, [r8, #876] @ 0x36c │ │ ldc2l 5, cr5, [sl, #404] @ 0x194 │ │ - ldc2l 11, cr9, [r7, #388] @ 0x184 @ │ │ + ldc2l 11, cr9, [r7, #568] @ 0x238 @ │ │ ldc2l 10, cr13, [r6, #540] @ 0x21c @ │ │ - ldc2l 0, cr12, [r8, #796] @ 0x31c │ │ + ldc2l 0, cr12, [r8, #976] @ 0x3d0 │ │ │ │ 024a94a4 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #32 │ │ mov r5, r1 │ │ ldr r1, [pc, #668] @ 24a9758 │ │ @@ -1411424,30 +1411424,30 @@ │ │ mov r2, r8 │ │ add r1, r5, r0 │ │ sub r3, r3, r0 │ │ mov r0, r9 │ │ bl 270d9e0 │ │ b 24a9678 │ │ ldc2l 0, cr14, [r9, #404] @ 0x194 │ │ - ldc2l 14, cr9, [r8, #24] │ │ + ldc2l 14, cr9, [r8, #204] @ 0xcc │ │ ldc2l 5, cr1, [sl, #740] @ 0x2e4 │ │ - ldc2l 5, cr6, [r7, #984] @ 0x3d8 │ │ + ldc2l 6, cr6, [r7, #140] @ 0x8c │ │ ldc2l 11, cr14, [r6, #1008] @ 0x3f0 @ │ │ - ldc2l 7, cr11, [r8, #888] @ 0x378 │ │ - ldc2l 13, cr9, [r8, #808] @ 0x328 │ │ + vcadd.f32 d27, d8, d11, #270 │ │ + ldc2l 13, cr9, [r8, #988] @ 0x3dc │ │ ldc2l 1, cr6, [r9, #796] @ 0x31c │ │ - vcadd.f32 , , , #270 │ │ - ldc2l 7, cr9, [r8, #1012] @ 0x3f4 │ │ - ldc2l 14, cr9, [r8, #456] @ 0x1c8 │ │ + vcadd.f32 , , q15, #270 │ │ + vcadd.f32 d25, d8, d26, #270 │ │ + ldc2l 14, cr9, [r8, #636] @ 0x27c │ │ ldc2l 1, cr2, [r9, #216] @ 0xd8 │ │ - ldc2l 9, cr9, [r7, #210] @ 0xd2 @ │ │ + ldc2l 9, cr9, [r7, #300] @ 0x12c @ │ │ ldc2l 11, cr5, [r9, #76] @ 0x4c @ │ │ - ldc2l 13, cr9, [r8, #8] │ │ + ldc2l 13, cr9, [r8, #188] @ 0xbc │ │ ldc2l 9, cr9, [r9, #364] @ 0x16c @ │ │ - ldc2l 7, cr9, [r7, #996] @ 0x3e4 │ │ + vcadd.f32 d25, d7, d22, #270 │ │ ldc2l 7, cr13, [r6, #124] @ 0x7c │ │ │ │ 024a97a0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #316 @ 0x13c │ │ str r0, [sp, #4] │ │ @@ -1411571,18 +1411571,18 @@ │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ strhteq r0, [fp], -r8 │ │ eoreq r0, fp, r4, ror #8 │ │ - ldc2l 11, cr11, [r8, #632] @ 0x278 @ │ │ + ldc2l 11, cr11, [r8, #812] @ 0x32c @ │ │ ldc2l 13, cr1, [r9, #564] @ 0x234 │ │ - ldc2l 5, cr9, [r7, #612] @ 0x264 │ │ - ldc2l 15, cr3, [r7, #976] @ 0x3d0 │ │ + ldc2l 5, cr9, [r7, #792] @ 0x318 │ │ + ldc2l 0, cr4, [r7, #132] @ 0x84 │ │ │ │ 024a99b0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #60 @ 0x3c │ │ sub sp, sp, #2048 @ 0x800 │ │ mov r5, r1 │ │ @@ -1412023,31 +1412023,31 @@ │ │ vcmp.f64 d16, d17 │ │ mov r5, #1 │ │ vmrs APSR_nzcv, fpscr │ │ movgt r5, #3 │ │ b 24aa068 │ │ ldc2l 10, cr5, [r9, #160] @ 0xa0 @ │ │ ldc2l 9, cr15, [r8, #246] @ 0xf6 @ │ │ - ldc2l 0, cr9, [r7, #900] @ 0x384 │ │ - ldc2l 14, cr8, [r8, #52] @ 0x34 │ │ + ldc2l 1, cr9, [r7, #56] @ 0x38 │ │ + ldc2l 14, cr8, [r8, #232] @ 0xe8 │ │ ldc2l 8, cr5, [r9, #224] @ 0xe0 │ │ ldc2l 7, cr3, [r9, #160] @ 0xa0 │ │ - ldc2l 14, cr8, [r7, #964] @ 0x3c4 │ │ + ldc2l 15, cr8, [r7, #120] @ 0x78 │ │ ldc2l 9, cr5, [r9, #368] @ 0x170 @ │ │ vcadd.f32 d19, d25, d28, #270 │ │ - ldc2l 0, cr9, [r7, #468] @ 0x1d4 │ │ - ldc2l 15, cr8, [r8, #564] @ 0x234 │ │ + ldc2l 0, cr9, [r7, #648] @ 0x288 │ │ + ldc2l 15, cr8, [r8, #744] @ 0x2e8 │ │ ldc2l 9, cr5, [r9, #120] @ 0x78 @ │ │ ldc2l 10, cr5, [r9, #496] @ 0x1f0 @ │ │ - ldc2l 7, cr11, [r8, #204] @ 0xcc │ │ - ldc2l 1, cr9, [r7, #212] @ 0xd4 │ │ + ldc2l 7, cr11, [r8, #384] @ 0x180 │ │ + ldc2l 1, cr9, [r7, #392] @ 0x188 │ │ ldc2l 13, cr0, [sl, #976] @ 0x3d0 │ │ ldc2l 10, cr5, [r9, #880] @ 0x370 @ │ │ ldc2l 10, cr6, [sl, #556] @ 0x22c @ │ │ - ldc2l 1, cr9, [r7, #596] @ 0x254 │ │ + ldc2l 1, cr9, [r7, #776] @ 0x308 │ │ ldc2l 3, cr5, [r9, #316] @ 0x13c │ │ │ │ 024aa0f0 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ ldr r4, [pc, #268] @ 24aa210 │ │ @@ -1412119,19 +1412119,19 @@ │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ ldreq ip, [pc, #-2720]! @ 24a9778 │ │ eoreq pc, sl, r4, lsr #26 │ │ eoreq pc, sl, ip, lsr fp @ │ │ ldc2l 7, cr4, [sl, #488] @ 0x1e8 │ │ - ldc2l 3, cr11, [r8, #288] @ 0x120 │ │ - ldc2l 13, cr8, [r7, #132] @ 0x84 │ │ - ldc2l 3, cr11, [r8, #200] @ 0xc8 │ │ - ldc2l 8, cr1, [r7, #624] @ 0x270 │ │ - ldc2l 6, cr5, [r8, #888] @ 0x378 │ │ + ldc2l 3, cr11, [r8, #468] @ 0x1d4 │ │ + ldc2l 13, cr8, [r7, #312] @ 0x138 │ │ + ldc2l 3, cr11, [r8, #380] @ 0x17c │ │ + vcadd.f32 , , , #270 │ │ + ldc2l 7, cr5, [r8, #44] @ 0x2c │ │ stc2l 1, cr15, [r2, #64]! @ 0x40 │ │ │ │ 024aa238 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #52 @ 0x34 │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ @@ -1412286,21 +1412286,21 @@ │ │ bl 270da10 │ │ mov r0, r6 │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - ldc2l 4, cr3, [r8, #152] @ 0x98 │ │ - ldc2l 2, cr13, [r8, #908] @ 0x38c │ │ - ldc2l 11, cr8, [r7, #164] @ 0xa4 @ │ │ + ldc2l 4, cr3, [r8, #332] @ 0x14c │ │ + ldc2l 3, cr13, [r8, #64] @ 0x40 │ │ + ldc2l 11, cr8, [r7, #344] @ 0x158 @ │ │ ldc2l 12, cr4, [r9, #844] @ 0x34c │ │ - ldc2l 3, cr3, [r8, #664] @ 0x298 │ │ + ldc2l 3, cr3, [r8, #844] @ 0x34c │ │ ldc2l 10, cr14, [r9, #560] @ 0x230 @ │ │ - ldc2l 10, cr8, [r7, #676] @ 0x2a4 @ │ │ + ldc2l 10, cr8, [r7, #856] @ 0x358 @ │ │ ldc2l 12, cr4, [r9, #332] @ 0x14c │ │ │ │ 024aa4cc : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #8 │ │ ldr r4, [r1] │ │ @@ -1412338,16 +1412338,16 @@ │ │ mov r0, r4 │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #8 │ │ pop {r4, sl, fp, pc} │ │ ldc2l 4, cr4, [sl, #124] @ 0x7c │ │ - ldc2l 4, cr3, [r7, #356] @ 0x164 │ │ - ldc2l 9, cr8, [r7, #386] @ 0x182 @ │ │ + ldc2l 4, cr3, [r7, #536] @ 0x218 │ │ + ldc2l 9, cr8, [r7, #476] @ 0x1dc @ │ │ ldc2l 2, cr13, [r6, #664] @ 0x298 │ │ │ │ 024aa580 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #72 @ 0x48 │ │ ldr r5, [fp, #24] │ │ @@ -1412491,22 +1412491,22 @@ │ │ mov r1, r5 │ │ mov r2, #1 │ │ bl 270daf0 │ │ ldr r0, [pc, #36] @ 24aa7ec │ │ mov r1, #14 │ │ add r0, pc, r0 │ │ b 24aa6b0 │ │ - ldc2l 7, cr7, [r7, #328] @ 0x148 │ │ + ldc2l 7, cr7, [r7, #508] @ 0x1fc │ │ ldc2l 10, cr8, [r9, #632] @ 0x278 @ │ │ - vcadd.f32 d24, d23, d25, #270 │ │ - ldc2l 0, cr7, [r7, #264] @ 0x108 │ │ - ldc2l 6, cr7, [r7, #216] @ 0xd8 │ │ + ldc2l 8, cr8, [r7, #856] @ 0x358 │ │ + ldc2l 0, cr7, [r7, #444] @ 0x1bc │ │ + ldc2l 6, cr7, [r7, #396] @ 0x18c │ │ ldc2l 13, cr6, [r9, #584] @ 0x248 │ │ - ldc2l 7, cr8, [r7, #580] @ 0x244 │ │ - ldc2l 4, cr13, [r7, #12] │ │ + ldc2l 7, cr8, [r7, #760] @ 0x2f8 │ │ + ldc2l 4, cr13, [r7, #192] @ 0xc0 │ │ │ │ 024aa7f0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #84 @ 0x54 │ │ mov r4, r0 │ │ ldr r0, [r2, #32] │ │ @@ -1412776,25 +1412776,25 @@ │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #60] @ 24aac6c │ │ add r0, pc, r0 │ │ b 24aaadc │ │ ldc2l 5, cr2, [sl, #860] @ 0x35c │ │ ldc2l 15, cr10, [r6, #48] @ 0x30 │ │ - ldc2l 4, cr8, [r7, #532] @ 0x214 │ │ - ldc2l 3, cr8, [r8, #580] @ 0x244 │ │ + ldc2l 4, cr8, [r7, #712] @ 0x2c8 │ │ + ldc2l 3, cr8, [r8, #760] @ 0x2f8 │ │ eoreq pc, sl, ip, asr #11 │ │ eoreq pc, sl, r8, lsl r5 @ │ │ ldc2l 4, cr12, [r6, #204] @ 0xcc │ │ ldc2l 4, cr2, [sl, #956] @ 0x3bc │ │ ldc2l 12, cr2, [r9, #84] @ 0x54 │ │ - ldc2l 3, cr8, [r7, #596] @ 0x254 │ │ - ldc2l 11, cr6, [r8, #288] @ 0x120 @ │ │ + ldc2l 3, cr8, [r7, #776] @ 0x308 │ │ + ldc2l 11, cr6, [r8, #468] @ 0x1d4 @ │ │ ldc2l 12, cr2, [r9, #4] │ │ - ldc2l 3, cr8, [r7, #164] @ 0xa4 │ │ + ldc2l 3, cr8, [r7, #344] @ 0x158 │ │ ldc2l 4, cr4, [r9, #764] @ 0x2fc │ │ ldc2l 3, cr2, [sl, #1020] @ 0x3fc │ │ │ │ 024aac70 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #24 │ │ @@ -1412894,18 +1412894,18 @@ │ │ mov r0, r4 │ │ bl 270ce90 │ │ ldr r0, [pc, #20] @ 24aae0c │ │ mov r1, #17 │ │ add r0, pc, r0 │ │ b 24aad40 │ │ ldc2l 4, cr13, [r6, #36] @ 0x24 │ │ - vcadd.f32 q8, , q11, #270 │ │ + ldc2l 9, cr0, [r7, #38] @ 0x26 @ │ │ ldc2l 3, cr13, [r6, #292] @ 0x124 │ │ ldc2l 3, cr4, [r9, #152] @ 0x98 │ │ - ldc2l 0, cr7, [r7, #472] @ 0x1d8 │ │ + ldc2l 0, cr7, [r7, #652] @ 0x28c │ │ │ │ 024aae14 : │ │ push {fp, lr} │ │ mov fp, sp │ │ mov r3, r2 │ │ mov r2, r1 │ │ mov r1, r0 │ │ @@ -1412951,16 +1412951,16 @@ │ │ add r0, r1, r0, lsl #7 │ │ str r0, [r4] │ │ ldrb r1, [r5, #4] │ │ add r0, r1, r0, lsl #7 │ │ str r0, [r4] │ │ mov r0, #0 │ │ pop {r4, r5, fp, pc} │ │ - ldc2l 15, cr6, [r7, #152] @ 0x98 │ │ - ldc2l 7, cr0, [r7, #696] @ 0x2b8 │ │ + ldc2l 15, cr6, [r7, #332] @ 0x14c │ │ + ldc2l 7, cr0, [r7, #876] @ 0x36c │ │ │ │ 024aaee0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #28 │ │ sub r0, r0, #1 │ │ cmp r0, #12 │ │ @@ -1413982,15 +1413982,15 @@ │ │ ldr r0, [pc, #2252] @ 24ac7a4 │ │ mov r1, #18 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #2240] @ 24ac7a8 │ │ add r0, pc, r0 │ │ b 24ac59c │ │ - ldc2l 9, cr4, [r8, #40] @ 0x28 @ │ │ + ldc2l 9, cr4, [r8, #130] @ 0x82 @ │ │ ldc2l 0, cr0, [r9, #164] @ 0xa4 │ │ ldr r1, [pc, #2040] @ 24ac6f4 │ │ mov r0, r9 │ │ ldr r2, [pc, #2036] @ 24ac6f8 │ │ add r1, pc, r1 │ │ add r2, pc, r2 │ │ bl 270d460 │ │ @@ -1414015,15 +1414015,15 @@ │ │ ldr r0, [pc, r0] │ │ add r0, r0, #1 │ │ str r0, [r8] │ │ ldr r0, [pc, #1956] @ 24ac70c │ │ ldr r0, [pc, r0] │ │ lsl r1, r0, #7 │ │ b 24ac154 │ │ - vcadd.f32 q10, q12, q12, #270 │ │ + ldc2l 9, cr4, [r8, #42] @ 0x2a @ │ │ eoreq lr, sl, ip, asr #29 │ │ ldreq ip, [pc, #-2100]! @ 24ab74c │ │ ldreq ip, [pc, #-2072]! @ 24ab76c │ │ ldreq fp, [pc, #-2996]! @ 24ab3d4 │ │ ldreq fp, [pc, #-2984]! @ 24ab3e4 │ │ ldreq fp, [pc, #-2948]! @ 24ab40c │ │ eoreq lr, sl, r4, lsr #28 │ │ @@ -1414098,15 +1414098,15 @@ │ │ mov r2, #1 │ │ add r0, pc, r0 │ │ bl 270db00 │ │ ldr r0, [pc, #1948] @ 24ac850 │ │ mov r1, #18 │ │ add r0, pc, r0 │ │ b 24ac324 │ │ - ldc2l 3, cr8, [r8, #60] @ 0x3c │ │ + ldc2l 3, cr8, [r8, #240] @ 0xf0 │ │ strhteq lr, [sl], -ip │ │ ldc2l 14, cr15, [r8, #580] @ 0x244 │ │ mlaeq sl, r0, sp, lr │ │ ldreq ip, [pc, #-1784]! @ 24ab9dc │ │ ldreq ip, [pc, #-1756]! @ 24ab9fc │ │ ldreq fp, [pc, #-2672]! @ 24ab66c │ │ ldr r1, [pc, #1512] @ 24ac6c8 │ │ @@ -1414140,15 +1414140,15 @@ │ │ mov r0, #256 @ 0x100 │ │ ldr r1, [pc, r1] │ │ add r1, r0, r1, lsl #8 │ │ ldr r0, [pc, #1460] @ 24ac710 │ │ str r1, [sl] │ │ add r0, pc, r0 │ │ b 24ac59c │ │ - ldc2l 10, cr14, [r7, #636] @ 0x27c @ │ │ + ldc2l 10, cr14, [r7, #816] @ 0x330 @ │ │ ldc2l 13, cr15, [r8, #964] @ 0x3c4 │ │ ldr r1, [pc, #1804] @ 24ac880 │ │ movw r5, #64513 @ 0xfc01 │ │ ldr r0, [r8] │ │ movt r5, #65535 @ 0xffff │ │ ldr r2, [pc, #1792] @ 24ac884 │ │ add r1, pc, r1 │ │ @@ -1414161,15 +1414161,15 @@ │ │ add r2, sp, #24 │ │ str r0, [sp, #24] │ │ mov r0, r9 │ │ str r5, [r1] │ │ str r6, [sp, #8] │ │ bl 270d670 │ │ b 24ac5a4 │ │ - ldc2l 10, cr14, [r7, #460] @ 0x1cc @ │ │ + ldc2l 10, cr14, [r7, #640] @ 0x280 @ │ │ ldc2l 6, cr14, [r8] │ │ ldc2l 13, cr15, [r8, #708] @ 0x2c4 │ │ ldc2l 5, cr14, [r8, #848] @ 0x350 │ │ ldr r0, [pc, #1300] @ 24ac6e4 │ │ mov r1, #40 @ 0x28 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ @@ -1414212,15 +1414212,15 @@ │ │ mov r0, r4 │ │ bl 270db00 │ │ ldr r1, [pc, #1408] @ 24ac7f8 │ │ add r1, pc, r1 │ │ b 24ac30c │ │ ldc2l 12, cr13, [r9, #524] @ 0x20c │ │ ldc2l 12, cr14, [r6, #24] │ │ - ldc2l 12, cr7, [r7, #340] @ 0x154 │ │ + ldc2l 12, cr7, [r7, #520] @ 0x208 │ │ ldreq fp, [pc, #-2344]! @ 24ab968 │ │ ldr r0, [pc, #1420] @ 24ac820 │ │ mov r1, #74 @ 0x4a │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #1408] @ 24ac824 │ │ mov r1, r8 │ │ @@ -1414333,16 +1414333,16 @@ │ │ b 24ac4fc │ │ eoreq lr, sl, r8, asr #20 │ │ ldreq ip, [pc, #-944]! @ 24ac0ac │ │ ldreq ip, [pc, #-916]! @ 24ac0cc │ │ ldreq fp, [pc, #-1836]! @ 24abd38 │ │ ldc2l 4, cr3, [sl, #480] @ 0x1e0 │ │ ldc2l 4, cr3, [sl, #468] @ 0x1d4 │ │ - ldc2l 4, cr2, [r7, #948] @ 0x3b4 │ │ - ldc2l 7, cr8, [r7, #468] @ 0x1d4 │ │ + ldc2l 5, cr2, [r7, #104] @ 0x68 │ │ + ldc2l 7, cr8, [r7, #648] @ 0x288 │ │ ldr r2, [pc, #820] @ 24ac7ac │ │ mov r3, #1024 @ 0x400 │ │ ldr r1, [pc, #816] @ 24ac7b0 │ │ ldr r0, [pc, #816] @ 24ac7b4 │ │ add r2, pc, r2 │ │ add r1, pc, r1 │ │ add r0, pc, r0 │ │ @@ -1414453,21 +1414453,21 @@ │ │ ldc2l 0, cr14, [r8, #288] @ 0x120 │ │ ldreq ip, [pc, #-76]! @ 24ac5ec │ │ ldreq ip, [pc, #-76]! @ 24ac5f0 │ │ ldreq ip, [pc, #-76]! @ 24ac5f4 │ │ ldreq ip, [pc, #-56]! @ 24ac60c │ │ ldreq ip, [pc, #-48]! @ 24ac618 │ │ ldreq fp, [pc, #-3384]! @ 24ab914 │ │ - ldc2l 15, cr11, [r8, #48] @ 0x30 │ │ - ldc2l 7, cr7, [r7, #100] @ 0x64 │ │ + ldc2l 15, cr11, [r8, #228] @ 0xe4 │ │ + ldc2l 7, cr7, [r7, #280] @ 0x118 │ │ ldreq fp, [pc, #-4076]! @ 24ab66c │ │ ldreq fp, [pc, #-4060]! @ 24ab680 │ │ ldreq fp, [pc, #-4044]! @ 24ab694 │ │ - ldc2l 3, cr10, [r7, #312] @ 0x138 │ │ - ldc2l 0, cr4, [r8, #160] @ 0xa0 │ │ + ldc2l 3, cr10, [r7, #492] @ 0x1ec │ │ + ldc2l 0, cr4, [r8, #340] @ 0x154 │ │ ldc2l 3, cr11, [r6, #444] @ 0x1bc │ │ eoreq lr, sl, r4, lsr #7 │ │ ldreq fp, [pc, #-252]! @ 24ac578 │ │ ldreq fp, [pc, #-3368]! @ 24ab950 │ │ eoreq lr, sl, r4, lsl #7 │ │ ldreq fp, [pc, #-1248]! @ 24ac1a0 │ │ ldreq fp, [pc, #-3344]! @ 24ab974 │ │ @@ -1414476,15 +1414476,15 @@ │ │ eoreq lr, sl, r4, lsr r3 │ │ eoreq lr, sl, r0, lsr #6 │ │ eoreq lr, sl, r0, lsr #6 │ │ eoreq lr, sl, ip, lsl #6 │ │ strdeq lr, [sl], -r8 @ │ │ eoreq lr, sl, r4, ror #5 │ │ strhteq lr, [sl], -ip │ │ - ldc2l 12, cr3, [r8, #448] @ 0x1c0 │ │ + ldc2l 12, cr3, [r8, #628] @ 0x274 │ │ eoreq lr, sl, ip, lsl #12 │ │ eoreq lr, sl, ip, lsl r6 │ │ ldreq fp, [pc, #-868]! @ 24ac354 │ │ eoreq lr, sl, ip, lsl #12 │ │ ldreq fp, [pc, #-3956]! @ 24ab74c │ │ ldreq fp, [pc, #-3924]! @ 24ab770 │ │ ldreq fp, [pc, #-3900]! @ 24ab78c │ │ @@ -1414492,16 +1414492,16 @@ │ │ eoreq sp, sl, r8, lsr #27 │ │ ldreq fp, [pc, #-772]! @ 24ac3d0 │ │ strhteq sp, [sl], -r8 │ │ ldreq fp, [pc, #-1824]! @ 24abfbc │ │ ldreq fp, [pc, #-1792]! @ 24abfe0 │ │ ldreq fp, [pc, #-1768]! @ 24abffc │ │ ldreq fp, [pc, #-1748]! @ 24ac014 │ │ - ldc2l 3, cr9, [r8, #92] @ 0x5c │ │ - ldc2l 13, cr6, [r7, #116] @ 0x74 │ │ + ldc2l 3, cr9, [r8, #272] @ 0x110 │ │ + ldc2l 13, cr6, [r7, #296] @ 0x128 │ │ ldc2l 6, cr11, [r6, #8] │ │ ldc2l 3, cr5, [r9, #392] @ 0x188 │ │ eoreq sp, sl, r8, lsl #31 │ │ ldreq fp, [pc, #-228]! @ 24ac61c │ │ mlaeq sl, r8, pc, sp @ │ │ ldreq fp, [pc, #-2304]! @ 24abe08 │ │ ldreq fp, [pc, #-2272]! @ 24abe2c │ │ @@ -1414538,92 +1414538,92 @@ │ │ strhteq sp, [sl], -r0 │ │ ldreq fp, [pc, #-12]! @ 24ac780 │ │ eoreq sp, sl, r0, asr #21 │ │ ldreq fp, [pc, #-1064]! @ 24ac36c │ │ ldreq fp, [pc, #-1032]! @ 24ac390 │ │ ldreq fp, [pc, #-1008]! @ 24ac3ac │ │ ldreq fp, [pc, #-988]! @ 24ac3c4 │ │ - ldc2l 6, cr9, [r8, #204] @ 0xcc │ │ - ldc2l 0, cr7, [r7, #228] @ 0xe4 │ │ + ldc2l 6, cr9, [r8, #384] @ 0x180 │ │ + ldc2l 0, cr7, [r7, #408] @ 0x198 │ │ ldc2l 9, cr11, [r6, #60] @ 0x3c @ │ │ - ldc2l 13, cr13, [r7, #300] @ 0x12c │ │ + ldc2l 13, cr13, [r7, #480] @ 0x1e0 │ │ eoreq sp, sl, r4, lsl #20 │ │ eoreq sp, sl, r4, lsl sl │ │ ldreq sl, [pc, #-1884]! @ 24ac060 │ │ eoreq sp, sl, r4, lsl #20 │ │ ldreq fp, [pc, #-876]! @ 24ac458 │ │ ldreq fp, [pc, #-844]! @ 24ac47c │ │ ldreq fp, [pc, #-820]! @ 24ac498 │ │ ldreq fp, [pc, #-804]! @ 24ac4ac │ │ - ldc2l 7, cr13, [r7, #172] @ 0xac │ │ - ldc2l 9, cr13, [r7, #168] @ 0xa8 @ │ │ - ldc2l 12, cr6, [r7, #36] @ 0x24 │ │ + ldc2l 7, cr13, [r7, #352] @ 0x160 │ │ + ldc2l 9, cr13, [r7, #258] @ 0x102 @ │ │ + ldc2l 12, cr6, [r7, #216] @ 0xd8 │ │ ldreq fp, [pc, #-1296]! @ 24ac2d0 │ │ - ldc2l 11, cr6, [r8, #260] @ 0x104 @ │ │ + ldc2l 11, cr6, [r8, #440] @ 0x1b8 @ │ │ ldc2l 4, cr13, [r8, #656] @ 0x290 │ │ eoreq lr, sl, r8, asr #1 │ │ ldreq fp, [pc, #-2608]! @ 24abdc0 │ │ ldreq fp, [pc, #-2580]! @ 24abde0 │ │ - ldc2l 10, cr15, [r7, #968] @ 0x3c8 @ │ │ - ldc2l 12, cr6, [r7, #628] @ 0x274 │ │ + ldc2l 11, cr15, [r7, #124] @ 0x7c @ │ │ + ldc2l 12, cr6, [r7, #808] @ 0x328 │ │ ldreq fp, [pc, #-1448]! @ 24ac258 │ │ eoreq lr, sl, r0, lsr #1 │ │ ldreq sl, [pc, #-3516]! @ 24aba4c │ │ eoreq lr, sl, r0, lsl #1 │ │ ldreq fp, [pc, #-2500]! @ 24abe4c │ │ ldreq sl, [pc, #-3424]! @ 24abab4 │ │ ldreq fp, [pc, #-2408]! @ 24abeb0 │ │ eoreq sp, sl, r8, lsl pc │ │ ldreq fp, [pc, #-2176]! @ 24abfa0 │ │ ldreq fp, [pc, #-2148]! @ 24abfc0 │ │ - ldc2l 4, cr11, [r8, #524] @ 0x20c │ │ - ldc2l 12, cr6, [r7, #356] @ 0x164 │ │ + ldc2l 4, cr11, [r8, #704] @ 0x2c0 │ │ + ldc2l 12, cr6, [r7, #536] @ 0x218 │ │ ldreq fp, [pc, #-1384]! @ 24ac2c8 │ │ strdeq sp, [sl], -r4 @ │ │ ldreq fp, [pc, #-1040]! @ 24ac428 │ │ ldrdeq sp, [sl], -r4 @ │ │ ldreq fp, [pc, #-2068]! @ 24ac02c │ │ ldreq sl, [pc, #-2996]! @ 24abc90 │ │ ldreq fp, [pc, #-1988]! @ 24ac084 │ │ ldc2l 7, cr13, [r8, #384] @ 0x180 │ │ - ldc2l 4, cr9, [r8, #348] @ 0x15c │ │ - ldc2l 14, cr6, [r7, #372] @ 0x174 │ │ + ldc2l 4, cr9, [r8, #528] @ 0x210 │ │ + ldc2l 14, cr6, [r7, #552] @ 0x228 │ │ ldc2l 7, cr11, [r6, #264] @ 0x108 │ │ - ldc2l 15, cr1, [r7, #536] @ 0x218 │ │ - ldc2l 4, cr7, [r7, #804] @ 0x324 │ │ + ldc2l 15, cr1, [r7, #716] @ 0x2cc │ │ + ldc2l 4, cr7, [r7, #984] @ 0x3d8 │ │ ldreq fp, [pc, #-3536]! @ 24aba94 │ │ - ldc2l 3, cr7, [r8, #740] @ 0x2e4 │ │ + ldc2l 3, cr7, [r8, #920] @ 0x398 │ │ ldc2l 13, cr3, [r9, #740] @ 0x2e4 │ │ - ldc2l 4, cr7, [r7, #516] @ 0x204 │ │ + ldc2l 4, cr7, [r7, #696] @ 0x2b8 │ │ ldreq fp, [pc, #-3468]! @ 24abae8 │ │ ldc2l 15, cr9, [r6, #872] @ 0x368 │ │ - ldc2l 5, cr7, [r7, #68] @ 0x44 │ │ + ldc2l 5, cr7, [r7, #248] @ 0xf8 │ │ ldreq fp, [pc, #-3616]! @ 24aba60 │ │ ldc2l 4, cr13, [r9, #1004] @ 0x3ec │ │ ldreq sl, [pc, #-2640]! @ 24abe38 │ │ eoreq sp, sl, r0, lsl sp │ │ eoreq sp, sl, ip, ror #25 │ │ - ldc2l 12, cr5, [r8, #756] @ 0x2f4 │ │ + ldc2l 12, cr5, [r8, #936] @ 0x3a8 │ │ ldc2l 11, cr5, [r9, #668] @ 0x29c @ │ │ ldc2l 7, cr12, [r6, #752] @ 0x2f0 │ │ - ldc2l 11, cr9, [r8, #332] @ 0x14c @ │ │ - ldc2l 5, cr7, [r7, #356] @ 0x164 │ │ + ldc2l 11, cr9, [r8, #512] @ 0x200 @ │ │ + ldc2l 5, cr7, [r7, #536] @ 0x218 │ │ ldc2l 14, cr11, [r6, #248] @ 0xf8 │ │ - ldc2l 0, cr2, [r7, #568] @ 0x238 │ │ + ldc2l 0, cr2, [r7, #748] @ 0x2ec │ │ ldc2l 15, cr14, [r9, #844] @ 0x34c │ │ eoreq lr, sl, ip, lsl #5 │ │ ldc2l 4, cr7, [r6, #364] @ 0x16c │ │ eoreq sp, sl, r4, lsl #25 │ │ ldc2l 0, cr11, [r9, #16] │ │ eoreq sp, sl, r8, lsl #19 │ │ ldc2l 10, cr0, [sl, #800] @ 0x320 @ │ │ eoreq sp, sl, ip, asr #18 │ │ - ldc2l 6, cr13, [r7, #764] @ 0x2fc │ │ - ldc2l 9, cr6, [r7, #74] @ 0x4a @ │ │ - ldc2l 14, cr8, [r7, #588] @ 0x24c │ │ + ldc2l 6, cr13, [r7, #944] @ 0x3b0 │ │ + ldc2l 9, cr6, [r7, #164] @ 0xa4 @ │ │ + ldc2l 14, cr8, [r7, #768] @ 0x300 │ │ ldc2l 1, cr15, [r8, #476] @ 0x1dc │ │ │ │ 024ac8d8 : │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r0, [pc, #16] @ 24ac8f8 │ │ mov r1, #17 │ │ @@ -1414907,16 +1414907,16 @@ │ │ mov r0, r4 │ │ mov r1, #8 │ │ bl 270ceb0 │ │ pop {r4, r5, fp, lr} │ │ mov r0, #0 │ │ bx lr │ │ ldc2l 4, cr11, [r6, #576] @ 0x240 │ │ - vcadd.f32 d24, d8, d31, #270 │ │ - ldc2l 2, cr6, [r7, #212] @ 0xd4 │ │ + ldc2l 8, cr8, [r8, #368] @ 0x170 │ │ + ldc2l 2, cr6, [r7, #392] @ 0x188 │ │ ldc2l 11, cr10, [r6, #104] @ 0x68 @ │ │ │ │ 024acd0c : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #40 @ 0x28 │ │ mov ip, r1 │ │ @@ -1415090,21 +1415090,21 @@ │ │ add r0, sp, #12 │ │ str r0, [sp, #8] │ │ ldr r1, [pc, #32] @ 24acfd8 │ │ mov r0, r6 │ │ add r1, pc, r1 │ │ bl 270d440 │ │ b 24acf20 │ │ - ldc2l 9, cr10, [r8, #244] @ 0xf4 @ │ │ + ldc2l 9, cr10, [r8, #334] @ 0x14e @ │ │ vcadd.f32 , , q10, #270 │ │ - ldc2l 0, cr6, [r7, #804] @ 0x324 │ │ + ldc2l 0, cr6, [r7, #984] @ 0x3d8 │ │ ldc2l 7, cr1, [sl, #24] │ │ eoreq sp, sl, r8, lsl r0 │ │ eoreq ip, sl, r8, lsl pc │ │ - vcadd.f32 q13, q12, q11, #270 │ │ + ldc2l 9, cr10, [r8, #38] @ 0x26 @ │ │ │ │ 024acfe0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #84 @ 0x54 │ │ mov r8, r3 │ │ mov r7, r2 │ │ @@ -1415442,25 +1415442,25 @@ │ │ ldr r0, [sp, #40] @ 0x28 │ │ add r5, r0, r5 │ │ cmp r5, r4 │ │ ble 24ad400 │ │ b 24ad09c │ │ ldc2l 6, cr6, [r6, #480] @ 0x1e0 │ │ ldc2l 6, cr13, [r9, #240] @ 0xf0 │ │ - ldc2l 14, cr5, [r7, #644] @ 0x284 │ │ + ldc2l 14, cr5, [r7, #824] @ 0x338 │ │ ldc2l 4, cr1, [sl, #888] @ 0x378 │ │ ldc2l 0, cr6, [r9, #260] @ 0x104 │ │ - ldc2l 13, cr5, [r7, #948] @ 0x3b4 │ │ + ldc2l 14, cr5, [r7, #104] @ 0x68 │ │ strhteq ip, [sl], -ip │ │ - ldc2l 12, cr5, [r8, #548] @ 0x224 │ │ - vcadd.f32 q8, , , #270 │ │ - ldc2l 13, cr5, [r7, #452] @ 0x1c4 │ │ + ldc2l 12, cr5, [r8, #728] @ 0x2d8 │ │ + ldc2l 8, cr0, [r7, #576] @ 0x240 │ │ + ldc2l 13, cr5, [r7, #632] @ 0x278 │ │ eoreq ip, sl, r0, asr #26 │ │ ldc2l 7, cr8, [r6, #884] @ 0x374 │ │ - ldc2l 12, cr5, [r7, #964] @ 0x3c4 │ │ + ldc2l 13, cr5, [r7, #120] @ 0x78 │ │ ldc2l 15, cr5, [r9, #256] @ 0x100 │ │ eoreq ip, sl, r0, ror ip │ │ eoreq ip, sl, r4, ror #21 │ │ ldc2l 5, cr6, [r6, #912] @ 0x390 │ │ │ │ 024ad578 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ @@ -1415679,18 +1415679,18 @@ │ │ add r2, sp, #36 @ 0x24 │ │ ldr r0, [sp, #20] │ │ add r1, pc, r1 │ │ bl 270d490 │ │ b 24ad634 │ │ ldc2l 11, cr5, [r9, #900] @ 0x384 @ │ │ ldc2l 14, cr3, [r9, #728] @ 0x2d8 │ │ - ldc2l 9, cr5, [r7, #18] @ │ │ + ldc2l 9, cr5, [r7, #108] @ 0x6c @ │ │ ldc2l 9, cr10, [r6, #264] @ 0x108 @ │ │ - vcadd.f32 , , , #270 │ │ - ldc2l 5, cr12, [r7, #836] @ 0x344 │ │ + vcadd.f32 d21, d23, d14, #270 │ │ + ldc2l 5, cr12, [r7, #1016] @ 0x3f8 │ │ strhteq ip, [sl], -ip │ │ strhteq ip, [sl], -r0 │ │ eoreq ip, sl, r8, lsr r6 │ │ eoreq ip, sl, r4, ror #12 │ │ eoreq ip, sl, r4, lsl #20 │ │ ldc2l 11, cr5, [r9, #324] @ 0x144 @ │ │ │ │ @@ -1415898,19 +1415898,19 @@ │ │ ldr r0, [pc, #36] @ 24adc44 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 1, cr2, [r7, #636] @ 0x27c │ │ + ldc2l 1, cr2, [r7, #816] @ 0x330 │ │ strdeq ip, [sl], -ip @ │ │ ldreq r9, [pc, #-3336]! @ 24acf3c │ │ eoreq ip, sl, ip, asr #13 │ │ - ldc2l 15, cr1, [r7, #940] @ 0x3ac │ │ + ldc2l 0, cr2, [r7, #96] @ 0x60 │ │ │ │ 024adc48 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #124 @ 0x7c │ │ ldr r4, [r2, #32] │ │ mov r9, r0 │ │ @@ -1416365,32 +1416365,32 @@ │ │ bl 270db90 │ │ clz r0, r0 │ │ lsr r0, r0, #5 │ │ str r0, [sl] │ │ b 24adde4 │ │ ldc2l 3, cr10, [r6, #740] @ 0x2e4 │ │ ldc2l 12, cr7, [r6, #532] @ 0x214 │ │ - ldc2l 1, cr5, [r7, #340] @ 0x154 │ │ - ldc2l 0, cr5, [r8, #580] @ 0x244 │ │ + ldc2l 1, cr5, [r7, #520] @ 0x208 │ │ + ldc2l 0, cr5, [r8, #760] @ 0x2f8 │ │ ldc2l 4, cr10, [r6, #388] @ 0x184 │ │ ldc2l 1, cr7, [r9, #264] @ 0x108 │ │ - ldc2l 1, cr5, [r7, #1012] @ 0x3f4 │ │ + ldc2l 2, cr5, [r7, #168] @ 0xa8 │ │ ldc2l 10, cr15, [r8, #632] @ 0x278 @ │ │ eoreq ip, sl, r8, lsr #5 │ │ eoreq ip, sl, ip, lsr #4 │ │ eoreq ip, sl, ip, ror #1 │ │ eoreq ip, sl, r0 │ │ ldc2l 10, cr8, [r6, #1004] @ 0x3ec @ │ │ ldc2l 2, cr10, [r6, #292] @ 0x124 │ │ vcadd.f32 , q4, , #270 │ │ - ldc2l 15, cr4, [r7, #916] @ 0x394 │ │ - ldc2l 7, cr3, [r8, #608] @ 0x260 │ │ + ldc2l 0, cr5, [r7, #72] @ 0x48 │ │ + ldc2l 7, cr3, [r8, #788] @ 0x314 │ │ ldc2l 1, cr10, [r6, #612] @ 0x264 │ │ vcadd.f32 d31, d8, d13, #270 │ │ - ldc2l 15, cr4, [r7, #212] @ 0xd4 │ │ + ldc2l 15, cr4, [r7, #392] @ 0x188 │ │ ldc2l 0, cr1, [r9, #812] @ 0x32c │ │ │ │ 024ae3c4 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #76 @ 0x4c │ │ mov r9, r0 │ │ @@ -1416595,21 +1416595,21 @@ │ │ ldr r0, [fp, #12] │ │ add r1, pc, r1 │ │ str r2, [fp, #-32] @ 0xffffffe0 │ │ add r0, r0, r2 │ │ sub r2, r8, r2 │ │ bl 270d9e0 │ │ b 24ae59c │ │ - vcadd.f32 d29, d23, d0, #270 │ │ + vcadd.f32 d29, d23, d29, #270 │ │ ldc2l 4, cr7, [r6, #336] @ 0x150 │ │ - ldc2l 9, cr4, [r7, #410] @ 0x19a @ │ │ - ldc2l 8, cr4, [r8, #868] @ 0x364 │ │ - ldc2l 9, cr13, [r7, #112] @ 0x70 @ │ │ + ldc2l 9, cr4, [r7, #500] @ 0x1f4 @ │ │ + ldc2l 9, cr4, [r8, #12] @ │ │ + ldc2l 9, cr13, [r7, #202] @ 0xca @ │ │ ldc2l 9, cr6, [r9, #404] @ 0x194 @ │ │ - ldc2l 10, cr4, [r7, #532] @ 0x214 @ │ │ + ldc2l 10, cr4, [r7, #712] @ 0x2c8 @ │ │ ldc2l 3, cr15, [r8, #88] @ 0x58 │ │ strdeq fp, [sl], -r0 @ │ │ eoreq fp, sl, r4, asr ip │ │ ldc2l 7, cr8, [r6, #364] @ 0x16c │ │ │ │ 024ae734 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ @@ -1416755,22 +1416755,22 @@ │ │ bl 270da10 │ │ mov r0, r5 │ │ mov r1, #7 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 3, cr7, [r7, #756] @ 0x2f4 │ │ + ldc2l 3, cr7, [r7, #936] @ 0x3a8 │ │ ldc2l 1, cr0, [sl, #392] @ 0x188 │ │ - ldc2l 6, cr4, [r7, #996] @ 0x3e4 │ │ - ldc2l 14, cr2, [r7, #584] @ 0x248 │ │ - ldc2l 2, cr7, [r7, #740] @ 0x2e4 │ │ + ldc2l 7, cr4, [r7, #152] @ 0x98 │ │ + ldc2l 14, cr2, [r7, #764] @ 0x2fc │ │ + ldc2l 2, cr7, [r7, #920] @ 0x398 │ │ ldc2l 6, cr10, [r9, #112] @ 0x70 │ │ - ldc2l 5, cr4, [r7, #996] @ 0x3e4 │ │ - ldc2l 2, cr9, [r7, #428] @ 0x1ac │ │ + ldc2l 6, cr4, [r7, #152] @ 0x98 │ │ + ldc2l 2, cr9, [r7, #608] @ 0x260 │ │ │ │ 024ae9a0 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #24 │ │ ldr r2, [r2, #32] │ │ ldr r7, [r1, #16] │ │ @@ -1416906,25 +1416906,25 @@ │ │ bl 270daf0 │ │ ldr r0, [pc, #60] @ 24aec00 │ │ mov r1, #10 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ mov r0, r5 │ │ b 24aea80 │ │ - ldc2l 3, cr3, [r7, #404] @ 0x194 │ │ + ldc2l 3, cr3, [r7, #584] @ 0x248 │ │ ldc2l 15, cr6, [r6, #900] @ 0x384 │ │ - ldc2l 4, cr4, [r7, #708] @ 0x2c4 │ │ - ldc2l 3, cr4, [r8, #948] @ 0x3b4 │ │ - ldc2l 2, cr3, [r7, #708] @ 0x2c4 │ │ - ldc2l 2, cr3, [r7, #664] @ 0x298 │ │ - ldc2l 3, cr4, [r7, #1012] @ 0x3f4 │ │ + ldc2l 4, cr4, [r7, #888] @ 0x378 │ │ + ldc2l 4, cr4, [r8, #104] @ 0x68 │ │ + ldc2l 2, cr3, [r7, #888] @ 0x378 │ │ + ldc2l 2, cr3, [r7, #844] @ 0x34c │ │ + ldc2l 4, cr4, [r7, #168] @ 0xa8 │ │ ldc2l 11, cr4, [r6, #284] @ 0x11c @ │ │ - ldc2l 2, cr3, [r7, #212] @ 0xd4 │ │ - ldc2l 2, cr13, [r7, #164] @ 0xa4 │ │ - ldc2l 3, cr4, [r7, #516] @ 0x204 │ │ + ldc2l 2, cr3, [r7, #392] @ 0x188 │ │ + ldc2l 2, cr13, [r7, #344] @ 0x158 │ │ + ldc2l 3, cr4, [r7, #696] @ 0x2b8 │ │ ldc2l 5, cr0, [r9, #108] @ 0x6c │ │ │ │ 024aec04 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #44 @ 0x2c │ │ mov r9, r0 │ │ @@ -1417200,26 +1417200,26 @@ │ │ lsr r0, r0, #5 │ │ str r0, [r8] │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 15, cr11, [r9, #36] @ 0x24 │ │ ldc2l 13, cr6, [r6, #132] @ 0x84 │ │ - ldc2l 1, cr4, [r7, #964] @ 0x3c4 │ │ - ldc2l 1, cr4, [r8, #180] @ 0xb4 │ │ + ldc2l 2, cr4, [r7, #120] @ 0x78 │ │ + ldc2l 1, cr4, [r8, #360] @ 0x168 │ │ eoreq fp, sl, r8, lsr r4 │ │ strdeq fp, [sl], -ip @ │ │ eoreq fp, sl, r4, lsr r3 │ │ ldc2l 14, cr11, [r9, #388] @ 0x184 │ │ - ldc2l 15, cr2, [r7, #968] @ 0x3c8 │ │ - ldc2l 1, cr4, [r7, #292] @ 0x124 │ │ + ldc2l 0, cr3, [r7, #124] @ 0x7c │ │ + ldc2l 1, cr4, [r7, #472] @ 0x1d8 │ │ ldc2l 8, cr4, [r6, #588] @ 0x24c │ │ ldc2l 13, cr11, [r9, #820] @ 0x334 │ │ - ldc2l 15, cr12, [r7, #372] @ 0x174 │ │ - ldc2l 0, cr4, [r7, #724] @ 0x2d4 │ │ + ldc2l 15, cr12, [r7, #552] @ 0x228 │ │ + ldc2l 0, cr4, [r7, #904] @ 0x388 │ │ ldc2l 2, cr0, [r9, #316] @ 0x13c │ │ │ │ 024af098 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #24 │ │ mov r4, r3 │ │ @@ -1417392,18 +1417392,18 @@ │ │ bl 270da10 │ │ mov r0, r5 │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - ldc2l 9, cr0, [r7, #180] @ 0xb4 @ │ │ + ldc2l 9, cr0, [r7, #270] @ 0x10e @ │ │ ldc2l 6, cr6, [r6, #672] @ 0x2a0 │ │ - ldc2l 12, cr3, [r7, #132] @ 0x84 │ │ - ldc2l 11, cr3, [r8, #180] @ 0xb4 @ │ │ + ldc2l 12, cr3, [r7, #312] @ 0x138 │ │ + ldc2l 11, cr3, [r8, #360] @ 0x168 @ │ │ strdeq fp, [sl], -ip @ │ │ │ │ 024af368 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #72 @ 0x48 │ │ ldr r5, [fp, #20] │ │ @@ -1417549,20 +1417549,20 @@ │ │ bl 270daf0 │ │ ldr r0, [pc, #36] @ 24af5d4 │ │ mov r1, #14 │ │ add r0, pc, r0 │ │ b 24af494 │ │ ldc2l 7, cr11, [r9, #936] @ 0x3a8 │ │ ldc2l 1, cr2, [r9, #320] @ 0x140 │ │ - ldc2l 10, cr3, [r7, #788] @ 0x314 @ │ │ - ldc2l 2, cr2, [r7, #376] @ 0x178 │ │ + ldc2l 10, cr3, [r7, #968] @ 0x3c8 @ │ │ + ldc2l 2, cr2, [r7, #556] @ 0x22c │ │ ldc2l 6, cr11, [r9, #808] @ 0x328 │ │ ldc2l 3, cr15, [r9, #164] @ 0xa4 │ │ - ldc2l 9, cr3, [r7, #338] @ 0x152 @ │ │ - ldc2l 6, cr8, [r7, #108] @ 0x6c │ │ + ldc2l 9, cr3, [r7, #428] @ 0x1ac @ │ │ + ldc2l 6, cr8, [r7, #288] @ 0x120 │ │ │ │ 024af5d8 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #24 │ │ mov r4, r0 │ │ ldr r0, [r2, #32] │ │ @@ -1417712,25 +1417712,25 @@ │ │ ldr r0, [pc, #64] @ 24af870 │ │ mov r1, #10 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #36] @ 24af864 │ │ add r0, pc, r0 │ │ b 24af704 │ │ - ldc2l 5, cr6, [r7, #148] @ 0x94 │ │ + ldc2l 5, cr6, [r7, #328] @ 0x148 │ │ ldc2l 2, cr6, [r6, #912] @ 0x390 │ │ - ldc2l 8, cr3, [r7, #372] @ 0x174 │ │ - ldc2l 7, cr3, [r8, #420] @ 0x1a4 │ │ - ldc2l 4, cr6, [r7, #340] @ 0x154 │ │ - ldc2l 6, cr2, [r7, #152] @ 0x98 │ │ - ldc2l 7, cr3, [r7, #500] @ 0x1f4 │ │ + vcadd.f32 d19, d23, d10, #270 │ │ + ldc2l 7, cr3, [r8, #600] @ 0x258 │ │ + ldc2l 4, cr6, [r7, #520] @ 0x208 │ │ + ldc2l 6, cr2, [r7, #332] @ 0x14c │ │ + ldc2l 7, cr3, [r7, #680] @ 0x2a8 │ │ ldc2l 14, cr3, [r6, #796] @ 0x31c │ │ - ldc2l 3, cr6, [r7, #404] @ 0x194 │ │ - ldc2l 5, cr12, [r7, #756] @ 0x2f4 │ │ - ldc2l 7, cr3, [r7, #84] @ 0x54 │ │ + ldc2l 3, cr6, [r7, #584] @ 0x248 │ │ + ldc2l 5, cr12, [r7, #936] @ 0x3a8 │ │ + ldc2l 7, cr3, [r7, #264] @ 0x108 │ │ vcadd.f32 d31, d24, d31, #270 │ │ │ │ 024af874 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #44 @ 0x2c │ │ mov r4, r0 │ │ @@ -1417998,28 +1417998,28 @@ │ │ bgt 24afc18 │ │ bl 270db90 │ │ clz r0, r0 │ │ ldr r6, [fp, #24] │ │ lsr r0, r0, #5 │ │ str r0, [r6] │ │ b 24af98c │ │ - ldc2l 2, cr0, [r7, #956] @ 0x3bc │ │ + ldc2l 3, cr0, [r7, #112] @ 0x70 │ │ ldc2l 0, cr6, [r6, #884] @ 0x374 │ │ - ldc2l 5, cr3, [r7, #692] @ 0x2b4 │ │ - ldc2l 4, cr3, [r8, #932] @ 0x3a4 │ │ + ldc2l 5, cr3, [r7, #872] @ 0x368 │ │ + ldc2l 5, cr3, [r8, #88] @ 0x58 │ │ eoreq sl, sl, r4, ror #15 │ │ eoreq sl, sl, ip, lsr #15 │ │ ldrdeq sl, [sl], -ip @ │ │ - ldc2l 2, cr0, [r7, #92] @ 0x5c │ │ - ldc2l 3, cr2, [r7, #504] @ 0x1f8 │ │ - ldc2l 4, cr3, [r7, #852] @ 0x354 │ │ + ldc2l 2, cr0, [r7, #272] @ 0x110 │ │ + ldc2l 3, cr2, [r7, #684] @ 0x2ac │ │ + ldc2l 5, cr3, [r7, #8] │ │ ldc2l 12, cr3, [r6, #124] @ 0x7c │ │ - ldc2l 1, cr0, [r7, #620] @ 0x26c │ │ - ldc2l 3, cr12, [r7, #4] │ │ - ldc2l 4, cr3, [r7, #356] @ 0x164 │ │ + ldc2l 1, cr0, [r7, #800] @ 0x320 │ │ + ldc2l 3, cr12, [r7, #184] @ 0xb8 │ │ + ldc2l 4, cr3, [r7, #536] @ 0x218 │ │ ldc2l 5, cr15, [r8, #972] @ 0x3cc │ │ │ │ 024afcf0 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #48 @ 0x30 │ │ mov r5, r3 │ │ @@ -1418139,16 +1418139,16 @@ │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ ldc2l 9, cr13, [r8, #458] @ 0x1ca @ │ │ ldc2l 11, cr5, [r6, #144] @ 0x90 @ │ │ - ldc2l 0, cr3, [r7, #628] @ 0x274 │ │ - ldc2l 15, cr2, [r8, #676] @ 0x2a4 │ │ + ldc2l 0, cr3, [r7, #808] @ 0x328 │ │ + ldc2l 15, cr2, [r8, #856] @ 0x358 │ │ eoreq sl, sl, r0, lsl #11 │ │ │ │ 024afeec : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #12 │ │ sub r0, r0, #1 │ │ @@ -1418928,20 +1418928,20 @@ │ │ ldreq r7, [pc, #-1312]! @ 24b05f8 │ │ ldreq r7, [pc, #-1352]! @ 24b05d4 │ │ ldreq r7, [pc, #-1300]! @ 24b060c │ │ ldreq r7, [pc, #-3180]! @ 24afeb8 │ │ ldreq r7, [pc, #-3204]! @ 24afea4 │ │ ldc2l 10, cr9, [r6, #520] @ 0x208 @ │ │ ldc2l 5, cr5, [r6, #924] @ 0x39c │ │ - ldc2l 10, cr2, [r7, #468] @ 0x1d4 @ │ │ - ldc2l 15, cr10, [r7, #308] @ 0x134 │ │ + ldc2l 10, cr2, [r7, #648] @ 0x288 @ │ │ + ldc2l 15, cr10, [r7, #488] @ 0x1e8 │ │ ldreq r7, [pc, #-3120]! @ 24aff0c │ │ ldc2l 14, cr9, [r6, #680] @ 0x2a8 │ │ - ldc2l 3, cr3, [r8, #788] @ 0x314 │ │ - ldc2l 14, cr2, [r7, #292] @ 0x124 │ │ + ldc2l 3, cr3, [r8, #968] @ 0x3c8 │ │ + ldc2l 14, cr2, [r7, #472] @ 0x1d8 │ │ ldreq r7, [pc, #-2944]! @ 24affcc │ │ ldreq r7, [pc, #-1900]! @ 24b03e4 │ │ ldreq r7, [pc, #-1876]! @ 24b0400 │ │ ldreq r7, [pc, #-1888]! @ 24b03f8 │ │ ldreq r7, [pc, #-1864]! @ 24b0414 │ │ ldc2l 2, cr13, [r8, #1016] @ 0x3f8 │ │ ldc2l 10, cr8, [r9, #252] @ 0xfc @ │ │ @@ -1418957,28 +1418957,28 @@ │ │ ldreq r7, [pc, #-1088]! @ 24b074c │ │ ldreq r7, [pc, #-1068]! @ 24b0764 │ │ ldreq r7, [pc, #-1092]! @ 24b0750 │ │ ldreq r7, [pc, #-1000]! @ 24b07b0 │ │ ldreq r7, [pc, #-996]! @ 24b07b8 │ │ ldreq r7, [pc, #-3068]! @ 24affa4 │ │ ldreq r7, [pc, #-3092]! @ 24aff90 │ │ - ldc2l 9, cr11, [r7, #220] @ 0xdc @ │ │ + ldc2l 9, cr11, [r7, #310] @ 0x136 @ │ │ ldc2l 5, cr14, [r9, #208] @ 0xd0 │ │ ldreq r7, [pc, #-3008]! @ 24afff0 │ │ - ldc2l 13, cr11, [r7, #296] @ 0x128 │ │ + ldc2l 13, cr11, [r7, #476] @ 0x1dc │ │ ldc2l 4, cr7, [r9, #596] @ 0x254 │ │ ldreq r7, [pc, #-1708]! @ 24b0510 │ │ ldreq r7, [pc, #-3300]! @ 24afedc │ │ ldc2l 5, cr7, [r9, #1000] @ 0x3e8 │ │ ldc2l 2, cr3, [r9, #64] @ 0x40 │ │ - ldc2l 15, cr2, [r7, #420] @ 0x1a4 │ │ + ldc2l 15, cr2, [r7, #600] @ 0x258 │ │ ldreq r7, [pc, #-3212]! @ 24aff44 │ │ ldc2l 5, cr14, [r9, #712] @ 0x2c8 │ │ ldc2l 14, cr6, [r9, #152] @ 0x98 │ │ - ldc2l 1, cr15, [r7, #116] @ 0x74 │ │ + ldc2l 1, cr15, [r7, #296] @ 0x128 │ │ ldreq r7, [pc, #-2368]! @ 24b02a0 │ │ ldreq r7, [pc, #-2384]! @ 24b0294 │ │ ldc2l 12, cr8, [r9, #364] @ 0x16c │ │ ldc2l 4, cr13, [r8, #952] @ 0x3b8 │ │ ldreq r7, [pc, #-2300]! @ 24b02f4 │ │ ldreq r7, [pc, #-976]! @ 24b0824 │ │ ldreq r7, [pc, #-1000]! @ 24b0810 │ │ @@ -1418987,19 +1418987,19 @@ │ │ ldreq r7, [pc, #-904]! @ 24b087c │ │ ldreq r7, [pc, #-656]! @ 24b0978 │ │ eoreq r9, sl, r4, lsl r9 │ │ ldreq r7, [pc, #-700]! @ 24b0954 │ │ ldreq r7, [pc, #-2620]! @ 24b01d8 │ │ ldc2l 6, cr15, [r8, #188] @ 0xbc │ │ ldc2l 15, cr2, [r9, #416] @ 0x1a0 │ │ - ldc2l 12, cr2, [r7, #772] @ 0x304 │ │ + ldc2l 12, cr2, [r7, #952] @ 0x3b8 │ │ ldreq r7, [pc, #-2532]! @ 24b0240 │ │ ldc2l 3, cr14, [r9, #40] @ 0x28 │ │ ldc2l 0, cr15, [r8, #876] @ 0x36c │ │ - ldc2l 0, cr15, [r7, #980] @ 0x3d4 │ │ + ldc2l 1, cr15, [r7, #136] @ 0x88 │ │ ldreq r7, [pc, #-2184]! @ 24b03ac │ │ ldreq r7, [pc, #-2200]! @ 24b03a0 │ │ ldc2l 4, cr13, [r8, #312] @ 0x138 │ │ ldc2l 11, cr8, [r9, #556] @ 0x22c @ │ │ ldreq r7, [pc, #-2116]! @ 24b0400 │ │ ldreq r7, [pc, #-824]! @ 24b0910 │ │ ldreq r7, [pc, #-844]! @ 24b0900 │ │ @@ -1419611,38 +1419611,38 @@ │ │ mov r1, #1 │ │ mov r7, r0 │ │ mov sl, r2 │ │ mov ip, r8 │ │ b 24b10a4 │ │ ldc2l 8, cr4, [r6, #996] @ 0x3e4 │ │ ldc2l 5, cr8, [r8, #908] @ 0x38c │ │ - ldc2l 13, cr1, [r7, #308] @ 0x134 │ │ - ldc2l 12, cr1, [r8, #420] @ 0x1a4 │ │ + ldc2l 13, cr1, [r7, #488] @ 0x1e8 │ │ + ldc2l 12, cr1, [r8, #600] @ 0x258 │ │ ldc2l 10, cr4, [r6, #516] @ 0x204 @ │ │ ldc2l 15, cr7, [r9, #440] @ 0x1b8 │ │ - ldc2l 14, cr1, [r7, #852] @ 0x354 │ │ + ldc2l 15, cr1, [r7, #8] │ │ ldc2l 11, cr9, [r9, #592] @ 0x250 @ │ │ ldc2l 6, cr4, [r6, #404] @ 0x194 │ │ - ldc2l 5, cr12, [r6, #896] @ 0x380 │ │ - ldc2l 10, cr1, [r7, #740] @ 0x2e4 @ │ │ + ldc2l 6, cr12, [r6, #52] @ 0x34 │ │ + ldc2l 10, cr1, [r7, #920] @ 0x398 @ │ │ ldc2l 12, cr13, [r8, #460] @ 0x1cc │ │ ldc2l 5, cr4, [r6, #564] @ 0x234 │ │ - ldc2l 5, cr12, [r6, #32] │ │ - ldc2l 9, cr1, [r7, #450] @ 0x1c2 @ │ │ + ldc2l 5, cr12, [r6, #212] @ 0xd4 │ │ + ldc2l 10, cr1, [r7, #56] @ 0x38 @ │ │ ldc2l 11, cr13, [r8, #620] @ 0x26c @ │ │ ldc2l 6, cr4, [r6, #548] @ 0x224 │ │ - ldc2l 0, cr4, [r8, #860] @ 0x35c │ │ + ldc2l 1, cr4, [r8, #16] │ │ ldc2l 14, cr13, [r8, #68] @ 0x44 │ │ ldc2l 1, cr8, [r6, #4] │ │ ldc2l 14, cr13, [r8, #484] @ 0x1e4 │ │ ldc2l 1, cr8, [r6, #420] @ 0x1a4 │ │ ldc2l 7, cr4, [r6, #516] @ 0x204 │ │ - ldc2l 9, cr6, [r7, #130] @ 0x82 @ │ │ - ldc2l 11, cr1, [r7, #852] @ 0x354 @ │ │ - ldc2l 6, cr12, [r6, #112] @ 0x70 │ │ + ldc2l 9, cr6, [r7, #220] @ 0xdc @ │ │ + ldc2l 12, cr1, [r7, #8] │ │ + ldc2l 6, cr12, [r6, #292] @ 0x124 │ │ │ │ 024b15f0 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #16 │ │ add r3, sp, #4 │ │ mov r4, r2 │ │ @@ -1419724,18 +1419724,18 @@ │ │ bl 270da10 │ │ mov r0, r5 │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - ldc2l 5, cr14, [r6, #304] @ 0x130 │ │ - ldc2l 14, cr3, [r8, #292] @ 0x124 │ │ - vcadd.f32 d17, d7, d1, #270 │ │ - ldc2l 7, cr1, [r8, #244] @ 0xf4 │ │ + ldc2l 5, cr14, [r6, #484] @ 0x1e4 │ │ + ldc2l 14, cr3, [r8, #472] @ 0x1d8 │ │ + vcadd.f32 d17, d7, d30, #270 │ │ + ldc2l 7, cr1, [r8, #424] @ 0x1a8 │ │ eoreq r8, sl, r0, lsl #25 │ │ │ │ 024b1758 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #36 @ 0x24 │ │ mov r6, r3 │ │ @@ -1419885,18 +1419885,18 @@ │ │ mov r1, #8 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 8, cr7, [r9, #124] @ 0x7c │ │ - ldc2l 9, cr11, [r6, #332] @ 0x14c @ │ │ + ldc2l 9, cr11, [r6, #422] @ 0x1a6 @ │ │ ldc2l 6, cr11, [r9, #884] @ 0x374 │ │ - ldc2l 5, cr1, [r7, #564] @ 0x234 │ │ - ldc2l 6, cr1, [r8, #456] @ 0x1c8 │ │ + ldc2l 5, cr1, [r7, #744] @ 0x2e8 │ │ + ldc2l 6, cr1, [r8, #636] @ 0x27c │ │ ldrdeq r8, [sl], -ip @ │ │ ldrdeq r8, [sl], -r0 @ │ │ ldc2l 5, cr5, [r6, #844] @ 0x34c │ │ eoreq r8, sl, r0, asr #20 │ │ eoreq r8, sl, ip, lsr #20 │ │ ldc2l 5, cr5, [r6, #140] @ 0x8c │ │ ldc2l 5, cr7, [r9, #1020] @ 0x3fc │ │ @@ -1419965,18 +1419965,18 @@ │ │ bl 270d5a0 │ │ ldr r4, [sp, #20] │ │ b 24b1aec │ │ mov r4, #1 │ │ mov r0, r4 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2l 13, cr11, [r7, #716] @ 0x2cc │ │ + ldc2l 13, cr11, [r7, #896] @ 0x380 │ │ ldc2l 15, cr3, [r6, #884] @ 0x374 │ │ - ldc2l 4, cr1, [r7, #692] @ 0x2b4 │ │ - ldc2l 3, cr1, [r8, #932] @ 0x3a4 │ │ + ldc2l 4, cr1, [r7, #872] @ 0x368 │ │ + ldc2l 4, cr1, [r8, #88] @ 0x58 │ │ │ │ 024b1b08 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #32 │ │ ldr r5, [r2, #32] │ │ ldr r4, [r1, #20] │ │ @@ -1420040,18 +1420040,18 @@ │ │ bl 270dd90 │ │ mov r1, r0 │ │ b 24b1c10 │ │ mov r1, #1 │ │ mov r0, r1 │ │ sub sp, fp, #8 │ │ pop {r4, r5, fp, pc} │ │ - ldc2l 1, cr2, [r7, #220] @ 0xdc │ │ + ldc2l 1, cr2, [r7, #400] @ 0x190 │ │ ldc2l 14, cr3, [r6, #804] @ 0x324 │ │ - ldc2l 3, cr1, [r7, #612] @ 0x264 │ │ - ldc2l 2, cr1, [r8, #852] @ 0x354 │ │ + ldc2l 3, cr1, [r7, #792] @ 0x318 │ │ + ldc2l 3, cr1, [r8, #8] │ │ │ │ 024b1c2c : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #24 │ │ ldr r6, [r2, #32] │ │ mov r4, #0 │ │ @@ -1420112,18 +1420112,18 @@ │ │ bl 270fce0 │ │ ldr r4, [sp, #20] │ │ b 24b1d28 │ │ mov r4, #1 │ │ mov r0, r4 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2l 1, cr10, [r7, #476] @ 0x1dc │ │ + ldc2l 1, cr10, [r7, #656] @ 0x290 │ │ ldc2l 13, cr3, [r6, #628] @ 0x274 │ │ - ldc2l 2, cr1, [r7, #436] @ 0x1b4 │ │ - ldc2l 1, cr1, [r8, #676] @ 0x2a4 │ │ + ldc2l 2, cr1, [r7, #616] @ 0x268 │ │ + ldc2l 1, cr1, [r8, #856] @ 0x358 │ │ │ │ 024b1d44 : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #8 │ │ mov r1, r0 │ │ ldr r0, [pc, #20] @ 24b1d70 │ │ @@ -1420701,28 +1420701,28 @@ │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldrbeq pc, [r7, #1320] @ 0x528 @ │ │ ldrbeq pc, [r7, #2392] @ 0x958 @ │ │ ldrbeq pc, [r7, #2177] @ 0x881 @ │ │ - ldc2l 2, cr11, [r6, #504] @ 0x1f8 │ │ + ldc2l 2, cr11, [r6, #684] @ 0x2ac │ │ ldrbeq pc, [r7, #2112] @ 0x840 @ │ │ ldrbeq pc, [r7, #2148] @ 0x864 @ │ │ ldrbeq pc, [r7, #940] @ 0x3ac @ │ │ ldrbeq pc, [r7, #1988] @ 0x7c4 @ │ │ ldrbeq pc, [r7, #2008] @ 0x7d8 @ │ │ - ldc2l 13, cr15, [r6, #1000] @ 0x3e8 │ │ - ldc2l 11, cr3, [r7, #648] @ 0x288 @ │ │ - ldc2l 14, cr0, [r7, #916] @ 0x394 │ │ + ldc2l 14, cr15, [r6, #156] @ 0x9c │ │ + ldc2l 11, cr3, [r7, #828] @ 0x33c @ │ │ + ldc2l 15, cr0, [r7, #72] @ 0x48 │ │ ldrbeq pc, [r7, #1804] @ 0x70c @ │ │ - ldc2l 15, cr0, [r8, #664] @ 0x298 │ │ + ldc2l 15, cr0, [r8, #844] @ 0x34c │ │ ldrbeq pc, [r7, #2308] @ 0x904 @ │ │ ldrbeq pc, [r7, #2085] @ 0x825 @ │ │ - ldc2l 2, cr11, [r6, #136] @ 0x88 │ │ + ldc2l 2, cr11, [r6, #316] @ 0x13c │ │ ldrbeq pc, [r7, #2068] @ 0x814 @ │ │ ldrbeq pc, [r7, #2312] @ 0x908 @ │ │ ldrbeq pc, [r7, #2340] @ 0x924 @ │ │ ldrbeq pc, [r7, #2248] @ 0x8c8 @ │ │ ldrbeq pc, [r7, #2216] @ 0x8a8 @ │ │ ldrbeq pc, [r7, #2220] @ 0x8ac @ │ │ ldrbeq pc, [r7, #2208] @ 0x8a0 @ │ │ @@ -1420731,80 +1420731,80 @@ │ │ ldrbeq pc, [r7, #636] @ 0x27c @ │ │ ldrbeq pc, [r7, #580] @ 0x244 @ │ │ ldrbeq pc, [r7, #584] @ 0x248 @ │ │ ldrbeq pc, [r7, #560] @ 0x230 @ │ │ ldrbeq pc, [r7, #516] @ 0x204 @ │ │ ldrbeq pc, [r7, #496] @ 0x1f0 @ │ │ ldrbeq pc, [r7, #484] @ 0x1e4 @ │ │ - ldc2l 8, cr9, [r7, #592] @ 0x250 │ │ + vcadd.f32 , , , #270 │ │ ldc2l 2, cr7, [r8, #500] @ 0x1f4 │ │ ldrbeq lr, [r7, #3464] @ 0xd88 │ │ ldrbeq pc, [r7, #384] @ 0x180 @ │ │ ldrbeq pc, [r7, #372] @ 0x174 @ │ │ ldrbeq lr, [r7, #3424] @ 0xd60 │ │ ldrbeq pc, [r7, #1900] @ 0x76c @ │ │ - ldc2l 14, cr9, [r7, #96] @ 0x60 │ │ + ldc2l 14, cr9, [r7, #276] @ 0x114 │ │ vcadd.f32 d23, d8, d1, #270 │ │ ldrbeq pc, [r7, #1736] @ 0x6c8 @ │ │ ldrbeq pc, [r7, #1664] @ 0x680 @ │ │ - ldc2l 13, cr9, [r7, #144] @ 0x90 │ │ + ldc2l 13, cr9, [r7, #324] @ 0x144 │ │ ldc2l 7, cr7, [r8, #52] @ 0x34 │ │ ldrbeq pc, [r7, #1576] @ 0x628 @ │ │ ldrbeq pc, [r7, #1544] @ 0x608 @ │ │ ldrbeq pc, [r7, #1532] @ 0x5fc @ │ │ ldrbeq pc, [r7, #1532] @ 0x5fc @ │ │ ldrbeq pc, [r7, #1512] @ 0x5e8 @ │ │ ldrbeq pc, [r7, #1468] @ 0x5bc @ │ │ ldrbeq pc, [r7, #416] @ 0x1a0 @ │ │ ldrbeq pc, [r7, #1448] @ 0x5a8 @ │ │ ldrbeq pc, [r7, #1444] @ 0x5a4 @ │ │ ldrbeq pc, [r7, #1436] @ 0x59c @ │ │ ldrbeq pc, [r7, #1436] @ 0x59c @ │ │ ldrbeq pc, [r7, #1400] @ 0x578 @ │ │ - ldc2l 12, cr9, [r7, #176] @ 0xb0 │ │ + ldc2l 12, cr9, [r7, #356] @ 0x164 │ │ ldc2l 6, cr7, [r8, #84] @ 0x54 │ │ ldrbeq pc, [r7, #1384] @ 0x568 @ │ │ ldrbeq pc, [r7, #1344] @ 0x540 @ │ │ ldrbeq pc, [r7, #1332] @ 0x534 @ │ │ ldrbeq pc, [r7, #1312] @ 0x520 @ │ │ ldrbeq pc, [r7, #1312] @ 0x520 @ │ │ ldrbeq pc, [r7, #1252] @ 0x4e4 @ │ │ - ldc2l 8, cr15, [r6, #232] @ 0xe8 │ │ - ldc2l 4, cr11, [r6, #444] @ 0x1bc │ │ + vcadd.f32 , q3, , #270 │ │ + ldc2l 4, cr11, [r6, #624] @ 0x270 │ │ ldrbeq pc, [r7, #1184] @ 0x4a0 @ │ │ - ldc2l 11, cr9, [r7, #320] @ 0x140 @ │ │ + ldc2l 11, cr9, [r7, #500] @ 0x1f4 @ │ │ ldc2l 5, cr7, [r8, #228] @ 0xe4 │ │ ldrbeq pc, [r7, #1152] @ 0x480 @ │ │ ldrbeq pc, [r7, #1136] @ 0x470 @ │ │ ldrbeq pc, [r7, #1100] @ 0x44c @ │ │ ldrbeq pc, [r7, #1072] @ 0x430 @ │ │ ldrbeq pc, [r7, #1064] @ 0x428 @ │ │ - ldc2l 10, cr9, [r7, #832] @ 0x340 @ │ │ + ldc2l 10, cr9, [r7, #1012] @ 0x3f4 @ │ │ ldc2l 4, cr7, [r8, #740] @ 0x2e4 │ │ ldrbeq pc, [r7, #952] @ 0x3b8 @ │ │ ldrbeq pc, [r7, #964] @ 0x3c4 @ │ │ ldrbeq pc, [r7, #928] @ 0x3a0 @ │ │ ldrbeq pc, [r7, #924] @ 0x39c @ │ │ ldrbeq pc, [r7, #900] @ 0x384 @ │ │ ldrbeq pc, [r7, #868] @ 0x364 @ │ │ ldrbeq lr, [r7, #3912] @ 0xf48 │ │ ldrbeq pc, [r7, #844] @ 0x34c @ │ │ ldrbeq lr, [r7, #3892] @ 0xf34 │ │ ldrbeq pc, [r7, #828] @ 0x33c @ │ │ ldrbeq pc, [r7, #844] @ 0x34c @ │ │ ldrbeq pc, [r7, #816] @ 0x330 @ │ │ ldrbeq pc, [r7, #800] @ 0x320 @ │ │ - ldc2l 9, cr9, [r7, #424] @ 0x1a8 @ │ │ + ldc2l 10, cr9, [r7, #4] @ │ │ ldc2l 3, cr7, [r8, #756] @ 0x2f4 │ │ ldrbeq pc, [r7, #784] @ 0x310 @ │ │ ldrbeq pc, [r7, #732] @ 0x2dc @ │ │ ldrbeq pc, [r7, #712] @ 0x2c8 @ │ │ - ldc2l 9, cr15, [r6, #228] @ 0xe4 @ │ │ - ldc2l 7, cr13, [r6, #628] @ 0x274 │ │ - ldc2l 9, cr0, [r7, #74] @ 0x4a @ │ │ + ldc2l 9, cr15, [r6, #318] @ 0x13e @ │ │ + ldc2l 7, cr13, [r6, #808] @ 0x328 │ │ + ldc2l 9, cr0, [r7, #164] @ 0xa4 @ │ │ ldrbeq pc, [r7, #332] @ 0x14c @ │ │ ldc2l 10, cr12, [r8, #748] @ 0x2ec @ │ │ │ │ 024b27d8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #12 │ │ @@ -1421372,65 +1421372,65 @@ │ │ ldr r0, [pc, #224] @ 24b3180 │ │ add r0, pc, r0 │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 11, cr2, [r8, #772] @ 0x304 @ │ │ + ldc2l 11, cr2, [r8, #952] @ 0x3b8 @ │ │ ldc2l 11, cr7, [r9, #104] @ 0x68 @ │ │ ldc2l 12, cr4, [r9, #236] @ 0xec │ │ ldc2l 12, cr14, [r8, #492] @ 0x1ec │ │ - ldc2l 5, cr0, [r7, #596] @ 0x254 │ │ + ldc2l 5, cr0, [r7, #776] @ 0x308 │ │ mlaeq sl, r4, r9, r7 │ │ ldrbeq pc, [r7, #1432] @ 0x598 @ │ │ ldrbeq lr, [r7, #3876] @ 0xf24 │ │ ldrbeq pc, [r7, #1388] @ 0x56c @ │ │ ldrbeq lr, [r7, #3848] @ 0xf08 │ │ ldc2l 11, cr8, [r8, #704] @ 0x2c0 @ │ │ ldc2l 14, cr11, [r9, #528] @ 0x210 │ │ ldc2l 10, cr10, [r8, #76] @ 0x4c @ │ │ - ldc2l 0, cr0, [r7, #820] @ 0x334 │ │ + ldc2l 0, cr0, [r7, #1000] @ 0x3e8 │ │ ldrbeq lr, [r7, #3120] @ 0xc30 │ │ ldrbeq lr, [r7, #3100] @ 0xc1c │ │ ldrbeq pc, [r7, #604] @ 0x25c @ │ │ - ldc2l 6, cr2, [r8, #936] @ 0x3a8 │ │ + ldc2l 7, cr2, [r8, #92] @ 0x5c │ │ ldrbeq lr, [r7, #3796] @ 0xed4 │ │ ldrbeq pc, [r7, #1324] @ 0x52c @ │ │ ldrbeq lr, [r7, #3768] @ 0xeb8 │ │ ldrbeq pc, [r7, #1224] @ 0x4c8 @ │ │ ldrbeq lr, [r7, #3704] @ 0xe78 │ │ ldrbeq lr, [r7, #3680] @ 0xe60 │ │ - ldc2l 1, cr15, [r6, #828] @ 0x33c │ │ - ldc2l 2, cr0, [r7, #788] @ 0x314 │ │ + ldc2l 1, cr15, [r6, #1008] @ 0x3f0 │ │ + ldc2l 2, cr0, [r7, #968] @ 0x3c8 │ │ ldrbeq lr, [r7, #3632] @ 0xe30 │ │ eoreq r7, sl, r8, asr #13 │ │ ldrbeq lr, [r7, #3580] @ 0xdfc │ │ ldrbeq lr, [r7, #3568] @ 0xdf0 │ │ ldrbeq lr, [r7, #3536] @ 0xdd0 │ │ ldrbeq lr, [r7, #3524] @ 0xdc4 │ │ ldc2l 5, cr4, [r9, #784] @ 0x310 │ │ - ldc2l 15, cr15, [r6, #212] @ 0xd4 │ │ + ldc2l 15, cr15, [r6, #392] @ 0x188 │ │ ldrbeq lr, [r7, #2712] @ 0xa98 │ │ ldrbeq lr, [r7, #2692] @ 0xa84 │ │ ldrbeq lr, [r7, #2684] @ 0xa7c │ │ ldrbeq lr, [r7, #3504] @ 0xdb0 │ │ ldrbeq lr, [r7, #3488] @ 0xda0 │ │ eoreq r7, sl, r4, lsr r6 │ │ ldrbeq pc, [r7, #176] @ 0xb0 @ │ │ ldrbeq lr, [r7, #3428] @ 0xd64 │ │ ldrbeq lr, [r7, #3412] @ 0xd54 │ │ ldrbeq lr, [r7, #3288] @ 0xcd8 │ │ ldrbeq pc, [r7, #804] @ 0x324 @ │ │ ldc2l 1, cr0, [r9, #752] @ 0x2f0 │ │ - ldc2l 14, cr15, [r6, #932] @ 0x3a4 │ │ + ldc2l 15, cr15, [r6, #88] @ 0x58 │ │ ldrbeq lr, [r7, #2636] @ 0xa4c │ │ ldrbeq lr, [r7, #2624] @ 0xa40 │ │ ldrbeq pc, [r7, #80] @ 0x50 @ │ │ - ldc2l 3, cr8, [r7, #388] @ 0x184 │ │ + ldc2l 3, cr8, [r7, #568] @ 0x238 │ │ ldc2l 4, cr4, [r9, #860] @ 0x35c │ │ ldrbeq lr, [r7, #3248] @ 0xcb0 │ │ ldc2l 10, cr13, [r9, #128] @ 0x80 @ │ │ ldc2l 12, cr11, [r9, #80] @ 0x50 │ │ ldrbeq lr, [r7, #3188] @ 0xc74 │ │ ldrbeq lr, [r7, #3184] @ 0xc70 │ │ ldc2l 10, cr13, [r9, #848] @ 0x350 @ │ │ @@ -1421442,33 +1421442,33 @@ │ │ ldc2l 11, cr11, [r9, #336] @ 0x150 @ │ │ ldrbeq pc, [r7, #516] @ 0x204 @ │ │ ldrbeq lr, [r7, #2988] @ 0xbac │ │ ldrbeq lr, [r7, #2952] @ 0xb88 │ │ ldrbeq pc, [r7, #384] @ 0x180 @ │ │ ldrbeq pc, [r7, #372] @ 0x174 @ │ │ ldc2l 11, cr7, [r9, #792] @ 0x318 @ │ │ - ldc2l 14, cr15, [r6, #708] @ 0x2c4 │ │ + ldc2l 14, cr15, [r6, #888] @ 0x378 │ │ ldrbeq lr, [r7, #2580] @ 0xa14 │ │ ldrbeq pc, [r7, #104] @ 0x68 @ │ │ ldrbeq lr, [r7, #2824] @ 0xb08 │ │ ldrbeq pc, [r7, #328] @ 0x148 @ │ │ ldrbeq lr, [r7, #2800] @ 0xaf0 │ │ ldc2l 14, cr13, [r8, #944] @ 0x3b0 │ │ ldc2l 10, cr11, [r9, #384] @ 0x180 @ │ │ ldrbeq lr, [r7, #2752] @ 0xac0 │ │ ldrbeq lr, [r7, #2096] @ 0x830 │ │ ldrbeq lr, [r7, #2880] @ 0xb40 │ │ ldrbeq pc, [r7, #460] @ 0x1cc @ │ │ ldc2l 6, cr4, [r9, #476] @ 0x1dc │ │ ldrbeq pc, [r7, #2036] @ 0x7f4 @ │ │ - ldc2l 2, cr7, [r7, #884] @ 0x374 │ │ - ldc2l 4, cr9, [r7, #100] @ 0x64 │ │ - ldc2l 5, cr0, [r7, #84] @ 0x54 │ │ + ldc2l 3, cr7, [r7, #40] @ 0x28 │ │ + ldc2l 4, cr9, [r7, #280] @ 0x118 │ │ + ldc2l 5, cr0, [r7, #264] @ 0x108 │ │ ldrbeq pc, [r7, #1724] @ 0x6bc @ │ │ - ldc2l 4, cr0, [r8, #308] @ 0x134 │ │ + ldc2l 4, cr0, [r8, #488] @ 0x1e8 │ │ ldrbeq pc, [r7, #2012] @ 0x7dc @ │ │ ldrbeq pc, [r7, #1192] @ 0x4a8 @ │ │ ldrbeq pc, [r7, #1984] @ 0x7c0 @ │ │ ldc2l 13, cr13, [r9, #832] @ 0x340 │ │ ldc2l 15, cr11, [r9, #784] @ 0x310 │ │ ldrbeq pc, [r7, #1660] @ 0x67c @ │ │ ldrbeq pc, [r7, #1616] @ 0x650 @ │ │ @@ -1421501,15 +1421501,15 @@ │ │ add r0, pc, r0 │ │ bl 270da10 │ │ mov r0, r4 │ │ mov r1, #8 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, sl, fp, pc} │ │ - ldc2l 2, cr2, [r8, #884] @ 0x374 │ │ + ldc2l 3, cr2, [r8, #40] @ 0x28 │ │ ldc2l 2, cr7, [r9, #216] @ 0xd8 │ │ │ │ 024b32b8 : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #8 │ │ mov r2, r1 │ │ @@ -1421811,21 +1421811,21 @@ │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ eoreq r6, sl, r8, lsl #29 │ │ eoreq r6, sl, r0, ror lr │ │ strdeq r6, [sl], -r0 @ │ │ ldrdeq r6, [sl], -r8 @ │ │ ldc2l 2, cr13, [r9, #28] │ │ - ldc2l 15, cr1, [r8, #400] @ 0x190 │ │ - ldc2l 8, cr15, [r6, #868] @ 0x364 │ │ + ldc2l 15, cr1, [r8, #580] @ 0x244 │ │ + ldc2l 9, cr15, [r6, #12] @ │ │ ldc2l 10, cr11, [r8, #396] @ 0x18c @ │ │ ldc2l 1, cr13, [r9, #28] │ │ ldc2l 15, cr7, [r8, #820] @ 0x334 │ │ - ldc2l 7, cr15, [r6, #868] @ 0x364 │ │ - ldc2l 2, cr10, [r6, #208] @ 0xd0 │ │ + vcadd.f32 d31, d6, d6, #270 │ │ + ldc2l 2, cr10, [r6, #388] @ 0x184 │ │ │ │ 024b378c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #412 @ 0x19c │ │ sub sp, sp, #2048 @ 0x800 │ │ str r0, [sp, #68] @ 0x44 │ │ @@ -1422202,30 +1422202,30 @@ │ │ ldr r0, [pc, #32] @ 24b3d90 │ │ mov r1, #19 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ b 24b3c3c │ │ strhteq r6, [sl], -r8 │ │ eoreq r6, sl, r0, ror #20 │ │ - ldc2l 0, cr6, [r7, #88] @ 0x58 │ │ - ldc2l 0, cr6, [r7, #60] @ 0x3c │ │ - ldc2l 2, cr15, [r6, #292] @ 0x124 │ │ - ldc2l 0, cr15, [r7, #964] @ 0x3c4 │ │ + ldc2l 0, cr6, [r7, #268] @ 0x10c │ │ + ldc2l 0, cr6, [r7, #240] @ 0xf0 │ │ + ldc2l 2, cr15, [r6, #472] @ 0x1d8 │ │ + ldc2l 1, cr15, [r7, #120] @ 0x78 │ │ ldc2l 5, cr11, [r8, #36] @ 0x24 │ │ ldc2l 7, cr5, [r6, #1012] @ 0x3f4 │ │ - ldc2l 15, cr5, [r7, #648] @ 0x288 │ │ - ldc2l 15, cr5, [r7, #620] @ 0x26c │ │ - ldc2l 1, cr15, [r6, #852] @ 0x354 │ │ + ldc2l 15, cr5, [r7, #828] @ 0x33c │ │ + ldc2l 15, cr5, [r7, #800] @ 0x320 │ │ + ldc2l 2, cr15, [r6, #8] │ │ ldc2l 6, cr11, [r8, #356] @ 0x164 │ │ ldc2l 9, cr5, [r6, #154] @ 0x9a @ │ │ - ldc2l 0, cr6, [r7, #712] @ 0x2c8 │ │ + ldc2l 0, cr6, [r7, #892] @ 0x37c │ │ ldc2l 10, cr7, [r8, #868] @ 0x364 @ │ │ - ldc2l 2, cr15, [r6, #916] @ 0x394 │ │ - ldc2l 13, cr9, [r6, #256] @ 0x100 │ │ - ldc2l 0, cr6, [r7, #408] @ 0x198 │ │ + ldc2l 3, cr15, [r6, #72] @ 0x48 │ │ + ldc2l 13, cr9, [r6, #436] @ 0x1b4 │ │ + ldc2l 0, cr6, [r7, #588] @ 0x24c │ │ │ │ 024b3dc4 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #300 @ 0x12c │ │ mov r6, r0 │ │ ldr r0, [r0] │ │ @@ -1422550,18 +1422550,18 @@ │ │ ldr r1, [fp, #-64] @ 0xffffffc0 │ │ add r0, r0, r1 │ │ str r0, [r7] │ │ bne 24b42ac │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 6, cr15, [r7, #248] @ 0xf8 │ │ + ldc2l 6, cr15, [r7, #428] @ 0x1ac │ │ ldc2l 9, cr7, [r8, #76] @ 0x4c @ │ │ - ldc2l 0, cr15, [r6, #948] @ 0x3b4 │ │ - ldc2l 5, cr7, [r7, #820] @ 0x334 │ │ + ldc2l 1, cr15, [r6, #104] @ 0x68 │ │ + ldc2l 5, cr7, [r7, #1000] @ 0x3e8 │ │ ldrbeq sp, [r7, #4008] @ 0xfa8 │ │ │ │ 024b4300 : │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr lr, [r2] │ │ mov r3, r0 │ │ @@ -1422854,16 +1422854,16 @@ │ │ bl 270ce50 │ │ ldr r0, [pc, #24] @ 24b4774 │ │ add r0, pc, r0 │ │ bl 270ce70 │ │ mov r0, r4 │ │ pop {r4, r5, r6, r7, r8, sl, fp, lr} │ │ b 270ce40 │ │ - ldc2l 6, cr7, [r7, #912] @ 0x390 │ │ - ldc2l 5, cr11, [r6, #408] @ 0x198 │ │ + ldc2l 7, cr7, [r7, #68] @ 0x44 │ │ + ldc2l 5, cr11, [r6, #588] @ 0x24c │ │ ldc2l 9, cr8, [r9, #26] @ │ │ │ │ 024b4778 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ mov r8, r3 │ │ @@ -1422981,17 +1422981,17 @@ │ │ bl 270cf60 │ │ ldr r0, [pc, #28] @ 24b4964 │ │ add r0, pc, r0 │ │ bl 270ce70 │ │ mov r0, r5 │ │ pop {r4, r5, r6, r7, fp, lr} │ │ b 270ce40 │ │ - ldc2l 12, cr0, [r8, #796] @ 0x31c │ │ - ldc2l 2, cr1, [r7, #708] @ 0x2c4 │ │ - ldc2l 5, cr14, [r6, #804] @ 0x324 │ │ + ldc2l 12, cr0, [r8, #976] @ 0x3d0 │ │ + ldc2l 2, cr1, [r7, #888] @ 0x378 │ │ + ldc2l 5, cr14, [r6, #984] @ 0x3d8 │ │ ldc2l 7, cr8, [r9, #132] @ 0x84 │ │ │ │ 024b4968 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ ldr r4, [fp, #12] │ │ @@ -1423117,21 +1423117,21 @@ │ │ ldr r4, [sp, #16] │ │ ldr r7, [sp, #12] │ │ str sl, [r7] │ │ str r0, [r4] │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 5, cr8, [r9, #948] @ 0x3b4 │ │ - ldc2l 1, cr1, [r7, #228] @ 0xe4 │ │ - ldc2l 4, cr14, [r6, #324] @ 0x144 │ │ + ldc2l 1, cr1, [r7, #408] @ 0x198 │ │ + ldc2l 4, cr14, [r6, #504] @ 0x1f8 │ │ ldc2l 5, cr8, [r9, #676] @ 0x2a4 │ │ ldc2l 5, cr8, [r9, #500] @ 0x1f4 │ │ - ldc2l 15, cr8, [r6, #460] @ 0x1cc │ │ - ldc2l 3, cr14, [r6, #900] @ 0x384 │ │ - ldc2l 11, cr12, [r7, #952] @ 0x3b8 @ │ │ + ldc2l 15, cr8, [r6, #640] @ 0x280 │ │ + ldc2l 4, cr14, [r6, #56] @ 0x38 │ │ + ldc2l 12, cr12, [r7, #108] @ 0x6c │ │ │ │ 024b4b8c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #12 │ │ sub sl, r2, #1 │ │ mov r8, r0 │ │ @@ -1423231,21 +1423231,21 @@ │ │ mov r0, r4 │ │ bl 270ce40 │ │ mov r0, r5 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ b 270ce40 │ │ ldc2l 11, cr4, [r8, #460] @ 0x1cc @ │ │ - ldc2l 15, cr0, [r7, #356] @ 0x164 │ │ - ldc2l 2, cr14, [r6, #452] @ 0x1c4 │ │ + ldc2l 15, cr0, [r7, #536] @ 0x218 │ │ + ldc2l 2, cr14, [r6, #632] @ 0x278 │ │ ldc2l 3, cr8, [r9, #804] @ 0x324 │ │ ldc2l 11, cr4, [r8, #12] @ │ │ - ldc2l 13, cr8, [r6, #588] @ 0x24c │ │ - ldc2l 2, cr14, [r6, #4] │ │ - ldc2l 10, cr12, [r7, #56] @ 0x38 @ │ │ + ldc2l 13, cr8, [r6, #768] @ 0x300 │ │ + ldc2l 2, cr14, [r6, #184] @ 0xb8 │ │ + ldc2l 10, cr12, [r7, #236] @ 0xec @ │ │ │ │ 024b4d4c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #12 │ │ sub sl, r1, #1 │ │ mov r4, r0 │ │ @@ -1423325,20 +1423325,20 @@ │ │ add r0, pc, r0 │ │ bl 270ce70 │ │ mov r0, r4 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ b 270ce40 │ │ ldc2l 14, cr5, [r9, #180] @ 0xb4 │ │ - ldc2l 13, cr0, [r7, #692] @ 0x2b4 │ │ - ldc2l 0, cr14, [r6, #788] @ 0x314 │ │ + ldc2l 13, cr0, [r7, #872] @ 0x368 │ │ + ldc2l 0, cr14, [r6, #968] @ 0x3c8 │ │ ldc2l 2, cr8, [r9, #116] @ 0x74 │ │ ldc2l 13, cr5, [r9, #916] @ 0x394 │ │ - ldc2l 13, cr0, [r7, #732] @ 0x2dc │ │ - ldc2l 8, cr12, [r7, #600] @ 0x258 │ │ + ldc2l 13, cr0, [r7, #912] @ 0x390 │ │ + vcadd.f32 q14, , , #270 │ │ │ │ 024b4eb8 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r5, r1 │ │ mov r4, r0 │ │ bl 2701990 │ │ @@ -1423368,17 +1423368,17 @@ │ │ bl 270cf60 │ │ ldr r0, [pc, #28] @ 24b4f50 │ │ add r0, pc, r0 │ │ bl 270ce70 │ │ mov r0, r5 │ │ pop {r4, r5, fp, lr} │ │ b 270ce40 │ │ - vcadd.f32 d28, d7, d28, #270 │ │ - ldc2l 13, cr10, [r6, #824] @ 0x338 │ │ - ldc2l 15, cr13, [r6, #884] @ 0x374 │ │ + ldc2l 8, cr12, [r7, #356] @ 0x164 │ │ + ldc2l 13, cr10, [r6, #1004] @ 0x3ec │ │ + ldc2l 0, cr14, [r6, #40] @ 0x28 │ │ ldc2l 7, cr14, [r5, #484] @ 0x1e4 │ │ │ │ 024b4f54 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ add r5, r0, r1 │ │ mov r8, r2 │ │ @@ -1423546,15 +1423546,15 @@ │ │ mov r2, r6 │ │ bl 27059b0 │ │ mov r1, #0 │ │ str r0, [r8] │ │ strb r1, [r0, r6] │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ ldc2l 13, cr15, [r8, #116] @ 0x74 │ │ - ldc2l 11, cr10, [r6, #120] @ 0x78 @ │ │ + ldc2l 11, cr10, [r6, #300] @ 0x12c @ │ │ ldc2l 14, cr7, [r9, #788] @ 0x314 │ │ │ │ 024b51f4 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ mov r8, r3 │ │ @@ -1423687,16 +1423687,16 @@ │ │ bl 270ce50 │ │ ldr r0, [pc, #24] @ 24b5418 │ │ add r0, pc, r0 │ │ bl 270ce70 │ │ mov r0, r4 │ │ pop {r4, sl, fp, lr} │ │ b 270ce40 │ │ - ldc2l 3, cr12, [r7, #352] @ 0x160 │ │ - vcadd.f32 q13, q11, q1, #270 │ │ + ldc2l 3, cr12, [r7, #532] @ 0x214 │ │ + vcadd.f32 q13, q11, , #270 │ │ ldc2l 12, cr7, [r9, #420] @ 0x1a4 │ │ │ │ 024b541c : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [r0] │ │ @@ -1423923,71 +1423923,71 @@ │ │ mov r0, r4 │ │ mov r1, #23 │ │ bl 270da10 │ │ mov r0, r5 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ b 24b73e4 │ │ - ldc2l 0, cr8, [r7, #736] @ 0x2e0 │ │ - ldc2l 0, cr8, [r7, #592] @ 0x250 │ │ + ldc2l 0, cr8, [r7, #916] @ 0x394 │ │ + ldc2l 0, cr8, [r7, #772] @ 0x304 │ │ ldc2l 0, cr4, [r8, #592] @ 0x250 │ │ - ldc2l 4, cr0, [r7, #960] @ 0x3c0 │ │ - ldc2l 1, cr6, [r6, #76] @ 0x4c │ │ + ldc2l 5, cr0, [r7, #116] @ 0x74 │ │ + ldc2l 1, cr6, [r6, #256] @ 0x100 │ │ ldc2l 5, cr4, [r6, #688] @ 0x2b0 │ │ - ldc2l 10, cr13, [r7, #732] @ 0x2dc @ │ │ + ldc2l 10, cr13, [r7, #912] @ 0x390 @ │ │ ldc2l 5, cr3, [r9, #944] @ 0x3b0 │ │ - ldc2l 3, cr4, [r7, #92] @ 0x5c │ │ + ldc2l 3, cr4, [r7, #272] @ 0x110 │ │ ldc2l 15, cr8, [r9, #840] @ 0x348 │ │ ldc2l 13, cr10, [r9, #752] @ 0x2f0 │ │ ldc2l 13, cr3, [r8, #412] @ 0x19c │ │ - ldc2l 12, cr1, [r8, #676] @ 0x2a4 │ │ - ldc2l 9, cr13, [r7, #144] @ 0x90 @ │ │ + ldc2l 12, cr1, [r8, #856] @ 0x358 │ │ + ldc2l 9, cr13, [r7, #234] @ 0xea @ │ │ ldc2l 15, cr15, [r5, #344] @ 0x158 │ │ - ldc2l 10, cr15, [r7, #528] @ 0x210 @ │ │ + ldc2l 10, cr15, [r7, #708] @ 0x2c4 @ │ │ ldc2l 0, cr13, [r8, #76] @ 0x4c │ │ - ldc2l 8, cr13, [r7, #480] @ 0x1e0 │ │ - ldc2l 14, cr5, [r6, #152] @ 0x98 │ │ + vcadd.f32 d29, d23, d21, #270 │ │ + ldc2l 14, cr5, [r6, #332] @ 0x14c │ │ ldc2l 9, cr1, [r9, #322] @ 0x142 @ │ │ - ldc2l 9, cr15, [r7, #252] @ 0xfc @ │ │ - ldc2l 9, cr15, [r7, #170] @ 0xaa @ │ │ - ldc2l 11, cr9, [r7, #732] @ 0x2dc @ │ │ - ldc2l 1, cr6, [r7, #72] @ 0x48 │ │ + ldc2l 9, cr15, [r7, #342] @ 0x156 @ │ │ + ldc2l 9, cr15, [r7, #260] @ 0x104 @ │ │ + ldc2l 11, cr9, [r7, #912] @ 0x390 @ │ │ + ldc2l 1, cr6, [r7, #252] @ 0xfc │ │ ldc2l 11, cr7, [r8, #32] @ │ │ - ldc2l 14, cr13, [r6, #992] @ 0x3e0 │ │ + ldc2l 15, cr13, [r6, #148] @ 0x94 │ │ ldc2l 10, cr10, [r9, #424] @ 0x1a8 @ │ │ - ldc2l 15, cr9, [r6, #132] @ 0x84 │ │ + ldc2l 15, cr9, [r6, #312] @ 0x138 │ │ ldc2l 3, cr2, [r6, #136] @ 0x88 │ │ - ldc2l 11, cr5, [r6, #952] @ 0x3b8 @ │ │ + ldc2l 12, cr5, [r6, #108] @ 0x6c │ │ ldc2l 7, cr1, [r9, #416] @ 0x1a0 │ │ ldc2l 7, cr11, [r8, #308] @ 0x134 │ │ ldc2l 15, cr3, [r6, #1012] @ 0x3f4 │ │ - ldc2l 11, cr7, [r6, #852] @ 0x354 @ │ │ - ldc2l 14, cr11, [r6, #864] @ 0x360 │ │ - ldc2l 9, cr9, [r7, #50] @ 0x32 @ │ │ + ldc2l 12, cr7, [r6, #8] │ │ + ldc2l 15, cr11, [r6, #20] │ │ + ldc2l 9, cr9, [r7, #140] @ 0x8c @ │ │ ldc2l 15, cr3, [r6, #220] @ 0xdc │ │ ldc2l 6, cr11, [r8, #100] @ 0x64 │ │ ldc2l 15, cr2, [r9, #608] @ 0x260 │ │ - ldc2l 6, cr11, [r7, #980] @ 0x3d4 │ │ + ldc2l 7, cr11, [r7, #136] @ 0x88 │ │ ldc2l 14, cr14, [r8, #124] @ 0x7c │ │ ldc2l 7, cr3, [r8, #296] @ 0x128 │ │ - ldc2l 13, cr5, [r7, #236] @ 0xec │ │ + ldc2l 13, cr5, [r7, #416] @ 0x1a0 │ │ ldc2l 6, cr3, [r8, #976] @ 0x3d0 │ │ - ldc2l 6, cr7, [r7, #720] @ 0x2d0 │ │ - ldc2l 2, cr13, [r7, #804] @ 0x324 │ │ - ldc2l 12, cr11, [r6, #460] @ 0x1cc │ │ - ldc2l 4, cr15, [r7, #84] @ 0x54 │ │ - ldc2l 2, cr13, [r7, #188] @ 0xbc │ │ - ldc2l 5, cr7, [r7, #764] @ 0x2fc │ │ + ldc2l 6, cr7, [r7, #900] @ 0x384 │ │ + ldc2l 2, cr13, [r7, #984] @ 0x3d8 │ │ + ldc2l 12, cr11, [r6, #640] @ 0x280 │ │ + ldc2l 4, cr15, [r7, #264] @ 0x108 │ │ + ldc2l 2, cr13, [r7, #368] @ 0x170 │ │ + ldc2l 5, cr7, [r7, #944] @ 0x3b0 │ │ ldc2l 15, cr12, [r8, #332] @ 0x14c │ │ ldc2l 3, cr1, [r9, #212] @ 0xd4 │ │ ldc2l 5, cr10, [r9, #148] @ 0x94 │ │ ldc2l 7, cr15, [r5, #376] @ 0x178 │ │ ldc2l 3, cr13, [r5, #308] @ 0x134 │ │ - ldc2l 9, cr9, [r6, #256] @ 0x100 @ │ │ - ldc2l 4, cr7, [r7, #348] @ 0x15c │ │ + ldc2l 9, cr9, [r6, #346] @ 0x15a @ │ │ + ldc2l 4, cr7, [r7, #528] @ 0x210 │ │ mov r4, r2 │ │ add r2, fp, #8 │ │ str r1, [sp, #36] @ 0x24 │ │ sub r6, fp, #36 @ 0x24 │ │ ldm r2, {r0, r1, r2} │ │ sub r7, r2, #4 │ │ sub sl, r1, #4 │ │ @@ -1425740,82 +1425740,82 @@ │ │ blt 24b7378 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 12, cr6, [r9, #508] @ 0x1fc │ │ ldc2l 4, cr9, [r8, #60] @ 0x3c │ │ ldc2l 12, cr6, [r9, #152] @ 0x98 │ │ - ldc2l 8, cr15, [r6, #600] @ 0x258 │ │ - ldc2l 5, cr5, [r6, #476] @ 0x1dc │ │ - ldc2l 9, cr5, [r7, #98] @ 0x62 @ │ │ + vcadd.f32 , q11, , #270 │ │ + ldc2l 5, cr5, [r6, #656] @ 0x290 │ │ + ldc2l 9, cr5, [r7, #188] @ 0xbc @ │ │ ldc2l 4, cr8, [r9, #848] @ 0x350 │ │ ldc2l 9, cr14, [r8, #144] @ 0x90 @ │ │ - ldc2l 6, cr13, [r6, #892] @ 0x37c │ │ - ldc2l 0, cr15, [r7, #252] @ 0xfc │ │ - ldc2l 8, cr5, [r7, #224] @ 0xe0 │ │ + ldc2l 7, cr13, [r6, #48] @ 0x30 │ │ + ldc2l 0, cr15, [r7, #432] @ 0x1b0 │ │ + vcadd.f32 , , , #270 │ │ ldc2l 15, cr10, [r8, #848] @ 0x350 │ │ ldc2l 15, cr0, [r9, #572] @ 0x23c │ │ - ldc2l 7, cr5, [r7, #676] @ 0x2a4 │ │ + ldc2l 7, cr5, [r7, #856] @ 0x358 │ │ ldc2l 1, cr3, [r8, #280] @ 0x118 │ │ ldc2l 8, cr2, [r9, #724] @ 0x2d4 │ │ ldc2l 0, cr5, [r8, #32] │ │ - ldc2l 3, cr7, [r6, #552] @ 0x228 │ │ + ldc2l 3, cr7, [r6, #732] @ 0x2dc │ │ ldc2l 0, cr10, [r9, #544] @ 0x220 │ │ - ldc2l 6, cr5, [r7, #496] @ 0x1f0 │ │ - ldc2l 2, cr5, [r6, #268] @ 0x10c │ │ - ldc2l 12, cr12, [r7, #128] @ 0x80 │ │ - ldc2l 4, cr15, [r6, #792] @ 0x318 │ │ + ldc2l 6, cr5, [r7, #676] @ 0x2a4 │ │ + ldc2l 2, cr5, [r6, #448] @ 0x1c0 │ │ + ldc2l 12, cr12, [r7, #308] @ 0x134 │ │ + ldc2l 4, cr15, [r6, #972] @ 0x3cc │ │ ldc2l 1, cr8, [r9, #432] @ 0x1b0 │ │ vcadd.f32 , q3, , #270 │ │ ldc2l 6, cr2, [r9, #740] @ 0x2e4 │ │ - ldc2l 4, cr11, [r6, #976] @ 0x3d0 │ │ + ldc2l 5, cr11, [r6, #132] @ 0x84 │ │ ldc2l 14, cr6, [r8, #892] @ 0x37c │ │ ldc2l 14, cr9, [r9, #524] @ 0x20c │ │ ldc2l 4, cr14, [r8, #852] @ 0x354 │ │ ldc2l 14, cr8, [r8, #156] @ 0x9c │ │ ldc2l 1, cr4, [r9, #964] @ 0x3c4 │ │ ldc2l 7, cr12, [r8, #344] @ 0x158 │ │ ldc2l 6, cr1, [r6, #524] @ 0x20c │ │ ldc2l 11, cr10, [r8, #104] @ 0x68 @ │ │ - ldc2l 1, cr1, [r7, #420] @ 0x1a4 │ │ - ldc2l 14, cr4, [r6, #976] @ 0x3d0 │ │ + ldc2l 1, cr1, [r7, #600] @ 0x258 │ │ + ldc2l 15, cr4, [r6, #132] @ 0x84 │ │ ldc2l 5, cr1, [r6, #768] @ 0x300 │ │ - ldc2l 1, cr9, [r6, #288] @ 0x120 │ │ + ldc2l 1, cr9, [r6, #468] @ 0x1d4 │ │ ldc2l 12, cr2, [r8, #140] @ 0x8c │ │ ldc2l 0, cr4, [r9, #120] @ 0x78 │ │ ldc2l 10, cr4, [r8, #900] @ 0x384 @ │ │ ldc2l 2, cr3, [r6, #340] @ 0x154 │ │ - ldc2l 0, cr3, [r7, #216] @ 0xd8 │ │ + ldc2l 0, cr3, [r7, #396] @ 0x18c │ │ ldc2l 9, cr12, [r5, #370] @ 0x172 @ │ │ - ldc2l 1, cr5, [r7, #72] @ 0x48 │ │ + ldc2l 1, cr5, [r7, #252] @ 0xfc │ │ ldc2l 10, cr2, [r8, #636] @ 0x27c @ │ │ - ldc2l 10, cr6, [r7, #372] @ 0x174 @ │ │ + ldc2l 10, cr6, [r7, #552] @ 0x228 @ │ │ ldc2l 8, cr12, [r5, #856] @ 0x358 │ │ ldc2l 10, cr8, [r8, #92] @ 0x5c @ │ │ ldc2l 9, cr6, [r8, #462] @ 0x1ce @ │ │ - ldc2l 13, cr0, [r7, #980] @ 0x3d4 │ │ - vcadd.f32 d16, d24, d2, #270 │ │ + ldc2l 14, cr0, [r7, #136] @ 0x88 │ │ + vcadd.f32 d16, d24, d31, #270 │ │ ldc2l 7, cr12, [r5, #692] @ 0x2b4 │ │ - ldc2l 11, cr4, [r6, #52] @ 0x34 @ │ │ - ldc2l 14, cr4, [r7, #864] @ 0x360 │ │ + ldc2l 11, cr4, [r6, #232] @ 0xe8 @ │ │ + ldc2l 15, cr4, [r7, #20] │ │ ldc2l 0, cr2, [r9, #64] @ 0x40 │ │ ldc2l 12, cr3, [r9, #408] @ 0x198 │ │ ldc2l 1, cr1, [r6, #216] @ 0xd8 │ │ - ldc2l 7, cr0, [r8, #48] @ 0x30 │ │ + ldc2l 7, cr0, [r8, #228] @ 0xe4 │ │ ldc2l 11, cr3, [r9, #812] @ 0x32c @ │ │ ldc2l 13, cr13, [r8, #944] @ 0x3b0 │ │ - ldc2l 12, cr14, [r6, #200] @ 0xc8 │ │ + ldc2l 12, cr14, [r6, #380] @ 0x17c │ │ ldc2l 7, cr8, [r8, #76] @ 0x4c │ │ - ldc2l 4, cr14, [r7, #600] @ 0x258 │ │ + ldc2l 4, cr14, [r7, #780] @ 0x30c │ │ ldc2l 0, cr12, [r8, #260] @ 0x104 │ │ - ldc2l 6, cr6, [r7, #252] @ 0xfc │ │ + ldc2l 6, cr6, [r7, #432] @ 0x1b0 │ │ ldc2l 10, cr3, [r9, #324] @ 0x144 @ │ │ - ldc2l 11, cr10, [r6, #876] @ 0x36c @ │ │ + ldc2l 12, cr10, [r6, #32] │ │ ldc2l 7, cr7, [r9, #528] @ 0x210 │ │ - ldc2l 5, cr8, [r7, #808] @ 0x328 │ │ + ldc2l 5, cr8, [r7, #988] @ 0x3dc │ │ eoreq r3, sl, ip, lsr #32 │ │ │ │ 024b7510 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d13} │ │ @@ -1426886,66 +1426886,66 @@ │ │ mov r0, r6 │ │ mov r2, sl │ │ movw r3, #514 @ 0x202 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 24b82dc │ │ ldc2l 10, cr5, [r8, #280] @ 0x118 @ │ │ - ldc2l 7, cr11, [r6, #788] @ 0x314 │ │ + ldc2l 7, cr11, [r6, #968] @ 0x3c8 │ │ ldc2l 10, cr13, [r5, #780] @ 0x30c @ │ │ ldc2l 7, cr5, [r8, #744] @ 0x2e8 │ │ - ldc2l 5, cr11, [r6, #228] @ 0xe4 │ │ - ldc2l 13, cr3, [r7, #288] @ 0x120 │ │ - ldc2l 13, cr11, [r7, #384] @ 0x180 │ │ + ldc2l 5, cr11, [r6, #408] @ 0x198 │ │ + ldc2l 13, cr3, [r7, #468] @ 0x1d4 │ │ + ldc2l 13, cr11, [r7, #564] @ 0x234 │ │ ldc2l 1, cr13, [r8, #808] @ 0x328 │ │ - ldc2l 11, cr3, [r7, #544] @ 0x220 @ │ │ - ldc2l 11, cr11, [r7, #640] @ 0x280 @ │ │ - ldc2l 11, cr3, [r7, #320] @ 0x140 @ │ │ - ldc2l 11, cr11, [r7, #416] @ 0x1a0 @ │ │ - ldc2l 1, cr3, [r7, #592] @ 0x250 │ │ - ldc2l 1, cr11, [r7, #688] @ 0x2b0 │ │ + ldc2l 11, cr3, [r7, #724] @ 0x2d4 @ │ │ + ldc2l 11, cr11, [r7, #820] @ 0x334 @ │ │ + ldc2l 11, cr3, [r7, #500] @ 0x1f4 @ │ │ + ldc2l 11, cr11, [r7, #596] @ 0x254 @ │ │ + ldc2l 1, cr3, [r7, #772] @ 0x304 │ │ + ldc2l 1, cr11, [r7, #868] @ 0x364 │ │ ldc2l 6, cr12, [r8, #760] @ 0x2f8 │ │ eoreq r1, sl, ip, asr #30 │ │ - ldc2l 14, cr2, [r7, #928] @ 0x3a0 │ │ - ldc2l 11, cr3, [r7, #32] @ │ │ - ldc2l 11, cr11, [r7, #128] @ 0x80 @ │ │ + ldc2l 15, cr2, [r7, #84] @ 0x54 │ │ + ldc2l 11, cr3, [r7, #212] @ 0xd4 @ │ │ + ldc2l 11, cr11, [r7, #308] @ 0x134 @ │ │ ldc2l 7, cr7, [r8, #248] @ 0xf8 │ │ - ldc2l 9, cr11, [r7, #80] @ 0x50 @ │ │ + ldc2l 9, cr11, [r7, #170] @ 0xaa @ │ │ ldc2l 5, cr7, [r8, #424] @ 0x1a8 │ │ - ldc2l 7, cr11, [r7, #336] @ 0x150 │ │ + ldc2l 7, cr11, [r7, #516] @ 0x204 │ │ ldc2l 5, cr7, [r8, #216] @ 0xd8 │ │ ldc2l 4, cr7, [r8, #1016] @ 0x3f8 │ │ - ldc2l 6, cr11, [r7, #928] @ 0x3a0 │ │ + ldc2l 7, cr11, [r7, #84] @ 0x54 │ │ ldc2l 4, cr7, [r8, #792] @ 0x318 │ │ - ldc2l 6, cr11, [r7, #704] @ 0x2c0 │ │ + ldc2l 6, cr11, [r7, #884] @ 0x374 │ │ ldc2l 3, cr7, [r8, #792] @ 0x318 │ │ - ldc2l 5, cr11, [r7, #704] @ 0x2c0 │ │ + ldc2l 5, cr11, [r7, #884] @ 0x374 │ │ ldc2l 3, cr7, [r8, #136] @ 0x88 │ │ - ldc2l 5, cr11, [r7, #48] @ 0x30 │ │ + ldc2l 5, cr11, [r7, #228] @ 0xe4 │ │ ldc2l 2, cr7, [r8, #392] @ 0x188 │ │ - ldc2l 4, cr11, [r7, #304] @ 0x130 │ │ + ldc2l 4, cr11, [r7, #484] @ 0x1e4 │ │ ldc2l 1, cr7, [r8, #1016] @ 0x3f8 │ │ - ldc2l 3, cr11, [r7, #928] @ 0x3a0 │ │ + ldc2l 4, cr11, [r7, #84] @ 0x54 │ │ ldc2l 1, cr7, [r8, #808] @ 0x328 │ │ - ldc2l 3, cr11, [r7, #720] @ 0x2d0 │ │ + ldc2l 3, cr11, [r7, #900] @ 0x384 │ │ ldc2l 1, cr7, [r8, #600] @ 0x258 │ │ - ldc2l 3, cr11, [r7, #512] @ 0x200 │ │ + ldc2l 3, cr11, [r7, #692] @ 0x2b4 │ │ ldc2l 1, cr7, [r8, #392] @ 0x188 │ │ - ldc2l 3, cr11, [r7, #304] @ 0x130 │ │ + ldc2l 3, cr11, [r7, #484] @ 0x1e4 │ │ ldc2l 1, cr7, [r8, #184] @ 0xb8 │ │ - ldc2l 3, cr11, [r7, #96] @ 0x60 │ │ + ldc2l 3, cr11, [r7, #276] @ 0x114 │ │ ldc2l 0, cr7, [r8, #984] @ 0x3d8 │ │ - ldc2l 2, cr11, [r7, #896] @ 0x380 │ │ - ldc2l 10, cr3, [r7, #416] @ 0x1a0 @ │ │ - ldc2l 10, cr11, [r7, #512] @ 0x200 @ │ │ + ldc2l 3, cr11, [r7, #52] @ 0x34 │ │ + ldc2l 10, cr3, [r7, #596] @ 0x254 @ │ │ + ldc2l 10, cr11, [r7, #692] @ 0x2b4 @ │ │ ldc2l 7, cr8, [r9, #960] @ 0x3c0 │ │ ldc2l 0, cr7, [r8, #216] @ 0xd8 │ │ - ldc2l 2, cr11, [r7, #128] @ 0x80 │ │ + ldc2l 2, cr11, [r7, #308] @ 0x134 │ │ ldc2l 7, cr12, [r8, #40] @ 0x28 │ │ - ldc2l 1, cr11, [r7, #960] @ 0x3c0 │ │ + ldc2l 2, cr11, [r7, #116] @ 0x74 │ │ ldc2l 7, cr13, [r8, #572] @ 0x23c │ │ │ │ 024b86b0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #316 @ 0x13c │ │ ldr r9, [fp, #8] │ │ @@ -1427248,21 +1427248,21 @@ │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 9, cr0, [r9, #4] @ │ │ ldrbeq r9, [r7, #2528] @ 0x9e0 │ │ eoreq r1, sl, ip, lsr ip │ │ ldrbeq r9, [r7, #2508] @ 0x9cc │ │ eoreq r1, sl, r8, lsl #21 │ │ eoreq r1, sl, r8, lsr #23 │ │ - ldc2l 13, cr12, [r6, #176] @ 0xb0 │ │ + ldc2l 13, cr12, [r6, #356] @ 0x164 │ │ ldrdeq r1, [sl], -r0 @ │ │ eoreq r1, sl, r8, ror r8 │ │ - ldc2l 13, cr6, [r7, #880] @ 0x370 │ │ - ldc2l 3, cr10, [r6, #1012] @ 0x3f4 │ │ + ldc2l 14, cr6, [r7, #36] @ 0x24 │ │ + ldc2l 4, cr10, [r6, #168] @ 0xa8 │ │ eoreq r1, sl, r4, lsl r8 │ │ - ldc2l 5, cr10, [r7, #968] @ 0x3c8 │ │ + ldc2l 6, cr10, [r7, #124] @ 0x7c │ │ eoreq r1, sl, r8, lsr #17 │ │ ldc2l 4, cr0, [r9, #632] @ 0x278 │ │ │ │ 024b8ba0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ @@ -1428264,15 +1428264,15 @@ │ │ add r1, pc, r1 │ │ bl 270da60 │ │ ldr r0, [pc, #3116] @ 24ba774 │ │ add r0, pc, r0 │ │ mov r1, #20 │ │ bl 270da10 │ │ b 24b966c │ │ - ldc2l 8, cr10, [r7, #632] @ 0x278 │ │ + vcadd.f32 q13, , , #270 │ │ ldr r1, [pc, #3096] @ 24ba778 │ │ add lr, sp, #1536 @ 0x600 │ │ add r0, lr, #11 │ │ mov r2, #80 @ 0x50 │ │ add r1, pc, r1 │ │ mov r3, #10 │ │ sub r5, fp, #1120 @ 0x460 │ │ @@ -1428304,22 +1428304,22 @@ │ │ bl 270da00 │ │ ldr r4, [pc, #2980] @ 24ba788 │ │ add lr, sp, #1536 @ 0x600 │ │ add r1, lr, #11 │ │ add r4, pc, r4 │ │ b 24b9a5c │ │ ldrbeq r9, [r7, #1544] @ 0x608 │ │ - ldc2l 11, cr12, [r6, #352] @ 0x160 @ │ │ + ldc2l 11, cr12, [r6, #532] @ 0x214 @ │ │ ldrbeq r9, [r7, #2352] @ 0x930 │ │ ldc2l 11, cr12, [r5, #220] @ 0xdc @ │ │ ldrbeq r9, [r7, #1488] @ 0x5d0 │ │ eoreq r1, sl, fp, ror r7 │ │ eoreq r1, sl, r0, lsl #15 │ │ - ldc2l 0, cr13, [r6, #992] @ 0x3e0 │ │ - ldc2l 14, cr12, [r6, #576] @ 0x240 │ │ + ldc2l 1, cr13, [r6, #148] @ 0x94 │ │ + ldc2l 14, cr12, [r6, #756] @ 0x2f4 │ │ ldrbeq r9, [r7, #2152] @ 0x868 │ │ ldr r0, [pc, #2924] @ 24ba78c │ │ add lr, sp, #1024 @ 0x400 │ │ add r1, lr, #120 @ 0x78 │ │ add r0, pc, r0 │ │ bl 270d1a0 │ │ add r0, sp, #528 @ 0x210 │ │ @@ -1428349,25 +1428349,25 @@ │ │ str r0, [sp, #56] @ 0x38 │ │ mov r0, #1 │ │ vldr d8, [pc, #852] @ 24b9ff0 │ │ str r2, [sp, #40] @ 0x28 │ │ str r1, [sp, #36] @ 0x24 │ │ str r0, [fp, #-1076] @ 0xfffffbcc │ │ b 24b9d0c │ │ - ldc2l 6, cr10, [r7, #936] @ 0x3a8 │ │ - ldc2l 12, cr2, [r6, #896] @ 0x380 │ │ - ldc2l 13, cr12, [r6, #920] @ 0x398 │ │ + ldc2l 7, cr10, [r7, #92] @ 0x5c │ │ + ldc2l 13, cr2, [r6, #52] @ 0x34 │ │ + ldc2l 14, cr12, [r6, #76] @ 0x4c │ │ ldrbeq r9, [r7, #1424] @ 0x590 │ │ ldc2l 6, cr10, [r5, #592] @ 0x250 │ │ - ldc2l 6, cr10, [r7, #248] @ 0xf8 │ │ + ldc2l 6, cr10, [r7, #428] @ 0x1ac │ │ ldc2l 6, cr10, [r5, #336] @ 0x150 │ │ ldc2l 10, cr5, [r9, #520] @ 0x208 @ │ │ ldrbeq r9, [r7, #1764] @ 0x6e4 │ │ ldc2l 4, cr8, [r8, #556] @ 0x22c │ │ - ldc2l 5, cr10, [r7, #584] @ 0x248 │ │ + ldc2l 5, cr10, [r7, #764] @ 0x2fc │ │ ldc2l 4, cr8, [r8, #300] @ 0x12c │ │ ldc2l 5, cr10, [r5, #588] @ 0x24c │ │ add lr, sp, #1024 @ 0x400 │ │ add r0, lr, #120 @ 0x78 │ │ add r2, r0, r1, lsl #3 │ │ ldr r1, [pc, #2720] @ 24ba790 │ │ sub r0, fp, #1488 @ 0x5d0 │ │ @@ -1428466,15 +1428466,15 @@ │ │ bhi 24b9e80 │ │ sub r0, fp, #484 @ 0x1e4 │ │ str r6, [r0, r1, lsl #2] │ │ mov r6, r0 │ │ b 24b9ed0 │ │ ldrbeq r9, [r7, #952] @ 0x3b8 │ │ ldc2l 6, cr4, [r8, #716] @ 0x2cc │ │ - ldc2l 4, cr10, [r7, #920] @ 0x398 │ │ + ldc2l 5, cr10, [r7, #76] @ 0x4c │ │ ldr r0, [pc, #3804] @ 24bad64 │ │ movw r3, #1155 @ 0x483 │ │ ldr r2, [pc, #3800] @ 24bad68 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [fp, #-1076] @ 0xfffffbcc │ │ @@ -1428497,19 +1428497,19 @@ │ │ ldr r0, [fp, #-1076] @ 0xfffffbcc │ │ sub r6, r0, #1 │ │ cmp r6, #2 │ │ bcs 24b9f10 │ │ mov r1, r6 │ │ b 24b9f5c │ │ ldc2l 6, cr4, [r8, #460] @ 0x1cc │ │ - ldc2l 11, cr0, [r7, #20] @ │ │ + ldc2l 11, cr0, [r7, #200] @ 0xc8 @ │ │ ldrbeq r9, [r7, #972] @ 0x3cc │ │ - ldc2l 12, cr6, [r6, #292] @ 0x124 │ │ - ldc2l 4, cr10, [r7, #232] @ 0xe8 │ │ - ldc2l 12, cr6, [r6, #36] @ 0x24 │ │ + ldc2l 12, cr6, [r6, #472] @ 0x1d8 │ │ + ldc2l 4, cr10, [r7, #412] @ 0x19c │ │ + ldc2l 12, cr6, [r6, #216] @ 0xd8 │ │ ldc2l 11, cr1, [r9, #764] @ 0x2fc @ │ │ ldr r0, [pc, #3676] @ 24bad74 │ │ mov r1, r6 │ │ ldr r2, [pc, #3672] @ 24bad78 │ │ movw r3, #1187 @ 0x4a3 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1428555,17 +1428555,17 @@ │ │ cmp r6, #2 │ │ bcs 24b9ffc │ │ ldr r4, [pc, #3512] @ 24bad8c │ │ mov r1, r6 │ │ add r4, pc, r4 │ │ b 24ba048 │ │ ldrbeq r9, [r7, #992] @ 0x3e0 │ │ - ldc2l 10, cr0, [r7, #80] @ 0x50 @ │ │ - ldc2l 3, cr10, [r7, #568] @ 0x238 │ │ - ldc2l 9, cr0, [r7, #424] @ 0x1a8 @ │ │ + ldc2l 10, cr0, [r7, #260] @ 0x104 @ │ │ + ldc2l 3, cr10, [r7, #748] @ 0x2ec │ │ + ldc2l 10, cr0, [r7, #4] @ │ │ ldc2l 2, cr8, [r8, #184] @ 0xb8 │ │ andeq r0, r0, r0 │ │ cdpcc 0, 4, cr0, cr0, cr0, {0} │ │ ldrbeq r9, [r7, #948] @ 0x3b4 │ │ ldr r4, [pc, #3468] @ 24bad90 │ │ mov r1, r6 │ │ ldr r2, [pc, #3464] @ 24bad94 │ │ @@ -1428603,46 +1428603,46 @@ │ │ ldr r0, [fp, #-1076] @ 0xfffffbcc │ │ sub r6, r0, #1 │ │ cmp r6, #2 │ │ bcs 24ba128 │ │ mov r1, r6 │ │ b 24ba16c │ │ ldc2l 14, cr3, [r9, #252] @ 0xfc │ │ - ldc2l 2, cr10, [r7, #904] @ 0x388 │ │ + ldc2l 3, cr10, [r7, #60] @ 0x3c │ │ ldc2l 13, cr3, [r9, #1020] @ 0x3fc │ │ ldc2l 2, cr10, [r5, #936] @ 0x3a8 │ │ ldrbeq r9, [r7, #584] @ 0x248 │ │ - vcadd.f32 q8, , , #270 │ │ - ldc2l 2, cr10, [r7, #216] @ 0xd8 │ │ - vcadd.f32 d16, d23, d3, #270 │ │ + ldc2l 8, cr0, [r7, #960] @ 0x3c0 │ │ + ldc2l 2, cr10, [r7, #396] @ 0x18c │ │ + ldc2l 8, cr0, [r7, #704] @ 0x2c0 │ │ ldc2l 0, cr8, [r8, #884] @ 0x374 │ │ ldrbeq r9, [r7, #348] @ 0x15c │ │ - ldc2l 9, cr1, [r7, #112] @ 0x70 @ │ │ - ldc2l 1, cr10, [r7, #552] @ 0x228 │ │ - ldc2l 8, cr1, [r7, #992] @ 0x3e0 │ │ - ldc2l 9, cr2, [r7, #426] @ 0x1aa @ │ │ + ldc2l 9, cr1, [r7, #202] @ 0xca @ │ │ + ldc2l 1, cr10, [r7, #732] @ 0x2dc │ │ + ldc2l 9, cr1, [r7, #74] @ 0x4a @ │ │ + ldc2l 10, cr2, [r7, #8] @ │ │ ldrbeq r8, [r7, #3952] @ 0xf70 │ │ ldc2l 7, cr0, [r6, #604] @ 0x25c │ │ - ldc2l 0, cr10, [r7, #888] @ 0x378 │ │ + ldc2l 1, cr10, [r7, #44] @ 0x2c │ │ ldc2l 7, cr0, [r6, #348] @ 0x15c │ │ - ldc2l 9, cr2, [r7, #94] @ 0x5e @ │ │ + ldc2l 9, cr2, [r7, #184] @ 0xb8 @ │ │ ldrbeq r8, [r7, #3908] @ 0xf44 │ │ - vcadd.f32 q11, q3, q5, #270 │ │ - ldc2l 0, cr10, [r7, #200] @ 0xc8 │ │ - vcadd.f32 d22, d6, d10, #270 │ │ - ldc2l 7, cr12, [r6, #212] @ 0xd4 │ │ + ldc2l 8, cr6, [r6, #476] @ 0x1dc │ │ + ldc2l 0, cr10, [r7, #380] @ 0x17c │ │ + ldc2l 8, cr6, [r6, #220] @ 0xdc │ │ + ldc2l 7, cr12, [r6, #392] @ 0x188 │ │ ldrbeq r9, [r7, #152] @ 0x98 │ │ ldc2l 1, cr7, [r9, #668] @ 0x29c │ │ - ldc2l 15, cr9, [r7, #552] @ 0x228 │ │ + ldc2l 15, cr9, [r7, #732] @ 0x2dc │ │ ldc2l 1, cr7, [r9, #428] @ 0x1ac │ │ ldc2l 1, cr4, [r8, #4] │ │ ldrbeq r8, [r7, #3956] @ 0xf74 │ │ - ldc2l 15, cr9, [r7, #8] │ │ - ldc2l 6, cr12, [r6, #176] @ 0xb0 │ │ - ldc2l 5, cr14, [r6, #852] @ 0x354 │ │ + ldc2l 15, cr9, [r7, #188] @ 0xbc │ │ + ldc2l 6, cr12, [r6, #356] @ 0x164 │ │ + ldc2l 6, cr14, [r6, #8] │ │ ldrbeq r8, [r7, #3292] @ 0xcdc │ │ strhteq r0, [sl], -r4 │ │ ldr r2, [pc, #3912] @ 24bb078 │ │ mov r0, r4 │ │ mov r1, r6 │ │ movw r3, #1196 @ 0x4ac │ │ add r2, pc, r2 │ │ @@ -1428897,18 +1428897,18 @@ │ │ mov r0, r5 │ │ mov r1, r7 │ │ mov r2, r6 │ │ str r4, [sp] │ │ bl 270f9e0 │ │ b 24bb148 │ │ ldc2l 8, cr14, [r5, #116] @ 0x74 │ │ - ldc2l 0, cr4, [r7, #640] @ 0x280 │ │ + ldc2l 0, cr4, [r7, #820] @ 0x334 │ │ eoreq r0, sl, r4, lsr #27 │ │ - ldc2l 14, cr9, [r7, #72] @ 0x48 │ │ - ldc2l 0, cr4, [r7, #312] @ 0x138 │ │ + ldc2l 14, cr9, [r7, #252] @ 0xfc │ │ + ldc2l 0, cr4, [r7, #492] @ 0x1ec │ │ ldc2l 5, cr11, [r8, #328] @ 0x148 │ │ eoreq r0, sl, ip, lsl #26 │ │ cmp r1, #2 │ │ bcc 24ba574 │ │ ldr r0, [pc, #3948] @ 24bb4cc │ │ movw r3, #1206 @ 0x4b6 │ │ ldr r2, [pc, #3944] @ 24bb4d0 │ │ @@ -1429032,32 +1429032,32 @@ │ │ ldc2l 12, cr6, [r9, #368] @ 0x170 │ │ eoreq r0, sl, r8, ror sl │ │ ldc2l 11, cr1, [r8, #692] @ 0x2b4 @ │ │ ldrbeq r8, [r7, #2112] @ 0x840 │ │ ldrbeq r8, [r7, #2864] @ 0xb30 │ │ strhteq r0, [sl], -r8 │ │ ldc2l 11, cr1, [r8, #188] @ 0xbc @ │ │ - ldc2l 4, cr9, [r6, #676] @ 0x2a4 │ │ - vcadd.f32 , , , #270 │ │ + ldc2l 4, cr9, [r6, #856] @ 0x358 │ │ + ldc2l 9, cr7, [r7, #40] @ 0x28 @ │ │ ldc2l 1, cr11, [r8, #596] @ 0x254 │ │ - ldc2l 4, cr9, [r6, #292] @ 0x124 │ │ + ldc2l 4, cr9, [r6, #472] @ 0x1d8 │ │ vcadd.f32 d23, d8, d5, #270 │ │ - ldc2l 4, cr9, [r6, #100] @ 0x64 │ │ + ldc2l 4, cr9, [r6, #280] @ 0x118 │ │ ldc2l 9, cr15, [r7, #174] @ 0xae @ │ │ ldc2l 3, cr3, [r9, #852] @ 0x354 │ │ ldc2l 3, cr15, [r8, #88] @ 0x58 │ │ - ldc2l 13, cr3, [r6, #404] @ 0x194 │ │ - ldc2l 14, cr1, [r6, #356] @ 0x164 │ │ + ldc2l 13, cr3, [r6, #584] @ 0x248 │ │ + ldc2l 14, cr1, [r6, #536] @ 0x218 │ │ ldc2l 2, cr0, [r6, #740] @ 0x2e4 │ │ - ldc2l 7, cr13, [r7, #932] @ 0x3a4 │ │ - ldc2l 3, cr9, [r6, #100] @ 0x64 │ │ + ldc2l 8, cr13, [r7, #88] @ 0x58 │ │ + ldc2l 3, cr9, [r6, #280] @ 0x118 │ │ ldrdeq r0, [sl], -r4 @ │ │ eoreq r0, sl, r0, lsl #14 │ │ - ldc2l 13, cr11, [r6, #888] @ 0x378 │ │ - ldc2l 0, cr12, [r6, #240] @ 0xf0 │ │ + ldc2l 14, cr11, [r6, #44] @ 0x2c │ │ + ldc2l 0, cr12, [r6, #420] @ 0x1a4 │ │ cmp r1, #2 │ │ bcc 24ba7c0 │ │ ldr r0, [pc, #3412] @ 24bb500 │ │ movw r3, #1236 @ 0x4d4 │ │ ldr r2, [pc, #3408] @ 24bb504 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1429421,27 +1429421,27 @@ │ │ ldc2l 0, cr13, [r5, #604] @ 0x25c │ │ ldrbeq r8, [r7, #1940] @ 0x794 │ │ ldc2l 1, cr8, [r8, #876] @ 0x36c │ │ vcadd.f32 d31, d21, d9, #270 │ │ strhteq r0, [sl], -r0 │ │ eoreq r0, sl, r0, lsl r5 │ │ ldc2l 2, cr8, [r5, #608] @ 0x260 │ │ - ldc2l 14, cr11, [r6, #848] @ 0x350 │ │ + ldc2l 15, cr11, [r6, #4] │ │ ldc2l 2, cr8, [r5, #400] @ 0x190 │ │ - ldc2l 14, cr11, [r6, #640] @ 0x280 │ │ + ldc2l 14, cr11, [r6, #820] @ 0x334 │ │ ldc2l 9, cr4, [r9, #84] @ 0x54 @ │ │ - ldc2l 14, cr11, [r6, #256] @ 0x100 │ │ + ldc2l 14, cr11, [r6, #436] @ 0x1b4 │ │ ldc2l 9, cr4, [r9, #10] @ │ │ - ldc2l 14, cr11, [r6, #80] @ 0x50 │ │ + ldc2l 14, cr11, [r6, #260] @ 0x104 │ │ ldrbeq r8, [r7, #1324] @ 0x52c │ │ eoreq r0, sl, r4, asr #8 │ │ ldc2l 8, cr4, [r9, #500] @ 0x1f4 │ │ vcadd.f32 q10, , , #270 │ │ - ldc2l 13, cr11, [r6, #336] @ 0x150 │ │ - ldc2l 13, cr11, [r6, #160] @ 0xa0 │ │ + ldc2l 13, cr11, [r6, #516] @ 0x204 │ │ + ldc2l 13, cr11, [r6, #340] @ 0x154 │ │ cmp r1, #2 │ │ bcc 24badc0 │ │ ldr r0, [pc, #4012] @ 24bbd58 │ │ movw r3, #1401 @ 0x579 │ │ ldr r2, [pc, #4008] @ 24bbd5c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1429617,30 +1429617,30 @@ │ │ sub r1, fp, #1488 @ 0x5d0 │ │ add r2, pc, r2 │ │ mov r3, r2 │ │ bl 270e810 │ │ b 24bb888 │ │ ldc2l 13, cr12, [r5, #844] @ 0x34c │ │ ldrbeq r8, [r7, #1232] @ 0x4d0 │ │ - ldc2l 12, cr11, [r6, #176] @ 0xb0 │ │ - ldc2l 12, cr11, [r6, #16] │ │ - ldc2l 11, cr11, [r6, #736] @ 0x2e0 @ │ │ - ldc2l 7, cr3, [r6, #16] │ │ - ldc2l 11, cr11, [r6, #400] @ 0x190 @ │ │ + ldc2l 12, cr11, [r6, #356] @ 0x164 │ │ + ldc2l 12, cr11, [r6, #196] @ 0xc4 │ │ + ldc2l 11, cr11, [r6, #916] @ 0x394 @ │ │ + ldc2l 7, cr3, [r6, #196] @ 0xc4 │ │ + ldc2l 11, cr11, [r6, #580] @ 0x244 @ │ │ ldc2l 14, cr12, [r8, #888] @ 0x378 │ │ - ldc2l 11, cr11, [r6, #64] @ 0x40 @ │ │ + ldc2l 11, cr11, [r6, #244] @ 0xf4 @ │ │ ldc2l 5, cr4, [r9, #880] @ 0x370 │ │ ldc2l 5, cr4, [r9, #676] @ 0x2a4 │ │ - ldc2l 10, cr11, [r6, #736] @ 0x2e0 @ │ │ - ldc2l 15, cr10, [r7, #108] @ 0x6c │ │ - ldc2l 7, cr15, [r6, #148] @ 0x94 │ │ - ldc2l 10, cr11, [r6, #384] @ 0x180 @ │ │ + ldc2l 10, cr11, [r6, #916] @ 0x394 @ │ │ + ldc2l 15, cr10, [r7, #288] @ 0x120 │ │ + ldc2l 7, cr15, [r6, #328] @ 0x148 │ │ + ldc2l 10, cr11, [r6, #564] @ 0x234 @ │ │ ldrbeq r7, [r7, #4064] @ 0xfe0 │ │ ldc2l 0, cr9, [r5, #636] @ 0x27c │ │ - ldc2l 9, cr11, [r6, #496] @ 0x1f0 @ │ │ + ldc2l 10, cr11, [r6, #148] @ 0x94 @ │ │ ldrbeq r7, [r7, #3732] @ 0xe94 │ │ cmp r0, #0 │ │ beq 24bb154 │ │ ldr r0, [fp, #-1076] @ 0xfffffbcc │ │ sub r1, r0, #1 │ │ cmp r1, #2 │ │ bcc 24bb0f0 │ │ @@ -1429827,15 +1429827,15 @@ │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #4088] @ 24bc3b0 │ │ add r0, pc, r0 │ │ b 24bb52c │ │ eoreq r0, sl, r4, lsr #32 │ │ - ldc2l 8, cr9, [r6, #476] @ 0x1dc │ │ + vcadd.f32 d25, d22, d20, #270 │ │ ldr r0, [fp, #-1076] @ 0xfffffbcc │ │ sub r1, r0, #1 │ │ cmp r1, #2 │ │ bcc 24bb3f0 │ │ ldr r0, [pc, #4056] @ 24bc3b4 │ │ movw r3, #1748 @ 0x6d4 │ │ ldr r2, [pc, #4052] @ 24bc3b8 │ │ @@ -1429858,15 +1429858,15 @@ │ │ ldr r1, [sp, #76] @ 0x4c │ │ ldr r3, [pc, #3988] @ 24bc3c0 │ │ add r0, lr, #808 @ 0x328 │ │ add r3, pc, r3 │ │ bl 270fc20 │ │ b 24bb5d0 │ │ ldc2l 6, cr0, [r9, #1020] @ 0x3fc │ │ - ldc2l 8, cr11, [r6, #848] @ 0x350 │ │ + ldc2l 9, cr11, [r6, #2] @ │ │ ldrbeq r7, [r7, #3864] @ 0xf18 │ │ cmp r1, #2 │ │ bcc 24bb468 │ │ ldr r0, [pc, #3952] @ 24bc3c4 │ │ movw r3, #1767 @ 0x6e7 │ │ ldr r2, [pc, #3948] @ 24bc3c8 │ │ add r0, pc, r0 │ │ @@ -1429893,30 +1429893,30 @@ │ │ add r8, sp, #920 @ 0x398 │ │ sub r1, r0, #1 │ │ cmp r1, #2 │ │ bcs 24bb508 │ │ ldr r0, [pc, #3856] @ 24bc3d4 │ │ add r0, pc, r0 │ │ b 24bb52c │ │ - ldc2l 2, cr11, [r6, #368] @ 0x170 │ │ + ldc2l 2, cr11, [r6, #548] @ 0x224 │ │ ldc2l 13, cr6, [r8, #264] @ 0x108 │ │ - ldc2l 7, cr11, [r6, #1008] @ 0x3f0 │ │ + vcadd.f32 d27, d6, d25, #270 │ │ ldrbeq r7, [r7, #3772] @ 0xebc │ │ ldc2l 5, cr0, [r9, #828] @ 0x33c │ │ - ldc2l 7, cr11, [r6, #656] @ 0x290 │ │ + ldc2l 7, cr11, [r6, #836] @ 0x344 │ │ ldrbeq r7, [r7, #3556] @ 0xde4 │ │ ldc2l 13, cr8, [r5, #972] @ 0x3cc │ │ - ldc2l 7, cr11, [r6, #304] @ 0x130 │ │ + ldc2l 7, cr11, [r6, #484] @ 0x1e4 │ │ ldrbeq r7, [r7, #3056] @ 0xbf0 │ │ eoreq pc, r9, r0, lsl #27 │ │ ldc2l 0, cr5, [r8, #568] @ 0x238 │ │ - ldc2l 6, cr11, [r6, #784] @ 0x310 │ │ - ldc2l 0, cr11, [r6, #496] @ 0x1f0 │ │ + ldc2l 6, cr11, [r6, #964] @ 0x3c4 │ │ + ldc2l 0, cr11, [r6, #676] @ 0x2a4 │ │ ldc2l 10, cr6, [r8, #984] @ 0x3d8 @ │ │ - ldc2l 5, cr11, [r6, #704] @ 0x2c0 │ │ + ldc2l 5, cr11, [r6, #884] @ 0x374 │ │ ldr r0, [pc, #4064] @ 24bc4f0 │ │ movw r3, #1770 @ 0x6ea │ │ ldr r2, [pc, #4060] @ 24bc4f4 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ @@ -1430087,22 +1430087,22 @@ │ │ add r0, lr, #120 @ 0x78 │ │ add r0, r0, r1, lsl #3 │ │ ldr r1, [sp, #28] │ │ bl 270f6f0 │ │ b 24bb830 │ │ ldrbeq r7, [r7, #3184] @ 0xc70 │ │ ldc2l 3, cr0, [r9, #524] @ 0x20c │ │ - ldc2l 5, cr11, [r6, #352] @ 0x160 │ │ + ldc2l 5, cr11, [r6, #532] @ 0x214 │ │ ldrbeq r7, [r7, #2968] @ 0xb98 │ │ ldc2l 11, cr8, [r5, #668] @ 0x29c @ │ │ - ldc2l 5, cr11, [r6] │ │ + ldc2l 5, cr11, [r6, #180] @ 0xb4 │ │ ldrbeq r7, [r7, #2468] @ 0x9a4 │ │ eoreq pc, r9, r4, lsr fp @ │ │ - ldc2l 1, cr15, [r6, #292] @ 0x124 │ │ - ldc2l 4, cr11, [r6, #528] @ 0x210 │ │ + ldc2l 1, cr15, [r6, #472] @ 0x1d8 │ │ + ldc2l 4, cr11, [r6, #708] @ 0x2c4 │ │ ldrbeq r7, [r7, #2556] @ 0x9fc │ │ cmp r0, #2 │ │ bcc 24bb818 │ │ ldr r0, [pc, #4088] @ 24bc7fc │ │ mov r3, #1872 @ 0x750 │ │ ldr r2, [pc, #4084] @ 24bc800 │ │ add r0, pc, r0 │ │ @@ -1430281,17 +1430281,17 @@ │ │ add r0, pc, r0 │ │ bl 270da30 │ │ ldr r6, [fp, #-1076] @ 0xfffffbcc │ │ mov r1, r0 │ │ b 24bb9e4 │ │ eoreq pc, r9, r0, lsr #18 │ │ ldc2l 12, cr4, [r8, #152] @ 0x98 │ │ - ldc2l 2, cr11, [r6, #368] @ 0x170 │ │ + ldc2l 2, cr11, [r6, #548] @ 0x224 │ │ ldc2l 11, cr4, [r8, #872] @ 0x368 @ │ │ - ldc2l 2, cr11, [r6, #64] @ 0x40 │ │ + ldc2l 2, cr11, [r6, #244] @ 0xf4 │ │ ldr r2, [pc, #4084] @ 24bcae0 │ │ sub lr, fp, #1024 @ 0x400 │ │ ldr r3, [pc, #4080] @ 24bcae4 │ │ mov r0, #5 │ │ sub r5, lr, #60 @ 0x3c │ │ add lr, sp, #1024 @ 0x400 │ │ str r0, [sp, #12] │ │ @@ -1430316,15 +1430316,15 @@ │ │ ldr r7, [pc, #4052] @ 24bcb24 │ │ add r8, r1, #8 │ │ sub r9, fp, #472 @ 0x1d8 │ │ sub r4, fp, #1904 @ 0x770 │ │ add r7, pc, r7 │ │ mov r5, #7 │ │ b 24bbba4 │ │ - ldc2l 11, cr10, [r6, #288] @ 0x120 @ │ │ + ldc2l 11, cr10, [r6, #468] @ 0x1d4 @ │ │ ldrbeq r7, [r7, #2284] @ 0x8ec │ │ ldrbeq r7, [r7, #2256] @ 0x8d0 │ │ ldc2l 10, cr4, [r8, #472] @ 0x1d8 @ │ │ add r3, r9, r1, lsl #3 │ │ mov r0, r8 │ │ mov r1, r4 │ │ mov r2, r7 │ │ @@ -1430400,18 +1430400,18 @@ │ │ movw r3, #2084 @ 0x824 │ │ ldr r2, [pc, #4092] @ 24bcca0 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 24bbb74 │ │ - ldc2l 0, cr11, [r6, #688] @ 0x2b0 │ │ + ldc2l 0, cr11, [r6, #868] @ 0x364 │ │ eoreq pc, r9, r8, lsl r7 @ │ │ ldc2l 10, cr4, [r8, #88] @ 0x58 @ │ │ - ldc2l 0, cr11, [r6, #304] @ 0x130 │ │ + ldc2l 0, cr11, [r6, #484] @ 0x1e4 │ │ strhteq pc, [r9], -r8 @ │ │ ldr r0, [pc, #4052] @ 24bcca4 │ │ mov r1, #186 @ 0xba │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #4040] @ 24bcca8 │ │ add lr, sp, #1024 @ 0x400 │ │ @@ -1430442,21 +1430442,21 @@ │ │ ldr r1, [pc, #4044] @ 24bcd14 │ │ mov r0, r4 │ │ mov r2, #1 │ │ mov r3, #8 │ │ add r1, pc, r1 │ │ b 24b9a80 │ │ ldc2l 4, cr6, [r8, #984] @ 0x3d8 │ │ - ldc2l 15, cr10, [r6, #704] @ 0x2c0 │ │ + ldc2l 15, cr10, [r6, #884] @ 0x374 │ │ ldrbeq r7, [r7, #1648] @ 0x670 │ │ ldc2l 13, cr15, [r8, #524] @ 0x20c │ │ - ldc2l 15, cr10, [r6, #352] @ 0x160 │ │ + ldc2l 15, cr10, [r6, #532] @ 0x214 │ │ ldrbeq r7, [r7, #1432] @ 0x598 │ │ ldc2l 5, cr8, [r5, #668] @ 0x29c │ │ - ldc2l 15, cr10, [r6] │ │ + ldc2l 15, cr10, [r6, #180] @ 0xb4 │ │ ldrbeq r7, [r7, #932] @ 0x3a4 │ │ eoreq pc, r9, r4, lsr r5 @ │ │ mlaeq r9, ip, r4, pc @ │ │ eoreq pc, r9, r8, lsr r4 @ │ │ ldr r2, [pc, #3956] @ 24bcd04 │ │ add lr, sp, #1024 @ 0x400 │ │ ldr r4, [pc, #3952] @ 24bcd08 │ │ @@ -1430612,15 +1430612,15 @@ │ │ add lr, sp, #1024 @ 0x400 │ │ add r1, lr, #120 @ 0x78 │ │ mov r0, r4 │ │ mov r2, #1 │ │ mov r3, #80 @ 0x50 │ │ b 24b9a80 │ │ ldc2l 6, cr4, [r8, #984] @ 0x3d8 │ │ - ldc2l 13, cr10, [r6, #176] @ 0xb0 │ │ + ldc2l 13, cr10, [r6, #356] @ 0x164 │ │ mlaeq r9, r0, r3, pc @ │ │ ldr r0, [sp, #64] @ 0x40 │ │ sub r1, fp, #1072 @ 0x430 │ │ add r2, sp, #84 @ 0x54 │ │ mov r3, #36 @ 0x24 │ │ bl 270ce00 │ │ ldr r0, [sp, #84] @ 0x54 │ │ @@ -1430661,25 +1430661,25 @@ │ │ bl 270da60 │ │ ldr r0, [pc, #3208] @ 24bcd40 │ │ mov r1, #23 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ b 24b966c │ │ ldc2l 10, cr15, [r8, #684] @ 0x2ac @ │ │ - ldc2l 12, cr10, [r6, #512] @ 0x200 │ │ + ldc2l 12, cr10, [r6, #692] @ 0x2b4 │ │ add r1, sp, #456 @ 0x1c8 │ │ ldr r0, [sp, #72] @ 0x48 │ │ str r0, [sp] │ │ add r2, r1, #4 │ │ add r3, r1, #8 │ │ sub r0, fp, #472 @ 0x1d8 │ │ bl 270f7b0 │ │ b 24bc5b4 │ │ ldrbeq r7, [r7, #708] @ 0x2c4 │ │ - ldc2l 6, cr10, [r6, #176] @ 0xb0 │ │ + ldc2l 6, cr10, [r6, #356] @ 0x164 │ │ ldr r0, [pc, #3200] @ 24bcd7c │ │ mov r1, #205 @ 0xcd │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #3188] @ 24bcd80 │ │ add lr, sp, #1024 @ 0x400 │ │ add r1, lr, #808 @ 0x328 │ │ @@ -1430700,15 +1430700,15 @@ │ │ bl 270da60 │ │ ldr r0, [pc, #3120] @ 24bcd84 │ │ mov r1, #18 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ b 24b966c │ │ ldc2l 4, cr2, [r8, #36] @ 0x24 │ │ - ldc2l 11, cr10, [r6, #960] @ 0x3c0 @ │ │ + ldc2l 12, cr10, [r6, #116] @ 0x74 │ │ ldrbeq r7, [r7, #600] @ 0x258 │ │ eoreq pc, r9, r8, lsr #4 │ │ ldc2l 12, cr11, [r5, #316] @ 0x13c │ │ ldrbeq r7, [r7, #844] @ 0x34c │ │ add lr, sp, #1024 @ 0x400 │ │ ldr r2, [pc, #2976] @ 24bcd24 │ │ ldr r3, [pc, #2976] @ 24bcd28 │ │ @@ -1430745,28 +1430745,28 @@ │ │ cmp r0, r1 │ │ bne 24bca08 │ │ sub lr, fp, #2048 @ 0x800 │ │ mov r1, r4 │ │ sub r0, lr, #152 @ 0x98 │ │ bl 270fc30 │ │ b 24bc4c0 │ │ - ldc2l 9, cr4, [r6, #304] @ 0x130 @ │ │ + ldc2l 9, cr4, [r6, #394] @ 0x18a @ │ │ ldc2l 13, cr7, [r8, #864] @ 0x360 │ │ ldc2l 10, cr9, [r8, #620] @ 0x26c @ │ │ - ldc2l 8, cr10, [r6, #452] @ 0x1c4 │ │ - ldc2l 10, cr10, [r6, #800] @ 0x320 @ │ │ + ldc2l 8, cr10, [r6, #632] @ 0x278 │ │ + ldc2l 10, cr10, [r6, #980] @ 0x3d4 @ │ │ ldrbeq r7, [r7, #432] @ 0x1b0 │ │ eoreq pc, r9, r0, lsl #2 │ │ ldc2l 13, cr7, [r8, #128] @ 0x80 │ │ - ldc2l 9, cr0, [r7, #66] @ 0x42 @ │ │ - ldc2l 10, cr10, [r6, #192] @ 0xc0 @ │ │ + ldc2l 9, cr0, [r7, #156] @ 0x9c @ │ │ + ldc2l 10, cr10, [r6, #372] @ 0x174 @ │ │ ldrbeq r6, [r7, #3748] @ 0xea4 │ │ eoreq pc, r9, r4, ror r0 @ │ │ - ldc2l 8, cr0, [r7, #732] @ 0x2dc │ │ - ldc2l 9, cr10, [r6, #384] @ 0x180 @ │ │ + vcadd.f32 q8, , q10, #270 │ │ + ldc2l 9, cr10, [r6, #474] @ 0x1da @ │ │ ldr r2, [pc, #2912] @ 24bcdb8 │ │ sub lr, fp, #1024 @ 0x400 │ │ ldr r3, [pc, #2908] @ 24bcdbc │ │ mov r0, #32 │ │ sub r7, lr, #60 @ 0x3c │ │ add r1, sp, #904 @ 0x388 │ │ add lr, sp, #1024 @ 0x400 │ │ @@ -1430848,20 +1430848,20 @@ │ │ mov r0, r5 │ │ mov r2, #1 │ │ mov r3, #13 │ │ add r1, pc, r1 │ │ bl 270da60 │ │ b 24bc9d4 │ │ ldrbeq r6, [r7, #3796] @ 0xed4 │ │ - ldc2l 6, cr12, [r6, #996] @ 0x3e4 │ │ - ldc2l 9, cr10, [r6, #256] @ 0x100 @ │ │ + ldc2l 7, cr12, [r6, #152] @ 0x98 │ │ + ldc2l 9, cr10, [r6, #346] @ 0x15a @ │ │ ldrbeq r7, [r7, #240] @ 0xf0 │ │ eoreq lr, r9, r8, asr #31 │ │ ldc2l 15, cr7, [r5, #728] @ 0x2d8 │ │ - ldc2l 9, cr10, [r6, #16] @ │ │ + ldc2l 9, cr10, [r6, #106] @ 0x6a @ │ │ ldrbeq r6, [r7, #3836] @ 0xefc │ │ eoreq lr, r9, ip, asr #30 │ │ ldrbeq r6, [r7, #3720] @ 0xe88 │ │ add lr, sp, #1024 @ 0x400 │ │ ldr r2, [pc, #2408] @ 24bcd4c │ │ ldr r3, [pc, #2408] @ 24bcd50 │ │ mov r1, #11 │ │ @@ -1430928,15 +1430928,15 @@ │ │ mov r3, r8 │ │ bl 270e7e0 │ │ add r1, sp, #160 @ 0xa0 │ │ mov r0, r9 │ │ bl 270de50 │ │ b 24b9a0c │ │ ldc2l 13, cr5, [r8, #612] @ 0x264 │ │ - vcadd.f32 q13, q3, q6, #270 │ │ + ldc2l 8, cr10, [r6, #484] @ 0x1e4 │ │ ldrbeq r6, [r7, #3616] @ 0xe20 │ │ mlaeq r9, r4, lr, lr │ │ ldr r0, [pc, #2280] @ 24bcdf0 │ │ mov r1, #115 @ 0x73 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #2268] @ 24bcdf4 │ │ @@ -1430958,15 +1430958,15 @@ │ │ bl 270db00 │ │ ldr r0, [pc, #2204] @ 24bcdf8 │ │ add r0, pc, r0 │ │ b 24b9b48 │ │ ldc2l 5, cr1, [r9, #424] @ 0x1a8 │ │ eoreq lr, r9, r8, lsr lr │ │ ldc2l 1, cr4, [r8, #200] @ 0xc8 │ │ - ldc2l 7, cr10, [r6, #416] @ 0x1a0 │ │ + ldc2l 7, cr10, [r6, #596] @ 0x254 │ │ ldr r0, [pc, #2044] @ 24bcd74 │ │ sub lr, fp, #2048 @ 0x800 │ │ sub r4, fp, #376 @ 0x178 │ │ ldr r1, [fp, #8] │ │ add r0, pc, r0 │ │ sub r2, lr, #152 @ 0x98 │ │ mov r3, r4 │ │ @@ -1430996,15 +1430996,15 @@ │ │ ldr r5, [pc, #2136] @ 24bce48 │ │ ldr r6, [pc, #2136] @ 24bce4c │ │ add r4, pc, r4 │ │ add r5, pc, r5 │ │ add r6, pc, r6 │ │ b 24bc62c │ │ ldc2l 0, cr4, [r8, #920] @ 0x398 │ │ - ldc2l 7, cr10, [r6, #112] @ 0x70 │ │ + ldc2l 7, cr10, [r6, #292] @ 0x124 │ │ ldr r0, [sp, #72] @ 0x48 │ │ add r1, r0, r1, lsl #3 │ │ mov r0, r4 │ │ bl 270d1a0 │ │ ldr r1, [fp, #-1076] @ 0xfffffbcc │ │ add r0, r1, #1 │ │ cmp r1, #3 │ │ @@ -1431038,15 +1431038,15 @@ │ │ ldr r5, [pc, #1924] @ 24bce1c │ │ ldr r6, [pc, #1924] @ 24bce20 │ │ add r4, pc, r4 │ │ add r5, pc, r5 │ │ add r6, pc, r6 │ │ b 24bc6d8 │ │ ldc2l 0, cr4, [r8, #376] @ 0x178 │ │ - ldc2l 6, cr10, [r6, #592] @ 0x250 │ │ + ldc2l 6, cr10, [r6, #772] @ 0x304 │ │ eoreq lr, r9, r0, lsl #26 │ │ ldr r0, [sp, #72] @ 0x48 │ │ add r1, r0, r1, lsl #3 │ │ mov r0, r4 │ │ bl 270d1a0 │ │ ldr r1, [fp, #-1076] @ 0xfffffbcc │ │ add r0, r1, #1 │ │ @@ -1431060,15 +1431060,15 @@ │ │ mov r0, r5 │ │ mov r2, r6 │ │ movw r3, #2234 @ 0x8ba │ │ bl 270da30 │ │ mov r1, r0 │ │ b 24bc6b4 │ │ ldc2l 15, cr3, [r8, #1016] @ 0x3f8 │ │ - ldc2l 6, cr10, [r6, #208] @ 0xd0 │ │ + ldc2l 6, cr10, [r6, #388] @ 0x184 │ │ eoreq lr, r9, r0, lsr #25 │ │ ldr r0, [pc, #1720] @ 24bcdcc │ │ mov r1, #203 @ 0xcb │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #1708] @ 24bcdd0 │ │ add lr, sp, #1024 @ 0x400 │ │ @@ -1431092,15 +1431092,15 @@ │ │ add lr, sp, #1024 @ 0x400 │ │ add r1, r1, r1, lsl #2 │ │ add r2, lr, #840 @ 0x348 │ │ add r0, pc, r0 │ │ add r1, r2, r1, lsl #4 │ │ b 24bbff4 │ │ ldc2l 15, cr3, [r8, #568] @ 0x238 │ │ - ldc2l 5, cr10, [r6, #784] @ 0x310 │ │ + ldc2l 5, cr10, [r6, #964] @ 0x3c4 │ │ ldr r1, [pc, #1684] @ 24bce24 │ │ sub lr, fp, #2048 @ 0x800 │ │ ldr r0, [fp, #8] │ │ sub r2, lr, #152 @ 0x98 │ │ add r1, pc, r1 │ │ sub r3, fp, #376 @ 0x178 │ │ bl 270ff60 │ │ @@ -1431123,15 +1431123,15 @@ │ │ ldr r5, [pc, #1604] @ 24bce30 │ │ ldr r6, [pc, #1604] @ 24bce34 │ │ add r4, pc, r4 │ │ add r5, pc, r5 │ │ add r6, pc, r6 │ │ b 24bc824 │ │ ldc2l 15, cr3, [r8, #136] @ 0x88 │ │ - ldc2l 5, cr10, [r6, #352] @ 0x160 │ │ + ldc2l 5, cr10, [r6, #532] @ 0x214 │ │ add r1, r9, r1, lsl #3 │ │ mov r0, r4 │ │ bl 270d1a0 │ │ ldr r1, [fp, #-1076] @ 0xfffffbcc │ │ add r0, r1, #1 │ │ cmp r1, #3 │ │ str r0, [fp, #-1076] @ 0xfffffbcc │ │ @@ -1431143,17 +1431143,17 @@ │ │ mov r0, r5 │ │ mov r2, r6 │ │ mov r3, #2256 @ 0x8d0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 24bc804 │ │ ldc2l 14, cr3, [r8, #792] @ 0x318 │ │ - ldc2l 4, cr10, [r6, #1008] @ 0x3f0 │ │ + ldc2l 5, cr10, [r6, #164] @ 0xa4 │ │ ldc2l 14, cr3, [r8, #424] @ 0x1a8 │ │ - ldc2l 4, cr10, [r6, #640] @ 0x280 │ │ + ldc2l 4, cr10, [r6, #820] @ 0x334 │ │ eoreq lr, r9, ip, lsl #22 │ │ ldr r0, [sp, #72] @ 0x48 │ │ sub r1, fp, #484 @ 0x1e4 │ │ add lr, sp, #1024 @ 0x400 │ │ str r0, [sp] │ │ add r3, r1, #4 │ │ add r0, lr, #120 @ 0x78 │ │ @@ -1431185,15 +1431185,15 @@ │ │ ldr r2, [pc, #1288] @ 24bcdec │ │ add r2, pc, r2 │ │ str r2, [sp] │ │ str r0, [sp, #4] │ │ sub r0, fp, #376 @ 0x178 │ │ b 24bc5ac │ │ ldc2l 14, cr3, [r8, #88] @ 0x58 │ │ - ldc2l 4, cr10, [r6, #304] @ 0x130 │ │ + ldc2l 4, cr10, [r6, #484] @ 0x1e4 │ │ ldc2l 10, cr5, [r8, #668] @ 0x29c @ │ │ mlaeq r9, ip, sl, lr │ │ ldr r0, [pc, #1160] @ 24bcd94 │ │ mov r1, #452 @ 0x1c4 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #1148] @ 24bcd98 │ │ @@ -1431214,15 +1431214,15 @@ │ │ mov r2, #1 │ │ mov r3, #32 │ │ bl 270da60 │ │ b 24bccf0 │ │ ldc2l 15, cr9, [r5, #616] @ 0x268 │ │ eoreq lr, r9, r8, asr #20 │ │ eoreq lr, r9, r0, lsr sl │ │ - ldc2l 3, cr10, [r6, #544] @ 0x220 │ │ + ldc2l 3, cr10, [r6, #724] @ 0x2d4 │ │ ldr r0, [pc, #1060] @ 24bcd9c │ │ movw r1, #329 @ 0x149 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #1048] @ 24bcda0 │ │ add lr, sp, #1024 @ 0x400 │ │ add r1, lr, #808 @ 0x328 │ │ @@ -1431269,15 +1431269,15 @@ │ │ sub r1, fp, #1072 @ 0x430 │ │ mov r2, #36 @ 0x24 │ │ bl 270db10 │ │ ldr r0, [pc, #756] @ 24bcd34 │ │ mov r1, #212 @ 0xd4 │ │ add r0, pc, r0 │ │ b 24bcc58 │ │ - ldc2l 1, cr12, [r6, #412] @ 0x19c │ │ + ldc2l 1, cr12, [r6, #592] @ 0x250 │ │ eoreq lr, r9, pc, ror #17 │ │ ldr r0, [pc, #1024] @ 24bce58 │ │ mov r1, #215 @ 0xd7 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #1012] @ 24bce5c │ │ add lr, sp, #1024 @ 0x400 │ │ @@ -1431307,15 +1431307,15 @@ │ │ ldr r4, [pc, #876] @ 24bce38 │ │ ldr r5, [pc, #876] @ 24bce3c │ │ ldr r8, [pc, #876] @ 24bce40 │ │ add r4, pc, r4 │ │ add r5, pc, r5 │ │ add r8, pc, r8 │ │ b 24bcb0c │ │ - ldc2l 0, cr4, [r6, #760] @ 0x2f8 │ │ + ldc2l 0, cr4, [r6, #940] @ 0x3ac │ │ eoreq lr, r9, r8, ror #17 │ │ ldr r2, [sp, #72] @ 0x48 │ │ add r0, r9, r7, lsl #3 │ │ add r1, r2, r1, lsl #3 │ │ bl 270f010 │ │ ldr r1, [fp, #-1076] @ 0xfffffbcc │ │ add r0, r1, #1 │ │ @@ -1431342,15 +1431342,15 @@ │ │ bcc 24bcae8 │ │ mov r0, r4 │ │ mov r2, r5 │ │ movw r3, #2274 @ 0x8e2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 24bcae8 │ │ - ldc2l 15, cr11, [r6, #956] @ 0x3bc │ │ + ldc2l 0, cr12, [r6, #112] @ 0x70 │ │ ldr r0, [pc, #560] @ 24bcda8 │ │ movw r1, #322 @ 0x142 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #548] @ 24bcdac │ │ add lr, sp, #1024 @ 0x400 │ │ add r1, lr, #808 @ 0x328 │ │ @@ -1431364,17 +1431364,17 @@ │ │ add r1, lr, #171 @ 0xab │ │ mov r2, #1 │ │ mov r3, #5 │ │ bl 270da60 │ │ ldr r0, [pc, #496] @ 24bcdb0 │ │ add r0, pc, r0 │ │ b 24b9b48 │ │ - ldc2l 1, cr10, [r6, #608] @ 0x260 │ │ + ldc2l 1, cr10, [r6, #788] @ 0x314 │ │ ldc2l 2, cr14, [r5, #480] @ 0x1e0 │ │ - ldc2l 1, cr10, [r6, #432] @ 0x1b0 │ │ + ldc2l 1, cr10, [r6, #612] @ 0x264 │ │ ldr r0, [pc, #404] @ 24bcd6c │ │ mov r1, #169 @ 0xa9 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #352] @ 24bcd48 │ │ add lr, sp, #1024 @ 0x400 │ │ add r1, lr, #808 @ 0x328 │ │ @@ -1431384,15 +1431384,15 @@ │ │ mov r0, r4 │ │ bl 270da60 │ │ add lr, sp, #1024 @ 0x400 │ │ add r1, lr, #840 @ 0x348 │ │ b 24bbff0 │ │ eoreq lr, r9, r0, asr #15 │ │ ldc2l 2, cr13, [r8, #124] @ 0x7c │ │ - ldc2l 1, cr10, [r6, #64] @ 0x40 │ │ + ldc2l 1, cr10, [r6, #244] @ 0xf4 │ │ ldc2l 1, cr13, [r8, #828] @ 0x33c │ │ ldr r0, [sp, #64] @ 0x40 │ │ sub r1, fp, #1072 @ 0x430 │ │ add r2, sp, #84 @ 0x54 │ │ mov r3, #36 @ 0x24 │ │ bl 270ce00 │ │ ldr r0, [sp, #84] @ 0x54 │ │ @@ -1431419,17 +1431419,17 @@ │ │ mov r2, #1 │ │ mov r3, #36 @ 0x24 │ │ mov r1, r5 │ │ bl 270da60 │ │ ldr r1, [pc, #160] @ 24bcd3c │ │ add r1, pc, r1 │ │ b 24bc08c │ │ - ldc2l 0, cr10, [r6, #768] @ 0x300 │ │ - ldc2l 14, cr7, [r6, #864] @ 0x360 │ │ - ldc2l 2, cr7, [r6, #100] @ 0x64 │ │ + ldc2l 0, cr10, [r6, #948] @ 0x3b4 │ │ + ldc2l 15, cr7, [r6, #20] │ │ + ldc2l 2, cr7, [r6, #280] @ 0x118 │ │ ldc2l 2, cr1, [r9, #20] │ │ ldr r0, [pc, #252] @ 24bcdb4 │ │ add r0, pc, r0 │ │ movw r1, #310 @ 0x136 │ │ bl 270da00 │ │ ldr r4, [pc, #196] @ 24bcd8c │ │ add lr, sp, #1024 @ 0x400 │ │ @@ -1431444,101 +1431444,101 @@ │ │ mov r2, #1 │ │ bl 270db00 │ │ ldr r0, [pc, #152] @ 24bcd90 │ │ mov r1, #24 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ b 24b966c │ │ - ldc2l 13, cr13, [r6, #388] @ 0x184 │ │ + ldc2l 13, cr13, [r6, #568] @ 0x238 │ │ eoreq lr, r9, ip, ror #12 │ │ ldc2l 11, cr9, [r5, #284] @ 0x11c @ │ │ ldc2l 8, cr15, [r7, #64] @ 0x40 │ │ ldc2l 14, cr14, [r8, #264] @ 0x108 │ │ ldc2l 15, cr10, [r8, #936] @ 0x3a8 │ │ - ldc2l 14, cr6, [r6, #660] @ 0x294 │ │ + ldc2l 14, cr6, [r6, #840] @ 0x348 │ │ ldc2l 4, cr15, [r7, #804] @ 0x324 │ │ - ldc2l 9, cr9, [r6, #230] @ 0xe6 @ │ │ + ldc2l 9, cr9, [r6, #320] @ 0x140 @ │ │ eoreq lr, r9, r0, asr #4 │ │ - ldc2l 4, cr5, [r7, #588] @ 0x24c │ │ + ldc2l 4, cr5, [r7, #768] @ 0x300 │ │ ldrbeq r6, [r7, #12] │ │ - ldc2l 15, cr12, [r6, #1008] @ 0x3f0 │ │ - ldc2l 2, cr6, [r6, #596] @ 0x254 │ │ - ldc2l 9, cr4, [r7, #422] @ 0x1a6 @ │ │ + ldc2l 0, cr13, [r6, #164] @ 0xa4 │ │ + ldc2l 2, cr6, [r6, #776] @ 0x308 │ │ + ldc2l 10, cr4, [r7] @ │ │ ldc2l 3, cr7, [r5, #372] @ 0x174 │ │ - ldc2l 2, cr15, [r6, #392] @ 0x188 │ │ - ldc2l 3, cr6, [r6, #68] @ 0x44 │ │ - ldc2l 7, cr9, [r6, #116] @ 0x74 │ │ + ldc2l 2, cr15, [r6, #572] @ 0x23c │ │ + ldc2l 3, cr6, [r6, #248] @ 0xf8 │ │ + ldc2l 7, cr9, [r6, #296] @ 0x128 │ │ eoreq sp, r9, r0, ror #31 │ │ - ldc2l 2, cr5, [r7, #204] @ 0xcc │ │ + ldc2l 2, cr5, [r7, #384] @ 0x180 │ │ ldrbeq r5, [r7, #3500] @ 0xdac │ │ - ldc2l 14, cr10, [r6, #560] @ 0x230 │ │ + ldc2l 14, cr10, [r6, #740] @ 0x2e4 │ │ eoreq sp, r9, r0, ror pc │ │ eoreq sp, r9, r4, asr pc │ │ eoreq sp, r9, r4, asr #30 │ │ - ldc2l 7, cr10, [r7, #236] @ 0xec │ │ + ldc2l 7, cr10, [r7, #416] @ 0x1a0 │ │ eoreq sp, r9, r4, lsr #30 │ │ ldrbeq r5, [r7, #4040] @ 0xfc8 │ │ eoreq sp, r9, r4, asr lr │ │ ldc2l 3, cr13, [r7, #544] @ 0x220 │ │ - ldc2l 13, cr6, [r6, #948] @ 0x3b4 │ │ + ldc2l 14, cr6, [r6, #104] @ 0x68 │ │ ldc2l 4, cr15, [r7, #48] @ 0x30 │ │ ldc2l 10, cr6, [r5, #260] @ 0x104 @ │ │ - ldc2l 2, cr6, [r6, #196] @ 0xc4 │ │ + ldc2l 2, cr6, [r6, #376] @ 0x178 │ │ ldc2l 10, cr1, [r9, #268] @ 0x10c @ │ │ ldc2l 14, cr8, [r5, #388] @ 0x184 │ │ - ldc2l 5, cr6, [r6, #884] @ 0x374 │ │ + ldc2l 6, cr6, [r6, #40] @ 0x28 │ │ ldc2l 11, cr12, [r7, #872] @ 0x368 @ │ │ - ldc2l 5, cr6, [r6, #452] @ 0x1c4 │ │ + ldc2l 5, cr6, [r6, #632] @ 0x278 │ │ ldc2l 11, cr3, [r9, #988] @ 0x3dc @ │ │ ldc2l 2, cr11, [r5, #616] @ 0x268 │ │ - ldc2l 3, cr6, [r6, #452] @ 0x1c4 │ │ - vcadd.f32 q12, q11, , #270 │ │ - ldc2l 15, cr4, [r6, #224] @ 0xe0 │ │ + ldc2l 3, cr6, [r6, #632] @ 0x278 │ │ + ldc2l 8, cr8, [r6, #960] @ 0x3c0 │ │ + ldc2l 15, cr4, [r6, #404] @ 0x194 │ │ eoreq lr, r9, r7, asr #2 │ │ eoreq lr, r9, r4, ror r1 │ │ ldc2l 14, cr10, [r8, #716] @ 0x2cc │ │ - ldc2l 11, cr6, [r6, #708] @ 0x2c4 @ │ │ + ldc2l 11, cr6, [r6, #888] @ 0x378 @ │ │ ldc2l 12, cr6, [r8, #560] @ 0x230 │ │ ldc2l 10, cr10, [r8, #44] @ 0x2c @ │ │ - ldc2l 7, cr6, [r6, #852] @ 0x354 │ │ + vcadd.f32 d22, d6, d2, #270 │ │ ldc2l 0, cr2, [r9, #1012] @ 0x3f4 │ │ - ldc2l 6, cr9, [r6, #48] @ 0x30 │ │ - ldc2l 7, cr6, [r6, #564] @ 0x234 │ │ + ldc2l 6, cr9, [r6, #228] @ 0xe4 │ │ + ldc2l 7, cr6, [r6, #744] @ 0x2e8 │ │ ldrbeq r5, [r7, #3260] @ 0xcbc │ │ eoreq sp, r9, r4, asr #22 │ │ ldrbeq r5, [r7, #3212] @ 0xc8c │ │ eoreq sp, r9, r0, lsl fp │ │ ldc2l 2, cr3, [r8, #148] @ 0x94 │ │ - ldc2l 9, cr6, [r6, #450] @ 0x1c2 @ │ │ + ldc2l 10, cr6, [r6, #56] @ 0x38 @ │ │ ldc2l 7, cr8, [r8, #728] @ 0x2d8 │ │ eoreq lr, r9, r8, asr #10 │ │ eoreq lr, r9, ip, lsr #10 │ │ ldc2l 7, cr4, [r9, #36] @ 0x24 │ │ - ldc2l 14, cr9, [r6, #512] @ 0x200 │ │ + ldc2l 14, cr9, [r6, #692] @ 0x2b4 │ │ ldc2l 15, cr12, [r8, #328] @ 0x148 │ │ - ldc2l 14, cr9, [r6, #240] @ 0xf0 │ │ + ldc2l 14, cr9, [r6, #420] @ 0x1a4 │ │ eoreq lr, r9, r4, asr r4 │ │ eoreq sp, r9, ip, asr sp │ │ - ldc2l 13, cr6, [r7, #192] @ 0xc0 │ │ - ldc2l 6, cr9, [r6, #784] @ 0x310 │ │ + ldc2l 13, cr6, [r7, #372] @ 0x174 │ │ + ldc2l 6, cr9, [r6, #964] @ 0x3c4 │ │ ldrbeq r5, [r7, #3504] @ 0xdb0 │ │ eoreq sp, r9, r0, lsr ip │ │ eoreq sp, r9, r8, lsl #24 │ │ ldc2l 5, cr8, [r8, #204] @ 0xcc │ │ - ldc2l 5, cr9, [r6, #448] @ 0x1c0 │ │ - ldc2l 8, cr6, [r7, #1008] @ 0x3f0 │ │ - ldc2l 2, cr9, [r6, #576] @ 0x240 │ │ + ldc2l 5, cr9, [r6, #628] @ 0x274 │ │ + ldc2l 9, cr6, [r7, #82] @ 0x52 @ │ │ + ldc2l 2, cr9, [r6, #756] @ 0x2f4 │ │ ldc2l 11, cr3, [r9, #96] @ 0x60 @ │ │ eoreq sp, r9, r4, lsl #28 │ │ - ldc2l 13, cr6, [r7, #864] @ 0x360 │ │ - ldc2l 7, cr9, [r6, #432] @ 0x1b0 │ │ + ldc2l 14, cr6, [r7, #20] │ │ + ldc2l 7, cr9, [r6, #612] @ 0x264 │ │ ldc2l 6, cr3, [r8, #764] @ 0x2fc │ │ - ldc2l 15, cr6, [r6, #164] @ 0xa4 │ │ + ldc2l 15, cr6, [r6, #344] @ 0x158 │ │ ldc2l 3, cr13, [r5, #240] @ 0xf0 │ │ - ldc2l 4, cr6, [r6, #580] @ 0x244 │ │ + ldc2l 4, cr6, [r6, #760] @ 0x2f8 │ │ │ │ 024bce60 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d13} │ │ sub sp, sp, #760 @ 0x2f8 │ │ @@ -1432604,31 +1432604,31 @@ │ │ mov r0, r6 │ │ mov r2, sl │ │ movw r3, #514 @ 0x202 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 24bdc1c │ │ ldc2l 0, cr0, [r8, #984] @ 0x3d8 │ │ - ldc2l 14, cr5, [r6, #468] @ 0x1d4 │ │ + ldc2l 14, cr5, [r6, #648] @ 0x288 │ │ ldc2l 1, cr8, [r5, #460] @ 0x1cc │ │ ldc2l 14, cr15, [r7, #440] @ 0x1b8 │ │ - ldc2l 11, cr5, [r6, #948] @ 0x3b4 @ │ │ - ldc2l 3, cr14, [r6, #992] @ 0x3e0 │ │ + ldc2l 12, cr5, [r6, #104] @ 0x68 │ │ + ldc2l 4, cr14, [r6, #148] @ 0x94 │ │ ldc2l 5, cr10, [r8, #680] @ 0x2a8 │ │ ldc2l 8, cr7, [r8, #488] @ 0x1e8 │ │ - ldc2l 2, cr14, [r6, #224] @ 0xe0 │ │ + ldc2l 2, cr14, [r6, #404] @ 0x194 │ │ ldc2l 3, cr10, [r8, #936] @ 0x3a8 │ │ - ldc2l 2, cr14, [r6] │ │ + ldc2l 2, cr14, [r6, #180] @ 0xb4 │ │ ldc2l 3, cr10, [r8, #712] @ 0x2c8 │ │ - ldc2l 8, cr13, [r6, #336] @ 0x150 │ │ + vcadd.f32 d29, d22, d1, #270 │ │ ldc2l 10, cr9, [r8, #24] @ │ │ ldc2l 13, cr6, [r8, #504] @ 0x1f8 │ │ ldrdeq ip, [r9], -ip @ │ │ - ldc2l 5, cr13, [r6, #672] @ 0x2a0 │ │ - ldc2l 1, cr14, [r6, #736] @ 0x2e0 │ │ + ldc2l 5, cr13, [r6, #852] @ 0x354 │ │ + ldc2l 1, cr14, [r6, #916] @ 0x394 │ │ ldc2l 3, cr10, [r8, #424] @ 0x1a8 │ │ ldc2l 14, cr1, [r8, #472] @ 0x1d8 │ │ ldc2l 1, cr10, [r8, #1000] @ 0x3e8 │ │ ldc2l 12, cr1, [r8, #696] @ 0x2b8 │ │ ldc2l 0, cr10, [r8, #200] @ 0xc8 │ │ ldc2l 12, cr1, [r8, #488] @ 0x1e8 │ │ ldc2l 12, cr1, [r8, #264] @ 0x108 │ │ @@ -1432649,15 +1432649,15 @@ │ │ ldc2l 12, cr9, [r8, #360] @ 0x168 │ │ vcadd.f32 d17, d24, d18, #270 │ │ ldc2l 12, cr9, [r8, #152] @ 0x98 │ │ vcadd.f32 , q4, q15, #270 │ │ ldc2l 11, cr9, [r8, #968] @ 0x3c8 @ │ │ ldc2l 8, cr1, [r8, #216] @ 0xd8 │ │ ldc2l 11, cr9, [r8, #744] @ 0x2e8 @ │ │ - ldc2l 8, cr13, [r6, #832] @ 0x340 │ │ + ldc2l 8, cr13, [r6, #1012] @ 0x3f4 │ │ ldc2l 10, cr9, [r8, #520] @ 0x208 @ │ │ ldc2l 6, cr2, [r9, #352] @ 0x160 │ │ ldc2l 7, cr1, [r8, #488] @ 0x1e8 │ │ ldc2l 10, cr9, [r8, #1016] @ 0x3f8 @ │ │ ldc2l 14, cr6, [r8, #312] @ 0x138 │ │ ldc2l 10, cr9, [r8, #824] @ 0x338 @ │ │ ldc2l 5, cr4, [r8, #560] @ 0x230 │ │ @@ -1432971,24 +1432971,24 @@ │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 10, cr0, [r9, #72] @ 0x48 @ │ │ ldrbeq r4, [r7, #1304] @ 0x518 │ │ eoreq ip, r9, ip, asr #7 │ │ ldrbeq r4, [r7, #1284] @ 0x504 │ │ eoreq ip, r9, r8, lsl r2 │ │ eoreq ip, r9, r8, lsr r3 │ │ - ldc2l 3, cr7, [r6, #864] @ 0x360 │ │ - vcadd.f32 , , , #270 │ │ - ldc2l 12, cr4, [r6, #820] @ 0x334 │ │ + ldc2l 4, cr7, [r6, #20] │ │ + vcadd.f32 d29, d21, d14, #270 │ │ + ldc2l 12, cr4, [r6, #1000] @ 0x3e8 │ │ ldc2l 6, cr2, [r9, #60] @ 0x3c │ │ eoreq ip, r9, ip, asr #32 │ │ strdeq fp, [r9], -r4 @ │ │ ldc2l 2, cr3, [r8, #20] │ │ - ldc2l 10, cr4, [r6, #676] @ 0x2a4 @ │ │ + ldc2l 10, cr4, [r6, #856] @ 0x358 @ │ │ mlaeq r9, r0, pc, fp @ │ │ - ldc2l 12, cr4, [r7, #648] @ 0x288 │ │ + ldc2l 12, cr4, [r7, #828] @ 0x33c │ │ eoreq ip, r9, r4, lsr #32 │ │ ldc2l 5, cr0, [r9, #616] @ 0x268 │ │ │ │ 024be500 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #88 @ 0x58 │ │ @@ -1433495,24 +1433495,24 @@ │ │ ldr r0, [pc, #44] @ 24becf8 │ │ mov r1, #8 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 1, cr1, [r6, #732] @ 0x2dc │ │ + ldc2l 1, cr1, [r6, #912] @ 0x390 │ │ ldc2l 12, cr10, [r7, #748] @ 0x2ec │ │ eoreq fp, r9, r8, lsr #17 │ │ - ldc2l 2, cr13, [r6, #136] @ 0x88 │ │ - ldc2l 2, cr4, [r6, #564] @ 0x234 │ │ - ldc2l 15, cr10, [r6, #136] @ 0x88 │ │ - ldc2l 0, cr1, [r6, #412] @ 0x19c │ │ + ldc2l 2, cr13, [r6, #316] @ 0x13c │ │ + ldc2l 2, cr4, [r6, #744] @ 0x2e8 │ │ + ldc2l 15, cr10, [r6, #316] @ 0x13c │ │ + ldc2l 0, cr1, [r6, #592] @ 0x250 │ │ ldc2l 10, cr4, [r5, #912] @ 0x390 @ │ │ - ldc2l 2, cr4, [r6, #868] @ 0x364 │ │ - ldc2l 7, cr12, [r6, #660] @ 0x294 │ │ + ldc2l 3, cr4, [r6, #24] │ │ + ldc2l 7, cr12, [r6, #840] @ 0x348 │ │ │ │ 024bed08 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ mov r5, r2 │ │ mov r9, r1 │ │ @@ -1433632,15 +1433632,15 @@ │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 4, cr4, [r8, #904] @ 0x388 │ │ ldc2l 3, cr4, [r8, #388] @ 0x184 │ │ - ldc2l 5, cr0, [r7, #708] @ 0x2c4 │ │ + ldc2l 5, cr0, [r7, #888] @ 0x378 │ │ ldc2l 3, cr4, [r8, #232] @ 0xe8 │ │ │ │ 024bef04 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #12 │ │ sub r0, r0, #1 │ │ @@ -1433965,29 +1433965,29 @@ │ │ ldr r5, [r6, r5, lsl #2] │ │ add r7, r7, #1 │ │ cmp r5, #0 │ │ bgt 24bf40c │ │ b 24bf3e0 │ │ ldc2l 4, cr4, [r5, #940] @ 0x3ac │ │ ldc2l 2, cr11, [r8, #456] @ 0x1c8 │ │ - ldc2l 5, cr4, [r7, #172] @ 0xac │ │ + ldc2l 5, cr4, [r7, #352] @ 0x160 │ │ ldc2l 14, cr7, [r5, #668] @ 0x29c │ │ - ldc2l 4, cr4, [r7, #876] @ 0x36c │ │ - ldc2l 4, cr2, [r7, #220] @ 0xdc │ │ - ldc2l 4, cr2, [r7, #176] @ 0xb0 │ │ + ldc2l 5, cr4, [r7, #32] │ │ + ldc2l 4, cr2, [r7, #400] @ 0x190 │ │ + ldc2l 4, cr2, [r7, #356] @ 0x164 │ │ ldc2l 2, cr8, [r8, #880] @ 0x370 │ │ - ldc2l 13, cr0, [r6, #432] @ 0x1b0 │ │ + ldc2l 13, cr0, [r6, #612] @ 0x264 │ │ ldc2l 6, cr8, [r8, #248] @ 0xf8 │ │ ldc2l 7, cr12, [r7, #336] @ 0x150 │ │ - ldc2l 10, cr12, [r5, #688] @ 0x2b0 @ │ │ + ldc2l 10, cr12, [r5, #868] @ 0x364 @ │ │ vcadd.f32 d26, d7, d1, #270 │ │ - ldc2l 12, cr4, [r6, #140] @ 0x8c │ │ + ldc2l 12, cr4, [r6, #320] @ 0x140 │ │ ldc2l 15, cr9, [r8, #396] @ 0x18c │ │ ldc2l 9, cr6, [r5, #506] @ 0x1fa @ │ │ - ldc2l 14, cr3, [r6, #260] @ 0x104 │ │ + ldc2l 14, cr3, [r6, #440] @ 0x1b8 │ │ ldc2l 7, cr1, [r9, #604] @ 0x25c │ │ │ │ 024bf468 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ @@ -1434038,17 +1434038,17 @@ │ │ bl 270db90 │ │ ldr r0, [pc, #24] @ 24bf544 │ │ mov r1, #8 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2l 15, cr3, [r7, #716] @ 0x2cc │ │ + ldc2l 15, cr3, [r7, #896] @ 0x380 │ │ ldc2l 9, cr7, [r5, #102] @ 0x66 @ │ │ - ldc2l 15, cr3, [r7, #396] @ 0x18c │ │ + ldc2l 15, cr3, [r7, #576] @ 0x240 │ │ │ │ 024bf548 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #32 │ │ add r5, fp, #12 │ │ mov ip, r1 │ │ @@ -1434490,32 +1434490,32 @@ │ │ ldc2l 14, cr13, [r7, #776] @ 0x308 │ │ ldc2l 10, cr10, [r8, #1000] @ 0x3e8 @ │ │ ldc2l 15, cr1, [r8, #1020] @ 0x3fc │ │ strdeq sl, [r9], -ip @ │ │ ldc2l 15, cr1, [r8, #716] @ 0x2cc │ │ ldc2l 4, cr10, [r5, #428] @ 0x1ac │ │ ldc2l 12, cr3, [r5, #484] @ 0x1e4 │ │ - ldc2l 4, cr3, [r6, #196] @ 0xc4 │ │ + ldc2l 4, cr3, [r6, #376] @ 0x178 │ │ ldc2l 5, cr13, [r8, #800] @ 0x320 │ │ ldc2l 3, cr10, [r5, #908] @ 0x38c │ │ - ldc2l 12, cr1, [r7, #112] @ 0x70 │ │ + ldc2l 12, cr1, [r7, #292] @ 0x124 │ │ ldc2l 10, cr7, [r8, #816] @ 0x330 @ │ │ - ldc2l 4, cr12, [r6, #832] @ 0x340 │ │ + ldc2l 4, cr12, [r6, #1012] @ 0x3f4 │ │ ldc2l 12, cr3, [r5, #804] @ 0x324 │ │ - ldc2l 4, cr3, [r6, #516] @ 0x204 │ │ + ldc2l 4, cr3, [r6, #696] @ 0x2b8 │ │ ldc2l 6, cr13, [r8, #80] @ 0x50 │ │ - ldc2l 5, cr0, [r6, #800] @ 0x320 │ │ + ldc2l 5, cr0, [r6, #980] @ 0x3d4 │ │ ldc2l 14, cr7, [r8, #600] @ 0x258 │ │ ldc2l 15, cr11, [r7, #688] @ 0x2b0 │ │ - ldc2l 3, cr12, [r5, #16] │ │ + ldc2l 3, cr12, [r5, #196] @ 0xc4 │ │ ldc2l 0, cr10, [r7, #356] @ 0x164 │ │ - ldc2l 4, cr4, [r6, #492] @ 0x1ec │ │ + ldc2l 4, cr4, [r6, #672] @ 0x2a0 │ │ ldc2l 6, cr5, [r8, #736] @ 0x2e0 │ │ ldc2l 2, cr6, [r5, #340] @ 0x154 │ │ - ldc2l 6, cr3, [r6, #612] @ 0x264 │ │ + ldc2l 6, cr3, [r6, #792] @ 0x318 │ │ ldc2l 15, cr0, [r9, #972] @ 0x3cc │ │ │ │ 024bfc70 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ @@ -1434682,18 +1434682,18 @@ │ │ add r0, pc, r0 │ │ bl 270da10 │ │ mov r0, r4 │ │ mov r1, #7 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, fp, pc} │ │ - ldc2l 0, cr12, [r6, #612] @ 0x264 │ │ + ldc2l 0, cr12, [r6, #792] @ 0x318 │ │ ldc2l 7, cr7, [r8, #616] @ 0x268 │ │ - ldc2l 0, cr3, [r6, #260] @ 0x104 │ │ - ldc2l 14, cr5, [r6, #632] @ 0x278 │ │ + ldc2l 0, cr3, [r6, #440] @ 0x1b8 │ │ + ldc2l 14, cr5, [r6, #812] @ 0x32c │ │ │ │ 024bfefc : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r1 │ │ ldr r1, [pc, #4084] @ 24c0f04 │ │ mov r7, #0 │ │ @@ -1435716,250 +1435716,250 @@ │ │ mov r2, #36 @ 0x24 │ │ str r0, [r5, #480] @ 0x1e0 │ │ movw r0, #4320 @ 0x10e0 │ │ ldr r1, [pc, #480] @ 24c10e4 │ │ b 24c12bc │ │ ldc2l 9, cr13, [r7, #224] @ 0xe0 @ │ │ vcadd.f32 , , q1, #270 │ │ - ldc2l 10, cr15, [r6, #216] @ 0xd8 @ │ │ + ldc2l 10, cr15, [r6, #396] @ 0x18c @ │ │ ldc2l 7, cr7, [r8, #76] @ 0x4c │ │ - ldc2l 15, cr11, [r6, #628] @ 0x274 │ │ - ldc2l 11, cr13, [r5, #388] @ 0x184 @ │ │ + ldc2l 15, cr11, [r6, #808] @ 0x328 │ │ + ldc2l 11, cr13, [r5, #568] @ 0x238 @ │ │ ldc2l 7, cr3, [r5, #516] @ 0x204 │ │ - ldc2l 13, cr5, [r6, #592] @ 0x250 │ │ + ldc2l 13, cr5, [r6, #772] @ 0x304 │ │ ldc2l 15, cr8, [r8, #976] @ 0x3d0 │ │ ldc2l 14, cr4, [r8, #852] @ 0x354 │ │ - ldc2l 9, cr15, [r6, #204] @ 0xcc @ │ │ - ldc2l 7, cr7, [r7, #208] @ 0xd0 │ │ - ldc2l 12, cr9, [r6, #684] @ 0x2ac │ │ - ldc2l 5, cr5, [r7, #608] @ 0x260 │ │ + ldc2l 9, cr15, [r6, #294] @ 0x126 @ │ │ + ldc2l 7, cr7, [r7, #388] @ 0x184 │ │ + ldc2l 12, cr9, [r6, #864] @ 0x360 │ │ + ldc2l 5, cr5, [r7, #788] @ 0x314 │ │ ldc2l 11, cr10, [r8, #888] @ 0x378 @ │ │ ldc2l 14, cr9, [r5, #272] @ 0x110 │ │ - vcadd.f32 , q11, q6, #270 │ │ - ldc2l 7, cr13, [r6, #232] @ 0xe8 │ │ + ldc2l 8, cr15, [r6, #996] @ 0x3e4 │ │ + ldc2l 7, cr13, [r6, #412] @ 0x19c │ │ ldc2l 13, cr9, [r5, #1020] @ 0x3fc │ │ ldc2l 13, cr4, [r8, #780] @ 0x30c │ │ - vcadd.f32 , q3, q11, #270 │ │ - ldc2l 11, cr15, [r5, #744] @ 0x2e8 @ │ │ + ldc2l 8, cr15, [r6, #588] @ 0x24c │ │ + ldc2l 11, cr15, [r5, #924] @ 0x39c @ │ │ ldc2l 15, cr7, [r5, #932] @ 0x3a4 │ │ - ldc2l 5, cr7, [r7, #884] @ 0x374 │ │ + ldc2l 6, cr7, [r7, #40] @ 0x28 │ │ ldc2l 6, cr9, [r7, #524] @ 0x20c │ │ - ldc2l 12, cr1, [r6, #368] @ 0x170 │ │ + ldc2l 12, cr1, [r6, #548] @ 0x224 │ │ ldc2l 0, cr3, [r8, #192] @ 0xc0 │ │ ldc2l 5, cr5, [r5, #108] @ 0x6c │ │ - ldc2l 10, cr7, [r6, #352] @ 0x160 @ │ │ + ldc2l 10, cr7, [r6, #532] @ 0x214 @ │ │ ldc2l 5, cr15, [r7, #992] @ 0x3e0 │ │ ldc2l 12, cr9, [r5, #564] @ 0x234 │ │ ldc2l 9, cr10, [r8, #418] @ 0x1a2 @ │ │ - ldc2l 11, cr1, [r6, #480] @ 0x1e0 @ │ │ - ldc2l 11, cr1, [r6, #368] @ 0x170 @ │ │ + ldc2l 11, cr1, [r6, #660] @ 0x294 @ │ │ + ldc2l 11, cr1, [r6, #548] @ 0x224 @ │ │ ldc2l 14, cr7, [r5, #392] @ 0x188 │ │ ldc2l 14, cr7, [r5, #276] @ 0x114 │ │ - ldc2l 7, cr11, [r5, #432] @ 0x1b0 │ │ + ldc2l 7, cr11, [r5, #612] @ 0x264 │ │ ldc2l 3, cr3, [r5, #760] @ 0x2f8 │ │ - ldc2l 4, cr13, [r6, #592] @ 0x250 │ │ + ldc2l 4, cr13, [r6, #772] @ 0x304 │ │ ldc2l 4, cr13, [r7, #688] @ 0x2b0 │ │ ldc2l 14, cr2, [r8, #328] @ 0x148 │ │ - ldc2l 9, cr9, [r6, #6] @ │ │ + ldc2l 9, cr9, [r6, #96] @ 0x60 @ │ │ ldc2l 5, cr14, [r8, #956] @ 0x3bc │ │ ldc2l 4, cr13, [r7, #152] @ 0x98 │ │ - vcadd.f32 d23, d6, d29, #270 │ │ - ldc2l 8, cr5, [r6, #852] @ 0x354 │ │ + ldc2l 8, cr7, [r6, #360] @ 0x168 │ │ + ldc2l 9, cr5, [r6, #4] @ │ │ ldc2l 1, cr7, [r8, #744] @ 0x2e8 │ │ - ldc2l 2, cr1, [r7, #516] @ 0x204 │ │ - ldc2l 7, cr7, [r6, #672] @ 0x2a0 │ │ + ldc2l 2, cr1, [r7, #696] @ 0x2b8 │ │ + ldc2l 7, cr7, [r6, #852] @ 0x354 │ │ ldc2l 3, cr13, [r7, #368] @ 0x170 │ │ ldc2l 12, cr2, [r8, #1004] @ 0x3ec │ │ ldc2l 1, cr7, [r8, #64] @ 0x40 │ │ - ldc2l 2, cr13, [r6, #720] @ 0x2d0 │ │ - ldc2l 9, cr11, [r6, #232] @ 0xe8 @ │ │ + ldc2l 2, cr13, [r6, #900] @ 0x384 │ │ + ldc2l 9, cr11, [r6, #322] @ 0x142 @ │ │ ldc2l 2, cr9, [r7, #444] @ 0x1bc │ │ ldc2l 2, cr15, [r7, #436] @ 0x1b4 │ │ - ldc2l 9, cr11, [r6, #42] @ 0x2a @ │ │ + ldc2l 9, cr11, [r6, #132] @ 0x84 @ │ │ ldc2l 12, cr2, [r8, #64] @ 0x40 │ │ - ldc2l 7, cr1, [r6, #972] @ 0x3cc │ │ - ldc2l 7, cr1, [r6, #856] @ 0x358 │ │ - ldc2l 6, cr7, [r6, #40] @ 0x28 │ │ - ldc2l 6, cr5, [r6, #680] @ 0x2a8 │ │ + vcadd.f32 d17, d6, d16, #270 │ │ + vcadd.f32 d17, d6, d3, #270 │ │ + ldc2l 6, cr7, [r6, #220] @ 0xdc │ │ + ldc2l 6, cr5, [r6, #860] @ 0x35c │ │ ldc2l 1, cr9, [r7, #388] @ 0x184 │ │ ldc2l 11, cr2, [r8, #272] @ 0x110 @ │ │ - ldc2l 6, cr15, [r5, #4] │ │ + ldc2l 6, cr15, [r5, #184] @ 0xb8 │ │ ldc2l 2, cr14, [r8, #848] @ 0x350 │ │ ldc2l 0, cr9, [r7, #888] @ 0x378 │ │ ldc2l 0, cr13, [r7, #956] @ 0x3bc │ │ ldc2l 14, cr6, [r8, #808] @ 0x328 │ │ - ldc2l 6, cr1, [r6, #528] @ 0x210 │ │ + ldc2l 6, cr1, [r6, #708] @ 0x2c4 │ │ ldc2l 0, cr13, [r7, #576] @ 0x240 │ │ - ldc2l 5, cr5, [r6, #324] @ 0x144 │ │ - ldc2l 15, cr6, [r7, #280] @ 0x118 │ │ + ldc2l 5, cr5, [r6, #504] @ 0x1f8 │ │ + ldc2l 15, cr6, [r7, #460] @ 0x1cc │ │ ldc2l 9, cr7, [r5, #60] @ 0x3c @ │ │ - ldc2l 15, cr12, [r6, #736] @ 0x2e0 │ │ + ldc2l 15, cr12, [r6, #916] @ 0x394 │ │ ldc2l 6, cr9, [r5, #432] @ 0x1b0 │ │ - ldc2l 5, cr1, [r6, #596] @ 0x254 │ │ + ldc2l 5, cr1, [r6, #776] @ 0x308 │ │ ldc2l 15, cr15, [r8, #384] @ 0x180 │ │ - ldc2l 3, cr9, [r6, #1000] @ 0x3e8 │ │ + ldc2l 4, cr9, [r6, #156] @ 0x9c │ │ ldc2l 15, cr12, [r7, #372] @ 0x174 │ │ ldc2l 15, cr12, [r7, #280] @ 0x118 │ │ ldc2l 13, cr10, [r7, #856] @ 0x358 │ │ - ldc2l 3, cr5, [r6, #872] @ 0x368 │ │ + ldc2l 4, cr5, [r6, #28] │ │ vcadd.f32 d18, d24, d14, #270 │ │ - ldc2l 4, cr1, [r6, #544] @ 0x220 │ │ - ldc2l 12, cr4, [r7, #48] @ 0x30 │ │ - ldc2l 0, cr13, [r5, #808] @ 0x328 │ │ + ldc2l 4, cr1, [r6, #724] @ 0x2d4 │ │ + ldc2l 12, cr4, [r7, #228] @ 0xe4 │ │ + ldc2l 0, cr13, [r5, #988] @ 0x3dc │ │ ldc2l 14, cr8, [r7, #24] │ │ - ldc2l 9, cr2, [r7, #496] @ 0x1f0 @ │ │ - ldc2l 3, cr1, [r6, #892] @ 0x37c │ │ + ldc2l 10, cr2, [r7, #148] @ 0x94 @ │ │ + ldc2l 4, cr1, [r6, #48] @ 0x30 │ │ ldc2l 7, cr2, [r8, #632] @ 0x278 │ │ - ldc2l 11, cr4, [r7, #248] @ 0xf8 @ │ │ - ldc2l 4, cr11, [r6, #196] @ 0xc4 │ │ + ldc2l 11, cr4, [r7, #428] @ 0x1ac @ │ │ + ldc2l 4, cr11, [r6, #376] @ 0x178 │ │ ldc2l 5, cr12, [r8, #436] @ 0x1b4 │ │ ldc2l 6, cr7, [r5, #272] @ 0x110 │ │ ldc2l 4, cr8, [r8, #432] @ 0x1b0 │ │ ldc2l 12, cr8, [r7, #852] @ 0x354 │ │ - ldc2l 15, cr12, [r5, #336] @ 0x150 │ │ - ldc2l 1, cr5, [r6, #704] @ 0x2c0 │ │ - ldc2l 3, cr11, [r6, #260] @ 0x104 │ │ - ldc2l 1, cr15, [r5, #120] @ 0x78 │ │ - ldc2l 9, cr4, [r7, #470] @ 0x1d6 @ │ │ - ldc2l 13, cr14, [r6, #356] @ 0x164 │ │ - ldc2l 14, cr12, [r5, #544] @ 0x220 │ │ + ldc2l 15, cr12, [r5, #516] @ 0x204 │ │ + ldc2l 1, cr5, [r6, #884] @ 0x374 │ │ + ldc2l 3, cr11, [r6, #440] @ 0x1b8 │ │ + ldc2l 1, cr15, [r5, #300] @ 0x12c │ │ + ldc2l 10, cr4, [r7, #96] @ 0x60 @ │ │ + ldc2l 13, cr14, [r6, #536] @ 0x218 │ │ + ldc2l 14, cr12, [r5, #724] @ 0x2d4 │ │ ldc2l 15, cr9, [r8, #896] @ 0x380 │ │ ldc2l 2, cr9, [r5, #360] @ 0x168 │ │ - ldc2l 2, cr11, [r6, #332] @ 0x14c │ │ + ldc2l 2, cr11, [r6, #512] @ 0x200 │ │ ldc2l 11, cr8, [r7, #352] @ 0x160 @ │ │ ldc2l 1, cr9, [r5, #996] @ 0x3e4 │ │ - ldc2l 13, cr12, [r5, #756] @ 0x2f4 │ │ - ldc2l 13, cr10, [r5, #340] @ 0x154 │ │ - ldc2l 9, cr0, [r7, #404] @ 0x194 @ │ │ + ldc2l 13, cr12, [r5, #936] @ 0x3a8 │ │ + ldc2l 13, cr10, [r5, #520] @ 0x208 │ │ + ldc2l 9, cr0, [r7, #494] @ 0x1ee @ │ │ ldc2l 10, cr8, [r7, #724] @ 0x2d4 @ │ │ - ldc2l 10, cr12, [r6, #440] @ 0x1b8 @ │ │ - ldc2l 11, cr14, [r6, #740] @ 0x2e4 @ │ │ - ldc2l 12, cr12, [r5, #976] @ 0x3d0 │ │ + ldc2l 10, cr12, [r6, #620] @ 0x26c @ │ │ + ldc2l 11, cr14, [r6, #920] @ 0x398 @ │ │ + ldc2l 13, cr12, [r5, #132] @ 0x84 │ │ ldc2l 3, cr7, [r5, #280] @ 0x118 │ │ ldc2l 12, cr4, [r5, #168] @ 0xa8 │ │ - ldc2l 12, cr12, [r5, #568] @ 0x238 │ │ - ldc2l 14, cr8, [r6, #384] @ 0x180 │ │ + ldc2l 12, cr12, [r5, #748] @ 0x2ec │ │ + ldc2l 14, cr8, [r6, #564] @ 0x234 │ │ ldc2l 3, cr6, [r8, #964] @ 0x3c4 │ │ ldc2l 4, cr2, [r5, #540] @ 0x21c │ │ - ldc2l 10, cr14, [r5, #388] @ 0x184 @ │ │ - vcadd.f32 d28, d5, d25, #270 │ │ + ldc2l 10, cr14, [r5, #568] @ 0x238 @ │ │ + ldc2l 8, cr12, [r5, #344] @ 0x158 │ │ ldc2l 11, cr3, [r8, #836] @ 0x344 @ │ │ - ldc2l 2, cr4, [r7, #908] @ 0x38c │ │ + ldc2l 3, cr4, [r7, #64] @ 0x40 │ │ ldc2l 4, cr14, [r7, #992] @ 0x3e0 │ │ - ldc2l 9, cr4, [r6, #496] @ 0x1f0 @ │ │ + ldc2l 10, cr4, [r6, #148] @ 0x94 @ │ │ ldc2l 6, cr13, [r8, #480] @ 0x1e0 │ │ ldc2l 11, cr8, [r5, #352] @ 0x160 @ │ │ - ldc2l 9, cr4, [r6, #298] @ 0x12a @ │ │ + ldc2l 9, cr4, [r6, #388] @ 0x184 @ │ │ ldc2l 3, cr2, [r5, #176] @ 0xb0 │ │ - ldc2l 1, cr4, [r7, #968] @ 0x3c8 │ │ - ldc2l 8, cr8, [r6, #736] @ 0x2e0 │ │ - ldc2l 2, cr0, [r7, #900] @ 0x384 │ │ + ldc2l 2, cr4, [r7, #124] @ 0x7c │ │ + vcadd.f32 q12, q11, , #270 │ │ + ldc2l 3, cr0, [r7, #56] @ 0x38 │ │ ldc2l 5, cr13, [r8, #536] @ 0x218 │ │ - ldc2l 6, cr10, [r5, #8] │ │ + ldc2l 6, cr10, [r5, #188] @ 0xbc │ │ ldc2l 10, cr8, [r5, #244] @ 0xf4 @ │ │ ldc2l 10, cr8, [r5, #132] @ 0x84 @ │ │ - ldc2l 9, cr0, [r6, #120] @ 0x78 @ │ │ + ldc2l 9, cr0, [r6, #210] @ 0xd2 @ │ │ ldc2l 9, cr3, [r8, #316] @ 0x13c @ │ │ ldc2l 12, cr1, [r8, #864] @ 0x360 │ │ ldc2l 1, cr0, [r8, #256] @ 0x100 │ │ ldc2l 4, cr13, [r8, #432] @ 0x1b0 │ │ - ldc2l 7, cr8, [r6, #216] @ 0xd8 │ │ + ldc2l 7, cr8, [r6, #396] @ 0x18c │ │ ldc2l 2, cr14, [r7, #368] @ 0x170 │ │ ldc2l 12, cr1, [r8, #192] @ 0xc0 │ │ ldc2l 2, cr8, [r7, #120] @ 0x78 │ │ vcadd.f32 d19, d24, d10, #270 │ │ ldc2l 9, cr7, [r8, #126] @ 0x7e @ │ │ ldc2l 3, cr13, [r8, #496] @ 0x1f0 │ │ ldc2l 1, cr14, [r7, #560] @ 0x230 │ │ ldc2l 1, cr8, [r7, #460] @ 0x1cc │ │ ldc2l 5, cr9, [r8, #352] @ 0x160 │ │ - ldc2l 5, cr8, [r6, #860] @ 0x35c │ │ - ldc2l 0, cr12, [r6, #872] @ 0x368 │ │ + ldc2l 6, cr8, [r6, #16] │ │ + ldc2l 1, cr12, [r6, #28] │ │ ldc2l 10, cr1, [r8, #828] @ 0x33c @ │ │ - ldc2l 6, cr0, [r6, #760] @ 0x2f8 │ │ - ldc2l 12, cr1, [r7, #552] @ 0x228 │ │ + ldc2l 6, cr0, [r6, #940] @ 0x3ac │ │ + ldc2l 12, cr1, [r7, #732] @ 0x2dc │ │ ldc2l 4, cr9, [r8, #532] @ 0x214 │ │ - ldc2l 12, cr1, [r7, #316] @ 0x13c │ │ - ldc2l 15, cr5, [r7, #256] @ 0x100 │ │ - ldc2l 4, cr8, [r6, #780] @ 0x30c │ │ - ldc2l 4, cr14, [r5, #716] @ 0x2cc │ │ - ldc2l 3, cr2, [r6, #772] @ 0x304 │ │ - ldc2l 0, cr14, [r6, #912] @ 0x390 │ │ - ldc2l 3, cr6, [r6, #696] @ 0x2b8 │ │ + ldc2l 12, cr1, [r7, #496] @ 0x1f0 │ │ + ldc2l 15, cr5, [r7, #436] @ 0x1b4 │ │ + ldc2l 4, cr8, [r6, #960] @ 0x3c0 │ │ + ldc2l 4, cr14, [r5, #896] @ 0x380 │ │ + ldc2l 3, cr2, [r6, #952] @ 0x3b8 │ │ + ldc2l 1, cr14, [r6, #68] @ 0x44 │ │ + ldc2l 3, cr6, [r6, #876] @ 0x36c │ │ ldc2l 9, cr1, [r8, #160] @ 0xa0 @ │ │ - ldc2l 5, cr10, [r6, #1000] @ 0x3e8 │ │ + ldc2l 6, cr10, [r6, #156] @ 0x9c │ │ ldc2l 3, cr9, [r8, #168] @ 0xa8 │ │ ldc2l 13, cr15, [r7, #380] @ 0x17c │ │ - ldc2l 3, cr4, [r6, #888] @ 0x378 │ │ + ldc2l 4, cr4, [r6, #44] @ 0x2c │ │ ldc2l 14, cr7, [r7, #700] @ 0x2bc │ │ - ldc2l 13, cr5, [r7, #612] @ 0x264 │ │ + ldc2l 13, cr5, [r7, #792] @ 0x318 │ │ ldc2l 13, cr9, [r7, #220] @ 0xdc │ │ ldc2l 12, cr5, [r8, #284] @ 0x11c │ │ ldc2l 12, cr1, [r5, #936] @ 0x3a8 │ │ - ldc2l 13, cr14, [r6, #300] @ 0x12c │ │ + ldc2l 13, cr14, [r6, #480] @ 0x1e0 │ │ ldc2l 12, cr9, [r7, #716] @ 0x2cc │ │ ldc2l 7, cr1, [r8, #684] @ 0x2ac │ │ ldc2l 4, cr3, [r8, #112] @ 0x70 │ │ - ldc2l 0, cr12, [r5, #96] @ 0x60 │ │ + ldc2l 0, cr12, [r5, #276] @ 0x114 │ │ ldc2l 12, cr1, [r5, #108] @ 0x6c │ │ ldc2l 11, cr15, [r7, #608] @ 0x260 @ │ │ - ldc2l 3, cr0, [r6, #8] │ │ + ldc2l 3, cr0, [r6, #188] @ 0xbc │ │ ldc2l 10, cr5, [r8, #944] @ 0x3b0 @ │ │ - ldc2l 11, cr15, [r6, #664] @ 0x298 @ │ │ - ldc2l 14, cr9, [r5, #980] @ 0x3d4 │ │ - ldc2l 12, cr11, [r6, #296] @ 0x128 │ │ + ldc2l 11, cr15, [r6, #844] @ 0x34c @ │ │ + ldc2l 15, cr9, [r5, #136] @ 0x88 │ │ + ldc2l 12, cr11, [r6, #476] @ 0x1dc │ │ ldc2l 4, cr11, [r8, #432] @ 0x1b0 │ │ - ldc2l 14, cr11, [r5, #940] @ 0x3ac │ │ - ldc2l 9, cr3, [r7, #410] @ 0x19a @ │ │ - ldc2l 9, cr3, [r7, #346] @ 0x15a @ │ │ - ldc2l 0, cr6, [r6, #56] @ 0x38 │ │ + ldc2l 15, cr11, [r5, #96] @ 0x60 │ │ + ldc2l 9, cr3, [r7, #500] @ 0x1f4 @ │ │ + ldc2l 9, cr3, [r7, #436] @ 0x1b4 @ │ │ + ldc2l 0, cr6, [r6, #236] @ 0xec │ │ ldc2l 10, cr15, [r7, #168] @ 0xa8 @ │ │ - ldc2l 7, cr1, [r7, #596] @ 0x254 │ │ + ldc2l 7, cr1, [r7, #776] @ 0x308 │ │ ldc2l 11, cr11, [r7, #568] @ 0x238 @ │ │ - ldc2l 13, cr9, [r5, #644] @ 0x284 │ │ - ldc2l 1, cr0, [r6, #236] @ 0xec │ │ + ldc2l 13, cr9, [r5, #824] @ 0x338 │ │ + ldc2l 1, cr0, [r6, #416] @ 0x1a0 │ │ ldc2l 13, cr3, [r5, #152] @ 0x98 │ │ - ldc2l 10, cr11, [r6, #860] @ 0x35c @ │ │ - ldc2l 15, cr3, [r6, #872] @ 0x368 │ │ + ldc2l 11, cr11, [r6, #16] @ │ │ + ldc2l 0, cr4, [r6, #28] │ │ ldc2l 1, cr8, [r5, #368] @ 0x170 │ │ ldc2l 12, cr12, [r8, #300] @ 0x12c │ │ - ldc2l 14, cr5, [r6, #612] @ 0x264 │ │ - ldc2l 14, cr5, [r6, #488] @ 0x1e8 │ │ - ldc2l 6, cr1, [r7, #144] @ 0x90 │ │ + ldc2l 14, cr5, [r6, #792] @ 0x318 │ │ + ldc2l 14, cr5, [r6, #668] @ 0x29c │ │ + ldc2l 6, cr1, [r7, #324] @ 0x144 │ │ ldc2l 2, cr11, [r8, #68] @ 0x44 │ │ ldc2l 3, cr1, [r8, #848] @ 0x350 │ │ - ldc2l 14, cr3, [r6, #880] @ 0x370 │ │ + ldc2l 15, cr3, [r6, #36] @ 0x24 │ │ ldc2l 13, cr8, [r8, #688] @ 0x2b0 │ │ ldc2l 13, cr8, [r8, #636] @ 0x27c │ │ - ldc2l 14, cr3, [r6, #448] @ 0x1c0 │ │ - ldc2l 11, cr9, [r5, #600] @ 0x258 @ │ │ + ldc2l 14, cr3, [r6, #628] @ 0x274 │ │ + ldc2l 11, cr9, [r5, #780] @ 0x30c @ │ │ ldc2l 9, cr7, [r7, #46] @ 0x2e @ │ │ vcadd.f32 q15, q12, , #270 │ │ - ldc2l 11, cr9, [r5, #164] @ 0xa4 @ │ │ + ldc2l 11, cr9, [r5, #344] @ 0x158 @ │ │ ldc2l 10, cr3, [r5, #824] @ 0x338 @ │ │ - ldc2l 9, cr13, [r6, #396] @ 0x18c @ │ │ - ldc2l 11, cr11, [r5, #140] @ 0x8c @ │ │ - ldc2l 4, cr1, [r7, #300] @ 0x12c │ │ - ldc2l 7, cr15, [r6, #88] @ 0x58 │ │ + ldc2l 9, cr13, [r6, #486] @ 0x1e6 @ │ │ + ldc2l 11, cr11, [r5, #320] @ 0x140 @ │ │ + ldc2l 4, cr1, [r7, #480] @ 0x1e0 │ │ + ldc2l 7, cr15, [r6, #268] @ 0x10c │ │ ldc2l 6, cr15, [r7, #560] @ 0x230 │ │ - ldc2l 6, cr5, [r7, #1012] @ 0x3f4 │ │ - ldc2l 7, cr11, [r6, #728] @ 0x2d8 │ │ + ldc2l 7, cr5, [r7, #168] @ 0xa8 │ │ + ldc2l 7, cr11, [r6, #908] @ 0x38c │ │ ldc2l 0, cr6, [r5, #744] @ 0x2e8 │ │ - ldc2l 7, cr11, [r6, #476] @ 0x1dc │ │ + ldc2l 7, cr11, [r6, #656] @ 0x290 │ │ ldc2l 13, cr2, [r8, #984] @ 0x3d8 │ │ - ldc2l 3, cr1, [r7, #252] @ 0xfc │ │ + ldc2l 3, cr1, [r7, #432] @ 0x1b0 │ │ ldc2l 5, cr15, [r7, #672] @ 0x2a0 │ │ ldc2l 7, cr11, [r7, #128] @ 0x80 │ │ ldc2l 13, cr2, [r8, #456] @ 0x1c8 │ │ ldc2l 14, cr10, [r8, #876] @ 0x36c │ │ - ldc2l 2, cr1, [r7, #644] @ 0x284 │ │ + ldc2l 2, cr1, [r7, #824] @ 0x338 │ │ ldc2l 5, cr9, [r7, #372] @ 0x174 │ │ ldc2l 5, cr1, [r5, #140] @ 0x8c │ │ - ldc2l 7, cr13, [r6, #448] @ 0x1c0 │ │ - ldc2l 10, cr1, [r6, #36] @ 0x24 @ │ │ + ldc2l 7, cr13, [r6, #628] @ 0x274 │ │ + ldc2l 10, cr1, [r6, #216] @ 0xd8 @ │ │ add r0, r4, r0 │ │ mov r3, #5 │ │ add r1, pc, r1 │ │ bl 270d9e0 │ │ movw r0, #637 @ 0x27d │ │ mov r2, #36 @ 0x24 │ │ str r0, [r5, #484] @ 0x1e4 │ │ @@ -1438001,252 +1438001,252 @@ │ │ bl 270d9e0 │ │ ldr r1, [pc, #496] @ 24c34a0 │ │ movw r0, #12924 @ 0x327c │ │ add r0, r4, r0 │ │ mvn r6, #155 @ 0x9b │ │ b 24c367c │ │ ldc2l 4, cr1, [r5, #788] @ 0x314 │ │ - ldc2l 10, cr13, [r5, #556] @ 0x22c @ │ │ - ldc2l 3, cr3, [r7, #424] @ 0x1a8 │ │ - ldc2l 12, cr9, [r6, #276] @ 0x114 │ │ + ldc2l 10, cr13, [r5, #736] @ 0x2e0 @ │ │ + ldc2l 3, cr3, [r7, #604] @ 0x25c │ │ + ldc2l 12, cr9, [r6, #456] @ 0x1c8 │ │ ldc2l 4, cr9, [r7, #420] @ 0x1a4 │ │ ldc2l 7, cr12, [r8, #12] │ │ ldc2l 3, cr5, [r8, #228] @ 0xe4 │ │ ldc2l 7, cr3, [r5, #196] @ 0xc4 │ │ ldc2l 14, cr0, [r8, #900] @ 0x384 │ │ - ldc2l 0, cr1, [r7, #860] @ 0x35c │ │ + ldc2l 1, cr1, [r7, #16] │ │ ldc2l 11, cr2, [r8, #220] @ 0xdc @ │ │ - ldc2l 2, cr3, [r7, #248] @ 0xf8 │ │ + ldc2l 2, cr3, [r7, #428] @ 0x1ac │ │ ldc2l 11, cr7, [r5, #120] @ 0x78 @ │ │ - ldc2l 6, cr11, [r5, #960] @ 0x3c0 │ │ - ldc2l 8, cr5, [r6, #324] @ 0x144 │ │ - ldc2l 0, cr1, [r7, #88] @ 0x58 │ │ - ldc2l 2, cr5, [r7, #1000] @ 0x3e8 │ │ + ldc2l 7, cr11, [r5, #116] @ 0x74 │ │ + ldc2l 8, cr5, [r6, #504] @ 0x1f8 │ │ + ldc2l 0, cr1, [r7, #268] @ 0x10c │ │ + ldc2l 3, cr5, [r7, #156] @ 0x9c │ │ ldc2l 3, cr11, [r7, #932] @ 0x3a4 │ │ - ldc2l 15, cr0, [r7, #760] @ 0x2f8 │ │ + ldc2l 15, cr0, [r7, #940] @ 0x3ac │ │ ldc2l 13, cr0, [r8, #456] @ 0x1c8 │ │ - ldc2l 4, cr13, [r6, #604] @ 0x25c │ │ - ldc2l 7, cr13, [r5, #1008] @ 0x3f0 │ │ + ldc2l 4, cr13, [r6, #784] @ 0x310 │ │ + vcadd.f32 d29, d5, d25, #270 │ │ ldc2l 9, cr7, [r5, #434] @ 0x1b2 @ │ │ - ldc2l 1, cr15, [r6, #860] @ 0x35c │ │ - ldc2l 6, cr1, [r6, #724] @ 0x2d4 │ │ + ldc2l 2, cr15, [r6, #16] │ │ + ldc2l 6, cr1, [r6, #904] @ 0x388 │ │ ldc2l 2, cr14, [r8, #476] @ 0x1dc │ │ ldc2l 1, cr9, [r7, #488] @ 0x1e8 │ │ - ldc2l 2, cr11, [r6, #388] @ 0x184 │ │ - ldc2l 4, cr11, [r5, #976] @ 0x3d0 │ │ + ldc2l 2, cr11, [r6, #568] @ 0x238 │ │ + ldc2l 5, cr11, [r5, #132] @ 0x84 │ │ ldc2l 3, cr12, [r8, #924] @ 0x39c │ │ ldc2l 2, cr7, [r7, #32] │ │ ldc2l 1, cr13, [r7, #820] @ 0x334 │ │ - ldc2l 6, cr13, [r5, #532] @ 0x214 │ │ + ldc2l 6, cr13, [r5, #712] @ 0x2c8 │ │ ldc2l 3, cr3, [r5, #808] @ 0x328 │ │ ldc2l 3, cr12, [r8, #240] @ 0xf0 │ │ ldc2l 15, cr14, [r7, #884] @ 0x374 │ │ - ldc2l 7, cr9, [r6, #1000] @ 0x3e8 │ │ - ldc2l 5, cr7, [r6, #756] @ 0x2f4 │ │ + vcadd.f32 d25, d6, d23, #270 │ │ + ldc2l 5, cr7, [r6, #936] @ 0x3a8 │ │ ldc2l 9, cr10, [r8, #28] @ │ │ - ldc2l 6, cr15, [r5, #900] @ 0x384 │ │ - ldc2l 5, cr3, [r6, #796] @ 0x31c │ │ + ldc2l 7, cr15, [r5, #56] @ 0x38 │ │ + ldc2l 5, cr3, [r6, #976] @ 0x3d0 │ │ ldc2l 7, cr7, [r5, #396] @ 0x18c │ │ ldc2l 0, cr7, [r7, #496] @ 0x1f0 │ │ ldc2l 10, cr0, [r8, #328] @ 0x148 @ │ │ - ldc2l 6, cr15, [r5, #232] @ 0xe8 │ │ + ldc2l 6, cr15, [r5, #412] @ 0x19c │ │ ldc2l 14, cr14, [r7, #640] @ 0x280 │ │ ldc2l 6, cr2, [r8, #492] @ 0x1ec │ │ ldc2l 9, cr0, [r8, #408] @ 0x198 @ │ │ - ldc2l 0, cr13, [r6, #948] @ 0x3b4 │ │ + ldc2l 1, cr13, [r6, #104] @ 0x68 │ │ ldc2l 15, cr12, [r7, #464] @ 0x1d0 │ │ ldc2l 3, cr8, [r8, #476] @ 0x1dc │ │ - ldc2l 3, cr7, [r6, #980] @ 0x3d4 │ │ - ldc2l 5, cr15, [r5, #168] @ 0xa8 │ │ + ldc2l 4, cr7, [r6, #136] @ 0x88 │ │ + ldc2l 5, cr15, [r5, #348] @ 0x15c │ │ ldc2l 15, cr10, [r7, #216] @ 0xd8 │ │ ldc2l 7, cr10, [r8, #72] @ 0x48 │ │ ldc2l 0, cr3, [r5, #936] @ 0x3a8 │ │ - ldc2l 13, cr14, [r6, #572] @ 0x23c │ │ - ldc2l 10, cr0, [r7, #700] @ 0x2bc @ │ │ - ldc2l 13, cr14, [r6, #284] @ 0x11c │ │ + ldc2l 13, cr14, [r6, #752] @ 0x2f0 │ │ + ldc2l 10, cr0, [r7, #880] @ 0x370 @ │ │ + ldc2l 13, cr14, [r6, #464] @ 0x1d0 │ │ ldc2l 14, cr10, [r7, #440] @ 0x1b8 │ │ - ldc2l 2, cr5, [r6, #264] @ 0x108 │ │ - ldc2l 4, cr9, [r6, #664] @ 0x298 │ │ - ldc2l 1, cr1, [r6, #760] @ 0x2f8 │ │ + ldc2l 2, cr5, [r6, #444] @ 0x1bc │ │ + ldc2l 4, cr9, [r6, #844] @ 0x34c │ │ + ldc2l 1, cr1, [r6, #940] @ 0x3ac │ │ ldc2l 11, cr4, [r8, #684] @ 0x2ac @ │ │ - ldc2l 9, cr1, [r7, #384] @ 0x180 @ │ │ - ldc2l 13, cr10, [r6, #372] @ 0x174 │ │ - ldc2l 12, cr14, [r6, #368] @ 0x170 │ │ + ldc2l 9, cr1, [r7, #474] @ 0x1da @ │ │ + ldc2l 13, cr10, [r6, #552] @ 0x228 │ │ + ldc2l 12, cr14, [r6, #548] @ 0x224 │ │ ldc2l 13, cr10, [r7, #376] @ 0x178 │ │ - ldc2l 1, cr13, [r5, #792] @ 0x318 │ │ + ldc2l 1, cr13, [r5, #972] @ 0x3cc │ │ ldc2l 10, cr4, [r8, #976] @ 0x3d0 @ │ │ - ldc2l 3, cr9, [r6, #596] @ 0x254 │ │ + ldc2l 3, cr9, [r6, #776] @ 0x308 │ │ ldc2l 3, cr2, [r8, #172] @ 0xac │ │ ldc2l 3, cr6, [r8, #792] @ 0x318 │ │ ldc2l 12, cr12, [r7, #288] @ 0x120 │ │ - ldc2l 1, cr3, [r6, #364] @ 0x16c │ │ - ldc2l 0, cr5, [r6, #336] @ 0x150 │ │ - ldc2l 1, cr3, [r6, #188] @ 0xbc │ │ + ldc2l 1, cr3, [r6, #544] @ 0x220 │ │ + ldc2l 0, cr5, [r6, #516] @ 0x204 │ │ + ldc2l 1, cr3, [r6, #368] @ 0x170 │ │ ldc2l 12, cr10, [r7, #140] @ 0x8c │ │ - ldc2l 0, cr7, [r6, #396] @ 0x18c │ │ - ldc2l 10, cr4, [r7, #680] @ 0x2a8 @ │ │ + ldc2l 0, cr7, [r6, #576] @ 0x240 │ │ + ldc2l 10, cr4, [r7, #860] @ 0x35c @ │ │ ldc2l 4, cr5, [r5, #440] @ 0x1b8 │ │ ldc2l 10, cr0, [r5, #120] @ 0x78 @ │ │ ldc2l 11, cr10, [r7, #564] @ 0x234 @ │ │ ldc2l 11, cr12, [r7, #20] @ │ │ ldc2l 15, cr7, [r8, #132] @ 0x84 │ │ ldc2l 15, cr7, [r8, #92] @ 0x5c │ │ - ldc2l 10, cr10, [r6, #652] @ 0x28c @ │ │ + ldc2l 10, cr10, [r6, #832] @ 0x340 @ │ │ ldc2l 9, cr14, [r7, #112] @ 0x70 @ │ │ ldc2l 9, cr8, [r7, #200] @ 0xc8 @ │ │ ldc2l 14, cr7, [r8, #604] @ 0x25c │ │ ldc2l 8, cr14, [r7, #884] @ 0x374 │ │ ldc2l 10, cr12, [r7, #24] @ │ │ ldc2l 11, cr11, [r8, #620] @ 0x26c @ │ │ ldc2l 0, cr7, [r5, #556] @ 0x22c │ │ ldc2l 11, cr2, [r5, #824] @ 0x338 @ │ │ ldc2l 4, cr14, [r7, #652] @ 0x28c │ │ - ldc2l 13, cr0, [r6, #388] @ 0x184 │ │ - ldc2l 11, cr10, [r5, #956] @ 0x3bc @ │ │ + ldc2l 13, cr0, [r6, #568] @ 0x238 │ │ + ldc2l 12, cr10, [r5, #112] @ 0x70 │ │ ldc2l 3, cr0, [r8, #160] @ 0xa0 │ │ vcadd.f32 d24, d7, d4, #270 │ │ - ldc2l 5, cr0, [r7, #92] @ 0x5c │ │ - ldc2l 15, cr8, [r6, #548] @ 0x224 │ │ - ldc2l 6, cr2, [r7, #312] @ 0x138 │ │ - ldc2l 9, cr12, [r6, #376] @ 0x178 @ │ │ + ldc2l 5, cr0, [r7, #272] @ 0x110 │ │ + ldc2l 15, cr8, [r6, #728] @ 0x2d8 │ │ + ldc2l 6, cr2, [r7, #492] @ 0x1ec │ │ + ldc2l 9, cr12, [r6, #466] @ 0x1d2 @ │ │ ldc2l 8, cr13, [r8, #92] @ 0x5c │ │ - ldc2l 10, cr10, [r5, #916] @ 0x394 @ │ │ + ldc2l 11, cr10, [r5, #72] @ 0x48 @ │ │ ldc2l 8, cr10, [r7, #480] @ 0x1e0 │ │ - ldc2l 14, cr14, [r5, #8] │ │ + ldc2l 14, cr14, [r5, #188] @ 0xbc │ │ ldc2l 14, cr1, [r8, #368] @ 0x170 │ │ ldc2l 11, cr7, [r8, #1020] @ 0x3fc @ │ │ ldc2l 0, cr5, [r5, #536] @ 0x218 │ │ - ldc2l 12, cr2, [r6, #636] @ 0x27c │ │ + ldc2l 12, cr2, [r6, #816] @ 0x330 │ │ ldc2l 7, cr6, [r7, #396] @ 0x18c │ │ ldc2l 9, cr2, [r5, #230] @ 0xe6 @ │ │ ldc2l 9, cr2, [r5, #198] @ 0xc6 @ │ │ - ldc2l 13, cr8, [r6, #748] @ 0x2ec │ │ - ldc2l 10, cr0, [r6, #824] @ 0x338 @ │ │ - ldc2l 6, cr10, [r6, #652] @ 0x28c │ │ + ldc2l 13, cr8, [r6, #928] @ 0x3a0 │ │ + ldc2l 10, cr0, [r6, #1004] @ 0x3ec @ │ │ + ldc2l 6, cr10, [r6, #832] @ 0x340 │ │ ldc2l 6, cr13, [r8, #224] @ 0xe0 │ │ ldc2l 6, cr10, [r7, #848] @ 0x350 │ │ - ldc2l 12, cr14, [r5, #284] @ 0x11c │ │ + ldc2l 12, cr14, [r5, #464] @ 0x1d0 │ │ ldc2l 9, cr5, [r8, #338] @ 0x152 @ │ │ vcadd.f32 , q12, q5, #270 │ │ ldc2l 2, cr12, [r7, #84] @ 0x54 │ │ - ldc2l 14, cr15, [r6, #188] @ 0xbc │ │ + ldc2l 14, cr15, [r6, #368] @ 0x170 │ │ vcadd.f32 , q4, , #270 │ │ - ldc2l 5, cr0, [r6, #684] @ 0x2ac │ │ - ldc2l 1, cr10, [r6, #608] @ 0x260 │ │ - ldc2l 6, cr12, [r5, #180] @ 0xb4 │ │ + ldc2l 5, cr0, [r6, #864] @ 0x360 │ │ + ldc2l 1, cr10, [r6, #788] @ 0x314 │ │ + ldc2l 6, cr12, [r5, #360] @ 0x168 │ │ vcadd.f32 d22, d5, d8, #270 │ │ ldc2l 15, cr15, [r4, #1020] @ 0x3fc │ │ ldc2l 15, cr13, [r7, #760] @ 0x2f8 │ │ ldc2l 15, cr13, [r7, #688] @ 0x2b0 │ │ ldc2l 15, cr13, [r7, #532] @ 0x214 │ │ ldc2l 2, cr11, [r8, #392] @ 0x188 │ │ - ldc2l 5, cr6, [r6, #188] @ 0xbc │ │ + ldc2l 5, cr6, [r6, #368] @ 0x170 │ │ ldc2l 15, cr15, [r4, #240] @ 0xf0 │ │ - ldc2l 4, cr4, [r6, #484] @ 0x1e4 │ │ + ldc2l 4, cr4, [r6, #664] @ 0x298 │ │ ldc2l 4, cr7, [r8, #468] @ 0x1d4 │ │ - ldc2l 4, cr6, [r6, #752] @ 0x2f0 │ │ + ldc2l 4, cr6, [r6, #932] @ 0x3a4 │ │ vcadd.f32 q10, , q8, #270 │ │ - ldc2l 2, cr10, [r5, #476] @ 0x1dc │ │ + ldc2l 2, cr10, [r5, #656] @ 0x290 │ │ ldc2l 1, cr11, [r8, #360] @ 0x168 │ │ ldc2l 15, cr12, [r8, #180] @ 0xb4 │ │ ldc2l 15, cr9, [r7, #804] @ 0x324 │ │ ldc2l 14, cr7, [r7, #168] @ 0xa8 │ │ - ldc2l 1, cr8, [r5, #344] @ 0x158 │ │ - ldc2l 1, cr8, [r5, #232] @ 0xe8 │ │ - ldc2l 5, cr8, [r6, #692] @ 0x2b4 │ │ - ldc2l 12, cr1, [r7, #312] @ 0x138 │ │ - ldc2l 0, cr8, [r5, #912] @ 0x390 │ │ - ldc2l 15, cr11, [r6, #692] @ 0x2b4 │ │ + ldc2l 1, cr8, [r5, #524] @ 0x20c │ │ + ldc2l 1, cr8, [r5, #412] @ 0x19c │ │ + ldc2l 5, cr8, [r6, #872] @ 0x368 │ │ + ldc2l 12, cr1, [r7, #492] @ 0x1ec │ │ + ldc2l 1, cr8, [r5, #68] @ 0x44 │ │ + ldc2l 15, cr11, [r6, #872] @ 0x368 │ │ ldc2l 13, cr7, [r7, #244] @ 0xf4 │ │ - ldc2l 2, cr6, [r6, #908] @ 0x38c │ │ + ldc2l 3, cr6, [r6, #64] @ 0x40 │ │ ldc2l 13, cr11, [r7, #952] @ 0x3b8 │ │ ldc2l 4, cr1, [r8, #528] @ 0x210 │ │ - ldc2l 9, cr15, [r6, #500] @ 0x1f4 @ │ │ - ldc2l 12, cr13, [r6, #608] @ 0x260 │ │ + ldc2l 10, cr15, [r6, #156] @ 0x9c @ │ │ + ldc2l 12, cr13, [r6, #788] @ 0x314 │ │ ldc2l 15, cr10, [r8, #272] @ 0x110 │ │ - ldc2l 10, cr1, [r7, #1016] @ 0x3f8 @ │ │ + ldc2l 11, cr1, [r7, #172] @ 0xac @ │ │ ldc2l 3, cr1, [r8, #884] @ 0x374 │ │ ldc2l 11, cr13, [r7, #896] @ 0x380 @ │ │ - ldc2l 0, cr0, [r6, #924] @ 0x39c │ │ - ldc2l 1, cr12, [r5, #600] @ 0x258 │ │ + ldc2l 1, cr0, [r6, #80] @ 0x50 │ │ + ldc2l 1, cr12, [r5, #780] @ 0x30c │ │ ldc2l 1, cr7, [r8, #24] │ │ ldc2l 11, cr13, [r7, #424] @ 0x1a8 @ │ │ - ldc2l 10, cr1, [r7, #80] @ 0x50 @ │ │ + ldc2l 10, cr1, [r7, #260] @ 0x104 @ │ │ ldc2l 14, cr10, [r8, #120] @ 0x78 │ │ ldc2l 2, cr1, [r8, #836] @ 0x344 │ │ ldc2l 12, cr9, [r7, #408] @ 0x198 │ │ ldc2l 12, cr9, [r7, #288] @ 0x120 │ │ ldc2l 2, cr5, [r8, #976] @ 0x3d0 │ │ - ldc2l 15, cr3, [r6, #816] @ 0x330 │ │ + ldc2l 15, cr3, [r6, #996] @ 0x3e4 │ │ ldc2l 4, cr4, [r5, #428] @ 0x1ac │ │ ldc2l 3, cr9, [r8, #424] @ 0x1a8 │ │ ldc2l 11, cr9, [r7, #640] @ 0x280 @ │ │ ldc2l 12, cr10, [r8, #912] @ 0x390 │ │ - ldc2l 1, cr14, [r5, #28] │ │ + ldc2l 1, cr14, [r5, #208] @ 0xd0 │ │ ldc2l 3, cr4, [r5, #836] @ 0x344 │ │ ldc2l 10, cr5, [r7, #704] @ 0x2c0 @ │ │ ldc2l 1, cr6, [r5, #248] @ 0xf8 │ │ - ldc2l 15, cr1, [r6, #592] @ 0x250 │ │ + ldc2l 15, cr1, [r6, #772] @ 0x304 │ │ ldc2l 10, cr11, [r7, #224] @ 0xe0 @ │ │ - ldc2l 9, cr13, [r6, #74] @ 0x4a @ │ │ - ldc2l 6, cr15, [r6, #252] @ 0xfc │ │ - vcadd.f32 , , q11, #270 │ │ - ldc2l 9, cr9, [r6, #380] @ 0x17c @ │ │ - ldc2l 15, cr13, [r5, #760] @ 0x2f8 │ │ + ldc2l 9, cr13, [r6, #164] @ 0xa4 @ │ │ + ldc2l 6, cr15, [r6, #432] @ 0x1b0 │ │ + ldc2l 9, cr3, [r7, #38] @ 0x26 @ │ │ + ldc2l 9, cr9, [r6, #470] @ 0x1d6 @ │ │ + ldc2l 15, cr13, [r5, #940] @ 0x3ac │ │ ldc2l 0, cr5, [r8, #732] @ 0x2dc │ │ ldc2l 8, cr15, [r4, #208] @ 0xd0 │ │ ldc2l 11, cr10, [r8, #88] @ 0x58 @ │ │ ldc2l 13, cr6, [r8, #460] @ 0x1cc │ │ - ldc2l 13, cr11, [r5, #796] @ 0x31c │ │ + ldc2l 13, cr11, [r5, #976] @ 0x3d0 │ │ ldc2l 1, cr4, [r5, #836] @ 0x344 │ │ ldc2l 13, cr6, [r8, #40] @ 0x28 │ │ ldc2l 15, cr4, [r8, #820] @ 0x334 │ │ ldc2l 15, cr0, [r8, #92] @ 0x5c │ │ - ldc2l 12, cr15, [r5, #192] @ 0xc0 │ │ - ldc2l 7, cr13, [r6, #244] @ 0xf4 │ │ - ldc2l 4, cr15, [r6, #240] @ 0xf0 │ │ - ldc2l 9, cr11, [r6, #74] @ 0x4a @ │ │ + ldc2l 12, cr15, [r5, #372] @ 0x174 │ │ + ldc2l 7, cr13, [r6, #424] @ 0x1a8 │ │ + ldc2l 4, cr15, [r6, #420] @ 0x1a4 │ │ + ldc2l 9, cr11, [r6, #164] @ 0xa4 @ │ │ ldc2l 6, cr15, [r4, #608] @ 0x260 │ │ ldc2l 6, cr7, [r7, #548] @ 0x224 │ │ ldc2l 14, cr4, [r8, #792] @ 0x318 │ │ - ldc2l 10, cr9, [r5, #20] @ │ │ - ldc2l 12, cr1, [r6, #456] @ 0x1c8 │ │ - ldc2l 4, cr1, [r7, #792] @ 0x318 │ │ - ldc2l 9, cr9, [r5, #340] @ 0x154 @ │ │ + ldc2l 10, cr9, [r5, #200] @ 0xc8 @ │ │ + ldc2l 12, cr1, [r6, #636] @ 0x27c │ │ + ldc2l 4, cr1, [r7, #972] @ 0x3cc │ │ + ldc2l 9, cr9, [r5, #430] @ 0x1ae @ │ │ ldc2l 6, cr12, [r8, #532] @ 0x214 │ │ - ldc2l 10, cr15, [r5, #716] @ 0x2cc @ │ │ + ldc2l 10, cr15, [r5, #896] @ 0x380 @ │ │ ldc2l 7, cr9, [r7, #72] @ 0x48 │ │ ldc2l 8, cr1, [r5, #736] @ 0x2e0 │ │ ldc2l 8, cr1, [r5, #608] @ 0x260 │ │ - ldc2l 5, cr3, [r7, #320] @ 0x140 │ │ - ldc2l 2, cr15, [r6, #364] @ 0x16c │ │ - ldc2l 12, cr13, [r5, #40] @ 0x28 │ │ + ldc2l 5, cr3, [r7, #500] @ 0x1f4 │ │ + ldc2l 2, cr15, [r6, #544] @ 0x220 │ │ + ldc2l 12, cr13, [r5, #220] @ 0xdc │ │ ldc2l 8, cr1, [r5, #108] @ 0x6c │ │ - ldc2l 10, cr5, [r6, #452] @ 0x1c4 @ │ │ - ldc2l 7, cr7, [r5, #804] @ 0x324 │ │ + ldc2l 10, cr5, [r6, #632] @ 0x278 @ │ │ + ldc2l 7, cr7, [r5, #984] @ 0x3d8 │ │ ldc2l 14, cr3, [r5, #408] @ 0x198 │ │ ldc2l 5, cr5, [r7, #220] @ 0xdc │ │ ldc2l 11, cr5, [r5, #824] @ 0x338 @ │ │ - ldc2l 7, cr7, [r5, #304] @ 0x130 │ │ - ldc2l 4, cr9, [r6, #848] @ 0x350 │ │ - ldc2l 4, cr9, [r6, #780] @ 0x30c │ │ - vcadd.f32 d31, d21, d7, #270 │ │ + ldc2l 7, cr7, [r5, #484] @ 0x1e4 │ │ + ldc2l 5, cr9, [r6, #4] │ │ + ldc2l 4, cr9, [r6, #960] @ 0x3c0 │ │ + ldc2l 8, cr15, [r5, #720] @ 0x2d0 │ │ ldc2l 4, cr9, [r7, #904] @ 0x388 │ │ ldc2l 13, cr3, [r5, #356] @ 0x164 │ │ ldc2l 2, cr13, [r7, #944] @ 0x3b0 │ │ ldc2l 6, cr1, [r5, #304] @ 0x130 │ │ - ldc2l 3, cr9, [r6, #1016] @ 0x3f8 │ │ - ldc2l 4, cr11, [r6, #968] @ 0x3c8 │ │ + ldc2l 4, cr9, [r6, #172] @ 0xac │ │ + ldc2l 5, cr11, [r6, #124] @ 0x7c │ │ ldc2l 11, cr8, [r8, #684] @ 0x2ac @ │ │ - ldc2l 8, cr1, [r6, #744] @ 0x2e8 │ │ + vcadd.f32 , q11, , #270 │ │ ldc2l 7, cr6, [r8, #668] @ 0x29c │ │ - ldc2l 2, cr13, [r6, #328] @ 0x148 │ │ - ldc2l 7, cr15, [r5, #56] @ 0x38 │ │ + ldc2l 2, cr13, [r6, #508] @ 0x1fc │ │ + ldc2l 7, cr15, [r5, #236] @ 0xec │ │ ldc2l 12, cr3, [r5, #16] │ │ - ldc2l 0, cr1, [r7, #464] @ 0x1d0 │ │ + ldc2l 0, cr1, [r7, #644] @ 0x284 │ │ ldc2l 9, cr4, [r8, #464] @ 0x1d0 @ │ │ add r1, pc, r1 │ │ mov r2, #36 @ 0x24 │ │ mov r3, #6 │ │ str r6, [r5, #1436] @ 0x59c │ │ bl 270d9e0 │ │ str r6, [r5, #1440] @ 0x5a0 │ │ @@ -1440291,128 +1440291,128 @@ │ │ bl 270d9e0 │ │ add r0, r6, #101 @ 0x65 │ │ str r0, [r5, #2368] @ 0x940 │ │ ldr r1, [pc, #464] @ 24c5850 │ │ movw r0, #21312 @ 0x5340 │ │ add r0, r4, r0 │ │ b 24c5854 │ │ - ldc2l 4, cr7, [r5, #812] @ 0x32c │ │ + ldc2l 4, cr7, [r5, #992] @ 0x3e0 │ │ ldc2l 6, cr6, [r8, #728] @ 0x2d8 │ │ - ldc2l 6, cr11, [r5, #980] @ 0x3d4 │ │ + ldc2l 7, cr11, [r5, #136] @ 0x88 │ │ ldc2l 0, cr15, [r4, #940] @ 0x3ac │ │ - ldc2l 14, cr14, [r6, #108] @ 0x6c │ │ + ldc2l 14, cr14, [r6, #288] @ 0x120 │ │ ldc2l 1, cr5, [r7, #760] @ 0x2f8 │ │ - ldc2l 3, cr7, [r5, #1012] @ 0x3f4 │ │ + ldc2l 4, cr7, [r5, #168] @ 0xa8 │ │ ldc2l 10, cr3, [r5, #668] @ 0x29c @ │ │ ldc2l 1, cr11, [r7, #208] @ 0xd0 │ │ - ldc2l 14, cr0, [r7, #976] @ 0x3d0 │ │ + ldc2l 15, cr0, [r7, #132] @ 0x84 │ │ ldc2l 15, cr6, [r7, #984] @ 0x3d8 │ │ - ldc2l 14, cr0, [r7, #736] @ 0x2e0 │ │ + ldc2l 14, cr0, [r7, #916] @ 0x394 │ │ ldc2l 10, cr14, [r7, #788] @ 0x314 @ │ │ ldc2l 15, cr6, [r7, #620] @ 0x26c │ │ - ldc2l 5, cr5, [r6, #272] @ 0x110 │ │ - ldc2l 14, cr0, [r7, #304] @ 0x130 │ │ - ldc2l 4, cr3, [r6, #360] @ 0x168 │ │ + ldc2l 5, cr5, [r6, #452] @ 0x1c4 │ │ + ldc2l 14, cr0, [r7, #484] @ 0x1e4 │ │ + ldc2l 4, cr3, [r6, #540] @ 0x21c │ │ ldc2l 0, cr9, [r7, #612] @ 0x264 │ │ - ldc2l 2, cr7, [r5, #380] @ 0x17c │ │ - ldc2l 4, cr11, [r5, #680] @ 0x2a8 │ │ - ldc2l 2, cr7, [r5, #120] @ 0x78 │ │ + ldc2l 2, cr7, [r5, #560] @ 0x230 │ │ + ldc2l 4, cr11, [r5, #860] @ 0x35c │ │ + ldc2l 2, cr7, [r5, #300] @ 0x12c │ │ ldc2l 14, cr6, [r7, #524] @ 0x20c │ │ ldc2l 15, cr11, [r8, #12] │ │ ldc2l 8, cr3, [r5, #480] @ 0x1e0 │ │ ldc2l 1, cr1, [r5, #460] @ 0x1cc │ │ ldc2l 15, cr8, [r7, #520] @ 0x208 │ │ - ldc2l 2, cr15, [r5, #932] @ 0x3a4 │ │ - ldc2l 13, cr2, [r7, #816] @ 0x330 │ │ + ldc2l 3, cr15, [r5, #88] @ 0x58 │ │ + ldc2l 13, cr2, [r7, #996] @ 0x3e4 │ │ ldc2l 5, cr4, [r8, #928] @ 0x3a0 │ │ - ldc2l 13, cr2, [r7, #556] @ 0x22c │ │ + ldc2l 13, cr2, [r7, #736] @ 0x2e0 │ │ ldc2l 13, cr6, [r7, #292] @ 0x124 │ │ - ldc2l 2, cr5, [r6, #920] @ 0x398 │ │ + ldc2l 3, cr5, [r6, #76] @ 0x4c │ │ ldc2l 5, cr4, [r8, #380] @ 0x17c │ │ - ldc2l 1, cr15, [r5, #968] @ 0x3c8 │ │ - ldc2l 12, cr2, [r7, #900] @ 0x384 │ │ + ldc2l 2, cr15, [r5, #124] @ 0x7c │ │ + ldc2l 13, cr2, [r7, #56] @ 0x38 │ │ ldc2l 13, cr11, [r8, #268] @ 0x10c │ │ ldc2l 15, cr9, [r8, #272] @ 0x110 │ │ - ldc2l 4, cr7, [r6, #76] @ 0x4c │ │ + ldc2l 4, cr7, [r6, #256] @ 0x100 │ │ ldc2l 6, cr3, [r5, #480] @ 0x1e0 │ │ - ldc2l 9, cr14, [r6, #136] @ 0x88 @ │ │ + ldc2l 9, cr14, [r6, #226] @ 0xe2 @ │ │ ldc2l 12, cr10, [r7, #832] @ 0x340 │ │ ldc2l 6, cr14, [r7, #796] @ 0x31c │ │ ldc2l 1, cr6, [r8, #44] @ 0x2c │ │ - ldc2l 3, cr7, [r6, #292] @ 0x124 │ │ + ldc2l 3, cr7, [r6, #472] @ 0x1d8 │ │ ldc2l 12, cr8, [r7, #896] @ 0x380 │ │ ldc2l 14, cr9, [r8, #28] │ │ - ldc2l 12, cr8, [r6, #212] @ 0xd4 │ │ + ldc2l 12, cr8, [r6, #392] @ 0x188 │ │ ldc2l 2, cr5, [r5, #628] @ 0x274 │ │ - ldc2l 14, cr8, [r5, #428] @ 0x1ac │ │ - ldc2l 1, cr13, [r5, #728] @ 0x2d8 │ │ + ldc2l 14, cr8, [r5, #608] @ 0x260 │ │ + ldc2l 1, cr13, [r5, #908] @ 0x38c │ │ ldc2l 3, cr8, [r8, #616] @ 0x268 │ │ ldc2l 9, cr2, [r8, #102] @ 0x66 @ │ │ - ldc2l 10, cr2, [r7, #440] @ 0x1b8 @ │ │ + ldc2l 10, cr2, [r7, #620] @ 0x26c @ │ │ ldc2l 11, cr8, [r7, #652] @ 0x28c @ │ │ - ldc2l 15, cr4, [r6, #736] @ 0x2e0 │ │ - ldc2l 9, cr12, [r6, #498] @ 0x1f2 @ │ │ - ldc2l 15, cr10, [r5, #544] @ 0x220 │ │ + ldc2l 15, cr4, [r6, #916] @ 0x394 │ │ + ldc2l 10, cr12, [r6, #152] @ 0x98 @ │ │ + ldc2l 15, cr10, [r5, #724] @ 0x2d4 │ │ ldc2l 3, cr3, [r5, #860] @ 0x35c │ │ ldc2l 4, cr14, [r7, #436] @ 0x1b4 │ │ - ldc2l 10, cr8, [r6, #416] @ 0x1a0 @ │ │ + ldc2l 10, cr8, [r6, #596] @ 0x254 @ │ │ ldc2l 0, cr5, [r5, #824] @ 0x338 │ │ ldc2l 2, cr8, [r8, #104] @ 0x68 │ │ - ldc2l 12, cr6, [r5, #300] @ 0x12c │ │ + ldc2l 12, cr6, [r5, #480] @ 0x1e0 │ │ ldc2l 10, cr8, [r7, #264] @ 0x108 @ │ │ ldc2l 9, cr10, [r7, #244] @ 0xf4 @ │ │ ldc2l 10, cr8, [r7, #16] @ │ │ ldc2l 15, cr4, [r5, #1016] @ 0x3f8 │ │ ldc2l 15, cr4, [r5, #900] @ 0x384 │ │ ldc2l 1, cr8, [r8, #156] @ 0x9c │ │ - ldc2l 12, cr2, [r6, #976] @ 0x3d0 │ │ + ldc2l 13, cr2, [r6, #132] @ 0x84 │ │ ldc2l 2, cr3, [r5, #60] @ 0x3c │ │ ldc2l 15, cr15, [r7, #240] @ 0xf0 │ │ - ldc2l 14, cr12, [r5, #520] @ 0x208 │ │ + ldc2l 14, cr12, [r5, #700] @ 0x2bc │ │ ldc2l 7, cr11, [r8, #960] @ 0x3c0 │ │ - ldc2l 13, cr0, [r6, #436] @ 0x1b4 │ │ - ldc2l 14, cr12, [r5, #128] @ 0x80 │ │ - ldc2l 4, cr14, [r6, #132] @ 0x84 │ │ - ldc2l 13, cr0, [r6, #44] @ 0x2c │ │ - ldc2l 11, cr14, [r5, #676] @ 0x2a4 @ │ │ + ldc2l 13, cr0, [r6, #616] @ 0x268 │ │ + ldc2l 14, cr12, [r5, #308] @ 0x134 │ │ + ldc2l 4, cr14, [r6, #312] @ 0x138 │ │ + ldc2l 13, cr0, [r6, #224] @ 0xe0 │ │ + ldc2l 11, cr14, [r5, #856] @ 0x358 @ │ │ ldc2l 14, cr4, [r5, #256] @ 0x100 │ │ - ldc2l 9, cr8, [r5, #502] @ 0x1f6 @ │ │ + ldc2l 10, cr8, [r5, #160] @ 0xa0 @ │ │ ldc2l 9, cr0, [r5, #246] @ 0xf6 @ │ │ ldc2l 13, cr4, [r5, #940] @ 0x3ac │ │ ldc2l 9, cr0, [r5, #148] @ 0x94 @ │ │ - ldc2l 9, cr8, [r5, #260] @ 0x104 @ │ │ + ldc2l 9, cr8, [r5, #350] @ 0x15e @ │ │ ldc2l 5, cr12, [r7, #380] @ 0x17c │ │ - ldc2l 11, cr0, [r6, #840] @ 0x348 @ │ │ + ldc2l 11, cr0, [r6, #1020] @ 0x3fc @ │ │ ldc2l 15, cr2, [r5, #728] @ 0x2d8 │ │ - ldc2l 7, cr10, [r6, #404] @ 0x194 │ │ - ldc2l 8, cr8, [r5, #872] @ 0x368 │ │ + ldc2l 7, cr10, [r6, #584] @ 0x248 │ │ + ldc2l 9, cr8, [r5, #14] @ │ │ ldc2l 3, cr2, [r8, #764] @ 0x2fc │ │ ldc2l 3, cr2, [r8, #676] @ 0x2a4 │ │ ldc2l 4, cr6, [r7, #636] @ 0x27c │ │ ldc2l 13, cr7, [r8, #732] @ 0x2dc │ │ ldc2l 4, cr12, [r7, #156] @ 0x9c │ │ ldc2l 12, cr4, [r5, #172] @ 0xac │ │ - ldc2l 9, cr10, [r5, #488] @ 0x1e8 @ │ │ - ldc2l 9, cr14, [r5, #20] @ │ │ - ldc2l 2, cr0, [r7, #716] @ 0x2cc │ │ + ldc2l 10, cr10, [r5, #132] @ 0x84 @ │ │ + ldc2l 9, cr14, [r5, #110] @ 0x6e @ │ │ + ldc2l 2, cr0, [r7, #896] @ 0x380 │ │ ldc2l 14, cr2, [r5, #128] @ 0x80 │ │ - ldc2l 9, cr4, [r6, #156] @ 0x9c @ │ │ + ldc2l 9, cr4, [r6, #246] @ 0xf6 @ │ │ ldc2l 11, cr4, [r5, #384] @ 0x180 @ │ │ - ldc2l 3, cr12, [r6, #436] @ 0x1b4 │ │ - ldc2l 2, cr0, [r7, #68] @ 0x44 │ │ + ldc2l 3, cr12, [r6, #616] @ 0x268 │ │ + ldc2l 2, cr0, [r7, #248] @ 0xf8 │ │ ldc2l 3, cr11, [r8, #664] @ 0x298 │ │ ldc2l 2, cr6, [r7, #872] @ 0x368 │ │ ldc2l 11, cr3, [r8, #80] @ 0x50 @ │ │ ldc2l 3, cr4, [r7, #540] @ 0x21c │ │ ldc2l 5, cr0, [r5, #872] @ 0x368 │ │ ldc2l 2, cr6, [r7, #384] @ 0x180 │ │ - ldc2l 7, cr2, [r6, #280] @ 0x118 │ │ - ldc2l 9, cr6, [r6, #422] @ 0x1a6 @ │ │ - ldc2l 2, cr12, [r6, #60] @ 0x3c │ │ - ldc2l 5, cr8, [r5, #580] @ 0x244 │ │ + ldc2l 7, cr2, [r6, #460] @ 0x1cc │ │ + ldc2l 10, cr6, [r6] @ │ │ + ldc2l 2, cr12, [r6, #240] @ 0xf0 │ │ + ldc2l 5, cr8, [r5, #760] @ 0x2f8 │ │ vcadd.f32 d19, d8, d28, #270 │ │ mov r2, #36 @ 0x24 │ │ add r1, pc, r1 │ │ mov r3, #13 │ │ bl 270d9e0 │ │ add r0, r6, #102 @ 0x66 │ │ str r0, [r5, #2372] @ 0x944 │ │ @@ -1441322,112 +1441322,112 @@ │ │ add r1, pc, r1 │ │ add r0, r4, r0 │ │ mov r2, #36 @ 0x24 │ │ mov r3, #6 │ │ bl 270d9e0 │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 15, cr11, [r6, #908] @ 0x38c │ │ + ldc2l 0, cr12, [r6, #64] @ 0x40 │ │ ldc2l 15, cr5, [r7, #620] @ 0x26c │ │ ldc2l 7, cr3, [r8, #824] @ 0x338 │ │ ldc2l 15, cr5, [r7, #356] @ 0x164 │ │ ldc2l 15, cr5, [r7, #280] @ 0x118 │ │ ldc2l 4, cr5, [r8, #352] @ 0x160 │ │ - ldc2l 4, cr10, [r5, #712] @ 0x2c8 │ │ - ldc2l 3, cr14, [r5, #776] @ 0x308 │ │ + ldc2l 4, cr10, [r5, #892] @ 0x37c │ │ + ldc2l 3, cr14, [r5, #956] @ 0x3bc │ │ ldc2l 3, cr5, [r8, #984] @ 0x3d8 │ │ - ldc2l 3, cr2, [r6, #540] @ 0x21c │ │ + ldc2l 3, cr2, [r6, #720] @ 0x2d0 │ │ ldc2l 1, cr9, [r8, #92] @ 0x5c │ │ - ldc2l 1, cr6, [r5, #548] @ 0x224 │ │ + ldc2l 1, cr6, [r5, #728] @ 0x2d8 │ │ ldc2l 5, cr15, [r7, #636] @ 0x27c │ │ - ldc2l 4, cr0, [r6, #200] @ 0xc8 │ │ + ldc2l 4, cr0, [r6, #380] @ 0x17c │ │ ldc2l 5, cr15, [r7, #416] @ 0x1a0 │ │ ldc2l 14, cr3, [r7, #520] @ 0x208 │ │ ldc2l 13, cr11, [r7, #208] @ 0xd0 │ │ ldc2l 7, cr2, [r5, #744] @ 0x2e8 │ │ ldc2l 7, cr2, [r5, #640] @ 0x280 │ │ - ldc2l 13, cr11, [r6, #308] @ 0x134 │ │ + ldc2l 13, cr11, [r6, #488] @ 0x1e8 │ │ ldc2l 0, cr0, [r5, #260] @ 0x104 │ │ - ldc2l 9, cr13, [r6, #458] @ 0x1ca @ │ │ - ldc2l 0, cr8, [r5, #388] @ 0x184 │ │ - ldc2l 3, cr12, [r5, #504] @ 0x1f8 │ │ - ldc2l 12, cr1, [r7, #428] @ 0x1ac │ │ - ldc2l 12, cr1, [r7, #312] @ 0x138 │ │ + ldc2l 10, cr13, [r6, #72] @ 0x48 @ │ │ + ldc2l 0, cr8, [r5, #568] @ 0x238 │ │ + ldc2l 3, cr12, [r5, #684] @ 0x2ac │ │ + ldc2l 12, cr1, [r7, #608] @ 0x260 │ │ + ldc2l 12, cr1, [r7, #492] @ 0x1ec │ │ ldc2l 4, cr4, [r5, #32] │ │ ldc2l 13, cr7, [r7, #472] @ 0x1d8 │ │ - ldc2l 8, cr13, [r6, #1004] @ 0x3ec │ │ - ldc2l 0, cr14, [r5, #752] @ 0x2f0 │ │ + ldc2l 9, cr13, [r6, #80] @ 0x50 @ │ │ + ldc2l 0, cr14, [r5, #932] @ 0x3a4 │ │ ldc2l 3, cr15, [r7, #204] @ 0xcc │ │ - ldc2l 0, cr2, [r6, #436] @ 0x1b4 │ │ - ldc2l 11, cr11, [r6, #428] @ 0x1ac @ │ │ - ldc2l 0, cr4, [r6, #772] @ 0x304 │ │ + ldc2l 0, cr2, [r6, #616] @ 0x268 │ │ + ldc2l 11, cr11, [r6, #608] @ 0x260 @ │ │ + ldc2l 0, cr4, [r6, #952] @ 0x3b8 │ │ ldc2l 5, cr13, [r7, #860] @ 0x35c │ │ - ldc2l 0, cr10, [r5, #660] @ 0x294 │ │ - ldc2l 10, cr11, [r6, #888] @ 0x378 @ │ │ + ldc2l 0, cr10, [r5, #840] @ 0x348 │ │ + ldc2l 11, cr11, [r6, #44] @ 0x2c @ │ │ ldc2l 11, cr9, [r7, #272] @ 0x110 @ │ │ ldc2l 10, cr10, [r8, #900] @ 0x384 @ │ │ ldc2l 2, cr4, [r5, #120] @ 0x78 │ │ - ldc2l 12, cr9, [r6, #188] @ 0xbc │ │ + ldc2l 12, cr9, [r6, #368] @ 0x170 │ │ ldc2l 4, cr13, [r7, #848] @ 0x350 │ │ ldc2l 4, cr2, [r5, #136] @ 0x88 │ │ - ldc2l 9, cr1, [r7, #340] @ 0x154 @ │ │ + ldc2l 9, cr1, [r7, #430] @ 0x1ae @ │ │ ldc2l 10, cr9, [r7, #288] @ 0x120 @ │ │ - ldc2l 10, cr7, [r6, #292] @ 0x124 @ │ │ - ldc2l 0, cr12, [r5, #192] @ 0xc0 │ │ + ldc2l 10, cr7, [r6, #472] @ 0x1d8 @ │ │ + ldc2l 0, cr12, [r5, #372] @ 0x174 │ │ ldc2l 14, cr4, [r8, #356] @ 0x164 │ │ ldc2l 14, cr4, [r8, #280] @ 0x118 │ │ - ldc2l 14, cr3, [r6, #412] @ 0x19c │ │ - ldc2l 7, cr15, [r6, #400] @ 0x190 │ │ - vcadd.f32 d17, d23, d5, #270 │ │ - ldc2l 9, cr7, [r6, #196] @ 0xc4 @ │ │ + ldc2l 14, cr3, [r6, #592] @ 0x250 │ │ + ldc2l 7, cr15, [r6, #580] @ 0x244 │ │ + ldc2l 8, cr1, [r7, #712] @ 0x2c8 │ │ + ldc2l 9, cr7, [r6, #286] @ 0x11e @ │ │ ldc2l 10, cr8, [r8, #884] @ 0x374 @ │ │ ldc2l 15, cr14, [r7, #656] @ 0x290 │ │ - ldc2l 11, cr7, [r5, #560] @ 0x230 @ │ │ + ldc2l 11, cr7, [r5, #740] @ 0x2e4 @ │ │ ldc2l 10, cr15, [r4, #1020] @ 0x3fc @ │ │ - vcadd.f32 d23, d22, d21, #270 │ │ + ldc2l 8, cr7, [r6, #840] @ 0x348 │ │ ldc2l 8, cr7, [r7, #848] @ 0x350 │ │ ldc2l 8, cr9, [r7, #68] @ 0x44 │ │ - ldc2l 10, cr5, [r5, #376] @ 0x178 @ │ │ + ldc2l 10, cr5, [r5, #556] @ 0x22c @ │ │ ldc2l 1, cr13, [r7, #860] @ 0x35c │ │ - ldc2l 12, cr9, [r5, #592] @ 0x250 │ │ + ldc2l 12, cr9, [r5, #772] @ 0x304 │ │ ldc2l 14, cr14, [r7, #328] @ 0x148 │ │ - ldc2l 11, cr13, [r5, #532] @ 0x214 @ │ │ + ldc2l 11, cr13, [r5, #712] @ 0x2c8 @ │ │ ldc2l 7, cr9, [r7, #244] @ 0xf4 │ │ - ldc2l 7, cr7, [r6, #412] @ 0x19c │ │ - ldc2l 11, cr1, [r6, #160] @ 0xa0 @ │ │ - vcadd.f32 d25, d6, d11, #270 │ │ + ldc2l 7, cr7, [r6, #592] @ 0x250 │ │ + ldc2l 11, cr1, [r6, #340] @ 0x154 @ │ │ + ldc2l 8, cr9, [r6, #224] @ 0xe0 │ │ ldc2l 14, cr6, [r8, #864] @ 0x360 │ │ - ldc2l 5, cr1, [r7, #848] @ 0x350 │ │ + ldc2l 6, cr1, [r7, #4] │ │ ldc2l 13, cr3, [r5, #480] @ 0x1e0 │ │ - ldc2l 13, cr5, [r6, #48] @ 0x30 │ │ - ldc2l 10, cr13, [r5, #320] @ 0x140 @ │ │ - ldc2l 6, cr7, [r6, #312] @ 0x138 │ │ + ldc2l 13, cr5, [r6, #228] @ 0xe4 │ │ + ldc2l 10, cr13, [r5, #500] @ 0x1f4 @ │ │ + ldc2l 6, cr7, [r6, #492] @ 0x1ec │ │ ldc2l 12, cr14, [r7, #716] @ 0x2cc │ │ ldc2l 12, cr14, [r7, #600] @ 0x258 │ │ ldc2l 5, cr9, [r7, #620] @ 0x26c │ │ - ldc2l 10, cr15, [r5, #832] @ 0x340 @ │ │ - vcadd.f32 d23, d5, d22, #270 │ │ + ldc2l 10, cr15, [r5, #1012] @ 0x3f4 @ │ │ + ldc2l 8, cr7, [r5, #332] @ 0x14c │ │ ldc2l 3, cr11, [r7, #996] @ 0x3e4 │ │ ldc2l 4, cr10, [r8, #684] @ 0x2ac │ │ ldc2l 4, cr10, [r8, #568] @ 0x238 │ │ ldc2l 14, cr1, [r5, #268] @ 0x10c │ │ - ldc2l 9, cr9, [r5, #284] @ 0x11c @ │ │ - ldc2l 6, cr5, [r5, #940] @ 0x3ac │ │ - ldc2l 7, cr7, [r5, #196] @ 0xc4 │ │ + ldc2l 9, cr9, [r5, #374] @ 0x176 @ │ │ + ldc2l 7, cr5, [r5, #96] @ 0x60 │ │ + ldc2l 7, cr7, [r5, #376] @ 0x178 │ │ ldc2l 3, cr11, [r7, #16] │ │ ldc2l 4, cr9, [r7, #88] @ 0x58 │ │ - ldc2l 10, cr5, [r6, #700] @ 0x2bc @ │ │ + ldc2l 10, cr5, [r6, #880] @ 0x370 @ │ │ ldc2l 13, cr12, [r7, #856] @ 0x358 │ │ ldc2l 3, cr9, [r7, #708] @ 0x2c4 │ │ ldc2l 5, cr8, [r8, #384] @ 0x180 │ │ ldc2l 10, cr3, [r5, #412] @ 0x19c @ │ │ ldc2l 2, cr5, [r7, #412] @ 0x19c │ │ ldc2l 11, cr6, [r8, #220] @ 0xdc @ │ │ - ldc2l 15, cr12, [r6, #164] @ 0xa4 │ │ - ldc2l 15, cr12, [r6, #48] @ 0x30 │ │ + ldc2l 15, cr12, [r6, #344] @ 0x158 │ │ + ldc2l 15, cr12, [r6, #228] @ 0xe4 │ │ ldc2l 1, cr13, [r4, #428] @ 0x1ac │ │ │ │ 024c6830 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ mov r6, r1 │ │ @@ -1441845,43 +1441845,43 @@ │ │ bl 270dff0 │ │ add r1, sp, #12 │ │ mov r0, sl │ │ mov r2, r6 │ │ mov r3, #32 │ │ bl 270d9e0 │ │ b 24c6c4c │ │ - ldc2l 5, cr5, [r6, #600] @ 0x258 │ │ - ldc2l 2, cr12, [r5, #932] @ 0x3a4 │ │ + ldc2l 5, cr5, [r6, #780] @ 0x30c │ │ + ldc2l 3, cr12, [r5, #88] @ 0x58 │ │ ldc2l 1, cr4, [r8, #516] @ 0x204 │ │ - ldc2l 1, cr1, [r6, #108] @ 0x6c │ │ - ldc2l 11, cr2, [r6, #948] @ 0x3b4 @ │ │ + ldc2l 1, cr1, [r6, #288] @ 0x120 │ │ + ldc2l 12, cr2, [r6, #104] @ 0x68 │ │ ldc2l 15, cr2, [r5, #508] @ 0x1fc │ │ - ldc2l 3, cr12, [r5, #228] @ 0xe4 │ │ + ldc2l 3, cr12, [r5, #408] @ 0x198 │ │ ldc2l 6, cr1, [r5, #872] @ 0x368 │ │ - ldc2l 12, cr10, [r6, #584] @ 0x248 │ │ + ldc2l 12, cr10, [r6, #764] @ 0x2fc │ │ ldc2l 14, cr6, [r7, #824] @ 0x338 │ │ - ldc2l 2, cr12, [r5, #500] @ 0x1f4 │ │ + ldc2l 2, cr12, [r5, #680] @ 0x2a8 │ │ ldc2l 1, cr4, [r8, #172] @ 0xac │ │ ldc2l 13, cr6, [r7, #136] @ 0x88 │ │ ldc2l 3, cr0, [r5, #172] @ 0xac │ │ - ldc2l 7, cr4, [r6, #640] @ 0x280 │ │ - ldc2l 6, cr4, [r6, #96] @ 0x60 │ │ - vcadd.f32 d20, d5, d18, #270 │ │ + ldc2l 7, cr4, [r6, #820] @ 0x334 │ │ + ldc2l 6, cr4, [r6, #276] @ 0x114 │ │ + vcadd.f32 q10, , , #270 │ │ ldc2l 9, cr15, [r7, #84] @ 0x54 @ │ │ - ldc2l 10, cr10, [r5, #32] @ │ │ - ldc2l 1, cr12, [r5, #708] @ 0x2c4 │ │ + ldc2l 10, cr10, [r5, #212] @ 0xd4 @ │ │ + ldc2l 1, cr12, [r5, #888] @ 0x378 │ │ ldc2l 13, cr7, [r8, #716] @ 0x2cc │ │ ldc2l 10, cr9, [r8, #660] @ 0x294 @ │ │ - ldc2l 9, cr8, [r5, #404] @ 0x194 @ │ │ + ldc2l 9, cr8, [r5, #494] @ 0x1ee @ │ │ ldc2l 12, cr11, [r7, #612] @ 0x264 │ │ - ldc2l 7, cr0, [r6, #1012] @ 0x3f4 │ │ + vcadd.f32 d16, d6, d26, #270 │ │ ldc2l 4, cr9, [r8, #356] @ 0x164 │ │ - ldc2l 3, cr5, [r6, #696] @ 0x2b8 │ │ - ldc2l 9, cr10, [r5, #216] @ 0xd8 @ │ │ - ldc2l 1, cr12, [r5, #84] @ 0x54 │ │ + ldc2l 3, cr5, [r6, #876] @ 0x36c │ │ + ldc2l 9, cr10, [r5, #306] @ 0x132 @ │ │ + ldc2l 1, cr12, [r5, #264] @ 0x108 │ │ ldc2l 10, cr9, [r8, #984] @ 0x3d8 @ │ │ │ │ 024c6f38 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #112 @ 0x70 │ │ mov r6, r1 │ │ @@ -1441961,15 +1441961,15 @@ │ │ bl 270ceb0 │ │ mov r0, r4 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ ldc2l 14, cr3, [r8, #716] @ 0x2cc │ │ ldc2l 14, cr15, [r4, #828] @ 0x33c │ │ ldc2l 15, cr1, [r7, #320] @ 0x140 │ │ - ldc2l 15, cr11, [r6, #408] @ 0x198 │ │ + ldc2l 15, cr11, [r6, #588] @ 0x24c │ │ ldc2l 13, cr3, [r8, #780] @ 0x30c │ │ ldc2l 9, cr8, [r7, #136] @ 0x88 @ │ │ ldc2l 0, cr8, [r7, #772] @ 0x304 │ │ ldc2l 14, cr11, [r4, #844] @ 0x34c │ │ ldc2l 13, cr3, [r8, #716] @ 0x2cc │ │ │ │ 024c70a0 : │ │ @@ -1443157,39 +1443157,39 @@ │ │ ldr r0, [pc, #124] @ 24c8390 │ │ mov r1, r6 │ │ mov r2, r5 │ │ movw r3, #414 @ 0x19e │ │ add r0, pc, r0 │ │ bl 270da30 │ │ b 24c82b4 │ │ - ldc2l 0, cr10, [r6, #40] @ 0x28 │ │ - ldc2l 5, cr2, [r6, #432] @ 0x1b0 │ │ - ldc2l 15, cr9, [r6, #600] @ 0x258 │ │ - ldc2l 4, cr2, [r6, #992] @ 0x3e0 │ │ - ldc2l 15, cr9, [r6, #392] @ 0x188 │ │ - ldc2l 4, cr2, [r6, #784] @ 0x310 │ │ - ldc2l 14, cr9, [r6, #632] @ 0x278 │ │ - ldc2l 4, cr2, [r6] │ │ - ldc2l 14, cr9, [r6, #56] @ 0x38 │ │ - ldc2l 3, cr2, [r6, #448] @ 0x1c0 │ │ - ldc2l 13, cr9, [r6, #360] @ 0x168 │ │ - ldc2l 2, cr2, [r6, #752] @ 0x2f0 │ │ - ldc2l 10, cr9, [r6, #856] @ 0x358 @ │ │ - ldc2l 0, cr2, [r6, #224] @ 0xe0 │ │ - ldc2l 10, cr9, [r6, #632] @ 0x278 @ │ │ - ldc2l 0, cr2, [r6] │ │ - ldc2l 10, cr9, [r6, #328] @ 0x148 @ │ │ - ldc2l 15, cr1, [r6, #720] @ 0x2d0 │ │ - ldc2l 15, cr1, [r6, #192] @ 0xc0 │ │ - ldc2l 8, cr9, [r6, #600] @ 0x258 │ │ - ldc2l 7, cr9, [r6, #1016] @ 0x3f8 │ │ - ldc2l 7, cr9, [r6, #712] @ 0x2c8 │ │ - ldc2l 7, cr9, [r6, #424] @ 0x1a8 │ │ - ldc2l 7, cr9, [r6, #136] @ 0x88 │ │ - ldc2l 11, cr1, [r6, #688] @ 0x2b0 @ │ │ + ldc2l 0, cr10, [r6, #220] @ 0xdc │ │ + ldc2l 5, cr2, [r6, #612] @ 0x264 │ │ + ldc2l 15, cr9, [r6, #780] @ 0x30c │ │ + ldc2l 5, cr2, [r6, #148] @ 0x94 │ │ + ldc2l 15, cr9, [r6, #572] @ 0x23c │ │ + ldc2l 4, cr2, [r6, #964] @ 0x3c4 │ │ + ldc2l 14, cr9, [r6, #812] @ 0x32c │ │ + ldc2l 4, cr2, [r6, #180] @ 0xb4 │ │ + ldc2l 14, cr9, [r6, #236] @ 0xec │ │ + ldc2l 3, cr2, [r6, #628] @ 0x274 │ │ + ldc2l 13, cr9, [r6, #540] @ 0x21c │ │ + ldc2l 2, cr2, [r6, #932] @ 0x3a4 │ │ + ldc2l 11, cr9, [r6, #12] @ │ │ + ldc2l 0, cr2, [r6, #404] @ 0x194 │ │ + ldc2l 10, cr9, [r6, #812] @ 0x32c @ │ │ + ldc2l 0, cr2, [r6, #180] @ 0xb4 │ │ + ldc2l 10, cr9, [r6, #508] @ 0x1fc @ │ │ + ldc2l 15, cr1, [r6, #900] @ 0x384 │ │ + ldc2l 15, cr1, [r6, #372] @ 0x174 │ │ + vcadd.f32 , q11, , #270 │ │ + vcadd.f32 d25, d6, d27, #270 │ │ + ldc2l 7, cr9, [r6, #892] @ 0x37c │ │ + ldc2l 7, cr9, [r6, #604] @ 0x25c │ │ + ldc2l 7, cr9, [r6, #316] @ 0x13c │ │ + ldc2l 11, cr1, [r6, #868] @ 0x364 @ │ │ ldc2l 6, cr1, [r7, #204] @ 0xcc │ │ ldc2l 6, cr1, [r7, #12] │ │ │ │ 024c8394 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ @@ -1443239,15 +1443239,15 @@ │ │ mov r3, sl │ │ bl 270d9d0 │ │ cmp r0, #0 │ │ bne 24c83dc │ │ ldr r0, [r4] │ │ str r0, [r8] │ │ b 24c8428 │ │ - ldc2l 11, cr9, [r5, #468] @ 0x1d4 @ │ │ + ldc2l 11, cr9, [r5, #648] @ 0x288 @ │ │ │ │ 024c846c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #860 @ 0x35c │ │ mov r4, r3 │ │ mov r6, r2 │ │ @@ -1443749,45 +1443749,45 @@ │ │ add r1, pc, r1 │ │ str r0, [sp] │ │ add r0, sp, #84 @ 0x54 │ │ bl 270e2a0 │ │ b 24c8540 │ │ ldc2l 11, cr12, [r7, #468] @ 0x1d4 @ │ │ ldc2l 8, cr14, [r4, #892] @ 0x37c │ │ - ldc2l 15, cr10, [r6, #956] @ 0x3bc │ │ + ldc2l 0, cr11, [r6, #112] @ 0x70 │ │ ldc2l 8, cr14, [r4, #636] @ 0x27c │ │ - ldc2l 15, cr10, [r6, #684] @ 0x2ac │ │ + ldc2l 15, cr10, [r6, #864] @ 0x360 │ │ ldc2l 8, cr14, [r4, #364] @ 0x16c │ │ - ldc2l 15, cr10, [r6, #444] @ 0x1bc │ │ + ldc2l 15, cr10, [r6, #624] @ 0x270 │ │ ldc2l 8, cr14, [r4, #124] @ 0x7c │ │ - ldc2l 15, cr10, [r6, #140] @ 0x8c │ │ + ldc2l 15, cr10, [r6, #320] @ 0x140 │ │ ldc2l 3, cr5, [r7, #452] @ 0x1c4 │ │ - ldc2l 8, cr10, [r5, #468] @ 0x1d4 │ │ + vcadd.f32 d26, d21, d18, #270 │ │ strhteq r1, [r9], -ip │ │ - ldc2l 2, cr9, [r6, #28] │ │ - ldc2l 12, cr6, [r6, #440] @ 0x1b8 │ │ + ldc2l 2, cr9, [r6, #208] @ 0xd0 │ │ + ldc2l 12, cr6, [r6, #620] @ 0x26c │ │ ldc2l 1, cr5, [r7, #828] @ 0x33c │ │ - ldc2l 6, cr10, [r5, #52] @ 0x34 │ │ - ldc2l 5, cr10, [r5, #820] @ 0x334 │ │ - ldc2l 9, cr6, [r6, #460] @ 0x1cc @ │ │ + ldc2l 6, cr10, [r5, #232] @ 0xe8 │ │ + ldc2l 5, cr10, [r5, #1000] @ 0x3e8 │ │ + ldc2l 10, cr6, [r6, #76] @ 0x4c @ │ │ eoreq r1, r9, r0, lsr #21 │ │ - ldc2l 4, cr10, [r5, #964] @ 0x3c4 │ │ - ldc2l 15, cr4, [r6, #324] @ 0x144 │ │ + ldc2l 5, cr10, [r5, #120] @ 0x78 │ │ + ldc2l 15, cr4, [r6, #504] @ 0x1f8 │ │ ldrdeq r1, [r9], -r4 @ │ │ - ldc2l 12, cr14, [r5, #788] @ 0x314 │ │ - ldc2l 5, cr11, [r5, #220] @ 0xdc │ │ - ldc2l 6, cr10, [r5, #564] @ 0x234 │ │ - ldc2l 4, cr10, [r5, #180] @ 0xb4 │ │ + ldc2l 12, cr14, [r5, #968] @ 0x3c8 │ │ + ldc2l 5, cr11, [r5, #400] @ 0x190 │ │ + ldc2l 6, cr10, [r5, #744] @ 0x2e8 │ │ + ldc2l 4, cr10, [r5, #360] @ 0x168 │ │ eoreq r1, r9, r4, lsr r9 │ │ - ldc2l 12, cr14, [r5, #148] @ 0x94 │ │ + ldc2l 12, cr14, [r5, #328] @ 0x148 │ │ ldc2l 13, cr0, [r7, #776] @ 0x308 │ │ - ldc2l 3, cr10, [r5, #452] @ 0x1c4 │ │ + ldc2l 3, cr10, [r5, #632] @ 0x278 │ │ eoreq r1, r9, r8, ror r8 │ │ ldc2l 2, cr2, [r8, #72] @ 0x48 │ │ - ldc2l 10, cr12, [r6, #1012] @ 0x3f4 @ │ │ + ldc2l 11, cr12, [r6, #168] @ 0xa8 @ │ │ eoreq r1, r9, r4, lsl r8 │ │ ldc2l 10, cr12, [r7, #820] @ 0x334 @ │ │ │ │ 024c8cdc : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #92 @ 0x5c │ │ @@ -1444593,60 +1444593,60 @@ │ │ ldrbeq r9, [r6, #1892] @ 0x764 │ │ ldrbeq r9, [r6, #1864] @ 0x748 │ │ ldrbeq r9, [r6, #1868] @ 0x74c │ │ ldrbeq r9, [r6, #1824] @ 0x720 │ │ ldrbeq r9, [r6, #1828] @ 0x724 │ │ ldrbeq r9, [r6, #1792] @ 0x700 │ │ ldc2l 8, cr2, [r7, #488] @ 0x1e8 │ │ - ldc2l 10, cr6, [r6, #456] @ 0x1c8 @ │ │ + ldc2l 10, cr6, [r6, #636] @ 0x27c @ │ │ ldrbeq r9, [r6, #1740] @ 0x6cc │ │ ldrbeq r9, [r6, #404] @ 0x194 │ │ - ldc2l 7, cr0, [r6, #624] @ 0x270 │ │ + ldc2l 7, cr0, [r6, #804] @ 0x324 │ │ ldc2l 5, cr5, [r8, #248] @ 0xf8 │ │ - vcadd.f32 , , , #270 │ │ + ldc2l 8, cr9, [r5, #616] @ 0x268 │ │ ldrbeq r9, [r6, #84] @ 0x54 │ │ - ldc2l 6, cr12, [r5, #712] @ 0x2c8 │ │ + ldc2l 6, cr12, [r5, #892] @ 0x37c │ │ eoreq r0, r9, ip, ror #29 │ │ eoreq r1, r9, r0, lsl r4 │ │ ldc2l 2, cr6, [r7, #364] @ 0x16c │ │ ldc2l 9, cr0, [r5, #110] @ 0x6e @ │ │ - ldc2l 1, cr12, [r6, #728] @ 0x2d8 │ │ + ldc2l 1, cr12, [r6, #908] @ 0x38c │ │ ldrbeq r9, [r6, #1668] @ 0x684 │ │ ldrbeq r9, [r6, #1648] @ 0x670 │ │ ldrbeq r8, [r6, #4000] @ 0xfa0 │ │ eoreq r0, r9, r4, lsl #26 │ │ ldrbeq r9, [r6, #1624] @ 0x658 │ │ ldrbeq r9, [r6, #1632] @ 0x660 │ │ eoreq r1, r9, r4, lsr #7 │ │ ldrbeq r9, [r6, #1592] @ 0x638 │ │ ldrbeq r8, [r6, #3864] @ 0xf18 │ │ ldc2l 1, cr6, [r7, #460] @ 0x1cc │ │ - ldc2l 6, cr6, [r5, #164] @ 0xa4 │ │ + ldc2l 6, cr6, [r5, #344] @ 0x158 │ │ ldc2l 1, cr6, [r7, #312] @ 0x138 │ │ ldc2l 15, cr9, [r4, #840] @ 0x348 │ │ ldrbeq r8, [r6, #3972] @ 0xf84 │ │ ldc2l 1, cr6, [r7, #908] @ 0x38c │ │ - ldc2l 6, cr6, [r5, #612] @ 0x264 │ │ + ldc2l 6, cr6, [r5, #792] @ 0x318 │ │ ldc2l 1, cr6, [r7, #760] @ 0x2f8 │ │ - ldc2l 2, cr4, [r6, #560] @ 0x230 │ │ + ldc2l 2, cr4, [r6, #740] @ 0x2e4 │ │ ldrbeq r9, [r6, #1488] @ 0x5d0 │ │ ldrbeq r9, [r6, #1464] @ 0x5b8 │ │ ldrbeq r9, [r6, #1468] @ 0x5bc │ │ ldrbeq r9, [r6, #1424] @ 0x590 │ │ ldrbeq r9, [r6, #1428] @ 0x594 │ │ ldrbeq r9, [r6, #1392] @ 0x570 │ │ ldc2l 6, cr2, [r7, #936] @ 0x3a8 │ │ - vcadd.f32 q11, q11, q9, #270 │ │ + ldc2l 9, cr6, [r6, #30] @ │ │ ldrbeq r9, [r6, #1340] @ 0x53c │ │ ldrbeq r9, [r6, #1028] @ 0x404 │ │ ldc2l 5, cr6, [r7, #756] @ 0x2f4 │ │ ldc2l 7, cr5, [r8, #1000] @ 0x3e8 │ │ - ldc2l 11, cr9, [r5, #164] @ 0xa4 @ │ │ + ldc2l 11, cr9, [r5, #344] @ 0x158 @ │ │ ldrbeq r9, [r6, #784] @ 0x310 │ │ - ldc2l 9, cr12, [r5, #220] @ 0xdc @ │ │ + ldc2l 9, cr12, [r5, #310] @ 0x136 @ │ │ ldrbeq r9, [r6, #996] @ 0x3e4 │ │ ldrbeq r9, [r6, #972] @ 0x3cc │ │ ldrbeq r8, [r6, #3728] @ 0xe90 │ │ ldrbeq r9, [r6, #948] @ 0x3b4 │ │ ldrbeq r9, [r6, #956] @ 0x3bc │ │ ldrbeq r9, [r6, #928] @ 0x3a0 │ │ ldrbeq r8, [r6, #3600] @ 0xe10 │ │ @@ -1444655,15 +1444655,15 @@ │ │ ldc2l 0, cr6, [r7, #280] @ 0x118 │ │ ldc2l 14, cr9, [r4, #808] @ 0x328 │ │ ldrbeq r9, [r6, #844] @ 0x34c │ │ ldrbeq r8, [r6, #3708] @ 0xe7c │ │ ldc2l 0, cr6, [r7, #916] @ 0x394 │ │ ldc2l 1, cr4, [r7, #1008] @ 0x3f0 │ │ ldc2l 0, cr6, [r7, #728] @ 0x2d8 │ │ - ldc2l 1, cr4, [r6, #528] @ 0x210 │ │ + ldc2l 1, cr4, [r6, #708] @ 0x2c4 │ │ │ │ 024c9a6c : │ │ mov r0, #0 │ │ bx lr │ │ │ │ 024c9a74 : │ │ push {fp, lr} │ │ @@ -1444823,17 +1444823,17 @@ │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 12, cr7, [r7, #908] @ 0x38c │ │ ldc2l 15, cr3, [r7, #584] @ 0x248 │ │ ldc2l 10, cr4, [r8, #20] @ │ │ - ldc2l 8, cr3, [r6, #1008] @ 0x3f0 │ │ - ldc2l 9, cr15, [r5, #388] @ 0x184 @ │ │ - ldc2l 8, cr5, [r6, #624] @ 0x270 │ │ + ldc2l 9, cr3, [r6, #82] @ 0x52 @ │ │ + ldc2l 9, cr15, [r5, #478] @ 0x1de @ │ │ + vcadd.f32 , q11, , #270 │ │ ldc2l 11, cr7, [r7, #316] @ 0x13c @ │ │ │ │ 024c9cf0 : │ │ ldr r0, [r0] │ │ bx lr │ │ │ │ 024c9cf8 : │ │ @@ -1444970,31 +1444970,31 @@ │ │ bl 270d9e0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldrbeq r8, [r6, #3044] @ 0xbe4 │ │ ldrbeq r8, [r6, #3413] @ 0xd55 │ │ ldrbeq r8, [r6, #3005] @ 0xbbd │ │ - ldc2l 1, cr6, [r5, #232] @ 0xe8 │ │ - ldc2l 1, cr6, [r5, #132] @ 0x84 │ │ - ldc2l 14, cr1, [r5, #216] @ 0xd8 │ │ - ldc2l 3, cr3, [r5, #732] @ 0x2dc │ │ + ldc2l 1, cr6, [r5, #412] @ 0x19c │ │ + ldc2l 1, cr6, [r5, #312] @ 0x138 │ │ + ldc2l 14, cr1, [r5, #396] @ 0x18c │ │ + ldc2l 3, cr3, [r5, #912] @ 0x390 │ │ ldc2l 3, cr0, [r5, #64] @ 0x40 │ │ ldc2l 0, cr15, [r7, #576] @ 0x240 │ │ - ldc2l 0, cr10, [r5, #260] @ 0x104 │ │ + ldc2l 0, cr10, [r5, #440] @ 0x1b8 │ │ ldc2l 11, cr15, [r6, #604] @ 0x25c @ │ │ ldc2l 10, cr1, [r7, #424] @ 0x1a8 @ │ │ vcadd.f32 , , q12, #270 │ │ - ldc2l 13, cr3, [r5, #896] @ 0x380 │ │ - ldc2l 10, cr4, [r6, #800] @ 0x320 @ │ │ - ldc2l 10, cr7, [r6, #228] @ 0xe4 @ │ │ + ldc2l 14, cr3, [r5, #52] @ 0x34 │ │ + ldc2l 10, cr4, [r6, #980] @ 0x3d4 @ │ │ + ldc2l 10, cr7, [r6, #408] @ 0x198 @ │ │ eoreq r0, r9, r0, lsr #11 │ │ ldrbeq r8, [r6, #2613] @ 0xa35 │ │ - ldc2l 0, cr8, [r5, #520] @ 0x208 │ │ - ldc2l 15, cr9, [r5, #344] @ 0x158 │ │ + ldc2l 0, cr8, [r5, #700] @ 0x2bc │ │ + ldc2l 15, cr9, [r5, #524] @ 0x20c │ │ │ │ 024c9f60 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #104 @ 0x68 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ @@ -1445102,28 +1445102,28 @@ │ │ ldr r0, [pc, #72] @ 24ca158 │ │ mov r1, #8 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2l 14, cr9, [r5, #784] @ 0x310 │ │ - ldc2l 1, cr3, [r5, #700] @ 0x2bc │ │ + ldc2l 14, cr9, [r5, #964] @ 0x3c4 │ │ + ldc2l 1, cr3, [r5, #880] @ 0x370 │ │ ldc2l 3, cr9, [r4, #432] @ 0x1b0 │ │ ldc2l 11, cr11, [r4, #708] @ 0x2c4 @ │ │ - ldc2l 14, cr5, [r5, #424] @ 0x1a8 │ │ - ldc2l 14, cr8, [r5, #852] @ 0x354 │ │ - ldc2l 14, cr5, [r5, #228] @ 0xe4 │ │ - ldc2l 11, cr1, [r5, #232] @ 0xe8 @ │ │ + ldc2l 14, cr5, [r5, #604] @ 0x25c │ │ + ldc2l 15, cr8, [r5, #8] │ │ + ldc2l 14, cr5, [r5, #408] @ 0x198 │ │ + ldc2l 11, cr1, [r5, #412] @ 0x19c @ │ │ ldc2l 13, cr12, [r4, #604] @ 0x25c │ │ - ldc2l 14, cr8, [r5, #84] @ 0x54 │ │ + ldc2l 14, cr8, [r5, #264] @ 0x108 │ │ ldc2l 14, cr7, [r7, #44] @ 0x2c │ │ - ldc2l 14, cr8, [r5, #180] @ 0xb4 │ │ + ldc2l 14, cr8, [r5, #360] @ 0x168 │ │ ldc2l 15, cr4, [r7, #892] @ 0x37c │ │ - ldc2l 13, cr9, [r5, #208] @ 0xd0 │ │ + ldc2l 13, cr9, [r5, #388] @ 0x184 │ │ │ │ 024ca15c : │ │ mov r1, #2 │ │ str r1, [r0] │ │ mov r0, #0 │ │ bx lr │ │ │ │ @@ -1445329,29 +1445329,29 @@ │ │ eoreq r0, r9, ip, lsl #6 │ │ eoreq r0, r9, r4, lsr r3 │ │ eoreq r0, r9, ip, asr r3 │ │ eoreq r0, r9, r4, lsl #7 │ │ ldrbeq r8, [r6, #2284] @ 0x8ec │ │ eoreq r0, r9, ip, ror r3 │ │ eoreq r0, r9, r0, asr #3 │ │ - ldc2l 10, cr13, [r5, #340] @ 0x154 @ │ │ - ldc2l 7, cr5, [r6, #264] @ 0x108 │ │ - ldc2l 11, cr8, [r5, #740] @ 0x2e4 @ │ │ - ldc2l 1, cr11, [r5, #156] @ 0x9c │ │ + ldc2l 10, cr13, [r5, #520] @ 0x208 @ │ │ + ldc2l 7, cr5, [r6, #444] @ 0x1bc │ │ + ldc2l 11, cr8, [r5, #920] @ 0x398 @ │ │ + ldc2l 1, cr11, [r5, #336] @ 0x150 │ │ eoreq r0, r9, ip, lsl r3 │ │ ldc2l 9, cr11, [r4, #418] @ 0x1a2 @ │ │ ldc2l 7, cr3, [r7, #424] @ 0x1a8 │ │ eoreq r0, r9, ip, lsl #2 │ │ - ldc2l 5, cr11, [r6, #296] @ 0x128 │ │ + ldc2l 5, cr11, [r6, #476] @ 0x1dc │ │ eoreq r0, r9, r0, lsr #2 │ │ ldc2l 15, cr13, [r4, #168] @ 0xa8 │ │ eoreq r0, r9, r4, lsr r1 │ │ ldc2l 4, cr7, [r7, #88] @ 0x58 │ │ eoreq r0, r9, r8, asr #2 │ │ - ldc2l 10, cr11, [r5, #444] @ 0x1bc @ │ │ + ldc2l 10, cr11, [r5, #624] @ 0x270 @ │ │ eoreq r0, r9, ip, asr r1 │ │ ldc2l 11, cr10, [r7, #824] @ 0x338 @ │ │ eoreq r0, r9, r0, ror #3 │ │ eoreq r0, r9, r8, lsl r2 │ │ eoreq r0, r9, r0, asr #4 │ │ eoreq r0, r9, ip, ror #4 │ │ mlaeq r9, r8, r2, r0 │ │ @@ -1446321,53 +1446321,53 @@ │ │ ldr r0, [pc, #96] @ 24cb444 │ │ mov r2, sl │ │ movw r3, #383 @ 0x17f │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 24cb190 │ │ - ldc2l 0, cr5, [r6, #796] @ 0x31c │ │ + ldc2l 0, cr5, [r6, #976] @ 0x3d0 │ │ ldc2l 6, cr2, [r7, #824] @ 0x338 │ │ - ldc2l 4, cr8, [r5, #308] @ 0x134 │ │ + ldc2l 4, cr8, [r5, #488] @ 0x1e8 │ │ ldc2l 7, cr10, [r4, #300] @ 0x12c │ │ ldc2l 4, cr2, [r7, #360] @ 0x168 │ │ - ldc2l 1, cr8, [r5, #868] @ 0x364 │ │ - ldc2l 9, cr0, [r6, #416] @ 0x1a0 @ │ │ - ldc2l 3, cr9, [r5, #740] @ 0x2e4 │ │ + ldc2l 2, cr8, [r5, #24] │ │ + ldc2l 9, cr0, [r6, #506] @ 0x1fa @ │ │ + ldc2l 3, cr9, [r5, #920] @ 0x398 │ │ ldc2l 6, cr2, [r7, #460] @ 0x1cc │ │ - ldc2l 8, cr0, [r6, #96] @ 0x60 │ │ - ldc2l 2, cr9, [r5, #4] │ │ - ldc2l 7, cr0, [r6, #880] @ 0x370 │ │ - ldc2l 1, cr9, [r5, #788] @ 0x314 │ │ - ldc2l 12, cr8, [r5, #804] @ 0x324 │ │ + vcadd.f32 q8, q3, , #270 │ │ + ldc2l 2, cr9, [r5, #184] @ 0xb8 │ │ + vcadd.f32 d16, d6, d9, #270 │ │ + ldc2l 1, cr9, [r5, #968] @ 0x3c8 │ │ + ldc2l 12, cr8, [r5, #984] @ 0x3d8 │ │ ldc2l 0, cr2, [r7, #172] @ 0xac │ │ - ldc2l 2, cr0, [r6, #608] @ 0x260 │ │ - ldc2l 2, cr0, [r6] │ │ + ldc2l 2, cr0, [r6, #788] @ 0x314 │ │ + ldc2l 2, cr0, [r6, #180] @ 0xb4 │ │ eoreq pc, r8, r4, ror #6 │ │ - ldc2l 0, cr0, [r6, #688] @ 0x2b0 │ │ - ldc2l 0, cr0, [r6, #480] @ 0x1e0 │ │ - ldc2l 7, cr0, [r6, #608] @ 0x260 │ │ - ldc2l 1, cr9, [r5, #516] @ 0x204 │ │ - vcadd.f32 q8, , q15, #270 │ │ - ldc2l 0, cr9, [r5, #228] @ 0xe4 │ │ - ldc2l 6, cr0, [r5, #792] @ 0x318 │ │ - ldc2l 14, cr8, [r5, #580] @ 0x244 │ │ - ldc2l 14, cr8, [r5, #372] @ 0x174 │ │ - ldc2l 6, cr0, [r5, #360] @ 0x168 │ │ - ldc2l 14, cr8, [r5, #148] @ 0x94 │ │ - ldc2l 6, cr0, [r5, #168] @ 0xa8 │ │ - ldc2l 13, cr8, [r5, #980] @ 0x3d4 │ │ - ldc2l 7, cr0, [r6, #32] │ │ - ldc2l 0, cr9, [r5, #964] @ 0x3c4 │ │ + ldc2l 0, cr0, [r6, #868] @ 0x364 │ │ + ldc2l 0, cr0, [r6, #660] @ 0x294 │ │ + ldc2l 7, cr0, [r6, #788] @ 0x314 │ │ + ldc2l 1, cr9, [r5, #696] @ 0x2b8 │ │ + ldc2l 8, cr0, [r5, #620] @ 0x26c │ │ + ldc2l 0, cr9, [r5, #408] @ 0x198 │ │ + ldc2l 6, cr0, [r5, #972] @ 0x3cc │ │ + ldc2l 14, cr8, [r5, #760] @ 0x2f8 │ │ + ldc2l 14, cr8, [r5, #552] @ 0x228 │ │ + ldc2l 6, cr0, [r5, #540] @ 0x21c │ │ + ldc2l 14, cr8, [r5, #328] @ 0x148 │ │ + ldc2l 6, cr0, [r5, #348] @ 0x15c │ │ + ldc2l 14, cr8, [r5, #136] @ 0x88 │ │ + ldc2l 7, cr0, [r6, #212] @ 0xd4 │ │ + ldc2l 1, cr9, [r5, #120] @ 0x78 │ │ ldc2l 4, cr5, [r8, #576] @ 0x240 │ │ - ldc2l 5, cr0, [r5, #424] @ 0x1a8 │ │ - ldc2l 13, cr8, [r5, #212] @ 0xd4 │ │ + ldc2l 5, cr0, [r5, #604] @ 0x25c │ │ + ldc2l 13, cr8, [r5, #392] @ 0x188 │ │ ldc2l 0, cr2, [r7, #444] @ 0x1bc │ │ - ldc2l 13, cr8, [r5, #20] │ │ - ldc2l 15, cr4, [r6, #844] @ 0x34c │ │ + ldc2l 13, cr8, [r5, #200] @ 0xc8 │ │ + ldc2l 0, cr5, [r6] │ │ │ │ 024cb494 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ mov r7, r1 │ │ ldr r1, [fp, #12] │ │ @@ -1446699,21 +1446699,21 @@ │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r8, r9, sl, fp, pc} │ │ ldc2l 11, cr7, [r7, #692] @ 0x2b4 @ │ │ strdeq lr, [r8], -r8 @ │ │ eoreq lr, r8, ip, lsl lr │ │ - ldc2l 14, cr9, [r5, #816] @ 0x330 │ │ + ldc2l 14, cr9, [r5, #996] @ 0x3e4 │ │ eoreq lr, r8, r8, asr #26 │ │ strdeq lr, [r8], -r0 @ │ │ ldc2l 10, cr7, [r7, #56] @ 0x38 @ │ │ - ldc2l 5, cr7, [r5, #628] @ 0x274 │ │ + ldc2l 5, cr7, [r5, #808] @ 0x328 │ │ eoreq lr, r8, ip, lsl #25 │ │ - ldc2l 7, cr7, [r6, #584] @ 0x248 │ │ + ldc2l 7, cr7, [r6, #764] @ 0x2fc │ │ eoreq lr, r8, r0, lsr #26 │ │ ldc2l 9, cr7, [r7, #314] @ 0x13a @ │ │ │ │ 024cb9f4 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ @@ -1447478,15 +1447478,15 @@ │ │ str r0, [sp, #40] @ 0x28 │ │ add r0, lr, #504 @ 0x1f8 │ │ str r0, [sp, #64] @ 0x40 │ │ mov r0, #0 │ │ str r1, [sp, #32] │ │ str r0, [sp, #48] @ 0x30 │ │ b 24cc63c │ │ - ldc2l 1, cr2, [r5, #884] @ 0x374 │ │ + ldc2l 2, cr2, [r5, #40] @ 0x28 │ │ ldrbeq r7, [r6, #272] @ 0x110 │ │ ldr r1, [sp, #48] @ 0x30 │ │ add r5, r5, #32 │ │ sub r7, fp, #344 @ 0x158 │ │ add r0, r1, #2 │ │ str r0, [fp, #-340] @ 0xfffffeac │ │ ldr r0, [sp, #64] @ 0x40 │ │ @@ -1447761,20 +1447761,20 @@ │ │ sub r1, fp, #984 @ 0x3d8 │ │ add r3, sp, #552 @ 0x228 │ │ mov r0, sl │ │ mov r2, r4 │ │ str r9, [sp] │ │ bl 270f9e0 │ │ b 24cd0f8 │ │ - ldc2l 12, cr9, [r5, #1008] @ 0x3f0 │ │ + ldc2l 13, cr9, [r5, #164] @ 0xa4 │ │ ldrbeq r7, [r6, #1076] @ 0x434 │ │ ldc2l 12, cr9, [r4, #876] @ 0x36c │ │ ldrbeq r7, [r6, #212] @ 0xd4 │ │ eoreq lr, r8, r4, lsl ip │ │ - ldc2l 15, cr15, [r4, #32] │ │ + ldc2l 15, cr15, [r4, #212] @ 0xd4 │ │ eoreq lr, r8, r3, asr #23 │ │ ldrbeq r7, [r6, #296] @ 0x128 │ │ ldc2l 8, cr7, [r4, #832] @ 0x340 │ │ ldrbeq r7, [r6, #744] @ 0x2e8 │ │ ldc2l 7, cr5, [r7, #268] @ 0x10c │ │ mov r7, #32 │ │ add lr, sp, #1024 @ 0x400 │ │ @@ -1447833,31 +1447833,31 @@ │ │ bl 270db90 │ │ cmp r0, #0 │ │ beq 24cd4a0 │ │ b 24cbf64 │ │ ldrbeq r7, [r6, #44] @ 0x2c │ │ ldc2l 9, cr1, [r7, #438] @ 0x1b6 @ │ │ ldrbeq r7, [r6, #176] @ 0xb0 │ │ - ldc2l 15, cr3, [r5, #900] @ 0x384 │ │ + ldc2l 0, cr4, [r5, #56] @ 0x38 │ │ ldrbeq r7, [r6, #308] @ 0x134 │ │ - ldc2l 14, cr13, [r5, #112] @ 0x70 │ │ + ldc2l 14, cr13, [r5, #292] @ 0x124 │ │ ldrbeq r7, [r6, #376] @ 0x178 │ │ ldc2l 2, cr1, [r8, #684] @ 0x2ac │ │ ldrbeq r7, [r6, #124] @ 0x7c │ │ - ldc2l 13, cr13, [r5, #636] @ 0x27c │ │ + ldc2l 13, cr13, [r5, #816] @ 0x330 │ │ ldrbeq r7, [r6] │ │ - ldc2l 14, cr14, [r5, #576] @ 0x240 │ │ + ldc2l 14, cr14, [r5, #756] @ 0x2f4 │ │ ldrbeq r6, [r6, #3716] @ 0xe84 │ │ ldc2l 13, cr13, [r4, #332] @ 0x14c │ │ ldrbeq r6, [r6, #3784] @ 0xec8 │ │ - ldc2l 14, cr3, [r5, #472] @ 0x1d8 │ │ + ldc2l 14, cr3, [r5, #652] @ 0x28c │ │ ldrbeq r7, [r6, #140] @ 0x8c │ │ vcadd.f32 q10, q4, , #270 │ │ ldrbeq r6, [r6, #4052] @ 0xfd4 │ │ - ldc2l 13, cr9, [r5, #320] @ 0x140 │ │ + ldc2l 13, cr9, [r5, #500] @ 0x1f4 │ │ ldrbeq r7, [r6, #152] @ 0x98 │ │ ldrbeq r6, [r6, #3404] @ 0xd4c │ │ mlaeq r8, r8, r8, lr │ │ eoreq lr, r8, r4, lsl #17 │ │ mov r7, #32 │ │ ldr r5, [sp, #60] @ 0x3c │ │ str r7, [sp] │ │ @@ -1448013,18 +1448013,18 @@ │ │ ldr r1, [pc, #4008] @ 24cdde4 │ │ mov r0, r6 │ │ mov r2, r7 │ │ add r1, pc, r1 │ │ bl 270e100 │ │ b 24cd4a0 │ │ ldc2l 15, cr11, [r4, #132] @ 0x84 │ │ - ldc2l 7, cr1, [r6, #688] @ 0x2b0 │ │ + ldc2l 7, cr1, [r6, #868] @ 0x364 │ │ eoreq lr, r8, r8, lsl #15 │ │ - ldc2l 12, cr1, [r5, #724] @ 0x2d4 │ │ - ldc2l 7, cr1, [r6, #344] @ 0x158 │ │ + ldc2l 12, cr1, [r5, #904] @ 0x388 │ │ + ldc2l 7, cr1, [r6, #524] @ 0x20c │ │ ldc2l 12, cr8, [r7, #392] @ 0x188 │ │ strdeq lr, [r8], -r8 @ │ │ ldc2l 14, cr10, [r4, #204] @ 0xcc │ │ ldrbeq r6, [r6, #3728] @ 0xe90 │ │ mov r7, #32 │ │ ldr r5, [sp, #60] @ 0x3c │ │ str r7, [sp] │ │ @@ -1448158,15 +1448158,15 @@ │ │ eoreq lr, r8, r8, lsl #9 │ │ ldc2l 2, cr15, [r6, #868] @ 0x364 │ │ ldrbeq r6, [r6, #2256] @ 0x8d0 │ │ eoreq lr, r8, r0, lsl r4 │ │ ldrbeq r6, [r6, #2948] @ 0xb84 │ │ eoreq lr, r8, r4, lsl #7 │ │ ldc2l 2, cr15, [r6, #140] @ 0x8c │ │ - ldc2l 11, cr6, [r5, #628] @ 0x274 @ │ │ + ldc2l 11, cr6, [r5, #808] @ 0x328 @ │ │ ldr r6, [sp, #56] @ 0x38 │ │ cmp r0, #0 │ │ ldr r5, [sp, #60] @ 0x3c │ │ beq 24cd104 │ │ mov r0, #32 │ │ sub r9, fp, #408 @ 0x198 │ │ str r0, [sp] │ │ @@ -1448343,19 +1448343,19 @@ │ │ ldr r0, [pc, #4080] @ 24ce354 │ │ add r1, sp, #616 @ 0x268 │ │ ldr r2, [sp, #40] @ 0x28 │ │ add r3, sp, #560 @ 0x230 │ │ add r0, pc, r0 │ │ bl 270e660 │ │ b 24cd3d0 │ │ - ldc2l 15, cr4, [r6, #876] @ 0x36c │ │ + ldc2l 0, cr5, [r6, #32] │ │ vcadd.f32 d24, d23, d9, #270 │ │ - ldc2l 11, cr6, [r5, #244] @ 0xf4 @ │ │ + ldc2l 11, cr6, [r5, #424] @ 0x1a8 @ │ │ ldc2l 14, cr4, [r7, #996] @ 0x3e4 │ │ - ldc2l 11, cr6, [r5, #52] @ 0x34 @ │ │ + ldc2l 11, cr6, [r5, #232] @ 0xe8 @ │ │ sub r0, fp, #344 @ 0x158 │ │ str r0, [sp] │ │ add r0, sp, #560 @ 0x230 │ │ str r0, [sp, #4] │ │ mov r0, #32 │ │ add lr, sp, #1024 @ 0x400 │ │ str r0, [sp, #8] │ │ @@ -1448377,15 +1448377,15 @@ │ │ ldr r1, [sp, #52] @ 0x34 │ │ add r0, sp, #560 @ 0x230 │ │ bl 270f010 │ │ b 24cd438 │ │ ldc2l 0, cr13, [r6, #300] @ 0x12c │ │ ldc2l 10, cr0, [r8, #804] @ 0x324 @ │ │ ldc2l 10, cr12, [r7, #24] @ │ │ - ldc2l 7, cr7, [r5, #272] @ 0x110 │ │ + ldc2l 7, cr7, [r5, #452] @ 0x1c4 │ │ ldr r1, [pc, #3920] @ 24ce35c │ │ sub r0, fp, #76 @ 0x4c │ │ add r2, sp, #552 @ 0x228 │ │ add r3, sp, #160 @ 0xa0 │ │ add r1, pc, r1 │ │ bl 2710060 │ │ bl 270db90 │ │ @@ -1448403,15 +1448403,15 @@ │ │ cmp r0, #0 │ │ beq 24cd474 │ │ ldr r0, [sp, #52] @ 0x34 │ │ sub r2, fp, #440 @ 0x1b8 │ │ ldr r1, [sp, #24] │ │ bl 270f6f0 │ │ b 24cd484 │ │ - ldc2l 10, cr6, [r5, #532] @ 0x214 @ │ │ + ldc2l 10, cr6, [r5, #712] @ 0x2c8 @ │ │ ldc2l 10, cr0, [r8, #452] @ 0x1c4 @ │ │ ldc2l 0, cr15, [r6, #496] @ 0x1f0 │ │ ldr r0, [sp, #52] @ 0x34 │ │ sub r2, fp, #440 @ 0x1b8 │ │ ldr r1, [sp, #24] │ │ bl 270f6e0 │ │ bl 270db90 │ │ @@ -1448432,19 +1448432,19 @@ │ │ ldr r1, [pc, #3736] @ 24ce360 │ │ mov r0, r6 │ │ mov r2, r7 │ │ add r1, pc, r1 │ │ bl 270e100 │ │ b 24cc5fc │ │ ldc2l 6, cr14, [r7, #696] @ 0x2b8 │ │ - ldc2l 3, cr1, [r5, #836] @ 0x344 │ │ - ldc2l 4, cr15, [r4, #804] @ 0x324 │ │ + ldc2l 3, cr1, [r5, #1016] @ 0x3f8 │ │ + ldc2l 4, cr15, [r4, #984] @ 0x3d8 │ │ ldc2l 9, cr13, [r4, #90] @ 0x5a @ │ │ - ldc2l 14, cr10, [r6, #372] @ 0x174 │ │ - ldc2l 9, cr6, [r5, #282] @ 0x11a @ │ │ + ldc2l 14, cr10, [r6, #552] @ 0x228 │ │ + ldc2l 9, cr6, [r5, #372] @ 0x174 @ │ │ eoreq lr, r8, r4, asr #2 │ │ ldrbeq r6, [r6, #1468] @ 0x5bc │ │ eoreq lr, r8, r0, asr r0 │ │ ldc2l 7, cr10, [r4, #588] @ 0x24c │ │ ldrbeq r6, [r6, #2032] @ 0x7f0 │ │ ldc2l 8, cr5, [r7, #860] @ 0x35c │ │ ldc2l 15, cr12, [r4, #548] @ 0x224 │ │ @@ -1448626,22 +1448626,22 @@ │ │ add r1, r3, #4 │ │ str r1, [sp] │ │ mov r1, r4 │ │ stmib sp, {r0, r8} │ │ mov r0, sl │ │ bl 270db40 │ │ b 24cbf64 │ │ - ldc2l 0, cr1, [r5, #816] @ 0x330 │ │ + ldc2l 0, cr1, [r5, #996] @ 0x3e4 │ │ ldc2l 8, cr10, [r7, #872] @ 0x368 │ │ ldc2l 0, cr2, [r8, #48] @ 0x30 │ │ - ldc2l 9, cr8, [r6, #262] @ 0x106 @ │ │ + ldc2l 9, cr8, [r6, #352] @ 0x160 @ │ │ ldrbeq r6, [r6, #968] @ 0x3c8 │ │ ldrbeq r6, [r6, #688] @ 0x2b0 │ │ eoreq sp, r8, r8, asr #27 │ │ - ldc2l 3, cr7, [r5, #188] @ 0xbc │ │ + ldc2l 3, cr7, [r5, #368] @ 0x170 │ │ ldr r2, [pc, #2996] @ 24ce3c0 │ │ add lr, sp, #1024 @ 0x400 │ │ ldr r4, [pc, #2992] @ 24ce3c4 │ │ add r1, lr, #504 @ 0x1f8 │ │ add lr, sp, #1024 @ 0x400 │ │ ldr r7, [sp, #56] @ 0x38 │ │ add r4, pc, r4 │ │ @@ -1448766,15 +1448766,15 @@ │ │ bl 270e100 │ │ add r0, r4, #1 │ │ add r6, r6, #32 │ │ cmp r4, sl │ │ mov r4, r0 │ │ blt 24cd90c │ │ b 24cbf64 │ │ - ldc2l 13, cr8, [r5, #192] @ 0xc0 │ │ + ldc2l 13, cr8, [r5, #372] @ 0x174 │ │ ldr r0, [pc, #2248] @ 24ce2e8 │ │ mov r1, #170 @ 0xaa │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #2236] @ 24ce2ec │ │ add lr, sp, #1024 @ 0x400 │ │ add r1, lr, #472 @ 0x1d8 │ │ @@ -1448833,15 +1448833,15 @@ │ │ mov r2, #1 │ │ mov r3, #36 @ 0x24 │ │ bl 270da60 │ │ ldr r0, [pc, #1996] @ 24ce2e4 │ │ mov r1, #23 │ │ add r0, pc, r0 │ │ b 24cc39c │ │ - ldc2l 12, cr8, [r5, #64] @ 0x40 │ │ + ldc2l 12, cr8, [r5, #244] @ 0xf4 │ │ ldr r0, [pc, #2032] @ 24ce31c │ │ mov r1, #205 @ 0xcd │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #2020] @ 24ce320 │ │ add lr, sp, #1024 @ 0x400 │ │ add r1, lr, #472 @ 0x1d8 │ │ @@ -1448952,15 +1448952,15 @@ │ │ mov r3, #13 │ │ add r1, pc, r1 │ │ bl 270da60 │ │ ldr r0, [pc, #1668] @ 24ce378 │ │ mov r1, #21 │ │ add r0, pc, r0 │ │ b 24cc39c │ │ - ldc2l 9, cr8, [r5, #360] @ 0x168 @ │ │ + ldc2l 9, cr8, [r5, #450] @ 0x1c2 @ │ │ ldr r2, [pc, #1472] @ 24ce2c8 │ │ add lr, sp, #1024 @ 0x400 │ │ ldr r3, [pc, #1468] @ 24ce2cc │ │ mov r1, #9 │ │ mov r0, #80 @ 0x50 │ │ add r6, lr, #504 @ 0x1f8 │ │ str r1, [sp, #12] │ │ @@ -1449192,15 +1449192,15 @@ │ │ add r0, pc, r0 │ │ b 24ce264 │ │ ldr r0, [pc, #576] @ 24ce2f0 │ │ mov r1, #168 @ 0xa8 │ │ add r0, pc, r0 │ │ b 24ce188 │ │ ldrbeq r5, [r6, #3168] @ 0xc60 │ │ - ldc2l 6, cr8, [r5, #496] @ 0x1f0 │ │ + ldc2l 6, cr8, [r5, #676] @ 0x2a4 │ │ ldr r0, [sp, #48] @ 0x30 │ │ sub r1, fp, #688 @ 0x2b0 │ │ add r2, sp, #72 @ 0x48 │ │ mov r3, #36 @ 0x24 │ │ bl 270ce00 │ │ ldr r0, [sp, #72] @ 0x48 │ │ cmp r0, #0 │ │ @@ -1449239,15 +1449239,15 @@ │ │ bl 270da60 │ │ ldr r0, [pc, #476] @ 24ce344 │ │ mov r1, #20 │ │ add r0, pc, r0 │ │ b 24cc39c │ │ ldc2l 12, cr9, [r4, #828] @ 0x33c │ │ ldrbeq r5, [r6, #3372] @ 0xd2c │ │ - ldc2l 10, cr2, [r5, #96] @ 0x60 @ │ │ + ldc2l 10, cr2, [r5, #276] @ 0x114 @ │ │ ldr r0, [pc, #396] @ 24ce310 │ │ mov r1, #169 @ 0xa9 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r4, [pc, #352] @ 24ce2f4 │ │ add lr, sp, #1024 @ 0x400 │ │ add r1, lr, #472 @ 0x1d8 │ │ @@ -1449321,92 +1449321,92 @@ │ │ add r0, pc, r0 │ │ b 24cc39c │ │ ldrbeq r5, [r6, #2300] @ 0x8fc │ │ ldrbeq r5, [r6, #2488] @ 0x9b8 │ │ ldrdeq sp, [r8], -r4 @ │ │ ldc2l 7, cr15, [r7, #776] @ 0x308 │ │ ldc2l 5, cr9, [r7, #552] @ 0x228 │ │ - ldc2l 4, cr5, [r5, #276] @ 0x114 │ │ + ldc2l 4, cr5, [r5, #456] @ 0x1c8 │ │ ldc2l 10, cr13, [r6, #420] @ 0x1a4 @ │ │ - ldc2l 13, cr7, [r5, #972] @ 0x3cc │ │ + ldc2l 14, cr7, [r5, #128] @ 0x80 │ │ mlaeq r8, ip, r9, ip │ │ - ldc2l 9, cr3, [r6, #22] @ │ │ + ldc2l 9, cr3, [r6, #112] @ 0x70 @ │ │ ldrbeq r4, [r6, #3556] @ 0xde4 │ │ - ldc2l 9, cr11, [r5, #136] @ 0x88 @ │ │ - ldc2l 12, cr4, [r5, #932] @ 0x3a4 │ │ - ldc2l 4, cr3, [r6, #156] @ 0x9c │ │ + ldc2l 9, cr11, [r5, #226] @ 0xe2 @ │ │ + ldc2l 13, cr4, [r5, #88] @ 0x58 │ │ + ldc2l 4, cr3, [r6, #336] @ 0x150 │ │ ldc2l 8, cr5, [r4, #1012] @ 0x3f4 │ │ ldc2l 12, cr1, [r7, #380] @ 0x17c │ │ - ldc2l 4, cr5, [r5, #804] @ 0x324 │ │ - ldc2l 11, cr13, [r5, #696] @ 0x2b8 @ │ │ - ldc2l 13, cr4, [r5, #404] @ 0x194 │ │ - ldc2l 13, cr7, [r5, #4] │ │ + ldc2l 4, cr5, [r5, #984] @ 0x3d8 │ │ + ldc2l 11, cr13, [r5, #876] @ 0x36c @ │ │ + ldc2l 13, cr4, [r5, #584] @ 0x248 │ │ + ldc2l 13, cr7, [r5, #184] @ 0xb8 │ │ strhteq ip, [r8], -ip │ │ - vcadd.f32 d19, d6, d15, #270 │ │ + ldc2l 8, cr3, [r6, #240] @ 0xf0 │ │ ldrbeq r4, [r6, #3304] @ 0xce8 │ │ - vcadd.f32 , , q8, #270 │ │ + ldc2l 9, cr9, [r5, #26] @ │ │ ldrbeq r5, [r6, #4] │ │ - ldc2l 1, cr9, [r6, #572] @ 0x23c │ │ + ldc2l 1, cr9, [r6, #752] @ 0x2f0 │ │ eoreq ip, r8, r4, lsr #18 │ │ ldrbeq r4, [r6, #3920] @ 0xf50 │ │ ldc2l 9, cr11, [r6, #176] @ 0xb0 @ │ │ - ldc2l 3, cr5, [r5, #756] @ 0x2f4 │ │ + ldc2l 3, cr5, [r5, #936] @ 0x3a8 │ │ ldc2l 9, cr13, [r6, #448] @ 0x1c0 @ │ │ ldc2l 3, cr5, [r4, #564] @ 0x234 │ │ - ldc2l 12, cr4, [r5, #532] @ 0x214 │ │ + ldc2l 12, cr4, [r5, #712] @ 0x2c8 │ │ ldc2l 4, cr0, [r8, #604] @ 0x25c │ │ ldc2l 7, cr7, [r4, #148] @ 0x94 │ │ - ldc2l 14, cr4, [r5, #644] @ 0x284 │ │ + ldc2l 14, cr4, [r5, #824] @ 0x338 │ │ ldc2l 12, cr9, [r4, #968] @ 0x3c8 │ │ - ldc2l 13, cr4, [r5, #804] @ 0x324 │ │ - ldc2l 3, cr7, [r5, #92] @ 0x5c │ │ - ldc2l 9, cr3, [r5, #280] @ 0x118 @ │ │ + ldc2l 13, cr4, [r5, #984] @ 0x3d8 │ │ + ldc2l 3, cr7, [r5, #272] @ 0x110 │ │ + ldc2l 9, cr3, [r5, #370] @ 0x172 @ │ │ ldrbeq r5, [r6, #2740] @ 0xab4 │ │ eoreq sp, r8, r4, lsl #6 │ │ eoreq sp, r8, ip, ror #6 │ │ ldrbeq r5, [r6, #2768] @ 0xad0 │ │ ldrbeq r5, [r6, #2708] @ 0xa94 │ │ eoreq sp, r8, r0, lsl #4 │ │ ldrdeq ip, [r8], -r3 @ │ │ eoreq ip, r8, r4, lsl #22 │ │ ldc2l 5, cr9, [r7, #460] @ 0x1cc │ │ - ldc2l 2, cr5, [r5, #452] @ 0x1c4 │ │ + ldc2l 2, cr5, [r5, #632] @ 0x278 │ │ ldc2l 3, cr5, [r7, #304] @ 0x130 │ │ ldc2l 8, cr2, [r8, #892] @ 0x37c │ │ ldrbeq r4, [r6, #3768] @ 0xeb8 │ │ strhteq ip, [r8], -r8 │ │ ldrbeq r4, [r6, #3720] @ 0xe88 │ │ ldc2l 14, cr3, [r7, #620] @ 0x26c │ │ eoreq sp, r8, ip, ror #2 │ │ ldc2l 3, cr8, [r4, #504] @ 0x1f8 │ │ eoreq sp, r8, r4, lsl r1 │ │ eoreq sp, r8, r7, asr #32 │ │ strdeq sp, [r8], -r0 @ │ │ eoreq ip, r8, r3, asr #31 │ │ - ldc2l 5, cr2, [r5, #120] @ 0x78 │ │ + ldc2l 5, cr2, [r5, #300] @ 0x12c │ │ eoreq sp, r8, r8 │ │ ldrbeq r5, [r6, #1992] @ 0x7c8 │ │ ldc2l 3, cr15, [r7, #808] @ 0x328 │ │ ldrbeq r5, [r6, #1896] @ 0x768 │ │ ldrbeq r5, [r6, #1828] @ 0x724 │ │ ldc2l 3, cr15, [r7, #232] @ 0xe8 │ │ - ldc2l 2, cr12, [r5, #916] @ 0x394 │ │ + ldc2l 3, cr12, [r5, #72] @ 0x48 │ │ eoreq ip, r8, r8, asr #29 │ │ ldc2l 0, cr8, [r4, #844] @ 0x34c │ │ ldc2l 8, cr1, [r7, #244] @ 0xf4 │ │ - ldc2l 15, cr4, [r5, #996] @ 0x3e4 │ │ + ldc2l 0, cr5, [r5, #152] @ 0x98 │ │ ldc2l 13, cr6, [r7, #824] @ 0x338 │ │ eoreq ip, r8, r8, lsr #27 │ │ ldc2l 12, cr2, [r8, #596] @ 0x254 │ │ - ldc2l 2, cr14, [r4, #380] @ 0x17c │ │ + ldc2l 2, cr14, [r4, #560] @ 0x230 │ │ ldc2l 4, cr11, [r7, #936] @ 0x3a8 │ │ eoreq ip, r8, ip, asr #25 │ │ ldc2l 12, cr11, [r4, #560] @ 0x230 │ │ ldc2l 1, cr9, [r7, #636] @ 0x27c │ │ - ldc2l 15, cr4, [r5, #420] @ 0x1a4 │ │ + ldc2l 15, cr4, [r5, #600] @ 0x258 │ │ │ │ 024ce3f8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d13} │ │ sub sp, sp, #3216 @ 0xc90 │ │ @@ -1450060,53 +1450060,53 @@ │ │ ldr r0, [pc, #96] @ 24cee90 │ │ mov r2, sl │ │ mov r3, #384 @ 0x180 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 24cebdc │ │ - ldc2l 9, cr9, [r5, #148] @ 0x94 @ │ │ + ldc2l 9, cr9, [r5, #238] @ 0xee @ │ │ ldc2l 12, cr14, [r6, #520] @ 0x208 │ │ - ldc2l 10, cr4, [r5, #4] @ │ │ + ldc2l 10, cr4, [r5, #184] @ 0xb8 @ │ │ ldc2l 12, cr6, [r4, #1020] @ 0x3fc │ │ ldc2l 10, cr14, [r6, #56] @ 0x38 @ │ │ - ldc2l 7, cr4, [r5, #564] @ 0x234 │ │ - ldc2l 15, cr12, [r5, #528] @ 0x210 │ │ + ldc2l 7, cr4, [r5, #744] @ 0x2e8 │ │ + ldc2l 15, cr12, [r5, #708] @ 0x2c4 │ │ ldc2l 4, cr1, [r7, #596] @ 0x254 │ │ ldc2l 12, cr14, [r6, #156] @ 0x9c │ │ - ldc2l 13, cr12, [r5, #816] @ 0x330 │ │ + ldc2l 13, cr12, [r5, #996] @ 0x3e4 │ │ ldc2l 2, cr1, [r7, #884] @ 0x374 │ │ - ldc2l 13, cr12, [r5, #576] @ 0x240 │ │ + ldc2l 13, cr12, [r5, #756] @ 0x2f4 │ │ ldc2l 2, cr1, [r7, #644] @ 0x284 │ │ ldc2l 13, cr0, [r7, #660] @ 0x294 │ │ ldc2l 5, cr14, [r6, #892] @ 0x37c │ │ - vcadd.f32 q14, , q6, #270 │ │ - ldc2l 7, cr12, [r5, #720] @ 0x2d0 │ │ + ldc2l 8, cr12, [r5, #484] @ 0x1e4 │ │ + ldc2l 7, cr12, [r5, #900] @ 0x384 │ │ eoreq fp, r8, ip, ror #19 │ │ - ldc2l 6, cr12, [r5, #384] @ 0x180 │ │ - ldc2l 6, cr12, [r5, #176] @ 0xb0 │ │ - ldc2l 13, cr12, [r5, #304] @ 0x130 │ │ + ldc2l 6, cr12, [r5, #564] @ 0x234 │ │ + ldc2l 6, cr12, [r5, #356] @ 0x164 │ │ + ldc2l 13, cr12, [r5, #484] @ 0x1e4 │ │ ldc2l 2, cr1, [r7, #372] @ 0x174 │ │ - ldc2l 14, cr12, [r4, #136] @ 0x88 │ │ + ldc2l 14, cr12, [r4, #316] @ 0x13c │ │ ldc2l 1, cr1, [r7, #84] @ 0x54 │ │ - ldc2l 12, cr12, [r4, #488] @ 0x1e8 │ │ + ldc2l 12, cr12, [r4, #668] @ 0x29c │ │ ldc2l 15, cr0, [r7, #436] @ 0x1b4 │ │ ldc2l 15, cr0, [r7, #228] @ 0xe4 │ │ - ldc2l 12, cr12, [r4, #56] @ 0x38 │ │ + ldc2l 12, cr12, [r4, #236] @ 0xec │ │ ldc2l 15, cr0, [r7, #4] │ │ - ldc2l 11, cr12, [r4, #888] @ 0x378 @ │ │ + ldc2l 12, cr12, [r4, #44] @ 0x2c │ │ ldc2l 14, cr0, [r7, #836] @ 0x344 │ │ - ldc2l 12, cr12, [r5, #752] @ 0x2f0 │ │ + ldc2l 12, cr12, [r5, #932] @ 0x3a4 │ │ ldc2l 1, cr1, [r7, #820] @ 0x334 │ │ ldc2l 10, cr1, [r8, #272] @ 0x110 @ │ │ - ldc2l 11, cr12, [r4, #120] @ 0x78 @ │ │ + ldc2l 11, cr12, [r4, #300] @ 0x12c @ │ │ ldc2l 14, cr0, [r7, #68] @ 0x44 │ │ ldc2l 6, cr14, [r6, #140] @ 0x8c │ │ ldc2l 13, cr0, [r7, #900] @ 0x384 │ │ - ldc2l 8, cr9, [r5, #344] @ 0x158 │ │ + vcadd.f32 d25, d21, d3, #270 │ │ │ │ 024ceee0 : │ │ push {r4, r5, r6, r8, r9, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #96 @ 0x60 │ │ ldr r9, [fp, #8] │ │ mov r5, r0 │ │ @@ -1450258,29 +1450258,29 @@ │ │ ldr r0, [pc, #76] @ 24cf18c │ │ mov r1, #8 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r8, r9, sl, fp, pc} │ │ - ldc2l 9, cr2, [r6, #302] @ 0x12e @ │ │ + ldc2l 9, cr2, [r6, #392] @ 0x188 @ │ │ eoreq fp, r8, ip, asr #14 │ │ eoreq fp, r8, r0, ror r7 │ │ - ldc2l 7, cr6, [r5, #240] @ 0xf0 │ │ - ldc2l 10, cr12, [r4, #756] @ 0x2f4 @ │ │ - ldc2l 15, cr3, [r5, #164] @ 0xa4 │ │ + ldc2l 7, cr6, [r5, #420] @ 0x1a4 │ │ + ldc2l 10, cr12, [r4, #936] @ 0x3a8 @ │ │ + ldc2l 15, cr3, [r5, #344] @ 0x158 │ │ vcadd.f32 , q4, , #270 │ │ eoreq fp, r8, r8, lsl #13 │ │ eoreq fp, r8, r0, lsr r6 │ │ ldc2l 15, cr11, [r7, #316] @ 0x13c │ │ - ldc2l 14, cr3, [r5, #52] @ 0x34 │ │ + ldc2l 14, cr3, [r5, #232] @ 0xe8 │ │ eoreq fp, r8, ip, asr #11 │ │ - ldc2l 0, cr4, [r6, #24] │ │ + ldc2l 0, cr4, [r6, #204] @ 0xcc │ │ eoreq fp, r8, r0, ror #12 │ │ - ldc2l 7, cr2, [r6, #460] @ 0x1cc │ │ + ldc2l 7, cr2, [r6, #640] @ 0x280 │ │ │ │ 024cf190 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #60 @ 0x3c │ │ mov r5, r3 │ │ mov r4, r2 │ │ @@ -1451384,20 +1451384,20 @@ │ │ ldrbeq r4, [r6, #1136] @ 0x470 │ │ ldrbeq r3, [r6, #3172] @ 0xc64 │ │ ldrbeq r3, [r6, #3828] @ 0xef4 │ │ ldrbeq r3, [r6, #3680] @ 0xe60 │ │ ldrbeq r3, [r6, #3132] @ 0xc3c │ │ ldrbeq r3, [r6, #3792] @ 0xed0 │ │ ldrbeq r4, [r6, #1088] @ 0x440 │ │ - ldc2l 10, cr0, [r5, #260] @ 0x104 @ │ │ - ldc2l 0, cr2, [r5, #68] @ 0x44 │ │ + ldc2l 10, cr0, [r5, #440] @ 0x1b8 @ │ │ + ldc2l 0, cr2, [r5, #248] @ 0xf8 │ │ mlaeq r8, ip, r2, fp │ │ - ldc2l 14, cr11, [r5, #848] @ 0x350 │ │ + ldc2l 15, cr11, [r5, #4] │ │ ldrbeq r4, [r6, #1020] @ 0x3fc │ │ - ldc2l 14, cr1, [r6, #704] @ 0x2c0 │ │ + ldc2l 14, cr1, [r6, #884] @ 0x374 │ │ eoreq fp, r8, r0, ror r2 │ │ ldrbeq r3, [r6, #2980] @ 0xba4 │ │ ldrbeq r3, [r6, #3632] @ 0xe30 │ │ ldc2l 3, cr12, [r6, #736] @ 0x2e0 │ │ ldr r0, [pc, #3960] @ 24d128c │ │ movw r3, #979 @ 0x3d3 │ │ ldr r5, [pc, #3956] @ 24d1290 │ │ @@ -1451506,15 +1451506,15 @@ │ │ rsb r1, r0, #0 │ │ ldr r0, [pc, #4040] @ 24d1484 │ │ add r0, pc, r0 │ │ str r1, [r0] │ │ mov r1, r6 │ │ bl 270e0f0 │ │ b 24d0504 │ │ - ldc2l 1, cr12, [r4, #596] @ 0x254 │ │ + ldc2l 1, cr12, [r4, #776] @ 0x308 │ │ ldrbeq r3, [r6, #2912] @ 0xb60 │ │ ldrbeq r3, [r6, #3564] @ 0xdec │ │ ldrbeq r3, [r6, #4076] @ 0xfec │ │ ldrbeq r4, [r6, #848] @ 0x350 │ │ ldrbeq r4, [r6, #816] @ 0x330 │ │ ldrbeq r3, [r6, #3976] @ 0xf88 │ │ ldrbeq r3, [r6, #3292] @ 0xcdc │ │ @@ -1451634,15 +1451634,15 @@ │ │ ldrbeq r3, [r6, #3456] @ 0xd80 │ │ ldrbeq r4, [r6, #248] @ 0xf8 │ │ ldrbeq r4, [r6, #244] @ 0xf4 │ │ ldrbeq r4, [r6, #224] @ 0xe0 │ │ ldrbeq r4, [r6, #160] @ 0xa0 │ │ ldrbeq r3, [r6, #3932] @ 0xf5c │ │ ldrbeq r3, [r6, #3916] @ 0xf4c │ │ - ldc2l 6, cr0, [r5, #596] @ 0x254 │ │ + ldc2l 6, cr0, [r5, #776] @ 0x308 │ │ ldr r0, [pc, #3796] @ 24d15ac │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ cmp r1, #132 @ 0x84 │ │ bcc 24d0700 │ │ ldr r0, [pc, #3780] @ 24d15b0 │ │ mov r3, #992 @ 0x3e0 │ │ @@ -1451720,15 +1451720,15 @@ │ │ ldrbeq r3, [r6, #3284] @ 0xcd4 │ │ ldrbeq r3, [r6, #3808] @ 0xee0 │ │ ldrbeq r4, [r6, #20] │ │ ldrbeq r3, [r6, #3784] @ 0xec8 │ │ ldrbeq r3, [r6, #3768] @ 0xeb8 │ │ ldrbeq r3, [r6, #4092] @ 0xffc │ │ ldc2l 4, cr4, [r7, #984] @ 0x3d8 │ │ - ldc2l 5, cr0, [r5, #884] @ 0x374 │ │ + ldc2l 6, cr0, [r5, #40] @ 0x28 │ │ ldrbeq r3, [r6, #3132] @ 0xc3c │ │ ldrbeq r3, [r6, #3676] @ 0xe5c │ │ ldrbeq r3, [r6, #3640] @ 0xe38 │ │ ldrbeq r3, [r6, #3940] @ 0xf64 │ │ ldrbeq r3, [r6, #3612] @ 0xe1c │ │ ldrbeq r3, [r6, #3596] @ 0xe0c │ │ mov r1, #255 @ 0xff │ │ @@ -1451781,20 +1451781,20 @@ │ │ add r0, pc, r0 │ │ str r1, [r0] │ │ mov r1, r4 │ │ bl 270e0f0 │ │ ldr r0, [pc, #3592] @ 24d171c │ │ ldr r0, [pc, r0] │ │ b 24d093c │ │ - ldc2l 5, cr0, [r5, #308] @ 0x134 │ │ + ldc2l 5, cr0, [r5, #488] @ 0x1e8 │ │ ldrbeq r3, [r6, #3548] @ 0xddc │ │ ldrbeq r3, [r6, #3520] @ 0xdc0 │ │ ldrbeq r3, [r6, #1772] @ 0x6ec │ │ ldc2l 6, cr5, [r7, #680] @ 0x2a8 │ │ - ldc2l 5, cr0, [r5, #36] @ 0x24 │ │ + ldc2l 5, cr0, [r5, #216] @ 0xd8 │ │ ldr r0, [pc, #3544] @ 24d1710 │ │ ldr r0, [pc, r0] │ │ str r0, [r2, r1, lsl #2] │ │ ldr r1, [pc, #3548] @ 24d1720 │ │ ldr sl, [fp, #20] │ │ ldr r1, [pc, r1] │ │ ldr r2, [pc, #3540] @ 24d1724 │ │ @@ -1451838,21 +1451838,21 @@ │ │ bl 270d9e0 │ │ b 24d1460 │ │ ldrbeq r3, [r6, #2292] @ 0x8f4 │ │ ldrbeq r3, [r6, #3628] @ 0xe2c │ │ ldrbeq r3, [r6, #2124] @ 0x84c │ │ ldrbeq r3, [r6, #3324] @ 0xcfc │ │ ldrbeq r3, [r6, #2744] @ 0xab8 │ │ - ldc2l 4, cr0, [r5, #180] @ 0xb4 │ │ + ldc2l 4, cr0, [r5, #360] @ 0x168 │ │ ldrbeq r3, [r6, #3260] @ 0xcbc │ │ ldrbeq r3, [r6, #3232] @ 0xca0 │ │ ldrbeq r3, [r6, #1484] @ 0x5cc │ │ ldrbeq r3, [r6, #2128] @ 0x850 │ │ ldc2l 2, cr4, [r7, #968] @ 0x3c8 │ │ - ldc2l 3, cr0, [r5, #868] @ 0x364 │ │ + ldc2l 4, cr0, [r5, #24] │ │ ldr r0, [pc, #2912] @ 24d1580 │ │ ldr r1, [pc, #2912] @ 24d1584 │ │ ldr r2, [sp, #28] │ │ add r0, pc, r0 │ │ str r2, [sp] │ │ add r1, pc, r1 │ │ ldr r2, [fp, #16] │ │ @@ -1451889,20 +1451889,20 @@ │ │ b 24d0b78 │ │ ldrbeq r3, [r6, #2616] @ 0xa38 │ │ ldrbeq r3, [r6, #3160] @ 0xc58 │ │ ldrbeq r3, [r6, #3124] @ 0xc34 │ │ ldrbeq r3, [r6, #3112] @ 0xc28 │ │ ldrbeq r3, [r6, #1340] @ 0x53c │ │ ldc2l 4, cr5, [r7, #968] @ 0x3c8 │ │ - ldc2l 3, cr0, [r5, #324] @ 0x144 │ │ + ldc2l 3, cr0, [r5, #504] @ 0x1f8 │ │ ldrbeq r3, [r6, #1948] @ 0x79c │ │ ldrbeq r3, [r6, #3028] @ 0xbd4 │ │ ldc2l 2, cr4, [r7, #184] @ 0xb8 │ │ ldrbeq r3, [r6, #2424] @ 0x978 │ │ - ldc2l 2, cr0, [r5, #964] @ 0x3c4 │ │ + ldc2l 3, cr0, [r5, #120] @ 0x78 │ │ ldrbeq r3, [r6, #2944] @ 0xb80 │ │ ldr r0, [pc, #2788] @ 24d15d0 │ │ ldr r1, [pc, #2788] @ 24d15d4 │ │ ldr r2, [sp, #28] │ │ add r0, pc, r0 │ │ str r2, [sp] │ │ add r1, pc, r1 │ │ @@ -1451955,21 +1451955,21 @@ │ │ b 24d0c8c │ │ ldc2l 4, cr5, [r7, #376] @ 0x178 │ │ ldrbeq r3, [r6, #1804] @ 0x70c │ │ ldrbeq r3, [r6, #2880] @ 0xb40 │ │ ldrbeq r3, [r6, #2860] @ 0xb2c │ │ ldrbeq r3, [r6, #2824] @ 0xb08 │ │ ldrbeq r3, [r6, #1720] @ 0x6b8 │ │ - ldc2l 2, cr0, [r5, #276] @ 0x114 │ │ + ldc2l 2, cr0, [r5, #456] @ 0x1c8 │ │ ldrbeq r3, [r6, #2772] @ 0xad4 │ │ ldrbeq r3, [r6, #2744] @ 0xab8 │ │ ldrbeq r3, [r6, #992] @ 0x3e0 │ │ ldrbeq r3, [r6, #1636] @ 0x664 │ │ ldc2l 3, cr5, [r7, #568] @ 0x238 │ │ - ldc2l 1, cr0, [r5, #948] @ 0x3b4 │ │ + ldc2l 2, cr0, [r5, #104] @ 0x68 │ │ ldr r0, [pc, #2552] @ 24d15ec │ │ ldr r1, [pc, #2552] @ 24d15f0 │ │ ldr r2, [sp, #28] │ │ add r0, pc, r0 │ │ str r2, [sp] │ │ add r1, pc, r1 │ │ ldr r2, [fp, #16] │ │ @@ -1452014,15 +1452014,15 @@ │ │ add r0, pc, r0 │ │ b 24d1458 │ │ ldrbeq r3, [r6, #2680] @ 0xa78 │ │ ldrbeq r3, [r6, #1576] @ 0x628 │ │ ldrbeq r3, [r6, #1536] @ 0x600 │ │ ldc2l 10, cr7, [r7, #144] @ 0x90 @ │ │ ldc2l 3, cr5, [r7, #120] @ 0x78 │ │ - ldc2l 1, cr0, [r5, #500] @ 0x1f4 │ │ + ldc2l 1, cr0, [r5, #680] @ 0x2a8 │ │ ldr r4, [pc, #2372] @ 24d160c │ │ mov r2, #255 @ 0xff │ │ ldr r5, [pc, #2368] @ 24d1610 │ │ add r4, pc, r4 │ │ add r5, pc, r5 │ │ mov r0, r4 │ │ mov r1, r5 │ │ @@ -1452085,24 +1452085,24 @@ │ │ ldrbeq r3, [r6, #2752] @ 0xac0 │ │ ldrbeq r3, [r6, #2740] @ 0xab4 │ │ ldrbeq r3, [r6, #1800] @ 0x708 │ │ ldrbeq r3, [r6, #2688] @ 0xa80 │ │ ldrbeq r3, [r6, #2668] @ 0xa6c │ │ ldrbeq r3, [r6, #2312] @ 0x908 │ │ ldrbeq r3, [r6, #2296] @ 0x8f8 │ │ - ldc2l 0, cr0, [r5, #260] @ 0x104 │ │ + ldc2l 0, cr0, [r5, #440] @ 0x1b8 │ │ ldrbeq r3, [r6, #2256] @ 0x8d0 │ │ ldrbeq r3, [r6, #488] @ 0x1e8 │ │ ldc2l 15, cr3, [r7, #120] @ 0x78 │ │ - ldc2l 0, cr0, [r5, #20] │ │ + ldc2l 0, cr0, [r5, #200] @ 0xc8 │ │ ldrbeq r3, [r6, #1636] @ 0x664 │ │ ldrbeq r3, [r6, #2160] @ 0x870 │ │ ldrbeq r3, [r6, #2172] @ 0x87c │ │ ldc2l 1, cr5, [r7, #376] @ 0x178 │ │ - ldc2l 15, cr15, [r4, #756] @ 0x2f4 │ │ + ldc2l 15, cr15, [r4, #936] @ 0x3a8 │ │ ldrbeq r3, [r6, #2464] @ 0x9a0 │ │ ldrbeq r3, [r6, #2456] @ 0x998 │ │ ldr r0, [pc, #2104] @ 24d1648 │ │ ldr r1, [pc, #2104] @ 24d164c │ │ ldr r2, [sp, #28] │ │ add r0, pc, r0 │ │ str r2, [sp] │ │ @@ -1452158,24 +1452158,24 @@ │ │ bl 270da60 │ │ ldr r3, [pc, #1924] @ 24d1670 │ │ mov r0, r6 │ │ mov r1, r8 │ │ ldr r3, [pc, r3] │ │ b 24d1238 │ │ ldrbeq r3, [r6, #2084] @ 0x824 │ │ - ldc2l 15, cr15, [r4, #436] @ 0x1b4 │ │ + ldc2l 15, cr15, [r4, #616] @ 0x268 │ │ ldrbeq r3, [r6, #2044] @ 0x7fc │ │ ldrbeq r3, [r6, #276] @ 0x114 │ │ ldc2l 14, cr3, [r7, #296] @ 0x128 │ │ - ldc2l 15, cr15, [r4, #196] @ 0xc4 │ │ + ldc2l 15, cr15, [r4, #376] @ 0x178 │ │ ldrbeq r3, [r6, #1984] @ 0x7c0 │ │ ldrbeq r3, [r6, #1416] @ 0x588 │ │ ldrbeq r3, [r6, #1940] @ 0x794 │ │ ldc2l 0, cr5, [r7, #552] @ 0x228 │ │ - ldc2l 14, cr15, [r4, #932] @ 0x3a4 │ │ + ldc2l 15, cr15, [r4, #88] @ 0x58 │ │ ldrbeq r3, [r6, #820] @ 0x334 │ │ ldrbeq r3, [r6, #636] @ 0x27c │ │ ldrbeq r3, [r6, #2188] @ 0x88c │ │ ldrbeq r3, [r6, #584] @ 0x248 │ │ ldrbeq r3, [r6, #1244] @ 0x4dc │ │ ldrbeq r3, [r6, #1784] @ 0x6f8 │ │ ldr r0, [pc, #1928] @ 24d16cc │ │ @@ -1452293,20 +1452293,20 @@ │ │ ldrbeq r3, [r6, #464] @ 0x1d0 │ │ ldrbeq r3, [r6, #1884] @ 0x75c │ │ ldrbeq r3, [r6, #956] @ 0x3bc │ │ ldrbeq r3, [r6, #1844] @ 0x734 │ │ ldrbeq r3, [r6, #1468] @ 0x5bc │ │ ldrbeq r3, [r6, #1452] @ 0x5ac │ │ ldc2l 12, cr3, [r7, #24] │ │ - ldc2l 12, cr15, [r4, #948] @ 0x3b4 │ │ + ldc2l 13, cr15, [r4, #104] @ 0x68 │ │ ldrbeq r3, [r6, #1768] @ 0x6e8 │ │ ldrbeq r3, [r6, #836] @ 0x344 │ │ ldrbeq r3, [r6, #1676] @ 0x68c │ │ ldc2l 11, cr3, [r7, #440] @ 0x1b8 @ │ │ - ldc2l 12, cr15, [r4, #340] @ 0x154 │ │ + ldc2l 12, cr15, [r4, #520] @ 0x208 │ │ ldrbeq r3, [r6, #1620] @ 0x654 │ │ ldrbeq r3, [r6, #692] @ 0x2b4 │ │ ldr r0, [pc, #1352] @ 24d1688 │ │ ldr r1, [pc, #1352] @ 24d168c │ │ ldr r2, [sp, #28] │ │ add r0, pc, r0 │ │ str r2, [sp] │ │ @@ -1452387,15 +1452387,15 @@ │ │ mov r1, r5 │ │ bl 270ece0 │ │ ldr r0, [pc, #656] @ 24d1514 │ │ mov r1, #160 @ 0xa0 │ │ add r0, pc, r0 │ │ b 24d13cc │ │ ldc2l 3, cr7, [r7, #976] @ 0x3d0 │ │ - ldc2l 11, cr15, [r4, #420] @ 0x1a4 @ │ │ + ldc2l 11, cr15, [r4, #600] @ 0x258 @ │ │ ldrbeq r2, [r6, #3348] @ 0xd14 │ │ ldrbeq r3, [r6, #972] @ 0x3cc │ │ ldrbeq r3, [r6, #1352] @ 0x548 │ │ ldc2l 12, cr4, [r7, #760] @ 0x2f8 │ │ ldr r2, [pc, #648] @ 24d1534 │ │ add r0, r1, r0 │ │ ldr r4, [pc, #644] @ 24d1538 │ │ @@ -1452445,20 +1452445,20 @@ │ │ add r0, pc, r0 │ │ b 24d145c │ │ ldrbeq r2, [r6, #3948] @ 0xf6c │ │ ldrbeq r3, [r6, #908] @ 0x38c │ │ ldrbeq r3, [r6, #1280] @ 0x500 │ │ ldrbeq r3, [r6, #1260] @ 0x4ec │ │ ldc2l 9, cr3, [r7, #436] @ 0x1b4 @ │ │ - ldc2l 10, cr15, [r4, #772] @ 0x304 @ │ │ + ldc2l 10, cr15, [r4, #952] @ 0x3b8 @ │ │ ldrbeq r3, [r6, #292] @ 0x124 │ │ ldrbeq r3, [r6, #1184] @ 0x4a0 │ │ ldrbeq r3, [r6, #1176] @ 0x498 │ │ ldc2l 9, cr3, [r7, #268] @ 0x10c @ │ │ - ldc2l 10, cr15, [r4, #436] @ 0x1b4 @ │ │ + ldc2l 10, cr15, [r4, #616] @ 0x268 @ │ │ ldrbeq r3, [r6, #208] @ 0xd0 │ │ ldrbeq r3, [r6, #716] @ 0x2cc │ │ ldrbeq r3, [r6, #708] @ 0x2c4 │ │ ldrbeq r3, [r6, #972] @ 0x3cc │ │ ldr r4, [pc, #432] @ 24d1558 │ │ mov r2, #255 @ 0xff │ │ ldr r5, [pc, #428] @ 24d155c │ │ @@ -1452548,75 +1452548,75 @@ │ │ ldrbeq r3, [r6, #392] @ 0x188 │ │ ldrbeq r3, [r6, #380] @ 0x17c │ │ ldrbeq r3, [r6, #360] @ 0x168 │ │ ldrbeq r3, [r6, #308] @ 0x134 │ │ ldrbeq r3, [r6, #284] @ 0x11c │ │ ldrbeq r1, [r6, #3293] @ 0xcdd │ │ ldrbeq r2, [r6, #1544] @ 0x608 │ │ - ldc2l 9, cr10, [r4, #122] @ 0x7a @ │ │ + ldc2l 9, cr10, [r4, #212] @ 0xd4 @ │ │ ldrbeq r2, [r6, #1096] @ 0x448 │ │ ldrbeq r1, [r6, #3696] @ 0xe70 │ │ ldrbeq r2, [r6, #1064] @ 0x428 │ │ - ldc2l 10, cr1, [r5, #980] @ 0x3d4 @ │ │ + ldc2l 11, cr1, [r5, #136] @ 0x88 @ │ │ ldrbeq r2, [r6, #1020] @ 0x3fc │ │ ldrbeq r2, [r6, #1004] @ 0x3ec │ │ - ldc2l 9, cr8, [r5, #374] @ 0x176 @ │ │ + ldc2l 9, cr8, [r5, #464] @ 0x1d0 @ │ │ ldrbeq r2, [r6, #1408] @ 0x580 │ │ ldrbeq r1, [r6, #3213] @ 0xc8d │ │ ldrbeq r2, [r6, #1464] @ 0x5b8 │ │ ldrbeq r2, [r6, #1348] @ 0x544 │ │ - ldc2l 5, cr6, [r6, #572] @ 0x23c │ │ - ldc2l 11, cr1, [r5, #980] @ 0x3d4 @ │ │ + ldc2l 5, cr6, [r6, #752] @ 0x2f0 │ │ + ldc2l 12, cr1, [r5, #136] @ 0x88 │ │ ldrbeq r2, [r6, #1284] @ 0x504 │ │ ldrbeq r2, [r6, #1272] @ 0x4f8 │ │ - ldc2l 5, cr0, [r6, #384] @ 0x180 │ │ + ldc2l 5, cr0, [r6, #564] @ 0x234 │ │ ldrbeq r1, [r6, #2969] @ 0xb99 │ │ ldrbeq r2, [r6, #1220] @ 0x4c4 │ │ - ldc2l 6, cr14, [r5, #944] @ 0x3b0 │ │ + ldc2l 7, cr14, [r5, #100] @ 0x64 │ │ ldrbeq r1, [r6, #2737] @ 0xab1 │ │ ldrbeq r2, [r6, #988] @ 0x3dc │ │ ldrbeq r2, [r6, #880] @ 0x370 │ │ ldc2l 6, cr12, [r6, #224] @ 0xe0 │ │ - ldc2l 1, cr2, [r5, #484] @ 0x1e4 │ │ + ldc2l 1, cr2, [r5, #664] @ 0x298 │ │ ldrbeq r2, [r6, #2696] @ 0xa88 │ │ - ldc2l 6, cr14, [r5, #836] @ 0x344 │ │ + ldc2l 6, cr14, [r5, #1016] @ 0x3f8 │ │ ldrbeq r2, [r6, #3656] @ 0xe48 │ │ ldrbeq r2, [r6, #3608] @ 0xe18 │ │ ldrbeq r2, [r6, #1261] @ 0x4ed │ │ ldrbeq r2, [r6, #3608] @ 0xe18 │ │ ldrbeq r2, [r6, #3504] @ 0xdb0 │ │ ldrbeq r2, [r6, #3480] @ 0xd98 │ │ - ldc2l 14, cr6, [r6, #668] @ 0x29c │ │ - ldc2l 3, cr2, [r5, #468] @ 0x1d4 │ │ + ldc2l 14, cr6, [r6, #848] @ 0x350 │ │ + ldc2l 3, cr2, [r5, #648] @ 0x288 │ │ ldrbeq r2, [r6, #3228] @ 0xc9c │ │ ldrbeq r2, [r6, #3200] @ 0xc80 │ │ ldc2l 5, cr12, [r6, #484] @ 0x1e4 │ │ ldrbeq r3, [r6, #444] @ 0x1bc │ │ ldc2l 6, cr3, [r7, #680] @ 0x2a8 │ │ - ldc2l 7, cr15, [r4, #580] @ 0x244 │ │ + ldc2l 7, cr15, [r4, #760] @ 0x2f8 │ │ ldrbeq r2, [r6, #3572] @ 0xdf4 │ │ ldrbeq r3, [r6, #368] @ 0x170 │ │ ldrbeq r3, [r6, #360] @ 0x168 │ │ ldc2l 6, cr3, [r7, #344] @ 0x158 │ │ - ldc2l 7, cr15, [r4, #244] @ 0xf4 │ │ + ldc2l 7, cr15, [r4, #424] @ 0x1a8 │ │ ldrbeq r2, [r6, #3488] @ 0xda0 │ │ ldrbeq r2, [r6, #3452] @ 0xd7c │ │ ldrbeq r2, [r6, #3404] @ 0xd4c │ │ ldrbeq r2, [r6, #1057] @ 0x421 │ │ ldrbeq r2, [r6, #3404] @ 0xd4c │ │ ldrbeq r2, [r6, #3300] @ 0xce4 │ │ ldrbeq r2, [r6, #3276] @ 0xccc │ │ ldc2l 14, cr8, [r6, #136] @ 0x88 │ │ ldrbeq r2, [r6, #3188] @ 0xc74 │ │ ldrbeq r2, [r6, #3140] @ 0xc44 │ │ ldrbeq r2, [r6, #793] @ 0x319 │ │ ldrbeq r2, [r6, #3140] @ 0xc44 │ │ ldrbeq r2, [r6, #3032] @ 0xbd8 │ │ - ldc2l 1, cr7, [r5, #172] @ 0xac │ │ - ldc2l 2, cr2, [r5, #548] @ 0x224 │ │ + ldc2l 1, cr7, [r5, #352] @ 0x160 │ │ + ldc2l 2, cr2, [r5, #728] @ 0x2d8 │ │ ldrbeq r2, [r6, #2980] @ 0xba4 │ │ ldrbeq r2, [r6, #633] @ 0x279 │ │ ldrbeq r2, [r6, #2980] @ 0xba4 │ │ ldrbeq r2, [r6, #2872] @ 0xb38 │ │ ldc2l 14, cr12, [r6, #424] @ 0x1a8 │ │ ldrbeq r3, [r6, #540] @ 0x21c │ │ ldrbeq r3, [r6, #224] @ 0xe0 │ │ @@ -1452632,51 +1452632,51 @@ │ │ ldrbeq r2, [r6, #2648] @ 0xa58 │ │ ldrbeq r2, [r6, #2600] @ 0xa28 │ │ ldrbeq r2, [r6, #253] @ 0xfd │ │ ldrbeq r2, [r6, #2600] @ 0xa28 │ │ ldrbeq r2, [r6, #2496] @ 0x9c0 │ │ ldrbeq r2, [r6, #2472] @ 0x9a8 │ │ ldc2l 11, cr8, [r6, #816] @ 0x330 @ │ │ - ldc2l 0, cr2, [r5, #340] @ 0x154 │ │ + ldc2l 0, cr2, [r5, #520] @ 0x208 │ │ ldrbeq r2, [r6, #2136] @ 0x858 │ │ ldrbeq r2, [r6, #2388] @ 0x954 │ │ ldrbeq r2, [r6, #2364] @ 0x93c │ │ - ldc2l 13, cr14, [r4, #8] │ │ + ldc2l 13, cr14, [r4, #188] @ 0xbc │ │ ldrbeq r2, [r6, #2716] @ 0xa9c │ │ ldrbeq r3, [r6, #148] @ 0x94 │ │ ldrbeq r2, [r6, #3928] @ 0xf58 │ │ ldc2l 6, cr6, [r4, #380] @ 0x17c │ │ ldrbeq r2, [r6, #1832] @ 0x728 │ │ ldrbeq r2, [r6, #1784] @ 0x6f8 │ │ ldrbeq r1, [r6, #3533] @ 0xdcd │ │ ldrbeq r2, [r6, #1784] @ 0x6f8 │ │ ldrbeq r2, [r6, #1676] @ 0x68c │ │ ldrbeq r2, [r6, #1412] @ 0x584 │ │ ldrbeq r2, [r6, #1376] @ 0x560 │ │ - ldc2l 12, cr6, [r5, #76] @ 0x4c │ │ - ldc2l 13, cr1, [r5, #132] @ 0x84 │ │ + ldc2l 12, cr6, [r5, #256] @ 0x100 │ │ + ldc2l 13, cr1, [r5, #312] @ 0x138 │ │ ldrbeq r2, [r6, #1316] @ 0x524 │ │ ldrbeq r2, [r6, #1308] @ 0x51c │ │ ldrbeq r2, [r6, #1260] @ 0x4ec │ │ ldrbeq r3, [r6, #4] │ │ ldrbeq r2, [r6, #3784] @ 0xec8 │ │ ldrbeq r2, [r6, #3756] @ 0xeac │ │ ldc2l 5, cr6, [r4, #812] @ 0x32c │ │ ldrbeq r2, [r6, #2504] @ 0x9c8 │ │ ldrbeq r2, [r6, #2340] @ 0x924 │ │ ldrbeq r2, [r6, #2292] @ 0x8f4 │ │ ldrbeq r1, [r6, #4041] @ 0xfc9 │ │ ldrbeq r2, [r6, #2292] @ 0x8f4 │ │ ldrbeq r2, [r6, #1916] @ 0x77c │ │ ldc2l 1, cr10, [r7, #308] @ 0x134 │ │ - ldc2l 15, cr1, [r5, #244] @ 0xf4 │ │ + ldc2l 15, cr1, [r5, #424] @ 0x1a8 │ │ ldrbeq r2, [r6, #1856] @ 0x740 │ │ ldrbeq r2, [r6, #1844] @ 0x734 │ │ ldrbeq r2, [r6, #1792] @ 0x700 │ │ - ldc2l 2, cr8, [r5, #724] @ 0x2d4 │ │ + ldc2l 2, cr8, [r5, #904] @ 0x388 │ │ ldrbeq r2, [r6, #521] @ 0x209 │ │ ldrbeq r2, [r6, #2868] @ 0xb34 │ │ ldrbeq r2, [r6, #2760] @ 0xac8 │ │ ldc2l 12, cr15, [r7, #216] @ 0xd8 │ │ ldrbeq r2, [r6, #3988] @ 0xf94 │ │ ldrbeq r2, [r6, #3964] @ 0xf7c │ │ ldrbeq r2, [r6, #3860] @ 0xf14 │ │ @@ -1452692,15 +1452692,15 @@ │ │ ldrbeq r2, [r6, #3420] @ 0xd5c │ │ ldrbeq r2, [r6, #2064] @ 0x810 │ │ ldrbeq r2, [r6, #2016] @ 0x7e0 │ │ ldrbeq r1, [r6, #3765] @ 0xeb5 │ │ ldrbeq r2, [r6, #2016] @ 0x7e0 │ │ ldrbeq r2, [r6, #1908] @ 0x774 │ │ ldc2l 12, cr4, [r4, #612] @ 0x264 │ │ - ldc2l 14, cr1, [r5, #148] @ 0x94 │ │ + ldc2l 14, cr1, [r5, #328] @ 0x148 │ │ ldrbeq r2, [r6, #1848] @ 0x738 │ │ ldrbeq r2, [r6, #1253] @ 0x4e5 │ │ ldc2l 3, cr2, [r4, #688] @ 0x2b0 │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ │ │ 024d1768 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ @@ -1453007,29 +1453007,29 @@ │ │ nop {0} │ │ andeq r0, r0, r0 │ │ adcmi r2, ip, r0 │ │ andeq r0, r0, r0 │ │ submi r0, lr, r0 │ │ ldc2l 6, cr5, [r4, #764] @ 0x2fc │ │ ldc2l 6, cr5, [r4, #76] @ 0x4c │ │ - ldc2l 6, cr4, [r5, #208] @ 0xd0 │ │ - ldc2l 6, cr1, [r5, #276] @ 0x114 │ │ + ldc2l 6, cr4, [r5, #388] @ 0x184 │ │ + ldc2l 6, cr1, [r5, #456] @ 0x1c8 │ │ ldc2l 5, cr5, [r4, #812] @ 0x32c │ │ ldc2l 14, cr5, [r7, #436] @ 0x1b4 │ │ ldc2l 5, cr5, [r4, #348] @ 0x15c │ │ ldc2l 15, cr9, [r6, #396] @ 0x18c │ │ ldc2l 15, cr9, [r6, #544] @ 0x220 │ │ ldc2l 2, cr13, [r7, #760] @ 0x2f8 │ │ - ldc2l 5, cr0, [r5, #964] @ 0x3c4 │ │ - ldc2l 5, cr0, [r5, #356] @ 0x164 │ │ + ldc2l 6, cr0, [r5, #120] @ 0x78 │ │ + ldc2l 5, cr0, [r5, #536] @ 0x218 │ │ ldc2l 14, cr9, [r6, #332] @ 0x14c │ │ ldc2l 14, cr9, [r6, #208] @ 0xd0 │ │ eoreq r8, r8, r4, lsl #24 │ │ - ldc2l 0, cr6, [r6, #396] @ 0x18c │ │ - ldc2l 5, cr1, [r5, #308] @ 0x134 │ │ + ldc2l 0, cr6, [r6, #576] @ 0x240 │ │ + ldc2l 5, cr1, [r5, #488] @ 0x1e8 │ │ │ │ 024d1c74 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #52 @ 0x34 │ │ str r2, [sp, #40] @ 0x28 │ │ str r1, [sp, #32] │ │ @@ -1454084,37 +1454084,37 @@ │ │ eoreq r8, r8, r0, lsr sl │ │ ldrbeq r3, [r6, #2032] @ 0x7f0 │ │ ldrbeq r1, [r6, #3000] @ 0xbb8 │ │ ldrbeq r2, [r6, #2500] @ 0x9c4 │ │ ldrbeq r3, [r6, #1964] @ 0x7ac │ │ ldrbeq r3, [r6, #1944] @ 0x798 │ │ ldrbeq r3, [r6, #1932] @ 0x78c │ │ - ldc2l 0, cr8, [r5, #540] @ 0x21c │ │ + ldc2l 0, cr8, [r5, #720] @ 0x2d0 │ │ ldc2l 11, cr9, [r7, #904] @ 0x388 @ │ │ ldc2l 2, cr7, [r7, #792] @ 0x318 │ │ - ldc2l 11, cr3, [r6, #148] @ 0x94 @ │ │ + ldc2l 11, cr3, [r6, #328] @ 0x148 @ │ │ ldrbeq r3, [r6, #1860] @ 0x744 │ │ ldc2l 11, cr9, [r7, #536] @ 0x218 @ │ │ ldrbeq r3, [r6, #1816] @ 0x718 │ │ - ldc2l 10, cr15, [r5, #636] @ 0x27c @ │ │ + ldc2l 10, cr15, [r5, #816] @ 0x330 @ │ │ ldc2l 11, cr9, [r7, #312] @ 0x138 @ │ │ ldrbeq r3, [r6, #1764] @ 0x6e4 │ │ ldrbeq r3, [r6, #1744] @ 0x6d0 │ │ ldc2l 2, cr7, [r7, #200] @ 0xc8 │ │ - ldc2l 10, cr3, [r6, #580] @ 0x244 @ │ │ + ldc2l 10, cr3, [r6, #760] @ 0x2f8 @ │ │ ldrbeq r3, [r6, #1712] @ 0x6b0 │ │ ldc2l 10, cr9, [r7, #968] @ 0x3c8 @ │ │ ldc2l 9, cr15, [r6, #190] @ 0xbe @ │ │ - ldc2l 10, cr15, [r5, #88] @ 0x58 @ │ │ + ldc2l 10, cr15, [r5, #268] @ 0x10c @ │ │ ldrbeq r3, [r6, #1628] @ 0x65c │ │ - ldc2l 11, cr5, [r6, #680] @ 0x2a8 @ │ │ + ldc2l 11, cr5, [r6, #860] @ 0x35c @ │ │ ldc2l 4, cr6, [r4, #104] @ 0x68 │ │ ldc2l 11, cr14, [r7, #532] @ 0x214 @ │ │ - ldc2l 11, cr11, [r5, #168] @ 0xa8 @ │ │ - ldc2l 13, cr9, [r4, #168] @ 0xa8 │ │ + ldc2l 11, cr11, [r5, #348] @ 0x15c @ │ │ + ldc2l 13, cr9, [r4, #348] @ 0x15c │ │ ldrbeq r3, [r6, #1512] @ 0x5e8 │ │ ldr r0, [pc, #3992] @ 24d3d04 │ │ mov r1, r6 │ │ ldr r2, [pc, #3988] @ 24d3d08 │ │ movw r3, #1170 @ 0x492 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1454230,17 +1454230,17 @@ │ │ mov r2, r5 │ │ bl 270e2a0 │ │ ldr r1, [pc, #3596] @ 24d3d4c │ │ str r9, [sp] │ │ add r1, pc, r1 │ │ b 24d2390 │ │ ldc2l 9, cr9, [r6, #178] @ 0xb2 @ │ │ - ldc2l 12, cr9, [r4, #952] @ 0x3b8 │ │ + ldc2l 13, cr9, [r4, #108] @ 0x6c │ │ ldrbeq r3, [r6, #1452] @ 0x5ac │ │ - ldc2l 15, cr0, [r5, #492] @ 0x1ec │ │ + ldc2l 15, cr0, [r5, #672] @ 0x2a0 │ │ ldc2l 12, cr12, [r7, #472] @ 0x1d8 │ │ ldc2l 8, cr15, [r6, #344] @ 0x158 │ │ ldc2l 4, cr1, [r7, #352] @ 0x160 │ │ ldrbeq r3, [r6, #1360] @ 0x550 │ │ ldr r5, [pc, #3552] @ 24d3d50 │ │ mov r1, #12 │ │ add r5, pc, r5 │ │ @@ -1454275,29 +1454275,29 @@ │ │ add r2, pc, r2 │ │ bl 27100c0 │ │ ldr r6, [fp, #48] @ 0x30 │ │ b 24d309c │ │ ldc2l 14, cr4, [r4, #156] @ 0x9c │ │ ldrbeq r1, [r6, #2152] @ 0x868 │ │ ldrbeq r1, [r6, #2128] @ 0x850 │ │ - ldc2l 12, cr1, [r6, #780] @ 0x30c │ │ + ldc2l 12, cr1, [r6, #960] @ 0x3c0 │ │ ldc2l 11, cr12, [r7, #496] @ 0x1f0 @ │ │ ldrbeq r3, [r6, #1156] @ 0x484 │ │ ldrbeq r3, [r6, #1120] @ 0x460 │ │ ldrbeq r3, [r6, #1080] @ 0x438 │ │ ldrbeq r1, [r6, #2044] @ 0x7fc │ │ ldc2l 13, cr4, [r4, #60] @ 0x3c │ │ vcadd.f32 q15, , , #270 │ │ - ldc2l 13, cr2, [r5, #992] @ 0x3e0 │ │ + ldc2l 14, cr2, [r5, #148] @ 0x94 │ │ ldrbeq r1, [r6, #1860] @ 0x744 │ │ ldrbeq r1, [r6, #1860] @ 0x744 │ │ ldrbeq r1, [r6, #1812] @ 0x714 │ │ ldrbeq r1, [r6, #1800] @ 0x708 │ │ ldc2l 14, cr7, [r4, #912] @ 0x390 │ │ - ldc2l 10, cr11, [r4, #280] @ 0x118 @ │ │ + ldc2l 10, cr11, [r4, #460] @ 0x1cc @ │ │ ldrbeq r3, [r6, #824] @ 0x338 │ │ ldr r0, [pc, #3364] @ 24d3d6c │ │ mov r2, #5 │ │ ldr r1, [pc, #3360] @ 24d3d70 │ │ mov r3, #1 │ │ add r0, pc, r0 │ │ ldr r1, [pc, r1] │ │ @@ -1454398,48 +1454398,48 @@ │ │ add r1, pc, r1 │ │ bl 270d9e0 │ │ ldr r1, [fp, #20] │ │ mov r0, #0 │ │ str r0, [r1] │ │ b 24d23a0 │ │ ldc2l 10, cr12, [r7, #88] @ 0x58 @ │ │ - ldc2l 10, cr9, [r4, #296] @ 0x128 @ │ │ + ldc2l 10, cr9, [r4, #476] @ 0x1dc @ │ │ ldc2l 7, cr2, [r4, #700] @ 0x2bc │ │ - ldc2l 10, cr9, [r4, #120] @ 0x78 @ │ │ + ldc2l 10, cr9, [r4, #300] @ 0x12c @ │ │ ldrbeq r3, [r6, #728] @ 0x2d8 │ │ - ldc2l 9, cr13, [r5, #154] @ 0x9a @ │ │ - ldc2l 9, cr9, [r4, #492] @ 0x1ec @ │ │ + ldc2l 9, cr13, [r5, #244] @ 0xf4 @ │ │ + ldc2l 10, cr9, [r4, #140] @ 0x8c @ │ │ ldrbeq r3, [r6, #688] @ 0x2b0 │ │ ldc2l 13, cr2, [r7, #588] @ 0x24c │ │ - ldc2l 2, cr1, [r6, #600] @ 0x258 │ │ - ldc2l 12, cr9, [r5, #904] @ 0x388 │ │ + ldc2l 2, cr1, [r6, #780] @ 0x30c │ │ + ldc2l 13, cr9, [r5, #60] @ 0x3c │ │ eoreq r8, r8, r8, lsr #8 │ │ ldc2l 11, cr4, [r4, #44] @ 0x2c @ │ │ ldc2l 0, cr5, [r4, #908] @ 0x38c │ │ eoreq r8, r8, r4, ror #7 │ │ ldrbeq r3, [r6, #432] @ 0x1b0 │ │ ldc2l 13, cr8, [r7, #668] @ 0x29c │ │ ldrbeq r1, [r6, #1284] @ 0x504 │ │ ldc2l 4, cr15, [r6, #200] @ 0xc8 │ │ - ldc2l 7, cr5, [r6, #48] @ 0x30 │ │ + ldc2l 7, cr5, [r6, #228] @ 0xe4 │ │ ldrbeq r3, [r6, #296] @ 0x128 │ │ ldc2l 5, cr2, [r4, #828] @ 0x33c │ │ ldc2l 13, cr8, [r7, #92] @ 0x5c │ │ ldc2l 5, cr2, [r4, #636] @ 0x27c │ │ ldrbeq r3, [r6, #208] @ 0xd0 │ │ ldrbeq r1, [r6, #1116] @ 0x45c │ │ - ldc2l 10, cr13, [r4, #772] @ 0x304 @ │ │ + ldc2l 10, cr13, [r4, #952] @ 0x3b8 @ │ │ ldc2l 9, cr3, [r4, #254] @ 0xfe @ │ │ ldrbeq r3, [r6, #124] @ 0x7c │ │ - ldc2l 9, cr1, [r5, #294] @ 0x126 @ │ │ - ldc2l 10, cr3, [r5, #252] @ 0xfc @ │ │ + ldc2l 9, cr1, [r5, #384] @ 0x180 @ │ │ + ldc2l 10, cr3, [r5, #432] @ 0x1b0 @ │ │ ldrbeq r3, [r6, #80] @ 0x50 │ │ ldc2l 5, cr14, [r7, #672] @ 0x2a0 │ │ - ldc2l 7, cr11, [r4, #216] @ 0xd8 │ │ - ldc2l 0, cr1, [r6, #536] @ 0x218 │ │ + ldc2l 7, cr11, [r4, #396] @ 0x18c │ │ + ldc2l 0, cr1, [r6, #716] @ 0x2cc │ │ ldc2l 6, cr11, [r6, #916] @ 0x394 │ │ ldc2l 2, cr15, [r6, #888] @ 0x378 │ │ ldc2l 14, cr0, [r7, #880] @ 0x370 │ │ ldr r0, [pc, #2864] @ 24d3db8 │ │ ldr r0, [pc, r0] │ │ ldr r5, [pc, #2860] @ 24d3dbc │ │ cmp r0, #0 │ │ @@ -1454617,40 +1454617,40 @@ │ │ str r2, [sp, #8] │ │ add r2, r8, r0 │ │ add r1, pc, r1 │ │ str r7, [sp] │ │ str r6, [sp, #4] │ │ b 24d39bc │ │ ldc2l 11, cr8, [r7, #1012] @ 0x3f4 @ │ │ - ldc2l 4, cr11, [r5, #952] @ 0x3b8 │ │ + ldc2l 5, cr11, [r5, #108] @ 0x6c │ │ sub r5, r0, #1 │ │ cmp r0, #300 @ 0x12c │ │ bhi 24d35d8 │ │ mov r1, r5 │ │ ldr r6, [fp, #44] @ 0x2c │ │ ldr sl, [fp, #-36] @ 0xffffffdc │ │ ldr r8, [fp, #20] │ │ ldr r4, [fp, #36] @ 0x24 │ │ b 24d3638 │ │ - ldc2l 9, cr15, [r4, #424] @ 0x1a8 @ │ │ + ldc2l 10, cr15, [r4, #4] @ │ │ ldrbeq r1, [r6, #764] @ 0x2fc │ │ ldrbeq r1, [r6, #776] @ 0x308 │ │ ldrbeq r2, [r6, #3908] @ 0xf44 │ │ ldc2l 2, cr6, [r7, #936] @ 0x3a8 │ │ ldrbeq r2, [r6, #3876] @ 0xf24 │ │ - ldc2l 3, cr3, [r6, #36] @ 0x24 │ │ + ldc2l 3, cr3, [r6, #216] @ 0xd8 │ │ ldrbeq r2, [r6, #3840] @ 0xf00 │ │ ldc2l 6, cr5, [r7, #884] @ 0x374 │ │ ldrbeq r2, [r6, #3792] @ 0xed0 │ │ - ldc2l 9, cr2, [r5, #96] @ 0x60 @ │ │ + ldc2l 9, cr2, [r5, #186] @ 0xba @ │ │ ldrbeq r2, [r6, #3756] @ 0xeac │ │ ldrbeq r2, [r6, #3740] @ 0xe9c │ │ ldrbeq r2, [r6, #3740] @ 0xe9c │ │ ldrbeq r2, [r6, #3720] @ 0xe88 │ │ - ldc2l 3, cr5, [r6, #916] @ 0x394 │ │ + ldc2l 4, cr5, [r6, #72] @ 0x48 │ │ ldc2l 0, cr5, [r7, #176] @ 0xb0 │ │ ldrbeq r1, [r6, #476] @ 0x1dc │ │ ldc2l 15, cr4, [r7, #912] @ 0x390 │ │ ldrbeq r1, [r6, #408] @ 0x198 │ │ vcadd.f32 q9, , q1, #270 │ │ ldrbeq r1, [r6, #308] @ 0x134 │ │ ldr r0, [pc, #3324] @ 24d42dc │ │ @@ -1454755,25 +1454755,25 @@ │ │ bl 270e2a0 │ │ ldr r1, [pc, #2988] @ 24d431c │ │ add r4, r4, r7, lsl #2 │ │ add r1, pc, r1 │ │ b 24d2348 │ │ ldrbeq r1, [r6, #308] @ 0x134 │ │ ldc2l 6, cr4, [r4, #588] @ 0x24c │ │ - ldc2l 2, cr5, [r6, #656] @ 0x290 │ │ - ldc2l 5, cr0, [r5, #224] @ 0xe0 │ │ - ldc2l 2, cr5, [r6, #468] @ 0x1d4 │ │ + ldc2l 2, cr5, [r6, #836] @ 0x344 │ │ + ldc2l 5, cr0, [r5, #404] @ 0x194 │ │ + ldc2l 2, cr5, [r6, #648] @ 0x288 │ │ ldrbeq r2, [r6, #3336] @ 0xd08 │ │ - ldc2l 2, cr5, [r6, #308] @ 0x134 │ │ - ldc2l 2, cr5, [r6, #260] @ 0x104 │ │ + ldc2l 2, cr5, [r6, #488] @ 0x1e8 │ │ + ldc2l 2, cr5, [r6, #440] @ 0x1b8 │ │ ldrbeq r2, [r6, #3244] @ 0xcac │ │ ldrbeq r1, [r6, #3720] @ 0xe88 │ │ ldrbeq r2, [r6, #3212] @ 0xc8c │ │ - ldc2l 12, cr0, [r6, #716] @ 0x2cc │ │ - ldc2l 6, cr9, [r5, #984] @ 0x3d8 │ │ + ldc2l 12, cr0, [r6, #896] @ 0x380 │ │ + ldc2l 7, cr9, [r5, #140] @ 0x8c │ │ eoreq r7, r8, ip, lsr lr │ │ ldc2l 5, cr4, [r4, #92] @ 0x5c │ │ ldc2l 10, cr4, [r4, #1004] @ 0x3ec @ │ │ strdeq r7, [r8], -r8 @ │ │ ldrbeq r2, [r6, #3012] @ 0xbc4 │ │ ldc2l 4, cr4, [r4, #732] @ 0x2dc │ │ ldc2l 10, cr4, [r4, #620] @ 0x26c @ │ │ @@ -1454909,42 +1454909,42 @@ │ │ ldr r0, [fp, #24] │ │ mov r1, sl │ │ b 24d2cd8 │ │ ldrbeq r2, [r6, #2860] @ 0xb2c │ │ ldc2l 14, cr8, [r6, #780] @ 0x30c │ │ ldc2l 14, cr8, [r6, #784] @ 0x310 │ │ ldrbeq r2, [r6, #2800] @ 0xaf0 │ │ - ldc2l 0, cr11, [r5, #148] @ 0x94 │ │ - ldc2l 5, cr15, [r4, #168] @ 0xa8 │ │ + ldc2l 0, cr11, [r5, #328] @ 0x148 │ │ + ldc2l 5, cr15, [r4, #348] @ 0x15c │ │ ldc2l 3, cr4, [r4, #892] @ 0x37c │ │ ldrbeq r2, [r6, #2716] @ 0xa9c │ │ eoreq r7, r8, r4, asr #25 │ │ eoreq r7, r8, ip, ror #24 │ │ ldc2l 2, cr5, [r7, #304] @ 0x130 │ │ - ldc2l 15, cr4, [r6, #740] @ 0x2e4 │ │ + ldc2l 15, cr4, [r6, #920] @ 0x398 │ │ eoreq r7, r8, r0, lsr ip │ │ ldrbeq r2, [r6, #2588] @ 0xa1c │ │ ldrbeq r2, [r6, #2544] @ 0x9f0 │ │ ldrbeq r0, [r6, #3512] @ 0xdb8 │ │ ldrbeq r2, [r6, #2536] @ 0x9e8 │ │ ldrbeq r2, [r6, #2532] @ 0x9e4 │ │ ldc2l 12, cr14, [r6, #580] @ 0x244 │ │ ldrbeq r0, [r6, #3368] @ 0xd28 │ │ ldrbeq r1, [r6, #2908] @ 0xb5c │ │ ldc2l 2, cr4, [r4, #524] @ 0x20c │ │ - vcadd.f32 q15, q2, q10, #270 │ │ + ldc2l 8, cr14, [r4, #580] @ 0x244 │ │ ldrbeq r1, [r6, #2788] @ 0xae4 │ │ - ldc2l 11, cr8, [r5, #336] @ 0x150 @ │ │ + ldc2l 11, cr8, [r5, #516] @ 0x204 @ │ │ ldrbeq r0, [r6, #3192] @ 0xc78 │ │ - ldc2l 3, cr9, [r5, #688] @ 0x2b0 │ │ + ldc2l 3, cr9, [r5, #868] @ 0x364 │ │ ldrbeq r2, [r6, #2256] @ 0x8d0 │ │ ldrbeq r0, [r6, #3136] @ 0xc40 │ │ ldrbeq r1, [r6, #2664] @ 0xa68 │ │ - ldc2l 2, cr0, [r5, #340] @ 0x154 │ │ - ldc2l 9, cr14, [r4, #148] @ 0x94 @ │ │ + ldc2l 2, cr0, [r5, #520] @ 0x208 │ │ + ldc2l 9, cr14, [r4, #238] @ 0xee @ │ │ ldr r0, [pc, #2460] @ 24d43fc │ │ mov r1, #1 │ │ mov r9, r4 │ │ add r0, pc, r0 │ │ bl 27100e0 │ │ cmp r0, #0 │ │ beq 24d3dc4 │ │ @@ -1455108,56 +1455108,56 @@ │ │ str r4, [sp, #12] │ │ bl 270e070 │ │ ldr r1, [pc, #1908] @ 24d446c │ │ ldr r0, [fp, #24] │ │ add r1, pc, r1 │ │ ldr r2, [fp, #44] @ 0x2c │ │ b 24d2048 │ │ - ldc2l 15, cr15, [r4, #880] @ 0x370 │ │ - ldc2l 13, cr4, [r6, #100] @ 0x64 │ │ + ldc2l 0, cr0, [r5, #36] @ 0x24 │ │ + ldc2l 13, cr4, [r6, #280] @ 0x118 │ │ ldrbeq r2, [r6, #1964] @ 0x7ac │ │ - ldc2l 12, cr4, [r6, #948] @ 0x3b4 │ │ - ldc2l 12, cr4, [r6, #900] @ 0x384 │ │ + ldc2l 13, cr4, [r6, #104] @ 0x68 │ │ + ldc2l 13, cr4, [r6, #56] @ 0x38 │ │ ldrbeq r2, [r6, #1868] @ 0x74c │ │ ldrbeq r1, [r6, #2344] @ 0x928 │ │ ldrbeq r2, [r6, #1836] @ 0x72c │ │ - ldc2l 7, cr0, [r6, #300] @ 0x12c │ │ - ldc2l 1, cr9, [r5, #600] @ 0x258 │ │ + ldc2l 7, cr0, [r6, #480] @ 0x1e0 │ │ + ldc2l 1, cr9, [r5, #780] @ 0x30c │ │ ldrdeq r7, [r8], -ip @ │ │ ldc2l 15, cr3, [r4, #716] @ 0x2cc │ │ ldc2l 5, cr4, [r4, #604] @ 0x25c │ │ mlaeq r8, r8, r8, r7 │ │ ldrbeq r2, [r6, #1628] @ 0x65c │ │ ldc2l 15, cr3, [r4, #300] @ 0x12c │ │ ldc2l 5, cr4, [r4, #188] @ 0xbc │ │ eoreq r7, r8, r0, lsr r8 │ │ ldrbeq r2, [r6, #1532] @ 0x5fc │ │ ldrbeq r2, [r6, #1468] @ 0x5bc │ │ ldrbeq r2, [r6, #1440] @ 0x5a0 │ │ ldrbeq r0, [r6, #2348] @ 0x92c │ │ - ldc2l 0, cr9, [r5, #788] @ 0x314 │ │ + ldc2l 0, cr9, [r5, #968] @ 0x3c8 │ │ ldrbeq r2, [r6, #1364] @ 0x554 │ │ ldc2l 4, cr1, [r7, #784] @ 0x310 │ │ ldrbeq r2, [r6, #1344] @ 0x540 │ │ - ldc2l 0, cr9, [r5, #116] @ 0x74 │ │ + ldc2l 0, cr9, [r5, #296] @ 0x128 │ │ ldrbeq r0, [r6, #2172] @ 0x87c │ │ ldc2l 4, cr1, [r7, #128] @ 0x80 │ │ ldrbeq r2, [r6, #1184] @ 0x4a0 │ │ ldrbeq r0, [r6, #2120] @ 0x848 │ │ ldrbeq r2, [r6, #1148] @ 0x47c │ │ ldc2l 3, cr1, [r7, #896] @ 0x380 │ │ ldrbeq r0, [r6, #2044] @ 0x7fc │ │ ldrbeq r1, [r6, #1584] @ 0x630 │ │ - ldc2l 3, cr14, [r4, #448] @ 0x1c0 │ │ + ldc2l 3, cr14, [r4, #628] @ 0x274 │ │ ldrbeq r1, [r6, #1520] @ 0x5f0 │ │ - ldc2l 6, cr8, [r5, #384] @ 0x180 │ │ + ldc2l 6, cr8, [r5, #564] @ 0x234 │ │ ldc2l 9, cr6, [r6, #502] @ 0x1f6 @ │ │ ldrbeq r2, [r6, #992] @ 0x3e0 │ │ - ldc2l 4, cr14, [r4, #600] @ 0x258 │ │ - ldc2l 13, cr15, [r4, #452] @ 0x1c4 │ │ + ldc2l 4, cr14, [r4, #780] @ 0x30c │ │ + ldc2l 13, cr15, [r4, #632] @ 0x278 │ │ ldrbeq r0, [r6, #1836] @ 0x72c │ │ ldrbeq r1, [r6, #1368] @ 0x558 │ │ ldc2l 12, cr3, [r4, #492] @ 0x1ec │ │ ldrbeq r2, [r6, #668] @ 0x29c │ │ ldrbeq r2, [r6, #656] @ 0x290 │ │ ldrbeq r0, [r6, #1584] @ 0x630 │ │ ldr r0, [pc, #1700] @ 24d4470 │ │ @@ -1455479,180 +1455479,180 @@ │ │ str r5, [sp] │ │ add r1, pc, r1 │ │ b 24d2398 │ │ ldrbeq r2, [r6, #612] @ 0x264 │ │ ldrbeq r2, [r6, #592] @ 0x250 │ │ ldrbeq r2, [r6, #592] @ 0x250 │ │ ldc2l 13, cr6, [r4, #880] @ 0x370 │ │ - ldc2l 7, cr4, [r6, #644] @ 0x284 │ │ + ldc2l 7, cr4, [r6, #824] @ 0x338 │ │ ldrbeq r0, [r6, #1464] @ 0x5b8 │ │ ldrbeq r2, [r6, #504] @ 0x1f8 │ │ - ldc2l 7, cr15, [r4, #416] @ 0x1a0 │ │ - ldc2l 4, cr4, [r6, #660] @ 0x294 │ │ + ldc2l 7, cr15, [r4, #596] @ 0x254 │ │ + ldc2l 4, cr4, [r6, #840] @ 0x348 │ │ ldrbeq r1, [r6, #3892] @ 0xf34 │ │ - ldc2l 4, cr4, [r6, #452] @ 0x1c4 │ │ - ldc2l 4, cr4, [r6, #404] @ 0x194 │ │ + ldc2l 4, cr4, [r6, #632] @ 0x278 │ │ + ldc2l 4, cr4, [r6, #584] @ 0x248 │ │ ldrbeq r1, [r6, #3784] @ 0xec8 │ │ ldrbeq r1, [r6, #168] @ 0xa8 │ │ ldrbeq r0, [r6, #648] @ 0x288 │ │ ldrbeq r1, [r6, #3752] @ 0xea8 │ │ - ldc2l 14, cr15, [r5, #828] @ 0x33c │ │ - ldc2l 9, cr8, [r5, #44] @ 0x2c @ │ │ + ldc2l 14, cr15, [r5, #1008] @ 0x3f0 │ │ + ldc2l 9, cr8, [r5, #134] @ 0x86 @ │ │ eoreq r7, r8, ip, asr r0 │ │ ldc2l 7, cr3, [r4, #204] @ 0xcc │ │ ldc2l 13, cr3, [r4, #92] @ 0x5c │ │ eoreq r7, r8, r4, lsl r0 │ │ ldrbeq r1, [r6, #3552] @ 0xde0 │ │ ldc2l 6, cr3, [r4, #876] @ 0x36c │ │ ldrbeq r0, [r6, #1404] @ 0x57c │ │ - ldc2l 11, cr14, [r4, #992] @ 0x3e0 @ │ │ + ldc2l 12, cr14, [r4, #148] @ 0x94 │ │ ldrbeq r0, [r6, #1356] @ 0x54c │ │ ldrbeq r0, [r6, #1356] @ 0x54c │ │ - ldc2l 11, cr1, [r5, #864] @ 0x360 @ │ │ + ldc2l 12, cr1, [r5, #20] │ │ ldrbeq r0, [r6, #1316] @ 0x524 │ │ ldrbeq r0, [r6, #1316] @ 0x524 │ │ - ldc2l 5, cr2, [r6, #228] @ 0xe4 │ │ + ldc2l 5, cr2, [r6, #408] @ 0x198 │ │ ldrbeq r0, [r6, #1276] @ 0x4fc │ │ ldrbeq r0, [r6, #1276] @ 0x4fc │ │ ldc2l 4, cr5, [r7, #808] @ 0x328 │ │ ldrbeq r0, [r6, #1236] @ 0x4d4 │ │ ldrbeq r0, [r6, #1236] @ 0x4d4 │ │ vcadd.f32 q10, , , #270 │ │ ldrbeq r0, [r6, #1196] @ 0x4ac │ │ ldrbeq r0, [r6, #1196] @ 0x4ac │ │ ldrbeq r0, [r6, #1176] @ 0x498 │ │ ldc2l 9, cr3, [r4, #494] @ 0x1ee @ │ │ - ldc2l 15, cr13, [r4, #864] @ 0x360 │ │ + ldc2l 0, cr14, [r4, #20] │ │ ldrbeq r0, [r6, #1064] @ 0x428 │ │ - ldc2l 2, cr8, [r5, #800] @ 0x320 │ │ + ldc2l 2, cr8, [r5, #980] @ 0x3d4 │ │ ldrbeq r0, [r6, #1008] @ 0x3f0 │ │ - ldc2l 6, cr12, [r5, #800] @ 0x320 │ │ + ldc2l 6, cr12, [r5, #980] @ 0x3d4 │ │ ldrbeq r2, [r6, #68] @ 0x44 │ │ - ldc2l 0, cr14, [r4, #1000] @ 0x3e8 │ │ + ldc2l 1, cr14, [r4, #156] @ 0x9c │ │ ldrbeq r0, [r6, #928] @ 0x3a0 │ │ ldrbeq r0, [r6, #920] @ 0x398 │ │ - ldc2l 9, cr15, [r4, #378] @ 0x17a @ │ │ - ldc2l 15, cr3, [r5, #476] @ 0x1dc │ │ + ldc2l 9, cr15, [r4, #468] @ 0x1d4 @ │ │ + ldc2l 15, cr3, [r5, #656] @ 0x290 │ │ ldrbeq r0, [r6, #224] @ 0xe0 │ │ ldrbeq r0, [r6, #224] @ 0xe0 │ │ ldc2l 4, cr5, [r6, #384] @ 0x180 │ │ ldrbeq r0, [r6, #176] @ 0xb0 │ │ ldrbeq r0, [r6, #176] @ 0xb0 │ │ - ldc2l 5, cr0, [r6, #44] @ 0x2c │ │ + ldc2l 5, cr0, [r6, #224] @ 0xe0 │ │ ldrbeq r0, [r6, #136] @ 0x88 │ │ ldrbeq r0, [r6, #136] @ 0x88 │ │ - ldc2l 5, cr11, [r5, #688] @ 0x2b0 │ │ + ldc2l 5, cr11, [r5, #868] @ 0x364 │ │ ldrbeq r0, [r6, #96] @ 0x60 │ │ ldrbeq r0, [r6, #96] @ 0x60 │ │ ldc2l 0, cr8, [r7, #1016] @ 0x3f8 │ │ ldrbeq r0, [r6, #56] @ 0x38 │ │ ldrbeq r0, [r6, #56] @ 0x38 │ │ ldrbeq r0, [r6, #40] @ 0x28 │ │ ldc2l 5, cr3, [r4, #540] @ 0x21c │ │ - ldc2l 11, cr13, [r4, #416] @ 0x1a0 @ │ │ + ldc2l 11, cr13, [r4, #596] @ 0x254 @ │ │ ldrbeq pc, [r5, #4024] @ 0xfb8 @ │ │ - ldc2l 14, cr7, [r5, #352] @ 0x160 │ │ + ldc2l 14, cr7, [r5, #532] @ 0x214 │ │ ldrbeq pc, [r5, #3968] @ 0xf80 @ │ │ - ldc2l 1, cr4, [r6, #700] @ 0x2bc │ │ + ldc2l 1, cr4, [r6, #880] @ 0x370 │ │ ldrbeq r1, [r6, #3028] @ 0xbd4 │ │ - ldc2l 12, cr13, [r4, #552] @ 0x228 │ │ + ldc2l 12, cr13, [r4, #732] @ 0x2dc │ │ ldrbeq pc, [r5, #3888] @ 0xf30 @ │ │ ldrbeq pc, [r5, #3880] @ 0xf28 @ │ │ - ldc2l 5, cr15, [r4, #308] @ 0x134 │ │ - ldc2l 11, cr14, [r4, #88] @ 0x58 @ │ │ + ldc2l 5, cr15, [r4, #488] @ 0x1e8 │ │ + ldc2l 11, cr14, [r4, #268] @ 0x10c @ │ │ vcadd.f32 q8, , q9, #270 │ │ ldc2l 3, cr3, [r4, #684] @ 0x2ac │ │ - ldc2l 10, cr14, [r4, #584] @ 0x248 @ │ │ + ldc2l 10, cr14, [r4, #764] @ 0x2fc @ │ │ ldrbeq pc, [r5, #3564] @ 0xdec @ │ │ ldrbeq pc, [r5, #3568] @ 0xdf0 @ │ │ ldc2l 8, cr0, [r7, #376] @ 0x178 │ │ ldrbeq r1, [r6, #2588] @ 0xa1c │ │ ldrbeq pc, [r5, #3520] @ 0xdc0 @ │ │ ldrbeq pc, [r5, #3524] @ 0xdc4 @ │ │ ldrbeq pc, [r5, #3484] @ 0xd9c @ │ │ ldrbeq pc, [r5, #3480] @ 0xd98 @ │ │ ldrbeq pc, [r5, #3464] @ 0xd88 @ │ │ ldrbeq pc, [r5, #3460] @ 0xd84 @ │ │ - vcadd.f32 , q10, q12, #270 │ │ - ldc2l 11, cr7, [r5, #912] @ 0x390 @ │ │ + ldc2l 9, cr13, [r4, #42] @ 0x2a @ │ │ + ldc2l 12, cr7, [r5, #68] @ 0x44 │ │ ldrbeq pc, [r5, #3344] @ 0xd10 @ │ │ ldrbeq pc, [r5, #3340] @ 0xd0c @ │ │ ldrbeq pc, [r5, #3324] @ 0xcfc @ │ │ ldrbeq pc, [r5, #3320] @ 0xcf8 @ │ │ ldc2l 14, cr12, [r7, #352] @ 0x160 │ │ ldrbeq r1, [r6, #2288] @ 0x8f0 │ │ - ldc2l 9, cr13, [r4, #332] @ 0x14c @ │ │ + ldc2l 9, cr13, [r4, #422] @ 0x1a6 @ │ │ ldrbeq pc, [r5, #3164] @ 0xc5c @ │ │ ldrbeq pc, [r5, #3160] @ 0xc58 @ │ │ - ldc2l 2, cr15, [r4, #420] @ 0x1a4 │ │ + ldc2l 2, cr15, [r4, #600] @ 0x258 │ │ ldrbeq pc, [r5, #3100] @ 0xc1c @ │ │ ldrbeq pc, [r5, #3092] @ 0xc14 @ │ │ ldc2l 1, cr3, [r4, #332] @ 0x14c │ │ ldc2l 10, cr13, [r6, #336] @ 0x150 @ │ │ ldc2l 2, cr6, [r4, #968] @ 0x3c8 │ │ ldrbeq r1, [r6, #1860] @ 0x744 │ │ - ldc2l 1, cr14, [r4, #444] @ 0x1bc │ │ + ldc2l 1, cr14, [r4, #624] @ 0x270 │ │ ldc2l 2, cr6, [r4, #792] @ 0x318 │ │ ldrbeq r1, [r6, #1816] @ 0x718 │ │ ldc2l 3, cr9, [r7, #184] @ 0xb8 │ │ - ldc2l 1, cr12, [r4, #164] @ 0xa4 │ │ + ldc2l 1, cr12, [r4, #344] @ 0x158 │ │ ldrbeq r1, [r6, #1768] @ 0x6e8 │ │ - ldc2l 12, cr9, [r5, #40] @ 0x28 │ │ - ldc2l 0, cr12, [r4, #1012] @ 0x3f4 │ │ + ldc2l 12, cr9, [r5, #220] @ 0xdc │ │ + ldc2l 1, cr12, [r4, #168] @ 0xa8 │ │ ldrbeq r1, [r6, #1724] @ 0x6bc │ │ ldc2l 5, cr15, [r6, #608] @ 0x260 │ │ ldc2l 2, cr5, [r7, #40] @ 0x28 │ │ ldrbeq r1, [r6, #1676] @ 0x68c │ │ ldc2l 15, cr1, [r4, #412] @ 0x19c │ │ ldc2l 1, cr5, [r7, #888] @ 0x378 │ │ ldrbeq r1, [r6, #1632] @ 0x660 │ │ - ldc2l 3, cr15, [r5, #112] @ 0x70 │ │ - ldc2l 13, cr11, [r5, #56] @ 0x38 │ │ + ldc2l 3, cr15, [r5, #292] @ 0x124 │ │ + ldc2l 13, cr11, [r5, #236] @ 0xec │ │ ldc2l 13, cr10, [r7, #152] @ 0x98 │ │ ldrbeq r1, [r6, #1580] @ 0x62c │ │ ldrbeq r1, [r6, #1572] @ 0x624 │ │ ldc2l 3, cr4, [r4, #868] @ 0x364 │ │ - ldc2l 9, cr13, [r5, #330] @ 0x14a @ │ │ + ldc2l 9, cr13, [r5, #420] @ 0x1a4 @ │ │ ldrbeq r1, [r6, #1512] @ 0x5e8 │ │ ldc2l 12, cr5, [r6, #212] @ 0xd4 │ │ ldc2l 8, cr3, [r7, #108] @ 0x6c │ │ ldrbeq r1, [r6, #1464] @ 0x5b8 │ │ ldc2l 1, cr6, [r4, #264] @ 0x108 │ │ - ldc2l 14, cr15, [r4, #780] @ 0x30c │ │ + ldc2l 14, cr15, [r4, #960] @ 0x3c0 │ │ ldrbeq r1, [r6, #1412] @ 0x584 │ │ - ldc2l 14, cr3, [r5, #508] @ 0x1fc │ │ + ldc2l 14, cr3, [r5, #688] @ 0x2b0 │ │ ldc2l 12, cr10, [r7, #328] @ 0x148 │ │ ldrbeq r1, [r6, #1364] @ 0x554 │ │ ldc2l 11, cr5, [r6, #684] @ 0x2ac @ │ │ vcadd.f32 d31, d3, d23, #270 │ │ ldrbeq r1, [r6, #1320] @ 0x528 │ │ - ldc2l 10, cr9, [r5, #336] @ 0x150 @ │ │ + ldc2l 10, cr9, [r5, #516] @ 0x204 @ │ │ ldc2l 7, cr15, [r3, #1020] @ 0x3fc │ │ ldrbeq r1, [r6, #1276] @ 0x4fc │ │ - ldc2l 12, cr7, [r4, #112] @ 0x70 │ │ - ldc2l 12, cr7, [r4, #112] @ 0x70 │ │ + ldc2l 12, cr7, [r4, #292] @ 0x124 │ │ + ldc2l 12, cr7, [r4, #292] @ 0x124 │ │ ldrbeq r1, [r6, #1232] @ 0x4d0 │ │ - ldc2l 13, cr3, [r5, #848] @ 0x350 │ │ + ldc2l 14, cr3, [r5, #4] │ │ ldc2l 3, cr15, [r6, #720] @ 0x2d0 │ │ ldrbeq r1, [r6, #1188] @ 0x4a4 │ │ ldc2l 15, cr0, [r7, #548] @ 0x224 │ │ - ldc2l 10, cr3, [r6, #684] @ 0x2ac @ │ │ + ldc2l 10, cr3, [r6, #864] @ 0x360 @ │ │ ldrbeq r1, [r6, #1144] @ 0x478 │ │ ldc2l 10, cr12, [r7, #120] @ 0x78 @ │ │ ldc2l 6, cr3, [r7, #720] @ 0x2d0 │ │ ldrbeq r1, [r6, #1100] @ 0x44c │ │ ldc2l 15, cr4, [r7, #680] @ 0x2a8 │ │ - ldc2l 13, cr5, [r5, #168] @ 0xa8 │ │ + ldc2l 13, cr5, [r5, #348] @ 0x15c │ │ ldrbeq r1, [r6, #1056] @ 0x420 │ │ - ldc2l 13, cr5, [r5, #24] │ │ + ldc2l 13, cr5, [r5, #204] @ 0xcc │ │ ldc2l 0, cr9, [r7, #256] @ 0x100 │ │ ldrbeq r1, [r6, #1012] @ 0x3f4 │ │ ldc2l 12, cr2, [r4, #748] @ 0x2ec │ │ - ldc2l 3, cr15, [r5, #892] @ 0x37c │ │ - ldc2l 14, cr7, [r5, #184] @ 0xb8 │ │ + ldc2l 4, cr15, [r5, #48] @ 0x30 │ │ + ldc2l 14, cr7, [r5, #364] @ 0x16c │ │ eoreq r6, r8, r4, ror r5 │ │ ldc2l 12, cr2, [r4, #284] @ 0x11c │ │ ldc2l 2, cr3, [r4, #172] @ 0xac │ │ eoreq r6, r8, ip, lsr #10 │ │ ldrbeq r1, [r6, #752] @ 0x2f0 │ │ ldc2l 11, cr2, [r4, #892] @ 0x37c @ │ │ ldc2l 1, cr3, [r4, #764] @ 0x2fc │ │ @@ -1456609,116 +1456609,116 @@ │ │ ldrbeq r0, [r6, #3480] @ 0xd98 │ │ ldrbeq r0, [r6, #3484] @ 0xd9c │ │ ldc2l 6, cr2, [r4, #380] @ 0x17c │ │ ldrbeq r0, [r6, #3448] @ 0xd78 │ │ ldc2l 2, cr12, [r7, #840] @ 0x348 │ │ ldrbeq r0, [r6, #3404] @ 0xd4c │ │ ldc2l 3, cr10, [r7, #856] @ 0x358 │ │ - ldc2l 6, cr13, [r4, #1012] @ 0x3f4 │ │ + ldc2l 7, cr13, [r4, #168] @ 0xa8 │ │ ldc2l 3, cr10, [r7, #536] @ 0x218 │ │ - ldc2l 5, cr15, [r4, #696] @ 0x2b8 │ │ - ldc2l 6, cr14, [r4, #164] @ 0xa4 │ │ - ldc2l 5, cr1, [r5, #940] @ 0x3ac │ │ - ldc2l 5, cr14, [r4, #740] @ 0x2e4 │ │ + ldc2l 5, cr15, [r4, #876] @ 0x36c │ │ + ldc2l 6, cr14, [r4, #344] @ 0x158 │ │ + ldc2l 6, cr1, [r5, #96] @ 0x60 │ │ + ldc2l 5, cr14, [r4, #920] @ 0x398 │ │ eoreq r5, r8, r8, lsl #30 │ │ - ldc2l 5, cr13, [r4, #964] @ 0x3c4 │ │ + ldc2l 6, cr13, [r4, #120] @ 0x78 │ │ ldrbeq r0, [r6, #2764] @ 0xacc │ │ ldrbeq r0, [r6, #2968] @ 0xb98 │ │ ldrbeq r0, [r6, #2748] @ 0xabc │ │ ldrbeq r0, [r6, #2692] @ 0xa84 │ │ ldrbeq r0, [r6, #2952] @ 0xb88 │ │ ldrbeq r0, [r6, #2936] @ 0xb78 │ │ - ldc2l 9, cr14, [r5, #140] @ 0x8c @ │ │ - ldc2l 2, cr14, [r4, #484] @ 0x1e4 │ │ + ldc2l 9, cr14, [r5, #230] @ 0xe6 @ │ │ + ldc2l 2, cr14, [r4, #664] @ 0x298 │ │ eoreq r5, r8, r4, asr #23 │ │ ldrbeq r0, [r6, #2200] @ 0x898 │ │ ldrbeq r0, [r6, #2224] @ 0x8b0 │ │ ldc2l 2, cr10, [r7, #472] @ 0x1d8 │ │ ldrbeq r0, [r6, #2984] @ 0xba8 │ │ ldrbeq r0, [r6, #3192] @ 0xc78 │ │ ldrbeq r0, [r6, #2924] @ 0xb6c │ │ ldrbeq r0, [r6, #3176] @ 0xc68 │ │ ldrbeq r0, [r6, #2964] @ 0xb94 │ │ ldrbeq r0, [r6, #3160] @ 0xc58 │ │ - ldc2l 2, cr7, [r4, #160] @ 0xa0 │ │ - ldc2l 4, cr14, [r4, #580] @ 0x244 │ │ + ldc2l 2, cr7, [r4, #340] @ 0x154 │ │ + ldc2l 4, cr14, [r4, #760] @ 0x2f8 │ │ eoreq r5, r8, r0, ror #27 │ │ ldc2l 10, cr10, [r6, #1004] @ 0x3ec @ │ │ - ldc2l 0, cr14, [r4, #340] @ 0x154 │ │ + ldc2l 0, cr14, [r4, #520] @ 0x208 │ │ ldrbeq r0, [r6, #1740] @ 0x6cc │ │ eoreq r5, r8, r8, asr #19 │ │ ldc2l 10, cr12, [r6, #480] @ 0x1e0 @ │ │ ldc2l 13, cr11, [r7, #852] @ 0x354 │ │ - ldc2l 14, cr12, [r4, #700] @ 0x2bc │ │ + ldc2l 14, cr12, [r4, #880] @ 0x370 │ │ ldrbeq r0, [r6, #1172] @ 0x494 │ │ ldc2l 13, cr0, [r4, #124] @ 0x7c │ │ ldc2l 10, cr11, [r7, #548] @ 0x224 @ │ │ - ldc2l 13, cr13, [r4, #868] @ 0x364 │ │ + ldc2l 14, cr13, [r4, #24] │ │ mlaeq r8, r0, r6, r5 │ │ strdeq r5, [r8], -r8 @ │ │ ldrbeq r0, [r6, #1036] @ 0x40c │ │ ldc2l 12, cr0, [r4, #588] @ 0x24c │ │ ldc2l 9, cr11, [r7, #506] @ 0x1fa @ │ │ - ldc2l 13, cr13, [r4, #308] @ 0x134 │ │ + ldc2l 13, cr13, [r4, #488] @ 0x1e8 │ │ eoreq r5, r8, r0, lsl #12 │ │ ldrbeq r0, [r6, #940] @ 0x3ac │ │ ldc2l 6, cr12, [r6, #272] @ 0x110 │ │ ldc2l 9, cr11, [r7, #322] @ 0x142 @ │ │ - ldc2l 12, cr13, [r4, #916] @ 0x394 │ │ + ldc2l 13, cr13, [r4, #72] @ 0x48 │ │ eoreq r5, r8, r8, lsr r6 │ │ ldrbeq r0, [r6, #1892] @ 0x764 │ │ ldrbeq r0, [r6, #1920] @ 0x780 │ │ ldc2l 4, cr12, [r6, #480] @ 0x1e0 │ │ ldc2l 7, cr11, [r7, #852] @ 0x354 │ │ ldrbeq r0, [r6, #388] @ 0x184 │ │ ldrbeq r0, [r6, #2612] @ 0xa34 │ │ ldrbeq r0, [r6, #2428] @ 0x97c │ │ - ldc2l 2, cr14, [r4, #804] @ 0x324 │ │ + ldc2l 2, cr14, [r4, #984] @ 0x3d8 │ │ eoreq r5, r8, r0, lsr #24 │ │ ldrbeq r0, [r6, #2324] @ 0x914 │ │ ldrbeq r0, [r6, #2816] @ 0xb00 │ │ ldc2l 11, cr14, [r3, #76] @ 0x4c @ │ │ - ldc2l 1, cr14, [r4, #804] @ 0x324 │ │ + ldc2l 1, cr14, [r4, #984] @ 0x3d8 │ │ eoreq r5, r8, r0, lsr #22 │ │ ldrbeq r0, [r6, #2324] @ 0x914 │ │ ldrbeq r0, [r6, #2560] @ 0xa00 │ │ - ldc2l 1, cr13, [r4, #184] @ 0xb8 │ │ + ldc2l 1, cr13, [r4, #364] @ 0x16c │ │ ldrbeq r0, [r6, #1828] @ 0x724 │ │ ldrbeq r0, [r6, #1012] @ 0x3f4 │ │ ldrbeq r0, [r6, #724] @ 0x2d4 │ │ ldrbeq r0, [r6, #964] @ 0x3c4 │ │ ldrbeq r0, [r6, #720] @ 0x2d0 │ │ ldrbeq r0, [r6, #648] @ 0x288 │ │ ldrbeq r0, [r6, #632] @ 0x278 │ │ ldrbeq r0, [r6, #856] @ 0x358 │ │ ldrbeq r0, [r6, #612] @ 0x264 │ │ ldrbeq r0, [r6, #540] @ 0x21c │ │ ldc2l 5, cr14, [r3, #300] @ 0x12c │ │ - ldc2l 11, cr13, [r4, #564] @ 0x234 @ │ │ + ldc2l 11, cr13, [r4, #744] @ 0x2e8 @ │ │ ldrdeq r5, [r8], -ip @ │ │ ldrbeq r0, [r6, #520] @ 0x208 │ │ ldrbeq r0, [r6, #2444] @ 0x98c │ │ ldrbeq r0, [r6, #2460] @ 0x99c │ │ ldrbeq r0, [r6, #2704] @ 0xa90 │ │ ldrbeq r0, [r6, #1680] @ 0x690 │ │ ldrbeq r0, [r6, #1608] @ 0x648 │ │ ldrbeq r0, [r6, #1588] @ 0x634 │ │ ldrbeq r0, [r6, #1608] @ 0x648 │ │ ldrbeq r0, [r6, #1552] @ 0x610 │ │ ldc2l 1, cr6, [r7, #864] @ 0x360 │ │ ldrbeq r0, [r6, #1480] @ 0x5c8 │ │ ldrbeq r0, [r6, #1416] @ 0x588 │ │ - ldc2l 12, cr10, [r5, #144] @ 0x90 │ │ + ldc2l 12, cr10, [r5, #324] @ 0x144 │ │ ldc2l 11, cr11, [r7, #724] @ 0x2d4 @ │ │ - ldc2l 15, cr13, [r4, #20] │ │ + ldc2l 15, cr13, [r4, #200] @ 0xc8 │ │ eoreq r5, r8, r4, lsr r8 │ │ ldrbeq r0, [r6, #1336] @ 0x538 │ │ - ldc2l 11, cr10, [r5, #752] @ 0x2f0 @ │ │ + ldc2l 11, cr10, [r5, #932] @ 0x3a4 @ │ │ ldc2l 11, cr11, [r7, #308] @ 0x134 @ │ │ - ldc2l 14, cr13, [r4, #628] @ 0x274 │ │ + ldc2l 14, cr13, [r4, #808] @ 0x328 │ │ ldrdeq r5, [r8], -r4 @ │ │ ldrbeq r0, [r6, #1232] @ 0x4d0 │ │ ldrbeq r0, [r6, #1664] @ 0x680 │ │ ldc2l 2, cr2, [r4, #380] @ 0x17c │ │ ldc2l 11, cr13, [r3, #280] @ 0x118 @ │ │ ldrbeq r0, [r6, #3848] @ 0xf08 │ │ ldc2l 12, cr5, [r6, #740] @ 0x2e4 │ │ @@ -1456994,15 +1456994,15 @@ │ │ ldr r1, [r4] │ │ add r0, r1, r0 │ │ str r0, [r4] │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ ldc2l 6, cr3, [r7, #920] @ 0x398 │ │ ldc2l 1, cr11, [r7, #804] @ 0x324 │ │ - ldc2l 11, cr7, [r4, #272] @ 0x110 @ │ │ + ldc2l 11, cr7, [r4, #452] @ 0x1c4 @ │ │ │ │ 024d5a30 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #60 @ 0x3c │ │ mov r4, r3 │ │ mov r5, r2 │ │ @@ -1458023,15 +1458023,15 @@ │ │ mov r2, #4 │ │ ldr r0, [pc, #3864] @ 24d7940 │ │ ldr r8, [sp, #40] @ 0x28 │ │ ldr r5, [fp, #-40] @ 0xffffffd8 │ │ add r0, pc, r0 │ │ str r2, [r0] │ │ b 24d6b7c │ │ - ldc2l 5, cr12, [r4, #512] @ 0x200 │ │ + ldc2l 5, cr12, [r4, #692] @ 0x2b4 │ │ ldrbeq pc, [r5, #3048] @ 0xbe8 @ │ │ ldrbeq r0, [r6, #1108] @ 0x454 │ │ ldrbeq r0, [r6, #1088] @ 0x440 │ │ ldr r0, [pc, #3804] @ 24d792c │ │ mov r2, #3 │ │ add r0, pc, r0 │ │ str r2, [r0] │ │ @@ -1458067,15 +1458067,15 @@ │ │ ldrbeq pc, [r5, #2932] @ 0xb74 @ │ │ ldrbeq pc, [r5, #2909] @ 0xb5d @ │ │ ldc2l 3, cr1, [r4, #188] @ 0xbc │ │ ldrbeq r0, [r6, #672] @ 0x2a0 │ │ ldrbeq r0, [r6, #640] @ 0x280 │ │ ldrbeq r0, [r6, #984] @ 0x3d8 │ │ ldrbeq pc, [r5, #3428] @ 0xd64 @ │ │ - ldc2l 2, cr4, [r5, #520] @ 0x208 │ │ + ldc2l 2, cr4, [r5, #700] @ 0x2bc │ │ ldc2l 1, cr14, [r6, #936] @ 0x3a8 │ │ ldc2l 2, cr1, [r4, #492] @ 0x1ec │ │ ldr r1, [pc, #4076] @ 24d7ae8 │ │ mov r2, r4 │ │ add r1, pc, r1 │ │ str r0, [r1] │ │ ldr r1, [sp, #32] │ │ @@ -1458151,25 +1458151,25 @@ │ │ ldrbeq r0, [r6, #592] @ 0x250 │ │ ldrbeq r0, [r6, #224] @ 0xe0 │ │ ldrbeq pc, [r5, #2548] @ 0x9f4 @ │ │ ldrbeq pc, [r5, #3200] @ 0xc80 @ │ │ ldrbeq pc, [r5, #2516] @ 0x9d4 @ │ │ ldrbeq pc, [r5, #3172] @ 0xc64 @ │ │ ldrbeq r0, [r6, #460] @ 0x1cc │ │ - vcadd.f32 d29, d21, d24, #270 │ │ - ldc2l 6, cr11, [r4, #980] @ 0x3d4 │ │ + ldc2l 8, cr13, [r5, #852] @ 0x354 │ │ + ldc2l 7, cr11, [r4, #136] @ 0x88 │ │ eoreq r4, r8, r8, ror #21 │ │ - ldc2l 5, cr5, [r5, #736] @ 0x2e0 │ │ + ldc2l 5, cr5, [r5, #916] @ 0x394 │ │ ldrbeq r0, [r6, #392] @ 0x188 │ │ - ldc2l 5, cr11, [r5, #592] @ 0x250 │ │ + ldc2l 5, cr11, [r5, #772] @ 0x304 │ │ strhteq r4, [r8], -ip │ │ ldrbeq pc, [r5, #2364] @ 0x93c @ │ │ ldrbeq pc, [r5, #3012] @ 0xbc4 @ │ │ ldc2l 10, cr5, [r6, #624] @ 0x270 @ │ │ - ldc2l 8, cr5, [r4, #484] @ 0x1e4 │ │ + vcadd.f32 d21, d20, d22, #270 │ │ ldrbeq pc, [r5, #2296] @ 0x8f8 @ │ │ ldrbeq pc, [r5, #2944] @ 0xb80 @ │ │ ldr r0, [pc, #3300] @ 24d7958 │ │ mov r2, r6 │ │ movw r3, #949 @ 0x3b5 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ @@ -1458698,16 +1458698,16 @@ │ │ mov r1, r4 │ │ mov r2, #1 │ │ bl 270db00 │ │ ldr r0, [pc, #1560] @ 24d7ad4 │ │ add r0, pc, r0 │ │ b 24d7408 │ │ ldc2l 11, cr14, [r6, #344] @ 0x158 @ │ │ - ldc2l 9, cr3, [r5, #188] @ 0xbc @ │ │ - ldc2l 9, cr3, [r5, #140] @ 0x8c @ │ │ + ldc2l 9, cr3, [r5, #278] @ 0x116 @ │ │ + ldc2l 9, cr3, [r5, #230] @ 0xe6 @ │ │ ldrbeq pc, [r5, #2268] @ 0x8dc @ │ │ ldrbeq pc, [r5, #2248] @ 0x8c8 @ │ │ ldrbeq pc, [r5, #2216] @ 0x8a8 @ │ │ ldrbeq pc, [r5, #2172] @ 0x87c @ │ │ ldrbeq pc, [r5, #2148] @ 0x864 @ │ │ ldrbeq pc, [r5, #396] @ 0x18c @ │ │ ldrbeq pc, [r5, #1036] @ 0x40c @ │ │ @@ -1458960,24 +1458960,24 @@ │ │ ldrbeq pc, [r5, #56] @ 0x38 @ │ │ ldrbeq pc, [r5, #1564] @ 0x61c @ │ │ ldrbeq pc, [r5, #708] @ 0x2c4 @ │ │ ldrbeq pc, [r5, #1248] @ 0x4e0 @ │ │ ldc2l 1, cr4, [r6, #448] @ 0x1c0 │ │ ldrbeq lr, [r5, #232] @ 0xe8 │ │ ldrbeq lr, [r5, #1700] @ 0x6a4 │ │ - ldc2l 6, cr11, [r4, #772] @ 0x304 │ │ + ldc2l 6, cr11, [r4, #952] @ 0x3b8 │ │ ldrbeq lr, [r5, #1660] @ 0x67c │ │ ldrbeq lr, [r5, #1884] @ 0x75c │ │ - ldc2l 6, cr2, [r5, #680] @ 0x2a8 │ │ - ldc2l 7, cr11, [r4, #340] @ 0x154 │ │ + ldc2l 6, cr2, [r5, #860] @ 0x35c │ │ + ldc2l 7, cr11, [r4, #520] @ 0x208 │ │ ldrbeq lr, [r5, #1824] @ 0x720 │ │ - ldc2l 0, cr10, [r5, #864] @ 0x360 │ │ + ldc2l 1, cr10, [r5, #20] │ │ ldc2l 12, cr11, [r6, #112] @ 0x70 │ │ ldc2l 0, cr12, [r3, #592] @ 0x250 │ │ - ldc2l 6, cr11, [r4, #292] @ 0x124 │ │ + ldc2l 6, cr11, [r4, #472] @ 0x1d8 │ │ ldrbeq pc, [r5, #1552] @ 0x610 @ │ │ ldrbeq pc, [r5, #1552] @ 0x610 @ │ │ ldrbeq pc, [r5, #1468] @ 0x5bc @ │ │ ldrbeq lr, [r5, #3240] @ 0xca8 │ │ ldrbeq pc, [r5, #452] @ 0x1c4 @ │ │ ldrbeq lr, [r5, #3348] @ 0xd14 │ │ ldrbeq pc, [r5, #564] @ 0x234 @ │ │ @@ -1459007,115 +1459007,115 @@ │ │ ldrbeq lr, [r5, #3716] @ 0xe84 │ │ ldrbeq pc, [r5, #500] @ 0x1f4 @ │ │ ldrbeq pc, [r5, #492] @ 0x1ec @ │ │ ldrbeq lr, [r5, #3640] @ 0xe38 │ │ ldrbeq lr, [r5, #3296] @ 0xce0 │ │ ldrbeq lr, [r5, #3252] @ 0xcb4 │ │ ldrbeq lr, [r5, #3176] @ 0xc68 │ │ - ldc2l 9, cr8, [r5, #284] @ 0x11c @ │ │ - ldc2l 11, cr11, [r4, #900] @ 0x384 @ │ │ + ldc2l 9, cr8, [r5, #374] @ 0x176 @ │ │ + ldc2l 12, cr11, [r4, #56] @ 0x38 │ │ ldrbeq lr, [r5, #2996] @ 0xbb4 │ │ ldc2l 14, cr5, [r6, #404] @ 0x194 │ │ ldrbeq lr, [r5, #3888] @ 0xf30 │ │ ldrbeq lr, [r5, #2940] @ 0xb7c │ │ ldrbeq lr, [r5, #3820] @ 0xeec │ │ ldrbeq lr, [r5, #3812] @ 0xee4 │ │ ldrbeq lr, [r5, #2864] @ 0xb30 │ │ ldrbeq lr, [r5, #3164] @ 0xc5c │ │ ldrbeq lr, [r5, #3120] @ 0xc30 │ │ ldrbeq lr, [r5, #3044] @ 0xbe4 │ │ - ldc2l 11, cr2, [r5, #1004] @ 0x3ec @ │ │ + ldc2l 12, cr2, [r5, #160] @ 0xa0 │ │ ldrbeq lr, [r5, #2184] @ 0x888 │ │ ldrbeq lr, [r5, #2140] @ 0x85c │ │ ldc2l 2, cr4, [r6, #696] @ 0x2b8 │ │ - ldc2l 8, cr11, [r4, #212] @ 0xd4 │ │ - ldc2l 5, cr2, [r5, #636] @ 0x27c │ │ + vcadd.f32 , q2, q9, #270 │ │ + ldc2l 5, cr2, [r5, #816] @ 0x330 │ │ ldrbeq pc, [r5, #52] @ 0x34 @ │ │ ldrbeq pc, [r5, #44] @ 0x2c @ │ │ ldrbeq lr, [r5, #2992] @ 0xbb0 │ │ ldrbeq lr, [r5, #2948] @ 0xb84 │ │ ldc2l 13, cr5, [r7, #864] @ 0x360 │ │ - ldc2l 11, cr11, [r4, #372] @ 0x174 @ │ │ + ldc2l 11, cr11, [r4, #552] @ 0x228 @ │ │ ldc2l 8, cr6, [r6, #244] @ 0xf4 │ │ - ldc2l 11, cr11, [r4, #52] @ 0x34 @ │ │ - ldc2l 0, cr8, [r5, #500] @ 0x1f4 │ │ + ldc2l 11, cr11, [r4, #232] @ 0xe8 @ │ │ + ldc2l 0, cr8, [r5, #680] @ 0x2a8 │ │ ldrbeq pc, [r5, #292] @ 0x124 @ │ │ ldrbeq pc, [r5, #284] @ 0x11c @ │ │ ldrbeq pc, [r5, #108] @ 0x6c @ │ │ ldrbeq lr, [r5, #2168] @ 0x878 │ │ ldrbeq lr, [r5, #3472] @ 0xd90 │ │ ldrbeq pc, [r5, #80] @ 0x50 @ │ │ ldc2l 15, cr15, [r3, #652] @ 0x28c │ │ ldrbeq lr, [r5, #3840] @ 0xf00 │ │ ldrbeq lr, [r5, #3820] @ 0xeec │ │ ldrbeq lr, [r5, #3820] @ 0xeec │ │ ldrbeq lr, [r5, #3816] @ 0xee8 │ │ ldrbeq lr, [r5, #3804] @ 0xedc │ │ ldrbeq lr, [r5, #3776] @ 0xec0 │ │ - ldc2l 15, cr2, [r5, #120] @ 0x78 │ │ + ldc2l 15, cr2, [r5, #300] @ 0x12c │ │ ldrbeq lr, [r5, #4084] @ 0xff4 │ │ ldrbeq lr, [r5, #3724] @ 0xe8c │ │ ldrbeq lr, [r5, #3712] @ 0xe80 │ │ ldrbeq lr, [r5, #3996] @ 0xf9c │ │ ldrbeq lr, [r5, #3652] @ 0xe44 │ │ ldrbeq lr, [r5, #3612] @ 0xe1c │ │ - ldc2l 14, cr2, [r5, #440] @ 0x1b8 │ │ + ldc2l 14, cr2, [r5, #620] @ 0x26c │ │ ldc2l 13, cr12, [r6, #856] @ 0x358 │ │ ldrbeq lr, [r5, #3372] @ 0xd2c │ │ ldrbeq lr, [r5, #3700] @ 0xe74 │ │ ldrbeq lr, [r5, #3332] @ 0xd04 │ │ ldrbeq lr, [r5, #2592] @ 0xa20 │ │ ldrbeq lr, [r5, #2548] @ 0x9f4 │ │ ldrbeq lr, [r5, #2480] @ 0x9b0 │ │ ldc2l 8, cr14, [r3, #1016] @ 0x3f8 │ │ - ldc2l 9, cr11, [r4, #346] @ 0x15a @ │ │ + ldc2l 9, cr11, [r4, #436] @ 0x1b4 @ │ │ ldrbeq lr, [r5, #2148] @ 0x864 │ │ ldrbeq lr, [r5, #2392] @ 0x958 │ │ ldrbeq lr, [r5, #3608] @ 0xe18 │ │ ldrbeq lr, [r5, #3308] @ 0xcec │ │ ldc2l 13, cr15, [r3, #268] @ 0x10c │ │ ldrbeq lr, [r5, #2404] @ 0x964 │ │ ldrbeq lr, [r5, #2360] @ 0x938 │ │ ldc2l 4, cr8, [r6, #32] │ │ - ldc2l 9, cr11, [r4, #42] @ 0x2a @ │ │ + ldc2l 9, cr11, [r4, #132] @ 0x84 @ │ │ ldrbeq lr, [r5, #1996] @ 0x7cc │ │ ldrbeq lr, [r5, #1988] @ 0x7c4 │ │ - ldc2l 9, cr8, [r4, #68] @ 0x44 @ │ │ + ldc2l 9, cr8, [r4, #158] @ 0x9e @ │ │ ldrbeq lr, [r5, #3496] @ 0xda8 │ │ ldrbeq lr, [r5, #3196] @ 0xc7c │ │ ldrbeq lr, [r5, #3172] @ 0xc64 │ │ ldc2l 12, cr15, [r3, #828] @ 0x33c │ │ ldrbeq lr, [r5, #2772] @ 0xad4 │ │ ldrbeq lr, [r5, #2728] @ 0xaa8 │ │ ldc2l 0, cr12, [r6, #824] @ 0x338 │ │ - ldc2l 10, cr11, [r4, #532] @ 0x214 @ │ │ + ldc2l 10, cr11, [r4, #712] @ 0x2c8 @ │ │ ldrbeq lr, [r5, #2364] @ 0x93c │ │ ldrbeq lr, [r5, #2352] @ 0x930 │ │ - ldc2l 14, cr1, [r5, #164] @ 0xa4 │ │ + ldc2l 14, cr1, [r5, #344] @ 0x158 │ │ ldc2l 12, cr1, [r7, #804] @ 0x324 │ │ ldrbeq lr, [r5, #3408] @ 0xd50 │ │ ldrbeq lr, [r5, #3388] @ 0xd3c │ │ ldrbeq lr, [r5, #3372] @ 0xd2c │ │ ldrbeq lr, [r5, #2928] @ 0xb70 │ │ ldrbeq pc, [r5, #140] @ 0x8c @ │ │ ldrbeq pc, [r5, #976] @ 0x3d0 @ │ │ - ldc2l 2, cr3, [r5, #1000] @ 0x3e8 │ │ + ldc2l 3, cr3, [r5, #156] @ 0x9c │ │ ldrbeq pc, [r5, #664] @ 0x298 @ │ │ ldrbeq pc, [r5, #652] @ 0x28c @ │ │ ldrbeq pc, [r5, #944] @ 0x3b0 @ │ │ ldrbeq pc, [r5, #976] @ 0x3d0 @ │ │ ldrbeq pc, [r5, #964] @ 0x3c4 @ │ │ ldrbeq lr, [r5, #3388] @ 0xd3c │ │ ldrbeq lr, [r5, #1936] @ 0x790 │ │ ldrbeq lr, [r5, #2076] @ 0x81c │ │ ldrbeq lr, [r5, #2032] @ 0x7f0 │ │ ldc2l 2, cr4, [r6, #264] @ 0x108 │ │ - ldc2l 7, cr11, [r4, #772] @ 0x304 │ │ + ldc2l 7, cr11, [r4, #952] @ 0x3b8 │ │ ldrbeq lr, [r5, #25] │ │ - ldc2l 7, cr10, [r4, #416] @ 0x1a0 │ │ + ldc2l 7, cr10, [r4, #596] @ 0x254 │ │ │ │ 024d7b2c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d13} │ │ sub sp, sp, #216 @ 0xd8 │ │ @@ -1459496,23 +1459496,23 @@ │ │ ldr r3, [sp, #52] @ 0x34 │ │ mov r1, r0 │ │ b 24d800c │ │ mov r0, r2 │ │ bl 270dda0 │ │ b 24d7c80 │ │ ldc2l 1, cr14, [r3, #688] @ 0x2b0 │ │ - ldc2l 10, cr9, [r5, #56] @ 0x38 @ │ │ + ldc2l 10, cr9, [r5, #236] @ 0xec @ │ │ ldc2l 0, cr14, [r3, #544] @ 0x220 │ │ ldc2l 0, cr14, [r3, #352] @ 0x160 │ │ - ldc2l 9, cr9, [r5, #316] @ 0x13c @ │ │ - ldc2l 9, cr9, [r5, #220] @ 0xdc @ │ │ - ldc2l 8, cr9, [r5, #72] @ 0x48 │ │ + ldc2l 9, cr9, [r5, #406] @ 0x196 @ │ │ + ldc2l 9, cr9, [r5, #310] @ 0x136 @ │ │ + ldc2l 8, cr9, [r5, #252] @ 0xfc │ │ ldc2l 14, cr13, [r3, #560] @ 0x230 │ │ - ldc2l 7, cr9, [r5, #808] @ 0x328 │ │ - ldc2l 7, cr9, [r5, #568] @ 0x238 │ │ + ldc2l 7, cr9, [r5, #988] @ 0x3dc │ │ + ldc2l 7, cr9, [r5, #748] @ 0x2ec │ │ ldc2l 14, cr13, [r3, #48] @ 0x30 │ │ │ │ 024d815c : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ ldr r6, [pc, #68] @ 24d81b0 │ │ mov r5, r2 │ │ @@ -1459823,17 +1459823,17 @@ │ │ ldrbeq sp, [r5, #3500] @ 0xdac │ │ ldrbeq sp, [r5, #3380] @ 0xd34 │ │ eoreq r2, r8, r4, ror #11 │ │ ldrbeq sp, [r5, #3220] @ 0xc94 │ │ ldrbeq sp, [r5, #3148] @ 0xc4c │ │ ldrbeq sp, [r5, #3104] @ 0xc20 │ │ ldrbeq sp, [r5, #3132] @ 0xc3c │ │ - vcadd.f32 d21, d20, d26, #270 │ │ + ldc2l 8, cr5, [r4, #860] @ 0x35c │ │ eoreq r2, r8, ip, ror #9 │ │ - ldc2l 5, cr9, [r5] │ │ + ldc2l 5, cr9, [r5, #180] @ 0xb4 │ │ ldc2l 8, cr5, [r6, #588] @ 0x24c │ │ ldc2l 7, cr1, [r6, #412] @ 0x19c │ │ ldc2l 13, cr4, [r7, #316] @ 0x13c │ │ vcadd.f32 d22, d7, d6, #270 │ │ ldc2l 7, cr5, [r6, #904] @ 0x388 │ │ eoreq r2, r8, ip, ror #6 │ │ ldc2l 7, cr15, [r6, #724] @ 0x2d4 │ │ @@ -1460656,69 +1460656,69 @@ │ │ add r0, r0, #10 │ │ str r0, [r1] │ │ b 24d8bd4 │ │ ldc2l 7, cr12, [r6, #616] @ 0x268 │ │ eoreq r1, r8, ip, asr #31 │ │ eoreq r2, r8, r4, asr #3 │ │ ldrbeq sp, [r5, #1812] @ 0x714 │ │ - ldc2l 6, cr10, [r4, #100] @ 0x64 │ │ + ldc2l 6, cr10, [r4, #280] @ 0x118 │ │ ldc2l 14, cr14, [r6, #624] @ 0x270 │ │ ldc2l 14, cr14, [r6, #620] @ 0x26c │ │ - ldc2l 15, cr12, [r5, #508] @ 0x1fc │ │ + ldc2l 15, cr12, [r5, #688] @ 0x2b0 │ │ ldc2l 0, cr1, [r6, #1004] @ 0x3ec │ │ - ldc2l 4, cr10, [r4, #228] @ 0xe4 │ │ + ldc2l 4, cr10, [r4, #408] @ 0x198 │ │ eoreq r1, r8, r4, lsr #31 │ │ mlaeq r8, r4, pc, r1 @ │ │ eoreq r1, r8, ip, ror pc │ │ ldc2l 3, cr13, [r3, #732] @ 0x2dc │ │ - ldc2l 3, cr10, [r4, #516] @ 0x204 │ │ + ldc2l 3, cr10, [r4, #696] @ 0x2b8 │ │ strdeq r1, [r8], -r8 @ │ │ eoreq r1, r8, r0, ror #29 │ │ eoreq r1, r8, ip, ror lr │ │ eoreq r1, r8, r4, asr #24 │ │ ldc2l 10, cr14, [r6, #604] @ 0x25c @ │ │ ldc2l 10, cr14, [r6, #496] @ 0x1f0 @ │ │ ldc2l 10, cr14, [r6, #508] @ 0x1fc @ │ │ ldc2l 13, cr0, [r6, #948] @ 0x3b4 │ │ - ldc2l 13, cr14, [r5, #108] @ 0x6c │ │ + ldc2l 13, cr14, [r5, #288] @ 0x120 │ │ ldc2l 11, cr10, [r3, #80] @ 0x50 @ │ │ ldc2l 8, cr14, [r6, #848] @ 0x350 │ │ ldc2l 8, cr14, [r6, #860] @ 0x35c │ │ - ldc2l 0, cr10, [r4, #148] @ 0x94 │ │ - ldc2l 3, cr2, [r5, #612] @ 0x264 │ │ + ldc2l 0, cr10, [r4, #328] @ 0x148 │ │ + ldc2l 3, cr2, [r5, #792] @ 0x318 │ │ ldc2l 14, cr0, [r6, #372] @ 0x174 │ │ - ldc2l 14, cr4, [r4, #520] @ 0x208 │ │ + ldc2l 14, cr4, [r4, #700] @ 0x2bc │ │ mlaeq r8, r0, ip, r1 │ │ - ldc2l 9, cr8, [r5, #378] @ 0x17a @ │ │ + ldc2l 9, cr8, [r5, #468] @ 0x1d4 @ │ │ ldc2l 8, cr14, [r6, #208] @ 0xd0 │ │ ldc2l 8, cr14, [r6, #220] @ 0xdc │ │ - ldc2l 15, cr9, [r4, #564] @ 0x234 │ │ + ldc2l 15, cr9, [r4, #744] @ 0x2e8 │ │ ldc2l 12, cr0, [r6, #260] @ 0x104 │ │ ldc2l 7, cr14, [r6, #860] @ 0x35c │ │ eoreq r1, r8, ip, lsl #21 │ │ - ldc2l 15, cr9, [r4, #164] @ 0xa4 │ │ - ldc2l 12, cr4, [r4, #280] @ 0x118 │ │ + ldc2l 15, cr9, [r4, #344] @ 0x158 │ │ + ldc2l 12, cr4, [r4, #460] @ 0x1cc │ │ ldc2l 7, cr14, [r6, #572] @ 0x23c │ │ - ldc2l 14, cr9, [r4, #932] @ 0x3a4 │ │ - ldc2l 15, cr0, [r5, #540] @ 0x21c │ │ - ldc2l 15, cr2, [r5, #476] @ 0x1dc │ │ - ldc2l 14, cr0, [r5, #368] @ 0x170 │ │ - ldc2l 9, cr4, [r5, #152] @ 0x98 @ │ │ - ldc2l 13, cr9, [r4, #788] @ 0x314 │ │ - ldc2l 7, cr8, [r5, #916] @ 0x394 │ │ + ldc2l 15, cr9, [r4, #88] @ 0x58 │ │ + ldc2l 15, cr0, [r5, #720] @ 0x2d0 │ │ + ldc2l 15, cr2, [r5, #656] @ 0x290 │ │ + ldc2l 14, cr0, [r5, #548] @ 0x224 │ │ + ldc2l 9, cr4, [r5, #242] @ 0xf2 @ │ │ + ldc2l 13, cr9, [r4, #968] @ 0x3c8 │ │ + ldc2l 8, cr8, [r5, #72] @ 0x48 │ │ ldc2l 11, cr0, [r6, #304] @ 0x130 @ │ │ - ldc2l 14, cr9, [r4, #244] @ 0xf4 │ │ + ldc2l 14, cr9, [r4, #424] @ 0x1a8 │ │ eoreq r1, r8, ip, lsr #19 │ │ ldc2l 5, cr6, [r6, #76] @ 0x4c │ │ ldc2l 5, cr14, [r6, #636] @ 0x27c │ │ ldc2l 0, cr8, [r7, #224] @ 0xe0 │ │ ldc2l 0, cr15, [r3, #960] @ 0x3c0 │ │ ldc2l 0, cr8, [r7, #64] @ 0x40 │ │ ldc2l 3, cr5, [r7, #212] @ 0xd4 │ │ - ldc2l 9, cr4, [r4, #364] @ 0x16c @ │ │ + ldc2l 9, cr4, [r4, #454] @ 0x1c6 @ │ │ eoreq r1, r8, ip, asr #11 │ │ eoreq r1, r8, r0, lsr #15 │ │ ldc2l 4, cr12, [r6, #360] @ 0x168 │ │ │ │ 024d941c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -1461543,110 +1461543,110 @@ │ │ sub r1, fp, #52 @ 0x34 │ │ mov r0, r4 │ │ mov r2, #1 │ │ bl 270db00 │ │ mov r0, r4 │ │ mov r1, r8 │ │ b 24d9fbc │ │ - ldc2l 9, cr8, [r4, #174] @ 0xae @ │ │ + ldc2l 9, cr8, [r4, #264] @ 0x108 @ │ │ ldc2l 14, cr0, [r7, #104] @ 0x68 │ │ - ldc2l 10, cr0, [r5, #484] @ 0x1e4 @ │ │ - ldc2l 3, cr12, [r5, #316] @ 0x13c │ │ + ldc2l 10, cr0, [r5, #664] @ 0x298 @ │ │ + ldc2l 3, cr12, [r5, #496] @ 0x1f0 │ │ ldrbeq ip, [r5, #2624] @ 0xa40 │ │ - ldc2l 9, cr9, [r4, #82] @ 0x52 @ │ │ + ldc2l 9, cr9, [r4, #172] @ 0xac @ │ │ ldc2l 3, cr10, [r3, #944] @ 0x3b0 │ │ - vcadd.f32 , q10, , #270 │ │ + vcadd.f32 , q10, q15, #270 │ │ ldc2l 4, cr11, [r6, #452] @ 0x1c4 │ │ - ldc2l 2, cr4, [r5, #672] @ 0x2a0 │ │ - ldc2l 6, cr9, [r4, #772] @ 0x304 │ │ - ldc2l 6, cr10, [r4, #304] @ 0x130 │ │ + ldc2l 2, cr4, [r5, #852] @ 0x354 │ │ + ldc2l 6, cr9, [r4, #952] @ 0x3b8 │ │ + ldc2l 6, cr10, [r4, #484] @ 0x1e4 │ │ eoreq r1, r8, ip, asr #19 │ │ - vcadd.f32 d16, d5, d21, #270 │ │ + ldc2l 8, cr0, [r5, #328] @ 0x148 │ │ eoreq r1, r8, r4, ror #2 │ │ eoreq r1, r8, r8, asr r4 │ │ - ldc2l 5, cr9, [r4, #564] @ 0x234 │ │ - ldc2l 9, cr1, [r5, #50] @ 0x32 @ │ │ - ldc2l 7, cr0, [r5, #516] @ 0x204 │ │ + ldc2l 5, cr9, [r4, #744] @ 0x2e8 │ │ + ldc2l 9, cr1, [r5, #140] @ 0x8c @ │ │ + ldc2l 7, cr0, [r5, #696] @ 0x2b8 │ │ eoreq r1, r8, r4, ror #17 │ │ eoreq r1, r8, r4, lsl #4 │ │ mlaeq r8, ip, r4, r1 │ │ - ldc2l 15, cr13, [r5, #344] @ 0x158 │ │ - ldc2l 15, cr3, [r5, #52] @ 0x34 │ │ + ldc2l 15, cr13, [r5, #524] @ 0x20c │ │ + ldc2l 15, cr3, [r5, #232] @ 0xe8 │ │ eoreq r1, r8, r8, asr r1 │ │ ldc2l 6, cr14, [r3, #916] @ 0x394 │ │ - ldc2l 14, cr3, [r5, #868] @ 0x364 │ │ + ldc2l 15, cr3, [r5, #24] │ │ eoreq r1, r8, r8, asr #2 │ │ eoreq r1, r8, ip, lsl #5 │ │ - ldc2l 2, cr9, [r4, #580] @ 0x244 │ │ - ldc2l 12, cr13, [r5, #648] @ 0x288 │ │ - ldc2l 12, cr3, [r5, #356] @ 0x164 │ │ - ldc2l 0, cr9, [r4, #196] @ 0xc4 │ │ + ldc2l 2, cr9, [r4, #760] @ 0x2f8 │ │ + ldc2l 12, cr13, [r5, #828] @ 0x33c │ │ + ldc2l 12, cr3, [r5, #536] @ 0x218 │ │ + ldc2l 0, cr9, [r4, #376] @ 0x178 │ │ mlaeq r8, r4, lr, r0 │ │ ldc2l 4, cr14, [r3, #100] @ 0x64 │ │ - ldc2l 2, cr9, [r4, #244] @ 0xf4 │ │ + ldc2l 2, cr9, [r4, #424] @ 0x1a8 │ │ eoreq r1, r8, r0, lsr #1 │ │ - ldc2l 15, cr8, [r4, #820] @ 0x334 │ │ + ldc2l 15, cr8, [r4, #1000] @ 0x3e8 │ │ eoreq r0, r8, r8, ror #28 │ │ ldc2l 2, cr3, [r7, #464] @ 0x1d0 │ │ strhteq r1, [r8], -r0 │ │ - ldc2l 1, cr9, [r4, #468] @ 0x1d4 │ │ + ldc2l 1, cr9, [r4, #648] @ 0x288 │ │ ldc2l 11, cr10, [r6, #468] @ 0x1d4 @ │ │ vcadd.f32 d16, d6, d8, #270 │ │ - ldc2l 4, cr12, [r5, #396] @ 0x18c │ │ + ldc2l 4, cr12, [r5, #576] @ 0x240 │ │ ldrbeq ip, [r5, #2900] @ 0xb54 │ │ - ldc2l 10, cr9, [r4, #244] @ 0xf4 @ │ │ - ldc2l 3, cr12, [r5, #952] @ 0x3b8 │ │ - ldc2l 9, cr9, [r4, #426] @ 0x1aa @ │ │ + ldc2l 10, cr9, [r4, #424] @ 0x1a8 @ │ │ + ldc2l 4, cr12, [r5, #108] @ 0x6c │ │ + ldc2l 10, cr9, [r4, #8] @ │ │ ldc2l 5, cr11, [r6, #596] @ 0x254 │ │ - ldc2l 2, cr4, [r5, #976] @ 0x3d0 │ │ - ldc2l 7, cr9, [r4, #52] @ 0x34 │ │ - ldc2l 6, cr10, [r4, #608] @ 0x260 │ │ + ldc2l 3, cr4, [r5, #132] @ 0x84 │ │ + ldc2l 7, cr9, [r4, #232] @ 0xe8 │ │ + ldc2l 6, cr10, [r4, #788] @ 0x314 │ │ mlaeq r8, r0, sl, r1 │ │ strhteq r1, [r8], -ip │ │ - ldc2l 5, cr9, [r4, #964] @ 0x3c4 │ │ + ldc2l 6, cr9, [r4, #120] @ 0x78 │ │ eoreq r1, r8, r0, asr sl │ │ eoreq r1, r8, r0, ror r3 │ │ eoreq r1, r8, r4, lsl #12 │ │ - ldc2l 1, cr14, [r5, #776] @ 0x308 │ │ - ldc2l 1, cr4, [r5, #484] @ 0x1e4 │ │ + ldc2l 1, cr14, [r5, #956] @ 0x3bc │ │ + ldc2l 1, cr4, [r5, #664] @ 0x298 │ │ eoreq r1, r8, r4, asr #7 │ │ ldc2l 9, cr14, [r3, #162] @ 0xa2 @ │ │ - ldc2l 1, cr4, [r5, #292] @ 0x124 │ │ + ldc2l 1, cr4, [r5, #472] @ 0x1d8 │ │ strhteq r1, [r8], -r4 │ │ strdeq r1, [r8], -r8 @ │ │ - ldc2l 4, cr9, [r4, #1012] @ 0x3f4 │ │ - ldc2l 13, cr13, [r5, #376] @ 0x178 │ │ - ldc2l 13, cr3, [r5, #68] @ 0x44 │ │ - ldc2l 0, cr9, [r4, #932] @ 0x3a4 │ │ + ldc2l 5, cr9, [r4, #168] @ 0xa8 │ │ + ldc2l 13, cr13, [r5, #556] @ 0x22c │ │ + ldc2l 13, cr3, [r5, #248] @ 0xf8 │ │ + ldc2l 1, cr9, [r4, #88] @ 0x58 │ │ eoreq r0, r8, ip, asr #30 │ │ ldc2l 4, cr14, [r3, #836] @ 0x344 │ │ - ldc2l 4, cr9, [r4, #644] @ 0x284 │ │ + ldc2l 4, cr9, [r4, #824] @ 0x338 │ │ eoreq r1, r8, r4, lsl #6 │ │ - ldc2l 0, cr9, [r4, #580] @ 0x244 │ │ + ldc2l 0, cr9, [r4, #760] @ 0x2f8 │ │ eoreq r0, r8, r8, lsl pc │ │ ldc2l 3, cr3, [r7, #176] @ 0xb0 │ │ eoreq r1, r8, r0 │ │ ldc2l 0, cr11, [r6, #700] @ 0x2bc │ │ - ldc2l 15, cr8, [r4, #356] @ 0x164 │ │ - ldc2l 4, cr11, [r4, #540] @ 0x21c │ │ + ldc2l 15, cr8, [r4, #536] @ 0x218 │ │ + ldc2l 4, cr11, [r4, #720] @ 0x2d0 │ │ eoreq r1, r8, ip, lsl r0 │ │ - ldc2l 14, cr8, [r4, #900] @ 0x384 │ │ + ldc2l 15, cr8, [r4, #56] @ 0x38 │ │ eoreq r1, r8, r8, lsr #2 │ │ vcadd.f32 q13, q11, , #270 │ │ - ldc2l 13, cr11, [r5, #796] @ 0x31c │ │ + ldc2l 13, cr11, [r5, #976] @ 0x3d0 │ │ ldrbeq ip, [r5, #1208] @ 0x4b8 │ │ - ldc2l 3, cr9, [r4, #628] @ 0x274 │ │ + ldc2l 3, cr9, [r4, #808] @ 0x328 │ │ eoreq r1, r8, ip, ror #11 │ │ - ldc2l 13, cr13, [r4, #672] @ 0x2a0 │ │ - ldc2l 14, cr8, [r4, #292] @ 0x124 │ │ - ldc2l 9, cr1, [r5, #250] @ 0xfa @ │ │ + ldc2l 13, cr13, [r4, #852] @ 0x354 │ │ + ldc2l 14, cr8, [r4, #472] @ 0x1d8 │ │ + ldc2l 9, cr1, [r5, #340] @ 0x154 @ │ │ ldc2l 11, cr15, [r5, #928] @ 0x3a0 @ │ │ - ldc2l 10, cr13, [r5, #580] @ 0x244 @ │ │ - ldc2l 2, cr10, [r4, #880] @ 0x370 │ │ - ldc2l 14, cr8, [r4, #132] @ 0x84 │ │ + ldc2l 10, cr13, [r5, #760] @ 0x2f8 @ │ │ + ldc2l 3, cr10, [r4, #36] @ 0x24 │ │ + ldc2l 14, cr8, [r4, #312] @ 0x138 │ │ │ │ 024da288 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ bl 270ce80 │ │ cmp r0, #0 │ │ beq 24da2a4 │ │ @@ -1461662,15 +1461662,15 @@ │ │ add r0, pc, r0 │ │ bl 270da10 │ │ mov r0, r4 │ │ mov r1, #6 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, sl, fp, pc} │ │ - ldc2l 13, cr7, [r4, #284] @ 0x11c │ │ + ldc2l 13, cr7, [r4, #464] @ 0x1d0 │ │ ldc2l 2, cr0, [r7, #40] @ 0x28 │ │ │ │ 024da2e4 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #16 │ │ mov ip, r2 │ │ @@ -1462611,43 +1462611,43 @@ │ │ ldrbeq fp, [r5, #3248] @ 0xcb0 │ │ ldrbeq fp, [r5, #3700] @ 0xe74 │ │ ldrbeq fp, [r5, #3124] @ 0xc34 │ │ ldrbeq fp, [r5, #3352] @ 0xd18 │ │ ldrbeq fp, [r5, #3312] @ 0xcf0 │ │ ldrbeq fp, [r5, #3300] @ 0xce4 │ │ ldrbeq fp, [r5, #3532] @ 0xdcc │ │ - ldc2l 6, cr3, [r5, #212] @ 0xd4 │ │ + ldc2l 6, cr3, [r5, #392] @ 0x188 │ │ ldrbeq fp, [r5, #3432] @ 0xd68 │ │ ldrbeq fp, [r5, #3416] @ 0xd58 │ │ ldrbeq fp, [r5, #2992] @ 0xbb0 │ │ ldrbeq fp, [r5, #2936] @ 0xb78 │ │ ldrbeq fp, [r5, #3068] @ 0xbfc │ │ ldrbeq fp, [r5, #2776] @ 0xad8 │ │ ldrbeq fp, [r5, #2924] @ 0xb6c │ │ ldrbeq fp, [r5, #3040] @ 0xbe0 │ │ ldrbeq fp, [r5, #3036] @ 0xbdc │ │ ldrbeq fp, [r5, #3304] @ 0xce8 │ │ - ldc2l 15, cr2, [r4, #772] @ 0x304 │ │ - ldc2l 10, cr15, [r4, #400] @ 0x190 @ │ │ + ldc2l 15, cr2, [r4, #952] @ 0x3b8 │ │ + ldc2l 10, cr15, [r4, #580] @ 0x244 @ │ │ ldrbeq fp, [r5, #2904] @ 0xb58 │ │ ldrbeq fp, [r5, #2848] @ 0xb20 │ │ ldrbeq fp, [r5, #2856] @ 0xb28 │ │ ldrbeq fp, [r5, #3180] @ 0xc6c │ │ ldrbeq fp, [r5, #2608] @ 0xa30 │ │ eoreq r0, r8, r4, ror #22 │ │ ldrbeq fp, [r5, #2772] @ 0xad4 │ │ eoreq r0, r8, r0, lsl fp │ │ ldrbeq fp, [r5, #2328] @ 0x918 │ │ ldrbeq fp, [r5, #2328] @ 0x918 │ │ ldrbeq fp, [r5, #2440] @ 0x988 │ │ ldrbeq fp, [r5, #2408] @ 0x968 │ │ ldrbeq fp, [r5, #2556] @ 0x9fc │ │ - ldc2l 3, cr3, [r5, #628] @ 0x274 │ │ + ldc2l 3, cr3, [r5, #808] @ 0x328 │ │ ldc2l 5, cr3, [r6, #216] @ 0xd8 │ │ - ldc2l 6, cr13, [r4, #824] @ 0x338 │ │ + ldc2l 6, cr13, [r4, #1004] @ 0x3ec │ │ ldc2l 13, cr15, [r6, #88] @ 0x58 │ │ ldrbeq fp, [r5, #2636] @ 0xa4c │ │ ldrbeq fp, [r5, #2236] @ 0x8bc │ │ ldrbeq fp, [r5, #2184] @ 0x888 │ │ ldrbeq fp, [r5, #2300] @ 0x8fc │ │ ldrbeq fp, [r5, #2168] @ 0x878 │ │ ldrbeq fp, [r5, #2060] @ 0x80c │ │ @@ -1462686,26 +1462686,26 @@ │ │ ldrbeq fp, [r5, #1912] @ 0x778 │ │ ldrbeq fp, [r5, #1456] @ 0x5b0 │ │ ldrbeq fp, [r5, #1872] @ 0x750 │ │ ldrbeq fp, [r5, #1860] @ 0x744 │ │ ldrbeq fp, [r5, #1860] @ 0x744 │ │ ldrbeq fp, [r5, #1940] @ 0x794 │ │ eoreq r0, r8, ip, ror r6 │ │ - ldc2l 11, cr8, [r5, #324] @ 0x144 @ │ │ - ldc2l 3, cr8, [r4, #468] @ 0x1d4 │ │ - ldc2l 4, cr7, [r4, #804] @ 0x324 │ │ + ldc2l 11, cr8, [r5, #504] @ 0x1f8 @ │ │ + ldc2l 3, cr8, [r4, #648] @ 0x288 │ │ + ldc2l 4, cr7, [r4, #984] @ 0x3d8 │ │ ldc2l 14, cr8, [r3, #664] @ 0x298 │ │ ldc2l 7, cr13, [r3, #416] @ 0x1a0 │ │ - ldc2l 4, cr7, [r4, #200] @ 0xc8 │ │ - ldc2l 3, cr8, [r4, #148] @ 0x94 │ │ + ldc2l 4, cr7, [r4, #380] @ 0x17c │ │ + ldc2l 3, cr8, [r4, #328] @ 0x148 │ │ ldc2l 14, cr8, [r3, #660] @ 0x294 │ │ ldc2l 14, cr4, [r6, #224] @ 0xe0 │ │ ldc2l 4, cr10, [r6, #288] @ 0x120 │ │ ldc2l 0, cr15, [r5, #204] @ 0xcc │ │ - ldc2l 14, cr2, [r5, #836] @ 0x344 │ │ + ldc2l 14, cr2, [r5, #1016] @ 0x3f8 │ │ ldrbeq fp, [r5, #1180] @ 0x49c │ │ ldrbeq fp, [r5, #636] @ 0x27c │ │ ldrbeq fp, [r5, #604] @ 0x25c │ │ ldrbeq fp, [r5, #996] @ 0x3e4 │ │ ldrbeq fp, [r5, #976] @ 0x3d0 │ │ ldrbeq fp, [r5, #1256] @ 0x4e8 │ │ ldrbeq fp, [r5, #936] @ 0x3a8 │ │ @@ -1462754,16 +1462754,16 @@ │ │ andeq r0, r0, r0 │ │ subsmi r8, r8, r0 │ │ andeq r0, r0, r0 │ │ subsgt r8, r3, r0 │ │ andeq r0, r0, r0 │ │ subsmi r0, lr, r0 │ │ ldc2l 9, cr8, [r3, #242] @ 0xf2 @ │ │ - ldc2l 13, cr7, [r4, #756] @ 0x2f4 │ │ - ldc2l 13, cr8, [r4, #688] @ 0x2b0 │ │ + ldc2l 13, cr7, [r4, #936] @ 0x3a8 │ │ + ldc2l 13, cr8, [r4, #868] @ 0x364 │ │ nop {0} │ │ andeq r0, r0, r0 │ │ subsmi r8, r3, r0 │ │ bl 2bec0a4 <_nl_msg_cat_cntr@@Base+0x45ab04> │ │ svccc 0x001a36e2 │ │ andeq r0, r0, r0 │ │ subgt r0, r2, r0 │ │ @@ -1464148,30 +1464148,30 @@ │ │ ldrbeq r9, [r5, #3776] @ 0xec0 │ │ ldrbeq r9, [r5, #3732] @ 0xe94 │ │ ldrbeq r9, [r5, #3604] @ 0xe14 │ │ ldrbeq r9, [r5, #3724] @ 0xe8c │ │ ldrbeq r9, [r5, #3596] @ 0xe0c │ │ ldrbeq r9, [r5, #3736] @ 0xe98 │ │ ldrbeq r9, [r5, #3596] @ 0xe0c │ │ - vcadd.f32 d17, d5, d9, #270 │ │ + ldc2l 8, cr1, [r5, #216] @ 0xd8 │ │ ldrbeq r9, [r5, #3904] @ 0xf40 │ │ ldrbeq r9, [r5, #3388] @ 0xd3c │ │ ldrbeq r9, [r5, #3316] @ 0xcf4 │ │ - ldc2l 10, cr7, [r4, #512] @ 0x200 @ │ │ + ldc2l 10, cr7, [r4, #692] @ 0x2b4 @ │ │ ldc2l 14, cr11, [r3, #548] @ 0x224 │ │ ldrbeq r9, [r5, #3076] @ 0xc04 │ │ ldrbeq r9, [r5, #2828] @ 0xb0c │ │ ldrbeq r9, [r5, #2792] @ 0xae8 │ │ ldrbeq r9, [r5, #2592] @ 0xa20 │ │ ldrbeq r9, [r5, #2888] @ 0xb48 │ │ ldrbeq r9, [r5, #2692] @ 0xa84 │ │ ldrbeq r9, [r5, #2908] @ 0xb5c │ │ ldrbeq r9, [r5, #2580] @ 0xa14 │ │ ldc2l 5, cr1, [r6, #260] @ 0x104 │ │ - ldc2l 1, cr5, [r5, #832] @ 0x340 │ │ + ldc2l 1, cr5, [r5, #1012] @ 0x3f4 │ │ │ │ 024dc9dc : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #8 │ │ ldr r5, [fp, #8] │ │ mov r4, r3 │ │ @@ -1465231,15 +1465231,15 @@ │ │ rsb r4, r0, #1 │ │ bhi 24ddbb0 │ │ ldr r0, [pc, #3812] @ 24de940 │ │ ldr r6, [sp, #44] @ 0x2c │ │ add r0, pc, r0 │ │ ldr r8, [r0, r1, lsl #2] │ │ b 24ddc20 │ │ - ldc2l 2, cr15, [r3, #84] @ 0x54 │ │ + ldc2l 2, cr15, [r3, #264] @ 0x108 │ │ ldrbeq r9, [r5, #2084] @ 0x824 │ │ ldrbeq sl, [r5, #2012] @ 0x7dc │ │ ldrbeq r9, [r5, #2192] @ 0x890 │ │ ldr r0, [pc, #3780] @ 24de944 │ │ movw r3, #1378 @ 0x562 │ │ ldr r2, [pc, #3776] @ 24de948 │ │ add r0, pc, r0 │ │ @@ -1465279,46 +1465279,46 @@ │ │ ldr r3, [sp, #44] @ 0x2c │ │ add r1, r1, r3 │ │ add r1, r1, r5 │ │ b 24ddc64 │ │ eoreq lr, r7, r0, ror #13 │ │ ldrdeq lr, [r7], -r4 @ │ │ eoreq lr, r7, r4, ror #12 │ │ - ldc2l 12, cr10, [r4, #64] @ 0x40 │ │ - ldc2l 5, cr5, [r4, #56] @ 0x38 │ │ + ldc2l 12, cr10, [r4, #244] @ 0xf4 │ │ + ldc2l 5, cr5, [r4, #236] @ 0xec │ │ mlaeq r7, r0, r6, lr │ │ - ldc2l 3, cr8, [r5, #792] @ 0x318 │ │ - ldc2l 4, cr5, [r4, #840] @ 0x348 │ │ + ldc2l 3, cr8, [r5, #972] @ 0x3cc │ │ + ldc2l 4, cr5, [r4, #1020] @ 0x3fc │ │ eoreq lr, r7, r4, asr r6 │ │ ldc2l 7, cr12, [pc, #128] @ 24ddbc8 │ │ ldrbeq r9, [r5, #1836] @ 0x72c │ │ eoreq lr, r7, ip, lsl #12 │ │ - ldc2l 11, cr10, [r4, #336] @ 0x150 @ │ │ - ldc2l 4, cr5, [r4, #328] @ 0x148 │ │ + ldc2l 11, cr10, [r4, #516] @ 0x204 @ │ │ + ldc2l 4, cr5, [r4, #508] @ 0x1fc │ │ ldrdeq lr, [r7], -r4 @ │ │ - ldc2l 3, cr8, [r5, #72] @ 0x48 │ │ - ldc2l 4, cr5, [r4, #120] @ 0x78 │ │ + ldc2l 3, cr8, [r5, #252] @ 0xfc │ │ + ldc2l 4, cr5, [r4, #300] @ 0x12c │ │ ldrbeq sl, [r5, #1972] @ 0x7b4 │ │ ldrbeq r9, [r5, #1620] @ 0x654 │ │ eoreq lr, r7, r0, ror #10 │ │ ldrbeq sl, [r5, #1696] @ 0x6a0 │ │ ldrbeq r9, [r5, #1744] @ 0x6d0 │ │ - ldc2l 2, cr3, [r4, #556] @ 0x22c │ │ + ldc2l 2, cr3, [r4, #736] @ 0x2e0 │ │ ldrbeq sl, [r5, #1396] @ 0x574 │ │ ldrbeq r9, [r5, #1980] @ 0x7bc │ │ ldrbeq r9, [r5, #1872] @ 0x750 │ │ ldc2l 13, cr14, [r5, #108] @ 0x6c │ │ ldc2l 3, cr13, [r3, #632] @ 0x278 │ │ ldc2l 12, cr12, [r3, #456] @ 0x1c8 │ │ ldrbeq sl, [r5, #1492] @ 0x5d4 │ │ ldc2l 13, cr6, [r3, #488] @ 0x1e8 │ │ - ldc2l 11, cr4, [r5, #840] @ 0x348 @ │ │ + ldc2l 11, cr4, [r5, #1020] @ 0x3fc @ │ │ ldc2l 13, cr12, [r3, #964] @ 0x3c4 │ │ - ldc2l 1, cr3, [r4, #460] @ 0x1cc │ │ - ldc2l 10, cr10, [r4, #152] @ 0x98 @ │ │ + ldc2l 1, cr3, [r4, #640] @ 0x280 │ │ + ldc2l 10, cr10, [r4, #332] @ 0x14c @ │ │ ldc2l 14, cr0, [r6, #672] @ 0x2a0 │ │ ldc2l 3, cr14, [r6, #748] @ 0x2ec │ │ str r5, [sp, #32] │ │ mov r5, r3 │ │ str r7, [sp, #40] @ 0x28 │ │ mov r3, #1408 @ 0x580 │ │ ldr r0, [pc, #4048] @ 24deb98 │ │ @@ -1465486,22 +1465486,22 @@ │ │ cmp r1, #280 @ 0x118 │ │ ldr r5, [pc, #3880] @ 24ded7c │ │ ldr r5, [pc, r5] │ │ bcs 24ddf34 │ │ mov r0, r1 │ │ b 24ddf58 │ │ ldc2l 15, cr5, [r6, #520] @ 0x208 │ │ - ldc2l 14, cr14, [r3, #208] @ 0xd0 │ │ + ldc2l 14, cr14, [r3, #388] @ 0x184 │ │ ldc2l 15, cr5, [r6, #200] @ 0xc8 │ │ nop {0} │ │ andeq r0, r0, r0 │ │ submi r0, lr, r0 │ │ andeq r0, r0, r0 │ │ adcmi r2, ip, r0 │ │ - ldc2l 10, cr8, [r5, #308] @ 0x134 @ │ │ + ldc2l 10, cr8, [r5, #488] @ 0x1e8 @ │ │ sub r2, r0, #13 │ │ cmp r2, #1 │ │ bhi 24de0ec │ │ vldr d17, [r5] │ │ mov r6, #1 │ │ vldr d16, [r5, #8] │ │ vcvt.s32.f64 s2, d17 │ │ @@ -1465520,31 +1465520,31 @@ │ │ vstr s2, [r5] │ │ vcvt.s32.f64 s0, d16 │ │ vstr s0, [r1] │ │ cmp r4, #0 │ │ ble 24de94c │ │ vmov r0, s0 │ │ b 24de9c4 │ │ - ldc2l 6, cr0, [r4, #292] @ 0x124 │ │ + ldc2l 6, cr0, [r4, #472] @ 0x1d8 │ │ ldr r0, [pc, #3736] @ 24ded90 │ │ mov r1, #135 @ 0x87 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ ldr r0, [pc, #3724] @ 24ded94 │ │ mov r1, #21 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ b 24de7dc │ │ - ldc2l 10, cr8, [r5, #72] @ 0x48 @ │ │ + ldc2l 10, cr8, [r5, #252] @ 0xfc @ │ │ ldc2l 1, cr12, [r5, #856] @ 0x358 │ │ - ldc2l 7, cr6, [r5, #884] @ 0x374 │ │ + vcadd.f32 d22, d5, d10, #270 │ │ ldc2l 11, cr6, [r3, #568] @ 0x238 @ │ │ ldc2l 12, cr12, [r5, #852] @ 0x354 │ │ ldc2l 5, cr6, [r6, #696] @ 0x2b8 │ │ - ldc2l 15, cr8, [r4, #316] @ 0x13c │ │ + ldc2l 15, cr8, [r4, #496] @ 0x1f0 │ │ ldc2l 12, cr12, [r5, #400] @ 0x190 │ │ ldr r0, [pc, #4076] @ 24def28 │ │ movw r3, #1676 @ 0x68c │ │ ldr r2, [pc, #4072] @ 24def2c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1465614,17 +1465614,17 @@ │ │ ldr r0, [sl, r1, lsl #2] │ │ vldr d8, [r4] │ │ ldr r5, [pc, #4044] @ 24df024 │ │ str r1, [sp, #60] @ 0x3c │ │ add r5, pc, r5 │ │ str r0, [r5] │ │ b 24de288 │ │ - ldc2l 12, cr14, [r3, #404] @ 0x194 │ │ - ldc2l 8, cr8, [r5, #620] @ 0x26c │ │ - ldc2l 10, cr10, [r5, #808] @ 0x328 @ │ │ + ldc2l 12, cr14, [r3, #584] @ 0x248 │ │ + vcadd.f32 q12, , q4, #270 │ │ + ldc2l 10, cr10, [r5, #988] @ 0x3dc @ │ │ ldr r0, [pc, #4016] @ 24df028 │ │ movw r3, #1687 @ 0x697 │ │ ldr r2, [pc, #4012] @ 24df02c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r0, [sl, r0, lsl #2] │ │ @@ -1465673,17 +1465673,17 @@ │ │ add r1, pc, r1 │ │ vstr d17, [r0] │ │ vstr s0, [r1] │ │ b 24ddca8 │ │ ldrbeq sl, [r5, #772] @ 0x304 │ │ ldrbeq r9, [r5, #464] @ 0x1d0 │ │ ldc2l 4, cr6, [r6, #108] @ 0x6c │ │ - ldc2l 11, cr14, [r3, #276] @ 0x114 @ │ │ + ldc2l 11, cr14, [r3, #456] @ 0x1c8 @ │ │ eoreq lr, r7, r0, ror r0 │ │ - ldc2l 11, cr14, [r3, #116] @ 0x74 @ │ │ + ldc2l 11, cr14, [r3, #296] @ 0x128 @ │ │ ldrbeq sl, [r5, #668] @ 0x29c │ │ ldrbeq sl, [r5, #368] @ 0x170 │ │ ldrbeq r9, [r5, #296] @ 0x128 │ │ ldrbeq sl, [r5, #348] @ 0x15c │ │ ldc2l 3, cr6, [r6, #588] @ 0x24c │ │ eoreq lr, r7, r4 │ │ eoreq lr, r7, r4 │ │ @@ -1465701,36 +1465701,36 @@ │ │ ldrbeq r9, [r5, #248] @ 0xf8 │ │ ldrbeq sl, [r5, #132] @ 0x84 │ │ ldrbeq r9, [r5, #4088] @ 0xff8 │ │ ldc2l 14, cr11, [r6, #440] @ 0x1b8 │ │ ldrbeq sl, [r5, #320] @ 0x140 │ │ ldrbeq sl, [r5, #68] @ 0x44 │ │ ldrbeq r9, [r5, #572] @ 0x23c │ │ - ldc2l 13, cr4, [r4, #376] @ 0x178 │ │ + ldc2l 13, cr4, [r4, #556] @ 0x22c │ │ ldrbeq sl, [r5, #252] @ 0xfc │ │ - ldc2l 13, cr4, [r4, #152] @ 0x98 │ │ + ldc2l 13, cr4, [r4, #332] @ 0x14c │ │ ldrbeq r9, [r5, #4032] @ 0xfc0 │ │ - ldc2l 12, cr4, [r4, #888] @ 0x378 │ │ + ldc2l 13, cr4, [r4, #44] @ 0x2c │ │ ldrbeq sl, [r5, #100] @ 0x64 │ │ - ldc2l 12, cr4, [r4, #584] @ 0x248 │ │ + ldc2l 12, cr4, [r4, #764] @ 0x2fc │ │ ldrbeq r8, [r5, #4000] @ 0xfa0 │ │ ldrbeq r8, [r5, #3808] @ 0xee0 │ │ ldrbeq r9, [r5, #3860] @ 0xf14 │ │ ldrbeq r9, [r5, #3828] @ 0xef4 │ │ - ldc2l 10, cr10, [r4, #700] @ 0x2bc @ │ │ - ldc2l 12, cr4, [r4, #56] @ 0x38 │ │ + ldc2l 10, cr10, [r4, #880] @ 0x370 @ │ │ + ldc2l 12, cr4, [r4, #236] @ 0xec │ │ ldrbeq r9, [r5, #3792] @ 0xed0 │ │ ldrbeq r9, [r5, #2428] @ 0x97c │ │ ldrbeq r9, [r5, #3988] @ 0xf94 │ │ - ldc2l 10, cr10, [r4, #412] @ 0x19c @ │ │ - ldc2l 11, cr4, [r4, #792] @ 0x318 @ │ │ + ldc2l 10, cr10, [r4, #592] @ 0x250 @ │ │ + ldc2l 11, cr4, [r4, #972] @ 0x3cc @ │ │ ldrbeq r8, [r5, #3660] @ 0xe4c │ │ ldrbeq r8, [r5, #3608] @ 0xe18 │ │ ldc2l 12, cr11, [r6, #328] @ 0x148 │ │ - ldc2l 11, cr4, [r4, #520] @ 0x208 @ │ │ + ldc2l 11, cr4, [r4, #700] @ 0x2bc @ │ │ ldrbeq r8, [r5, #3708] @ 0xe7c │ │ ldrbeq r9, [r5, #24] │ │ ldrbeq r8, [r5, #4072] @ 0xfe8 │ │ ldrbeq r8, [r5, #3624] @ 0xe28 │ │ ldr r0, [pc, #3972] @ 24df1b4 │ │ movw r3, #1694 @ 0x69e │ │ ldr r2, [pc, #3968] @ 24df1b8 │ │ @@ -1465944,16 +1465944,16 @@ │ │ bcc 24de638 │ │ ldr r0, [pc, #4060] @ 24df558 │ │ movw r3, #1759 @ 0x6df │ │ ldr r2, [pc, #4056] @ 24df55c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ b 24de630 │ │ - ldc2l 10, cr14, [r4, #960] @ 0x3c0 @ │ │ - ldc2l 7, cr2, [r5, #72] @ 0x48 │ │ + ldc2l 11, cr14, [r4, #116] @ 0x74 @ │ │ + ldc2l 7, cr2, [r5, #252] @ 0xfc │ │ ldrbeq r9, [r5, #3664] @ 0xe50 │ │ ldrbeq r8, [r5, #3440] @ 0xd70 │ │ ldrbeq r8, [r5, #3428] @ 0xd64 │ │ eoreq sp, r7, r4, lsr #23 │ │ ldrbeq r8, [r5, #3388] @ 0xd3c │ │ ldrbeq r9, [r5, #3548] @ 0xddc │ │ ldrbeq r8, [r5, #3704] @ 0xe78 │ │ @@ -1466103,15 +1466103,15 @@ │ │ mov r0, #0 │ │ sub sp, fp, #64 @ 0x40 │ │ vpop {d8-d11} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldrdeq sp, [r7], -r0 @ │ │ eoreq sp, r7, ip, lsl r9 │ │ - ldc2l 6, cr2, [r4, #888] @ 0x378 │ │ + ldc2l 7, cr2, [r4, #44] @ 0x2c │ │ sub r2, r1, #13 │ │ cmp r2, #1 │ │ bhi 24de8ac │ │ ldr r0, [pc, #3812] @ 24df704 │ │ cmp r1, #13 │ │ ldr r5, [sp, #36] @ 0x24 │ │ add r0, pc, r0 │ │ @@ -1466142,23 +1466142,23 @@ │ │ ldr r1, [pc, #3728] @ 24df720 │ │ ldr r1, [pc, r1] │ │ str r1, [sp, #60] @ 0x3c │ │ cmp r1, #280 @ 0x118 │ │ bcs 24df1c4 │ │ mov r0, r1 │ │ b 24df1e4 │ │ - ldc2l 6, cr5, [r4, #324] @ 0x144 │ │ - ldc2l 4, cr2, [r5, #76] @ 0x4c │ │ + ldc2l 6, cr5, [r4, #504] @ 0x1f8 │ │ + ldc2l 4, cr2, [r5, #256] @ 0x100 │ │ sub r1, r1, #1 │ │ cmp r1, #6 │ │ bhi 24df040 │ │ add r2, pc, #8 │ │ ldr r1, [r2, r1, lsl #2] │ │ add pc, r2, r1 │ │ - ldc2l 6, cr5, [r4, #164] @ 0xa4 │ │ + ldc2l 6, cr5, [r4, #344] @ 0x158 │ │ andeq r0, r0, r0, lsr #32 │ │ andeq r0, r0, ip, asr #13 │ │ andeq r0, r0, r8, ror r7 │ │ andeq r0, r0, ip, ror #12 │ │ andeq r0, r0, r8, ror r7 │ │ andeq r0, r0, r8, ror r7 │ │ andeq r0, r0, r0, lsl r7 │ │ @@ -1466182,16 +1466182,16 @@ │ │ ldrbeq r9, [r5, #2824] @ 0xb08 │ │ ldrbeq r8, [r5, #2896] @ 0xb50 │ │ ldrbeq r8, [r5, #2880] @ 0xb40 │ │ ldrbeq r9, [r5, #2788] @ 0xae4 │ │ ldrbeq r8, [r5, #2928] @ 0xb70 │ │ eoreq sp, r7, r8, lsl #16 │ │ eoreq sp, r7, r4, asr #14 │ │ - ldc2l 12, cr9, [r4, #960] @ 0x3c0 │ │ - ldc2l 5, cr4, [r4, #952] @ 0x3b8 │ │ + ldc2l 13, cr9, [r4, #116] @ 0x74 │ │ + ldc2l 6, cr4, [r4, #108] @ 0x6c │ │ ldr r1, [pc, #3932] @ 24df8b0 │ │ mov r0, r5 │ │ ldr r6, [pc, #3928] @ 24df8b4 │ │ ldr r3, [pc, #3928] @ 24df8b8 │ │ add r1, pc, r1 │ │ add r6, pc, r6 │ │ add r3, pc, r3 │ │ @@ -1466268,16 +1466268,16 @@ │ │ add r0, pc, r0 │ │ ldr r5, [sp, #40] @ 0x28 │ │ ldr r4, [sp, #32] │ │ ldr r6, [r0, r1, lsl #2] │ │ b 24deb10 │ │ eoreq sp, r7, r8, lsl #14 │ │ ldrbeq r8, [r5, #2700] @ 0xa8c │ │ - ldc2l 4, cr7, [r5, #680] @ 0x2a8 │ │ - ldc2l 5, cr4, [r4, #728] @ 0x2d8 │ │ + ldc2l 4, cr7, [r5, #860] @ 0x35c │ │ + ldc2l 5, cr4, [r4, #908] @ 0x38c │ │ ldc2l 7, cr11, [pc, #912] @ 24dee3c │ │ str r3, [sp, #28] │ │ movw r3, #1439 @ 0x59f │ │ ldr r0, [pc, #3820] @ 24df9a4 │ │ ldr r2, [pc, #3820] @ 24df9a8 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1466331,20 +1466331,20 @@ │ │ ldr r0, [pc, #3952] @ 24dfaf4 │ │ add r0, pc, r0 │ │ vldr d16, [r0] │ │ ldr r0, [pc, #3944] @ 24dfaf8 │ │ add r0, pc, r0 │ │ vldr d17, [r0] │ │ b 24df1a0 │ │ - ldc2l 11, cr9, [r4, #688] @ 0x2b0 @ │ │ - ldc2l 4, cr4, [r4, #680] @ 0x2a8 │ │ + ldc2l 11, cr9, [r4, #868] @ 0x364 @ │ │ + ldc2l 4, cr4, [r4, #860] @ 0x35c │ │ eoreq sp, r7, r4, asr #11 │ │ ldrbeq r8, [r5, #2376] @ 0x948 │ │ - ldc2l 3, cr7, [r5, #408] @ 0x198 │ │ - ldc2l 4, cr4, [r4, #456] @ 0x1c8 │ │ + ldc2l 3, cr7, [r5, #588] @ 0x24c │ │ + ldc2l 4, cr4, [r4, #636] @ 0x27c │ │ ldr r0, [pc, #3908] @ 24dfafc │ │ ldr r4, [pc, #3908] @ 24dfb00 │ │ add r0, pc, r0 │ │ add r4, pc, r4 │ │ vldr d16, [r0] │ │ ldr r0, [pc, #3896] @ 24dfb04 │ │ ldr r1, [pc, #3896] @ 24dfb08 │ │ @@ -1466395,28 +1466395,28 @@ │ │ ldr r2, [pc, r2] │ │ vmov r1, s0 │ │ add r1, r2, r1 │ │ str r1, [r0] │ │ b 24ddca8 │ │ ldrbeq r9, [r5, #1692] @ 0x69c │ │ ldrbeq r8, [r5, #2168] @ 0x878 │ │ - ldc2l 10, cr5, [r5, #484] @ 0x1e4 @ │ │ + ldc2l 10, cr5, [r5, #664] @ 0x298 @ │ │ vldmia r5, {d16-d17} │ │ ldr r0, [pc, #3720] @ 24dfb30 │ │ vcvt.s32.f64 s0, d16 │ │ ldr r1, [pc, #3716] @ 24dfb34 │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ vstr d17, [r0] │ │ vmov r0, s0 │ │ ldr r2, [pc, #3700] @ 24dfb38 │ │ ldr r2, [pc, r2] │ │ add r0, r2, r0 │ │ b 24ddca4 │ │ - ldc2l 3, cr4, [r4, #664] @ 0x298 │ │ + ldc2l 3, cr4, [r4, #844] @ 0x34c │ │ ldrbeq r8, [r5, #2016] @ 0x7e0 │ │ ldrbeq r8, [r5, #2092] @ 0x82c │ │ ldrbeq r8, [r5, #1864] @ 0x748 │ │ ldrbeq r8, [r5, #1556] @ 0x614 │ │ ldrbeq r9, [r5, #1472] @ 0x5c0 │ │ ldrbeq r9, [r5, #1564] @ 0x61c │ │ ldrbeq r9, [r5, #1544] @ 0x608 │ │ @@ -1466441,19 +1466441,19 @@ │ │ vldr d16, [r4] │ │ ldr r0, [pc, #4000] @ 24dfce0 │ │ vcvt.s32.f64 s0, d16 │ │ add r0, pc, r0 │ │ vstr s0, [r0] │ │ b 24ddca8 │ │ ldrbeq r9, [r5, #1820] @ 0x71c │ │ - ldc2l 9, cr5, [r5, #426] @ 0x1aa @ │ │ - ldc2l 3, cr4, [r4, #8] │ │ + ldc2l 10, cr5, [r5, #8] @ │ │ + ldc2l 3, cr4, [r4, #188] @ 0xbc │ │ ldrbeq r8, [r5, #1940] @ 0x794 │ │ - ldc2l 9, cr5, [r5, #306] @ 0x132 @ │ │ - ldc2l 2, cr4, [r4, #792] @ 0x318 │ │ + ldc2l 9, cr5, [r5, #396] @ 0x18c @ │ │ + ldc2l 2, cr4, [r4, #972] @ 0x3cc │ │ ldrbeq r9, [r5, #1280] @ 0x500 │ │ ldrbeq r8, [r5, #1356] @ 0x54c │ │ ldrbeq r9, [r5, #1336] @ 0x538 │ │ ldrbeq r8, [r5, #1284] @ 0x504 │ │ ldrbeq r8, [r5, #4068] @ 0xfe4 │ │ ldrbeq r9, [r5, #1528] @ 0x5f8 │ │ ldrbeq r9, [r5, #1272] @ 0x4f8 │ │ @@ -1466559,16 +1466559,16 @@ │ │ bhi 24df5a0 │ │ ldr r0, [pc, #4068] @ 24dfefc │ │ ldr r5, [sp, #44] @ 0x2c │ │ add r0, pc, r0 │ │ ldr r7, [sp, #40] @ 0x28 │ │ ldr r6, [r0, r1, lsl #2] │ │ b 24df604 │ │ - ldc2l 15, cr9, [r4, #844] @ 0x34c │ │ - ldc2l 1, cr4, [r4, #200] @ 0xc8 │ │ + ldc2l 0, cr10, [r4] │ │ + ldc2l 1, cr4, [r4, #380] @ 0x17c │ │ ldrbeq r9, [r5, #1240] @ 0x4d8 │ │ ldr r0, [pc, #4036] @ 24dff00 │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #4032] @ 24dff04 │ │ ldr r1, [pc, r1] │ │ sub r0, r1, r0 │ │ vmov s0, r0 │ │ @@ -1466582,15 +1466582,15 @@ │ │ vnmls.f64 d18, d16, d17 │ │ ldr r0, [pc, #3996] @ 24dff10 │ │ add r0, pc, r0 │ │ vldr d16, [r0] │ │ vadd.f64 d16, d18, d16 │ │ b 24df018 │ │ ldc2l 1, cr11, [r6, #712] @ 0x2c8 │ │ - ldc2l 0, cr4, [r4, #904] @ 0x388 │ │ + ldc2l 1, cr4, [r4, #60] @ 0x3c │ │ ldrbeq r8, [r5, #1432] @ 0x598 │ │ ldrbeq r9, [r5, #1180] @ 0x49c │ │ ldrbeq r8, [r5, #848] @ 0x350 │ │ ldr r0, [pc, #3960] @ 24dff14 │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #3956] @ 24dff18 │ │ ldr r1, [pc, r1] │ │ @@ -1466623,20 +1466623,20 @@ │ │ vldr d18, [r0] │ │ vadd.f64 d17, d18, d17 │ │ vadd.f64 d16, d17, d16 │ │ ldr r0, [sp, #36] @ 0x24 │ │ vstr d16, [r0] │ │ b 24de7dc │ │ ldrbeq r9, [r5, #752] @ 0x2f0 │ │ - ldc2l 14, cr9, [r4, #604] @ 0x25c │ │ - ldc2l 15, cr3, [r4, #984] @ 0x3d8 │ │ + ldc2l 14, cr9, [r4, #784] @ 0x310 │ │ + ldc2l 0, cr4, [r4, #140] @ 0x8c │ │ ldrbeq r9, [r5, #692] @ 0x2b4 │ │ ldrbeq r9, [r5, #912] @ 0x390 │ │ ldc2l 0, cr11, [r6, #520] @ 0x208 │ │ - ldc2l 15, cr3, [r4, #712] @ 0x2c8 │ │ + ldc2l 15, cr3, [r4, #892] @ 0x37c │ │ cmp r0, #18 │ │ beq 24df380 │ │ cmp r0, #20 │ │ bne 24df4f0 │ │ ldr r1, [pc, #3800] @ 24dff30 │ │ ldr r2, [pc, #3800] @ 24dff34 │ │ ldr r4, [pc, #3800] @ 24dff38 │ │ @@ -1466722,16 +1466722,16 @@ │ │ vstr d16, [r4] │ │ vldr d17, [r2] │ │ vmul.f64 d16, d17, d16 │ │ ldr r0, [pc, #3540] @ 24dff80 │ │ add r0, pc, r0 │ │ vstr d16, [r0] │ │ b 24ddca8 │ │ - ldc2l 12, cr9, [r4, #892] @ 0x37c │ │ - ldc2l 14, cr3, [r4, #248] @ 0xf8 │ │ + ldc2l 13, cr9, [r4, #48] @ 0x30 │ │ + ldc2l 14, cr3, [r4, #428] @ 0x1ac │ │ ldrbeq r9, [r5, #252] @ 0xfc │ │ ldrbeq r9, [r5, #472] @ 0x1d8 │ │ ldr r0, [pc, #3836] @ 24e00c8 │ │ movw r3, #1811 @ 0x713 │ │ ldr r2, [pc, #3832] @ 24e00cc │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1466765,15 +1466765,15 @@ │ │ add r0, pc, r0 │ │ vldr s0, [r0] │ │ vcvt.f64.s32 d17, s0 │ │ vadd.f64 d16, d16, d17 │ │ vstr d16, [r5, #8] │ │ b 24de7dc │ │ ldc2l 14, cr10, [r6, #808] @ 0x328 │ │ - ldc2l 13, cr3, [r4, #1000] @ 0x3e8 │ │ + ldc2l 14, cr3, [r4, #156] @ 0x9c │ │ ldrbeq r8, [r5, #428] @ 0x1ac │ │ ldrbeq r9, [r5, #40] @ 0x28 │ │ ldrbeq r8, [r5, #116] @ 0x74 │ │ ldrbeq r9, [r5, #128] @ 0x80 │ │ ldrbeq r9, [r5, #400] @ 0x190 │ │ vldmia r5, {d16-d19} │ │ mov r3, #0 │ │ @@ -1466799,16 +1466799,16 @@ │ │ vstr s6, [r1] │ │ cmp r4, #0 │ │ sub r0, r0, #1 │ │ str r0, [r2] │ │ ble 24df9c0 │ │ vmov r8, s0 │ │ b 24dfa28 │ │ - ldc2l 4, cr5, [r5, #292] @ 0x124 │ │ - ldc2l 13, cr3, [r4, #472] @ 0x1d8 │ │ + ldc2l 4, cr5, [r5, #472] @ 0x1d8 │ │ + ldc2l 13, cr3, [r4, #652] @ 0x28c │ │ ldrbeq r8, [r5, #4016] @ 0xfb0 │ │ ldrbeq r7, [r5, #4092] @ 0xffc │ │ ldrbeq r8, [r5, #4092] @ 0xffc │ │ ldrbeq r8, [r5, #4084] @ 0xff4 │ │ ldr r0, [pc, #3400] @ 24e0050 │ │ mov r2, #32 │ │ ldr r1, [pc, #3396] @ 24e0054 │ │ @@ -1466831,15 +1466831,15 @@ │ │ ldr r0, [pc, #3340] @ 24e0060 │ │ mov r3, r1 │ │ add r0, pc, r0 │ │ strd r2, [r5] │ │ b 24de7e4 │ │ ldrbeq r9, [r5, #264] @ 0x108 │ │ ldc2l 13, cr11, [r3, #360] @ 0x168 │ │ - ldc2l 12, cr3, [r4, #952] @ 0x3b8 │ │ + ldc2l 13, cr3, [r4, #108] @ 0x6c │ │ ldrbeq r8, [r5, #192] @ 0xc0 │ │ ldrbeq r8, [r5, #3988] @ 0xf94 │ │ ldrbeq r9, [r5, #176] @ 0xb0 │ │ ldrbeq r7, [r5, #3724] @ 0xe8c │ │ ldrbeq r8, [r5, #128] @ 0x80 │ │ ldr r4, [pc, #3424] @ 24e00e8 │ │ mov r0, #0 │ │ @@ -1466955,23 +1466955,23 @@ │ │ ldr r5, [pc, #3108] @ 24e0168 │ │ ldr r5, [pc, r5] │ │ bcs 24df8c4 │ │ mov r0, r1 │ │ b 24df8e8 │ │ ldrbeq r7, [r5, #4052] @ 0xfd4 │ │ ldrbeq r7, [r5, #4020] @ 0xfb4 │ │ - ldc2l 1, cr9, [r4, #976] @ 0x3d0 │ │ - ldc2l 10, cr3, [r4, #968] @ 0x3c8 @ │ │ + ldc2l 2, cr9, [r4, #132] @ 0x84 │ │ + ldc2l 11, cr3, [r4, #124] @ 0x7c @ │ │ ldrbeq r7, [r5, #3900] @ 0xf3c │ │ eoreq ip, r7, r8, lsr #24 │ │ eoreq ip, r7, r4, ror #23 │ │ ldrbeq r7, [r5, #3884] @ 0xf2c │ │ ldrbeq r7, [r5, #3852] @ 0xf0c │ │ ldc2l 12, cr0, [r6, #436] @ 0x1b4 │ │ - ldc2l 10, cr3, [r4, #296] @ 0x128 @ │ │ + ldc2l 10, cr3, [r4, #476] @ 0x1dc @ │ │ ldrbeq r8, [r5, #3208] @ 0xc88 │ │ ldrbeq r7, [r5, #3284] @ 0xcd4 │ │ ldrbeq r8, [r5, #3280] @ 0xcd0 │ │ ldrbeq r8, [r5, #3576] @ 0xdf8 │ │ mlaeq r7, r8, fp, ip │ │ ldrbeq r7, [r5, #3744] @ 0xea0 │ │ ldrbeq r7, [r5, #3620] @ 0xe24 │ │ @@ -1467061,15 +1467061,15 @@ │ │ ldrbeq r7, [r5, #3116] @ 0xc2c │ │ ldrbeq r8, [r5, #3428] @ 0xd64 │ │ ldrbeq r7, [r5, #3080] @ 0xc08 │ │ ldrbeq r7, [r5, #3584] @ 0xe00 │ │ ldrbeq r8, [r5, #3384] @ 0xd38 │ │ ldrbeq r7, [r5, #2952] @ 0xb88 │ │ ldrbeq r7, [r5, #3452] @ 0xd7c │ │ - ldc2l 4, cr13, [r3, #964] @ 0x3c4 │ │ + ldc2l 5, cr13, [r3, #120] @ 0x78 │ │ ldrbeq r7, [r5, #2820] @ 0xb04 │ │ ldrbeq r8, [r5, #2820] @ 0xb04 │ │ ldrbeq r7, [r5, #2768] @ 0xad0 │ │ ldrbeq r8, [r5, #1460] @ 0x5b4 │ │ ldrbeq r8, [r5, #2672] @ 0xa70 │ │ ldrbeq r8, [r5, #3012] @ 0xbc4 │ │ ldrbeq r8, [r5, #2560] @ 0xa00 │ │ @@ -1467230,16 +1467230,16 @@ │ │ strd r0, [r4] │ │ b 24de7dc │ │ ldrbeq r7, [r5, #2928] @ 0xb70 │ │ ldrbeq r8, [r5, #2728] @ 0xaa8 │ │ ldrbeq r7, [r5, #2328] @ 0x918 │ │ ldrdeq ip, [r7], -r4 @ │ │ eoreq ip, r7, r0, lsr #14 │ │ - ldc2l 12, cr8, [r4, #752] @ 0x2f0 │ │ - ldc2l 5, cr3, [r4, #744] @ 0x2e8 │ │ + ldc2l 12, cr8, [r4, #932] @ 0x3a4 │ │ + ldc2l 5, cr3, [r4, #924] @ 0x39c │ │ nop {0} │ │ andeq r0, r0, r0 │ │ submi r0, lr, r0 │ │ ldrdeq ip, [r7], -r4 @ │ │ ldrbeq r7, [r5, #2648] @ 0xa58 │ │ ldr r1, [pc, #1572] @ 24dffec │ │ mov r0, r5 │ │ @@ -1467307,16 +1467307,16 @@ │ │ bhi 24dfb3c │ │ ldr r0, [pc, #1344] @ 24e0008 │ │ ldr r4, [sp, #44] @ 0x2c │ │ add r0, pc, r0 │ │ ldr r7, [sp, #40] @ 0x28 │ │ ldr r5, [r0, r1, lsl #2] │ │ b 24dfba8 │ │ - ldc2l 4, cr6, [r5, #472] @ 0x1d8 │ │ - ldc2l 5, cr3, [r4, #520] @ 0x208 │ │ + ldc2l 4, cr6, [r5, #652] @ 0x28c │ │ + ldc2l 5, cr3, [r4, #700] @ 0x2bc │ │ ldc2l 7, cr10, [pc, #784] @ 24dfdf8 │ │ ldrbeq r8, [r5, #2044] @ 0x7fc │ │ ldrbeq r8, [r5, #2328] @ 0x918 │ │ ldrbeq r8, [r5, #2004] @ 0x7d4 │ │ ldrbeq r7, [r5, #2484] @ 0x9b4 │ │ ldrbeq r8, [r5, #1872] @ 0x750 │ │ ldrbeq r7, [r5, #1924] @ 0x784 │ │ @@ -1467599,27 +1467599,27 @@ │ │ ldrbeq r7, [r5, #600] @ 0x258 │ │ andeq r0, r0, r0 │ │ submi r0, lr, r0 │ │ andeq r0, r0, r0 │ │ adcmi r2, ip, r0 │ │ ldrbeq r7, [r5, #508] @ 0x1fc │ │ ldc2l 0, cr10, [r6, #40] @ 0x28 │ │ - ldc2l 15, cr2, [r4, #232] @ 0xe8 │ │ + ldc2l 15, cr2, [r4, #412] @ 0x19c │ │ ldrbeq r8, [r5, #736] @ 0x2e0 │ │ ldrbeq r7, [r5, #1000] @ 0x3e8 │ │ ldc2l 15, cr9, [r6, #824] @ 0x338 │ │ - ldc2l 14, cr2, [r4, #1016] @ 0x3f8 │ │ + ldc2l 15, cr2, [r4, #172] @ 0xac │ │ ldrbeq r7, [r5, #384] @ 0x180 │ │ ldrbeq r7, [r5, #376] @ 0x178 │ │ - ldc2l 1, cr8, [r4, #784] @ 0x310 │ │ - ldc2l 10, cr2, [r4, #776] @ 0x308 @ │ │ + ldc2l 1, cr8, [r4, #964] @ 0x3c4 │ │ + ldc2l 10, cr2, [r4, #956] @ 0x3bc @ │ │ ldrdeq fp, [r7], -ip @ │ │ ldrbeq r6, [r5, #3936] @ 0xf60 │ │ - ldc2l 9, cr5, [r5, #252] @ 0xfc @ │ │ - ldc2l 10, cr2, [r4, #552] @ 0x228 @ │ │ + ldc2l 9, cr5, [r5, #342] @ 0x156 @ │ │ + ldc2l 10, cr2, [r4, #732] @ 0x2dc @ │ │ ldc2l 12, cr9, [pc, #832] @ 24e02e4 │ │ eoreq fp, r7, r0, asr #23 │ │ ldrbeq r6, [r5, #3336] @ 0xd08 │ │ ldrbeq r6, [r5, #3788] @ 0xecc │ │ ldrbeq r7, [r5, #3324] @ 0xcfc │ │ eoreq fp, r7, r8, lsr #23 │ │ ldrbeq r7, [r5, #3264] @ 0xcc0 │ │ @@ -1467640,20 +1467640,20 @@ │ │ ldrbeq r7, [r5, #2716] @ 0xa9c │ │ ldrbeq r6, [r5, #2788] @ 0xae4 │ │ ldrbeq r6, [r5, #2772] @ 0xad4 │ │ ldrbeq r7, [r5, #2680] @ 0xa78 │ │ ldrbeq r6, [r5, #2820] @ 0xb04 │ │ eoreq fp, r7, ip, lsl #15 │ │ ldrdeq fp, [r7], -r8 @ │ │ - ldc2l 12, cr7, [r4, #144] @ 0x90 │ │ - ldc2l 5, cr2, [r4, #136] @ 0x88 │ │ + ldc2l 12, cr7, [r4, #324] @ 0x144 │ │ + ldc2l 5, cr2, [r4, #316] @ 0x13c │ │ eoreq fp, r7, ip, lsr r6 │ │ ldrbeq r6, [r5, #2496] @ 0x9c0 │ │ - ldc2l 3, cr5, [r5, #888] @ 0x378 │ │ - ldc2l 4, cr2, [r4, #936] @ 0x3a8 │ │ + ldc2l 4, cr5, [r5, #44] @ 0x2c │ │ + ldc2l 5, cr2, [r4, #92] @ 0x5c │ │ ldc2l 7, cr9, [pc, #176] @ 24e00dc │ │ eoreq fp, r7, r8, lsl r6 │ │ ldrbeq r6, [r5, #1892] @ 0x764 │ │ ldrbeq r6, [r5, #2348] @ 0x92c │ │ ldrbeq r7, [r5, #1872] @ 0x750 │ │ strdeq fp, [r7], -ip @ │ │ ldrbeq r7, [r5, #1820] @ 0x71c │ │ @@ -1467661,66 +1467661,66 @@ │ │ ldrbeq r7, [r5, #1768] @ 0x6e8 │ │ ldrbeq r6, [r5, #2268] @ 0x8dc │ │ ldrbeq r7, [r5, #2060] @ 0x80c │ │ ldrbeq r7, [r5, #108] @ 0x6c │ │ ldrbeq r8, [r5, #52] @ 0x34 │ │ ldrbeq r8, [r5, #268] @ 0x10c │ │ ldrbeq r7, [r5, #60] @ 0x3c │ │ - ldc2l 9, cr12, [r3, #250] @ 0xfa @ │ │ + ldc2l 9, cr12, [r3, #340] @ 0x154 @ │ │ ldc2l 1, cr3, [r6, #24] │ │ ldrbeq r7, [r5, #1872] @ 0x750 │ │ ldrbeq r6, [r5, #1540] @ 0x604 │ │ ldrbeq r6, [r5, #2084] @ 0x824 │ │ ldrbeq r7, [r5, #1792] @ 0x700 │ │ ldrbeq r7, [r5, #1768] @ 0x6e8 │ │ ldrbeq r7, [r5, #152] @ 0x98 │ │ ldrbeq r7, [r5, #1496] @ 0x5d8 │ │ - ldc2l 0, cr8, [r4, #524] @ 0x20c │ │ - ldc2l 1, cr2, [r4, #904] @ 0x388 │ │ + ldc2l 0, cr8, [r4, #704] @ 0x2c0 │ │ + ldc2l 2, cr2, [r4, #60] @ 0x3c │ │ ldrbeq r6, [r5, #3932] @ 0xf5c │ │ ldrbeq r7, [r5, #1180] @ 0x49c │ │ ldrbeq r7, [r5, #1396] @ 0x574 │ │ ldc2l 2, cr9, [r6, #408] @ 0x198 │ │ - ldc2l 1, cr2, [r4, #600] @ 0x258 │ │ + ldc2l 1, cr2, [r4, #780] @ 0x30c │ │ ldc2l 3, cr9, [r6, #408] @ 0x198 │ │ - ldc2l 2, cr2, [r4, #600] @ 0x258 │ │ + ldc2l 2, cr2, [r4, #780] @ 0x30c │ │ ldrbeq r6, [r5, #1608] @ 0x648 │ │ ldrbeq r7, [r5, #1220] @ 0x4c4 │ │ ldrbeq r6, [r5, #1296] @ 0x510 │ │ ldrbeq r7, [r5, #1540] @ 0x604 │ │ - ldc2l 0, cr8, [r4, #780] @ 0x30c │ │ - ldc2l 2, cr2, [r4, #136] @ 0x88 │ │ + ldc2l 0, cr8, [r4, #960] @ 0x3c0 │ │ + ldc2l 2, cr2, [r4, #316] @ 0x13c │ │ ldrbeq r6, [r5, #3992] @ 0xf98 │ │ ldrbeq r7, [r5, #1244] @ 0x4dc │ │ ldc2l 15, cr9, [r6, #456] @ 0x1c8 │ │ - ldc2l 14, cr2, [r4, #648] @ 0x288 │ │ + ldc2l 14, cr2, [r4, #828] @ 0x33c │ │ ldrbeq r8, [r5, #584] @ 0x248 │ │ ldrbeq r7, [r5, #848] @ 0x350 │ │ ldc2l 15, cr9, [r6, #216] @ 0xd8 │ │ - ldc2l 14, cr2, [r4, #408] @ 0x198 │ │ + ldc2l 14, cr2, [r4, #588] @ 0x24c │ │ ldrbeq r7, [r5, #236] @ 0xec │ │ ldrbeq r7, [r5, #732] @ 0x2dc │ │ ldrbeq r6, [r5, #4000] @ 0xfa0 │ │ ldrbeq r7, [r5, #3992] @ 0xf98 │ │ ldrbeq r6, [r5, #3948] @ 0xf6c │ │ eoreq fp, r7, ip, lsr lr │ │ ldrbeq r8, [r5, #168] @ 0xa8 │ │ ldrbeq r7, [r5, #236] @ 0xec │ │ ldrbeq r7, [r5, #220] @ 0xdc │ │ ldrbeq r8, [r5, #128] @ 0x80 │ │ eoreq fp, r7, r4, lsr #27 │ │ ldrbeq r7, [r5, #132] @ 0x84 │ │ ldrbeq r7, [r5, #3732] @ 0xe94 │ │ ldrdeq fp, [r7], -r0 @ │ │ - ldc2l 0, cr8, [r4, #240] @ 0xf0 │ │ - ldc2l 9, cr2, [r4, #116] @ 0x74 @ │ │ + ldc2l 0, cr8, [r4, #420] @ 0x1a4 │ │ + ldc2l 9, cr2, [r4, #206] @ 0xce @ │ │ eoreq fp, r7, r4, asr sl │ │ ldrbeq r6, [r5, #3544] @ 0xdd8 │ │ - ldc2l 7, cr5, [r5, #984] @ 0x3d8 │ │ - ldc2l 9, cr2, [r4, #4] @ │ │ + vcadd.f32 d21, d5, d19, #270 │ │ + ldc2l 9, cr2, [r4, #94] @ 0x5e @ │ │ ldc2l 11, cr9, [pc, #256] @ 24e0238 @ │ │ eoreq fp, r7, r0, lsr sl │ │ ldrbeq r7, [r5, #2896] @ 0xb50 │ │ ldrbeq r6, [r5, #2848] @ 0xb20 │ │ eoreq fp, r7, r4, lsl #20 │ │ ldrbeq r6, [r5, #2884] @ 0xb44 │ │ ldrbeq r7, [r5, #3152] @ 0xc50 │ │ @@ -1467728,21 +1467728,21 @@ │ │ ldrbeq r7, [r5, #2832] @ 0xb10 │ │ ldrbeq r6, [r5, #3280] @ 0xcd0 │ │ ldrbeq r7, [r5, #3656] @ 0xe48 │ │ ldrbeq r6, [r5, #3604] @ 0xe14 │ │ ldrbeq r7, [r5, #2292] @ 0x8f4 │ │ ldrbeq r7, [r5, #3848] @ 0xf08 │ │ ldrbeq r7, [r5, #3592] @ 0xe08 │ │ - ldc2l 6, cr8, [r4, #268] @ 0x10c │ │ - ldc2l 7, cr2, [r4, #648] @ 0x288 │ │ + ldc2l 6, cr8, [r4, #448] @ 0x1c0 │ │ + ldc2l 7, cr2, [r4, #828] @ 0x33c │ │ ldrbeq r7, [r5, #2888] @ 0xb48 │ │ ldrbeq r7, [r5, #2508] @ 0x9cc │ │ ldrbeq r6, [r5, #2584] @ 0xa18 │ │ ldc2l 8, cr9, [r6, #72] @ 0x48 │ │ - ldc2l 7, cr2, [r4, #264] @ 0x108 │ │ + ldc2l 7, cr2, [r4, #444] @ 0x1bc │ │ ldrbeq r6, [r5, #3056] @ 0xbf0 │ │ ldrbeq r7, [r5, #2804] @ 0xaf4 │ │ ldc2l 4, cr3, [r6, #552] @ 0x228 │ │ ldrbeq r6, [r5, #2564] @ 0xa04 │ │ │ │ 024e0198 : │ │ ldr r3, [r1] │ │ @@ -1467868,17 +1467868,17 @@ │ │ vldr d16, [r4] │ │ vadd.f64 d16, d8, d16 │ │ vstr d16, [r4] │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ vpop {d8-d9} │ │ pop {r4, r5, fp, pc} │ │ - ldc2l 13, cr1, [r4, #584] @ 0x248 │ │ + ldc2l 13, cr1, [r4, #764] @ 0x2fc │ │ ldc2l 8, cr0, [r7, #628] @ 0x274 │ │ - ldc2l 2, cr13, [r3, #96] @ 0x60 │ │ + ldc2l 2, cr13, [r3, #276] @ 0x114 │ │ │ │ 024e0398 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d10} │ │ sub sp, sp, #24 │ │ @@ -1468147,15 +1468147,15 @@ │ │ mrccc 5, 6, r6, cr12, cr15, {7} │ │ vmovcc.s8 r0, d31[2] │ │ @ instruction: 0xbdfefbe8 │ │ ldrb lr, [r1, pc, ror #31]! │ │ svccc 0x00f00b36 │ │ ldc2l 13, cr9, [r3, #48] @ 0x30 │ │ ldc2l 9, cr9, [r3, #462] @ 0x1ce @ │ │ - ldc2l 7, cr2, [r4, #932] @ 0x3a4 │ │ + ldc2l 8, cr2, [r4, #88] @ 0x58 │ │ ldc2l 1, cr1, [r6, #76] @ 0x4c │ │ ldc2l 9, cr9, [r3, #344] @ 0x158 @ │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ │ │ 024e07f0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -1468901,16 +1468901,16 @@ │ │ mov r0, #0 │ │ sub sp, fp, #96 @ 0x60 │ │ vpop {d8-d15} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldmibls r9, {r1, r3, r4, r7, r8, fp, ip, pc} │ │ svccc 0x00c99999 │ │ - ldc2l 2, cr11, [r4, #632] @ 0x278 │ │ - ldc2l 13, cr10, [r4, #760] @ 0x2f8 │ │ + ldc2l 2, cr11, [r4, #812] @ 0x32c │ │ + ldc2l 13, cr10, [r4, #940] @ 0x3ac │ │ │ │ 024e13a0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d15} │ │ sub sp, sp, #120 @ 0x78 │ │ @@ -1471054,59 +1471054,59 @@ │ │ ldrbeq r4, [r5, #1592] @ 0x638 │ │ ldrdeq r8, [r7], -ip @ │ │ ldrbeq r4, [r5, #1540] @ 0x604 │ │ mlaeq r7, r8, r1, r8 │ │ ldrbeq r4, [r5, #1540] @ 0x604 │ │ ldrbeq r4, [r5, #1032] @ 0x408 │ │ ldrbeq r4, [r5, #1460] @ 0x5b4 │ │ - ldc2l 6, cr2, [r4, #608] @ 0x260 │ │ + ldc2l 6, cr2, [r4, #788] @ 0x314 │ │ ldrbeq r4, [r5, #932] @ 0x3a4 │ │ ldrbeq r4, [r5, #1468] @ 0x5bc │ │ ldrbeq r4, [r5, #1300] @ 0x514 │ │ ldrbeq r4, [r5, #924] @ 0x39c │ │ ldrbeq r4, [r5, #1396] @ 0x574 │ │ ldrbeq r4, [r5, #1380] @ 0x564 │ │ ldrbeq r4, [r5, #1360] @ 0x550 │ │ ldc2l 15, cr9, [r6, #792] @ 0x318 │ │ - ldc2l 12, cr15, [r3, #820] @ 0x334 │ │ + ldc2l 12, cr15, [r3, #1000] @ 0x3e8 │ │ ldc2l 15, cr1, [r3, #828] @ 0x33c │ │ ldrbeq r4, [r5, #1336] @ 0x538 │ │ ldrbeq r4, [r5, #1240] @ 0x4d8 │ │ ldrbeq r4, [r5, #792] @ 0x318 │ │ ldrbeq r4, [r5, #1324] @ 0x52c │ │ ldrbeq r4, [r5, #796] @ 0x31c │ │ ldrbeq r4, [r5, #768] @ 0x300 │ │ ldc2l 15, cr9, [r6, #552] @ 0x228 │ │ - ldc2l 12, cr15, [r3, #580] @ 0x244 │ │ + ldc2l 12, cr15, [r3, #760] @ 0x2f8 │ │ ldc2l 7, cr8, [r5, #716] @ 0x2cc │ │ ldrbeq r4, [r5, #740] @ 0x2e4 │ │ ldrbeq r4, [r5, #1248] @ 0x4e0 │ │ - ldc2l 4, cr2, [r4, #832] @ 0x340 │ │ + ldc2l 4, cr2, [r4, #1012] @ 0x3f4 │ │ ldrbeq r4, [r5, #540] @ 0x21c │ │ ldrbeq r4, [r5, #1048] @ 0x418 │ │ ldrbeq r4, [r5, #892] @ 0x37c │ │ ldrbeq r4, [r5, #940] @ 0x3ac │ │ ldrbeq r4, [r5, #944] @ 0x3b0 │ │ ldrbeq r4, [r5, #892] @ 0x37c │ │ ldrbeq r4, [r5, #892] @ 0x37c │ │ - ldc2l 4, cr2, [r4, #48] @ 0x30 │ │ + ldc2l 4, cr2, [r4, #228] @ 0xe4 │ │ ldrbeq r4, [r5, #424] @ 0x1a8 │ │ ldrbeq r4, [r5, #812] @ 0x32c │ │ ldrbeq r4, [r5, #812] @ 0x32c │ │ ldrbeq r4, [r5, #240] @ 0xf0 │ │ ldrbeq r4, [r5, #716] @ 0x2cc │ │ ldrbeq r4, [r5, #228] @ 0xe4 │ │ ldrbeq r4, [r5, #712] @ 0x2c8 │ │ ldrbeq r4, [r5, #704] @ 0x2c0 │ │ ldrbeq r4, [r5, #112] @ 0x70 │ │ ldrbeq r4, [r5, #684] @ 0x2ac │ │ ldrbeq r4, [r5, #296] @ 0x128 │ │ ldrbeq r4, [r5, #112] @ 0x70 │ │ ldrbeq r4, [r5, #612] @ 0x264 │ │ - ldc2l 15, cr15, [r4, #80] @ 0x50 │ │ + ldc2l 15, cr15, [r4, #260] @ 0x104 │ │ ldc2l 3, cr14, [r5, #620] @ 0x26c │ │ ldrbeq r4, [r5, #76] @ 0x4c │ │ ldrbeq r4, [r5, #104] @ 0x68 │ │ ldrbeq r3, [r5, #4064] @ 0xfe0 │ │ eoreq r7, r7, ip, asr #26 │ │ ldc2l 7, cr14, [r5, #184] @ 0xb8 │ │ │ │ @@ -1471262,16 +1471262,16 @@ │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 11, cr5, [r6, #180] @ 0xb4 @ │ │ ldrbeq r4, [r5, #176] @ 0xb0 │ │ strdeq r7, [r7], -r0 @ │ │ strhteq r7, [r7], -r4 │ │ ldrbeq r4, [r5, #72] @ 0x48 │ │ ldc2l 7, cr2, [r3, #812] @ 0x32c │ │ - ldc2l 7, cr15, [r3, #292] @ 0x124 │ │ - ldc2l 4, cr10, [r3, #516] @ 0x204 │ │ + ldc2l 7, cr15, [r3, #472] @ 0x1d8 │ │ + ldc2l 4, cr10, [r3, #696] @ 0x2b8 │ │ ldrbeq r4, [r5, #12] │ │ ldrbeq r3, [r5, #4076] @ 0xfec │ │ ldrbeq r3, [r5, #4032] @ 0xfc0 │ │ ldrbeq r3, [r5, #3964] @ 0xf7c │ │ strhteq r7, [r7], -ip │ │ eoreq r7, r7, r0, asr #21 │ │ eoreq r7, r7, r4, ror #20 │ │ @@ -1471435,21 +1471435,21 @@ │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 7, cr1, [r6, #1016] @ 0x3f8 │ │ ldrbeq r3, [r5, #3624] @ 0xe28 │ │ eoreq r7, r7, r4, ror r9 │ │ eoreq r7, r7, r8, lsr r9 │ │ ldrbeq r3, [r5, #3516] @ 0xdbc │ │ ldrbeq r3, [r5, #3512] @ 0xdb8 │ │ - ldc2l 2, cr10, [r3, #1012] @ 0x3f4 │ │ - ldc2l 5, cr15, [r3, #452] @ 0x1c4 │ │ - ldc2l 9, cr13, [r4, #422] @ 0x1a6 @ │ │ - ldc2l 3, cr12, [r4, #568] @ 0x238 │ │ + ldc2l 3, cr10, [r3, #168] @ 0xa8 │ │ + ldc2l 5, cr15, [r3, #632] @ 0x278 │ │ + ldc2l 10, cr13, [r4] @ │ │ + ldc2l 3, cr12, [r4, #748] @ 0x2ec │ │ ldc2l 4, cr2, [r3, #828] @ 0x33c │ │ - ldc2l 4, cr15, [r3, #308] @ 0x134 │ │ - ldc2l 1, cr10, [r3, #532] @ 0x214 │ │ + ldc2l 4, cr15, [r3, #488] @ 0x1e8 │ │ + ldc2l 1, cr10, [r3, #712] @ 0x2c8 │ │ ldrbeq r3, [r5, #3284] @ 0xcd4 │ │ ldrbeq r3, [r5, #3248] @ 0xcb0 │ │ ldc2l 5, cr1, [r6, #872] @ 0x368 │ │ │ │ 024e3b28 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -1471778,74 +1471778,74 @@ │ │ ldr r3, [fp, #12] │ │ add r1, pc, r1 │ │ add r2, pc, r2 │ │ str r3, [sp] │ │ mov r3, r2 │ │ bl 270e810 │ │ b 24e3c74 │ │ - ldc2l 14, cr13, [r4, #132] @ 0x84 │ │ + ldc2l 14, cr13, [r4, #312] @ 0x138 │ │ ldrbeq r3, [r5, #2944] @ 0xb80 │ │ ldrbeq r3, [r5, #3412] @ 0xd54 │ │ strhteq r7, [r7], -r0 │ │ ldrbeq r3, [r5, #3360] @ 0xd20 │ │ eoreq r7, r7, ip, ror #12 │ │ ldrbeq r3, [r5, #3360] @ 0xd20 │ │ ldrbeq r3, [r5, #2852] @ 0xb24 │ │ ldrbeq r3, [r5, #3280] @ 0xcd0 │ │ - ldc2l 11, cr1, [r4, #240] @ 0xf0 @ │ │ + ldc2l 11, cr1, [r4, #420] @ 0x1a4 @ │ │ ldrbeq r3, [r5, #2752] @ 0xac0 │ │ ldrbeq r3, [r5, #3288] @ 0xcd8 │ │ ldrbeq r3, [r5, #3120] @ 0xc30 │ │ ldrbeq r3, [r5, #2744] @ 0xab8 │ │ ldrbeq r3, [r5, #3216] @ 0xc90 │ │ ldrbeq r3, [r5, #3200] @ 0xc80 │ │ ldrbeq r3, [r5, #3180] @ 0xc6c │ │ ldc2l 4, cr9, [r6, #424] @ 0x1a8 │ │ - ldc2l 1, cr15, [r3, #452] @ 0x1c4 │ │ + ldc2l 1, cr15, [r3, #632] @ 0x278 │ │ ldc2l 4, cr1, [r3, #460] @ 0x1cc │ │ ldrbeq r3, [r5, #3156] @ 0xc54 │ │ ldrbeq r3, [r5, #3060] @ 0xbf4 │ │ ldrbeq r3, [r5, #2612] @ 0xa34 │ │ ldrbeq r3, [r5, #3144] @ 0xc48 │ │ ldrbeq r3, [r5, #2616] @ 0xa38 │ │ ldrbeq r3, [r5, #2588] @ 0xa1c │ │ ldc2l 4, cr9, [r6, #184] @ 0xb8 │ │ - ldc2l 1, cr15, [r3, #212] @ 0xd4 │ │ + ldc2l 1, cr15, [r3, #392] @ 0x188 │ │ ldc2l 12, cr7, [r5, #348] @ 0x15c │ │ ldrbeq r3, [r5, #2560] @ 0xa00 │ │ ldrbeq r3, [r5, #3068] @ 0xbfc │ │ - ldc2l 9, cr1, [r4, #232] @ 0xe8 @ │ │ + ldc2l 9, cr1, [r4, #322] @ 0x142 @ │ │ ldrbeq r3, [r5, #2360] @ 0x938 │ │ ldrbeq r3, [r5, #2868] @ 0xb34 │ │ ldrbeq r3, [r5, #2712] @ 0xa98 │ │ ldrbeq r3, [r5, #2760] @ 0xac8 │ │ ldrbeq r3, [r5, #2764] @ 0xacc │ │ ldrbeq r3, [r5, #2712] @ 0xa98 │ │ ldrbeq r3, [r5, #2712] @ 0xa98 │ │ - ldc2l 8, cr1, [r4, #704] @ 0x2c0 │ │ + ldc2l 8, cr1, [r4, #884] @ 0x374 │ │ ldrbeq r3, [r5, #2244] @ 0x8c4 │ │ ldrbeq r3, [r5, #2632] @ 0xa48 │ │ ldrbeq r3, [r5, #2632] @ 0xa48 │ │ ldrbeq r3, [r5, #2060] @ 0x80c │ │ ldrbeq r3, [r5, #2536] @ 0x9e8 │ │ ldrbeq r3, [r5, #2048] @ 0x800 │ │ ldrbeq r3, [r5, #2532] @ 0x9e4 │ │ ldrbeq r3, [r5, #2524] @ 0x9dc │ │ ldrbeq r3, [r5, #1932] @ 0x78c │ │ ldrbeq r3, [r5, #2504] @ 0x9c8 │ │ ldrbeq r3, [r5, #2116] @ 0x844 │ │ ldrbeq r3, [r5, #1932] @ 0x78c │ │ ldrbeq r3, [r5, #2432] @ 0x980 │ │ - ldc2l 3, cr15, [r4, #736] @ 0x2e0 │ │ + ldc2l 3, cr15, [r4, #916] @ 0x394 │ │ ldc2l 5, cr15, [r5, #552] @ 0x228 │ │ ldrbeq r3, [r5, #1896] @ 0x768 │ │ ldrbeq r3, [r5, #1924] @ 0x784 │ │ ldrbeq r3, [r5, #1788] @ 0x6fc │ │ eoreq r7, r7, r0, lsr #4 │ │ - ldc2l 13, cr13, [r4, #36] @ 0x24 │ │ + ldc2l 13, cr13, [r4, #216] @ 0xd8 │ │ │ │ 024e4144 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #300 @ 0x12c │ │ mov r5, r3 │ │ mov r4, r2 │ │ @@ -1471989,30 +1471989,30 @@ │ │ ldr r0, [pc, #80] @ 24e43d4 │ │ mov r1, #8 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 5, cr15, [r4, #844] @ 0x34c │ │ + ldc2l 6, cr15, [r4] │ │ ldrbeq r3, [r5, #1996] @ 0x7cc │ │ eoreq r7, r7, r4, asr #1 │ │ eoreq r7, r7, r8, lsl #1 │ │ ldrbeq r3, [r5, #1892] @ 0x764 │ │ ldc2l 12, cr1, [r3, #444] @ 0x1bc │ │ - ldc2l 11, cr14, [r3, #948] @ 0x3b4 @ │ │ - ldc2l 9, cr9, [r3, #74] @ 0x4a @ │ │ + ldc2l 12, cr14, [r3, #104] @ 0x68 │ │ + ldc2l 9, cr9, [r3, #164] @ 0xa4 @ │ │ ldrbeq r3, [r5, #1832] @ 0x728 │ │ ldrbeq r3, [r5, #1800] @ 0x708 │ │ ldrbeq r3, [r5, #1756] @ 0x6dc │ │ ldrbeq r3, [r5, #1688] @ 0x698 │ │ mlaeq r7, r0, pc, r6 @ │ │ mlaeq r7, r4, pc, r6 @ │ │ eoreq r6, r7, r8, lsr pc │ │ - ldc2l 3, cr15, [r4, #796] @ 0x31c │ │ + ldc2l 3, cr15, [r4, #976] @ 0x3d0 │ │ │ │ 024e43d8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #188 @ 0xbc │ │ mov r4, r3 │ │ mov r6, r2 │ │ @@ -1472168,21 +1472168,21 @@ │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 6, cr7, [r5, #240] @ 0xf0 │ │ ldrbeq r3, [r5, #1348] @ 0x544 │ │ eoreq r6, r7, r8, asr #28 │ │ eoreq r6, r7, ip, lsl #28 │ │ ldrbeq r3, [r5, #1240] @ 0x4d8 │ │ ldrbeq r3, [r5, #1236] @ 0x4d4 │ │ - ldc2l 7, cr9, [r3, #644] @ 0x284 │ │ - ldc2l 10, cr14, [r3, #84] @ 0x54 @ │ │ - ldc2l 14, cr12, [r4, #476] @ 0x1dc │ │ - ldc2l 8, cr11, [r4, #200] @ 0xc8 │ │ + ldc2l 7, cr9, [r3, #824] @ 0x338 │ │ + ldc2l 10, cr14, [r3, #264] @ 0x108 @ │ │ + ldc2l 14, cr12, [r4, #656] @ 0x290 │ │ + ldc2l 8, cr11, [r4, #380] @ 0x17c │ │ ldc2l 9, cr1, [r3, #230] @ 0xe6 @ │ │ - ldc2l 8, cr14, [r3, #964] @ 0x3c4 │ │ - ldc2l 6, cr9, [r3, #164] @ 0xa4 │ │ + ldc2l 9, cr14, [r3, #60] @ 0x3c @ │ │ + ldc2l 6, cr9, [r3, #344] @ 0x158 │ │ ldrbeq r3, [r5, #1008] @ 0x3f0 │ │ ldrbeq r3, [r5, #972] @ 0x3cc │ │ ldc2l 4, cr7, [r5, #96] @ 0x60 │ │ │ │ 024e4684 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -1473287,15 +1473287,15 @@ │ │ bl 270e800 │ │ ldr r1, [sp, #24] │ │ add r2, r4, #24 │ │ mov r0, r9 │ │ add r4, sp, #688 @ 0x2b0 │ │ bl 270e800 │ │ b 24e5888 │ │ - ldc2l 13, cr10, [r4, #244] @ 0xf4 │ │ + ldc2l 13, cr10, [r4, #424] @ 0x1a8 │ │ ldc2l 1, cr6, [r6, #764] @ 0x2fc │ │ ldc2l 10, cr10, [r5, #416] @ 0x1a0 @ │ │ ldr r0, [sp, #584] @ 0x248 │ │ sub r0, r0, #1 │ │ cmp r0, #20 │ │ bhi 24e58dc │ │ cmp r5, #0 │ │ @@ -1473542,96 +1473542,96 @@ │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldr r0, [pc, #24] @ 24e5bd8 │ │ mov r1, #137 @ 0x89 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ b 24e5708 │ │ - ldc2l 9, cr10, [r4, #106] @ 0x6a @ │ │ - ldc2l 10, cr2, [r4, #120] @ 0x78 @ │ │ + ldc2l 9, cr10, [r4, #196] @ 0xc4 @ │ │ + ldc2l 10, cr2, [r4, #300] @ 0x12c @ │ │ ldc2l 7, cr1, [r3, #492] @ 0x1ec │ │ ldc2l 4, cr11, [r5, #528] @ 0x210 │ │ ldc2l 1, cr5, [r6, #988] @ 0x3dc │ │ - vcadd.f32 d29, d3, d1, #270 │ │ + vcadd.f32 d29, d3, d30, #270 │ │ ldc2l 11, cr15, [r2, #12] @ │ │ ldc2l 13, cr11, [r5, #436] @ 0x1b4 │ │ ldc2l 7, cr3, [r3, #444] @ 0x1bc │ │ eoreq r6, r7, ip, ror r5 │ │ eoreq r6, r7, r4, lsl #9 │ │ strdeq r6, [r7], -ip @ │ │ ldc2l 7, cr3, [r6, #464] @ 0x1d0 │ │ ldrbeq r2, [r5, #1380] @ 0x564 │ │ - ldc2l 2, cr4, [r4, #388] @ 0x184 │ │ - ldc2l 10, cr13, [r3, #564] @ 0x234 @ │ │ + ldc2l 2, cr4, [r4, #568] @ 0x238 │ │ + ldc2l 10, cr13, [r3, #744] @ 0x2e8 @ │ │ ldc2l 5, cr3, [r6, #912] @ 0x390 │ │ ldrbeq r2, [r5, #980] @ 0x3d4 │ │ - ldc2l 0, cr4, [r4, #836] @ 0x344 │ │ - ldc2l 8, cr13, [r3, #1012] @ 0x3f4 │ │ - ldc2l 1, cr10, [r3, #208] @ 0xd0 │ │ + ldc2l 0, cr4, [r4, #1016] @ 0x3f8 │ │ + ldc2l 9, cr13, [r3, #84] @ 0x54 @ │ │ + ldc2l 1, cr10, [r3, #388] @ 0x184 │ │ ldc2l 13, cr15, [r2, #692] @ 0x2b4 │ │ - ldc2l 15, cr7, [r4, #360] @ 0x168 │ │ - ldc2l 8, cr13, [r3, #468] @ 0x1d4 │ │ - ldc2l 0, cr4, [r4, #108] @ 0x6c │ │ + ldc2l 15, cr7, [r4, #540] @ 0x21c │ │ + vcadd.f32 d29, d19, d18, #270 │ │ + ldc2l 0, cr4, [r4, #288] @ 0x120 │ │ ldc2l 1, cr12, [r5, #740] @ 0x2e4 │ │ - ldc2l 6, cr10, [r4, #548] @ 0x224 │ │ + ldc2l 6, cr10, [r4, #728] @ 0x2d8 │ │ ldc2l 4, cr3, [r3, #780] @ 0x30c │ │ - ldc2l 5, cr10, [r4, #484] @ 0x1e4 │ │ + ldc2l 5, cr10, [r4, #664] @ 0x298 │ │ ldc2l 3, cr3, [r3, #892] @ 0x37c │ │ ldc2l 1, cr3, [r3, #652] @ 0x28c │ │ ldc2l 7, cr5, [r6, #988] @ 0x3dc │ │ ldc2l 1, cr3, [r3, #556] @ 0x22c │ │ ldc2l 11, cr5, [r6, #76] @ 0x4c @ │ │ strhteq r6, [r7], -ip │ │ ldc2l 10, cr5, [r6, #860] @ 0x35c @ │ │ eoreq r6, r7, r4, ror r0 │ │ ldc2l 15, cr2, [r3, #860] @ 0x35c │ │ - ldc2l 5, cr10, [r4, #292] @ 0x124 │ │ + ldc2l 5, cr10, [r4, #472] @ 0x1d8 │ │ ldc2l 3, cr3, [r3, #524] @ 0x20c │ │ - ldc2l 5, cr10, [r4, #100] @ 0x64 │ │ + ldc2l 5, cr10, [r4, #280] @ 0x118 │ │ ldc2l 0, cr3, [r3, #716] @ 0x2cc │ │ - ldc2l 4, cr10, [r4, #900] @ 0x384 │ │ + ldc2l 5, cr10, [r4, #56] @ 0x38 │ │ ldc2l 3, cr3, [r3, #108] @ 0x6c │ │ - ldc2l 4, cr10, [r4, #708] @ 0x2c4 │ │ - ldc2l 4, cr10, [r4, #548] @ 0x224 │ │ - ldc2l 2, cr10, [r4, #324] @ 0x144 │ │ + ldc2l 4, cr10, [r4, #888] @ 0x378 │ │ + ldc2l 4, cr10, [r4, #728] @ 0x2d8 │ │ + ldc2l 2, cr10, [r4, #504] @ 0x1f8 │ │ ldc2l 6, cr5, [r6, #748] @ 0x2ec │ │ ldc2l 6, cr5, [r6, #524] @ 0x20c │ │ ldc2l 6, cr5, [r6, #92] @ 0x5c │ │ eoreq r5, r7, r0, asr #29 │ │ ldc2l 5, cr5, [r6, #876] @ 0x36c │ │ - ldc2l 4, cr10, [r4, #324] @ 0x144 │ │ - ldc2l 4, cr10, [r4, #196] @ 0xc4 │ │ + ldc2l 4, cr10, [r4, #504] @ 0x1f8 │ │ + ldc2l 4, cr10, [r4, #376] @ 0x178 │ │ vcadd.f32 d21, d22, d11, #270 │ │ eoreq r6, r7, r0, lsr r1 │ │ ldc2l 7, cr5, [r6, #572] @ 0x23c │ │ ldc2l 1, cr3, [r3, #140] @ 0x8c │ │ ldc2l 7, cr5, [r6, #364] @ 0x16c │ │ ldc2l 0, cr3, [r3, #956] @ 0x3bc │ │ - ldc2l 5, cr10, [r4, #948] @ 0x3b4 │ │ + ldc2l 6, cr10, [r4, #104] @ 0x68 │ │ ldc2l 4, cr3, [r3, #156] @ 0x9c │ │ ldc2l 4, cr5, [r6, #476] @ 0x1dc │ │ ldc2l 14, cr2, [r3, #44] @ 0x2c │ │ eoreq r5, r7, r8, lsl sp │ │ - ldc2l 0, cr10, [r4, #52] @ 0x34 │ │ + ldc2l 0, cr10, [r4, #232] @ 0xe8 │ │ ldc2l 14, cr2, [r3, #284] @ 0x11c │ │ - ldc2l 13, cr9, [r4, #836] @ 0x344 │ │ + ldc2l 13, cr9, [r4, #1016] @ 0x3f8 │ │ ldc2l 12, cr2, [r3, #44] @ 0x2c │ │ eoreq r5, r7, r0, lsl sl │ │ ldc2l 1, cr5, [r6, #92] @ 0x5c │ │ ldc2l 10, cr2, [r3, #684] @ 0x2ac @ │ │ strhteq r5, [r7], -r8 │ │ - ldc2l 12, cr9, [r4, #132] @ 0x84 │ │ + ldc2l 12, cr9, [r4, #312] @ 0x138 │ │ ldc2l 10, cr2, [r3, #364] @ 0x16c @ │ │ - ldc2l 11, cr9, [r4, #980] @ 0x3d4 @ │ │ + ldc2l 12, cr9, [r4, #136] @ 0x88 │ │ ldc2l 10, cr2, [r3, #188] @ 0xbc @ │ │ - ldc2l 11, cr9, [r4, #804] @ 0x324 @ │ │ + ldc2l 11, cr9, [r4, #984] @ 0x3d8 @ │ │ ldc2l 10, cr2, [r3, #12] @ │ │ ldc2l 0, cr5, [r6, #220] @ 0xdc │ │ mlaeq r7, r8, r8, r5 │ │ - ldc2l 11, cr9, [r4, #100] @ 0x64 @ │ │ + ldc2l 11, cr9, [r4, #280] @ 0x118 @ │ │ ldc2l 9, cr2, [r3, #166] @ 0xa6 @ │ │ ldc2l 15, cr4, [r6, #428] @ 0x1ac │ │ ldc2l 8, cr2, [r3, #1020] @ 0x3fc │ │ eoreq r5, r7, ip, lsl #16 │ │ eoreq r5, r7, r4, lsr r7 │ │ eoreq r5, r7, r8, lsl r7 │ │ ldc2l 12, cr11, [r5, #820] @ 0x334 │ │ @@ -1474668,15 +1474668,15 @@ │ │ ldr r0, [pc, #1424] @ 24e72d8 │ │ mov r1, #20 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ ldr r0, [pc, #1412] @ 24e72dc │ │ add r0, pc, r0 │ │ b 24e7248 │ │ - ldc2l 2, cr4, [r4, #568] @ 0x238 │ │ + ldc2l 2, cr4, [r4, #748] @ 0x2ec │ │ ldrbeq r1, [r5, #3104] @ 0xc20 │ │ ldrbeq r1, [r5, #3120] @ 0xc30 │ │ eoreq r5, r7, r4, asr #9 │ │ ldr r1, [pc, #1292] @ 24e7280 │ │ mov r0, r8 │ │ mov r2, r5 │ │ mov r3, #1 │ │ @@ -1474698,15 +1474698,15 @@ │ │ mov r1, #19 │ │ add r0, pc, r0 │ │ bl 270da10 │ │ bl 270db90 │ │ cmp r0, #0 │ │ bne 24e719c │ │ b 24e5e44 │ │ - ldc2l 2, cr4, [r4, #152] @ 0x98 │ │ + ldc2l 2, cr4, [r4, #332] @ 0x14c │ │ ldrbeq r1, [r5, #3020] @ 0xbcc │ │ ldrbeq r1, [r5, #2981] @ 0xba5 │ │ ldrbeq r1, [r5, #3016] @ 0xbc8 │ │ eoreq r5, r7, r4, lsr r4 │ │ ldc2l 14, cr3, [r5, #104] @ 0x68 │ │ ldr r0, [pc, #1424] @ 24e7384 │ │ mov r1, sl │ │ @@ -1474740,15 +1474740,15 @@ │ │ bl 270e800 │ │ ldr r1, [sp, #24] │ │ add r2, r4, #24 │ │ mov r0, r9 │ │ add r4, sp, #688 @ 0x2b0 │ │ bl 270e800 │ │ b 24e6f34 │ │ - ldc2l 6, cr9, [r4, #580] @ 0x244 │ │ + ldc2l 6, cr9, [r4, #760] @ 0x2f8 │ │ ldc2l 11, cr4, [r6, #76] @ 0x4c @ │ │ ldc2l 3, cr9, [r5, #752] @ 0x2f0 │ │ ldr r0, [sp, #584] @ 0x248 │ │ sub r0, r0, #1 │ │ cmp r0, #20 │ │ bhi 24e6f88 │ │ cmp r5, #0 │ │ @@ -1474995,103 +1474995,103 @@ │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldr r0, [pc, #24] @ 24e7284 │ │ mov r1, #137 @ 0x89 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ b 24e6db4 │ │ - ldc2l 2, cr9, [r4, #548] @ 0x224 │ │ + ldc2l 2, cr9, [r4, #728] @ 0x2d8 │ │ ldc2l 7, cr1, [r3, #772] @ 0x304 │ │ ldc2l 0, cr0, [r3, #828] @ 0x33c │ │ ldc2l 13, cr9, [r5, #864] @ 0x360 │ │ ldc2l 11, cr3, [r6, #300] @ 0x12c @ │ │ - ldc2l 1, cr12, [r3, #340] @ 0x154 │ │ + ldc2l 1, cr12, [r3, #520] @ 0x208 │ │ ldc2l 4, cr14, [r2, #348] @ 0x15c │ │ - ldc2l 14, cr2, [r4, #376] @ 0x178 │ │ + ldc2l 14, cr2, [r4, #556] @ 0x22c │ │ ldc2l 9, cr3, [r5, #492] @ 0x1ec @ │ │ ldrdeq r4, [r7], -r4 @ │ │ ldrdeq r4, [r7], -ip @ │ │ eoreq r4, r7, r4, asr lr │ │ ldc2l 0, cr2, [r6, #800] @ 0x320 │ │ ldrbeq r0, [r5, #3820] @ 0xeec │ │ - ldc2l 11, cr2, [r4, #724] @ 0x2d4 @ │ │ - ldc2l 3, cr12, [r3, #900] @ 0x384 │ │ + ldc2l 11, cr2, [r4, #904] @ 0x388 @ │ │ + ldc2l 4, cr12, [r3, #56] @ 0x38 │ │ ldc2l 15, cr1, [r6, #224] @ 0xe0 │ │ ldrbeq r0, [r5, #3420] @ 0xd5c │ │ - ldc2l 10, cr2, [r4, #148] @ 0x94 @ │ │ - ldc2l 2, cr12, [r3, #324] @ 0x144 │ │ - ldc2l 10, cr8, [r3, #544] @ 0x220 @ │ │ + ldc2l 10, cr2, [r4, #328] @ 0x148 @ │ │ + ldc2l 2, cr12, [r3, #504] @ 0x1f8 │ │ + ldc2l 10, cr8, [r3, #724] @ 0x2d4 @ │ │ ldc2l 7, cr14, [r2, #4] │ │ - vcadd.f32 d22, d20, d30, #270 │ │ - ldc2l 1, cr12, [r3, #804] @ 0x324 │ │ - ldc2l 9, cr2, [r4, #222] @ 0xde @ │ │ - ldc2l 2, cr3, [r4, #680] @ 0x2a8 │ │ - ldc2l 15, cr8, [r4, #884] @ 0x374 │ │ + ldc2l 8, cr6, [r4, #876] @ 0x36c │ │ + ldc2l 1, cr12, [r3, #984] @ 0x3d8 │ │ + ldc2l 9, cr2, [r4, #312] @ 0x138 @ │ │ + ldc2l 2, cr3, [r4, #860] @ 0x35c │ │ + ldc2l 0, cr9, [r4, #40] @ 0x28 │ │ ldc2l 7, cr3, [r5, #296] @ 0x128 │ │ - ldc2l 14, cr8, [r4, #820] @ 0x334 │ │ + ldc2l 14, cr8, [r4, #1000] @ 0x3e8 │ │ ldc2l 6, cr3, [r5, #408] @ 0x198 │ │ ldc2l 4, cr3, [r5, #168] @ 0xa8 │ │ ldc2l 1, cr4, [r6, #300] @ 0x12c │ │ ldc2l 4, cr3, [r5, #72] @ 0x48 │ │ ldc2l 4, cr4, [r6, #412] @ 0x19c │ │ eoreq r4, r7, r4, lsl sp │ │ ldc2l 4, cr4, [r6, #172] @ 0xac │ │ eoreq r4, r7, ip, asr #19 │ │ ldc2l 2, cr3, [r5, #376] @ 0x178 │ │ - ldc2l 14, cr8, [r4, #628] @ 0x274 │ │ + ldc2l 14, cr8, [r4, #808] @ 0x328 │ │ ldc2l 6, cr3, [r5, #40] @ 0x28 │ │ - ldc2l 14, cr8, [r4, #436] @ 0x1b4 │ │ + ldc2l 14, cr8, [r4, #616] @ 0x268 │ │ ldc2l 3, cr3, [r5, #232] @ 0xe8 │ │ - ldc2l 14, cr8, [r4, #212] @ 0xd4 │ │ + ldc2l 14, cr8, [r4, #392] @ 0x188 │ │ ldc2l 5, cr3, [r5, #648] @ 0x288 │ │ - ldc2l 14, cr8, [r4, #20] │ │ - ldc2l 13, cr8, [r4, #884] @ 0x374 │ │ - ldc2l 11, cr8, [r4, #660] @ 0x294 @ │ │ + ldc2l 14, cr8, [r4, #200] @ 0xc8 │ │ + ldc2l 14, cr8, [r4, #40] @ 0x28 │ │ + ldc2l 11, cr8, [r4, #840] @ 0x348 @ │ │ ldc2l 0, cr4, [r6, #60] @ 0x3c │ │ ldc2l 15, cr3, [r6, #860] @ 0x35c │ │ ldc2l 15, cr3, [r6, #428] @ 0x1ac │ │ eoreq r4, r7, r8, lsl r8 │ │ ldc2l 15, cr3, [r6, #188] @ 0xbc │ │ - ldc2l 13, cr8, [r4, #660] @ 0x294 │ │ - ldc2l 13, cr8, [r4, #532] @ 0x214 │ │ + ldc2l 13, cr8, [r4, #840] @ 0x348 │ │ + ldc2l 13, cr8, [r4, #712] @ 0x2c8 │ │ ldc2l 1, cr4, [r6, #892] @ 0x37c │ │ eoreq r4, r7, r8, lsl #21 │ │ ldc2l 0, cr4, [r6, #908] @ 0x38c │ │ ldc2l 3, cr3, [r5, #680] @ 0x2a8 │ │ ldc2l 0, cr4, [r6, #700] @ 0x2bc │ │ ldc2l 3, cr3, [r5, #472] @ 0x1d8 │ │ - ldc2l 15, cr8, [r4, #260] @ 0x104 │ │ + ldc2l 15, cr8, [r4, #440] @ 0x1b8 │ │ ldc2l 6, cr3, [r5, #696] @ 0x2b8 │ │ ldc2l 13, cr3, [r6, #812] @ 0x32c │ │ ldc2l 0, cr3, [r5, #584] @ 0x248 │ │ eoreq r4, r7, r0, ror r6 │ │ - ldc2l 9, cr8, [r4, #194] @ 0xc2 @ │ │ + ldc2l 9, cr8, [r4, #284] @ 0x11c @ │ │ ldc2l 0, cr3, [r5, #824] @ 0x338 │ │ - ldc2l 7, cr8, [r4, #148] @ 0x94 │ │ + ldc2l 7, cr8, [r4, #328] @ 0x148 │ │ ldc2l 14, cr2, [r5, #584] @ 0x248 │ │ eoreq r4, r7, r8, ror #6 │ │ ldc2l 10, cr3, [r6, #428] @ 0x1ac @ │ │ ldc2l 13, cr2, [r5, #200] @ 0xc8 │ │ eoreq r4, r7, r0, lsl r3 │ │ - ldc2l 5, cr8, [r4, #468] @ 0x1d4 │ │ + ldc2l 5, cr8, [r4, #648] @ 0x288 │ │ ldc2l 12, cr2, [r5, #904] @ 0x388 │ │ - ldc2l 5, cr8, [r4, #292] @ 0x124 │ │ + ldc2l 5, cr8, [r4, #472] @ 0x1d8 │ │ ldc2l 12, cr2, [r5, #728] @ 0x2d8 │ │ - ldc2l 5, cr8, [r4, #116] @ 0x74 │ │ + ldc2l 5, cr8, [r4, #296] @ 0x128 │ │ ldc2l 12, cr2, [r5, #552] @ 0x228 │ │ ldc2l 9, cr3, [r6, #278] @ 0x116 @ │ │ strdeq r4, [r7], -r0 @ │ │ - ldc2l 4, cr8, [r4, #436] @ 0x1b4 │ │ + ldc2l 4, cr8, [r4, #616] @ 0x268 │ │ ldc2l 11, cr2, [r5, #872] @ 0x368 @ │ │ ldc2l 8, cr3, [r6, #764] @ 0x2fc │ │ ldc2l 11, cr2, [r5, #536] @ 0x218 @ │ │ eoreq r4, r7, r4, ror #2 │ │ eoreq r4, r7, ip, lsl #1 │ │ eoreq r4, r7, r0, ror r0 │ │ - ldc2l 13, cr2, [r4, #760] @ 0x2f8 │ │ + ldc2l 13, cr2, [r4, #940] @ 0x3ac │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ │ │ 024e73e0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d12} │ │ @@ -1475357,35 +1475357,35 @@ │ │ str r4, [sp] │ │ bl 270f0a0 │ │ b 24e75a8 │ │ @ instruction: 0x4646d497 │ │ stclcc 14, cr0, [r7], #-980 @ 0xfffffc2c │ │ @ instruction: 0xfff24190 │ │ svccc 0x00efffff │ │ - ldc2l 5, cr14, [r4, #144] @ 0x90 │ │ + ldc2l 5, cr14, [r4, #324] @ 0x144 │ │ ldrbeq r0, [r5, #1448] @ 0x5a8 │ │ eoreq r3, r7, r8, asr #28 │ │ eoreq r3, r7, ip, lsl #28 │ │ ldrbeq r0, [r5, #1340] @ 0x53c │ │ ldrbeq r0, [r5, #1340] @ 0x53c │ │ ldrbeq r0, [r5, #1332] @ 0x534 │ │ ldc2l 9, cr14, [r2, #486] @ 0x1e6 @ │ │ - ldc2l 9, cr11, [r3, #226] @ 0xe2 @ │ │ - ldc2l 6, cr6, [r3, #676] @ 0x2a4 │ │ + ldc2l 9, cr11, [r3, #316] @ 0x13c @ │ │ + ldc2l 6, cr6, [r3, #856] @ 0x358 │ │ ldrbeq r0, [r5, #1260] @ 0x4ec │ │ eoreq r3, r7, r4, ror sp │ │ ldrbeq r0, [r5, #1036] @ 0x40c │ │ ldrbeq r0, [r5, #1004] @ 0x3ec │ │ ldrbeq r0, [r5, #988] @ 0x3dc │ │ ldrbeq r0, [r5, #932] @ 0x3a4 │ │ eoreq r3, r7, r8, lsr ip │ │ - vcadd.f32 d18, d20, d15, #270 │ │ - ldc2l 13, cr5, [r3, #640] @ 0x280 │ │ + ldc2l 8, cr2, [r4, #752] @ 0x2f0 │ │ + ldc2l 13, cr5, [r3, #820] @ 0x334 │ │ ldrdeq r3, [r7], -r0 @ │ │ - ldc2l 3, cr14, [r4, #576] @ 0x240 │ │ + ldc2l 3, cr14, [r4, #756] @ 0x2f4 │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ │ │ 024e7870 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d12} │ │ @@ -1475651,35 +1475651,35 @@ │ │ str r4, [sp] │ │ bl 270f0a0 │ │ b 24e7a38 │ │ @ instruction: 0x4646d497 │ │ stclcc 14, cr0, [r7], #-980 @ 0xfffffc2c │ │ @ instruction: 0xfff24190 │ │ svccc 0x00efffff │ │ - ldc2l 2, cr6, [r4, #484] @ 0x1e4 │ │ + ldc2l 2, cr6, [r4, #664] @ 0x298 │ │ ldrbeq r0, [r5, #300] @ 0x12c │ │ ldrdeq r3, [r7], -r0 @ │ │ mlaeq r7, r4, r9, r3 │ │ ldrbeq r0, [r5, #192] @ 0xc0 │ │ ldrbeq r0, [r5, #192] @ 0xc0 │ │ ldrbeq r0, [r5, #184] @ 0xb8 │ │ ldc2l 5, cr14, [r2, #396] @ 0x18c │ │ - ldc2l 4, cr11, [r3, #900] @ 0x384 │ │ - ldc2l 2, cr6, [r3, #100] @ 0x64 │ │ + ldc2l 5, cr11, [r3, #56] @ 0x38 │ │ + ldc2l 2, cr6, [r3, #280] @ 0x118 │ │ ldrbeq r0, [r5, #112] @ 0x70 │ │ strdeq r3, [r7], -ip @ │ │ ldrbeq pc, [r4, #3984] @ 0xf90 @ │ │ ldrbeq pc, [r4, #3952] @ 0xf70 @ │ │ ldrbeq pc, [r4, #3936] @ 0xf60 @ │ │ ldrbeq pc, [r4, #3880] @ 0xf28 @ │ │ eoreq r3, r7, r0, asr #15 │ │ - ldc2l 3, cr2, [r4, #1020] @ 0x3fc │ │ - ldc2l 9, cr5, [r3, #32] @ │ │ + ldc2l 4, cr2, [r4, #176] @ 0xb0 │ │ + ldc2l 9, cr5, [r3, #122] @ 0x7a @ │ │ eoreq r3, r7, r8, asr r6 │ │ - ldc2l 0, cr6, [r4, #916] @ 0x394 │ │ + ldc2l 1, cr6, [r4, #72] @ 0x48 │ │ │ │ 024e7cfc : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #32 │ │ mov r7, r3 │ │ mov r4, r2 │ │ @@ -1476013,47 +1476013,47 @@ │ │ ldr r1, [pc, #188] @ 24e82e0 │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ bl 270e800 │ │ b 24e7f04 │ │ ldc2l 13, cr8, [r6, #628] @ 0x274 │ │ ldrbeq pc, [r4, #2996] @ 0xbb4 @ │ │ - ldc2l 9, cr13, [r3, #24] @ │ │ + ldc2l 9, cr13, [r3, #114] @ 0x72 @ │ │ ldrbeq pc, [r4, #2968] @ 0xb98 @ │ │ ldrbeq pc, [r4, #3176] @ 0xc68 @ │ │ ldc2l 3, cr1, [r3, #496] @ 0x1f0 │ │ ldrbeq pc, [r4, #2952] @ 0xb88 @ │ │ - ldc2l 13, cr11, [r3, #620] @ 0x26c │ │ + ldc2l 13, cr11, [r3, #800] @ 0x320 │ │ ldrbeq pc, [r4, #2980] @ 0xba4 @ │ │ ldrbeq pc, [r4, #2840] @ 0xb18 @ │ │ ldrbeq pc, [r4, #3000] @ 0xbb8 @ │ │ ldrbeq pc, [r4, #2984] @ 0xba8 @ │ │ ldrbeq pc, [r4, #2960] @ 0xb90 @ │ │ ldc2l 1, cr5, [r6, #728] @ 0x2d8 │ │ - ldc2l 14, cr10, [r3, #756] @ 0x2f4 │ │ + ldc2l 14, cr10, [r3, #936] @ 0x3a8 │ │ ldc2l 1, cr13, [r2, #764] @ 0x2fc │ │ ldrbeq pc, [r4, #2936] @ 0xb78 @ │ │ ldrbeq pc, [r4, #2912] @ 0xb60 @ │ │ ldrbeq pc, [r4, #2752] @ 0xac0 @ │ │ ldrbeq pc, [r4, #2920] @ 0xb68 @ │ │ ldrbeq pc, [r4, #2752] @ 0xac0 @ │ │ ldrbeq pc, [r4, #2724] @ 0xaa4 @ │ │ ldc2l 1, cr5, [r6, #488] @ 0x1e8 │ │ - ldc2l 14, cr10, [r3, #516] @ 0x204 │ │ + ldc2l 14, cr10, [r3, #696] @ 0x2b8 │ │ ldc2l 9, cr3, [r5, #326] @ 0x146 @ │ │ ldrbeq pc, [r4, #2700] @ 0xa8c @ │ │ ldrbeq pc, [r4, #2624] @ 0xa40 @ │ │ - ldc2l 6, cr13, [r3, #752] @ 0x2f0 │ │ + ldc2l 6, cr13, [r3, #932] @ 0x3a4 │ │ ldrbeq pc, [r4, #2404] @ 0x964 @ │ │ ldrbeq pc, [r4, #2532] @ 0x9e4 @ │ │ ldrbeq pc, [r4, #2500] @ 0x9c4 @ │ │ ldrbeq pc, [r4, #2484] @ 0x9b4 @ │ │ ldrbeq pc, [r4, #2444] @ 0x98c @ │ │ ldrbeq pc, [r4, #2404] @ 0x964 @ │ │ - ldc2l 5, cr13, [r3, #928] @ 0x3a0 │ │ + ldc2l 6, cr13, [r3, #84] @ 0x54 │ │ ldrbeq pc, [r4, #2188] @ 0x88c @ │ │ ldrbeq pc, [r4, #2160] @ 0x870 @ │ │ ldrbeq pc, [r4, #2384] @ 0x950 @ │ │ ldrbeq pc, [r4, #2340] @ 0x924 @ │ │ ldrbeq pc, [r4, #2172] @ 0x87c @ │ │ ldrbeq pc, [r4, #2056] @ 0x808 @ │ │ ldrbeq pc, [r4, #2296] @ 0x8f8 @ │ │ @@ -1477120,15 +1477120,15 @@ │ │ b 24e9458 │ │ eoreq r2, r7, ip, asr #30 │ │ ldc2l 13, cr12, [r5, #204] @ 0xcc │ │ ldrbeq pc, [r4, #1916] @ 0x77c @ │ │ ldrbeq pc, [r4, #1877] @ 0x755 @ │ │ ldrbeq pc, [r4, #1912] @ 0x778 @ │ │ eoreq r2, r7, r8, asr #29 │ │ - ldc2l 11, cr11, [r3, #120] @ 0x78 @ │ │ + ldc2l 11, cr11, [r3, #300] @ 0x12c @ │ │ ldr r0, [pc, #796] @ 24e96a4 │ │ movw r3, #1051 @ 0x41b │ │ ldr r2, [pc, #792] @ 24e96a8 │ │ ldr r1, [sp, #16] │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1477164,15 +1477164,15 @@ │ │ add r1, r2, r1, lsl #1 │ │ add r0, pc, r0 │ │ mov r2, r4 │ │ bl 270da30 │ │ add r1, r9, r0, lsl #3 │ │ add r0, sp, #128 @ 0x80 │ │ b 24e94b0 │ │ - ldc2l 0, cr7, [r4, #932] @ 0x3a4 │ │ + ldc2l 1, cr7, [r4, #88] @ 0x58 │ │ ldc2l 5, cr2, [r6, #428] @ 0x1ac │ │ ldc2l 14, cr6, [r5, #80] @ 0x50 │ │ ldc2l 13, cr6, [r5, #496] @ 0x1f0 │ │ ldr r0, [pc, #636] @ 24e96c0 │ │ movw r3, #1066 @ 0x42a │ │ ldr r2, [pc, #632] @ 24e96c4 │ │ ldr r1, [sp, #16] │ │ @@ -1477263,84 +1477263,84 @@ │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldr r0, [pc, #20] @ 24e95c0 │ │ mov r1, #137 @ 0x89 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ b 24e91fc │ │ - ldc2l 13, cr6, [r4, #308] @ 0x134 │ │ + ldc2l 13, cr6, [r4, #488] @ 0x1e8 │ │ ldc2l 12, cr13, [r2, #540] @ 0x21c │ │ ldc2l 10, cr7, [r5, #608] @ 0x260 @ │ │ ldc2l 7, cr1, [r6, #12] │ │ - ldc2l 13, cr9, [r3, #52] @ 0x34 │ │ + ldc2l 13, cr9, [r3, #232] @ 0xe8 │ │ ldc2l 0, cr12, [r2, #60] @ 0x3c │ │ ldc2l 11, cr11, [r5, #636] @ 0x27c @ │ │ eoreq r2, r7, r4, ror fp │ │ ldc2l 11, cr6, [r5, #16] @ │ │ - ldc2l 7, cr11, [r3, #712] @ 0x2c8 │ │ - ldc2l 13, cr6, [r4, #324] @ 0x144 │ │ - ldc2l 7, cr11, [r3, #408] @ 0x198 │ │ + ldc2l 7, cr11, [r3, #892] @ 0x37c │ │ + ldc2l 13, cr6, [r4, #504] @ 0x1f8 │ │ + ldc2l 7, cr11, [r3, #588] @ 0x24c │ │ eoreq r2, r7, r0, lsl ip │ │ ldc2l 12, cr15, [r5, #496] @ 0x1f0 │ │ ldrbeq lr, [r4, #3072] @ 0xc00 │ │ - ldc2l 7, cr0, [r4, #420] @ 0x1a4 │ │ - ldc2l 15, cr9, [r3, #596] @ 0x254 │ │ + ldc2l 7, cr0, [r4, #600] @ 0x258 │ │ + ldc2l 15, cr9, [r3, #776] @ 0x308 │ │ ldc2l 10, cr15, [r5, #896] @ 0x380 @ │ │ ldrbeq lr, [r4, #2660] @ 0xa64 │ │ - ldc2l 5, cr0, [r4, #820] @ 0x334 │ │ - ldc2l 13, cr9, [r3, #996] @ 0x3e4 │ │ + ldc2l 5, cr0, [r4, #1000] @ 0x3e8 │ │ + ldc2l 14, cr9, [r3, #152] @ 0x98 │ │ ldc2l 2, cr12, [r2, #872] @ 0x368 │ │ ldc2l 2, cr12, [r2, #676] @ 0x2a4 │ │ - ldc2l 4, cr4, [r4, #344] @ 0x158 │ │ - ldc2l 13, cr9, [r3, #452] @ 0x1c4 │ │ - ldc2l 5, cr0, [r4, #92] @ 0x5c │ │ + ldc2l 4, cr4, [r4, #524] @ 0x20c │ │ + ldc2l 13, cr9, [r3, #632] @ 0x278 │ │ + ldc2l 5, cr0, [r4, #272] @ 0x110 │ │ ldc2l 15, cr11, [r5, #44] @ 0x2c │ │ - ldc2l 11, cr6, [r4, #196] @ 0xc4 @ │ │ - ldc2l 4, cr11, [r3, #376] @ 0x178 │ │ - ldc2l 10, cr6, [r4, #180] @ 0xb4 @ │ │ - ldc2l 4, cr11, [r3, #488] @ 0x1e8 │ │ + ldc2l 11, cr6, [r4, #376] @ 0x178 @ │ │ + ldc2l 4, cr11, [r3, #556] @ 0x22c │ │ + ldc2l 10, cr6, [r4, #360] @ 0x168 @ │ │ + ldc2l 4, cr11, [r3, #668] @ 0x29c │ │ ldc2l 12, cr1, [r6, #780] @ 0x30c │ │ ldc2l 15, cr1, [r6, #764] @ 0x2fc │ │ - ldc2l 5, cr11, [r3, #184] @ 0xb8 │ │ - ldc2l 9, cr6, [r4, #482] @ 0x1e2 @ │ │ - ldc2l 9, cr6, [r4, #274] @ 0x112 @ │ │ - ldc2l 9, cr6, [r4, #186] @ 0xba @ │ │ - ldc2l 9, cr6, [r4, #106] @ 0x6a @ │ │ - ldc2l 7, cr6, [r4, #212] @ 0xd4 │ │ + ldc2l 5, cr11, [r3, #364] @ 0x16c │ │ + ldc2l 10, cr6, [r4, #120] @ 0x78 @ │ │ + ldc2l 9, cr6, [r4, #364] @ 0x16c @ │ │ + ldc2l 9, cr6, [r4, #276] @ 0x114 @ │ │ + ldc2l 9, cr6, [r4, #196] @ 0xc4 @ │ │ + ldc2l 7, cr6, [r4, #392] @ 0x188 │ │ ldc2l 11, cr1, [r6, #652] @ 0x28c @ │ │ ldc2l 11, cr1, [r6, #92] @ 0x5c @ │ │ - ldc2l 0, cr11, [r3, #536] @ 0x218 │ │ + ldc2l 0, cr11, [r3, #716] @ 0x2cc │ │ ldc2l 10, cr1, [r6, #908] @ 0x38c @ │ │ - ldc2l 8, cr6, [r4, #980] @ 0x3d4 │ │ - ldc2l 8, cr6, [r4, #852] @ 0x354 │ │ + ldc2l 9, cr6, [r4, #68] @ 0x44 @ │ │ + ldc2l 9, cr6, [r4, #4] @ │ │ ldc2l 13, cr1, [r6, #204] @ 0xcc │ │ ldc2l 12, cr1, [r6, #444] @ 0x1bc │ │ - ldc2l 1, cr11, [r3, #888] @ 0x378 │ │ + ldc2l 2, cr11, [r3, #44] @ 0x2c │ │ ldc2l 12, cr1, [r6, #236] @ 0xec │ │ eoreq r2, r7, r4, ror #16 │ │ - ldc2l 10, cr6, [r4, #596] @ 0x254 @ │ │ + ldc2l 10, cr6, [r4, #776] @ 0x308 @ │ │ ldc2l 9, cr1, [r6, #206] @ 0xce @ │ │ - ldc2l 14, cr10, [r3, #856] @ 0x358 │ │ - ldc2l 5, cr6, [r4, #20] │ │ - ldc2l 15, cr10, [r3, #104] @ 0x68 │ │ - ldc2l 2, cr6, [r4, #980] @ 0x3d4 │ │ - ldc2l 13, cr10, [r3, #40] @ 0x28 │ │ + ldc2l 15, cr10, [r3, #12] │ │ + ldc2l 5, cr6, [r4, #200] @ 0xc8 │ │ + ldc2l 15, cr10, [r3, #284] @ 0x11c │ │ + ldc2l 3, cr6, [r4, #136] @ 0x88 │ │ + ldc2l 13, cr10, [r3, #220] @ 0xdc │ │ ldc2l 6, cr1, [r6, #572] @ 0x23c │ │ - ldc2l 11, cr10, [r3, #1016] @ 0x3f8 @ │ │ - ldc2l 1, cr6, [r4, #580] @ 0x244 │ │ - ldc2l 11, cr10, [r3, #664] @ 0x298 @ │ │ - ldc2l 1, cr6, [r4, #420] @ 0x1a4 │ │ - ldc2l 11, cr10, [r3, #504] @ 0x1f8 @ │ │ - ldc2l 1, cr6, [r4, #260] @ 0x104 │ │ - ldc2l 11, cr10, [r3, #344] @ 0x158 @ │ │ + ldc2l 12, cr10, [r3, #172] @ 0xac │ │ + ldc2l 1, cr6, [r4, #760] @ 0x2f8 │ │ + ldc2l 11, cr10, [r3, #844] @ 0x34c @ │ │ + ldc2l 1, cr6, [r4, #600] @ 0x258 │ │ + ldc2l 11, cr10, [r3, #684] @ 0x2ac @ │ │ + ldc2l 1, cr6, [r4, #440] @ 0x1b8 │ │ + ldc2l 11, cr10, [r3, #524] @ 0x20c @ │ │ ldc2l 5, cr1, [r6, #716] @ 0x2cc │ │ - ldc2l 0, cr6, [r4, #852] @ 0x354 │ │ - ldc2l 10, cr10, [r3, #936] @ 0x3a8 @ │ │ + ldc2l 1, cr6, [r4, #8] │ │ + ldc2l 11, cr10, [r3, #92] @ 0x5c @ │ │ ldc2l 5, cr1, [r6, #188] @ 0xbc │ │ - ldc2l 10, cr10, [r3, #632] @ 0x278 @ │ │ + ldc2l 10, cr10, [r3, #812] @ 0x32c @ │ │ eoreq r1, r7, r4, ror #26 │ │ ldc2l 11, cr11, [r5, #220] @ 0xdc @ │ │ │ │ 024e96d8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ @@ -1477593,41 +1477593,41 @@ │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #48 @ 0x30 │ │ vpop {d8-d9} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 5, cr4, [r3, #756] @ 0x2f4 │ │ + ldc2l 5, cr4, [r3, #936] @ 0x3a8 │ │ ldrbeq lr, [r4, #1032] @ 0x408 │ │ eoreq r1, r7, sp, lsr #23 │ │ ldrbeq lr, [r4, #988] @ 0x3dc │ │ eoreq r1, r7, r0, ror fp │ │ eoreq r1, r7, r4, lsr fp │ │ ldc2l 10, cr14, [r2, #212] @ 0xd4 @ │ │ - ldc2l 4, cr9, [r3, #884] @ 0x374 │ │ + ldc2l 5, cr9, [r3, #40] @ 0x28 │ │ ldc2l 6, cr11, [r5, #560] @ 0x230 │ │ eoreq r1, r7, sp, lsr fp │ │ ldrbeq lr, [r4, #864] @ 0x360 │ │ ldrbeq lr, [r4, #832] @ 0x340 │ │ ldrbeq lr, [r4, #176] @ 0xb0 │ │ ldrbeq lr, [r4, #800] @ 0x320 │ │ ldrbeq lr, [r4, #736] @ 0x2e0 │ │ ldrbeq lr, [r4, #724] @ 0x2d4 │ │ ldc2l 5, cr12, [r2, #140] @ 0x8c │ │ - ldc2l 4, cr9, [r3, #644] @ 0x284 │ │ - ldc2l 1, cr4, [r3, #868] @ 0x364 │ │ + ldc2l 4, cr9, [r3, #824] @ 0x338 │ │ + ldc2l 2, cr4, [r3, #24] │ │ ldrbeq lr, [r4, #680] @ 0x2a8 │ │ ldrbeq lr, [r4, #656] @ 0x290 │ │ ldrbeq lr, [r4, #540] @ 0x21c │ │ ldrbeq lr, [r4, #528] @ 0x210 │ │ ldrbeq lr, [r4, #468] @ 0x1d4 │ │ ldrbeq lr, [r4, #364] @ 0x16c │ │ ldrbeq lr, [r4, #328] @ 0x148 │ │ - ldc2l 2, cr4, [r3, #100] @ 0x64 │ │ + ldc2l 2, cr4, [r3, #280] @ 0x118 │ │ │ │ 024e9b44 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #36 @ 0x24 │ │ mov r6, r3 │ │ mov r7, r2 │ │ @@ -1477891,47 +1477891,47 @@ │ │ ldr r1, [pc, #188] @ 24ea020 │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ bl 270e800 │ │ b 24e9c44 │ │ ldc2l 7, cr3, [r6, #272] @ 0x110 │ │ ldrbeq sp, [r4, #4036] @ 0xfc4 │ │ - ldc2l 11, cr11, [r3, #816] @ 0x330 @ │ │ + ldc2l 11, cr11, [r3, #996] @ 0x3e4 @ │ │ ldrbeq sp, [r4, #4008] @ 0xfa8 │ │ ldrbeq lr, [r4, #120] @ 0x78 │ │ ldc2l 6, cr15, [r2, #240] @ 0xf0 │ │ ldrbeq sp, [r4, #3992] @ 0xf98 │ │ - ldc2l 0, cr10, [r3, #364] @ 0x16c │ │ + ldc2l 0, cr10, [r3, #544] @ 0x220 │ │ ldrbeq sp, [r4, #4020] @ 0xfb4 │ │ ldrbeq sp, [r4, #3880] @ 0xf28 │ │ ldrbeq sp, [r4, #4040] @ 0xfc8 │ │ ldrbeq sp, [r4, #4024] @ 0xfb8 │ │ ldrbeq sp, [r4, #4000] @ 0xfa0 │ │ ldc2l 4, cr3, [r6, #472] @ 0x1d8 │ │ - ldc2l 1, cr9, [r3, #500] @ 0x1f4 │ │ + ldc2l 1, cr9, [r3, #680] @ 0x2a8 │ │ ldc2l 4, cr11, [r2, #508] @ 0x1fc │ │ ldrbeq sp, [r4, #3976] @ 0xf88 │ │ ldrbeq sp, [r4, #3952] @ 0xf70 │ │ ldrbeq sp, [r4, #3792] @ 0xed0 │ │ ldrbeq sp, [r4, #3960] @ 0xf78 │ │ ldrbeq sp, [r4, #3792] @ 0xed0 │ │ ldrbeq sp, [r4, #3764] @ 0xeb4 │ │ ldc2l 4, cr3, [r6, #232] @ 0xe8 │ │ - ldc2l 1, cr9, [r3, #260] @ 0x104 │ │ + ldc2l 1, cr9, [r3, #440] @ 0x1b8 │ │ ldc2l 12, cr1, [r5, #396] @ 0x18c │ │ ldrbeq sp, [r4, #3740] @ 0xe9c │ │ ldrbeq sp, [r4, #3664] @ 0xe50 │ │ - ldc2l 9, cr11, [r3, #248] @ 0xf8 @ │ │ + ldc2l 9, cr11, [r3, #338] @ 0x152 @ │ │ ldrbeq sp, [r4, #3444] @ 0xd74 │ │ ldrbeq sp, [r4, #3572] @ 0xdf4 │ │ ldrbeq sp, [r4, #3540] @ 0xdd4 │ │ ldrbeq sp, [r4, #3524] @ 0xdc4 │ │ ldrbeq sp, [r4, #3484] @ 0xd9c │ │ ldrbeq sp, [r4, #3444] @ 0xd74 │ │ - vcadd.f32 d27, d19, d24, #270 │ │ + ldc2l 8, cr11, [r3, #852] @ 0x354 │ │ ldrbeq sp, [r4, #3228] @ 0xc9c │ │ ldrbeq sp, [r4, #3200] @ 0xc80 │ │ ldrbeq sp, [r4, #3424] @ 0xd60 │ │ ldrbeq sp, [r4, #3380] @ 0xd34 │ │ ldrbeq sp, [r4, #3212] @ 0xc8c │ │ ldrbeq sp, [r4, #3096] @ 0xc18 │ │ ldrbeq sp, [r4, #3336] @ 0xd08 │ │ @@ -1478955,15 +1478955,15 @@ │ │ add r1, sp, #368 @ 0x170 │ │ add r2, sp, #128 @ 0x80 │ │ bl 270cff0 │ │ add r0, sl, sl, lsl #1 │ │ mvn r1, #5 │ │ add r0, r1, r0, lsl #1 │ │ b 24eb160 │ │ - ldc2l 9, cr7, [r4, #92] @ 0x5c @ │ │ + ldc2l 9, cr7, [r4, #182] @ 0xb6 @ │ │ ldrbeq sp, [r4, #3040] @ 0xbe0 │ │ ldrbeq sp, [r4, #3056] @ 0xbf0 │ │ add r5, sp, #208 @ 0xd0 │ │ add r0, sp, #368 @ 0x170 │ │ sub r1, fp, #100 @ 0x64 │ │ mov r2, r8 │ │ mov r3, r5 │ │ @@ -1478993,20 +1478993,20 @@ │ │ add r1, sp, #424 @ 0x1a8 │ │ b 24eb204 │ │ cmp r4, #0 │ │ beq 24eb17c │ │ ldr r0, [sp, #16] │ │ b 24eb198 │ │ eoreq r1, r7, ip, asr #4 │ │ - vcadd.f32 , q10, q5, #270 │ │ + ldc2l 8, cr7, [r4, #988] @ 0x3dc │ │ ldrbeq sp, [r4, #2956] @ 0xb8c │ │ ldrbeq sp, [r4, #2917] @ 0xb65 │ │ ldrbeq sp, [r4, #2952] @ 0xb88 │ │ eoreq r1, r7, r8, asr #3 │ │ - ldc2l 12, cr5, [r4, #820] @ 0x334 │ │ + ldc2l 12, cr5, [r4, #1000] @ 0x3e8 │ │ ldr r0, [pc, #796] @ 24eb3e4 │ │ movw r3, #1051 @ 0x41b │ │ ldr r2, [pc, #792] @ 24eb3e8 │ │ ldr r1, [sp, #16] │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1479042,15 +1479042,15 @@ │ │ add r1, r2, r1, lsl #1 │ │ add r0, pc, r0 │ │ mov r2, r4 │ │ bl 270da30 │ │ add r1, r9, r0, lsl #3 │ │ add r0, sp, #128 @ 0x80 │ │ b 24eb1f0 │ │ - ldc2l 3, cr5, [r4, #676] @ 0x2a4 │ │ + ldc2l 3, cr5, [r4, #856] @ 0x358 │ │ vcadd.f32 d16, d6, d27, #270 │ │ ldc2l 0, cr5, [r5, #848] @ 0x350 │ │ ldc2l 0, cr5, [r5, #240] @ 0xf0 │ │ ldr r0, [pc, #636] @ 24eb400 │ │ movw r3, #1066 @ 0x42a │ │ ldr r2, [pc, #632] @ 24eb404 │ │ ldr r1, [sp, #16] │ │ @@ -1479145,82 +1479145,82 @@ │ │ add r0, pc, r0 │ │ bl 270da00 │ │ b 24eaf3c │ │ ldc2l 15, cr3, [r6, #516] @ 0x204 │ │ ldc2l 15, cr11, [r2, #284] @ 0x11c │ │ ldc2l 13, cr5, [r5, #352] @ 0x160 │ │ ldc2l 9, cr15, [r5, #390] @ 0x186 @ │ │ - ldc2l 15, cr7, [r3, #820] @ 0x334 │ │ + ldc2l 15, cr7, [r3, #1000] @ 0x3e8 │ │ ldc2l 2, cr10, [r2, #828] @ 0x33c │ │ - ldc2l 7, cr6, [r4, #216] @ 0xd8 │ │ + ldc2l 7, cr6, [r4, #396] @ 0x18c │ │ eoreq r0, r7, r4, ror lr │ │ ldc2l 13, cr4, [r5, #784] @ 0x310 │ │ - ldc2l 9, cr5, [r4, #194] @ 0xc2 @ │ │ - ldc2l 0, cr5, [r4, #68] @ 0x44 │ │ - ldc2l 9, cr5, [r4, #42] @ 0x2a @ │ │ + ldc2l 9, cr5, [r4, #284] @ 0x11c @ │ │ + ldc2l 0, cr5, [r4, #248] @ 0xf8 │ │ + ldc2l 9, cr5, [r4, #132] @ 0x84 @ │ │ eoreq r0, r7, r0, lsl pc │ │ ldc2l 15, cr13, [r5, #240] @ 0xf0 │ │ ldrbeq sp, [r4, #16] │ │ - ldc2l 10, cr14, [r3, #164] @ 0xa4 @ │ │ - ldc2l 2, cr8, [r3, #340] @ 0x154 │ │ + ldc2l 10, cr14, [r3, #344] @ 0x158 @ │ │ + ldc2l 2, cr8, [r3, #520] @ 0x208 │ │ ldc2l 13, cr13, [r5, #640] @ 0x280 │ │ ldrbeq ip, [r4, #3700] @ 0xe74 │ │ - vcadd.f32 d30, d19, d13, #270 │ │ - ldc2l 0, cr8, [r3, #740] @ 0x2e4 │ │ + ldc2l 8, cr14, [r3, #744] @ 0x2e8 │ │ + ldc2l 0, cr8, [r3, #920] @ 0x398 │ │ ldc2l 5, cr10, [r2, #616] @ 0x268 │ │ ldc2l 5, cr10, [r2, #420] @ 0x1a4 │ │ - ldc2l 7, cr2, [r4, #88] @ 0x58 │ │ - ldc2l 0, cr8, [r3, #196] @ 0xc4 │ │ - ldc2l 7, cr14, [r3, #860] @ 0x35c │ │ - ldc2l 10, cr6, [r4, #648] @ 0x288 @ │ │ - ldc2l 13, cr4, [r4, #964] @ 0x3c4 │ │ - ldc2l 6, cr5, [r4, #52] @ 0x34 │ │ - ldc2l 12, cr4, [r4, #948] @ 0x3b4 │ │ - ldc2l 6, cr5, [r4, #164] @ 0xa4 │ │ + ldc2l 7, cr2, [r4, #268] @ 0x10c │ │ + ldc2l 0, cr8, [r3, #376] @ 0x178 │ │ + vcadd.f32 d30, d3, d4, #270 │ │ + ldc2l 10, cr6, [r4, #828] @ 0x33c @ │ │ + ldc2l 14, cr4, [r4, #120] @ 0x78 │ │ + ldc2l 6, cr5, [r4, #232] @ 0xe8 │ │ + ldc2l 13, cr4, [r4, #104] @ 0x68 │ │ + ldc2l 6, cr5, [r4, #344] @ 0x158 │ │ ldc2l 15, cr15, [r5, #524] @ 0x20c │ │ ldc2l 2, cr0, [r6, #508] @ 0x1fc │ │ - ldc2l 6, cr5, [r4, #884] @ 0x374 │ │ - ldc2l 12, cr4, [r4, #708] @ 0x2c4 │ │ - ldc2l 12, cr4, [r4, #292] @ 0x124 │ │ - ldc2l 12, cr4, [r4, #116] @ 0x74 │ │ - ldc2l 11, cr4, [r4, #980] @ 0x3d4 @ │ │ - ldc2l 9, cr4, [r4, #490] @ 0x1ea @ │ │ + ldc2l 7, cr5, [r4, #40] @ 0x28 │ │ + ldc2l 12, cr4, [r4, #888] @ 0x378 │ │ + ldc2l 12, cr4, [r4, #472] @ 0x1d8 │ │ + ldc2l 12, cr4, [r4, #296] @ 0x128 │ │ + ldc2l 12, cr4, [r4, #136] @ 0x88 │ │ + ldc2l 10, cr4, [r4, #136] @ 0x88 @ │ │ ldc2l 14, cr15, [r5, #396] @ 0x18c │ │ ldc2l 13, cr15, [r5, #860] @ 0x35c │ │ - ldc2l 2, cr5, [r4, #212] @ 0xd4 │ │ + ldc2l 2, cr5, [r4, #392] @ 0x188 │ │ ldc2l 13, cr15, [r5, #652] @ 0x28c │ │ - ldc2l 11, cr4, [r4, #724] @ 0x2d4 @ │ │ - ldc2l 11, cr4, [r4, #596] @ 0x254 @ │ │ + ldc2l 11, cr4, [r4, #904] @ 0x388 @ │ │ + ldc2l 11, cr4, [r4, #776] @ 0x308 @ │ │ ldc2l 15, cr15, [r5, #972] @ 0x3cc │ │ ldc2l 15, cr15, [r5, #188] @ 0xbc │ │ - ldc2l 3, cr5, [r4, #564] @ 0x234 │ │ + ldc2l 3, cr5, [r4, #744] @ 0x2e8 │ │ ldc2l 14, cr15, [r5, #1004] @ 0x3ec │ │ eoreq r0, r7, r4, ror #22 │ │ - ldc2l 13, cr4, [r4, #340] @ 0x154 │ │ + ldc2l 13, cr4, [r4, #520] @ 0x208 │ │ ldc2l 12, cr15, [r5, #156] @ 0x9c │ │ - ldc2l 0, cr5, [r4, #532] @ 0x214 │ │ - ldc2l 7, cr4, [r4, #788] @ 0x314 │ │ - ldc2l 0, cr5, [r4, #804] @ 0x324 │ │ - ldc2l 5, cr4, [r4, #724] @ 0x2d4 │ │ - ldc2l 14, cr4, [r4, #740] @ 0x2e4 │ │ + ldc2l 0, cr5, [r4, #712] @ 0x2c8 │ │ + ldc2l 7, cr4, [r4, #968] @ 0x3c8 │ │ + ldc2l 0, cr5, [r4, #984] @ 0x3d8 │ │ + ldc2l 5, cr4, [r4, #904] @ 0x388 │ │ + ldc2l 14, cr4, [r4, #920] @ 0x398 │ │ ldc2l 9, cr15, [r5, #158] @ 0x9e @ │ │ - ldc2l 13, cr4, [r4, #692] @ 0x2b4 │ │ - ldc2l 4, cr4, [r4, #324] @ 0x144 │ │ - ldc2l 13, cr4, [r4, #340] @ 0x154 │ │ - ldc2l 4, cr4, [r4, #164] @ 0xa4 │ │ - ldc2l 13, cr4, [r4, #180] @ 0xb4 │ │ - ldc2l 4, cr4, [r4, #4] │ │ - ldc2l 13, cr4, [r4, #20] │ │ + ldc2l 13, cr4, [r4, #872] @ 0x368 │ │ + ldc2l 4, cr4, [r4, #504] @ 0x1f8 │ │ + ldc2l 13, cr4, [r4, #520] @ 0x208 │ │ + ldc2l 4, cr4, [r4, #344] @ 0x158 │ │ + ldc2l 13, cr4, [r4, #360] @ 0x168 │ │ + ldc2l 4, cr4, [r4, #184] @ 0xb8 │ │ + ldc2l 13, cr4, [r4, #200] @ 0xc8 │ │ ldc2l 8, cr15, [r5, #460] @ 0x1cc │ │ - ldc2l 3, cr4, [r4, #596] @ 0x254 │ │ - ldc2l 12, cr4, [r4, #612] @ 0x264 │ │ + ldc2l 3, cr4, [r4, #776] @ 0x308 │ │ + ldc2l 12, cr4, [r4, #792] @ 0x318 │ │ ldc2l 7, cr15, [r5, #956] @ 0x3bc │ │ - ldc2l 12, cr4, [r4, #308] @ 0x134 │ │ + ldc2l 12, cr4, [r4, #488] @ 0x1e8 │ │ eoreq r0, r7, r4, rrx │ │ - ldc2l 6, cr6, [r4, #824] @ 0x338 │ │ + ldc2l 6, cr6, [r4, #1004] @ 0x3ec │ │ │ │ 024eb418 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d9} │ │ sub sp, sp, #64 @ 0x40 │ │ @@ -1479471,41 +1479471,41 @@ │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #48 @ 0x30 │ │ vpop {d8-d9} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 7, cr12, [r4, #272] @ 0x110 │ │ + ldc2l 7, cr12, [r4, #452] @ 0x1c4 │ │ ldrbeq ip, [r4, #2072] @ 0x818 │ │ eoreq pc, r6, sp, lsr #29 │ │ ldrbeq ip, [r4, #2028] @ 0x7ec │ │ eoreq pc, r6, r0, ror lr @ │ │ eoreq pc, r6, r4, lsr lr @ │ │ ldc2l 12, cr12, [r2, #980] @ 0x3d4 │ │ - ldc2l 7, cr7, [r3, #628] @ 0x274 │ │ + ldc2l 7, cr7, [r3, #808] @ 0x328 │ │ ldc2l 9, cr9, [r5, #152] @ 0x98 @ │ │ eoreq pc, r6, sp, lsr lr @ │ │ ldrbeq ip, [r4, #1904] @ 0x770 │ │ ldrbeq ip, [r4, #1872] @ 0x750 │ │ ldrbeq ip, [r4, #1216] @ 0x4c0 │ │ ldrbeq ip, [r4, #1840] @ 0x730 │ │ ldrbeq ip, [r4, #1776] @ 0x6f0 │ │ ldrbeq ip, [r4, #1764] @ 0x6e4 │ │ ldc2l 7, cr10, [r2, #908] @ 0x38c │ │ - ldc2l 7, cr7, [r3, #388] @ 0x184 │ │ - ldc2l 4, cr2, [r3, #612] @ 0x264 │ │ + ldc2l 7, cr7, [r3, #568] @ 0x238 │ │ + ldc2l 4, cr2, [r3, #792] @ 0x318 │ │ ldrbeq ip, [r4, #1720] @ 0x6b8 │ │ ldrbeq ip, [r4, #1696] @ 0x6a0 │ │ ldrbeq ip, [r4, #1580] @ 0x62c │ │ ldrbeq ip, [r4, #1568] @ 0x620 │ │ ldrbeq ip, [r4, #1508] @ 0x5e4 │ │ ldrbeq ip, [r4, #1404] @ 0x57c │ │ ldrbeq ip, [r4, #1368] @ 0x558 │ │ - ldc2l 3, cr12, [r4, #640] @ 0x280 │ │ + ldc2l 3, cr12, [r4, #820] @ 0x334 │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ │ │ 024eb888 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d12} │ │ @@ -1479889,16 +1479889,16 @@ │ │ bl 270ec50 │ │ mov r0, #0 │ │ sub sp, fp, #72 @ 0x48 │ │ vpop {d8-d12} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldc2l 11, cr7, [r5, #928] @ 0x3a0 @ │ │ - ldc2l 5, cr4, [r3, #844] @ 0x34c │ │ - ldc2l 11, cr1, [r3, #256] @ 0x100 @ │ │ + ldc2l 6, cr4, [r3] │ │ + ldc2l 11, cr1, [r3, #436] @ 0x1b4 @ │ │ eoreq pc, r6, r4, lsr #18 │ │ eoreq pc, r6, ip, lsr #17 │ │ eoreq pc, r6, ip, lsr #16 │ │ strdeq pc, [r6], -r4 @ │ │ eoreq pc, r6, r0, lsl #11 │ │ ldrdeq pc, [r6], -r0 @ │ │ ldrdeq pc, [r6], -r0 @ │ │ @@ -1480956,15 +1480956,15 @@ │ │ ldrbeq sp, [r4, #3188] @ 0xc74 │ │ ldrbeq fp, [r4, #3260] @ 0xcbc │ │ ldrbeq r9, [fp, #1376] @ 0x560 │ │ ldrbeq r9, [fp, #1364] @ 0x554 │ │ eoreq pc, r6, ip, asr #6 │ │ ldrbeq r9, [fp, #1060] @ 0x424 │ │ ldc2l 10, cr2, [r6, #116] @ 0x74 @ │ │ - ldc2l 11, cr6, [r3, #436] @ 0x1b4 @ │ │ + ldc2l 11, cr6, [r3, #616] @ 0x268 @ │ │ vcadd.f32 q10, q3, q2, #270 │ │ ldrbeq r9, [fp, #1276] @ 0x4fc │ │ ldrdeq pc, [r6], -r8 @ │ │ ldrbeq ip, [r4, #3052] @ 0xbec │ │ ldrbeq r8, [fp, #952] @ 0x3b8 │ │ ldrbeq r7, [fp, #988] @ 0x3dc │ │ ldrbeq sp, [r4, #2988] @ 0xbac │ │ @@ -1480993,34 +1480993,34 @@ │ │ ldrbeq r7, [fp, #1680] @ 0x690 │ │ ldrbeq r6, [fp, #1716] @ 0x6b4 │ │ ldrbeq ip, [r4, #3716] @ 0xe84 │ │ ldrbeq ip, [r4, #3716] @ 0xe84 │ │ ldrbeq sl, [r4, #3788] @ 0xecc │ │ ldrbeq fp, [r4, #2704] @ 0xa90 │ │ ldrbeq sp, [r4, #2608] @ 0xa30 │ │ - ldc2l 7, cr9, [r4, #84] @ 0x54 │ │ + ldc2l 7, cr9, [r4, #264] @ 0x108 │ │ ldc2l 9, cr4, [r6, #332] @ 0x14c @ │ │ ldrbeq fp, [r4, #2640] @ 0xa50 │ │ ldrbeq sp, [r4, #2528] @ 0x9e0 │ │ - ldc2l 6, cr6, [r4, #560] @ 0x230 │ │ + ldc2l 6, cr6, [r4, #740] @ 0x2e4 │ │ ldc2l 9, cr4, [r6, #172] @ 0xac @ │ │ - ldc2l 10, cr1, [r3, #136] @ 0x88 @ │ │ + ldc2l 10, cr1, [r3, #316] @ 0x13c @ │ │ ldc2l 9, cr4, [r6, #60] @ 0x3c @ │ │ ldc2l 14, cr12, [r5, #392] @ 0x188 │ │ vcadd.f32 q10, q11, q13, #270 │ │ - ldc2l 13, cr3, [r3, #344] @ 0x158 │ │ + ldc2l 13, cr3, [r3, #524] @ 0x20c │ │ ldc2l 8, cr4, [r6, #616] @ 0x268 │ │ ldrbeq sl, [r6, #3512] @ 0xdb8 │ │ - ldc2l 9, cr1, [r3, #52] @ 0x34 @ │ │ + ldc2l 9, cr1, [r3, #142] @ 0x8e @ │ │ ldc2l 8, cr4, [r6, #88] @ 0x58 │ │ ldc2l 7, cr4, [r6, #568] @ 0x238 │ │ ldc2l 8, cr1, [r5, #756] @ 0x2f4 │ │ ldrbeq r8, [r8, #244] @ 0xf4 │ │ ldc2l 12, cr12, [r5, #168] @ 0xa8 │ │ - ldc2l 11, cr3, [r3, #232] @ 0xe8 @ │ │ + ldc2l 11, cr3, [r3, #412] @ 0x19c @ │ │ ldrbeq sl, [r6, #2980] @ 0xba4 │ │ ldc2l 7, cr1, [r5, #916] @ 0x394 │ │ ldrbeq r8, [r8, #28] │ │ ldrbeq r7, [sl, #1104] @ 0x450 │ │ ldc2l 15, cr6, [r5, #68] @ 0x44 │ │ ldrbeq r8, [r9, #1648] @ 0x670 │ │ ldc2l 13, cr6, [r5, #260] @ 0x104 │ │ @@ -1481029,59 +1481029,59 @@ │ │ eoreq lr, r6, r4, lsr #10 │ │ ldrbeq fp, [r4, #3640] @ 0xe38 │ │ ldrbeq r7, [fp, #1540] @ 0x604 │ │ ldrbeq r6, [fp, #1576] @ 0x628 │ │ ldrbeq ip, [r4, #3576] @ 0xdf8 │ │ ldrbeq ip, [r4, #3576] @ 0xdf8 │ │ ldrbeq sl, [r4, #3648] @ 0xe40 │ │ - ldc2l 15, cr5, [r4, #192] @ 0xc0 │ │ + ldc2l 15, cr5, [r4, #372] @ 0x174 │ │ ldrbeq r5, [fp, #2724] @ 0xaa4 │ │ ldc2l 7, cr12, [r5, #120] @ 0x78 │ │ ldrbeq ip, [r4, #3420] @ 0xd5c │ │ ldrbeq ip, [r4, #3420] @ 0xd5c │ │ - ldc2l 5, cr11, [r4, #260] @ 0x104 │ │ + ldc2l 5, cr11, [r4, #440] @ 0x1b8 │ │ ldrbeq r7, [sl, #964] @ 0x3c4 │ │ ldc2l 14, cr6, [r5, #820] @ 0x334 │ │ ldrbeq r8, [r9, #2268] @ 0x8dc │ │ ldrbeq ip, [r4, #3668] @ 0xe54 │ │ eoreq lr, r6, r8, asr r5 │ │ ldrbeq fp, [r4, #3692] @ 0xe6c │ │ ldrbeq r7, [fp, #1592] @ 0x638 │ │ ldrbeq r6, [fp, #1632] @ 0x660 │ │ ldrbeq ip, [r4, #3636] @ 0xe34 │ │ - ldc2l 12, cr6, [r4, #112] @ 0x70 │ │ - ldc2l 11, cr6, [r4, #912] @ 0x390 @ │ │ - ldc2l 11, cr6, [r4, #720] @ 0x2d0 @ │ │ - ldc2l 11, cr6, [r4, #496] @ 0x1f0 @ │ │ + ldc2l 12, cr6, [r4, #292] @ 0x124 │ │ + ldc2l 12, cr6, [r4, #68] @ 0x44 │ │ + ldc2l 11, cr6, [r4, #900] @ 0x384 @ │ │ + ldc2l 11, cr6, [r4, #676] @ 0x2a4 @ │ │ ldrbeq sp, [r4, #796] @ 0x31c │ │ strdeq lr, [r6], -r4 @ │ │ ldrbeq sp, [r4, #1992] @ 0x7c8 │ │ ldrbeq sp, [r4, #1552] @ 0x610 │ │ ldc2l 12, cr6, [r5, #948] @ 0x3b4 │ │ ldrbeq sp, [r4, #880] @ 0x370 │ │ ldrbeq r8, [r9, #1760] @ 0x6e0 │ │ - ldc2l 14, cr8, [r3, #400] @ 0x190 │ │ + ldc2l 14, cr8, [r3, #580] @ 0x244 │ │ ldc2l 8, cr6, [r5, #724] @ 0x2d4 │ │ ldrbeq ip, [r4, #3892] @ 0xf34 │ │ ldrbeq r8, [r9, #676] @ 0x2a4 │ │ - ldc2l 10, cr8, [r3, #160] @ 0xa0 @ │ │ + ldc2l 10, cr8, [r3, #340] @ 0x154 @ │ │ ldrbeq ip, [r4, #3536] @ 0xdd0 │ │ ldrdeq lr, [r6], -r4 @ │ │ ldrbeq fp, [r4, #3560] @ 0xde8 │ │ ldrbeq r7, [fp, #1460] @ 0x5b4 │ │ ldrbeq r6, [fp, #1500] @ 0x5dc │ │ ldrbeq ip, [r4, #3508] @ 0xdb4 │ │ ldrbeq sl, [r4, #3568] @ 0xdf0 │ │ ldc2l 15, cr2, [r5, #656] @ 0x290 │ │ ldrbeq r9, [r8, #2760] @ 0xac8 │ │ eoreq lr, r6, r4, lsr #17 │ │ - vcadd.f32 q11, q2, q14, #270 │ │ - ldc2l 8, cr6, [r4, #208] @ 0xd0 │ │ - vcadd.f32 d22, d4, d4, #270 │ │ - ldc2l 7, cr6, [r4, #816] @ 0x330 │ │ + ldc2l 8, cr6, [r4, #612] @ 0x264 │ │ + vcadd.f32 q11, q2, , #270 │ │ + ldc2l 8, cr6, [r4, #196] @ 0xc4 │ │ + ldc2l 7, cr6, [r4, #996] @ 0x3e4 │ │ eoreq lr, r6, r8, lsr #13 │ │ ldrbeq ip, [r4, #3944] @ 0xf68 │ │ ldrbeq r8, [fp, #2056] @ 0x808 │ │ eoreq lr, r6, r8, lsr #14 │ │ ldrbeq ip, [r4, #4092] @ 0xffc │ │ ldc2l 13, cr2, [r5, #768] @ 0x300 │ │ ldrbeq r9, [r8, #2288] @ 0x8f0 │ │ @@ -1481133,18 +1481133,18 @@ │ │ ldr r0, [pc, #32] @ 24ed1fc │ │ mov r1, #8 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 14, cr10, [r3, #552] @ 0x228 │ │ + ldc2l 14, cr10, [r3, #732] @ 0x2dc │ │ eoreq lr, r6, r4, ror #3 │ │ eoreq lr, r6, r0, asr #3 │ │ - ldc2l 14, cr10, [r3, #88] @ 0x58 │ │ + ldc2l 14, cr10, [r3, #268] @ 0x10c │ │ │ │ 024ed200 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #796 @ 0x31c │ │ mov r6, r3 │ │ mov r4, r2 │ │ @@ -1482176,75 +1482176,75 @@ │ │ mov r1, r7 │ │ mov r2, #1 │ │ mov r3, #80 @ 0x50 │ │ bl 270da60 │ │ ldr r0, [pc, #224] @ 24ee310 │ │ add r0, pc, r0 │ │ b 24ed754 │ │ - ldc2l 14, cr2, [r3, #368] @ 0x170 │ │ + ldc2l 14, cr2, [r3, #548] @ 0x224 │ │ ldc2l 3, cr6, [r5, #384] @ 0x180 │ │ - ldc2l 12, cr5, [r3, #644] @ 0x284 │ │ + ldc2l 12, cr5, [r3, #824] @ 0x338 │ │ ldc2l 14, cr7, [r5, #272] @ 0x110 │ │ - ldc2l 8, cr0, [r4, #456] @ 0x1c8 │ │ + ldc2l 8, cr0, [r4, #636] @ 0x27c │ │ ldc2l 5, cr10, [r2, #548] @ 0x224 │ │ ldc2l 1, cr11, [r2, #352] @ 0x160 │ │ - ldc2l 12, cr10, [r3, #812] @ 0x32c │ │ + ldc2l 12, cr10, [r3, #992] @ 0x3e0 │ │ ldc2l 14, cr11, [r5, #68] @ 0x44 │ │ strdeq sp, [r6], -ip @ │ │ - ldc2l 6, cr0, [r4, #1020] @ 0x3fc │ │ - ldc2l 10, cr5, [r3, #756] @ 0x2f4 @ │ │ + ldc2l 7, cr0, [r4, #176] @ 0xb0 │ │ + ldc2l 10, cr5, [r3, #936] @ 0x3a8 @ │ │ strdeq sp, [r6], -r8 @ │ │ ldc2l 9, cr11, [r5, #148] @ 0x94 @ │ │ - ldc2l 6, cr5, [r3, #836] @ 0x344 │ │ + ldc2l 6, cr5, [r3, #1016] @ 0x3f8 │ │ ldc2l 5, cr15, [r5, #360] @ 0x168 │ │ - ldc2l 0, cr14, [r3, #416] @ 0x1a0 │ │ + ldc2l 0, cr14, [r3, #596] @ 0x254 │ │ vcadd.f32 d17, d6, d8, #270 │ │ vcadd.f32 d17, d6, d10, #270 │ │ ldc2l 0, cr10, [r5, #116] @ 0x74 │ │ ldc2l 4, cr3, [r6, #368] @ 0x170 │ │ ldc2l 6, cr1, [r6, #200] @ 0xc8 │ │ - ldc2l 7, cr5, [r3, #244] @ 0xf4 │ │ - ldc2l 8, cr2, [r3, #756] @ 0x2f4 │ │ + ldc2l 7, cr5, [r3, #424] @ 0x1a8 │ │ + vcadd.f32 q9, , q13, #270 │ │ ldc2l 10, cr12, [r2, #168] @ 0xa8 @ │ │ - ldc2l 7, cr5, [r3, #964] @ 0x3c4 │ │ + ldc2l 8, cr5, [r3, #120] @ 0x78 │ │ ldc2l 1, cr10, [r5, #356] @ 0x164 │ │ ldc2l 13, cr5, [r5, #268] @ 0x10c │ │ - ldc2l 6, cr5, [r3, #420] @ 0x1a4 │ │ + ldc2l 6, cr5, [r3, #600] @ 0x258 │ │ ldc2l 10, cr8, [r5, #320] @ 0x140 @ │ │ ldc2l 3, cr5, [r2, #760] @ 0x2f8 │ │ ldc2l 15, cr4, [r2, #888] @ 0x378 │ │ ldc2l 5, cr8, [r5, #992] @ 0x3e0 │ │ ldc2l 3, cr7, [r5, #744] @ 0x2e8 │ │ eoreq sp, r6, r0, lsr r9 │ │ - ldc2l 0, cr2, [r4, #524] @ 0x20c │ │ - ldc2l 1, cr5, [r3, #244] @ 0xf4 │ │ + ldc2l 0, cr2, [r4, #704] @ 0x2c0 │ │ + ldc2l 1, cr5, [r3, #424] @ 0x1a8 │ │ ldc2l 3, cr12, [r2, #900] @ 0x384 │ │ - ldc2l 6, cr2, [r3, #352] @ 0x160 │ │ - ldc2l 4, cr5, [r3, #548] @ 0x224 │ │ + ldc2l 6, cr2, [r3, #532] @ 0x214 │ │ + ldc2l 4, cr5, [r3, #728] @ 0x2d8 │ │ eoreq sp, r6, r8, asr #17 │ │ - ldc2l 5, cr10, [r3, #372] @ 0x174 │ │ + ldc2l 5, cr10, [r3, #552] @ 0x228 │ │ eoreq sp, r6, r8, lsl #17 │ │ - ldc2l 10, cr5, [r4] @ │ │ - ldc2l 1, cr5, [r3, #596] @ 0x254 │ │ - ldc2l 14, cr9, [r4, #128] @ 0x80 │ │ - ldc2l 13, cr3, [r4, #156] @ 0x9c │ │ - ldc2l 2, cr5, [r3, #484] @ 0x1e4 │ │ + ldc2l 10, cr5, [r4, #180] @ 0xb4 @ │ │ + ldc2l 1, cr5, [r3, #776] @ 0x308 │ │ + ldc2l 14, cr9, [r4, #308] @ 0x134 │ │ + ldc2l 13, cr3, [r4, #336] @ 0x150 │ │ + ldc2l 2, cr5, [r3, #664] @ 0x298 │ │ ldc2l 4, cr1, [r5, #188] @ 0xbc │ │ eoreq sp, r6, r8, lsr r7 │ │ eoreq sp, r6, r8, lsl r5 │ │ eoreq sp, r6, r4, lsr #9 │ │ ldrdeq sp, [r6], -r8 @ │ │ - ldc2l 13, cr5, [r3, #768] @ 0x300 │ │ - ldc2l 13, cr4, [r3, #420] @ 0x1a4 │ │ - ldc2l 13, cr7, [r3, #112] @ 0x70 │ │ - ldc2l 12, cr2, [r3, #640] @ 0x280 │ │ - ldc2l 1, cr10, [r3, #120] @ 0x78 │ │ - ldc2l 15, cr4, [r3, #916] @ 0x394 │ │ - ldc2l 0, cr14, [r3, #916] @ 0x394 │ │ - ldc2l 14, cr4, [r3, #596] @ 0x254 │ │ + ldc2l 13, cr5, [r3, #948] @ 0x3b4 │ │ + ldc2l 13, cr4, [r3, #600] @ 0x258 │ │ + ldc2l 13, cr7, [r3, #292] @ 0x124 │ │ + ldc2l 12, cr2, [r3, #820] @ 0x334 │ │ + ldc2l 1, cr10, [r3, #300] @ 0x12c │ │ + ldc2l 0, cr5, [r3, #72] @ 0x48 │ │ + ldc2l 1, cr14, [r3, #72] @ 0x48 │ │ + ldc2l 14, cr4, [r3, #776] @ 0x308 │ │ │ │ 024ee328 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ ldr r8, [pc, #92] @ 24ee394 │ │ mov r6, r1 │ │ mov r7, r0 │ │ @@ -1483250,15 +1483250,15 @@ │ │ ldr r0, [pc, #3956] @ 24f024c │ │ vcvt.s32.f64 s0, d16 │ │ add r0, pc, r0 │ │ vstr s0, [r0] │ │ b 24ef9a4 │ │ ldc2l 14, cr12, [r5, #240] @ 0xf0 │ │ ldc2l 3, cr14, [r5, #964] @ 0x3c4 │ │ - ldc2l 10, cr1, [r3, #472] @ 0x1d8 @ │ │ + ldc2l 10, cr1, [r3, #652] @ 0x28c @ │ │ eoreq ip, r6, r4, ror pc │ │ ldc2l 8, cr11, [r4, #464] @ 0x1d0 │ │ eoreq ip, r6, r0, asr #30 │ │ ldr r0, [pc, #3916] @ 24f0250 │ │ mov r2, #16 │ │ ldr r1, [pc, #3912] @ 24f0254 │ │ mov r3, #2 │ │ @@ -1483430,15 +1483430,15 @@ │ │ sub r1, r0, #1 │ │ cmp r0, #0 │ │ ble 24ef6ac │ │ vmov r0, s0 │ │ b 24ef6d0 │ │ ldc2l 8, cr8, [r2, #508] @ 0x1fc │ │ ldc2l 5, cr5, [r2, #208] @ 0xd0 │ │ - ldc2l 9, cr4, [r3, #2] @ │ │ + ldc2l 9, cr4, [r3, #92] @ 0x5c @ │ │ ldc2l 4, cr1, [r5, #92] @ 0x5c │ │ ldrbeq r7, [fp, #44] @ 0x2c │ │ vcadd.f32 d24, d2, d3, #270 │ │ ldr r0, [pc, #3932] @ 24f0530 │ │ mov r1, #1 │ │ add r0, pc, r0 │ │ str r1, [r0] │ │ @@ -1483474,18 +1483474,18 @@ │ │ ldrbeq r7, [fp, #592] @ 0x250 │ │ eoreq ip, r6, r4, lsr #27 │ │ ldrbeq r6, [fp, #3732] @ 0xe94 │ │ ldrbeq r6, [fp, #3736] @ 0xe98 │ │ ldrbeq r6, [fp, #3820] @ 0xeec │ │ ldrbeq r7, [fp, #296] @ 0x128 │ │ ldc2l 1, cr3, [r5, #328] @ 0x148 │ │ - ldc2l 7, cr4, [r3, #836] @ 0x344 │ │ + ldc2l 7, cr4, [r3, #1016] @ 0x3f8 │ │ ldc2l 4, cr2, [r6, #796] @ 0x31c │ │ ldrbeq r6, [fp, #3880] @ 0xf28 │ │ - ldc2l 9, cr1, [r3, #390] @ 0x186 @ │ │ + ldc2l 9, cr1, [r3, #480] @ 0x1e0 @ │ │ strdeq ip, [r6], -ip @ │ │ strdeq ip, [r6], -r4 @ │ │ nop {0} │ │ andeq r0, r0, r0 │ │ addsmi fp, r8, r0, lsl #16 │ │ andeq r0, r0, r0 │ │ rsbsmi r7, r1, r0 │ │ @@ -1483569,22 +1483569,22 @@ │ │ add r7, pc, r7 │ │ vstr d9, [r0] │ │ add r6, pc, r6 │ │ b 24ef9a4 │ │ ldrbeq r6, [fp, #3570] @ 0xdf2 │ │ ldc2l 0, cr13, [r4, #768] @ 0x300 │ │ ldrbeq r6, [fp, #3534] @ 0xdce │ │ - ldc2l 7, cr3, [r3, #276] @ 0x114 │ │ + ldc2l 7, cr3, [r3, #456] @ 0x1c8 │ │ ldrbeq r6, [fp, #4044] @ 0xfcc │ │ ldrbeq r6, [fp, #4048] @ 0xfd0 │ │ ldrbeq r6, [fp, #4040] @ 0xfc8 │ │ ldrbeq r6, [fp, #4024] @ 0xfb8 │ │ ldrbeq r6, [fp, #4012] @ 0xfac │ │ ldrbeq r6, [fp, #3536] @ 0xdd0 │ │ - ldc2l 6, cr7, [r3, #852] @ 0x354 │ │ + ldc2l 7, cr7, [r3, #8] │ │ vldr d16, [r6] │ │ vcmp.f64 d16, d17 │ │ vmrs APSR_nzcv, fpscr │ │ bne 24ef2b0 │ │ ldr r0, [pc, #3328] @ 24f0520 │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ @@ -1483605,31 +1483605,31 @@ │ │ mov r1, #0 │ │ vcmp.f64 d17, d16 │ │ vmrs APSR_nzcv, fpscr │ │ movwmi r1, #1 │ │ str r1, [r0] │ │ bpl 24ef2c0 │ │ b 24ef4a8 │ │ - ldc2l 9, cr9, [r4, #446] @ 0x1be @ │ │ + ldc2l 10, cr9, [r4, #48] @ 0x30 @ │ │ ldrbeq r6, [fp, #3280] @ 0xcd0 │ │ - ldc2l 12, cr14, [r2, #452] @ 0x1c4 │ │ + ldc2l 12, cr14, [r2, #632] @ 0x278 │ │ ldc2l 8, cr10, [r4, #120] @ 0x78 │ │ - ldc2l 6, cr11, [r3, #912] @ 0x390 │ │ - ldc2l 15, cr8, [r3, #136] @ 0x88 │ │ + ldc2l 7, cr11, [r3, #68] @ 0x44 │ │ + ldc2l 15, cr8, [r3, #316] @ 0x13c │ │ ldrbeq r6, [fp, #3348] @ 0xd14 │ │ - ldc2l 6, cr7, [r3, #84] @ 0x54 │ │ + ldc2l 6, cr7, [r3, #264] @ 0x108 │ │ ldrbeq r6, [fp, #3340] @ 0xd0c │ │ ldrbeq r6, [fp, #3220] @ 0xc94 │ │ ldc2l 7, cr3, [r2, #984] @ 0x3d8 │ │ ldrbeq r6, [fp, #3832] @ 0xef8 │ │ ldrbeq r6, [fp, #3284] @ 0xcd4 │ │ ldrbeq r6, [fp, #3688] @ 0xe68 │ │ strdeq ip, [r6], -r8 @ │ │ ldrbeq r6, [fp, #3640] @ 0xe38 │ │ - ldc2l 6, cr11, [r3, #568] @ 0x238 │ │ + ldc2l 6, cr11, [r3, #748] @ 0x2ec │ │ ldc2l 3, cr0, [r6, #976] @ 0x3d0 │ │ ldrbeq r6, [fp, #2968] @ 0xb98 │ │ ldrbeq r6, [fp, #3560] @ 0xde8 │ │ ldr r0, [pc, #3192] @ 24f0548 │ │ movw r3, #1221 @ 0x4c5 │ │ ldr r2, [pc, #3188] @ 24f054c │ │ add r0, pc, r0 │ │ @@ -1483715,15 +1483715,15 @@ │ │ ldr r0, [pc, #3032] @ 24f05f4 │ │ add r0, pc, r0 │ │ vldr d16, [r0] │ │ add r0, r6, r1, lsl #3 │ │ vldr d17, [r0] │ │ vsub.f64 d8, d17, d16 │ │ b 24efb30 │ │ - ldc2l 6, cr11, [r3, #248] @ 0xf8 │ │ + ldc2l 6, cr11, [r3, #428] @ 0x1ac │ │ ldc2l 3, cr0, [r6, #656] @ 0x290 │ │ ldrbeq r6, [fp, #2888] @ 0xb48 │ │ ldrbeq r6, [fp, #3604] @ 0xe14 │ │ ldrbeq r6, [fp, #3464] @ 0xd88 │ │ ldr r0, [pc, #2944] @ 24f05cc │ │ mov r2, #6 │ │ ldr r1, [pc, #2940] @ 24f05d0 │ │ @@ -1483738,29 +1483738,29 @@ │ │ ldr r1, [pc, #2912] @ 24f05d8 │ │ mov r3, #3 │ │ add r0, pc, r0 │ │ str r5, [sp] │ │ add r1, pc, r1 │ │ b 24eeae0 │ │ ldrbeq r6, [fp, #2828] @ 0xb0c │ │ - ldc2l 5, cr11, [r3, #352] @ 0x160 │ │ + ldc2l 5, cr11, [r3, #532] @ 0x214 │ │ ldr r0, [pc, #2888] @ 24f05e0 │ │ mov r2, #6 │ │ ldr r1, [pc, #2884] @ 24f05e4 │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ b 24efe8c │ │ ldc2l 1, cr11, [r2, #100] @ 0x64 │ │ ldrbeq r6, [fp, #2862] @ 0xb2e │ │ - ldc2l 10, cr14, [r2, #500] @ 0x1f4 @ │ │ - ldc2l 5, cr11, [r3, #472] @ 0x1d8 │ │ + ldc2l 10, cr14, [r2, #680] @ 0x2a8 @ │ │ + ldc2l 5, cr11, [r3, #652] @ 0x28c │ │ ldc2l 2, cr0, [r6, #880] @ 0x370 │ │ ldrbeq r6, [fp, #2692] @ 0xa84 │ │ ldrbeq r6, [fp, #3304] @ 0xce8 │ │ - ldc2l 5, cr11, [r3, #232] @ 0xe8 │ │ + ldc2l 5, cr11, [r3, #412] @ 0x19c │ │ ldc2l 2, cr0, [r6, #640] @ 0x280 │ │ ldrbeq r6, [fp, #2632] @ 0xa48 │ │ ldr r0, [pc, #2848] @ 24f05f8 │ │ movw r3, #1283 @ 0x503 │ │ ldr r2, [pc, #2844] @ 24f05fc │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1483871,15 +1483871,15 @@ │ │ ldrbeq r6, [fp, #2656] @ 0xa60 │ │ ldrbeq r6, [fp, #2628] @ 0xa44 │ │ ldrbeq r6, [fp, #2060] @ 0x80c │ │ ldrbeq r6, [fp, #2584] @ 0xa18 │ │ ldrbeq r6, [fp, #2676] @ 0xa74 │ │ ldrbeq r6, [fp, #2528] @ 0x9e0 │ │ ldrbeq r6, [fp, #1892] @ 0x764 │ │ - ldc2l 2, cr11, [r3, #152] @ 0x98 │ │ + ldc2l 2, cr11, [r3, #332] @ 0x14c │ │ ldc2l 15, cr15, [r5, #560] @ 0x230 │ │ ldr r0, [pc, #2440] @ 24f0638 │ │ movw r3, #1285 @ 0x505 │ │ ldr r2, [pc, #2436] @ 24f063c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1483983,32 +1483983,32 @@ │ │ mov r2, #400 @ 0x190 │ │ add r5, pc, r5 │ │ mov r3, #194 @ 0xc2 │ │ add r1, pc, r1 │ │ b 24efec8 │ │ ldrbeq r6, [fp, #1844] @ 0x734 │ │ ldrbeq r6, [fp, #2456] @ 0x998 │ │ - ldc2l 1, cr11, [r3, #936] @ 0x3a8 │ │ + ldc2l 2, cr11, [r3, #92] @ 0x5c │ │ ldc2l 15, cr15, [r5, #320] @ 0x140 │ │ ldr r0, [pc, #2036] @ 24f0664 │ │ mov r1, #1 │ │ add r0, pc, r0 │ │ str r1, [r0] │ │ ldr r0, [pc, #2052] @ 24f0684 │ │ mov r2, #3 │ │ ldr r1, [pc, #2048] @ 24f0688 │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ str r2, [sp] │ │ b 24eead8 │ │ ldrbeq r6, [fp, #1784] @ 0x6f8 │ │ ldc2l 2, cr10, [r4, #360] @ 0x168 │ │ - ldc2l 6, cr14, [r2, #420] @ 0x1a4 │ │ + ldc2l 6, cr14, [r2, #600] @ 0x258 │ │ ldrbeq r6, [fp, #2312] @ 0x908 │ │ - ldc2l 1, cr11, [r3, #376] @ 0x178 │ │ + ldc2l 1, cr11, [r3, #556] @ 0x22c │ │ ldc2l 14, cr15, [r5, #784] @ 0x310 │ │ ldr r5, [pc, #2016] @ 24f0694 │ │ mov r6, #400 @ 0x190 │ │ ldr r1, [pc, #2012] @ 24f0698 │ │ mov r2, #400 @ 0x190 │ │ add r5, pc, r5 │ │ mov r3, #218 @ 0xda │ │ @@ -1484038,22 +1484038,22 @@ │ │ mov r1, r9 │ │ mov r3, r5 │ │ b 24effb4 │ │ ldrbeq r6, [fp, #1640] @ 0x668 │ │ ldrbeq r6, [fp, #2264] @ 0x8d8 │ │ ldc2l 9, cr12, [r4, #198] @ 0xc6 @ │ │ ldrbeq r6, [fp, #2320] @ 0x910 │ │ - ldc2l 1, cr9, [r3, #88] @ 0x58 │ │ + ldc2l 1, cr9, [r3, #268] @ 0x10c │ │ ldrbeq r6, [fp, #2196] @ 0x894 │ │ ldc2l 9, cr12, [r4, #62] @ 0x3e @ │ │ ldrbeq r6, [fp, #1500] @ 0x5dc │ │ - ldc2l 15, cr2, [r3, #584] @ 0x248 │ │ - ldc2l 10, cr14, [r3, #404] @ 0x194 @ │ │ + ldc2l 15, cr2, [r3, #764] @ 0x2fc │ │ + ldc2l 10, cr14, [r3, #584] @ 0x248 @ │ │ ldrbeq r6, [fp, #2036] @ 0x7f4 │ │ - ldc2l 0, cr11, [r3, #280] @ 0x118 │ │ + ldc2l 0, cr11, [r3, #460] @ 0x1cc │ │ ldc2l 13, cr15, [r5, #688] @ 0x2b0 │ │ ldrbeq r6, [fp, #1360] @ 0x550 │ │ ldr r7, [pc, #1852] @ 24f06a8 │ │ mov r2, #400 @ 0x190 │ │ ldr r1, [pc, #1848] @ 24f06ac │ │ mov r3, #187 @ 0xbb │ │ add r7, pc, r7 │ │ @@ -1484110,32 +1484110,32 @@ │ │ ble 24f00ac │ │ vmov.f64 d17, #112 @ 0x3f800000 1.0 │ │ vldr d18, [pc, #568] @ 24f0288 │ │ b 24f00c4 │ │ ldrbeq r6, [fp, #1956] @ 0x7a4 │ │ ldrbeq r6, [fp, #1316] @ 0x524 │ │ ldc2l 6, cr4, [r5, #484] @ 0x1e4 │ │ - ldc2l 14, cr3, [r3, #372] @ 0x174 │ │ + ldc2l 14, cr3, [r3, #552] @ 0x228 │ │ ldrbeq r6, [fp, #1876] @ 0x754 │ │ - ldc2l 15, cr10, [r3, #664] @ 0x298 │ │ + ldc2l 15, cr10, [r3, #844] @ 0x34c │ │ ldc2l 13, cr15, [r5, #48] @ 0x30 │ │ ldrbeq r6, [fp, #1200] @ 0x4b0 │ │ ldrbeq r6, [fp, #1796] @ 0x704 │ │ ldrbeq r6, [fp, #1156] @ 0x484 │ │ - ldc2l 15, cr10, [r3, #264] @ 0x108 │ │ + ldc2l 15, cr10, [r3, #444] @ 0x1bc │ │ ldc2l 12, cr15, [r5, #672] @ 0x2a0 │ │ ldrbeq r6, [fp, #1104] @ 0x450 │ │ ldrbeq r6, [fp, #1720] @ 0x6b8 │ │ - ldc2l 15, cr10, [r3, #24] │ │ + ldc2l 15, cr10, [r3, #204] @ 0xcc │ │ ldc2l 12, cr15, [r5, #432] @ 0x1b0 │ │ - ldc2l 14, cr10, [r3, #904] @ 0x388 │ │ + ldc2l 15, cr10, [r3, #60] @ 0x3c │ │ ldc2l 12, cr15, [r5, #288] @ 0x120 │ │ ldrbeq r6, [fp, #1008] @ 0x3f0 │ │ ldrbeq r6, [fp, #1624] @ 0x658 │ │ - ldc2l 14, cr10, [r3, #664] @ 0x298 │ │ + ldc2l 14, cr10, [r3, #844] @ 0x34c │ │ ldc2l 12, cr15, [r5, #48] @ 0x30 │ │ ldrbeq r6, [fp, #940] @ 0x3ac │ │ vcmp.f64 d16, #0.0 │ │ vmov.i32 d17, #0 @ 0x00000000 │ │ vmrs APSR_nzcv, fpscr │ │ bpl 24f00cc │ │ vmov.f64 d17, #240 @ 0xbf800000 -1.0 │ │ @@ -1484236,23 +1484236,23 @@ │ │ eoreq ip, r6, r4, lsl r1 │ │ ldrbeq r6, [fp, #1408] @ 0x580 │ │ eoreq ip, r6, r0, lsl #2 │ │ ldrbeq r6, [fp, #860] @ 0x35c │ │ ldrbeq r6, [fp, #724] @ 0x2d4 │ │ ldrbeq r6, [fp, #1552] @ 0x610 │ │ ldrbeq r6, [fp, #734] @ 0x2de │ │ - ldc2l 12, cr2, [r3, #356] @ 0x164 │ │ + ldc2l 12, cr2, [r3, #536] @ 0x218 │ │ ldrbeq r6, [fp, #1220] @ 0x4c4 │ │ - ldc2l 13, cr10, [r3, #40] @ 0x28 │ │ + ldc2l 13, cr10, [r3, #220] @ 0xdc │ │ ldc2l 10, cr15, [r5, #448] @ 0x1c0 @ │ │ ldrbeq r6, [fp, #1128] @ 0x468 │ │ - ldc2l 12, cr10, [r3, #696] @ 0x2b8 │ │ + ldc2l 12, cr10, [r3, #876] @ 0x36c │ │ ldc2l 10, cr15, [r5, #80] @ 0x50 @ │ │ ldrbeq r6, [fp, #1060] @ 0x424 │ │ - ldc2l 12, cr10, [r3, #424] @ 0x1a8 │ │ + ldc2l 12, cr10, [r3, #604] @ 0x25c │ │ ldc2l 9, cr15, [r5, #416] @ 0x1a0 @ │ │ ldrbeq r6, [fp, #496] @ 0x1f0 │ │ andeq r0, r0, r0 │ │ submi r8, sp, r0 │ │ andeq r0, r0, r0 │ │ subgt r0, lr, r0 │ │ andeq r0, r0, r0 │ │ @@ -1484388,15 +1484388,15 @@ │ │ ldr r2, [pc, #684] @ 24f074c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 24f029c │ │ ldrbeq r6, [fp, #302] @ 0x12e │ │ - ldc2l 10, cr2, [r3, #676] @ 0x2a4 @ │ │ + ldc2l 10, cr2, [r3, #856] @ 0x358 @ │ │ ldrbeq r6, [fp, #200] @ 0xc8 │ │ ldrbeq r6, [fp, #128] @ 0x80 │ │ ldrbeq r6, [fp, #776] @ 0x308 │ │ ldr r0, [pc, #680] @ 24f0774 │ │ mov r1, #400 @ 0x190 │ │ add r0, pc, r0 │ │ bl 270da00 │ │ @@ -1484409,143 +1484409,143 @@ │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #48 @ 0x30 │ │ vpop {d8-d9} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 11, cr10, [r3, #328] @ 0x148 @ │ │ + ldc2l 11, cr10, [r3, #508] @ 0x1fc @ │ │ ldc2l 8, cr15, [r5, #736] @ 0x2e0 │ │ ldrbeq r6, [fp, #300] @ 0x12c │ │ ldrbeq r6, [fp, #708] @ 0x2c4 │ │ - ldc2l 11, cr10, [r3, #40] @ 0x28 @ │ │ + ldc2l 11, cr10, [r3, #220] @ 0xdc @ │ │ ldc2l 8, cr15, [r5, #448] @ 0x1c0 │ │ ldrbeq r5, [fp, #4088] @ 0xff8 │ │ - ldc2l 8, cr10, [r3, #248] @ 0xf8 │ │ + vcadd.f32 q13, , , #270 │ │ ldc2l 5, cr15, [r5, #656] @ 0x290 │ │ ldrbeq r5, [fp, #3524] @ 0xdc4 │ │ ldrbeq r6, [fp, #156] @ 0x9c │ │ ldrbeq r6, [fp, #564] @ 0x234 │ │ - ldc2l 10, cr10, [r3, #488] @ 0x1e8 @ │ │ + ldc2l 10, cr10, [r3, #668] @ 0x29c @ │ │ ldc2l 7, cr15, [r5, #896] @ 0x380 │ │ ldrbeq r6, [fp, #716] @ 0x2cc │ │ ldrbeq r6, [fp, #488] @ 0x1e8 │ │ - ldc2l 7, cr10, [r3, #648] @ 0x288 │ │ + ldc2l 7, cr10, [r3, #828] @ 0x33c │ │ ldc2l 5, cr15, [r5, #32] │ │ ldrbeq r6, [fp, #4] │ │ ldrbeq r5, [fp, #4060] @ 0xfdc │ │ ldrbeq r5, [fp, #3420] @ 0xd5c │ │ ldrbeq r5, [fp, #4048] @ 0xfd0 │ │ ldrbeq r5, [fp, #4080] @ 0xff0 │ │ ldrbeq r5, [fp, #3180] @ 0xc6c │ │ ldrbeq r5, [fp, #3768] @ 0xeb8 │ │ - ldc2l 6, cr10, [r3, #1016] @ 0x3f8 │ │ + ldc2l 7, cr10, [r3, #172] @ 0xac │ │ ldc2l 4, cr15, [r5, #400] @ 0x190 │ │ ldrbeq r5, [fp, #3736] @ 0xe98 │ │ ldrbeq r5, [fp, #3064] @ 0xbf8 │ │ ldrbeq r6, [fp, #860] @ 0x35c │ │ ldrbeq r6, [fp, #632] @ 0x278 │ │ - ldc2l 9, cr10, [r3, #380] @ 0x17c @ │ │ + ldc2l 9, cr10, [r3, #470] @ 0x1d6 @ │ │ ldc2l 7, cr15, [r5, #144] @ 0x90 │ │ ldrbeq r6, [fp, #544] @ 0x220 │ │ ldrbeq r6, [fp, #504] @ 0x1f8 │ │ ldrbeq r6, [fp, #500] @ 0x1f4 │ │ ldrbeq r6, [fp, #532] @ 0x214 │ │ ldrbeq r5, [fp, #3724] @ 0xe8c │ │ ldrbeq r5, [fp, #3676] @ 0xe5c │ │ - ldc2l 9, cr10, [r3, #60] @ 0x3c @ │ │ + ldc2l 9, cr10, [r3, #150] @ 0x96 @ │ │ ldc2l 6, cr15, [r5, #528] @ 0x210 │ │ ldrbeq r5, [fp, #3580] @ 0xdfc │ │ ldrbeq r6, [fp, #140] @ 0x8c │ │ - ldc2l 8, cr10, [r3, #840] @ 0x348 │ │ + ldc2l 8, cr10, [r3, #1020] @ 0x3fc │ │ ldc2l 6, cr15, [r5, #224] @ 0xe0 │ │ ldrbeq r5, [fp, #3760] @ 0xeb0 │ │ ldrbeq r6, [fp, #100] @ 0x64 │ │ ldrbeq r5, [fp, #3524] @ 0xdc4 │ │ ldc2l 7, cr9, [r4, #424] @ 0x1a8 │ │ ldrbeq r5, [fp, #3076] @ 0xc04 │ │ - ldc2l 7, cr12, [r3, #336] @ 0x150 │ │ + ldc2l 7, cr12, [r3, #516] @ 0x204 │ │ ldc2l 6, cr9, [r4, #664] @ 0x298 │ │ - ldc2l 10, cr13, [r2, #836] @ 0x344 @ │ │ - ldc2l 11, cr13, [r2, #468] @ 0x1d4 @ │ │ + ldc2l 10, cr13, [r2, #1016] @ 0x3f8 @ │ │ + ldc2l 11, cr13, [r2, #648] @ 0x288 @ │ │ ldrbeq r5, [fp, #3004] @ 0xbbc │ │ - ldc2l 7, cr12, [r3, #64] @ 0x40 │ │ + ldc2l 7, cr12, [r3, #244] @ 0xf4 │ │ ldrbeq r5, [fp, #3196] @ 0xc7c │ │ ldrbeq r5, [fp, #3036] @ 0xbdc │ │ ldrbeq r5, [fp, #3584] @ 0xe00 │ │ ldrbeq r5, [fp, #2912] @ 0xb60 │ │ - ldc2l 5, cr10, [r3, #616] @ 0x268 │ │ + ldc2l 5, cr10, [r3, #796] @ 0x31c │ │ ldc2l 3, cr15, [r5] │ │ ldrbeq r5, [fp, #2696] @ 0xa88 │ │ ldrbeq r5, [fp, #3332] @ 0xd04 │ │ - ldc2l 5, cr10, [r3, #344] @ 0x158 │ │ + ldc2l 5, cr10, [r3, #524] @ 0x20c │ │ ldc2l 2, cr15, [r5, #752] @ 0x2f0 │ │ ldrbeq r5, [fp, #3284] @ 0xcd4 │ │ ldrbeq r5, [fp, #2612] @ 0xa34 │ │ - ldc2l 4, cr10, [r3, #856] @ 0x358 │ │ + ldc2l 5, cr10, [r3, #12] │ │ ldc2l 2, cr15, [r5, #240] @ 0xf0 │ │ ldrbeq r5, [fp, #2508] @ 0x9cc │ │ ldrbeq r5, [fp, #3144] @ 0xc48 │ │ - ldc2l 4, cr10, [r3, #584] @ 0x248 │ │ + ldc2l 4, cr10, [r3, #764] @ 0x2fc │ │ ldc2l 1, cr15, [r5, #992] @ 0x3e0 │ │ ldrbeq r5, [fp, #3076] @ 0xc04 │ │ ldrbeq r5, [fp, #2428] @ 0x97c │ │ - ldc2l 3, cr10, [r3, #776] @ 0x308 │ │ + ldc2l 3, cr10, [r3, #956] @ 0x3bc │ │ ldc2l 1, cr15, [r5, #160] @ 0xa0 │ │ ldrbeq r5, [fp, #2868] @ 0xb34 │ │ - ldc2l 3, cr10, [r3, #552] @ 0x228 │ │ + ldc2l 3, cr10, [r3, #732] @ 0x2dc │ │ ldc2l 0, cr15, [r5, #960] @ 0x3c0 │ │ ldrbeq r5, [fp, #2380] @ 0x94c │ │ ldrbeq r5, [fp, #2768] @ 0xad0 │ │ - ldc2l 3, cr10, [r3, #152] @ 0x98 │ │ + ldc2l 3, cr10, [r3, #332] @ 0x14c │ │ ldc2l 0, cr15, [r5, #560] @ 0x230 │ │ ldrbeq r5, [fp, #2160] @ 0x870 │ │ ldrbeq r5, [fp, #2832] @ 0xb10 │ │ ldrbeq r5, [fp, #2472] @ 0x9a8 │ │ ldrbeq r5, [fp, #2160] @ 0x870 │ │ ldc2l 3, cr2, [r2, #840] @ 0x348 │ │ ldc2l 0, cr7, [r2, #588] @ 0x24c │ │ ldrbeq r5, [fp, #1980] @ 0x7bc │ │ ldrbeq r5, [fp, #2616] @ 0xa38 │ │ ldrbeq r5, [fp, #2050] @ 0x802 │ │ ldrbeq r5, [fp, #2576] @ 0xa10 │ │ ldrbeq r5, [fp, #1894] @ 0x766 │ │ - ldc2l 6, cr13, [r2, #804] @ 0x324 │ │ + ldc2l 6, cr13, [r2, #984] @ 0x3d8 │ │ ldrbeq r5, [fp, #2132] @ 0x854 │ │ ldrbeq r5, [fp, #2032] @ 0x7f0 │ │ ldrbeq r5, [fp, #1976] @ 0x7b8 │ │ - ldc2l 11, cr1, [r4, #300] @ 0x12c @ │ │ - ldc2l 0, cr3, [r3, #132] @ 0x84 │ │ + ldc2l 11, cr1, [r4, #480] @ 0x1e0 @ │ │ + ldc2l 0, cr3, [r3, #312] @ 0x138 │ │ ldrbeq r5, [fp, #2092] @ 0x82c │ │ - ldc2l 14, cr11, [r2, #592] @ 0x250 │ │ + ldc2l 14, cr11, [r2, #772] @ 0x304 │ │ ldrbeq r5, [fp, #1792] @ 0x700 │ │ ldc2l 14, cr13, [r4, #64] @ 0x40 │ │ - ldc2l 15, cr2, [r3, #404] @ 0x194 │ │ - ldc2l 15, cr2, [r3, #212] @ 0xd4 │ │ + ldc2l 15, cr2, [r3, #584] @ 0x248 │ │ + ldc2l 15, cr2, [r3, #392] @ 0x188 │ │ ldrbeq r5, [fp, #2328] @ 0x918 │ │ ldrbeq r5, [fp, #1692] @ 0x69c │ │ ldrbeq r5, [fp, #1424] @ 0x590 │ │ ldrbeq r5, [fp, #2276] @ 0x8e4 │ │ ldrbeq r5, [fp, #2168] @ 0x878 │ │ ldrbeq r5, [fp, #2280] @ 0x8e8 │ │ ldrbeq r5, [fp, #1180] @ 0x49c │ │ ldrbeq r5, [fp, #1260] @ 0x4ec │ │ - ldc2l 13, cr15, [r3, #488] @ 0x1e8 │ │ + ldc2l 13, cr15, [r3, #668] @ 0x29c │ │ ldrbeq r5, [fp, #1256] @ 0x4e8 │ │ ldrbeq r5, [fp, #1872] @ 0x750 │ │ ldrbeq r5, [fp, #1210] @ 0x4ba │ │ - ldc2l 13, cr2, [r3, #644] @ 0x284 │ │ + ldc2l 13, cr2, [r3, #824] @ 0x338 │ │ ldrbeq r5, [fp, #1296] @ 0x510 │ │ ldrbeq r5, [fp, #1128] @ 0x468 │ │ ldrbeq r5, [fp, #1104] @ 0x450 │ │ ldrbeq r5, [fp, #1056] @ 0x420 │ │ - ldc2l 13, cr5, [r3, #500] @ 0x1f4 │ │ + ldc2l 13, cr5, [r3, #680] @ 0x2a8 │ │ ldrbeq r5, [fp, #936] @ 0x3a8 │ │ ldrbeq r5, [fp, #1156] @ 0x484 │ │ - ldc2l 7, cr1, [r4, #584] @ 0x248 │ │ + ldc2l 7, cr1, [r4, #764] @ 0x2fc │ │ ldc2l 10, cr14, [r5, #528] @ 0x210 @ │ │ ldrbeq r5, [fp, #656] @ 0x290 │ │ ldrbeq r5, [fp, #1420] @ 0x58c │ │ ldc2l 8, cr0, [r6, #496] @ 0x1f0 │ │ ldc2l 10, cr14, [r5, #256] @ 0x100 @ │ │ ldrbeq r5, [fp, #448] @ 0x1c0 │ │ ldrbeq r5, [fp, #440] @ 0x1b8 │ │ @@ -1484553,23 +1484553,23 @@ │ │ ldrbeq r5, [fp, #1212] @ 0x4bc │ │ ldrbeq r5, [fp, #472] @ 0x1d8 │ │ ldrbeq r5, [fp, #1172] @ 0x494 │ │ ldrbeq r5, [fp, #1204] @ 0x4b4 │ │ ldrbeq r5, [fp, #1152] @ 0x480 │ │ ldrbeq r5, [fp, #288] @ 0x120 │ │ ldrbeq r5, [fp, #496] @ 0x1f0 │ │ - ldc2l 3, cr3, [r4, #32] │ │ + ldc2l 3, cr3, [r4, #212] @ 0xd4 │ │ ldc2l 9, cr14, [r5, #128] @ 0x80 @ │ │ strdeq fp, [r6], -ip @ │ │ ldrbeq r5, [fp, #940] @ 0x3ac │ │ - ldc2l 12, cr2, [r3, #196] @ 0xc4 │ │ + ldc2l 12, cr2, [r3, #376] @ 0x178 │ │ ldrbeq r5, [fp, #1520] @ 0x5f0 │ │ ldrbeq r5, [fp, #764] @ 0x2fc │ │ ldrbeq r5, [fp, #740] @ 0x2e4 │ │ - ldc2l 12, cr5, [r3, #276] @ 0x114 │ │ + ldc2l 12, cr5, [r3, #456] @ 0x1c8 │ │ ldrbeq r5, [fp, #728] @ 0x2d8 │ │ ldrbeq r5, [fp, #1036] @ 0x40c │ │ ldrbeq r5, [fp, #424] @ 0x1a8 │ │ ldc2l 13, cr12, [r5, #948] @ 0x3b4 │ │ ldc2l 13, cr10, [r5, #208] @ 0xd0 │ │ │ │ 024f0780 : │ │ @@ -1484914,35 +1484914,35 @@ │ │ ldr r0, [pc, #304] @ 24f0e00 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 4, cr7, [r4, #52] @ 0x34 │ │ + ldc2l 4, cr7, [r4, #232] @ 0xe8 │ │ ldrbeq r5, [fp, #364] @ 0x16c │ │ ldrbeq r5, [fp, #332] @ 0x14c │ │ - ldc2l 1, cr0, [r4, #844] @ 0x34c │ │ + ldc2l 2, cr0, [r4] │ │ ldrbeq r5, [fp, #124] @ 0x7c │ │ ldrbeq r5, [fp, #112] @ 0x70 │ │ - ldc2l 5, cr15, [r2, #600] @ 0x258 │ │ + ldc2l 5, cr15, [r2, #780] @ 0x30c │ │ ldrbeq r4, [fp, #3772] @ 0xebc │ │ - ldc2l 10, cr12, [r2, #884] @ 0x374 @ │ │ + ldc2l 11, cr12, [r2, #40] @ 0x28 @ │ │ ldrbeq r4, [fp, #3736] @ 0xe98 │ │ ldc2l 6, cr8, [r4, #536] @ 0x218 │ │ ldrbeq r4, [fp, #3700] @ 0xe74 │ │ ldc2l 10, cr15, [r5, #888] @ 0x378 @ │ │ ldrbeq r4, [fp, #3664] @ 0xe50 │ │ - ldc2l 7, cr7, [r4, #700] @ 0x2bc │ │ + ldc2l 7, cr7, [r4, #880] @ 0x370 │ │ eoreq sl, r6, r8, lsl #19 │ │ ldc2l 3, cr6, [r2, #220] @ 0xdc │ │ eoreq sl, r6, r8, ror #18 │ │ - ldc2l 5, cr7, [r3, #976] @ 0x3d0 │ │ - ldc2l 2, cr2, [r3, #324] @ 0x144 │ │ - ldc2l 12, cr4, [r4, #576] @ 0x240 │ │ + ldc2l 6, cr7, [r3, #132] @ 0x84 │ │ + ldc2l 2, cr2, [r3, #504] @ 0x1f8 │ │ + ldc2l 12, cr4, [r4, #756] @ 0x2f4 │ │ ldrbeq r5, [fp, #76] @ 0x4c │ │ ldc2l 3, cr9, [r4, #576] @ 0x240 │ │ ldrbeq r4, [fp, #3572] @ 0xdf4 │ │ eoreq sl, r6, ip, ror sl │ │ eoreq sl, r6, r4, ror r9 │ │ ldc2l 13, cr6, [r5, #328] @ 0x148 │ │ ldc2l 1, cr9, [r4, #196] @ 0xc4 │ │ @@ -1484962,38 +1484962,38 @@ │ │ eoreq sl, r6, r4, asr r8 │ │ ldc2l 2, cr6, [r2, #76] @ 0x4c │ │ ldrbeq r5, [fp, #36] @ 0x24 │ │ vcadd.f32 d24, d21, d12, #270 │ │ ldrbeq r4, [fp, #4060] @ 0xfdc │ │ ldc2l 2, cr3, [r2, #372] @ 0x174 │ │ ldrbeq r4, [fp, #4024] @ 0xfb8 │ │ - ldc2l 7, cr1, [r3, #52] @ 0x34 │ │ + ldc2l 7, cr1, [r3, #232] @ 0xe8 │ │ ldrbeq r4, [fp, #3988] @ 0xf94 │ │ ldc2l 10, cr7, [r2, #900] @ 0x384 @ │ │ eoreq sl, r6, r8, asr #16 │ │ ldrbeq r4, [fp, #3264] @ 0xcc0 │ │ ldc2l 0, cr11, [r4, #628] @ 0x274 │ │ ldrbeq r5, [fp, #236] @ 0xec │ │ ldc2l 15, cr11, [r5, #612] @ 0x264 │ │ ldrbeq r4, [fp, #3972] @ 0xf84 │ │ ldc2l 7, cr8, [r5, #944] @ 0x3b0 │ │ eoreq sl, r6, r0, ror #16 │ │ ldrbeq r4, [fp, #3936] @ 0xf60 │ │ - ldc2l 4, cr15, [r2, #536] @ 0x218 │ │ + ldc2l 4, cr15, [r2, #716] @ 0x2cc │ │ eoreq sl, r6, r4, lsr r8 │ │ ldrbeq r4, [fp, #3900] @ 0xf3c │ │ ldc2l 2, cr9, [r4, #528] @ 0x210 │ │ eoreq sl, r6, r0, lsr #16 │ │ - ldc2l 1, cr13, [r3, #92] @ 0x5c │ │ - ldc2l 4, cr2, [r3, #740] @ 0x2e4 │ │ + ldc2l 1, cr13, [r3, #272] @ 0x110 │ │ + ldc2l 4, cr2, [r3, #920] @ 0x398 │ │ ldc2l 0, cr11, [r4, #476] @ 0x1dc │ │ ldc2l 2, cr11, [r4, #456] @ 0x1c8 │ │ - ldc2l 6, cr2, [r3, #484] @ 0x1e4 │ │ + ldc2l 6, cr2, [r3, #664] @ 0x298 │ │ ldc2l 9, cr8, [r5, #90] @ 0x5a @ │ │ - ldc2l 14, cr6, [r4, #980] @ 0x3d4 │ │ + ldc2l 15, cr6, [r4, #136] @ 0x88 │ │ │ │ 024f0e04 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #28 │ │ mov r8, r1 │ │ ldr r1, [pc, #2440] @ 24f17a4 │ │ @@ -1485625,18 +1485625,18 @@ │ │ ldrbeq r4, [fp, #2052] @ 0x804 │ │ ldrbeq r4, [fp, #2052] @ 0x804 │ │ ldrbeq r4, [fp, #2036] @ 0x7f4 │ │ ldrbeq r4, [fp, #2016] @ 0x7e0 │ │ ldrbeq r4, [fp, #2016] @ 0x7e0 │ │ ldrbeq r4, [fp, #1972] @ 0x7b4 │ │ eoreq sl, r6, r8, lsr r4 │ │ - ldc2l 3, cr6, [r3, #416] @ 0x1a0 │ │ + ldc2l 3, cr6, [r3, #596] @ 0x254 │ │ ldc2l 9, cr13, [r5, #432] @ 0x1b0 @ │ │ ldrbeq r4, [fp, #1408] @ 0x580 │ │ - ldc2l 11, cr3, [r4, #152] @ 0x98 @ │ │ + ldc2l 11, cr3, [r4, #332] @ 0x14c @ │ │ ldc2l 9, cr13, [r5, #328] @ 0x148 @ │ │ ldrbeq r4, [fp, #1312] @ 0x520 │ │ ldc2l 14, cr7, [lr, #672] @ 0x2a0 │ │ ldrbeq r4, [fp, #1268] @ 0x4f4 │ │ eoreq sl, r6, r4, lsr #3 │ │ ldrbeq r4, [fp, #1288] @ 0x508 │ │ ldrbeq r4, [fp, #1276] @ 0x4fc │ │ @@ -1485651,15 +1485651,15 @@ │ │ eoreq sl, r6, r4, asr #32 │ │ eoreq sl, r6, r8, lsl r0 │ │ ldrbeq r4, [fp, #828] @ 0x33c │ │ strdeq r9, [r6], -r0 @ │ │ eoreq r9, r6, r4, lsl #31 │ │ ldrbeq r4, [fp, #848] @ 0x350 │ │ ldrbeq r4, [fp, #780] @ 0x30c │ │ - ldc2l 0, cr6, [r3, #992] @ 0x3e0 │ │ + ldc2l 1, cr6, [r3, #148] @ 0x94 │ │ ldc2l 7, cr13, [r5, #416] @ 0x1a0 │ │ ldrbeq r4, [fp, #632] @ 0x278 │ │ eoreq r9, r6, ip, lsr #30 │ │ strdeq r9, [r6], -r0 @ │ │ ldrbeq r4, [fp, #652] @ 0x28c │ │ ldrbeq r4, [fp, #584] @ 0x248 │ │ ldc2l 11, cr13, [r4, #340] @ 0x154 @ │ │ @@ -1485682,19 +1485682,19 @@ │ │ ldrbeq r4, [fp, #2596] @ 0xa24 │ │ ldrbeq r4, [fp, #2608] @ 0xa30 │ │ ldrbeq r4, [fp, #2572] @ 0xa0c │ │ ldrbeq r4, [fp, #2492] @ 0x9bc │ │ eoreq sl, r6, ip, lsl #12 │ │ strdeq sl, [r6], -r0 @ │ │ eoreq sl, r6, r4, ror #10 │ │ - ldc2l 5, cr6, [r3, #320] @ 0x140 │ │ + ldc2l 5, cr6, [r3, #500] @ 0x1f4 │ │ ldc2l 11, cr13, [r5, #768] @ 0x300 @ │ │ eoreq sl, r6, r8, lsl #7 │ │ ldrbeq r4, [fp, #1888] @ 0x760 │ │ - ldc2l 13, cr3, [r4, #24] │ │ + ldc2l 13, cr3, [r4, #204] @ 0xcc │ │ ldc2l 11, cr13, [r5, #528] @ 0x210 @ │ │ ldc2l 0, cr8, [lr, #592] @ 0x250 │ │ ldrbeq r4, [fp, #1724] @ 0x6bc │ │ eoreq sl, r6, ip, ror #6 │ │ ldrbeq r4, [fp, #1708] @ 0x6ac │ │ ldrbeq r4, [fp, #1728] @ 0x6c0 │ │ ldrbeq r4, [fp, #1680] @ 0x690 │ │ @@ -1485707,15 +1485707,15 @@ │ │ ldrbeq r4, [fp, #1576] @ 0x628 │ │ mlaeq r6, ip, r2, sl │ │ ldrbeq r4, [fp, #1484] @ 0x5cc │ │ eoreq sl, r6, r0, lsl #5 │ │ eoreq sl, r6, r4, lsl r2 │ │ ldrbeq r4, [fp, #1504] @ 0x5e0 │ │ ldrbeq r4, [fp, #1436] @ 0x59c │ │ - ldc2l 3, cr6, [r3, #528] @ 0x210 │ │ + ldc2l 3, cr6, [r3, #708] @ 0x2c4 │ │ ldc2l 9, cr13, [r5, #488] @ 0x1e8 @ │ │ ldrbeq r4, [fp, #732] @ 0x2dc │ │ mlaeq r6, r0, pc, r9 @ │ │ eoreq r9, r6, r4, asr pc │ │ ldrbeq r4, [fp, #752] @ 0x2f0 │ │ ldrbeq r4, [fp, #684] @ 0x2ac │ │ ldc2l 11, cr13, [r4, #724] @ 0x2d4 @ │ │ @@ -1486157,34 +1486157,34 @@ │ │ mov r3, r8 │ │ bl 270d9b0 │ │ mov r0, r6 │ │ mov r1, r6 │ │ b 24f1e90 │ │ ldc2l 4, cr5, [r2, #300] @ 0x12c │ │ eoreq r9, r6, r0, lsr ip │ │ - ldc2l 0, cr0, [r4, #568] @ 0x238 │ │ - ldc2l 13, cr1, [r4, #216] @ 0xd8 │ │ - ldc2l 2, cr12, [r2, #388] @ 0x184 │ │ + ldc2l 0, cr0, [r4, #748] @ 0x2ec │ │ + ldc2l 13, cr1, [r4, #396] @ 0x18c │ │ + ldc2l 2, cr12, [r2, #568] @ 0x238 │ │ ldc2l 12, cr7, [r2, #68] @ 0x44 │ │ ldc2l 5, cr0, [r5, #108] @ 0x6c │ │ - ldc2l 6, cr15, [r2, #480] @ 0x1e0 │ │ - ldc2l 15, cr15, [r3, #1000] @ 0x3e8 │ │ - ldc2l 6, cr10, [r3, #700] @ 0x2bc │ │ - ldc2l 3, cr1, [r3, #900] @ 0x384 │ │ - ldc2l 3, cr4, [r3, #744] @ 0x2e8 │ │ + ldc2l 6, cr15, [r2, #660] @ 0x294 │ │ + ldc2l 0, cr0, [r4, #156] @ 0x9c │ │ + ldc2l 6, cr10, [r3, #880] @ 0x370 │ │ + ldc2l 4, cr1, [r3, #56] @ 0x38 │ │ + ldc2l 3, cr4, [r3, #924] @ 0x39c │ │ ldc2l 15, cr13, [r4, #108] @ 0x6c │ │ - ldc2l 3, cr14, [r3, #116] @ 0x74 │ │ - ldc2l 15, cr15, [r3, #504] @ 0x1f8 │ │ - ldc2l 6, cr10, [r3, #204] @ 0xcc │ │ - ldc2l 3, cr1, [r3, #404] @ 0x194 │ │ - ldc2l 15, cr15, [r3, #120] @ 0x78 │ │ + ldc2l 3, cr14, [r3, #296] @ 0x128 │ │ + ldc2l 15, cr15, [r3, #684] @ 0x2ac │ │ + ldc2l 6, cr10, [r3, #384] @ 0x180 │ │ + ldc2l 3, cr1, [r3, #584] @ 0x248 │ │ + ldc2l 15, cr15, [r3, #300] @ 0x12c │ │ ldc2l 12, cr15, [r4, #728] @ 0x2d8 │ │ - ldc2l 2, cr1, [r3, #996] @ 0x3e4 │ │ - ldc2l 5, cr6, [r3, #144] @ 0x90 │ │ - ldc2l 4, cr15, [r2, #96] @ 0x60 │ │ + ldc2l 3, cr1, [r3, #152] @ 0x98 │ │ + ldc2l 5, cr6, [r3, #324] @ 0x144 │ │ + ldc2l 4, cr15, [r2, #276] @ 0x114 │ │ strdeq r9, [r6], -r4 @ │ │ eoreq r9, r6, r8, ror #14 │ │ ldc2l 2, cr7, [r5, #200] @ 0xc8 │ │ eoreq r9, r6, r8, lsl #13 │ │ │ │ 024f2090 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ @@ -1486395,18 +1486395,18 @@ │ │ mov r1, r4 │ │ bl 270e130 │ │ add r0, sp, #4 │ │ mov r1, r4 │ │ bl 270e280 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2l 11, cr13, [r3, #272] @ 0x110 @ │ │ - vcadd.f32 d21, d20, d8, #270 │ │ - ldc2l 11, cr0, [r3, #692] @ 0x2b4 @ │ │ - ldc2l 0, cr15, [r3, #76] @ 0x4c │ │ + ldc2l 11, cr13, [r3, #452] @ 0x1c4 @ │ │ + ldc2l 8, cr5, [r4, #724] @ 0x2d4 │ │ + ldc2l 11, cr0, [r3, #872] @ 0x368 @ │ │ + ldc2l 0, cr15, [r3, #256] @ 0x100 │ │ │ │ 024f23e0 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r5, r1 │ │ mov r4, r0 │ │ bl 270ce80 │ │ @@ -1486447,17 +1486447,17 @@ │ │ ldr r0, [pc, #32] @ 24f24a4 │ │ mov r1, #6 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ pop {r4, r5, fp, pc} │ │ ldc2l 13, cr6, [r5, #820] @ 0x334 │ │ - ldc2l 11, cr4, [r4, #480] @ 0x1e0 @ │ │ - ldc2l 10, cr0, [r3, #628] @ 0x274 @ │ │ - ldc2l 15, cr2, [r3, #892] @ 0x37c │ │ + ldc2l 11, cr4, [r4, #660] @ 0x294 @ │ │ + ldc2l 10, cr0, [r3, #808] @ 0x328 @ │ │ + ldc2l 0, cr3, [r3, #48] @ 0x30 │ │ ldc2l 13, cr6, [r5, #340] @ 0x154 │ │ │ │ 024f24a8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #284 @ 0x11c │ │ sub sp, sp, #1024 @ 0x400 │ │ @@ -1487601,15 +1487601,15 @@ │ │ ldrbeq r3, [fp, #764] @ 0x2fc │ │ ldrbeq r5, [fp, #160] @ 0xa0 │ │ ldrbeq r3, [fp, #1672] @ 0x688 │ │ ldrbeq r3, [fp, #700] @ 0x2bc │ │ ldrbeq r5, [fp, #116] @ 0x74 │ │ ldrbeq r3, [fp, #1200] @ 0x4b0 │ │ ldrbeq r5, [fp, #196] @ 0xc4 │ │ - ldc2l 4, cr11, [r3, #812] @ 0x32c │ │ + ldc2l 4, cr11, [r3, #992] @ 0x3e0 │ │ ldr r0, [pc, #3944] @ 24f4604 │ │ ldr r0, [pc, r0] │ │ ldr r2, [pc, #3940] @ 24f4608 │ │ add r0, r0, #1 │ │ add r2, pc, r2 │ │ str r0, [r2] │ │ ldr r2, [fp, #24] │ │ @@ -1487688,15 +1487688,15 @@ │ │ add r2, r0, r2, lsl #2 │ │ add r3, pc, r3 │ │ b 24f3068 │ │ ldrbeq r3, [fp, #1408] @ 0x580 │ │ ldrbeq r4, [fp, #2144] @ 0x860 │ │ ldrbeq r4, [fp, #2584] @ 0xa18 │ │ ldrbeq r4, [fp, #4032] @ 0xfc0 │ │ - ldc2l 3, cr11, [r3, #764] @ 0x2fc │ │ + ldc2l 3, cr11, [r3, #944] @ 0x3b0 │ │ ldrbeq r4, [fp, #2096] @ 0x830 │ │ ldrbeq r4, [fp, #3852] @ 0xf0c │ │ ldrbeq r3, [fp, #1260] @ 0x4ec │ │ ldrbeq r4, [fp, #3804] @ 0xedc │ │ ldrbeq r4, [fp, #3812] @ 0xee4 │ │ ldrdeq r8, [r6], -r0 @ │ │ ldr r0, [pc, #3624] @ 24f4638 │ │ @@ -1487787,19 +1487787,19 @@ │ │ cmp r4, #64 @ 0x40 │ │ bcs 24f3c50 │ │ mov r2, r4 │ │ b 24f3c9c │ │ ldrbeq r3, [fp, #24] │ │ ldrbeq r3, [fp, #1328] @ 0x530 │ │ ldrbeq r4, [fp, #3168] @ 0xc60 │ │ - ldc2l 6, cr7, [r3, #732] @ 0x2dc │ │ - ldc2l 9, cr12, [r3, #284] @ 0x11c @ │ │ + ldc2l 6, cr7, [r3, #912] @ 0x390 │ │ + ldc2l 9, cr12, [r3, #374] @ 0x176 @ │ │ eoreq r8, r6, r0, lsl #25 │ │ ldrbeq r4, [fp, #2444] @ 0x98c │ │ - ldc2l 1, cr11, [r3, #844] @ 0x34c │ │ + ldc2l 2, cr11, [r3] │ │ eoreq r8, r6, r4, asr #24 │ │ ldr r0, [pc, #3788] @ 24f4864 │ │ mov r1, r4 │ │ mov r2, r6 │ │ movw r3, #3029 @ 0xbd5 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ @@ -1487835,18 +1487835,18 @@ │ │ ldr r3, [pc, #3676] @ 24f4880 │ │ add r0, pc, r0 │ │ add r2, r0, r2, lsl #2 │ │ add r3, pc, r3 │ │ b 24f3068 │ │ ldrbeq r3, [fp, #780] @ 0x30c │ │ ldrbeq r3, [fp, #2268] @ 0x8dc │ │ - ldc2l 14, cr2, [r4, #1020] @ 0x3fc │ │ + ldc2l 15, cr2, [r4, #176] @ 0xb0 │ │ ldc2l 2, cr6, [r4, #104] @ 0x68 │ │ - ldc2l 1, cr11, [r3, #428] @ 0x1ac │ │ - ldc2l 14, cr5, [r3, #920] @ 0x398 │ │ + ldc2l 1, cr11, [r3, #608] @ 0x260 │ │ + ldc2l 15, cr5, [r3, #76] @ 0x4c │ │ ldrbeq r3, [fp, #344] @ 0x158 │ │ ldrbeq r3, [fp, #724] @ 0x2d4 │ │ ldr r0, [pc, #4060] @ 24f4a34 │ │ ldr r2, [fp, #48] @ 0x30 │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #4052] @ 24f4a38 │ │ ldr r1, [pc, r1] │ │ @@ -1487915,15 +1487915,15 @@ │ │ ldrbeq r2, [fp, #3644] @ 0xe3c │ │ ldrbeq r4, [fp, #3044] @ 0xbe4 │ │ ldrbeq r4, [fp, #3148] @ 0xc4c │ │ ldrbeq r3, [fp, #456] @ 0x1c8 │ │ ldrbeq r2, [fp, #3576] @ 0xdf8 │ │ ldrbeq r4, [fp, #3000] @ 0xbb8 │ │ ldrbeq r2, [fp, #3560] @ 0xde8 │ │ - ldc2l 0, cr11, [r3, #92] @ 0x5c │ │ + ldc2l 0, cr11, [r3, #272] @ 0x110 │ │ ldrbeq r4, [fp, #2964] @ 0xb94 │ │ ldrbeq r4, [fp, #3016] @ 0xbc8 │ │ ldrbeq r4, [fp, #3000] @ 0xbb8 │ │ ldr r0, [pc, #4028] @ 24f4b4c │ │ mov r1, r4 │ │ mov r2, r6 │ │ movw r3, #3045 @ 0xbe5 │ │ @@ -1488111,15 +1488111,15 @@ │ │ ldrbeq r4, [fp, #2144] @ 0x860 │ │ ldc2l 15, cr3, [r2, #188] @ 0xbc │ │ ldrbeq r4, [fp, #2148] @ 0x864 │ │ ldrbeq r2, [fp, #3584] @ 0xe00 │ │ ldrbeq r2, [fp, #2620] @ 0xa3c │ │ ldrbeq r4, [fp, #1352] @ 0x548 │ │ ldrbeq r2, [fp, #3092] @ 0xc14 │ │ - ldc2l 12, cr10, [r3, #188] @ 0xbc │ │ + ldc2l 12, cr10, [r3, #368] @ 0x170 │ │ ldc2l 7, cr4, [r5, #352] @ 0x160 │ │ ldc2l 0, cr2, [r5, #424] @ 0x1a8 │ │ ldrbeq r2, [fp, #2520] @ 0x9d8 │ │ ldrbeq r4, [fp, #2060] @ 0x80c │ │ ldrbeq r4, [fp, #1940] @ 0x794 │ │ ldr r1, [pc, #4040] @ 24f4e70 │ │ mov r3, #320 @ 0x140 │ │ @@ -1488208,15 +1488208,15 @@ │ │ b 24fab38 │ │ ldc2l 14, cr3, [r2, #300] @ 0x12c │ │ ldrbeq r4, [fp, #2004] @ 0x7d4 │ │ ldrbeq r2, [fp, #3392] @ 0xd40 │ │ ldrbeq r2, [fp, #3384] @ 0xd38 │ │ ldrbeq r3, [fp, #496] @ 0x1f0 │ │ ldrbeq r3, [fp, #3848] @ 0xf08 │ │ - ldc2l 8, cr11, [r3, #732] @ 0x2dc │ │ + vcadd.f32 , , q10, #270 │ │ ldrbeq r2, [fp, #3300] @ 0xce4 │ │ ldrbeq r2, [fp, #3288] @ 0xcd8 │ │ ldrbeq r4, [fp, #1764] @ 0x6e4 │ │ ldrbeq r2, [fp, #2292] @ 0x8f4 │ │ ldrbeq r2, [fp, #3220] @ 0xc94 │ │ ldrbeq r2, [fp, #2244] @ 0x8c4 │ │ ldrbeq r2, [fp, #3176] @ 0xc68 │ │ @@ -1488602,15 +1488602,15 @@ │ │ ldc2l 2, cr14, [r4, #56] @ 0x38 │ │ ldrbeq r2, [fp, #1532] @ 0x5fc │ │ ldc2l 4, cr0, [r2, #240] @ 0xf0 │ │ ldrbeq r2, [fp, #1488] @ 0x5d0 │ │ ldrbeq r2, [fp, #1480] @ 0x5c8 │ │ ldrbeq r2, [fp, #2688] @ 0xa80 │ │ ldrbeq r3, [fp, #1944] @ 0x798 │ │ - ldc2l 10, cr8, [r3, #508] @ 0x1fc @ │ │ + ldc2l 10, cr8, [r3, #688] @ 0x2b0 @ │ │ ldc2l 1, cr14, [r4, #264] @ 0x108 │ │ ldr r0, [pc, #3936] @ 24f55a4 │ │ mov r1, r8 │ │ ldr r2, [pc, #3932] @ 24f55a8 │ │ mov r9, r8 │ │ add r0, pc, r0 │ │ str r6, [sp] │ │ @@ -1488733,31 +1488733,31 @@ │ │ b 24f48b8 │ │ ldrbeq r2, [fp, #1328] @ 0x530 │ │ ldc2l 3, cr0, [r2, #448] @ 0x1c0 │ │ ldrbeq r2, [fp, #1284] @ 0x504 │ │ ldrbeq r2, [fp, #1276] @ 0x4fc │ │ ldrbeq r2, [fp, #2484] @ 0x9b4 │ │ ldrbeq r3, [fp, #1740] @ 0x6cc │ │ - ldc2l 4, cr3, [r3, #288] @ 0x120 │ │ + ldc2l 4, cr3, [r3, #468] @ 0x1d4 │ │ ldc2l 0, cr14, [r4, #568] @ 0x238 │ │ ldrbeq r2, [fp, #1148] @ 0x47c │ │ ldc2l 2, cr0, [r2, #752] @ 0x2f0 │ │ ldrbeq r2, [fp, #1104] @ 0x450 │ │ ldrbeq r2, [fp, #1096] @ 0x448 │ │ ldrbeq r2, [fp, #2304] @ 0x900 │ │ ldrbeq r3, [fp, #1560] @ 0x618 │ │ - ldc2l 4, cr8, [r2, #344] @ 0x158 │ │ + ldc2l 4, cr8, [r2, #524] @ 0x20c │ │ ldc2l 15, cr13, [r4, #744] @ 0x2e8 │ │ ldrbeq r2, [fp, #936] @ 0x3a8 │ │ ldc2l 1, cr0, [r2, #928] @ 0x3a0 │ │ ldrbeq r2, [fp, #892] @ 0x37c │ │ ldrbeq r2, [fp, #884] @ 0x374 │ │ ldrbeq r2, [fp, #2092] @ 0x82c │ │ ldrbeq r3, [fp, #1348] @ 0x544 │ │ - ldc2l 7, cr12, [r2, #68] @ 0x44 │ │ + ldc2l 7, cr12, [r2, #248] @ 0xf8 │ │ str r5, [r4, r1, lsl #2] │ │ add r0, r0, #1 │ │ ldr r1, [pc, #3920] @ 24f57e4 │ │ add r1, pc, r1 │ │ str r0, [r1] │ │ ldr r1, [pc, #3912] @ 24f57e8 │ │ ldr r1, [pc, r1] │ │ @@ -1488935,15 +1488935,15 @@ │ │ ldc2l 13, cr13, [r4, #776] @ 0x308 │ │ ldrbeq r2, [fp, #432] @ 0x1b0 │ │ ldc2l 15, cr15, [r1, #960] @ 0x3c0 │ │ ldrbeq r2, [fp, #388] @ 0x184 │ │ ldrbeq r2, [fp, #380] @ 0x17c │ │ ldrbeq r2, [fp, #1588] @ 0x634 │ │ ldrbeq r3, [fp, #844] @ 0x34c │ │ - ldc2l 0, cr4, [r4, #136] @ 0x88 │ │ + ldc2l 0, cr4, [r4, #316] @ 0x13c │ │ ldc2l 12, cr13, [r4, #1000] @ 0x3e8 │ │ ldrbeq r2, [fp, #232] @ 0xe8 │ │ ldc2l 15, cr15, [r1, #160] @ 0xa0 │ │ ldrbeq r2, [fp, #188] @ 0xbc │ │ ldrbeq r2, [fp, #180] @ 0xb4 │ │ ldrbeq r2, [fp, #1388] @ 0x56c │ │ ldrbeq r3, [fp, #644] @ 0x284 │ │ @@ -1489064,15 +1489064,15 @@ │ │ sub r1, r3, #1 │ │ cmp r1, #64 @ 0x40 │ │ bcs 24f4b98 │ │ mov r0, r1 │ │ b 24f4bb8 │ │ ldrbeq r2, [fp, #1232] @ 0x4d0 │ │ ldrbeq r3, [fp, #488] @ 0x1e8 │ │ - ldc2l 15, cr9, [r3, #108] @ 0x6c │ │ + ldc2l 15, cr9, [r3, #288] @ 0x120 │ │ ldc2l 11, cr13, [r4, #584] @ 0x248 @ │ │ ldr r5, [pc, #3988] @ 24f5d10 │ │ ldr r5, [pc, r5] │ │ ldr r1, [pc, #3984] @ 24f5d14 │ │ rsb r2, r5, #65 @ 0x41 │ │ ldr r0, [pc, #3980] @ 24f5d18 │ │ mov r3, #1 │ │ @@ -1489258,20 +1489258,20 @@ │ │ sub r1, r3, #1 │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f508c │ │ str r7, [sl, r1, lsl #2] │ │ b 24f50e0 │ │ ldc2l 8, cr13, [r4, #592] @ 0x250 │ │ - ldc2l 0, cr12, [r2, #316] @ 0x13c │ │ + ldc2l 0, cr12, [r2, #496] @ 0x1f0 │ │ ldc2l 15, cr0, [r5, #1016] @ 0x3f8 │ │ ldc2l 10, cr15, [r1, #664] @ 0x298 @ │ │ ldc2l 10, cr15, [r1, #596] @ 0x254 @ │ │ ldc2l 1, cr9, [r5, #584] @ 0x248 │ │ - ldc2l 0, cr4, [r3, #104] @ 0x68 │ │ + ldc2l 0, cr4, [r3, #284] @ 0x11c │ │ ldr r0, [pc, #4016] @ 24f6044 │ │ movw r3, #1948 @ 0x79c │ │ ldr r2, [pc, #4012] @ 24f6048 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r7, [sl, r0, lsl #2] │ │ @@ -1489320,24 +1489320,24 @@ │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f5198 │ │ str r7, [sl, r1, lsl #2] │ │ b 24f51ec │ │ - ldc2l 11, cr9, [r2, #504] @ 0x1f8 @ │ │ + ldc2l 11, cr9, [r2, #684] @ 0x2ac @ │ │ ldc2l 11, cr5, [r4, #128] @ 0x80 @ │ │ ldc2l 0, cr6, [r2, #216] @ 0xd8 │ │ - ldc2l 13, cr1, [r3, #736] @ 0x2e0 │ │ - ldc2l 11, cr9, [r2, #124] @ 0x7c @ │ │ - ldc2l 0, cr8, [r3, #148] @ 0x94 │ │ - ldc2l 0, cr8, [r3, #72] @ 0x48 │ │ + ldc2l 13, cr1, [r3, #916] @ 0x394 │ │ + ldc2l 11, cr9, [r2, #304] @ 0x130 @ │ │ + ldc2l 0, cr8, [r3, #328] @ 0x148 │ │ + ldc2l 0, cr8, [r3, #252] @ 0xfc │ │ ldc2l 10, cr12, [r5, #860] @ 0x35c @ │ │ ldc2l 7, cr13, [r4, #244] @ 0xf4 │ │ - ldc2l 13, cr15, [r2, #452] @ 0x1c4 │ │ + ldc2l 13, cr15, [r2, #632] @ 0x278 │ │ ldc2l 0, cr9, [r5, #464] @ 0x1d0 │ │ ldr r0, [pc, #4024] @ 24f6158 │ │ movw r3, #1957 @ 0x7a5 │ │ ldr r2, [pc, #4020] @ 24f615c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1489389,21 +1489389,21 @@ │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f52a4 │ │ str r7, [sl, r1, lsl #2] │ │ b 24f52f8 │ │ ldc2l 11, cr9, [r4, #784] @ 0x310 @ │ │ ldc2l 11, cr10, [r5, #320] @ 0x140 @ │ │ - ldc2l 10, cr9, [r2, #280] @ 0x118 @ │ │ - ldc2l 12, cr15, [r2, #1012] @ 0x3f4 │ │ + ldc2l 10, cr9, [r2, #460] @ 0x1cc @ │ │ + ldc2l 13, cr15, [r2, #168] @ 0xa8 │ │ ldc2l 4, cr15, [r4, #444] @ 0x1bc │ │ ldc2l 13, cr0, [r5, #924] @ 0x39c │ │ vcadd.f32 d23, d4, d21, #270 │ │ ldc2l 10, cr10, [r5, #688] @ 0x2b0 @ │ │ - ldc2l 13, cr13, [r2, #156] @ 0x9c │ │ + ldc2l 13, cr13, [r2, #336] @ 0x150 │ │ ldrbeq r2, [fp, #3664] @ 0xe50 │ │ ldc2l 3, cr11, [r5, #488] @ 0x1e8 │ │ ldr r0, [pc, #4016] @ 24f625c │ │ movw r3, #1967 @ 0x7af │ │ ldr r2, [pc, #4012] @ 24f6260 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1489454,23 +1489454,23 @@ │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f53ac │ │ str r7, [sl, r1, lsl #2] │ │ b 24f5400 │ │ - ldc2l 14, cr7, [r3, #584] @ 0x248 │ │ - ldc2l 7, cr13, [r3, #120] @ 0x78 │ │ + ldc2l 14, cr7, [r3, #764] @ 0x2fc │ │ + ldc2l 7, cr13, [r3, #300] @ 0x12c │ │ ldc2l 10, cr9, [r4, #416] @ 0x1a0 @ │ │ - ldc2l 14, cr3, [r4, #604] @ 0x25c │ │ + ldc2l 14, cr3, [r4, #784] @ 0x310 │ │ ldrbeq r2, [fp, #3440] @ 0xd70 │ │ - ldc2l 8, cr9, [r3, #480] @ 0x1e0 │ │ + vcadd.f32 d25, d19, d21, #270 │ │ ldc2l 9, cr10, [r5, #408] @ 0x198 @ │ │ - ldc2l 13, cr7, [r3, #864] @ 0x360 │ │ - ldc2l 13, cr7, [r3, #784] @ 0x310 │ │ + ldc2l 14, cr7, [r3, #20] │ │ + ldc2l 13, cr7, [r3, #964] @ 0x3c4 │ │ ldc2l 4, cr13, [r4, #1004] @ 0x3ec │ │ ldr r0, [pc, #4028] @ 24f6370 │ │ movw r3, #1977 @ 0x7b9 │ │ ldr r2, [pc, #4024] @ 24f6374 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1489654,26 +1489654,26 @@ │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f56f0 │ │ str r7, [sl, r1, lsl #2] │ │ b 24f5744 │ │ ldc2l 9, cr0, [r5, #204] @ 0xcc @ │ │ - ldc2l 5, cr9, [r3, #124] @ 0x7c │ │ + ldc2l 5, cr9, [r3, #304] @ 0x130 │ │ ldrbeq r1, [fp, #1264] @ 0x4f0 │ │ ldrbeq r1, [fp, #988] @ 0x3dc │ │ ldc2l 9, cr0, [r5, #84] @ 0x54 @ │ │ - ldc2l 4, cr9, [r3, #908] @ 0x38c │ │ + ldc2l 5, cr9, [r3, #64] @ 0x40 │ │ ldrbeq r2, [fp, #2876] @ 0xb3c │ │ ldc2l 4, cr15, [r1, #560] @ 0x230 │ │ - ldc2l 4, cr9, [r3, #700] @ 0x2bc │ │ + ldc2l 4, cr9, [r3, #880] @ 0x370 │ │ ldrbeq r2, [fp, #2080] @ 0x820 │ │ ldrbeq r1, [fp, #1144] @ 0x478 │ │ ldc2l 4, cr15, [r1, #304] @ 0x130 │ │ - ldc2l 4, cr9, [r3, #444] @ 0x1bc │ │ + ldc2l 4, cr9, [r3, #624] @ 0x270 │ │ ldrbeq r1, [fp, #1088] @ 0x440 │ │ ldrbeq r3, [fp, #76] @ 0x4c │ │ ldrbeq r2, [fp, #4064] @ 0xfe0 │ │ ldrbeq r1, [fp, #1056] @ 0x420 │ │ ldrbeq r2, [fp, #2704] @ 0xa90 │ │ ldrbeq r1, [fp, #1068] @ 0x42c │ │ ldrbeq r2, [fp, #2700] @ 0xa8c │ │ @@ -1489733,15 +1489733,15 @@ │ │ str r7, [sl, r1, lsl #2] │ │ b 24f5848 │ │ ldrbeq r2, [fp, #3980] @ 0xf8c │ │ ldrbeq r1, [fp, #1004] @ 0x3ec │ │ ldrbeq r1, [fp, #424] @ 0x1a8 │ │ ldrbeq r1, [fp, #404] @ 0x194 │ │ ldrbeq r1, [fp, #2592] @ 0xa20 │ │ - ldc2l 3, cr9, [r3, #764] @ 0x2fc │ │ + ldc2l 3, cr9, [r3, #944] @ 0x3b0 │ │ ldrbeq r2, [fp, #3912] @ 0xf48 │ │ ldrbeq r2, [fp, #3800] @ 0xed8 │ │ ldrbeq r2, [fp, #3784] @ 0xec8 │ │ ldc2l 14, cr2, [r5, #256] @ 0x100 │ │ ldr r0, [pc, #3992] @ 24f6794 │ │ movw r3, #2008 @ 0x7d8 │ │ ldr r2, [pc, #3988] @ 24f6798 │ │ @@ -1489869,19 +1489869,19 @@ │ │ ldrbeq r2, [fp, #3548] @ 0xddc │ │ ldc2l 1, cr15, [r1, #624] @ 0x270 │ │ ldrbeq r2, [fp, #3500] @ 0xdac │ │ ldrbeq r0, [fp, #3936] @ 0xf60 │ │ ldrbeq r2, [fp, #3364] @ 0xd24 │ │ ldc2l 3, cr2, [r2, #972] @ 0x3cc │ │ ldc2l 12, cr2, [r5, #512] @ 0x200 │ │ - ldc2l 1, cr9, [r3, #316] @ 0x13c │ │ + ldc2l 1, cr9, [r3, #496] @ 0x1f0 │ │ ldrbeq r0, [fp, #3856] @ 0xf10 │ │ ldrbeq r2, [fp, #3376] @ 0xd30 │ │ ldc2l 5, cr0, [r5, #360] @ 0x168 │ │ - ldc2l 1, cr9, [r3, #76] @ 0x4c │ │ + ldc2l 1, cr9, [r3, #256] @ 0x100 │ │ ldrbeq r2, [fp, #3324] @ 0xcfc │ │ ldrbeq r0, [fp, #4040] @ 0xfc8 │ │ ldrbeq r2, [fp, #3204] @ 0xc84 │ │ ldrbeq r1, [fp, #224] @ 0xe0 │ │ ldr r0, [pc, #3952] @ 24f699c │ │ movw r3, #2024 @ 0x7e8 │ │ ldr r2, [pc, #3948] @ 24f69a0 │ │ @@ -1489936,15 +1489936,15 @@ │ │ str r7, [sl, r1, lsl #2] │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ b 24f5b80 │ │ ldrbeq r0, [fp, #3728] @ 0xe90 │ │ ldrbeq r0, [fp, #3712] @ 0xe80 │ │ ldrbeq r1, [fp, #1800] @ 0x708 │ │ ldrbeq r2, [fp, #1068] @ 0x42c │ │ - ldc2l 0, cr9, [r3, #652] @ 0x28c │ │ + ldc2l 0, cr9, [r3, #832] @ 0x340 │ │ ldc2l 0, cr15, [r1, #80] @ 0x50 │ │ ldrbeq r2, [fp, #3112] @ 0xc28 │ │ ldrbeq r2, [fp, #2996] @ 0xbb4 │ │ ldrbeq r2, [fp, #2988] @ 0xbac │ │ ldrbeq r2, [fp, #2960] @ 0xb90 │ │ ldrbeq r2, [fp, #3044] @ 0xbe4 │ │ ldr r0, [pc, #3948] @ 24f6a9c │ │ @@ -1490129,23 +1490129,23 @@ │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f5e44 │ │ mov r0, #3 │ │ str r0, [sl, r1, lsl #2] │ │ b 24f5e9c │ │ ldrbeq r2, [fp, #2400] @ 0x960 │ │ - ldc2l 13, cr2, [r4, #768] @ 0x300 │ │ - ldc2l 6, cr12, [r2, #116] @ 0x74 │ │ + ldc2l 13, cr2, [r4, #948] @ 0x3b4 │ │ + ldc2l 6, cr12, [r2, #296] @ 0x128 │ │ ldrbeq r0, [fp, #3836] @ 0xefc │ │ vcadd.f32 , q2, q6, #270 │ │ - ldc2l 13, cr8, [r3, #236] @ 0xec │ │ + ldc2l 13, cr8, [r3, #416] @ 0x1a0 │ │ ldrbeq r0, [fp, #3748] @ 0xea4 │ │ ldrbeq r0, [fp, #3740] @ 0xe9c │ │ ldc2l 3, cr6, [r4, #12] │ │ - ldc2l 12, cr8, [r3, #1020] @ 0x3fc │ │ + ldc2l 13, cr8, [r3, #176] @ 0xb0 │ │ ldrbeq r0, [fp, #3688] @ 0xe68 │ │ ldrbeq r2, [fp, #24] │ │ ldrbeq r0, [fp, #3652] @ 0xe44 │ │ ldrbeq r0, [fp, #3260] @ 0xcbc │ │ ldr r0, [pc, #3948] @ 24f6db8 │ │ mov r3, #2048 @ 0x800 │ │ ldr r2, [pc, #3944] @ 24f6dbc │ │ @@ -1490200,28 +1490200,28 @@ │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f5f64 │ │ str r7, [sl, r1, lsl #2] │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ b 24f5fbc │ │ - ldc2l 0, cr15, [r2, #620] @ 0x26c │ │ - ldc2l 12, cr8, [r3, #636] @ 0x27c │ │ - ldc2l 11, cr12, [r3, #608] @ 0x260 @ │ │ + ldc2l 0, cr15, [r2, #800] @ 0x320 │ │ + ldc2l 12, cr8, [r3, #816] @ 0x330 │ │ + ldc2l 11, cr12, [r3, #788] @ 0x314 @ │ │ ldrbeq r0, [fp, #3560] @ 0xde8 │ │ ldc2l 7, cr7, [r4, #320] @ 0x140 │ │ - ldc2l 12, cr8, [r3, #252] @ 0xfc │ │ + ldc2l 12, cr8, [r3, #432] @ 0x1b0 │ │ ldrbeq r0, [fp, #3496] @ 0xda8 │ │ ldc2l 2, cr6, [r4, #76] @ 0x4c │ │ - ldc2l 12, cr8, [r3, #60] @ 0x3c │ │ + ldc2l 12, cr8, [r3, #240] @ 0xf0 │ │ ldrbeq r0, [fp, #3448] @ 0xd78 │ │ ldrbeq r0, [fp, #3420] @ 0xd5c │ │ ldrbeq r0, [fp, #3028] @ 0xbd4 │ │ - ldc2l 15, cr14, [r2, #716] @ 0x2cc │ │ - ldc2l 11, cr8, [r3, #732] @ 0x2dc @ │ │ + ldc2l 15, cr14, [r2, #896] @ 0x380 │ │ + ldc2l 11, cr8, [r3, #912] @ 0x390 @ │ │ ldr r0, [pc, #3940] @ 24f6ed0 │ │ movw r3, #2058 @ 0x80a │ │ ldr r2, [pc, #3936] @ 24f6ed4 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r7, [sl, r0, lsl #2] │ │ @@ -1490268,27 +1490268,27 @@ │ │ ldr r3, [pc, #4012] @ 24f6fd4 │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f6074 │ │ str r7, [sl, r1, lsl #2] │ │ b 24f60c8 │ │ - ldc2l 6, cr4, [r3, #452] @ 0x1c4 │ │ + ldc2l 6, cr4, [r3, #632] @ 0x278 │ │ ldrbeq r0, [fp, #3332] @ 0xd04 │ │ ldc2l 6, cr7, [r4, #336] @ 0x150 │ │ - ldc2l 11, cr8, [r3, #268] @ 0x10c @ │ │ + ldc2l 11, cr8, [r3, #448] @ 0x1c0 @ │ │ ldrbeq r0, [fp, #3244] @ 0xcac │ │ ldc2l 1, cr6, [r4, #92] @ 0x5c │ │ - ldc2l 11, cr8, [r3, #76] @ 0x4c @ │ │ + ldc2l 11, cr8, [r3, #256] @ 0x100 @ │ │ ldrbeq r0, [fp, #3196] @ 0xc7c │ │ ldrbeq r0, [fp, #3168] @ 0xc60 │ │ ldrbeq r0, [fp, #2776] @ 0xad8 │ │ - ldc2l 14, cr14, [r2, #732] @ 0x2dc │ │ - ldc2l 10, cr8, [r3, #748] @ 0x2ec @ │ │ - ldc2l 6, cr2, [r3, #168] @ 0xa8 │ │ + ldc2l 14, cr14, [r2, #912] @ 0x390 │ │ + ldc2l 10, cr8, [r3, #928] @ 0x3a0 @ │ │ + ldc2l 6, cr2, [r3, #348] @ 0x15c │ │ ldrbeq r0, [fp, #3080] @ 0xc08 │ │ ldr r0, [pc, #3932] @ 24f6fd8 │ │ mov r3, #2064 @ 0x810 │ │ ldr r2, [pc, #3928] @ 24f6fdc │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1490340,23 +1490340,23 @@ │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f6184 │ │ str r7, [sl, r1, lsl #2] │ │ b 24f61d8 │ │ ldc2l 5, cr7, [r4, #288] @ 0x120 │ │ - ldc2l 10, cr8, [r3, #220] @ 0xdc @ │ │ + ldc2l 10, cr8, [r3, #400] @ 0x190 @ │ │ ldrbeq r0, [fp, #2976] @ 0xba0 │ │ ldc2l 0, cr6, [r4, #44] @ 0x2c │ │ - ldc2l 10, cr8, [r3, #28] @ │ │ + ldc2l 10, cr8, [r3, #208] @ 0xd0 @ │ │ ldrbeq r0, [fp, #2928] @ 0xb70 │ │ ldrbeq r0, [fp, #2900] @ 0xb54 │ │ ldrbeq r0, [fp, #2508] @ 0x9cc │ │ - ldc2l 13, cr14, [r2, #684] @ 0x2ac │ │ - ldc2l 9, cr8, [r3, #350] @ 0x15e @ │ │ + ldc2l 13, cr14, [r2, #864] @ 0x360 │ │ + ldc2l 9, cr8, [r3, #440] @ 0x1b8 @ │ │ ldc2l 13, cr12, [r4, #556] @ 0x22c │ │ ldr r0, [pc, #3924] @ 24f70e0 │ │ movw r3, #2074 @ 0x81a │ │ ldr r2, [pc, #3920] @ 24f70e4 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1490405,24 +1490405,24 @@ │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f628c │ │ str r7, [sl, r1, lsl #2] │ │ b 24f62e0 │ │ ldrbeq r0, [fp, #2812] @ 0xafc │ │ ldc2l 4, cr7, [r4, #240] @ 0xf0 │ │ - ldc2l 9, cr8, [r3, #86] @ 0x56 @ │ │ + ldc2l 9, cr8, [r3, #176] @ 0xb0 @ │ │ ldrbeq r0, [fp, #2708] @ 0xa94 │ │ ldc2l 14, cr5, [r4, #1020] @ 0x3fc │ │ - ldc2l 8, cr8, [r3, #1004] @ 0x3ec │ │ + ldc2l 9, cr8, [r3, #80] @ 0x50 @ │ │ ldrbeq r0, [fp, #2660] @ 0xa64 │ │ ldrbeq r0, [fp, #2632] @ 0xa48 │ │ ldrbeq r0, [fp, #2240] @ 0x8c0 │ │ - ldc2l 12, cr14, [r2, #636] @ 0x27c │ │ - vcadd.f32 d24, d19, d19, #270 │ │ - ldc2l 13, cr11, [r2, #1008] @ 0x3f0 │ │ + ldc2l 12, cr14, [r2, #816] @ 0x330 │ │ + ldc2l 8, cr8, [r3, #832] @ 0x340 │ │ + ldc2l 14, cr11, [r2, #164] @ 0xa4 │ │ ldrbeq r0, [fp, #2544] @ 0x9f0 │ │ ldr r0, [pc, #3924] @ 24f71e8 │ │ mov r3, #2080 @ 0x820 │ │ ldr r2, [pc, #3920] @ 24f71ec │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1490474,23 +1490474,23 @@ │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f63a0 │ │ mov r0, #3 │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ str r0, [sl, r1, lsl #2] │ │ b 24f63fc │ │ ldc2l 3, cr7, [r4, #208] @ 0xd0 │ │ - vcadd.f32 d24, d3, d19, #270 │ │ + ldc2l 8, cr8, [r3, #320] @ 0x140 │ │ ldrbeq r0, [fp, #2444] @ 0x98c │ │ ldc2l 13, cr5, [r4, #988] @ 0x3dc │ │ - ldc2l 7, cr8, [r3, #972] @ 0x3cc │ │ + vcadd.f32 d24, d3, d16, #270 │ │ ldrbeq r0, [fp, #2396] @ 0x95c │ │ ldrbeq r0, [fp, #2368] @ 0x940 │ │ ldrbeq r0, [fp, #1976] @ 0x7b8 │ │ - ldc2l 11, cr14, [r2, #604] @ 0x25c @ │ │ - ldc2l 7, cr8, [r3, #620] @ 0x26c │ │ + ldc2l 11, cr14, [r2, #784] @ 0x310 @ │ │ + ldc2l 7, cr8, [r3, #800] @ 0x320 │ │ ldc2l 14, cr7, [r5, #600] @ 0x258 │ │ ldrbeq r0, [fp, #2276] @ 0x8e4 │ │ ldr r0, [pc, #3928] @ 24f7300 │ │ movw r3, #2090 @ 0x82a │ │ ldr r2, [pc, #3924] @ 24f7304 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1490541,23 +1490541,23 @@ │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f64a4 │ │ str r7, [sl, r1, lsl #2] │ │ b 24f64f8 │ │ ldc2l 2, cr7, [r4, #112] @ 0x70 │ │ - ldc2l 7, cr8, [r3, #44] @ 0x2c │ │ + ldc2l 7, cr8, [r3, #224] @ 0xe0 │ │ ldrbeq r0, [fp, #2164] @ 0x874 │ │ ldc2l 12, cr5, [r4, #876] @ 0x36c │ │ - ldc2l 6, cr8, [r3, #860] @ 0x35c │ │ + ldc2l 7, cr8, [r3, #16] │ │ ldrbeq r0, [fp, #2112] @ 0x840 │ │ ldrbeq r0, [fp, #2084] @ 0x824 │ │ - ldc2l 10, cr14, [r2, #540] @ 0x21c @ │ │ - ldc2l 6, cr8, [r3, #556] @ 0x22c │ │ - ldc2l 11, cr9, [r2, #964] @ 0x3c4 @ │ │ + ldc2l 10, cr14, [r2, #720] @ 0x2d0 @ │ │ + ldc2l 6, cr8, [r3, #736] @ 0x2e0 │ │ + ldc2l 12, cr9, [r2, #120] @ 0x78 │ │ ldr r0, [pc, #3932] @ 24f7408 │ │ mov r3, #2096 @ 0x830 │ │ ldr r2, [pc, #3928] @ 24f740c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r7, [sl, r0, lsl #2] │ │ @@ -1490605,23 +1490605,23 @@ │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f65a8 │ │ str r7, [sl, r1, lsl #2] │ │ b 24f65fc │ │ ldrbeq r0, [fp, #2004] @ 0x7d4 │ │ ldc2l 1, cr7, [r4, #160] @ 0xa0 │ │ - ldc2l 6, cr8, [r3, #92] @ 0x5c │ │ + ldc2l 6, cr8, [r3, #272] @ 0x110 │ │ ldrbeq r0, [fp, #1920] @ 0x780 │ │ ldc2l 11, cr5, [r4, #940] @ 0x3ac @ │ │ - ldc2l 5, cr8, [r3, #924] @ 0x39c │ │ + ldc2l 6, cr8, [r3, #80] @ 0x50 │ │ ldrbeq r0, [fp, #1872] @ 0x750 │ │ ldrbeq r0, [fp, #1844] @ 0x734 │ │ ldrbeq r0, [fp, #1452] @ 0x5ac │ │ - ldc2l 9, cr14, [r2, #262] @ 0x106 @ │ │ - ldc2l 5, cr8, [r3, #540] @ 0x21c │ │ + ldc2l 9, cr14, [r2, #352] @ 0x160 @ │ │ + ldc2l 5, cr8, [r3, #720] @ 0x2d0 │ │ ldc2l 13, cr1, [r2, #892] @ 0x37c │ │ ldr r0, [pc, #3928] @ 24f7508 │ │ movw r3, #2102 @ 0x836 │ │ ldr r2, [pc, #3924] @ 24f750c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1490671,22 +1490671,22 @@ │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f66a8 │ │ str r7, [sl, r1, lsl #2] │ │ b 24f66fc │ │ ldrbeq r0, [fp, #1744] @ 0x6d0 │ │ ldc2l 15, cr6, [r4, #960] @ 0x3c0 │ │ - ldc2l 4, cr8, [r3, #892] @ 0x37c │ │ + ldc2l 5, cr8, [r3, #48] @ 0x30 │ │ ldrbeq r0, [fp, #1608] @ 0x648 │ │ ldc2l 10, cr5, [r4, #716] @ 0x2cc @ │ │ - ldc2l 4, cr8, [r3, #700] @ 0x2bc │ │ + ldc2l 4, cr8, [r3, #880] @ 0x370 │ │ ldrbeq r0, [fp, #1560] @ 0x618 │ │ ldrbeq r0, [fp, #1532] @ 0x5fc │ │ - ldc2l 8, cr14, [r2, #348] @ 0x15c │ │ - ldc2l 4, cr8, [r3, #364] @ 0x16c │ │ + vcadd.f32 d30, d18, d4, #270 │ │ + ldc2l 4, cr8, [r3, #544] @ 0x220 │ │ ldr r0, [pc, #3932] @ 24f760c │ │ movw r3, #2108 @ 0x83c │ │ ldr r2, [pc, #3928] @ 24f7610 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r7, [sl, r0, lsl #2] │ │ @@ -1490736,25 +1490736,25 @@ │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f67b8 │ │ str r7, [sl, r1, lsl #2] │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ b 24f6810 │ │ - ldc2l 10, cr13, [r3, #336] @ 0x150 @ │ │ + ldc2l 10, cr13, [r3, #516] @ 0x204 @ │ │ ldrbeq r0, [fp, #1444] @ 0x5a4 │ │ ldc2l 14, cr6, [r4, #944] @ 0x3b0 │ │ - ldc2l 3, cr8, [r3, #876] @ 0x36c │ │ + ldc2l 4, cr8, [r3, #32] │ │ ldrbeq r0, [fp, #1348] @ 0x544 │ │ ldc2l 9, cr5, [r4, #350] @ 0x15e @ │ │ - ldc2l 3, cr8, [r3, #684] @ 0x2ac │ │ + ldc2l 3, cr8, [r3, #864] @ 0x360 │ │ ldrbeq r0, [fp, #1300] @ 0x514 │ │ ldrbeq r0, [fp, #1272] @ 0x4f8 │ │ ldrbeq r0, [fp, #880] @ 0x370 │ │ - ldc2l 7, cr14, [r2, #284] @ 0x11c │ │ + ldc2l 7, cr14, [r2, #464] @ 0x1d0 │ │ ldr r0, [pc, #3924] @ 24f7714 │ │ movw r3, #2121 @ 0x849 │ │ ldr r2, [pc, #3920] @ 24f7718 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r7, [sl, r0, lsl #2] │ │ @@ -1490800,25 +1490800,25 @@ │ │ ldr r3, [pc, #4012] @ 24f7824 │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f68b8 │ │ str r7, [sl, r1, lsl #2] │ │ b 24f690c │ │ - ldc2l 3, cr8, [r3, #300] @ 0x12c │ │ + ldc2l 3, cr8, [r3, #480] @ 0x1e0 │ │ ldc2l 0, cr6, [r4, #80] @ 0x50 │ │ ldrbeq r0, [fp, #1172] @ 0x494 │ │ ldc2l 13, cr6, [r4, #864] @ 0x360 │ │ - ldc2l 2, cr8, [r3, #796] @ 0x31c │ │ + ldc2l 2, cr8, [r3, #976] @ 0x3d0 │ │ ldrbeq r0, [fp, #1072] @ 0x430 │ │ ldc2l 8, cr5, [r4, #620] @ 0x26c │ │ - ldc2l 2, cr8, [r3, #604] @ 0x25c │ │ + ldc2l 2, cr8, [r3, #784] @ 0x310 │ │ ldrbeq r0, [fp, #1024] @ 0x400 │ │ ldrbeq r0, [fp, #992] @ 0x3e0 │ │ - ldc2l 6, cr14, [r2, #268] @ 0x10c │ │ + ldc2l 6, cr14, [r2, #448] @ 0x1c0 │ │ ldr r0, [pc, #3944] @ 24f7828 │ │ movw r3, #2127 @ 0x84f │ │ ldr r2, [pc, #3940] @ 24f782c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r7, [sl, r0, lsl #2] │ │ @@ -1490865,22 +1490865,22 @@ │ │ ldr r3, [pc, #4032] @ 24f793c │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f69b4 │ │ str r7, [sl, r1, lsl #2] │ │ b 24f6a08 │ │ - ldc2l 2, cr8, [r3, #284] @ 0x11c │ │ + ldc2l 2, cr8, [r3, #464] @ 0x1d0 │ │ ldc2l 8, cr4, [r2, #232] @ 0xe8 │ │ ldrbeq r0, [fp, #912] @ 0x390 │ │ ldc2l 12, cr6, [r4, #752] @ 0x2f0 │ │ - ldc2l 1, cr8, [r3, #684] @ 0x2ac │ │ + ldc2l 1, cr8, [r3, #864] @ 0x360 │ │ ldrbeq r0, [fp, #788] @ 0x314 │ │ ldc2l 7, cr5, [r4, #508] @ 0x1fc │ │ - ldc2l 1, cr8, [r3, #492] @ 0x1ec │ │ + ldc2l 1, cr8, [r3, #672] @ 0x2a0 │ │ ldrbeq r0, [fp, #740] @ 0x2e4 │ │ ldr r0, [pc, #3972] @ 24f7940 │ │ movw r3, #2133 @ 0x855 │ │ ldr r2, [pc, #3968] @ 24f7944 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1490928,23 +1490928,23 @@ │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f6ab4 │ │ str r7, [sl, r1, lsl #2] │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ b 24f6b0c │ │ ldrbeq r0, [fp, #712] @ 0x2c8 │ │ - ldc2l 5, cr14, [r2, #172] @ 0xac │ │ - ldc2l 1, cr8, [r3, #188] @ 0xbc │ │ - ldc2l 15, cr7, [r3, #612] @ 0x264 │ │ + ldc2l 5, cr14, [r2, #352] @ 0x160 │ │ + ldc2l 1, cr8, [r3, #368] @ 0x170 │ │ + ldc2l 15, cr7, [r3, #792] @ 0x318 │ │ ldrbeq r0, [fp, #632] @ 0x278 │ │ ldc2l 11, cr6, [r4, #736] @ 0x2e0 @ │ │ - ldc2l 0, cr8, [r3, #668] @ 0x29c │ │ + ldc2l 0, cr8, [r3, #848] @ 0x350 │ │ ldrbeq r0, [fp, #528] @ 0x210 │ │ ldc2l 6, cr5, [r4, #476] @ 0x1dc │ │ - ldc2l 0, cr8, [r3, #460] @ 0x1cc │ │ + ldc2l 0, cr8, [r3, #640] @ 0x280 │ │ ldrbeq r0, [fp, #476] @ 0x1dc │ │ ldr r0, [pc, #3996] @ 24f7a58 │ │ movw r3, #2139 @ 0x85b │ │ ldr r2, [pc, #3992] @ 24f7a5c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1490993,23 +1490993,23 @@ │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f6bbc │ │ str r7, [sl, r1, lsl #2] │ │ b 24f6c10 │ │ ldrbeq r0, [fp, #448] @ 0x1c0 │ │ - ldc2l 4, cr14, [r2, #140] @ 0x8c │ │ - ldc2l 0, cr8, [r3, #156] @ 0x9c │ │ - ldc2l 1, cr6, [r2, #844] @ 0x34c │ │ + ldc2l 4, cr14, [r2, #320] @ 0x140 │ │ + ldc2l 0, cr8, [r3, #336] @ 0x150 │ │ + ldc2l 2, cr6, [r2] │ │ ldrbeq r0, [fp, #368] @ 0x170 │ │ ldc2l 10, cr6, [r4, #736] @ 0x2e0 @ │ │ - ldc2l 15, cr7, [r3, #668] @ 0x29c │ │ + ldc2l 15, cr7, [r3, #848] @ 0x350 │ │ ldrbeq r0, [fp, #272] @ 0x110 │ │ ldc2l 5, cr5, [r4, #492] @ 0x1ec │ │ - ldc2l 15, cr7, [r3, #476] @ 0x1dc │ │ + ldc2l 15, cr7, [r3, #656] @ 0x290 │ │ ldrbeq r0, [fp, #224] @ 0xe0 │ │ ldrbeq r0, [fp, #192] @ 0xc0 │ │ ldr r0, [pc, #3996] @ 24f7b60 │ │ movw r3, #2145 @ 0x861 │ │ ldr r2, [pc, #3992] @ 24f7b64 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1491061,23 +1491061,23 @@ │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f6ccc │ │ mov r0, #3 │ │ str r0, [sl, r1, lsl #2] │ │ b 24f6d24 │ │ - ldc2l 3, cr14, [r2, #140] @ 0x8c │ │ - ldc2l 15, cr7, [r3, #156] @ 0x9c │ │ - ldc2l 3, cr12, [r2, #796] @ 0x31c │ │ + ldc2l 3, cr14, [r2, #320] @ 0x140 │ │ + ldc2l 15, cr7, [r3, #336] @ 0x150 │ │ + ldc2l 3, cr12, [r2, #976] @ 0x3d0 │ │ ldrbeq r0, [fp, #116] @ 0x74 │ │ ldc2l 9, cr6, [r4, #352] @ 0x160 @ │ │ - ldc2l 14, cr7, [r3, #636] @ 0x27c │ │ + ldc2l 14, cr7, [r3, #816] @ 0x330 │ │ ldrbeq r0, [fp, #4] │ │ ldc2l 4, cr5, [r4, #444] @ 0x1bc │ │ - ldc2l 14, cr7, [r3, #428] @ 0x1ac │ │ + ldc2l 14, cr7, [r3, #608] @ 0x260 │ │ ldrbeq pc, [sl, #4052] @ 0xfd4 @ │ │ ldrbeq pc, [sl, #4024] @ 0xfb8 @ │ │ ldr r0, [pc, #3992] @ 24f7c6c │ │ movw r3, #2156 @ 0x86c │ │ ldr r2, [pc, #3988] @ 24f7c70 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1491127,23 +1491127,23 @@ │ │ sub r1, r3, #1 │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f6dd4 │ │ mov r0, #3 │ │ str r0, [sl, r1, lsl #2] │ │ b 24f6e2c │ │ - ldc2l 2, cr14, [r2, #108] @ 0x6c │ │ - ldc2l 14, cr7, [r3, #124] @ 0x7c │ │ + ldc2l 2, cr14, [r2, #288] @ 0x120 │ │ + ldc2l 14, cr7, [r3, #304] @ 0x130 │ │ ldc2l 5, cr7, [r5, #116] @ 0x74 │ │ ldrbeq pc, [sl, #3948] @ 0xf6c @ │ │ ldc2l 8, cr6, [r4, #624] @ 0x270 │ │ - ldc2l 13, cr7, [r3, #556] @ 0x22c │ │ + ldc2l 13, cr7, [r3, #736] @ 0x2e0 │ │ ldrbeq pc, [sl, #3824] @ 0xef0 @ │ │ ldc2l 3, cr5, [r4, #364] @ 0x16c │ │ - ldc2l 13, cr7, [r3, #348] @ 0x15c │ │ + ldc2l 13, cr7, [r3, #528] @ 0x210 │ │ ldrbeq pc, [sl, #3776] @ 0xec0 @ │ │ ldrbeq pc, [sl, #3748] @ 0xea4 @ │ │ ldr r0, [pc, #3992] @ 24f7d74 │ │ movw r3, #2162 @ 0x872 │ │ ldr r2, [pc, #3988] @ 24f7d78 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1491197,23 +1491197,23 @@ │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f6ee8 │ │ mov r0, #3 │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ str r0, [sl, r1, lsl #2] │ │ b 24f6f44 │ │ ldrbeq pc, [sl, #3356] @ 0xd1c @ │ │ - ldc2l 0, cr14, [r2, #1004] @ 0x3ec │ │ - ldc2l 12, cr7, [r3, #1020] @ 0x3fc │ │ + ldc2l 1, cr14, [r2, #160] @ 0xa0 │ │ + ldc2l 13, cr7, [r3, #176] @ 0xb0 │ │ ldc2l 9, cr5, [r4, #390] @ 0x186 @ │ │ ldrbeq pc, [sl, #3656] @ 0xe48 @ │ │ ldc2l 7, cr6, [r4, #496] @ 0x1f0 │ │ - ldc2l 12, cr7, [r3, #428] @ 0x1ac │ │ + ldc2l 12, cr7, [r3, #608] @ 0x260 │ │ ldrbeq pc, [sl, #3540] @ 0xdd4 @ │ │ ldc2l 2, cr5, [r4, #236] @ 0xec │ │ - ldc2l 12, cr7, [r3, #220] @ 0xdc │ │ + ldc2l 12, cr7, [r3, #400] @ 0x190 │ │ ldrbeq pc, [sl, #3488] @ 0xda0 @ │ │ ldr r0, [pc, #3996] @ 24f7e8c │ │ movw r3, #2172 @ 0x87c │ │ ldr r2, [pc, #3992] @ 24f7e90 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1491263,23 +1491263,23 @@ │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f6ff0 │ │ str r7, [sl, r1, lsl #2] │ │ b 24f7044 │ │ ldrbeq pc, [sl, #3460] @ 0xd84 @ │ │ - ldc2l 15, cr13, [r2, #924] @ 0x39c │ │ - ldc2l 11, cr7, [r3, #940] @ 0x3ac @ │ │ + ldc2l 0, cr14, [r2, #80] @ 0x50 │ │ + ldc2l 12, cr7, [r3, #96] @ 0x60 │ │ ldc2l 10, cr9, [r4, #280] @ 0x118 @ │ │ ldrbeq pc, [sl, #3380] @ 0xd34 @ │ │ ldc2l 6, cr6, [r4, #432] @ 0x1b0 │ │ - ldc2l 11, cr7, [r3, #364] @ 0x16c @ │ │ + ldc2l 11, cr7, [r3, #544] @ 0x220 @ │ │ ldrbeq pc, [sl, #3268] @ 0xcc4 @ │ │ ldc2l 1, cr5, [r4, #188] @ 0xbc │ │ - ldc2l 11, cr7, [r3, #172] @ 0xac @ │ │ + ldc2l 11, cr7, [r3, #352] @ 0x160 @ │ │ ldrbeq pc, [sl, #3220] @ 0xc94 @ │ │ ldr r0, [pc, #3996] @ 24f7f94 │ │ movw r3, #2178 @ 0x882 │ │ ldr r2, [pc, #3992] @ 24f7f98 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1491329,23 +1491329,23 @@ │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f70f4 │ │ mov r0, #3 │ │ str r0, [sl, r1, lsl #2] │ │ b 24f714c │ │ ldrbeq pc, [sl, #3192] @ 0xc78 @ │ │ ldrbeq pc, [sl, #2796] @ 0xaec @ │ │ - ldc2l 14, cr13, [r2, #812] @ 0x32c │ │ - ldc2l 10, cr7, [r3, #828] @ 0x33c @ │ │ - ldc2l 15, cr3, [r3, #900] @ 0x384 │ │ + ldc2l 14, cr13, [r2, #992] @ 0x3e0 │ │ + ldc2l 10, cr7, [r3, #1008] @ 0x3f0 @ │ │ + ldc2l 0, cr4, [r3, #56] @ 0x38 │ │ ldrbeq pc, [sl, #3096] @ 0xc18 @ │ │ ldc2l 5, cr6, [r4, #368] @ 0x170 │ │ - ldc2l 10, cr7, [r3, #300] @ 0x12c @ │ │ + ldc2l 10, cr7, [r3, #480] @ 0x1e0 @ │ │ ldrbeq pc, [sl, #2996] @ 0xbb4 @ │ │ ldc2l 0, cr5, [r4, #124] @ 0x7c │ │ - ldc2l 10, cr7, [r3, #108] @ 0x6c @ │ │ + ldc2l 10, cr7, [r3, #288] @ 0x120 @ │ │ ldr r0, [pc, #4000] @ 24f809c │ │ movw r3, #2184 @ 0x888 │ │ ldr r2, [pc, #3996] @ 24f80a0 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, #3 │ │ @@ -1491395,23 +1491395,23 @@ │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f7200 │ │ mov r0, #3 │ │ str r0, [sl, r1, lsl #2] │ │ b 24f7258 │ │ ldrbeq pc, [sl, #2948] @ 0xb84 @ │ │ ldrbeq pc, [sl, #2920] @ 0xb68 @ │ │ - ldc2l 13, cr13, [r2, #812] @ 0x32c │ │ - ldc2l 9, cr7, [r3, #414] @ 0x19e @ │ │ + ldc2l 13, cr13, [r2, #992] @ 0x3e0 │ │ + ldc2l 9, cr7, [r3, #504] @ 0x1f8 @ │ │ vcadd.f32 d25, d4, d29, #270 │ │ ldrbeq pc, [sl, #2844] @ 0xb1c @ │ │ ldc2l 4, cr6, [r4, #336] @ 0x150 │ │ - ldc2l 9, cr7, [r3, #134] @ 0x86 @ │ │ + ldc2l 9, cr7, [r3, #224] @ 0xe0 @ │ │ ldrbeq pc, [sl, #2732] @ 0xaac @ │ │ ldc2l 15, cr4, [r4, #92] @ 0x5c │ │ - ldc2l 9, cr7, [r3, #38] @ 0x26 @ │ │ + ldc2l 9, cr7, [r3, #128] @ 0x80 @ │ │ ldrbeq pc, [sl, #2684] @ 0xa7c @ │ │ ldr r0, [pc, #4004] @ 24f81ac │ │ movw r3, #2190 @ 0x88e │ │ ldr r2, [pc, #4000] @ 24f81b0 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1491465,23 +1491465,23 @@ │ │ bhi 24f7314 │ │ mov r0, #3 │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ str r0, [sl, r1, lsl #2] │ │ b 24f7370 │ │ ldrbeq pc, [sl, #2656] @ 0xa60 @ │ │ ldrbeq pc, [sl, #2264] @ 0x8d8 @ │ │ - ldc2l 12, cr13, [r2, #732] @ 0x2dc │ │ - ldc2l 8, cr7, [r3, #748] @ 0x2ec │ │ - ldc2l 15, cr5, [r3] │ │ + ldc2l 12, cr13, [r2, #912] @ 0x390 │ │ + vcadd.f32 , , q12, #270 │ │ + ldc2l 15, cr5, [r3, #180] @ 0xb4 │ │ ldrbeq pc, [sl, #2568] @ 0xa08 @ │ │ ldc2l 3, cr6, [r4, #256] @ 0x100 │ │ - vcadd.f32 d23, d3, d31, #270 │ │ + ldc2l 8, cr7, [r3, #368] @ 0x170 │ │ ldrbeq pc, [sl, #2452] @ 0x994 @ │ │ ldc2l 13, cr4, [r4, #1004] @ 0x3ec │ │ - ldc2l 7, cr7, [r3, #988] @ 0x3dc │ │ + vcadd.f32 d23, d3, d20, #270 │ │ ldr r0, [pc, #3988] @ 24f82b0 │ │ movw r3, #2200 @ 0x898 │ │ ldr r2, [pc, #3984] @ 24f82b4 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, #3 │ │ @@ -1491531,23 +1491531,23 @@ │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f741c │ │ str r7, [sl, r1, lsl #2] │ │ b 24f7470 │ │ ldrbeq pc, [sl, #2400] @ 0x960 @ │ │ ldrbeq pc, [sl, #2372] @ 0x944 @ │ │ - ldc2l 11, cr13, [r2, #668] @ 0x29c @ │ │ - ldc2l 7, cr7, [r3, #684] @ 0x2ac │ │ + ldc2l 11, cr13, [r2, #848] @ 0x350 @ │ │ + ldc2l 7, cr7, [r3, #864] @ 0x360 │ │ ldc2l 7, cr5, [r4, #112] @ 0x70 │ │ ldrbeq pc, [sl, #2292] @ 0x8f4 @ │ │ ldc2l 2, cr6, [r4, #240] @ 0xf0 │ │ - ldc2l 7, cr7, [r3, #172] @ 0xac │ │ + ldc2l 7, cr7, [r3, #352] @ 0x160 │ │ ldrbeq pc, [sl, #2196] @ 0x894 @ │ │ ldc2l 12, cr4, [r4, #1020] @ 0x3fc │ │ - ldc2l 6, cr7, [r3, #1004] @ 0x3ec │ │ + ldc2l 7, cr7, [r3, #160] @ 0xa0 │ │ ldr r0, [pc, #3984] @ 24f83b4 │ │ movw r3, #2206 @ 0x89e │ │ ldr r2, [pc, #3980] @ 24f83b8 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r7, [sl, r0, lsl #2] │ │ @@ -1491595,23 +1491595,23 @@ │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f751c │ │ str r7, [sl, r1, lsl #2] │ │ b 24f7570 │ │ ldrbeq pc, [sl, #2148] @ 0x864 @ │ │ ldrbeq pc, [sl, #2116] @ 0x844 @ │ │ - ldc2l 10, cr13, [r2, #668] @ 0x29c @ │ │ - ldc2l 6, cr7, [r3, #684] @ 0x2ac │ │ + ldc2l 10, cr13, [r2, #848] @ 0x350 @ │ │ + ldc2l 6, cr7, [r3, #864] @ 0x360 │ │ ldc2l 3, cr1, [r5, #468] @ 0x1d4 │ │ ldrbeq pc, [sl, #2040] @ 0x7f8 @ │ │ ldc2l 1, cr6, [r4, #224] @ 0xe0 │ │ - ldc2l 6, cr7, [r3, #156] @ 0x9c │ │ + ldc2l 6, cr7, [r3, #336] @ 0x150 │ │ ldrbeq pc, [sl, #1936] @ 0x790 @ │ │ ldc2l 11, cr4, [r4, #1004] @ 0x3ec @ │ │ - ldc2l 5, cr7, [r3, #988] @ 0x3dc │ │ + ldc2l 6, cr7, [r3, #144] @ 0x90 │ │ ldr r0, [pc, #3992] @ 24f84bc │ │ movw r3, #2212 @ 0x8a4 │ │ ldr r2, [pc, #3988] @ 24f84c0 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r7, [sl, r0, lsl #2] │ │ @@ -1491660,23 +1491660,23 @@ │ │ bhi 24f7624 │ │ mov r0, #3 │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ str r0, [sl, r1, lsl #2] │ │ b 24f7680 │ │ ldrbeq pc, [sl, #1888] @ 0x760 @ │ │ ldrbeq pc, [sl, #1860] @ 0x744 @ │ │ - ldc2l 9, cr13, [r2, #334] @ 0x14e @ │ │ - ldc2l 5, cr7, [r3, #684] @ 0x2ac │ │ - ldc2l 0, cr14, [r3, #96] @ 0x60 │ │ + ldc2l 9, cr13, [r2, #424] @ 0x1a8 @ │ │ + ldc2l 5, cr7, [r3, #864] @ 0x360 │ │ + ldc2l 0, cr14, [r3, #276] @ 0x114 │ │ ldrbeq pc, [sl, #1780] @ 0x6f4 @ │ │ ldc2l 0, cr6, [r4, #224] @ 0xe0 │ │ - ldc2l 5, cr7, [r3, #156] @ 0x9c │ │ + ldc2l 5, cr7, [r3, #336] @ 0x150 │ │ ldrbeq pc, [sl, #1680] @ 0x690 @ │ │ ldc2l 10, cr4, [r4, #1004] @ 0x3ec @ │ │ - ldc2l 4, cr7, [r3, #988] @ 0x3dc │ │ + ldc2l 5, cr7, [r3, #144] @ 0x90 │ │ ldrbeq pc, [sl, #1632] @ 0x660 @ │ │ ldr r0, [pc, #3992] @ 24f85c4 │ │ movw r3, #2218 @ 0x8aa │ │ ldr r2, [pc, #3988] @ 24f85c8 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1491726,23 +1491726,23 @@ │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f772c │ │ str r7, [sl, r1, lsl #2] │ │ b 24f7780 │ │ ldrbeq pc, [sl, #1604] @ 0x644 @ │ │ ldrbeq pc, [sl, #1212] @ 0x4bc @ │ │ - ldc2l 8, cr13, [r2, #620] @ 0x26c │ │ - ldc2l 4, cr7, [r3, #636] @ 0x27c │ │ - ldc2l 3, cr11, [r3, #616] @ 0x268 │ │ + vcadd.f32 , q9, q4, #270 │ │ + ldc2l 4, cr7, [r3, #816] @ 0x330 │ │ + ldc2l 3, cr11, [r3, #796] @ 0x31c │ │ ldrbeq pc, [sl, #1512] @ 0x5e8 @ │ │ ldc2l 15, cr5, [r4, #160] @ 0xa0 │ │ - ldc2l 4, cr7, [r3, #92] @ 0x5c │ │ + ldc2l 4, cr7, [r3, #272] @ 0x110 │ │ ldrbeq pc, [sl, #1408] @ 0x580 @ │ │ ldc2l 9, cr4, [r4, #462] @ 0x1ce @ │ │ - ldc2l 3, cr7, [r3, #908] @ 0x38c │ │ + ldc2l 4, cr7, [r3, #64] @ 0x40 │ │ ldrbeq pc, [sl, #1356] @ 0x54c @ │ │ ldr r0, [pc, #4000] @ 24f86d4 │ │ mov r3, #2224 @ 0x8b0 │ │ ldr r2, [pc, #3996] @ 24f86d8 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1491795,23 +1491795,23 @@ │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f7844 │ │ mov r0, #3 │ │ str r0, [sl, r1, lsl #2] │ │ b 24f789c │ │ ldrbeq pc, [sl, #1328] @ 0x530 @ │ │ - ldc2l 7, cr13, [r2, #588] @ 0x24c │ │ - ldc2l 3, cr7, [r3, #604] @ 0x25c │ │ + ldc2l 7, cr13, [r2, #768] @ 0x300 │ │ + ldc2l 3, cr7, [r3, #784] @ 0x310 │ │ ldc2l 15, cr12, [r4, #40] @ 0x28 │ │ ldrbeq pc, [sl, #1252] @ 0x4e4 @ │ │ ldc2l 14, cr5, [r4, #160] @ 0xa0 │ │ - ldc2l 3, cr7, [r3, #92] @ 0x5c │ │ + ldc2l 3, cr7, [r3, #272] @ 0x110 │ │ ldrbeq pc, [sl, #1152] @ 0x480 @ │ │ vcadd.f32 q10, q10, , #270 │ │ - ldc2l 2, cr7, [r3, #924] @ 0x39c │ │ + ldc2l 3, cr7, [r3, #80] @ 0x50 │ │ ldrbeq pc, [sl, #1104] @ 0x450 @ │ │ ldrbeq pc, [sl, #1072] @ 0x430 @ │ │ ldr r0, [pc, #3980] @ 24f87d8 │ │ movw r3, #2234 @ 0x8ba │ │ ldr r2, [pc, #3976] @ 24f87dc │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1491865,27 +1491865,27 @@ │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f7964 │ │ mov r0, #3 │ │ str r0, [sl, r1, lsl #2] │ │ b 24f79bc │ │ - ldc2l 6, cr13, [r2, #588] @ 0x24c │ │ - ldc2l 2, cr7, [r3, #604] @ 0x25c │ │ + ldc2l 6, cr13, [r2, #768] @ 0x300 │ │ + ldc2l 2, cr7, [r3, #784] @ 0x310 │ │ ldc2l 1, cr6, [r5, #340] @ 0x154 │ │ ldrbeq pc, [sl, #992] @ 0x3e0 @ │ │ ldc2l 13, cr5, [r4, #176] @ 0xb0 │ │ - ldc2l 2, cr7, [r3, #108] @ 0x6c │ │ + ldc2l 2, cr7, [r3, #288] @ 0x120 │ │ ldrbeq pc, [sl, #900] @ 0x384 @ │ │ ldc2l 7, cr4, [r4, #956] @ 0x3bc │ │ - ldc2l 1, cr7, [r3, #940] @ 0x3ac │ │ + ldc2l 2, cr7, [r3, #96] @ 0x60 │ │ ldrbeq pc, [sl, #852] @ 0x354 @ │ │ ldrbeq pc, [sl, #824] @ 0x338 @ │ │ - ldc2l 5, cr13, [r2, #620] @ 0x26c │ │ - ldc2l 1, cr7, [r3, #636] @ 0x27c │ │ + ldc2l 5, cr13, [r2, #800] @ 0x320 │ │ + ldc2l 1, cr7, [r3, #816] @ 0x330 │ │ ldr r0, [pc, #3956] @ 24f88e0 │ │ movw r3, #2244 @ 0x8c4 │ │ ldr r2, [pc, #3952] @ 24f88e4 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, #3 │ │ @@ -1491937,25 +1491937,25 @@ │ │ ldr r3, [pc, #4024] @ 24f89f4 │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f7a7c │ │ str r7, [sl, r1, lsl #2] │ │ b 24f7ad0 │ │ - ldc2l 2, cr0, [r4, #248] @ 0xf8 │ │ + ldc2l 2, cr0, [r4, #428] @ 0x1ac │ │ ldrbeq pc, [sl, #748] @ 0x2ec @ │ │ ldc2l 12, cr5, [r4, #176] @ 0xb0 │ │ - ldc2l 1, cr7, [r3, #108] @ 0x6c │ │ + ldc2l 1, cr7, [r3, #288] @ 0x120 │ │ ldrbeq pc, [sl, #644] @ 0x284 @ │ │ ldc2l 6, cr4, [r4, #940] @ 0x3ac │ │ - ldc2l 0, cr7, [r3, #924] @ 0x39c │ │ + ldc2l 1, cr7, [r3, #80] @ 0x50 │ │ ldrbeq pc, [sl, #592] @ 0x250 @ │ │ ldrbeq pc, [sl, #564] @ 0x234 @ │ │ - ldc2l 4, cr13, [r2, #604] @ 0x25c │ │ - ldc2l 0, cr7, [r3, #620] @ 0x26c │ │ + ldc2l 4, cr13, [r2, #784] @ 0x310 │ │ + ldc2l 0, cr7, [r3, #800] @ 0x320 │ │ ldr r0, [pc, #3956] @ 24f89f8 │ │ movw r3, #2254 @ 0x8ce │ │ ldr r2, [pc, #3952] @ 24f89fc │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r7, [sl, r0, lsl #2] │ │ @@ -1492003,26 +1492003,26 @@ │ │ ldr r3, [pc, #4036] @ 24f8b08 │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f7b88 │ │ str r7, [sl, r1, lsl #2] │ │ b 24f7bdc │ │ - ldc2l 13, cr10, [r3, #252] @ 0xfc │ │ + ldc2l 13, cr10, [r3, #432] @ 0x1b0 │ │ ldrbeq pc, [sl, #484] @ 0x1e4 @ │ │ ldc2l 11, cr5, [r4, #144] @ 0x90 @ │ │ - ldc2l 0, cr7, [r3, #76] @ 0x4c │ │ + ldc2l 0, cr7, [r3, #256] @ 0x100 │ │ ldrbeq pc, [sl, #380] @ 0x17c @ │ │ ldc2l 5, cr4, [r4, #924] @ 0x39c │ │ - ldc2l 15, cr6, [r3, #908] @ 0x38c │ │ + ldc2l 0, cr7, [r3, #64] @ 0x40 │ │ ldrbeq pc, [sl, #332] @ 0x14c @ │ │ ldrbeq pc, [sl, #304] @ 0x130 @ │ │ ldrbeq lr, [sl, #4004] @ 0xfa4 │ │ - ldc2l 3, cr13, [r2, #524] @ 0x20c │ │ - ldc2l 15, cr6, [r3, #540] @ 0x21c │ │ + ldc2l 3, cr13, [r2, #704] @ 0x2c0 │ │ + ldc2l 15, cr6, [r3, #720] @ 0x2d0 │ │ ldr r0, [pc, #3964] @ 24f8b0c │ │ movw r3, #2260 @ 0x8d4 │ │ ldr r2, [pc, #3960] @ 24f8b10 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r7, [sl, r0, lsl #2] │ │ @@ -1492073,22 +1492073,22 @@ │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f7c90 │ │ str r7, [sl, r1, lsl #2] │ │ b 24f7ce4 │ │ ldc2l 0, cr10, [r5, #608] @ 0x260 │ │ ldrbeq pc, [sl, #212] @ 0xd4 @ │ │ ldc2l 10, cr5, [r4, #80] @ 0x50 @ │ │ - ldc2l 15, cr6, [r3, #12] │ │ + ldc2l 15, cr6, [r3, #192] @ 0xc0 │ │ ldrbeq pc, [sl, #104] @ 0x68 @ │ │ ldc2l 4, cr4, [r4, #844] @ 0x34c │ │ - ldc2l 14, cr6, [r3, #828] @ 0x33c │ │ + ldc2l 14, cr6, [r3, #1008] @ 0x3f0 │ │ ldrbeq pc, [sl, #56] @ 0x38 @ │ │ ldrbeq pc, [sl, #28] @ │ │ - ldc2l 2, cr13, [r2, #508] @ 0x1fc │ │ - ldc2l 14, cr6, [r3, #524] @ 0x20c │ │ + ldc2l 2, cr13, [r2, #688] @ 0x2b0 │ │ + ldc2l 14, cr6, [r3, #704] @ 0x2c0 │ │ ldr r0, [pc, #3980] @ 24f8c24 │ │ movw r3, #2266 @ 0x8da │ │ ldr r2, [pc, #3976] @ 24f8c28 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r7, [sl, r0, lsl #2] │ │ @@ -1492139,23 +1492139,23 @@ │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f7d9c │ │ str r7, [sl, r1, lsl #2] │ │ b 24f7df0 │ │ ldc2l 15, cr9, [r5, #628] @ 0x274 │ │ ldrbeq lr, [sl, #4048] @ 0xfd0 │ │ ldc2l 9, cr5, [r4, #24] @ │ │ - ldc2l 13, cr6, [r3, #1004] @ 0x3ec │ │ + ldc2l 14, cr6, [r3, #160] @ 0xa0 │ │ ldrbeq lr, [sl, #3936] @ 0xf60 │ │ ldc2l 3, cr4, [r4, #812] @ 0x32c │ │ - ldc2l 13, cr6, [r3, #796] @ 0x31c │ │ + ldc2l 13, cr6, [r3, #976] @ 0x3d0 │ │ ldrbeq lr, [sl, #3888] @ 0xf30 │ │ ldrbeq lr, [sl, #3860] @ 0xf14 │ │ ldrbeq lr, [sl, #3468] @ 0xd8c │ │ - ldc2l 1, cr13, [r2, #428] @ 0x1ac │ │ - ldc2l 13, cr6, [r3, #444] @ 0x1bc │ │ + ldc2l 1, cr13, [r2, #608] @ 0x260 │ │ + ldc2l 13, cr6, [r3, #624] @ 0x270 │ │ ldr r0, [pc, #3756] @ 24f8c50 │ │ mov r3, #2272 @ 0x8e0 │ │ ldr r2, [pc, #3752] @ 24f8c54 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r7, [sl, r0, lsl #2] │ │ @@ -1492206,25 +1492206,25 @@ │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f7eb0 │ │ mov r0, #3 │ │ str r0, [sl, r1, lsl #2] │ │ b 24f7f08 │ │ - ldc2l 1, cr15, [r2, #4] │ │ + ldc2l 1, cr15, [r2, #184] @ 0xb8 │ │ ldrbeq lr, [sl, #3772] @ 0xebc │ │ ldc2l 7, cr5, [r4, #992] @ 0x3e0 │ │ - ldc2l 12, cr6, [r3, #924] @ 0x39c │ │ + ldc2l 13, cr6, [r3, #80] @ 0x50 │ │ ldrbeq lr, [sl, #3660] @ 0xe4c │ │ ldc2l 2, cr4, [r4, #716] @ 0x2cc │ │ - ldc2l 12, cr6, [r3, #700] @ 0x2bc │ │ + ldc2l 12, cr6, [r3, #880] @ 0x370 │ │ ldrbeq lr, [sl, #3608] @ 0xe18 │ │ ldrbeq lr, [sl, #3580] @ 0xdfc │ │ - ldc2l 0, cr13, [r2, #380] @ 0x17c │ │ - ldc2l 12, cr6, [r3, #396] @ 0x18c │ │ + ldc2l 0, cr13, [r2, #560] @ 0x230 │ │ + ldc2l 12, cr6, [r3, #576] @ 0x240 │ │ ldr r0, [pc, #3952] @ 24f8e28 │ │ movw r3, #2282 @ 0x8ea │ │ ldr r2, [pc, #3948] @ 24f8e2c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, #3 │ │ @@ -1492275,22 +1492275,22 @@ │ │ bhi 24f7fb8 │ │ mov r0, #3 │ │ str r0, [sl, r1, lsl #2] │ │ b 24f8010 │ │ ldc2l 9, cr4, [r4, #72] @ 0x48 @ │ │ ldrbeq lr, [sl, #3500] @ 0xdac │ │ ldc2l 6, cr5, [r4, #960] @ 0x3c0 │ │ - ldc2l 11, cr6, [r3, #892] @ 0x37c @ │ │ + ldc2l 12, cr6, [r3, #48] @ 0x30 │ │ ldrbeq lr, [sl, #3400] @ 0xd48 │ │ ldc2l 1, cr4, [r4, #716] @ 0x2cc │ │ - ldc2l 11, cr6, [r3, #700] @ 0x2bc @ │ │ + ldc2l 11, cr6, [r3, #880] @ 0x370 @ │ │ ldrbeq lr, [sl, #3352] @ 0xd18 │ │ ldrbeq lr, [sl, #3320] @ 0xcf8 │ │ - ldc2l 15, cr12, [r2, #364] @ 0x16c │ │ - ldc2l 11, cr6, [r3, #380] @ 0x17c @ │ │ + ldc2l 15, cr12, [r2, #544] @ 0x220 │ │ + ldc2l 11, cr6, [r3, #560] @ 0x230 @ │ │ ldr r0, [pc, #4064] @ 24f8fa0 │ │ mov r3, #2288 @ 0x8f0 │ │ ldr r2, [pc, #4060] @ 24f8fa4 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, #3 │ │ @@ -1492338,26 +1492338,26 @@ │ │ sub r1, r3, #1 │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f80c4 │ │ mov r0, #3 │ │ str r0, [sl, r1, lsl #2] │ │ b 24f811c │ │ - ldc2l 1, cr5, [r3, #692] @ 0x2b4 │ │ + ldc2l 1, cr5, [r3, #872] @ 0x368 │ │ ldrbeq lr, [sl, #3244] @ 0xcac │ │ ldc2l 5, cr5, [r4, #944] @ 0x3b0 │ │ - ldc2l 10, cr6, [r3, #876] @ 0x36c @ │ │ + ldc2l 11, cr6, [r3, #32] @ │ │ ldrbeq lr, [sl, #3136] @ 0xc40 │ │ ldc2l 0, cr4, [r4, #684] @ 0x2ac │ │ - ldc2l 10, cr6, [r3, #668] @ 0x29c @ │ │ + ldc2l 10, cr6, [r3, #848] @ 0x350 @ │ │ ldrbeq lr, [sl, #3088] @ 0xc10 │ │ ldrbeq lr, [sl, #3060] @ 0xbf4 │ │ - ldc2l 14, cr12, [r2, #348] @ 0x15c │ │ - ldc2l 10, cr6, [r3, #364] @ 0x16c @ │ │ - ldc2l 11, cr6, [r2, #480] @ 0x1e0 @ │ │ + ldc2l 14, cr12, [r2, #528] @ 0x210 │ │ + ldc2l 10, cr6, [r3, #544] @ 0x220 @ │ │ + ldc2l 11, cr6, [r2, #660] @ 0x294 @ │ │ ldr r0, [pc, #3924] @ 24f9020 │ │ movw r3, #2294 @ 0x8f6 │ │ ldr r2, [pc, #3920] @ 24f9024 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, #3 │ │ @@ -1492409,23 +1492409,23 @@ │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f81d4 │ │ str r7, [sl, r1, lsl #2] │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ b 24f822c │ │ ldrbeq lr, [sl, #2984] @ 0xba8 │ │ ldc2l 4, cr5, [r4, #896] @ 0x380 │ │ - ldc2l 9, cr6, [r3, #414] @ 0x19e @ │ │ + ldc2l 9, cr6, [r3, #504] @ 0x1f8 @ │ │ ldrbeq lr, [sl, #2868] @ 0xb34 │ │ ldc2l 15, cr3, [r4, #636] @ 0x27c │ │ - ldc2l 9, cr6, [r3, #310] @ 0x136 @ │ │ + ldc2l 9, cr6, [r3, #400] @ 0x190 @ │ │ ldrbeq lr, [sl, #2820] @ 0xb04 │ │ ldrbeq lr, [sl, #2792] @ 0xae8 │ │ ldrbeq lr, [sl, #2400] @ 0x960 │ │ - ldc2l 13, cr12, [r2, #252] @ 0xfc │ │ - ldc2l 9, cr6, [r3, #134] @ 0x86 @ │ │ + ldc2l 13, cr12, [r2, #432] @ 0x1b0 │ │ + ldc2l 9, cr6, [r3, #224] @ 0xe0 @ │ │ ldr r0, [pc, #4056] @ 24f91b4 │ │ mov r3, #2304 @ 0x900 │ │ ldr r2, [pc, #4052] @ 24f91b8 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r7, [sl, r0, lsl #2] │ │ @@ -1492474,22 +1492474,22 @@ │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f82d4 │ │ str r7, [sl, r1, lsl #2] │ │ b 24f8328 │ │ ldc2l 11, cr7, [r5, #320] @ 0x140 @ │ │ ldrbeq lr, [sl, #2704] @ 0xa90 │ │ ldc2l 3, cr5, [r4, #816] @ 0x330 │ │ - ldc2l 8, cr6, [r3, #748] @ 0x2ec │ │ + vcadd.f32 q11, , q12, #270 │ │ ldrbeq lr, [sl, #2592] @ 0xa20 │ │ ldc2l 14, cr3, [r4, #540] @ 0x21c │ │ - vcadd.f32 d22, d19, d3, #270 │ │ + ldc2l 8, cr6, [r3, #704] @ 0x2c0 │ │ ldrbeq lr, [sl, #2540] @ 0x9ec │ │ ldrbeq lr, [sl, #2512] @ 0x9d0 │ │ - ldc2l 12, cr12, [r2, #204] @ 0xcc │ │ - ldc2l 8, cr6, [r3, #220] @ 0xdc │ │ + ldc2l 12, cr12, [r2, #384] @ 0x180 │ │ + vcadd.f32 q11, , q10, #270 │ │ ldr r0, [pc, #3976] @ 24f9264 │ │ movw r3, #2310 @ 0x906 │ │ ldr r2, [pc, #3972] @ 24f9268 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r7, [sl, r0, lsl #2] │ │ @@ -1492539,22 +1492539,22 @@ │ │ bhi 24f83d8 │ │ mov r0, #3 │ │ str r0, [sl, r1, lsl #2] │ │ b 24f8430 │ │ ldc2l 15, cr5, [r5, #240] @ 0xf0 │ │ ldrbeq lr, [sl, #2432] @ 0x980 │ │ ldc2l 2, cr5, [r4, #784] @ 0x310 │ │ - ldc2l 7, cr6, [r3, #716] @ 0x2cc │ │ + ldc2l 7, cr6, [r3, #896] @ 0x380 │ │ ldrbeq lr, [sl, #2332] @ 0x91c │ │ ldc2l 13, cr3, [r4, #540] @ 0x21c │ │ - ldc2l 7, cr6, [r3, #524] @ 0x20c │ │ + ldc2l 7, cr6, [r3, #704] @ 0x2c0 │ │ ldrbeq lr, [sl, #2284] @ 0x8ec │ │ ldrbeq lr, [sl, #2252] @ 0x8cc │ │ - ldc2l 11, cr12, [r2, #188] @ 0xbc @ │ │ - ldc2l 7, cr6, [r3, #204] @ 0xcc │ │ + ldc2l 11, cr12, [r2, #368] @ 0x170 @ │ │ + ldc2l 7, cr6, [r3, #384] @ 0x180 │ │ ldr r0, [pc, #3956] @ 24f9354 │ │ movw r3, #2316 @ 0x90c │ │ ldr r2, [pc, #3952] @ 24f9358 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, #3 │ │ @@ -1492602,25 +1492602,25 @@ │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f84e0 │ │ mov r0, #3 │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ str r0, [sl, r1, lsl #2] │ │ b 24f853c │ │ - ldc2l 3, cr12, [r3, #292] @ 0x124 │ │ + ldc2l 3, cr12, [r3, #472] @ 0x1d8 │ │ ldrbeq lr, [sl, #2176] @ 0x880 │ │ ldc2l 1, cr5, [r4, #784] @ 0x310 │ │ - ldc2l 6, cr6, [r3, #716] @ 0x2cc │ │ + ldc2l 6, cr6, [r3, #896] @ 0x380 │ │ ldrbeq lr, [sl, #2076] @ 0x81c │ │ ldc2l 12, cr3, [r4, #540] @ 0x21c │ │ - ldc2l 6, cr6, [r3, #524] @ 0x20c │ │ + ldc2l 6, cr6, [r3, #704] @ 0x2c0 │ │ ldrbeq lr, [sl, #2028] @ 0x7ec │ │ ldrbeq lr, [sl, #2000] @ 0x7d0 │ │ - ldc2l 10, cr12, [r2, #204] @ 0xcc @ │ │ - ldc2l 6, cr6, [r3, #220] @ 0xdc │ │ + ldc2l 10, cr12, [r2, #384] @ 0x180 @ │ │ + ldc2l 6, cr6, [r3, #400] @ 0x190 │ │ ldr r0, [pc, #4008] @ 24f9490 │ │ movw r3, #2322 @ 0x912 │ │ ldr r2, [pc, #4004] @ 24f9494 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, #3 │ │ @@ -1492668,25 +1492668,25 @@ │ │ ldr r3, [pc, #4048] @ 24f9578 │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f85e8 │ │ str r7, [sl, r1, lsl #2] │ │ b 24f863c │ │ - ldc2l 3, cr14, [r3, #692] @ 0x2b4 │ │ + ldc2l 3, cr14, [r3, #872] @ 0x368 │ │ ldrbeq lr, [sl, #1924] @ 0x784 │ │ ldc2l 0, cr5, [r4, #752] @ 0x2f0 │ │ - ldc2l 5, cr6, [r3, #684] @ 0x2ac │ │ + ldc2l 5, cr6, [r3, #864] @ 0x360 │ │ ldrbeq lr, [sl, #1808] @ 0x710 │ │ ldc2l 11, cr3, [r4, #476] @ 0x1dc @ │ │ - ldc2l 5, cr6, [r3, #460] @ 0x1cc │ │ + ldc2l 5, cr6, [r3, #640] @ 0x280 │ │ ldrbeq lr, [sl, #1756] @ 0x6dc │ │ ldrbeq lr, [sl, #1728] @ 0x6c0 │ │ - ldc2l 9, cr12, [r2, #70] @ 0x46 @ │ │ - ldc2l 5, cr6, [r3, #156] @ 0x9c │ │ + ldc2l 9, cr12, [r2, #160] @ 0xa0 @ │ │ + ldc2l 5, cr6, [r3, #336] @ 0x150 │ │ ldr r0, [pc, #3980] @ 24f957c │ │ movw r3, #2328 @ 0x918 │ │ ldr r2, [pc, #3976] @ 24f9580 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r7, [sl, r0, lsl #2] │ │ @@ -1492739,23 +1492739,23 @@ │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f86fc │ │ str r7, [sl, r1, lsl #2] │ │ b 24f8750 │ │ ldc2l 13, cr0, [r2, #700] @ 0x2bc │ │ ldrbeq lr, [sl, #1652] @ 0x674 │ │ ldc2l 15, cr4, [r4, #720] @ 0x2d0 │ │ - ldc2l 4, cr6, [r3, #652] @ 0x28c │ │ + ldc2l 4, cr6, [r3, #832] @ 0x340 │ │ ldrbeq lr, [sl, #1548] @ 0x60c │ │ ldc2l 10, cr3, [r4, #476] @ 0x1dc @ │ │ - ldc2l 4, cr6, [r3, #460] @ 0x1cc │ │ + ldc2l 4, cr6, [r3, #640] @ 0x280 │ │ ldrbeq lr, [sl, #1500] @ 0x5dc │ │ ldrbeq lr, [sl, #1472] @ 0x5c0 │ │ ldrbeq lr, [sl, #1080] @ 0x438 │ │ - vcadd.f32 d28, d2, d15, #270 │ │ - ldc2l 4, cr6, [r3, #76] @ 0x4c │ │ + ldc2l 8, cr12, [r2, #240] @ 0xf0 │ │ + ldc2l 4, cr6, [r3, #256] @ 0x100 │ │ ldr r0, [pc, #4048] @ 24f96d4 │ │ movw r3, #2338 @ 0x922 │ │ ldr r2, [pc, #4044] @ 24f96d8 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ str r7, [sl, r0, lsl #2] │ │ @@ -1492804,18 +1492804,18 @@ │ │ bhi 24f87f8 │ │ str r7, [sl, r1, lsl #2] │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ b 24f8850 │ │ ldc2l 10, cr3, [r5, #252] @ 0xfc @ │ │ ldrbeq lr, [sl, #1376] @ 0x560 │ │ ldc2l 14, cr4, [r4, #624] @ 0x270 │ │ - ldc2l 3, cr6, [r3, #556] @ 0x22c │ │ + ldc2l 3, cr6, [r3, #736] @ 0x2e0 │ │ ldrbeq lr, [sl, #1264] @ 0x4f0 │ │ ldc2l 9, cr3, [r4, #182] @ 0xb6 @ │ │ - ldc2l 3, cr6, [r3, #348] @ 0x15c │ │ + ldc2l 3, cr6, [r3, #528] @ 0x210 │ │ ldrbeq lr, [sl, #1216] @ 0x4c0 │ │ ldrbeq lr, [sl, #1188] @ 0x4a4 │ │ ldrbeq lr, [sl, #796] @ 0x31c │ │ ldr r0, [pc, #3840] @ 24f9700 │ │ movw r3, #2344 @ 0x928 │ │ ldr r2, [pc, #3836] @ 24f9704 │ │ add r0, pc, r0 │ │ @@ -1492865,23 +1492865,23 @@ │ │ ldr r3, [pc, #4064] @ 24f989c │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f8900 │ │ str r7, [sl, r1, lsl #2] │ │ b 24f8954 │ │ - ldc2l 6, cr12, [r2, #972] @ 0x3cc │ │ - ldc2l 2, cr6, [r3, #988] @ 0x3dc │ │ - ldc2l 1, cr10, [r3, #984] @ 0x3d8 │ │ + ldc2l 7, cr12, [r2, #128] @ 0x80 │ │ + ldc2l 3, cr6, [r3, #144] @ 0x90 │ │ + ldc2l 2, cr10, [r3, #140] @ 0x8c │ │ ldrbeq lr, [sl, #1092] @ 0x444 │ │ ldc2l 13, cr4, [r4, #496] @ 0x1f0 │ │ - ldc2l 2, cr6, [r3, #428] @ 0x1ac │ │ + ldc2l 2, cr6, [r3, #608] @ 0x260 │ │ ldrbeq lr, [sl, #976] @ 0x3d0 │ │ ldc2l 8, cr3, [r4, #236] @ 0xec │ │ - ldc2l 2, cr6, [r3, #220] @ 0xdc │ │ + ldc2l 2, cr6, [r3, #400] @ 0x190 │ │ ldrbeq lr, [sl, #928] @ 0x3a0 │ │ ldrbeq lr, [sl, #900] @ 0x384 │ │ ldrbeq lr, [sl, #508] @ 0x1fc │ │ ldr r0, [pc, #4024] @ 24f98c0 │ │ movw r3, #2350 @ 0x92e │ │ ldr r2, [pc, #4020] @ 24f98c4 │ │ add r0, pc, r0 │ │ @@ -1492935,23 +1492935,23 @@ │ │ ldr r3, [pc, #3864] @ 24f98ec │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f8a14 │ │ str r7, [sl, r1, lsl #2] │ │ b 24f8a68 │ │ - ldc2l 5, cr12, [r2, #844] @ 0x34c │ │ - ldc2l 1, cr6, [r3, #860] @ 0x35c │ │ - ldc2l 5, cr10, [r2, #296] @ 0x128 │ │ + ldc2l 6, cr12, [r2] │ │ + ldc2l 2, cr6, [r3, #16] │ │ + ldc2l 5, cr10, [r2, #476] @ 0x1dc │ │ ldrbeq lr, [sl, #800] @ 0x320 │ │ ldc2l 12, cr4, [r4, #400] @ 0x190 │ │ - ldc2l 1, cr6, [r3, #332] @ 0x14c │ │ + ldc2l 1, cr6, [r3, #512] @ 0x200 │ │ ldrbeq lr, [sl, #700] @ 0x2bc │ │ ldc2l 7, cr3, [r4, #156] @ 0x9c │ │ - ldc2l 1, cr6, [r3, #140] @ 0x8c │ │ + ldc2l 1, cr6, [r3, #320] @ 0x140 │ │ ldrbeq lr, [sl, #652] @ 0x28c │ │ ldrbeq lr, [sl, #624] @ 0x270 │ │ ldr r0, [pc, #3796] @ 24f98f0 │ │ movw r3, #2359 @ 0x937 │ │ ldr r2, [pc, #3792] @ 24f98f4 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1493004,27 +1493004,27 @@ │ │ ldr r3, [pc, r3] │ │ sub r1, r3, #1 │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f8b30 │ │ mov r0, #3 │ │ str r0, [sl, r1, lsl #2] │ │ b 24f8b88 │ │ - ldc2l 4, cr12, [r2, #812] @ 0x32c │ │ - ldc2l 0, cr6, [r3, #828] @ 0x33c │ │ + ldc2l 4, cr12, [r2, #992] @ 0x3e0 │ │ + ldc2l 0, cr6, [r3, #1008] @ 0x3f0 │ │ ldc2l 9, cr0, [r2, #182] @ 0xb6 @ │ │ ldrbeq lr, [sl, #536] @ 0x218 │ │ ldc2l 11, cr4, [r4, #352] @ 0x160 @ │ │ - ldc2l 0, cr6, [r3, #284] @ 0x11c │ │ + ldc2l 0, cr6, [r3, #464] @ 0x1d0 │ │ ldrbeq lr, [sl, #432] @ 0x1b0 │ │ ldc2l 6, cr3, [r4, #108] @ 0x6c │ │ - ldc2l 0, cr6, [r3, #92] @ 0x5c │ │ + ldc2l 0, cr6, [r3, #272] @ 0x110 │ │ ldrbeq lr, [sl, #384] @ 0x180 │ │ ldrbeq lr, [sl, #356] @ 0x164 │ │ - ldc2l 3, cr12, [r2, #764] @ 0x2fc │ │ - ldc2l 15, cr5, [r3, #780] @ 0x30c │ │ + ldc2l 3, cr12, [r2, #944] @ 0x3b0 │ │ + ldc2l 15, cr5, [r3, #960] @ 0x3c0 │ │ ldr r0, [pc, #3560] @ 24f9920 │ │ mov r3, #2368 @ 0x940 │ │ ldr r2, [pc, #3556] @ 24f9924 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ mov r1, #3 │ │ @@ -1493079,26 +1493079,26 @@ │ │ cmp r1, #69 @ 0x45 │ │ bhi 24f8c5c │ │ str r6, [sl, r1, lsl #2] │ │ b 24f8cb0 │ │ ldc2l 14, cr7, [r5, #832] @ 0x340 │ │ ldrbeq lr, [sl, #268] @ 0x10c │ │ ldc2l 10, cr4, [r4, #320] @ 0x140 @ │ │ - ldc2l 15, cr5, [r3, #252] @ 0xfc │ │ + ldc2l 15, cr5, [r3, #432] @ 0x1b0 │ │ ldrbeq lr, [sl, #168] @ 0xa8 │ │ ldc2l 5, cr3, [r4, #76] @ 0x4c │ │ - ldc2l 15, cr5, [r3, #60] @ 0x3c │ │ + ldc2l 15, cr5, [r3, #240] @ 0xf0 │ │ ldrbeq lr, [sl, #120] @ 0x78 │ │ ldrbeq lr, [sl, #92] @ 0x5c │ │ - ldc2l 2, cr12, [r2, #732] @ 0x2dc │ │ - ldc2l 14, cr5, [r3, #748] @ 0x2ec │ │ - ldc2l 3, cr10, [r2, #388] @ 0x184 │ │ + ldc2l 2, cr12, [r2, #912] @ 0x390 │ │ + ldc2l 14, cr5, [r3, #928] @ 0x3a0 │ │ + ldc2l 3, cr10, [r2, #568] @ 0x238 │ │ ldrbeq lr, [sl, #4] │ │ ldc2l 9, cr4, [r4, #136] @ 0x88 @ │ │ - ldc2l 14, cr5, [r3, #204] @ 0xcc │ │ + ldc2l 14, cr5, [r3, #384] @ 0x180 │ │ ldrbeq sp, [sl, #3996] @ 0xf9c │ │ ldr r0, [pc, #4044] @ 24f9c30 │ │ movw r3, #2377 @ 0x949 │ │ ldr r2, [pc, #4040] @ 24f9c34 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1493183,15 +1493183,15 @@ │ │ ldr r0, [pc, #3780] @ 24f9c78 │ │ ldr r0, [pc, r0] │ │ ldr r1, [pc, #3776] @ 24f9c7c │ │ add r1, pc, r1 │ │ str r0, [r1] │ │ b 24fabc8 │ │ ldc2l 4, cr3, [r4, #28] │ │ - ldc2l 14, cr5, [r3, #12] │ │ + ldc2l 14, cr5, [r3, #192] @ 0xc0 │ │ ldr r1, [pc, #3756] @ 24f9c80 │ │ mov r3, #31 │ │ ldr r0, [fp, #8] │ │ add r1, pc, r1 │ │ ldr r2, [fp, #48] @ 0x30 │ │ b 24fab38 │ │ ldrbeq sp, [sl, #3948] @ 0xf6c │ │ @@ -1493203,23 +1493203,23 @@ │ │ ldr r5, [pc, #3720] @ 24f9c8c │ │ add r4, pc, r4 │ │ add sl, pc, sl │ │ str r9, [sp, #28] │ │ add r5, pc, r5 │ │ b 24f8e9c │ │ ldrbeq sp, [sl, #3528] @ 0xdc8 │ │ - ldc2l 1, cr12, [r2, #636] @ 0x27c │ │ - ldc2l 13, cr5, [r3, #652] @ 0x28c │ │ + ldc2l 1, cr12, [r2, #816] @ 0x330 │ │ + ldc2l 13, cr5, [r3, #832] @ 0x340 │ │ ldc2l 15, cr6, [r5, #728] @ 0x2d8 │ │ ldrbeq sp, [sl, #3824] @ 0xef0 │ │ ldc2l 8, cr4, [r4, #192] @ 0xc0 │ │ - ldc2l 13, cr5, [r3, #124] @ 0x7c │ │ + ldc2l 13, cr5, [r3, #304] @ 0x130 │ │ ldrbeq sp, [sl, #3716] @ 0xe84 │ │ ldc2l 2, cr3, [r4, #956] @ 0x3bc │ │ - ldc2l 12, cr5, [r3, #940] @ 0x3ac │ │ + ldc2l 13, cr5, [r3, #96] @ 0x60 │ │ ldrbeq sp, [sl, #3668] @ 0xe54 │ │ ldrbeq sp, [sl, #3636] @ 0xe34 │ │ ldr r0, [pc, #4044] @ 24f9e18 │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ add r0, pc, r0 │ │ str r4, [r0, r1, lsl #2] │ │ ldr r4, [pc, #4032] @ 24f9e1c │ │ @@ -1493274,17 +1493274,17 @@ │ │ strb r3, [r2, r1] │ │ ldr r4, [pc, #4092] @ 24f9f20 │ │ ldr r4, [pc, r4] │ │ bcs 24f8fb4 │ │ ldr r7, [pc, #4084] @ 24f9f24 │ │ add r7, pc, r7 │ │ b 24f8fdc │ │ - ldc2l 0, cr12, [r2, #604] @ 0x25c │ │ - ldc2l 12, cr5, [r3, #620] @ 0x26c │ │ - ldc2l 12, cr15, [r3, #552] @ 0x228 │ │ + ldc2l 0, cr12, [r2, #784] @ 0x310 │ │ + ldc2l 12, cr5, [r3, #800] @ 0x320 │ │ + ldc2l 12, cr15, [r3, #732] @ 0x2dc │ │ ldrbeq sp, [sl, #3560] @ 0xde8 │ │ ldr r0, [pc, #4060] @ 24f9f28 │ │ add r0, pc, r0 │ │ ldrb r6, [r0] │ │ ldr r0, [pc, #4052] @ 24f9f2c │ │ cmp r6, #0 │ │ movwne r6, #32 │ │ @@ -1493302,18 +1493302,18 @@ │ │ ldr r9, [pc, #4008] @ 24f9f38 │ │ ldr r9, [pc, r9] │ │ str r9, [r5] │ │ bcs 24f927c │ │ mov r3, r9 │ │ b 24f92c8 │ │ ldc2l 7, cr4, [r4, #160] @ 0xa0 │ │ - ldc2l 12, cr5, [r3, #92] @ 0x5c │ │ + ldc2l 12, cr5, [r3, #272] @ 0x110 │ │ ldrbeq sp, [sl, #3452] @ 0xd7c │ │ ldc2l 1, cr3, [r4, #924] @ 0x39c │ │ - ldc2l 11, cr5, [r3, #908] @ 0x38c @ │ │ + ldc2l 12, cr5, [r3, #64] @ 0x40 │ │ ldr r0, [pc, #3968] @ 24f9f3c │ │ movw r3, #2436 @ 0x984 │ │ ldr r7, [pc, #3964] @ 24f9f40 │ │ add r0, pc, r0 │ │ add r7, pc, r7 │ │ mov r2, r7 │ │ bl 270da30 │ │ @@ -1493329,23 +1493329,23 @@ │ │ ldr r4, [pc, #4088] @ 24f9ff4 │ │ ldr r4, [pc, r4] │ │ bcs 24f9040 │ │ mov r3, r4 │ │ b 24f9060 │ │ ldrbeq sp, [sl, #3404] @ 0xd4c │ │ ldrbeq sp, [sl, #3376] @ 0xd30 │ │ - ldc2l 15, cr11, [r2, #588] @ 0x24c │ │ - ldc2l 11, cr5, [r3, #604] @ 0x25c @ │ │ - ldc2l 12, cr5, [r3, #208] @ 0xd0 │ │ + ldc2l 15, cr11, [r2, #768] @ 0x300 │ │ + ldc2l 11, cr5, [r3, #784] @ 0x310 @ │ │ + ldc2l 12, cr5, [r3, #388] @ 0x184 │ │ ldrbeq sp, [sl, #3300] @ 0xce4 │ │ ldc2l 6, cr4, [r4, #112] @ 0x70 │ │ - ldc2l 11, cr5, [r3, #44] @ 0x2c @ │ │ + ldc2l 11, cr5, [r3, #224] @ 0xe0 @ │ │ ldrbeq sp, [sl, #3184] @ 0xc70 │ │ ldc2l 0, cr3, [r4, #876] @ 0x36c │ │ - ldc2l 10, cr5, [r3, #860] @ 0x35c @ │ │ + ldc2l 11, cr5, [r3, #16] @ │ │ ldrbeq sp, [sl, #3136] @ 0xc40 │ │ ldrbeq sp, [sl, #3108] @ 0xc24 │ │ ldrbeq sp, [sl, #2716] @ 0xa9c │ │ ldr r0, [pc, #4016] @ 24f9ff8 │ │ mov r2, r7 │ │ movw r3, #2437 @ 0x985 │ │ add r0, pc, r0 │ │ @@ -1493409,17 +1493409,17 @@ │ │ ldr r4, [pc, r4] │ │ bcc 24f8e5c │ │ ldr r0, [pc, #3964] @ 24fa0c0 │ │ mov r2, r7 │ │ movw r3, #2450 @ 0x992 │ │ add r0, pc, r0 │ │ b 24f9800 │ │ - ldc2l 14, cr11, [r2, #492] @ 0x1ec │ │ - ldc2l 10, cr5, [r3, #508] @ 0x1fc @ │ │ - ldc2l 3, cr5, [r2, #852] @ 0x354 │ │ + ldc2l 14, cr11, [r2, #672] @ 0x2a0 │ │ + ldc2l 10, cr5, [r3, #688] @ 0x2b0 @ │ │ + ldc2l 4, cr5, [r2, #8] │ │ ldrbeq sp, [sl, #3020] @ 0xbcc │ │ cmp r0, #9 │ │ bne 24f91d0 │ │ ldr r1, [pc, #3924] @ 24fa0c4 │ │ ldr r1, [pc, r1] │ │ ldr r2, [pc, #3920] @ 24fa0c8 │ │ add r0, r1, #1 │ │ @@ -1493435,18 +1493435,18 @@ │ │ ldr r6, [pc, r6] │ │ bcs 24f937c │ │ ldr r5, [pc, #4092] @ 24fa1a8 │ │ mov r4, r6 │ │ add r5, pc, r5 │ │ b 24f93ac │ │ ldc2l 5, cr4, [r4, #48] @ 0x30 │ │ - ldc2l 9, cr5, [r3, #502] @ 0x1f6 @ │ │ + ldc2l 10, cr5, [r3, #160] @ 0xa0 @ │ │ ldrbeq sp, [sl, #2916] @ 0xb64 │ │ ldc2l 15, cr2, [r4, #812] @ 0x32c │ │ - ldc2l 9, cr5, [r3, #398] @ 0x18e @ │ │ + ldc2l 9, cr5, [r3, #488] @ 0x1e8 @ │ │ ldrbeq sp, [sl, #2864] @ 0xb30 │ │ ldrbeq sp, [sl, #2836] @ 0xb14 │ │ sub r0, r0, #127 @ 0x7f │ │ cmn r0, #96 @ 0x60 │ │ bls 24fb060 │ │ ldr r0, [pc, #4040] @ 24fa1ac │ │ mov r2, #1 │ │ @@ -1493474,23 +1493474,23 @@ │ │ ldr r0, [pc, #3964] @ 24fa1bc │ │ add r0, pc, r0 │ │ ldr sl, [r0, r1, lsl #2] │ │ ldr r0, [pc, #3956] @ 24fa1c0 │ │ add r0, pc, r0 │ │ str sl, [r0] │ │ b 24f94f0 │ │ - ldc2l 13, cr11, [r2, #476] @ 0x1dc │ │ - ldc2l 9, cr5, [r3, #246] @ 0xf6 @ │ │ + ldc2l 13, cr11, [r2, #656] @ 0x290 │ │ + ldc2l 9, cr5, [r3, #336] @ 0x150 @ │ │ ldc2l 14, cr0, [r4, #632] @ 0x278 │ │ ldrbeq sp, [sl, #2760] @ 0xac8 │ │ ldc2l 4, cr4, [r4, #48] @ 0x30 │ │ - ldc2l 8, cr5, [r3, #1004] @ 0x3ec │ │ + ldc2l 9, cr5, [r3, #80] @ 0x50 @ │ │ ldrbeq sp, [sl, #2660] @ 0xa64 │ │ ldc2l 14, cr2, [r4, #828] @ 0x33c │ │ - vcadd.f32 , , , #270 │ │ + ldc2l 8, cr5, [r3, #992] @ 0x3e0 │ │ ldrbeq sp, [sl, #2612] @ 0xa34 │ │ ldr r0, [pc, #4092] @ 24fa280 │ │ mov r1, r2 │ │ ldr r2, [pc, #4088] @ 24fa284 │ │ movw r3, #2465 @ 0x9a1 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1493534,27 +1493534,27 @@ │ │ cmp r3, r6 │ │ mov r3, r4 │ │ blt 24f9304 │ │ b 24f96a4 │ │ mov r2, r3 │ │ b 24f96a4 │ │ ldrbeq sp, [sl, #2580] @ 0xa14 │ │ - ldc2l 12, cr11, [r2, #476] @ 0x1dc │ │ - ldc2l 8, cr5, [r3, #492] @ 0x1ec │ │ + ldc2l 12, cr11, [r2, #656] @ 0x290 │ │ + vcadd.f32 d21, d19, d24, #270 │ │ ldc2l 5, cr15, [r4, #288] @ 0x120 │ │ ldrbeq sp, [sl, #2504] @ 0x9c8 │ │ ldc2l 3, cr4, [r4, #32] │ │ - ldc2l 7, cr5, [r3, #988] @ 0x3dc │ │ + vcadd.f32 d21, d3, d20, #270 │ │ ldrbeq sp, [sl, #2396] @ 0x95c │ │ ldc2l 13, cr2, [r4, #796] @ 0x31c │ │ - ldc2l 7, cr5, [r3, #780] @ 0x30c │ │ + ldc2l 7, cr5, [r3, #960] @ 0x3c0 │ │ ldrbeq sp, [sl, #2348] @ 0x92c │ │ ldrbeq sp, [sl, #2320] @ 0x910 │ │ - ldc2l 11, cr11, [r2, #460] @ 0x1cc @ │ │ - ldc2l 7, cr5, [r3, #476] @ 0x1dc │ │ + ldc2l 11, cr11, [r2, #640] @ 0x280 @ │ │ + ldc2l 7, cr5, [r3, #656] @ 0x290 │ │ ldc2l 13, cr1, [r2, #436] @ 0x1b4 │ │ ldr r0, [pc, #3976] @ 24fa30c │ │ movw r3, #2507 @ 0x9cb │ │ ldr r5, [pc, #3972] @ 24fa310 │ │ add r0, pc, r0 │ │ add r5, pc, r5 │ │ mov r2, r5 │ │ @@ -1493618,22 +1493618,22 @@ │ │ add r0, pc, r0 │ │ str r6, [r0, r1, lsl #2] │ │ ldr r4, [pc, #3920] @ 24fa3d8 │ │ add r4, pc, r4 │ │ b 24f9888 │ │ ldrbeq sp, [sl, #2244] @ 0x8c4 │ │ ldc2l 2, cr4, [r4] │ │ - ldc2l 6, cr5, [r3, #956] @ 0x3bc │ │ + ldc2l 7, cr5, [r3, #112] @ 0x70 │ │ ldrbeq sp, [sl, #2132] @ 0x854 │ │ ldc2l 12, cr2, [r4, #748] @ 0x2ec │ │ - ldc2l 6, cr5, [r3, #732] @ 0x2dc │ │ + ldc2l 6, cr5, [r3, #912] @ 0x390 │ │ ldrbeq sp, [sl, #2080] @ 0x820 │ │ ldrbeq sp, [sl, #2052] @ 0x804 │ │ - ldc2l 10, cr11, [r2, #412] @ 0x19c @ │ │ - ldc2l 6, cr5, [r3, #428] @ 0x1ac │ │ + ldc2l 10, cr11, [r2, #592] @ 0x250 @ │ │ + ldc2l 6, cr5, [r3, #608] @ 0x260 │ │ ldr r0, [pc, #4084] @ 24fa4b0 │ │ movw r3, #2566 @ 0xa06 │ │ ldr r2, [pc, #4080] @ 24fa4b4 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #4068] @ 24fa4b8 │ │ @@ -1493677,23 +1493677,23 @@ │ │ ldr r5, [fp, #36] @ 0x24 │ │ add r6, pc, r6 │ │ add r7, pc, r7 │ │ b 24f95dc │ │ ldc2l 12, cr11, [r1, #444] @ 0x1bc │ │ ldrbeq sp, [sl, #1972] @ 0x7b4 │ │ ldc2l 0, cr4, [r4, #992] @ 0x3e0 │ │ - ldc2l 5, cr5, [r3, #924] @ 0x39c │ │ + ldc2l 6, cr5, [r3, #80] @ 0x50 │ │ ldrbeq sp, [sl, #1872] @ 0x750 │ │ ldc2l 11, cr2, [r4, #748] @ 0x2ec @ │ │ - ldc2l 5, cr5, [r3, #732] @ 0x2dc │ │ + ldc2l 5, cr5, [r3, #912] @ 0x390 │ │ ldrbeq sp, [sl, #1824] @ 0x720 │ │ ldrbeq sp, [sl, #1796] @ 0x704 │ │ ldrbeq sp, [sl, #1400] @ 0x578 │ │ - ldc2l 9, cr11, [r2, #174] @ 0xae @ │ │ - ldc2l 5, cr5, [r3, #364] @ 0x16c │ │ + ldc2l 9, cr11, [r2, #264] @ 0x108 @ │ │ + ldc2l 5, cr5, [r3, #544] @ 0x220 │ │ ldr r0, [pc, #4032] @ 24fa56c │ │ mov r1, r9 │ │ ldr r7, [pc, #4092] @ 24fa5b0 │ │ movw r3, #2570 @ 0xa0a │ │ add r0, pc, r0 │ │ add r7, pc, r7 │ │ mov r2, r7 │ │ @@ -1493746,15 +1493746,15 @@ │ │ ldrb r0, [r0] │ │ ldr r1, [pc, #4076] @ 24fa670 │ │ cmp r0, #0 │ │ add r1, pc, r1 │ │ str sl, [r1] │ │ bne 24f94f4 │ │ b 24f9f14 │ │ - ldc2l 11, cr3, [r3, #696] @ 0x2b8 @ │ │ + ldc2l 11, cr3, [r3, #876] @ 0x36c @ │ │ ldrbeq sp, [sl, #1700] @ 0x6a4 │ │ mov r2, r3 │ │ ldr r9, [sp, #28] │ │ sub r4, r2, #1 │ │ str r4, [r5] │ │ ldr r0, [pc, #4056] @ 24fa68c │ │ cmp r1, #64 @ 0x40 │ │ @@ -1493763,26 +1493763,26 @@ │ │ str r2, [r0] │ │ ldr r7, [pc, #4040] @ 24fa690 │ │ add r7, pc, r7 │ │ bcs 24f9708 │ │ mov r0, r4 │ │ b 24f9728 │ │ ldc2l 15, cr3, [r4, #912] @ 0x390 │ │ - ldc2l 4, cr5, [r3, #844] @ 0x34c │ │ + ldc2l 5, cr5, [r3] │ │ ldrbeq sp, [sl, #1596] @ 0x63c │ │ ldc2l 10, cr2, [r4, #668] @ 0x29c @ │ │ - ldc2l 4, cr5, [r3, #652] @ 0x28c │ │ + ldc2l 4, cr5, [r3, #832] @ 0x340 │ │ ldrbeq sp, [sl, #1548] @ 0x60c │ │ ldrbeq sp, [sl, #1520] @ 0x5f0 │ │ - ldc2l 8, cr11, [r2, #332] @ 0x14c │ │ - ldc2l 4, cr5, [r3, #348] @ 0x15c │ │ - ldc2l 8, cr11, [r2, #228] @ 0xe4 │ │ + vcadd.f32 d27, d18, d0, #270 │ │ + ldc2l 4, cr5, [r3, #528] @ 0x210 │ │ + vcadd.f32 , q1, q11, #270 │ │ ldrbeq sp, [sl, #1444] @ 0x5a4 │ │ ldc2l 14, cr3, [r4, #928] @ 0x3a0 │ │ - ldc2l 3, cr5, [r3, #860] @ 0x35c │ │ + ldc2l 4, cr5, [r3, #16] │ │ ldr r0, [pc, #3972] @ 24fa694 │ │ mov r2, r7 │ │ movw r3, #2479 @ 0x9af │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #3952] @ 24fa698 │ │ @@ -1493842,19 +1493842,19 @@ │ │ movw r3, #2491 @ 0x9bb │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ b 24f8e5c │ │ ldrbeq sp, [sl, #1344] @ 0x540 │ │ ldc2l 9, cr2, [r4, #334] @ 0x14e @ │ │ - ldc2l 3, cr5, [r3, #652] @ 0x28c │ │ + ldc2l 3, cr5, [r3, #832] @ 0x340 │ │ ldrbeq sp, [sl, #1292] @ 0x50c │ │ ldrbeq sp, [sl, #1264] @ 0x4f0 │ │ - ldc2l 7, cr11, [r2, #332] @ 0x14c │ │ - ldc2l 3, cr5, [r3, #348] @ 0x15c │ │ + ldc2l 7, cr11, [r2, #512] @ 0x200 │ │ + ldc2l 3, cr5, [r3, #528] @ 0x210 │ │ ldr r0, [pc, #3956] @ 24fa7a4 │ │ mov r2, r5 │ │ movw r3, #2521 @ 0x9d9 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ ldr r1, [pc, #3940] @ 24fa7a8 │ │ add r1, pc, r1 │ │ @@ -1493875,59 +1493875,59 @@ │ │ add r0, pc, r0 │ │ bl 270da30 │ │ mov r1, r0 │ │ ldr r0, [pc, #3884] @ 24fa7bc │ │ add r0, pc, r0 │ │ str r6, [r0, r1, lsl #2] │ │ b 24f8e70 │ │ - ldc2l 9, cr15, [r3, #470] @ 0x1d6 @ │ │ + ldc2l 10, cr15, [r3, #96] @ 0x60 @ │ │ ldrbeq sp, [sl, #1184] @ 0x4a0 │ │ ldr r0, [pc, #3864] @ 24fa7c0 │ │ mov r9, r8 │ │ str r6, [fp, #-32] @ 0xffffffe0 │ │ add r0, pc, r0 │ │ ldrb r0, [r0] │ │ cmp r0, #1 │ │ bne 24f8e70 │ │ b 24fbaac │ │ ldc2l 13, cr3, [r4, #896] @ 0x380 │ │ - ldc2l 2, cr5, [r3, #828] @ 0x33c │ │ + ldc2l 2, cr5, [r3, #1008] @ 0x3f0 │ │ ldrbeq sp, [sl, #1080] @ 0x438 │ │ vcadd.f32 d18, d20, d19, #270 │ │ - ldc2l 2, cr5, [r3, #636] @ 0x27c │ │ + ldc2l 2, cr5, [r3, #816] @ 0x330 │ │ ldrbeq sp, [sl, #1032] @ 0x408 │ │ ldrbeq sp, [sl, #1004] @ 0x3ec │ │ ldrbeq sp, [sl, #612] @ 0x264 │ │ - ldc2l 6, cr11, [r2, #236] @ 0xec │ │ - ldc2l 2, cr5, [r3, #252] @ 0xfc │ │ - ldc2l 12, cr8, [r2, #328] @ 0x148 │ │ + ldc2l 6, cr11, [r2, #416] @ 0x1a0 │ │ + ldc2l 2, cr5, [r3, #432] @ 0x1b0 │ │ + ldc2l 12, cr8, [r2, #508] @ 0x1fc │ │ ldrbeq sp, [sl, #904] @ 0x388 │ │ ldc2l 12, cr3, [r4, #816] @ 0x330 │ │ - ldc2l 1, cr5, [r3, #748] @ 0x2ec │ │ + ldc2l 1, cr5, [r3, #928] @ 0x3a0 │ │ ldrbeq sp, [sl, #804] @ 0x324 │ │ ldc2l 7, cr2, [r4, #572] @ 0x23c │ │ - ldc2l 1, cr5, [r3, #556] @ 0x22c │ │ + ldc2l 1, cr5, [r3, #736] @ 0x2e0 │ │ ldrbeq sp, [sl, #756] @ 0x2f4 │ │ ldrbeq sp, [sl, #728] @ 0x2d8 │ │ ldrbeq sp, [sl, #336] @ 0x150 │ │ - ldc2l 5, cr11, [r2, #156] @ 0x9c │ │ - ldc2l 1, cr5, [r3, #172] @ 0xac │ │ + ldc2l 5, cr11, [r2, #336] @ 0x150 │ │ + ldc2l 1, cr5, [r3, #352] @ 0x160 │ │ ldc2l 2, cr8, [r5, #304] @ 0x130 │ │ ldrbeq sp, [sl, #632] @ 0x278 │ │ ldc2l 11, cr3, [r4, #704] @ 0x2c0 @ │ │ - ldc2l 0, cr5, [r3, #636] @ 0x27c │ │ + ldc2l 0, cr5, [r3, #816] @ 0x330 │ │ ldrbeq sp, [sl, #516] @ 0x204 │ │ ldc2l 6, cr2, [r4, #444] @ 0x1bc │ │ - ldc2l 0, cr5, [r3, #428] @ 0x1ac │ │ + ldc2l 0, cr5, [r3, #608] @ 0x260 │ │ ldrbeq sp, [sl, #468] @ 0x1d4 │ │ ldrbeq sp, [sl, #440] @ 0x1b8 │ │ ldrbeq sp, [sl, #48] @ 0x30 │ │ - ldc2l 4, cr11, [r2, #28] │ │ - ldc2l 0, cr5, [r3, #44] @ 0x2c │ │ - ldc2l 13, cr12, [r3, #36] @ 0x24 │ │ + ldc2l 4, cr11, [r2, #208] @ 0xd0 │ │ + ldc2l 0, cr5, [r3, #224] @ 0xe0 │ │ + ldc2l 13, cr12, [r3, #216] @ 0xd8 │ │ ldrbeq sp, [sl, #340] @ 0x154 │ │ sub r1, r2, #1 │ │ cmp r1, #70 @ 0x46 │ │ bcc 24f997c │ │ ldr r0, [pc, #4036] @ 24fa928 │ │ mov r2, r7 │ │ movw r3, #2581 @ 0xa15 │ │ @@ -1494106,18 +1494106,18 @@ │ │ add r1, pc, r1 │ │ add r1, r1, r4 │ │ sub r3, r1, #1 │ │ ldr r1, [pc, #4060] @ 24fac08 │ │ add r1, pc, r1 │ │ b 24f9d64 │ │ ldc2l 10, cr3, [r4, #528] @ 0x210 @ │ │ - ldc2l 15, cr4, [r3, #460] @ 0x1cc │ │ + ldc2l 15, cr4, [r3, #640] @ 0x280 │ │ ldrbeq sp, [sl, #220] @ 0xdc │ │ ldc2l 5, cr2, [r4, #284] @ 0x11c │ │ - ldc2l 15, cr4, [r3, #268] @ 0x10c │ │ + ldc2l 15, cr4, [r3, #448] @ 0x1c0 │ │ ldrbeq sp, [sl, #172] @ 0xac │ │ ldc2l 1, cr14, [r1, #476] @ 0x1dc │ │ ldrbeq lr, [sl, #2672] @ 0xa70 │ │ ldc2l 1, cr14, [r1, #284] @ 0x11c │ │ ldrbeq lr, [sl, #2640] @ 0xa50 │ │ ldrbeq lr, [sl, #1948] @ 0x79c │ │ ldrbeq ip, [sl, #3148] @ 0xc4c │ │ @@ -1494125,15 +1494125,15 @@ │ │ ldrbeq lr, [sl, #1244] @ 0x4dc │ │ ldrbeq lr, [sl, #2672] @ 0xa70 │ │ ldrbeq ip, [sl, #3652] @ 0xe44 │ │ ldrbeq ip, [sl, #3632] @ 0xe30 │ │ ldrbeq ip, [sl, #3640] @ 0xe38 │ │ ldrbeq lr, [sl, #2600] @ 0xa28 │ │ ldrbeq ip, [sl, #3048] @ 0xbe8 │ │ - ldc2l 1, cr13, [r2, #756] @ 0x2f4 │ │ + ldc2l 1, cr13, [r2, #936] @ 0x3a8 │ │ ldrbeq ip, [sl, #3520] @ 0xdc0 │ │ ldrbeq ip, [sl, #3512] @ 0xdb8 │ │ ldrbeq lr, [sl, #1088] @ 0x440 │ │ cmp r0, #0 │ │ mov r0, r9 │ │ bgt 24f9cb4 │ │ ldr r0, [pc, #3944] @ 24fac0c │ │ @@ -1494294,22 +1494294,22 @@ │ │ str r0, [r1] │ │ ldr r4, [pc, #3864] @ 24fae2c │ │ add r4, pc, r4 │ │ str r9, [fp, #-32] @ 0xffffffe0 │ │ mov r9, r8 │ │ b 24f8e70 │ │ ldrbeq ip, [sl, #3232] @ 0xca0 │ │ - ldc2l 12, cr4, [r3, #716] @ 0x2cc │ │ + ldc2l 12, cr4, [r3, #896] @ 0x380 │ │ ldrbeq ip, [sl, #4000] @ 0xfa0 │ │ ldrbeq ip, [sl, #3168] @ 0xc60 │ │ ldrbeq lr, [sl, #2156] @ 0x86c │ │ ldrbeq lr, [sl, #2140] @ 0x85c │ │ ldrbeq ip, [sl, #3124] @ 0xc34 │ │ ldc2l 7, cr14, [r4, #304] @ 0x130 │ │ - ldc2l 12, cr4, [r3, #108] @ 0x6c │ │ + ldc2l 12, cr4, [r3, #288] @ 0x120 │ │ ldrbeq lr, [sl, #2048] @ 0x800 │ │ ldrbeq ip, [sl, #2508] @ 0x9cc │ │ sub sl, r2, #1 │ │ cmp sl, #70 @ 0x46 │ │ mov r0, sl │ │ bcc 24f9f74 │ │ ldr r0, [pc, #4064] @ 24faf44 │ │ @@ -1494455,15 +1494455,15 @@ │ │ sub r0, r0, #1 │ │ bl 270d9e0 │ │ ldr r0, [pc, #4044] @ 24fb168 │ │ mov r1, #1 │ │ add r0, pc, r0 │ │ strb r1, [r0] │ │ b 24f9d88 │ │ - ldc2l 10, cr4, [r3, #204] @ 0xcc @ │ │ + ldc2l 10, cr4, [r3, #384] @ 0x180 @ │ │ ldrbeq ip, [sl, #2544] @ 0x9f0 │ │ ldrbeq ip, [sl, #2520] @ 0x9d8 │ │ ldrbeq ip, [sl, #2508] @ 0x9cc │ │ ldrbeq ip, [sl, #3264] @ 0xcc0 │ │ ldrbeq ip, [sl, #2464] @ 0x9a0 │ │ ldrbeq ip, [sl, #2832] @ 0xb10 │ │ ldr r0, [pc, #4072] @ 24fb1b4 │ │ @@ -1494510,15 +1494510,15 @@ │ │ ldr r1, [pc, #3940] @ 24fb1d4 │ │ add r1, pc, r1 │ │ mov r2, #3 │ │ mov r3, #3 │ │ bl 270d9e0 │ │ b 24f9d88 │ │ ldc2l 4, cr14, [r4, #512] @ 0x200 │ │ - ldc2l 9, cr4, [r3, #158] @ 0x9e @ │ │ + ldc2l 9, cr4, [r3, #248] @ 0xf8 @ │ │ ldrbeq ip, [sl, #3144] @ 0xc48 │ │ ldr r0, [pc, #3908] @ 24fb1d8 │ │ mov r1, r9 │ │ mov r2, r7 │ │ movw r3, #2710 @ 0xa96 │ │ add r0, pc, r0 │ │ bl 270da30 │ │ @@ -1494545,15 +1494545,15 @@ │ │ blt 24fa3dc │ │ ldr r1, [pc, #4064] @ 24fb2e0 │ │ mov r3, #66 @ 0x42 │ │ ldr r2, [fp, #48] @ 0x30 │ │ add r1, pc, r1 │ │ b 24fab38 │ │ ldc2l 3, cr14, [r4, #528] @ 0x210 │ │ - ldc2l 8, cr4, [r3, #332] @ 0x14c │ │ + vcadd.f32 d20, d19, d0, #270 │ │ ldr r0, [pc, #4040] @ 24fb2e4 │ │ ldr r0, [pc, r0] │ │ sub r1, r0, #1 │ │ cmp r1, #64 @ 0x40 │ │ bcc 24fa344 │ │ ldr r0, [pc, #4024] @ 24fb2e8 │ │ movw r3, #927 @ 0x39f │ │ @@ -1494650,25 +1494650,25 @@ │ │ ldr r2, [pc, #3956] @ 24fb414 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ ldr r0, [r0, r1, lsl #2] │ │ str r0, [r2] │ │ b 24facb8 │ │ ldc2l 7, cr15, [r3, #808] @ 0x328 │ │ - ldc2l 7, cr4, [r3, #108] @ 0x6c │ │ + ldc2l 7, cr4, [r3, #288] @ 0x120 │ │ ldrbeq ip, [sl, #1804] @ 0x70c │ │ ldrbeq ip, [sl, #2164] @ 0x874 │ │ ldrbeq ip, [sl, #1732] @ 0x6c4 │ │ - ldc2l 4, cr15, [r2, #264] @ 0x108 │ │ - ldc2l 6, cr4, [r3, #764] @ 0x2fc │ │ + ldc2l 4, cr15, [r2, #444] @ 0x1bc │ │ + ldc2l 6, cr4, [r3, #944] @ 0x3b0 │ │ ldrbeq ip, [sl, #2104] @ 0x838 │ │ ldrbeq ip, [sl, #2072] @ 0x818 │ │ ldrbeq ip, [sl, #2464] @ 0x9a0 │ │ ldrbeq sp, [sl, #3300] @ 0xce4 │ │ - ldc2l 6, cr4, [r3, #460] @ 0x1cc │ │ + ldc2l 6, cr4, [r3, #640] @ 0x280 │ │ ldr r0, [pc, #3888] @ 24fb418 │ │ mov r1, r8 │ │ ldr r2, [pc, #3884] @ 24fb41c │ │ mov r3, #64 @ 0x40 │ │ add r0, pc, r0 │ │ str r6, [sp] │ │ add r2, pc, r2 │ │ @@ -1494713,15 +1494713,15 @@ │ │ sub r2, r2, #1 │ │ stmib sp, {r3, r8} │ │ sub r1, r1, r2 │ │ str r1, [sp, #12] │ │ add r2, r9, r2 │ │ ldr r1, [fp, #48] @ 0x30 │ │ b 24fb198 │ │ - ldc2l 6, cr4, [r3, #156] @ 0x9c │ │ + ldc2l 6, cr4, [r3, #336] @ 0x150 │ │ ldrbeq ip, [sl, #1932] @ 0x78c │ │ ldrbeq sp, [sl, #3188] @ 0xc74 │ │ ldrbeq sp, [sl, #2696] @ 0xa88 │ │ ldrbeq ip, [sl, #1484] @ 0x5cc │ │ ldr r0, [pc, #4024] @ 24fb584 │ │ add r7, sp, #36 @ 0x24 │ │ ldr r1, [pc, #4020] @ 24fb588 │ │ @@ -1494736,15 +1494736,15 @@ │ │ str r2, [sp, #16] │ │ add r2, r9, r1 │ │ stmib sp, {r3, r8} │ │ b 24fb19c │ │ ldr r1, [pc, #3972] @ 24fb58c │ │ add r1, pc, r1 │ │ b 24fabc0 │ │ - ldc2l 9, cr10, [r2, #374] @ 0x176 @ │ │ + ldc2l 9, cr10, [r2, #464] @ 0x1d0 @ │ │ eoreq r2, r6, r8, lsr r0 │ │ ldrbeq ip, [sl, #2220] @ 0x8ac │ │ ldrbeq ip, [sl, #1780] @ 0x6f4 │ │ ldr r1, [pc, #3948] @ 24fb590 │ │ mov r4, r0 │ │ ldr r5, [fp, #48] @ 0x30 │ │ mov r3, #74 @ 0x4a │ │ @@ -1494769,15 +1494769,15 @@ │ │ ldr r1, [pc, #4068] @ 24fb660 │ │ mov r3, #56 @ 0x38 │ │ ldr r0, [fp, #8] │ │ add r1, pc, r1 │ │ ldr r2, [fp, #48] @ 0x30 │ │ b 24fab38 │ │ ldrbeq ip, [sl, #1312] @ 0x520 │ │ - ldc2l 5, cr4, [r3, #108] @ 0x6c │ │ + ldc2l 5, cr4, [r3, #288] @ 0x120 │ │ ldc2l 9, cr11, [r4, #28] @ │ │ ldrbeq sp, [sl, #2856] @ 0xb28 │ │ ldrbeq ip, [sl, #904] @ 0x388 │ │ ldrbeq sp, [sl, #2708] @ 0xa94 │ │ ldrbeq ip, [sl, #1148] @ 0x47c │ │ ldrbeq lr, [sl, #128] @ 0x80 │ │ ldrbeq sp, [sl, #2772] @ 0xad4 │ │ @@ -1494979,15 +1494979,15 @@ │ │ ldr r1, [pc, #4068] @ 24fb9a8 │ │ mov r3, #63 @ 0x3f │ │ add r0, pc, r0 │ │ str r6, [sp] │ │ add r1, pc, r1 │ │ bl 270e290 │ │ b 24faad8 │ │ - ldc2l 5, cr10, [r2, #972] @ 0x3cc │ │ + ldc2l 6, cr10, [r2, #128] @ 0x80 │ │ ldrbeq ip, [sl, #1268] @ 0x4f4 │ │ ldrbeq sp, [sl, #2120] @ 0x848 │ │ ldrbeq ip, [sl, #1212] @ 0x4bc │ │ ldrbeq ip, [sl, #1200] @ 0x4b0 │ │ ldrbeq sp, [sl, #2048] @ 0x800 │ │ ldrbeq ip, [sl, #1156] @ 0x484 │ │ ldrbeq sp, [sl, #1996] @ 0x7cc │ │ @@ -1495109,15 +1495109,15 @@ │ │ bl 270d9e0 │ │ mov r0, #1 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldr r0, [pc, #4032] @ 24fbb9c │ │ add r0, pc, r0 │ │ b 24fabec │ │ - ldc2l 4, cr8, [r2, #692] @ 0x2b4 │ │ + ldc2l 4, cr8, [r2, #872] @ 0x368 │ │ ldr r0, [pc, #4020] @ 24fbba0 │ │ add r0, pc, r0 │ │ ldr r2, [pc, #4092] @ 24fbbf0 │ │ mov r1, #1 │ │ add r2, pc, r2 │ │ b 24fb180 │ │ ldrbeq sp, [sl, #1480] @ 0x5c8 │ │ @@ -1495461,15 +1495461,15 @@ │ │ b 24f4e68 │ │ ldrbeq fp, [sl, #2676] @ 0xa74 │ │ ldr r0, [pc, #4008] @ 24fc0fc │ │ add r0, pc, r0 │ │ b 24fb174 │ │ ldrbeq fp, [sl, #2676] @ 0xa74 │ │ ldc2l 8, cr7, [r4, #124] @ 0x7c │ │ - ldc2l 13, cr5, [r3, #60] @ 0x3c │ │ + ldc2l 13, cr5, [r3, #240] @ 0xf0 │ │ ldrbeq sp, [sl, #860] @ 0x35c │ │ ldrbeq fp, [sl, #2584] @ 0xa18 │ │ ldr r0, [pc, #3980] @ 24fc100 │ │ add r0, pc, r0 │ │ ldr r2, [pc, #3976] @ 24fc104 │ │ mov r1, #5 │ │ add r2, pc, r2 │ │ @@ -1495557,22 +1495557,22 @@ │ │ cmp r1, #63 @ 0x3f │ │ bhi 24fb304 │ │ ldr r0, [pc, #3900] @ 24fc210 │ │ add r0, pc, r0 │ │ ldr r0, [r0, r1, lsl #2] │ │ str r0, [r4] │ │ b 24fb360 │ │ - ldc2l 9, cr3, [r3, #430] @ 0x1ae @ │ │ + ldc2l 10, cr3, [r3, #16] @ │ │ ldrbeq fp, [sl, #2216] @ 0x8a8 │ │ ldc2l 3, cr13, [r4, #864] @ 0x360 │ │ - vcadd.f32 d19, d19, d23, #270 │ │ + ldc2l 8, cr3, [r3, #848] @ 0x350 │ │ ldrbeq fp, [sl, #1632] @ 0x660 │ │ ldrbeq ip, [sl, #3824] @ 0xef0 │ │ ldc2l 12, cr10, [r4, #680] @ 0x2a8 │ │ - vcadd.f32 , , , #270 │ │ + ldc2l 8, cr3, [r3, #576] @ 0x240 │ │ ldrbeq fp, [sl, #1832] @ 0x728 │ │ ldr r0, [pc, #3848] @ 24fc214 │ │ movw r3, #3284 @ 0xcd4 │ │ ldr r2, [pc, #3844] @ 24fc218 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1495627,17 +1495627,17 @@ │ │ mov r2, r5 │ │ ldr r1, [pc, #4076] @ 24fc3d4 │ │ add r0, pc, r0 │ │ str r6, [sp] │ │ add r1, pc, r1 │ │ b 24fb7c0 │ │ ldrbeq ip, [sl, #3660] @ 0xe4c │ │ - ldc2l 11, cr9, [r2, #824] @ 0x338 @ │ │ + ldc2l 11, cr9, [r2, #1004] @ 0x3ec @ │ │ ldrbeq sp, [sl, #840] @ 0x348 │ │ - ldc2l 9, cr9, [r3, #38] @ 0x26 @ │ │ + ldc2l 9, cr9, [r3, #128] @ 0x80 @ │ │ eoreq r1, r6, r0, lsr r2 │ │ ldrbeq ip, [sl, #3560] @ 0xde8 │ │ ldrbeq ip, [sl, #3532] @ 0xdcc │ │ ldrbeq fp, [sl, #1296] @ 0x510 │ │ ldrbeq fp, [sl, #2236] @ 0x8bc │ │ ldrbeq sp, [sl, #648] @ 0x288 │ │ ldrbeq fp, [sl, #1192] @ 0x4a8 │ │ @@ -1495729,16 +1495729,16 @@ │ │ str r0, [r4] │ │ b 24fb6e4 │ │ ldrbeq ip, [sl, #3272] @ 0xcc8 │ │ ldrbeq fp, [sl, #1588] @ 0x634 │ │ ldrbeq ip, [sl, #3532] @ 0xdcc │ │ ldrbeq fp, [sl, #1516] @ 0x5ec │ │ ldc2l 2, cr1, [r4, #736] @ 0x2e0 │ │ - ldc2l 3, cr11, [r3, #304] @ 0x130 │ │ - ldc2l 8, cr8, [r2, #724] @ 0x2d4 │ │ + ldc2l 3, cr11, [r3, #484] @ 0x1e4 │ │ + vcadd.f32 q12, q9, q9, #270 │ │ cmp r7, #2 │ │ blt 24fb9b8 │ │ ldr r1, [sp, #28] │ │ ldr r2, [fp, #48] @ 0x30 │ │ ldr r3, [fp, #36] @ 0x24 │ │ bl 270d9e0 │ │ ldr r0, [pc, #4088] @ 24fc5b0 │ │ @@ -1495781,19 +1495781,19 @@ │ │ ldr r0, [pc, #3968] @ 24fc5cc │ │ ldr r2, [pc, #3968] @ 24fc5d0 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ ldr r0, [r0, r1, lsl #2] │ │ str r0, [r2] │ │ b 24fbd00 │ │ - ldc2l 6, cr3, [r3, #136] @ 0x88 │ │ + ldc2l 6, cr3, [r3, #316] @ 0x13c │ │ ldrbeq ip, [sl, #2936] @ 0xb78 │ │ - ldc2l 4, cr7, [r3, #104] @ 0x68 │ │ + ldc2l 4, cr7, [r3, #284] @ 0x11c │ │ ldrbeq sp, [sl, #116] @ 0x74 │ │ - ldc2l 14, cr7, [r2, #456] @ 0x1c8 │ │ + ldc2l 14, cr7, [r2, #636] @ 0x27c │ │ eoreq r0, r6, ip, asr pc │ │ ldrbeq ip, [sl, #2836] @ 0xb14 │ │ ldrbeq ip, [sl, #2808] @ 0xaf8 │ │ ldrbeq fp, [sl, #572] @ 0x23c │ │ ldrbeq fp, [sl, #1512] @ 0x5e8 │ │ ldr r0, [pc, #3908] @ 24fc5d4 │ │ movw r3, #3311 @ 0xcef │ │ @@ -1495872,31 +1495872,31 @@ │ │ ldr r1, [pc, #4072] @ 24fc7a0 │ │ add r0, pc, r0 │ │ str r7, [sp] │ │ add r1, pc, r1 │ │ mov r3, #1 │ │ bl 270e2a0 │ │ b 24fab3c │ │ - ldc2l 12, cr6, [r2, #512] @ 0x200 │ │ + ldc2l 12, cr6, [r2, #692] @ 0x2b4 │ │ ldrbeq fp, [sl, #1380] @ 0x564 │ │ - ldc2l 15, cr0, [r3, #432] @ 0x1b0 │ │ + ldc2l 15, cr0, [r3, #612] @ 0x264 │ │ ldrbeq fp, [sl, #1324] @ 0x52c │ │ - ldc2l 9, cr13, [r2, #118] @ 0x76 @ │ │ + ldc2l 9, cr13, [r2, #208] @ 0xd0 @ │ │ eoreq r0, r6, r8, lsl lr │ │ ldrbeq fp, [sl, #860] @ 0x35c │ │ ldc2l 5, cr2, [r5, #688] @ 0x2b0 │ │ - ldc2l 3, cr3, [r3, #364] @ 0x16c │ │ - ldc2l 6, cr8, [r2, #388] @ 0x184 │ │ + ldc2l 3, cr3, [r3, #544] @ 0x220 │ │ + ldc2l 6, cr8, [r2, #568] @ 0x238 │ │ ldrbeq fp, [sl, #2708] @ 0xa94 │ │ ldrbeq fp, [sl, #1160] @ 0x488 │ │ ldrbeq fp, [sl, #1148] @ 0x47c │ │ ldc2l 5, cr12, [r1, #204] @ 0xcc │ │ - ldc2l 11, cr6, [r2, #32] @ │ │ + ldc2l 11, cr6, [r2, #212] @ 0xd4 @ │ │ ldrbeq fp, [sl, #1004] @ 0x3ec │ │ - ldc2l 13, cr0, [r3, #976] @ 0x3d0 │ │ + ldc2l 14, cr0, [r3, #132] @ 0x84 │ │ ldrbeq fp, [sl, #948] @ 0x3b4 │ │ ldr r0, [pc, #4080] @ 24fc80c │ │ movw r3, #3332 @ 0xd04 │ │ ldr r2, [pc, #4076] @ 24fc810 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ @@ -1495990,19 +1495990,19 @@ │ │ bcc 24fc648 │ │ ldr r0, [pc, #3792] @ 24fc864 │ │ movw r3, #3340 @ 0xd0c │ │ ldr r2, [pc, #3788] @ 24fc868 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ b 24fc640 │ │ - ldc2l 8, cr1, [r3, #604] @ 0x25c │ │ + vcadd.f32 , , q2, #270 │ │ eoreq r0, r6, r0, lsr #25 │ │ - ldc2l 10, cr6, [r2, #144] @ 0x90 @ │ │ + ldc2l 10, cr6, [r2, #324] @ 0x144 @ │ │ ldrbeq fp, [sl, #776] @ 0x308 │ │ - ldc2l 13, cr0, [r3, #64] @ 0x40 │ │ + ldc2l 13, cr0, [r3, #244] @ 0xf4 │ │ cmp r3, #2 │ │ blt 24fbe4c │ │ ldr r1, [sp, #28] │ │ ldr r2, [fp, #48] @ 0x30 │ │ ldr r3, [fp, #36] @ 0x24 │ │ bl 270d9e0 │ │ ldr r0, [pc, #3852] @ 24fc8e4 │ │ @@ -1496048,17 +1496048,17 @@ │ │ add r2, pc, r2 │ │ ldr r0, [r0, r1, lsl #2] │ │ str r0, [r2] │ │ b 24fbfc0 │ │ ldrbeq fp, [sl, #720] @ 0x2d0 │ │ ldc2l 3, cr3, [r4, #680] @ 0x2a8 │ │ strhteq r0, [r6], -ip │ │ - ldc2l 11, cr6, [r2, #280] @ 0x118 @ │ │ + ldc2l 11, cr6, [r2, #460] @ 0x1cc @ │ │ ldrbeq ip, [sl, #3340] @ 0xd0c │ │ - ldc2l 4, cr8, [r2, #116] @ 0x74 │ │ + ldc2l 4, cr8, [r2, #296] @ 0x128 │ │ ldrbeq fp, [sl, #628] @ 0x274 │ │ ldrbeq fp, [sl, #620] @ 0x26c │ │ ldc2l 3, cr12, [r1, #124] @ 0x7c │ │ ldrbeq ip, [sl, #3164] @ 0xc5c │ │ ldc2l 0, cr4, [r5, #648] @ 0x288 │ │ ldr r7, [fp, #8] │ │ mov r1, r9 │ │ @@ -1496115,15 +1496115,15 @@ │ │ str r5, [sp, #4] │ │ sub r2, r0, #1 │ │ str r5, [sp, #8] │ │ str r6, [sp, #12] │ │ mov r0, r7 │ │ b 24fa664 │ │ ldrbeq ip, [sl, #3096] @ 0xc18 │ │ - ldc2l 3, cr7, [r2, #708] @ 0x2c4 │ │ + ldc2l 3, cr7, [r2, #888] @ 0x378 │ │ ldrbeq ip, [sl, #2628] @ 0xa44 │ │ ldrbeq ip, [sl, #1972] @ 0x7b4 │ │ ldr r0, [pc, #3128] @ 24fc7e4 │ │ add r0, pc, r0 │ │ str sl, [fp, #-32] @ 0xffffffe0 │ │ mov r3, #320 @ 0x140 │ │ ldr r1, [pc, #3100] @ 24fc7d8 │ │ @@ -1496158,36 +1496158,36 @@ │ │ str r1, [sp, #12] │ │ add r2, r8, r2 │ │ ldr r1, [fp, #48] @ 0x30 │ │ str r1, [sp, #16] │ │ mov r1, r8 │ │ b 24fb1a0 │ │ ldc2l 10, cr12, [r4, #688] @ 0x2b0 @ │ │ - ldc2l 15, cr2, [r3, #492] @ 0x1ec │ │ + ldc2l 15, cr2, [r3, #672] @ 0x2a0 │ │ ldrbeq sl, [sl, #3384] @ 0xd38 │ │ ldrbeq fp, [sl, #228] @ 0xe4 │ │ ldrbeq ip, [sl, #1472] @ 0x5c0 │ │ ldc2l 3, cr10, [r4, #488] @ 0x1e8 │ │ - ldc2l 15, cr2, [r3, #204] @ 0xcc │ │ + ldc2l 15, cr2, [r3, #384] @ 0x180 │ │ ldrbeq sl, [sl, #3564] @ 0xdec │ │ ldrbeq fp, [sl, #144] @ 0x90 │ │ - ldc2l 7, cr6, [r2, #544] @ 0x220 │ │ - ldc2l 10, cr0, [r3, #496] @ 0x1f0 @ │ │ + ldc2l 7, cr6, [r2, #724] @ 0x2d4 │ │ + ldc2l 10, cr0, [r3, #676] @ 0x2a4 @ │ │ ldrbeq fp, [sl, #60] @ 0x3c │ │ - ldc2l 1, cr8, [r2, #772] @ 0x304 │ │ + ldc2l 1, cr8, [r2, #952] @ 0x3b8 │ │ ldrbeq ip, [sl, #1304] @ 0x518 │ │ ldrbeq fp, [sl, #24] │ │ ldrbeq fp, [sl, #12] │ │ ldrbeq ip, [sl, #1228] @ 0x4cc │ │ ldc2l 9, cr12, [r4, #232] @ 0xe8 @ │ │ - ldc2l 14, cr2, [r3, #268] @ 0x10c │ │ + ldc2l 14, cr2, [r3, #448] @ 0x1c0 │ │ ldrbeq sl, [sl, #3076] @ 0xc04 │ │ ldrbeq ip, [sl, #1164] @ 0x48c │ │ ldc2l 2, cr10, [r4, #296] @ 0x128 │ │ - ldc2l 14, cr2, [r3, #12] │ │ + ldc2l 14, cr2, [r3, #192] @ 0xc0 │ │ ldr r0, [pc, #3044] @ 24fc888 │ │ mov r3, #3360 @ 0xd20 │ │ ldr r2, [pc, #3040] @ 24fc88c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #3028] @ 24fc890 │ │ @@ -1496281,17 +1496281,17 @@ │ │ ldr r0, [pc, #2752] @ 24fc8dc │ │ movw r3, #3368 @ 0xd28 │ │ ldr r2, [pc, #2748] @ 24fc8e0 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ b 24fc640 │ │ ldrbeq ip, [sl, #1036] @ 0x40c │ │ - ldc2l 1, cr9, [r2, #960] @ 0x3c0 │ │ + ldc2l 2, cr9, [r2, #116] @ 0x74 │ │ ldrbeq ip, [sl, #2312] @ 0x908 │ │ - ldc2l 7, cr7, [r2, #24] │ │ + ldc2l 7, cr7, [r2, #204] @ 0xcc │ │ strdeq r0, [r6], -r0 @ │ │ ldc2l 10, cr10, [r4, #696] @ 0x2b8 @ │ │ ldrbeq ip, [sl, #896] @ 0x380 │ │ ldrbeq ip, [sl, #824] @ 0x338 │ │ cmp lr, #2 │ │ blt 24fc108 │ │ ldr r1, [sp, #28] │ │ @@ -1496342,26 +1496342,26 @@ │ │ ldr r0, [r0, r1, lsl #2] │ │ str r0, [r2] │ │ b 24fc2a4 │ │ ldrbeq ip, [sl, #816] @ 0x330 │ │ ldrbeq sl, [sl, #2684] @ 0xa7c │ │ ldrbeq sl, [sl, #3624] @ 0xe28 │ │ ldrbeq ip, [sl, #716] @ 0x2cc │ │ - ldc2l 2, cr13, [r2, #184] @ 0xb8 │ │ + ldc2l 2, cr13, [r2, #364] @ 0x16c │ │ ldrbeq ip, [sl, #1992] @ 0x7c8 │ │ ldc2l 9, cr10, [r4, #308] @ 0x134 @ │ │ strhteq r0, [r6], -r0 │ │ ldrbeq ip, [sl, #616] @ 0x268 │ │ ldrbeq ip, [sl, #588] @ 0x24c │ │ ldrbeq sl, [sl, #2448] @ 0x990 │ │ ldrbeq sl, [sl, #3388] @ 0xd3c │ │ - ldc2l 7, cr0, [r3, #32] │ │ + ldc2l 7, cr0, [r3, #212] @ 0xd4 │ │ ldrbeq sl, [sl, #2884] @ 0xb44 │ │ ldrbeq sl, [sl, #2856] @ 0xb28 │ │ - ldc2l 3, cr6, [r2, #656] @ 0x290 │ │ + ldc2l 3, cr6, [r2, #836] @ 0x344 │ │ ldrbeq sl, [sl, #2820] @ 0xb04 │ │ ldc2l 0, cr10, [r4, #180] @ 0xb4 │ │ ldr r0, [pc, #2468] @ 24fc908 │ │ movw r3, #3388 @ 0xd3c │ │ ldr r2, [pc, #2464] @ 24fc90c │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ @@ -1496457,20 +1496457,20 @@ │ │ ldr r0, [pc, #2176] @ 24fc95c │ │ movw r3, #3396 @ 0xd44 │ │ ldr r2, [pc, #2172] @ 24fc960 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ b 24fc640 │ │ eoreq r0, r6, r4, ror r5 │ │ - ldc2l 13, cr7, [r2, #964] @ 0x3c4 │ │ + ldc2l 14, cr7, [r2, #120] @ 0x78 │ │ ldrbeq sl, [sl, #2724] @ 0xaa4 │ │ ldrbeq sl, [sl, #2720] @ 0xaa0 │ │ ldrbeq ip, [sl, #1228] @ 0x4cc │ │ ldrbeq ip, [sl, #556] @ 0x22c │ │ - ldc2l 14, cr10, [r2, #228] @ 0xe4 │ │ + ldc2l 14, cr10, [r2, #408] @ 0x198 │ │ cmp ip, #2 │ │ blt 24fc3d8 │ │ ldr r1, [sp, #28] │ │ ldr r2, [fp, #48] @ 0x30 │ │ ldr r3, [fp, #36] @ 0x24 │ │ bl 270d9e0 │ │ ldr r0, [pc, #2236] @ 24fc9e4 │ │ @@ -1496517,35 +1496517,35 @@ │ │ ldr r0, [r0, r1, lsl #2] │ │ str r0, [r2] │ │ b 24fc4c8 │ │ ldr r0, [pc, #1532] @ 24fc7d4 │ │ add r0, pc, r0 │ │ b 24fbbac │ │ ldc2l 5, cr12, [r4, #112] @ 0x70 │ │ - ldc2l 9, cr2, [r3, #470] @ 0x1d6 @ │ │ + ldc2l 10, cr2, [r3, #96] @ 0x60 @ │ │ ldrbeq sl, [sl, #1960] @ 0x7a8 │ │ ldrbeq sl, [sl, #2900] @ 0xb54 │ │ ldrbeq ip, [sl, #48] @ 0x30 │ │ ldc2l 13, cr9, [r4, #952] @ 0x3b8 │ │ - ldc2l 9, cr2, [r3, #334] @ 0x14e @ │ │ + ldc2l 9, cr2, [r3, #424] @ 0x1a8 @ │ │ ldrbeq sl, [sl, #2148] @ 0x864 │ │ ldrbeq sl, [sl, #2824] @ 0xb08 │ │ - ldc2l 2, cr6, [r2] │ │ - ldc2l 4, cr0, [r3, #992] @ 0x3e0 │ │ + ldc2l 2, cr6, [r2, #180] @ 0xb4 │ │ + ldc2l 5, cr0, [r3, #148] @ 0x94 │ │ ldrbeq sl, [sl, #2744] @ 0xab8 │ │ ldrbeq fp, [sl, #3980] @ 0xf8c │ │ ldrbeq sl, [sl, #1756] @ 0x6dc │ │ ldc2l 3, cr12, [r4, #1008] @ 0x3f0 │ │ - vcadd.f32 q9, , , #270 │ │ + ldc2l 8, cr2, [r3, #992] @ 0x3e0 │ │ ldrbeq sl, [sl, #1676] @ 0x68c │ │ ldrbeq fp, [sl, #3860] @ 0xf14 │ │ ldc2l 12, cr9, [r4, #840] @ 0x348 │ │ - vcadd.f32 d18, d19, d11, #270 │ │ - ldc2l 0, cr6, [r2, #1008] @ 0x3f0 │ │ - ldc2l 3, cr0, [r3, #960] @ 0x3c0 │ │ + ldc2l 8, cr2, [r3, #736] @ 0x2e0 │ │ + ldc2l 1, cr6, [r2, #164] @ 0xa4 │ │ + ldc2l 4, cr0, [r3, #116] @ 0x74 │ │ ldrbeq sl, [sl, #2480] @ 0x9b0 │ │ ldrbeq fp, [sl, #3732] @ 0xe94 │ │ mlaeq r6, ip, r2, r0 │ │ ldr r0, [pc, #1856] @ 24fc988 │ │ movw r3, #3416 @ 0xd58 │ │ ldr r2, [pc, #1852] @ 24fc98c │ │ add r0, pc, r0 │ │ @@ -1496661,26 +1496661,26 @@ │ │ mov r3, #122 @ 0x7a │ │ ldr r5, [fp, #48] @ 0x30 │ │ ldr r1, [pc, #1628] @ 24fca70 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ b 24fa630 │ │ ldc2l 2, cr12, [r4, #816] @ 0x330 │ │ - ldc2l 7, cr2, [r3, #620] @ 0x26c │ │ + ldc2l 7, cr2, [r3, #800] @ 0x320 │ │ ldrbeq sl, [sl, #1368] @ 0x558 │ │ ldrbeq sl, [sl, #2308] @ 0x904 │ │ ldrbeq fp, [sl, #3552] @ 0xde0 │ │ ldc2l 11, cr9, [r4, #616] @ 0x268 @ │ │ - ldc2l 7, cr2, [r3, #332] @ 0x14c │ │ + ldc2l 7, cr2, [r3, #512] @ 0x200 │ │ ldrbeq sl, [sl, #1548] @ 0x60c │ │ ldrbeq sl, [sl, #2224] @ 0x8b0 │ │ - ldc2l 15, cr5, [r2, #672] @ 0x2a0 │ │ - ldc2l 2, cr0, [r3, #640] @ 0x280 │ │ + ldc2l 15, cr5, [r2, #852] @ 0x354 │ │ + ldc2l 2, cr0, [r3, #820] @ 0x334 │ │ ldrbeq sl, [sl, #2144] @ 0x860 │ │ - ldc2l 9, cr7, [r2, #458] @ 0x1ca @ │ │ + ldc2l 10, cr7, [r2, #72] @ 0x48 @ │ │ ldrbeq fp, [sl, #3388] @ 0xd3c │ │ ldrbeq sl, [sl, #2108] @ 0x83c │ │ ldrbeq sl, [sl, #2096] @ 0x830 │ │ ldrbeq fp, [sl, #3312] @ 0xcf0 │ │ ldrbeq sl, [sl, #1088] @ 0x440 │ │ ldr r0, [pc, #1436] @ 24fca08 │ │ movw r3, #3444 @ 0xd74 │ │ @@ -1496764,26 +1496764,26 @@ │ │ add r0, pc, r0 │ │ ldr r0, [r0, r1, lsl #2] │ │ str r0, [r4] │ │ b 24fc648 │ │ ldrbeq fp, [sl, #3228] @ 0xc9c │ │ ldc2l 3, cr6, [r4, #832] @ 0x340 │ │ ldrbeq ip, [sl, #408] @ 0x198 │ │ - ldc2l 0, cr9, [r3, #528] @ 0x210 │ │ + ldc2l 0, cr9, [r3, #708] @ 0x2c4 │ │ eoreq r0, r6, r0, lsl #1 │ │ ldrbeq fp, [sl, #3128] @ 0xc38 │ │ ldrbeq fp, [sl, #3100] @ 0xc1c │ │ ldrbeq sl, [sl, #864] @ 0x360 │ │ ldrbeq sl, [sl, #1804] @ 0x70c │ │ ldc2l 0, cr12, [r4, #480] @ 0x1e0 │ │ - ldc2l 5, cr2, [r3, #284] @ 0x11c │ │ + ldc2l 5, cr2, [r3, #464] @ 0x1d0 │ │ ldrbeq sl, [sl, #776] @ 0x308 │ │ ldrbeq fp, [sl, #2960] @ 0xb90 │ │ ldc2l 9, cr9, [r4, #156] @ 0x9c @ │ │ - ldc2l 5, cr2, [r3, #28] │ │ + ldc2l 5, cr2, [r3, #208] @ 0xd0 │ │ ldr r0, [pc, #1112] @ 24fca4c │ │ movw r3, #3451 @ 0xd7b │ │ ldr r2, [pc, #1108] @ 24fca50 │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ bl 270da30 │ │ ldr r1, [pc, #1096] @ 24fca54 │ │ @@ -1496840,32 +1496840,32 @@ │ │ stm sp, {r3, r5} │ │ sub r2, r2, r0 │ │ str r2, [sp, #8] │ │ ldr r2, [sp, #28] │ │ str r3, [sp, #12] │ │ add r2, r2, r0 │ │ b 24fb780 │ │ - ldc2l 13, cr5, [r2, #464] @ 0x1d0 │ │ + ldc2l 13, cr5, [r2, #644] @ 0x284 │ │ ldr r4, [fp, #8] │ │ mov r3, #82 @ 0x52 │ │ ldr r5, [fp, #48] @ 0x30 │ │ ldr r1, [pc, #864] @ 24fca64 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ b 24fa630 │ │ - ldc2l 0, cr0, [r3, #400] @ 0x190 │ │ + ldc2l 0, cr0, [r3, #580] @ 0x244 │ │ ldr r4, [fp, #8] │ │ mov r3, #91 @ 0x5b │ │ ldr r5, [fp, #48] @ 0x30 │ │ ldr r1, [pc, #836] @ 24fca68 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ b 24fa630 │ │ ldrbeq sl, [sl, #1572] @ 0x624 │ │ - ldc2l 7, cr7, [r2, #692] @ 0x2b4 │ │ + ldc2l 7, cr7, [r2, #872] @ 0x368 │ │ ldrbeq fp, [sl, #2820] @ 0xb04 │ │ ldrbeq sl, [sl, #1536] @ 0x600 │ │ ldrbeq sl, [sl, #1528] @ 0x5f8 │ │ sub r1, r1, #1 │ │ ldr r0, [pc, #148] @ 24fc7e0 │ │ sub r2, ip, r1 │ │ mov r3, #320 @ 0x140 │ │ @@ -1496903,177 +1496903,177 @@ │ │ ldrbeq fp, [sl, #1600] @ 0x640 │ │ ldrbeq r9, [sl, #4012] @ 0xfac │ │ ldrbeq fp, [sl, #456] @ 0x1c8 │ │ ldrbeq fp, [sl, #1680] @ 0x690 │ │ ldrbeq r9, [sl, #4092] @ 0xffc │ │ ldrbeq sl, [sl, #3136] @ 0xc40 │ │ ldrbeq fp, [sl, #2676] @ 0xa74 │ │ - ldc2l 9, cr5, [r2, #312] @ 0x138 @ │ │ + ldc2l 9, cr5, [r2, #402] @ 0x192 @ │ │ ldrbeq sl, [sl, #224] @ 0xe0 │ │ - ldc2l 12, cr15, [r2, #544] @ 0x220 │ │ + ldc2l 12, cr15, [r2, #724] @ 0x2d4 │ │ ldrbeq sl, [sl, #172] @ 0xac │ │ ldc2l 0, cr0, [r4, #296] @ 0x128 │ │ ldrbeq fp, [sl, #3236] @ 0xca4 │ │ ldc2l 2, cr2, [r4, #1008] @ 0x3f0 │ │ - ldc2l 3, cr7, [r2, #596] @ 0x254 │ │ + ldc2l 3, cr7, [r2, #776] @ 0x308 │ │ ldrbeq sl, [sl, #80] @ 0x50 │ │ ldc2l 14, cr11, [r4, #944] @ 0x3b0 │ │ - ldc2l 3, cr2, [r3, #748] @ 0x2ec │ │ + ldc2l 3, cr2, [r3, #928] @ 0x3a0 │ │ ldrbeq sl, [sl, #376] @ 0x178 │ │ ldrbeq sl, [sl, #1316] @ 0x524 │ │ ldrbeq fp, [sl, #2560] @ 0xa00 │ │ ldc2l 7, cr9, [r4, #744] @ 0x2e8 │ │ - ldc2l 3, cr2, [r3, #460] @ 0x1cc │ │ + ldc2l 3, cr2, [r3, #640] @ 0x280 │ │ ldrbeq sl, [sl, #556] @ 0x22c │ │ ldrbeq sl, [sl, #1232] @ 0x4d0 │ │ - ldc2l 11, cr5, [r2, #800] @ 0x320 @ │ │ - ldc2l 14, cr15, [r2, #768] @ 0x300 │ │ + ldc2l 11, cr5, [r2, #980] @ 0x3d4 @ │ │ + ldc2l 14, cr15, [r2, #948] @ 0x3b4 │ │ ldrbeq sl, [sl, #1152] @ 0x480 │ │ - ldc2l 6, cr7, [r2, #20] │ │ + ldc2l 6, cr7, [r2, #200] @ 0xc8 │ │ ldrbeq fp, [sl, #2396] @ 0x95c │ │ ldrbeq sl, [sl, #1116] @ 0x45c │ │ ldrbeq sl, [sl, #1104] @ 0x450 │ │ ldrbeq fp, [sl, #2316] @ 0x90c │ │ ldrbeq r9, [sl, #1036] @ 0x40c │ │ ldc2l 13, cr11, [r4, #720] @ 0x2d0 │ │ - ldc2l 2, cr2, [r3, #524] @ 0x20c │ │ + ldc2l 2, cr2, [r3, #704] @ 0x2c0 │ │ ldrbeq sl, [sl, #68] @ 0x44 │ │ ldrbeq fp, [sl, #2252] @ 0x8cc │ │ ldc2l 6, cr9, [r4, #552] @ 0x228 │ │ - ldc2l 2, cr2, [r3, #268] @ 0x10c │ │ - ldc2l 14, cr4, [r2, #64] @ 0x40 │ │ - ldc2l 1, cr15, [r2] │ │ + ldc2l 2, cr2, [r3, #448] @ 0x1c0 │ │ + ldc2l 14, cr4, [r2, #244] @ 0xf4 │ │ + ldc2l 1, cr15, [r2, #180] @ 0xb4 │ │ ldrbeq r9, [sl, #1728] @ 0x6c0 │ │ - vcadd.f32 q11, q1, , #270 │ │ + ldc2l 8, cr6, [r2, #472] @ 0x1d8 │ │ ldrbeq sl, [sl, #2976] @ 0xba0 │ │ ldrbeq r9, [sl, #1692] @ 0x69c │ │ ldrbeq r9, [sl, #1684] @ 0x694 │ │ ldc2l 10, cr11, [r4, #400] @ 0x190 @ │ │ - ldc2l 15, cr1, [r3, #204] @ 0xcc │ │ + ldc2l 15, cr1, [r3, #384] @ 0x180 │ │ ldrbeq r9, [sl, #3312] @ 0xcf0 │ │ ldrbeq sl, [sl, #156] @ 0x9c │ │ ldrbeq fp, [sl, #1400] @ 0x578 │ │ ldc2l 3, cr9, [r4, #200] @ 0xc8 │ │ - ldc2l 14, cr1, [r3, #940] @ 0x3ac │ │ + ldc2l 15, cr1, [r3, #96] @ 0x60 │ │ ldrbeq r9, [sl, #3492] @ 0xda4 │ │ ldrbeq sl, [sl, #72] @ 0x48 │ │ - ldc2l 7, cr5, [r2, #256] @ 0x100 │ │ - ldc2l 10, cr15, [r2, #224] @ 0xe0 @ │ │ + ldc2l 7, cr5, [r2, #436] @ 0x1b4 │ │ + ldc2l 10, cr15, [r2, #404] @ 0x194 @ │ │ ldrbeq r9, [sl, #4088] @ 0xff8 │ │ - ldc2l 1, cr7, [r2, #500] @ 0x1f4 │ │ + ldc2l 1, cr7, [r2, #680] @ 0x2a8 │ │ ldrbeq fp, [sl, #1236] @ 0x4d4 │ │ ldrbeq r9, [sl, #4052] @ 0xfd4 │ │ ldrbeq r9, [sl, #4040] @ 0xfc8 │ │ ldrbeq fp, [sl, #1156] @ 0x484 │ │ ldc2l 9, cr11, [r4, #88] @ 0x58 @ │ │ - ldc2l 13, cr1, [r3, #1004] @ 0x3ec │ │ + ldc2l 14, cr1, [r3, #160] @ 0xa0 │ │ ldrbeq r9, [sl, #3004] @ 0xbbc │ │ ldrbeq fp, [sl, #1092] @ 0x444 │ │ ldc2l 2, cr9, [r4, #8] │ │ - ldc2l 13, cr1, [r3, #748] @ 0x2ec │ │ + ldc2l 13, cr1, [r3, #928] @ 0x3a0 │ │ ldrbeq fp, [sl, #2172] @ 0x87c │ │ - ldc2l 8, cr0, [r3, #732] @ 0x2dc │ │ + vcadd.f32 q8, , q10, #270 │ │ ldrbeq fp, [sl, #3448] @ 0xd78 │ │ ldc2l 7, cr14, [r1, #980] @ 0x3d4 │ │ eoreq pc, r5, r0, ror #24 │ │ ldrbeq fp, [sl, #2072] @ 0x818 │ │ ldrbeq fp, [sl, #2044] @ 0x7fc │ │ ldrbeq r9, [sl, #3904] @ 0xf40 │ │ ldrbeq sl, [sl, #748] @ 0x2ec │ │ ldc2l 7, cr11, [r4, #656] @ 0x290 │ │ - ldc2l 12, cr1, [r3, #460] @ 0x1cc │ │ + ldc2l 12, cr1, [r3, #640] @ 0x280 │ │ ldrbeq r9, [sl, #2608] @ 0xa30 │ │ ldrbeq r9, [sl, #3548] @ 0xddc │ │ ldrbeq fp, [sl, #696] @ 0x2b8 │ │ ldc2l 0, cr9, [r4, #456] @ 0x1c8 │ │ - ldc2l 12, cr1, [r3, #172] @ 0xac │ │ + ldc2l 12, cr1, [r3, #352] @ 0x160 │ │ ldrbeq r9, [sl, #2788] @ 0xae4 │ │ ldrbeq r9, [sl, #3464] @ 0xd88 │ │ - ldc2l 4, cr5, [r2, #512] @ 0x200 │ │ - ldc2l 7, cr15, [r2, #480] @ 0x1e0 │ │ + ldc2l 4, cr5, [r2, #692] @ 0x2b4 │ │ + ldc2l 7, cr15, [r2, #660] @ 0x294 │ │ ldrbeq r9, [sl, #3384] @ 0xd38 │ │ - ldc2l 14, cr6, [r2, #756] @ 0x2f4 │ │ + ldc2l 14, cr6, [r2, #936] @ 0x3a8 │ │ ldrbeq fp, [sl, #532] @ 0x214 │ │ ldrbeq r9, [sl, #3348] @ 0xd14 │ │ ldrbeq r9, [sl, #3336] @ 0xd08 │ │ ldrbeq fp, [sl, #452] @ 0x1c4 │ │ ldc2l 6, cr11, [r4, #432] @ 0x1b0 │ │ - ldc2l 11, cr1, [r3, #236] @ 0xec @ │ │ + ldc2l 11, cr1, [r3, #416] @ 0x1a0 @ │ │ ldrbeq r9, [sl, #2300] @ 0x8fc │ │ ldrbeq fp, [sl, #388] @ 0x184 │ │ ldc2l 15, cr8, [r4, #264] @ 0x108 │ │ - ldc2l 10, cr1, [r3, #1004] @ 0x3ec @ │ │ + ldc2l 11, cr1, [r3, #160] @ 0xa0 @ │ │ ldrbeq fp, [sl, #1000] @ 0x3e8 │ │ - ldc2l 15, cr15, [r1, #212] @ 0xd4 │ │ + ldc2l 15, cr15, [r1, #392] @ 0x188 │ │ ldrbeq fp, [sl, #2276] @ 0x8e4 │ │ - ldc2l 6, cr6, [r2, #720] @ 0x2d0 │ │ + ldc2l 6, cr6, [r2, #900] @ 0x384 │ │ eoreq pc, r5, ip, asr #15 │ │ ldrbeq fp, [sl, #900] @ 0x384 │ │ ldrbeq fp, [sl, #872] @ 0x368 │ │ ldrbeq r9, [sl, #2732] @ 0xaac │ │ ldrbeq r9, [sl, #3672] @ 0xe58 │ │ ldc2l 4, cr11, [r4, #768] @ 0x300 │ │ - ldc2l 9, cr1, [r3, #286] @ 0x11e @ │ │ + ldc2l 9, cr1, [r3, #376] @ 0x178 @ │ │ ldrbeq r9, [sl, #1868] @ 0x74c │ │ ldrbeq r9, [sl, #2808] @ 0xaf8 │ │ ldrbeq sl, [sl, #4052] @ 0xfd4 │ │ ldc2l 13, cr8, [r4, #568] @ 0x238 │ │ - ldc2l 9, cr1, [r3, #142] @ 0x8e @ │ │ + ldc2l 9, cr1, [r3, #232] @ 0xe8 @ │ │ ldrbeq r9, [sl, #2048] @ 0x800 │ │ ldrbeq r9, [sl, #2724] @ 0xaa4 │ │ - ldc2l 1, cr5, [r2, #624] @ 0x270 │ │ - ldc2l 4, cr15, [r2, #592] @ 0x250 │ │ + ldc2l 1, cr5, [r2, #804] @ 0x324 │ │ + ldc2l 4, cr15, [r2, #772] @ 0x304 │ │ ldrbeq r9, [sl, #2644] @ 0xa54 │ │ - ldc2l 11, cr6, [r2, #868] @ 0x364 @ │ │ + ldc2l 12, cr6, [r2, #24] │ │ ldrbeq sl, [sl, #3888] @ 0xf30 │ │ ldrbeq r9, [sl, #2608] @ 0xa30 │ │ ldrbeq r9, [sl, #2596] @ 0xa24 │ │ ldrbeq sl, [sl, #3808] @ 0xee0 │ │ ldc2l 3, cr11, [r4, #544] @ 0x220 │ │ - ldc2l 8, cr1, [r3, #348] @ 0x15c │ │ + vcadd.f32 d17, d19, d4, #270 │ │ ldrbeq r9, [sl, #1560] @ 0x618 │ │ ldrbeq sl, [sl, #3744] @ 0xea0 │ │ ldc2l 12, cr8, [r4, #376] @ 0x178 │ │ - ldc2l 8, cr1, [r3, #92] @ 0x5c │ │ + vcadd.f32 , , q2, #270 │ │ ldrbeq fp, [sl, #300] @ 0x12c │ │ ldc2l 0, cr14, [r1, #796] @ 0x31c │ │ ldrbeq fp, [sl, #1576] @ 0x628 │ │ - ldc2l 3, cr6, [r2, #1000] @ 0x3e8 │ │ + ldc2l 4, cr6, [r2, #156] @ 0x9c │ │ eoreq pc, r5, r0, lsl r5 @ │ │ ldrbeq fp, [sl, #200] @ 0xc8 │ │ ldrbeq fp, [sl, #172] @ 0xac │ │ ldrbeq r9, [sl, #2032] @ 0x7f0 │ │ ldrbeq r9, [sl, #2972] @ 0xb9c │ │ ldc2l 2, cr11, [r4, #624] @ 0x270 │ │ - ldc2l 7, cr1, [r3, #428] @ 0x1ac │ │ + ldc2l 7, cr1, [r3, #608] @ 0x260 │ │ ldrbeq r9, [sl, #1320] @ 0x528 │ │ ldrbeq r9, [sl, #2260] @ 0x8d4 │ │ ldrbeq sl, [sl, #3504] @ 0xdb0 │ │ ldc2l 11, cr8, [r4, #424] @ 0x1a8 @ │ │ - ldc2l 7, cr1, [r3, #140] @ 0x8c │ │ + ldc2l 7, cr1, [r3, #320] @ 0x140 │ │ ldrbeq r9, [sl, #1500] @ 0x5dc │ │ ldrbeq r9, [sl, #2176] @ 0x880 │ │ - ldc2l 15, cr4, [r2, #480] @ 0x1e0 │ │ - ldc2l 2, cr15, [r2, #448] @ 0x1c0 │ │ + ldc2l 15, cr4, [r2, #660] @ 0x294 │ │ + ldc2l 2, cr15, [r2, #628] @ 0x274 │ │ ldrbeq r9, [sl, #2096] @ 0x830 │ │ - ldc2l 9, cr6, [r2, #362] @ 0x16a @ │ │ + ldc2l 9, cr6, [r2, #452] @ 0x1c4 @ │ │ ldrbeq sl, [sl, #3340] @ 0xd0c │ │ ldrbeq r9, [sl, #2060] @ 0x80c │ │ ldrbeq r9, [sl, #2048] @ 0x800 │ │ ldrbeq sl, [sl, #3260] @ 0xcbc │ │ ldc2l 1, cr11, [r4, #80] @ 0x50 │ │ - ldc2l 5, cr1, [r3, #908] @ 0x38c │ │ + ldc2l 6, cr1, [r3, #64] @ 0x40 │ │ ldrbeq r9, [sl, #932] @ 0x3a4 │ │ ldrbeq sl, [sl, #3116] @ 0xc2c │ │ ldc2l 9, cr8, [r4, #468] @ 0x1d4 @ │ │ - ldc2l 5, cr1, [r3, #652] @ 0x28c │ │ + ldc2l 5, cr1, [r3, #832] @ 0x340 │ │ ldc2l 13, cr11, [r1, #556] @ 0x22c │ │ - ldc2l 10, cr11, [r2, #1016] @ 0x3f8 @ │ │ + ldc2l 11, cr11, [r2, #172] @ 0xac @ │ │ ldc2l 8, cr9, [r1, #108] @ 0x6c │ │ - ldc2l 8, cr11, [r3, #196] @ 0xc4 │ │ + ldc2l 8, cr11, [r3, #376] @ 0x178 │ │ ldc2l 8, cr9, [r1, #364] @ 0x16c │ │ │ │ 024fca78 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ ldr r4, [pc, #48] @ 24fcab8 │ │ mov r1, #6 │ │ @@ -1497426,16 +1497426,16 @@ │ │ stm sp, {r0, r8} │ │ str r7, [sp, #8] │ │ str r8, [sp, #12] │ │ bl 270ee60 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 1, cr7, [r2, #784] @ 0x310 │ │ - ldc2l 2, cr4, [r2, #224] @ 0xe0 │ │ + ldc2l 1, cr7, [r2, #964] @ 0x3c4 │ │ + ldc2l 2, cr4, [r2, #404] @ 0x194 │ │ │ │ 024fcfb4 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #12 │ │ mov r8, r3 │ │ ldr r3, [pc, #368] @ 24fd13c │ │ @@ -1497532,15 +1497532,15 @@ │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldrbeq sl, [sl, #2064] @ 0x810 │ │ ldrbeq sl, [sl, #2016] @ 0x7e0 │ │ ldrbeq sl, [sl, #2000] @ 0x7d0 │ │ ldc2l 11, cr6, [r1, #724] @ 0x2d4 @ │ │ - ldc2l 1, cr3, [r2, #116] @ 0x74 │ │ + ldc2l 1, cr3, [r2, #296] @ 0x128 │ │ ldrbeq sl, [sl, #1956] @ 0x7a4 │ │ ldrbeq sl, [sl, #1820] @ 0x71c │ │ ldrbeq sl, [sl, #1764] @ 0x6e4 │ │ ldrbeq sl, [sl, #1744] @ 0x6d0 │ │ │ │ 024fd160 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ @@ -1497639,15 +1497639,15 @@ │ │ bl 270e070 │ │ ldr r0, [fp, #8] │ │ mov r1, #0 │ │ str r1, [r0] │ │ mov r0, #0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - ldc2l 12, cr5, [r2, #532] @ 0x214 │ │ + ldc2l 12, cr5, [r2, #712] @ 0x2c8 │ │ │ │ 024fd2ec : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #948 @ 0x3b4 │ │ str r3, [sp, #16] │ │ mov r4, r1 │ │ @@ -1497663,134 +1497663,134 @@ │ │ add r8, pc, r8 │ │ str r4, [sp, #4] │ │ bne 2500208 │ │ b 24fd528 │ │ ldrbeq sl, [sl, #2784] @ 0xae0 │ │ ldrbeq sl, [sl, #2765] @ 0xacd │ │ ldrbeq ip, [sl, #1957] @ 0x7a5 │ │ - ldc2l 9, cr2, [r3, #160] @ 0xa0 @ │ │ - ldc2l 11, cr2, [r2, #948] @ 0x3b4 @ │ │ + ldc2l 9, cr2, [r3, #250] @ 0xfa @ │ │ + ldc2l 12, cr2, [r2, #104] @ 0x68 │ │ ldc2l 2, cr6, [r4, #8] │ │ - ldc2l 11, cr6, [r2, #60] @ 0x3c @ │ │ - ldc2l 13, cr14, [r2, #376] @ 0x178 │ │ + ldc2l 11, cr6, [r2, #240] @ 0xf0 @ │ │ + ldc2l 13, cr14, [r2, #556] @ 0x22c │ │ ldc2l 8, cr1, [r5, #364] @ 0x16c │ │ - ldc2l 10, cr4, [r2, #844] @ 0x34c @ │ │ - ldc2l 10, cr4, [r2, #716] @ 0x2cc @ │ │ + ldc2l 11, cr4, [r2] @ │ │ + ldc2l 10, cr4, [r2, #896] @ 0x380 @ │ │ ldc2l 6, cr12, [r3, #540] @ 0x21c │ │ ldc2l 1, cr6, [r4, #208] @ 0xd0 │ │ - ldc2l 6, cr0, [r2, #740] @ 0x2e4 │ │ + ldc2l 6, cr0, [r2, #920] @ 0x398 │ │ ldc2l 10, cr8, [r1, #108] @ 0x6c @ │ │ ldc2l 12, cr15, [r4, #432] @ 0x1b0 │ │ - ldc2l 12, cr14, [r2, #376] @ 0x178 │ │ - ldc2l 7, cr14, [r1, #292] @ 0x124 │ │ + ldc2l 12, cr14, [r2, #556] @ 0x22c │ │ + ldc2l 7, cr14, [r1, #472] @ 0x1d8 │ │ ldc2l 3, cr2, [r4, #724] @ 0x2d4 │ │ ldc2l 4, cr6, [r1, #716] @ 0x2cc │ │ - ldc2l 9, cr6, [r2, #162] @ 0xa2 @ │ │ + ldc2l 9, cr6, [r2, #252] @ 0xfc @ │ │ ldc2l 1, cr10, [r4, #340] @ 0x154 │ │ ldc2l 3, cr2, [r4, #52] @ 0x34 │ │ - ldc2l 8, cr6, [r2, #852] @ 0x354 │ │ - ldc2l 7, cr8, [r2, #748] @ 0x2ec │ │ + ldc2l 9, cr6, [r2, #4] @ │ │ + ldc2l 7, cr8, [r2, #928] @ 0x3a0 │ │ ldc2l 2, cr2, [r4, #588] @ 0x24c │ │ - ldc2l 3, cr4, [r3, #52] @ 0x34 │ │ + ldc2l 3, cr4, [r3, #232] @ 0xe8 │ │ ldc2l 9, cr13, [r4, #370] @ 0x172 @ │ │ ldc2l 0, cr10, [r4, #172] @ 0xac │ │ ldc2l 2, cr3, [r5, #56] @ 0x38 │ │ ldc2l 14, cr9, [r4, #576] @ 0x240 │ │ - ldc2l 3, cr10, [r3, #720] @ 0x2d0 │ │ - ldc2l 0, cr8, [r3, #636] @ 0x27c │ │ + ldc2l 3, cr10, [r3, #900] @ 0x384 │ │ + ldc2l 0, cr8, [r3, #816] @ 0x330 │ │ ldc2l 14, cr5, [r4, #260] @ 0x104 │ │ ldc2l 11, cr10, [r1, #552] @ 0x228 @ │ │ - ldc2l 7, cr12, [r2, #628] @ 0x274 │ │ - ldc2l 1, cr4, [r3, #828] @ 0x33c │ │ + ldc2l 7, cr12, [r2, #808] @ 0x328 │ │ + ldc2l 1, cr4, [r3, #1008] @ 0x3f0 │ │ vcadd.f32 d28, d17, d11, #270 │ │ ldc2l 14, cr5, [r1, #220] @ 0xdc │ │ - ldc2l 1, cr4, [r3, #472] @ 0x1d8 │ │ + ldc2l 1, cr4, [r3, #652] @ 0x28c │ │ ldc2l 1, cr6, [r1, #784] @ 0x310 │ │ ldc2l 3, cr1, [r5, #956] @ 0x3bc │ │ ldc2l 7, cr11, [r4, #612] @ 0x264 │ │ - ldc2l 2, cr10, [r3, #380] @ 0x17c │ │ - ldc2l 5, cr8, [r2, #256] @ 0x100 │ │ + ldc2l 2, cr10, [r3, #560] @ 0x230 │ │ + ldc2l 5, cr8, [r2, #436] @ 0x1b4 │ │ ldc2l 0, cr2, [r4, #172] @ 0xac │ │ - ldc2l 7, cr10, [r2, #728] @ 0x2d8 │ │ + ldc2l 7, cr10, [r2, #908] @ 0x38c │ │ ldc2l 7, cr13, [r4, #332] @ 0x14c │ │ ldc2l 0, cr6, [r1, #852] @ 0x354 │ │ - ldc2l 4, cr8, [r2, #644] @ 0x284 │ │ - ldc2l 7, cr14, [r2, #864] @ 0x360 │ │ + ldc2l 4, cr8, [r2, #824] @ 0x338 │ │ + vcadd.f32 d30, d2, d5, #270 │ │ ldc2l 7, cr15, [r4, #712] @ 0x2c8 │ │ ldc2l 1, cr3, [r5, #632] @ 0x278 │ │ ldc2l 9, cr10, [r1, #110] @ 0x6e @ │ │ ldc2l 2, cr1, [r5, #296] @ 0x128 │ │ - ldc2l 6, cr10, [r2, #564] @ 0x234 │ │ - ldc2l 5, cr12, [r2, #40] @ 0x28 │ │ - ldc2l 5, cr2, [r2, #144] @ 0x90 │ │ + ldc2l 6, cr10, [r2, #744] @ 0x2e8 │ │ + ldc2l 5, cr12, [r2, #220] @ 0xdc │ │ + ldc2l 5, cr2, [r2, #324] @ 0x144 │ │ ldc2l 13, cr3, [r4, #708] @ 0x2c4 │ │ - ldc2l 15, cr3, [r3, #124] @ 0x7c │ │ + ldc2l 15, cr3, [r3, #304] @ 0x130 │ │ ldc2l 12, cr9, [r4, #428] @ 0x1ac │ │ ldc2l 0, cr3, [r5, #624] @ 0x270 │ │ - ldc2l 14, cr3, [r3, #856] @ 0x358 │ │ - ldc2l 1, cr14, [r1, #284] @ 0x11c │ │ - ldc2l 15, cr9, [r3, #816] @ 0x330 │ │ + ldc2l 15, cr3, [r3, #12] │ │ + ldc2l 1, cr14, [r1, #464] @ 0x1d0 │ │ + ldc2l 15, cr9, [r3, #996] @ 0x3e4 │ │ ldc2l 5, cr13, [r4, #116] @ 0x74 │ │ ldc2l 14, cr11, [r3, #252] @ 0xfc │ │ ldc2l 3, cr8, [r1, #92] @ 0x5c │ │ - ldc2l 12, cr7, [r3, #88] @ 0x58 │ │ + ldc2l 12, cr7, [r3, #268] @ 0x10c │ │ ldc2l 4, cr11, [r4, #100] @ 0x64 │ │ ldc2l 4, cr11, [r4, #16] │ │ - ldc2l 1, cr8, [r2, #768] @ 0x300 │ │ - ldc2l 0, cr14, [r1, #40] @ 0x28 │ │ + ldc2l 1, cr8, [r2, #948] @ 0x3b4 │ │ + ldc2l 0, cr14, [r1, #220] @ 0xdc │ │ ldc2l 15, cr0, [r5, #920] @ 0x398 │ │ ldc2l 13, cr13, [r3, #416] @ 0x1a0 │ │ - ldc2l 2, cr4, [r2, #132] @ 0x84 │ │ - ldc2l 2, cr2, [r2, #532] @ 0x214 │ │ - ldc2l 3, cr10, [r2, #644] @ 0x284 │ │ + ldc2l 2, cr4, [r2, #312] @ 0x138 │ │ + ldc2l 2, cr2, [r2, #712] @ 0x2c8 │ │ + ldc2l 3, cr10, [r2, #824] @ 0x338 │ │ ldc2l 15, cr15, [r3, #560] @ 0x230 │ │ ldc2l 3, cr13, [r4, #228] @ 0xe4 │ │ ldc2l 3, cr13, [r4, #136] @ 0x88 │ │ - ldc2l 10, cr7, [r3, #532] @ 0x214 @ │ │ + ldc2l 10, cr7, [r3, #712] @ 0x2c8 @ │ │ ldc2l 2, cr11, [r4, #564] @ 0x234 │ │ ldc2l 12, cr5, [r1, #412] @ 0x19c │ │ - ldc2l 1, cr6, [r2, #84] @ 0x54 │ │ + ldc2l 1, cr6, [r2, #264] @ 0x108 │ │ ldc2l 12, cr5, [r1, #164] @ 0xa4 │ │ - ldc2l 3, cr14, [r2, #172] @ 0xac │ │ - ldc2l 2, cr10, [r2, #420] @ 0x1a4 │ │ + ldc2l 3, cr14, [r2, #352] @ 0x160 │ │ + ldc2l 2, cr10, [r2, #600] @ 0x258 │ │ ldc2l 2, cr12, [r1, #60] @ 0x3c │ │ ldc2l 1, cr12, [r1, #948] @ 0x3b4 │ │ - ldc2l 12, cr15, [r1, #516] @ 0x204 │ │ + ldc2l 12, cr15, [r1, #696] @ 0x2b8 │ │ ldc2l 1, cr13, [r4, #568] @ 0x238 │ │ - ldc2l 0, cr2, [r2, #372] @ 0x174 │ │ + ldc2l 0, cr2, [r2, #552] @ 0x228 │ │ ldc2l 10, cr5, [r1, #996] @ 0x3e4 @ │ │ - ldc2l 15, cr5, [r2, #508] @ 0x1fc │ │ - ldc2l 1, cr14, [r2, #960] @ 0x3c0 │ │ + ldc2l 15, cr5, [r2, #688] @ 0x2b0 │ │ + ldc2l 2, cr14, [r2, #116] @ 0x74 │ │ ldc2l 12, cr0, [r5, #812] @ 0x32c │ │ - ldc2l 15, cr11, [r2, #732] @ 0x2dc │ │ + ldc2l 15, cr11, [r2, #912] @ 0x390 │ │ ldc2l 10, cr5, [r1, #444] @ 0x1bc @ │ │ - ldc2l 14, cr5, [r2, #1004] @ 0x3ec │ │ + ldc2l 15, cr5, [r2, #160] @ 0xa0 │ │ ldc2l 14, cr7, [r1, #764] @ 0x2fc │ │ ldc2l 8, cr1, [r4, #880] @ 0x370 │ │ - ldc2l 1, cr14, [r2, #8] │ │ - ldc2l 5, cr5, [r3, #948] @ 0x3b4 │ │ - ldc2l 5, cr5, [r3, #812] @ 0x32c │ │ + ldc2l 1, cr14, [r2, #188] @ 0xbc │ │ + ldc2l 6, cr5, [r3, #104] @ 0x68 │ │ + ldc2l 5, cr5, [r3, #992] @ 0x3e0 │ │ ldc2l 10, cr11, [r3, #240] @ 0xf0 @ │ │ - ldc2l 14, cr11, [r2, #508] @ 0x1fc │ │ + ldc2l 14, cr11, [r2, #688] @ 0x2b0 │ │ ldc2l 11, cr15, [r3, #740] @ 0x2e4 @ │ │ - ldc2l 11, cr13, [r1, #172] @ 0xac @ │ │ + ldc2l 11, cr13, [r1, #352] @ 0x160 @ │ │ ldc2l 7, cr1, [r4, #680] @ 0x2a8 │ │ ldc2l 4, cr5, [r4, #208] @ 0xd0 │ │ - ldc2l 9, cr15, [r1, #410] @ 0x19a @ │ │ + ldc2l 9, cr15, [r1, #500] @ 0x1f4 @ │ │ ldc2l 15, cr14, [r4, #548] @ 0x224 │ │ ldc2l 13, cr6, [r4, #756] @ 0x2f4 │ │ - ldc2l 10, cr13, [r1, #332] @ 0x14c @ │ │ - ldc2l 10, cr13, [r1, #188] @ 0xbc @ │ │ + ldc2l 10, cr13, [r1, #512] @ 0x200 @ │ │ + ldc2l 10, cr13, [r1, #368] @ 0x170 @ │ │ ldc2l 9, cr2, [r5, #26] @ │ │ - ldc2l 14, cr13, [r2, #944] @ 0x3b0 │ │ - ldc2l 12, cr11, [r2, #868] @ 0x364 │ │ - ldc2l 11, cr7, [r2, #352] @ 0x160 @ │ │ - ldc2l 9, cr1, [r3, #470] @ 0x1d6 @ │ │ - ldc2l 13, cr9, [r2, #772] @ 0x304 │ │ - ldc2l 8, cr15, [r2, #216] @ 0xd8 │ │ + ldc2l 15, cr13, [r2, #100] @ 0x64 │ │ + ldc2l 13, cr11, [r2, #24] │ │ + ldc2l 11, cr7, [r2, #532] @ 0x214 @ │ │ + ldc2l 10, cr1, [r3, #96] @ 0x60 @ │ │ + ldc2l 13, cr9, [r2, #952] @ 0x3b8 │ │ + vcadd.f32 , q1, , #270 │ │ ldc2l 7, cr11, [r3, #768] @ 0x300 │ │ ldc2l 2, cr5, [r4, #440] @ 0x1b8 │ │ ldr r1, [pc, #-496] @ 24fd340 │ │ mov r2, #1 │ │ strb r2, [r3] │ │ mov r0, r8 │ │ add r1, pc, r1 │ │ @@ -1499835,116 +1499835,116 @@ │ │ mov r1, sl │ │ bl 270d9e0 │ │ ldr r1, [pc, #3580] @ 2500320 │ │ b 24ff6cc │ │ ldc2l 13, cr11, [r1, #220] @ 0xdc │ │ ldc2l 4, cr3, [r4, #608] @ 0x260 │ │ ldc2l 11, cr10, [r4, #72] @ 0x48 @ │ │ - ldc2l 8, cr11, [r2, #504] @ 0x1f8 │ │ - ldc2l 8, cr1, [r3, #864] @ 0x360 │ │ + vcadd.f32 d27, d18, d27, #270 │ │ + ldc2l 9, cr1, [r3, #10] @ │ │ vcadd.f32 , , , #270 │ │ - ldc2l 11, cr1, [r2, #388] @ 0x184 @ │ │ + ldc2l 11, cr1, [r2, #568] @ 0x238 @ │ │ ldc2l 7, cr2, [r5, #200] @ 0xc8 │ │ - ldc2l 6, cr9, [r3, #692] @ 0x2b4 │ │ - ldc2l 6, cr9, [r3, #552] @ 0x228 │ │ - ldc2l 10, cr11, [r2, #760] @ 0x2f8 @ │ │ + ldc2l 6, cr9, [r3, #872] @ 0x368 │ │ + ldc2l 6, cr9, [r3, #732] @ 0x2dc │ │ + ldc2l 10, cr11, [r2, #940] @ 0x3ac @ │ │ ldc2l 5, cr0, [r5, #520] @ 0x208 │ │ ldc2l 2, cr9, [r4, #240] @ 0xf0 │ │ ldc2l 3, cr3, [r4, #236] @ 0xec │ │ - ldc2l 10, cr1, [r2, #488] @ 0x1e8 @ │ │ - ldc2l 8, cr7, [r2, #884] @ 0x374 │ │ + ldc2l 10, cr1, [r2, #668] @ 0x29c @ │ │ + ldc2l 9, cr7, [r2, #20] @ │ │ ldc2l 11, cr12, [r4, #308] @ 0x134 @ │ │ - ldc2l 4, cr3, [r3, #364] @ 0x16c │ │ + ldc2l 4, cr3, [r3, #544] @ 0x220 │ │ ldc2l 11, cr12, [r4, #136] @ 0x88 @ │ │ - ldc2l 11, cr9, [r2, #128] @ 0x80 @ │ │ - ldc2l 9, cr11, [r2, #316] @ 0x13c @ │ │ - ldc2l 5, cr15, [r1, #404] @ 0x194 │ │ + ldc2l 11, cr9, [r2, #308] @ 0x134 @ │ │ + ldc2l 9, cr11, [r2, #406] @ 0x196 @ │ │ + ldc2l 5, cr15, [r1, #584] @ 0x248 │ │ ldc2l 15, cr8, [r4, #624] @ 0x270 │ │ ldc2l 12, cr9, [r1, #960] @ 0x3c0 │ │ - ldc2l 1, cr7, [r3, #684] @ 0x2ac │ │ + ldc2l 1, cr7, [r3, #864] @ 0x360 │ │ ldc2l 0, cr9, [r4, #756] @ 0x2f4 │ │ ldc2l 12, cr9, [r1, #600] @ 0x258 │ │ - ldc2l 1, cr7, [r3, #452] @ 0x1c4 │ │ + ldc2l 1, cr7, [r3, #632] @ 0x278 │ │ ldc2l 2, cr1, [r4, #300] @ 0x12c │ │ ldc2l 9, cr11, [r1, #364] @ 0x16c @ │ │ - ldc2l 8, cr11, [r2, #364] @ 0x16c │ │ - vcadd.f32 , q1, q4, #270 │ │ + vcadd.f32 d27, d18, d8, #270 │ │ + ldc2l 8, cr1, [r2, #468] @ 0x1d4 │ │ ldc2l 7, cr7, [r1, #528] @ 0x210 │ │ - ldc2l 2, cr3, [r3, #268] @ 0x10c │ │ - ldc2l 9, cr13, [r2, #458] @ 0x1ca @ │ │ + ldc2l 2, cr3, [r3, #448] @ 0x1c0 │ │ + ldc2l 10, cr13, [r2, #72] @ 0x48 @ │ │ ldc2l 3, cr2, [r5, #768] @ 0x300 │ │ ldc2l 4, cr0, [r5, #692] @ 0x2b4 │ │ vcadd.f32 q14, q10, , #270 │ │ ldc2l 15, cr8, [r4, #104] @ 0x68 │ │ - ldc2l 3, cr15, [r1, #260] @ 0x104 │ │ + ldc2l 3, cr15, [r1, #440] @ 0x1b8 │ │ vcadd.f32 , , q11, #270 │ │ ldc2l 13, cr4, [r4, #404] @ 0x194 │ │ - ldc2l 15, cr6, [r3, #616] @ 0x268 │ │ + ldc2l 15, cr6, [r3, #796] @ 0x31c │ │ vcadd.f32 d27, d1, d13, #270 │ │ ldc2l 14, cr8, [r4, #384] @ 0x180 │ │ - ldc2l 3, cr9, [r2, #496] @ 0x1f0 │ │ + ldc2l 3, cr9, [r2, #676] @ 0x2a4 │ │ ldc2l 9, cr4, [r4, #144] @ 0x90 @ │ │ ldc2l 9, cr9, [r1, #502] @ 0x1f6 @ │ │ vcadd.f32 d30, d4, d11, #270 │ │ - ldc2l 4, cr7, [r2, #704] @ 0x2c0 │ │ - ldc2l 7, cr13, [r2, #1000] @ 0x3e8 │ │ + ldc2l 4, cr7, [r2, #884] @ 0x374 │ │ + vcadd.f32 d29, d2, d23, #270 │ │ ldc2l 1, cr11, [r3, #412] @ 0x19c │ │ ldc2l 0, cr13, [r3, #404] @ 0x194 │ │ ldc2l 2, cr0, [r5, #664] @ 0x298 │ │ ldc2l 6, cr11, [r1, #780] @ 0x30c │ │ ldc2l 6, cr11, [r1, #632] @ 0x278 │ │ ldc2l 6, cr11, [r1, #476] @ 0x1dc │ │ ldc2l 11, cr4, [r1, #924] @ 0x39c @ │ │ ldc2l 4, cr7, [r1, #364] @ 0x16c │ │ - ldc2l 4, cr11, [r2, #912] @ 0x390 │ │ - ldc2l 2, cr1, [r3, #108] @ 0x6c │ │ + ldc2l 5, cr11, [r2, #68] @ 0x44 │ │ + ldc2l 2, cr1, [r3, #288] @ 0x120 │ │ ldc2l 13, cr2, [r4, #352] @ 0x160 │ │ ldc2l 0, cr2, [r5, #508] @ 0x1fc │ │ ldc2l 1, cr15, [r3, #760] @ 0x2f8 │ │ - ldc2l 4, cr1, [r2, #340] @ 0x154 │ │ + ldc2l 4, cr1, [r2, #520] @ 0x208 │ │ ldc2l 14, cr4, [r1, #704] @ 0x2c0 │ │ ldc2l 5, cr14, [r4, #880] @ 0x370 │ │ ldc2l 4, cr10, [r4, #532] @ 0x214 │ │ ldc2l 14, cr12, [r3, #440] @ 0x1b8 │ │ - ldc2l 2, cr7, [r2, #160] @ 0xa0 │ │ - ldc2l 15, cr14, [r1, #556] @ 0x22c │ │ + ldc2l 2, cr7, [r2, #340] @ 0x154 │ │ + ldc2l 15, cr14, [r1, #736] @ 0x2e0 │ │ ldc2l 11, cr8, [r4, #148] @ 0x94 @ │ │ - ldc2l 10, cr4, [r3, #92] @ 0x5c @ │ │ + ldc2l 10, cr4, [r3, #272] @ 0x110 @ │ │ ldc2l 13, cr4, [r1, #740] @ 0x2e4 │ │ ldc2l 3, cr6, [r4, #236] @ 0xec │ │ - ldc2l 4, cr13, [r2, #736] @ 0x2e0 │ │ - ldc2l 2, cr11, [r2, #868] @ 0x364 │ │ - ldc2l 14, cr14, [r2, #500] @ 0x1f4 │ │ + ldc2l 4, cr13, [r2, #916] @ 0x394 │ │ + ldc2l 3, cr11, [r2, #24] │ │ + ldc2l 14, cr14, [r2, #680] @ 0x2a8 │ │ vcadd.f32 q10, q10, q0, #270 │ │ ldc2l 15, cr14, [r3, #660] @ 0x294 │ │ - ldc2l 14, cr14, [r1, #80] @ 0x50 │ │ + ldc2l 14, cr14, [r1, #260] @ 0x104 │ │ ldc2l 12, cr15, [r4, #824] @ 0x338 │ │ - ldc2l 12, cr2, [r3, #176] @ 0xb0 │ │ - ldc2l 3, cr9, [r2, #4] │ │ - ldc2l 1, cr1, [r2, #824] @ 0x338 │ │ + ldc2l 12, cr2, [r3, #356] @ 0x164 │ │ + ldc2l 3, cr9, [r2, #184] @ 0xb8 │ │ + ldc2l 1, cr1, [r2, #1004] @ 0x3ec │ │ ldc2l 13, cr1, [r5, #536] @ 0x218 │ │ ldc2l 0, cr7, [r1, #736] @ 0x2e0 │ │ - ldc2l 15, cr6, [r2, #788] @ 0x314 │ │ - ldc2l 12, cr14, [r2, #1004] @ 0x3ec │ │ - ldc2l 11, cr2, [r3, #252] @ 0xfc @ │ │ - ldc2l 0, cr11, [r2, #976] @ 0x3d0 │ │ - ldc2l 14, cr0, [r3, #80] @ 0x50 │ │ + ldc2l 15, cr6, [r2, #968] @ 0x3c8 │ │ + ldc2l 13, cr14, [r2, #160] @ 0xa0 │ │ + ldc2l 11, cr2, [r3, #432] @ 0x1b0 @ │ │ + ldc2l 1, cr11, [r2, #132] @ 0x84 │ │ + ldc2l 14, cr0, [r3, #260] @ 0x104 │ │ ldc2l 9, cr2, [r4, #150] @ 0x96 @ │ │ - ldc2l 13, cr0, [r3, #764] @ 0x2fc │ │ + ldc2l 13, cr0, [r3, #944] @ 0x3b0 │ │ ldc2l 7, cr8, [r4, #944] @ 0x3b0 │ │ ldc2l 13, cr14, [r3, #468] @ 0x1d4 │ │ - ldc2l 0, cr11, [r2, #68] @ 0x44 │ │ + ldc2l 0, cr11, [r2, #248] @ 0xf8 │ │ ldc2l 9, cr0, [r4, #196] @ 0xc4 @ │ │ ldc2l 11, cr1, [r5, #732] @ 0x2dc @ │ │ ldc2l 3, cr9, [r1, #272] @ 0x110 │ │ ldc2l 1, cr14, [r4, #268] @ 0x10c │ │ ldc2l 12, cr14, [r3, #648] @ 0x288 │ │ ldc2l 12, cr15, [r4, #12] │ │ ldc2l 0, cr14, [r4, #768] @ 0x300 │ │ - ldc2l 14, cr4, [r2, #140] @ 0x8c │ │ + ldc2l 14, cr4, [r2, #320] @ 0x140 │ │ ldc2l 10, cr10, [r3, #32] @ │ │ movw r7, #5472 @ 0x1560 │ │ add r0, r8, r7 │ │ mov r2, #32 │ │ add r1, pc, r1 │ │ mov r3, #10 │ │ bl 270d9e0 │ │ @@ -1500709,106 +1500709,106 @@ │ │ ldr r0, [sp, #8] │ │ ldr r1, [r0] │ │ mov r0, #0 │ │ cmp r1, #230 @ 0xe6 │ │ movwgt r0, #1 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 14, cr0, [r2, #536] @ 0x218 │ │ - ldc2l 8, cr2, [r3, #592] @ 0x250 │ │ + ldc2l 14, cr0, [r2, #716] @ 0x2cc │ │ + vcadd.f32 q9, , , #270 │ │ ldc2l 13, cr6, [r1, #636] @ 0x27c │ │ ldc2l 14, cr9, [r4, #796] @ 0x31c │ │ ldc2l 9, cr1, [r5, #484] @ 0x1e4 @ │ │ ldc2l 10, cr15, [r4, #752] @ 0x2f0 @ │ │ - ldc2l 15, cr12, [r2, #532] @ 0x214 │ │ + ldc2l 15, cr12, [r2, #712] @ 0x2c8 │ │ ldc2l 8, cr15, [r4, #248] @ 0xf8 │ │ ldc2l 10, cr14, [r3, #788] @ 0x314 @ │ │ - ldc2l 15, cr12, [r2, #148] @ 0x94 │ │ + ldc2l 15, cr12, [r2, #328] @ 0x148 │ │ ldc2l 15, cr3, [r4, #944] @ 0x3b0 │ │ ldc2l 13, cr5, [r4, #184] @ 0xb8 │ │ - ldc2l 3, cr4, [r3, #740] @ 0x2e4 │ │ + ldc2l 3, cr4, [r3, #920] @ 0x398 │ │ ldc2l 6, cr0, [r4, #372] @ 0x174 │ │ ldc2l 8, cr1, [r5, #736] @ 0x2e0 │ │ - ldc2l 8, cr14, [r2, #448] @ 0x1c0 │ │ - ldc2l 9, cr0, [r3, #374] @ 0x176 @ │ │ + ldc2l 8, cr14, [r2, #628] @ 0x274 │ │ + ldc2l 9, cr0, [r3, #464] @ 0x1d0 @ │ │ ldc2l 13, cr11, [r4, #440] @ 0x1b8 │ │ - ldc2l 6, cr14, [r1, #464] @ 0x1d0 │ │ - ldc2l 9, cr2, [r2, #378] @ 0x17a @ │ │ - ldc2l 4, cr2, [r3, #428] @ 0x1ac │ │ - ldc2l 8, cr6, [r2, #364] @ 0x16c │ │ + ldc2l 6, cr14, [r1, #644] @ 0x284 │ │ + ldc2l 9, cr2, [r2, #468] @ 0x1d4 @ │ │ + ldc2l 4, cr2, [r3, #608] @ 0x260 │ │ + vcadd.f32 d22, d18, d8, #270 │ │ ldc2l 4, cr4, [r1, #324] @ 0x144 │ │ - ldc2l 9, cr10, [r2, #268] @ 0x10c @ │ │ + ldc2l 9, cr10, [r2, #358] @ 0x166 @ │ │ ldc2l 5, cr1, [r5, #404] @ 0x194 │ │ - vcadd.f32 d18, d18, d27, #270 │ │ + ldc2l 8, cr2, [r2, #864] @ 0x360 │ │ ldc2l 5, cr1, [r5, #228] @ 0xe4 │ │ - ldc2l 5, cr14, [r1, #12] │ │ + ldc2l 5, cr14, [r1, #192] @ 0xc0 │ │ ldc2l 6, cr14, [r3, #244] @ 0xf4 │ │ ldc2l 14, cr3, [r4, #948] @ 0x3b4 │ │ - ldc2l 5, cr12, [r1, #416] @ 0x1a0 │ │ - ldc2l 3, cr8, [r3, #868] @ 0x364 │ │ - ldc2l 0, cr6, [r3, #692] @ 0x2b4 │ │ + ldc2l 5, cr12, [r1, #596] @ 0x254 │ │ + ldc2l 4, cr8, [r3, #24] │ │ + ldc2l 0, cr6, [r3, #872] @ 0x368 │ │ ldc2l 3, cr10, [r3, #456] @ 0x1c8 │ │ ldc2l 7, cr6, [r1, #248] @ 0xf8 │ │ - ldc2l 0, cr6, [r3, #316] @ 0x13c │ │ + ldc2l 0, cr6, [r3, #496] @ 0x1f0 │ │ ldc2l 3, cr1, [r5, #684] @ 0x2ac │ │ vcadd.f32 d26, d17, d31, #270 │ │ - ldc2l 7, cr10, [r2, #456] @ 0x1c8 │ │ - ldc2l 7, cr10, [r2, #324] @ 0x144 │ │ - ldc2l 13, cr3, [r3, #844] @ 0x34c │ │ + ldc2l 7, cr10, [r2, #636] @ 0x27c │ │ + ldc2l 7, cr10, [r2, #504] @ 0x1f8 │ │ + ldc2l 14, cr3, [r3] │ │ ldc2l 7, cr5, [r4] │ │ ldc2l 10, cr8, [r1, #284] @ 0x11c @ │ │ ldc2l 10, cr8, [r1, #152] @ 0x98 @ │ │ - ldc2l 14, cr5, [r3, #896] @ 0x380 │ │ - ldc2l 3, cr12, [r1, #48] @ 0x30 │ │ + ldc2l 15, cr5, [r3, #52] @ 0x34 │ │ + ldc2l 3, cr12, [r1, #228] @ 0xe4 │ │ ldc2l 15, cr15, [r3, #520] @ 0x208 │ │ - ldc2l 6, cr8, [r2, #1020] @ 0x3fc │ │ + ldc2l 7, cr8, [r2, #176] @ 0xb0 │ │ ldc2l 1, cr1, [r5, #792] @ 0x318 │ │ ldc2l 15, cr15, [r3, #180] @ 0xb4 │ │ - ldc2l 12, cr3, [r3, #260] @ 0x104 │ │ + ldc2l 12, cr3, [r3, #440] @ 0x1b8 │ │ ldc2l 9, cr8, [r1, #38] @ 0x26 @ │ │ - ldc2l 0, cr8, [r3, #732] @ 0x2dc │ │ - ldc2l 4, cr4, [r2, #424] @ 0x1a8 │ │ + ldc2l 0, cr8, [r3, #912] @ 0x390 │ │ + ldc2l 4, cr4, [r2, #604] @ 0x25c │ │ ldc2l 12, cr7, [r4, #532] @ 0x214 │ │ ldc2l 4, cr6, [r1, #60] @ 0x3c │ │ ldc2l 5, cr11, [r4, #708] @ 0x2c4 │ │ - ldc2l 14, cr1, [r3, #736] @ 0x2e0 │ │ - ldc2l 5, cr8, [r2, #644] @ 0x284 │ │ + ldc2l 14, cr1, [r3, #916] @ 0x394 │ │ + ldc2l 5, cr8, [r2, #824] @ 0x338 │ │ ldc2l 5, cr11, [r4, #436] @ 0x1b4 │ │ ldc2l 14, cr11, [r3, #716] @ 0x2cc │ │ - ldc2l 5, cr12, [r2, #980] @ 0x3d4 │ │ - ldc2l 3, cr2, [r2, #292] @ 0x124 │ │ - ldc2l 3, cr4, [r2, #116] @ 0x74 │ │ - ldc2l 3, cr0, [r2, #656] @ 0x290 │ │ + ldc2l 6, cr12, [r2, #136] @ 0x88 │ │ + ldc2l 3, cr2, [r2, #472] @ 0x1d8 │ │ + ldc2l 3, cr4, [r2, #296] @ 0x128 │ │ + ldc2l 3, cr0, [r2, #836] @ 0x344 │ │ ldc2l 7, cr8, [r1, #224] @ 0xe0 │ │ ldc2l 5, cr13, [r4, #212] @ 0xd4 │ │ - ldc2l 5, cr12, [r2, #248] @ 0xf8 │ │ + ldc2l 5, cr12, [r2, #428] @ 0x1ac │ │ ldc2l 0, cr14, [r3, #572] @ 0x23c │ │ ldc2l 14, cr9, [r3, #572] @ 0x23c │ │ ldc2l 4, cr13, [r4, #760] @ 0x2f8 │ │ ldc2l 2, cr6, [r1, #124] @ 0x7c │ │ ldc2l 3, cr11, [r4, #740] @ 0x2e4 │ │ ldc2l 15, cr14, [r4, #436] @ 0x1b4 │ │ - ldc2l 3, cr8, [r2, #676] @ 0x2a4 │ │ + ldc2l 3, cr8, [r2, #856] @ 0x358 │ │ ldc2l 1, cr6, [r1, #764] @ 0x2fc │ │ ldc2l 15, cr14, [r4, #80] @ 0x50 │ │ - ldc2l 1, cr2, [r2, #400] @ 0x190 │ │ - ldc2l 13, cr13, [r1, #732] @ 0x2dc │ │ - ldc2l 1, cr0, [r2, #720] @ 0x2d0 │ │ + ldc2l 1, cr2, [r2, #580] @ 0x244 │ │ + ldc2l 13, cr13, [r1, #912] @ 0x390 │ │ + ldc2l 1, cr0, [r2, #900] @ 0x384 │ │ ldc2l 3, cr13, [r4, #460] @ 0x1cc │ │ ldc2l 9, cr7, [r4, #44] @ 0x2c @ │ │ ldc2l 11, cr11, [r3, #816] @ 0x330 @ │ │ ldc2l 14, cr14, [r4, #36] @ 0x24 │ │ - ldc2l 7, cr3, [r3, #688] @ 0x2b0 │ │ - ldc2l 12, cr7, [r3, #296] @ 0x128 │ │ + ldc2l 7, cr3, [r3, #868] @ 0x364 │ │ + ldc2l 12, cr7, [r3, #476] @ 0x1dc │ │ ldc2l 1, cr9, [r4, #248] @ 0xf8 │ │ - ldc2l 1, cr8, [r2, #848] @ 0x350 │ │ + ldc2l 2, cr8, [r2, #4] │ │ ldc2l 15, cr5, [r1, #944] @ 0x3b0 │ │ - ldc2l 8, cr5, [r3, #852] @ 0x354 │ │ + ldc2l 9, cr5, [r3, #4] @ │ │ ldc2l 6, cr3, [r4, #308] @ 0x134 │ │ - ldc2l 11, cr13, [r1, #884] @ 0x374 @ │ │ + ldc2l 12, cr13, [r1, #40] @ 0x28 │ │ ldc2l 0, cr9, [r4, #356] @ 0x164 │ │ ldc2l 11, cr9, [r3, #24] @ │ │ │ │ 02500450 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #52 @ 0x34 │ │ @@ -1500983,33 +1500983,33 @@ │ │ ldr r0, [pc, #92] @ 2500760 │ │ mov r1, #8 │ │ add r0, pc, r0 │ │ bl 270ceb0 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 9, cr11, [r1, #438] @ 0x1b6 @ │ │ + ldc2l 10, cr11, [r1, #32] @ │ │ ldc2l 2, cr3, [r4, #728] @ 0x2d8 │ │ - ldc2l 9, cr2, [r2, #490] @ 0x1ea @ │ │ + ldc2l 10, cr2, [r2, #136] @ 0x88 @ │ │ ldc2l 10, cr12, [r4, #772] @ 0x304 @ │ │ ldc2l 2, cr9, [r3, #368] @ 0x170 │ │ - ldc2l 10, cr2, [r2, #164] @ 0xa4 @ │ │ - vcadd.f32 , q1, q1, #270 │ │ - ldc2l 7, cr1, [r2, #928] @ 0x3a0 │ │ + ldc2l 10, cr2, [r2, #344] @ 0x158 @ │ │ + vcadd.f32 , q1, , #270 │ │ + ldc2l 8, cr1, [r2, #84] @ 0x54 │ │ ldc2l 7, cr9, [r3, #612] @ 0x264 │ │ ldc2l 13, cr8, [sp, #816] @ 0x330 │ │ - ldc2l 7, cr1, [r2, #720] @ 0x2d0 │ │ + ldc2l 7, cr1, [r2, #900] @ 0x384 │ │ ldc2l 7, cr9, [r3, #404] @ 0x194 │ │ - ldc2l 14, cr2, [r3, #16] │ │ + ldc2l 14, cr2, [r3, #196] @ 0xc4 │ │ ldc2l 7, cr9, [r3, #164] @ 0xa4 │ │ eoreq fp, r5, r0, lsr #32 │ │ eoreq fp, r5, ip │ │ - ldc2l 9, cr3, [r2, #494] @ 0x1ee @ │ │ + ldc2l 10, cr3, [r2, #144] @ 0x90 @ │ │ ldc2l 13, cr6, [r4, #700] @ 0x2bc │ │ - ldc2l 7, cr11, [r1, #348] @ 0x15c │ │ + ldc2l 7, cr11, [r1, #528] @ 0x210 │ │ │ │ 02500764 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ vpush {d8-d9} │ │ sub sp, sp, #152 @ 0x98 │ │ vldmia r1, {d17-d18} │ │ @@ -1501259,15 +1501259,15 @@ │ │ sub sp, fp, #40 @ 0x28 │ │ vpop {d8} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ nop {0} │ │ andeq r0, r0, r0 │ │ submi r8, sp, r0 │ │ - ldc2l 7, cr2, [r3, #512] @ 0x200 │ │ + ldc2l 7, cr2, [r3, #692] @ 0x2b4 │ │ eoreq sl, r5, ip, lsl #24 │ │ │ │ 02500b58 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r2 │ │ mov r6, r1 │ │ @@ -1501317,20 +1501317,20 @@ │ │ ldr r0, [r6, #4] │ │ cmp r0, #0 │ │ bne 2500bf0 │ │ ldr r0, [pc, #16] @ 2500c38 │ │ mov r1, #143 @ 0x8f │ │ add r0, pc, r0 │ │ b 2500bc4 │ │ - ldc2l 0, cr1, [r3, #172] @ 0xac │ │ - ldc2l 14, cr4, [r3, #288] @ 0x120 │ │ + ldc2l 0, cr1, [r3, #352] @ 0x160 │ │ + ldc2l 14, cr4, [r3, #468] @ 0x1d4 │ │ ldc2l 15, cr2, [r1, #960] @ 0x3c0 │ │ - ldc2l 3, cr2, [r2, #164] @ 0xa4 │ │ - ldc2l 8, cr4, [r2, #604] @ 0x25c │ │ - ldc2l 15, cr0, [r3, #748] @ 0x2ec │ │ + ldc2l 3, cr2, [r2, #344] @ 0x158 │ │ + vcadd.f32 q10, q9, q2, #270 │ │ + ldc2l 15, cr0, [r3, #928] @ 0x3a0 │ │ │ │ 02500c48 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ cmp r0, #2 │ │ beq 2500d08 │ │ @@ -1502595,48 +1502595,48 @@ │ │ ldrbeq sl, [sl, #528] @ 0x210 │ │ ldrbeq sl, [sl, #516] @ 0x204 │ │ ldrbeq sl, [sl, #212] @ 0xd4 │ │ ldrbeq sl, [sl, #212] @ 0xd4 │ │ ldrbeq sl, [sl, #212] @ 0xd4 │ │ ldrbeq sl, [sl, #256] @ 0x100 │ │ eoreq r9, r5, ip, asr #29 │ │ - ldc2l 10, cr6, [r2, #828] @ 0x33c @ │ │ - ldc2l 5, cr12, [r2, #308] @ 0x134 │ │ - ldc2l 13, cr4, [r2, #288] @ 0x120 │ │ + ldc2l 10, cr6, [r2, #1008] @ 0x3f0 @ │ │ + ldc2l 5, cr12, [r2, #488] @ 0x1e8 │ │ + ldc2l 13, cr4, [r2, #468] @ 0x1d4 │ │ ldrbeq r9, [sl, #4004] @ 0xfa4 │ │ ldrbeq r9, [sl, #3948] @ 0xf6c │ │ ldrbeq r9, [sl, #3892] @ 0xf34 │ │ ldrbeq r9, [sl, #3836] @ 0xefc │ │ ldrbeq r9, [sl, #4036] @ 0xfc4 │ │ ldrbeq r9, [sl, #3944] @ 0xf68 │ │ ldrbeq r9, [sl, #3700] @ 0xe74 │ │ ldrbeq r9, [sl, #3656] @ 0xe48 │ │ ldrbeq r9, [sl, #3860] @ 0xf14 │ │ ldrbeq r9, [sl, #3828] @ 0xef4 │ │ ldrbeq r9, [sl, #3584] @ 0xe00 │ │ ldrbeq r9, [sl, #3544] @ 0xdd8 │ │ ldc2l 9, cr11, [r4, #128] @ 0x80 @ │ │ - ldc2l 3, cr12, [r2, #148] @ 0x94 │ │ + ldc2l 3, cr12, [r2, #328] @ 0x148 │ │ ldrbeq r9, [sl, #3480] @ 0xd98 │ │ ldrbeq r9, [sl, #3412] @ 0xd54 │ │ ldrbeq r9, [sl, #3708] @ 0xe7c │ │ ldrbeq r9, [sl, #3492] @ 0xda4 │ │ ldc2l 8, cr7, [sp, #736] @ 0x2e0 │ │ - ldc2l 1, cr0, [r3, #112] @ 0x70 │ │ - ldc2l 2, cr12, [r2, #612] @ 0x264 │ │ + ldc2l 1, cr0, [r3, #292] @ 0x124 │ │ + ldc2l 2, cr12, [r2, #792] @ 0x318 │ │ ldrbeq r9, [sl, #3124] @ 0xc34 │ │ ldrbeq r9, [sl, #3080] @ 0xc08 │ │ ldrbeq r9, [sl, #3056] @ 0xbf0 │ │ ldrbeq r9, [sl, #3012] @ 0xbc4 │ │ - ldc2l 9, cr4, [r2, #24] @ │ │ + ldc2l 9, cr4, [r2, #114] @ 0x72 @ │ │ ldrbeq r9, [sl, #2960] @ 0xb90 │ │ ldrbeq r9, [sl, #2964] @ 0xb94 │ │ ldrbeq r9, [sl, #2916] @ 0xb64 │ │ ldrbeq r9, [sl, #2872] @ 0xb38 │ │ - ldc2l 5, cr6, [r2, #1020] @ 0x3fc │ │ + ldc2l 6, cr6, [r2, #176] @ 0xb0 │ │ ldrbeq r9, [sl, #2880] @ 0xb40 │ │ ldrbeq r9, [sl, #3040] @ 0xbe0 │ │ ldrbeq r9, [sl, #2768] @ 0xad0 │ │ ldrbeq r9, [sl, #2752] @ 0xac0 │ │ ldrbeq r9, [sl, #2932] @ 0xb74 │ │ ldrbeq r9, [sl, #2884] @ 0xb44 │ │ ldrbeq r9, [sl, #2652] @ 0xa5c │ │ @@ -1503599,50 +1503599,50 @@ │ │ str r1, [fp, #-32] @ 0xffffffe0 │ │ ldr r1, [sp, #16] │ │ add r1, r1, r2, lsl #3 │ │ sub r2, r1, #8 │ │ sub r1, fp, #32 │ │ bl 270e100 │ │ b 2502764 │ │ - ldc2l 0, cr8, [r2, #456] @ 0x1c8 │ │ + ldc2l 0, cr8, [r2, #636] @ 0x27c │ │ ldrbeq r9, [sl, #2036] @ 0x7f4 │ │ ldc2l 1, cr1, [r1, #880] @ 0x370 │ │ ldrbeq r9, [sl, #3012] @ 0xbc4 │ │ ldc2l 0, cr15, [r3, #40] @ 0x28 │ │ ldc2l 11, cr1, [r1, #272] @ 0x110 @ │ │ - ldc2l 15, cr10, [r1, #476] @ 0x1dc │ │ + ldc2l 15, cr10, [r1, #656] @ 0x290 │ │ strhteq r9, [r5], -r4 │ │ ldrbeq r9, [sl, #2836] @ 0xb14 │ │ ldrbeq r9, [sl, #1792] @ 0x700 │ │ - ldc2l 2, cr13, [r2, #768] @ 0x300 │ │ - ldc2l 11, cr0, [r2, #452] @ 0x1c4 @ │ │ + ldc2l 2, cr13, [r2, #948] @ 0x3b4 │ │ + ldc2l 11, cr0, [r2, #632] @ 0x278 @ │ │ ldrbeq r9, [sl, #1760] @ 0x6e0 │ │ - ldc2l 12, cr13, [r2, #392] @ 0x188 │ │ - ldc2l 12, cr0, [r2, #596] @ 0x254 │ │ + ldc2l 12, cr13, [r2, #572] @ 0x23c │ │ + ldc2l 12, cr0, [r2, #776] @ 0x308 │ │ ldc2l 9, cr12, [r3, #262] @ 0x106 @ │ │ ldrbeq r9, [sl, #1680] @ 0x690 │ │ ldc2l 12, cr8, [r4, #504] @ 0x1f8 │ │ ldc2l 11, cr14, [r3, #136] @ 0x88 @ │ │ ldc2l 6, cr1, [r1, #368] @ 0x170 │ │ ldrbeq r9, [sl, #1720] @ 0x6b8 │ │ - ldc2l 8, cr0, [r2, #596] @ 0x254 │ │ + vcadd.f32 q8, q9, q1, #270 │ │ ldrbeq r9, [sl, #672] @ 0x2a0 │ │ ldc2l 10, cr14, [r3, #824] @ 0x338 @ │ │ ldc2l 6, cr1, [r1, #32] │ │ - ldc2l 7, cr0, [r2, #756] @ 0x2f4 │ │ - ldc2l 10, cr11, [r1, #584] @ 0x248 @ │ │ - ldc2l 12, cr0, [r2, #68] @ 0x44 │ │ + ldc2l 7, cr0, [r2, #936] @ 0x3a8 │ │ + ldc2l 10, cr11, [r1, #764] @ 0x2fc @ │ │ + ldc2l 12, cr0, [r2, #248] @ 0xf8 │ │ ldc2l 14, cr14, [r3, #328] @ 0x148 │ │ ldc2l 9, cr1, [r1, #280] @ 0x118 @ │ │ ldrbeq r9, [sl, #2536] @ 0x9e8 │ │ - ldc2l 11, cr0, [r2, #788] @ 0x314 @ │ │ + ldc2l 11, cr0, [r2, #968] @ 0x3c8 @ │ │ ldrbeq r9, [sl, #1488] @ 0x5d0 │ │ ldc2l 13, cr14, [r3, #1016] @ 0x3f8 │ │ ldc2l 9, cr1, [r1, #112] @ 0x70 @ │ │ - ldc2l 10, cr0, [r2, #500] @ 0x1f4 @ │ │ + ldc2l 10, cr0, [r2, #680] @ 0x2a8 @ │ │ ldrbeq r9, [sl, #352] @ 0x160 │ │ ldc2l 4, cr1, [r1, #264] @ 0x108 │ │ ldc2l 4, cr1, [r1, #208] @ 0xd0 │ │ ldc2l 3, cr1, [r1, #984] @ 0x3d8 │ │ ldc2l 3, cr1, [r1, #928] @ 0x3a0 │ │ ldc2l 3, cr1, [r1, #800] @ 0x320 │ │ ldc2l 3, cr1, [r1, #504] @ 0x1f8 │ │ @@ -1503659,37 +1503659,37 @@ │ │ ldc2l 1, cr1, [r1, #920] @ 0x398 │ │ ldc2l 1, cr1, [r1, #864] @ 0x360 │ │ ldc2l 1, cr1, [r1, #736] @ 0x2e0 │ │ ldc2l 4, cr1, [r1, #872] @ 0x368 │ │ ldc2l 4, cr1, [r1, #816] @ 0x330 │ │ eoreq r8, r5, r4, ror #22 │ │ ldrbeq r8, [sl, #2456] @ 0x998 │ │ - ldc2l 10, cr7, [r2, #120] @ 0x78 @ │ │ + ldc2l 10, cr7, [r2, #300] @ 0x12c @ │ │ ldc2l 9, cr12, [r4, #236] @ 0xec @ │ │ ldc2l 12, cr14, [r3, #264] @ 0x108 │ │ ldc2l 7, cr1, [r1, #496] @ 0x1f0 │ │ ldrbeq r9, [sl, #2008] @ 0x7d8 │ │ - ldc2l 9, cr0, [r2, #362] @ 0x16a @ │ │ + ldc2l 9, cr0, [r2, #452] @ 0x1c4 @ │ │ ldrbeq r9, [sl, #960] @ 0x3c0 │ │ ldc2l 11, cr14, [r3, #952] @ 0x3b8 @ │ │ ldc2l 7, cr1, [r1, #160] @ 0xa0 │ │ ldc2l 11, cr8, [r4, #952] @ 0x3b8 @ │ │ ldc2l 10, cr14, [r3, #584] @ 0x248 @ │ │ ldc2l 5, cr1, [r1, #816] @ 0x330 │ │ ldrbeq r9, [sl, #1576] @ 0x628 │ │ - vcadd.f32 d16, d2, d5, #270 │ │ + ldc2l 8, cr0, [r2, #200] @ 0xc8 │ │ ldrbeq r9, [sl, #528] @ 0x210 │ │ ldc2l 10, cr14, [r3, #248] @ 0xf8 @ │ │ ldc2l 5, cr1, [r1, #480] @ 0x1e0 │ │ - ldc2l 9, cr11, [r1, #308] @ 0x134 @ │ │ - ldc2l 11, cr0, [r2, #100] @ 0x64 @ │ │ + ldc2l 9, cr11, [r1, #398] @ 0x18e @ │ │ + ldc2l 11, cr0, [r2, #280] @ 0x118 @ │ │ ldc2l 13, cr14, [r3, #360] @ 0x168 │ │ ldc2l 8, cr1, [r1, #592] @ 0x250 │ │ ldrbeq r9, [sl, #2288] @ 0x8f0 │ │ - ldc2l 10, cr0, [r2, #820] @ 0x334 @ │ │ + ldc2l 10, cr0, [r2, #1000] @ 0x3e8 @ │ │ ldrbeq r9, [sl, #1240] @ 0x4d8 │ │ ldc2l 13, cr14, [r3, #24] │ │ vcadd.f32 , , q0, #270 │ │ ldrbeq r8, [sl, #3440] @ 0xd70 │ │ ldc2l 0, cr1, [r1, #104] @ 0x68 │ │ ldc2l 0, cr1, [r1, #48] @ 0x30 │ │ ldc2l 15, cr0, [r1, #808] @ 0x328 │ │ @@ -1503714,24 +1503714,24 @@ │ │ ldc2l 0, cr1, [r1, #936] @ 0x3a8 │ │ ldc2l 0, cr1, [r1, #880] @ 0x370 │ │ eoreq r8, r5, r4, ror #14 │ │ vcadd.f32 q14, q10, q11, #270 │ │ ldc2l 11, cr14, [r3, #712] @ 0x2c8 @ │ │ ldc2l 6, cr1, [r1, #944] @ 0x3b0 │ │ ldrbeq r9, [sl, #1864] @ 0x748 │ │ - ldc2l 9, cr0, [r2, #74] @ 0x4a @ │ │ + ldc2l 9, cr0, [r2, #164] @ 0xa4 @ │ │ ldrbeq r9, [sl, #816] @ 0x330 │ │ ldc2l 11, cr14, [r3, #376] @ 0x178 @ │ │ ldc2l 6, cr1, [r1, #608] @ 0x260 │ │ ldc2l 8, cr1, [r1, #84] @ 0x54 │ │ ldrbeq r9, [sl, #1132] @ 0x46c │ │ ldc2l 12, cr14, [r3, #616] @ 0x268 │ │ ldc2l 7, cr1, [r1, #848] @ 0x350 │ │ ldrbeq r9, [sl, #2104] @ 0x838 │ │ - ldc2l 10, cr0, [r2, #84] @ 0x54 @ │ │ + ldc2l 10, cr0, [r2, #264] @ 0x108 @ │ │ │ │ 0250319c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #36 @ 0x24 │ │ mov r4, r3 │ │ mov r7, r2 │ │ @@ -1504222,90 +1504222,90 @@ │ │ strb r2, [fp, #-29] @ 0xffffffe3 │ │ orr r1, r1, r2, lsl #24 │ │ str r1, [r6, r0, lsl #2] │ │ add r1, r0, #1 │ │ str r1, [sp, #28] │ │ blt 25038c4 │ │ b 25037dc │ │ - ldc2l 13, cr12, [r2, #456] @ 0x1c8 │ │ + ldc2l 13, cr12, [r2, #636] @ 0x27c │ │ ldrbeq r8, [sl, #2916] @ 0xb64 │ │ ldc2l 1, cr0, [r1, #160] @ 0xa0 │ │ ldrbeq r8, [sl, #2872] @ 0xb38 │ │ ldc2l 15, cr13, [r3, #344] @ 0x158 │ │ ldc2l 0, cr7, [r1, #552] @ 0x228 │ │ - ldc2l 14, cr9, [r1, #796] @ 0x31c │ │ + ldc2l 14, cr9, [r1, #976] @ 0x3d0 │ │ eoreq r8, r5, ip, lsl #8 │ │ ldrbeq r8, [sl, #2700] @ 0xa8c │ │ ldrbeq r8, [sl, #2680] @ 0xa78 │ │ - ldc2l 2, cr12, [r2, #112] @ 0x70 │ │ - ldc2l 10, cr15, [r1, #820] @ 0x334 @ │ │ + ldc2l 2, cr12, [r2, #292] @ 0x124 │ │ + ldc2l 10, cr15, [r1, #1000] @ 0x3e8 @ │ │ ldrbeq r8, [sl, #2648] @ 0xa58 │ │ - ldc2l 11, cr12, [r2, #728] @ 0x2d8 @ │ │ - ldc2l 11, cr15, [r1, #932] @ 0x3a4 @ │ │ + ldc2l 11, cr12, [r2, #908] @ 0x38c @ │ │ + ldc2l 12, cr15, [r1, #88] @ 0x58 │ │ ldrbeq r8, [sl, #2572] @ 0xa0c │ │ ldc2l 11, cr7, [r4, #984] @ 0x3d8 @ │ │ ldc2l 10, cr13, [r3, #632] @ 0x278 @ │ │ ldc2l 11, cr6, [r1, #840] @ 0x348 @ │ │ ldrbeq r8, [sl, #1628] @ 0x65c │ │ - ldc2l 8, cr15, [r1, #68] @ 0x44 │ │ + ldc2l 8, cr15, [r1, #248] @ 0xf8 │ │ ldrbeq r8, [sl, #1604] @ 0x644 │ │ ldc2l 10, cr13, [r3, #312] @ 0x138 @ │ │ ldc2l 11, cr6, [r1, #520] @ 0x208 @ │ │ - ldc2l 7, cr15, [r1, #276] @ 0x114 │ │ + ldc2l 7, cr15, [r1, #456] @ 0x1c8 │ │ ldc2l 9, cr6, [r3, #238] @ 0xee @ │ │ - ldc2l 11, cr15, [r1, #404] @ 0x194 @ │ │ + ldc2l 11, cr15, [r1, #584] @ 0x248 @ │ │ ldc2l 13, cr13, [r3, #680] @ 0x2a8 │ │ ldc2l 14, cr6, [r1, #888] @ 0x378 │ │ ldrbeq r8, [sl, #2408] @ 0x968 │ │ - ldc2l 11, cr15, [r1, #116] @ 0x74 @ │ │ + ldc2l 11, cr15, [r1, #296] @ 0x128 @ │ │ ldrbeq r8, [sl, #2384] @ 0x950 │ │ ldc2l 13, cr13, [r3, #360] @ 0x168 │ │ ldc2l 14, cr6, [r1, #568] @ 0x238 │ │ - ldc2l 9, cr15, [r1, #450] @ 0x1c2 @ │ │ + ldc2l 10, cr15, [r1, #56] @ 0x38 @ │ │ ldc2l 9, cr11, [r4, #230] @ 0xe6 @ │ │ ldc2l 11, cr13, [r3, #696] @ 0x2b8 @ │ │ ldc2l 12, cr6, [r1, #904] @ 0x388 │ │ ldrbeq r8, [sl, #1900] @ 0x76c │ │ - ldc2l 9, cr15, [r1, #66] @ 0x42 @ │ │ + ldc2l 9, cr15, [r1, #156] @ 0x9c @ │ │ ldrbeq r8, [sl, #1876] @ 0x754 │ │ ldc2l 11, cr13, [r3, #376] @ 0x178 @ │ │ ldc2l 12, cr6, [r1, #584] @ 0x248 │ │ ldc2l 11, cr7, [r4, #440] @ 0x1b8 @ │ │ ldc2l 10, cr13, [r3, #88] @ 0x58 @ │ │ ldc2l 11, cr6, [r1, #296] @ 0x128 @ │ │ ldrbeq r8, [sl, #1492] @ 0x5d4 │ │ - ldc2l 7, cr15, [r1, #548] @ 0x224 │ │ + ldc2l 7, cr15, [r1, #728] @ 0x2d8 │ │ ldrbeq r8, [sl, #1468] @ 0x5bc │ │ ldc2l 9, cr13, [r3, #396] @ 0x18c @ │ │ ldc2l 10, cr6, [r1, #1000] @ 0x3e8 @ │ │ vcadd.f32 d22, d19, d7, #270 │ │ - ldc2l 10, cr15, [r1, #468] @ 0x1d4 @ │ │ + ldc2l 10, cr15, [r1, #648] @ 0x288 @ │ │ ldc2l 12, cr13, [r3, #744] @ 0x2e8 │ │ ldc2l 13, cr6, [r1, #952] @ 0x3b8 │ │ ldrbeq r8, [sl, #2168] @ 0x878 │ │ - ldc2l 10, cr15, [r1, #180] @ 0xb4 @ │ │ + ldc2l 10, cr15, [r1, #360] @ 0x168 @ │ │ ldrbeq r8, [sl, #2144] @ 0x860 │ │ ldc2l 12, cr13, [r3, #424] @ 0x1a8 │ │ ldc2l 13, cr6, [r1, #632] @ 0x278 │ │ vcadd.f32 , q10, , #270 │ │ ldc2l 11, cr13, [r3, #152] @ 0x98 @ │ │ ldc2l 12, cr6, [r1, #360] @ 0x168 │ │ ldrbeq r8, [sl, #1764] @ 0x6e4 │ │ - ldc2l 8, cr15, [r1, #612] @ 0x264 │ │ + vcadd.f32 , , q3, #270 │ │ ldrbeq r8, [sl, #1740] @ 0x6cc │ │ ldc2l 10, cr13, [r3, #856] @ 0x358 @ │ │ ldc2l 12, cr6, [r1, #40] @ 0x28 │ │ ldc2l 9, cr10, [r3, #292] @ 0x124 @ │ │ ldrbeq r8, [sl, #2040] @ 0x7f8 │ │ ldc2l 12, cr13, [r3, #8] │ │ ldc2l 13, cr6, [r1, #216] @ 0xd8 │ │ ldrbeq r8, [sl, #1992] @ 0x7c8 │ │ - ldc2l 9, cr15, [r1, #250] @ 0xfa @ │ │ + ldc2l 9, cr15, [r1, #340] @ 0x154 @ │ │ ldc2l 9, cr11, [r3, #22] @ │ │ - ldc2l 7, cr12, [r2, #376] @ 0x178 │ │ + ldc2l 7, cr12, [r2, #556] @ 0x22c │ │ │ │ 02503a8c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8-d15} │ │ @@ -1517707,15 +1517707,15 @@ │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ mov r2, #3 │ │ ldr sl, [fp, #8] │ │ b 251005c │ │ strdeq r0, [r0], -r4 │ │ ldc2l 3, cr11, [r2, #36] @ 0x24 │ │ - ldc2l 3, cr12, [r1, #132] @ 0x84 │ │ + ldc2l 3, cr12, [r1, #312] @ 0x138 │ │ ldc2l 15, cr3, [pc, #256] @ 2510188 │ │ mov r0, r1 │ │ mov r1, r2 │ │ b 2705a10 │ │ │ │ 02510090 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ @@ -1518775,31 +1518775,31 @@ │ │ ldr r1, [pc, #92] @ 251113c │ │ sub r0, r0, r5 │ │ add r1, pc, r1 │ │ sbfx r0, r0, #2, #16 │ │ ldr r4, [r1, r0, lsl #2] │ │ mov r0, r4 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2l 12, cr0, [r2, #940] @ 0x3ac │ │ + ldc2l 13, cr0, [r2, #96] @ 0x60 │ │ strdeq r9, [r1], -r8 @ │ │ ldc2l 4, cr10, [r3, #260] @ 0x104 │ │ ldrdeq r9, [r1], -r4 @ │ │ - ldc2l 13, cr6, [r2, #908] @ 0x38c │ │ - ldc2l 14, cr10, [r0, #472] @ 0x1d8 │ │ + ldc2l 14, cr6, [r2, #64] @ 0x40 │ │ + ldc2l 14, cr10, [r0, #652] @ 0x28c │ │ ldc2l 5, cr7, [r0, #884] @ 0x374 │ │ - ldc2l 2, cr9, [r1, #188] @ 0xbc │ │ + ldc2l 2, cr9, [r1, #368] @ 0x170 │ │ ldc2l 2, cr8, [r3, #608] @ 0x260 │ │ - ldc2l 3, cr7, [r1, #220] @ 0xdc │ │ - ldc2l 14, cr12, [r0, #556] @ 0x22c │ │ - ldc2l 11, cr9, [r1, #712] @ 0x2c8 @ │ │ + ldc2l 3, cr7, [r1, #400] @ 0x190 │ │ + ldc2l 14, cr12, [r0, #736] @ 0x2e0 │ │ + ldc2l 11, cr9, [r1, #892] @ 0x37c @ │ │ ldc2l 13, cr8, [r2, #880] @ 0x370 │ │ ldc2l 3, cr12, [r3, #408] @ 0x198 │ │ ldc2l 13, cr8, [r2, #700] @ 0x2bc │ │ - ldc2l 15, cr0, [r1, #276] @ 0x114 │ │ - ldc2l 11, cr0, [r2, #552] @ 0x228 @ │ │ + ldc2l 15, cr0, [r1, #456] @ 0x1c8 │ │ + ldc2l 11, cr0, [r2, #732] @ 0x2dc @ │ │ ldc2l 7, cr2, [r3, #816] @ 0x330 │ │ eoreq r9, r1, r8, asr #18 │ │ │ │ 02511140 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ ldr r1, [pc, #196] @ 2511214 │ │ @@ -1518849,21 +1518849,21 @@ │ │ ldr r1, [pc, #48] @ 2511230 │ │ sub r0, r0, r5 │ │ add r1, pc, r1 │ │ sbfx r0, r0, #2, #16 │ │ ldr r4, [r1, r0, lsl #2] │ │ mov r0, r4 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2l 0, cr6, [r1, #324] @ 0x144 │ │ + ldc2l 0, cr6, [r1, #504] @ 0x1f8 │ │ eoreq r9, r1, r0, lsl r9 │ │ - ldc2l 11, cr6, [r2, #580] @ 0x244 @ │ │ + ldc2l 11, cr6, [r2, #760] @ 0x2f8 @ │ │ eoreq r9, r1, ip, ror #17 │ │ ldc2l 15, cr8, [r3, #252] @ 0xfc │ │ - ldc2l 15, cr14, [r0, #836] @ 0x344 │ │ - ldc2l 14, cr4, [r1, #184] @ 0xb8 │ │ + ldc2l 15, cr14, [r0, #1016] @ 0x3f8 │ │ + ldc2l 14, cr4, [r1, #364] @ 0x16c │ │ eoreq r9, r1, ip, lsl #17 │ │ │ │ 02511234 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #24 │ │ mov r6, r2 │ │ @@ -1519693,19 +1519693,19 @@ │ │ bl 27109b0 │ │ cmp r0, #0 │ │ bne 25119e8 │ │ b 2511e38 │ │ ldc2l 6, cr8, [r2, #760] @ 0x2f8 │ │ ldc2l 4, cr10, [r2, #968] @ 0x3c8 │ │ eoreq r9, r1, r0, lsr #23 │ │ - ldc2l 1, cr4, [r2, #1000] @ 0x3e8 │ │ + ldc2l 2, cr4, [r2, #156] @ 0x9c │ │ eoreq r9, r1, r0, lsr #22 │ │ eoreq r9, r1, ip, lsl #3 │ │ eoreq sl, r1, r4, lsl #11 │ │ - ldc2l 4, cr0, [r1, #724] @ 0x2d4 │ │ + ldc2l 4, cr0, [r1, #904] @ 0x388 │ │ eoreq sl, r1, r4, lsl #9 │ │ eoreq sl, r1, r4, asr r0 │ │ │ │ 02511f30 : │ │ b 27111c0 │ │ ldrb r2, [r0] │ │ mov r1, r0 │ │ @@ -1519918,16 +1519918,16 @@ │ │ bne 2512220 │ │ sub r5, r5, r7 │ │ b 251219c │ │ mov r0, #1 │ │ str r0, [r9] │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2l 13, cr1, [r2, #944] @ 0x3b0 │ │ - ldc2l 12, cr1, [r2, #752] @ 0x2f0 │ │ + ldc2l 14, cr1, [r2, #100] @ 0x64 │ │ + ldc2l 12, cr1, [r2, #932] @ 0x3a4 │ │ │ │ 02512298 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ mov r9, r1 │ │ ldr r1, [r2] │ │ @@ -1520206,15 +1520206,15 @@ │ │ mov r0, r4 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ b 25126ec │ │ mov r0, sp │ │ bl 27105c0 │ │ bl 26ffb60 │ │ - vcadd.f32 d25, d0, d4, #270 │ │ + ldc2l 8, cr9, [r0, #196] @ 0xc4 │ │ │ │ 025126fc : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r6, r2 │ │ mov r5, r1 │ │ @@ -1520267,15 +1520267,15 @@ │ │ pop {r4, r5, r6, r7, fp, pc} │ │ mov r0, sp │ │ bl 2710590 │ │ b 25127d8 │ │ mov r0, r4 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - ldc2l 6, cr9, [r0, #880] @ 0x370 │ │ + ldc2l 7, cr9, [r0, #36] @ 0x24 │ │ │ │ 025127e8 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r0 │ │ ldr r0, [r2] │ │ cmp r0, #0 │ │ @@ -1520305,15 +1520305,15 @@ │ │ mov r0, r4 │ │ ldr r3, [r1, #8] │ │ mov r1, r5 │ │ mov r2, r6 │ │ pop {r4, r5, r6, sl, fp, lr} │ │ bx r3 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2l 6, cr9, [r0, #144] @ 0x90 │ │ + ldc2l 6, cr9, [r0, #324] @ 0x144 │ │ │ │ 02512878 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #40 @ 0x28 │ │ mov r5, r3 │ │ ldr r3, [r3] │ │ @@ -1521052,15 +1521052,15 @@ │ │ bl 27103d0 │ │ sub r0, fp, #144 @ 0x90 │ │ bl 27103d0 │ │ sub r0, fp, #88 @ 0x58 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ ldc2l 0, cr1, [pc, #1000] @ 25137d4 │ │ - ldc2l 0, cr12, [r1, #568] @ 0x238 │ │ + ldc2l 0, cr12, [r1, #748] @ 0x2ec │ │ strhteq r9, [r1], -r4 │ │ │ │ 025133f0 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #24 │ │ mov r4, r3 │ │ @@ -1521311,17 +1521311,17 @@ │ │ pop {r4, r5, r6, sl, fp, pc} │ │ sub r0, fp, #24 │ │ bl 2710590 │ │ b 25137b0 │ │ add r0, sp, #12 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - ldc2l 15, cr12, [r0, #452] @ 0x1c4 │ │ + ldc2l 15, cr12, [r0, #632] @ 0x278 │ │ eoreq r7, r1, r8, lsr #7 │ │ - ldc2l 10, cr0, [r1, #116] @ 0x74 @ │ │ + ldc2l 10, cr0, [r1, #296] @ 0x128 @ │ │ eoreq r7, r1, r8, asr #6 │ │ eoreq r7, r1, ip, asr #25 │ │ │ │ 025137d0 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #80 @ 0x50 │ │ @@ -1521396,15 +1521396,15 @@ │ │ pop {r4, r5, r6, sl, fp, pc} │ │ sub r0, fp, #24 │ │ bl 2710590 │ │ b 25138fc │ │ add r0, sp, #12 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - ldc2l 14, cr12, [r0, #148] @ 0x94 │ │ + ldc2l 14, cr12, [r0, #328] @ 0x148 │ │ eoreq r8, r1, r4, ror r5 │ │ ldc2l 9, cr6, [r0, #260] @ 0x104 @ │ │ eoreq r8, r1, r4, lsl r5 │ │ eoreq r8, r1, r4, lsr r9 │ │ │ │ 0251391c : │ │ push {r4, r5, r6, r7, fp, lr} │ │ @@ -1521518,16 +1521518,16 @@ │ │ b 2513adc │ │ add r0, sp, #68 @ 0x44 │ │ bl 2710590 │ │ b 2513adc │ │ sub r0, fp, #76 @ 0x4c │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - ldc2l 8, cr4, [r1, #868] @ 0x364 │ │ - ldc2l 8, cr4, [r1, #596] @ 0x254 │ │ + ldc2l 9, cr4, [r1, #12] @ │ │ + vcadd.f32 q10, , q1, #270 │ │ │ │ 02513af0 : │ │ b 2711600 │ │ │ │ 02513af4 : │ │ ldr r1, [r1] │ │ cmp r1, #0 │ │ @@ -1525268,15 +1525268,15 @@ │ │ add r1, pc, r1 │ │ bl 2713760 │ │ mov ip, #0 │ │ mov r4, #10 │ │ b 25171f8 │ │ ldc2l 2, cr11, [r3, #736] @ 0x2e0 │ │ ldc2l 15, cr12, [lr, #228] @ 0xe4 │ │ - ldc2l 15, cr8, [r0, #292] @ 0x124 │ │ + ldc2l 15, cr8, [r0, #472] @ 0x1d8 │ │ │ │ 025172ac : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ ldr r5, [fp, #8] │ │ mov r4, #0 │ │ cmp r5, #0 │ │ @@ -1525332,15 +1525332,15 @@ │ │ pop {r4, r5, r6, r7, fp, pc} │ │ mov r0, r3 │ │ mov r4, r2 │ │ bl 26fe39c │ │ mov r0, r4 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ ldc2l 1, cr11, [r3, #832] @ 0x340 │ │ - ldc2l 12, cr8, [r1, #584] @ 0x248 │ │ + ldc2l 12, cr8, [r1, #764] @ 0x2fc │ │ │ │ 025173a4 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ ldr r9, [fp, #8] │ │ mov ip, #0 │ │ cmp r9, #0 │ │ @@ -1525396,15 +1525396,15 @@ │ │ mov r6, #10 │ │ b 25173e0 │ │ mov ip, r2 │ │ mov r0, ip │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ ldc2l 11, cr12, [lr, #296] @ 0x128 @ │ │ ldc2l 0, cr11, [r3, #816] @ 0x330 │ │ - ldc2l 9, cr6, [r1, #158] @ 0x9e @ │ │ + ldc2l 9, cr6, [r1, #248] @ 0xf8 @ │ │ │ │ 0251749c : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ ldr r5, [fp, #8] │ │ mov r4, #0 │ │ cmp r5, #0 │ │ @@ -1525464,15 +1525464,15 @@ │ │ mov r0, r3 │ │ mov r4, r2 │ │ bl 26fe39c │ │ mov r0, r4 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ ldc2l 10, cr12, [lr, #344] @ 0x158 @ │ │ ldc2l 15, cr10, [r3, #864] @ 0x360 │ │ - ldc2l 11, cr14, [r0, #144] @ 0x90 @ │ │ + ldc2l 11, cr14, [r0, #324] @ 0x144 @ │ │ │ │ 025175a4 : │ │ cmp r0, #0 │ │ moveq r0, #0 │ │ bxeq lr │ │ push {fp, lr} │ │ mov fp, sp │ │ @@ -1526014,15 +1526014,15 @@ │ │ ldr r8, [sp, #16] │ │ ldr r6, [r0, #36] @ 0x24 │ │ add r3, r8, r3 │ │ str r7, [sp] │ │ blx r6 │ │ b 2517c14 │ │ ldc2l 7, cr5, [r3, #704] @ 0x2c0 │ │ - ldc2l 3, cr8, [r1, #508] @ 0x1fc │ │ + ldc2l 3, cr8, [r1, #688] @ 0x2b0 │ │ │ │ 02517dd4 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ ldr r7, [fp, #8] │ │ mov ip, r0 │ │ mov r0, #0 │ │ @@ -1527884,16 +1527884,16 @@ │ │ b 25199b0 │ │ add r0, sp, #20 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ blx 207deaa │ │ ldrbeq r2, [r9, #2184] @ 0x888 │ │ ldrbeq r2, [r9, #2152] @ 0x868 │ │ - ldc2l 12, cr8, [r0, #420] @ 0x1a4 │ │ - ldc2l 14, cr12, [r1, #460] @ 0x1cc │ │ + ldc2l 12, cr8, [r0, #600] @ 0x258 │ │ + ldc2l 14, cr12, [r1, #640] @ 0x280 │ │ ldc2l 4, cr7, [r3, #928] @ 0x3a0 │ │ ldrbeq r2, [r9, #1116] @ 0x45c │ │ ldrbeq r2, [r9, #1092] @ 0x444 │ │ ldrbeq r2, [r9, #908] @ 0x38c │ │ │ │ 02519a58 : │ │ push {fp, lr} │ │ @@ -1529639,17 +1529639,17 @@ │ │ ldr r2, [sp, #136] @ 0x88 │ │ sub r0, fp, #248 @ 0xf8 │ │ mov r1, r4 │ │ mov r3, sl │ │ bl 27112a0 │ │ b 251b550 │ │ andeq r4, r0, r8, lsr #1 │ │ - ldc2l 11, cr11, [r0, #796] @ 0x31c @ │ │ + ldc2l 11, cr11, [r0, #976] @ 0x3d0 @ │ │ vcadd.f32 q11, , q11, #270 │ │ - ldc2l 14, cr1, [r1, #824] @ 0x338 │ │ + ldc2l 14, cr1, [r1, #1004] @ 0x3ec │ │ ldc2l 5, cr7, [r2, #176] @ 0xb0 │ │ add r1, sp, #136 @ 0x88 │ │ mov r0, r9 │ │ mov r2, sl │ │ bl 251e270 │ │ cmp r0, #0 │ │ beq 251b55c │ │ @@ -1529672,17 +1529672,17 @@ │ │ ldr r1, [r0, #4] │ │ mov r0, r8 │ │ blx r1 │ │ sub r0, fp, #248 @ 0xf8 │ │ bl 2711190 │ │ mov r7, #0 │ │ b 251b714 │ │ - ldc2l 11, cr7, [r0, #812] @ 0x32c @ │ │ - ldc2l 13, cr13, [r0, #864] @ 0x360 │ │ - ldc2l 12, cr5, [r0, #296] @ 0x128 │ │ + ldc2l 11, cr7, [r0, #992] @ 0x3e0 @ │ │ + ldc2l 14, cr13, [r0, #20] │ │ + ldc2l 12, cr5, [r0, #476] @ 0x1dc │ │ mov r8, #0 │ │ str r6, [sp, #76] @ 0x4c │ │ ldr r0, [sp, #64] @ 0x40 │ │ mov r4, #0 │ │ bl 2713e40 │ │ mov r9, r0 │ │ cmp r0, #1 │ │ @@ -1529780,15 +1529780,15 @@ │ │ str r0, [sp, #52] @ 0x34 │ │ mov r2, #0 │ │ mov r4, #0 │ │ str r1, [sp, #24] │ │ mov r3, #0 │ │ str r1, [sp, #48] @ 0x30 │ │ b 251b858 │ │ - ldc2l 10, cr7, [r0, #132] @ 0x84 @ │ │ + ldc2l 10, cr7, [r0, #312] @ 0x138 @ │ │ mov r0, #7 │ │ str r0, [sl] │ │ mov r0, r8 │ │ bl 2713810 │ │ ldr r0, [sp, #32] │ │ bl 2713810 │ │ ldr r0, [sp, #20] │ │ @@ -1529952,15 +1529952,15 @@ │ │ mov r0, #0 │ │ str r1, [sp, #24] │ │ mov r3, #0 │ │ str r1, [sp, #48] @ 0x30 │ │ ldr r6, [sp, #76] @ 0x4c │ │ ldr r1, [sp, #40] @ 0x28 │ │ b 251bb6c │ │ - ldc2l 12, cr5, [r0, #292] @ 0x124 │ │ + ldc2l 12, cr5, [r0, #472] @ 0x1d8 │ │ cmp r5, #0 │ │ beq 251ba0c │ │ mov r0, r5 │ │ bl 2713e90 │ │ ldr r0, [sl] │ │ mov r1, #0 │ │ str r1, [sp, #24] │ │ @@ -1530071,15 +1530071,15 @@ │ │ blx 207deaa │ │ blx 207deaa │ │ blx 207deaa │ │ b 251bbc8 │ │ add r0, sp, #272 @ 0x110 │ │ bl 2710d40 │ │ b 251bbd8 │ │ - ldc2l 5, cr7, [r0, #564] @ 0x234 │ │ + ldc2l 5, cr7, [r0, #744] @ 0x2e8 │ │ ldr r9, [sp, #60] @ 0x3c │ │ ldr r8, [sp, #48] @ 0x30 │ │ b 251bdb4 │ │ b 251bdb4 │ │ blx 207deaa │ │ blx 207deaa │ │ b 251bbfc │ │ @@ -1530287,28 +1530287,28 @@ │ │ add r0, sp, #272 @ 0x110 │ │ bl 27103d0 │ │ b 251bf28 │ │ str r6, [sp, #76] @ 0x4c │ │ ldr r0, [sp, #76] @ 0x4c │ │ bl 2713ef0 │ │ bl 26ffb60 │ │ - ldc2l 11, cr6, [r0, #292] @ 0x124 @ │ │ - vcadd.f32 d22, d16, d1, #270 │ │ - ldc2l 6, cr6, [r0, #820] @ 0x334 │ │ + ldc2l 11, cr6, [r0, #472] @ 0x1d8 @ │ │ + vcadd.f32 d22, d16, d30, #270 │ │ + ldc2l 6, cr6, [r0, #1000] @ 0x3e8 │ │ mlaeq r2, r4, r6, r0 │ │ mlaeq r2, r8, r6, r0 │ │ strdeq r0, [r2], -r8 @ │ │ strdeq r0, [r2], -ip @ │ │ eoreq r0, r2, ip, asr r5 │ │ eoreq r0, r2, r0, ror #10 │ │ eoreq r0, r2, r0, asr #9 │ │ eoreq r0, r2, r4, asr #9 │ │ eoreq r0, r2, ip, lsr #8 │ │ eoreq r0, r2, r0, lsr r4 │ │ - ldc2l 13, cr14, [r0, #832] @ 0x340 │ │ + ldc2l 13, cr14, [r0, #1012] @ 0x3f4 │ │ stc2l 13, cr10, [pc, #344] @ 251c0cc │ │ ldc2l 7, cr3, [r3, #768] @ 0x300 │ │ │ │ 0251bf74 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ @@ -1530633,15 +1530633,15 @@ │ │ bl 2711210 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ blx 207deaa │ │ mov r0, r4 │ │ bl 2711190 │ │ bl 26ffb60 │ │ - ldc2l 2, cr4, [r0, #724] @ 0x2d4 │ │ + ldc2l 2, cr4, [r0, #904] @ 0x388 │ │ ldrbeq pc, [r8, #2456] @ 0x998 @ │ │ ldrbeq pc, [r8, #2424] @ 0x978 @ │ │ │ │ 0251c458 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #8 │ │ @@ -1530660,15 +1530660,15 @@ │ │ mov r2, #1 │ │ bl 2711180 │ │ sub sp, fp, #8 │ │ pop {r4, r5, fp, pc} │ │ mov r0, r4 │ │ bl 2711190 │ │ bl 26ffb60 │ │ - ldc2l 2, cr4, [r0, #4] │ │ + ldc2l 2, cr4, [r0, #184] @ 0xb8 │ │ │ │ 0251c4b4 : │ │ ldr r0, [r0, #32] │ │ b 2713c80 │ │ │ │ 0251c4bc : │ │ ldr r0, [r0, #32] │ │ @@ -1531330,50 +1531330,50 @@ │ │ mov r0, r5 │ │ bl 2713dd0 │ │ bl 26ffb60 │ │ ldrbeq pc, [r8, #1524] @ 0x5f4 @ │ │ ldrbeq pc, [r8, #1500] @ 0x5dc @ │ │ ldrbeq pc, [r8, #1172] @ 0x494 @ │ │ @ instruction: 0xffffca8c │ │ - ldc2l 13, cr3, [r0, #388] @ 0x184 │ │ + ldc2l 13, cr3, [r0, #568] @ 0x238 │ │ ldrbeq pc, [r8, #1108] @ 0x454 @ │ │ - ldc2l 14, cr9, [r1, #220] @ 0xdc │ │ + ldc2l 14, cr9, [r1, #400] @ 0x190 │ │ ldrbeq pc, [r8, #1044] @ 0x414 @ │ │ stc2l 3, cr7, [pc, #920] @ 251d1e8 │ │ ldrbeq pc, [r8, #988] @ 0x3dc @ │ │ - ldc2l 7, cr13, [r0, #888] @ 0x378 │ │ + vcadd.f32 d29, d0, d11, #270 │ │ ldrbeq pc, [r8, #924] @ 0x39c @ │ │ - ldc2l 4, cr1, [r0, #376] @ 0x178 │ │ + ldc2l 4, cr1, [r0, #556] @ 0x22c │ │ ldrbeq pc, [r8, #860] @ 0x35c @ │ │ ldc2l 3, cr4, [r3, #416] @ 0x1a0 │ │ ldrbeq pc, [r8, #796] @ 0x31c @ │ │ ldc2l 7, cr12, [r2, #668] @ 0x29c │ │ ldrbeq pc, [r8, #736] @ 0x2e0 @ │ │ ldc2l 7, cr12, [r2, #284] @ 0x11c │ │ ldrbeq pc, [r8, #672] @ 0x2a0 @ │ │ stc2l 3, cr10, [pc, #696] @ 251d138 │ │ stc2l 2, cr7, [pc, #376] @ 251cffc │ │ ldrbeq pc, [r8, #600] @ 0x258 @ │ │ - ldc2l 6, cr3, [r0, #120] @ 0x78 │ │ + ldc2l 6, cr3, [r0, #300] @ 0x12c │ │ ldrbeq pc, [r8, #536] @ 0x218 @ │ │ ldc2l 6, cr12, [r2, #828] @ 0x33c │ │ ldrbeq pc, [r8, #476] @ 0x1dc @ │ │ ldc2l 0, cr15, [r1, #636] @ 0x27c │ │ ldrbeq pc, [r8, #412] @ 0x19c @ │ │ - ldc2l 14, cr8, [r1, #800] @ 0x320 │ │ + ldc2l 14, cr8, [r1, #980] @ 0x3d4 │ │ ldc2l 6, cr12, [r2, #92] @ 0x5c │ │ ldrbeq pc, [r8, #344] @ 0x158 @ │ │ - ldc2l 7, cr15, [r0, #552] @ 0x228 │ │ + ldc2l 7, cr15, [r0, #732] @ 0x2dc │ │ ldrbeq pc, [r8, #280] @ 0x118 @ │ │ - ldc2l 5, cr13, [r0, #400] @ 0x190 │ │ + ldc2l 5, cr13, [r0, #580] @ 0x244 │ │ ldrbeq pc, [r8, #220] @ 0xdc @ │ │ - ldc2l 1, cr1, [r0, #408] @ 0x198 │ │ - ldc2l 10, cr9, [r1, #716] @ 0x2cc @ │ │ + ldc2l 1, cr1, [r0, #588] @ 0x24c │ │ + ldc2l 10, cr9, [r1, #896] @ 0x380 @ │ │ ldrbeq pc, [r8, #148] @ 0x94 @ │ │ - ldc2l 0, cr11, [r1, #420] @ 0x1a4 │ │ + ldc2l 0, cr11, [r1, #600] @ 0x258 │ │ ldrbeq pc, [r8, #84] @ 0x54 @ │ │ ldc2l 7, cr5, [r2, #328] @ 0x148 │ │ ldrbeq pc, [r8, #16] @ │ │ ldrbeq lr, [r8, #4056] @ 0xfd8 │ │ ldrbeq lr, [r8, #4068] @ 0xfe4 │ │ ldrbeq lr, [r8, #4008] @ 0xfa8 │ │ ldrbeq lr, [r8, #3984] @ 0xf90 │ │ @@ -1532434,16 +1532434,16 @@ │ │ mov r1, r6 │ │ bl 2713f70 │ │ b 251debc │ │ mov r0, #0 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ mov r0, #1 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - stc2l 0, cr14, [pc, #360] @ 251e078 │ │ - stc2l 0, cr14, [pc, #212] @ 251dfe8 │ │ + stc2l 0, cr14, [pc, #540] @ 251e12c │ │ + stc2l 0, cr14, [pc, #392] @ 251e09c │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #332 @ 0x14c │ │ mov r9, r0 │ │ ldr r0, [r2] │ │ mov r8, r1 │ │ cmp r0, #0 │ │ @@ -1532606,15 +1532606,15 @@ │ │ add r0, sp, #20 │ │ bl 2711190 │ │ b 251e1a8 │ │ sub r0, fp, #120 @ 0x78 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ andeq r0, r0, r8, asr #12 │ │ - stc2l 13, cr13, [pc, #560] @ 251e3f0 │ │ + stc2l 13, cr13, [pc, #740] @ 251e4a4 │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ ldr r8, [fp, #8] │ │ mov r6, #0 │ │ ldr r2, [r8] │ │ cmp r2, #0 │ │ ble 251e1e0 │ │ @@ -1533920,20 +1533920,20 @@ │ │ bl 2702a20 │ │ ldr r0, [pc, #44] @ 251f4f4 │ │ add r0, pc, r0 │ │ str r6, [r0] │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldrbeq ip, [r8, #2448] @ 0x990 │ │ ldc2l 11, cr15, [r2, #948] @ 0x3b4 @ │ │ - stc2l 10, cr12, [pc, #676] @ 251f784 @ │ │ - vcadd.f32 q9, , , #270 │ │ + stc2l 10, cr12, [pc, #856] @ 251f838 @ │ │ + vcadd.f32 q9, , q15, #270 │ │ andeq r0, r0, r8, ror r0 │ │ ldrbeq ip, [r8, #2360] @ 0x938 │ │ - ldc2l 15, cr8, [r0, #64] @ 0x40 │ │ - ldc2l 7, cr2, [r1, #980] @ 0x3d4 │ │ + ldc2l 15, cr8, [r0, #244] @ 0xf4 │ │ + vcadd.f32 d18, d1, d18, #270 │ │ ldrbeq ip, [r8, #2308] @ 0x904 │ │ ldrbeq ip, [r8, #2380] @ 0x94c │ │ mov r1, r2 │ │ b 270ae50 │ │ │ │ 0251f500 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ @@ -1534134,28 +1534134,28 @@ │ │ ldr r1, [pc, #116] @ 251f888 │ │ ldr r1, [pc, r1] │ │ ldr r5, [r1, r0, lsl #2] │ │ mov r0, r5 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldrbeq ip, [r8, #2208] @ 0x8a0 │ │ - ldc2l 8, cr8, [r1, #492] @ 0x1ec │ │ + vcadd.f32 d24, d17, d24, #270 │ │ stc2l 0, cr9, [pc, #460] @ 251fa00 │ │ ldrbeq ip, [r8, #2188] @ 0x88c │ │ ldc2l 12, cr5, [r2, #508] @ 0x1fc │ │ ldrbeq ip, [r8, #2168] @ 0x878 │ │ ldc2l 12, cr5, [r2, #380] @ 0x17c │ │ ldrbeq ip, [r8, #2136] @ 0x858 │ │ ldrbeq ip, [r8, #2112] @ 0x840 │ │ - ldc2l 3, cr4, [r1, #248] @ 0xf8 │ │ + ldc2l 3, cr4, [r1, #428] @ 0x1ac │ │ vcadd.f32 d26, d17, d18, #270 │ │ ldc2l 12, cr5, [r2, #28] │ │ ldrbeq ip, [r8, #2048] @ 0x800 │ │ - ldc2l 2, cr4, [r1, #888] @ 0x378 │ │ - ldc2l 7, cr8, [r1, #396] @ 0x18c │ │ + ldc2l 3, cr4, [r1, #44] @ 0x2c │ │ + ldc2l 7, cr8, [r1, #576] @ 0x240 │ │ stc2l 15, cr8, [pc, #364] @ 251f9d4 │ │ ldrbeq ip, [r8, #1744] @ 0x6d0 │ │ stc2l 10, cr6, [pc, #984] @ 251fc48 @ │ │ ldrbeq ip, [r8, #1848] @ 0x738 │ │ ldrbeq ip, [r8, #1800] @ 0x708 │ │ ldc2l 11, cr4, [lr, #704] @ 0x2c0 @ │ │ ldc2l 11, cr4, [lr, #656] @ 0x290 @ │ │ @@ -1534217,17 +1534217,17 @@ │ │ add r1, pc, r1 │ │ bl 2705a10 │ │ clz r0, r0 │ │ lsr r5, r0, #5 │ │ mov r0, r5 │ │ pop {r4, r5, fp, pc} │ │ ldc2l 5, cr1, [r3, #144] @ 0x90 │ │ - ldc2l 8, cr4, [r0, #712] @ 0x2c8 │ │ + ldc2l 8, cr4, [r0, #892] @ 0x37c │ │ ldc2l 4, cr1, [r3, #1008] @ 0x3f0 │ │ - vcadd.f32 d18, d0, d25, #270 │ │ + ldc2l 8, cr2, [r0, #344] @ 0x158 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #660 @ 0x294 │ │ add r5, sp, #84 @ 0x54 │ │ mov r4, r0 │ │ mov r6, #0 │ │ mov r7, r1 │ │ @@ -1534531,22 +1534531,22 @@ │ │ add r0, sp, #84 @ 0x54 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ ldrbeq sp, [r8, #1088] @ 0x440 │ │ ldrbeq sp, [r8, #68] @ 0x44 │ │ ldrbeq sp, [r8, #1036] @ 0x40c │ │ strdeq r0, [r0], -r0 @ │ │ - ldc2l 6, cr1, [r0, #768] @ 0x300 │ │ - ldc2l 5, cr15, [r0, #204] @ 0xcc │ │ + ldc2l 6, cr1, [r0, #948] @ 0x3b4 │ │ + ldc2l 5, cr15, [r0, #384] @ 0x180 │ │ ldc2l 3, cr10, [r1, #808] @ 0x328 │ │ ldc2l 9, cr13, [r2, #250] @ 0xfa @ │ │ ldc2l 6, cr5, [r2, #364] @ 0x16c │ │ ldc2l 15, cr14, [r1, #716] @ 0x2cc │ │ ldc2l 15, cr14, [r1, #636] @ 0x27c │ │ - ldc2l 0, cr8, [r1, #428] @ 0x1ac │ │ + ldc2l 0, cr8, [r1, #608] @ 0x260 │ │ vcadd.f16 q12, , , #270 │ │ ldrbeq sp, [r8, #148] @ 0x94 │ │ ldrbeq sp, [r8, #100] @ 0x64 │ │ │ │ 0251fe88 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ @@ -1534578,15 +1534578,15 @@ │ │ cmp r0, #0 │ │ beq 251ff0c │ │ mov r1, r5 │ │ mov r4, r0 │ │ bl 270ae50 │ │ b 251fea8 │ │ pop {r4, r5, fp, pc} │ │ - ldc2l 7, cr0, [r0, #868] @ 0x364 │ │ + vcadd.f32 d16, d0, d6, #270 │ │ ldrbeq ip, [r8, #3952] @ 0xf70 │ │ ldrbeq ip, [r8, #3920] @ 0xf50 │ │ andeq r0, r0, r8, asr #32 │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ ldr r0, [pc, #236] @ 252001c │ │ ldr r0, [pc, r0] │ │ @@ -1534728,15 +1534728,15 @@ │ │ ldr r0, [pc, #40] @ 252016c │ │ ldr r0, [pc, r0] │ │ pop {r4, r5, fp, pc} │ │ ldrbeq ip, [r8, #3520] @ 0xdc0 │ │ ldrbeq ip, [r8, #3496] @ 0xda8 │ │ ldrbeq ip, [r8, #3456] @ 0xd80 │ │ ldc2l 3, cr11, [r2, #332] @ 0x14c │ │ - ldc2l 5, cr0, [r0, #724] @ 0x2d4 │ │ + ldc2l 5, cr0, [r0, #904] @ 0x388 │ │ ldrbeq ip, [r8, #3360] @ 0xd20 │ │ ldrbeq ip, [r8, #3328] @ 0xd00 │ │ @ instruction: 0xfffffdf8 │ │ ldrbeq ip, [r8, #3324] @ 0xcfc │ │ ldrbeq ip, [r8, #3292] @ 0xcdc │ │ │ │ 02520170 : │ │ @@ -1534780,15 +1534780,15 @@ │ │ ldr r1, [r4] │ │ cmp r1, #0 │ │ bgt 2520190 │ │ ldr r0, [pc, #20] @ 252022c │ │ ldr r0, [pc, r0] │ │ ldr r0, [r0] │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2l 4, cr0, [r0, #964] @ 0x3c4 │ │ + ldc2l 5, cr0, [r0, #120] @ 0x78 │ │ eoreq fp, r1, r0, lsr r4 │ │ eoreq fp, r1, r4, lsl r4 │ │ ldrbeq ip, [r8, #3084] @ 0xc0c │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ ldr r1, [pc, #200] @ 252030c │ │ @@ -1534841,16 +1534841,16 @@ │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ mov r0, r5 │ │ bl 2713d70 │ │ bl 26ffb60 │ │ @ instruction: 0xfffffcd0 │ │ ldrbeq ip, [r8, #2984] @ 0xba8 │ │ - stc2l 12, cr13, [pc, #808] @ 2520644 │ │ - ldc2l 3, cr0, [r0, #644] @ 0x284 │ │ + stc2l 12, cr13, [pc, #988] @ 25206f8 │ │ + ldc2l 3, cr0, [r0, #824] @ 0x338 │ │ ldrbeq ip, [r8, #2924] @ 0xb6c │ │ │ │ 02520320 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r5, r0 │ │ @@ -1535086,27 +1535086,27 @@ │ │ bl 27134a0 │ │ ldr r0, [pc, #84] @ 252071c │ │ ldr r0, [pc, r0] │ │ pop {r4, r5, r6, r7, fp, pc} │ │ ldrbeq ip, [r8, #2604] @ 0xa2c │ │ ldc2l 12, cr11, [r1, #48] @ 0x30 │ │ ldc2l 0, cr12, [r2, #580] @ 0x244 │ │ - ldc2l 3, cr4, [r1, #576] @ 0x240 │ │ - ldc2l 9, cr14, [r0, #316] @ 0x13c @ │ │ - ldc2l 9, cr14, [r0, #214] @ 0xd6 @ │ │ + ldc2l 3, cr4, [r1, #756] @ 0x2f4 │ │ + ldc2l 9, cr14, [r0, #406] @ 0x196 @ │ │ + ldc2l 9, cr14, [r0, #304] @ 0x130 @ │ │ ldc2l 11, cr11, [r1, #592] @ 0x250 @ │ │ ldc2l 0, cr12, [r2, #100] @ 0x64 │ │ ldc2l 6, cr1, [r3, #304] @ 0x130 │ │ ldrbeq ip, [r8, #2388] @ 0x954 │ │ ldrbeq ip, [r8, #2356] @ 0x934 │ │ ldc2l 10, cr11, [r1, #944] @ 0x3b0 @ │ │ ldc2l 15, cr11, [r2, #452] @ 0x1c4 │ │ ldc2l 5, cr1, [r3, #656] @ 0x290 │ │ - ldc2l 10, cr15, [r0, #1016] @ 0x3f8 @ │ │ - stc2l 9, cr13, [pc, #58] @ 252074a @ │ │ + ldc2l 11, cr15, [r0, #172] @ 0xac @ │ │ + stc2l 9, cr13, [pc, #148] @ 25207a4 @ │ │ ldrbeq ip, [r8, #1968] @ 0x7b0 │ │ ldrbeq ip, [r8, #1924] @ 0x784 │ │ ldrbeq ip, [r8, #1916] @ 0x77c │ │ @ instruction: 0xfffff86c │ │ ldrbeq ip, [r8, #1888] @ 0x760 │ │ │ │ 02520720 : │ │ @@ -1535357,15 +1535357,15 @@ │ │ mov r3, #0 │ │ b 2520934 │ │ │ │ 02520ae8 : │ │ ldr r1, [pc, #4] @ 2520af4 │ │ add r1, pc, r1 │ │ b 27120b0 │ │ - ldc2l 14, cr2, [r1, #212] @ 0xd4 │ │ + ldc2l 14, cr2, [r1, #392] @ 0x188 │ │ │ │ 02520af8 : │ │ ldr r0, [r1] │ │ cmp r0, #0 │ │ movle r0, #16 │ │ strle r0, [r1] │ │ mov r0, #0 │ │ @@ -1538241,15 +1538241,15 @@ │ │ b 25234cc │ │ mov r0, #1 │ │ str r0, [r4, #4] │ │ b 25234e4 │ │ mov r0, #1 │ │ str r0, [r4, #4] │ │ b 25234fc │ │ - stc2l 1, cr13, [pc, #436] @ 2523814 │ │ + stc2l 1, cr13, [pc, #616] @ 25238c8 │ │ │ │ 0252365c : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ ldr r5, [r0, #28] │ │ mov r6, #0 │ │ mov r4, r0 │ │ @@ -1538684,15 +1538684,15 @@ │ │ mov r0, r7 │ │ blx r1 │ │ b 2523cfc │ │ add r0, sp, #16 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ ldc2l 4, cr10, [r1, #412] @ 0x19c │ │ - stc2l 10, cr12, [pc, #628] @ 2523f88 @ │ │ + stc2l 10, cr12, [pc, #808] @ 252403c @ │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #288 @ 0x120 │ │ mov r4, r2 │ │ ldr r2, [r2] │ │ cmp r2, #0 │ │ ble 2523d34 │ │ @@ -1538747,15 +1538747,15 @@ │ │ bl 2711190 │ │ b 2523dfc │ │ b 2523dfc │ │ b 2523dfc │ │ sub r0, fp, #84 @ 0x54 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - stc2l 4, cr14, [pc, #368] @ 2523f80 │ │ + stc2l 4, cr14, [pc, #548] @ 2524034 │ │ │ │ 02523e0c : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ mov r7, r0 │ │ mov r4, r3 │ │ @@ -1540014,15 +1540014,15 @@ │ │ sub r0, fp, #88 @ 0x58 │ │ bl 27103d0 │ │ add r0, sp, #36 @ 0x24 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ b 2525168 │ │ ldc2l 11, cr6, [r1, #648] @ 0x288 @ │ │ - stc2l 5, cr11, [pc, #980] @ 2525558 │ │ + stc2l 6, cr11, [pc, #136] @ 252520c │ │ │ │ 02525180 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #24 │ │ mov r5, r3 │ │ ldr r3, [r3] │ │ @@ -1540281,15 +1540281,15 @@ │ │ sub r0, fp, #88 @ 0x58 │ │ bl 27103d0 │ │ add r0, sp, #40 @ 0x28 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ b 252557c │ │ ldc2l 7, cr6, [r1, #552] @ 0x228 │ │ - stc2l 1, cr11, [pc, #884] @ 252590c │ │ + stc2l 2, cr11, [pc, #40] @ 25255c0 │ │ │ │ 02525594 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #192 @ 0xc0 │ │ mov r4, r0 │ │ sub r0, fp, #76 @ 0x4c │ │ @@ -1540507,15 +1540507,15 @@ │ │ b 25258f0 │ │ b 25258f0 │ │ b 25258f0 │ │ mov r0, r4 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ stc2l 9, cr0, [pc, #420] @ 2525aa8 @ │ │ - ldc2l 9, cr4, [r0, #280] @ 0x118 @ │ │ + ldc2l 9, cr4, [r0, #370] @ 0x172 @ │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #56 @ 0x38 │ │ mov r5, r3 │ │ mov r6, r2 │ │ mov r7, r1 │ │ mov r4, r0 │ │ @@ -1540678,18 +1540678,18 @@ │ │ mov r1, r8 │ │ mov r2, sl │ │ ldr r3, [r0, #8] │ │ mov r0, r5 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ bx r3 │ │ - ldc2l 3, cr14, [r0, #880] @ 0x370 │ │ - ldc2l 3, cr14, [r0, #544] @ 0x220 │ │ - ldc2l 3, cr14, [r0, #272] @ 0x110 │ │ - ldc2l 3, cr14, [r0, #160] @ 0xa0 │ │ + ldc2l 4, cr14, [r0, #36] @ 0x24 │ │ + ldc2l 3, cr14, [r0, #724] @ 0x2d4 │ │ + ldc2l 3, cr14, [r0, #452] @ 0x1c4 │ │ + ldc2l 3, cr14, [r0, #340] @ 0x154 │ │ │ │ 02525bbc : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ ldr r1, [r0, #12] │ │ cmp r1, #0 │ │ beq 2525bdc │ │ @@ -1541359,19 +1541359,19 @@ │ │ str r5, [sp, #16] │ │ bl 27116d0 │ │ b 252654c │ │ add r0, sp, #44 @ 0x2c │ │ bl 2710f00 │ │ bl 26ffb60 │ │ blx 207deaa │ │ - stc2l 1, cr10, [pc, #1012] @ 2526a0c │ │ + stc2l 2, cr10, [pc, #168] @ 25266c0 │ │ ldc2l 7, cr5, [r1, #584] @ 0x248 │ │ - stc2l 1, cr10, [pc, #852] @ 2526974 │ │ + stc2l 2, cr10, [pc, #8] @ 2526628 │ │ ldc2l 7, cr5, [r1, #408] @ 0x198 │ │ - stc2l 0, cr10, [pc, #980] @ 25269fc │ │ + stc2l 1, cr10, [pc, #136] @ 25266b0 │ │ │ │ 02526624 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #36 @ 0x24 │ │ ldr sl, [fp, #20] │ │ ldr r7, [sl] │ │ @@ -1541546,23 +1541546,23 @@ │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ mov r1, #7 │ │ str r4, [sp] │ │ stmib sp, {r1, sl} │ │ mov r1, #44 @ 0x2c │ │ b 2526878 │ │ - stc2l 0, cr10, [pc, #164] @ 25269a0 │ │ + stc2l 0, cr10, [pc, #344] @ 2526a54 │ │ ldc2l 5, cr5, [r1, #744] @ 0x2e8 │ │ - stc2l 9, cr15, [pc, #354] @ 2526a66 @ │ │ + stc2l 9, cr15, [pc, #444] @ 2526ac0 @ │ │ ldc2l 3, cr9, [r1, #492] @ 0x1ec │ │ stc2l 14, cr1, [pc, #288] @ 2526a2c │ │ ldc2l 9, cr14, [r1, #484] @ 0x1e4 @ │ │ - stc2l 9, cr15, [pc, #268] @ 2526a20 @ │ │ + stc2l 9, cr15, [pc, #358] @ 2526a7a @ │ │ ldc2l 3, cr9, [r1, #840] @ 0x348 │ │ - stc2l 15, cr9, [pc, #484] @ 2526b00 │ │ + stc2l 15, cr9, [pc, #664] @ 2526bb4 │ │ ldc2l 5, cr5, [r1, #56] @ 0x38 │ │ │ │ 0252691c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #28 │ │ ldr r8, [fp, #16] │ │ @@ -1541603,15 +1541603,15 @@ │ │ str r0, [sp, #16] │ │ mov r0, sl │ │ stm sp, {r4, r6} │ │ str r8, [sp, #20] │ │ bl 2711560 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - stc2l 13, cr9, [pc, #180] @ 2526a8c │ │ + stc2l 13, cr9, [pc, #360] @ 2526b40 │ │ ldc2l 2, cr5, [r1, #760] @ 0x2f8 │ │ │ │ 025269d8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #148 @ 0x94 │ │ ldr r5, [fp, #28] │ │ @@ -1542143,24 +1542143,24 @@ │ │ b 2527228 │ │ b 2527228 │ │ b 2527228 │ │ add r0, sp, #80 @ 0x50 │ │ bl 2710650 │ │ bl 26ffb60 │ │ ldc2l 1, cr5, [r1, #728] @ 0x2d8 │ │ - stc2l 11, cr9, [pc, #980] @ 2527614 @ │ │ + stc2l 12, cr9, [pc, #136] @ 25272c8 │ │ ldc2l 2, cr5, [r1, #184] @ 0xb8 │ │ - stc2l 11, cr9, [pc, #692] @ 25274fc @ │ │ + stc2l 11, cr9, [pc, #872] @ 25275b0 @ │ │ ldc2l 13, cr12, [r1, #856] @ 0x358 │ │ - stc2l 11, cr9, [pc, #404] @ 25273e4 @ │ │ - stc2l 6, cr9, [pc, #84] @ 25272a8 │ │ - stc2l 6, cr9, [pc, #20] @ 252726c │ │ - stc2l 5, cr9, [pc, #980] @ 2527630 │ │ + stc2l 11, cr9, [pc, #584] @ 2527498 @ │ │ + stc2l 6, cr9, [pc, #264] @ 252735c │ │ + stc2l 6, cr9, [pc, #200] @ 2527320 │ │ + stc2l 6, cr9, [pc, #136] @ 25272e4 │ │ ldc2l 11, cr4, [r1, #232] @ 0xe8 @ │ │ - stc2l 12, cr9, [pc, #292] @ 2527388 │ │ + stc2l 12, cr9, [pc, #472] @ 252743c │ │ ldc2l 1, cr5, [r1, #840] @ 0x348 │ │ │ │ 02527264 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #64 @ 0x40 │ │ ldr r0, [r2] │ │ @@ -1542382,15 +1542382,15 @@ │ │ ldr r1, [r0, #8] │ │ mov r0, r8 │ │ bl 2705a10 │ │ cmp r0, #0 │ │ mov r0, r4 │ │ orreq r0, r0, #1 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ - stc2l 1, cr9, [pc, #388] @ 2527760 │ │ + stc2l 1, cr9, [pc, #568] @ 2527814 │ │ │ │ 025275d8 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #16 │ │ mov r6, r1 │ │ ldr r1, [pc, #828] @ 252792c │ │ @@ -1542600,15 +1542600,15 @@ │ │ b 2527920 │ │ b 2527920 │ │ mov r0, sp │ │ bl 2710650 │ │ bl 26ffb60 │ │ ldc2l 6, cr4, [r1, #104] @ 0x68 │ │ ldc2l 6, cr4, [r1, #776] @ 0x308 │ │ - stc2l 0, cr9, [pc, #228] @ 2527a20 │ │ + stc2l 0, cr9, [pc, #408] @ 2527ad4 │ │ │ │ 02527938 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #244 @ 0xf4 │ │ ldr r7, [fp, #28] │ │ mov r4, r0 │ │ @@ -1542885,26 +1542885,26 @@ │ │ b 2527d90 │ │ sub r0, fp, #88 @ 0x58 │ │ bl 2710f00 │ │ sub r0, fp, #60 @ 0x3c │ │ bl 2710f00 │ │ bl 26ffb60 │ │ blx 207deaa │ │ - stc2l 12, cr8, [pc, #644] @ 252802c │ │ + stc2l 12, cr8, [pc, #824] @ 25280e0 │ │ ldc2l 2, cr4, [r1, #168] @ 0xa8 │ │ - stc2l 12, cr8, [pc, #244] @ 2527ea4 │ │ - stc2l 11, cr8, [pc, #724] @ 2528088 @ │ │ - stc2l 11, cr8, [pc, #628] @ 252802c @ │ │ - stc2l 10, cr8, [pc, #548] @ 2527fe0 @ │ │ - stc2l 10, cr8, [pc, #100] @ 2527e24 @ │ │ - stc2l 10, cr8, [pc, #628] @ 2528038 @ │ │ - stc2l 9, cr8, [pc, #378] @ 2527f42 @ │ │ - stc2l 9, cr8, [pc, #170] @ 2527e76 @ │ │ + stc2l 12, cr8, [pc, #424] @ 2527f58 │ │ + stc2l 11, cr8, [pc, #904] @ 252813c @ │ │ + stc2l 11, cr8, [pc, #808] @ 25280e0 @ │ │ + stc2l 10, cr8, [pc, #728] @ 2528094 @ │ │ + stc2l 10, cr8, [pc, #280] @ 2527ed8 @ │ │ + stc2l 10, cr8, [pc, #808] @ 25280ec @ │ │ + stc2l 9, cr8, [pc, #468] @ 2527f9c @ │ │ + stc2l 9, cr8, [pc, #260] @ 2527ed0 @ │ │ ldc2l 1, cr4, [r1, #552] @ 0x228 │ │ - stc2l 13, cr8, [pc, #68] @ 2527e18 │ │ + stc2l 13, cr8, [pc, #248] @ 2527ecc │ │ ldc2l 2, cr4, [r1, #616] @ 0x268 │ │ │ │ 02527dd4 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #276 @ 0x114 │ │ mov r4, r0 │ │ @@ -1543528,35 +1543528,35 @@ │ │ blx 207deaa │ │ b 2528790 │ │ add r0, sp, #140 @ 0x8c │ │ bl 27141d0 │ │ sub r0, fp, #144 @ 0x90 │ │ bl 27141e0 │ │ bl 26ffb60 │ │ - stc2l 3, cr10, [pc, #668] @ 2528a48 &, int&, UErrorCode&)@@Base+0x20> │ │ + stc2l 3, cr10, [pc, #848] @ 2528afc &, int&, UErrorCode&)@@Base+0xd4> │ │ ldc2l 13, cr7, [r1, #564] @ 0x234 │ │ eoreq r3, r1, r8, ror #16 │ │ stc2l 3, cr14, [lr, #296] @ 0x128 │ │ - ldc2l 3, cr2, [r0, #260] @ 0x104 │ │ + ldc2l 3, cr2, [r0, #440] @ 0x1b8 │ │ ldc2l 5, cr5, [r2, #332] @ 0x14c │ │ stc2l 6, cr0, [pc, #684] @ 2528a70 &, int&, UErrorCode&)@@Base+0x48> │ │ - stc2l 15, cr5, [pc, #500] @ 25289bc &, int&, UErrorCode&)@@Base+0xf8> │ │ - ldc2l 12, cr9, [r0, #768] @ 0x300 │ │ - stc2l 11, cr5, [pc, #324] @ 2528914 &, int&, UErrorCode&)@@Base+0x50> @ │ │ + stc2l 15, cr5, [pc, #680] @ 2528a70 &, int&, UErrorCode&)@@Base+0x48> │ │ + ldc2l 12, cr9, [r0, #948] @ 0x3b4 │ │ + stc2l 11, cr5, [pc, #504] @ 25289c8 &, int&, UErrorCode&)@@Base+0x104> @ │ │ stc2l 9, cr11, [lr, #486] @ 0x1e6 @ │ │ - stc2l 12, cr13, [pc, #808] @ 2528b00 &, int&, UErrorCode&)@@Base+0xd8> │ │ + stc2l 12, cr13, [pc, #988] @ 2528bb4 &, int&, UErrorCode&)@@Base+0x18c> │ │ vcadd.f32 d19, d1, d11, #270 │ │ ldc2l 11, cr12, [r1, #612] @ 0x264 @ │ │ eoreq r3, r1, r0, ror #11 │ │ eoreq r3, r1, r4, ror #11 │ │ eoreq r3, r1, r4, lsr r5 │ │ eoreq r3, r1, r8, lsr r5 │ │ - stc2l 4, cr8, [pc, #196] @ 25288b8 │ │ + stc2l 4, cr8, [pc, #376] @ 252896c &, int&, UErrorCode&)@@Base+0xa8> │ │ ldc2l 9, cr3, [r1, #396] @ 0x18c @ │ │ - stc2l 0, cr8, [pc, #948] @ 2528bb0 &, int&, UErrorCode&)@@Base+0x188> │ │ + stc2l 1, cr8, [pc, #104] @ 2528864 │ │ ldc2l 6, cr3, [r1, #520] @ 0x208 │ │ │ │ 025287fc : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ ldr r0, [r0] │ │ @@ -1544551,15 +1544551,15 @@ │ │ mov r3, #0 │ │ str r3, [r1, #24] │ │ add r2, pc, r2 │ │ str r3, [r1, #12] │ │ str r2, [r1] │ │ str r2, [r1, #4] │ │ pop {r4, r5, fp, pc} │ │ - stc2l 15, cr6, [pc, #324] @ 2529884 │ │ + stc2l 15, cr6, [pc, #504] @ 2529938 │ │ │ │ 0252973c : │ │ ldr r0, [r0, #12] │ │ b 2710990 │ │ │ │ 02529744 : │ │ push {r4, r5, fp, lr} │ │ @@ -1544589,15 +1544589,15 @@ │ │ add r0, pc, r0 │ │ str r1, [r5, #12] │ │ str r0, [r5] │ │ str r0, [r5, #4] │ │ mov r0, r4 │ │ pop {r4, r5, fp, pc} │ │ blx 207deaa │ │ - stc2l 14, cr6, [pc, #836] @ 2529b0c │ │ + stc2l 14, cr6, [pc, #1016] @ 2529bc0 │ │ │ │ 025297c4 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r1 │ │ mov r4, r0 │ │ ldr r1, [r1] │ │ @@ -1548112,23 +1548112,23 @@ │ │ ldrbeq r0, [r8, #3672] @ 0xe58 │ │ ldrbeq r0, [r8, #3632] @ 0xe30 │ │ strhteq pc, [r0], -ip @ │ │ ldrbeq r0, [r8, #3324] @ 0xcfc │ │ ldc2l 6, cr7, [r1, #864] @ 0x360 │ │ eoreq pc, r0, r0, lsr #8 │ │ eoreq pc, r0, r4, lsr #8 │ │ - ldc2l 1, cr0, [r0, #412] @ 0x19c │ │ - stc2l 14, cr5, [pc, #172] @ 252ce24 │ │ - stc2l 14, cr5, [pc, #128] @ 252cdfc │ │ + ldc2l 1, cr0, [r0, #592] @ 0x250 │ │ + stc2l 14, cr5, [pc, #352] @ 252ced8 │ │ + stc2l 14, cr5, [pc, #308] @ 252ceb0 │ │ ldrbeq r0, [r8, #2816] @ 0xb00 │ │ ldrbeq r0, [r8, #2316] @ 0x90c │ │ ldrbeq r0, [r8, #2268] @ 0x8dc │ │ ldrbeq r0, [r8, #1944] @ 0x798 │ │ - stc2l 10, cr15, [pc, #556] @ 252cfbc @ │ │ - stc2l 11, cr15, [pc, #604] @ 252cff0 @ │ │ + stc2l 10, cr15, [pc, #736] @ 252d070 @ │ │ + stc2l 11, cr15, [pc, #784] @ 252d0a4 @ │ │ ldrbeq r0, [r8, #1216] @ 0x4c0 │ │ ldrbeq r0, [r8, #1132] @ 0x46c │ │ ldrbeq r0, [r8, #1092] @ 0x444 │ │ ldrbeq r0, [r8, #1040] @ 0x410 │ │ │ │ 0252cda0 : │ │ push {r4, r5, fp, lr} │ │ @@ -1553227,17 +1553227,17 @@ │ │ bl 27103d0 │ │ bl 26ffb60 │ │ ldc2l 9, cr14, [sp, #332] @ 0x14c @ │ │ ldc2l 5, cr14, [sp, #952] @ 0x3b8 │ │ ldc2l 3, cr14, [sp, #288] @ 0x120 │ │ ldc2l 3, cr14, [sp, #368] @ 0x170 │ │ ldc2l 11, cr0, [r1, #140] @ 0x8c @ │ │ - vcadd.f32 q8, q0, , #270 │ │ + ldc2l 8, cr0, [r0, #472] @ 0x1d8 │ │ ldc2l 2, cr14, [sp, #664] @ 0x298 │ │ - stc2l 12, cr12, [pc, #464] @ 2531e70 │ │ + stc2l 12, cr12, [pc, #644] @ 2531f24 │ │ ldc2l 2, cr14, [sp, #268] @ 0x10c │ │ ldc2l 5, cr0, [r1, #60] @ 0x3c │ │ ldc2l 12, cr13, [sp, #908] @ 0x38c │ │ ldc2l 4, cr0, [r1, #812] @ 0x32c │ │ ldc2l 12, cr13, [sp, #692] @ 0x2b4 │ │ ldc2l 4, cr0, [r1, #588] @ 0x24c │ │ │ │ @@ -1555531,16 +1555531,16 @@ │ │ bl 27103d0 │ │ ldr r0, [fp, #8] │ │ ldr r0, [r0] │ │ cmp r0, #1 │ │ blt 2533454 │ │ b 2534210 │ │ ldc2l 4, cr12, [sp, #656] @ 0x290 │ │ - ldc2l 13, cr0, [r0, #640] @ 0x280 │ │ - ldc2l 13, cr0, [r0, #160] @ 0xa0 │ │ + ldc2l 13, cr0, [r0, #820] @ 0x334 │ │ + ldc2l 13, cr0, [r0, #340] @ 0x154 │ │ mov r0, #0 │ │ str r0, [sp, #36] @ 0x24 │ │ str r0, [sp, #48] @ 0x30 │ │ ldr r0, [sp, #56] @ 0x38 │ │ ldr r7, [r0, #36] @ 0x24 │ │ mov r0, r7 │ │ bl 26ffea0 │ │ @@ -1555621,16 +1555621,16 @@ │ │ cmn r0, #1 │ │ bgt 25341a0 │ │ str r5, [r7, #8] │ │ str r4, [r5, #8] │ │ b 2534210 │ │ mov r0, #1 │ │ b 2534208 │ │ - ldc2l 12, cr0, [r0, #192] @ 0xc0 │ │ - ldc2l 11, cr0, [r0, #688] @ 0x2b0 @ │ │ + ldc2l 12, cr0, [r0, #372] @ 0x174 │ │ + ldc2l 11, cr0, [r0, #868] @ 0x364 @ │ │ ldc2l 1, cr12, [sp, #832] @ 0x340 │ │ ldr r0, [sp, #112] @ 0x70 │ │ mov r2, #0 │ │ ldr r1, [sp, #116] @ 0x74 │ │ str r2, [r1, r0, lsl #2] │ │ add r0, r0, #1 │ │ str r0, [sp, #112] @ 0x70 │ │ @@ -1555899,17 +1555899,17 @@ │ │ ldc2l 13, cr11, [sp, #776] @ 0x308 │ │ ldc2l 10, cr11, [sp, #844] @ 0x34c @ │ │ ldc2l 10, cr11, [sp, #80] @ 0x50 @ │ │ ldc2l 9, cr11, [sp, #472] @ 0x1d8 @ │ │ ldc2l 6, cr11, [sp, #460] @ 0x1cc │ │ ldc2l 6, cr11, [sp, #316] @ 0x13c │ │ ldc2l 5, cr11, [sp, #668] @ 0x29c │ │ - stc2l 1, cr11, [pc, #24] @ 2534658 │ │ + stc2l 1, cr11, [pc, #204] @ 253470c │ │ ldc2l 0, cr7, [r0, #356] @ 0x164 │ │ - stc2l 0, cr8, [pc, #404] @ 25347dc │ │ + stc2l 0, cr8, [pc, #584] @ 2534890 │ │ ldc2l 0, cr7, [r0, #20] │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ ldr r5, [r0] │ │ mov r4, r0 │ │ cmp r5, #0 │ │ beq 25346b0 │ │ @@ -1562256,15 +1562256,15 @@ │ │ cmp lr, #0 │ │ bne 253a480 │ │ ldr ip, [pc, #12] @ 253a534 │ │ add ip, pc, ip │ │ mov r0, ip │ │ sub sp, fp, #16 │ │ pop {r4, r5, r7, sl, fp, pc} │ │ - stc2l 1, cr6, [lr, #324] @ 0x144 │ │ + stc2l 1, cr6, [lr, #504] @ 0x1f8 │ │ │ │ 0253a538 : │ │ mov r3, r0 │ │ mov r0, #0 │ │ cmp r2, #0 │ │ bxeq lr │ │ push {r4, sl, fp, lr} │ │ @@ -1563413,16 +1563413,16 @@ │ │ b 253b6a0 │ │ b 253b6a0 │ │ b 253b6a0 │ │ add r0, sp, #68 @ 0x44 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ stc2l 9, cr14, [pc, #92] @ 253b710 @ │ │ - stc2l 1, cr5, [lr, #292] @ 0x124 │ │ - stc2l 11, cr3, [lr, #484] @ 0x1e4 @ │ │ + stc2l 1, cr5, [lr, #472] @ 0x1d8 │ │ + stc2l 11, cr3, [lr, #664] @ 0x298 @ │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ ldr r9, [fp, #12] │ │ mov r4, r0 │ │ ldr r8, [fp, #16] │ │ mov sl, r1 │ │ @@ -1564700,16 +1564700,16 @@ │ │ ldrbeq r0, [r7, #3128] @ 0xc38 │ │ andeq r3, r0, r4, asr r8 │ │ andeq r3, r0, r8, ror r8 │ │ ldrbeq r0, [r7, #3080] @ 0xc08 │ │ andeq r3, r0, r0, lsr #17 │ │ ldrbeq r0, [r7, #2820] @ 0xb04 │ │ ldrbeq r0, [r7, #1272] @ 0x4f8 │ │ - stc2l 5, cr9, [pc, #628] @ 253ccf8 │ │ - stc2l 1, cr9, [pc, #948] @ 253ce3c │ │ + stc2l 5, cr9, [pc, #808] @ 253cdac │ │ + stc2l 2, cr9, [pc, #104] @ 253caf0 │ │ stc2l 7, cr13, [pc, #280] @ 253cba4 │ │ ldrbeq r0, [r7, #1804] @ 0x70c │ │ ldrbeq r0, [r7, #3500] @ 0xdac │ │ ldrbeq r0, [r7, #3464] @ 0xd88 │ │ andeq r3, r0, r8, lsl #19 │ │ andeq r3, r0, ip, lsr #19 │ │ ldrbeq r0, [r7, #3392] @ 0xd40 │ │ @@ -1564883,15 +1564883,15 @@ │ │ b 253cd18 │ │ mov r0, #48 @ 0x30 │ │ strh r0, [r1] │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, lr} │ │ mov r0, r1 │ │ bx lr │ │ - stc2l 3, cr12, [lr, #960] @ 0x3c0 │ │ + stc2l 4, cr12, [lr, #116] @ 0x74 │ │ │ │ 0253cd2c : │ │ cmp r0, #0 │ │ beq 253cd48 │ │ ldr r1, [r0, #8] │ │ cmp r1, #0 │ │ beq 253cd54 │ │ @@ -1564936,15 +1564936,15 @@ │ │ b 253cde4 │ │ mov r0, #48 @ 0x30 │ │ strh r0, [r1] │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, lr} │ │ mov r0, r1 │ │ bx lr │ │ - stc2l 3, cr12, [lr, #144] @ 0x90 │ │ + stc2l 3, cr12, [lr, #324] @ 0x144 │ │ │ │ 0253cdf8 : │ │ cmp r0, #0 │ │ bxeq lr │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ @@ -1564988,15 +1564988,15 @@ │ │ strh r0, [r1] │ │ mov r2, r6 │ │ mov r0, r2 │ │ bl 27120b0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, lr} │ │ bx lr │ │ - stc2l 2, cr12, [lr, #416] @ 0x1a0 │ │ + stc2l 2, cr12, [lr, #596] @ 0x254 │ │ │ │ 0253cec0 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ mov r6, r1 │ │ ldr r1, [r1] │ │ @@ -1565058,15 +1565058,15 @@ │ │ mov r0, r7 │ │ mov r1, #1 │ │ bl 2539ff8 │ │ mov r0, r4 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ andseq r1, pc, r8, ror #13 │ │ - stc2l 0, cr15, [sp, #144] @ 0x90 │ │ + stc2l 0, cr15, [sp, #324] @ 0x144 │ │ ldc2l 3, cr8, [r0, #548] @ 0x224 │ │ │ │ 0253cfd4 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #852 @ 0x354 │ │ mov r4, r0 │ │ @@ -1565849,26 +1565849,26 @@ │ │ sub r0, fp, #200 @ 0xc8 │ │ bl 27103d0 │ │ sub r0, fp, #144 @ 0x90 │ │ bl 27103d0 │ │ sub r0, fp, #88 @ 0x58 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - stc2l 1, cr9, [pc, #184] @ 253dce0 │ │ - stc2l 14, cr8, [pc, #136] @ 253dcb4 │ │ + stc2l 1, cr9, [pc, #364] @ 253dd94 │ │ + stc2l 14, cr8, [pc, #316] @ 253dd68 │ │ stc2l 10, cr12, [pc, #456] @ 253ddf8 @ │ │ stc2l 8, cr12, [pc, #872] @ 253df9c │ │ - stc2l 12, cr8, [pc, #600] @ 253de90 │ │ - stc2l 4, cr6, [pc, #88] @ 253dc94 │ │ + stc2l 12, cr8, [pc, #780] @ 253df44 │ │ + stc2l 4, cr6, [pc, #268] @ 253dd48 │ │ stc2l 7, cr12, [pc, #680] @ 253dee8 │ │ stc2l 5, cr12, [pc, #248] @ 253dd3c │ │ - stc2l 8, cr8, [pc, #1000] @ 253e030 │ │ - stc2l 9, cr1, [pc, #428] @ 253ddf8 @ │ │ + stc2l 9, cr8, [pc, #78] @ 253dc96 @ │ │ + stc2l 10, cr1, [pc, #12] @ 253dc58 @ │ │ stc2l 9, cr13, [pc, #66] @ 253dc92 @ │ │ - vcadd.f16 , , q11, #270 │ │ + stc2l 8, cr1, [pc, #588] @ 253dea0 │ │ stc2l 7, cr13, [pc, #708] @ 253df1c │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #64 @ 0x40 │ │ mov r6, r2 │ │ ldr r2, [r3] │ │ mov r5, r0 │ │ @@ -1565929,15 +1565929,15 @@ │ │ mov r0, r4 │ │ mov r1, r6 │ │ bl 2710850 │ │ mov r0, r6 │ │ bl 27103d0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - stc2l 13, cr5, [pc, #68] @ 253ddac │ │ + stc2l 13, cr5, [pc, #248] @ 253de60 │ │ │ │ 0253dd64 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #260 @ 0x104 │ │ sub sp, sp, #4096 @ 0x1000 │ │ vmov.i32 q8, #0 @ 0x00000000 │ │ @@ -1566116,15 +1566116,15 @@ │ │ bl 2713790 │ │ add r1, r4, #1 │ │ mov r0, r5 │ │ mov r2, r7 │ │ bl 2713be0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - stc2l 2, cr8, [pc, #552] @ 253e274 │ │ + stc2l 2, cr8, [pc, #732] @ 253e328 │ │ ldc2l 11, cr3, [r0, #908] @ 0x38c @ │ │ │ │ 0253e04c : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #8 │ │ mov r4, r2 │ │ @@ -1566411,15 +1566411,15 @@ │ │ b 253e438 │ │ blx 207deaa │ │ blx 207deaa │ │ ldrbeq lr, [r6, #3492] @ 0xda4 │ │ ldrbeq lr, [r6, #3452] @ 0xd7c │ │ ldrbeq lr, [r6, #3272] @ 0xcc8 │ │ ldrbeq lr, [r6, #3204] @ 0xc84 │ │ - stc2l 13, cr0, [lr, #4] │ │ + stc2l 13, cr0, [lr, #184] @ 0xb8 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #180 @ 0xb4 │ │ ldr sl, [fp, #24] │ │ mov r6, r2 │ │ ldr r8, [fp, #20] │ │ ldr r2, [sl] │ │ @@ -1566811,17 +1566811,17 @@ │ │ add r0, sp, #40 @ 0x28 │ │ bl 27103d0 │ │ sub r0, fp, #92 @ 0x5c │ │ bl 2710d40 │ │ sub r0, fp, #88 @ 0x58 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - stc2l 12, cr1, [lr, #732] @ 0x2dc │ │ + stc2l 12, cr1, [lr, #912] @ 0x390 │ │ stc2l 7, cr13, [pc, #204] @ 253ebf0 │ │ - stc2l 0, cr2, [lr, #132] @ 0x84 │ │ + stc2l 0, cr2, [lr, #312] @ 0x138 │ │ push {fp, lr} │ │ mov fp, sp │ │ bl 27128e0 │ │ pop {fp, lr} │ │ b 2713d70 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -1567516,18 +1567516,18 @@ │ │ bl 26ffb60 │ │ sub r0, fp, #92 @ 0x5c │ │ bl 27105c0 │ │ bl 26ffb60 │ │ stc2l 13, cr10, [pc, #904] @ 253f9a0 │ │ ldc2l 11, cr0, [sp, #976] @ 0x3d0 @ │ │ ldc2l 6, cr0, [sp, #1012] @ 0x3f4 │ │ - stc2l 10, cr4, [pc, #752] @ 253f914 @ │ │ - stc2l 9, cr4, [pc, #472] @ 253f800 @ │ │ - stc2l 11, cr4, [pc, #784] @ 253f93c @ │ │ - stc2l 10, cr4, [pc, #480] @ 253f810 @ │ │ + stc2l 10, cr4, [pc, #932] @ 253f9c8 @ │ │ + stc2l 10, cr4, [pc, #100] @ 253f68c @ │ │ + stc2l 11, cr4, [pc, #964] @ 253f9f0 @ │ │ + stc2l 10, cr4, [pc, #660] @ 253f8c4 @ │ │ ldc2l 5, cr0, [sp, #532] @ 0x214 │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #184 @ 0xb8 │ │ vmov.i32 q8, #0 @ 0x00000000 │ │ add r3, sp, #8 │ │ mov r4, r2 │ │ @@ -1567821,17 +1567821,17 @@ │ │ cmp r0, #0 │ │ bne 253f9c0 │ │ b 253f998 │ │ str r1, [r5] │ │ mov r4, #0 │ │ b 253f998 │ │ ldc2l 9, cr9, [r0, #260] @ 0x104 @ │ │ - stc2l 15, cr3, [pc, #676] @ 253fd8c │ │ + stc2l 15, cr3, [pc, #856] @ 253fe40 │ │ stc2l 3, cr10, [pc, #424] @ 253fc94 │ │ - stc2l 0, cr6, [pc, #884] @ 253fe64 │ │ + stc2l 1, cr6, [pc, #40] @ 253fb18 │ │ ldr r3, [r1] │ │ mov r2, r0 │ │ mov r0, #0 │ │ cmp r3, #0 │ │ bxgt lr │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ @@ -1568157,16 +1568157,16 @@ │ │ b 2540014 │ │ b 2540014 │ │ add r0, sp, #24 │ │ bl 27103d0 │ │ mov r0, r9 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - stc2l 4, cr0, [lr, #568] @ 0x238 │ │ - stc2l 15, cr3, [pc, #992] @ 254040c │ │ + stc2l 4, cr0, [lr, #748] @ 0x2ec │ │ + stc2l 0, cr4, [pc, #148] @ 25400c0 │ │ ldc2l 6, cr1, [sp, #336] @ 0x150 │ │ ldc2l 3, cr0, [sp, #992] @ 0x3e0 │ │ ldc2l 5, cr1, [sp, #944] @ 0x3b0 │ │ ldc2l 3, cr0, [sp, #576] @ 0x240 │ │ ldc2l 3, cr1, [sp, #220] @ 0xdc │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ @@ -1570482,21 +1570482,21 @@ │ │ beq 25420b4 │ │ ldr r0, [sp, #20] │ │ bl 2710990 │ │ mov r1, #0 │ │ b 2541f7c │ │ stc2l 15, cr7, [pc, #704] @ 2542604 │ │ ldc2l 2, cr3, [r0, #888] @ 0x378 │ │ - stc2l 1, cr8, [lr, #824] @ 0x338 │ │ - stc2l 2, cr6, [lr, #668] @ 0x29c │ │ - stc2l 0, cr8, [lr, #436] @ 0x1b4 │ │ - stc2l 0, cr2, [lr, #588] @ 0x24c │ │ + stc2l 1, cr8, [lr, #1004] @ 0x3ec │ │ + stc2l 2, cr6, [lr, #848] @ 0x350 │ │ + stc2l 0, cr8, [lr, #616] @ 0x268 │ │ + stc2l 0, cr2, [lr, #768] @ 0x300 │ │ stc2l 3, cr6, [sp, #340] @ 0x154 │ │ - stc2l 2, cr10, [lr, #12] │ │ - stc2l 2, cr2, [lr, #444] @ 0x1bc │ │ + stc2l 2, cr10, [lr, #192] @ 0xc0 │ │ + stc2l 2, cr2, [lr, #624] @ 0x270 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #68 @ 0x44 │ │ ldr r7, [fp, #16] │ │ lsr r4, r3, #28 │ │ str r7, [fp, #-32] @ 0xffffffe0 │ │ cmp r4, #9 │ │ @@ -1571018,20 +1571018,20 @@ │ │ ldr r1, [fp, #-40] @ 0xffffffd8 │ │ cmp r0, r1 │ │ beq 2542398 │ │ lsl r2, r6, #2 │ │ bl 26fe39c │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - stc2l 0, cr14, [sp, #628] @ 0x274 │ │ + stc2l 0, cr14, [sp, #808] @ 0x328 │ │ ldc2l 15, cr0, [sp, #432] @ 0x1b0 │ │ - stc2l 14, cr13, [sp, #932] @ 0x3a4 │ │ + stc2l 15, cr13, [sp, #88] @ 0x58 │ │ ldc2l 7, cr12, [r0, #1016] @ 0x3f8 │ │ andeq r0, r0, r8, lsl r2 │ │ - stc2l 11, cr5, [lr, #952] @ 0x3b8 @ │ │ + stc2l 12, cr5, [lr, #108] @ 0x6c │ │ stc2l 9, cr7, [sp, #398] @ 0x18e @ │ │ ldr r1, [r1] │ │ ldr r3, [r2] │ │ add r2, r0, r1 │ │ add r1, r0, r3 │ │ mov r0, r2 │ │ b 2705a10 │ │ @@ -1571623,15 +1571623,15 @@ │ │ ldr r0, [sp, #4] │ │ bl 27103d0 │ │ ldr r0, [sp] │ │ bl 27103d0 │ │ mov r0, sl │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - stc2l 2, cr13, [sp, #212] @ 0xd4 │ │ + stc2l 2, cr13, [sp, #392] @ 0x188 │ │ │ │ 0254349c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ mov r6, r0 │ │ ldr r0, [r1] │ │ @@ -1572522,23 +1572522,23 @@ │ │ bl 26ffb60 │ │ stc2l 1, cr8, [pc, #652] @ 2544500 │ │ ldc2l 7, cr5, [r0, #644] @ 0x284 │ │ stc2l 15, cr13, [pc, #464] @ 254444c │ │ stc2l 10, cr4, [sp, #100] @ 0x64 @ │ │ stc2l 9, cr4, [sp, #186] @ 0xba @ │ │ stc2l 9, cr4, [sp, #146] @ 0x92 @ │ │ - stc2l 2, cr13, [sp, #848] @ 0x350 │ │ - stc2l 2, cr13, [sp, #560] @ 0x230 │ │ + stc2l 3, cr13, [sp, #4] │ │ + stc2l 2, cr13, [sp, #740] @ 0x2e4 │ │ stc2l 7, cr4, [sp, #596] @ 0x254 │ │ ldc2l 5, cr9, [r0, #724] @ 0x2d4 │ │ - stc2l 10, cr1, [pc, #988] @ 2544678 @ │ │ + stc2l 11, cr1, [pc, #144] @ 254432c @ │ │ stc2l 10, cr13, [pc, #500] @ 2544494 @ │ │ - stc2l 1, cr0, [lr, #884] @ 0x374 │ │ + stc2l 2, cr0, [lr, #40] @ 0x28 │ │ stc2l 11, cr11, [pc, #80] @ 25442f8 @ │ │ - stc2l 5, cr12, [sp, #356] @ 0x164 │ │ + stc2l 5, cr12, [sp, #536] @ 0x218 │ │ ldrbeq r8, [r6, #4060] @ 0xfdc │ │ ldrbeq r8, [r6, #3968] @ 0xf80 │ │ ldrbeq r8, [r6, #3340] @ 0xd0c │ │ ldrbeq r8, [r6, #3864] @ 0xf18 │ │ │ │ 025442b8 : │ │ push {fp, lr} │ │ @@ -1573997,15 +1573997,15 @@ │ │ add r1, pc, r1 │ │ mov r0, r4 │ │ bl 2713760 │ │ mov r0, #16 │ │ b 25456f8 │ │ vcadd.f16 d20, d31, d6, #270 │ │ stc2l 3, cr12, [pc, #540] @ 2545b88 │ │ - stc2l 12, cr2, [lr, #616] @ 0x268 │ │ + stc2l 12, cr2, [lr, #796] @ 0x31c │ │ stc2l 2, cr10, [pc, #776] @ 2545c7c │ │ │ │ 02545970 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #36 @ 0x24 │ │ ldr sl, [fp, #8] │ │ @@ -1574128,15 +1574128,15 @@ │ │ lsl r2, r0, #1 │ │ mov r0, r4 │ │ blx r7 │ │ ldr r0, [sp, #28] │ │ ldr r1, [sp, #32] │ │ add r1, r0, r1 │ │ b 2545a0c │ │ - stc2l 10, cr6, [lr, #896] @ 0x380 @ │ │ + stc2l 11, cr6, [lr, #52] @ 0x34 @ │ │ stc2l 2, cr6, [pc, #748] @ 2545e64 │ │ │ │ 02545b74 : │ │ ldr ip, [r3] │ │ cmp ip, #0 │ │ ble 2545b88 │ │ mov r0, #0 │ │ @@ -1586415,15 +1586415,15 @@ │ │ mov r1, r3 │ │ movlt r0, #37 @ 0x25 │ │ strblt r0, [r4, r5] │ │ add r0, r5, #1 │ │ str r0, [sp, #68] @ 0x44 │ │ ldr r5, [sp, #68] @ 0x44 │ │ b 254f1e0 │ │ - stc2l 0, cr3, [lr, #600] @ 0x258 │ │ + stc2l 0, cr3, [lr, #780] @ 0x30c │ │ cmp r5, #0 │ │ bne 2551980 │ │ cmp lr, #1 │ │ blt 2551980 │ │ mov r5, #0 │ │ cmp lr, #16 │ │ bcc 2551968 │ │ @@ -1594575,15 +1594575,15 @@ │ │ @ instruction: 0x001e2ddc │ │ stc2l 8, cr13, [fp, #632] @ 0x278 │ │ stc2l 15, cr4, [pc, #664] @ 255957c │ │ stc2l 2, cr3, [lr, #584] @ 0x248 │ │ andseq r5, sp, r0, lsl #30 │ │ stc2l 13, cr8, [lr, #924] @ 0x39c │ │ stc2l 8, cr15, [fp, #748] @ 0x2ec │ │ - stc2l 0, cr5, [sp, #60] @ 0x3c │ │ + stc2l 0, cr5, [sp, #240] @ 0xf0 │ │ │ │ 025592f4 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [r0, #320] @ 0x140 │ │ cmp r0, #0 │ │ @@ -1595537,15 +1595537,15 @@ │ │ sub r0, fp, #160 @ 0xa0 │ │ bl 2714160 │ │ sub r0, fp, #96 @ 0x60 │ │ bl 2714160 │ │ bl 26ffb60 │ │ andseq r1, lr, r8, lsr ip │ │ stc2l 5, cr8, [pc, #96] @ 255a22c │ │ - stc2l 9, cr6, [ip, #202] @ 0xca @ │ │ + stc2l 9, cr6, [ip, #292] @ 0x124 @ │ │ @ instruction: 0xffb08d1c │ │ │ │ 0255a1d0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ mov r7, r3 │ │ @@ -1598388,18 +1598388,18 @@ │ │ ldrbeq r1, [r5, #140] @ 0x8c │ │ ldrbeq r1, [r5, #52] @ 0x34 │ │ stc2l 12, cr11, [pc, #760] @ 255d0b0 │ │ andseq pc, sp, r4, lsr r7 @ │ │ ldrbeq r1, [r5, #24] │ │ andseq r3, ip, r4, lsl #18 │ │ ldrbeq r1, [r5, #72] @ 0x48 │ │ - stc2l 14, cr3, [ip, #976] @ 0x3d0 │ │ - stc2l 14, cr3, [ip, #848] @ 0x350 │ │ + stc2l 15, cr3, [ip, #132] @ 0x84 │ │ + stc2l 15, cr3, [ip, #4] │ │ ldrbeq r0, [r5, #3668] @ 0xe54 │ │ - stc2l 15, cr1, [ip, #40] @ 0x28 │ │ + stc2l 15, cr1, [ip, #220] @ 0xdc │ │ andseq pc, sp, r0 │ │ andseq pc, sp, ip, lsr r4 @ │ │ ldrbeq r0, [r5, #612] @ 0x264 │ │ │ │ 0255cde0 : │ │ mov r1, #0 │ │ cmp r0, #127 @ 0x7f │ │ @@ -1598669,15 +1598669,15 @@ │ │ ldr r1, [r0, #4] │ │ mov r0, r5 │ │ blx r1 │ │ add r0, sp, #40 @ 0x28 │ │ bl 2718670 │ │ bl 26ffb60 │ │ @ instruction: 0x001de9b4 │ │ - stc2l 6, cr3, [ip, #452] @ 0x1c4 │ │ + stc2l 6, cr3, [ip, #632] @ 0x278 │ │ andseq lr, sp, ip, lsr #11 │ │ mulseq sp, r0, sl │ │ andseq lr, sp, r8, lsr fp │ │ andseq lr, sp, ip, lsl #18 │ │ @ instruction: 0x001de7d8 │ │ cmp r1, #0 │ │ bxmi lr │ │ @@ -1601057,17 +1601057,17 @@ │ │ bne 2560098 │ │ ldr r2, [sp, #48] @ 0x30 │ │ mov r0, r9 │ │ mov r1, #0 │ │ bl 2716050 │ │ b 25604dc │ │ andseq sp, sp, r8, lsr #7 │ │ - stc2l 4, cr7, [sp, #392] @ 0x188 │ │ - stc2l 11, cr1, [ip, #112] @ 0x70 @ │ │ - stc2l 11, cr1, [ip] @ │ │ + stc2l 4, cr7, [sp, #572] @ 0x23c │ │ + stc2l 11, cr1, [ip, #292] @ 0x124 @ │ │ + stc2l 11, cr1, [ip, #180] @ 0xb4 @ │ │ ldr r0, [sp, #64] @ 0x40 │ │ ldr r1, [r0] │ │ ldr r3, [r1, #112] @ 0x70 │ │ sub r2, fp, #132 @ 0x84 │ │ mov r1, #3 │ │ blx r3 │ │ ldr r1, [fp, #8] │ │ @@ -1601522,15 +1601522,15 @@ │ │ stmib sp, {r0, r3, r9} │ │ bl 271c2f0 │ │ mov r7, r0 │ │ ldr r0, [r5] │ │ cmn r7, r0 │ │ subeq r7, r7, #1 │ │ b 255e938 │ │ - stc2l 1, cr15, [fp, #440] @ 0x1b8 │ │ + stc2l 1, cr15, [fp, #620] @ 0x26c │ │ add r0, r8, #256 @ 0x100 │ │ add r8, r8, #192 @ 0xc0 │ │ mov sl, r0 │ │ ldr r0, [sp, #64] @ 0x40 │ │ ldr r1, [r0] │ │ ldr r3, [r1, #112] @ 0x70 │ │ sub r2, fp, #132 @ 0x84 │ │ @@ -1602038,15 +1602038,15 @@ │ │ sub r0, fp, #128 @ 0x80 │ │ bl 27184b0 │ │ bl 26ffb60 │ │ @ instruction: 0xffb0330c │ │ stc2l 13, cr2, [pc, #32] @ 2560680 │ │ stc2l 12, cr2, [pc, #496] @ 2560854 │ │ @ instruction: 0xffb029dc │ │ - stc2l 11, cr13, [fp, #552] @ 0x228 @ │ │ + stc2l 11, cr13, [fp, #732] @ 0x2dc @ │ │ │ │ 02560668 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #92 @ 0x5c │ │ mov r6, r0 │ │ mov r0, #2 │ │ @@ -1602672,15 +1602672,15 @@ │ │ bl 2716050 │ │ add r0, r7, r9 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ rsb r0, r9, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - stc2l 15, cr12, [fp, #872] @ 0x368 │ │ + stc2l 0, cr13, [fp, #28] │ │ │ │ 02561030 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #228 @ 0xe4 │ │ mov r0, #2 │ │ str r1, [sp, #16] │ │ @@ -1602810,15 +1602810,15 @@ │ │ add r0, sp, #92 @ 0x5c │ │ bl 2714160 │ │ b 256123c │ │ sub r0, fp, #96 @ 0x60 │ │ bl 2714160 │ │ bl 26ffb60 │ │ andseq sl, sp, r4, ror #12 │ │ - stc2l 14, cr12, [fp, #184] @ 0xb8 │ │ + stc2l 14, cr12, [fp, #364] @ 0x16c │ │ │ │ 02561250 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ vpush {d8} │ │ sub sp, sp, #8 │ │ ldr r4, [fp, #8] │ │ @@ -1603431,16 +1603431,16 @@ │ │ bl 2711190 │ │ bl 26ffb60 │ │ stc2l 6, cr8, [sp, #244] @ 0xf4 │ │ stc2l 4, cr15, [lr] │ │ stc2l 10, cr5, [pc, #232] @ 2561c9c @ │ │ ldrbeq fp, [r4, #1348] @ 0x544 │ │ ldrbeq fp, [r4, #1288] @ 0x508 │ │ - stc2l 11, cr14, [fp, #516] @ 0x204 @ │ │ - stc2l 6, cr14, [ip, #328] @ 0x148 │ │ + stc2l 11, cr14, [fp, #696] @ 0x2b8 @ │ │ + stc2l 6, cr14, [ip, #508] @ 0x1fc │ │ vcadd.f16 d21, d31, d22, #270 │ │ │ │ 02561bc4 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #72 @ 0x48 │ │ mov r4, r2 │ │ @@ -1605437,15 +1605437,15 @@ │ │ andseq r8, sp, ip, ror #21 │ │ andseq r8, sp, r8, ror #21 │ │ andseq r8, sp, r8, asr #21 │ │ @ instruction: 0xffb000f8 │ │ @ instruction: 0xffb000c9 │ │ @ instruction: 0xffb00001 │ │ @ instruction: 0xffaffff4 │ │ - vcadd.f16 d29, d27, d21, #270 │ │ + stc2l 8, cr13, [fp, #840] @ 0x348 │ │ @ instruction: 0xffafff41 │ │ ldr r3, [fp, #-36] @ 0xffffffdc │ │ str r0, [fp, #-40] @ 0xffffffd8 │ │ add r0, sp, #468 @ 0x1d4 │ │ sub r2, fp, #40 @ 0x28 │ │ mov r1, #1 │ │ bl 2714270 │ │ @@ -1606304,24 +1606304,24 @@ │ │ add r6, r6, #64 @ 0x40 │ │ subs r4, r4, #1 │ │ bne 256473c │ │ b 25647dc │ │ stc2l 5, cr8, [sp, #952] @ 0x3b8 │ │ andseq fp, ip, r0, lsl r2 │ │ stc2l 1, cr0, [lr, #572] @ 0x23c │ │ - stc2l 10, cr12, [fp, #904] @ 0x388 @ │ │ + stc2l 11, cr12, [fp, #60] @ 0x3c @ │ │ stc2l 13, cr9, [lr, #544] @ 0x220 │ │ stc2l 3, cr14, [sp, #644] @ 0x284 │ │ stc2l 2, cr4, [lr, #536] @ 0x218 │ │ stc2l 7, cr6, [sp, #600] @ 0x258 │ │ - stc2l 1, cr0, [sp, #420] @ 0x1a4 │ │ - stc2l 3, cr2, [sp, #252] @ 0xfc │ │ - stc2l 10, cr12, [fp, #348] @ 0x15c @ │ │ + stc2l 1, cr0, [sp, #600] @ 0x258 │ │ + stc2l 3, cr2, [sp, #432] @ 0x1b0 │ │ + stc2l 10, cr12, [fp, #528] @ 0x210 @ │ │ stc2l 10, cr1, [lr, #832] @ 0x340 @ │ │ - stc2l 3, cr2, [sp, #72] @ 0x48 │ │ + stc2l 3, cr2, [sp, #252] @ 0xfc │ │ stc2l 3, cr12, [sp, #652] @ 0x28c │ │ andseq fp, ip, r4, ror #1 │ │ ldrheq fp, [ip], -r8 │ │ andseq fp, ip, r8, lsr #1 │ │ mulseq ip, r8, r0 │ │ andseq fp, ip, r8, lsl #1 │ │ andseq fp, ip, r8, ror r0 │ │ @@ -1617699,15 +1617699,15 @@ │ │ b 256f708 │ │ sub r0, fp, #228 @ 0xe4 │ │ bl 2711190 │ │ bl 26ffb60 │ │ ldrbeq sp, [r3, #2920] @ 0xb68 │ │ mulseq ip, r8, r1 │ │ @ instruction: 0x001cc1d4 │ │ - stc2l 1, cr1, [fp, #324] @ 0x144 │ │ + stc2l 1, cr1, [fp, #504] @ 0x1f8 │ │ @ instruction: 0x001cc1b0 │ │ andseq ip, ip, r8, lsr r1 │ │ @ instruction: 0xffaf3a1b │ │ stc2l 13, cr11, [sp, #680] @ 0x2a8 │ │ │ │ 0256f734 : │ │ b 2712b50 │ │ @@ -1618279,16 +1618279,16 @@ │ │ bl 2711190 │ │ bl 26ffb60 │ │ @ instruction: 0xffaf3503 │ │ @ instruction: 0xffaf4312 │ │ @ instruction: 0xffaf4260 │ │ @ instruction: 0xffaf445a │ │ @ instruction: 0xffaf43b4 │ │ - vcadd.f16 d24, d27, d12, #270 │ │ - stc2l 6, cr4, [fp, #296] @ 0x128 │ │ + stc2l 8, cr8, [fp, #740] @ 0x2e4 │ │ + stc2l 6, cr4, [fp, #476] @ 0x1dc │ │ stc2l 0, cr12, [ip, #1008] @ 0x3f0 │ │ stc2l 14, cr15, [ip, #424] @ 0x1a8 │ │ │ │ 0256ffe8 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r6, #0 │ │ @@ -1619071,16 +1619071,16 @@ │ │ bl 27103d0 │ │ add r0, sp, #60 @ 0x3c │ │ bl 27103d0 │ │ sub r0, fp, #76 @ 0x4c │ │ bl 27103d0 │ │ bl 26ffb60 │ │ @ instruction: 0xffaf263b │ │ - stc2l 10, cr7, [fp, #416] @ 0x1a0 @ │ │ - vcadd.f16 d19, d11, d31, #270 │ │ + stc2l 10, cr7, [fp, #596] @ 0x254 @ │ │ + stc2l 8, cr3, [fp, #368] @ 0x170 │ │ stc2l 2, cr11, [ip, #864] @ 0x360 │ │ │ │ 02570bec : │ │ sub r2, r1, #1 │ │ cmp r2, #6 │ │ bxhi lr │ │ ldr r2, [r0, #256] @ 0x100 │ │ @@ -1624072,25 +1624072,25 @@ │ │ str r2, [r9, #216] @ 0xd8 │ │ str r0, [r9, #224] @ 0xe0 │ │ strb ip, [r9, #126] @ 0x7e │ │ strb lr, [r9, #7] │ │ strh lr, [r9, #4] │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ - stc2l 7, cr0, [ip, #112] @ 0x70 │ │ - stc2l 13, cr14, [sl, #1016] @ 0x3f8 │ │ - stc2l 10, cr8, [sl, #888] @ 0x378 @ │ │ + stc2l 7, cr0, [ip, #292] @ 0x124 │ │ + stc2l 14, cr14, [sl, #172] @ 0xac │ │ + stc2l 11, cr8, [sl, #44] @ 0x2c @ │ │ stc2l 1, cr3, [sl, #832] @ 0x340 │ │ - stc2l 4, cr14, [fp, #656] @ 0x290 │ │ + stc2l 4, cr14, [fp, #836] @ 0x344 │ │ stc2l 0, cr8, [sp, #344] @ 0x158 │ │ stc2l 9, cr14, [r9, #386] @ 0x182 @ │ │ stc2l 6, cr12, [ip, #316] @ 0x13c │ │ - vcadd.f16 d18, d28, d13, #270 │ │ + stc2l 8, cr2, [ip, #744] @ 0x2e8 │ │ stc2l 14, cr5, [sp, #632] @ 0x278 │ │ - stc2l 13, cr10, [sl, #220] @ 0xdc │ │ + stc2l 13, cr10, [sl, #400] @ 0x190 │ │ stc2l 15, cr7, [sp, #808] @ 0x328 │ │ │ │ 025757ec : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r0 │ │ ldr r0, [r1] │ │ @@ -1627044,27 +1627044,27 @@ │ │ pop {r4, sl, fp, pc} │ │ mov r0, #15 │ │ pop {r4, sl, fp, pc} │ │ mov r0, #16 │ │ pop {r4, sl, fp, pc} │ │ @ instruction: 0xffaebcea │ │ stc2l 12, cr1, [ip, #628] @ 0x274 │ │ - stc2l 14, cr9, [sl, #820] @ 0x334 │ │ + stc2l 14, cr9, [sl, #1000] @ 0x3e8 │ │ stc2l 6, cr11, [ip, #72] @ 0x48 │ │ stc2l 3, cr0, [sl, #400] @ 0x190 │ │ stc2l 11, cr11, [r9, #508] @ 0x1fc @ │ │ - stc2l 11, cr5, [fp, #116] @ 0x74 @ │ │ - stc2l 12, cr5, [sl, #40] @ 0x28 │ │ - stc2l 14, cr7, [sl, #880] @ 0x370 │ │ - stc2l 15, cr1, [fp, #64] @ 0x40 │ │ - stc2l 14, cr7, [sl, #912] @ 0x390 │ │ - stc2l 11, cr5, [sl, #708] @ 0x2c4 @ │ │ - stc2l 7, cr13, [fp, #624] @ 0x270 │ │ + stc2l 11, cr5, [fp, #296] @ 0x128 @ │ │ + stc2l 12, cr5, [sl, #220] @ 0xdc │ │ + stc2l 15, cr7, [sl, #36] @ 0x24 │ │ + stc2l 15, cr1, [fp, #244] @ 0xf4 │ │ + stc2l 15, cr7, [sl, #68] @ 0x44 │ │ + stc2l 11, cr5, [sl, #888] @ 0x378 @ │ │ + stc2l 7, cr13, [fp, #804] @ 0x324 │ │ stc2l 15, cr2, [sp, #936] @ 0x3a8 │ │ - stc2l 14, cr7, [sl, #336] @ 0x150 │ │ + stc2l 14, cr7, [sl, #516] @ 0x204 │ │ stc2l 1, cr5, [sp, #36] @ 0x24 │ │ stc2l 9, cr3, [ip, #72] @ 0x48 @ │ │ stc2l 4, cr11, [ip, #792] @ 0x318 │ │ │ │ 0257859c (icu_75::Locale const&, icu_75::SharedCalendar const*&, UErrorCode&)@@Base>: │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ @@ -1633736,15 +1633736,15 @@ │ │ add r0, sp, #28 │ │ bl 2710d40 │ │ b 257e8bc │ │ add r0, sp, #36 @ 0x24 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ @ instruction: 0xffae5b2c │ │ - stc2l 13, cr9, [sl, #644] @ 0x284 │ │ + stc2l 13, cr9, [sl, #824] @ 0x338 │ │ @ instruction: 0xffae5ac1 │ │ stc2l 2, cr5, [ip, #364] @ 0x16c │ │ @ instruction: 0xffae5b14 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #236 @ 0xec │ │ ldr r8, [fp, #24] │ │ @@ -1634088,24 +1634088,24 @@ │ │ add r0, sp, #80 @ 0x50 │ │ bl 27141e0 │ │ sub r0, fp, #152 @ 0x98 │ │ bl 27141e0 │ │ sub r0, fp, #40 @ 0x28 │ │ bl 2710d40 │ │ bl 26ffb60 │ │ - stc2l 6, cr11, [sl, #284] @ 0x11c │ │ - stc2l 12, cr4, [fp, #1008] @ 0x3f0 │ │ + stc2l 6, cr11, [sl, #464] @ 0x1d0 │ │ + stc2l 13, cr4, [fp, #164] @ 0xa4 │ │ stc2l 7, cr12, [ip, #952] @ 0x3b8 │ │ │ │ 0257ee50 : │ │ mov r2, r1 │ │ ldr r1, [pc, #4] @ 257ee60 │ │ add r1, pc, r1 │ │ b 257ee64 │ │ - stc2l 13, cr6, [fp, #592] @ 0x250 │ │ + stc2l 13, cr6, [fp, #772] @ 0x304 │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #72 @ 0x48 │ │ mov r4, r2 │ │ mov r2, r0 │ │ ldr r3, [r4] │ │ mov r0, #4 │ │ @@ -1634163,15 +1634163,15 @@ │ │ ldr r1, [pc, #24] @ 257ef6c │ │ add r1, pc, r1 │ │ ldr r1, [r1, r0, lsl #2] │ │ b 257eeb4 │ │ add r0, sp, #16 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - stc2l 3, cr7, [sl, #24] │ │ + stc2l 3, cr7, [sl, #204] @ 0xcc │ │ @ instruction: 0xffae52f8 │ │ │ │ 0257ef70 : │ │ mov r2, r1 │ │ ldr r1, [pc, #4] @ 257ef80 │ │ add r1, pc, r1 │ │ b 257ee64 │ │ @@ -1635423,15 +1635423,15 @@ │ │ bl 2713e30 │ │ mov r1, r7 │ │ mov r2, r0 │ │ mov r3, r4 │ │ bl 2713e30 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - vcadd.f16 , , q7, #270 │ │ + stc2l 8, cr3, [fp, #1004] @ 0x3ec │ │ │ │ 02580134 : │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r0, [pc, #64] @ 2580184 │ │ add r0, pc, r0 │ │ ldr r0, [r0] │ │ @@ -1636719,18 +1636719,18 @@ │ │ mov r3, r4 │ │ mov r7, r0 │ │ bl 2715220 │ │ mov r0, r7 │ │ bl 2713e90 │ │ mov r0, r6 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - vcadd.f16 d20, d11, d7, #270 │ │ - vcadd.f16 q10, , , #270 │ │ - stc2l 10, cr12, [sl, #820] @ 0x334 @ │ │ - stc2l 10, cr12, [sl, #500] @ 0x1f4 @ │ │ + stc2l 8, cr4, [fp, #208] @ 0xd0 │ │ + stc2l 8, cr4, [fp, #448] @ 0x1c0 │ │ + stc2l 10, cr12, [sl, #1000] @ 0x3e8 @ │ │ + stc2l 10, cr12, [sl, #680] @ 0x2a8 @ │ │ │ │ 02581490 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #248 @ 0xf8 │ │ mov r4, r0 │ │ mov r0, #2 │ │ @@ -1636838,15 +1636838,15 @@ │ │ bl 27141e0 │ │ b 2581640 │ │ mov r0, r4 │ │ bl 2714160 │ │ bl 26ffb60 │ │ andseq sl, fp, r4, lsl #4 │ │ stc2l 5, cr6, [ip, #756] @ 0x2f4 │ │ - stc2l 6, cr4, [fp, #636] @ 0x27c │ │ + stc2l 6, cr4, [fp, #816] @ 0x330 │ │ │ │ 02581658 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ ldr r1, [pc, #132] @ 25816f0 │ │ add r5, sp, #4 │ │ @@ -1636879,16 +1636879,16 @@ │ │ mov r0, r4 │ │ bl 2713e90 │ │ cmp r6, #1 │ │ movge r5, r8 │ │ mov r0, r5 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - stc2l 5, cr4, [fp, #172] @ 0xac │ │ - stc2l 5, cr4, [fp, #380] @ 0x17c │ │ + stc2l 5, cr4, [fp, #352] @ 0x160 │ │ + stc2l 5, cr4, [fp, #560] @ 0x230 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #100 @ 0x64 │ │ mov r9, r0 │ │ mov r0, #2 │ │ str r1, [sp, #16] │ │ mov r5, r2 │ │ @@ -1637050,17 +1637050,17 @@ │ │ mov r0, r5 │ │ bl 2713e90 │ │ mov r0, r4 │ │ bl 2713e90 │ │ mov r0, r8 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - stc2l 2, cr4, [fp, #972] @ 0x3cc │ │ - stc2l 3, cr4, [fp, #172] @ 0xac │ │ - stc2l 5, cr12, [sl, #772] @ 0x304 │ │ + stc2l 3, cr4, [fp, #128] @ 0x80 │ │ + stc2l 3, cr4, [fp, #352] @ 0x160 │ │ + stc2l 5, cr12, [sl, #952] @ 0x3b8 │ │ │ │ 025819a0 : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #8 │ │ mov r1, #0 │ │ str r1, [sp, #4] │ │ @@ -1637111,17 +1637111,17 @@ │ │ bl 2713e90 │ │ mov r0, r5 │ │ bl 2713e90 │ │ mov r0, r6 │ │ cmp r4, #0 │ │ movwgt r0, #0 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - stc2l 1, cr4, [fp, #700] @ 0x2bc │ │ - stc2l 1, cr4, [fp, #956] @ 0x3bc │ │ - stc2l 5, cr10, [r9, #344] @ 0x158 │ │ + stc2l 1, cr4, [fp, #880] @ 0x370 │ │ + stc2l 2, cr4, [fp, #112] @ 0x70 │ │ + stc2l 5, cr10, [r9, #524] @ 0x20c │ │ │ │ 02581a84 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #24 │ │ mov r8, r1 │ │ mov r1, r0 │ │ @@ -1638005,16 +1638005,16 @@ │ │ b 2582800 │ │ add r0, sp, #4 │ │ bl 27141e0 │ │ bl 26ffb60 │ │ ldrbeq sl, [r2, #2884] @ 0xb44 │ │ ldrbeq sl, [r2, #2860] @ 0xb2c │ │ @ instruction: 0xffffe3dc │ │ - stc2l 4, cr3, [fp, #172] @ 0xac │ │ - stc2l 10, cr3, [sl, #372] @ 0x174 @ │ │ + stc2l 4, cr3, [fp, #352] @ 0x160 │ │ + stc2l 10, cr3, [sl, #552] @ 0x228 @ │ │ ldrbeq sl, [r2, #2636] @ 0xa4c │ │ ldrbeq sl, [r2, #2584] @ 0xa18 │ │ │ │ 02582828 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #8 │ │ @@ -1638340,16 +1638340,16 @@ │ │ b 2582d24 │ │ str sl, [sp, #24] │ │ add r0, sp, #24 │ │ sub r0, fp, #92 @ 0x5c │ │ bl 2714160 │ │ bl 26ffb60 │ │ andseq r8, fp, r4, lsl ip │ │ - stc2l 7, cr1, [sl, #836] @ 0x344 │ │ - stc2l 7, cr1, [sl, #936] @ 0x3a8 │ │ + stc2l 7, cr1, [sl, #1016] @ 0x3f8 │ │ + stc2l 8, cr1, [sl, #92] @ 0x5c │ │ │ │ 02582d3c : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #144 @ 0x90 │ │ mov r4, r2 │ │ ldrh r2, [r2, #4] │ │ @@ -1638444,16 +1638444,16 @@ │ │ mov r0, r4 │ │ b 2582ec4 │ │ mov r0, r4 │ │ mov r1, r7 │ │ mvn r2, #0 │ │ bl 271b260 │ │ b 2582db4 │ │ - stc2l 5, cr1, [sl, #212] @ 0xd4 │ │ - stc2l 5, cr1, [sl, #280] @ 0x118 │ │ + stc2l 5, cr1, [sl, #392] @ 0x188 │ │ + stc2l 5, cr1, [sl, #460] @ 0x1cc │ │ stc2l 15, cr8, [fp, #304] @ 0x130 │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #120 @ 0x78 │ │ mov r4, r1 │ │ ldr r1, [r1] │ │ mov r5, r0 │ │ @@ -1638753,16 +1638753,16 @@ │ │ str r5, [sp, #40] @ 0x28 │ │ add r0, sp, #40 @ 0x28 │ │ b 2583390 │ │ sub r0, fp, #96 @ 0x60 │ │ bl 2714160 │ │ bl 26ffb60 │ │ @ instruction: 0xffffdb48 │ │ - stc2l 11, cr2, [fp, #636] @ 0x27c @ │ │ - stc2l 11, cr2, [fp, #908] @ 0x38c @ │ │ + stc2l 11, cr2, [fp, #816] @ 0x330 @ │ │ + stc2l 12, cr2, [fp, #64] @ 0x40 │ │ andseq r8, fp, ip, lsr #12 │ │ @ instruction: 0xffae121e │ │ ldrbeq r9, [r2, #3868] @ 0xf1c │ │ ldrbeq r9, [r2, #3864] @ 0xf18 │ │ @ instruction: 0xffae1082 │ │ ldrbeq r9, [r2, #3848] @ 0xf08 │ │ ldrbeq r9, [r2, #3848] @ 0xf08 │ │ @@ -1639014,16 +1639014,16 @@ │ │ add r0, sp, #32 │ │ b 25837a0 │ │ b 25837a0 │ │ b 25837a0 │ │ add r0, sp, #40 @ 0x28 │ │ bl 2714160 │ │ bl 26ffb60 │ │ - stc2l 7, cr2, [fp, #316] @ 0x13c │ │ - stc2l 7, cr2, [fp, #588] @ 0x24c │ │ + stc2l 7, cr2, [fp, #496] @ 0x1f0 │ │ + stc2l 7, cr2, [fp, #768] @ 0x300 │ │ andseq r8, fp, r8, lsr #4 │ │ @ instruction: 0x001b83d8 │ │ andseq r8, fp, r4, lsr #8 │ │ │ │ 025837c0 : │ │ push {r4, r5, r6, r8, r9, sl, fp, lr} │ │ add fp, sp, #24 │ │ @@ -1639327,16 +1639327,16 @@ │ │ add r0, sp, #12 │ │ bl 2714160 │ │ b 2583c50 │ │ ldr r0, [sp, #8] │ │ str r0, [sp, #4] │ │ add r0, sp, #4 │ │ bl 26ffb60 │ │ - stc2l 0, cr2, [fp, #188] @ 0xbc │ │ - stc2l 0, cr2, [fp, #428] @ 0x1ac │ │ + stc2l 0, cr2, [fp, #368] @ 0x170 │ │ + stc2l 0, cr2, [fp, #608] @ 0x260 │ │ │ │ 02583c68 : │ │ ldr r0, [pc, #4] @ 2583c74 │ │ add r0, pc, r0 │ │ bx lr │ │ ldrbeq r9, [r2, #1540] @ 0x604 │ │ │ │ @@ -1648881,15 +1648881,15 @@ │ │ pop {r4, r5, r6, r7, fp, pc} │ │ add r0, sp, #4 │ │ bl 2711190 │ │ bl 26ffb60 │ │ add r0, sp, #208 @ 0xd0 │ │ bl 2718a30 │ │ bl 26ffb60 │ │ - stc2l 11, cr15, [r9, #112] @ 0x70 @ │ │ + stc2l 11, cr15, [r9, #292] @ 0x124 @ │ │ andseq lr, ip, r4, lsr #24 │ │ andseq lr, ip, r0, lsl ip │ │ │ │ 0258cb04 : │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r0, [pc, #64] @ 258cb54 │ │ @@ -1649647,15 +1649647,15 @@ │ │ bl 2711190 │ │ mov r0, sl │ │ bl 2718690 │ │ bl 26ffb60 │ │ b 258d670 │ │ andseq lr, sl, ip, lsl sp │ │ andseq lr, sl, ip, lsr r8 │ │ - stc2l 3, cr7, [r9, #140] @ 0x8c │ │ + stc2l 3, cr7, [r9, #320] @ 0x140 │ │ @ instruction: 0xffad766c │ │ @ instruction: 0xffad7650 │ │ @ instruction: 0xffad7636 │ │ @ instruction: 0xffad75fc │ │ @ instruction: 0xffad75cc │ │ @ instruction: 0xffad74c2 │ │ @ instruction: 0xffad749c │ │ @@ -1657142,15 +1657142,15 @@ │ │ mov r3, #0 │ │ add r1, pc, r1 │ │ str ip, [sp] │ │ movne r1, lr │ │ bl 2711230 │ │ mov sp, fp │ │ pop {fp, pc} │ │ - stc2l 13, cr11, [r8, #964] @ 0x3c4 │ │ + stc2l 14, cr11, [r8, #120] @ 0x78 │ │ │ │ 025948a0 : │ │ ldr r3, [r2] │ │ mov ip, r0 │ │ mov r0, #0 │ │ cmp r3, #0 │ │ bxgt lr │ │ @@ -1659686,15 +1659686,15 @@ │ │ ldr r0, [r7] │ │ ldr r1, [r0, #4] │ │ mov r0, r7 │ │ blx r1 │ │ add r0, sp, #4 │ │ bl 2714160 │ │ bl 26ffb60 │ │ - stc2l 7, cr13, [r8, #172] @ 0xac │ │ + stc2l 7, cr13, [r8, #352] @ 0x160 │ │ @ instruction: 0xffacdce2 │ │ andseq r4, sl, r4, lsl #20 │ │ andseq r4, sl, r4, lsl #20 │ │ andeq r0, r0, ip, ror #2 │ │ │ │ 02596dd0 : │ │ push {r4, sl, fp, lr} │ │ @@ -1661712,16 +1661712,16 @@ │ │ mov sl, #0 │ │ mov r4, r7 │ │ b 2598b08 │ │ mov r0, r5 │ │ bl 2713d70 │ │ bl 26ffb60 │ │ stc2l 9, cr4, [fp, #130] @ 0x82 @ │ │ - stc2l 7, cr1, [r9, #256] @ 0x100 │ │ - vcadd.f16 d17, d9, d29, #270 │ │ + stc2l 7, cr1, [r9, #436] @ 0x1b4 │ │ + stc2l 8, cr1, [r9, #360] @ 0x168 │ │ │ │ 02598c6c : │ │ ldr r2, [r0, #4] │ │ mov r0, #0 │ │ cmp r2, #0 │ │ beq 2598c94 │ │ cmp r1, #16 │ │ @@ -1662399,16 +1662399,16 @@ │ │ andseq r2, sl, r4, lsl #5 │ │ andseq r2, sl, r8, lsl #5 │ │ ldrbeq r3, [r1, #3844] @ 0xf04 │ │ andeq r0, r0, ip, lsr #15 │ │ strdeq r0, [r0], -ip │ │ ldrbeq r3, [r1, #3636] @ 0xe34 │ │ ldrbeq r3, [r1, #3632] @ 0xe30 │ │ - stc2l 13, cr10, [r8, #956] @ 0x3bc │ │ - stc2l 0, cr3, [r9, #328] @ 0x148 │ │ + stc2l 14, cr10, [r8, #112] @ 0x70 │ │ + stc2l 0, cr3, [r9, #508] @ 0x1fc │ │ @ instruction: 0xffacb3ae │ │ @ instruction: 0xffacb322 │ │ ldrbeq r3, [r1, #3384] @ 0xd38 │ │ @ instruction: 0xffacb3fa │ │ ldrbeq r3, [r1, #3236] @ 0xca4 │ │ │ │ 025996ac : │ │ @@ -1663136,15 +1663136,15 @@ │ │ str r0, [r8] │ │ b 2599fa8 │ │ b 259a1e0 │ │ b 259a1e0 │ │ add r0, sp, #8 │ │ bl 2714160 │ │ bl 26ffb60 │ │ - stc2l 7, cr6, [r8, #628] @ 0x274 │ │ + stc2l 7, cr6, [r8, #808] @ 0x328 │ │ @ instruction: 0xffacab48 │ │ @ instruction: 0xffacaa8a │ │ @ instruction: 0xffacaa66 │ │ @ instruction: 0xffaca8dc │ │ @ instruction: 0xffaca75e │ │ │ │ 0259a204 : │ │ @@ -1671603,15 +1671603,15 @@ │ │ add r0, sp, #116 @ 0x74 │ │ bl 2714160 │ │ sub r0, fp, #88 @ 0x58 │ │ bl 2714160 │ │ bl 26ffb60 │ │ @ instruction: 0xffacad3e │ │ @ instruction: 0xffacad1a │ │ - stc2l 3, cr2, [r8, #604] @ 0x25c │ │ + stc2l 3, cr2, [r8, #784] @ 0x310 │ │ @ instruction: 0xffacace6 │ │ @ instruction: 0xffacacce │ │ @ instruction: 0xffacac63 │ │ andseq r9, r9, r8, lsr #10 │ │ andseq r9, r9, ip, lsr #10 │ │ @ instruction: 0x000002bc │ │ andeq r0, r0, ip, ror r3 │ │ @@ -1675230,24 +1675230,24 @@ │ │ b 25a5a7c │ │ add r0, sp, #160 @ 0xa0 │ │ bl 2714160 │ │ sub r0, fp, #96 @ 0x60 │ │ bl 2714160 │ │ bl 26ffb60 │ │ @ instruction: 0x001962b0 │ │ - stc2l 13, cr10, [r8, #332] @ 0x14c │ │ - stc2l 9, cr12, [r8, #154] @ 0x9a @ │ │ - stc2l 14, cr4, [r8, #440] @ 0x1b8 │ │ - stc2l 13, cr14, [r7, #884] @ 0x374 │ │ - stc2l 8, cr12, [r8, #324] @ 0x144 │ │ + stc2l 13, cr10, [r8, #512] @ 0x200 │ │ + stc2l 9, cr12, [r8, #244] @ 0xf4 @ │ │ + stc2l 14, cr4, [r8, #620] @ 0x26c │ │ + stc2l 14, cr14, [r7, #40] @ 0x28 │ │ + stc2l 8, cr12, [r8, #504] @ 0x1f8 │ │ stc2l 14, cr4, [r7, #412] @ 0x19c │ │ - stc2l 5, cr12, [r8, #180] @ 0xb4 │ │ + stc2l 5, cr12, [r8, #360] @ 0x168 │ │ stc2l 3, cr12, [r9, #444] @ 0x1bc │ │ - stc2l 5, cr12, [r8, #56] @ 0x38 │ │ - stc2l 6, cr8, [r7, #616] @ 0x268 │ │ + stc2l 5, cr12, [r8, #236] @ 0xec │ │ + stc2l 6, cr8, [r7, #796] @ 0x31c │ │ andseq r5, r9, ip, lsl ip │ │ │ │ 025a5ab8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ mov sl, r0 │ │ @@ -1676529,17 +1676529,17 @@ │ │ add r0, sp, #20 │ │ bl 2714160 │ │ bl 26ffb60 │ │ add r0, sp, #20 │ │ bl 2711190 │ │ bl 26ffb60 │ │ stc2l 7, cr14, [r9, #944] @ 0x3b0 │ │ - stc2l 13, cr12, [r8, #592] @ 0x250 │ │ + stc2l 13, cr12, [r8, #772] @ 0x304 │ │ stc2l 6, cr14, [r9, #592] @ 0x250 │ │ - stc2l 12, cr12, [r8, #208] @ 0xd0 │ │ + stc2l 12, cr12, [r8, #388] @ 0x184 │ │ │ │ 025a6e8c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ mov r5, r0 │ │ ldr r0, [r0, #1096] @ 0x448 │ │ @@ -1676639,17 +1676639,17 @@ │ │ asrpl r2, r0, #5 │ │ mov r0, r4 │ │ str r7, [sp, #4] │ │ bl 2714c70 │ │ cmp r8, #0 │ │ beq 25a6fd4 │ │ b 25a6fe4 │ │ - stc2l 15, cr0, [r9, #260] @ 0x104 │ │ - stc2l 6, cr5, [r8] │ │ - stc2l 5, cr5, [r8, #784] @ 0x310 │ │ + stc2l 15, cr0, [r9, #440] @ 0x1b8 │ │ + stc2l 6, cr5, [r8, #180] @ 0xb4 │ │ + stc2l 5, cr5, [r8, #964] @ 0x3c4 │ │ │ │ 025a703c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ mov r5, r0 │ │ ldr r0, [r0, #1096] @ 0x448 │ │ @@ -1676749,17 +1676749,17 @@ │ │ asrpl r2, r0, #5 │ │ mov r0, r4 │ │ str r7, [sp, #4] │ │ bl 2714c70 │ │ cmp r8, #0 │ │ beq 25a7184 │ │ b 25a7194 │ │ - stc2l 15, cr6, [r7, #400] @ 0x190 │ │ - stc2l 1, cr3, [r8, #972] @ 0x3cc │ │ - stc2l 1, cr3, [r8, #732] @ 0x2dc │ │ + stc2l 15, cr6, [r7, #580] @ 0x244 │ │ + stc2l 2, cr3, [r8, #128] @ 0x80 │ │ + stc2l 1, cr3, [r8, #912] @ 0x390 │ │ │ │ 025a71ec : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #24 │ │ mov r4, r1 │ │ ldrh r1, [r1, #4] │ │ @@ -1676909,16 +1676909,16 @@ │ │ strd r8, [sp] │ │ asrpl r2, r0, #5 │ │ mov r0, r4 │ │ bl 2714c70 │ │ cmp r6, #0 │ │ beq 25a73f0 │ │ b 25a7400 │ │ - stc2l 11, cr6, [r8, #284] @ 0x11c @ │ │ - stc2l 11, cr6, [r8, #60] @ 0x3c @ │ │ + stc2l 11, cr6, [r8, #464] @ 0x1d0 @ │ │ + stc2l 11, cr6, [r8, #240] @ 0xf0 @ │ │ │ │ 025a7450 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #84 @ 0x54 │ │ mov r7, r1 │ │ ldr r1, [pc, #640] @ 25a76e8 │ │ @@ -1677079,18 +1677079,18 @@ │ │ bl 2714c70 │ │ cmp r9, #0 │ │ beq 25a767c │ │ b 25a768c │ │ add r0, sp, #16 │ │ bl 2714160 │ │ bl 26ffb60 │ │ - stc2l 11, cr4, [r7, #136] @ 0x88 @ │ │ + stc2l 11, cr4, [r7, #316] @ 0x13c @ │ │ stc2l 15, cr3, [sl, #588] @ 0x24c │ │ - stc2l 8, cr0, [r9, #108] @ 0x6c │ │ - stc2l 7, cr0, [r9, #892] @ 0x37c │ │ + vcadd.f16 q8, , q4, #270 │ │ + vcadd.f16 d16, d9, d12, #270 │ │ │ │ 025a76f8 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #208 @ 0xd0 │ │ add r6, sp, #4 │ │ mov r5, r0 │ │ @@ -1677333,17 +1677333,17 @@ │ │ bl 2714160 │ │ bl 26ffb60 │ │ add r0, sp, #12 │ │ bl 2711190 │ │ bl 26ffb60 │ │ stc2l 6, cr2, [r9, #248] @ 0xf8 │ │ stc2l 11, cr13, [r9, #560] @ 0x230 @ │ │ - stc2l 1, cr12, [r8, #240] @ 0xf0 │ │ + stc2l 1, cr12, [r8, #420] @ 0x1a4 │ │ stc2l 10, cr13, [r9, #384] @ 0x180 @ │ │ - stc2l 15, cr11, [r8, #992] @ 0x3e0 │ │ + stc2l 0, cr12, [r8, #148] @ 0x94 │ │ │ │ 025a7adc : │ │ mov r3, #0 │ │ b 27110c0 │ │ │ │ 025a7ae4 : │ │ push {r4, r5, fp, lr} │ │ @@ -1678139,18 +1678139,18 @@ │ │ addne r0, r1, r7 │ │ movne r1, #1 │ │ strbne r1, [r0, #1104] @ 0x450 │ │ strbne r1, [r5, #4] │ │ b 25a8564 │ │ stc2l 2, cr2, [r9, #276] @ 0x114 │ │ stc2l 10, cr1, [r9, #288] @ 0x120 @ │ │ - stc2l 4, cr11, [r8, #160] @ 0xa0 │ │ + stc2l 4, cr11, [r8, #340] @ 0x154 │ │ stc2l 4, cr9, [r9, #864] @ 0x360 │ │ - stc2l 11, cr9, [r7, #508] @ 0x1fc @ │ │ - stc2l 13, cr15, [r7, #592] @ 0x250 │ │ + stc2l 11, cr9, [r7, #688] @ 0x2b0 @ │ │ + stc2l 13, cr15, [r7, #772] @ 0x304 │ │ │ │ 025a86c0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #564 @ 0x234 │ │ mov r9, r0 │ │ add r0, sp, #244 @ 0xf4 │ │ @@ -1678331,15 +1678331,15 @@ │ │ b 25a8998 │ │ b 25a8998 │ │ b 25a8998 │ │ add r0, sp, #244 @ 0xf4 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ stc2l 12, cr0, [sl, #188] @ 0xbc │ │ - stc2l 10, cr9, [r8, #112] @ 0x70 @ │ │ + stc2l 10, cr9, [r8, #292] @ 0x124 @ │ │ stc2l 11, cr0, [sl, #44] @ 0x2c @ │ │ stc2l 2, cr15, [r9, #172] @ 0xac │ │ │ │ 025a89b4 : │ │ mov r2, r1 │ │ mov r1, #1 │ │ b 2710450 │ │ @@ -1678414,15 +1678414,15 @@ │ │ pop {r4, r5, r6, r7, fp, lr} │ │ b 2710460 │ │ b 25a8ad4 │ │ add r0, sp, #12 │ │ bl 2711190 │ │ bl 26ffb60 │ │ ldrbeq r4, [r0, #2408] @ 0x968 │ │ - stc2l 12, cr7, [r7, #324] @ 0x144 │ │ + stc2l 12, cr7, [r7, #504] @ 0x1f8 │ │ ldrbeq r4, [r0, #2332] @ 0x91c │ │ │ │ 025a8aec : │ │ mov r2, r1 │ │ mov r1, #2 │ │ b 2710450 │ │ │ │ @@ -1678942,27 +1678942,27 @@ │ │ b 25a9280 │ │ b 25a9280 │ │ add r0, sp, #112 @ 0x70 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ stc2l 1, cr1, [r9, #628] @ 0x274 │ │ stc2l 14, cr5, [sl, #572] @ 0x23c │ │ - stc2l 12, cr14, [r8, #872] @ 0x368 │ │ + stc2l 13, cr14, [r8, #28] │ │ andseq r2, r9, r8, lsl r6 │ │ stc2l 7, cr15, [r6, #880] @ 0x370 │ │ stc2l 14, cr10, [r9, #156] @ 0x9c │ │ stc2l 12, cr6, [r9, #980] @ 0x3d4 │ │ stc2l 13, cr7, [sl, #752] @ 0x2f0 │ │ stc2l 2, cr0, [sl, #108] @ 0x6c │ │ - stc2l 14, cr14, [r8, #20] │ │ + stc2l 14, cr14, [r8, #200] @ 0xc8 │ │ andseq r2, r9, r0, ror r4 │ │ stc2l 9, cr14, [r9, #486] @ 0x1e6 @ │ │ - stc2l 0, cr7, [r8, #164] @ 0xa4 │ │ + stc2l 0, cr7, [r8, #344] @ 0x158 │ │ stc2l 2, cr4, [sl, #52] @ 0x34 │ │ - stc2l 10, cr12, [r8, #244] @ 0xf4 @ │ │ + stc2l 10, cr12, [r8, #424] @ 0x1a8 @ │ │ stc2l 2, cr6, [sl, #320] @ 0x140 │ │ │ │ 025a92cc : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #16 │ │ cmp r2, #2 │ │ @@ -1682653,15 +1682653,15 @@ │ │ mov r2, #4 │ │ mov r3, r1 │ │ str r9, [sp] │ │ blx r7 │ │ ldr r6, [sp, #24] │ │ b 25ac664 │ │ stc2l 5, cr5, [r9, #40] @ 0x28 │ │ - stc2l 4, cr9, [r8, #808] @ 0x328 │ │ + stc2l 4, cr9, [r8, #988] @ 0x3dc │ │ vcadd.f16 , q4, q13, #270 │ │ │ │ 025aca74 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ ldr r4, [fp, #12] │ │ @@ -1706639,15 +1706639,15 @@ │ │ add r0, sp, #92 @ 0x5c │ │ bl 2714160 │ │ sub r0, fp, #100 @ 0x64 │ │ bl 2714160 │ │ bl 26ffb60 │ │ stc2l 1, cr3, [r9, #232] @ 0xe8 │ │ andseq r8, r7, r0, ror r0 │ │ - stc2l 12, cr8, [r6, #984] @ 0x3d8 │ │ + stc2l 13, cr8, [r6, #140] @ 0x8c │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r0, [pc, #60] @ 25c37d4 │ │ ldr r0, [pc, r0] │ │ cmp r0, #0 │ │ beq 25c37a8 │ │ bl 2714600 │ │ @@ -1708424,16 +1708424,16 @@ │ │ mov r0, #0 │ │ cmp r1, #1 │ │ movwlt r0, #1 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ strbeq r8, [lr, #1652] @ 0x674 │ │ strbeq r8, [lr, #1628] @ 0x65c │ │ - stc2l 13, cr8, [r6, #688] @ 0x2b0 │ │ - stc2l 0, cr11, [r6, #376] @ 0x178 │ │ + stc2l 13, cr8, [r6, #868] @ 0x364 │ │ + stc2l 0, cr11, [r6, #556] @ 0x22c │ │ andeq r1, r0, r0, ror #4 │ │ strbeq r8, [lr, #1568] @ 0x620 │ │ strbeq r8, [lr, #1428] @ 0x594 │ │ strbeq r8, [lr, #1380] @ 0x564 │ │ strbeq r8, [lr, #1332] @ 0x534 │ │ strbeq r8, [lr, #1320] @ 0x528 │ │ strbeq r8, [lr, #1312] @ 0x520 │ │ @@ -1709872,15 +1709872,15 @@ │ │ addgt r1, r0, r2 │ │ cmp ip, lr │ │ addgt r6, r0, lr │ │ str r1, [r4, #24] │ │ str r6, [r4, #28] │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - stc2l 6, cr7, [r6, #960] @ 0x3c0 │ │ + stc2l 7, cr7, [r6, #116] @ 0x74 │ │ stc2l 2, cr1, [r8, #856] @ 0x358 │ │ andseq r4, r7, r8, asr #26 │ │ │ │ 025c68f4 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #16 │ │ @@ -1711886,15 +1711886,15 @@ │ │ cmp r0, #1 │ │ strge r0, [r5] │ │ ldr r0, [pc, #16] @ 25c876c │ │ ldr r0, [pc, r0] │ │ pop {r4, r5, r6, sl, fp, pc} │ │ strbeq r5, [lr, #144] @ 0x90 │ │ strbeq r5, [lr, #120] @ 0x78 │ │ - stc2l 11, cr7, [r5, #812] @ 0x32c @ │ │ + stc2l 11, cr7, [r5, #992] @ 0x3e0 @ │ │ strbeq r5, [lr, #32] │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r1 │ │ ldr r1, [pc, #524] @ 25c8990 │ │ mov r5, r0 │ │ add r1, pc, r1 │ │ @@ -1712024,17 +1712024,17 @@ │ │ b 25c894c │ │ mov r0, #7 │ │ str r0, [r4] │ │ ldr r0, [pc, #32] @ 25c89a8 │ │ add r0, pc, r0 │ │ b 25c894c │ │ bl 2707fc0 │ │ - stc2l 11, cr7, [r5, #460] @ 0x1cc @ │ │ + stc2l 11, cr7, [r5, #640] @ 0x280 @ │ │ strbeq r4, [lr, #3592] @ 0xe08 │ │ - stc2l 10, cr7, [r5, #540] @ 0x21c @ │ │ + stc2l 10, cr7, [r5, #720] @ 0x2d0 @ │ │ andseq r2, r7, ip, asr #25 │ │ strbeq r4, [lr, #3780] @ 0xec4 │ │ vcadd.f16 d17, d23, d25, #270 │ │ strbeq r4, [lr, #3576] @ 0xdf8 │ │ stc2l 7, cr1, [r7, #340] @ 0x154 │ │ andseq r2, r7, ip, asr #24 │ │ strbeq r4, [lr, #3656] @ 0xe48 │ │ @@ -1712161,15 +1712161,15 @@ │ │ ldr r0, [pc, #24] @ 25c8ba0 │ │ ldr r0, [pc, r0] │ │ cmp r0, #0 │ │ addne r0, r0, #4 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ strbeq r4, [lr, #3172] @ 0xc64 │ │ strbeq r4, [lr, #3148] @ 0xc4c │ │ - stc2l 7, cr7, [r5, #636] @ 0x27c │ │ + stc2l 7, cr7, [r5, #816] @ 0x330 │ │ strbeq r4, [lr, #3060] @ 0xbf4 │ │ │ │ 025c8ba4 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ ldr r2, [r0] │ │ mov r5, r0 │ │ @@ -1712203,15 +1712203,15 @@ │ │ ldr r0, [pc, #24] @ 25c8c40 │ │ ldr r0, [pc, r0] │ │ cmp r0, #0 │ │ addne r0, r0, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ strbeq r4, [lr, #3012] @ 0xbc4 │ │ strbeq r4, [lr, #2988] @ 0xbac │ │ - stc2l 6, cr7, [r5, #1020] @ 0x3fc │ │ + stc2l 7, cr7, [r5, #176] @ 0xb0 │ │ strbeq r4, [lr, #2900] @ 0xb54 │ │ │ │ 025c8c44 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ ldr r2, [r0] │ │ mov r5, r0 │ │ @@ -1712497,16 +1712497,16 @@ │ │ bl 2710e30 │ │ bl 26ffb60 │ │ mov r0, #0 │ │ bl 2713dc0 │ │ bl 26ffb60 │ │ blx 207deaa │ │ blx 207deaa │ │ - stc2l 15, cr14, [r6, #928] @ 0x3a0 │ │ - stc2l 4, cr7, [r5, #588] @ 0x24c │ │ + stc2l 0, cr15, [r6, #84] @ 0x54 │ │ + stc2l 4, cr7, [r5, #768] @ 0x300 │ │ stc2l 1, cr1, [r7, #804] @ 0x324 │ │ stc2l 0, cr8, [r8, #436] @ 0x1b4 │ │ strbeq r4, [lr, #2468] @ 0x9a4 │ │ andeq r0, r0, r0, ror #5 │ │ strbeq r4, [lr, #2236] @ 0x8bc │ │ andseq r2, r7, r4, lsr r7 │ │ andseq r2, r7, r8, lsr r7 │ │ @@ -1712680,19 +1712680,19 @@ │ │ ldr r0, [pc, #24] @ 25c9394 │ │ ldr r0, [pc, r0] │ │ cmp r0, #0 │ │ addne r0, r0, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ strbeq r4, [lr, #1188] @ 0x4a4 │ │ strbeq r4, [lr, #1160] @ 0x488 │ │ - stc2l 15, cr6, [r5, #860] @ 0x35c │ │ + stc2l 0, cr7, [r5, #16] │ │ strbeq r4, [lr, #1024] @ 0x400 │ │ strbeq r4, [lr, #1280] @ 0x500 │ │ strbeq r4, [lr, #1252] @ 0x4e4 │ │ - stc2l 0, cr7, [r5, #204] @ 0xcc │ │ + stc2l 0, cr7, [r5, #384] @ 0x180 │ │ strbeq r4, [lr, #1056] @ 0x420 │ │ │ │ 025c93a8 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ ldr r1, [r0] │ │ mov r4, r0 │ │ @@ -1712730,15 +1712730,15 @@ │ │ ldr r1, [pc, #24] @ 25c9454 │ │ ldr r1, [pc, r1] │ │ cmp r1, #0 │ │ ldrne r0, [r1] │ │ pop {r4, r5, r6, sl, fp, pc} │ │ strbeq r4, [lr, #956] @ 0x3bc │ │ strbeq r4, [lr, #932] @ 0x3a4 │ │ - stc2l 14, cr6, [r5, #956] @ 0x3bc │ │ + stc2l 15, cr6, [r5, #112] @ 0x70 │ │ strbeq r4, [lr, #832] @ 0x340 │ │ │ │ 025c9458 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ ldr r1, [r0] │ │ mov r4, r0 │ │ @@ -1712818,15 +1712818,15 @@ │ │ ldr r0, [pc, #24] @ 25c95a4 │ │ ldr r0, [pc, r0] │ │ cmp r0, #0 │ │ addne r0, r0, #4 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ strbeq r4, [lr, #608] @ 0x260 │ │ strbeq r4, [lr, #584] @ 0x248 │ │ - stc2l 13, cr6, [r5, #620] @ 0x26c │ │ + stc2l 13, cr6, [r5, #800] @ 0x320 │ │ strbeq r4, [lr, #496] @ 0x1f0 │ │ │ │ 025c95a8 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ ldr r2, [r0] │ │ mov r5, r0 │ │ @@ -1712860,15 +1712860,15 @@ │ │ ldr r0, [pc, #24] @ 25c9644 │ │ ldr r0, [pc, r0] │ │ cmp r0, #0 │ │ addne r0, r0, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ strbeq r4, [lr, #448] @ 0x1c0 │ │ strbeq r4, [lr, #424] @ 0x1a8 │ │ - stc2l 12, cr6, [r5, #1004] @ 0x3ec │ │ + stc2l 13, cr6, [r5, #160] @ 0xa0 │ │ strbeq r4, [lr, #336] @ 0x150 │ │ │ │ 025c9648 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ ldr r2, [r0] │ │ mov r5, r0 │ │ @@ -1721696,16 +1721696,16 @@ │ │ sub r2, r0, r6 │ │ mov r0, r4 │ │ str r8, [sp] │ │ blx ip │ │ ldr r0, [sp, #24] │ │ add r1, sl, r0 │ │ b 25d1c90 │ │ - stc2l 5, cr0, [r5, #648] @ 0x288 │ │ - stc2l 1, cr12, [r5, #976] @ 0x3d0 │ │ + stc2l 5, cr0, [r5, #828] @ 0x33c │ │ + stc2l 2, cr12, [r5, #132] @ 0x84 │ │ stc2l 6, cr9, [r7, #860] @ 0x35c │ │ │ │ 025d1e1c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ mov r4, r0 │ │ @@ -1729613,15 +1729613,15 @@ │ │ movw r0, #65535 @ 0xffff │ │ tst r2, r0 │ │ movne r0, #62 @ 0x3e │ │ strbne r0, [r8, r6] │ │ add r0, ip, r6 │ │ uxth r0, r0 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - stc2l 6, cr7, [r4, #152] @ 0x98 │ │ + stc2l 6, cr7, [r4, #332] @ 0x14c │ │ andseq r7, r5, r0, lsr #6 │ │ │ │ 025d9694 : │ │ cmp r3, #0 │ │ beq 25d96a8 │ │ ldr r0, [r3] │ │ cmp r0, #0 │ │ @@ -1730025,15 +1730025,15 @@ │ │ b 25d9788 │ │ ldr r2, [sp, #64] @ 0x40 │ │ cmp r8, r4 │ │ bne 25d9788 │ │ b 25d9790 │ │ @ instruction: 0x00156bb8 │ │ strbeq r3, [sp, #3908] @ 0xf44 │ │ - stc2l 13, cr6, [r4, #852] @ 0x354 │ │ + stc2l 14, cr6, [r4, #8] │ │ strbeq r3, [sp, #3060] @ 0xbf4 │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ movw r1, #64976 @ 0xfdd0 │ │ cmp r0, r1 │ │ blt 25d9d3c │ │ movw r1, #65008 @ 0xfdf0 │ │ @@ -1731040,15 +1731040,15 @@ │ │ mov r0, #1 │ │ b 25daca8 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ bx lr │ │ strbeq r3, [sp] │ │ - stc2l 2, cr9, [r5, #128] @ 0x80 │ │ + stc2l 2, cr9, [r5, #308] @ 0x134 │ │ strbeq r2, [sp, #4040] @ 0xfc8 │ │ strbeq r2, [sp, #3980] @ 0xf8c │ │ andseq r5, r5, ip, ror lr │ │ strbeq r2, [sp, #3384] @ 0xd38 │ │ strbeq r2, [sp, #2856] @ 0xb28 │ │ │ │ 025dacd0 : │ │ @@ -1731562,19 +1731562,19 @@ │ │ ldr r1, [pc, #32] @ 25db4dc │ │ mov r0, r4 │ │ ldr r2, [sp, #52] @ 0x34 │ │ add r1, pc, r1 │ │ bl 2713760 │ │ b 25dae94 │ │ stc2l 0, cr6, [r7, #984] @ 0x3d8 │ │ - stc2l 3, cr11, [r4, #428] @ 0x1ac │ │ + stc2l 3, cr11, [r4, #608] @ 0x260 │ │ stc2l 13, cr5, [r7, #816] @ 0x330 │ │ stc2l 7, cr6, [r6, #640] @ 0x280 │ │ stc2l 10, cr8, [r3, #452] @ 0x1c4 @ │ │ - stc2l 11, cr10, [r5, #356] @ 0x164 @ │ │ + stc2l 11, cr10, [r5, #536] @ 0x218 @ │ │ stc2l 14, cr13, [r6, #748] @ 0x2ec │ │ nop {0} │ │ nop {0} │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #276 @ 0x114 │ │ mov r7, r0 │ │ @@ -1737482,15 +1737482,15 @@ │ │ b 25e0e10 │ │ add r0, sp, #88 @ 0x58 │ │ bl 27103d0 │ │ sub r0, fp, #88 @ 0x58 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ stc2l 7, cr8, [r6, #908] @ 0x38c │ │ - stc2l 11, cr15, [r3, #4] @ │ │ + stc2l 11, cr15, [r3, #184] @ 0xb8 @ │ │ stc2l 7, cr5, [r3, #284] @ 0x11c │ │ stc2l 6, cr8, [r6, #588] @ 0x24c │ │ andseq sl, r5, r4, asr #16 │ │ andseq sl, r5, r8, lsr #16 │ │ @ instruction: 0x0015a7f0 │ │ @ instruction: 0x0015a7dc │ │ andseq sl, r5, r4, lsr #15 │ │ @@ -1739688,15 +1739688,15 @@ │ │ b 25e2f88 │ │ b 25e2f88 │ │ b 25e2f88 │ │ mov r0, r4 │ │ bl 2714160 │ │ bl 26ffb60 │ │ stc2l 4, cr6, [r6, #604] @ 0x25c │ │ - stc2l 7, cr13, [r3, #724] @ 0x2d4 │ │ + stc2l 7, cr13, [r3, #904] @ 0x388 │ │ stc2l 0, cr14, [r6, #860] @ 0x35c │ │ andseq r8, r5, r0, asr #15 │ │ │ │ 025e2fa4 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #128 @ 0x80 │ │ @@ -1744866,16 +1744866,16 @@ │ │ b 25e7cd0 │ │ ldr r1, [pc, #24] @ 25e7e48 │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 2713760 │ │ b 25e7cc4 │ │ stc2l 9, cr5, [r6, #192] @ 0xc0 @ │ │ - stc2l 5, cr8, [r3, #944] @ 0x3b0 │ │ - stc2l 4, cr14, [r3, #552] @ 0x228 │ │ + stc2l 6, cr8, [r3, #100] @ 0x64 │ │ + stc2l 4, cr14, [r3, #732] @ 0x2dc │ │ stc2l 12, cr15, [r5, #628] @ 0x274 │ │ │ │ 025e7e4c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #12 │ │ mov r0, #0 │ │ @@ -1745202,17 +1745202,17 @@ │ │ bl 27128e0 │ │ add r0, sp, #4 │ │ bl 2710d40 │ │ bl 26ffb60 │ │ strbeq r5, [ip, #1472] @ 0x5c0 │ │ strbeq r5, [ip, #1448] @ 0x5a8 │ │ muleq r0, r0, r1 │ │ - stc2l 12, cr3, [r3, #752] @ 0x2f0 │ │ + stc2l 12, cr3, [r3, #932] @ 0x3a4 │ │ andseq r8, r4, r8, asr sl │ │ - stc2l 3, cr8, [r3, #596] @ 0x254 │ │ + stc2l 3, cr8, [r3, #776] @ 0x308 │ │ │ │ 025e836c : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r6, r0 │ │ ldr r0, [r1] │ │ cmp r0, #0 │ │ @@ -1745395,15 +1745395,15 @@ │ │ b 25e8548 │ │ mov r0, #7 │ │ str r0, [r8] │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ strbeq r5, [ip, #744] @ 0x2e8 │ │ stc2l 13, cr12, [r5, #548] @ 0x224 │ │ - vcadd.f16 d31, d20, d24, #270 │ │ + stc2l 8, cr15, [r4, #852] @ 0x354 │ │ strbeq r5, [ip, #584] @ 0x248 │ │ push {fp, lr} │ │ mov fp, sp │ │ bl 2713f30 │ │ pop {fp, lr} │ │ b 2713d70 │ │ ldr r1, [r1] │ │ @@ -1745574,15 +1745574,15 @@ │ │ @ instruction: 0x001485b4 │ │ andseq r8, r4, r4, lsl r6 │ │ andseq r8, r4, r0, lsr #12 │ │ andseq r8, r4, r4, lsl #13 │ │ @ instruction: 0x001486f0 │ │ andseq r8, r4, r0, lsl r7 │ │ andseq r8, r4, r0, asr r7 │ │ - stc2l 5, cr15, [r4, #532] @ 0x214 │ │ + stc2l 5, cr15, [r4, #712] @ 0x2c8 │ │ andseq r8, r4, ip, asr #14 │ │ │ │ 025e88f8 : │ │ b 2715a70 │ │ │ │ 025e88fc : │ │ push {r4, sl, fp, lr} │ │ @@ -1746532,16 +1746532,16 @@ │ │ bl 2713e00 │ │ bl 26ffb60 │ │ andseq r2, r5, r4, lsr r1 │ │ andseq r2, r5, r8, ror r2 │ │ andseq r2, r5, r4, ror r2 │ │ andseq r2, r5, r8, lsl #2 │ │ stc2l 14, cr15, [r5, #860] @ 0x35c │ │ - stc2l 15, cr10, [r3, #412] @ 0x19c │ │ - stc2l 5, cr10, [r4, #908] @ 0x38c │ │ + stc2l 15, cr10, [r3, #592] @ 0x250 │ │ + stc2l 6, cr10, [r4, #64] @ 0x40 │ │ andseq r2, r5, ip, lsr #3 │ │ │ │ 025e9724 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r2 │ │ ldr r2, [r2] │ │ @@ -1750559,15 +1750559,15 @@ │ │ ldr r0, [sp, #12] │ │ cmp r0, #0 │ │ beq 25ed308 │ │ ldr r1, [r0] │ │ ldr r1, [r1, #4] │ │ blx r1 │ │ bl 26ffb60 │ │ - stc2l 4, cr3, [r3, #68] @ 0x44 │ │ + stc2l 4, cr3, [r3, #248] @ 0xf8 │ │ andseq lr, r4, r4, asr r4 │ │ │ │ 025ed314 : │ │ mov r3, #0 │ │ b 2715060 │ │ │ │ 025ed31c : │ │ @@ -1751612,25 +1751612,25 @@ │ │ b 25ee254 │ │ b 25ee254 │ │ add r0, sp, #76 @ 0x4c │ │ bl 27103d0 │ │ sub r0, fp, #88 @ 0x58 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - stc2l 1, cr14, [r2, #424] @ 0x1a8 │ │ + stc2l 1, cr14, [r2, #604] @ 0x25c │ │ strbeq pc, [fp, #2432] @ 0x980 @ │ │ ldrdeq r3, [r0], -r8 │ │ strbeq pc, [fp, #2408] @ 0x968 @ │ │ strbeq pc, [fp, #2344] @ 0x928 @ │ │ - stc2l 5, cr10, [r3, #308] @ 0x134 │ │ + stc2l 5, cr10, [r3, #488] @ 0x1e8 │ │ @ instruction: 0xffa886f4 │ │ @ instruction: 0xffa886f1 │ │ stc2l 13, cr13, [r4, #828] @ 0x33c │ │ stc2l 10, cr9, [r6, #848] @ 0x350 @ │ │ - stc2l 7, cr5, [r4, #788] @ 0x314 │ │ + stc2l 7, cr5, [r4, #968] @ 0x3c8 │ │ │ │ 025ee28c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #164 @ 0xa4 │ │ ldr r6, [fp, #12] │ │ mov sl, r0 │ │ @@ -1751804,19 +1751804,19 @@ │ │ add r0, sp, #40 @ 0x28 │ │ bl 27103d0 │ │ add r0, sp, #96 @ 0x60 │ │ bl 2710d40 │ │ sub r0, fp, #88 @ 0x58 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - stc2l 1, cr10, [r3, #916] @ 0x394 │ │ + stc2l 2, cr10, [r3, #72] @ 0x48 │ │ @ instruction: 0xffa882d8 │ │ @ instruction: 0xffa8828c │ │ @ instruction: 0xffa882b2 │ │ - stc2l 13, cr0, [r3, #612] @ 0x264 │ │ + stc2l 13, cr0, [r3, #792] @ 0x318 │ │ @ instruction: 0xffa8821f │ │ │ │ 025ee570 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #76 @ 0x4c │ │ ldr sl, [fp, #12] │ │ @@ -1751914,17 +1751914,17 @@ │ │ cmn r1, #127 @ 0x7f │ │ strne r0, [sl] │ │ b 25ee5c4 │ │ b 25ee6fc │ │ add r0, sp, #16 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - stc2l 15, cr9, [r3, #36] @ 0x24 │ │ + stc2l 15, cr9, [r3, #216] @ 0xd8 │ │ @ instruction: 0xffa88066 │ │ - stc2l 13, cr13, [r2, #380] @ 0x17c │ │ + stc2l 13, cr13, [r2, #560] @ 0x230 │ │ │ │ 025ee714 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #468 @ 0x1d4 │ │ ldr r5, [fp, #16] │ │ mov r4, r0 │ │ @@ -1753003,22 +1753003,22 @@ │ │ strbeq lr, [fp, #3716] @ 0xe84 │ │ strbeq lr, [fp, #3676] @ 0xe5c │ │ strbeq lr, [fp, #3636] @ 0xe34 │ │ strbeq lr, [fp, #3596] @ 0xe0c │ │ strbeq lr, [fp, #3556] @ 0xde4 │ │ strbeq lr, [fp, #3516] @ 0xdbc │ │ strbeq lr, [fp, #3532] @ 0xdcc │ │ - stc2l 9, cr9, [r3, #242] @ 0xf2 @ │ │ + stc2l 9, cr9, [r3, #332] @ 0x14c @ │ │ @ instruction: 0xffa87acb │ │ @ instruction: 0xffa8795e │ │ andseq ip, r4, r8, ror r8 │ │ andseq ip, r4, ip, ror r8 │ │ andseq ip, r4, r8, asr r8 │ │ andseq ip, r4, ip, asr r8 │ │ - stc2l 6, cr9, [r3, #708] @ 0x2c4 │ │ + stc2l 6, cr9, [r3, #888] @ 0x378 │ │ @ instruction: 0xffa87803 │ │ @ instruction: 0xffa874da │ │ andeq r2, r0, r4, ror #19 │ │ andeq r2, r0, ip, asr #19 │ │ strbeq lr, [fp, #1176] @ 0x498 │ │ strbeq lr, [fp, #1108] @ 0x454 │ │ strbeq lr, [fp, #336] @ 0x150 │ │ @@ -1753474,15 +1753474,15 @@ │ │ bl 2713e90 │ │ mov r0, r6 │ │ bl 2713e90 │ │ mov r0, r4 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ @ instruction: 0xffa86920 │ │ - stc2l 7, cr8, [r3, #20] │ │ + stc2l 7, cr8, [r3, #200] @ 0xc8 │ │ @ instruction: 0xffa868b0 │ │ @ instruction: 0xffa868f4 │ │ @ instruction: 0xffa868c0 │ │ @ instruction: 0xffa8686d │ │ @ instruction: 0xffa86800 │ │ │ │ 025eff58 : │ │ @@ -1753842,20 +1753842,20 @@ │ │ svcvc 0x00efffff │ │ strbeq sp, [fp, #2020] @ 0x7e4 │ │ strbeq sp, [fp, #1992] @ 0x7c8 │ │ strheq r1, [r0], -r8 │ │ andseq fp, r4, ip, asr #10 │ │ andseq fp, r4, r0, asr r5 │ │ andeq r1, r0, r4, asr #25 │ │ - stc2l 3, cr8, [r3, #692] @ 0x2b4 │ │ + stc2l 3, cr8, [r3, #872] @ 0x368 │ │ @ instruction: 0xffa86558 │ │ @ instruction: 0xffa86551 │ │ - stc2l 5, cr3, [r4, #180] @ 0xb4 │ │ - stc2l 7, cr0, [r3, #268] @ 0x10c │ │ - stc2l 6, cr8, [r3, #204] @ 0xcc │ │ + stc2l 5, cr3, [r4, #360] @ 0x168 │ │ + stc2l 7, cr0, [r3, #448] @ 0x1c0 │ │ + stc2l 6, cr8, [r3, #384] @ 0x180 │ │ strbeq sp, [fp, #1656] @ 0x678 │ │ strbeq sp, [fp, #1160] @ 0x488 │ │ strbeq sp, [fp, #1696] @ 0x6a0 │ │ strbeq sp, [fp, #988] @ 0x3dc │ │ │ │ 025f0510 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ @@ -1754068,19 +1754068,19 @@ │ │ b 25f0854 │ │ b 25f0854 │ │ b 25f0854 │ │ b 25f0854 │ │ add r0, sp, #12 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - stc2l 14, cr7, [r3, #724] @ 0x2d4 │ │ + stc2l 14, cr7, [r3, #904] @ 0x388 │ │ @ instruction: 0xffa86060 │ │ @ instruction: 0xffa8605d │ │ - stc2l 3, cr0, [r3, #348] @ 0x15c │ │ - stc2l 2, cr8, [r3, #300] @ 0x12c │ │ + stc2l 3, cr0, [r3, #528] @ 0x210 │ │ + stc2l 2, cr8, [r3, #480] @ 0x1e0 │ │ │ │ 025f0874 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8-d9} │ │ sub sp, sp, #88 @ 0x58 │ │ @@ -1754308,20 +1754308,20 @@ │ │ b 25f0c0c │ │ b 25f0c0c │ │ b 25f0c0c │ │ b 25f0c0c │ │ add r0, sp, #24 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - stc2l 11, cr7, [r3, #852] @ 0x354 @ │ │ + stc2l 12, cr7, [r3, #8] │ │ @ instruction: 0xffa85d80 │ │ @ instruction: 0xffa85d7d │ │ - stc2l 13, cr2, [r4, #708] @ 0x2c4 │ │ - stc2l 15, cr15, [r2, #844] @ 0x34c │ │ - stc2l 14, cr7, [r3, #828] @ 0x33c │ │ + stc2l 13, cr2, [r4, #888] @ 0x378 │ │ + stc2l 0, cr0, [r3] │ │ + stc2l 14, cr7, [r3, #1008] @ 0x3f0 │ │ │ │ 025f0c30 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #548 @ 0x224 │ │ mov r4, r0 │ │ sub r0, fp, #88 @ 0x58 │ │ @@ -1754610,19 +1754610,19 @@ │ │ b 25f10b8 │ │ b 25f10b8 │ │ b 25f10b8 │ │ sub r0, fp, #88 @ 0x58 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ andseq r0, r4, ip, ror r7 │ │ - vcadd.f16 , , , #270 │ │ + vcadd.f16 , , q15, #270 │ │ @ instruction: 0xffa859ec │ │ @ instruction: 0xffa859dd │ │ - stc2l 9, cr2, [r4, #154] @ 0x9a @ │ │ - stc2l 10, cr7, [r3, #796] @ 0x31c @ │ │ + stc2l 9, cr2, [r4, #244] @ 0xf4 @ │ │ + stc2l 10, cr7, [r3, #976] @ 0x3d0 @ │ │ stc2l 12, cr10, [r4, #248] @ 0xf8 │ │ │ │ 025f10e0 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r4, #0 │ │ @@ -1754671,15 +1754671,15 @@ │ │ cmp r0, #0 │ │ movwgt r4, #0 │ │ mov r0, r5 │ │ bl 2713e90 │ │ mov r0, r4 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - stc2l 2, cr5, [r3, #288] @ 0x120 │ │ + stc2l 2, cr5, [r3, #468] @ 0x1d4 │ │ stc2l 8, cr2, [r5, #832] @ 0x340 │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ ldr r0, [pc, #440] @ 25f1384 │ │ ldr r0, [pc, r0] │ │ cmp r0, #0 │ │ beq 25f11f8 │ │ @@ -1756788,27 +1756788,27 @@ │ │ ldr r0, [fp, #-36] @ 0xffffffdc │ │ str r0, [sp, #12] │ │ add r0, sp, #12 │ │ bl 26ffb60 │ │ add r0, sp, #16 │ │ bl 2714160 │ │ bl 26ffb60 │ │ - stc2l 9, cr5, [r3, #198] @ 0xc6 @ │ │ - stc2l 1, cr15, [r3, #648] @ 0x288 │ │ + stc2l 9, cr5, [r3, #288] @ 0x120 @ │ │ + stc2l 1, cr15, [r3, #828] @ 0x33c │ │ strbeq sl, [fp, #2904] @ 0xb58 │ │ strbeq sl, [fp, #2804] @ 0xaf4 │ │ strbeq sl, [fp, #2712] @ 0xa98 │ │ strbeq sl, [fp, #2620] @ 0xa3c │ │ strbeq sl, [fp, #2528] @ 0x9e0 │ │ strbeq sl, [fp, #2436] @ 0x984 │ │ strbeq sl, [fp, #2344] @ 0x928 │ │ strbeq sl, [fp, #2252] @ 0x8cc │ │ strbeq sl, [fp, #2160] @ 0x870 │ │ strbeq sl, [fp, #2068] @ 0x814 │ │ - stc2l 9, cr5, [r3, #150] @ 0x96 @ │ │ + stc2l 9, cr5, [r3, #240] @ 0xf0 @ │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ mov r0, #152 @ 0x98 │ │ mov r6, r2 │ │ mov r7, r1 │ │ bl 2713db0 │ │ @@ -1757240,18 +1757240,18 @@ │ │ sub r0, fp, #148 @ 0x94 │ │ bl 27141e0 │ │ mov r0, r4 │ │ bl 2715e10 │ │ bl 26ffb60 │ │ @ instruction: 0x001486f0 │ │ @ instruction: 0xffa82eac │ │ - stc2l 13, cr10, [r2, #156] @ 0x9c │ │ + stc2l 13, cr10, [r2, #336] @ 0x150 │ │ stc2l 5, cr1, [r5, #232] @ 0xe8 │ │ stc2l 9, cr8, [r4, #276] @ 0x114 @ │ │ - stc2l 14, cr2, [r3, #404] @ 0x194 │ │ + stc2l 14, cr2, [r3, #584] @ 0x248 │ │ stc2l 7, cr8, [r4, #348] @ 0x15c │ │ stc2l 9, cr13, [r5, #428] @ 0x1ac @ │ │ stc2l 13, cr5, [r5, #832] @ 0x340 │ │ stc2l 13, cr1, [r5, #568] @ 0x238 │ │ andseq r7, r4, r0, lsl #31 │ │ │ │ 025f394c : │ │ @@ -1763664,16 +1763664,16 @@ │ │ strd r2, [r4] │ │ pop {r4, sl, fp, pc} │ │ ldr r1, [pc, #16] @ 25f9a4c │ │ mov r0, r4 │ │ add r1, pc, r1 │ │ bl 2712dd0 │ │ pop {r4, sl, fp, pc} │ │ - stc2l 12, cr6, [r2, #580] @ 0x244 │ │ - stc2l 12, cr6, [r2, #228] @ 0xe4 │ │ + stc2l 12, cr6, [r2, #760] @ 0x2f8 │ │ + stc2l 12, cr6, [r2, #408] @ 0x198 │ │ │ │ 025f9a50 : │ │ push {r4, r5, r6, r8, r9, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #80 @ 0x50 │ │ mov r4, r0 │ │ ldr r0, [r0, #16] │ │ @@ -1763824,15 +1763824,15 @@ │ │ blx r1 │ │ bl 26ffb60 │ │ b 25f9cb0 │ │ mov r0, r6 │ │ bl 2713d70 │ │ bl 26ffb60 │ │ stc2l 12, cr3, [r5, #68] @ 0x44 │ │ - stc2l 1, cr12, [r3, #532] @ 0x214 │ │ + stc2l 1, cr12, [r3, #712] @ 0x2c8 │ │ stc2l 13, cr6, [r4, #840] @ 0x348 │ │ │ │ 025f9cc8 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r1 │ │ ldr r1, [r0, #20] │ │ @@ -1764213,15 +1764213,15 @@ │ │ ldr r0, [r0] │ │ strne r1, [r6] │ │ pop {r4, r5, r6, sl, fp, pc} │ │ mov r0, #7 │ │ str r0, [r4] │ │ mov r0, r5 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - stc2l 4, cr6, [r2, #468] @ 0x1d4 │ │ + stc2l 4, cr6, [r2, #648] @ 0x288 │ │ │ │ 025fa268 : │ │ b 2718510 │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ │ │ 025fa270 : │ │ bx lr │ │ @@ -1766008,15 +1766008,15 @@ │ │ bl 26ffb60 │ │ andeq r0, r0, r0 │ │ svcvc 0x00f80000 │ │ andeq r0, r0, r0 │ │ @ instruction: 0xfff00000 @ IMB │ │ andeq r0, r0, r0 │ │ svcvc 0x00f00000 @ IMB │ │ - stc2l 9, cr4, [r2, #474] @ 0x1da @ │ │ + stc2l 10, cr4, [r2, #104] @ 0x68 @ │ │ │ │ 025fbd24 : │ │ ldr r2, [r0, #44] @ 0x2c │ │ add r1, r2, r1 │ │ str r1, [r0, #44] @ 0x2c │ │ bx lr │ │ │ │ @@ -1766623,15 +1766623,15 @@ │ │ strd r6, [r0, #48] @ 0x30 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ blx 207deaa │ │ add r0, sp, #8 │ │ bl 27197b0 │ │ bl 26ffb60 │ │ - stc2l 14, cr5, [r2, #144] @ 0x90 │ │ + stc2l 14, cr5, [r2, #324] @ 0x144 │ │ │ │ 025fc648 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ ldr r8, [r1] │ │ mov sl, r0 │ │ @@ -1769791,18 +1769791,18 @@ │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ blx 207deaa │ │ b 25ff6e0 │ │ sub r0, fp, #64 @ 0x40 │ │ bl 2719cc0 │ │ bl 26ffb60 │ │ - stc2l 2, cr2, [r3, #380] @ 0x17c │ │ + stc2l 2, cr2, [r3, #560] @ 0x230 │ │ stc2l 3, cr1, [r4, #408] @ 0x198 │ │ stc2l 9, cr2, [r4, #270] @ 0x10e @ │ │ - stc2l 0, cr1, [r2, #116] @ 0x74 │ │ + stc2l 0, cr1, [r2, #296] @ 0x128 │ │ stc2l 9, cr1, [r5, #376] @ 0x178 @ │ │ stc2l 1, cr5, [r1, #396] @ 0x18c │ │ stc2l 14, cr10, [r1, #884] @ 0x374 │ │ │ │ 025ff708 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ @@ -1769989,15 +1769989,15 @@ │ │ bl 27103d0 │ │ mov r0, r4 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ add r0, sp, #32 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - stc2l 9, cr0, [r3, #104] @ 0x68 @ │ │ + stc2l 9, cr0, [r3, #194] @ 0xc2 @ │ │ stc2l 12, cr11, [r4, #192] @ 0xc0 │ │ stc2l 15, cr6, [r5, #944] @ 0x3b0 │ │ │ │ 025ff9f0 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ @@ -1770782,28 +1770782,28 @@ │ │ orr r0, r0, #4096 @ 0x1000 │ │ b 260056c │ │ ldr r0, [r4, #20] │ │ orr r0, r0, #8192 @ 0x2000 │ │ str r0, [r4, #20] │ │ mov r0, r4 │ │ pop {r4, r5, fp, pc} │ │ - stc2l 0, cr0, [r2, #252] @ 0xfc │ │ - stc2l 0, cr4, [r2, #648] @ 0x288 │ │ - stc2l 7, cr3, [r3, #204] @ 0xcc │ │ - stc2l 7, cr3, [r3, #188] @ 0xbc │ │ + stc2l 0, cr0, [r2, #432] @ 0x1b0 │ │ + stc2l 0, cr4, [r2, #828] @ 0x33c │ │ + stc2l 7, cr3, [r3, #384] @ 0x180 │ │ + stc2l 7, cr3, [r3, #368] @ 0x170 │ │ stc2l 8, cr1, [r4, #964] @ 0x3c4 │ │ - stc2l 0, cr4, [r2, #332] @ 0x14c │ │ + stc2l 0, cr4, [r2, #512] @ 0x200 │ │ stc2l 0, cr5, [r4, #48] @ 0x30 │ │ stc2l 13, cr1, [r1, #512] @ 0x200 │ │ stc2l 15, cr5, [r1, #500] @ 0x1f4 │ │ - stc2l 15, cr15, [r1, #484] @ 0x1e4 │ │ + stc2l 15, cr15, [r1, #664] @ 0x298 │ │ stc2l 8, cr15, [r3, #600] @ 0x258 │ │ - stc2l 14, cr1, [r2, #628] @ 0x274 │ │ + stc2l 14, cr1, [r2, #808] @ 0x328 │ │ stc2l 0, cr11, [r4, #956] @ 0x3bc │ │ - stc2l 15, cr15, [r1, #132] @ 0x84 │ │ + stc2l 15, cr15, [r1, #312] @ 0x138 │ │ │ │ 026005b0 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r5, r1 │ │ ldr r1, [pc, #504] @ 26007bc │ │ mov r4, r0 │ │ @@ -1770929,28 +1770929,28 @@ │ │ orr r0, r0, #4096 @ 0x1000 │ │ b 26007b0 │ │ ldr r0, [r4, #20] │ │ orr r0, r0, #8192 @ 0x2000 │ │ str r0, [r4, #20] │ │ mov r0, r4 │ │ pop {r4, r5, fp, pc} │ │ - stc2l 13, cr15, [r1, #1004] @ 0x3ec │ │ - stc2l 14, cr3, [r2, #376] @ 0x178 │ │ - stc2l 4, cr3, [r3, #956] @ 0x3bc │ │ - stc2l 4, cr3, [r3, #940] @ 0x3ac │ │ + stc2l 14, cr15, [r1, #160] @ 0xa0 │ │ + stc2l 14, cr3, [r2, #556] @ 0x22c │ │ + stc2l 5, cr3, [r3, #112] @ 0x70 │ │ + stc2l 5, cr3, [r3, #96] @ 0x60 │ │ stc2l 6, cr1, [r4, #692] @ 0x2b4 │ │ - stc2l 14, cr3, [r2, #60] @ 0x3c │ │ + stc2l 14, cr3, [r2, #240] @ 0xf0 │ │ stc2l 13, cr4, [r4, #800] @ 0x320 │ │ stc2l 11, cr1, [r1, #240] @ 0xf0 @ │ │ stc2l 13, cr5, [r1, #228] @ 0xe4 │ │ - stc2l 13, cr15, [r1, #212] @ 0xd4 │ │ + stc2l 13, cr15, [r1, #392] @ 0x188 │ │ stc2l 6, cr15, [r3, #328] @ 0x148 │ │ - stc2l 12, cr1, [r2, #356] @ 0x164 │ │ + stc2l 12, cr1, [r2, #536] @ 0x218 │ │ stc2l 14, cr10, [r4, #684] @ 0x2ac │ │ - stc2l 12, cr15, [r1, #884] @ 0x374 │ │ + stc2l 13, cr15, [r1, #40] @ 0x28 │ │ │ │ 026007f4 : │ │ ldr r2, [r0, #20] │ │ orr r1, r2, r1 │ │ str r1, [r0, #20] │ │ bx lr │ │ │ │ @@ -1771078,27 +1771078,27 @@ │ │ ldr r0, [pc, #64] @ 2600a2c │ │ add r0, pc, r0 │ │ bx lr │ │ ldr r0, [pc, #24] @ 2600a10 │ │ add r0, pc, r0 │ │ bx lr │ │ vcadd.f16 , , q12, #270 │ │ - stc2l 10, cr15, [r1, #452] @ 0x1c4 @ │ │ + stc2l 10, cr15, [r1, #632] @ 0x278 @ │ │ stc2l 11, cr10, [r4, #1020] @ 0x3fc @ │ │ - stc2l 10, cr3, [r2, #584] @ 0x248 @ │ │ + stc2l 10, cr3, [r2, #764] @ 0x2fc @ │ │ stc2l 10, cr5, [r1, #436] @ 0x1b4 @ │ │ stc2l 2, cr1, [r4, #900] @ 0x384 │ │ - stc2l 1, cr3, [r3, #44] @ 0x2c │ │ - stc2l 1, cr3, [r3, #172] @ 0xac │ │ + stc2l 1, cr3, [r3, #224] @ 0xe0 │ │ + stc2l 1, cr3, [r3, #352] @ 0x160 │ │ stc2l 3, cr15, [r3, #600] @ 0x258 │ │ - stc2l 9, cr1, [r2, #330] @ 0x14a @ │ │ - stc2l 10, cr15, [r1, #44] @ 0x2c @ │ │ - stc2l 10, cr3, [r2, #556] @ 0x22c @ │ │ + stc2l 9, cr1, [r2, #420] @ 0x1a4 @ │ │ + stc2l 10, cr15, [r1, #224] @ 0xe0 @ │ │ + stc2l 10, cr3, [r2, #736] @ 0x2e0 @ │ │ stc2l 10, cr4, [r4, #224] @ 0xe0 @ │ │ - stc2l 10, cr15, [r1, #708] @ 0x2c4 @ │ │ + stc2l 10, cr15, [r1, #888] @ 0x378 @ │ │ stc2l 7, cr9, [r3, #440] @ 0x1b8 │ │ │ │ 02600a38 : │ │ ands r0, r1, r0 │ │ movwne r0, #1 │ │ bx lr │ │ │ │ @@ -1772099,17 +1772099,17 @@ │ │ bne 2601844 │ │ cmp r9, r1 │ │ bgt 2601844 │ │ mov r1, #0 │ │ str r1, [sp, #20] │ │ b 26016c4 │ │ stc2l 4, cr2, [r4, #400] @ 0x190 │ │ - stc2l 15, cr6, [r2, #672] @ 0x2a0 │ │ - stc2l 0, cr9, [r2, #16] │ │ - stc2l 9, cr0, [r3, #352] @ 0x160 @ │ │ + stc2l 15, cr6, [r2, #852] @ 0x354 │ │ + stc2l 0, cr9, [r2, #196] @ 0xc4 │ │ + stc2l 9, cr0, [r3, #442] @ 0x1ba @ │ │ @ instruction: 0xffa75174 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ ldr r6, [r1] │ │ ldr r9, [fp, #12] │ │ ldr lr, [fp, #8] │ │ sub r5, r3, r6 │ │ @@ -1791951,15 +1791951,15 @@ │ │ strne r5, [r8] │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ │ │ 02614c38 : │ │ ldr r0, [pc, #4] @ 2614c44 │ │ add r0, pc, r0 │ │ bx lr │ │ - stc2l 2, cr9, [r1, #548] @ 0x224 │ │ + stc2l 2, cr9, [r1, #728] @ 0x2d8 │ │ │ │ 02614c48 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ mov r0, #616 @ 0x268 │ │ bl 2713db0 │ │ @@ -1795096,15 +1795096,15 @@ │ │ bl 2713d70 │ │ bl 26ffb60 │ │ │ │ 02617a70 : │ │ ldr r0, [pc, #4] @ 2617a7c │ │ add r0, pc, r0 │ │ bx lr │ │ - vcadd.f16 q12, q0, q4, #270 │ │ + stc2l 8, cr8, [r0, #468] @ 0x1d4 │ │ │ │ 02617a80 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #108 @ 0x6c │ │ mov r4, r0 │ │ ldr r0, [r0] │ │ @@ -1795626,15 +1795626,15 @@ │ │ pop {r4, sl, fp, lr} │ │ b 2713d70 │ │ │ │ 02618258 : │ │ ldr r0, [pc, #4] @ 2618264 │ │ add r0, pc, r0 │ │ bx lr │ │ - stc2l 0, cr8, [r0, #352] @ 0x160 │ │ + stc2l 0, cr8, [r0, #532] @ 0x214 │ │ │ │ 02618268 : │ │ ldr r0, [pc, #12] @ 261827c │ │ add r0, pc, r0 │ │ add r0, r0, r1, lsl #4 │ │ ldr r0, [r0, r2, lsl #2] │ │ bx lr │ │ @@ -1796862,15 +1796862,15 @@ │ │ pop {r4, r5, r6, r7, fp, pc} │ │ add r0, sp, #4 │ │ bl 2711190 │ │ bl 26ffb60 │ │ add r0, sp, #208 @ 0xd0 │ │ bl 27162f0 │ │ bl 26ffb60 │ │ - stc2l 10, cr4, [r1, #976] @ 0x3d0 @ │ │ + stc2l 11, cr4, [r1, #132] @ 0x84 @ │ │ @ instruction: 0x001421f8 │ │ andseq r2, r4, r4, ror #3 │ │ │ │ 02619550 : │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r0, [pc, #64] @ 26195a0 │ │ @@ -1797095,25 +1797095,25 @@ │ │ bl 2716050 │ │ mov r0, r4 │ │ mov r1, #22 │ │ mov r2, #1 │ │ pop {r4, r5, r6, sl, fp, lr} │ │ b 2716050 │ │ stc2l 10, cr4, [r2, #276] @ 0x114 @ │ │ - stc2l 12, cr0, [r1, #572] @ 0x23c │ │ + stc2l 12, cr0, [r1, #752] @ 0x2f0 │ │ stc2l 8, cr7, [r3, #984] @ 0x3d8 │ │ - stc2l 9, cr4, [r0, #396] @ 0x18c @ │ │ + stc2l 9, cr4, [r0, #486] @ 0x1e6 @ │ │ stc2l 14, cr0, [r0, #216] @ 0xd8 │ │ ldc2 12, cr12, [pc, #492]! @ 2619ab4 │ │ - stc2l 9, cr4, [r0, #262] @ 0x106 @ │ │ + stc2l 9, cr4, [r0, #352] @ 0x160 @ │ │ stc2l 2, cr10, [r2, #564] @ 0x234 │ │ stc2l 12, cr15, [r2, #436] @ 0x1b4 │ │ - stc2l 11, cr12, [r0, #756] @ 0x2f4 @ │ │ - stc2l 7, cr14, [r1, #36] @ 0x24 │ │ - stc2l 13, cr2, [r1, #840] @ 0x348 │ │ + stc2l 11, cr12, [r0, #936] @ 0x3a8 @ │ │ + stc2l 7, cr14, [r1, #216] @ 0xd8 │ │ + stc2l 13, cr2, [r1, #1020] @ 0x3fc │ │ │ │ 026198dc : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r0 │ │ ldr r0, [r1] │ │ mov r7, #0 │ │ @@ -1797637,15 +1797637,15 @@ │ │ bl 26ffb60 │ │ andseq r1, r2, r8, ror #15 │ │ │ │ 0261a0bc : │ │ ldr r0, [pc, #4] @ 261a0c8 │ │ add r0, pc, r0 │ │ bx lr │ │ - stc2l 15, cr3, [r0, #68] @ 0x44 │ │ + stc2l 15, cr3, [r0, #248] @ 0xf8 │ │ │ │ 0261a0cc : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #8 │ │ ldr r2, [r1] │ │ mov r4, r0 │ │ @@ -1797850,15 +1797850,15 @@ │ │ pop {r4, r5, r6, r7, fp, pc} │ │ add r0, sp, #4 │ │ bl 2711190 │ │ bl 26ffb60 │ │ add r0, sp, #208 @ 0xd0 │ │ bl 2718430 │ │ bl 26ffb60 │ │ - stc2l 0, cr12, [r0, #504] @ 0x1f8 │ │ + stc2l 0, cr12, [r0, #684] @ 0x2ac │ │ andseq r1, r4, r8, asr r3 │ │ andseq r1, r4, r4, asr #6 │ │ │ │ 0261a400 : │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r0, [pc, #64] @ 261a450 │ │ @@ -1797935,15 +1797935,15 @@ │ │ bl 26ffb60 │ │ andseq r1, r2, r4, lsr #7 │ │ │ │ 0261a504 : │ │ ldr r0, [pc, #4] @ 261a510 │ │ add r0, pc, r0 │ │ bx lr │ │ - stc2l 6, cr11, [r1, #816] @ 0x330 │ │ + stc2l 6, cr11, [r1, #996] @ 0x3e4 │ │ │ │ 0261a514 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #8 │ │ ldr r2, [r1] │ │ mov r4, r0 │ │ @@ -1798885,15 +1798885,15 @@ │ │ pop {r4, sl, fp, lr} │ │ b 2713d70 │ │ │ │ 0261b27c : │ │ ldr r0, [pc, #4] @ 261b288 │ │ add r0, pc, r0 │ │ bx lr │ │ - stc2l 0, cr15, [r0, #512] @ 0x200 │ │ + stc2l 0, cr15, [r0, #692] @ 0x2b4 │ │ │ │ 0261b28c : │ │ ldr r0, [pc, #12] @ 261b2a0 │ │ add r0, pc, r0 │ │ add r0, r0, r1, lsl #4 │ │ ldr r0, [r0, r2, lsl #2] │ │ bx lr │ │ @@ -1799513,15 +1799513,15 @@ │ │ bl 2713d70 │ │ bl 26ffb60 │ │ │ │ 0261bb9c : │ │ ldr r0, [pc, #4] @ 261bba8 │ │ add r0, pc, r0 │ │ bx lr │ │ - stc2l 6, cr6, [r0, #468] @ 0x1d4 │ │ + stc2l 6, cr6, [r0, #648] @ 0x288 │ │ │ │ 0261bbac : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #8 │ │ ldr r2, [r1] │ │ mov r4, r0 │ │ @@ -1800056,15 +1800056,15 @@ │ │ pop {r4, sl, fp, lr} │ │ b 2713d70 │ │ │ │ 0261c348 : │ │ ldr r0, [pc, #4] @ 261c354 │ │ add r0, pc, r0 │ │ bx lr │ │ - stc2l 12, cr1, [r0, #504] @ 0x1f8 │ │ + stc2l 12, cr1, [r0, #684] @ 0x2ac │ │ │ │ 0261c358 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r5, r0 │ │ mov r0, #616 @ 0x268 │ │ bl 2713db0 │ │ @@ -1801564,26 +1801564,26 @@ │ │ mov r2, #11 │ │ b 261da04 │ │ mov r2, #12 │ │ mov r0, r4 │ │ mov r1, #2 │ │ pop {r4, r5, r6, sl, fp, lr} │ │ b 2716050 │ │ - stc2l 3, cr8, [r1, #528] @ 0x210 │ │ - stc2l 10, cr6, [r0, #408] @ 0x198 @ │ │ - stc2l 7, cr0, [r0, #280] @ 0x118 │ │ + stc2l 3, cr8, [r1, #708] @ 0x2c4 │ │ + stc2l 10, cr6, [r0, #588] @ 0x24c @ │ │ + stc2l 7, cr0, [r0, #460] @ 0x1cc │ │ ldc2 14, cr10, [pc, #224]! @ 261db08 │ │ - stc2l 1, cr6, [r1, #48] @ 0x30 │ │ + stc2l 1, cr6, [r1, #228] @ 0xe4 │ │ ldc2 12, cr12, [pc, #792]! @ 261dd48 │ │ stc2l 12, cr15, [r2, #664] @ 0x298 │ │ ldc2 6, cr6, [pc, #68]! @ 261da7c │ │ stc2l 2, cr4, [r2, #636] @ 0x27c │ │ - stc2l 4, cr10, [r1, #884] @ 0x374 │ │ + stc2l 5, cr10, [r1, #40] @ 0x28 │ │ stc2l 10, cr13, [r2, #952] @ 0x3b8 @ │ │ - stc2l 9, cr2, [r0, #270] @ 0x10e @ │ │ + stc2l 9, cr2, [r0, #360] @ 0x168 @ │ │ stc2l 12, cr15, [r2, #104] @ 0x68 │ │ │ │ 0261da48 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r4, r1 │ │ @@ -1801681,16 +1801681,16 @@ │ │ add r1, pc, r1 │ │ bl 2710a20 │ │ clz r0, r0 │ │ lsr r0, r0, #5 │ │ pop {fp, pc} │ │ mov r0, #0 │ │ pop {fp, pc} │ │ - stc2l 3, cr4, [r1, #68] @ 0x44 │ │ - stc2l 6, cr0, [r1, #288] @ 0x120 │ │ + stc2l 3, cr4, [r1, #248] @ 0xf8 │ │ + stc2l 6, cr0, [r1, #468] @ 0x1d4 │ │ │ │ 0261dbc0 : │ │ ldr r0, [pc, #4] @ 261dbcc │ │ ldr r0, [pc, r0] │ │ bx lr │ │ strbeq pc, [r8, #3760] @ 0xeb0 @ │ │ │ │ @@ -1801776,16 +1801776,16 @@ │ │ pop {r4, r5, r6, sl, fp, lr} │ │ ldr r1, [pc, #36] @ 261dd38 │ │ mov r0, #7 │ │ add r1, pc, r1 │ │ b 271d260 │ │ strbeq pc, [r8, #3632] @ 0xe30 @ │ │ strbeq pc, [r8, #3604] @ 0xe14 @ │ │ - stc2l 2, cr4, [r1, #68] @ 0x44 │ │ - stc2l 5, cr0, [r1, #288] @ 0x120 │ │ + stc2l 2, cr4, [r1, #248] @ 0xf8 │ │ + stc2l 5, cr0, [r1, #468] @ 0x1d4 │ │ stc2l 3, cr12, [r1, #4] │ │ strbeq pc, [r8, #3484] @ 0xd9c @ │ │ strbeq pc, [r8, #3456] @ 0xd80 @ │ │ andeq r0, r0, r8, ror #10 │ │ │ │ 0261dd3c : │ │ b 2718a20 │ │ @@ -1802566,16 +1802566,16 @@ │ │ b 261e8bc │ │ ldr r0, [sp, #36] @ 0x24 │ │ bl 2710990 │ │ sub r0, fp, #32 │ │ bl 2710d40 │ │ bl 26ffb60 │ │ blx 207deaa │ │ - stc2l 0, cr10, [r0, #208] @ 0xd0 │ │ - stc2l 15, cr5, [r0, #608] @ 0x260 │ │ + stc2l 0, cr10, [r0, #388] @ 0x184 │ │ + stc2l 15, cr5, [r0, #788] @ 0x314 │ │ stc2l 15, cr6, [r2, #424] @ 0x1a8 │ │ ldc2 6, cr4, [pc, #152]! @ 261e980 │ │ stc2l 6, cr3, [r2, #180] @ 0xb4 │ │ @ instruction: 0xffa5a046 │ │ │ │ 0261e8ec : │ │ ldr ip, [r3] │ │ @@ -1804050,16 +1804050,16 @@ │ │ b 261fe78 │ │ b 261fe78 │ │ b 261fe78 │ │ b 261fe78 │ │ add r0, sp, #12 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - stc2l 8, cr8, [r0, #1008] @ 0x3f0 │ │ - stc2l 6, cr4, [r0, #780] @ 0x30c │ │ + stc2l 9, cr8, [r0, #82] @ 0x52 @ │ │ + stc2l 6, cr4, [r0, #960] @ 0x3c0 │ │ stc2l 1, cr12, [r1, #416] @ 0x1a0 │ │ andseq r3, r1, r4, lsr r3 │ │ andseq r3, r1, r8, lsr #5 │ │ │ │ 0261fe98 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -1804486,15 +1804486,15 @@ │ │ bl 2713d70 │ │ bl 26ffb60 │ │ │ │ 026204a8 : │ │ ldr r0, [pc, #4] @ 26204b4 │ │ add r0, pc, r0 │ │ bx lr │ │ - ldc2 14, cr15, [pc, #256]! @ 26205bc │ │ + ldc2 14, cr15, [pc, #436]! @ 2620670 │ │ │ │ 026204b8 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ ldr r2, [r1] │ │ mov r4, r0 │ │ mov r0, #0 │ │ @@ -1804686,15 +1804686,15 @@ │ │ pop {r4, r5, r6, r7, fp, pc} │ │ add r0, sp, #4 │ │ bl 2711190 │ │ bl 26ffb60 │ │ add r0, sp, #208 @ 0xd0 │ │ bl 27171f0 │ │ bl 26ffb60 │ │ - stc2l 13, cr3, [r0, #580] @ 0x244 │ │ + stc2l 13, cr3, [r0, #760] @ 0x2f8 │ │ andseq fp, r3, r0 │ │ andseq sl, r3, ip, ror #31 │ │ │ │ 026207b8 : │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r0, [pc, #64] @ 2620808 │ │ @@ -1806084,15 +1806084,15 @@ │ │ mov r0, r7 │ │ bl 2718890 │ │ b 2621c50 │ │ mov r0, r7 │ │ bl 2713d70 │ │ bl 26ffb60 │ │ andseq r9, r1, r4, asr #27 │ │ - ldc2 10, cr14, [pc, #484]! @ 2621e4c @ │ │ + ldc2 10, cr14, [pc, #664]! @ 2621f00 @ │ │ │ │ 02621c64 : │ │ mov r3, #1 │ │ str r1, [r0] │ │ str r3, [r0, #4] │ │ ldr r3, [r2] │ │ cmp r3, #0 │ │ @@ -1816677,15 +1816677,15 @@ │ │ ldrne r1, [pc, #24] @ 262b2b8 │ │ addne r1, pc, r1 │ │ ldrne r0, [r1, r0, lsl #2] │ │ bxne lr │ │ ldr r0, [pc, #4] @ 262b2b4 │ │ add r0, pc, r0 │ │ bx lr │ │ - ldc2 3, cr5, [pc, #804]! @ 262b5e0 │ │ + ldc2 3, cr5, [pc, #984]! @ 262b694 │ │ andseq r8, r0, r0, lsl r1 │ │ │ │ 0262b2bc : │ │ ldrsb r1, [r0, #10] │ │ cmn r1, #1 │ │ ldreq r0, [pc, #80] @ 262b31c │ │ addeq r0, pc, r0 │ │ @@ -1816705,15 +1816705,15 @@ │ │ ldrpl r1, [r2, r1, lsl #2] │ │ addpl r2, r1, r0 │ │ ldr r0, [pc, #20] @ 262b324 │ │ add r0, pc, r0 │ │ add r0, r0, r2, lsl #2 │ │ ldr r0, [r0] │ │ bx lr │ │ - ldc2 3, cr5, [pc, #692]! @ 262b5d8 │ │ + ldc2 3, cr5, [pc, #872]! @ 262b68c │ │ @ instruction: 0xffa4d4f4 │ │ ldrsheq r8, [r0], -ip │ │ │ │ 0262b328 : │ │ ldr r1, [r0, #4] │ │ cmp r1, #0 │ │ addne r0, r1, #52 @ 0x34 │ │ @@ -1817159,15 +1817159,15 @@ │ │ ldr r2, [pc, #36] @ 262ba04 │ │ add r2, pc, r2 │ │ ldr r0, [r2, r0, lsl #2] │ │ sub r0, r5, r0 │ │ strh r0, [r1, #8] │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2 11, cr0, [pc, #212]! @ 262bad0 @ │ │ + ldc2 11, cr0, [pc, #392]! @ 262bb84 @ │ │ andseq r7, r0, ip, asr #21 │ │ @ instruction: 0xffa4ce90 │ │ mulseq r0, r4, sl │ │ @ instruction: 0xffa4ce14 │ │ │ │ 0262ba08 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ @@ -1817319,15 +1817319,15 @@ │ │ bl 2718ea0 │ │ b 262bc60 │ │ mov r0, r5 │ │ bl 2718ec0 │ │ mov r0, r7 │ │ bl 2713d70 │ │ bl 26ffb60 │ │ - ldc2 5, cr0, [pc, #424]! @ 262be1c ::create(icu_75::SingleUnitImpl const&)@@Base+0xbc> │ │ + ldc2 5, cr0, [pc, #604]! @ 262bed0 │ │ andseq r7, r0, r8, ror #18 │ │ @ instruction: 0xffa4cd44 │ │ andseq r7, r0, r0, asr #18 │ │ @ instruction: 0xffa4ccc7 │ │ @ instruction: 0xffa4cc30 │ │ @ instruction: 0xffa4cbbc │ │ │ │ @@ -1818235,24 +1818235,24 @@ │ │ pop {r4, sl, fp, pc} │ │ mov r0, #12 │ │ pop {r4, sl, fp, pc} │ │ mov r0, #13 │ │ pop {r4, sl, fp, pc} │ │ ldc2 5, cr8, [lr, #16]! │ │ stc2l 7, cr15, [r0, #4] │ │ - ldc2 8, cr15, [lr, #996]! @ 0x3e4 │ │ + ldc2 9, cr15, [lr, #76]! @ 0x4c @ │ │ stc2l 12, cr12, [r1, #484] @ 0x1e4 │ │ - ldc2 9, cr1, [pc, #150]! @ 262ca32 @ │ │ - stc2l 10, cr3, [r0, #668] @ 0x29c @ │ │ - ldc2 13, cr11, [pc, #684]! @ 262cc50 │ │ - ldc2 12, cr3, [pc, #8]! @ 262c9b0 │ │ + ldc2 9, cr1, [pc, #240]! @ 262ca8c @ │ │ + stc2l 10, cr3, [r0, #848] @ 0x350 @ │ │ + ldc2 13, cr11, [pc, #864]! @ 262cd04 │ │ + ldc2 12, cr3, [pc, #188]! @ 262ca64 │ │ ldc2 15, cr11, [lr, #612]! @ 0x264 │ │ - stc2l 6, cr5, [r0, #504] @ 0x1f8 │ │ - stc2l 7, cr11, [r0, #124] @ 0x7c │ │ - stc2l 7, cr1, [r0, #212] @ 0xd4 │ │ + stc2l 6, cr5, [r0, #684] @ 0x2ac │ │ + stc2l 7, cr11, [r0, #304] @ 0x130 │ │ + stc2l 7, cr1, [r0, #392] @ 0x188 │ │ vcadd.f16 d29, d16, d2, #270 │ │ stc2l 7, cr4, [r2, #580] @ 0x244 │ │ stc2l 11, cr8, [r1, #716] @ 0x2cc @ │ │ │ │ 0262c9c0 : │ │ cmp r0, #6 │ │ ldrhi r0, [pc, #20] @ 262c9e0 │ │ @@ -1818323,19 +1818323,19 @@ │ │ pop {r4, sl, fp, pc} │ │ mov r0, #4 │ │ pop {r4, sl, fp, pc} │ │ mov r0, #5 │ │ pop {r4, sl, fp, pc} │ │ ldc2 2, cr8, [lr, #720]! @ 0x2d0 │ │ stc2l 4, cr15, [r0, #744] @ 0x2e8 │ │ - ldc2 10, cr3, [pc, #220]! @ 262cbc0 @ │ │ + ldc2 10, cr3, [pc, #400]! @ 262cc74 @ │ │ stc2l 10, cr8, [r1, #464] @ 0x1d0 @ │ │ - ldc2 11, cr11, [pc, #592]! @ 262cd3c @ │ │ + ldc2 11, cr11, [pc, #772]! @ 262cdf0 @ │ │ ldc2 9, cr9, [lr, #306]! @ 0x132 @ │ │ - ldc2 9, cr15, [lr, #110]! @ 0x6e @ │ │ + ldc2 9, cr15, [lr, #200]! @ 0xc8 @ │ │ │ │ 0262caf0 : │ │ cmp r0, #8 │ │ ldrhi r0, [pc, #20] @ 262cb10 │ │ addhi r0, pc, r0 │ │ bxhi lr │ │ ldr r1, [pc, #12] @ 262cb14 │ │ @@ -1818417,22 +1818417,22 @@ │ │ mov r0, #5 │ │ pop {r4, sl, fp, pc} │ │ mov r0, #6 │ │ pop {r4, sl, fp, pc} │ │ mov r0, #7 │ │ pop {r4, sl, fp, pc} │ │ ldc2 1, cr8, [lr, #528]! @ 0x210 │ │ - ldc2 8, cr15, [lr, #508]! @ 0x1fc │ │ + vcmla.f32 d15, d30, d28, #270 │ │ stc2l 1, cr5, [r1, #632] @ 0x278 │ │ - stc2l 7, cr3, [r0, #384] @ 0x180 │ │ - stc2l 4, cr11, [r0, #232] @ 0xe8 │ │ + stc2l 7, cr3, [r0, #564] @ 0x234 │ │ + stc2l 4, cr11, [r0, #412] @ 0x19c │ │ ldc2 10, cr13, [lr, #236]! @ 0xec @ │ │ stc2l 11, cr0, [r2, #492] @ 0x1ec @ │ │ - vcmla.f32 , , q2, #270 │ │ - ldc2 7, cr5, [pc, #440]! @ 262ce20 │ │ + ldc2 8, cr9, [pc, #452]! @ 262ce28 │ │ + ldc2 7, cr5, [pc, #620]! @ 262ced4 │ │ │ │ 0262cc64 : │ │ ldr r0, [pc, #4] @ 262cc70 │ │ add r0, pc, r0 │ │ bx lr │ │ strbeq r0, [r8, #3657] @ 0xe49 │ │ │ │ @@ -1819412,22 +1819412,22 @@ │ │ @ instruction: 0xffa4b66b │ │ @ instruction: 0x001069dc │ │ @ instruction: 0xffa4b5aa │ │ @ instruction: 0xffa4b573 │ │ @ instruction: 0xffa4b51a │ │ @ instruction: 0xffa4b39e │ │ andseq sp, r0, r0, asr lr │ │ - ldc2 12, cr10, [pc, #308]! @ 262dcec │ │ + ldc2 12, cr10, [pc, #488]! @ 262dda0 │ │ @ instruction: 0xffa4b076 │ │ @ instruction: 0x001064f4 │ │ stc2l 14, cr15, [r1, #116] @ 0x74 │ │ - stc2l 1, cr6, [r0, #916] @ 0x394 │ │ + stc2l 2, cr6, [r0, #72] @ 0x48 │ │ ldc2 4, cr9, [lr, #796]! @ 0x31c │ │ stc2l 13, cr15, [r1, #548] @ 0x224 │ │ - stc2l 1, cr6, [r0, #340] @ 0x154 │ │ + stc2l 1, cr6, [r0, #520] @ 0x208 │ │ ldc2 4, cr9, [lr, #220]! @ 0xdc │ │ │ │ 0262dbd4 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #140 @ 0x8c │ │ mov r4, r0 │ │ @@ -1821501,15 +1821501,15 @@ │ │ sub r0, fp, #108 @ 0x6c │ │ bl 2710d40 │ │ b 262fbec │ │ sub r0, fp, #96 @ 0x60 │ │ bl 2714160 │ │ bl 26ffb60 │ │ andseq fp, r0, r4, lsr #27 │ │ - ldc2 11, cr8, [pc, #308]! @ 262fd38 @ │ │ + ldc2 11, cr8, [pc, #488]! @ 262fdec @ │ │ stc2l 6, cr1, [r2, #716] @ 0x2cc │ │ │ │ 0262fc04 : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #8 │ │ movw ip, #2132 @ 0x854 │ │ @@ -1827027,15 +1827027,15 @@ │ │ strh r0, [r4, #18] │ │ mov r0, r4 │ │ pop {r4, r5, fp, pc} │ │ mov r0, r4 │ │ bl 2718ee0 │ │ bl 26ffb60 │ │ @ instruction: 0x001067d8 │ │ - ldc2 15, cr6, [lr, #280]! @ 0x118 │ │ + ldc2 15, cr6, [lr, #460]! @ 0x1cc │ │ │ │ 026350a8 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #16 │ │ mov r4, r0 │ │ bl 2718e20 │ │ @@ -1832142,22 +1832142,22 @@ │ │ pop {r4, sl, fp, pc} │ │ mov r0, #6 │ │ pop {r4, sl, fp, pc} │ │ mov r0, #5 │ │ pop {r4, sl, fp, pc} │ │ mov r0, #4 │ │ pop {r4, sl, fp, pc} │ │ - ldc2 10, cr2, [pc, #292]! @ 2639d64 @ │ │ - ldc2 8, cr12, [lr, #84]! @ 0x54 │ │ - ldc2 4, cr14, [pc, #608]! @ 2639ea8 │ │ + ldc2 10, cr2, [pc, #472]! @ 2639e18 @ │ │ + vcmla.f32 q6, q7, q1, #270 │ │ + ldc2 4, cr14, [pc, #788]! @ 2639f5c │ │ ldc2 7, cr0, [lr, #536]! @ 0x218 │ │ - ldc2 5, cr8, [lr, #588]! @ 0x24c │ │ - ldc2 5, cr2, [lr, #308]! @ 0x134 │ │ + ldc2 5, cr8, [lr, #768]! @ 0x300 │ │ + ldc2 5, cr2, [lr, #488]! @ 0x1e8 │ │ stc2l 13, cr6, [r0, #968] @ 0x3c8 │ │ - ldc2 10, cr10, [pc, #600]! @ 2639eb4 @ │ │ + ldc2 10, cr10, [pc, #780]! @ 2639f68 @ │ │ │ │ 02639c58 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #72 @ 0x48 │ │ ldrsh r1, [r0, #4] │ │ ldr r2, [r0, #8] │ │ @@ -1835746,16 +1835746,16 @@ │ │ bl 2710d40 │ │ b 263d1ec │ │ sub r0, fp, #100 @ 0x64 │ │ bl 2714160 │ │ bl 26ffb60 │ │ andeq lr, pc, r8, asr r9 @ │ │ stc2l 14, cr10, [r0, #412] @ 0x19c │ │ - ldc2 4, cr3, [pc, #908]! @ 263d594 │ │ - ldc2 1, cr5, [pc, #104]! @ 263d274 │ │ + ldc2 5, cr3, [pc, #64]! @ 263d248 │ │ + ldc2 1, cr5, [pc, #284]! @ 263d328 │ │ stc2l 5, cr8, [r0, #288] @ 0x120 │ │ │ │ 0263d20c : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #72 @ 0x48 │ │ vmov s0, r2 │ │ @@ -1840919,15 +1840919,15 @@ │ │ add r1, sp, #13 │ │ mov r0, r4 │ │ mvn r2, #0 │ │ mov r3, #0 │ │ bl 2714240 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2 15, cr11, [lr, #964]! @ 0x3c4 │ │ + ldc2 0, cr12, [lr, #120]! @ 0x78 │ │ ldc2 7, cr6, [sp, #944]! @ 0x3b0 │ │ │ │ 0264206c : │ │ push {fp, lr} │ │ mov fp, sp │ │ vpush {d8} │ │ vldr s0, [r0, #48] @ 0x30 │ │ @@ -1840992,15 +1840992,15 @@ │ │ bl 2710d40 │ │ b 2642164 │ │ mov r0, r4 │ │ bl 2713f30 │ │ bl 26ffb60 │ │ @ instruction: 0x000f99b0 │ │ stc2l 10, cr5, [r0, #956] @ 0x3bc @ │ │ - ldc2 1, cr14, [lr, #780]! @ 0x30c │ │ + ldc2 1, cr14, [lr, #960]! @ 0x3c0 │ │ │ │ 0264217c : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ ldr r1, [pc, #56] @ 26421c4 │ │ mov r4, r0 │ │ ldr r1, [pc, r1] │ │ @@ -1841403,16 +1841403,16 @@ │ │ bl 27103d0 │ │ sub r0, fp, #20 │ │ bl 2710d40 │ │ b 2642768 │ │ mov r0, r4 │ │ bl 271b6c0 │ │ bl 26ffb60 │ │ - ldc2 14, cr13, [sp, #508]! @ 0x1fc │ │ - vcmla.f32 , q15, , #270 │ │ + ldc2 14, cr13, [sp, #688]! @ 0x2b0 │ │ + ldc2 9, cr15, [lr, #32]! @ │ │ ldc2 10, cr11, [pc, #972]! @ 2642b50 @ │ │ andeq r1, pc, ip, lsr #25 │ │ │ │ 02642784 : │ │ push {r4, r5, r6, r8, r9, sl, fp, lr} │ │ add fp, sp, #24 │ │ mov r5, r1 │ │ @@ -1844393,15 +1844393,15 @@ │ │ mov r0, r5 │ │ bl 2718890 │ │ b 2645424 │ │ mov r0, r5 │ │ bl 2713d70 │ │ bl 26ffb60 │ │ andeq r6, pc, r0, lsr r6 @ │ │ - ldc2 2, cr11, [sp, #916]! @ 0x394 │ │ + ldc2 3, cr11, [sp, #72]! @ 0x48 │ │ andeq r6, pc, r0, lsr #11 │ │ │ │ 0264543c : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r6, r0 │ │ ldr r0, [r0, #396] @ 0x18c │ │ @@ -1844536,15 +1844536,15 @@ │ │ mov r0, r5 │ │ bl 2718890 │ │ b 2645650 │ │ mov r0, r5 │ │ bl 2713d70 │ │ bl 26ffb60 │ │ andeq r6, pc, r4, lsl #8 │ │ - ldc2 0, cr11, [sp, #740]! @ 0x2e4 │ │ + ldc2 0, cr11, [sp, #920]! @ 0x398 │ │ andeq r6, pc, r4, ror r3 @ │ │ │ │ 02645668 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ ldr r9, [fp, #8] │ │ @@ -1844614,15 +1844614,15 @@ │ │ mov r0, r5 │ │ bl 2718890 │ │ b 2645780 │ │ mov r0, r5 │ │ bl 2713d70 │ │ bl 26ffb60 │ │ ldrdeq r6, [pc], -r8 │ │ - ldc2 15, cr10, [sp, #548]! @ 0x224 │ │ + ldc2 15, cr10, [sp, #728]! @ 0x2d8 │ │ andeq r6, pc, r4, asr #4 │ │ │ │ 02645798 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ mov r5, r3 │ │ ldr r3, [r3] │ │ @@ -1844687,15 +1844687,15 @@ │ │ mov r0, r7 │ │ bl 2718890 │ │ b 264589c │ │ mov r0, r7 │ │ bl 2713d70 │ │ bl 26ffb60 │ │ @ instruction: 0x000f61b0 │ │ - ldc2 14, cr10, [sp, #420]! @ 0x1a4 │ │ + ldc2 14, cr10, [sp, #600]! @ 0x258 │ │ andeq r6, pc, r4, lsr #2 │ │ │ │ 026458b4 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ ldr r0, [r0, #396] @ 0x18c │ │ @@ -1849150,39 +1849150,39 @@ │ │ strbeq r4, [r6, #2656] @ 0xa60 │ │ strbeq r4, [r6, #2632] @ 0xa48 │ │ andeq fp, lr, r4, asr r2 │ │ ldc2 6, cr10, [pc, #1004]! @ 2649df4 │ │ strbeq r4, [r6, #2568] @ 0xa08 │ │ strbeq r4, [r6, #2472] @ 0x9a8 │ │ andeq fp, lr, ip, lsr #1 │ │ - ldc2 11, cr14, [lr, #232]! @ 0xe8 @ │ │ + ldc2 11, cr14, [lr, #412]! @ 0x19c @ │ │ ldc2 11, cr8, [pc, #76]! @ 2649a68 @ │ │ - ldc2 10, cr8, [lr, #256]! @ 0x100 @ │ │ - ldc2 10, cr14, [lr, #756]! @ 0x2f4 @ │ │ + ldc2 10, cr8, [lr, #436]! @ 0x1b4 @ │ │ + ldc2 10, cr14, [lr, #936]! @ 0x3a8 @ │ │ stc2l 12, cr5, [r0, #556] @ 0x22c │ │ - ldc2 11, cr2, [sp, #532]! @ 0x214 @ │ │ - ldc2 14, cr6, [sp, #912]! @ 0x390 │ │ + ldc2 11, cr2, [sp, #712]! @ 0x2c8 @ │ │ + ldc2 15, cr6, [sp, #68]! @ 0x44 │ │ ldc2 0, cr1, [sp, #200]! @ 0xc8 │ │ - ldc2 9, cr8, [lr, #172]! @ 0xac @ │ │ + ldc2 9, cr8, [lr, #262]! @ 0x106 @ │ │ stc2l 10, cr7, [r0, #548] @ 0x224 @ │ │ - ldc2 9, cr8, [lr, #24]! @ │ │ + ldc2 9, cr8, [lr, #114]! @ 0x72 @ │ │ stc2l 10, cr7, [r0, #252] @ 0xfc @ │ │ stc2l 0, cr4, [r0, #816] @ 0x330 │ │ - ldc2 15, cr2, [lr, #592]! @ 0x250 │ │ - ldc2 13, cr0, [lr, #372]! @ 0x174 │ │ - ldc2 15, cr2, [lr, #296]! @ 0x128 │ │ + ldc2 15, cr2, [lr, #772]! @ 0x304 │ │ + ldc2 13, cr0, [lr, #552]! @ 0x228 │ │ + ldc2 15, cr2, [lr, #476]! @ 0x1dc │ │ stc2l 9, cr7, [r0, #250] @ 0xfa @ │ │ ldc2 4, cr14, [pc, #764]! @ 2649d58 │ │ - ldc2 7, cr8, [lr, #840]! @ 0x348 │ │ - ldc2 5, cr12, [lr, #700]! @ 0x2bc │ │ - ldc2 12, cr6, [sp, #680]! @ 0x2a8 │ │ + ldc2 7, cr8, [lr, #1020]! @ 0x3fc │ │ + ldc2 5, cr12, [lr, #880]! @ 0x370 │ │ + ldc2 12, cr6, [sp, #860]! @ 0x35c │ │ strbeq r4, [r6, #1468] @ 0x5bc │ │ strbeq r4, [r6, #1436] @ 0x59c │ │ andeq sl, lr, r8, asr #27 │ │ - ldc2 12, cr6, [sp, #88]! @ 0x58 │ │ + ldc2 12, cr6, [sp, #268]! @ 0x10c │ │ strbeq r4, [r6, #1344] @ 0x540 │ │ strbeq r4, [r6, #1280] @ 0x500 │ │ │ │ 02649a7c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #156 @ 0x9c │ │ @@ -1849313,17 +1849313,17 @@ │ │ bl 27103d0 │ │ b 2649c84 │ │ b 2649c84 │ │ sub r0, fp, #84 @ 0x54 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ andeq r1, r0, r4, ror #6 │ │ - ldc2 4, cr8, [lr, #64]! @ 0x40 │ │ - ldc2 3, cr14, [lr, #1012]! @ 0x3f4 │ │ - ldc2 4, cr14, [lr, #200]! @ 0xc8 │ │ + ldc2 4, cr8, [lr, #244]! @ 0xf4 │ │ + ldc2 4, cr14, [lr, #168]! @ 0xa8 │ │ + ldc2 4, cr14, [lr, #380]! @ 0x17c │ │ ldc2 4, cr8, [pc, #92]! @ 2649d04 │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r5, r0 │ │ ldr r0, [r0, #4] │ │ mov r4, r3 │ │ str r0, [r5, #8] │ │ @@ -1849910,15 +1849910,15 @@ │ │ mov r3, r4 │ │ bl 27108e0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ stc2l 13, cr4, [r0, #380] @ 0x17c │ │ stc2l 11, cr6, [r0, #996] @ 0x3e4 @ │ │ ldc2 11, cr7, [pc, #76]! @ 264a5f0 @ │ │ - ldc2 12, cr1, [sp, #452]! @ 0x1c4 │ │ + ldc2 12, cr1, [sp, #632]! @ 0x278 │ │ strdeq r9, [lr], -r0 │ │ strbeq r3, [r6, #2136] @ 0x858 │ │ │ │ 0264a5ac : │ │ ldr r0, [r0] │ │ ldr r1, [pc, #8] @ 264a5c0 │ │ ldr r1, [pc, r1] │ │ @@ -1850038,15 +1850038,15 @@ │ │ str r2, [r4, #24] │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ mov r0, #0 │ │ stm r4, {r0, r1, r2} │ │ ldr r0, [pc, #20] @ 264a798 │ │ ldr r0, [pc, r0] │ │ b 264a754 │ │ - ldc2 15, cr5, [sp, #212]! @ 0xd4 │ │ + ldc2 15, cr5, [sp, #392]! @ 0x188 │ │ stc2l 2, cr12, [r0, #256] @ 0x100 │ │ strbeq r3, [r6, #1828] @ 0x724 │ │ strbeq r3, [r6, #1792] @ 0x700 │ │ strbeq r3, [r6, #1620] @ 0x654 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #28 │ │ @@ -1851318,15 +1851318,15 @@ │ │ add r0, sp, #4 │ │ bl 27103d0 │ │ b 264bb24 │ │ b 264bb24 │ │ sub r0, fp, #68 @ 0x44 │ │ bl 2710650 │ │ bl 26ffb60 │ │ - ldc2 10, cr10, [sp, #332]! @ 0x14c @ │ │ + ldc2 10, cr10, [sp, #512]! @ 0x200 @ │ │ ldc2 3, cr8, [pc, #476]! @ 264bd18 ::create(int&, icu_75::MeasureUnitImpl const&, UErrorCode&)@@Base+0xbc> │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #48 @ 0x30 │ │ mov r4, r1 │ │ ldr r6, [r0] │ │ ldr r1, [r0, #4] │ │ @@ -1853674,15 +1853674,15 @@ │ │ sxth r0, r5 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ blx 207deaa │ │ add r0, sp, #8 │ │ bl 2710d40 │ │ bl 26ffb60 │ │ - ldc2 2, cr10, [lr, #464]! @ 0x1d0 │ │ + ldc2 2, cr10, [lr, #644]! @ 0x284 │ │ │ │ 0264ddcc : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ ldrh r3, [r0] │ │ mov r4, r0 │ │ mov r0, #0 │ │ @@ -1855338,21 +1855338,21 @@ │ │ ldr r1, [r0] │ │ ldr r1, [r1, #4] │ │ blx r1 │ │ b 264f744 │ │ sub r0, fp, #52 @ 0x34 │ │ bl 2717370 │ │ bl 26ffb60 │ │ - ldc2 6, cr13, [ip, #232]! @ 0xe8 │ │ + ldc2 6, cr13, [ip, #412]! @ 0x19c │ │ ldc2 12, cr12, [pc, #148]! @ 264f7f0 │ │ ldc2 10, cr6, [pc, #716]! @ 264fa2c @ │ │ @ instruction: 0xffa2a7e8 │ │ stc2l 15, cr7, [r0, #640] @ 0x280 │ │ ldc2 8, cr7, [ip, #704]! @ 0x2c0 │ │ - ldc2 11, cr1, [sp, #260]! @ 0x104 @ │ │ + ldc2 11, cr1, [sp, #440]! @ 0x1b8 @ │ │ │ │ 0264f76c : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r1 │ │ cmp r1, #0 │ │ ldreq r4, [r0, #428] @ 0x1ac │ │ @@ -1855937,15 +1855937,15 @@ │ │ subs r6, r6, #96 @ 0x60 │ │ mov r4, r5 │ │ bne 2650014 │ │ mov r0, r8 │ │ bl 271a2a0 │ │ bl 26ffb60 │ │ andeq fp, lr, ip, ror #19 │ │ - ldc2 6, cr0, [sp, #596]! @ 0x254 │ │ + ldc2 6, cr0, [sp, #776]! @ 0x308 │ │ andeq fp, lr, ip, ror #18 │ │ │ │ 0265004c : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #80] @ 26500b0 │ │ @@ -1857323,20 +1857323,20 @@ │ │ bl 27103d0 │ │ sub r0, fp, #48 @ 0x30 │ │ bl 2710d40 │ │ sub r0, fp, #44 @ 0x2c │ │ bl 27128e0 │ │ bl 26ffb60 │ │ ldc2 12, cr2, [pc, #844]! @ 2651804 │ │ - ldc2 3, cr14, [ip, #196]! @ 0xc4 │ │ - ldc2 2, cr14, [ip, #900]! @ 0x384 │ │ + ldc2 3, cr14, [ip, #376]! @ 0x178 │ │ + ldc2 3, cr14, [ip, #56]! @ 0x38 │ │ ldc2 14, cr10, [lr, #524]! @ 0x20c │ │ - ldc2 2, cr5, [sp, #300]! @ 0x12c │ │ + ldc2 2, cr5, [sp, #480]! @ 0x1e0 │ │ ldc2 7, cr10, [pc, #100]! @ 2651530 │ │ - ldc2 4, cr1, [sp, #148]! @ 0x94 │ │ + ldc2 4, cr1, [sp, #328]! @ 0x148 │ │ strdeq sl, [lr], -r0 │ │ ldc2 5, cr10, [pc, #660]! @ 265176c │ │ ldc2 10, cr11, [pc, #40]! @ 2651504 @ │ │ ldc2 5, cr10, [pc, #84]! @ 2651534 │ │ andeq sl, lr, r0, ror r5 │ │ ldc2 8, cr11, [pc, #872]! @ 2651850 │ │ ldc2 11, cr14, [lr, #80]! @ 0x50 @ │ │ @@ -1857635,18 +1857635,18 @@ │ │ bl 2718ea0 │ │ add r0, sp, #72 @ 0x48 │ │ bl 2714160 │ │ bl 26ffb60 │ │ sub r0, fp, #344 @ 0x158 │ │ bl 2718e80 │ │ bl 26ffb60 │ │ - ldc2 14, cr14, [ip, #28]! │ │ + ldc2 14, cr14, [ip, #208]! @ 0xd0 │ │ andeq r9, lr, ip, ror #30 │ │ ldc2 14, cr4, [ip, #180]! @ 0xb4 │ │ - ldc2 9, cr1, [lr, #8]! @ │ │ + ldc2 9, cr1, [lr, #98]! @ 0x62 @ │ │ ldc2 12, cr3, [pc, #460]! @ 2651b78 │ │ andeq sl, lr, r8, asr r0 │ │ │ │ 026519ac : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #300 @ 0x12c │ │ @@ -1857828,17 +1857828,17 @@ │ │ bl 27103d0 │ │ mov r0, r4 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ mov r0, sp │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - ldc2 10, cr14, [ip, #84]! @ 0x54 @ │ │ - ldc2 10, cr14, [ip, #468]! @ 0x1d4 @ │ │ - ldc2 10, cr14, [ip, #36]! @ 0x24 @ │ │ + ldc2 10, cr14, [ip, #264]! @ 0x108 @ │ │ + ldc2 10, cr14, [ip, #648]! @ 0x288 @ │ │ + ldc2 10, cr14, [ip, #216]! @ 0xd8 @ │ │ andeq r2, lr, r4, asr #25 │ │ │ │ 02651ca0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #1012 @ 0x3f4 │ │ sub sp, sp, #2048 @ 0x800 │ │ @@ -1858437,20 +1858437,20 @@ │ │ sub r0, fp, #1072 @ 0x430 │ │ bl 2718ea0 │ │ sub r0, fp, #248 @ 0xf8 │ │ bl 2718ea0 │ │ sub r0, fp, #140 @ 0x8c │ │ bl 2718ea0 │ │ bl 26ffb60 │ │ - ldc2 2, cr12, [ip, #852]! @ 0x354 │ │ - ldc2 5, cr14, [ip, #988]! @ 0x3dc │ │ + ldc2 3, cr12, [ip, #8]! │ │ + ldc2 6, cr14, [ip, #144]! @ 0x90 │ │ andeq r9, lr, r0, ror #15 │ │ - ldc2 4, cr14, [ip, #108]! @ 0x6c │ │ + ldc2 4, cr14, [ip, #288]! @ 0x120 │ │ stc2l 5, cr5, [r0, #512] @ 0x200 │ │ - ldc2 2, cr14, [ip, #140]! @ 0x8c │ │ + ldc2 2, cr14, [ip, #320]! @ 0x140 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #460 @ 0x1cc │ │ add r8, r0, #8 │ │ mov r7, #0 │ │ mov r6, r0 │ │ strh r7, [r0, #4] │ │ @@ -1858725,19 +1858725,19 @@ │ │ sub r0, fp, #148 @ 0x94 │ │ bl 27141e0 │ │ mov r0, r9 │ │ bl 27103d0 │ │ mov r0, r8 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - ldc2 13, cr3, [sp, #604]! @ 0x25c │ │ + ldc2 13, cr3, [sp, #784]! @ 0x310 │ │ ldc2 11, cr12, [pc, #200]! @ 2652b60 @ │ │ ldc2 1, cr6, [ip, #376]! @ 0x178 │ │ ldc2 6, cr7, [lr, #712]! @ 0x2c8 │ │ - ldc2 15, cr11, [sp, #440]! @ 0x1b8 │ │ + ldc2 15, cr11, [sp, #620]! @ 0x26c │ │ andeq r8, lr, r4, asr #30 │ │ stc2l 1, cr5, [r0, #88] @ 0x58 │ │ stc2l 0, cr5, [r0, #360] @ 0x168 │ │ │ │ 02652aac : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -1859774,20 +1859774,20 @@ │ │ mov r1, #0 │ │ bl 2714f40 │ │ b 2653b04 │ │ mov r5, #10 │ │ b 26537c4 │ │ vcmla.f32 , q6, , #270 │ │ andeq r8, lr, r4, lsr #21 │ │ - ldc2 9, cr9, [sp, #200]! @ 0xc8 @ │ │ + ldc2 9, cr9, [sp, #290]! @ 0x122 @ │ │ ldc2 7, cr3, [ip, #196]! @ 0xc4 │ │ - ldc2 4, cr11, [ip, #356]! @ 0x164 │ │ + ldc2 4, cr11, [ip, #536]! @ 0x218 │ │ ldc2 7, cr3, [ip, #68]! @ 0x44 │ │ - ldc2 4, cr11, [ip, #244]! @ 0xf4 │ │ - ldc2 3, cr0, [lr, #816]! @ 0x330 │ │ + ldc2 4, cr11, [ip, #424]! @ 0x1a8 │ │ + ldc2 3, cr0, [lr, #996]! @ 0x3e4 │ │ movw r4, #65535 @ 0xffff │ │ add r0, sp, #320 @ 0x140 │ │ bl 2714160 │ │ sub r0, fp, #244 @ 0xf4 │ │ ldr r0, [r0, r7, lsl #2] │ │ cmp r0, #0 │ │ bne 2653b28 │ │ @@ -1860009,15 +1860009,15 @@ │ │ bl 2714cc0 │ │ mov r0, r4 │ │ bl 2714160 │ │ ldr r0, [fp, #12] │ │ mov r1, #16 │ │ str r1, [r0] │ │ b 2653d74 │ │ - ldc2 7, cr13, [ip, #900]! @ 0x384 │ │ + vcmla.f32 d13, d12, d14, #270 │ │ andeq r1, lr, r0, ror sl │ │ sub r6, fp, #244 @ 0xf4 │ │ sub r4, fp, #1392 @ 0x570 │ │ add r9, sp, #216 @ 0xd8 │ │ mov r0, #0 │ │ mov r5, #2 │ │ b 2653eec │ │ @@ -1860227,15 +1860227,15 @@ │ │ b 26542d0 │ │ sub lr, fp, #1024 @ 0x400 │ │ sub r0, lr, #440 @ 0x1b8 │ │ bl 27128e0 │ │ add r0, sp, #320 @ 0x140 │ │ bl 27103d0 │ │ b 2654278 │ │ - ldc2 15, cr11, [ip, #372]! @ 0x174 │ │ + ldc2 15, cr11, [ip, #552]! @ 0x228 │ │ add r0, sp, #320 @ 0x140 │ │ bl 2714160 │ │ add r0, sp, #1000 @ 0x3e8 │ │ bl 2714160 │ │ ldr r0, [sp, #76] @ 0x4c │ │ bl 2714160 │ │ ldr r0, [sp, #44] @ 0x2c │ │ @@ -1860306,18 +1860306,18 @@ │ │ sub r0, fp, #124 @ 0x7c │ │ bl 2714160 │ │ sub r0, fp, #60 @ 0x3c │ │ bl 2718e80 │ │ bl 26ffb60 │ │ stc2l 7, cr3, [r0, #864] @ 0x360 │ │ ldc2 15, cr1, [pc, #780]! @ 2654648 │ │ - ldc2 11, cr15, [sp, #560]! @ 0x230 @ │ │ + ldc2 11, cr15, [sp, #740]! @ 0x2e4 @ │ │ ldc2 14, cr2, [ip, #452]! @ 0x1c4 │ │ ldc2 4, cr4, [pc, #816]! @ 2654678 │ │ - ldc2 14, cr8, [sp, #844]! @ 0x34c │ │ + ldc2 15, cr8, [sp] │ │ ldc2 14, cr6, [ip, #288]! @ 0x120 │ │ stc2l 14, cr3, [r0, #720] @ 0x2d0 │ │ stc2l 8, cr3, [r0, #240] @ 0xf0 │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #112 @ 0x70 │ │ mov r5, r0 │ │ @@ -1860929,15 +1860929,15 @@ │ │ sub r0, fp, #32 │ │ bl 2710d40 │ │ bl 26ffb60 │ │ ldc2 0, cr15, [lr, #156]! @ 0x9c │ │ strdeq r6, [lr], -r0 │ │ ldc2 11, cr6, [pc, #4]! @ 2654cf0 @ │ │ ldc2 6, cr5, [lr, #32]! │ │ - ldc2 5, cr10, [ip, #772]! @ 0x304 │ │ + ldc2 5, cr10, [ip, #952]! @ 0x3b8 │ │ ldc2 10, cr6, [pc, #244]! @ 2654dec @ │ │ andeq r6, lr, r4, lsl #21 │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #312 @ 0x138 │ │ mov r4, r0 │ │ sub r0, fp, #144 @ 0x90 │ │ @@ -1861051,20 +1861051,20 @@ │ │ b 2654ec0 │ │ b 2654ec8 │ │ add r0, sp, #80 @ 0x50 │ │ bl 27141e0 │ │ sub r0, fp, #144 @ 0x90 │ │ bl 27141e0 │ │ bl 26ffb60 │ │ - ldc2 6, cr1, [sp, #1020]! @ 0x3fc │ │ + ldc2 7, cr1, [sp, #176]! @ 0xb0 │ │ ldc2 4, cr10, [pc, #616]! @ 2655148 │ │ ldc2 10, cr3, [ip, #792]! @ 0x318 @ │ │ ldc2 0, cr5, [lr, #152]! @ 0x98 │ │ - ldc2 6, cr5, [sp, #512]! @ 0x200 │ │ - ldc2 13, cr14, [sp, #556]! @ 0x22c │ │ + ldc2 6, cr5, [sp, #692]! @ 0x2b4 │ │ + ldc2 13, cr14, [sp, #736]! @ 0x2e0 │ │ ldrdeq r6, [lr], -r0 │ │ │ │ 02654ef0 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #720 @ 0x2d0 │ │ ldr r9, [fp, #8] │ │ @@ -1861174,15 +1861174,15 @@ │ │ bl 2714160 │ │ add r0, r8, #64 @ 0x40 │ │ bl 2714160 │ │ mov r0, r8 │ │ bl 2714160 │ │ bl 26ffb60 │ │ muleq lr, r8, r7 │ │ - ldc2 7, cr11, [ip, #84]! @ 0x54 │ │ + ldc2 7, cr11, [ip, #264]! @ 0x108 │ │ andeq r6, lr, r4, asr #14 │ │ │ │ 026550c0 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #720 @ 0x2d0 │ │ ldr r9, [fp, #12] │ │ @@ -1861308,15 +1861308,15 @@ │ │ mov r0, r8 │ │ bl 2714160 │ │ bl 26ffb60 │ │ mov r0, r5 │ │ bl 2714160 │ │ bl 26ffb60 │ │ andeq r6, lr, r8, asr #11 │ │ - ldc2 5, cr11, [ip, #292]! @ 0x124 │ │ + ldc2 5, cr11, [ip, #472]! @ 0x1d8 │ │ andeq r6, lr, r8, ror r5 │ │ │ │ 026552d0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #892 @ 0x37c │ │ str r0, [sp, #36] @ 0x24 │ │ @@ -1861538,15 +1861538,15 @@ │ │ bl 2714160 │ │ add r0, r4, #64 @ 0x40 │ │ bl 2714160 │ │ mov r0, r4 │ │ bl 2714160 │ │ bl 26ffb60 │ │ andeq r6, lr, ip, ror r3 │ │ - ldc2 1, cr3, [sp, #340]! @ 0x154 │ │ + ldc2 1, cr3, [sp, #520]! @ 0x208 │ │ ldc2 13, cr8, [lr, #932]! @ 0x3a4 │ │ stc2l 15, cr1, [r0, #808] @ 0x328 │ │ │ │ 02655664 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #128 @ 0x80 │ │ @@ -1862678,18 +1862678,18 @@ │ │ pop {r4, r5, r6, r7, fp, pc} │ │ mov r0, #9 │ │ b 265672c │ │ ldr r0, [fp, #-24] @ 0xffffffe8 │ │ str r0, [sp, #4] │ │ add r0, sp, #4 │ │ bl 26ffb60 │ │ - ldc2 10, cr7, [ip, #852]! @ 0x354 @ │ │ + ldc2 11, cr7, [ip, #8]! @ │ │ ldc2 5, cr1, [pc, #320]! @ 2656924 │ │ ldc2 14, cr3, [ip, #1008]! @ 0x3f0 │ │ - ldc2 15, cr5, [sp, #284]! @ 0x11c │ │ + ldc2 15, cr5, [sp, #464]! @ 0x1d0 │ │ push {fp, lr} │ │ mov fp, sp │ │ bl 27128e0 │ │ pop {fp, lr} │ │ b 2713d70 │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ @@ -1862817,18 +1862817,18 @@ │ │ b 2656898 │ │ ldr r0, [fp, #-24] @ 0xffffffe8 │ │ str r0, [sp, #12] │ │ add r0, sp, #12 │ │ bl 26ffb60 │ │ ldc2 3, cr1, [pc, #912]! @ 2656d94 │ │ ldc2 13, cr3, [ip, #576]! @ 0x240 │ │ - ldc2 13, cr5, [sp, #876]! @ 0x36c │ │ + ldc2 14, cr5, [sp, #32]! │ │ ldc2 3, cr11, [lr, #840]! @ 0x348 │ │ ldc2 3, cr11, [lr, #712]! @ 0x2c8 │ │ - ldc2 5, cr13, [sp, #144]! @ 0x90 │ │ + ldc2 5, cr13, [sp, #324]! @ 0x144 │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #24 │ │ ldr r5, [fp, #8] │ │ mov r6, r0 │ │ mov r0, r1 │ │ mov r1, r2 │ │ @@ -1862886,17 +1862886,17 @@ │ │ mov r2, r5 │ │ add r1, pc, r1 │ │ bl 27141a0 │ │ cmp r0, #0 │ │ movwne r0, #1 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2 4, cr1, [lr, #988]! @ 0x3dc │ │ - ldc2 4, cr1, [lr, #876]! @ 0x36c │ │ - ldc2 3, cr13, [sp, #560]! @ 0x230 │ │ + ldc2 5, cr1, [lr, #144]! @ 0x90 │ │ + ldc2 5, cr1, [lr, #32]! │ │ + ldc2 3, cr13, [sp, #740]! @ 0x2e4 │ │ │ │ 02656b24 : │ │ push {fp, lr} │ │ mov fp, sp │ │ sub sp, sp, #8 │ │ ldrh r2, [r1, #8] │ │ mov lr, #0 │ │ @@ -1862976,15 +1862976,15 @@ │ │ subs r6, r6, #96 @ 0x60 │ │ mov r4, r5 │ │ bne 2656c40 │ │ mov r0, r9 │ │ bl 271a2a0 │ │ bl 26ffb60 │ │ @ instruction: 0x000e4dbc │ │ - ldc2 10, cr9, [ip, #420]! @ 0x1a4 @ │ │ + ldc2 10, cr9, [ip, #600]! @ 0x258 @ │ │ andeq r4, lr, r0, asr #26 │ │ │ │ 02656c78 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ mov r4, r0 │ │ ldr r0, [pc, #244] @ 2656d80 │ │ @@ -1864330,15 +1864330,15 @@ │ │ pop {r4, r5, r6, r7, fp, pc} │ │ mov r0, r6 │ │ bl 2713d70 │ │ b 265808c │ │ add r0, sp, #4 │ │ bl 2711190 │ │ bl 26ffb60 │ │ - ldc2 11, cr13, [sp, #884]! @ 0x374 @ │ │ + ldc2 12, cr13, [sp, #40]! @ 0x28 │ │ │ │ 0265809c : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r1 │ │ ldr r1, [pc, #96] @ 2658110 │ │ mov r2, r4 │ │ @@ -1864362,15 +1864362,15 @@ │ │ mov r0, #7 │ │ str r0, [r4] │ │ mov r0, #0 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ mov r0, r5 │ │ bl 2713d70 │ │ bl 26ffb60 │ │ - ldc2 11, cr13, [sp, #308]! @ 0x134 @ │ │ + ldc2 11, cr13, [sp, #488]! @ 0x1e8 @ │ │ │ │ 02658114 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r3 │ │ mov r3, #1 │ │ cmp r1, #2 │ │ @@ -1865488,23 +1865488,23 @@ │ │ str r0, [sp, #44] @ 0x2c │ │ add r0, sp, #44 @ 0x2c │ │ bl 26ffb60 │ │ ldr r0, [sp, #68] @ 0x44 │ │ str r0, [sp, #60] @ 0x3c │ │ add r0, sp, #60 @ 0x3c │ │ bl 26ffb60 │ │ - ldc2 1, cr3, [ip, #992]! @ 0x3e0 │ │ + ldc2 2, cr3, [ip, #148]! @ 0x94 │ │ ldc2 14, cr13, [pc, #280]! @ 2659384 │ │ ldc2 10, cr14, [pc, #240]! @ 2659360 @ │ │ strdeq r0, [r0], -ip │ │ ldc2 5, cr14, [pc, #200]! @ 2659340 │ │ ldc2 9, cr14, [pc, #12]! @ 2659288 @ │ │ andeq r0, r0, r8, lsl #6 │ │ ldc2 4, cr13, [fp, #356]! @ 0x164 │ │ - ldc2 0, cr15, [sp, #340]! @ 0x154 │ │ + ldc2 0, cr15, [sp, #520]! @ 0x208 │ │ ldc2 13, cr14, [pc, #168]! @ 2659334 │ │ ldc2 14, cr13, [pc, #664]! @ 2659528 │ │ andeq r0, r0, r8, ror #12 │ │ ldrsh r1, [r0, #4] │ │ ldr r2, [r0, #8] │ │ cmp r1, #0 │ │ asrpl r2, r1, #5 │ │ @@ -1866175,15 +1866175,15 @@ │ │ add r0, sp, #44 @ 0x2c │ │ bl 2714160 │ │ bl 26ffb60 │ │ ldr r0, [fp, #-32] @ 0xffffffe0 │ │ str r0, [sp, #16] │ │ add r0, sp, #16 │ │ bl 26ffb60 │ │ - ldc2 0, cr3, [ip, #96]! @ 0x60 │ │ + ldc2 0, cr3, [ip, #276]! @ 0x114 │ │ ldc2 6, cr12, [lr, #480]! @ 0x1e0 │ │ ldc2 9, cr0, [ip, #124]! @ 0x7c @ │ │ ldc2 15, cr8, [fp, #952]! @ 0x3b8 │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r4, r0 │ │ @@ -1866518,19 +1866518,19 @@ │ │ bl 2712dd0 │ │ ldm sp, {r1, r2} │ │ mov r0, r4 │ │ mov r3, r6 │ │ bl 27108e0 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ - ldc2 0, cr6, [sp, #672]! @ 0x2a0 │ │ - ldc2 15, cr1, [ip] │ │ + ldc2 0, cr6, [sp, #852]! @ 0x354 │ │ + ldc2 15, cr1, [ip, #180]! @ 0xb4 │ │ ldc2 15, cr4, [pc, #984]! @ 265a638 │ │ vcmla.f32 , q15, , #270 │ │ - ldc2 2, cr0, [sp, #116]! @ 0x74 │ │ + ldc2 2, cr0, [sp, #296]! @ 0x128 │ │ │ │ 0265a264 : │ │ cmp r1, #0 │ │ movmi r0, #0 │ │ bxmi lr │ │ movw r2, #697 @ 0x2b9 │ │ ldrsb r2, [r0, r2] │ │ @@ -1868448,15 +1868448,15 @@ │ │ @ instruction: 0xffa1dc14 │ │ @ instruction: 0xffa1dbeb │ │ @ instruction: 0xffa1dbdc │ │ @ instruction: 0xffa1dbba │ │ @ instruction: 0xffa1db9e │ │ @ instruction: 0xffa1db6f │ │ @ instruction: 0xffa1db60 │ │ - ldc2 11, cr12, [ip, #100]! @ 0x64 @ │ │ + ldc2 11, cr12, [ip, #280]! @ 0x118 @ │ │ @ instruction: 0xffa1daab │ │ @ instruction: 0xffa1d9cc │ │ @ instruction: 0xffa1d96c │ │ @ instruction: 0xffa1d954 │ │ @ instruction: 0xffa1d8d0 │ │ @ instruction: 0xffa1d878 │ │ @ instruction: 0xffa1d860 │ │ @@ -1875634,15 +1875634,15 @@ │ │ bl 26ffb60 │ │ blx 207deaa │ │ andeq r8, sp, r0, ror #22 │ │ andeq r8, sp, r4, ror #22 │ │ strbeq fp, [r4, #724] @ 0x2d4 │ │ andeq r8, sp, r4, lsr #26 │ │ andeq r8, sp, r8, lsl sp │ │ - ldc2 9, cr5, [ip, #304]! @ 0x130 @ │ │ + ldc2 9, cr5, [ip, #394]! @ 0x18a @ │ │ andeq r2, sp, r8, lsr #6 │ │ ldc2 15, cr0, [lr, #460]! @ 0x1cc │ │ │ │ 02662bf8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #284 @ 0x11c │ │ @@ -1879699,24 +1879699,24 @@ │ │ mov r0, #11 │ │ pop {r4, sl, fp, pc} │ │ mov r0, #12 │ │ pop {r4, sl, fp, pc} │ │ mov r0, #13 │ │ pop {r4, sl, fp, pc} │ │ ldc2 5, cr7, [sp, #928]! @ 0x3a0 │ │ - ldc2 9, cr5, [ip, #322]! @ 0x142 @ │ │ + ldc2 9, cr5, [ip, #412]! @ 0x19c @ │ │ ldc2 12, cr14, [sp, #264]! @ 0x108 │ │ - ldc2 7, cr13, [fp, #164]! @ 0xa4 │ │ - ldc2 13, cr1, [ip, #216]! @ 0xd8 │ │ + ldc2 7, cr13, [fp, #344]! @ 0x158 │ │ + ldc2 13, cr1, [ip, #396]! @ 0x18c │ │ vcmla.f32 d8, d13, d5, #270 │ │ ldc2 2, cr13, [sp, #64]! @ 0x40 │ │ ldc2 8, cr8, [lr, #964]! @ 0x3c4 │ │ - ldc2 3, cr7, [fp, #856]! @ 0x358 │ │ + ldc2 4, cr7, [fp, #12]! │ │ ldc2 3, cr3, [sp, #480]! @ 0x1e0 │ │ - ldc2 3, cr7, [fp, #684]! @ 0x2ac │ │ + ldc2 3, cr7, [fp, #864]! @ 0x360 │ │ ldc2 1, cr13, [sp, #656]! @ 0x290 │ │ │ │ 02666a0c : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #32 │ │ add r0, sp, #7 │ │ @@ -1879879,23 +1879879,23 @@ │ │ b 2666c9c │ │ mov r4, #13 │ │ b 2666c9c │ │ mov r4, #14 │ │ mov r0, r4 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2 11, cr1, [ip, #712]! @ 0x2c8 @ │ │ + ldc2 11, cr1, [ip, #892]! @ 0x37c @ │ │ ldc2 4, cr13, [sp, #220]! @ 0xdc │ │ - ldc2 11, cr1, [ip, #588]! @ 0x24c @ │ │ - ldc2 4, cr7, [ip, #820]! @ 0x334 │ │ + ldc2 11, cr1, [ip, #768]! @ 0x300 @ │ │ + ldc2 4, cr7, [ip, #1000]! @ 0x3e8 │ │ ldc2 12, cr8, [lr, #88]! @ 0x58 │ │ ldc2 10, cr4, [lr, #756]! @ 0x2f4 @ │ │ - ldc2 2, cr15, [ip, #172]! @ 0xac │ │ - ldc2 1, cr7, [ip, #320]! @ 0x140 │ │ - ldc2 4, cr1, [sp, #660]! @ 0x294 │ │ + ldc2 2, cr15, [ip, #352]! @ 0x160 │ │ + ldc2 1, cr7, [ip, #500]! @ 0x1f4 │ │ + ldc2 4, cr1, [sp, #840]! @ 0x348 │ │ ldc2 8, cr15, [sl, #736]! @ 0x2e0 │ │ ldc2 1, cr11, [sp, #380]! @ 0x17c │ │ ldc2 8, cr13, [sl, #248]! @ 0xf8 │ │ ldc2 11, cr8, [lr, #128]! @ 0x80 @ │ │ ldc2 3, cr13, [sl, #808]! @ 0x328 │ │ ldc2 9, cr3, [fp, #418]! @ 0x1a2 @ │ │ │ │ @@ -1882681,15 +1882681,15 @@ │ │ add r0, sp, #28 │ │ b 2669608 │ │ mov r9, sl │ │ mov r0, r9 │ │ bl 2710990 │ │ bl 26ffb60 │ │ blx 207deaa │ │ - ldc2 0, cr7, [ip, #688]! @ 0x2b0 │ │ + ldc2 0, cr7, [ip, #868]! @ 0x364 │ │ ldc2 9, cr14, [sp, #376]! @ 0x178 @ │ │ strbeq r4, [r4, #2284] @ 0x8ec │ │ ldrsh r2, [r0, #4] │ │ ldr r1, [r0, #8] │ │ cmp r2, #0 │ │ asrpl r1, r2, #5 │ │ cmp r1, #2 │ │ @@ -1883046,15 +1883046,15 @@ │ │ add r0, sp, #72 @ 0x48 │ │ bl 2714160 │ │ bl 26ffb60 │ │ ldr r0, [fp, #-20] @ 0xffffffec │ │ str r0, [sp, #4] │ │ add r0, sp, #4 │ │ bl 26ffb60 │ │ - ldc2 6, cr4, [fp, #648]! @ 0x288 │ │ + ldc2 6, cr4, [fp, #828]! @ 0x33c │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #152 @ 0x98 │ │ add r6, sp, #80 @ 0x50 │ │ mov r5, r2 │ │ mov r4, r0 │ │ mvn r2, #0 │ │ @@ -1884193,15 +1884193,15 @@ │ │ ldrdeq r1, [sp], -r4 │ │ ldrdeq r1, [sp], -r0 │ │ muleq sp, r4, r8 │ │ muleq sp, r0, r8 │ │ andeq r1, sp, r0, asr r8 │ │ andeq r1, sp, ip, asr #16 │ │ strbeq r3, [r4, #4028] @ 0xfbc │ │ - ldc2 2, cr12, [fp, #428]! @ 0x1ac │ │ + ldc2 2, cr12, [fp, #608]! @ 0x260 │ │ ldr r3, [fp, #-36] @ 0xffffffdc │ │ str r0, [fp, #-40] @ 0xffffffd8 │ │ sub r2, fp, #40 @ 0x28 │ │ mov r0, r5 │ │ mov r1, #1 │ │ bl 2714270 │ │ ldr r0, [fp, #-40] @ 0xffffffd8 │ │ @@ -1884264,23 +1884264,23 @@ │ │ b 266af04 │ │ ldc2 15, cr6, [lr, #536]! @ 0x218 │ │ ldr r0, [r6] │ │ cmp r0, #0 │ │ movle r0, #7 │ │ strle r0, [r6] │ │ b 266aef4 │ │ - ldc2 2, cr8, [fp, #684]! @ 0x2ac │ │ + ldc2 2, cr8, [fp, #864]! @ 0x360 │ │ ldr r0, [r5] │ │ ldr r1, [r0, #4] │ │ mov r0, r5 │ │ blx r1 │ │ b 266aef4 │ │ - ldc2 6, cr14, [fp, #80]! @ 0x50 │ │ + ldc2 6, cr14, [fp, #260]! @ 0x104 │ │ ldc2 2, cr4, [sp, #904]! @ 0x388 │ │ - ldc2 0, cr14, [ip, #1020]! @ 0x3fc │ │ + ldc2 1, cr14, [ip, #176]! @ 0xb0 │ │ ldr r0, [r6] │ │ cmp r0, #0 │ │ movle r0, #7 │ │ strle r0, [r6] │ │ str r5, [r4, #84] @ 0x54 │ │ add r0, sp, #172 @ 0xac │ │ bl 2714160 │ │ @@ -1884294,15 +1884294,15 @@ │ │ sub r9, fp, #168 @ 0xa8 │ │ mov sl, #0 │ │ mov r5, #0 │ │ str r7, [sp, #28] │ │ b 266b044 │ │ ldc2 4, cr12, [sl, #1004]! @ 0x3ec │ │ ldc2 8, cr3, [lr, #64]! @ 0x40 │ │ - ldc2 11, cr6, [fp, #808]! @ 0x328 @ │ │ + ldc2 11, cr6, [fp, #988]! @ 0x3dc @ │ │ ldc2 13, cr5, [sp, #820]! @ 0x334 │ │ mvn r0, #0 │ │ add r4, sp, #236 @ 0xec │ │ str r0, [sp, #236] @ 0xec │ │ ldr r7, [pc, #3308] @ 266bc3c │ │ ldr r8, [pc, #3308] @ 266bc40 │ │ add r7, pc, r7 │ │ @@ -1884326,15 +1884326,15 @@ │ │ mov r0, r5 │ │ mov r2, r8 │ │ mov r3, r6 │ │ ldr r1, [pc, r1] │ │ bl 2713e10 │ │ b 266afcc │ │ ldc2 13, cr1, [sp, #992]! @ 0x3e0 │ │ - ldc2 6, cr14, [fp, #200]! @ 0xc8 │ │ + ldc2 6, cr14, [fp, #380]! @ 0x17c │ │ andeq r1, r0, r8, asr ip │ │ ldr r0, [r6] │ │ cmp r0, #0 │ │ movle r0, #7 │ │ strle r0, [r6] │ │ ldr r0, [sl, #76] @ 0x4c │ │ str r5, [r7, r0, lsl #2] │ │ @@ -1885121,19 +1885121,19 @@ │ │ sub r0, fp, #48 @ 0x30 │ │ bl 2711410 │ │ sub r0, fp, #44 @ 0x2c │ │ bl 2711410 │ │ bl 26ffb60 │ │ @ instruction: 0x000d04b8 │ │ @ instruction: 0x000d04b4 │ │ - ldc2 14, cr6, [fp, #532]! @ 0x214 │ │ + ldc2 14, cr6, [fp, #712]! @ 0x2c8 │ │ strdeq r0, [sp], -r8 │ │ strdeq r0, [sp], -r4 │ │ ldc2 4, cr6, [lr, #216]! @ 0xd8 │ │ - ldc2 6, cr5, [ip, #304]! @ 0x130 │ │ + ldc2 6, cr5, [ip, #484]! @ 0x1e4 │ │ muleq sp, r8, r8 │ │ muleq sp, r4, r8 │ │ strbeq r2, [r4, #3832] @ 0xef8 │ │ andeq r0, sp, ip, asr r7 │ │ andeq r0, sp, r8, lsl #14 │ │ strbeq r2, [r4, #1980] @ 0x7bc │ │ strbeq r2, [r4, #1980] @ 0x7bc │ │ @@ -1887715,16 +1887715,16 @@ │ │ mov r0, r5 │ │ mov r1, r6 │ │ mov r2, #0 │ │ mov r3, r4 │ │ bl 271b120 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2 14, cr15, [fp, #648]! @ 0x288 │ │ - ldc2 15, cr15, [sl, #836]! @ 0x344 │ │ + ldc2 14, cr15, [fp, #828]! @ 0x33c │ │ + ldc2 15, cr15, [sl, #1016]! @ 0x3f8 │ │ strbeq pc, [r3, #3292] @ 0xcdc @ │ │ strbeq pc, [r3, #3224] @ 0xc98 @ │ │ │ │ 0266e220 : │ │ mov r3, r2 │ │ mov r2, #0 │ │ b 271b120 │ │ @@ -1891240,15 +1891240,15 @@ │ │ bl 26ffb60 │ │ nop {0} │ │ @ instruction: 0xffc00000 │ │ ldrshmi pc, [pc, #255] @ 2671703 @ │ │ andeq r0, r0, r0 │ │ mvngt r0, r0 │ │ andeq sl, ip, r4, asr r5 │ │ - ldc2 2, cr15, [sl, #68]! @ 0x44 │ │ + ldc2 2, cr15, [sl, #248]! @ 0xf8 │ │ andeq sl, ip, ip, ror #3 │ │ nop {0} │ │ │ │ 02671618 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ vpush {d8} │ │ @@ -1891466,15 +1891466,15 @@ │ │ bl 26ffb60 │ │ nop {0} │ │ @ instruction: 0xffc00000 │ │ ldrshmi pc, [pc, #255] @ 2671a73 @ │ │ andeq r0, r0, r0 │ │ mvngt r0, r0 │ │ andeq sl, ip, ip, ror #3 │ │ - ldc2 14, cr14, [sl, #676]! @ 0x2a4 │ │ + ldc2 14, cr14, [sl, #856]! @ 0x358 │ │ andeq r9, ip, r4, lsl #29 │ │ nop {0} │ │ │ │ 02671988 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ @@ -1891610,15 +1891610,15 @@ │ │ bl 26ffb60 │ │ nop {0} │ │ @ instruction: 0xffc00000 │ │ ldrshmi pc, [pc, #255] @ 2671cab @ │ │ andeq r0, r0, r0 │ │ mvngt r0, r0 │ │ andeq r9, ip, r8, lsr #31 │ │ - ldc2 12, cr14, [sl, #404]! @ 0x194 │ │ + ldc2 12, cr14, [sl, #584]! @ 0x248 │ │ andeq r9, ip, ip, asr #24 │ │ │ │ 02671bbc : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #24 │ │ cmp r1, #0 │ │ @@ -1891801,15 +1891801,15 @@ │ │ mov r0, sp │ │ bl 2718890 │ │ bl 26ffb60 │ │ mov r0, sp │ │ bl 271a4f0 │ │ bl 26ffb60 │ │ andeq r9, ip, r8, lsl #25 │ │ - ldc2 9, cr14, [sl, #138]! @ 0x8a @ │ │ + ldc2 9, cr14, [sl, #228]! @ 0xe4 @ │ │ andeq r9, ip, r0, lsr #18 │ │ │ │ 02671e90 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ ldr r1, [r0, #352] @ 0x160 │ │ movw r4, #4296 @ 0x10c8 │ │ @@ -1891951,15 +1891951,15 @@ │ │ mov r0, sp │ │ bl 2718890 │ │ bl 26ffb60 │ │ mov r0, sp │ │ bl 271a4f0 │ │ bl 26ffb60 │ │ andeq r9, ip, r4, asr #20 │ │ - ldc2 7, cr14, [sl, #4]! │ │ + ldc2 7, cr14, [sl, #184]! @ 0xb8 │ │ ldrdeq r9, [ip], -ip │ │ │ │ 026720d8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #396 @ 0x18c │ │ ldr sl, [fp, #16] │ │ @@ -1892070,15 +1892070,15 @@ │ │ mov r0, sp │ │ bl 2718890 │ │ bl 26ffb60 │ │ mov r0, sp │ │ bl 271a4f0 │ │ bl 26ffb60 │ │ andeq r9, ip, r4, ror #16 │ │ - ldc2 5, cr14, [sl, #132]! @ 0x84 │ │ + ldc2 5, cr14, [sl, #312]! @ 0x138 │ │ andeq r9, ip, r8, lsl #10 │ │ │ │ 026722ac : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #396 @ 0x18c │ │ ldr r8, [fp, #12] │ │ @@ -1892172,15 +1892172,15 @@ │ │ mov r0, sp │ │ bl 2718890 │ │ bl 26ffb60 │ │ mov r0, sp │ │ bl 271a4f0 │ │ bl 26ffb60 │ │ muleq ip, ip, r6 │ │ - ldc2 3, cr14, [sl, #356]! @ 0x164 │ │ + ldc2 3, cr14, [sl, #536]! @ 0x218 │ │ andeq r9, ip, ip, lsr r3 │ │ │ │ 0267243c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #396 @ 0x18c │ │ ldr r8, [fp, #8] │ │ @@ -1892272,15 +1892272,15 @@ │ │ mov r0, sp │ │ bl 2718890 │ │ bl 26ffb60 │ │ mov r0, sp │ │ bl 271a4f0 │ │ bl 26ffb60 │ │ andeq r9, ip, ip, lsl #10 │ │ - ldc2 1, cr14, [sl, #804]! @ 0x324 │ │ + ldc2 1, cr14, [sl, #984]! @ 0x3d8 │ │ @ instruction: 0x000c91b4 │ │ │ │ 026725c4 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #388 @ 0x184 │ │ ldr r9, [fp, #8] │ │ @@ -1892375,15 +1892375,15 @@ │ │ mov r0, sp │ │ bl 2718890 │ │ bl 26ffb60 │ │ mov r0, sp │ │ bl 271a4f0 │ │ bl 26ffb60 │ │ andeq r9, ip, r4, lsl #7 │ │ - ldc2 0, cr14, [sl, #260]! @ 0x104 │ │ + ldc2 0, cr14, [sl, #440]! @ 0x1b8 │ │ andeq r9, ip, r0, lsr #32 │ │ │ │ 02672758 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #236 @ 0xec │ │ mov r6, r1 │ │ @@ -1894364,15 +1894364,15 @@ │ │ mov r0, sp │ │ bl 2718890 │ │ bl 26ffb60 │ │ mov r0, sp │ │ bl 271a4f0 │ │ bl 26ffb60 │ │ andeq r7, ip, ip, ror r5 │ │ - ldc2 2, cr12, [sl, #228]! @ 0xe4 │ │ + ldc2 2, cr12, [sl, #408]! @ 0x198 │ │ │ │ 026744c0 : │ │ ldr r3, [r1] │ │ mov r2, r0 │ │ mov r0, #0 │ │ cmp r3, #0 │ │ bxgt lr │ │ @@ -1907215,15 +1907215,15 @@ │ │ bl 271b010 │ │ bl 26ffb60 │ │ b 2680618 │ │ andeq fp, fp, r0, lsr r7 │ │ andeq fp, fp, r0, lsr #6 │ │ andeq r5, fp, r8, lsl #14 │ │ ldc2 0, cr6, [r9, #416]! @ 0x1a0 │ │ - ldc2 14, cr15, [sl, #588]! @ 0x24c │ │ + ldc2 14, cr15, [sl, #768]! @ 0x300 │ │ │ │ 0268063c : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ vpush {d8-d9} │ │ mov r6, r1 │ │ mov r4, r0 │ │ @@ -1907816,16 +1907816,16 @@ │ │ ldr r0, [sp, #84] @ 0x54 │ │ str r0, [sp, #16] │ │ add r0, sp, #16 │ │ bl 26ffb60 │ │ add r0, sp, #88 @ 0x58 │ │ bl 2714160 │ │ bl 26ffb60 │ │ - ldc2 7, cr15, [r9, #596]! @ 0x254 │ │ - vcmla.f32 , , , #270 │ │ + ldc2 7, cr15, [r9, #776]! @ 0x308 │ │ + ldc2 9, cr15, [r9, #28]! @ │ │ │ │ 02680f3c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #92 @ 0x5c │ │ mov r9, r0 │ │ cmp r2, #0 │ │ @@ -1909640,15 +1909640,15 @@ │ │ mov r0, r5 │ │ bl 2713e90 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ add r0, sp, #12 │ │ bl 2711190 │ │ bl 26ffb60 │ │ - ldc2 5, cr11, [r9, #472]! @ 0x1d8 │ │ + ldc2 5, cr11, [r9, #652]! @ 0x28c │ │ ldc2 7, cr12, [ip, #516]! @ 0x204 │ │ │ │ 02682afc : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #72 @ 0x48 │ │ mov r4, r0 │ │ @@ -1919342,15 +1919342,15 @@ │ │ bl 26ffb60 │ │ add r0, sp, #112 @ 0x70 │ │ bl 2714160 │ │ add r0, sp, #176 @ 0xb0 │ │ bl 271a4f0 │ │ bl 26ffb60 │ │ andeq pc, sl, ip, asr #31 │ │ - ldc2 12, cr4, [r9, #484]! @ 0x1e4 │ │ + ldc2 12, cr4, [r9, #664]! @ 0x298 │ │ andeq pc, sl, r8, asr ip @ │ │ andeq pc, sl, r8, ror #30 │ │ andeq pc, sl, ip, lsr #27 │ │ │ │ 0268bd14 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ @@ -1924797,15 +1924797,15 @@ │ │ b 2690fe8 │ │ mov r0, r5 │ │ bl 2711190 │ │ b 2690ff4 │ │ mov r0, r4 │ │ bl 2716490 │ │ bl 26ffb60 │ │ - ldc2 7, cr15, [r8, #868]! @ 0x364 │ │ + vcmla.f32 d15, d8, d6, #270 │ │ andeq sl, sl, r0, lsr #24 │ │ │ │ 02691008 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ mov r4, r0 │ │ ldr r0, [r2] │ │ @@ -1929677,21 +1929677,21 @@ │ │ add r0, sp, #240 @ 0xf0 │ │ bl 27103d0 │ │ sub r0, fp, #248 @ 0xf8 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ b 2695aa4 │ │ ldc2 10, cr4, [sl, #712]! @ 0x2c8 @ │ │ - ldc2 15, cr2, [r9, #612]! @ 0x264 │ │ + ldc2 15, cr2, [r9, #792]! @ 0x318 │ │ ldc2 0, cr1, [r8, #696]! @ 0x2b8 │ │ ldc2 0, cr1, [r8, #200]! @ 0xc8 │ │ ldc2 15, cr0, [r8, #776]! @ 0x308 │ │ ldc2 15, cr0, [r8, #328]! @ 0x148 │ │ ldc2 14, cr0, [r8, #904]! @ 0x388 │ │ - ldc2 13, cr2, [r9, #132]! @ 0x84 │ │ + ldc2 13, cr2, [r9, #312]! @ 0x138 │ │ ldc2 12, cr0, [r8, #328]! @ 0x148 │ │ ldc2 11, cr0, [r8, #472]! @ 0x1d8 @ │ │ │ │ 02695ae4 : │ │ ldr r3, [r0, #8] │ │ ldr r0, [r0, #4] │ │ ldrb r2, [r3, #16] │ │ @@ -1939552,28 +1939552,28 @@ │ │ bl 2711190 │ │ bl 26ffb60 │ │ strbeq pc, [r0, #492] @ 0x1ec @ │ │ strbeq pc, [r0, #428] @ 0x1ac @ │ │ ldc2 4, cr0, [fp, #356]! @ 0x164 │ │ ldc2 1, cr5, [r7, #700]! @ 0x2bc │ │ andeq r7, r9, r4, ror #9 │ │ - ldc2 1, cr9, [r9, #204]! @ 0xcc │ │ - ldc2 4, cr3, [r8, #392]! @ 0x188 │ │ + ldc2 1, cr9, [r9, #384]! @ 0x180 │ │ + ldc2 4, cr3, [r8, #572]! @ 0x23c │ │ ldc2 14, cr2, [sl, #12]! │ │ ldc2 8, cr14, [sl, #324]! @ 0x144 │ │ ldc2 15, cr12, [r9, #556]! @ 0x22c │ │ ldc2 11, cr0, [sl, #784]! @ 0x310 @ │ │ - ldc2 4, cr11, [r8, #848]! @ 0x350 │ │ + ldc2 5, cr11, [r8, #4]! │ │ ldc2 1, cr11, [r9, #796]! @ 0x31c │ │ ldc2 5, cr6, [sl, #168]! @ 0xa8 │ │ - ldc2 0, cr9, [r9, #396]! @ 0x18c │ │ - ldc2 0, cr15, [r8, #176]! @ 0xb0 │ │ + ldc2 0, cr9, [r9, #576]! @ 0x240 │ │ + ldc2 0, cr15, [r8, #356]! @ 0x164 │ │ andeq r7, r9, r4, lsl #10 │ │ - ldc2 13, cr6, [r9, #44]! @ 0x2c │ │ - ldc2 14, cr15, [r8, #860]! @ 0x35c │ │ + ldc2 13, cr6, [r9, #224]! @ 0xe0 │ │ + ldc2 15, cr15, [r8, #16]! │ │ │ │ 0269f1e4 : │ │ ldr r1, [r0] │ │ ldr r1, [r1, #20] │ │ bx r1 │ │ │ │ 0269f1f0 : │ │ @@ -1939872,16 +1939872,16 @@ │ │ b 269f648 │ │ b 269f648 │ │ sub r0, fp, #144 @ 0x90 │ │ bl 27141e0 │ │ bl 26ffb60 │ │ strbeq lr, [r0, #2712] @ 0xa98 │ │ strbeq lr, [r0, #2688] @ 0xa80 │ │ - ldc2 10, cr2, [r9, #944]! @ 0x3b0 @ │ │ - ldc2 11, cr12, [r7, #64]! @ 0x40 @ │ │ + ldc2 11, cr2, [r9, #100]! @ 0x64 @ │ │ + ldc2 11, cr12, [r7, #244]! @ 0xf4 @ │ │ ldc2 14, cr5, [sl, #500]! @ 0x1f4 │ │ strbeq lr, [r0, #2472] @ 0x9a8 │ │ strbeq lr, [r0, #2364] @ 0x93c │ │ strbeq lr, [r0, #2256] @ 0x8d0 │ │ strbeq lr, [r0, #2220] @ 0x8ac │ │ andeq r0, r0, r0, lsl #25 │ │ strbeq lr, [r0, #2564] @ 0xa04 │ │ @@ -1940638,16 +1940638,16 @@ │ │ pop {r4, sl, fp, pc} │ │ movw r0, #4098 @ 0x1002 │ │ pop {r4, sl, fp, pc} │ │ movw r0, #4099 @ 0x1003 │ │ pop {r4, sl, fp, pc} │ │ ldc2 7, cr8, [r7, #744]! @ 0x2e8 │ │ ldc2 7, cr8, [r7, #672]! @ 0x2a0 │ │ - ldc2 2, cr8, [r9, #632]! @ 0x278 │ │ - ldc2 14, cr11, [r7, #792]! @ 0x318 │ │ + ldc2 2, cr8, [r9, #812]! @ 0x32c │ │ + ldc2 14, cr11, [r7, #972]! @ 0x3cc │ │ ldc2 10, cr3, [r7, #964]! @ 0x3c4 @ │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ ldr r0, [pc, #184] @ 26a01f8 │ │ ldr r0, [pc, r0] │ │ cmp r0, #0 │ │ beq 26a0164 │ │ @@ -1940940,15 +1940940,15 @@ │ │ bl 2713d70 │ │ b 26a05a0 │ │ add r0, sp, #4 │ │ bl 2711190 │ │ bl 26ffb60 │ │ andeq fp, r9, r0, ror #2 │ │ andeq fp, r9, r0, ror #2 │ │ - ldc2 1, cr0, [r8, #484]! @ 0x1e4 │ │ + ldc2 1, cr0, [r8, #664]! @ 0x298 │ │ │ │ 026a05b8 : │ │ ldr r1, [r1] │ │ ldr r0, [r0, #76] @ 0x4c │ │ cmp r1, #0 │ │ movwgt r0, #0 │ │ bx lr │ │ @@ -1941113,15 +1941113,15 @@ │ │ b 26a0818 │ │ ldr r0, [sp, #12] │ │ str r0, [sp, #4] │ │ add r0, sp, #4 │ │ bl 26ffb60 │ │ ldc2 3, cr6, [fp, #712]! @ 0x2c8 │ │ andeq fp, r9, r0, asr #32 │ │ - ldc2 7, cr1, [r9, #800]! @ 0x320 │ │ + ldc2 7, cr1, [r9, #980]! @ 0x3d4 │ │ andeq sl, r9, ip, ror #31 │ │ │ │ 026a0838 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [r0] │ │ @@ -1941159,18 +1941159,18 @@ │ │ str r0, [r5] │ │ pop {r4, r5, fp, pc} │ │ ldr r1, [pc, #40] @ 26a08fc │ │ mov r0, #28 │ │ add r1, pc, r1 │ │ pop {r4, r5, fp, lr} │ │ b 271d260 │ │ - ldc2 6, cr1, [r9, #976]! @ 0x3d0 │ │ + ldc2 7, cr1, [r9, #132]! @ 0x84 │ │ ldc2 5, cr9, [r9, #360]! @ 0x168 │ │ strbeq sp, [r0, #1628] @ 0x65c │ │ - ldc2 11, cr5, [r8, #684]! @ 0x2ac @ │ │ + ldc2 11, cr5, [r8, #864]! @ 0x360 @ │ │ strbeq sp, [r0, #1600] @ 0x640 │ │ strbeq sp, [r0, #1588] @ 0x634 │ │ strbeq sp, [r0, #1560] @ 0x618 │ │ andeq r0, r0, r4, lsr #32 │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ ldr r0, [pc, #72] @ 26a0958 │ │ @@ -1941280,18 +1941280,18 @@ │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ str r5, [sp, #8] │ │ add r0, sp, #8 │ │ bl 26ffb60 │ │ strbeq sp, [r0, #1368] @ 0x558 │ │ strbeq sp, [r0, #1340] @ 0x53c │ │ - ldc2 5, cr1, [r9, #544]! @ 0x220 │ │ + ldc2 5, cr1, [r9, #724]! @ 0x2d4 │ │ ldc2 3, cr9, [r9, #952]! @ 0x3b8 │ │ strbeq sp, [r0, #1264] @ 0x4f0 │ │ - ldc2 10, cr5, [r8, #252]! @ 0xfc @ │ │ + ldc2 10, cr5, [r8, #432]! @ 0x1b0 @ │ │ strbeq sp, [r0, #1236] @ 0x4d4 │ │ strbeq sp, [r0, #1224] @ 0x4c8 │ │ strbeq sp, [r0, #1196] @ 0x4ac │ │ @ instruction: 0xfffffea4 │ │ strbeq sp, [r0, #1116] @ 0x45c │ │ strbeq sp, [r0, #1104] @ 0x450 │ │ │ │ @@ -1941392,17 +1941392,17 @@ │ │ add r0, sp, #12 │ │ bl 2710d40 │ │ add r0, sp, #16 │ │ bl 2710d40 │ │ add r0, sp, #20 │ │ bl 2710d40 │ │ bl 26ffb60 │ │ - ldc2 3, cr1, [r9, #992]! @ 0x3e0 │ │ + ldc2 4, cr1, [r9, #148]! @ 0x94 │ │ @ instruction: 0xff9db32f │ │ - vcmla.f32 , , , #270 │ │ + ldc2 9, cr15, [r7, #56]! @ 0x38 @ │ │ │ │ 026a0c80 ::createObject(void const*, UErrorCode&) const@@Base>: │ │ mov r0, r1 │ │ ldr r1, [r1, #456] @ 0x1c8 │ │ cmp r1, #0 │ │ beq 26a0cb0 ::createObject(void const*, UErrorCode&) const@@Base+0x30> │ │ ldr r1, [r0, #460] @ 0x1cc │ │ @@ -1941630,17 +1941630,17 @@ │ │ b 26a0fec │ │ mov r0, r9 │ │ bl 2711190 │ │ b 26a0ff8 │ │ mov r0, r8 │ │ bl 2711190 │ │ bl 26ffb60 │ │ - ldc2 3, cr7, [r8, #372]! @ 0x174 │ │ - ldc2 2, cr5, [r9, #88]! @ 0x58 │ │ - ldc2 3, cr7, [r8, #4]! │ │ + ldc2 3, cr7, [r8, #552]! @ 0x228 │ │ + ldc2 2, cr5, [r9, #268]! @ 0x10c │ │ + ldc2 3, cr7, [r8, #184]! @ 0xb8 │ │ │ │ 026a1010 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [r0, #464] @ 0x1d0 │ │ bl 2713e90 │ │ @@ -1941743,16 +1941743,16 @@ │ │ add r0, sp, #8 │ │ bl 2711190 │ │ b 26a11ac │ │ b 26a11ac │ │ add r0, sp, #212 @ 0xd4 │ │ bl 2711190 │ │ bl 26ffb60 │ │ - ldc2 14, cr0, [r9, #768]! @ 0x300 │ │ - ldc2 1, cr7, [r8, #500]! @ 0x1f4 │ │ + ldc2 14, cr0, [r9, #948]! @ 0x3b4 │ │ + ldc2 1, cr7, [r8, #680]! @ 0x2a8 │ │ │ │ 026a11c0 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #16 │ │ mov r5, r0 │ │ ldr r0, [r1] │ │ @@ -1941887,19 +1941887,19 @@ │ │ mov r1, r0 │ │ b 26a11e4 │ │ blx 207deaa │ │ add r0, sp, #8 │ │ bl 2710d40 │ │ bl 26ffb60 │ │ @ instruction: 0xff9dac9f │ │ - ldc2 15, cr4, [r9, #376]! @ 0x178 │ │ + ldc2 15, cr4, [r9, #556]! @ 0x22c │ │ ldc2 10, cr0, [fp, #32]! @ │ │ ldc2 13, cr8, [r9, #940]! @ 0x3ac │ │ ldc2 9, cr0, [fp, #88]! @ 0x58 @ │ │ - ldc2 15, cr6, [r8, #4]! │ │ + ldc2 15, cr6, [r8, #184]! @ 0xb8 │ │ ldc2 14, cr8, [r9, #332]! @ 0x14c │ │ ldc2 9, cr0, [fp, #288]! @ 0x120 @ │ │ │ │ 026a140c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #428 @ 0x1ac │ │ @@ -1942110,19 +1942110,19 @@ │ │ b 26a1750 │ │ blx 207deaa │ │ sub r0, fp, #36 @ 0x24 │ │ bl 2710d40 │ │ bl 26ffb60 │ │ ldc2 12, cr8, [r9, #844]! @ 0x34c │ │ ldc2 6, cr0, [fp, #560]! @ 0x230 │ │ - ldc2 12, cr6, [r8, #260]! @ 0x104 │ │ - ldc2 13, cr6, [r8, #324]! @ 0x144 │ │ + ldc2 12, cr6, [r8, #440]! @ 0x1b8 │ │ + ldc2 13, cr6, [r8, #504]! @ 0x1f8 │ │ ldc2 8, cr8, [r9, #88]! @ 0x58 │ │ ldc2 7, cr0, [fp, #16]! │ │ - ldc2 11, cr6, [r8, #1012]! @ 0x3f4 @ │ │ + ldc2 12, cr6, [r8, #168]! @ 0xa8 │ │ │ │ 026a1778 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #452 @ 0x1c4 │ │ mov r6, r0 │ │ ldr r0, [r1] │ │ @@ -1942366,21 +1942366,21 @@ │ │ sub r0, fp, #36 @ 0x24 │ │ bl 2710d40 │ │ ldr r0, [r4] │ │ ldr r1, [r0, #4] │ │ mov r0, r4 │ │ blx r1 │ │ bl 26ffb60 │ │ - ldc2 11, cr14, [r8, #296]! @ 0x128 @ │ │ - ldc2 12, cr14, [r7, #380]! @ 0x17c │ │ - ldc2 6, cr0, [r9, #384]! @ 0x180 │ │ + ldc2 11, cr14, [r8, #476]! @ 0x1dc @ │ │ + ldc2 12, cr14, [r7, #560]! @ 0x230 │ │ + ldc2 6, cr0, [r9, #564]! @ 0x234 │ │ ldc2 11, cr4, [r7, #364]! @ 0x16c @ │ │ ldc2 3, cr0, [fp, #304]! @ 0x130 │ │ - ldc2 8, cr6, [r8, #964]! @ 0x3c4 │ │ - ldc2 8, cr6, [r8, #724]! @ 0x2d4 │ │ + ldc2 9, cr6, [r8, #60]! @ 0x3c @ │ │ + vcmla.f32 q3, q12, q9, #270 │ │ │ │ 026a1b78 : │ │ ldr r1, [r2] │ │ cmp r1, #0 │ │ movgt r0, #0 │ │ bxgt lr │ │ push {r4, r5, fp, lr} │ │ @@ -1942650,16 +1942650,16 @@ │ │ ldr r0, [pc, #24] @ 26a1f88 │ │ mov r2, r1 │ │ ldr r3, [pc, #20] @ 26a1f8c │ │ add r0, pc, r0 │ │ add r3, pc, r3 │ │ mov r1, r3 │ │ b 2715370 │ │ - ldc2 3, cr6, [r8, #532]! @ 0x214 │ │ - ldc2 15, cr15, [r8, #896]! @ 0x380 │ │ + ldc2 3, cr6, [r8, #712]! @ 0x2c8 │ │ + ldc2 0, cr0, [r9, #52]! @ 0x34 │ │ @ instruction: 0xff9d9f27 │ │ │ │ 026a1f90 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #16 │ │ ldr r0, [pc, #276] @ 26a20b8 │ │ @@ -1942729,15 +1942729,15 @@ │ │ bl 26a20c8 │ │ b 26a20ac │ │ mov r0, sp │ │ bl 27128e0 │ │ add r0, sp, #12 │ │ bl 2710d40 │ │ bl 26ffb60 │ │ - ldc2 15, cr15, [r8, #688]! @ 0x2b0 │ │ + ldc2 15, cr15, [r8, #868]! @ 0x364 │ │ andeq r4, r9, r0, asr r4 │ │ @ instruction: 0xff9d9ec3 │ │ ldrdeq r4, [r9], -r0 │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ ldr r1, [pc, #36] @ 26a20fc │ │ mov r4, r0 │ │ @@ -1942766,15 +1942766,15 @@ │ │ mov r2, ip │ │ ldr r5, [fp, #12] │ │ mov r3, lr │ │ str r5, [sp, #16] │ │ bl 2715360 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2 14, cr15, [r8, #240]! @ 0xf0 │ │ + ldc2 14, cr15, [r8, #420]! @ 0x1a4 │ │ @ instruction: 0xff9d9d7f │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ ldr r1, [pc, #40] @ 26a2184 │ │ mov r4, r0 │ │ ldr r0, [r0, #4] │ │ add r1, pc, r1 │ │ @@ -1942937,15 +1942937,15 @@ │ │ str r0, [sp, #4] │ │ add r0, sp, #4 │ │ b 26a23e4 │ │ b 26a23e4 │ │ add r0, sp, #72 @ 0x48 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - ldc2 14, cr3, [r9, #968]! @ 0x3c8 │ │ + ldc2 15, cr3, [r9, #124]! @ 0x7c │ │ vcmla.f32 , , , #270 │ │ │ │ 026a23f8 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r2 │ │ ldr r2, [pc, #92] @ 26a2468 │ │ @@ -1943180,16 +1943180,16 @@ │ │ ldr r3, [sp, #24] │ │ mov r4, r0 │ │ ldr r1, [sp, #8] │ │ ldr r2, [sp, #20] │ │ str r1, [r0, #4] │ │ strd r2, [r0, #16] │ │ b 26a2714 │ │ - ldc2 7, cr11, [r8, #672]! @ 0x2a0 │ │ - ldc2 13, cr7, [r8, #144]! @ 0x90 │ │ + ldc2 7, cr11, [r8, #852]! @ 0x354 │ │ + ldc2 13, cr7, [r8, #324]! @ 0x144 │ │ │ │ 026a277c : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #40 @ 0x28 │ │ mov r6, r0 │ │ ldr r0, [r1] │ │ @@ -1943327,19 +1943327,19 @@ │ │ ldr r1, [r0, #4] │ │ mov r0, r4 │ │ blx r1 │ │ bl 26ffb60 │ │ mov r0, r4 │ │ bl 2713d70 │ │ bl 26ffb60 │ │ - ldc2 5, cr11, [r8, #656]! @ 0x290 │ │ - ldc2 11, cr7, [r8, #128]! @ 0x80 @ │ │ - ldc2 7, cr15, [r8, #48]! @ 0x30 │ │ - ldc2 6, cr11, [r8, #560]! @ 0x230 │ │ - ldc2 12, cr7, [r8, #32]! │ │ + ldc2 5, cr11, [r8, #836]! @ 0x344 │ │ + ldc2 11, cr7, [r8, #308]! @ 0x134 @ │ │ + ldc2 7, cr15, [r8, #228]! @ 0xe4 │ │ + ldc2 6, cr11, [r8, #740]! @ 0x2e4 │ │ + ldc2 12, cr7, [r8, #212]! @ 0xd4 │ │ andeq r8, r9, ip, asr pc │ │ andeq r0, r0, r0, lsl #2 │ │ strbeq fp, [r0, #1492] @ 0x5d4 │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r0, [pc, #60] @ 26a2a24 │ │ ldr r0, [pc, r0] │ │ @@ -1944308,15 +1944308,15 @@ │ │ mov r0, r8 │ │ bl 2711190 │ │ mov r0, r5 │ │ bl 2714160 │ │ mov r0, r4 │ │ bl 2712ca0 │ │ bl 26ffb60 │ │ - ldc2 14, cr12, [r7, #788]! @ 0x314 │ │ + ldc2 14, cr12, [r7, #968]! @ 0x3c8 │ │ andeq r8, r9, ip, lsr #32 │ │ andeq r7, r9, r0, ror #29 │ │ muleq r9, ip, pc @ │ │ │ │ 026a38dc : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ @@ -1955258,15 +1955258,15 @@ │ │ mov r0, r4 │ │ str r5, [r4, #224] @ 0xe0 │ │ sub sp, fp, #8 │ │ pop {r4, r5, fp, pc} │ │ mov r0, r4 │ │ bl 2716490 │ │ bl 26ffb60 │ │ - vcmla.f32 d2, d23, d21, #270 │ │ + ldc2 8, cr2, [r7, #840]! @ 0x348 │ │ andeq sp, r8, ip, ror #25 │ │ │ │ 026ade24 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #16 │ │ mov r7, r2 │ │ @@ -1955302,15 +1955302,15 @@ │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ mov r0, r5 │ │ bl 2711190 │ │ b 26adeb8 │ │ mov r0, r4 │ │ bl 2716490 │ │ bl 26ffb60 │ │ - vcmla.f32 d2, d7, d21, #270 │ │ + ldc2 8, cr2, [r7, #328]! @ 0x148 │ │ andeq sp, r8, ip, ror #24 │ │ │ │ 026adecc : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #580 @ 0x244 │ │ ldr r5, [fp, #16] │ │ @@ -1955460,15 +1955460,15 @@ │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ mov r0, r6 │ │ bl 2711190 │ │ b 26ae120 │ │ mov r0, r4 │ │ bl 2716490 │ │ bl 26ffb60 │ │ - ldc2 5, cr2, [r7, #772]! @ 0x304 │ │ + ldc2 5, cr2, [r7, #952]! @ 0x3b8 │ │ andeq sp, r8, r8, lsl #20 │ │ │ │ 026ae134 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #16 │ │ mov r5, r3 │ │ @@ -1955506,15 +1955506,15 @@ │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ mov r0, r6 │ │ bl 2711190 │ │ b 26ae1d0 │ │ mov r0, r4 │ │ bl 2716490 │ │ bl 26ffb60 │ │ - ldc2 5, cr2, [r7, #68]! @ 0x44 │ │ + ldc2 5, cr2, [r7, #248]! @ 0xf8 │ │ andeq sp, r8, r8, asr r9 │ │ │ │ 026ae1e4 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #16 │ │ mov r8, r3 │ │ @@ -1955553,15 +1955553,15 @@ │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ mov r0, r7 │ │ bl 2711190 │ │ b 26ae284 │ │ mov r0, r4 │ │ bl 2716490 │ │ bl 26ffb60 │ │ - ldc2 4, cr2, [r7, #388]! @ 0x184 │ │ + ldc2 4, cr2, [r7, #568]! @ 0x238 │ │ andeq sp, r8, r8, lsr #17 │ │ │ │ 026ae298 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #16 │ │ mov r9, r3 │ │ @@ -1955599,15 +1955599,15 @@ │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ mov r0, r5 │ │ bl 2711190 │ │ b 26ae334 │ │ mov r0, r4 │ │ bl 2716490 │ │ bl 26ffb60 │ │ - ldc2 3, cr2, [r7, #692]! @ 0x2b4 │ │ + ldc2 3, cr2, [r7, #872]! @ 0x368 │ │ strdeq sp, [r8], -r4 │ │ │ │ 026ae348 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #52 @ 0x34 │ │ ldr r4, [fp, #12] │ │ @@ -1955786,15 +1955786,15 @@ │ │ ldr r1, [r0, #4] │ │ mov r0, r8 │ │ blx r1 │ │ bl 26ffb60 │ │ mov r0, r8 │ │ bl 2713d70 │ │ bl 26ffb60 │ │ - ldc2 7, cr5, [r8, #296]! @ 0x128 │ │ + ldc2 7, cr5, [r8, #476]! @ 0x1dc │ │ │ │ 026ae628 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ mov r4, r0 │ │ ldr r0, [pc, #360] @ 26ae7a4 │ │ mov r5, r3 │ │ @@ -1955886,15 +1955886,15 @@ │ │ bl 2714600 │ │ b 26ae798 │ │ mov r0, r4 │ │ bl 2716d60 │ │ bl 26ffb60 │ │ andeq sp, r8, r4, ror #2 │ │ ldc2 3, cr5, [r9, #1012]! @ 0x3f4 │ │ - ldc2 13, cr1, [r7, #304]! @ 0x130 │ │ + ldc2 13, cr1, [r7, #484]! @ 0x1e4 │ │ │ │ 026ae7b0 : │ │ mov r3, r2 │ │ mov r2, #0 │ │ b 2716600 │ │ │ │ 026ae7bc : │ │ @@ -1956256,18 +1956256,18 @@ │ │ ldr r0, [sp, #12] │ │ str r1, [r0, #196] @ 0xc4 │ │ mov r1, #15 │ │ ldr r0, [sp] │ │ str r1, [r0] │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - ldc2 6, cr1, [r8, #260]! @ 0x104 │ │ - ldc2 4, cr15, [r6, #276]! @ 0x114 │ │ - ldc2 9, cr9, [r7, #70]! @ 0x46 @ │ │ - ldc2 3, cr9, [r8, #84]! @ 0x54 │ │ + ldc2 6, cr1, [r8, #440]! @ 0x1b8 │ │ + ldc2 4, cr15, [r6, #456]! @ 0x1c8 │ │ + ldc2 9, cr9, [r7, #160]! @ 0xa0 @ │ │ + ldc2 3, cr9, [r8, #264]! @ 0x108 │ │ │ │ 026aed64 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #612 @ 0x264 │ │ mov r9, r0 │ │ ldr r0, [pc, #620] @ 26aefe8 │ │ @@ -1956857,21 +1956857,21 @@ │ │ bl 2716680 │ │ b 26af498 │ │ b 26af690 │ │ add r0, sp, #20 │ │ bl 2714160 │ │ bl 26ffb60 │ │ andeq ip, r8, r8, ror #9 │ │ - ldc2 11, cr6, [r8, #392]! @ 0x188 @ │ │ - ldc2 2, cr11, [r7, #160]! @ 0xa0 │ │ - ldc2 6, cr4, [r8, #264]! @ 0x108 │ │ + ldc2 11, cr6, [r8, #572]! @ 0x23c @ │ │ + ldc2 2, cr11, [r7, #340]! @ 0x154 │ │ + ldc2 6, cr4, [r8, #444]! @ 0x1bc │ │ ldc2 12, cr15, [r9, #812]! @ 0x32c │ │ - ldc2 0, cr1, [r7, #380]! @ 0x17c │ │ + ldc2 0, cr1, [r7, #560]! @ 0x230 │ │ ldc2 10, cr12, [r8, #836]! @ 0x344 @ │ │ - ldc2 1, cr9, [r7, #988]! @ 0x3dc │ │ + ldc2 2, cr9, [r7, #144]! @ 0x90 │ │ ldc2 13, cr15, [r9, #424]! @ 0x1a8 │ │ │ │ 026af6c0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #28 │ │ mov lr, r0 │ │ @@ -1957474,15 +1957474,15 @@ │ │ ldr r1, [r2, #4] │ │ mov r2, r0 │ │ cmp r1, #65536 @ 0x10000 │ │ bcc 26afef4 │ │ b 26afed8 │ │ bl 2707fc0 │ │ vcmla.f32 d1, d26, d7, #270 │ │ - ldc2 11, cr10, [r7, #120]! @ 0x78 @ │ │ + ldc2 11, cr10, [r7, #300]! @ 0x12c @ │ │ │ │ 026b0040 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ ldr r7, [r3] │ │ mov r8, r1 │ │ @@ -1958441,20 +1958441,20 @@ │ │ b 26b0f00 │ │ add r0, sp, #96 @ 0x60 │ │ bl 2714160 │ │ sub r0, fp, #96 @ 0x60 │ │ bl 2714160 │ │ bl 26ffb60 │ │ @ instruction: 0x0008acb4 │ │ - vcmla.f32 , , , #270 │ │ + vcmla.f32 , , q15, #270 │ │ ldc2 13, cr7, [r6, #536]! @ 0x218 │ │ ldc2 9, cr4, [r9, #424]! @ 0x1a8 @ │ │ ldc2 5, cr9, [r8, #216]! @ 0xd8 │ │ - ldc2 15, cr2, [r8, #40]! @ 0x28 │ │ - ldc2 4, cr11, [r6, #648]! @ 0x288 │ │ + ldc2 15, cr2, [r8, #220]! @ 0xdc │ │ + ldc2 4, cr11, [r6, #828]! @ 0x33c │ │ ldc2 3, cr3, [r6, #796]! @ 0x31c │ │ ldc2 11, cr12, [r9, #784]! @ 0x310 @ │ │ vcmla.f32 d10, d25, d19, #270 │ │ ldc2 2, cr0, [sl, #536]! @ 0x218 │ │ │ │ 026b0f38 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ @@ -1960454,15 +1960454,15 @@ │ │ cmp r0, #0 │ │ bgt 26b2b38 │ │ ldr r0, [r5, #36] @ 0x24 │ │ b 26b2b90 │ │ mov r0, r2 │ │ str r2, [r5, #36] @ 0x24 │ │ b 26b2d74 │ │ - ldc2 2, cr11, [r7, #936]! @ 0x3a8 │ │ + ldc2 3, cr11, [r7, #92]! @ 0x5c │ │ │ │ 026b2d98 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ mov r5, r1 │ │ mov r4, r0 │ │ @@ -1960579,15 +1960579,15 @@ │ │ cmp r2, #0 │ │ str r0, [r4, #24] │ │ beq 26b2dcc │ │ mov r0, r4 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ b 2716db0 │ │ - ldc2 4, cr13, [r7, #224]! @ 0xe0 │ │ + ldc2 4, cr13, [r7, #404]! @ 0x194 │ │ ldc2 15, cr8, [r8, #852]! @ 0x354 │ │ ldc2 14, cr12, [r8, #320]! @ 0x140 │ │ │ │ 026b2f8c : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #828 @ 0x33c │ │ @@ -1961841,25 +1961841,25 @@ │ │ ldc2 5, cr3, [sl, #960]! @ 0x3c0 │ │ ldc2 15, cr3, [sl, #464]! @ 0x1d0 │ │ ldc2 12, cr3, [sl, #800]! @ 0x320 │ │ ldc2 4, cr4, [sl, #824]! @ 0x338 │ │ ldc2 14, cr2, [sl, #1016]! @ 0x3f8 │ │ ldc2 4, cr3, [sl, #16]! │ │ ldc2 0, cr3, [sl, #832]! @ 0x340 │ │ - ldc2 9, cr8, [r7, #462]! @ 0x1ce @ │ │ + ldc2 10, cr8, [r7, #80]! @ 0x50 @ │ │ ldc2 7, cr2, [sl, #160]! @ 0xa0 │ │ ldc2 15, cr11, [r8, #600]! @ 0x258 │ │ ldc2 0, cr12, [r8, #56]! @ 0x38 │ │ - ldc2 3, cr4, [r7, #980]! @ 0x3d4 │ │ + ldc2 4, cr4, [r7, #136]! @ 0x88 │ │ ldc2 14, cr11, [r8, #952]! @ 0x3b8 │ │ - ldc2 4, cr14, [r6, #144]! @ 0x90 │ │ - ldc2 12, cr1, [r8, #804]! @ 0x324 │ │ + ldc2 4, cr14, [r6, #324]! @ 0x144 │ │ + ldc2 12, cr1, [r8, #984]! @ 0x3d8 │ │ ldc2 6, cr6, [r6, #536]! @ 0x218 │ │ ldc2 0, cr4, [sl, #720]! @ 0x2d0 │ │ - ldc2 14, cr15, [r7, #180]! @ 0xb4 │ │ + ldc2 14, cr15, [r7, #360]! @ 0x168 │ │ │ │ 026b435c : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ ldr r0, [r0, #8] │ │ ldrsh ip, [r0, #4] │ │ ldr r2, [r0, #8] │ │ @@ -1962446,15 +1962446,15 @@ │ │ bl 2714160 │ │ add r0, sp, #80 @ 0x50 │ │ bl 2714160 │ │ sub r0, fp, #88 @ 0x58 │ │ bl 2714160 │ │ bl 26ffb60 │ │ muleq r8, r0, ip │ │ - ldc2 10, cr7, [r7, #280]! @ 0x118 @ │ │ + ldc2 10, cr7, [r7, #460]! @ 0x1cc @ │ │ │ │ 026b4c80 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #220 @ 0xdc │ │ mov sl, r0 │ │ mov r0, #2 │ │ @@ -1962768,22 +1962768,22 @@ │ │ b 26b5164 │ │ add r0, sp, #88 @ 0x58 │ │ bl 2714160 │ │ sub r0, fp, #96 @ 0x60 │ │ bl 2714160 │ │ bl 26ffb60 │ │ andeq r6, r8, r0, lsl sl │ │ - ldc2 0, cr9, [r7, #164]! @ 0xa4 │ │ + ldc2 0, cr9, [r7, #344]! @ 0x158 │ │ ldc2 11, cr14, [r8, #428]! @ 0x1ac @ │ │ - ldc2 4, cr11, [r6, #204]! @ 0xcc │ │ + ldc2 4, cr11, [r6, #384]! @ 0x180 │ │ ldc2 0, cr5, [r8, #980]! @ 0x3d4 │ │ ldc2 3, cr1, [r6, #860]! @ 0x35c │ │ - ldc2 1, cr9, [r6, #360]! @ 0x168 │ │ - ldc2 11, cr14, [r7, #508]! @ 0x1fc @ │ │ - ldc2 3, cr13, [r6, #16]! │ │ + ldc2 1, cr9, [r6, #540]! @ 0x21c │ │ + ldc2 11, cr14, [r7, #688]! @ 0x2b0 @ │ │ + ldc2 3, cr13, [r6, #196]! @ 0xc4 │ │ │ │ 026b519c : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r1 │ │ ldr r1, [r0, #8] │ │ ldrsh r2, [r1, #4] │ │ @@ -1963452,17 +1963452,17 @@ │ │ ldr r0, [pc, #28] @ 26b5c0c │ │ mov r1, #3 │ │ ldr r2, [sl, #20] │ │ mov r8, r7 │ │ add r0, pc, r0 │ │ b 26b5bb4 │ │ ldc2 1, cr12, [r8, #700]! @ 0x2bc │ │ - ldc2 9, cr10, [r6, #388]! @ 0x184 @ │ │ - ldc2 4, cr2, [r8, #852]! @ 0x354 │ │ - ldc2 0, cr14, [r7, #72]! @ 0x48 │ │ + ldc2 9, cr10, [r6, #478]! @ 0x1de @ │ │ + ldc2 5, cr2, [r8, #8]! │ │ + ldc2 0, cr14, [r7, #252]! @ 0xfc │ │ │ │ 026b5c10 : │ │ sub r2, r0, #33 @ 0x21 │ │ mov r1, r0 │ │ mov r0, #0 │ │ cmp r2, #93 @ 0x5d │ │ bxhi lr │ │ @@ -1963817,15 +1963817,15 @@ │ │ b 26b618c │ │ b 26b618c │ │ add r0, sp, #72 @ 0x48 │ │ bl 27103d0 │ │ sub r0, fp, #48 @ 0x30 │ │ bl 2715bb0 │ │ bl 26ffb60 │ │ - ldc2 15, cr7, [r7, #184]! @ 0xb8 │ │ + ldc2 15, cr7, [r7, #364]! @ 0x16c │ │ │ │ 026b61a4 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #96 @ 0x60 │ │ mov r4, r0 │ │ ldr r0, [pc, #412] @ 26b6358 │ │ @@ -1964086,15 +1964086,15 @@ │ │ str r1, [r0, #24] │ │ bne 26b6494 │ │ b 26b6498 │ │ add r0, sp, #4 │ │ bl 2714160 │ │ bl 26ffb60 │ │ ldc2 3, cr7, [r9, #352]! @ 0x160 │ │ - ldc2 1, cr10, [r6, #16]! │ │ + ldc2 1, cr10, [r6, #196]! @ 0xc4 │ │ ldc2 9, cr5, [r8, #366]! @ 0x16e @ │ │ │ │ 026b65cc : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ ldr r1, [pc, #208] @ 26b66ac │ │ mov r4, r0 │ │ @@ -1964148,16 +1964148,16 @@ │ │ pop {r4, sl, fp, pc} │ │ movw r0, #4099 @ 0x1003 │ │ pop {r4, sl, fp, pc} │ │ movw r0, #4100 @ 0x1004 │ │ pop {r4, sl, fp, pc} │ │ ldc2 2, cr2, [r6, #376]! @ 0x178 │ │ ldc2 2, cr2, [r6, #304]! @ 0x130 │ │ - ldc2 13, cr1, [r8, #264]! @ 0x108 │ │ - ldc2 9, cr5, [r6, #212]! @ 0xd4 @ │ │ + ldc2 13, cr1, [r8, #444]! @ 0x1bc │ │ + ldc2 9, cr5, [r6, #302]! @ 0x12e @ │ │ ldc2 5, cr13, [r5, #596]! @ 0x254 │ │ ldc2 9, cr13, [r5, #400]! @ 0x190 @ │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ │ │ 026b66d0 : │ │ @@ -1980432,15 +1980432,15 @@ │ │ bl 2714160 │ │ add r0, sp, #328 @ 0x148 │ │ bl 2714600 │ │ sub r0, fp, #184 @ 0xb8 │ │ bl 2714600 │ │ bl 26ffb60 │ │ andeq r5, r7, r0, lsr sl │ │ - ldc2 7, cr10, [r5, #708]! @ 0x2c4 │ │ + ldc2 7, cr10, [r5, #888]! @ 0x378 │ │ b 2714590 │ │ b 2714570 │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #80 @ 0x50 │ │ mov r4, r0 │ │ mov r3, r2 │ │ @@ -1980668,18 +1980668,18 @@ │ │ add r0, sp, #4 │ │ bl 27103d0 │ │ add r0, sp, #60 @ 0x3c │ │ bl 27103d0 │ │ add r0, sp, #116 @ 0x74 │ │ bl 271d400 │ │ bl 26ffb60 │ │ - ldc2 13, cr11, [r6, #80]! @ 0x50 │ │ - ldc2 7, cr13, [r6, #280]! @ 0x118 │ │ - ldc2 0, cr2, [r6, #324]! @ 0x144 │ │ - ldc2 14, cr15, [r6, #1000]! @ 0x3e8 │ │ + ldc2 13, cr11, [r6, #260]! @ 0x104 │ │ + ldc2 7, cr13, [r6, #460]! @ 0x1cc │ │ + ldc2 0, cr2, [r6, #504]! @ 0x1f8 │ │ + ldc2 15, cr15, [r6, #156]! @ 0x9c │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #68 @ 0x44 │ │ mov sl, r0 │ │ ldr r0, [r3] │ │ mov r5, r1 │ │ str r2, [sp, #4] │ │ @@ -1980979,18 +1980979,18 @@ │ │ ldr r1, [r5, #280] @ 0x118 │ │ mov r0, r6 │ │ ldr r2, [r5, #332] @ 0x14c │ │ mov r3, r4 │ │ bl 27108e0 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ - ldc2 6, cr13, [r6, #832]! @ 0x340 │ │ - ldc2 6, cr13, [r6, #560]! @ 0x230 │ │ - ldc2 6, cr13, [r6, #320]! @ 0x140 │ │ - ldc2 6, cr13, [r6, #128]! @ 0x80 │ │ + ldc2 6, cr13, [r6, #1012]! @ 0x3f4 │ │ + ldc2 6, cr13, [r6, #740]! @ 0x2e4 │ │ + ldc2 6, cr13, [r6, #500]! @ 0x1f4 │ │ + ldc2 6, cr13, [r6, #308]! @ 0x134 │ │ @ instruction: 0xff9b6010 │ │ @ instruction: 0xff9b5fd8 │ │ │ │ 026c6940 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #564 @ 0x234 │ │ @@ -1982323,15 +1982323,15 @@ │ │ ldreq r6, [lr, #612]! @ 0x264 │ │ andeq r3, r7, r8, asr #19 │ │ andeq r3, r7, ip, asr #19 │ │ ldc2 8, cr13, [r7, #464]! @ 0x1d0 │ │ ldreq r6, [lr, #572]! @ 0x23c │ │ ldc2 7, cr13, [r7, #880]! @ 0x370 │ │ andeq r3, r7, r8, asr #22 │ │ - ldc2 9, cr8, [r5, #202]! @ 0xca @ │ │ + ldc2 9, cr8, [r5, #292]! @ 0x124 @ │ │ strdeq r3, [r7], -ip │ │ ldrdeq r3, [r7], -r4 │ │ │ │ 026c7dcc : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #216 @ 0xd8 │ │ @@ -1983017,21 +1983017,21 @@ │ │ mov r0, #9 │ │ pop {r4, sl, fp, pc} │ │ mov r0, #10 │ │ pop {r4, sl, fp, pc} │ │ ldc2 4, cr9, [r7, #872]! @ 0x368 │ │ vcmla.f32 d11, d4, d9, #270 │ │ ldc2 6, cr3, [r7, #636]! @ 0x27c │ │ - ldc2 6, cr9, [r6, #296]! @ 0x128 │ │ + ldc2 6, cr9, [r6, #476]! @ 0x1dc │ │ ldc2 7, cr11, [r4, #792]! @ 0x318 │ │ ldc2 2, cr11, [r7, #40]! @ 0x28 │ │ ldc2 1, cr11, [r7, #996]! @ 0x3e4 │ │ - ldc2 7, cr5, [r6, #200]! @ 0xc8 │ │ + ldc2 7, cr5, [r6, #380]! @ 0x17c │ │ ldc2 11, cr12, [r7, #956]! @ 0x3bc @ │ │ - ldc2 11, cr1, [r6, #260]! @ 0x104 @ │ │ + ldc2 11, cr1, [r6, #440]! @ 0x1b8 @ │ │ ldc2 11, cr2, [r8, #504]! @ 0x1f8 @ │ │ vcmla.f32 , q2, , #270 │ │ │ │ 026c888c : │ │ b 26c88a4 │ │ subs ip, r1, #24 │ │ movne ip, r1 │ │ @@ -1983370,15 +1983370,15 @@ │ │ ldr r0, [fp, #-36] @ 0xffffffdc │ │ str r0, [sp, #20] │ │ add r0, sp, #20 │ │ bl 26ffb60 │ │ add r0, sp, #24 │ │ bl 2714160 │ │ bl 26ffb60 │ │ - ldc2 6, cr7, [r6, #828]! @ 0x33c │ │ + ldc2 6, cr7, [r6, #1008]! @ 0x3f0 │ │ ldreq r5, [lr, #424]! @ 0x1a8 │ │ vcmla.f32 d12, d23, d4, #270 │ │ ldreq r5, [lr, #680]! @ 0x2a8 │ │ ldreq r5, [lr, #352]! @ 0x160 │ │ ldreq r5, [lr, #840]! @ 0x348 │ │ │ │ 026c8dec : │ │ @@ -1983996,21 +1983996,21 @@ │ │ add r0, sp, #36 @ 0x24 │ │ bl 26ffb60 │ │ ldr r0, [fp, #-76] @ 0xffffffb4 │ │ str r0, [sp, #44] @ 0x2c │ │ add r0, sp, #44 @ 0x2c │ │ bl 26ffb60 │ │ ldc2 2, cr9, [r4, #160]! @ 0xa0 │ │ - vcmla.f32 , , , #270 │ │ - ldc2 1, cr7, [r6, #324]! @ 0x144 │ │ + ldc2 8, cr7, [r5, #976]! @ 0x3d0 │ │ + ldc2 1, cr7, [r6, #504]! @ 0x1f8 │ │ ldc2 4, cr2, [r8, #184]! @ 0xb8 │ │ - ldc2 12, cr8, [r6, #1008]! @ 0x3f0 │ │ - ldc2 1, cr7, [r6, #692]! @ 0x2b4 │ │ + ldc2 13, cr8, [r6, #164]! @ 0xa4 │ │ + ldc2 1, cr7, [r6, #872]! @ 0x368 │ │ ldc2 4, cr2, [r8, #552]! @ 0x228 │ │ - ldc2 13, cr8, [r6, #352]! @ 0x160 │ │ + ldc2 13, cr8, [r6, #532]! @ 0x214 │ │ ldreq r4, [lr, #2772]! @ 0xad4 │ │ ldreq r4, [lr, #2480]! @ 0x9b0 │ │ │ │ 026c97a8 : │ │ ldr r0, [pc, #4] @ 26c97b4 │ │ add r0, pc, r0 │ │ bx lr │ │ @@ -1988901,15 +1988901,15 @@ │ │ add r0, sp, #24 │ │ bl 26ffb60 │ │ str r6, [sp, #16] │ │ add r0, sp, #16 │ │ sub r0, fp, #100 @ 0x64 │ │ bl 2714160 │ │ bl 26ffb60 │ │ - ldc2 5, cr2, [r5, #116]! @ 0x74 │ │ + ldc2 5, cr2, [r5, #296]! @ 0x128 │ │ │ │ 026ce24c : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r0, r1 │ │ mov r1, r2 │ │ bl 271b100 │ │ @@ -1989786,15 +1989786,15 @@ │ │ ldrb r2, [r1, r3] │ │ add r3, r3, #1 │ │ cmp r2, #0 │ │ bne 26ceed4 │ │ mov r1, #0 │ │ strb r1, [r0] │ │ b 26cee98 │ │ - ldc2 1, cr3, [r6, #492]! @ 0x1ec │ │ + ldc2 1, cr3, [r6, #672]! @ 0x2a0 │ │ │ │ 026ceef8 : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r2 │ │ mov r5, r0 │ │ add r0, r0, #356 @ 0x164 │ │ @@ -1996053,17 +1996053,17 @@ │ │ b 26d4e88 │ │ add r0, sp, #40 @ 0x28 │ │ bl 2718e80 │ │ b 26d4e94 │ │ sub r0, fp, #36 @ 0x24 │ │ bl 2718e80 │ │ bl 26ffb60 │ │ - ldc2 3, cr7, [r4, #792]! @ 0x318 │ │ - ldc2 3, cr7, [r4, #664]! @ 0x298 │ │ - ldc2 3, cr7, [r4, #264]! @ 0x108 │ │ + ldc2 3, cr7, [r4, #972]! @ 0x3cc │ │ + ldc2 3, cr7, [r4, #844]! @ 0x34c │ │ + ldc2 3, cr7, [r4, #444]! @ 0x1bc │ │ ldc2 11, cr1, [r8, #952]! @ 0x3b8 @ │ │ ldc2 9, cr6, [r7, #58]! @ 0x3a @ │ │ ldc2 7, cr1, [r8, #280]! @ 0x118 │ │ ldc2 7, cr0, [r7, #684]! @ 0x2ac │ │ ldc2 0, cr3, [r8, #320]! @ 0x140 │ │ ldc2 0, cr3, [r8, #176]! @ 0xb0 │ │ │ │ @@ -1997381,15 +1997381,15 @@ │ │ add r0, sp, #64 @ 0x40 │ │ bl 2718890 │ │ bl 26ffb60 │ │ add r0, sp, #64 @ 0x40 │ │ bl 271a4f0 │ │ bl 26ffb60 │ │ andeq r5, r6, r0, ror r8 │ │ - ldc2 5, cr10, [r4, #180]! @ 0xb4 │ │ + ldc2 5, cr10, [r4, #360]! @ 0x168 │ │ │ │ 026d6274 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #436 @ 0x1b4 │ │ ldr r9, [fp, #8] │ │ mov r7, r1 │ │ @@ -1997474,15 +1997474,15 @@ │ │ add r0, sp, #64 @ 0x40 │ │ bl 2718890 │ │ bl 26ffb60 │ │ add r0, sp, #64 @ 0x40 │ │ bl 271a4f0 │ │ bl 26ffb60 │ │ andeq r5, r6, r0, ror #13 │ │ - ldc2 3, cr10, [r4, #628]! @ 0x274 │ │ + ldc2 3, cr10, [r4, #808]! @ 0x328 │ │ │ │ 026d63e0 : │ │ mov r0, #0 │ │ str r0, [r3, #8] │ │ bx lr │ │ │ │ 026d63ec : │ │ @@ -1999325,15 +1999325,15 @@ │ │ ldr r4, [r4] │ │ bl 2713e90 │ │ mov r0, r6 │ │ cmp r4, #0 │ │ movwgt r0, #3 │ │ pop {r4, r5, r6, sl, fp, lr} │ │ bx lr │ │ - ldc2 6, cr12, [r4, #432]! @ 0x1b0 │ │ + ldc2 6, cr12, [r4, #612]! @ 0x264 │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #56 @ 0x38 │ │ mov r9, r1 │ │ mov r1, r0 │ │ ldr r0, [r2] │ │ mov r7, #0 │ │ @@ -1999404,15 +1999404,15 @@ │ │ mov r0, r7 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ b 26d80b8 │ │ mov r0, sp │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - ldc2 5, cr0, [r5, #144]! @ 0x90 │ │ + ldc2 5, cr0, [r5, #324]! @ 0x144 │ │ ldc2 13, cr9, [r6, #800]! @ 0x320 │ │ ldc2 13, cr3, [r6, #336]! @ 0x150 │ │ │ │ 026d80d0 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ @@ -1999449,15 +1999449,15 @@ │ │ str r1, [r7] │ │ ldr r0, [r0, #4] │ │ str r0, [r6] │ │ mov r0, r4 │ │ bl 2713e90 │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ - ldc2 15, cr5, [r5, #620]! @ 0x26c │ │ + ldc2 15, cr5, [r5, #800]! @ 0x320 │ │ │ │ 026d8174 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r0 │ │ ldr r0, [r1] │ │ cmp r0, #0 │ │ @@ -1999473,16 +1999473,16 @@ │ │ mov r3, r4 │ │ mov r6, r0 │ │ add r1, pc, r1 │ │ bl 2715380 │ │ mov r0, r6 │ │ pop {r4, r5, r6, sl, fp, lr} │ │ b 2713e90 │ │ - ldc2 3, cr0, [r5, #320]! @ 0x140 │ │ - ldc2 3, cr12, [r4, #284]! @ 0x11c │ │ + ldc2 3, cr0, [r5, #500]! @ 0x1f4 │ │ + ldc2 3, cr12, [r4, #464]! @ 0x1d0 │ │ │ │ 026d81d0 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ ldr r7, [r3] │ │ mov r4, r0 │ │ @@ -1999563,16 +1999563,16 @@ │ │ bgt 26d81f8 │ │ mov r0, r1 │ │ mov r1, r8 │ │ bl 2715720 │ │ ldr r0, [sp, #4] │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ - ldc2 11, cr9, [r5, #388]! @ 0x184 @ │ │ - ldc2 0, cr12, [r4, #628]! @ 0x274 │ │ + ldc2 11, cr9, [r5, #568]! @ 0x238 @ │ │ + ldc2 0, cr12, [r4, #808]! @ 0x328 │ │ │ │ 026d8330 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ ldr r7, [r3] │ │ mov r5, r0 │ │ @@ -1999685,16 +1999685,16 @@ │ │ mov r0, r9 │ │ mov r2, r8 │ │ mov r1, r4 │ │ bl 2715720 │ │ ldr r0, [sp, #4] │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ - ldc2 10, cr9, [r5, #4]! @ │ │ - ldc2 13, cr7, [r5, #716]! @ 0x2cc │ │ + ldc2 10, cr9, [r5, #184]! @ 0xb8 @ │ │ + ldc2 13, cr7, [r5, #896]! @ 0x380 │ │ @ instruction: 0xff9a46f4 │ │ @ instruction: 0xff9a46e8 │ │ │ │ 026d8518 : │ │ ldr r2, [r0, #632] @ 0x278 │ │ ldr r0, [r0, #636] @ 0x27c │ │ str r0, [r1] │ │ @@ -2000486,15 +2000486,15 @@ │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r1, [r0] │ │ ldr r1, [r1, #36] @ 0x24 │ │ blx r1 │ │ ldr r0, [r0, #32] │ │ pop {fp, pc} │ │ - ldc2 5, cr7, [r4, #564]! @ 0x234 │ │ + ldc2 5, cr7, [r4, #744]! @ 0x2e8 │ │ │ │ 026d9110 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #136 @ 0x88 │ │ ldr r4, [fp, #8] │ │ cmp r4, #0 │ │ @@ -2000895,15 +2000895,15 @@ │ │ add r0, sp, #4 │ │ bl 27128e0 │ │ add r0, sp, #12 │ │ bl 2710d40 │ │ bl 26ffb60 │ │ ldc2 4, cr3, [r7, #152]! @ 0x98 │ │ andeq sp, r5, r8, asr r6 │ │ - ldc2 13, cr6, [r4, #680]! @ 0x2a8 │ │ + ldc2 13, cr6, [r4, #860]! @ 0x35c │ │ │ │ 026d972c : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ ldr r4, [r0] │ │ mov r8, r3 │ │ cmp r4, #0 │ │ @@ -2000986,15 +2000986,15 @@ │ │ b 26d986c │ │ mov r0, r5 │ │ bl 271d840 │ │ mov r0, r4 │ │ bl 271d850 │ │ bl 26ffb60 │ │ ldc2 2, cr3, [r7, #1016]! @ 0x3f8 │ │ - ldc2 13, cr6, [r4, #412]! @ 0x19c │ │ + ldc2 13, cr6, [r4, #592]! @ 0x250 │ │ andeq sp, r5, r0, lsr r5 │ │ │ │ 026d988c : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #16 │ │ ldr r5, [fp, #8] │ │ @@ -2001664,30 +2001664,30 @@ │ │ bl 27103d0 │ │ sub r0, fp, #108 @ 0x6c │ │ bl 27103d0 │ │ mov r0, r9 │ │ bl 271d840 │ │ bl 26ffb60 │ │ ldc2 9, cr8, [r6, #372]! @ 0x174 @ │ │ - ldc2 10, cr8, [r4, #112]! @ 0x70 @ │ │ + ldc2 10, cr8, [r4, #292]! @ 0x124 @ │ │ ldc2 4, cr0, [r6, #328]! @ 0x148 │ │ ldc2 4, cr0, [r6, #756]! @ 0x2f4 │ │ - vcmla.f32 q1, , , #270 │ │ + ldc2 8, cr2, [r5, #992]! @ 0x3e0 │ │ ldc2 4, cr0, [r6, #132]! @ 0x84 │ │ - ldc2 7, cr6, [r4, #804]! @ 0x324 │ │ + ldc2 7, cr6, [r4, #984]! @ 0x3d8 │ │ andeq r1, r6, r4, lsl #15 │ │ ldc2 14, cr14, [r3, #168]! @ 0xa8 │ │ - ldc2 9, cr6, [r5, #336]! @ 0x150 @ │ │ - ldc2 1, cr10, [r5, #736]! @ 0x2e0 │ │ + ldc2 9, cr6, [r5, #426]! @ 0x1aa @ │ │ + ldc2 1, cr10, [r5, #916]! @ 0x394 │ │ ldc2 10, cr11, [r6, #268]! @ 0x10c @ │ │ - ldc2 12, cr9, [r5, #720]! @ 0x2d0 │ │ - ldc2 13, cr13, [r5, #212]! @ 0xd4 │ │ - ldc2 3, cr14, [r5, #728]! @ 0x2d8 │ │ + ldc2 12, cr9, [r5, #900]! @ 0x384 │ │ + ldc2 13, cr13, [r5, #392]! @ 0x188 │ │ + ldc2 3, cr14, [r5, #908]! @ 0x38c │ │ ldc2 5, cr11, [r6, #236]! @ 0xec │ │ - ldc2 13, cr3, [r4, #872]! @ 0x368 │ │ + ldc2 14, cr3, [r4, #28]! │ │ ldc2 13, cr1, [r6, #512]! @ 0x200 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #260 @ 0x104 │ │ ldr r5, [fp, #20] │ │ mov r4, r0 │ │ mvn r9, #0 │ │ @@ -2001898,16 +2001898,16 @@ │ │ ldr r0, [sp, #32] │ │ bl 27103d0 │ │ ldr r0, [sp, #40] @ 0x28 │ │ bl 27103d0 │ │ ldr r0, [sp, #28] │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - ldc2 12, cr11, [r5, #264]! @ 0x108 │ │ - ldc2 12, cr11, [r5, #104]! @ 0x68 │ │ + ldc2 12, cr11, [r5, #444]! @ 0x1bc │ │ + ldc2 12, cr11, [r5, #284]! @ 0x11c │ │ ldc2 9, cr1, [r6, #40]! @ 0x28 @ │ │ vcmla.f32 , q11, q10, #270 │ │ push {fp, lr} │ │ mov fp, sp │ │ bl 27128e0 │ │ pop {fp, lr} │ │ b 2713d70 │ │ @@ -2002285,20 +2002285,20 @@ │ │ add r0, sp, #256 @ 0x100 │ │ bl 2714160 │ │ sub r0, fp, #224 @ 0xe0 │ │ bl 2714160 │ │ sub r0, fp, #160 @ 0xa0 │ │ bl 2714160 │ │ bl 26ffb60 │ │ - ldc2 13, cr5, [r4, #424]! @ 0x1a8 │ │ + ldc2 13, cr5, [r4, #604]! @ 0x25c │ │ andeq r0, r6, r4, lsr pc │ │ ldc2 5, cr9, [r6, #332]! @ 0x14c │ │ - ldc2 8, cr1, [r4, #844]! @ 0x34c │ │ + ldc2 9, cr1, [r4] @ │ │ ldc2 4, cr13, [r6, #688]! @ 0x2b0 │ │ - ldc2 3, cr9, [r5, #932]! @ 0x3a4 │ │ + ldc2 4, cr9, [r5, #88]! @ 0x58 │ │ ldc2 2, cr9, [r6, #764]! @ 0x2fc │ │ push {fp, lr} │ │ mov fp, sp │ │ bl 27128e0 │ │ pop {fp, lr} │ │ b 2713d70 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ @@ -2002619,15 +2002619,15 @@ │ │ b 26db1ec │ │ b 26db1ec │ │ add r0, sp, #56 @ 0x38 │ │ bl 2719920 │ │ add r0, sp, #120 @ 0x78 │ │ bl 27103d0 │ │ bl 26ffb60 │ │ - vcmla.f32 , q2, , #270 │ │ + ldc2 8, cr5, [r4, #448]! @ 0x1c0 │ │ ldc2 4, cr11, [r3, #172]! @ 0xac │ │ ldc2 13, cr6, [r6, #624]! @ 0x270 │ │ ldc2 15, cr0, [r6, #452]! @ 0x1c4 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #12 │ │ mov r5, r2 │ │ @@ -2005045,33 +2005045,33 @@ │ │ vmul.f64 d16, d17, d16 │ │ b 26dd390 │ │ nop {0} │ │ andeq r0, r0, r0 │ │ addsmi r0, fp, r0 │ │ andeq r0, r0, r0 │ │ rsbmi lr, ip, r0 │ │ - ldc2 10, cr6, [r5, #660]! @ 0x294 @ │ │ - ldc2 1, cr5, [r4, #844]! @ 0x34c │ │ + ldc2 10, cr6, [r5, #840]! @ 0x348 @ │ │ + ldc2 2, cr5, [r4] │ │ ldc2 3, cr13, [r3, #696]! @ 0x2b8 │ │ - ldc2 15, cr0, [r4, #204]! @ 0xcc │ │ - ldc2 0, cr3, [r5, #576]! @ 0x240 │ │ + ldc2 15, cr0, [r4, #384]! @ 0x180 │ │ + ldc2 0, cr3, [r5, #756]! @ 0x2f4 │ │ ldc2 1, cr12, [r6, #84]! @ 0x54 │ │ - ldc2 9, cr6, [r5, #194]! @ 0xc2 @ │ │ + ldc2 9, cr6, [r5, #284]! @ 0x11c @ │ │ ldc2 8, cr10, [r6, #72]! @ 0x48 │ │ - ldc2 0, cr13, [r4, #444]! @ 0x1bc │ │ - ldc2 13, cr0, [r4, #356]! @ 0x164 │ │ - vcmla.f32 q4, , , #270 │ │ + ldc2 0, cr13, [r4, #624]! @ 0x270 │ │ + ldc2 13, cr0, [r4, #536]! @ 0x218 │ │ + vcmla.f32 q4, , q15, #270 │ │ ldc2 0, cr9, [r3, #140]! @ 0x8c │ │ ldc2 13, cr6, [r3, #680]! @ 0x2a8 │ │ ldc2 11, cr3, [r7, #940]! @ 0x3ac @ │ │ - ldc2 15, cr12, [r4, #160]! @ 0xa0 │ │ - ldc2 15, cr2, [r4, #648]! @ 0x288 │ │ - ldc2 14, cr6, [r4, #972]! @ 0x3cc │ │ + ldc2 15, cr12, [r4, #340]! @ 0x154 │ │ + ldc2 15, cr2, [r4, #828]! @ 0x33c │ │ + ldc2 15, cr6, [r4, #128]! @ 0x80 │ │ ldc2 15, cr12, [r3, #848]! @ 0x350 │ │ - ldc2 13, cr8, [r4, #768]! @ 0x300 │ │ + ldc2 13, cr8, [r4, #948]! @ 0x3b4 │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #48 @ 0x30 │ │ vmov.i32 q8, #0 @ 0x00000000 │ │ mov r5, r1 │ │ mov r1, r0 │ │ add r0, sp, #8 │ │ @@ -2005091,15 +2005091,15 @@ │ │ vmov d0, r0, r1 │ │ ldr r0, [sp, #4] │ │ cmp r0, r5 │ │ movne r0, #3 │ │ strne r0, [r4] │ │ sub sp, fp, #8 │ │ pop {r4, r5, fp, pc} │ │ - ldc2 14, cr2, [r4, #948]! @ 0x3b4 │ │ + ldc2 15, cr2, [r4, #104]! @ 0x68 │ │ │ │ 026dd7cc : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #204 @ 0xcc │ │ mov r5, #0 │ │ str r1, [sp, #32] │ │ @@ -2006881,17 +2006881,17 @@ │ │ mov r0, #5 │ │ str r0, [r1] │ │ sub sp, fp, #96 @ 0x60 │ │ vpop {d8-d15} │ │ add sp, sp, #4 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ andeq ip, r5, ip, asr #17 │ │ - ldc2 4, cr1, [r4, #500]! @ 0x1f4 │ │ - ldc2 4, cr1, [r4, #116]! @ 0x74 │ │ - ldc2 3, cr1, [r4, #708]! @ 0x2c4 │ │ + ldc2 4, cr1, [r4, #680]! @ 0x2a8 │ │ + ldc2 4, cr1, [r4, #296]! @ 0x128 │ │ + ldc2 3, cr1, [r4, #888]! @ 0x378 │ │ │ │ 026df39c : │ │ vmov d16, r2, r3 │ │ eor r0, r3, #-2147483648 @ 0x80000000 │ │ vcmp.f64 d16, #0.0 │ │ vmrs APSR_nzcv, fpscr │ │ vmov d17, r2, r0 │ │ @@ -2007091,17 +2007091,17 @@ │ │ b 26df650 │ │ vmov.f64 d8, d16 │ │ b 26df650 │ │ vmov.f64 d17, #112 @ 0x3f800000 1.0 │ │ b 26df64c │ │ strbtvs r6, [r6], -r6, ror #12 │ │ submi lr, fp, r6, ror #12 │ │ - ldc2 0, cr5, [r4, #72]! @ 0x48 │ │ + ldc2 0, cr5, [r4, #252]! @ 0xfc │ │ @ instruction: 0xff99d750 │ │ - ldc2 15, cr4, [r4, #376]! @ 0x178 │ │ + ldc2 15, cr4, [r4, #556]! @ 0x22c │ │ @ instruction: 0xff99d678 │ │ │ │ 026df6d0 : │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ vpush {d8} │ │ sub sp, sp, #16 │ │ @@ -2007235,17 +2007235,17 @@ │ │ vmov s0, r3 │ │ vcvt.f64.s32 d16, s0 │ │ b 26df84c │ │ vmov.f64 d16, #49 @ 0x41880000 17.0 │ │ b 26df84c │ │ strbtvs r6, [r6], -r6, ror #12 │ │ submi lr, fp, r6, ror #12 │ │ - ldc2 13, cr4, [r4, #696]! @ 0x2b8 │ │ + ldc2 13, cr4, [r4, #876]! @ 0x36c │ │ @ instruction: 0xff99d4ec │ │ - ldc2 13, cr4, [r4, #24]! │ │ + ldc2 13, cr4, [r4, #204]! @ 0xcc │ │ @ instruction: 0xff99d3d0 │ │ │ │ 026df908 : │ │ add r2, r1, #344 @ 0x158 │ │ ldrb r1, [r1, #376] @ 0x178 │ │ strb r1, [r0, #16] │ │ vldmia r2, {d16-d19} │ │ @@ -2007316,15 +2007316,15 @@ │ │ mov r0, r5 │ │ mov r1, r4 │ │ strd r8, [sp] │ │ bl 271d9f0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ andeq fp, r5, r8, ror ip │ │ - ldc2 12, cr0, [r4, #628]! @ 0x274 │ │ + ldc2 12, cr0, [r4, #808]! @ 0x328 │ │ │ │ 026dfa38 : │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ mov r4, r0 │ │ mov r7, r1 │ │ mov r6, r2 │ │ @@ -2014535,16 +2014535,16 @@ │ │ bl 2713e90 │ │ mov r0, r4 │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, r9, fp, pc} │ │ mov r0, r4 │ │ bl 2713d70 │ │ bl 26ffb60 │ │ - ldc2 5, cr15, [r4, #380]! @ 0x17c │ │ - ldc2 11, cr15, [r3, #516]! @ 0x204 @ │ │ + ldc2 5, cr15, [r4, #560]! @ 0x230 │ │ + ldc2 11, cr15, [r3, #696]! @ 0x2b8 @ │ │ │ │ 026e66d8 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #12 │ │ mov r5, r1 │ │ ldr r1, [r1] │ │ @@ -2014618,16 +2014618,16 @@ │ │ blx r1 │ │ mov r0, #0 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ mov r0, r7 │ │ bl 2713d70 │ │ bl 26ffb60 │ │ - ldc2 4, cr15, [r4, #268]! @ 0x10c │ │ - ldc2 10, cr15, [r3, #436]! @ 0x1b4 @ │ │ + ldc2 4, cr15, [r4, #448]! @ 0x1c0 │ │ + ldc2 10, cr15, [r3, #616]! @ 0x268 @ │ │ │ │ 026e681c : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #8 │ │ mov r5, r1 │ │ mov r1, r0 │ │ @@ -2023582,16 +2023582,16 @@ │ │ b 26ef2a0 │ │ b 26ef2a0 │ │ add r0, sp, #52 @ 0x34 │ │ bl 27141e0 │ │ sub r0, fp, #96 @ 0x60 │ │ bl 2714160 │ │ bl 26ffb60 │ │ - ldc2 0, cr0, [r3, #676]! @ 0x2a4 │ │ - ldc2 1, cr4, [r4, #176]! @ 0xb0 │ │ + ldc2 0, cr0, [r3, #856]! @ 0x358 │ │ + ldc2 1, cr4, [r4, #356]! @ 0x164 │ │ @ instruction: 0xff98de64 │ │ @ instruction: 0xff98de73 │ │ @ instruction: 0xff98de48 │ │ │ │ 026ef2c0 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -2025687,20 +2025687,20 @@ │ │ add r5, sp, #376 @ 0x178 │ │ movs r4, r0 │ │ add r5, sp, #8 │ │ movs r4, r0 │ │ strh r1, [r5, #44] @ 0x2c │ │ ldc2 9, cr7, [r5, #120]! @ 0x78 @ │ │ ldc2 2, cr13, [r2, #864]! @ 0x360 │ │ - ldc2 4, cr1, [r4, #764]! @ 0x2fc │ │ + ldc2 4, cr1, [r4, #944]! @ 0x3b0 │ │ ldc2 5, cr8, [r3, #532]! @ 0x214 │ │ ldc2 12, cr6, [r5, #832]! @ 0x340 │ │ - ldc2 5, cr9, [r5, #484]! @ 0x1e4 │ │ + ldc2 5, cr9, [r5, #664]! @ 0x298 │ │ ldc2 5, cr4, [r3, #744]! @ 0x2e8 │ │ - ldc2 2, cr13, [r5, #416]! @ 0x1a0 │ │ + ldc2 2, cr13, [r5, #596]! @ 0x254 │ │ ldc2 1, cr6, [r2, #664]! @ 0x298 │ │ movs r4, r0 │ │ │ │ 026f117c > >)>)@@Base>: │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ @@ -2026369,37 +2026369,37 @@ │ │ add r6, pc, #808 @ (adr r6, 26f1ae0 > >)>)@@Base+0x6d0>) │ │ movs r4, r0 │ │ lsrs r6, r7, #2 │ │ ldc2 7, cr6, [r5, #180]! @ 0xb4 │ │ ldc2 13, cr12, [r5, #64]! @ 0x40 │ │ ldc2 0, cr4, [r4, #644]! @ 0x284 │ │ ldc2 3, cr7, [r5, #236]! @ 0xec │ │ - ldc2 15, cr2, [r2, #484]! @ 0x1e4 │ │ + ldc2 15, cr2, [r2, #664]! @ 0x298 │ │ ldc2 2, cr4, [r3, #148]! @ 0x94 │ │ ldc2 4, cr11, [r5, #128]! @ 0x80 │ │ ldc2 12, cr13, [r4, #584]! @ 0x248 │ │ ldc2 5, cr10, [r5, #648]! @ 0x288 │ │ movs r4, r0 │ │ add r5, pc, #640 @ (adr r5, 26f1a64 > >)>)@@Base+0x654>) │ │ movs r4, r0 │ │ strb r1, [r0, #9] │ │ ldc2 15, cr3, [r2, #724]! @ 0x2d4 │ │ ldc2 5, cr10, [r5, #216]! @ 0xd8 │ │ movs r4, r0 │ │ - lsrs r0, r3, #22 │ │ + lsrs r5, r0, #23 │ │ ldc2 3, cr11, [r3, #208]! @ 0xd0 │ │ - ldc2 6, cr4, [r4, #960]! @ 0x3c0 │ │ - ldc2 13, cr0, [r4, #280]! @ 0x118 │ │ + ldc2 7, cr4, [r4, #116]! @ 0x74 │ │ + ldc2 13, cr0, [r4, #460]! @ 0x1cc │ │ ldc2 15, cr9, [r3, #700]! @ 0x2bc │ │ ldc2 1, cr7, [r5, #332]! @ 0x14c │ │ ldc2 14, cr3, [r2, #612]! @ 0x264 │ │ ldc2 4, cr10, [r5, #248]! @ 0xf8 │ │ movs r4, r0 │ │ strb r1, [r5, #4] │ │ - ldc2 14, cr14, [r2, #112]! @ 0x70 │ │ + ldc2 14, cr14, [r2, #292]! @ 0x124 │ │ ldc2 6, cr9, [r2, #16]! │ │ mov r0, sl │ │ ldr r1, [pc, #952] @ (26f1bd8 > >)>)@@Base+0x7c8>) │ │ ldr r2, [r2, #24] │ │ add r1, pc │ │ blx r2 │ │ mov r6, r0 │ │ @@ -2026791,41 +2026791,41 @@ │ │ ldrne r0, [sp, #64] @ 0x40 │ │ blxne 26ffb40 │ │ b.n 26f1922 > >)>)@@Base+0x512> │ │ nop │ │ ldr r3, [r3, #120] @ 0x78 │ │ ldc2 4, cr0, [r2, #848]! @ 0x350 │ │ ldc2 10, cr12, [r5, #232]! @ 0xe8 @ │ │ - ldc2 11, cr14, [r4, #480]! @ 0x1e0 @ │ │ + ldc2 11, cr14, [r4, #660]! @ 0x294 @ │ │ ldc2 4, cr6, [r3, #200]! @ 0xc8 │ │ ldc2 14, cr9, [r5, #544]! @ 0x220 │ │ ldc2 10, cr13, [r5, #172]! @ 0xac @ │ │ - ldc2 10, cr14, [r5, #996]! @ 0x3e4 @ │ │ + ldc2 11, cr14, [r5, #152]! @ 0x98 @ │ │ ldc2 0, cr7, [r3, #12]! │ │ ldc2 5, cr2, [r2, #816]! @ 0x330 │ │ ldc2 1, cr10, [r2, #744]! @ 0x2e8 │ │ movs r4, r0 │ │ ldrb r0, [r3, r0] │ │ movs r4, r0 │ │ add r1, pc, #56 @ (adr r1, 26f1c3c ) │ │ movs r4, r0 │ │ add r1, pc, #64 @ (adr r1, 26f1c48 ) │ │ movs r4, r0 │ │ ldrh r2, [r1, r6] │ │ movs r4, r0 │ │ ldr r7, [r7, #88] @ 0x58 │ │ - ldc2 10, cr14, [r2, #600]! @ 0x258 @ │ │ + ldc2 10, cr14, [r2, #780]! @ 0x30c @ │ │ ldc2 13, cr6, [r2, #308]! @ 0x134 │ │ ldc2 10, cr3, [r2, #772]! @ 0x304 @ │ │ ldc2 0, cr10, [r5, #264]! @ 0x108 │ │ movs r4, r0 │ │ ldr r5, [r5, #80] @ 0x50 │ │ - ldc2 10, cr14, [r2, #128]! @ 0x80 @ │ │ + ldc2 10, cr14, [r2, #308]! @ 0x134 @ │ │ ldc2 0, cr11, [r2, #744]! @ 0x2e8 │ │ - ldc2 1, cr7, [r4, #340]! @ 0x154 │ │ + ldc2 1, cr7, [r4, #520]! @ 0x208 │ │ ldc2 4, cr0, [r4, #304]! @ 0x130 │ │ ldc2 7, cr9, [r5, #444]! @ 0x1bc │ │ ldc2 8, cr8, [r2, #588]! @ 0x24c │ │ Address 0x26f1c3a is out of bounds. │ │ │ │ │ │ 026f1c3c : │ │ @@ -2027561,15 +2027561,15 @@ │ │ movs r4, r0 │ │ ldr r1, [sp, #352] @ 0x160 │ │ movs r4, r0 │ │ lsrs r7, r1, #29 │ │ movs r0, r0 │ │ bpl.n 26f2278 │ │ movs r2, r0 │ │ - subs r3, #27 │ │ + subs r3, #72 @ 0x48 │ │ ldc2 15, cr0, [r4, #164]! @ 0xa4 │ │ movs r0, r0 │ │ bpl.n 26f2238 │ │ movs r2, r0 │ │ │ │ 026f2334 > >)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -2029152,21 +2029152,21 @@ │ │ nop │ │ str r5, [r1, #60] @ 0x3c │ │ ldc2 3, cr3, [r5, #768]! @ 0x300 │ │ ldc2 4, cr2, [r2, #676]! @ 0x2a4 │ │ ldc2 13, cr14, [r5, #120]! @ 0x78 │ │ ldc2 3, cr3, [r4, #616]! @ 0x268 │ │ ldc2 4, cr2, [r2, #524]! @ 0x20c │ │ - ldc2 5, cr9, [r5, #752]! @ 0x2f0 │ │ + ldc2 5, cr9, [r5, #932]! @ 0x3a4 │ │ ldc2 3, cr3, [r3, #464]! @ 0x1d0 │ │ ldc2 4, cr2, [r2, #372]! @ 0x174 │ │ ldc2 4, cr3, [r5, #76]! @ 0x4c │ │ - ldc2 3, cr3, [r2, #40]! @ 0x28 │ │ + ldc2 3, cr3, [r2, #220]! @ 0xdc │ │ ldc2 4, cr7, [r3, #900]! @ 0x384 │ │ - ldc2 11, cr0, [r2, #188]! @ 0xbc @ │ │ + ldc2 11, cr0, [r2, #368]! @ 0x170 @ │ │ ldc2 5, cr11, [r4, #832]! @ 0x340 │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [r0, #0] │ │ movs r1, #0 │ │ cmp r0, #0 │ │ str r1, [r4, #0] │ │ @@ -2029699,17 +2029699,17 @@ │ │ lsls r0, r5, #1 │ │ ldr r4, [sp, #32] │ │ strb.w r0, [sp, #56] @ 0x38 │ │ b.n 26f3808 │ │ nop │ │ tst r6, r3 │ │ movs r4, r0 │ │ - add r6, sp, #88 @ 0x58 │ │ + add r6, sp, #268 @ 0x10c │ │ ldc2 7, cr11, [r2, #324]! @ 0x144 │ │ - ldc2 12, cr8, [r4, #776]! @ 0x308 │ │ + ldc2 12, cr8, [r4, #956]! @ 0x3bc │ │ ldc2 5, cr14, [r2, #584]! @ 0x248 │ │ ldc2 0, cr2, [r5, #452]! @ 0x1c4 │ │ ldc2 0, cr8, [r5, #256]! @ 0x100 │ │ ldc2 4, cr11, [r5, #708]! @ 0x2c4 │ │ ldc2 1, cr15, [r4, #20]! │ │ movs r1, r5 │ │ bic.w r8, r0, #15 │ │ @@ -2029962,15 +2029962,15 @@ │ │ add r0, sp, #56 @ 0x38 │ │ blx 271e0a0 │ │ add r0, sp, #88 @ 0x58 │ │ blx 271e0a0 │ │ ldr r0, [sp, #8] │ │ blx 271e090 │ │ blx 2707fc0 │ │ - ldmia r3!, {r0, r2, r5, r7} │ │ + ldmia r3!, {r1, r4, r6, r7} │ │ ldc2 3, cr11, [r3, #300]! @ 0x12c │ │ ldc2 5, cr11, [r4, #960]! @ 0x3c0 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ ldrb r4, [r0, #0] │ │ mov r6, r0 │ │ @@ -2031577,15 +2031577,15 @@ │ │ ldr r1, [pc, #12] @ (26f4998 ) │ │ add r1, pc │ │ blx 271e020 │ │ cmp r5, #76 @ 0x4c │ │ movs r4, r0 │ │ lsls r5, r1, #2 │ │ movs r0, r0 │ │ - ldr r0, [sp, #760] @ 0x2f8 │ │ + ldr r0, [sp, #940] @ 0x3ac │ │ Address 0x26f499a is out of bounds. │ │ │ │ │ │ 026f499c : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ @@ -2032316,39 +2032316,39 @@ │ │ ldr r2, [r2, #108] @ 0x6c │ │ movs r4, r0 │ │ beq.n 26f4fa0 │ │ ldc2 14, cr2, [r4, #1020]! @ 0x3fc │ │ ldc2 4, cr9, [r5, #904]! @ 0x388 │ │ ldc2 8, cr0, [r4, #452]! @ 0x1c4 │ │ ldc2 11, cr3, [r5, #44]! @ 0x2c @ │ │ - ldc2 7, cr15, [r2, #292]! @ 0x124 │ │ + ldc2 7, cr15, [r2, #472]! @ 0x1d8 │ │ ldc2 9, cr0, [r2, #490]! @ 0x1ea @ │ │ ldc2 11, cr7, [r5, #952]! @ 0x3b8 @ │ │ ldc2 4, cr10, [r4, #384]! @ 0x180 │ │ ldc2 13, cr6, [r5, #448]! @ 0x1c0 │ │ movs r4, r0 │ │ ldr r6, [r5, #84] @ 0x54 │ │ movs r4, r0 │ │ - lsrs r7, r3, #29 │ │ + lsrs r4, r1, #30 │ │ ldc2 7, cr0, [r4, #524]! @ 0x20c │ │ ldc2 13, cr6, [r5, #240]! @ 0xf0 │ │ movs r4, r0 │ │ - bpl.n 26f5180 │ │ + bpl.n 26f4fda │ │ ldc2 11, cr7, [r2] @ │ │ - ldc2 14, cr0, [r4, #752]! @ 0x2f0 │ │ - ldc2 5, cr13, [r4, #72]! @ 0x48 │ │ + ldc2 14, cr0, [r4, #932]! @ 0x3a4 │ │ + ldc2 5, cr13, [r4, #252]! @ 0xfc │ │ ldc2 7, cr6, [r2, #492]! @ 0x1ec │ │ - ldc2 14, cr0, [r5, #444]! @ 0x1bc │ │ + ldc2 14, cr0, [r5, #624]! @ 0x270 │ │ ldc2 6, cr0, [r4, #404]! @ 0x194 │ │ ldc2 12, cr6, [r5, #256]! @ 0x100 │ │ movs r4, r0 │ │ - lsrs r3, r0, #25 │ │ - ldc2 5, cr11, [r4, #920]! @ 0x398 │ │ + lsrs r0, r6, #25 │ │ + ldc2 6, cr11, [r4, #76]! @ 0x4c │ │ ldc2 2, cr9, [r2, #464]! @ 0x1d0 │ │ - ldc2 3, cr11, [r4, #712]! @ 0x2c8 │ │ + ldc2 3, cr11, [r4, #892]! @ 0x37c │ │ ldc2 12, cr2, [r3, #432]! @ 0x1b0 │ │ ldc2 6, cr6, [r5, #776]! @ 0x308 │ │ ldc2 2, cr10, [r5, #404]! @ 0x194 │ │ ldc2 5, cr9, [r5, #24]! │ │ mov r0, r9 │ │ ldr r2, [pc, #792] @ (26f540c ) │ │ ldr r3, [pc, #796] @ (26f5410 ) │ │ @@ -2032670,40 +2032670,40 @@ │ │ ldrb.w r0, [sp, #64] @ 0x40 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #72] @ 0x48 │ │ blxne 26ffb40 │ │ b.n 26f5158 │ │ nop │ │ - lsrs r5, r6, #18 │ │ + lsrs r2, r4, #19 │ │ ldc2 12, cr12, [r4, #632]! @ 0x278 │ │ - ldc2 2, cr11, [r4, #772]! @ 0x304 │ │ + ldc2 2, cr11, [r4, #952]! @ 0x3b8 │ │ ldc2 7, cr3, [r3, #812]! @ 0x32c │ │ ldc2 13, cr14, [r2, #568]! @ 0x238 │ │ ldc2 9, cr6, [r1, #244]! @ 0xf4 @ │ │ movs r4, r0 │ │ movs r3, #218 @ 0xda │ │ movs r4, r0 │ │ ldr r0, [r2, #12] │ │ movs r4, r0 │ │ ldr r2, [r2, #12] │ │ movs r4, r0 │ │ movs r3, #76 @ 0x4c │ │ movs r4, r0 │ │ - lsrs r5, r2, #11 │ │ - ldc2 2, cr11, [r4, #368]! @ 0x170 │ │ - ldc2 10, cr0, [r2, #396]! @ 0x18c @ │ │ + lsrs r2, r0, #12 │ │ + ldc2 2, cr11, [r4, #548]! @ 0x224 │ │ + ldc2 10, cr0, [r2, #576]! @ 0x240 @ │ │ ldc2 2, cr0, [r4, #540]! @ 0x21c │ │ vcmla.f32 q3, , q0, #270 │ │ movs r4, r0 │ │ - lsrs r3, r0, #9 │ │ - ldc2 1, cr11, [r4, #920]! @ 0x398 │ │ + lsrs r0, r6, #9 │ │ + ldc2 2, cr11, [r4, #76]! @ 0x4c │ │ vcmla.f32 d7, d18, d2, #270 │ │ ldc2 4, cr0, [r4, #840]! @ 0x348 │ │ - ldc2 13, cr12, [r5, #832]! @ 0x340 │ │ + ldc2 13, cr12, [r5, #1012]! @ 0x3f4 │ │ ldc2 9, cr9, [r3, #246]! @ 0xf6 @ │ │ ldc2 0, cr5, [r4, #364]! @ 0x16c │ │ ldc2 15, cr5, [r4, #140]! @ 0x8c │ │ Address 0x26f545e is out of bounds. │ │ │ │ │ │ 026f5460 : │ │ @@ -2034145,15 +2034145,15 @@ │ │ ldrh r2, [r5, r5] │ │ movs r4, r0 │ │ ldrh r0, [r3, r5] │ │ movs r4, r0 │ │ beq.n 26f6152 │ │ vabdl.u , d15, d30 │ │ movs r2, r0 │ │ - stmia r3!, {r1, r2, r5, r6, r7} │ │ + stmia r4!, {r0, r1, r4} │ │ ldc2 9, cr7, [r2, #260]! @ 0x104 @ │ │ movs r6, r0 │ │ ldrb r0, [r5, #5] │ │ movs r6, r0 │ │ beq.n 26f6112 │ │ vabdl.u , d15, d4 │ │ movs r2, r0 │ │ @@ -2034934,15 +2034934,15 @@ │ │ strh r0, [r3, r6] │ │ movs r4, r0 │ │ strh r4, [r1, r6] │ │ movs r4, r0 │ │ ldmia r1, {r0, r1, r3, r4, r5, r6} │ │ @ instruction: 0xffff8fd4 │ │ movs r2, r0 │ │ - ldrb r5, [r1, #2] │ │ + ldrb r2, [r7, #2] │ │ ldc2 3, cr5, [r3, #672]! @ 0x2a0 │ │ movs r4, r0 │ │ strh r0, [r4, r6] │ │ movs r4, r0 │ │ ldmia r1!, {r0, r2, r4, r6} │ │ @ instruction: 0xffff8fae │ │ movs r2, r0 │ │ @@ -2035048,15 +2035048,15 @@ │ │ strh r0, [r2, r2] │ │ movs r4, r0 │ │ strh r4, [r0, r2] │ │ movs r4, r0 │ │ ldmia r0, {r0, r3, r5, r6} │ │ vqrdmlah.s q12, , d2[0] │ │ movs r2, r0 │ │ - asrs r5, r2, #30 │ │ + asrs r2, r0, #31 │ │ ldc2 2, cr5, [r4, #640]! @ 0x280 │ │ movs r4, r0 │ │ strh r0, [r3, r2] │ │ movs r4, r0 │ │ ldmia r0, {r0, r1, r6} │ │ @ instruction: 0xffff8e9c │ │ movs r2, r0 │ │ @@ -2035153,15 +2035153,15 @@ │ │ str r2, [r0, r6] │ │ movs r4, r0 │ │ str r6, [r6, r5] │ │ movs r4, r0 │ │ stmia r7!, {r0, r2, r5, r6} │ │ @ instruction: 0xffff8dbe │ │ movs r2, r0 │ │ - ldr r3, [sp, #456] @ 0x1c8 │ │ + ldr r3, [sp, #636] @ 0x27c │ │ ldc2 1, cr5, [r2, #584]! @ 0x248 │ │ movs r4, r0 │ │ str r2, [r1, r6] │ │ movs r4, r0 │ │ stmia r7!, {r0, r1, r2, r3, r4, r5} │ │ @ instruction: 0xffff8d98 │ │ movs r2, r0 │ │ @@ -2035771,27 +2035771,27 @@ │ │ movs r0, #1 │ │ str.w r3, [r9, #28] │ │ b.n 26f702c │ │ ldr r0, [r5, #48] @ 0x30 │ │ ldr r6, [pc, #440] @ (26f7280 ) │ │ lsls r6, r2, #27 │ │ movs r4, r0 │ │ - strb r0, [r5, #11] │ │ - ldc2 2, cr7, [r2, #980]! @ 0x3d4 │ │ - ldc2 5, cr13, [r2, #664]! @ 0x298 │ │ + strb r5, [r2, #12] │ │ + ldc2 3, cr7, [r2, #136]! @ 0x88 │ │ + ldc2 5, cr13, [r2, #844]! @ 0x34c │ │ ldc2 8, cr6, [r2, #356]! @ 0x164 │ │ - ldc2 7, cr5, [r5, #272]! @ 0x110 │ │ + ldc2 7, cr5, [r5, #452]! @ 0x1c4 │ │ ldc2 5, cr15, [r3, #924]! @ 0x39c │ │ - ldc2 12, cr12, [r1, #888]! @ 0x378 │ │ - ldc2 4, cr11, [r3, #804]! @ 0x324 │ │ - ldc2 6, cr1, [r2, #620]! @ 0x26c │ │ + ldc2 13, cr12, [r1, #44]! @ 0x2c │ │ + ldc2 4, cr11, [r3, #984]! @ 0x3d8 │ │ + ldc2 6, cr1, [r2, #800]! @ 0x320 │ │ ldc2 2, cr3, [r3, #172]! @ 0xac │ │ - ldc2 15, cr15, [r4, #932]! @ 0x3a4 │ │ - ldc2 13, cr14, [r2, #712]! @ 0x2c8 │ │ - ldc2 15, cr15, [r3, #572]! @ 0x23c │ │ + ldc2 0, cr0, [r4, #88]! @ 0x58 │ │ + ldc2 13, cr14, [r3, #892]! @ 0x37c │ │ + ldc2 15, cr15, [r3, #752]! @ 0x2f0 │ │ Address 0x26f70fe is out of bounds. │ │ │ │ │ │ 026f7100 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -2035882,16 +2035882,16 @@ │ │ cmp r0, #0 │ │ beq.n 26f7154 │ │ ldr r0, [r5, #0] │ │ ldr r1, [r0, #68] @ 0x44 │ │ mov r0, r5 │ │ blx r1 │ │ b.n 26f7154 │ │ - str r5, [sp, #140] @ 0x8c │ │ - ldc2 5, cr9, [r2, #112]! @ 0x70 │ │ + str r5, [sp, #320] @ 0x140 │ │ + ldc2 5, cr9, [r2, #292]! @ 0x124 │ │ ldc2 0, cr4, [r2, #204]! @ 0xcc │ │ ldc2 4, cr3, [r5, #864]! @ 0x360 │ │ ldc2 15, cr3, [r2, #860]! @ 0x35c │ │ Address 0x26f71e6 is out of bounds. │ │ │ │ │ │ 026f71e8 <_JNIEnv::CallFloatMethod(_jobject*, _jmethodID*, ...)@@Base>: │ │ @@ -2036559,16 +2036559,16 @@ │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ lsls r2, r4, #1 │ │ movs r4, r0 │ │ ldr r2, [r0, #28] │ │ lsls r3, r7, #22 │ │ - str r7, [r2, r4] │ │ - ldc2 14, cr10, [r3, #712]! @ 0x2c8 │ │ + str r4, [r0, r5] │ │ + ldc2 14, cr10, [r3, #892]! @ 0x37c │ │ vcmla.f32 d4, d2, d29, #270 │ │ add r0, pc │ │ blx 2701a70 │ │ cmp r0, #0 │ │ beq.w 26f75f0 │ │ movs r0, #6 │ │ movw r1, #20559 @ 0x504f │ │ @@ -2036635,15 +2036635,15 @@ │ │ movs r0, r0 │ │ str r2, [r2, #96] @ 0x60 │ │ lsls r3, r7, #22 │ │ ldrb r4, [r0, #28] │ │ movs r2, r0 │ │ str r4, [r2, #96] @ 0x60 │ │ lsls r3, r7, #22 │ │ - ldmia r7!, {r0, r4} │ │ + ldmia r7!, {r1, r2, r3, r4, r5} │ │ ldc2 7, cr8, [r2, #976]! @ 0x3d0 │ │ ldc2 9, cr6, [r4, #68]! @ 0x44 @ │ │ lsls r3, r7, #22 │ │ bmi.n 26f7968 │ │ bmi.n 26f796a │ │ │ │ 026f79c0 : │ │ @@ -2037384,15 +2037384,15 @@ │ │ subs r3, #206 @ 0xce │ │ movs r4, r0 │ │ subs r3, #188 @ 0xbc │ │ movs r4, r0 │ │ cbz r5, 26f8168 │ │ @ instruction: 0xffff776e │ │ movs r2, r0 │ │ - strh r7, [r4, #46] @ 0x2e │ │ + strh r4, [r2, #48] @ 0x30 │ │ ldc2 3, cr15, [r2, #880]! @ 0x370 │ │ movs r3, r0 │ │ usat16 r0, #3, lr │ │ sub sp, #444 @ 0x1bc │ │ @ instruction: 0xffff7748 │ │ movs r2, r0 │ │ │ │ @@ -2038109,27 +2038109,27 @@ │ │ adds r4, #74 @ 0x4a │ │ movs r4, r0 │ │ adds r4, #46 @ 0x2e │ │ movs r4, r0 │ │ add r1, sp, #652 @ 0x28c │ │ @ instruction: 0xffff6ffc │ │ movs r2, r0 │ │ - ldrb r1, [r7, #14] │ │ + ldrb r6, [r4, #15] │ │ ldc2 9, cr10, [r3, #246]! @ 0xf6 @ │ │ @ instruction: 0xffff6fd4 │ │ movs r2, r0 │ │ - push {r0, r2, r3, r4, r5, r6} │ │ + push {r1, r3, r5, r7} │ │ ldc2 9, cr10, [r3, #166]! @ 0xa6 @ │ │ @ instruction: 0xffff6fac │ │ movs r2, r0 │ │ adds r4, r6, #7 │ │ ldc2 9, cr10, [r2, #86]! @ 0x56 @ │ │ @ instruction: 0xffff6f84 │ │ movs r2, r0 │ │ - ldr r4, [sp, #352] @ 0x160 │ │ + ldr r4, [sp, #532] @ 0x214 │ │ Address 0x26f894e is out of bounds. │ │ │ │ │ │ 026f8950 >)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -2038406,25 +2038406,25 @@ │ │ adds r0, #182 @ 0xb6 │ │ movs r4, r0 │ │ adds r0, #174 @ 0xae │ │ movs r4, r0 │ │ add r6, pc, #276 @ (adr r6, 26f8d50 >, std::__ndk1::chrono::duration >)@@Base+0x48>) │ │ @ instruction: 0xffff6c9e │ │ movs r2, r0 │ │ - bls.n 26f8c98 │ │ + bls.n 26f8cf2 │ │ ldc2 0, cr3, [r2, #336]! @ 0x150 │ │ movs r4, r0 │ │ cmp r7, #172 @ 0xac │ │ movs r4, r0 │ │ add r6, pc, #100 @ (adr r6, 26f8cb4 ) │ │ vcvt.f16.u16 q11, q9, #1 │ │ movs r2, r0 │ │ adds r0, #68 @ 0x44 │ │ movs r4, r0 │ │ - bhi.n 26f8b80 >)@@Base+0x230> │ │ + bhi.n 26f8bda >)@@Base+0x28a> │ │ Address 0x26f8c5a is out of bounds. │ │ │ │ │ │ 026f8c5c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ @@ -2038822,19 +2038822,19 @@ │ │ cmp r4, #46 @ 0x2e │ │ movs r4, r0 │ │ cmp r4, #38 @ 0x26 │ │ movs r4, r0 │ │ add r2, pc, #36 @ (adr r2, 26f9094 ) │ │ vtbx.8 d22, {d15}, d18 │ │ movs r2, r0 │ │ - str r4, [sp, #840] @ 0x348 │ │ + str r4, [sp, #1020] @ 0x3fc │ │ ldc2 1, cr10, [r2, #908]! @ 0x38c │ │ vqshrun.s64 d22, q14, #1 │ │ movs r2, r0 │ │ - add r4, sp, #700 @ 0x2bc │ │ + add r4, sp, #880 @ 0x370 │ │ Address 0x26f9082 is out of bounds. │ │ │ │ │ │ 026f9084 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -2039648,15 +2039648,15 @@ │ │ movs r5, #210 @ 0xd2 │ │ movs r4, r0 │ │ movs r5, #188 @ 0xbc │ │ movs r4, r0 │ │ ldr r1, [sp, #692] @ 0x2b4 │ │ vaddl.u q11, d15, d6 │ │ movs r2, r0 │ │ - cmp r3, #32 │ │ + cmp r3, #77 @ 0x4d │ │ ldc2 9, cr9, [r2, #178]! @ 0xb2 @ │ │ @ instruction: 0xffff5fb2 │ │ movs r2, r0 │ │ iteee cc │ │ ldc2cc 9, cr9, [r4, #6]! @ │ │ vcvtcs.u32.f32 , q6, #1 │ │ movcs r2, r0 │ │ @@ -2040330,15 +2040330,15 @@ │ │ subs r2, r4, r5 │ │ movs r4, r0 │ │ subs r0, r2, r5 │ │ movs r4, r0 │ │ str r1, [sp, #476] @ 0x1dc │ │ vqshl.u64 , q0, #63 @ 0x3f │ │ movs r2, r0 │ │ - strh r2, [r5, #32] │ │ + strh r7, [r2, #34] @ 0x22 │ │ Address 0x26fa0de is out of bounds. │ │ │ │ │ │ 026fa0e0 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -2040441,19 +2040441,19 @@ │ │ subs r2, r6, r2 │ │ movs r4, r0 │ │ subs r6, r4, r2 │ │ movs r4, r0 │ │ str r0, [sp, #556] @ 0x22c │ │ vmlsl.u , d31, d20[0] │ │ movs r2, r0 │ │ - lsls r2, r0, #15 │ │ + lsls r7, r5, #15 │ │ ldc2 0, cr9, [r3, #404]! @ 0x194 │ │ vqshlu.s64 d21, d30, #63 @ 0x3f │ │ movs r2, r0 │ │ - strh r6, [r7, #24] │ │ + strh r3, [r5, #26] │ │ Address 0x26fa1fa is out of bounds. │ │ │ │ │ │ 026fa1fc : │ │ cmp r1, #0 │ │ it mi │ │ bxmi lr │ │ @@ -2043298,27 +2043298,27 @@ │ │ blx 271e020 │ │ bl 26f26b2 > >)@@Base+0x2e> │ │ ldr r1, [pc, #40] @ (26fc028 ) │ │ movs r0, #1 │ │ add r1, pc │ │ blx 271e020 │ │ nop │ │ - strh r7, [r5, #42] @ 0x2a │ │ + strh r4, [r3, #44] @ 0x2c │ │ ldc2 13, cr15, [r2, #608]! @ 0x260 │ │ movs r3, r0 │ │ stc2 0, cr0, [ip, #12] │ │ strb r1, [r6, #10] │ │ vtbl.8 d19, {d15-d16}, d10 │ │ movs r2, r0 │ │ lsls r3, r4, #6 │ │ ldc2 2, cr7, [r4, #548]! @ 0x224 │ │ vtbx.8 d19, {d31}, d18 │ │ movs r2, r0 │ │ bl 25d2b94 │ │ - ldrsh r4, [r4, r6] │ │ + ldrsh r1, [r2, r7] │ │ ldc2 0, cr15, [r3, #8]! │ │ pop {r4, r7} │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ movs r0, #8 │ │ blx 26ffbf0 │ │ @@ -2043839,15 +2043839,15 @@ │ │ cbz r2, 26fc58c │ │ movs r3, r0 │ │ @ instruction: 0xf74e0003 │ │ @ instruction: 0xf74a0003 │ │ ldr r7, [r7, #88] @ 0x58 │ │ vsri.32 d19, d4, #1 │ │ movs r2, r0 │ │ - stc2l 13, cr15, [lr], #708 @ 0x2c4 │ │ + ldc2 13, cr15, [fp, #-708] @ 0xfffffd3c │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ sub sp, #16 │ │ mov r6, r0 │ │ ldr r0, [pc, #216] @ (26fc64c ) │ │ mov r5, r1 │ │ @@ -2043930,16 +2043930,16 @@ │ │ movs r0, #35 @ 0x23 │ │ add r1, pc │ │ blx 271e020 │ │ nop │ │ sub sp, #224 @ 0xe0 │ │ movs r3, r0 │ │ bl 27a31bc <_nl_msg_cat_cntr@@Base+0x11c1c> │ │ - ldrb r5, [r3, #28] │ │ - ldc2 9, cr5, [r2, #164]! @ 0xa4 @ │ │ + ldrb r2, [r1, #29] │ │ + ldc2 9, cr5, [r2, #254]! @ 0xfe @ │ │ ldc2 0, cr15, [r3, #8]! │ │ cbnz r2, 26fc680 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ movs r0, #8 │ │ blx 26ffbf0 │ │ @@ -2044154,22 +2044154,22 @@ │ │ nop │ │ add r7, sp, #488 @ 0x1e8 │ │ movs r3, r0 │ │ stmia r0!, {r0, r1, r4, r6, r7} │ │ ldc2 11, cr2, [r4, #936]! @ 0x3a8 @ │ │ ldc2 15, cr8, [r5, #708]! @ 0x2c4 │ │ ldc2 5, cr11, [r4, #740]! @ 0x2e4 │ │ - ldc2 15, cr3, [r4, #336]! @ 0x150 │ │ - ldc2 15, cr3, [r2, #348]! @ 0x15c │ │ + ldc2 15, cr3, [r4, #516]! @ 0x204 │ │ + ldc2 15, cr3, [r2, #528]! @ 0x210 │ │ ldc2 11, cr1, [r2, #304]! @ 0x130 @ │ │ ldc2 4, cr7, [r4, #452]! @ 0x1c4 │ │ - ldc2 9, cr1, [r4, #438]! @ 0x1b6 @ │ │ + ldc2 10, cr1, [r4, #32]! @ │ │ ldc2 11, cr2, [r3, #536]! @ 0x218 @ │ │ ldc2 8, cr15, [r5, #632]! @ 0x278 │ │ - ldc2 9, cr11, [r3, #420]! @ 0x1a4 @ │ │ + ldc2 9, cr11, [r3, #510]! @ 0x1fe @ │ │ ldc2 4, cr15, [r3, #112]! @ 0x70 │ │ movs r3, r0 │ │ add r4, sp, #528 @ 0x210 │ │ movs r3, r0 │ │ │ │ 026fc8bc : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -2044671,15 +2044671,15 @@ │ │ add r2, sp, #248 @ 0xf8 │ │ movs r3, r0 │ │ vext.8 d0, d0, d3, #0 │ │ vaddl.s32 q0, d12, d3 │ │ str r1, [r4, #96] @ 0x60 │ │ vcvt.f16.u16 q9, q11, #1 │ │ movs r2, r0 │ │ - bhi.n 26fcd18 │ │ + bhi.n 26fcd72 │ │ ldc2 0, cr15, [r2, #4]! │ │ pop {r4, r6, r7, pc} │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ movs r0, #8 │ │ blx 26ffbf0 │ │ @@ -2045479,26 +2045479,26 @@ │ │ lsrs r4, r0, #6 │ │ lsls r3, r7, #22 │ │ lsrs r6, r0, #19 │ │ lsls r3, r7, #22 │ │ bcc.n 26fd718 │ │ ldc2 3, cr14, [r1, #928]! @ 0x3a0 │ │ ldc2 9, cr11, [r4, #140]! @ 0x8c @ │ │ - ldc2 2, cr3, [r3, #716]! @ 0x2cc │ │ + ldc2 2, cr3, [r3, #896]! @ 0x380 │ │ ldc2 7, cr6, [r2, #896]! @ 0x380 │ │ - vcmla.f32 q3, q10, , #270 │ │ - ldc2 2, cr3, [r3, #172]! @ 0xac │ │ + ldc2 9, cr6, [r4, #40]! @ 0x28 @ │ │ + ldc2 2, cr3, [r3, #352]! @ 0x160 │ │ vcmla.f32 q5, q1, q15, #270 │ │ - ldc2 8, cr6, [r4, #380]! @ 0x17c │ │ - ldc2 1, cr3, [r3, #652]! @ 0x28c │ │ + vcmla.f32 d6, d20, d12, #270 │ │ + ldc2 1, cr3, [r3, #832]! @ 0x340 │ │ ldc2 11, cr6, [r2, #808]! @ 0x328 @ │ │ - ldc2 7, cr6, [r1, #844]! @ 0x34c │ │ - ldc2 1, cr3, [r3, #100]! @ 0x64 │ │ - ldc2 11, cr0, [r2, #724]! @ 0x2d4 @ │ │ - ldc2 7, cr6, [r3, #292]! @ 0x124 │ │ + vcmla.f32 d6, d1, d0, #270 │ │ + ldc2 1, cr3, [r3, #280]! @ 0x118 │ │ + ldc2 11, cr0, [r2, #904]! @ 0x388 @ │ │ + ldc2 7, cr6, [r3, #472]! @ 0x1d8 │ │ Address 0x26fd68a is out of bounds. │ │ │ │ │ │ 026fd68c : │ │ strb.w r1, [r0, #248] @ 0xf8 │ │ bx lr │ │ │ │ @@ -2045648,15 +2045648,15 @@ │ │ moveq r0, r4 │ │ addeq sp, #24 │ │ ldreq.w fp, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 26ffb50 │ │ ldr r6, [sp, #600] @ 0x258 │ │ movs r3, r0 │ │ - cmp r6, #189 @ 0xbd │ │ + cmp r6, #234 @ 0xea │ │ Address 0x26fd812 is out of bounds. │ │ │ │ │ │ 026fd814 : │ │ push {r7, lr} │ │ mov r7, sp │ │ blx 271df90 │ ├── readelf --wide --decompress --hex-dump=.data.rel.ro {} │ │ @@ -26,207 +26,207 @@ │ │ 0x0271fa00 00000000 00000000 05520902 00000000 .........R...... │ │ 0x0271fa10 0d520902 08000000 00000000 00000000 .R.............. │ │ 0x0271fa20 08000000 50262500 00000000 00000000 ....P&%......... │ │ 0x0271fa30 20fa7102 00000000 6df60902 00000000 .q.....m....... │ │ 0x0271fa40 a7a70e02 aba70e02 b9a70e02 39ab0e02 ............9... │ │ 0x0271fa50 05ac0e02 31ae0e02 9db00e02 adb10e02 ....1........... │ │ 0x0271fa60 39b40e02 15b50e02 75b50e02 0db60e02 9.......u....... │ │ - 0x0271fa70 00000000 74662200 01000000 18002400 ....tf".......$. │ │ - 0x0271fa80 02000000 62822300 03000000 34202300 ....b.#.....4 #. │ │ + 0x0271fa70 00000000 a1662200 01000000 18002400 .....f".......$. │ │ + 0x0271fa80 02000000 8f822300 03000000 61202300 ......#.....a #. │ │ 0x0271fa90 04000000 06a82100 05000000 85f42400 ......!.......$. │ │ 0x0271faa0 06000000 411f2400 07000000 451f2400 ....A.$.....E.$. │ │ 0x0271fab0 08000000 07d92400 09000000 f48a2100 ......$.......!. │ │ - 0x0271fac0 0a000000 0cd92400 0b000000 3c5f2300 ......$.....<_#. │ │ + 0x0271fac0 0a000000 0cd92400 0b000000 695f2300 ......$.....i_#. │ │ 0x0271fad0 0c000000 19a42300 0d000000 8d3c2400 ......#......<$. │ │ 0x0271fae0 0e000000 67422100 00000000 00000000 ....gB!......... │ │ 0x0271faf0 00000000 00000000 00000000 00000000 ................ │ │ 0x0271fb00 00000000 00000000 00000000 00000000 ................ │ │ 0x0271fb10 00000000 08000000 00000000 00000000 ................ │ │ - 0x0271fb20 26e22200 8e3d2300 90a32300 bdc02300 &."..=#...#...#. │ │ - 0x0271fb30 9cd82400 073e2300 a98a2100 d0ff2300 ..$..>#...!...#. │ │ - 0x0271fb40 1e3e2300 2bc12300 c3c02300 6ce32100 .>#.+.#...#.l.!. │ │ - 0x0271fb50 92252200 617d2400 7bff2300 c53d2300 .%".a}$.{.#..=#. │ │ - 0x0271fb60 acc22100 d31e2400 757d2400 76a72100 ..!...$.u}$.v.!. │ │ - 0x0271fb70 503c2400 ff872200 37422100 d0c02300 P<$...".7B!...#. │ │ - 0x0271fb80 90ff2300 53672100 6c672100 34a62200 ..#.Sg!.lg!.4.". │ │ - 0x0271fb90 7e212100 98a32300 bec22100 c3c72200 ~!!...#...!...". │ │ - 0x0271fba0 e61e2400 42662200 bc462200 ccc22100 ..$.Bf"..F"...!. │ │ - 0x0271fbb0 f6812300 7a8a2100 dac22100 5ee32300 ..#.z.!...!.^.#. │ │ - 0x0271fbc0 e8042300 04822300 96212100 643c2400 ..#...#..!!.d<$. │ │ - 0x0271fbd0 50662200 f41e2400 13822300 f7042300 Pf"...$...#...#. │ │ + 0x0271fb20 53e22200 bb3d2300 90a32300 bdc02300 S."..=#...#...#. │ │ + 0x0271fb30 9cd82400 343e2300 a98a2100 d0ff2300 ..$.4>#...!...#. │ │ + 0x0271fb40 4b3e2300 2bc12300 c3c02300 99e32100 K>#.+.#...#...!. │ │ + 0x0271fb50 bf252200 617d2400 7bff2300 f23d2300 .%".a}$.{.#..=#. │ │ + 0x0271fb60 d9c22100 d31e2400 757d2400 76a72100 ..!...$.u}$.v.!. │ │ + 0x0271fb70 503c2400 2c882200 37422100 d0c02300 P<$.,.".7B!...#. │ │ + 0x0271fb80 90ff2300 53672100 6c672100 61a62200 ..#.Sg!.lg!.a.". │ │ + 0x0271fb90 7e212100 98a32300 ebc22100 f0c72200 ~!!...#...!...". │ │ + 0x0271fba0 e61e2400 6f662200 e9462200 f9c22100 ..$.of"..F"...!. │ │ + 0x0271fbb0 23822300 7a8a2100 07c32100 5ee32300 #.#.z.!...!.^.#. │ │ + 0x0271fbc0 15052300 31822300 96212100 643c2400 ..#.1.#..!!.d<$. │ │ + 0x0271fbd0 7d662200 f41e2400 40822300 24052300 }f"...$.@.#.$.#. │ │ 0x0271fbe0 e3c02300 a5212100 888a2100 f2c02300 ..#..!!...!...#. │ │ - 0x0271fbf0 91a72100 6ce32300 f9952400 d13d2300 ..!.l.#...$..=#. │ │ - 0x0271fc00 22822300 13202300 6b582400 7a582400 ".#.. #.kX$.zX$. │ │ - 0x0271fc10 89582400 98582400 efe22200 0a000000 .X$..X$..."..... │ │ + 0x0271fbf0 91a72100 6ce32300 f9952400 fe3d2300 ..!.l.#...$..=#. │ │ + 0x0271fc00 4f822300 40202300 6b582400 7a582400 O.#.@ #.kX$.zX$. │ │ + 0x0271fc10 89582400 98582400 1ce32200 0a000000 .X$..X$..."..... │ │ 0x0271fc20 00000000 00000000 5b1e2400 06000000 ........[.$..... │ │ - 0x0271fc30 01000000 01000000 28212300 09000000 ........(!#..... │ │ - 0x0271fc40 03000000 01000000 d23c2300 05000000 .........<#..... │ │ + 0x0271fc30 01000000 01000000 55212300 09000000 ........U!#..... │ │ + 0x0271fc40 03000000 01000000 ff3c2300 05000000 .........<#..... │ │ 0x0271fc50 06000000 01000000 58592400 09000000 ........XY$..... │ │ 0x0271fc60 05000000 02000000 00000000 00000000 ................ │ │ 0x0271fc70 00000000 00000000 00000000 00000000 ................ │ │ 0x0271fc80 00000000 00000000 00000000 00000000 ................ │ │ 0x0271fc90 00000000 00000000 00000000 00000000 ................ │ │ 0x0271fca0 00000000 00000000 08000000 00000000 ................ │ │ - 0x0271fcb0 00000000 43682100 9b822300 7a002400 ....Ch!...#.z.$. │ │ - 0x0271fcc0 7e002400 9f822300 c7962400 ecc82200 ~.$...#...$...". │ │ - 0x0271fcd0 f0c82200 90b92400 a31f2400 82002400 .."...$...$...$. │ │ + 0x0271fcb0 00000000 43682100 c8822300 7a002400 ....Ch!...#.z.$. │ │ + 0x0271fcc0 7e002400 cc822300 c7962400 19c92200 ~.$...#...$...". │ │ + 0x0271fcd0 1dc92200 90b92400 a31f2400 82002400 .."...$...$...$. │ │ 0x0271fce0 2ea92100 44d92400 29e42300 063d2400 ..!.D.$.).#..=$. │ │ - 0x0271fcf0 97b92400 52262200 ab1f2400 ab072200 ..$.R&"...$...". │ │ - 0x0271fd00 0a3d2400 f8a62200 90422100 58222100 .=$..."..B!.X"!. │ │ - 0x0271fd10 47682100 27f52400 cb962400 fae22200 Gh!.'.$...$...". │ │ - 0x0271fd20 cfe32100 5c222100 0e3d2400 ab072200 ..!.\"!..=$...". │ │ - 0x0271fd30 af072200 853e2300 4fc32100 94422100 .."..>#.O.!..B!. │ │ - 0x0271fd40 143d2400 02e32200 a8592400 00000000 .=$..."..Y$..... │ │ + 0x0271fcf0 97b92400 7f262200 ab1f2400 d8072200 ..$..&"...$...". │ │ + 0x0271fd00 0a3d2400 25a72200 90422100 58222100 .=$.%."..B!.X"!. │ │ + 0x0271fd10 47682100 27f52400 cb962400 27e32200 Gh!.'.$...$.'.". │ │ + 0x0271fd20 fce32100 5c222100 0e3d2400 d8072200 ..!.\"!..=$...". │ │ + 0x0271fd30 dc072200 b23e2300 7cc32100 94422100 .."..>#.|.!..B!. │ │ + 0x0271fd40 143d2400 2fe32200 a8592400 00000000 .=$./."..Y$..... │ │ 0x0271fd50 00000000 00000000 00000000 a9b71002 ................ │ │ 0x0271fd60 00000000 afb71002 08000000 00000000 ................ │ │ - 0x0271fd70 00000000 00000000 32212300 09000000 ........2!#..... │ │ - 0x0271fd80 f0f8ffff 8b5f2300 0c000000 faebd7ff ....._#......... │ │ + 0x0271fd70 00000000 00000000 5f212300 09000000 ........_!#..... │ │ + 0x0271fd80 f0f8ffff b85f2300 0c000000 faebd7ff ....._#......... │ │ 0x0271fd90 9bb92400 04000000 00ffffff 4bd92400 ..$.........K.$. │ │ - 0x0271fda0 0a000000 7fffd4ff 01a72200 05000000 .........."..... │ │ + 0x0271fda0 0a000000 7fffd4ff 2ea72200 05000000 .........."..... │ │ 0x0271fdb0 f0ffffff b81f2400 05000000 f5f5dcff ......$......... │ │ 0x0271fdc0 808b2100 06000000 ffe4c4ff dfa42300 ..!...........#. │ │ 0x0271fdd0 05000000 000000ff f0962400 0e000000 ..........$..... │ │ 0x0271fde0 ffebcdff 1c3d2400 04000000 0000ffff .....=$......... │ │ - 0x0271fdf0 2bf52400 0a000000 8a2be2ff 6ec32100 +.$......+..n.!. │ │ + 0x0271fdf0 2bf52400 0a000000 8a2be2ff 9bc32100 +.$......+....!. │ │ 0x0271fe00 05000000 a52a2aff 36f52400 09000000 .....**.6.$..... │ │ - 0x0271fe10 deb887ff 07a72200 09000000 5f9ea0ff ......"....._... │ │ + 0x0271fe10 deb887ff 34a72200 09000000 5f9ea0ff ....4."....._... │ │ 0x0271fe20 a0b92400 0a000000 7fff00ff abb92400 ..$...........$. │ │ 0x0271fe30 09000000 d2691eff 467e2400 05000000 .....i..F~$..... │ │ 0x0271fe40 ff7f50ff 40f52400 0e000000 6495edff ..P.@.$.....d... │ │ - 0x0271fe50 11a72200 08000000 fff8dcff 85882200 .."...........". │ │ - 0x0271fe60 07000000 dc143cff 8d882200 04000000 ......<..."..... │ │ + 0x0271fe50 3ea72200 08000000 fff8dcff b2882200 >."...........". │ │ + 0x0271fe60 07000000 dc143cff ba882200 04000000 ......<..."..... │ │ 0x0271fe70 00ffffff 4b682100 08000000 00008bff ....Kh!......... │ │ - 0x0271fe80 56d92400 08000000 008b8bff f7c82200 V.$...........". │ │ + 0x0271fe80 56d92400 08000000 008b8bff 24c92200 V.$.........$.". │ │ 0x0271fe90 0d000000 b8860bff 213d2400 08000000 ........!=$..... │ │ 0x0271fea0 a9a9a9ff b5b92400 09000000 006400ff ......$......d.. │ │ - 0x0271feb0 a1052300 09000000 bdb76bff 56262200 ..#.......k.V&". │ │ - 0x0271fec0 0b000000 8b008bff ba662200 0e000000 .........f"..... │ │ + 0x0271feb0 ce052300 09000000 bdb76bff 83262200 ..#.......k..&". │ │ + 0x0271fec0 0b000000 8b008bff e7662200 0e000000 .........f"..... │ │ 0x0271fed0 556b2fff 8c002400 0a000000 ff8c00ff Uk/...$......... │ │ 0x0271fee0 97002400 0a000000 9932ccff 54682100 ..$......2..Th!. │ │ - 0x0271fef0 07000000 8b0000ff a6472200 0a000000 .........G"..... │ │ - 0x0271ff00 e9967aff ab052300 0c000000 8fbc8fff ..z...#......... │ │ - 0x0271ff10 37a92100 0d000000 483d8bff 92882200 7.!.....H=....". │ │ - 0x0271ff20 0d000000 2f4f4fff b1472200 0d000000 ..../OO..G"..... │ │ - 0x0271ff30 00ced1ff 62262200 0a000000 9400d3ff ....b&"......... │ │ + 0x0271fef0 07000000 8b0000ff d3472200 0a000000 .........G"..... │ │ + 0x0271ff00 e9967aff d8052300 0c000000 8fbc8fff ..z...#......... │ │ + 0x0271ff10 37a92100 0d000000 483d8bff bf882200 7.!.....H=....". │ │ + 0x0271ff20 0d000000 2f4f4fff de472200 0d000000 ..../OO..G"..... │ │ + 0x0271ff30 00ced1ff 8f262200 0a000000 9400d3ff .....&"......... │ │ 0x0271ff40 9e422100 08000000 ff1493ff 5c682100 .B!.........\h!. │ │ 0x0271ff50 0b000000 00bfffff 45a92100 07000000 ........E.!..... │ │ 0x0271ff60 696969ff ff962400 0a000000 1e90ffff iii...$......... │ │ 0x0271ff70 e5a42300 09000000 b22222ff 62222100 ..#......"".b"!. │ │ - 0x0271ff80 0b000000 fffaf0ff 0be32200 0b000000 .........."..... │ │ - 0x0271ff90 228b22ff 6d262200 07000000 ff00ffff ".".m&"......... │ │ - 0x0271ffa0 bd822300 09000000 dcdcdcff 2a3d2400 ..#.........*=$. │ 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08000000 00000000 00000000 93642100 .............d!. │ │ - 0x02736360 05000000 1d032300 00000000 86942400 ......#.......$. │ │ + 0x02736360 05000000 4a032300 00000000 86942400 ....J.#.......$. │ │ 0x02736370 03000000 84d72400 02000000 e9102500 ......$.......%. │ │ - 0x02736380 01000000 f6102500 04000000 09e02200 ......%.......". │ │ - 0x02736390 07000000 2b802300 00000000 72232200 ....+.#.....r#". │ │ + 0x02736380 01000000 f6102500 04000000 36e02200 ......%.....6.". │ │ + 0x02736390 07000000 58802300 00000000 9f232200 ....X.#......#". │ │ 0x027363a0 01000000 2b1d2400 02000000 91d72400 ....+.$.......$. │ │ 0x027363b0 03000000 e3be2300 0f000000 34fb2300 ......#.....4.#. │ │ - 0x027363c0 10000000 5ca42200 11000000 67a12300 ....\.".....g.#. │ │ - 0x027363d0 14000000 e2542400 15000000 33802300 .....T$.....3.#. │ │ - 0x027363e0 18000000 14e02200 19000000 00000000 ......"......... │ │ - 0x027363f0 c9822200 00000000 00000000 00000000 .."............. │ │ + 0x027363c0 10000000 89a42200 11000000 67a12300 ......".....g.#. │ │ + 0x027363d0 14000000 e2542400 15000000 60802300 .....T$.....`.#. │ │ + 0x027363e0 18000000 41e02200 19000000 00000000 ....A."......... │ │ + 0x027363f0 f6822200 00000000 00000000 00000000 .."............. │ │ 0x02736400 00000000 00000000 00000000 00000000 ................ │ │ 0x02736410 00000000 00000000 2c647302 c8206a02 ........,ds.. j. │ │ 0x02736420 4c216a02 00000000 88216a02 08000000 L!j......!j..... │ │ 0x02736430 b2be0702 00000000 00000000 00000000 ................ │ │ 0x02736440 00000000 00000000 00000000 00000000 ................ │ │ 0x02736450 00000000 00000000 00000000 00000000 ................ │ │ 0x02736460 08000000 00000000 00000000 08000000 ................ │ │ @@ -5862,19 +5862,19 @@ │ │ 0x027366c0 00000000 00000000 00000000 00000000 ................ │ │ 0x027366d0 00000000 00000000 00000000 00000000 ................ │ │ 0x027366e0 00000000 08000000 00000000 00000000 ................ │ │ 0x027366f0 00000000 00000000 00000000 00000000 ................ │ │ 0x02736700 00000000 00000000 00000000 08000000 ................ │ │ 0x02736710 00000000 00000000 00000000 30677302 ............0gs. │ │ 0x02736720 00000000 58296b02 00000000 6c296b02 ....X)k.....l)k. │ │ - 0x02736730 08000000 29c70702 00000000 82802300 ....).........#. │ │ - 0x02736740 5c3c2300 93bf2300 ebe12300 04e22300 \<#...#...#...#. │ │ - 0x02736750 de232200 f5232200 d5e12100 c7c62200 .#"..#"...!...". │ │ - 0x02736760 d5c62200 faa12300 6a1f2300 9b802300 .."...#.j.#...#. │ │ - 0x02736770 8de02200 00000000 00000000 00000000 .."............. │ │ + 0x02736730 08000000 29c70702 00000000 af802300 ....).........#. │ │ + 0x02736740 893c2300 93bf2300 ebe12300 04e22300 .<#...#...#...#. │ │ + 0x02736750 0b242200 22242200 02e22100 f4c62200 .$"."$"...!...". │ │ + 0x02736760 02c72200 faa12300 971f2300 c8802300 .."...#...#...#. │ │ + 0x02736770 bae02200 00000000 00000000 00000000 .."............. │ │ 0x02736780 00000000 00000000 00000000 00000000 ................ │ │ 0x02736790 00000000 00000000 08000000 00000000 ................ │ │ 0x027367a0 00000000 00000000 00000000 00000000 ................ │ │ 0x027367b0 00000000 00000000 00000000 08000000 ................ │ │ 0x027367c0 00000000 00000000 00000000 00000000 ................ │ │ 0x027367d0 00000000 00000000 00000000 00000000 ................ │ │ 0x027367e0 00000000 00000000 00000000 00000000 ................ │ │ @@ -5955,16 +5955,16 @@ │ │ 0x02736c90 00000000 00000000 00000000 00000000 ................ │ │ 0x02736ca0 00000000 00000000 00000000 00000000 ................ │ │ 0x02736cb0 00000000 00000000 00000000 00000000 ................ │ │ 0x02736cc0 00000000 00000000 00000000 00000000 ................ │ │ 0x02736cd0 00000000 00000000 00000000 00000000 ................ │ │ 0x02736ce0 00000000 00000000 08000000 00000000 ................ │ │ 0x02736cf0 00000000 08000000 00000000 00000000 ................ │ │ - 0x02736d00 b6942400 9a1d2400 9be02200 98b62400 ..$...$..."...$. │ │ - 0x02736d10 b6b62400 09a22300 75862200 49112500 ..$...#.u.".I.%. │ │ + 0x02736d00 b6942400 9a1d2400 c8e02200 98b62400 ..$...$..."...$. │ │ + 0x02736d10 b6b62400 09a22300 a2862200 49112500 ..$...#...".I.%. │ │ 0x02736d20 00000000 386d7302 00000000 c4a66d02 ....8ms.......m. │ │ 0x02736d30 00000000 d8a66d02 08000000 78cb0702 ......m.....x... │ │ 0x02736d40 00000000 00000000 5c6d7302 00000000 ........\ms..... │ │ 0x02736d50 dcac6d02 00000000 f0ac6d02 08000000 ..m.......m..... │ │ 0x02736d60 aecb0702 00000000 00000000 00000000 ................ │ │ 0x02736d70 00000000 00000000 00000000 00000000 ................ │ │ 0x02736d80 00000000 00000000 00000000 00000000 ................ │ │ @@ -6038,15 +6038,15 @@ │ │ 0x027371c0 00000000 00000000 91326f02 93326f02 .........2o..2o. │ │ 0x027371d0 99326f02 b9326f02 cd326f02 cf326f02 .2o..2o..2o..2o. │ │ 0x027371e0 d3326f02 00000000 00000000 91326f02 .2o..........2o. │ │ 0x027371f0 05336f02 09336f02 29336f02 3d336f02 .3o..3o.)3o.=3o. │ │ 0x02737200 3f336f02 43336f02 00000000 00000000 ?3o.C3o......... │ │ 0x02737210 00000000 00000000 00000000 00000000 ................ │ │ 0x02737220 00000000 00000000 00000000 00000000 ................ │ │ - 0x02737230 00000000 00000000 bde02200 e0882100 .........."...!. │ │ + 0x02737230 00000000 00000000 eae02200 e0882100 .........."...!. │ │ 0x02737240 00000000 c7bf2300 12952400 00000000 ......#...$..... │ │ 0x02737250 00000000 00000000 00000000 00000000 ................ │ │ 0x02737260 00000000 00000000 00000000 00000000 ................ │ │ 0x02737270 00000000 656d6f02 676d6f02 6d6d6f02 ....emo.gmo.mmo. │ │ 0x02737280 8d6d6f02 a56d6f02 a76d6f02 ab6d6f02 .mo..mo..mo..mo. │ │ 0x02737290 00000000 00000000 b76d6f02 b96d6f02 .........mo..mo. │ │ 0x027372a0 bd6d6f02 dd6d6f02 f16d6f02 f36d6f02 .mo..mo..mo..mo. │ ├── readelf --wide --decompress --hex-dump=.data {} │ │ @@ -43,16 +43,16 @@ │ │ 0x02744a10 00000000 ed210f02 e1220f02 01010000 .....!..."...... │ │ 0x02744a20 08000000 00000000 00000000 00000000 ................ │ │ 0x02744a30 00000000 01000000 00000000 00000000 ................ │ │ 0x02744a40 00000000 02000000 ffffffff 00000000 ................ │ │ 0x02744a50 00000000 03000000 fdffffff 01000000 ................ │ │ 0x02744a60 00000000 04000000 faffffff 04000000 ................ │ │ 0x02744a70 ffffffff e8602500 1c000000 2e000000 .....`%......... │ │ - 0x02744a80 c6612300 04452100 7a072300 a9a72300 .a#..E!.z.#...#. │ │ - 0x02744a90 00212100 5c892200 cda82200 00000000 .!!.\."..."..... │ │ + 0x02744a80 f3612300 04452100 a7072300 a9a72300 .a#..E!...#...#. │ │ + 0x02744a90 00212100 89892200 faa82200 00000000 .!!..."..."..... │ │ 0x02744aa0 0000803f 00000000 00000000 00000000 ...?............ │ │ 0x02744ab0 00000000 0000803f 00000000 00000000 .......?........ │ │ 0x02744ac0 00000000 00000000 0000803f 00000000 ...........?.... │ │ 0x02744ad0 00000000 00000000 00000000 0000803f ...............? │ │ 0x02744ae0 0000803f 00000000 00000000 00000000 ...?............ │ │ 0x02744af0 00000000 0000803f 00000000 00000000 .......?........ │ │ 0x02744b00 00000000 00000000 0000803f 00000000 ...........?.... │ │ @@ -988,21 +988,21 @@ │ │ 0x02748520 01000000 00000000 00000000 00000000 ................ │ │ 0x02748530 00000000 01000000 00000000 00000000 ................ │ │ 0x02748540 00000000 00000000 01000000 00000000 ................ │ │ 0x02748550 00000000 00000000 00000000 01000000 ................ │ │ 0x02748560 00000000 00000000 00000000 00000000 ................ │ │ 0x02748570 88130000 02000000 7c000000 fa000000 ........|....... │ │ 0x02748580 7d000000 80000000 01000000 01000000 }............... │ │ - 0x02748590 65662400 16e42400 a4f42100 cdd32200 ef$...$...!...". │ │ - 0x027485a0 2ae42400 56142200 086b2300 9f8e2300 *.$.V."..k#...#. │ │ - 0x027485b0 4ef02300 30772100 954c2300 58b52100 N.#.0w!..L#.X.!. │ │ + 0x02748590 65662400 16e42400 d1f42100 fad32200 ef$...$...!...". │ │ + 0x027485a0 2ae42400 83142200 356b2300 9f8e2300 *.$...".5k#...#. │ │ + 0x027485b0 4ef02300 30772100 c24c2300 85b52100 N.#.0w!..L#...!. │ │ 0x027485c0 a3af2300 5ef02300 30772100 b24f2100 ..#.^.#.0w!..O!. │ │ - 0x027485d0 ae8e2300 20cf2300 1d6b2300 c78a2400 ..#. .#..k#...$. │ │ - 0x027485e0 cc4f2100 29932200 c68e2300 c1752200 .O!.)."...#..u". │ │ - 0x027485f0 2f6b2300 8d002500 42932200 a5002500 /k#...%.B."...%. │ │ + 0x027485d0 ae8e2300 20cf2300 4a6b2300 c78a2400 ..#. .#.Jk#...$. │ │ + 0x027485e0 cc4f2100 56932200 c68e2300 ee752200 .O!.V."...#..u". │ │ + 0x027485f0 5c6b2300 8d002500 6f932200 a5002500 \k#...%.o."...%. │ │ 0x02748600 e08a2400 70f02300 85f02300 01000000 ..$.p.#...#..... │ │ 0x02748610 ffffffff ffffffff 88130000 01000000 ................ │ │ 0x02748620 80000000 01000000 01000000 00000000 ................ │ │ 0x02748630 00000000 00000000 00000000 80000000 ................ │ │ 0x02748640 01000000 01000000 00000000 01000000 ................ │ │ 0x02748650 00000000 00000000 01000000 01000000 ................ │ │ 0x02748660 00000000 00000000 00000000 00000000 ................ │ │ @@ -4718,16 +4718,16 @@ │ │ 0x02756e40 00000000 01000000 00000000 00000000 ................ │ │ 0x02756e50 01000000 00000000 00000000 00000000 ................ │ │ 0x02756e60 00000000 80000000 01000000 00000000 ................ │ │ 0x02756e70 01000000 00000000 00000000 01000000 ................ │ │ 0x02756e80 00000000 00000000 00000000 00000000 ................ │ │ 0x02756e90 01000000 88130000 04000000 03000000 ................ │ │ 0x02756ea0 01000000 00010000 03000000 03000000 ................ │ │ - 0x02756eb0 00010000 02000000 03000000 2e052300 ..............#. │ │ - 0x02756ec0 7beb2300 f1a82100 be882400 a4562200 {.#...!...$..V". │ │ + 0x02756eb0 00010000 02000000 03000000 5b052300 ............[.#. │ │ + 0x02756ec0 7beb2300 f1a82100 be882400 d1562200 {.#...!...$..V". │ │ 0x02756ed0 4c222100 90010000 94fad803 88130000 L"!............. │ │ 0x02756ee0 05000000 02000000 01000000 93650000 .............e.. │ │ 0x02756ef0 801a0600 983a0000 e8030000 dffb0100 .....:.......... │ │ 0x02756f00 01000000 20000000 01000000 02000000 .... ........... │ │ 0x02756f10 01000000 0e000000 03000000 02000000 ................ │ │ 0x02756f20 30303031 30323033 30343035 30363037 0001020304050607 │ │ 0x02756f30 30383039 31303131 31323133 31343135 0809101112131415 │ │ @@ -6439,10 +6439,10 @@ │ │ 0x0275d9d0 64090000 01200000 1f000000 840a0000 d.... .......... │ │ 0x0275d9e0 03200000 1c000000 c6110000 01100000 . .............. │ │ 0x0275d9f0 17000000 a0120000 02200000 a6000000 ......... ...... │ │ 0x0275da00 5e130000 04200000 08000000 0d200000 ^.... ....... .. │ │ 0x0275da10 00200000 09000000 4e200000 05200000 . ......N ... .. │ │ 0x0275da20 02000000 54210000 03100000 06000000 ....T!.......... │ │ 0x0275da30 64210000 06200000 06000000 a4210000 d!... .......!.. │ │ - 0x0275da40 00100000 01000000 04220000 ba802300 ........."....#. │ │ + 0x0275da40 00100000 01000000 04220000 e7802300 ........."....#. │ │ 0x0275da50 04000000 04000000 00000000 e8d00702 ................ ├── lib/x86_64/libcelestia.so │┄ File has been modified after NT_GNU_BUILD_ID has been applied. │ ├── readelf --wide --relocs {} │ │ @@ -22,305 +22,305 @@ │ │ 00000000029b5538 0000000000000008 R_X86_64_RELATIVE 22fa300 │ │ 00000000029b5540 0000000000000008 R_X86_64_RELATIVE 22fa540 │ │ 00000000029b5548 0000000000000008 R_X86_64_RELATIVE 22fa650 │ │ 00000000029b5550 0000000000000008 R_X86_64_RELATIVE 22fa970 │ │ 00000000029b5558 0000000000000008 R_X86_64_RELATIVE 22faa70 │ │ 00000000029b5560 0000000000000008 R_X86_64_RELATIVE 22faad0 │ │ 00000000029b5568 0000000000000008 R_X86_64_RELATIVE 22fab50 │ │ -00000000029b5578 0000000000000008 R_X86_64_RELATIVE 293d0d │ │ +00000000029b5578 0000000000000008 R_X86_64_RELATIVE 293d3a │ │ 00000000029b5588 0000000000000008 R_X86_64_RELATIVE 2addbd │ │ -00000000029b5598 0000000000000008 R_X86_64_RELATIVE 2a5dd6 │ │ -00000000029b55a8 0000000000000008 R_X86_64_RELATIVE 29f929 │ │ +00000000029b5598 0000000000000008 R_X86_64_RELATIVE 2a5e03 │ │ +00000000029b55a8 0000000000000008 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