--- /home/fdroid/fdroiddata/tmp/com.buzbuz.smartautoclicker_52.apk +++ /home/fdroid/fdroiddata/tmp/sigcp_com.buzbuz.smartautoclicker_52.apk ├── /usr/lib/android-sdk/build-tools/debian/apksigner verify --verbose --print-certs {} │┄ error from `/usr/lib/android-sdk/build-tools/debian/apksigner verify --verbose --print-certs {}` (b): │┄ DOES NOT VERIFY │┄ ERROR: APK Signature Scheme v3 signer #1: APK integrity check failed. CHUNKED_SHA256 digest mismatch. Expected: <2ae262fd7cebc50d2d85080769d24568ba72307cfd09653a70f00d47a71ba3db>, actual: <70926476bbd4af23709725c45f989a6f2368c805ffa54f00e665ba7c7b5059de> │┄ ERROR: APK Signature Scheme v3 signer #1: APK integrity check failed. VERITY_CHUNKED_SHA256 digest mismatch. Expected: <710dedfa68a53b96ce4fce9750afddbeb130cfc46cc076124431f143c01782bc2391b50100000000>, actual: <68e32cd444deea63604d1b854a35cd38807bdf3adc1cac837e9dd53529085fd62391b50100000000> │ @@ -1,16 +0,0 @@ │ -Verifies │ -Verified using v1 scheme (JAR signing): false │ -Verified using v2 scheme (APK Signature Scheme v2): true │ -Verified using v3 scheme (APK Signature Scheme v3): true │ -Verified using v4 scheme (APK Signature Scheme v4): false │ -Verified for SourceStamp: false │ -Number of signers: 1 │ -Signer #1 certificate DN: CN=FDroid, OU=FDroid, O=fdroid.org, L=ORG, ST=ORG, C=UK │ -Signer #1 certificate SHA-256 digest: 63fade675304d03c96cff5c6aac351b005ea14f38a666148723b528c60d651db │ -Signer #1 certificate SHA-1 digest: 395607540776de5090ebc53a455624362a40815b │ -Signer #1 certificate MD5 digest: 8fd7b756f50183638d36beb5c420fbc5 │ -Signer #1 key algorithm: RSA │ -Signer #1 key size (bits): 2048 │ -Signer #1 public key SHA-256 digest: 16456b8b90302aa6336fb87875fe97b4c9bab4dc92bd3531c48567e510149885 │ -Signer #1 public key SHA-1 digest: d3344cc243edc51edc6192bc753b0b4c5472ea03 │ -Signer #1 public key MD5 digest: 1b3ad95a251f47c31cc9273575d9cc5a ├── zipinfo {} │ @@ -1,11 +1,11 @@ │ Zip file size: 28680483 bytes, number of entries: 1057 │ -rw-r--r-- 0.0 unx 56 b- defN 81-Jan-01 01:01 META-INF/com/android/build/gradle/app-metadata.properties │ -rw-r--r-- 0.0 unx 120 b- defN 81-Jan-01 01:01 META-INF/version-control-info.textproto │ --rw-r--r-- 0.0 unx 2998 b- stor 81-Jan-01 01:01 assets/dexopt/baseline.prof │ +-rw-r--r-- 0.0 unx 2997 b- stor 81-Jan-01 01:01 assets/dexopt/baseline.prof │ -rw-r--r-- 0.0 unx 339 b- stor 81-Jan-01 01:01 assets/dexopt/baseline.profm │ -rw-r--r-- 0.0 unx 4359180 b- defN 81-Jan-01 01:01 classes.dex │ -rw-r--r-- 0.0 unx 7112 b- stor 81-Jan-01 01:01 lib/arm64-v8a/libdatastore_shared_counter.so │ -rw-r--r-- 0.0 unx 3314792 b- stor 81-Jan-01 01:01 lib/arm64-v8a/libopencv_core.so │ -rw-r--r-- 0.0 unx 2793080 b- stor 81-Jan-01 01:01 lib/arm64-v8a/libopencv_imgproc.so │ -rw-r--r-- 0.0 unx 47000 b- stor 81-Jan-01 01:01 lib/arm64-v8a/libsmartautoclicker.so │ -rw-r--r-- 0.0 unx 4416 b- stor 81-Jan-01 01:01 lib/armeabi-v7a/libdatastore_shared_counter.so │ @@ -1052,8 +1052,8 @@ │ -rw---- 0.0 fat 1172 b- defN 81-Jan-01 01:01 res/zp.xml │ -rw---- 0.0 fat 448 b- defN 81-Jan-01 01:01 res/zp1.xml │ -rw---- 0.0 fat 464 b- defN 81-Jan-01 01:01 res/zq.xml │ -rw---- 0.0 fat 1144172 b- stor 81-Jan-01 01:01 resources.arsc │ -rw---- 2.0 fat 97267 b- defN 81-Jan-01 01:01 META-INF/58A85B83.SF │ -rw---- 2.0 fat 1342 b- defN 81-Jan-01 01:01 META-INF/58A85B83.RSA │ -rw---- 2.0 fat 97140 b- defN 81-Jan-01 01:01 META-INF/MANIFEST.MF │ -1057 files, 31425154 bytes uncompressed, 28415146 bytes compressed: 9.6% │ +1057 files, 31425153 bytes uncompressed, 28415145 bytes compressed: 9.6% ├── assets/dexopt/baseline.prof │ @@ -1,8 +1,8 @@ │ -00000000: 7072 6f00 3031 3000 012f 3300 00a5 0b00 pro.010../3..... │ +00000000: 7072 6f00 3031 3000 012f 3300 00a4 0b00 pro.010../3..... │ 00000010: 0078 01ed 5b0b 7054 e515 3e77 b349 3610 .x..[.pT..>w.I6. │ 00000020: 4802 4905 81e6 06a8 f250 08d8 07d8 486e H.I......P....Hn │ 00000030: 8c44 acbc 54aa d876 6a40 2cb5 2213 0bb5 .D..T..vj@,."... │ 00000040: 8c20 5cc0 22a5 ad0d da02 2dd4 8283 83e3 . \.".....-..... │ 00000050: 380a e350 add6 b238 654a 1d06 432d 831d 8..P...8eJ..C-.. │ 00000060: 79a4 cf30 b503 015b 09f2 d89e 6fef fd36 y..0...[....o..6 │ 00000070: 3f37 bb61 b324 8e76 fcc3 bfe7 fce7 f19d ?7.a.$.v........ │ @@ -97,92 +97,92 @@ │ 00000600: e3f1 99a3 3cb2 f5e6 c8f3 688a e7c0 be00 ....<.....h..... │ 00000610: d193 7b14 4839 0909 b423 e533 2a03 8e25 ..{.H9...#.3*..% │ 00000620: e3b1 80e2 25d4 88f7 875e 8988 de21 1c27 ....%....^...!.' │ 00000630: 1f3b c12b 8e4f a762 81fa 05f7 8c74 4af9 .;.+.O.b.....tJ. │ 00000640: c58c 0ccc 8b99 7648 8f03 83a5 1163 ead8 ......vH.....c.. │ 00000650: 6ca6 4575 33eb 3f1c c3ed 973e 8941 845d l.Eu3.?....>.A.] │ 00000660: e6bd b900 a6fd 9097 aa75 3200 70ce 0e97 .........u2.p... │ -00000670: 68df bd45 91dd 12c9 c0df c51d ca2b 0e99 h..E.........+.. │ -00000680: d4b4 66d0 e8b2 bede fa73 47a4 36cb 4013 ..f......sG.6.@. │ -00000690: 8dc5 66e7 feb6 7263 ca79 751d 9cbe 1d2c ..f...rc.yu...., │ -000006a0: 6efa f689 69d6 8d81 674b d715 f7d5 74f7 n...i...gK....t. │ -000006b0: 68c7 73b0 a4f1 713c edda 942f adf9 fde0 h.s...q<.../.... │ -000006c0: f8fd a78d 263d c100 dd40 ee60 d846 6a8a ....&=...@.`.Fj. │ -000006d0: a716 15e9 29d5 f152 fe52 6943 2c17 b7b6 ....)..R.RiC,... │ -000006e0: 40f1 7767 bd34 1e3f 850b 5ca0 e0f7 3d69 @.wg.4.?..\...=i │ -000006f0: 9605 eb6e 7e40 9ec7 454f 8bfb 50da dbbe ...n~@..EO..P... │ -00000700: 97d8 228b d427 e4e8 8751 74ae 7005 485a .."..'...Qt.p.HZ │ -00000710: f05e f093 f291 1c81 cf57 6393 d54c 6be8 .^.......Wc..Lk. │ -00000720: b3d9 2a15 f73b 8e6d 15ce 4d64 fa9b 1e4f ..*..;.m..Md...O │ -00000730: e5ae 58f6 8be9 7dc2 9f1d 5f9b 907e 78cc ..X...}..._..~x. │ -00000740: 5356 f4bd ac5a 4b6a 1f7b e87d 5da6 62bb SV...ZKj.{.}].b. │ -00000750: b72c aaeb f676 f686 d8c2 e7bd c3e7 3f67 .,...v........?g │ -00000760: bebc f0c8 4b7f 6dd8 f7eb fb72 cff7 a819 ....K.m....r.... │ -00000770: e6cc 5cfd c1fe 1333 7a4e 2f3c 7f09 696e ..\....3zN/<..in │ -00000780: b447 1d2d c41b 1e0d 8a97 2b7e d193 d5b2 .G.-......+~.... │ -00000790: 7dfe ff85 386d 3b92 e2d8 4dfb 8c68 8bd8 }...8m;...M..h.. │ -000007a0: 4912 e48a 771d 5d5b a2fa 95c5 d6df ef6f I...w.][.......o │ -000007b0: 13f9 e623 27b6 0eef 27cb 1ac5 754f d838 ...#'...'...uO.8 │ -000007c0: dfc6 ddfe 4428 f913 3d31 3c4e d7a6 d7d5 ....D(..=1v.*..e..C....k │ -000008b0: 60f3 a082 13bf fce7 f031 d37e 52f6 42ee `........1.~R.B. │ -000008c0: 3e6b fe9b 4dff 2829 bcbe f1aa ac03 2d3b >k..M.()......-; │ -000008d0: 724b eabc d7a6 29b0 20d6 09ea dc42 3cab rK....). ....B<. │ -000008e0: 6e68 0238 ac5f b4c5 b657 b4de ad6c 5f37 nh.8._...W...l_7 │ -000008f0: 84e6 da56 1bc7 17b7 4b92 5cc4 8c39 5157 ...V....K.\..9QW │ -00000900: 03b3 5da0 8e2a cd03 a519 5fe3 ed0b e35e ..]..*...._....^ │ -00000910: 0c4f 5776 48dc a437 f60b 5c7f 7841 2be3 .OWvH..7..\.xA+. │ -00000920: deb8 17c0 746d c34e 0edf 6e5f edf3 25d2 ....tm.N..n_..%. │ -00000930: 98df 1409 cf1a 3dd8 4e01 901c 362e 8db6 ......=.N...6... │ -00000940: 7eb5 48c3 f9c5 a2f5 0d07 97e9 ef1e 1e97 ~.H............. │ -00000950: e881 5467 623b d152 ab1a 63b1 17b3 8e2c ..Tgb;.R..c...., │ -00000960: 792b 655f 1d3b a52a 35aa 935a 15d0 b889 y+e_.;.*5..Z.... │ -00000970: 761f 713b b567 0960 32d1 435d 7671 718b v.q;.g.`2.C]vqq. │ -00000980: 97d7 dd64 be2d 624c b9fa 9dbb 476f cafc ...d.-bL....Go.. │ -00000990: d9e8 f6d4 0de4 e005 ae84 073d fbec 33dd ...........=..3. │ -000009a0: dc04 7207 9897 df29 f857 6c6d 922c fcdd ..r....).Wlm.,.. │ -000009b0: 3941 9a4f 9db9 ab2d e0ca b6a2 5492 8a3d 9A.O...-....T..= │ -000009c0: 4f8f 9103 7e08 e7b5 b4b7 7d1e de14 8e53 O...~.....}....S │ -000009d0: 54cb d60f fd7b c9f8 a77e e879 9a72 3974 T....{...~.y.r9t │ -000009e0: d93c 32f8 2734 d311 585f 96af 7338 68d8 .<2.'4..X_..s8h. │ -000009f0: 9c9e 7f74 0ba4 f15a bb5e 2295 09b0 c339 ...t...Z.^"....9 │ -00000a00: fbb2 aa77 4ebe 3a3f f4f3 81e5 09e9 87c7 ...wN.:?........ │ -00000a10: fcb9 b0f1 b4b5 55a4 7949 6c09 9ed7 853b ......U.yIl....; │ -00000a20: 872c 6ee9 f1ef d0de d8c3 feb1 fac1 b957 .,n............W │ -00000a30: 761c 5ff8 c0d1 a307 b767 c556 0c2a b1b7 v._......g.V.*.. │ -00000a40: 4d38 77ec 6c79 ee55 1175 c8b8 4cad ef3f M8w.ly.U.u..L..? │ -00000a50: fffb def9 102d 6d45 098b dbba e05b c51f .....-mE.....[.. │ -00000a60: 6bce 6e9b 7d8a ed9a f619 d116 b193 24c8 k.n.}.........$. │ -00000a70: b5f5 56d7 49a0 6d60 6af5 4571 a1b8 dbbe ..V.I.m`j.Eq.... │ -00000a80: 2632 ff8d 9643 6b2b a5aa 599c 8696 429c &2...Ck+..Y...B. │ -00000a90: 6f95 efde b4fa b236 2e10 2486 c74e aafe o......6..$..N.. │ -00000aa0: b808 5d4d b499 df8a ec4c b29e 2dee 0ba1 ..]M.....L..-... │ -00000ab0: b952 bbeb bf65 53be 70f9 9f1e 2b90 a3b1 .R...eS.p...+... │ -00000ac0: 53a7 76e9 7db6 cad6 a3e5 7777 29a8 db78 S.v.}.....ww)..x │ -00000ad0: e6c4 e1ca 93f8 0b95 4c8a 3fd6 cfc5 9f38 ........L.?....8 │ -00000ae0: f9b2 3be5 9327 4d70 1fcf f6cd a332 31ba ..;..'Mp.....21. │ -00000af0: 52d6 2566 3480 522b 7392 de1d 0266 6613 R.%f4.R+s....ff. │ -00000b00: ff3d c12c 8ed7 c872 aec1 0374 7ac8 fa8b .=.,...r...tz... │ -00000b10: 3321 fef7 4671 f993 3572 654e 837e 8991 3!..Fq..5reN.~.. │ -00000b20: af14 cbf6 8132 4ba5 8d57 3479 3e39 af57 .....2K..W4y>9.W │ -00000b30: 1b37 bc75 76ed d2aa c297 2dd7 bd4c df43 .7.uv.....-..L.C │ -00000b40: 7a16 97fe e9a4 07e1 3e2d f16f f5b5 d26b z.......>-.o...k │ -00000b50: d1d6 c8da b7dc aa3a fd66 bbe5 58c1 8e55 .......:.f..X..U │ -00000b60: 9b92 bd4b d43b 02cb d438 5315 ea2f 635c ...K.;...8S../c\ │ -00000b70: ca3a 89da 2970 0af1 556e 628e dbf3 f4b1 .:..)p..Unb..... │ -00000b80: 50c5 e7f2 8a5a 563f da32 e554 49ff 616f P....ZV?.2.TI.ao │ -00000b90: d41f 587e 545e 697a ef64 b7c8 a6ba 354b ..X~T^iz.d....5K │ -00000ba0: ef3b 7b64 79cf b1a2 cfc3 768b 4e50 e796 .;{dy.....v.NP.. │ -00000bb0: ff01 ba47 8a30 ...G.0 │ +00000670: 68df bd45 91dd 12c9 c41f 7728 af38 6452 h..E......w(.8dR │ +00000680: d39a 41a3 cbfa 7aeb cf1d 91da 2c03 4d34 ..A...z.....,.M4 │ +00000690: 169b 9dfb dbca 8d29 e7d5 7570 fa76 b0b8 .......)..up.v.. │ +000006a0: e9db 27a6 5937 069e 2d5d 57dc 57d3 dda3 ..'.Y7..-]W.W... │ +000006b0: 1dcf c192 c6c7 f1b4 6b53 beb4 e6f7 83e3 ........kS...... │ +000006c0: f79f 369a f404 0374 03b9 8361 1ba9 299e ..6....t...a..). │ +000006d0: 5a54 a4a7 54c7 4bf9 4ba5 0db1 5cdc da02 ZT..T.K.K...\... │ +000006e0: c5df 9df5 d278 fc14 2e70 8182 dff7 a459 .....x...p.....Y │ +000006f0: 16ac bbf9 0179 1e17 3d2d ee43 696f fb5e .....y..=-.Cio.^ │ +00000700: 628b 2c52 9f90 a31f 46d1 b9c2 1520 69c1 b.,R....F.... i. │ +00000710: 7bc1 4fca 4772 043e 5f8d 4d56 33ad a1cf {.O.Gr.>_.MV3... │ +00000720: 66ab 54dc ef38 b655 3837 91e9 6f7a 3c95 f.T..8.U87..oz<. │ +00000730: bb62 d92f a6f7 097f 767c 6d42 fae1 314f .b./....v|mB..1O │ +00000740: 59d1 f7b2 6a2d a97d eca1 f775 998a edde Y...j-.}...u.... │ +00000750: b2a8 aedb dbd9 1b62 0b9f f70e 9fff 9cf9 .......b........ │ +00000760: f2c2 232f fdb5 61df afef cb3d dfa3 6698 ..#/..a....=..f. │ +00000770: 3373 f507 fb4f cce8 39bd f0fc 25a4 b9d1 3s...O..9...%... │ +00000780: 1e75 b410 6f78 3428 5eae f845 4f56 cbf6 .u..ox4(^..EOV.. │ +00000790: f9ff 17e2 b4ed 488a 6337 ed33 a22d 6227 ......H.c7.3.-b' │ +000007a0: 4990 2bde 7574 6d89 ea57 165b 7fbf bf4d I.+.utm..W.[...M │ +000007b0: e49b 8f9c d83a bc9f 2c6b 14d7 3d61 e37c .....:..,k..=a.| │ +000007c0: 1b77 fb13 a1e4 4ff4 c4f0 385d 9b5e 57a3 .w....O...8].^W. │ +000007d0: eb33 a4b6 f5ea 9c41 b4bd fa07 0cd9 0725 .3.....A.......% │ +000007e0: baea ddea 27e7 163f d3b7 401a 7e3c e9f8 ....'..?..@.~<.. │ +000007f0: 0ff4 25cd 3267 b1c8 caf8 836b e781 bfbd ..%.2g.....k.... │ +00000800: 56f9 f7ea 0ce0 e1e2 8ff5 747c 91d5 bf78 V.........t|...x │ +00000810: a88f 53f0 1916 1fcf f1dd 5d2b e216 59e5 ..S.......]+..Y. │ +00000820: a9ae 3751 791b 6ff1 3b52 7e15 3076 bd76 ..7Qy.o.;R~.0v.v │ +00000830: 8efb 0d5b b9ad e1d0 eb4b ebe5 7a4f 2852 ...[.....K..zO(R │ +00000840: f123 999c bfd1 1247 360f 9181 e365 b72a .#.....G6....e.* │ +00000850: a293 f67a 4ff7 fc47 1e35 6e78 e555 d1d0 ...zO..G.5nx.U.. │ +00000860: 72bb 4ebf 5d8d 741d bf1b 84c9 9cba 69ba r.N.].t.......i. │ +00000870: de6c 0d81 6554 06b7 d416 8dd8 622d afd5 .l..eT......b-.. │ +00000880: 0373 caa1 d2c5 25d5 e7bc 6ca1 4e14 e360 .s....%...l.N..` │ +00000890: d918 172e 0b8f 913a 4962 9970 c980 7152 .......:Ib.p..qR │ +000008a0: f8d8 e5aa 5817 9601 270f 652f f856 af81 ....X...'.e/.V.. │ +000008b0: cd83 0a4e fcf2 9fc3 c74c fb49 d90b b9fb ...N.....L.I.... │ +000008c0: acf9 6f36 fda3 a4f0 fac6 abb2 0eb4 ecc8 ..o6............ │ +000008d0: 2da9 f35e 9ba6 c082 5827 a873 0bf1 acba -..^....X'.s.... │ +000008e0: a109 e0b0 7ed1 16db 5ed1 7ab7 b27d dd10 ....~...^.z..}.. │ +000008f0: 9a6b 5b6d 1c5f dc2e 4972 1133 e644 5d0d .k[m._..Ir.3.D]. │ +00000900: cc76 813a aa34 0f94 667c 8db7 2f8c 7b31 .v.:.4..f|../.{1 │ +00000910: 3c5d d921 7193 ded8 2f70 fde1 05ad 8c7b <].!q.../p.....{ │ +00000920: e35e 00d3 b50d 3b39 7cbb 7db5 cf97 4863 .^....;9|.}...Hc │ +00000930: 7e53 243c 6bf4 603b 0540 72d8 b834 dafa ~S$u....+..RI*.< │ +000009c0: 3d46 0ef8 219c d7d2 def6 7978 5338 4e51 =F..!.....yxS8NQ │ +000009d0: 2d5b 3ff4 ef25 e39f faa1 e769 cae5 d065 -[?..%.....i...e │ +000009e0: f3c8 e09f d04c 4760 7d59 bece e1a0 6173 .....LG`}Y....as │ +000009f0: 7afe d12d 90c6 6bed 7a89 5426 c00e e7ec z..-..k.z.T&.... │ +00000a00: cbaa de39 f9ea fcd0 cf07 9627 a41f 1ef3 ...9.......'.... │ +00000a10: e7c2 c6d3 d656 91e6 25b1 2578 5e17 ee1c .....V..%.%x^... │ +00000a20: b2b8 a5c7 bf43 7b63 0ffb c7ea 07e7 5ed9 .....C{c......^. │ +00000a30: 717c e103 478f 1edc 9e15 5b31 a8c4 de36 q|..G.....[1...6 │ +00000a40: e1dc b1b3 e5b9 5745 d421 e332 b5be fffc ......WE.!.2.... │ +00000a50: ef7b e743 b4b4 1525 2c6e eb82 6f15 7fac .{.C...%,n..o... │ +00000a60: 39bb 6df6 29b6 6bda 6744 5bc4 4e92 20d7 9.m.).k.gD[.N. . │ +00000a70: d65b 5d27 81b6 81a9 d517 c585 e26e fb9a .[]'.........n.. │ +00000a80: c8fc 375a 0ead ad94 aa66 711a 5a0a 71be ..7Z.....fq.Z.q. │ +00000a90: 55be 7bd3 eacb dab8 4090 181e 3ba9 fae3 U.{.....@...;... │ +00000aa0: 2274 35d1 667e 2bb2 33c9 7ab6 b82f 84e6 "t5.f~+.3.z../.. │ +00000ab0: 4aed aeff 964d f9c2 e57f 7aac 408e c64e J....M....z.@..N │ +00000ac0: 9dda a5f7 d92a 5b8f 96df dda5 a06e e399 .....*[......n.. │ +00000ad0: 1387 2b4f e22f 5432 29fe 583f 177f e2e4 ..+O./T2).X?.... │ +00000ae0: cbee 944f 9e34 c17d 3cdb 378f cac4 e84a ...O.4.}<.7....J │ +00000af0: 5997 98d1 004a adcc 497a 7708 9899 4dfc Y....J..Izw...M. │ +00000b00: f704 b338 5e23 cbb9 060f d0e9 21eb 2fce ...8^#......!./. │ +00000b10: 84f8 df1b c5e5 4fd6 c895 390d fa25 46be ......O...9..%F. │ +00000b20: 522c db07 ca2c 9536 5ed1 e4f9 e4bc 5e6d R,...,.6^.....^m │ +00000b30: dcf0 d6d9 b54b ab0a 5fb6 5cf7 327d 0fe9 .....K.._.\.2}.. │ +00000b40: 595c faa7 931e 84fb b4c4 bfd5 d74a af45 Y\...........J.E │ +00000b50: 5b23 6bdf 72ab eaf4 9bed 9663 053b 566d [#k.r......c.;Vm │ +00000b60: 4af6 2e51 ef08 2c53 e34c 55a8 bf8c 7129 J..Q..,S.LU...q) │ +00000b70: eb24 6aa7 c029 c457 b989 396e cfd3 c742 .$j..).W..9n...B │ +00000b80: 159f cb2b 6a59 fd68 cb94 5325 fd87 bd51 ...+jY.h..S%...Q │ +00000b90: 7f60 f951 79a5 e9bd 93dd 229b ead6 2cbd .`.Qy....."...,. │ +00000ba0: efec 91e5 3dc7 8a3e 0fdb 2d3a 419d 5bfe ....=..>..-:A.[. │ +00000bb0: 0721 0489 b0 .!... ├── lib/armeabi-v7a/libopencv_core.so │ ├── readelf --wide --notes {} │ │ @@ -1,8 +1,8 @@ │ │ │ │ Displaying notes found in: .note.android.ident │ │ Owner Data size Description │ │ Android 0x00000084 NT_VERSION (version) description data: 18 00 00 00 72 32 36 62 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 31 30 39 30 39 31 32 35 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 │ │ │ │ Displaying notes found in: .note.gnu.build-id │ │ Owner Data size Description │ │ - GNU 0x00000014 NT_GNU_BUILD_ID (unique build ID bitstring) Build ID: b77c9eb1f1110aac45e9f978070e7a598ba59b9d │ │ + GNU 0x00000014 NT_GNU_BUILD_ID (unique build ID bitstring) Build ID: 272bac300501470779a780defcabed17a9b7189a │ ├── strings --all --bytes=8 {} │ │ @@ -4513,14 +4513,79 @@ │ │ /sys/fs/cgroup/cpuset/cpuset.cpus │ │ core(parallel): using backend: │ │ Unknown type identifier: '%c' in '%s' │ │ The closing '%c' does not match the opening '%c' │ │ k < dims │ │ void cv::randShuffle(InputOutputArray, double, RNG *) │ │ OPENCV_DUMP_ERRORS │ │ +General configuration for OpenCV 4.9.0 ===================================== │ │ + Version control: 3.0.5-dirty │ │ + Platform: │ │ + Timestamp: 2024-12-14T10:27:37Z │ │ + Host: Linux 6.1.0-28-amd64 x86_64 │ │ + Target: Android 1 armv7-a │ │ + CMake: 3.22.1-g37088a8 │ │ + CMake generator: Ninja │ │ + CMake build tool: /opt/android-sdk/cmake/3.22.1/bin/ninja │ │ + Configuration: Release │ │ + CPU/HW features: │ │ + Baseline: NEON │ │ + requested: DETECT │ │ + disabled: ON SSE SSE2 │ │ + C/C++: │ │ + Built as dynamic libs?: YES │ │ + C++ standard: 11 │ │ + C++ Compiler: /opt/android-sdk/ndk/26.1.10909125/toolchains/llvm/prebuilt/linux-x86_64/bin/clang++ (ver 17.0.2) │ │ + C++ flags (Release): -g -DANDROID -fdata-sections -ffunction-sections -funwind-tables -fstack-protector-strong -no-canonical-prefixes -D_FORTIFY_SOURCE=2 -march=armv7-a -mthumb -Wformat -Werror=format-security -Wl,--build-id -fsigned-char -W -Wall -Wreturn-type -Wnon-virtual-dtor -Waddress -Wsequence-point -Wformat -Wformat-security -Wmissing-declarations -Wmissing-prototypes -Wstrict-prototypes -Wundef -Winit-self -Wpointer-arith -Wshadow -Wsign-promo -Wuninitialized -Winconsistent-missing-override -Wno-delete-non-virtual-dtor -Wno-unnamed-type-template-args -Wno-comment -Wno-deprecated-enum-enum-conversion -Wno-deprecated-anon-enum-enum-conversion -fdiagnostics-show-option -Qunused-arguments -ffunction-sections -fdata-sections -fvisibility=hidden -fvisibility-inlines-hidden -O3 -DNDEBUG -DNDEBUG │ │ + C++ flags (Debug): -g -DANDROID -fdata-sections -ffunction-sections -funwind-tables -fstack-protector-strong -no-canonical-prefixes -D_FORTIFY_SOURCE=2 -march=armv7-a -mthumb -Wformat -Werror=format-security -Wl,--build-id -fsigned-char -W -Wall -Wreturn-type -Wnon-virtual-dtor -Waddress -Wsequence-point -Wformat -Wformat-security -Wmissing-declarations -Wmissing-prototypes -Wstrict-prototypes -Wundef -Winit-self -Wpointer-arith -Wshadow -Wsign-promo -Wuninitialized -Winconsistent-missing-override -Wno-delete-non-virtual-dtor -Wno-unnamed-type-template-args -Wno-comment -Wno-deprecated-enum-enum-conversion -Wno-deprecated-anon-enum-enum-conversion -fdiagnostics-show-option -Qunused-arguments -ffunction-sections -fdata-sections -fvisibility=hidden -fvisibility-inlines-hidden -fno-limit-debug-info -O0 -DDEBUG -D_DEBUG │ │ + C Compiler: /opt/android-sdk/ndk/26.1.10909125/toolchains/llvm/prebuilt/linux-x86_64/bin/clang │ │ + C flags (Release): -g -DANDROID -fdata-sections -ffunction-sections -funwind-tables -fstack-protector-strong -no-canonical-prefixes -D_FORTIFY_SOURCE=2 -march=armv7-a -mthumb -Wformat -Werror=format-security -fsigned-char -W -Wall -Wreturn-type -Wnon-virtual-dtor -Waddress -Wsequence-point -Wformat -Wformat-security -Wmissing-declarations -Wmissing-prototypes -Wstrict-prototypes -Wundef -Winit-self -Wpointer-arith -Wshadow -Wsign-promo -Wuninitialized -Winconsistent-missing-override -Wno-delete-non-virtual-dtor -Wno-unnamed-type-template-args -Wno-comment -Wno-deprecated-enum-enum-conversion -Wno-deprecated-anon-enum-enum-conversion -fdiagnostics-show-option -Qunused-arguments -ffunction-sections -fdata-sections -fvisibility=hidden -fvisibility-inlines-hidden -O3 -DNDEBUG -DNDEBUG │ │ + C flags (Debug): -g -DANDROID -fdata-sections -ffunction-sections -funwind-tables -fstack-protector-strong -no-canonical-prefixes -D_FORTIFY_SOURCE=2 -march=armv7-a -mthumb -Wformat -Werror=format-security -fsigned-char -W -Wall -Wreturn-type -Wnon-virtual-dtor -Waddress -Wsequence-point -Wformat -Wformat-security -Wmissing-declarations -Wmissing-prototypes -Wstrict-prototypes -Wundef -Winit-self -Wpointer-arith -Wshadow -Wsign-promo -Wuninitialized -Winconsistent-missing-override -Wno-delete-non-virtual-dtor -Wno-unnamed-type-template-args -Wno-comment -Wno-deprecated-enum-enum-conversion -Wno-deprecated-anon-enum-enum-conversion -fdiagnostics-show-option -Qunused-arguments -ffunction-sections -fdata-sections -fvisibility=hidden -fvisibility-inlines-hidden -fno-limit-debug-info -O0 -DDEBUG -D_DEBUG │ │ + Linker flags (Release): -static-libstdc++ -Wl,--build-id=sha1 -Wl,--no-rosegment -Wl,--no-undefined-version -Wl,--fatal-warnings -Wl,--no-undefined -Qunused-arguments -Wl,--gc-sections -Wl,--as-needed -Wl,--no-undefined -Wl,--gc-sections │ │ + Linker flags (Debug): -static-libstdc++ -Wl,--build-id=sha1 -Wl,--no-rosegment -Wl,--no-undefined-version -Wl,--fatal-warnings -Wl,--no-undefined -Qunused-arguments -Wl,--gc-sections -Wl,--as-needed -Wl,--no-undefined │ │ + ccache: NO │ │ + Precompiled headers: NO │ │ + Extra dependencies: dl m log │ │ + 3rdparty dependencies: │ │ + OpenCV modules: │ │ + To be built: core imgproc │ │ + Disabled: world │ │ + Disabled by dependency: calib3d dnn features2d flann gapi highgui imgcodecs java_bindings_generator js_bindings_generator ml objc_bindings_generator objdetect photo stitching video videoio │ │ + Unavailable: java python2 python3 ts │ │ + Applications: - │ │ + Documentation: NO │ │ + Non-free algorithms: NO │ │ + Android NDK: /opt/android-sdk/ndk/26.1.10909125 (ver 26.1.10909125) │ │ + Android ABI: armeabi-v7a │ │ + NDK toolchain: arm-linux-androideabi-clang │ │ + STL type: c++_static │ │ + Native API level: 24 │ │ + Android SDK: not used, projects are not built │ │ + Media I/O: │ │ + ZLib: z (ver 1.2.13) │ │ + JPEG: build-libjpeg-turbo (ver 2.1.3-62) │ │ + SIMD Support Request: NO │ │ + PNG: build (ver 1.6.37) │ │ + TIFF: build (ver 42 - 4.2.0) │ │ + JPEG 2000: build (ver 2.5.0) │ │ + HDR: YES │ │ + SUNRASTER: YES │ │ + PXM: YES │ │ + PFM: YES │ │ + Video I/O: │ │ + MEDIANDK: YES │ │ + NDK Camera: YES │ │ + Parallel framework: none │ │ + Trace: YES (built-in) │ │ + Other third-party libraries: │ │ + Custom HAL: NO │ │ + Flatbuffers: builtin/3rdparty (23.5.9) │ │ + Python (for build): /usr/bin/python3 │ │ + Install to: /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/.cxx/Release/t1f4h131/armeabi-v7a/install │ │ +----------------------------------------------------------------- │ │ Input image depth is not supported by function │ │ Parsing error │ │ OPENCV: Trying to disable baseline CPU feature: '%s'.This has very limited effect, because code optimizations for this feature are executed unconditionally in the most cases. │ │ OPENCV_TRACE_MAX_CHILDREN_OPENCV │ │ static void cv::KeyPoint::convert(const std::vector &, std::vector &, float, float, int, int) │ │ findDataFile │ │ WARNINGS │ │ @@ -5177,79 +5242,14 @@ │ │ decodeFormat │ │ NULL or empty filename │ │ startNextStream │ │ make_base64_header │ │ ']' - right-brace of seq is missing │ │ nelems == m.total()*m.channels() │ │ Directive tags are not allowed here │ │ -General configuration for OpenCV 4.9.0 ===================================== │ │ - Version control: 3.0.5-dirty │ │ - Platform: │ │ - Timestamp: 2024-10-16T01:58:13Z │ │ - Host: Linux 6.1.0-25-amd64 x86_64 │ │ - Target: Android 1 armv7-a │ │ - CMake: 3.22.1-g37088a8 │ │ - CMake generator: Ninja │ │ - CMake build tool: /opt/android-sdk/cmake/3.22.1/bin/ninja │ │ - Configuration: Release │ │ - CPU/HW features: │ │ - Baseline: NEON │ │ - requested: DETECT │ │ - disabled: ON SSE SSE2 │ │ - C/C++: │ │ - Built as dynamic libs?: YES │ │ - C++ standard: 11 │ │ - C++ Compiler: /opt/android-sdk/ndk/26.1.10909125/toolchains/llvm/prebuilt/linux-x86_64/bin/clang++ (ver 17.0.2) │ │ - C++ flags (Release): -g -DANDROID -fdata-sections -ffunction-sections -funwind-tables -fstack-protector-strong -no-canonical-prefixes -D_FORTIFY_SOURCE=2 -march=armv7-a -mthumb -Wformat -Werror=format-security -Wl,--build-id -fsigned-char -W -Wall -Wreturn-type -Wnon-virtual-dtor -Waddress -Wsequence-point -Wformat -Wformat-security -Wmissing-declarations -Wmissing-prototypes -Wstrict-prototypes -Wundef -Winit-self -Wpointer-arith -Wshadow -Wsign-promo -Wuninitialized -Winconsistent-missing-override -Wno-delete-non-virtual-dtor -Wno-unnamed-type-template-args -Wno-comment -Wno-deprecated-enum-enum-conversion -Wno-deprecated-anon-enum-enum-conversion -fdiagnostics-show-option -Qunused-arguments -ffunction-sections -fdata-sections -fvisibility=hidden -fvisibility-inlines-hidden -O3 -DNDEBUG -DNDEBUG │ │ - C++ flags (Debug): -g -DANDROID -fdata-sections -ffunction-sections -funwind-tables -fstack-protector-strong -no-canonical-prefixes -D_FORTIFY_SOURCE=2 -march=armv7-a -mthumb -Wformat -Werror=format-security -Wl,--build-id -fsigned-char -W -Wall -Wreturn-type -Wnon-virtual-dtor -Waddress -Wsequence-point -Wformat -Wformat-security -Wmissing-declarations -Wmissing-prototypes -Wstrict-prototypes -Wundef -Winit-self -Wpointer-arith -Wshadow -Wsign-promo -Wuninitialized -Winconsistent-missing-override -Wno-delete-non-virtual-dtor -Wno-unnamed-type-template-args -Wno-comment -Wno-deprecated-enum-enum-conversion -Wno-deprecated-anon-enum-enum-conversion -fdiagnostics-show-option -Qunused-arguments -ffunction-sections -fdata-sections -fvisibility=hidden -fvisibility-inlines-hidden -fno-limit-debug-info -O0 -DDEBUG -D_DEBUG │ │ - C Compiler: /opt/android-sdk/ndk/26.1.10909125/toolchains/llvm/prebuilt/linux-x86_64/bin/clang │ │ - C flags (Release): -g -DANDROID -fdata-sections -ffunction-sections -funwind-tables -fstack-protector-strong -no-canonical-prefixes -D_FORTIFY_SOURCE=2 -march=armv7-a -mthumb -Wformat -Werror=format-security -fsigned-char -W -Wall -Wreturn-type -Wnon-virtual-dtor -Waddress -Wsequence-point -Wformat -Wformat-security -Wmissing-declarations -Wmissing-prototypes -Wstrict-prototypes -Wundef -Winit-self -Wpointer-arith -Wshadow -Wsign-promo -Wuninitialized -Winconsistent-missing-override -Wno-delete-non-virtual-dtor -Wno-unnamed-type-template-args -Wno-comment -Wno-deprecated-enum-enum-conversion -Wno-deprecated-anon-enum-enum-conversion -fdiagnostics-show-option -Qunused-arguments -ffunction-sections -fdata-sections -fvisibility=hidden -fvisibility-inlines-hidden -O3 -DNDEBUG -DNDEBUG │ │ - C flags (Debug): -g -DANDROID -fdata-sections -ffunction-sections -funwind-tables -fstack-protector-strong -no-canonical-prefixes -D_FORTIFY_SOURCE=2 -march=armv7-a -mthumb -Wformat -Werror=format-security -fsigned-char -W -Wall -Wreturn-type -Wnon-virtual-dtor -Waddress -Wsequence-point -Wformat -Wformat-security -Wmissing-declarations -Wmissing-prototypes -Wstrict-prototypes -Wundef -Winit-self -Wpointer-arith -Wshadow -Wsign-promo -Wuninitialized -Winconsistent-missing-override -Wno-delete-non-virtual-dtor -Wno-unnamed-type-template-args -Wno-comment -Wno-deprecated-enum-enum-conversion -Wno-deprecated-anon-enum-enum-conversion -fdiagnostics-show-option -Qunused-arguments -ffunction-sections -fdata-sections -fvisibility=hidden -fvisibility-inlines-hidden -fno-limit-debug-info -O0 -DDEBUG -D_DEBUG │ │ - Linker flags (Release): -static-libstdc++ -Wl,--build-id=sha1 -Wl,--no-rosegment -Wl,--no-undefined-version -Wl,--fatal-warnings -Wl,--no-undefined -Qunused-arguments -Wl,--gc-sections -Wl,--as-needed -Wl,--no-undefined -Wl,--gc-sections │ │ - Linker flags (Debug): -static-libstdc++ -Wl,--build-id=sha1 -Wl,--no-rosegment -Wl,--no-undefined-version -Wl,--fatal-warnings -Wl,--no-undefined -Qunused-arguments -Wl,--gc-sections -Wl,--as-needed -Wl,--no-undefined │ │ - ccache: NO │ │ - Precompiled headers: NO │ │ - Extra dependencies: dl m log │ │ - 3rdparty dependencies: │ │ - OpenCV modules: │ │ - To be built: core imgproc │ │ - Disabled: world │ │ - Disabled by dependency: calib3d dnn features2d flann gapi highgui imgcodecs java_bindings_generator js_bindings_generator ml objc_bindings_generator objdetect photo stitching video videoio │ │ - Unavailable: java python2 python3 ts │ │ - Applications: - │ │ - Documentation: NO │ │ - Non-free algorithms: NO │ │ - Android NDK: /opt/android-sdk/ndk/26.1.10909125 (ver 26.1.10909125) │ │ - Android ABI: armeabi-v7a │ │ - NDK toolchain: arm-linux-androideabi-clang │ │ - STL type: c++_static │ │ - Native API level: 24 │ │ - Android SDK: not used, projects are not built │ │ - Media I/O: │ │ - ZLib: z (ver 1.2.13) │ │ - JPEG: build-libjpeg-turbo (ver 2.1.3-62) │ │ - SIMD Support Request: NO │ │ - PNG: build (ver 1.6.37) │ │ - TIFF: build (ver 42 - 4.2.0) │ │ - JPEG 2000: build (ver 2.5.0) │ │ - HDR: YES │ │ - SUNRASTER: YES │ │ - PXM: YES │ │ - PFM: YES │ │ - Video I/O: │ │ - MEDIANDK: YES │ │ - NDK Camera: YES │ │ - Parallel framework: none │ │ - Trace: YES (built-in) │ │ - Other third-party libraries: │ │ - Custom HAL: NO │ │ - Flatbuffers: builtin/3rdparty (23.5.9) │ │ - Python (for build): /usr/bin/python3 │ │ - Install to: /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/.cxx/Release/t1f4h131/armeabi-v7a/install │ │ ------------------------------------------------------------------ │ │ OPENCV_DUMP_CONFIG │ │ Required baseline features: │ │ AVX512BW │ │ AVX512VBMI │ │ Unknown feature │ │ cv::error() │ │ Region location is disabled. Bailout │ ├── readelf --wide --decompress --string-dump=.rodata {} │ │ @@ -636,836 +636,19 @@ │ │ [ 632f] core(parallel): using backend: │ │ [ 634f] Unknown type identifier: '%c' in '%s' │ │ [ 6375] puts │ │ [ 637a] The closing '%c' does not match the opening '%c' │ │ [ 63ab] k < dims │ │ [ 63b4] void cv::randShuffle(InputOutputArray, double, RNG *) │ │ [ 63ea] OPENCV_DUMP_ERRORS │ │ - [ 63fd] Input image depth is not supported by function │ │ - [ 642c] Parsing error │ │ - [ 643a] OPENCV: Trying to disable baseline CPU feature: '%s'.This has very limited effect, because code optimizations for this feature are executed unconditionally in the most cases.\n │ │ - [ 64ea] OPENCV_TRACE_MAX_CHILDREN_OPENCV │ │ - [ 650b] convert │ │ - [ 6513] static void cv::KeyPoint::convert(const std::vector &, std::vector &, float, float, int, int) │ │ - [ 6584] findDataFile │ │ - [ 6591] WARNINGS │ │ - [ 659a] collate_byname::collate_byname failed to construct for │ │ - [ 65d8] codecvt_byname::codecvt_byname failed to construct for │ │ - [ 662a] %a │ │ - [ 662d] guard variable for │ │ - [ 6641] so │ │ - [ 6644] __uuidof │ │ - [ 664d] decimal32 │ │ - [ 6657] complex │ │ - [ 6660] actions & (_UA_SEARCH_PHASE | _UA_HANDLER_FRAME | _UA_FORCE_UNWIND) │ │ - [ 66a4] d26 │ │ - [ 66a8] cvtFn │ │ - [ 66ae] cvOrS │ │ - [ 66b4] psrc1->sameSize(*psrc2) && type1 == type2 │ │ - [ 66de] void cv::hal::cpu_baseline::max32s(const int *, size_t, const int *, size_t, int *, size_t, int, int) │ │ - [ 6744] void cv::hal::cpu_baseline::absdiff8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, int, int) │ │ - [ 67b3] void cv::hal::cpu_baseline::absdiff64f(const double *, size_t, const double *, size_t, double *, size_t, int, int) │ │ - [ 6826] void cv::hal::cpu_baseline::mul8s(const schar *, size_t, const schar *, size_t, schar *, size_t, int, int, const double *) │ │ - [ 68a1] void cv::hal::sub8s(const schar *, size_t, const schar *, size_t, schar *, size_t, int, int, void *) │ │ - [ 6906] void cv::hal::min64f(const double *, size_t, const double *, size_t, double *, size_t, int, int, void *) │ │ - [ 696f] void cv::hal::max64f(const double *, size_t, const double *, size_t, double *, size_t, int, int, void *) │ │ - [ 69d8] void cv::hal::xor8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, int, int, void *) │ │ - [ 6a3d] void cv::hal::mul8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, int, int, void *) │ │ - [ 6aa2] cmpop == CMP_NE │ │ - [ 6ab2] cvInitMatHeader │ │ - [ 6ac2] Iterator pointer is NULL │ │ - [ 6adb] cvSetData │ │ - [ 6ae5] cvPtr3D │ │ - [ 6aed] cvSet1D │ │ - [ 6af5] cvSet2D │ │ - [ 6afd] cvCheckTermCriteria │ │ - [ 6b11] kind=0x%08llx │ │ - [ 6b20] oneBuf == NULL │ │ - [ 6b2f] < │ │ - [ 6b31] dst.size() == src.size() && dst.type() == CV_MAKETYPE(lut.depth(), src.channels()) │ │ - [ 6b84] cvNormalize │ │ - [ 6b90] mask.depth() == CV_8U && (mcn == 1 || mcn == cn) │ │ - [ 6bc1] Effectively2D(*this) │ │ - [ 6bd6] ptr + elem_size <= seq->block_max │ │ - [ 6bf8] cvSeqPushMulti │ │ - [ 6c07] cvSeqPartition │ │ - [ 6c16] cvGraphAddVtx │ │ - [ 6c24] icvGrowSeq │ │ - [ 6c2f] convertToD3D10Texture2D │ │ - [ 6c47] elem_size == sizeof(Complex) │ │ - [ 6c6b] glob_rec │ │ - [ 6c74] OPENCV_KMEANS_PARALLEL_GRANULARITY │ │ - [ 6c97] virtual void cv::KMeansDistanceComputer::operator()(const Range &) const [onlyDistance = false] │ │ - [ 6cfe] double cv::determinant(InputArray) │ │ - [ 6d21] method == DECOMP_LU || method == DECOMP_CHOLESKY │ │ - [ 6d52] solve │ │ - [ 6d58] void cv::SVBackSubst(InputArray, InputArray, InputArray, InputArray, OutputArray) │ │ - [ 6daa] cvSVD │ │ - [ 6db0] cvSVBkSb │ │ - [ 6db9] void cv::hal::cpu_baseline::sqrt32f(const float *, float *, int) │ │ - [ 6dfa] void cv::hal::sqrt64f(const double *, double *, int) │ │ - [ 6e2f] void cv::hal::exp32f(const float *, float *, int) │ │ - [ 6e61] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/matmul.simd.hpp │ │ - [ 6eda] void cv::cpu_baseline::gemm32fc(const float *, size_t, const float *, size_t, float, const float *, size_t, float, float *, size_t, int, int, int, int) │ │ - [ 6f72] calcCovarMatrix │ │ - [ 6f82] nsamples > 0 │ │ - [ 6f8f] The total matrix size does not fit to "size_t" type │ │ - [ 6fc3] resize │ │ - [ 6fca] d.cols == 1 || d.rows == 1 │ │ - [ 6fe5] m2.dims │ │ - [ 6fed] cvarrToMat │ │ - [ 6ff8] virtual void cv::MatOp::multiply(const MatExpr &, double, MatExpr &) const │ │ - [ 7043] MatExpr cv::min(const Mat &, double) │ │ - [ 7068] vconcat │ │ - [ 7070] trace │ │ - [ 7076] void cv::reduce(InputArray, OutputArray, int, int, int) │ │ - [ 70ae] _sizes && 0 < d && d <= CV_MAX_DIM │ │ - [ 70d1] transposeND │ │ - [ 70dd] type │ │ - [ 70e2] i >= 0 && i < (int)vv.size() │ │ - [ 70ff] !fixedType() || ((cuda::GpuMat*)obj)->type() == mtype │ │ - [ 7135] move │ │ - [ 713a] mask.empty() || mask.type() == CV_8U │ │ - [ 715f] void cv::hal::merge16u(const ushort **, ushort *, int, int) │ │ - [ 719b] void cv::minMaxLoc(InputArray, double *, double *, Point *, Point *, InputArray) │ │ - [ 71ec] core(parallel): Updated backends priorities: │ │ - [ 721a] backend: Unknown C++ exception │ │ - [ 723a] backend: │ │ - [ 7245] initPluginAPI │ │ - [ 7253] core(parallel): initialized ' │ │ - [ 7271] read │ │ - [ 7276] open │ │ - [ 727b] parseBase64 │ │ - [ 7287] %s(%d): %s │ │ - [ 7292] blockIdx < fs_data_ptrs.size() │ │ - [ 72b1] Invalid fs.state │ │ - [ 72c2] Invalid character in the stream │ │ - [ 72e2] n.isInt() │ │ - [ 72ec] The YAML streams must start with '---', except the first one │ │ - [ 7329] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/system.cpp │ │ - [ 739d] Bad parameter of type CvPoint │ │ - [ 73bb] AVX512VL │ │ - [ 73c4] FALSE │ │ - [ 73ca] _HINT= │ │ - [ 73d1] => result: │ │ - [ 73df] findFile │ │ - [ 73e8] idivt │ │ - [ 73ee] %A │ │ - [ 73f1] thread-local wrapper routine for │ │ - [ 7413] tl │ │ - [ 7416] operator- │ │ - [ 7420] operator!= │ │ - [ 742b] const __shim_type_info *__cxxabiv1::get_shim_type_info(uint64_t, const uint8_t *, uint8_t, bool, _Unwind_Control_Block *, uintptr_t) │ │ - [ 74b0] s4 │ │ - [ 74b3] unknown register │ │ - [ 74c4] void cv::hal::cpu_baseline::addWeighted8s(const schar *, size_t, const schar *, size_t, schar *, size_t, int, int, const double *) │ │ - [ 7547] void cv::hal::cmp16u(const ushort *, size_t, const ushort *, size_t, uchar *, size_t, int, int, void *) │ │ - [ 75af] The array is too big │ │ - [ 75c4] cvReleaseSparseMat │ │ - [ 75d7] cvCloneSparseMat │ │ - [ 75e8] cvPtr2D │ │ - [ 75f0] The total matrix width is not divisible by the new number of columns │ │ - [ 7635] icvGetNodePtr │ │ - [ 7643] Associated AsyncArray has been destroyed │ │ - [ 766c] , w= │ │ - [ 7671] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/buffer_area.cpp │ │ - [ 76ea] == │ │ - [ 76ed] '\n │ │ - [ 76f0] %s │ │ - [ 76f3] operator= │ │ - [ 76fd] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/include/opencv2/core/mat.inl.hpp │ │ - [ 7783] void cv::cpu_baseline::cvt16s8s(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ 77f0] void cv::cpu_baseline::cvt16u64f(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ 785e] void cv::cpu_baseline::cvt32s16f(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ 78cc] top >= 0 && bottom >= 0 && left >= 0 && right >= 0 && _src.dims() <= 2 │ │ - [ 7913] (int)idx.size() == dims - 2 │ │ - [ 792f] cvSeqRemoveSlice │ │ - [ 7940] parent->v_next == node │ │ - [ 7957] cvInitTreeNodeIterator │ │ - [ 796e] storage->free_space >= delta │ │ - [ 798b] icvSeqElemsClearFlags │ │ - [ 79a1] convertFromD3D11Texture2D │ │ - [ 79bb] DFTInit │ │ - [ 79c3] (method != DECOMP_LU && method != DECOMP_CHOLESKY) || is_normal || src.rows == src.cols │ │ - [ 7a1b] backSubst │ │ - [ 7a25] lda │ │ - [ 7a29] %d@%llu │ │ - [ 7a31] [ WARN: │ │ - [ 7a39] void cv::polarToCart(InputArray, InputArray, OutputArray, OutputArray, bool) │ │ - [ 7a86] cvLog │ │ - [ 7a8c] void cv::perspectiveTransform(InputArray, OutputArray, InputArray) │ │ - [ 7acf] void cv::calcCovarMatrix(InputArray, OutputArray, InputOutputArray, int, int) │ │ - [ 7b1d] void cv::mulTransposed(InputArray, OutputArray, bool, InputArray, double, int) │ │ - [ 7b6c] mat.size == size │ │ - [ 7b7d] cvCalcPCA │ │ - [ 7b87] dst0.data == dst.data │ │ - [ 7b9d] void cv::cpu_baseline::gemmImpl(Mat, Mat, double, Mat, double, Mat, int) │ │ - [ 7be6] setSize │ │ - [ 7bee] Size cv::getContinuousSize2D(Mat &, Mat &, int) │ │ - [ 7c1e] allocate │ │ - [ 7c27] 0 <= coi && coi < mat.channels() │ │ - [ 7c48] insertImageCOI │ │ - [ 7c57] virtual void cv::MatOp::subtract(const Scalar &, const MatExpr &, MatExpr &) const │ │ - [ 7caa] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/matrix_iterator.cpp │ │ - [ 7d27] void cv::hconcat(InputArray, InputArray, OutputArray) │ │ - [ 7d5d] cross │ │ - [ 7d63] inp.channels() │ │ - [ 7d72] getOGlBufferRef │ │ - [ 7d82] int cv::cpu_baseline::sqsum32s(const int *, const uchar *, double *, double *, int, int) │ │ - [ 7ddb] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/merge.dispatch.cpp │ │ - [ 7e57] mv[i].size == mv[0].size && mv[i].depth() == depth │ │ - [ 7e8a] depth == CV_8S || depth == CV_16S || depth == CV_32S || depth == CV_32F || depth == CV_64F │ │ - [ 7ee5] setTexCoordArray │ │ - [ 7ef6] range.start │ │ - [ 7f02] getPluginCandidates │ │ - [ 7f16] _mean.size() == mean_sz │ │ - [ 7f2e] decodeSimpleFormat │ │ - [ 7f41] rt │ │ - [ 7f44] .json.gz │ │ - [ 7f4d] Base64ContextEmitter │ │ - [ 7f62] parseSeq │ │ - [ 7f6b] cols │ │ - [ 7f70] !!binary | │ │ - [ 7f7b] Tabs are prohibited in YAML! │ │ - [ 7f98] 0 < coi && coi <= 4 │ │ - [ 7fac] OPENCV_TEMP_PATH │ │ - [ 7fbd] Unspecified error │ │ - [ 7fcf] Internal error │ │ - [ 7fde] calling android_getCpuFeatures() ... │ │ - [ 8003] SSE4.1 │ │ - [ 800a] .txt │ │ - [ 800f] OPENCV_TRACE_LOCATION │ │ - [ 8025] void cv::UMat::convertTo(OutputArray, int, double, double) const │ │ - [ 8066] usage_count == 1 │ │ - [ 8077] utils::findDataFile(): the current directory is source sub-directory: │ │ - [ 80be] NULL │ │ - [ 80c3] load │ │ - [ 80c9] iwmmxt │ │ - [ 80d0] locale not supported │ │ - [ 80e5] typeinfo name for │ │ - [ 80f8] operator<= │ │ - [ 8103] operator+ │ │ - [ 810d] short │ │ - [ 8113] yptn │ │ - [ 8118] virtual StringView (anonymous namespace)::itanium_demangle::SpecialSubstitution::getBaseName() const │ │ - [ 817d] libunwind: %s - %s\n │ │ - [ 8191] getRegister │ │ - [ 819d] d5 │ │ - [ 81a0] d24 │ │ - [ 81a4] d28 │ │ - [ 81a8] void cv::Algorithm::writeFormat(FileStorage &) const │ │ - [ 81dd] Unsupported depth value CV_16F │ │ - [ 81fc] func │ │ - [ 8201] src2.size == dst.size && src2.channels() == dst.channels() │ │ - [ 823c] binary_op │ │ - [ 8246] The operation is neither 'array op array' (where arrays have the same size and the same number of channels), nor 'array op scalar', nor 'scalar op array' │ │ - [ 82e0] void cv::hal::cpu_baseline::cmp64f(const double *, size_t, const double *, size_t, uchar *, size_t, int, int, int) │ │ - [ 8353] cvGetRows │ │ - [ 835d] The matrix is not continuous so the number of rows can not be changed │ │ - [ 83a3] cvGetImageCOI │ │ - [ 83b1] (type == CV_8U && dtype == CV_32S) || dtype == CV_32F │ │ - [ 83e7] size(-1)=[ │ │ - [ 83f3] size(0)=%dx%d │ │ - [ 8402] downloads │ │ - [ 840c] reinterpret_cast(*ptr) % alignment == 0 │ │ - [ 843c] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/channels.cpp │ │ - [ 84b2] extractChannel │ │ - [ 84c1] must be │ │ - [ 84ca] void cv::cpu_baseline::cvt8u16u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ 8537] void cv::cpu_baseline::cvt8s16s(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ 85a4] scalarToRawData │ │ - [ 85b4] checkScalar(value, type(), _value.kind(), _InputArray::MAT ) │ │ - [ 85f1] cn == 1 │ │ - [ 85f9] CountNonZeroFunc cv::getCountNonZeroTab(int) │ │ - [ 8626] GpuMatND │ │ - [ 862f] cvCreateChildMemStorage │ │ - [ 8647] block != seq->first │ │ - [ 865b] cvGraphAddEdge │ │ - [ 866a] cvCreateGraphScanner │ │ - [ 867f] void cv::mulSpectrums(InputArray, InputArray, OutputArray, int, bool) │ │ - [ 86c5] subspaceReconstruct │ │ - [ 86d9] (size_t)eigenvectors64f.cols == n │ │ - [ 86fb] global │ │ - [ 8702] OPENCV_LOG_TIMESTAMP_NS │ │ - [ 871a] _roots.data == _roots0.data │ │ - [ 8736] void cv::hal::magnitude32f(const float *, const float *, float *, int) │ │ - [ 877d] scn == dcn │ │ - [ 8788] perspectiveTransform │ │ - [ 879d] dst.channels() == m.rows │ │ - [ 87b6] count >= 1 │ │ - [ 87c1] dst.cols <= evects.rows │ │ - [ 87d9] ScaleAddFunc cv::getScaleAddFunc(int) │ │ - [ 87ff] Size cv::getContinuousSize2D(Mat &, int) │ │ - [ 8828] u->refcount == 0 │ │ - [ 8839] srcA.size() == dst.size() && srcA.type() == dst.type() │ │ - [ 8870] idx0.data == idx.data │ │ - [ 8886] virtual void cv::MatOp_GEMM::subtract(const MatExpr &, const MatExpr &, MatExpr &) const │ │ - [ 88df] static MatExpr cv::Mat::zeros(int, const int *, int) │ │ - [ 8914] isIdentity(expr) │ │ - [ 8925] !fixedSize() || ((cuda::HostMem*)obj)->size() == _sz │ │ - [ 895a] Can't reallocate UMat with locked type (probably due to misused 'const' modifier) │ │ - [ 89ac] !fixedSize() || len == vv.size() │ │ - [ 89cd] !fixedSize() │ │ - [ 89da] getHostMemRef │ │ - [ 89e8] meanStdDev │ │ - [ 89f4] (:, :, %d) = \n │ │ - [ 8a03] } │ │ - [ 8a05] bool cv::parallel::setParallelForBackend(const std::string &, bool) │ │ - [ 8a49] - │ │ - [ 8a50] OPENCV_PARALLEL_BACKEND │ │ - [ 8a68] core(parallel): NOTE: plugin is supported, but there is API version mismath: │ │ - [ 8ab6] name │ │ - [ 8abb] FileStorage::APPEND and FileStorage::MEMORY are not currently compatible │ │ - [ 8b04] UTF-16 XML encoding is not supported! Use 8-bit encoding\n │ │ - [ 8b3e] endWriteStruct │ │ - [ 8b4d] Parser is not available │ │ - [ 8b65] fs.write_mode │ │ - [ 8b73] The key is an empty │ │ - [ 8b87] left-brace of top level is missing │ │ - [ 8baa] Unrecognized value │ │ - [ 8bbd] !sizes_node.empty() │ │ - [ 8bd1] Literal " is not allowed within a string. Use " │ │ - [ 8c06] %YAML 1. │ │ - [ 8c0f] The wrong closing bracket │ │ - [ 8c29] Missing ':' │ │ - [ 8c35] split │ │ - [ 8c3b] int cv::hal::normHamming(const uchar *, int) │ │ - [ 8c68] No OpenGL support │ │ - [ 8c7a] OPENCV_SKIP_CPU_BASELINE_CHECK │ │ - [ 8c99] AVX512PF │ │ - [ 8ca2] true │ │ - [ 8ca7] ~DynamicLib │ │ - [ 8cb3] void cv::utils::logging::LogTagManager::setLevelByFullName(const std::string &, LogLevel) │ │ - [ 8d0d] OPENCV_SAMPLES_DATA_PATH │ │ - [ 8d26] CPU variant │ │ - [ 8d32] condition_variable::wait: mutex not locked │ │ - [ 8d5d] __next_prime overflow │ │ - [ 8d73] unexpected_handler unexpectedly returned │ │ - [ 8d9c] VTT for │ │ - [ 8da5] tw │ │ - [ 8da8] nullptr │ │ - [ 8db0] string literal │ │ - [ 8dbf] struct │ │ - [ 8dc6] bool __cxxabiv1::exception_spec_can_catch(int64_t, const uint8_t *, uint8_t, const __shim_type_info *, void *, _Unwind_Control_Block *, uintptr_t) │ │ - [ 8e59] d11 │ │ - [ 8e5d] d20 │ │ - [ 8e61] void cv::bitwise_not(InputArray, OutputArray, InputArray) │ │ - [ 8e9b] cvAndS │ │ - [ 8ea2] When the input arrays in add/subtract/multiply/divide functions have different types, the output array type must be explicitly specified │ │ - [ 8f2b] void cv::hal::cpu_baseline::mul8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, int, int, const double *) │ │ - [ 8fa6] void cv::hal::add32s(const int *, size_t, const int *, size_t, int *, size_t, int, int, void *) │ │ - [ 9006] void cv::hal::sub32f(const float *, size_t, const float *, size_t, float *, size_t, int, int, void *) │ │ - [ 906c] void cv::hal::addWeighted64f(const double *, size_t, const double *, size_t, double *, size_t, int, int, void *) │ │ - [ 90de] Array should be CvMat or IplImage │ │ - [ 9100] cvGetImage │ │ - [ 910b] valid() │ │ - [ 9113] type == src2.type() && src1.cols == src2.cols && (type == CV_32F || type == CV_8U) │ │ - [ 9166] type(-1)= │ │ - [ 9171] i1 >= 0 && j < ndsts && dst[j].depth() == depth │ │ - [ 91a1] CV_32S │ │ - [ 91a8] can not convert: [%s] to [%s] │ │ - [ 91c6] void cv::cpu_baseline::cvt16u8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ 9233] void cv::cpu_baseline::cvt32s8s(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ 92a0] void cv::cpu_baseline::cvt32f16u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ 930e] void cv::cpu_baseline::cvt16u16s(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ 937c] void cv::cpu_baseline::cvt32f16s(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ 93ea] void cv::cpu_baseline::cvt64f16s(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ 9458] void cv::repeat(InputArray, int, int, OutputArray) │ │ - [ 948b] maskarr == 0 │ │ - [ 9498] findNonZero │ │ - [ 94a4] NULL storage pointer │ │ - [ 94b9] cvCreateGraph │ │ - [ 94c7] getTypeFromD3DFORMAT │ │ - [ 94dc] type == CV_32FC1 || type == CV_32FC2 || type == CV_64FC1 || type == CV_64FC2 │ │ - [ 9529] dct │ │ - [ 952d] (unsigned)j < (unsigned)n2 │ │ - [ 9548] There can't be more clusters than elements │ │ - [ 9573] bool cv::Cholesky(double *, size_t, int, double *, size_t, int) │ │ - [ 95b3] src.type() == dst.type() && src.rows == dst.cols && src.cols == dst.rows │ │ - [ 95fc] cvInvert │ │ - [ 9605] load │ │ - [ 960a] nn > 0 │ │ - [ 9611] void cv::magnitude(InputArray, InputArray, OutputArray) │ │ - [ 9649] void cv::log(InputArray, OutputArray) │ │ - [ 966f] cvCartToPolar │ │ - [ 967d] void cv::hal::exp64f(const double *, double *, int) │ │ - [ 96b1] gemm │ │ - [ 96b6] scn == m.cols || scn + 1 == m.cols │ │ - [ 96d9] type == _src2.type() │ │ - [ 96ee] data │ │ - [ 96f3] cvRange │ │ - [ 96fb] MatExpr cv::min(const Mat &, const Mat &) │ │ - [ 9725] MatExpr cv::abs(const Mat &) │ │ - [ 9742] static MatExpr cv::Mat::ones(Size, int) │ │ - [ 976a] src[i].dims <= 2 && src[i].cols == src[0].cols && src[i].type() == src[0].type() │ │ - [ 97bb] sortIdx_ │ │ - [ 97c4] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/matrix_sparse.cpp │ │ - [ 983f] hdr != 0 │ │ - [ 9848] hdr && hdr->dims == 3 │ │ - [ 985e] Only 32f and 64f are supported │ │ - [ 987d] ndim │ │ - [ 9882] int cv::cpu_baseline::sqsum16u(const ushort *, const uchar *, int *, double *, int, int) │ │ - [ 98db] SumSqrFunc cv::getSumSqrFunc(int) │ │ - [ 98fd] void cv::hal::cpu_baseline::merge16u(const ushort **, ushort *, int, int) │ │ - [ 9947] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/ocl_disabled.impl.hpp │ │ - [ 99c6] convertToGLTexture2D │ │ - [ 99db] int32 │ │ - [ 99e1] float16 │ │ - [ 99e9] ], dtype='%s') │ │ - [ 99f8] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/parallel/registry_parallel.impl.hpp │ │ - [ 9a85] calcStructSize │ │ - [ 9a94] \n │ │ - [ 9aa7] Can't open archive: ' │ │ - [ 9abd] Input file is invalid │ │ - [ 9ad3] !fs_data_ptrs.empty() │ │ - [ 9ae9] type_id │ │ - [ 9af1] Map element should have a name │ │ - [ 9b10] Invalid filename │ │ - [ 9b21] key2 < fs->str_hash_data.size() │ │ - [ 9b41] Unexpected End-Of-File │ │ - [ 9b58] '[' - left-brace of seq is missing │ │ - [ 9b7b] idx_k >= 0 │ │ - [ 9b86] int cv::cpu_baseline::sum64f(const double *, const uchar *, double *, int, int) │ │ - [ 9bd6] Incorrect size of input array │ │ - [ 9bf4] Gpu API call │ │ - [ 9c01] AVX512DQ │ │ - [ 9c0a] readSettings │ │ - [ 9c17] utils::findDataFile(): ... skip, not a valid directory: │ │ - [ 9c50] pImpl->lock() │ │ - [ 9c5e] unlock │ │ - [ 9c65] libraryRelease │ │ - [ 9c74] DISABLED │ │ - [ 9c7d] locale constructed with null │ │ - [ 9c9a] time_put_byname failed to construct for │ │ - [ 9cc3] moneypunct_byname failed to construct for │ │ - [ 9cee] _Z │ │ - [ 9cf1] covariant return thunk to │ │ - [ 9d0c] basic_ostream │ │ - [ 9d1a] char16_t │ │ - [ 9d23] & │ │ - [ 9d25] _Unwind_Resume() can't return │ │ - [ 9d43] r8 │ │ - [ 9d46] r12 │ │ - [ 9d4a] d6 │ │ - [ 9d4d] d10 │ │ - [ 9d51] The operation is neither 'array op array' (where arrays have the same size and the same type), nor 'array op scalar', nor 'scalar op array' │ │ - [ 9ddd] cvNot │ │ - [ 9de3] cvAbsDiff │ │ - [ 9ded] void cv::hal::cpu_baseline::add8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, int, int) │ │ - [ 9e58] Non-positive width or height │ │ - [ 9e75] Number of channels is not the same for all arrays │ │ - [ 9ea7] cvGetDimSize │ │ - [ 9eb4] cvGetReal1D │ │ - [ 9ec0] Input array has NULL data pointer │ │ - [ 9ee2] Unknown object type │ │ - [ 9ef6] _Function.empty()==false │ │ - [ 9f0f] void cv::cpu_baseline::cvt16f32s(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ 9f7d] void cv::cpu_baseline::cvt16f64f(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ 9feb] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/convert_c.cpp │ │ - [ a062] i < src.channels() │ │ - [ a075] size() == mask.size() │ │ - [ a08b] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/cuda_gpu_mat_nd.cpp │ │ - [ a108] cvSeqSort │ │ - [ a112] parent->bottom == block │ │ - [ a12a] innerDownhillSimplex │ │ - [ a13f] dft │ │ - [ a143] generateCentersPP │ │ - [ a155] mat.rows == mat.cols && (type == CV_32F || type == CV_64F) │ │ - [ a190] cvSolve │ │ - [ a198] Wrong shape of input matrix! Expected a matrix with one row or column. │ │ - [ a1df] void cv::patchNaNs(InputOutputArray, double) │ │ - [ a20c] patchNaNs │ │ - [ a216] cvSolveCubic │ │ - [ a223] void cv::cpu_baseline::gemm64f(const double *, size_t, const double *, size_t, double, const double *, size_t, double, double *, size_t, int, int, int, int) │ │ - [ a2c0] cvScaleAdd │ │ - [ a2cb] MulTransposedR │ │ - [ a2da] nelems <= (size_t)size.p[0] │ │ - [ a2f6] Size cv::getContinuousSize2D(Mat &, Mat &, Mat &, int) │ │ - [ a32d] extractImageCOI │ │ - [ a33d] virtual void cv::MatOp::divide(double, const MatExpr &, MatExpr &) const │ │ - [ a386] MatExpr cv::Mat::mul(InputArray, double) const │ │ - [ a3b5] reduce │ │ - [ a3bc] sort │ │ - [ a3c1] flipND: given axis is out of range │ │ - [ a3e4] void cv::broadcast(InputArray, InputArray, OutputArray) │ │ - [ a41c] empty │ │ - [ a422] !fixedSize() || ((ogl::Buffer*)obj)->size() == _sz │ │ - [ a455] void cv::hal::cpu_baseline::merge32s(const int **, int *, int, int) │ │ - [ a499] void cv::merge(const Mat *, size_t, OutputArray) │ │ - [ a4ca] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/minmax.cpp │ │ - [ a53e] (size_t)it.size │ │ - [ a54e] setUseOpenVX │ │ - [ a55b] core(parallel): Disable backend: │ │ - [ a57d] core(parallel): wrong OpenCV major version used by plugin ' │ │ - [ a5b9] ' in │ │ - [ a5bf] The storage is not opened │ │ - [ a5d9] Some collection type: FileNode::SEQ or FileNode::MAP must be specified │ │ - [ a620] addNode │ │ - [ a628] Sequence element should not have name (use <_>) │ │ - [ a65c] check_dt │ │ - [ a665] iss.eof() │ │ - [ a66f] The written string is too long │ │ - [ a68e] Attribute value should be put into single or double quotes │ │ - [ a6c9] Incorrect indentation │ │ - [ a6df] Empty type name │ │ - [ a6ef] Complex keys are not supported │ │ - [ a70e] ? │ │ - [ a710] Input COI is not supported │ │ - [ a72b] Bad type of mask argument │ │ - [ a745] NEON │ │ - [ a74a] VSX │ │ - [ a74e] u->data != 0 && "Error mapping of UMat to host memory." │ │ - [ a786] void cv::UMat::copyTo(OutputArray) const │ │ - [ a7af] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/utils/datafile.cpp │ │ - [ a82b] cv::samples::findFile(' │ │ - [ a843] condition_variable::timed wait: mutex not locked │ │ - [ a874] %I:%M:%S %p │ │ - [ a880] unexpected │ │ - [ a88b] std::bad_exception │ │ - [ a89e] libc++abi │ │ - [ a8a8] operator? │ │ - [ a8b2] Ub │ │ - [ a8b5] allocator │ │ - [ a8bf] basic_iostream │ │ - [ a8ce] NodeArray (anonymous namespace)::itanium_demangle::AbstractManglingParser<(anonymous namespace)::itanium_demangle::ManglingParser<(anonymous namespace)::DefaultAllocator>, (anonymous namespace)::DefaultAllocator>::popTrailingNodeArray(size_t) [Derived = (anonymous namespace)::itanium_demangle::ManglingParser<(anonymous namespace)::DefaultAllocator>, Alloc = (anonymous namespace)::DefaultAllocator] │ │ - [ aa5f] decltype(auto) │ │ - [ aa6e] && │ │ - [ aa71] ((ttypeEncoding == DW_EH_PE_absptr) || (ttypeEncoding == DW_EH_PE_pcrel) || (ttypeEncoding == (DW_EH_PE_pcrel | DW_EH_PE_indirect))) && "Unexpected TTypeEncoding" │ │ - [ ab14] setFloatRegister │ │ - [ ab25] r9 │ │ - [ ab28] cv::Algorithm::Algorithm() │ │ - [ ab43] void cv::bitwise_and(InputArray, InputArray, OutputArray, InputArray) │ │ - [ ab89] void cv::divide(double, InputArray, OutputArray, int) │ │ - [ abbf] cvMin │ │ - [ abc5] void cv::hal::cpu_baseline::xor8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, int, int) │ │ - [ ac30] void cv::hal::cpu_baseline::mul16u(const ushort *, size_t, const ushort *, size_t, ushort *, size_t, int, int, const double *) │ │ - [ acaf] void cv::hal::cpu_baseline::addWeighted32s(const int *, size_t, const int *, size_t, int *, size_t, int, int, const double *) │ │ - [ ad2d] void cv::hal::sub64f(const double *, size_t, const double *, size_t, double *, size_t, int, int, void *) │ │ - [ ad96] void cv::hal::mul16u(const ushort *, size_t, const ushort *, size_t, ushort *, size_t, int, int, void *) │ │ - [ adff] void cv::hal::div64f(const double *, size_t, const double *, size_t, double *, size_t, int, int, void *) │ │ - [ ae68] _dst.data == data0 │ │ - [ ae7b] Invalid sparse matrix header │ │ - [ ae98] cvSetReal* support only single-channel arrays │ │ - [ aec6] cvGetMatND │ │ - [ aed1] !has_result │ │ - [ aedd] [x= │ │ - [ aee1] 0 <= coi && coi < dcn && scn == 1 │ │ - [ af03] setTermCriteria │ │ - [ af13] void cv::cpu_baseline::cvt16s8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ af80] cn <= 4 │ │ - [ af88] sz <= sizeof(scalar) │ │ - [ af9d] 0 <= roi.x && 0 <= roi.width && roi.x + roi.width <= m.cols && 0 <= roi.y && 0 <= roi.height && roi.y + roi.height <= m.rows │ │ - [ b01a] (size_t)ptr % CV_STRUCT_ALIGN == 0 │ │ - [ b03d] writer->block->count > 0 │ │ - [ b056] cvReleaseGraphScanner │ │ - [ b06c] ihi != inhi │ │ - [ b078] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/glob.cpp │ │ - [ b0ea] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/lda.cpp │ │ - [ b15b] sortMatrixColumnsByIndices │ │ - [ b176] int cv::solveLP(InputArray, InputArray, OutputArray, double) │ │ - [ b1b3] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/mathfuncs_core.dispatch.cpp │ │ - [ b238] a_size.width == len │ │ - [ b24c] TransformFunc cv::getDiagTransformFunc(int) │ │ - [ b278] total │ │ - [ b27e] Input and output arrays must have the same number of channels │ │ - [ b2bc] virtual int cv::MatOp::type(const MatExpr &) const │ │ - [ b2ef] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/matrix_operations.cpp │ │ - [ b36e] void cv::setIdentity(InputOutputArray, const Scalar &) │ │ - [ b3a5] _sizes[i] > 0 │ │ - [ b3b3] norm │ │ - [ b3b8] void cv::transposeND(InputArray, const std::vector &, OutputArray) │ │ - [ b400] broadcast: input array must be single channel │ │ - [ b42e] getGpuMat │ │ - [ b438] sizend │ │ - [ b43f] i >= 0 && (size_t)i < vv.size() │ │ - [ b45f] !fixedSize() || len == ((std::vector*)v)->size() / esz │ │ - [ b49d] getGpuMatRef │ │ - [ b4aa] void reduceMinMax(cv::InputArray, cv::OutputArray, ReduceMode, int) │ │ - [ b4ee] double cv::norm(InputArray, int, InputArray) │ │ - [ b51b] cn >= 1 && cn <= 4 │ │ - [ b52e] TBB │ │ - [ b532] core(parallel): fallback on builtin code │ │ - [ b55b] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/pca.cpp │ │ - [ b5cc] !mean.empty() && !eigenvectors.empty() && ((mean.rows == 1 && eigenvectors.rows == data.cols) || (mean.cols == 1 && eigenvectors.rows == data.rows)) │ │ - [ b661] }\n │ │ - [ b664] .json │ │ - [ b66a] !write_stack.empty() │ │ - [ b67f] Null data pointer │ │ - [ b691] ptr >= bufferstart && ptr <= bufferEnd() │ │ - [ b6ba] setBufferPtr │ │ - [ b6c7] Bad format of floating-point constant │ │ - [ b6ed] blockIdx == fs_data_ptrs.size() - 1 │ │ - [ b711] getDefaultObjectName │ │ - [ b726] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/persistence_impl.hpp │ │ - [ b7a4] Unexpected end of line │ │ - [ b7bb] fs != 0 │ │ - [ b7c3] opencv_storage │ │ - [ b7d2] Attribute name should be followed by '=' │ │ - [ b7fb] Inplace operation is not supported │ │ - [ b81e] Unknown %s code %d │ │ - [ b831] pthread_key_create(&tlsKey, opencv_tls_destructor) == 0 │ │ - [ b869] MMX │ │ - [ b86d] releaseSlot │ │ - [ b879] Invalid value for parameter │ │ - [ b896] Trace: Total events: │ │ - [ b8ac] parallelForSetRootRegion │ │ - [ b8c5] ... Line %d: trying open '%s' │ │ - [ b8e3] utils::findDataFile(): can't find data file via │ │ - [ b914] /proc/cpuinfo │ │ - [ b922] std::bad_alloc │ │ - [ b931] out/llvm-project/libcxxabi/src/demangle/ItaniumDemangle.h │ │ - [ b96b] operator. │ │ - [ b975] __int128 │ │ - [ b97e] Last != First && "Popping empty vector!" │ │ - [ b9a7] decimal64 │ │ - [ b9b1] reinterpret_cast(p + 1) % RequiredAlignment == 0 │ │ - [ b9ea] unwind_phase2 │ │ - [ b9f8] d9 │ │ - [ b9fb] d15 │ │ - [ b9ff] d16 │ │ - [ ba03] void cv::multiply(InputArray, InputArray, OutputArray, double, int) │ │ - [ ba47] void cv::hal::cpu_baseline::cmp32f(const float *, size_t, const float *, size_t, uchar *, size_t, int, int, int) │ │ - [ bab8] void cv::hal::cpu_baseline::mul16s(const short *, size_t, const short *, size_t, short *, size_t, int, int, const double *) │ │ - [ bb34] void cv::hal::min32f(const float *, size_t, const float *, size_t, float *, size_t, int, int, void *) │ │ - [ bb9a] void cv::hal::absdiff8s(const schar *, size_t, const schar *, size_t, schar *, size_t, int, int, void *) │ │ - [ bc03] void cv::hal::addWeighted8s(const schar *, size_t, const schar *, size_t, schar *, size_t, int, int, void *) │ │ - [ bc70] Iterator with mask is not supported │ │ - [ bc94] iterator != 0 │ │ - [ bca2] None of array parameters is changed: dummy call? │ │ - [ bcd3] cvResetImageROI │ │ - [ bce3] cvGetImageROI │ │ - [ bcf1] Accuracy flag is set and epsilon is < 0 │ │ - [ bd19] setValue │ │ - [ bd22] !nidx.empty() │ │ - [ bd30] ' │ │ - [ bd36] greater than │ │ - [ bd43] void cv::hal::cpu_baseline::addRNGBias64f(double *, const double *, int) │ │ - [ bd8c] convertTo │ │ - [ bd96] void cv::cpu_baseline::cvt32s64f(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ be04] dims > 0 && dims < CV_MAX_DIM │ │ - [ be22] copyMakeBorder │ │ - [ be31] src.channels() == dst.channels() │ │ - [ be52] GpuMat │ │ - [ be59] createGpuMatHeader │ │ - [ be6c] NULL sequence pointer │ │ - [ be82] cvSetRemove │ │ - [ be8e] vertex pointers coincide (or set to NULL) │ │ - [ beb8] createInitialSimplex │ │ - [ becd] !((flags & DFT_COMPLEX_INPUT) && src.channels() != 2) │ │ - [ bf03] srcA.size == dst.size && srcA.type() == dst.type() │ │ - [ bf36] cvDCT │ │ - [ bf3c] The function can not solve under-determined linear systems │ │ - [ bf77] rhs.data == 0 || (rhs.type() == type && rhs.rows == m) │ │ - [ bfae] void cv::hal::cpu_baseline::invSqrt32f(const float *, float *, int) │ │ - [ bff2] src1.size == src2.size │ │ - [ c009] dst.rows == data.rows │ │ - [ c01f] double cv::dotProd_8s(const schar *, const schar *, int) │ │ - [ c058] (int)ranges.size() == d │ │ - [ c070] m1.dims │ │ - [ c078] is_m2_vector │ │ - [ c085] src.size() == idx.size() && idx.type() == CV_32S && src.data != idx.data │ │ - [ c0ce] static MatExpr cv::Mat::ones(int, int, int) │ │ - [ c0fa] void cv::vconcat(InputArray, OutputArray) │ │ - [ c124] sortIdx │ │ - [ c12c] 0 <= i && i < sz.height │ │ - [ c144] create() called for the missing output array │ │ - [ c171] SumSqrFunc cv::cpu_baseline::getSumSqrFunc(int) │ │ - [ c1a1] void cv::hal::cpu_baseline::merge8u(const uchar **, uchar *, int, int) │ │ - [ c1e8] merge │ │ - [ c1ee] Unsupported matrix type. │ │ - [ c207] %d.0 │ │ - [ c20c] mode │ │ - [ c212] \n │ │ - [ c237] unlock() │ │ - [ c4bf] SILENT │ │ - [ c4c6] /sys/devices/system/cpu/possible │ │ - [ c4e7] ios_base::clear │ │ - [ c4f7] a+e │ │ - [ c4fb] terminating due to %s exception of type %s │ │ - [ c526] _block_invoke │ │ - [ c534] virtual thunk to │ │ - [ c546] operator co_await │ │ - [ c558] vE │ │ - [ c55b] Last != First && "Calling back() on empty vector!" │ │ - [ c58e] s22 │ │ - [ c592] d19 │ │ - [ c596] OPENCV_ENABLE_MEMALIGN │ │ - [ c5ad] void cv::min(InputArray, InputArray, OutputArray) │ │ - [ c5df] void cv::hal::cpu_baseline::add16u(const ushort *, size_t, const ushort *, size_t, ushort *, size_t, int, int) │ │ - [ c64e] void cv::hal::cpu_baseline::absdiff16u(const ushort *, size_t, const ushort *, size_t, ushort *, size_t, int, int) │ │ - [ c6c1] void cv::hal::cpu_baseline::div8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, int, int, const double *) │ │ - [ c73c] void cv::hal::cmp8s(const schar *, size_t, const schar *, size_t, uchar *, size_t, int, int, void *) │ │ - [ c7a1] void cv::hal::cmp32f(const float *, size_t, const float *, size_t, uchar *, size_t, int, int, void *) │ │ - [ c807] Either all the pointers should be null or they all should be non-null │ │ - [ c84d] cvSetIPLAllocators │ │ - [ c860] NULL pointer │ │ - [ c875] one of dimension sizes is non-positive │ │ - [ c89c] cvGetCols │ │ - [ c8a6] cvGet2D │ │ - [ c8ae] timeoutNs < 0 │ │ - [ c8bc] The combination of type=%d, dtype=%d and normType=%d is not supported │ │ - [ c902] commit │ │ - [ c909] (expected: ' │ │ - [ c917] >= │ │ - [ c91a] Field KEYS could not be empty\n │ │ - [ c939] void cv::cpu_baseline::cvt8s8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ c9a5] void cv::cpu_baseline::cvt32s8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ ca12] void cv::cpu_baseline::cvt16f32f(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ ca80] dvec[j].channels() == 1 │ │ - [ ca98] borderInterpolate │ │ - [ caaa] cvClearMemStorage │ │ - [ cabc] cvStartWriteSeq │ │ - [ cacc] cvSeqInsert │ │ - [ cad8] Source and destination sequence element sizes are different. │ │ - [ cb15] Null graph scanner │ │ - [ cb28] counters[k] != 0 │ │ - [ cb39] A.type() == x.type() && A.cols == x.rows && x.cols == b.cols │ │ - [ cb76] subspaceProject │ │ - [ cb86] ctype == CV_32F || ctype == CV_64F │ │ - [ cba9] a_size.height == len │ │ - [ cbbe] type == CV_64FC2 │ │ - [ cbcf] data[i].size() == size │ │ - [ cbe6] delta.channels() == 1 │ │ - [ cbfc] (D.cols == ((flags & 2) == 0 ? B.cols : B.rows)) │ │ - [ cc2d] delta_cols == 1 │ │ - [ cc3d] m.dims <= 2 │ │ - [ cc49] locateROI │ │ - [ cc53] total_sz │ │ - [ cc5c] getContinuousSize2D │ │ - [ cc70] src.size() == dst.size() && src.type() == dst.type() │ │ - [ cca5] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/matrix_expressions.cpp │ │ - [ cd25] virtual void cv::MatOp_T::transpose(const MatExpr &, MatExpr &) const │ │ - [ cd6b] narrays <= 1000 │ │ - [ cd7b] pos │ │ - [ cd7f] completeSymm │ │ - [ cd8c] hdr │ │ - [ cd90] it.ptr │ │ - [ cd97] Unknown/unsupported norm type │ │ - [ cdb5] CV_MAT_TYPE(mtype) == m.type() │ │ - [ cdd4] int cv::cpu_baseline::sqsum16s(const short *, const uchar *, int *, double *, int, int) │ │ - [ ce2c] PSNR │ │ - [ ce31] setColorArray │ │ - [ ce3f] rbe │ │ - [ ce43] (priority= │ │ - [ ce4f] core(parallel): exception during plugin loading: │ │ - [ ce81] %.4e │ │ - [ ce86] %.8e │ │ - [ ce8b] getsFromFile │ │ - [ ce98] maxCount < MAX_BLOCK_SIZE │ │ - [ ceb2] binary │ │ - [ ceb9] symbolToType │ │ - [ cec6] Key must start with '"' │ │ - [ cede] Key must end with '"' │ │ - [ cef4] , (anonymous namespace)::DefaultAllocator>::ScopedTemplateParamList::~ScopedTemplateParamList() [Derived = (anonymous namespace)::itanium_demangle::ManglingParser<(anonymous namespace)::DefaultAllocator>, Alloc = (anonymous namespace)::DefaultAllocator] │ │ - [ d25d] out/llvm-project/libcxxabi/src/demangle/StringView.h │ │ - [ d292] basic_istream │ │ - [ d2a0] long double │ │ - [ d2ac] index inlined table detected but pr function requires extra words │ │ - [ d2ee] r6 │ │ - [ d2f1] s2 │ │ - [ d2f4] s9 │ │ - [ d2f7] s18 │ │ - [ d2fb] void cv::hal::cpu_baseline::cmp16u(const ushort *, size_t, const ushort *, size_t, uchar *, size_t, int, int, int) │ │ - [ d36e] void cv::hal::cpu_baseline::addWeighted32f(const float *, size_t, const float *, size_t, float *, size_t, int, int, const double *) │ │ - [ d3f2] void cv::hal::div16u(const ushort *, size_t, const ushort *, size_t, ushort *, size_t, int, int, void *) │ │ - [ d45b] void cv::hal::recip64f(const double *, size_t, const double *, size_t, double *, size_t, int, int, void *) │ │ - [ d4c6] Data type is not the same for all arrays │ │ - [ d4ef] The total width is not divisible by the new number of channels │ │ - [ d52e] Bad input origin │ │ - [ d53f] Iterations flag is set and maximum number of iterations is <= 0 │ │ - [ d57f] static_cast(*ptr) + type_size * count <= static_cast(raw_mem) + type_size * allocated_count │ │ - [ d5eb] vector │ │ - [ d5f2] j < nsrcs && src[j].depth() == depth │ │ - [ d617] ' │ │ - [ d619] %s │ │ - [ d61d] x_mat.type()==CV_64FC1 │ │ - [ d634] void cv::cpu_baseline::cvt64f16u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ d6a2] void cv::cpu_baseline::cvt8s64f(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ d70f] void cv::cpu_baseline::cvt64f16f(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ - [ d77d] nz > 0 │ │ - [ d784] src.size == dst.size && dst.type() == CV_8UC(src.channels()) │ │ - [ d7c1] cvSetSeqReaderPos │ │ - [ d7d3] set != NULL │ │ - [ d7df] seq->first->start_index == 0 │ │ - [ d7fc] icvFreeSeqBlock │ │ - [ d80c] seq->ptr == block->data │ │ - [ d824] termcrit.type == (TermCriteria::MAX_ITER + TermCriteria::EPS) && termcrit.epsilon > 0 && termcrit.maxCount > 0 │ │ - [ d893] kmeans: can't update cluster center (check input for huge or NaN values) │ │ - [ d8dc] compute │ │ - [ d8e4] The data is expected as InputArray::STD_VECTOR_MAT (a std::vector) or _InputArray::STD_VECTOR_VECTOR (a std::vector< std::vector<...> >). │ │ - [ d973] (Func_.rows()==1 && (Constr_.cols()-Func_.cols()==1))|| (Func_.cols()==1 && (Constr_.cols()-Func_.rows()==1)) │ │ - [ d9e1] void cv::phase(InputArray, InputArray, OutputArray, bool) │ │ - [ da1b] CV_MAT_DEPTH(ctype) >= CV_32F && CV_MAT_CN(ctype) <= 2 │ │ - [ da52] void cv::hal::gemm64fc(const double *, size_t, const double *, size_t, double, const double *, size_t, double, double *, size_t, int, int, int, int) │ │ - [ dae7] (*each).type() == type │ │ - [ dafe] double cv::Mahalanobis(InputArray, InputArray, InputArray) │ │ - [ db39] dims <= 2 │ │ - [ db43] Pushed vector type is not the same as matrix type │ │ - [ db75] dims <= 2 && step[0] > 0 │ │ - [ db8e] empty() │ │ - [ db96] cvIplImage │ │ - [ dba1] img->dataOrder == IPL_DATA_ORDER_PIXEL || img->roi->coi != 0 │ │ - [ dbde] virtual void cv::MatOp_Bin::divide(double, const MatExpr &, MatExpr &) const │ │ - [ dc2b] virtual void cv::MatOp_T::multiply(const MatExpr &, double, MatExpr &) const │ │ - [ dc78] MatExpr cv::Mat::t() const │ │ - [ dc93] _m.dims() <= 2 │ │ - [ dca2] void cv::completeSymm(InputOutputArray, bool) │ │ - [ dcd0] hdr && hdr->dims == 1 │ │ - [ dce6] broadcast: input array must be contiguous │ │ - [ dd10] broadcast: not supported data type │ │ - [ dd33] i < (int)vv.size() │ │ - [ dd46] mv && n > 0 │ │ - [ dd52] _src1.type() == _src2.type() │ │ - [ dd6f] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/ovx.cpp │ │ - [ dde0] core(parallel): exception during plugin initialization: │ │ - [ de19] ParallelBackendRegistry │ │ - [ de31] core(parallel): trying backend: │ │ - [ de52] fs.isOpened() │ │ - [ de60] decodeFormat │ │ - [ de6d] NULL or empty filename │ │ - [ de84] startNextStream │ │ - [ de94] readRaw │ │ - [ de9c] make_base64_header │ │ - [ deaf] ']' - right-brace of seq is missing │ │ - [ ded3] sizes │ │ - [ ded9] nelems == m.total()*m.channels() │ │ - [ defa] Directive tags are not allowed here │ │ - [ df1f] General configuration for OpenCV 4.9.0 =====================================\n │ │ + [ 63fe] General configuration for OpenCV 4.9.0 =====================================\n │ │ Version control: 3.0.5-dirty\n │ │ Platform:\n │ │ - Timestamp: 2024-10-16T01:58:13Z\n │ │ - Host: Linux 6.1.0-25-amd64 x86_64\n │ │ + Timestamp: 2024-12-14T10:27:37Z\n │ │ + Host: Linux 6.1.0-28-amd64 x86_64\n │ │ Target: Android 1 armv7-a\n │ │ CMake: 3.22.1-g37088a8\n │ │ CMake generator: Ninja\n │ │ CMake build tool: /opt/android-sdk/cmake/3.22.1/bin/ninja\n │ │ Configuration: Release\n │ │ CPU/HW features:\n │ │ Baseline: NEON\n │ │ @@ -1519,15 +702,832 @@ │ │ Trace: YES (built-in)\n │ │ Other third-party libraries:\n │ │ Custom HAL: NO\n │ │ Flatbuffers: builtin/3rdparty (23.5.9)\n │ │ Python (for build): /usr/bin/python3\n │ │ Install to: /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/.cxx/Release/t1f4h131/armeabi-v7a/install\n │ │ -----------------------------------------------------------------\n │ │ - OPENCV_DUMP_CONFIG │ │ + Input image depth is not supported by function │ │ + [ 7ea8] Parsing error │ │ + [ 7eb6] OPENCV: Trying to disable baseline CPU feature: '%s'.This has very limited effect, because code optimizations for this feature are executed unconditionally in the most cases.\n │ │ + [ 7f66] OPENCV_TRACE_MAX_CHILDREN_OPENCV │ │ + [ 7f87] convert │ │ + [ 7f8f] static void cv::KeyPoint::convert(const std::vector &, std::vector &, float, float, int, int) │ │ + [ 8000] findDataFile │ │ + [ 800d] WARNINGS │ │ + [ 8016] collate_byname::collate_byname failed to construct for │ │ + [ 8054] codecvt_byname::codecvt_byname failed to construct for │ │ + [ 80a6] %a │ │ + [ 80a9] guard variable for │ │ + [ 80bd] so │ │ + [ 80c0] __uuidof │ │ + [ 80c9] decimal32 │ │ + [ 80d3] complex │ │ + [ 80dc] actions & (_UA_SEARCH_PHASE | _UA_HANDLER_FRAME | _UA_FORCE_UNWIND) │ │ + [ 8120] d26 │ │ + [ 8124] cvtFn │ │ + [ 812a] cvOrS │ │ + [ 8130] psrc1->sameSize(*psrc2) && type1 == type2 │ │ + [ 815a] void cv::hal::cpu_baseline::max32s(const int *, size_t, const int *, size_t, int *, size_t, int, int) │ │ + [ 81c0] void cv::hal::cpu_baseline::absdiff8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, int, int) │ │ + [ 822f] void cv::hal::cpu_baseline::absdiff64f(const double *, size_t, const double *, size_t, double *, size_t, int, int) │ │ + [ 82a2] void cv::hal::cpu_baseline::mul8s(const schar *, size_t, const schar *, size_t, schar *, size_t, int, int, const double *) │ │ + [ 831d] void cv::hal::sub8s(const schar *, size_t, const schar *, size_t, schar *, size_t, int, int, void *) │ │ + [ 8382] void cv::hal::min64f(const double *, size_t, const double *, size_t, double *, size_t, int, int, void *) │ │ + [ 83eb] void cv::hal::max64f(const double *, size_t, const double *, size_t, double *, size_t, int, int, void *) │ │ + [ 8454] void cv::hal::xor8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, int, int, void *) │ │ + [ 84b9] void cv::hal::mul8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, int, int, void *) │ │ + [ 851e] cmpop == CMP_NE │ │ + [ 852e] cvInitMatHeader │ │ + [ 853e] Iterator pointer is NULL │ │ + [ 8557] cvSetData │ │ + [ 8561] cvPtr3D │ │ + [ 8569] cvSet1D │ │ + [ 8571] cvSet2D │ │ + [ 8579] cvCheckTermCriteria │ │ + [ 858d] kind=0x%08llx │ │ + [ 859c] oneBuf == NULL │ │ + [ 85ab] < │ │ + [ 85ad] dst.size() == src.size() && dst.type() == CV_MAKETYPE(lut.depth(), src.channels()) │ │ + [ 8600] cvNormalize │ │ + [ 860c] mask.depth() == CV_8U && (mcn == 1 || mcn == cn) │ │ + [ 863d] Effectively2D(*this) │ │ + [ 8652] ptr + elem_size <= seq->block_max │ │ + [ 8674] cvSeqPushMulti │ │ + [ 8683] cvSeqPartition │ │ + [ 8692] cvGraphAddVtx │ │ + [ 86a0] icvGrowSeq │ │ + [ 86ab] convertToD3D10Texture2D │ │ + [ 86c3] elem_size == sizeof(Complex) │ │ + [ 86e7] glob_rec │ │ + [ 86f0] OPENCV_KMEANS_PARALLEL_GRANULARITY │ │ + [ 8713] virtual void cv::KMeansDistanceComputer::operator()(const Range &) const [onlyDistance = false] │ │ + [ 877a] double cv::determinant(InputArray) │ │ + [ 879d] method == DECOMP_LU || method == DECOMP_CHOLESKY │ │ + [ 87ce] solve │ │ + [ 87d4] void cv::SVBackSubst(InputArray, InputArray, InputArray, InputArray, OutputArray) │ │ + [ 8826] cvSVD │ │ + [ 882c] cvSVBkSb │ │ + [ 8835] void cv::hal::cpu_baseline::sqrt32f(const float *, float *, int) │ │ + [ 8876] void cv::hal::sqrt64f(const double *, double *, int) │ │ + [ 88ab] void cv::hal::exp32f(const float *, float *, int) │ │ + [ 88dd] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/matmul.simd.hpp │ │ + [ 8956] void cv::cpu_baseline::gemm32fc(const float *, size_t, const float *, size_t, float, const float *, size_t, float, float *, size_t, int, int, int, int) │ │ + [ 89ee] calcCovarMatrix │ │ + [ 89fe] nsamples > 0 │ │ + [ 8a0b] The total matrix size does not fit to "size_t" type │ │ + [ 8a3f] resize │ │ + [ 8a46] d.cols == 1 || d.rows == 1 │ │ + [ 8a61] m2.dims │ │ + [ 8a69] cvarrToMat │ │ + [ 8a74] virtual void cv::MatOp::multiply(const MatExpr &, double, MatExpr &) const │ │ + [ 8abf] MatExpr cv::min(const Mat &, double) │ │ + [ 8ae4] vconcat │ │ + [ 8aec] trace │ │ + [ 8af2] void cv::reduce(InputArray, OutputArray, int, int, int) │ │ + [ 8b2a] _sizes && 0 < d && d <= CV_MAX_DIM │ │ + [ 8b4d] transposeND │ │ + [ 8b59] type │ │ + [ 8b5e] i >= 0 && i < (int)vv.size() │ │ + [ 8b7b] !fixedType() || ((cuda::GpuMat*)obj)->type() == mtype │ │ + [ 8bb1] move │ │ + [ 8bb6] mask.empty() || mask.type() == CV_8U │ │ + [ 8bdb] void cv::hal::merge16u(const ushort **, ushort *, int, int) │ │ + [ 8c17] void cv::minMaxLoc(InputArray, double *, double *, Point *, Point *, InputArray) │ │ + [ 8c68] core(parallel): Updated backends priorities: │ │ + [ 8c96] backend: Unknown C++ exception │ │ + [ 8cb6] backend: │ │ + [ 8cc1] initPluginAPI │ │ + [ 8ccf] core(parallel): initialized ' │ │ + [ 8ced] read │ │ + [ 8cf2] open │ │ + [ 8cf7] parseBase64 │ │ + [ 8d03] %s(%d): %s │ │ + [ 8d0e] blockIdx < fs_data_ptrs.size() │ │ + [ 8d2d] Invalid fs.state │ │ + [ 8d3e] Invalid character in the stream │ │ + [ 8d5e] n.isInt() │ │ + [ 8d68] The YAML streams must start with '---', except the first one │ │ + [ 8da5] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/system.cpp │ │ + [ 8e19] Bad parameter of type CvPoint │ │ + [ 8e37] AVX512VL │ │ + [ 8e40] FALSE │ │ + [ 8e46] _HINT= │ │ + [ 8e4d] => result: │ │ + [ 8e5b] findFile │ │ + [ 8e64] idivt │ │ + [ 8e6a] %A │ │ + [ 8e6d] thread-local wrapper routine for │ │ + [ 8e8f] tl │ │ + [ 8e92] operator- │ │ + [ 8e9c] operator!= │ │ + [ 8ea7] const __shim_type_info *__cxxabiv1::get_shim_type_info(uint64_t, const uint8_t *, uint8_t, bool, _Unwind_Control_Block *, uintptr_t) │ │ + [ 8f2c] s4 │ │ + [ 8f2f] unknown register │ │ + [ 8f40] void cv::hal::cpu_baseline::addWeighted8s(const schar *, size_t, const schar *, size_t, schar *, size_t, int, int, const double *) │ │ + [ 8fc3] void cv::hal::cmp16u(const ushort *, size_t, const ushort *, size_t, uchar *, size_t, int, int, void *) │ │ + [ 902b] The array is too big │ │ + [ 9040] cvReleaseSparseMat │ │ + [ 9053] cvCloneSparseMat │ │ + [ 9064] cvPtr2D │ │ + [ 906c] The total matrix width is not divisible by the new number of columns │ │ + [ 90b1] icvGetNodePtr │ │ + [ 90bf] Associated AsyncArray has been destroyed │ │ + [ 90e8] , w= │ │ + [ 90ed] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/buffer_area.cpp │ │ + [ 9166] == │ │ + [ 9169] '\n │ │ + [ 916c] %s │ │ + [ 916f] operator= │ │ + [ 9179] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/include/opencv2/core/mat.inl.hpp │ │ + [ 91ff] void cv::cpu_baseline::cvt16s8s(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ 926c] void cv::cpu_baseline::cvt16u64f(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ 92da] void cv::cpu_baseline::cvt32s16f(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ 9348] top >= 0 && bottom >= 0 && left >= 0 && right >= 0 && _src.dims() <= 2 │ │ + [ 938f] (int)idx.size() == dims - 2 │ │ + [ 93ab] cvSeqRemoveSlice │ │ + [ 93bc] parent->v_next == node │ │ + [ 93d3] cvInitTreeNodeIterator │ │ + [ 93ea] storage->free_space >= delta │ │ + [ 9407] icvSeqElemsClearFlags │ │ + [ 941d] convertFromD3D11Texture2D │ │ + [ 9437] DFTInit │ │ + [ 943f] (method != DECOMP_LU && method != DECOMP_CHOLESKY) || is_normal || src.rows == src.cols │ │ + [ 9497] backSubst │ │ + [ 94a1] lda │ │ + [ 94a5] %d@%llu │ │ + [ 94ad] [ WARN: │ │ + [ 94b5] void cv::polarToCart(InputArray, InputArray, OutputArray, OutputArray, bool) │ │ + [ 9502] cvLog │ │ + [ 9508] void cv::perspectiveTransform(InputArray, OutputArray, InputArray) │ │ + [ 954b] void cv::calcCovarMatrix(InputArray, OutputArray, InputOutputArray, int, int) │ │ + [ 9599] void cv::mulTransposed(InputArray, OutputArray, bool, InputArray, double, int) │ │ + [ 95e8] mat.size == size │ │ + [ 95f9] cvCalcPCA │ │ + [ 9603] dst0.data == dst.data │ │ + [ 9619] void cv::cpu_baseline::gemmImpl(Mat, Mat, double, Mat, double, Mat, int) │ │ + [ 9662] setSize │ │ + [ 966a] Size cv::getContinuousSize2D(Mat &, Mat &, int) │ │ + [ 969a] allocate │ │ + [ 96a3] 0 <= coi && coi < mat.channels() │ │ + [ 96c4] insertImageCOI │ │ + [ 96d3] virtual void cv::MatOp::subtract(const Scalar &, const MatExpr &, MatExpr &) const │ │ + [ 9726] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/matrix_iterator.cpp │ │ + [ 97a3] void cv::hconcat(InputArray, InputArray, OutputArray) │ │ + [ 97d9] cross │ │ + [ 97df] inp.channels() │ │ + [ 97ee] getOGlBufferRef │ │ + [ 97fe] int cv::cpu_baseline::sqsum32s(const int *, const uchar *, double *, double *, int, int) │ │ + [ 9857] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/merge.dispatch.cpp │ │ + [ 98d3] mv[i].size == mv[0].size && mv[i].depth() == depth │ │ + [ 9906] depth == CV_8S || depth == CV_16S || depth == CV_32S || depth == CV_32F || depth == CV_64F │ │ + [ 9961] setTexCoordArray │ │ + [ 9972] range.start │ │ + [ 997e] getPluginCandidates │ │ + [ 9992] _mean.size() == mean_sz │ │ + [ 99aa] decodeSimpleFormat │ │ + [ 99bd] rt │ │ + [ 99c0] .json.gz │ │ + [ 99c9] Base64ContextEmitter │ │ + [ 99de] parseSeq │ │ + [ 99e7] cols │ │ + [ 99ec] !!binary | │ │ + [ 99f7] Tabs are prohibited in YAML! │ │ + [ 9a14] 0 < coi && coi <= 4 │ │ + [ 9a28] OPENCV_TEMP_PATH │ │ + [ 9a39] Unspecified error │ │ + [ 9a4b] Internal error │ │ + [ 9a5a] calling android_getCpuFeatures() ... │ │ + [ 9a7f] SSE4.1 │ │ + [ 9a86] .txt │ │ + [ 9a8b] OPENCV_TRACE_LOCATION │ │ + [ 9aa1] void cv::UMat::convertTo(OutputArray, int, double, double) const │ │ + [ 9ae2] usage_count == 1 │ │ + [ 9af3] utils::findDataFile(): the current directory is source sub-directory: │ │ + [ 9b3a] NULL │ │ + [ 9b3f] load │ │ + [ 9b45] iwmmxt │ │ + [ 9b4c] locale not supported │ │ + [ 9b61] typeinfo name for │ │ + [ 9b74] operator<= │ │ + [ 9b7f] operator+ │ │ + [ 9b89] short │ │ + [ 9b8f] yptn │ │ + [ 9b94] virtual StringView (anonymous namespace)::itanium_demangle::SpecialSubstitution::getBaseName() const │ │ + [ 9bf9] libunwind: %s - %s\n │ │ + [ 9c0d] getRegister │ │ + [ 9c19] d5 │ │ + [ 9c1c] d24 │ │ + [ 9c20] d28 │ │ + [ 9c24] void cv::Algorithm::writeFormat(FileStorage &) const │ │ + [ 9c59] Unsupported depth value CV_16F │ │ + [ 9c78] func │ │ + [ 9c7d] src2.size == dst.size && src2.channels() == dst.channels() │ │ + [ 9cb8] binary_op │ │ + [ 9cc2] The operation is neither 'array op array' (where arrays have the same size and the same number of channels), nor 'array op scalar', nor 'scalar op array' │ │ + [ 9d5c] void cv::hal::cpu_baseline::cmp64f(const double *, size_t, const double *, size_t, uchar *, size_t, int, int, int) │ │ + [ 9dcf] cvGetRows │ │ + [ 9dd9] The matrix is not continuous so the number of rows can not be changed │ │ + [ 9e1f] cvGetImageCOI │ │ + [ 9e2d] (type == CV_8U && dtype == CV_32S) || dtype == CV_32F │ │ + [ 9e63] size(-1)=[ │ │ + [ 9e6f] size(0)=%dx%d │ │ + [ 9e7e] downloads │ │ + [ 9e88] reinterpret_cast(*ptr) % alignment == 0 │ │ + [ 9eb8] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/channels.cpp │ │ + [ 9f2e] extractChannel │ │ + [ 9f3d] must be │ │ + [ 9f46] void cv::cpu_baseline::cvt8u16u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ 9fb3] void cv::cpu_baseline::cvt8s16s(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ a020] scalarToRawData │ │ + [ a030] checkScalar(value, type(), _value.kind(), _InputArray::MAT ) │ │ + [ a06d] cn == 1 │ │ + [ a075] CountNonZeroFunc cv::getCountNonZeroTab(int) │ │ + [ a0a2] GpuMatND │ │ + [ a0ab] cvCreateChildMemStorage │ │ + [ a0c3] block != seq->first │ │ + [ a0d7] cvGraphAddEdge │ │ + [ a0e6] cvCreateGraphScanner │ │ + [ a0fb] void cv::mulSpectrums(InputArray, InputArray, OutputArray, int, bool) │ │ + [ a141] subspaceReconstruct │ │ + [ a155] (size_t)eigenvectors64f.cols == n │ │ + [ a177] global │ │ + [ a17e] OPENCV_LOG_TIMESTAMP_NS │ │ + [ a196] _roots.data == _roots0.data │ │ + [ a1b2] void cv::hal::magnitude32f(const float *, const float *, float *, int) │ │ + [ a1f9] scn == dcn │ │ + [ a204] perspectiveTransform │ │ + [ a219] dst.channels() == m.rows │ │ + [ a232] count >= 1 │ │ + [ a23d] dst.cols <= evects.rows │ │ + [ a255] ScaleAddFunc cv::getScaleAddFunc(int) │ │ + [ a27b] Size cv::getContinuousSize2D(Mat &, int) │ │ + [ a2a4] u->refcount == 0 │ │ + [ a2b5] srcA.size() == dst.size() && srcA.type() == dst.type() │ │ + [ a2ec] idx0.data == idx.data │ │ + [ a302] virtual void cv::MatOp_GEMM::subtract(const MatExpr &, const MatExpr &, MatExpr &) const │ │ + [ a35b] static MatExpr cv::Mat::zeros(int, const int *, int) │ │ + [ a390] isIdentity(expr) │ │ + [ a3a1] !fixedSize() || ((cuda::HostMem*)obj)->size() == _sz │ │ + [ a3d6] Can't reallocate UMat with locked type (probably due to misused 'const' modifier) │ │ + [ a428] !fixedSize() || len == vv.size() │ │ + [ a449] !fixedSize() │ │ + [ a456] getHostMemRef │ │ + [ a464] meanStdDev │ │ + [ a470] (:, :, %d) = \n │ │ + [ a47f] } │ │ + [ a481] bool cv::parallel::setParallelForBackend(const std::string &, bool) │ │ + [ a4c5] - │ │ + [ a4cc] OPENCV_PARALLEL_BACKEND │ │ + [ a4e4] core(parallel): NOTE: plugin is supported, but there is API version mismath: │ │ + [ a532] name │ │ + [ a537] FileStorage::APPEND and FileStorage::MEMORY are not currently compatible │ │ + [ a580] UTF-16 XML encoding is not supported! Use 8-bit encoding\n │ │ + [ a5ba] endWriteStruct │ │ + [ a5c9] Parser is not available │ │ + [ a5e1] fs.write_mode │ │ + [ a5ef] The key is an empty │ │ + [ a603] left-brace of top level is missing │ │ + [ a626] Unrecognized value │ │ + [ a639] !sizes_node.empty() │ │ + [ a64d] Literal " is not allowed within a string. Use " │ │ + [ a682] %YAML 1. │ │ + [ a68b] The wrong closing bracket │ │ + [ a6a5] Missing ':' │ │ + [ a6b1] split │ │ + [ a6b7] int cv::hal::normHamming(const uchar *, int) │ │ + [ a6e4] No OpenGL support │ │ + [ a6f6] OPENCV_SKIP_CPU_BASELINE_CHECK │ │ + [ a715] AVX512PF │ │ + [ a71e] true │ │ + [ a723] ~DynamicLib │ │ + [ a72f] void cv::utils::logging::LogTagManager::setLevelByFullName(const std::string &, LogLevel) │ │ + [ a789] OPENCV_SAMPLES_DATA_PATH │ │ + [ a7a2] CPU variant │ │ + [ a7ae] condition_variable::wait: mutex not locked │ │ + [ a7d9] __next_prime overflow │ │ + [ a7ef] unexpected_handler unexpectedly returned │ │ + [ a818] VTT for │ │ + [ a821] tw │ │ + [ a824] nullptr │ │ + [ a82c] string literal │ │ + [ a83b] struct │ │ + [ a842] bool __cxxabiv1::exception_spec_can_catch(int64_t, const uint8_t *, uint8_t, const __shim_type_info *, void *, _Unwind_Control_Block *, uintptr_t) │ │ + [ a8d5] d11 │ │ + [ a8d9] d20 │ │ + [ a8dd] void cv::bitwise_not(InputArray, OutputArray, InputArray) │ │ + [ a917] cvAndS │ │ + [ a91e] When the input arrays in add/subtract/multiply/divide functions have different types, the output array type must be explicitly specified │ │ + [ a9a7] void cv::hal::cpu_baseline::mul8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, int, int, const double *) │ │ + [ aa22] void cv::hal::add32s(const int *, size_t, const int *, size_t, int *, size_t, int, int, void *) │ │ + [ aa82] void cv::hal::sub32f(const float *, size_t, const float *, size_t, float *, size_t, int, int, void *) │ │ + [ aae8] void cv::hal::addWeighted64f(const double *, size_t, const double *, size_t, double *, size_t, int, int, void *) │ │ + [ ab5a] Array should be CvMat or IplImage │ │ + [ ab7c] cvGetImage │ │ + [ ab87] valid() │ │ + [ ab8f] type == src2.type() && src1.cols == src2.cols && (type == CV_32F || type == CV_8U) │ │ + [ abe2] type(-1)= │ │ + [ abed] i1 >= 0 && j < ndsts && dst[j].depth() == depth │ │ + [ ac1d] CV_32S │ │ + [ ac24] can not convert: [%s] to [%s] │ │ + [ ac42] void cv::cpu_baseline::cvt16u8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ acaf] void cv::cpu_baseline::cvt32s8s(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ ad1c] void cv::cpu_baseline::cvt32f16u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ ad8a] void cv::cpu_baseline::cvt16u16s(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ adf8] void cv::cpu_baseline::cvt32f16s(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ ae66] void cv::cpu_baseline::cvt64f16s(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ aed4] void cv::repeat(InputArray, int, int, OutputArray) │ │ + [ af07] maskarr == 0 │ │ + [ af14] findNonZero │ │ + [ af20] NULL storage pointer │ │ + [ af35] cvCreateGraph │ │ + [ af43] getTypeFromD3DFORMAT │ │ + [ af58] type == CV_32FC1 || type == CV_32FC2 || type == CV_64FC1 || type == CV_64FC2 │ │ + [ afa5] dct │ │ + [ afa9] (unsigned)j < (unsigned)n2 │ │ + [ afc4] There can't be more clusters than elements │ │ + [ afef] bool cv::Cholesky(double *, size_t, int, double *, size_t, int) │ │ + [ b02f] src.type() == dst.type() && src.rows == dst.cols && src.cols == dst.rows │ │ + [ b078] cvInvert │ │ + [ b081] load │ │ + [ b086] nn > 0 │ │ + [ b08d] void cv::magnitude(InputArray, InputArray, OutputArray) │ │ + [ b0c5] void cv::log(InputArray, OutputArray) │ │ + [ b0eb] cvCartToPolar │ │ + [ b0f9] void cv::hal::exp64f(const double *, double *, int) │ │ + [ b12d] gemm │ │ + [ b132] scn == m.cols || scn + 1 == m.cols │ │ + [ b155] type == _src2.type() │ │ + [ b16a] data │ │ + [ b16f] cvRange │ │ + [ b177] MatExpr cv::min(const Mat &, const Mat &) │ │ + [ b1a1] MatExpr cv::abs(const Mat &) │ │ + [ b1be] static MatExpr cv::Mat::ones(Size, int) │ │ + [ b1e6] src[i].dims <= 2 && src[i].cols == src[0].cols && src[i].type() == src[0].type() │ │ + [ b237] sortIdx_ │ │ + [ b240] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/matrix_sparse.cpp │ │ + [ b2bb] hdr != 0 │ │ + [ b2c4] hdr && hdr->dims == 3 │ │ + [ b2da] Only 32f and 64f are supported │ │ + [ b2f9] ndim │ │ + [ b2fe] int cv::cpu_baseline::sqsum16u(const ushort *, const uchar *, int *, double *, int, int) │ │ + [ b357] SumSqrFunc cv::getSumSqrFunc(int) │ │ + [ b379] void cv::hal::cpu_baseline::merge16u(const ushort **, ushort *, int, int) │ │ + [ b3c3] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/ocl_disabled.impl.hpp │ │ + [ b442] convertToGLTexture2D │ │ + [ b457] int32 │ │ + [ b45d] float16 │ │ + [ b465] ], dtype='%s') │ │ + [ b474] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/parallel/registry_parallel.impl.hpp │ │ + [ b501] calcStructSize │ │ + [ b510] \n │ │ + [ b523] Can't open archive: ' │ │ + [ b539] Input file is invalid │ │ + [ b54f] !fs_data_ptrs.empty() │ │ + [ b565] type_id │ │ + [ b56d] Map element should have a name │ │ + [ b58c] Invalid filename │ │ + [ b59d] key2 < fs->str_hash_data.size() │ │ + [ b5bd] Unexpected End-Of-File │ │ + [ b5d4] '[' - left-brace of seq is missing │ │ + [ b5f7] idx_k >= 0 │ │ + [ b602] int cv::cpu_baseline::sum64f(const double *, const uchar *, double *, int, int) │ │ + [ b652] Incorrect size of input array │ │ + [ b670] Gpu API call │ │ + [ b67d] AVX512DQ │ │ + [ b686] readSettings │ │ + [ b693] utils::findDataFile(): ... skip, not a valid directory: │ │ + [ b6cc] pImpl->lock() │ │ + [ b6da] unlock │ │ + [ b6e1] libraryRelease │ │ + [ b6f0] DISABLED │ │ + [ b6f9] locale constructed with null │ │ + [ b716] time_put_byname failed to construct for │ │ + [ b73f] moneypunct_byname failed to construct for │ │ + [ b76a] _Z │ │ + [ b76d] covariant return thunk to │ │ + [ b788] basic_ostream │ │ + [ b796] char16_t │ │ + [ b79f] & │ │ + [ b7a1] _Unwind_Resume() can't return │ │ + [ b7bf] r8 │ │ + [ b7c2] r12 │ │ + [ b7c6] d6 │ │ + [ b7c9] d10 │ │ + [ b7cd] The operation is neither 'array op array' (where arrays have the same size and the same type), nor 'array op scalar', nor 'scalar op array' │ │ + [ b859] cvNot │ │ + [ b85f] cvAbsDiff │ │ + [ b869] void cv::hal::cpu_baseline::add8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, int, int) │ │ + [ b8d4] Non-positive width or height │ │ + [ b8f1] Number of channels is not the same for all arrays │ │ + [ b923] cvGetDimSize │ │ + [ b930] cvGetReal1D │ │ + [ b93c] Input array has NULL data pointer │ │ + [ b95e] Unknown object type │ │ + [ b972] _Function.empty()==false │ │ + [ b98b] void cv::cpu_baseline::cvt16f32s(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ b9f9] void cv::cpu_baseline::cvt16f64f(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ ba67] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/convert_c.cpp │ │ + [ bade] i < src.channels() │ │ + [ baf1] size() == mask.size() │ │ + [ bb07] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/cuda_gpu_mat_nd.cpp │ │ + [ bb84] cvSeqSort │ │ + [ bb8e] parent->bottom == block │ │ + [ bba6] innerDownhillSimplex │ │ + [ bbbb] dft │ │ + [ bbbf] generateCentersPP │ │ + [ bbd1] mat.rows == mat.cols && (type == CV_32F || type == CV_64F) │ │ + [ bc0c] cvSolve │ │ + [ bc14] Wrong shape of input matrix! Expected a matrix with one row or column. │ │ + [ bc5b] void cv::patchNaNs(InputOutputArray, double) │ │ + [ bc88] patchNaNs │ │ + [ bc92] cvSolveCubic │ │ + [ bc9f] void cv::cpu_baseline::gemm64f(const double *, size_t, const double *, size_t, double, const double *, size_t, double, double *, size_t, int, int, int, int) │ │ + [ bd3c] cvScaleAdd │ │ + [ bd47] MulTransposedR │ │ + [ bd56] nelems <= (size_t)size.p[0] │ │ + [ bd72] Size cv::getContinuousSize2D(Mat &, Mat &, Mat &, int) │ │ + [ bda9] extractImageCOI │ │ + [ bdb9] virtual void cv::MatOp::divide(double, const MatExpr &, MatExpr &) const │ │ + [ be02] MatExpr cv::Mat::mul(InputArray, double) const │ │ + [ be31] reduce │ │ + [ be38] sort │ │ + [ be3d] flipND: given axis is out of range │ │ + [ be60] void cv::broadcast(InputArray, InputArray, OutputArray) │ │ + [ be98] empty │ │ + [ be9e] !fixedSize() || ((ogl::Buffer*)obj)->size() == _sz │ │ + [ bed1] void cv::hal::cpu_baseline::merge32s(const int **, int *, int, int) │ │ + [ bf15] void cv::merge(const Mat *, size_t, OutputArray) │ │ + [ bf46] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/minmax.cpp │ │ + [ bfba] (size_t)it.size │ │ + [ bfca] setUseOpenVX │ │ + [ bfd7] core(parallel): Disable backend: │ │ + [ bff9] core(parallel): wrong OpenCV major version used by plugin ' │ │ + [ c035] ' in │ │ + [ c03b] The storage is not opened │ │ + [ c055] Some collection type: FileNode::SEQ or FileNode::MAP must be specified │ │ + [ c09c] addNode │ │ + [ c0a4] Sequence element should not have name (use <_>) │ │ + [ c0d8] check_dt │ │ + [ c0e1] iss.eof() │ │ + [ c0eb] The written string is too long │ │ + [ c10a] Attribute value should be put into single or double quotes │ │ + [ c145] Incorrect indentation │ │ + [ c15b] Empty type name │ │ + [ c16b] Complex keys are not supported │ │ + [ c18a] ? │ │ + [ c18c] Input COI is not supported │ │ + [ c1a7] Bad type of mask argument │ │ + [ c1c1] NEON │ │ + [ c1c6] VSX │ │ + [ c1ca] u->data != 0 && "Error mapping of UMat to host memory." │ │ + [ c202] void cv::UMat::copyTo(OutputArray) const │ │ + [ c22b] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/utils/datafile.cpp │ │ + [ c2a7] cv::samples::findFile(' │ │ + [ c2bf] condition_variable::timed wait: mutex not locked │ │ + [ c2f0] %I:%M:%S %p │ │ + [ c2fc] unexpected │ │ + [ c307] std::bad_exception │ │ + [ c31a] libc++abi │ │ + [ c324] operator? │ │ + [ c32e] Ub │ │ + [ c331] allocator │ │ + [ c33b] basic_iostream │ │ + [ c34a] NodeArray (anonymous namespace)::itanium_demangle::AbstractManglingParser<(anonymous namespace)::itanium_demangle::ManglingParser<(anonymous namespace)::DefaultAllocator>, (anonymous namespace)::DefaultAllocator>::popTrailingNodeArray(size_t) [Derived = (anonymous namespace)::itanium_demangle::ManglingParser<(anonymous namespace)::DefaultAllocator>, Alloc = (anonymous namespace)::DefaultAllocator] │ │ + [ c4db] decltype(auto) │ │ + [ c4ea] && │ │ + [ c4ed] ((ttypeEncoding == DW_EH_PE_absptr) || (ttypeEncoding == DW_EH_PE_pcrel) || (ttypeEncoding == (DW_EH_PE_pcrel | DW_EH_PE_indirect))) && "Unexpected TTypeEncoding" │ │ + [ c590] setFloatRegister │ │ + [ c5a1] r9 │ │ + [ c5a4] cv::Algorithm::Algorithm() │ │ + [ c5bf] void cv::bitwise_and(InputArray, InputArray, OutputArray, InputArray) │ │ + [ c605] void cv::divide(double, InputArray, OutputArray, int) │ │ + [ c63b] cvMin │ │ + [ c641] void cv::hal::cpu_baseline::xor8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, int, int) │ │ + [ c6ac] void cv::hal::cpu_baseline::mul16u(const ushort *, size_t, const ushort *, size_t, ushort *, size_t, int, int, const double *) │ │ + [ c72b] void cv::hal::cpu_baseline::addWeighted32s(const int *, size_t, const int *, size_t, int *, size_t, int, int, const double *) │ │ + [ c7a9] void cv::hal::sub64f(const double *, size_t, const double *, size_t, double *, size_t, int, int, void *) │ │ + [ c812] void cv::hal::mul16u(const ushort *, size_t, const ushort *, size_t, ushort *, size_t, int, int, void *) │ │ + [ c87b] void cv::hal::div64f(const double *, size_t, const double *, size_t, double *, size_t, int, int, void *) │ │ + [ c8e4] _dst.data == data0 │ │ + [ c8f7] Invalid sparse matrix header │ │ + [ c914] cvSetReal* support only single-channel arrays │ │ + [ c942] cvGetMatND │ │ + [ c94d] !has_result │ │ + [ c959] [x= │ │ + [ c95d] 0 <= coi && coi < dcn && scn == 1 │ │ + [ c97f] setTermCriteria │ │ + [ c98f] void cv::cpu_baseline::cvt16s8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ c9fc] cn <= 4 │ │ + [ ca04] sz <= sizeof(scalar) │ │ + [ ca19] 0 <= roi.x && 0 <= roi.width && roi.x + roi.width <= m.cols && 0 <= roi.y && 0 <= roi.height && roi.y + roi.height <= m.rows │ │ + [ ca96] (size_t)ptr % CV_STRUCT_ALIGN == 0 │ │ + [ cab9] writer->block->count > 0 │ │ + [ cad2] cvReleaseGraphScanner │ │ + [ cae8] ihi != inhi │ │ + [ caf4] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/glob.cpp │ │ + [ cb66] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/lda.cpp │ │ + [ cbd7] sortMatrixColumnsByIndices │ │ + [ cbf2] int cv::solveLP(InputArray, InputArray, OutputArray, double) │ │ + [ cc2f] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/mathfuncs_core.dispatch.cpp │ │ + [ ccb4] a_size.width == len │ │ + [ ccc8] TransformFunc cv::getDiagTransformFunc(int) │ │ + [ ccf4] total │ │ + [ ccfa] Input and output arrays must have the same number of channels │ │ + [ cd38] virtual int cv::MatOp::type(const MatExpr &) const │ │ + [ cd6b] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/matrix_operations.cpp │ │ + [ cdea] void cv::setIdentity(InputOutputArray, const Scalar &) │ │ + [ ce21] _sizes[i] > 0 │ │ + [ ce2f] norm │ │ + [ ce34] void cv::transposeND(InputArray, const std::vector &, OutputArray) │ │ + [ ce7c] broadcast: input array must be single channel │ │ + [ ceaa] getGpuMat │ │ + [ ceb4] sizend │ │ + [ cebb] i >= 0 && (size_t)i < vv.size() │ │ + [ cedb] !fixedSize() || len == ((std::vector*)v)->size() / esz │ │ + [ cf19] getGpuMatRef │ │ + [ cf26] void reduceMinMax(cv::InputArray, cv::OutputArray, ReduceMode, int) │ │ + [ cf6a] double cv::norm(InputArray, int, InputArray) │ │ + [ cf97] cn >= 1 && cn <= 4 │ │ + [ cfaa] TBB │ │ + [ cfae] core(parallel): fallback on builtin code │ │ + [ cfd7] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/pca.cpp │ │ + [ d048] !mean.empty() && !eigenvectors.empty() && ((mean.rows == 1 && eigenvectors.rows == data.cols) || (mean.cols == 1 && eigenvectors.rows == data.rows)) │ │ + [ d0dd] }\n │ │ + [ d0e0] .json │ │ + [ d0e6] !write_stack.empty() │ │ + [ d0fb] Null data pointer │ │ + [ d10d] ptr >= bufferstart && ptr <= bufferEnd() │ │ + [ d136] setBufferPtr │ │ + [ d143] Bad format of floating-point constant │ │ + [ d169] blockIdx == fs_data_ptrs.size() - 1 │ │ + [ d18d] getDefaultObjectName │ │ + [ d1a2] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/persistence_impl.hpp │ │ + [ d220] Unexpected end of line │ │ + [ d237] fs != 0 │ │ + [ d23f] opencv_storage │ │ + [ d24e] Attribute name should be followed by '=' │ │ + [ d277] Inplace operation is not supported │ │ + [ d29a] Unknown %s code %d │ │ + [ d2ad] pthread_key_create(&tlsKey, opencv_tls_destructor) == 0 │ │ + [ d2e5] MMX │ │ + [ d2e9] releaseSlot │ │ + [ d2f5] Invalid value for parameter │ │ + [ d312] Trace: Total events: │ │ + [ d328] parallelForSetRootRegion │ │ + [ d341] ... Line %d: trying open '%s' │ │ + [ d35f] utils::findDataFile(): can't find data file via │ │ + [ d390] /proc/cpuinfo │ │ + [ d39e] std::bad_alloc │ │ + [ d3ad] out/llvm-project/libcxxabi/src/demangle/ItaniumDemangle.h │ │ + [ d3e7] operator. │ │ + [ d3f1] __int128 │ │ + [ d3fa] Last != First && "Popping empty vector!" │ │ + [ d423] decimal64 │ │ + [ d42d] reinterpret_cast(p + 1) % RequiredAlignment == 0 │ │ + [ d466] unwind_phase2 │ │ + [ d474] d9 │ │ + [ d477] d15 │ │ + [ d47b] d16 │ │ + [ d47f] void cv::multiply(InputArray, InputArray, OutputArray, double, int) │ │ + [ d4c3] void cv::hal::cpu_baseline::cmp32f(const float *, size_t, const float *, size_t, uchar *, size_t, int, int, int) │ │ + [ d534] void cv::hal::cpu_baseline::mul16s(const short *, size_t, const short *, size_t, short *, size_t, int, int, const double *) │ │ + [ d5b0] void cv::hal::min32f(const float *, size_t, const float *, size_t, float *, size_t, int, int, void *) │ │ + [ d616] void cv::hal::absdiff8s(const schar *, size_t, const schar *, size_t, schar *, size_t, int, int, void *) │ │ + [ d67f] void cv::hal::addWeighted8s(const schar *, size_t, const schar *, size_t, schar *, size_t, int, int, void *) │ │ + [ d6ec] Iterator with mask is not supported │ │ + [ d710] iterator != 0 │ │ + [ d71e] None of array parameters is changed: dummy call? │ │ + [ d74f] cvResetImageROI │ │ + [ d75f] cvGetImageROI │ │ + [ d76d] Accuracy flag is set and epsilon is < 0 │ │ + [ d795] setValue │ │ + [ d79e] !nidx.empty() │ │ + [ d7ac] ' │ │ + [ d7b2] greater than │ │ + [ d7bf] void cv::hal::cpu_baseline::addRNGBias64f(double *, const double *, int) │ │ + [ d808] convertTo │ │ + [ d812] void cv::cpu_baseline::cvt32s64f(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ d880] dims > 0 && dims < CV_MAX_DIM │ │ + [ d89e] copyMakeBorder │ │ + [ d8ad] src.channels() == dst.channels() │ │ + [ d8ce] GpuMat │ │ + [ d8d5] createGpuMatHeader │ │ + [ d8e8] NULL sequence pointer │ │ + [ d8fe] cvSetRemove │ │ + [ d90a] vertex pointers coincide (or set to NULL) │ │ + [ d934] createInitialSimplex │ │ + [ d949] !((flags & DFT_COMPLEX_INPUT) && src.channels() != 2) │ │ + [ d97f] srcA.size == dst.size && srcA.type() == dst.type() │ │ + [ d9b2] cvDCT │ │ + [ d9b8] The function can not solve under-determined linear systems │ │ + [ d9f3] rhs.data == 0 || (rhs.type() == type && rhs.rows == m) │ │ + [ da2a] void cv::hal::cpu_baseline::invSqrt32f(const float *, float *, int) │ │ + [ da6e] src1.size == src2.size │ │ + [ da85] dst.rows == data.rows │ │ + [ da9b] double cv::dotProd_8s(const schar *, const schar *, int) │ │ + [ dad4] (int)ranges.size() == d │ │ + [ daec] m1.dims │ │ + [ daf4] is_m2_vector │ │ + [ db01] src.size() == idx.size() && idx.type() == CV_32S && src.data != idx.data │ │ + [ db4a] static MatExpr cv::Mat::ones(int, int, int) │ │ + [ db76] void cv::vconcat(InputArray, OutputArray) │ │ + [ dba0] sortIdx │ │ + [ dba8] 0 <= i && i < sz.height │ │ + [ dbc0] create() called for the missing output array │ │ + [ dbed] SumSqrFunc cv::cpu_baseline::getSumSqrFunc(int) │ │ + [ dc1d] void cv::hal::cpu_baseline::merge8u(const uchar **, uchar *, int, int) │ │ + [ dc64] merge │ │ + [ dc6a] Unsupported matrix type. │ │ + [ dc83] %d.0 │ │ + [ dc88] mode │ │ + [ dc8e] \n │ │ + [ dcb3] unlock() │ │ + [ df3b] SILENT │ │ + [ df42] /sys/devices/system/cpu/possible │ │ + [ df63] ios_base::clear │ │ + [ df73] a+e │ │ + [ df77] terminating due to %s exception of type %s │ │ + [ dfa2] _block_invoke │ │ + [ dfb0] virtual thunk to │ │ + [ dfc2] operator co_await │ │ + [ dfd4] vE │ │ + [ dfd7] Last != First && "Calling back() on empty vector!" │ │ + [ e00a] s22 │ │ + [ e00e] d19 │ │ + [ e012] OPENCV_ENABLE_MEMALIGN │ │ + [ e029] void cv::min(InputArray, InputArray, OutputArray) │ │ + [ e05b] void cv::hal::cpu_baseline::add16u(const ushort *, size_t, const ushort *, size_t, ushort *, size_t, int, int) │ │ + [ e0ca] void cv::hal::cpu_baseline::absdiff16u(const ushort *, size_t, const ushort *, size_t, ushort *, size_t, int, int) │ │ + [ e13d] void cv::hal::cpu_baseline::div8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, int, int, const double *) │ │ + [ e1b8] void cv::hal::cmp8s(const schar *, size_t, const schar *, size_t, uchar *, size_t, int, int, void *) │ │ + [ e21d] void cv::hal::cmp32f(const float *, size_t, const float *, size_t, uchar *, size_t, int, int, void *) │ │ + [ e283] Either all the pointers should be null or they all should be non-null │ │ + [ e2c9] cvSetIPLAllocators │ │ + [ e2dc] NULL pointer │ │ + [ e2f1] one of dimension sizes is non-positive │ │ + [ e318] cvGetCols │ │ + [ e322] cvGet2D │ │ + [ e32a] timeoutNs < 0 │ │ + [ e338] The combination of type=%d, dtype=%d and normType=%d is not supported │ │ + [ e37e] commit │ │ + [ e385] (expected: ' │ │ + [ e393] >= │ │ + [ e396] Field KEYS could not be empty\n │ │ + [ e3b5] void cv::cpu_baseline::cvt8s8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ e421] void cv::cpu_baseline::cvt32s8u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ e48e] void cv::cpu_baseline::cvt16f32f(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ e4fc] dvec[j].channels() == 1 │ │ + [ e514] borderInterpolate │ │ + [ e526] cvClearMemStorage │ │ + [ e538] cvStartWriteSeq │ │ + [ e548] cvSeqInsert │ │ + [ e554] Source and destination sequence element sizes are different. │ │ + [ e591] Null graph scanner │ │ + [ e5a4] counters[k] != 0 │ │ + [ e5b5] A.type() == x.type() && A.cols == x.rows && x.cols == b.cols │ │ + [ e5f2] subspaceProject │ │ + [ e602] ctype == CV_32F || ctype == CV_64F │ │ + [ e625] a_size.height == len │ │ + [ e63a] type == CV_64FC2 │ │ + [ e64b] data[i].size() == size │ │ + [ e662] delta.channels() == 1 │ │ + [ e678] (D.cols == ((flags & 2) == 0 ? B.cols : B.rows)) │ │ + [ e6a9] delta_cols == 1 │ │ + [ e6b9] m.dims <= 2 │ │ + [ e6c5] locateROI │ │ + [ e6cf] total_sz │ │ + [ e6d8] getContinuousSize2D │ │ + [ e6ec] src.size() == dst.size() && src.type() == dst.type() │ │ + [ e721] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/matrix_expressions.cpp │ │ + [ e7a1] virtual void cv::MatOp_T::transpose(const MatExpr &, MatExpr &) const │ │ + [ e7e7] narrays <= 1000 │ │ + [ e7f7] pos │ │ + [ e7fb] completeSymm │ │ + [ e808] hdr │ │ + [ e80c] it.ptr │ │ + [ e813] Unknown/unsupported norm type │ │ + [ e831] CV_MAT_TYPE(mtype) == m.type() │ │ + [ e850] int cv::cpu_baseline::sqsum16s(const short *, const uchar *, int *, double *, int, int) │ │ + [ e8a8] PSNR │ │ + [ e8ad] setColorArray │ │ + [ e8bb] rbe │ │ + [ e8bf] (priority= │ │ + [ e8cb] core(parallel): exception during plugin loading: │ │ + [ e8fd] %.4e │ │ + [ e902] %.8e │ │ + [ e907] getsFromFile │ │ + [ e914] maxCount < MAX_BLOCK_SIZE │ │ + [ e92e] binary │ │ + [ e935] symbolToType │ │ + [ e942] Key must start with '"' │ │ + [ e95a] Key must end with '"' │ │ + [ e970] , (anonymous namespace)::DefaultAllocator>::ScopedTemplateParamList::~ScopedTemplateParamList() [Derived = (anonymous namespace)::itanium_demangle::ManglingParser<(anonymous namespace)::DefaultAllocator>, Alloc = (anonymous namespace)::DefaultAllocator] │ │ + [ ecd9] out/llvm-project/libcxxabi/src/demangle/StringView.h │ │ + [ ed0e] basic_istream │ │ + [ ed1c] long double │ │ + [ ed28] index inlined table detected but pr function requires extra words │ │ + [ ed6a] r6 │ │ + [ ed6d] s2 │ │ + [ ed70] s9 │ │ + [ ed73] s18 │ │ + [ ed77] void cv::hal::cpu_baseline::cmp16u(const ushort *, size_t, const ushort *, size_t, uchar *, size_t, int, int, int) │ │ + [ edea] void cv::hal::cpu_baseline::addWeighted32f(const float *, size_t, const float *, size_t, float *, size_t, int, int, const double *) │ │ + [ ee6e] void cv::hal::div16u(const ushort *, size_t, const ushort *, size_t, ushort *, size_t, int, int, void *) │ │ + [ eed7] void cv::hal::recip64f(const double *, size_t, const double *, size_t, double *, size_t, int, int, void *) │ │ + [ ef42] Data type is not the same for all arrays │ │ + [ ef6b] The total width is not divisible by the new number of channels │ │ + [ efaa] Bad input origin │ │ + [ efbb] Iterations flag is set and maximum number of iterations is <= 0 │ │ + [ effb] static_cast(*ptr) + type_size * count <= static_cast(raw_mem) + type_size * allocated_count │ │ + [ f067] vector │ │ + [ f06e] j < nsrcs && src[j].depth() == depth │ │ + [ f093] ' │ │ + [ f095] %s │ │ + [ f099] x_mat.type()==CV_64FC1 │ │ + [ f0b0] void cv::cpu_baseline::cvt64f16u(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ f11e] void cv::cpu_baseline::cvt8s64f(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ f18b] void cv::cpu_baseline::cvt64f16f(const uchar *, size_t, const uchar *, size_t, uchar *, size_t, Size, void *) │ │ + [ f1f9] nz > 0 │ │ + [ f200] src.size == dst.size && dst.type() == CV_8UC(src.channels()) │ │ + [ f23d] cvSetSeqReaderPos │ │ + [ f24f] set != NULL │ │ + [ f25b] seq->first->start_index == 0 │ │ + [ f278] icvFreeSeqBlock │ │ + [ f288] seq->ptr == block->data │ │ + [ f2a0] termcrit.type == (TermCriteria::MAX_ITER + TermCriteria::EPS) && termcrit.epsilon > 0 && termcrit.maxCount > 0 │ │ + [ f30f] kmeans: can't update cluster center (check input for huge or NaN values) │ │ + [ f358] compute │ │ + [ f360] The data is expected as InputArray::STD_VECTOR_MAT (a std::vector) or _InputArray::STD_VECTOR_VECTOR (a std::vector< std::vector<...> >). │ │ + [ f3ef] (Func_.rows()==1 && (Constr_.cols()-Func_.cols()==1))|| (Func_.cols()==1 && (Constr_.cols()-Func_.rows()==1)) │ │ + [ f45d] void cv::phase(InputArray, InputArray, OutputArray, bool) │ │ + [ f497] CV_MAT_DEPTH(ctype) >= CV_32F && CV_MAT_CN(ctype) <= 2 │ │ + [ f4ce] void cv::hal::gemm64fc(const double *, size_t, const double *, size_t, double, const double *, size_t, double, double *, size_t, int, int, int, int) │ │ + [ f563] (*each).type() == type │ │ + [ f57a] double cv::Mahalanobis(InputArray, InputArray, InputArray) │ │ + [ f5b5] dims <= 2 │ │ + [ f5bf] Pushed vector type is not the same as matrix type │ │ + [ f5f1] dims <= 2 && step[0] > 0 │ │ + [ f60a] empty() │ │ + [ f612] cvIplImage │ │ + [ f61d] img->dataOrder == IPL_DATA_ORDER_PIXEL || img->roi->coi != 0 │ │ + [ f65a] virtual void cv::MatOp_Bin::divide(double, const MatExpr &, MatExpr &) const │ │ + [ f6a7] virtual void cv::MatOp_T::multiply(const MatExpr &, double, MatExpr &) const │ │ + [ f6f4] MatExpr cv::Mat::t() const │ │ + [ f70f] _m.dims() <= 2 │ │ + [ f71e] void cv::completeSymm(InputOutputArray, bool) │ │ + [ f74c] hdr && hdr->dims == 1 │ │ + [ f762] broadcast: input array must be contiguous │ │ + [ f78c] broadcast: not supported data type │ │ + [ f7af] i < (int)vv.size() │ │ + [ f7c2] mv && n > 0 │ │ + [ f7ce] _src1.type() == _src2.type() │ │ + [ f7eb] /home/vagrant/build/com.buzbuz.smartautoclicker/core/smart/detection/src/release/opencv/modules/core/src/ovx.cpp │ │ + [ f85c] core(parallel): exception during plugin initialization: │ │ + [ f895] ParallelBackendRegistry │ │ + [ f8ad] core(parallel): trying backend: │ │ + [ f8ce] fs.isOpened() │ │ + [ f8dc] decodeFormat │ │ + [ f8e9] NULL or empty filename │ │ + [ f900] startNextStream │ │ + [ f910] readRaw │ │ + [ f918] make_base64_header │ │ + [ f92b] ']' - right-brace of seq is missing │ │ + [ f94f] sizes │ │ + [ f955] nelems == m.total()*m.channels() │ │ + [ f976] Directive tags are not allowed here │ │ + [ f99a] OPENCV_DUMP_CONFIG │ │ [ f9ae] Required baseline features:\n │ │ [ f9cb] SSE │ │ [ f9cf] FP16 │ │ [ f9d4] AVX512BW │ │ [ f9dd] AVX512VBMI │ │ [ f9e8] Unknown feature │ │ [ f9f8] cv::error() │ ├── objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {} │ │ @@ -741,15 +741,15 @@ │ │ ldr r0, [sp, #16] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strb r0, [r6, #19] │ │ movs r1, r3 │ │ ldr r6, [pc, #264] @ (a9460 ) │ │ movs r1, r3 │ │ - adds r7, #2 │ │ + str r6, [r7, r5] │ │ @ instruction: 0xfffebb5f │ │ vtbx.8 d24, {d13}, d28 │ │ @ instruction: 0xfffe6c9d │ │ @ instruction: 0xfffebb39 │ │ vtbx.8 d24, {d13}, d6 │ │ vcvt.f16.u16 q11, , #2 │ │ @ instruction: 0xfffe4dfc │ │ @@ -795,15 +795,15 @@ │ │ b.n a9390 │ │ mov r0, r5 │ │ blx 2307d0 <__emutls_get_address@@Base+0x3948> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strb r0, [r2, #15] │ │ movs r1, r3 │ │ - adds r6, #8 │ │ + str r4, [r0, r2] │ │ Address 0xa93ee is out of bounds. │ │ │ │ │ │ 000a93f0 : │ │ b.w 2300cc <__emutls_get_address@@Base+0x3244> │ │ │ │ 000a93f4 : │ │ @@ -846,15 +846,15 @@ │ │ b.n a940c │ │ mov r0, r5 │ │ blx 2307d0 <__emutls_get_address@@Base+0x3948> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strb r4, [r2, #13] │ │ movs r1, r3 │ │ - adds r5, #140 @ 0x8c │ │ + str r0, [r1, r0] │ │ vzip. d31, d6 │ │ bkpt 0x001c │ │ ldr r0, [r0, #4] │ │ dmb ish │ │ asrs r1, r0, #31 │ │ bx lr │ │ ldr r0, [r0, #8] │ │ @@ -910,15 +910,15 @@ │ │ blx 2307d0 <__emutls_get_address@@Base+0x3948> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strb r0, [r4, #10] │ │ movs r1, r3 │ │ stmia r2!, {r1, r6} │ │ movs r0, r3 │ │ - adds r4, #248 @ 0xf8 │ │ + ldr r7, [pc, #464] @ (a96d8 ) │ │ Address 0xa9506 is out of bounds. │ │ │ │ │ │ 000a9508 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -1557,16 +1557,16 @@ │ │ bhi.n a9b9c │ │ ldr r4, [sp, #44] @ 0x2c │ │ adds r4, #1 │ │ add r0, sp, #60 @ 0x3c │ │ blx 230920 <__emutls_get_address@@Base+0x3a98> │ │ b.n a9b8c │ │ strh r2, [r4, #56] @ 0x38 │ │ - @ instruction: 0xfffdee06 │ │ - vabs.s d24, d1 │ │ + vtbl.8 d16, {d29}, d2 │ │ + vshll.i q12, d1, # │ │ vtbl.8 d25, {d14-d15}, d14 │ │ mvn.w r0, #2147483648 @ 0x80000000 │ │ blx 22ca04 <__cxa_call_unexpected@@Base+0x510> │ │ mov r9, r0 │ │ cmp.w sl, #0 │ │ bne.n a9b56 │ │ cmp r9, r8 │ │ @@ -1974,26 +1974,26 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r0, [sp, #272] @ 0x110 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldr r3, [pc, #0] @ (aa040 ) │ │ movs r1, r3 │ │ - b.n a9e00 │ │ - vqshl.u32 d30, d2, #29 │ │ - vdup.8 d23, d13[6] │ │ - @ instruction: 0xfffecb74 │ │ - vqshlu.s64 q15, q8, #61 @ 0x3d │ │ - vtbx.8 d23, {d29- d16, d14 │ │ + vdup.16 d23, d13[3] │ │ + vsli.64 q15, q8, #62 @ 0x3e │ │ + vceq.i q8, q14, #0 │ │ + vtbx.8 d23, {d30-, #2 │ │ - vqshl.u32 q15, q3, #29 │ │ - vcvt.f16.u16 , , #3 │ │ - vabdl.u q15, d14, d2 │ │ - vqshl.u32 d30, d22, #29 │ │ - vcvt.f16.u16 d23, d17, #3 │ │ + vsra.u64 q8, q1, #3 │ │ + vcvt.f16.u16 , , #2 │ │ + vsra.u32 q8, q15, #2 │ │ + vsra.u64 d16, d18, #2 │ │ + vcvt.f16.u16 d23, d17, #2 │ │ vrshr.u32 d20, d20, #2 │ │ movs r1, r3 │ │ │ │ 000aa074 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -3434,16 +3434,16 @@ │ │ cmp.w r0, #65536 @ 0x10000 │ │ bne.n aaf3c │ │ ldr r1, [r4, #4] │ │ add.w r0, sp, #1240 @ 0x4d8 │ │ blx 230890 <__emutls_get_address@@Base+0x3a08> │ │ b.n aaf4a │ │ nop │ │ - bge.n ab00c │ │ - vcvt.f16.u16 , q3, #3 │ │ + bl ffd93f2e <__cxa_new_handler@@Base+0xffb5033e> │ │ + ldrb r6, [r2, #17] │ │ vcvt.u32.f32 q11, , #2 │ │ vabal.u , d14, d13 │ │ str r3, [r3, #8] │ │ mov r1, r4 │ │ mov.w r2, #4294967295 @ 0xffffffff │ │ blx 2308a0 <__emutls_get_address@@Base+0x3a18> │ │ mov.w r1, #1032 @ 0x408 │ │ @@ -4361,21 +4361,21 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r0, [sp, #208] @ 0xd0 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldmia r2, {r1, r2, r3, r5} │ │ vsra.u32 d23, d14, #2 │ │ vsri.32 d22, d9, #2 │ │ - vtbl.8 d29, {d14-d17}, d22 │ │ + vabal.u , d30, d18 │ │ vshr.u64 d23, d20, #3 │ │ vsubw.u q11, q15, d31 │ │ @ instruction: 0xfffedb13 │ │ vshr.u64 , q13, #2 │ │ vrsra.u64 q11, , #2 │ │ - @ instruction: 0xfffecea4 │ │ + vtbl.8 d30, {d14-d15}, d16 │ │ vshr.u64 , q4, #3 │ │ vrsra.u64 q11, , #2 │ │ vtbl.8 d18, {d30-d31}, d26 │ │ movs r1, r3 │ │ │ │ 000ab8a8 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -5684,25 +5684,25 @@ │ │ @ instruction: 0xfffddb96 │ │ vrsubhn.i d21, q15, │ │ vtbx.8 d20, {d14}, d25 │ │ @ instruction: 0xfffedb74 │ │ vmlsl.u , d14, d29[0] │ │ vcvt.f16.u16 d17, d8, #2 │ │ movs r1, r3 │ │ - bgt.n ac712 │ │ - vtbl.8 d29, {d13-d16}, d16 │ │ + bl fff6868e <__cxa_new_handler@@Base+0xffd24a9e> │ │ + blt.n ac6d8 │ │ vqshlu.s32 d21, d9, #30 │ │ - vshr.u64 q14, , #2 │ │ + @ instruction: 0xfffedb79 │ │ @ instruction: 0xfffddb52 │ │ vmlsl.u , d14, d11[0] │ │ vmls.i , q15, d18[0] │ │ movs r0, r3 │ │ - add r5, pc, #456 @ (adr r5, ac878 ) │ │ + itee al │ │ @ instruction: 0xfffddafc │ │ - vsli.64 , , #62 @ 0x3e │ │ + vsli.64 , , #62 @ 0x3e │ │ Address 0xac6b6 is out of bounds. │ │ │ │ │ │ 000ac6b8 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -6774,15 +6774,15 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #116 @ 0x74 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ lsrs r6, r7, #28 │ │ movs r1, r3 │ │ ldr r2, [pc, #16] @ (ad290 ) │ │ - vqrdmlsh.s q14, q15, d21[0] │ │ + vtbx.8 d30, {d14-d16}, d17 │ │ vqshrn.u64 d20, , #3 │ │ vsli.64 d24, d14, #62 @ 0x3e │ │ movs r0, r3 │ │ lsrs r0, r6, #27 │ │ movs r1, r3 │ │ lsrs r0, r3, #26 │ │ movs r1, r3 │ │ @@ -7457,15 +7457,15 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r0, sp, #256 @ 0x100 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ lsrs r0, r0, #3 │ │ movs r1, r3 │ │ orrs r0, r2 │ │ - vtbl.8 d27, {d30-d31}, d31 │ │ + vraddhn.i d29, q7, │ │ vclt.s q10, , #0 │ │ @ instruction: 0xfffe7ebc │ │ movs r0, r3 │ │ lsls r4, r6, #31 │ │ movs r1, r3 │ │ lsls r4, r4, #30 │ │ movs r1, r3 │ │ @@ -7630,15 +7630,15 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r0, sp, #256 @ 0x100 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ lsls r4, r6, #27 │ │ movs r1, r3 │ │ adcs r4, r0 │ │ - @ instruction: 0xfffe8ff6 │ │ + @ instruction: 0xfffeaa72 │ │ vshr.u32 q10, , #3 │ │ @ instruction: 0xfffe7d04 │ │ movs r0, r3 │ │ lsls r4, r5, #24 │ │ movs r1, r3 │ │ lsls r0, r3, #23 │ │ movs r1, r3 │ │ @@ -8778,15 +8778,15 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #196 @ 0xc4 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #252 @ 0xfc │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ mls r0, r8, r8, r0 │ │ - ldr r7, [sp, #244] @ 0xf4 │ │ + cbnz r1, ae7a2 │ │ vtbl.8 d21, {d13-d16}, d25 │ │ vmls.i , q7, d23[0] │ │ vqmovun.s d23, q2 │ │ movs r0, r3 │ │ subs r6, r1, #3 │ │ movs r1, r3 │ │ vst1.8 @ instruction: 0xf9c40018 │ │ @@ -9065,15 +9065,15 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #188 @ 0xbc │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ @ instruction: 0xf77a0018 │ │ ldrsb r0, [r7, r7] │ │ - vtbl.8 d27, {d14}, d9 │ │ + vqmovn.s d29, │ │ vsra.u32 , , #3 │ │ @ instruction: 0xfffe6e82 │ │ movs r0, r3 │ │ subs r0, r0, r4 │ │ movs r1, r3 │ │ @ instruction: 0xf6b60018 │ │ │ │ @@ -9787,15 +9787,15 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ b.n af1ca │ │ add r0, sp, #124 @ 0x7c │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ vshr.s32 d0, d8, #22 │ │ str r2, [r7, r1] │ │ - vqrdmlah.s , q7, d23[0] │ │ + vtbx.8 d29, {d30}, d19 │ │ @ instruction: 0xfffd29df │ │ vcvt.u32.f32 d30, d24, #2 │ │ movs r0, r3 │ │ │ │ 000af1e8 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -11985,15 +11985,15 @@ │ │ b.n b0a02 │ │ add r0, sp, #20 │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bl a8d68 │ │ blt.n b0a70 │ │ movs r0, r3 │ │ - str r4, [r1, #80] @ 0x50 │ │ + ldrb r0, [r1, #30] │ │ @ instruction: 0xfffd9990 │ │ vqmovn.s d17, q2 │ │ vmlsl.u , d30, d30[0] │ │ movs r0, r3 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -12434,15 +12434,15 @@ │ │ b.n b0ec6 │ │ add r0, sp, #20 │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bl a8d68 │ │ bvs.n b0fac │ │ movs r0, r3 │ │ - str r0, [r1, #4] │ │ + ldrb r4, [r0, #11] │ │ vcge.f , q6, #0 │ │ vqrdmulh.s q8, q15, d0[0] │ │ vmovn.i d29, q13 │ │ movs r0, r3 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -13093,15 +13093,15 @@ │ │ add r0, sp, #44 @ 0x2c │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bl a8d68 │ │ nop │ │ bne.n b156c │ │ movs r0, r3 │ │ - ldr r2, [r0, r4] │ │ + strb r6, [r7, #13] │ │ @ instruction: 0xfffd8d86 │ │ vqshlu.s32 q8, q13, #30 │ │ vtbx.8 d28, {d30- │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bl a8d68 │ │ nop │ │ ldmia r2, {r1, r2, r3, r4, r6} │ │ movs r0, r3 │ │ - str r2, [r7, r6] │ │ + ldr r6, [r6, #64] @ 0x40 │ │ vqshlu.s32 d24, d30, #29 │ │ vcvt.u32.f32 d31, d18, #2 │ │ vrsra.u64 d28, d12, #3 │ │ movs r0, r3 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -14416,15 +14416,15 @@ │ │ b.n b24a6 │ │ add r0, sp, #44 @ 0x2c │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bl a8d68 │ │ stmia r3!, {r1, r2, r4} │ │ movs r0, r3 │ │ - ldr r2, [pc, #416] @ (b265c ) │ │ + str r4, [r4, #76] @ 0x4c │ │ vqrdmlah.s , , d28[0] │ │ @ instruction: 0xfffef7e0 │ │ vdup.8 , d10[6] │ │ movs r0, r3 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -15109,15 +15109,15 @@ │ │ b.n b2c1a │ │ add r0, sp, #44 @ 0x2c │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bl a8d68 │ │ cbnz r6, b2c9c │ │ movs r0, r3 │ │ - cmn r4, r6 │ │ + ldrb r0, [r6, r5] │ │ vqshl.u32 , q12, #29 │ │ vmla.i , q7, d28[0] │ │ vsri.64 , q3, #3 │ │ movs r0, r3 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -15529,15 +15529,15 @@ │ │ b.n b30c6 │ │ add r0, sp, #68 @ 0x44 │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bl a8d68 │ │ push {r1, r4, r6} │ │ movs r0, r3 │ │ - subs r6, #72 @ 0x48 │ │ + ldr r4, [r0, r3] │ │ vqrdmlsh.s q8, , d24[0] │ │ vtbx.8 d30, {d29- d27, d26, #0 │ │ movs r0, r3 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -26300,16 +26300,16 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ subs r6, #130 @ 0x82 │ │ movs r0, r3 │ │ - cmp r1, #203 @ 0xcb │ │ - vtbl.8 d18, {d13-d15}, d5 │ │ + add r7, r8 │ │ + vcge.f d20, d1, #0 │ │ vcgt.f d23, d23, #0 │ │ vqshl.u64 d22, d24, #60 @ 0x3c │ │ movs r0, r3 │ │ subs r6, #70 @ 0x46 │ │ movs r0, r3 │ │ │ │ 000ba2c0 : │ │ @@ -26412,17 +26412,17 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ subs r5, #198 @ 0xc6 │ │ movs r0, r3 │ │ - vmaxnm.f16 , q13, q14 │ │ - @ instruction: 0xfff1fffd │ │ - strb r5, [r4, #12] │ │ + adds r6, r2, r6 │ │ + @ instruction: 0xfffdfff1 │ │ + vabs.s d23, d21 │ │ vtbx.8 d22, {d12-d14}, d22 │ │ vqrdmlsh.s , , d15[0] │ │ vabs.s d23, d3 │ │ vqrdmulh.s , q6, d8[0] │ │ movs r0, r3 │ │ │ │ 000ba3f0 : │ │ @@ -26859,24 +26859,24 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ subs r1, #110 @ 0x6e │ │ movs r0, r3 │ │ - stc 15, cr15, [r9, #-1008] @ 0xfffffc10 │ │ - stmia r6!, {r1, r4, r6, r7} │ │ + lsls r5, r0, #30 │ │ + vceq.i q15, q7, #0 │ │ @ instruction: 0xfffc6e8f │ │ vsli.64 d27, d31, #60 @ 0x3c │ │ - vqshlu.s64 d28, d16, #61 @ 0x3d │ │ + vceq.i d30, d28, #0 │ │ vqrdmlah.s q11, q6, d29[0] │ │ @ instruction: 0xfffc38b2 │ │ movs r0, r3 │ │ - stcl 15, cr15, [pc, #-1008]! @ ba49c │ │ - stmia r7!, {r3, r4, r5} │ │ + lsls r3, r5, #31 │ │ + vsra.u64 d30, d20, #3 │ │ @ instruction: 0xfffc6ef5 │ │ Address 0xba892 is out of bounds. │ │ │ │ │ │ 000ba894 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -26983,19 +26983,19 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ subs r0, #10 │ │ movs r0, r3 │ │ - @ instruction: 0xebe1fffc │ │ - ldr r1, [r4, r2] │ │ + lsls r5, r3, #25 │ │ + vtbl.8 d21, {d29}, d17 │ │ vqrdmulh.s q11, , d23[0] │ │ - @ instruction: 0xfffcebbf │ │ - vqrshrun.s64 d21, , #4 │ │ + vqshlu.s32 d16, d27, #28 │ │ + vqrshrun.s64 d21, , #3 │ │ vqrdmulh.s q11, , d5[0] │ │ vqshl.u64 d19, d10, #60 @ 0x3c │ │ movs r0, r3 │ │ │ │ 000ba9ac : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -27242,26 +27242,26 @@ │ │ movs r0, r3 │ │ strb r4, [r2, #13] │ │ @ instruction: 0xfffd6b92 │ │ @ instruction: 0xfffc6b1d │ │ @ instruction: 0xfffc734d │ │ @ instruction: 0xfffd6b70 │ │ @ instruction: 0xfffc6afb │ │ - vshr.u64 q9, q3, #4 │ │ + @ instruction: 0xfffc3b52 │ │ vtbx.8 d22, {d13-d16}, d14 │ │ @ instruction: 0xfffc6ad9 │ │ vshr.u64 , q6, #4 │ │ vtbl.8 d22, {d14-d17}, d28 │ │ @ instruction: 0xfffc6ab7 │ │ vabal.u , d28, d6 │ │ movs r0, r3 │ │ - movs r1, #117 @ 0x75 │ │ + subs r3, #241 @ 0xf1 │ │ @ instruction: 0xfffd6bd8 │ │ vtbx.8 d22, {d12-d15}, d19 │ │ - @ instruction: 0xfffcce8d │ │ + vtbl.8 d30, {d12-d13}, d9 │ │ @ instruction: 0xfffc6bb6 │ │ vtbx.8 d22, {d12-d15}, d1 │ │ Address 0xbac72 is out of bounds. │ │ │ │ │ │ 000bac74 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -27607,15 +27607,15 @@ │ │ vneg.f d22, d17 │ │ vtbx.8 d24, {d12-d13}, d6 │ │ vsli.32 d30, d20, #29 │ │ vqshl.u32 q11, , #29 │ │ @ instruction: 0xfffc2da2 │ │ @ instruction: 0xfffeaedd │ │ vqshl.u32 q11, , #29 │ │ - vrsra.u32 d16, d28, #4 │ │ + @ instruction: 0xfffc1db8 │ │ vsli.32 d30, d2, #29 │ │ vqshl.u32 d22, d23, #29 │ │ @ instruction: 0xfffc31c6 │ │ movs r0, r3 │ │ │ │ 000bb00c : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -28013,34 +28013,34 @@ │ │ movs r0, r3 │ │ add r2, sp, #756 @ 0x2f4 │ │ vcge.f d28, d31, #0 │ │ vrsra.u32 d22, d29, #3 │ │ @ instruction: 0xfffc5a90 │ │ vcge.f d28, d11, #0 │ │ vrsra.u32 d22, d9, #3 │ │ - @ instruction: 0xfffcbb54 │ │ + vsli.64 , q0, #60 @ 0x3c │ │ vcls.s q14, │ │ vrshr.u64 q11, , #3 │ │ vtbl.8 d21, {d28-d31}, d12 │ │ vcle.f d28, d7, #0 │ │ vsri.32 d22, d5, #3 │ │ - @ instruction: 0xfffc0cde │ │ + vqshl.u32 q9, q5, #28 │ │ vcgt.f q14, , #0 │ │ vrshr.u64 q11, , #3 │ │ vqshl.u32 d17, d1, #28 │ │ @ instruction: 0xfffec563 │ │ vrsra.u64 q11, , #3 │ │ vqrshrun.s64 d27, q9, #4 │ │ vsli.32 d28, d31, #29 │ │ vneg.s q11, │ │ - vpadal.s d18, d12 │ │ + vrev32. d20, d8 │ │ vsli.32 d28, d11, #29 │ │ vneg.s d22, d25 │ │ - @ instruction: 0xfffcef97 │ │ - vsri.64 q14, , #4 │ │ + vshll.u32 q8, d3, #28 │ │ + vsri.64 q14, , #3 │ │ vneg.s d22, d5 │ │ vqneg.s q8, q10 │ │ vsri.64 q14, , #2 │ │ vabs.s q11, │ │ vtbl.8 d27, {d12-d13}, d14 │ │ vcle.f d28, d27, #0 │ │ vsri.32 d22, d25, #3 │ │ @@ -28195,25 +28195,25 @@ │ │ ldr r0, [sp, #12] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ cmp r3, #248 @ 0xf8 │ │ movs r0, r3 │ │ strh r0, [r5, #26] │ │ - vqrdmulh.s , , d6[0] │ │ - vrev32. q11, │ │ + vneg.f , q1 │ │ + vcge.s q11, , #0 │ │ vdup.32 , d16[1] │ │ - @ instruction: 0xfffdfe0e │ │ - vsra.u64 d22, d23, #4 │ │ + vtbl.8 d17, {d29}, d10 │ │ + vsra.u64 d22, d23, #3 │ │ vqrshrun.s64 d26, q8, #4 │ │ - vqrdmulh.s , q6, d26[0] │ │ - vsra.u32 d22, d3, #4 │ │ - @ instruction: 0xfffced28 │ │ - @ instruction: 0xfffcfd22 │ │ - vrev32. q11, │ │ + vqneg.s , q11 │ │ + vsra.u32 d22, d3, #3 │ │ + vqneg.s d16, d20 │ │ + vqshl.u64 d17, d14, #61 @ 0x3d │ │ + vcge.s q11, , #0 │ │ @ instruction: 0xfffc2b36 │ │ movs r0, r3 │ │ │ │ 000bb650 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -28302,15 +28302,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ cmp r2, #74 @ 0x4a │ │ movs r0, r3 │ │ - lsrs r2, r0, #7 │ │ + movs r4, #62 @ 0x3e │ │ vcvt.u16.f16 , , #3 │ │ @ instruction: 0xfffd5f91 │ │ @ instruction: 0xfffc29b4 │ │ movs r0, r3 │ │ │ │ 000bb754 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -28468,18 +28468,18 @@ │ │ movs r0, r3 │ │ str r5, [r7, #100] @ 0x64 │ │ vqrdmlsh.s q10, , d25[0] │ │ @ instruction: 0xfffc5e2b │ │ vtbx.8 d25, {d12}, d17 │ │ vqrdmlsh.s q10, , d5[0] │ │ @ instruction: 0xfffc5e07 │ │ - @ instruction: 0xfffc13e0 │ │ + vcvt.f32.u32 q9, q6, #4 │ │ @ instruction: 0xfffd4f21 │ │ vqrdmulh.s , q14, d19[0] │ │ - vcls.s , │ │ + @ instruction: 0xfffc2edd │ │ @ instruction: 0xfffd4f8d │ │ vqrdmlah.s , q6, d15[0] │ │ vqrshrun.s64 d18, q10, #4 │ │ movs r0, r3 │ │ │ │ 000bb92c : │ │ push {r4, r5, r7, lr} │ │ @@ -28552,19 +28552,19 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ movs r7, #116 @ 0x74 │ │ movs r0, r3 │ │ - blt.n bb90e │ │ - vshr.u32 q14, q8, #4 │ │ + bl ffecd9dc <__cxa_new_handler@@Base+0xffc89dec> │ │ + bge.n bb9c0 │ │ vcvt.u16.f16 d21, d11, #4 │ │ - @ instruction: 0xfffcdb71 │ │ - vrev64. q14, q6 │ │ + @ instruction: 0xfffcf5ed │ │ + vtbx.8 d29, {d28-d30}, d8 │ │ @ instruction: 0xfffc5cf7 │ │ vqshl.u32 d18, d26, #28 │ │ movs r0, r3 │ │ │ │ 000bb9fc : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -28618,15 +28618,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ movs r6, #162 @ 0xa2 │ │ movs r0, r3 │ │ add r3, pc, #348 @ (adr r3, bbbe4 ) │ │ - @ instruction: 0xfffcbfb9 │ │ + vshll.u32 , d21, #28 │ │ vcvt.f16.u16 , , #4 │ │ vqshlu.s32 q9, q9, #28 │ │ movs r0, r3 │ │ │ │ 000bba94 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ @@ -28703,16 +28703,16 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ movs r6, #12 │ │ movs r0, r3 │ │ - bl 7fb4c │ │ - lsrs r3, r3, #27 │ │ + asrs r7, r7, #8 │ │ + @ instruction: 0xfffd0edb │ │ vtbl.8 d21, {d30- instruction: 0xfffd0eb7 │ │ vtbl.8 d21, {d30- instruction: 0xfffc25ca │ │ movs r0, r3 │ │ │ │ @@ -28983,31 +28983,31 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ movs r5, #42 @ 0x2a │ │ movs r0, r3 │ │ - bhi.n bbe6a │ │ - vsra.u64 , , #4 │ │ + bl 33de58 <__cxa_new_handler@@Base+0xfa268> │ │ + ldmia r4, {r0, r1, r4, r5, r6} │ │ vtbl.8 d21, {d28-d29}, d11 │ │ vpaddl.u d24, d18 │ │ - vsra.u32 d27, d3, #4 │ │ + vtbl.8 d28, {d28-d31}, d15 │ │ vtbl.8 d21, {d28}, d23 │ │ - @ instruction: 0xfffcd8d3 │ │ - vpaddl.u , │ │ + @ instruction: 0xfffcf34f │ │ + vqrdmulh.s q14, q6, d1[0] │ │ @ instruction: 0xfffc5a59 │ │ vtbl.8 d23, {d28-d30}, d8 │ │ - vcge.s , , #0 │ │ + vtbx.8 d28, {d13-d16}, d27 │ │ vtbl.8 d21, {d28}, d3 │ │ - vcvt.f16.u16 d27, d7, #4 │ │ - vsra.u32 d27, d23, #4 │ │ + vqshlu.s64 d29, d3, #60 @ 0x3c │ │ + @ instruction: 0xfffccbb3 │ │ vtbx.8 d21, {d28}, d11 │ │ @ instruction: 0xfffc1a94 │ │ - vshll.i , d19, # │ │ + @ instruction: 0xfffecd9f │ │ @ instruction: 0xfffc5ab7 │ │ vpaddl.u q9, q15 │ │ movs r0, r3 │ │ │ │ 000bbea8 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -29581,33 +29581,33 @@ │ │ itt ne │ │ ldrne r0, [sp, #20] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ subs r4, r5, #4 │ │ movs r0, r3 │ │ strb r5, [r2, #1] │ │ - vpadal.u d27, d6 │ │ + vrev16. d29, d2 │ │ vsubw.u , q6, d13 │ │ vqshl.u32 , q3, #28 │ │ - vqshlu.s32 d27, d10, #29 │ │ + vshr.u64 d29, d6, #3 │ │ vpaddl.u d21, d17 │ │ vshr.u64 d23, d13, #4 │ │ - vpadal.u , q7 │ │ + vrev16. , q5 │ │ vrsra.u32 , , #4 │ │ - vrev16. , │ │ - vpadal.s , q9 │ │ + @ instruction: 0xfffcebdf │ │ + vshr.u64 , q7, #4 │ │ vpaddl.u , │ │ vshr.u32 , , #4 │ │ - vpadal.u d27, d26 │ │ + vrev16. d29, d22 │ │ vrsra.u32 d21, d17, #4 │ │ @ instruction: 0xfffce8b3 │ │ - vqshlu.s32 d27, d30, #29 │ │ + vshr.u64 d29, d26, #3 │ │ vpaddl.u , │ │ vclz.i , q5 │ │ - vtbx.8 d27, {d14}, d22 │ │ + vqmovn.u d29, q9 │ │ vclz.i , │ │ @ instruction: 0xfffc1d88 │ │ movs r0, r3 │ │ │ │ 000bc498 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ @@ -29993,27 +29993,27 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ adds r4, r6, r7 │ │ movs r0, r3 │ │ ldrsb r1, [r6, r6] │ │ - @ instruction: 0xfffddb7f │ │ + vsli.64 , , #61 @ 0x3d │ │ vqrdmlsh.s q10, q6, d7[0] │ │ vqshl.u32 , , #28 │ │ - vtbl.8 d29, {d13-d16}, d21 │ │ + vcle.f d31, d17, #0 │ │ vqrdmlah.s q10, q14, d29[0] │ │ vqshl.u32 d21, d19, #28 │ │ - vtbl.8 d29, {d13-d16}, d1 │ │ + vsli.32 , , #29 │ │ vqrdmlah.s q10, q14, d9[0] │ │ vqabs.s d21, d15 │ │ - @ instruction: 0xfffddadd │ │ + vsli.32 , , #29 │ │ @ instruction: 0xfffc4ea5 │ │ @ instruction: 0xfffc0f9a │ │ - @ instruction: 0xfffedbf5 │ │ + vqshlu.s32 , , #30 │ │ @ instruction: 0xfffc4fbd │ │ vtbl.8 d17, {d12-d13}, d14 │ │ movs r0, r3 │ │ │ │ 000bc878 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ @@ -30076,15 +30076,15 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ adds r0, r5, r0 │ │ movs r0, r3 │ │ asrs r4, r7, #30 │ │ movs r0, r3 │ │ - ldmia r4!, {r2, r3, r5, r6} │ │ + b.n bc6ec │ │ vpaddl.u q13, q11 │ │ @ instruction: 0xfffd4df1 │ │ Address 0xbc922 is out of bounds. │ │ │ │ │ │ 000bc924 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -30222,21 +30222,21 @@ │ │ itt ne │ │ ldrne r0, [sp, #12] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ asrs r2, r6, #29 │ │ movs r0, r3 │ │ - ldmia r2, {r0, r2, r3, r5, r6, r7} │ │ + b.n bc562 │ │ vcvt.f32.u32 d26, d0, #4 │ │ vcvt.f16.u16 q10, , #3 │ │ - vtbx.8 d28, {d28-d30}, d9 │ │ + @ instruction: 0xfffce545 │ │ vqrdmulh.s q13, q14, d28[0] │ │ vdup.8 q10, d15[6] │ │ - @ instruction: 0xfffccb11 │ │ + vabal.u q15, d28, d13 │ │ vcvt.f32.u32 d26, d20, #4 │ │ @ instruction: 0xfffd4c97 │ │ vpadal.u , q2 │ │ movs r0, r3 │ │ │ │ 000bcab4 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -30610,15 +30610,15 @@ │ │ vqrshrun.s64 d20, , #3 │ │ vabal.u , d28, d4 │ │ @ instruction: 0xfffd6adb │ │ vqrshrun.s64 d20, , #3 │ │ vsra.u32 d21, d7, #4 │ │ vtbl.8 d22, {d13-d16}, d19 │ │ @ instruction: 0xfffd4899 │ │ - @ instruction: 0xfffcd562 │ │ + @ instruction: 0xfffcefde │ │ vtbl.8 d22, {d28-d31}, d15 │ │ vtbl.8 d20, {d13-d14}, d5 │ │ vqrdmlsh.s q12, q14, d29[0] │ │ vtbx.8 d22, {d12-d15}, d7 │ │ @ instruction: 0xfffd48bd │ │ vrsra.u32 , q8, #4 │ │ movs r0, r3 │ │ @@ -30751,19 +30751,19 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #12] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ asrs r2, r2, #6 │ │ movs r0, r3 │ │ - stmia r5!, {r0, r3, r4} │ │ - vqneg.s d27, d3 │ │ + svc 149 @ 0x95 │ │ + vsra.u64 , , #4 │ │ vqshlu.s64 d20, d15, #60 @ 0x3c │ │ - vsli.32 d28, d29, #28 │ │ - vqneg.s d27, d23 │ │ + @ instruction: 0xfffcdfb9 │ │ + vpaddl.s d29, d19 │ │ vpadal.u q10, │ │ vshr.u64 , q8, #4 │ │ movs r0, r3 │ │ │ │ 000bd054 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -30877,20 +30877,20 @@ │ │ itt ne │ │ ldrne r0, [sp, #12] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ asrs r2, r0, #1 │ │ movs r0, r3 │ │ - stmia r3!, {r0, r1, r2, r4, r5, r6, r7} │ │ - vtbl.8 d31, {d28-d31}, d26 │ │ - vsli.32 q10, , #28 │ │ - vrsra.u64 q14, , #4 │ │ - vtbl.8 d31, {d28-d31}, d6 │ │ - vsli.32 q10, , #28 │ │ + udf #115 @ 0x73 │ │ + vpadal.s d17, d22 │ │ + vsli.32 q10, , #29 │ │ + vqrdmlah.s , q6, d15[0] │ │ + vpadal.s d17, d2 │ │ + vsli.32 q10, , #29 │ │ @ instruction: 0xfffc0faa │ │ movs r0, r3 │ │ │ │ 000bd19c : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #48 @ 0x30 │ │ @@ -31026,21 +31026,21 @@ │ │ itt ne │ │ ldrne r0, [sp, #12] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ lsrs r0, r0, #28 │ │ movs r0, r3 │ │ - stmia r2!, {r0, r2, r5, r7} │ │ + ble.n bd33e │ │ vcvt.f32.u32 d22, d17, #4 │ │ vcls.s d20, d27 │ │ - vpaddl.u d28, d1 │ │ + @ instruction: 0xfffcdcfd │ │ @ instruction: 0xfffc6e0d │ │ vcls.s d20, d7 │ │ - vrshr.u32 q14, , #4 │ │ + @ instruction: 0xfffcdcd9 │ │ vqrdmulh.s q11, q14, d25[0] │ │ @ instruction: 0xfffc43e3 │ │ vcvt.f32.u32 q8, q2, #4 │ │ movs r0, r3 │ │ │ │ 000bd320 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -32246,23 +32246,23 @@ │ │ ldrne r0, [sp, #28] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ lsls r4, r5, #9 │ │ movs r0, r3 │ │ ldrh r3, [r6, #24] │ │ - vtbx.8 d25, {d29-d30}, d15 │ │ + vcgt.f , , #0 │ │ vpadal.s d19, d9 │ │ vpadal.u d31, d18 │ │ - @ instruction: 0xfffd99f3 │ │ + vcgt.f , , #0 │ │ vpadal.s d19, d29 │ │ vrev16. q9, q4 │ │ - vtbl.8 d25, {d29-d30}, d27 │ │ + vcgt.f d27, d23, #0 │ │ @ instruction: 0xfffc35e5 │ │ - vsra.u64 , , #4 │ │ + vcvt.f16.u16 q15, , #4 │ │ @ instruction: 0xfffce8f1 │ │ vcle.f , , #0 │ │ vshr.u32 q8, q1, #4 │ │ movs r0, r3 │ │ │ │ 000be150 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -32367,18 +32367,18 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ vqadd.u8 d16, d8, d7 │ │ strh r5, [r7, r0] │ │ - vqrdmulh.s q12, q6, d27[0] │ │ + vqneg.s q13, │ │ vsri.64 , , #4 │ │ vsri.32 , q7, #4 │ │ - @ instruction: 0xfffd8cf7 │ │ + vqshl.u32 q13, , #29 │ │ vclz.i d19, d1 │ │ @ instruction: 0xfffcfea4 │ │ movs r7, r2 │ │ │ │ 000be274 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -32809,18 +32809,18 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ smlawt r0, r8, r7, r0 │ │ ldr r5, [pc, #340] @ (be824 ) │ │ - vpadal.s q15, q2 │ │ - vrev64. d19, d13 │ │ + vrev32. q8, q0 │ │ + vcgt.s d19, d13, #0 │ │ vrev64. d31, d30 │ │ - vneg.s , q7 │ │ + vqrdmlah.s q13, , d10[0] │ │ vshr.u32 , , #4 │ │ @ instruction: 0xfffcfabc │ │ movs r7, r2 │ │ │ │ 000be6e8 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -32908,15 +32908,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrsh.w r0, [r0, #23] │ │ vrecps.f32 , q12, │ │ - strh r5, [r4, #60] @ 0x3c │ │ + add r2, pc, #132 @ (adr r2, be858 ) │ │ @ instruction: 0xfffc2f2f │ │ vqrshrn.u64 d31, q1, #4 │ │ movs r7, r2 │ │ │ │ 000be7dc : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ @@ -33127,18 +33127,18 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldrh.w r0, [sl, r7, lsl #1] │ │ ldr r2, [pc, #124] @ (bea80 ) │ │ - vqshrn.u64 d27, q6, #4 │ │ + vrsra.u64 d29, d8, #4 │ │ @ instruction: 0xfffc2cd7 │ │ @ instruction: 0xfffc2d8e │ │ - vtbx.8 d27, {d12-d13}, d0 │ │ + vrsra.u64 d29, d28, #4 │ │ @ instruction: 0xfffc2cfb │ │ vqshl.u32 d31, d14, #28 │ │ movs r7, r2 │ │ │ │ 000bea1c : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -33314,15 +33314,15 @@ │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ @ instruction: 0xf6800017 │ │ ldr r0, [pc, #180] @ (becac ) │ │ @ instruction: 0xfffccfbc │ │ vtbx.8 d18, {d29-d31}, d21 │ │ vtbl.8 d30, {d12-d15}, d26 │ │ - vqrdmlah.s q12, , d10[0] │ │ + vtbx.8 d26, {d13-d14}, d6 │ │ @ instruction: 0xfffc2b51 │ │ @ instruction: 0xfffc2b9c │ │ vqrdmlsh.s q14, q14, d16[0] │ │ vtbl.8 d18, {d13-d16}, d9 │ │ vsli.32 , q12, #28 │ │ movs r7, r2 │ │ │ │ @@ -33446,15 +33446,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ eor.w r0, r2, #9895936 @ 0x970000 │ │ @ instruction: 0xe990fffd │ │ - strh r5, [r5, #16] │ │ + ldr r4, [sp, #676] @ 0x2a4 │ │ @ instruction: 0xfffc29b7 │ │ vtbl.8 d18, {d12-d14}, d2 │ │ vsri.64 d17, d22, #4 │ │ vtbx.8 d18, {d13-d14}, d31 │ │ @ instruction: 0xfffcf3e0 │ │ movs r7, r2 │ │ │ │ @@ -33672,15 +33672,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #12] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ addw r0, r4, #23 │ │ add r1, ip │ │ - @ instruction: 0xfffc7f97 │ │ + vshll.u32 , d3, #28 │ │ vqshl.u32 d18, d9, #28 │ │ vrev16. , q7 │ │ movs r7, r2 │ │ │ │ 000befcc : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -33816,18 +33816,18 @@ │ │ itt ne │ │ ldrne r0, [sp, #48] @ 0x30 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ @ instruction: 0xf0ca0017 │ │ cmn r5, r3 │ │ - vcvt.f32.u32 d23, d11, #4 │ │ + @ instruction: 0xfffc9897 │ │ vsli.64 d18, d5, #60 @ 0x3c │ │ vsli.64 d30, d22, #60 @ 0x3c │ │ - vqrshrn.u64 d24, q3, #3 │ │ + vrsra.u64 q13, q1, #3 │ │ vsli.64 q9, , #60 @ 0x3c │ │ vrev64. , q2 │ │ movs r7, r2 │ │ │ │ 000bf160 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -33915,15 +33915,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #48] @ 0x30 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ vqadd.s64 d0, d8, d7 │ │ b.n beb58 │ │ - vcvt.u16.f16 d23, d13, #3 │ │ + vqshl.u64 d25, d9, #61 @ 0x3d │ │ vclz.i d18, d23 │ │ vqrdmlah.s q15, q14, d14[0] │ │ movs r7, r2 │ │ │ │ 000bf264 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -34145,15 +34145,15 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldc 0, cr0, [lr, #92] @ 0x5c │ │ subs r7, #119 @ 0x77 │ │ vsri.64 d20, d0, #4 │ │ vclt.s d18, d31, #0 │ │ - vqrdmlah.s , q14, d2[0] │ │ + vqshrn.u64 d29, q15, #4 │ │ vclz.i q10, q15 │ │ vsubl.u q9, d29, d13 │ │ vcvt.f16.u16 q15, q1, #4 │ │ movs r7, r2 │ │ │ │ 000bf4c4 : │ │ push {r4, r5, r7, lr} │ │ @@ -34337,17 +34337,17 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ rsbs r0, r8, r7, lsr #32 │ │ subs r5, #127 @ 0x7f │ │ vtbx.8 d21, {d28-d30}, d8 │ │ vshr.u32 d18, d23, #3 │ │ vshr.u32 q15, q4, #4 │ │ - vrsra.u64 q12, q12, #3 │ │ + vcvt.f32.u32 , q10, #3 │ │ vshr.u32 q9, , #4 │ │ - vqrdmulh.s , q6, d30[0] │ │ + vqneg.s , q13 │ │ vtbx.8 d21, {d28-d31}, d10 │ │ vsra.u32 d18, d25, #3 │ │ vtbl.8 d30, {d28-d30}, d18 │ │ movs r7, r2 │ │ │ │ 000bf6cc : │ │ push {r4, r6, r7, lr} │ │ @@ -34472,17 +34472,17 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrd r0, r0, [r2, #92] @ 0x5c │ │ udf #226 @ 0xe2 │ │ - vqshl.u32 , , #29 │ │ + vsra.u64 , , #3 │ │ @ instruction: 0xfffc1f09 │ │ - @ instruction: 0xfffcbaf6 │ │ + vsli.32 , q9, #28 │ │ vpaddl.s d29, d9 │ │ vqrdmlah.s , , d1[0] │ │ vtbl.8 d30, {d12-d13}, d30 │ │ movs r7, r2 │ │ │ │ 000bf834 : │ │ push {r4, r5, r7, lr} │ │ @@ -34581,15 +34581,15 @@ │ │ ldrb.w r0, [sp, #4] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #12] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strd r0, r0, [r8], #-92 @ 0x5c │ │ - cbnz r2, bf96a │ │ + bmi.n bf9e0 │ │ vdup.32 q12, d9[1] │ │ @ instruction: 0xfffd1da5 │ │ vqneg.s q15, q2 │ │ movs r7, r2 │ │ │ │ 000bf940 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -35353,30 +35353,30 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ b.n bfc9c │ │ movs r7, r2 │ │ ldmia r2!, {r0, r1, r3, r5, r6, r7} │ │ @ instruction: 0xfffd08db │ │ vqneg.s d17, d11 │ │ - vaddw.u q14, q14, d22 │ │ + vdup.32 d29, d18[1] │ │ @ instruction: 0xfffc08b7 │ │ vqabs.s , │ │ vrsra.u32 d18, d5, #4 │ │ vtbx.8 d16, {d12}, d11 │ │ vqshlu.s64 , , #60 @ 0x3c │ │ @ instruction: 0xfffc39be │ │ vtbx.8 d16, {d13}, d31 │ │ vqshl.u32 d17, d15, #28 │ │ vsubw.u q10, q14, d14 │ │ vtbl.8 d16, {d13}, d3 │ │ vqshlu.s64 d17, d19, #60 @ 0x3c │ │ - @ instruction: 0xfffc7b3c │ │ + vsli.64 d25, d24, #60 @ 0x3c │ │ @ instruction: 0xfffc08ff │ │ vqneg.s d17, d31 │ │ - vqneg.s d24, d9 │ │ + vpaddl.s d26, d5 │ │ vqshl.u64 q8, , #60 @ 0x3c │ │ vpadal.u d17, d15 │ │ vrsra.u64 q13, , #4 │ │ vqshl.u64 d16, d27, #61 @ 0x3d │ │ vpadal.s , │ │ vaddw.u , q14, d17 │ │ vtbl.8 d16, {d13}, d23 │ │ @@ -35662,33 +35662,33 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #20] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ udf #128 @ 0x80 │ │ movs r7, r2 │ │ - str r1, [sp, #460] @ 0x1cc │ │ + add r3, sp, #956 @ 0x3bc │ │ @ instruction: 0xfffc5a71 │ │ vrshr.u64 , , #4 │ │ vqdmulh.s , q14, d13[0] │ │ vtbl.8 d21, {d12-d14}, d25 │ │ vrshr.u64 d17, d17, #4 │ │ - vrev16. d25, d7 │ │ + vtbl.8 d26, {d28-d31}, d3 │ │ vtbl.8 d21, {d12-d14}, d5 │ │ vpaddl.u d17, d13 │ │ vqabs.s , │ │ vtbx.8 d21, {d29-d30}, d17 │ │ vpaddl.s , │ │ vqshl.u32 q11, q4, #28 │ │ @ instruction: 0xfffd59bd │ │ vpaddl.s , │ │ @ instruction: 0xfffc9f8d │ │ @ instruction: 0xfffd5999 │ │ vpaddl.s d17, d17 │ │ - @ instruction: 0xfffcd561 │ │ + @ instruction: 0xfffcefdd │ │ vtbx.8 d21, {d12-d14}, d13 │ │ vrshr.u64 , , #4 │ │ @ instruction: 0xfffcdd28 │ │ movs r7, r2 │ │ │ │ 000c0518 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -35810,22 +35810,22 @@ │ │ itt ne │ │ ldrne r0, [sp, #24] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ blt.n c0554 │ │ movs r7, r2 │ │ - ldrh r5, [r4, #56] @ 0x38 │ │ - vcvt.u32.f32 d24, d28, #4 │ │ + add r1, sp, #644 @ 0x284 │ │ + @ instruction: 0xfffca9b8 │ │ vrev32. d17, d27 │ │ - vqrdmlsh.s q12, q6, d9[0] │ │ - vqrdmlsh.s q12, q6, d16[0] │ │ + vtbx.8 d26, {d28-d29}, d5 │ │ + @ instruction: 0xfffca9dc │ │ vrev32. , │ │ - @ instruction: 0xfffc8f01 │ │ - vcvt.u32.f32 d24, d8, #4 │ │ + vqrshrn.u64 d26, , #4 │ │ + @ instruction: 0xfffca994 │ │ vrev32. d17, d7 │ │ @ instruction: 0xfffcdaf4 │ │ movs r7, r2 │ │ │ │ 000c067c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -36062,24 +36062,24 @@ │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bge.n c0920 │ │ movs r7, r2 │ │ subs r6, r6, r3 │ │ vtbl.8 d17, {d12-d15}, d1 │ │ @ instruction: 0xfffc0eaf │ │ - vcvt.f32.u32 d24, d27, #4 │ │ + @ instruction: 0xfffca8b7 │ │ vqrdmulh.s , q14, d2[0] │ │ movs r7, r2 │ │ ldrsb r3, [r1, r1] │ │ @ instruction: 0xfffd1add │ │ @ instruction: 0xfffc0e8b │ │ vtbx.8 d18, {d28-d31}, d5 │ │ @ instruction: 0xfffc1ab9 │ │ vqrdmlah.s q8, q6, d23[0] │ │ - vrev16. d29, d14 │ │ + vtbl.8 d30, {d28-d31}, d10 │ │ @ instruction: 0xfffc1a95 │ │ vqrdmlah.s q8, q6, d3[0] │ │ @ instruction: 0xfffc6ffc │ │ vtbx.8 d17, {d13-d15}, d13 │ │ @ instruction: 0xfffc0dfb │ │ vqshrun.s64 d19, q5, #4 │ │ @ instruction: 0xfffc1a71 │ │ @@ -36136,15 +36136,15 @@ │ │ strd r1, r1, [sp, #24] │ │ blx r6 │ │ add sp, #40 @ 0x28 │ │ ldmia.w sp!, {r8, r9, fp} │ │ pop {r4, r5, r6, r7, pc} │ │ lsls r6, r0, #3 │ │ movs r0, r3 │ │ - ldrh r5, [r1, #28] │ │ + add r6, pc, #36 @ (adr r6, c09e0 ) │ │ @ instruction: 0xfffc5b36 │ │ movs r7, r2 │ │ │ │ 000c09c0 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -36233,15 +36233,15 @@ │ │ ldrne r0, [sp, #48] @ 0x30 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ movs r6, r7 │ │ movs r0, r3 │ │ bvs.n c0a44 │ │ movs r7, r2 │ │ - ldrh r5, [r7, #22] │ │ + add r5, pc, #484 @ (adr r5, c0c88 ) │ │ vtbl.8 d21, {d28-d30}, d20 │ │ movs r7, r2 │ │ bl 59aa4 │ │ ldrb r1, [r5, #11] │ │ vcvt.f16.u16 d16, d25, #3 │ │ vqshlu.s32 , q7, #28 │ │ movs r7, r2 │ │ @@ -36315,15 +36315,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bpl.n c0b30 │ │ movs r7, r2 │ │ - ldrh r7, [r5, #14] │ │ + add r4, pc, #428 @ (adr r4, c0d10 ) │ │ vcvt.f32.u32 d18, d23, #4 │ │ @ instruction: 0xfffd0b75 │ │ vcvt.u32.f32 d31, d28, #4 │ │ movs r7, r2 │ │ bpl.n c0ac4 │ │ movs r7, r2 │ │ bpl.n c0b0c │ │ @@ -36401,15 +36401,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ bpl.n c0c78 │ │ movs r7, r2 │ │ - ldrh r1, [r5, #8] │ │ + add r3, pc, #660 @ (adr r3, c0ec0 ) │ │ vrev16. q13, │ │ vtbl.8 d16, {d29-d31}, d31 │ │ vcvt.f32.u32 , q11, #4 │ │ movs r7, r2 │ │ bmi.n c0c00 │ │ movs r7, r2 │ │ bpl.n c0c48 │ │ @@ -36528,15 +36528,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bmi.n c0e10 │ │ movs r7, r2 │ │ - strh r5, [r5, #62] @ 0x3e │ │ + add r2, pc, #420 @ (adr r2, c0f0c ) │ │ @ instruction: 0xfffcfb32 │ │ vqrshrn.u64 d16, , #5 │ │ vqshlu.s64 d20, d18, #60 @ 0x3c │ │ vtbx.8 d31, {d28-d31}, d20 │ │ vtbl.8 d16, {d11-d13}, d21 │ │ vcvt.u16.f16 d31, d16, #4 │ │ movs r7, r2 │ │ @@ -36595,16 +36595,16 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bcc.n c0e38 │ │ movs r7, r2 │ │ - strh r3, [r1, #58] @ 0x3a │ │ - vrsra.u32 d27, d21, #4 │ │ + add r1, pc, #796 @ (adr r1, c1124 ) │ │ + @ instruction: 0xfffccdb1 │ │ @ instruction: 0xfffc08d1 │ │ vcvt.f16.u16 , q9, #4 │ │ movs r7, r2 │ │ bcs.n c0df8 │ │ movs r7, r2 │ │ │ │ 000c0e18 : │ │ @@ -36663,15 +36663,15 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ bcs.n c0db4 │ │ movs r7, r2 │ │ asrs r2, r3, #4 │ │ - vrshr.u64 d27, d15, #3 │ │ + vcvt.u16.f16 d28, d11, #3 │ │ vtbl.8 d16, {d12}, d27 │ │ vpaddl.s , q5 │ │ movs r7, r2 │ │ │ │ 000c0ebc : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -36759,18 +36759,18 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bne.n c0f54 │ │ movs r7, r2 │ │ - strh r5, [r3, #46] @ 0x2e │ │ + add r0, pc, #356 @ (adr r0, c1100 ) │ │ vsli.32 d25, d2, #28 │ │ vabs.f q8, │ │ - vsli.64 d24, d25, #60 @ 0x3c │ │ + vshr.u32 d26, d21, #4 │ │ vclz.i , q15 │ │ vqshl.u32 d16, d31, #29 │ │ @ instruction: 0xfffcfb1e │ │ movs r7, r2 │ │ bne.n c0ec4 │ │ movs r7, r2 │ │ │ │ @@ -36817,16 +36817,16 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ beq.n c0ff4 │ │ movs r7, r2 │ │ - strh r3, [r5, #40] @ 0x28 │ │ - vqneg.s , │ │ + ldr r7, [sp, #668] @ 0x29c │ │ + vpaddl.s , │ │ vqshlu.s64 d16, d17, #60 @ 0x3c │ │ vshr.u64 , q0, #4 │ │ movs r7, r2 │ │ │ │ 000c1034 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -37063,24 +37063,24 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldmia r7!, {r6} │ │ movs r7, r2 │ │ adds r1, #148 @ 0x94 │ │ - @ instruction: 0xfffd5d21 │ │ + vqshl.u64 d23, d13, #61 @ 0x3d │ │ vsri.64 d16, d3, #4 │ │ - vqabs.s q14, │ │ - @ instruction: 0xfffc5cfd │ │ + @ instruction: 0xfffce1c7 │ │ + vqshl.u32 , , #28 │ │ vcls.s q8, │ │ - @ instruction: 0xfffcaed9 │ │ - @ instruction: 0xfffc5cd9 │ │ + vqrshrn.u64 d28, , #4 │ │ + vqshl.u32 , , #28 │ │ vcls.s q8, │ │ @ instruction: 0xfffcfcf2 │ │ - @ instruction: 0xfffc5d97 │ │ + vqshrun.s64 d23, , #4 │ │ vabal.u q8, d12, d9 │ │ @ instruction: 0xfffcceb2 │ │ movs r7, r2 │ │ │ │ 000c12c4 ::operator()(CvMat*) const@@Base>: │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -37347,15 +37347,15 @@ │ │ vcvt.f16.u16 d28, d18, #4 │ │ movs r7, r2 │ │ rsb r0, r4, #9895936 @ 0x970000 │ │ ldmia r4, {r4} │ │ movs r7, r2 │ │ ldmia r4, {r1, r4, r6} │ │ movs r7, r2 │ │ - ldrh r0, [r1, #56] @ 0x38 │ │ + add r1, sp, #528 @ 0x210 │ │ vtbx.8 d20, {d12-d14}, d11 │ │ vsubl.u q8, d29, d9 │ │ Address 0xc1522 is out of bounds. │ │ │ │ │ │ 000c1524 : │ │ push {r4, r6, r7, lr} │ │ @@ -37449,15 +37449,15 @@ │ │ asrs r3, r6, #20 │ │ vqshlu.s32 d26, d8, #29 │ │ vcge.s q8, , #0 │ │ vtbl.8 d28, {d12-d15}, d6 │ │ movs r7, r2 │ │ ldmia r3!, {r1, r2, r5} │ │ movs r7, r2 │ │ - ldrh r2, [r1, #46] @ 0x2e │ │ + add r0, sp, #280 @ 0x118 │ │ vpadal.u d26, d2 │ │ vceq.i q8, , #0 │ │ Address 0xc1616 is out of bounds. │ │ │ │ │ │ 000c1618 : │ │ movs r1, #0 │ │ @@ -37851,15 +37851,15 @@ │ │ stmia r7!, {r2, r4, r6} │ │ movs r7, r2 │ │ stmia r7!, {r1, r2, r4, r6} │ │ movs r7, r2 │ │ vrecps.f16 , , │ │ lsrs r0, r1, #7 │ │ vrshr.u64 d21, d3, #4 │ │ - vsri.32 , q15, #3 │ │ + @ instruction: 0xfffdcefa │ │ @ instruction: 0xfffc0a9c │ │ @ instruction: 0xfffc5367 │ │ Address 0xc1a1e is out of bounds. │ │ │ │ │ │ 000c1a20 : │ │ push {r4, r6, r7, lr} │ │ @@ -38219,15 +38219,15 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r0, [sp, #192] @ 0xc0 │ │ blx 230d30 <__emutls_get_address@@Base+0x3ea8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ stmia r5!, {r1, r3, r6} │ │ movs r7, r2 │ │ - strb r5, [r7, #31] │ │ + str r2, [sp, #484] @ 0x1e4 │ │ vqshlu.s64 d17, d26, #60 @ 0x3c │ │ @ instruction: 0xfffc4e89 │ │ vceq.f d28, d22, #0 │ │ movs r7, r2 │ │ stmia r5!, {r5} │ │ movs r7, r2 │ │ stmia r5!, {r5} │ │ @@ -38586,15 +38586,15 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ it hi │ │ movhi r7, r2 │ │ adds r7, r7, r0 │ │ - @ instruction: 0xfffd9ffd │ │ + @ instruction: 0xfffdba79 │ │ vtbl.8 d20, {d28-d30}, d7 │ │ vcvt.u32.f32 , q12, #3 │ │ movs r7, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ sub sp, #24 │ │ @@ -38807,19 +38807,19 @@ │ │ beq.n c23c0 │ │ ldr r0, [sp, #12] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ itt eq │ │ moveq r7, r2 │ │ - ldrsbeq r5, [r3, r4] │ │ - vqrdmulh.s , q14, d23[0] │ │ + strbeq r1, [r3, #6] │ │ + vtbx.8 d27, {d12}, d19 │ │ vqrshrun.s64 d20, , #4 │ │ - @ instruction: 0xfffd8f8b │ │ - vqrdmulh.s , q14, d7[0] │ │ + vtbl.8 d26, {d13-d15}, d7 │ │ + vtbx.8 d27, {d12}, d3 │ │ vqrshrun.s64 d20, , #4 │ │ vsri.32 d20, d2, #3 │ │ movs r7, r2 │ │ pop {r5, r6, pc} │ │ movs r7, r2 │ │ bics r2, r1 │ │ movs r7, r2 │ │ @@ -38984,18 +38984,18 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ mov r0, r4 │ │ blx 230d30 <__emutls_get_address@@Base+0x3ea8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ pop {} │ │ movs r7, r2 │ │ - strb r5, [r0, r5] │ │ + ldr r1, [r0, #124] @ 0x7c │ │ vcvt.u32.f32 q11, q10, #4 │ │ vqshlu.s64 d20, d9, #61 @ 0x3d │ │ - @ instruction: 0xfffd8db3 │ │ + vtbl.8 d26, {d13}, d31 │ │ vcvt.u32.f32 q11, q2, #4 │ │ vqshlu.s32 q10, , #29 │ │ @ instruction: 0xfffdbb92 │ │ movs r7, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -39198,18 +39198,18 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r0, [sp, #16] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ cbnz r0, c2804 │ │ movs r7, r2 │ │ - strh r5, [r2, r4] │ │ + ldr r1, [r2, #88] @ 0x58 │ │ vqrdmulh.s q11, q6, d4[0] │ │ vcgt.f q10, , #0 │ │ - vtbl.8 d24, {d29-, #61 @ 0x3d │ │ @ instruction: 0xfffc6d24 │ │ vcgt.f q10, , #0 │ │ vtbx.8 d27, {d13-d14}, d18 │ │ movs r7, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -40878,21 +40878,21 @@ │ │ str.w r9, [sp, #48] @ 0x30 │ │ mov r0, sl │ │ str.w sl, [sp, #40] @ 0x28 │ │ strd r2, ip, [sp, #60] @ 0x3c │ │ b.n c39aa │ │ adds r0, #132 @ 0x84 │ │ movs r7, r2 │ │ - ldrsh r5, [r6, r3] │ │ + ldrb r1, [r6, #5] │ │ vsli.64 d24, d2, #60 @ 0x3c │ │ vclt.s q10, q4, #0 │ │ vqshlu.s32 q9, , #29 │ │ vsri.32 d24, d10, #4 │ │ vshr.u64 q10, q0, #3 │ │ - vsri.64 , q10, #3 │ │ + vcvt.u32.f32 q13, q8, #3 │ │ @ instruction: 0xfffc83e0 │ │ vshr.u64 d20, d6, #3 │ │ vqshrun.s64 d25, , #3 │ │ add.w r0, r0, r5, lsl #2 │ │ str r4, [r0, #0] │ │ ldr r6, [sp, #344] @ 0x158 │ │ adds r4, #1 │ │ @@ -41604,18 +41604,18 @@ │ │ @ instruction: 0xffc0ffff │ │ rors r7, r3 │ │ add r2, sp, #896 @ 0x380 │ │ movs r7, r2 │ │ asrs r1, r6, #16 │ │ vcvt.f16.u16 d23, d24, #4 │ │ vtbx.8 d19, {d29}, d30 │ │ - vqshrun.s64 d20, , #3 │ │ + vrshr.u64 d22, d3, #3 │ │ vcvt.f16.u16 d23, d6, #4 │ │ vtbx.8 d19, {d29}, d12 │ │ - vceq.i q12, q11, #0 │ │ + vtbx.8 d25, {d29- instruction: 0xfffc7bf4 │ │ vtbl.8 d19, {d29}, d26 │ │ vclt.s d16, d29, #0 │ │ movs r0, r0 │ │ lsls r3, r3, #16 │ │ movs r0, r0 │ │ lsls r5, r2, #22 │ │ @@ -43240,25 +43240,25 @@ │ │ movs r7, r2 │ │ ldrh r2, [r6, #0] │ │ vcle.f d20, d19, #0 │ │ vsra.u64 d25, d28, #3 │ │ movs r7, r2 │ │ ldmia r0!, {r2, r3, r4, r5} │ │ vcvtm.s32.f32 , q1 │ │ - vqrdmlsh.s , q14, d17[0] │ │ + @ instruction: 0xfffc3a5d │ │ vsri.32 q15, , #4 │ │ vqrshrun.s64 d18, q1, #5 │ │ @ instruction: 0xfffd8eb4 │ │ movs r7, r2 │ │ @ instruction: 0xb8e0 │ │ @ instruction: 0xfffbb8b0 │ │ vqrdmlah.s , , d16[0] │ │ - vqabs.s d19, d1 │ │ + vsra.u32 , , #4 │ │ vpaddl.u q15, │ │ - vrecpe.u32 d20, d24 │ │ + @ instruction: 0xfffb5ea4 │ │ @ instruction: 0xfffcff03 │ │ vcvt.u32.f32 d24, d4, #4 │ │ movs r7, r2 │ │ ldrh r2, [r5, #52] @ 0x34 │ │ movs r7, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -43686,15 +43686,15 @@ │ │ ldrh r0, [r7, #40] @ 0x28 │ │ movs r7, r2 │ │ bvc.n c5812 │ │ @ instruction: 0xfffc8cfa │ │ movs r7, r2 │ │ stmia r3!, {r1, r3, r4, r5, r6} │ │ @ instruction: 0xfffbae80 │ │ - @ instruction: 0xfffc1b1f │ │ + vsli.64 d19, d11, #60 @ 0x3c │ │ vrev64. d30, d25 │ │ b.n c579c │ │ b.n c57d8 │ │ b.n c579c │ │ b.n c579c │ │ b.n c57dc │ │ b.n c579c │ │ @@ -43751,15 +43751,15 @@ │ │ vtbx.8 d24, {d13-d14}, d4 │ │ movs r7, r2 │ │ push {r1, r5} │ │ vrsra.u64 , q9, #5 │ │ vtbl.8 d27, {d27-d28}, d24 │ │ vsri.32 q15, , #4 │ │ vtbl.8 d30, {d12-d15}, d12 │ │ - vcvtp.s32.f32 d19, d17 │ │ + @ instruction: 0xfffb4c9d │ │ @ instruction: 0xfffc4db2 │ │ vcvt.u16.f16 d29, d25, #3 │ │ vtbl.8 d31, {d27-d28}, d17 │ │ vtbx.8 d24, {d28-d29}, d10 │ │ movs r7, r2 │ │ ldrh r0, [r4, #10] │ │ movs r7, r2 │ │ @@ -44152,25 +44152,25 @@ │ │ movs r7, r2 │ │ ldrb r2, [r4, #14] │ │ vceq.i , , #0 │ │ vqshrun.s64 d24, q2, #3 │ │ movs r7, r2 │ │ bkpt 0x0094 │ │ @ instruction: 0xfffba99a │ │ - vqshlu.s32 d17, d25, #28 │ │ + vshr.u64 d19, d21, #4 │ │ @ instruction: 0xfffcdad3 │ │ @ instruction: 0xfffb1eaa │ │ vceq.f d24, d12, #0 │ │ movs r7, r2 │ │ add r7, sp, #224 @ 0xe0 │ │ @ instruction: 0xfffbaf08 │ │ vsri.64 d27, d24, #5 │ │ - vcvt.u16.f16 q9, , #4 │ │ + vqshl.u64 q10, , #60 @ 0x3c │ │ vtbl.8 d29, {d12-d13}, d19 │ │ - vtbl.8 d19, {d27-d29}, d0 │ │ + vsri.64 , q14, #5 │ │ vsli.32 , , #28 │ │ @ instruction: 0xfffc856c │ │ movs r7, r2 │ │ strh r2, [r0, #40] @ 0x28 │ │ movs r7, r2 │ │ │ │ 000c5cac : │ │ @@ -44554,15 +44554,15 @@ │ │ strh r4, [r7, #30] │ │ movs r7, r2 │ │ b.n c5df4 │ │ vrsra.u64 d24, d30, #4 │ │ movs r7, r2 │ │ rev r6, r7 │ │ vrecpe.f32 q13, q2 │ │ - @ instruction: 0xfffc11e3 │ │ + vcvt.f16.u16 q9, , #4 │ │ vqshlu.s32 , , #28 │ │ vcvta.s32.f32 d30, d25 │ │ b.n c6126 │ │ b.n c60ea │ │ b.n c612c │ │ b.n c60e6 │ │ b.n c6122 │ │ @@ -44623,15 +44623,15 @@ │ │ @ instruction: 0xfffd7ffa │ │ movs r7, r2 │ │ add r2, sp, #920 @ 0x398 │ │ @ instruction: 0xfffbaab6 │ │ vcvta.s32.f32 , q14 │ │ @ instruction: 0xfffcdb3d │ │ vsra.u64 q15, q0, #4 │ │ - vtbx.8 d18, {d27}, d21 │ │ + vcvtm.s32.f32 q10, │ │ vcls.s q10, q13 │ │ vrsra.u64 , , #3 │ │ vshr.u32 , , #5 │ │ vrev32. d24, d2 │ │ movs r7, r2 │ │ strh r0, [r3, #0] │ │ movs r7, r2 │ │ @@ -45180,22 +45180,22 @@ │ │ add r0, sp, #32 │ │ blx 231070 <__emutls_get_address@@Base+0x41e8> │ │ mov r0, r4 │ │ blx 230de0 <__emutls_get_address@@Base+0x3f58> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldrb r0, [r2, #14] │ │ movs r7, r2 │ │ - ldr r5, [pc, #796] @ (c6a40 ) │ │ + ldr r3, [r0, #4] │ │ vcvt.u16.f16 d25, d26, #4 │ │ - vsli.32 d17, d20, #28 │ │ + @ instruction: 0xfffc2fb0 │ │ vqrdmlsh.s , q14, d24[0] │ │ @ instruction: 0xfffd1fb5 │ │ - vcvt.u16.f16 q10, , #3 │ │ + vqshl.u64 q11, , #61 @ 0x3d │ │ @ instruction: 0xfffc9cde │ │ - vclz.i , q8 │ │ + vcvt.u32.f32 q9, q6, #4 │ │ @ instruction: 0xfffc1fa2 │ │ vqrdmulh.s q14, , d29[0] │ │ @ instruction: 0xfffb7a9a │ │ movs r7, r2 │ │ ldrb r0, [r0, #10] │ │ movs r7, r2 │ │ ldrb r0, [r6, #9] │ │ @@ -45215,15 +45215,15 @@ │ │ ldr r1, [pc, #12] @ (c6778 ) │ │ ldr r2, [pc, #16] @ (c677c ) │ │ add r1, pc │ │ add r2, pc │ │ blx 231090 <__emutls_get_address@@Base+0x4208> │ │ pop {r7, pc} │ │ nop │ │ - movs r0, #210 @ 0xd2 │ │ + subs r3, #78 @ 0x4e │ │ vpadal.u , │ │ vsli.64 , q8, #59 @ 0x3b │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ ldr r1, [pc, #88] @ (c67e4 ) │ │ ldr r2, [r0, #0] │ │ ldr r3, [pc, #88] @ (c67e8 ) │ │ @@ -45745,15 +45745,15 @@ │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strb r4, [r1, #22] │ │ movs r7, r2 │ │ strb r6, [r0, #11] │ │ @ instruction: 0xfffd5db9 │ │ - @ instruction: 0xfffd0e23 │ │ + @ instruction: 0xfffd289f │ │ vcls.s , q6 │ │ movs r7, r2 │ │ strb r0, [r1, #21] │ │ movs r7, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -45863,21 +45863,21 @@ │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strb r6, [r5, #14] │ │ movs r7, r2 │ │ strb r2, [r1, #7] │ │ vqrdmlsh.s , , d29[0] │ │ - @ instruction: 0xfffd0d25 │ │ - vtbl.8 d17, {d28-d30}, d28 │ │ + vneg.f d18, d17 │ │ + vabal.u , d12, d24 │ │ vqrdmlsh.s , q14, d11[0] │ │ - @ instruction: 0xfffd0d03 │ │ - @ instruction: 0xfffc6bfd │ │ + vqshl.u32 q9, , #29 │ │ + vqshlu.s32 q12, , #28 │ │ @ instruction: 0xfffc3fa9 │ │ - vqdmulh.s q8, , d17[0] │ │ + vqshl.u32 q9, , #29 │ │ @ instruction: 0xfffc7348 │ │ movs r7, r2 │ │ │ │ 000c6e20 : │ │ push {r7, lr} │ │ mov r7, sp │ │ sub sp, #24 │ │ @@ -45981,18 +45981,18 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strb r0, [r0, #10] │ │ movs r7, r2 │ │ ldr r0, [r1, #108] @ 0x6c │ │ vqrdmlsh.s q15, , d21[0] │ │ - vdup.32 d16, d13[1] │ │ + vpadal.u d18, d9 │ │ vqneg.s d22, d16 │ │ @ instruction: 0xfffd5b75 │ │ - vtbx.8 d16, {d29- q9, , #0 │ │ vrshr.u32 d23, d22, #4 │ │ movs r7, r2 │ │ strb r0, [r3, #9] │ │ movs r7, r2 │ │ │ │ 000c6f3c : │ │ push {r4, r5, r7, lr} │ │ @@ -46065,15 +46065,15 @@ │ │ nop │ │ strb r2, [r4, #5] │ │ movs r7, r2 │ │ strb r0, [r6, #4] │ │ movs r7, r2 │ │ str r0, [r3, #108] @ 0x6c │ │ vtbl.8 d21, {d29-d31}, d29 │ │ - vtbl.8 d16, {d13-d16}, d5 │ │ + vcle.f d18, d1, #0 │ │ Address 0xc6ff2 is out of bounds. │ │ │ │ │ │ 000c6ff4 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #24 │ │ @@ -46166,22 +46166,22 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strb r2, [r5, #2] │ │ movs r7, r2 │ │ add r7, sp, #312 @ 0x138 │ │ - @ instruction: 0xfffc5cdc │ │ - vtbx.8 d16, {d12-d14}, d9 │ │ - vqrdmlah.s , q14, d20[0] │ │ - @ instruction: 0xfffb5cba │ │ - vtbl.8 d16, {d12-d14}, d23 │ │ + vqshl.u32 , q4, #28 │ │ + vclz.i q9, │ │ + vtbx.8 d17, {d12-d13}, d16 │ │ + vqshl.u32 d23, d22, #28 │ │ + vclz.i d18, d19 │ │ vrev64. , q1 │ │ - @ instruction: 0xfffb5c98 │ │ - vtbl.8 d16, {d12-d14}, d5 │ │ + vqshl.u32 d23, d4, #27 │ │ + vclz.i d18, d1 │ │ vshr.u64 d23, d10, #4 │ │ movs r7, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #24 │ │ mov r4, r0 │ │ @@ -46255,18 +46255,18 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r6, [r3, #120] @ 0x78 │ │ movs r7, r2 │ │ ldr r0, [r5, #92] @ 0x5c │ │ vsra.u64 d27, d16, #3 │ │ - vtbx.8 d16, {d11-d12}, d3 │ │ + vrsra.u64 d18, d31, #5 │ │ @ instruction: 0xfffced04 │ │ vaddw.u , q14, d14 │ │ - vtbl.8 d16, {d11-d12}, d17 │ │ + vrsra.u64 d18, d13, #5 │ │ vqrdmlsh.s q11, q6, d26[0] │ │ movs r7, r2 │ │ push {r7, lr} │ │ mov r7, sp │ │ movs r0, #4 │ │ blx 230710 <__emutls_get_address@@Base+0x3888> │ │ blx 2310a0 <__emutls_get_address@@Base+0x4218> │ │ @@ -46283,15 +46283,15 @@ │ │ ldr r0, [r4, #112] @ 0x70 │ │ movs r7, r2 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (c7204 ) │ │ add r0, pc │ │ bl a91f8 │ │ - ldr r1, [r5, #0] │ │ + strh r5, [r4, #20] │ │ vabal.u , d28, d0 │ │ mov r7, sp │ │ ldr r0, [pc, #16] @ (c7220 ) │ │ movs r1, #0 │ │ add r0, pc │ │ blx 2307a0 <__emutls_get_address@@Base+0x3918> │ │ ldr r1, [pc, #12] @ (c7224 ) │ │ @@ -46660,15 +46660,15 @@ │ │ str r1, [sp, #56] @ 0x38 │ │ str.w r8, [sp, #44] @ 0x2c │ │ str r0, [sp, #68] @ 0x44 │ │ b.n c7602 │ │ eors.w r0, r8, #9830400 @ 0x960000 │ │ str r6, [sp, #404] @ 0x194 │ │ vqrshrn.u64 d20, q10, #5 │ │ - vcle.f , q10, #0 │ │ + vcgt.s , q8, #0 │ │ @ instruction: 0xfffc9d07 │ │ adds r5, #1 │ │ add r0, sp, #108 @ 0x6c │ │ blx 230920 <__emutls_get_address@@Base+0x3a98> │ │ ldr r0, [sp, #124] @ 0x7c │ │ ldrd r2, r1, [sp, #12] │ │ cmp r5, r0 │ │ @@ -46902,20 +46902,20 @@ │ │ movs r0, r0 │ │ movs r2, r0 │ │ movs r0, r0 │ │ movs r3, r0 │ │ movs r0, r0 │ │ ldr r6, [r2, #100] @ 0x64 │ │ movs r7, r2 │ │ - str r4, [r3, #36] @ 0x24 │ │ + ldrb r0, [r3, #19] │ │ vcls.s d20, d24 │ │ - vshr.u64 d17, d8, #3 │ │ - @ instruction: 0xfffc1db9 │ │ + @ instruction: 0xfffd2b14 │ │ + vqshrun.s64 d19, , #4 │ │ vcls.s d20, d6 │ │ - vshr.u32 , q11, #3 │ │ + @ instruction: 0xfffd2af2 │ │ vrshr.u32 d31, d0, #4 │ │ movs r6, r2 │ │ ldr r0, [r7, #12] │ │ movs r7, r2 │ │ │ │ 000c78b4 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -47174,15 +47174,15 @@ │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ mrc 0, 1, r0, cr4, cr6, {0} │ │ str r4, [r3, #124] @ 0x7c │ │ movs r7, r2 │ │ cmp r1, #133 @ 0x85 │ │ vceq.i d20, d12, #0 │ │ - vcvt.u16.f16 q8, q14, #3 │ │ + vqshl.u64 q9, q12, #61 @ 0x3d │ │ vsli.64 q11, q2, #60 @ 0x3c │ │ movs r7, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #92 @ 0x5c │ │ add.w r8, r0, #8 │ │ @@ -47699,15 +47699,15 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strd r0, r0, [ip], #-88 @ 0x58 │ │ str r0, [r0, #32] │ │ movs r7, r2 │ │ strh r5, [r6, #24] │ │ vmull.u , d28, d12 │ │ - @ instruction: 0xfffd08fc │ │ + vrsra.u32 q9, q12, #3 │ │ vqrdmlsh.s , q14, d12[0] │ │ movs r7, r2 │ │ │ │ 000c818c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -47828,16 +47828,16 @@ │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ b.n c7dd8 │ │ movs r6, r2 │ │ ldrsh r6, [r0, r4] │ │ movs r7, r2 │ │ add r0, sp, #836 @ 0x344 │ │ - vpadal.s q8, q15 │ │ - vsli.64 q8, q11, #60 @ 0x3c │ │ + vrev32. q9, q13 │ │ + vshr.u32 q9, q9, #4 │ │ vqrdmlah.s , q6, d12[0] │ │ movs r7, r2 │ │ │ │ 000c82e0 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -47983,18 +47983,18 @@ │ │ nop │ │ b.n c7ce8 │ │ movs r6, r2 │ │ ldrb r2, [r6, r6] │ │ movs r7, r2 │ │ ldrh r4, [r1, #24] │ │ vqshlu.s32 d31, d13, #28 │ │ - vsri.64 d16, d0, #4 │ │ - @ instruction: 0xfffc2f21 │ │ + @ instruction: 0xfffc1f0c │ │ + @ instruction: 0xfffc499d │ │ vsli.64 , , #60 @ 0x3c │ │ - vcls.s q8, q15 │ │ + vqrdmlah.s , q14, d26[0] │ │ vqdmulh.s , q14, d22[0] │ │ movs r7, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #16 │ │ ldr.w r8, [r7, #12] │ │ @@ -48894,35 +48894,35 @@ │ │ movs r7, r2 │ │ strb r4, [r5, r7] │ │ movs r7, r2 │ │ strb r6, [r5, r6] │ │ movs r7, r2 │ │ strb r2, [r1, r6] │ │ movs r7, r2 │ │ - rors r1, r0 │ │ + ldrb r5, [r7, r0] │ │ vqshlu.s32 d28, d8, #28 │ │ vshr.u32 , q2, #4 │ │ vabs.s , q8 │ │ movs r7, r2 │ │ blt.n c8d70 │ │ movs r6, r2 │ │ stmia r5!, {r1, r2, r5, r6, r7} │ │ vqshlu.s64 , q4, #60 @ 0x3c │ │ - @ instruction: 0xfffc3566 │ │ + vqrdmlsh.s q10, q14, d18[0] │ │ vcvt.f32.u32 d26, d11, #4 │ │ vsri.64 d27, d22, #4 │ │ vtbl.8 d29, {d11-d14}, d18 │ │ movs r6, r2 │ │ str r3, [sp, #360] @ 0x168 │ │ vrsra.u32 , q0, #4 │ │ - vcvt.f16.u16 , , #4 │ │ - vqrdmlsh.s q9, , d30[0] │ │ + vpadal.u , │ │ + vqrdmlsh.s q9, q6, d30[0] │ │ vtbl.8 d29, {d13-d16}, d8 │ │ movs r6, r2 │ │ - adds r4, #170 @ 0xaa │ │ + ldr r7, [pc, #152] @ (c8e94 ) │ │ vcvt.u16.f16 q13, , #4 │ │ vrsra.u64 , q12, #4 │ │ vtbx.8 d29, {d11-d13}, d20 │ │ movs r6, r2 │ │ str r2, [sp, #600] @ 0x258 │ │ vsli.64 d27, d16, #60 @ 0x3c │ │ add r7, sp, #8 │ │ @@ -49253,32 +49253,32 @@ │ │ movs r7, r2 │ │ strh r0, [r7, r0] │ │ movs r7, r2 │ │ str r2, [r7, r7] │ │ movs r7, r2 │ │ str r6, [r2, r7] │ │ movs r7, r2 │ │ - subs r6, #13 │ │ + ldr r1, [r1, r2] │ │ vpaddl.s q14, q10 │ │ vmull.u q9, d28, d16 │ │ vqrdmlsh.s q10, , d4[0] │ │ movs r7, r2 │ │ bhi.n c91a4 │ │ movs r6, r2 │ │ stmia r2!, {r1, r4, r5} │ │ vsubw.u , q6, d20 │ │ - vsra.u64 d19, d18, #4 │ │ + vdup.32 d20, d30[1] │ │ vtbx.8 d26, {d12-d14}, d23 │ │ vrev16. d27, d2 │ │ @ instruction: 0xfffb8fbc │ │ - @ instruction: 0xfffcf8d1 │ │ - vtbx.8 d18, {d27-d30}, d12 │ │ + @ instruction: 0xfffc134d │ │ + vtbx.8 d18, {d28-d31}, d12 │ │ vabs.f , q11 │ │ movs r6, r2 │ │ - adds r1, #8 │ │ + ldr r3, [pc, #528] @ (c93a0 ) │ │ @ instruction: 0xfffca9bb │ │ vshr.u32 , q3, #4 │ │ vcvt.u32.f32 d24, d0, #5 │ │ vabal.u , d28, d0 │ │ mov r7, sp │ │ ldrb.w ip, [r1] │ │ ldrd r2, lr, [r1, #4] │ │ @@ -49536,30 +49536,30 @@ │ │ movs r7, r2 │ │ ldr r6, [pc, #896] @ (c97b8 ) │ │ movs r7, r2 │ │ ldr r6, [pc, #648] @ (c96c4 ) │ │ movs r7, r2 │ │ ldr r6, [pc, #504] @ (c9638 ) │ │ movs r7, r2 │ │ - subs r2, #181 @ 0xb5 │ │ + strb r1, [r6, r4] │ │ @ instruction: 0xfffcbf0c │ │ vtbx.8 d18, {d12-d13}, d8 │ │ @ instruction: 0xfffd4cd8 │ │ movs r7, r2 │ │ bmi.n c93e0 │ │ movs r6, r2 │ │ bkpt 0x00da │ │ vqrdmlsh.s q11, q14, d12[0] │ │ - vcvt.f32.u32 q9, q5, #4 │ │ + @ instruction: 0xfffc48d6 │ │ vqabs.s d26, d15 │ │ - vabal.u , d28, d27 │ │ - vtbl.8 d18, {d27}, d22 │ │ + vrev64. d17, d23 │ │ + vtbl.8 d18, {d28}, d22 │ │ vcgt.f , q0, #0 │ │ movs r6, r2 │ │ - cmp r5, #226 @ 0xe2 │ │ + ldr r0, [pc, #376] @ (c95ec ) │ │ vqshlu.s64 d26, d5, #60 @ 0x3c │ │ Address 0xc9476 is out of bounds. │ │ │ │ │ │ 000c9478 : │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -49807,30 +49807,30 @@ │ │ movs r7, r2 │ │ ldr r4, [pc, #144] @ (c9784 ) │ │ movs r7, r2 │ │ ldr r3, [pc, #920] @ (c9a90 ) │ │ movs r7, r2 │ │ ldr r3, [pc, #776] @ (c9a04 ) │ │ movs r7, r2 │ │ - adds r7, #249 @ 0xf9 │ │ + strh r5, [r6, r1] │ │ vcvt.f16.u16 , q0, #4 │ │ vpadal.u d18, d12 │ │ vshll.u32 q10, d12, #29 │ │ movs r7, r2 │ │ bcs.n c9724 │ │ movs r6, r2 │ │ pop {r1, r2, r3, r4} │ │ vcvt.u16.f16 d22, d0, #4 │ │ - @ instruction: 0xfffc2b9e │ │ + vqshlu.s32 d20, d10, #28 │ │ vsri.32 q13, , #4 │ │ - vpaddl.u , │ │ - vrsqrte.f32 q9, q13 │ │ + vqrdmulh.s q8, q6, d27[0] │ │ + @ instruction: 0xfffc25ea │ │ vcle.s d29, d4, #0 │ │ movs r6, r2 │ │ - cmp r3, #38 @ 0x26 │ │ + cmp sl, r4 │ │ vrsra.u64 q13, , #4 │ │ Address 0xc9732 is out of bounds. │ │ │ │ │ │ 000c9734 : │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -50093,30 +50093,30 @@ │ │ movs r7, r2 │ │ ldr r1, [pc, #304] @ (c9afc ) │ │ movs r7, r2 │ │ ldr r1, [pc, #56] @ (c9a08 ) │ │ movs r7, r2 │ │ ldr r0, [pc, #936] @ (c9d7c ) │ │ movs r7, r2 │ │ - adds r5, #33 @ 0x21 │ │ + ldr r7, [pc, #628] @ (c9c4c ) │ │ vqrshrn.u64 d27, q12, #4 │ │ vrsra.u64 d18, d20, #4 │ │ vabs.f q10, q2 │ │ movs r7, r2 │ │ ldmia r7!, {r1, r4, r5} │ │ movs r6, r2 │ │ cbnz r6, c99fc │ │ vshll.u32 q11, d24, #28 │ │ - vtbx.8 d18, {d28}, d6 │ │ + @ instruction: 0xfffc4342 │ │ vsra.u32 q13, , #4 │ │ - vshr.u32 d31, d7, #4 │ │ - vrsra.u32 d18, d2, #5 │ │ + @ instruction: 0xfffc0a93 │ │ + vrsra.u32 d18, d2, #4 │ │ @ instruction: 0xfffdceac │ │ movs r6, r2 │ │ - cmp r0, #78 @ 0x4e │ │ + cmn r2, r1 │ │ vrev16. d26, d1 │ │ Address 0xc9a0a is out of bounds. │ │ │ │ │ │ 000c9a0c : │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -50363,30 +50363,30 @@ │ │ movs r7, r2 │ │ mov ip, r2 │ │ movs r7, r2 │ │ mov r6, sl │ │ movs r7, r2 │ │ mov r2, r6 │ │ movs r7, r2 │ │ - adds r2, #105 @ 0x69 │ │ + ldr r4, [pc, #916] @ (ca024 , cv::Size_, cv::detail::CheckContext const&)@@Base+0x84>) │ │ vpadal.u , q0 │ │ vshr.u64 q9, q14, #4 │ │ vcge.f d20, d12, #0 │ │ movs r7, r2 │ │ ldmia r4, {r1, r3, r4, r5, r6} │ │ movs r6, r2 │ │ @ instruction: 0xb68e │ │ vqneg.s d22, d0 │ │ - vpadal.s d18, d14 │ │ + vrev32. d20, d10 │ │ vqrdmlah.s , q14, d3[0] │ │ - vcvt.u16.f16 q15, , #4 │ │ - vshr.u32 q9, q5, #5 │ │ + vqshl.u64 q8, , #60 @ 0x3c │ │ + vshr.u32 q9, q5, #4 │ │ @ instruction: 0xfffdcbf4 │ │ movs r6, r2 │ │ - movs r5, #150 @ 0x96 │ │ + ands r2, r2 │ │ vqrdmlah.s , q6, d9[0] │ │ Address 0xc9cc2 is out of bounds. │ │ │ │ │ │ 000c9cc4 : │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -50640,30 +50640,30 @@ │ │ movs r7, r2 │ │ mvns r4, r0 │ │ movs r7, r2 │ │ bics r6, r0 │ │ movs r7, r2 │ │ muls r2, r4 │ │ movs r7, r2 │ │ - cmp r7, #153 @ 0x99 │ │ + ldr r2, [pc, #84] @ (c9fc0 , cv::Size_, cv::detail::CheckContext const&)@@Base+0x20>) │ │ vrsra.u64 , q8, #4 │ │ @ instruction: 0xfffc1e2c │ │ vsra.u64 d20, d16, #3 │ │ movs r7, r2 │ │ ldmia r1, {r1, r3, r5, r7} │ │ movs r6, r2 │ │ cbz r6, c9fee , cv::Size_, cv::detail::CheckContext const&)@@Base+0x4e> │ │ vsri.64 d22, d16, #4 │ │ - vrsra.u32 d18, d30, #4 │ │ + @ instruction: 0xfffc3dba │ │ @ instruction: 0xfffc9bf3 │ │ - vtbl.8 d30, {d28-d30}, d9 │ │ - @ instruction: 0xfffb1d84 │ │ + vabal.u q8, d12, d5 │ │ + @ instruction: 0xfffc1d84 │ │ vqshrn.u64 d28, q7, #3 │ │ movs r6, r2 │ │ - movs r2, #192 @ 0xc0 │ │ + subs r5, #60 @ 0x3c │ │ @ instruction: 0xfffc9b73 │ │ Address 0xc9f9e is out of bounds. │ │ │ │ │ │ 000c9fa0 , cv::Size_, cv::detail::CheckContext const&)@@Base>: │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -50913,30 +50913,30 @@ │ │ movs r7, r2 │ │ lsrs r0, r5 │ │ movs r7, r2 │ │ lsls r2, r5 │ │ movs r7, r2 │ │ lsls r6, r0 │ │ movs r7, r2 │ │ - cmp r4, #189 @ 0xbd │ │ + bx r7 │ │ vsra.u32 d27, d4, #4 │ │ @ instruction: 0xfffc1b50 │ │ vqrdmlah.s , , d20[0] │ │ movs r7, r2 │ │ stmia r6!, {r1, r2, r3, r6, r7} │ │ movs r6, r2 │ │ sub sp, #392 @ 0x188 │ │ vsra.u64 q11, q2, #4 │ │ - vrev64. q9, q9 │ │ + @ instruction: 0xfffc3ade │ │ vqshrn.u64 d25, , #4 │ │ - vqshl.u64 d30, d21, #60 @ 0x3c │ │ - @ instruction: 0xfffb1ab0 │ │ + vrshr.u32 d16, d17, #4 │ │ + @ instruction: 0xfffc1ab0 │ │ vclt.f q14, q5, #0 │ │ movs r6, r2 │ │ - subs r4, r5, #7 │ │ + subs r2, #104 @ 0x68 │ │ @ instruction: 0xfffc989f │ │ Address 0xca26a is out of bounds. │ │ │ │ │ │ 000ca26c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -51145,18 +51145,18 @@ │ │ subs r6, #24 │ │ movs r7, r2 │ │ subs r5, #248 @ 0xf8 │ │ movs r7, r2 │ │ ldrb r2, [r6, #18] │ │ vqrdmulh.s , q14, d4[0] │ │ movs r7, r2 │ │ - subs r6, r2, #0 │ │ - vqshlu.s64 , , #60 @ 0x3c │ │ + subs r0, #146 @ 0x92 │ │ + vsra.u32 , , #4 │ │ vdup.32 , d0[1] │ │ - @ instruction: 0xfffc1dd8 │ │ + vqrshrun.s64 d19, q2, #4 │ │ vpadal.u d25, d13 │ │ @ instruction: 0xfffc9d28 │ │ vmull.u , d27, d8 │ │ movs r7, r2 │ │ stmia r3!, {r2, r4, r7} │ │ movs r6, r2 │ │ ldrb r4, [r1, #15] │ │ @@ -51365,18 +51365,18 @@ │ │ subs r3, #196 @ 0xc4 │ │ movs r7, r2 │ │ subs r3, #164 @ 0xa4 │ │ movs r7, r2 │ │ ldrb r6, [r3, #9] │ │ @ instruction: 0xfffc3b70 │ │ movs r7, r2 │ │ - subs r2, r0, r7 │ │ - vclz.i d19, d7 │ │ + adds r6, #62 @ 0x3e │ │ + @ instruction: 0xfffc4f03 │ │ vtbx.8 d23, {d28-d29}, d28 │ │ - vtbl.8 d17, {d28-d31}, d4 │ │ + vpadal.s d19, d0 │ │ vsri.32 d25, d25, #4 │ │ @ instruction: 0xfffc9ad4 │ │ vtbl.8 d23, {d27-d28}, d14 │ │ vtbx.8 d19, {d12-d14}, d0 │ │ movs r7, r2 │ │ │ │ 000ca700 : │ │ @@ -51573,18 +51573,18 @@ │ │ subs r1, #104 @ 0x68 │ │ movs r7, r2 │ │ subs r1, #72 @ 0x48 │ │ movs r7, r2 │ │ ldrb r2, [r0, #0] │ │ vqshrn.u64 d19, q2, #4 │ │ movs r7, r2 │ │ - adds r6, r4, r5 │ │ - vpaddl.s d19, d27 │ │ + adds r3, #226 @ 0xe2 │ │ + vmull.u q10, d28, d23 │ │ vqshl.u64 d23, d0, #60 @ 0x3c │ │ - vtbl.8 d17, {d12-d13}, d24 │ │ + vsubw.u , q14, d20 │ │ vsra.u64 , , #4 │ │ vqshrun.s64 d19, q5, #4 │ │ movs r7, r2 │ │ │ │ 000ca920 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -51741,15 +51741,15 @@ │ │ adds r7, #106 @ 0x6a │ │ movs r7, r2 │ │ adds r7, #70 @ 0x46 │ │ movs r7, r2 │ │ strb r0, [r0, #24] │ │ vqshl.u32 d19, d2, #28 │ │ movs r7, r2 │ │ - asrs r4, r4, #29 │ │ + adds r1, #224 @ 0xe0 │ │ vtbx.8 d29, {d12-d15}, d7 │ │ vqshlu.s32 , q5, #28 │ │ movs r7, r2 │ │ │ │ 000caad4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -51906,15 +51906,15 @@ │ │ adds r5, #182 @ 0xb6 │ │ movs r7, r2 │ │ adds r5, #146 @ 0x92 │ │ movs r7, r2 │ │ strb r4, [r1, #17] │ │ vsli.32 , q7, #28 │ │ movs r7, r2 │ │ - asrs r0, r6, #22 │ │ + adds r0, #44 @ 0x2c │ │ vqshl.u64 , q13, #60 @ 0x3c │ │ vclz.i d19, d22 │ │ movs r7, r2 │ │ │ │ 000cac88 : │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -52124,18 +52124,18 @@ │ │ adds r3, #196 @ 0xc4 │ │ movs r7, r2 │ │ adds r3, #164 @ 0xa4 │ │ movs r7, r2 │ │ strb r6, [r3, #9] │ │ vrsra.u32 , q8, #4 │ │ movs r7, r2 │ │ - asrs r2, r0, #15 │ │ - vmull.u q9, d28, d7 │ │ + cmp r6, #62 @ 0x3e │ │ + vqabs.s d20, d3 │ │ @ instruction: 0xfffc71ec │ │ - vsubw.u , q14, d4 │ │ + @ instruction: 0xfffc2e00 │ │ vcvt.f16.u16 d24, d25, #4 │ │ vrshr.u32 , q11, #4 │ │ movs r7, r2 │ │ │ │ 000caec4 : │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -52330,18 +52330,18 @@ │ │ adds r1, #164 @ 0xa4 │ │ movs r7, r2 │ │ adds r1, #132 @ 0x84 │ │ movs r7, r2 │ │ strb r6, [r7, #0] │ │ vsra.u32 , q0, #4 │ │ movs r7, r2 │ │ - asrs r2, r4, #6 │ │ - vtbx.8 d18, {d12-d14}, d23 │ │ + cmp r4, #30 │ │ + vclz.i q10, │ │ vqrdmlsh.s q11, q14, d12[0] │ │ - vrev16. , q10 │ │ + vtbx.8 d18, {d28-d31}, d16 │ │ vshll.u32 q12, d9, #28 │ │ vshr.u32 , q3, #4 │ │ movs r7, r2 │ │ │ │ 000cb0e4 : │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -52537,18 +52537,18 @@ │ │ cmp r7, #128 @ 0x80 │ │ movs r7, r2 │ │ cmp r7, #96 @ 0x60 │ │ movs r7, r2 │ │ ldr r2, [r3, #96] @ 0x60 │ │ @ instruction: 0xfffc2f2c │ │ movs r7, r2 │ │ - lsrs r6, r7, #29 │ │ - vtbx.8 d18, {d12}, d3 │ │ + cmp r1, #250 @ 0xfa │ │ + vrshr.u64 d20, d31, #4 │ │ @ instruction: 0xfffc6da8 │ │ - vqrdmlsh.s q8, q6, d0[0] │ │ + @ instruction: 0xfffc29bc │ │ vqshl.u64 q12, , #60 @ 0x3c │ │ @ instruction: 0xfffc2e2c │ │ movs r7, r2 │ │ │ │ 000cb30c , cv::detail::CheckContext const&)@@Base>: │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -52742,18 +52742,18 @@ │ │ cmp r5, #88 @ 0x58 │ │ movs r7, r2 │ │ cmp r5, #56 @ 0x38 │ │ movs r7, r2 │ │ ldr r2, [r6, #60] @ 0x3c │ │ @ instruction: 0xfffc2d04 │ │ movs r7, r2 │ │ - lsrs r6, r2, #21 │ │ - vqshlu.s32 d18, d11, #28 │ │ + movs r7, #210 @ 0xd2 │ │ + vshr.u64 d20, d7, #4 │ │ vtbl.8 d22, {d28-d31}, d0 │ │ - vcvt.u16.f16 d16, d8, #4 │ │ + vqshl.u64 d18, d4, #60 @ 0x3c │ │ @ instruction: 0xfffc85cd │ │ vdup.32 d18, d12[1] │ │ movs r7, r2 │ │ │ │ 000cb52c , std::__ndk1::allocator > const&, cv::detail::CheckContext const&)@@Base>: │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -52936,18 +52936,18 @@ │ │ cmp r3, #80 @ 0x50 │ │ movs r7, r2 │ │ cmp r3, #48 @ 0x30 │ │ movs r7, r2 │ │ ldr r2, [r5, #28] │ │ @ instruction: 0xfffc2afc │ │ movs r7, r2 │ │ - lsrs r6, r1, #13 │ │ - vsri.32 d18, d3, #4 │ │ + movs r5, #202 @ 0xca │ │ + @ instruction: 0xfffc3e8f │ │ vqrshrn.u64 d22, q12, #4 │ │ - @ instruction: 0xfffc0b10 │ │ + vabal.u q9, d28, d12 │ │ @ instruction: 0xfffc83c5 │ │ vtbl.8 d18, {d12-d14}, d4 │ │ movs r7, r2 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r1 │ │ ldr r1, [pc, #44] @ (cb768 , std::__ndk1::allocator > const&, cv::detail::CheckContext const&)@@Base+0x23c>) │ │ @@ -53461,15 +53461,15 @@ │ │ strb r7, [r4, #7] │ │ vtbx.8 d24, {d28}, d0 │ │ vtbx.8 d30, {d12-d13}, d10 │ │ vqrdmlah.s , q14, d0[0] │ │ vsri.64 d18, d24, #4 │ │ movs r7, r2 │ │ movs r0, #100 @ 0x64 │ │ - vsra.u32 d28, d13, #3 │ │ + @ instruction: 0xfffddb99 │ │ vsra.u32 q8, , #5 │ │ vtbl.8 d20, {d13}, d27 │ │ vtbx.8 d24, {d12-d13}, d2 │ │ vsli.64 d27, d16, #60 @ 0x3c │ │ add r7, sp, #8 │ │ mov r5, r0 │ │ ldrb r0, [r2, #0] │ │ @@ -53953,16 +53953,16 @@ │ │ movs r7, r2 │ │ b.n cc8a8 , std::__ndk1::allocator > const&)@@Base+0x370> │ │ vqshrun.s64 d20, q7, #4 │ │ vcvtp.u32.f32 q12, q9 │ │ vrev64. d24, d20 │ │ vqshl.u32 q13, q4, #27 │ │ movs r6, r2 │ │ - bmi.n cc1ac , std::__ndk1::allocator > const&, bool, cv::Param, void*) const@@Base+0xa38> │ │ - vqshrun.s64 d20, q15, #5 │ │ + vrsqrts.f16 , q13, │ │ + ldr r0, [pc, #248] @ (cc2ac ) │ │ vcvtm.s32.f32 d24, d2 │ │ vshr.u32 q9, q15, #4 │ │ movs r7, r2 │ │ movs r0, #90 @ 0x5a │ │ movs r7, r2 │ │ movs r0, #4 │ │ movs r7, r2 │ │ @@ -54754,17 +54754,17 @@ │ │ movs r2, #1 │ │ ldr r0, [r0, #0] │ │ ldr r1, [pc, #20] @ (cc9f8 , std::__ndk1::allocator > const&)@@Base+0x4c0>) │ │ add r1, pc │ │ strb.w r2, [r0], #4 │ │ blx 231280 <__emutls_get_address@@Base+0x43f8> │ │ b.n cca0a , std::__ndk1::allocator > const&)@@Base+0x4d2> │ │ - ldmia r6, {r0, r1, r2, r4, r6, r7} │ │ - @ instruction: 0xfffbccf5 │ │ - vrsra.u32 q8, q9, #5 │ │ + ldrd pc, pc, [r3, #-1004] @ 0x3ec │ │ + b.n cc8da , std::__ndk1::allocator > const&)@@Base+0x3a2> │ │ + vqrdmulh.s , , d30[0] │ │ vrev16. d31, d8 │ │ movs r4, r6 │ │ add.w r8, sp, #72 @ 0x48 │ │ mov r1, r8 │ │ bl ce838 │ │ ldr r4, [sp, #96] @ 0x60 │ │ cbz r4, cca36 , std::__ndk1::allocator > const&)@@Base+0x4fe> │ │ @@ -55535,15 +55535,15 @@ │ │ add r2, pc │ │ ldr r1, [r0, #0] │ │ mov r0, r6 │ │ ldr r2, [r2, #0] │ │ blx 230720 <__emutls_get_address@@Base+0x3898> │ │ b.n cd2f8 , std::__ndk1::allocator > const&, char, char) const@@Base+0x4e0> │ │ nop │ │ - stmia r6!, {r0, r1, r2, r7} │ │ + b.n cd422 , std::__ndk1::allocator > const&, char, char) const@@Base+0x60a> │ │ vcvtm.u32.f32 d24, d9 │ │ vsri.64 , , #5 │ │ vclz.i d27, d31 │ │ vshr.u32 d18, d28, #4 │ │ blx 230710 <__emutls_get_address@@Base+0x3888> │ │ ldr r1, [pc, #624] @ (cd4a0 , std::__ndk1::allocator > const&, char, char) const@@Base+0x688>) │ │ mov r6, r0 │ │ @@ -55768,35 +55768,35 @@ │ │ itt ne │ │ ldrne r0, [sp, #216] @ 0xd8 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ asrs r4, r7, #9 │ │ movs r7, r2 │ │ ldr r6, [pc, #864] @ (cd7d0 , std::__ndk1::allocator > const&, std::__ndk1::basic_string, std::__ndk1::allocator > const&)@@Base+0x14>) │ │ - vsri.32 d28, d11, #4 │ │ + @ instruction: 0xfffcde97 │ │ vcvtp.u32.f32 , q15 │ │ @ instruction: 0xfffc0fa6 │ │ movs r7, r2 │ │ lsrs r0, r5, #30 │ │ movs r7, r2 │ │ strh r1, [r6, #20] │ │ vrecpe.u32 d27, d7 │ │ vrsra.u64 , , #4 │ │ @ instruction: 0xfffc4e00 │ │ - @ instruction: 0xfffcc343 │ │ + @ instruction: 0xfffcddbf │ │ vrshr.u32 d23, d6, #5 │ │ vqrdmlah.s q8, q14, d14[0] │ │ movs r7, r2 │ │ lsrs r0, r2, #27 │ │ movs r7, r2 │ │ strh r5, [r1, #14] │ │ vcvtm.s32.f32 d27, d19 │ │ vrshr.u64 , , #4 │ │ vcvt.u16.f16 d20, d12, #4 │ │ - vrshr.u32 q14, , #4 │ │ + @ instruction: 0xfffcdcdb │ │ vsra.u32 d23, d18, #5 │ │ vqrdmulh.s q8, q14, d26[0] │ │ movs r7, r2 │ │ lsrs r4, r5, #23 │ │ movs r7, r2 │ │ asrs r2, r2, #1 │ │ movs r7, r2 │ │ @@ -56021,15 +56021,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #56] @ 0x38 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ lsrs r2, r2, #15 │ │ movs r7, r2 │ │ - bkpt 0x00fd │ │ + bls.n cd816 , std::__ndk1::allocator > const&, std::__ndk1::basic_string, std::__ndk1::allocator > const&)@@Base+0x5a> │ │ @ instruction: 0xfffb09de │ │ movs r7, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ ldr r5, [r0, #0] │ │ mov r4, r0 │ │ @@ -57119,16 +57119,16 @@ │ │ str.w sl, [sp] │ │ adds r3, r0, #1 │ │ mov r0, r8 │ │ blx 2311d0 <__emutls_get_address@@Base+0x4348> │ │ b.n ce20e │ │ nop │ │ strh r6, [r5, #0] │ │ - @ instruction: 0xfffbfbdf │ │ - vcvta.s32.f32 d18, d0 │ │ + vqshlu.s32 , , #27 │ │ + vrev64. d18, d0 │ │ strh.w r0, [sp, #8] │ │ ldr r1, [pc, #124] @ (ce28c ) │ │ mov r0, r8 │ │ add r1, pc │ │ blx 231320 <__emutls_get_address@@Base+0x4498> │ │ cmp r0, #0 │ │ beq.w ce0ca │ │ @@ -57159,23 +57159,23 @@ │ │ ldrne r0, [sp, #32] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ lsls r4, r1, #10 │ │ movs r7, r2 │ │ ldr r3, [sp, #304] @ 0x130 │ │ vclz.i d21, d6 │ │ - vtbx.8 d25, {d11-d13}, d24 │ │ - vrsqrte.u32 d27, d19 │ │ + vrsqrte.u32 , q10 │ │ + vcvt.u32.f32 d28, d15, #5 │ │ @ instruction: 0xfffbe9d4 │ │ vrev64. d19, d3 │ │ - @ instruction: 0xfffc9b5a │ │ + vsli.64 , q3, #60 @ 0x3c │ │ vsli.32 q13, , #27 │ │ vqrdmlah.s , q6, d30[0] │ │ movs r6, r2 │ │ - cbz r7, ce2d0 │ │ + ldmia r5!, {r0, r1, r7} │ │ vqshrun.s64 d30, q13, #5 │ │ vcvt.f32.u32 d18, d27, #4 │ │ vsli.64 d27, d16, #60 @ 0x3c │ │ add r7, sp, #8 │ │ mov r5, r0 │ │ ldrb r0, [r2, #0] │ │ mov ip, r1 │ │ @@ -58028,16 +58028,16 @@ │ │ ldr.w r8, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (cebc4 ) │ │ add r0, pc │ │ bl a91f8 │ │ - mcr 15, 3, pc, cr9, cr11, {7} @ │ │ - push {r4, r5, r6, r7, lr} │ │ + lsrs r5, r4, #3 │ │ + vsli.64 , q8, #60 @ 0x3c │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ mov r4, r0 │ │ ldrb r0, [r0, #12] │ │ cbnz r0, cebfa │ │ ldrd r0, r1, [r4, #4] │ │ ldr r5, [r0, #0] │ │ @@ -58068,16 +58068,16 @@ │ │ mov r0, r4 │ │ pop {r4, r6, r7, pc} │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (cec28 ) │ │ add r0, pc │ │ bl a91f8 │ │ - mcr 15, 0, pc, cr5, cr11, {7} @ │ │ - push {r4, r5, r6, r7, lr} │ │ + lsrs r1, r0, #2 │ │ + vsli.64 , q8, #60 @ 0x3c │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ ldr r6, [r0, #8] │ │ cmp r6, r1 │ │ beq.n ceca8 │ │ mov r8, r1 │ │ mov r9, r0 │ │ @@ -63812,21 +63812,21 @@ │ │ add r0, sp, #532 @ 0x214 │ │ blx 2313c0 <__emutls_get_address@@Base+0x4538> │ │ add r0, sp, #588 @ 0x24c │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ pop {r3, r7} │ │ movs r6, r2 │ │ - ldrb r6, [r2, #13] │ │ + str r5, [sp, #840] @ 0x348 │ │ vtbx.8 d31, {d11-d14}, d30 │ │ vtbl.8 d17, {d10-d11}, d20 │ │ vqshlu.s64 d19, d8, #59 @ 0x3b │ │ vtbx.8 d31, {d11-d14}, d14 │ │ vtbl.8 d17, {d10-d11}, d4 │ │ - vrshr.u32 d27, d29, #5 │ │ + @ instruction: 0xfffbccb9 │ │ vtbl.8 d31, {d11-d14}, d30 │ │ vtbx.8 d17, {d26}, d20 │ │ @ instruction: 0xfffbb8f4 │ │ movs r6, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -63929,16 +63929,16 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r0, sp, #20 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ @ instruction: 0xb7b8 │ │ movs r6, r2 │ │ bl ffef39e6 <__cxa_new_handler@@Base+0xffcafdf6> │ │ - str r7, [r6, r5] │ │ - vsra.u32 , , #5 │ │ + ldr r3, [r6, #60] @ 0x3c │ │ + @ instruction: 0xfffb6bfb │ │ vqshl.u32 d27, d8, #27 │ │ movs r6, r2 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ ldr r5, [r0, #4] │ │ mov r4, r0 │ │ cbz r5, d2a20 │ │ @@ -64143,15 +64143,15 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ push {r1, lr} │ │ movs r6, r2 │ │ b.n d3274 const&, cv::TermCriteria)@@Base+0x630> │ │ - vqshl.u32 d24, d21, #27 │ │ + vsra.u64 d26, d17, #5 │ │ vrecpe.f32 d17, d2 │ │ vrsqrte.u32 , q0 │ │ movs r6, r2 │ │ │ │ 000d2c44 const&, cv::TermCriteria)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -70480,15 +70480,15 @@ │ │ strb r4, [r1, #24] │ │ movs r6, r2 │ │ strb r0, [r3, #20] │ │ movs r6, r2 │ │ mcr2 0, 5, r0, cr14, cr5, {0} │ │ ldc2l 0, cr0, [r2, #-84] @ 0xffffffac │ │ bvc.n d6ca6 │ │ - vsri.64 , q10, #5 │ │ + vcvt.u32.f32 q11, q8, #5 │ │ @ instruction: 0xfffb5d9e │ │ Address 0xd6d4e is out of bounds. │ │ │ │ │ │ 000d6d50 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -71137,29 +71137,29 @@ │ │ bl d7448 │ │ add r0, sp, #96 @ 0x60 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strb r4, [r7, #1] │ │ movs r6, r2 │ │ - ldr r1, [r2, #4] │ │ + strh r5, [r1, #22] │ │ vcvt.u16.f16 d30, d4, #5 │ │ - vshr.u64 d19, d17, #6 │ │ + vtbl.8 d20, {d10-d13}, d29 │ │ vshr.u32 q15, q7, #5 │ │ vcvt.f32.u32 d30, d16, #5 │ │ - vzip.32 , │ │ + vdup.16 q10, d9[2] │ │ vqrdmulh.s q13, , d7[0] │ │ vcvt.u16.f16 q15, q2, #5 │ │ - vshr.u64 , , #6 │ │ - @ instruction: 0xfffb5b74 │ │ + vtbx.8 d20, {d10-d13}, d29 │ │ + vsli.64 , q8, #59 @ 0x3b │ │ vcvt.u16.f16 d30, d20, #5 │ │ - vshr.u64 , , #6 │ │ - vsra.u32 d19, d6, #5 │ │ + vtbx.8 d20, {d10-d13}, d13 │ │ + @ instruction: 0xfffb4b92 │ │ @ instruction: 0xfffbecf4 │ │ - vshr.u64 d19, d1, #6 │ │ + vtbl.8 d20, {d10-d13}, d13 │ │ @ instruction: 0xfffb6d98 │ │ movs r6, r2 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ ldr r5, [r0, #0] │ │ mov r4, r0 │ │ cbz r5, d746e │ │ @@ -71507,20 +71507,20 @@ │ │ bl d7448 │ │ add r0, sp, #104 @ 0x68 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldr r2, [r4, #64] @ 0x40 │ │ movs r6, r2 │ │ - str r1, [r1, #68] @ 0x44 │ │ + ldrb r5, [r0, #27] │ │ vsri.32 , , #5 │ │ - vmull.u q9, d28, d25 │ │ + vqabs.s d20, d21 │ │ vcvtp.s32.f32 d26, d24 │ │ vsli.32 , , #26 │ │ - @ instruction: 0xfffc2dd7 │ │ + vqrshrun.s64 d20, , #4 │ │ vqrshrn.u64 d22, q0, #5 │ │ movs r6, r2 │ │ │ │ 000d7800 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -71713,17 +71713,17 @@ │ │ b.n d79f0 │ │ add r0, sp, #100 @ 0x64 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ str r2, [r2, #120] @ 0x78 │ │ movs r6, r2 │ │ - str r0, [r1, #32] │ │ + ldrb r4, [r0, #18] │ │ vsli.64 , , #59 @ 0x3b │ │ - vtbx.8 d18, {d12-d14}, d17 │ │ + vsri.64 q10, , #4 │ │ vcvt.s32.f32 d22, d8 │ │ movs r6, r2 │ │ │ │ 000d7a10 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -71817,15 +71817,15 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ str r2, [r0, #104] @ 0x68 │ │ movs r6, r2 │ │ ldr r6, [sp, #88] @ 0x58 │ │ vshll.i32 , d10, #32 │ │ - vqrshrn.u64 d18, , #5 │ │ + vrsra.u64 q10, , #5 │ │ vcvt.f32.s32 d22, d0 │ │ movs r6, r2 │ │ │ │ 000d7b18 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -71940,17 +71940,17 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #172 @ 0xac │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ str r0, [r7, #84] @ 0x54 │ │ movs r6, r2 │ │ - bl 4c3c3c <__cxa_new_handler@@Base+0x28004c> │ │ - add sp, #324 @ 0x144 │ │ - @ instruction: 0xfffb2897 │ │ + lsrs r7, r4, #25 │ │ + vshr.u32 , , #5 │ │ + vrsra.u32 d20, d3, #5 │ │ vrsqrte.u32 d22, d28 │ │ movs r6, r2 │ │ │ │ 000d7c54 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ @@ -72084,16 +72084,16 @@ │ │ add r0, sp, #220 @ 0xdc │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ str r4, [r7, #64] @ 0x40 │ │ movs r6, r2 │ │ adds r1, r5, r0 │ │ - vrshr.u64 , q6, #4 │ │ - vrint?.f32 q9, │ │ + vcvt.u16.f16 q8, q4, #4 │ │ + vsra.u64 d20, d29, #5 │ │ vcvtm.s32.f32 q11, q4 │ │ movs r6, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ mov r4, r0 │ │ ldrb r0, [r0, #4] │ │ @@ -75522,16 +75522,16 @@ │ │ b.n da4ca const&, void*, int, int)@@Base+0x582> │ │ add r0, sp, #24 │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bl a8d68 │ │ adcs r6, r0 │ │ movs r6, r2 │ │ - lsrs r0, r4, #28 │ │ - vsli.32 d30, d24, #27 │ │ + cmp r1, #156 @ 0x9c │ │ + @ instruction: 0xfffbffb4 │ │ vtbl.8 d27, {d10-d13}, d17 │ │ vdup.8 d19, d20[5] │ │ movs r6, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #44 @ 0x2c │ │ @@ -75667,15 +75667,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #36] @ 0x24 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ subs r3, #168 @ 0xa8 │ │ movs r6, r2 │ │ - stmia r4!, {r1, r3, r5, r6, r7} │ │ + svc 102 @ 0x66 │ │ vshll.u32 , d23, #26 │ │ vtbx.8 d27, {d27-d28}, d3 │ │ vtbx.8 d19, {d27-d29}, d30 │ │ movs r6, r2 │ │ movs r5, #185 @ 0xb9 │ │ vshll.u32 , d5, #28 │ │ vtbl.8 d27, {d27-d28}, d17 │ │ @@ -76507,15 +76507,15 @@ │ │ vqshl.u32 d30, d0, #27 │ │ vcvtn.s32.f32 , │ │ vrecpe.u32 , q8 │ │ movs r6, r2 │ │ ldmia r4, {r0, r1, r3, r4} │ │ vcvt.f32.u32 q15, q15 │ │ vcvtn.s32.f32 d27, d29 │ │ - vrsra.u64 , q12, #5 │ │ + vcvt.f32.u32 q9, q10, #5 │ │ vqshl.u32 d30, d22, #27 │ │ vsra.u32 , , #5 │ │ vcvtp.s32.f32 q14, q11 │ │ movs r5, r2 │ │ │ │ 000daf54 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -76803,19 +76803,19 @@ │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ stmia r1!, {r1, r2, r3, r6, r7} │ │ movs r5, r2 │ │ adds r1, #62 @ 0x3e │ │ movs r6, r2 │ │ - bkpt 0x0020 │ │ + bhi.n db184 │ │ vrsra.u64 q15, q1, #6 │ │ vcvt.f32.u32 d26, d1, #5 │ │ - vcvtp.u32.f32 , │ │ - vrsra.u64 d30, d16, #6 │ │ + vcvt.u16.f16 q8, , #5 │ │ + vrsra.u64 d30, d16, #5 │ │ vqrdmulh.s q13, , d31[0] │ │ vsri.64 d21, d20, #5 │ │ movs r6, r2 │ │ @ instruction: 0xf949ffff │ │ pldw [r3, #4095] @ 0xfff │ │ cmp r7, #148 @ 0x94 │ │ movs r6, r2 │ │ @@ -77051,16 +77051,16 @@ │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ bkpt 0x00c6 │ │ movs r5, r2 │ │ cmp r6, #36 @ 0x24 │ │ movs r6, r2 │ │ - vminnm.f16 , q10, q13 │ │ - stmia r6!, {r0, r1, r4, r7} │ │ + adds r0, r6, r6 │ │ + vcvtn.s32.f32 d30, d15 │ │ vtbl.8 d26, {d10-d13}, d29 │ │ @ instruction: 0xfffb2e00 │ │ movs r6, r2 │ │ │ │ 000db4f4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -77404,16 +77404,16 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #72 @ 0x48 │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ cmp r3, #154 @ 0x9a │ │ movs r6, r2 │ │ - bcs.n db9b8 │ │ - vrintn.f32 , │ │ + ldcl 15, cr15, [r8], #1000 @ 0x3e8 │ │ + strb r5, [r4, #17] │ │ vtbx.8 d26, {d11}, d9 │ │ @ instruction: 0xfffbce21 │ │ vcvtm.u32.f32 d23, d17 │ │ vcvt.u32.f32 d26, d5 │ │ vcvt.u32.f32 d20, d4, #5 │ │ movs r6, r2 │ │ bl 4858da <__cxa_new_handler@@Base+0x241cea> │ │ @@ -77814,18 +77814,18 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ movs r4, #216 @ 0xd8 │ │ movs r6, r2 │ │ str r2, [r1, #124] @ 0x7c │ │ - vrshr.u32 , q4, #6 │ │ + @ instruction: 0xfffa2cd4 │ │ vcvtm.s32.f32 q13, │ │ @ instruction: 0xfffbd8fd │ │ - vrshr.u32 d17, d20, #5 │ │ + @ instruction: 0xfffb2cb0 │ │ vcvtm.s32.f32 d26, d25 │ │ vrsqrte.u32 q9, q4 │ │ movs r6, r2 │ │ bmi.n dbc94 │ │ bmi.n dbc96 │ │ bmi.n dbc98 │ │ bmi.n dbc9a │ │ @@ -78138,15 +78138,15 @@ │ │ addw r1, sp, #1292 @ 0x50c │ │ str r0, [sp, #0] │ │ mvn.w r0, #214 @ 0xd6 │ │ blx 2306b0 <__emutls_get_address@@Base+0x3828> │ │ push {r3, r4, r5, r6} │ │ movs r5, r2 │ │ ldr r6, [r6, r2] │ │ - vsra.u64 q8, q8, #6 │ │ + vdup.16 , d28[2] │ │ vcvt.u32.f32 , , #5 │ │ vqshrun.s64 d25, q0, #5 │ │ negs r5, r0 │ │ ldr r2, [sp, #68] @ 0x44 │ │ mov r0, r5 │ │ mov r1, r6 │ │ blx 231540 <__emutls_get_address@@Base+0x46b8> │ │ @@ -78647,17 +78647,17 @@ │ │ movs r0, r0 │ │ movs r2, r0 │ │ movs r0, r0 │ │ movs r3, r0 │ │ movs r0, r0 │ │ movs r3, #152 @ 0x98 │ │ movs r6, r2 │ │ - @ instruction: 0xb800 │ │ - vqrdmulh.s , q5, d10[0] │ │ - @ instruction: 0xfffa9ab5 │ │ + bcs.n dc6c0 │ │ + vrintp.f32 , q3 │ │ + @ instruction: 0xfffb9ab5 │ │ vcvt.u16.f16 , q14, #5 │ │ movs r6, r2 │ │ │ │ 000dc5d4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -78987,25 +78987,25 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #152 @ 0x98 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ b.n dc93c │ │ subs r2, r0, r3 │ │ movs r6, r2 │ │ - ldmia r7, {r0, r1, r3, r5, r6, r7} │ │ - vrshr.u64 q8, q11, #6 │ │ + @ instruction: 0xea67fffa │ │ + lsls r6, r6, #11 │ │ vpadal.u , │ │ @ instruction: 0xfffb8d24 │ │ vrsra.u32 q8, q7, #6 │ │ vqabs.s , │ │ vtbl.8 d25, {d27}, d8 │ │ vrsra.u32 d16, d10, #6 │ │ vqabs.s d25, d5 │ │ - @ instruction: 0xfffbf9d7 │ │ - vrsra.u32 d16, d28, #6 │ │ + vsri.32 , , #5 │ │ + vrsra.u32 d16, d28, #5 │ │ vqabs.s d25, d23 │ │ vqshrn.u64 d17, q14, #5 │ │ movs r6, r2 │ │ │ │ 000dc980 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -79740,15 +79740,15 @@ │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ add r2, pc, #96 @ (adr r2, dd15c ) │ │ movs r5, r2 │ │ asrs r6, r0, #4 │ │ movs r6, r2 │ │ - cbnz r1, dd132 │ │ + bmi.n dd16e │ │ vrint?.f32 , q9 │ │ vqrdmulh.s , , d19[0] │ │ vcvtn.u32.f32 q13, q10 │ │ movs r5, r2 │ │ add r1, pc, #640 @ (adr r1, dd394 ) │ │ movs r5, r2 │ │ strb r3, [r4, #15] │ │ @@ -80107,15 +80107,15 @@ │ │ sub.w r0, r7, #88 @ 0x58 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ lsrs r0, r6, #29 │ │ movs r6, r2 │ │ ldr r3, [r6, #104] @ 0x68 │ │ - vrintn.f32 q14, q7 │ │ + vqrdmlah.s , q13, d10[0] │ │ vqrshrn.u64 d25, , #6 │ │ vdup.8 q8, d8[5] │ │ movs r6, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ @@ -80218,15 +80218,15 @@ │ │ bl dd61c │ │ bl c71d0 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (dd628 ) │ │ add r0, pc │ │ bl a91f8 │ │ - lsls r5, r0, #16 │ │ + subs r1, r0, #2 │ │ Address 0xdd62a is out of bounds. │ │ │ │ │ │ 000dd62c : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #24 │ │ @@ -80561,19 +80561,19 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ lsrs r2, r2, #2 │ │ movs r6, r2 │ │ ldr r5, [r5, #56] @ 0x38 │ │ - vtbx.8 d30, {d11-d12}, d0 │ │ - vtbl.8 d22, {d10-d12}, d2 │ │ + vrsra.u64 d16, d28, #5 │ │ + vtbl.8 d22, {d11-d13}, d2 │ │ @ instruction: 0xfffa3ff7 │ │ - vqshrn.u64 d30, q7, #6 │ │ - vtbx.8 d22, {d26-d27}, d16 │ │ + vrsra.u64 d16, d10, #6 │ │ + vtbx.8 d22, {d27-d28}, d16 │ │ vrintp.f32 d16, d2 │ │ movs r6, r2 │ │ │ │ 000dd9b8 )@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -80686,17 +80686,17 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ lsls r4, r3, #27 │ │ movs r6, r2 │ │ - bls.n dda3a )@@Base+0x82> │ │ - vtbx.8 d30, {d10}, d6 │ │ - vtbl.8 d22, {d10-d11}, d8 │ │ + bl ffcf7af4 <__cxa_new_handler@@Base+0xffab3f04> │ │ + lsls r2, r0, #11 │ │ + vtbl.8 d22, {d11-d12}, d8 │ │ vsli.64 q8, q6, #58 @ 0x3a │ │ movs r6, r2 │ │ │ │ 000ddb0c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ @@ -80879,16 +80879,16 @@ │ │ vcvt.f32.u32 q11, q15 │ │ vcvt.u32.f32 d24, d28, #6 │ │ vrsra.u64 q12, , #5 │ │ vcvt.f32.u32 q11, q7 │ │ vqshl.u32 q14, , #26 │ │ vrsra.u64 d24, d27, #5 │ │ vcvt.f32.u32 d22, d30 │ │ - @ instruction: 0xfffafcf5 │ │ - vsri.32 d24, d11, #6 │ │ + vqshl.u32 , , #26 │ │ + vsri.32 d24, d11, #5 │ │ vcvt.s32.f32 d22, d14 │ │ vrintx.f32 d16, d10 │ │ movs r6, r2 │ │ │ │ 000ddd18 &, cv::Point_&) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -81793,16 +81793,16 @@ │ │ itt ne │ │ strne.w r0, [r8, #12] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ @ instruction: 0xfb7c0015 │ │ @ instruction: 0xfad80015 │ │ ldrsh r3, [r2, r7] │ │ - vrsqrte.u32 q13, q11 │ │ - vqrdmlsh.s , q5, d9[0] │ │ + vqrdmlsh.s , , d18[0] │ │ + vtbx.8 d29, {d26-d27}, d5 │ │ Address 0xde64a is out of bounds. │ │ │ │ │ │ 000de64c >, int, std::__ndk1::vector >)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -82069,18 +82069,18 @@ │ │ beq.n de948 >, int, std::__ndk1::vector >)@@Base+0x2fc> │ │ ldr r0, [sp, #12] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ @ instruction: 0xfa480015 │ │ b.n def5e >, cv::Range, cv::Range) const@@Base+0x2f2> │ │ vdup.8 q10, d29[5] │ │ - @ instruction: 0xfffabbd9 │ │ + vqshlu.s32 , , #26 │ │ vrintz.f32 d24, d3 │ │ vdup.8 q10, d11[5] │ │ - @ instruction: 0xfffabbb7 │ │ + vqshlu.s32 d29, d19, #26 │ │ vqshrun.s64 d31, q0, #6 │ │ movs r5, r2 │ │ │ │ 000de96c > const&) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -82211,18 +82211,18 @@ │ │ ldr r0, [sp, #16] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ @ instruction: 0xf72a0015 │ │ ldr r0, [r5, #20] │ │ vcvt.u16.f16 d25, d9, #5 │ │ - vtbx.8 d27, {d27-d29}, d31 │ │ + vrecpe.f32 , │ │ sha256su0.32 q12, q9 │ │ vcvt.f16.u16 , , #5 │ │ - vshll.u32 , d17, #27 │ │ + vrsqrte.u32 d29, d29 │ │ vqshlu.s32 d31, d26, #26 │ │ movs r5, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ mov r6, r0 │ │ mov r9, r1 │ │ @@ -82702,17 +82702,17 @@ │ │ ldr r0, [sp, #68] @ 0x44 │ │ cbz r0, df042 >, cv::Range, cv::Range) const@@Base+0x3d6> │ │ str r0, [sp, #72] @ 0x48 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ bic.w r0, lr, #9764864 @ 0x950000 │ │ - ldrh r1, [r3, #42] @ 0x2a │ │ - vrshr.u64 d29, d3, #6 │ │ - vrintx.f32 , │ │ + add r7, pc, #852 @ (adr r7, df3a4 ) │ │ + @ instruction: 0xfffaed0f │ │ + vcvt.u32.f32 d28, d31, #6 │ │ vsra.u32 d31, d24, #6 │ │ movs r5, r2 │ │ │ │ 000df05c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -82797,17 +82797,17 @@ │ │ ldrb.w r0, [sp, #8] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bics.w r0, ip, #21 │ │ - ldrb r1, [r6, #27] │ │ - vsra.u32 , , #6 │ │ - sha1su1.32 , │ │ + ldr r1, [sp, #436] @ 0x1b4 │ │ + @ instruction: 0xfffaebf9 │ │ + @ instruction: 0xffface29 │ │ @ instruction: 0xfffaefbc │ │ movs r5, r2 │ │ │ │ 000df150 >, cv::Range, cv::Range) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -83079,27 +83079,27 @@ │ │ bl df32c │ │ bmi.n df39a │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (df3fc ) │ │ add r0, pc │ │ bl a91f8 │ │ - b.n df062 │ │ - vrintz.f32 d27, d0 │ │ + lsls r5, r5, #2 │ │ + vrsqrte.f32 d27, d0 │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (df40c ) │ │ add r0, pc │ │ bl a91f8 │ │ - b.n df052 >, cv::Range, cv::Range) const@@Base+0x3e6> │ │ - vrintz.f32 d27, d0 │ │ + lsls r5, r3, #2 │ │ + vrsqrte.f32 d27, d0 │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (df41c ) │ │ add r0, pc │ │ bl a91f8 │ │ - b.n df042 >, cv::Range, cv::Range) const@@Base+0x3d6> │ │ + lsls r5, r1, #2 │ │ Address 0xdf41e is out of bounds. │ │ │ │ │ │ 000df420 : │ │ push {r7, lr} │ │ mov r7, sp │ │ bl df428 │ │ @@ -83339,15 +83339,15 @@ │ │ vsli.64 , q11, #59 @ 0x3b │ │ vsli.64 d23, d4, #59 @ 0x3b │ │ vshll.u32 q11, d19, #27 │ │ vsli.64 , q2, #59 @ 0x3b │ │ vqrdmulh.s q13, , d11[0] │ │ vshll.u32 q11, d1, #27 │ │ vsli.64 d29, d18, #59 @ 0x3b │ │ - vrsra.u32 q15, , #5 │ │ + vqrdmulh.s , , d13[0] │ │ @ instruction: 0xfffa6a77 │ │ vqshlu.s32 d29, d8, #27 │ │ vtbx.8 d30, {d27-d29}, d22 │ │ movs r5, r2 │ │ │ │ 000df6c4 : │ │ bx lr │ │ @@ -84144,16 +84144,16 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ b.n df5a4 │ │ movs r5, r2 │ │ - ldr r0, [sp, #428] @ 0x1ac │ │ - @ instruction: 0xfffa8db1 │ │ + uxtb r7, r4 │ │ + vtbl.8 d26, {d10}, d29 │ │ vrintx.f32 q11, │ │ vrsra.u64 q9, , #6 │ │ vsri.64 d22, d17, #5 │ │ vsri.32 d30, d0, #6 │ │ movs r5, r2 │ │ │ │ 000dfd18 : │ │ @@ -84213,15 +84213,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ b.n e04b4 │ │ movs r5, r2 │ │ - str r7, [sp, #684] @ 0x2ac │ │ + sxth r7, r4 │ │ vcvt.f16.u16 d16, d19, #6 │ │ vrintn.f32 d22, d13 │ │ @ instruction: 0xfffae36c │ │ movs r5, r2 │ │ b.n e0458 │ │ movs r5, r2 │ │ push {r4, r5, r6, r7, lr} │ │ @@ -84346,16 +84346,16 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ b.n e0388 │ │ movs r5, r2 │ │ - str r6, [sp, #476] @ 0x1dc │ │ - vshr.u32 d29, d24, #6 │ │ + sub sp, #460 @ 0x1cc │ │ + @ instruction: 0xfffaeab4 │ │ vrshr.u64 q11, , #6 │ │ vqmovun.s64 d30, q3 │ │ movs r5, r2 │ │ b.n e0324 │ │ movs r5, r2 │ │ │ │ 000dfeec : │ │ @@ -84402,15 +84402,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ b.n e02c0 │ │ movs r5, r2 │ │ - str r5, [sp, #972] @ 0x3cc │ │ + add sp, #444 @ 0x1bc │ │ vrintn.f32 , │ │ vrshr.u32 q11, , #5 │ │ vsra.u64 d30, d8, #6 │ │ movs r5, r2 │ │ │ │ 000dff6c : │ │ push {r4, r6, r7, lr} │ │ @@ -84482,18 +84482,18 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ b.n e027c │ │ movs r5, r2 │ │ - str r5, [sp, #372] @ 0x174 │ │ + add r7, sp, #868 @ 0x364 │ │ vrshr.u32 d22, d26, #6 │ │ vsra.u64 d22, d31, #6 │ │ - vsli.32 d25, d25, #26 │ │ + @ instruction: 0xfffaafb5 │ │ vrshr.u32 d22, d6, #6 │ │ vsra.u64 d22, d11, #6 │ │ vuzp.32 d30, d2 │ │ movs r5, r2 │ │ │ │ 000e0034 : │ │ push {r4, r5, r7, lr} │ │ @@ -84620,27 +84620,27 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ b.n e0240 │ │ movs r5, r2 │ │ - ldr r0, [sp, #272] @ 0x110 │ │ + uxtb r0, r0 │ │ vmull.u , d26, d18 │ │ vshr.u64 q11, , #5 │ │ vsri.64 d20, d21, #6 │ │ vcvt.f16.u16 , q15, #5 │ │ vshr.u64 d22, d27, #5 │ │ @ instruction: 0xfffa2b18 │ │ vcvt.f16.u16 , q5, #5 │ │ vshr.u64 d22, d7, #5 │ │ vrsra.u32 d18, d6, #6 │ │ vcvt.f16.u16 d27, d2, #6 │ │ vcvta.s32.f32 q11, │ │ - @ instruction: 0xfffab34e │ │ + vqrdmulh.s q14, q13, d10[0] │ │ vcvt.f16.u16 d27, d22, #6 │ │ vshr.u32 q11, , #5 │ │ vaddl.u q15, d10, d18 │ │ movs r5, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -84770,18 +84770,18 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ udf #238 @ 0xee │ │ movs r5, r2 │ │ - str r2, [sp, #572] @ 0x23c │ │ + add r5, sp, #44 @ 0x2c │ │ vqrdmlsh.s , q5, d28[0] │ │ @ instruction: 0xfffa5ef1 │ │ - vqmovn.s64 d26, q8 │ │ + vcvt.u16.f16 d27, d12, #6 │ │ vrint?.f32 q8, q15 │ │ vqrdmlah.s , q13, d13[0] │ │ @ instruction: 0xfffa2996 │ │ vqshl.u64 d16, d22, #59 @ 0x3b │ │ vcvt.u32.f32 d21, d5, #6 │ │ vcvt.f32.u32 , q6, #6 │ │ movs r5, r2 │ │ @@ -84901,18 +84901,18 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ble.n e0350 │ │ movs r5, r2 │ │ - str r1, [sp, #364] @ 0x16c │ │ + add r3, sp, #860 @ 0x35c │ │ vqrshrun.s64 d18, , #6 │ │ @ instruction: 0xfffb5dbd │ │ - vsra.u32 d25, d23, #6 │ │ + @ instruction: 0xfffaabb3 │ │ vqshrun.s64 d18, , #6 │ │ @ instruction: 0xfffb5d99 │ │ @ instruction: 0xfffa4f8b │ │ vqshrun.s64 d18, , #5 │ │ vcvt.u16.f16 , , #5 │ │ @ instruction: 0xfffadd06 │ │ movs r5, r2 │ │ @@ -85020,18 +85020,18 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ bgt.n e05d0 │ │ movs r5, r2 │ │ - str r0, [sp, #180] @ 0xb4 │ │ + add r2, sp, #676 @ 0x2a4 │ │ vtbl.8 d16, {d26-d29}, d26 │ │ vmull.u , d27, d15 │ │ - vaddl.u , d10, d9 │ │ + vtbl.8 d26, {d26-d28}, d5 │ │ vtbl.8 d16, {d26-d29}, d6 │ │ vdup.8 , d27[5] │ │ @ instruction: 0xfffa3e98 │ │ vtbx.8 d16, {d10-d13}, d18 │ │ vdup.8 , d7[5] │ │ @ instruction: 0xfffadbd6 │ │ movs r5, r2 │ │ @@ -85163,15 +85163,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ bge.n e0610 │ │ movs r5, r2 │ │ - ldrh r5, [r0, #52] @ 0x34 │ │ + add r1, sp, #4 │ │ vsli.64 d18, d3, #58 @ 0x3a │ │ vtbx.8 d21, {d27-d29}, d23 │ │ vqrdmulh.s , q5, d12[0] │ │ vtbl.8 d29, {d11-d13}, d30 │ │ movs r5, r2 │ │ │ │ 000e06e0 : │ │ @@ -85331,15 +85331,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #12] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bls.n e0958 │ │ movs r5, r2 │ │ - ldrh r7, [r3, #38] @ 0x26 │ │ + add r7, pc, #364 @ (adr r7, e09e0 ) │ │ vsri.32 d28, d21, #6 │ │ vtbx.8 d21, {d11-d12}, d1 │ │ vtbl.8 d29, {d26}, d10 │ │ movs r5, r2 │ │ │ │ 000e0880 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -85417,15 +85417,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bhi.n e0988 │ │ movs r5, r2 │ │ - ldrh r3, [r7, #30] │ │ + add r6, pc, #476 @ (adr r6, e0b34 ) │ │ vrint?.f32 , q10 │ │ vqrshrun.s64 d21, , #5 │ │ vrintp.f32 d29, d20 │ │ movs r5, r2 │ │ │ │ 000e0964 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -85588,22 +85588,22 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ bvc.n e0b68 │ │ movs r5, r2 │ │ - ldrh r1, [r4, #20] │ │ - vsra.u32 , , #6 │ │ + add r5, pc, #116 @ (adr r5, e0b74 ) │ │ + @ instruction: 0xfffaebf5 │ │ vrint?.f32 d21, d3 │ │ - @ instruction: 0xfffa8a7d │ │ - vsra.u32 , , #6 │ │ + vsri.64 q13, , #6 │ │ + @ instruction: 0xfffaebd1 │ │ vqshlu.s64 , , #58 @ 0x3a │ │ - @ instruction: 0xfffa8a59 │ │ - vsra.u32 d29, d17, #6 │ │ + vsri.64 q13, , #6 │ │ + vtbl.8 d30, {d26-d29}, d29 │ │ vqshlu.s64 d21, d27, #58 @ 0x3a │ │ vrint?.f32 , q5 │ │ movs r5, r2 │ │ │ │ 000e0b24 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -85730,18 +85730,18 @@ │ │ itt ne │ │ ldrne r0, [sp, #12] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ bpl.n e0d60 │ │ movs r5, r2 │ │ - ldrh r1, [r2, #14] │ │ + add r4, pc, #308 @ (adr r4, e0db0 ) │ │ vqshrn.u64 d31, q8, #6 │ │ vqshlu.s32 d21, d19, #26 │ │ - vtbl.8 d24, {d10-d11}, d1 │ │ + vrsra.u32 q13, , #6 │ │ vtbx.8 d31, {d10}, d16 │ │ vrinta.f32 , │ │ vtbx.8 d31, {d10}, d16 │ │ vqshrun.s64 d31, q14, #6 │ │ vsli.32 d21, d31, #26 │ │ vrintx.f32 d29, d28 │ │ movs r5, r2 │ │ @@ -85803,15 +85803,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bcc.n e0d2c │ │ movs r5, r2 │ │ - ldrh r7, [r3, #0] │ │ + add r2, pc, #620 @ (adr r2, e0fa0 ) │ │ vqshlu.s64 q10, q13, #58 @ 0x3a │ │ vrsqrte.u32 d21, d1 │ │ sha256su0.32 , q2 │ │ movs r5, r2 │ │ │ │ 000e0d40 : │ │ push {r4, r6, r7, lr} │ │ @@ -85889,18 +85889,18 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ bcc.n e0ebc │ │ movs r5, r2 │ │ - strh r7, [r6, #58] @ 0x3a │ │ - vuzp.32 q14, q5 │ │ + add r1, pc, #972 @ (adr r1, e11d0 ) │ │ + vtbx.8 d29, {d26-d29}, d6 │ │ vrsra.u64 , , #6 │ │ - vqshl.u32 q12, , #26 │ │ + vzip.32 q13, │ │ vrint?.f32 d20, d30 │ │ vrsra.u64 d21, d21, #5 │ │ vrsra.u32 d29, d12, #6 │ │ movs r5, r2 │ │ │ │ 000e0e1c : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -85979,20 +85979,20 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ bcs.n e0ddc │ │ movs r5, r2 │ │ - strh r3, [r3, #52] @ 0x34 │ │ + add r1, pc, #92 @ (adr r1, e0f3c ) │ │ sha1su1.32 , │ │ vrshr.u64 , , #6 │ │ vqmovun.s64 d29, q2 │ │ movs r5, r2 │ │ - add r5, pc, #860 @ (adr r5, e124c ) │ │ + stmia r0!, {r0, r1, r4, r6} │ │ @ instruction: 0xfffa536b │ │ vrshr.u64 , , #6 │ │ Address 0xe0ef6 is out of bounds. │ │ │ │ │ │ 000e0ef8 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -86090,28 +86090,28 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ bne.n e0f2c │ │ movs r5, r2 │ │ - strh r7, [r0, #44] @ 0x2c │ │ + add r0, pc, #12 @ (adr r0, e1000 ) │ │ vtbl.8 d31, {d10-d12}, d19 │ │ vcle.s32 , , #0 │ │ vsra.u32 d29, d18, #6 │ │ movs r5, r2 │ │ - add r4, pc, #780 @ (adr r4, e1310 ) │ │ - vrshr.u32 , , #6 │ │ - vzip.32 , │ │ + itttt cc │ │ + vrshrcc.u32 , , #6 │ │ + vzipcc.32 , │ │ Address 0xe100a is out of bounds. │ │ │ │ │ │ 000e100c : │ │ push {r4, r5, r6, r7, lr} │ │ - add r7, sp, #12 │ │ + addcc r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #24 │ │ mov r4, r0 │ │ ldr r0, [pc, #208] @ (e10ec ) │ │ cmp r4, #0 │ │ add r0, pc │ │ ldr r0, [r0, #0] │ │ @@ -86194,20 +86194,20 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ beq.n e1008 │ │ movs r5, r2 │ │ - strh r5, [r0, #36] @ 0x24 │ │ + ldr r7, [sp, #4] │ │ vtbx.8 d18, {d26-d28}, d2 │ │ vcvta.u32.f32 , │ │ vaddl.u , d10, d30 │ │ movs r5, r2 │ │ - add r3, pc, #772 @ (adr r3, e1408 ) │ │ + bkpt 0x003d │ │ vsra.u32 , , #6 │ │ vtrn.32 , │ │ vsli.64 , q8, #58 @ 0x3a │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #28 │ │ str r1, [sp, #8] │ │ @@ -86428,24 +86428,24 @@ │ │ itt ne │ │ ldrne r0, [sp, #20] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldmia r7, {r2, r3, r7} │ │ movs r5, r2 │ │ cmn r6, r6 │ │ - vcvt.u16.f16 , q0, #6 │ │ + vrintp.f32 , q6 │ │ vcvt.f32.u32 q10, , #6 │ │ - @ instruction: 0xfffa6bbe │ │ - vqrdmlah.s , q5, d24[0] │ │ + vqshlu.s32 d24, d26, #26 │ │ + vtbx.8 d23, {d26}, d20 │ │ @ instruction: 0xfffa4f8f │ │ vuzp.32 , q4 │ │ - vcvt.u16.f16 , q10, #6 │ │ + vqshl.u64 , q8, #58 @ 0x3a │ │ @ instruction: 0xfffa4e9b │ │ - @ instruction: 0xfffac8f3 │ │ - @ instruction: 0xfffa5d2c │ │ + @ instruction: 0xfffae36f │ │ + vrintp.f32 d23, d24 │ │ vcvt.f32.u32 q10, , #6 │ │ vqrdmulh.s q14, q13, d24[0] │ │ movs r5, r2 │ │ │ │ 000e1398 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ @@ -86503,15 +86503,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldmia r5!, {r3} │ │ movs r5, r2 │ │ - strh r3, [r4, #8] │ │ + ldr r3, [sp, #636] @ 0x27c │ │ vrshr.u64 , q12, #6 │ │ @ instruction: 0xfffb4d85 │ │ vqdmulh.s q14, q13, d8[0] │ │ movs r5, r2 │ │ │ │ 000e143c : │ │ push {r4, r6, r7, lr} │ │ @@ -86581,15 +86581,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldmia r4!, {r5, r6} │ │ movs r5, r2 │ │ - strh r7, [r5, #2] │ │ + ldr r2, [sp, #940] @ 0x3ac │ │ @ instruction: 0xfffa0fb2 │ │ @ instruction: 0xfffa4cd1 │ │ @ instruction: 0xfffacf2e │ │ vcvt.f16.u16 d28, d8, #5 │ │ movs r5, r2 │ │ │ │ 000e14f4 : │ │ @@ -86678,18 +86678,18 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldmia r3!, {r1, r2, r5, r7} │ │ movs r5, r2 │ │ - ldrb r3, [r5, #30] │ │ + ldr r2, [sp, #156] @ 0x9c │ │ vsri.32 d16, d21, #6 │ │ vdup.16 d20, d13[2] │ │ - vtbl.8 d21, {d26-d28}, d0 │ │ + vsri.64 , q14, #6 │ │ vsri.32 d16, d1, #6 │ │ vtbx.8 d20, {d26-d29}, d25 │ │ @ instruction: 0xfffacb56 │ │ movs r5, r2 │ │ │ │ 000e15e8 : │ │ push {r4, r5, r7, lr} │ │ @@ -86788,18 +86788,18 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldmia r2, {r1, r2, r4, r5, r7} │ │ movs r5, r2 │ │ - ldrb r5, [r0, #27] │ │ + ldr r1, [sp, #260] @ 0x104 │ │ vcvt.f32.u32 d16, d10, #6 │ │ vtbl.8 d20, {d10-d13}, d23 │ │ - @ instruction: 0xfffa7ea1 │ │ + vqshrn.u64 d25, , #6 │ │ @ instruction: 0xfffa0df6 │ │ vtbl.8 d20, {d10-d13}, d3 │ │ vrsra.u32 d31, d19, #6 │ │ @ instruction: 0xfff90dd2 │ │ @ instruction: 0xfffa4adf │ │ vtbx.8 d28, {d10-d12}, d26 │ │ movs r5, r2 │ │ @@ -86937,21 +86937,21 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldmia r1!, {r3, r4, r7} │ │ movs r5, r2 │ │ ldrb r0, [r4, #23] │ │ - vrecpe.u32 d28, d16 │ │ + @ instruction: 0xfffbde9c │ │ vtbx.8 d20, {d10-d11}, d31 │ │ - vsri.32 d28, d8, #6 │ │ - vrsra.u64 q14, q14, #6 │ │ + @ instruction: 0xfffade94 │ │ + vcvt.f32.u32 , q12, #6 │ │ vtbx.8 d20, {d10-d11}, d11 │ │ vcvt.u32.f32 q11, q9, #6 │ │ - vrecpe.u32 q14, q2 │ │ + vqrdmlah.s , , d0[0] │ │ @ instruction: 0xfffa4993 │ │ @ instruction: 0xfffac8da │ │ movs r5, r2 │ │ │ │ 000e1894 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -87042,15 +87042,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldmia r0!, {r1, r2} │ │ movs r5, r2 │ │ - ldrb r1, [r0, #16] │ │ + str r6, [sp, #500] @ 0x1f4 │ │ vqrdmulh.s q11, q13, d23[0] │ │ vtbx.8 d20, {d11}, d19 │ │ vqshl.u32 d25, d0, #26 │ │ vqrdmulh.s q11, , d3[0] │ │ vqshrun.s64 d20, , #5 │ │ vrintp.f32 d28, d28 │ │ movs r5, r2 │ │ @@ -87148,18 +87148,18 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ stmia r7!, {r1, r3} │ │ movs r5, r2 │ │ - ldrb r1, [r7, #11] │ │ + str r5, [sp, #468] @ 0x1d4 │ │ vrsra.u32 d26, d16, #6 │ │ vqshl.u32 q10, , #27 │ │ - @ instruction: 0xfffa7ad5 │ │ + vsli.32 , , #26 │ │ vshll.i32 q13, d12, #32 │ │ vqshl.u32 d20, d23, #27 │ │ vrintm.f32 d28, d28 │ │ movs r5, r2 │ │ stmia r6!, {r1, r2, r6, r7} │ │ movs r5, r2 │ │ │ │ @@ -87435,32 +87435,32 @@ │ │ itt ne │ │ ldrne r0, [sp, #28] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ stmia r5!, {r2, r3, r4, r5, r6, r7} │ │ movs r5, r2 │ │ - ldrb r5, [r5, #0] │ │ - vrshr.u32 d27, d0, #6 │ │ + str r2, [sp, #676] @ 0x2a4 │ │ + vmull.u q14, d26, d12 │ │ vrintx.f32 d20, d15 │ │ - vtbl.8 d23, {d10}, d9 │ │ - vzip.32 , q14 │ │ + vqmovn.s64 d25, │ │ + vdup.16 q14, d24[2] │ │ vrintn.f32 q10, │ │ vsli.64 q14, q0, #58 @ 0x3a │ │ movs r5, r2 │ │ stmia r5!, {r3, r5, r7} │ │ movs r5, r2 │ │ stc2 15, cr15, [r5], {249} @ 0xf9 │ │ - cbz r0, e1dce │ │ + ldmia r4!, {r2, r6} │ │ vrintn.f32 q10, │ │ vtbx.8 d16, {d10}, d3 │ │ - vrshr.u64 d27, d28, #6 │ │ + vcvt.u16.f16 d28, d24, #6 │ │ vsli.32 d20, d27, #26 │ │ - @ instruction: 0xfffa6edd │ │ - vrsra.u32 , q3, #6 │ │ + vqrshrn.u64 d24, , #6 │ │ + @ instruction: 0xfffacdd2 │ │ vsli.64 q10, , #58 @ 0x3a │ │ vrsra.u64 q14, q4, #6 │ │ movs r5, r2 │ │ │ │ 000e1dbc : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -87675,15 +87675,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #20] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ stmia r2!, {r1, r3, r4, r6, r7} │ │ movs r5, r2 │ │ - strb r3, [r0, #22] │ │ + ldrh r7, [r7, #62] @ 0x3e │ │ vrintz.f32 d24, d1 │ │ vcvtn.u32.f32 q10, │ │ vsli.64 , , #58 @ 0x3a │ │ vsli.32 q12, , #27 │ │ vcvtn.u32.f32 q10, │ │ vqmovn.s64 d28, q12 │ │ movs r5, r2 │ │ @@ -87880,22 +87880,22 @@ │ │ itt ne │ │ ldrne r0, [sp, #12] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ stmia r0!, {r1, r3, r4, r5, r6} │ │ movs r5, r2 │ │ - add r1, pc, #16 @ (adr r1, e2218 ) │ │ - @ instruction: 0xfffa4e84 │ │ + cbnz r0, e2268 │ │ + vtbl.8 d22, {d10-d11}, d0 │ │ @ instruction: 0xfffa3fd7 │ │ vtbl.8 d31, {d10}, d7 │ │ - vqrdmlah.s q10, , d16[0] │ │ + @ instruction: 0xfff968dc │ │ @ instruction: 0xfffa3fb3 │ │ vqrdmlsh.s q12, q5, d14[0] │ │ - @ instruction: 0xfffb4f2a │ │ + vtbl.8 d22, {d27-d28}, d22 │ │ vshr.u32 q10, , #6 │ │ @ instruction: 0xfffabf84 │ │ movs r5, r2 │ │ │ │ 000e222c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -88086,15 +88086,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ bkpt 0x006a │ │ movs r5, r2 │ │ - ldr r6, [sp, #952] @ 0x3b8 │ │ + cbnz r2, e243a │ │ @ instruction: 0xfffafcd7 │ │ vqrdmulh.s , q13, d1[0] │ │ vsli.64 , , #58 @ 0x3a │ │ @ instruction: 0xfff9fcb3 │ │ @ instruction: 0xfffa3d9d │ │ @ instruction: 0xfffa3eb8 │ │ vcvt.u16.f16 d31, d15, #6 │ │ @@ -88148,15 +88148,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ pop {r4, r6} │ │ movs r5, r2 │ │ - strb r1, [r2, #2] │ │ + ldrh r5, [r1, #24] │ │ vuzp.32 d18, d5 │ │ @ instruction: 0xfffb3cf3 │ │ vdup.16 , d0[2] │ │ movs r5, r2 │ │ │ │ 000e24d0 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -88390,15 +88390,15 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ cbnz r6, e279c │ │ movs r5, r2 │ │ ldc2l 15, cr15, [r5, #996]! @ 0x3e4 │ │ subs r1, #191 @ 0xbf │ │ @ instruction: 0xfffb3ad3 │ │ - vsra.u64 , q8, #6 │ │ + vdup.16 q12, d28[2] │ │ vqrshrn.u64 d19, , #6 │ │ vtbl.8 d19, {d27-d29}, d11 │ │ @ instruction: 0xfffa39b2 │ │ @ instruction: 0xfffb399b │ │ vtbl.8 d19, {d27-d29}, d31 │ │ @ instruction: 0xfffaba7c │ │ movs r5, r2 │ │ @@ -88689,18 +88689,18 @@ │ │ itt ne │ │ ldrne r0, [sp, #48] @ 0x30 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ cbnz r2, e2a54 │ │ movs r5, r2 │ │ @ instruction: 0xfab5fff9 │ │ - strh r7, [r6, r5] │ │ + ldr r3, [r6, #92] @ 0x5c │ │ vqshl.u64 d19, d3, #58 @ 0x3a │ │ @ instruction: 0xfffa5d0e │ │ - vrsra.u32 , , #5 │ │ + vqrdmulh.s q11, , d15[0] │ │ vrint?.f32 , │ │ vqshl.u32 d27, d0, #26 │ │ movs r5, r2 │ │ @ instruction: 0xb6ec │ │ movs r5, r2 │ │ │ │ 000e2a64 : │ │ @@ -89165,18 +89165,18 @@ │ │ movs r5, r2 │ │ lsls r1, r1, #27 │ │ vqshlu.s64 , q15, #58 @ 0x3a │ │ vcvtp.u32.f32 , │ │ vtbl.8 d29, {d10-d13}, d8 │ │ vqshlu.s64 d17, d22, #57 @ 0x39 │ │ vrshr.u64 d19, d9, #5 │ │ - vshr.u32 q13, q3, #6 │ │ + @ instruction: 0xfffabad2 │ │ vqshlu.s64 , q5, #58 @ 0x3a │ │ vrshr.u64 d19, d29, #5 │ │ - vqshlu.s32 d22, d3, #26 │ │ + vtrn.32 d24, d15 │ │ vqshlu.s64 d17, d2, #58 @ 0x3a │ │ vrshr.u32 , , #5 │ │ vmovn.i64 d27, q12 │ │ movs r5, r2 │ │ │ │ 000e2f78 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -91172,47 +91172,47 @@ │ │ ldrb.w r0, [sp, #244] @ 0xf4 │ │ lsls r0, r0, #31 │ │ beq.n e43c8 │ │ ldr r0, [sp, #252] @ 0xfc │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ adds r7, #97 @ 0x61 │ │ - vcvtn.u32.f32 q11, q8 │ │ + vcvt.f16.u16 , q6, #5 │ │ @ instruction: 0xfffa1e23 │ │ vcvt.u16.f16 d17, d7, #6 │ │ - vsra.u64 d22, d30, #5 │ │ + vcvt.f16.u16 d23, d26, #5 │ │ @ instruction: 0xfffa1e01 │ │ - vrshr.u32 d21, d23, #6 │ │ + @ instruction: 0xfffa6cb3 │ │ vsra.u32 q15, q13, #6 │ │ @ instruction: 0xfff91e99 │ │ - vrshr.u32 , , #6 │ │ + @ instruction: 0xfffa6cd7 │ │ vsra.u64 d30, d14, #6 │ │ @ instruction: 0xfff91ebd │ │ - vrshr.u32 d21, d3, #6 │ │ - vtbx.8 d25, {d26}, d27 │ │ + vmull.u q11, d26, d15 │ │ + @ instruction: 0xfffab367 │ │ vcvt.f32.u32 , , #6 │ │ - vzip.32 , │ │ - vtbx.8 d25, {d26}, d7 │ │ + vdup.16 q11, d27[2] │ │ + @ instruction: 0xfffab343 │ │ vcvt.f32.u32 , , #6 │ │ - vqmovn.s64 d21, │ │ + vcvt.u16.f16 d22, d15, #6 │ │ vzip.32 q15, q11 │ │ @ instruction: 0xfff91f05 │ │ - vqmovn.u64 d21, │ │ + vqrdmulh.s q11, q5, d23[0] │ │ vmovn.i64 d30, q15 │ │ vqrdmlsh.s , , d13[0] │ │ - vrsra.u32 d21, d19, #6 │ │ + @ instruction: 0xfffa6daf │ │ vrshr.u32 q15, q11, #6 │ │ @ instruction: 0xfff91f95 │ │ - vrshr.u32 , , #6 │ │ + @ instruction: 0xfffa6cfb │ │ vzip.32 q15, q1 │ │ vqrdmlah.s , , d17[0] │ │ - vqmovn.u64 d21, │ │ + vqrdmulh.s q11, q5, d3[0] │ │ vmovn.i64 d30, q5 │ │ @ instruction: 0xfff91f29 │ │ - vshll.i32 , d15, #32 │ │ + @ instruction: 0xfffa6d8b │ │ vrshr.u32 q15, q1, #6 │ │ vcvt.u32.f32 , , #7 │ │ Address 0xe445a is out of bounds. │ │ │ │ │ │ 000e445c : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -92129,32 +92129,32 @@ │ │ ldrb.w r0, [sp, #64] @ 0x40 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #72] @ 0x48 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ - ldr r3, [pc, #100] @ (e4ddc ) │ │ + str r5, [r2, #88] @ 0x58 │ │ vqshl.u64 , q3, #58 @ 0x3a │ │ movs r5, r2 │ │ - ldr r0, [pc, #284] @ (e4e9c ) │ │ - @ instruction: 0xfffa2365 │ │ + str r3, [r0, #44] @ 0x2c │ │ + vqrdmulh.s , q13, d17[0] │ │ vrintx.f32 d17, d25 │ │ - vtbl.8 d20, {d10}, d19 │ │ - @ instruction: 0xfffa2341 │ │ + vrshr.u64 d22, d15, #6 │ │ + @ instruction: 0xfffa3dbd │ │ vrintx.f32 d17, d5 │ │ - vrintp.f32 q10, │ │ - vshll.i32 q9, d1, #32 │ │ + vrshr.u32 q11, , #6 │ │ + vcvt.u16.f16 , , #6 │ │ vrintn.f32 , │ │ sha1su1.32 , │ │ vrintn.f32 , │ │ @ instruction: 0xfffa09f4 │ │ vqshl.u32 , , #27 │ │ vshr.u64 d23, d28, #6 │ │ - vcvtm.u32.f32 d18, d9 │ │ + @ instruction: 0xfffb3e05 │ │ vrintx.f32 , │ │ vsri.32 d25, d14, #6 │ │ movs r5, r2 │ │ │ │ 000e4dc0 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ @@ -92217,18 +92217,18 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ str r2, [sp, #896] @ 0x380 │ │ movs r5, r2 │ │ - mov r9, lr │ │ + str r5, [r5, #20] │ │ vrintp.f32 d16, d19 │ │ vrsra.u32 , , #6 │ │ - vqshl.u32 d20, d27, #26 │ │ + vsra.u64 d22, d23, #6 │ │ vrintp.f32 q8, │ │ vrsra.u64 d17, d13, #6 │ │ vrshr.u64 d25, d6, #6 │ │ movs r5, r2 │ │ │ │ 000e4e7c : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -92343,15 +92343,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ str r2, [sp, #112] @ 0x70 │ │ movs r5, r2 │ │ - cmp r9, sl │ │ + str r5, [r1, #4] │ │ vsri.64 d31, d21, #6 │ │ vrshr.u32 d17, d19, #7 │ │ vsra.u32 d17, d27, #6 │ │ vsri.64 d31, d1, #5 │ │ vclt.s32 d17, d15, #0 │ │ vsra.u32 , q14, #6 │ │ movs r5, r2 │ │ @@ -92441,16 +92441,16 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ str r0, [sp, #888] @ 0x378 │ │ movs r5, r2 │ │ - ldrh r5, [r6, #28] │ │ - vrshr.u32 , q4, #6 │ │ + add r6, pc, #196 @ (adr r6, e5158 ) │ │ + @ instruction: 0xfffa8cd4 │ │ vuzp.32 d17, d17 │ │ vmla.i , q5, d20[0] │ │ movs r5, r2 │ │ │ │ 000e50a0 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -92560,16 +92560,16 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldrh r4, [r7, #58] @ 0x3a │ │ movs r5, r2 │ │ - mvns r3, r3 │ │ - vrintp.f32 d20, d27 │ │ + ldrsh r7, [r2, r1] │ │ + vmovn.i64 d22, │ │ vshr.u32 d17, d29, #6 │ │ @ instruction: 0xfffa8f2a │ │ movs r5, r2 │ │ │ │ 000e51bc : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -92639,15 +92639,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrh r6, [r3, #54] @ 0x36 │ │ movs r5, r2 │ │ - orrs r1, r0 │ │ + ldrb r5, [r7, r5] │ │ vcvt.f32.u32 d21, d31, #6 │ │ vqrdmlsh.s q8, , d19[0] │ │ vrsra.u32 , , #6 │ │ vqrdmlsh.s q8, q5, d5[0] │ │ @ instruction: 0xfffa8eaa │ │ movs r5, r2 │ │ │ │ @@ -92727,16 +92727,16 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrh r2, [r2, #48] @ 0x30 │ │ movs r5, r2 │ │ - tst r5, r0 │ │ - vcvt.u16.f16 d17, d18, #6 │ │ + ldrb r1, [r0, r2] │ │ + vrintp.f32 d19, d30 │ │ vqrdmlah.s q8, q5, d23[0] │ │ @ instruction: 0xfffa8db6 │ │ movs r5, r2 │ │ │ │ 000e535c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -92822,15 +92822,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrh r4, [r7, #40] @ 0x28 │ │ movs r5, r2 │ │ - asrs r7, r7 │ │ + ldrh r3, [r7, r6] │ │ vzip.32 d30, d17 │ │ @ instruction: 0xfff90da1 │ │ vshr.u64 d29, d23, #6 │ │ vsra.u32 q15, , #7 │ │ vcvt.u16.f16 q8, , #7 │ │ vqdmulh.s q12, q13, d26[0] │ │ movs r5, r2 │ │ @@ -93010,15 +93010,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldrh r6, [r0, #34] @ 0x22 │ │ movs r5, r2 │ │ - lsls r5, r4 │ │ + ldrh r1, [r4, r4] │ │ vuzp.32 q8, │ │ @ instruction: 0xfffa0d07 │ │ vrintm.f32 , q8 │ │ vshr.u32 d16, d11, #5 │ │ @ instruction: 0xfffa0bbf │ │ vtbx.8 d16, {d26-d28}, d23 │ │ @ instruction: 0xfffbfff7 │ │ @@ -93149,15 +93149,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrh r0, [r1, #18] │ │ movs r5, r2 │ │ - subs r5, #219 @ 0xdb │ │ + ldr r7, [r2, r1] │ │ vrinta.f32 , │ │ vshll.u32 q8, d29, #27 │ │ @ instruction: 0xfffa3ea5 │ │ vrecpe.f32 , │ │ vtbx.8 d16, {d11-d13}, d17 │ │ vtbl.8 d24, {d26-d27}, d26 │ │ movs r5, r2 │ │ @@ -93257,15 +93257,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrh r2, [r1, #8] │ │ movs r5, r2 │ │ - subs r5, #105 @ 0x69 │ │ + ldrsb r5, [r4, r7] │ │ vcvt.f32.u32 d19, d11, #6 │ │ vtbx.8 d16, {d27-d28}, d11 │ │ vsri.32 , q7, #6 │ │ @ instruction: 0xfffb3d8d │ │ vqshrn.u64 d16, , #5 │ │ vtbl.8 d24, {d26}, d0 │ │ movs r5, r2 │ │ @@ -93566,15 +93566,15 @@ │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strh r4, [r6, #52] @ 0x34 │ │ movs r5, r2 │ │ asrs r3, r1, #14 │ │ vtbl.8 d29, {d27-d29}, d13 │ │ vclt.f32 q8, , #0 │ │ - vqshl.u64 d22, d2, #58 @ 0x3a │ │ + vmovn.i64 d24, q7 │ │ vtbx.8 d29, {d10-d12}, d25 │ │ vclt.f32 q8, , #0 │ │ vrintp.f32 d16, d4 │ │ @ instruction: 0xfffadaf1 │ │ vmlsl.u q8, d25, d11[0] │ │ vsli.64 d24, d18, #58 @ 0x3a │ │ movs r5, r2 │ │ @@ -93711,16 +93711,16 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strh r2, [r6, #38] @ 0x26 │ │ movs r5, r2 │ │ - subs r0, #101 @ 0x65 │ │ - @ instruction: 0xfffa2dd7 │ │ + strh r1, [r4, r3] │ │ + vqrshrun.s64 d20, , #6 │ │ vrintx.f32 q8, │ │ vsri.32 d24, d4, #6 │ │ movs r5, r2 │ │ │ │ 000e5cfc : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -93849,15 +93849,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strh r2, [r4, #28] │ │ movs r5, r2 │ │ - adds r7, #25 │ │ + str r5, [r2, r6] │ │ vrint?.f32 d20, d19 │ │ vrsra.u32 q8, , #5 │ │ vqmovn.u64 d24, q2 │ │ movs r5, r2 │ │ │ │ 000e5e48 : │ │ push {r4, r6, r7, lr} │ │ @@ -93912,15 +93912,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strh r6, [r2, #18] │ │ movs r5, r2 │ │ - adds r6, #131 @ 0x83 │ │ + str r7, [r7, r3] │ │ vqshlu.s64 d20, d15, #58 @ 0x3a │ │ vcvtp.u32.f32 q8, │ │ vmovn.i64 d24, q12 │ │ movs r5, r2 │ │ │ │ 000e5edc : │ │ push {r4, r6, r7, lr} │ │ @@ -94029,18 +94029,18 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strh r2, [r0, #14] │ │ movs r5, r2 │ │ - adds r5, #119 @ 0x77 │ │ + ldr r7, [pc, #972] @ (e63ac ) │ │ vtbx.8 d27, {d10-d12}, d8 │ │ vsra.u64 q8, , #7 │ │ - vsli.64 d19, d11, #58 @ 0x3a │ │ + vshr.u32 d21, d7, #6 │ │ vtbx.8 d27, {d10-d12}, d28 │ │ vsra.u64 q8, , #7 │ │ vuzp.32 q12, q0 │ │ movs r5, r2 │ │ │ │ 000e5ff8 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -94200,21 +94200,21 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strh r0, [r4, #4] │ │ movs r5, r2 │ │ add r7, r9 │ │ - @ instruction: 0xfffb2992 │ │ + vrecpe.u32 d20, d14 │ │ vshr.u32 q8, , #6 │ │ vsri.32 d20, d30, #6 │ │ - vtbx.8 d18, {d11-d12}, d30 │ │ + vcvtm.u32.f32 q10, q13 │ │ vmla.i q8, q5, d15[0] │ │ - sha256su0.32 , │ │ - vdup.16 , d27[2] │ │ + vqrdmlah.s q10, q5, d5[0] │ │ + vrintm.f32 , │ │ vaddl.u q8, d10, d27 │ │ @ instruction: 0xfffa7fdc │ │ movs r5, r2 │ │ │ │ 000e61b4 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -94272,15 +94272,15 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrb r2, [r5, #27] │ │ movs r5, r2 │ │ add r2, pc, #1020 @ (adr r2, e6640 ) │ │ - vrshr.u32 , q15, #6 │ │ + @ instruction: 0xfffa6cfa │ │ vcvt.u32.f32 , , #6 │ │ @ instruction: 0xfff97eb6 │ │ movs r5, r2 │ │ │ │ 000e6250 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -94546,18 +94546,18 @@ │ │ lsls r0, r0, #31 │ │ beq.n e6508 │ │ ldr r0, [sp, #32] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldrb r2, [r0, #25] │ │ movs r5, r2 │ │ - ldr r7, [r4, #40] @ 0x28 │ │ + strh r3, [r4, #40] @ 0x28 │ │ vrinta.f32 q13, q9 │ │ @ instruction: 0xfff9fcd1 │ │ - vcgt.s32 , , #0 │ │ + vtbx.8 d20, {d25-d27}, d7 │ │ vrinta.f32 q13, q8 │ │ vmull.u , d25, d29 │ │ vcvt.f16.u16 , q1, #7 │ │ movs r5, r2 │ │ │ │ 000e652c : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -94813,18 +94813,18 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrb r2, [r5, #13] │ │ movs r5, r2 │ │ bgt.n e6760 │ │ @ instruction: 0xfff9f993 │ │ vtbl.8 d31, {d10-d12}, d31 │ │ - vceq.i32 , q6, #0 │ │ + vtbx.8 d20, {d25-d28}, d8 │ │ vtbx.8 d31, {d10-d11}, d11 │ │ vtbx.8 d31, {d26-d27}, d23 │ │ - @ instruction: 0xfff92da9 │ │ + vtbl.8 d20, {d9}, d21 │ │ vqshrn.u64 d27, q1, #6 │ │ vtbl.8 d31, {d10-d12}, d11 │ │ vqrshrn.u64 d23, q12, #7 │ │ movs r5, r2 │ │ │ │ 000e67f8 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -94904,15 +94904,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldrb r2, [r4, #2] │ │ movs r5, r2 │ │ - adds r0, #94 @ 0x5e │ │ + ldr r2, [pc, #872] @ (e6c24 ) │ │ @ instruction: 0xfffa3cf0 │ │ @ instruction: 0xfffbf8f9 │ │ vtbx.8 d23, {d9}, d2 │ │ movs r5, r2 │ │ │ │ 000e68c8 : │ │ push {r4, r6, r7, lr} │ │ @@ -94975,19 +94975,19 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strb r6, [r2, #31] │ │ movs r5, r2 │ │ - cmp r4, #17 │ │ - vsri.32 , , #6 │ │ + mov sp, r1 │ │ + @ instruction: 0xfffa2efb │ │ vqrshrun.s64 d31, , #6 │ │ - vtbx.8 d18, {d25-d28}, d29 │ │ - vsri.32 , , #6 │ │ + vclt.f32 q10, , #0 │ │ + @ instruction: 0xfffa2ed7 │ │ vtbx.8 d31, {d10}, d15 │ │ vqshl.u64 d23, d22, #57 @ 0x39 │ │ movs r5, r2 │ │ │ │ 000e6980 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ @@ -95135,15 +95135,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strb r6, [r4, #25] │ │ movs r5, r2 │ │ - cmp r2, #151 @ 0x97 │ │ + cmp r3, r2 │ │ vtbl.8 d30, {d26-d27}, d5 │ │ vqshlu.s64 , , #58 @ 0x3a │ │ vtbl.8 d30, {d25-d26}, d2 │ │ vtbx.8 d30, {d10-d11}, d17 │ │ vqshlu.s64 , , #58 @ 0x3a │ │ vqshlu.s32 d23, d28, #25 │ │ movs r5, r2 │ │ @@ -95237,23 +95237,23 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strb r4, [r4, #22] │ │ movs r5, r2 │ │ - cmp r1, #197 @ 0xc5 │ │ + add r1, r8 │ │ vsli.32 q13, q2, #26 │ │ vrint?.f32 d31, d23 │ │ vceq.i32 q11, q5, #0 │ │ vsli.32 d26, d16, #27 │ │ vrint?.f32 d31, d3 │ │ vceq.f32 , q13, #0 │ │ movs r5, r2 │ │ - asrs r0, r4, #7 │ │ + cmp r4, #92 @ 0x5c │ │ vrinta.f32 d26, d12 │ │ vsli.64 , , #58 @ 0x3a │ │ Address 0xe6bfe is out of bounds. │ │ │ │ │ │ 000e6c00 : │ │ push {r4, r6, r7, lr} │ │ @@ -95324,15 +95324,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strb r6, [r3, #18] │ │ movs r5, r2 │ │ - cmp r0, #167 @ 0xa7 │ │ + orrs r3, r4 │ │ vtbx.8 d17, {d26-d28}, d13 │ │ vrecpe.f32 d31, d9 │ │ vcgt.f32 , q6, #0 │ │ movs r5, r2 │ │ │ │ 000e6cb8 : │ │ b.w 2301a4 <__emutls_get_address@@Base+0x331c> │ │ @@ -95536,15 +95536,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strb r0, [r0, #10] │ │ movs r5, r2 │ │ ldr r2, [r2, #64] @ 0x40 │ │ - vtbx.8 d18, {d27-d29}, d1 │ │ + vsli.32 d20, d29, #27 │ │ @ instruction: 0xfffacd2f │ │ Address 0xe6e9a is out of bounds. │ │ │ │ │ │ 000e6e9c : │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -95842,15 +95842,15 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldr r4, [r0, #120] @ 0x78 │ │ movs r5, r2 │ │ ldr r6, [r2, #16] │ │ - @ instruction: 0xfffb0c9f │ │ + vqshl.u32 d18, d11, #27 │ │ vshll.u32 q14, d19, #26 │ │ Address 0xe719a is out of bounds. │ │ │ │ │ │ 000e719c : │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -95893,16 +95893,16 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldr r4, [r0, #112] @ 0x70 │ │ movs r5, r2 │ │ ldr r6, [r2, #8] │ │ - @ instruction: 0xfffbfead │ │ - @ instruction: 0xfff9c9b3 │ │ + vtbl.8 d17, {d11-d12}, d25 │ │ + @ instruction: 0xfffac9b3 │ │ Address 0xe721a is out of bounds. │ │ │ │ │ │ 000e721c : │ │ push {r7, lr} │ │ mov r7, sp │ │ sub sp, #24 │ │ @@ -96435,16 +96435,16 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldr r0, [r4, #24] │ │ movs r5, r2 │ │ - str r2, [r2, #80] @ 0x50 │ │ - vtbx.8 d19, {d26-d29}, d21 │ │ + ldrb r6, [r1, #30] │ │ + vrint?.f32 , │ │ vqshl.u32 , , #26 │ │ vqrshrn.u64 d22, q8, #6 │ │ movs r5, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ sub sp, #216 @ 0xd8 │ │ @@ -96942,21 +96942,21 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r0, sp, #256 @ 0x100 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ str r6, [r6, #96] @ 0x60 │ │ movs r5, r2 │ │ b.n e7678 const&, cv::_InputArray const&, cv::TermCriteria)@@Base+0x2dc> │ │ - vrintm.f32 q10, q2 │ │ + vuzp.32 q11, q0 │ │ vqmovn.s64 d31, │ │ vtbx.8 d16, {d10-d13}, d7 │ │ - vcvt.f32.u32 d20, d4 │ │ + vcvtn.s32.f32 d22, d0 │ │ vqmovun.s64 d31, │ │ @ instruction: 0xfffac995 │ │ - vrintm.f32 d20, d20 │ │ + vuzp.32 d22, d16 │ │ vqmovun.s64 d31, │ │ vsri.64 d22, d14, #6 │ │ movs r5, r2 │ │ bmi.n e7ca0 const&, cv::_InputArray const&, cv::TermCriteria)@@Base+0x904> │ │ bmi.n e7ca2 const&, cv::_InputArray const&, cv::TermCriteria)@@Base+0x906> │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -97530,16 +97530,16 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ str r6, [r2, #56] @ 0x38 │ │ movs r5, r2 │ │ strb r0, [r0, r3] │ │ vsra.u64 , , #5 │ │ vcvt.f16.u16 d30, d19, #6 │ │ - vsra.u64 , q8, #6 │ │ - vqmovn.s64 d18, q9 │ │ + vdup.16 q10, d28[2] │ │ + vcvt.u16.f16 d19, d14, #6 │ │ vtbx.8 d30, {d26-d29}, d31 │ │ vcvt.f32.u32 , q12, #6 │ │ movs r5, r2 │ │ strb r6, [r3, r2] │ │ vsra.u64 , , #5 │ │ vcvt.f16.u16 d30, d1, #6 │ │ @ instruction: 0xfffa5b10 │ │ @@ -98929,19 +98929,19 @@ │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ b.n e96b0 │ │ movs r4, r2 │ │ str r2, [r6, r1] │ │ movs r5, r2 │ │ - lsls r0, r7, #28 │ │ - sha1su1.32 , │ │ + movs r1, #180 @ 0xb4 │ │ + @ instruction: 0xfffa2e0b │ │ vqrdmulh.s , q5, d5[0] │ │ - vuzp.32 , │ │ - vrsra.u64 d17, d17, #6 │ │ + vtbx.8 d20, {d26-d29}, d7 │ │ + @ instruction: 0xfffa2e2d │ │ vqrdmulh.s , q5, d23[0] │ │ @ instruction: 0xfffa4f02 │ │ movs r5, r2 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ ldr r5, [r0, #4] │ │ mov r4, r0 │ │ @@ -101449,16 +101449,16 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #272 @ 0x110 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #96 @ 0x60 │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ - ldmdb ip, {r0, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc} │ │ - ldmia r2, {r2, r6, r7} │ │ + lsls r0, r3, #14 │ │ + vtbx.8 d28, {d26-d28}, d4 │ │ @ instruction: 0xfffabf29 │ │ vtrn.32 , q2 │ │ movs r5, r2 │ │ │ │ 000eb074 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -101711,16 +101711,16 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ stmia r0!, {r1, r2, r3, r4, r5, r6, r7} │ │ movs r4, r2 │ │ cmp r7, #2 │ │ movs r5, r2 │ │ str r7, [r0, #116] @ 0x74 │ │ - vqshlu.s64 d30, d9, #57 @ 0x39 │ │ - vdup.8 , d21[4] │ │ + vsra.u32 d16, d5, #7 │ │ + vdup.16 , d21[2] │ │ @ instruction: 0xfffa2e00 │ │ movs r5, r2 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ ldr r5, [r0, #4] │ │ mov r4, r0 │ │ cbz r5, eb360 │ │ @@ -102068,15 +102068,15 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ b.n eb6ae │ │ add r0, sp, #172 @ 0xac │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ cmp r2, #248 @ 0xf8 │ │ movs r5, r2 │ │ - lsrs r3, r2, #19 │ │ + movs r7, #79 @ 0x4f │ │ vcvt.u32.f32 d30, d27, #6 │ │ @ instruction: 0xfffab8b9 │ │ @ instruction: 0xfffa2a54 │ │ movs r5, r2 │ │ │ │ 000eb6cc : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -102168,15 +102168,15 @@ │ │ add r0, sp, #100 @ 0x64 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ cmp r1, #198 @ 0xc6 │ │ movs r5, r2 │ │ str r2, [r7, #72] @ 0x48 │ │ - @ instruction: 0xfffa0bf4 │ │ + vqshlu.s32 q9, q8, #26 │ │ vqshl.u64 d27, d19, #58 @ 0x3a │ │ vtbx.8 d18, {d10-d11}, d14 │ │ movs r5, r2 │ │ │ │ 000eb7cc : │ │ movw r1, #38303 @ 0x959f │ │ movt r1, #32436 @ 0x7eb4 │ │ @@ -102813,21 +102813,21 @@ │ │ itt ne │ │ ldrne r0, [sp, #76] @ 0x4c │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ movs r7, #222 @ 0xde │ │ movs r5, r2 │ │ add r3, pc, #756 @ (adr r3, ec1e4 ) │ │ - vcvt.u32.f32 , , #7 │ │ + @ instruction: 0xfff9d9d5 │ │ vshr.u64 d27, d3, #7 │ │ vshll.i32 q10, d13, #32 │ │ vcvtp.u32.f32 d20, d19 │ │ vrshr.u32 d20, d0, #5 │ │ - vcvtn.u32.f32 , │ │ - vcvt.u32.f32 d27, d23, #7 │ │ + vdup.8 q14, d11[5] │ │ + @ instruction: 0xfff9d9b3 │ │ vshr.u32 , , #7 │ │ vrshr.u32 d18, d16, #6 │ │ movs r5, r2 │ │ b.w ebf2c │ │ b.w ed190 │ │ b.w ed4b8 │ │ b.w ed8dc │ │ @@ -103862,15 +103862,15 @@ │ │ vcge.f32 q13, , #0 │ │ @ instruction: 0xfffadb11 │ │ vtbx.8 d23, {d10-d11}, d25 │ │ vsri.32 d26, d27, #7 │ │ vqshlu.s64 d25, d7, #58 @ 0x3a │ │ @ instruction: 0xfffa79d5 │ │ vcge.f32 d26, d23, #0 │ │ - @ instruction: 0xfffacea3 │ │ + vqshrn.u64 d30, , #6 │ │ vtbl.8 d23, {d25-d26}, d13 │ │ vsri.32 q13, , #7 │ │ vrintm.f32 , q8 │ │ movs r5, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -105912,15 +105912,15 @@ │ │ vtbl.8 d24, {d25-d28}, d23 │ │ vzip.32 q14, │ │ vaddl.u q11, d10, d17 │ │ @ instruction: 0xfff98af3 │ │ vqrdmulh.s , q5, d15[0] │ │ vtrn.32 d22, d13 │ │ @ instruction: 0xfff98b5f │ │ - vsli.32 , , #26 │ │ + @ instruction: 0xfffacfd7 │ │ vcgt.s32 q11, , #0 │ │ @ instruction: 0xfff98b17 │ │ @ instruction: 0xfffafd94 │ │ movs r4, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -109321,15 +109321,15 @@ │ │ ldrh r3, [r3, #26] │ │ vsri.32 q11, , #6 │ │ vqrdmlsh.s q8, q5, d4[0] │ │ vtbx.8 d24, {d9-d12}, d12 │ │ vsri.32 d22, d23, #6 │ │ vqshlu.s32 d31, d6, #26 │ │ vqrshrun.s64 d31, q5, #6 │ │ - vsli.32 q11, , #26 │ │ + vqrdmlsh.s , q13, d31[0] │ │ vtbl.8 d24, {d9-d12}, d26 │ │ vsri.32 d22, d5, #6 │ │ vsli.64 d27, d16, #58 @ 0x3a │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ ldr.w r0, [r0, #1256] @ 0x4e8 │ │ add.w r5, r4, #1264 @ 0x4f0 │ │ @@ -110406,16 +110406,16 @@ │ │ bl a8d68 │ │ nop │ │ ldmia r4!, {r1, r3, r6} │ │ movs r4, r2 │ │ ldmia r2!, {r3, r4} │ │ movs r4, r2 │ │ str r7, [r2, #64] @ 0x40 │ │ - @ instruction: 0xfffa59d9 │ │ - vqrdmulh.s , , d20[0] │ │ + vsri.32 , , #6 │ │ + vtbx.8 d27, {d9}, d16 │ │ Address 0xf1776 is out of bounds. │ │ │ │ │ │ 000f1778 , std::__ndk1::allocator > const&, std::__ndk1::basic_string, std::__ndk1::allocator > const&, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > >&, bool, bool)@@Base>: │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ @@ -110823,15 +110823,15 @@ │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrh r0, [r4, r2] │ │ movs r4, r2 │ │ stmia r7!, {r1, r2, r6} │ │ movs r4, r2 │ │ - ldr r1, [r3, #116] @ 0x74 │ │ + ldrh r5, [r2, #14] │ │ vcle.f32 , q0, #0 │ │ vqshl.u64 d20, d24, #58 @ 0x3a │ │ vtbx.8 d21, {d9-d11}, d26 │ │ movs r4, r2 │ │ ldrh r6, [r4, r0] │ │ movs r4, r2 │ │ cmp r1, #131 @ 0x83 │ │ @@ -112406,18 +112406,18 @@ │ │ vtbl.8 d17, {d26-d28}, d24 │ │ vtbl.8 d17, {d26}, d27 │ │ vsli.64 d30, d27, #57 @ 0x39 │ │ @ instruction: 0xfff91af6 │ │ @ instruction: 0xfffa18f9 │ │ vmlsl.u , d25, d28[0] │ │ movs r4, r2 │ │ - cbz r3, f2d9e │ │ - vshll.u32 , d31, #25 │ │ + ldmia r4, {r0, r1, r2, r4} │ │ + vsri.64 d25, d27, #7 │ │ vtbl.8 d17, {d9-d10}, d17 │ │ - vsri.32 q13, q5, #7 │ │ + @ instruction: 0xfff9bed6 │ │ vtbx.8 d17, {d9-d12}, d6 │ │ vtbx.8 d17, {d10-d11}, d9 │ │ vcle.f32 d27, d0, #0 │ │ mov r7, sp │ │ blx 231000 <__emutls_get_address@@Base+0x4178> │ │ ldmia.w sp!, {r7, lr} │ │ b.w 2300a8 <__emutls_get_address@@Base+0x3220> │ │ @@ -112713,15 +112713,15 @@ │ │ mov.w r1, #1000 @ 0x3e8 │ │ add r0, pc │ │ blx 2319f0 <__emutls_get_address@@Base+0x4b68> │ │ ldr r1, [pc, #8] @ (f30c0 ) │ │ add r1, pc │ │ str r0, [r1, #0] │ │ pop {r7, pc} │ │ - ands r2, r0 │ │ + ldrh r6, [r7, r1] │ │ vtbl.8 d29, {d9-d12}, d10 │ │ movs r4, r2 │ │ │ │ 000f30c4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -114799,15 +114799,15 @@ │ │ adds r1, #42 @ 0x2a │ │ movs r4, r2 │ │ ldr r4, [sp, #480] @ 0x1e0 │ │ movs r4, r2 │ │ bcc.n f47fa │ │ vcvt.u16.f16 q8, q2, #8 │ │ vqrdmulh.s , q13, d16[0] │ │ - vqrdmlah.s , q4, d15[0] │ │ + vtbx.8 d23, {d24}, d11 │ │ vcvt.u16.f16 d16, d18, #7 │ │ @ instruction: 0xfffafdbe │ │ vtbl.8 d25, {d24-d25}, d28 │ │ movs r4, r2 │ │ │ │ 000f47d8 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -115658,15 +115658,15 @@ │ │ movs r4, r2 │ │ ldr r1, [r4, #76] @ 0x4c │ │ vqshlu.s32 d20, d30, #26 │ │ vsri.32 d31, d26, #6 │ │ vrshr.u32 d17, d21, #8 │ │ vqshlu.s32 d20, d12, #25 │ │ vsri.32 d31, d8, #6 │ │ - vshr.u32 q9, , #8 │ │ + vtbx.8 d19, {d24-d26}, d15 │ │ vsli.64 q10, q13, #57 @ 0x39 │ │ vrsra.u64 , q11, #6 │ │ vtbl.8 d29, {d8-d11}, d25 │ │ vsli.64 q10, q4, #57 @ 0x39 │ │ vrsra.u64 , q2, #6 │ │ vrev64.32 d25, d8 │ │ movs r4, r2 │ │ @@ -116066,24 +116066,24 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ sub.w r0, r7, #88 @ 0x58 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldrh r6, [r2, #46] @ 0x2e │ │ movs r4, r2 │ │ bhi.n f578a │ │ - vshll.u32 q9, d17, #25 │ │ + vcge.f32 d20, d29, #0 │ │ vcge.s32 , q11, #0 │ │ vrshr.u32 d31, d1, #8 │ │ - @ instruction: 0xfff929f7 │ │ + vsri.32 q10, , #7 │ │ vcge.s32 d31, d28, #0 │ │ - vqrdmulh.s q11, q12, d27[0] │ │ - vtbl.8 d18, {d25}, d3 │ │ + vtbx.8 d24, {d8}, d23 │ │ + vrshr.u64 q10, , #7 │ │ vcvt.u32.f32 d30, d24, #7 │ │ - @ instruction: 0xfff83f2f │ │ - vtbx.8 d18, {d9}, d17 │ │ + vtbl.8 d21, {d24-d25}, d27 │ │ + vrshr.u64 q10, , #7 │ │ vcvt.u32.f32 d30, d6, #7 │ │ @ instruction: 0xfff88afa │ │ movs r4, r2 │ │ │ │ 000f56c0 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -117478,28 +117478,28 @@ │ │ b.n f66d4 │ │ add r0, sp, #136 @ 0x88 │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strh r2, [r3, #52] @ 0x34 │ │ movs r4, r2 │ │ lsls r7, r1 │ │ - @ instruction: 0xfffa0bf4 │ │ + vqshlu.s32 q9, q8, #26 │ │ vcvt.u32.f32 , q9, #7 │ │ vqrdmlsh.s q8, q12, d20[0] │ │ movs r4, r2 │ │ - adds r3, r4, r0 │ │ - vtbl.8 d16, {d25-d28}, d22 │ │ + adds r2, #159 @ 0x9f │ │ + vclt.f32 d18, d18, #0 │ │ @ instruction: 0xfff9df24 │ │ @ instruction: 0xfff8fd26 │ │ - vtbl.8 d16, {d24-d27}, d4 │ │ + vpadal.s32 d18, d0 │ │ @ instruction: 0xfff9df02 │ │ @ instruction: 0xfff87b36 │ │ movs r4, r2 │ │ - ldrb r6, [r7, r6] │ │ - vtbx.8 d16, {d25-d28}, d8 │ │ + ldrb r2, [r7, #0] │ │ + vclt.f32 q9, q2, #0 │ │ vqrdmlsh.s , , d6[0] │ │ vsli.64 , q8, #56 @ 0x38 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8-d10} │ │ sub sp, #64 @ 0x40 │ │ @@ -119031,16 +119031,16 @@ │ │ add r0, sp, #44 @ 0x2c │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #100 @ 0x64 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r4, [r6, #36] @ 0x24 │ │ movs r4, r2 │ │ - movs r3, #127 @ 0x7f │ │ - vrsra.u64 d18, d28, #7 │ │ + subs r5, #251 @ 0xfb │ │ + vcvt.f32.u32 d19, d24, #7 │ │ @ instruction: 0xfff9ce90 │ │ vtbx.8 d22, {d24-d25}, d0 │ │ movs r4, r2 │ │ │ │ 000f773c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -119163,16 +119163,16 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #172 @ 0xac │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldr r4, [r2, #20] │ │ movs r4, r2 │ │ - ldrsb r7, [r1, r7] │ │ - vcvt.f32.u32 d18, d10, #7 │ │ + strb r3, [r1, #9] │ │ + @ instruction: 0xfff94896 │ │ vcvt.u16.f16 q14, q5, #7 │ │ vqrshrun.s64 d22, q11, #8 │ │ movs r4, r2 │ │ │ │ 000f788c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -119895,28 +119895,28 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #464 @ 0x1d0 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ str r2, [r3, #80] @ 0x50 │ │ movs r4, r2 │ │ @ instruction: 0xb755 │ │ - vpaddl.u32 , q15 │ │ - vqshlu.s32 d28, d4, #24 │ │ + vqrdmulh.s q8, q4, d26[0] │ │ + vqshlu.s32 d28, d4, #25 │ │ @ instruction: 0xfff83eba │ │ - vqmovn.u64 d31, q6 │ │ - vsli.64 q14, q9, #56 @ 0x38 │ │ + vqrdmulh.s q8, q5, d8[0] │ │ + vsli.64 q14, q9, #57 @ 0x39 │ │ vqshl.u64 d28, d26, #56 @ 0x38 │ │ - vsubl.u , d25, d26 │ │ - vsli.64 q14, q0, #56 @ 0x38 │ │ + @ instruction: 0xfff90d26 │ │ + vsli.64 q14, q0, #57 @ 0x39 │ │ vrev16.32 q13, │ │ - vsubl.u , d25, d8 │ │ - vabal.u q14, d24, d30 │ │ + @ instruction: 0xfff90d04 │ │ + vcle.f32 d28, d30, #0 │ │ vpaddl.s32 q15, q6 │ │ - vclt.s32 , q11, #0 │ │ - vabal.u q14, d24, d12 │ │ + vqdmulh.s q8, , d18[0] │ │ + vcle.f32 d28, d12, #0 │ │ vsra.u64 q11, q3, #8 │ │ movs r4, r2 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ adds r0, #112 @ 0x70 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ @@ -120127,16 +120127,16 @@ │ │ add r0, sp, #408 @ 0x198 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ str r0, [r4, #0] │ │ movs r4, r2 │ │ stc 15, cr15, [r3, #996]! @ 0x3e4 │ │ - @ instruction: 0xefcafff8 │ │ - stmia r2!, {r1, r3, r5, r6, r7} │ │ + lsrs r6, r0, #9 │ │ + sha1h.32 q14, q13 │ │ @ instruction: 0xfff85eaa │ │ movs r4, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #60 @ 0x3c │ │ mov fp, r0 │ │ @@ -121520,19 +121520,19 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #360 @ 0x168 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ str r2, [r5, r2] │ │ movs r4, r2 │ │ stmia r4!, {r2, r3, r4, r5} │ │ - @ instruction: 0xfff83db2 │ │ - vabs.s32 d18, d20 │ │ + vtbl.8 d21, {d8}, d30 │ │ + @ instruction: 0xfff93da0 │ │ vqrshrun.s64 d23, q14, #7 │ │ - @ instruction: 0xfff83d88 │ │ - vrshr.u64 q9, q13, #7 │ │ + vtbl.8 d21, {d8}, d4 │ │ + vcvt.u16.f16 , q11, #7 │ │ @ instruction: 0xfff94ed6 │ │ movs r4, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ mov r5, r0 │ │ mov r0, r1 │ │ @@ -121805,19 +121805,19 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #360 @ 0x168 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r5, [pc, #664] @ (f983c ) │ │ movs r4, r2 │ │ stmia r1!, {r2, r3, r5} │ │ - vsli.64 , , #56 @ 0x38 │ │ - vshr.u32 d18, d6, #8 │ │ + vrev64.32 , │ │ + @ instruction: 0xfff93a92 │ │ vceq.f32 q12, , #0 │ │ - @ instruction: 0xfff8f5c7 │ │ - vqrdmlsh.s , q12, d26[0] │ │ + vrev64.32 , │ │ + vtbx.8 d19, {d9-d11}, d22 │ │ vtbx.8 d20, {d25-d28}, d6 │ │ movs r4, r2 │ │ │ │ 000f95c0 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -122328,30 +122328,30 @@ │ │ add r0, sp, #72 @ 0x48 │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r2, [pc, #824] @ (f9e70 ) │ │ movs r4, r2 │ │ ldr r4, [sp, #552] @ 0x228 │ │ @ instruction: 0xfff89d21 │ │ - @ instruction: 0xfff81b76 │ │ + vsli.64 , q9, #56 @ 0x38 │ │ vneg.s32 q9, │ │ @ instruction: 0xfffa9cff │ │ - @ instruction: 0xfff81b54 │ │ + vsli.64 , q0, #56 @ 0x38 │ │ vsra.u64 q15, q5, #7 │ │ @ instruction: 0xfff99cdd │ │ - @ instruction: 0xfff81b32 │ │ + vabal.u , d24, d30 │ │ @ instruction: 0xfff98afe │ │ vmull.u , d24, d31 │ │ - vtbl.8 d17, {d8-d11}, d4 │ │ - vshr.u64 , , #7 │ │ - vmull.u , d24, d13 │ │ - vtbx.8 d17, {d24-d26}, d18 │ │ + vabal.u , d24, d0 │ │ + @ instruction: 0xfff90b5b │ │ + vmull.u , d25, d13 │ │ + vsli.32 , q7, #24 │ │ vceq.i32 , q9, #0 │ │ vqrdmulh.s , q4, d7[0] │ │ - @ instruction: 0xfff81b9c │ │ + vqshlu.s32 d19, d8, #24 │ │ vabs.f32 q10, q3 │ │ movs r4, r2 │ │ bmi.n f9b30 │ │ bmi.n f9b32 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -123291,25 +123291,25 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #64 @ 0x40 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ subs r6, #126 @ 0x7e │ │ movs r4, r2 │ │ - subs r0, #48 @ 0x30 │ │ + strh r4, [r5, r2] │ │ vshr.u32 d24, d24, #7 │ │ - vrev64.32 d17, d24 │ │ + vtbl.8 d18, {d24-d26}, d20 │ │ vtbx.8 d17, {d9-d10}, d29 │ │ vtrn.32 d24, d6 │ │ - vshr.u32 , q11, #8 │ │ + @ instruction: 0xfff82af2 │ │ vcvt.f16.u16 d19, d26, #7 │ │ movs r4, r2 │ │ add r1, pc, #752 @ (adr r1, fa898 ) │ │ - vtbx.8 d19, {d8}, d0 │ │ - vcgt.s32 , q6, #0 │ │ + vrshr.u64 d21, d28, #8 │ │ + vtbx.8 d18, {d25-d27}, d8 │ │ Address 0xfa5ae is out of bounds. │ │ │ │ │ │ 000fa5b0 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ @@ -123392,15 +123392,15 @@ │ │ add r0, sp, #24 │ │ blx 2306f0 <__emutls_get_address@@Base+0x3868> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ subs r2, #214 @ 0xd6 │ │ movs r4, r2 │ │ asrs r3, r5, #30 │ │ vshr.u32 d27, d27, #6 │ │ - vqrdmlah.s q8, q12, d26[0] │ │ + vtbx.8 d18, {d8-d9}, d22 │ │ vtbl.8 d19, {d25-d27}, d14 │ │ movs r4, r2 │ │ │ │ 000fa690 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -123727,16 +123727,16 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r0, sp, #24 │ │ blx 2306f0 <__emutls_get_address@@Base+0x3868> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ adds r7, #122 @ 0x7a │ │ movs r4, r2 │ │ stmia r6!, {r0, r1, r4, r7} │ │ - vcge.s32 d31, d27, #0 │ │ - vtbl.8 d16, {d24-d27}, d14 │ │ + vtbl.8 d16, {d9-d12}, d23 │ │ + vclt.f32 d18, d10, #0 │ │ vqshl.u32 d19, d18, #25 │ │ movs r4, r2 │ │ │ │ 000fa9ec : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -125152,23 +125152,23 @@ │ │ add r0, sp, #812 @ 0x32c │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ adds r5, #232 @ 0xe8 │ │ movs r4, r2 │ │ strb r0, [r5, #24] │ │ - vqshl.u64 d28, d9, #57 @ 0x39 │ │ - vcvt.f32.u32 , q6, #8 │ │ - @ instruction: 0xfff85ab3 │ │ - vqshl.u32 q14, , #25 │ │ - vcvt.f32.u32 d31, d24, #8 │ │ - @ instruction: 0xfff8eed2 │ │ - vpadal.u32 q8, │ │ - vcvt.f32.u32 d31, d6, #6 │ │ - vshll.u32 q9, d8, #24 │ │ + vrshr.u32 d30, d5, #7 │ │ + @ instruction: 0xfff818d8 │ │ + @ instruction: 0xfff95ab3 │ │ + vsra.u64 q15, , #7 │ │ + @ instruction: 0xfff818b4 │ │ + vtbx.8 d16, {d9-d10}, d14 │ │ + vmlsl.u q8, d25, d29[0] │ │ + @ instruction: 0xfffa1892 │ │ + vshll.u32 q9, d8, #25 │ │ movs r4, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #28 │ │ mov r9, r1 │ │ ldr r1, [pc, #556] @ (fbb44 ) │ │ @@ -125592,17 +125592,17 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ ldr r0, [sp, #16] │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ movs r5, #74 @ 0x4a │ │ movs r4, r2 │ │ str r7, [sp, #836] @ 0x344 │ │ - vqrshrun.s64 d31, , #7 │ │ - vtbl.8 d31, {d8}, d12 │ │ - vrsra.u64 d18, d20, #8 │ │ + vrshr.u64 , , #7 │ │ + vsubl.u , d25, d8 │ │ + vrsra.u64 d18, d20, #7 │ │ movs r4, r2 │ │ │ │ 000fbd9c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #96 @ 0x60 │ │ @@ -127399,20 +127399,20 @@ │ │ ldrb.w r0, [sp, #84] @ 0x54 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #92] @ 0x5c │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ - stmia r6!, {r3, r6, r7} │ │ + b.n fd640 │ │ vrshr.u64 , q5, #8 │ │ - vsra.u64 d30, d10, #7 │ │ + vcvt.f16.u16 d31, d6, #7 │ │ vqrdmlsh.s q12, q12, d26[0] │ │ vrshr.u64 , q15, #8 │ │ - vsra.u64 d30, d30, #7 │ │ + vcvt.f16.u16 d31, d26, #7 │ │ vcls.s32 d17, d24 │ │ movs r4, r2 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [r0, #4] │ │ cmp r0, #0 │ │ @@ -127463,15 +127463,15 @@ │ │ str r5, [r4, #16] │ │ pop {r4, r5, r7, pc} │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (fd454 ) │ │ add r0, pc │ │ bl a91f8 │ │ - lsls r1, r3, #23 │ │ + movs r0, #85 @ 0x55 │ │ vsli.64 , q0, #57 @ 0x39 │ │ add r7, sp, #8 │ │ subs r2, r1, r0 │ │ clz r2, r2 │ │ mov.w r2, r2, lsr #5 │ │ strb r2, [r1, #12] │ │ beq.n fd4f0 │ │ @@ -127623,15 +127623,15 @@ │ │ ldmia.w sp!, {r4, r5, r7, lr} │ │ b.w 2300a8 <__emutls_get_address@@Base+0x3220> │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (fd5f8 ) │ │ add r0, pc │ │ bl a91f8 │ │ - lsls r5, r6, #16 │ │ + subs r1, r6, #2 │ │ vsli.64 , q8, #57 @ 0x39 │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ ldr r5, [pc, #88] @ (fd660 ) │ │ mov r4, r0 │ │ add r5, pc │ │ ldrb r0, [r5, #16] │ │ @@ -127730,15 +127730,15 @@ │ │ blx 2307d0 <__emutls_get_address@@Base+0x3948> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ adds r5, #162 @ 0xa2 │ │ movs r4, r2 │ │ lsrs r4, r6, #8 │ │ movs r4, r2 │ │ - push {r0, r1, r2, r3, r4, r5, r6} │ │ + ldmia r6, {r0, r1, r3, r4, r5, r6, r7} │ │ vshll.u32 q8, d12, #24 │ │ movs r4, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ ldr r6, [pc, #80] @ (fd76c ) │ │ add r6, pc │ │ @@ -128541,15 +128541,15 @@ │ │ nop │ │ adds r0, #152 @ 0x98 │ │ movs r4, r2 │ │ ldrb r7, [r1, #5] │ │ vqshlu.s64 d29, d5, #57 @ 0x39 │ │ @ instruction: 0xe8262e0b │ │ subs r6, #17 │ │ - add r2, pc, #532 @ (adr r2, fe140 ) │ │ + pop {r0, pc} │ │ vsra.u32 , q0, #8 │ │ vsri.64 q8, q3, #7 │ │ movs r4, r2 │ │ lsls r6, r6, #18 │ │ movs r4, r2 │ │ lsls r2, r7, #17 │ │ movs r4, r2 │ │ @@ -128744,33 +128744,33 @@ │ │ ldrne r0, [sp, #176] @ 0xb0 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ lsls r6, r7, #20 │ │ movs r4, r2 │ │ add r0, sp, #800 @ 0x320 │ │ - vtbl.8 d26, {d25-d27}, d12 │ │ + vceq.f32 d28, d8, #0 │ │ @ instruction: 0xfff8fffc │ │ movs r3, r2 │ │ cmp r5, #77 @ 0x4d │ │ vqrshrn.u64 d22, , #8 │ │ vabs.s32 d16, d2 │ │ movs r4, r2 │ │ - add r0, pc, #324 @ (adr r0, fe294 ) │ │ + revsh r5, r1 │ │ @ instruction: 0xfff868f7 │ │ vsubl.u q8, d25, d4 │ │ movs r4, r2 │ │ strh r5, [r3, #38] @ 0x26 │ │ vqrshrun.s64 d22, , #8 │ │ vclt.s32 d16, d6, #0 │ │ movs r4, r2 │ │ lsls r2, r7, #5 │ │ movs r4, r2 │ │ str r5, [r7, #108] @ 0x6c │ │ - @ instruction: 0xfff89b70 │ │ + @ instruction: 0xfff8b5ec │ │ vrev16.32 q8, q1 │ │ movs r4, r2 │ │ lsls r4, r0, #5 │ │ movs r4, r2 │ │ lsls r6, r7, #2 │ │ movs r4, r2 │ │ lsls r6, r0, #1 │ │ @@ -129032,15 +129032,15 @@ │ │ bl 1a5c7c │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ movs r2, #102 @ 0x66 │ │ movs r4, r2 │ │ stc2 0, cr0, [r4, #-76] @ 0xffffffb4 │ │ add r5, pc, #540 @ (adr r5, fe638 ) │ │ - vsra.u32 , , #7 │ │ + @ instruction: 0xfff9cbd9 │ │ vqdmulh.s , q12, d8[0] │ │ movs r3, r2 │ │ ldr r0, [pc, #4] @ (fe42c ) │ │ add r0, pc │ │ b.w fd5fc │ │ movs r7, #234 @ 0xea │ │ movs r4, r2 │ │ @@ -130410,16 +130410,16 @@ │ │ movs r0, r0 │ │ subs r3, #158 @ 0x9e │ │ @ instruction: 0xfff97ed2 │ │ vceq.f32 q13, , #0 │ │ vsri.64 d22, d30, #7 │ │ @ instruction: 0xfff87eb0 │ │ vceq.f32 q13, , #0 │ │ - vcvt.f16.u16 d30, d23, #7 │ │ - @ instruction: 0xfff87ef4 │ │ + vqshlu.s64 d16, d19, #57 @ 0x39 │ │ + @ instruction: 0xfff97ef4 │ │ vsli.64 d26, d1, #57 @ 0x39 │ │ vcvt.u32.f32 q15, q3, #7 │ │ movs r3, r2 │ │ strh r6, [r2, #34] @ 0x22 │ │ movs r3, r2 │ │ bmi.n ff2f8 │ │ bmi.n ff2fa │ │ @@ -130869,18 +130869,18 @@ │ │ beq.n ff7f8 │ │ ldr r0, [sp, #72] @ 0x48 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldc 0, cr0, [r4, #-76]! @ 0xffffffb4 │ │ b.n ff46c │ │ vcvt.f16.u16 d22, d9, #7 │ │ - @ instruction: 0xfff883c5 │ │ + vqrdmlah.s , q4, d1[0] │ │ vsli.64 q15, q8, #56 @ 0x38 │ │ @ instruction: 0xfff96bd5 │ │ - vsubw.u q12, q12, d1 │ │ + @ instruction: 0xfff89dfd │ │ vqrshrn.u64 d30, q8, #8 │ │ movs r3, r2 │ │ │ │ 000ff81c : │ │ push {r7, lr} │ │ mov r7, sp │ │ sub sp, #8 │ │ @@ -131202,15 +131202,15 @@ │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ b.n ff6e0 │ │ movs r3, r2 │ │ b.n fffe0 │ │ vneg.f32 q11, │ │ - @ instruction: 0xfff87fa7 │ │ + vtbl.8 d25, {d8-d10}, d19 │ │ vsli.32 d30, d28, #24 │ │ movs r3, r2 │ │ │ │ 000ffbcc : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -135858,15 +135858,15 @@ │ │ movs r0, r0 │ │ ldrb r0, [r0, #30] │ │ ldr r4, [pc, #424] @ (102e9c ) │ │ movs r3, r2 │ │ push {r1, r3, r4, r5, r6, lr} │ │ movs r3, r2 │ │ lsls r7, r5, #3 │ │ - @ instruction: 0xfff979b6 │ │ + vsri.32 d25, d18, #7 │ │ vtbx.8 d17, {d8-d10}, d14 │ │ vcls.s32 , q2 │ │ movs r3, r2 │ │ │ │ 00102d08 : │ │ b.w 230234 <__emutls_get_address@@Base+0x33ac> │ │ │ │ @@ -136107,18 +136107,18 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #280 @ 0x118 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ cbz r0, 102fcc │ │ movs r3, r2 │ │ str r0, [sp, #820] @ 0x334 │ │ - @ instruction: 0xfff96cfb │ │ + vqshl.u32 q12, , #25 │ │ vqshrn.u64 d17, q8, #8 │ │ vcvt.u16.f16 , , #8 │ │ - @ instruction: 0xfff76c91 │ │ + vcvt.s16.f16 d24, d13 │ │ vtbx.8 d17, {d24}, d6 │ │ vaddw.u , q12, d20 │ │ movs r3, r2 │ │ │ │ 00102f88 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -136550,15 +136550,15 @@ │ │ b.n 1033ce │ │ add r0, sp, #100 @ 0x64 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r5, sp, #632 @ 0x278 │ │ movs r3, r2 │ │ ldrh r3, [r0, #26] │ │ - vtbl.8 d20, {d9-d12}, d18 │ │ + vsli.64 d22, d14, #57 @ 0x39 │ │ @ instruction: 0xfff81340 │ │ @ instruction: 0xfff8ad2c │ │ movs r3, r2 │ │ │ │ 001033ec : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -137351,15 +137351,15 @@ │ │ nop │ │ strb r5, [r2, r5] │ │ strb r5, [r2, r5] │ │ strb r5, [r2, r5] │ │ subs r7, #213 @ 0xd5 │ │ add r2, sp, #888 @ 0x378 │ │ movs r3, r2 │ │ - str r3, [sp, #344] @ 0x158 │ │ + add r5, sp, #840 @ 0x348 │ │ vqrdmlsh.s , q4, d19[0] │ │ vtbx.8 d16, {d9-d11}, d24 │ │ @ instruction: 0xfff8fa5e │ │ vqrdmlsh.s , , d1[0] │ │ vtbx.8 d16, {d9-d11}, d6 │ │ vclz.i32 q13, q12 │ │ movs r3, r2 │ │ @@ -138030,15 +138030,15 @@ │ │ strb r5, [r2, r5] │ │ subs r7, #213 @ 0xd5 │ │ lsls r0, r6, #20 │ │ b.n 103dea │ │ vqrdmulh.s32 d2, d14, d27 │ │ add r3, pc, #512 @ (adr r3, 1046d4 ) │ │ movs r3, r2 │ │ - ldr r2, [sp, #380] @ 0x17c │ │ + push {r0, r1, r3, r4, r6, r7} │ │ @ instruction: 0xfff889d9 │ │ vrshr.u64 q8, q6, #7 │ │ vrev16.32 d30, d22 │ │ @ instruction: 0xfff789b7 │ │ vrshr.u64 d16, d26, #7 │ │ vqdmulh.s , q12, d20[0] │ │ movs r3, r2 │ │ @@ -138135,16 +138135,16 @@ │ │ b.n 1045d4 │ │ add r0, sp, #156 @ 0x9c │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldr r3, [sp, #648] @ 0x288 │ │ movs r3, r2 │ │ - cmp ip, r8 │ │ - vshr.u64 d22, d20, #8 │ │ + str r0, [r0, #4] │ │ + @ instruction: 0xfff87b30 │ │ vrev16.32 q8, q1 │ │ @ instruction: 0xfff89b30 │ │ movs r3, r2 │ │ │ │ 001045f4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -145188,15 +145188,15 @@ │ │ movs r0, r0 │ │ ldrb r1, [r0, r3] │ │ movs r0, r0 │ │ ldrsb r7, [r6, r6] │ │ movs r0, r0 │ │ add r0, pc, #704 @ (adr r0, 109ad8 ) │ │ vrsra.u64 d24, d2, #9 │ │ - vtbx.8 d29, {d7-d10}, d23 │ │ + vrsqrte.f16 , │ │ vsli.64 , q8, #55 @ 0x37 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ subw sp, sp, #1124 @ 0x464 │ │ ldr.w r3, [pc, #1700] @ 109ed4 │ │ mov.w fp, #0 │ │ add r3, pc │ │ @@ -145758,17 +145758,17 @@ │ │ itt ne │ │ cmpne r0, #0 │ │ blxne 230900 <__emutls_get_address@@Base+0x3a78> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldr r0, [pc, #464] @ (10a0a8 ) │ │ movs r3, r2 │ │ - adds r1, #215 @ 0xd7 │ │ - vtbx.8 d16, {d8}, d25 │ │ - vrsra.u64 , , #8 │ │ + ldr r4, [pc, #332] @ (10a028 ) │ │ + vpaddl.u32 q9, │ │ + vcvt.f32.u32 q15, , #8 │ │ vrshr.u32 d20, d16, #9 │ │ movs r3, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8} │ │ @@ -146713,17 +146713,17 @@ │ │ itt ne │ │ cmpne r0, #0 │ │ blxne 230900 <__emutls_get_address@@Base+0x3a78> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ subs r4, #204 @ 0xcc │ │ movs r3, r2 │ │ - movs r6, #231 @ 0xe7 │ │ - vcvt.u16.f16 , , #8 │ │ - vtbl.8 d28, {d7-d8}, d13 │ │ + adcs r3, r4 │ │ + vqshl.u64 , , #56 @ 0x38 │ │ + vsubw.u q15, q12, d9 │ │ vcvt.s16.f16 , q0 │ │ movs r3, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8} │ │ @@ -147656,17 +147656,17 @@ │ │ itt ne │ │ cmpne r0, #0 │ │ blxne 230900 <__emutls_get_address@@Base+0x3a78> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ adds r2, #36 @ 0x24 │ │ movs r3, r2 │ │ - adds r3, r1, #0 │ │ - vrshr.u64 d31, d13, #8 │ │ - vcvt.f32.u32 d27, d17, #9 │ │ + adds r6, #135 @ 0x87 │ │ + vcvt.u16.f16 d16, d9, #8 │ │ + vtbl.8 d29, {d24}, d29 │ │ vdup.8 q9, d22[3] │ │ movs r3, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8} │ │ @@ -148583,17 +148583,17 @@ │ │ cmp r0, r4 │ │ itt ne │ │ cmpne r0, #0 │ │ blxne 230900 <__emutls_get_address@@Base+0x3a78> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ movs r6, #162 @ 0xa2 │ │ movs r3, r2 │ │ - asrs r1, r5, #5 │ │ - vqshl.u64 q15, , #56 @ 0x38 │ │ - vcvtm.u16.f16 d27, d15 │ │ + cmp r3, #229 @ 0xe5 │ │ + vrshr.u32 q8, , #8 │ │ + @ instruction: 0xfff8ce0b │ │ vcvtn.u16.f16 q9, q1 │ │ movs r3, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8} │ │ @@ -149548,17 +149548,17 @@ │ │ itt ne │ │ cmpne r0, #0 │ │ blxne 230900 <__emutls_get_address@@Base+0x3a78> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ adds r4, r1, #1 │ │ movs r3, r2 │ │ - lsls r7, r2, #24 │ │ - vmull.u , d24, d25 │ │ - vqshrun.s64 d26, , #9 │ │ + movs r0, #147 @ 0x93 │ │ + vqabs.s32 d31, d21 │ │ + vrshr.u64 d28, d25, #9 │ │ vqshlu.s32 , q8, #23 │ │ movs r3, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8} │ │ @@ -150487,17 +150487,17 @@ │ │ cmp r0, r9 │ │ itt ne │ │ cmpne r0, #0 │ │ blxne 230900 <__emutls_get_address@@Base+0x3a78> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ asrs r4, r4, #2 │ │ movs r3, r2 │ │ - @ instruction: 0xfb49fff7 │ │ - bne.n 10d522 │ │ - vqrdmulh.s , , d31[0] │ │ + asrs r5, r0, #23 │ │ + vcvt.f16.u16 q15, , #8 │ │ + vcvt.u16.f16 , │ │ vtbl.8 d16, {d23-d26}, d18 │ │ movs r3, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8} │ │ @@ -151429,17 +151429,17 @@ │ │ cmp r0, r4 │ │ itt ne │ │ cmpne r0, #0 │ │ blxne 230900 <__emutls_get_address@@Base+0x3a78> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ lsls r0, r4, #24 │ │ movs r3, r2 │ │ - bl 17c032 │ │ - stmia r6!, {r0, r1, r2, r3, r4, r5, r6, r7} │ │ - vrshr.u64 d25, d3, #9 │ │ + lsrs r1, r5, #11 │ │ + vsra.u32 q15, , #8 │ │ + @ instruction: 0xfff7ad0f │ │ vcvta.u16.f16 q8, q3 │ │ movs r3, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8} │ │ @@ -152293,17 +152293,17 @@ │ │ cmp r0, r4 │ │ itt ne │ │ cmpne r0, #0 │ │ blxne 230900 <__emutls_get_address@@Base+0x3a78> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ @ instruction: 0xfb8a0012 │ │ - b.n 10e72a │ │ - @ instruction: 0xfff7bd09 │ │ - @ instruction: 0xfff7889d │ │ + lsls r3, r6, #3 │ │ + vqneg.s32 d29, d5 │ │ + vrsra.u32 d26, d9, #9 │ │ vqshlu.s64 , q1, #55 @ 0x37 │ │ movs r2, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8} │ │ @@ -153135,17 +153135,17 @@ │ │ cmp r0, r4 │ │ itt ne │ │ cmpne r0, #0 │ │ blxne 230900 <__emutls_get_address@@Base+0x3a78> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ rsb r0, r6, #18 │ │ - bgt.n 10f39a │ │ - vrsra.u32 , , #9 │ │ - @ instruction: 0xfff77f0d │ │ + bl 733ba │ │ + ldmia r5, {r0, r2, r4, r5, r6, r7} │ │ + vtbl.8 d25, {d23-d24}, d9 │ │ vqrdmulh.s q15, , d2[0] │ │ movs r2, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8} │ │ @@ -154298,39 +154298,39 @@ │ │ add r0, sp, #340 @ 0x154 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ b.n 10fb44 │ │ movs r2, r2 │ │ adds r7, r1, #1 │ │ - vcvt.f16.u16 , , #9 │ │ + vqshlu.s64 , , #55 @ 0x37 │ │ vtbl.8 d20, {d23-d24}, d2 │ │ vqshl.u32 d18, d26, #23 │ │ - vcvt.f16.u16 d25, d19, #9 │ │ + vcvt.f16.u16 d27, d31 │ │ vtbx.8 d20, {d7-d8}, d16 │ │ - vqshl.u32 d27, d30, #23 │ │ - vtbl.8 d25, {d23-d26}, d27 │ │ + vsra.u64 d29, d26, #9 │ │ + vcvt.f16.s16 d27, d23 │ │ @ instruction: 0xfff748d8 │ │ - vcvta.u16.f16 d29, d13 │ │ - vtbl.8 d25, {d23-d26}, d9 │ │ + vtbl.8 d30, {d7-d10}, d9 │ │ + vcvt.f16.s16 d27, d5 │ │ @ instruction: 0xfff748b6 │ │ - vcvt.u16.f16 d27, d2 │ │ - vtbx.8 d25, {d23-d26}, d31 │ │ + vsra.u64 , q15, #9 │ │ + vcvt.f16.s16 , │ │ vqshrn.u64 d20, q6, #9 │ │ - vshr.u64 , , #9 │ │ - vtbx.8 d25, {d23-d26}, d13 │ │ + vtbx.8 d30, {d7-d10}, d13 │ │ + vcvt.f16.s16 , │ │ @ instruction: 0xfff748fa │ │ @ instruction: 0xfff798ff │ │ - vcvt.f16.u16 d25, d1, #8 │ │ + vpadal.u32 d27, d13 │ │ vqshrn.u64 d20, q15, #9 │ │ vtbx.8 d16, {d7}, d16 │ │ - @ instruction: 0xfff89d83 │ │ + vqshl.u64 , , #56 @ 0x38 │ │ @ instruction: 0xfff74ab0 │ │ - vcvta.u16.f16 d29, d0 │ │ - vtbx.8 d25, {d7-d10}, d23 │ │ + @ instruction: 0xfff7eafc │ │ + vrsqrte.f16 , │ │ @ instruction: 0xfff74894 │ │ vrshr.u32 d30, d28, #9 │ │ movs r2, r2 │ │ │ │ 00110090 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -154889,18 +154889,18 @@ │ │ subs r6, #128 @ 0x80 │ │ movs r0, r0 │ │ movs r0, r0 │ │ movs r0, r0 │ │ subs r4, #176 @ 0xb0 │ │ svc 254 @ 0xfe │ │ movs r2, r2 │ │ - str r5, [sp, #464] @ 0x1d0 │ │ + add r7, sp, #960 @ 0x3c0 │ │ vsra.u64 d21, d9, #9 │ │ vrshr.u64 d20, d0, #9 │ │ - vsli.64 q12, , #55 @ 0x37 │ │ + vshr.u32 q13, , #9 │ │ vsra.u32 , , #9 │ │ vcvtp.s16.f16 q10, q6 │ │ vqshlu.s64 d23, d6, #55 @ 0x37 │ │ movs r2, r2 │ │ strb r6, [r4, #21] │ │ movs r2, r2 │ │ strb r4, [r5, #29] │ │ @@ -155205,26 +155205,26 @@ │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strb r0, [r2, #15] │ │ movs r2, r2 │ │ bls.n 110984 │ │ movs r2, r2 │ │ ldc2 15, cr15, [sp, #-988]! @ 0xfffffc24 │ │ - strh r0, [r3, #20] │ │ + ldr r5, [sp, #80] @ 0x50 │ │ vqrdmlah.s , , d30[0] │ │ vsri.32 q14, q12, #9 │ │ - vrshr.u32 q12, q11, #8 │ │ + @ instruction: 0xfff89cf2 │ │ vqrdmlah.s , , d12[0] │ │ vrsra.u32 d23, d20, #9 │ │ movs r2, r2 │ │ strh r3, [r2, #34] @ 0x22 │ │ vqshrun.s64 d24, , #1 │ │ vmla.i , , d0[0] │ │ vrshr.u64 q8, , #8 │ │ - vtbl.8 d22, {d7-d8}, d27 │ │ + vcvtm.u16.f16 d24, d23 │ │ vcvt.u16.f16 d29, d18 │ │ movs r2, r2 │ │ │ │ 00110a40 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -155508,29 +155508,29 @@ │ │ add r0, sp, #72 @ 0x48 │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strb r2, [r6, #1] │ │ movs r2, r2 │ │ bvs.n 110de4 │ │ movs r2, r2 │ │ - ldrh r3, [r4, #52] @ 0x34 │ │ + add r1, sp, #124 @ 0x7c │ │ vrshr.u32 q9, q12, #9 │ │ @ instruction: 0xfff83b9c │ │ - vqshl.u64 d27, d10, #55 @ 0x37 │ │ + vrshr.u32 d29, d6, #9 │ │ vrshr.u32 q9, q3, #9 │ │ @ instruction: 0xfff83b7a │ │ vcvta.s16.f16 d23, d18 │ │ movs r2, r2 │ │ ldrh r3, [r6, #0] │ │ vtbx.8 d24, {d15}, d19 │ │ vsri.32 , q3, #1 │ │ movs r2, r2 │ │ ldmia r4!, {r1, r2, r3, r5, r6, r7} │ │ @ instruction: 0xfff87db3 │ │ - vsli.64 q11, , #56 @ 0x38 │ │ + vshr.u32 q12, , #8 │ │ Address 0x110d82 is out of bounds. │ │ │ │ │ │ 00110d84 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -155860,28 +155860,28 @@ │ │ add r0, sp, #72 @ 0x48 │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r6, [r0, #84] @ 0x54 │ │ movs r2, r2 │ │ bcc.n 1110f0 │ │ movs r2, r2 │ │ - ldrh r0, [r6, #24] │ │ - vcvtm.u16.f16 d22, d24 │ │ + add r5, pc, #688 @ (adr r5, 11138c ) │ │ + @ instruction: 0xfff77e24 │ │ vqshrun.s64 d19, q2, #9 │ │ - vcvtm.u16.f16 d22, d18 │ │ - vcvtm.u16.f16 d22, d6 │ │ + vcvt.f32.u32 d23, d14, #9 │ │ + @ instruction: 0xfff77e02 │ │ vqshl.u64 , q9, #55 @ 0x37 │ │ vcvt.s16.f16 , q3 │ │ - @ instruction: 0xfff86364 │ │ + vqrdmulh.s , q12, d16[0] │ │ vqshl.u64 , q0, #55 @ 0x37 │ │ - vshr.u32 q14, , #9 │ │ - vcvtm.u16.f16 q11, q14 │ │ + @ instruction: 0xfff7dad1 │ │ + vqrdmlah.s , , d24[0] │ │ vqrshrun.s64 d19, q4, #9 │ │ vtbl.8 d18, {d23}, d28 │ │ - vcvtm.u16.f16 q11, q5 │ │ + vqrdmlah.s , , d6[0] │ │ vqshrun.s64 d19, q11, #9 │ │ vcvtn.s16.f16 d29, d10 │ │ movs r2, r2 │ │ │ │ 00111118 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -156527,33 +156527,33 @@ │ │ add r0, sp, #48 @ 0x30 │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldmia r7!, {r3, r4, r5, r6} │ │ movs r2, r2 │ │ strb r7, [r2, #16] │ │ - vcvt.u16.f16 d21, d20, #8 │ │ + vqshl.u64 d23, d16, #56 @ 0x38 │ │ vcvtn.u16.f16 d19, d16 │ │ vrecpe.u16 , q13 │ │ - vcvt.u16.f16 , q12, #8 │ │ + vqshl.u64 , q10, #56 @ 0x38 │ │ vcvtn.u16.f16 , q10 │ │ - @ instruction: 0xfff7c8d7 │ │ - vcvt.u16.f16 , q3, #9 │ │ + vrsra.u32 q15, , #9 │ │ + vqshl.u64 , q1, #55 @ 0x37 │ │ vcvtn.u16.f16 , q1 │ │ vshr.u64 , q10, #9 │ │ - vcvt.u16.f16 d21, d2, #8 │ │ + vqneg.s32 d23, d14 │ │ vsra.u32 , q15, #9 │ │ vcvta.u16.f16 , │ │ - @ instruction: 0xfff85cf0 │ │ + vqabs.s32 , q14 │ │ vsra.u32 , q6, #9 │ │ - vqdmulh.s , , d26[0] │ │ - vqdmulh.s , , d14[0] │ │ + vcvt.s16.f16 , q11 │ │ + vcvt.s16.f16 , q5 │ │ vsra.u32 d19, d26, #9 │ │ vcvta.u16.f16 q12, q13 │ │ - vmull.u , d24, d28 │ │ + vqabs.s32 d23, d24 │ │ vsra.u32 d19, d8, #9 │ │ @ instruction: 0xfff7ca96 │ │ movs r2, r2 │ │ │ │ 00111844 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -156951,15 +156951,15 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldmia r0!, {r1, r2, r6} │ │ movs r2, r2 │ │ cmp r5, #39 @ 0x27 │ │ @ instruction: 0xfff73bd8 │ │ @ instruction: 0xfff72c9c │ │ - vrsqrte.u16 d27, d14 │ │ + @ instruction: 0xfff7cf0a │ │ @ instruction: 0xfff73bb6 │ │ vcvt.f16.u16 q9, q13, #9 │ │ @ instruction: 0xfff76ef5 │ │ @ instruction: 0xfff83b94 │ │ vcvt.f16.u16 q9, q4, #9 │ │ vqdmulh.s , , d3[0] │ │ @ instruction: 0xfff73b72 │ │ @@ -157245,15 +157245,15 @@ │ │ vtbx.8 d18, {d7-d8}, d24 │ │ vcvt.f16.s16 , │ │ vabdl.u , d31, d17 │ │ vrshr.u64 d28, d0, #1 │ │ movs r2, r2 │ │ revsh r4, r1 │ │ vrsra.u32 q10, , #8 │ │ - vrsra.u64 d21, d25, #8 │ │ + vcvt.f32.u32 d22, d21, #8 │ │ Address 0x111fc2 is out of bounds. │ │ │ │ │ │ 00111fc4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -157424,15 +157424,15 @@ │ │ stmia r0!, {r2, r3, r6, r7} │ │ movs r2, r2 │ │ lsrs r3, r3, #24 │ │ vqabs.s32 d23, d4 │ │ vqabs.s32 d18, d26 │ │ vtbl.8 d21, {d23-d26}, d4 │ │ movs r2, r2 │ │ - ldrsh r2, [r4, r2] │ │ + ldrb r6, [r3, #4] │ │ vcvt.f16.u16 , q9 │ │ vqabs.s32 d18, d8 │ │ vcvtm.s16.f16 q9, │ │ vpadal.u32 , q0 │ │ vpadal.u32 q9, q11 │ │ vqrdmlsh.s , , d22[0] │ │ movs r2, r2 │ │ @@ -157720,15 +157720,15 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ pop {r4, r5, r6, r7, pc} │ │ movs r2, r2 │ │ movs r4, #3 │ │ vrshr.u64 d30, d21, #8 │ │ vsri.32 d18, d24, #9 │ │ - vdup.8 q13, d0[3] │ │ + vqshlu.s64 d28, d28, #55 @ 0x37 │ │ vrshr.u64 d30, d3, #9 │ │ vsri.32 d18, d6, #9 │ │ vcvtm.s16.f16 , q5 │ │ vrshr.u32 q15, , #9 │ │ vrsra.u64 q9, q10, #9 │ │ vqdmulh.s , , d26[0] │ │ movs r2, r2 │ │ @@ -157954,15 +157954,15 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ cbnz r2, 112780 │ │ movs r2, r2 │ │ ldr r2, [pc, #912] @ (112a9c ) │ │ vsri.32 q11, , #8 │ │ vsra.u64 d18, d20, #8 │ │ - vsli.32 q11, , #23 │ │ + @ instruction: 0xfff77fd9 │ │ vrecpe.u16 q11, │ │ vsra.u64 d18, d2, #8 │ │ vtbx.8 d27, {d7-d9}, d22 │ │ movs r2, r2 │ │ │ │ 00112724 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -158217,18 +158217,18 @@ │ │ add r0, sp, #172 @ 0xac │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ @ instruction: 0xb81a │ │ movs r2, r2 │ │ ble.n 112a70 │ │ - @ instruction: 0xfff77da8 │ │ + vtbl.8 d25, {d7}, d20 │ │ vqrdmlah.s , , d6[0] │ │ vqrdmulh.s , , d3[0] │ │ - @ instruction: 0xfff87d86 │ │ + vtbl.8 d25, {d8}, d2 │ │ @ instruction: 0xfff71ea4 │ │ vqshl.u32 , q12, #23 │ │ movs r2, r2 │ │ │ │ 001129dc : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -158500,15 +158500,15 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ @ instruction: 0xb6ba │ │ movs r2, r2 │ │ strh r4, [r3, #44] @ 0x2c │ │ vrev64.32 , q15 │ │ vmull.u , d8, d4 │ │ - vqrdmlsh.s , , d6[0] │ │ + vtbx.8 d23, {d7-d9}, d2 │ │ vcvta.s16.f16 , q6 │ │ vtbx.8 d17, {d24-d27}, d18 │ │ vsri.64 d27, d22, #9 │ │ movs r2, r2 │ │ │ │ 00112cd0 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -159222,27 +159222,27 @@ │ │ add r0, sp, #664 @ 0x298 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ sub sp, #448 @ 0x1c0 │ │ movs r2, r2 │ │ str r2, [r2, #80] @ 0x50 │ │ - vqdmulh.s q10, q12, d7[0] │ │ + vqabs.s32 q11, │ │ vrecpe.f16 d17, d24 │ │ @ instruction: 0xfff7ee23 │ │ - vmull.u q10, d23, d21 │ │ + vcvt.s16.f16 d22, d17 │ │ vrecpe.f16 d17, d6 │ │ vtbl.8 d25, {d7-d10}, d31 │ │ - vmull.u q10, d24, d3 │ │ + vqshlu.s64 q11, , #56 @ 0x38 │ │ vrsqrte.u16 , q10 │ │ vrecpe.u16 d18, d29 │ │ - vdup.8 q10, d17[3] │ │ + vqshlu.s64 q11, , #55 @ 0x37 │ │ vrsqrte.u16 , q1 │ │ vcvtm.u16.f16 d31, d5 │ │ - vcvt.f16.u16 d20, d31, #10 │ │ + vqshlu.s64 d22, d27, #54 @ 0x36 │ │ vrsqrte.u16 d17, d16 │ │ @ instruction: 0xfff7addc │ │ movs r2, r2 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ adds r0, #112 @ 0x70 │ │ @@ -159524,27 +159524,27 @@ │ │ b.n 11372c │ │ b.n 113732 │ │ add r0, sp, #532 @ 0x214 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r4, sp, #8 │ │ movs r2, r2 │ │ - strb r7, [r1, r6] │ │ + strb r3, [r1, #0] │ │ vcvt.f16.s16 d29, d9 │ │ vzip.16 d17, d16 │ │ - vcvt.u32.f32 d24, d13, #9 │ │ + @ instruction: 0xfff7a999 │ │ vcvt.s16.f16 , │ │ vqmovn.u32 d17, q11 │ │ vqrdmlsh.s , , d24[0] │ │ @ instruction: 0xfff8d5e7 │ │ vsra.u32 , q15, #10 │ │ vrsqrte.f16 q10, q10 │ │ @ instruction: 0xfff8d5c5 │ │ vsra.u32 , q6, #10 │ │ - vqrshrn.u64 d20, , #9 │ │ + vrsra.u64 q11, , #9 │ │ vcvt.f16.s16 d29, d27 │ │ vzip.16 , q1 │ │ @ instruction: 0xfff7aa76 │ │ movs r2, r2 │ │ │ │ 00113798 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -159801,24 +159801,24 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ add r0, sp, #984 @ 0x3d8 │ │ movs r2, r2 │ │ str r5, [sp, #124] @ 0x7c │ │ vqrdmulh.s q11, q4, d21[0] │ │ @ instruction: 0xfff80eb8 │ │ - vcvt.f16.u16 d24, d1, #9 │ │ + vcvt.f16.u16 d26, d13 │ │ @ instruction: 0xfff76e87 │ │ @ instruction: 0xfff80fda │ │ vsli.32 d25, d6, #23 │ │ vqrdmulh.s q11, q4, d3[0] │ │ @ instruction: 0xfff80e96 │ │ vrshr.u64 q10, q14, #9 │ │ @ instruction: 0xfff86d21 │ │ vcvt.f32.u32 q8, q10, #8 │ │ - vcvt.f16.u16 d20, d15 │ │ + vcvtn.s16.f16 d22, d11 │ │ @ instruction: 0xfff76d87 │ │ @ instruction: 0xfff80eda │ │ vcvt.u16.f16 d26, d14 │ │ movs r2, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -162201,20 +162201,20 @@ │ │ cmpne r0, #0 │ │ blxne 230900 <__emutls_get_address@@Base+0x3a78> │ │ add r0, sp, #280 @ 0x118 │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ str r1, [sp, #424] @ 0x1a8 │ │ movs r2, r2 │ │ - ldrb r2, [r6, #11] │ │ + str r5, [sp, #440] @ 0x1b8 │ │ vcvtn.u16.f16 , q2 │ │ - @ instruction: 0xfff81d87 │ │ + vtbl.8 d19, {d8}, d3 │ │ vqrdmulh.s q14, , d15[0] │ │ vrsra.u64 , , #10 │ │ - @ instruction: 0xfff61da7 │ │ + vtbl.8 d19, {d6}, d19 │ │ vsli.64 , q8, #55 @ 0x37 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ vpush {d8-d9} │ │ subw sp, sp, #2248 @ 0x8c8 │ │ mov ip, r0 │ │ @@ -169102,26 +169102,26 @@ │ │ itt ne │ │ ldrne r0, [sp, #28] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ands r6, r3 │ │ movs r2, r2 │ │ ldr r2, [r0, #48] @ 0x30 │ │ - @ instruction: 0xfff6ddd8 │ │ + vqrshrun.s64 d31, q2, #10 │ │ vtbl.8 d22, {d22-d24}, d0 │ │ vqshlu.s64 q13, q10, #54 @ 0x36 │ │ - vcvt.f32.u32 d29, d14, #10 │ │ + @ instruction: 0xfff6f89a │ │ vtbx.8 d22, {d22-d24}, d6 │ │ vqrdmlsh.s , q11, d4[0] │ │ movs r2, r2 │ │ add r6, pc, #632 @ (adr r6, 11a510 ) │ │ - @ instruction: 0xfff7dea6 │ │ + vtbl.8 d31, {d7-d8}, d18 │ │ vtbx.8 d22, {d6-d9}, d14 │ │ - vsra.u64 d29, d17, #10 │ │ - @ instruction: 0xfff6ddfc │ │ + vdup.16 d30, d29[1] │ │ + vqrshrun.s64 d31, q12, #10 │ │ vtbl.8 d22, {d22-d24}, d20 │ │ vsli.64 , q8, #54 @ 0x36 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ mov.w ip, #0 │ │ cmp r1, #1 │ │ blt.n 11a2ce │ │ @@ -171081,15 +171081,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ cmp r2, #214 @ 0xd6 │ │ movs r2, r2 │ │ add r5, sp, #908 @ 0x38c │ │ - vmla.i q8, q3, d14[0] │ │ + vtbx.8 d17, {d22-d24}, d10 │ │ vcvt.f16.s16 , q10 │ │ vtbx.8 d18, {d6-d8}, d20 │ │ movs r2, r2 │ │ │ │ 0011b6a0 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -171316,15 +171316,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ cmp r1, #12 │ │ movs r2, r2 │ │ strb r0, [r6, r2] │ │ - vrshr.u32 q14, , #10 │ │ + vqdmulh.s , q11, d29[0] │ │ vrintn.f16 d21, d12 │ │ vqshrun.s64 d18, q1, #10 │ │ movs r2, r2 │ │ │ │ 0011b8f8 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -171919,19 +171919,19 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #28] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ movs r3, #148 @ 0x94 │ │ movs r2, r2 │ │ - asrs r5, r7, #4 │ │ + cmp r3, #185 @ 0xb9 │ │ vqrdmlsh.s , , d15[0] │ │ @ instruction: 0xfff74d82 │ │ - vqshlu.s32 d31, d5, #22 │ │ - vuzp.16 q8, │ │ + vshr.u64 d17, d1, #10 │ │ + vcvtn.s16.f16 q8, │ │ @ instruction: 0xfff84efa │ │ vzip.16 d18, d8 │ │ movs r2, r2 │ │ │ │ 0011bf90 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -172386,15 +172386,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #20] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ subs r0, r5, #0 │ │ movs r2, r2 │ │ - lsls r2, r5, #1 │ │ + subs r6, r4, r3 │ │ vtbx.8 d31, {d23-d25}, d17 │ │ @ instruction: 0xfff74894 │ │ vcvt.f16.f32 d23, q7 │ │ vcvt.f16.u16 d31, d5, #10 │ │ vtbx.8 d20, {d23-d24}, d8 │ │ @ instruction: 0xfff61c98 │ │ movs r2, r2 │ │ @@ -172548,15 +172548,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #20] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ adds r2, r3, #0 │ │ movs r2, r2 │ │ - adds r7, r2, r6 │ │ + adds r4, #19 │ │ vrshr.u32 , , #9 │ │ vcvt.f16.u16 q10, q8 │ │ vtbx.8 d17, {d22-d24}, d20 │ │ movs r2, r2 │ │ │ │ 0011c624 : │ │ push {r4, r5, r7, lr} │ │ @@ -172635,16 +172635,16 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r0, [sp, #28] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ subs r2, r7, r1 │ │ movs r2, r2 │ │ - b.n 11c7d4 │ │ - vqmovn.s32 d23, │ │ + @ instruction: 0xfaf2fff6 │ │ + strb r5, [r4, #10] │ │ vqshlu.s32 d20, d14, #22 │ │ vshll.u32 , d14, #22 │ │ movs r2, r2 │ │ │ │ 0011c6f4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -173133,15 +173133,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ asrs r2, r4, #20 │ │ movs r2, r2 │ │ blt.n 11cce4 │ │ - vtbl.8 d26, {d7}, d5 │ │ + vcvtp.u16.f16 d28, d1 │ │ vshr.u64 q10, q0, #10 │ │ vsri.64 , q2, #10 │ │ movs r2, r2 │ │ │ │ 0011cc34 const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -173450,15 +173450,15 @@ │ │ asrs r0, r4, #15 │ │ movs r2, r2 │ │ asrs r0, r6, #9 │ │ movs r2, r2 │ │ subs r0, #22 │ │ vrecpe.u16 q10, q4 │ │ vqrdmulh.s , , d6[0] │ │ - vmla.i , q3, d19[0] │ │ + @ instruction: 0xfff62adf │ │ vrecpe.u16 d20, d20 │ │ @ instruction: 0xfff73da2 │ │ vsra.u64 , q5, #10 │ │ movs r2, r2 │ │ │ │ 0011cf84 &, cv::Point_&) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -173567,16 +173567,16 @@ │ │ itt ne │ │ ldrne r0, [sp, #28] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ asrs r6, r2, #4 │ │ movs r2, r2 │ │ - lsrs r5, r1, #29 │ │ - vshr.u32 d16, d5, #9 │ │ + cmp r1, #201 @ 0xc9 │ │ + @ instruction: 0xfff71a91 │ │ vcvt.f16.u16 , q5, #9 │ │ vshr.u32 , q7, #10 │ │ movs r2, r2 │ │ │ │ 0011d0ac : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -173749,15 +173749,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #28] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ lsrs r6, r5, #31 │ │ movs r2, r2 │ │ - lsrs r1, r4, #21 │ │ + movs r7, #221 @ 0xdd │ │ vcvt.u32.f32 , , #9 │ │ vtbx.8 d19, {d7-d9}, d30 │ │ vcvt.f32.u32 q8, q10, #10 │ │ movs r2, r2 │ │ │ │ 0011d298 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -174034,27 +174034,27 @@ │ │ b.n 11d578 │ │ add r0, sp, #16 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ lsrs r6, r7, #23 │ │ movs r2, r2 │ │ - lsrs r3, r1, #11 │ │ + movs r5, #71 @ 0x47 │ │ vtbl.8 d24, {d23-d26}, d23 │ │ vqshrun.s64 d19, q2, #9 │ │ vrintm.f16 d30, d27 │ │ vtbx.8 d24, {d7-d10}, d19 │ │ vqshl.u64 , q0, #55 @ 0x37 │ │ vrintm.f16 d25, d18 │ │ vtbx.8 d24, {d7-d10}, d1 │ │ vcvt.u16.f16 d19, d30 │ │ @ instruction: 0xfff6ced9 │ │ @ instruction: 0xfff78b1f │ │ vcvt.u16.f16 d19, d12 │ │ - vsri.32 q8, , #10 │ │ + @ instruction: 0xfff61edb │ │ vtbl.8 d24, {d23-d26}, d5 │ │ vqshl.u64 , q9, #55 @ 0x37 │ │ vcvt.f16.u16 d16, d6, #10 │ │ movs r2, r2 │ │ │ │ 0011d5c8 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -174438,15 +174438,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ lsls r0, r0, #31 │ │ movs r2, r2 │ │ - lsls r0, r7, #24 │ │ + movs r0, #180 @ 0xb4 │ │ vqshlu.s64 d24, d31, #55 @ 0x37 │ │ vcvtm.s16.f16 d19, d28 │ │ vqshl.u32 d16, d16, #22 │ │ movs r2, r2 │ │ │ │ 0011d9d8 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -174545,15 +174545,15 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r0, [sp, #48] @ 0x30 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ lsls r0, r0, #27 │ │ movs r2, r2 │ │ - ldr r1, [sp, #480] @ 0x1e0 │ │ + cbz r4, 11db5c │ │ vqrdmulh.s , q11, d1[0] │ │ vrshr.u32 d19, d16, #9 │ │ vqshlu.s32 d16, d20, #22 │ │ movs r2, r2 │ │ │ │ 0011daec : │ │ push {r7, lr} │ │ @@ -174854,22 +174854,22 @@ │ │ itt ne │ │ ldrne r0, [sp, #12] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ lsls r2, r2, #18 │ │ movs r2, r2 │ │ str r3, [sp, #732] @ 0x2dc │ │ - vcvtp.u16.f16 , q13 │ │ - vcvt.u32.f32 d18, d12, #10 │ │ - vrintm.f16 q15, q15 │ │ - vqmovn.u32 d31, q3 │ │ - @ instruction: 0xfff62ef8 │ │ + vqrdmulh.s q8, , d22[0] │ │ + vcvt.u32.f32 d18, d12, #9 │ │ + vuzp.16 q8, q13 │ │ + vqrdmulh.s q8, , d2[0] │ │ + @ instruction: 0xfff72ef8 │ │ vzip.16 , │ │ - vcvtm.s16.f16 d31, d16 │ │ - vcvt.u32.f32 q9, q1, #10 │ │ + @ instruction: 0xfff70d9c │ │ + vcvt.u32.f32 q9, q1, #9 │ │ @ instruction: 0xfff6036a │ │ movs r2, r2 │ │ ldr r7, [sp, #1008] @ 0x3f0 │ │ movs r1, r2 │ │ add r0, pc, #56 @ (adr r0, 11de74 ) │ │ movs r1, r2 │ │ ldr r7, [sp, #976] @ 0x3d0 │ │ @@ -175140,25 +175140,25 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ lsls r2, r3, #9 │ │ movs r2, r2 │ │ str r0, [sp, #852] @ 0x354 │ │ - vcvta.s16.f16 d31, d8 │ │ - vcvt.f16.u16 d18, d26, #10 │ │ - vrintn.f16 d30, d12 │ │ - vqrdmlsh.s q15, q11, d20[0] │ │ - vcvt.f16.u16 d18, d6, #10 │ │ + vtbl.8 d16, {d23-d25}, d4 │ │ + vcvt.f16.u16 d18, d26, #9 │ │ + @ instruction: 0xfff6fe88 │ │ + vtbx.8 d16, {d6-d8}, d16 │ │ + vcvt.f16.u16 d18, d6, #9 │ │ vtbl.8 d21, {d22}, d14 │ │ - vqrdmlsh.s q15, q11, d0[0] │ │ - @ instruction: 0xfff62bf2 │ │ + vshll.u32 q8, d28, #22 │ │ + @ instruction: 0xfff72bf2 │ │ @ instruction: 0xfff64fbe │ │ - vshr.u64 , q9, #9 │ │ - @ instruction: 0xfff62d24 │ │ + vtbx.8 d16, {d7-d10}, d30 │ │ + @ instruction: 0xfff72d24 │ │ vtrn.16 d16, d0 │ │ movs r2, r2 │ │ ldr r5, [sp, #408] @ 0x198 │ │ movs r1, r2 │ │ ldr r5, [sp, #480] @ 0x1e0 │ │ movs r1, r2 │ │ ldr r5, [sp, #552] @ 0x228 │ │ @@ -175307,15 +175307,15 @@ │ │ beq.n 11e2de │ │ ldr r0, [sp, #16] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ vqadd.u8 d0, d4, d1 │ │ ldcl 15, cr15, [r6], #988 @ 0x3dc │ │ - ldr r6, [sp, #376] @ 0x178 │ │ + @ instruction: 0xb8da │ │ vtbx.8 d18, {d22-d24}, d14 │ │ @ instruction: 0xfff6fdf4 │ │ movs r1, r2 │ │ mov r0, r1 │ │ cmp r1, #0 │ │ it ne │ │ movne r0, #1 │ │ @@ -175401,15 +175401,15 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldc2 0, cr0, [ip, #68] @ 0x44 │ │ add r7, pc, #984 @ (adr r7, 11e7a0 *)@@Base+0x298>) │ │ vshr.u64 q12, , #9 │ │ vqrshrn.u64 d18, q1, #10 │ │ - @ instruction: 0xfff6a8d6 │ │ + vrsra.u32 q14, q1, #10 │ │ vtrn.16 q12, │ │ vqshrn.u64 d18, q8, #10 │ │ vqrdmulh.s , q3, d30[0] │ │ movs r1, r2 │ │ ldc2l 0, cr0, [r2, #-68] @ 0xffffffbc │ │ │ │ 0011e3e4 : │ │ @@ -175517,17 +175517,17 @@ │ │ ldrb.w r0, [sp, #16] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #24] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ stc2l 0, cr0, [lr], #-68 @ 0xffffffbc │ │ - @ instruction: 0xebb5fff6 │ │ - @ instruction: 0xfb02fff6 │ │ - movs r2, #115 @ 0x73 │ │ + lsls r1, r6, #24 │ │ + vsli.32 , q15, #23 │ │ + vrshr.u32 q9, , #9 │ │ @ instruction: 0xfff7fbfe │ │ movs r1, r2 │ │ │ │ 0011e508 *)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -175845,15 +175845,15 @@ │ │ subs r2, #1 │ │ muls r0, r2 │ │ ldr r2, [r5, #44] @ 0x2c │ │ mul.w ip, r0, r2 │ │ b.n 11e8d4 *)@@Base+0x3cc> │ │ nop │ │ subs r4, #57 @ 0x39 │ │ - vqrdmlah.s q12, , d3[0] │ │ + vqshrn.u64 d26, , #9 │ │ vsra.u64 q9, , #10 │ │ vcvta.s16.f16 , │ │ lsrs r0, r0, #16 │ │ ldr r4, [sp, #12] │ │ ldr.w r0, [sl] │ │ ldrd r2, r1, [r1, #4] │ │ add r4, ip │ │ @@ -176052,24 +176052,24 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r0, [sp, #224] @ 0xe0 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ @ instruction: 0xfb8e0011 │ │ @ instruction: 0xf6bc0011 │ │ ldrb r6, [r7, #6] │ │ - @ instruction: 0xfff789b5 │ │ + vsri.32 d26, d17, #9 │ │ vqdmulh.s , q11, d15[0] │ │ @ instruction: 0xfff74f21 │ │ vqrdmulh.s , q3, d25[0] │ │ @ instruction: 0xfff71cf1 │ │ - vsli.64 d31, d23, #55 @ 0x37 │ │ - @ instruction: 0xfff61d89 │ │ + vshr.u32 d17, d19, #9 │ │ + @ instruction: 0xfff71d89 │ │ vcvt.u16.f16 d17, d1, #9 │ │ vtbx.8 d23, {d7-d9}, d30 │ │ - vshll.u32 q12, d7, #22 │ │ + vsri.64 d26, d3, #10 │ │ vcvt.u16.f16 d17, d17, #10 │ │ Address 0x11eb16 is out of bounds. │ │ │ │ │ │ 0011eb18 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -176196,18 +176196,18 @@ │ │ b.n 11ec54 │ │ add r0, sp, #84 @ 0x54 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ sbcs.w r0, lr, #9502720 @ 0x910000 │ │ bcc.n 11ec76 │ │ - vtbx.8 d27, {d7-d10}, d9 │ │ + vrsqrte.f16 , │ │ vtbl.8 d17, {d6-d9}, d19 │ │ - vrecpe.u16 , │ │ - vtbx.8 d27, {d6-d9}, d25 │ │ + vqrdmlah.s q13, , d27[0] │ │ + vrintz.f16 , │ │ vtbx.8 d17, {d6-d9}, d3 │ │ vrsqrte.u16 , q6 │ │ movs r1, r2 │ │ │ │ 0011ec80 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -176337,18 +176337,18 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #76 @ 0x4c │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ands.w r0, r6, #9502720 @ 0x910000 │ │ bne.n 11ed12 │ │ - vcvtm.s16.f16 d25, d2 │ │ + vcvt.u16.f16 q13, q15, #9 │ │ vtbx.8 d17, {d22-d23}, d1 │ │ vcvtn.u16.f16 d30, d17 │ │ - vcvtm.s16.f16 d25, d18 │ │ + @ instruction: 0xfff7ad9e │ │ vtbx.8 d17, {d22-d23}, d17 │ │ vcvtm.s16.f16 , q13 │ │ movs r1, r2 │ │ │ │ 0011ede0 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -176713,15 +176713,15 @@ │ │ b.n 11f170 │ │ add r0, sp, #156 @ 0x9c │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #212 @ 0xd4 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bics.w r0, r6, #17 │ │ - ldr r3, [sp, #788] @ 0x314 │ │ + @ instruction: 0xb641 │ │ @ instruction: 0xfff61cbd │ │ vrintm.f16 d17, d7 │ │ vcvt.u32.f32 q15, q9, #9 │ │ movs r1, r2 │ │ │ │ 0011f194 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -176879,15 +176879,15 @@ │ │ b.n 11f310 │ │ add r0, sp, #44 @ 0x2c │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #100 @ 0x64 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ mrc 0, 7, r0, cr12, cr1, {0} │ │ - stmia r3!, {r1, r2, r5, r6, r7} │ │ + udf #98 @ 0x62 │ │ vshr.u32 q9, q11, #10 │ │ vrecpe.u16 , │ │ vsri.64 q11, q12, #9 │ │ vshr.u64 d18, d8, #10 │ │ vrsqrte.u16 d17, d5 │ │ vtbx.8 d25, {d7-d8}, d6 │ │ vsra.u32 d18, d12, #9 │ │ @@ -177106,15 +177106,15 @@ │ │ movs r0, r0 │ │ movs r3, r0 │ │ ... │ │ subs r4, #176 @ 0xb0 │ │ ldc 0, cr0, [lr, #-68]! @ 0xffffffbc │ │ sbcs.w r0, ip, r1, lsr #32 │ │ ldrb r2, [r1, #16] │ │ - vrsqrte.f16 q13, │ │ + vcvta.s16.f16 q14, │ │ vsra.u64 , , #10 │ │ Address 0x11f5ba is out of bounds. │ │ │ │ │ │ 0011f5bc : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -177328,24 +177328,24 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #100 @ 0x64 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #156 @ 0x9c │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ @ instruction: 0xead40011 │ │ - ldmia r6!, {r0, r4, r7} │ │ - vqrshrn.u64 d19, , #10 │ │ + stmdb sp, {r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc} │ │ + subs r1, #113 @ 0x71 │ │ vcvtn.s16.f16 d17, d7 │ │ - vrecpe.f16 , q14 │ │ + vqrdmlsh.s q13, , d24[0] │ │ vtbx.8 d19, {d6}, d17 │ │ @ instruction: 0xfff70ff7 │ │ - vtbx.8 d29, {d23-d24}, d28 │ │ + vrecpe.u16 , q12 │ │ vtbx.8 d19, {d22}, d17 │ │ vshr.u32 , , #9 │ │ - vtbx.8 d24, {d7}, d17 │ │ + vrshr.u64 q13, , #9 │ │ vqshrun.s64 d19, , #10 │ │ @ instruction: 0xfff70fd5 │ │ vtbl.8 d30, {d23-d24}, d0 │ │ movs r1, r2 │ │ │ │ 0011f810 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -183562,15 +183562,15 @@ │ │ ldr r0, [sp, #32] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r7, pc, #632 @ (adr r7, 123c50 ) │ │ movs r1, r2 │ │ lsrs r4, r6, #27 │ │ @ instruction: 0xfff71ea9 │ │ - vqshl.u32 d25, d27, #22 │ │ + vsra.u64 d27, d23, #10 │ │ vcvt.f32.f16 q13, d26 │ │ movs r1, r2 │ │ │ │ 001239e8 const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -183650,15 +183650,15 @@ │ │ ldr r0, [sp, #28] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r6, pc, #696 @ (adr r6, 123d84 ) │ │ movs r1, r2 │ │ str r5, [sp, #348] @ 0x15c │ │ @ instruction: 0xfff71dbb │ │ - vcvt.bf16.f32 d25, │ │ + vtrn.16 , │ │ vqshlu.s32 d26, d28, #22 │ │ movs r1, r2 │ │ │ │ 00123adc const&, cv::Mat const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -183738,15 +183738,15 @@ │ │ ldr r0, [sp, #28] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r5, pc, #744 @ (adr r5, 123ea8 ) │ │ movs r1, r2 │ │ str r4, [sp, #396] @ 0x18c │ │ vqdmulh.s , , d7[0] │ │ - vsli.32 , , #22 │ │ + @ instruction: 0xfff6afd5 │ │ vrinta.f16 q13, q4 │ │ movs r1, r2 │ │ │ │ 00123bd0 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -183899,15 +183899,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ add r4, pc, #72 @ (adr r4, 123dc0 const&)@@Base+0x38>) │ │ movs r1, r2 │ │ str r2, [sp, #700] @ 0x2bc │ │ @ instruction: 0xfff71b13 │ │ - vsubw.u , q11, d21 │ │ + @ instruction: 0xfff6ae21 │ │ vrsra.u64 d26, d4, #10 │ │ movs r1, r2 │ │ │ │ 00123d88 const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -184090,15 +184090,15 @@ │ │ ldr r0, [sp, #32] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r1, pc, #968 @ (adr r1, 124354 ) │ │ movs r1, r2 │ │ lsrs r0, r0, #5 │ │ @ instruction: 0xfff718f5 │ │ - vzip.16 d25, d7 │ │ + vdup.16 d26, d3[1] │ │ vsra.u32 q13, q11, #10 │ │ movs r1, r2 │ │ │ │ 00123f9c const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -184187,15 +184187,15 @@ │ │ ldr r0, [sp, #68] @ 0x44 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r0, pc, #1000 @ (adr r0, 124484 const&, cv::MatExpr const&)@@Base+0x3c>) │ │ movs r1, r2 │ │ ldrh r7, [r0, #60] @ 0x3c │ │ vcvt.u16.f16 , │ │ - vshr.u32 , , #10 │ │ + @ instruction: 0xfff6aaf9 │ │ vmla.i q13, q3, d28[0] │ │ movs r1, r2 │ │ │ │ 001240ac const&, cv::Mat const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -184275,15 +184275,15 @@ │ │ ldr r0, [sp, #28] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r7, [sp, #936] @ 0x3a8 │ │ movs r1, r2 │ │ ldrh r3, [r2, #52] @ 0x34 │ │ vqshlu.s64 , , #55 @ 0x37 │ │ - @ instruction: 0xfff68f89 │ │ + vtbl.8 d26, {d6-d8}, d5 │ │ vcvt.u32.f32 , q12, #10 │ │ movs r1, r2 │ │ │ │ 001241a0 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -184370,15 +184370,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldr r6, [sp, #984] @ 0x3d8 │ │ movs r1, r2 │ │ ldrh r3, [r2, #44] @ 0x2c │ │ vsli.64 , , #55 @ 0x37 │ │ - @ instruction: 0xfff68e89 │ │ + vtbl.8 d26, {d6-d7}, d5 │ │ vcvt.f32.u32 , q12, #10 │ │ movs r1, r2 │ │ │ │ 001242a4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -184465,15 +184465,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldr r5, [sp, #968] @ 0x3c8 │ │ movs r1, r2 │ │ ldrh r7, [r1, #36] @ 0x24 │ │ vsri.64 , , #9 │ │ - @ instruction: 0xfff68d85 │ │ + vtbl.8 d26, {d6}, d1 │ │ vcvt.u16.f16 , q10, #10 │ │ movs r1, r2 │ │ │ │ 001243a8 const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -184685,15 +184685,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldr r3, [sp, #576] @ 0x240 │ │ movs r1, r2 │ │ ldrh r1, [r5, #16] │ │ vcvtp.u16.f16 d17, d13 │ │ - @ instruction: 0xfff68b1f │ │ + vsli.64 d26, d11, #54 @ 0x36 │ │ @ instruction: 0xfff69b12 │ │ movs r1, r2 │ │ │ │ 0012460c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -184831,15 +184831,15 @@ │ │ ldr r0, [sp, #36] @ 0x24 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r1, [sp, #1000] @ 0x3e8 │ │ movs r1, r2 │ │ lsls r6, r1, #5 │ │ vcvtn.s16.f16 d17, d3 │ │ - @ instruction: 0xfff68995 │ │ + vsri.32 d26, d1, #10 │ │ vtbl.8 d25, {d22-d23}, d4 │ │ movs r1, r2 │ │ │ │ 00124794 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -184929,15 +184929,15 @@ │ │ ldr r0, [sp, #68] @ 0x44 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r0, [sp, #1000] @ 0x3e8 │ │ movs r1, r2 │ │ strh r7, [r1, #60] @ 0x3c │ │ @ instruction: 0xfff70ff3 │ │ - vtbl.8 d24, {d22}, d5 │ │ + vshll.i16 q13, d1, #16 │ │ vqrshrun.s64 d25, q15, #10 │ │ movs r1, r2 │ │ │ │ 001248a4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -185028,15 +185028,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ str r7, [sp, #928] @ 0x3a0 │ │ movs r1, r2 │ │ strh r5, [r7, #50] @ 0x32 │ │ vqrdmlah.s q8, , d17[0] │ │ - vqshl.u32 q12, , #22 │ │ + vzip.16 q13, │ │ vrint?.f16 , q14 │ │ movs r1, r2 │ │ │ │ 001249b8 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -185189,15 +185189,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ str r6, [sp, #168] @ 0xa8 │ │ movs r1, r2 │ │ strh r7, [r0, #38] @ 0x26 │ │ @ instruction: 0xfff70d2b │ │ - vsli.64 d24, d29, #54 @ 0x36 │ │ + vshr.u32 d26, d25, #10 │ │ vrintz.f16 d25, d28 │ │ movs r1, r2 │ │ │ │ 00124b70 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -185378,15 +185378,15 @@ │ │ ldr r0, [sp, #16] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ str r3, [sp, #1016] @ 0x3f8 │ │ movs r1, r2 │ │ @ instruction: 0xfb64fff6 │ │ lsrs r1, r3, #12 │ │ - vsubw.u q12, q11, d27 │ │ + @ instruction: 0xfff69e27 │ │ vrsra.u64 d25, d10, #10 │ │ movs r1, r2 │ │ │ │ 00124d78 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -185478,15 +185478,15 @@ │ │ ldr r0, [sp, #68] @ 0x44 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ str r3, [sp, #88] @ 0x58 │ │ movs r1, r2 │ │ strh r3, [r4, #12] │ │ vtbl.8 d16, {d7-d9}, d7 │ │ - vrshr.u64 d24, d9, #10 │ │ + vcvt.u16.f16 d25, d5, #10 │ │ vrshr.u64 d25, d2, #10 │ │ movs r1, r2 │ │ │ │ 00124e90 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -185568,15 +185568,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ str r2, [sp, #0] │ │ movs r1, r2 │ │ strh r5, [r5, #4] │ │ vqshrn.u64 d16, , #9 │ │ - vzip.16 d24, d19 │ │ + vcvt.f16.u16 d25, d15, #10 │ │ vsra.u64 d25, d6, #10 │ │ movs r1, r2 │ │ │ │ 00124f88 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ @@ -185736,15 +185736,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ str r0, [sp, #296] @ 0x128 │ │ movs r1, r2 │ │ ldrb r3, [r3, #27] │ │ vqshl.u32 d16, d31, #23 │ │ - @ instruction: 0xfff67fd1 │ │ + vtbx.8 d25, {d6-d8}, d13 │ │ vqrdmlsh.s q12, q11, d0[0] │ │ movs r1, r2 │ │ │ │ 0012515c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -185930,15 +185930,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrh r6, [r6, #46] @ 0x2e │ │ movs r1, r2 │ │ bl ffe8c358 <__cxa_new_handler@@Base+0xffc48768> │ │ lsls r3, r3, #20 │ │ - @ instruction: 0xfff67dad │ │ + vtbl.8 d25, {d6}, d25 │ │ @ instruction: 0xfff68d9c │ │ movs r1, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ sub sp, #288 @ 0x120 │ │ mov r5, r0 │ │ @@ -186112,15 +186112,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrh r6, [r7, #30] │ │ movs r1, r2 │ │ ldrb r3, [r7, #10] │ │ vrsra.u32 d16, d15, #9 │ │ - @ instruction: 0xfff67bb1 │ │ + vcvt.f16.f32 d25, │ │ vtbl.8 d24, {d22-d25}, d20 │ │ movs r1, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ sub sp, #344 @ 0x158 │ │ mov r5, r0 │ │ @@ -186298,15 +186298,15 @@ │ │ ldr r0, [sp, #16] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldrh r4, [r5, #14] │ │ movs r1, r2 │ │ ldrb r1, [r5, #2] │ │ vcvtn.s16.f16 d16, d13 │ │ - @ instruction: 0xfff6799f │ │ + vsri.32 d25, d11, #10 │ │ @ instruction: 0xfff68992 │ │ movs r1, r2 │ │ │ │ 00125784 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -186379,15 +186379,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrh r2, [r2, #8] │ │ movs r1, r2 │ │ bl 1a883c , cv::_OutputArray const&)@@Base+0x454> │ │ movs r7, r6 │ │ - vtbx.8 d23, {d22}, d9 │ │ + @ instruction: 0xfff69345 │ │ @ instruction: 0xfff688b8 │ │ movs r1, r2 │ │ │ │ 0012585c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -186461,15 +186461,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrh r6, [r6, #0] │ │ movs r1, r2 │ │ strb r3, [r6, #27] │ │ vcvt.u32.f32 , , #9 │ │ - vneg.f16 , │ │ + vclt.s16 , , #0 │ │ vqshl.u64 q12, q6, #54 @ 0x36 │ │ movs r1, r2 │ │ │ │ 0012593c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -186542,15 +186542,15 @@ │ │ ldr r0, [sp, #16] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strh r4, [r2, #58] @ 0x3a │ │ movs r1, r2 │ │ strb r1, [r2, #24] │ │ vcvt.f32.u32 , , #9 │ │ - vabs.f16 d23, d7 │ │ + vcle.s16 d25, d3, #0 │ │ vqshlu.s64 q12, q13, #54 @ 0x36 │ │ movs r1, r2 │ │ │ │ 00125a1c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -186623,15 +186623,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strh r2, [r7, #50] @ 0x32 │ │ movs r1, r2 │ │ stcl 15, cr15, [sl, #984]! @ 0x3d8 │ │ ldc2 15, cr15, [pc, #980] @ 125ec0 │ │ - strb r1, [r6, #24] │ │ + str r0, [sp, #692] @ 0x2b4 │ │ vcvt.f16.f32 d24, q8 │ │ movs r1, r2 │ │ │ │ 00125af4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -186705,15 +186705,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strh r6, [r3, #44] @ 0x2c │ │ movs r1, r2 │ │ strb r3, [r3, #17] │ │ @ instruction: 0xfff7fcbf │ │ - vsli.32 , , #21 │ │ + vqrdmlsh.s q12, , d13[0] │ │ vrinta.f16 q12, q2 │ │ movs r1, r2 │ │ │ │ 00125bd4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -186786,15 +186786,15 @@ │ │ ldr r0, [sp, #16] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strh r4, [r7, #36] @ 0x24 │ │ movs r1, r2 │ │ strb r1, [r7, #13] │ │ @ instruction: 0xfff7fbdd │ │ - vcgt.f16 , , #0 │ │ + vqrdmlah.s q12, , d27[0] │ │ vrintn.f16 q12, q9 │ │ movs r1, r2 │ │ │ │ 00125cb4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -186867,15 +186867,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strh r2, [r4, #30] │ │ movs r1, r2 │ │ @ instruction: 0xeb52fff6 │ │ @ instruction: 0xfb07fff5 │ │ - strb r1, [r3, #14] │ │ + ldrh r5, [r2, #48] @ 0x30 │ │ vsubw.u q12, q11, d8 │ │ movs r1, r2 │ │ │ │ 00125d8c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -186949,15 +186949,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strh r6, [r0, #24] │ │ movs r1, r2 │ │ strb r3, [r0, #7] │ │ vtbl.8 d31, {d7-d9}, d23 │ │ - vrshr.u64 d23, d25, #11 │ │ + vcvt.u16.f16 d24, d21, #11 │ │ vqmovn.s32 d24, q14 │ │ movs r1, r2 │ │ │ │ 00125e6c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -187030,15 +187030,15 @@ │ │ ldr r0, [sp, #16] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strh r4, [r4, #16] │ │ movs r1, r2 │ │ strb r1, [r4, #3] │ │ vtbx.8 d31, {d7-d8}, d5 │ │ - vsra.u64 , , #11 │ │ + vcvt.f16.u16 q12, , #11 │ │ vzip.16 q12, q5 │ │ movs r1, r2 │ │ │ │ 00125f4c =(cv::Mat const&, cv::Mat const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -187111,15 +187111,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strh r2, [r1, #10] │ │ movs r1, r2 │ │ ldmia.w sl!, {r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc} │ │ str??.w pc, [pc, #-4085] @ 125027 │ │ - strb r1, [r0, #4] │ │ + ldrh r5, [r7, #26] │ │ vshr.u64 q12, q8, #10 │ │ movs r1, r2 │ │ │ │ 00126024 =(cv::Mat const&, double)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -187193,15 +187193,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strh r6, [r5, #2] │ │ movs r1, r2 │ │ ldr r3, [r5, #112] @ 0x70 │ │ vcvt.u16.f16 d31, d15 │ │ - vcgt.s16 d23, d17, #0 │ │ + @ instruction: 0xfff58a9d │ │ vshr.u32 d24, d4, #10 │ │ movs r1, r2 │ │ │ │ 00126104 =(double, cv::Mat const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -187274,15 +187274,15 @@ │ │ ldr r0, [sp, #16] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldrb r4, [r1, #30] │ │ movs r1, r2 │ │ ldr r1, [r1, #100] @ 0x64 │ │ vcvt.f16.u16 d31, d29 │ │ - vcvt.u32.f32 d22, d31, #11 │ │ + @ instruction: 0xfff589bb │ │ vcvt.u32.f32 d23, d18, #10 │ │ movs r1, r2 │ │ │ │ 001261e4 (cv::Mat const&, cv::Mat const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -187355,15 +187355,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrb r2, [r6, #26] │ │ movs r1, r2 │ │ b.n 125ef4 │ │ vsli.64 , , #54 @ 0x36 │ │ - vqrdmlah.s q11, , d25[0] │ │ + vtbx.8 d24, {d21}, d21 │ │ vcvt.f32.u32 , q4, #10 │ │ movs r1, r2 │ │ │ │ 001262bc (cv::Mat const&, double)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -187437,15 +187437,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrb r6, [r2, #23] │ │ movs r1, r2 │ │ ldr r3, [r2, #72] @ 0x48 │ │ vsri.64 , , #9 │ │ - @ instruction: 0xfff56d89 │ │ + vtbl.8 d24, {d5}, d5 │ │ vcvt.u16.f16 , q14, #10 │ │ movs r1, r2 │ │ │ │ 0012639c (double, cv::Mat const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -187518,15 +187518,15 @@ │ │ ldr r0, [sp, #16] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldrb r4, [r6, #19] │ │ movs r1, r2 │ │ ldr r1, [r6, #56] @ 0x38 │ │ vsri.32 d31, d5, #9 │ │ - vmull.u q11, d21, d23 │ │ + vabs.f16 d24, d19 │ │ @ instruction: 0xfff67c9a │ │ movs r1, r2 │ │ │ │ 0012647c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -187614,15 +187614,15 @@ │ │ nop │ │ adds r6, r3, #0 │ │ movs r1, r2 │ │ ldrb r6, [r2, #16] │ │ movs r1, r2 │ │ b.n 126c4c │ │ vshll.i16 , d19, #16 │ │ - @ instruction: 0xfff56bb5 │ │ + vqshlu.s32 d24, d17, #21 │ │ vtbl.8 d23, {d22-d25}, d18 │ │ movs r1, r2 │ │ │ │ 0012657c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -187713,15 +187713,15 @@ │ │ nop │ │ subs r6, r5, r4 │ │ movs r1, r2 │ │ ldrb r2, [r2, #12] │ │ movs r1, r2 │ │ ldr r3, [r6, #24] │ │ vrshr.u32 d31, d7, #9 │ │ - vtbl.8 d22, {d21-d23}, d25 │ │ + vceq.f16 d24, d21, #0 │ │ @ instruction: 0xfff67a9a │ │ movs r1, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ sub sp, #344 @ 0x158 │ │ mov r5, r0 │ │ @@ -187916,15 +187916,15 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ adds r6, r1, r4 │ │ movs r1, r2 │ │ ldrb r6, [r3, #3] │ │ movs r1, r2 │ │ str r5, [r7, #116] @ 0x74 │ │ vqrdmlsh.s q15, , d17[0] │ │ - vqrshrun.s64 d22, , #11 │ │ + vmlal.u q12, d21, d31[0] │ │ vtbx.8 d23, {d6}, d20 │ │ movs r1, r2 │ │ │ │ 001268bc : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -188012,15 +188012,15 @@ │ │ nop │ │ adds r2, r3, r0 │ │ movs r1, r2 │ │ strb r6, [r2, #31] │ │ movs r1, r2 │ │ svc 46 @ 0x2e │ │ vqrdmlah.s q15, q11, d19[0] │ │ - vqshl.u32 q11, , #21 │ │ + vsra.u64 q12, , #11 │ │ vrint?.f16 , q9 │ │ movs r1, r2 │ │ │ │ 001269bc : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -188111,15 +188111,15 @@ │ │ nop │ │ asrs r2, r5, #28 │ │ movs r1, r2 │ │ strb r2, [r2, #27] │ │ movs r1, r2 │ │ str r3, [r6, #84] @ 0x54 │ │ @ instruction: 0xfff7edd7 │ │ - vclt.f16 q11, , #0 │ │ + vcge.s16 q12, , #0 │ │ vqshlu.s32 , q5, #22 │ │ movs r1, r2 │ │ │ │ 00126ac8 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -188209,15 +188209,15 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ asrs r2, r6, #24 │ │ movs r1, r2 │ │ strb r6, [r0, #23] │ │ movs r1, r2 │ │ str r5, [r4, #68] @ 0x44 │ │ vqdmulh.s q15, , d9[0] │ │ - vsli.32 q11, , #21 │ │ + @ instruction: 0xfff57fd7 │ │ vrinta.f16 , q6 │ │ movs r1, r2 │ │ │ │ 00126bd4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -188292,15 +188292,15 @@ │ │ ldr r0, [sp, #16] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strb r2, [r0, #19] │ │ movs r1, r2 │ │ bgt.n 126cf8 const&)@@Base+0x44> │ │ @ instruction: 0xfff6ebdd │ │ - vcgt.f16 q11, , #0 │ │ + vqrdmlah.s , , d27[0] │ │ vsri.32 , q7, #10 │ │ movs r1, r2 │ │ │ │ 00126cb4 const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -188370,15 +188370,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strb r2, [r4, #15] │ │ movs r1, r2 │ │ str r3, [r5, #40] @ 0x28 │ │ vtbl.8 d30, {d7-d10}, d15 │ │ - vneg.s16 d22, d17 │ │ + vcvt.f32.u32 d23, d13, #11 │ │ vrsra.u64 d23, d0, #10 │ │ movs r1, r2 │ │ │ │ 00126d84 const&, cv::Mat const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -188448,15 +188448,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strb r2, [r2, #12] │ │ movs r1, r2 │ │ str r3, [r3, #28] │ │ vshll.u32 q15, d31, #23 │ │ - vrshr.u64 q11, , #11 │ │ + vqrdmulh.s , , d13[0] │ │ vqmovn.u32 d23, q0 │ │ movs r1, r2 │ │ │ │ 00126e54 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -188531,15 +188531,15 @@ │ │ ldr r0, [sp, #16] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strb r2, [r0, #9] │ │ movs r1, r2 │ │ bls.n 126e78 │ │ vqrshrn.u64 d30, , #10 │ │ - vcle.s16 q11, , #0 │ │ + vdup.8 , d27[2] │ │ vsra.u64 , q7, #10 │ │ movs r1, r2 │ │ │ │ 00126f34 const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -188609,15 +188609,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strb r2, [r4, #5] │ │ movs r1, r2 │ │ str r3, [r5, #0] │ │ vtbl.8 d30, {d23}, d15 │ │ - vceq.i16 d22, d17, #0 │ │ + @ instruction: 0xfff57b9d │ │ vsra.u32 d23, d0, #10 │ │ movs r1, r2 │ │ │ │ 00127004 const&, cv::Mat const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -188687,15 +188687,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ strb r2, [r2, #2] │ │ movs r1, r2 │ │ ldrsh r3, [r3, r5] │ │ vqshl.u64 d30, d31, #55 @ 0x37 │ │ - vshr.u32 q11, , #11 │ │ + vtbx.8 d23, {d21-d23}, d13 │ │ vmla.i , q3, d0[0] │ │ movs r1, r2 │ │ │ │ 001270d4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -188770,15 +188770,15 @@ │ │ ldr r0, [sp, #16] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r2, [r0, #124] @ 0x7c │ │ movs r1, r2 │ │ bvc.n 1271f8 const&)@@Base+0x44> │ │ vqshlu.s64 q15, , #54 @ 0x36 │ │ - vqrdmlsh.s , , d31[0] │ │ + vtbx.8 d23, {d21-d22}, d27 │ │ vcvt.u32.f32 q11, q7, #10 │ │ movs r1, r2 │ │ │ │ 001271b4 const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -188848,15 +188848,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldr r2, [r4, #108] @ 0x6c │ │ movs r1, r2 │ │ ldrb r3, [r5, r6] │ │ vcvt.f16.s16 d30, d15 │ │ - @ instruction: 0xfff55ea1 │ │ + vqshrn.u64 d23, , #11 │ │ @ instruction: 0xfff66e90 │ │ movs r1, r2 │ │ │ │ 00127284 const&, cv::Mat const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -188926,15 +188926,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldr r2, [r2, #96] @ 0x60 │ │ movs r1, r2 │ │ ldrb r3, [r3, r3] │ │ vsli.32 d30, d31, #23 │ │ - @ instruction: 0xfff55dd1 │ │ + vtbx.8 d23, {d5}, d13 │ │ vqrdmulh.s q11, q11, d0[0] │ │ movs r1, r2 │ │ │ │ 00127354 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #48 @ 0x30 │ │ @@ -189004,15 +189004,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldr r0, [r1, #84] @ 0x54 │ │ movs r1, r2 │ │ ldrb r3, [r1, r0] │ │ vrecpe.u16 q15, │ │ - @ instruction: 0xfff55d01 │ │ + vqshl.u32 , , #21 │ │ vqdmulh.s q11, q11, d28[0] │ │ movs r1, r2 │ │ │ │ 00127424 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #56 @ 0x38 │ │ @@ -189093,15 +189093,15 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ lsrs r2, r6, #19 │ │ movs r1, r2 │ │ ldr r4, [r6, #68] @ 0x44 │ │ movs r1, r2 │ │ ldrh r1, [r5, r4] │ │ vcvtm.u16.f16 d30, d13 │ │ - vcvt.f16.u16 d21, d15, #11 │ │ + vqshlu.s64 d23, d11, #53 @ 0x35 │ │ vdup.16 d22, d8[1] │ │ movs r1, r2 │ │ │ │ 00127510 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #16 │ │ @@ -189428,15 +189428,15 @@ │ │ nop │ │ ldr r4, [r7, #16] │ │ movs r1, r2 │ │ ldr r4, [r3, #16] │ │ movs r1, r2 │ │ b.n 1278a0 │ │ vtbl.8 d31, {d21-d22}, d28 │ │ - @ instruction: 0xfff658df │ │ + vrsra.u32 , , #10 │ │ vtbx.8 d22, {d22}, d10 │ │ movs r1, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #300 @ 0x12c │ │ ldr.w r0, [pc, #1888] @ 127fac │ │ @@ -189904,15 +189904,15 @@ │ │ str r6, [r2, #108] @ 0x6c │ │ movs r1, r2 │ │ str r6, [r2, #108] @ 0x6c │ │ movs r1, r2 │ │ push {r0, r2, r3, r4, r6, lr} │ │ vqshlu.s32 q11, q10, #22 │ │ movs r1, r2 │ │ - ldrsb r5, [r5, r0] │ │ + strb r1, [r5, #2] │ │ vqshlu.s64 , q11, #54 @ 0x36 │ │ vrintz.f16 q11, q14 │ │ movs r1, r2 │ │ ldr r3, [sp, #544] @ 0x220 │ │ movs r1, r2 │ │ add.w sl, r5, #16777216 @ 0x1000000 │ │ movs r4, #0 │ │ @@ -190088,15 +190088,15 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r4, [r2, #4] │ │ movs r1, r2 │ │ str r0, [r7, #20] │ │ movs r1, r2 │ │ cbz r5, 128020 │ │ - vsri.32 , , #10 │ │ + @ instruction: 0xfff66ef3 │ │ vrinta.f16 , q0 │ │ vsra.u32 q11, q10, #10 │ │ movs r1, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ mov r4, r0 │ │ @@ -191095,15 +191095,15 @@ │ │ add r0, sp, #68 @ 0x44 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldrh r4, [r3, r1] │ │ movs r1, r2 │ │ ldrb r3, [r6, #24] │ │ vtbl.8 d30, {d6}, d10 │ │ - vqshl.u32 d20, d29, #22 │ │ + vsra.u64 d22, d25, #10 │ │ vsli.64 , q14, #54 @ 0x36 │ │ movs r1, r2 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ vpush {d8} │ │ sub sp, #16 │ │ @@ -192666,15 +192666,15 @@ │ │ nop │ │ cmp sl, r1 │ │ movs r1, r2 │ │ add lr, sl │ │ movs r1, r2 │ │ strh r4, [r2, #48] @ 0x30 │ │ vsli.64 d29, d20, #54 @ 0x36 │ │ - vrintx.f16 , │ │ + vqrdmlsh.s q10, q3, d19[0] │ │ vsli.64 , q8, #54 @ 0x36 │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #16 │ │ mov r4, r1 │ │ ldr r1, [pc, #180] @ (129cf8 ) │ │ ldr r0, [pc, #184] @ (129cfc ) │ │ @@ -192820,15 +192820,15 @@ │ │ nop │ │ b.n 1298cc │ │ movs r0, r2 │ │ bics r4, r2 │ │ movs r1, r2 │ │ adds r2, #79 @ 0x4f │ │ @ instruction: 0xfff7bab3 │ │ - vabs.s16 , │ │ + vqrdmulh.s q10, , d1[0] │ │ vshll.i16 q10, d30, #16 │ │ movs r1, r2 │ │ │ │ 00129dec : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -193958,17 +193958,17 @@ │ │ add r0, sp, #236 @ 0xec │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldrb r6, [r1, r5] │ │ movs r1, r2 │ │ adds r7, #212 @ 0xd4 │ │ movs r1, r2 │ │ - b.n 12b12c │ │ - vneg.s16 , q6 │ │ - vcvt.f32.f16 q9, d13 │ │ + mcr2 15, 0, pc, cr6, cr5, {7} @ │ │ + bcc.n 12a9b4 │ │ + vzip.16 d20, d9 │ │ vqshlu.s64 , q15, #54 @ 0x36 │ │ movs r1, r2 │ │ b.w 2300a8 <__emutls_get_address@@Base+0x3220> │ │ movs r0, #1 │ │ bx lr │ │ b.w 2300a8 <__emutls_get_address@@Base+0x3220> │ │ movs r0, #1 │ │ @@ -194401,30 +194401,30 @@ │ │ ldr r0, [sp, #24] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ adds r5, #194 @ 0xc2 │ │ movs r1, r2 │ │ ldrh r1, [r6, #52] @ 0x34 │ │ vcvt.u32.f32 q14, q6, #10 │ │ - vrshr.u64 d29, d6, #10 │ │ - vabs.s16 q9, │ │ + vcvt.u16.f16 d30, d2, #10 │ │ + @ instruction: 0xfff53dbf │ │ vcvt.u32.f32 d28, d26, #10 │ │ - vrshr.u32 , q10, #10 │ │ + @ instruction: 0xfff6ecf0 │ │ vdup.8 d24, d1[2] │ │ vqrdmlsh.s q14, , d20[0] │ │ - vrsra.u32 d29, d14, #10 │ │ + @ instruction: 0xfff6ed9a │ │ vrsra.u64 q14, , #11 │ │ @ instruction: 0xfff6cfa0 │ │ - vrshr.u64 , q5, #10 │ │ + vcvt.u16.f16 q15, q3, #10 │ │ vclt.s16 d17, d27, #0 │ │ vcvt.u32.f32 q14, q15, #9 │ │ - vrshr.u64 d29, d24, #10 │ │ + vcvt.u16.f16 d30, d20, #10 │ │ @ instruction: 0xfff58bdf │ │ vqrdmlsh.s q14, , d2[0] │ │ - vrshr.u64 , q14, #10 │ │ + vcvt.u16.f16 q15, q12, #10 │ │ vabs.s16 d19, d8 │ │ movs r1, r2 │ │ │ │ 0012aefc : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #8 │ │ @@ -194695,16 +194695,16 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ cmp r7, #162 @ 0xa2 │ │ movs r1, r2 │ │ ldrh r6, [r3, #2] │ │ - vshr.u32 d18, d31, #11 │ │ - vqrdmlsh.s q14, q3, d28[0] │ │ + @ instruction: 0xfff53abb │ │ + vtbx.8 d30, {d22-d23}, d24 │ │ vcvt.u32.f32 q9, q3, #11 │ │ movs r1, r2 │ │ │ │ 0012b1b0 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ @@ -195253,15 +195253,15 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bcs.n 12b77c │ │ movs r0, r2 │ │ cmp r2, #206 @ 0xce │ │ movs r1, r2 │ │ b.n 12bb6a │ │ vdup.16 d31, d10[1] │ │ - vaddl.u q8, d6, d27 │ │ + vtbl.8 d17, {d22-d24}, d23 │ │ vtbx.8 d18, {d22-d23}, d14 │ │ movs r1, r2 │ │ │ │ 0012b75c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -195561,18 +195561,18 @@ │ │ add r0, sp, #32 │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldmia r7!, {r1, r3, r4, r5} │ │ movs r0, r2 │ │ movs r7, #178 @ 0xb2 │ │ movs r1, r2 │ │ - b.n 12bda0 const&)@@Base+0x1a8> │ │ - vtbl.8 d27, {d21-d23}, d14 │ │ - vcvt.u16.f16 d31, d3, #11 │ │ - vqshlu.s64 d18, d22, #53 @ 0x35 │ │ + ldc2 15, cr15, [r8], {245} @ 0xf5 │ │ + bpl.n 12ba80 │ │ + vneg.f16 d17, d15 │ │ + vqshlu.s64 d18, d22, #54 @ 0x36 │ │ movs r1, r2 │ │ │ │ 0012ba74 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #128 @ 0x80 │ │ @@ -195917,18 +195917,18 @@ │ │ movs r0, r0 │ │ movs r1, r0 │ │ movs r0, r0 │ │ ldmia r4, {r3, r4, r6} │ │ movs r0, r2 │ │ movs r4, #150 @ 0x96 │ │ movs r1, r2 │ │ - movs r3, #57 @ 0x39 │ │ + subs r5, #181 @ 0xb5 │ │ vtbl.8 d29, {d22-d25}, d30 │ │ - vtbl.8 d31, {d22-d23}, d7 │ │ - vrsra.u32 d18, d18, #11 │ │ + vrintn.f16 d17, d3 │ │ + vrsra.u32 d18, d18, #10 │ │ movs r1, r2 │ │ │ │ 0012be08 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #64 @ 0x40 │ │ mov r5, r0 │ │ @@ -196172,18 +196172,18 @@ │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldmia r1, {r1, r2, r3, r5, r6} │ │ movs r0, r2 │ │ movs r1, #152 @ 0x98 │ │ movs r1, r2 │ │ - asrs r5, r3, #1 │ │ - vrintx.f16 d27, d4 │ │ - vabs.f16 d31, d1 │ │ - vcge.s16 d18, d20, #0 │ │ + cmp r2, #217 @ 0xd9 │ │ + @ instruction: 0xfff6cf00 │ │ + vsra.u32 , , #11 │ │ + vtrn.16 d18, d20 │ │ movs r1, r2 │ │ │ │ 0012c084 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #108 @ 0x6c │ │ @@ -196314,17 +196314,17 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ stmia r7!, {r1, r3, r4, r5, r6, r7} │ │ movs r0, r2 │ │ movs r0, #16 │ │ movs r1, r2 │ │ str r4, [sp, #980] @ 0x3d4 │ │ - vaddl.u , d6, d27 │ │ - vsli.64 d31, d9, #54 @ 0x36 │ │ - vqrdmlsh.s , , d6[0] │ │ + vtbl.8 d18, {d22-d24}, d23 │ │ + vshr.u32 d17, d5, #10 │ │ + vqrdmlsh.s , q3, d6[0] │ │ movs r1, r2 │ │ │ │ 0012c1e4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #80 @ 0x50 │ │ @@ -196508,17 +196508,17 @@ │ │ add r0, sp, #20 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ subs r2, r6, #2 │ │ movs r1, r2 │ │ bvc.n 12c404 │ │ - vcvt.u32.f32 d27, d23, #10 │ │ - vcge.f16 , , #0 │ │ - @ instruction: 0xfff51cfc │ │ + @ instruction: 0xfff6d9b3 │ │ + vqrdmlsh.s q8, , d3[0] │ │ + @ instruction: 0xfff61cfc │ │ movs r1, r2 │ │ │ │ 0012c404 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #268 @ 0x10c │ │ @@ -197216,27 +197216,27 @@ │ │ add r0, sp, #216 @ 0xd8 │ │ blx 230a40 <__emutls_get_address@@Base+0x3bb8> │ │ add r0, sp, #40 @ 0x28 │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrsh r1, [r5, r7] │ │ - @ instruction: 0xfff5dfd5 │ │ - @ instruction: 0xfff5ef0d │ │ - vcge.s16 d18, d13, #0 │ │ + @ instruction: 0xfff5fa51 │ │ + vtbl.8 d16, {d21-d22}, d9 │ │ + vtrn.16 d18, d13 │ │ movs r0, r0 │ │ adds r2, r1, #2 │ │ movs r1, r2 │ │ ldrh r3, [r1, #6] │ │ - vqrdmulh.s , q11, d25[0] │ │ - @ instruction: 0xfff5ed21 │ │ - vqrdmlsh.s q14, , d4[0] │ │ - vqrdmulh.s , q11, d7[0] │ │ - @ instruction: 0xfff5ecff │ │ - vrsra.u32 d16, d25, #11 │ │ + vtbx.8 d31, {d6}, d21 │ │ + vqshl.u64 d16, d13, #53 @ 0x35 │ │ + vqrdmlsh.s q14, q11, d4[0] │ │ + vtbx.8 d31, {d6}, d3 │ │ + vqshl.u32 q8, , #21 │ │ + vrsra.u32 d16, d25, #10 │ │ movs r0, r0 │ │ asrs r4, r0, #27 │ │ movs r1, r2 │ │ lsls r5, r2, #16 │ │ movs r0, r0 │ │ lsls r5, r4, #19 │ │ movs r0, r0 │ │ @@ -201595,19 +201595,19 @@ │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ str r1, [sp, #632] @ 0x278 │ │ movs r0, r2 │ │ @ instruction: 0xe98a0010 │ │ str r3, [r1, r3] │ │ - vaddl.u , d6, d4 │ │ - vcvt.u32.f32 d27, d21, #11 │ │ + vtbl.8 d28, {d22-d24}, d0 │ │ + @ instruction: 0xfff5d9b1 │ │ vdup.8 q10, d29[2] │ │ - vqrdmlsh.s q13, q11, d18[0] │ │ - vcvt.u32.f32 d27, d3, #11 │ │ + @ instruction: 0xfff6ca5e │ │ + vtbl.8 d29, {d21-d22}, d15 │ │ vceq.i16 d25, d20, #0 │ │ movs r0, r2 │ │ @ instruction: 0xe8d80010 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ subw sp, sp, #1068 @ 0x42c │ │ @@ -203442,19 +203442,19 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrb r6, [r6, #30] │ │ movs r0, r2 │ │ bvc.n 130bc0 │ │ movs r0, r2 │ │ subs r6, #113 @ 0x71 │ │ - @ instruction: 0xfff6bb12 │ │ - @ instruction: 0xfff5acdb │ │ + vrintz.f16 d29, d14 │ │ + vqshl.u32 q14, , #21 │ │ vshll.u32 , d3, #21 │ │ - @ instruction: 0xfff6baf0 │ │ - @ instruction: 0xfff5acb9 │ │ + vrinta.f16 , q14 │ │ + vqshl.u32 d28, d21, #21 │ │ @ instruction: 0xfff57efe │ │ movs r0, r2 │ │ bvs.n 130c00 │ │ movs r0, r2 │ │ bmi.n 130ab0 │ │ bmi.n 130ab2 │ │ bmi.n 130ab4 │ │ @@ -203861,16 +203861,16 @@ │ │ movs r2, r0 │ │ movs r0, r0 │ │ movs r3, r0 │ │ movs r0, r0 │ │ bpl.n 130e24 │ │ movs r0, r2 │ │ subs r3, #32 │ │ - vqrdmulh.s q12, , d3[0] │ │ - vqrshrun.s64 d26, , #11 │ │ + vqshl.u64 d26, d31, #53 @ 0x35 │ │ + vrshr.u64 q14, , #11 │ │ vclt.s16 , q12, #0 │ │ movs r0, r2 │ │ bmi.n 130ee0 │ │ bmi.n 130ee2 │ │ bmi.n 130ee4 │ │ bmi.n 130ee6 │ │ bmi.n 130ee8 │ │ @@ -204275,16 +204275,16 @@ │ │ movs r2, r0 │ │ movs r0, r0 │ │ movs r3, r0 │ │ movs r0, r0 │ │ bne.n 1313f4 │ │ movs r0, r2 │ │ adds r6, #240 @ 0xf0 │ │ - vqshrn.u64 d24, , #11 │ │ - vcgt.f16 q13, , #0 │ │ + vneg.s16 d26, d15 │ │ + vqrdmlah.s , , d1[0] │ │ vcvt.f32.u32 d28, d24, #11 │ │ movs r0, r2 │ │ bmi.n 131310 │ │ bmi.n 131312 │ │ bmi.n 131314 │ │ bmi.n 131316 │ │ bmi.n 131318 │ │ @@ -204691,16 +204691,16 @@ │ │ movs r2, r0 │ │ movs r0, r0 │ │ movs r3, r0 │ │ movs r0, r0 │ │ ldmia r5, {r5} │ │ movs r0, r2 │ │ adds r2, #124 @ 0x7c │ │ - vsri.64 d24, d15, #11 │ │ - @ instruction: 0xfff59fd1 │ │ + vcvt.u32.f32 d25, d11, #11 │ │ + vtbx.8 d27, {d5-d7}, d13 │ │ @ instruction: 0xfff5c9d0 │ │ movs r0, r2 │ │ bmi.n 131780 │ │ bmi.n 131782 │ │ bmi.n 131784 │ │ bmi.n 131786 │ │ bmi.n 131788 │ │ @@ -205107,16 +205107,16 @@ │ │ movs r2, r0 │ │ movs r0, r0 │ │ movs r3, r0 │ │ movs r0, r0 │ │ ldmia r0!, {r4, r5, r7} │ │ movs r0, r2 │ │ cmp r6, #12 │ │ - vcgt.s16 d24, d31, #0 │ │ - vtbx.8 d25, {d5-d8}, d17 │ │ + vtbl.8 d25, {d21-d23}, d27 │ │ + vsli.64 , , #53 @ 0x35 │ │ vceq.f16 q14, q8, #0 │ │ movs r0, r2 │ │ bmi.n 131bf0 │ │ bmi.n 131bf2 │ │ bmi.n 131bf4 │ │ bmi.n 131bf6 │ │ bmi.n 131bf8 │ │ @@ -205505,16 +205505,16 @@ │ │ movs r2, r0 │ │ movs r0, r0 │ │ movs r3, r0 │ │ movs r0, r0 │ │ stmia r4!, {r2, r3, r4, r5} │ │ movs r0, r2 │ │ cmp r1, #216 @ 0xd8 │ │ - @ instruction: 0xfff57bfb │ │ - vabs.f16 d25, d29 │ │ + vqshlu.s32 , , #21 │ │ + vcle.s16 d27, d25, #0 │ │ vceq.i16 d28, d16, #0 │ │ movs r0, r2 │ │ bmi.n 132020 │ │ bmi.n 132022 │ │ bmi.n 132024 │ │ bmi.n 132026 │ │ bmi.n 132028 │ │ @@ -205869,16 +205869,16 @@ │ │ movs r2, r0 │ │ movs r0, r0 │ │ movs r3, r0 │ │ movs r0, r0 │ │ stmia r0!, {r2, r3} │ │ movs r0, r2 │ │ movs r6, #2 │ │ - vtbl.8 d23, {d5}, d21 │ │ - vrsra.u32 , , #11 │ │ + vsubl.u , d21, d17 │ │ + @ instruction: 0xfff5add3 │ │ vcvt.u16.f16 , q1, #11 │ │ movs r0, r2 │ │ bmi.n 132400 │ │ bmi.n 132402 │ │ bmi.n 132404 │ │ bmi.n 132406 │ │ bmi.n 132408 │ │ @@ -206243,16 +206243,16 @@ │ │ movs r2, r0 │ │ movs r0, r0 │ │ movs r3, r0 │ │ movs r0, r0 │ │ pop {r4, r5} │ │ movs r0, r2 │ │ movs r2, #12 │ │ - vcgt.f16 d23, d31, #0 │ │ - vqrdmlsh.s q12, , d17[0] │ │ + @ instruction: 0xfff58eab │ │ + @ instruction: 0xfff5a9dd │ │ vqrshrn.u64 d27, q7, #11 │ │ movs r0, r2 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ ldr r1, [pc, #44] @ (132878 ) │ │ mov r4, r0 │ │ ldr r0, [r0, #20] │ │ @@ -228960,20 +228960,20 @@ │ │ lsls r0, r0, #31 │ │ beq.n 141d14 │ │ ldr r0, [sp, #16] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ stmia r5!, {r5} │ │ movs r7, r1 │ │ - ldr r3, [sp, #148] @ 0x94 │ │ + push {r0, r5, r7, lr} │ │ vshr.u32 d27, d22, #12 │ │ - vcvt.u32.f32 d23, d22, #11 │ │ - vtbl.8 d21, {d4}, d10 │ │ + @ instruction: 0xfff599b2 │ │ + vpaddl.u16 d23, d6 │ │ vshr.u32 d27, d2, #12 │ │ - vcvt.u32.f32 d23, d2, #11 │ │ + vtbl.8 d25, {d21-d22}, d14 │ │ vcls.s16 d28, d14 │ │ movs r7, r1 │ │ stmia r4!, {r3, r6} │ │ movs r7, r1 │ │ │ │ 00141d3c : │ │ ldrd r2, r1, [r1] │ │ @@ -229509,27 +229509,27 @@ │ │ bne.n 142272 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r0, [sp, #40] @ 0x28 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ stmia r0!, {r3, r5, r7} │ │ movs r7, r1 │ │ - ldrb r5, [r0, #10] │ │ - vqrdmlsh.s , q10, d6[0] │ │ - @ instruction: 0xfff479fc │ │ + str r5, [sp, #4] │ │ + vtbx.8 d27, {d4-d6}, d2 │ │ + vsri.32 , q12, #12 │ │ vshr.u32 , q6, #12 │ │ movs r7, r1 │ │ movs r2, #93 @ 0x5d │ │ @ instruction: 0xfff59e81 │ │ - @ instruction: 0xfff579d8 │ │ + vsri.32 , q2, #11 │ │ vshr.u64 , q12, #12 │ │ movs r7, r1 │ │ movs r2, #59 @ 0x3b │ │ vneg.s16 d20, d30 │ │ - @ instruction: 0xfff479b6 │ │ + vsri.32 d25, d18, #12 │ │ @ instruction: 0xfff4bed4 │ │ movs r7, r1 │ │ │ │ 001422b0 : │ │ mov r0, r1 │ │ bx lr │ │ │ │ @@ -230082,17 +230082,17 @@ │ │ itt ne │ │ ldrne r0, [sp, #44] @ 0x2c │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ revsh r6, r7 │ │ movs r7, r1 │ │ - add r1, sp, #648 @ 0x288 │ │ + stmia r4!, {r1, r2, r3, r4} │ │ vqneg.s16 q13, q7 │ │ - vneg.s16 , q6 │ │ + vqrdmlah.s q12, , d8[0] │ │ vtbx.8 d27, {d20}, d30 │ │ movs r7, r1 │ │ │ │ 00142874 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -230755,17 +230755,17 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #48] @ 0x30 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ push {r3, r5, lr} │ │ movs r7, r1 │ │ - add r2, pc, #888 @ (adr r2, 14329c ) │ │ + pop {r1, r3, r4, r6, pc} │ │ vqshlu.s64 d22, d4, #52 @ 0x34 │ │ - @ instruction: 0xfff56d08 │ │ + vneg.f16 d24, d4 │ │ vsra.u64 , q4, #12 │ │ movs r7, r1 │ │ │ │ 00142f30 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -230977,27 +230977,27 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #40] @ 0x28 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ cbz r0, 143190 │ │ movs r7, r1 │ │ - add r0, pc, #824 @ (adr r0, 1434b4 ) │ │ - vrev32.16 , q1 │ │ - @ instruction: 0xfff46af8 │ │ + cbnz r2, 1431ce │ │ + @ instruction: 0xfff4ab3e │ │ + vsli.32 q12, q10, #20 │ │ vshr.u32 q11, q15, #12 │ │ movs r7, r1 │ │ asrs r7, r6, #12 │ │ vcvt.u32.f32 q12, , #11 │ │ - @ instruction: 0xfff56ab2 │ │ + vceq.f16 d24, d30, #0 │ │ vpaddl.s16 d22, d0 │ │ movs r7, r1 │ │ asrs r1, r3, #13 │ │ vcge.f16 , q6, #0 │ │ - @ instruction: 0xfff46ad4 │ │ + vsli.32 q12, q0, #20 │ │ @ instruction: 0xfff4afd0 │ │ movs r7, r1 │ │ │ │ 001431a8 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #24 │ │ @@ -231072,17 +231072,17 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r6, sp, #992 @ 0x3e0 │ │ movs r7, r1 │ │ - add r6, sp, #856 @ 0x358 │ │ + ldmia r1, {r1, r4, r6} │ │ vsli.64 , , #52 @ 0x34 │ │ - @ instruction: 0xfff369bc │ │ + vsri.32 d24, d24, #13 │ │ @ instruction: 0xfff4ae88 │ │ movs r7, r1 │ │ │ │ 0014327c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -231167,15 +231167,15 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r6, sp, #128 @ 0x80 │ │ movs r7, r1 │ │ ldc2 15, cr15, [r0, #-976]! @ 0xfffffc30 │ │ bl ffe4534a <__cxa_new_handler@@Base+0xffc0175a> │ │ - ldr r4, [r1, #12] │ │ + strh r0, [r1, #26] │ │ @ instruction: 0xfff4ad9c │ │ movs r7, r1 │ │ │ │ 0014336c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -231264,17 +231264,17 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r5, sp, #192 @ 0xc0 │ │ movs r7, r1 │ │ - ldr r6, [r3, #4] │ │ + strh r2, [r3, #22] │ │ vcls.s16 d31, d1 │ │ - @ instruction: 0xfff367cc │ │ + vmlal.u q12, d3, d8[0] │ │ @ instruction: 0xfff4ac9c │ │ movs r7, r1 │ │ │ │ 0014346c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -231395,17 +231395,17 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #20] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r4, sp, #192 @ 0xc0 │ │ movs r7, r1 │ │ - ldr r4, [sp, #248] @ 0xf8 │ │ + @ instruction: 0xb6ba │ │ vrshr.u64 d31, d13, #12 │ │ - vmlsl.u q11, d3, d24[0] │ │ + vmla.i q12, , d20[0] │ │ @ instruction: 0xfff4ab38 │ │ movs r7, r1 │ │ add r3, sp, #464 @ 0x1d0 │ │ movs r7, r1 │ │ │ │ 001435d4 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -231495,15 +231495,15 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r2, sp, #800 @ 0x320 │ │ movs r7, r1 │ │ ldr??.w pc, [r0, #4084] @ 0xff4 │ │ str r2, [r6, #56] @ 0x38 │ │ - vceq.f16 q11, q14, #0 │ │ + vqrdmlsh.s , , d24[0] │ │ vshll.u32 q13, d28, #20 │ │ movs r7, r1 │ │ │ │ 001436cc : │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [r0, #4] │ │ @@ -231617,17 +231617,17 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ add r1, sp, #608 @ 0x260 │ │ movs r7, r1 │ │ - str r4, [r7, #72] @ 0x48 │ │ + ldrb r0, [r7, #28] │ │ vrshr.u32 q11, q8, #12 │ │ - vcgt.f16 d22, d26, #0 │ │ + @ instruction: 0xfff57ea6 │ │ @ instruction: 0xfff4a8fa │ │ movs r7, r1 │ │ │ │ 00143810 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -231756,17 +231756,17 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #28] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r0, sp, #560 @ 0x230 │ │ movs r7, r1 │ │ - ldr r0, [sp, #584] @ 0x248 │ │ + cbz r6, 1439b2 │ │ vrev16.16 d22, d2 │ │ - vrshr.u64 d22, d28, #11 │ │ + vcvt.u16.f16 d23, d24, #11 │ │ vqneg.s16 d26, d20 │ │ movs r7, r1 │ │ bmi.n 143928 │ │ bmi.n 14392a │ │ │ │ 00143980 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -232173,39 +232173,39 @@ │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strb r2, [r0, r7] │ │ movs r7, r1 │ │ add r5, pc, #800 @ (adr r5, 1440c8 ) │ │ movs r7, r1 │ │ beq.n 143e60 │ │ - vtbl.8 d23, {d19-d21}, d27 │ │ - @ instruction: 0xfff45eba │ │ - @ instruction: 0xfff49560 │ │ - @ instruction: 0xfff47b77 │ │ - @ instruction: 0xfff45f86 │ │ + vabal.u , d3, d23 │ │ + vqshrn.u64 d23, q11, #12 │ │ + @ instruction: 0xfff4afdc │ │ + vsli.64 , , #52 @ 0x34 │ │ + vtbl.8 d23, {d4-d6}, d2 │ │ vclz.i16 d26, d0 │ │ movs r7, r1 │ │ - str r4, [sp, #1000] @ 0x3e8 │ │ - @ instruction: 0xfff47b11 │ │ - @ instruction: 0xfff45f20 │ │ - vsri.64 , q4, #12 │ │ - vtbx.8 d23, {d20-d22}, d31 │ │ - @ instruction: 0xfff45efe │ │ - vabal.u , d20, d2 │ │ - @ instruction: 0xfff47b99 │ │ - @ instruction: 0xfff45fa8 │ │ - vsli.32 d25, d12, #20 │ │ - @ instruction: 0xfff47b33 │ │ - vqrdmlsh.s , q2, d2[0] │ │ - vsli.32 d25, d30, #20 │ │ - @ instruction: 0xfff47b55 │ │ - vqrdmlsh.s , q2, d20[0] │ │ - @ instruction: 0xfff45f84 │ │ - vtbx.8 d23, {d20-d22}, d13 │ │ - @ instruction: 0xfff45edc │ │ + add r7, sp, #472 @ 0x1d8 │ │ + vabal.u , d20, d13 │ │ + @ instruction: 0xfff4799c │ │ + vcvt.u32.f32 q13, q2, #12 │ │ + @ instruction: 0xfff4956b │ │ + vqrshrn.u64 d23, q13, #12 │ │ + @ instruction: 0xfff4affe │ │ + vqshlu.s32 d25, d5, #20 │ │ + vtbl.8 d23, {d4-d6}, d20 │ │ + @ instruction: 0xfff4af98 │ │ + vabal.u , d20, d31 │ │ + @ instruction: 0xfff479be │ │ + @ instruction: 0xfff4afba │ │ + vsli.64 , , #52 @ 0x34 │ │ + vtbx.8 d23, {d20-d21}, d16 │ │ + vtbl.8 d23, {d4-d6}, d0 │ │ + @ instruction: 0xfff49549 │ │ + vqrshrn.u64 d23, q4, #12 │ │ vsri.64 , q2, #12 │ │ bmi.n 143dba │ │ │ │ 00143e10 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -232494,25 +232494,25 @@ │ │ vqrdmlsh.s , , d31[0] │ │ vcvt.u32.f32 , , #1 │ │ vcvt.u32.f32 , , #1 │ │ strh r0, [r1, r2] │ │ movs r7, r1 │ │ add r2, pc, #488 @ (adr r2, 144308 ) │ │ movs r7, r1 │ │ - str r1, [sp, #232] @ 0xe8 │ │ + add r3, sp, #728 @ 0x2d8 │ │ vcvt.f16.u16 , , #12 │ │ - vtbx.8 d21, {d4-d7}, d16 │ │ - vsra.u32 , q6, #12 │ │ + vsli.64 , q6, #52 @ 0x34 │ │ + @ instruction: 0xfff4abd8 │ │ @ instruction: 0xfff4fc95 │ │ - vtbl.8 d21, {d20-d23}, d2 │ │ + vsli.64 , q15, #52 @ 0x34 │ │ vshr.u64 d26, d0, #12 │ │ movs r7, r1 │ │ - ldrh r6, [r4, r7] │ │ + strb r2, [r4, #25] │ │ vcvt.f16.u16 , , #12 │ │ - @ instruction: 0xfff45b3e │ │ + vsli.64 d23, d26, #52 @ 0x34 │ │ Address 0x144146 is out of bounds. │ │ │ │ │ │ 00144148 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -232597,17 +232597,17 @@ │ │ subs r4, #176 @ 0xb0 │ │ ldr r7, [pc, #440] @ (1443dc ) │ │ movs r7, r1 │ │ ldr r7, [sp, #296] @ 0x128 │ │ movs r7, r1 │ │ ldr r6, [sp, #928] @ 0x3a0 │ │ movs r7, r1 │ │ - ldrh r3, [r7, #62] @ 0x3e │ │ + add r2, sp, #476 @ 0x1dc │ │ vpadal.s16 q11, │ │ - vshll.u32 , d10, #21 │ │ + vsri.64 d23, d6, #11 │ │ Address 0x144236 is out of bounds. │ │ │ │ │ │ 00144238 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -235981,15 +235981,15 @@ │ │ bne.n 14688e │ │ bx lr │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (1468b0 ) │ │ add r0, pc │ │ bl a91f8 │ │ - strb r5, [r7, #5] │ │ + ldrh r1, [r7, #30] │ │ vsli.64 , q8, #52 @ 0x34 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r9, r0 │ │ ldr r4, [r0, #0] │ │ ldr r0, [r0, #8] │ │ @@ -236821,27 +236821,27 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ add r0, sp, #144 @ 0x90 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strb r0, [r0, #15] │ │ movs r7, r1 │ │ cmp r2, #58 @ 0x3a │ │ - vsri.64 d16, d27, #11 │ │ + vcvt.u32.f32 d17, d23, #11 │ │ vqdmulh.s q14, q10, d7[0] │ │ vrsra.u64 d18, d0, #12 │ │ movs r7, r1 │ │ movs r3, #160 @ 0xa0 │ │ movs r7, r1 │ │ movs r3, #242 @ 0xf2 │ │ movs r7, r1 │ │ bhi.n 147230 │ │ - vclz.i16 d16, d3 │ │ + @ instruction: 0xfff41eff │ │ vmull.u q14, d20, d15 │ │ vqshl.u64 d27, d7, #52 @ 0x34 │ │ - vmls.i q8, , d17[0] │ │ + @ instruction: 0xfff31edd │ │ vdup.32 q14, d29[0] │ │ vrev32.16 d23, d2 │ │ movs r7, r1 │ │ │ │ 00147190 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -241166,16 +241166,16 @@ │ │ vsra.u32 d30, d9, #12 │ │ vqrshrun.s64 d28, q0, #12 │ │ vshr.u32 q13, , #12 │ │ vqrshrun.s64 d31, q10, #12 │ │ movs r6, r1 │ │ add r8, r5 │ │ movs r7, r1 │ │ - pldw [r5, #4083] @ 0xff3 │ │ - ldmia r0!, {r5, r7} │ │ + asrs r1, r6, #12 │ │ + vtbl.8 d28, {d20}, d16 │ │ vrev32.16 d26, d25 │ │ vsli.64 , q8, #52 @ 0x34 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #20 │ │ ldr.w fp, [r0] │ │ cmp r2, #0 │ │ @@ -243120,15 +243120,15 @@ │ │ vqshl.u32 , q12, #20 │ │ @ instruction: 0xfff45da3 │ │ vtbl.8 d25, {d19}, d31 │ │ vqshl.u64 , q7, #52 @ 0x34 │ │ vrsra.u64 d22, d26, #12 │ │ vtbl.8 d25, {d20}, d13 │ │ vqshl.u64 d21, d28, #52 @ 0x34 │ │ - vcls.s16 , q4 │ │ + vqrdmlah.s q9, q10, d4[0] │ │ vqneg.s16 , │ │ vqshlu.s64 , q8, #52 @ 0x34 │ │ vrsra.u64 d22, d8, #12 │ │ vtbx.8 d25, {d4}, d27 │ │ vqshl.u64 d21, d10, #52 @ 0x34 │ │ vsri.64 , q3, #12 │ │ vqshl.u32 d25, d17, #19 │ │ @@ -243570,27 +243570,27 @@ │ │ vmlal.u , d19, d4[0] │ │ vshr.u64 , q9, #12 │ │ vraddhn.i d25, , q9 │ │ vrshr.u32 , q14, #13 │ │ vaddw.u , q10, d2 │ │ vsli.32 d25, d18, #19 │ │ vsubw.u , , d12 │ │ - vtbl.8 d18, {d4-d7}, d3 │ │ + vsli.32 q10, , #20 │ │ @ instruction: 0xfff493ca │ │ vaddw.u , , d20 │ │ - @ instruction: 0xfff42adf │ │ + vsli.32 q10, , #20 │ │ vsubw.u , q10, d22 │ │ vaddw.u , , d0 │ │ vcvt.f32.u32 d21, d3, #12 │ │ vsri.32 d25, d2, #12 │ │ @ instruction: 0xfff351ec │ │ vpaddl.u16 q9, q6 │ │ vsli.32 , q3, #21 │ │ vrsra.u32 d21, d16, #13 │ │ - vtbl.8 d18, {d4-d7}, d23 │ │ + vabal.u q10, d20, d19 │ │ @ instruction: 0xfff493ee │ │ @ instruction: 0xfff351c8 │ │ vrev32.16 d27, d26 │ │ vsri.32 , q5, #13 │ │ vrshr.u32 d21, d20, #13 │ │ vsra.u32 d27, d6, #12 │ │ vmls.i , , d6[0] │ │ @@ -243811,36 +243811,36 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ cmp r1, #18 │ │ movs r7, r1 │ │ cbnz r6, 14b9ec │ │ - vqdmulh.s , q10, d9[0] │ │ + vqabs.s16 , │ │ vqrdmlsh.s q10, , d12[0] │ │ - vqrshrun.s64 d18, , #12 │ │ - vcvt.f16.u16 d27, d1, #12 │ │ + vpaddl.u16 q10, │ │ + vpadal.u16 d29, d13 │ │ vcvt.u32.f32 d20, d4, #13 │ │ @ instruction: 0xfff4b8d2 │ │ - vtbl.8 d27, {d20-d23}, d21 │ │ + vpadal.s16 d29, d17 │ │ @ instruction: 0xfff34ea8 │ │ - vtbl.8 d18, {d4}, d27 │ │ - vtbx.8 d27, {d20-d23}, d9 │ │ + vpaddl.u16 d20, d23 │ │ + vpadal.s16 , │ │ vqrdmlah.s q10, , d12[0] │ │ vtbx.8 d27, {d20-d21}, d12 │ │ - @ instruction: 0xfff4bc9f │ │ + vqshl.u32 d29, d11, #20 │ │ @ instruction: 0xfff34fa2 │ │ @ instruction: 0xfff45b17 │ │ - vtbx.8 d27, {d20-d23}, d29 │ │ + vpadal.s16 , │ │ @ instruction: 0xfff34ef0 │ │ @ instruction: 0xfff41ef8 │ │ - vcvt.f16.u16 , , #11 │ │ + vqshlu.s64 , , #53 @ 0x35 │ │ vcvt.u32.f32 q10, q6, #13 │ │ vqrdmlsh.s , q10, d4[0] │ │ - vcvt.f16.u16 d27, d21, #13 │ │ + vqshlu.s64 d29, d17, #51 @ 0x33 │ │ vcvt.u32.f32 d20, d24, #13 │ │ vtbl.8 d18, {d4}, d10 │ │ movs r7, r1 │ │ │ │ 0014ba10 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -244867,16 +244867,16 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ adds r4, r3, #0 │ │ movs r7, r1 │ │ asrs r6, r0, #12 │ │ - vrsra.u64 d31, d18, #11 │ │ - @ instruction: 0xfff34360 │ │ + @ instruction: 0xfff50e2e │ │ + @ instruction: 0xfff44360 │ │ Address 0x14c4f2 is out of bounds. │ │ │ │ │ │ 0014c4f4 >&) const@@Base>: │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #24 │ │ @@ -245363,28 +245363,28 @@ │ │ ldreq.w r8, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 230610 <__emutls_get_address@@Base+0x3788> │ │ nop │ │ subs r2, r3, r0 │ │ movs r7, r1 │ │ ldr r5, [sp, #856] @ 0x358 │ │ - @ instruction: 0xfff3efb8 │ │ - vqrdmlsh.s , , d16[0] │ │ + vshll.u32 q8, d20, #19 │ │ + vqrdmlsh.s , q2, d16[0] │ │ @ instruction: 0xfff49dfa │ │ - @ instruction: 0xfff3efdc │ │ - @ instruction: 0xfff33f84 │ │ - @ instruction: 0xfff4189b │ │ - @ instruction: 0xfff4ef94 │ │ - vcvt.u32.f32 d19, d28, #13 │ │ + @ instruction: 0xfff30a58 │ │ + @ instruction: 0xfff43f84 │ │ + vrsra.u32 d19, d7, #12 │ │ + vshll.u32 q8, d0, #20 │ │ + vcvt.u32.f32 d19, d28, #12 │ │ @ instruction: 0xfff44b3f │ │ - vcvt.u32.f32 q15, q8, #12 │ │ - vcvt.u32.f32 d19, d8, #13 │ │ - vtbx.8 d17, {d4}, d1 │ │ - vcvt.u32.f32 d30, d26, #12 │ │ - vqrdmlah.s , , d18[0] │ │ + vtbx.8 d16, {d20-d21}, d28 │ │ + vcvt.u32.f32 d19, d8, #12 │ │ + vrshr.u64 d19, d29, #12 │ │ + @ instruction: 0xfff409b6 │ │ + vqrdmlah.s , q10, d18[0] │ │ vpadal.u16 , q14 │ │ movs r7, r1 │ │ ldmia r4!, {r2, r6} │ │ movs r6, r1 │ │ │ │ 0014ca1c : │ │ push {r4, r6, r7, lr} │ │ @@ -245690,24 +245690,24 @@ │ │ vcvt.u16.f16 d19, d10, #12 │ │ @ instruction: 0xfff49b18 │ │ vcvt.u16.f16 d19, d13, #13 │ │ vmull.u , d20, d18 │ │ vcvt.f16.u16 d25, d14, #12 │ │ @ instruction: 0xfff33e23 │ │ @ instruction: 0xfff43da8 │ │ - vsri.64 d17, d29, #12 │ │ + vcvt.u32.f32 d18, d25, #12 │ │ @ instruction: 0xfff43bd9 │ │ @ instruction: 0xfff43b5e │ │ - vclz.i16 , │ │ + vcvt.u32.f32 q9, , #12 │ │ @ instruction: 0xfff43bfd │ │ vtbl.8 d19, {d20-d23}, d2 │ │ vqneg.s16 q10, │ │ vdup.32 d19, d17[0] │ │ vtbl.8 d19, {d20-d23}, d22 │ │ - vabal.u , d4, d25 │ │ + @ instruction: 0xfff42fa5 │ │ vdup.32 , d5[0] │ │ vtbx.8 d19, {d20-d23}, d10 │ │ vtbx.8 d25, {d20-d22}, d20 │ │ vqdmulh.s , , d25[0] │ │ vdup.32 , d30[0] │ │ vtbx.8 d25, {d20-d23}, d10 │ │ vqrdmulh.s , , d15[0] │ │ @@ -246062,37 +246062,37 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ asrs r0, r1, #7 │ │ movs r7, r1 │ │ - asrs r3, r0, #3 │ │ - vsli.64 q15, q14, #52 @ 0x34 │ │ - @ instruction: 0xfff33764 │ │ + cmp r3, #63 @ 0x3f │ │ + vshr.u32 q8, q12, #12 │ │ + vqabs.s16 , q10 │ │ vsubw.u q10, q10, d31 │ │ - vpadal.s16 d30, d16 │ │ - vabdl.u , d19, d8 │ │ + vshr.u64 d16, d12, #12 │ │ + vqneg.s16 d19, d8 │ │ vpadal.s16 , q3 │ │ - vmlsl.u q15, d3, d24[0] │ │ - vqshl.u64 , q0, #51 @ 0x33 │ │ + vmla.i q8, , d20[0] │ │ + vqshl.u64 , q0, #52 @ 0x34 │ │ vshr.u64 d17, d30, #12 │ │ movs r7, r1 │ │ str r6, [sp, #424] @ 0x1a8 │ │ - vrsubhn.i d30, , q6 │ │ - vqshl.u64 , q10, #51 @ 0x33 │ │ + vaddw.u q8, , d8 │ │ + vqshl.u64 , q10, #52 @ 0x34 │ │ vsra.u32 d17, d14, #12 │ │ movs r7, r1 │ │ asrs r4, r0, #5 │ │ movs r7, r1 │ │ asrs r4, r2, #6 │ │ movs r7, r1 │ │ - asrs r3, r1, #4 │ │ - vpadal.s16 q15, q2 │ │ - vabdl.u , d19, d28 │ │ + cmp r3, #135 @ 0x87 │ │ + vrev32.16 q8, q0 │ │ + vqneg.s16 d19, d28 │ │ vrev32.16 , q10 │ │ movs r7, r1 │ │ asrs r2, r4, #2 │ │ movs r7, r1 │ │ │ │ 0014d140 : │ │ push {r7, lr} │ │ @@ -246216,15 +246216,15 @@ │ │ lsrs r6, r7, #28 │ │ movs r7, r1 │ │ lsrs r6, r4, #26 │ │ movs r7, r1 │ │ lsrs r0, r0, #28 │ │ movs r7, r1 │ │ strh r0, [r0, #52] @ 0x34 │ │ - vqshlu.s32 d29, d16, #19 │ │ + vaddl.u , d19, d28 │ │ vsli.64 , q10, #51 @ 0x33 │ │ vqrdmlah.s q8, q10, d2[0] │ │ movs r7, r1 │ │ │ │ 0014d26c : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ @@ -246363,21 +246363,21 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ lsrs r4, r6, #24 │ │ movs r7, r1 │ │ - b.n 14ce3a │ │ - vcvt.u16.f16 q15, , #13 │ │ - vclz.i16 , q5 │ │ + @ instruction: 0xffb1fff3 │ │ + ldcl 15, cr15, [r3, #-976]! @ 0xfffffc30 │ │ + adds r4, #202 @ 0xca │ │ vqabs.s16 d22, d23 │ │ @ instruction: 0xfff3ed2b │ │ vclz.i16 d19, d2 │ │ - vsli.32 q15, , #20 │ │ + @ instruction: 0xfff4ffd5 │ │ @ instruction: 0xfff3ed97 │ │ vclz.i16 , q15 │ │ vsli.32 d24, d18, #20 │ │ vqrdmulh.s q15, , d15[0] │ │ vclz.i16 d19, d22 │ │ @ instruction: 0xfff40d9e │ │ movs r7, r1 │ │ @@ -246519,24 +246519,24 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ lsrs r0, r4, #18 │ │ movs r7, r1 │ │ - b.n 14cd9e │ │ - @ instruction: 0xfff33fdd │ │ + mrc2 15, 4, pc, cr11, cr3, {7} │ │ + subs r7, #221 @ 0xdd │ │ vrsra.u64 d19, d20, #12 │ │ vsli.64 d22, d7, #52 @ 0x34 │ │ vcvt.u32.f32 d19, d11, #13 │ │ vrshr.u64 , q9, #12 │ │ - vsubw.u q15, q10, d21 │ │ + @ instruction: 0xfff4fe21 │ │ vqrdmlsh.s , , d19[0] │ │ vrsra.u32 d19, d26, #12 │ │ - vshr.u32 d28, d15, #12 │ │ + @ instruction: 0xfff4da9b │ │ vcvt.u32.f32 d19, d31, #13 │ │ vrsra.u32 d19, d6, #12 │ │ vtbx.8 d16, {d20-d23}, d26 │ │ movs r7, r1 │ │ │ │ 0014d590 : │ │ push {r4, r6, r7, lr} │ │ @@ -246766,30 +246766,30 @@ │ │ movs r7, r1 │ │ ldrh r6, [r5, #58] @ 0x3a │ │ vmlsl.u , d19, d14[0] │ │ vshr.u64 , q12, #13 │ │ vqrdmlsh.s q12, q2, d10[0] │ │ vrsubhn.i d19, , q13 │ │ vshr.u64 , q2, #13 │ │ - @ instruction: 0xfff49ef6 │ │ + vqrshrn.u64 d27, q9, #12 │ │ vqshl.u64 d19, d30, #51 @ 0x33 │ │ @ instruction: 0xfff331e8 │ │ vrsra.u32 d22, d17, #12 │ │ vmlsl.u , d3, d18[0] │ │ vaddl.u , d19, d12 │ │ - @ instruction: 0xfff4e1cf │ │ + vdup.32 , d11[0] │ │ vqshl.u32 d19, d26, #19 │ │ @ instruction: 0xfff33164 │ │ @ instruction: 0xfff48f26 │ │ vrsubhn.i d19, , q3 │ │ vshr.u64 d19, d16, #13 │ │ - vaddw.u q15, q10, d27 │ │ + vdup.32 d31, d23[0] │ │ vqshl.u32 d19, d6, #19 │ │ @ instruction: 0xfff33140 │ │ - @ instruction: 0xfff4be25 │ │ + vtbl.8 d29, {d20}, d17 │ │ vqshlu.s64 , q9, #51 @ 0x33 │ │ vsra.u32 d19, d12, #13 │ │ vshll.u32 q8, d4, #20 │ │ movs r7, r1 │ │ │ │ 0014d82c : │ │ push {r4, r6, r7, lr} │ │ @@ -247019,30 +247019,30 @@ │ │ movs r7, r1 │ │ ldrh r4, [r2, #38] @ 0x26 │ │ vaddl.u , d19, d9 │ │ vcvt.f32.u32 q9, q7, #13 │ │ @ instruction: 0xfff48cb0 │ │ vmla.i , , d21[0] │ │ vcvt.f32.u32 d18, d26, #13 │ │ - vcvt.f16.u16 , q4, #12 │ │ + vqshlu.s64 , q2, #52 @ 0x34 │ │ vsra.u32 , , #13 │ │ vqrdmlsh.s q9, , d10[0] │ │ vshr.u64 d22, d7, #12 │ │ vshr.u32 d23, d13, #13 │ │ @ instruction: 0xfff32df2 │ │ - vcvt.u32.f32 d29, d21, #12 │ │ + @ instruction: 0xfff4f9b1 │ │ vshr.u64 , , #13 │ │ vqrdmlah.s q9, , d10[0] │ │ vmull.u q12, d20, d12 │ │ vmla.i , , d1[0] │ │ vcvt.f32.u32 d18, d6, #13 │ │ - vcvt.u32.f32 d29, d1, #12 │ │ + vtbl.8 d31, {d20-d21}, d13 │ │ vshr.u64 , , #13 │ │ @ instruction: 0xfff32ea6 │ │ - vtbl.8 d27, {d20-d23}, d11 │ │ + vpadal.s16 d29, d7 │ │ vaddl.u , d19, d29 │ │ @ instruction: 0xfff32e82 │ │ vqshl.u32 q8, q13, #20 │ │ movs r7, r1 │ │ │ │ 0014dac8 : │ │ push {r4, r6, r7, lr} │ │ @@ -247144,15 +247144,15 @@ │ │ movs r7, r1 │ │ lsls r4, r5, #21 │ │ movs r7, r1 │ │ lsls r0, r0, #22 │ │ movs r7, r1 │ │ lsls r6, r1, #21 │ │ movs r7, r1 │ │ - cbnz r1, 14dbf0 │ │ + bmi.n 14dc02 │ │ vtbl.8 d27, {d3-d5}, d6 │ │ @ instruction: 0xfff42c98 │ │ Address 0x14dbce is out of bounds. │ │ │ │ │ │ 0014dbd0 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -247349,15 +247349,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #24] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ lsls r4, r1, #19 │ │ movs r7, r1 │ │ - cbz r3, 14ddd6 │ │ + ldmia r3!, {r0, r1, r2, r4, r5, r7} │ │ vqshlu.s32 d29, d22, #19 │ │ vtbx.8 d18, {d4-d7}, d2 │ │ vsri.64 d16, d10, #12 │ │ movs r7, r1 │ │ lsls r6, r6, #16 │ │ movs r7, r1 │ │ @ instruction: 0xfa72fff4 │ │ @@ -247484,15 +247484,15 @@ │ │ movs r7, r1 │ │ lsls r0, r3, #8 │ │ movs r7, r1 │ │ lsls r4, r5, #8 │ │ movs r7, r1 │ │ lsls r2, r7, #7 │ │ movs r7, r1 │ │ - @ instruction: 0xb649 │ │ + beq.n 14deaa │ │ vrsubhn.i d27, , q15 │ │ vtbx.8 d18, {d4-d5}, d0 │ │ Address 0x14df26 is out of bounds. │ │ │ │ │ │ 0014df28 : │ │ ldrb r0, [r0, #3] │ │ @@ -247902,30 +247902,30 @@ │ │ @ instruction: 0xfff3ea9a │ │ vsli.64 d18, d24, #52 @ 0x34 │ │ vshr.u32 d16, d12, #12 │ │ movs r7, r1 │ │ ldr r7, [r2, #0] │ │ vcvt.f16.u16 d30, d4, #12 │ │ vqshl.u32 d18, d18, #20 │ │ - vrshr.u64 d25, d31, #12 │ │ + vcvt.u16.f16 d26, d27, #12 │ │ @ instruction: 0xfff3ea76 │ │ vsli.64 d18, d4, #52 @ 0x34 │ │ vpadal.s16 d31, d24 │ │ vtbx.8 d30, {d4-d7}, d30 │ │ vpadal.u16 d18, d12 │ │ - vqabs.s16 q14, q4 │ │ + @ instruction: 0xfff4e1c4 │ │ @ instruction: 0xfff3ebdc │ │ vqshlu.s64 q9, q13, #52 @ 0x34 │ │ vqrdmulh.s q15, q2, d24[0] │ │ @ instruction: 0xfff4ea52 │ │ vsli.32 q9, q8, #20 │ │ vsri.64 q12, q15, #12 │ │ @ instruction: 0xfff3eb18 │ │ vqshlu.s32 d18, d22, #20 │ │ - vcvt.f16.u16 d26, d3, #12 │ │ + vpadal.u16 d28, d15 │ │ vtbl.8 d30, {d19-d22}, d20 │ │ vpadal.u16 q9, q1 │ │ vsli.64 d28, d1, #52 @ 0x34 │ │ vtbl.8 d30, {d4-d6}, d30 │ │ @ instruction: 0xfff4254c │ │ vsli.64 d31, d12, #52 @ 0x34 │ │ vtbx.8 d30, {d20-d22}, d18 │ │ @@ -249840,15 +249840,15 @@ │ │ add r2, pc, #208 @ (adr r2, 14f860 ) │ │ movs r6, r1 │ │ add r1, pc, #856 @ (adr r1, 14faec ) │ │ movs r6, r1 │ │ adds r4, #129 @ 0x81 │ │ vqshrn.u64 d29, q7, #13 │ │ vsri.32 d17, d28, #12 │ │ - vaddw.u , q10, d6 │ │ + vdup.32 d30, d2[0] │ │ @ instruction: 0xfff3d8f8 │ │ vsri.32 d17, d6, #12 │ │ vsra.u64 d26, d28, #12 │ │ movs r6, r1 │ │ add r1, pc, #392 @ (adr r1, 14f93c ) │ │ movs r6, r1 │ │ str r4, [r5, #68] @ 0x44 │ │ @@ -249885,32 +249885,32 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #20] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ @ instruction: 0xf6ea000e │ │ - stmia r4!, {r0, r1, r5} │ │ + udf #159 @ 0x9f │ │ vsri.32 d17, d22, #13 │ │ vqrshrun.s64 d29, q3, #12 │ │ vrsra.u32 , q10, #12 │ │ vsri.32 d17, d2, #12 │ │ vqshrun.s64 d29, q9, #12 │ │ vrsra.u32 , q0, #12 │ │ vcvt.u32.f32 , , #12 │ │ vtbl.8 d29, {d4}, d14 │ │ vsubw.u , q2, d28 │ │ vcls.s16 d22, d1 │ │ vabdl.u , d19, d18 │ │ vpaddl.u16 , q0 │ │ - vqshl.u64 d25, d12, #52 @ 0x34 │ │ + vrshr.u32 d27, d8, #12 │ │ vrsubhn.i d29, , q11 │ │ @ instruction: 0xfff411c4 │ │ - vdup.32 q15, d23[0] │ │ - @ instruction: 0xfff3d7ea │ │ + vpadal.u16 q8, │ │ + vqneg.s16 , q13 │ │ vsubw.u , q2, d8 │ │ vcls.s16 , q7 │ │ movs r6, r1 │ │ ssat r0, #15, r2 │ │ add.w r0, sl, #14 │ │ @ instruction: 0xf130000e │ │ @ instruction: 0xf0be000e │ │ @@ -249940,39 +249940,39 @@ │ │ vpaddl.u16 , q10 │ │ vcvt.u16.f16 d23, d13, #12 │ │ vqshl.u32 , q5, #20 │ │ vrshr.u32 , q12, #12 │ │ vcvt.f32.u32 d22, d30, #12 │ │ vqshlu.s32 d29, d6, #20 │ │ vsra.u32 d17, d20, #12 │ │ - @ instruction: 0xfff4db5d │ │ + vsli.64 , , #52 @ 0x34 │ │ vqshlu.s32 , q7, #19 │ │ vsra.u32 , q14, #12 │ │ vcvt.u32.f32 d22, d19, #12 │ │ vpadal.u16 , q15 │ │ vpaddl.s16 d17, d12 │ │ vrsra.u64 q11, , #12 │ │ vqshl.u32 , q15, #19 │ │ vrshr.u64 d17, d12, #12 │ │ @ instruction: 0xfff46df6 │ │ @ instruction: 0xfff4d5ce │ │ vrev32.16 , q14 │ │ - vtbl.8 d29, {d20-d23}, d1 │ │ + vsli.64 , , #52 @ 0x34 │ │ vrsubhn.i d29, , q1 │ │ vaddw.u , q10, d16 │ │ vcvt.u32.f32 q11, , #12 │ │ vqshl.u32 d29, d2, #20 │ │ vrshr.u32 d17, d16, #12 │ │ @ instruction: 0xfff47cf9 │ │ vqshl.u32 d29, d22, #20 │ │ vrshr.u32 , q2, #12 │ │ vcvt.f32.u32 d22, d10, #12 │ │ vsli.64 , q9, #52 @ 0x34 │ │ vsra.u32 d17, d0, #12 │ │ - @ instruction: 0xfff4db39 │ │ + vsli.64 d31, d21, #52 @ 0x34 │ │ vqshlu.s32 d29, d26, #19 │ │ vsra.u32 , q4, #12 │ │ @ instruction: 0xfff46f0f │ │ vpadal.u16 , q5 │ │ @ instruction: 0xfff411e8 │ │ Address 0x14f966 is out of bounds. │ │ │ │ @@ -250374,15 +250374,15 @@ │ │ vmla.i , , d26[0] │ │ vtbl.8 d16, {d20-d23}, d8 │ │ @ instruction: 0xfff4e5ec │ │ movs r6, r1 │ │ asrs r3, r5, #11 │ │ @ instruction: 0xfff3d1e4 │ │ @ instruction: 0xfff40d02 │ │ - vtbl.8 d23, {d20}, d15 │ │ + vsubw.u , q2, d11 │ │ vmla.i , , d6[0] │ │ vtbx.8 d16, {d4-d7}, d20 │ │ @ instruction: 0xfff4dbf8 │ │ vsra.u32 d29, d30, #12 │ │ vcvt.f16.u16 q8, q6, #12 │ │ vqneg.s16 q9, q1 │ │ vaddw.u , q10, d28 │ │ @@ -250940,15 +250940,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ble.n 1504a8 │ │ movs r6, r1 │ │ - ldrh r7, [r7, #18] │ │ + add r4, pc, #1004 @ (adr r4, 1507b0 ) │ │ @ instruction: 0xfff37a7b │ │ vclz.i16 d16, d6 │ │ vcvt.u16.f16 , q3, #12 │ │ movs r6, r1 │ │ ble.n 150448 │ │ movs r6, r1 │ │ │ │ @@ -251079,15 +251079,15 @@ │ │ vrsra.u64 d16, d26, #13 │ │ vsli.32 d21, d12, #20 │ │ vtbx.8 d16, {d19-d20}, d11 │ │ vrsra.u64 d16, d6, #13 │ │ vsri.32 d16, d0, #12 │ │ vtbl.8 d16, {d20-d21}, d3 │ │ @ instruction: 0xfff3034e │ │ - vrev32.16 q14, q5 │ │ + vtbx.8 d29, {d4-d7}, d6 │ │ vtbl.8 d16, {d19-d20}, d23 │ │ vrsra.u32 q8, q9, #13 │ │ vdup.32 , d24[0] │ │ movs r6, r1 │ │ │ │ 00150534 : │ │ push {r4, r6, r7, lr} │ │ @@ -251237,15 +251237,15 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ bge.n 15076c │ │ movs r6, r1 │ │ strh r7, [r1, r5] │ │ - vrshr.u32 , , #13 │ │ + vqdmulh.s q14, , d13[0] │ │ vsra.u64 d16, d4, #13 │ │ vtbx.8 d29, {d4-d6}, d2 │ │ movs r6, r1 │ │ │ │ 001506c4 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ @@ -251343,15 +251343,15 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ bls.n 15086c │ │ movs r6, r1 │ │ strh r1, [r7, #34] @ 0x22 │ │ - vtbl.8 d23, {d4-d6}, d22 │ │ + vclz.i16 d25, d18 │ │ vshr.u64 d16, d4, #13 │ │ vtbx.8 d29, {d4-d5}, d2 │ │ movs r6, r1 │ │ │ │ 001507c4 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ @@ -251396,15 +251396,15 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ bhi.n 1507ec │ │ movs r6, r1 │ │ lsls r7, r3, #25 │ │ - vrsubhn.i d24, , q7 │ │ + vaddl.u q13, d19, d10 │ │ vshr.u32 d16, d4, #13 │ │ vtbx.8 d29, {d20}, d2 │ │ movs r6, r1 │ │ │ │ 00150844 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -251512,15 +251512,15 @@ │ │ bhi.n 15094c │ │ movs r6, r1 │ │ bvc.n 150924 │ │ movs r6, r1 │ │ ldmia r6, {r1, r2, r3, r6, r7} │ │ vrshr.u64 q9, , #12 │ │ vcvt.u32.f32 d31, d18, #12 │ │ - vcvt.f16.u16 d24, d7, #13 │ │ + vqshlu.s64 d26, d3, #51 @ 0x33 │ │ vrshr.u64 q9, , #13 │ │ @ instruction: 0xfff4ff0e │ │ Address 0x150962 is out of bounds. │ │ │ │ │ │ 00150964 : │ │ push {r4, r5, r7, lr} │ │ @@ -251614,15 +251614,15 @@ │ │ ldr r0, [sp, #28] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bvc.n 150ac4 │ │ movs r6, r1 │ │ bvc.n 150a7c │ │ movs r6, r1 │ │ - ldrh r7, [r0, #24] │ │ + add r5, pc, #524 @ (adr r5, 150c68 ) │ │ vabdl.u q11, d19, d14 │ │ @ instruction: 0xfff4fdfe │ │ vrsubhn.i d29, , q14 │ │ movs r6, r1 │ │ │ │ 00150a68 : │ │ push {r4, r5, r7, lr} │ │ @@ -251717,15 +251717,15 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bvs.n 150bbc │ │ movs r6, r1 │ │ bpl.n 150ac0 │ │ movs r6, r1 │ │ bpl.n 150af0 │ │ movs r6, r1 │ │ - ldrh r7, [r0, #16] │ │ + add r4, pc, #524 @ (adr r4, 150d6c ) │ │ vrsubhn.i d22, , q7 │ │ @ instruction: 0xfff4fcfe │ │ Address 0x150b66 is out of bounds. │ │ │ │ │ │ 00150b68 : │ │ push {r4, r5, r7, lr} │ │ @@ -251842,16 +251842,16 @@ │ │ movs r6, r1 │ │ bmi.n 150c64 │ │ movs r6, r1 │ │ bpl.n 150ca0 │ │ movs r6, r1 │ │ bmi.n 150d8c │ │ movs r6, r1 │ │ - ldrh r1, [r3, #6] │ │ - vtbl.8 d22, {d3-d4}, d21 │ │ + add r3, pc, #340 @ (adr r3, 150de8 > const&) const@@Base+0x1c>) │ │ + vsubw.u q12, , d17 │ │ @ instruction: 0xfff3fbd0 │ │ Address 0x150c9a is out of bounds. │ │ │ │ │ │ 00150c9c : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -251966,16 +251966,16 @@ │ │ movs r6, r1 │ │ bcc.n 150d30 │ │ movs r6, r1 │ │ bcc.n 150e68 > const&) const@@Base+0x9c> │ │ movs r6, r1 │ │ bcc.n 150e98 > const&) const@@Base+0xcc> │ │ movs r6, r1 │ │ - strh r1, [r5, #60] @ 0x3c │ │ - vqshl.u64 q11, , #51 @ 0x33 │ │ + add r2, pc, #148 @ (adr r2, 150e58 > const&) const@@Base+0x8c>) │ │ + vrshr.u32 q12, , #13 │ │ vtbl.8 d31, {d19-d21}, d16 │ │ Address 0x150dca is out of bounds. │ │ │ │ │ │ 00150dcc > const&) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -252153,15 +252153,15 @@ │ │ vmlal.u q11, d3, d24[0] │ │ @ instruction: 0xfff4f8d8 │ │ vaddw.u , , d30 │ │ movs r6, r1 │ │ lsrs r3, r0, #18 │ │ vmlal.u q11, d3, d4[0] │ │ @ instruction: 0xfff4f8b4 │ │ - vrsubhn.i d24, , │ │ + vaddl.u q13, d19, d1 │ │ vsubl.u q11, d19, d12 │ │ @ instruction: 0xfff4f8fc │ │ Address 0x150fbe is out of bounds. │ │ │ │ │ │ 00150fc0 > const&) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -252340,15 +252340,15 @@ │ │ vshr.u32 q11, q11, #13 │ │ vpadal.u16 , q11 │ │ @ instruction: 0xfff3cfbc │ │ movs r6, r1 │ │ lsrs r1, r2, #10 │ │ vshr.u32 q11, q1, #13 │ │ vpadal.u16 , q1 │ │ - vsri.32 d24, d3, #13 │ │ + @ instruction: 0xfff39e8f │ │ vshr.u64 d22, d10, #13 │ │ vqabs.s16 d31, d10 │ │ Address 0x1511ae is out of bounds. │ │ │ │ │ │ 001511b0 : │ │ ldr r0, [pc, #4] @ (1511b8 ) │ │ @@ -252672,15 +252672,15 @@ │ │ pop {r4, r5, r7, pc} │ │ bmi.n 1514b2 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (151514 ) │ │ add r0, pc │ │ bl a91f8 │ │ - stmia r5!, {r0, r3, r4} │ │ + svc 149 @ 0x95 │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r8, r0 │ │ ldrd r5, r0, [r0, #4] │ │ mov r4, r1 │ │ @@ -252847,15 +252847,15 @@ │ │ bl c71d0 │ │ bmi.n 1516ba │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (15171c ) │ │ add r0, pc │ │ bl a91f8 │ │ - stmia r3!, {r0, r4} │ │ + ble.n 15163a │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r8, r0 │ │ ldrd r5, r0, [r0, #4] │ │ mov r6, r1 │ │ @@ -252966,15 +252966,15 @@ │ │ bl 151864 │ │ bl c71d0 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (151870 ) │ │ add r0, pc │ │ bl a91f8 │ │ - stmia r1!, {r0, r2, r3, r4, r5, r7} │ │ + bgt.n 1518e6 │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r4, r0 │ │ ldrd sl, r0, [r0, #4] │ │ movw r8, #43691 @ 0xaaab │ │ @@ -253117,19 +253117,19 @@ │ │ bl c71d0 │ │ bmi.n 1519d2 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (151a34 ) │ │ add r0, pc │ │ bl a91f8 │ │ - ittee │ │ - vsli.64 , q8, #51 @ 0x33 │ │ - add r7, sp, #12 │ │ - stmdbal sp!, {r8, r9, sl, fp} │ │ - subal sp, #12 │ │ + bge.n 151b22 │ │ + vsli.64 , q8, #51 @ 0x33 │ │ + add r7, sp, #12 │ │ + stmdb sp!, {r8, r9, sl, fp} │ │ + sub sp, #12 │ │ mov r4, r0 │ │ ldrd fp, r0, [r0, #4] │ │ mov sl, r1 │ │ movw r3, #43691 @ 0xaaab │ │ sub.w r1, r0, fp │ │ movt r3, #43690 @ 0xaaaa │ │ mov r5, fp │ │ @@ -253274,15 +253274,15 @@ │ │ bl c71d0 │ │ bmi.n 151b9e │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (151c00 ) │ │ add r0, pc │ │ bl a91f8 │ │ - bkpt 0x002d │ │ + bhi.n 151b56 │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r8, r0 │ │ ldrd r6, r0, [r0, #4] │ │ mov r4, r1 │ │ @@ -253387,15 +253387,15 @@ │ │ bl 151d3c │ │ bl c71d0 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (151d48 ) │ │ add r0, pc │ │ bl a91f8 │ │ - pop {r0, r2, r5, r6, r7} │ │ + bvc.n 151e0e │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #12 │ │ mov r4, r0 │ │ ldrd fp, r0, [r0, #4] │ │ mov sl, r1 │ │ @@ -253543,15 +253543,15 @@ │ │ bl 151f08 │ │ bl c71d0 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (151f14 ) │ │ add r0, pc │ │ bl a91f8 │ │ - cbnz r1, 151f5e │ │ + bpl.n 151e42 │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r8, r0 │ │ ldrd r6, r0, [r0, #4] │ │ mov r4, r1 │ │ @@ -253666,15 +253666,15 @@ │ │ bl c71d0 │ │ bmi.n 152016 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (152078 ) │ │ add r0, pc │ │ bl a91f8 │ │ - cbnz r5, 1520a8 │ │ + bmi.n 1520de │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r8, r0 │ │ ldrd r5, r0, [r0, #4] │ │ mov r4, r1 │ │ @@ -253777,15 +253777,15 @@ │ │ bl 1521b0 │ │ bl c71d0 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (1521bc ) │ │ add r0, pc │ │ bl a91f8 │ │ - @ instruction: 0xb871 │ │ + bcs.n 15219a │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r8, r0 │ │ ldrd r5, r0, [r0, #4] │ │ mov r4, r1 │ │ @@ -253890,15 +253890,15 @@ │ │ bl 1522f8 │ │ bl c71d0 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (152304 ) │ │ add r0, pc │ │ bl a91f8 │ │ - @ instruction: 0xb729 │ │ + bne.n 152252 │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r8, r0 │ │ ldrd r5, r0, [r0, #4] │ │ mov r4, r1 │ │ @@ -254010,15 +254010,15 @@ │ │ bl c71d0 │ │ bmi.n 152402 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (152464 ) │ │ add r0, pc │ │ bl a91f8 │ │ - push {r0, r3, r6, r7, lr} │ │ + beq.n 1524f2 │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r8, r0 │ │ ldrd r5, r0, [r0, #4] │ │ mov r9, r1 │ │ @@ -254098,15 +254098,15 @@ │ │ bl 152554 │ │ bl c71d0 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (152560 ) │ │ add r0, pc │ │ bl a91f8 │ │ - push {r0, r2, r3, r6, r7} │ │ + ldmia r7!, {r0, r3, r6} │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r8, r0 │ │ ldrd r5, r0, [r0, #4] │ │ mov r4, r1 │ │ @@ -254217,15 +254217,15 @@ │ │ bl 1526a8 │ │ bl c71d0 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (1526b4 ) │ │ add r0, pc │ │ bl a91f8 │ │ - cbz r1, 152716 │ │ + ldmia r5, {r0, r2, r4, r5, r6, r7} │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r8, r0 │ │ ldrd r5, r0, [r0, #4] │ │ mov r4, r1 │ │ @@ -254339,15 +254339,15 @@ │ │ bl c71d0 │ │ bmi.n 1527ae │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (152810 ) │ │ add r0, pc │ │ bl a91f8 │ │ - sxth r5, r3 │ │ + ldmia r4, {r0, r3, r4, r7} │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r4, r0 │ │ ldrd r5, r0, [r0, #4] │ │ mov r8, r1 │ │ @@ -254465,15 +254465,15 @@ │ │ bl 152958 │ │ bl c71d0 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (152964 ) │ │ add r0, pc │ │ bl a91f8 │ │ - sub sp, #292 @ 0x124 │ │ + ldmia r3!, {r0, r2, r6} │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r8, r0 │ │ ldrd r5, r0, [r0, #4] │ │ mov r4, r1 │ │ @@ -254591,15 +254591,15 @@ │ │ bl c71d0 │ │ bmi.n 152a66 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (152ac8 ) │ │ add r0, pc │ │ bl a91f8 │ │ - add r7, sp, #404 @ 0x194 │ │ + ldmia r1!, {r0, r5, r6, r7} │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r4, r0 │ │ ldrd r5, r0, [r0, #4] │ │ mov r8, r1 │ │ @@ -254726,15 +254726,15 @@ │ │ bl c71d0 │ │ bmi.n 152bd6 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (152c38 ) │ │ add r0, pc │ │ bl a91f8 │ │ - add r5, sp, #980 @ 0x3d4 │ │ + ldmia r0, {r0, r4, r5, r6} │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r8, r0 │ │ ldrd r5, r0, [r0, #4] │ │ mov r4, r1 │ │ @@ -254860,15 +254860,15 @@ │ │ bl c71d0 │ │ bmi.n 152d52 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (152db4 ) │ │ add r0, pc │ │ bl a91f8 │ │ - add r4, sp, #484 @ 0x1e4 │ │ + stmia r6!, {r0, r2, r4, r5, r6, r7} │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r8, r0 │ │ ldrd r5, r0, [r0, #4] │ │ mov r4, r1 │ │ @@ -254997,15 +254997,15 @@ │ │ bl 152f2c │ │ bl c71d0 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (152f38 ) │ │ add r0, pc │ │ bl a91f8 │ │ - add r2, sp, #980 @ 0x3d4 │ │ + stmia r5!, {r0, r4, r5, r6} │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r8, r0 │ │ ldrd r5, r0, [r0, #4] │ │ mov r9, r1 │ │ @@ -255101,15 +255101,15 @@ │ │ bl 153048 │ │ bl c71d0 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (153054 ) │ │ add r0, pc │ │ bl a91f8 │ │ - add r1, sp, #868 @ 0x364 │ │ + stmia r4!, {r0, r2, r4, r6} │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #36 @ 0x24 │ │ mov r8, r0 │ │ ldr r0, [pc, #236] @ (153154 ) │ │ mov r4, r8 │ │ @@ -255200,15 +255200,15 @@ │ │ add r7, sp, #536 @ 0x218 │ │ movs r6, r1 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (153168 ) │ │ add r0, pc │ │ bl a91f8 │ │ - add r0, sp, #788 @ 0x314 │ │ + stmia r3!, {r0, r6} │ │ vsli.64 , q0, #51 @ 0x33 │ │ add r7, sp, #8 │ │ ldrd lr, ip, [r7, #12] │ │ ldr r1, [r7, #20] │ │ cmp r3, lr │ │ beq.n 15322a │ │ sub.w r2, r1, #64 @ 0x40 │ │ @@ -255355,15 +255355,15 @@ │ │ bl 15330c │ │ bl c71d0 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (153318 ) │ │ add r0, pc │ │ bl a91f8 │ │ - add r7, pc, #84 @ (adr r7, 153370 ) │ │ + stmia r1!, {r0, r4, r7} │ │ vtbl.8 d22, {d3}, d10 │ │ str r2, [r0, #0] │ │ ldr r2, [r1, #4] │ │ str r2, [r0, #4] │ │ ldr r2, [r1, #8] │ │ str r2, [r0, #8] │ │ ldr r2, [r1, #12] │ │ @@ -255651,15 +255651,15 @@ │ │ bl 1536c0 │ │ bl c71d0 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (1536cc ) │ │ add r0, pc │ │ bl a91f8 │ │ - add r3, pc, #388 @ (adr r3, 153854 ) │ │ + pop {r0, r2, r3, r4, r6, r7, pc} │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #60 @ 0x3c │ │ str r0, [sp, #36] @ 0x24 │ │ mov r6, r1 │ │ ldr r1, [pc, #948] @ (153a94 ) │ │ @@ -258587,15 +258587,15 @@ │ │ sub.w r0, r7, #92 @ 0x5c │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #64 @ 0x40 │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldrh r2, [r0, #26] │ │ movs r6, r1 │ │ - adds r0, r4, #3 │ │ + adds r7, #92 @ 0x5c │ │ vqshl.u64 , q15, #51 @ 0x33 │ │ @ instruction: 0xfff4cad0 │ │ vsubl.u q15, d19, d15 │ │ vqshrun.s64 d23, q7, #14 │ │ @ instruction: 0xfff4caf0 │ │ vtbx.8 d24, {d3}, d12 │ │ movs r6, r1 │ │ @@ -259398,24 +259398,24 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ add r0, sp, #128 @ 0x80 │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strh r6, [r3, #58] @ 0x3a │ │ movs r6, r1 │ │ beq.n 1561ba │ │ - vqrdmulh.s q9, , d24[0] │ │ + @ instruction: 0xfff347e4 │ │ vrshr.u64 d28, d22, #13 │ │ vtbx.8 d31, {d19}, d25 │ │ - @ instruction: 0xfff22d24 │ │ + vabdl.u q10, d18, d16 │ │ vrshr.u32 q14, q9, #13 │ │ vsubw.u q15, , d21 │ │ - vqrdmulh.s q9, , d6[0] │ │ + @ instruction: 0xfff347c2 │ │ vrshr.u64 d28, d4, #13 │ │ vrsubhn.i d31, , │ │ - @ instruction: 0xfff32d8a │ │ + vtbl.8 d20, {d3}, d6 │ │ vrshr.u64 q14, q4, #13 │ │ vshr.u32 q12, q14, #13 │ │ movs r6, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #12 │ │ @@ -260812,26 +260812,26 @@ │ │ movs r0, r0 │ │ movs r2, r0 │ │ movs r0, r0 │ │ movs r3, r0 │ │ movs r0, r0 │ │ strb r6, [r5, #20] │ │ movs r6, r1 │ │ - strb r4, [r1, #6] │ │ - vrsubhn.i d21, , q9 │ │ - vrshr.u32 d17, d3, #13 │ │ + ldrh r0, [r1, #32] │ │ + vshr.u64 d23, d14, #13 │ │ + vmull.u q9, d19, d15 │ │ vtbl.8 d25, {d3-d4}, d7 │ │ - vrsubhn.i d21, , q1 │ │ - vsra.u64 , , #13 │ │ - vrshr.u64 d17, d29, #13 │ │ - vmlsl.u , d3, d2[0] │ │ - vrshr.u32 d17, d19, #13 │ │ + vshr.u32 , q15, #13 │ │ + vdup.8 q9, d31[1] │ │ + vcvt.u16.f16 d18, d25, #13 │ │ + vshr.u64 d23, d30, #13 │ │ + vmull.u q9, d19, d31 │ │ vsri.32 d27, d4, #13 │ │ - @ instruction: 0xfff355e2 │ │ - vsra.u64 , , #13 │ │ + vshr.u32 , q7, #13 │ │ + vdup.8 q9, d15[1] │ │ vshr.u64 , q10, #13 │ │ movs r6, r1 │ │ │ │ 00157108 : │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #24 │ │ @@ -261240,18 +261240,18 @@ │ │ nop │ │ movs r6, #182 @ 0xb6 │ │ movs r6, r1 │ │ ldr r4, [r3, #108] @ 0x6c │ │ movs r6, r1 │ │ ldrsh r5, [r3, r2] │ │ @ instruction: 0xfff45efa │ │ - vqshlu.s64 , q8, #52 @ 0x34 │ │ + vrev16.16 , q14 │ │ vqrdmlsh.s q14, , d11[0] │ │ vcvt.f16.u16 , q3, #13 │ │ - vcls.s16 , q6 │ │ + vqrdmlah.s q10, q10, d8[0] │ │ vrsubhn.i d18, , q11 │ │ movs r6, r1 │ │ ldr r4, [r2, #64] @ 0x40 │ │ movs r6, r1 │ │ │ │ 00157568 *, cv::Point_*, cv::_InputArray const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -261748,16 +261748,16 @@ │ │ add r0, sp, #40 @ 0x28 │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r0, [r2, #36] @ 0x24 │ │ movs r6, r1 │ │ udf #73 @ 0x49 │ │ @ instruction: 0xfff3eb75 │ │ - vcvt.u32.f32 d18, d22, #13 │ │ - vdup.8 q10, d0[1] │ │ + @ instruction: 0xfff349b2 │ │ + vqshlu.s64 d22, d28, #51 @ 0x33 │ │ @ instruction: 0xfff3eb5a │ │ vcvt.u32.f32 d24, d20, #13 │ │ vqshlu.s64 q11, q15, #51 @ 0x33 │ │ movs r6, r1 │ │ │ │ 00157a94 : │ │ mov ip, r2 │ │ @@ -265451,21 +265451,21 @@ │ │ add r0, sp, #48 @ 0x30 │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ @ instruction: 0x47a2 │ │ movs r6, r1 │ │ asrs r2, r0, #15 │ │ - vtbx.8 d17, {d4}, d7 │ │ + vpaddl.u16 , │ │ vrsra.u32 d29, d29, #13 │ │ - vsli.64 d29, d24, #51 @ 0x33 │ │ - vtbl.8 d17, {d2}, d21 │ │ + vshr.u32 d31, d20, #13 │ │ + vqmovn.s16 d19, │ │ vrsra.u32 d29, d11, #13 │ │ vsri.64 d26, d7, #13 │ │ - vtbl.8 d17, {d3}, d3 │ │ + vrshr.u32 , , #13 │ │ vrshr.u64 , , #13 │ │ vtbl.8 d31, {d3-d4}, d10 │ │ movs r5, r1 │ │ adcs r2, r1 │ │ movs r6, r1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ @@ -266436,26 +266436,26 @@ │ │ nop │ │ movs r0, r0 │ │ movs r0, r0 │ │ subs r6, #38 @ 0x26 │ │ movs r6, r1 │ │ cdp 0, 10, cr0, cr6, cr13, {0} │ │ add r5, sp, #740 @ 0x2e4 │ │ - vqrdmulh.s q8, , d3[0] │ │ + vqshl.u64 d18, d31, #51 @ 0x33 │ │ vqshrun.s64 d28, , #13 │ │ vabdl.u , d3, d18 │ │ movs r6, r1 │ │ ldr r4, [r7, #44] @ 0x2c │ │ - @ instruction: 0xfff30d21 │ │ + vqshl.u64 d18, d13, #51 @ 0x33 │ │ vqshrun.s64 d28, , #13 │ │ - @ instruction: 0xfff3ca92 │ │ - @ instruction: 0xfff20cff │ │ + vabal.u q15, d3, d14 │ │ + vqshl.u32 q9, , #18 │ │ vqshl.u64 q14, , #51 @ 0x33 │ │ vqrshrn.u64 d25, , #13 │ │ - @ instruction: 0xfff30cdd │ │ + vqshl.u32 q9, , #19 │ │ vqshl.u64 q14, , #51 @ 0x33 │ │ vcvt.f32.u32 d30, d16, #13 │ │ movs r5, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ ldrd lr, ip, [r7, #8] │ │ @@ -266740,16 +266740,16 @@ │ │ movs r0, r0 │ │ movs r0, r0 │ │ movs r0, r0 │ │ subs r4, #176 @ 0xb0 │ │ @ instruction: 0xeb3a000d │ │ adds r2, #106 @ 0x6a │ │ movs r6, r1 │ │ - adds r2, #146 @ 0x92 │ │ - @ instruction: 0xfff32360 │ │ + ldr r5, [pc, #56] @ (15af8c ) │ │ + @ instruction: 0xfff33ddc │ │ vrsra.u64 q14, , #13 │ │ vsra.u64 , q3, #13 │ │ movs r6, r1 │ │ │ │ 0015af60 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -266953,15 +266953,15 @@ │ │ movs r0, r0 │ │ movs r0, r0 │ │ movs r0, r0 │ │ subs r4, #176 @ 0xb0 │ │ ands.w r0, r0, sp │ │ adds r1, #44 @ 0x2c │ │ movs r6, r1 │ │ - movs r0, #143 @ 0x8f │ │ + subs r3, #11 │ │ vqshlu.s64 , , #51 @ 0x33 │ │ vsra.u64 d28, d5, #13 │ │ @ instruction: 0xfff32f8a │ │ movs r6, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ @@ -270154,15 +270154,15 @@ │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ lsrs r4, r1, #16 │ │ movs r6, r1 │ │ lsls r4, r0, #24 │ │ vabal.u , d4, d14 │ │ - vtbx.8 d28, {d19}, d9 │ │ + @ instruction: 0xfff3e345 │ │ Address 0x15d516 is out of bounds. │ │ │ │ │ │ 0015d518 : │ │ movs r1, #0 │ │ str r1, [r0, #0] │ │ bx lr │ │ @@ -272146,16 +272146,16 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ cdp2 0, 1, cr0, cr12, cr13, {0} │ │ strh r1, [r2, #30] │ │ - vcvt.u32.f32 d30, d1, #14 │ │ - vtrn.8 , q9 │ │ + vtbl.8 d16, {d18-d19}, d13 │ │ + vmla.i , , d18[0] │ │ vqrdmulh.s , , d30[0] │ │ movs r5, r1 │ │ │ │ 0015e39c : │ │ bx lr │ │ bmi.n 15e34a │ │ │ │ @@ -272287,15 +272287,15 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldc2l 0, cr0, [r8], #52 @ 0x34 │ │ adds r7, #73 @ 0x49 │ │ vqrshrun.s64 d26, q12, #14 │ │ @ instruction: 0xfff3cf82 │ │ - vcvt.f32.u32 d25, d26, #13 │ │ + @ instruction: 0xfff3b8b6 │ │ @ instruction: 0xfff2a89c │ │ @ instruction: 0xfff3cfa6 │ │ vcvt.f16.u16 d31, d26, #13 │ │ movs r5, r1 │ │ │ │ 0015e508 : │ │ bx lr │ │ @@ -272426,19 +272426,19 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ smull r0, r0, ip, sp │ │ - bcc.n 15e71e │ │ - vcvt.u16.f16 d25, d15, #14 │ │ + ldcl 15, cr15, [sp, #968] @ 0x3c8 │ │ + @ instruction: 0xb79b │ │ vcvt.f32.u32 d28, d28, #14 │ │ @ instruction: 0xfff373ec │ │ - @ instruction: 0xfff29cfb │ │ + vqshl.u32 , , #18 │ │ vcvt.f32.u32 d28, d8, #14 │ │ vtbx.8 d31, {d19-d21}, d12 │ │ movs r5, r1 │ │ │ │ 0015e674 : │ │ bx lr │ │ │ │ @@ -272565,15 +272565,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldr??.w r0, [r8, sp] │ │ bl 18d78a │ │ - @ instruction: 0xb6b4 │ │ + bne.n 15e808 │ │ @ instruction: 0xfff2ccf0 │ │ Address 0x15e7aa is out of bounds. │ │ │ │ │ │ 0015e7ac : │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -273245,16 +273245,16 @@ │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ mov r0, sl │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r6, sp, #504 @ 0x1f8 │ │ movs r5, r1 │ │ @ instruction: 0xf3d4000d │ │ - b.n 15f36e │ │ - @ instruction: 0xfff22896 │ │ + stc2 15, cr15, [r9, #-968] @ 0xfffffc38 │ │ + cmp r0, #150 @ 0x96 │ │ vcvt.f32.u32 d18, d3, #13 │ │ @ instruction: 0xfff25bd2 │ │ @ instruction: 0xfff30169 │ │ movs r0, r0 │ │ lsls r1, r2, #6 │ │ movs r0, r0 │ │ lsls r1, r4, #6 │ │ @@ -273911,15 +273911,15 @@ │ │ mov r0, r4 │ │ add sp, #28 │ │ ldmia.w sp!, {r8, r9, sl, fp} │ │ pop {r4, r5, r6, r7, pc} │ │ strb.w sl, [r5, #12]! │ │ b.n 15f4b0 │ │ nop │ │ - ldr r1, [sp, #860] @ 0x35c │ │ + push {r0, r1, r4, r6} │ │ vtbx.8 d25, {d2-d3}, d29 │ │ vaddw.u q9, , d0 │ │ str r1, [r0, #108] @ 0x6c │ │ bx lr │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ @@ -274069,15 +274069,15 @@ │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 230610 <__emutls_get_address@@Base+0x3788> │ │ mov r0, r4 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ eors.w r0, r8, sp │ │ - ldr r6, [sp, #932] @ 0x3a4 │ │ + cbnz r5, 15f6d0 │ │ vshll.u32 q15, d10, #18 │ │ movs r5, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #100 @ 0x64 │ │ mov r9, r0 │ │ @@ -274640,15 +274640,15 @@ │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ b.n 15f690 │ │ movs r5, r1 │ │ lsrs r6, r7, #9 │ │ movs r6, r1 │ │ - add r2, pc, #292 @ (adr r2, 15fdbc ) │ │ + pop {r0, r2, r6, r7} │ │ vcvt.f32.u32 d20, d30, #14 │ │ vmls.i q15, q1, d14[0] │ │ movs r5, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #100 @ 0x64 │ │ @@ -274854,15 +274854,15 @@ │ │ mov r0, r6 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ b.n 1603e4 │ │ movs r5, r1 │ │ lsls r4, r0 │ │ - @ instruction: 0xfff38fff │ │ + @ instruction: 0xfff3aa7b │ │ vrshr.u32 d30, d2, #14 │ │ movs r5, r1 │ │ │ │ 0015fec8 : │ │ movs r0, #0 │ │ bx lr │ │ │ │ @@ -274905,16 +274905,16 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ b.n 1602c8 │ │ movs r5, r1 │ │ push {r5, r6, r7, lr} │ │ - vtbl.8 d26, {d19-d21}, d10 │ │ - vqmovn.s16 d30, │ │ + vabal.u q14, d3, d6 │ │ + @ instruction: 0xfff2fd25 │ │ Address 0x15ff32 is out of bounds. │ │ │ │ │ │ 0015ff34 : │ │ udf #254 @ 0xfe │ │ bmi.n 15fee2 │ │ │ │ @@ -276049,21 +276049,21 @@ │ │ bhi.n 160a1c │ │ movs r5, r1 │ │ bhi.n 160ac4 │ │ movs r5, r1 │ │ bhi.n 1609c4 │ │ movs r5, r1 │ │ strh r2, [r0, #36] @ 0x24 │ │ - vtbl.8 d28, {d19-d20}, d25 │ │ + vraddhn.i d30, , │ │ vabdl.u , d2, d30 │ │ movs r5, r1 │ │ bhi.n 160b00 │ │ movs r5, r1 │ │ add r3, sp, #668 @ 0x29c │ │ - @ instruction: 0xfff3c8fd │ │ + vrsra.u32 q15, , #13 │ │ vmlsl.u , d18, d6[0] │ │ movs r5, r1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #52] @ (160aa8 ) │ │ mov r5, r4 │ │ @@ -277727,15 +277727,15 @@ │ │ @ instruction: 0xfff3c340 │ │ vabdl.u q14, d19, d28 │ │ movs r5, r1 │ │ stmia r7!, {r1, r3, r5, r7} │ │ movs r5, r1 │ │ stmia r7!, {r3, r5, r7} │ │ movs r5, r1 │ │ - ldr r4, [r7, #28] │ │ + strh r0, [r7, #34] @ 0x22 │ │ vabdl.u q14, d18, d16 │ │ movs r5, r1 │ │ ldr r5, [r2, r7] │ │ @ instruction: 0xfff3efff │ │ vabal.u q9, d18, d9 │ │ vraddhn.i d22, , q11 │ │ vmls.i q9, , d16[0] │ │ @@ -277954,15 +277954,15 @@ │ │ ldrne.w r0, [r1, #-4] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ cmp r4, sl │ │ mov r1, r4 │ │ bne.n 161df2 │ │ ldr r0, [sp, #248] @ 0xf8 │ │ b.n 161ae4 │ │ - strb r5, [r0, #10] │ │ + ldrh r1, [r0, #40] @ 0x28 │ │ vqrdmulh.s q15, q9, d7[0] │ │ vqmovun.s16 d18, q3 │ │ vmla.i , , d14[0] │ │ vext.8 d4, d2, d6, #6 │ │ cbz r0, 161e28 │ │ ldr r0, [r6, #4] │ │ cmp r0, #5 │ │ @@ -278700,16 +278700,16 @@ │ │ ldrb.w r0, [sp, #344] @ 0x158 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #352] @ 0x160 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ - ite ne │ │ - vqshlne.u32 d18, d26, #18 │ │ + bls.n 1624f0 │ │ + vqshl.u32 d18, d26, #18 │ │ @ instruction: 0xfff21b5c │ │ @ instruction: 0xfff325e7 │ │ @ instruction: 0xfff3bcd6 │ │ movs r5, r1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ ldr r5, [r0, #4] │ │ @@ -280198,16 +280198,16 @@ │ │ blx 2307d0 <__emutls_get_address@@Base+0x3948> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ b.n 162da0 , std::__ndk1::allocator > const&, bool)@@Base+0x3e4> │ │ movs r5, r1 │ │ add r3, sp, #928 @ 0x3a0 │ │ movs r5, r1 │ │ - ldr r2, [r2, r6] │ │ - vshr.u32 d22, d13, #14 │ │ + strb r6, [r1, #16] │ │ + @ instruction: 0xfff27a99 │ │ vtbx.8 d26, {d18-d21}, d22 │ │ movs r5, r1 │ │ movs r1, #40 @ 0x28 │ │ movs r5, r1 │ │ add r3, sp, #840 @ 0x348 │ │ movs r5, r1 │ │ push {r4, r5, r6, r7, lr} │ │ @@ -280830,22 +280830,22 @@ │ │ blx 230de0 <__emutls_get_address@@Base+0x3f58> │ │ b.n 163c84 , std::__ndk1::allocator > const&, bool)@@Base+0x12c8> │ │ b.n 163c62 , std::__ndk1::allocator > const&, bool)@@Base+0x12a6> │ │ b.n 163c80 , std::__ndk1::allocator > const&, bool)@@Base+0x12c4> │ │ b.n 163c74 , std::__ndk1::allocator > const&, bool)@@Base+0x12b8> │ │ b.n 163c62 , std::__ndk1::allocator > const&, bool)@@Base+0x12a6> │ │ nop │ │ - add r2, sp, #204 @ 0xcc │ │ - vtbl.8 d25, {d2-d4}, d15 │ │ + stmia r4!, {r0, r1, r2, r3, r5, r7} │ │ + vraddhn.i d27, q9, │ │ @ instruction: 0xfff2e740 │ │ vtrn.8 d17, d22 │ │ vqshl.u64 q13, q14, #51 @ 0x33 │ │ movs r5, r1 │ │ cmp r5, #231 @ 0xe7 │ │ - vtbx.8 d25, {d18}, d5 │ │ + @ instruction: 0xfff2b341 │ │ vsli.64 q15, q11, #50 @ 0x32 │ │ vcvt.u32.f32 q8, q7, #14 │ │ vqshlu.s64 d26, d18, #51 @ 0x33 │ │ movs r5, r1 │ │ cmp r3, #52 @ 0x34 │ │ vqrdmlah.s q8, , d0[0] │ │ vsli.64 d26, d4, #51 @ 0x33 │ │ @@ -281229,15 +281229,15 @@ │ │ add r0, pc │ │ blx 2307d0 <__emutls_get_address@@Base+0x3948> │ │ b.n 164062 , std::__ndk1::allocator > const&, bool)@@Base+0x16a6> │ │ nop │ │ add r4, pc, #640 @ (adr r4, 164294 , std::__ndk1::allocator > const&, bool)@@Base+0x18d8>) │ │ movs r5, r1 │ │ str r2, [r4, r3] │ │ - @ instruction: 0xfff339b6 │ │ + vsri.32 d21, d18, #13 │ │ vcvt.f16.u16 q8, q0, #14 │ │ @ instruction: 0xfff3f89d │ │ lsls r0, r1, #1 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #80] @ 0x50 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ @@ -281309,17 +281309,17 @@ │ │ movs r5, r1 │ │ bhi.n 164088 , std::__ndk1::allocator > const&, bool)@@Base+0x16cc> │ │ movs r5, r1 │ │ add r0, pc, #344 @ (adr r0, 164230 , std::__ndk1::allocator > const&, bool)@@Base+0x1874>) │ │ movs r5, r1 │ │ add r0, pc, #992 @ (adr r0, 1644bc , std::__ndk1::allocator > const&, bool)@@Base+0x1b00>) │ │ movs r5, r1 │ │ - ldrb r4, [r4, #9] │ │ + str r4, [sp, #896] @ 0x380 │ │ vswp , q9 │ │ - vqshrn.u64 d19, q3, #13 │ │ + vrsra.u64 d21, d2, #13 │ │ vtbx.8 d16, {d18-d21}, d26 │ │ vtbl.8 d16, {d3-d5}, d14 │ │ vsra.u32 q13, q7, #13 │ │ movs r5, r1 │ │ bl 4410dc <__cxa_new_handler@@Base+0x1fd4ec> │ │ lsrs r0, r2, #11 │ │ vsli.64 , q8, #51 @ 0x33 │ │ @@ -281659,22 +281659,22 @@ │ │ movs r5, r1 │ │ ldr r7, [sp, #288] @ 0x120 │ │ movs r5, r1 │ │ ldr r7, [sp, #280] @ 0x118 │ │ movs r5, r1 │ │ ldr r7, [sp, #272] @ 0x110 │ │ movs r5, r1 │ │ - add r0, pc, #700 @ (adr r0, 164760 , std::__ndk1::allocator > const&, bool)@@Base+0x1da4>) │ │ + cbnz r3, 1644ee , std::__ndk1::allocator > const&, bool)@@Base+0x1b32> │ │ vcvt.u32.f32 d25, d28, #14 │ │ movs r5, r1 │ │ movs r3, #172 @ 0xac │ │ vqrdmlah.s q15, , d2[0] │ │ - @ instruction: 0xfff25b96 │ │ - vqmovn.s16 d19, q13 │ │ - vtbx.8 d21, {d2-d4}, d8 │ │ + vqshlu.s32 d23, d2, #18 │ │ + @ instruction: 0xfff24d26 │ │ + vmls.i , q9, d4[0] │ │ @ instruction: 0xfff28c92 │ │ vaddw.u , , d9 │ │ lsrs r1, r0, #4 │ │ str r4, [r6, #0] │ │ ldr.w fp, [sp, #68] @ 0x44 │ │ ldr r0, [sp, #64] @ 0x40 │ │ add.w sl, sl, #1 │ │ @@ -282118,19 +282118,19 @@ │ │ beq.n 1649b0 , std::__ndk1::allocator > const&, bool)@@Base+0x1ff4> │ │ add r0, sp, #96 @ 0x60 │ │ mov r1, r4 │ │ bl 164d94 , std::__ndk1::allocator > const&, bool)@@Base+0x23d8> │ │ ldrb.w r0, [sp, #96] @ 0x60 │ │ b.n 1649c2 , std::__ndk1::allocator > const&, bool)@@Base+0x2006> │ │ nop │ │ - str r1, [r3, #56] @ 0x38 │ │ - vqshl.u64 , q5, #50 @ 0x32 │ │ + ldrb r5, [r2, #24] │ │ + vrshr.u32 , q3, #14 │ │ vrshr.u64 d17, d0, #14 │ │ vqshrn.u64 d30, q2, #14 │ │ - @ instruction: 0xfff255e4 │ │ + vswp , q8 │ │ @ instruction: 0xfff20fb7 │ │ movs r0, r0 │ │ bl 3d998e <__cxa_new_handler@@Base+0x195d9e> │ │ asrs r4, r3, #4 │ │ vmlsl.u , d2, d2[0] │ │ strb r6, [r1, #1] │ │ movt r0, #65 @ 0x41 │ │ @@ -282452,23 +282452,23 @@ │ │ bl 16587e , std::__ndk1::allocator > const&, bool)@@Base+0x2ec2> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldr r7, [sp, #584] @ 0x248 │ │ movs r5, r1 │ │ bne.n 164cde , std::__ndk1::allocator > const&, bool)@@Base+0x2322> │ │ vcle.s8 , , #0 │ │ - @ instruction: 0xfff16e9a │ │ - @ instruction: 0xfff26e8c │ │ + vqshrn.u64 d24, q3, #15 │ │ + vtbl.8 d24, {d2-d3}, d8 │ │ vtbx.8 d22, {d2-d4}, d8 │ │ vshll.u32 q11, d26, #19 │ │ @ instruction: 0xfff30d0b │ │ movs r0, r0 │ │ lsrs r2, r3, #11 │ │ movs r5, r1 │ │ - strb r0, [r5, r0] │ │ + ldr r4, [r4, #104] @ 0x68 │ │ vmlsl.u , d2, d2[0] │ │ movs r5, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ ldr r6, [r0, #0] │ │ mov r8, r0 │ │ @@ -283054,15 +283054,15 @@ │ │ movs r5, r1 │ │ str r0, [sp, #1008] @ 0x3f0 │ │ movs r5, r1 │ │ str r0, [sp, #1000] @ 0x3e8 │ │ movs r5, r1 │ │ lsrs r6, r5, #10 │ │ @ instruction: 0xfff2f997 │ │ - vcvt.u16.f16 q10, q13, #14 │ │ + vqshl.u64 q11, q11, #50 @ 0x32 │ │ vqrdmlsh.s q12, q9, d28[0] │ │ movs r5, r1 │ │ bne.n 165326 , std::__ndk1::allocator > const&, bool)@@Base+0x296a> │ │ @ instruction: 0xfff2f740 │ │ vtrn.8 , │ │ stc 8, cr15, [ip, #-884] @ 0xfffffc8c │ │ add r0, pc, #256 @ (adr r0, 16546c , std::__ndk1::allocator > const&, bool)@@Base+0x2ab0>) │ │ @@ -283406,16 +283406,16 @@ │ │ adds r1, r0, #4 │ │ add r0, sp, #104 @ 0x68 │ │ blx 230dd0 <__emutls_get_address@@Base+0x3f48> │ │ ldr r0, [sp, #52] @ 0x34 │ │ blx 230de0 <__emutls_get_address@@Base+0x3f58> │ │ b.n 16516a , std::__ndk1::allocator > const&, bool)@@Base+0x27ae> │ │ subs r3, r2, #6 │ │ - vqshlu.s32 q12, , #19 │ │ - vshll.u32 q10, d2, #18 │ │ + vshr.u64 q13, , #13 │ │ + vraddhn.i d22, q9, q7 │ │ vmull.u q12, d18, d4 │ │ movs r5, r1 │ │ ldr r2, [pc, #648] @ (1659c0 , std::__ndk1::allocator > const&, bool)@@Base+0x3004>) │ │ movs r5, r1 │ │ ldr r2, [pc, #472] @ (165914 , std::__ndk1::allocator > const&, bool)@@Base+0x2f58>) │ │ movs r5, r1 │ │ mov r4, r0 │ │ @@ -283534,15 +283534,15 @@ │ │ movs r5, r1 │ │ ldrh r2, [r6, #8] │ │ movs r5, r1 │ │ ldrh r4, [r5, #8] │ │ movs r5, r1 │ │ ldrh r2, [r7, #6] │ │ movs r5, r1 │ │ - bx ip │ │ + str r2, [r4, #28] │ │ @ instruction: 0xfff289d8 │ │ movs r5, r1 │ │ ldr r2, [r0, #0] │ │ movs r0, #0 │ │ ldr r1, [r1, #0] │ │ cmp r2, r1 │ │ it gt │ │ @@ -283764,15 +283764,15 @@ │ │ ldmia.w sp!, {r8, r9, fp} │ │ pop {r4, r5, r6, r7, pc} │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (165ac8 , std::__ndk1::allocator > const&, bool)@@Base+0x310c>) │ │ add r0, pc │ │ bl a91f8 │ │ - ldrb r5, [r4, #29] │ │ + ldr r1, [sp, #900] @ 0x384 │ │ vsli.64 , q8, #50 @ 0x32 │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ mov r8, r0 │ │ ldrb r0, [r0, #12] │ │ cbz r0, 165ae2 , std::__ndk1::allocator > const&, bool)@@Base+0x3126> │ │ mov r0, r8 │ │ @@ -289911,17 +289911,17 @@ │ │ movs r5, r1 │ │ ldr r0, [pc, #872] @ (169ebc , std::__ndk1::allocator > const&, bool)@@Base+0x7500>) │ │ movs r5, r1 │ │ adds r3, r2, #4 │ │ vtbl.8 d20, {d19}, d10 │ │ movs r5, r1 │ │ ldrh r5, [r5, #34] @ 0x22 │ │ - vsra.u64 q10, , #14 │ │ + vdup.16 , d15[0] │ │ vqshlu.s32 d26, d0, #18 │ │ - @ instruction: 0xfff2ddd5 │ │ + vqrshrun.s64 d31, , #14 │ │ vqshl.u64 q10, q15, #49 @ 0x31 │ │ movs r5, r1 │ │ @ instruction: 0x479a │ │ movs r5, r1 │ │ blx r3 │ │ movs r5, r1 │ │ subs r2, r3, r7 │ │ @@ -290106,33 +290106,33 @@ │ │ movs r5, r1 │ │ cmp r6, r7 │ │ movs r5, r1 │ │ add r6, sp, #428 @ 0x1ac │ │ vcge.f8 q10, q11, #0 │ │ movs r5, r1 │ │ add r2, pc, #296 @ (adr r2, 169e88 , std::__ndk1::allocator > const&, bool)@@Base+0x74cc>) │ │ - vtbl.8 d29, {d2-d4}, d15 │ │ + vraddhn.i d31, q9, │ │ vsri.32 d20, d18, #15 │ │ movs r5, r1 │ │ mvns r6, r2 │ │ movs r5, r1 │ │ - eors r7, r7 │ │ + ldrh r3, [r7, r3] │ │ vsri.64 d26, d24, #14 │ │ - vcvt.f16.u16 , , #14 │ │ + vqshlu.s64 , , #50 @ 0x32 │ │ vrsubhn.i d20, , q7 │ │ movs r5, r1 │ │ mov ip, r1 │ │ movs r5, r1 │ │ strh r2, [r5, #14] │ │ vqshlu.s32 d20, d20, #17 │ │ movs r5, r1 │ │ ldrh r7, [r2, #16] │ │ vqrdmlsh.s , q9, d17[0] │ │ vneg.s8 d26, d8 │ │ - vtbx.8 d29, {d2-d5}, d13 │ │ + @ instruction: 0xfff2f5c9 │ │ vsli.64 , q8, #49 @ 0x31 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #204 @ 0xcc │ │ ldr.w r0, [pc, #2328] @ 16a6bc , std::__ndk1::allocator > const&, bool)@@Base+0x7d00> │ │ mov r9, r1 │ │ add r0, pc │ │ @@ -290537,32 +290537,32 @@ │ │ adds r1, r0, #4 │ │ add r0, sp, #56 @ 0x38 │ │ blx 230dd0 <__emutls_get_address@@Base+0x3f48> │ │ ldr r0, [sp, #40] @ 0x28 │ │ blx 230de0 <__emutls_get_address@@Base+0x3f58> │ │ movs r0, #1 │ │ b.n 16a4c4 , std::__ndk1::allocator > const&, bool)@@Base+0x7b08> │ │ - bhi.n 16a266 , std::__ndk1::allocator > const&, bool)@@Base+0x78aa> │ │ - vsubl.u q10, d17, d4 │ │ + bl 4181e6 <__cxa_new_handler@@Base+0x1d45f6> │ │ + cmp r4, r0 │ │ movs r5, r1 │ │ stmia r7!, {r4, r5, r7} │ │ vcvt.f32.u32 d23, d21, #14 │ │ vtbx.8 d16, {d17-d18}, d21 │ │ vqshrun.s64 d23, , #13 │ │ vtrn.8 q12, q7 │ │ @ instruction: 0xfff29f8a │ │ vmull.u , d18, d30 │ │ vsra.u32 q10, q10, #15 │ │ movs r5, r1 │ │ asrs r0, r4 │ │ movs r5, r1 │ │ asrs r0, r4 │ │ movs r5, r1 │ │ - mcr 15, 4, pc, cr14, cr1, {7} @ │ │ - lsrs r4, r1 │ │ + lsrs r2, r1, #4 │ │ + vtrn.8 q10, q6 │ │ movs r5, r1 │ │ ldrh r0, [r1, #6] │ │ @ instruction: 0xfff19e2a │ │ vtbx.8 d25, {d2-d5}, d14 │ │ vshr.u32 d20, d6, #15 │ │ movs r5, r1 │ │ subs r7, #210 @ 0xd2 │ │ @@ -290945,15 +290945,15 @@ │ │ blx 230de0 <__emutls_get_address@@Base+0x3f58> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ subs r6, #94 @ 0x5e │ │ movs r5, r1 │ │ subs r6, #92 @ 0x5c │ │ movs r5, r1 │ │ - lsls r3, r3, #27 │ │ + movs r1, #87 @ 0x57 │ │ @ instruction: 0xfff23e04 │ │ movs r5, r1 │ │ lsls r6, r6, #5 │ │ vaddl.u q15, d3, d23 │ │ b.n 16a6b0 , std::__ndk1::allocator > const&, bool)@@Base+0x7cf4> │ │ b.n 16a684 , std::__ndk1::allocator > const&, bool)@@Base+0x7cc8> │ │ b.n 16a694 , std::__ndk1::allocator > const&, bool)@@Base+0x7cd8> │ │ @@ -291250,15 +291250,15 @@ │ │ blx 232590 <__emutls_get_address@@Base+0x5708> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bl a8d68 │ │ subs r0, #90 @ 0x5a │ │ movs r5, r1 │ │ subs r0, #48 @ 0x30 │ │ movs r5, r1 │ │ - cmp r1, #223 @ 0xdf │ │ + add r3, fp │ │ vzip.8 d26, d16 │ │ vcle.f8 , q5, #0 │ │ @ instruction: 0xfff218f9 │ │ vsli.64 , q8, #51 @ 0x33 │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #24 │ │ @@ -291900,18 +291900,18 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ adds r5, #142 @ 0x8e │ │ movs r5, r1 │ │ ldrh r1, [r5, #36] @ 0x24 │ │ vneg.f8 d29, d13 │ │ - vshll.u32 q8, d19, #18 │ │ - vrsra.u64 , q6, #14 │ │ + vraddhn.i d18, q9, │ │ + vcvt.f32.u32 q15, q4, #14 │ │ vabs.f8 , │ │ - vshll.u32 q8, d3, #18 │ │ + vraddhn.i d18, q9, │ │ vuzp.8 , q15 │ │ movs r5, r1 │ │ │ │ 0016b03c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ @@ -292458,21 +292458,21 @@ │ │ add r0, sp, #460 @ 0x1cc │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ cmp r7, #240 @ 0xf0 │ │ movs r5, r1 │ │ strh r1, [r2, #54] @ 0x36 │ │ vsra.u64 d29, d21, #15 │ │ - vsri.32 q8, , #14 │ │ + @ instruction: 0xfff21ed7 │ │ vsri.64 d21, d18, #14 │ │ vsra.u64 d29, d5, #14 │ │ - vsri.32 d16, d27, #14 │ │ - vqrdmulh.s q14, q9, d20[0] │ │ + @ instruction: 0xfff21eb7 │ │ + vtbx.8 d30, {d2}, d16 │ │ vsra.u32 , , #15 │ │ - vsri.32 d16, d11, #14 │ │ + @ instruction: 0xfff21e97 │ │ @ instruction: 0xfff22b9e │ │ movs r5, r1 │ │ │ │ 0016b644 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -292703,17 +292703,17 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ cmp r2, #84 @ 0x54 │ │ movs r5, r1 │ │ - cmp r2, #148 @ 0x94 │ │ + cmp r0, r2 │ │ vabal.u , d2, d16 │ │ - vzip.8 d16, d15 │ │ + vdup.16 d17, d11[0] │ │ @ instruction: 0xfff20e84 │ │ @ instruction: 0xfff34764 │ │ vtrn.8 d16, d27 │ │ vqrdmlah.s q8, , d16[0] │ │ @ instruction: 0xfff34740 │ │ vtrn.8 d16, d7 │ │ vcvt.f32.u32 d16, d28, #13 │ │ @@ -292869,22 +292869,22 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r0, [sp, #28] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ movs r7, #184 @ 0xb8 │ │ movs r5, r1 │ │ asrs r0, r1, #30 │ │ - @ instruction: 0xfff3bcb9 │ │ - @ instruction: 0xfff1ffa1 │ │ - vcle.f8 , q13, #0 │ │ + vqshl.u32 d29, d21, #19 │ │ + vshll.u32 , d13, #17 │ │ + vswp , q11 │ │ @ instruction: 0xfff1efb3 │ │ @ instruction: 0xfff2b994 │ │ - @ instruction: 0xfff2bc97 │ │ - vcvt.u32.f32 , , #15 │ │ - @ instruction: 0xfff11d8a │ │ + vqshl.u32 d29, d3, #18 │ │ + @ instruction: 0xfff119fb │ │ + @ instruction: 0xfff21d8a │ │ @ instruction: 0xfff3a141 │ │ vqshlu.s64 , q12, #49 @ 0x31 │ │ vqshlu.s64 q9, q5, #51 @ 0x33 │ │ movs r5, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -293291,16 +293291,16 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ movs r4, #38 @ 0x26 │ │ movs r5, r1 │ │ lsls r5, r6, #13 │ │ vmlal.u , d19, d30[0] │ │ - vtbl.8 d31, {d3-d6}, d7 │ │ - vrshr.u32 d18, d30, #15 │ │ + vabal.u , d19, d3 │ │ + vrshr.u32 d18, d30, #14 │ │ movs r5, r1 │ │ │ │ 0016bef4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #24 │ │ @@ -293523,18 +293523,18 @@ │ │ b.n 16c142 │ │ b.n 16c142 │ │ add r0, sp, #228 @ 0xe4 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ movs r1, #58 @ 0x3a │ │ movs r5, r1 │ │ - pli [r8, #241]! │ │ - bl ffe1413c <__cxa_new_handler@@Base+0xffbd054c> │ │ - pld [r9, #4081] @ 0xff1 │ │ - subs r0, r2, #7 │ │ + asrs r4, r2, #14 │ │ + vraddhn.i d31, q9, │ │ + vrsra.u32 d17, d5, #14 │ │ + @ instruction: 0xfff21fd0 │ │ movs r5, r1 │ │ │ │ 0016c160 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #24 │ │ @@ -294182,16 +294182,16 @@ │ │ itt eq │ │ moveq r1, #46 @ 0x2e │ │ strbeq r1, [r0, #0] │ │ mov r0, r4 │ │ add sp, #8 │ │ pop {r4, r6, r7, pc} │ │ nop │ │ - mrc2 15, 7, pc, cr9, cr1, {7} │ │ - add r4, sp, #176 @ 0xb0 │ │ + adds r5, r6, r5 │ │ + vdup.16 d26, d28[0] │ │ vshll.u32 q8, d2, #18 │ │ vrsra.u64 d24, d31, #13 │ │ vshll.u32 q8, d20, #17 │ │ vabal.u , d19, d0 │ │ mov r7, sp │ │ sub sp, #16 │ │ mov ip, r1 │ │ @@ -294429,27 +294429,27 @@ │ │ ldrne r0, [sp, #20] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ adds r4, r6, r0 │ │ movs r5, r1 │ │ str r0, [sp, #848] @ 0x350 │ │ - @ instruction: 0xfff1189c │ │ + vrsra.u32 d19, d8, #15 │ │ vabdl.u q11, d2, d24 │ │ @ instruction: 0xfff26a78 │ │ vsubl.u , d19, d6 │ │ - vtbl.8 d17, {d1-d2}, d2 │ │ + vrsra.u32 , q15, #15 │ │ vabdl.u q11, d18, d14 │ │ vqmovun.s16 d23, q1 │ │ - vqshrn.u64 d16, , #15 │ │ + vrsra.u64 d18, d3, #15 │ │ @ instruction: 0xfff2674a │ │ vqshl.u32 d17, d20, #18 │ │ movs r5, r1 │ │ ldr r5, [pc, #776] @ (16cd68 ) │ │ - vtbx.8 d17, {d18}, d16 │ │ + vrsra.u32 , q6, #14 │ │ @ instruction: 0xfff2676c │ │ vsli.64 , q8, #50 @ 0x32 │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub.w sp, sp, #520 @ 0x208 │ │ mov r8, r1 │ │ ldr r1, [pc, #172] @ (16cb24 ) │ │ @@ -294661,15 +294661,15 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ asrs r0, r5, #21 │ │ movs r5, r1 │ │ asrs r4, r4, #17 │ │ movs r5, r1 │ │ ldr r3, [sp, #124] @ 0x7c │ │ - vclt.s8 , , #0 │ │ + vqdmulh.s q15, , d5[0] │ │ vsri.64 d22, d16, #15 │ │ vsli.64 , q0, #50 @ 0x32 │ │ add r7, sp, #8 │ │ sub.w sp, sp, #536 @ 0x218 │ │ ldr r1, [pc, #120] @ (16cd38 ) │ │ movs r2, #128 @ 0x80 │ │ add r1, pc │ │ @@ -294718,15 +294718,15 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ asrs r0, r5, #15 │ │ movs r5, r1 │ │ add r6, pc, #744 @ (adr r6, 16d028 ) │ │ - vqshlu.s32 , q5, #18 │ │ + vshr.u64 , q3, #14 │ │ vsri.32 d22, d8, #15 │ │ @ instruction: 0xfff213c8 │ │ movs r5, r1 │ │ │ │ 0016cd4c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -295435,16 +295435,16 @@ │ │ blx r2 │ │ b.n 16d2e2 │ │ bl a8d68 │ │ bl a8d68 │ │ nop │ │ lsrs r0, r5, #26 │ │ movs r5, r1 │ │ - ldmia r1!, {r2, r3, r5, r6, r7} │ │ - vsli.64 d30, d31, #49 @ 0x31 │ │ + b.n 16cdd4 │ │ + vshr.u32 d16, d27, #15 │ │ Address 0x16d506 is out of bounds. │ │ │ │ │ │ 0016d508 , std::__ndk1::allocator >*)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -295586,16 +295586,16 @@ │ │ it eq │ │ beq.w 230414 <__emutls_get_address@@Base+0x358c> │ │ blx 230610 <__emutls_get_address@@Base+0x3788> │ │ mov r0, sp │ │ bl a91e8 │ │ lsrs r2, r2, #14 │ │ movs r5, r1 │ │ - ldmia r1!, {r4, r6} │ │ - vceq.f8 d30, d19, #0 │ │ + b.n 16de24 │ │ + @ instruction: 0xfff1ff9f │ │ vtbx.8 d16, {d1-d3}, d10 │ │ movs r5, r1 │ │ │ │ 0016d694 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ @@ -295784,22 +295784,22 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ lsrs r2, r6, #7 │ │ movs r5, r1 │ │ str r3, [r6, #124] @ 0x7c │ │ - @ instruction: 0xfff2b764 │ │ + vzip.8 , q8 │ │ vqshrn.u64 d21, q1, #15 │ │ - vrshr.u32 q15, q12, #14 │ │ - vabs.f8 , q0 │ │ + @ instruction: 0xfff2fcf4 │ │ + vsra.u64 d29, d28, #15 │ │ vtbx.8 d21, {d17}, d30 │ │ vsri.64 d28, d4, #14 │ │ vraddhn.i d22, q1, q12 │ │ - vabs.s8 d30, d2 │ │ + vcvt.u16.f16 , q15, #15 │ │ @ instruction: 0xfff108b8 │ │ movs r5, r1 │ │ │ │ 0016d8b4 , std::__ndk1::allocator > const&, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > >&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -296289,18 +296289,18 @@ │ │ b.n 16e2bc │ │ cmp.w fp, #40 @ 0x28 │ │ ldr.w fp, [sp, #24] │ │ itt ne │ │ addne.w r0, r5, #40 @ 0x28 │ │ strne.w r0, [r9, #104] @ 0x68 │ │ b.n 16e2bc │ │ - svc 21 │ │ - vneg.s8 d22, d20 │ │ + pli [r1, #4081] @ 0xff1 │ │ + str r4, [r4, #56] @ 0x38 │ │ @ instruction: 0xfff25547 │ │ - vqshl.u32 d26, d3, #18 │ │ + vzip.8 d28, d15 │ │ vcge.s8 , q1, #0 │ │ vorr.i32 d27, #8 @ 0x00000008 │ │ ldr r1, [r0, #4] │ │ cmp r1, #2 │ │ blt.w 16df6a │ │ str r0, [sp, #24] │ │ movs r5, #0 │ │ @@ -296647,27 +296647,27 @@ │ │ lsls r2, r1, #11 │ │ movs r5, r1 │ │ lsls r2, r1, #11 │ │ movs r5, r1 │ │ ldr r4, [r5, #64] @ 0x40 │ │ vrshr.u32 q8, q8, #14 │ │ movs r5, r1 │ │ - ldmia r3, {r0, r1, r3, r6} │ │ + b.n 16dd32 │ │ vqrdmlah.s q9, , d24[0] │ │ vcvt.u32.f32 d26, d25, #14 │ │ - @ instruction: 0xfff297e3 │ │ - vabs.f8 q15, q10 │ │ - vrshr.u32 d21, d6, #15 │ │ - vqshl.u64 d25, d12, #50 @ 0x32 │ │ + vrshr.u32 , , #14 │ │ + vcle.s8 q8, q8, #0 │ │ + vrshr.u32 d21, d6, #14 │ │ + vrshr.u32 d27, d8, #14 │ │ vsra.u64 d16, d0, #15 │ │ movs r5, r1 │ │ - push {r0, r3, r5, lr} │ │ + ldmia r7, {r0, r2, r5, r7} │ │ @ instruction: 0xfff1adfa │ │ vqrdmulh.s q13, q9, d22[0] │ │ - vcvt.f32.u32 , q10, #14 │ │ + @ instruction: 0xfff2d8f0 │ │ vcge.s8 , , #0 │ │ vtrn.8 d21, d23 │ │ vshr.u32 , q0, #14 │ │ vshr.u32 d31, d22, #14 │ │ vqshlu.s32 q10, q4, #18 │ │ mov.w r1, #4294967295 @ 0xffffffff │ │ blx 2327f0 <__emutls_get_address@@Base+0x5968> │ │ @@ -296970,24 +296970,24 @@ │ │ ldrex r1, [r0] │ │ subs r2, r1, #1 │ │ strex r3, r2, [r0] │ │ cmp r3, #0 │ │ bne.n 16e502 │ │ b.n 16e560 │ │ nop │ │ - bhi.n 16e47c │ │ - @ instruction: 0xfff1d898 │ │ - vsra.u32 d26, d24, #15 │ │ - vceq.i8 d26, d16, #0 │ │ + bl 49d4fa <__cxa_new_handler@@Base+0x25990a> │ │ + bl 4834fe <__cxa_new_handler@@Base+0x23f90e> │ │ + cbnz r4, 16e58c │ │ + @ instruction: 0xfff1bb9c │ │ vtbl.8 d19, {d1-d3}, d6 │ │ @ instruction: 0xfff139f6 │ │ @ instruction: 0xfff15b9a │ │ vtbl.8 d21, {d18-d21}, d12 │ │ - vrsra.u32 d30, d29, #14 │ │ - vabs.s8 d30, d31 │ │ + @ instruction: 0xfff2fdb9 │ │ + @ instruction: 0xfff1fdab │ │ vqshlu.s32 q8, q10, #17 │ │ movs r5, r1 │ │ ldr.w r6, [r9, #152] @ 0x98 │ │ movs r0, #0 │ │ strd r0, r0, [r9, #148] @ 0x94 │ │ cbz r6, 16e566 │ │ adds r0, r6, #4 │ │ @@ -297623,15 +297623,15 @@ │ │ mov r0, r9 │ │ blx r2 │ │ b.n 16ed10 │ │ stc 15, cr15, [r2], #968 @ 0x3c8 │ │ strh r2, [r0, r1] │ │ vceq.i8 d23, d22, #0 │ │ vneg.s8 q9, q3 │ │ - @ instruction: 0xfff18bfe │ │ + vqshlu.s32 q13, q13, #17 │ │ vqshlu.s32 q10, q10, #17 │ │ @ instruction: 0xfff2cad1 │ │ @ instruction: 0xfff2bdff │ │ vqshlu.s32 q15, q13, #18 │ │ vsli.64 d30, d2, #50 @ 0x32 │ │ vshr.u64 , q1, #14 │ │ vqrdmulh.s q12, , d24[0] │ │ @@ -297991,25 +297991,25 @@ │ │ add r1, sp, #80 @ 0x50 │ │ str r0, [sp, #0] │ │ mvn.w r0, #205 @ 0xcd │ │ blx 2306b0 <__emutls_get_address@@Base+0x3828> │ │ nop │ │ add sp, #76 @ 0x4c │ │ @ instruction: 0xfff2affd │ │ - vtbx.8 d29, {d2-d3}, d28 │ │ + @ instruction: 0xfff2f3e8 │ │ vtbx.8 d23, {d1-d2}, d5 │ │ vrshr.u32 d31, d20, #14 │ │ movs r4, r1 │ │ @ instruction: 0xf232000c │ │ - add r7, sp, #876 @ 0x36c │ │ + ldmia r2, {r0, r1, r2, r4, r6} │ │ vsra.u64 , q7, #15 │ │ movs r4, r1 │ │ add r5, sp, #340 @ 0x154 │ │ vzip.8 d20, d30 │ │ - vqshl.u32 d24, d20, #18 │ │ + vsra.u64 d26, d16, #14 │ │ vtbx.8 d20, {d17-d18}, d8 │ │ add r1, pc │ │ add r0, sp, #80 @ 0x50 │ │ bl a8ee4 const&, std::__ndk1::basic_string, std::__ndk1::allocator > const&) const@@Base+0x78> │ │ ldr r2, [pc, #796] @ (16f39c ) │ │ ldr r3, [pc, #796] @ (16f3a0 ) │ │ add r2, pc │ │ @@ -298277,55 +298277,55 @@ │ │ blx 232770 <__emutls_get_address@@Base+0x58e8> │ │ blx 231340 <__emutls_get_address@@Base+0x44b8> │ │ blx 230ee0 <__emutls_get_address@@Base+0x4058> │ │ add r0, sp, #56 @ 0x38 │ │ bl cd728 , std::__ndk1::allocator > const&, char, bool) const@@Base+0x264> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bl a8d68 │ │ - bl 41b30a <__cxa_new_handler@@Base+0x1d771a> │ │ - strh r0, [r5, #52] @ 0x34 │ │ + lsrs r7, r4, #20 │ │ + vuzp.8 d26, d20 │ │ vsra.u32 d20, d14, #15 │ │ - @ instruction: 0xfff29ed1 │ │ - vrsubhn.i d24, , q0 │ │ + vtbx.8 d27, {d2-d3}, d13 │ │ + vshr.u64 q13, q14, #15 │ │ vshr.u64 q10, q11, #15 │ │ @ instruction: 0xfff2374d │ │ - vcge.f8 q12, q2, #0 │ │ + vqrdmlsh.s , , d0[0] │ │ vcvt.u32.f32 d19, d26, #15 │ │ @ instruction: 0xfff2ee80 │ │ movs r4, r1 │ │ @ instruction: 0xf2de000c │ │ add r3, sp, #32 │ │ - vsli.32 d24, d0, #18 │ │ + @ instruction: 0xfff29f8c │ │ @ instruction: 0xfff13f86 │ │ - @ instruction: 0xfff29d80 │ │ - vcge.f8 q12, q11, #0 │ │ + vqshl.u64 , q14, #50 @ 0x32 │ │ + vqrdmlsh.s , , d18[0] │ │ vcvt.u32.f32 , q6, #15 │ │ @ instruction: 0xfff26994 │ │ - vsli.32 q12, q2, #17 │ │ + @ instruction: 0xfff19fd0 │ │ vqrdmlsh.s , , d10[0] │ │ vrsra.u64 d19, d3, #14 │ │ - vsli.32 d24, d18, #18 │ │ + @ instruction: 0xfff29fae │ │ @ instruction: 0xfff13fa8 │ │ vtbl.8 d20, {d18-d21}, d27 │ │ - vclt.f8 d24, d14, #0 │ │ + vcge.s8 d26, d10, #0 │ │ vcge.s8 d20, d4, #0 │ │ vraddhn.i d19, q1, │ │ - vabal.u q12, d18, d16 │ │ + vshr.u32 d26, d12, #14 │ │ vshr.u32 d20, d6, #15 │ │ vtbx.8 d20, {d18-d21}, d29 │ │ - vqshlu.s32 d24, d16, #17 │ │ + vcge.s8 d26, d28, #0 │ │ vcge.s8 d20, d22, #0 │ │ - vcvt.f32.u32 d26, d23, #14 │ │ - vcle.f8 q12, q10, #0 │ │ + @ instruction: 0xfff2c8b3 │ │ + vcgt.s8 q13, q8, #0 │ │ vshr.u32 q10, q5, #15 │ │ vrshr.u64 d24, d24, #14 │ │ - vsli.32 q12, q15, #18 │ │ + @ instruction: 0xfff29ffa │ │ @ instruction: 0xfff13ff4 │ │ - @ instruction: 0xfff2ae2b │ │ - vcle.f8 q12, q1, #0 │ │ + vtbl.8 d28, {d18}, d23 │ │ + vshr.u32 d26, d30, #15 │ │ vshr.u32 d20, d24, #15 │ │ Address 0x16f3c6 is out of bounds. │ │ │ │ │ │ 0016f3c8 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -298665,19 +298665,19 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #40] @ 0x28 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ stcl 0, cr0, [ip], {12} │ │ strd r0, r0, [r6, #48]! @ 0x30 │ │ - udf #2 │ │ - vsri.32 d27, d2, #15 │ │ + ldr??.w pc, [lr, #241]! │ │ + push {r1, r4} │ │ vdup.16 , d10[0] │ │ - vrshr.u64 , , #14 │ │ - @ instruction: 0xfff1db99 │ │ + vcvt.u16.f16 q14, , #14 │ │ + vqshlu.s32 d31, d5, #17 │ │ @ instruction: 0xfff139fa │ │ Address 0x16f77a is out of bounds. │ │ │ │ │ │ 0016f77c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -299270,15 +299270,15 @@ │ │ ldr r0, [sp, #64] @ 0x40 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r0, sp, #44 @ 0x2c │ │ bl 177310 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldmdb r8, {r2, r3} │ │ - pop {r0, r3, r4, r5, r6, r7, pc} │ │ + bhi.n 16fef6 │ │ vtbl.8 d18, {d1}, d7 │ │ @ instruction: 0xfff233ec │ │ vcvt.u32.f32 d19, d3, #14 │ │ vneg.f8 q9, │ │ @ instruction: 0xfff233c8 │ │ @ instruction: 0xfff2c562 │ │ vqshl.u64 d18, d31, #50 @ 0x32 │ │ @@ -299575,15 +299575,15 @@ │ │ vshr.u32 , q15, #15 │ │ vswp d30, d20 │ │ movs r4, r1 │ │ b.n 1701e8 │ │ movs r4, r1 │ │ b.n 1701a0 │ │ movs r4, r1 │ │ - add r1, sp, #228 @ 0xe4 │ │ + stmia r3!, {r0, r2, r4, r5, r7} │ │ vmlsl.u q11, d17, d19[0] │ │ vshr.u32 , q5, #15 │ │ Address 0x17011e is out of bounds. │ │ │ │ │ │ 00170120 : │ │ push {r4, r6, r7, lr} │ │ @@ -299646,16 +299646,16 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ svc 128 @ 0x80 │ │ movs r4, r1 │ │ svc 112 @ 0x70 │ │ movs r4, r1 │ │ svc 74 @ 0x4a │ │ movs r4, r1 │ │ - add r0, sp, #516 @ 0x204 │ │ - vceq.i8 , , #0 │ │ + stmia r2!, {r0, r2, r3, r4, r5, r6, r7} │ │ + @ instruction: 0xfff1ebbd │ │ @ instruction: 0xfff12fa2 │ │ Address 0x1701c2 is out of bounds. │ │ │ │ │ │ 001701c4 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -300272,24 +300272,24 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ blt.n 170810 │ │ movs r4, r1 │ │ subs r0, #167 @ 0xa7 │ │ vqshl.u32 q8, , #18 │ │ vtbx.8 d18, {d17-d18}, d6 │ │ - vrshr.u64 d26, d11, #14 │ │ + vcvt.u16.f16 d27, d7, #14 │ │ vqshl.u32 d16, d19, #17 │ │ vtbl.8 d18, {d17-d18}, d18 │ │ vsli.64 d25, d18, #50 @ 0x32 │ │ @ instruction: 0xfff23546 │ │ - vcgt.f8 d27, d16, #0 │ │ + @ instruction: 0xfff1ce9c │ │ vceq.f8 , q5, #0 │ │ vsri.64 , q7, #14 │ │ - vrsra.u64 d27, d24, #15 │ │ - vqshrun.s64 d25, , #15 │ │ + vcvt.f32.u32 d28, d20, #15 │ │ + vsubl.u , d17, d31 │ │ @ instruction: 0xfff1d99c │ │ movs r4, r1 │ │ │ │ 0017082c : │ │ and.w r0, r0, #6 │ │ subs r0, #4 │ │ clz r0, r0 │ │ @@ -300479,22 +300479,22 @@ │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ bhi.n 170a84 │ │ movs r4, r1 │ │ bvc.n 170958 │ │ movs r4, r1 │ │ - ldmia r2!, {r4, r6} │ │ + b.n 170388 │ │ vtbl.8 d18, {d1}, d20 │ │ vtbl.8 d28, {d2}, d8 │ │ vqshl.u64 d18, d4, #50 @ 0x32 │ │ vsri.64 , q6, #14 │ │ @ instruction: 0xfff2c7e4 │ │ vqshl.u32 q9, q8, #18 │ │ - vtbx.8 d28, {d18-d19}, d8 │ │ + vmls.i q15, q1, d4[0] │ │ vabs.f8 , q11 │ │ movs r4, r1 │ │ cbnz r0, 170a1a │ │ vtbl.8 d28, {d2}, d28 │ │ vqshl.u64 d18, d24, #50 @ 0x32 │ │ vqshl.u64 , q6, #50 @ 0x32 │ │ movs r4, r1 │ │ @@ -300645,15 +300645,15 @@ │ │ bpl.n 170af4 │ │ movs r4, r1 │ │ adds r4, #213 @ 0xd5 │ │ vcvt.f16.u16 q8, , #14 │ │ vsli.64 q9, q10, #50 @ 0x32 │ │ vsra.u64 d25, d10, #14 │ │ vuzp.8 d19, d30 │ │ - vcgt.s8 d27, d8, #0 │ │ + vtbl.8 d28, {d17-d19}, d4 │ │ vsli.64 d29, d10, #49 @ 0x31 │ │ movs r4, r1 │ │ │ │ 00170ba0 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -300803,21 +300803,21 @@ │ │ beq.n 170d24 │ │ ldr r0, [sp, #24] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bmi.n 170d20 │ │ movs r4, r1 │ │ adds r3, #71 @ 0x47 │ │ - vsli.64 , q15, #50 @ 0x32 │ │ + vshr.u32 , q13, #14 │ │ vcgt.f8 q9, q11, #0 │ │ vraddhn.i d29, q1, q6 │ │ movs r4, r1 │ │ str r0, [sp, #48] @ 0x30 │ │ @ instruction: 0xfff22fa0 │ │ - vcvt.f32.u32 q13, q13, #15 │ │ + @ instruction: 0xfff1c8f6 │ │ Address 0x170d46 is out of bounds. │ │ │ │ │ │ 00170d48 , std::__ndk1::allocator > const&, int)@@Base>: │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #24 │ │ @@ -300887,15 +300887,15 @@ │ │ bcc.n 170ea0 , std::__ndk1::allocator > const&, double)@@Base+0x94> │ │ movs r4, r1 │ │ adds r2, #103 @ 0x67 │ │ @ instruction: 0xfff2ff84 │ │ vneg.s8 d18, d6 │ │ @ instruction: 0xfff28f2c │ │ vqrdmlah.s q9, q9, d0[0] │ │ - @ instruction: 0xfff1ad9a │ │ + vqshrun.s64 d28, q3, #15 │ │ vabs.s8 d29, d30 │ │ movs r4, r1 │ │ │ │ 00170e0c , std::__ndk1::allocator > const&, double)@@Base>: │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #24 │ │ @@ -300967,15 +300967,15 @@ │ │ bcs.n 170de4 , std::__ndk1::allocator > const&, int)@@Base+0x9c> │ │ movs r4, r1 │ │ adds r1, #157 @ 0x9d │ │ @ instruction: 0xfff2feba │ │ vrshr.u64 d18, d28, #15 │ │ vqrdmlah.s q12, q1, d18[0] │ │ @ instruction: 0xfff22df6 │ │ - @ instruction: 0xfff1acd0 │ │ + vabs.f8 q14, q6 │ │ vclt.s8 , q11, #0 │ │ movs r4, r1 │ │ │ │ 00170ed8 , std::__ndk1::allocator > const&, std::__ndk1::basic_string, std::__ndk1::allocator > const&)@@Base>: │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #24 │ │ @@ -301053,15 +301053,15 @@ │ │ bne.n 170f24 , std::__ndk1::allocator > const&, std::__ndk1::basic_string, std::__ndk1::allocator > const&)@@Base+0x4c> │ │ movs r4, r1 │ │ adds r0, #195 @ 0xc3 │ │ vqrdmulh.s , q9, d16[0] │ │ vcle.s8 q9, q9, #0 │ │ @ instruction: 0xfff28d88 │ │ vcvt.u16.f16 d18, d12, #14 │ │ - @ instruction: 0xfff1abf6 │ │ + vqshlu.s32 q14, q9, #17 │ │ vsra.u64 d29, d0, #15 │ │ movs r4, r1 │ │ │ │ 00170fb0 , std::__ndk1::allocator > const&, void const*, unsigned int)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -301700,36 +301700,36 @@ │ │ movs r4, r1 │ │ add r5, sp, #12 │ │ vrsra.u32 d25, d17, #14 │ │ vtbx.8 d17, {d2-d5}, d20 │ │ @ instruction: 0xfff268f2 │ │ vshll.i8 , d13, #8 │ │ vtbx.8 d17, {d2-d5}, d0 │ │ - vsri.64 d26, d27, #14 │ │ + vcvt.u32.f32 d27, d23, #14 │ │ vmlal.u , d17, d25[0] │ │ @ instruction: 0xfff21b1c │ │ vswp d29, d12 │ │ movs r4, r1 │ │ - bkpt 0x007d │ │ + bhi.n 17168a , std::__ndk1::allocator > const&, void const*, unsigned int)@@Base+0x6da> │ │ @ instruction: 0xfff15ebc │ │ - vqmovn.u16 d27, │ │ + vcvt.u16.f16 q14, , #14 │ │ @ instruction: 0xfff1bcbc │ │ @ instruction: 0xfff25e88 │ │ - vqmovn.s16 d27, │ │ + @ instruction: 0xfff2cd0b │ │ vqshlu.s64 , , #49 @ 0x31 │ │ vqrdmulh.s , , d24[0] │ │ - vcvt.f32.u32 d27, d30, #14 │ │ + @ instruction: 0xfff2d8ba │ │ @ instruction: 0xfff15ea2 │ │ - vrshr.u64 d27, d25, #14 │ │ + vcvt.u16.f16 d28, d21, #14 │ │ vneg.f8 d16, d16 │ │ vrsra.u32 , , #15 │ │ vtbl.8 d17, {d18-d21}, d28 │ │ vqshl.u64 d24, d8, #50 @ 0x32 │ │ vabdl.u q9, d2, d28 │ │ - vclt.f8 d26, d6, #0 │ │ + vcge.s8 d28, d2, #0 │ │ Address 0x1716d6 is out of bounds. │ │ │ │ │ │ 001716d8 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -302224,15 +302224,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #24] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ stmia r6!, {r1, r2, r4, r5} │ │ movs r4, r1 │ │ - @ instruction: 0xb804 │ │ + bcs.n 171a94 │ │ vsli.32 q14, q2, #17 │ │ movs r4, r1 │ │ │ │ 00171b98 : │ │ push {r7, lr} │ │ mov r7, sp │ │ mov r2, r1 │ │ @@ -302353,16 +302353,16 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ stmia r4!, {r2, r7} │ │ movs r4, r1 │ │ - ldr r6, [sp, #404] @ 0x194 │ │ - @ instruction: 0xfff19e82 │ │ + @ instruction: 0xb8e1 │ │ + @ instruction: 0xfff1b8fe │ │ vsri.64 d17, d20, #15 │ │ vsri.32 q14, q5, #14 │ │ movs r4, r1 │ │ │ │ 00171cb0 : │ │ ldr r0, [r0, #72] @ 0x48 │ │ bx lr │ │ @@ -302421,15 +302421,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ stmia r3!, {r2, r3, r5, r6, r7} │ │ movs r4, r1 │ │ - ldr r5, [sp, #616] @ 0x268 │ │ + @ instruction: 0xb816 │ │ vtbx.8 d20, {d1-d2}, d9 │ │ vsri.32 d17, d0, #14 │ │ @ instruction: 0xfff2c3c2 │ │ movs r4, r1 │ │ │ │ 00171d54 : │ │ movs r1, #0 │ │ @@ -302557,20 +302557,20 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ stmia r3!, {r1, r2, r3, r4, r5} │ │ movs r4, r1 │ │ - ldr r4, [sp, #836] @ 0x344 │ │ + @ instruction: 0xb74d │ │ vtbx.8 d24, {d17-d19}, d0 │ │ vqmovn.u16 d17, q11 │ │ vrshr.u64 d28, d6, #14 │ │ movs r4, r1 │ │ - ldr r4, [sp, #692] @ 0x2b4 │ │ + @ instruction: 0xb729 │ │ @ instruction: 0xfff18a9c │ │ vqmovn.u16 d17, q1 │ │ Address 0x171eaa is out of bounds. │ │ │ │ │ │ 00171eac : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -303279,17 +303279,17 @@ │ │ ldrne r0, [sp, #48] @ 0x30 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ pop {r2, r4, r5, r6, r7, pc} │ │ movs r4, r1 │ │ ldrb r0, [r0, #8] │ │ - @ instruction: 0xfff28742 │ │ - vdup.8 d23, d9[0] │ │ - vabs.f8 d24, d20 │ │ + vsra.u64 d26, d30, #14 │ │ + vrsubhn.i d25, , │ │ + vcle.s8 d26, d16, #0 │ │ @ instruction: 0xfff10df0 │ │ @ instruction: 0xfff2bb3a │ │ movs r4, r1 │ │ │ │ 001725f4 : │ │ ldr r0, [r0, #0] │ │ clz r0, r0 │ │ @@ -303449,21 +303449,21 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ rev16 r2, r6 │ │ movs r4, r1 │ │ adds r4, #57 @ 0x39 │ │ - vtbx.8 d25, {d1-d3}, d11 │ │ + vcge.f8 , , #0 │ │ vshll.u32 q8, d14, #17 │ │ vrsra.u32 q15, q0, #14 │ │ - vtbl.8 d25, {d1-d3}, d23 │ │ + vcge.f8 d27, d19, #0 │ │ @ instruction: 0xfff109fa │ │ vsra.u64 q12, , #14 │ │ - vtbl.8 d25, {d2-d4}, d3 │ │ + vsri.32 , , #14 │ │ @ instruction: 0xfff109d6 │ │ vtbx.8 d27, {d18-d19}, d4 │ │ movs r4, r1 │ │ │ │ 001727a8 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -304721,17 +304721,17 @@ │ │ movs r4, r1 │ │ stc2 15, cr15, [r4, #-964]! @ 0xfffffc3c │ │ stmia.w r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc} │ │ mrrc2 15, 15, pc, ip, cr1 @ │ │ bl 4c3538 <__cxa_new_handler@@Base+0x27f948> │ │ ldrex pc, [ip, #960] @ 0x3c0 │ │ ldc2 15, cr15, [r8], #-964 @ 0xfffffc3c │ │ - ldrh r1, [r0, r2] │ │ + strb r5, [r7, #19] │ │ vsubl.u q15, d17, d12 │ │ - vclt.f8 q12, q6, #0 │ │ + vcge.s8 q13, q4, #0 │ │ @ instruction: 0xfff1ac9c │ │ movs r4, r1 │ │ │ │ 00173570 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ @@ -305386,20 +305386,20 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ movs r0, r0 │ │ movs r0, r0 │ │ add r2, sp, #272 @ 0x110 │ │ movs r4, r1 │ │ lsrs r4, r1, #27 │ │ - vtbl.8 d19, {d18-d20}, d29 │ │ + vabal.u , d2, d25 │ │ vsli.32 d31, d14, #17 │ │ vsri.64 q13, q10, #15 │ │ movs r4, r1 │ │ b.n 173ec8 │ │ - @ instruction: 0xfff03ad1 │ │ + vcnt.8 , │ │ vceq.f8 , q1, #0 │ │ Address 0x173c62 is out of bounds. │ │ │ │ │ │ 00173c64 , std::__ndk1::allocator > const&, char const*, int)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -305480,15 +305480,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #28] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r4, pc, #192 @ (adr r4, 173df8 ) │ │ movs r4, r1 │ │ - subs r2, #53 @ 0x35 │ │ + strb r1, [r6, r2] │ │ Address 0x173d3a is out of bounds. │ │ │ │ │ │ 00173d3c : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #24 │ │ @@ -305550,15 +305550,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r3, pc, #400 @ (adr r3, 173f70 ) │ │ movs r4, r1 │ │ - subs r1, #74 @ 0x4a │ │ + strh r6, [r0, r7] │ │ vceq.i8 q10, , #0 │ │ vrsra.u64 d31, d8, #14 │ │ vsra.u32 q10, q6, #15 │ │ vuzp.8 q10, │ │ vrsra.u32 , q10, #14 │ │ vrsra.u32 d26, d28, #15 │ │ movs r4, r1 │ │ @@ -306071,16 +306071,16 @@ │ │ ldr r1, [pc, #12] @ (17430c ) │ │ add r1, pc │ │ ldr r0, [r4, #0] │ │ ldr r2, [r0, #12] │ │ mov r0, r4 │ │ blx r2 │ │ b.n 1742c2 │ │ - ldrh r0, [r2, r7] │ │ - vneg.f8 d23, d19 │ │ + strb r4, [r1, #25] │ │ + vrshr.u32 d25, d15, #15 │ │ Address 0x174312 is out of bounds. │ │ │ │ │ │ 00174314 : │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r3, [r1, #20] │ │ @@ -306448,16 +306448,16 @@ │ │ itt ne │ │ cmpne r0, #0 │ │ blxne 230900 <__emutls_get_address@@Base+0x3a78> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r4, [sp, #312] @ 0x138 │ │ movs r4, r1 │ │ ldr r1, [pc, #368] @ (174828 , std::__ndk1::allocator > const&) const@@Base+0x5c>) │ │ - vtbx.8 d21, {d18}, d20 │ │ - vsri.64 , , #15 │ │ + @ instruction: 0xfff27360 │ │ + vcvt.u32.f32 q12, , #15 │ │ @ instruction: 0xfff1eab4 │ │ vqshl.u64 d21, d28, #49 @ 0x31 │ │ @ instruction: 0xfff29b12 │ │ movs r4, r1 │ │ │ │ 001746cc : │ │ ldr r0, [r0, #20] │ │ @@ -306758,15 +306758,15 @@ │ │ ldr r0, [sp, #264] @ 0x108 │ │ movs r4, r1 │ │ str r7, [sp, #784] @ 0x310 │ │ movs r4, r1 │ │ lsls r5, r3, #7 │ │ vtbl.8 d18, {d17-d19}, d30 │ │ vqshl.u64 d30, d14, #50 @ 0x32 │ │ - vclt.f8 d21, d3, #0 │ │ + vshr.u32 , , #15 │ │ @ instruction: 0xfff12ad2 │ │ @ instruction: 0xfff2e7c2 │ │ Address 0x1749da is out of bounds. │ │ │ │ │ │ 001749dc : │ │ ldrd r2, r3, [r1] │ │ @@ -307415,18 +307415,18 @@ │ │ vrshr.u32 d30, d0, #15 │ │ vtbl.8 d17, {d17}, d4 │ │ vcgt.s8 , q7, #0 │ │ vcle.s8 q15, q13, #0 │ │ vtbl.8 d29, {d1-d3}, d24 │ │ vrev64.8 d27, d26 │ │ vcle.s8 q15, q3, #0 │ │ - vqshlu.s64 , , #49 @ 0x31 │ │ + vsra.u32 , , #15 │ │ vcgt.s8 d27, d4, #0 │ │ vcle.s8 d30, d16, #0 │ │ - vabs.f8 q9, │ │ + vcle.s8 q10, , #0 │ │ vqrdmlsh.s q13, , d16[0] │ │ vsra.u32 q15, q14, #15 │ │ vneg.s8 d25, d10 │ │ movs r4, r1 │ │ │ │ 00175020 : │ │ movs r1, #0 │ │ @@ -308837,34 +308837,34 @@ │ │ itt ne │ │ ldrne r0, [sp, #48] @ 0x30 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strh r0, [r5, #58] @ 0x3a │ │ movs r4, r1 │ │ add r4, sp, #540 @ 0x21c │ │ - vcge.f8 d24, d28, #0 │ │ + @ instruction: 0xfff19f28 │ │ vabs.s8 d29, d4 │ │ vcgt.f8 d24, d24, #0 │ │ movs r4, r1 │ │ - subs r4, r0, r0 │ │ + adds r4, #128 @ 0x80 │ │ vclt.s8 d18, d19, #0 │ │ vsri.32 , q1, #14 │ │ vclt.s8 d18, d8, #0 │ │ vsra.u64 q9, , #14 │ │ vraddhn.i d29, q1, q8 │ │ @ instruction: 0xfff1bf84 │ │ - vsli.32 d24, d24, #16 │ │ + @ instruction: 0xfff09fb4 │ │ vrsra.u64 d29, d0, #15 │ │ @ instruction: 0xfff1bfa8 │ │ - vsli.32 q12, q6, #16 │ │ + @ instruction: 0xfff09fd8 │ │ vrsra.u64 d29, d20, #15 │ │ vceq.f8 , q4, #0 │ │ - vqshlu.s32 d24, d14, #17 │ │ + vshr.u64 d26, d10, #15 │ │ vsri.32 , q11, #15 │ │ - vtbl.8 d17, {d17-d18}, d30 │ │ + vcgt.f8 d19, d26, #0 │ │ vcle.s8 q9, , #0 │ │ vrsra.u64 , q14, #14 │ │ vcle.s8 q9, q0, #0 │ │ vzip.8 d18, d25 │ │ vrsra.u64 , q4, #14 │ │ vtbl.8 d28, {d17-d20}, d24 │ │ @ instruction: 0xfff0faf0 │ │ @@ -309521,15 +309521,15 @@ │ │ pop {r4, r5, r6, r7, pc} │ │ bl a8d68 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (176504 ) │ │ add r0, pc │ │ bl a91f8 │ │ - strb r1, [r5, #20] │ │ + ldrh r5, [r4, #60] @ 0x3c │ │ vsli.64 , q8, #49 @ 0x31 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #20 │ │ mov r6, r0 │ │ ldr.w r0, [pc, #980] @ 1768ec │ │ add r0, pc │ │ @@ -310228,15 +310228,15 @@ │ │ pop {r4, r6, r7, pc} │ │ bmi.n 176c4a │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (176cac ) │ │ add r0, pc │ │ bl a91f8 │ │ - ldr r1, [r0, #88] @ 0x58 │ │ + strh r5, [r7, #62] @ 0x3e │ │ vsli.64 , q8, #49 @ 0x31 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #20 │ │ mov r6, r0 │ │ ldr.w r0, [pc, #984] @ 177098 │ │ add r0, pc │ │ @@ -310776,15 +310776,15 @@ │ │ pop {r4, r5, r6, r7, pc} │ │ bl c71d0 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (1772bc ) │ │ add r0, pc │ │ bl 1772c0 │ │ - str r1, [r6, #116] @ 0x74 │ │ + strh r5, [r5, #14] │ │ vsli.64 d27, d16, #49 @ 0x31 │ │ add r7, sp, #8 │ │ mov r5, r0 │ │ movs r0, #8 │ │ blx 230710 <__emutls_get_address@@Base+0x3888> │ │ mov r4, r0 │ │ mov r1, r5 │ │ @@ -311077,21 +311077,21 @@ │ │ bl 1775e8 │ │ bl c71d0 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (1775f4 ) │ │ add r0, pc │ │ bl a91f8 │ │ - str r1, [r7, #64] @ 0x40 │ │ + ldrb r5, [r6, #26] │ │ vcle.f8 d27, d0, #0 │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (177604 ) │ │ add r0, pc │ │ bl a91f8 │ │ - str r1, [r5, #64] @ 0x40 │ │ + ldrb r5, [r4, #26] │ │ vsli.64 , q8, #49 @ 0x31 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r6, r0 │ │ ldrb r0, [r1, #0] │ │ ldrd sl, r5, [r1, #4] │ │ @@ -311984,15 +311984,15 @@ │ │ str r6, [r2, #44] @ 0x2c │ │ movs r4, r1 │ │ str r0, [r7, #44] @ 0x2c │ │ movs r4, r1 │ │ str r4, [r7, #40] @ 0x28 │ │ movs r4, r1 │ │ b.n 177e9a │ │ - vrsra.u64 q11, q9, #15 │ │ + vqrdmlah.s , , d30[0] │ │ vcgt.s8 , , #0 │ │ @ instruction: 0xfff061ee │ │ movs r4, r1 │ │ str r0, [r2, #36] @ 0x24 │ │ movs r4, r1 │ │ str r6, [r4, #28] │ │ movs r4, r1 │ │ @@ -312156,15 +312156,15 @@ │ │ ldr r0, [r4, #12] │ │ b.n 17810c │ │ mov r0, r6 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ str r2, [r4, #0] │ │ movs r4, r1 │ │ - lsrs r1, r2, #27 │ │ + cmp r1, #77 @ 0x4d │ │ vshr.u64 , , #15 │ │ vqrdmlah.s q12, q1, d13[0] │ │ @ instruction: 0xfff05ff2 │ │ movs r4, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -312263,16 +312263,16 @@ │ │ cmp r0, #0 │ │ itt ne │ │ strne r0, [r4, #12] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldrsh r0, [r5, r5] │ │ movs r4, r1 │ │ - lsrs r1, r7, #22 │ │ - vsra.u64 d16, d5, #15 │ │ + cmp r0, #53 @ 0x35 │ │ + vcvt.f16.u16 d17, d1, #15 │ │ vcvt.u16.f16 d24, d21, #15 │ │ vqrdmlah.s , q8, d18[0] │ │ movs r4, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ sub sp, #40 @ 0x28 │ │ @@ -312451,18 +312451,18 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrb r4, [r2, r7] │ │ movs r4, r1 │ │ b.n 1789be │ │ - vqshlu.s64 d18, d28, #49 @ 0x31 │ │ + vsra.u32 d20, d24, #15 │ │ vtbx.8 d24, {d1-d4}, d13 │ │ vsli.64 , q5, #48 @ 0x30 │ │ - vabs.f8 q9, q15 │ │ + vcle.s8 q10, q13, #0 │ │ @ instruction: 0xfff18bff │ │ @ instruction: 0xfff05cf2 │ │ movs r4, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #116 @ 0x74 │ │ @@ -313207,30 +313207,30 @@ │ │ b.n 178bf0 │ │ add r0, sp, #28 │ │ bl ce5f8 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrsb r0, [r4, r6] │ │ movs r4, r1 │ │ - subs r7, r5, #3 │ │ - @ instruction: 0xfff13af8 │ │ + subs r1, #107 @ 0x6b │ │ + vsli.32 , q10, #17 │ │ vabs.s8 q12, │ │ vcvt.f32.u32 d25, d19, #16 │ │ - @ instruction: 0xfff03b1a │ │ + vsli.64 d21, d6, #48 @ 0x30 │ │ vneg.s8 d24, d13 │ │ aese.8 q8, │ │ movs r0, r0 │ │ lsls r3, r0, #10 │ │ movs r0, r0 │ │ lsls r3, r0, #12 │ │ movs r0, r0 │ │ lsls r5, r3, #10 │ │ movs r0, r0 │ │ blt.n 178cb2 │ │ - @ instruction: 0xfff13b3c │ │ + vsli.64 d21, d24, #49 @ 0x31 │ │ vneg.s8 d24, d31 │ │ vpaddl.u8 q8, │ │ movs r0, r0 │ │ ldrsb r6, [r0, r0] │ │ movs r4, r1 │ │ strb r0, [r3, r7] │ │ movs r4, r1 │ │ @@ -313445,15 +313445,15 @@ │ │ bl 1772c0 │ │ add r2, pc, #688 @ (adr r2, 1790e0 ) │ │ vmvn d27, d0 │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (178e3c ) │ │ add r0, pc │ │ bl a91f8 │ │ - ldr r3, [pc, #964] @ (179204 ) │ │ + str r5, [r5, #100] @ 0x64 │ │ vsli.64 d27, d16, #49 @ 0x31 │ │ add r7, sp, #8 │ │ mov r5, r0 │ │ movs r0, #20 │ │ mov r4, r1 │ │ blx 2306d0 <__emutls_get_address@@Base+0x3848> │ │ ldr r1, [pc, #32] @ (178e70 ) │ │ @@ -313628,15 +313628,15 @@ │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ str r2, [r4, r6] │ │ movs r4, r1 │ │ add r2, pc, #448 @ (adr r2, 1791c4 ) │ │ vsra.u64 q10, q1, #15 │ │ vqmovn.s16 d26, │ │ - vabs.s8 q10, q4 │ │ + vqrdmulh.s , , d4[0] │ │ vceq.i8 d21, d16, #0 │ │ movs r4, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ ldr r5, [r1, #12] │ │ mov r4, r0 │ │ @@ -313944,15 +313944,15 @@ │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r7, [pc, #96] @ (179350 ) │ │ movs r4, r1 │ │ ldrb r4, [r3, #20] │ │ vtbl.8 d23, {d16-d18}, d2 │ │ @ instruction: 0xfff19fd1 │ │ - vqshl.u64 , , #49 @ 0x31 │ │ + vclt.s8 , , #0 │ │ vtbx.8 d23, {d1-d3}, d16 │ │ @ instruction: 0xfff19faf │ │ @ instruction: 0xfff14e2e │ │ movs r4, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -314300,16 +314300,16 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldr r5, [pc, #552] @ (179880 ) │ │ movs r4, r1 │ │ stmia r7!, {r2, r3, r5, r6, r7} │ │ vcls.s8 q12, q6 │ │ vcvt.u32.f32 d25, d7, #15 │ │ - @ instruction: 0xfff1f9b9 │ │ - vaddw.u q12, q8, d24 │ │ + vsri.32 d17, d21, #15 │ │ + vcle.s8 d24, d24, #0 │ │ vcvt.f16.u16 , , #15 │ │ @ instruction: 0xfff19cdd │ │ vcle.s8 d24, d6, #0 │ │ vcvt.f16.u16 , , #15 │ │ vsli.64 , q10, #49 @ 0x31 │ │ aesimc.8 q12, q3 │ │ @ instruction: 0xfff19e91 │ │ @@ -314657,16 +314657,16 @@ │ │ ldr r0, [pc, #112] @ (179a48 ) │ │ movs r4, r1 │ │ ldrb r4, [r2, #25] │ │ vcvt.u16.f16 q14, , #15 │ │ vtbl.8 d25, {d1-d2}, d5 │ │ vabs.f8 q10, q10 │ │ movs r4, r1 │ │ - bl fffb59cc <__cxa_new_handler@@Base+0xffd71ddc> │ │ - ldmia r5, {r0, r4, r5} │ │ + asrs r7, r6, #2 │ │ + vcvt.u16.f16 d28, d17, #15 │ │ @ instruction: 0xfff198df │ │ vsli.64 , q8, #49 @ 0x31 │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ sub sp, #24 │ │ ldr r5, [pc, #144] @ (179a90 ) │ │ ldr r2, [r7, #8] │ │ @@ -314731,15 +314731,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ mov lr, r4 │ │ movs r4, r1 │ │ - movs r1, #130 @ 0x82 │ │ + subs r3, #254 @ 0xfe │ │ vcle.s8 d27, d12, #0 │ │ vtbl.8 d25, {d0}, d9 │ │ vrsubhn.i d20, , q0 │ │ movs r4, r1 │ │ bx lr │ │ bmi.n 179a52 │ │ push {r4, r5, r6, r7, lr} │ │ @@ -314984,15 +314984,15 @@ │ │ vqshl.u64 d25, d15, #49 @ 0x31 │ │ vmlsl.u , d17, d2[0] │ │ vrsubhn.i d25, , │ │ vqshlu.s32 d25, d5, #17 │ │ vcvt.f16.u16 q12, , #15 │ │ vqabs.s8 d25, d23 │ │ vqshlu.s64 d25, d3, #49 @ 0x31 │ │ - vtbl.8 d29, {d17-d19}, d6 │ │ + vceq.f8 d31, d2, #0 │ │ vpadal.u8 d25, d3 │ │ vcle.f8 , , #0 │ │ vcgt.f8 d26, d15, #0 │ │ vqshlu.s64 , , #49 @ 0x31 │ │ vqshlu.s32 , , #17 │ │ vsri.32 q10, q11, #15 │ │ movs r4, r1 │ │ @@ -315419,27 +315419,27 @@ │ │ beq.n 17a0d4 │ │ ldr r0, [sp, #36] @ 0x24 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ sbcs r4, r2 │ │ movs r4, r1 │ │ bcc.n 17a0a0 │ │ - vabs.s8 d30, d16 │ │ + @ instruction: 0xfff1fd9c │ │ vsra.u64 , , #16 │ │ - @ instruction: 0xfff1ff02 │ │ - vrshr.u64 q15, q14, #16 │ │ + vqrshrn.u64 d17, q15, #15 │ │ + vcvt.u16.f16 , q12, #15 │ │ vsra.u64 , , #16 │ │ @ instruction: 0xfff189d8 │ │ - aesd.8 q15, q3 │ │ + vqrdmulh.s , q8, d2[0] │ │ vrshr.u32 d25, d13, #16 │ │ vsri.32 , q2, #15 │ │ - vrsra.u64 d30, d4, #15 │ │ + vcvt.f32.u32 d31, d0, #15 │ │ vpaddl.s8 , │ │ - vmlal.u q10, d17, d7[0] │ │ - vabs.s8 q15, q14 │ │ + vqrdmulh.s , , d3[0] │ │ + vqrdmulh.s , , d24[0] │ │ vpaddl.s8 , │ │ vcge.s8 q10, q6, #0 │ │ movs r4, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #52 @ 0x34 │ │ @@ -315669,21 +315669,21 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ subs r7, #124 @ 0x7c │ │ movs r4, r1 │ │ strb r0, [r1, #21] │ │ vmlsl.u , d17, d18[0] │ │ @ instruction: 0xfff18ff9 │ │ - vcgt.s8 , q14, #0 │ │ + vtbx.8 d20, {d17-d19}, d24 │ │ vqshlu.s64 d27, d26, #49 @ 0x31 │ │ @ instruction: 0xfff18fd1 │ │ vqshl.u64 q12, , #49 @ 0x31 │ │ vqabs.s8 d27, d10 │ │ vcgt.s8 d25, d17, #0 │ │ - vshr.u32 , q6, #15 │ │ + @ instruction: 0xfff14ad8 │ │ vqshlu.s64 d27, d2, #49 @ 0x31 │ │ @ instruction: 0xfff18fa9 │ │ vsra.u64 d29, d9, #15 │ │ vclt.f8 , q13, #0 │ │ @ instruction: 0xfff18f81 │ │ vshr.u32 d25, d15, #15 │ │ vqshlu.s32 d27, d28, #17 │ │ @@ -316609,25 +316609,25 @@ │ │ itt ne │ │ ldrne r0, [sp, #24] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r2, pc, #184 @ (adr r2, 17ad08 ) │ │ vqrdmlah.s q11, , d26[0] │ │ @ instruction: 0xfff1899b │ │ - vqshlu.s64 d30, d22, #49 @ 0x31 │ │ - @ instruction: 0xfff06e86 │ │ + vsra.u32 d16, d18, #15 │ │ + @ instruction: 0xfff16e86 │ │ vqshrn.u64 d24, , #15 │ │ @ instruction: 0xfff1cb38 │ │ vqdmulh.s , , d26[0] │ │ movs r4, r1 │ │ bl 470c52 <__cxa_new_handler@@Base+0x22d062> │ │ ldr r0, [r4, #88] @ 0x58 │ │ vqrshrun.s64 d24, , #15 │ │ - vcle.f8 d31, d15, #0 │ │ - vqrdmulh.s q11, q8, d8[0] │ │ + vcgt.s8 d17, d11, #0 │ │ + vqrdmulh.s q11, , d8[0] │ │ vqrshrun.s64 d24, , #15 │ │ vcge.s8 q13, q15, #0 │ │ @ instruction: 0xfff06d00 │ │ vqshl.u64 d24, d17, #49 @ 0x31 │ │ vtbx.8 d27, {d17-d20}, d7 │ │ @ instruction: 0xfff16cb0 │ │ vabs.f8 q12, │ │ @@ -318053,28 +318053,28 @@ │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ movs r7, #110 @ 0x6e │ │ movs r4, r1 │ │ str r2, [sp, #612] @ 0x264 │ │ vpaddl.s8 d30, d3 │ │ - vtbl.8 d27, {d17-d20}, d21 │ │ + vclt.f8 d29, d17, #0 │ │ vtbx.8 d23, {d0}, d11 │ │ vdup.8 d31, d23[0] │ │ - vtbx.8 d28, {d17-d18}, d13 │ │ - vshr.u64 d30, d18, #16 │ │ + vcgt.f8 q15, , #0 │ │ + vtbl.8 d31, {d0-d3}, d30 │ │ @ instruction: 0xfff078b8 │ │ - vtbl.8 d27, {d17-d20}, d5 │ │ + vclt.f8 d29, d1, #0 │ │ vtbl.8 d23, {d0}, d27 │ │ - vtbl.8 d18, {d1-d2}, d11 │ │ - vsri.64 d29, d13, #15 │ │ - vtbx.8 d27, {d0-d3}, d5 │ │ + vneg.s8 d20, d7 │ │ + vcvt.u32.f32 d30, d9, #15 │ │ + vmvn , │ │ vqneg.s8 , │ │ - vqshl.u64 q9, , #49 @ 0x31 │ │ - vtbx.8 d27, {d1-d4}, d21 │ │ + vrshr.u32 q10, , #15 │ │ + vcle.f8 , , #0 │ │ vtbl.8 d23, {d0}, d11 │ │ vcle.f8 q9, q2, #0 │ │ movs r4, r1 │ │ │ │ 0017bc24 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -318426,29 +318426,29 @@ │ │ nop │ │ movs r4, #114 @ 0x72 │ │ movs r4, r1 │ │ movs r4, #94 @ 0x5e │ │ movs r4, r1 │ │ ldrh r3, [r2, #60] @ 0x3c │ │ vcvt.f32.u32 d29, d11, #16 │ │ - vqshl.u64 d27, d29, #49 @ 0x31 │ │ + vrshr.u32 d29, d25, #15 │ │ vcls.s8 , │ │ - vclt.f8 q9, , #0 │ │ - vshr.u64 , , #15 │ │ - vqshl.u64 d27, d13, #48 @ 0x30 │ │ + vcge.s8 q10, , #0 │ │ + @ instruction: 0xfff1eb71 │ │ + vrshr.u32 d29, d9, #16 │ │ vcls.s8 , │ │ - vqrdmulh.s , , d28[0] │ │ + vtbx.8 d31, {d1}, d24 │ │ vshr.u32 d28, d7, #16 │ │ - vqshl.u32 , , #17 │ │ + vsra.u64 , , #15 │ │ vcls.s8 d23, d19 │ │ - vqrshrun.s64 d27, q5, #15 │ │ - vqshl.u64 , , #48 @ 0x30 │ │ + vrshr.u64 , q3, #15 │ │ + vrshr.u32 , , #16 │ │ vclz.i8 d23, d3 │ │ - vsra.u32 d30, d3, #15 │ │ - vqshl.u64 , , #48 @ 0x30 │ │ + vtbl.8 d31, {d17-d20}, d15 │ │ + vrshr.u32 , , #16 │ │ vclz.i8 d23, d19 │ │ vrshr.u32 d18, d12, #15 │ │ movs r4, r1 │ │ │ │ 0017c004 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -319406,15 +319406,15 @@ │ │ asrs r6, r7, #27 │ │ movs r4, r1 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (17c9fc >&)@@Base+0x42c>) │ │ add r0, pc │ │ bl a91f8 │ │ - asrs r1, r6, #32 │ │ + cmp r2, #173 @ 0xad │ │ vsli.64 , q8, #49 @ 0x31 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #44 @ 0x2c │ │ mov lr, r0 │ │ ldr r0, [pc, #832] @ (17cd50 >&)@@Base+0x780>) │ │ ldr r5, [r7, #8] │ │ @@ -320870,15 +320870,15 @@ │ │ movs r0, r0 │ │ nop {8} │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (17d90c >&)@@Base+0x133c>) │ │ add r0, pc │ │ bl a91f8 │ │ - lsls r1, r4, #4 │ │ + subs r5, r3, r6 │ │ vsli.64 , q8, #49 @ 0x31 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #36 @ 0x24 │ │ mov r6, r0 │ │ ldr r0, [pc, #152] @ (17d9b8 >&)@@Base+0x13e8>) │ │ mov r4, r2 │ │ @@ -321075,16 +321075,16 @@ │ │ @ instruction: 0xffffffff │ │ vcvt.u32.f32 , , #1 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (17db5c >&)@@Base+0x158c>) │ │ add r0, pc │ │ bl a91f8 │ │ - mrc2 15, 6, pc, cr1, cr0, {7} │ │ - push {r4, r5, r7, lr} │ │ + adds r5, r1, r5 │ │ + vsli.64 d27, d16, #49 @ 0x31 │ │ add r7, sp, #8 │ │ mov r5, r0 │ │ movs r0, #20 │ │ mov r4, r1 │ │ blx 2306d0 <__emutls_get_address@@Base+0x3848> │ │ ldr r1, [pc, #32] @ (17db90 >&)@@Base+0x15c0>) │ │ movs r3, #0 │ │ @@ -321672,15 +321672,15 @@ │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ lsls r4, r7, #5 │ │ movs r4, r1 │ │ cmp r6, #200 @ 0xc8 │ │ vmull.u q9, d0, d30 │ │ @ instruction: 0xfff129b6 │ │ - @ instruction: 0xfff1c99d │ │ + vsri.32 d30, d9, #15 │ │ vmull.u q9, d0, d12 │ │ @ instruction: 0xfff12994 │ │ vabs.s8 d30, d24 │ │ vqrdmlsh.s , , d26[0] │ │ movs r3, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -322532,15 +322532,15 @@ │ │ vrsra.u64 d18, d20, #15 │ │ @ instruction: 0xfff1e8bc │ │ vqrdmlah.s q9, , d5[0] │ │ vcle.s8 d18, d20, #0 │ │ @ instruction: 0xfff18d28 │ │ vcgt.s8 d19, d27, #0 │ │ vabs.s8 d18, d10 │ │ - @ instruction: 0xfff1ddab │ │ + vtbl.8 d31, {d1}, d23 │ │ @ instruction: 0xfff02ea3 │ │ vcle.s8 d18, d2, #0 │ │ vclt.f8 , q14, #0 │ │ vqrdmlah.s q9, , d23[0] │ │ vcle.s8 q9, q3, #0 │ │ vqshl.u64 , q14, #49 @ 0x31 │ │ movs r3, r1 │ │ @@ -322962,25 +322962,25 @@ │ │ ldrb.w r0, [sp, #88] @ 0x58 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #96] @ 0x60 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ @ instruction: 0xf61a000b │ │ - ldmia r6, {r0, r1, r3, r5, r6, r7} │ │ - vtbl.8 d23, {d16-d17}, d31 │ │ + strd pc, pc, [r7, #-960]! @ 0x3c0 │ │ + ldrb r7, [r5, #6] │ │ @ instruction: 0xfff11d96 │ │ vtbl.8 d18, {d17-d19}, d6 │ │ vtbl.8 d23, {d17-d18}, d7 │ │ vqrdmulh.s , , d30[0] │ │ - vtbl.8 d29, {d17-d20}, d25 │ │ + vclt.f8 d31, d21, #0 │ │ vmull.u , d0, d9 │ │ vtbx.8 d23, {d1-d2}, d19 │ │ vqrdmulh.s , , d10[0] │ │ - vcge.s8 , , #0 │ │ + vtbx.8 d30, {d1-d4}, d25 │ │ vtbx.8 d18, {d16-d18}, d14 │ │ vtbx.8 d23, {d17-d18}, d15 │ │ @ instruction: 0xfff11db6 │ │ vsli.32 d30, d10, #17 │ │ @ instruction: 0xfff179f3 │ │ @ instruction: 0xfff11dda │ │ @ instruction: 0xfff15f01 │ │ @@ -323058,15 +323058,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ @ instruction: 0xf222000b │ │ - ldmia r4, {r1, r2, r3, r4, r5, r6, r7} │ │ + b.n 17ee10 >&)@@Base+0x2840> │ │ @ instruction: 0xfff05d08 │ │ @ instruction: 0xfff01bbe │ │ vcle.s8 , q11, #0 │ │ movs r3, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -323260,15 +323260,15 @@ │ │ sbcs.w r0, r0, #11 │ │ muls r7, r2 │ │ vclt.s8 q10, , #0 │ │ vtbl.8 d17, {d1-d3}, d12 │ │ vabs.f8 q9, q15 │ │ vrshr.u64 d20, d19, #15 │ │ @ instruction: 0xfff11a58 │ │ - vqshlu.s64 d24, d0, #49 @ 0x31 │ │ + vceq.i8 d26, d12, #0 │ │ vpaddl.u8 d20, d13 │ │ vshll.u32 , d18, #17 │ │ vcge.s8 d31, d0, #0 │ │ movs r3, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -323985,21 +323985,21 @@ │ │ vceq.f8 d17, d30, #0 │ │ vqshrn.u64 d25, q11, #15 │ │ vsri.32 q11, , #15 │ │ vcle.f8 d17, d16, #0 │ │ vqrdmlsh.s , , d15[0] │ │ vrsra.u64 d22, d11, #15 │ │ vcge.f8 , q9, #0 │ │ - vqshlu.s32 q14, q12, #17 │ │ + vshr.u64 q15, q10, #15 │ │ aesimc.8 q11, │ │ vceq.f8 d17, d8, #0 │ │ - vcge.f8 , q0, #0 │ │ + vcvt.u32.f32 d28, d28, #15 │ │ aesd.8 q11, │ │ vsri.64 d17, d4, #15 │ │ - vqshl.u32 d28, d22, #17 │ │ + vsra.u64 d30, d18, #15 │ │ vclz.i8 d22, d29 │ │ vsli.64 , q10, #49 @ 0x31 │ │ vsra.u32 d23, d9, #15 │ │ vrsra.u32 q11, , #15 │ │ vcge.f8 , q2, #0 │ │ vclt.s8 q9, q14, #0 │ │ vcgt.f8 d22, d13, #0 │ │ @@ -324508,15 +324508,15 @@ │ │ bl 17ef28 >&)@@Base+0x2958> │ │ mov r1, r0 │ │ cbnz r1, 17fd58 >&)@@Base+0x3788> │ │ b.n 180046 >&)@@Base+0x3a76> │ │ asrs r0, r0, #24 │ │ @ instruction: 0xfff01e00 │ │ vtbl.8 d18, {d17-d20}, d24 │ │ - @ instruction: 0xfff1d8f6 │ │ + vrsra.u32 , q9, #15 │ │ vtbx.8 d19, {d0}, d9 │ │ vshll.u32 q13, d13, #17 │ │ mov r0, fp │ │ mov r1, r4 │ │ bl 17f860 >&)@@Base+0x3290> │ │ mov r1, r0 │ │ add r0, sp, #40 @ 0x28 │ │ @@ -325077,15 +325077,15 @@ │ │ movs r3, r1 │ │ asrs r4, r3, #25 │ │ vqshlu.s32 , q6, #17 │ │ vtbx.8 d16, {d1-d2}, d6 │ │ vqshl.u64 , q15, #49 @ 0x31 │ │ vqshl.u64 , q14, #49 @ 0x31 │ │ vtbx.8 d16, {d17-d19}, d22 │ │ - vrsra.u64 q15, q8, #15 │ │ + vqrdmlah.s , , d28[0] │ │ vtbx.8 d17, {d0}, d30 │ │ @ instruction: 0xfff10b58 │ │ vcvt.u32.f32 , , #15 │ │ vqshl.u64 , q3, #49 @ 0x31 │ │ vtbx.8 d16, {d17-d19}, d0 │ │ vabs.f8 d22, d9 │ │ vqshl.u64 d17, d24, #49 @ 0x31 │ │ @@ -325098,15 +325098,15 @@ │ │ vtbl.8 d16, {d1-d3}, d28 │ │ vshll.u32 q10, d6, #17 │ │ vqshlu.s64 , q0, #49 @ 0x31 │ │ @ instruction: 0xfff109ba │ │ @ instruction: 0xfff128b9 │ │ vqshlu.s32 d17, d22, #16 │ │ vtbl.8 d16, {d1-d2}, d16 │ │ - @ instruction: 0xfff18f03 │ │ + vqrshrn.u64 d26, , #15 │ │ vpadal.u8 d17, d26 │ │ @ instruction: 0xfff10994 │ │ vshll.u32 q8, d28, #17 │ │ vrsubhn.i d17, , q2 │ │ vtbx.8 d16, {d1-d2}, d30 │ │ @ instruction: 0xfff19dbf │ │ vtbx.8 d17, {d1}, d8 │ │ @@ -325338,16 +325338,16 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ bgt.n 1804a8 >&)@@Base+0x3ed8> │ │ movs r3, r1 │ │ cmp r5, #8 │ │ vdup.8 q14, d26[0] │ │ vcge.s8 , , #0 │ │ - @ instruction: 0xfff1ceb4 │ │ - @ instruction: 0xfff07f02 │ │ + vqshrn.u64 d30, q8, #15 │ │ + vqrshrn.u64 d25, q15, #16 │ │ vtbl.8 d23, {d0-d3}, d14 │ │ @ instruction: 0xfff1189a │ │ vtbl.8 d29, {d16-d19}, d16 │ │ movs r3, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -325712,18 +325712,18 @@ │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bls.n 1808a4 >&)@@Base+0x42d4> │ │ movs r3, r1 │ │ lsls r0, r2, #28 │ │ vsri.32 q8, q11, #16 │ │ vqrdmulh.s q13, , d11[0] │ │ - vcle.s8 q13, , #0 │ │ + vdup.8 , d17[0] │ │ vsri.32 q8, q2, #16 │ │ @ instruction: 0xfff1ad29 │ │ - @ instruction: 0xfff1beae │ │ + vtbl.8 d29, {d1-d2}, d26 │ │ vtbl.8 d29, {d0}, d18 │ │ movs r3, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #28 │ │ mov r4, r0 │ │ @@ -326065,15 +326065,15 @@ │ │ movs r3, r1 │ │ str r2, [r4, r7] │ │ vqrdmlah.s q8, q0, d2[0] │ │ @ instruction: 0xfff1ac93 │ │ vqrdmulh.s , , d0[0] │ │ @ instruction: 0xfff00b92 │ │ vtbx.8 d26, {d17-d18}, d19 │ │ - vcgt.f8 d24, d9, #0 │ │ + @ instruction: 0xfff19e85 │ │ @ instruction: 0xfff00bf8 │ │ vtbx.8 d26, {d1-d3}, d9 │ │ vabs.f8 d18, d11 │ │ @ instruction: 0xfff10bb4 │ │ vtbl.8 d26, {d1-d3}, d5 │ │ @ instruction: 0xfff14f9b │ │ @ instruction: 0xfff00bd6 │ │ @@ -326648,21 +326648,21 @@ │ │ movs r3, r1 │ │ lsls r0, r1, #26 │ │ vcle.f8 d21, d11, #0 │ │ vsri.64 d26, d31, #15 │ │ @ instruction: 0xfff10dfc │ │ vqdmulh.s q9, q8, d22[0] │ │ vrev16.8 d19, d2 │ │ - vcge.s8 q12, q11, #0 │ │ - vmvn d22, d30 │ │ + vtbx.8 d25, {d1-d4}, d18 │ │ + vrev64.8 d24, d26 │ │ vsli.32 d21, d31, #16 │ │ vsri.32 q13, , #15 │ │ @ instruction: 0xfff10d9c │ │ vshr.u64 d19, d12, #16 │ │ - vcge.s8 d24, d0, #0 │ │ + @ instruction: 0xfff19afc │ │ vtbl.8 d18, {d16-d19}, d14 │ │ vsli.64 d21, d17, #48 @ 0x30 │ │ vcge.f8 q13, , #0 │ │ @ instruction: 0xfff12d20 │ │ vtbx.8 d19, {d16-d18}, d16 │ │ vcnt.8 , │ │ vsri.64 d26, d9, #15 │ │ @@ -326768,15 +326768,15 @@ │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldmia r6, {r1, r6} │ │ movs r3, r1 │ │ lsls r4, r2, #19 │ │ vtbl.8 d19, {d1-d2}, d8 │ │ aese.8 q13, │ │ - @ instruction: 0xfff1a8d6 │ │ + vrsra.u32 q14, q1, #15 │ │ vtbx.8 d19, {d16}, d16 │ │ vpaddl.u8 q13, │ │ @ instruction: 0xfff1ce0c │ │ movs r3, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -326951,24 +326951,24 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldmia r5, {r2, r3, r4, r5} │ │ movs r3, r1 │ │ lsls r6, r6, #12 │ │ vcvt.f32.u32 , , #15 │ │ vceq.i8 q13, , #0 │ │ - vmlsl.u , d17, d19[0] │ │ + vsra.u32 , , #15 │ │ @ instruction: 0xfff01ed9 │ │ vcle.s8 q13, , #0 │ │ vdup.8 q14, d8[0] │ │ movs r3, r1 │ │ cmp r0, #214 @ 0xd6 │ │ @ instruction: 0xfff01f0d │ │ vsra.u64 q13, , #15 │ │ vtbx.8 d22, {d17-d19}, d14 │ │ - @ instruction: 0xfff16f0d │ │ + vtbl.8 d24, {d17-d18}, d9 │ │ vqrdmlah.s , q0, d11[0] │ │ vsra.u32 d26, d29, #15 │ │ vsli.64 , q8, #49 @ 0x31 │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #92 @ 0x5c │ │ strd r3, r2, [sp, #32] │ │ @@ -327357,30 +327357,30 @@ │ │ mov r5, r6 │ │ ldrb.w r0, [r5, #2]! │ │ sub.w r1, r0, #92 @ 0x5c │ │ cmp r1, #24 │ │ bhi.n 18196e >&)@@Base+0x539e> │ │ addw r2, pc, #8 │ │ tbb [r2, r1] │ │ - pop {r1, r3, r7, pc} │ │ + bhi.n 181928 >&)@@Base+0x5358> │ │ vcls.s8 d19, d18 │ │ adds r4, #52 @ 0x34 │ │ adds r4, #52 @ 0x34 │ │ adds r4, #52 @ 0x34 │ │ adds r4, #52 @ 0x34 │ │ adds r4, #52 @ 0x34 │ │ adds r4, #52 @ 0x34 │ │ adds r4, #52 @ 0x34 │ │ adds r4, #52 @ 0x34 │ │ adds r4, #38 @ 0x26 │ │ adds r4, #52 @ 0x34 │ │ adds r4, #61 @ 0x3d │ │ movs r0, r7 │ │ nop │ │ - pop {r5, r6, r7} │ │ + bvc.n 1819f4 >&)@@Base+0x5424> │ │ @ instruction: 0xfff0f998 │ │ vsli.64 q13, , #47 @ 0x2f │ │ vqrdmlsh.s q8, , d4[0] │ │ vsra.u32 q8, q13, #15 │ │ vcvt.f32.u32 d24, d27, #15 │ │ vsra.u64 d17, d21, #15 │ │ vcvt.u32.f32 d31, d20, #16 │ │ @@ -328147,15 +328147,15 @@ │ │ nop │ │ movs r2, #251 @ 0xfb │ │ vtbx.8 d28, {d1-d4}, d28 │ │ movs r3, r1 │ │ ldr.w pc, [r6, #4080] @ 0xff0 │ │ ldr.w pc, [r6, #4080] @ 0xff0 │ │ str r7, [sp, #52] @ 0x34 │ │ - vtbx.8 d24, {d17-d20}, d27 │ │ + vclt.f8 q13, , #0 │ │ vtbl.8 d31, {d16}, d6 │ │ vqshlu.s64 d25, d29, #48 @ 0x30 │ │ vqrshrun.s64 d31, q7, #15 │ │ vqrshrun.s64 d31, q7, #16 │ │ vqshlu.s64 d25, d5, #48 @ 0x30 │ │ @ instruction: 0xfff1c9b4 │ │ movs r3, r1 │ │ @@ -328164,30 +328164,30 @@ │ │ vpadal.u8 , │ │ vshr.u64 d22, d30, #15 │ │ @ instruction: 0xfff1f8fe │ │ vqshl.u32 d25, d21, #16 │ │ vcge.s8 q11, q11, #0 │ │ vtbl.8 d31, {d1-d2}, d22 │ │ vqshl.u32 , , #16 │ │ - vcgt.s8 d23, d27, #0 │ │ + vtbl.8 d24, {d17-d19}, d23 │ │ vqshl.u64 d31, d6, #48 @ 0x30 │ │ vmvn , │ │ vqshrun.s64 d31, q11, #15 │ │ vqshrun.s64 d31, q11, #16 │ │ vpadal.s8 , │ │ vceq.f8 , , #0 │ │ vneg.f8 , q11 │ │ vqshlu.s32 d25, d13, #16 │ │ vtbl.8 d31, {d1}, d14 │ │ vtbl.8 d31, {d0}, d14 │ │ vpadal.s8 , │ │ - vmull.u q12, d17, d27 │ │ + vabs.f8 d26, d23 │ │ vqrshrn.u64 d31, q6, #16 │ │ vqshl.u64 d25, d3, #48 @ 0x30 │ │ - vtbx.8 d24, {d17-d19}, d19 │ │ + vsli.32 q13, , #17 │ │ vqabs.s8 , q15 │ │ vmvn d25, d21 │ │ @ instruction: 0xfff1efd4 │ │ vqshl.u64 d31, d30, #47 @ 0x2f │ │ vsli.64 , , #48 @ 0x30 │ │ vneg.s8 d28, d10 │ │ movs r3, r1 │ │ @@ -328373,15 +328373,15 @@ │ │ vrsra.u64 d25, d15, #15 │ │ vtbx.8 d19, {d17}, d23 │ │ vqshlu.s64 d19, d0, #48 @ 0x30 │ │ vabs.s8 d25, d29 │ │ @ instruction: 0xfff1ed8a │ │ vqshlu.s64 , q6, #47 @ 0x2f │ │ vrsra.u32 , , #15 │ │ - vqrdmulh.s q11, , d11[0] │ │ + vtbx.8 d24, {d1}, d7 │ │ vqshlu.s64 d19, d22, #48 @ 0x30 │ │ vrsra.u32 , , #15 │ │ vcvt.f32.u32 , q13, #15 │ │ movs r3, r1 │ │ │ │ 00182340 : │ │ push {r4, r5, r7, lr} │ │ @@ -329049,15 +329049,15 @@ │ │ mov r9, r4 │ │ ldr.w r4, [r7, #-196] │ │ ldr r5, [sp, #64] @ 0x40 │ │ ldr.w r0, [sp, #2340] @ 0x924 │ │ lsls r1, r0, #17 │ │ bmi.n 182b22 │ │ b.n 182b30 │ │ - ldr r7, [sp, #248] @ 0xf8 │ │ + cbnz r2, 182b0a │ │ vsli.64 d31, d17, #48 @ 0x30 │ │ vqrdmulh.s32 , , d4[1] │ │ vmull.u q8, d0, d23 │ │ vsli.32 , , #17 │ │ @ instruction: 0xffeffda4 │ │ vpadal.s8 q10, q4 │ │ ldr r3, [sp, #88] @ 0x58 │ │ @@ -348655,16 +348655,16 @@ │ │ bl a8cf0 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r6, pc, #984 @ (adr r6, 190338 ) │ │ movs r2, r1 │ │ b.n 1904ac │ │ movs r2, r1 │ │ asrs r0, r1, #5 │ │ - vsra.u32 , , #17 │ │ - @ instruction: 0xffefc8f0 │ │ + @ instruction: 0xffefabd7 │ │ + @ instruction: 0xffefe36c │ │ vsra.u64 d30, d22, #17 │ │ movs r2, r1 │ │ │ │ 0018ff74 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -348859,15 +348859,15 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r0, sp, #24 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ b.n 1901a8 │ │ movs r2, r1 │ │ - strh r2, [r0, #22] │ │ + ldr r5, [sp, #248] @ 0xf8 │ │ vsli.32 q9, q7, #15 │ │ vqshlu.s64 , , #48 @ 0x30 │ │ @ instruction: 0xfff0dfb0 │ │ movs r2, r1 │ │ │ │ 00190160 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -349047,15 +349047,15 @@ │ │ b.n 19032e │ │ b.n 19032e │ │ add r0, sp, #132 @ 0x84 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ udf #150 @ 0x96 │ │ movs r2, r1 │ │ - strh r2, [r4, #6] │ │ + ldr r3, [sp, #376] @ 0x178 │ │ @ instruction: 0xffef3d96 │ │ vsri.64 , , #16 │ │ vqrdmulh.s , q8, d14[0] │ │ movs r2, r1 │ │ │ │ 0019034c : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -349207,16 +349207,16 @@ │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ b.n 1904da │ │ add r0, sp, #128 @ 0x80 │ │ blx 2308b0 <__emutls_get_address@@Base+0x3a28> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ble.n 190574 │ │ movs r2, r1 │ │ - ldrb r0, [r7, #28] │ │ - vrsra.u64 q14, q6, #17 │ │ + ldr r1, [sp, #720] @ 0x2d0 │ │ + vcvt.f32.u32 , q4, #17 │ │ vrsra.u32 , , #17 │ │ vmull.u , d0, d20 │ │ movs r2, r1 │ │ │ │ 001904f8 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -352427,15 +352427,15 @@ │ │ movs r2, r1 │ │ bl 3c8762 <__cxa_new_handler@@Base+0x184b72> │ │ ldr r6, [pc, #480] @ (192968 ) │ │ vtbx.8 d27, {d16-d17}, d8 │ │ movs r2, r1 │ │ strb r6, [r3, #28] │ │ vrsra.u64 , q6, #16 │ │ - vqrdmlah.s q11, q8, d11[0] │ │ + vtbx.8 d24, {d0-d1}, d7 │ │ vmls.f32 q9, , d13[1] │ │ @ instruction: 0xfff04ebc │ │ vtbl.8 d27, {d16-d17}, d30 │ │ movs r2, r1 │ │ │ │ 001927a4 : │ │ push {r4, r6, r7, lr} │ │ @@ -352636,16 +352636,16 @@ │ │ itt ne │ │ cmpne r0, #0 │ │ blxne 230900 <__emutls_get_address@@Base+0x3a78> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ @ instruction: 0xb86c │ │ movs r2, r1 │ │ lsls r1, r6, #10 │ │ - vmul.f32 q13, , d14[1] │ │ - vmull.p64 q10, d15, d13 │ │ + vmls.i32 q14, , d10[1] │ │ + vmlal.u32 q11, d31, d9 │ │ vabdl.u32 , d31, d0 │ │ movs r2, r1 │ │ │ │ 001929a4 : │ │ add.w r2, r0, #219 @ 0xdb │ │ mov r1, r0 │ │ cmp r2, #219 @ 0xdb │ │ @@ -352983,43 +352983,43 @@ │ │ add r0, pc │ │ bx lr │ │ ldr r0, [pc, #4] @ (192c5c ) │ │ add r0, pc │ │ bx lr │ │ nop │ │ subs r3, r7, #6 │ │ - vqneg.s8 d21, d25 │ │ - @ instruction: 0xffef57c1 │ │ + vpaddl.s8 d23, d21 │ │ + vrshr.u32 d23, d29, #17 │ │ vmls.i32 q15, , d9[0] │ │ vmls.i32 q15, q7, d3[1] │ │ vmla.i32 , q15, d6[1] │ │ @ instruction: 0xffeffa50 │ │ - vsri.32 d23, d20, #17 │ │ + @ instruction: 0xffef8eb0 │ │ @ instruction: 0xffefec94 │ │ - @ instruction: 0xffef9cb5 │ │ + vqshl.u32 d27, d17, #15 │ │ vcvt.u16.f16 q9, q15, #17 │ │ - vrev64.8 , │ │ + vtbx.8 d26, {d16-d18}, d17 │ │ vmls.i32 q15, , d2[1] │ │ - vcvt.f16.u16 d19, d9, #18 │ │ + vqshlu.s64 d21, d5, #46 @ 0x2e │ │ @ instruction: 0xffef2df8 │ │ vshr.u32 q8, q13, #16 │ │ @ instruction: 0xffef49a0 │ │ vshr.u64 q9, , #16 │ │ - vcvt.u32.f32 d23, d18, #17 │ │ + @ instruction: 0xffef99ae │ │ vabdl.u32 q13, d15, d29 │ │ aesimc.8 , q4 │ │ - vcvt.f16.u16 d20, d15, #16 │ │ - @ instruction: 0xffef7fb3 │ │ - vqdmulh.s32 , , d12[0] │ │ + vqshlu.s64 d22, d11, #48 @ 0x30 │ │ + vmlsl.u32 , d15, d31 │ │ + @ instruction: 0xffef5748 │ │ vmull.u32 , d31, d3 │ │ vtbx.8 d16, {d16-d17}, d0 │ │ vtbx.8 d24, {d0-d3}, d11 │ │ vpaddl.u8 d23, d8 │ │ - vsri.64 d23, d18, #16 │ │ - vabal.u32 q11, d15, d28 │ │ + @ instruction: 0xfff08f2e │ │ + @ instruction: 0xffef7fa8 │ │ vaddl.u32 q9, d31, d25 │ │ @ instruction: 0xfff0f1e4 │ │ vqrshrn.u64 d16, q12, #18 │ │ @ instruction: 0xfff0f8bd │ │ movs r2, r1 │ │ │ │ 00192ce4 : │ │ @@ -353149,15 +353149,15 @@ │ │ nop │ │ cbz r2, 192e64 │ │ movs r2, r1 │ │ ldrh.w r0, [r2, sl] │ │ beq.n 192d20 │ │ @ instruction: 0xffefd8be │ │ movs r2, r1 │ │ - ldrb r4, [r1, #22] │ │ + ldr r0, [sp, #32] │ │ vmlal.u32 , d15, d22 │ │ vpaddl.u8 , q3 │ │ movs r2, r1 │ │ │ │ 00192e30 : │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -353364,15 +353364,15 @@ │ │ ldr.w fp, [sp], #4 │ │ pop {r4, r5, r6, r7, pc} │ │ mov r0, r4 │ │ blx 2307d0 <__emutls_get_address@@Base+0x3948> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ cdp2 0, 2, cr0, cr10, cr10, {0} │ │ - cbz r2, 19307e , std::__ndk1::allocator > const&, char const*, char const*, int)@@Base+0x1a> │ │ + subs r0, #89 @ 0x59 │ │ vsra.u32 d27, d6, #17 │ │ movs r2, r1 │ │ movs r6, #88 @ 0x58 │ │ movs r2, r1 │ │ │ │ 00193028 : │ │ movw r1, #11828 @ 0x2e34 │ │ @@ -353847,15 +353847,15 @@ │ │ ldrb.w r0, [sp, #32] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #40] @ 0x28 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ - strh r6, [r6, r1] │ │ + ldr r2, [r6, #76] @ 0x4c │ │ vcvt.u32.f32 d26, d20, #17 │ │ movs r2, r1 │ │ add r5, sp, #80 @ 0x50 │ │ vpadal.u8 q13, q14 │ │ vcvt.f16.u16 d26, d18, #16 │ │ movs r2, r1 │ │ │ │ @@ -354011,15 +354011,15 @@ │ │ ldrh.w r0, [ip, sl] │ │ add r2, sp, #992 @ 0x3e0 │ │ movs r2, r1 │ │ ldr r7, [r1, r4] │ │ vrsra.u64 , q0, #16 │ │ vcvt.u32.f32 d19, d14, #16 │ │ vtbl.8 d28, {d0}, d0 │ │ - vsri.64 q10, q11, #17 │ │ + vcvt.u32.f32 , q9, #17 │ │ vshll.u32 q13, d24, #15 │ │ movs r2, r1 │ │ add r2, sp, #232 @ 0xe8 │ │ movs r2, r1 │ │ │ │ 001936d8 : │ │ push {r4, r6, r7, lr} │ │ @@ -354173,15 +354173,15 @@ │ │ cmp r1, r0 │ │ itt eq │ │ addeq sp, #16 │ │ popeq {r7, pc} │ │ blx 230610 <__emutls_get_address@@Base+0x3788> │ │ nop │ │ ldcl 0, cr0, [r5], #40 @ 0x28 │ │ - strh r0, [r1, #36] @ 0x24 │ │ + ldr r7, [sp, #16] │ │ @ instruction: 0xffefa8d4 │ │ movs r2, r1 │ │ add r0, sp, #720 @ 0x2d0 │ │ movs r2, r1 │ │ │ │ 00193818 : │ │ movs r0, #0 │ │ @@ -354529,17 +354529,17 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ lsls r1, r7, #1 │ │ movs r0, r0 │ │ add r5, pc, #808 @ (adr r5, 193e70 ) │ │ movs r2, r1 │ │ - strh r7, [r3, #10] │ │ + ldr r3, [sp, #876] @ 0x36c │ │ @ instruction: 0xffef2d27 │ │ - vqdmulh.s , q0, d9[0] │ │ + vpadal.u8 , │ │ vsli.64 d26, d18, #47 @ 0x2f │ │ movs r2, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ ldr r5, [pc, #96] @ (193bc4 ) │ │ mov r4, r0 │ │ @@ -354777,15 +354777,15 @@ │ │ mov r0, r9 │ │ blx 232590 <__emutls_get_address@@Base+0x5708> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r4, pc, #384 @ (adr r4, 193f50 ) │ │ movs r2, r1 │ │ str r4, [r1, #8] │ │ vqdmulh.s q11, q0, d8[0] │ │ - vtbx.8 d19, {d16-d17}, d7 │ │ + vcls.s8 , │ │ vmls.i32 q13, , d4[0] │ │ movs r2, r1 │ │ lsrs r7, r7, #29 │ │ vsri.64 q13, q14, #16 │ │ movs r2, r1 │ │ strh r4, [r1, r2] │ │ vrsra.u32 q13, q13, #16 │ │ @@ -354984,15 +354984,15 @@ │ │ mov r0, r8 │ │ blx 232590 <__emutls_get_address@@Base+0x5708> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r2, pc, #192 @ (adr r2, 1940c0 >&) const@@Base+0x38>) │ │ movs r2, r1 │ │ bne.n 194046 │ │ @ instruction: 0xffee5e98 │ │ - vqneg.s8 d19, d17 │ │ + vrshr.u32 d21, d13, #16 │ │ vaddw.u32 q13, , d12 │ │ movs r2, r1 │ │ │ │ 00194010 : │ │ push {r7, lr} │ │ mov r7, sp │ │ sub sp, #24 │ │ @@ -355035,15 +355035,15 @@ │ │ bl a8d68 │ │ add r1, pc, #472 @ (adr r1, 194248 >&) const@@Base+0x1c0>) │ │ movs r2, r1 │ │ add r0, pc, #560 @ (adr r0, 1942a4 >&) const@@Base+0x21c>) │ │ movs r2, r1 │ │ ldr r0, [sp, #816] @ 0x330 │ │ vpadal.u8 , │ │ - vqabs.s8 d19, d15 │ │ + vaddw.u , q8, d11 │ │ vshr.u32 q13, q10, #17 │ │ movs r2, r1 │ │ │ │ 00194084 : │ │ udf #254 @ 0xfe │ │ bmi.n 194032 │ │ │ │ @@ -355266,18 +355266,18 @@ │ │ mov r0, sl │ │ blx 232590 <__emutls_get_address@@Base+0x5708> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r7, [sp, #648] @ 0x288 │ │ movs r2, r1 │ │ ldmia r6, {r0, r1, r3, r6} │ │ vrshr.u64 , , #18 │ │ - vmls.i32 , , d11[0] │ │ + vqrdmlsh.s32 q10, , d7[0] │ │ vqshl.u32 q11, q8, #15 │ │ vrshr.u64 d31, d29, #16 │ │ - vraddhn.i64 d19, , │ │ + @ instruction: 0xffef4f25 │ │ vqrdmlah.s32 , , d4[0] │ │ movs r2, r1 │ │ │ │ 00194314 >&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, fp} │ │ @@ -355508,19 +355508,19 @@ │ │ b.n 19458e >&)@@Base+0x27a> │ │ ldr r0, [sp, #20] │ │ blx 232590 <__emutls_get_address@@Base+0x5708> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r5, [sp, #88] @ 0x58 │ │ movs r2, r1 │ │ ldmia r3!, {r0, r1, r2, r5, r7} │ │ - @ instruction: 0xffee776d │ │ - vsubl.u32 , d15, d23 │ │ + vmla.f32 , q15, d9[1] │ │ + vmull.u32 q10, d31, d19 │ │ vmls.i32 q11, , d12[0] │ │ - vqabs.s8 , │ │ - vsubl.u32 , d15, d5 │ │ + @ instruction: 0xfff091c7 │ │ + vmull.u32 q10, d31, d1 │ │ @ instruction: 0xffef9ba0 │ │ movs r2, r1 │ │ │ │ 001945b8 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -355834,15 +355834,15 @@ │ │ ldr r0, [sp, #16] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r1, [sp, #56] @ 0x38 │ │ movs r2, r1 │ │ udf #141 @ 0x8d │ │ vqrdmlah.s32 , , d1[0] │ │ - vcvt.u32.f32 q9, , #17 │ │ + vmul.f32 q10, , d15[0] │ │ vqshlu.s32 d30, d26, #15 │ │ movs r2, r1 │ │ ldr r0, [sp, #768] @ 0x300 │ │ movs r2, r1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #24 │ │ @@ -355903,15 +355903,15 @@ │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ str r7, [sp, #760] @ 0x2f8 │ │ movs r2, r1 │ │ str r6, [r3, #12] │ │ @ instruction: 0xfff0dd85 │ │ - vcvt.f32.u32 d18, d7, #17 │ │ + @ instruction: 0xffef4893 │ │ vqshl.u32 , q15, #15 │ │ movs r2, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #36 @ 0x24 │ │ mov fp, r0 │ │ @@ -356148,18 +356148,18 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ str r7, [sp, #72] @ 0x48 │ │ movs r2, r1 │ │ ldrsh r6, [r7, r1] │ │ vcvt.f32.u32 d21, d24, #16 │ │ - @ instruction: 0xfff02bb7 │ │ + vqshlu.s32 d20, d19, #16 │ │ vrshr.u32 , q4, #17 │ │ vcvt.f32.u32 d21, d4, #16 │ │ - @ instruction: 0xfff02b93 │ │ + vpadal.s8 d20, d15 │ │ vsli.64 , q10, #47 @ 0x2f │ │ movs r2, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ ldr r6, [pc, #100] @ (194ca4 ) │ │ add r6, pc │ │ @@ -356357,16 +356357,16 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bl a8d68 │ │ nop │ │ str r3, [sp, #512] @ 0x200 │ │ movs r2, r1 │ │ str r2, [sp, #952] @ 0x3b8 │ │ movs r2, r1 │ │ - cmp r0, #163 @ 0xa3 │ │ - vqrshrn.u64 d18, , #17 │ │ + orrs r7, r3 │ │ + vrsra.u64 q10, , #17 │ │ Address 0x194e4a is out of bounds. │ │ │ │ │ │ 00194e4c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ @@ -356544,16 +356544,16 @@ │ │ blx 230ee0 <__emutls_get_address@@Base+0x4058> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bl a8d68 │ │ str r1, [sp, #640] @ 0x280 │ │ movs r2, r1 │ │ str r1, [sp, #80] @ 0x50 │ │ movs r2, r1 │ │ - movs r6, #205 @ 0xcd │ │ - vabdl.u32 q9, d31, d3 │ │ + adcs r1, r1 │ │ + vsra.u64 q10, , #17 │ │ Address 0x19501e is out of bounds. │ │ │ │ │ │ 00195020 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ @@ -356776,16 +356776,16 @@ │ │ blx 230ee0 <__emutls_get_address@@Base+0x4058> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bl a8d68 │ │ ldrh r2, [r2, #58] @ 0x3a │ │ movs r2, r1 │ │ ldrh r4, [r1, #54] @ 0x36 │ │ movs r2, r1 │ │ - movs r4, #133 @ 0x85 │ │ - vsli.32 d18, d27, #15 │ │ + subs r7, #1 │ │ + @ instruction: 0xffef3fb7 │ │ Address 0x195266 is out of bounds. │ │ │ │ │ │ 00195268 , std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ @@ -356962,16 +356962,16 @@ │ │ blx 230ee0 <__emutls_get_address@@Base+0x4058> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bl a8d68 │ │ ldrh r2, [r0, #44] @ 0x2c │ │ movs r2, r1 │ │ ldrh r4, [r7, #38] @ 0x26 │ │ movs r2, r1 │ │ - movs r2, #181 @ 0xb5 │ │ - @ instruction: 0xffef236b │ │ + subs r5, #49 @ 0x31 │ │ + vqrdmulh.s32 , , d7[1] │ │ Address 0x195436 is out of bounds. │ │ │ │ │ │ 00195438 : │ │ movs r0, #0 │ │ bx lr │ │ │ │ @@ -357187,15 +357187,15 @@ │ │ movs r2, r1 │ │ str r2, [r0, r5] │ │ movs r2, r1 │ │ ldrh r6, [r6, #28] │ │ movs r2, r1 │ │ strh r4, [r2, #24] │ │ vrev16.8 d22, d29 │ │ - vsra.u32 q9, , #16 │ │ + @ instruction: 0xfff03bd3 │ │ @ instruction: 0xffef8abe │ │ movs r2, r1 │ │ │ │ 0019564c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -357542,46 +357542,46 @@ │ │ str r0, [sp, #24] │ │ beq.n 195a3a │ │ b.n 195a34 │ │ nop │ │ ldmia r5!, {r2, r3, r4, r6, r7} │ │ movs r2, r1 │ │ ldr r5, [r3, #52] @ 0x34 │ │ - aesmc.8 , q2 │ │ + @ instruction: 0xfff06e00 │ │ vsli.64 q14, q6, #47 @ 0x2f │ │ @ instruction: 0xffee7cff │ │ - vtbx.8 d23, {d0-d3}, d11 │ │ - @ instruction: 0xffef536f │ │ + vmvn , │ │ + vqrdmulh.s32 q11, , d11[1] │ │ vsri.32 d29, d31, #17 │ │ @ instruction: 0xffee6b2e │ │ - vtbl.8 d23, {d0-d3}, d23 │ │ + vmvn d25, d19 │ │ vsli.32 d30, d1, #15 │ │ vsubw.u32 q8, q15, d15 │ │ vshr.u32 d17, d12, #17 │ │ - @ instruction: 0xfff01fad │ │ + vtbl.8 d19, {d0-d2}, d25 │ │ vmls.f32 q13, , d9[0] │ │ - vmlal.u32 , d31, d3 │ │ + vrshr.u64 , , #17 │ │ vmull.u32 q11, d31, d9[1] │ │ vcvt.f32.u32 q14, , #16 │ │ - vqshl.u64 q10, , #47 @ 0x2f │ │ + vrshr.u32 q11, , #17 │ │ @ instruction: 0xffef7c9a │ │ vmvn d26, d22 │ │ vmla.i32 q14, , d5[0] │ │ vqrshrun.s64 d27, , #17 │ │ @ instruction: 0xffeed3ca │ │ vqdmulh.s32 , q15, d4[1] │ │ vsli.32 q13, , #16 │ │ vmul.i32 q15, , d11[0] │ │ vmla.f32 q8, , d6[0] │ │ - @ instruction: 0xfff02b99 │ │ + vqshlu.s32 d20, d5, #16 │ │ vrsra.u32 d27, d2, #17 │ │ @ instruction: 0xffef5e93 │ │ vrshr.u64 q8, q14, #16 │ │ vsli.32 d26, d19, #15 │ │ - @ instruction: 0xffef63cf │ │ + vqrdmlah.s32 , , d11[0] │ │ vraddhn.i64 d31, , │ │ vmlal.u32 q15, d14, d10 │ │ @ instruction: 0xffef6a7c │ │ vrsra.u32 , q13, #16 │ │ @ instruction: 0xffeebfd1 │ │ @ instruction: 0xffefbfd2 │ │ vqrdmulh.s32 q14, , d14[0] │ │ @@ -357993,15 +357993,15 @@ │ │ add r0, sp, #40 @ 0x28 │ │ blx 230dd0 <__emutls_get_address@@Base+0x3f48> │ │ b.n 195e54 │ │ ldr r0, [sp, #36] @ 0x24 │ │ blx 230de0 <__emutls_get_address@@Base+0x3f58> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ - cmp r1, #120 @ 0x78 │ │ + mvns r4, r6 │ │ @ instruction: 0xffeff89d │ │ movs r0, r5 │ │ lsls r0, r0, #31 │ │ bne.n 195e70 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r0, [sp, #48] @ 0x30 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ @@ -358009,43 +358009,43 @@ │ │ nop │ │ ldrh r0, [r3, #6] │ │ movs r2, r1 │ │ strh r0, [r0, #38] @ 0x26 │ │ movs r2, r1 │ │ bne.n 195eb4 │ │ movs r2, r1 │ │ - strh r0, [r0, #44] @ 0x2c │ │ + lsrs r7, r3, #9 │ │ vrsra.u32 d24, d12, #17 │ │ movs r2, r1 │ │ ldr.w r0, [lr, r9] │ │ vmin.f16 , , │ │ strh r2, [r4, #20] │ │ movs r2, r1 │ │ - adds r7, r0, #2 │ │ + adds r7, #3 │ │ vmlsl.u32 , d31, d15 │ │ vmvn q12, q3 │ │ movs r2, r1 │ │ bl 288e88 <__cxa_new_handler@@Base+0x45298> │ │ strh r0, [r3, #22] │ │ movs r2, r1 │ │ - subs r5, r0, r5 │ │ + adds r5, #193 @ 0xc1 │ │ vmul.f32 , , d13[0] │ │ vclz.i8 d24, d2 │ │ movs r2, r1 │ │ - adds r4, #56 @ 0x38 │ │ + ldr r6, [pc, #720] @ (196190 ) │ │ vraddhn.i64 d24, , q6 │ │ movs r2, r1 │ │ strb r6, [r3, #25] │ │ vrev32.8 q13, │ │ vsra.u32 d20, d10, #17 │ │ @ instruction: 0xfff0efbd │ │ vshr.u64 q13, q11, #18 │ │ vcvt.f32.u32 , q11, #17 │ │ vqshl.u64 d17, d31, #48 @ 0x30 │ │ - vtbl.8 d17, {d16-d17}, d31 │ │ + vcls.s8 d19, d27 │ │ vrsra.u64 q12, q11, #17 │ │ movs r2, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #44 @ 0x2c │ │ mov sl, r0 │ │ @@ -358285,27 +358285,27 @@ │ │ nop │ │ b.n 19653a │ │ vaddw.u32 q12, , d26 │ │ movs r2, r1 │ │ stmia r5!, {r1, r3, r5, r6, r7} │ │ movs r2, r1 │ │ b.n 196170 │ │ - vqrdmlsh.s32 , , d2[0] │ │ - vqshlu.s32 , , #15 │ │ + @ instruction: 0xffef59be │ │ + vshr.u64 , , #17 │ │ vshr.u64 q12, q6, #17 │ │ movs r2, r1 │ │ ldr r5, [sp, #424] @ 0x1a8 │ │ - vqshl.u64 d16, d26, #47 @ 0x2f │ │ + vrshr.u32 d18, d22, #17 │ │ vaddl.u32 q12, d31, d30 │ │ movs r2, r1 │ │ ldr r5, [sp, #240] @ 0xf0 │ │ vmull.u32 q15, d15, d16 │ │ vsra.u32 d24, d4, #18 │ │ movs r2, r1 │ │ - ldr r5, [r4, #0] │ │ + strh r1, [r4, #20] │ │ vaddw.u32 q12, , d14 │ │ movs r2, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ mov sl, r0 │ │ blx 232db0 <__emutls_get_address@@Base+0x5f28> │ │ @@ -358534,27 +358534,27 @@ │ │ movs r2, r1 │ │ strh r4, [r2, r4] │ │ vmvn d27, d0 │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (196400 ) │ │ add r0, pc │ │ bl a91f8 │ │ - strb r5, [r5, #24] │ │ + str r0, [sp, #676] @ 0x2a4 │ │ vabal.u32 , d31, d0 │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (196410 ) │ │ add r0, pc │ │ bl a91f8 │ │ - strb r5, [r3, #24] │ │ + str r0, [sp, #612] @ 0x264 │ │ vabal.u32 , d31, d0 │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (196420 ) │ │ add r0, pc │ │ bl a91f8 │ │ - strb r5, [r1, #24] │ │ + str r0, [sp, #548] @ 0x224 │ │ vsli.64 , q8, #47 @ 0x2f │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #4 │ │ mov r8, r0 │ │ ldrd r4, r0, [r0, #4] │ │ mov r5, r1 │ │ @@ -358756,15 +358756,15 @@ │ │ movs r2, r1 │ │ ldrb r2, [r2, #11] │ │ movs r2, r1 │ │ ldrb r4, [r4, #14] │ │ movs r2, r1 │ │ strb r2, [r0, #12] │ │ vsra.u32 d21, d11, #16 │ │ - vrev16.8 , │ │ + vtbx.8 d18, {d16-d19}, d1 │ │ vmlsl.u32 , d31, d28 │ │ movs r2, r1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #24 │ │ mov r4, r0 │ │ ldr r0, [pc, #132] @ (1966e8 ) │ │ @@ -358824,15 +358824,15 @@ │ │ movs r2, r1 │ │ ldrb r2, [r0, #9] │ │ movs r2, r1 │ │ ldrb r4, [r2, #12] │ │ movs r2, r1 │ │ strb r0, [r5, #9] │ │ vrev32.8 d21, d9 │ │ - vrev32.8 d17, d29 │ │ + vtbl.8 d18, {d0-d3}, d25 │ │ vshll.u32 , d12, #15 │ │ movs r2, r1 │ │ push {r7, lr} │ │ mov r7, sp │ │ movs r0, #32 │ │ blx 2306d0 <__emutls_get_address@@Base+0x3848> │ │ movs r1, #0 │ │ @@ -358927,15 +358927,15 @@ │ │ movs r2, r1 │ │ ldrb r6, [r4, #4] │ │ movs r2, r1 │ │ ldrb r0, [r7, #7] │ │ movs r2, r1 │ │ strb r6, [r2, #5] │ │ vqrdmlsh.s q10, q0, d31[0] │ │ - @ instruction: 0xfff00f99 │ │ + vshll.u32 q9, d5, #16 │ │ @ instruction: 0xffef7900 │ │ movs r2, r1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #24 │ │ mov r4, r0 │ │ ldr r0, [pc, #132] @ (196894 ) │ │ @@ -358995,15 +358995,15 @@ │ │ movs r2, r1 │ │ ldrb r6, [r2, #2] │ │ movs r2, r1 │ │ ldrb r0, [r5, #5] │ │ movs r2, r1 │ │ strb r4, [r7, #2] │ │ @ instruction: 0xfff04edd │ │ - @ instruction: 0xfff00f01 │ │ + vqrshrn.u64 d18, , #16 │ │ vqrshrun.s64 d23, q8, #17 │ │ movs r2, r1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ movs r0, #4 │ │ blx 2306d0 <__emutls_get_address@@Base+0x3848> │ │ dmb ish │ │ @@ -359109,15 +359109,15 @@ │ │ add r2, pc │ │ blx 230720 <__emutls_get_address@@Base+0x3898> │ │ mov r0, r5 │ │ blx 230730 <__emutls_get_address@@Base+0x38a8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ lsrs r0, r4, #12 │ │ vrsra.u32 q15, , #16 │ │ - vmull.p64 q8, d31, d0 │ │ + @ instruction: 0xffef28fc │ │ @ instruction: 0xffef3d26 │ │ movs r2, r1 │ │ lsls r1, r3, #7 │ │ movs r0, r0 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -359238,15 +359238,15 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strb r2, [r3, #28] │ │ movs r2, r1 │ │ strb r0, [r1, #27] │ │ movs r2, r1 │ │ strb r6, [r4, #27] │ │ movs r2, r1 │ │ - strh r3, [r7, r1] │ │ + ldr r7, [r6, #76] @ 0x4c │ │ vrsubhn.i64 d23, , q11 │ │ movs r2, r1 │ │ ldr r7, [sp, #572] @ 0x23c │ │ vmlsl.u32 , d15, d12[0] │ │ movs r2, r1 │ │ strb r2, [r4, #23] │ │ movs r2, r1 │ │ @@ -359714,15 +359714,15 @@ │ │ movs r2, r1 │ │ strb r6, [r2, #5] │ │ movs r2, r1 │ │ strb r0, [r5, #8] │ │ movs r2, r1 │ │ ldr r6, [r0, #24] │ │ vqshl.u64 d20, d15, #48 @ 0x30 │ │ - vqneg.s8 q8, │ │ + vpaddl.s8 q9, │ │ vsra.u32 d23, d16, #17 │ │ movs r2, r1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ sub sp, #24 │ │ mov r4, r0 │ │ ldr r0, [pc, #132] @ (197064 ) │ │ @@ -359782,15 +359782,15 @@ │ │ movs r2, r1 │ │ strb r6, [r0, #3] │ │ movs r2, r1 │ │ strb r0, [r3, #6] │ │ movs r2, r1 │ │ ldr r4, [r5, #12] │ │ vqabs.s8 d20, d13 │ │ - vqshl.u32 d16, d17, #16 │ │ + vaddw.u q9, q8, d29 │ │ vaddl.u32 , d31, d16 │ │ movs r2, r1 │ │ push {r7, lr} │ │ mov r7, sp │ │ movs r0, #8 │ │ blx 2306d0 <__emutls_get_address@@Base+0x3848> │ │ movs r1, #0 │ │ @@ -359803,15 +359803,15 @@ │ │ bx lr │ │ bmi.n 19704a │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (1970ac ) │ │ add r0, pc │ │ bl a91f8 │ │ - ldr r1, [r0, #24] │ │ + strh r5, [r7, #30] │ │ vsli.64 , q8, #47 @ 0x2f │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ mov r5, r0 │ │ movs r0, #1 │ │ strb.w r0, [r5, #36] @ 0x24 │ │ mov r0, r5 │ │ @@ -360454,15 +360454,15 @@ │ │ ldr r0, [sp, #20] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r4, [r7, #56] @ 0x38 │ │ movs r2, r1 │ │ cbnz r2, 197742 │ │ movs r2, r1 │ │ - lsrs r7, r1, #22 │ │ + cmp r0, #11 │ │ vsubw.u32 q15, , d31 │ │ vshll.u32 q11, d24, #15 │ │ movs r2, r1 │ │ svc 122 @ 0x7a │ │ movs r1, r1 │ │ str r6, [sp, #560] @ 0x230 │ │ vmla.f32 q10, , d4[1] │ │ @@ -361636,15 +361636,15 @@ │ │ movs r2, r1 │ │ cbnz r4, 198394 │ │ @ instruction: 0xffee5eb0 │ │ movs r2, r1 │ │ add r2, sp, #220 @ 0xdc │ │ @ instruction: 0xffee5e90 │ │ movs r2, r1 │ │ - str r2, [r7, r3] │ │ + ldr r6, [r6, #52] @ 0x34 │ │ @ instruction: 0xffef5dd8 │ │ movs r2, r1 │ │ │ │ 00198360 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -361849,21 +361849,21 @@ │ │ ldrb r2, [r7, r4] │ │ movs r2, r1 │ │ movs r4, #110 @ 0x6e │ │ movs r2, r1 │ │ add r2, sp, #488 @ 0x1e8 │ │ movs r2, r1 │ │ @ instruction: 0xfb75ffef │ │ - vpmin.f16 , , q15 │ │ - bpl.n 1985c2 │ │ + adds r5, r6, r7 │ │ + vsli.32 d29, d9, #15 │ │ vmull.u32 , d15, d18 │ │ movs r2, r1 │ │ bne.n 198660 │ │ movs r1, r1 │ │ - lsls r4, r1, #1 │ │ + subs r0, r1, r3 │ │ vraddhn.i64 d18, , q13 │ │ movs r2, r1 │ │ ldrb r2, [r4, r0] │ │ movs r2, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -362043,15 +362043,15 @@ │ │ movs r2, r1 │ │ @ instruction: 0xb714 │ │ @ instruction: 0xffee5a96 │ │ movs r2, r1 │ │ add r6, pc, #132 @ (adr r6, 1987f8 ) │ │ @ instruction: 0xffee5a7a │ │ movs r2, r1 │ │ - ldr r4, [pc, #904] @ (198b04 ) │ │ + str r6, [r3, #116] @ 0x74 │ │ vmul.f32 , , d0[0] │ │ movs r2, r1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [pc, #76] @ (1987d4 ) │ │ add r0, pc │ │ @@ -362413,28 +362413,28 @@ │ │ movs r2, r1 │ │ add r6, pc, #8 @ (adr r6, 198b34 ) │ │ movs r2, r1 │ │ ldr r4, [r6, r1] │ │ movs r2, r1 │ │ ldr r4, [r6, r1] │ │ movs r2, r1 │ │ - adds r4, #12 │ │ + ldr r6, [pc, #544] @ (198d58 ) │ │ vqshrun.s64 d21, q6, #17 │ │ movs r2, r1 │ │ strb r6, [r4, r7] │ │ movs r2, r1 │ │ bl 3bb22 │ │ cmp r6, #82 @ 0x52 │ │ vqshl.u64 d21, d6, #48 @ 0x30 │ │ movs r2, r1 │ │ ldrsb r6, [r2, r5] │ │ movs r2, r1 │ │ ldrsb r4, [r2, r5] │ │ movs r2, r1 │ │ - ldr r1, [pc, #520] @ (198d60 ) │ │ + str r6, [r7, #60] @ 0x3c │ │ vqshlu.s64 , q14, #47 @ 0x2f │ │ movs r2, r1 │ │ bl fff1fb3e <__cxa_new_handler@@Base+0xffcdbf4e> │ │ cmp r5, #54 @ 0x36 │ │ vqshlu.s32 , q13, #16 │ │ movs r2, r1 │ │ ldrsb r2, [r0, r4] │ │ @@ -362674,18 +362674,18 @@ │ │ ldr r0, [sp, #8] │ │ blx 232590 <__emutls_get_address@@Base+0x5708> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strb r2, [r5, r4] │ │ movs r2, r1 │ │ bge.n 198d96 │ │ @ instruction: 0xffefa7c3 │ │ - vsli.64 q10, q7, #47 @ 0x2f │ │ + vshr.u32 q11, q5, #17 │ │ @ instruction: 0xffefbf92 │ │ vabdl.u32 q13, d30, d17 │ │ - vsli.64 d20, d28, #47 @ 0x2f │ │ + vshr.u32 d22, d24, #17 │ │ @ instruction: 0xffef5362 │ │ movs r2, r1 │ │ push {r4, r5, r7, lr} │ │ add r7, sp, #8 │ │ ldr r5, [pc, #72] @ (198e80 ) │ │ add r5, pc │ │ ldrb.w r0, [r5, #32] │ │ @@ -362836,18 +362836,18 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r7, [sp, #632] @ 0x278 │ │ movs r2, r1 │ │ strh r0, [r1, r0] │ │ movs r2, r1 │ │ ldr r5, [r2, #112] @ 0x70 │ │ - @ instruction: 0xffef2d8c │ │ + vmlal.u32 q10, d15, d8 │ │ vshr.u32 , q1, #17 │ │ @ instruction: 0xffef1af5 │ │ - vqrdmulh.s q9, q0, d24[0] │ │ + vqneg.s8 q10, q10 │ │ vaddl.u32 , d15, d30 │ │ vsra.u64 d21, d2, #17 │ │ movs r2, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ ldr r5, [pc, #132] @ (199068 ) │ │ @@ -364655,15 +364655,15 @@ │ │ ldmia.w sp!, {r4, r5, r7, lr} │ │ b.w 2300a8 <__emutls_get_address@@Base+0x3220> │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (19a300 ) │ │ add r0, pc │ │ bl a91f8 │ │ - adds r7, #45 @ 0x2d │ │ + str r1, [r5, r6] │ │ vsli.64 , q8, #47 @ 0x2f │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ mov r5, r0 │ │ movs r0, #1 │ │ strb.w r0, [r5, #36] @ 0x24 │ │ mov r0, r5 │ │ @@ -364756,15 +364756,15 @@ │ │ blx 2319f0 <__emutls_get_address@@Base+0x4b68> │ │ str r0, [r4, #12] │ │ pop {r4, r6, r7, pc} │ │ nop │ │ lsls r5, r5, #25 │ │ vtbx.8 d24, {d0-d2}, d26 │ │ movs r2, r1 │ │ - stmia r5!, {r1, r4, r6} │ │ + svc 206 @ 0xce │ │ vmlsl.u32 q8, d14, d9[1] │ │ Address 0x19a406 is out of bounds. │ │ │ │ │ │ 0019a408 : │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -364939,15 +364939,15 @@ │ │ lsls r6, r3, #16 │ │ movs r2, r1 │ │ subs r4, #70 @ 0x46 │ │ movs r2, r1 │ │ subs r3, #62 @ 0x3e │ │ movs r2, r1 │ │ beq.n 19a624 , std::__ndk1::allocator > > const&, std::__ndk1::vector >&, float, float, int, int)@@Base+0x4c> │ │ - vrsra.u64 d28, d25, #17 │ │ + vcvt.f32.u32 d29, d21, #17 │ │ vmlsl.u32 q15, d14, d1 │ │ Address 0x19a5d6 is out of bounds. │ │ │ │ │ │ 0019a5d8 , std::__ndk1::allocator > > const&, std::__ndk1::vector >&, float, float, int, int)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -365865,15 +365865,15 @@ │ │ bl 19b17c │ │ bl c71d0 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (19b188 ) │ │ add r0, pc │ │ bl a91f8 │ │ - cmp r0, #165 @ 0xa5 │ │ + orrs r1, r4 │ │ Address 0x19b18a is out of bounds. │ │ │ │ │ │ 0019b18c : │ │ vmov.i32 q8, #0 @ 0x00000000 │ │ strd r1, r1, [r0] │ │ add.w r1, r0, #8 │ │ @@ -365996,15 +365996,15 @@ │ │ str r0, [sp, #0] │ │ mvn.w r0, #214 @ 0xd6 │ │ blx 2306b0 <__emutls_get_address@@Base+0x3828> │ │ bl a8d68 │ │ nop │ │ cmp r6, #232 @ 0xe8 │ │ movs r2, r1 │ │ - asrs r5, r6, #24 │ │ + adds r0, #177 @ 0xb1 │ │ vshr.u64 d17, d20, #17 │ │ vpaddl.u8 q12, │ │ vcvt.f32.u32 d18, d6, #17 │ │ movs r2, r1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ ldr r4, [pc, #248] @ (19b3e0 ) │ │ @@ -366599,15 +366599,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ movs r7, #246 @ 0xf6 │ │ movs r2, r1 │ │ - ldmia r3, {r1, r3, r5, r6} │ │ + b.n 19b53c │ │ vmul.f32 , q15, d12[0] │ │ vcvt.f16.u16 , , #17 │ │ vsli.64 , q3, #47 @ 0x2f │ │ movs r2, r1 │ │ movs r7, #138 @ 0x8a │ │ movs r2, r1 │ │ │ │ @@ -368685,30 +368685,30 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ asrs r4, r0, #15 │ │ movs r2, r1 │ │ subs r6, #196 @ 0xc4 │ │ - vsra.u64 d27, d10, #18 │ │ + vcvt.f16.u16 d28, d6, #18 │ │ vqshl.u32 d22, d1, #14 │ │ @ instruction: 0xffef7ab8 │ │ - vmla.f32 , q15, d2[1] │ │ + vcvt.f16.u16 q14, q7, #18 │ │ vqshl.u32 q11, , #14 │ │ vrsra.u32 , q4, #17 │ │ movs r2, r1 │ │ - add r5, pc, #460 @ (adr r5, 19d0a4 ) │ │ - vsra.u64 d27, d30, #18 │ │ - vqshl.u32 d22, d21, #14 │ │ + iteee al │ │ + vcvtal.f16.u16 d28, d26, #18 │ │ + vqshl.u32 d22, d21, #14 │ │ Address 0x19cede is out of bounds. │ │ │ │ │ │ 0019cee0 : │ │ push {r4, r6, r7, lr} │ │ - add r7, sp, #8 │ │ + add r7, sp, #8 │ │ mov r4, r0 │ │ ldr r0, [r0, #0] │ │ ldr r1, [r4, #4] │ │ ldrd r2, r3, [r4, #32] │ │ bl 11a2ac │ │ str r0, [r4, #0] │ │ pop {r4, r6, r7, pc} │ │ @@ -369589,18 +369589,18 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #12] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ lsrs r4, r5, #9 │ │ movs r2, r1 │ │ - pldw [r9, #4078] @ 0xfee │ │ - svc 164 @ 0xa4 │ │ + asrs r5, r6, #12 │ │ + @ instruction: 0xffefdfa4 │ │ vqrdmulh.s32 , , d13[0] │ │ - @ instruction: 0xffefdcf9 │ │ + vqshl.u32 , , #15 │ │ vaddl.u32 q15, d30, d4 │ │ vmull.p64 , d31, d29 │ │ @ instruction: 0xffef0904 │ │ movs r2, r1 │ │ │ │ 0019d814 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -369889,16 +369889,16 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ lsls r6, r5, #27 │ │ movs r2, r1 │ │ - @ instruction: 0xe9acffee │ │ - bgt.n 19dc20 │ │ + lsls r0, r5, #16 │ │ + vcvt.f16.u16 , q14, #17 │ │ vmlsl.u32 , d31, d21 │ │ vqrdmlah.s32 , , d14[0] │ │ @ instruction: 0xffeedd2e │ │ @ instruction: 0xffef5b57 │ │ vsli.64 q8, q6, #47 @ 0x2f │ │ movs r2, r1 │ │ │ │ @@ -370003,15 +370003,15 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r0, [sp, #16] │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ lsls r6, r3, #21 │ │ movs r2, r1 │ │ - lsls r5, r7, #13 │ │ + adds r1, r7, #7 │ │ vcvt.f16.u16 , , #17 │ │ @ instruction: 0xffef5995 │ │ vmls.i32 q8, , d10[0] │ │ movs r2, r1 │ │ │ │ 0019dc4c &, cv::Point_&) const@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ @@ -370108,17 +370108,17 @@ │ │ itt ne │ │ ldrne r0, [sp, #20] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ lsls r6, r1, #17 │ │ movs r2, r1 │ │ - lsls r5, r3, #10 │ │ - @ instruction: 0xffeff365 │ │ - vqrshrun.s64 d21, , #18 │ │ + adds r1, r3, #4 │ │ + vqrdmulh.s32 q8, , d1[1] │ │ + vqrshrun.s64 d21, , #17 │ │ vsubw.u32 q8, , d30 │ │ movs r2, r1 │ │ │ │ 0019dd5c : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ @@ -370240,15 +370240,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #28] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ lsls r6, r7, #12 │ │ movs r2, r1 │ │ - lsls r1, r1, #5 │ │ + subs r5, r0, r7 │ │ @ instruction: 0xffefd365 │ │ vabdl.u32 , d15, d21 │ │ vrshr.u32 q8, q6, #17 │ │ movs r2, r1 │ │ │ │ 0019deb0 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -370474,28 +370474,28 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ b.n 19e112 │ │ mov r0, r8 │ │ blx 230a40 <__emutls_get_address@@Base+0x3bb8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ lsls r6, r4, #7 │ │ movs r2, r1 │ │ - vpmin.f32 , , q15 │ │ - strh r7, [r0, #0] │ │ + adds r7, r4, r6 │ │ + vaddl.u32 q12, d15, d7 │ │ vmls.f32 , , d3[0] │ │ @ instruction: 0xffefdb0b │ │ vqrdmlsh.s32 , , d3[0] │ │ vsri.64 , , #17 │ │ @ instruction: 0xffef8b02 │ │ @ instruction: 0xffef7fa1 │ │ vsri.64 , , #17 │ │ vrsra.u32 d28, d25, #17 │ │ vcvt.u32.f32 , , #17 │ │ vsri.64 d21, d27, #17 │ │ - @ instruction: 0xffeff8bf │ │ - vqrdmlsh.s32 , q15, d5[1] │ │ + vrsra.u32 d17, d27, #17 │ │ + vqrdmlsh.s32 , , d5[1] │ │ vabal.u32 , d15, d17 │ │ vshr.u32 q8, q11, #17 │ │ movs r2, r1 │ │ │ │ 0019e160 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -370591,15 +370591,15 @@ │ │ lsls r0, r0, #31 │ │ bne.n 19e256 │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r0, [sp, #48] @ 0x30 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ vhadd.u d0, d8, d9 │ │ - str r1, [sp, #952] @ 0x3b8 │ │ + add r4, sp, #424 @ 0x1a8 │ │ vqshlu.s32 d27, d23, #14 │ │ vrsra.u32 , , #17 │ │ vmull.p64 , d31, d26 │ │ movs r1, r1 │ │ │ │ 0019e274 : │ │ push {r7, lr} │ │ @@ -371081,15 +371081,15 @@ │ │ add r0, sp, #20 │ │ blx 233050 <__emutls_get_address@@Base+0x61c8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ bl a8d68 │ │ nop │ │ @ instruction: 0xfa640009 │ │ ldrsh.w r0, [r0, #9] │ │ - stmia r4!, {r1, r3, r4, r5, r6} │ │ + udf #246 @ 0xf6 │ │ vqrdmlah.s32 q12, q15, d9[0] │ │ vcvt.f32.u32 q10, , #17 │ │ Address 0x19e78a is out of bounds. │ │ │ │ │ │ 0019e78c : │ │ push {r4, r5, r7, lr} │ │ @@ -371166,15 +371166,15 @@ │ │ ldrb.w r0, [sp, #8] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldrsb.w r0, [r0, r9] │ │ - add r4, pc, #496 @ (adr r4, 19ea38 ) │ │ + bkpt 0x00f8 │ │ vmls.f32 , q7, d7[1] │ │ @ instruction: 0xffee4da5 │ │ @ instruction: 0xffef73c7 │ │ vmls.f32 , q7, d3[0] │ │ @ instruction: 0xffee4d81 │ │ @ instruction: 0xffeff8d6 │ │ movs r1, r1 │ │ @@ -372246,21 +372246,21 @@ │ │ nop │ │ subs r4, r3, r6 │ │ vshr.u32 , q9, #17 │ │ movs r1, r1 │ │ eor.w r0, lr, #9 │ │ eor.w r0, ip, #9 │ │ eor.w r0, sl, #9 │ │ - ldrb r0, [r4, #5] │ │ + str r3, [sp, #880] @ 0x370 │ │ vshr.u32 , q15, #18 │ │ movs r1, r1 │ │ ldr r0, [r1, #48] @ 0x30 │ │ - @ instruction: 0xffeeba9d │ │ - @ instruction: 0xffeecab7 │ │ - vmul.f32 , q7, d13[0] │ │ + vsli.32 d29, d9, #14 │ │ + vsli.32 d30, d19, #14 │ │ + @ instruction: 0xffeed3c9 │ │ vrsra.u32 d20, d2, #18 │ │ @ instruction: 0xffefed90 │ │ movs r1, r1 │ │ ldrb.w r0, [sl] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne.w r0, [sl, #8] │ │ @@ -372485,16 +372485,16 @@ │ │ and.w r0, r0, r6, lsl #1 │ │ b.n 19f610 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x5f8> │ │ str r0, [sp, #224] @ 0xe0 │ │ strd r0, r0, [sp, #216] @ 0xd8 │ │ b.n 19fb92 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0xb7a> │ │ subs r3, #190 @ 0xbe │ │ movs r2, r1 │ │ - ldmia r0, {r0, r4, r7} │ │ - vabdl.u32 , d14, d21 │ │ + b.n 19fc06 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0xbee> │ │ + vaddw.u32 , q15, d17 │ │ vmla.i32 q10, q15, d8[1] │ │ vmla.i32 , , d6[0] │ │ movs r7, r1 │ │ add.w r9, r0, #1 │ │ mov r0, r9 │ │ blx 2306d0 <__emutls_get_address@@Base+0x3848> │ │ mov r5, r0 │ │ @@ -372977,21 +372977,21 @@ │ │ blx 230de0 <__emutls_get_address@@Base+0x3f58> │ │ movs r4, #0 │ │ ldr.w sl, [sp, #80] @ 0x50 │ │ add r5, sp, #192 @ 0xc0 │ │ b.n 19fb5e , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0xb46> │ │ nop │ │ movs r1, #254 @ 0xfe │ │ - vshr.u32 q12, q10, #17 │ │ - vsri.32 d27, d3, #18 │ │ - vraddhn.i64 d28, q7, │ │ - vsubl.u32 , d30, d19 │ │ + @ instruction: 0xffef9af0 │ │ + vmull.p64 q14, d30, d15 │ │ + vmull.p64 , d30, d11 │ │ + vcvt.u16.f16 d28, d15, #18 │ │ vqdmulh.s32 , q7, d4[1] │ │ vmls.i32 q13, , d2[0] │ │ - vaddw.u32 , , d25 │ │ + @ instruction: 0xffefcba5 │ │ vqshlu.s32 q10, , #14 │ │ blx 2325e0 <__emutls_get_address@@Base+0x5758> │ │ ldrb.w r0, [sp, #192] @ 0xc0 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #200] @ 0xc8 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ @@ -373470,20 +373470,20 @@ │ │ blx 230de0 <__emutls_get_address@@Base+0x3f58> │ │ movs r4, #0 │ │ ldr.w sl, [sp, #80] @ 0x50 │ │ add r5, sp, #180 @ 0xb4 │ │ b.n 1a00b2 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x109a> │ │ adds r0, r6, #2 │ │ vraddhn.i64 d17, , │ │ - vqrdmlah.s32 q13, q15, d5[0] │ │ - @ instruction: 0xffeebebf │ │ - vcvt.u16.f16 q13, , #18 │ │ + vmul.f32 q14, q7, d1[0] │ │ + vqshrn.u64 d29, , #18 │ │ + @ instruction: 0xffeec7cd │ │ vqshl.u32 d19, d0, #14 │ │ vmla.f32 q10, , d3[0] │ │ - @ instruction: 0xffefabd5 │ │ + vqshlu.s32 q14, , #15 │ │ vqshlu.s32 q10, , #14 │ │ blx 2325e0 <__emutls_get_address@@Base+0x5758> │ │ ldrb.w r0, [sp, #180] @ 0xb4 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #188] @ 0xbc │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ @@ -373621,17 +373621,17 @@ │ │ blx 230de0 <__emutls_get_address@@Base+0x3f58> │ │ ldr.w sl, [sp, #80] @ 0x50 │ │ movs r0, #0 │ │ strd r0, r0, [sl] │ │ str.w r0, [sl, #8] │ │ b.w 1a1c6e , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x2c56> │ │ nop │ │ - cbnz r1, 1a02a0 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x1288> │ │ + bvs.n 1a02c6 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x12ae> │ │ @ instruction: 0xffee5a9e │ │ - vmlsl.u32 q13, d14, d27 │ │ + vraddhn.i64 d28, q15, │ │ vshr.u32 d25, d21, #18 │ │ strd r0, r0, [sp, #204] @ 0xcc │ │ add r0, sp, #192 @ 0xc0 │ │ blx 2330a0 <__emutls_get_address@@Base+0x6218> │ │ movs r0, #112 @ 0x70 │ │ blx 2306d0 <__emutls_get_address@@Base+0x3848> │ │ ldr r1, [pc, #40] @ (1a0270 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x1258>) │ │ @@ -373722,17 +373722,16 @@ │ │ ldr r3, [r3, #0] │ │ str r5, [r2, #0] │ │ add.w r9, r3, #8 │ │ str.w r9, [sp, #252] @ 0xfc │ │ movs r2, #69 @ 0x45 │ │ bl c30b0 │ │ b.n 1a0348 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x1330> │ │ - beq.n 1a0330 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x1318> │ │ - @ instruction: 0xffeef89d │ │ - adds r0, #192 @ 0xc0 │ │ + @ instruction: 0xeb70ffee │ │ + ldrb.w r3, [sp, #192] @ 0xc0 │ │ ldrd r2, r1, [sp, #196] @ 0xc4 │ │ ands.w r5, r3, #1 │ │ add r5, sp, #192 @ 0xc0 │ │ itt eq │ │ addeq r1, r5, #1 │ │ lsreq r2, r3, #1 │ │ bl c30b0 │ │ @@ -374098,21 +374097,21 @@ │ │ bl 1a2a9c , std::__ndk1::allocator > const&, bool, char const*)@@Base+0x2ac> │ │ ldr r5, [r4, #0] │ │ ldrd r0, r1, [r5] │ │ str.w fp, [sp, #84] @ 0x54 │ │ cmp r1, r0 │ │ bne.w 19f39a , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x382> │ │ b.w 19f558 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x540> │ │ - add r0, sp, #428 @ 0x1ac │ │ + stmia r2!, {r0, r1, r2, r5, r6, r7} │ │ vsri.32 q11, q6, #18 │ │ vqshlu.s32 , q9, #15 │ │ - vqshl.u32 q13, , #15 │ │ + vsra.u64 q14, , #17 │ │ vmls.f32 , q15, d6[1] │ │ - vmlsl.u32 , d31, d5[1] │ │ - vsli.32 q13, , #14 │ │ + vmla.f32 , , d1[1] │ │ + vqrdmlsh.s32 , q15, d15[1] │ │ vcvt.u32.f32 d18, d18, #18 │ │ vaddl.u32 q9, d15, d0 │ │ str r0, [sp, #20] │ │ movs r0, #0 │ │ strd r0, r0, [sp, #168] @ 0xa8 │ │ str r0, [sp, #176] @ 0xb0 │ │ add r0, sp, #152 @ 0x98 │ │ @@ -374346,15 +374345,15 @@ │ │ ldr r3, [r3, #0] │ │ str r5, [r2, #0] │ │ add.w r8, r3, #8 │ │ str.w r8, [sp, #252] @ 0xfc │ │ movs r2, #70 @ 0x46 │ │ bl c30b0 │ │ b.n 1a0a18 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x1a00> │ │ - ldrb r3, [r7, #10] │ │ + str r5, [sp, #220] @ 0xdc │ │ @ instruction: 0xffeef89d │ │ adds r0, #168 @ 0xa8 │ │ add r5, sp, #168 @ 0xa8 │ │ ldrd r2, r1, [sp, #172] @ 0xac │ │ ands.w r6, r3, #1 │ │ itt eq │ │ addeq r1, r5, #1 │ │ @@ -374379,15 +374378,15 @@ │ │ mov.w r3, #320 @ 0x140 │ │ strd r0, r1, [sp] │ │ movs r0, #5 │ │ mov r1, r4 │ │ blx 230db0 <__emutls_get_address@@Base+0x3f28> │ │ b.n 1a0a6c , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x1a54> │ │ nop │ │ - add r1, pc, #620 @ (adr r1, 1a0cd8 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x1cc0>) │ │ + pop {r0, r1, r2, r4} │ │ @ instruction: 0xffeef89d │ │ lsls r0, r1, #2 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #144] @ 0x90 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ ldrb.w r0, [sp, #284] @ 0x11c │ │ @@ -374805,20 +374804,20 @@ │ │ str r6, [sp, #240] @ 0xf0 │ │ strd r9, r8, [sp, #248] @ 0xf8 │ │ itt ne │ │ ldrne r0, [sp, #292] @ 0x124 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ mov r0, sl │ │ b.n 1a1026 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x200e> │ │ - add r0, pc, #428 @ (adr r0, 1a10c4 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x20ac>) │ │ - vaddl.u32 , d14, d21 │ │ - @ instruction: 0xffee9eb3 │ │ + revsh r7, r4 │ │ + vmlsl.u32 q14, d30, d17 │ │ + @ instruction: 0xffeeb92f │ │ vqrshrun.s64 d18, q9, #18 │ │ - vmls.f32 q14, , d12[1] │ │ - vcvt.u16.f16 d25, d5, #18 │ │ + vmla.i32 q15, , d8[1] │ │ + vqshl.u64 d27, d1, #46 @ 0x2e │ │ vaddl.u32 , d30, d15 │ │ vmax.s32 d4, d8, d4 │ │ cbz r0, 1a0f3c , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x1f24> │ │ ldr r0, [r4, #4] │ │ cmp r0, #4 │ │ blt.w 1a1040 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x2028> │ │ ldr r0, [sp, #64] @ 0x40 │ │ @@ -374884,15 +374883,15 @@ │ │ movw r3, #341 @ 0x155 │ │ strd r0, r1, [sp] │ │ movs r0, #4 │ │ mov r1, r4 │ │ blx 230db0 <__emutls_get_address@@Base+0x3f28> │ │ b.n 1a0ffc , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x1fe4> │ │ nop │ │ - ldr r4, [sp, #44] @ 0x2c │ │ + @ instruction: 0xb687 │ │ @ instruction: 0xffeef89d │ │ lsls r4, r7, #1 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #132] @ 0x84 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ ldrb.w r0, [sp, #284] @ 0x11c │ │ @@ -375021,15 +375020,15 @@ │ │ mov.w r3, #348 @ 0x15c │ │ strd r0, r1, [sp] │ │ movs r0, #5 │ │ mov r1, r4 │ │ blx 230db0 <__emutls_get_address@@Base+0x3f28> │ │ b.n 1a1178 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x2160> │ │ nop │ │ - ldr r2, [sp, #572] @ 0x23c │ │ + push {r0, r1, r3, lr} │ │ @ instruction: 0xffeef89d │ │ lsls r4, r7, #1 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #132] @ 0x84 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ ldrb.w r0, [sp, #284] @ 0x11c │ │ @@ -375126,15 +375125,15 @@ │ │ mov.w r3, #352 @ 0x160 │ │ strd r0, r1, [sp] │ │ movs r0, #5 │ │ mov r1, r4 │ │ blx 230db0 <__emutls_get_address@@Base+0x3f28> │ │ b.n 1a129c , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x2284> │ │ nop │ │ - ldr r1, [sp, #428] @ 0x1ac │ │ + cbz r7, 1a1314 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x22fc> │ │ @ instruction: 0xffeef89d │ │ lsls r4, r7, #1 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #132] @ 0x84 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ ldrb.w r0, [sp, #284] @ 0x11c │ │ @@ -375272,15 +375271,15 @@ │ │ it eq │ │ moveq r3, r0 │ │ add r0, sp, #100 @ 0x64 │ │ mov.w r2, #360 @ 0x168 │ │ blx 2307c0 <__emutls_get_address@@Base+0x3938> │ │ b.n 1a142c , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x2414> │ │ nop │ │ - add r0, sp, #948 @ 0x3b4 │ │ + stmia r3!, {r0, r3, r5, r6} │ │ @ instruction: 0xffeef89d │ │ lsls r4, r4, #1 │ │ ldrd r2, r1, [sp, #104] @ 0x68 │ │ ands.w r3, r0, #1 │ │ ldr r3, [sp, #48] @ 0x30 │ │ itt eq │ │ moveq r1, r3 │ │ @@ -375644,21 +375643,21 @@ │ │ ldrne r0, [sp, #108] @ 0x6c │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ subs r4, #1 │ │ sub.w r6, r6, #12 │ │ add r5, sp, #100 @ 0x64 │ │ bne.w 1a1690 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x2678> │ │ b.n 1a18cc , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x28b4> │ │ - str r7, [sp, #460] @ 0x1cc │ │ + cbz r7, 1a1866 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x284e> │ │ vsra.u32 d18, d22, #18 │ │ vsri.64 d28, d14, #17 │ │ vmla.i32 q9, , d7[0] │ │ - vmls.f32 , , d1[1] │ │ - vsli.64 q13, , #46 @ 0x2e │ │ - vmls.i32 , q7, d11[1] │ │ + vshr.u32 , , #17 │ │ + vshr.u32 q14, , #18 │ │ + vqrdmlah.s32 q13, q15, d7[1] │ │ vcvt.f32.u32 d17, d16, #18 │ │ vaddl.u32 , d31, d15 │ │ eors.w r6, sl, r4, lsl #16 │ │ cbz r0, 1a1856 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x283e> │ │ ldr r0, [r4, #4] │ │ cmp r0, #5 │ │ blt.n 1a18cc , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x28b4> │ │ @@ -375668,15 +375667,15 @@ │ │ ldr r1, [pc, #16] @ (1a1870 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x2858>) │ │ add r1, pc │ │ add.w r0, r5, #8 │ │ movs r2, #56 @ 0x38 │ │ bl c30b0 │ │ b.n 1a1874 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x285c> │ │ nop │ │ - strh r3, [r6, #62] @ 0x3e │ │ + add r2, pc, #444 @ (adr r2, 1a1a30 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x2a18>) │ │ vqshrn.u64 d26, q6, #18 │ │ bl c919c │ │ cmp r4, #0 │ │ ite ne │ │ ldrne r4, [r4, #0] │ │ moveq r4, #0 │ │ add.w r1, r5, #12 │ │ @@ -375694,15 +375693,15 @@ │ │ movw r3, #389 @ 0x185 │ │ strd r0, r1, [sp] │ │ movs r0, #5 │ │ mov r1, r4 │ │ blx 230db0 <__emutls_get_address@@Base+0x3f28> │ │ b.n 1a18b8 , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x28a0> │ │ nop │ │ - str r3, [sp, #316] @ 0x13c │ │ + add r5, sp, #812 @ 0x32c │ │ @ instruction: 0xffeef89d │ │ lsls r4, r4, #1 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #108] @ 0x6c │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ add r0, sp, #240 @ 0xf0 │ │ @@ -376125,17 +376124,17 @@ │ │ ldr r0, [sp, #144] @ 0x90 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ b.w 1a096e , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x1956> │ │ blx 2325e0 <__emutls_get_address@@Base+0x5758> │ │ b.n 1a1c1a , std::__ndk1::allocator > const&, char const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*, std::__ndk1::vector, std::__ndk1::allocator >, std::__ndk1::allocator, std::__ndk1::allocator > > > const*)@@Base+0x2c02> │ │ movs r3, #234 @ 0xea │ │ vrsra.u64 d19, d28, #18 │ │ - vsra.u64 , , #18 │ │ - vsubl.u32 q13, d14, d3 │ │ - vshr.u64 d25, d1, #18 │ │ + vcvt.f16.u16 q13, , #18 │ │ + vcvt.f16.u16 , , #18 │ │ + @ instruction: 0xffeeab0d │ │ @ instruction: 0xffee1a54 │ │ vshr.u64 d31, d0, #17 │ │ ldc 8, cr15, [ip], #-628 @ 0xfffffd8c │ │ lsls r4, r4, #1 │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #108] @ 0x6c │ │ @@ -377152,20 +377151,20 @@ │ │ movs r1, r1 │ │ cbnz r0, 1a2818 , std::__ndk1::allocator > const&, bool, char const*)@@Base+0x28> │ │ movs r1, r1 │ │ asrs r1, r6, #1 │ │ @ instruction: 0xffefbaf6 │ │ movs r1, r1 │ │ ldr r0, [r4, #28] │ │ - vmla.f32 , , d7[0] │ │ - vaddw.u32 , q15, d28 │ │ + vqdmulh.s32 q11, , d3[0] │ │ + vmull.u32 q11, d14, d24 │ │ vqshrun.s64 d29, q9, #18 │ │ vqrshrn.u64 d27, q2, #18 │ │ movs r1, r1 │ │ - strh r3, [r3, #42] @ 0x2a │ │ + ldr r7, [sp, #860] @ 0x35c │ │ @ instruction: 0xffee1ad7 │ │ vshll.u32 , d2, #15 │ │ movs r1, r1 │ │ cbnz r4, 1a281e , std::__ndk1::allocator > const&, bool, char const*)@@Base+0x2e> │ │ movs r1, r1 │ │ │ │ 001a27f0 , std::__ndk1::allocator > const&, bool, char const*)@@Base>: │ │ @@ -377410,29 +377409,29 @@ │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ @ instruction: 0xb8a6 │ │ movs r1, r1 │ │ @ instruction: 0xb8b2 │ │ movs r1, r1 │ │ @ instruction: 0xb8b2 │ │ movs r1, r1 │ │ - ldrb r0, [r5, r1] │ │ + strb r4, [r4, #27] │ │ vqrshrun.s64 d27, q4, #18 │ │ movs r1, r1 │ │ ldr r3, [pc, #888] @ (1a2dec , std::__ndk1::allocator > const&, std::__ndk1::basic_string, std::__ndk1::allocator > const&)@@Base+0x1e8>) │ │ - vmlal.u32 q11, d15, d30 │ │ + vsubl.u32 q12, d31, d26 │ │ vmlal.u32 , d30, d13 │ │ vrsubhn.i64 d27, , q10 │ │ movs r1, r1 │ │ - strh r3, [r6, #20] │ │ - vaddl.u32 q10, d30, d6 │ │ + ldr r5, [sp, #188] @ 0xbc │ │ + @ instruction: 0xffee5b02 │ │ @ instruction: 0xffeeb764 │ │ movs r1, r1 │ │ - add r2, sp, #600 @ 0x258 │ │ - @ instruction: 0xffee3fd0 │ │ - vsra.u64 q12, , #18 │ │ + stmia r5!, {r1, r4} │ │ + vmull.u32 , d14, d12[0] │ │ + vcvt.f16.u16 , , #18 │ │ vmlsl.u32 , d30, d12[1] │ │ movs r1, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ mov r4, r1 │ │ mov r6, r0 │ │ @@ -378500,15 +378499,15 @@ │ │ vrshr.u32 d26, d5, #17 │ │ @ instruction: 0xffefada0 │ │ movs r1, r1 │ │ add r5, sp, #120 @ 0x78 │ │ movs r1, r1 │ │ add r5, sp, #120 @ 0x78 │ │ movs r1, r1 │ │ - add r0, pc, #536 @ (adr r0, 1a37a0 , std::__ndk1::allocator > const&)@@Base+0x48>) │ │ + cbnz r2, 1a35c8 │ │ vqdmulh.s32 q13, q15, d4[0] │ │ movs r1, r1 │ │ add r3, sp, #1000 @ 0x3e8 │ │ movs r1, r1 │ │ ldr r3, [r1, #44] @ 0x2c │ │ vaddl.u32 q13, d31, d23 │ │ vcvt.f16.u16 d26, d18, #17 │ │ @@ -378994,15 +378993,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #12] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r6, pc, #904 @ (adr r6, 1a3dc0 ) │ │ movs r1, r1 │ │ - str r2, [r1, #104] @ 0x68 │ │ + strh r6, [r0, #8] │ │ vaddl.u32 , d30, d6 │ │ vabal.u32 q11, d15, d31 │ │ vqshlu.s64 d26, d28, #47 @ 0x2f │ │ movs r1, r1 │ │ │ │ 001a3a48 : │ │ push {r4, r6, r7, lr} │ │ @@ -379053,16 +379052,16 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #12] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r6, pc, #344 @ (adr r6, 1a3c1c ) │ │ movs r1, r1 │ │ - ldrh r5, [r3, #50] @ 0x32 │ │ - vrsubhn.i64 d22, q7, q0 │ │ + add r0, sp, #868 @ 0x364 │ │ + vshr.u32 q12, q14, #18 │ │ vraddhn.i64 d22, q15, │ │ vqshlu.s32 d26, d16, #15 │ │ movs r1, r1 │ │ │ │ 001a3ad4 : │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ @@ -379169,15 +379168,15 @@ │ │ itt ne │ │ ldrne r0, [sp, #12] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ add r5, pc, #264 @ (adr r5, 1a3ce0 ) │ │ movs r1, r1 │ │ lsls r0, r1, #7 │ │ - @ instruction: 0xffee990a │ │ + vsubw.u32 , q15, d6 │ │ vsubw.u32 q11, q15, d15 │ │ vsli.32 d26, d12, #15 │ │ movs r1, r1 │ │ │ │ 001a3be8 : │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ @@ -379550,15 +379549,15 @@ │ │ ldrb.w r0, [sp, #48] @ 0x30 │ │ lsls r0, r0, #31 │ │ beq.n 1a3fd2 │ │ ldr r0, [sp, #56] @ 0x38 │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ b.n 1a3fd2 │ │ b.n 1a3fd2 │ │ - ldr r3, [r1, r4] │ │ + strb r7, [r0, #14] │ │ vmlal.u32 q13, d14, d12 │ │ bl c2a5c │ │ b.n 1a3fd2 │ │ b.n 1a3fd2 │ │ ldrb r0, [r4, #0] │ │ lsls r0, r0, #31 │ │ itt ne │ │ @@ -379811,15 +379810,15 @@ │ │ nop │ │ add r0, pc, #168 @ (adr r0, 1a4300 ) │ │ movs r1, r1 │ │ add r0, pc, #176 @ (adr r0, 1a430c ) │ │ movs r1, r1 │ │ add r0, pc, #176 @ (adr r0, 1a4310 ) │ │ movs r1, r1 │ │ - mvns r5, r4 │ │ + ldrsh r1, [r4, r1] │ │ @ instruction: 0xffee9fd0 │ │ movs r1, r1 │ │ adds r5, #0 │ │ vqdmulh.s32 q8, , d5[0] │ │ vcvt.f32.u32 , , #18 │ │ vqrdmlah.s32 , , d6[0] │ │ movs r1, r1 │ │ @@ -380007,15 +380006,15 @@ │ │ movs r1, r1 │ │ bge.n 1a440a │ │ @ instruction: 0xffed9db8 │ │ movs r1, r1 │ │ ldr r4, [sp, #768] @ 0x300 │ │ movs r1, r1 │ │ strb r1, [r3, #15] │ │ - vqrdmulh.s32 q10, , d5[0] │ │ + @ instruction: 0xffef67c1 │ │ @ instruction: 0xffee9d0a │ │ movs r1, r1 │ │ ldr r4, [sp, #624] @ 0x270 │ │ movs r1, r1 │ │ │ │ 001a4470 : │ │ push {r4, r5, r6, r7, lr} │ │ @@ -380192,15 +380191,15 @@ │ │ movs r1, r1 │ │ str r7, [r1, #88] @ 0x58 │ │ @ instruction: 0xffef9bd8 │ │ movs r1, r1 │ │ ldr r2, [sp, #832] @ 0x340 │ │ movs r1, r1 │ │ strb r3, [r7, #7] │ │ - @ instruction: 0xffef5b25 │ │ + vabal.u32 , d31, d17 │ │ @ instruction: 0xffee9b2c │ │ movs r1, r1 │ │ ldr r2, [sp, #800] @ 0x320 │ │ movs r1, r1 │ │ │ │ 001a4658 : │ │ ldr r0, [r0, #0] │ │ @@ -380259,15 +380258,15 @@ │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ ldrb r0, [r4, #0] │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [r4, #8] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ - add sp, r4 │ │ + ldrsh r1, [r4, r4] │ │ vsli.64 , q8, #46 @ 0x2e │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ ldr r5, [r0, #0] │ │ mov r4, r0 │ │ cbz r5, 1a4732 │ │ ldr r1, [r4, #4] │ │ @@ -381349,17 +381348,17 @@ │ │ add r0, r1 │ │ clz r0, r0 │ │ lsrs r5, r0, #5 │ │ b.n 1a5272 │ │ nop │ │ lsrs r2, r6, #13 │ │ vsra.u64 d19, d22, #17 │ │ - vmla.f32 , , d14[1] │ │ + vqdmulh.s32 q11, , d10[1] │ │ vshr.u32 , q0, #18 │ │ - @ instruction: 0xffef1ad3 │ │ + vmls.f32 , , d15[0] │ │ @ instruction: 0xffeeedaf │ │ @ instruction: 0xffed0bf6 │ │ vmlal.u32 q8, d30, d24 │ │ vabal.u32 q9, d15, d0 │ │ cmp r2, #0 │ │ itt ne │ │ ldrne r0, [sp, #8] │ │ @@ -381598,15 +381597,15 @@ │ │ addeq sp, #16 │ │ ldreq.w fp, [sp], #4 │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 230610 <__emutls_get_address@@Base+0x3788> │ │ str r4, [sp, #432] @ 0x1b0 │ │ movs r1, r1 │ │ @ instruction: 0xb71a │ │ - vmls.f32 , q15, d5[0] │ │ + vmla.i32 , q7, d1[0] │ │ vrshr.u64 d24, d10, #18 │ │ @ instruction: 0xffef8b96 │ │ movs r1, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ sub sp, #48 @ 0x30 │ │ @@ -381768,15 +381767,15 @@ │ │ lsls r0, r0, #31 │ │ itt ne │ │ ldrne r0, [sp, #40] @ 0x28 │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldrh r4, [r3, #26] │ │ movs r1, r1 │ │ - adds r5, #83 @ 0x53 │ │ + ldr r7, [pc, #828] @ (1a5a2c ) │ │ @ instruction: 0xffee89f8 │ │ movs r1, r1 │ │ push {r7, lr} │ │ mov r7, sp │ │ blx 230e80 <__emutls_get_address@@Base+0x3ff8> │ │ ldrb r2, [r0, #0] │ │ ldrd r1, lr, [r0, #4] │ │ @@ -381833,15 +381832,15 @@ │ │ bne.n 1a578e │ │ pop {r7, pc} │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (1a57b4 ) │ │ add r0, pc │ │ bl a91f8 │ │ - strh r1, [r7, #18] │ │ + ldr r4, [sp, #980] @ 0x3d4 │ │ vsli.64 , q8, #46 @ 0x2e │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ mov r5, r1 │ │ mov r4, r0 │ │ ldrd r1, r0, [r0] │ │ movw r2, #52429 @ 0xcccd │ │ @@ -381936,15 +381935,15 @@ │ │ bl 1a58e4 │ │ bl c71d0 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (1a58f0 ) │ │ add r0, pc │ │ bl a91f8 │ │ - strh r5, [r7, #8] │ │ + ldr r3, [sp, #740] @ 0x2e4 │ │ vsli.64 , q8, #46 @ 0x2e │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ sub sp, #16 │ │ mov r4, r0 │ │ ldr r0, [pc, #332] @ (1a5a50 ) │ │ mov r9, r1 │ │ @@ -384257,15 +384256,15 @@ │ │ b.n 1a6fd8 │ │ bmi.n 1a7062 │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (1a70c4 ) │ │ add r0, pc │ │ bl a91f8 │ │ - ldr r1, [r5, #20] │ │ + strh r5, [r4, #30] │ │ vsli.64 , q8, #46 @ 0x2e │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl, fp} │ │ sub sp, #28 │ │ mov r8, r0 │ │ ldr.w r0, [pc, #992] @ 1a74b8 │ │ mov fp, r1 │ │ @@ -384787,27 +384786,27 @@ │ │ bl c71d0 │ │ bmi.n 1a762a │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (1a768c ) │ │ add r0, pc │ │ bl 1772c0 │ │ - str r1, [r4, #56] @ 0x38 │ │ + ldrb r5, [r3, #24] │ │ vabal.u32 , d30, d0 │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (1a769c ) │ │ add r0, pc │ │ bl 1772c0 │ │ - str r1, [r2, #56] @ 0x38 │ │ + ldrb r5, [r1, #24] │ │ vabal.u32 , d30, d0 │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (1a76ac ) │ │ add r0, pc │ │ bl a91f8 │ │ - str r1, [r0, #56] @ 0x38 │ │ + ldrb r5, [r7, #23] │ │ vsli.64 , q8, #46 @ 0x2e │ │ add r7, sp, #12 │ │ stmdb sp!, {r8, r9, sl} │ │ mov r5, r1 │ │ mov r9, r1 │ │ ldr.w r1, [r5, #8]! │ │ mov r8, r0 │ │ @@ -385242,27 +385241,27 @@ │ │ bl c71d0 │ │ bmi.n 1a7b2e │ │ push {r7, lr} │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (1a7b90 ) │ │ add r0, pc │ │ bl 1772c0 │ │ - ldrsh r5, [r3, r2] │ │ + ldrb r1, [r3, #4] │ │ vabal.u32 , d30, d0 │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (1a7ba0 ) │ │ add r0, pc │ │ bl 1772c0 │ │ - ldrsh r5, [r1, r2] │ │ + ldrb r1, [r1, #4] │ │ vabal.u32 , d30, d0 │ │ mov r7, sp │ │ ldr r0, [pc, #4] @ (1a7bb0 ) │ │ add r0, pc │ │ bl a91f8 │ │ - ldrsh r5, [r7, r1] │ │ + ldrb r1, [r7, #3] │ │ Address 0x1a7bb2 is out of bounds. │ │ │ │ │ │ 001a7bb4 , std::__ndk1::allocator > const&)@@Base>: │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w fp, [sp, #-4]! │ │ @@ -385849,15 +385848,15 @@ │ │ b.n 1a81d4 , std::__ndk1::allocator > const&, bool, bool)@@Base+0x420> │ │ nop │ │ str r6, [r4, #44] @ 0x2c │ │ movs r1, r1 │ │ str r6, [r4, #44] @ 0x2c │ │ movs r1, r1 │ │ bl fffe11a4 <__cxa_new_handler@@Base+0xffd9d5b4> │ │ - asrs r6, r0, #10 │ │ + cmp r5, #2 │ │ vsubl.u32 q11, d30, d14 │ │ movs r1, r1 │ │ cmp r4, #49 @ 0x31 │ │ vmlal.u32 , d15, d6 │ │ blx 230de0 <__emutls_get_address@@Base+0x3f58> │ │ b.n 1a822c , std::__ndk1::allocator > const&, bool, bool)@@Base+0x478> │ │ b.n 1a822c , std::__ndk1::allocator > const&, bool, bool)@@Base+0x478> │ │ @@ -385899,38 +385898,38 @@ │ │ blx 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ str r6, [r3, #44] @ 0x2c │ │ movs r1, r1 │ │ ldrsh r0, [r3, r3] │ │ movs r1, r1 │ │ add r5, sp, #1004 @ 0x3ec │ │ - vqshrn.u64 d31, , #19 │ │ - vmla.f32 q11, , d4[0] │ │ + vrsra.u64 d17, d23, #19 │ │ + vmla.f32 q11, q15, d4[0] │ │ movs r1, r1 │ │ add sp, #208 @ 0xd0 │ │ movs r1, r1 │ │ - asrs r7, r4, #7 │ │ + cmp r4, #99 @ 0x63 │ │ vshr.u64 q11, q3, #18 │ │ movs r1, r1 │ │ str r4, [r2, #12] │ │ movs r1, r1 │ │ - cmp r4, #5 │ │ + mov r9, r0 │ │ vaddl.u32 q11, d30, d0 │ │ movs r1, r1 │ │ bgt.n 1a8352 │ │ - @ instruction: 0xffed599b │ │ + vsri.32 d23, d7, #19 │ │ vcvt.u32.f32 d21, d28, #18 │ │ movs r1, r1 │ │ add r3, sp, #988 @ 0x3dc │ │ - vqshl.u32 d31, d23, #13 │ │ - vqrdmlsh.s32 , , d4[0] │ │ + vsra.u64 d17, d19, #19 │ │ + vqrdmlsh.s32 , q15, d4[0] │ │ movs r1, r1 │ │ add r3, sp, #872 @ 0x368 │ │ - vqshlu.s64 d31, d5, #45 @ 0x2d │ │ - @ instruction: 0xffedab51 │ │ + vsra.u32 d17, d1, #19 │ │ + @ instruction: 0xffeeab51 │ │ vcvt.u32.f32 , q3, #19 │ │ movs r1, r1 │ │ push {r4, r5, r6, r7, lr} │ │ add r7, sp, #12 │ │ str.w r8, [sp, #-4]! │ │ ldr r4, [pc, #52] @ (1a82d8 , std::__ndk1::allocator > const&, bool, bool)@@Base+0x524>) │ │ mov.w r8, #0 │ │ @@ -386052,15 +386051,15 @@ │ │ ldrne r0, [sp, #16] │ │ blxne 230670 <__emutls_get_address@@Base+0x37e8> │ │ blx 2306a0 <__emutls_get_address@@Base+0x3818> │ │ nop │ │ ldrb r4, [r7, r4] │ │ movs r1, r1 │ │ ldr r0, [r0, r4] │ │ - vsra.u32 d21, d26, #17 │ │ + @ instruction: 0xffef6bb6 │ │ @ instruction: 0xffee8dfa │ │ Address 0x1a83e6 is out of bounds. │ │ │ │ │ │ 001a83e8 , cv::_OutputArray const&)@@Base>: │ │ push {r7, lr} │ │ mov r7, sp │ │ @@ -386458,18 +386457,18 @@ │ │ cmpne r5, #32 │ │ beq.n 1a87b8 , cv::_OutputArray const&)@@Base+0x3d0> │ │ mov.w r8, #0 │ │ b.n 1a880e , cv::_OutputArray const&)@@Base+0x426> │ │ nop │ │ add r3, sp, #0 │ │ movs r1, r1 │ │ - subs r0, #210 @ 0xd2 │ │ - vmul.i32 , q7, d2[1] │ │ + strh r6, [r1, r5] │ │ + vrshr.u64 , q7, #18 │ │ vsubw.u32 q15, q15, d22 │ │ - vrsra.u64 d20, d12, #18 │ │ + vcvt.f32.u32 d21, d8, #18 │ │ vmls.f32 q9, q7, d9[0] │ │ vmls.i32 , , d9[0] │ │ vmla.i32 , q7, d15[1] │ │ @ instruction: 0xffee5b46 │ │ movs r1, r1 │ │ ldrsb r6, [r4, r4] │ │ @ instruction: 0xffef23cd │ │ @@ -386810,16 +386809,16 @@ │ │ bmi.n 1a8b24 , cv::_OutputArray const&)@@Base+0x73c> │ │ mov r2, r3 │ │ b.n 1a8b38 , cv::_OutputArray const&)@@Base+0x750> │ │ nop │ │ push {r3, r4, r6, lr} │ │ vabal.u32 , d29, d24 │ │ @ instruction: 0xffeddfbe │ │ - vqrdmlah.s32 q15, q7, d12[1] │ │ - vmla.i32 , , d3[0] │ │ + vmul.i32 q8, q15, d8[1] │ │ + vmla.i32 , q7, d3[0] │ │ lsls r6, r4, #8 │ │ strd r2, r1, [r5, #24] │ │ cmp r0, #0 │ │ itt mi │ │ orrmi.w r2, r3, #294 @ 0x126 │ │ strdmi r2, r1, [r5, #24] │ │ ands.w r0, r2, #2 │ │ @@ -387041,16 +387040,16 @@ │ │ ldmiaeq.w sp!, {r8, r9, sl, fp} │ │ popeq {r4, r5, r6, r7, pc} │ │ blx 230610 <__emutls_get_address@@Base+0x3788> │ │ ldrb r0, [r3, r0] │ │ movs r1, r1 │ │ ldrsb r4, [r5, r5] │ │ movs r1, r1 │ │ - @ instruction: 0xfab3ffed │ │ - subs r4, r7, #0 │ │ + asrs r7, r5, #20 │ │ + vcvt.f32.u32 d17, d28, #18 │ │ movs r1, r1 │ │ stmia r0!, {r5, r7} │ │ vmull.u32 q9, d29, d7[1] │ │ vrsra.u32 , q7, #17 │ │ movs r1, r1 │ │ push {r4, r6, r7, lr} │ │ add r7, sp, #8 │ │ @@ -411919,15 +411918,15 @@ │ │ add r1, pc, r1 │ │ bl 233370 <__emutls_get_address@@Base+0x64e8> │ │ ldr r1, [pc, #12] @ 1c0fd8 &)@@Base+0x44> │ │ mov r0, #1 │ │ add r1, pc, r1 │ │ b 1c0fc0 &)@@Base+0x2c> │ │ blx a8d68 │ │ - @ instruction: 0xffec819e │ │ + @ instruction: 0xffec9c1a │ │ @ instruction: 0xffedb437 │ │ │ │ 001c0fe0 &, std::__ndk1::chrono::time_point > >)@@Base>: │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r4, r0 │ │ @@ -411969,15 +411968,15 @@ │ │ mov r0, #1 │ │ add r1, pc, r1 │ │ b 1c1090 &, std::__ndk1::chrono::time_point > >)@@Base+0xb0> │ │ ldr r1, [pc, #12] @ 1c109c &, std::__ndk1::chrono::time_point > >)@@Base+0xbc> │ │ add r1, pc, r1 │ │ bl 233370 <__emutls_get_address@@Base+0x64e8> │ │ blx a8d68 │ │ - @ instruction: 0xffec9bfb │ │ + @ instruction: 0xffecb677 │ │ @ instruction: 0xffed49c2 │ │ │ │ 001c10a0 )@@Base>: │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r1 │ │ mov r4, r0 │ │ @@ -412705,15 +412704,15 @@ │ │ add r0, pc, r0 │ │ bl 1c1bac │ │ @ instruction: 0xffee4788 │ │ @ instruction: 0xffee47d8 │ │ @ instruction: 0xffee47a4 │ │ @ instruction: 0xffee46dc │ │ @ instruction: 0xffee3fb0 │ │ - @ instruction: 0xffec7609 │ │ + @ instruction: 0xffec9085 │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r5, r0 │ │ mov r0, #8 │ │ bl 230710 <__emutls_get_address@@Base+0x3888> │ │ mov r4, r0 │ │ mov r1, r5 │ │ @@ -412975,15 +412974,15 @@ │ │ mov fp, sp │ │ bl 233540 <__emutls_get_address@@Base+0x66b8> │ │ cmp r0, #0 │ │ popeq {fp, pc} │ │ ldr r1, [pc, #4] @ 1c1f48 │ │ add r1, pc, r1 │ │ bl 233370 <__emutls_get_address@@Base+0x64e8> │ │ - @ instruction: 0xffecb595 │ │ + @ instruction: 0xffecd011 │ │ │ │ 001c1f4c : │ │ push {fp, lr} │ │ mov fp, sp │ │ bl 233560 <__emutls_get_address@@Base+0x66d8> │ │ clz r0, r0 │ │ lsr r0, r0, #5 │ │ @@ -413097,15 +413096,15 @@ │ │ pop {r4, sl, fp, lr} │ │ b 230e30 <__emutls_get_address@@Base+0x3fa8> │ │ ldr r1, [pc, #12] @ 1c20e8 │ │ add r1, pc, r1 │ │ bl 233370 <__emutls_get_address@@Base+0x64e8> │ │ blx a8d68 │ │ blx a8d68 │ │ - @ instruction: 0xffecb3fd │ │ + @ instruction: 0xffecce79 │ │ │ │ 001c20ec : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r4, r0 │ │ mov r0, #1 │ │ @@ -413138,15 +413137,15 @@ │ │ bl 233550 <__emutls_get_address@@Base+0x66c8> │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ ldr r1, [pc, #8] @ 1c2184 │ │ add r1, pc, r1 │ │ bl 233370 <__emutls_get_address@@Base+0x64e8> │ │ blx a8d68 │ │ - @ instruction: 0xffecb35d │ │ + @ instruction: 0xffeccdd9 │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ ldrb r0, [r0, #4] │ │ cmp r0, #0 │ │ beq 1c21a8 │ │ ldr r0, [r4] │ │ @@ -413191,15 +413190,15 @@ │ │ bl 233550 <__emutls_get_address@@Base+0x66c8> │ │ pop {r4, sl, fp, pc} │ │ ldr r1, [pc, #12] @ 1c2248 │ │ add r1, pc, r1 │ │ bl 233370 <__emutls_get_address@@Base+0x64e8> │ │ blx a8d68 │ │ blx a8d68 │ │ - @ instruction: 0xffecb29d │ │ + @ instruction: 0xffeccd19 │ │ │ │ 001c224c : │ │ vmov.i32 q8, #0 @ 0x00000000 │ │ vst1.32 {d16-d17}, [r0] │ │ bx lr │ │ │ │ 001c2258 : │ │ @@ -413217,15 +413216,15 @@ │ │ pop {r4, sl, fp, lr} │ │ b 230e30 <__emutls_get_address@@Base+0x3fa8> │ │ ldr r1, [pc, #12] @ 1c22a0 │ │ add r1, pc, r1 │ │ bl 233370 <__emutls_get_address@@Base+0x64e8> │ │ blx a8d68 │ │ blx a8d68 │ │ - @ instruction: 0xffecb245 │ │ + @ instruction: 0xffecccc1 │ │ │ │ 001c22a4 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r4, r0 │ │ bl 2335c0 <__emutls_get_address@@Base+0x6738> │ │ @@ -413282,15 +413281,15 @@ │ │ add r1, pc, r1 │ │ bl 233370 <__emutls_get_address@@Base+0x64e8> │ │ mov r0, sp │ │ bl 1c2188 │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ blx a8d68 │ │ @ instruction: 0xffed5353 │ │ - @ instruction: 0xffecb155 │ │ + @ instruction: 0xffeccbd1 │ │ │ │ 001c23a0 : │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ bl 2335c0 <__emutls_get_address@@Base+0x6738> │ │ mov r5, r0 │ │ @@ -413348,15 +413347,15 @@ │ │ b 233380 <__emutls_get_address@@Base+0x64f8> │ │ ldr r1, [pc, #16] @ 1c2494 │ │ add r1, pc, r1 │ │ bl 233370 <__emutls_get_address@@Base+0x64e8> │ │ blx a8d68 │ │ blx a8d68 │ │ blx a8d68 │ │ - @ instruction: 0xffecb055 │ │ + @ instruction: 0xffeccad1 │ │ │ │ 001c2498 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ ldr r7, [pc, #228] @ 1c258c │ │ mov r4, r0 │ │ mov r5, r2 │ │ @@ -421764,20 +421763,20 @@ │ │ mov r0, #0 │ │ strb r0, [r4, r6] │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ mov r0, r4 │ │ blx a91e8 │ │ bl 233860 <__emutls_get_address@@Base+0x69d8> │ │ - @ instruction: 0xffebf231 │ │ + @ instruction: 0xffec0cad │ │ @ instruction: 0xffec9e70 │ │ ldr r0, [pc, #4] @ 1ca398 │ │ add r0, pc, r0 │ │ bx lr │ │ - @ instruction: 0xffec3157 │ │ + @ instruction: 0xffec4bd3 │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ cmp r2, #4096 @ 0x1000 │ │ blt 1ca3f8 │ │ mov r0, #48 @ 0x30 │ │ bl 2306d0 <__emutls_get_address@@Base+0x3848> │ │ @@ -422934,21 +422933,21 @@ │ │ mov r0, r5 │ │ bl 1cb508 │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r0, [pc, #4] @ 1cb504 │ │ add r0, pc, r0 │ │ blx a91f8 │ │ - @ instruction: 0xffec2527 │ │ + @ instruction: 0xffec3fa3 │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r0, [pc, #4] @ 1cb51c │ │ add r0, pc, r0 │ │ blx a91f8 │ │ - @ instruction: 0xffec250f │ │ + @ instruction: 0xffec3f8b │ │ cmp r0, #0 │ │ bxeq lr │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ bl 2338e0 <__emutls_get_address@@Base+0x6a58> │ │ mov r0, r4 │ │ @@ -424189,15 +424188,15 @@ │ │ streq r1, [r0] │ │ subeq sp, fp, #28 │ │ popeq {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldr r0, [pc, #8] @ 1cc780 │ │ add r0, pc, r0 │ │ bl 1cca38 │ │ andeq r6, r7, r8, ror #17 │ │ - @ instruction: 0xffec01ab │ │ + @ instruction: 0xffec1c27 │ │ │ │ 001cc784 : │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ mov r4, r0 │ │ ldr r0, [r0, #68] @ 0x44 │ │ @@ -424254,15 +424253,15 @@ │ │ streq r1, [r0] │ │ subeq sp, fp, #28 │ │ popeq {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ ldr r0, [pc, #8] @ 1cc87c │ │ add r0, pc, r0 │ │ bl 1cca38 │ │ strdeq r6, [r7], -r0 │ │ - @ instruction: 0xffec00af │ │ + @ instruction: 0xffec1b2b │ │ │ │ 001cc880 : │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ mov r6, r1 │ │ ldr r1, [r0, #40] @ 0x28 │ │ mov r4, r0 │ │ @@ -424311,15 +424310,15 @@ │ │ ldr r0, [r4, #40] @ 0x28 │ │ add r0, r0, #1 │ │ str r0, [r4, #40] @ 0x28 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ ldr r0, [pc, #4] @ 1cc958 │ │ add r0, pc, r0 │ │ bl 1cca38 │ │ - @ instruction: 0xffebffcf │ │ + @ instruction: 0xffec1a4b │ │ │ │ 001cc95c : │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ ldr r1, [pc, #120] @ 1cc9e4 │ │ mov r4, r0 │ │ ldr r1, [pc, r1] │ │ @@ -424372,15 +424371,15 @@ │ │ orreq r1, r1, #1 │ │ str r1, [r0, #16] │ │ tst r2, r1 │ │ popeq {fp, pc} │ │ ldr r0, [pc, #4] @ 1cca34 │ │ add r0, pc, r0 │ │ bl 1cca38 │ │ - @ instruction: 0xffebfef3 │ │ + @ instruction: 0xffec196f │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #8 │ │ mov r5, r0 │ │ mov r0, #16 │ │ bl 230710 <__emutls_get_address@@Base+0x3888> │ │ mov r4, r0 │ │ @@ -435783,18 +435782,18 @@ │ │ mov r0, r5 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ @ instruction: 0xffeacac2 │ │ @ instruction: 0xffebd97e │ │ @ instruction: 0xffebd588 │ │ @ instruction: 0xffec36fe │ │ @ instruction: 0xffeb8ab7 │ │ - @ instruction: 0xffeb559b │ │ + @ instruction: 0xffeb7017 │ │ @ instruction: 0xffec0ccb │ │ @ instruction: 0xffeaaaba │ │ - @ instruction: 0xffeb5eb3 │ │ + @ instruction: 0xffeb792f │ │ @ instruction: 0xffebc316 │ │ @ instruction: 0xffebd909 │ │ @ instruction: 0xffebf59e │ │ │ │ 001d747c >::open(std::__ndk1::basic_string, std::__ndk1::allocator > const&, unsigned int)@@Base>: │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ @@ -447865,15 +447864,15 @@ │ │ ldr lr, [fp, #8] │ │ add ip, pc, ip │ │ str lr, [sp] │ │ str ip, [sp, #4] │ │ bl 1e2f74 > >::do_put(std::__ndk1::ostreambuf_iterator >, std::__ndk1::ios_base&, char, long) const@@Base+0x30> │ │ mov sp, fp │ │ pop {fp, pc} │ │ - @ instruction: 0xffeaa597 │ │ + @ instruction: 0xffeac013 │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #72 @ 0x48 │ │ mov r6, r2 │ │ mov r8, r1 │ │ ldr r1, [r6, #4] │ │ mov r0, #0 │ │ @@ -448164,15 +448163,15 @@ │ │ ldr lr, [fp, #8] │ │ add ip, pc, ip │ │ str lr, [sp] │ │ str ip, [sp, #4] │ │ bl 1e3410 > >::do_put(std::__ndk1::ostreambuf_iterator >, std::__ndk1::ios_base&, char, unsigned long) const@@Base+0x30> │ │ mov sp, fp │ │ pop {fp, pc} │ │ - @ instruction: 0xffeaa0fb │ │ + @ instruction: 0xffeabb77 │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #72 @ 0x48 │ │ mov r6, r2 │ │ mov r0, #0 │ │ mov r8, r1 │ │ str r0, [fp, #-28] @ 0xffffffe4 │ │ @@ -448459,15 +448458,15 @@ │ │ vldr d16, [fp, #8] │ │ add ip, pc, ip │ │ str ip, [sp, #8] │ │ vstr d16, [sp] │ │ bl 1e389c > >::do_put(std::__ndk1::ostreambuf_iterator >, std::__ndk1::ios_base&, char, double) const@@Base+0x30> │ │ mov sp, fp │ │ pop {fp, pc} │ │ - @ instruction: 0xffea5c95 │ │ + @ instruction: 0xffea7711 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8} │ │ sub sp, sp, #144 @ 0x90 │ │ mov r0, #0 │ │ ldr r6, [r2, #4] │ │ @@ -449409,15 +449408,15 @@ │ │ ldr lr, [fp, #8] │ │ add ip, pc, ip │ │ str lr, [sp] │ │ str ip, [sp, #4] │ │ bl 1e474c > >::do_put(std::__ndk1::ostreambuf_iterator >, std::__ndk1::ios_base&, wchar_t, long) const@@Base+0x30> │ │ mov sp, fp │ │ pop {fp, pc} │ │ - @ instruction: 0xffea8dbf │ │ + @ instruction: 0xffeaa83b │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #144 @ 0x90 │ │ mov r6, r2 │ │ mov r8, r1 │ │ ldr r1, [r6, #4] │ │ mov r0, #0 │ │ @@ -449708,15 +449707,15 @@ │ │ ldr lr, [fp, #8] │ │ add ip, pc, ip │ │ str lr, [sp] │ │ str ip, [sp, #4] │ │ bl 1e4be8 > >::do_put(std::__ndk1::ostreambuf_iterator >, std::__ndk1::ios_base&, wchar_t, unsigned long) const@@Base+0x30> │ │ mov sp, fp │ │ pop {fp, pc} │ │ - @ instruction: 0xffea8923 │ │ + @ instruction: 0xffeaa39f │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #144 @ 0x90 │ │ mov r6, r2 │ │ mov r0, #0 │ │ mov r8, r1 │ │ str r0, [fp, #-28] @ 0xffffffe4 │ │ @@ -450003,15 +450002,15 @@ │ │ vldr d16, [fp, #8] │ │ add ip, pc, ip │ │ str ip, [sp, #8] │ │ vstr d16, [sp] │ │ bl 1e5074 > >::do_put(std::__ndk1::ostreambuf_iterator >, std::__ndk1::ios_base&, wchar_t, double) const@@Base+0x30> │ │ mov sp, fp │ │ pop {fp, pc} │ │ - @ instruction: 0xffea44bd │ │ + @ instruction: 0xffea5f39 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ vpush {d8} │ │ sub sp, sp, #320 @ 0x140 │ │ mov r0, #0 │ │ ldr r6, [r2, #4] │ │ @@ -457105,15 +457104,15 @@ │ │ ldr r0, [pc, #20] @ 1ebd98 │ │ add r0, pc, r0 │ │ bl 233b30 <__emutls_get_address@@Base+0x6ca8> │ │ blx a8d68 │ │ sub r0, fp, #28 │ │ bl 20ede8 ::~__narrow_to_utf8()@@Base+0x64c> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ - @ instruction: 0xffe9c788 │ │ + @ instruction: 0xffe9e204 │ │ │ │ 001ebd9c ::do_decimal_point() const@@Base>: │ │ mov r0, #255 @ 0xff │ │ bx lr │ │ │ │ 001ebda4 ::do_thousands_sep() const@@Base>: │ │ mov r0, #255 @ 0xff │ │ @@ -475538,15 +475537,15 @@ │ │ beq 1fd9f0 │ │ ldr r0, [sp, #12] │ │ bl 230670 <__emutls_get_address@@Base+0x37e8> │ │ b 1fd9f0 │ │ mov r0, r9 │ │ bl 230670 <__emutls_get_address@@Base+0x37e8> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ - @ instruction: 0xffe8c6ed │ │ + @ instruction: 0xffe8e169 │ │ │ │ 001fda00 , std::__ndk1::allocator > const&)@@Base>: │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ mov r0, #168 @ 0xa8 │ │ mov r6, r1 │ │ @@ -475643,15 +475642,15 @@ │ │ beq 1fdb84 │ │ ldr r0, [sp, #16] │ │ bl 230670 <__emutls_get_address@@Base+0x37e8> │ │ b 1fdb84 │ │ mov r0, r9 │ │ bl 230670 <__emutls_get_address@@Base+0x37e8> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ - @ instruction: 0xffe8c559 │ │ + @ instruction: 0xffe8dfd5 │ │ │ │ 001fdb94 , std::__ndk1::allocator > const&, int)@@Base>: │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ mov r4, r0 │ │ mov r0, #168 @ 0xa8 │ │ mov r8, r3 │ │ @@ -476195,15 +476194,15 @@ │ │ mov r0, r4 │ │ bl 233530 <__emutls_get_address@@Base+0x66a8> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ mov r0, r4 │ │ bl 233530 <__emutls_get_address@@Base+0x66a8> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ andeq r0, r4, ip, lsl #1 │ │ - @ instruction: 0xffe8869a │ │ + @ instruction: 0xffe8a116 │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ mov r5, r0 │ │ mov r0, #8 │ │ bl 230710 <__emutls_get_address@@Base+0x3888> │ │ mov r4, r0 │ │ mov r1, r5 │ │ @@ -476282,15 +476281,15 @@ │ │ mov r0, r4 │ │ bl 233530 <__emutls_get_address@@Base+0x66a8> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ mov r0, r4 │ │ bl 233530 <__emutls_get_address@@Base+0x66a8> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ strdeq pc, [r3], -ip │ │ - @ instruction: 0xffe8850a │ │ + @ instruction: 0xffe89f86 │ │ │ │ 001fe520 ::~collate_byname()@@Base>: │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ ldr r1, [pc, #36] @ 1fe554 ::~collate_byname()@@Base+0x34> │ │ mov r4, r0 │ │ ldr r1, [pc, r1] │ │ @@ -478649,15 +478648,15 @@ │ │ mov r0, r4 │ │ bl 233530 <__emutls_get_address@@Base+0x66a8> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ mov r0, r4 │ │ bl 233530 <__emutls_get_address@@Base+0x66a8> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ andeq sp, r3, r8, ror #24 │ │ - @ instruction: 0xffe862a0 │ │ + @ instruction: 0xffe87d1c │ │ │ │ 00200804 ::~codecvt()@@Base>: │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ mov r4, r0 │ │ bl 2341f0 <__emutls_get_address@@Base+0x7368> │ │ mov r0, r4 │ │ @@ -486559,15 +486558,15 @@ │ │ add r0, r6, #12 │ │ pop {r4, r5, r6, sl, fp, pc} │ │ mov r0, r4 │ │ bl 2307d0 <__emutls_get_address@@Base+0x3948> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ @ instruction: 0x0003bbb8 │ │ andeq fp, r3, ip, lsl #26 │ │ - @ instruction: 0xffe82ea0 │ │ + @ instruction: 0xffe8491c │ │ andeq sp, r2, r0, lsr #16 │ │ ldrdeq r6, [r3], -r8 │ │ │ │ 00207e64 ::__r() const@@Base>: │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ ldr r0, [pc, #124] @ 207ef0 ::__r() const@@Base+0x8c> │ │ @@ -487852,15 +487851,15 @@ │ │ ldrb r0, [sl] │ │ tst r0, #1 │ │ bne 209250 ::__analyze(char, std::__ndk1::ctype const&)@@Base+0x7c0> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ ldr r0, [sl, #8] │ │ bl 230670 <__emutls_get_address@@Base+0x37e8> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ - @ instruction: 0xffe7f2f0 │ │ + @ instruction: 0xffe80d6c │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #132 @ 0x84 │ │ mov r8, r0 │ │ sub r0, r3, r2 │ │ str r1, [sp, #20] │ │ movw r1, #43691 @ 0xaaab │ │ @@ -488436,28 +488435,28 @@ │ │ bl 230670 <__emutls_get_address@@Base+0x37e8> │ │ vldr d16, [sp, #8] │ │ ldr r0, [sp, #16] │ │ str r0, [r4, #8] │ │ vstr d16, [r4] │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ - @ instruction: 0xffe7e24a │ │ - @ instruction: 0xffe7d426 │ │ - @ instruction: 0xffe7e1a6 │ │ - @ instruction: 0xffe7d3a6 │ │ - @ instruction: 0xffe7e126 │ │ - @ instruction: 0xffe7d326 │ │ - @ instruction: 0xffe7e0a6 │ │ - @ instruction: 0xffe7d2a6 │ │ - @ instruction: 0xffe7e026 │ │ - @ instruction: 0xffe7d226 │ │ - @ instruction: 0xffe7dfa6 │ │ - @ instruction: 0xffe7d1a6 │ │ - @ instruction: 0xffe7df26 │ │ - @ instruction: 0xffe7d126 │ │ + @ instruction: 0xffe7fcc6 │ │ + @ instruction: 0xffe7eea2 │ │ + @ instruction: 0xffe7fc22 │ │ + @ instruction: 0xffe7ee22 │ │ + @ instruction: 0xffe7fba2 │ │ + @ instruction: 0xffe7eda2 │ │ + @ instruction: 0xffe7fb22 │ │ + @ instruction: 0xffe7ed22 │ │ + @ instruction: 0xffe7faa2 │ │ + @ instruction: 0xffe7eca2 │ │ + @ instruction: 0xffe7fa22 │ │ + @ instruction: 0xffe7ec22 │ │ + @ instruction: 0xffe7f9a2 │ │ + @ instruction: 0xffe7eba2 │ │ @ instruction: 0xffe92afe │ │ @ instruction: 0xffe8dd5b │ │ @ instruction: 0xffe910da │ │ │ │ 00209bb8 ::init(std::__ndk1::ctype const&)@@Base>: │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -488779,17 +488778,17 @@ │ │ blx a8d68 │ │ b 20a0bc ::init(std::__ndk1::ctype const&)@@Base+0x504> │ │ b 20a0bc ::init(std::__ndk1::ctype const&)@@Base+0x504> │ │ b 20a0bc ::init(std::__ndk1::ctype const&)@@Base+0x504> │ │ add r0, sp, #8 │ │ bl 20ede8 ::~__narrow_to_utf8()@@Base+0x64c> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ - @ instruction: 0xffe7dc06 │ │ - @ instruction: 0xffe7e480 │ │ - @ instruction: 0xffe7cdb2 │ │ + @ instruction: 0xffe7f682 │ │ + @ instruction: 0xffe7fefc │ │ + @ instruction: 0xffe7e82e │ │ @ instruction: 0xffe926fe │ │ @ instruction: 0xffe8d8d3 │ │ @ instruction: 0xffe90c4e │ │ @ instruction: 0xffe90bc2 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #44 @ 0x2c │ │ @@ -491211,15 +491210,15 @@ │ │ b 20c674 │ │ ldrb r0, [sp] │ │ tst r0, #1 │ │ beq 20c64c │ │ ldr r0, [sp, #8] │ │ bl 230670 <__emutls_get_address@@Base+0x37e8> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ - @ instruction: 0xffe7dab6 │ │ + @ instruction: 0xffe7f532 │ │ │ │ 0020c684 , std::__ndk1::allocator > const&)@@Base>: │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #16 │ │ mov r4, r1 │ │ mov r5, r0 │ │ @@ -491245,15 +491244,15 @@ │ │ bl 1fe3cc ::collate_byname(char const*, unsigned int)@@Base+0xf0> │ │ ldrb r0, [sp, #4] │ │ tst r0, #1 │ │ beq 20c6fc , std::__ndk1::allocator > const&)@@Base+0x78> │ │ ldr r0, [sp, #12] │ │ bl 230670 <__emutls_get_address@@Base+0x37e8> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ - @ instruction: 0xffe7d9fe │ │ + @ instruction: 0xffe7f47a │ │ │ │ 0020c704 : │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ ldr r5, [pc, #136] @ 20c79c │ │ mov r4, r0 │ │ ldr r7, [r0] │ │ @@ -491497,15 +491496,15 @@ │ │ beq 20cad4 ::init(char const*)@@Base+0x32c> │ │ ldr r0, [sp, #32] │ │ bl 230670 <__emutls_get_address@@Base+0x37e8> │ │ b 20cad4 ::init(char const*)@@Base+0x32c> │ │ sub r0, fp, #28 │ │ bl 204e80 ::~numpunct_byname()@@Base+0xf4> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ - @ instruction: 0xffe7d6a7 │ │ + @ instruction: 0xffe7f123 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ mov ip, r1 │ │ mov sl, r0 │ │ mov lr, #0 │ │ cmp r2, #0 │ │ @@ -492012,15 +492011,15 @@ │ │ beq 20d2d8 ::init(char const*)@@Base+0x32c> │ │ ldr r0, [sp, #32] │ │ bl 230670 <__emutls_get_address@@Base+0x37e8> │ │ b 20d2d8 ::init(char const*)@@Base+0x32c> │ │ sub r0, fp, #28 │ │ bl 204e80 ::~numpunct_byname()@@Base+0xf4> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ - @ instruction: 0xffe7cea3 │ │ + @ instruction: 0xffe7e91f │ │ │ │ 0020d2e8 ::init(char const*)@@Base>: │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #452 @ 0x1c4 │ │ mov sl, r0 │ │ movw r0, #8127 @ 0x1fbf │ │ @@ -492358,19 +492357,19 @@ │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ sub r0, fp, #36 @ 0x24 │ │ bl 204e80 ::~numpunct_byname()@@Base+0xf4> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ sub r0, fp, #36 @ 0x24 │ │ bl 204e80 ::~numpunct_byname()@@Base+0xf4> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ - @ instruction: 0xffe7c9d3 │ │ - @ instruction: 0xffe7adc4 │ │ + @ instruction: 0xffe7e44f │ │ + @ instruction: 0xffe7c840 │ │ @ instruction: 0xffe984b0 │ │ @ instruction: 0xffe9841c │ │ - @ instruction: 0xffe7adf8 │ │ + @ instruction: 0xffe7c874 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ mov ip, r1 │ │ mov lr, r0 │ │ mov r4, #0 │ │ cmp r2, #0 │ │ @@ -493026,19 +493025,19 @@ │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ sub r0, fp, #36 @ 0x24 │ │ bl 204e80 ::~numpunct_byname()@@Base+0xf4> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ sub r0, fp, #36 @ 0x24 │ │ bl 204e80 ::~numpunct_byname()@@Base+0xf4> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ - @ instruction: 0xffe7bf6b │ │ - @ instruction: 0xffe7a35c │ │ + @ instruction: 0xffe7d9e7 │ │ + @ instruction: 0xffe7bdd8 │ │ @ instruction: 0xffe97a48 │ │ @ instruction: 0xffe979b4 │ │ - @ instruction: 0xffe7a390 │ │ + @ instruction: 0xffe7be0c │ │ push {fp, lr} │ │ mov fp, sp │ │ bl 233df0 <__emutls_get_address@@Base+0x6f68> │ │ pop {fp, lr} │ │ b 230670 <__emutls_get_address@@Base+0x37e8> │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ @@ -493787,15 +493786,15 @@ │ │ mov r0, r4 │ │ pop {r4, sl, fp, pc} │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r0, [pc, #4] @ 20ee80 ::~__narrow_to_utf8()@@Base+0x6e4> │ │ add r0, pc, r0 │ │ blx a91f8 │ │ - @ instruction: 0xffe7ebab │ │ + @ instruction: 0xffe80627 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #4 │ │ mov r9, r0 │ │ ldr r7, [r0] │ │ ldr r0, [r0, #8] │ │ sub r8, r2, r1 │ │ @@ -494727,15 +494726,15 @@ │ │ mov r0, r4 │ │ bl 233530 <__emutls_get_address@@Base+0x66a8> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ mov r0, r4 │ │ bl 233530 <__emutls_get_address@@Base+0x66a8> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ andeq lr, r2, r4, asr r6 │ │ - @ instruction: 0xffe7a3ea │ │ + @ instruction: 0xffe7be66 │ │ andeq lr, r2, r4, lsr #12 │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #16 │ │ mov r4, r0 │ │ ldr r0, [pc, #152] @ 20fde8 ::~__narrow_to_utf8()@@Base+0x164c> │ │ mov r5, r1 │ │ @@ -494774,15 +494773,15 @@ │ │ mov r0, r4 │ │ bl 233530 <__emutls_get_address@@Base+0x66a8> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ mov r0, r4 │ │ bl 233530 <__emutls_get_address@@Base+0x66a8> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ muleq r2, r8, r5 │ │ - @ instruction: 0xffe7a32e │ │ + @ instruction: 0xffe7bdaa │ │ andeq lr, r2, ip, ror #10 │ │ ldr r0, [r0] │ │ ldr r0, [r0] │ │ ldr r2, [r0] │ │ ldmib r0, {r1, r3} │ │ tst r3, #1 │ │ add r0, r2, r3, asr #1 │ │ @@ -496545,15 +496544,15 @@ │ │ andeq ip, r2, r8, lsl #21 │ │ push {fp, lr} │ │ mov fp, sp │ │ blx r0 │ │ ldr r0, [pc, #4] @ 211970 │ │ add r0, pc, r0 │ │ bl 212024 │ │ - @ instruction: 0xffe77843 │ │ + @ instruction: 0xffe792bf │ │ │ │ 00211974 : │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r0, [pc, #12] @ 211990 │ │ ldr r0, [pc, r0] │ │ ldr r0, [r0] │ │ @@ -496674,29 +496673,29 @@ │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ blx a8d68 │ │ muleq r0, ip, r1 │ │ muleq r0, ip, r1 │ │ andeq ip, r2, r0, asr #13 │ │ andeq lr, r2, r4, lsr ip │ │ @ instruction: 0xffe8a97d │ │ - @ instruction: 0xffe7ae1f │ │ + @ instruction: 0xffe7c89b │ │ strdeq lr, [r2], -r4 │ │ @ instruction: 0xffe7237b │ │ @ instruction: 0xffe8657b │ │ andeq lr, r2, r8, lsl #24 │ │ push {fp, lr} │ │ mov fp, sp │ │ ldr r0, [pc, #16] @ 211b90 │ │ ldr r1, [pc, #16] @ 211b94 │ │ add r0, pc, r0 │ │ add r1, pc, r1 │ │ str r1, [r0] │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ andeq lr, r2, ip, lsl #23 │ │ - @ instruction: 0xffe79134 │ │ + @ instruction: 0xffe7abb0 │ │ │ │ 00211b98 : │ │ ldr r1, [pc, #44] @ 211bcc │ │ dmb ish │ │ ldr r2, [pc, #40] @ 211bd0 │ │ cmp r0, #0 │ │ add r1, pc, r1 │ │ @@ -496804,15 +496803,15 @@ │ │ pop {r4, sl, fp, lr} │ │ b 230670 <__emutls_get_address@@Base+0x37e8> │ │ │ │ 00211cf8 : │ │ ldr r0, [pc, #4] @ 211d04 │ │ add r0, pc, r0 │ │ bx lr │ │ - @ instruction: 0xffe78fc7 │ │ + @ instruction: 0xffe7aa43 │ │ │ │ 00211d08 : │ │ ldr r1, [pc, #12] @ 211d1c │ │ ldr r1, [pc, r1] │ │ add r1, r1, #8 │ │ str r1, [r0] │ │ bx lr │ │ @@ -496827,15 +496826,15 @@ │ │ pop {r4, sl, fp, lr} │ │ b 230670 <__emutls_get_address@@Base+0x37e8> │ │ │ │ 00211d3c : │ │ ldr r0, [pc, #4] @ 211d48 │ │ add r0, pc, r0 │ │ bx lr │ │ - @ instruction: 0xffe7a01a │ │ + @ instruction: 0xffe7ba96 │ │ │ │ 00211d4c : │ │ ldr r1, [pc, #12] @ 211d60 │ │ ldr r1, [pc, r1] │ │ add r1, r1, #8 │ │ str r1, [r0] │ │ bx lr │ │ @@ -497108,16 +497107,16 @@ │ │ ldr r2, [sp, #4] │ │ add r1, pc, r1 │ │ bl 234590 <__emutls_get_address@@Base+0x7708> │ │ bl 2345a0 <__emutls_get_address@@Base+0x7718> │ │ bl 233860 <__emutls_get_address@@Base+0x69d8> │ │ @ instruction: 0xffe8b518 │ │ andeq ip, r2, r0, lsl #4 │ │ - @ instruction: 0xffe78c26 │ │ - @ instruction: 0xffe75a64 │ │ + @ instruction: 0xffe7a6a2 │ │ + @ instruction: 0xffe774e0 │ │ b 234530 <__emutls_get_address@@Base+0x76a8> │ │ udf #65006 @ 0xfdee │ │ bx lr │ │ bx lr │ │ push {fp, lr} │ │ mov fp, sp │ │ bl 234530 <__emutls_get_address@@Base+0x76a8> │ │ @@ -499010,23 +499009,23 @@ │ │ movw r1, #395 @ 0x18b │ │ bl 2345c0 <__emutls_get_address@@Base+0x7738> │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ b 213e78 <__cxa_demangle@@Base+0x614> │ │ add r0, sp, #56 @ 0x38 │ │ bl 213eac <__cxa_demangle@@Base+0x648> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ - @ instruction: 0xffe76736 │ │ + @ instruction: 0xffe781b2 │ │ @ instruction: 0xffe865de │ │ andeq r9, r2, r8, asr #31 │ │ @ instruction: 0xffe82ae7 │ │ @ instruction: 0xffe71ea9 │ │ @ instruction: 0xffe6d3ea │ │ @ instruction: 0xffe6e435 │ │ - @ instruction: 0xffe79a89 │ │ - @ instruction: 0xffe78bea │ │ + @ instruction: 0xffe7b505 │ │ + @ instruction: 0xffe7a666 │ │ @ instruction: 0xffe6ff63 │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r0 │ │ movw r0, #4504 @ 0x1198 │ │ mov r5, r4 │ │ ldr r0, [r5, r0]! │ │ @@ -499845,20 +499844,20 @@ │ │ b 214b84 <__cxa_demangle@@Base+0x1320> │ │ b 214b84 <__cxa_demangle@@Base+0x1320> │ │ b 214b84 <__cxa_demangle@@Base+0x1320> │ │ b 214b84 <__cxa_demangle@@Base+0x1320> │ │ add r0, sp, #56 @ 0x38 │ │ bl 21708c <__cxa_demangle@@Base+0x3828> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ - @ instruction: 0xffe73079 │ │ - @ instruction: 0xffe720b5 │ │ + @ instruction: 0xffe74af5 │ │ + @ instruction: 0xffe73b31 │ │ andeq r8, r2, ip, lsl r2 │ │ @ instruction: 0xffe81f7f │ │ ldrdeq r8, [r2], -r4 │ │ - @ instruction: 0xffe77215 │ │ + @ instruction: 0xffe78c91 │ │ @ instruction: 0xffe6e3c2 │ │ @ instruction: 0xffe6c746 │ │ @ instruction: 0xffe6d9da │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ ldrd r4, [r1] │ │ cmp r2, #0 │ │ @@ -501312,15 +501311,15 @@ │ │ andeq r7, r2, r0, lsr r1 │ │ @ instruction: 0xffe6d2c9 │ │ andeq r7, r2, r0, ror #2 │ │ @ instruction: 0xffe7befc │ │ andeq r7, r2, r4, rrx │ │ @ instruction: 0xffe7b08c │ │ andeq r6, r2, ip, asr #30 │ │ - @ instruction: 0xffe72845 │ │ + @ instruction: 0xffe742c1 │ │ andeq r6, r2, r0, lsl pc │ │ @ instruction: 0xffe83393 │ │ andeq r7, r2, ip, asr #32 │ │ @ instruction: 0xffe86039 │ │ andeq r7, r2, ip, lsr #32 │ │ @ instruction: 0xffe6c2af │ │ andeq r7, r2, r0 │ │ @@ -501328,36 +501327,36 @@ │ │ andeq r6, r2, r8, ror #31 │ │ @ instruction: 0xffe7f0e7 │ │ andeq r6, r2, r4, ror lr │ │ @ instruction: 0xffe8426d │ │ andeq r6, r2, r0, asr #28 │ │ @ instruction: 0xffe7f3b0 │ │ andeq r6, r2, ip, lsr #31 │ │ - @ instruction: 0xffe7610d │ │ + @ instruction: 0xffe77b89 │ │ andeq r6, r2, r8, ror pc │ │ @ instruction: 0xffe7afae │ │ strheq r7, [r2], -r0 │ │ @ instruction: 0xffe8490f │ │ andeq r7, r2, r0, lsl r1 │ │ @ instruction: 0xffe81ee1 │ │ andeq r7, r2, r4, ror #1 │ │ - @ instruction: 0xffe77b70 │ │ + @ instruction: 0xffe795ec │ │ muleq r2, r0, r0 │ │ @ instruction: 0xffe85c94 │ │ andeq r6, r2, r4, lsl lr │ │ @ instruction: 0xffe7e21b │ │ - @ instruction: 0xffe75d87 │ │ + @ instruction: 0xffe77803 │ │ @ instruction: 0xffe865e5 │ │ - @ instruction: 0xffe70a01 │ │ + @ instruction: 0xffe7247d │ │ @ instruction: 0xffe84a52 │ │ @ instruction: 0xffe7c799 │ │ - @ instruction: 0xffe74032 │ │ + @ instruction: 0xffe75aae │ │ @ instruction: 0xffe7b9de │ │ @ instruction: 0xffe6cd8b │ │ - @ instruction: 0xffe74e4b │ │ + @ instruction: 0xffe768c7 │ │ @ instruction: 0xffe7e0d6 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ mov sl, r1 │ │ ldr r6, [r0] │ │ ldr r1, [r0, #4] │ │ @@ -501834,15 +501833,15 @@ │ │ mov r0, r9 │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ andeq r7, r2, ip, ror r5 │ │ andeq r6, r2, ip, lsr r7 │ │ @ instruction: 0xffe7a440 │ │ - @ instruction: 0xffe72938 │ │ + @ instruction: 0xffe743b4 │ │ andeq r7, r2, ip, lsl r0 │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ mov r4, r0 │ │ ldrd r0, [r0] │ │ subs r2, r1, r0 │ │ @@ -502148,18 +502147,18 @@ │ │ ldr r2, [pc, #24] @ 216f90 <__cxa_demangle@@Base+0x372c> │ │ ldr r3, [pc, #24] @ 216f94 <__cxa_demangle@@Base+0x3730> │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ add r3, pc, r3 │ │ bl 2345c0 <__emutls_get_address@@Base+0x7738> │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ - @ instruction: 0xffe74df1 │ │ - @ instruction: 0xffe73d8a │ │ + @ instruction: 0xffe7686d │ │ + @ instruction: 0xffe75806 │ │ @ instruction: 0xffe6a350 │ │ - @ instruction: 0xffe74e11 │ │ + @ instruction: 0xffe7688d │ │ @ instruction: 0xffe6c0a6 │ │ @ instruction: 0xffe6a342 │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ mov r7, r0 │ │ movw r0, #4504 @ 0x1198 │ │ ldr r5, [r7, r0]! │ │ @@ -502465,15 +502464,15 @@ │ │ ldr r6, [r4] │ │ and r1, r1, #61440 @ 0xf000 │ │ stm ip, {r2, r3, r6} │ │ orr r1, r1, #1344 @ 0x540 │ │ strh r1, [r0, #5] │ │ pop {r4, r5, r6, sl, fp, pc} │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ - @ instruction: 0xffe71d90 │ │ + @ instruction: 0xffe7380c │ │ muleq r2, r0, r7 │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r0 │ │ movw r0, #4504 @ 0x1198 │ │ ldr r6, [r5, r0]! │ │ mov r4, r1 │ │ @@ -502557,15 +502556,15 @@ │ │ ldr r6, [r4] │ │ and r1, r1, #61440 @ 0xf000 │ │ stm ip, {r2, r3, r6} │ │ orr r1, r1, #1344 @ 0x540 │ │ strh r1, [r0, #5] │ │ pop {r4, r5, r6, sl, fp, pc} │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ - @ instruction: 0xffe70f69 │ │ + @ instruction: 0xffe729e5 │ │ andeq r5, r2, r0, lsr #12 │ │ push {r4, r5, fp, lr} │ │ add fp, sp, #8 │ │ ldrd r4, [r0] │ │ mov r1, r0 │ │ mov r0, #1 │ │ cmp r4, r5 │ │ @@ -502708,15 +502707,15 @@ │ │ ldr r6, [r4] │ │ and r1, r1, #61440 @ 0xf000 │ │ stm ip, {r2, r3, r6} │ │ orr r1, r1, #1344 @ 0x540 │ │ strh r1, [r0, #5] │ │ pop {r4, r5, r6, sl, fp, pc} │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ - @ instruction: 0xffe72919 │ │ + @ instruction: 0xffe74395 │ │ andeq r5, r2, r4, asr #7 │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r6, r0 │ │ movw r0, #4504 @ 0x1198 │ │ ldr r7, [r6, r0]! │ │ mov r4, r1 │ │ @@ -502843,15 +502842,15 @@ │ │ ldr r6, [r4] │ │ and r1, r1, #61440 @ 0xf000 │ │ stm ip, {r2, r3, r6} │ │ orr r1, r1, #1344 @ 0x540 │ │ strh r1, [r0, #5] │ │ pop {r4, r5, r6, sl, fp, pc} │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ - @ instruction: 0xffe74f40 │ │ + @ instruction: 0xffe769bc │ │ andeq r5, r2, r8, lsr #3 │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r0 │ │ movw r0, #4504 @ 0x1198 │ │ ldr r6, [r5, r0]! │ │ mov r4, r1 │ │ @@ -503988,17 +503987,17 @@ │ │ ldr r0, [sp, #36] @ 0x24 │ │ ldr r1, [sp, #12] │ │ cmp r0, r1 │ │ beq 218c44 <__cxa_demangle@@Base+0x53e0> │ │ bl 2307f0 <__emutls_get_address@@Base+0x3968> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ andeq r5, r2, ip, ror r3 │ │ - @ instruction: 0xffe73151 │ │ + @ instruction: 0xffe74bcd │ │ @ instruction: 0xffe6a1ce │ │ - @ instruction: 0xffe73d73 │ │ + @ instruction: 0xffe757ef │ │ andeq r4, r2, r8, ror lr │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r6, r0 │ │ movw r0, #4504 @ 0x1198 │ │ ldr r7, [r6, r0]! │ │ mov r4, r1 │ │ @@ -506413,23 +506412,23 @@ │ │ bl 2345c0 <__emutls_get_address@@Base+0x7738> │ │ strb r4, [sl, #388] @ 0x184 │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ andeq r2, r2, ip, asr #5 │ │ @ instruction: 0xffe7bea7 │ │ andeq r2, r2, ip, ror #18 │ │ ldrdeq r2, [r2], -r8 │ │ - @ instruction: 0xffe6c7c1 │ │ + @ instruction: 0xffe6e23d │ │ @ instruction: 0xffe793db │ │ @ instruction: 0xffe67502 │ │ @ instruction: 0xffe7fe48 │ │ - @ instruction: 0xffe6ca4b │ │ + @ instruction: 0xffe6e4c7 │ │ @ instruction: 0xffe75dc3 │ │ - @ instruction: 0xffe6e2c5 │ │ - @ instruction: 0xffe6ba08 │ │ - @ instruction: 0xffe70b61 │ │ + @ instruction: 0xffe6fd41 │ │ + @ instruction: 0xffe6d484 │ │ + @ instruction: 0xffe725dd │ │ @ instruction: 0xffe812b4 │ │ @ instruction: 0xffe68be0 │ │ @ instruction: 0xffe7e208 │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ mov r7, r0 │ │ movw r0, #4504 @ 0x1198 │ │ @@ -507588,30 +507587,30 @@ │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ @ instruction: 0xffe811dd │ │ @ instruction: 0xffe7f9e6 │ │ @ instruction: 0xffe7f9d2 │ │ @ instruction: 0xffe66f49 │ │ @ instruction: 0xffe75c18 │ │ @ instruction: 0xffe74e8c │ │ - @ instruction: 0xffe6ca25 │ │ + @ instruction: 0xffe6e4a1 │ │ @ instruction: 0xffe7d317 │ │ - @ instruction: 0xffe6d775 │ │ + @ instruction: 0xffe6f1f1 │ │ @ instruction: 0xffe78665 │ │ - @ instruction: 0xffe71643 │ │ + @ instruction: 0xffe730bf │ │ @ instruction: 0xffe7ec2a │ │ @ instruction: 0xffe791d2 │ │ @ instruction: 0xffe78fc3 │ │ - @ instruction: 0xffe6fa21 │ │ + @ instruction: 0xffe7149d │ │ @ instruction: 0xffe7490e │ │ strdeq r0, [r2], -r0 @ │ │ andeq r0, r2, r0, asr #27 │ │ andeq r0, r2, r8, lsl lr │ │ - @ instruction: 0xffe6e3f6 │ │ + @ instruction: 0xffe6fe72 │ │ @ instruction: 0xffe7ba29 │ │ - @ instruction: 0xffe6d4d0 │ │ + @ instruction: 0xffe6ef4c │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #8 │ │ ldr r8, [r0] │ │ mov r4, r0 │ │ ldr r5, [r0, #4] │ │ sub r1, r5, r8 │ │ @@ -508082,18 +508081,18 @@ │ │ add r2, pc, r2 │ │ add r3, pc, r3 │ │ bl 2345c0 <__emutls_get_address@@Base+0x7738> │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ andeq r0, r2, r4, lsl r3 │ │ @ instruction: 0xffe78234 │ │ andeq r0, r2, ip, asr #18 │ │ - @ instruction: 0xffe70a71 │ │ + @ instruction: 0xffe724ed │ │ @ instruction: 0xffe76aea │ │ @ instruction: 0xffe69132 │ │ - @ instruction: 0xffe6f165 │ │ + @ instruction: 0xffe70be1 │ │ @ instruction: 0xffe7f8b8 │ │ @ instruction: 0xffe671e4 │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ mov r4, r0 │ │ ldrd r0, [r0] │ │ cmp r1, r0 │ │ @@ -511812,24 +511811,24 @@ │ │ bl 2218fc <__cxa_demangle@@Base+0xe098> │ │ ldr r0, [sp, #12] │ │ str r0, [r4, #392] @ 0x188 │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ @ instruction: 0xffe63f0d │ │ andeq sp, r1, r4, lsr r1 │ │ @ instruction: 0xffe70d48 │ │ - @ instruction: 0xffe68333 │ │ - @ instruction: 0xffe6b721 │ │ + @ instruction: 0xffe69daf │ │ + @ instruction: 0xffe6d19d │ │ @ instruction: 0xffe713a8 │ │ - @ instruction: 0xffe6b766 │ │ - @ instruction: 0xffe6c630 │ │ + @ instruction: 0xffe6d1e2 │ │ + @ instruction: 0xffe6e0ac │ │ andeq ip, r1, r0, ror #29 │ │ - @ instruction: 0xffe6b741 │ │ - @ instruction: 0xffe6cecb │ │ + @ instruction: 0xffe6d1bd │ │ + @ instruction: 0xffe6e947 │ │ @ instruction: 0xffe647c0 │ │ - @ instruction: 0xffe6ad82 │ │ + @ instruction: 0xffe6c7fe │ │ andeq ip, r1, r0, ror r6 │ │ @ instruction: 0xffe79a53 │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r0 │ │ movw r0, #4504 @ 0x1198 │ │ ldr r6, [r5, r0]! │ │ @@ -512133,15 +512132,15 @@ │ │ mov r2, r6 │ │ bl 22d704 <__emutls_get_address@@Base+0x87c> │ │ ldr r0, [r4, #4] │ │ add r0, r0, r6 │ │ str r0, [r4, #4] │ │ pop {r4, r5, r6, sl, fp, pc} │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ - @ instruction: 0xffe685ce │ │ + @ instruction: 0xffe6a04a │ │ @ instruction: 0xffe76978 │ │ b 230670 <__emutls_get_address@@Base+0x37e8> │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #40 @ 0x28 │ │ ldr r3, [r0, #8] │ │ ldr r0, [r0, #12] │ │ @@ -512407,15 +512406,15 @@ │ │ bl 22d704 <__emutls_get_address@@Base+0x87c> │ │ ldr r0, [r8, #4] │ │ add r0, r0, r5 │ │ str r0, [r8, #4] │ │ sub sp, fp, #24 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ - @ instruction: 0xffe65b12 │ │ + @ instruction: 0xffe6758e │ │ b 230670 <__emutls_get_address@@Base+0x37e8> │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #64 @ 0x40 │ │ mov r8, r1 │ │ ldr r1, [r0, #8] │ │ ldr r0, [r0, #12] │ │ @@ -512987,16 +512986,16 @@ │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ @ instruction: 0xffe5fef7 │ │ andeq fp, r1, r4, lsl #27 │ │ @ instruction: 0xffe6f8d3 │ │ andeq fp, r1, r0, lsr sp │ │ @ instruction: 0xffe63a0d │ │ andeq fp, r1, r8, lsl #23 │ │ - @ instruction: 0xffe6a4c1 │ │ - @ instruction: 0xffe6bc4b │ │ + @ instruction: 0xffe6bf3d │ │ + @ instruction: 0xffe6d6c7 │ │ @ instruction: 0xffe63540 │ │ @ instruction: 0xffe72313 │ │ andeq fp, r1, r4, asr sp │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ ldr r1, [r0] │ │ mov r4, r0 │ │ @@ -513020,16 +513019,16 @@ │ │ ldr r3, [pc, #28] @ 221974 <__cxa_demangle@@Base+0xe110> │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ add r3, pc, r3 │ │ movw r1, #2409 @ 0x969 │ │ bl 2345c0 <__emutls_get_address@@Base+0x7738> │ │ blx a8d68 │ │ - @ instruction: 0xffe6a415 │ │ - @ instruction: 0xffe6bb9f │ │ + @ instruction: 0xffe6be91 │ │ + @ instruction: 0xffe6d61b │ │ @ instruction: 0xffe63494 │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r4, r1 │ │ ldr r1, [r1, #4] │ │ ldr r2, [r4, #8] │ │ mov r5, r0 │ │ @@ -513197,17 +513196,17 @@ │ │ ldr r3, [pc, #28] @ 221c38 <__cxa_demangle@@Base+0xe3d4> │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ add r3, pc, r3 │ │ bl 2345c0 <__emutls_get_address@@Base+0x7738> │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ andeq fp, r1, r0, asr #15 │ │ - @ instruction: 0xffe6a151 │ │ + @ instruction: 0xffe6bbcd │ │ @ instruction: 0xffe611ce │ │ - @ instruction: 0xffe6ad73 │ │ + @ instruction: 0xffe6c7ef │ │ push {r4, r5, r6, r7, r8, r9, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #24 │ │ mov r5, r0 │ │ ldr r0, [r0, #8] │ │ mov r8, r1 │ │ cmp r0, #2 │ │ @@ -516764,21 +516763,21 @@ │ │ ldr r3, [pc, #48] @ 225408 <__cxa_demangle@@Base+0x11ba4> │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ add r3, pc, r3 │ │ bl 2345c0 <__emutls_get_address@@Base+0x7738> │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ @ instruction: 0xffe5de32 │ │ - @ instruction: 0xffe65a4d │ │ - @ instruction: 0xffe683ce │ │ - @ instruction: 0xffe64e38 │ │ - @ instruction: 0xffe659db │ │ + @ instruction: 0xffe674c9 │ │ + @ instruction: 0xffe69e4a │ │ + @ instruction: 0xffe668b4 │ │ + @ instruction: 0xffe67457 │ │ @ instruction: 0xffe7074c │ │ - @ instruction: 0xffe66995 │ │ - @ instruction: 0xffe63178 │ │ + @ instruction: 0xffe68411 │ │ + @ instruction: 0xffe64bf4 │ │ @ instruction: 0xffe6d469 │ │ @ instruction: 0xffe5dde6 │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ ldr r5, [pc, #232] @ 225508 <__cxa_demangle@@Base+0x11ca4> │ │ mov r8, r0 │ │ ldr r0, [pc, #228] @ 22550c <__cxa_demangle@@Base+0x11ca8> │ │ @@ -516836,22 +516835,22 @@ │ │ ldr r2, [pc, #48] @ 225528 <__cxa_demangle@@Base+0x11cc4> │ │ ldr r3, [pc, #48] @ 22552c <__cxa_demangle@@Base+0x11cc8> │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ add r3, pc, r3 │ │ bl 2345c0 <__emutls_get_address@@Base+0x7738> │ │ @ instruction: 0xffe5dca2 │ │ - @ instruction: 0xffe658bd │ │ - @ instruction: 0xffe64cc4 │ │ - @ instruction: 0xffe65827 │ │ + @ instruction: 0xffe67339 │ │ + @ instruction: 0xffe66740 │ │ + @ instruction: 0xffe672a3 │ │ @ instruction: 0xffe5dc6e │ │ - @ instruction: 0xffe68256 │ │ + @ instruction: 0xffe69cd2 │ │ @ instruction: 0xffe705e4 │ │ - @ instruction: 0xffe66871 │ │ - @ instruction: 0xffe63054 │ │ + @ instruction: 0xffe682ed │ │ + @ instruction: 0xffe64ad0 │ │ @ instruction: 0xffe6d345 │ │ b 230670 <__emutls_get_address@@Base+0x37e8> │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r4, r1 │ │ ldr r1, [r1, #4] │ │ @@ -519820,15 +519819,15 @@ │ │ orr r0, r0, #1344 @ 0x540 │ │ str r5, [r6, #16] │ │ strh r0, [r6, #5] │ │ mov r0, r6 │ │ pop {r4, r5, r6, r7, r8, sl, fp, pc} │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ @ instruction: 0xffe743fe │ │ - @ instruction: 0xffe60f33 │ │ + @ instruction: 0xffe629af │ │ @ instruction: 0xffe70e5f │ │ @ instruction: 0xffe689c6 │ │ @ instruction: 0xffe6d7f6 │ │ @ instruction: 0xffe6bf01 │ │ andeq r5, r1, r4, asr #21 │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ @@ -519963,15 +519962,15 @@ │ │ and r1, r1, #61440 @ 0xf000 │ │ str r2, [r0, #12] │ │ orr r1, r1, #1344 @ 0x540 │ │ str r3, [r0, #16] │ │ strh r1, [r0, #5] │ │ pop {r4, r5, r6, sl, fp, pc} │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ - @ instruction: 0xffe5e4e7 │ │ + @ instruction: 0xffe5ff63 │ │ andeq r5, r1, r4, lsr r9 │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r0 │ │ movw r0, #4504 @ 0x1198 │ │ ldr r6, [r5, r0]! │ │ mov r4, r1 │ │ @@ -522245,16 +522244,16 @@ │ │ strb r0, [r4, #16] │ │ sub sp, fp, #16 │ │ pop {r4, r5, r6, r7, fp, pc} │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ mov r0, #0 │ │ strb r0, [r4, #16] │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ - @ instruction: 0xffe605a6 │ │ - @ instruction: 0xffe5f853 │ │ + @ instruction: 0xffe62022 │ │ + @ instruction: 0xffe612cf │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r4, r0 │ │ ldrb r0, [r0, #16] │ │ cmp r0, #0 │ │ beq 22a9bc <__cxa_demangle@@Base+0x17158> │ │ @@ -522430,15 +522429,15 @@ │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ b 22ac60 <__cxa_demangle@@Base+0x173fc> │ │ ldr r0, [sp] │ │ cmp r0, r8 │ │ beq 22ac70 <__cxa_demangle@@Base+0x1740c> │ │ bl 2307f0 <__emutls_get_address@@Base+0x3968> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ - @ instruction: 0xffe61125 │ │ + @ instruction: 0xffe62ba1 │ │ @ instruction: 0xffe6e49e │ │ @ instruction: 0xffe66d64 │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r0 │ │ ldr r0, [r0, #8] │ │ mov r4, r1 │ │ @@ -523381,15 +523380,15 @@ │ │ bl 233550 <__emutls_get_address@@Base+0x66c8> │ │ bl 2306a0 <__emutls_get_address@@Base+0x3818> │ │ blx a8d68 │ │ andeq r8, r1, r4, asr r5 │ │ andeq r8, r1, ip, lsr r3 │ │ @ instruction: 0xffe64517 │ │ @ instruction: 0xffe564f8 │ │ - @ instruction: 0xffe60401 │ │ + @ instruction: 0xffe61e7d │ │ @ instruction: 0xffe64567 │ │ @ instruction: 0xffe56548 │ │ @ instruction: 0xffe6d81a │ │ andeq r8, r1, r4, lsr r4 │ │ strdeq r8, [r1], -r8 @ │ │ ldr r1, [pc, #28] @ 22ba5c <__cxa_uncaught_exceptions@@Base+0x230> │ │ add r1, pc, r1 │ │ @@ -524062,25 +524061,25 @@ │ │ ldr r2, [pc, #32] @ 22c4c8 <__gxx_personality_v0@@Base+0x974> │ │ ldr r3, [pc, #32] @ 22c4cc <__gxx_personality_v0@@Base+0x978> │ │ add r0, pc, r0 │ │ add r2, pc, r2 │ │ add r3, pc, r3 │ │ bl 2345c0 <__emutls_get_address@@Base+0x7738> │ │ @ instruction: 0xffe68918 │ │ - @ instruction: 0xffe5b3e3 │ │ - @ instruction: 0xffe5ea25 │ │ + @ instruction: 0xffe5ce5f │ │ + @ instruction: 0xffe604a1 │ │ @ instruction: 0xffe688ec │ │ @ instruction: 0xffe6f3af │ │ - @ instruction: 0xffe5a5e8 │ │ + @ instruction: 0xffe5c064 │ │ @ instruction: 0xffe68950 │ │ @ instruction: 0xffe6f413 │ │ @ instruction: 0xffe7021d │ │ @ instruction: 0xffe68af0 │ │ - @ instruction: 0xffe5cf56 │ │ - @ instruction: 0xffe5ebfd │ │ + @ instruction: 0xffe5e9d2 │ │ + @ instruction: 0xffe60679 │ │ @ instruction: 0xffe68a3c │ │ @ instruction: 0xffe6f4ff │ │ @ instruction: 0xffe63bca │ │ │ │ 0022c4f4 <__cxa_call_unexpected@@Base>: │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ @@ -524388,16 +524387,16 @@ │ │ add r2, pc, r2 │ │ add r3, pc, r3 │ │ bl 2345c0 <__emutls_get_address@@Base+0x7738> │ │ ldr r0, [fp, #16] │ │ bl 230640 <__emutls_get_address@@Base+0x37b8> │ │ bl 230650 <__emutls_get_address@@Base+0x37c8> │ │ @ instruction: 0xffe683e8 │ │ - @ instruction: 0xffe5c84e │ │ - @ instruction: 0xffe5e4f5 │ │ + @ instruction: 0xffe5e2ca │ │ + @ instruction: 0xffe5ff71 │ │ ldrble sp, [r4], #1236 @ 0x4d4 │ │ push {r4, r7, lr} │ │ add r7, sp, #4 │ │ eor r4, r0, r1 │ │ eor r2, r0, r0, asr #31 │ │ eor r3, r1, r1, asr #31 │ │ sub r0, r2, r0, asr #31 │ │ @@ -525698,15 +525697,15 @@ │ │ ldr r0, [pc, r0] │ │ add r4, r0, #168 @ 0xa8 │ │ mov r0, r4 │ │ bl 232e80 <__emutls_get_address@@Base+0x5ff8> │ │ mov r0, r4 │ │ bl 2312f0 <__emutls_get_address@@Base+0x4468> │ │ bl 233860 <__emutls_get_address@@Base+0x69d8> │ │ - @ instruction: 0xffe5a7a5 │ │ + @ instruction: 0xffe5c221 │ │ @ instruction: 0xffe62140 │ │ @ instruction: 0xffe6b3cd │ │ andeq r0, r1, r0, lsr r4 │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ ldr r6, [fp, #8] │ │ mov r5, r2 │ │ @@ -525769,15 +525768,15 @@ │ │ ldr r0, [pc, r0] │ │ add r4, r0, #168 @ 0xa8 │ │ mov r0, r4 │ │ bl 232e80 <__emutls_get_address@@Base+0x5ff8> │ │ mov r0, r4 │ │ bl 2312f0 <__emutls_get_address@@Base+0x4468> │ │ bl 233860 <__emutls_get_address@@Base+0x69d8> │ │ - @ instruction: 0xffe5a689 │ │ + @ instruction: 0xffe5c105 │ │ @ instruction: 0xffe69807 │ │ @ instruction: 0xffe6b2b1 │ │ andeq r0, r1, r4, lsl r3 │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ add fp, sp, #28 │ │ sub sp, sp, #20 │ │ mov r7, r3 │ │ @@ -526085,15 +526084,15 @@ │ │ ldr r0, [pc, r0] │ │ add r4, r0, #168 @ 0xa8 │ │ mov r0, r4 │ │ bl 232e80 <__emutls_get_address@@Base+0x5ff8> │ │ mov r0, r4 │ │ bl 2312f0 <__emutls_get_address@@Base+0x4468> │ │ bl 233860 <__emutls_get_address@@Base+0x69d8> │ │ - @ instruction: 0xffe5a199 │ │ + @ instruction: 0xffe5bc15 │ │ @ instruction: 0xffe56a09 │ │ @ instruction: 0xffe6adc1 │ │ andeq pc, r0, r4, lsr #28 │ │ mov r0, r1 │ │ mov r1, r2 │ │ b 22e464 <__emutls_get_address@@Base+0x15dc> │ │ push {r4, r5, r6, r7, r8, r9, sl, fp, lr} │ │ @@ -526230,19 +526229,19 @@ │ │ ldr r0, [pc, r0] │ │ add r4, r0, #168 @ 0xa8 │ │ mov r0, r4 │ │ bl 232e80 <__emutls_get_address@@Base+0x5ff8> │ │ mov r0, r4 │ │ bl 2312f0 <__emutls_get_address@@Base+0x4468> │ │ bl 233860 <__emutls_get_address@@Base+0x69d8> │ │ - @ instruction: 0xffe59f55 │ │ + @ instruction: 0xffe5b9d1 │ │ @ instruction: 0xffe618dd │ │ @ instruction: 0xffe6ab98 │ │ andeq pc, r0, r0, ror #23 │ │ - @ instruction: 0xffe59f8d │ │ + @ instruction: 0xffe5ba09 │ │ @ instruction: 0xffe61915 │ │ @ instruction: 0xffe68373 │ │ andeq pc, r0, r8, lsl ip @ │ │ mov r0, r1 │ │ mov r1, r2 │ │ b 22e464 <__emutls_get_address@@Base+0x15dc> │ │ mov r0, r1 │ │ @@ -526386,16 +526385,16 @@ │ │ ldr r0, [sp, #4] │ │ str r0, [r5, #16] │ │ mov r0, r4 │ │ bl 22ee44 <__emutls_get_address@@Base+0x1fbc> │ │ sub sp, fp, #28 │ │ pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} │ │ bl 233860 <__emutls_get_address@@Base+0x69d8> │ │ - @ instruction: 0xffe59d29 │ │ - @ instruction: 0xffe5d58e │ │ + @ instruction: 0xffe5b7a5 │ │ + @ instruction: 0xffe5f00a │ │ @ instruction: 0xffe62408 │ │ @ instruction: 0x0000f9b4 │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ sub sp, sp, #736 @ 0x2e0 │ │ mov r4, r0 │ │ sub r0, fp, #344 @ 0x158 │ │ @@ -526425,17 +526424,17 @@ │ │ ldr r0, [pc, r0] │ │ add r4, r0, #168 @ 0xa8 │ │ mov r0, r4 │ │ bl 232e80 <__emutls_get_address@@Base+0x5ff8> │ │ mov r0, r4 │ │ bl 2312f0 <__emutls_get_address@@Base+0x4468> │ │ bl 233860 <__emutls_get_address@@Base+0x69d8> │ │ - @ instruction: 0xffe59c49 │ │ + @ instruction: 0xffe5b6c5 │ │ @ instruction: 0xffe573fa │ │ - @ instruction: 0xffe5b7e5 │ │ + @ instruction: 0xffe5d261 │ │ ldrdeq pc, [r0], -r4 │ │ push {r4, r5, r6, r7, r8, sl, fp, lr} │ │ add fp, sp, #24 │ │ sub sp, sp, #48 @ 0x30 │ │ mov r6, r1 │ │ mov r1, r0 │ │ mov r0, r6 │ │ @@ -526796,16 +526795,16 @@ │ │ bl 232e80 <__emutls_get_address@@Base+0x5ff8> │ │ mov r0, r4 │ │ bl 2312f0 <__emutls_get_address@@Base+0x4468> │ │ bl 233860 <__emutls_get_address@@Base+0x69d8> │ │ add r0, r0, #64 @ 0x40 │ │ ldr r0, [r0] │ │ pop {r4, sl, fp, pc} │ │ - @ instruction: 0xffe59689 │ │ - @ instruction: 0xffe59695 │ │ + @ instruction: 0xffe5b105 │ │ + @ instruction: 0xffe5b111 │ │ @ instruction: 0xffe56e45 │ │ andeq pc, r0, r4, lsl r3 @ │ │ push {r4, sl, fp, lr} │ │ add fp, sp, #8 │ │ add r3, r1, #2 │ │ cmp r3, #17 │ │ bhi 22eff4 <__emutls_get_address@@Base+0x216c> │ │ @@ -526854,15 +526853,15 @@ │ │ ldr r0, [pc, r0] │ │ add r4, r0, #168 @ 0xa8 │ │ mov r0, r4 │ │ bl 232e80 <__emutls_get_address@@Base+0x5ff8> │ │ mov r0, r4 │ │ bl 2312f0 <__emutls_get_address@@Base+0x4468> │ │ bl 233860 <__emutls_get_address@@Base+0x69d8> │ │ - @ instruction: 0xffe59595 │ │ + @ instruction: 0xffe5b011 │ │ @ instruction: 0xffe60f49 │ │ @ instruction: 0xffe56d51 │ │ andeq pc, r0, r0, lsr #4 │ │ bic r0, r1, #31 │ │ sub r0, r0, #256 @ 0x100 │ │ clz r0, r0 │ │ lsr r0, r0, #5 │ │ @@ -526921,15 +526920,15 @@ │ │ ldr r0, [pc, r0] │ │ add r4, r0, #168 @ 0xa8 │ │ mov r0, r4 │ │ bl 232e80 <__emutls_get_address@@Base+0x5ff8> │ │ mov r0, r4 │ │ bl 2312f0 <__emutls_get_address@@Base+0x4468> │ │ bl 233860 <__emutls_get_address@@Base+0x69d8> │ │ - @ instruction: 0xffe59489 │ │ + @ instruction: 0xffe5af05 │ │ @ instruction: 0xffe6b9c7 │ │ @ instruction: 0xffe521b5 │ │ andeq pc, r0, r4, lsl r1 @ │ │ push {r4, r5, r6, r7, fp, lr} │ │ add fp, sp, #16 │ │ mov r5, r0 │ │ bic r0, r1, #15 │ │ @@ -526985,16 +526984,16 @@ │ │ ldr r0, [pc, r0] │ │ add r4, r0, #168 @ 0xa8 │ │ mov r0, r4 │ │ bl 232e80 <__emutls_get_address@@Base+0x5ff8> │ │ mov r0, r4 │ │ bl 2312f0 <__emutls_get_address@@Base+0x4468> │ │ bl 233860 <__emutls_get_address@@Base+0x69d8> │ │ - @ instruction: 0xffe59389 │ │ - @ instruction: 0xffe5bd18 │ │ + @ instruction: 0xffe5ae05 │ │ + @ instruction: 0xffe5d794 │ │ @ instruction: 0xffe520b5 │ │ andeq pc, r0, r4, lsl r0 @ │ │ push {r4, r5, r6, sl, fp, lr} │ │ add fp, sp, #16 │ │ sub sp, sp, #8 │ │ mov r5, r0 │ │ ldrb r0, [r0, #384] @ 0x180 │ │ @@ -527249,22 +527248,22 @@ │ │ mov r0, r4 │ │ bl 232e80 <__emutls_get_address@@Base+0x5ff8> │ │ mov r0, r4 │ │ bl 2312f0 <__emutls_get_address@@Base+0x4468> │ │ bl 233860 <__emutls_get_address@@Base+0x69d8> │ │ andeq lr, r0, r8, asr #28 │ │ andeq lr, r0, r8, ror #28 │ │ - @ instruction: 0xffe58f71 │ │ + @ instruction: 0xffe5a9ed │ │ @ instruction: 0xffe616b7 │ │ @ instruction: 0xffe51cb8 │ │ strdeq lr, [r0], -ip │ │ andeq lr, r0, ip, asr lr │ │ - @ instruction: 0xffe58fa9 │ │ + @ instruction: 0xffe5aa25 │ │ @ instruction: 0xffe616ef │ │ - @ instruction: 0xffe5e0cc │ │ + @ instruction: 0xffe5fb48 │ │ andeq lr, r0, r4, lsr ip │ │ add r1, r0, #2 │ │ lsr r0, r1, #1 │ │ cmp r0, #144 @ 0x90 │ │ bhi 22fbfc <__emutls_get_address@@Base+0x2d74> │ │ ldr r0, [pc, #2132] @ 22ff08 <__emutls_get_address@@Base+0x3080> │ │ add r2, pc, #8 │ │ @@ -527806,86 +527805,86 @@ │ │ @ instruction: 0xffe63bab │ │ @ instruction: 0xffe65f41 │ │ @ instruction: 0xffe62d02 │ │ @ instruction: 0xffe517b4 │ │ @ instruction: 0xffe552c1 │ │ @ instruction: 0xffe61193 │ │ @ instruction: 0xffe542b2 │ │ - @ instruction: 0xffe5db86 │ │ + @ instruction: 0xffe5f602 │ │ @ instruction: 0xffe52365 │ │ - @ instruction: 0xffe5a5c3 │ │ - @ instruction: 0xffe5b399 │ │ + @ instruction: 0xffe5c03f │ │ + @ instruction: 0xffe5ce15 │ │ @ instruction: 0xffe645ea │ │ @ instruction: 0xffe645e2 │ │ - @ instruction: 0xffe5a596 │ │ + @ instruction: 0xffe5c012 │ │ @ instruction: 0xffe645b6 │ │ @ instruction: 0xffe651af │ │ - @ instruction: 0xffe5db05 │ │ + @ instruction: 0xffe5f581 │ │ @ instruction: 0xffe64595 │ │ - @ instruction: 0xffe57cac │ │ + @ instruction: 0xffe59728 │ │ @ instruction: 0xffe6d98f │ │ @ instruction: 0xffe56142 │ │ @ instruction: 0xffe65e3c │ │ @ instruction: 0xffe551d4 │ │ - @ instruction: 0xffe5dab4 │ │ + @ instruction: 0xffe5f530 │ │ @ instruction: 0xffe63ad8 │ │ @ instruction: 0xffe62bd9 │ │ @ instruction: 0xffe560fd │ │ @ instruction: 0xffe6957a │ │ @ instruction: 0xffe6d926 │ │ @ instruction: 0xffe54189 │ │ @ instruction: 0xffe66cfa │ │ @ instruction: 0xffe5516b │ │ - @ instruction: 0xffe5da4b │ │ + @ instruction: 0xffe5f4c7 │ │ @ instruction: 0xffe644d8 │ │ @ instruction: 0xffe60281 │ │ @ instruction: 0xffe533bf │ │ - @ instruction: 0xffe5ccb2 │ │ + @ instruction: 0xffe5e72e │ │ @ instruction: 0xffe6bbad │ │ @ instruction: 0xffe6ade0 │ │ @ instruction: 0xffe54115 │ │ @ instruction: 0xffe66c86 │ │ @ instruction: 0xffe521c4 │ │ @ instruction: 0xffe6d882 │ │ @ instruction: 0xffe540e9 │ │ @ instruction: 0xffe60faa │ │ @ instruction: 0xffe515a7 │ │ @ instruction: 0xffe62ae1 │ │ @ instruction: 0xffe6c901 │ │ @ instruction: 0xffe51587 │ │ @ instruction: 0xffe5331b │ │ @ instruction: 0xffe6ad54 │ │ - @ instruction: 0xffe5880d │ │ - @ instruction: 0xffe5a3ae │ │ + @ instruction: 0xffe5a289 │ │ + @ instruction: 0xffe5be2a │ │ @ instruction: 0xffe68306 │ │ @ instruction: 0xffe60195 │ │ - @ instruction: 0xffe5c038 │ │ - @ instruction: 0xffe5a381 │ │ - @ instruction: 0xffe59481 │ │ + @ instruction: 0xffe5dab4 │ │ + @ instruction: 0xffe5bdfd │ │ + @ instruction: 0xffe5aefd │ │ @ instruction: 0xffe55f81 │ │ @ instruction: 0xffe643a4 │ │ @ instruction: 0xffe60150 │ │ - @ instruction: 0xffe5bff3 │ │ - @ instruction: 0xffe5bfeb │ │ + @ instruction: 0xffe5da6f │ │ + @ instruction: 0xffe5da67 │ │ @ instruction: 0xffe6d78a │ │ @ instruction: 0xffe64f66 │ │ - @ instruction: 0xffe5cb5a │ │ - @ instruction: 0xffe59419 │ │ + @ instruction: 0xffe5e5d6 │ │ + @ instruction: 0xffe5ae95 │ │ @ instruction: 0xffe638d8 │ │ @ instruction: 0xffe64f3a │ │ @ instruction: 0xffe66b2e │ │ - @ instruction: 0xffe5872c │ │ + @ instruction: 0xffe5a1a8 │ │ @ instruction: 0xffe61ca4 │ │ - @ instruction: 0xffe56c18 │ │ + @ instruction: 0xffe58694 │ │ @ instruction: 0xffe6d716 │ │ - @ instruction: 0xffe58700 │ │ + @ instruction: 0xffe5a17c │ │ @ instruction: 0xffe6933e │ │ @ instruction: 0xffe64ede │ │ @ instruction: 0xffe62970 │ │ - @ instruction: 0xffe57ceb │ │ + @ instruction: 0xffe59767 │ │ mov lr, r0 │ │ ldm lr, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip} │ │ ldr sp, [lr, #52] @ 0x34 │ │ ldr lr, [lr, #60] @ 0x3c │ │ bx lr │ │ vldmia r0, {d0-d15} │ │ bx lr │ ├── readelf --wide --decompress --hex-dump=.data.rel.ro {} │ │ @@ -1,56 +1,56 @@ │ │ │ │ Hex dump of section '.data.rel.ro': │ │ 0x00235650 50562300 00000000 00000000 00000000 PV#............. │ │ 0x00235660 00000000 dd910a00 df910a00 e1910a00 ................ │ │ 0x00235670 e3910a00 00000000 00000000 40072400 ............@.$. │ │ - 0x00235680 68af0800 5d3e0800 32000000 01000000 h...]>..2....... │ │ + 0x00235680 e4c90800 5d3e0800 32000000 01000000 ....]>..2....... │ │ 0x00235690 44072400 5aa00900 5d3e0800 37000000 D.$.Z...]>..7... │ │ 0x002356a0 01000000 48072400 36130800 5d3e0800 ....H.$.6...]>.. │ │ 0x002356b0 3c000000 01000000 4c072400 300d0900 <.......L.$.0... │ │ 0x002356c0 5d3e0800 51000000 01000000 50072400 ]>..Q.......P.$. │ │ 0x002356d0 de4d0900 5d3e0800 5a000000 01000000 .M..]>..Z....... │ │ - 0x002356e0 54072400 e8850800 5d3e0800 60000000 T.$.....]>..`... │ │ + 0x002356e0 54072400 64a00800 5d3e0800 60000000 T.$.d...]>..`... │ │ 0x002356f0 01000000 08000000 00000000 00000000 ................ │ │ 0x00235700 28572300 ab940a00 6d940a00 71940a00 (W#.....m...q... │ │ 0x00235710 7b940a00 85940a00 8f940a00 99940a00 {............... │ │ 0x00235720 08000000 01e00900 08000000 d2df0900 ................ │ │ - 0x00235730 20572300 74072400 83af0800 791b0900 W#.t.$.....y... │ │ + 0x00235730 20572300 74072400 ffc90800 791b0900 W#.t.$.....y... │ │ 0x00235740 6a010000 01000000 78072400 75130800 j.......x.$.u... │ │ 0x00235750 791b0900 72010000 01000000 7c072400 y...r.......|.$. │ │ 0x00235760 f1800900 791b0900 7a010000 01000000 ....y...z....... │ │ - 0x00235770 80072400 a1920800 791b0900 82010000 ..$.....y....... │ │ + 0x00235770 80072400 1dad0800 791b0900 82010000 ..$.....y....... │ │ 0x00235780 01000000 84072400 37810900 791b0900 ......$.7...y... │ │ - 0x00235790 8a010000 01000000 88072400 edc90800 ..........$..... │ │ + 0x00235790 8a010000 01000000 88072400 69e40800 ..........$.i... │ │ 0x002357a0 791b0900 91010000 01000000 8c072400 y.............$. │ │ 0x002357b0 40040800 791b0900 98010000 01000000 @...y........... │ │ 0x002357c0 90072400 d8410900 791b0900 a0010000 ..$..A..y....... │ │ 0x002357d0 01000000 94072400 201f0800 791b0900 ......$. ...y... │ │ 0x002357e0 a8010000 01000000 98072400 0e000900 ..........$..... │ │ 0x002357f0 791b0900 b0010000 01000000 9c072400 y.............$. │ │ 0x00235800 6e040800 791b0900 94030000 01000000 n...y........... │ │ 0x00235810 a0072400 134e0900 791b0900 9c030000 ..$..N..y....... │ │ 0x00235820 01000000 a4072400 d43e0800 791b0900 ......$..>..y... │ │ 0x00235830 a3030000 01000000 a8072400 6c370900 ..........$.l7.. │ │ 0x00235840 791b0900 aa030000 01000000 ac072400 y.............$. │ │ - 0x00235850 43be0800 791b0900 dd030000 01000000 C...y........... │ │ + 0x00235850 bfd80800 791b0900 dd030000 01000000 ....y........... │ │ 0x00235860 b0072400 5b4e0900 791b0900 e6030000 ..$.[N..y....... │ │ - 0x00235870 01000000 b4072400 c9af0800 791b0900 ......$.....y... │ │ + 0x00235870 01000000 b4072400 45ca0800 791b0900 ......$.E...y... │ │ 0x00235880 ee030000 01000000 b8072400 32920900 ..........$.2... │ │ 0x00235890 791b0900 0f040000 01000000 bc072400 y.............$. │ │ 0x002358a0 ed1b0900 791b0900 9b040000 01000000 ....y........... │ │ 0x002358b0 c0072400 9d4e0900 791b0900 bc060000 ..$..N..y....... │ │ 0x002358c0 01000000 00000000 00000000 00000000 ................ │ │ 0x002358d0 00000000 00000000 00000000 00000000 ................ │ │ 0x002358e0 00000000 71f50a00 d5f50a00 39f60a00 ....q.......9... │ │ 0x002358f0 b3f60a00 2df70a00 a7f70a00 35f80a00 ....-.......5... │ │ - 0x00235900 00000000 c4072400 2da20800 681c0900 ......$.-...h... │ │ + 0x00235900 00000000 c4072400 a9bc0800 681c0900 ......$.....h... │ │ 0x00235910 1d020000 01000000 c8072400 b8810900 ..........$..... │ │ 0x00235920 681c0900 1d020000 01000000 cc072400 h.............$. │ │ - 0x00235930 1fca0800 681c0900 1d020000 01000000 ....h........... │ │ + 0x00235930 9be40800 681c0900 1d020000 01000000 ....h........... │ │ 0x00235940 d0072400 86280900 681c0900 1d020000 ..$..(..h....... │ │ 0x00235950 01000000 d4072400 3f000900 681c0900 ......$.?...h... │ │ 0x00235960 1d020000 01000000 d8072400 c1130800 ..........$..... │ │ 0x00235970 681c0900 1d020000 01000000 dc072400 h.............$. │ │ 0x00235980 3f420900 681c0900 1d020000 01000000 ?B..h........... │ │ 0x00235990 e0072400 473f0800 681c0900 1e020000 ..$.G?..h....... │ │ 0x002359a0 01000000 e4072400 d44e0800 681c0900 ......$..N..h... │ │ @@ -70,65 +70,65 @@ │ │ 0x00235a80 10082400 e7a00900 681c0900 20020000 ..$.....h... ... │ │ 0x00235a90 01000000 14082400 8e820900 681c0900 ......$.....h... │ │ 0x00235aa0 20020000 01000000 18082400 3f4f0800 .........$.?O.. │ │ 0x00235ab0 681c0900 21020000 01000000 1c082400 h...!.........$. │ │ 0x00235ac0 e3300800 681c0900 21020000 01000000 .0..h...!....... │ │ 0x00235ad0 20082400 4c200800 681c0900 21020000 .$.L ..h...!... │ │ 0x00235ae0 01000000 24082400 785b0900 681c0900 ....$.$.x[..h... │ │ - 0x00235af0 21020000 01000000 28082400 1e6b0800 !.......(.$..k.. │ │ + 0x00235af0 21020000 01000000 28082400 9a850800 !.......(.$..... │ │ 0x00235b00 681c0900 21020000 01000000 2c082400 h...!.......,.$. │ │ 0x00235b10 4e310800 681c0900 21020000 01000000 N1..h...!....... │ │ 0x00235b20 30082400 dfc60900 681c0900 21020000 0.$.....h...!... │ │ - 0x00235b30 01000000 34082400 846b0800 681c0900 ....4.$..k..h... │ │ + 0x00235b30 01000000 34082400 00860800 681c0900 ....4.$.....h... │ │ 0x00235b40 23020000 01000000 38082400 4ec70900 #.......8.$.N... │ │ 0x00235b50 681c0900 23020000 01000000 3c082400 h...#.......<.$. │ │ - 0x00235b60 8eca0800 681c0900 23020000 01000000 ....h...#....... │ │ + 0x00235b60 0ae50800 681c0900 23020000 01000000 ....h...#....... │ │ 0x00235b70 40082400 53a10900 681c0900 23020000 @.$.S...h...#... │ │ 0x00235b80 01000000 44082400 e45b0900 681c0900 ....D.$..[..h... │ │ 0x00235b90 23020000 01000000 48082400 aa4f0800 #.......H.$..O.. │ │ 0x00235ba0 681c0900 23020000 01000000 4c082400 h...#.......L.$. │ │ - 0x00235bb0 f36b0800 681c0900 23020000 01000000 .k..h...#....... │ │ + 0x00235bb0 6f860800 681c0900 23020000 01000000 o...h...#....... │ │ 0x00235bc0 50082400 1a500800 681c0900 25020000 P.$..P..h...%... │ │ - 0x00235bd0 01000000 54082400 05b00800 681c0900 ....T.$.....h... │ │ + 0x00235bd0 01000000 54082400 81ca0800 681c0900 ....T.$.....h... │ │ 0x00235be0 26020000 01000000 58082400 e3690900 &.......X.$..i.. │ │ 0x00235bf0 681c0900 27020000 01000000 5c082400 h...'.......\.$. │ │ 0x00235c00 4e5c0900 681c0900 34020000 01000000 N\..h...4....... │ │ 0x00235c10 60082400 7a050800 681c0900 64030000 `.$.z...h...d... │ │ 0x00235c20 01000000 64082400 bb200800 681c0900 ....d.$.. ..h... │ │ - 0x00235c30 64030000 01000000 68082400 3bd70800 d.......h.$.;... │ │ + 0x00235c30 64030000 01000000 68082400 b7f10800 d.......h.$..... │ │ 0x00235c40 681c0900 64030000 01000000 6c082400 h...d.......l.$. │ │ 0x00235c50 524f0900 681c0900 64030000 01000000 RO..h...d....... │ │ 0x00235c60 70082400 c34f0900 681c0900 64030000 p.$..O..h...d... │ │ - 0x00235c70 01000000 74082400 87be0800 681c0900 ....t.$.....h... │ │ - 0x00235c80 64030000 01000000 78082400 20870800 d.......x.$. ... │ │ + 0x00235c70 01000000 74082400 03d90800 681c0900 ....t.$.....h... │ │ + 0x00235c80 64030000 01000000 78082400 9ca10800 d.......x.$..... │ │ 0x00235c90 681c0900 64030000 01000000 7c082400 h...d.......|.$. │ │ - 0x00235ca0 6b930800 681c0900 17060000 01000000 k...h........... │ │ - 0x00235cb0 80082400 666c0800 681c0900 17060000 ..$.fl..h....... │ │ - 0x00235cc0 01000000 84082400 70b00800 681c0900 ......$.p...h... │ │ - 0x00235cd0 17060000 01000000 88082400 f8be0800 ..........$..... │ │ + 0x00235ca0 e7ad0800 681c0900 17060000 01000000 ....h........... │ │ + 0x00235cb0 80082400 e2860800 681c0900 17060000 ..$.....h....... │ │ + 0x00235cc0 01000000 84082400 ecca0800 681c0900 ......$.....h... │ │ + 0x00235cd0 17060000 01000000 88082400 74d90800 ..........$.t... │ │ 0x00235ce0 681c0900 17060000 01000000 8c082400 h.............$. │ │ 0x00235cf0 fd820900 681c0900 18060000 01000000 ....h........... │ │ 0x00235d00 90082400 a5000900 681c0900 19060000 ..$.....h....... │ │ 0x00235d10 01000000 94082400 79830900 681c0900 ......$.y...h... │ │ - 0x00235d20 1a060000 01000000 98082400 01cb0800 ..........$..... │ │ + 0x00235d20 1a060000 01000000 98082400 7de50800 ..........$.}... │ │ 0x00235d30 681c0900 8e060000 01000000 9c082400 h.............$. │ │ 0x00235d40 f8830900 681c0900 8e060000 01000000 ....h........... │ │ 0x00235d50 a0082400 39930900 681c0900 8e060000 ..$.9...h....... │ │ 0x00235d60 01000000 a4082400 b23f0800 681c0900 ......$..?..h... │ │ 0x00235d70 8e060000 01000000 a8082400 4e6a0900 ..........$.Nj.. │ │ 0x00235d80 681c0900 8e060000 01000000 ac082400 h.............$. │ │ 0x00235d90 9c140800 681c0900 8e060000 01000000 ....h........... │ │ 0x00235da0 b0082400 aaab0900 681c0900 8e060000 ..$.....h....... │ │ 0x00235db0 01000000 b4082400 c3a10900 681c0900 ......$.....h... │ │ - 0x00235dc0 22070000 01000000 b8082400 04790800 ".........$..y.. │ │ + 0x00235dc0 22070000 01000000 b8082400 80930800 ".........$..... │ │ 0x00235dd0 681c0900 22070000 01000000 bc082400 h...".........$. │ │ 0x00235de0 ba310800 681c0900 22070000 01000000 .1..h..."....... │ │ 0x00235df0 c0082400 c46a0900 681c0900 22070000 ..$..j..h..."... │ │ - 0x00235e00 01000000 c4082400 efb00800 681c0900 ......$.....h... │ │ - 0x00235e10 23070000 01000000 c8082400 aed70800 #.........$..... │ │ + 0x00235e00 01000000 c4082400 6bcb0800 681c0900 ......$.k...h... │ │ + 0x00235e10 23070000 01000000 c8082400 2af20800 #.........$.*... │ │ 0x00235e20 681c0900 24070000 01000000 cc082400 h...$.........$. │ │ 0x00235e30 84500800 681c0900 25070000 01000000 .P..h...%....... │ │ 0x00235e40 d0082400 18150800 681c0900 87070000 ..$.....h....... │ │ 0x00235e50 01000000 d4082400 d5b90900 681c0900 ......$.....h... │ │ 0x00235e60 87070000 01000000 d8082400 b95c0900 ..........$..\.. │ │ 0x00235e70 681c0900 87070000 01000000 dc082400 h.............$. │ │ 0x00235e80 ea050800 681c0900 87070000 01000000 ....h........... │ │ @@ -137,103 +137,103 @@ │ │ 0x00235eb0 87070000 01000000 e8082400 7e150800 ..........$.~... │ │ 0x00235ec0 681c0900 87070000 01000000 ec082400 h.............$. │ │ 0x00235ed0 0b510800 681c0900 1d020000 01000000 .Q..h........... │ │ 0x00235ee0 f0082400 1b010900 681c0900 1d020000 ..$.....h....... │ │ 0x00235ef0 01000000 f4082400 80010900 681c0900 ......$.....h... │ │ 0x00235f00 1d020000 01000000 f8082400 46a20900 ..........$.F... │ │ 0x00235f10 681c0900 1d020000 01000000 fc082400 h.............$. │ │ - 0x00235f20 e6930800 681c0900 1d020000 01000000 ....h........... │ │ + 0x00235f20 62ae0800 681c0900 1d020000 01000000 b...h........... │ │ 0x00235f30 00092400 471d0900 681c0900 1d020000 ..$.G...h....... │ │ 0x00235f40 01000000 04092400 3bba0900 681c0900 ......$.;...h... │ │ 0x00235f50 1d020000 01000000 08092400 30500900 ..........$.0P.. │ │ 0x00235f60 681c0900 1e020000 01000000 0c092400 h.............$. │ │ - 0x00235f70 e16c0800 681c0900 1e020000 01000000 .l..h........... │ │ + 0x00235f70 5d870800 681c0900 1e020000 01000000 ]...h........... │ │ 0x00235f80 10092400 225d0900 681c0900 1e020000 ..$."]..h....... │ │ 0x00235f90 01000000 14092400 ad1d0900 681c0900 ......$.....h... │ │ 0x00235fa0 1e020000 01000000 18092400 92210800 ..........$..!.. │ │ 0x00235fb0 681c0900 1e020000 01000000 1c092400 h.............$. │ │ - 0x00235fc0 46940800 681c0900 1e020000 01000000 F...h........... │ │ - 0x00235fd0 20092400 6db10800 681c0900 1e020000 .$.m...h....... │ │ + 0x00235fc0 c2ae0800 681c0900 1e020000 01000000 ....h........... │ │ + 0x00235fd0 20092400 e9cb0800 681c0900 1e020000 .$.....h....... │ │ 0x00235fe0 01000000 24092400 41320800 681c0900 ....$.$.A2..h... │ │ 0x00235ff0 20020000 01000000 28092400 bdc70900 .......(.$..... │ │ 0x00236000 681c0900 20020000 01000000 2c092400 h... .......,.$. │ │ 0x00236010 22c80900 681c0900 20020000 01000000 "...h... ....... │ │ 0x00236020 30092400 f2280900 681c0900 20020000 0.$..(..h... ... │ │ 0x00236030 01000000 34092400 58290900 681c0900 ....4.$.X)..h... │ │ - 0x00236040 20020000 01000000 38092400 74bf0800 .......8.$.t... │ │ + 0x00236040 20020000 01000000 38092400 f0d90800 .......8.$..... │ │ 0x00236050 681c0900 20020000 01000000 3c092400 h... .......<.$. │ │ - 0x00236060 466d0800 681c0900 20020000 01000000 Fm..h... ....... │ │ + 0x00236060 c2870800 681c0900 20020000 01000000 ....h... ....... │ │ 0x00236070 40092400 8bc80900 681c0900 21020000 @.$.....h...!... │ │ 0x00236080 01000000 44092400 51060800 681c0900 ....D.$.Q...h... │ │ 0x00236090 21020000 01000000 48092400 ae420900 !.......H.$..B.. │ │ 0x002360a0 681c0900 21020000 01000000 4c092400 h...!.......L.$. │ │ 0x002360b0 b8290900 681c0900 21020000 01000000 .)..h...!....... │ │ 0x002360c0 50092400 2e400800 681c0900 21020000 P.$..@..h...!... │ │ 0x002360d0 01000000 54092400 a6320800 681c0900 ....T.$..2..h... │ │ - 0x002360e0 21020000 01000000 58092400 af6d0800 !.......X.$..m.. │ │ + 0x002360e0 21020000 01000000 58092400 2b880800 !.......X.$.+... │ │ 0x002360f0 681c0900 21020000 01000000 5c092400 h...!.......\.$. │ │ 0x00236100 1e2a0900 681c0900 23020000 01000000 .*..h...#....... │ │ - 0x00236110 60092400 dabf0800 681c0900 23020000 `.$.....h...#... │ │ + 0x00236110 60092400 56da0800 681c0900 23020000 `.$.V...h...#... │ │ 0x00236120 01000000 64092400 70510800 681c0900 ....d.$.pQ..h... │ │ 0x00236130 23020000 01000000 68092400 8b5d0900 #.......h.$..].. │ │ 0x00236140 681c0900 23020000 01000000 6c092400 h...#.......l.$. │ │ 0x00236150 0c330800 681c0900 23020000 01000000 .3..h...#....... │ │ 0x00236160 70092400 dd510800 681c0900 23020000 p.$..Q..h...#... │ │ 0x00236170 01000000 74092400 b8930900 681c0900 ....t.$.....h... │ │ 0x00236180 23020000 01000000 78092400 f2210800 #.......x.$..!.. │ │ 0x00236190 681c0900 25020000 01000000 7c092400 h...%.......|.$. │ │ - 0x002361a0 186e0800 681c0900 26020000 01000000 .n..h...&....... │ │ + 0x002361a0 94880800 681c0900 26020000 01000000 ....h...&....... │ │ 0x002361b0 80092400 25940900 681c0900 27020000 ..$.%...h...'... │ │ 0x002361c0 01000000 84092400 e7150800 681c0900 ......$.....h... │ │ 0x002361d0 3b020000 01000000 88092400 4c160800 ;.........$.L... │ │ 0x002361e0 681c0900 64030000 01000000 8c092400 h...d.........$. │ │ - 0x002361f0 7ccb0800 681c0900 64030000 01000000 |...h...d....... │ │ - 0x00236200 90092400 87790800 681c0900 64030000 ..$..y..h...d... │ │ + 0x002361f0 f8e50800 681c0900 64030000 01000000 ....h...d....... │ │ + 0x00236200 90092400 03940800 681c0900 64030000 ..$.....h...d... │ │ 0x00236210 01000000 94092400 47520800 681c0900 ......$.GR..h... │ │ 0x00236220 64030000 01000000 98092400 131e0900 d.........$..... │ │ 0x00236230 681c0900 64030000 01000000 9c092400 h...d.........$. │ │ - 0x00236240 e1cb0800 681c0900 64030000 01000000 ....h...d....... │ │ + 0x00236240 5de60800 681c0900 64030000 01000000 ]...h...d....... │ │ 0x00236250 a0092400 95500900 681c0900 64030000 ..$..P..h...d... │ │ - 0x00236260 01000000 a4092400 7d6e0800 681c0900 ......$.}n..h... │ │ + 0x00236260 01000000 a4092400 f9880800 681c0900 ......$.....h... │ │ 0x00236270 17060000 01000000 a8092400 f0c80900 ..........$..... │ │ 0x00236280 681c0900 17060000 01000000 ac092400 h.............$. │ │ - 0x00236290 d6b10800 681c0900 17060000 01000000 ....h........... │ │ + 0x00236290 52cc0800 681c0900 17060000 01000000 R...h........... │ │ 0x002362a0 b0092400 aca20900 681c0900 17060000 ..$.....h....... │ │ 0x002362b0 01000000 b4092400 a4ba0900 681c0900 ......$.....h... │ │ 0x002362c0 18060000 01000000 b8092400 af370900 ..........$..7.. │ │ 0x002362d0 681c0900 19060000 01000000 bc092400 h.............$. │ │ 0x002362e0 70330800 681c0900 1a060000 01000000 p3..h........... │ │ 0x002362f0 c0092400 751e0900 681c0900 8e060000 ..$.u...h....... │ │ 0x00236300 01000000 c4092400 56220800 681c0900 ......$.V"..h... │ │ - 0x00236310 8e060000 01000000 c8092400 32d80800 ..........$.2... │ │ + 0x00236310 8e060000 01000000 c8092400 aef20800 ..........$..... │ │ 0x00236320 681c0900 8e060000 01000000 cc092400 h.............$. │ │ 0x00236330 bb770900 681c0900 8e060000 01000000 .w..h........... │ │ 0x00236340 d0092400 12a30900 681c0900 8e060000 ..$.....h....... │ │ 0x00236350 01000000 d4092400 a00d0900 681c0900 ......$.....h... │ │ - 0x00236360 8e060000 01000000 d8092400 3fb20800 ..........$.?... │ │ + 0x00236360 8e060000 01000000 d8092400 bbcc0800 ..........$..... │ │ 0x00236370 681c0900 8e060000 01000000 dc092400 h.............$. │ │ 0x00236380 73840900 681c0900 22070000 01000000 s...h..."....... │ │ - 0x00236390 e0092400 43c00800 681c0900 22070000 ..$.C...h..."... │ │ + 0x00236390 e0092400 bfda0800 681c0900 22070000 ..$.....h..."... │ │ 0x002363a0 01000000 e4092400 ad520800 681c0900 ......$..R..h... │ │ 0x002363b0 22070000 01000000 e8092400 55c90900 ".........$.U... │ │ 0x002363c0 681c0900 22070000 01000000 ec092400 h...".........$. │ │ 0x002363d0 b6060800 681c0900 23070000 01000000 ....h...#....... │ │ 0x002363e0 f0092400 0f380900 681c0900 24070000 ..$..8..h...$... │ │ - 0x002363f0 01000000 f4092400 ac940800 681c0900 ......$.....h... │ │ + 0x002363f0 01000000 f4092400 28af0800 681c0900 ......$.(...h... │ │ 0x00236400 25070000 01000000 f8092400 1e070800 %.........$..... │ │ 0x00236410 681c0900 87070000 01000000 fc092400 h.............$. │ │ 0x00236420 17430900 681c0900 87070000 01000000 .C..h........... │ │ 0x00236430 000a2400 e0840900 681c0900 87070000 ..$.....h....... │ │ 0x00236440 01000000 040a2400 85070800 681c0900 ......$.....h... │ │ 0x00236450 87070000 01000000 080a2400 872a0900 ..........$..*.. │ │ 0x00236460 681c0900 87070000 01000000 0c0a2400 h.............$. │ │ 0x00236470 29ac0900 681c0900 87070000 01000000 )...h........... │ │ - 0x00236480 100a2400 9bd80800 681c0900 87070000 ..$.....h....... │ │ - 0x00236490 01000000 86390900 86390900 1d950800 .....9...9...... │ │ - 0x002364a0 1d950800 2fca0900 8b390900 2fca0900 ..../....9../... │ │ + 0x00236480 100a2400 17f30800 681c0900 87070000 ..$.....h....... │ │ + 0x00236490 01000000 86390900 86390900 99af0800 .....9...9...... │ │ + 0x002364a0 99af0800 2fca0900 8b390900 2fca0900 ..../....9../... │ │ 0x002364b0 13230800 40000000 00000000 00000000 .#..@........... │ │ 0x002364c0 5d2a0c00 412b0c00 38000000 f8ffffff ]*..A+..8....... │ │ 0x002364d0 00000000 b92b0c00 292c0c00 c0ffffff .....+..),...... │ │ 0x002364e0 c0ffffff 00000000 a12c0c00 192d0c00 .........,...-.. │ │ 0x002364f0 0c000000 0c000000 0c000000 20000000 ............ ... │ │ 0x00236500 0c000000 20000000 34000000 20000000 .... ...4... ... │ │ 0x00236510 34000000 20000000 40000000 00000000 4... ...@....... │ │ @@ -262,28 +262,28 @@ │ │ 0x00236680 38000000 00000000 00000000 05530c00 8............S.. │ │ 0x00236690 f1670c00 c8ffffff c8ffffff 00000000 .g.............. │ │ 0x002366a0 81670c00 61680c00 0c000000 0c000000 .g..ah.......... │ │ 0x002366b0 20000000 20000000 38000000 00000000 ... ...8....... │ │ 0x002366c0 00000000 00000000 00000000 c8ffffff ................ │ │ 0x002366d0 c8ffffff 00000000 00000000 00000000 ................ │ │ 0x002366e0 08000000 00000000 00000000 300a2400 ............0.$. │ │ - 0x002366f0 f7390900 7c880800 61000000 01000000 .9..|...a....... │ │ - 0x00236700 340a2400 586c0900 7c880800 13010000 4.$.Xl..|....... │ │ - 0x00236710 01000000 380a2400 3a790900 7c880800 ....8.$.:y..|... │ │ + 0x002366f0 f7390900 f8a20800 61000000 01000000 .9......a....... │ │ + 0x00236700 340a2400 586c0900 f8a20800 13010000 4.$.Xl.......... │ │ + 0x00236710 01000000 380a2400 3a790900 f8a20800 ....8.$.:y...... │ │ 0x00236720 34010000 01000000 3c0a2400 97790900 4.......<.$..y.. │ │ - 0x00236730 7c880800 a6010000 01000000 400a2400 |...........@.$. │ │ - 0x00236740 cd790900 7c880800 c2010000 01000000 .y..|........... │ │ + 0x00236730 f8a20800 a6010000 01000000 400a2400 ............@.$. │ │ + 0x00236740 cd790900 f8a20800 c2010000 01000000 .y.............. │ │ 0x00236750 7d840c00 7d840c00 9f850c00 9f850c00 }...}........... │ │ 0x00236760 bf860c00 bf860c00 f1870c00 00000000 ................ │ │ 0x00236770 2a230800 2c090800 85ad0900 725e0800 *#..,.......r^.. │ │ - 0x00236780 e1950800 5e2b0900 54ca0900 120f0900 ....^+..T....... │ │ - 0x00236790 1cbc0900 2a7b0800 20bc0900 de020900 ....*{.. ....... │ │ - 0x002367a0 6f6f0800 57cd0800 b06c0900 b26c0900 oo..W....l...l.. │ │ + 0x00236780 5db00800 5e2b0900 54ca0900 120f0900 ]...^+..T....... │ │ + 0x00236790 1cbc0900 a6950800 20bc0900 de020900 ........ ....... │ │ + 0x002367a0 eb890800 d3e70800 b06c0900 b26c0900 .........l...l.. │ │ 0x002367b0 9b170800 5bca0900 a4170800 c16c0900 ....[........l.. │ │ - 0x002367c0 30230800 76c10800 3c000000 00000000 0#..v...<....... │ │ + 0x002367c0 30230800 f2db0800 3c000000 00000000 0#......<....... │ │ 0x002367d0 00000000 f9e50c00 65e60c00 c4ffffff ........e....... │ │ 0x002367e0 c4ffffff 00000000 d5e60c00 45e70c00 ............E... │ │ 0x002367f0 0c000000 0c000000 20000000 20000000 ........ ... ... │ │ 0x00236800 3c000000 00000000 00000000 00000000 <............... │ │ 0x00236810 00000000 c4ffffff c4ffffff 00000000 ................ │ │ 0x00236820 00000000 00000000 08000000 00000000 ................ │ │ 0x00236830 00000000 41bc0900 45bc0900 257a0900 ....A...E...%z.. │ │ @@ -299,15 +299,15 @@ │ │ 0x002368d0 00000000 00000000 08000000 95e20900 ................ │ │ 0x002368e0 00000000 00000000 00692300 dd2e0d00 .........i#..... │ │ 0x002368f0 ed2e0d00 092f0d00 00000000 832f0d00 ...../......./.. │ │ 0x00236900 08000000 dde20900 00000000 540a2400 ............T.$. │ │ 0x00236910 b65e0800 92410800 28000000 01000000 .^...A..(....... │ │ 0x00236920 580a2400 fd5e0800 92410800 3d000000 X.$..^...A..=... │ │ 0x00236930 01000000 5c0a2400 ba170800 92410800 ....\.$......A.. │ │ - 0x00236940 52000000 01000000 600a2400 83c10800 R.......`.$..... │ │ + 0x00236940 52000000 01000000 600a2400 ffdb0800 R.......`.$..... │ │ 0x00236950 92410800 5a000000 01000000 892f0d00 .A..Z......../.. │ │ 0x00236960 01300d00 cd300d00 bd310d00 c5320d00 .0...0...1...2.. │ │ 0x00236970 bd330d00 55340d00 ed340d00 91350d00 .3..U4...4...5.. │ │ 0x00236980 892f0d00 61360d00 51370d00 45380d00 ./..a6..Q7..E8.. │ │ 0x00236990 3d390d00 d5390d00 6d3a0d00 113b0d00 =9...9..m:...;.. │ │ 0x002369a0 013c0d00 ed3c0d00 653d0d00 5d3e0d00 .<...<..e=..]>.. │ │ 0x002369b0 2d3f0d00 cd3f0d00 6d400d00 1d410d00 -?...?..m@...A.. │ │ @@ -327,87 +327,87 @@ │ │ 0x00236a90 1c000000 01000000 700a2400 47340800 ........p.$.G4.. │ │ 0x00236aa0 78ca0900 22000000 01000000 740a2400 x...".......t.$. │ │ 0x00236ab0 cb6c0900 78ca0900 8b000000 01000000 .l..x........... │ │ 0x00236ac0 780a2400 b55e0900 78ca0900 b0000000 x.$..^..x....... │ │ 0x00236ad0 01000000 7c0a2400 d7940900 78ca0900 ....|.$.....x... │ │ 0x00236ae0 e7000000 01000000 800a2400 86850900 ..........$..... │ │ 0x00236af0 92410800 0a010000 01000000 840a2400 .A............$. │ │ - 0x00236b00 79cd0800 92410800 c3000000 01000000 y....A.......... │ │ - 0x00236b10 880a2400 06960800 92410800 cd000000 ..$......A...... │ │ - 0x00236b20 01000000 8c0a2400 53b30800 92410800 ......$.S....A.. │ │ - 0x00236b30 d7000000 01000000 900a2400 e5cd0800 ..........$..... │ │ + 0x00236b00 f5e70800 92410800 c3000000 01000000 .....A.......... │ │ + 0x00236b10 880a2400 82b00800 92410800 cd000000 ..$......A...... │ │ + 0x00236b20 01000000 8c0a2400 cfcd0800 92410800 ......$......A.. │ │ + 0x00236b30 d7000000 01000000 900a2400 61e80800 ..........$.a... │ │ 0x00236b40 92410800 e1000000 01000000 940a2400 .A............$. │ │ 0x00236b50 6c3a0900 92410800 eb000000 01000000 l:...A.......... │ │ 0x00236b60 980a2400 20540800 92410800 f5000000 ..$. T...A...... │ │ 0x00236b70 01000000 9c0a2400 a4ad0900 92410800 ......$......A.. │ │ 0x00236b80 ff000000 01000000 a00a2400 d7510900 ..........$..Q.. │ │ 0x00236b90 92410800 b9000000 01000000 a40a2400 .A............$. │ │ 0x00236ba0 8d540800 92410800 ce000000 01000000 .T...A.......... │ │ - 0x00236bb0 a80a2400 c37b0800 92410800 d8000000 ..$..{...A...... │ │ - 0x00236bc0 01000000 ac0a2400 73960800 92410800 ......$.s....A.. │ │ + 0x00236bb0 a80a2400 3f960800 92410800 d8000000 ..$.?....A...... │ │ + 0x00236bc0 01000000 ac0a2400 efb00800 92410800 ......$......A.. │ │ 0x00236bd0 e2000000 01000000 b00a2400 11ae0900 ..........$..... │ │ 0x00236be0 92410800 ec000000 01000000 b40a2400 .A............$. │ │ 0x00236bf0 445f0800 92410800 f6000000 01000000 D_...A.......... │ │ 0x00236c00 b80a2400 01180800 92410800 00010000 ..$......A...... │ │ - 0x00236c10 01000000 bc0a2400 0a890800 92410800 ......$......A.. │ │ + 0x00236c10 01000000 bc0a2400 86a30800 92410800 ......$......A.. │ │ 0x00236c20 ba000000 01000000 c00a2400 7eae0900 ..........$.~... │ │ 0x00236c30 92410800 c4000000 01000000 c40a2400 .A............$. │ │ 0x00236c40 f2020900 92410800 0d010000 01000000 .....A.......... │ │ 0x00236c50 c80a2400 752b0900 92410800 d9000000 ..$.u+...A...... │ │ 0x00236c60 01000000 cc0a2400 05200900 92410800 ......$.. ...A.. │ │ - 0x00236c70 e3000000 01000000 d00a2400 e0960800 ..........$..... │ │ + 0x00236c70 e3000000 01000000 d00a2400 5cb10800 ..........$.\... │ │ 0x00236c80 92410800 ed000000 01000000 d40a2400 .A............$. │ │ - 0x00236c90 74da0800 92410800 f7000000 01000000 t....A.......... │ │ + 0x00236c90 f0f40800 92410800 f7000000 01000000 .....A.......... │ │ 0x00236ca0 d80a2400 f6ca0900 92410800 01010000 ..$......A...... │ │ 0x00236cb0 01000000 dc0a2400 f55e0900 92410800 ......$..^...A.. │ │ - 0x00236cc0 bb000000 01000000 e00a2400 77890800 ..........$.w... │ │ + 0x00236cc0 bb000000 01000000 e00a2400 f3a30800 ..........$..... │ │ 0x00236cd0 92410800 c5000000 01000000 e40a2400 .A............$. │ │ - 0x00236ce0 4e970800 92410800 cf000000 01000000 N....A.......... │ │ + 0x00236ce0 cab10800 92410800 cf000000 01000000 .....A.......... │ │ 0x00236cf0 e80a2400 85440900 92410800 e4000000 ..$..D...A...... │ │ - 0x00236d00 01000000 ec0a2400 bc970800 92410800 ......$......A.. │ │ - 0x00236d10 ee000000 01000000 f00a2400 2a980800 ..........$.*... │ │ + 0x00236d00 01000000 ec0a2400 38b20800 92410800 ......$.8....A.. │ │ + 0x00236d10 ee000000 01000000 f00a2400 a6b20800 ..........$..... │ │ 0x00236d20 92410800 f8000000 01000000 f40a2400 .A............$. │ │ 0x00236d30 ebae0900 92410800 02010000 01000000 .....A.......... │ │ 0x00236d40 f80a2400 ff6c0900 92410800 bc000000 ..$..l...A...... │ │ 0x00236d50 01000000 fc0a2400 82340800 92410800 ......$..4...A.. │ │ 0x00236d60 c6000000 01000000 000b2400 6c6d0900 ..........$.lm.. │ │ 0x00236d70 92410800 d0000000 01000000 040b2400 .A............$. │ │ 0x00236d80 59af0900 92410800 da000000 01000000 Y....A.......... │ │ 0x00236d90 080b2400 43520900 92410800 10010000 ..$.CR...A...... │ │ 0x00236da0 01000000 0c0b2400 45420800 92410800 ......$.EB...A.. │ │ 0x00236db0 ef000000 01000000 100b2400 b3420800 ..........$..B.. │ │ 0x00236dc0 92410800 f9000000 01000000 140b2400 .A............$. │ │ - 0x00236dd0 4fa30800 92410800 03010000 01000000 O....A.......... │ │ + 0x00236dd0 cbbd0800 92410800 03010000 01000000 .....A.......... │ │ 0x00236de0 180b2400 63230800 92410800 bd000000 ..$.c#...A...... │ │ 0x00236df0 01000000 1c0b2400 f0850900 92410800 ......$......A.. │ │ 0x00236e00 c7000000 01000000 200b2400 fa540800 ........ .$..T.. │ │ 0x00236e10 92410800 d1000000 01000000 240b2400 .A..........$.$. │ │ 0x00236e20 5d030900 92410800 db000000 01000000 ]....A.......... │ │ 0x00236e30 280b2400 d0230800 92410800 e5000000 (.$..#...A...... │ │ 0x00236e40 01000000 2c0b2400 b15f0800 92410800 ....,.$.._...A.. │ │ - 0x00236e50 fa000000 01000000 300b2400 52ce0800 ........0.$.R... │ │ + 0x00236e50 fa000000 01000000 300b2400 cee80800 ........0.$..... │ │ 0x00236e60 92410800 04010000 01000000 340b2400 .A..........4.$. │ │ 0x00236e70 625f0900 92410800 be000000 01000000 b_...A.......... │ │ - 0x00236e80 380b2400 e2da0800 92410800 c8000000 8.$......A...... │ │ - 0x00236e90 01000000 3c0b2400 307c0800 92410800 ....<.$.0|...A.. │ │ + 0x00236e80 380b2400 5ef50800 92410800 c8000000 8.$.^....A...... │ │ + 0x00236e90 01000000 3c0b2400 ac960800 92410800 ....<.$......A.. │ │ 0x00236ea0 d2000000 01000000 400b2400 ef340800 ........@.$..4.. │ │ 0x00236eb0 92410800 dc000000 01000000 440b2400 .A..........D.$. │ │ - 0x00236ec0 d6c10800 92410800 e6000000 01000000 .....A.......... │ │ + 0x00236ec0 52dc0800 92410800 e6000000 01000000 R....A.......... │ │ 0x00236ed0 480b2400 cb030900 92410800 f0000000 H.$......A...... │ │ 0x00236ee0 01000000 4c0b2400 cd0f0900 92410800 ....L.$......A.. │ │ - 0x00236ef0 13010000 01000000 500b2400 bda30800 ........P.$..... │ │ + 0x00236ef0 13010000 01000000 500b2400 39be0800 ........P.$.9... │ │ 0x00236f00 92410800 05010000 01000000 540b2400 .A..........T.$. │ │ 0x00236f10 1f600800 92410800 bf000000 01000000 .`...A.......... │ │ 0x00236f20 580b2400 64cb0900 92410800 c9000000 X.$.d....A...... │ │ 0x00236f30 01000000 5c0b2400 d93a0900 92410800 ....\.$..:...A.. │ │ 0x00236f40 d3000000 01000000 600b2400 38100900 ........`.$.8... │ │ 0x00236f50 92410800 dd000000 01000000 640b2400 .A..........d.$. │ │ - 0x00236f60 9e7c0800 92410800 e7000000 01000000 .|...A.......... │ │ + 0x00236f60 1a970800 92410800 e7000000 01000000 .....A.......... │ │ 0x00236f70 680b2400 b9a40900 92410800 f1000000 h.$......A...... │ │ - 0x00236f80 01000000 6c0b2400 4fdb0800 92410800 ....l.$.O....A.. │ │ + 0x00236f80 01000000 6c0b2400 cbf50800 92410800 ....l.$......A.. │ │ 0x00236f90 fb000000 01000000 057e0d00 6d7e0d00 .........~..m~.. │ │ 0x00236fa0 d57e0d00 437f0d00 b17f0d00 1f800d00 .~..C........... │ │ 0x00236fb0 89800d00 00000000 fb800d00 5f810d00 ............_... │ │ 0x00236fc0 c3810d00 2d820d00 97820d00 01830d00 ....-........... │ │ 0x00236fd0 67830d00 d5830d00 55840d00 b9840d00 g.......U....... │ │ 0x00236fe0 1d850d00 87850d00 f1850d00 5b860d00 ............[... │ │ 0x00236ff0 c1860d00 2f870d00 af870d00 1b880d00 ..../........... │ │ @@ -425,38 +425,38 @@ │ │ 0x002370b0 e39b0d00 5f9c0d00 700b2400 42950900 ...._...p.$.B... │ │ 0x002370c0 94600800 18000000 01000000 740b2400 .`..........t.$. │ │ 0x002370d0 d9af0900 94600800 59000000 01000000 .....`..Y....... │ │ 0x002370e0 780b2400 39040900 94600800 11000000 x.$.9....`...... │ │ 0x002370f0 01000000 7c0b2400 76090800 cf5f0900 ....|.$.v...._.. │ │ 0x00237100 44000000 01000000 800b2400 4abc0900 D.........$.J... │ │ 0x00237110 cf5f0900 33010000 01000000 4abc0900 ._..3.......J... │ │ - 0x00237120 cf5f0900 66010000 05000000 1d950800 ._..f........... │ │ + 0x00237120 cf5f0900 66010000 05000000 99af0800 ._..f........... │ │ 0x00237130 58600900 bb220800 840b2400 68550800 X`..."....$.hU.. │ │ 0x00237140 cf5f0900 ac010000 01000000 880b2400 ._............$. │ │ 0x00237150 60040900 cf5f0900 fc010000 01000000 `...._.......... │ │ 0x00237160 8c0b2400 18610800 cf5f0900 6a020000 ..$..a..._..j... │ │ - 0x00237170 01000000 900b2400 98980800 cf5f0900 ......$......_.. │ │ + 0x00237170 01000000 900b2400 14b30800 cf5f0900 ......$......_.. │ │ 0x00237180 b8020000 01000000 940b2400 dc520900 ..........$..R.. │ │ 0x00237190 cf5f0900 00040000 01000000 55cd0d00 ._..........U... │ │ 0x002371a0 55cd0d00 d3cd0d00 d3cd0d00 3fce0d00 U...........?... │ │ 0x002371b0 9fce0d00 05cf0d00 00000000 980b2400 ..............$. │ │ 0x002371c0 c5860900 e96d0900 79000000 01000000 .....m..y....... │ │ - 0x002371d0 9c0b2400 398a0800 e96d0900 11000000 ..$.9....m...... │ │ + 0x002371d0 9c0b2400 b5a40800 e96d0900 11000000 ..$......m...... │ │ 0x002371e0 01000000 00000000 00722300 5d750e00 .........r#.]u.. │ │ 0x002371f0 6d750e00 89750e00 00000000 d9750e00 mu...u.......u.. │ │ 0x00237200 08000000 f0e30900 00000000 00000000 ................ │ │ 0x00237210 5c722300 dd750e00 29760e00 dd910a00 \r#..u..)v...... │ │ 0x00237220 df910a00 e1910a00 e3910a00 00000000 ................ │ │ 0x00237230 00000000 7d760e00 9d760e00 f3760e00 ....}v...v...v.. │ │ 0x00237240 01770e00 95770e00 a9790e00 b1790e00 .w...w...y...y.. │ │ 0x00237250 08000000 00000000 00000000 08000000 ................ │ │ 0x00237260 40e40900 00000000 a00b2400 06460900 @.........$..F.. │ │ 0x00237270 376f0900 a00d0000 01000000 a40b2400 7o............$. │ │ 0x00237280 6b0a0800 376f0900 d20d0000 01000000 k...7o.......... │ │ - 0x00237290 a80b2400 bf8a0800 376f0900 770e0000 ..$.....7o..w... │ │ + 0x00237290 a80b2400 3ba50800 376f0900 770e0000 ..$.;...7o..w... │ │ 0x002372a0 01000000 ac0b2400 80bd0900 376f0900 ......$.....7o.. │ │ 0x002372b0 3a110000 01000000 b00b2400 36460900 :.........$.6F.. │ │ 0x002372c0 376f0900 52110000 01000000 08000000 7o..R........... │ │ 0x002372d0 00000000 00000000 e8722300 19b80e00 .........r#..... │ │ 0x002372e0 25b80e00 6bb80e00 08000000 4cfe0900 %...k.......L... │ │ 0x002372f0 00000000 08000000 00000000 00000000 ................ │ │ 0x00237300 10732300 fdf10e00 2bf30e00 1ff40e00 .s#.....+....... │ │ @@ -467,182 +467,182 @@ │ │ 0x00237350 a9100f00 b9100f00 01110f00 19110f00 ................ │ │ 0x00237360 08000000 a0020a00 00000000 00000000 ................ │ │ 0x00237370 88732300 00000000 1d110f00 2d110f00 .s#.........-... │ │ 0x00237380 45110f00 5d110f00 08000000 95030a00 E...]........... │ │ 0x00237390 00000000 00000000 b0732300 00000000 .........s#..... │ │ 0x002373a0 61110f00 71110f00 b9110f00 d1110f00 a...q........... │ │ 0x002373b0 08000000 80040a00 00000000 b40b2400 ..............$. │ │ - 0x002373c0 14cd0900 b8b40800 b5000000 01000000 ................ │ │ - 0x002373d0 b80b2400 6b620800 b8b40800 1f010000 ..$.kb.......... │ │ + 0x002373c0 14cd0900 34cf0800 b5000000 01000000 ....4........... │ │ + 0x002373d0 b80b2400 6b620800 34cf0800 1f010000 ..$.kb..4....... │ │ 0x002373e0 01000000 75180f00 75180f00 9d180f00 ....u...u....... │ │ 0x002373f0 9d180f00 c5180f00 ed180f00 1f190f00 ................ │ │ 0x00237400 00000000 bc0b2400 c0880900 9e620800 ......$......b.. │ │ 0x00237410 3e000000 01000000 c00b2400 52960900 >.........$.R... │ │ 0x00237420 9e620800 11000000 01000000 c80b2400 .b............$. │ │ 0x00237430 fa7a0900 67440800 e9000000 01000000 .z..gD.......... │ │ 0x00237440 fa7a0900 67440800 f3000000 05000000 .z..gD.......... │ │ - 0x00237450 88990800 33610900 19110900 cc0b2400 ....3a........$. │ │ + 0x00237450 04b40800 33610900 19110900 cc0b2400 ....3a........$. │ │ 0x00237460 547b0900 67440800 62000000 01000000 T{..gD..b....... │ │ 0x00237470 00000000 84742300 00000000 8d2d0f00 .....t#......-.. │ │ 0x00237480 9d2d0f00 08000000 6d050a00 00000000 .-......m....... │ │ 0x00237490 d00b2400 46110900 67440800 47000000 ..$.F...gD..G... │ │ 0x002374a0 01000000 00000000 b8742300 00000000 .........t#..... │ │ 0x002374b0 512e0f00 612e0f00 08000000 8d050a00 Q...a........... │ │ 0x002374c0 00000000 d40b2400 e0880900 67440800 ......$.....gD.. │ │ 0x002374d0 b3000000 01000000 00000000 ec742300 .............t#. │ │ 0x002374e0 00000000 152f0f00 312f0f00 08000000 ...../..1/...... │ │ - 0x002374f0 b1050a00 00000000 d80b2400 d7700800 ..........$..p.. │ │ + 0x002374f0 b1050a00 00000000 d80b2400 538b0800 ..........$.S... │ │ 0x00237500 67440800 b3000000 01000000 dc0b2400 gD............$. │ │ 0x00237510 db440800 12450800 46000000 01000000 .D...E..F....... │ │ 0x00237520 e00b2400 86450800 12450800 4d000000 ..$..E...E..M... │ │ 0x00237530 01000000 e40b2400 35610900 12450800 ......$.5a...E.. │ │ - 0x00237540 54000000 01000000 e80b2400 b3990800 T.........$..... │ │ + 0x00237540 54000000 01000000 e80b2400 2fb40800 T.........$./... │ │ 0x00237550 12450800 5b000000 01000000 ec0b2400 .E..[.........$. │ │ - 0x00237560 3e710800 12450800 cd020000 01000000 >q...E.......... │ │ + 0x00237560 ba8b0800 12450800 cd020000 01000000 .....E.......... │ │ 0x00237570 f00b2400 947b0900 12450800 1b030000 ..$..{...E...... │ │ 0x00237580 01000000 f40b2400 73610900 12450800 ......$.sa...E.. │ │ 0x00237590 0a040000 01000000 73610900 12450800 ........sa...E.. │ │ 0x002375a0 16040000 00000000 4e1a0800 90540900 ........N....T.. │ │ 0x002375b0 bf450800 f80b2400 e1240800 12450800 .E....$..$...E.. │ │ 0x002375c0 35050000 01000000 fc0b2400 37460800 5.........$.7F.. │ │ 0x002375d0 12450800 ca050000 01000000 000c2400 .E............$. │ │ 0x002375e0 602c0900 12450800 d1050000 01000000 `,...E.......... │ │ 0x002375f0 040c2400 97540900 12450800 03060000 ..$..T...E...... │ │ - 0x00237600 01000000 080c2400 98710800 12450800 ......$..q...E.. │ │ + 0x00237600 01000000 080c2400 148c0800 12450800 ......$......E.. │ │ 0x00237610 0a060000 01000000 0c0c2400 e06f0900 ..........$..o.. │ │ - 0x00237620 2ab50800 be030000 01000000 100c2400 *.............$. │ │ - 0x00237630 ff460900 2ab50800 98030000 01000000 .F..*........... │ │ - 0x00237640 b6b50800 1b970900 67000000 00000000 ........g....... │ │ - 0x00237650 1d950800 c2460800 b3560800 440c2400 .....F...V..D.$. │ │ + 0x00237620 a6cf0800 be030000 01000000 100c2400 ..............$. │ │ + 0x00237630 ff460900 a6cf0800 98030000 01000000 .F.............. │ │ + 0x00237640 32d00800 1b970900 67000000 00000000 2.......g....... │ │ + 0x00237650 99af0800 c2460800 b3560800 440c2400 .....F...V..D.$. │ │ 0x00237660 91970900 e6610900 69010000 01000000 .....a..i....... │ │ 0x00237670 edff0f00 59001000 c5001000 27011000 ....Y.......'... │ │ 0x00237680 89011000 eb011000 55021000 00000000 ........U....... │ │ 0x00237690 00000000 a4762300 00000000 ddff0f00 .....v#......... │ │ 0x002376a0 e1fe0f00 08000000 d5050a00 00000000 ................ │ │ 0x002376b0 480c2400 cc460800 e6460800 6a000000 H.$..F...F..j... │ │ - 0x002376c0 01000000 4c0c2400 519a0800 e6460800 ....L.$.Q....F.. │ │ - 0x002376d0 95000000 01000000 500c2400 21de0800 ........P.$.!... │ │ + 0x002376c0 01000000 4c0c2400 cdb40800 e6460800 ....L.$......F.. │ │ + 0x002376d0 95000000 01000000 500c2400 9df80800 ........P.$..... │ │ 0x002376e0 e6460800 b9000000 01000000 540c2400 .F..........T.$. │ │ 0x002376f0 4bcd0900 e6460800 0f010000 01000000 K....F.......... │ │ - 0x00237700 580c2400 797e0800 e6460800 38020000 X.$.y~...F..8... │ │ + 0x00237700 580c2400 f5980800 e6460800 38020000 X.$......F..8... │ │ 0x00237710 01000000 5c0c2400 440b0800 e6460800 ....\.$.D....F.. │ │ - 0x00237720 a0020000 01000000 600c2400 899a0800 ........`.$..... │ │ + 0x00237720 a0020000 01000000 600c2400 05b50800 ........`.$..... │ │ 0x00237730 e6460800 c1020000 01000000 640c2400 .F..........d.$. │ │ 0x00237740 5b050900 e6460800 c2040000 01000000 [....F.......... │ │ 0x00237750 a1491000 954a1000 ad4b1000 ad4c1000 .I...J...K...L.. │ │ 0x00237760 cd4d1000 d94e1000 634f1000 00000000 .M...N..cO...... │ │ 0x00237770 680c2400 6a0b0800 e6460800 60050000 h.$.j....F..`... │ │ 0x00237780 01000000 6c0c2400 ef110900 e6460800 ....l.$......F.. │ │ - 0x00237790 b7050000 01000000 700c2400 1fa60800 ........p.$..... │ │ + 0x00237790 b7050000 01000000 700c2400 9bc00800 ........p.$..... │ │ 0x002377a0 e6460800 42060000 01000000 740c2400 .F..B.......t.$. │ │ 0x002377b0 fb560800 e6460800 e8060000 01000000 .V...F.......... │ │ 0x002377c0 780c2400 6b470800 e6460800 7b070000 x.$.kG...F..{... │ │ 0x002377d0 01000000 c4152400 b5b00900 6b250800 ......$.....k%.. │ │ 0x002377e0 a3000000 01000000 c8152400 c60b0800 ..........$..... │ │ 0x002377f0 6b250800 a9000000 01000000 cc152400 k%............$. │ │ 0x00237800 87370800 6b250800 c4000000 01000000 .7..k%.......... │ │ 0x00237810 d0152400 0fb10900 6b250800 e5000000 ..$.....k%...... │ │ - 0x00237820 01000000 d4152400 eec30800 6b250800 ......$.....k%.. │ │ + 0x00237820 01000000 d4152400 6ade0800 6b250800 ......$.j...k%.. │ │ 0x00237830 07010000 01000000 d8152400 c5890900 ..........$..... │ │ 0x00237840 6b250800 24010000 01000000 dc152400 k%..$.........$. │ │ - 0x00237850 f9710800 6b250800 3f010000 01000000 .q..k%..?....... │ │ + 0x00237850 758c0800 6b250800 3f010000 01000000 u...k%..?....... │ │ 0x00237860 e0152400 9a2d0900 6b250800 5c010000 ..$..-..k%..\... │ │ 0x00237870 01000000 e4152400 9e470800 6b250800 ......$..G..k%.. │ │ 0x00237880 b6010000 01000000 e8152400 de470800 ..........$..G.. │ │ 0x00237890 6b250800 27020000 01000000 ec152400 k%..'.........$. │ │ 0x002378a0 71a60900 6b250800 ad020000 01000000 q...k%.......... │ │ 0x002378b0 f0152400 ebcd0900 6b250800 f4020000 ..$.....k%...... │ │ - 0x002378c0 01000000 f4152400 230c0800 f3b50800 ......$.#....... │ │ + 0x002378c0 01000000 f4152400 230c0800 6fd00800 ......$.#...o... │ │ 0x002378d0 10000000 01000000 f8152400 94630800 ..........$..c.. │ │ - 0x002378e0 f3b50800 1a000000 01000000 fc152400 ..............$. │ │ - 0x002378f0 3e470900 f3b50800 25000000 01000000 >G......%....... │ │ - 0x00237900 00162400 768b0800 f3b50800 2c000000 ..$.v.......,... │ │ - 0x00237910 01000000 04162400 b2550900 f3b50800 ......$..U...... │ │ + 0x002378e0 6fd00800 1a000000 01000000 fc152400 o.............$. │ │ + 0x002378f0 3e470900 6fd00800 25000000 01000000 >G..o...%....... │ │ + 0x00237900 00162400 f2a50800 6fd00800 2c000000 ..$.....o...,... │ │ + 0x00237910 01000000 04162400 b2550900 6fd00800 ......$..U..o... │ │ 0x00237920 38000000 01000000 08162400 0b8a0900 8.........$..... │ │ - 0x00237930 f3b50800 45000000 01000000 0c162400 ....E.........$. │ │ - 0x00237940 418a0900 f3b50800 51000000 01000000 A.......Q....... │ │ - 0x00237950 10162400 e3630800 f3b50800 5d000000 ..$..c......]... │ │ - 0x00237960 01000000 14162400 3a720800 f3b50800 ......$.:r...... │ │ - 0x00237970 68000000 01000000 18162400 6f720800 h.........$.or.. │ │ - 0x00237980 f3b50800 72000000 01000000 1c162400 ....r.........$. │ │ - 0x00237990 bd9a0800 f3b50800 7d000000 01000000 ........}....... │ │ - 0x002379a0 20162400 2e120900 f3b50800 88000000 .$............. │ │ - 0x002379b0 01000000 24162400 60120900 f3b50800 ....$.$.`....... │ │ + 0x00237930 6fd00800 45000000 01000000 0c162400 o...E.........$. │ │ + 0x00237940 418a0900 6fd00800 51000000 01000000 A...o...Q....... │ │ + 0x00237950 10162400 e3630800 6fd00800 5d000000 ..$..c..o...]... │ │ + 0x00237960 01000000 14162400 b68c0800 6fd00800 ......$.....o... │ │ + 0x00237970 68000000 01000000 18162400 eb8c0800 h.........$..... │ │ + 0x00237980 6fd00800 72000000 01000000 1c162400 o...r.........$. │ │ + 0x00237990 39b50800 6fd00800 7d000000 01000000 9...o...}....... │ │ + 0x002379a0 20162400 2e120900 6fd00800 88000000 .$.....o....... │ │ + 0x002379b0 01000000 24162400 60120900 6fd00800 ....$.$.`...o... │ │ 0x002379c0 93000000 01000000 28162400 94120900 ........(.$..... │ │ - 0x002379d0 a1720800 4d050000 01000000 2c162400 .r..M.......,.$. │ │ - 0x002379e0 63a60800 a1720800 55050000 01000000 c....r..U....... │ │ - 0x002379f0 30162400 1a730800 a1720800 5d050000 0.$..s...r..]... │ │ - 0x00237a00 01000000 34162400 ea7b0900 a1720800 ....4.$..{...r.. │ │ + 0x002379d0 1d8d0800 4d050000 01000000 2c162400 ....M.......,.$. │ │ + 0x002379e0 dfc00800 1d8d0800 55050000 01000000 ........U....... │ │ + 0x002379f0 30162400 968d0800 1d8d0800 5d050000 0.$.........]... │ │ + 0x00237a00 01000000 34162400 ea7b0900 1d8d0800 ....4.$..{...... │ │ 0x00237a10 65050000 01000000 3d671000 d76a1000 e.......=g...j.. │ │ 0x00237a20 7d6e1000 47721000 1b761000 31791000 }n..Gr...v..1y.. │ │ 0x00237a30 257c1000 00000000 a17e1000 b3801000 %|.......~...... │ │ 0x00237a40 d1821000 1d851000 71871000 77891000 ........q...w... │ │ 0x00237a50 238b1000 00000000 38162400 dd2d0900 #.......8.$..-.. │ │ 0x00237a60 20480800 1c010000 01000000 3c162400 H..........<.$. │ │ 0x00237a70 f4370800 20480800 2a010000 01000000 .7.. H..*....... │ │ 0x00237a80 40162400 6b2e0900 20480800 38010000 @.$.k... H..8... │ │ - 0x00237a90 01000000 44162400 92de0800 20480800 ....D.$..... H.. │ │ + 0x00237a90 01000000 44162400 0ef90800 20480800 ....D.$..... H.. │ │ 0x00237aa0 46010000 01000000 48162400 bf260800 F.......H.$..&.. │ │ 0x00237ab0 20480800 c6010000 01000000 4c162400 H..........L.$. │ │ - 0x00237ac0 cc7e0800 20480800 22020000 01000000 .~.. H.."....... │ │ + 0x00237ac0 48990800 20480800 22020000 01000000 H... H.."....... │ │ 0x00237ad0 50162400 74620900 20480800 82020000 P.$.tb.. H...... │ │ 0x00237ae0 01000000 54162400 67b10900 20480800 ....T.$.g... H.. │ │ - 0x00237af0 b2020000 01000000 58162400 0f7f0800 ........X.$..... │ │ + 0x00237af0 b2020000 01000000 58162400 8b990800 ........X.$..... │ │ 0x00237b00 20480800 dc020000 01000000 5c162400 H..........\.$. │ │ - 0x00237b10 3edf0800 20480800 43030000 01000000 >... H..C....... │ │ - 0x00237b20 60162400 5d7f0800 20480800 70030000 `.$.]... H..p... │ │ + 0x00237b10 baf90800 20480800 43030000 01000000 .... H..C....... │ │ + 0x00237b20 60162400 d9990800 20480800 70030000 `.$..... H..p... │ │ 0x00237b30 01000000 64162400 b1480800 20480800 ....d.$..H.. H.. │ │ 0x00237b40 e3030000 01000000 68162400 b3620900 ........h.$..b.. │ │ 0x00237b50 20480800 36040000 01000000 6c162400 H..6.......l.$. │ │ - 0x00237b60 8cb60800 20480800 bf010000 01000000 .... H.......... │ │ + 0x00237b60 08d10800 20480800 bf010000 01000000 .... H.......... │ │ 0x00237b70 70162400 e78a0900 20480800 b8010000 p.$..... H...... │ │ 0x00237b80 01000000 74162400 f01a0800 20480800 ....t.$..... H.. │ │ - 0x00237b90 1b020000 01000000 78162400 198c0800 ........x.$..... │ │ + 0x00237b90 1b020000 01000000 78162400 95a60800 ........x.$..... │ │ 0x00237ba0 20480800 7b020000 01000000 793a1100 H..{.......y:.. │ │ 0x00237bb0 193b1100 b93b1100 593c1100 f93c1100 .;...;..Y<...<.. │ │ 0x00237bc0 893d1100 213e1100 00000000 7c162400 .=..!>......|.$. │ │ 0x00237bd0 41210900 20480800 a9030000 01000000 A!.. H.......... │ │ - 0x00237be0 80162400 5fc40800 20480800 af030000 ..$._... H...... │ │ + 0x00237be0 80162400 dbde0800 20480800 af030000 ..$..... H...... │ │ 0x00237bf0 01000000 84162400 940c0800 20480800 ......$..... H.. │ │ 0x00237c00 b5030000 01000000 88162400 da620900 ..........$..b.. │ │ 0x00237c10 20480800 bb030000 01000000 8c162400 H............$. │ │ 0x00237c20 b8060900 20480800 c1030000 01000000 .... H.......... │ │ 0x00237c30 90162400 14630900 20480800 c7030000 ..$..c.. H...... │ │ 0x00237c40 01000000 94162400 23980900 20480800 ......$.#... H.. │ │ - 0x00237c50 cd030000 01000000 98162400 dd7f0800 ..........$..... │ │ - 0x00237c60 a1720800 eb020000 01000000 9c162400 .r............$. │ │ - 0x00237c70 e5a60900 a1720800 cf070000 01000000 .....r.......... │ │ - 0x00237c80 a0162400 1f1b0800 a1720800 cf070000 ..$......r...... │ │ + 0x00237c50 cd030000 01000000 98162400 599a0800 ..........$.Y... │ │ + 0x00237c60 1d8d0800 eb020000 01000000 9c162400 ..............$. │ │ + 0x00237c70 e5a60900 1d8d0800 cf070000 01000000 ................ │ │ + 0x00237c80 a0162400 1f1b0800 1d8d0800 cf070000 ..$............. │ │ 0x00237c90 01000000 7d551100 cd641100 7d551100 ....}U...d..}U.. │ │ 0x00237ca0 7d551100 7d551100 7d551100 7d551100 }U..}U..}U..}U.. │ │ 0x00237cb0 7d551100 75751100 f9891100 195f1100 }U..uu......._.. │ │ 0x00237cc0 c96d1100 195f1100 195f1100 195f1100 .m..._..._..._.. │ │ 0x00237cd0 195f1100 195f1100 195f1100 69821100 ._..._..._..i... │ │ 0x00237ce0 d9931100 09641100 ad741100 09641100 .....d...t...d.. │ │ 0x00237cf0 09641100 09641100 09641100 09641100 .d...d...d...d.. │ │ 0x00237d00 09641100 e5881100 a5981100 a4162400 .d............$. │ │ 0x00237d10 4e630900 d00c0800 58000000 01000000 Nc......X....... │ │ 0x00237d20 14560900 d00c0800 ce010000 05000000 .V.............. │ │ - 0x00237d30 1d950800 33640800 39640800 3f8c0800 ....3d..9d..?... │ │ - 0x00237d40 d00c0800 15050000 03000000 1d950800 ................ │ │ - 0x00237d50 b0c40800 0f270800 2e800800 d00c0800 .....'.......... │ │ - 0x00237d60 1b050000 03000000 1d950800 b0c40800 ................ │ │ - 0x00237d70 0f270800 2e800800 d00c0800 1c050000 .'.............. │ │ - 0x00237d80 03000000 1d950800 25740800 0f270800 ........%t...'.. │ │ - 0x00237d90 2e800800 d00c0800 21050000 01000000 ........!....... │ │ - 0x00237da0 1d950800 93d00800 47480900 36a70800 ........GH..6... │ │ - 0x00237db0 d00c0800 35050000 03000000 1d950800 ....5........... │ │ - 0x00237dc0 b0c40800 0f270800 36a70800 d00c0800 .....'..6....... │ │ - 0x00237dd0 36050000 03000000 1d950800 25740800 6...........%t.. │ │ - 0x00237de0 0f270800 36a70800 d00c0800 37050000 .'..6.......7... │ │ - 0x00237df0 03000000 1d950800 64980900 0f270800 ........d....'.. │ │ - 0x00237e00 36a70800 d00c0800 3c050000 01000000 6.......<....... │ │ - 0x00237e10 1d950800 93d00800 47480900 36a70800 ........GH..6... │ │ - 0x00237e20 d00c0800 3d050000 01000000 1d950800 ....=........... │ │ - 0x00237e30 93d00800 8b1b0800 00000000 00000000 ................ │ │ + 0x00237d30 99af0800 33640800 39640800 bba60800 ....3d..9d...... │ │ + 0x00237d40 d00c0800 15050000 03000000 99af0800 ................ │ │ + 0x00237d50 2cdf0800 0f270800 aa9a0800 d00c0800 ,....'.......... │ │ + 0x00237d60 1b050000 03000000 99af0800 2cdf0800 ............,... │ │ + 0x00237d70 0f270800 aa9a0800 d00c0800 1c050000 .'.............. │ │ + 0x00237d80 03000000 99af0800 a18e0800 0f270800 .............'.. │ │ + 0x00237d90 aa9a0800 d00c0800 21050000 01000000 ........!....... │ │ + 0x00237da0 99af0800 0feb0800 47480900 b2c10800 ........GH...... │ │ + 0x00237db0 d00c0800 35050000 03000000 99af0800 ....5........... │ │ + 0x00237dc0 2cdf0800 0f270800 b2c10800 d00c0800 ,....'.......... │ │ + 0x00237dd0 36050000 03000000 99af0800 a18e0800 6............... │ │ + 0x00237de0 0f270800 b2c10800 d00c0800 37050000 .'..........7... │ │ + 0x00237df0 03000000 99af0800 64980900 0f270800 ........d....'.. │ │ + 0x00237e00 b2c10800 d00c0800 3c050000 01000000 ........<....... │ │ + 0x00237e10 99af0800 0feb0800 47480900 b2c10800 ........GH...... │ │ + 0x00237e20 d00c0800 3d050000 01000000 99af0800 ....=........... │ │ + 0x00237e30 0feb0800 8b1b0800 00000000 00000000 ................ │ │ 0x00237e40 61e11100 63e11100 00000000 00000000 a...c........... │ │ 0x00237e50 00000000 00000000 00000000 00000000 ................ │ │ 0x00237e60 00000000 00000000 00000000 08000000 ................ │ │ 0x00237e70 00000000 00000000 9c7e2300 65e11100 .........~#.e... │ │ 0x00237e80 6be11100 71e11100 73e11100 a19e1100 k...q...s....... │ │ 0x00237e90 75e11100 08000000 651a0a00 08000000 u.......e....... │ │ 0x00237ea0 441a0a00 947e2300 00000000 dc7e2300 D....~#......~#. │ │ @@ -660,72 +660,72 @@ │ │ 0x00237f60 00000000 00000000 00000000 00000000 ................ │ │ 0x00237f70 00000000 00000000 00000000 00000000 ................ │ │ 0x00237f80 00000000 00000000 00000000 00000000 ................ │ │ 0x00237f90 00000000 00000000 00000000 00000000 ................ │ │ 0x00237fa0 00000000 00000000 00000000 00000000 ................ │ │ 0x00237fb0 00000000 00000000 00000000 00000000 ................ │ │ 0x00237fc0 00000000 00000000 00000000 00000000 ................ │ │ - 0x00237fd0 00000000 d8162400 df570800 e5d00800 ......$..W...... │ │ + 0x00237fd0 00000000 d8162400 df570800 61eb0800 ......$..W..a... │ │ 0x00237fe0 48010000 01000000 dc162400 b5980900 H.........$..... │ │ - 0x00237ff0 e5d00800 69010000 01000000 e0162400 ....i.........$. │ │ - 0x00238000 107d0900 e5d00800 73010000 01000000 .}......s....... │ │ - 0x00238010 e4162400 97800800 e5d00800 94010000 ..$............. │ │ - 0x00238020 01000000 e8162400 74650800 e5d00800 ......$.te...... │ │ - 0x00238030 9e010000 01000000 ec162400 38740800 ..........$.8t.. │ │ - 0x00238040 e5d00800 d3010000 01000000 f0162400 ..............$. │ │ - 0x00238050 aa210900 e5d00800 dd010000 01000000 .!.............. │ │ - 0x00238060 f4162400 7da70800 e5d00800 07020000 ..$.}........... │ │ - 0x00238070 01000000 f8162400 52480900 e5d00800 ......$.RH...... │ │ + 0x00237ff0 61eb0800 69010000 01000000 e0162400 a...i.........$. │ │ + 0x00238000 107d0900 61eb0800 73010000 01000000 .}..a...s....... │ │ + 0x00238010 e4162400 139b0800 61eb0800 94010000 ..$.....a....... │ │ + 0x00238020 01000000 e8162400 74650800 61eb0800 ......$.te..a... │ │ + 0x00238030 9e010000 01000000 ec162400 b48e0800 ..........$..... │ │ + 0x00238040 61eb0800 d3010000 01000000 f0162400 a.............$. │ │ + 0x00238050 aa210900 61eb0800 dd010000 01000000 .!..a........... │ │ + 0x00238060 f4162400 f9c10800 61eb0800 07020000 ..$.....a....... │ │ + 0x00238070 01000000 f8162400 52480900 61eb0800 ......$.RH..a... │ │ 0x00238080 11020000 01000000 fc162400 9dcf0900 ..........$..... │ │ - 0x00238090 e5d00800 1b020000 01000000 00172400 ..............$. │ │ - 0x002380a0 fcb60800 e5d00800 5d020000 01000000 ........]....... │ │ - 0x002380b0 04172400 3b9b0800 e5d00800 43040000 ..$.;.......C... │ │ - 0x002380c0 01000000 08172400 83740800 e5d00800 ......$..t...... │ │ + 0x00238090 61eb0800 1b020000 01000000 00172400 a.............$. │ │ + 0x002380a0 78d10800 61eb0800 5d020000 01000000 x...a...]....... │ │ + 0x002380b0 04172400 b7b50800 61eb0800 43040000 ..$.....a...C... │ │ + 0x002380c0 01000000 08172400 ff8e0800 61eb0800 ......$.....a... │ │ 0x002380d0 4d040000 01000000 0c172400 6a270800 M.........$.j'.. │ │ - 0x002380e0 e5d00800 57040000 01000000 10172400 ....W.........$. │ │ - 0x002380f0 d0650800 e5d00800 61040000 01000000 .e......a....... │ │ - 0x00238100 14172400 43b20900 e5d00800 6b040000 ..$.C.......k... │ │ - 0x00238110 01000000 18172400 8f270800 e5d00800 ......$..'...... │ │ - 0x00238120 75040000 01000000 1c172400 659b0800 u.........$.e... │ │ - 0x00238130 e5d00800 cf040000 01000000 20172400 ............ .$. │ │ - 0x00238140 b82f0900 e5d00800 d9040000 01000000 ./.............. │ │ - 0x00238150 24172400 647d0900 e5d00800 ef040000 $.$.d}.......... │ │ - 0x00238160 01000000 28172400 4f640900 e5d00800 ....(.$.Od...... │ │ + 0x002380e0 61eb0800 57040000 01000000 10172400 a...W.........$. │ │ + 0x002380f0 d0650800 61eb0800 61040000 01000000 .e..a...a....... │ │ + 0x00238100 14172400 43b20900 61eb0800 6b040000 ..$.C...a...k... │ │ + 0x00238110 01000000 18172400 8f270800 61eb0800 ......$..'..a... │ │ + 0x00238120 75040000 01000000 1c172400 e1b50800 u.........$..... │ │ + 0x00238130 61eb0800 cf040000 01000000 20172400 a........... .$. │ │ + 0x00238140 b82f0900 61eb0800 d9040000 01000000 ./..a........... │ │ + 0x00238150 24172400 647d0900 61eb0800 ef040000 $.$.d}..a....... │ │ + 0x00238160 01000000 28172400 4f640900 61eb0800 ....(.$.Od..a... │ │ 0x00238170 4b050000 01000000 2c172400 50bf0900 K.......,.$.P... │ │ - 0x00238180 e5d00800 54050000 01000000 30172400 ....T.......0.$. │ │ - 0x00238190 61a70900 e5d00800 5e050000 01000000 a.......^....... │ │ - 0x002381a0 34172400 a9bf0900 e5d00800 68050000 4.$.........h... │ │ - 0x002381b0 01000000 38172400 b2a70900 e5d00800 ....8.$......... │ │ + 0x00238180 61eb0800 54050000 01000000 30172400 a...T.......0.$. │ │ + 0x00238190 61a70900 61eb0800 5e050000 01000000 a...a...^....... │ │ + 0x002381a0 34172400 a9bf0900 61eb0800 68050000 4.$.....a...h... │ │ + 0x002381b0 01000000 38172400 b2a70900 61eb0800 ....8.$.....a... │ │ 0x002381c0 73050000 01000000 3c172400 b7710900 s.......<.$..q.. │ │ - 0x002381d0 e5d00800 7d050000 01000000 40172400 ....}.......@.$. │ │ - 0x002381e0 9b8b0900 e5d00800 bb050000 01000000 ................ │ │ - 0x002381f0 44172400 1ee00800 e5d00800 c8050000 D.$............. │ │ - 0x00238200 01000000 48172400 6be00800 e5d00800 ....H.$.k....... │ │ - 0x00238210 01060000 01000000 4c172400 65d10800 ........L.$.e... │ │ - 0x00238220 e5d00800 09060000 01000000 50172400 ............P.$. │ │ - 0x00238230 68b20900 e5d00800 23060000 01000000 h.......#....... │ │ - 0x00238240 54172400 c68c0800 e5d00800 36060000 T.$.........6... │ │ - 0x00238250 01000000 58172400 bcb20900 e5d00800 ....X.$......... │ │ + 0x002381d0 61eb0800 7d050000 01000000 40172400 a...}.......@.$. │ │ + 0x002381e0 9b8b0900 61eb0800 bb050000 01000000 ....a........... │ │ + 0x002381f0 44172400 9afa0800 61eb0800 c8050000 D.$.....a....... │ │ + 0x00238200 01000000 48172400 e7fa0800 61eb0800 ....H.$.....a... │ │ + 0x00238210 01060000 01000000 4c172400 e1eb0800 ........L.$..... │ │ + 0x00238220 61eb0800 09060000 01000000 50172400 a...........P.$. │ │ + 0x00238230 68b20900 61eb0800 23060000 01000000 h...a...#....... │ │ + 0x00238240 54172400 42a70800 61eb0800 36060000 T.$.B...a...6... │ │ + 0x00238250 01000000 58172400 bcb20900 61eb0800 ....X.$.....a... │ │ 0x00238260 49060000 01000000 5c172400 b4270800 I.......\.$..'.. │ │ - 0x00238270 e5d00800 52060000 01000000 60172400 ....R.......`.$. │ │ - 0x00238280 f8bf0900 e5d00800 a3060000 01000000 ................ │ │ - 0x00238290 64172400 b8e00800 e5d00800 b7060000 d.$............. │ │ - 0x002382a0 01000000 68172400 827d0900 e5d00800 ....h.$..}...... │ │ - 0x002382b0 c1060000 01000000 6c172400 c6a70800 ........l.$..... │ │ - 0x002382c0 e5d00800 cb060000 01000000 70172400 ............p.$. │ │ - 0x002382d0 92390800 e5d00800 d4060000 01000000 .9.............. │ │ - 0x002382e0 74172400 a3640900 e5d00800 dd060000 t.$..d.......... │ │ - 0x002382f0 01000000 78172400 1f8d0800 e5d00800 ....x.$......... │ │ - 0x00238300 e6060000 01000000 7c172400 0ec50800 ........|.$..... │ │ - 0x00238310 e5d00800 ef060000 01000000 80172400 ..............$. │ │ - 0x00238320 829b0800 e5d00800 f8060000 01000000 ................ │ │ - 0x00238330 84172400 c33c0900 e5d00800 01070000 ..$..<.......... │ │ - 0x00238340 01000000 88172400 a1490800 e5d00800 ......$..I...... │ │ + 0x00238270 61eb0800 52060000 01000000 60172400 a...R.......`.$. │ │ + 0x00238280 f8bf0900 61eb0800 a3060000 01000000 ....a........... │ │ + 0x00238290 64172400 34fb0800 61eb0800 b7060000 d.$.4...a....... │ │ + 0x002382a0 01000000 68172400 827d0900 61eb0800 ....h.$..}..a... │ │ + 0x002382b0 c1060000 01000000 6c172400 42c20800 ........l.$.B... │ │ + 0x002382c0 61eb0800 cb060000 01000000 70172400 a...........p.$. │ │ + 0x002382d0 92390800 61eb0800 d4060000 01000000 .9..a........... │ │ + 0x002382e0 74172400 a3640900 61eb0800 dd060000 t.$..d..a....... │ │ + 0x002382f0 01000000 78172400 9ba70800 61eb0800 ....x.$.....a... │ │ + 0x00238300 e6060000 01000000 7c172400 8adf0800 ........|.$..... │ │ + 0x00238310 61eb0800 ef060000 01000000 80172400 a.............$. │ │ + 0x00238320 feb50800 61eb0800 f8060000 01000000 ....a........... │ │ + 0x00238330 84172400 c33c0900 61eb0800 01070000 ..$..<..a....... │ │ + 0x00238340 01000000 88172400 a1490800 61eb0800 ......$..I..a... │ │ 0x00238350 0a070000 01000000 8c172400 fca70900 ..........$..... │ │ - 0x00238360 e5d00800 13070000 01000000 00000000 ................ │ │ + 0x00238360 61eb0800 13070000 01000000 00000000 a............... │ │ 0x00238370 e8832300 00000000 25aa1200 29aa1200 ..#.....%...)... │ │ 0x00238380 65771200 00000000 00000000 00000000 ew.............. │ │ 0x00238390 00000000 00000000 00000000 00000000 ................ │ │ 0x002383a0 00000000 00000000 00000000 00000000 ................ │ │ 0x002383b0 00000000 00000000 00000000 00000000 ................ │ │ 0x002383c0 00000000 00000000 00000000 00000000 ................ │ │ 0x002383d0 00000000 00000000 00000000 00000000 ................ │ │ @@ -790,31 +790,31 @@ │ │ 0x00238780 97aa1200 9baa1200 0d9b1200 00000000 ................ │ │ 0x00238790 00000000 00000000 00000000 00000000 ................ │ │ 0x002387a0 00000000 00000000 00000000 00000000 ................ │ │ 0x002387b0 00000000 00000000 00000000 00000000 ................ │ │ 0x002387c0 00000000 359c1200 00000000 00000000 ....5........... │ │ 0x002387d0 00000000 00000000 00000000 00000000 ................ │ │ 0x002387e0 00000000 00000000 08000000 341b0a00 ............4... │ │ - 0x002387f0 00000000 9c172400 df070900 2fb70800 ......$...../... │ │ - 0x00238800 36000000 01000000 a0172400 67810800 6.........$.g... │ │ - 0x00238810 2fb70800 52000000 01000000 a4172400 /...R.........$. │ │ - 0x00238820 961b0800 2fb70800 5a000000 01000000 ..../...Z....... │ │ - 0x00238830 a8172400 24220900 2fb70800 63000000 ..$.$"../...c... │ │ - 0x00238840 05000000 ac172400 64580800 2fb70800 ......$.dX../... │ │ - 0x00238850 7f000000 01000000 b0172400 3ac50800 ..........$.:... │ │ - 0x00238860 2fb70800 87000000 01000000 b4172400 /.............$. │ │ - 0x00238870 aeb70800 2fb70800 ba000000 01000000 ..../........... │ │ - 0x00238880 b8172400 de130900 2fb70800 fa000000 ..$...../....... │ │ - 0x00238890 01000000 bc172400 e2e00800 2fb70800 ......$...../... │ │ - 0x002388a0 1d010000 01000000 c0172400 b6740800 ..........$..t.. │ │ - 0x002388b0 2fb70800 ff020000 01000000 c4172400 /.............$. │ │ - 0x002388c0 23a80900 2fb70800 e6040000 01000000 #.../........... │ │ + 0x002387f0 00000000 9c172400 df070900 abd10800 ......$......... │ │ + 0x00238800 36000000 01000000 a0172400 e39b0800 6.........$..... │ │ + 0x00238810 abd10800 52000000 01000000 a4172400 ....R.........$. │ │ + 0x00238820 961b0800 abd10800 5a000000 01000000 ........Z....... │ │ + 0x00238830 a8172400 24220900 abd10800 63000000 ..$.$"......c... │ │ + 0x00238840 05000000 ac172400 64580800 abd10800 ......$.dX...... │ │ + 0x00238850 7f000000 01000000 b0172400 b6df0800 ..........$..... │ │ + 0x00238860 abd10800 87000000 01000000 b4172400 ..............$. │ │ + 0x00238870 2ad20800 abd10800 ba000000 01000000 *............... │ │ + 0x00238880 b8172400 de130900 abd10800 fa000000 ..$............. │ │ + 0x00238890 01000000 bc172400 5efb0800 abd10800 ......$.^....... │ │ + 0x002388a0 1d010000 01000000 c0172400 328f0800 ..........$.2... │ │ + 0x002388b0 abd10800 ff020000 01000000 c4172400 ..............$. │ │ + 0x002388c0 23a80900 abd10800 e6040000 01000000 #............... │ │ 0x002388d0 99f81200 d1fa1200 09fd1200 79ff1200 ............y... │ │ 0x002388e0 e9011300 45041300 9d061300 00000000 ....E........... │ │ - 0x002388f0 c8172400 dd390800 2fb70800 fb040000 ..$..9../....... │ │ + 0x002388f0 c8172400 dd390800 abd10800 fb040000 ..$..9.......... │ │ 0x00238900 01000000 110b1300 410f1300 71131300 ........A...q... │ │ 0x00238910 e1171300 511c1300 81201300 61241300 ....Q.... ..a$.. │ │ 0x00238920 00000000 00000000 38892300 45281300 ........8.#.E(.. │ │ 0x00238930 7d281300 b9281300 08000000 4d1b0a00 }(...(......M... │ │ 0x00238940 00000000 00000000 58892300 3d291300 ........X.#.=).. │ │ 0x00238950 75291300 b1291300 08000000 871b0a00 u)...).......... │ │ 0x00238960 00000000 00000000 78892300 6d2a1300 ........x.#.m*.. │ │ @@ -929,18 +929,18 @@ │ │ 0x00239030 81af1300 91af1300 08000000 05280a00 .............(.. │ │ 0x00239040 00000000 00000000 58902300 00000000 ........X.#..... │ │ 0x00239050 11b21300 21b21300 08000000 42280a00 ....!.......B(.. │ │ 0x00239060 00000000 00000000 78902300 00000000 ........x.#..... │ │ 0x00239070 69b41300 79b41300 08000000 7f280a00 i...y........(.. │ │ 0x00239080 00000000 00000000 98902300 00000000 ..........#..... │ │ 0x00239090 e1b61300 f1b61300 08000000 bc280a00 .............(.. │ │ - 0x002390a0 00000000 cc172400 16720900 049c0800 ......$..r...... │ │ + 0x002390a0 00000000 cc172400 16720900 80b60800 ......$..r...... │ │ 0x002390b0 c1020000 01000000 d0172400 cc640900 ..........$..d.. │ │ - 0x002390c0 049c0800 02030000 01000000 d4172400 ..............$. │ │ - 0x002390d0 6bc00900 049c0800 45030000 01000000 k.......E....... │ │ + 0x002390c0 80b60800 02030000 01000000 d4172400 ..............$. │ │ + 0x002390d0 6bc00900 80b60800 45030000 01000000 k.......E....... │ │ 0x002390e0 41461400 93461400 f9461400 73471400 AF...F...F..sG.. │ │ 0x002390f0 ed471400 63481400 ef481400 00000000 .G..cH...H...... │ │ 0x00239100 81491400 e5491400 374a1400 ab4a1400 .I...I..7J...J.. │ │ 0x00239110 274b1400 9f4b1400 2d4c1400 00000000 'K...K..-L...... │ │ 0x00239120 c14c1400 374d1400 ad4d1400 034e1400 .L..7M...M...N.. │ │ 0x00239130 754e1400 e34e1400 4f4f1400 00000000 uN...N..OO...... │ │ 0x00239140 cf4f1400 5f501400 db501400 43511400 .O.._P...P..CQ.. │ │ @@ -982,103 +982,103 @@ │ │ 0x00239380 3fab1400 85ab1400 d1ab1400 00000000 ?............... │ │ 0x00239390 17ac1400 00000000 67ac1400 00000000 ........g....... │ │ 0x002393a0 00000000 00000000 adac1400 00000000 ................ │ │ 0x002393b0 00000000 00000000 fdac1400 00000000 ................ │ │ 0x002393c0 00000000 00000000 00000000 00000000 ................ │ │ 0x002393d0 00000000 00000000 41ad1400 00000000 ........A....... │ │ 0x002393e0 00000000 00000000 00000000 00000000 ................ │ │ - 0x002393f0 00000000 00000000 99ad1400 f8b70800 ................ │ │ + 0x002393f0 00000000 00000000 99ad1400 74d20800 ............t... │ │ 0x00239400 1f3d0900 26010000 01000000 979a0900 .=..&........... │ │ - 0x00239410 a3810800 0e660800 f8b70800 1f3d0900 .....f.......=.. │ │ + 0x00239410 1f9c0800 0e660800 74d20800 1f3d0900 .....f..t....=.. │ │ 0x00239420 27010000 01000000 57220900 bc9a0900 '.......W"...... │ │ - 0x00239430 10660800 f8b70800 1f3d0900 2d010000 .f.......=..-... │ │ + 0x00239430 10660800 74d20800 1f3d0900 2d010000 .f..t....=..-... │ │ 0x00239440 01000000 ff490800 7d220900 dc480900 .....I..}"...H.. │ │ 0x00239450 dc172400 9c220900 1f3d0900 0c030000 ..$.."...=...... │ │ 0x00239460 01000000 e0172400 0c3a0800 1f3d0900 ......$..:...=.. │ │ 0x00239470 4a030000 01000000 0c3a0800 1f3d0900 J........:...=.. │ │ - 0x00239480 50030000 04000000 01a80800 bac00900 P............... │ │ - 0x00239490 bd9c0800 0c3a0800 1f3d0900 51030000 .....:...=..Q... │ │ - 0x002394a0 05000000 01a80800 bac00900 9a580800 .............X.. │ │ - 0x002394b0 e4172400 24a80800 1f3d0900 a3030000 ..$.$....=...... │ │ - 0x002394c0 01000000 24a80800 1f3d0900 a6030000 ....$....=...... │ │ - 0x002394d0 00000000 26e10800 b37d0900 1d950800 ....&....}...... │ │ - 0x002394e0 24a80800 1f3d0900 a7030000 01000000 $....=.......... │ │ - 0x002394f0 40b80800 ea8b0900 0e660800 24a80800 @........f..$... │ │ + 0x00239480 50030000 04000000 7dc20800 bac00900 P.......}....... │ │ + 0x00239490 39b70800 0c3a0800 1f3d0900 51030000 9....:...=..Q... │ │ + 0x002394a0 05000000 7dc20800 bac00900 9a580800 ....}........X.. │ │ + 0x002394b0 e4172400 a0c20800 1f3d0900 a3030000 ..$......=...... │ │ + 0x002394c0 01000000 a0c20800 1f3d0900 a6030000 .........=...... │ │ + 0x002394d0 00000000 a2fb0800 b37d0900 99af0800 .........}...... │ │ + 0x002394e0 a0c20800 1f3d0900 a7030000 01000000 .....=.......... │ │ + 0x002394f0 bcd20800 ea8b0900 0e660800 a0c20800 .........f...... │ │ 0x00239500 1f3d0900 aa030000 01000000 ce9a0900 .=.............. │ │ - 0x00239510 fc9a0900 e1950800 24a80800 1f3d0900 ........$....=.. │ │ + 0x00239510 fc9a0900 5db00800 a0c20800 1f3d0900 ....]........=.. │ │ 0x00239520 b1030000 03000000 2e660800 c0c00900 .........f...... │ │ - 0x00239530 c67d0900 24a80800 1f3d0900 b9030000 .}..$....=...... │ │ + 0x00239530 c67d0900 a0c20800 1f3d0900 b9030000 .}.......=...... │ │ 0x00239540 01000000 099b0900 c8220900 12080900 ........."...... │ │ - 0x00239550 24a80800 1f3d0900 e1030000 00000000 $....=.......... │ │ - 0x00239560 50e10800 9d3d0900 e07d0900 8b3a0800 P....=...}...:.. │ │ + 0x00239550 a0c20800 1f3d0900 e1030000 00000000 .....=.......... │ │ + 0x00239560 ccfb0800 9d3d0900 e07d0900 8b3a0800 .....=...}...:.. │ │ 0x00239570 22080900 37020000 03000000 a93d0900 "...7........=.. │ │ 0x00239580 0d7e0900 0f270800 459b0900 22080900 .~...'..E..."... │ │ 0x00239590 14050000 01000000 0c8c0900 400e0800 ............@... │ │ 0x002395a0 c01b0800 459b0900 22080900 18050000 ....E..."....... │ │ 0x002395b0 01000000 5d8c0900 82140900 4e230900 ....].......N#.. │ │ 0x002395c0 459b0900 22080900 1a050000 01000000 E..."........... │ │ 0x002395d0 5d8c0900 b73d0900 50280800 459b0900 ]....=..P(..E... │ │ - 0x002395e0 22080900 32050000 01000000 9a8d0800 "...2........... │ │ + 0x002395e0 22080900 32050000 01000000 16a80800 "...2........... │ │ 0x002395f0 400e0800 c01b0800 459b0900 22080900 @.......E..."... │ │ 0x00239600 36050000 01000000 03590800 82140900 6........Y...... │ │ 0x00239610 4e230900 459b0900 22080900 38050000 N#..E..."...8... │ │ 0x00239620 01000000 03590800 b73d0900 50280800 .....Y...=..P(.. │ │ 0x00239630 459b0900 22080900 43050000 03000000 E..."...C....... │ │ - 0x00239640 1d950800 4e230900 0f270800 459b0900 ....N#...'..E... │ │ - 0x00239650 22080900 49050000 00000000 1d950800 "...I........... │ │ + 0x00239640 99af0800 4e230900 0f270800 459b0900 ....N#...'..E... │ │ + 0x00239650 22080900 49050000 00000000 99af0800 "...I........... │ │ 0x00239660 aa720900 89140900 459b0900 22080900 .r......E..."... │ │ - 0x00239670 4f050000 01000000 1d950800 aa720900 O............r.. │ │ + 0x00239670 4f050000 01000000 99af0800 aa720900 O............r.. │ │ 0x00239680 504a0800 459b0900 22080900 55050000 PJ..E..."...U... │ │ - 0x00239690 00000000 1d950800 aa720900 41d00900 .........r..A... │ │ - 0x002396a0 e8172400 b1c50800 c13d0900 39010000 ..$......=..9... │ │ + 0x00239690 00000000 99af0800 aa720900 41d00900 .........r..A... │ │ + 0x002396a0 e8172400 2de00800 c13d0900 39010000 ..$.-....=..9... │ │ 0x002396b0 01000000 d1361500 413b1500 d53f1500 .....6..A;...?.. │ │ 0x002396c0 39441500 a9481500 014d1500 49511500 9D...H...M..IQ.. │ │ 0x002396d0 00000000 ec172400 50230900 78230900 ......$.P#..x#.. │ │ 0x002396e0 7f000000 01000000 f0172400 1cb30900 ..........$..... │ │ 0x002396f0 78230900 06020000 01000000 f4172400 x#............$. │ │ 0x00239700 383e0900 c13d0900 23010000 01000000 8>...=..#....... │ │ 0x00239710 f8172400 21150900 c13d0900 26010000 ..$.!....=..&... │ │ - 0x00239720 01000000 fc172400 c29c0800 c13d0900 ......$......=.. │ │ - 0x00239730 29010000 01000000 00182400 14d20800 ).........$..... │ │ + 0x00239720 01000000 fc172400 3eb70800 c13d0900 ......$.>....=.. │ │ + 0x00239730 29010000 01000000 00182400 90ec0800 ).........$..... │ │ 0x00239740 c13d0900 2c010000 01000000 04182400 .=..,.........$. │ │ - 0x00239750 c2810800 c13d0900 2f010000 01000000 .....=../....... │ │ + 0x00239750 3e9c0800 c13d0900 2f010000 01000000 >....=../....... │ │ 0x00239760 08182400 f3230900 c13d0900 32010000 ..$..#...=..2... │ │ 0x00239770 01000000 0c182400 a49b0900 c13d0900 ......$......=.. │ │ - 0x00239780 35010000 01000000 10182400 1b9d0800 5.........$..... │ │ + 0x00239780 35010000 01000000 10182400 97b70800 5.........$..... │ │ 0x00239790 78230900 be000000 01000000 14182400 x#............$. │ │ - 0x002397a0 e1c50800 1e3b0800 af000000 01000000 .....;.......... │ │ - 0x002397b0 18182400 3d9d0800 1e3b0800 ba000000 ..$.=....;...... │ │ - 0x002397c0 01000000 1c182400 95a80800 1e3b0800 ......$......;.. │ │ + 0x002397a0 5de00800 1e3b0800 af000000 01000000 ]....;.......... │ │ + 0x002397b0 18182400 b9b70800 1e3b0800 ba000000 ..$......;...... │ │ + 0x002397c0 01000000 1c182400 11c30800 1e3b0800 ......$......;.. │ │ 0x002397d0 c5000000 01000000 20182400 91570900 ........ .$..W.. │ │ 0x002397e0 1e3b0800 d0000000 01000000 24182400 .;..........$.$. │ │ - 0x002397f0 e8080900 1b820800 10000000 01000000 ................ │ │ - 0x00239800 28182400 9f750800 1b820800 18000000 (.$..u.......... │ │ - 0x00239810 01000000 2c182400 d9570900 1b820800 ....,.$..W...... │ │ + 0x002397f0 e8080900 979c0800 10000000 01000000 ................ │ │ + 0x00239800 28182400 1b900800 979c0800 18000000 (.$............. │ │ + 0x00239810 01000000 2c182400 d9570900 979c0800 ....,.$..W...... │ │ 0x00239820 20000000 01000000 30182400 ba280800 .......0.$..(.. │ │ - 0x00239830 1b820800 28000000 01000000 34182400 ....(.......4.$. │ │ - 0x00239840 d9a80800 1b820800 76000000 01000000 ........v....... │ │ - 0x00239850 38182400 8c3e0900 1b820800 07010000 8.$..>.......... │ │ + 0x00239830 979c0800 28000000 01000000 34182400 ....(.......4.$. │ │ + 0x00239840 55c30800 979c0800 76000000 01000000 U.......v....... │ │ + 0x00239850 38182400 8c3e0900 979c0800 07010000 8.$..>.......... │ │ 0x00239860 01000000 00000000 00000000 00000000 ................ │ │ 0x00239870 00000000 00000000 00000000 00000000 ................ │ │ - 0x00239880 00000000 3c182400 75150900 0aa90800 ....<.$.u....... │ │ - 0x00239890 de050000 01000000 40182400 db750800 ........@.$..u.. │ │ - 0x002398a0 0aa90800 26060000 01000000 db750800 ....&........u.. │ │ - 0x002398b0 0aa90800 29060000 03000000 1d950800 ....)........... │ │ + 0x00239880 00000000 3c182400 75150900 86c30800 ....<.$.u....... │ │ + 0x00239890 de050000 01000000 40182400 57900800 ........@.$.W... │ │ + 0x002398a0 86c30800 26060000 01000000 57900800 ....&.......W... │ │ + 0x002398b0 86c30800 29060000 03000000 99af0800 ....)........... │ │ 0x002398c0 9b080900 0f270800 a77a1500 657b1500 .....'...z..e{.. │ │ 0x002398d0 237c1500 e17c1500 9f7d1500 537e1500 #|...|...}..S~.. │ │ - 0x002398e0 157f1500 00000000 44182400 eab80800 ........D.$..... │ │ - 0x002398f0 0aa90800 84060000 01000000 48182400 ............H.$. │ │ - 0x00239900 2eb90800 eb720900 57020000 01000000 .....r..W....... │ │ - 0x00239910 2eb90800 eb720900 c7020000 04000000 .....r.......... │ │ - 0x00239920 1d950800 7ea90800 1b7e0900 4c182400 ....~....~..L.$. │ │ + 0x002398e0 157f1500 00000000 44182400 66d30800 ........D.$.f... │ │ + 0x002398f0 86c30800 84060000 01000000 48182400 ............H.$. │ │ + 0x00239900 aad30800 eb720900 57020000 01000000 .....r..W....... │ │ + 0x00239910 aad30800 eb720900 c7020000 04000000 .....r.......... │ │ + 0x00239920 99af0800 fac30800 1b7e0900 4c182400 .........~..L.$. │ │ 0x00239930 62650900 eb720900 2d040000 01000000 be...r..-....... │ │ 0x00239940 62650900 eb720900 2f040000 01000000 be...r../....... │ │ 0x00239950 49580900 009c0900 963b0800 62650900 IX.......;..be.. │ │ - 0x00239960 eb720900 9b040000 04000000 1d950800 .r.............. │ │ - 0x00239970 7ea90800 1b7e0900 50182400 14b40900 ~....~..P.$..... │ │ + 0x00239960 eb720900 9b040000 04000000 99af0800 .r.............. │ │ + 0x00239970 fac30800 1b7e0900 50182400 14b40900 .....~..P.$..... │ │ 0x00239980 eb720900 f2040000 01000000 54182400 .r..........T.$. │ │ 0x00239990 68240900 eb720900 56050000 01000000 h$...r..V....... │ │ 0x002399a0 c1b11500 dbb21500 1db41500 49b51500 ............I... │ │ 0x002399b0 6fb61500 c1a11500 89b71500 00000000 o............... │ │ 0x002399c0 1fb81500 1db91500 45ba1500 35bb1500 ........E...5... │ │ 0x002399d0 3dbc1500 41a11500 c9bc1500 00000000 =...A........... │ │ 0x002399e0 41bd1500 3bbe1500 35bf1500 b5bf1500 A...;...5....... │ │ @@ -1131,35 +1131,35 @@ │ │ 0x00239cd0 109b2300 00000000 f09c2300 c9fd1500 ..#.......#..... │ │ 0x00239ce0 d9fd1500 f5fd1500 00000000 f7fd1500 ................ │ │ 0x00239cf0 08000000 9b2e0a00 00000000 00000000 ................ │ │ 0x00239d00 209d2300 00000000 fbfd1500 01fe1500 .#............. │ │ 0x00239d10 41eb1500 45eb1500 49eb1500 4deb1500 A...E...I...M... │ │ 0x00239d20 08000000 e32e0a00 109b2300 84182400 ..........#...$. │ │ 0x00239d30 82c10900 a8160900 fa010000 01000000 ................ │ │ - 0x00239d40 88182400 36830800 00000000 8c182400 ..$.6.........$. │ │ + 0x00239d40 88182400 b29d0800 00000000 8c182400 ..$...........$. │ │ 0x00239d50 821c0800 00000000 90182400 8c1c0800 ..........$..... │ │ 0x00239d60 00000000 00000000 00000000 00000000 ................ │ │ 0x00239d70 00000000 00000000 08000000 00000000 ................ │ │ 0x00239d80 00000000 949d2300 00000000 b7041600 ......#......... │ │ 0x00239d90 bd041600 08000000 0d2f0a00 00000000 ........./...... │ │ 0x00239da0 98182400 38670800 a8160900 42010000 ..$.8g......B... │ │ - 0x00239db0 01000000 9c182400 36830800 00000000 ......$.6....... │ │ + 0x00239db0 01000000 9c182400 b29d0800 00000000 ......$......... │ │ 0x00239dc0 a0182400 821c0800 00000000 64000000 ..$.........d... │ │ 0x00239dd0 00000000 00000000 6d0a1600 110c1600 ........m....... │ │ 0x00239de0 9cffffff 9cffffff 00000000 5d0c1600 ............]... │ │ 0x00239df0 a90c1600 0c000000 0c000000 20000000 ............ ... │ │ 0x00239e00 20000000 64000000 00000000 00000000 ...d........... │ │ 0x00239e10 00000000 00000000 9cffffff 9cffffff ................ │ │ 0x00239e20 00000000 00000000 00000000 08000000 ................ │ │ 0x00239e30 00000000 00000000 00000000 00000000 ................ │ │ 0x00239e40 8d0b1600 f90c1600 090d1600 b90d1600 ................ │ │ 0x00239e50 730e1600 010f1600 690f1600 00000000 s.......i....... │ │ 0x00239e60 00000000 ad101600 00000000 5d121600 ............]... │ │ 0x00239e70 00000000 a1121600 08000000 00000000 ................ │ │ - 0x00239e80 00000000 d4182400 458e0800 56490900 ......$.E...VI.. │ │ + 0x00239e80 00000000 d4182400 c1a80800 56490900 ......$.....VI.. │ │ 0x00239e90 80000000 01000000 00000000 00000000 ................ │ │ 0x00239ea0 00000000 00000000 00000000 00000000 ................ │ │ 0x00239eb0 00000000 00000000 00000000 08000000 ................ │ │ 0x00239ec0 00000000 00000000 e09e2300 e9951600 ..........#..... │ │ 0x00239ed0 f9951600 15961600 00000000 1b961600 ................ │ │ 0x00239ee0 08000000 be2f0a00 00000000 00000000 ...../.......... │ │ 0x00239ef0 089f2300 3d971600 4d971600 69971600 ..#.=...M...i... │ │ @@ -1168,21 +1168,21 @@ │ │ 0x00239f20 29a71600 45a71600 00000000 89a71600 )...E........... │ │ 0x00239f30 08000000 6a300a00 00000000 00000000 ....j0.......... │ │ 0x00239f40 589f2300 8da71600 cfa71600 17a81600 X.#............. │ │ 0x00239f50 08000000 f2300a00 08000000 c9300a00 .....0.......0.. │ │ 0x00239f60 509f2300 00000000 809f2300 00000000 P.#.......#..... │ │ 0x00239f70 5daa1600 6daa1600 71aa1600 89aa1600 ]...m...q....... │ │ 0x00239f80 08000000 1a310a00 00000000 18192400 .....1........$. │ │ - 0x00239f90 320a0900 9bb90800 63010000 01000000 2.......c....... │ │ - 0x00239fa0 1c192400 25170900 9bb90800 6f010000 ..$.%.......o... │ │ - 0x00239fb0 01000000 20192400 a6580900 9bb90800 .... .$..X...... │ │ + 0x00239f90 320a0900 17d40800 63010000 01000000 2.......c....... │ │ + 0x00239fa0 1c192400 25170900 17d40800 6f010000 ..$.%.......o... │ │ + 0x00239fb0 01000000 20192400 a6580900 17d40800 .... .$..X...... │ │ 0x00239fc0 7b010000 01000000 24192400 544a0900 {.......$.$.TJ.. │ │ - 0x00239fd0 9bb90800 87010000 01000000 28192400 ............(.$. │ │ - 0x00239fe0 b93f0900 9bb90800 93010000 01000000 .?.............. │ │ - 0x00239ff0 2c192400 b48d0900 9bb90800 9e010000 ,.$............. │ │ + 0x00239fd0 17d40800 87010000 01000000 28192400 ............(.$. │ │ + 0x00239fe0 b93f0900 17d40800 93010000 01000000 .?.............. │ │ + 0x00239ff0 2c192400 b48d0900 17d40800 9e010000 ,.$............. │ │ 0x0023a000 01000000 00000000 00000000 00000000 ................ │ │ 0x0023a010 00000000 00000000 00000000 00000000 ................ │ │ 0x0023a020 00000000 00000000 00000000 00000000 ................ │ │ 0x0023a030 00000000 00000000 00000000 00000000 ................ │ │ 0x0023a040 00000000 00000000 00000000 00000000 ................ │ │ 0x0023a050 00000000 00000000 00000000 00000000 ................ │ │ 0x0023a060 00000000 00000000 00000000 00000000 ................ │ │ @@ -1249,38 +1249,38 @@ │ │ 0x0023a430 00000000 00000000 00000000 00000000 ................ │ │ 0x0023a440 00000000 e14a1800 68202400 d12a0800 .....J..h $..*.. │ │ 0x0023a450 998e0900 b3000000 01000000 6c202400 ............l $. │ │ 0x0023a460 5cd20900 998e0900 be000000 01000000 \............... │ │ 0x0023a470 70202400 07350900 998e0900 c9000000 p $..5.......... │ │ 0x0023a480 01000000 74202400 629d0900 998e0900 ....t $.b....... │ │ 0x0023a490 d4000000 01000000 78202400 5f400900 ........x $._@.. │ │ - 0x0023a4a0 0cc80800 10000000 01000000 7c202400 ............| $. │ │ - 0x0023a4b0 0a260900 0cc80800 18000000 01000000 .&.............. │ │ - 0x0023a4c0 80202400 a6d20900 0cc80800 20000000 . $......... ... │ │ - 0x0023a4d0 01000000 84202400 46260900 0cc80800 ..... $.F&...... │ │ + 0x0023a4a0 88e20800 10000000 01000000 7c202400 ............| $. │ │ + 0x0023a4b0 0a260900 88e20800 18000000 01000000 .&.............. │ │ + 0x0023a4c0 80202400 a6d20900 88e20800 20000000 . $......... ... │ │ + 0x0023a4d0 01000000 84202400 46260900 88e20800 ..... $.F&...... │ │ 0x0023a4e0 28000000 01000000 88202400 e0170900 (........ $..... │ │ - 0x0023a4f0 0cc80800 79000000 01000000 8c202400 ....y........ $. │ │ - 0x0023a500 aa9d0900 0cc80800 d9000000 01000000 ................ │ │ + 0x0023a4f0 88e20800 79000000 01000000 8c202400 ....y........ $. │ │ + 0x0023a500 aa9d0900 88e20800 d9000000 01000000 ................ │ │ 0x0023a510 00000000 00000000 00000000 00000000 ................ │ │ 0x0023a520 00000000 00000000 00000000 00000000 ................ │ │ - 0x0023a530 90202400 7b900800 dcd20900 0e000000 . $.{........... │ │ + 0x0023a530 90202400 f7aa0800 dcd20900 0e000000 . $............. │ │ 0x0023a540 01000000 94202400 860b0900 dcd20900 ..... $......... │ │ 0x0023a550 16000000 01000000 1d081900 250b1900 ............%... │ │ 0x0023a560 390e1900 21111900 11141900 8d171900 9...!........... │ │ 0x0023a570 191b1900 00000000 98202400 92590900 ......... $..Y.. │ │ 0x0023a580 a3670900 1a000000 01000000 9c202400 .g........... $. │ │ 0x0023a590 043d0800 a3670900 ba000000 01000000 .=...g.......... │ │ 0x0023a5a0 a0202400 9e400900 681d0800 9f010000 . $..@..h....... │ │ 0x0023a5b0 01000000 a4202400 182b0800 681d0800 ..... $..+..h... │ │ 0x0023a5c0 a2010000 01000000 a8202400 632b0800 ......... $.c+.. │ │ 0x0023a5d0 681d0800 a5010000 01000000 ac202400 h............ $. │ │ 0x0023a5e0 a34b0900 681d0800 a8010000 01000000 .K..h........... │ │ 0x0023a5f0 b0202400 8cb60900 681d0800 ab010000 . $.....h....... │ │ 0x0023a600 01000000 b4202400 b02b0800 681d0800 ..... $..+..h... │ │ - 0x0023a610 ae010000 01000000 b8202400 c69f0800 ......... $..... │ │ + 0x0023a610 ae010000 01000000 b8202400 42ba0800 ......... $.B... │ │ 0x0023a620 681d0800 b1010000 01000000 00000000 h............... │ │ 0x0023a630 00000000 00000000 00000000 00000000 ................ │ │ 0x0023a640 08000000 00000000 00000000 00000000 ................ │ │ 0x0023a650 00000000 00000000 00000000 00000000 ................ │ │ 0x0023a660 00000000 08000000 00000000 00000000 ................ │ │ 0x0023a670 84a62300 c9651900 59661900 05671900 ..#..e..Yf...g.. │ │ 0x0023a680 27671900 08000000 e8490a00 00000000 'g.......I...... │ │ @@ -1312,38 +1312,38 @@ │ │ 0x0023a820 0b560a00 00000000 01000000 00000000 .V.............. │ │ 0x0023a830 00000000 08000000 be550a00 1ca82300 .........U....#. │ │ 0x0023a840 00000000 1ca82300 01a21900 29a21900 ......#.....)... │ │ 0x0023a850 55a21900 aba21900 00000000 74a82300 U...........t.#. │ │ 0x0023a860 00000000 7ba31900 8ba31900 a5a31900 ....{........... │ │ 0x0023a870 bda31900 08000000 4c560a00 00000000 ........LV...... │ │ 0x0023a880 a82e2400 ef180900 958f0900 44000000 ..$.........D... │ │ - 0x0023a890 01000000 ac2e2400 53690800 958f0900 ......$.Si...... │ │ - 0x0023a8a0 60000000 01000000 2c2f2400 c6ab0800 `.......,/$..... │ │ + 0x0023a890 01000000 ac2e2400 cf830800 958f0900 ......$......... │ │ + 0x0023a8a0 60000000 01000000 2c2f2400 42c60800 `.......,/$.B... │ │ 0x0023a8b0 9f350900 6f040000 01000000 302f2400 .5..o.......0/$. │ │ 0x0023a8c0 f0750900 9f350900 a5040000 01000000 .u...5.......... │ │ - 0x0023a8d0 342f2400 65840800 9f350900 d6040000 4/$.e....5...... │ │ + 0x0023a8d0 342f2400 e19e0800 9f350900 d6040000 4/$......5...... │ │ 0x0023a8e0 01000000 382f2400 80680900 9f350900 ....8/$..h...5.. │ │ 0x0023a8f0 17050000 01000000 00000000 10a92300 ..............#. │ │ 0x0023a900 71ec1900 99ec1900 c5ec1900 d9ec1900 q............... │ │ 0x0023a910 08000000 73570a00 00000000 01000000 ....sW.......... │ │ 0x0023a920 00000000 00000000 00000000 44a92300 ............D.#. │ │ 0x0023a930 00000000 3d2b1a00 4d2b1a00 992b1a00 ....=+..M+...+.. │ │ 0x0023a940 b52b1a00 08000000 9b570a00 00000000 .+.......W...... │ │ 0x0023a950 542f2400 25760900 439f0900 7b000000 T/$.%v..C...{... │ │ 0x0023a960 01000000 582f2400 81190900 439f0900 ....X/$.....C... │ │ 0x0023a970 ba000000 01000000 5c2f2400 a52c0800 ........\/$..,.. │ │ 0x0023a980 439f0900 dd000000 01000000 602f2400 C...........`/$. │ │ 0x0023a990 965c0800 0b110800 48000000 01000000 .\......H....... │ │ 0x0023a9a0 642f2400 2f270900 0b110800 68000000 d/$./'......h... │ │ - 0x0023a9b0 01000000 682f2400 f3900800 0b110800 ....h/$......... │ │ + 0x0023a9b0 01000000 682f2400 6fab0800 0b110800 ....h/$.o....... │ │ 0x0023a9c0 74000000 01000000 6c2f2400 7a360900 t.......l/$.z6.. │ │ 0x0023a9d0 0b110800 99000000 01000000 00000000 ................ │ │ 0x0023a9e0 f8a92300 bd6d1a00 cd6d1a00 e96d1a00 ..#..m...m...m.. │ │ 0x0023a9f0 00000000 ef6d1a00 08000000 005a0a00 .....m.......Z.. │ │ - 0x0023aa00 00000000 e3360900 78180800 66910800 .....6..x...f... │ │ + 0x0023aa00 00000000 e3360900 78180800 e2ab0800 .....6..x....... │ │ 0x0023aa10 78140400 02120800 78040c00 893d0800 x.......x....=.. │ │ 0x0023aa20 64000400 00000000 00000000 00000000 d............... │ │ 0x0023aa30 00000000 08000000 00000000 00000000 ................ │ │ 0x0023aa40 00000000 00000000 00000000 00000000 ................ │ │ 0x0023aa50 08000000 00000000 00000000 00000000 ................ │ │ 0x0023aa60 00000000 00000000 00000000 00000000 ................ │ │ 0x0023aa70 08000000 00000000 00000000 00000000 ................ │ │ @@ -1895,39 +1895,39 @@ │ │ 0x0023cc90 a87d2100 b07d2100 b87d2100 c07d2100 .}!..}!..}!..}!. │ │ 0x0023cca0 f8822100 887e2100 8c7e2100 ec2c2200 ..!..~!..~!..,". │ │ 0x0023ccb0 04842100 08000000 f47c0a00 04cc2300 ..!......|....#. │ │ 0x0023ccc0 00000000 eccc2300 009c2100 889c2100 ......#...!...!. │ │ 0x0023ccd0 0c9d2100 909d2100 dc9d2100 249e2100 ..!...!...!.$.!. │ │ 0x0023cce0 8c7e2100 ec2c2200 6c9e2100 08000000 .~!..,".l.!..... │ │ 0x0023ccf0 237d0a00 04cc2300 614e0222 29280900 #}....#.aN.")(.. │ │ - 0x0023cd00 61530222 337b0800 6161021c 314d0900 aS."3{..aa..1M.. │ │ + 0x0023cd00 61530222 af950800 6161021c 314d0900 aS."....aa..1M.. │ │ 0x0023cd10 61640004 d82d0800 616e0216 d82d0800 ad...-..an...-.. │ │ - 0x0023cd20 61740c05 ce760900 61770a00 86c90800 at...v..aw...... │ │ + 0x0023cd20 61740c05 ce760900 61770a00 02e40800 at...v..aw...... │ │ 0x0023cd30 617a0c04 ce760900 63630b02 79120800 az...v..cc..y... │ │ 0x0023cd40 636c0702 f3860900 636d0224 e04d0800 cl......cm.$.M.. │ │ 0x0023cd50 636f0004 84120800 63760806 3c4d0900 co......cv..