--- /home/fdroid/fdroiddata/tmp/alt.nainapps.sharepaste.fdroid_1734722267.apk
+++ /home/fdroid/fdroiddata/tmp/sigcp_alt.nainapps.sharepaste.fdroid_1734722267.apk
├── zipinfo -v {}
│ @@ -231,15 +231,15 @@
│    version of encoding software:                   0.0
│    minimum file system compatibility required:     MS-DOS, OS/2 or NT FAT
│    minimum software version required to extract:   0.0
│    compression method:                             none (stored)
│    file security status:                           not encrypted
│    extended local header:                          no
│    file last modified on (DOS date/time):          1981 Jan 1 01:01:02
│ -  32-bit CRC value (hex):                         a6fe18dc
│ +  32-bit CRC value (hex):                         0a0c93c9
│    compressed size:                                5114536 bytes
│    uncompressed size:                              5114536 bytes
│    length of filename:                             27 characters
│    length of extra field:                          0 bytes
│    length of file comment:                         0 characters
│    disk number on which file begins:               disk 1
│    apparent file type:                             binary
├── lib/armeabi-v7a/libpbcli.so
│ ├── strings --all --bytes=8 {}
│ │ @@ -5418,14 +5418,15 @@
│ │  crypto/dsa/dsa_pmeth.c
│ │  dh_1024_160
│ │  dh_2048_256
│ │  generator G:
│ │  subgroup order Q:
│ │  ffc_validate_LN
│ │  ossl_namemap_add_names
│ │ +built on: Fri Dec 20 19:14:54 2024 UTC
│ │  CPUINFO: OPENSSL_armcap=0x%x
│ │  expecting a dsa key
│ │  getting AlgorithmIdentifier not supported
│ │  locking not supported
│ │  no cipher set
│ │  depth exceeded
│ │  list error
│ │ @@ -8324,15 +8325,14 @@
│ │  implicit-rejection
│ │  hexsecret
│ │  X942KDF-ASN1
│ │  rsa-factor8
│ │  fips186_4
│ │  pkey_ec_derive
│ │  ossl_method_construct_precondition
│ │ -built on: Tue Dec 24 14:53:20 2024 UTC
│ │  arg2 lt arg3
│ │  no suitable digest
│ │  private key too large
│ │  q too large
│ │  camellia key setup failed
│ │  expecting an rsa key
│ │  inaccessible key
│ ├── readelf --wide --decompress --string-dump=.rodata {}
│ │ @@ -6204,3353 +6204,3353 @@
│ │    [ 2e84c]  dh_1024_160
│ │    [ 2e858]  dh_2048_256
│ │    [ 2e864]  generator G:
│ │    [ 2e871]  subgroup order Q:
│ │    [ 2e883]  seed:
│ │    [ 2e889]  ffc_validate_LN
│ │    [ 2e899]  ossl_namemap_add_names
│ │ -  [ 2e8b0]  CPUINFO: OPENSSL_armcap=0x%x
│ │ -  [ 2e8cd]  expecting a dsa key
│ │ -  [ 2e8e1]  getting AlgorithmIdentifier not supported
│ │ -  [ 2e90b]  locking not supported
│ │ -  [ 2e921]  no cipher set
│ │ -  [ 2e92f]  depth exceeded
│ │ -  [ 2e93e]  list error
│ │ -  [ 2e949]  odd number of chars
│ │ -  [ 2e95d]  param of incompatible type
│ │ -  [ 2e978]  too many bytes
│ │ -  [ 2e987]  invalid trinomial basis
│ │ -  [ 2e99f]  invalid cmd number
│ │ -  [ 2e9b2]  connect failure
│ │ -  [ 2e9c2]  error parsing asn1 length
│ │ -  [ 2e9dc]  cms datafinal error
│ │ -  [ 2e9f0]  invalid label
│ │ -  [ 2e9fe]  no matching signature
│ │ -  [ 2ea14]  no private key
│ │ -  [ 2ea23]  bad request id
│ │ -  [ 2ea32]  missing private key for popo
│ │ -  [ 2ea4f]  unsupported pkibody
│ │ -  [ 2ea63]  DESX
│ │ -  [ 2ea68]  NO_VCHECK
│ │ -  [ 2ea72]  crypto/params_dup.c
│ │ -  [ 2ea86]  crypto/provider_child.c
│ │ -  [ 2ea9e]  providers
│ │ -  [ 2eaa8]  crypto/self_test_core.c
│ │ -  [ 2eac0]  nsRenewalUrl
│ │ -  [ 2eacd]  RSA-MDC2
│ │ -  [ 2ead6]  cast5-cbc
│ │ -  [ 2eae0]  nsSGC
│ │ -  [ 2eae6]  PBE-SHA1-RC2-128
│ │ -  [ 2eaf7]  Extension Request
│ │ -  [ 2eb09]  OCSP Signing
│ │ -  [ 2eb16]  id-smime-ct-publishCert
│ │ -  [ 2eb2e]  id-smime-cti-ets-proofOfSender
│ │ -  [ 2eb4d]  md4
│ │ -  [ 2eb51]  id-pkix-mod
│ │ -  [ 2eb5d]  id-mod-kea-profile-88
│ │ -  [ 2eb73]  id-alg-dh-sig-hmac-sha1
│ │ -  [ 2eb8b]  Trust Root
│ │ -  [ 2eb96]  ANSI X9.62
│ │ -  [ 2eba1]  pagerTelephoneNumber
│ │ -  [ 2ebb6]  MIME MHS
│ │ -  [ 2ebbf]  setct-CertResData
│ │ -  [ 2ebd1]  setct-AuthRevResTBEB
│ │ -  [ 2ebe6]  setext-pinAny
│ │ -  [ 2ebf4]  setAttr-PGWYcap
│ │ -  [ 2ec04]  aes-192-cfb1
│ │ -  [ 2ec11]  des-ede3-cfb1
│ │ -  [ 2ec1f]  X509v3 Name Constraints
│ │ -  [ 2ec37]  identified-organization
│ │ -  [ 2ec4f]  c2onb191v5
│ │ -  [ 2ec5a]  policyMappings
│ │ -  [ 2ec69]  CAMELLIA-192-CFB1
│ │ -  [ 2ec7b]  SEED-CBC
│ │ -  [ 2ec84]  HMAC-SHA1
│ │ -  [ 2ec8e]  dsa_with_SHA224
│ │ -  [ 2ec9e]  id-GostR3410-94-CryptoPro-XchB-ParamSet
│ │ -  [ 2ecc6]  Permanent Identifier
│ │ -  [ 2ecdb]  internationaliSDNNumber
│ │ -  [ 2ecf3]  authorityRevocationList
│ │ -  [ 2ed0b]  distinguishedName
│ │ -  [ 2ed1d]  dmdName
│ │ -  [ 2ed25]  id-aes256-GCM
│ │ -  [ 2ed33]  rsassaPss
│ │ -  [ 2ed3d]  AES-128-CBC-HMAC-SHA1
│ │ -  [ 2ed53]  dhSinglePass-cofactorDH-sha384kdf-scheme
│ │ -  [ 2ed7c]  Signing Tool of Issuer
│ │ -  [ 2ed93]  TLS Feature
│ │ -  [ 2ed9f]  Signing KDC Response
│ │ -  [ 2edb4]  auth-gost12
│ │ -  [ 2edc0]  aria-256-ecb
│ │ -  [ 2edcd]  ARIA-192-CFB1
│ │ -  [ 2eddb]  id-dsa-with-sha384
│ │ -  [ 2edee]  ISO CN Member Body
│ │ -  [ 2ee01]  Class of Signing Tool KC3
│ │ -  [ 2ee1b]  id-regCtrl-algId
│ │ -  [ 2ee2c]  sOAIdentifier
│ │ -  [ 2ee3a]  OCSP_RESPONSE
│ │ -  [ 2ee48]  OCSP_RESPDATA
│ │ -  [ 2ee56]  no response data
│ │ -  [ 2ee67]  load_iv
│ │ -  [ 2ee6f]  PKCS12_unpack_authsafes
│ │ -  [ 2ee87]  PBMAC1_PBKDF2_HMAC
│ │ -  [ 2ee9a]  d.data
│ │ -  [ 2eea1]  issuer_and_serial
│ │ -  [ 2eeb3]  unknown operation
│ │ -  [ 2eec5]  too little nonce requested
│ │ -  [ 2eee0]  unable to fetch drbg
│ │ -  [ 2eef5]  RSA_PSS_PARAMS
│ │ -  [ 2ef04]  invalid header
│ │ -  [ 2ef13]  salt length check failed
│ │ -  [ 2ef2c]  ossl_bn_rsa_fips186_4_derive_prime
│ │ -  [ 2ef4f]  reading strings
│ │ -  [ 2ef5f]  exptext
│ │ -  [ 2ef67]  , value=
│ │ -  [ 2ef70]  ,name:
│ │ -  [ 2ef77]  %*sUnknown Qualifier: 
│ │ -  [ 2ef8e]  emailCA
│ │ -  [ 2ef96]  keyCertSign
│ │ -  [ 2efa2]  ca
│ │ -  [ 2efa5]  DIST_POINT_NAME
│ │ -  [ 2efb5]  reasons
│ │ -  [ 2efbd]  Affiliation Changed
│ │ -  [ 2efd1]  distpoint
│ │ -  [ 2efdb]  Reasons
│ │ -  [ 2efe3]  Remove From CRL
│ │ -  [ 2eff3]  IPAddressFamily
│ │ -  [ 2f003]  u.addressesOrRanges
│ │ -  [ 2f017]  ipAddressChoice
│ │ -  [ 2f027]  %*sIPv6
│ │ -  [ 2f02f]  crypto/x509/v3_ac_tgt.c
│ │ -  [ 2f047]  %*scATool      : 
│ │ -  [ 2f059]  namingAuthorityText
│ │ -  [ 2f06d]  language
│ │ -  [ 2f076]  othername: SmtpUTF8Mailbox
│ │ -  [ 2f091]  othername:XmppAddr:%.*s
│ │ -  [ 2f0a9]  copy_email
│ │ -  [ 2f0b4]  ossl_x509_pubkey_hash
│ │ -  [ 2f0ca]  unable to get issuer details
│ │ -  [ 2f0e7]  ok
│ │ -  [ 2f0ea]  unable to decrypt certificate's signature
│ │ -  [ 2f114]  key usage does not include CRL signing
│ │ -  [ 2f13b]  Suite B: invalid ECC curve
│ │ -  [ 2f156]  CA cert does not include key usage extension
│ │ -  [ 2f183]  set
│ │ -  [ 2f187]  X509_NAME
│ │ -  [ 2f191]  public_key
│ │ -  [ 2f19c]  x509_pubkey_ex_d2i_ex
│ │ -  [ 2f1b2]  mem alloc failed
│ │ -  [ 2f1c3]  -ENOMEM ( code 
│ │ -  [ 2f1d3]  provider=base,fips=no,output=blob
│ │ -  [ 2f1f5]  provider=base,fips=yes,input=der,structure=rsa
│ │ -  [ 2f224]  provider=base,fips=yes,input=pem
│ │ -  [ 2f245]  OpenSSL SM2 implementation
│ │ -  [ 2f260]  DSA-SHA2-256:DSA-SHA256:dsa_with_SHA256:2.16.840.1.101.3.4.3.2
│ │ -  [ 2f29f]  DSA-SHA3-512:dsa_with_SHA3-512:id-dsa-with-sha3-512:2.16.840.1.101.3.4.3.8
│ │ -  [ 2f2ea]  provider=default,fips=yes,output=der,structure=type-specific
│ │ -  [ 2f327]  provider=default,fips=yes,output=pem,structure=dsa
│ │ -  [ 2f35a]  AES-128-WRAP-INV:AES128-WRAP-INV
│ │ -  [ 2f37b]  ARIA-128-OFB:1.2.410.200046.1.1.4
│ │ -  [ 2f39d]  ARIA-128-CTR:1.2.410.200046.1.1.5
│ │ -  [ 2f3bf]  DES-EDE3-CBC:DES3:1.2.840.113549.3.7
│ │ -  [ 2f3e4]  x25519
│ │ -  [ 2f3eb]  chacha20_poly1305_set_ctx_params
│ │ -  [ 2f40c]  ossl_b2i_RSA_after_header
│ │ -  [ 2f426]  prepare_ec_params
│ │ -  [ 2f438]  ec_to_SubjectPublicKeyInfo_pem_encode
│ │ -  [ 2f45e]  dhx_to_DHX_der_encode
│ │ -  [ 2f474]  ec_to_X9_62_der_encode
│ │ -  [ 2f48b]  providers/implementations/encode_decode/encode_key2ms.c
│ │ -  [ 2f4c3]  SEED:
│ │ -  [ 2f4c9]  dh_set_ctx_params
│ │ -  [ 2f4db]  sk
│ │ -  [ 2f4de]  providers/implementations/kem/rsa_kem.c
│ │ -  [ 2f506]  d-rounds
│ │ -  [ 2f50f]  kat
│ │ -  [ 2f513]  eddsa_dupctx
│ │ -  [ 2f520]  the EdDSA instance is preset, you may not try to specify it
│ │ -  [ 2f55c]  Ed25519ctx
│ │ -  [ 2f567]  MGF1 hash algorithm name too long
│ │ -  [ 2f589]  minimum salt length: %d, actual salt length: %d
│ │ -  [ 2f5b9]  rsa_signverify_message_update
│ │ -  [ 2f5d7]  sm2sig_set_mdname
│ │ -  [ 2f5e9]  providers/common/der/der_rsa_key.c
│ │ -  [ 2f60c]  parent cannot supply entropy seed
│ │ -  [ 2f62e]  ossl_cipher_generic_set_ctx_params
│ │ -  [ 2f651]  ossl_ccm_get_ctx_params
│ │ -  [ 2f669]  ypt-only
│ │ -  [ 2f672]  tion
│ │ -  [ 2f677]  m_mac
│ │ -  [ 2f67d]  lti
│ │ -  [ 2f681]  c-bits
│ │ -  [ 2f688]  ms-check
│ │ -  [ 2f691]  2kdf-key-check
│ │ -  [ 2f6a0]  d4
│ │ -  [ 2f6a3]  d17
│ │ -  [ 2f6a7]  TLS_DH_anon_WITH_AES_128_CBC_SHA256
│ │ -  [ 2f6cb]  TLS_DHE_DSS_WITH_AES_256_GCM_SHA384
│ │ -  [ 2f6ef]  TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
│ │ -  [ 2f717]  ECDHE-ECDSA-AES256-GCM-SHA384
│ │ -  [ 2f735]  TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
│ │ -  [ 2f75d]  SRP-AES-256-CBC-SHA
│ │ -  [ 2f771]  TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
│ │ -  [ 2f79a]  TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
│ │ -  [ 2f7c7]  TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
│ │ -  [ 2f7f0]  ARIA256-GCM-SHA384
│ │ -  [ 2f803]  ECDHE-ECDSA-ARIA256-GCM-SHA384
│ │ -  [ 2f822]  time
│ │ -  [ 2f827]  %s/%s
│ │ -  [ 2f82d]  GOST89
│ │ -  [ 2f834]  GOST89MAC
│ │ -  [ 2f83e]  binder does not verify
│ │ -  [ 2f855]  certificate verify failed
│ │ -  [ 2f86f]  cert cb error
│ │ -  [ 2f87d]  dane tlsa bad certificate
│ │ -  [ 2f897]  empty raw public key
│ │ -  [ 2f8ac]  fragmented client hello
│ │ -  [ 2f8c4]  invalid config
│ │ -  [ 2f8d3]  length too long
│ │ -  [ 2f8e3]  can't find SRP server param
│ │ -  [ 2f8ff]  record length mismatch
│ │ -  [ 2f916]  remote peer address not set
│ │ -  [ 2f932]  scsv received when renegotiating
│ │ -  [ 2f953]  ssl3 session id too long
│ │ -  [ 2f96c]  ssl/tls alert illegal parameter
│ │ -  [ 2f98c]  no_etm
│ │ -  [ 2f993]  ciphersuites
│ │ -  [ 2f9a0]  NoRenegotiation
│ │ -  [ 2f9b0]  tls1_set_groups
│ │ -  [ 2f9c0]  add_provider_groups
│ │ -  [ 2f9d4]  PSS
│ │ -  [ 2f9d8]  ossl_quic_channel_on_new_conn_id
│ │ -  [ 2f9f9]  bad transport parameter
│ │ -  [ 2fa11]  max_udp_payload_size
│ │ -  [ 2fa26]  server
│ │ -  [ 2fa2d]  title
│ │ -  [ 2fa33]  reason
│ │ -  [ 2fa3a]  closing
│ │ -  [ 2fa42]  reset_stream
│ │ -  [ 2fa4f]  STREAM valid only in 0/1-RTT
│ │ -  [ 2fa6c]  MAX_DATA valid only in 0/1-RTT
│ │ -  [ 2fa8b]  CONN_CLOSE (APP) valid only in 0/1-RTT
│ │ -  [ 2fab2]  STOP_SENDING frame for RX only stream
│ │ -  [ 2fad8]  read_ahead
│ │ -  [ 2fae3]  ssl/record/methods/tls13_meth.c
│ │ -  [ 2fb03]  final_ec_pt_formats
│ │ -  [ 2fb17]  No groups enabled for max supported SSL/TLS version
│ │ -  [ 2fb4b]  tls_construct_ctos_use_srtp
│ │ -  [ 2fb67]  tls_parse_ctos_supported_groups
│ │ -  [ 2fb87]  tls_construct_client_hello
│ │ -  [ 2fba2]  pub
│ │ -  [ 2fba6]  crypto/asn1/a_object.c
│ │ -  [ 2fbbd]  i2a_ASN1_OBJECT
│ │ -  [ 2fbcd]  EXTERNAL
│ │ -  [ 2fbd6]  NUMERICSTRING
│ │ -  [ 2fbe4]  VIDEOTEXSTRING
│ │ -  [ 2fbf3]  :BAD ENUMERATED
│ │ -  [ 2fc03]  ossl_d2i_PrivateKey_legacy
│ │ -  [ 2fc1e]  ASN1_ANY
│ │ -  [ 2fc27]  ASN1_PRINTABLE
│ │ -  [ 2fc36]  ASN1_SET_ANY
│ │ -  [ 2fc43]  UINT32
│ │ -  [ 2fc4a]  ZUINT64
│ │ -  [ 2fc52]  crypto/async/async.c
│ │ -  [ 2fc67]  crypto/bio/bf_buff.c
│ │ -  [ 2fc7c]  malformed host or service
│ │ -  [ 2fc96]  transfer timeout
│ │ -  [ 2fca7]  %09u
│ │ -  [ 2fcac]  crypto/asn1/tasn_prn.c
│ │ -  [ 2fcc3]   (%s)
│ │ -  [ 2fcc9]  EMPTY
│ │ -  [ 2fccf]  PBKDF2PARAM
│ │ -  [ 2fcdb]  NCONF_new_ex
│ │ -  [ 2fce8]  module=%s, value=%s retcode=%-8d
│ │ -  [ 2fd09]  do_init_module_list_lock
│ │ -  [ 2fd22]  UTF8
│ │ -  [ 2fd27]  IMP
│ │ -  [ 2fd2b]  DSO_merge
│ │ -  [ 2fd35]  ec_pkey_param_check
│ │ -  [ 2fd49]  ECPKPARAMETERS
│ │ -  [ 2fd58]  p.tpBasis
│ │ -  [ 2fd62]  ec_asn1_group2fieldid
│ │ -  [ 2fd78]  explicit
│ │ -  [ 2fd81]  named-nist
│ │ -  [ 2fd8c]  NIST/SECG/WTLS curve over a 233 bit binary field
│ │ -  [ 2fdbd]  EC_KEY_oct2priv
│ │ -  [ 2fdcd]  Prime:
│ │ -  [ 2fdd4]  Order: 
│ │ -  [ 2fddc]  ossl_ecx_key_op
│ │ -  [ 2fdec]  ossl_decoder_instance_dup
│ │ -  [ 2fe06]  ENGINE_set_default_string
│ │ -  [ 2fe20]  ENGINE_finish
│ │ -  [ 2fe2e]  ENGINE_pkey_asn1_find_str
│ │ -  [ 2fe48]  ENGINE_get_digest
│ │ -  [ 2fe5a]  crypto/err/err_blocks.c
│ │ -  [ 2fe72]  secp256k1
│ │ -  [ 2fe7c]  B-571
│ │ -  [ 2fe82]  EVP_EncryptUpdate
│ │ -  [ 2fe94]  aead
│ │ -  [ 2fe99]  ossl_encoder_instance_new
│ │ -  [ 2feb3]  EVP_DigestSign
│ │ -  [ 2fec2]  evp_mac_from_algorithm
│ │ -  [ 2fed9]  assertion failed: keylen <= sizeof(key)
│ │ -  [ 2ff01]  encoded-pub-key
│ │ -  [ 2ff11]  EXTRACT_ONLY
│ │ -  [ 2ff1e]  SCRYPT
│ │ -  [ 2ff25]  EVP_PKEY_CTX_dup
│ │ -  [ 2ff36]  pkey_dh_derive
│ │ -  [ 2ff45]  pkey_dh_ctrl_str
│ │ -  [ 2ff56]  dsa_paramgen_check
│ │ -  [ 2ff69]  validate-pq
│ │ -  [ 2ff75]  called with even modulus
│ │ -  [ 2ff8e]  unknown pbe algorithm
│ │ -  [ 2ffa4]  invalid utf8string
│ │ -  [ 2ffb7]  missing equal sign
│ │ -  [ 2ffca]  i2d ecpkparameters failure
│ │ -  [ 2ffe5]  invalid generator
│ │ -  [ 2fff7]  point is not on curve
│ │ -  [ 3000d]  undefined order
│ │ -  [ 3001d]  already loaded
│ │ -  [ 3002c]  error sending
│ │ -  [ 3003a]  invalid port number
│ │ -  [ 3004e]  no receipt request
│ │ -  [ 30061]  certificate not accepted
│ │ -  [ 3007a]  error setting certhash
│ │ -  [ 30091]  DES
│ │ -  [ 30095]  rc2-40
│ │ -  [ 3009c]  assertion failed: list >= 0 && list < sh.freelist_size
│ │ -  [ 300d3]  ossl_hexstr2buf_sep
│ │ -  [ 300e7]  ossl_param_build_set_bn_pad
│ │ -  [ 30103]  provider_conf_load
│ │ -  [ 30116]  identity
│ │ -  [ 3011f]  ON
│ │ -  [ 30122]  name=%s, provider has no provider init function
│ │ -  [ 30152]  shaWithRSAEncryption
│ │ -  [ 30167]  X509v3 Subject Key Identifier
│ │ -  [ 30185]  BF-CFB
│ │ -  [ 3018c]  givenName
│ │ -  [ 30196]  DSA-SHA1
│ │ -  [ 3019f]  id-smime-aa-dvcs-dvc
│ │ -  [ 301b4]  id-smime-cti-ets-proofOfDelivery
│ │ -  [ 301d5]  id-mod-cmp2000
│ │ -  [ 301e4]  qcStatements
│ │ -  [ 301f1]  dvcs
│ │ -  [ 301f6]  id-cct-PKIResponse
│ │ -  [ 30209]  noCheck
│ │ -  [ 30211]  Management
│ │ -  [ 3021c]  DC
│ │ -  [ 3021f]  holdInstructionReject
│ │ -  [ 30235]  domainRelatedObject
│ │ -  [ 30249]  id-hex-multipart-message
│ │ -  [ 30262]  set-attr
│ │ -  [ 3026b]  setct-AuthRevReqBaggage
│ │ -  [ 30283]  setct-AuthTokenTBE
│ │ -  [ 30296]  setct-CapRevReqTBEX
│ │ -  [ 302aa]  setct-CredReqTBEX
│ │ -  [ 302bc]  setct-CertReqTBEX
│ │ -  [ 302ce]  merchant initiated auth
│ │ -  [ 302e6]  set-addPolicy
│ │ -  [ 302f4]  cleartext track 2
│ │ -  [ 30306]  aes-256-cfb8
│ │ -  [ 30313]  proxyCertInfo
│ │ -  [ 30321]  wap-wsg
│ │ -  [ 30329]  camellia-192-cfb
│ │ -  [ 3033a]  gost89-cnt
│ │ -  [ 30345]  CMAC
│ │ -  [ 3034a]  kuznyechik-ofb
│ │ -  [ 30359]  chacha20
│ │ -  [ 30362]  auth-srp
│ │ -  [ 3036b]  id-smime-ct-contentCollection
│ │ -  [ 30389]  ARIA-256-CTR
│ │ -  [ 30396]  id-hmacWithSHA3-256
│ │ -  [ 303aa]  magma-ctr-acpkm-omac
│ │ -  [ 303bf]  gmac
│ │ -  [ 303c4]  AES-256-SIV
│ │ -  [ 303d0]  Class of Signing Tool KB2
│ │ -  [ 303ea]  sm4-ccm
│ │ -  [ 303f2]  Brotli compression
│ │ -  [ 30405]  OCSP_SINGLERESP
│ │ -  [ 30415]  responseType
│ │ -  [ 30422]  value.unknown
│ │ -  [ 30430]  responses
│ │ -  [ 3043a]  digest name err
│ │ -  [ 3044a]  missing ocspsigning usage
│ │ -  [ 30464]  DEK-Info:
│ │ -  [ 3046e]  PRIVATE KEY
│ │ -  [ 3047a]  CMS
│ │ -  [ 3047e]  PKCS12
│ │ -  [ 30485]  pkcs12_gen_mac
│ │ -  [ 30494]  invalid type
│ │ -  [ 304a1]  PKCS7_SIGNED
│ │ -  [ 304ae]  evp_rand_from_algorithm
│ │ -  [ 304c6]  saltLength
│ │ -  [ 304d1]  algorithm mismatch
│ │ -  [ 304e4]  digest too big for rsa key
│ │ -  [ 304ff]  crypto/rsa/rsa_gen.c
│ │ -  [ 30514]  rsa_ossl_private_encrypt
│ │ -  [ 3052d]  RSA_padding_check_PKCS1_OAEP_mgf1
│ │ -  [ 3054f]  ossl_rsa_padding_check_PKCS1_type_2
│ │ -  [ 30573]  ossl_rsa_prf
│ │ -  [ 30580]  SHA2-512
│ │ -  [ 30589]  ossl_rsa_sp800_56b_pairwise_test
│ │ -  [ 305aa]  error verifying pkcs12 mac
│ │ -  [ 305c5]  unsupported search type
│ │ -  [ 305dd]  ossl_store_handle_load_result
│ │ -  [ 305fb]  flushing
│ │ -  [ 30604]  POLICYINFO
│ │ -  [ 3060f]  crypto/x509/v3_ia5.c
│ │ -  [ 30624]  %*scrlNum: 
│ │ -  [ 30630]  IPv4-SAFI
│ │ -  [ 3063a]  crypto/ct/ct_x509v3.c
│ │ -  [ 30650]  signTool
│ │ -  [ 30659]  namingAuthorityId
│ │ -  [ 3066b]  %*s  Profession Info Entry %0d:\n
│ │ -  [ 3068c]  process_pci_value
│ │ -  [ 3069e]  v2i_POLICY_MAPPINGS
│ │ -  [ 306b2]  OCSP helper
│ │ -  [ 306be]  othername: NAIRealm
│ │ -  [ 306d2]  invalid multiple rdns
│ │ -  [ 306e8]  CRL path validation error
│ │ -  [ 30702]  OCSP verification needed
│ │ -  [ 3071b]  Path length invalid for non-CA cert
│ │ -  [ 3073f]  Using cert extension requires at least X509v3
│ │ -  [ 3076d]  x509_verify_x509
│ │ -  [ 3077e]  X509_NAME_add_entry
│ │ -  [ 30792]  %*s%.*s
│ │ -  [ 3079a]  (COULD NOT DECODE DISTINGUISHED NAME)\n
│ │ -  [ 307c1]  X509_NAME_ENTRIES
│ │ -  [ 307d3]  X509_PUBKEY_get
│ │ -  [ 307e3]  crypto/x509/x_x509.c
│ │ -  [ 307f8]  ALG_PERR: %s(%d): Failed to set socket option : 
│ │ -  [ 30829]  provider=base,fips=yes,input=der,structure=dsa
│ │ -  [ 30858]  SHA3-256:2.16.840.1.101.3.4.2.8
│ │ -  [ 30878]  AES-128-ECB:2.16.840.1.101.3.4.1.1
│ │ -  [ 3089b]  ARIA-192-GCM:1.2.410.200046.1.1.35
│ │ -  [ 308be]  BIO to Core filter
│ │ -  [ 308d1]  SHA-1
│ │ -  [ 308d7]  rsa_get_ctx_params
│ │ -  [ 308ea]  aes_cbc_cts_set_ctx_params
│ │ -  [ 30905]  DSA PARAMETERS
│ │ -  [ 30914]  dh_to_EncryptedPrivateKeyInfo_der_encode
│ │ -  [ 3093d]  dh_spki_pub_to_der
│ │ -  [ 30950]  dsa_to_EncryptedPrivateKeyInfo_pem_encode
│ │ -  [ 3097a]  ed25519_to_PrivateKeyInfo_pem_encode
│ │ -  [ 3099f]  x25519_to_EncryptedPrivateKeyInfo_der_encode
│ │ -  [ 309cc]    Minimum Salt Length: %d%s\n
│ │ -  [ 309e9]  kdf_argon2i_new
│ │ -  [ 309f9]  constant
│ │ -  [ 30a02]  dsa_precheck_params
│ │ -  [ 30a16]  crypto/sm2/sm2_key.c
│ │ -  [ 30a2b]  ecx_gen
│ │ -  [ 30a33]  encode_string
│ │ -  [ 30a41]  get_parent_reseed_count
│ │ -  [ 30a59]  ed25519_verify
│ │ -  [ 30a68]  ed448_verify
│ │ -  [ 30a75]  Cannot use autodetected salt length
│ │ -  [ 30a99]  rsa_verify_message_final
│ │ -  [ 30ab2]  invalid aad
│ │ -  [ 30abe]  ossl_ccm_set_ctx_params
│ │ -  [ 30ad6]  rly_clean
│ │ -  [ 30ae0]  ine
│ │ -  [ 30ae4]  _padding
│ │ -  [ 30aed]  erivation_function
│ │ -  [ 30b00]  tm
│ │ -  [ 30b03]  _Unwind_Resume() can't return
│ │ -  [ 30b21]  ProcessDescriptors
│ │ -  [ 30b34]  dtls1_check_timeout_num
│ │ -  [ 30b4c]  TLS_CHACHA20_POLY1305_SHA256
│ │ -  [ 30b69]  NULL-MD5
│ │ -  [ 30b72]  TLS_DHE_DSS_WITH_AES_128_CBC_SHA
│ │ -  [ 30b93]  TLS_DHE_DSS_WITH_AES_256_CBC_SHA
│ │ -  [ 30bb4]  NULL-SHA256
│ │ -  [ 30bc0]  ADH-AES128-GCM-SHA256
│ │ -  [ 30bd6]  AES128-CCM8
│ │ -  [ 30be2]  TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8
│ │ -  [ 30c05]  TLS_ECDHE_ECDSA_WITH_NULL_SHA
│ │ -  [ 30c23]  ECDHE-ECDSA-AES256-SHA
│ │ -  [ 30c3a]  TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
│ │ -  [ 30c60]  TLS_RSA_PSK_WITH_AES_256_GCM_SHA384
│ │ -  [ 30c84]  SRP-RSA-AES-256-CBC-SHA
│ │ -  [ 30c9c]  TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
│ │ -  [ 30cc5]  ADH-CAMELLIA256-SHA256
│ │ -  [ 30cdc]  TLS_DH_anon_WITH_CAMELLIA_128_CBC_SHA
│ │ -  [ 30d02]  gost-mac-12
│ │ -  [ 30d0e]  TLSv1.0
│ │ -  [ 30d16]  RC4
│ │ -  [ 30d1a]  bad ecc cert
│ │ -  [ 30d27]  library has no ciphers
│ │ -  [ 30d3e]  unknown cipher returned
│ │ -  [ 30d56]  wrong signature size
│ │ -  [ 30d6b]  no_legacy_server_connect
│ │ -  [ 30d84]  sigalgs
│ │ -  [ 30d8c]  SSL_use_PrivateKey_file
│ │ -  [ 30da4]  ssl_srp_ctx_init_intern
│ │ -  [ 30dbc]  RETRY_SCID sent when not performing a retry
│ │ -  [ 30de8]  INITIAL_MAX_STREAMS_UNI appears multiple times
│ │ -  [ 30e17]  INITIAL_SCID was not sent but is required
│ │ -  [ 30e41]  RETRY_SCID was not sent but is required
│ │ -  [ 30e69]  preferred_addr
│ │ -  [ 30e78]  port_v4
│ │ -  [ 30e80]  ch_rxku_tick
│ │ -  [ 30e8d]  packet header reserved bits
│ │ -  [ 30ea9]  unidirectional
│ │ -  [ 30eb8]  ChaCha20-Poly1305
│ │ -  [ 30eca]  HANDSHAKE_DONE valid only in 1-RTT
│ │ -  [ 30eed]  depack_do_frame_reset_stream
│ │ -  [ 30f0a]  depack_do_frame_handshake_done
│ │ -  [ 30f29]  quic_increment_sequence_ctr
│ │ -  [ 30f45]  STREAM
│ │ -  [ 30f4c]  STREAM_STATE_ERROR
│ │ -  [ 30f5f]  CONNECTION_ID_LIMIT_ERROR
│ │ -  [ 30f79]  APPLICATION_ERROR
│ │ -  [ 30f8b]  use_etm
│ │ -  [ 30f93]  tls-mac
│ │ -  [ 30f9b]  rlayer_early_data_count_ok
│ │ -  [ 30fb6]  tls13_validate_record_header
│ │ -  [ 30fd3]  tls_construct_ctos_server_name
│ │ -  [ 30ff2]  tls_construct_stoc_psk
│ │ -  [ 31009]  read_state_machine
│ │ -  [ 3101c]  ossl_statem_client_post_process_message
│ │ -  [ 31044]  crypto/asn1/a_strex.c
│ │ -  [ 3105a]  asn1_collect
│ │ -  [ 31067]  asn1_item_embed_new
│ │ -  [ 3107b]  DIRECTORYSTRING
│ │ -  [ 3108b]  crypto/asn1/tasn_utl.c
│ │ -  [ 310a2]  no hostname or service specified
│ │ -  [ 310c3]  transfer error
│ │ -  [ 310d2]  unable to reuseaddr
│ │ -  [ 310e6]  unsupported method
│ │ -  [ 310f9]  BIO_ctrl
│ │ -  [ 31102]  bio_write_intern
│ │ -  [ 31113]  0123456789ABCDEF
│ │ -  [ 31124]  <ABSENT>\n
│ │ -  [ 3112e]  encryption
│ │ -  [ 31139]  NCONF_get_string
│ │ -  [ 3114a]  crypto/conf/conf_mod.c
│ │ -  [ 31161]  BITSTRING
│ │ -  [ 3116b]  SCT_CTX_verify
│ │ -  [ 3117a]   (Negative)
│ │ -  [ 31186]  named
│ │ -  [ 3118c]  generator
│ │ -  [ 31196]  NIST/SECG/WTLS curve over a 163 bit binary field
│ │ -  [ 311c7]  RFC 5639 curve over a 384 bit prime field
│ │ -  [ 311f1]  ossl_ec_GF2m_simple_group_set_curve
│ │ -  [ 31215]  ossl_ec_key_simple_priv2oct
│ │ -  [ 31231]  EC_GROUP_get_curve
│ │ -  [ 31244]  EC_GROUP_get_degree
│ │ -  [ 31258]  EC_POINT_mul
│ │ -  [ 31265]  ossl_ecdsa_sign_sig
│ │ -  [ 31279]  ossl_ecdsa_verify_sig
│ │ -  [ 3128f]  crypto/ec/ecdsa_vrf.c
│ │ -  [ 312a5]  ecp_nistz256_points_mul
│ │ -  [ 312bd]  crypto/ec/ecp_smpl.c
│ │ -  [ 312d2]  ecx_generic_import_from
│ │ -  [ 312ea]  pkey_ecd_digestsign448
│ │ -  [ 31301]  OSSL_DECODER_CTX_set_selection
│ │ -  [ 31320]  input
│ │ -  [ 31326]  readbuffer
│ │ -  [ 31331]  ossl_decoder_get_number
│ │ -  [ 31349]  %s, Name (%s : %d), Properties (%s)
│ │ -  [ 3136d]  init
│ │ -  [ 31372]  crypto/engine/eng_list.c
│ │ -  [ 3138b]  DIR_LOAD
│ │ -  [ 31394]  1
│ │ -  [ 31396]  time stamp routines
│ │ -  [ 313aa]  crypto/evp/asymcipher.c
│ │ -  [ 313c2]  aes_ocb_cipher
│ │ -  [ 313d1]  c2pnb304w1
│ │ -  [ 313dc]  assertion failed: ctx->length <= (int)sizeof(ctx->enc_data)
│ │ -  [ 31418]  randkey
│ │ -  [ 31420]  has-randkey
│ │ -  [ 3142c]  num
│ │ -  [ 31430]  OSSL_ENCODER_CTX_set_params
│ │ -  [ 3144c]  seterr
│ │ -  [ 31453]  crypto/evp/exchange.c
│ │ -  [ 31469]  EVP_DigestSignFinal
│ │ -  [ 3147d]  EVP_DigestVerify
│ │ -  [ 3148e]  PKCS5_pbe_set_ex
│ │ -  [ 3149f]  dh_rfc5114
│ │ -  [ 314aa]  pkcs1
│ │ -  [ 314b0]  get_payload_private_key
│ │ -  [ 314c8]  EVP_PKEY_verify
│ │ -  [ 314d8]  crypto/comp_methods.c
│ │ -  [ 314ee]  /home/vagrant/build/alt.nainapps.sharepaste.fdroid/rust/target/armv7-linux-androideabi/release/build/openssl-sys-d039a4a9eb3ff645/out/openssl-build/install/lib/ossl-modules
│ │ -  [ 3159b]  bad q value
│ │ -  [ 315a7]  header too long
│ │ -  [ 315b7]  nested too deep
│ │ -  [ 315c7]  module initialization error
│ │ -  [ 315e3]  insufficient data space
│ │ -  [ 315fb]  invalid group order
│ │ -  [ 3160f]  invalid p
│ │ -  [ 31619]  point coordinates blind failure
│ │ -  [ 31639]  add signer error
│ │ -  [ 3164a]  cms lib
│ │ -  [ 31652]  ess signing certid mismatch error
│ │ -  [ 31674]  not supported for this key type
│ │ -  [ 31694]  no content
│ │ -  [ 3169f]  no key or cert
│ │ -  [ 316ae]  malformed iv
│ │ -  [ 316bb]  popo raverified not accepted
│ │ -  [ 316d8]  generate certreqtemplate
│ │ -  [ 316f1]  sm4
│ │ -  [ 316f5]  aes128-wrap-pad
│ │ -  [ 31705]  id-aes192-wrap-pad
│ │ -  [ 31718]  ARIA-192-CBC
│ │ -  [ 31725]  hexstr2buf_sep
│ │ -  [ 31734]  OSSL_PARAM_set_utf8_ptr
│ │ -  [ 3174c]  unsigned_from_signed
│ │ -  [ 31761]  set_string_internal
│ │ -  [ 31775]  organizationalUnitName
│ │ -  [ 3178c]  des-cfb
│ │ -  [ 31794]  nsCertType
│ │ -  [ 3179f]  PKIX
│ │ -  [ 317a4]  ISO
│ │ -  [ 317a8]  id-on
│ │ -  [ 317ae]  ipsecEndSystem
│ │ -  [ 317bd]  id-regInfo-certReq
│ │ -  [ 317d0]  id-cmc-identification
│ │ -  [ 317e6]  id-cmc-transactionId
│ │ -  [ 317fb]  id-cmc-revokeRequest
│ │ -  [ 31810]  id-cmc-popLinkWitness
│ │ -  [ 31826]  caseIgnoreIA5StringSyntax
│ │ -  [ 31840]  associatedDomain
│ │ -  [ 31851]  setct-CardCInitResTBS
│ │ -  [ 31867]  msSmartcardLogin
│ │ -  [ 31878]  AES-192-CFB1
│ │ -  [ 31885]  id-ppl-anyLanguage
│ │ -  [ 31898]  sha384WithRSAEncryption
│ │ -  [ 318b0]  sha224WithRSAEncryption
│ │ -  [ 318c8]  camellia-192-cfb8
│ │ -  [ 318da]  id-DHBasedMac
│ │ -  [ 318e8]  deltaRevocationList
│ │ -  [ 318fc]  RSASSA-PSS
│ │ -  [ 31907]  dhSinglePass-stdDH-sha1kdf-scheme
│ │ -  [ 31929]  camellia-192-cmac
│ │ -  [ 3193b]  md_gost12_256
│ │ -  [ 31949]  id-tc26-hmac-gost-3411-2012-512
│ │ -  [ 31969]  aria-192-cbc
│ │ -  [ 31976]  ARIA-256-OFB
│ │ -  [ 31983]  SHA3-512
│ │ -  [ 3198c]  SHAKE128
│ │ -  [ 31995]  dstu28147
│ │ -  [ 3199f]  DSTU curve 1
│ │ -  [ 319ac]  DSTU curve 4
│ │ -  [ 319b9]  id-tc26-cipher-gostr3412-2015-kuznyechik
│ │ -  [ 319e2]  id-tc26-gost-3410-2012-256-paramSetD
│ │ -  [ 31a07]  aes-256-siv
│ │ -  [ 31a13]  kx-gost18
│ │ -  [ 31a1d]  X509v3 Alternative Signature Algorithm
│ │ -  [ 31a44]  Hardware Module Name
│ │ -  [ 31a59]  not encrypted
│ │ -  [ 31a67]  PKCS #7 SIGNED DATA
│ │ -  [ 31a7b]  get_name
│ │ -  [ 31a84]  PKCS7_dataInit
│ │ -  [ 31a93]  cipher not initialized
│ │ -  [ 31aaa]  content and data present
│ │ -  [ 31ac3]  unable to find message digest
│ │ -  [ 31ae1]  not an ascii character
│ │ -  [ 31af8]  BN_BLINDING_new
│ │ -  [ 31b08]  data too small for key size
│ │ -  [ 31b24]  invalid pss parameters
│ │ -  [ 31b3b]  unknown padding type
│ │ -  [ 31b50]  8192
│ │ -  [ 31b55]  cannot find config variable
│ │ -  [ 31b71]  OpenSSL default user interface
│ │ -  [ 31b90]  NOTICEREF
│ │ -  [ 31b9a]  %*sExplicit Text: %.*s
│ │ -  [ 31bb1]  Object Signing
│ │ -  [ 31bc0]  keyEncipherment
│ │ -  [ 31bd0]  %*s<EMPTY>\n
│ │ -  [ 31bdc]  ASIdentifierChoice_canonize
│ │ -  [ 31bf8]  targetName
│ │ -  [ 31c03]  certDigestInfo
│ │ -  [ 31c13]  %*sTimestamp : 
│ │ -  [ 31c23]  namingAuthorityUrl
│ │ -  [ 31c36]  Not Before: 
│ │ -  [ 31c43]  crlsign
│ │ -  [ 31c4b]  crypto/x509/v3_san.c
│ │ -  [ 31c60]  copy_issuer
│ │ -  [ 31c6c]  user
│ │ -  [ 31c71]  crypto/x509/v3_tlsf.c
│ │ -  [ 31c87]  i2s_ASN1_INTEGER
│ │ -  [ 31c98]  self-signed certificate
│ │ -  [ 31cb0]  Suite B: invalid signature algorithm
│ │ -  [ 31cd5]  %*sFALSE
│ │ -  [ 31cde]  %*s<Unsupported tag %d>
│ │ -  [ 31cf6]  validity
│ │ -  [ 31cff]  socket bind failed
│ │ -  [ 31d12]  provider=base,fips=yes,output=der,structure=EncryptedPrivateKeyInfo
│ │ -  [ 31d56]  provider=base,fips=yes,output=der,structure=ec
│ │ -  [ 31d85]  ARGON2ID
│ │ -  [ 31d8e]  provider=default,fips=yes,output=der,structure=X9.62
│ │ -  [ 31dc3]  provider=default,fips=yes,input=msblob
│ │ -  [ 31dea]  provider=default,fips=no,input=der,structure=type-specific
│ │ -  [ 31e25]  ARIA-256-CCM:1.2.410.200046.1.1.39
│ │ -  [ 31e48]  DES3-WRAP:id-smime-alg-CMS3DESwrap:1.2.840.113549.1.9.16.3.6
│ │ -  [ 31e85]  providers/implementations/ciphers/cipher_aes_gcm_siv.c
│ │ -  [ 31ebc]  aes_ocb_set_ctx_params
│ │ -  [ 31ed3]  providers/implementations/ciphers/cipher_null.c
│ │ -  [ 31f03]  DH PUBLIC KEY
│ │ -  [ 31f11]  ec_to_PrivateKeyInfo_der_encode
│ │ -  [ 31f31]  x448_to_EncryptedPrivateKeyInfo_pem_encode
│ │ -  [ 31f5c]  rsapss_to_PKCS1_pem_encode
│ │ -  [ 31f77]  Q:   
│ │ -  [ 31f7d]  providers/implementations/kdfs/kbkdf.c
│ │ -  [ 31fa4]  sskdf_size
│ │ -  [ 31faf]  AES-256-WRAP
│ │ -  [ 31fbc]  ossl_kdf_ctx_create
│ │ -  [ 31fd0]  crypto/dsa/dsa_check.c
│ │ -  [ 31fe7]  ec_gen_assign_group
│ │ -  [ 31ffb]  providers/implementations/macs/gmac_prov.c
│ │ -  [ 32026]  ecdsa_signverify_init
│ │ -  [ 3203c]  crypto/sm2/sm2_sign.c
│ │ -  [ 32052]  cipher operation failed
│ │ -  [ 3206a]  missing config data
│ │ -  [ 3207e]  missing session id
│ │ -  [ 32091]  oneshot call out of order
│ │ -  [ 320ab]  c
│ │ -  [ 320ad]  ssl-version
│ │ -  [ 320b9]  erties
│ │ -  [ 320c0]  hase
│ │ -  [ 320c5]  lient-version
│ │ -  [ 320d3]  eybits
│ │ -  [ 320da]  s7
│ │ -  [ 320dd]  d22
│ │ -  [ 320e1]  DHE-DSS-AES128-SHA
│ │ -  [ 320f4]  DHE-RSA-AES128-CCM
│ │ -  [ 32107]  RSA-PSK-AES128-CBC-SHA
│ │ -  [ 3211e]  SRP-DSS-AES-256-CBC-SHA
│ │ -  [ 32136]  TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
│ │ -  [ 3215b]  TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
│ │ -  [ 32181]  ADH-CAMELLIA128-SHA
│ │ -  [ 32195]  TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
│ │ -  [ 321c0]  TLS_RSA_WITH_ARIA_128_GCM_SHA256
│ │ -  [ 321e1]  TLS_DHE_PSK_WITH_ARIA_128_GCM_SHA256
│ │ -  [ 32206]  ssl_server
│ │ -  [ 32211]  IDEA
│ │ -  [ 32216]  ARIA128
│ │ -  [ 3221e]  ca dn length mismatch
│ │ -  [ 32234]  dane tlsa bad matching type
│ │ -  [ 32250]  data between ccs and finished
│ │ -  [ 3226e]  maximum encrypted pkts reached
│ │ -  [ 3228d]  no shared signature algorithms
│ │ -  [ 322ac]  no verify cookie callback
│ │ -  [ 322c6]  old session compression algorithm not returned
│ │ -  [ 322f5]  srtp could not allocate profiles
│ │ -  [ 32316]  tlsv1 alert user cancelled
│ │ -  [ 32331]  automatic
│ │ -  [ 3233b]  No valid groups in '%s'
│ │ -  [ 32353]  tls1_set_server_sigalgs
│ │ -  [ 3236b]  AES-256-CBC
│ │ -  [ 32377]  rsa_pkcs1_sha384
│ │ -  [ 32388]  data
│ │ -  [ 3238d]  failed to start channel
│ │ -  [ 323a5]  handshake cannot be confirmed before it is completed
│ │ -  [ 323da]  ORIG_DCID may not be sent by a client
│ │ -  [ 32400]  INITIAL_SCID is malformed
│ │ -  [ 3241a]  forgery limit
│ │ -  [ 32428]  initial_source_connection_id
│ │ -  [ 32445]  key update
│ │ -  [ 32450]  application_error
│ │ -  [ 32462]  stream
│ │ -  [ 32469]  AES-128-GCM
│ │ -  [ 32475]  depack_do_frame_stop_sending
│ │ -  [ 32492]  DATA_BLOCKED
│ │ -  [ 3249f]  NEW_CONN_ID
│ │ -  [ 324ab]  AES-256-ECB
│ │ -  [ 324b7]  SSL alert number %d
│ │ -  [ 324cb]  tls_parse_ctos_post_handshake_auth
│ │ -  [ 324ee]  tls_construct_stoc_renegotiate
│ │ -  [ 3250d]  tls_construct_stoc_client_cert_type
│ │ -  [ 32531]  tls_process_cert_status_body
│ │ -  [ 3254e]  tls_construct_change_cipher_spec
│ │ -  [ 3256f]  parse_ca_names
│ │ -  [ 32580]  %04d%02d%02d%02d%02d%02dZ
│ │ -  [ 3259a]  %s %2d %02d:%02d:%02d%.*s %d%s
│ │ -  [ 325b9]  OBJECT
│ │ -  [ 325c0]  ASN1_ENUMERATED
│ │ -  [ 325d0]  broken pipe
│ │ -  [ 325dc]  unable to keepalive
│ │ -  [ 325f0]  BIO_new_mem_buf
│ │ -  [ 32600]  mem_write
│ │ -  [ 3260a]  crypto/bn/bn_exp.c
│ │ -  [ 3261d]  BN_generate_prime_ex2
│ │ -  [ 32633]  bnrand
│ │ -  [ 3263a]  keyfunc
│ │ -  [ 32642]  off
│ │ -  [ 32646]  module_run
│ │ -  [ 32651]  stbl_section
│ │ -  [ 3265e]  OCTETSTRING
│ │ -  [ 3266a]  i2o_SCT_signature
│ │ -  [ 3267c]  crypto/dsa/dsa_ossl.c
│ │ -  [ 32692]  do_EC_KEY_print
│ │ -  [ 326a2]  b
│ │ -  [ 326a4]  group
│ │ -  [ 326aa]  NIST/SECG curve over a 521 bit prime field
│ │ -  [ 326d5]  X9.62 curve over a 239 bit binary field
│ │ -  [ 326fd]  ossl_ecdsa_sign_setup
│ │ -  [ 32713]  ossl_ec_GFp_mont_field_inv
│ │ -  [ 3272e]  ecp_nistz256_mult_precompute
│ │ -  [ 3274b]  ossl_ecx_key_dup
│ │ -  [ 3275c]  crypto/bio/bf_readbuff.c
│ │ -  [ 32775]  <null>
│ │ -  [ 3277c]  section=%s, name=%s, value=%s
│ │ -  [ 3279a]  ENGINE_ctrl
│ │ -  [ 327a6]  engine_list_add
│ │ -  [ 327b6]  engine_table_register
│ │ -  [ 327cc]  CT routines
│ │ -  [ 327d8]  ASN1 lib
│ │ -  [ 327e1]  dh_paramgen_check
│ │ -  [ 327f3]  EVP_DigestFinalXOF
│ │ -  [ 32806]  prime192v3
│ │ -  [ 32811]  c2tnb191v3
│ │ -  [ 3281c]  brainpoolP256t1
│ │ -  [ 3282c]  EVP_DecryptFinal_ex
│ │ -  [ 32840]  EVP_MD_get_block_size
│ │ -  [ 32856]  crypto/evp/m_sigver.c
│ │ -  [ 3286c]  evp_mac_final
│ │ -  [ 3287a]  key type = %s
│ │ -  [ 32888]  [action:%d, state:%d] padding name %s
│ │ -  [ 328ae]  rsa-coefficient6
│ │ -  [ 328bf]  pkey_ec_paramgen
│ │ -  [ 328d0]  crypto/evp/signature.c
│ │ -  [ 328e7]  ffdhe4096
│ │ -  [ 328f1]  prime P:
│ │ -  [ 328fa]  counter: %d\n
│ │ -  [ 32907]  SHA-256
│ │ -  [ 3290f]  unknown option
│ │ -  [ 3291e]  asn1 parse error
│ │ -  [ 3292f]  explicit length mismatch
│ │ -  [ 32948]  invalid bmpstring length
│ │ -  [ 32961]  invalid universalstring length
│ │ -  [ 32980]  mime no content type
│ │ -  [ 32995]  no sig content type
│ │ -  [ 329a9]  the asn1 object identifier is not known for this md
│ │ -  [ 329dd]  unsupported any defined by type
│ │ -  [ 329fd]  no conf or environment variable
│ │ -  [ 32a1d]  param cannot be represented exactly
│ │ -  [ 32a41]  wrong order
│ │ -  [ 32a4d]  smime text error
│ │ -  [ 32a5e]  unsupported label source
│ │ -  [ 32a77]  missing trust store
│ │ -  [ 32a8b]  ess cert id wrong order
│ │ -  [ 32aa3]  RC2-CBC
│ │ -  [ 32aab]  aes128
│ │ -  [ 32ab2]  assertion failed: !sh_testbit(ptr, list, sh.bitmalloc)
│ │ -  [ 32ae9]  assertion failed: sh.freelist[list] == ptr
│ │ -  [ 32b14]  assertion failed: (bit & 1) == 0
│ │ -  [ 32b35]  crypto/packet.c
│ │ -  [ 32b45]  crypto/provider_conf.c
│ │ -  [ 32b5c]  provider_conf_init
│ │ -  [ 32b6f]  MD2
│ │ -  [ 32b73]  des-ede3-ofb
│ │ -  [ 32b80]  BF-ECB
│ │ -  [ 32b87]  rc4-40
│ │ -  [ 32b8e]  rc2-40-cbc
│ │ -  [ 32b99]  RSA-NP-MD5
│ │ -  [ 32ba4]  CRLReason
│ │ -  [ 32bae]  extReq
│ │ -  [ 32bb5]  id-smime-mod-ets-eSigPolicy-88
│ │ -  [ 32bd4]  id-smime-mod-ets-eSigPolicy-97
│ │ -  [ 32bf3]  id-smime-aa-ets-certValues
│ │ -  [ 32c0e]  id-qt
│ │ -  [ 32c14]  id-pkix1-implicit-93
│ │ -  [ 32c29]  ac-targeting
│ │ -  [ 32c36]  id-alg-noSignature
│ │ -  [ 32c49]  id-alg-dh-pop
│ │ -  [ 32c57]  id-cmc-getCert
│ │ -  [ 32c66]  acceptableResponses
│ │ -  [ 32c7a]  private
│ │ -  [ 32c82]  aes-128-cbc
│ │ -  [ 32c8e]  AES-192-ECB
│ │ -  [ 32c9a]  aes-192-ofb
│ │ -  [ 32ca6]  pseudonym
│ │ -  [ 32cb0]  Secure Electronic Transactions
│ │ -  [ 32ccf]  setct-AuthRevReqTBE
│ │ -  [ 32ce3]  setct-BatchAdminResTBE
│ │ -  [ 32cfa]  setct-CertResTBE
│ │ -  [ 32d0b]  setext-miAuth
│ │ -  [ 32d19]  setCext-certType
│ │ -  [ 32d2a]  setCext-TokenType
│ │ -  [ 32d3c]  set-brand-MasterCard
│ │ -  [ 32d51]  RSA-SHA384
│ │ -  [ 32d5c]  SEED-OFB
│ │ -  [ 32d65]  id-GostR3410-2001DH
│ │ -  [ 32d79]  id-aes192-CCM
│ │ -  [ 32d87]  rsaesOaep
│ │ -  [ 32d91]  aes-256-cbc-hmac-sha256
│ │ -  [ 32da9]  kuznyechik-cfb
│ │ -  [ 32db8]  KxANY
│ │ -  [ 32dbe]  x509ExtAdmission
│ │ -  [ 32dcf]  id-ecdsa-with-sha3-256
│ │ -  [ 32de6]  id-rsassa-pkcs1-v1_5-with-sha3-256
│ │ -  [ 32e09]  sm4-cfb1
│ │ -  [ 32e12]  RSA-SHA512/256
│ │ -  [ 32e21]  X509v3 Time Specification
│ │ -  [ 32e3b]  X509v3 User Notice
│ │ -  [ 32e4e]  X509v3 Acceptable Certification Policies
│ │ -  [ 32e77]  unknown nid
│ │ -  [ 32e83]  locator
│ │ -  [ 32e8b]  unknown message digest
│ │ -  [ 32ea2]  cipher is null
│ │ -  [ 32eb1]  PKCS12_MAC_DATA
│ │ -  [ 32ec1]  crypto/pkcs12/p12_kiss.c
│ │ -  [ 32eda]  crypto/pkcs12/p12_utl.c
│ │ -  [ 32ef2]  d.sign
│ │ -  [ 32ef9]  content_type
│ │ -  [ 32f06]  invalid null pointer
│ │ -  [ 32f1b]  invalid signed data type
│ │ -  [ 32f34]  !=
│ │ -  [ 32f37]  unable to get parent reseed prop counter
│ │ -  [ 32f60]  OpenSSL PKCS#1 RSA
│ │ -  [ 32f73]  crypto/rsa/rsa_pmeth.c
│ │ -  [ 32f8a]  crypto/rsa/rsa_x931.c
│ │ -  [ 32fa0]  RSA_padding_add_X931
│ │ -  [ 32fb5]  2048
│ │ -  [ 32fba]  1024
│ │ -  [ 32fbf]  crypto/store/store_meth.c
│ │ -  [ 32fd9]  could not set time
│ │ -  [ 32fec]  closing session
│ │ -  [ 32ffc]  noticeref
│ │ -  [ 33006]  explicitText
│ │ -  [ 33013]  superseded
│ │ -  [ 3301e]   - 
│ │ -  [ 33022]  %*sTarget Group: 
│ │ -  [ 33034]  Target Certificate:\n
│ │ -  [ 33049]  %*scAToolCert  : 
│ │ -  [ 3305b]  %*s  namingAuthorityUrl: 
│ │ -  [ 33075]  Require Explicit Policy
│ │ -  [ 3308d]  issuerDomainPolicy
│ │ -  [ 330a0]  any
│ │ -  [ 330a4]  %X:
│ │ -  [ 330a8]  bad option
│ │ -  [ 330b3]  illegal empty extension
│ │ -  [ 330cb]  invalid name
│ │ -  [ 330d8]  invalid object identifier
│ │ -  [ 330f2]  no config database
│ │ -  [ 33105]  unable to get issuer keyid
│ │ -  [ 33120]  invalid field name
│ │ -  [ 33133]  key type mismatch
│ │ -  [ 33145]  crypto/x509/x509_lu.c
│ │ -  [ 3315b]  X509_STORE_add_lookup
│ │ -  [ 33171]  compatible
│ │ -  [ 3317c]  name constraints minimum and maximum not supported
│ │ -  [ 331af]  object
│ │ -  [ 331b6]  engines/e_afalg_err.c
│ │ -  [ 331cc]  io setup failed
│ │ -  [ 331dc]  provider=base,fips=no,output=der,structure=SubjectPublicKeyInfo
│ │ -  [ 3321c]  provider=base,fips=yes,output=pem,structure=X9.62
│ │ -  [ 3324e]  provider=base,fips=yes,input=der,structure=dhx
│ │ -  [ 3327d]  provider=base,fips=no,input=der,structure=type-specific
│ │ -  [ 332b5]  MD5:SSL3-MD5:1.2.840.113549.2.5
│ │ -  [ 332d5]  DSA:dsaEncryption:1.2.840.10040.4.1
│ │ -  [ 332f9]  DSA-SHA2-384:DSA-SHA384:dsa_with_SHA384:id-dsa-with-sha384:1.2.840.1.101.3.4.3.3
│ │ -  [ 3334a]  provider=default,fips=yes,output=pem,structure=type-specific
│ │ -  [ 33387]  provider=default,fips=yes,output=pem,structure=ec
│ │ -  [ 333b9]  AES-256-WRAP:id-aes256-wrap:AES256-WRAP:2.16.840.1.101.3.4.1.45
│ │ -  [ 333f9]  AES-192-WRAP-PAD:id-aes192-wrap-pad:AES192-WRAP-PAD:2.16.840.1.101.3.4.1.28
│ │ -  [ 33445]  ARIA-128-CBC:ARIA128:1.2.410.200046.1.1.2
│ │ -  [ 3346f]  x448
│ │ -  [ 33474]  crypto/sm2/sm2_crypt.c
│ │ -  [ 3348b]  providers/implementations/ciphers/cipher_aria_ccm.c
│ │ -  [ 334bf]  providers/implementations/digests/sha3_prov.c
│ │ -  [ 334ed]  ossl_b2i_DSA_after_header
│ │ -  [ 33507]  check_bitlen_dsa
│ │ -  [ 33518]  key2any_encode
│ │ -  [ 33527]  ec_to_type_specific_no_pub_pem_encode
│ │ -  [ 3354d]  rsa_to_PrivateKeyInfo_pem_encode
│ │ -  [ 3356e]  ecx_pki_priv_to_der
│ │ -  [ 33582]  ED25519 PUBLIC KEY
│ │ -  [ 33595]  ecx_spki_pub_to_der
│ │ -  [ 335a9]  X448 PRIVATE KEY
│ │ -  [ 335ba]  rsa2msblob_encode
│ │ -  [ 335cc]  invalid Argon2 type
│ │ -  [ 335e0]  kdf_argon2_ctx_set_m_cost
│ │ -  [ 335fa]  hmac_drbg_kdf_set_ctx_params
│ │ -  [ 33617]  AES-128-WRAP
│ │ -  [ 33624]  crypto/hpke/hpke_util.c
│ │ -  [ 3363c]  RSASVE
│ │ -  [ 33643]  gen_type set to unsupported value %d
│ │ -  [ 33668]  providers/implementations/keymgmt/kdf_legacy_kmgmt.c
│ │ -  [ 3369d]  providers/implementations/macs/blake2_mac_impl.c
│ │ -  [ 336ce]  gmac_setkey
│ │ -  [ 336da]  digest=%s
│ │ -  [ 336e4]  failed to sign
│ │ -  [ 336f3]  parent cannot generate random numbers
│ │ -  [ 33719]  providers/implementations/ciphers/ciphercommon_block.c
│ │ -  [ 33750]  tance
│ │ -  [ 33756]  ey
│ │ -  [ 33759]  short-mac
│ │ -  [ 33763]  erence
│ │ -  [ 3376a]  ata-size
│ │ -  [ 33773]  -kem
│ │ -  [ 33778]  _Unwind_Resume
│ │ -  [ 33787]  d2
│ │ -  [ 3378a]  d12
│ │ -  [ 3378e]  NULL-SHA
│ │ -  [ 33797]  AES256-GCM-SHA384
│ │ -  [ 337a9]  RSA-PSK-NULL-SHA
│ │ -  [ 337ba]  TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA
│ │ -  [ 337dd]  ECDHE-PSK-NULL-SHA384
│ │ -  [ 337f3]  TLS_DH_anon_WITH_CAMELLIA_128_CBC_SHA256
│ │ -  [ 3381c]  DHE-RSA-CAMELLIA256-SHA
│ │ -  [ 33834]  DHE-DSS-CAMELLIA128-SHA
│ │ -  [ 3384c]  TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384
│ │ -  [ 33875]  TLS_RSA_PSK_WITH_ARIA_256_GCM_SHA384
│ │ -  [ 3389a]  cipher
│ │ -  [ 338a1]  ssl/ssl_cert.c
│ │ -  [ 338b0]  calling OPENSSL_dir_read(%s)
│ │ -  [ 338cd]  attempt to reuse session in different context
│ │ -  [ 338fb]  callback failed
│ │ -  [ 3390b]  invalid ccs message
│ │ -  [ 3391f]  serverhello tlsext
│ │ -  [ 33932]  ssl3 ext invalid servername type
│ │ -  [ 33953]  ssl command section empty
│ │ -  [ 3396d]  ssl session id too long
│ │ -  [ 33985]  tlsv1 alert unknown ca
│ │ -  [ 3399c]  version too high
│ │ -  [ 339ad]  wrong rpk type
│ │ -  [ 339bc]  wrong signature type
│ │ -  [ 339d1]  can_renegotiate
│ │ -  [ 339e1]  include/internal/packet.h
│ │ -  [ 339fb]  <EMPTY>
│ │ -  [ 33a03]  cmd=%s
│ │ -  [ 33a0a]  no_renegotiation
│ │ -  [ 33a1b]  ChainCAPath
│ │ -  [ 33a27]  RequestCAStore
│ │ -  [ 33a36]  UnsafeLegacyServerConnect
│ │ -  [ 33a50]  tls-group-name-internal
│ │ -  [ 33a68]  tls-min-dtls
│ │ -  [ 33a75]  rsa_pss_rsae_sha512
│ │ -  [ 33a89]  rsa_pss_pss_sha384
│ │ -  [ 33a9c]  RETRY_SCID does not match expected value
│ │ -  [ 33ac5]  INITIAL_SCID appears multiple times
│ │ -  [ 33ae9]  PREFERRED_ADDR is malformed
│ │ -  [ 33b05]  client received initial token
│ │ -  [ 33b23]  aead_limit_reached
│ │ -  [ 33b36]  ssl/quic/quic_tls.c
│ │ -  [ 33b4a]  CRYPTO
│ │ -  [ 33b51]  STREAM_OFF
│ │ -  [ 33b5c]  CONNECTION_REFUSED
│ │ -  [ 33b6f]  ChaCha20
│ │ -  [ 33b78]  dtls1_read_bytes
│ │ -  [ 33b89]  tls_construct_extensions
│ │ -  [ 33ba2]  tls_parse_ctos_sig_algs
│ │ -  [ 33bba]  tls_construct_stoc_early_data
│ │ -  [ 33bd8]  write_state_machine
│ │ -  [ 33bec]  tls_construct_cke_dhe
│ │ -  [ 33c02]  tls_output_rpk
│ │ -  [ 33c11]  tls13_restore_handshake_digest_for_pha
│ │ -  [ 33c38]  GOST_KX_MESSAGE
│ │ -  [ 33c48]  ossl_statem_server_write_transition
│ │ -  [ 33c6c]  \U%04lX
│ │ -  [ 33c74]  GENERALIZEDTIME
│ │ -  [ 33c84]  BIO_new_ex
│ │ -  [ 33c8f]  dgram_pair_write
│ │ -  [ 33ca0]  BN_mod_exp_mont_word
│ │ -  [ 33cb5]  iter
│ │ -  [ 33cba]  module_init
│ │ -  [ 33cc6]  FORMAT
│ │ -  [ 33ccd]  crypto/ct/ct_vfy.c
│ │ -  [ 33ce0]  %s: (%d bit)\n
│ │ -  [ 33cee]  j
│ │ -  [ 33cf0]  Private-Key
│ │ -  [ 33cfc]  old_dsa_priv_decode
│ │ -  [ 33d10]  ossl_dsa_do_sign_int
│ │ -  [ 33d25]  crypto/ec/ecdsa_sign.c
│ │ -  [ 33d3c]  ossl_ecx_compute_key
│ │ -  [ 33d51]  lib(%lu)
│ │ -  [ 33d5a]  BIO lib
│ │ -  [ 33d62]  interrupted or cancelled
│ │ -  [ 33d7b]  sect113r1
│ │ -  [ 33d85]  c2pnb176v1
│ │ -  [ 33d90]  c2tnb239v1
│ │ -  [ 33d9b]  wap-wsg-idm-ecid-wtls5
│ │ -  [ 33db2]  crypto/evp/evp_fetch.c
│ │ -  [ 33dc9]  parallelizationParameter
│ │ -  [ 33de2]  ossl_encoder_ctx_setup_for_pkey
│ │ -  [ 33e02]  EVP_PKEY_encapsulate
│ │ -  [ 33e17]  EVP_MAC_CTX_new
│ │ -  [ 33e27]  crypto/evp/p5_crpt.c
│ │ -  [ 33e3c]  rsa_pss_saltlen
│ │ -  [ 33e4c]  hexinfo
│ │ -  [ 33e54]  get_payload_public_key
│ │ -  [ 33e6b]  evp_pkey_ctx_set_md
│ │ -  [ 33e7f]  ossl_method_construct_postcondition
│ │ -  [ 33ea3]  OPENSSLDIR: "/usr/local/ssl"
│ │ -  [ 33ec0]  ctrl not implemented
│ │ -  [ 33ed5]  invalid key
│ │ -  [ 33ee1]  unknown security bits
│ │ -  [ 33ef7]  unsupported cipher
│ │ -  [ 33f0a]  unsupported keylength
│ │ -  [ 33f20]  no matching choice type
│ │ -  [ 33f38]  second number too large
│ │ -  [ 33f50]  wrong public key type
│ │ -  [ 33f66]  wrong tag
│ │ -  [ 33f70]  illegal hex digit
│ │ -  [ 33f82]  undefined generator
│ │ -  [ 33f96]  unknown group
│ │ -  [ 33fa4]  wrong curve parameters
│ │ -  [ 33fbb]  ctrl command not implemented
│ │ -  [ 33fd8]  no load function
│ │ -  [ 33fe9]  content not found
│ │ -  [ 33ffb]  unsupported encryption type
│ │ -  [ 34017]  popo missing public key
│ │ -  [ 3402f]  missing certid
│ │ -  [ 3403e]  unrecognized signature nid
│ │ -  [ 34059]  rc2-64
│ │ -  [ 34060]  bf
│ │ -  [ 34063]  CAST
│ │ -  [ 34068]  id-aes128-wrap
│ │ -  [ 34077]  AES192
│ │ -  [ 3407e]  aes192
│ │ -  [ 34085]  crypto/evp/e_aria.c
│ │ -  [ 34099]  assertion failed: ((ptr - sh.arena) & ((sh.arena_size >> list) - 1)) == 0
│ │ -  [ 340e3]  OSSL_PARAM_get_int32
│ │ -  [ 340f8]  module-filename
│ │ -  [ 34108]  crypto/objects/o_names.c
│ │ -  [ 34121]  RSA Data Security, Inc.
│ │ -  [ 34139]  O
│ │ -  [ 3413b]  pkcs7-signedAndEnvelopedData
│ │ -  [ 34158]  DES-ECB
│ │ -  [ 34160]  idea-ecb
│ │ -  [ 34169]  contentType
│ │ -  [ 34175]  Netscape
│ │ -  [ 3417e]  des-ede-cfb
│ │ -  [ 3418a]  Netscape Renewal Url
│ │ -  [ 3419f]  crlNumber
│ │ -  [ 341a9]  mdc2
│ │ -  [ 341ae]  surname
│ │ -  [ 341b6]  RC5-OFB
│ │ -  [ 341be]  Microsoft Individual Code Signing
│ │ -  [ 341e0]  S/MIME
│ │ -  [ 341e7]  id-smime-aa-receiptRequest
│ │ -  [ 34202]  id-smime-spq-ets-sqt-uri
│ │ -  [ 3421b]  id-aca-accessIdentity
│ │ -  [ 34231]  dod
│ │ -  [ 34235]  Hold Instruction Code
│ │ -  [ 3424b]  Hold Instruction None
│ │ -  [ 34261]  documentAuthor
│ │ -  [ 34270]  subtreeMaximumQuality
│ │ -  [ 34286]  set-policy
│ │ -  [ 34291]  setct-PI
│ │ -  [ 3429a]  setct-AuthTokenTBS
│ │ -  [ 342ad]  setct-CertReqData
│ │ -  [ 342bf]  setct-AuthResTBE
│ │ -  [ 342d0]  setAttr-IssCap
│ │ -  [ 342df]  Microsoft Smartcard Login
│ │ -  [ 342f9]  Inherit all
│ │ -  [ 34305]  camellia-192-cfb1
│ │ -  [ 34317]  CAMELLIA-192-CFB8
│ │ -  [ 34329]  id-PasswordBasedMAC
│ │ -  [ 3433d]  ecdsa-with-SHA256
│ │ -  [ 3434f]  GOST R 34.11-94 with GOST R 34.10-94
│ │ -  [ 34374]  md_gost94
│ │ -  [ 3437e]  id-GostR3410-94-CryptoPro-XchA-ParamSet
│ │ -  [ 343a6]  aes-256-xts
│ │ -  [ 343b2]  RC4-HMAC-MD5
│ │ -  [ 343bf]  aes-192-cbc-hmac-sha1
│ │ -  [ 343d5]  dhSinglePass-stdDH-sha384kdf-scheme
│ │ -  [ 343f9]  CAMELLIA-128-CTR
│ │ -  [ 3440a]  id-tc26-agreement-gost-3410-2012-512
│ │ -  [ 3442f]  issuerSignTool
│ │ -  [ 3443e]  capwapWTP
│ │ -  [ 34448]  KxDHE
│ │ -  [ 3444e]  auth-dss
│ │ -  [ 34457]  BLAKE2b512
│ │ -  [ 34462]  ARIA-256-CFB8
│ │ -  [ 34470]  sha3-384
│ │ -  [ 34479]  ecdsa_with_SHA3-224
│ │ -  [ 3448d]  RSA-SHA3-384
│ │ -  [ 3449a]  aria-128-ccm
│ │ -  [ 344a7]  aria-192-gcm
│ │ -  [ 344b4]  IEEE Security in Storage Working Group
│ │ -  [ 344db]  KMAC256
│ │ -  [ 344e3]  id-on-NAIRealm
│ │ -  [ 344f2]  brainpoolP512r1tls13
│ │ -  [ 34507]  zstd
│ │ -  [ 3450c]  protRestrict
│ │ -  [ 34519]  responseBytes
│ │ -  [ 34527]  certStatus
│ │ -  [ 34532]  ENCRYPTED PRIVATE KEY
│ │ -  [ 34548]  PKCS7
│ │ -  [ 3454e]  value.sdsicert
│ │ -  [ 3455d]  PKCS12_item_i2d_encrypt_ex
│ │ -  [ 34578]  key_enc_algor
│ │ -  [ 34586]  enc_key
│ │ -  [ 3458e]  pkcs7_bio_add_digest
│ │ -  [ 345a3]  sha1 (default)
│ │ -  [ 345b2]  14 (default)
│ │ -  [ 345bf]  ossl_rsa_fromdata
│ │ -  [ 345d1]  mp r not prime
│ │ -  [ 345e0]  crypto/srp/srp_lib.c
│ │ -  [ 345f5]  is not a
│ │ -  [ 345fe]  unacceptable policy
│ │ -  [ 34612]  get_cert_by_subject_ex
│ │ -  [ 34629]  crypto/asn1/x_info.c
│ │ -  [ 3463e]  d.usernotice
│ │ -  [ 3464b]  %*sNumber%s: 
│ │ -  [ 34659]  %*sOnly Attribute Certificates\n
│ │ -  [ 34679]  %*sCRL Issuer:\n
│ │ -  [ 34689]  unspecified
│ │ -  [ 34695]  /%d\n
│ │ -  [ 3469a]  OSSL_OBJECT_DIGEST_INFO
│ │ -  [ 346b2]  %*sDigest Type: Other\n
│ │ -  [ 346c9]  GENERAL_SUBTREE
│ │ -  [ 346d9]  xn--
│ │ -  [ 346de]  notBefore
│ │ -  [ 346e8]  notAfter
│ │ -  [ 346f1]  POLICY_MAPPING
│ │ -  [ 34700]  URI
│ │ -  [ 34704]  crypto/x509/v3_sxnet.c
│ │ -  [ 3471b]  zone
│ │ -  [ 34720]  Y
│ │ -  [ 34722]  -0x
│ │ -  [ 34726]  bad object
│ │ -  [ 34731]  duplicate zone id
│ │ -  [ 34743]  unknown purpose id
│ │ -  [ 34756]  unknown sigid algs
│ │ -  [ 34769]  x509_sig_info_init
│ │ -  [ 3477c]  self-signed certificate in certificate chain
│ │ -  [ 347a9]  unsupported name constraint type
│ │ -  [ 347ca]  Suite B: curve not allowed for this LOS
│ │ -  [ 347f2]  CA signature digest algorithm too weak
│ │ -  [ 34819]  X509_STORE_CTX_init
│ │ -  [ 3482d]  crypto/x509/x_all.c
│ │ -  [ 34841]  crypto/x509/x_crl.c
│ │ -  [ 34855]  failed to get platform info
│ │ -  [ 34871]  socket operation failed
│ │ -  [ 34889]  ALG_PERR: %s(%d): Socket Accept Failed : 
│ │ -  [ 348b3]  ALG_PERR: %s(%d): Failed to get eventfd : 
│ │ -  [ 348de]  provider=base,fips=yes,input=pvk
│ │ -  [ 348ff]  SHAKE-256:SHAKE256:2.16.840.1.101.3.4.2.12
│ │ -  [ 3492a]  DSA-SHA3-384:dsa_with_SHA3-384:id-dsa-with-sha3-384:2.16.840.1.101.3.4.3.7
│ │ -  [ 34975]  provider=default,fips=yes,output=msblob
│ │ -  [ 3499d]  AES-256-CBC:AES256:2.16.840.1.101.3.4.1.42
│ │ -  [ 349c8]  AES-256-GCM:id-aes256-GCM:2.16.840.1.101.3.4.1.46
│ │ -  [ 349fa]  AES-128-GCM:id-aes128-GCM:2.16.840.1.101.3.4.1.6
│ │ -  [ 34a2b]  DES-EDE3-ECB:DES-EDE3
│ │ -  [ 34a41]  secp256r1
│ │ -  [ 34a4b]  ossl_blake2b_get_ctx_params
│ │ -  [ 34a67]  SM2 PARAMETERS
│ │ -  [ 34a76]  providers/implementations/encode_decode/decode_spki2typespki.c
│ │ -  [ 34ab5]  rsapss_to_SubjectPublicKeyInfo_pem_encode
│ │ -  [ 34adf]  dh_to_PrivateKeyInfo_pem_encode
│ │ -  [ 34aff]  dh_to_SubjectPublicKeyInfo_pem_encode
│ │ -  [ 34b25]  dhx_to_EncryptedPrivateKeyInfo_der_encode
│ │ -  [ 34b4f]  dsa_to_PrivateKeyInfo_der_encode
│ │ -  [ 34b70]  ed25519_to_SubjectPublicKeyInfo_der_encode
│ │ -  [ 34b9b]  x4482text_encode
│ │ -  [ 34bac]  rsa_to_text
│ │ -  [ 34bb8]  rsapss2text_encode
│ │ -  [ 34bcb]  sskdf_derive
│ │ -  [ 34bd8]  x942kdf_size
│ │ -  [ 34be5]  dhkem_encap
│ │ -  [ 34bf1]  mac_key_fromdata
│ │ -  [ 34c02]  Given path=%s
│ │ -  [ 34c10]  file_open_stream
│ │ -  [ 34c21]  obj
│ │ -  [ 34c25]  length too large
│ │ -  [ 34c36]  unsupported cek alg
│ │ -  [ 34c4a]  props
│ │ -  [ 34c50]  nt-format
│ │ -  [ 34c5a]  nv
│ │ -  [ 34c5d]  eparator
│ │ -  [ 34c66]  ssl_encapsulate
│ │ -  [ 34c76]  AES128-GCM-SHA256
│ │ -  [ 34c88]  TLS_DH_anon_WITH_AES_128_GCM_SHA256
│ │ -  [ 34cac]  DHE-PSK-AES128-CCM
│ │ -  [ 34cbf]  ECDHE-ECDSA-AES128-CCM8
│ │ -  [ 34cd7]  TLS_DHE_PSK_WITH_NULL_SHA384
│ │ -  [ 34cf4]  TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256
│ │ -  [ 34d1e]  TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256
│ │ -  [ 34d4c]  DHE-DSS-CAMELLIA256-SHA256
│ │ -  [ 34d67]  TLS_EMPTY_RENEGOTIATION_INFO_SCSV
│ │ -  [ 34d89]  ssl3_finish_mac
│ │ -  [ 34d99]  SSL for verify callback
│ │ -  [ 34db1]  kuznyechik-mac
│ │ -  [ 34dc0]  kECDHE
│ │ -  [ 34dc7]  kPSK
│ │ -  [ 34dcc]  kDHEPSK
│ │ -  [ 34dd4]  aGOST
│ │ -  [ 34dda]  AECDH
│ │ -  [ 34de0]  bad digest length
│ │ -  [ 34df2]  ccs received early
│ │ -  [ 34e05]  compression disabled
│ │ -  [ 34e1a]  ee key too small
│ │ -  [ 34e2b]  parse tlsext
│ │ -  [ 34e38]  private key mismatch
│ │ -  [ 34e4d]  read bio not set
│ │ -  [ 34e5e]  ssl/tls alert handshake failure
│ │ -  [ 34e7e]  stream recv only
│ │ -  [ 34e8f]  too much early data
│ │ -  [ 34ea3]  unknown key exchange type
│ │ -  [ 34ebd]  unsupported compression algorithm
│ │ -  [ 34edf]  SSL_new
│ │ -  [ 34ee7]  ossl_bytes_to_cipher_list
│ │ -  [ 34f01]  no_anti_replay
│ │ -  [ 34f10]  KTLSTxZerocopySendfile
│ │ -  [ 34f27]  RequirePostHandshake
│ │ -  [ 34f3c]  tls1_setup_key_block
│ │ -  [ 34f51]  master secret
│ │ -  [ 34f5f]  tls1_PRF
│ │ -  [ 34f68]  tls-sigalg-name
│ │ -  [ 34f78]  ecdsa_sha224
│ │ -  [ 34f85]  tls13_hkdf_expand_ex
│ │ -  [ 34f9a]  tls13_hkdf_expand
│ │ -  [ 34fac]  ssl/tls_depr.c
│ │ -  [ 34fbb]  ossl_quic_pending_int
│ │ -  [ 34fd1]  ssl/quic/quic_engine.c
│ │ -  [ 34fe8]  ORIG_DCID does not match expected value
│ │ -  [ 35010]  ACTIVE_CONN_ID_LIMIT appears multiple times
│ │ -  [ 3503c]  ACTIVE_CONN_ID_LIMIT is malformed
│ │ -  [ 3505e]  common_fields
│ │ -  [ 3506c]  ossl_quic_rstream_queue_data
│ │ -  [ 35089]  depack_do_frame_new_token
│ │ -  [ 350a3]  PING
│ │ -  [ 350a8]  MAX_STREAMS_UNI
│ │ -  [ 350b8]  HANDSHAKE_DONE
│ │ -  [ 350c7]  PROTOCOL_VIOLATION
│ │ -  [ 350da]  INVALID_TOKEN
│ │ -  [ 350e8]  block_padding
│ │ -  [ 350f6]  stream_mac
│ │ -  [ 35101]  tls13_common_post_process_record
│ │ -  [ 35122]  final_ems
│ │ -  [ 3512c]  tls_construct_ctos_sig_algs
│ │ -  [ 35148]  tls_construct_ctos_post_handshake_auth
│ │ -  [ 3516f]  tls_parse_ctos_key_share
│ │ -  [ 35188]  tls_construct_stoc_cryptopro_bug
│ │ -  [ 351a9]  ossl_statem_server_process_message
│ │ -  [ 351cc]  ASN1_get_object
│ │ -  [ 351dc]  <ASN1 13>
│ │ -  [ 351e6]  cons: 
│ │ -  [ 351ed]  ZINT64
│ │ -  [ 351f4]  ASYNC_init_thread
│ │ -  [ 35206]  non-fatal or transient error
│ │ -  [ 35223]  crypto/bn/bn_rand.c
│ │ -  [ 35237]  ossl_bn_priv_rand_range_fixed_top
│ │ -  [ 35259]  SHA512
│ │ -  [ 35260]  group=%s name=%s
│ │ -  [ 35271]  INT
│ │ -  [ 35275]  ASN1_STRING_TABLE_add
│ │ -  [ 3528b]  ossl_dh_compute_key
│ │ -  [ 3529f]  pub_key
│ │ -  [ 352a7]  OpenSSL EC algorithm
│ │ -  [ 352bc]  EC_GROUP_new_from_ecparameters
│ │ -  [ 352db]  i2d_ECParameters
│ │ -  [ 352ec]  d2i_ECParameters
│ │ -  [ 352fd]  ossl_ec_key_param_from_x509_algor
│ │ -  [ 3531f]  RFC 5639 curve over a 224 bit prime field
│ │ -  [ 35349]  ossl_ec_group_set_params
│ │ -  [ 35362]  crypto/ec/ec_mult.c
│ │ -  [ 35376]  ossl_ec_GFp_mont_field_mul
│ │ -  [ 35391]  OpenSSL ED448 algorithm
│ │ -  [ 353a9]  No decoders were found. For standard decoders you need at least one of the default or base providers available. Did you forget to load them?
│ │ -  [ 35436]  Input structure: 
│ │ -  [ 35448]  data-type
│ │ -  [ 35452]  crypto/encode_decode/decoder_meth.c
│ │ -  [ 35476]  engine_id
│ │ -  [ 35480]  crypto/engine/tb_digest.c
│ │ -  [ 3549a]  secp112r2
│ │ -  [ 354a4]  sect131r1
│ │ -  [ 354ae]  EVP_PKEY_CTX_set_group_name
│ │ -  [ 354ca]  asn1_oct_int
│ │ -  [ 354d7]  evp_keymgmt_util_copy
│ │ -  [ 354ed]  rsa_padding_mode
│ │ -  [ 354fe]  oaep
│ │ -  [ 35503]  rsa-exponent1
│ │ -  [ 35511]  rsa-exponent6
│ │ -  [ 3551f]  ffdhe6144
│ │ -  [ 35529]  Got number %d when expecting %d
│ │ -  [ 35549]  peer key error
│ │ -  [ 35558]  cache constants failed
│ │ -  [ 3556f]  invalid seed length
│ │ -  [ 35583]  p not prime
│ │ -  [ 3558f]  illegal null
│ │ -  [ 3559c]  illegal options on item template
│ │ -  [ 355bd]  invalid separator
│ │ -  [ 355cf]  unknown signature algorithm
│ │ -  [ 355eb]  unknown tag
│ │ -  [ 355f7]  hex string too short
│ │ -  [ 3560c]  provider section error
│ │ -  [ 35623]  group2pkparameters failure
│ │ -  [ 3563e]  invalid output length
│ │ -  [ 35654]  conflicting engine id
│ │ -  [ 3566a]  failed loading private key
│ │ -  [ 35685]  redirection from https to http
│ │ -  [ 356a4]  error getting public key
│ │ -  [ 356bd]  error setting recipientinfo
│ │ -  [ 356d9]  invalid encrypted key length
│ │ -  [ 356f6]  multiple san sources
│ │ -  [ 3570b]  log conf missing key
│ │ -  [ 35720]  blowfish
│ │ -  [ 35729]  RSA-SHA1-2
│ │ -  [ 35734]  Specifies the path to the new ENGINE shared library
│ │ -  [ 35768]  general_get_uint
│ │ -  [ 35779]  ossl_pw_get_passphrase
│ │ -  [ 35790]  RC2-OFB
│ │ -  [ 35798]  dsaEncryption-old
│ │ -  [ 357aa]  X509v3 Basic Constraints
│ │ -  [ 357c3]  X509v3 CRL Reason Code
│ │ -  [ 357da]  PBE-SHA1-3DES
│ │ -  [ 357e8]  pkcs8ShroudedKeyBag
│ │ -  [ 357fc]  localKeyID
│ │ -  [ 35807]  x509Crl
│ │ -  [ 3580f]  PBE-MD2-RC2-64
│ │ -  [ 3581e]  id-smime-ct-TDTInfo
│ │ -  [ 35832]  id-smime-aa-ets-archiveTimeStamp
│ │ -  [ 35853]  id-smime-aa-signatureType
│ │ -  [ 3586d]  id-smime-alg-ESDHwith3DES
│ │ -  [ 35887]  id-cct
│ │ -  [ 3588e]  id-mod-attribute-cert
│ │ -  [ 358a4]  id-regCtrl
│ │ -  [ 358af]  id-cmc-statusInfo
│ │ -  [ 358c1]  id-cmc-senderNonce
│ │ -  [ 358d4]  id-cmc-decryptedPOP
│ │ -  [ 358e8]  serviceLocator
│ │ -  [ 358f7]  Microsoft CSP Name
│ │ -  [ 3590a]  aes-128-cfb
│ │ -  [ 35916]  Hold Instruction Reject
│ │ -  [ 3592e]  roomNumber
│ │ -  [ 35939]  manager
│ │ -  [ 35941]  content types
│ │ -  [ 3594f]  setct-PIDataUnsigned
│ │ -  [ 35964]  setct-CredRevReqTBS
│ │ -  [ 35978]  setct-AuthReqTBE
│ │ -  [ 35989]  setct-CapTokenTBEX
│ │ -  [ 3599c]  set-policy-root
│ │ -  [ 359ac]  aes-128-cfb1
│ │ -  [ 359b9]  AES-192-CFB8
│ │ -  [ 359c6]  CAMELLIA-192-OFB
│ │ -  [ 359d7]  hmacWithSHA384
│ │ -  [ 359e6]  id-GostR3411-94-with-GostR3410-2001
│ │ -  [ 35a0a]  id-GostR3411-94-CryptoProParamSet
│ │ -  [ 35a2c]  GOST 34.10-94 Cryptocom
│ │ -  [ 35a44]  LocalKeySet
│ │ -  [ 35a50]  AES-128-CTR
│ │ -  [ 35a5c]  AES-256-CTR
│ │ -  [ 35a68]  rc4-hmac-md5
│ │ -  [ 35a75]  dhSinglePass-cofactorDH-sha224kdf-scheme
│ │ -  [ 35a9e]  jurisdictionL
│ │ -  [ 35aac]  CAMELLIA-192-GCM
│ │ -  [ 35abd]  id-scrypt
│ │ -  [ 35ac7]  capwapAC
│ │ -  [ 35ad0]  kx-ecdhe
│ │ -  [ 35ad9]  BLAKE2s256
│ │ -  [ 35ae4]  SM4-OFB
│ │ -  [ 35aec]  sm-scheme
│ │ -  [ 35af6]  GOST R 34.10-2012 (512 bit) ParamSet C
│ │ -  [ 35b1d]  DSTU 4145-2002 little endian
│ │ -  [ 35b3a]  uacurve7
│ │ -  [ 35b43]  DSTU curve 8
│ │ -  [ 35b50]  magma-ctr-acpkm
│ │ -  [ 35b60]  magma-cbc
│ │ -  [ 35b6a]  hmacWithSHA512-256
│ │ -  [ 35b7d]  BLAKE2BMAC
│ │ -  [ 35b88]  CMC Archive Server
│ │ -  [ 35b9b]  cmKGA
│ │ -  [ 35ba1]  ms-app-policies
│ │ -  [ 35bb1]  acceptableCertPolicies
│ │ -  [ 35bc8]  value.byName
│ │ -  [ 35bd5]  error in nextupdate field
│ │ -  [ 35bef]  no revoked time
│ │ -  [ 35bff]  keyblob too short
│ │ -  [ 35c11]  Proc-Type: 4,%s\n
│ │ -  [ 35c22]  PEM_write_bio
│ │ -  [ 35c30]  pem_read_bio_key_legacy
│ │ -  [ 35c48]  attrib
│ │ -  [ 35c4f]  PBMAC1_get1_pbkdf2_param
│ │ -  [ 35c68]  PKCS12_verify_mac
│ │ -  [ 35c7a]  mac absent
│ │ -  [ 35c85]  parse error
│ │ -  [ 35c91]  PKCS7_find_digest
│ │ -  [ 35ca3]  crypto/pkcs7/pk7_attr.c
│ │ -  [ 35cbb]  seed_properties
│ │ -  [ 35ccb]  entropy_factor=%u, entropy_needed=%zu, bytes_needed=%zu,pool->max_len=%zu, pool->len=%zu
│ │ -  [ 35d24]  ossl_rsa_param_decode
│ │ -  [ 35d3a]  rsa_ossl_private_decrypt
│ │ -  [ 35d53]  crypto/rsa/rsa_none.c
│ │ -  [ 35d69]  ossl_rsa_sp800_56b_check_public
│ │ -  [ 35d89]  ossl_store_get0_loader_int
│ │ -  [ 35da4]  assertion failed: rc == 0
│ │ -  [ 35dbe]  pqualid
│ │ -  [ 35dc6]  (null)
│ │ -  [ 35dcd]  Cessation Of Operation
│ │ -  [ 35de4]   (Unicast)
│ │ -  [ 35def]  :\n
│ │ -  [ 35df2]  [%d]
│ │ -  [ 35df7]  ASRange
│ │ -  [ 35dff]  %*sCertificate Digest Info:\n
│ │ -  [ 35e1c]  %*s  admissionAuthorityId: 
│ │ -  [ 35e38]  inhibitPolicyMapping
│ │ -  [ 35e4d]  IP Address
│ │ -  [ 35e58]  <No Attributes>\n
│ │ -  [ 35e69]  v2i_TLS_FEATURE
│ │ -  [ 35e79]  invalid proxy policy setting
│ │ -  [ 35e96]  no crl number
│ │ -  [ 35ea4]  NO X509_NAME
│ │ -  [ 35eb1]  key usage does not include certificate signing
│ │ -  [ 35ee0]  unhandled critical extension
│ │ -  [ 35efd]  unhandled critical CRL extension
│ │ -  [ 35f1e]  Suite B: invalid public key algorithm
│ │ -  [ 35f44]  proxy subject name violation
│ │ -  [ 35f61]  OCSP unknown cert
│ │ -  [ 35f73]  Cannot find certificate signature algorithm
│ │ -  [ 35f9f]  cert info signature and signature algorithm mismatch
│ │ -  [ 35fd4]  X509_VERIFY_PARAM_set1_policies
│ │ -  [ 35ff4]  provider=base,fips=no,output=text
│ │ -  [ 36016]  provider=base,fips=yes,input=der,structure=EncryptedPrivateKeyInfo
│ │ -  [ 36059]  SHA1:SHA-1:SSL3-SHA1:1.3.14.3.2.26
│ │ -  [ 3607c]  BLAKE2B-512:BLAKE2b512:1.3.6.1.4.1.1722.12.2.1.16
│ │ -  [ 360ae]  RIPEMD-160:RIPEMD160:RIPEMD:RMD160:1.3.36.3.2.1
│ │ -  [ 360de]  X963KDF:X942KDF-CONCAT
│ │ -  [ 360f5]  DSA-SHA2-224:DSA-SHA224:dsa_with_SHA224:2.16.840.1.101.3.4.3.1
│ │ -  [ 36134]  DSA-SHA2-512:DSA-SHA512:dsa_with_SHA512:id-dsa-with-sha512:1.2.840.1.101.3.4.3.4
│ │ -  [ 36185]  RSA-SHA3-256:id-rsassa-pkcs1-v1_5-with-sha3-256:2.16.840.1.101.3.4.3.14
│ │ -  [ 361cd]  ECDSA-SHA1:ECDSA-SHA-1:ecdsa-with-SHA1:1.2.840.10045.4.1
│ │ -  [ 36206]  provider=default,fips=no,output=der,structure=type-specific
│ │ -  [ 36242]  ARIA-256-CTR:1.2.410.200046.1.1.15
│ │ -  [ 36265]  engine
│ │ -  [ 3626c]  invalid operation: %d
│ │ -  [ 36282]  C1y
│ │ -  [ 36286]  aes_wrap_cipher_internal
│ │ -  [ 3629f]  sm4_xts_cipher
│ │ -  [ 362ae]  tdes_init
│ │ -  [ 362b8]  ossl_blake2s_set_ctx_params
│ │ -  [ 362d4]  ossl_do_blob_header
│ │ -  [ 362e8]  do_PVK_body_key
│ │ -  [ 362f8]  RSA PUBLIC KEY
│ │ -  [ 36307]  dhx_to_X9_42_pem_encode
│ │ -  [ 3631f]  dsa2pvk_encode
│ │ -  [ 3632e]  kdf-digest-props
│ │ -  [ 3633f]  kdf_argon2_ctx_set_threads
│ │ -  [ 3635a]  invalid Argon2 version
│ │ -  [ 36371]  scrypt_alg
│ │ -  [ 3637c]  sskdf_common_set_ctx_params
│ │ -  [ 36398]  shared_secret
│ │ -  [ 363a6]  Invalid recipient public key
│ │ -  [ 363c3]  max_noncelen
│ │ -  [ 363d0]  drbg_ctr_init
│ │ -  [ 363de]  /dev/hwrng
│ │ -  [ 363e9]  Should be more than %d, but would be set to %d
│ │ -  [ 36418]  indicator integrity failure
│ │ -  [ 36434]  vp-info
│ │ -  [ 3643c]  ng
│ │ -  [ 3643f]  utlen
│ │ -  [ 36445]  datory-digest
│ │ -  [ 36453]  -info
│ │ -  [ 36459]  ign-x931-pad-disabled
│ │ -  [ 3646f]  ndfrag
│ │ -  [ 36476]  TLS_AES_128_CCM_8_SHA256
│ │ -  [ 3648f]  TLS_RSA_WITH_AES_128_CCM
│ │ -  [ 364a8]  PSK-AES128-CCM
│ │ -  [ 364b7]  AECDH-NULL-SHA
│ │ -  [ 364c6]  ECDHE-RSA-AES128-GCM-SHA256
│ │ -  [ 364e2]  TLS_PSK_WITH_AES_128_CBC_SHA256
│ │ -  [ 36502]  DHE-PSK-NULL-SHA384
│ │ -  [ 36516]  RSA-PSK-AES256-CBC-SHA384
│ │ -  [ 36530]  DHE-PSK-CHACHA20-POLY1305
│ │ -  [ 3654a]  CAMELLIA256-SHA256
│ │ -  [ 3655d]  DHE-DSS-CAMELLIA256-SHA
│ │ -  [ 36575]  DHE-PSK-CAMELLIA256-SHA384
│ │ -  [ 36590]  TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256
│ │ -  [ 365b9]  TLS_ECDHE_ECDSA_WITH_ARIA_256_GCM_SHA384
│ │ -  [ 365e2]  verify_result
│ │ -  [ 365f0]  DEFAULT
│ │ -  [ 365f8]  kRSAPSK
│ │ -  [ 36600]  EECDH
│ │ -  [ 36606]  block cipher pad is wrong
│ │ -  [ 36620]  dh public value length is wrong
│ │ -  [ 36640]  invalid serverinfo data
│ │ -  [ 36658]  not on record boundary
│ │ -  [ 3666f]  records not released
│ │ -  [ 36684]  shutdown while in init
│ │ -  [ 3669b]  ssl/tls alert certificate unknown
│ │ -  [ 366bd]  stream reset
│ │ -  [ 366ca]  tx_cert_comp
│ │ -  [ 366d7]  no_middlebox
│ │ -  [ 366e4]  ClientRenegotiation
│ │ -  [ 366f8]  ExtendedMasterSecret
│ │ -  [ 3670d]  Request
│ │ -  [ 36715]  ecdsa_secp256r1_sha256
│ │ -  [ 3672c]  rsa_pss_pss_sha512
│ │ -  [ 3673f]  prefix
│ │ -  [ 36746]  tls13_change_cipher_state
│ │ -  [ 36760]  SERVER_TRAFFIC_SECRET_N
│ │ -  [ 36778]  srp_generate_server_master_secret
│ │ -  [ 3679a]  internal error (packet buf init)
│ │ -  [ 367bb]  DISABLE_ACTIVE_MIGRATION appears multiple times
│ │ -  [ 367eb]  transport:parameters_set
│ │ -  [ 36804]  Post-handshake TLS CertificateRequest received
│ │ -  [ 36833]  ch_tick_tls
│ │ -  [ 3683f]  qlog_version
│ │ -  [ 3684c]  packet_lost
│ │ -  [ 36858]  transport:packet_received
│ │ -  [ 36872]  handshake_confirmed
│ │ -  [ 36886]  CRYPTO frame not valid in 0-RTT
│ │ -  [ 368a6]  AES-128-ECB
│ │ -  [ 368b2]  ssl/quic/quic_types.c
│ │ -  [ 368c8]  ACK_WITHOUT_ECN
│ │ -  [ 368d8]  MAX_DATA
│ │ -  [ 368e1]  STREAMS_BLOCKED_BIDI
│ │ -  [ 368f6]  tls_construct_ctos_sct
│ │ -  [ 3690d]  tls_parse_stoc_use_srtp
│ │ -  [ 36925]  tls_parse_ctos_status_request
│ │ -  [ 36943]  tls_construct_stoc_supported_versions
│ │ -  [ 36969]  tls_process_key_exchange
│ │ -  [ 36982]  ossl_statem_server_construct_message
│ │ -  [ 369a7]  tls_process_client_hello
│ │ -  [ 369c0]  tls_construct_server_certificate
│ │ -  [ 369e1]  tls_process_cke_psk_preamble
│ │ -  [ 369fe]  ASN1_item_dup
│ │ -  [ 36a0c]  asn1_get_int64
│ │ -  [ 36a1b]  crypto/asn1/a_mbstr.c
│ │ -  [ 36a31]  %4d-%02d-%02d %02d:%02d:%02d%s
│ │ -  [ 36a50]  tfo disabled
│ │ -  [ 36a5d]  local address not available
│ │ -  [ 36a79]  BIO_sendmmsg
│ │ -  [ 36a86]  ossl_bn_gen_dsa_nonce_fixed_top
│ │ -  [ 36aa6]  bnrand_range
│ │ -  [ 36ab3]  crypto/bn/bn_recp.c
│ │ -  [ 36ac7]  BN_rshift
│ │ -  [ 36ad1]  OpenSSL default
│ │ -  [ 36ae1]  default
│ │ -  [ 36ae9]  .cnf
│ │ -  [ 36aee]  crypto/asn1/asn_mstbl.c
│ │ -  [ 36b06]  name=%s, value=%s
│ │ -  [ 36b18]  OID
│ │ -  [ 36b1c]  DH Parameters
│ │ -  [ 36b2a]  bn_set_words
│ │ -  [ 36b37]  counter
│ │ -  [ 36b3f]  dh_new_intern
│ │ -  [ 36b4d]  DSO_load
│ │ -  [ 36b56]  EC_GROUP_check
│ │ -  [ 36b65]  X9.62 curve over a 176 bit binary field
│ │ -  [ 36b8d]  ossl_ec_GF2m_simple_point_set_affine_coordinates
│ │ -  [ 36bbe]  ec_GF2m_simple_ladder_pre
│ │ -  [ 36bd8]  ossl_ec_scalar_mul_ladder
│ │ -  [ 36bf2]  ossl_ec_GFp_mont_group_set_curve
│ │ -  [ 36c13]  ecx_pub_encode
│ │ -  [ 36c22]  OSSL_DECODER_CTX_set_construct
│ │ -  [ 36c41]  OSSL_DECODER_CTX_new_for_pkey
│ │ -  [ 36c5f]  object identifier routines
│ │ -  [ 36c7a]  engine routines
│ │ -  [ 36c8a]  BN lib
│ │ -  [ 36c91]  X509 lib
│ │ -  [ 36c9a]  crypto/evp/digest.c
│ │ -  [ 36cae]  crypto/evp/e_chacha20_poly1305.c
│ │ -  [ 36ccf]  Oakley-EC2N-3
│ │ -  [ 36cdd]  brainpoolP384r1
│ │ -  [ 36ced]  ivlen
│ │ -  [ 36cf3]  EVP_KDF_CTX_dup
│ │ -  [ 36d03]  crypto/evp/mac_lib.c
│ │ -  [ 36d18]  crypto/evp/mac_meth.c
│ │ -  [ 36d2e]  kdf-ukm
│ │ -  [ 36d36]  d
│ │ -  [ 36d38]  rsa-factor4
│ │ -  [ 36d44]  fips186_2
│ │ -  [ 36d4e]  fromdata_init
│ │ -  [ 36d5c]  OpenSSL 3.4.0 22 Oct 2024
│ │ -  [ 36d76]  div by zero
│ │ -  [ 36d82]  no inverse
│ │ -  [ 36d8d]  bad generator
│ │ -  [ 36d9b]  cannot set parameters
│ │ -  [ 36db1]  get raw key failed
│ │ -  [ 36dc4]  invalid parameters
│ │ -  [ 36dd7]  bmpstring is wrong length
│ │ -  [ 36df1]  mandatory braces in variable expansion
│ │ -  [ 36e18]  no value
│ │ -  [ 36e21]  explicit params not supported
│ │ -  [ 36e3f]  invalid curve
│ │ -  [ 36e4d]  ladder post failure
│ │ -  [ 36e61]  no filename
│ │ -  [ 36e6d]  command takes no input
│ │ -  [ 36e84]  error parsing url
│ │ -  [ 36e96]  max resp len exceeded
│ │ -  [ 36eac]  unexpected content type
│ │ -  [ 36ec4]  msgsigdigest wrong length
│ │ -  [ 36ede]  type not compressed data
│ │ -  [ 36ef7]  failed extracting pubkey
│ │ -  [ 36f10]  RIPEMD160
│ │ -  [ 36f1a]  assertion failed: temp-(sh.arena_size >> slist) == sh_find_my_buddy(temp, slist)
│ │ -  [ 36f6b]  prepare_from_text
│ │ -  [ 36f7d]  RSA-MD5
│ │ -  [ 36f85]  pbeWithMD2AndDES-CBC
│ │ -  [ 36f9a]  DES-OFB
│ │ -  [ 36fa2]  countersignature
│ │ -  [ 36fb3]  nsCertSequence
│ │ -  [ 36fc2]  authorityKeyIdentifier
│ │ -  [ 36fd9]  ripemd160
│ │ -  [ 36fe3]  RC5-ECB
│ │ -  [ 36feb]  codeSigning
│ │ -  [ 36ff7]  dnQualifier
│ │ -  [ 37003]  sbgp-routerIdentifier
│ │ -  [ 37019]  Extended OCSP Status
│ │ -  [ 3702e]  documentTitle
│ │ -  [ 3703c]  secretary
│ │ -  [ 37046]  setct-PInitResData
│ │ -  [ 37059]  setct-BatchAdminReqData
│ │ -  [ 37071]  setext-genCrypt
│ │ -  [ 37081]  setCext-TokenIdentifier
│ │ -  [ 37099]  setAttr-T2cleartxt
│ │ -  [ 370ac]  nameConstraints
│ │ -  [ 370bc]  ppBasis
│ │ -  [ 370c4]  ecdsa-with-Specified
│ │ -  [ 370d9]  id-GostR3410-94-b
│ │ -  [ 370eb]  id-alg-PWRI-KEK
│ │ -  [ 370fb]  aes-128-gcm
│ │ -  [ 37107]  id-aes256-CCM
│ │ -  [ 37115]  MGF1
│ │ -  [ 3711a]  dhSinglePass-stdDH-sha512kdf-scheme
│ │ -  [ 3713e]  id-tc26-algorithms
│ │ -  [ 37151]  GOST R 34.11-2012 with 512 bit hash
│ │ -  [ 37175]  id-tc26-digest-constants
│ │ -  [ 3718e]  tlsfeature
│ │ -  [ 37199]  aria-128-ecb
│ │ -  [ 371a6]  ARIA-192-CFB
│ │ -  [ 371b3]  aria-256-cfb
│ │ -  [ 371c0]  dsa_with_SHA3-224
│ │ -  [ 371d2]  ARIA-256-GCM
│ │ -  [ 371df]  cmcCA
│ │ -  [ 371e5]  DSTU curve 5
│ │ -  [ 371f2]  sm2
│ │ -  [ 371f6]  kuznyechik-ctr-acpkm
│ │ -  [ 3720b]  sshkdf
│ │ -  [ 37212]  cades-attributes
│ │ -  [ 37223]  timeSpecification
│ │ -  [ 37235]  crypto/objects/obj_lib.c
│ │ -  [ 3724e]  OCSP_CERTID
│ │ -  [ 3725a]  crlNum
│ │ -  [ 37261]  error converting private key
│ │ -  [ 3727e]  missing dek iv
│ │ -  [ 3728d]  value.x509cert
│ │ -  [ 3729c]  crypto/pkcs12/p12_decr.c
│ │ -  [ 372b5]  maybe wrong password
│ │ -  [ 372ca]  PKCS7_ATTR_SIGN
│ │ -  [ 372da]  d.encrypted
│ │ -  [ 372e6]  serial
│ │ -  [ 372ed]  crypto/rand/prov_seed.c
│ │ -  [ 37305]  already instantiated
│ │ -  [ 3731a]  entropy input too long
│ │ -  [ 37331]  error entropy pool was ignored
│ │ -  [ 37350]  random pool overflow
│ │ -  [ 37365]  unable to get parent strength
│ │ -  [ 37383]  ossl_rand_pool_bytes_needed
│ │ -  [ 3739f]  ossl_rand_pool_add
│ │ -  [ 373b2]  modulus:
│ │ -  [ 373bb]  Hash Algorithm: 
│ │ -  [ 373cc]  block type is not 02
│ │ -  [ 373e1]  d e not congruent to 1
│ │ -  [ 373f8]  invalid x931 digest
│ │ -  [ 3740c]  mp exponent not congruent to d
│ │ -  [ 3742b]  oaep decoding error
│ │ -  [ 3743f]  loader incomplete
│ │ -  [ 37451]  not a name
│ │ -  [ 3745c]  common ok and cancel characters
│ │ -  [ 3747c]  index too large
│ │ -  [ 3748c]  result too small
│ │ -  [ 3749d]  UI_get_result_length
│ │ -  [ 374b2]  UI_set_result_ex
│ │ -  [ 374c3]  crypto/ui/ui_openssl.c
│ │ -  [ 374da]  Load certs from files in a directory
│ │ -  [ 374ff]  decipherOnly
│ │ -  [ 3750c]  CA
│ │ -  [ 3750f]  onlyCA
│ │ -  [ 37516]  onlyAA
│ │ -  [ 3751d]  %*sFull Name:\n
│ │ -  [ 3752c]  u.addressPrefix
│ │ -  [ 3753c]  v2i_ASIdentifiers
│ │ -  [ 3754e]  RDI
│ │ -  [ 37552]  %*sTarget Name: 
│ │ -  [ 37563]  PROFESSION_INFO
│ │ -  [ 37573]  %*s      %s%s%s%s\n
│ │ -  [ 37586]  excluded
│ │ -  [ 3758f]  IP Address:%s
│ │ -  [ 3759d]  Registered ID:
│ │ -  [ 375ac]  s2i_ASN1_OCTET_STRING
│ │ -  [ 375c2]  s2i_ASN1_INTEGER
│ │ -  [ 375d3]  invalid trust
│ │ -  [ 375e1]  X509_STORE_add_cert
│ │ -  [ 375f5]  X509_STORE_add_crl
│ │ -  [ 37608]  %*sREAL
│ │ -  [ 37610]  lastUpdate
│ │ -  [ 3761b]  provider=base,fips=yes,output=der,structure=dhx
│ │ -  [ 3764b]  provider=base,fips=yes,output=der,structure=X9.42
│ │ -  [ 3767d]  KECCAK-256
│ │ -  [ 37688]  KECCAK-KMAC-128:KECCAK-KMAC128
│ │ -  [ 376a7]  GMAC:1.0.9797.3.4
│ │ -  [ 376b9]  X942KDF-ASN1:X942KDF
│ │ -  [ 376ce]  RSA-PSS:RSASSA-PSS:1.2.840.113549.1.1.10
│ │ -  [ 376f7]  ED448:1.3.101.113
│ │ -  [ 37709]  OpenSSL SCRYPT via EVP_PKEY implementation
│ │ -  [ 37734]  provider=default,fips=yes,output=der,structure=SubjectPublicKeyInfo
│ │ -  [ 37778]  provider=default,fips=no,output=pem,structure=EncryptedPrivateKeyInfo
│ │ -  [ 377be]  AES-256-OFB:2.16.840.1.101.3.4.1.43
│ │ -  [ 377e2]  AES-192-GCM-SIV
│ │ -  [ 377f2]  AES-256-CCM:id-aes256-CCM:2.16.840.1.101.3.4.1.47
│ │ -  [ 37824]  AES-256-WRAP-PAD:id-aes256-wrap-pad:AES256-WRAP-PAD:2.16.840.1.101.3.4.1.48
│ │ -  [ 37870]  aes_ocb_block_update_internal
│ │ -  [ 3788e]  siv_init
│ │ -  [ 37897]  providers/implementations/ciphers/cipher_aes_wrp.c
│ │ -  [ 378ca]  chacha20_get_ctx_params
│ │ -  [ 378e2]  dh_to_type_specific_params_pem_encode
│ │ -  [ 37908]  rsa_to_SubjectPublicKeyInfo_pem_encode
│ │ -  [ 3792f]  ed25519_to_EncryptedPrivateKeyInfo_der_encode
│ │ -  [ 3795d]  ed25519_to_EncryptedPrivateKeyInfo_pem_encode
│ │ -  [ 3798b]  h: %d\n
│ │ -  [ 37992]  use-l
│ │ -  [ 37998]  use-separator
│ │ -  [ 379a6]  providers/implementations/kdfs/sskdf.c
│ │ -  [ 379cd]  DES3-WRAP
│ │ -  [ 379d7]  secretsz invalid
│ │ -  [ 379e8]  providers/implementations/kem/ecx_kem.c
│ │ -  [ 37a10]  kmac_setkey
│ │ -  [ 37a1c]  min_noncelen
│ │ -  [ 37a29]  Ed25519
│ │ -  [ 37a31]  Ed25519ph
│ │ -  [ 37a3b]  RSA key size = %d, expected minimum = %d
│ │ -  [ 37a64]  failed during derivation
│ │ -  [ 37a7d]  fips module in error state
│ │ -  [ 37a98]  invalid input length
│ │ -  [ 37aad]  invalid kdf
│ │ -  [ 37ab9]  ossl_cipher_generic_get_params
│ │ -  [ 37ad8]  ossl_cipher_generic_block_final
│ │ -  [ 37af8]  ossl_cipher_generic_stream_update
│ │ -  [ 37b1a]  bg-no-trunc-md
│ │ -  [ 37b29]  dinlen
│ │ -  [ 37b30]  um_length
│ │ -  [ 37b3a]  len
│ │ -  [ 37b3e]  pe
│ │ -  [ 37b41]  sp
│ │ -  [ 37b44]  TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
│ │ -  [ 37b68]  DHE-RSA-AES256-SHA256
│ │ -  [ 37b7e]  TLS_RSA_WITH_AES_256_CCM_8
│ │ -  [ 37b99]  ECDHE-ECDSA-AES256-CCM
│ │ -  [ 37bb0]  ECDHE-RSA-AES128-SHA
│ │ -  [ 37bc5]  ECDHE-ECDSA-AES256-SHA384
│ │ -  [ 37bdf]  TLS_RSA_PSK_WITH_AES_128_CBC_SHA
│ │ -  [ 37c00]  TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
│ │ -  [ 37c24]  TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
│ │ -  [ 37c49]  ECDHE-PSK-CAMELLIA128-SHA256
│ │ -  [ 37c66]  ECDHE-PSK-CAMELLIA256-SHA384
│ │ -  [ 37c83]  DHE-RSA-ARIA128-GCM-SHA256
│ │ -  [ 37c9e]  TLS_DHE_RSA_WITH_ARIA_256_GCM_SHA384
│ │ -  [ 37cc3]  ECDHE-ARIA256-GCM-SHA384
│ │ -  [ 37cdc]  TLS_PSK_WITH_ARIA_128_GCM_SHA256
│ │ -  [ 37cfd]  DHE-PSK-ARIA256-GCM-SHA384
│ │ -  [ 37d18]  session_id
│ │ -  [ 37d23]  key_arg
│ │ -  [ 37d2b]  ssl_verify_internal
│ │ -  [ 37d3f]  TLS_AES_256_GCM_SHA384:TLS_CHACHA20_POLY1305_SHA256:TLS_AES_128_GCM_SHA256
│ │ -  [ 37d8a]  ciphersuite_cb
│ │ -  [ 37d99]  DHE
│ │ -  [ 37d9d]  bad early data
│ │ -  [ 37dac]  bad hrr version
│ │ -  [ 37dbc]  bad packet length
│ │ -  [ 37dce]  dtls message too big
│ │ -  [ 37de3]  ecdh required for suiteb mode
│ │ -  [ 37e01]  invalid command
│ │ -  [ 37e11]  missing rsa certificate
│ │ -  [ 37e29]  missing supported versions extension
│ │ -  [ 37e4e]  missing tmp ecdh key
│ │ -  [ 37e63]  no cookie callback set
│ │ -  [ 37e7a]  tls illegal exporter label
│ │ -  [ 37e95]  ssl/ssl_mcnf.c
│ │ -  [ 37ea4]  Curves
│ │ -  [ 37eab]  verifyCAfile
│ │ -  [ 37eb8]  EmptyFragments
│ │ -  [ 37ec7]  DHSingle
│ │ -  [ 37ed0]  Require
│ │ -  [ 37ed8]  g
│ │ -  [ 37eda]  rsa_pss_rsae_sha256
│ │ -  [ 37eee]  derive_secret_key_and_iv
│ │ -  [ 37f07]  quic_do_handshake
│ │ -  [ 37f19]  ossl_quic_channel_raise_protocol_error_loc
│ │ -  [ 37f44]  INITIAL_MAX_STREAM_DATA_BIDI_LOCAL is malformed
│ │ -  [ 37f74]  ACK_DELAY_EXP appears multiple times
│ │ -  [ 37f99]  STATELESS_RESET_TOKEN is malformed
│ │ -  [ 37fbc]  wb
│ │ -  [ 37fbf]  OpenSSL/%s (%s)
│ │ -  [ 37fcf]  header
│ │ -  [ 37fd6]  protocol_violation
│ │ -  [ 37fe9]  ssl/quic/quic_record_tx.c
│ │ -  [ 38003]  DATA_BLOCKED valid only in 0/1-RTT
│ │ -  [ 38026]  conn has zero-length CID
│ │ -  [ 3803f]  ossl_quic_tx_packetiser_set_cur_scid
│ │ -  [ 38064]  ssl3_write_bytes
│ │ -  [ 38075]  ssl/record/methods/tls_common.c
│ │ -  [ 38095]  final_key_share
│ │ -  [ 380a5]  tls_construct_ctos_key_share
│ │ -  [ 380c2]  tls_construct_stoc_server_name
│ │ -  [ 380e1]  tls_construct_stoc_session_ticket
│ │ -  [ 38103]  tls_parse_ctos_client_cert_type
│ │ -  [ 38123]  ssl/statem/statem.c
│ │ -  [ 38137]  ossl_statem_client_write_transition
│ │ -  [ 3815b]  tls_process_server_rpk
│ │ -  [ 38172]  tls_construct_cke_rsa
│ │ -  [ 38188]  tls_process_cke_gost
│ │ -  [ 3819d]  , 
│ │ -  [ 381a0]  ASN1_item_ex_i2d
│ │ -  [ 381b1]  async_release_job
│ │ -  [ 381c3]  <NULL>
│ │ -  [ 381ca]  dgram_mem_read
│ │ -  [ 381d9]  NULL\n
│ │ -  [ 381df]  PBE2PARAM
│ │ -  [ 381e9]  str_copy
│ │ -  [ 381f2]  parsebool
│ │ -  [ 381fc]  params.q
│ │ -  [ 38205]  DSO_get_filename
│ │ -  [ 38216]  symname(%s): %s
│ │ -  [ 38226]  fieldID
│ │ -  [ 3822e]  X9.62 curve over a 191 bit binary field
│ │ -  [ 38256]  BN_GF2m_mod_solve_quad_arr
│ │ -  [ 38271]  ossl_ec_key_simple_check_key
│ │ -  [ 3828e]  ossl_ec_GF2m_simple_point2oct
│ │ -  [ 382ac]  ecdsa_sign_setup
│ │ -  [ 382bd]  crypto/ec/ecp_mont.c
│ │ -  [ 382d2]  ossl_ec_GFp_simple_set_compressed_coordinates
│ │ -  [ 38300]  ossl_ec_GFp_simple_oct2point
│ │ -  [ 3831d]  int_engine_configure
│ │ -  [ 38332]  crypto/engine/eng_ctrl.c
│ │ -  [ 3834b]  UI lib
│ │ -  [ 38352]  secp192k1
│ │ -  [ 3835c]  prime239v2
│ │ -  [ 38367]  brainpoolP224t1
│ │ -  [ 38377]  K-409
│ │ -  [ 3837d]  tls1multi_enclen
│ │ -  [ 3838e]  custom-iv
│ │ -  [ 38398]  evp_pkcs82pkey_legacy
│ │ -  [ 383ae]  evp_keyexch_from_algorithm
│ │ -  [ 383c9]  evp_pkey_ctx_ctrl_to_param
│ │ -  [ 383e4]  dsa_paramgen_bits
│ │ -  [ 383f6]  bad reciprocal
│ │ -  [ 38405]  aes key setup failed
│ │ -  [ 3841a]  invalid iv length
│ │ -  [ 3842c]  no keymgmt available
│ │ -  [ 38441]  signature type and key type incompatible
│ │ -  [ 3846a]  invalid digest type
│ │ -  [ 3847e]  q not prime
│ │ -  [ 3848a]  expecting an integer
│ │ -  [ 3849f]  short line
│ │ -  [ 384aa]  unknown name in random section
│ │ -  [ 384c9]  cleanup method function failed
│ │ -  [ 384e8]  unimplemented digest
│ │ -  [ 384fd]  cipher aead set tag error
│ │ -  [ 38517]  ctrl error
│ │ -  [ 38522]  unwrap failure
│ │ -  [ 38531]  certhash unmatched
│ │ -  [ 38544]  DES-EDE
│ │ -  [ 3854c]  des-ede3-ecb
│ │ -  [ 38559]  ARIA192
│ │ -  [ 38561]  assertion failed: sh_testbit(ptr, list, sh.bittable)
│ │ -  [ 38596]  Prompt info data type incorrect
│ │ -  [ 385b6]  pass phrase
│ │ -  [ 385c2]  X500
│ │ -  [ 385c7]  Netscape Certificate Sequence
│ │ -  [ 385e5]  X509v3 CRL Number
│ │ -  [ 385f7]  uid
│ │ -  [ 385fb]  uniqueIdentifier
│ │ -  [ 3860c]  RC5-CBC
│ │ -  [ 38614]  pbeWithSHA1And40BitRC2-CBC
│ │ -  [ 3862f]  msExtReq
│ │ -  [ 38638]  sbgp-ipAddrBlock
│ │ -  [ 38649]  id-it-caKeyUpdateInfo
│ │ -  [ 3865f]  id-regCtrl-pkiPublicationInfo
│ │ -  [ 3867d]  DOD
│ │ -  [ 38681]  id-aca-encAttrs
│ │ -  [ 38691]  targetInformation
│ │ -  [ 386a3]  noRevAvail
│ │ -  [ 386ae]  X509v3 No Revocation Available
│ │ -  [ 386cd]  pilotObjectClass
│ │ -  [ 386de]  simpleSecurityObject
│ │ -  [ 386f3]  mail
│ │ -  [ 386f8]  documentVersion
│ │ -  [ 38708]  lastModifiedTime
│ │ -  [ 38719]  setAttr-Token-EMV
│ │ -  [ 3872b]  generate cryptogram
│ │ -  [ 3873f]  International Organizations
│ │ -  [ 3875b]  DES-CFB8
│ │ -  [ 38764]  CAMELLIA-128-ECB
│ │ -  [ 38775]  seed-ofb
│ │ -  [ 3877e]  caRepository
│ │ -  [ 3878b]  CA Repository
│ │ -  [ 38799]  ecdsa-with-SHA512
│ │ -  [ 387ab]  id-Gost28147-89-CryptoPro-Oscar-1-1-ParamSet
│ │ -  [ 387d8]  id-GostR3410-94-CryptoPro-B-ParamSet
│ │ -  [ 387fd]  id-GostR3410-2001-CryptoPro-A-ParamSet
│ │ -  [ 38824]  postalAddress
│ │ -  [ 38832]  x121Address
│ │ -  [ 3883e]  dhSinglePass-cofactorDH-sha1kdf-scheme
│ │ -  [ 38865]  CT Precertificate Poison
│ │ -  [ 3887e]  scrypt
│ │ -  [ 38885]  GOST R 34.10-2012 with 256 bit modulus
│ │ -  [ 388ac]  GOST R 34.11-2012 with 256 bit hash
│ │ -  [ 388d0]  SSH Server
│ │ -  [ 388db]  KxPSK
│ │ -  [ 388e1]  AuthDSS
│ │ -  [ 388e9]  Poly1305
│ │ -  [ 388f2]  auth-any
│ │ -  [ 388fb]  aria-128-ctr
│ │ -  [ 38908]  ARIA-192-CTR
│ │ -  [ 38915]  aria-192-cfb1
│ │ -  [ 38923]  SHA3-256
│ │ -  [ 3892c]  CMC Certificate Authority
│ │ -  [ 38946]  sm4-cbc
│ │ -  [ 3894e]  DSTU curve 2
│ │ -  [ 3895b]  DSTU curve 3
│ │ -  [ 38968]  id-tc26-gost-3410-2012-256-paramSetB
│ │ -  [ 3898d]  KMAC128
│ │ -  [ 38995]  aes-128-siv
│ │ -  [ 389a1]  Class of Signing Tool KB1
│ │ -  [ 389bb]  SM4-CCM
│ │ -  [ 389c3]  brotli
│ │ -  [ 389ca]  Microsoft NTDS AD objectSid
│ │ -  [ 389e6]  ms-ntds-sec-ext
│ │ -  [ 389f6]  basicAttConstraints
│ │ -  [ 38a0a]  short header
│ │ -  [ 38a17]  value.bag
│ │ -  [ 38a21]  PKCS7_ctrl
│ │ -  [ 38a2c]  ossl_parse_query
│ │ -  [ 38a3d]  crypto/property/property_string.c
│ │ -  [ 38a5f]  max_request
│ │ -  [ 38a6b]  drbg not initialised
│ │ -  [ 38a80]  unable to lock parent
│ │ -  [ 38a96]  Private-Key: (%d bit, %d primes)\n
│ │ -  [ 38ab8]  exponent1:
│ │ -  [ 38ac3]  (INVALID PSS PARAMETERS)\n
│ │ -  [ 38add]  iqmp
│ │ -  [ 38ae2]  mgf
│ │ -  [ 38ae6]  invalid strength
│ │ -  [ 38af7]  no public exponent
│ │ -  [ 38b0a]  crypto/rsa/rsa_saos.c
│ │ -  [ 38b20]  ossl_rsa_fips186_4_gen_prob_primes
│ │ -  [ 38b43]  not a public key
│ │ -  [ 38b54]  OSSL_STORE_LOADER_get0_provider
│ │ -  [ 38b74]  /dev/tty
│ │ -  [ 38b7d]  keyid
│ │ -  [ 38b83]  certificateHold
│ │ -  [ 38b93]  %*sIndirect CRL\n
│ │ -  [ 38ba4]  asnum
│ │ -  [ 38baa]  %*s%s-
│ │ -  [ 38bb1]  %*sPath Length Constraint: 
│ │ -  [ 38bcd]  POLICY_MAPPINGS
│ │ -  [ 38bdd]  setup_dp
│ │ -  [ 38be6]  X400Name
│ │ -  [ 38bef]  i2s_ASN1_UTF8STRING
│ │ -  [ 38c03]  x509v3_add_len_value
│ │ -  [ 38c18]  bad ip address
│ │ -  [ 38c27]  no proxy cert policy language defined
│ │ -  [ 38c4d]  X509_check_private_key
│ │ -  [ 38c64]  /usr/local/ssl/cert.pem
│ │ -  [ 38c7c]  unknown trust id
│ │ -  [ 38c8d]  CRL is not yet valid
│ │ -  [ 38ca2]  issuer certificate lookup error
│ │ -  [ 38cc2]  Certificate public key has explicit ECC parameters
│ │ -  [ 38cf5]  build_chain
│ │ -  [ 38d01]  crypto/x509/pcy_data.c
│ │ -  [ 38d18]  X509_VERIFY_PARAM_set1
│ │ -  [ 38d2f]  X509_PUBKEY_set
│ │ -  [ 38d3f]  afalg
│ │ -  [ 38d45]  cbc(aes)
│ │ -  [ 38d4e]  code 
│ │ -  [ 38d54]  provider=base,fips=yes,output=der,structure=SubjectPublicKeyInfo
│ │ -  [ 38d95]  provider=base,fips=yes,output=pem,structure=pkcs3
│ │ -  [ 38dc7]  SCRYPT:id-scrypt:1.3.6.1.4.1.11591.4.11
│ │ -  [ 38def]  OpenSSL X9.42 DH implementation
│ │ -  [ 38e0f]  ED448ph
│ │ -  [ 38e17]  ECDSA-SHA2-256:ECDSA-SHA256:ecdsa-with-SHA256:1.2.840.10045.4.3.2
│ │ -  [ 38e59]  provider=default,fips=yes,input=der,structure=PrivateKeyInfo
│ │ -  [ 38e96]  provider=default,fips=yes,input=der,structure=SubjectPublicKeyInfo
│ │ -  [ 38ed9]  AES-256-GCM-SIV
│ │ -  [ 38ee9]  C2
│ │ -  [ 38eec]  aes_cbc_cts_get_ctx_params
│ │ -  [ 38f07]  providers/implementations/ciphers/cipher_aes_hw.c
│ │ -  [ 38f39]  sm4_xts_stream_update
│ │ -  [ 38f4f]  GB
│ │ -  [ 38f52]  providers/implementations/digests/blake2_prov.c
│ │ -  [ 38f82]  rsa_to_type_specific_keypair_pem_encode
│ │ -  [ 38faa]  dhx_to_type_specific_params_pem_encode
│ │ -  [ 38fd1]  p8info_to_encp8
│ │ -  [ 38fe1]  dhx_to_EncryptedPrivateKeyInfo_pem_encode
│ │ -  [ 3900b]  sm2_to_PrivateKeyInfo_der_encode
│ │ -  [ 3902c]  sm2_to_SubjectPublicKeyInfo_der_encode
│ │ -  [ 39053]  :\n
│ │ +  [ 2e8b0]  built on: Fri Dec 20 19:14:54 2024 UTC
│ │ +  [ 2e8d7]  CPUINFO: OPENSSL_armcap=0x%x
│ │ +  [ 2e8f4]  expecting a dsa key
│ │ +  [ 2e908]  getting AlgorithmIdentifier not supported
│ │ +  [ 2e932]  locking not supported
│ │ +  [ 2e948]  no cipher set
│ │ +  [ 2e956]  depth exceeded
│ │ +  [ 2e965]  list error
│ │ +  [ 2e970]  odd number of chars
│ │ +  [ 2e984]  param of incompatible type
│ │ +  [ 2e99f]  too many bytes
│ │ +  [ 2e9ae]  invalid trinomial basis
│ │ +  [ 2e9c6]  invalid cmd number
│ │ +  [ 2e9d9]  connect failure
│ │ +  [ 2e9e9]  error parsing asn1 length
│ │ +  [ 2ea03]  cms datafinal error
│ │ +  [ 2ea17]  invalid label
│ │ +  [ 2ea25]  no matching signature
│ │ +  [ 2ea3b]  no private key
│ │ +  [ 2ea4a]  bad request id
│ │ +  [ 2ea59]  missing private key for popo
│ │ +  [ 2ea76]  unsupported pkibody
│ │ +  [ 2ea8a]  DESX
│ │ +  [ 2ea8f]  NO_VCHECK
│ │ +  [ 2ea99]  crypto/params_dup.c
│ │ +  [ 2eaad]  crypto/provider_child.c
│ │ +  [ 2eac5]  providers
│ │ +  [ 2eacf]  crypto/self_test_core.c
│ │ +  [ 2eae7]  nsRenewalUrl
│ │ +  [ 2eaf4]  RSA-MDC2
│ │ +  [ 2eafd]  cast5-cbc
│ │ +  [ 2eb07]  nsSGC
│ │ +  [ 2eb0d]  PBE-SHA1-RC2-128
│ │ +  [ 2eb1e]  Extension Request
│ │ +  [ 2eb30]  OCSP Signing
│ │ +  [ 2eb3d]  id-smime-ct-publishCert
│ │ +  [ 2eb55]  id-smime-cti-ets-proofOfSender
│ │ +  [ 2eb74]  md4
│ │ +  [ 2eb78]  id-pkix-mod
│ │ +  [ 2eb84]  id-mod-kea-profile-88
│ │ +  [ 2eb9a]  id-alg-dh-sig-hmac-sha1
│ │ +  [ 2ebb2]  Trust Root
│ │ +  [ 2ebbd]  ANSI X9.62
│ │ +  [ 2ebc8]  pagerTelephoneNumber
│ │ +  [ 2ebdd]  MIME MHS
│ │ +  [ 2ebe6]  setct-CertResData
│ │ +  [ 2ebf8]  setct-AuthRevResTBEB
│ │ +  [ 2ec0d]  setext-pinAny
│ │ +  [ 2ec1b]  setAttr-PGWYcap
│ │ +  [ 2ec2b]  aes-192-cfb1
│ │ +  [ 2ec38]  des-ede3-cfb1
│ │ +  [ 2ec46]  X509v3 Name Constraints
│ │ +  [ 2ec5e]  identified-organization
│ │ +  [ 2ec76]  c2onb191v5
│ │ +  [ 2ec81]  policyMappings
│ │ +  [ 2ec90]  CAMELLIA-192-CFB1
│ │ +  [ 2eca2]  SEED-CBC
│ │ +  [ 2ecab]  HMAC-SHA1
│ │ +  [ 2ecb5]  dsa_with_SHA224
│ │ +  [ 2ecc5]  id-GostR3410-94-CryptoPro-XchB-ParamSet
│ │ +  [ 2eced]  Permanent Identifier
│ │ +  [ 2ed02]  internationaliSDNNumber
│ │ +  [ 2ed1a]  authorityRevocationList
│ │ +  [ 2ed32]  distinguishedName
│ │ +  [ 2ed44]  dmdName
│ │ +  [ 2ed4c]  id-aes256-GCM
│ │ +  [ 2ed5a]  rsassaPss
│ │ +  [ 2ed64]  AES-128-CBC-HMAC-SHA1
│ │ +  [ 2ed7a]  dhSinglePass-cofactorDH-sha384kdf-scheme
│ │ +  [ 2eda3]  Signing Tool of Issuer
│ │ +  [ 2edba]  TLS Feature
│ │ +  [ 2edc6]  Signing KDC Response
│ │ +  [ 2eddb]  auth-gost12
│ │ +  [ 2ede7]  aria-256-ecb
│ │ +  [ 2edf4]  ARIA-192-CFB1
│ │ +  [ 2ee02]  id-dsa-with-sha384
│ │ +  [ 2ee15]  ISO CN Member Body
│ │ +  [ 2ee28]  Class of Signing Tool KC3
│ │ +  [ 2ee42]  id-regCtrl-algId
│ │ +  [ 2ee53]  sOAIdentifier
│ │ +  [ 2ee61]  OCSP_RESPONSE
│ │ +  [ 2ee6f]  OCSP_RESPDATA
│ │ +  [ 2ee7d]  no response data
│ │ +  [ 2ee8e]  load_iv
│ │ +  [ 2ee96]  PKCS12_unpack_authsafes
│ │ +  [ 2eeae]  PBMAC1_PBKDF2_HMAC
│ │ +  [ 2eec1]  d.data
│ │ +  [ 2eec8]  issuer_and_serial
│ │ +  [ 2eeda]  unknown operation
│ │ +  [ 2eeec]  too little nonce requested
│ │ +  [ 2ef07]  unable to fetch drbg
│ │ +  [ 2ef1c]  RSA_PSS_PARAMS
│ │ +  [ 2ef2b]  invalid header
│ │ +  [ 2ef3a]  salt length check failed
│ │ +  [ 2ef53]  ossl_bn_rsa_fips186_4_derive_prime
│ │ +  [ 2ef76]  reading strings
│ │ +  [ 2ef86]  exptext
│ │ +  [ 2ef8e]  , value=
│ │ +  [ 2ef97]  ,name:
│ │ +  [ 2ef9e]  %*sUnknown Qualifier: 
│ │ +  [ 2efb5]  emailCA
│ │ +  [ 2efbd]  keyCertSign
│ │ +  [ 2efc9]  ca
│ │ +  [ 2efcc]  DIST_POINT_NAME
│ │ +  [ 2efdc]  reasons
│ │ +  [ 2efe4]  Affiliation Changed
│ │ +  [ 2eff8]  distpoint
│ │ +  [ 2f002]  Reasons
│ │ +  [ 2f00a]  Remove From CRL
│ │ +  [ 2f01a]  IPAddressFamily
│ │ +  [ 2f02a]  u.addressesOrRanges
│ │ +  [ 2f03e]  ipAddressChoice
│ │ +  [ 2f04e]  %*sIPv6
│ │ +  [ 2f056]  crypto/x509/v3_ac_tgt.c
│ │ +  [ 2f06e]  %*scATool      : 
│ │ +  [ 2f080]  namingAuthorityText
│ │ +  [ 2f094]  language
│ │ +  [ 2f09d]  othername: SmtpUTF8Mailbox
│ │ +  [ 2f0b8]  othername:XmppAddr:%.*s
│ │ +  [ 2f0d0]  copy_email
│ │ +  [ 2f0db]  ossl_x509_pubkey_hash
│ │ +  [ 2f0f1]  unable to get issuer details
│ │ +  [ 2f10e]  ok
│ │ +  [ 2f111]  unable to decrypt certificate's signature
│ │ +  [ 2f13b]  key usage does not include CRL signing
│ │ +  [ 2f162]  Suite B: invalid ECC curve
│ │ +  [ 2f17d]  CA cert does not include key usage extension
│ │ +  [ 2f1aa]  set
│ │ +  [ 2f1ae]  X509_NAME
│ │ +  [ 2f1b8]  public_key
│ │ +  [ 2f1c3]  x509_pubkey_ex_d2i_ex
│ │ +  [ 2f1d9]  mem alloc failed
│ │ +  [ 2f1ea]  -ENOMEM ( code 
│ │ +  [ 2f1fa]  provider=base,fips=no,output=blob
│ │ +  [ 2f21c]  provider=base,fips=yes,input=der,structure=rsa
│ │ +  [ 2f24b]  provider=base,fips=yes,input=pem
│ │ +  [ 2f26c]  OpenSSL SM2 implementation
│ │ +  [ 2f287]  DSA-SHA2-256:DSA-SHA256:dsa_with_SHA256:2.16.840.1.101.3.4.3.2
│ │ +  [ 2f2c6]  DSA-SHA3-512:dsa_with_SHA3-512:id-dsa-with-sha3-512:2.16.840.1.101.3.4.3.8
│ │ +  [ 2f311]  provider=default,fips=yes,output=der,structure=type-specific
│ │ +  [ 2f34e]  provider=default,fips=yes,output=pem,structure=dsa
│ │ +  [ 2f381]  AES-128-WRAP-INV:AES128-WRAP-INV
│ │ +  [ 2f3a2]  ARIA-128-OFB:1.2.410.200046.1.1.4
│ │ +  [ 2f3c4]  ARIA-128-CTR:1.2.410.200046.1.1.5
│ │ +  [ 2f3e6]  DES-EDE3-CBC:DES3:1.2.840.113549.3.7
│ │ +  [ 2f40b]  x25519
│ │ +  [ 2f412]  chacha20_poly1305_set_ctx_params
│ │ +  [ 2f433]  ossl_b2i_RSA_after_header
│ │ +  [ 2f44d]  prepare_ec_params
│ │ +  [ 2f45f]  ec_to_SubjectPublicKeyInfo_pem_encode
│ │ +  [ 2f485]  dhx_to_DHX_der_encode
│ │ +  [ 2f49b]  ec_to_X9_62_der_encode
│ │ +  [ 2f4b2]  providers/implementations/encode_decode/encode_key2ms.c
│ │ +  [ 2f4ea]  SEED:
│ │ +  [ 2f4f0]  dh_set_ctx_params
│ │ +  [ 2f502]  sk
│ │ +  [ 2f505]  providers/implementations/kem/rsa_kem.c
│ │ +  [ 2f52d]  d-rounds
│ │ +  [ 2f536]  kat
│ │ +  [ 2f53a]  eddsa_dupctx
│ │ +  [ 2f547]  the EdDSA instance is preset, you may not try to specify it
│ │ +  [ 2f583]  Ed25519ctx
│ │ +  [ 2f58e]  MGF1 hash algorithm name too long
│ │ +  [ 2f5b0]  minimum salt length: %d, actual salt length: %d
│ │ +  [ 2f5e0]  rsa_signverify_message_update
│ │ +  [ 2f5fe]  sm2sig_set_mdname
│ │ +  [ 2f610]  providers/common/der/der_rsa_key.c
│ │ +  [ 2f633]  parent cannot supply entropy seed
│ │ +  [ 2f655]  ossl_cipher_generic_set_ctx_params
│ │ +  [ 2f678]  ossl_ccm_get_ctx_params
│ │ +  [ 2f690]  ypt-only
│ │ +  [ 2f699]  tion
│ │ +  [ 2f69e]  m_mac
│ │ +  [ 2f6a4]  lti
│ │ +  [ 2f6a8]  c-bits
│ │ +  [ 2f6af]  ms-check
│ │ +  [ 2f6b8]  2kdf-key-check
│ │ +  [ 2f6c7]  d4
│ │ +  [ 2f6ca]  d17
│ │ +  [ 2f6ce]  TLS_DH_anon_WITH_AES_128_CBC_SHA256
│ │ +  [ 2f6f2]  TLS_DHE_DSS_WITH_AES_256_GCM_SHA384
│ │ +  [ 2f716]  TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
│ │ +  [ 2f73e]  ECDHE-ECDSA-AES256-GCM-SHA384
│ │ +  [ 2f75c]  TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
│ │ +  [ 2f784]  SRP-AES-256-CBC-SHA
│ │ +  [ 2f798]  TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
│ │ +  [ 2f7c1]  TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
│ │ +  [ 2f7ee]  TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
│ │ +  [ 2f817]  ARIA256-GCM-SHA384
│ │ +  [ 2f82a]  ECDHE-ECDSA-ARIA256-GCM-SHA384
│ │ +  [ 2f849]  time
│ │ +  [ 2f84e]  %s/%s
│ │ +  [ 2f854]  GOST89
│ │ +  [ 2f85b]  GOST89MAC
│ │ +  [ 2f865]  binder does not verify
│ │ +  [ 2f87c]  certificate verify failed
│ │ +  [ 2f896]  cert cb error
│ │ +  [ 2f8a4]  dane tlsa bad certificate
│ │ +  [ 2f8be]  empty raw public key
│ │ +  [ 2f8d3]  fragmented client hello
│ │ +  [ 2f8eb]  invalid config
│ │ +  [ 2f8fa]  length too long
│ │ +  [ 2f90a]  can't find SRP server param
│ │ +  [ 2f926]  record length mismatch
│ │ +  [ 2f93d]  remote peer address not set
│ │ +  [ 2f959]  scsv received when renegotiating
│ │ +  [ 2f97a]  ssl3 session id too long
│ │ +  [ 2f993]  ssl/tls alert illegal parameter
│ │ +  [ 2f9b3]  no_etm
│ │ +  [ 2f9ba]  ciphersuites
│ │ +  [ 2f9c7]  NoRenegotiation
│ │ +  [ 2f9d7]  tls1_set_groups
│ │ +  [ 2f9e7]  add_provider_groups
│ │ +  [ 2f9fb]  PSS
│ │ +  [ 2f9ff]  ossl_quic_channel_on_new_conn_id
│ │ +  [ 2fa20]  bad transport parameter
│ │ +  [ 2fa38]  max_udp_payload_size
│ │ +  [ 2fa4d]  server
│ │ +  [ 2fa54]  title
│ │ +  [ 2fa5a]  reason
│ │ +  [ 2fa61]  closing
│ │ +  [ 2fa69]  reset_stream
│ │ +  [ 2fa76]  STREAM valid only in 0/1-RTT
│ │ +  [ 2fa93]  MAX_DATA valid only in 0/1-RTT
│ │ +  [ 2fab2]  CONN_CLOSE (APP) valid only in 0/1-RTT
│ │ +  [ 2fad9]  STOP_SENDING frame for RX only stream
│ │ +  [ 2faff]  read_ahead
│ │ +  [ 2fb0a]  ssl/record/methods/tls13_meth.c
│ │ +  [ 2fb2a]  final_ec_pt_formats
│ │ +  [ 2fb3e]  No groups enabled for max supported SSL/TLS version
│ │ +  [ 2fb72]  tls_construct_ctos_use_srtp
│ │ +  [ 2fb8e]  tls_parse_ctos_supported_groups
│ │ +  [ 2fbae]  tls_construct_client_hello
│ │ +  [ 2fbc9]  pub
│ │ +  [ 2fbcd]  crypto/asn1/a_object.c
│ │ +  [ 2fbe4]  i2a_ASN1_OBJECT
│ │ +  [ 2fbf4]  EXTERNAL
│ │ +  [ 2fbfd]  NUMERICSTRING
│ │ +  [ 2fc0b]  VIDEOTEXSTRING
│ │ +  [ 2fc1a]  :BAD ENUMERATED
│ │ +  [ 2fc2a]  ossl_d2i_PrivateKey_legacy
│ │ +  [ 2fc45]  ASN1_ANY
│ │ +  [ 2fc4e]  ASN1_PRINTABLE
│ │ +  [ 2fc5d]  ASN1_SET_ANY
│ │ +  [ 2fc6a]  UINT32
│ │ +  [ 2fc71]  ZUINT64
│ │ +  [ 2fc79]  crypto/async/async.c
│ │ +  [ 2fc8e]  crypto/bio/bf_buff.c
│ │ +  [ 2fca3]  malformed host or service
│ │ +  [ 2fcbd]  transfer timeout
│ │ +  [ 2fcce]  %09u
│ │ +  [ 2fcd3]  crypto/asn1/tasn_prn.c
│ │ +  [ 2fcea]   (%s)
│ │ +  [ 2fcf0]  EMPTY
│ │ +  [ 2fcf6]  PBKDF2PARAM
│ │ +  [ 2fd02]  NCONF_new_ex
│ │ +  [ 2fd0f]  module=%s, value=%s retcode=%-8d
│ │ +  [ 2fd30]  do_init_module_list_lock
│ │ +  [ 2fd49]  UTF8
│ │ +  [ 2fd4e]  IMP
│ │ +  [ 2fd52]  DSO_merge
│ │ +  [ 2fd5c]  ec_pkey_param_check
│ │ +  [ 2fd70]  ECPKPARAMETERS
│ │ +  [ 2fd7f]  p.tpBasis
│ │ +  [ 2fd89]  ec_asn1_group2fieldid
│ │ +  [ 2fd9f]  explicit
│ │ +  [ 2fda8]  named-nist
│ │ +  [ 2fdb3]  NIST/SECG/WTLS curve over a 233 bit binary field
│ │ +  [ 2fde4]  EC_KEY_oct2priv
│ │ +  [ 2fdf4]  Prime:
│ │ +  [ 2fdfb]  Order: 
│ │ +  [ 2fe03]  ossl_ecx_key_op
│ │ +  [ 2fe13]  ossl_decoder_instance_dup
│ │ +  [ 2fe2d]  ENGINE_set_default_string
│ │ +  [ 2fe47]  ENGINE_finish
│ │ +  [ 2fe55]  ENGINE_pkey_asn1_find_str
│ │ +  [ 2fe6f]  ENGINE_get_digest
│ │ +  [ 2fe81]  crypto/err/err_blocks.c
│ │ +  [ 2fe99]  secp256k1
│ │ +  [ 2fea3]  B-571
│ │ +  [ 2fea9]  EVP_EncryptUpdate
│ │ +  [ 2febb]  aead
│ │ +  [ 2fec0]  ossl_encoder_instance_new
│ │ +  [ 2feda]  EVP_DigestSign
│ │ +  [ 2fee9]  evp_mac_from_algorithm
│ │ +  [ 2ff00]  assertion failed: keylen <= sizeof(key)
│ │ +  [ 2ff28]  encoded-pub-key
│ │ +  [ 2ff38]  EXTRACT_ONLY
│ │ +  [ 2ff45]  SCRYPT
│ │ +  [ 2ff4c]  EVP_PKEY_CTX_dup
│ │ +  [ 2ff5d]  pkey_dh_derive
│ │ +  [ 2ff6c]  pkey_dh_ctrl_str
│ │ +  [ 2ff7d]  dsa_paramgen_check
│ │ +  [ 2ff90]  validate-pq
│ │ +  [ 2ff9c]  called with even modulus
│ │ +  [ 2ffb5]  unknown pbe algorithm
│ │ +  [ 2ffcb]  invalid utf8string
│ │ +  [ 2ffde]  missing equal sign
│ │ +  [ 2fff1]  i2d ecpkparameters failure
│ │ +  [ 3000c]  invalid generator
│ │ +  [ 3001e]  point is not on curve
│ │ +  [ 30034]  undefined order
│ │ +  [ 30044]  already loaded
│ │ +  [ 30053]  error sending
│ │ +  [ 30061]  invalid port number
│ │ +  [ 30075]  no receipt request
│ │ +  [ 30088]  certificate not accepted
│ │ +  [ 300a1]  error setting certhash
│ │ +  [ 300b8]  DES
│ │ +  [ 300bc]  rc2-40
│ │ +  [ 300c3]  assertion failed: list >= 0 && list < sh.freelist_size
│ │ +  [ 300fa]  ossl_hexstr2buf_sep
│ │ +  [ 3010e]  ossl_param_build_set_bn_pad
│ │ +  [ 3012a]  provider_conf_load
│ │ +  [ 3013d]  identity
│ │ +  [ 30146]  ON
│ │ +  [ 30149]  name=%s, provider has no provider init function
│ │ +  [ 30179]  shaWithRSAEncryption
│ │ +  [ 3018e]  X509v3 Subject Key Identifier
│ │ +  [ 301ac]  BF-CFB
│ │ +  [ 301b3]  givenName
│ │ +  [ 301bd]  DSA-SHA1
│ │ +  [ 301c6]  id-smime-aa-dvcs-dvc
│ │ +  [ 301db]  id-smime-cti-ets-proofOfDelivery
│ │ +  [ 301fc]  id-mod-cmp2000
│ │ +  [ 3020b]  qcStatements
│ │ +  [ 30218]  dvcs
│ │ +  [ 3021d]  id-cct-PKIResponse
│ │ +  [ 30230]  noCheck
│ │ +  [ 30238]  Management
│ │ +  [ 30243]  DC
│ │ +  [ 30246]  holdInstructionReject
│ │ +  [ 3025c]  domainRelatedObject
│ │ +  [ 30270]  id-hex-multipart-message
│ │ +  [ 30289]  set-attr
│ │ +  [ 30292]  setct-AuthRevReqBaggage
│ │ +  [ 302aa]  setct-AuthTokenTBE
│ │ +  [ 302bd]  setct-CapRevReqTBEX
│ │ +  [ 302d1]  setct-CredReqTBEX
│ │ +  [ 302e3]  setct-CertReqTBEX
│ │ +  [ 302f5]  merchant initiated auth
│ │ +  [ 3030d]  set-addPolicy
│ │ +  [ 3031b]  cleartext track 2
│ │ +  [ 3032d]  aes-256-cfb8
│ │ +  [ 3033a]  proxyCertInfo
│ │ +  [ 30348]  wap-wsg
│ │ +  [ 30350]  camellia-192-cfb
│ │ +  [ 30361]  gost89-cnt
│ │ +  [ 3036c]  CMAC
│ │ +  [ 30371]  kuznyechik-ofb
│ │ +  [ 30380]  chacha20
│ │ +  [ 30389]  auth-srp
│ │ +  [ 30392]  id-smime-ct-contentCollection
│ │ +  [ 303b0]  ARIA-256-CTR
│ │ +  [ 303bd]  id-hmacWithSHA3-256
│ │ +  [ 303d1]  magma-ctr-acpkm-omac
│ │ +  [ 303e6]  gmac
│ │ +  [ 303eb]  AES-256-SIV
│ │ +  [ 303f7]  Class of Signing Tool KB2
│ │ +  [ 30411]  sm4-ccm
│ │ +  [ 30419]  Brotli compression
│ │ +  [ 3042c]  OCSP_SINGLERESP
│ │ +  [ 3043c]  responseType
│ │ +  [ 30449]  value.unknown
│ │ +  [ 30457]  responses
│ │ +  [ 30461]  digest name err
│ │ +  [ 30471]  missing ocspsigning usage
│ │ +  [ 3048b]  DEK-Info:
│ │ +  [ 30495]  PRIVATE KEY
│ │ +  [ 304a1]  CMS
│ │ +  [ 304a5]  PKCS12
│ │ +  [ 304ac]  pkcs12_gen_mac
│ │ +  [ 304bb]  invalid type
│ │ +  [ 304c8]  PKCS7_SIGNED
│ │ +  [ 304d5]  evp_rand_from_algorithm
│ │ +  [ 304ed]  saltLength
│ │ +  [ 304f8]  algorithm mismatch
│ │ +  [ 3050b]  digest too big for rsa key
│ │ +  [ 30526]  crypto/rsa/rsa_gen.c
│ │ +  [ 3053b]  rsa_ossl_private_encrypt
│ │ +  [ 30554]  RSA_padding_check_PKCS1_OAEP_mgf1
│ │ +  [ 30576]  ossl_rsa_padding_check_PKCS1_type_2
│ │ +  [ 3059a]  ossl_rsa_prf
│ │ +  [ 305a7]  SHA2-512
│ │ +  [ 305b0]  ossl_rsa_sp800_56b_pairwise_test
│ │ +  [ 305d1]  error verifying pkcs12 mac
│ │ +  [ 305ec]  unsupported search type
│ │ +  [ 30604]  ossl_store_handle_load_result
│ │ +  [ 30622]  flushing
│ │ +  [ 3062b]  POLICYINFO
│ │ +  [ 30636]  crypto/x509/v3_ia5.c
│ │ +  [ 3064b]  %*scrlNum: 
│ │ +  [ 30657]  IPv4-SAFI
│ │ +  [ 30661]  crypto/ct/ct_x509v3.c
│ │ +  [ 30677]  signTool
│ │ +  [ 30680]  namingAuthorityId
│ │ +  [ 30692]  %*s  Profession Info Entry %0d:\n
│ │ +  [ 306b3]  process_pci_value
│ │ +  [ 306c5]  v2i_POLICY_MAPPINGS
│ │ +  [ 306d9]  OCSP helper
│ │ +  [ 306e5]  othername: NAIRealm
│ │ +  [ 306f9]  invalid multiple rdns
│ │ +  [ 3070f]  CRL path validation error
│ │ +  [ 30729]  OCSP verification needed
│ │ +  [ 30742]  Path length invalid for non-CA cert
│ │ +  [ 30766]  Using cert extension requires at least X509v3
│ │ +  [ 30794]  x509_verify_x509
│ │ +  [ 307a5]  X509_NAME_add_entry
│ │ +  [ 307b9]  %*s%.*s
│ │ +  [ 307c1]  (COULD NOT DECODE DISTINGUISHED NAME)\n
│ │ +  [ 307e8]  X509_NAME_ENTRIES
│ │ +  [ 307fa]  X509_PUBKEY_get
│ │ +  [ 3080a]  crypto/x509/x_x509.c
│ │ +  [ 3081f]  ALG_PERR: %s(%d): Failed to set socket option : 
│ │ +  [ 30850]  provider=base,fips=yes,input=der,structure=dsa
│ │ +  [ 3087f]  SHA3-256:2.16.840.1.101.3.4.2.8
│ │ +  [ 3089f]  AES-128-ECB:2.16.840.1.101.3.4.1.1
│ │ +  [ 308c2]  ARIA-192-GCM:1.2.410.200046.1.1.35
│ │ +  [ 308e5]  BIO to Core filter
│ │ +  [ 308f8]  SHA-1
│ │ +  [ 308fe]  rsa_get_ctx_params
│ │ +  [ 30911]  aes_cbc_cts_set_ctx_params
│ │ +  [ 3092c]  DSA PARAMETERS
│ │ +  [ 3093b]  dh_to_EncryptedPrivateKeyInfo_der_encode
│ │ +  [ 30964]  dh_spki_pub_to_der
│ │ +  [ 30977]  dsa_to_EncryptedPrivateKeyInfo_pem_encode
│ │ +  [ 309a1]  ed25519_to_PrivateKeyInfo_pem_encode
│ │ +  [ 309c6]  x25519_to_EncryptedPrivateKeyInfo_der_encode
│ │ +  [ 309f3]    Minimum Salt Length: %d%s\n
│ │ +  [ 30a10]  kdf_argon2i_new
│ │ +  [ 30a20]  constant
│ │ +  [ 30a29]  dsa_precheck_params
│ │ +  [ 30a3d]  crypto/sm2/sm2_key.c
│ │ +  [ 30a52]  ecx_gen
│ │ +  [ 30a5a]  encode_string
│ │ +  [ 30a68]  get_parent_reseed_count
│ │ +  [ 30a80]  ed25519_verify
│ │ +  [ 30a8f]  ed448_verify
│ │ +  [ 30a9c]  Cannot use autodetected salt length
│ │ +  [ 30ac0]  rsa_verify_message_final
│ │ +  [ 30ad9]  invalid aad
│ │ +  [ 30ae5]  ossl_ccm_set_ctx_params
│ │ +  [ 30afd]  rly_clean
│ │ +  [ 30b07]  ine
│ │ +  [ 30b0b]  _padding
│ │ +  [ 30b14]  erivation_function
│ │ +  [ 30b27]  tm
│ │ +  [ 30b2a]  _Unwind_Resume() can't return
│ │ +  [ 30b48]  ProcessDescriptors
│ │ +  [ 30b5b]  dtls1_check_timeout_num
│ │ +  [ 30b73]  TLS_CHACHA20_POLY1305_SHA256
│ │ +  [ 30b90]  NULL-MD5
│ │ +  [ 30b99]  TLS_DHE_DSS_WITH_AES_128_CBC_SHA
│ │ +  [ 30bba]  TLS_DHE_DSS_WITH_AES_256_CBC_SHA
│ │ +  [ 30bdb]  NULL-SHA256
│ │ +  [ 30be7]  ADH-AES128-GCM-SHA256
│ │ +  [ 30bfd]  AES128-CCM8
│ │ +  [ 30c09]  TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8
│ │ +  [ 30c2c]  TLS_ECDHE_ECDSA_WITH_NULL_SHA
│ │ +  [ 30c4a]  ECDHE-ECDSA-AES256-SHA
│ │ +  [ 30c61]  TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
│ │ +  [ 30c87]  TLS_RSA_PSK_WITH_AES_256_GCM_SHA384
│ │ +  [ 30cab]  SRP-RSA-AES-256-CBC-SHA
│ │ +  [ 30cc3]  TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
│ │ +  [ 30cec]  ADH-CAMELLIA256-SHA256
│ │ +  [ 30d03]  TLS_DH_anon_WITH_CAMELLIA_128_CBC_SHA
│ │ +  [ 30d29]  gost-mac-12
│ │ +  [ 30d35]  TLSv1.0
│ │ +  [ 30d3d]  RC4
│ │ +  [ 30d41]  bad ecc cert
│ │ +  [ 30d4e]  library has no ciphers
│ │ +  [ 30d65]  unknown cipher returned
│ │ +  [ 30d7d]  wrong signature size
│ │ +  [ 30d92]  no_legacy_server_connect
│ │ +  [ 30dab]  sigalgs
│ │ +  [ 30db3]  SSL_use_PrivateKey_file
│ │ +  [ 30dcb]  ssl_srp_ctx_init_intern
│ │ +  [ 30de3]  RETRY_SCID sent when not performing a retry
│ │ +  [ 30e0f]  INITIAL_MAX_STREAMS_UNI appears multiple times
│ │ +  [ 30e3e]  INITIAL_SCID was not sent but is required
│ │ +  [ 30e68]  RETRY_SCID was not sent but is required
│ │ +  [ 30e90]  preferred_addr
│ │ +  [ 30e9f]  port_v4
│ │ +  [ 30ea7]  ch_rxku_tick
│ │ +  [ 30eb4]  packet header reserved bits
│ │ +  [ 30ed0]  unidirectional
│ │ +  [ 30edf]  ChaCha20-Poly1305
│ │ +  [ 30ef1]  HANDSHAKE_DONE valid only in 1-RTT
│ │ +  [ 30f14]  depack_do_frame_reset_stream
│ │ +  [ 30f31]  depack_do_frame_handshake_done
│ │ +  [ 30f50]  quic_increment_sequence_ctr
│ │ +  [ 30f6c]  STREAM
│ │ +  [ 30f73]  STREAM_STATE_ERROR
│ │ +  [ 30f86]  CONNECTION_ID_LIMIT_ERROR
│ │ +  [ 30fa0]  APPLICATION_ERROR
│ │ +  [ 30fb2]  use_etm
│ │ +  [ 30fba]  tls-mac
│ │ +  [ 30fc2]  rlayer_early_data_count_ok
│ │ +  [ 30fdd]  tls13_validate_record_header
│ │ +  [ 30ffa]  tls_construct_ctos_server_name
│ │ +  [ 31019]  tls_construct_stoc_psk
│ │ +  [ 31030]  read_state_machine
│ │ +  [ 31043]  ossl_statem_client_post_process_message
│ │ +  [ 3106b]  crypto/asn1/a_strex.c
│ │ +  [ 31081]  asn1_collect
│ │ +  [ 3108e]  asn1_item_embed_new
│ │ +  [ 310a2]  DIRECTORYSTRING
│ │ +  [ 310b2]  crypto/asn1/tasn_utl.c
│ │ +  [ 310c9]  no hostname or service specified
│ │ +  [ 310ea]  transfer error
│ │ +  [ 310f9]  unable to reuseaddr
│ │ +  [ 3110d]  unsupported method
│ │ +  [ 31120]  BIO_ctrl
│ │ +  [ 31129]  bio_write_intern
│ │ +  [ 3113a]  0123456789ABCDEF
│ │ +  [ 3114b]  <ABSENT>\n
│ │ +  [ 31155]  encryption
│ │ +  [ 31160]  NCONF_get_string
│ │ +  [ 31171]  crypto/conf/conf_mod.c
│ │ +  [ 31188]  BITSTRING
│ │ +  [ 31192]  SCT_CTX_verify
│ │ +  [ 311a1]   (Negative)
│ │ +  [ 311ad]  named
│ │ +  [ 311b3]  generator
│ │ +  [ 311bd]  NIST/SECG/WTLS curve over a 163 bit binary field
│ │ +  [ 311ee]  RFC 5639 curve over a 384 bit prime field
│ │ +  [ 31218]  ossl_ec_GF2m_simple_group_set_curve
│ │ +  [ 3123c]  ossl_ec_key_simple_priv2oct
│ │ +  [ 31258]  EC_GROUP_get_curve
│ │ +  [ 3126b]  EC_GROUP_get_degree
│ │ +  [ 3127f]  EC_POINT_mul
│ │ +  [ 3128c]  ossl_ecdsa_sign_sig
│ │ +  [ 312a0]  ossl_ecdsa_verify_sig
│ │ +  [ 312b6]  crypto/ec/ecdsa_vrf.c
│ │ +  [ 312cc]  ecp_nistz256_points_mul
│ │ +  [ 312e4]  crypto/ec/ecp_smpl.c
│ │ +  [ 312f9]  ecx_generic_import_from
│ │ +  [ 31311]  pkey_ecd_digestsign448
│ │ +  [ 31328]  OSSL_DECODER_CTX_set_selection
│ │ +  [ 31347]  input
│ │ +  [ 3134d]  readbuffer
│ │ +  [ 31358]  ossl_decoder_get_number
│ │ +  [ 31370]  %s, Name (%s : %d), Properties (%s)
│ │ +  [ 31394]  init
│ │ +  [ 31399]  crypto/engine/eng_list.c
│ │ +  [ 313b2]  DIR_LOAD
│ │ +  [ 313bb]  1
│ │ +  [ 313bd]  time stamp routines
│ │ +  [ 313d1]  crypto/evp/asymcipher.c
│ │ +  [ 313e9]  aes_ocb_cipher
│ │ +  [ 313f8]  c2pnb304w1
│ │ +  [ 31403]  assertion failed: ctx->length <= (int)sizeof(ctx->enc_data)
│ │ +  [ 3143f]  randkey
│ │ +  [ 31447]  has-randkey
│ │ +  [ 31453]  num
│ │ +  [ 31457]  OSSL_ENCODER_CTX_set_params
│ │ +  [ 31473]  seterr
│ │ +  [ 3147a]  crypto/evp/exchange.c
│ │ +  [ 31490]  EVP_DigestSignFinal
│ │ +  [ 314a4]  EVP_DigestVerify
│ │ +  [ 314b5]  PKCS5_pbe_set_ex
│ │ +  [ 314c6]  dh_rfc5114
│ │ +  [ 314d1]  pkcs1
│ │ +  [ 314d7]  get_payload_private_key
│ │ +  [ 314ef]  EVP_PKEY_verify
│ │ +  [ 314ff]  crypto/comp_methods.c
│ │ +  [ 31515]  /home/vagrant/build/alt.nainapps.sharepaste.fdroid/rust/target/armv7-linux-androideabi/release/build/openssl-sys-d039a4a9eb3ff645/out/openssl-build/install/lib/ossl-modules
│ │ +  [ 315c2]  bad q value
│ │ +  [ 315ce]  header too long
│ │ +  [ 315de]  nested too deep
│ │ +  [ 315ee]  module initialization error
│ │ +  [ 3160a]  insufficient data space
│ │ +  [ 31622]  invalid group order
│ │ +  [ 31636]  invalid p
│ │ +  [ 31640]  point coordinates blind failure
│ │ +  [ 31660]  add signer error
│ │ +  [ 31671]  cms lib
│ │ +  [ 31679]  ess signing certid mismatch error
│ │ +  [ 3169b]  not supported for this key type
│ │ +  [ 316bb]  no content
│ │ +  [ 316c6]  no key or cert
│ │ +  [ 316d5]  malformed iv
│ │ +  [ 316e2]  popo raverified not accepted
│ │ +  [ 316ff]  generate certreqtemplate
│ │ +  [ 31718]  sm4
│ │ +  [ 3171c]  aes128-wrap-pad
│ │ +  [ 3172c]  id-aes192-wrap-pad
│ │ +  [ 3173f]  ARIA-192-CBC
│ │ +  [ 3174c]  hexstr2buf_sep
│ │ +  [ 3175b]  OSSL_PARAM_set_utf8_ptr
│ │ +  [ 31773]  unsigned_from_signed
│ │ +  [ 31788]  set_string_internal
│ │ +  [ 3179c]  organizationalUnitName
│ │ +  [ 317b3]  des-cfb
│ │ +  [ 317bb]  nsCertType
│ │ +  [ 317c6]  PKIX
│ │ +  [ 317cb]  ISO
│ │ +  [ 317cf]  id-on
│ │ +  [ 317d5]  ipsecEndSystem
│ │ +  [ 317e4]  id-regInfo-certReq
│ │ +  [ 317f7]  id-cmc-identification
│ │ +  [ 3180d]  id-cmc-transactionId
│ │ +  [ 31822]  id-cmc-revokeRequest
│ │ +  [ 31837]  id-cmc-popLinkWitness
│ │ +  [ 3184d]  caseIgnoreIA5StringSyntax
│ │ +  [ 31867]  associatedDomain
│ │ +  [ 31878]  setct-CardCInitResTBS
│ │ +  [ 3188e]  msSmartcardLogin
│ │ +  [ 3189f]  AES-192-CFB1
│ │ +  [ 318ac]  id-ppl-anyLanguage
│ │ +  [ 318bf]  sha384WithRSAEncryption
│ │ +  [ 318d7]  sha224WithRSAEncryption
│ │ +  [ 318ef]  camellia-192-cfb8
│ │ +  [ 31901]  id-DHBasedMac
│ │ +  [ 3190f]  deltaRevocationList
│ │ +  [ 31923]  RSASSA-PSS
│ │ +  [ 3192e]  dhSinglePass-stdDH-sha1kdf-scheme
│ │ +  [ 31950]  camellia-192-cmac
│ │ +  [ 31962]  md_gost12_256
│ │ +  [ 31970]  id-tc26-hmac-gost-3411-2012-512
│ │ +  [ 31990]  aria-192-cbc
│ │ +  [ 3199d]  ARIA-256-OFB
│ │ +  [ 319aa]  SHA3-512
│ │ +  [ 319b3]  SHAKE128
│ │ +  [ 319bc]  dstu28147
│ │ +  [ 319c6]  DSTU curve 1
│ │ +  [ 319d3]  DSTU curve 4
│ │ +  [ 319e0]  id-tc26-cipher-gostr3412-2015-kuznyechik
│ │ +  [ 31a09]  id-tc26-gost-3410-2012-256-paramSetD
│ │ +  [ 31a2e]  aes-256-siv
│ │ +  [ 31a3a]  kx-gost18
│ │ +  [ 31a44]  X509v3 Alternative Signature Algorithm
│ │ +  [ 31a6b]  Hardware Module Name
│ │ +  [ 31a80]  not encrypted
│ │ +  [ 31a8e]  PKCS #7 SIGNED DATA
│ │ +  [ 31aa2]  get_name
│ │ +  [ 31aab]  PKCS7_dataInit
│ │ +  [ 31aba]  cipher not initialized
│ │ +  [ 31ad1]  content and data present
│ │ +  [ 31aea]  unable to find message digest
│ │ +  [ 31b08]  not an ascii character
│ │ +  [ 31b1f]  BN_BLINDING_new
│ │ +  [ 31b2f]  data too small for key size
│ │ +  [ 31b4b]  invalid pss parameters
│ │ +  [ 31b62]  unknown padding type
│ │ +  [ 31b77]  8192
│ │ +  [ 31b7c]  cannot find config variable
│ │ +  [ 31b98]  OpenSSL default user interface
│ │ +  [ 31bb7]  NOTICEREF
│ │ +  [ 31bc1]  %*sExplicit Text: %.*s
│ │ +  [ 31bd8]  Object Signing
│ │ +  [ 31be7]  keyEncipherment
│ │ +  [ 31bf7]  %*s<EMPTY>\n
│ │ +  [ 31c03]  ASIdentifierChoice_canonize
│ │ +  [ 31c1f]  targetName
│ │ +  [ 31c2a]  certDigestInfo
│ │ +  [ 31c3a]  %*sTimestamp : 
│ │ +  [ 31c4a]  namingAuthorityUrl
│ │ +  [ 31c5d]  Not Before: 
│ │ +  [ 31c6a]  crlsign
│ │ +  [ 31c72]  crypto/x509/v3_san.c
│ │ +  [ 31c87]  copy_issuer
│ │ +  [ 31c93]  user
│ │ +  [ 31c98]  crypto/x509/v3_tlsf.c
│ │ +  [ 31cae]  i2s_ASN1_INTEGER
│ │ +  [ 31cbf]  self-signed certificate
│ │ +  [ 31cd7]  Suite B: invalid signature algorithm
│ │ +  [ 31cfc]  %*sFALSE
│ │ +  [ 31d05]  %*s<Unsupported tag %d>
│ │ +  [ 31d1d]  validity
│ │ +  [ 31d26]  socket bind failed
│ │ +  [ 31d39]  provider=base,fips=yes,output=der,structure=EncryptedPrivateKeyInfo
│ │ +  [ 31d7d]  provider=base,fips=yes,output=der,structure=ec
│ │ +  [ 31dac]  ARGON2ID
│ │ +  [ 31db5]  provider=default,fips=yes,output=der,structure=X9.62
│ │ +  [ 31dea]  provider=default,fips=yes,input=msblob
│ │ +  [ 31e11]  provider=default,fips=no,input=der,structure=type-specific
│ │ +  [ 31e4c]  ARIA-256-CCM:1.2.410.200046.1.1.39
│ │ +  [ 31e6f]  DES3-WRAP:id-smime-alg-CMS3DESwrap:1.2.840.113549.1.9.16.3.6
│ │ +  [ 31eac]  providers/implementations/ciphers/cipher_aes_gcm_siv.c
│ │ +  [ 31ee3]  aes_ocb_set_ctx_params
│ │ +  [ 31efa]  providers/implementations/ciphers/cipher_null.c
│ │ +  [ 31f2a]  DH PUBLIC KEY
│ │ +  [ 31f38]  ec_to_PrivateKeyInfo_der_encode
│ │ +  [ 31f58]  x448_to_EncryptedPrivateKeyInfo_pem_encode
│ │ +  [ 31f83]  rsapss_to_PKCS1_pem_encode
│ │ +  [ 31f9e]  Q:   
│ │ +  [ 31fa4]  providers/implementations/kdfs/kbkdf.c
│ │ +  [ 31fcb]  sskdf_size
│ │ +  [ 31fd6]  AES-256-WRAP
│ │ +  [ 31fe3]  ossl_kdf_ctx_create
│ │ +  [ 31ff7]  crypto/dsa/dsa_check.c
│ │ +  [ 3200e]  ec_gen_assign_group
│ │ +  [ 32022]  providers/implementations/macs/gmac_prov.c
│ │ +  [ 3204d]  ecdsa_signverify_init
│ │ +  [ 32063]  crypto/sm2/sm2_sign.c
│ │ +  [ 32079]  cipher operation failed
│ │ +  [ 32091]  missing config data
│ │ +  [ 320a5]  missing session id
│ │ +  [ 320b8]  oneshot call out of order
│ │ +  [ 320d2]  c
│ │ +  [ 320d4]  ssl-version
│ │ +  [ 320e0]  erties
│ │ +  [ 320e7]  hase
│ │ +  [ 320ec]  lient-version
│ │ +  [ 320fa]  eybits
│ │ +  [ 32101]  s7
│ │ +  [ 32104]  d22
│ │ +  [ 32108]  DHE-DSS-AES128-SHA
│ │ +  [ 3211b]  DHE-RSA-AES128-CCM
│ │ +  [ 3212e]  RSA-PSK-AES128-CBC-SHA
│ │ +  [ 32145]  SRP-DSS-AES-256-CBC-SHA
│ │ +  [ 3215d]  TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
│ │ +  [ 32182]  TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
│ │ +  [ 321a8]  ADH-CAMELLIA128-SHA
│ │ +  [ 321bc]  TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
│ │ +  [ 321e7]  TLS_RSA_WITH_ARIA_128_GCM_SHA256
│ │ +  [ 32208]  TLS_DHE_PSK_WITH_ARIA_128_GCM_SHA256
│ │ +  [ 3222d]  ssl_server
│ │ +  [ 32238]  IDEA
│ │ +  [ 3223d]  ARIA128
│ │ +  [ 32245]  ca dn length mismatch
│ │ +  [ 3225b]  dane tlsa bad matching type
│ │ +  [ 32277]  data between ccs and finished
│ │ +  [ 32295]  maximum encrypted pkts reached
│ │ +  [ 322b4]  no shared signature algorithms
│ │ +  [ 322d3]  no verify cookie callback
│ │ +  [ 322ed]  old session compression algorithm not returned
│ │ +  [ 3231c]  srtp could not allocate profiles
│ │ +  [ 3233d]  tlsv1 alert user cancelled
│ │ +  [ 32358]  automatic
│ │ +  [ 32362]  No valid groups in '%s'
│ │ +  [ 3237a]  tls1_set_server_sigalgs
│ │ +  [ 32392]  AES-256-CBC
│ │ +  [ 3239e]  rsa_pkcs1_sha384
│ │ +  [ 323af]  data
│ │ +  [ 323b4]  failed to start channel
│ │ +  [ 323cc]  handshake cannot be confirmed before it is completed
│ │ +  [ 32401]  ORIG_DCID may not be sent by a client
│ │ +  [ 32427]  INITIAL_SCID is malformed
│ │ +  [ 32441]  forgery limit
│ │ +  [ 3244f]  initial_source_connection_id
│ │ +  [ 3246c]  key update
│ │ +  [ 32477]  application_error
│ │ +  [ 32489]  stream
│ │ +  [ 32490]  AES-128-GCM
│ │ +  [ 3249c]  depack_do_frame_stop_sending
│ │ +  [ 324b9]  DATA_BLOCKED
│ │ +  [ 324c6]  NEW_CONN_ID
│ │ +  [ 324d2]  AES-256-ECB
│ │ +  [ 324de]  SSL alert number %d
│ │ +  [ 324f2]  tls_parse_ctos_post_handshake_auth
│ │ +  [ 32515]  tls_construct_stoc_renegotiate
│ │ +  [ 32534]  tls_construct_stoc_client_cert_type
│ │ +  [ 32558]  tls_process_cert_status_body
│ │ +  [ 32575]  tls_construct_change_cipher_spec
│ │ +  [ 32596]  parse_ca_names
│ │ +  [ 325a7]  %04d%02d%02d%02d%02d%02dZ
│ │ +  [ 325c1]  %s %2d %02d:%02d:%02d%.*s %d%s
│ │ +  [ 325e0]  OBJECT
│ │ +  [ 325e7]  ASN1_ENUMERATED
│ │ +  [ 325f7]  broken pipe
│ │ +  [ 32603]  unable to keepalive
│ │ +  [ 32617]  BIO_new_mem_buf
│ │ +  [ 32627]  mem_write
│ │ +  [ 32631]  crypto/bn/bn_exp.c
│ │ +  [ 32644]  BN_generate_prime_ex2
│ │ +  [ 3265a]  bnrand
│ │ +  [ 32661]  keyfunc
│ │ +  [ 32669]  off
│ │ +  [ 3266d]  module_run
│ │ +  [ 32678]  stbl_section
│ │ +  [ 32685]  OCTETSTRING
│ │ +  [ 32691]  i2o_SCT_signature
│ │ +  [ 326a3]  crypto/dsa/dsa_ossl.c
│ │ +  [ 326b9]  do_EC_KEY_print
│ │ +  [ 326c9]  b
│ │ +  [ 326cb]  group
│ │ +  [ 326d1]  NIST/SECG curve over a 521 bit prime field
│ │ +  [ 326fc]  X9.62 curve over a 239 bit binary field
│ │ +  [ 32724]  ossl_ecdsa_sign_setup
│ │ +  [ 3273a]  ossl_ec_GFp_mont_field_inv
│ │ +  [ 32755]  ecp_nistz256_mult_precompute
│ │ +  [ 32772]  ossl_ecx_key_dup
│ │ +  [ 32783]  crypto/bio/bf_readbuff.c
│ │ +  [ 3279c]  <null>
│ │ +  [ 327a3]  section=%s, name=%s, value=%s
│ │ +  [ 327c1]  ENGINE_ctrl
│ │ +  [ 327cd]  engine_list_add
│ │ +  [ 327dd]  engine_table_register
│ │ +  [ 327f3]  CT routines
│ │ +  [ 327ff]  ASN1 lib
│ │ +  [ 32808]  dh_paramgen_check
│ │ +  [ 3281a]  EVP_DigestFinalXOF
│ │ +  [ 3282d]  prime192v3
│ │ +  [ 32838]  c2tnb191v3
│ │ +  [ 32843]  brainpoolP256t1
│ │ +  [ 32853]  EVP_DecryptFinal_ex
│ │ +  [ 32867]  EVP_MD_get_block_size
│ │ +  [ 3287d]  crypto/evp/m_sigver.c
│ │ +  [ 32893]  evp_mac_final
│ │ +  [ 328a1]  key type = %s
│ │ +  [ 328af]  [action:%d, state:%d] padding name %s
│ │ +  [ 328d5]  rsa-coefficient6
│ │ +  [ 328e6]  pkey_ec_paramgen
│ │ +  [ 328f7]  crypto/evp/signature.c
│ │ +  [ 3290e]  ffdhe4096
│ │ +  [ 32918]  prime P:
│ │ +  [ 32921]  counter: %d\n
│ │ +  [ 3292e]  SHA-256
│ │ +  [ 32936]  unknown option
│ │ +  [ 32945]  asn1 parse error
│ │ +  [ 32956]  explicit length mismatch
│ │ +  [ 3296f]  invalid bmpstring length
│ │ +  [ 32988]  invalid universalstring length
│ │ +  [ 329a7]  mime no content type
│ │ +  [ 329bc]  no sig content type
│ │ +  [ 329d0]  the asn1 object identifier is not known for this md
│ │ +  [ 32a04]  unsupported any defined by type
│ │ +  [ 32a24]  no conf or environment variable
│ │ +  [ 32a44]  param cannot be represented exactly
│ │ +  [ 32a68]  wrong order
│ │ +  [ 32a74]  smime text error
│ │ +  [ 32a85]  unsupported label source
│ │ +  [ 32a9e]  missing trust store
│ │ +  [ 32ab2]  ess cert id wrong order
│ │ +  [ 32aca]  RC2-CBC
│ │ +  [ 32ad2]  aes128
│ │ +  [ 32ad9]  assertion failed: !sh_testbit(ptr, list, sh.bitmalloc)
│ │ +  [ 32b10]  assertion failed: sh.freelist[list] == ptr
│ │ +  [ 32b3b]  assertion failed: (bit & 1) == 0
│ │ +  [ 32b5c]  crypto/packet.c
│ │ +  [ 32b6c]  crypto/provider_conf.c
│ │ +  [ 32b83]  provider_conf_init
│ │ +  [ 32b96]  MD2
│ │ +  [ 32b9a]  des-ede3-ofb
│ │ +  [ 32ba7]  BF-ECB
│ │ +  [ 32bae]  rc4-40
│ │ +  [ 32bb5]  rc2-40-cbc
│ │ +  [ 32bc0]  RSA-NP-MD5
│ │ +  [ 32bcb]  CRLReason
│ │ +  [ 32bd5]  extReq
│ │ +  [ 32bdc]  id-smime-mod-ets-eSigPolicy-88
│ │ +  [ 32bfb]  id-smime-mod-ets-eSigPolicy-97
│ │ +  [ 32c1a]  id-smime-aa-ets-certValues
│ │ +  [ 32c35]  id-qt
│ │ +  [ 32c3b]  id-pkix1-implicit-93
│ │ +  [ 32c50]  ac-targeting
│ │ +  [ 32c5d]  id-alg-noSignature
│ │ +  [ 32c70]  id-alg-dh-pop
│ │ +  [ 32c7e]  id-cmc-getCert
│ │ +  [ 32c8d]  acceptableResponses
│ │ +  [ 32ca1]  private
│ │ +  [ 32ca9]  aes-128-cbc
│ │ +  [ 32cb5]  AES-192-ECB
│ │ +  [ 32cc1]  aes-192-ofb
│ │ +  [ 32ccd]  pseudonym
│ │ +  [ 32cd7]  Secure Electronic Transactions
│ │ +  [ 32cf6]  setct-AuthRevReqTBE
│ │ +  [ 32d0a]  setct-BatchAdminResTBE
│ │ +  [ 32d21]  setct-CertResTBE
│ │ +  [ 32d32]  setext-miAuth
│ │ +  [ 32d40]  setCext-certType
│ │ +  [ 32d51]  setCext-TokenType
│ │ +  [ 32d63]  set-brand-MasterCard
│ │ +  [ 32d78]  RSA-SHA384
│ │ +  [ 32d83]  SEED-OFB
│ │ +  [ 32d8c]  id-GostR3410-2001DH
│ │ +  [ 32da0]  id-aes192-CCM
│ │ +  [ 32dae]  rsaesOaep
│ │ +  [ 32db8]  aes-256-cbc-hmac-sha256
│ │ +  [ 32dd0]  kuznyechik-cfb
│ │ +  [ 32ddf]  KxANY
│ │ +  [ 32de5]  x509ExtAdmission
│ │ +  [ 32df6]  id-ecdsa-with-sha3-256
│ │ +  [ 32e0d]  id-rsassa-pkcs1-v1_5-with-sha3-256
│ │ +  [ 32e30]  sm4-cfb1
│ │ +  [ 32e39]  RSA-SHA512/256
│ │ +  [ 32e48]  X509v3 Time Specification
│ │ +  [ 32e62]  X509v3 User Notice
│ │ +  [ 32e75]  X509v3 Acceptable Certification Policies
│ │ +  [ 32e9e]  unknown nid
│ │ +  [ 32eaa]  locator
│ │ +  [ 32eb2]  unknown message digest
│ │ +  [ 32ec9]  cipher is null
│ │ +  [ 32ed8]  PKCS12_MAC_DATA
│ │ +  [ 32ee8]  crypto/pkcs12/p12_kiss.c
│ │ +  [ 32f01]  crypto/pkcs12/p12_utl.c
│ │ +  [ 32f19]  d.sign
│ │ +  [ 32f20]  content_type
│ │ +  [ 32f2d]  invalid null pointer
│ │ +  [ 32f42]  invalid signed data type
│ │ +  [ 32f5b]  !=
│ │ +  [ 32f5e]  unable to get parent reseed prop counter
│ │ +  [ 32f87]  OpenSSL PKCS#1 RSA
│ │ +  [ 32f9a]  crypto/rsa/rsa_pmeth.c
│ │ +  [ 32fb1]  crypto/rsa/rsa_x931.c
│ │ +  [ 32fc7]  RSA_padding_add_X931
│ │ +  [ 32fdc]  2048
│ │ +  [ 32fe1]  1024
│ │ +  [ 32fe6]  crypto/store/store_meth.c
│ │ +  [ 33000]  could not set time
│ │ +  [ 33013]  closing session
│ │ +  [ 33023]  noticeref
│ │ +  [ 3302d]  explicitText
│ │ +  [ 3303a]  superseded
│ │ +  [ 33045]   - 
│ │ +  [ 33049]  %*sTarget Group: 
│ │ +  [ 3305b]  Target Certificate:\n
│ │ +  [ 33070]  %*scAToolCert  : 
│ │ +  [ 33082]  %*s  namingAuthorityUrl: 
│ │ +  [ 3309c]  Require Explicit Policy
│ │ +  [ 330b4]  issuerDomainPolicy
│ │ +  [ 330c7]  any
│ │ +  [ 330cb]  %X:
│ │ +  [ 330cf]  bad option
│ │ +  [ 330da]  illegal empty extension
│ │ +  [ 330f2]  invalid name
│ │ +  [ 330ff]  invalid object identifier
│ │ +  [ 33119]  no config database
│ │ +  [ 3312c]  unable to get issuer keyid
│ │ +  [ 33147]  invalid field name
│ │ +  [ 3315a]  key type mismatch
│ │ +  [ 3316c]  crypto/x509/x509_lu.c
│ │ +  [ 33182]  X509_STORE_add_lookup
│ │ +  [ 33198]  compatible
│ │ +  [ 331a3]  name constraints minimum and maximum not supported
│ │ +  [ 331d6]  object
│ │ +  [ 331dd]  engines/e_afalg_err.c
│ │ +  [ 331f3]  io setup failed
│ │ +  [ 33203]  provider=base,fips=no,output=der,structure=SubjectPublicKeyInfo
│ │ +  [ 33243]  provider=base,fips=yes,output=pem,structure=X9.62
│ │ +  [ 33275]  provider=base,fips=yes,input=der,structure=dhx
│ │ +  [ 332a4]  provider=base,fips=no,input=der,structure=type-specific
│ │ +  [ 332dc]  MD5:SSL3-MD5:1.2.840.113549.2.5
│ │ +  [ 332fc]  DSA:dsaEncryption:1.2.840.10040.4.1
│ │ +  [ 33320]  DSA-SHA2-384:DSA-SHA384:dsa_with_SHA384:id-dsa-with-sha384:1.2.840.1.101.3.4.3.3
│ │ +  [ 33371]  provider=default,fips=yes,output=pem,structure=type-specific
│ │ +  [ 333ae]  provider=default,fips=yes,output=pem,structure=ec
│ │ +  [ 333e0]  AES-256-WRAP:id-aes256-wrap:AES256-WRAP:2.16.840.1.101.3.4.1.45
│ │ +  [ 33420]  AES-192-WRAP-PAD:id-aes192-wrap-pad:AES192-WRAP-PAD:2.16.840.1.101.3.4.1.28
│ │ +  [ 3346c]  ARIA-128-CBC:ARIA128:1.2.410.200046.1.1.2
│ │ +  [ 33496]  x448
│ │ +  [ 3349b]  crypto/sm2/sm2_crypt.c
│ │ +  [ 334b2]  providers/implementations/ciphers/cipher_aria_ccm.c
│ │ +  [ 334e6]  providers/implementations/digests/sha3_prov.c
│ │ +  [ 33514]  ossl_b2i_DSA_after_header
│ │ +  [ 3352e]  check_bitlen_dsa
│ │ +  [ 3353f]  key2any_encode
│ │ +  [ 3354e]  ec_to_type_specific_no_pub_pem_encode
│ │ +  [ 33574]  rsa_to_PrivateKeyInfo_pem_encode
│ │ +  [ 33595]  ecx_pki_priv_to_der
│ │ +  [ 335a9]  ED25519 PUBLIC KEY
│ │ +  [ 335bc]  ecx_spki_pub_to_der
│ │ +  [ 335d0]  X448 PRIVATE KEY
│ │ +  [ 335e1]  rsa2msblob_encode
│ │ +  [ 335f3]  invalid Argon2 type
│ │ +  [ 33607]  kdf_argon2_ctx_set_m_cost
│ │ +  [ 33621]  hmac_drbg_kdf_set_ctx_params
│ │ +  [ 3363e]  AES-128-WRAP
│ │ +  [ 3364b]  crypto/hpke/hpke_util.c
│ │ +  [ 33663]  RSASVE
│ │ +  [ 3366a]  gen_type set to unsupported value %d
│ │ +  [ 3368f]  providers/implementations/keymgmt/kdf_legacy_kmgmt.c
│ │ +  [ 336c4]  providers/implementations/macs/blake2_mac_impl.c
│ │ +  [ 336f5]  gmac_setkey
│ │ +  [ 33701]  digest=%s
│ │ +  [ 3370b]  failed to sign
│ │ +  [ 3371a]  parent cannot generate random numbers
│ │ +  [ 33740]  providers/implementations/ciphers/ciphercommon_block.c
│ │ +  [ 33777]  tance
│ │ +  [ 3377d]  ey
│ │ +  [ 33780]  short-mac
│ │ +  [ 3378a]  erence
│ │ +  [ 33791]  ata-size
│ │ +  [ 3379a]  -kem
│ │ +  [ 3379f]  _Unwind_Resume
│ │ +  [ 337ae]  d2
│ │ +  [ 337b1]  d12
│ │ +  [ 337b5]  NULL-SHA
│ │ +  [ 337be]  AES256-GCM-SHA384
│ │ +  [ 337d0]  RSA-PSK-NULL-SHA
│ │ +  [ 337e1]  TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA
│ │ +  [ 33804]  ECDHE-PSK-NULL-SHA384
│ │ +  [ 3381a]  TLS_DH_anon_WITH_CAMELLIA_128_CBC_SHA256
│ │ +  [ 33843]  DHE-RSA-CAMELLIA256-SHA
│ │ +  [ 3385b]  DHE-DSS-CAMELLIA128-SHA
│ │ +  [ 33873]  TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384
│ │ +  [ 3389c]  TLS_RSA_PSK_WITH_ARIA_256_GCM_SHA384
│ │ +  [ 338c1]  cipher
│ │ +  [ 338c8]  ssl/ssl_cert.c
│ │ +  [ 338d7]  calling OPENSSL_dir_read(%s)
│ │ +  [ 338f4]  attempt to reuse session in different context
│ │ +  [ 33922]  callback failed
│ │ +  [ 33932]  invalid ccs message
│ │ +  [ 33946]  serverhello tlsext
│ │ +  [ 33959]  ssl3 ext invalid servername type
│ │ +  [ 3397a]  ssl command section empty
│ │ +  [ 33994]  ssl session id too long
│ │ +  [ 339ac]  tlsv1 alert unknown ca
│ │ +  [ 339c3]  version too high
│ │ +  [ 339d4]  wrong rpk type
│ │ +  [ 339e3]  wrong signature type
│ │ +  [ 339f8]  can_renegotiate
│ │ +  [ 33a08]  include/internal/packet.h
│ │ +  [ 33a22]  <EMPTY>
│ │ +  [ 33a2a]  cmd=%s
│ │ +  [ 33a31]  no_renegotiation
│ │ +  [ 33a42]  ChainCAPath
│ │ +  [ 33a4e]  RequestCAStore
│ │ +  [ 33a5d]  UnsafeLegacyServerConnect
│ │ +  [ 33a77]  tls-group-name-internal
│ │ +  [ 33a8f]  tls-min-dtls
│ │ +  [ 33a9c]  rsa_pss_rsae_sha512
│ │ +  [ 33ab0]  rsa_pss_pss_sha384
│ │ +  [ 33ac3]  RETRY_SCID does not match expected value
│ │ +  [ 33aec]  INITIAL_SCID appears multiple times
│ │ +  [ 33b10]  PREFERRED_ADDR is malformed
│ │ +  [ 33b2c]  client received initial token
│ │ +  [ 33b4a]  aead_limit_reached
│ │ +  [ 33b5d]  ssl/quic/quic_tls.c
│ │ +  [ 33b71]  CRYPTO
│ │ +  [ 33b78]  STREAM_OFF
│ │ +  [ 33b83]  CONNECTION_REFUSED
│ │ +  [ 33b96]  ChaCha20
│ │ +  [ 33b9f]  dtls1_read_bytes
│ │ +  [ 33bb0]  tls_construct_extensions
│ │ +  [ 33bc9]  tls_parse_ctos_sig_algs
│ │ +  [ 33be1]  tls_construct_stoc_early_data
│ │ +  [ 33bff]  write_state_machine
│ │ +  [ 33c13]  tls_construct_cke_dhe
│ │ +  [ 33c29]  tls_output_rpk
│ │ +  [ 33c38]  tls13_restore_handshake_digest_for_pha
│ │ +  [ 33c5f]  GOST_KX_MESSAGE
│ │ +  [ 33c6f]  ossl_statem_server_write_transition
│ │ +  [ 33c93]  \U%04lX
│ │ +  [ 33c9b]  GENERALIZEDTIME
│ │ +  [ 33cab]  BIO_new_ex
│ │ +  [ 33cb6]  dgram_pair_write
│ │ +  [ 33cc7]  BN_mod_exp_mont_word
│ │ +  [ 33cdc]  iter
│ │ +  [ 33ce1]  module_init
│ │ +  [ 33ced]  FORMAT
│ │ +  [ 33cf4]  crypto/ct/ct_vfy.c
│ │ +  [ 33d07]  %s: (%d bit)\n
│ │ +  [ 33d15]  j
│ │ +  [ 33d17]  Private-Key
│ │ +  [ 33d23]  old_dsa_priv_decode
│ │ +  [ 33d37]  ossl_dsa_do_sign_int
│ │ +  [ 33d4c]  crypto/ec/ecdsa_sign.c
│ │ +  [ 33d63]  ossl_ecx_compute_key
│ │ +  [ 33d78]  lib(%lu)
│ │ +  [ 33d81]  BIO lib
│ │ +  [ 33d89]  interrupted or cancelled
│ │ +  [ 33da2]  sect113r1
│ │ +  [ 33dac]  c2pnb176v1
│ │ +  [ 33db7]  c2tnb239v1
│ │ +  [ 33dc2]  wap-wsg-idm-ecid-wtls5
│ │ +  [ 33dd9]  crypto/evp/evp_fetch.c
│ │ +  [ 33df0]  parallelizationParameter
│ │ +  [ 33e09]  ossl_encoder_ctx_setup_for_pkey
│ │ +  [ 33e29]  EVP_PKEY_encapsulate
│ │ +  [ 33e3e]  EVP_MAC_CTX_new
│ │ +  [ 33e4e]  crypto/evp/p5_crpt.c
│ │ +  [ 33e63]  rsa_pss_saltlen
│ │ +  [ 33e73]  hexinfo
│ │ +  [ 33e7b]  get_payload_public_key
│ │ +  [ 33e92]  evp_pkey_ctx_set_md
│ │ +  [ 33ea6]  ossl_method_construct_postcondition
│ │ +  [ 33eca]  OPENSSLDIR: "/usr/local/ssl"
│ │ +  [ 33ee7]  ctrl not implemented
│ │ +  [ 33efc]  invalid key
│ │ +  [ 33f08]  unknown security bits
│ │ +  [ 33f1e]  unsupported cipher
│ │ +  [ 33f31]  unsupported keylength
│ │ +  [ 33f47]  no matching choice type
│ │ +  [ 33f5f]  second number too large
│ │ +  [ 33f77]  wrong public key type
│ │ +  [ 33f8d]  wrong tag
│ │ +  [ 33f97]  illegal hex digit
│ │ +  [ 33fa9]  undefined generator
│ │ +  [ 33fbd]  unknown group
│ │ +  [ 33fcb]  wrong curve parameters
│ │ +  [ 33fe2]  ctrl command not implemented
│ │ +  [ 33fff]  no load function
│ │ +  [ 34010]  content not found
│ │ +  [ 34022]  unsupported encryption type
│ │ +  [ 3403e]  popo missing public key
│ │ +  [ 34056]  missing certid
│ │ +  [ 34065]  unrecognized signature nid
│ │ +  [ 34080]  rc2-64
│ │ +  [ 34087]  bf
│ │ +  [ 3408a]  CAST
│ │ +  [ 3408f]  id-aes128-wrap
│ │ +  [ 3409e]  AES192
│ │ +  [ 340a5]  aes192
│ │ +  [ 340ac]  crypto/evp/e_aria.c
│ │ +  [ 340c0]  assertion failed: ((ptr - sh.arena) & ((sh.arena_size >> list) - 1)) == 0
│ │ +  [ 3410a]  OSSL_PARAM_get_int32
│ │ +  [ 3411f]  module-filename
│ │ +  [ 3412f]  crypto/objects/o_names.c
│ │ +  [ 34148]  RSA Data Security, Inc.
│ │ +  [ 34160]  O
│ │ +  [ 34162]  pkcs7-signedAndEnvelopedData
│ │ +  [ 3417f]  DES-ECB
│ │ +  [ 34187]  idea-ecb
│ │ +  [ 34190]  contentType
│ │ +  [ 3419c]  Netscape
│ │ +  [ 341a5]  des-ede-cfb
│ │ +  [ 341b1]  Netscape Renewal Url
│ │ +  [ 341c6]  crlNumber
│ │ +  [ 341d0]  mdc2
│ │ +  [ 341d5]  surname
│ │ +  [ 341dd]  RC5-OFB
│ │ +  [ 341e5]  Microsoft Individual Code Signing
│ │ +  [ 34207]  S/MIME
│ │ +  [ 3420e]  id-smime-aa-receiptRequest
│ │ +  [ 34229]  id-smime-spq-ets-sqt-uri
│ │ +  [ 34242]  id-aca-accessIdentity
│ │ +  [ 34258]  dod
│ │ +  [ 3425c]  Hold Instruction Code
│ │ +  [ 34272]  Hold Instruction None
│ │ +  [ 34288]  documentAuthor
│ │ +  [ 34297]  subtreeMaximumQuality
│ │ +  [ 342ad]  set-policy
│ │ +  [ 342b8]  setct-PI
│ │ +  [ 342c1]  setct-AuthTokenTBS
│ │ +  [ 342d4]  setct-CertReqData
│ │ +  [ 342e6]  setct-AuthResTBE
│ │ +  [ 342f7]  setAttr-IssCap
│ │ +  [ 34306]  Microsoft Smartcard Login
│ │ +  [ 34320]  Inherit all
│ │ +  [ 3432c]  camellia-192-cfb1
│ │ +  [ 3433e]  CAMELLIA-192-CFB8
│ │ +  [ 34350]  id-PasswordBasedMAC
│ │ +  [ 34364]  ecdsa-with-SHA256
│ │ +  [ 34376]  GOST R 34.11-94 with GOST R 34.10-94
│ │ +  [ 3439b]  md_gost94
│ │ +  [ 343a5]  id-GostR3410-94-CryptoPro-XchA-ParamSet
│ │ +  [ 343cd]  aes-256-xts
│ │ +  [ 343d9]  RC4-HMAC-MD5
│ │ +  [ 343e6]  aes-192-cbc-hmac-sha1
│ │ +  [ 343fc]  dhSinglePass-stdDH-sha384kdf-scheme
│ │ +  [ 34420]  CAMELLIA-128-CTR
│ │ +  [ 34431]  id-tc26-agreement-gost-3410-2012-512
│ │ +  [ 34456]  issuerSignTool
│ │ +  [ 34465]  capwapWTP
│ │ +  [ 3446f]  KxDHE
│ │ +  [ 34475]  auth-dss
│ │ +  [ 3447e]  BLAKE2b512
│ │ +  [ 34489]  ARIA-256-CFB8
│ │ +  [ 34497]  sha3-384
│ │ +  [ 344a0]  ecdsa_with_SHA3-224
│ │ +  [ 344b4]  RSA-SHA3-384
│ │ +  [ 344c1]  aria-128-ccm
│ │ +  [ 344ce]  aria-192-gcm
│ │ +  [ 344db]  IEEE Security in Storage Working Group
│ │ +  [ 34502]  KMAC256
│ │ +  [ 3450a]  id-on-NAIRealm
│ │ +  [ 34519]  brainpoolP512r1tls13
│ │ +  [ 3452e]  zstd
│ │ +  [ 34533]  protRestrict
│ │ +  [ 34540]  responseBytes
│ │ +  [ 3454e]  certStatus
│ │ +  [ 34559]  ENCRYPTED PRIVATE KEY
│ │ +  [ 3456f]  PKCS7
│ │ +  [ 34575]  value.sdsicert
│ │ +  [ 34584]  PKCS12_item_i2d_encrypt_ex
│ │ +  [ 3459f]  key_enc_algor
│ │ +  [ 345ad]  enc_key
│ │ +  [ 345b5]  pkcs7_bio_add_digest
│ │ +  [ 345ca]  sha1 (default)
│ │ +  [ 345d9]  14 (default)
│ │ +  [ 345e6]  ossl_rsa_fromdata
│ │ +  [ 345f8]  mp r not prime
│ │ +  [ 34607]  crypto/srp/srp_lib.c
│ │ +  [ 3461c]  is not a
│ │ +  [ 34625]  unacceptable policy
│ │ +  [ 34639]  get_cert_by_subject_ex
│ │ +  [ 34650]  crypto/asn1/x_info.c
│ │ +  [ 34665]  d.usernotice
│ │ +  [ 34672]  %*sNumber%s: 
│ │ +  [ 34680]  %*sOnly Attribute Certificates\n
│ │ +  [ 346a0]  %*sCRL Issuer:\n
│ │ +  [ 346b0]  unspecified
│ │ +  [ 346bc]  /%d\n
│ │ +  [ 346c1]  OSSL_OBJECT_DIGEST_INFO
│ │ +  [ 346d9]  %*sDigest Type: Other\n
│ │ +  [ 346f0]  GENERAL_SUBTREE
│ │ +  [ 34700]  xn--
│ │ +  [ 34705]  notBefore
│ │ +  [ 3470f]  notAfter
│ │ +  [ 34718]  POLICY_MAPPING
│ │ +  [ 34727]  URI
│ │ +  [ 3472b]  crypto/x509/v3_sxnet.c
│ │ +  [ 34742]  zone
│ │ +  [ 34747]  Y
│ │ +  [ 34749]  -0x
│ │ +  [ 3474d]  bad object
│ │ +  [ 34758]  duplicate zone id
│ │ +  [ 3476a]  unknown purpose id
│ │ +  [ 3477d]  unknown sigid algs
│ │ +  [ 34790]  x509_sig_info_init
│ │ +  [ 347a3]  self-signed certificate in certificate chain
│ │ +  [ 347d0]  unsupported name constraint type
│ │ +  [ 347f1]  Suite B: curve not allowed for this LOS
│ │ +  [ 34819]  CA signature digest algorithm too weak
│ │ +  [ 34840]  X509_STORE_CTX_init
│ │ +  [ 34854]  crypto/x509/x_all.c
│ │ +  [ 34868]  crypto/x509/x_crl.c
│ │ +  [ 3487c]  failed to get platform info
│ │ +  [ 34898]  socket operation failed
│ │ +  [ 348b0]  ALG_PERR: %s(%d): Socket Accept Failed : 
│ │ +  [ 348da]  ALG_PERR: %s(%d): Failed to get eventfd : 
│ │ +  [ 34905]  provider=base,fips=yes,input=pvk
│ │ +  [ 34926]  SHAKE-256:SHAKE256:2.16.840.1.101.3.4.2.12
│ │ +  [ 34951]  DSA-SHA3-384:dsa_with_SHA3-384:id-dsa-with-sha3-384:2.16.840.1.101.3.4.3.7
│ │ +  [ 3499c]  provider=default,fips=yes,output=msblob
│ │ +  [ 349c4]  AES-256-CBC:AES256:2.16.840.1.101.3.4.1.42
│ │ +  [ 349ef]  AES-256-GCM:id-aes256-GCM:2.16.840.1.101.3.4.1.46
│ │ +  [ 34a21]  AES-128-GCM:id-aes128-GCM:2.16.840.1.101.3.4.1.6
│ │ +  [ 34a52]  DES-EDE3-ECB:DES-EDE3
│ │ +  [ 34a68]  secp256r1
│ │ +  [ 34a72]  ossl_blake2b_get_ctx_params
│ │ +  [ 34a8e]  SM2 PARAMETERS
│ │ +  [ 34a9d]  providers/implementations/encode_decode/decode_spki2typespki.c
│ │ +  [ 34adc]  rsapss_to_SubjectPublicKeyInfo_pem_encode
│ │ +  [ 34b06]  dh_to_PrivateKeyInfo_pem_encode
│ │ +  [ 34b26]  dh_to_SubjectPublicKeyInfo_pem_encode
│ │ +  [ 34b4c]  dhx_to_EncryptedPrivateKeyInfo_der_encode
│ │ +  [ 34b76]  dsa_to_PrivateKeyInfo_der_encode
│ │ +  [ 34b97]  ed25519_to_SubjectPublicKeyInfo_der_encode
│ │ +  [ 34bc2]  x4482text_encode
│ │ +  [ 34bd3]  rsa_to_text
│ │ +  [ 34bdf]  rsapss2text_encode
│ │ +  [ 34bf2]  sskdf_derive
│ │ +  [ 34bff]  x942kdf_size
│ │ +  [ 34c0c]  dhkem_encap
│ │ +  [ 34c18]  mac_key_fromdata
│ │ +  [ 34c29]  Given path=%s
│ │ +  [ 34c37]  file_open_stream
│ │ +  [ 34c48]  obj
│ │ +  [ 34c4c]  length too large
│ │ +  [ 34c5d]  unsupported cek alg
│ │ +  [ 34c71]  props
│ │ +  [ 34c77]  nt-format
│ │ +  [ 34c81]  nv
│ │ +  [ 34c84]  eparator
│ │ +  [ 34c8d]  ssl_encapsulate
│ │ +  [ 34c9d]  AES128-GCM-SHA256
│ │ +  [ 34caf]  TLS_DH_anon_WITH_AES_128_GCM_SHA256
│ │ +  [ 34cd3]  DHE-PSK-AES128-CCM
│ │ +  [ 34ce6]  ECDHE-ECDSA-AES128-CCM8
│ │ +  [ 34cfe]  TLS_DHE_PSK_WITH_NULL_SHA384
│ │ +  [ 34d1b]  TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256
│ │ +  [ 34d45]  TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256
│ │ +  [ 34d73]  DHE-DSS-CAMELLIA256-SHA256
│ │ +  [ 34d8e]  TLS_EMPTY_RENEGOTIATION_INFO_SCSV
│ │ +  [ 34db0]  ssl3_finish_mac
│ │ +  [ 34dc0]  SSL for verify callback
│ │ +  [ 34dd8]  kuznyechik-mac
│ │ +  [ 34de7]  kECDHE
│ │ +  [ 34dee]  kPSK
│ │ +  [ 34df3]  kDHEPSK
│ │ +  [ 34dfb]  aGOST
│ │ +  [ 34e01]  AECDH
│ │ +  [ 34e07]  bad digest length
│ │ +  [ 34e19]  ccs received early
│ │ +  [ 34e2c]  compression disabled
│ │ +  [ 34e41]  ee key too small
│ │ +  [ 34e52]  parse tlsext
│ │ +  [ 34e5f]  private key mismatch
│ │ +  [ 34e74]  read bio not set
│ │ +  [ 34e85]  ssl/tls alert handshake failure
│ │ +  [ 34ea5]  stream recv only
│ │ +  [ 34eb6]  too much early data
│ │ +  [ 34eca]  unknown key exchange type
│ │ +  [ 34ee4]  unsupported compression algorithm
│ │ +  [ 34f06]  SSL_new
│ │ +  [ 34f0e]  ossl_bytes_to_cipher_list
│ │ +  [ 34f28]  no_anti_replay
│ │ +  [ 34f37]  KTLSTxZerocopySendfile
│ │ +  [ 34f4e]  RequirePostHandshake
│ │ +  [ 34f63]  tls1_setup_key_block
│ │ +  [ 34f78]  master secret
│ │ +  [ 34f86]  tls1_PRF
│ │ +  [ 34f8f]  tls-sigalg-name
│ │ +  [ 34f9f]  ecdsa_sha224
│ │ +  [ 34fac]  tls13_hkdf_expand_ex
│ │ +  [ 34fc1]  tls13_hkdf_expand
│ │ +  [ 34fd3]  ssl/tls_depr.c
│ │ +  [ 34fe2]  ossl_quic_pending_int
│ │ +  [ 34ff8]  ssl/quic/quic_engine.c
│ │ +  [ 3500f]  ORIG_DCID does not match expected value
│ │ +  [ 35037]  ACTIVE_CONN_ID_LIMIT appears multiple times
│ │ +  [ 35063]  ACTIVE_CONN_ID_LIMIT is malformed
│ │ +  [ 35085]  common_fields
│ │ +  [ 35093]  ossl_quic_rstream_queue_data
│ │ +  [ 350b0]  depack_do_frame_new_token
│ │ +  [ 350ca]  PING
│ │ +  [ 350cf]  MAX_STREAMS_UNI
│ │ +  [ 350df]  HANDSHAKE_DONE
│ │ +  [ 350ee]  PROTOCOL_VIOLATION
│ │ +  [ 35101]  INVALID_TOKEN
│ │ +  [ 3510f]  block_padding
│ │ +  [ 3511d]  stream_mac
│ │ +  [ 35128]  tls13_common_post_process_record
│ │ +  [ 35149]  final_ems
│ │ +  [ 35153]  tls_construct_ctos_sig_algs
│ │ +  [ 3516f]  tls_construct_ctos_post_handshake_auth
│ │ +  [ 35196]  tls_parse_ctos_key_share
│ │ +  [ 351af]  tls_construct_stoc_cryptopro_bug
│ │ +  [ 351d0]  ossl_statem_server_process_message
│ │ +  [ 351f3]  ASN1_get_object
│ │ +  [ 35203]  <ASN1 13>
│ │ +  [ 3520d]  cons: 
│ │ +  [ 35214]  ZINT64
│ │ +  [ 3521b]  ASYNC_init_thread
│ │ +  [ 3522d]  non-fatal or transient error
│ │ +  [ 3524a]  crypto/bn/bn_rand.c
│ │ +  [ 3525e]  ossl_bn_priv_rand_range_fixed_top
│ │ +  [ 35280]  SHA512
│ │ +  [ 35287]  group=%s name=%s
│ │ +  [ 35298]  INT
│ │ +  [ 3529c]  ASN1_STRING_TABLE_add
│ │ +  [ 352b2]  ossl_dh_compute_key
│ │ +  [ 352c6]  pub_key
│ │ +  [ 352ce]  OpenSSL EC algorithm
│ │ +  [ 352e3]  EC_GROUP_new_from_ecparameters
│ │ +  [ 35302]  i2d_ECParameters
│ │ +  [ 35313]  d2i_ECParameters
│ │ +  [ 35324]  ossl_ec_key_param_from_x509_algor
│ │ +  [ 35346]  RFC 5639 curve over a 224 bit prime field
│ │ +  [ 35370]  ossl_ec_group_set_params
│ │ +  [ 35389]  crypto/ec/ec_mult.c
│ │ +  [ 3539d]  ossl_ec_GFp_mont_field_mul
│ │ +  [ 353b8]  OpenSSL ED448 algorithm
│ │ +  [ 353d0]  No decoders were found. For standard decoders you need at least one of the default or base providers available. Did you forget to load them?
│ │ +  [ 3545d]  Input structure: 
│ │ +  [ 3546f]  data-type
│ │ +  [ 35479]  crypto/encode_decode/decoder_meth.c
│ │ +  [ 3549d]  engine_id
│ │ +  [ 354a7]  crypto/engine/tb_digest.c
│ │ +  [ 354c1]  secp112r2
│ │ +  [ 354cb]  sect131r1
│ │ +  [ 354d5]  EVP_PKEY_CTX_set_group_name
│ │ +  [ 354f1]  asn1_oct_int
│ │ +  [ 354fe]  evp_keymgmt_util_copy
│ │ +  [ 35514]  rsa_padding_mode
│ │ +  [ 35525]  oaep
│ │ +  [ 3552a]  rsa-exponent1
│ │ +  [ 35538]  rsa-exponent6
│ │ +  [ 35546]  ffdhe6144
│ │ +  [ 35550]  Got number %d when expecting %d
│ │ +  [ 35570]  peer key error
│ │ +  [ 3557f]  cache constants failed
│ │ +  [ 35596]  invalid seed length
│ │ +  [ 355aa]  p not prime
│ │ +  [ 355b6]  illegal null
│ │ +  [ 355c3]  illegal options on item template
│ │ +  [ 355e4]  invalid separator
│ │ +  [ 355f6]  unknown signature algorithm
│ │ +  [ 35612]  unknown tag
│ │ +  [ 3561e]  hex string too short
│ │ +  [ 35633]  provider section error
│ │ +  [ 3564a]  group2pkparameters failure
│ │ +  [ 35665]  invalid output length
│ │ +  [ 3567b]  conflicting engine id
│ │ +  [ 35691]  failed loading private key
│ │ +  [ 356ac]  redirection from https to http
│ │ +  [ 356cb]  error getting public key
│ │ +  [ 356e4]  error setting recipientinfo
│ │ +  [ 35700]  invalid encrypted key length
│ │ +  [ 3571d]  multiple san sources
│ │ +  [ 35732]  log conf missing key
│ │ +  [ 35747]  blowfish
│ │ +  [ 35750]  RSA-SHA1-2
│ │ +  [ 3575b]  Specifies the path to the new ENGINE shared library
│ │ +  [ 3578f]  general_get_uint
│ │ +  [ 357a0]  ossl_pw_get_passphrase
│ │ +  [ 357b7]  RC2-OFB
│ │ +  [ 357bf]  dsaEncryption-old
│ │ +  [ 357d1]  X509v3 Basic Constraints
│ │ +  [ 357ea]  X509v3 CRL Reason Code
│ │ +  [ 35801]  PBE-SHA1-3DES
│ │ +  [ 3580f]  pkcs8ShroudedKeyBag
│ │ +  [ 35823]  localKeyID
│ │ +  [ 3582e]  x509Crl
│ │ +  [ 35836]  PBE-MD2-RC2-64
│ │ +  [ 35845]  id-smime-ct-TDTInfo
│ │ +  [ 35859]  id-smime-aa-ets-archiveTimeStamp
│ │ +  [ 3587a]  id-smime-aa-signatureType
│ │ +  [ 35894]  id-smime-alg-ESDHwith3DES
│ │ +  [ 358ae]  id-cct
│ │ +  [ 358b5]  id-mod-attribute-cert
│ │ +  [ 358cb]  id-regCtrl
│ │ +  [ 358d6]  id-cmc-statusInfo
│ │ +  [ 358e8]  id-cmc-senderNonce
│ │ +  [ 358fb]  id-cmc-decryptedPOP
│ │ +  [ 3590f]  serviceLocator
│ │ +  [ 3591e]  Microsoft CSP Name
│ │ +  [ 35931]  aes-128-cfb
│ │ +  [ 3593d]  Hold Instruction Reject
│ │ +  [ 35955]  roomNumber
│ │ +  [ 35960]  manager
│ │ +  [ 35968]  content types
│ │ +  [ 35976]  setct-PIDataUnsigned
│ │ +  [ 3598b]  setct-CredRevReqTBS
│ │ +  [ 3599f]  setct-AuthReqTBE
│ │ +  [ 359b0]  setct-CapTokenTBEX
│ │ +  [ 359c3]  set-policy-root
│ │ +  [ 359d3]  aes-128-cfb1
│ │ +  [ 359e0]  AES-192-CFB8
│ │ +  [ 359ed]  CAMELLIA-192-OFB
│ │ +  [ 359fe]  hmacWithSHA384
│ │ +  [ 35a0d]  id-GostR3411-94-with-GostR3410-2001
│ │ +  [ 35a31]  id-GostR3411-94-CryptoProParamSet
│ │ +  [ 35a53]  GOST 34.10-94 Cryptocom
│ │ +  [ 35a6b]  LocalKeySet
│ │ +  [ 35a77]  AES-128-CTR
│ │ +  [ 35a83]  AES-256-CTR
│ │ +  [ 35a8f]  rc4-hmac-md5
│ │ +  [ 35a9c]  dhSinglePass-cofactorDH-sha224kdf-scheme
│ │ +  [ 35ac5]  jurisdictionL
│ │ +  [ 35ad3]  CAMELLIA-192-GCM
│ │ +  [ 35ae4]  id-scrypt
│ │ +  [ 35aee]  capwapAC
│ │ +  [ 35af7]  kx-ecdhe
│ │ +  [ 35b00]  BLAKE2s256
│ │ +  [ 35b0b]  SM4-OFB
│ │ +  [ 35b13]  sm-scheme
│ │ +  [ 35b1d]  GOST R 34.10-2012 (512 bit) ParamSet C
│ │ +  [ 35b44]  DSTU 4145-2002 little endian
│ │ +  [ 35b61]  uacurve7
│ │ +  [ 35b6a]  DSTU curve 8
│ │ +  [ 35b77]  magma-ctr-acpkm
│ │ +  [ 35b87]  magma-cbc
│ │ +  [ 35b91]  hmacWithSHA512-256
│ │ +  [ 35ba4]  BLAKE2BMAC
│ │ +  [ 35baf]  CMC Archive Server
│ │ +  [ 35bc2]  cmKGA
│ │ +  [ 35bc8]  ms-app-policies
│ │ +  [ 35bd8]  acceptableCertPolicies
│ │ +  [ 35bef]  value.byName
│ │ +  [ 35bfc]  error in nextupdate field
│ │ +  [ 35c16]  no revoked time
│ │ +  [ 35c26]  keyblob too short
│ │ +  [ 35c38]  Proc-Type: 4,%s\n
│ │ +  [ 35c49]  PEM_write_bio
│ │ +  [ 35c57]  pem_read_bio_key_legacy
│ │ +  [ 35c6f]  attrib
│ │ +  [ 35c76]  PBMAC1_get1_pbkdf2_param
│ │ +  [ 35c8f]  PKCS12_verify_mac
│ │ +  [ 35ca1]  mac absent
│ │ +  [ 35cac]  parse error
│ │ +  [ 35cb8]  PKCS7_find_digest
│ │ +  [ 35cca]  crypto/pkcs7/pk7_attr.c
│ │ +  [ 35ce2]  seed_properties
│ │ +  [ 35cf2]  entropy_factor=%u, entropy_needed=%zu, bytes_needed=%zu,pool->max_len=%zu, pool->len=%zu
│ │ +  [ 35d4b]  ossl_rsa_param_decode
│ │ +  [ 35d61]  rsa_ossl_private_decrypt
│ │ +  [ 35d7a]  crypto/rsa/rsa_none.c
│ │ +  [ 35d90]  ossl_rsa_sp800_56b_check_public
│ │ +  [ 35db0]  ossl_store_get0_loader_int
│ │ +  [ 35dcb]  assertion failed: rc == 0
│ │ +  [ 35de5]  pqualid
│ │ +  [ 35ded]  (null)
│ │ +  [ 35df4]  Cessation Of Operation
│ │ +  [ 35e0b]   (Unicast)
│ │ +  [ 35e16]  :\n
│ │ +  [ 35e19]  [%d]
│ │ +  [ 35e1e]  ASRange
│ │ +  [ 35e26]  %*sCertificate Digest Info:\n
│ │ +  [ 35e43]  %*s  admissionAuthorityId: 
│ │ +  [ 35e5f]  inhibitPolicyMapping
│ │ +  [ 35e74]  IP Address
│ │ +  [ 35e7f]  <No Attributes>\n
│ │ +  [ 35e90]  v2i_TLS_FEATURE
│ │ +  [ 35ea0]  invalid proxy policy setting
│ │ +  [ 35ebd]  no crl number
│ │ +  [ 35ecb]  NO X509_NAME
│ │ +  [ 35ed8]  key usage does not include certificate signing
│ │ +  [ 35f07]  unhandled critical extension
│ │ +  [ 35f24]  unhandled critical CRL extension
│ │ +  [ 35f45]  Suite B: invalid public key algorithm
│ │ +  [ 35f6b]  proxy subject name violation
│ │ +  [ 35f88]  OCSP unknown cert
│ │ +  [ 35f9a]  Cannot find certificate signature algorithm
│ │ +  [ 35fc6]  cert info signature and signature algorithm mismatch
│ │ +  [ 35ffb]  X509_VERIFY_PARAM_set1_policies
│ │ +  [ 3601b]  provider=base,fips=no,output=text
│ │ +  [ 3603d]  provider=base,fips=yes,input=der,structure=EncryptedPrivateKeyInfo
│ │ +  [ 36080]  SHA1:SHA-1:SSL3-SHA1:1.3.14.3.2.26
│ │ +  [ 360a3]  BLAKE2B-512:BLAKE2b512:1.3.6.1.4.1.1722.12.2.1.16
│ │ +  [ 360d5]  RIPEMD-160:RIPEMD160:RIPEMD:RMD160:1.3.36.3.2.1
│ │ +  [ 36105]  X963KDF:X942KDF-CONCAT
│ │ +  [ 3611c]  DSA-SHA2-224:DSA-SHA224:dsa_with_SHA224:2.16.840.1.101.3.4.3.1
│ │ +  [ 3615b]  DSA-SHA2-512:DSA-SHA512:dsa_with_SHA512:id-dsa-with-sha512:1.2.840.1.101.3.4.3.4
│ │ +  [ 361ac]  RSA-SHA3-256:id-rsassa-pkcs1-v1_5-with-sha3-256:2.16.840.1.101.3.4.3.14
│ │ +  [ 361f4]  ECDSA-SHA1:ECDSA-SHA-1:ecdsa-with-SHA1:1.2.840.10045.4.1
│ │ +  [ 3622d]  provider=default,fips=no,output=der,structure=type-specific
│ │ +  [ 36269]  ARIA-256-CTR:1.2.410.200046.1.1.15
│ │ +  [ 3628c]  engine
│ │ +  [ 36293]  invalid operation: %d
│ │ +  [ 362a9]  C1y
│ │ +  [ 362ad]  aes_wrap_cipher_internal
│ │ +  [ 362c6]  sm4_xts_cipher
│ │ +  [ 362d5]  tdes_init
│ │ +  [ 362df]  ossl_blake2s_set_ctx_params
│ │ +  [ 362fb]  ossl_do_blob_header
│ │ +  [ 3630f]  do_PVK_body_key
│ │ +  [ 3631f]  RSA PUBLIC KEY
│ │ +  [ 3632e]  dhx_to_X9_42_pem_encode
│ │ +  [ 36346]  dsa2pvk_encode
│ │ +  [ 36355]  kdf-digest-props
│ │ +  [ 36366]  kdf_argon2_ctx_set_threads
│ │ +  [ 36381]  invalid Argon2 version
│ │ +  [ 36398]  scrypt_alg
│ │ +  [ 363a3]  sskdf_common_set_ctx_params
│ │ +  [ 363bf]  shared_secret
│ │ +  [ 363cd]  Invalid recipient public key
│ │ +  [ 363ea]  max_noncelen
│ │ +  [ 363f7]  drbg_ctr_init
│ │ +  [ 36405]  /dev/hwrng
│ │ +  [ 36410]  Should be more than %d, but would be set to %d
│ │ +  [ 3643f]  indicator integrity failure
│ │ +  [ 3645b]  vp-info
│ │ +  [ 36463]  ng
│ │ +  [ 36466]  utlen
│ │ +  [ 3646c]  datory-digest
│ │ +  [ 3647a]  -info
│ │ +  [ 36480]  ign-x931-pad-disabled
│ │ +  [ 36496]  ndfrag
│ │ +  [ 3649d]  TLS_AES_128_CCM_8_SHA256
│ │ +  [ 364b6]  TLS_RSA_WITH_AES_128_CCM
│ │ +  [ 364cf]  PSK-AES128-CCM
│ │ +  [ 364de]  AECDH-NULL-SHA
│ │ +  [ 364ed]  ECDHE-RSA-AES128-GCM-SHA256
│ │ +  [ 36509]  TLS_PSK_WITH_AES_128_CBC_SHA256
│ │ +  [ 36529]  DHE-PSK-NULL-SHA384
│ │ +  [ 3653d]  RSA-PSK-AES256-CBC-SHA384
│ │ +  [ 36557]  DHE-PSK-CHACHA20-POLY1305
│ │ +  [ 36571]  CAMELLIA256-SHA256
│ │ +  [ 36584]  DHE-DSS-CAMELLIA256-SHA
│ │ +  [ 3659c]  DHE-PSK-CAMELLIA256-SHA384
│ │ +  [ 365b7]  TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256
│ │ +  [ 365e0]  TLS_ECDHE_ECDSA_WITH_ARIA_256_GCM_SHA384
│ │ +  [ 36609]  verify_result
│ │ +  [ 36617]  DEFAULT
│ │ +  [ 3661f]  kRSAPSK
│ │ +  [ 36627]  EECDH
│ │ +  [ 3662d]  block cipher pad is wrong
│ │ +  [ 36647]  dh public value length is wrong
│ │ +  [ 36667]  invalid serverinfo data
│ │ +  [ 3667f]  not on record boundary
│ │ +  [ 36696]  records not released
│ │ +  [ 366ab]  shutdown while in init
│ │ +  [ 366c2]  ssl/tls alert certificate unknown
│ │ +  [ 366e4]  stream reset
│ │ +  [ 366f1]  tx_cert_comp
│ │ +  [ 366fe]  no_middlebox
│ │ +  [ 3670b]  ClientRenegotiation
│ │ +  [ 3671f]  ExtendedMasterSecret
│ │ +  [ 36734]  Request
│ │ +  [ 3673c]  ecdsa_secp256r1_sha256
│ │ +  [ 36753]  rsa_pss_pss_sha512
│ │ +  [ 36766]  prefix
│ │ +  [ 3676d]  tls13_change_cipher_state
│ │ +  [ 36787]  SERVER_TRAFFIC_SECRET_N
│ │ +  [ 3679f]  srp_generate_server_master_secret
│ │ +  [ 367c1]  internal error (packet buf init)
│ │ +  [ 367e2]  DISABLE_ACTIVE_MIGRATION appears multiple times
│ │ +  [ 36812]  transport:parameters_set
│ │ +  [ 3682b]  Post-handshake TLS CertificateRequest received
│ │ +  [ 3685a]  ch_tick_tls
│ │ +  [ 36866]  qlog_version
│ │ +  [ 36873]  packet_lost
│ │ +  [ 3687f]  transport:packet_received
│ │ +  [ 36899]  handshake_confirmed
│ │ +  [ 368ad]  CRYPTO frame not valid in 0-RTT
│ │ +  [ 368cd]  AES-128-ECB
│ │ +  [ 368d9]  ssl/quic/quic_types.c
│ │ +  [ 368ef]  ACK_WITHOUT_ECN
│ │ +  [ 368ff]  MAX_DATA
│ │ +  [ 36908]  STREAMS_BLOCKED_BIDI
│ │ +  [ 3691d]  tls_construct_ctos_sct
│ │ +  [ 36934]  tls_parse_stoc_use_srtp
│ │ +  [ 3694c]  tls_parse_ctos_status_request
│ │ +  [ 3696a]  tls_construct_stoc_supported_versions
│ │ +  [ 36990]  tls_process_key_exchange
│ │ +  [ 369a9]  ossl_statem_server_construct_message
│ │ +  [ 369ce]  tls_process_client_hello
│ │ +  [ 369e7]  tls_construct_server_certificate
│ │ +  [ 36a08]  tls_process_cke_psk_preamble
│ │ +  [ 36a25]  ASN1_item_dup
│ │ +  [ 36a33]  asn1_get_int64
│ │ +  [ 36a42]  crypto/asn1/a_mbstr.c
│ │ +  [ 36a58]  %4d-%02d-%02d %02d:%02d:%02d%s
│ │ +  [ 36a77]  tfo disabled
│ │ +  [ 36a84]  local address not available
│ │ +  [ 36aa0]  BIO_sendmmsg
│ │ +  [ 36aad]  ossl_bn_gen_dsa_nonce_fixed_top
│ │ +  [ 36acd]  bnrand_range
│ │ +  [ 36ada]  crypto/bn/bn_recp.c
│ │ +  [ 36aee]  BN_rshift
│ │ +  [ 36af8]  OpenSSL default
│ │ +  [ 36b08]  default
│ │ +  [ 36b10]  .cnf
│ │ +  [ 36b15]  crypto/asn1/asn_mstbl.c
│ │ +  [ 36b2d]  name=%s, value=%s
│ │ +  [ 36b3f]  OID
│ │ +  [ 36b43]  DH Parameters
│ │ +  [ 36b51]  bn_set_words
│ │ +  [ 36b5e]  counter
│ │ +  [ 36b66]  dh_new_intern
│ │ +  [ 36b74]  DSO_load
│ │ +  [ 36b7d]  EC_GROUP_check
│ │ +  [ 36b8c]  X9.62 curve over a 176 bit binary field
│ │ +  [ 36bb4]  ossl_ec_GF2m_simple_point_set_affine_coordinates
│ │ +  [ 36be5]  ec_GF2m_simple_ladder_pre
│ │ +  [ 36bff]  ossl_ec_scalar_mul_ladder
│ │ +  [ 36c19]  ossl_ec_GFp_mont_group_set_curve
│ │ +  [ 36c3a]  ecx_pub_encode
│ │ +  [ 36c49]  OSSL_DECODER_CTX_set_construct
│ │ +  [ 36c68]  OSSL_DECODER_CTX_new_for_pkey
│ │ +  [ 36c86]  object identifier routines
│ │ +  [ 36ca1]  engine routines
│ │ +  [ 36cb1]  BN lib
│ │ +  [ 36cb8]  X509 lib
│ │ +  [ 36cc1]  crypto/evp/digest.c
│ │ +  [ 36cd5]  crypto/evp/e_chacha20_poly1305.c
│ │ +  [ 36cf6]  Oakley-EC2N-3
│ │ +  [ 36d04]  brainpoolP384r1
│ │ +  [ 36d14]  ivlen
│ │ +  [ 36d1a]  EVP_KDF_CTX_dup
│ │ +  [ 36d2a]  crypto/evp/mac_lib.c
│ │ +  [ 36d3f]  crypto/evp/mac_meth.c
│ │ +  [ 36d55]  kdf-ukm
│ │ +  [ 36d5d]  d
│ │ +  [ 36d5f]  rsa-factor4
│ │ +  [ 36d6b]  fips186_2
│ │ +  [ 36d75]  fromdata_init
│ │ +  [ 36d83]  OpenSSL 3.4.0 22 Oct 2024
│ │ +  [ 36d9d]  div by zero
│ │ +  [ 36da9]  no inverse
│ │ +  [ 36db4]  bad generator
│ │ +  [ 36dc2]  cannot set parameters
│ │ +  [ 36dd8]  get raw key failed
│ │ +  [ 36deb]  invalid parameters
│ │ +  [ 36dfe]  bmpstring is wrong length
│ │ +  [ 36e18]  mandatory braces in variable expansion
│ │ +  [ 36e3f]  no value
│ │ +  [ 36e48]  explicit params not supported
│ │ +  [ 36e66]  invalid curve
│ │ +  [ 36e74]  ladder post failure
│ │ +  [ 36e88]  no filename
│ │ +  [ 36e94]  command takes no input
│ │ +  [ 36eab]  error parsing url
│ │ +  [ 36ebd]  max resp len exceeded
│ │ +  [ 36ed3]  unexpected content type
│ │ +  [ 36eeb]  msgsigdigest wrong length
│ │ +  [ 36f05]  type not compressed data
│ │ +  [ 36f1e]  failed extracting pubkey
│ │ +  [ 36f37]  RIPEMD160
│ │ +  [ 36f41]  assertion failed: temp-(sh.arena_size >> slist) == sh_find_my_buddy(temp, slist)
│ │ +  [ 36f92]  prepare_from_text
│ │ +  [ 36fa4]  RSA-MD5
│ │ +  [ 36fac]  pbeWithMD2AndDES-CBC
│ │ +  [ 36fc1]  DES-OFB
│ │ +  [ 36fc9]  countersignature
│ │ +  [ 36fda]  nsCertSequence
│ │ +  [ 36fe9]  authorityKeyIdentifier
│ │ +  [ 37000]  ripemd160
│ │ +  [ 3700a]  RC5-ECB
│ │ +  [ 37012]  codeSigning
│ │ +  [ 3701e]  dnQualifier
│ │ +  [ 3702a]  sbgp-routerIdentifier
│ │ +  [ 37040]  Extended OCSP Status
│ │ +  [ 37055]  documentTitle
│ │ +  [ 37063]  secretary
│ │ +  [ 3706d]  setct-PInitResData
│ │ +  [ 37080]  setct-BatchAdminReqData
│ │ +  [ 37098]  setext-genCrypt
│ │ +  [ 370a8]  setCext-TokenIdentifier
│ │ +  [ 370c0]  setAttr-T2cleartxt
│ │ +  [ 370d3]  nameConstraints
│ │ +  [ 370e3]  ppBasis
│ │ +  [ 370eb]  ecdsa-with-Specified
│ │ +  [ 37100]  id-GostR3410-94-b
│ │ +  [ 37112]  id-alg-PWRI-KEK
│ │ +  [ 37122]  aes-128-gcm
│ │ +  [ 3712e]  id-aes256-CCM
│ │ +  [ 3713c]  MGF1
│ │ +  [ 37141]  dhSinglePass-stdDH-sha512kdf-scheme
│ │ +  [ 37165]  id-tc26-algorithms
│ │ +  [ 37178]  GOST R 34.11-2012 with 512 bit hash
│ │ +  [ 3719c]  id-tc26-digest-constants
│ │ +  [ 371b5]  tlsfeature
│ │ +  [ 371c0]  aria-128-ecb
│ │ +  [ 371cd]  ARIA-192-CFB
│ │ +  [ 371da]  aria-256-cfb
│ │ +  [ 371e7]  dsa_with_SHA3-224
│ │ +  [ 371f9]  ARIA-256-GCM
│ │ +  [ 37206]  cmcCA
│ │ +  [ 3720c]  DSTU curve 5
│ │ +  [ 37219]  sm2
│ │ +  [ 3721d]  kuznyechik-ctr-acpkm
│ │ +  [ 37232]  sshkdf
│ │ +  [ 37239]  cades-attributes
│ │ +  [ 3724a]  timeSpecification
│ │ +  [ 3725c]  crypto/objects/obj_lib.c
│ │ +  [ 37275]  OCSP_CERTID
│ │ +  [ 37281]  crlNum
│ │ +  [ 37288]  error converting private key
│ │ +  [ 372a5]  missing dek iv
│ │ +  [ 372b4]  value.x509cert
│ │ +  [ 372c3]  crypto/pkcs12/p12_decr.c
│ │ +  [ 372dc]  maybe wrong password
│ │ +  [ 372f1]  PKCS7_ATTR_SIGN
│ │ +  [ 37301]  d.encrypted
│ │ +  [ 3730d]  serial
│ │ +  [ 37314]  crypto/rand/prov_seed.c
│ │ +  [ 3732c]  already instantiated
│ │ +  [ 37341]  entropy input too long
│ │ +  [ 37358]  error entropy pool was ignored
│ │ +  [ 37377]  random pool overflow
│ │ +  [ 3738c]  unable to get parent strength
│ │ +  [ 373aa]  ossl_rand_pool_bytes_needed
│ │ +  [ 373c6]  ossl_rand_pool_add
│ │ +  [ 373d9]  modulus:
│ │ +  [ 373e2]  Hash Algorithm: 
│ │ +  [ 373f3]  block type is not 02
│ │ +  [ 37408]  d e not congruent to 1
│ │ +  [ 3741f]  invalid x931 digest
│ │ +  [ 37433]  mp exponent not congruent to d
│ │ +  [ 37452]  oaep decoding error
│ │ +  [ 37466]  loader incomplete
│ │ +  [ 37478]  not a name
│ │ +  [ 37483]  common ok and cancel characters
│ │ +  [ 374a3]  index too large
│ │ +  [ 374b3]  result too small
│ │ +  [ 374c4]  UI_get_result_length
│ │ +  [ 374d9]  UI_set_result_ex
│ │ +  [ 374ea]  crypto/ui/ui_openssl.c
│ │ +  [ 37501]  Load certs from files in a directory
│ │ +  [ 37526]  decipherOnly
│ │ +  [ 37533]  CA
│ │ +  [ 37536]  onlyCA
│ │ +  [ 3753d]  onlyAA
│ │ +  [ 37544]  %*sFull Name:\n
│ │ +  [ 37553]  u.addressPrefix
│ │ +  [ 37563]  v2i_ASIdentifiers
│ │ +  [ 37575]  RDI
│ │ +  [ 37579]  %*sTarget Name: 
│ │ +  [ 3758a]  PROFESSION_INFO
│ │ +  [ 3759a]  %*s      %s%s%s%s\n
│ │ +  [ 375ad]  excluded
│ │ +  [ 375b6]  IP Address:%s
│ │ +  [ 375c4]  Registered ID:
│ │ +  [ 375d3]  s2i_ASN1_OCTET_STRING
│ │ +  [ 375e9]  s2i_ASN1_INTEGER
│ │ +  [ 375fa]  invalid trust
│ │ +  [ 37608]  X509_STORE_add_cert
│ │ +  [ 3761c]  X509_STORE_add_crl
│ │ +  [ 3762f]  %*sREAL
│ │ +  [ 37637]  lastUpdate
│ │ +  [ 37642]  provider=base,fips=yes,output=der,structure=dhx
│ │ +  [ 37672]  provider=base,fips=yes,output=der,structure=X9.42
│ │ +  [ 376a4]  KECCAK-256
│ │ +  [ 376af]  KECCAK-KMAC-128:KECCAK-KMAC128
│ │ +  [ 376ce]  GMAC:1.0.9797.3.4
│ │ +  [ 376e0]  X942KDF-ASN1:X942KDF
│ │ +  [ 376f5]  RSA-PSS:RSASSA-PSS:1.2.840.113549.1.1.10
│ │ +  [ 3771e]  ED448:1.3.101.113
│ │ +  [ 37730]  OpenSSL SCRYPT via EVP_PKEY implementation
│ │ +  [ 3775b]  provider=default,fips=yes,output=der,structure=SubjectPublicKeyInfo
│ │ +  [ 3779f]  provider=default,fips=no,output=pem,structure=EncryptedPrivateKeyInfo
│ │ +  [ 377e5]  AES-256-OFB:2.16.840.1.101.3.4.1.43
│ │ +  [ 37809]  AES-192-GCM-SIV
│ │ +  [ 37819]  AES-256-CCM:id-aes256-CCM:2.16.840.1.101.3.4.1.47
│ │ +  [ 3784b]  AES-256-WRAP-PAD:id-aes256-wrap-pad:AES256-WRAP-PAD:2.16.840.1.101.3.4.1.48
│ │ +  [ 37897]  aes_ocb_block_update_internal
│ │ +  [ 378b5]  siv_init
│ │ +  [ 378be]  providers/implementations/ciphers/cipher_aes_wrp.c
│ │ +  [ 378f1]  chacha20_get_ctx_params
│ │ +  [ 37909]  dh_to_type_specific_params_pem_encode
│ │ +  [ 3792f]  rsa_to_SubjectPublicKeyInfo_pem_encode
│ │ +  [ 37956]  ed25519_to_EncryptedPrivateKeyInfo_der_encode
│ │ +  [ 37984]  ed25519_to_EncryptedPrivateKeyInfo_pem_encode
│ │ +  [ 379b2]  h: %d\n
│ │ +  [ 379b9]  use-l
│ │ +  [ 379bf]  use-separator
│ │ +  [ 379cd]  providers/implementations/kdfs/sskdf.c
│ │ +  [ 379f4]  DES3-WRAP
│ │ +  [ 379fe]  secretsz invalid
│ │ +  [ 37a0f]  providers/implementations/kem/ecx_kem.c
│ │ +  [ 37a37]  kmac_setkey
│ │ +  [ 37a43]  min_noncelen
│ │ +  [ 37a50]  Ed25519
│ │ +  [ 37a58]  Ed25519ph
│ │ +  [ 37a62]  RSA key size = %d, expected minimum = %d
│ │ +  [ 37a8b]  failed during derivation
│ │ +  [ 37aa4]  fips module in error state
│ │ +  [ 37abf]  invalid input length
│ │ +  [ 37ad4]  invalid kdf
│ │ +  [ 37ae0]  ossl_cipher_generic_get_params
│ │ +  [ 37aff]  ossl_cipher_generic_block_final
│ │ +  [ 37b1f]  ossl_cipher_generic_stream_update
│ │ +  [ 37b41]  bg-no-trunc-md
│ │ +  [ 37b50]  dinlen
│ │ +  [ 37b57]  um_length
│ │ +  [ 37b61]  len
│ │ +  [ 37b65]  pe
│ │ +  [ 37b68]  sp
│ │ +  [ 37b6b]  TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
│ │ +  [ 37b8f]  DHE-RSA-AES256-SHA256
│ │ +  [ 37ba5]  TLS_RSA_WITH_AES_256_CCM_8
│ │ +  [ 37bc0]  ECDHE-ECDSA-AES256-CCM
│ │ +  [ 37bd7]  ECDHE-RSA-AES128-SHA
│ │ +  [ 37bec]  ECDHE-ECDSA-AES256-SHA384
│ │ +  [ 37c06]  TLS_RSA_PSK_WITH_AES_128_CBC_SHA
│ │ +  [ 37c27]  TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
│ │ +  [ 37c4b]  TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
│ │ +  [ 37c70]  ECDHE-PSK-CAMELLIA128-SHA256
│ │ +  [ 37c8d]  ECDHE-PSK-CAMELLIA256-SHA384
│ │ +  [ 37caa]  DHE-RSA-ARIA128-GCM-SHA256
│ │ +  [ 37cc5]  TLS_DHE_RSA_WITH_ARIA_256_GCM_SHA384
│ │ +  [ 37cea]  ECDHE-ARIA256-GCM-SHA384
│ │ +  [ 37d03]  TLS_PSK_WITH_ARIA_128_GCM_SHA256
│ │ +  [ 37d24]  DHE-PSK-ARIA256-GCM-SHA384
│ │ +  [ 37d3f]  session_id
│ │ +  [ 37d4a]  key_arg
│ │ +  [ 37d52]  ssl_verify_internal
│ │ +  [ 37d66]  TLS_AES_256_GCM_SHA384:TLS_CHACHA20_POLY1305_SHA256:TLS_AES_128_GCM_SHA256
│ │ +  [ 37db1]  ciphersuite_cb
│ │ +  [ 37dc0]  DHE
│ │ +  [ 37dc4]  bad early data
│ │ +  [ 37dd3]  bad hrr version
│ │ +  [ 37de3]  bad packet length
│ │ +  [ 37df5]  dtls message too big
│ │ +  [ 37e0a]  ecdh required for suiteb mode
│ │ +  [ 37e28]  invalid command
│ │ +  [ 37e38]  missing rsa certificate
│ │ +  [ 37e50]  missing supported versions extension
│ │ +  [ 37e75]  missing tmp ecdh key
│ │ +  [ 37e8a]  no cookie callback set
│ │ +  [ 37ea1]  tls illegal exporter label
│ │ +  [ 37ebc]  ssl/ssl_mcnf.c
│ │ +  [ 37ecb]  Curves
│ │ +  [ 37ed2]  verifyCAfile
│ │ +  [ 37edf]  EmptyFragments
│ │ +  [ 37eee]  DHSingle
│ │ +  [ 37ef7]  Require
│ │ +  [ 37eff]  g
│ │ +  [ 37f01]  rsa_pss_rsae_sha256
│ │ +  [ 37f15]  derive_secret_key_and_iv
│ │ +  [ 37f2e]  quic_do_handshake
│ │ +  [ 37f40]  ossl_quic_channel_raise_protocol_error_loc
│ │ +  [ 37f6b]  INITIAL_MAX_STREAM_DATA_BIDI_LOCAL is malformed
│ │ +  [ 37f9b]  ACK_DELAY_EXP appears multiple times
│ │ +  [ 37fc0]  STATELESS_RESET_TOKEN is malformed
│ │ +  [ 37fe3]  wb
│ │ +  [ 37fe6]  OpenSSL/%s (%s)
│ │ +  [ 37ff6]  header
│ │ +  [ 37ffd]  protocol_violation
│ │ +  [ 38010]  ssl/quic/quic_record_tx.c
│ │ +  [ 3802a]  DATA_BLOCKED valid only in 0/1-RTT
│ │ +  [ 3804d]  conn has zero-length CID
│ │ +  [ 38066]  ossl_quic_tx_packetiser_set_cur_scid
│ │ +  [ 3808b]  ssl3_write_bytes
│ │ +  [ 3809c]  ssl/record/methods/tls_common.c
│ │ +  [ 380bc]  final_key_share
│ │ +  [ 380cc]  tls_construct_ctos_key_share
│ │ +  [ 380e9]  tls_construct_stoc_server_name
│ │ +  [ 38108]  tls_construct_stoc_session_ticket
│ │ +  [ 3812a]  tls_parse_ctos_client_cert_type
│ │ +  [ 3814a]  ssl/statem/statem.c
│ │ +  [ 3815e]  ossl_statem_client_write_transition
│ │ +  [ 38182]  tls_process_server_rpk
│ │ +  [ 38199]  tls_construct_cke_rsa
│ │ +  [ 381af]  tls_process_cke_gost
│ │ +  [ 381c4]  , 
│ │ +  [ 381c7]  ASN1_item_ex_i2d
│ │ +  [ 381d8]  async_release_job
│ │ +  [ 381ea]  <NULL>
│ │ +  [ 381f1]  dgram_mem_read
│ │ +  [ 38200]  NULL\n
│ │ +  [ 38206]  PBE2PARAM
│ │ +  [ 38210]  str_copy
│ │ +  [ 38219]  parsebool
│ │ +  [ 38223]  params.q
│ │ +  [ 3822c]  DSO_get_filename
│ │ +  [ 3823d]  symname(%s): %s
│ │ +  [ 3824d]  fieldID
│ │ +  [ 38255]  X9.62 curve over a 191 bit binary field
│ │ +  [ 3827d]  BN_GF2m_mod_solve_quad_arr
│ │ +  [ 38298]  ossl_ec_key_simple_check_key
│ │ +  [ 382b5]  ossl_ec_GF2m_simple_point2oct
│ │ +  [ 382d3]  ecdsa_sign_setup
│ │ +  [ 382e4]  crypto/ec/ecp_mont.c
│ │ +  [ 382f9]  ossl_ec_GFp_simple_set_compressed_coordinates
│ │ +  [ 38327]  ossl_ec_GFp_simple_oct2point
│ │ +  [ 38344]  int_engine_configure
│ │ +  [ 38359]  crypto/engine/eng_ctrl.c
│ │ +  [ 38372]  UI lib
│ │ +  [ 38379]  secp192k1
│ │ +  [ 38383]  prime239v2
│ │ +  [ 3838e]  brainpoolP224t1
│ │ +  [ 3839e]  K-409
│ │ +  [ 383a4]  tls1multi_enclen
│ │ +  [ 383b5]  custom-iv
│ │ +  [ 383bf]  evp_pkcs82pkey_legacy
│ │ +  [ 383d5]  evp_keyexch_from_algorithm
│ │ +  [ 383f0]  evp_pkey_ctx_ctrl_to_param
│ │ +  [ 3840b]  dsa_paramgen_bits
│ │ +  [ 3841d]  bad reciprocal
│ │ +  [ 3842c]  aes key setup failed
│ │ +  [ 38441]  invalid iv length
│ │ +  [ 38453]  no keymgmt available
│ │ +  [ 38468]  signature type and key type incompatible
│ │ +  [ 38491]  invalid digest type
│ │ +  [ 384a5]  q not prime
│ │ +  [ 384b1]  expecting an integer
│ │ +  [ 384c6]  short line
│ │ +  [ 384d1]  unknown name in random section
│ │ +  [ 384f0]  cleanup method function failed
│ │ +  [ 3850f]  unimplemented digest
│ │ +  [ 38524]  cipher aead set tag error
│ │ +  [ 3853e]  ctrl error
│ │ +  [ 38549]  unwrap failure
│ │ +  [ 38558]  certhash unmatched
│ │ +  [ 3856b]  DES-EDE
│ │ +  [ 38573]  des-ede3-ecb
│ │ +  [ 38580]  ARIA192
│ │ +  [ 38588]  assertion failed: sh_testbit(ptr, list, sh.bittable)
│ │ +  [ 385bd]  Prompt info data type incorrect
│ │ +  [ 385dd]  pass phrase
│ │ +  [ 385e9]  X500
│ │ +  [ 385ee]  Netscape Certificate Sequence
│ │ +  [ 3860c]  X509v3 CRL Number
│ │ +  [ 3861e]  uid
│ │ +  [ 38622]  uniqueIdentifier
│ │ +  [ 38633]  RC5-CBC
│ │ +  [ 3863b]  pbeWithSHA1And40BitRC2-CBC
│ │ +  [ 38656]  msExtReq
│ │ +  [ 3865f]  sbgp-ipAddrBlock
│ │ +  [ 38670]  id-it-caKeyUpdateInfo
│ │ +  [ 38686]  id-regCtrl-pkiPublicationInfo
│ │ +  [ 386a4]  DOD
│ │ +  [ 386a8]  id-aca-encAttrs
│ │ +  [ 386b8]  targetInformation
│ │ +  [ 386ca]  noRevAvail
│ │ +  [ 386d5]  X509v3 No Revocation Available
│ │ +  [ 386f4]  pilotObjectClass
│ │ +  [ 38705]  simpleSecurityObject
│ │ +  [ 3871a]  mail
│ │ +  [ 3871f]  documentVersion
│ │ +  [ 3872f]  lastModifiedTime
│ │ +  [ 38740]  setAttr-Token-EMV
│ │ +  [ 38752]  generate cryptogram
│ │ +  [ 38766]  International Organizations
│ │ +  [ 38782]  DES-CFB8
│ │ +  [ 3878b]  CAMELLIA-128-ECB
│ │ +  [ 3879c]  seed-ofb
│ │ +  [ 387a5]  caRepository
│ │ +  [ 387b2]  CA Repository
│ │ +  [ 387c0]  ecdsa-with-SHA512
│ │ +  [ 387d2]  id-Gost28147-89-CryptoPro-Oscar-1-1-ParamSet
│ │ +  [ 387ff]  id-GostR3410-94-CryptoPro-B-ParamSet
│ │ +  [ 38824]  id-GostR3410-2001-CryptoPro-A-ParamSet
│ │ +  [ 3884b]  postalAddress
│ │ +  [ 38859]  x121Address
│ │ +  [ 38865]  dhSinglePass-cofactorDH-sha1kdf-scheme
│ │ +  [ 3888c]  CT Precertificate Poison
│ │ +  [ 388a5]  scrypt
│ │ +  [ 388ac]  GOST R 34.10-2012 with 256 bit modulus
│ │ +  [ 388d3]  GOST R 34.11-2012 with 256 bit hash
│ │ +  [ 388f7]  SSH Server
│ │ +  [ 38902]  KxPSK
│ │ +  [ 38908]  AuthDSS
│ │ +  [ 38910]  Poly1305
│ │ +  [ 38919]  auth-any
│ │ +  [ 38922]  aria-128-ctr
│ │ +  [ 3892f]  ARIA-192-CTR
│ │ +  [ 3893c]  aria-192-cfb1
│ │ +  [ 3894a]  SHA3-256
│ │ +  [ 38953]  CMC Certificate Authority
│ │ +  [ 3896d]  sm4-cbc
│ │ +  [ 38975]  DSTU curve 2
│ │ +  [ 38982]  DSTU curve 3
│ │ +  [ 3898f]  id-tc26-gost-3410-2012-256-paramSetB
│ │ +  [ 389b4]  KMAC128
│ │ +  [ 389bc]  aes-128-siv
│ │ +  [ 389c8]  Class of Signing Tool KB1
│ │ +  [ 389e2]  SM4-CCM
│ │ +  [ 389ea]  brotli
│ │ +  [ 389f1]  Microsoft NTDS AD objectSid
│ │ +  [ 38a0d]  ms-ntds-sec-ext
│ │ +  [ 38a1d]  basicAttConstraints
│ │ +  [ 38a31]  short header
│ │ +  [ 38a3e]  value.bag
│ │ +  [ 38a48]  PKCS7_ctrl
│ │ +  [ 38a53]  ossl_parse_query
│ │ +  [ 38a64]  crypto/property/property_string.c
│ │ +  [ 38a86]  max_request
│ │ +  [ 38a92]  drbg not initialised
│ │ +  [ 38aa7]  unable to lock parent
│ │ +  [ 38abd]  Private-Key: (%d bit, %d primes)\n
│ │ +  [ 38adf]  exponent1:
│ │ +  [ 38aea]  (INVALID PSS PARAMETERS)\n
│ │ +  [ 38b04]  iqmp
│ │ +  [ 38b09]  mgf
│ │ +  [ 38b0d]  invalid strength
│ │ +  [ 38b1e]  no public exponent
│ │ +  [ 38b31]  crypto/rsa/rsa_saos.c
│ │ +  [ 38b47]  ossl_rsa_fips186_4_gen_prob_primes
│ │ +  [ 38b6a]  not a public key
│ │ +  [ 38b7b]  OSSL_STORE_LOADER_get0_provider
│ │ +  [ 38b9b]  /dev/tty
│ │ +  [ 38ba4]  keyid
│ │ +  [ 38baa]  certificateHold
│ │ +  [ 38bba]  %*sIndirect CRL\n
│ │ +  [ 38bcb]  asnum
│ │ +  [ 38bd1]  %*s%s-
│ │ +  [ 38bd8]  %*sPath Length Constraint: 
│ │ +  [ 38bf4]  POLICY_MAPPINGS
│ │ +  [ 38c04]  setup_dp
│ │ +  [ 38c0d]  X400Name
│ │ +  [ 38c16]  i2s_ASN1_UTF8STRING
│ │ +  [ 38c2a]  x509v3_add_len_value
│ │ +  [ 38c3f]  bad ip address
│ │ +  [ 38c4e]  no proxy cert policy language defined
│ │ +  [ 38c74]  X509_check_private_key
│ │ +  [ 38c8b]  /usr/local/ssl/cert.pem
│ │ +  [ 38ca3]  unknown trust id
│ │ +  [ 38cb4]  CRL is not yet valid
│ │ +  [ 38cc9]  issuer certificate lookup error
│ │ +  [ 38ce9]  Certificate public key has explicit ECC parameters
│ │ +  [ 38d1c]  build_chain
│ │ +  [ 38d28]  crypto/x509/pcy_data.c
│ │ +  [ 38d3f]  X509_VERIFY_PARAM_set1
│ │ +  [ 38d56]  X509_PUBKEY_set
│ │ +  [ 38d66]  afalg
│ │ +  [ 38d6c]  cbc(aes)
│ │ +  [ 38d75]  code 
│ │ +  [ 38d7b]  provider=base,fips=yes,output=der,structure=SubjectPublicKeyInfo
│ │ +  [ 38dbc]  provider=base,fips=yes,output=pem,structure=pkcs3
│ │ +  [ 38dee]  SCRYPT:id-scrypt:1.3.6.1.4.1.11591.4.11
│ │ +  [ 38e16]  OpenSSL X9.42 DH implementation
│ │ +  [ 38e36]  ED448ph
│ │ +  [ 38e3e]  ECDSA-SHA2-256:ECDSA-SHA256:ecdsa-with-SHA256:1.2.840.10045.4.3.2
│ │ +  [ 38e80]  provider=default,fips=yes,input=der,structure=PrivateKeyInfo
│ │ +  [ 38ebd]  provider=default,fips=yes,input=der,structure=SubjectPublicKeyInfo
│ │ +  [ 38f00]  AES-256-GCM-SIV
│ │ +  [ 38f10]  C2
│ │ +  [ 38f13]  aes_cbc_cts_get_ctx_params
│ │ +  [ 38f2e]  providers/implementations/ciphers/cipher_aes_hw.c
│ │ +  [ 38f60]  sm4_xts_stream_update
│ │ +  [ 38f76]  GB
│ │ +  [ 38f79]  providers/implementations/digests/blake2_prov.c
│ │ +  [ 38fa9]  rsa_to_type_specific_keypair_pem_encode
│ │ +  [ 38fd1]  dhx_to_type_specific_params_pem_encode
│ │ +  [ 38ff8]  p8info_to_encp8
│ │ +  [ 39008]  dhx_to_EncryptedPrivateKeyInfo_pem_encode
│ │ +  [ 39032]  sm2_to_PrivateKeyInfo_der_encode
│ │ +  [ 39053]  sm2_to_SubjectPublicKeyInfo_der_encode
│ │ +  [ 3907a]  :\n
│ │              %s
│ │ -  [ 39058]  dsa2text_encode
│ │ -  [ 39068]  ec2text_encode
│ │ -  [ 39077]  PSS parameter restrictions:\n
│ │ -  [ 39094]  m_cost must be greater or equal than 8 times the number of lanes
│ │ -  [ 390d5]  kdf_hkdf_derive
│ │ -  [ 390e5]  kdf_sshkdf_set_ctx_params
│ │ -  [ 390ff]  use-keybits
│ │ -  [ 3910b]  blake2_mac_set_ctx_params
│ │ -  [ 39125]  providers/implementations/rands/drbg_ctr.c
│ │ -  [ 39150]  /dev/srandom
│ │ -  [ 3915d]  nonce-type
│ │ -  [ 39168]  digest-size
│ │ -  [ 39174]  ed25519_sign
│ │ -  [ 39181]  ed448_digest_signverify_init
│ │ -  [ 3919e]  input-type
│ │ -  [ 391a9]  failed to decrypt
│ │ -  [ 391bb]  fips module conditional error
│ │ -  [ 391d9]  providers/implementations/ciphers/ciphercommon_gcm.c
│ │ -  [ 3920e]  en
│ │ -  [ 39211]  el
│ │ -  [ 39214]  ider-name
│ │ -  [ 3921e]  sion_id
│ │ -  [ 39226]  ssl/record/methods/tls_pad.c
│ │ -  [ 39243]  s28
│ │ -  [ 39247]  TLS_DHE_DSS_WITH_AES_128_CBC_SHA256
│ │ -  [ 3926b]  DHE-RSA-AES128-CCM8
│ │ -  [ 3927f]  ECDHE-RSA-AES256-GCM-SHA384
│ │ -  [ 3929b]  DHE-PSK-NULL-SHA
│ │ -  [ 392ac]  DHE-PSK-AES256-CBC-SHA
│ │ -  [ 392c3]  TLS_RSA_PSK_WITH_NULL_SHA384
│ │ -  [ 392e0]  SUITEB192
│ │ -  [ 392ea]  aECDSA
│ │ -  [ 392f1]  CAMELLIA128
│ │ -  [ 392fd]  ssl_cipher_process_rulestr
│ │ -  [ 39318]  decryption failed or bad record mac
│ │ -  [ 3933c]  duplicate compression id
│ │ -  [ 39355]  got a fin before a ccs
│ │ -  [ 3936c]  missing ecdsa signing cert
│ │ -  [ 39387]  no ciphers available
│ │ -  [ 3939c]  peer did not return a certificate
│ │ -  [ 393be]  renegotiation encoding err
│ │ -  [ 393d9]  renegotiation mismatch
│ │ -  [ 393f0]  tlsv1 bad certificate hash value
│ │ -  [ 39411]  SSL_do_handshake
│ │ -  [ 39422]  decrypt-only
│ │ -  [ 3942f]  dhparam
│ │ -  [ 39437]  TLSv1.1
│ │ -  [ 3943f]  ssl/ssl_sess.c
│ │ -  [ 3944e]  tls-sigalg-sig-oid
│ │ -  [ 39461]  properties
│ │ -  [ 3946c]  SERVER_HANDSHAKE_TRAFFIC_SECRET
│ │ -  [ 3948c]  retiring connection id limit violated
│ │ -  [ 394b3]  ch_on_handshake_alert
│ │ -  [ 394c9]  new packet with old keys
│ │ -  [ 394e2]  local
│ │ -  [ 394e8]  cur_cwnd_size
│ │ -  [ 394f6]  qlog_format
│ │ -  [ 39502]  group_id
│ │ -  [ 3950b]  invalid_token
│ │ -  [ 39519]  handshake
│ │ -  [ 39523]  PATH_RESPONSE
│ │ -  [ 39531]  ssl/quic/uint_set.c
│ │ -  [ 39545]  tls_default_read_n
│ │ -  [ 39558]  final_supported_versions
│ │ -  [ 39571]  ssl/statem/extensions_clnt.c
│ │ -  [ 3958e]  ssl3_output_cert_chain
│ │ -  [ 395a5]  crypto/asn1/d2i_pr.c
│ │ -  [ 395ba]  Field=
│ │ -  [ 395c1]  crypto/asn1/tasn_new.c
│ │ -  [ 395d8]  ASN1_IA5STRING
│ │ -  [ 395e7]  DISPLAYTEXT
│ │ -  [ 395f3]  algorithm
│ │ -  [ 395fd]  ZUINT32
│ │ -  [ 39605]  nbio connect error
│ │ -  [ 39618]  port mismatch
│ │ -  [ 39626]  unable to tfo
│ │ -  [ 39634]  BIO_puts
│ │ -  [ 3963d]  BIO_gets
│ │ -  [ 39646]  bio_read_intern
│ │ -  [ 39656]  crypto/bn/bn_add.c
│ │ -  [ 39669]  crypto/bn/bn_conv.c
│ │ -  [ 3967d]  crypto/bn/bn_lib.c
│ │ -  [ 39690]  BUF_MEM_grow_clean
│ │ -  [ 396a3]  Unprocessed type %d\n
│ │ -  [ 396b8]  crypto/asn1/p5_pbev2.c
│ │ -  [ 396cf]  calling stat(%s)
│ │ -  [ 396e0]  o2i_SCT_LIST
│ │ -  [ 396ed]  priv_len
│ │ -  [ 396f6]  %02x%s
│ │ -  [ 396fd]  %s %s%lu (%s0x%lx)\n
│ │ -  [ 39711]  DH_check_pub_key
│ │ -  [ 39722]  eckey_pub_encode
│ │ -  [ 39733]  order
│ │ -  [ 39739]  crypto/ec/ec_curve.c
│ │ -  [ 3974e]  SECG curve over a 163 bit binary field
│ │ -  [ 39775]  crypto/ec/ec2_smpl.c
│ │ -  [ 3978a]  crypto/bn/bn_gf2m.c
│ │ -  [ 3979e]  ossl_ecdsa_simple_sign_sig
│ │ -  [ 397b9]  ossl_ec_GFp_mont_field_encode
│ │ -  [ 397d7]  ossl_decoder_cache_flush
│ │ -  [ 397f0]  err:%lx:%lx:%lx:%lx
│ │ -  [ 39804]  CRMF routines
│ │ -  [ 39812]  EVP_PKEY_decrypt
│ │ -  [ 39823]  aes_init_key
│ │ -  [ 39830]  sect283k1
│ │ -  [ 3983a]  wap-wsg-idm-ecid-wtls9
│ │ -  [ 39851]  alg_section
│ │ -  [ 3985d]  No encoders were found. For standard encoders you need at least one of the default or base providers available. Did you forget to load them?
│ │ -  [ 398ea]  evp_kem_init
│ │ -  [ 398f7]  EVP_DigestVerifyUpdate
│ │ -  [ 3990e]  PBEPARAM
│ │ -  [ 39917]  evp_pkey_get0_DSA_int
│ │ -  [ 3992d]  rsa_pss_keygen_md
│ │ -  [ 3993f]  maxmem_bytes
│ │ -  [ 3994c]  fix_dh_paramgen_type
│ │ -  [ 39961]  fix_dh_nid5114
│ │ -  [ 39970]  EXPAND_ONLY
│ │ -  [ 3997c]  rsa-factor2
│ │ -  [ 39988]  pkey_ec_keygen
│ │ -  [ 39997]  pkey_ec_ctrl
│ │ -  [ 399a4]  modp_1536
│ │ -  [ 399ae]  Global default library context
│ │ -  [ 399cd]  3.4.0
│ │ -  [ 399d3]  not available
│ │ -  [ 399e1]  bad decrypt
│ │ -  [ 399ed]  setting xof failed
│ │ -  [ 39a00]  data is wrong
│ │ -  [ 39a0e]  illegal boolean
│ │ -  [ 39a1e]  integer too large for long
│ │ -  [ 39a39]  mime sig parse error
│ │ -  [ 39a4e]  missing eoc
│ │ -  [ 39a5a]  nested asn1 string
│ │ -  [ 39a6d]  curve does not support ecdh
│ │ -  [ 39a89]  incorrect file syntax
│ │ -  [ 39a9f]  received error
│ │ -  [ 39aae]  need one signer
│ │ -  [ 39abe]  no matching recipient
│ │ -  [ 39ad4]  unsupported kek algorithm
│ │ -  [ 39aee]  error
│ │ -  [ 39af4]  popo missing subject
│ │ -  [ 39b09]  setting mac algor failure
│ │ -  [ 39b23]  checkafter out of range
│ │ -  [ 39b3b]  encountered waiting
│ │ -  [ 39b4f]  error validating protection
│ │ -  [ 39b6b]  error creating crlstatus
│ │ -  [ 39b84]  ess cert digest error
│ │ -  [ 39b9a]  DES-EDE3-CBC
│ │ -  [ 39ba7]  openssl
│ │ -  [ 39baf]  EVP_PKEY_base_id
│ │ -  [ 39bc0]  assertion failed: sh_testbit(chunk, list, sh.bittable)
│ │ -  [ 39bf7]  push_BN
│ │ -  [ 39bff]  crypto/params.c
│ │ -  [ 39c0f]  get_ptr_internal
│ │ -  [ 39c20]  L
│ │ -  [ 39c22]  des-ecb
│ │ -  [ 39c2a]  Netscape Data Type
│ │ -  [ 39c3d]  sha1WithRSAEncryption
│ │ -  [ 39c53]  Netscape CA Revocation Url
│ │ -  [ 39c6e]  id-ce
│ │ -  [ 39c74]  MDC2
│ │ -  [ 39c79]  X509v3 Extended Key Usage
│ │ -  [ 39c93]  hmacWithSHA1
│ │ -  [ 39ca0]  id-smime-alg
│ │ -  [ 39cad]  id-smime-spq
│ │ -  [ 39cba]  id-smime-ct-DVCSRequestData
│ │ -  [ 39cd6]  id-smime-aa-contentIdentifier
│ │ -  [ 39cf4]  id-smime-spq-ets-sqt-unotice
│ │ -  [ 39d11]  id-pkix1-implicit-88
│ │ -  [ 39d26]  id-cmc-responseInfo
│ │ -  [ 39d3a]  Nonce
│ │ -  [ 39d40]  X500algorithms
│ │ -  [ 39d4f]  ORG
│ │ -  [ 39d53]  Domain
│ │ -  [ 39d5a]  Selected Attribute Types
│ │ -  [ 39d73]  Subject Information Access
│ │ -  [ 39d8e]  ansi-X9-62
│ │ -  [ 39d99]  aes-192-cfb
│ │ -  [ 39da5]  account
│ │ -  [ 39dad]  subtreeMinimumQuality
│ │ -  [ 39dc3]  setct-CapRevResTBE
│ │ -  [ 39dd6]  setct-CRLNotificationTBS
│ │ -  [ 39def]  setAttr-TokICCsig
│ │ -  [ 39e01]  DES-CDMF
│ │ -  [ 39e0a]  street
│ │ -  [ 39e11]  certicom-arc
│ │ -  [ 39e1e]  id-GostR3411-94-with-GostR3410-94
│ │ -  [ 39e40]  id-Gost28147-89-TestParamSet
│ │ -  [ 39e5d]  id-GostR3410-2001-TestParamSet
│ │ -  [ 39e7c]  id-GostR3410-2001-CryptoPro-XchB-ParamSet
│ │ -  [ 39ea6]  id-aes128-CCM
│ │ -  [ 39eb4]  aes-256-gcm
│ │ -  [ 39ec0]  AES-256-OCB
│ │ -  [ 39ecc]  HMAC GOST 34.11-2012 256 bit
│ │ -  [ 39ee9]  id-tc26-gost-3410-2012-512-paramSetB
│ │ -  [ 39f0e]  GOST R 34.10-2012 (512 bit) ParamSet B
│ │ -  [ 39f35]  subjectSignTool
│ │ -  [ 39f45]  KxGOST
│ │ -  [ 39f4c]  Professional Information or basis for Admission
│ │ -  [ 39f7c]  shake128
│ │ -  [ 39f85]  RSA-SM3
│ │ -  [ 39f8d]  GOST R 34.10-2012 (256 bit) ParamSet D
│ │ -  [ 39fb4]  SRVName
│ │ -  [ 39fbc]  id-ct-ASPA
│ │ -  [ 39fc7]  id-aa-ets-longTermValidation
│ │ -  [ 39fe4]  issuedOnBehalfOf
│ │ -  [ 39ff5]  crypto/asn1/a_verify.c
│ │ -  [ 3a00c]  crypto/pem/pem_lib.c
│ │ -  [ 3a021]  DEK-Info: %s,
│ │ -  [ 3a02f]  pem_read_bio_key_decoder
│ │ -  [ 3a048]  unsupported pkcs12 mode
│ │ -  [ 3a060]  d.signed_and_enveloped
│ │ -  [ 3a077]  operation not supported on this type
│ │ -  [ 3a09c]  wrong content type
│ │ -  [ 3a0af]  EVP_RAND_CTX_new
│ │ -  [ 3a0c0]  crypto/rand/rand_pool.c
│ │ -  [ 3a0d8]  ossl_rsa_pss_to_ctx
│ │ -  [ 3a0ec]  rsa_priv_encode
│ │ -  [ 3a0fc]  illegal or unsupported padding mode
│ │ -  [ 3a120]  invalid multi prime key
│ │ -  [ 3a138]  rsa_multiprime_keygen
│ │ -  [ 3a14e]  pkey_rsa_sign
│ │ -  [ 3a15c]  encode_pkcs1
│ │ -  [ 3a169]  OSSL_STORE_INFO_new_CRL
│ │ -  [ 3a181]  writing strings
│ │ -  [ 3a191]  PEM password callback wrapper
│ │ -  [ 3a1af]  qualifiers
│ │ -  [ 3a1ba]  notice_section
│ │ -  [ 3a1c9]  digitalSignature
│ │ -  [ 3a1da]  Privilege Withdrawn
│ │ -  [ 3a1ee]  AA Compromise
│ │ -  [ 3a1fc]  gnames_from_sectname
│ │ -  [ 3a211]  crypto/ocsp/v3_ocsp.c
│ │ -  [ 3a227]  Autonomous System Numbers
│ │ -  [ 3a241]  OSSL_ISSUER_SERIAL
│ │ -  [ 3a254]  otherObjectTypeID
│ │ -  [ 3a267]  %*sSignature Value: 
│ │ -  [ 3a27c]  signToolCert
│ │ -  [ 3a289]  ADMISSION_SYNTAX
│ │ -  [ 3a29a]  authority
│ │ -  [ 3a2a4]  ocsphelper
│ │ -  [ 3a2af]  RID
│ │ -  [ 3a2b3]  dirName
│ │ -  [ 3a2bb]  s2i_ASN1_UTF8STRING
│ │ -  [ 3a2cf]  error converting zone
│ │ -  [ 3a2e5]  invalid numbers
│ │ -  [ 3a2f5]  policy path length already defined
│ │ -  [ 3a318]  policy when proxy language requires no policy
│ │ -  [ 3a346]  crl verify failure
│ │ -  [ 3a359]  unknown certificate verification error
│ │ -  [ 3a380]  ossl_policy_level_add_node
│ │ -  [ 3a39b]  revoked
│ │ -  [ 3a3a3]  critical
│ │ -  [ 3a3ac]  cert_info
│ │ -  [ 3a3b6]  provider=base,fips=yes,output=pem,structure=dhx
│ │ -  [ 3a3e6]  SHA2-512:SHA-512:SHA512:2.16.840.1.101.3.4.2.3
│ │ -  [ 3a415]  SHA3-224:2.16.840.1.101.3.4.2.7
│ │ -  [ 3a435]  KECCAK-224
│ │ -  [ 3a440]  RSA-RIPEMD160:ripemd160WithRSA:1.3.36.3.3.1.2
│ │ -  [ 3a46e]  ECDSA-SHA2-224:ECDSA-SHA224:ecdsa-with-SHA224:1.2.840.10045.4.3.1
│ │ -  [ 3a4b0]  ECDSA-SHA3-512:ecdsa_with_SHA3-512:id-ecdsa-with-sha3-512:2.16.840.1.101.3.4.3.12
│ │ -  [ 3a502]  provider=default,fips=yes,output=text
│ │ -  [ 3a528]  provider=default,fips=yes,output=der,structure=X9.42
│ │ -  [ 3a55d]  AES-192-OFB:2.16.840.1.101.3.4.1.23
│ │ -  [ 3a581]  AES-192-WRAP-INV:AES192-WRAP-INV
│ │ -  [ 3a5a2]  null_get_ctx_params
│ │ -  [ 3a5b6]  sm4_xts_set_ctx_params
│ │ -  [ 3a5cd]  epki2pki_decode
│ │ -  [ 3a5dd]  providers/implementations/encode_decode/encode_key2any.c
│ │ -  [ 3a616]  RSA-PSS PRIVATE KEY
│ │ -  [ 3a62a]  rsapss_to_PrivateKeyInfo_pem_encode
│ │ -  [ 3a64e]  prepare_dh_params
│ │ -  [ 3a660]  sm2_to_EncryptedPrivateKeyInfo_pem_encode
│ │ -  [ 3a68a]  ED448 PRIVATE KEY
│ │ -  [ 3a69c]  x25519_to_EncryptedPrivateKeyInfo_pem_encode
│ │ -  [ 3a6c9]  x448_to_PrivateKeyInfo_der_encode
│ │ -  [ 3a6eb]  x448_to_PrivateKeyInfo_pem_encode
│ │ -  [ 3a70d]  ec2blob_encode
│ │ -  [ 3a71c]  P:   
│ │ -  [ 3a722]  ecx_set_peer
│ │ -  [ 3a72f]  cannot allocate required memory
│ │ -  [ 3a74f]  providers/implementations/kdfs/hmacdrbg_kdf.c
│ │ -  [ 3a77d]  partyv-info
│ │ -  [ 3a789]  supp-privinfo
│ │ -  [ 3a797]  ec_gen_set_group
│ │ -  [ 3a7a8]  common_get_params
│ │ -  [ 3a7ba]  cmac_set_ctx_params
│ │ -  [ 3a7ce]  providers/implementations/macs/kmac_prov.c
│ │ -  [ 3a7f9]  kmac_set_ctx_params
│ │ -  [ 3a80d]  ossl_drbg_enable_locking
│ │ -  [ 3a826]  strength
│ │ -  [ 3a82f]  is %zu, should be at least %zu
│ │ -  [ 3a84e]  rsa_pss_compute_saltlen
│ │ -  [ 3a866]  ems not enabled
│ │ -  [ 3a876]  failed to generate key
│ │ -  [ 3a88d]  invalid constant length
│ │ -  [ 3a8a5]  invalid eddsa instance for attempted operation
│ │ -  [ 3a8d4]  not xof or invalid length
│ │ -  [ 3a8ee]  gcm_tls_cipher
│ │ -  [ 3a8fd]  tant
│ │ -  [ 3a902]  kem-ikm
│ │ -  [ 3a90a]  evel
│ │ -  [ 3a90f]  erslen
│ │ -  [ 3a916]  uffer_len
│ │ -  [ 3a920]  binfo
│ │ -  [ 3a926]  egotiated-version
│ │ -  [ 3a938]  s3
│ │ -  [ 3a93b]  s8
│ │ -  [ 3a93e]  d18
│ │ -  [ 3a942]  d21
│ │ -  [ 3a946]  d24
│ │ -  [ 3a94a]  _Unwind_GetDataRelBase
│ │ -  [ 3a961]  client finished
│ │ -  [ 3a971]  AES256-SHA
│ │ -  [ 3a97c]  TLS_PSK_DHE_WITH_AES_128_CCM_8
│ │ -  [ 3a99b]  ECDHE-ECDSA-AES128-CCM
│ │ -  [ 3a9b2]  TLS_PSK_WITH_AES_256_CBC_SHA
│ │ -  [ 3a9cf]  TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256
│ │ -  [ 3a9f5]  ADH-CAMELLIA128-SHA256
│ │ -  [ 3aa0c]  TLS_DHE_DSS_WITH_CAMELLIA_128_CBC_SHA
│ │ -  [ 3aa32]  TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
│ │ -  [ 3aa58]  PSK-ARIA128-GCM-SHA256
│ │ -  [ 3aa6f]  GOST12
│ │ -  [ 3aa76]  SHA384
│ │ -  [ 3aa7d]  AES256
│ │ -  [ 3aa84]  bn lib
│ │ -  [ 3aa8b]  digest check failed
│ │ -  [ 3aa9f]  exceeds max fragment size
│ │ -  [ 3aab9]  failed to get parameter
│ │ -  [ 3aad1]  invalid compression algorithm
│ │ -  [ 3aaef]  no suitable digest algorithm
│ │ -  [ 3ab0c]  no suitable key share
│ │ -  [ 3ab22]  error with the srp params
│ │ -  [ 3ab3c]  ssl/tls alert bad record mac
│ │ -  [ 3ab59]  ssl command section not found
│ │ -  [ 3ab77]  tlsv1 alert unknown psk identity
│ │ -  [ 3ab98]  too many key updates
│ │ -  [ 3abad]  unexpected eof while reading
│ │ -  [ 3abca]  unsupported config value class
│ │ -  [ 3abe9]  unsupported elliptic curve
│ │ -  [ 3ac04]  x509 verification setup problems
│ │ -  [ 3ac25]  SSL_clear
│ │ -  [ 3ac2f]  client_sigalgs
│ │ -  [ 3ac3e]  CANames
│ │ -  [ 3ac46]  tls-sigalg-hash-name
│ │ -  [ 3ac5b]  ecdsa_secp384r1_sha384
│ │ -  [ 3ac72]  ecdsa_sha1
│ │ -  [ 3ac7d]  network BIO I/O error
│ │ -  [ 3ac93]  )
│ │ -  [ 3ac95]  ch_on_handshake_yield_secret
│ │ -  [ 3acb2]  PREFERRED_ADDR may not be sent by a client
│ │ -  [ 3acdd]  type
│ │ -  [ 3ace2]  connection_id_limit_error
│ │ -  [ 3acfc]  1RTT
│ │ -  [ 3ad01]  scid
│ │ -  [ 3ad06]  explicit_length
│ │ -  [ 3ad16]  ossl_qrl_enc_level_set_key_cooldown_done
│ │ -  [ 3ad3f]  tls_construct_ctos_ec_pt_formats
│ │ -  [ 3ad60]  tls_construct_ctos_ems
│ │ -  [ 3ad77]  tls_parse_stoc_cookie
│ │ -  [ 3ad8d]  tls_parse_stoc_early_data
│ │ -  [ 3ada7]  tls_construct_finished
│ │ -  [ 3adbe]  tls_process_cke_srp
│ │ -  [ 3add2]   + 
│ │ -  [ 3add6]  minsize=%ld
│ │ -  [ 3ade2]  BIT STRING
│ │ -  [ 3aded]  GRAPHICSTRING
│ │ -  [ 3adfb]  ASN1_item_unpack_ex
│ │ -  [ 3ae0f]  %*s%04x - 
│ │ -  [ 3ae1a]  crypto/bio/bio_print.c
│ │ -  [ 3ae31]  crypto/bn/bn_div.c
│ │ -  [ 3ae44]  %*s%s OF %s {\n
│ │ -  [ 3ae53]  dollarid
│ │ -  [ 3ae5c]  openssl.cnf
│ │ -  [ 3ae68]  path
│ │ -  [ 3ae6d]  crypto/ct/ct_sct_ctx.c
│ │ -  [ 3ae84]  dh_priv_encode
│ │ -  [ 3ae93]  dh_pkey_import_from_type
│ │ -  [ 3aeac]  dsa_priv_encode
│ │ -  [ 3aebc]  dsa_pkey_import_from
│ │ -  [ 3aed1]  dsa_sign_setup
│ │ -  [ 3aee0]  %s.so
│ │ -  [ 3aee6]  EC_GROUP_get_ecpkparameters
│ │ -  [ 3af02]  crypto/ec/ec_check.c
│ │ -  [ 3af17]  X9.62 curve over a 359 bit binary field
│ │ -  [ 3af3f]  ossl_ec_wNAF_mul
│ │ -  [ 3af50]  crypto/ec/ec_oct.c
│ │ -  [ 3af63]  Generator (uncompressed):
│ │ -  [ 3af7d]  ossl_ec_GFp_simple_point_get_affine_coordinates
│ │ -  [ 3afad]  ossl_ecx_public_from_private
│ │ -  [ 3afca]  OSSL_DECODER_CTX_set_cleanup
│ │ -  [ 3afe7]  PKEY
│ │ -  [ 3afec]  Provider routines
│ │ -  [ 3affe]  PEM lib
│ │ -  [ 3b006]  passed invalid argument
│ │ -  [ 3b01e]  sect409k1
│ │ -  [ 3b028]  wap-wsg-idm-ecid-wtls4
│ │ -  [ 3b03f]  wap-wsg-idm-ecid-wtls8
│ │ -  [ 3b056]  wap-wsg-idm-ecid-wtls10
│ │ -  [ 3b06e]  brainpoolP256r1
│ │ -  [ 3b07e]  brainpoolP320t1
│ │ -  [ 3b08e]  P-521
│ │ -  [ 3b094]  default_properties
│ │ -  [ 3b0a7]  EVP_EncryptFinal_ex
│ │ -  [ 3b0bb]  EVP_CIPHER_CTX_set_key_length
│ │ -  [ 3b0d9]  assertion failed: niv >= 0 && niv <= EVP_MAX_IV_LENGTH
│ │ -  [ 3b110]  tls-multi
│ │ -  [ 3b11a]  TYPE=%s
│ │ -  [ 3b122]  crypto/asn1/p5_scrypt.c
│ │ -  [ 3b13a]  OSSL_ENCODER_get0_provider
│ │ -  [ 3b155]  OSSL_ENCODER_CTX_set_selection
│ │ -  [ 3b174]  EVP_PKEY_derive_set_peer_ex
│ │ -  [ 3b190]  EVP_PKEY_get_security_bits
│ │ -  [ 3b1ab]  evp_pkey_get0_ECX_KEY
│ │ -  [ 3b1c1]  [action:%d, state:%d] unknown OSSL_PARAM data type %d
│ │ -  [ 3b1f7]  [action:%d, state:%d] unsupported OSSL_PARAM data type %d
│ │ -  [ 3b231]  dh_paramgen_subprime_len
│ │ -  [ 3b24a]  EVP_SignFinal_ex
│ │ -  [ 3b25b]  potential
│ │ -  [ 3b265]  EVP_PKEY_CTX_get_signature_md
│ │ -  [ 3b283]  evp_pkey_signature_init
│ │ -  [ 3b29b]  platform: linux-armv4
│ │ -  [ 3b2b1]  input not reduced
│ │ -  [ 3b2c3]  invalid secret
│ │ -  [ 3b2d2]  kdf parameter error
│ │ -  [ 3b2e6]  bad key length
│ │ -  [ 3b2f5]  error setting cipher params
│ │ -  [ 3b311]  illegal null value
│ │ -  [ 3b324]  invalid number
│ │ -  [ 3b333]  missing second number
│ │ -  [ 3b349]  mstring not universal
│ │ -  [ 3b35f]  wrong integer type
│ │ -  [ 3b372]  no section
│ │ -  [ 3b37d]  invalid ossl param type
│ │ -  [ 3b395]  provider already exists
│ │ -  [ 3b3ad]  command takes input
│ │ -  [ 3b3c1]  operation unsupported
│ │ -  [ 3b3d7]  recipient error
│ │ -  [ 3b3e7]  bad pbm iterationcount
│ │ -  [ 3b3fe]  invalid keyspec
│ │ -  [ 3b40e]  DES3
│ │ -  [ 3b413]  aria128
│ │ -  [ 3b41b]  rc2_magic_to_meth
│ │ -  [ 3b42d]  ossl_pw_set_ui_method
│ │ -  [ 3b443]  OBJ_nid2obj
│ │ -  [ 3b44f]  idea-cfb
│ │ -  [ 3b458]  des-ede-ofb
│ │ -  [ 3b464]  nsSslServerName
│ │ -  [ 3b474]  Netscape SSL Server Name
│ │ -  [ 3b48d]  serverAuth
│ │ -  [ 3b498]  msCodeCom
│ │ -  [ 3b4a2]  x509Certificate
│ │ -  [ 3b4b2]  Policy Qualifier CPS
│ │ -  [ 3b4c7]  pbeWithMD2AndRC2-CBC
│ │ -  [ 3b4dc]  OCSP
│ │ -  [ 3b4e1]  member-body
│ │ -  [ 3b4ed]  SMIME
│ │ -  [ 3b4f3]  id-smime-mod-ets-eSignature-88
│ │ -  [ 3b512]  id-cmc
│ │ -  [ 3b519]  id-pkix1-explicit-88
│ │ -  [ 3b52e]  id-regCtrl-protocolEncrKey
│ │ -  [ 3b549]  id-cmc-lraPOPWitness
│ │ -  [ 3b55e]  ad_timestamping
│ │ -  [ 3b56e]  iana
│ │ -  [ 3b573]  Directory
│ │ -  [ 3b57d]  Mail
│ │ -  [ 3b582]  RSA-MD4
│ │ -  [ 3b58a]  ac-proxying
│ │ -  [ 3b596]  holdInstructionCode
│ │ -  [ 3b5aa]  mXRecord
│ │ -  [ 3b5b3]  set-ctype
│ │ -  [ 3b5bd]  setct-CredRevResData
│ │ -  [ 3b5d2]  setCext-hashedRoot
│ │ -  [ 3b5e5]  setAttr-IssCap-CVM
│ │ -  [ 3b5f8]  set-brand-Visa
│ │ -  [ 3b607]  des-cfb8
│ │ -  [ 3b610]  sha256WithRSAEncryption
│ │ -  [ 3b628]  dsa_with_SHA256
│ │ -  [ 3b638]  whirlpool
│ │ -  [ 3b642]  id-GostR3410-2001-CryptoPro-C-ParamSet
│ │ -  [ 3b669]  GOST R 34.11-94 with GOST R 34.10-94 Cryptocom
│ │ -  [ 3b698]  GOST R 34.11-94 with GOST R 34.10-2001 Cryptocom
│ │ -  [ 3b6c9]  Microsoft Local Key set
│ │ -  [ 3b6e1]  physicalDeliveryOfficeName
│ │ -  [ 3b6fc]  id-camellia256-wrap
│ │ -  [ 3b710]  Any Extended Key Usage
│ │ -  [ 3b727]  CAMELLIA-128-CMAC
│ │ -  [ 3b739]  Send Owner
│ │ -  [ 3b744]  KxRSA_PSK
│ │ -  [ 3b74e]  aria-192-cfb8
│ │ -  [ 3b75c]  id-dsa-with-sha512
│ │ -  [ 3b76f]  ARIA-128-GCM
│ │ -  [ 3b77c]  CMC Registration Authority
│ │ -  [ 3b797]  sm4-ctr
│ │ -  [ 3b79f]  ISO-CN
│ │ -  [ 3b7a6]  RSA-SHA512/224
│ │ -  [ 3b7b5]  id-tc26-gost-3410-2012-256-paramSetC
│ │ -  [ 3b7da]  BLAKE2SMAC
│ │ -  [ 3b7e5]  X942KDF
│ │ -  [ 3b7ed]  id-on-SmtpUTF8Mailbox
│ │ -  [ 3b803]  Class of Signing Tool KA1
│ │ -  [ 3b81d]  RPKI Manifest
│ │ -  [ 3b82b]  X509v3 Basic Attribute Certificate Constraints
│ │ -  [ 3b85a]  acceptablePrivPolicies
│ │ -  [ 3b871]  unknown object name
│ │ -  [ 3b885]  expecting private key blob
│ │ -  [ 3b8a0]  PKCS12_SAFEBAGS
│ │ -  [ 3b8b0]  dinfo
│ │ -  [ 3b8b6]  PKCS12KDF
│ │ -  [ 3b8c0]  PKCS8_encrypt_ex
│ │ -  [ 3b8d1]  invalid null pkcs12 pointer
│ │ -  [ 3b8ed]  signing ctrl failure
│ │ -  [ 3b902]  signing not supported for this key type
│ │ -  [ 3b92a]  fips
│ │ -  [ 3b92f]  Mask Algorithm: 
│ │ -  [ 3b940]  %s Salt Length: 0x
│ │ -  [ 3b953]  RSA factors/exponents are too big for for n-modulus\n
│ │ -  [ 3b988]  rsa_new_intern
│ │ -  [ 3b997]  ossl_rsa_padding_add_PKCS1_OAEP_mgf1_ex
│ │ -  [ 3b9bf]  RSA_padding_check_PKCS1_type_1
│ │ -  [ 3b9de]  %s:
│ │ -  [ 3b9e2]  crypto/ui/ui_util.c
│ │ -  [ 3b9f6]  crypto/asn1/x_pkey.c
│ │ -  [ 3ba0b]  crypto/x509/v3_conf.c
│ │ -  [ 3ba21]  d.rfc822Name
│ │ -  [ 3ba2e]  d.uniformResourceIdentifier
│ │ -  [ 3ba4a]  s2i_ASN1_IA5STRING
│ │ -  [ 3ba5d]  DIST_POINT
│ │ -  [ 3ba68]  ADMISSIONS
│ │ -  [ 3ba73]  registrationNumber
│ │ -  [ 3ba86]  crypto/x509/v3_ind_iss.c
│ │ -  [ 3ba9f]  sslserver
│ │ -  [ 3baa9]  v2i_subject_alt
│ │ -  [ 3baba]  %*sZone: %s, User: 
│ │ -  [ 3bace]  duplicate attribute
│ │ -  [ 3bae2]  public key decode error
│ │ -  [ 3bafa]  Object Signer
│ │ -  [ 3bb08]  certificate signature failure
│ │ -  [ 3bb26]  subject issuer mismatch
│ │ -  [ 3bb3e]  Empty Subject Alternative Name extension
│ │ -  [ 3bb67]  X509_self_signed
│ │ -  [ 3bb78]  X509_STORE_CTX_set_default
│ │ -  [ 3bb93]  crypto/x509/pcy_cache.c
│ │ -  [ 3bbab]  socket accept failed
│ │ -  [ 3bbc0]  ALG_PERR: %s(%d): io_getevents failed : 
│ │ -  [ 3bbe9]  provider=base,fips=yes,output=pem,structure=type-specific
│ │ -  [ 3bc23]  provider=base,fips=yes,output=der,structure=dsa
│ │ -  [ 3bc53]  provider=base,fips=yes,output=der,structure=pkcs1
│ │ -  [ 3bc85]  provider=base,fips=no,input=der,structure=PrivateKeyInfo
│ │ -  [ 3bcbe]  OpenSSL Default Provider
│ │ -  [ 3bcd7]  OpenSSL X448 implementation
│ │ -  [ 3bcf3]  RSA-SHA2-384:RSA-SHA384:sha384WithRSAEncryption:1.2.840.113549.1.1.12
│ │ -  [ 3bd39]  provider=default,fips=yes,output=blob
│ │ -  [ 3bd5f]  AES-192-ECB:2.16.840.1.101.3.4.1.21
│ │ -  [ 3bd83]  providers/implementations/ciphers/cipher_aes_cts.inc
│ │ -  [ 3bdb8]  providers/implementations/ciphers/cipher_tdes_wrap.c
│ │ -  [ 3bded]  rsa_to_PrivateKeyInfo_der_encode
│ │ -  [ 3be0e]  dh_to_DH_pem_encode
│ │ -  [ 3be22]  providers/implementations/kdfs/hkdf.c
│ │ -  [ 3be48]  feedback
│ │ -  [ 3be51]  providers/implementations/kdfs/pkcs12kdf.c
│ │ -  [ 3be7c]  kdf_pkcs12_derive
│ │ -  [ 3be8e]  acvp-info
│ │ -  [ 3be98]  generate_ecdhkm
│ │ -  [ 3bea8]  eae_prk
│ │ -  [ 3beb0]  ossl_drbg_get_seed
│ │ -  [ 3bec3]  ossl_prov_drbg_instantiate
│ │ -  [ 3bede]  test_nonce
│ │ -  [ 3bee9]  input=PVK
│ │ -  [ 3bef3]  bad tls client version
│ │ -  [ 3bf0a]  fips module entering error state
│ │ -  [ 3bf2b]  ossl_cipher_trailingdata
│ │ -  [ 3bf44]  providers/implementations/ciphers/ciphercommon_ccm.c
│ │ -  [ 3bf79]  d-pub-key
│ │ -  [ 3bf83]  rly_data
│ │ -  [ 3bf8c]  gth
│ │ -  [ 3bf90]  fy-message
│ │ -  [ 3bf9b]  Type matching not implemented
│ │ -  [ 3bfb9]  s14
│ │ -  [ 3bfbd]  s15
│ │ -  [ 3bfc1]  d15
│ │ -  [ 3bfc5]  d28
│ │ -  [ 3bfc9]  ssl3_ctrl
│ │ -  [ 3bfd3]  TLS_RSA_WITH_AES_256_CBC_SHA
│ │ -  [ 3bff0]  TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
│ │ -  [ 3c014]  DHE-DSS-AES256-GCM-SHA384
│ │ -  [ 3c02e]  AECDH-AES256-SHA
│ │ -  [ 3c03f]  TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
│ │ -  [ 3c065]  PSK-NULL-SHA384
│ │ -  [ 3c075]  RSA-PSK-AES128-CBC-SHA256
│ │ -  [ 3c08f]  RSA-PSK-NULL-SHA384
│ │ -  [ 3c0a3]  TLS_ECDHE_PSK_WITH_NULL_SHA384
│ │ -  [ 3c0c2]  TLS_PSK_WITH_CHACHA20_POLY1305_SHA256
│ │ -  [ 3c0e8]  TLS_DHE_DSS_WITH_CAMELLIA_256_CBC_SHA256
│ │ -  [ 3c111]  tlsext_tick
│ │ -  [ 3c11d]  SHA1
│ │ -  [ 3c122]  aGOST12
│ │ -  [ 3c12a]  EDH
│ │ -  [ 3c12e]  SHA
│ │ -  [ 3c132]  bad cipher
│ │ -  [ 3c13d]  bad srtp mki value
│ │ -  [ 3c150]  ca key too small
│ │ -  [ 3c161]  invalid alert
│ │ -  [ 3c16f]  legacy sigalg disallowed or unsupported
│ │ -  [ 3c197]  missing fatal
│ │ -  [ 3c1a5]  ocsp callback failure
│ │ -  [ 3c1bb]  quic handshake layer error
│ │ -  [ 3c1d6]  quic protocol error
│ │ -  [ 3c1ea]  ssl3 ext invalid max fragment length
│ │ -  [ 3c20f]  ssl session id conflict
│ │ -  [ 3c227]  ssl_undefined_void_function
│ │ -  [ 3c243]  SSL_set_ct_validation_callback
│ │ -  [ 3c262]  add_provider_sigalgs
│ │ -  [ 3c277]  quic_read_again
│ │ -  [ 3c287]  unable to store stateless reset token
│ │ -  [ 3c2ad]  port_v6
│ │ -  [ 3c2b5]  crypto_error_0x%03llx
│ │ -  [ 3c2cb]  closed
│ │ -  [ 3c2d2]  retire_connection_id
│ │ -  [ 3c2e7]  stream_data_blocked
│ │ -  [ 3c2fb]  MAX_STREAMS valid only in 0/1-RTT
│ │ -  [ 3c31d]  depack_do_frame_max_streams
│ │ -  [ 3c339]  hdr_generate_mask
│ │ -  [ 3c34b]  ossl_set_tls_provider_parameters
│ │ -  [ 3c36c]  tls_get_more_records
│ │ -  [ 3c381]  tls13_add_record_padding
│ │ -  [ 3c39a]  PUT 
│ │ -  [ 3c39f]  CONNE
│ │ -  [ 3c3a5]  tls_psk_do_binder
│ │ -  [ 3c3b7]  tls_construct_ctos_server_cert_type
│ │ -  [ 3c3db]  tls_construct_stoc_maxfragmentlen
│ │ -  [ 3c3fd]  tls_client_key_exchange_post_work
│ │ -  [ 3c41f]  tls_post_process_server_rpk
│ │ -  [ 3c43b]  tls_construct_cke_srp
│ │ -  [ 3c451]  tls_construct_server_hello
│ │ -  [ 3c46c]  asn1_string_get_int64
│ │ -  [ 3c482]  crypto/asn1/asn1_lib.c
│ │ -  [ 3c499]  length is greater than %ld\n
│ │ -  [ 3c4b5]  ASN1_item_unpack
│ │ -  [ 3c4c6]  attributes
│ │ -  [ 3c4d1]  BIO_callback_ctrl
│ │ -  [ 3c4e3]  keylength
│ │ -  [ 3c4ed]  process_include
│ │ -  [ 3c4fd]  Char=%c
│ │ -  [ 3c505]  i2o_SCT
│ │ -  [ 3c50d]  dh_pkey_public_check
│ │ -  [ 3c522]  priv
│ │ -  [ 3c527]  dh_builtin_genparams
│ │ -  [ 3c53c]  DSO_free
│ │ -  [ 3c545]  crypto/dso/dso_dlfcn.c
│ │ -  [ 3c55c]  dlfcn_merger
│ │ -  [ 3c569]  i2o_ECPublicKey
│ │ -  [ 3c579]  p.onBasis
│ │ -  [ 3c583]  p.char_two
│ │ -  [ 3c58e]  X9.62 curve over a 272 bit binary field
│ │ -  [ 3c5b6]  ossl_ec_GF2m_simple_point_get_affine_coordinates
│ │ -  [ 3c5e7]  ossl_ec_group_new_ex
│ │ -  [ 3c5fc]  crypto/ec/ec2_oct.c
│ │ -  [ 3c610]  ossl_ec_GFp_mont_field_sqr
│ │ -  [ 3c62b]  validate_ecx_derive
│ │ -  [ 3c63f]  the mandatory 'input' property is missing for decoder %s (properties: %s)
│ │ -  [ 3c689]  crypto/encode_decode/decoder_pkey.c
│ │ -  [ 3c6ad]  ossl_decoder_ctx_for_pkey_dup
│ │ -  [ 3c6cb]  ENGINE_init
│ │ -  [ 3c6d7]  passed a null parameter
│ │ -  [ 3c6ef]  micalg
│ │ -  [ 3c6f6]  wap-wsg-idm-ecid-wtls3
│ │ -  [ 3c70d]  assertion failed: j <= sizeof(c->iv)
│ │ -  [ 3c732]  encoder_process
│ │ -  [ 3c742]  crypto/asn1/p5_pbe.c
│ │ -  [ 3c757]  EVP_PKEY_set_type_by_keymgmt
│ │ -  [ 3c774]  rsa_pss_keygen_saltlen
│ │ -  [ 3c78b]  qx
│ │ -  [ 3c78e]  rsa-factor3
│ │ -  [ 3c79a]  pcounter
│ │ -  [ 3c7a3]  OSSL_WINCTX: Undefined
│ │ -  [ 3c7ba]  HMAC-DRBG-KDF
│ │ -  [ 3c7c8]  crypto/indicator_core.c
│ │ -  [ 3c7e0]  not a square
│ │ -  [ 3c7ed]  copy error
│ │ -  [ 3c7f8]  pbkdf2 error
│ │ -  [ 3c805]  unknown max size
│ │ -  [ 3c816]  seed_len is less than the length of q
│ │ -  [ 3c83c]  bad object header
│ │ -  [ 3c84e]  no multipart body failure
│ │ -  [ 3c868]  no space for terminating null
│ │ -  [ 3c886]  odd number of digits
│ │ -  [ 3c89b]  cannot invert
│ │ -  [ 3c8a9]  invalid compression bit
│ │ -  [ 3c8c1]  invalid field
│ │ -  [ 3c8cf]  could not load the shared library
│ │ -  [ 3c8f1]  set filename failed
│ │ -  [ 3c905]  could not unload the shared library
│ │ -  [ 3c929]  finish failed
│ │ -  [ 3c937]  signfinal error
│ │ -  [ 3c947]  unknown digest algorithm
│ │ -  [ 3c960]  unwrap error
│ │ -  [ 3c96d]  crmferror
│ │ -  [ 3c977]  error creating pollrep
│ │ -  [ 3c98e]  error creating rp
│ │ -  [ 3c9a0]  id-aes192-wrap
│ │ -  [ 3c9af]  Software engine support
│ │ -  [ 3c9c7]  bind_engine
│ │ -  [ 3c9d3]  activate
│ │ -  [ 3c9dc]  rsaEncryption
│ │ -  [ 3c9ea]  commonName
│ │ -  [ 3c9f5]  des-cbc
│ │ -  [ 3c9fd]  idea-cbc
│ │ -  [ 3ca06]  nsRevocationUrl
│ │ -  [ 3ca16]  issuerAltName
│ │ -  [ 3ca24]  X509v3 Authority Key Identifier
│ │ -  [ 3ca44]  mdc2WithRSA
│ │ -  [ 3ca50]  TLS Web Server Authentication
│ │ -  [ 3ca6e]  Netscape Server Gated Crypto
│ │ -  [ 3ca8b]  PBES2
│ │ -  [ 3ca91]  authorityInfoAccess
│ │ -  [ 3caa5]  id-smime-cti
│ │ -  [ 3cab2]  id-smime-aa-ets-RevocationRefs
│ │ -  [ 3cad1]  MD4
│ │ -  [ 3cad5]  id-aca
│ │ -  [ 3cadc]  id-mod-kea-profile-93
│ │ -  [ 3caf2]  id-cct-crs
│ │ -  [ 3cafd]  IANA
│ │ -  [ 3cb02]  pilotGroups
│ │ -  [ 3cb0e]  pilotObject
│ │ -  [ 3cb1a]  janetMailbox
│ │ -  [ 3cb27]  setct-HODInput
│ │ -  [ 3cb36]  setct-PResData
│ │ -  [ 3cb45]  setct-CapTokenTBE
│ │ -  [ 3cb57]  setct-CredResTBE
│ │ -  [ 3cb68]  setCext-setQualf
│ │ -  [ 3cb79]  X509v3 Any Policy
│ │ -  [ 3cb8b]  camellia-192-cbc
│ │ -  [ 3cb9c]  camellia-256-cbc
│ │ -  [ 3cbad]  certificateIssuer
│ │ -  [ 3cbbf]  hmac-md5
│ │ -  [ 3cbc8]  ecdsa-with-Recommended
│ │ -  [ 3cbdf]  hmacWithMD5
│ │ -  [ 3cbeb]  id-GostR3410-94-CryptoPro-A-ParamSet
│ │ -  [ 3cc10]  crossCertificatePair
│ │ -  [ 3cc25]  uniqueMember
│ │ -  [ 3cc32]  aes-128-xts
│ │ -  [ 3cc3e]  dhpublicnumber
│ │ -  [ 3cc4d]  AES-128-CBC-HMAC-SHA256
│ │ -  [ 3cc65]  jurisdictionC
│ │ -  [ 3cc73]  CAMELLIA-256-GCM
│ │ -  [ 3cc84]  ipsecIKE
│ │ -  [ 3cc8d]  AuthNULL
│ │ -  [ 3cc96]  aria-128-ofb
│ │ -  [ 3cca3]  aria-192-cfb
│ │ -  [ 3ccb0]  aria-128-cfb1
│ │ -  [ 3ccbe]  sha3-224
│ │ -  [ 3ccc7]  sha3-512
│ │ -  [ 3ccd0]  id-hmacWithSHA3-224
│ │ -  [ 3cce4]  dsa_with_SHA512
│ │ -  [ 3ccf4]  id-dsa-with-sha3-256
│ │ -  [ 3cd09]  kuznyechik-kexp15
│ │ -  [ 3cd1b]  ipAddr-asNumberv2
│ │ -  [ 3cd2d]  etsi
│ │ -  [ 3cd32]  Microsoft NTDS CA Extension
│ │ -  [ 3cd4e]  X509v3 Delegated Name Constraints
│ │ -  [ 3cd70]  aAissuingDistributionPoint
│ │ -  [ 3cd8b]  X509v3 Authorization Validation
│ │ -  [ 3cdab]  oid exists
│ │ -  [ 3cdb6]  digest err
│ │ -  [ 3cdc1]  request not signed
│ │ -  [ 3cdd4]  root ca not trusted
│ │ -  [ 3cde8]  status not yet valid
│ │ -  [ 3cdfd]  expecting public key blob
│ │ -  [ 3ce17]  keyblob header parse error
│ │ -  [ 3ce32]  PEM_do_header
│ │ -  [ 3ce40]  PKCS12_BAGS
│ │ -  [ 3ce4c]  crypto/pkcs12/p12_crpt.c
│ │ -  [ 3ce65]  iv gen error
│ │ -  [ 3ce72]  mac setup error
│ │ -  [ 3ce82]  PKCS7_DIGEST
│ │ -  [ 3ce8f]  d.digest
│ │ -  [ 3ce98]  crypto/pkcs7/pk7_lib.c
│ │ -  [ 3ceaf]  additional input too long
│ │ -  [ 3cec9]  entropy out of range
│ │ -  [ 3cede]  error initialising drbg
│ │ -  [ 3cef6]  Function not implemented
│ │ -  [ 3cf0f]  in error state
│ │ -  [ 3cf1e]  personalisation string too long
│ │ -  [ 3cf3e]  reseed error
│ │ -  [ 3cf4b]  too much nonce requested
│ │ -  [ 3cf64]  random_conf_init
│ │ -  [ 3cf75]  block type is not 01
│ │ -  [ 3cf8a]  invalid keypair
│ │ -  [ 3cf9a]  mgf1 digest not allowed
│ │ -  [ 3cfb2]  RSA_sign_ASN1_OCTET_STRING
│ │ -  [ 3cfcd]  unregistered scheme
│ │ -  [ 3cfe1]  OSSL_STORE_INFO_new_PKEY
│ │ -  [ 3cffa]  loader_from_algorithm
│ │ -  [ 3d010]  invalid signer certificate purpose
│ │ -  [ 3d033]  general_allocate_prompt
│ │ -  [ 3d04b]  CERTIFICATEPOLICIES
│ │ -  [ 3d05f]  d.cpsuri
│ │ -  [ 3d068]  %*sCPS: %.*s
│ │ -  [ 3d075]  type_id
│ │ -  [ 3d07d]  d.otherName
│ │ -  [ 3d089]  GeneralNames
│ │ -  [ 3d096]  i2v_AUTHORITY_INFO_ACCESS
│ │ -  [ 3d0b0]  SSL Server
│ │ -  [ 3d0bb]  crypto/x509/v3_bcons.c
│ │ -  [ 3d0d2]  name.fullname
│ │ -  [ 3d0e0]  removeFromCRL
│ │ -  [ 3d0ee]  IPAddressRange
│ │ -  [ 3d0fd]  OSSL_TARGETING_INFORMATION
│ │ -  [ 3d118]  Targets
│ │ -  [ 3d121]  %*sLog       : %s
│ │ -  [ 3d134]  %*sSignature : 
│ │ -  [ 3d144]  contentsOfAdmissions
│ │ -  [ 3d159]  ossl_x509v3_cache_extensions
│ │ -  [ 3d176]  SSL server
│ │ -  [ 3d181]  othername: %s
│ │ -  [ 3d18f]  othername
│ │ -  [ 3d199]  v2i_GENERAL_NAME_ex
│ │ -  [ 3d1ad]  crypto/x509/v3_skid.c
│ │ -  [ 3d1c3]  s2i_skey_id
│ │ -  [ 3d1cf]  invalid section
│ │ -  [ 3d1df]  unable to get certificate CRL
│ │ -  [ 3d1fd]  X509_CRL_digest
│ │ -  [ 3d20d]  provider=base,fips=yes,output=der,structure=PrivateKeyInfo
│ │ -  [ 3d248]  provider=base,fips=no,output=der,structure=EncryptedPrivateKeyInfo
│ │ -  [ 3d28b]  SHA2-384:SHA-384:SHA384:2.16.840.1.101.3.4.2.2
│ │ -  [ 3d2ba]  OpenSSL CMAC via EVP_PKEY implementation
│ │ -  [ 3d2e3]  provider=default,fips=yes,output=der,structure=dh
│ │ -  [ 3d315]  provider=default,fips=yes,input=der,structure=type-specific
│ │ -  [ 3d351]  AES-128-XTS:1.3.111.2.1619.0.1.1
│ │ -  [ 3d372]  ARIA-128-CCM:1.2.410.200046.1.1.37
│ │ -  [ 3d395]  ARIA-192-CBC:ARIA192:1.2.410.200046.1.1.7
│ │ -  [ 3d3bf]  SM4-ECB:1.2.156.10197.1.104.1
│ │ -  [ 3d3dd]  chacha20_set_ctx_params
│ │ -  [ 3d3f5]  blake2s256_internal_final
│ │ -  [ 3d40f]  providers/implementations/encode_decode/decode_msblob2key.c
│ │ -  [ 3d44b]  PVKKDF
│ │ -  [ 3d452]  dh_to_type_specific_params_der_encode
│ │ -  [ 3d478]  sm2_to_type_specific_no_pub_der_encode
│ │ -  [ 3d49f]  J:   
│ │ -  [ 3d4a5]  ecdh_X9_63_kdf_derive
│ │ -  [ 3d4bb]  ecdh_match_params
│ │ -  [ 3d4cd]  kdf_argon2_derive
│ │ -  [ 3d4df]  operation
│ │ -  [ 3d4e9]  ecxkem_encapsulate
│ │ -  [ 3d4fc]  rsasve_generate
│ │ -  [ 3d50c]  rsa_gen_set_params
│ │ -  [ 3d51f]  seed_src_reseed
│ │ -  [ 3d52f]  providers/implementations/signature/dsa_sig.c
│ │ -  [ 3d55d]  ed448_sign
│ │ -  [ 3d568]  OAEP padding not allowed for signing / verifying
│ │ -  [ 3d599]  ossl_sm2_compute_z_digest
│ │ -  [ 3d5b3]  missing constant
│ │ -  [ 3d5c4]  missing pass
│ │ -  [ 3d5d1]  missing type
│ │ -  [ 3d5de]  ype
│ │ -  [ 3d5e2]  check
│ │ -  [ 3d5e8]  s-randkey
│ │ -  [ 3d5f2]  ey-check
│ │ -  [ 3d5fb]  eprime-generator
│ │ -  [ 3d60c]  eed
│ │ -  [ 3d610]  tls
│ │ -  [ 3d614]  unsupported register class
│ │ -  [ 3d62f]  unknown personality routine
│ │ -  [ 3d64b]  s27
│ │ -  [ 3d64f]  d26
│ │ -  [ 3d653]  d27
│ │ -  [ 3d657]  ADH-AES256-SHA
│ │ -  [ 3d666]  TLS_DHE_RSA_WITH_AES_128_CCM
│ │ -  [ 3d683]  TLS_ECDH_anon_WITH_AES_128_CBC_SHA
│ │ -  [ 3d6a6]  PSK-NULL-SHA256
│ │ -  [ 3d6b6]  TLS_PSK_WITH_NULL_SHA384
│ │ -  [ 3d6cf]  ECDHE-PSK-AES256-CBC-SHA
│ │ -  [ 3d6e8]  TLS_ECDHE_PSK_WITH_NULL_SHA256
│ │ -  [ 3d707]  TLS_SRP_SHA_DSS_WITH_AES_256_CBC_SHA
│ │ -  [ 3d72c]  DHE-RSA-CHACHA20-POLY1305
│ │ -  [ 3d746]  TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
│ │ -  [ 3d768]  TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
│ │ -  [ 3d791]  IANA-GOST2012-GOST8912-GOST8912
│ │ -  [ 3d7b1]  SEED-SHA
│ │ -  [ 3d7ba]  TLS_RSA_WITH_SEED_CBC_SHA
│ │ -  [ 3d7d4]  master_key
│ │ -  [ 3d7df]  gost2001
│ │ -  [ 3d7e8]  kGOST
│ │ -  [ 3d7ee]  SEED
│ │ -  [ 3d7f3]  eNULL
│ │ -  [ 3d7f9]  EDH-DSS-DES-CBC3-SHA
│ │ -  [ 3d80e]  bad certificate
│ │ -  [ 3d81e]  failed to init async
│ │ -  [ 3d833]  inconsistent early data alpn
│ │ -  [ 3d850]  inconsistent early data sni
│ │ -  [ 3d86c]  missing psk kex modes extension
│ │ -  [ 3d88c]  no change following hrr
│ │ -  [ 3d8a4]  no suitable record layer
│ │ -  [ 3d8bd]  null ssl method passed
│ │ -  [ 3d8d4]  renegotiate ext too long
│ │ -  [ 3d8ed]  required compression algorithm missing
│ │ -  [ 3d914]  ssl/tls alert unsupported certificate
│ │ -  [ 3d93a]  ssl section empty
│ │ -  [ 3d94c]  unable to find public key parameters
│ │ -  [ 3d971]  ssl_validate_ct
│ │ -  [ 3d981]  ssl_do_config
│ │ -  [ 3d98f]  groups
│ │ -  [ 3d996]  DTLSv1
│ │ -  [ 3d99d]  DTLSv1.2
│ │ -  [ 3d9a6]  X448
│ │ -  [ 3d9ab]  tls-sigalg-sec-bits
│ │ -  [ 3d9bf]  dsa_sha512
│ │ -  [ 3d9ca]  failed to start assist thread
│ │ -  [ 3d9e8]  expect_quic_with_stream_lock
│ │ -  [ 3da05]  QUIC error code: 0x%llx%s%s%s (triggered by frame type: 0x%llx%s%s%s), reason: "%s"
│ │ -  [ 3da59]  ORIG_DCID was not sent but is required
│ │ -  [ 3da80]  stateless_reset_token
│ │ -  [ 3da96]  connection_id
│ │ -  [ 3daa4]  version negotiation failure
│ │ -  [ 3dac0]  packet_number
│ │ -  [ 3dace]  token
│ │ -  [ 3dad4]  ect0
│ │ -  [ 3dad9]  final_size
│ │ -  [ 3dae4]  depack_do_frame_max_data
│ │ -  [ 3dafd]  STREAM_DATA_BLOCKED frame for TX only stream
│ │ -  [ 3db2a]  ALPN must be configured when using QUIC
│ │ -  [ 3db52]  ossl_quic_gen_rand_conn_id
│ │ -  [ 3db6d]  RETIRE_CONN_ID
│ │ -  [ 3db7c]  ssl/record/rec_layer_s3.c
│ │ -  [ 3db96]  tls_new_record_layer
│ │ -  [ 3dbab]  tls_construct_ctos_psk
│ │ -  [ 3dbc2]  tls_parse_ctos_psk_kex_modes
│ │ -  [ 3dbdf]  tls_construct_stoc_ec_pt_formats
│ │ -  [ 3dc00]  tls_construct_stoc_status_request
│ │ -  [ 3dc22]  tls_construct_next_proto
│ │ -  [ 3dc3b]  ossl_statem_server_read_transition
│ │ -  [ 3dc5e]  opaqueBlob
│ │ -  [ 3dc69]  ; 
│ │ -  [ 3dc6c]  :
│ │ -  [ 3dc6e]  BAD RECURSION DEPTH\n
│ │ -  [ 3dc83]  asn1_check_tlen
│ │ -  [ 3dc93]  crypto/asn1/a_bitstr.c
│ │ -  [ 3dcaa]  ossl_asn1_do_adb
│ │ -  [ 3dcbb]  %ju\n
│ │ -  [ 3dcc0]  WSAStartup
│ │ -  [ 3dccb]  dgram_pair_recvmmsg
│ │ -  [ 3dcdf]  crypto/asn1/a_d2i_fp.c
│ │ -  [ 3dcf6]  PKCS5_pbe2_set_iv_ex
│ │ -  [ 3dd0b]  .include
│ │ -  [ 3dd14]  do_tcreate
│ │ -  [ 3dd1f]  ENUM
│ │ -  [ 3dd24]  VISIBLE
│ │ -  [ 3dd2c]  parse_tagging
│ │ -  [ 3dd3a]  crypto/dh/dh_key.c
│ │ -  [ 3dd4d]  generate_key
│ │ -  [ 3dd5a]  OpenSSL 'dlfcn' shared library method
│ │ -  [ 3dd80]  ec_key_point_format_fromdata
│ │ -  [ 3dd9d]  SECG curve over a 160 bit prime field
│ │ -  [ 3ddc3]  SECG curve over a 192 bit prime field
│ │ -  [ 3dde9]  WTLS curve over a 224 bit prime field
│ │ -  [ 3de0f]  ossl_ec_key_simple_oct2priv
│ │ -  [ 3de2b]  crypto/ec/ec_lib.c
│ │ -  [ 3de3e]  EC_GROUP_set_generator
│ │ -  [ 3de55]  EC_POINT_invert
│ │ -  [ 3de65]  ossl_ec_GFp_simple_group_check_discriminant
│ │ -  [ 3de91]  ENGINE_add
│ │ -  [ 3de9c]  BIO routines
│ │ -  [ 3dea9]  secp160r2
│ │ -  [ 3deb3]  prime192v2
│ │ -  [ 3debe]  prime239v1
│ │ -  [ 3dec9]  sect193r1
│ │ -  [ 3ded3]  crypto/evp/encode.c
│ │ -  [ 3dee7]  alg_module_init
│ │ -  [ 3def7]  crypto/evp/evp_enc.c
│ │ -  [ 3df0c]  crypto/evp/keymgmt_lib.c
│ │ -  [ 3df25]  evp_pkey_get0_EC_KEY_int
│ │ -  [ 3df3e]  md
│ │ -  [ 3df41]  x931
│ │ -  [ 3df46]  pss
│ │ -  [ 3df4a]  qy
│ │ -  [ 3df4d]  rsa-coefficient2
│ │ -  [ 3df5e]  ffdhe8192
│ │ -  [ 3df68]  subgroup factor:
│ │ -  [ 3df79]  check pubkey invalid
│ │ -  [ 3df8e]  keys not set
│ │ -  [ 3df9b]  no parameters set
│ │ -  [ 3dfad]  command not supported
│ │ -  [ 3dfc3]  inaccessible domain parameters
│ │ -  [ 3dfe2]  missing private key
│ │ -  [ 3dff6]  explicit tag not constructed
│ │ -  [ 3e013]  unknown message digest algorithm
│ │ -  [ 3e034]  number too large
│ │ -  [ 3e045]  param not integer type
│ │ -  [ 3e05c]  not a NIST prime
│ │ -  [ 3e06d]  dso not found
│ │ -  [ 3e07b]  invalid url path
│ │ -  [ 3e08c]  decrypt error
│ │ -  [ 3e09a]  msgsigdigest error
│ │ -  [ 3e0ad]  not a signed receipt
│ │ -  [ 3e0c2]  not pwri
│ │ -  [ 3e0cb]  type not digested data
│ │ -  [ 3e0e2]  iterationcount below 100
│ │ -  [ 3e0fb]  error creating genp
│ │ -  [ 3e10f]  invalid args
│ │ -  [ 3e11c]  missing key input for creating protection
│ │ -  [ 3e146]  pkistatusinfo not found
│ │ -  [ 3e15e]  unknown pkistatus
│ │ -  [ 3e170]  wrong pbm value
│ │ -  [ 3e180]  BF
│ │ -  [ 3e183]  id-aes256-wrap-pad
│ │ -  [ 3e196]  dynamic_load
│ │ -  [ 3e1a3]  Specifies whether to load from 'DIR_ADD' directories (0=no,1=yes,2=mandatory)
│ │ -  [ 3e1f1]  assertion failed: WITHIN_ARENA(chunk)
│ │ -  [ 3e217]  assertion failed: WITHIN_FREELIST(temp2->p_next) || WITHIN_ARENA(temp2->p_next)
│ │ -  [ 3e267]  crypto/o_str.c
│ │ -  [ 3e276]  crypto/param_build_set.c
│ │ -  [ 3e28f]  OSSL_PARAM_set_int32
│ │ -  [ 3e2a4]  general_get_int
│ │ -  [ 3e2b4]  No password method specified
│ │ -  [ 3e2d1]  calling gettimeofday()
│ │ -  [ 3e2e8]  md5
│ │ -  [ 3e2ec]  PBE-MD2-DES
│ │ -  [ 3e2f8]  rsa
│ │ -  [ 3e2fc]  pkcs7-data
│ │ -  [ 3e307]  DES-EDE-CBC
│ │ -  [ 3e313]  des-ede3-cfb
│ │ -  [ 3e320]  subjectKeyIdentifier
│ │ -  [ 3e335]  CAST5-OFB
│ │ -  [ 3e33f]  id-kp
│ │ -  [ 3e345]  pbeWithSHA1And2-KeyTripleDES-CBC
│ │ -  [ 3e366]  id-qt-cps
│ │ -  [ 3e370]  id-smime-aa-contentReference
│ │ -  [ 3e38d]  id-cmc-queryPending
│ │ -  [ 3e3a1]  id-cmc-confirmCertAcceptance
│ │ -  [ 3e3be]  experimental
│ │ -  [ 3e3cb]  Experimental
│ │ -  [ 3e3d8]  clearance
│ │ -  [ 3e3e2]  md4WithRSAEncryption
│ │ -  [ 3e3f7]  X509v3 Policy Constraints
│ │ -  [ 3e411]  pilotAttributeSyntax
│ │ -  [ 3e426]  generationQualifier
│ │ -  [ 3e43a]  setct-AuthRevResBaggage
│ │ -  [ 3e452]  setct-CertInqReqTBS
│ │ -  [ 3e466]  setct-CapReqTBE
│ │ -  [ 3e476]  setCext-setExt
│ │ -  [ 3e485]  des-cdmf
│ │ -  [ 3e48e]  ITU-T
│ │ -  [ 3e494]  msUPN
│ │ -  [ 3e49a]  aes-192-cfb8
│ │ -  [ 3e4a7]  sha512WithRSAEncryption
│ │ -  [ 3e4bf]  camellia-192-ecb
│ │ -  [ 3e4d0]  GOST 28147-89
│ │ -  [ 3e4de]  userPassword
│ │ -  [ 3e4eb]  id-aes128-GCM
│ │ -  [ 3e4f9]  id-camellia192-wrap
│ │ -  [ 3e50d]  ct_precert_scts
│ │ -  [ 3e51d]  aes-128-ocb
│ │ -  [ 3e529]  id-tc26-gost-3410-2012-512-paramSetA
│ │ -  [ 3e54e]  kx-dhe
│ │ -  [ 3e555]  kx-dhe-psk
│ │ -  [ 3e560]  hmac-sha3-384
│ │ -  [ 3e56e]  uacurve2
│ │ -  [ 3e577]  kmac128
│ │ -  [ 3e57f]  NAIRealm
│ │ -  [ 3e588]  classSignToolKC2
│ │ -  [ 3e599]  authorizationValidation
│ │ -  [ 3e5b1]  id-kp-wisun-fan-device
│ │ -  [ 3e5c8]  responseStatus
│ │ -  [ 3e5d7]  no signer key
│ │ -  [ 3e5e5]  read key
│ │ -  [ 3e5ee]  PEM_def_callback
│ │ -  [ 3e5ff]  DH PARAMETERS
│ │ -  [ 3e60d]  crypto/pem/pem_pkey.c
│ │ -  [ 3e623]  PKCS12_key_gen_utf8_ex
│ │ -  [ 3e63a]  stack_to_property_list
│ │ -  [ 3e651]  RAND_priv_bytes_ex
│ │ -  [ 3e664]  RAND_get0_primary
│ │ -  [ 3e676]  ossl_rand_pool_add_begin
│ │ -  [ 3e68f]  dmq1
│ │ -  [ 3e694]  invalid digest length
│ │ -  [ 3e6aa]  RSA_padding_add_none
│ │ -  [ 3e6bf]  ossl_rsa_padding_check_PKCS1_type_2_TLS
│ │ -  [ 3e6e7]  pkey_rsa_ctrl
│ │ -  [ 3e6f5]  file
│ │ -  [ 3e6fa]  PEM_X509_INFO_read_bio_ex
│ │ -  [ 3e714]  d.dNSName
│ │ -  [ 3e71e]  crypto/x509/v3_info.c
│ │ -  [ 3e734]  v2i_ASN1_BIT_STRING
│ │ -  [ 3e748]  sslCA
│ │ -  [ 3e74e]  dataEncipherment
│ │ -  [ 3e75f]  keyAgreement
│ │ -  [ 3e76c]  onlysomereasons
│ │ -  [ 3e77c]  onlyattr
│ │ -  [ 3e785]  %*sIssuer: 
│ │ -  [ 3e791]  crypto/x509/v3_addr.c
│ │ -  [ 3e7a7]  crypto/x509/v3_asid.c
│ │ -  [ 3e7bd]  %*sinherit\n
│ │ -  [ 3e7c9]  %s\n
│ │ -  [ 3e7cd]  %*sSigned Certificate Timestamp:
│ │ -  [ 3e7ef]  %*sVersion   : 
│ │ -  [ 3e7ff]  infinite
│ │ -  [ 3e808]  Netscape SSL server
│ │ -  [ 3e81c]  copy
│ │ -  [ 3e821]  Attributes
│ │ -  [ 3e82c]  invalid extension string
│ │ -  [ 3e845]  invalid policy identifier
│ │ -  [ 3e85f]  invalid syntax
│ │ -  [ 3e86e]  othername error
│ │ -  [ 3e87e]  X509_NAME_oneline
│ │ -  [ 3e890]  invalid or inconsistent certificate policy extension
│ │ -  [ 3e8c5]  Suite B: certificate version invalid
│ │ -  [ 3e8ea]  crypto/x509/x509_vfy.c
│ │ -  [ 3e901]  crypto/x509/x509_vpm.c
│ │ -  [ 3e918]  trust
│ │ -  [ 3e91e]  skcipher
│ │ -  [ 3e927]  provider=base,fips=yes,input=der,structure=PrivateKeyInfo
│ │ -  [ 3e961]  SHA3-384:2.16.840.1.101.3.4.2.9
│ │ -  [ 3e981]  OpenSSL DSA implementation
│ │ -  [ 3e99c]  X448:1.3.101.111
│ │ -  [ 3e9ad]  RSA-SHA1:RSA-SHA-1:sha1WithRSAEncryption:1.2.840.113549.1.1.5
│ │ -  [ 3e9eb]  ECDSA-SHA3-224:ecdsa_with_SHA3-224:id-ecdsa-with-sha3-224:2.16.840.1.101.3.4.3.9
│ │ -  [ 3ea3c]  provider=default,fips=no,output=text
│ │ -  [ 3ea61]  provider=default,fips=yes,output=pem,structure=X9.62
│ │ -  [ 3ea96]  ARIA-256-OFB:1.2.410.200046.1.1.14
│ │ -  [ 3eab9]  ossl_aes_gcm_siv_init
│ │ -  [ 3eacf]  ossl_aes_gcm_siv_get_ctx_params
│ │ -  [ 3eaef]  aes_siv_set_ctx_params
│ │ -  [ 3eb06]  encode_dsa_params
│ │ -  [ 3eb18]  key_to_pubkey
│ │ -  [ 3eb26]  rsapss_to_SubjectPublicKeyInfo_der_encode
│ │ -  [ 3eb50]  dh_to_EncryptedPrivateKeyInfo_pem_encode
│ │ -  [ 3eb79]  dsa_spki_pub_to_der
│ │ -  [ 3eb8d]  X25519 PRIVATE KEY
│ │ -  [ 3eba0]  x448_to_SubjectPublicKeyInfo_pem_encode
│ │ -  [ 3ebc8]  ec_to_EC_pem_encode
│ │ -  [ 3ebdc]  ec_to_text
│ │ -  [ 3ebe7]  %s Public-Key:\n
│ │ -  [ 3ebf7]  providers/implementations/exchange/ecx_exch.c
│ │ -  [ 3ec25]  ecx_dupctx
│ │ -  [ 3ec30]  early_clean
│ │ -  [ 3ec3c]  kdf_sshkdf_derive
│ │ -  [ 3ec4e]  Invalid sender auth public key
│ │ -  [ 3ec6d]  providers/implementations/keymgmt/dsa_kmgmt.c
│ │ -  [ 3ec9b]  ossl_drbg_hmac_init
│ │ -  [ 3ecaf]  providers/implementations/signature/eddsa_sig.c
│ │ -  [ 3ecdf]  rsa_set_ctx_params
│ │ -  [ 3ecf2]  cofactor required
│ │ -  [ 3ed04]  not supported
│ │ -  [ 3ed12]  seed sources must not have a parent
│ │ -  [ 3ed36]  unable to load sha256
│ │ -  [ 3ed4c]  ossl_cipher_generic_stream_final
│ │ -  [ 3ed6d]  ossl_cipher_generic_cipher
│ │ -  [ 3ed88]  ccm_init
│ │ -  [ 3ed91]  ildinfo
│ │ -  [ 3ed99]  ault-digest
│ │ -  [ 3eda5]  ep-label
│ │ -  [ 3edae]  ation
│ │ -  [ 3edb4]  oid
│ │ -  [ 3edb8]  nterleave
│ │ -  [ 3edc2]  getRegister
│ │ -  [ 3edce]  s17
│ │ -  [ 3edd2]  d1
│ │ -  [ 3edd5]  unknown register
│ │ -  [ 3ede6]  ssl3_ctx_ctrl
│ │ -  [ 3edf4]  TLS_RSA_WITH_AES_128_CBC_SHA256
│ │ -  [ 3ee14]  TLS_DHE_RSA_WITH_AES_256_CCM_8
│ │ -  [ 3ee33]  TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
│ │ -  [ 3ee58]  ECDHE-RSA-AES128-SHA256
│ │ -  [ 3ee70]  TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
│ │ -  [ 3ee94]  ECDHE-PSK-NULL-SHA256
│ │ -  [ 3eeaa]  SRP-DSS-AES-128-CBC-SHA
│ │ -  [ 3eec2]  CAMELLIA256-SHA
│ │ -  [ 3eed2]  TLS_GOSTR341001_WITH_NULL_GOSTR3411
│ │ -  [ 3eef6]  DHE-RSA-SEED-SHA
│ │ -  [ 3ef07]  ssl_version
│ │ -  [ 3ef13]  bad key update
│ │ -  [ 3ef22]  bad length
│ │ -  [ 3ef2d]  bad psk
│ │ -  [ 3ef35]  data length too long
│ │ -  [ 3ef4a]  https proxy request
│ │ -  [ 3ef5e]  no private key assigned
│ │ -  [ 3ef76]  old session cipher not returned
│ │ -  [ 3ef96]  pipeline failure
│ │ -  [ 3efa7]  protocol is shutdown
│ │ -  [ 3efbc]  request pending
│ │ -  [ 3efcc]  stream count limited
│ │ -  [ 3efe1]  unknown cipher type
│ │ -  [ 3eff5]  SSL_CONF_cmd
│ │ -  [ 3f002]  CipherString
│ │ -  [ 3f00f]  RxCertificateCompression
│ │ -  [ 3f028]  TLS1-PRF
│ │ -  [ 3f031]  tls1_set_groups_list
│ │ -  [ 3f046]  tls12_check_peer_sigalg
│ │ -  [ 3f05e]  tls-group-is-kem
│ │ -  [ 3f06f]  ecdsa_brainpoolP256r1_sha256
│ │ -  [ 3f08c]  dsa_sha256
│ │ -  [ 3f097]  TLS13-KDF
│ │ -  [ 3f0a1]  MAX_UDP_PAYLOAD_SIZE appears multiple times
│ │ -  [ 3f0cd]  zero-length CID in PREFERRED_ADDR
│ │ -  [ 3f0ef]  transport
│ │ -  [ 3f0f9]  handshake alert
│ │ -  [ 3f109]  JSON-SEQ
│ │ -  [ 3f112]  QUIC
│ │ -  [ 3f117]  system_info
│ │ -  [ 3f123]  connection_closed
│ │ -  [ 3f135]  \n
│ │ -  [ 3f138]  connectivity:connection_state_updated
│ │ -  [ 3f15e]  connectivity:connection_closed
│ │ -  [ 3f17d]  attempted
│ │ -  [ 3f187]  key_update_error
│ │ -  [ 3f198]  dcid
│ │ -  [ 3f19d]  acked_ranges
│ │ -  [ 3f1aa]  error_space
│ │ -  [ 3f1b6]  error_code_value
│ │ -  [ 3f1c7]  non-minimal frame type encoding
│ │ -  [ 3f1e7]  tls-data-size
│ │ -  [ 3f1f5]  tls13_post_process_record
│ │ -  [ 3f20f]  final_sig_algs
│ │ -  [ 3f21e]  custom_ext_parse
│ │ -  [ 3f22f]  tls_parse_ctos_maxfragmentlen
│ │ -  [ 3f24d]  tls_construct_stoc_use_srtp
│ │ -  [ 3f269]  tls_construct_cke_gost18
│ │ -  [ 3f282]  tls13_save_handshake_digest_for_pha
│ │ -  [ 3f2a6]  tls_process_next_proto
│ │ -  [ 3f2bd]  tls_process_cke_rsa
│ │ -  [ 3f2d1]   GMT
│ │ -  [ 3f2d6]  ASN1_STRING_set
│ │ -  [ 3f2e6]  UTCTIME
│ │ -  [ 3f2ee]  <ASN1 29>
│ │ -  [ 3f2f8]  asn1_d2i_ex_primitive
│ │ -  [ 3f30e]  %*s
│ │ -  [ 3f312]  lookup returned nothing
│ │ -  [ 3f32a]  dgram_pair_ctrl_set_write_buf_size
│ │ -  [ 3f34d]  PBMAC1PARAM
│ │ -  [ 3f359]  line 
│ │ -  [ 3f35f]  CONF_modules_load
│ │ -  [ 3f371]  module_load_dso
│ │ -  [ 3f381]  nomask
│ │ -  [ 3f388]  BITLIST
│ │ -  [ 3f390]  UTF8String
│ │ -  [ 3f39b]  section=%s
│ │ -  [ 3f3a6]  X9.42 DH
│ │ -  [ 3f3af]  crypto/dsa/dsa_lib.c
│ │ -  [ 3f3c4]  DSO_new_method
│ │ -  [ 3f3d3]  %*spub:\n
│ │ -  [ 3f3dc]  i2d_ECPKParameters
│ │ -  [ 3f3ef]  i2d_ECPrivateKey
│ │ -  [ 3f400]  EC_POINT_set_compressed_coordinates
│ │ -  [ 3f424]  ossl_ecdsa_deterministic_sign
│ │ -  [ 3f442]  ECDSA_do_sign_ex
│ │ -  [ 3f453]  ossl_ec_GFp_simple_blind_coordinates
│ │ -  [ 3f478]  PKCS7 routines
│ │ -  [ 3f487]  random number generator
│ │ -  [ 3f49f]  DSO support routines
│ │ -  [ 3f4b4]  crypto/evp/e_aes.c
│ │ -  [ 3f4c7]  aes_ccm_init_key
│ │ -  [ 3f4d8]  aes_wrap_init_key
│ │ -  [ 3f4ea]  keylen
│ │ -  [ 3f4f1]  tls1multi_maxbufsz
│ │ -  [ 3f504]  EVP_CIPHER_CTX_copy
│ │ -  [ 3f518]  ossl_asn1_type_get_octetstring_int
│ │ -  [ 3f53b]  keymgmt_from_algorithm
│ │ -  [ 3f552]  EVP_DigestVerifyFinal
│ │ -  [ 3f568]  evp_pkey_get0_DH_int
│ │ -  [ 3f57d]  EVP_PKEY_get_params
│ │ -  [ 3f591]  new_raw_key_int
│ │ -  [ 3f5a1]  pkey_set_type
│ │ -  [ 3f5af]  [action:%d, state:%d] trying to get a BIGNUM via ctrl call
│ │ -  [ 3f5ea]  mgf1-digest
│ │ -  [ 3f5f6]  implicit-rejection
│ │ -  [ 3f609]  hexsecret
│ │ -  [ 3f613]  X942KDF-ASN1
│ │ -  [ 3f620]  rsa-factor8
│ │ -  [ 3f62c]  fips186_4
│ │ -  [ 3f636]  pkey_ec_derive
│ │ -  [ 3f645]  ossl_method_construct_precondition
│ │ -  [ 3f668]  built on: Tue Dec 24 14:53:20 2024 UTC
│ │ +  [ 3907f]  dsa2text_encode
│ │ +  [ 3908f]  ec2text_encode
│ │ +  [ 3909e]  PSS parameter restrictions:\n
│ │ +  [ 390bb]  m_cost must be greater or equal than 8 times the number of lanes
│ │ +  [ 390fc]  kdf_hkdf_derive
│ │ +  [ 3910c]  kdf_sshkdf_set_ctx_params
│ │ +  [ 39126]  use-keybits
│ │ +  [ 39132]  blake2_mac_set_ctx_params
│ │ +  [ 3914c]  providers/implementations/rands/drbg_ctr.c
│ │ +  [ 39177]  /dev/srandom
│ │ +  [ 39184]  nonce-type
│ │ +  [ 3918f]  digest-size
│ │ +  [ 3919b]  ed25519_sign
│ │ +  [ 391a8]  ed448_digest_signverify_init
│ │ +  [ 391c5]  input-type
│ │ +  [ 391d0]  failed to decrypt
│ │ +  [ 391e2]  fips module conditional error
│ │ +  [ 39200]  providers/implementations/ciphers/ciphercommon_gcm.c
│ │ +  [ 39235]  en
│ │ +  [ 39238]  el
│ │ +  [ 3923b]  ider-name
│ │ +  [ 39245]  sion_id
│ │ +  [ 3924d]  ssl/record/methods/tls_pad.c
│ │ +  [ 3926a]  s28
│ │ +  [ 3926e]  TLS_DHE_DSS_WITH_AES_128_CBC_SHA256
│ │ +  [ 39292]  DHE-RSA-AES128-CCM8
│ │ +  [ 392a6]  ECDHE-RSA-AES256-GCM-SHA384
│ │ +  [ 392c2]  DHE-PSK-NULL-SHA
│ │ +  [ 392d3]  DHE-PSK-AES256-CBC-SHA
│ │ +  [ 392ea]  TLS_RSA_PSK_WITH_NULL_SHA384
│ │ +  [ 39307]  SUITEB192
│ │ +  [ 39311]  aECDSA
│ │ +  [ 39318]  CAMELLIA128
│ │ +  [ 39324]  ssl_cipher_process_rulestr
│ │ +  [ 3933f]  decryption failed or bad record mac
│ │ +  [ 39363]  duplicate compression id
│ │ +  [ 3937c]  got a fin before a ccs
│ │ +  [ 39393]  missing ecdsa signing cert
│ │ +  [ 393ae]  no ciphers available
│ │ +  [ 393c3]  peer did not return a certificate
│ │ +  [ 393e5]  renegotiation encoding err
│ │ +  [ 39400]  renegotiation mismatch
│ │ +  [ 39417]  tlsv1 bad certificate hash value
│ │ +  [ 39438]  SSL_do_handshake
│ │ +  [ 39449]  decrypt-only
│ │ +  [ 39456]  dhparam
│ │ +  [ 3945e]  TLSv1.1
│ │ +  [ 39466]  ssl/ssl_sess.c
│ │ +  [ 39475]  tls-sigalg-sig-oid
│ │ +  [ 39488]  properties
│ │ +  [ 39493]  SERVER_HANDSHAKE_TRAFFIC_SECRET
│ │ +  [ 394b3]  retiring connection id limit violated
│ │ +  [ 394da]  ch_on_handshake_alert
│ │ +  [ 394f0]  new packet with old keys
│ │ +  [ 39509]  local
│ │ +  [ 3950f]  cur_cwnd_size
│ │ +  [ 3951d]  qlog_format
│ │ +  [ 39529]  group_id
│ │ +  [ 39532]  invalid_token
│ │ +  [ 39540]  handshake
│ │ +  [ 3954a]  PATH_RESPONSE
│ │ +  [ 39558]  ssl/quic/uint_set.c
│ │ +  [ 3956c]  tls_default_read_n
│ │ +  [ 3957f]  final_supported_versions
│ │ +  [ 39598]  ssl/statem/extensions_clnt.c
│ │ +  [ 395b5]  ssl3_output_cert_chain
│ │ +  [ 395cc]  crypto/asn1/d2i_pr.c
│ │ +  [ 395e1]  Field=
│ │ +  [ 395e8]  crypto/asn1/tasn_new.c
│ │ +  [ 395ff]  ASN1_IA5STRING
│ │ +  [ 3960e]  DISPLAYTEXT
│ │ +  [ 3961a]  algorithm
│ │ +  [ 39624]  ZUINT32
│ │ +  [ 3962c]  nbio connect error
│ │ +  [ 3963f]  port mismatch
│ │ +  [ 3964d]  unable to tfo
│ │ +  [ 3965b]  BIO_puts
│ │ +  [ 39664]  BIO_gets
│ │ +  [ 3966d]  bio_read_intern
│ │ +  [ 3967d]  crypto/bn/bn_add.c
│ │ +  [ 39690]  crypto/bn/bn_conv.c
│ │ +  [ 396a4]  crypto/bn/bn_lib.c
│ │ +  [ 396b7]  BUF_MEM_grow_clean
│ │ +  [ 396ca]  Unprocessed type %d\n
│ │ +  [ 396df]  crypto/asn1/p5_pbev2.c
│ │ +  [ 396f6]  calling stat(%s)
│ │ +  [ 39707]  o2i_SCT_LIST
│ │ +  [ 39714]  priv_len
│ │ +  [ 3971d]  %02x%s
│ │ +  [ 39724]  %s %s%lu (%s0x%lx)\n
│ │ +  [ 39738]  DH_check_pub_key
│ │ +  [ 39749]  eckey_pub_encode
│ │ +  [ 3975a]  order
│ │ +  [ 39760]  crypto/ec/ec_curve.c
│ │ +  [ 39775]  SECG curve over a 163 bit binary field
│ │ +  [ 3979c]  crypto/ec/ec2_smpl.c
│ │ +  [ 397b1]  crypto/bn/bn_gf2m.c
│ │ +  [ 397c5]  ossl_ecdsa_simple_sign_sig
│ │ +  [ 397e0]  ossl_ec_GFp_mont_field_encode
│ │ +  [ 397fe]  ossl_decoder_cache_flush
│ │ +  [ 39817]  err:%lx:%lx:%lx:%lx
│ │ +  [ 3982b]  CRMF routines
│ │ +  [ 39839]  EVP_PKEY_decrypt
│ │ +  [ 3984a]  aes_init_key
│ │ +  [ 39857]  sect283k1
│ │ +  [ 39861]  wap-wsg-idm-ecid-wtls9
│ │ +  [ 39878]  alg_section
│ │ +  [ 39884]  No encoders were found. For standard encoders you need at least one of the default or base providers available. Did you forget to load them?
│ │ +  [ 39911]  evp_kem_init
│ │ +  [ 3991e]  EVP_DigestVerifyUpdate
│ │ +  [ 39935]  PBEPARAM
│ │ +  [ 3993e]  evp_pkey_get0_DSA_int
│ │ +  [ 39954]  rsa_pss_keygen_md
│ │ +  [ 39966]  maxmem_bytes
│ │ +  [ 39973]  fix_dh_paramgen_type
│ │ +  [ 39988]  fix_dh_nid5114
│ │ +  [ 39997]  EXPAND_ONLY
│ │ +  [ 399a3]  rsa-factor2
│ │ +  [ 399af]  pkey_ec_keygen
│ │ +  [ 399be]  pkey_ec_ctrl
│ │ +  [ 399cb]  modp_1536
│ │ +  [ 399d5]  Global default library context
│ │ +  [ 399f4]  3.4.0
│ │ +  [ 399fa]  not available
│ │ +  [ 39a08]  bad decrypt
│ │ +  [ 39a14]  setting xof failed
│ │ +  [ 39a27]  data is wrong
│ │ +  [ 39a35]  illegal boolean
│ │ +  [ 39a45]  integer too large for long
│ │ +  [ 39a60]  mime sig parse error
│ │ +  [ 39a75]  missing eoc
│ │ +  [ 39a81]  nested asn1 string
│ │ +  [ 39a94]  curve does not support ecdh
│ │ +  [ 39ab0]  incorrect file syntax
│ │ +  [ 39ac6]  received error
│ │ +  [ 39ad5]  need one signer
│ │ +  [ 39ae5]  no matching recipient
│ │ +  [ 39afb]  unsupported kek algorithm
│ │ +  [ 39b15]  error
│ │ +  [ 39b1b]  popo missing subject
│ │ +  [ 39b30]  setting mac algor failure
│ │ +  [ 39b4a]  checkafter out of range
│ │ +  [ 39b62]  encountered waiting
│ │ +  [ 39b76]  error validating protection
│ │ +  [ 39b92]  error creating crlstatus
│ │ +  [ 39bab]  ess cert digest error
│ │ +  [ 39bc1]  DES-EDE3-CBC
│ │ +  [ 39bce]  openssl
│ │ +  [ 39bd6]  EVP_PKEY_base_id
│ │ +  [ 39be7]  assertion failed: sh_testbit(chunk, list, sh.bittable)
│ │ +  [ 39c1e]  push_BN
│ │ +  [ 39c26]  crypto/params.c
│ │ +  [ 39c36]  get_ptr_internal
│ │ +  [ 39c47]  L
│ │ +  [ 39c49]  des-ecb
│ │ +  [ 39c51]  Netscape Data Type
│ │ +  [ 39c64]  sha1WithRSAEncryption
│ │ +  [ 39c7a]  Netscape CA Revocation Url
│ │ +  [ 39c95]  id-ce
│ │ +  [ 39c9b]  MDC2
│ │ +  [ 39ca0]  X509v3 Extended Key Usage
│ │ +  [ 39cba]  hmacWithSHA1
│ │ +  [ 39cc7]  id-smime-alg
│ │ +  [ 39cd4]  id-smime-spq
│ │ +  [ 39ce1]  id-smime-ct-DVCSRequestData
│ │ +  [ 39cfd]  id-smime-aa-contentIdentifier
│ │ +  [ 39d1b]  id-smime-spq-ets-sqt-unotice
│ │ +  [ 39d38]  id-pkix1-implicit-88
│ │ +  [ 39d4d]  id-cmc-responseInfo
│ │ +  [ 39d61]  Nonce
│ │ +  [ 39d67]  X500algorithms
│ │ +  [ 39d76]  ORG
│ │ +  [ 39d7a]  Domain
│ │ +  [ 39d81]  Selected Attribute Types
│ │ +  [ 39d9a]  Subject Information Access
│ │ +  [ 39db5]  ansi-X9-62
│ │ +  [ 39dc0]  aes-192-cfb
│ │ +  [ 39dcc]  account
│ │ +  [ 39dd4]  subtreeMinimumQuality
│ │ +  [ 39dea]  setct-CapRevResTBE
│ │ +  [ 39dfd]  setct-CRLNotificationTBS
│ │ +  [ 39e16]  setAttr-TokICCsig
│ │ +  [ 39e28]  DES-CDMF
│ │ +  [ 39e31]  street
│ │ +  [ 39e38]  certicom-arc
│ │ +  [ 39e45]  id-GostR3411-94-with-GostR3410-94
│ │ +  [ 39e67]  id-Gost28147-89-TestParamSet
│ │ +  [ 39e84]  id-GostR3410-2001-TestParamSet
│ │ +  [ 39ea3]  id-GostR3410-2001-CryptoPro-XchB-ParamSet
│ │ +  [ 39ecd]  id-aes128-CCM
│ │ +  [ 39edb]  aes-256-gcm
│ │ +  [ 39ee7]  AES-256-OCB
│ │ +  [ 39ef3]  HMAC GOST 34.11-2012 256 bit
│ │ +  [ 39f10]  id-tc26-gost-3410-2012-512-paramSetB
│ │ +  [ 39f35]  GOST R 34.10-2012 (512 bit) ParamSet B
│ │ +  [ 39f5c]  subjectSignTool
│ │ +  [ 39f6c]  KxGOST
│ │ +  [ 39f73]  Professional Information or basis for Admission
│ │ +  [ 39fa3]  shake128
│ │ +  [ 39fac]  RSA-SM3
│ │ +  [ 39fb4]  GOST R 34.10-2012 (256 bit) ParamSet D
│ │ +  [ 39fdb]  SRVName
│ │ +  [ 39fe3]  id-ct-ASPA
│ │ +  [ 39fee]  id-aa-ets-longTermValidation
│ │ +  [ 3a00b]  issuedOnBehalfOf
│ │ +  [ 3a01c]  crypto/asn1/a_verify.c
│ │ +  [ 3a033]  crypto/pem/pem_lib.c
│ │ +  [ 3a048]  DEK-Info: %s,
│ │ +  [ 3a056]  pem_read_bio_key_decoder
│ │ +  [ 3a06f]  unsupported pkcs12 mode
│ │ +  [ 3a087]  d.signed_and_enveloped
│ │ +  [ 3a09e]  operation not supported on this type
│ │ +  [ 3a0c3]  wrong content type
│ │ +  [ 3a0d6]  EVP_RAND_CTX_new
│ │ +  [ 3a0e7]  crypto/rand/rand_pool.c
│ │ +  [ 3a0ff]  ossl_rsa_pss_to_ctx
│ │ +  [ 3a113]  rsa_priv_encode
│ │ +  [ 3a123]  illegal or unsupported padding mode
│ │ +  [ 3a147]  invalid multi prime key
│ │ +  [ 3a15f]  rsa_multiprime_keygen
│ │ +  [ 3a175]  pkey_rsa_sign
│ │ +  [ 3a183]  encode_pkcs1
│ │ +  [ 3a190]  OSSL_STORE_INFO_new_CRL
│ │ +  [ 3a1a8]  writing strings
│ │ +  [ 3a1b8]  PEM password callback wrapper
│ │ +  [ 3a1d6]  qualifiers
│ │ +  [ 3a1e1]  notice_section
│ │ +  [ 3a1f0]  digitalSignature
│ │ +  [ 3a201]  Privilege Withdrawn
│ │ +  [ 3a215]  AA Compromise
│ │ +  [ 3a223]  gnames_from_sectname
│ │ +  [ 3a238]  crypto/ocsp/v3_ocsp.c
│ │ +  [ 3a24e]  Autonomous System Numbers
│ │ +  [ 3a268]  OSSL_ISSUER_SERIAL
│ │ +  [ 3a27b]  otherObjectTypeID
│ │ +  [ 3a28e]  %*sSignature Value: 
│ │ +  [ 3a2a3]  signToolCert
│ │ +  [ 3a2b0]  ADMISSION_SYNTAX
│ │ +  [ 3a2c1]  authority
│ │ +  [ 3a2cb]  ocsphelper
│ │ +  [ 3a2d6]  RID
│ │ +  [ 3a2da]  dirName
│ │ +  [ 3a2e2]  s2i_ASN1_UTF8STRING
│ │ +  [ 3a2f6]  error converting zone
│ │ +  [ 3a30c]  invalid numbers
│ │ +  [ 3a31c]  policy path length already defined
│ │ +  [ 3a33f]  policy when proxy language requires no policy
│ │ +  [ 3a36d]  crl verify failure
│ │ +  [ 3a380]  unknown certificate verification error
│ │ +  [ 3a3a7]  ossl_policy_level_add_node
│ │ +  [ 3a3c2]  revoked
│ │ +  [ 3a3ca]  critical
│ │ +  [ 3a3d3]  cert_info
│ │ +  [ 3a3dd]  provider=base,fips=yes,output=pem,structure=dhx
│ │ +  [ 3a40d]  SHA2-512:SHA-512:SHA512:2.16.840.1.101.3.4.2.3
│ │ +  [ 3a43c]  SHA3-224:2.16.840.1.101.3.4.2.7
│ │ +  [ 3a45c]  KECCAK-224
│ │ +  [ 3a467]  RSA-RIPEMD160:ripemd160WithRSA:1.3.36.3.3.1.2
│ │ +  [ 3a495]  ECDSA-SHA2-224:ECDSA-SHA224:ecdsa-with-SHA224:1.2.840.10045.4.3.1
│ │ +  [ 3a4d7]  ECDSA-SHA3-512:ecdsa_with_SHA3-512:id-ecdsa-with-sha3-512:2.16.840.1.101.3.4.3.12
│ │ +  [ 3a529]  provider=default,fips=yes,output=text
│ │ +  [ 3a54f]  provider=default,fips=yes,output=der,structure=X9.42
│ │ +  [ 3a584]  AES-192-OFB:2.16.840.1.101.3.4.1.23
│ │ +  [ 3a5a8]  AES-192-WRAP-INV:AES192-WRAP-INV
│ │ +  [ 3a5c9]  null_get_ctx_params
│ │ +  [ 3a5dd]  sm4_xts_set_ctx_params
│ │ +  [ 3a5f4]  epki2pki_decode
│ │ +  [ 3a604]  providers/implementations/encode_decode/encode_key2any.c
│ │ +  [ 3a63d]  RSA-PSS PRIVATE KEY
│ │ +  [ 3a651]  rsapss_to_PrivateKeyInfo_pem_encode
│ │ +  [ 3a675]  prepare_dh_params
│ │ +  [ 3a687]  sm2_to_EncryptedPrivateKeyInfo_pem_encode
│ │ +  [ 3a6b1]  ED448 PRIVATE KEY
│ │ +  [ 3a6c3]  x25519_to_EncryptedPrivateKeyInfo_pem_encode
│ │ +  [ 3a6f0]  x448_to_PrivateKeyInfo_der_encode
│ │ +  [ 3a712]  x448_to_PrivateKeyInfo_pem_encode
│ │ +  [ 3a734]  ec2blob_encode
│ │ +  [ 3a743]  P:   
│ │ +  [ 3a749]  ecx_set_peer
│ │ +  [ 3a756]  cannot allocate required memory
│ │ +  [ 3a776]  providers/implementations/kdfs/hmacdrbg_kdf.c
│ │ +  [ 3a7a4]  partyv-info
│ │ +  [ 3a7b0]  supp-privinfo
│ │ +  [ 3a7be]  ec_gen_set_group
│ │ +  [ 3a7cf]  common_get_params
│ │ +  [ 3a7e1]  cmac_set_ctx_params
│ │ +  [ 3a7f5]  providers/implementations/macs/kmac_prov.c
│ │ +  [ 3a820]  kmac_set_ctx_params
│ │ +  [ 3a834]  ossl_drbg_enable_locking
│ │ +  [ 3a84d]  strength
│ │ +  [ 3a856]  is %zu, should be at least %zu
│ │ +  [ 3a875]  rsa_pss_compute_saltlen
│ │ +  [ 3a88d]  ems not enabled
│ │ +  [ 3a89d]  failed to generate key
│ │ +  [ 3a8b4]  invalid constant length
│ │ +  [ 3a8cc]  invalid eddsa instance for attempted operation
│ │ +  [ 3a8fb]  not xof or invalid length
│ │ +  [ 3a915]  gcm_tls_cipher
│ │ +  [ 3a924]  tant
│ │ +  [ 3a929]  kem-ikm
│ │ +  [ 3a931]  evel
│ │ +  [ 3a936]  erslen
│ │ +  [ 3a93d]  uffer_len
│ │ +  [ 3a947]  binfo
│ │ +  [ 3a94d]  egotiated-version
│ │ +  [ 3a95f]  s3
│ │ +  [ 3a962]  s8
│ │ +  [ 3a965]  d18
│ │ +  [ 3a969]  d21
│ │ +  [ 3a96d]  d24
│ │ +  [ 3a971]  _Unwind_GetDataRelBase
│ │ +  [ 3a988]  client finished
│ │ +  [ 3a998]  AES256-SHA
│ │ +  [ 3a9a3]  TLS_PSK_DHE_WITH_AES_128_CCM_8
│ │ +  [ 3a9c2]  ECDHE-ECDSA-AES128-CCM
│ │ +  [ 3a9d9]  TLS_PSK_WITH_AES_256_CBC_SHA
│ │ +  [ 3a9f6]  TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256
│ │ +  [ 3aa1c]  ADH-CAMELLIA128-SHA256
│ │ +  [ 3aa33]  TLS_DHE_DSS_WITH_CAMELLIA_128_CBC_SHA
│ │ +  [ 3aa59]  TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
│ │ +  [ 3aa7f]  PSK-ARIA128-GCM-SHA256
│ │ +  [ 3aa96]  GOST12
│ │ +  [ 3aa9d]  SHA384
│ │ +  [ 3aaa4]  AES256
│ │ +  [ 3aaab]  bn lib
│ │ +  [ 3aab2]  digest check failed
│ │ +  [ 3aac6]  exceeds max fragment size
│ │ +  [ 3aae0]  failed to get parameter
│ │ +  [ 3aaf8]  invalid compression algorithm
│ │ +  [ 3ab16]  no suitable digest algorithm
│ │ +  [ 3ab33]  no suitable key share
│ │ +  [ 3ab49]  error with the srp params
│ │ +  [ 3ab63]  ssl/tls alert bad record mac
│ │ +  [ 3ab80]  ssl command section not found
│ │ +  [ 3ab9e]  tlsv1 alert unknown psk identity
│ │ +  [ 3abbf]  too many key updates
│ │ +  [ 3abd4]  unexpected eof while reading
│ │ +  [ 3abf1]  unsupported config value class
│ │ +  [ 3ac10]  unsupported elliptic curve
│ │ +  [ 3ac2b]  x509 verification setup problems
│ │ +  [ 3ac4c]  SSL_clear
│ │ +  [ 3ac56]  client_sigalgs
│ │ +  [ 3ac65]  CANames
│ │ +  [ 3ac6d]  tls-sigalg-hash-name
│ │ +  [ 3ac82]  ecdsa_secp384r1_sha384
│ │ +  [ 3ac99]  ecdsa_sha1
│ │ +  [ 3aca4]  network BIO I/O error
│ │ +  [ 3acba]  )
│ │ +  [ 3acbc]  ch_on_handshake_yield_secret
│ │ +  [ 3acd9]  PREFERRED_ADDR may not be sent by a client
│ │ +  [ 3ad04]  type
│ │ +  [ 3ad09]  connection_id_limit_error
│ │ +  [ 3ad23]  1RTT
│ │ +  [ 3ad28]  scid
│ │ +  [ 3ad2d]  explicit_length
│ │ +  [ 3ad3d]  ossl_qrl_enc_level_set_key_cooldown_done
│ │ +  [ 3ad66]  tls_construct_ctos_ec_pt_formats
│ │ +  [ 3ad87]  tls_construct_ctos_ems
│ │ +  [ 3ad9e]  tls_parse_stoc_cookie
│ │ +  [ 3adb4]  tls_parse_stoc_early_data
│ │ +  [ 3adce]  tls_construct_finished
│ │ +  [ 3ade5]  tls_process_cke_srp
│ │ +  [ 3adf9]   + 
│ │ +  [ 3adfd]  minsize=%ld
│ │ +  [ 3ae09]  BIT STRING
│ │ +  [ 3ae14]  GRAPHICSTRING
│ │ +  [ 3ae22]  ASN1_item_unpack_ex
│ │ +  [ 3ae36]  %*s%04x - 
│ │ +  [ 3ae41]  crypto/bio/bio_print.c
│ │ +  [ 3ae58]  crypto/bn/bn_div.c
│ │ +  [ 3ae6b]  %*s%s OF %s {\n
│ │ +  [ 3ae7a]  dollarid
│ │ +  [ 3ae83]  openssl.cnf
│ │ +  [ 3ae8f]  path
│ │ +  [ 3ae94]  crypto/ct/ct_sct_ctx.c
│ │ +  [ 3aeab]  dh_priv_encode
│ │ +  [ 3aeba]  dh_pkey_import_from_type
│ │ +  [ 3aed3]  dsa_priv_encode
│ │ +  [ 3aee3]  dsa_pkey_import_from
│ │ +  [ 3aef8]  dsa_sign_setup
│ │ +  [ 3af07]  %s.so
│ │ +  [ 3af0d]  EC_GROUP_get_ecpkparameters
│ │ +  [ 3af29]  crypto/ec/ec_check.c
│ │ +  [ 3af3e]  X9.62 curve over a 359 bit binary field
│ │ +  [ 3af66]  ossl_ec_wNAF_mul
│ │ +  [ 3af77]  crypto/ec/ec_oct.c
│ │ +  [ 3af8a]  Generator (uncompressed):
│ │ +  [ 3afa4]  ossl_ec_GFp_simple_point_get_affine_coordinates
│ │ +  [ 3afd4]  ossl_ecx_public_from_private
│ │ +  [ 3aff1]  OSSL_DECODER_CTX_set_cleanup
│ │ +  [ 3b00e]  PKEY
│ │ +  [ 3b013]  Provider routines
│ │ +  [ 3b025]  PEM lib
│ │ +  [ 3b02d]  passed invalid argument
│ │ +  [ 3b045]  sect409k1
│ │ +  [ 3b04f]  wap-wsg-idm-ecid-wtls4
│ │ +  [ 3b066]  wap-wsg-idm-ecid-wtls8
│ │ +  [ 3b07d]  wap-wsg-idm-ecid-wtls10
│ │ +  [ 3b095]  brainpoolP256r1
│ │ +  [ 3b0a5]  brainpoolP320t1
│ │ +  [ 3b0b5]  P-521
│ │ +  [ 3b0bb]  default_properties
│ │ +  [ 3b0ce]  EVP_EncryptFinal_ex
│ │ +  [ 3b0e2]  EVP_CIPHER_CTX_set_key_length
│ │ +  [ 3b100]  assertion failed: niv >= 0 && niv <= EVP_MAX_IV_LENGTH
│ │ +  [ 3b137]  tls-multi
│ │ +  [ 3b141]  TYPE=%s
│ │ +  [ 3b149]  crypto/asn1/p5_scrypt.c
│ │ +  [ 3b161]  OSSL_ENCODER_get0_provider
│ │ +  [ 3b17c]  OSSL_ENCODER_CTX_set_selection
│ │ +  [ 3b19b]  EVP_PKEY_derive_set_peer_ex
│ │ +  [ 3b1b7]  EVP_PKEY_get_security_bits
│ │ +  [ 3b1d2]  evp_pkey_get0_ECX_KEY
│ │ +  [ 3b1e8]  [action:%d, state:%d] unknown OSSL_PARAM data type %d
│ │ +  [ 3b21e]  [action:%d, state:%d] unsupported OSSL_PARAM data type %d
│ │ +  [ 3b258]  dh_paramgen_subprime_len
│ │ +  [ 3b271]  EVP_SignFinal_ex
│ │ +  [ 3b282]  potential
│ │ +  [ 3b28c]  EVP_PKEY_CTX_get_signature_md
│ │ +  [ 3b2aa]  evp_pkey_signature_init
│ │ +  [ 3b2c2]  platform: linux-armv4
│ │ +  [ 3b2d8]  input not reduced
│ │ +  [ 3b2ea]  invalid secret
│ │ +  [ 3b2f9]  kdf parameter error
│ │ +  [ 3b30d]  bad key length
│ │ +  [ 3b31c]  error setting cipher params
│ │ +  [ 3b338]  illegal null value
│ │ +  [ 3b34b]  invalid number
│ │ +  [ 3b35a]  missing second number
│ │ +  [ 3b370]  mstring not universal
│ │ +  [ 3b386]  wrong integer type
│ │ +  [ 3b399]  no section
│ │ +  [ 3b3a4]  invalid ossl param type
│ │ +  [ 3b3bc]  provider already exists
│ │ +  [ 3b3d4]  command takes input
│ │ +  [ 3b3e8]  operation unsupported
│ │ +  [ 3b3fe]  recipient error
│ │ +  [ 3b40e]  bad pbm iterationcount
│ │ +  [ 3b425]  invalid keyspec
│ │ +  [ 3b435]  DES3
│ │ +  [ 3b43a]  aria128
│ │ +  [ 3b442]  rc2_magic_to_meth
│ │ +  [ 3b454]  ossl_pw_set_ui_method
│ │ +  [ 3b46a]  OBJ_nid2obj
│ │ +  [ 3b476]  idea-cfb
│ │ +  [ 3b47f]  des-ede-ofb
│ │ +  [ 3b48b]  nsSslServerName
│ │ +  [ 3b49b]  Netscape SSL Server Name
│ │ +  [ 3b4b4]  serverAuth
│ │ +  [ 3b4bf]  msCodeCom
│ │ +  [ 3b4c9]  x509Certificate
│ │ +  [ 3b4d9]  Policy Qualifier CPS
│ │ +  [ 3b4ee]  pbeWithMD2AndRC2-CBC
│ │ +  [ 3b503]  OCSP
│ │ +  [ 3b508]  member-body
│ │ +  [ 3b514]  SMIME
│ │ +  [ 3b51a]  id-smime-mod-ets-eSignature-88
│ │ +  [ 3b539]  id-cmc
│ │ +  [ 3b540]  id-pkix1-explicit-88
│ │ +  [ 3b555]  id-regCtrl-protocolEncrKey
│ │ +  [ 3b570]  id-cmc-lraPOPWitness
│ │ +  [ 3b585]  ad_timestamping
│ │ +  [ 3b595]  iana
│ │ +  [ 3b59a]  Directory
│ │ +  [ 3b5a4]  Mail
│ │ +  [ 3b5a9]  RSA-MD4
│ │ +  [ 3b5b1]  ac-proxying
│ │ +  [ 3b5bd]  holdInstructionCode
│ │ +  [ 3b5d1]  mXRecord
│ │ +  [ 3b5da]  set-ctype
│ │ +  [ 3b5e4]  setct-CredRevResData
│ │ +  [ 3b5f9]  setCext-hashedRoot
│ │ +  [ 3b60c]  setAttr-IssCap-CVM
│ │ +  [ 3b61f]  set-brand-Visa
│ │ +  [ 3b62e]  des-cfb8
│ │ +  [ 3b637]  sha256WithRSAEncryption
│ │ +  [ 3b64f]  dsa_with_SHA256
│ │ +  [ 3b65f]  whirlpool
│ │ +  [ 3b669]  id-GostR3410-2001-CryptoPro-C-ParamSet
│ │ +  [ 3b690]  GOST R 34.11-94 with GOST R 34.10-94 Cryptocom
│ │ +  [ 3b6bf]  GOST R 34.11-94 with GOST R 34.10-2001 Cryptocom
│ │ +  [ 3b6f0]  Microsoft Local Key set
│ │ +  [ 3b708]  physicalDeliveryOfficeName
│ │ +  [ 3b723]  id-camellia256-wrap
│ │ +  [ 3b737]  Any Extended Key Usage
│ │ +  [ 3b74e]  CAMELLIA-128-CMAC
│ │ +  [ 3b760]  Send Owner
│ │ +  [ 3b76b]  KxRSA_PSK
│ │ +  [ 3b775]  aria-192-cfb8
│ │ +  [ 3b783]  id-dsa-with-sha512
│ │ +  [ 3b796]  ARIA-128-GCM
│ │ +  [ 3b7a3]  CMC Registration Authority
│ │ +  [ 3b7be]  sm4-ctr
│ │ +  [ 3b7c6]  ISO-CN
│ │ +  [ 3b7cd]  RSA-SHA512/224
│ │ +  [ 3b7dc]  id-tc26-gost-3410-2012-256-paramSetC
│ │ +  [ 3b801]  BLAKE2SMAC
│ │ +  [ 3b80c]  X942KDF
│ │ +  [ 3b814]  id-on-SmtpUTF8Mailbox
│ │ +  [ 3b82a]  Class of Signing Tool KA1
│ │ +  [ 3b844]  RPKI Manifest
│ │ +  [ 3b852]  X509v3 Basic Attribute Certificate Constraints
│ │ +  [ 3b881]  acceptablePrivPolicies
│ │ +  [ 3b898]  unknown object name
│ │ +  [ 3b8ac]  expecting private key blob
│ │ +  [ 3b8c7]  PKCS12_SAFEBAGS
│ │ +  [ 3b8d7]  dinfo
│ │ +  [ 3b8dd]  PKCS12KDF
│ │ +  [ 3b8e7]  PKCS8_encrypt_ex
│ │ +  [ 3b8f8]  invalid null pkcs12 pointer
│ │ +  [ 3b914]  signing ctrl failure
│ │ +  [ 3b929]  signing not supported for this key type
│ │ +  [ 3b951]  fips
│ │ +  [ 3b956]  Mask Algorithm: 
│ │ +  [ 3b967]  %s Salt Length: 0x
│ │ +  [ 3b97a]  RSA factors/exponents are too big for for n-modulus\n
│ │ +  [ 3b9af]  rsa_new_intern
│ │ +  [ 3b9be]  ossl_rsa_padding_add_PKCS1_OAEP_mgf1_ex
│ │ +  [ 3b9e6]  RSA_padding_check_PKCS1_type_1
│ │ +  [ 3ba05]  %s:
│ │ +  [ 3ba09]  crypto/ui/ui_util.c
│ │ +  [ 3ba1d]  crypto/asn1/x_pkey.c
│ │ +  [ 3ba32]  crypto/x509/v3_conf.c
│ │ +  [ 3ba48]  d.rfc822Name
│ │ +  [ 3ba55]  d.uniformResourceIdentifier
│ │ +  [ 3ba71]  s2i_ASN1_IA5STRING
│ │ +  [ 3ba84]  DIST_POINT
│ │ +  [ 3ba8f]  ADMISSIONS
│ │ +  [ 3ba9a]  registrationNumber
│ │ +  [ 3baad]  crypto/x509/v3_ind_iss.c
│ │ +  [ 3bac6]  sslserver
│ │ +  [ 3bad0]  v2i_subject_alt
│ │ +  [ 3bae1]  %*sZone: %s, User: 
│ │ +  [ 3baf5]  duplicate attribute
│ │ +  [ 3bb09]  public key decode error
│ │ +  [ 3bb21]  Object Signer
│ │ +  [ 3bb2f]  certificate signature failure
│ │ +  [ 3bb4d]  subject issuer mismatch
│ │ +  [ 3bb65]  Empty Subject Alternative Name extension
│ │ +  [ 3bb8e]  X509_self_signed
│ │ +  [ 3bb9f]  X509_STORE_CTX_set_default
│ │ +  [ 3bbba]  crypto/x509/pcy_cache.c
│ │ +  [ 3bbd2]  socket accept failed
│ │ +  [ 3bbe7]  ALG_PERR: %s(%d): io_getevents failed : 
│ │ +  [ 3bc10]  provider=base,fips=yes,output=pem,structure=type-specific
│ │ +  [ 3bc4a]  provider=base,fips=yes,output=der,structure=dsa
│ │ +  [ 3bc7a]  provider=base,fips=yes,output=der,structure=pkcs1
│ │ +  [ 3bcac]  provider=base,fips=no,input=der,structure=PrivateKeyInfo
│ │ +  [ 3bce5]  OpenSSL Default Provider
│ │ +  [ 3bcfe]  OpenSSL X448 implementation
│ │ +  [ 3bd1a]  RSA-SHA2-384:RSA-SHA384:sha384WithRSAEncryption:1.2.840.113549.1.1.12
│ │ +  [ 3bd60]  provider=default,fips=yes,output=blob
│ │ +  [ 3bd86]  AES-192-ECB:2.16.840.1.101.3.4.1.21
│ │ +  [ 3bdaa]  providers/implementations/ciphers/cipher_aes_cts.inc
│ │ +  [ 3bddf]  providers/implementations/ciphers/cipher_tdes_wrap.c
│ │ +  [ 3be14]  rsa_to_PrivateKeyInfo_der_encode
│ │ +  [ 3be35]  dh_to_DH_pem_encode
│ │ +  [ 3be49]  providers/implementations/kdfs/hkdf.c
│ │ +  [ 3be6f]  feedback
│ │ +  [ 3be78]  providers/implementations/kdfs/pkcs12kdf.c
│ │ +  [ 3bea3]  kdf_pkcs12_derive
│ │ +  [ 3beb5]  acvp-info
│ │ +  [ 3bebf]  generate_ecdhkm
│ │ +  [ 3becf]  eae_prk
│ │ +  [ 3bed7]  ossl_drbg_get_seed
│ │ +  [ 3beea]  ossl_prov_drbg_instantiate
│ │ +  [ 3bf05]  test_nonce
│ │ +  [ 3bf10]  input=PVK
│ │ +  [ 3bf1a]  bad tls client version
│ │ +  [ 3bf31]  fips module entering error state
│ │ +  [ 3bf52]  ossl_cipher_trailingdata
│ │ +  [ 3bf6b]  providers/implementations/ciphers/ciphercommon_ccm.c
│ │ +  [ 3bfa0]  d-pub-key
│ │ +  [ 3bfaa]  rly_data
│ │ +  [ 3bfb3]  gth
│ │ +  [ 3bfb7]  fy-message
│ │ +  [ 3bfc2]  Type matching not implemented
│ │ +  [ 3bfe0]  s14
│ │ +  [ 3bfe4]  s15
│ │ +  [ 3bfe8]  d15
│ │ +  [ 3bfec]  d28
│ │ +  [ 3bff0]  ssl3_ctrl
│ │ +  [ 3bffa]  TLS_RSA_WITH_AES_256_CBC_SHA
│ │ +  [ 3c017]  TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
│ │ +  [ 3c03b]  DHE-DSS-AES256-GCM-SHA384
│ │ +  [ 3c055]  AECDH-AES256-SHA
│ │ +  [ 3c066]  TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
│ │ +  [ 3c08c]  PSK-NULL-SHA384
│ │ +  [ 3c09c]  RSA-PSK-AES128-CBC-SHA256
│ │ +  [ 3c0b6]  RSA-PSK-NULL-SHA384
│ │ +  [ 3c0ca]  TLS_ECDHE_PSK_WITH_NULL_SHA384
│ │ +  [ 3c0e9]  TLS_PSK_WITH_CHACHA20_POLY1305_SHA256
│ │ +  [ 3c10f]  TLS_DHE_DSS_WITH_CAMELLIA_256_CBC_SHA256
│ │ +  [ 3c138]  tlsext_tick
│ │ +  [ 3c144]  SHA1
│ │ +  [ 3c149]  aGOST12
│ │ +  [ 3c151]  EDH
│ │ +  [ 3c155]  SHA
│ │ +  [ 3c159]  bad cipher
│ │ +  [ 3c164]  bad srtp mki value
│ │ +  [ 3c177]  ca key too small
│ │ +  [ 3c188]  invalid alert
│ │ +  [ 3c196]  legacy sigalg disallowed or unsupported
│ │ +  [ 3c1be]  missing fatal
│ │ +  [ 3c1cc]  ocsp callback failure
│ │ +  [ 3c1e2]  quic handshake layer error
│ │ +  [ 3c1fd]  quic protocol error
│ │ +  [ 3c211]  ssl3 ext invalid max fragment length
│ │ +  [ 3c236]  ssl session id conflict
│ │ +  [ 3c24e]  ssl_undefined_void_function
│ │ +  [ 3c26a]  SSL_set_ct_validation_callback
│ │ +  [ 3c289]  add_provider_sigalgs
│ │ +  [ 3c29e]  quic_read_again
│ │ +  [ 3c2ae]  unable to store stateless reset token
│ │ +  [ 3c2d4]  port_v6
│ │ +  [ 3c2dc]  crypto_error_0x%03llx
│ │ +  [ 3c2f2]  closed
│ │ +  [ 3c2f9]  retire_connection_id
│ │ +  [ 3c30e]  stream_data_blocked
│ │ +  [ 3c322]  MAX_STREAMS valid only in 0/1-RTT
│ │ +  [ 3c344]  depack_do_frame_max_streams
│ │ +  [ 3c360]  hdr_generate_mask
│ │ +  [ 3c372]  ossl_set_tls_provider_parameters
│ │ +  [ 3c393]  tls_get_more_records
│ │ +  [ 3c3a8]  tls13_add_record_padding
│ │ +  [ 3c3c1]  PUT 
│ │ +  [ 3c3c6]  CONNE
│ │ +  [ 3c3cc]  tls_psk_do_binder
│ │ +  [ 3c3de]  tls_construct_ctos_server_cert_type
│ │ +  [ 3c402]  tls_construct_stoc_maxfragmentlen
│ │ +  [ 3c424]  tls_client_key_exchange_post_work
│ │ +  [ 3c446]  tls_post_process_server_rpk
│ │ +  [ 3c462]  tls_construct_cke_srp
│ │ +  [ 3c478]  tls_construct_server_hello
│ │ +  [ 3c493]  asn1_string_get_int64
│ │ +  [ 3c4a9]  crypto/asn1/asn1_lib.c
│ │ +  [ 3c4c0]  length is greater than %ld\n
│ │ +  [ 3c4dc]  ASN1_item_unpack
│ │ +  [ 3c4ed]  attributes
│ │ +  [ 3c4f8]  BIO_callback_ctrl
│ │ +  [ 3c50a]  keylength
│ │ +  [ 3c514]  process_include
│ │ +  [ 3c524]  Char=%c
│ │ +  [ 3c52c]  i2o_SCT
│ │ +  [ 3c534]  dh_pkey_public_check
│ │ +  [ 3c549]  priv
│ │ +  [ 3c54e]  dh_builtin_genparams
│ │ +  [ 3c563]  DSO_free
│ │ +  [ 3c56c]  crypto/dso/dso_dlfcn.c
│ │ +  [ 3c583]  dlfcn_merger
│ │ +  [ 3c590]  i2o_ECPublicKey
│ │ +  [ 3c5a0]  p.onBasis
│ │ +  [ 3c5aa]  p.char_two
│ │ +  [ 3c5b5]  X9.62 curve over a 272 bit binary field
│ │ +  [ 3c5dd]  ossl_ec_GF2m_simple_point_get_affine_coordinates
│ │ +  [ 3c60e]  ossl_ec_group_new_ex
│ │ +  [ 3c623]  crypto/ec/ec2_oct.c
│ │ +  [ 3c637]  ossl_ec_GFp_mont_field_sqr
│ │ +  [ 3c652]  validate_ecx_derive
│ │ +  [ 3c666]  the mandatory 'input' property is missing for decoder %s (properties: %s)
│ │ +  [ 3c6b0]  crypto/encode_decode/decoder_pkey.c
│ │ +  [ 3c6d4]  ossl_decoder_ctx_for_pkey_dup
│ │ +  [ 3c6f2]  ENGINE_init
│ │ +  [ 3c6fe]  passed a null parameter
│ │ +  [ 3c716]  micalg
│ │ +  [ 3c71d]  wap-wsg-idm-ecid-wtls3
│ │ +  [ 3c734]  assertion failed: j <= sizeof(c->iv)
│ │ +  [ 3c759]  encoder_process
│ │ +  [ 3c769]  crypto/asn1/p5_pbe.c
│ │ +  [ 3c77e]  EVP_PKEY_set_type_by_keymgmt
│ │ +  [ 3c79b]  rsa_pss_keygen_saltlen
│ │ +  [ 3c7b2]  qx
│ │ +  [ 3c7b5]  rsa-factor3
│ │ +  [ 3c7c1]  pcounter
│ │ +  [ 3c7ca]  OSSL_WINCTX: Undefined
│ │ +  [ 3c7e1]  HMAC-DRBG-KDF
│ │ +  [ 3c7ef]  crypto/indicator_core.c
│ │ +  [ 3c807]  not a square
│ │ +  [ 3c814]  copy error
│ │ +  [ 3c81f]  pbkdf2 error
│ │ +  [ 3c82c]  unknown max size
│ │ +  [ 3c83d]  seed_len is less than the length of q
│ │ +  [ 3c863]  bad object header
│ │ +  [ 3c875]  no multipart body failure
│ │ +  [ 3c88f]  no space for terminating null
│ │ +  [ 3c8ad]  odd number of digits
│ │ +  [ 3c8c2]  cannot invert
│ │ +  [ 3c8d0]  invalid compression bit
│ │ +  [ 3c8e8]  invalid field
│ │ +  [ 3c8f6]  could not load the shared library
│ │ +  [ 3c918]  set filename failed
│ │ +  [ 3c92c]  could not unload the shared library
│ │ +  [ 3c950]  finish failed
│ │ +  [ 3c95e]  signfinal error
│ │ +  [ 3c96e]  unknown digest algorithm
│ │ +  [ 3c987]  unwrap error
│ │ +  [ 3c994]  crmferror
│ │ +  [ 3c99e]  error creating pollrep
│ │ +  [ 3c9b5]  error creating rp
│ │ +  [ 3c9c7]  id-aes192-wrap
│ │ +  [ 3c9d6]  Software engine support
│ │ +  [ 3c9ee]  bind_engine
│ │ +  [ 3c9fa]  activate
│ │ +  [ 3ca03]  rsaEncryption
│ │ +  [ 3ca11]  commonName
│ │ +  [ 3ca1c]  des-cbc
│ │ +  [ 3ca24]  idea-cbc
│ │ +  [ 3ca2d]  nsRevocationUrl
│ │ +  [ 3ca3d]  issuerAltName
│ │ +  [ 3ca4b]  X509v3 Authority Key Identifier
│ │ +  [ 3ca6b]  mdc2WithRSA
│ │ +  [ 3ca77]  TLS Web Server Authentication
│ │ +  [ 3ca95]  Netscape Server Gated Crypto
│ │ +  [ 3cab2]  PBES2
│ │ +  [ 3cab8]  authorityInfoAccess
│ │ +  [ 3cacc]  id-smime-cti
│ │ +  [ 3cad9]  id-smime-aa-ets-RevocationRefs
│ │ +  [ 3caf8]  MD4
│ │ +  [ 3cafc]  id-aca
│ │ +  [ 3cb03]  id-mod-kea-profile-93
│ │ +  [ 3cb19]  id-cct-crs
│ │ +  [ 3cb24]  IANA
│ │ +  [ 3cb29]  pilotGroups
│ │ +  [ 3cb35]  pilotObject
│ │ +  [ 3cb41]  janetMailbox
│ │ +  [ 3cb4e]  setct-HODInput
│ │ +  [ 3cb5d]  setct-PResData
│ │ +  [ 3cb6c]  setct-CapTokenTBE
│ │ +  [ 3cb7e]  setct-CredResTBE
│ │ +  [ 3cb8f]  setCext-setQualf
│ │ +  [ 3cba0]  X509v3 Any Policy
│ │ +  [ 3cbb2]  camellia-192-cbc
│ │ +  [ 3cbc3]  camellia-256-cbc
│ │ +  [ 3cbd4]  certificateIssuer
│ │ +  [ 3cbe6]  hmac-md5
│ │ +  [ 3cbef]  ecdsa-with-Recommended
│ │ +  [ 3cc06]  hmacWithMD5
│ │ +  [ 3cc12]  id-GostR3410-94-CryptoPro-A-ParamSet
│ │ +  [ 3cc37]  crossCertificatePair
│ │ +  [ 3cc4c]  uniqueMember
│ │ +  [ 3cc59]  aes-128-xts
│ │ +  [ 3cc65]  dhpublicnumber
│ │ +  [ 3cc74]  AES-128-CBC-HMAC-SHA256
│ │ +  [ 3cc8c]  jurisdictionC
│ │ +  [ 3cc9a]  CAMELLIA-256-GCM
│ │ +  [ 3ccab]  ipsecIKE
│ │ +  [ 3ccb4]  AuthNULL
│ │ +  [ 3ccbd]  aria-128-ofb
│ │ +  [ 3ccca]  aria-192-cfb
│ │ +  [ 3ccd7]  aria-128-cfb1
│ │ +  [ 3cce5]  sha3-224
│ │ +  [ 3ccee]  sha3-512
│ │ +  [ 3ccf7]  id-hmacWithSHA3-224
│ │ +  [ 3cd0b]  dsa_with_SHA512
│ │ +  [ 3cd1b]  id-dsa-with-sha3-256
│ │ +  [ 3cd30]  kuznyechik-kexp15
│ │ +  [ 3cd42]  ipAddr-asNumberv2
│ │ +  [ 3cd54]  etsi
│ │ +  [ 3cd59]  Microsoft NTDS CA Extension
│ │ +  [ 3cd75]  X509v3 Delegated Name Constraints
│ │ +  [ 3cd97]  aAissuingDistributionPoint
│ │ +  [ 3cdb2]  X509v3 Authorization Validation
│ │ +  [ 3cdd2]  oid exists
│ │ +  [ 3cddd]  digest err
│ │ +  [ 3cde8]  request not signed
│ │ +  [ 3cdfb]  root ca not trusted
│ │ +  [ 3ce0f]  status not yet valid
│ │ +  [ 3ce24]  expecting public key blob
│ │ +  [ 3ce3e]  keyblob header parse error
│ │ +  [ 3ce59]  PEM_do_header
│ │ +  [ 3ce67]  PKCS12_BAGS
│ │ +  [ 3ce73]  crypto/pkcs12/p12_crpt.c
│ │ +  [ 3ce8c]  iv gen error
│ │ +  [ 3ce99]  mac setup error
│ │ +  [ 3cea9]  PKCS7_DIGEST
│ │ +  [ 3ceb6]  d.digest
│ │ +  [ 3cebf]  crypto/pkcs7/pk7_lib.c
│ │ +  [ 3ced6]  additional input too long
│ │ +  [ 3cef0]  entropy out of range
│ │ +  [ 3cf05]  error initialising drbg
│ │ +  [ 3cf1d]  Function not implemented
│ │ +  [ 3cf36]  in error state
│ │ +  [ 3cf45]  personalisation string too long
│ │ +  [ 3cf65]  reseed error
│ │ +  [ 3cf72]  too much nonce requested
│ │ +  [ 3cf8b]  random_conf_init
│ │ +  [ 3cf9c]  block type is not 01
│ │ +  [ 3cfb1]  invalid keypair
│ │ +  [ 3cfc1]  mgf1 digest not allowed
│ │ +  [ 3cfd9]  RSA_sign_ASN1_OCTET_STRING
│ │ +  [ 3cff4]  unregistered scheme
│ │ +  [ 3d008]  OSSL_STORE_INFO_new_PKEY
│ │ +  [ 3d021]  loader_from_algorithm
│ │ +  [ 3d037]  invalid signer certificate purpose
│ │ +  [ 3d05a]  general_allocate_prompt
│ │ +  [ 3d072]  CERTIFICATEPOLICIES
│ │ +  [ 3d086]  d.cpsuri
│ │ +  [ 3d08f]  %*sCPS: %.*s
│ │ +  [ 3d09c]  type_id
│ │ +  [ 3d0a4]  d.otherName
│ │ +  [ 3d0b0]  GeneralNames
│ │ +  [ 3d0bd]  i2v_AUTHORITY_INFO_ACCESS
│ │ +  [ 3d0d7]  SSL Server
│ │ +  [ 3d0e2]  crypto/x509/v3_bcons.c
│ │ +  [ 3d0f9]  name.fullname
│ │ +  [ 3d107]  removeFromCRL
│ │ +  [ 3d115]  IPAddressRange
│ │ +  [ 3d124]  OSSL_TARGETING_INFORMATION
│ │ +  [ 3d13f]  Targets
│ │ +  [ 3d148]  %*sLog       : %s
│ │ +  [ 3d15b]  %*sSignature : 
│ │ +  [ 3d16b]  contentsOfAdmissions
│ │ +  [ 3d180]  ossl_x509v3_cache_extensions
│ │ +  [ 3d19d]  SSL server
│ │ +  [ 3d1a8]  othername: %s
│ │ +  [ 3d1b6]  othername
│ │ +  [ 3d1c0]  v2i_GENERAL_NAME_ex
│ │ +  [ 3d1d4]  crypto/x509/v3_skid.c
│ │ +  [ 3d1ea]  s2i_skey_id
│ │ +  [ 3d1f6]  invalid section
│ │ +  [ 3d206]  unable to get certificate CRL
│ │ +  [ 3d224]  X509_CRL_digest
│ │ +  [ 3d234]  provider=base,fips=yes,output=der,structure=PrivateKeyInfo
│ │ +  [ 3d26f]  provider=base,fips=no,output=der,structure=EncryptedPrivateKeyInfo
│ │ +  [ 3d2b2]  SHA2-384:SHA-384:SHA384:2.16.840.1.101.3.4.2.2
│ │ +  [ 3d2e1]  OpenSSL CMAC via EVP_PKEY implementation
│ │ +  [ 3d30a]  provider=default,fips=yes,output=der,structure=dh
│ │ +  [ 3d33c]  provider=default,fips=yes,input=der,structure=type-specific
│ │ +  [ 3d378]  AES-128-XTS:1.3.111.2.1619.0.1.1
│ │ +  [ 3d399]  ARIA-128-CCM:1.2.410.200046.1.1.37
│ │ +  [ 3d3bc]  ARIA-192-CBC:ARIA192:1.2.410.200046.1.1.7
│ │ +  [ 3d3e6]  SM4-ECB:1.2.156.10197.1.104.1
│ │ +  [ 3d404]  chacha20_set_ctx_params
│ │ +  [ 3d41c]  blake2s256_internal_final
│ │ +  [ 3d436]  providers/implementations/encode_decode/decode_msblob2key.c
│ │ +  [ 3d472]  PVKKDF
│ │ +  [ 3d479]  dh_to_type_specific_params_der_encode
│ │ +  [ 3d49f]  sm2_to_type_specific_no_pub_der_encode
│ │ +  [ 3d4c6]  J:   
│ │ +  [ 3d4cc]  ecdh_X9_63_kdf_derive
│ │ +  [ 3d4e2]  ecdh_match_params
│ │ +  [ 3d4f4]  kdf_argon2_derive
│ │ +  [ 3d506]  operation
│ │ +  [ 3d510]  ecxkem_encapsulate
│ │ +  [ 3d523]  rsasve_generate
│ │ +  [ 3d533]  rsa_gen_set_params
│ │ +  [ 3d546]  seed_src_reseed
│ │ +  [ 3d556]  providers/implementations/signature/dsa_sig.c
│ │ +  [ 3d584]  ed448_sign
│ │ +  [ 3d58f]  OAEP padding not allowed for signing / verifying
│ │ +  [ 3d5c0]  ossl_sm2_compute_z_digest
│ │ +  [ 3d5da]  missing constant
│ │ +  [ 3d5eb]  missing pass
│ │ +  [ 3d5f8]  missing type
│ │ +  [ 3d605]  ype
│ │ +  [ 3d609]  check
│ │ +  [ 3d60f]  s-randkey
│ │ +  [ 3d619]  ey-check
│ │ +  [ 3d622]  eprime-generator
│ │ +  [ 3d633]  eed
│ │ +  [ 3d637]  tls
│ │ +  [ 3d63b]  unsupported register class
│ │ +  [ 3d656]  unknown personality routine
│ │ +  [ 3d672]  s27
│ │ +  [ 3d676]  d26
│ │ +  [ 3d67a]  d27
│ │ +  [ 3d67e]  ADH-AES256-SHA
│ │ +  [ 3d68d]  TLS_DHE_RSA_WITH_AES_128_CCM
│ │ +  [ 3d6aa]  TLS_ECDH_anon_WITH_AES_128_CBC_SHA
│ │ +  [ 3d6cd]  PSK-NULL-SHA256
│ │ +  [ 3d6dd]  TLS_PSK_WITH_NULL_SHA384
│ │ +  [ 3d6f6]  ECDHE-PSK-AES256-CBC-SHA
│ │ +  [ 3d70f]  TLS_ECDHE_PSK_WITH_NULL_SHA256
│ │ +  [ 3d72e]  TLS_SRP_SHA_DSS_WITH_AES_256_CBC_SHA
│ │ +  [ 3d753]  DHE-RSA-CHACHA20-POLY1305
│ │ +  [ 3d76d]  TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
│ │ +  [ 3d78f]  TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
│ │ +  [ 3d7b8]  IANA-GOST2012-GOST8912-GOST8912
│ │ +  [ 3d7d8]  SEED-SHA
│ │ +  [ 3d7e1]  TLS_RSA_WITH_SEED_CBC_SHA
│ │ +  [ 3d7fb]  master_key
│ │ +  [ 3d806]  gost2001
│ │ +  [ 3d80f]  kGOST
│ │ +  [ 3d815]  SEED
│ │ +  [ 3d81a]  eNULL
│ │ +  [ 3d820]  EDH-DSS-DES-CBC3-SHA
│ │ +  [ 3d835]  bad certificate
│ │ +  [ 3d845]  failed to init async
│ │ +  [ 3d85a]  inconsistent early data alpn
│ │ +  [ 3d877]  inconsistent early data sni
│ │ +  [ 3d893]  missing psk kex modes extension
│ │ +  [ 3d8b3]  no change following hrr
│ │ +  [ 3d8cb]  no suitable record layer
│ │ +  [ 3d8e4]  null ssl method passed
│ │ +  [ 3d8fb]  renegotiate ext too long
│ │ +  [ 3d914]  required compression algorithm missing
│ │ +  [ 3d93b]  ssl/tls alert unsupported certificate
│ │ +  [ 3d961]  ssl section empty
│ │ +  [ 3d973]  unable to find public key parameters
│ │ +  [ 3d998]  ssl_validate_ct
│ │ +  [ 3d9a8]  ssl_do_config
│ │ +  [ 3d9b6]  groups
│ │ +  [ 3d9bd]  DTLSv1
│ │ +  [ 3d9c4]  DTLSv1.2
│ │ +  [ 3d9cd]  X448
│ │ +  [ 3d9d2]  tls-sigalg-sec-bits
│ │ +  [ 3d9e6]  dsa_sha512
│ │ +  [ 3d9f1]  failed to start assist thread
│ │ +  [ 3da0f]  expect_quic_with_stream_lock
│ │ +  [ 3da2c]  QUIC error code: 0x%llx%s%s%s (triggered by frame type: 0x%llx%s%s%s), reason: "%s"
│ │ +  [ 3da80]  ORIG_DCID was not sent but is required
│ │ +  [ 3daa7]  stateless_reset_token
│ │ +  [ 3dabd]  connection_id
│ │ +  [ 3dacb]  version negotiation failure
│ │ +  [ 3dae7]  packet_number
│ │ +  [ 3daf5]  token
│ │ +  [ 3dafb]  ect0
│ │ +  [ 3db00]  final_size
│ │ +  [ 3db0b]  depack_do_frame_max_data
│ │ +  [ 3db24]  STREAM_DATA_BLOCKED frame for TX only stream
│ │ +  [ 3db51]  ALPN must be configured when using QUIC
│ │ +  [ 3db79]  ossl_quic_gen_rand_conn_id
│ │ +  [ 3db94]  RETIRE_CONN_ID
│ │ +  [ 3dba3]  ssl/record/rec_layer_s3.c
│ │ +  [ 3dbbd]  tls_new_record_layer
│ │ +  [ 3dbd2]  tls_construct_ctos_psk
│ │ +  [ 3dbe9]  tls_parse_ctos_psk_kex_modes
│ │ +  [ 3dc06]  tls_construct_stoc_ec_pt_formats
│ │ +  [ 3dc27]  tls_construct_stoc_status_request
│ │ +  [ 3dc49]  tls_construct_next_proto
│ │ +  [ 3dc62]  ossl_statem_server_read_transition
│ │ +  [ 3dc85]  opaqueBlob
│ │ +  [ 3dc90]  ; 
│ │ +  [ 3dc93]  :
│ │ +  [ 3dc95]  BAD RECURSION DEPTH\n
│ │ +  [ 3dcaa]  asn1_check_tlen
│ │ +  [ 3dcba]  crypto/asn1/a_bitstr.c
│ │ +  [ 3dcd1]  ossl_asn1_do_adb
│ │ +  [ 3dce2]  %ju\n
│ │ +  [ 3dce7]  WSAStartup
│ │ +  [ 3dcf2]  dgram_pair_recvmmsg
│ │ +  [ 3dd06]  crypto/asn1/a_d2i_fp.c
│ │ +  [ 3dd1d]  PKCS5_pbe2_set_iv_ex
│ │ +  [ 3dd32]  .include
│ │ +  [ 3dd3b]  do_tcreate
│ │ +  [ 3dd46]  ENUM
│ │ +  [ 3dd4b]  VISIBLE
│ │ +  [ 3dd53]  parse_tagging
│ │ +  [ 3dd61]  crypto/dh/dh_key.c
│ │ +  [ 3dd74]  generate_key
│ │ +  [ 3dd81]  OpenSSL 'dlfcn' shared library method
│ │ +  [ 3dda7]  ec_key_point_format_fromdata
│ │ +  [ 3ddc4]  SECG curve over a 160 bit prime field
│ │ +  [ 3ddea]  SECG curve over a 192 bit prime field
│ │ +  [ 3de10]  WTLS curve over a 224 bit prime field
│ │ +  [ 3de36]  ossl_ec_key_simple_oct2priv
│ │ +  [ 3de52]  crypto/ec/ec_lib.c
│ │ +  [ 3de65]  EC_GROUP_set_generator
│ │ +  [ 3de7c]  EC_POINT_invert
│ │ +  [ 3de8c]  ossl_ec_GFp_simple_group_check_discriminant
│ │ +  [ 3deb8]  ENGINE_add
│ │ +  [ 3dec3]  BIO routines
│ │ +  [ 3ded0]  secp160r2
│ │ +  [ 3deda]  prime192v2
│ │ +  [ 3dee5]  prime239v1
│ │ +  [ 3def0]  sect193r1
│ │ +  [ 3defa]  crypto/evp/encode.c
│ │ +  [ 3df0e]  alg_module_init
│ │ +  [ 3df1e]  crypto/evp/evp_enc.c
│ │ +  [ 3df33]  crypto/evp/keymgmt_lib.c
│ │ +  [ 3df4c]  evp_pkey_get0_EC_KEY_int
│ │ +  [ 3df65]  md
│ │ +  [ 3df68]  x931
│ │ +  [ 3df6d]  pss
│ │ +  [ 3df71]  qy
│ │ +  [ 3df74]  rsa-coefficient2
│ │ +  [ 3df85]  ffdhe8192
│ │ +  [ 3df8f]  subgroup factor:
│ │ +  [ 3dfa0]  check pubkey invalid
│ │ +  [ 3dfb5]  keys not set
│ │ +  [ 3dfc2]  no parameters set
│ │ +  [ 3dfd4]  command not supported
│ │ +  [ 3dfea]  inaccessible domain parameters
│ │ +  [ 3e009]  missing private key
│ │ +  [ 3e01d]  explicit tag not constructed
│ │ +  [ 3e03a]  unknown message digest algorithm
│ │ +  [ 3e05b]  number too large
│ │ +  [ 3e06c]  param not integer type
│ │ +  [ 3e083]  not a NIST prime
│ │ +  [ 3e094]  dso not found
│ │ +  [ 3e0a2]  invalid url path
│ │ +  [ 3e0b3]  decrypt error
│ │ +  [ 3e0c1]  msgsigdigest error
│ │ +  [ 3e0d4]  not a signed receipt
│ │ +  [ 3e0e9]  not pwri
│ │ +  [ 3e0f2]  type not digested data
│ │ +  [ 3e109]  iterationcount below 100
│ │ +  [ 3e122]  error creating genp
│ │ +  [ 3e136]  invalid args
│ │ +  [ 3e143]  missing key input for creating protection
│ │ +  [ 3e16d]  pkistatusinfo not found
│ │ +  [ 3e185]  unknown pkistatus
│ │ +  [ 3e197]  wrong pbm value
│ │ +  [ 3e1a7]  BF
│ │ +  [ 3e1aa]  id-aes256-wrap-pad
│ │ +  [ 3e1bd]  dynamic_load
│ │ +  [ 3e1ca]  Specifies whether to load from 'DIR_ADD' directories (0=no,1=yes,2=mandatory)
│ │ +  [ 3e218]  assertion failed: WITHIN_ARENA(chunk)
│ │ +  [ 3e23e]  assertion failed: WITHIN_FREELIST(temp2->p_next) || WITHIN_ARENA(temp2->p_next)
│ │ +  [ 3e28e]  crypto/o_str.c
│ │ +  [ 3e29d]  crypto/param_build_set.c
│ │ +  [ 3e2b6]  OSSL_PARAM_set_int32
│ │ +  [ 3e2cb]  general_get_int
│ │ +  [ 3e2db]  No password method specified
│ │ +  [ 3e2f8]  calling gettimeofday()
│ │ +  [ 3e30f]  md5
│ │ +  [ 3e313]  PBE-MD2-DES
│ │ +  [ 3e31f]  rsa
│ │ +  [ 3e323]  pkcs7-data
│ │ +  [ 3e32e]  DES-EDE-CBC
│ │ +  [ 3e33a]  des-ede3-cfb
│ │ +  [ 3e347]  subjectKeyIdentifier
│ │ +  [ 3e35c]  CAST5-OFB
│ │ +  [ 3e366]  id-kp
│ │ +  [ 3e36c]  pbeWithSHA1And2-KeyTripleDES-CBC
│ │ +  [ 3e38d]  id-qt-cps
│ │ +  [ 3e397]  id-smime-aa-contentReference
│ │ +  [ 3e3b4]  id-cmc-queryPending
│ │ +  [ 3e3c8]  id-cmc-confirmCertAcceptance
│ │ +  [ 3e3e5]  experimental
│ │ +  [ 3e3f2]  Experimental
│ │ +  [ 3e3ff]  clearance
│ │ +  [ 3e409]  md4WithRSAEncryption
│ │ +  [ 3e41e]  X509v3 Policy Constraints
│ │ +  [ 3e438]  pilotAttributeSyntax
│ │ +  [ 3e44d]  generationQualifier
│ │ +  [ 3e461]  setct-AuthRevResBaggage
│ │ +  [ 3e479]  setct-CertInqReqTBS
│ │ +  [ 3e48d]  setct-CapReqTBE
│ │ +  [ 3e49d]  setCext-setExt
│ │ +  [ 3e4ac]  des-cdmf
│ │ +  [ 3e4b5]  ITU-T
│ │ +  [ 3e4bb]  msUPN
│ │ +  [ 3e4c1]  aes-192-cfb8
│ │ +  [ 3e4ce]  sha512WithRSAEncryption
│ │ +  [ 3e4e6]  camellia-192-ecb
│ │ +  [ 3e4f7]  GOST 28147-89
│ │ +  [ 3e505]  userPassword
│ │ +  [ 3e512]  id-aes128-GCM
│ │ +  [ 3e520]  id-camellia192-wrap
│ │ +  [ 3e534]  ct_precert_scts
│ │ +  [ 3e544]  aes-128-ocb
│ │ +  [ 3e550]  id-tc26-gost-3410-2012-512-paramSetA
│ │ +  [ 3e575]  kx-dhe
│ │ +  [ 3e57c]  kx-dhe-psk
│ │ +  [ 3e587]  hmac-sha3-384
│ │ +  [ 3e595]  uacurve2
│ │ +  [ 3e59e]  kmac128
│ │ +  [ 3e5a6]  NAIRealm
│ │ +  [ 3e5af]  classSignToolKC2
│ │ +  [ 3e5c0]  authorizationValidation
│ │ +  [ 3e5d8]  id-kp-wisun-fan-device
│ │ +  [ 3e5ef]  responseStatus
│ │ +  [ 3e5fe]  no signer key
│ │ +  [ 3e60c]  read key
│ │ +  [ 3e615]  PEM_def_callback
│ │ +  [ 3e626]  DH PARAMETERS
│ │ +  [ 3e634]  crypto/pem/pem_pkey.c
│ │ +  [ 3e64a]  PKCS12_key_gen_utf8_ex
│ │ +  [ 3e661]  stack_to_property_list
│ │ +  [ 3e678]  RAND_priv_bytes_ex
│ │ +  [ 3e68b]  RAND_get0_primary
│ │ +  [ 3e69d]  ossl_rand_pool_add_begin
│ │ +  [ 3e6b6]  dmq1
│ │ +  [ 3e6bb]  invalid digest length
│ │ +  [ 3e6d1]  RSA_padding_add_none
│ │ +  [ 3e6e6]  ossl_rsa_padding_check_PKCS1_type_2_TLS
│ │ +  [ 3e70e]  pkey_rsa_ctrl
│ │ +  [ 3e71c]  file
│ │ +  [ 3e721]  PEM_X509_INFO_read_bio_ex
│ │ +  [ 3e73b]  d.dNSName
│ │ +  [ 3e745]  crypto/x509/v3_info.c
│ │ +  [ 3e75b]  v2i_ASN1_BIT_STRING
│ │ +  [ 3e76f]  sslCA
│ │ +  [ 3e775]  dataEncipherment
│ │ +  [ 3e786]  keyAgreement
│ │ +  [ 3e793]  onlysomereasons
│ │ +  [ 3e7a3]  onlyattr
│ │ +  [ 3e7ac]  %*sIssuer: 
│ │ +  [ 3e7b8]  crypto/x509/v3_addr.c
│ │ +  [ 3e7ce]  crypto/x509/v3_asid.c
│ │ +  [ 3e7e4]  %*sinherit\n
│ │ +  [ 3e7f0]  %s\n
│ │ +  [ 3e7f4]  %*sSigned Certificate Timestamp:
│ │ +  [ 3e816]  %*sVersion   : 
│ │ +  [ 3e826]  infinite
│ │ +  [ 3e82f]  Netscape SSL server
│ │ +  [ 3e843]  copy
│ │ +  [ 3e848]  Attributes
│ │ +  [ 3e853]  invalid extension string
│ │ +  [ 3e86c]  invalid policy identifier
│ │ +  [ 3e886]  invalid syntax
│ │ +  [ 3e895]  othername error
│ │ +  [ 3e8a5]  X509_NAME_oneline
│ │ +  [ 3e8b7]  invalid or inconsistent certificate policy extension
│ │ +  [ 3e8ec]  Suite B: certificate version invalid
│ │ +  [ 3e911]  crypto/x509/x509_vfy.c
│ │ +  [ 3e928]  crypto/x509/x509_vpm.c
│ │ +  [ 3e93f]  trust
│ │ +  [ 3e945]  skcipher
│ │ +  [ 3e94e]  provider=base,fips=yes,input=der,structure=PrivateKeyInfo
│ │ +  [ 3e988]  SHA3-384:2.16.840.1.101.3.4.2.9
│ │ +  [ 3e9a8]  OpenSSL DSA implementation
│ │ +  [ 3e9c3]  X448:1.3.101.111
│ │ +  [ 3e9d4]  RSA-SHA1:RSA-SHA-1:sha1WithRSAEncryption:1.2.840.113549.1.1.5
│ │ +  [ 3ea12]  ECDSA-SHA3-224:ecdsa_with_SHA3-224:id-ecdsa-with-sha3-224:2.16.840.1.101.3.4.3.9
│ │ +  [ 3ea63]  provider=default,fips=no,output=text
│ │ +  [ 3ea88]  provider=default,fips=yes,output=pem,structure=X9.62
│ │ +  [ 3eabd]  ARIA-256-OFB:1.2.410.200046.1.1.14
│ │ +  [ 3eae0]  ossl_aes_gcm_siv_init
│ │ +  [ 3eaf6]  ossl_aes_gcm_siv_get_ctx_params
│ │ +  [ 3eb16]  aes_siv_set_ctx_params
│ │ +  [ 3eb2d]  encode_dsa_params
│ │ +  [ 3eb3f]  key_to_pubkey
│ │ +  [ 3eb4d]  rsapss_to_SubjectPublicKeyInfo_der_encode
│ │ +  [ 3eb77]  dh_to_EncryptedPrivateKeyInfo_pem_encode
│ │ +  [ 3eba0]  dsa_spki_pub_to_der
│ │ +  [ 3ebb4]  X25519 PRIVATE KEY
│ │ +  [ 3ebc7]  x448_to_SubjectPublicKeyInfo_pem_encode
│ │ +  [ 3ebef]  ec_to_EC_pem_encode
│ │ +  [ 3ec03]  ec_to_text
│ │ +  [ 3ec0e]  %s Public-Key:\n
│ │ +  [ 3ec1e]  providers/implementations/exchange/ecx_exch.c
│ │ +  [ 3ec4c]  ecx_dupctx
│ │ +  [ 3ec57]  early_clean
│ │ +  [ 3ec63]  kdf_sshkdf_derive
│ │ +  [ 3ec75]  Invalid sender auth public key
│ │ +  [ 3ec94]  providers/implementations/keymgmt/dsa_kmgmt.c
│ │ +  [ 3ecc2]  ossl_drbg_hmac_init
│ │ +  [ 3ecd6]  providers/implementations/signature/eddsa_sig.c
│ │ +  [ 3ed06]  rsa_set_ctx_params
│ │ +  [ 3ed19]  cofactor required
│ │ +  [ 3ed2b]  not supported
│ │ +  [ 3ed39]  seed sources must not have a parent
│ │ +  [ 3ed5d]  unable to load sha256
│ │ +  [ 3ed73]  ossl_cipher_generic_stream_final
│ │ +  [ 3ed94]  ossl_cipher_generic_cipher
│ │ +  [ 3edaf]  ccm_init
│ │ +  [ 3edb8]  ildinfo
│ │ +  [ 3edc0]  ault-digest
│ │ +  [ 3edcc]  ep-label
│ │ +  [ 3edd5]  ation
│ │ +  [ 3eddb]  oid
│ │ +  [ 3eddf]  nterleave
│ │ +  [ 3ede9]  getRegister
│ │ +  [ 3edf5]  s17
│ │ +  [ 3edf9]  d1
│ │ +  [ 3edfc]  unknown register
│ │ +  [ 3ee0d]  ssl3_ctx_ctrl
│ │ +  [ 3ee1b]  TLS_RSA_WITH_AES_128_CBC_SHA256
│ │ +  [ 3ee3b]  TLS_DHE_RSA_WITH_AES_256_CCM_8
│ │ +  [ 3ee5a]  TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
│ │ +  [ 3ee7f]  ECDHE-RSA-AES128-SHA256
│ │ +  [ 3ee97]  TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
│ │ +  [ 3eebb]  ECDHE-PSK-NULL-SHA256
│ │ +  [ 3eed1]  SRP-DSS-AES-128-CBC-SHA
│ │ +  [ 3eee9]  CAMELLIA256-SHA
│ │ +  [ 3eef9]  TLS_GOSTR341001_WITH_NULL_GOSTR3411
│ │ +  [ 3ef1d]  DHE-RSA-SEED-SHA
│ │ +  [ 3ef2e]  ssl_version
│ │ +  [ 3ef3a]  bad key update
│ │ +  [ 3ef49]  bad length
│ │ +  [ 3ef54]  bad psk
│ │ +  [ 3ef5c]  data length too long
│ │ +  [ 3ef71]  https proxy request
│ │ +  [ 3ef85]  no private key assigned
│ │ +  [ 3ef9d]  old session cipher not returned
│ │ +  [ 3efbd]  pipeline failure
│ │ +  [ 3efce]  protocol is shutdown
│ │ +  [ 3efe3]  request pending
│ │ +  [ 3eff3]  stream count limited
│ │ +  [ 3f008]  unknown cipher type
│ │ +  [ 3f01c]  SSL_CONF_cmd
│ │ +  [ 3f029]  CipherString
│ │ +  [ 3f036]  RxCertificateCompression
│ │ +  [ 3f04f]  TLS1-PRF
│ │ +  [ 3f058]  tls1_set_groups_list
│ │ +  [ 3f06d]  tls12_check_peer_sigalg
│ │ +  [ 3f085]  tls-group-is-kem
│ │ +  [ 3f096]  ecdsa_brainpoolP256r1_sha256
│ │ +  [ 3f0b3]  dsa_sha256
│ │ +  [ 3f0be]  TLS13-KDF
│ │ +  [ 3f0c8]  MAX_UDP_PAYLOAD_SIZE appears multiple times
│ │ +  [ 3f0f4]  zero-length CID in PREFERRED_ADDR
│ │ +  [ 3f116]  transport
│ │ +  [ 3f120]  handshake alert
│ │ +  [ 3f130]  JSON-SEQ
│ │ +  [ 3f139]  QUIC
│ │ +  [ 3f13e]  system_info
│ │ +  [ 3f14a]  connection_closed
│ │ +  [ 3f15c]  \n
│ │ +  [ 3f15f]  connectivity:connection_state_updated
│ │ +  [ 3f185]  connectivity:connection_closed
│ │ +  [ 3f1a4]  attempted
│ │ +  [ 3f1ae]  key_update_error
│ │ +  [ 3f1bf]  dcid
│ │ +  [ 3f1c4]  acked_ranges
│ │ +  [ 3f1d1]  error_space
│ │ +  [ 3f1dd]  error_code_value
│ │ +  [ 3f1ee]  non-minimal frame type encoding
│ │ +  [ 3f20e]  tls-data-size
│ │ +  [ 3f21c]  tls13_post_process_record
│ │ +  [ 3f236]  final_sig_algs
│ │ +  [ 3f245]  custom_ext_parse
│ │ +  [ 3f256]  tls_parse_ctos_maxfragmentlen
│ │ +  [ 3f274]  tls_construct_stoc_use_srtp
│ │ +  [ 3f290]  tls_construct_cke_gost18
│ │ +  [ 3f2a9]  tls13_save_handshake_digest_for_pha
│ │ +  [ 3f2cd]  tls_process_next_proto
│ │ +  [ 3f2e4]  tls_process_cke_rsa
│ │ +  [ 3f2f8]   GMT
│ │ +  [ 3f2fd]  ASN1_STRING_set
│ │ +  [ 3f30d]  UTCTIME
│ │ +  [ 3f315]  <ASN1 29>
│ │ +  [ 3f31f]  asn1_d2i_ex_primitive
│ │ +  [ 3f335]  %*s
│ │ +  [ 3f339]  lookup returned nothing
│ │ +  [ 3f351]  dgram_pair_ctrl_set_write_buf_size
│ │ +  [ 3f374]  PBMAC1PARAM
│ │ +  [ 3f380]  line 
│ │ +  [ 3f386]  CONF_modules_load
│ │ +  [ 3f398]  module_load_dso
│ │ +  [ 3f3a8]  nomask
│ │ +  [ 3f3af]  BITLIST
│ │ +  [ 3f3b7]  UTF8String
│ │ +  [ 3f3c2]  section=%s
│ │ +  [ 3f3cd]  X9.42 DH
│ │ +  [ 3f3d6]  crypto/dsa/dsa_lib.c
│ │ +  [ 3f3eb]  DSO_new_method
│ │ +  [ 3f3fa]  %*spub:\n
│ │ +  [ 3f403]  i2d_ECPKParameters
│ │ +  [ 3f416]  i2d_ECPrivateKey
│ │ +  [ 3f427]  EC_POINT_set_compressed_coordinates
│ │ +  [ 3f44b]  ossl_ecdsa_deterministic_sign
│ │ +  [ 3f469]  ECDSA_do_sign_ex
│ │ +  [ 3f47a]  ossl_ec_GFp_simple_blind_coordinates
│ │ +  [ 3f49f]  PKCS7 routines
│ │ +  [ 3f4ae]  random number generator
│ │ +  [ 3f4c6]  DSO support routines
│ │ +  [ 3f4db]  crypto/evp/e_aes.c
│ │ +  [ 3f4ee]  aes_ccm_init_key
│ │ +  [ 3f4ff]  aes_wrap_init_key
│ │ +  [ 3f511]  keylen
│ │ +  [ 3f518]  tls1multi_maxbufsz
│ │ +  [ 3f52b]  EVP_CIPHER_CTX_copy
│ │ +  [ 3f53f]  ossl_asn1_type_get_octetstring_int
│ │ +  [ 3f562]  keymgmt_from_algorithm
│ │ +  [ 3f579]  EVP_DigestVerifyFinal
│ │ +  [ 3f58f]  evp_pkey_get0_DH_int
│ │ +  [ 3f5a4]  EVP_PKEY_get_params
│ │ +  [ 3f5b8]  new_raw_key_int
│ │ +  [ 3f5c8]  pkey_set_type
│ │ +  [ 3f5d6]  [action:%d, state:%d] trying to get a BIGNUM via ctrl call
│ │ +  [ 3f611]  mgf1-digest
│ │ +  [ 3f61d]  implicit-rejection
│ │ +  [ 3f630]  hexsecret
│ │ +  [ 3f63a]  X942KDF-ASN1
│ │ +  [ 3f647]  rsa-factor8
│ │ +  [ 3f653]  fips186_4
│ │ +  [ 3f65d]  pkey_ec_derive
│ │ +  [ 3f66c]  ossl_method_construct_precondition
│ │    [ 3f68f]  arg2 lt arg3
│ │    [ 3f69c]  no suitable digest
│ │    [ 3f6af]  private key too large
│ │    [ 3f6c5]  q too large
│ │    [ 3f6d1]  camellia key setup failed
│ │    [ 3f6eb]  expecting an rsa key
│ │    [ 3f700]  inaccessible key
│ ├── objdump --line-numbers --disassemble --demangle --reloc --no-show-raw-insn --section=.text {}
│ │ @@ -266302,15 +266302,15 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	1f9496 <uniffi_pbcli_checksum_method_api_base@@Base+0x8cc12>
│ │  	ldrb	r6, [r5, #1]
│ │  	add.w	r0, r1, r5
│ │  	b.n	1f901e <uniffi_pbcli_checksum_method_api_base@@Base+0x8c79a>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r1, r2, r4, r5, r7, r9, ip, sp, lr, pc}
│ │ -	vcvt.f32.u32	<illegal reg q14.5>, q10, #25
│ │ +			@ <UNDEFINED> instruction: 0xffe7de9b
│ │  	vshll.u32	q8, d19, #9
│ │  	and.w	r8, r0, r0, ror #19
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	1f9210 <uniffi_pbcli_checksum_method_api_base@@Base+0x8c98c>
│ │  	ands	r0, r0
│ │  	b.n	1f903a <uniffi_pbcli_checksum_method_api_base@@Base+0x8c7b6>
│ │  	lsls	r0, r4, #13
│ │ @@ -268424,29 +268424,29 @@
│ │  			@ <UNDEFINED> instruction: 0xffe6eaff
│ │  	lsls	r2, r3, #13
│ │  	b.n	1fa57a <uniffi_pbcli_checksum_method_api_base@@Base+0x8dcf6>
│ │  	lsls	r0, r6, #2
│ │  	b.n	1fa2a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x8da24>
│ │  			@ <UNDEFINED> instruction: 0xff92eaff
│ │  	asrs	r6, r7, #8
│ │ -	vsra.u32	q12, <illegal reg q14.5>, #24
│ │ +	vaddw.u32	q12, q12, d20
│ │  	vaddw.u32	<illegal reg q8.5>, q13, d2
│ │ -	vmla.i32	q12, q12, d1[0]
│ │ +	vmla.i32	q12, q12, d8[1]
│ │  	vmlsl.u32	<illegal reg q8.5>, d26, d14[1]
│ │ -	vrsubhn.i64	d24, q4, <illegal reg q14.5>
│ │ +	vqshlu.s32	q12, q2, #8
│ │  	vsubl.u32	<illegal reg q8.5>, d10, d18
│ │ -	vmla.f32	q12, q4, d1[1]
│ │ +	vaddw.u32	q12, q12, d8
│ │  	vsra.u64	<illegal reg q8.5>, q15, #22
│ │  	vsra.u64	d17, d30, #24
│ │ -	vshr.u64	q12, <illegal reg q14.5>, #24
│ │ +	vaddw.u32	q12, q4, d20
│ │  	vmla.f32	<illegal reg q8.5>, q5, d10[0]
│ │  	vaddw.u32	<illegal reg q8.5>, q4, d22
│ │ -	vmla.i32	q12, q4, d5[1]
│ │ +	vaddl.u32	q12, d24, d12
│ │  	vrsubhn.i64	d17, q13, q3
│ │ -	vmls.f32	q12, q12, d5[0]
│ │ +	vmls.f32	q12, q12, d12[1]
│ │  	vqshlu.s32	d17, d2, #10
│ │  			@ <UNDEFINED> instruction: 0xffe848f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	1fa4e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x8dc64>
│ │  	strb	r1, [r0, #0]
│ │  	b.n	1fa312 <uniffi_pbcli_checksum_method_api_base@@Base+0x8da8e>
│ │  	asrs	r4, r6, #1
│ │ @@ -269501,41 +269501,41 @@
│ │  	movs	r0, #0
│ │  	b.n	1fb046 <uniffi_pbcli_checksum_method_api_base@@Base+0x8e7c2>
│ │  	strb	r3, [r3, #7]
│ │  	add.w	r0, r3, r6
│ │  	b.n	1fac4e <uniffi_pbcli_checksum_method_api_base@@Base+0x8e3ca>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r1, r2, r5, r7, fp}
│ │ -	vrsubhn.i64	d26, q4, q1
│ │ +	vrsubhn.i64	d26, q4, <illegal reg q12.5>
│ │  			@ <UNDEFINED> instruction: 0xffea07c6
│ │ -	vabal.u32	q13, d8, d18
│ │ +	vmls.f32	q13, q4, d9[0]
│ │  	vcvt.f16.u16	q8, q15, #22
│ │ -			@ <UNDEFINED> instruction: 0xffe8a9da
│ │ +	vmlsl.u32	q13, d8, d1
│ │  	vmlal.u32	q8, d26, d10
│ │ -	vmls.f32	q13, q12, d6[1]
│ │ +	vrsubhn.i64	d26, q4, <illegal reg q6.5>
│ │  			@ <UNDEFINED> instruction: 0xffea08d2
│ │ -	vrsubhn.i64	d26, q4, q15
│ │ +	vqshlu.s32	q13, <illegal reg q2.5>, #8
│ │  			@ <UNDEFINED> instruction: 0xffea0bd2
│ │  			@ <UNDEFINED> instruction: 0xffe80b92
│ │ -	vmul.i32	q13, q12, d14[1]
│ │ +	vqshrn.u64	d26, <illegal reg q2.5>, #24
│ │  	vqrshrun.s64	d16, q3, #22
│ │  	vqshrun.s64	d16, q9, #24
│ │ -	vabal.u32	q13, d24, d14
│ │ +	vsli.64	d26, d21, #40	@ 0x28
│ │  	vsri.32	q8, q6, #22
│ │  	movs	r0, r0
│ │  	lsrs	r6, r1, #13
│ │  			@ <UNDEFINED> instruction: 0xffe80b3a
│ │  			@ <UNDEFINED> instruction: 0xffe80b12
│ │ -	vmul.i32	q13, q4, d14[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe8a895
│ │  			@ <UNDEFINED> instruction: 0xffea09f6
│ │  			@ <UNDEFINED> instruction: 0xffe809b6
│ │  	vqshl.u64	d16, d10, #40	@ 0x28
│ │ -	vsri.64	q13, q11, #24
│ │ +	vsli.32	d26, d13, #8
│ │  	vmull.u32	q8, d10, d18
│ │ -	vqrshrn.u64	d26, q15, #24
│ │ +			@ <UNDEFINED> instruction: 0xffe8a9a5
│ │  	vaddl.u32	q8, d10, d0
│ │  	b.n	1fb022 <uniffi_pbcli_checksum_method_api_base@@Base+0x8e79e>
│ │  	movs	r6, r1
│ │  	lsrs	r0, r0, #8
│ │  	asrs	r0, r0, #32
│ │  	b.n	1fa4aa <uniffi_pbcli_checksum_method_api_base@@Base+0x8dc26>
│ │  	movs	r1, r0
│ │ @@ -273049,22 +273049,22 @@
│ │  	cmp	r0, #11
│ │  	add.w	r0, r4, r5
│ │  	b.n	1fcb52 <uniffi_pbcli_checksum_method_api_base@@Base+0x902ce>
│ │  	beq.n	1fc84c <uniffi_pbcli_checksum_method_api_base@@Base+0x8ffc8>
│ │  	b.n	1fccac <uniffi_pbcli_checksum_method_api_base@@Base+0x90428>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r1, r3, r4, r5, r6, r8, fp, sp, lr, pc}
│ │ -	vsli.32	q15, q3, #7
│ │ +	vsli.32	q15, <illegal reg q14.5>, #7
│ │  			@ <UNDEFINED> instruction: 0xffe9e9ba
│ │ -	vsli.64	d30, d6, #39	@ 0x27
│ │ +	vsli.64	d30, d29, #39	@ 0x27
│ │  	vmlsl.u32	q15, d9, d18
│ │  	vmul.f32	q15, <illegal reg q11.5>, d2[1]
│ │ -	vsli.64	d30, d30, #39	@ 0x27
│ │ +	vmls.f32	q15, <illegal reg q11.5>, d5[1]
│ │  			@ <UNDEFINED> instruction: 0xffe9e8f6
│ │ -	vsri.64	q15, q1, #25
│ │ +	vsri.64	q15, <illegal reg q12.5>, #25
│ │  			@ <UNDEFINED> instruction: 0xffe9e896
│ │  	vcvt.f16.u16	d20, d0, #25
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	1fcd64 <uniffi_pbcli_checksum_method_api_base@@Base+0x904e0>
│ │  	ands	r0, r0
│ │  	b.n	1fcb8e <uniffi_pbcli_checksum_method_api_base@@Base+0x9030a>
│ │  	asrs	r4, r1, #9
│ │ @@ -273259,15 +273259,15 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	1fd146 <uniffi_pbcli_checksum_method_api_base@@Base+0x908c2>
│ │  	ldr	r2, [r4, #16]
│ │  	add.w	r0, r1, r5
│ │  	b.n	1fcd4e <uniffi_pbcli_checksum_method_api_base@@Base+0x904ca>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r1, r3, r5, r7, r8, r9, sl, fp, sp, lr, pc}
│ │ -	vrsra.u64	d30, d9, #24
│ │ +			@ <UNDEFINED> instruction: 0xffe8e3c0
│ │  			@ <UNDEFINED> instruction: 0xffe948f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	1fcf3c <uniffi_pbcli_checksum_method_api_base@@Base+0x906b8>
│ │  	beq.n	1fca34 <uniffi_pbcli_checksum_method_api_base@@Base+0x901b0>
│ │  	b.n	1fcec0 <uniffi_pbcli_checksum_method_api_base@@Base+0x9063c>
│ │  	ands	r0, r0
│ │  	b.n	1fcd6a <uniffi_pbcli_checksum_method_api_base@@Base+0x904e6>
│ │ @@ -274979,15 +274979,15 @@
│ │  	lsrs	r0, r4, #30
│ │  	b.n	1fdbf2 <uniffi_pbcli_checksum_method_api_base@@Base+0x9136e>
│ │  	movs	r0, r0
│ │  	b.n	1fd3ba <uniffi_pbcli_checksum_method_api_base@@Base+0x90b36>
│ │  	beq.n	1fd8ce <uniffi_pbcli_checksum_method_api_base@@Base+0x9104a>
│ │  	b.n	1fdbfa <uniffi_pbcli_checksum_method_api_base@@Base+0x91376>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r8, sl, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r6, r8, sl, ip, lr, pc}
│ │  	vqdmulh.s32	<illegal reg q9.5>, <illegal reg q4.5>, d8[0]
│ │  	movs	r6, r5
│ │  	ldrb	r0, [r5, r0]
│ │  	movs	r6, r5
│ │  	subs	r4, #56	@ 0x38
│ │  	movs	r6, r5
│ │  	ldr	r4, [pc, #448]	@ (1fda90 <uniffi_pbcli_checksum_method_api_base@@Base+0x9120c>)
│ │ @@ -275070,17 +275070,17 @@
│ │  	b.n	1fe0b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x91832>
│ │  	asrs	r1, r0, #32
│ │  	b.n	1fda98 <uniffi_pbcli_checksum_method_api_base@@Base+0x91214>
│ │  	ldrb	r3, [r2, #21]
│ │  	add.w	r0, r4, r4
│ │  	b.n	1fdcc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x9143e>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r3, r5, r7, r8, r9, sl, fp, ip, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffe9bf89
│ │ -			@ <UNDEFINED> instruction: 0xffe9bf25
│ │ +	ldmia.w	sp!, {r4, r6, r7, r8, r9, sl, fp, ip, sp, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffe9bfb0
│ │ +	vqrdmlsh.s32	<illegal reg q13.5>, <illegal reg q4.5>, d12[0]
│ │  	vshr.u32	q8, q0, #23
│ │  	movs	r0, r0
│ │  	ldr	r4, [pc, #448]	@ (1fdb58 <uniffi_pbcli_checksum_method_api_base@@Base+0x912d4>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	1fdeb8 <uniffi_pbcli_checksum_method_api_base@@Base+0x91634>
│ │  	ands	r3, r0
│ │  	b.n	1fdce2 <uniffi_pbcli_checksum_method_api_base@@Base+0x9145e>
│ │ @@ -275670,24 +275670,24 @@
│ │  			@ <UNDEFINED> instruction: 0xeb00a000
│ │  	b.n	1fe5e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x91d5e>
│ │  	movs	r2, r1
│ │  	b.n	1fe1e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x91962>
│ │  	beq.n	1fdee0 <uniffi_pbcli_checksum_method_api_base@@Base+0x9165c>
│ │  	b.n	1fe340 <uniffi_pbcli_checksum_method_api_base@@Base+0x91abc>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r5, r8, sl, fp, ip, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffe9bd01
│ │ -			@ <UNDEFINED> instruction: 0xffe9bb65
│ │ -	vmlsl.u32	<illegal reg q13.5>, d9, d21
│ │ +	ldmia.w	sp!, {r2, r3, r6, r8, sl, fp, ip, sp, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffe9bd28
│ │ +			@ <UNDEFINED> instruction: 0xffe9bb8c
│ │ +	vmull.u32	<illegal reg q13.5>, d9, d12[0]
│ │  			@ <UNDEFINED> instruction: 0xffe91d9a
│ │ -			@ <UNDEFINED> instruction: 0xffe9bbd5
│ │ -			@ <UNDEFINED> instruction: 0xffe9bba1
│ │ -			@ <UNDEFINED> instruction: 0xffe9bb39
│ │ -	vmull.u32	<illegal reg q13.5>, d25, d9[1]
│ │ -	vmull.u32	<illegal reg q13.5>, d9, d13[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe9bbfc
│ │ +			@ <UNDEFINED> instruction: 0xffe9bbc8
│ │ +			@ <UNDEFINED> instruction: 0xffe9bb60
│ │ +			@ <UNDEFINED> instruction: 0xffe9bb10
│ │ +			@ <UNDEFINED> instruction: 0xffe9ba74
│ │  	vqshrun.s64	d20, q8, #23
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	1fe3f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x91b74>
│ │  	movs	r0, r0
│ │  	b.n	1fe582 <uniffi_pbcli_checksum_method_api_base@@Base+0x91cfe>
│ │  	movs	r2, r1
│ │  	lsrs	r0, r0, #8
│ │ @@ -275771,15 +275771,15 @@
│ │  	b.n	1fe2de <uniffi_pbcli_checksum_method_api_base@@Base+0x91a5a>
│ │  	asrs	r5, r0, #32
│ │  	b.n	1fe2e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x91a5e>
│ │  	movs	r1, #33	@ 0x21
│ │  	b.n	1fe5a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x91d22>
│ │  	ldr	r0, [pc, #192]	@ (1fe068 <uniffi_pbcli_checksum_method_api_base@@Base+0x917e4>)
│ │  	ldmia.w	sp!, {r0, r1, r2, r6, r7, r8, r9, fp, ip, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xea04b965
│ │ +			@ <UNDEFINED> instruction: 0xea04b98c
│ │  			@ <UNDEFINED> instruction: 0xffe94bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	1fe4d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x91c50>
│ │  	movs	r0, r0
│ │  	b.n	1fe65e <uniffi_pbcli_checksum_method_api_base@@Base+0x91dda>
│ │  	str	r0, [sp, #0]
│ │  	asrs	r0, r4, #6
│ │ @@ -275833,15 +275833,15 @@
│ │  	b.n	1fdb32 <uniffi_pbcli_checksum_method_api_base@@Base+0x912ae>
│ │  	movs	r0, r0
│ │  	b.n	1fe2d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x91a54>
│ │  	str	r0, [r2, #0]
│ │  	b.n	1fdb3a <uniffi_pbcli_checksum_method_api_base@@Base+0x912b6>
│ │  			@ <UNDEFINED> instruction: 0xffea3aff
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r5, r7, fp, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r2, r5, r6, r7, fp, ip, sp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffe94ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	1fe560 <uniffi_pbcli_checksum_method_api_base@@Base+0x91cdc>
│ │  	beq.n	1fe050 <uniffi_pbcli_checksum_method_api_base@@Base+0x917cc>
│ │  	b.n	1fe4e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x91c60>
│ │  	str	r0, [r0, #0]
│ │  	b.n	1fe38e <uniffi_pbcli_checksum_method_api_base@@Base+0x91b0a>
│ │ @@ -275939,15 +275939,15 @@
│ │  	b.n	1fe85a <uniffi_pbcli_checksum_method_api_base@@Base+0x91fd6>
│ │  	str	r6, [r2, #60]	@ 0x3c
│ │  	add.w	r0, r3, r4
│ │  	b.n	1fe462 <uniffi_pbcli_checksum_method_api_base@@Base+0x91bde>
│ │  	beq.n	1fe15c <uniffi_pbcli_checksum_method_api_base@@Base+0x918d8>
│ │  	b.n	1fe5bc <uniffi_pbcli_checksum_method_api_base@@Base+0x91d38>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r7, r8, r9, sl, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r2, r6, r7, r8, r9, sl, ip, sp, pc}
│ │  	vabdl.u32	q10, d25, d25
│ │  	vcvt.f16.u16	q10, q8, #23
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	1fe654 <uniffi_pbcli_checksum_method_api_base@@Base+0x91dd0>
│ │  	ands	r1, r0
│ │  	b.n	1fe47e <uniffi_pbcli_checksum_method_api_base@@Base+0x91bfa>
│ │  	str	r0, [r0, #0]
│ │ @@ -276078,15 +276078,15 @@
│ │  	b.n	1fe996 <uniffi_pbcli_checksum_method_api_base@@Base+0x92112>
│ │  	str	r7, [r0, #56]	@ 0x38
│ │  	add.w	r0, r3, r4
│ │  	b.n	1fe59e <uniffi_pbcli_checksum_method_api_base@@Base+0x91d1a>
│ │  	beq.n	1fe280 <uniffi_pbcli_checksum_method_api_base@@Base+0x919fc>
│ │  	b.n	1fe6f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x91e74>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r6, r9, sl, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r2, r7, r9, sl, ip, sp, pc}
│ │  	vabdl.u32	<illegal reg q14.5>, d25, d6
│ │  	vcvt.f16.u16	d20, d0, #24
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	1fe790 <uniffi_pbcli_checksum_method_api_base@@Base+0x91f0c>
│ │  	ands	r2, r0
│ │  	b.n	1fe5ba <uniffi_pbcli_checksum_method_api_base@@Base+0x91d36>
│ │  			@ <UNDEFINED> instruction: 0xffcaebff
│ │ @@ -276612,31 +276612,31 @@
│ │  	b.n	1fea4e <uniffi_pbcli_checksum_method_api_base@@Base+0x921ca>
│ │  	asrs	r0, r0, #16
│ │  	add.w	r0, r6, r7
│ │  	b.n	1fea56 <uniffi_pbcli_checksum_method_api_base@@Base+0x921d2>
│ │  	beq.n	1fe750 <uniffi_pbcli_checksum_method_api_base@@Base+0x91ecc>
│ │  	b.n	1febb0 <uniffi_pbcli_checksum_method_api_base@@Base+0x9232c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r3, r5, r7, r8, r9, ip, sp, pc}
│ │ -	vmlal.u32	<illegal reg q15.5>, d9, d31
│ │ -			@ <UNDEFINED> instruction: 0xffe9b3cd
│ │ -	vqrshrun.s64	d31, <illegal reg q1.5>, #23
│ │ -	vsra.u64	d27, d21, #23
│ │ -	vqshlu.s32	d31, d27, #9
│ │ +	ldmia.w	sp!, {r4, r6, r7, r8, r9, ip, sp, pc}
│ │ +	vqrshrun.s64	d31, q3, #23
│ │ +	vrsra.u64	<illegal reg q13.5>, q10, #23
│ │ +	vqrshrun.s64	d31, q13, #23
│ │ +	vsra.u64	<illegal reg q13.5>, q6, #23
│ │ +	vmlsl.u32	<illegal reg q15.5>, d9, d2[1]
│ │  	vqrdmlsh.s32	q10, <illegal reg q4.5>, d8[0]
│ │  	movs	r6, r5
│ │  	bl	4db73a <uniffi_pbcli_checksum_method_api_base@@Base+0x36eeb6>
│ │  	ldr	r7, [pc, #192]	@ (1fe800 <uniffi_pbcli_checksum_method_api_base@@Base+0x91f7c>)
│ │  	movs	r6, r5
│ │  	cmp	r7, #60	@ 0x3c
│ │  	movs	r6, r5
│ │  	bmi.n	1fe756 <uniffi_pbcli_checksum_method_api_base@@Base+0x91ed2>
│ │ -	vmull.u32	<illegal reg q12.5>, d8, d18
│ │ -	vsra.u64	<illegal reg q13.5>, <illegal reg q12.5>, #23
│ │ -	vqshlu.s32	<illegal reg q15.5>, <illegal reg q15.5>, #9
│ │ +	vqdmulh.s32	<illegal reg q12.5>, q4, d9[0]
│ │ +	vsubl.u32	<illegal reg q13.5>, d9, d16
│ │ +	vrsubhn.i64	d31, <illegal reg q12.5>, q11
│ │  	vaddl.u32	q9, d9, d0
│ │  	b.n	1fee9a <uniffi_pbcli_checksum_method_api_base@@Base+0x92616>
│ │  	vpmin.u32	q7, <illegal reg q14.5>, <illegal reg q15.5>
│ │  	ldr	r0, [pc, #192]	@ (1fe820 <uniffi_pbcli_checksum_method_api_base@@Base+0x91f9c>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	1fec80 <uniffi_pbcli_checksum_method_api_base@@Base+0x923fc>
│ │  	movs	r0, r0
│ │ @@ -276851,15 +276851,15 @@
│ │  	str	r1, [r4, #96]	@ 0x60
│ │  	add.w	r0, sl, r0, lsl #16
│ │  	b.n	1fec7e <uniffi_pbcli_checksum_method_api_base@@Base+0x923fa>
│ │  			@ <UNDEFINED> instruction: 0xffeaeaff
│ │  	ands	r0, r0
│ │  	b.n	1fe9d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x9214c>
│ │  			@ <UNDEFINED> instruction: 0xffe8eaff
│ │ -	add	r7, sp, #644	@ 0x284
│ │ +	add	r7, sp, #800	@ 0x320
│ │  			@ <UNDEFINED> instruction: 0xffe94df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	1fee70 <uniffi_pbcli_checksum_method_api_base@@Base+0x925ec>
│ │  	beq.n	1fe968 <uniffi_pbcli_checksum_method_api_base@@Base+0x920e4>
│ │  	b.n	1fedf4 <uniffi_pbcli_checksum_method_api_base@@Base+0x92570>
│ │  	str	r0, [r0, #0]
│ │  	b.n	1fec9e <uniffi_pbcli_checksum_method_api_base@@Base+0x9241a>
│ │ @@ -276972,15 +276972,15 @@
│ │  	movs	r0, r0
│ │  	lsrs	r0, r6, #24
│ │  	movs	r0, r0
│ │  	lsrs	r0, r6, #24
│ │  	movs	r0, r0
│ │  	lsrs	r0, r6, #24
│ │  	movs	r0, r0
│ │ -	add	r6, sp, #564	@ 0x234
│ │ +	add	r6, sp, #720	@ 0x2d0
│ │  	vqrshrn.u64	d27, q2, #23
│ │  			@ <UNDEFINED> instruction: 0xffe84bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	1fef88 <uniffi_pbcli_checksum_method_api_base@@Base+0x92704>
│ │  	beq.n	1fea80 <uniffi_pbcli_checksum_method_api_base@@Base+0x921fc>
│ │  	b.n	1fef0c <uniffi_pbcli_checksum_method_api_base@@Base+0x92688>
│ │  	str	r0, [r0, r0]
│ │ @@ -277123,15 +277123,15 @@
│ │  	beq.n	1febe0 <uniffi_pbcli_checksum_method_api_base@@Base+0x9235c>
│ │  	b.n	1ff048 <uniffi_pbcli_checksum_method_api_base@@Base+0x927c4>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r0, r1, r2}
│ │  	b.n	1feefa <uniffi_pbcli_checksum_method_api_base@@Base+0x92676>
│ │  	adds	r1, #85	@ 0x55
│ │  			@ <UNDEFINED> instruction: 0xeb06fff5
│ │ -			@ <UNDEFINED> instruction: 0xeaffad31
│ │ +			@ <UNDEFINED> instruction: 0xeaffad58
│ │  	vsri.64	<illegal reg q12.5>, <illegal reg q5.5>, #23
│ │  			@ <UNDEFINED> instruction: 0xffe74ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	1ff0ec <uniffi_pbcli_checksum_method_api_base@@Base+0x92868>
│ │  	beq.n	1feccc <uniffi_pbcli_checksum_method_api_base@@Base+0x92448>
│ │  	b.n	1ff070 <uniffi_pbcli_checksum_method_api_base@@Base+0x927ec>
│ │  	blt.n	1febda <uniffi_pbcli_checksum_method_api_base@@Base+0x92356>
│ │ @@ -277425,22 +277425,22 @@
│ │  	movs	r0, r0
│ │  	lsrs	r0, r5, #14
│ │  	movs	r0, r0
│ │  	lsrs	r0, r5, #14
│ │  	movs	r0, r0
│ │  	lsrs	r0, r5, #14
│ │  	movs	r0, r0
│ │ -	add	r3, sp, #260	@ 0x104
│ │ +	add	r3, sp, #416	@ 0x1a0
│ │  	vsli.32	q12, <illegal reg q5.5>, #9
│ │ -	vmull.u32	q13, d8, d9[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe8aa90
│ │  	vraddhn.i64	d24, <illegal reg q12.5>, <illegal reg q1.5>
│ │ -			@ <UNDEFINED> instruction: 0xffe86b33
│ │ -			@ <UNDEFINED> instruction: 0xffe9ab01
│ │ +			@ <UNDEFINED> instruction: 0xffe86b5a
│ │ +			@ <UNDEFINED> instruction: 0xffe9ab28
│ │  	vsli.32	d24, d11, #9
│ │ -	vmull.u32	q13, d24, d12[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe8ab13
│ │  	vcvt.f16.u16	q10, q8, #23
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	1ff3b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x92b2c>
│ │  	ands	r1, r0
│ │  	b.n	1ff1da <uniffi_pbcli_checksum_method_api_base@@Base+0x92956>
│ │  	asrs	r4, r6, #32
│ │  	b.n	1fe9dc <uniffi_pbcli_checksum_method_api_base@@Base+0x92158>
│ │ @@ -278047,23 +278047,23 @@
│ │  	b.n	1ff746 <uniffi_pbcli_checksum_method_api_base@@Base+0x92ec2>
│ │  	asrs	r2, r0, #3
│ │  	add.w	r0, r6, r5
│ │  	b.n	1ff74e <uniffi_pbcli_checksum_method_api_base@@Base+0x92eca>
│ │  	beq.n	1ff448 <uniffi_pbcli_checksum_method_api_base@@Base+0x92bc4>
│ │  	b.n	1ff8a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x93024>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r6, r7, r8, r9, sl, sp, pc}
│ │ +	ldmia.w	sp!, {r2, fp, sp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffe90b5f
│ │ -	vrsubhn.i64	d26, <illegal reg q12.5>, <illegal reg q10.5>
│ │ +	vmlsl.u32	q13, d25, d12[0]
│ │  	vmlsl.u32	q8, d9, d23
│ │ -	vmlsl.u32	q13, d9, d9[0]
│ │ +	vqshlu.s32	q13, q8, #9
│ │  	vmul.f32	q8, <illegal reg q12.5>, d11[0]
│ │ -	vabal.u32	q13, d9, d29
│ │ +	vsli.32	q13, q2, #9
│ │  	vmlal.u32	q8, d25, d31
│ │ -	vsri.64	q13, <illegal reg q6.5>, #23
│ │ +	vabal.u32	q13, d9, d4
│ │  	vqrshrun.s64	d16, <illegal reg q7.5>, #23
│ │  	vqshlu.s32	d26, d24, #9
│ │  			@ <UNDEFINED> instruction: 0xffe748f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	1ff964 <uniffi_pbcli_checksum_method_api_base@@Base+0x930e0>
│ │  	strb	r4, [r7, #0]
│ │  	b.n	1ffb8e <uniffi_pbcli_checksum_method_api_base@@Base+0x9330a>
│ │ @@ -279096,18 +279096,18 @@
│ │  	vcvt.u16.f16	d22, d8, #22
│ │  	vqshl.u64	d24, d15, #42	@ 0x2a
│ │  	vrshr.u32	<illegal reg q14.5>, q7, #25
│ │  			@ <UNDEFINED> instruction: 0xffe7eb2e
│ │  	vrsra.u32	d29, d15, #25
│ │  	vqdmulh.s32	q11, <illegal reg q3.5>, d4[0]
│ │  	vmul.f32	q13, q13, d8[1]
│ │ -	vrshr.u64	d23, d26, #24
│ │ +	vmlal.u32	<illegal reg q11.5>, d24, d1[1]
│ │  	vaddl.u32	<illegal reg q12.5>, d9, d26
│ │ -	vmlal.u32	<illegal reg q13.5>, d8, d9[1]
│ │ -	vcvt.f16.u16	d19, d7, #23
│ │ +	vrshr.u64	d27, d0, #24
│ │ +	vcvt.f16.u16	d19, d30, #23
│ │  	vabdl.u32	<illegal reg q8.5>, d26, d15
│ │  	vmull.u32	q9, d8, d17
│ │  	vcvt.f16.u16	q10, q8, #23
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	20028c <uniffi_pbcli_checksum_method_api_base@@Base+0x93a08>
│ │  	ands	r2, r0
│ │  	b.n	2000b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x93832>
│ │ @@ -282216,15 +282216,15 @@
│ │  	b.n	201ec6 <uniffi_pbcli_checksum_method_api_base@@Base+0x95642>
│ │  	str	r6, [r0, #0]
│ │  	b.n	2018a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x95024>
│ │  	movs	r4, r1
│ │  	and.w	sl, r0, r1, lsl #2
│ │  			@ <UNDEFINED> instruction: 0xffe99bd1
│ │  	vsri.32	<illegal reg q15.5>, q2, #24
│ │ -			@ <UNDEFINED> instruction: 0xffe8eadc
│ │ +			@ <UNDEFINED> instruction: 0xffe8eb03
│ │  	vaddl.u32	q8, d9, d7
│ │  	b.n	201ae2 <uniffi_pbcli_checksum_method_api_base@@Base+0x9525e>
│ │  	asrs	r4, r0, #32
│ │  	b.n	201ae6 <uniffi_pbcli_checksum_method_api_base@@Base+0x95262>
│ │  	strh	r2, [r3, #48]	@ 0x30
│ │  	add.w	r0, r5, r1, lsl #16
│ │  	b.n	201c36 <uniffi_pbcli_checksum_method_api_base@@Base+0x953b2>
│ │ @@ -282336,27 +282336,27 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	2019c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x95140>
│ │  	ldr	r0, [r1, #88]	@ 0x58
│ │  	add.w	r0, r4, r9
│ │  	b.n	201bee <uniffi_pbcli_checksum_method_api_base@@Base+0x9536a>
│ │  	strh	r1, [r4, #32]
│ │  	add.w	r0, r5, r2, lsr #32
│ │ -	and.w	lr, r0, r3, lsr #17
│ │ +	and.w	lr, r0, sl, ror #17
│ │  	vshll.u32	q11, d10, #9
│ │  	vaddl.u32	<illegal reg q8.5>, d24, d0
│ │  	b.n	201400 <uniffi_pbcli_checksum_method_api_base@@Base+0x94b7c>
│ │  	movs	r6, r0
│ │  	b.n	201c06 <uniffi_pbcli_checksum_method_api_base@@Base+0x95382>
│ │  	movs	r6, #78	@ 0x4e
│ │  	b.n	201eca <uniffi_pbcli_checksum_method_api_base@@Base+0x95646>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2019ec <uniffi_pbcli_checksum_method_api_base@@Base+0x95168>
│ │  	movs	r2, r1
│ │  			@ <UNDEFINED> instruction: 0xea009082
│ │ -	vcvt.f32.u32	d20, d19, #25
│ │ +	vcvt.f32.u32	q10, q5, #25
│ │  	vmla.i32	<illegal reg q8.5>, <illegal reg q4.5>, d8[0]
│ │  	b.n	20141c <uniffi_pbcli_checksum_method_api_base@@Base+0x94b98>
│ │  	movs	r0, r1
│ │  	b.n	201c22 <uniffi_pbcli_checksum_method_api_base@@Base+0x9539e>
│ │  	movs	r6, #66	@ 0x42
│ │  	b.n	201ee6 <uniffi_pbcli_checksum_method_api_base@@Base+0x95662>
│ │  	asrs	r1, r0, #32
│ │ @@ -282376,15 +282376,15 @@
│ │  			@ <UNDEFINED> instruction: 0xfb9aeaff
│ │  	subs	r2, #71	@ 0x47
│ │  	vsubl.u32	<illegal reg q9.5>, d24, d23
│ │  			@ <UNDEFINED> instruction: 0xffe82ff7
│ │  			@ <UNDEFINED> instruction: 0xffe82fa7
│ │  	vmlal.u32	q8, d8, d8
│ │  	movs	r2, r5
│ │ -	add	r7, sp, #320	@ 0x140
│ │ +	add	r7, sp, #476	@ 0x1dc
│ │  	vraddhn.i64	d23, <illegal reg q4.5>, q12
│ │  	vqdmulh.s32	q9, q4, d7[0]
│ │  	vmlsl.u32	q9, d24, d11
│ │  			@ <UNDEFINED> instruction: 0xffe82a77
│ │  	vmull.u32	q9, d8, d23
│ │  	vqrdmulh.s32	q10, q12, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffea2b3b
│ │ @@ -283806,19 +283806,19 @@
│ │  	strh	r0, [r3, r3]
│ │  	add.w	r0, r3, r4, asr #32
│ │  	b.n	202054 <uniffi_pbcli_checksum_method_api_base@@Base+0x957d0>
│ │  	beq.n	202554 <uniffi_pbcli_checksum_method_api_base@@Base+0x95cd0>
│ │  	b.n	2029b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x96130>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6, r9, sl, fp, ip}
│ │ -	vmull.p64	q14, d8, d1
│ │ +	vmull.p64	q14, d8, d24
│ │  			@ <UNDEFINED> instruction: 0xffe9bfae
│ │  	vqshrun.s64	d29, q5, #24
│ │  			@ <UNDEFINED> instruction: 0xffe81f07
│ │ -	vmull.p64	q14, d24, d9
│ │ +			@ <UNDEFINED> instruction: 0xffe8ceb0
│ │  	vaddl.u32	q8, d9, d4
│ │  	b.n	20207c <uniffi_pbcli_checksum_method_api_base@@Base+0x957f8>
│ │  	movs	r0, r0
│ │  	b.n	202660 <uniffi_pbcli_checksum_method_api_base@@Base+0x95ddc>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	str	r0, [r7, #88]	@ 0x58
│ │  	vqshrun.s64	d20, q8, #24
│ │ @@ -284047,15 +284047,15 @@
│ │  	b.n	202e8e <uniffi_pbcli_checksum_method_api_base@@Base+0x9660a>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r2}
│ │  	b.n	202294 <uniffi_pbcli_checksum_method_api_base@@Base+0x95a10>
│ │  	movs	r0, r0
│ │  	b.n	202878 <uniffi_pbcli_checksum_method_api_base@@Base+0x95ff4>
│ │  	vrhadd.u16	d14, d14, d31
│ │ -	push	{r0, r1, r5, r6, r7, lr}
│ │ +			@ <UNDEFINED> instruction: 0xb60a
│ │  			@ <UNDEFINED> instruction: 0xffe948f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	202c84 <uniffi_pbcli_checksum_method_api_base@@Base+0x96400>
│ │  	beq.n	20280c <uniffi_pbcli_checksum_method_api_base@@Base+0x95f88>
│ │  	b.n	202c08 <uniffi_pbcli_checksum_method_api_base@@Base+0x96384>
│ │  	str	r1, [r0, #0]
│ │  	b.n	202ab2 <uniffi_pbcli_checksum_method_api_base@@Base+0x9622e>
│ │ @@ -284121,15 +284121,15 @@
│ │  	strh	r0, [r4, r0]
│ │  	add.w	r0, r3, r4
│ │  	b.n	202b3a <uniffi_pbcli_checksum_method_api_base@@Base+0x962b6>
│ │  	beq.n	20281c <uniffi_pbcli_checksum_method_api_base@@Base+0x95f98>
│ │  	b.n	202c94 <uniffi_pbcli_checksum_method_api_base@@Base+0x96410>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r7, r8, r9, fp, ip}
│ │ -	vabal.u32	<illegal reg q13.5>, d24, d30
│ │ +	vsli.64	<illegal reg q13.5>, <illegal reg q2.5>, #40	@ 0x28
│ │  	vqshrun.s64	d20, q8, #23
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	202d2c <uniffi_pbcli_checksum_method_api_base@@Base+0x964a8>
│ │  	str	r0, [r0, r0]
│ │  	b.n	202b56 <uniffi_pbcli_checksum_method_api_base@@Base+0x962d2>
│ │  	movs	r4, r1
│ │  	b.n	202f5a <uniffi_pbcli_checksum_method_api_base@@Base+0x966d6>
│ │ @@ -284514,15 +284514,15 @@
│ │  	movs	r0, #0
│ │  	b.n	2032d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x96a52>
│ │  	str	r7, [r6, r4]
│ │  	add.w	r0, r3, r0
│ │  	b.n	2032de <uniffi_pbcli_checksum_method_api_base@@Base+0x96a5a>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r5, r7, r8}
│ │ -	vshr.u64	d30, d13, #24
│ │ +	vmla.i32	q15, q12, d4[0]
│ │  			@ <UNDEFINED> instruction: 0xffe948f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2030cc <uniffi_pbcli_checksum_method_api_base@@Base+0x96848>
│ │  	ands	r0, r0
│ │  	b.n	2032f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x96a72>
│ │  	movs	r0, r0
│ │  	b.n	20325a <uniffi_pbcli_checksum_method_api_base@@Base+0x969d6>
│ │ @@ -284794,17 +284794,17 @@
│ │  	movs	r0, #0
│ │  	b.n	203556 <uniffi_pbcli_checksum_method_api_base@@Base+0x96cd2>
│ │  	str	r7, [r2, r2]
│ │  	add.w	r0, r3, r0
│ │  	b.n	20355e <uniffi_pbcli_checksum_method_api_base@@Base+0x96cda>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r3, r6, r8, r9, sl, fp, ip, sp, lr, pc}
│ │ -	vshr.u64	q12, <illegal reg q15.5>, #25
│ │ +	vaddw.u32	q12, <illegal reg q3.5>, d22
│ │  			@ <UNDEFINED> instruction: 0xffe9ff21
│ │ -	vshr.u64	q12, <illegal reg q3.5>, #25
│ │ +	vshr.u64	q12, q15, #25
│ │  			@ <UNDEFINED> instruction: 0xffe948f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	203354 <uniffi_pbcli_checksum_method_api_base@@Base+0x96ad0>
│ │  	str	r2, [r0, r0]
│ │  	b.n	20317e <uniffi_pbcli_checksum_method_api_base@@Base+0x968fa>
│ │  	str	r1, [r0, #0]
│ │  	b.n	203182 <uniffi_pbcli_checksum_method_api_base@@Base+0x968fe>
│ │ @@ -285735,15 +285735,15 @@
│ │  	b.n	203160 <uniffi_pbcli_checksum_method_api_base@@Base+0x968dc>
│ │  	ldrh	r4, [r2, #4]
│ │  	b.n	203164 <uniffi_pbcli_checksum_method_api_base@@Base+0x968e0>
│ │  	movs	r4, r0
│ │  	b.n	20399e <uniffi_pbcli_checksum_method_api_base@@Base+0x9711a>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, r2, r3, r5, r8, r9, sl, ip, sp, lr, pc}
│ │ -	vqdmulh.s32	q15, <illegal reg q3.5>, d7[0]
│ │ +	vqdmulh.s32	q15, <illegal reg q3.5>, d14[1]
│ │  	vcvt.f16.u16	d20, d0, #23
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	203b8c <uniffi_pbcli_checksum_method_api_base@@Base+0x97308>
│ │  	movs	r0, r0
│ │  	b.n	203d16 <uniffi_pbcli_checksum_method_api_base@@Base+0x97492>
│ │  	movs	r2, r1
│ │  	lsrs	r0, r0, #8
│ │ @@ -287544,15 +287544,15 @@
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0}
│ │  	b.n	204dae <uniffi_pbcli_checksum_method_api_base@@Base+0x9852a>
│ │  	beq.n	204680 <uniffi_pbcli_checksum_method_api_base@@Base+0x97dfc>
│ │  	b.n	204b08 <uniffi_pbcli_checksum_method_api_base@@Base+0x98284>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r3, r8, r9, sl, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffe7adf1
│ │ +	vcvt.f32.u32	d26, d8, #25
│ │  	vcvt.u16.f16	q9, q8, #23
│ │  	movs	r0, r0
│ │  	ldr	r4, [pc, #64]	@ (2046c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x97e40>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	204ba4 <uniffi_pbcli_checksum_method_api_base@@Base+0x98320>
│ │  	movs	r0, r0
│ │  	b.n	204d2e <uniffi_pbcli_checksum_method_api_base@@Base+0x984aa>
│ │ @@ -288631,15 +288631,15 @@
│ │  	movs	r0, #0
│ │  	b.n	20573e <uniffi_pbcli_checksum_method_api_base@@Base+0x98eba>
│ │  	ldr	r0, [pc, #116]	@ (205074 <uniffi_pbcli_checksum_method_api_base@@Base+0x987f0>)
│ │  	add.w	r0, r3, r0
│ │  	b.n	205746 <uniffi_pbcli_checksum_method_api_base@@Base+0x98ec2>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r3, r4, r5, r8, sl, fp, ip, lr, pc}
│ │ -	vmul.f32	q10, <illegal reg q11.5>, d1[1]
│ │ +	vmlsl.u32	q10, d7, d8
│ │  	vqshrun.s64	d20, q8, #23
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	205534 <uniffi_pbcli_checksum_method_api_base@@Base+0x98cb0>
│ │  	movs	r0, r0
│ │  	b.n	2056be <uniffi_pbcli_checksum_method_api_base@@Base+0x98e3a>
│ │  	movs	r2, r0
│ │  	lsrs	r0, r0, #8
│ │ @@ -288719,15 +288719,15 @@
│ │  	movs	r0, #0
│ │  	b.n	205802 <uniffi_pbcli_checksum_method_api_base@@Base+0x98f7e>
│ │  	blxns	sp
│ │  	add.w	r0, r3, r0
│ │  	b.n	20580a <uniffi_pbcli_checksum_method_api_base@@Base+0x98f86>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r2, r4, r5, r6, sl, fp, ip, lr, pc}
│ │ -	vqshrn.u64	d20, <illegal reg q6.5>, #25
│ │ +	vmul.f32	q10, <illegal reg q3.5>, d4[0]
│ │  			@ <UNDEFINED> instruction: 0xffe94bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2055f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x98d74>
│ │  	beq.n	205160 <uniffi_pbcli_checksum_method_api_base@@Base+0x988dc>
│ │  	b.n	20557c <uniffi_pbcli_checksum_method_api_base@@Base+0x98cf8>
│ │  	movs	r0, r0
│ │  	b.n	205786 <uniffi_pbcli_checksum_method_api_base@@Base+0x98f02>
│ │ @@ -292833,15 +292833,15 @@
│ │  	movs	r0, #0
│ │  	b.n	207b82 <uniffi_pbcli_checksum_method_api_base@@Base+0x9b2fe>
│ │  	subs	r7, #12
│ │  	add.w	r0, r3, r0
│ │  	b.n	207b8a <uniffi_pbcli_checksum_method_api_base@@Base+0x9b306>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r3, r4, r5, r6, r7, fp, ip, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffe7adf7
│ │ +	vcvt.f32.u32	d26, d14, #25
│ │  	vcvt.f16.u16	q10, q8, #23
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	207978 <uniffi_pbcli_checksum_method_api_base@@Base+0x9b0f4>
│ │  	ands	r0, r0
│ │  	b.n	2077a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x9af1e>
│ │  	movs	r4, r5
│ │  	b.n	206f86 <uniffi_pbcli_checksum_method_api_base@@Base+0x9a702>
│ │ @@ -294136,19 +294136,19 @@
│ │  	b.n	208716 <uniffi_pbcli_checksum_method_api_base@@Base+0x9be92>
│ │  	lsls	r4, r7, #29
│ │  	b.n	207ae2 <uniffi_pbcli_checksum_method_api_base@@Base+0x9b25e>
│ │  	movs	r0, r0
│ │  	b.n	20871e <uniffi_pbcli_checksum_method_api_base@@Base+0x9be9a>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r4, r6, r7, r8, sl, fp, sp, pc}
│ │ -	vshll.u32	<illegal reg q13.5>, d9, #7
│ │ +	vmull.u32	<illegal reg q13.5>, d7, d0[0]
│ │  			@ <UNDEFINED> instruction: 0xffe9ada1
│ │ -	vmul.f32	<illegal reg q13.5>, <illegal reg q11.5>, d9[1]
│ │ +	vshll.u32	<illegal reg q13.5>, d0, #7
│ │  	vcvt.u16.f16	q13, <illegal reg q10.5>, #23
│ │ -			@ <UNDEFINED> instruction: 0xffe7b9bd
│ │ +	vmul.f32	<illegal reg q13.5>, <illegal reg q11.5>, d4[1]
│ │  	vqshrun.s64	d20, q8, #23
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	20851c <uniffi_pbcli_checksum_method_api_base@@Base+0x9bc98>
│ │  	beq.n	208014 <uniffi_pbcli_checksum_method_api_base@@Base+0x9b790>
│ │  	b.n	2084a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x9bc1c>
│ │  	str	r0, [r0, r0]
│ │  	b.n	20834a <uniffi_pbcli_checksum_method_api_base@@Base+0x9bac6>
│ │ @@ -294668,16 +294668,16 @@
│ │  	vaddw.u32	<illegal reg q12.5>, <illegal reg q3.5>, d29
│ │  	vmull.u32	q13, d8, d9[1]
│ │  	vmlsl.u32	q13, d7, d29
│ │  	vmul.f32	q13, <illegal reg q3.5>, d9[0]
│ │  			@ <UNDEFINED> instruction: 0xffe78fa5
│ │  			@ <UNDEFINED> instruction: 0xffe8a921
│ │  	vcvt.u32.f32	q12, <illegal reg q14.5>, #25
│ │ -	vmlsl.u32	<illegal reg q8.5>, d8, d5[1]
│ │ -	vqshlu.s32	d17, d21, #9
│ │ +	vrsubhn.i64	d17, q12, q6
│ │ +	vqshlu.s32	<illegal reg q8.5>, q6, #9
│ │  	vmul.i32	q13, <illegal reg q12.5>, d9[0]
│ │  			@ <UNDEFINED> instruction: 0xffe78f25
│ │  			@ <UNDEFINED> instruction: 0xffe84ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2089d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x9c150>
│ │  	beq.n	2084f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x9bc70>
│ │  	b.n	208958 <uniffi_pbcli_checksum_method_api_base@@Base+0x9c0d4>
│ │ @@ -295062,25 +295062,25 @@
│ │  	movs	r0, #0
│ │  	b.n	208f5a <uniffi_pbcli_checksum_method_api_base@@Base+0x9c6d6>
│ │  	subs	r2, #22
│ │  	add.w	r0, r3, ip, lsl #24
│ │  	b.n	20835c <uniffi_pbcli_checksum_method_api_base@@Base+0x9bad8>
│ │  			@ <UNDEFINED> instruction: 0xffcdeaff
│ │  	add	r7, pc, #868	@ (adr r7, 208b8c <uniffi_pbcli_checksum_method_api_base@@Base+0x9c308>)
│ │ -			@ <UNDEFINED> instruction: 0xffe72997
│ │ +			@ <UNDEFINED> instruction: 0xffe729be
│ │  	vqshrun.s64	d26, <illegal reg q0.5>, #23
│ │ -	vmul.f32	q9, <illegal reg q11.5>, d15[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe729f6
│ │  	vqshl.u32	q13, <illegal reg q8.5>, #9
│ │ -			@ <UNDEFINED> instruction: 0xffe7292b
│ │ +	vqrshrn.u64	d18, q1, #25
│ │  	vsli.32	q13, <illegal reg q14.5>, #9
│ │ -	vqshl.u32	d18, d27, #7
│ │ +			@ <UNDEFINED> instruction: 0xffe72762
│ │  	vqshlu.s32	d26, d21, #9
│ │ -	vqshl.u64	q9, <illegal reg q9.5>, #39	@ 0x27
│ │ +	vqshrun.s64	d18, q5, #25
│ │  	vsli.32	d26, d13, #9
│ │ -	vqshlu.s64	q9, <illegal reg q5.5>, #39	@ 0x27
│ │ +	vabdl.u32	q9, d7, d2
│ │  	vqshl.u32	d17, d12, #9
│ │  	b.n	20837a <uniffi_pbcli_checksum_method_api_base@@Base+0x9baf6>
│ │  	movs	r0, r0
│ │  	b.n	208f00 <uniffi_pbcli_checksum_method_api_base@@Base+0x9c67c>
│ │  	movs	r5, r0
│ │  	lsrs	r0, r0, #8
│ │  	asrs	r0, r0, #12
│ │ @@ -295216,15 +295216,15 @@
│ │  	b.n	2090c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x9c842>
│ │  	subs	r2, #74	@ 0x4a
│ │  	add.w	r0, r3, r4
│ │  	b.n	208cce <uniffi_pbcli_checksum_method_api_base@@Base+0x9c44a>
│ │  	beq.n	2089b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x9c12c>
│ │  	b.n	208e28 <uniffi_pbcli_checksum_method_api_base@@Base+0x9c5a4>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r4, r5, r6, r7, r9, fp, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r3, r4, r8, r9, fp, sp, lr}
│ │  	vcvt.f16.u16	d20, d0, #23
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	208ebc <uniffi_pbcli_checksum_method_api_base@@Base+0x9c638>
│ │  	ands	r0, r0
│ │  	b.n	208ce6 <uniffi_pbcli_checksum_method_api_base@@Base+0x9c462>
│ │  	add	r1, sp, #296	@ 0x128
│ │  	add.w	r0, r3, r0
│ │ @@ -295870,19 +295870,19 @@
│ │  	movs	r4, r0
│ │  	b.n	208f6c <uniffi_pbcli_checksum_method_api_base@@Base+0x9c6e8>
│ │  	movs	r0, r0
│ │  	b.n	20926a <uniffi_pbcli_checksum_method_api_base@@Base+0x9c9e6>
│ │  	beq.n	208f98 <uniffi_pbcli_checksum_method_api_base@@Base+0x9c714>
│ │  	b.n	2093f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x9cb74>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r5, r6, r7, ip, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffe9abc9
│ │ +	ldmia.w	sp!, {r3, r8, ip, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffe9abf0
│ │  	vcvt.f32.u32	d16, d11, #23
│ │ -			@ <UNDEFINED> instruction: 0xffe74f85
│ │ -	vmull.u32	q13, d9, d13[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe74fac
│ │ +			@ <UNDEFINED> instruction: 0xffe9aa94
│ │  	vmls.f32	<illegal reg q10.5>, <illegal reg q4.5>, d3[1]
│ │  	vrsra.u64	q10, q0, #24
│ │  	movs	r5, r5
│ │  	asrs	r0, r0, #32
│ │  	b.n	2092c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x9ca42>
│ │  	movs	r0, r0
│ │  	b.n	2096ca <uniffi_pbcli_checksum_method_api_base@@Base+0x9ce46>
│ │ @@ -296154,27 +296154,27 @@
│ │  	ldmia.w	r1, {r0, r1, ip, sp}
│ │  	b.n	209568 <uniffi_pbcli_checksum_method_api_base@@Base+0x9cce4>
│ │  	movs	r0, r0
│ │  	b.n	209566 <uniffi_pbcli_checksum_method_api_base@@Base+0x9cce2>
│ │  	movs	r1, r1
│ │  	stmia.w	r1, {r0, r2, r3, r5, r7, r8, r9, sl, fp, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeaff0ad6
│ │ -	vqrdmlsh.s32	<illegal reg q13.5>, <illegal reg q3.5>, d9[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe7bf90
│ │  	vqrdmulh.s32	q13, <illegal reg q4.5>, d4[0]
│ │  	movs	r1, r5
│ │  	lsrs	r6, r1, #13
│ │  			@ <UNDEFINED> instruction: 0xffe7ccbe
│ │  	vsli.32	d29, d12, #7
│ │  	vmlsl.u32	q8, d9, d10
│ │ -			@ <UNDEFINED> instruction: 0xffe7be9d
│ │ -	vmlal.u32	q8, d25, d11
│ │ +	vqrdmlah.s32	<illegal reg q13.5>, <illegal reg q11.5>, d4[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe908b2
│ │  	vrsra.u32	d17, d18, #23
│ │  			@ <UNDEFINED> instruction: 0xffe80b0e
│ │ -			@ <UNDEFINED> instruction: 0xffe7bfa1
│ │ -			@ <UNDEFINED> instruction: 0xffe90997
│ │ +	vqrdmlsh.s32	<illegal reg q13.5>, <illegal reg q11.5>, d8[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe909be
│ │  			@ <UNDEFINED> instruction: 0xffe94bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	209740 <uniffi_pbcli_checksum_method_api_base@@Base+0x9cebc>
│ │  	movs	r0, r0
│ │  	b.n	2098cc <uniffi_pbcli_checksum_method_api_base@@Base+0x9d048>
│ │  	str	r0, [r0, r0]
│ │  	asrs	r1, r2, #22
│ │ @@ -297057,15 +297057,15 @@
│ │  	b.n	20a082 <uniffi_pbcli_checksum_method_api_base@@Base+0x9d7fe>
│ │  	str	r1, [r0, #0]
│ │  	stmia	r3!, {}
│ │  	movs	r6, r0
│ │  	b.n	209d2a <uniffi_pbcli_checksum_method_api_base@@Base+0x9d4a6>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r5, r6, r7, r9, ip, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffe7e9f1
│ │ +	vshll.u32	q15, d8, #7
│ │  	vraddhn.i64	d25, q4, q1
│ │  	vqshrun.s64	d20, q8, #25
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	209f1c <uniffi_pbcli_checksum_method_api_base@@Base+0x9d698>
│ │  	str	r0, [r0, r0]
│ │  	b.n	209d46 <uniffi_pbcli_checksum_method_api_base@@Base+0x9d4c2>
│ │  	movs	r4, r1
│ │ @@ -298814,19 +298814,19 @@
│ │  	movs	r5, r0
│ │  	b.n	20ac76 <uniffi_pbcli_checksum_method_api_base@@Base+0x9e3f2>
│ │  	ldr	r4, [pc, #448]	@ (20aaf8 <uniffi_pbcli_checksum_method_api_base@@Base+0x9e274>)
│ │  	ldmia.w	sp!, {r4, r6, r7, r8, r9, sl, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xea01e3fe
│ │  	vmull.u32	<illegal reg q9.5>, d7, d27
│ │  	vrsra.u64	d24, d31, #25
│ │ -			@ <UNDEFINED> instruction: 0xffe74bc7
│ │ +			@ <UNDEFINED> instruction: 0xffe74bee
│ │  	vsubw.u32	<illegal reg q13.5>, <illegal reg q4.5>, d20
│ │  	vsli.32	q9, <illegal reg q11.5>, #7
│ │ -	vshr.u64	<illegal reg q12.5>, q7, #25
│ │ -	vmla.i32	<illegal reg q12.5>, <illegal reg q12.5>, d13[0]
│ │ +	vaddw.u32	<illegal reg q12.5>, <illegal reg q3.5>, d5
│ │ +	vshr.u64	<illegal reg q12.5>, q10, #23
│ │  	vmlal.u32	<illegal reg q12.5>, d25, d20
│ │  	movs	r1, r5
│ │  	ldr	r4, [pc, #448]	@ (20ab24 <uniffi_pbcli_checksum_method_api_base@@Base+0x9e2a0>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	20ae84 <uniffi_pbcli_checksum_method_api_base@@Base+0x9e600>
│ │  	beq.n	20a97c <uniffi_pbcli_checksum_method_api_base@@Base+0x9e0f8>
│ │  	b.n	20ae08 <uniffi_pbcli_checksum_method_api_base@@Base+0x9e584>
│ │ @@ -299528,21 +299528,21 @@
│ │  	b.n	20b6da <uniffi_pbcli_checksum_method_api_base@@Base+0x9ee56>
│ │  	movs	r4, r2
│ │  	b.n	20b6de <uniffi_pbcli_checksum_method_api_base@@Base+0x9ee5a>
│ │  	asrs	r0, r1, #32
│ │  	b.n	20b2e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x9ea5e>
│ │  			@ <UNDEFINED> instruction: 0xffb2eaff
│ │  	adds	r6, #172	@ 0xac
│ │ -	vcvt.u32.f32	<illegal reg q13.5>, q4, #24
│ │ +	vcvt.u32.f32	<illegal reg q13.5>, <illegal reg q15.5>, #24
│ │  	vrsubhn.i64	d19, q12, q0
│ │ -			@ <UNDEFINED> instruction: 0xffe8bf2c
│ │ +	vcvt.u32.f32	<illegal reg q13.5>, <illegal reg q1.5>, #24
│ │  	vmls.f32	<illegal reg q9.5>, q12, d12[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe8be98
│ │ +			@ <UNDEFINED> instruction: 0xffe8bebf
│ │  	vmls.f32	<illegal reg q9.5>, q4, d12[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe8bdf8
│ │ +	vcvt.f32.u32	d27, d15, #24
│ │  	vcvt.f16.u16	q10, q8, #24
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	20b4e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x9ec64>
│ │  	beq.n	20afe0 <uniffi_pbcli_checksum_method_api_base@@Base+0x9e75c>
│ │  	b.n	20b46c <uniffi_pbcli_checksum_method_api_base@@Base+0x9ebe8>
│ │  	movs	r0, r0
│ │  	b.n	20b678 <uniffi_pbcli_checksum_method_api_base@@Base+0x9edf4>
│ │ @@ -301623,16 +301623,16 @@
│ │  	add.w	r0, r4, r0, lsl #20
│ │  	b.n	20c972 <uniffi_pbcli_checksum_method_api_base@@Base+0xa00ee>
│ │  	movs	r5, r0
│ │  	b.n	20c576 <uniffi_pbcli_checksum_method_api_base@@Base+0x9fcf2>
│ │  	beq.n	20c258 <uniffi_pbcli_checksum_method_api_base@@Base+0x9f9d4>
│ │  	b.n	20c6d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x9fe4c>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r5, r7, r9, ip, sp}
│ │ -	vrshr.u32	d19, d3, #23
│ │ +	ldmia.w	sp!, {r1, r2, r4, r6, r7, r9, ip, sp}
│ │ +	vrshr.u32	d19, d26, #23
│ │  			@ <UNDEFINED> instruction: 0xffe94df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	20c768 <uniffi_pbcli_checksum_method_api_base@@Base+0x9fee4>
│ │  	strh	r1, [r0, #0]
│ │  	b.n	20c592 <uniffi_pbcli_checksum_method_api_base@@Base+0x9fd0e>
│ │  	asrs	r0, r6, #10
│ │  	b.n	20bd94 <uniffi_pbcli_checksum_method_api_base@@Base+0x9f510>
│ │ @@ -301949,24 +301949,24 @@
│ │  	ldr	r1, [pc, #44]	@ (20c524 <uniffi_pbcli_checksum_method_api_base@@Base+0x9fca0>)
│ │  	add.w	r0, r4, r0
│ │  	b.n	20cb9e <uniffi_pbcli_checksum_method_api_base@@Base+0xa031a>
│ │  	lsls	r4, r4, #11
│ │  	b.n	20c00a <uniffi_pbcli_checksum_method_api_base@@Base+0x9f786>
│ │  			@ <UNDEFINED> instruction: 0xffbd1aff
│ │  			@ <UNDEFINED> instruction: 0xfff1eaff
│ │ -	adds	r1, #219	@ 0xdb
│ │ -			@ <UNDEFINED> instruction: 0xffe92f83
│ │ +	adds	r2, #2
│ │ +			@ <UNDEFINED> instruction: 0xffe92faa
│ │  	vaddl.u32	q12, d9, d0
│ │ -	vshr.u64	<illegal reg q9.5>, <illegal reg q1.5>, #25
│ │ -	vaddl.u32	<illegal reg q9.5>, d25, d27
│ │ -	vmla.i32	<illegal reg q9.5>, <illegal reg q4.5>, d11[1]
│ │ -	vqrdmlsh.s32	q9, <illegal reg q4.5>, d7[0]
│ │ -	vaddl.u32	<illegal reg q9.5>, d9, d19
│ │ -			@ <UNDEFINED> instruction: 0xffe92ffb
│ │ -	vqrdmlsh.s32	q9, <illegal reg q12.5>, d15[0]
│ │ +	vshr.u64	<illegal reg q9.5>, q13, #25
│ │ +	vshr.u64	<illegal reg q9.5>, q1, #23
│ │ +	vshr.u64	d19, d2, #23
│ │ +	vqrdmlsh.s32	q9, <illegal reg q4.5>, d14[1]
│ │ +	vmla.i32	<illegal reg q9.5>, <illegal reg q4.5>, d10[0]
│ │ +	vaddl.u32	<illegal reg q9.5>, d9, d18
│ │ +			@ <UNDEFINED> instruction: 0xffe92ff6
│ │  	vmlal.u32	q10, d9, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	20c87a <uniffi_pbcli_checksum_method_api_base@@Base+0x9fff6>
│ │  	vqrdmlah.s<illegal width 8>	q15, <illegal reg q8.5>, <illegal reg q15.5>
│ │  	movs	r0, r0
│ │  	b.n	20cbe2 <uniffi_pbcli_checksum_method_api_base@@Base+0xa035e>
│ │  	asrs	r0, r0, #32
│ │ @@ -302229,25 +302229,25 @@
│ │  	b.n	20cabe <uniffi_pbcli_checksum_method_api_base@@Base+0xa023a>
│ │  	beq.n	20c7b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x9ff2c>
│ │  	b.n	20cc18 <uniffi_pbcli_checksum_method_api_base@@Base+0xa0394>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, ip, lr}
│ │  	b.n	20ceca <uniffi_pbcli_checksum_method_api_base@@Base+0xa0646>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │ -	cmp	r6, #163	@ 0xa3
│ │ +	cmp	r6, #202	@ 0xca
│ │  	vqshlu.s32	d31, d11, #9
│ │ -	vcvt.u16.f16	q9, <illegal reg q5.5>, #25
│ │ +			@ <UNDEFINED> instruction: 0xffe72d82
│ │  	vsri.64	<illegal reg q15.5>, <illegal reg q1.5>, #23
│ │  	vaddw.u32	q8, <illegal reg q11.5>, d4
│ │  	movs	r0, r0
│ │ -	cmp	r5, #43	@ 0x2b
│ │ +	cmp	r5, #82	@ 0x52
│ │  	vraddhn.i64	d31, <illegal reg q12.5>, <illegal reg q9.5>
│ │ -			@ <UNDEFINED> instruction: 0xffe72d9b
│ │ +	vqrdmulh.s32	q9, <illegal reg q11.5>, d2[0]
│ │  	vsli.32	d31, d3, #9
│ │ -	vqdmulh.s32	q9, <illegal reg q11.5>, d3[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe72d0a
│ │  	vsri.32	<illegal reg q15.5>, <illegal reg q5.5>, #23
│ │  			@ <UNDEFINED> instruction: 0xffe74df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	20ccdc <uniffi_pbcli_checksum_method_api_base@@Base+0xa0458>
│ │  	str	r2, [r0, r0]
│ │  	b.n	20cb06 <uniffi_pbcli_checksum_method_api_base@@Base+0xa0282>
│ │  	str	r1, [r0, #0]
│ │ @@ -302500,17 +302500,17 @@
│ │  	add.w	r0, r0, r0, lsl #24
│ │  	b.n	20d126 <uniffi_pbcli_checksum_method_api_base@@Base+0xa08a2>
│ │  	movs	r6, r0
│ │  	b.n	20cd2a <uniffi_pbcli_checksum_method_api_base@@Base+0xa04a6>
│ │  	beq.n	20ca24 <uniffi_pbcli_checksum_method_api_base@@Base+0xa01a0>
│ │  	b.n	20ce84 <uniffi_pbcli_checksum_method_api_base@@Base+0xa0600>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r8, r9, fp, sp}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r6, r8, r9, fp, sp}
│ │  	vsra.u32	q11, q7, #23
│ │ -			@ <UNDEFINED> instruction: 0xffe82adb
│ │ +			@ <UNDEFINED> instruction: 0xffe82b02
│ │  	vaddw.u32	q11, <illegal reg q4.5>, d2
│ │  	vqshrun.s64	d20, q8, #24
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	20cf24 <uniffi_pbcli_checksum_method_api_base@@Base+0xa06a0>
│ │  	movs	r0, r0
│ │  	b.n	20d0ae <uniffi_pbcli_checksum_method_api_base@@Base+0xa082a>
│ │  	movs	r2, r1
│ │ @@ -302622,15 +302622,15 @@
│ │  	b.n	20d246 <uniffi_pbcli_checksum_method_api_base@@Base+0xa09c2>
│ │  	movs	r0, #5
│ │  	b.n	20ce4a <uniffi_pbcli_checksum_method_api_base@@Base+0xa05c6>
│ │  	adds	r3, #103	@ 0x67
│ │  	b.n	20d10e <uniffi_pbcli_checksum_method_api_base@@Base+0xa088a>
│ │  	ldr	r0, [pc, #192]	@ (20cbd0 <uniffi_pbcli_checksum_method_api_base@@Base+0xa034c>)
│ │  	ldmia.w	sp!, {r0, r3, r7, r8, lr}
│ │ -	and.w	r9, r4, r7, asr #10
│ │ +	and.w	r9, r4, lr, lsl #11
│ │  			@ <UNDEFINED> instruction: 0xffe94df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	20d03c <uniffi_pbcli_checksum_method_api_base@@Base+0xa07b8>
│ │  	svc	202	@ 0xca
│ │  	b.n	20cfc0 <uniffi_pbcli_checksum_method_api_base@@Base+0xa073c>
│ │  	ldr	r0, [r4, r2]
│ │  	b.n	20c64a <uniffi_pbcli_checksum_method_api_base@@Base+0x9fdc6>
│ │ @@ -303462,19 +303462,19 @@
│ │  	str	r1, [r0, r0]
│ │  	b.n	20d96e <uniffi_pbcli_checksum_method_api_base@@Base+0xa10ea>
│ │  	lsls	r0, r5, #10
│ │  	b.n	20cd52 <uniffi_pbcli_checksum_method_api_base@@Base+0xa04ce>
│ │  	lsls	r4, r7, #29
│ │  	b.n	20cd3e <uniffi_pbcli_checksum_method_api_base@@Base+0xa04ba>
│ │  			@ <UNDEFINED> instruction: 0xffa2eaff
│ │ -	movs	r4, #103	@ 0x67
│ │ +	movs	r4, #142	@ 0x8e
│ │  	vsli.32	q10, <illegal reg q10.5>, #9
│ │ -			@ <UNDEFINED> instruction: 0xffe72343
│ │ +			@ <UNDEFINED> instruction: 0xffe7236a
│ │  	vsri.32	q10, <illegal reg q0.5>, #23
│ │ -	vsubl.u32	q9, d23, d3
│ │ +	vsubl.u32	q9, d23, d26
│ │  	vrsra.u64	d20, d1, #23
│ │  	vaddl.u32	q9, d7, d1
│ │  	b.n	20d996 <uniffi_pbcli_checksum_method_api_base@@Base+0xa1112>
│ │  			@ <UNDEFINED> instruction: 0xffffeaff
│ │  	ldr	r5, [pc, #960]	@ (20d61c <uniffi_pbcli_checksum_method_api_base@@Base+0xa0d98>)
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	20d77c <uniffi_pbcli_checksum_method_api_base@@Base+0xa0ef8>
│ │ @@ -304614,18 +304614,18 @@
│ │  	adds	r0, #0
│ │  	b.n	20e352 <uniffi_pbcli_checksum_method_api_base@@Base+0xa1ace>
│ │  	str	r0, [r0, r0]
│ │  	b.n	20e356 <uniffi_pbcli_checksum_method_api_base@@Base+0xa1ad2>
│ │  	movs	r4, #158	@ 0x9e
│ │  			@ <UNDEFINED> instruction: 0xeb01ff8b
│ │  			@ <UNDEFINED> instruction: 0xeaffa61b
│ │ -			@ <UNDEFINED> instruction: 0xffe6d340
│ │ +			@ <UNDEFINED> instruction: 0xffe6d367
│ │  	vmlsl.u32	q13, d24, d11[1]
│ │  	vmlsl.u32	q13, d6, d3[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe6d368
│ │ +	vsubw.u32	<illegal reg q14.5>, q11, d15
│ │  			@ <UNDEFINED> instruction: 0xffe84f26
│ │  			@ <UNDEFINED> instruction: 0xffe84bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	20e158 <uniffi_pbcli_checksum_method_api_base@@Base+0xa18d4>
│ │  	beq.n	20dd20 <uniffi_pbcli_checksum_method_api_base@@Base+0xa149c>
│ │  	b.n	20e0dc <uniffi_pbcli_checksum_method_api_base@@Base+0xa1858>
│ │  	strb	r0, [r0, #0]
│ │ @@ -305054,23 +305054,23 @@
│ │  	movs	r4, #30
│ │  	add.w	r0, r3, r6
│ │  	b.n	20e342 <uniffi_pbcli_checksum_method_api_base@@Base+0xa1abe>
│ │  	beq.n	20e03c <uniffi_pbcli_checksum_method_api_base@@Base+0xa17b8>
│ │  	b.n	20e49c <uniffi_pbcli_checksum_method_api_base@@Base+0xa1c18>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r1, r2, r4, r7, r9, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffe6cfdb
│ │ -	vrshr.u64	<illegal reg q11.5>, q6, #24
│ │ +	vaddl.u32	<illegal reg q14.5>, d6, d2
│ │ +	vsubw.u32	<illegal reg q11.5>, q4, d3
│ │  	vmls.i32	q13, <illegal reg q4.5>, d12[1]
│ │  	vabdl.u32	<illegal reg q9.5>, d22, d29
│ │  	vqshlu.s64	q8, q13, #39	@ 0x27
│ │  	vmlal.u32	q13, d24, d15[0]
│ │ -	vshr.u32	d29, d7, #26
│ │ +	vshr.u32	d29, d30, #26
│ │  	vrshr.u32	q13, <illegal reg q3.5>, #24
│ │ -			@ <UNDEFINED> instruction: 0xffe6cf9f
│ │ +	vqrdmlsh.s32	q14, q11, d6[0]
│ │  			@ <UNDEFINED> instruction: 0xffe84df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	20e554 <uniffi_pbcli_checksum_method_api_base@@Base+0xa1cd0>
│ │  	beq.n	20df9c <uniffi_pbcli_checksum_method_api_base@@Base+0xa1718>
│ │  	b.n	20e4d8 <uniffi_pbcli_checksum_method_api_base@@Base+0xa1c54>
│ │  	ands	r0, r0
│ │  	b.n	20e382 <uniffi_pbcli_checksum_method_api_base@@Base+0xa1afe>
│ │ @@ -305211,15 +305211,15 @@
│ │  	b.n	20e8a2 <uniffi_pbcli_checksum_method_api_base@@Base+0xa201e>
│ │  	movs	r5, r0
│ │  	b.n	20e4a6 <uniffi_pbcli_checksum_method_api_base@@Base+0xa1c22>
│ │  	beq.n	20e198 <uniffi_pbcli_checksum_method_api_base@@Base+0xa1914>
│ │  	b.n	20e600 <uniffi_pbcli_checksum_method_api_base@@Base+0xa1d7c>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r1, r2, r4, r6, sl, ip, sp}
│ │ -			@ <UNDEFINED> instruction: 0xffe7ced1
│ │ +			@ <UNDEFINED> instruction: 0xffe7cef8
│ │  			@ <UNDEFINED> instruction: 0xffe84ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	20e698 <uniffi_pbcli_checksum_method_api_base@@Base+0xa1e14>
│ │  	beq.n	20e1e8 <uniffi_pbcli_checksum_method_api_base@@Base+0xa1964>
│ │  	b.n	20e61c <uniffi_pbcli_checksum_method_api_base@@Base+0xa1d98>
│ │  	strb	r0, [r2, #0]
│ │  	b.n	20dcbc <uniffi_pbcli_checksum_method_api_base@@Base+0xa1438>
│ │ @@ -305482,17 +305482,17 @@
│ │  	b.n	20e6fe <uniffi_pbcli_checksum_method_api_base@@Base+0xa1e7a>
│ │  	beq.n	20e3f8 <uniffi_pbcli_checksum_method_api_base@@Base+0xa1b74>
│ │  	b.n	20e858 <uniffi_pbcli_checksum_method_api_base@@Base+0xa1fd4>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r5, r6, sp, pc}
│ │  	vsra.u64	d29, d29, #26
│ │  	vshr.u32	d26, d3, #26
│ │ -	vmlsl.u32	q9, d22, d13[0]
│ │ +	vqshlu.s64	q9, q10, #38	@ 0x26
│ │  	vqshl.u64	q10, <illegal reg q3.5>, #41	@ 0x29
│ │ -	vmull.u32	q14, d23, d5
│ │ +	vmull.u32	q14, d23, d28
│ │  	vrshr.u32	<illegal reg q9.5>, q15, #24
│ │  	vqshl.u32	q10, q13, #7
│ │  			@ <UNDEFINED> instruction: 0xffe89e93
│ │  	vqrdmlsh.s32	q14, q11, d1[1]
│ │  	vcvt.f32.u32	<illegal reg q12.5>, <illegal reg q5.5>, #26
│ │  	vshr.u32	q8, q12, #26
│ │  	b.n	20ea96 <uniffi_pbcli_checksum_method_api_base@@Base+0xa2212>
│ │ @@ -306469,15 +306469,15 @@
│ │  	b.n	20f36a <uniffi_pbcli_checksum_method_api_base@@Base+0xa2ae6>
│ │  	movs	r0, r0
│ │  	b.n	20f2dc <uniffi_pbcli_checksum_method_api_base@@Base+0xa2a58>
│ │  			@ <UNDEFINED> instruction: 0xffce1aff
│ │  			@ <UNDEFINED> instruction: 0xffd3eaff
│ │  	rors	r3, r1
│ │  	vmul.i32	q12, <illegal reg q11.5>, d7[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe74d96
│ │ +			@ <UNDEFINED> instruction: 0xffe74dbd
│ │  	vcvt.f16.u16	d20, d0, #23
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	20f164 <uniffi_pbcli_checksum_method_api_base@@Base+0xa28e0>
│ │  	beq.n	20ec5c <uniffi_pbcli_checksum_method_api_base@@Base+0xa23d8>
│ │  	b.n	20f0e8 <uniffi_pbcli_checksum_method_api_base@@Base+0xa2864>
│ │  	adds	r0, #4
│ │  	b.n	20e772 <uniffi_pbcli_checksum_method_api_base@@Base+0xa1eee>
│ │ @@ -307120,15 +307120,15 @@
│ │  	subs	r0, r6, #6
│ │  	add.w	r0, r3, r5
│ │  	b.n	20f4fa <uniffi_pbcli_checksum_method_api_base@@Base+0xa2c76>
│ │  	beq.n	20f1f4 <uniffi_pbcli_checksum_method_api_base@@Base+0xa2970>
│ │  	b.n	20f654 <uniffi_pbcli_checksum_method_api_base@@Base+0xa2dd0>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r9, fp, sp, pc}
│ │ -	vqshrun.s64	d22, q0, #26
│ │ +	vqshrun.s64	d22, <illegal reg q11.5>, #26
│ │  			@ <UNDEFINED> instruction: 0xffe8ab1b
│ │  	vqshl.u32	<illegal reg q11.5>, q0, #6
│ │  	vshll.u32	q13, d31, #9
│ │  	vmull.u32	q13, d6, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffe64df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	20f6fc <uniffi_pbcli_checksum_method_api_base@@Base+0xa2e78>
│ │ @@ -307272,16 +307272,16 @@
│ │  	beq.n	20f338 <uniffi_pbcli_checksum_method_api_base@@Base+0xa2ab4>
│ │  	b.n	20f7a0 <uniffi_pbcli_checksum_method_api_base@@Base+0xa2f1c>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r7, r8, fp, sp, pc}
│ │  	vshr.u64	q8, q8, #26
│ │  	movs	r0, r0
│ │  	add	r0, sp, #956	@ 0x3bc
│ │ -	vqrdmulh.s32	<illegal reg q10.5>, q3, d1[1]
│ │ -	vshr.u32	<illegal reg q12.5>, <illegal reg q1.5>, #23
│ │ +			@ <UNDEFINED> instruction: 0xffe65d88
│ │ +	vshr.u32	<illegal reg q12.5>, q13, #23
│ │  	vqshrn.u64	d26, <illegal reg q13.5>, #24
│ │  	vqshrn.u64	d26, <illegal reg q5.5>, #26
│ │  			@ <UNDEFINED> instruction: 0xffe6a8bb
│ │  			@ <UNDEFINED> instruction: 0xffe64bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	20f850 <uniffi_pbcli_checksum_method_api_base@@Base+0xa2fcc>
│ │  	beq.n	20f3b8 <uniffi_pbcli_checksum_method_api_base@@Base+0xa2b34>
│ │ @@ -309093,35 +309093,35 @@
│ │  	b.n	2109f2 <uniffi_pbcli_checksum_method_api_base@@Base+0xa416e>
│ │  	movs	r1, r1
│ │  	b.n	2105f6 <uniffi_pbcli_checksum_method_api_base@@Base+0xa3d72>
│ │  	asrs	r0, r5, #32
│ │  	b.n	2109fa <uniffi_pbcli_checksum_method_api_base@@Base+0xa4176>
│ │  	mrc2	10, 7, lr, cr10, cr15, {7}	@ <UNPREDICTABLE>
│ │  	ldr	r5, [sp, #492]	@ 0x1ec
│ │ -	vsubl.u32	<illegal reg q10.5>, d6, d2
│ │ +	vsubl.u32	<illegal reg q10.5>, d6, d25
│ │  			@ <UNDEFINED> instruction: 0xffe99d23
│ │ -	vaddw.u32	<illegal reg q10.5>, q11, d26
│ │ +	vsra.u64	<illegal reg q10.5>, <illegal reg q0.5>, #26
│ │  			@ <UNDEFINED> instruction: 0xffe99b37
│ │ -			@ <UNDEFINED> instruction: 0xffe64fbe
│ │ +	vqrdmlsh.s32	q10, q11, d5[1]
│ │  	vmlsl.u32	<illegal reg q12.5>, d25, d23
│ │ -			@ <UNDEFINED> instruction: 0xffe64f2e
│ │ +	vcvt.u32.f32	q10, <illegal reg q2.5>, #26
│ │  			@ <UNDEFINED> instruction: 0xffe99a77
│ │ -			@ <UNDEFINED> instruction: 0xffe64efe
│ │ +			@ <UNDEFINED> instruction: 0xffe64f25
│ │  			@ <UNDEFINED> instruction: 0xffe999b7
│ │ -	vcvt.f32.u32	d20, d30, #26
│ │ +	vqrdmlah.s32	q10, q3, d5[1]
│ │  			@ <UNDEFINED> instruction: 0xffe99b53
│ │ -			@ <UNDEFINED> instruction: 0xffe64fda
│ │ +	vaddl.u32	<illegal reg q10.5>, d6, d1
│ │  			@ <UNDEFINED> instruction: 0xffe99b0b
│ │ -			@ <UNDEFINED> instruction: 0xffe64f92
│ │ +			@ <UNDEFINED> instruction: 0xffe64fb9
│ │  	vmlsl.u32	<illegal reg q12.5>, d9, d23
│ │ -	vmull.p64	q10, d22, d30
│ │ +			@ <UNDEFINED> instruction: 0xffe64ed5
│ │  	vmul.f32	<illegal reg q12.5>, <illegal reg q12.5>, d7[1]
│ │ -	vqrdmlah.s32	q10, q3, d14[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe64e95
│ │  	vqshrn.u64	d25, <illegal reg q1.5>, #23
│ │ -			@ <UNDEFINED> instruction: 0xffe64d9a
│ │ +	vqrdmulh.s32	q10, q11, d1[0]
│ │  	vqshrun.s64	d20, q8, #23
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	210838 <uniffi_pbcli_checksum_method_api_base@@Base+0xa3fb4>
│ │  	str	r1, [r0, r0]
│ │  	b.n	210662 <uniffi_pbcli_checksum_method_api_base@@Base+0xa3dde>
│ │  	asrs	r4, r1, #3
│ │  	b.n	20fe64 <uniffi_pbcli_checksum_method_api_base@@Base+0xa35e0>
│ │ @@ -310075,17 +310075,17 @@
│ │  			@ <UNDEFINED> instruction: 0xfff91aff
│ │  			@ <UNDEFINED> instruction: 0xffebeaff
│ │  	str	r2, [sp, #508]	@ 0x1fc
│ │  	vsra.u64	<illegal reg q12.5>, <illegal reg q15.5>, #26
│ │  	vqrdmlsh.s32	<illegal reg q10.5>, q3, d14[1]
│ │  	vcvt.u32.f32	d21, d26, #23
│ │  	vmla.f32	<illegal reg q12.5>, <illegal reg q12.5>, d15[0]
│ │ -	vmul.f32	<illegal reg q11.5>, q3, d3[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe6798a
│ │  	vsra.u64	d25, d11, #24
│ │ -			@ <UNDEFINED> instruction: 0xffe6792f
│ │ +	vqrshrn.u64	d23, q3, #26
│ │  			@ <UNDEFINED> instruction: 0xffe84ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	21108c <uniffi_pbcli_checksum_method_api_base@@Base+0xa4808>
│ │  	beq.n	210b9c <uniffi_pbcli_checksum_method_api_base@@Base+0xa4318>
│ │  	b.n	211010 <uniffi_pbcli_checksum_method_api_base@@Base+0xa478c>
│ │  	ldrsb	r4, [r5, r2]
│ │  	b.n	21069a <uniffi_pbcli_checksum_method_api_base@@Base+0xa3e16>
│ │ @@ -311312,15 +311312,15 @@
│ │  	str	r4, [r3, #0]
│ │  	b.n	211114 <uniffi_pbcli_checksum_method_api_base@@Base+0xa4890>
│ │  	movs	r0, r0
│ │  	b.n	211c7e <uniffi_pbcli_checksum_method_api_base@@Base+0xa53fa>
│ │  	str	r0, [sp, #20]
│ │  	lsls	r0, r0, #12
│ │  			@ <UNDEFINED> instruction: 0xff95eaff
│ │ -	strb	r3, [r6, #2]
│ │ +	strb	r2, [r3, #3]
│ │  	vaddl.u32	<illegal reg q14.5>, d24, d31
│ │  	vqshl.u32	d24, d23, #7
│ │  	vqshlu.s32	d24, d31, #6
│ │  	vrsubhn.i64	d24, q3, <illegal reg q11.5>
│ │  	vrsubhn.i64	d24, q11, <illegal reg q1.5>
│ │  			@ <UNDEFINED> instruction: 0xffe6874f
│ │  	vqshrun.s64	d20, q8, #26
│ │ @@ -314587,15 +314587,15 @@
│ │  	b.n	2136a4 <uniffi_pbcli_checksum_method_api_base@@Base+0xa6e20>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {sp, lr}
│ │  	b.n	213956 <uniffi_pbcli_checksum_method_api_base@@Base+0xa70d2>
│ │  			@ <UNDEFINED> instruction: 0xfff2eaff
│ │  	ldr	r2, [sp, #104]	@ 0x68
│ │  	vaddw.u32	<illegal reg q8.5>, q11, d0
│ │ -	vcvt.u16.f16	d26, d24, #24
│ │ +	vcvt.u16.f16	q13, <illegal reg q7.5>, #24
│ │  			@ <UNDEFINED> instruction: 0xffe84bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	213748 <uniffi_pbcli_checksum_method_api_base@@Base+0xa6ec4>
│ │  	beq.n	213250 <uniffi_pbcli_checksum_method_api_base@@Base+0xa69cc>
│ │  	b.n	2136cc <uniffi_pbcli_checksum_method_api_base@@Base+0xa6e48>
│ │  	movs	r0, r0
│ │  	b.n	2138dc <uniffi_pbcli_checksum_method_api_base@@Base+0xa7058>
│ │ @@ -316336,45 +316336,45 @@
│ │  	movs	r0, #2
│ │  	b.n	214260 <uniffi_pbcli_checksum_method_api_base@@Base+0xa79dc>
│ │  	vpmin.u<illegal width 64>	q15, q9, <illegal reg q15.5>
│ │  	ldrb	r3, [r2, r3]
│ │  	vqrdmlah.s32	<illegal reg q10.5>, q11, d15[1]
│ │  	vshr.u64	d31, d7, #26
│ │  			@ <UNDEFINED> instruction: 0xffe65d0f
│ │ -			@ <UNDEFINED> instruction: 0xffe61b10
│ │ +			@ <UNDEFINED> instruction: 0xffe61b37
│ │  	vcvt.f32.u32	<illegal reg q10.5>, <illegal reg q11.5>, #24
│ │ -	vqdmulh.s32	<illegal reg q10.5>, q11, d12[1]
│ │ +	vcvt.u16.f16	d21, d3, #26
│ │  	vmull.u32	<illegal reg q10.5>, d24, d27
│ │ -	vmlsl.u32	<illegal reg q8.5>, d22, d28
│ │ +			@ <UNDEFINED> instruction: 0xffe61ad3
│ │  	vmull.p64	<illegal reg q10.5>, d8, d31
│ │  	vshr.u32	d31, d2, #26
│ │  	vmull.u32	<illegal reg q10.5>, d6, d19
│ │ -	vmlsl.u32	<illegal reg q8.5>, d6, d20
│ │ +	vmull.u32	<illegal reg q8.5>, d6, d11[0]
│ │  	vrshr.u32	<illegal reg q12.5>, q9, #24
│ │  	vmull.u32	<illegal reg q10.5>, d7, d7
│ │ -	vmlsl.u32	<illegal reg q8.5>, d6, d8
│ │ +	vmlsl.u32	<illegal reg q8.5>, d6, d31
│ │  			@ <UNDEFINED> instruction: 0xffe85daf
│ │  	vaddl.u32	<illegal reg q12.5>, d6, d19
│ │  			@ <UNDEFINED> instruction: 0xffe65beb
│ │ -	vmul.f32	<illegal reg q8.5>, q11, d12[1]
│ │ -	vsubl.u32	<illegal reg q8.5>, d8, d10
│ │ +	vshll.u32	<illegal reg q8.5>, d3, #6
│ │ +	vrshr.u32	d17, d17, #24
│ │  			@ <UNDEFINED> instruction: 0xffe97be7
│ │  	vmull.u32	<illegal reg q10.5>, d23, d15[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe618d0
│ │ +			@ <UNDEFINED> instruction: 0xffe618f7
│ │  			@ <UNDEFINED> instruction: 0xffe85d2b
│ │ -			@ <UNDEFINED> instruction: 0xffe61b2c
│ │ +			@ <UNDEFINED> instruction: 0xffe61b53
│ │  			@ <UNDEFINED> instruction: 0xffe8beb6
│ │  			@ <UNDEFINED> instruction: 0xffe65ab3
│ │ -			@ <UNDEFINED> instruction: 0xffe618b4
│ │ -	vmlsl.u32	<illegal reg q10.5>, d8, d28
│ │ +			@ <UNDEFINED> instruction: 0xffe618db
│ │ +			@ <UNDEFINED> instruction: 0xffe85a53
│ │  			@ <UNDEFINED> instruction: 0xffe85a97
│ │ -			@ <UNDEFINED> instruction: 0xffe61898
│ │ +			@ <UNDEFINED> instruction: 0xffe618bf
│ │  	vraddhn.i64	d26, q12, <illegal reg q5.5>
│ │  			@ <UNDEFINED> instruction: 0xffe75a7b
│ │ -	vqrshrun.s64	d17, q14, #26
│ │ +	vmlal.u32	<illegal reg q8.5>, d22, d19
│ │  	vcvt.f16.u16	<illegal reg q10.5>, <illegal reg q13.5>, #24
│ │  			@ <UNDEFINED> instruction: 0xffe64ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2146f8 <uniffi_pbcli_checksum_method_api_base@@Base+0xa7e74>
│ │  	beq.n	214208 <uniffi_pbcli_checksum_method_api_base@@Base+0xa7984>
│ │  	b.n	21467c <uniffi_pbcli_checksum_method_api_base@@Base+0xa7df8>
│ │  	str	r0, [sp, #0]
│ │ @@ -317484,58 +317484,58 @@
│ │  	b.n	215296 <uniffi_pbcli_checksum_method_api_base@@Base+0xa8a12>
│ │  	lsrs	r7, r0, #5
│ │  	add.w	r0, r3, r1, lsl #16
│ │  	b.n	21529e <uniffi_pbcli_checksum_method_api_base@@Base+0xa8a1a>
│ │  	mrc2	10, 2, lr, cr3, cr15, {7}	@ <UNPREDICTABLE>
│ │  	ldrsb	r7, [r1, r5]
│ │  			@ <UNDEFINED> instruction: 0xffe65997
│ │ -			@ <UNDEFINED> instruction: 0xffe66cf0
│ │ +	vcvt.u16.f16	d22, d7, #26
│ │  	vabdl.u32	<illegal reg q10.5>, d24, d11
│ │ -	vmull.p64	<illegal reg q14.5>, d6, d30
│ │ +	vcvt.f32.u32	<illegal reg q14.5>, <illegal reg q2.5>, #26
│ │  			@ <UNDEFINED> instruction: 0xffe85903
│ │  			@ <UNDEFINED> instruction: 0xffe6bafa
│ │  	vabdl.u32	<illegal reg q10.5>, d7, d23
│ │ -	vqrdmulh.s32	<illegal reg q14.5>, q11, d10[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe6ddf1
│ │  			@ <UNDEFINED> instruction: 0xffe85897
│ │  	vaddw.u32	q8, q11, d3
│ │  	vrsubhn.i64	d21, <illegal reg q3.5>, <illegal reg q11.5>
│ │ -	vqdmulh.s32	<illegal reg q14.5>, q11, d10[0]
│ │ -	vqshlu.s32	d31, d11, #8
│ │ +			@ <UNDEFINED> instruction: 0xffe6dcf1
│ │ +	vmlsl.u32	<illegal reg q15.5>, d8, d2[0]
│ │  	vrsubhn.i64	d21, q4, <illegal reg q5.5>
│ │ -	vmull.u32	<illegal reg q14.5>, d22, d30
│ │ +			@ <UNDEFINED> instruction: 0xffe6dcd5
│ │  	vqshrun.s64	d23, <illegal reg q7.5>, #24
│ │  			@ <UNDEFINED> instruction: 0xffe757cb
│ │  	vqshl.u64	d21, d19, #38	@ 0x26
│ │  	vcvt.u32.f32	d31, d9, #26
│ │  	vsli.64	d21, d23, #38	@ 0x26
│ │  	vsli.64	d21, d15, #38	@ 0x26
│ │ -	vmull.p64	q13, d6, d2
│ │ +	vmull.p64	q13, d6, d25
│ │  	vsli.32	d21, d31, #8
│ │  	vabal.u32	<illegal reg q10.5>, d6, d23
│ │ -	vabal.u32	q14, d22, d2
│ │ +	vabal.u32	q14, d22, d25
│ │  	vmls.i32	<illegal reg q10.5>, q12, d7[0]
│ │  	vraddhn.i64	d21, q11, <illegal reg q15.5>
│ │  	vqdmulh.s32	q11, q3, d5[0]
│ │  	vmls.i32	<illegal reg q10.5>, q3, d15[0]
│ │  	vsri.32	d21, d23, #26
│ │  	vcvt.f16.u16	d28, d31, #26
│ │  	vrsra.u64	<illegal reg q10.5>, <illegal reg q3.5>, #25
│ │  	vrsra.u64	d21, d31, #26
│ │  	vqshlu.s32	d24, d22, #6
│ │  	vrsra.u32	<illegal reg q10.5>, <illegal reg q5.5>, #26
│ │  	vsubw.u32	<illegal reg q11.5>, q3, d27
│ │  	vsubl.u32	<illegal reg q10.5>, d7, d7
│ │ -	vmlal.u32	<illegal reg q14.5>, d22, d26
│ │ +			@ <UNDEFINED> instruction: 0xffe6d8d1
│ │  	vsli.64	<illegal reg q13.5>, q5, #40	@ 0x28
│ │  	vmla.f32	<illegal reg q10.5>, q11, d11[1]
│ │ -	vmlal.u32	<illegal reg q14.5>, d22, d14
│ │ +			@ <UNDEFINED> instruction: 0xffe6d8b5
│ │  	vsra.u64	d21, d19, #24
│ │ -	vqrshrun.s64	d29, q3, #26
│ │ +	vqrshrun.s64	d29, <illegal reg q14.5>, #26
│ │  	vshr.u32	<illegal reg q10.5>, <illegal reg q13.5>, #24
│ │ -	vqshl.u32	d29, d14, #6
│ │ +			@ <UNDEFINED> instruction: 0xffe6d745
│ │  	vqshlu.s64	<illegal reg q10.5>, <illegal reg q11.5>, #40	@ 0x28
│ │  	vcvt.f16.u16	q10, q8, #26
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	215140 <uniffi_pbcli_checksum_method_api_base@@Base+0xa88bc>
│ │  	ands	r1, r0
│ │  	b.n	214f6a <uniffi_pbcli_checksum_method_api_base@@Base+0xa86e6>
│ │  	asrs	r4, r1, #3
│ │ @@ -317630,15 +317630,15 @@
│ │  	ldmia.w	sp!, {r1, r2, r5, r6, r8, r9, sl, fp}
│ │  	b.n	215436 <uniffi_pbcli_checksum_method_api_base@@Base+0xa8bb2>
│ │  	movs	r0, r0
│ │  	b.n	214806 <uniffi_pbcli_checksum_method_api_base@@Base+0xa7f82>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r3, r5, r6, r7, r8, sl, lr, pc}
│ │  	vraddhn.i64	d24, <illegal reg q3.5>, q6
│ │ -	vqrdmulh.s32	q8, <illegal reg q3.5>, d4[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe70d8b
│ │  			@ <UNDEFINED> instruction: 0xffe833e7
│ │  	vqrdmlsh.s32	<illegal reg q11.5>, q11, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffe64df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	215234 <uniffi_pbcli_checksum_method_api_base@@Base+0xa89b0>
│ │  	beq.n	214d3c <uniffi_pbcli_checksum_method_api_base@@Base+0xa84b8>
│ │  	b.n	2151b8 <uniffi_pbcli_checksum_method_api_base@@Base+0xa8934>
│ │ @@ -318074,28 +318074,28 @@
│ │  	b.n	21581e <uniffi_pbcli_checksum_method_api_base@@Base+0xa8f9a>
│ │  	lsls	r5, r4, #31
│ │  	add.w	r0, r3, r5
│ │  	b.n	215426 <uniffi_pbcli_checksum_method_api_base@@Base+0xa8ba2>
│ │  	beq.n	215120 <uniffi_pbcli_checksum_method_api_base@@Base+0xa889c>
│ │  	b.n	215580 <uniffi_pbcli_checksum_method_api_base@@Base+0xa8cfc>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r6, r9}
│ │ +	ldmia.w	sp!, {r1, r3, r5, r6, r9}
│ │  	vshr.u32	d27, d20, #23
│ │ -	vmla.i32	q11, q11, d5[0]
│ │ +	vmla.i32	q11, q11, d12[1]
│ │  	vmull.p64	q13, d8, d28
│ │ -			@ <UNDEFINED> instruction: 0xffe65ebd
│ │ +	vqrdmlah.s32	<illegal reg q10.5>, q11, d4[1]
│ │  	vqshlu.s64	<illegal reg q12.5>, q4, #40	@ 0x28
│ │  	vsubw.u32	<illegal reg q9.5>, q3, d0
│ │  			@ <UNDEFINED> instruction: 0xffe61ad4
│ │ -			@ <UNDEFINED> instruction: 0xffe977cb
│ │ +	vqshl.u64	<illegal reg q11.5>, q9, #41	@ 0x29
│ │  	vmlsl.u32	<illegal reg q8.5>, d24, d20
│ │  	vsli.32	q9, <illegal reg q0.5>, #9
│ │ -	vrsra.u64	d19, d4, #25
│ │ +	vrsra.u64	d19, d27, #25
│ │  	vmull.p64	q13, d24, d0
│ │ -	vcvt.u32.f32	d21, d1, #26
│ │ +	vcvt.u32.f32	d21, d24, #26
│ │  			@ <UNDEFINED> instruction: 0xffe84df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	215648 <uniffi_pbcli_checksum_method_api_base@@Base+0xa8dc4>
│ │  	beq.n	215170 <uniffi_pbcli_checksum_method_api_base@@Base+0xa88ec>
│ │  	b.n	2155cc <uniffi_pbcli_checksum_method_api_base@@Base+0xa8d48>
│ │  	ands	r0, r0
│ │  	b.n	215476 <uniffi_pbcli_checksum_method_api_base@@Base+0xa8bf2>
│ │ @@ -318174,15 +318174,15 @@
│ │  	lsls	r0, r6, #28
│ │  	add.w	r0, r1, r5
│ │  	b.n	215516 <uniffi_pbcli_checksum_method_api_base@@Base+0xa8c92>
│ │  	beq.n	215208 <uniffi_pbcli_checksum_method_api_base@@Base+0xa8984>
│ │  	b.n	215670 <uniffi_pbcli_checksum_method_api_base@@Base+0xa8dec>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r2, r3, r4, r5, r8, sl, fp, sp, pc}
│ │ -	vqrdmulh.s32	<illegal reg q10.5>, q11, d2[1]
│ │ +	vmull.p64	<illegal reg q10.5>, d6, d9
│ │  			@ <UNDEFINED> instruction: 0xffe848f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	215708 <uniffi_pbcli_checksum_method_api_base@@Base+0xa8e84>
│ │  	beq.n	215230 <uniffi_pbcli_checksum_method_api_base@@Base+0xa89ac>
│ │  	b.n	21568c <uniffi_pbcli_checksum_method_api_base@@Base+0xa8e08>
│ │  	ands	r0, r0
│ │  	b.n	215536 <uniffi_pbcli_checksum_method_api_base@@Base+0xa8cb2>
│ │ @@ -318255,15 +318255,15 @@
│ │  	add.w	r0, r1, r5
│ │  	b.n	2155c6 <uniffi_pbcli_checksum_method_api_base@@Base+0xa8d42>
│ │  	beq.n	2152a8 <uniffi_pbcli_checksum_method_api_base@@Base+0xa8a24>
│ │  	b.n	215720 <uniffi_pbcli_checksum_method_api_base@@Base+0xa8e9c>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, ip}
│ │  	vmull.u32	q13, d25, d12
│ │ -	vcvt.u16.f16	d21, d18, #26
│ │ +	vcvt.u16.f16	<illegal reg q10.5>, <illegal reg q4.5>, #26
│ │  			@ <UNDEFINED> instruction: 0xffe84ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2157bc <uniffi_pbcli_checksum_method_api_base@@Base+0xa8f38>
│ │  	beq.n	2151fc <uniffi_pbcli_checksum_method_api_base@@Base+0xa8978>
│ │  	b.n	215740 <uniffi_pbcli_checksum_method_api_base@@Base+0xa8ebc>
│ │  	str	r0, [r0, #0]
│ │  	b.n	2155ea <uniffi_pbcli_checksum_method_api_base@@Base+0xa8d66>
│ │ @@ -318575,24 +318575,24 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	215c9a <uniffi_pbcli_checksum_method_api_base@@Base+0xa9416>
│ │  	lsls	r5, r1, #25
│ │  	add.w	r0, r1, r8
│ │  	b.n	2158a2 <uniffi_pbcli_checksum_method_api_base@@Base+0xa901e>
│ │  	ldrh	r1, [r4, #4]
│ │  			@ <UNDEFINED> instruction: 0xeb03ffeb
│ │ -			@ <UNDEFINED> instruction: 0xeafffdbb
│ │ +			@ <UNDEFINED> instruction: 0xeafffde2
│ │  			@ <UNDEFINED> instruction: 0xffe8aaf0
│ │  			@ <UNDEFINED> instruction: 0xffe6aafc
│ │  			@ <UNDEFINED> instruction: 0xffe6a9b4
│ │  	vmul.f32	q13, q11, d0[0]
│ │  	vrshr.u64	d25, d16, #26
│ │  			@ <UNDEFINED> instruction: 0xffe62ed8
│ │  	vqshlu.s64	d17, d0, #38	@ 0x26
│ │  	vqshrun.s64	d20, <illegal reg q3.5>, #23
│ │ -	vrshr.u64	<illegal reg q11.5>, <illegal reg q13.5>, #26
│ │ +	vsubw.u32	<illegal reg q11.5>, q3, d18
│ │  	vsli.64	<illegal reg q8.5>, q2, #40	@ 0x28
│ │  	vshr.u64	d18, d1, #23
│ │  	vmls.f32	<illegal reg q8.5>, <illegal reg q11.5>, d3[0]
│ │  	vmlsl.u32	q13, d9, d8
│ │  	vshll.u32	q13, d4, #6
│ │  	vcvt.f16.u16	q10, q8, #26
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │ @@ -318914,21 +318914,21 @@
│ │  	b.n	215faa <uniffi_pbcli_checksum_method_api_base@@Base+0xa9726>
│ │  			@ <UNDEFINED> instruction: 0xe9b3eb03
│ │  	lsls	r4, r2, #1
│ │  	b.n	2153ac <uniffi_pbcli_checksum_method_api_base@@Base+0xa8b28>
│ │  	beq.n	2158ac <uniffi_pbcli_checksum_method_api_base@@Base+0xa9028>
│ │  	b.n	215d0c <uniffi_pbcli_checksum_method_api_base@@Base+0xa9488>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r6, r8, sl, fp, ip, pc}
│ │ +	ldmia.w	sp!, {r5, r7, r8, sl, fp, ip, pc}
│ │  	vrsubhn.i64	d29, q4, q7
│ │  	vqshl.u32	d26, d12, #6
│ │  			@ <UNDEFINED> instruction: 0xffe68d2f
│ │  	vrshr.u32	d17, d10, #25
│ │  	vrsubhn.i64	d26, <illegal reg q12.5>, q14
│ │ -	vqshl.u32	<illegal reg q10.5>, q1, #6
│ │ +	vqshl.u32	<illegal reg q10.5>, <illegal reg q12.5>, #6
│ │  	vqshrun.s64	d20, q8, #24
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	215db8 <uniffi_pbcli_checksum_method_api_base@@Base+0xa9534>
│ │  	beq.n	2158e0 <uniffi_pbcli_checksum_method_api_base@@Base+0xa905c>
│ │  	b.n	215d3c <uniffi_pbcli_checksum_method_api_base@@Base+0xa94b8>
│ │  	asrs	r4, r3, #28
│ │  	b.n	2153c6 <uniffi_pbcli_checksum_method_api_base@@Base+0xa8b42>
│ │ @@ -320216,51 +320216,51 @@
│ │  	b.n	215ebc <uniffi_pbcli_checksum_method_api_base@@Base+0xa9638>
│ │  	movs	r0, r0
│ │  	b.n	2164a0 <uniffi_pbcli_checksum_method_api_base@@Base+0xa9c1c>
│ │  	movs	r0, #2
│ │  	b.n	2164a4 <uniffi_pbcli_checksum_method_api_base@@Base+0xa9c20>
│ │  			@ <UNDEFINED> instruction: 0xffd8eaff
│ │  	ldr	r6, [sp, #0]
│ │ -	vqshlu.s32	q11, q1, #6
│ │ +	vqshlu.s32	q11, <illegal reg q12.5>, #6
│ │  	vmull.u32	<illegal reg q12.5>, d8, d4
│ │ -	vsri.32	q11, q3, #26
│ │ +	vsri.32	q11, <illegal reg q14.5>, #26
│ │  	vcvt.u16.f16	<illegal reg q12.5>, q2, #24
│ │ -	vabal.u32	q11, d22, d22
│ │ +	vmls.f32	q11, q11, d13[0]
│ │  	vmull.u32	<illegal reg q12.5>, d8, d28
│ │ -	vsri.32	q11, q15, #26
│ │ +	vraddhn.i64	d22, q11, <illegal reg q10.5>
│ │  			@ <UNDEFINED> instruction: 0xffe89cb4
│ │ -	vabal.u32	q11, d6, d6
│ │ +	vabal.u32	q11, d6, d29
│ │  	vqrdmlah.s32	q8, q12, d13[0]
│ │  			@ <UNDEFINED> instruction: 0xffe99b6c
│ │ -	vrsra.u64	d22, d30, #26
│ │ +			@ <UNDEFINED> instruction: 0xffe663e5
│ │  	vabdl.u32	<illegal reg q10.5>, d24, d29
│ │  	vcvt.f32.u32	d16, d3, #26
│ │  			@ <UNDEFINED> instruction: 0xffe95765
│ │  			@ <UNDEFINED> instruction: 0xffe69d28
│ │ -	vsli.32	q11, q13, #6
│ │ +	vabal.u32	q11, d22, d17
│ │  	vqrdmulh.s32	q8, q4, d11[1]
│ │  	vqrdmulh.s32	q14, <illegal reg q12.5>, d12[0]
│ │  	vaddl.u32	<illegal reg q8.5>, d23, d20
│ │  	vmul.f32	q15, <illegal reg q4.5>, d14[0]
│ │  			@ <UNDEFINED> instruction: 0xffe79dd4
│ │ -	vrsubhn.i64	d22, q3, q11
│ │ +	vmlsl.u32	q11, d6, d13[0]
│ │  	vqrdmulh.s32	q8, q12, d5[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe997e8
│ │ +	vmlal.u32	<illegal reg q12.5>, d9, d15
│ │  	vmla.i32	<illegal reg q8.5>, q4, d6[1]
│ │  	vsra.u64	q11, <illegal reg q13.5>, #23
│ │  	vqdmulh.s32	q8, <illegal reg q3.5>, d10[1]
│ │  			@ <UNDEFINED> instruction: 0xffe99d8c
│ │ -	vcvt.f32.u32	d20, d18, #26
│ │ +	vcvt.f32.u32	q10, <illegal reg q4.5>, #26
│ │  			@ <UNDEFINED> instruction: 0xffe80b5b
│ │  			@ <UNDEFINED> instruction: 0xffe99cdc
│ │ -			@ <UNDEFINED> instruction: 0xffe64d82
│ │ +			@ <UNDEFINED> instruction: 0xffe64da9
│ │  			@ <UNDEFINED> instruction: 0xffe8fdb0
│ │  	vmull.u32	q8, d6, d10[0]
│ │  	vcvt.f16.u16	<illegal reg q12.5>, q10, #23
│ │ -	vcvt.u16.f16	d20, d10, #26
│ │ +	vqrdmulh.s32	q10, q3, d1[0]
│ │  			@ <UNDEFINED> instruction: 0xffe89b90
│ │  			@ <UNDEFINED> instruction: 0xffe64ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	216948 <uniffi_pbcli_checksum_method_api_base@@Base+0xaa0c4>
│ │  	beq.n	216468 <uniffi_pbcli_checksum_method_api_base@@Base+0xa9be4>
│ │  	b.n	2168cc <uniffi_pbcli_checksum_method_api_base@@Base+0xaa048>
│ │  	str	r0, [r0, #0]
│ │ @@ -320672,33 +320672,33 @@
│ │  	b.n	2162f0 <uniffi_pbcli_checksum_method_api_base@@Base+0xa9a6c>
│ │  	movs	r0, r0
│ │  	b.n	2168d4 <uniffi_pbcli_checksum_method_api_base@@Base+0xaa050>
│ │  	movs	r0, #2
│ │  	b.n	2168d8 <uniffi_pbcli_checksum_method_api_base@@Base+0xaa054>
│ │  			@ <UNDEFINED> instruction: 0xffd7eaff
│ │  	str	r7, [sp, #224]	@ 0xe0
│ │ -	vqshl.u32	d23, d18, #6
│ │ +	vqshl.u32	<illegal reg q11.5>, <illegal reg q4.5>, #6
│ │  			@ <UNDEFINED> instruction: 0xffe899ac
│ │ -			@ <UNDEFINED> instruction: 0xffe64a52
│ │ +			@ <UNDEFINED> instruction: 0xffe64a79
│ │  	vqrdmlah.s32	<illegal reg q14.5>, q12, d2[0]
│ │  	vabdl.u32	<illegal reg q12.5>, d22, d28
│ │ -	vabdl.u32	<illegal reg q11.5>, d22, d22
│ │ +			@ <UNDEFINED> instruction: 0xffe677cd
│ │  	vqshl.u32	<illegal reg q12.5>, q2, #8
│ │ -			@ <UNDEFINED> instruction: 0xffe6774e
│ │ +	vqshl.u32	<illegal reg q11.5>, <illegal reg q10.5>, #6
│ │  	vqshl.u64	<illegal reg q12.5>, q2, #40	@ 0x28
│ │ -			@ <UNDEFINED> instruction: 0xffe677ce
│ │ +	vqshl.u64	<illegal reg q11.5>, <illegal reg q10.5>, #38	@ 0x26
│ │  	vqshrn.u64	d25, q8, #24
│ │  	vmlal.u32	<illegal reg q12.5>, d6, d0
│ │ -	vqshl.u64	<illegal reg q11.5>, q13, #38	@ 0x26
│ │ +	vmlal.u32	<illegal reg q11.5>, d6, d17
│ │  	vsri.32	d16, d0, #24
│ │  	vmlal.u32	<illegal reg q12.5>, d9, d28
│ │ -			@ <UNDEFINED> instruction: 0xffe648d2
│ │ +			@ <UNDEFINED> instruction: 0xffe648f9
│ │  			@ <UNDEFINED> instruction: 0xffe803cf
│ │  	vmul.i32	<illegal reg q12.5>, <illegal reg q4.5>, d12[1]
│ │ -	vqshrn.u64	d20, q1, #26
│ │ +	vqshrn.u64	d20, <illegal reg q12.5>, #26
│ │  			@ <UNDEFINED> instruction: 0xffe84ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	216d30 <uniffi_pbcli_checksum_method_api_base@@Base+0xaa4ac>
│ │  	beq.n	2167e0 <uniffi_pbcli_checksum_method_api_base@@Base+0xa9f5c>
│ │  	b.n	216cb4 <uniffi_pbcli_checksum_method_api_base@@Base+0xaa430>
│ │  	strb	r1, [r0, #0]
│ │  	b.n	216b5e <uniffi_pbcli_checksum_method_api_base@@Base+0xaa2da>
│ │ @@ -320941,15 +320941,15 @@
│ │  	beq.n	216a50 <uniffi_pbcli_checksum_method_api_base@@Base+0xaa1cc>
│ │  	b.n	216eb0 <uniffi_pbcli_checksum_method_api_base@@Base+0xaa62c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r6, r8, sl, ip, pc}
│ │  	vsubl.u32	q9, d22, d7
│ │  	vmla.f32	q8, <illegal reg q11.5>, d6[1]
│ │  	vmlsl.u32	q13, d25, d31
│ │ -	vqrdmulh.s32	<illegal reg q10.5>, <illegal reg q11.5>, d8[1]
│ │ +	vmull.p64	<illegal reg q10.5>, d7, d15
│ │  	vmls.i32	<illegal reg q12.5>, q12, d0[1]
│ │  	vmla.i32	q8, q3, d13[1]
│ │  	b.n	2170da <uniffi_pbcli_checksum_method_api_base@@Base+0xaa856>
│ │  	lsls	r4, r6, #1
│ │  	asrs	r0, r2, #13
│ │  	vrhadd.u16	d0, d14, d31
│ │  	udf	#106	@ 0x6a
│ │ @@ -321406,15 +321406,15 @@
│ │  	and.w	r0, r0, r0, lsl #16
│ │  	b.n	21759a <uniffi_pbcli_checksum_method_api_base@@Base+0xaad16>
│ │  	movs	r4, r0
│ │  	b.n	21719e <uniffi_pbcli_checksum_method_api_base@@Base+0xaa91a>
│ │  	beq.n	216e70 <uniffi_pbcli_checksum_method_api_base@@Base+0xaa5ec>
│ │  	b.n	2172f8 <uniffi_pbcli_checksum_method_api_base@@Base+0xaaa74>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r2, r4, r5, r6, r8, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r4, r7, r8, lr}
│ │  			@ <UNDEFINED> instruction: 0xffe8bc94
│ │  	vaddl.u32	q8, d7, d0
│ │  	b.n	217512 <uniffi_pbcli_checksum_method_api_base@@Base+0xaac8e>
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #448]	@ (21703c <uniffi_pbcli_checksum_method_api_base@@Base+0xaa7b8>)
│ │ @@ -321834,15 +321834,15 @@
│ │  			@ <UNDEFINED> instruction: 0xffd1eaff
│ │  	str	r3, [r1, #8]
│ │  	b.n	217996 <uniffi_pbcli_checksum_method_api_base@@Base+0xab112>
│ │  			@ <UNDEFINED> instruction: 0xffcfeaff
│ │  	subs	r4, r7, r3
│ │  			@ <UNDEFINED> instruction: 0xffe71ad4
│ │  			@ <UNDEFINED> instruction: 0xffe71a9c
│ │ -			@ <UNDEFINED> instruction: 0xffe7fbf0
│ │ +	vcvt.f16.u16	d31, d7, #25
│ │  	vaddl.u32	q8, d7, d0
│ │  	b.n	21790e <uniffi_pbcli_checksum_method_api_base@@Base+0xab08a>
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	lsls	r0, r2, #1
│ │  	movt	pc, #122	@ 0x7a
│ │ @@ -322116,15 +322116,15 @@
│ │  	b.n	217c0e <uniffi_pbcli_checksum_method_api_base@@Base+0xab38a>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	217c12 <uniffi_pbcli_checksum_method_api_base@@Base+0xab38e>
│ │  	vselge.f64	d30, d15, d0
│ │  			@ <UNDEFINED> instruction: 0xffe9eaff
│ │  	adds	r4, r3, r0
│ │  	vqshl.u64	d17, d8, #39	@ 0x27
│ │ -	vmlal.u32	<illegal reg q10.5>, d23, d0[0]
│ │ +	vmlal.u32	<illegal reg q10.5>, d23, d7[1]
│ │  			@ <UNDEFINED> instruction: 0xffe84ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	217a08 <uniffi_pbcli_checksum_method_api_base@@Base+0xab184>
│ │  	beq.n	217518 <uniffi_pbcli_checksum_method_api_base@@Base+0xaac94>
│ │  	b.n	21798c <uniffi_pbcli_checksum_method_api_base@@Base+0xab108>
│ │  	ands	r0, r0
│ │  	b.n	217836 <uniffi_pbcli_checksum_method_api_base@@Base+0xaafb2>
│ │ @@ -326172,29 +326172,29 @@
│ │  	lsrs	r1, r0, #16
│ │  	b.n	219d3a <uniffi_pbcli_checksum_method_api_base@@Base+0xad4b6>
│ │  	asrs	r2, r0, #32
│ │  	b.n	219f7e <uniffi_pbcli_checksum_method_api_base@@Base+0xad6fa>
│ │  	asrs	r0, r0, #32
│ │  	b.n	219342 <uniffi_pbcli_checksum_method_api_base@@Base+0xacabe>
│ │  	mrc2	10, 6, lr, cr15, cr15, {7}	@ <UNPREDICTABLE>
│ │ -	ldr	r3, [pc, #300]	@ (219974 <uniffi_pbcli_checksum_method_api_base@@Base+0xad0f0>)
│ │ -			@ <UNDEFINED> instruction: 0xffe84ad3
│ │ -			@ <UNDEFINED> instruction: 0xffe84af7
│ │ -			@ <UNDEFINED> instruction: 0xffe848b7
│ │ +	ldr	r3, [pc, #456]	@ (219a10 <uniffi_pbcli_checksum_method_api_base@@Base+0xad18c>)
│ │ +			@ <UNDEFINED> instruction: 0xffe84afa
│ │ +			@ <UNDEFINED> instruction: 0xffe84b1e
│ │ +			@ <UNDEFINED> instruction: 0xffe848de
│ │  			@ <UNDEFINED> instruction: 0xffe83a5e
│ │  	vsri.64	d25, d28, #25
│ │  	vmlsl.u32	<illegal reg q9.5>, d7, d6
│ │ -			@ <UNDEFINED> instruction: 0xffe7ed09
│ │ -			@ <UNDEFINED> instruction: 0xffe74903
│ │ +	vcvt.u16.f16	d30, d16, #25
│ │ +			@ <UNDEFINED> instruction: 0xffe7492a
│ │  	vcvt.u16.f16	d17, d0, #24
│ │  	movs	r0, r0
│ │ -	bx	r9
│ │ -	vmlsl.u32	q10, d24, d11[1]
│ │ +	bx	lr
│ │ +	vqshl.u32	d20, d2, #8
│ │  			@ <UNDEFINED> instruction: 0xffe83896
│ │ -	vsra.u64	q13, q3, #25
│ │ +	vsra.u64	q13, <illegal reg q14.5>, #25
│ │  	vcvt.f16.u16	d20, d0, #24
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	219da0 <uniffi_pbcli_checksum_method_api_base@@Base+0xad51c>
│ │  	beq.n	219898 <uniffi_pbcli_checksum_method_api_base@@Base+0xad014>
│ │  	b.n	219d24 <uniffi_pbcli_checksum_method_api_base@@Base+0xad4a0>
│ │  	ands	r0, r0
│ │  	b.n	219bce <uniffi_pbcli_checksum_method_api_base@@Base+0xad34a>
│ │ @@ -327834,18 +327834,18 @@
│ │  	movs	r4, r0
│ │  	b.n	21a9f6 <uniffi_pbcli_checksum_method_api_base@@Base+0xae172>
│ │  	movs	r7, #27
│ │  	b.n	21acba <uniffi_pbcli_checksum_method_api_base@@Base+0xae436>
│ │  			@ <UNDEFINED> instruction: 0xffedeaff
│ │  	ldr	r6, [sp, #968]	@ 0x3c8
│ │  	vcvt.f32.u32	<illegal reg q12.5>, q13, #25
│ │ -	vsri.64	<illegal reg q12.5>, q0, #25
│ │ +	vsri.64	<illegal reg q12.5>, <illegal reg q11.5>, #25
│ │  	vmlsl.u32	<illegal reg q15.5>, d8, d12[1]
│ │  	vsli.32	d31, d20, #5
│ │ -	vrsra.u32	<illegal reg q12.5>, q14, #27
│ │ +	vsubw.u32	<illegal reg q12.5>, <illegal reg q10.5>, d19
│ │  	vcvt.f16.u16	q10, q8, #24
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	21abf8 <uniffi_pbcli_checksum_method_api_base@@Base+0xae374>
│ │  	str	r0, [r0, r0]
│ │  	b.n	21aa22 <uniffi_pbcli_checksum_method_api_base@@Base+0xae19e>
│ │  	lsrs	r0, r7, #22
│ │  	b.n	21aa86 <uniffi_pbcli_checksum_method_api_base@@Base+0xae202>
│ │ @@ -329110,16 +329110,16 @@
│ │  	add.w	r0, r5, r4
│ │  	b.n	21b50e <uniffi_pbcli_checksum_method_api_base@@Base+0xaec8a>
│ │  	beq.n	21b1f0 <uniffi_pbcli_checksum_method_api_base@@Base+0xae96c>
│ │  	b.n	21b668 <uniffi_pbcli_checksum_method_api_base@@Base+0xaede4>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r1, r3, r4, r5, r8, r9, ip, pc}
│ │  	vrshr.u32	d25, d18, #25
│ │ -	vmull.p64	<illegal reg q15.5>, d23, d19
│ │ -	vqrdmlah.s32	<illegal reg q15.5>, <illegal reg q3.5>, d7[0]
│ │ +	vqrdmlah.s32	<illegal reg q15.5>, <illegal reg q11.5>, d10[0]
│ │ +	vqrdmlah.s32	<illegal reg q15.5>, <illegal reg q3.5>, d14[1]
│ │  			@ <UNDEFINED> instruction: 0xffe748f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	21b708 <uniffi_pbcli_checksum_method_api_base@@Base+0xaee84>
│ │  	beq.n	21b200 <uniffi_pbcli_checksum_method_api_base@@Base+0xae97c>
│ │  	b.n	21b68c <uniffi_pbcli_checksum_method_api_base@@Base+0xaee08>
│ │  	strb	r1, [r0, #0]
│ │  	b.n	21b536 <uniffi_pbcli_checksum_method_api_base@@Base+0xaecb2>
│ │ @@ -330536,15 +330536,15 @@
│ │  	movs	r0, r0
│ │  	b.n	21c4fe <uniffi_pbcli_checksum_method_api_base@@Base+0xafc7a>
│ │  	movs	r1, r0
│ │  	asrs	r0, r0, #12
│ │  	beq.n	21be74 <uniffi_pbcli_checksum_method_api_base@@Base+0xaf5f0>
│ │  	b.n	21c2fc <uniffi_pbcli_checksum_method_api_base@@Base+0xafa78>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r6, sl, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r7, sl, sp, lr}
│ │  	vqshrun.s64	d20, q8, #24
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	21c390 <uniffi_pbcli_checksum_method_api_base@@Base+0xafb0c>
│ │  	beq.n	21be88 <uniffi_pbcli_checksum_method_api_base@@Base+0xaf604>
│ │  	b.n	21c314 <uniffi_pbcli_checksum_method_api_base@@Base+0xafa90>
│ │  	asrs	r0, r4, #1
│ │  	b.n	21b9bc <uniffi_pbcli_checksum_method_api_base@@Base+0xaf138>
│ │ @@ -330588,28 +330588,28 @@
│ │  	and.w	r0, r0, r0, lsl #16
│ │  	b.n	21c616 <uniffi_pbcli_checksum_method_api_base@@Base+0xafd92>
│ │  	movs	r4, r0
│ │  	b.n	21c21a <uniffi_pbcli_checksum_method_api_base@@Base+0xaf996>
│ │  	beq.n	21beec <uniffi_pbcli_checksum_method_api_base@@Base+0xaf668>
│ │  	b.n	21c374 <uniffi_pbcli_checksum_method_api_base@@Base+0xafaf0>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r6, r8, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r3, r5, r6, r8, ip, sp, lr, pc}
│ │  	vshr.u64	q8, q10, #25
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │  	b.n	21c58e <uniffi_pbcli_checksum_method_api_base@@Base+0xafd0a>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	asrs	r0, r1, #32
│ │  	b.n	21ba34 <uniffi_pbcli_checksum_method_api_base@@Base+0xaf1b0>
│ │  	movs	r0, #53	@ 0x35
│ │  	b.n	21c63a <uniffi_pbcli_checksum_method_api_base@@Base+0xafdb6>
│ │  	asrs	r1, r0, #32
│ │  	b.n	21c01c <uniffi_pbcli_checksum_method_api_base@@Base+0xaf798>
│ │  	lsls	r2, r6, #15
│ │ -			@ <UNDEFINED> instruction: 0xea04f0d1
│ │ +			@ <UNDEFINED> instruction: 0xea04f0f8
│ │  	vshr.u32	d16, d8, #25
│ │  	b.n	21c40a <uniffi_pbcli_checksum_method_api_base@@Base+0xafb86>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r0, r1
│ │  	b.n	21ba32 <uniffi_pbcli_checksum_method_api_base@@Base+0xaf1ae>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r0, [pc, #0]	@ (21bf18 <uniffi_pbcli_checksum_method_api_base@@Base+0xaf694>)
│ │ @@ -333814,15 +333814,15 @@
│ │  	b.n	21d590 <uniffi_pbcli_checksum_method_api_base@@Base+0xb0d0c>
│ │  	movs	r0, r1
│ │  	b.n	21ddba <uniffi_pbcli_checksum_method_api_base@@Base+0xb1536>
│ │  	lsls	r1, r2, #24
│ │  			@ <UNDEFINED> instruction: 0xeb00fcc4
│ │  			@ <UNDEFINED> instruction: 0xeaffcfb8
│ │  	vsubl.u32	<illegal reg q9.5>, d5, d30
│ │ -	vaddw.u32	q13, q11, d28
│ │ +	vsra.u64	q13, <illegal reg q1.5>, #26
│ │  	vaddl.u32	q8, d7, d2
│ │  	b.n	21ddd2 <uniffi_pbcli_checksum_method_api_base@@Base+0xb154e>
│ │  	lsls	r1, r0, #12
│ │  	b.n	21e0b6 <uniffi_pbcli_checksum_method_api_base@@Base+0xb1832>
│ │  	stc2l	10, cr1, [r1], {255}	@ 0xff	@ <UNPREDICTABLE>
│ │  	asrs	r0, r0, #32
│ │  	b.n	21d5ce <uniffi_pbcli_checksum_method_api_base@@Base+0xb0d4a>
│ │ @@ -334875,15 +334875,15 @@
│ │  	b.n	21deb2 <uniffi_pbcli_checksum_method_api_base@@Base+0xb162e>
│ │  	beq.n	21e390 <uniffi_pbcli_checksum_method_api_base@@Base+0xb1b0c>
│ │  	b.n	21e7c8 <uniffi_pbcli_checksum_method_api_base@@Base+0xb1f44>
│ │  	ldrh	r4, [r0, #24]
│ │  	ldc	0, cr13, [sp], #16
│ │  	b.n	21e854 <uniffi_pbcli_checksum_method_api_base@@Base+0xb1fd0>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r3, r5, r7, r9, fp, ip, pc}
│ │ +	ldmia.w	sp!, {r2, r4, r6, r7, r9, fp, ip, pc}
│ │  			@ <UNDEFINED> instruction: 0xffe72b2a
│ │  	vmla.f32	q10, q11, d4[0]
│ │  	vaddl.u32	<illegal reg q15.5>, d6, d0
│ │  	b.n	21e98e <uniffi_pbcli_checksum_method_api_base@@Base+0xb210a>
│ │  	blx	61e990 <uniffi_pbcli_checksum_method_api_base@@Base+0x4b210c>
│ │  			@ <UNDEFINED> instruction: 0xffffffff
│ │  			@ <UNDEFINED> instruction: 0xffffffff
│ │ @@ -335019,33 +335019,33 @@
│ │  	movs	r0, r0
│ │  	lsrs	r0, r5, #29
│ │  	vabdl.u32	q9, d6, d14
│ │  	vqshl.u32	d31, d18, #6
│ │  	vmls.f32	q9, <illegal reg q10.5>, d5[1]
│ │  	vqshlu.s64	d18, d30, #39	@ 0x27
│ │  	vcvt.u16.f16	<illegal reg q9.5>, q4, #26
│ │ -	vsri.32	q14, <illegal reg q0.5>, #26
│ │ +	vsri.32	q14, q12, #26
│ │  	vqrshrun.s64	d18, q3, #25
│ │  			@ <UNDEFINED> instruction: 0xffe63ef0
│ │  	vabdl.u32	q9, d22, d26
│ │ -	vshr.u64	d31, d19, #26
│ │ -	vmlal.u32	q11, d23, d4[1]
│ │ -	vmlsl.u32	q13, d24, d2
│ │ +	vshr.u64	<illegal reg q15.5>, q5, #26
│ │ +	vsubw.u32	q11, <illegal reg q3.5>, d11
│ │ +	vmlsl.u32	q13, d24, d25
│ │  	vsli.32	q9, q9, #7
│ │  			@ <UNDEFINED> instruction: 0xffe6da99
│ │  	vsri.64	d18, d22, #27
│ │ -			@ <UNDEFINED> instruction: 0xffe6edbf
│ │ +	vqrdmulh.s32	q15, q11, d6[1]
│ │  	vqrdmlsh.s32	q12, <illegal reg q3.5>, d12[0]
│ │ -	vshr.u32	d26, d1, #28
│ │ +	vshr.u32	d26, d24, #28
│ │  	vmull.u32	<illegal reg q8.5>, d23, d2[0]
│ │  			@ <UNDEFINED> instruction: 0xffe61b74
│ │  			@ <UNDEFINED> instruction: 0xffe67d88
│ │  	vcvt.u32.f32	d17, d10, #26
│ │  	vsli.64	<illegal reg q9.5>, q8, #38	@ 0x26
│ │ -	vmull.p64	<illegal reg q8.5>, d22, d5
│ │ +	vmull.p64	<illegal reg q8.5>, d22, d28
│ │  	vmul.i32	q9, q12, d6[0]
│ │  	vqrdmlsh.s32	<illegal reg q9.5>, q3, d0[1]
│ │  	vmlal.u32	q10, d6, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	21e82a <uniffi_pbcli_checksum_method_api_base@@Base+0xb1fa6>
│ │  	asrs	r0, r0, #32
│ │  	b.n	21e010 <uniffi_pbcli_checksum_method_api_base@@Base+0xb178c>
│ │ @@ -335290,15 +335290,15 @@
│ │  	b.n	21ee3e <uniffi_pbcli_checksum_method_api_base@@Base+0xb25ba>
│ │  	adds	r5, #177	@ 0xb1
│ │  	add.w	r0, r0, r1, lsl #24
│ │  	b.n	21ee46 <uniffi_pbcli_checksum_method_api_base@@Base+0xb25c2>
│ │  			@ <UNDEFINED> instruction: 0xfff6eaff
│ │  	mcr2	15, 6, pc, cr8, cr15, {7}	@ <UNPREDICTABLE>
│ │  	adds	r6, r2, r1
│ │ -	vmla.f32	q15, q3, d7[1]
│ │ +	vaddw.u32	q15, q11, d14
│ │  			@ <UNDEFINED> instruction: 0xffe74ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	21ec38 <uniffi_pbcli_checksum_method_api_base@@Base+0xb23b4>
│ │  	beq.n	21e798 <uniffi_pbcli_checksum_method_api_base@@Base+0xb1f14>
│ │  	b.n	21ebbc <uniffi_pbcli_checksum_method_api_base@@Base+0xb2338>
│ │  	str	r0, [r0, r0]
│ │  	b.n	21ea66 <uniffi_pbcli_checksum_method_api_base@@Base+0xb21e2>
│ │ @@ -335856,26 +335856,26 @@
│ │  	str	r1, [r0, #0]
│ │  	b.n	21f32e <uniffi_pbcli_checksum_method_api_base@@Base+0xb2aaa>
│ │  	lsrs	r1, r0, #16
│ │  	b.n	21f2f2 <uniffi_pbcli_checksum_method_api_base@@Base+0xb2a6e>
│ │  	movs	r0, r0
│ │  	b.n	21e704 <uniffi_pbcli_checksum_method_api_base@@Base+0xb1e80>
│ │  			@ <UNDEFINED> instruction: 0xffa4eaff
│ │ -	str	r7, [r3, #108]	@ 0x6c
│ │ +	str	r6, [r0, #112]	@ 0x70
│ │  	vqshlu.s64	q15, q14, #40	@ 0x28
│ │ -			@ <UNDEFINED> instruction: 0xffe6ddd3
│ │ +			@ <UNDEFINED> instruction: 0xffe6ddfa
│ │  	vcvt.u16.f16	d31, d2, #25
│ │ -			@ <UNDEFINED> instruction: 0xffe50a9a
│ │ +	vmull.u32	q8, d21, d1[0]
│ │  	vmul.i32	<illegal reg q12.5>, q12, d10[0]
│ │  	vsra.u64	d26, d10, #27
│ │ -	vmul.f32	<illegal reg q12.5>, q3, d12[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe799ac
│ │ -	vshll.u32	q8, d18, #7
│ │ +	vqrshrn.u64	d25, <illegal reg q9.5>, #26
│ │ +			@ <UNDEFINED> instruction: 0xffe799d3
│ │ +			@ <UNDEFINED> instruction: 0xffe70a59
│ │  	vmla.f32	<illegal reg q13.5>, q4, d2[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe56f05
│ │ +			@ <UNDEFINED> instruction: 0xffe56f2c
│ │  			@ <UNDEFINED> instruction: 0xffe7c90c
│ │  	vshll.u32	<illegal reg q13.5>, d17, #5
│ │  	vshr.u32	q10, <illegal reg q9.5>, #26
│ │  	vqshl.u64	d25, d1, #39	@ 0x27
│ │  	vaddw.u32	q13, <illegal reg q2.5>, d1
│ │  	vqshl.u64	<illegal reg q10.5>, <illegal reg q12.5>, #38	@ 0x26
│ │  			@ <UNDEFINED> instruction: 0xffe713c5
│ │ @@ -336622,15 +336622,15 @@
│ │  	b.n	21edd2 <uniffi_pbcli_checksum_method_api_base@@Base+0xb254e>
│ │  	asrs	r0, r2, #16
│ │  	add.w	r0, r0, r5
│ │  	b.n	21f5f2 <uniffi_pbcli_checksum_method_api_base@@Base+0xb2d6e>
│ │  	beq.n	21f2d4 <uniffi_pbcli_checksum_method_api_base@@Base+0xb2a50>
│ │  	b.n	21f74c <uniffi_pbcli_checksum_method_api_base@@Base+0xb2ec8>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r5, r6, r8, ip, pc}
│ │ +	ldmia.w	sp!, {r3, r7, r8, ip, pc}
│ │  	vmull.u32	q8, d23, d30
│ │  	vsri.32	<illegal reg q15.5>, <illegal reg q3.5>, #26
│ │  			@ <UNDEFINED> instruction: 0xffe54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	21f7e8 <uniffi_pbcli_checksum_method_api_base@@Base+0xb2f64>
│ │  	beq.n	21f398 <uniffi_pbcli_checksum_method_api_base@@Base+0xb2b14>
│ │  	b.n	21f76c <uniffi_pbcli_checksum_method_api_base@@Base+0xb2ee8>
│ │ @@ -336893,24 +336893,24 @@
│ │  	b.n	21effe <uniffi_pbcli_checksum_method_api_base@@Base+0xb277a>
│ │  	asrs	r0, r0, #1
│ │  	b.n	21fa14 <uniffi_pbcli_checksum_method_api_base@@Base+0xb3190>
│ │  	mcr2	11, 3, lr, cr10, cr15, {7}	@ <UNPREDICTABLE>
│ │  	beq.n	21f538 <uniffi_pbcli_checksum_method_api_base@@Base+0xb2cb4>
│ │  	b.n	21f998 <uniffi_pbcli_checksum_method_api_base@@Base+0xb3114>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r6, r8, fp, ip}
│ │ +	ldmia.w	sp!, {r1, r7, r8, fp, ip}
│ │  			@ <UNDEFINED> instruction: 0xffe8c90b
│ │ -	vmla.f32	q8, q3, d14[1]
│ │ +	vsra.u64	d16, d5, #26
│ │  			@ <UNDEFINED> instruction: 0xffe80b6e
│ │ -			@ <UNDEFINED> instruction: 0xffe6eb6d
│ │ -	vmla.i32	q8, <illegal reg q11.5>, d14[1]
│ │ -	vmul.i32	<illegal reg q8.5>, q12, d7[0]
│ │ -	vqshlu.s32	d20, d5, #8
│ │ +			@ <UNDEFINED> instruction: 0xffe6eb94
│ │ +	vsra.u32	d16, d5, #25
│ │ +	vmul.i32	<illegal reg q8.5>, q12, d14[1]
│ │ +	vqshlu.s32	d20, d28, #8
│ │  			@ <UNDEFINED> instruction: 0xffe80ada
│ │ -			@ <UNDEFINED> instruction: 0xffe6ead9
│ │ +			@ <UNDEFINED> instruction: 0xffe6eb00
│ │  	vmul.f32	<illegal reg q9.5>, <illegal reg q11.5>, d10[0]
│ │  			@ <UNDEFINED> instruction: 0xffe64df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	21fa54 <uniffi_pbcli_checksum_method_api_base@@Base+0xb31d0>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	21f87e <uniffi_pbcli_checksum_method_api_base@@Base+0xb2ffa>
│ │  	str	r0, [r0, r0]
│ │ @@ -337507,24 +337507,24 @@
│ │  	b.n	21fd72 <uniffi_pbcli_checksum_method_api_base@@Base+0xb34ee>
│ │  	itt	vc
│ │  			@ <UNDEFINED> instruction: 0xeb01d01c
│ │  	bvc.n	21fed0 <uniffi_pbcli_checksum_method_api_base@@Base+0xb364c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r9, fp, pc}
│ │  	vqshl.u64	d16, d14, #37	@ 0x25
│ │ -	vrshr.u32	q11, q6, #26
│ │ +	vsubl.u32	q11, d22, d3
│ │  	vsri.64	q14, <illegal reg q7.5>, #25
│ │  			@ <UNDEFINED> instruction: 0xffe607ce
│ │ -	vsubl.u32	q11, d22, d8
│ │ -			@ <UNDEFINED> instruction: 0xffe7fcbc
│ │ +	vsubl.u32	q11, d22, d31
│ │ +	vqdmulh.s32	<illegal reg q15.5>, <illegal reg q11.5>, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffe70742
│ │ -	vsra.u64	q11, q14, #26
│ │ -	vmul.i32	q9, <illegal reg q11.5>, d15[0]
│ │ +	vsubl.u32	q11, d6, d19
│ │ +			@ <UNDEFINED> instruction: 0xffe728f6
│ │  	vsli.32	q8, q3, #8
│ │ -	vshr.u32	d22, d4, #26
│ │ +	vshr.u32	d22, d27, #26
│ │  	vabdl.u32	q9, d7, d20
│ │  	movs	r0, r0
│ │  	subs	r0, r6, r1
│ │  	vsri.64	q8, q11, #25
│ │  	vsli.64	d16, d2, #38	@ 0x26
│ │  	vsubw.u32	q8, q3, d16
│ │  	b.n	21f5a2 <uniffi_pbcli_checksum_method_api_base@@Base+0xb2d1e>
│ │ @@ -337604,15 +337604,15 @@
│ │  	b.n	21fc48 <uniffi_pbcli_checksum_method_api_base@@Base+0xb33c4>
│ │  	ands	r0, r2
│ │  	b.n	21f648 <uniffi_pbcli_checksum_method_api_base@@Base+0xb2dc4>
│ │  	ldc2l	11, cr14, [sp], {255}	@ 0xff	@ <UNPREDICTABLE>
│ │  	beq.n	21fb54 <uniffi_pbcli_checksum_method_api_base@@Base+0xb32d0>
│ │  	b.n	21ffcc <uniffi_pbcli_checksum_method_api_base@@Base+0xb3748>
│ │  	ldrh	r0, [r2, #38]	@ 0x26
│ │ -	ldmia.w	sp!, {r0, r4, r6, r8, ip}
│ │ +	ldmia.w	sp!, {r3, r4, r5, r6, r8, ip}
│ │  	vsri.64	q8, q2, #24
│ │  	b.n	21f662 <uniffi_pbcli_checksum_method_api_base@@Base+0xb2dde>
│ │  	lsls	r0, r2, #11
│ │  	b.n	21fb06 <uniffi_pbcli_checksum_method_api_base@@Base+0xb3282>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (21fb8c <uniffi_pbcli_checksum_method_api_base@@Base+0xb3308>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │ @@ -338736,15 +338736,15 @@
│ │  	b.n	22000e <uniffi_pbcli_checksum_method_api_base@@Base+0xb378a>
│ │  	asrs	r2, r0, #32
│ │  	b.n	220c2a <uniffi_pbcli_checksum_method_api_base@@Base+0xb43a6>
│ │  	ldrb	r5, [r3, r1]
│ │  			@ <UNDEFINED> instruction: 0xeb00d01c
│ │  	b.n	220988 <uniffi_pbcli_checksum_method_api_base@@Base+0xb4104>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r4, r7, r8, r9, sl, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r5, r7, r8, r9, sl, fp, ip, sp, lr}
│ │  	vmull.u32	<illegal reg q15.5>, d7, d6[0]
│ │  			@ <UNDEFINED> instruction: 0xffe5faf8
│ │  	vabdl.u32	<illegal reg q12.5>, d21, d28
│ │  			@ <UNDEFINED> instruction: 0xffe5fa9a
│ │  	vqshl.u64	d25, d29, #37	@ 0x25
│ │  	vmlal.u32	q10, d5, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │ @@ -339230,15 +339230,15 @@
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {ip, sp, lr}
│ │  	b.n	22106e <uniffi_pbcli_checksum_method_api_base@@Base+0xb47ea>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │  	str	r0, [r0, #36]	@ 0x24
│ │  	vmull.u32	<illegal reg q9.5>, d20, d10
│ │  	vqshlu.s32	<illegal reg q15.5>, q7, #6
│ │ -	vrsra.u64	q8, <illegal reg q8.5>, #27
│ │ +	vsri.32	d16, d8, #27
│ │  			@ <UNDEFINED> instruction: 0xffe84ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	220e64 <uniffi_pbcli_checksum_method_api_base@@Base+0xb45e0>
│ │  	svc	97	@ 0x61
│ │  	b.n	220de8 <uniffi_pbcli_checksum_method_api_base@@Base+0xb4564>
│ │  	adds	r0, #2
│ │  	b.n	220c92 <uniffi_pbcli_checksum_method_api_base@@Base+0xb440e>
│ │ @@ -341169,15 +341169,15 @@
│ │  	b.n	221a84 <uniffi_pbcli_checksum_method_api_base@@Base+0xb5200>
│ │  	mrrc2	10, 15, lr, sl, cr15
│ │  	str	r2, [sp, #736]	@ 0x2e0
│ │  	b.n	2214ac <uniffi_pbcli_checksum_method_api_base@@Base+0xb4c28>
│ │  	str	r0, [sp, #36]	@ 0x24
│ │  	b.n	221a90 <uniffi_pbcli_checksum_method_api_base@@Base+0xb520c>
│ │  	mrrc2	10, 15, lr, r7, cr15
│ │ -	str	r3, [r2, #72]	@ 0x48
│ │ +	str	r2, [r7, #72]	@ 0x48
│ │  	vsubl.u32	<illegal reg q12.5>, d23, d4
│ │  	b.n	2214bc <uniffi_pbcli_checksum_method_api_base@@Base+0xb4c38>
│ │  	str	r0, [sp, #36]	@ 0x24
│ │  	b.n	221aa0 <uniffi_pbcli_checksum_method_api_base@@Base+0xb521c>
│ │  	mrrc2	10, 15, lr, r3, cr15
│ │  	str	r1, [sp, #992]	@ 0x3e0
│ │  	b.n	2214c8 <uniffi_pbcli_checksum_method_api_base@@Base+0xb4c44>
│ │ @@ -341343,15 +341343,15 @@
│ │  	b.n	221c2c <uniffi_pbcli_checksum_method_api_base@@Base+0xb53a8>
│ │  			@ <UNDEFINED> instruction: 0xfbf0eaff
│ │  	str	r0, [sp, #464]	@ 0x1d0
│ │  	b.n	221654 <uniffi_pbcli_checksum_method_api_base@@Base+0xb4dd0>
│ │  	str	r0, [sp, #36]	@ 0x24
│ │  	b.n	221c38 <uniffi_pbcli_checksum_method_api_base@@Base+0xb53b4>
│ │  			@ <UNDEFINED> instruction: 0xfbedeaff
│ │ -	pop	{r1, r5, r6}
│ │ +	pop	{r0, r3, r7}
│ │  	vmla.i32	<illegal reg q12.5>, <illegal reg q3.5>, d8[1]
│ │  	b.n	221664 <uniffi_pbcli_checksum_method_api_base@@Base+0xb4de0>
│ │  	str	r0, [sp, #36]	@ 0x24
│ │  	b.n	221c48 <uniffi_pbcli_checksum_method_api_base@@Base+0xb53c4>
│ │  			@ <UNDEFINED> instruction: 0xfbe9eaff
│ │  	bl	5fcafa <uniffi_pbcli_checksum_method_api_base@@Base+0x490276>
│ │  	blt.n	221a54 <uniffi_pbcli_checksum_method_api_base@@Base+0xb51d0>
│ │ @@ -341361,109 +341361,109 @@
│ │  	b.n	221c5c <uniffi_pbcli_checksum_method_api_base@@Base+0xb53d8>
│ │  			@ <UNDEFINED> instruction: 0xfbe4eaff
│ │  	str	r0, [sp, #208]	@ 0xd0
│ │  	b.n	221684 <uniffi_pbcli_checksum_method_api_base@@Base+0xb4e00>
│ │  	str	r0, [sp, #36]	@ 0x24
│ │  	b.n	221c68 <uniffi_pbcli_checksum_method_api_base@@Base+0xb53e4>
│ │  			@ <UNDEFINED> instruction: 0xfbe1eaff
│ │ -	mov	sp, r1
│ │ +	mov	ip, r6
│ │  	vqrdmlah.s32	q14, <illegal reg q3.5>, d15[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe56b56
│ │ +			@ <UNDEFINED> instruction: 0xffe56b7d
│ │  	vabdl.u32	<illegal reg q13.5>, d7, d6
│ │ -	vabal.u32	<illegal reg q12.5>, d6, d16
│ │ -	vsli.32	d25, d0, #7
│ │ -	vrsubhn.i64	d25, <illegal reg q3.5>, q2
│ │ +	vmls.f32	<illegal reg q12.5>, q3, d7[0]
│ │ +	vsli.32	d25, d23, #7
│ │ +	vrsubhn.i64	d25, <illegal reg q3.5>, <illegal reg q13.5>
│ │  			@ <UNDEFINED> instruction: 0xffe72b95
│ │  	vsra.u32	<illegal reg q8.5>, <illegal reg q8.5>, #26
│ │ -			@ <UNDEFINED> instruction: 0xffe753e4
│ │ +	vraddhn.i64	d21, <illegal reg q3.5>, <illegal reg q5.5>
│ │  			@ <UNDEFINED> instruction: 0xffe799da
│ │ -	vcvt.u32.f32	<illegal reg q11.5>, q6, #27
│ │ -	vcvt.u32.f32	<illegal reg q11.5>, q0, #25
│ │ -	vshr.u32	q12, q8, #25
│ │ -	vsra.u32	d24, d21, #25
│ │ -	vmull.u32	q11, d7, d4[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe57f83
│ │ +	vcvt.u32.f32	<illegal reg q11.5>, <illegal reg q11.5>, #25
│ │ +	vshr.u64	d24, d7, #25
│ │ +	vsra.u32	q12, q6, #25
│ │ +	vmlsl.u32	q11, d23, d11
│ │  	vsra.u64	q10, q10, #25
│ │  	vmla.f32	q10, q11, d4[1]
│ │  	vrshr.u64	q10, q14, #26
│ │  	vcvt.f32.u32	d28, d16, #26
│ │  			@ <UNDEFINED> instruction: 0xffe569b0
│ │  	vsli.64	d27, d23, #37	@ 0x25
│ │ -	vmlsl.u32	q14, d5, d8[0]
│ │ +	vmlsl.u32	q14, d5, d15[1]
│ │  	vmull.u32	q9, d7, d10[0]
│ │  	vmls.f32	<illegal reg q13.5>, <illegal reg q11.5>, d13[0]
│ │  	vaddw.u32	<illegal reg q8.5>, <illegal reg q10.5>, d4
│ │  	movs	r0, r0
│ │  			@ <UNDEFINED> instruction: 0xb7bd
│ │  	vraddhn.i64	d20, q3, <illegal reg q7.5>
│ │  	vsra.u32	d17, d24, #26
│ │  	movs	r0, r0
│ │ -	stmia	r6!, {r2, r5}
│ │ +	stmia	r6!, {r0, r1, r3, r6}
│ │  	vsra.u64	d24, d19, #25
│ │  	vaddw.u32	q12, <illegal reg q10.5>, d23
│ │  			@ <UNDEFINED> instruction: 0xffe5cbd3
│ │  	vsri.32	<illegal reg q13.5>, q13, #26
│ │  	vmls.i32	<illegal reg q13.5>, <illegal reg q2.5>, d14[1]
│ │  	vsubl.u32	<illegal reg q8.5>, d5, d15
│ │  	vqdmulh.s32	q14, <illegal reg q11.5>, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffe5ccd4
│ │ -	vraddhn.i64	d21, <illegal reg q10.5>, q10
│ │ +	vmls.i32	<illegal reg q10.5>, <illegal reg q10.5>, d11[0]
│ │  	vmlsl.u32	q12, d23, d19
│ │  			@ <UNDEFINED> instruction: 0xffe68a97
│ │  	vrshr.u64	<illegal reg q8.5>, <illegal reg q5.5>, #26
│ │  	vmlsl.u32	q11, d7, d10
│ │ -	vqshl.u64	<illegal reg q9.5>, <illegal reg q2.5>, #37	@ 0x25
│ │ +	vqshl.u64	<illegal reg q9.5>, q14, #37	@ 0x25
│ │  	vmlsl.u32	<illegal reg q15.5>, d8, d3
│ │  			@ <UNDEFINED> instruction: 0xffe6f9f7
│ │ -	vrsubhn.i64	d25, q11, q6
│ │ -	vabal.u32	<illegal reg q12.5>, d23, d12
│ │ -	vabal.u32	<illegal reg q12.5>, d23, d0
│ │ +	vqshlu.s64	d25, d19, #38	@ 0x26
│ │ +	vsli.64	d25, d19, #39	@ 0x27
│ │ +	vabal.u32	<illegal reg q12.5>, d23, d23
│ │  	vshll.u32	q11, d12, #7
│ │  			@ <UNDEFINED> instruction: 0xffe5cc94
│ │ -	vraddhn.i64	d28, q11, <illegal reg q14.5>
│ │ -	vraddhn.i64	d28, <illegal reg q11.5>, <illegal reg q8.5>
│ │ +	vsri.64	q14, q2, #26
│ │ +	vmls.i32	q14, <illegal reg q11.5>, d8[0]
│ │  	vsli.32	d30, d30, #7
│ │  			@ <UNDEFINED> instruction: 0xffe58bc8
│ │ -	vrsra.u32	d31, d30, #26
│ │ +			@ <UNDEFINED> instruction: 0xffe6f365
│ │  	vsra.u64	<illegal reg q8.5>, <illegal reg q1.5>, #25
│ │ -	vmla.i32	q12, <illegal reg q11.5>, d13[1]
│ │ -	vmlsl.u32	<illegal reg q9.5>, d23, d5[0]
│ │ -	vcvt.u32.f32	q13, <illegal reg q5.5>, #24
│ │ +	vsra.u32	d24, d4, #25
│ │ +	vmlsl.u32	<illegal reg q9.5>, d23, d12[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe8af82
│ │  	vmull.u32	q9, d7, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffe62a54
│ │ -	vmla.f32	q10, q3, d9[1]
│ │ -	vmla.f32	q9, <illegal reg q11.5>, d13[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe85a7d
│ │ +	vsra.u64	d20, d0, #26
│ │ +	vrshr.u32	d18, d4, #25
│ │ +	vmlsl.u32	<illegal reg q10.5>, d24, d20
│ │  	vshr.u64	d29, d0, #25
│ │ -	vdup.8	<illegal reg q9.5>, d3[7]
│ │ +	vdup.8	<illegal reg q9.5>, d26[7]
│ │  	vqdmulh.s32	<illegal reg q13.5>, q4, d0[1]
│ │ -	vrsra.u32	d27, d23, #26
│ │ +	vrsra.u32	<illegal reg q13.5>, q7, #26
│ │  	vrshr.u32	<illegal reg q14.5>, q15, #25
│ │  	vmlsl.u32	q15, d21, d3
│ │  	vqshl.u32	<illegal reg q11.5>, q1, #5
│ │  			@ <UNDEFINED> instruction: 0xffe69ef2
│ │  	vmlsl.u32	q15, d5, d22
│ │  	vqshlu.s32	<illegal reg q8.5>, <illegal reg q5.5>, #5
│ │  	vcvt.u16.f16	q11, <illegal reg q8.5>, #25
│ │  	vmlsl.u32	<illegal reg q11.5>, d21, d13[0]
│ │  			@ <UNDEFINED> instruction: 0xffe62db9
│ │  			@ <UNDEFINED> instruction: 0xffe7e989
│ │  	vrsubhn.i64	d26, <illegal reg q2.5>, q15
│ │  	vcvt.u32.f32	d24, d2, #26
│ │  			@ <UNDEFINED> instruction: 0xffe68f01
│ │ -	vsubw.u32	q10, q11, d5
│ │ +	vsubw.u32	q10, q11, d28
│ │  	vsli.64	d24, d10, #39	@ 0x27
│ │  	vqrdmulh.s32	<illegal reg q12.5>, <illegal reg q2.5>, d0[1]
│ │ -	vsubw.u32	q9, <illegal reg q10.5>, d4
│ │ -	vqshl.u32	<illegal reg q10.5>, <illegal reg q0.5>, #8
│ │ -			@ <UNDEFINED> instruction: 0xffe75748
│ │ -			@ <UNDEFINED> instruction: 0xffe70b65
│ │ +	vsubw.u32	q9, <illegal reg q10.5>, d27
│ │ +	vqshl.u32	<illegal reg q10.5>, q12, #8
│ │ +			@ <UNDEFINED> instruction: 0xffe7576f
│ │ +			@ <UNDEFINED> instruction: 0xffe70b8c
│ │  	vqdmulh.s32	<illegal reg q12.5>, q12, d11[1]
│ │  			@ <UNDEFINED> instruction: 0xffe56ba4
│ │ -	vmlal.u32	q9, d21, d12[1]
│ │ -	vmlal.u32	q9, d24, d10[1]
│ │ +	vrsra.u32	d18, d3, #27
│ │ +	vrsra.u32	d18, d1, #24
│ │  			@ <UNDEFINED> instruction: 0xffe86b5e
│ │  	vqrshrun.s64	d16, q2, #27
│ │  	movs	r0, r0
│ │  	ldc2	15, cr15, [r1], {230}	@ 0xe6
│ │  	b.n	221a5c <uniffi_pbcli_checksum_method_api_base@@Base+0xb51d8>
│ │  	vcvt.f32.u32	q14, q14, #27
│ │  	vqshrun.s64	d20, q8, #27
│ │ @@ -341729,23 +341729,23 @@
│ │  	b.n	222652 <uniffi_pbcli_checksum_method_api_base@@Base+0xb5dce>
│ │  			@ <UNDEFINED> instruction: 0xf4ebebff
│ │  	movs	r1, r0
│ │  	b.n	22265a <uniffi_pbcli_checksum_method_api_base@@Base+0xb5dd6>
│ │  	beq.n	221f2c <uniffi_pbcli_checksum_method_api_base@@Base+0xb56a8>
│ │  	b.n	2223b4 <uniffi_pbcli_checksum_method_api_base@@Base+0xb5b30>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r2, r5, r7, r8, fp, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r6, r7, r8, fp, sp, pc}
│ │  	vshr.u64	d30, d18, #25
│ │ -	vmlsl.u32	<illegal reg q14.5>, d5, d11[0]
│ │ +	vqshlu.s32	<illegal reg q14.5>, q9, #5
│ │  	vqrdmulh.s32	q8, <illegal reg q3.5>, d0[0]
│ │  	vshr.u32	q15, q11, #25
│ │ -	vrsubhn.i64	d29, <illegal reg q2.5>, <illegal reg q7.5>
│ │ -	vrshr.u32	d19, d1, #25
│ │ +	vqshlu.s32	d29, d22, #5
│ │ +	vrshr.u32	d19, d24, #25
│ │  	vaddl.u32	q15, d8, d22
│ │ -	vsli.64	d29, d19, #37	@ 0x25
│ │ +	vsli.64	<illegal reg q14.5>, q5, #37	@ 0x25
│ │  			@ <UNDEFINED> instruction: 0xffe74bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	222468 <uniffi_pbcli_checksum_method_api_base@@Base+0xb5be4>
│ │  	beq.n	221f70 <uniffi_pbcli_checksum_method_api_base@@Base+0xb56ec>
│ │  	b.n	2223ec <uniffi_pbcli_checksum_method_api_base@@Base+0xb5b68>
│ │  	asrs	r0, r0, #32
│ │  	b.n	221a76 <uniffi_pbcli_checksum_method_api_base@@Base+0xb51f2>
│ │ @@ -348463,15 +348463,15 @@
│ │  	b.n	2258f8 <uniffi_pbcli_checksum_method_api_base@@Base+0xb9074>
│ │  	movs	r0, #83	@ 0x53
│ │  	adds	r3, #0
│ │  	movs	r0, #0
│ │  	b.n	225254 <uniffi_pbcli_checksum_method_api_base@@Base+0xb89d0>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r1, r5, r6, r7, r9, sl, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffe69f24
│ │ +	vqrdmlsh.s32	<illegal reg q12.5>, q3, d11[0]
│ │  	vqshlu.s32	q11, q14, #7
│ │  	vmlal.u32	q13, d6, d11
│ │  	vmlsl.u32	<illegal reg q11.5>, d22, d27
│ │  	vqshrun.s64	d20, q8, #26
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	225c8c <uniffi_pbcli_checksum_method_api_base@@Base+0xb9408>
│ │  	str	r1, [r0, r0]
│ │ @@ -348543,15 +348543,15 @@
│ │  	asrs	r0, r4, #14
│ │  	lsls	r4, r6, #1
│ │  	asrs	r4, r0, #22
│ │  	movs	r1, r0
│ │  	b.n	225f4a <uniffi_pbcli_checksum_method_api_base@@Base+0xb96c6>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r1, r3, r4, r6, r7, sl, sp, lr}
│ │ -	vqrdmulh.s32	<illegal reg q12.5>, q3, d4[0]
│ │ +	vqrdmulh.s32	<illegal reg q12.5>, q3, d11[1]
│ │  	vsri.64	d22, d24, #25
│ │  	vmlsl.u32	q13, d6, d11[1]
│ │  			@ <UNDEFINED> instruction: 0xffe67927
│ │  	vmlal.u32	q10, d6, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	225b6a <uniffi_pbcli_checksum_method_api_base@@Base+0xb92e6>
│ │  	stmia	r0!, {r3, r5}
│ │ @@ -349923,18 +349923,18 @@
│ │  	b.n	2266be <uniffi_pbcli_checksum_method_api_base@@Base+0xb9e3a>
│ │  	lsls	r6, r1, #9
│ │  			@ <UNDEFINED> instruction: 0xeb00ff85
│ │  			@ <UNDEFINED> instruction: 0xeaff6dd3
│ │  	vsli.64	q12, q15, #37	@ 0x25
│ │  	vmlsl.u32	<illegal reg q9.5>, d21, d5
│ │  	vrsra.u32	d30, d6, #27
│ │ -	vqshl.u32	<illegal reg q15.5>, q13, #5
│ │ +	vabdl.u32	<illegal reg q15.5>, d21, d17
│ │  	vrshr.u64	q12, q1, #26
│ │  	vqrdmlah.s32	q11, q3, d5[1]
│ │ -	vqdmulh.s32	<illegal reg q11.5>, q11, d12[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe67cf3
│ │  	vmull.u32	<illegal reg q15.5>, d7, d2[0]
│ │  	vmul.f32	<illegal reg q9.5>, <illegal reg q2.5>, d1[0]
│ │  			@ <UNDEFINED> instruction: 0xffe53925
│ │  			@ <UNDEFINED> instruction: 0xffe54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2268d4 <uniffi_pbcli_checksum_method_api_base@@Base+0xba050>
│ │  	beq.n	226404 <uniffi_pbcli_checksum_method_api_base@@Base+0xb9b80>
│ │ @@ -351004,23 +351004,23 @@
│ │  	b.n	227118 <uniffi_pbcli_checksum_method_api_base@@Base+0xba894>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r6, sl, fp, sp, pc}
│ │  	vcvt.u16.f16	d26, d26, #26
│ │  			@ <UNDEFINED> instruction: 0xffe5ab9d
│ │  	vsli.32	d25, d23, #6
│ │  			@ <UNDEFINED> instruction: 0xffe6ab15
│ │ -			@ <UNDEFINED> instruction: 0xffe6e76f
│ │ -	vqshlu.s64	q15, <illegal reg q5.5>, #39	@ 0x27
│ │ +	vqshl.u64	d30, d6, #38	@ 0x26
│ │ +	vabdl.u32	q15, d7, d2
│ │  	vqshlu.s64	d22, d24, #39	@ 0x27
│ │ -	vmlsl.u32	q15, d6, d3[0]
│ │ +	vmlsl.u32	q15, d6, d10[1]
│ │  	vrsra.u64	d25, d12, #25
│ │ -	vsli.64	d30, d27, #38	@ 0x26
│ │ +	vmls.f32	q15, q11, d2[1]
│ │  	vsubw.u32	<illegal reg q12.5>, <illegal reg q3.5>, d16
│ │  			@ <UNDEFINED> instruction: 0xffe6176b
│ │ -	vcvt.f16.u16	d21, d28, #27
│ │ +	vqdmulh.s32	<illegal reg q10.5>, <illegal reg q2.5>, d3[1]
│ │  	vaddl.u32	q8, d7, d0
│ │  	b.n	227362 <uniffi_pbcli_checksum_method_api_base@@Base+0xbaade>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (226d88 <uniffi_pbcli_checksum_method_api_base@@Base+0xba504>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2271e8 <uniffi_pbcli_checksum_method_api_base@@Base+0xba964>
│ │  	ands	r0, r0
│ │ @@ -351483,40 +351483,40 @@
│ │  	b.n	22741e <uniffi_pbcli_checksum_method_api_base@@Base+0xbab9a>
│ │  	lsls	r2, r7, #4
│ │  	add.w	r0, r0, r1
│ │  	b.n	227826 <uniffi_pbcli_checksum_method_api_base@@Base+0xbafa2>
│ │  	beq.n	227118 <uniffi_pbcli_checksum_method_api_base@@Base+0xba894>
│ │  	b.n	227580 <uniffi_pbcli_checksum_method_api_base@@Base+0xbacfc>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r6, r9, fp, ip, lr}
│ │ +	ldmia.w	sp!, {r1, r4, r5, r6, r9, fp, ip, lr}
│ │  	vsli.32	d17, d27, #7
│ │ -	vmlsl.u32	q12, d21, d2[1]
│ │ -	vmlal.u32	q15, d23, d5[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe7ebed
│ │ +	vabdl.u32	q12, d5, d9
│ │ +	vsubw.u32	q15, <illegal reg q3.5>, d12
│ │ +	vcvt.f16.u16	d30, d4, #25
│ │  	vcvt.f32.u32	d18, d29, #26
│ │  	vsubl.u32	q11, d21, d31
│ │  			@ <UNDEFINED> instruction: 0xffe62df9
│ │  			@ <UNDEFINED> instruction: 0xffe578d7
│ │ -	vaddw.u32	q10, <illegal reg q10.5>, d6
│ │ +	vaddw.u32	q10, <illegal reg q10.5>, d29
│ │  	vqrdmlsh.s32	q12, <illegal reg q3.5>, d7[1]
│ │  	vrsubhn.i64	d23, q11, <illegal reg q6.5>
│ │  	vqshlu.s32	d16, d3, #6
│ │ -	vmla.f32	q15, q11, d10[1]
│ │ -	vsli.64	d24, d22, #39	@ 0x27
│ │ +	vrshr.u32	d30, d1, #26
│ │ +	vsli.64	q12, <illegal reg q6.5>, #39	@ 0x27
│ │  	vcvt.u16.f16	d18, d17, #25
│ │ -	vsra.u64	d30, d3, #27
│ │ +	vsra.u64	d30, d26, #27
│ │  			@ <UNDEFINED> instruction: 0xffe71d06
│ │  	vsli.64	d19, d3, #38	@ 0x26
│ │ -			@ <UNDEFINED> instruction: 0xffe66f9b
│ │ -			@ <UNDEFINED> instruction: 0xffe79c9d
│ │ -			@ <UNDEFINED> instruction: 0xffe7e9d2
│ │ +	vqrdmlsh.s32	q11, q11, d2[0]
│ │ +	vqdmulh.s32	<illegal reg q12.5>, <illegal reg q11.5>, d4[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe7e9f9
│ │  	vabal.u32	<illegal reg q11.5>, d6, d30
│ │  	vmull.u32	<illegal reg q8.5>, d6, d29
│ │  			@ <UNDEFINED> instruction: 0xffe61be5
│ │ -	vrshr.u64	d17, d16, #26
│ │ +	vrshr.u64	<illegal reg q8.5>, <illegal reg q3.5>, #26
│ │  			@ <UNDEFINED> instruction: 0xffe748f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	227678 <uniffi_pbcli_checksum_method_api_base@@Base+0xbadf4>
│ │  	movs	r0, r0
│ │  	b.n	227802 <uniffi_pbcli_checksum_method_api_base@@Base+0xbaf7e>
│ │  	ands	r0, r0
│ │  	asrs	r0, r4, #6
│ │ @@ -351612,15 +351612,15 @@
│ │  	b.n	22756a <uniffi_pbcli_checksum_method_api_base@@Base+0xbace6>
│ │  	lsls	r1, r3, #5
│ │  	add.w	r0, r0, r0
│ │  	b.n	227972 <uniffi_pbcli_checksum_method_api_base@@Base+0xbb0ee>
│ │  	lsls	r0, r1, #1
│ │  	b.n	226d3e <uniffi_pbcli_checksum_method_api_base@@Base+0xba4ba>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r3, r7, r9, sl, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r4, r5, r7, r9, sl, sp, lr, pc}
│ │  	vcvt.f16.u16	d20, d0, #26
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	227760 <uniffi_pbcli_checksum_method_api_base@@Base+0xbaedc>
│ │  	ands	r0, r0
│ │  	b.n	22758a <uniffi_pbcli_checksum_method_api_base@@Base+0xbad06>
│ │  	movs	r0, r0
│ │  	b.n	2278f0 <uniffi_pbcli_checksum_method_api_base@@Base+0xbb06c>
│ │ @@ -354957,15 +354957,15 @@
│ │  	movs	r1, r0
│ │  	b.n	2295d6 <uniffi_pbcli_checksum_method_api_base@@Base+0xbcd52>
│ │  	movs	r4, r0
│ │  	b.n	228a22 <uniffi_pbcli_checksum_method_api_base@@Base+0xbc19e>
│ │  	beq.n	228ed4 <uniffi_pbcli_checksum_method_api_base@@Base+0xbc650>
│ │  	b.n	229334 <uniffi_pbcli_checksum_method_api_base@@Base+0xbcab0>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r3, r6, r7, r9, sl, lr, pc}
│ │ +	ldmia.w	sp!, {r4, r5, r6, r7, r9, sl, lr, pc}
│ │  	vrshr.u32	d19, d11, #25
│ │  			@ <UNDEFINED> instruction: 0xffe65d29
│ │  	vqshrun.s64	d27, <illegal reg q14.5>, #27
│ │  	vaddw.u32	<illegal reg q9.5>, q11, d0
│ │  	vmlsl.u32	<illegal reg q8.5>, d6, d13
│ │  	vmla.i32	<illegal reg q9.5>, q3, d15[1]
│ │  			@ <UNDEFINED> instruction: 0xffe62f27
│ │ @@ -356121,21 +356121,21 @@
│ │  	b.n	229bc2 <uniffi_pbcli_checksum_method_api_base@@Base+0xbd33e>
│ │  	beq.n	2298a4 <uniffi_pbcli_checksum_method_api_base@@Base+0xbd020>
│ │  	b.n	229d1c <uniffi_pbcli_checksum_method_api_base@@Base+0xbd498>
│ │  	ldr	r4, [pc, #448]	@ (229a48 <uniffi_pbcli_checksum_method_api_base@@Base+0xbd1c4>)
│ │  	ldmia.w	sp!, {r0, r4, r5, r9, sl, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeaff7cc5
│ │  	vrsubhn.i64	d22, q11, <illegal reg q7.5>
│ │ -	vmul.f32	<illegal reg q13.5>, q3, d0[1]
│ │ -	vsubl.u32	q14, d7, d30
│ │ -	vshr.u32	d19, d30, #26
│ │ +			@ <UNDEFINED> instruction: 0xffe6b987
│ │ +	vrshr.u32	q14, <illegal reg q2.5>, #25
│ │ +	vmla.i32	<illegal reg q9.5>, q3, d5[1]
│ │  	vcvt.u32.f32	d20, d24, #25
│ │ -	vqshrn.u64	d27, <illegal reg q0.5>, #27
│ │ +	vqshrn.u64	d27, q12, #27
│ │  	vmls.i32	q9, <illegal reg q3.5>, d6[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe68a77
│ │ +			@ <UNDEFINED> instruction: 0xffe68a9e
│ │  			@ <UNDEFINED> instruction: 0xffe7dcb5
│ │  	vcvt.f16.u16	q10, q8, #27
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	229dd8 <uniffi_pbcli_checksum_method_api_base@@Base+0xbd554>
│ │  	beq.n	229910 <uniffi_pbcli_checksum_method_api_base@@Base+0xbd08c>
│ │  	b.n	229d5c <uniffi_pbcli_checksum_method_api_base@@Base+0xbd4d8>
│ │  	movs	r1, #32
│ │ @@ -356272,26 +356272,26 @@
│ │  	movs	r4, r0
│ │  	b.n	229d1e <uniffi_pbcli_checksum_method_api_base@@Base+0xbd49a>
│ │  	bf	16, 2261de <uniffi_pbcli_checksum_method_api_base@@Base+0xb995a>
│ │  	beq.n	229a04 <uniffi_pbcli_checksum_method_api_base@@Base+0xbd180>
│ │  	b.n	229e7c <uniffi_pbcli_checksum_method_api_base@@Base+0xbd5f8>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r3, r4, r5, r7, r8, r9, fp, ip, sp, lr}
│ │ -	vmul.i32	<illegal reg q13.5>, q3, d3[0]
│ │ -	vqrshrun.s64	d27, q11, #25
│ │ +	vmul.i32	<illegal reg q13.5>, q3, d10[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe7b89d
│ │  	vqshlu.s32	q11, <illegal reg q1.5>, #7
│ │ -			@ <UNDEFINED> instruction: 0xffe55bce
│ │ +			@ <UNDEFINED> instruction: 0xffe55bf5
│ │  	vcvt.f32.u32	d20, d26, #25
│ │  			@ <UNDEFINED> instruction: 0xffe5f349
│ │  	vsra.u32	<illegal reg q13.5>, q0, #27
│ │  	movs	r7, r4
│ │ -	ldrh	r5, [r4, #8]
│ │ +	ldrh	r4, [r1, #10]
│ │  	vmlsl.u32	q13, d7, d0
│ │  			@ <UNDEFINED> instruction: 0xffe6a9f0
│ │ -	vshr.u32	q14, <illegal reg q5.5>, #26
│ │ +	vaddl.u32	q14, d22, d2
│ │  	vqshrun.s64	d20, q8, #26
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	229f3c <uniffi_pbcli_checksum_method_api_base@@Base+0xbd6b8>
│ │  	beq.n	229a34 <uniffi_pbcli_checksum_method_api_base@@Base+0xbd1b0>
│ │  	b.n	229ec0 <uniffi_pbcli_checksum_method_api_base@@Base+0xbd63c>
│ │  	movs	r0, #196	@ 0xc4
│ │  	b.n	229568 <uniffi_pbcli_checksum_method_api_base@@Base+0xbcce4>
│ │ @@ -356383,22 +356383,22 @@
│ │  	movs	r4, r0
│ │  	b.n	229e26 <uniffi_pbcli_checksum_method_api_base@@Base+0xbd5a2>
│ │  	beq.n	229af8 <uniffi_pbcli_checksum_method_api_base@@Base+0xbd274>
│ │  	b.n	229f80 <uniffi_pbcli_checksum_method_api_base@@Base+0xbd6fc>
│ │  	ldr	r0, [pc, #192]	@ (229bac <uniffi_pbcli_checksum_method_api_base@@Base+0xbd328>)
│ │  	ldmia.w	sp!, {r3, r4, r7, r8, sl, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeaffe903
│ │ -	vmull.p64	q9, d4, d8
│ │ +	vmull.p64	q9, d4, d31
│ │  			@ <UNDEFINED> instruction: 0xffe77ba5
│ │ -	vmls.f32	q10, <illegal reg q2.5>, d3[1]
│ │ +	vabal.u32	q10, d21, d10
│ │  	vrsubhn.i64	d19, <illegal reg q11.5>, q15
│ │  	vshr.u32	<illegal reg q13.5>, q4, #26
│ │  	movs	r7, r4
│ │  	lsls	r1, r7, #7
│ │ -	vqrdmlsh.s32	<illegal reg q12.5>, <illegal reg q10.5>, d8[1]
│ │ +	vaddl.u32	q13, d5, d15
│ │  			@ <UNDEFINED> instruction: 0xffe748f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	22a034 <uniffi_pbcli_checksum_method_api_base@@Base+0xbd7b0>
│ │  	beq.n	229b3c <uniffi_pbcli_checksum_method_api_base@@Base+0xbd2b8>
│ │  	b.n	229fb8 <uniffi_pbcli_checksum_method_api_base@@Base+0xbd734>
│ │  	str	r2, [r0, #0]
│ │  	b.n	229e62 <uniffi_pbcli_checksum_method_api_base@@Base+0xbd5de>
│ │ @@ -356461,15 +356461,15 @@
│ │  	beq.n	229bb8 <uniffi_pbcli_checksum_method_api_base@@Base+0xbd334>
│ │  	b.n	22a030 <uniffi_pbcli_checksum_method_api_base@@Base+0xbd7ac>
│ │  	ldr	r0, [pc, #960]	@ (229f5c <uniffi_pbcli_checksum_method_api_base@@Base+0xbd6d8>)
│ │  	ldmia.w	sp!, {r2, r3, r5, r6, r8, sl, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeaffd010
│ │  	b.n	22a03c <uniffi_pbcli_checksum_method_api_base@@Base+0xbd7b8>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r1, r4, r5, r7, r8, sl, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r4, r6, r7, r8, sl, ip, sp, pc}
│ │  	vrsra.u32	d22, d28, #25
│ │  	vsra.u32	<illegal reg q15.5>, q15, #26
│ │  			@ <UNDEFINED> instruction: 0xffe54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	22a0d8 <uniffi_pbcli_checksum_method_api_base@@Base+0xbd854>
│ │  	svc	173	@ 0xad
│ │  	b.n	22a05c <uniffi_pbcli_checksum_method_api_base@@Base+0xbd7d8>
│ │ @@ -357918,112 +357918,112 @@
│ │  			@ <UNDEFINED> instruction: 0xffeceaff
│ │  	movs	r4, r0
│ │  	b.n	22ab56 <uniffi_pbcli_checksum_method_api_base@@Base+0xbe2d2>
│ │  	bfcsel	a, 22b016 <uniffi_pbcli_checksum_method_api_base@@Base+0xbe792>, e, vc
│ │  	beq.n	22a854 <uniffi_pbcli_checksum_method_api_base@@Base+0xbdfd0>
│ │  	b.n	22acb4 <uniffi_pbcli_checksum_method_api_base@@Base+0xbe430>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, sl, lr}
│ │  	vmls.f32	<illegal reg q9.5>, <illegal reg q3.5>, d6[0]
│ │  	vqrdmlah.s32	q13, q11, d8[1]
│ │  	movs	r7, r4
│ │  	lsls	r1, r2, #2
│ │ -	vcvt.f32.u32	<illegal reg q12.5>, q14, #27
│ │ -	vsli.32	d27, d28, #7
│ │ -	vaddl.u32	<illegal reg q11.5>, d23, d1
│ │ -	vmull.p64	<illegal reg q12.5>, d7, d26
│ │ +	vmull.p64	<illegal reg q12.5>, d21, d19
│ │ +	vmls.f32	<illegal reg q13.5>, <illegal reg q3.5>, d3[1]
│ │ +	vaddl.u32	<illegal reg q11.5>, d23, d24
│ │ +	vcvt.f32.u32	<illegal reg q12.5>, <illegal reg q0.5>, #25
│ │  	vsubl.u32	<illegal reg q9.5>, d23, d19
│ │ -	vqshlu.s64	d30, d28, #37	@ 0x25
│ │ +	vmlsl.u32	q15, d21, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffe6a8ba
│ │  	vmul.i32	q8, <illegal reg q2.5>, d8[1]
│ │  	vsra.u64	<illegal reg q11.5>, <illegal reg q0.5>, #26
│ │  	vcvt.f32.u32	q9, q1, #26
│ │  	vsri.64	<illegal reg q11.5>, <illegal reg q8.5>, #26
│ │  	vmull.u32	<illegal reg q8.5>, d22, d27
│ │  	vmla.f32	<illegal reg q9.5>, q3, d7[0]
│ │  	vmull.u32	q15, d22, d28
│ │ -			@ <UNDEFINED> instruction: 0xffe59a7c
│ │ +	vmlsl.u32	<illegal reg q12.5>, d21, d19
│ │  			@ <UNDEFINED> instruction: 0xffe74743
│ │ -	vsra.u32	d27, d13, #27
│ │ +	vmla.f32	<illegal reg q13.5>, <illegal reg q2.5>, d4[0]
│ │  	vaddw.u32	<illegal reg q11.5>, <illegal reg q11.5>, d21
│ │ -	vabdl.u32	<illegal reg q13.5>, d6, d10
│ │ +	vqshl.u32	d27, d17, #6
│ │  	vmla.f32	<illegal reg q8.5>, q3, d11[0]
│ │  			@ <UNDEFINED> instruction: 0xffe58894
│ │ -	vqshl.u32	<illegal reg q12.5>, <illegal reg q6.5>, #6
│ │ +	vabdl.u32	<illegal reg q12.5>, d22, d4
│ │  	vsra.u32	d23, d21, #25
│ │  	vmla.f32	q8, q11, d7[1]
│ │  	vshr.u64	<illegal reg q8.5>, <illegal reg q5.5>, #26
│ │  	vmlal.u32	q12, d5, d20
│ │  	vshr.u64	<illegal reg q11.5>, <illegal reg q4.5>, #26
│ │  	vsubl.u32	<illegal reg q11.5>, d6, d2
│ │  			@ <UNDEFINED> instruction: 0xffe587e7
│ │  	vmlal.u32	q15, d22, d29
│ │  	vmls.f32	<illegal reg q11.5>, <illegal reg q10.5>, d13[1]
│ │ -	vsli.32	q15, q9, #6
│ │ +	vsli.64	d30, d9, #38	@ 0x26
│ │  	vsli.64	d17, d3, #38	@ 0x26
│ │  	vqdmulh.s32	q12, <illegal reg q10.5>, d7[1]
│ │  			@ <UNDEFINED> instruction: 0xffe6eda9
│ │ -			@ <UNDEFINED> instruction: 0xffe56dba
│ │ +	vqrdmulh.s32	q11, <illegal reg q10.5>, d1[1]
│ │  	vsubl.u32	<illegal reg q9.5>, d7, d1
│ │  			@ <UNDEFINED> instruction: 0xffe66ff9
│ │  			@ <UNDEFINED> instruction: 0xffe62a77
│ │  	vmla.i32	q10, <illegal reg q2.5>, d8[0]
│ │  	vsubw.u32	<illegal reg q11.5>, q11, d21
│ │  	vraddhn.i64	d26, q11, q5
│ │ -	vcvt.u16.f16	q14, <illegal reg q0.5>, #27
│ │ +	vcvt.u16.f16	q14, q12, #27
│ │  	vmull.u32	<illegal reg q13.5>, d6, d25
│ │  			@ <UNDEFINED> instruction: 0xffe5eb8d
│ │  			@ <UNDEFINED> instruction: 0xffe56fbd
│ │  	vcvt.f32.u32	d29, d21, #26
│ │  	vqrdmlsh.s32	q8, q2, d3[1]
│ │  	vqrdmulh.s32	q11, <illegal reg q10.5>, d13[1]
│ │  	vsli.32	d24, d10, #6
│ │  	vqrdmulh.s32	q11, q11, d1[0]
│ │  	vmul.i32	q9, q3, d8[0]
│ │  	vmlal.u32	<illegal reg q11.5>, d21, d5[1]
│ │  	vmull.u32	<illegal reg q15.5>, d22, d1[0]
│ │  	vrshr.u64	d17, d1, #28
│ │ -			@ <UNDEFINED> instruction: 0xffe5aed7
│ │ -			@ <UNDEFINED> instruction: 0xffe7af8e
│ │ -	vcvt.u32.f32	q13, q15, #25
│ │ +			@ <UNDEFINED> instruction: 0xffe5aefe
│ │ +			@ <UNDEFINED> instruction: 0xffe7afb5
│ │ +			@ <UNDEFINED> instruction: 0xffe7afa5
│ │  			@ <UNDEFINED> instruction: 0xffe789a0
│ │  	vqdmulh.s32	q9, q11, d14[1]
│ │ -	vqshl.u64	d27, d7, #37	@ 0x25
│ │ +	vqshl.u64	d27, d30, #37	@ 0x25
│ │  			@ <UNDEFINED> instruction: 0xffe66d99
│ │  	vcvt.f32.u32	<illegal reg q9.5>, q6, #26
│ │  	vqrdmlah.s32	q11, q11, d1[0]
│ │  	vmul.f32	q9, q3, d9[1]
│ │  	vmlsl.u32	<illegal reg q8.5>, d5, d7[1]
│ │  			@ <UNDEFINED> instruction: 0xffe6b74f
│ │ -	vsri.32	d25, d22, #27
│ │ -	vraddhn.i64	d25, <illegal reg q3.5>, q4
│ │ +	vsri.32	<illegal reg q12.5>, <illegal reg q6.5>, #27
│ │ +	vraddhn.i64	d25, <illegal reg q3.5>, <illegal reg q15.5>
│ │  	vcvt.f32.u32	d22, d17, #25
│ │ -	vmull.u32	<illegal reg q11.5>, d6, d22
│ │ +	vqdmulh.s32	<illegal reg q11.5>, q3, d13[0]
│ │  	vsli.64	<illegal reg q8.5>, <illegal reg q3.5>, #39	@ 0x27
│ │  	vqrdmlsh.s32	q11, q3, d1[1]
│ │  	vqshlu.s64	d24, d13, #38	@ 0x26
│ │  	vshll.u32	<illegal reg q10.5>, d13, #6
│ │  			@ <UNDEFINED> instruction: 0xffe56f25
│ │ -			@ <UNDEFINED> instruction: 0xffe67d2f
│ │ +	vcvt.u16.f16	<illegal reg q11.5>, q3, #26
│ │  	vqrdmlah.s32	q8, <illegal reg q11.5>, d11[0]
│ │  			@ <UNDEFINED> instruction: 0xffe57345
│ │  	vrsra.u32	d17, d9, #26
│ │ -			@ <UNDEFINED> instruction: 0xffe5ccf1
│ │ +	vcvt.u16.f16	d28, d8, #27
│ │  			@ <UNDEFINED> instruction: 0xffe6bbc9
│ │  			@ <UNDEFINED> instruction: 0xffe5eb2d
│ │  	vshr.u32	<illegal reg q11.5>, <illegal reg q10.5>, #27
│ │  	vcvt.u32.f32	<illegal reg q12.5>, q2, #26
│ │ -	vqshlu.s32	<illegal reg q12.5>, q3, #6
│ │ +	vqshlu.s32	<illegal reg q12.5>, <illegal reg q14.5>, #6
│ │  	vmull.u32	q9, d23, d15[0]
│ │ -	vqrdmlah.s32	<illegal reg q14.5>, <illegal reg q10.5>, d8[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe5df0f
│ │  	vcvt.u16.f16	q11, <illegal reg q12.5>, #26
│ │  			@ <UNDEFINED> instruction: 0xffe629f2
│ │  			@ <UNDEFINED> instruction: 0xffe66e91
│ │  			@ <UNDEFINED> instruction: 0xffe527cb
│ │ -			@ <UNDEFINED> instruction: 0xffe5dbe4
│ │ +	vmull.u32	<illegal reg q14.5>, d5, d11
│ │  	vsubl.u32	<illegal reg q11.5>, d6, d17
│ │  	vmull.u32	<illegal reg q10.5>, d6, d14
│ │  	vmlsl.u32	q15, d6, d1
│ │  			@ <UNDEFINED> instruction: 0xffe50cb4
│ │  			@ <UNDEFINED> instruction: 0xffe548f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	22aed8 <uniffi_pbcli_checksum_method_api_base@@Base+0xbe654>
│ │ @@ -358090,17 +358090,17 @@
│ │  	beq.n	22aa5c <uniffi_pbcli_checksum_method_api_base@@Base+0xbe1d8>
│ │  	b.n	22aed4 <uniffi_pbcli_checksum_method_api_base@@Base+0xbe650>
│ │  	ldr	r0, [pc, #960]	@ (22ae00 <uniffi_pbcli_checksum_method_api_base@@Base+0xbe57c>)
│ │  	ldmia.w	sp!, {r0, r1, r6, r7, r8, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeaffd010
│ │  	b.n	22aee0 <uniffi_pbcli_checksum_method_api_base@@Base+0xbe65c>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r8, r9, sl, sp, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r4, r5, r8, r9, sl, sp, pc}
│ │  	vraddhn.i64	d21, <illegal reg q11.5>, q10
│ │ -	vcvt.f32.u32	<illegal reg q8.5>, q8, #26
│ │ +			@ <UNDEFINED> instruction: 0xffe61e97
│ │  			@ <UNDEFINED> instruction: 0xffe74df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	22af7c <uniffi_pbcli_checksum_method_api_base@@Base+0xbe6f8>
│ │  	beq.n	22aa74 <uniffi_pbcli_checksum_method_api_base@@Base+0xbe1f0>
│ │  	b.n	22af00 <uniffi_pbcli_checksum_method_api_base@@Base+0xbe67c>
│ │  	ands	r0, r0
│ │  	b.n	22b1aa <uniffi_pbcli_checksum_method_api_base@@Base+0xbe926>
│ │ @@ -365316,19 +365316,19 @@
│ │  	movs	r1, r0
│ │  	lsls	r0, r0, #8
│ │  	movs	r6, r0
│ │  	lsls	r0, r6, #4
│ │  			@ <UNDEFINED> instruction: 0xffe21aff
│ │  			@ <UNDEFINED> instruction: 0xffedeaff
│ │  	cmp	r7, #34	@ 0x22
│ │ -	vqshlu.s32	d18, d6, #5
│ │ +	vqshlu.s32	d18, d29, #5
│ │  			@ <UNDEFINED> instruction: 0xffe72ede
│ │ -	vsli.64	q9, q1, #37	@ 0x25
│ │ +	vsli.64	q9, <illegal reg q12.5>, #37	@ 0x25
│ │  			@ <UNDEFINED> instruction: 0xffe72efa
│ │ -	vmls.f32	q9, <illegal reg q10.5>, d14[1]
│ │ +	vqshlu.s32	d18, d5, #5
│ │  	vsri.32	q12, q12, #25
│ │  	vqshrun.s64	d20, q8, #25
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	22ed14 <uniffi_pbcli_checksum_method_api_base@@Base+0xc2490>
│ │  	ands	r0, r0
│ │  	b.n	22eb3e <uniffi_pbcli_checksum_method_api_base@@Base+0xc22ba>
│ │  	movs	r4, r1
│ │ @@ -365372,15 +365372,15 @@
│ │  	cmp	r0, r6
│ │  	b.n	22e352 <uniffi_pbcli_checksum_method_api_base@@Base+0xc1ace>
│ │  	stmia	r2!, {r2, r4, r5, r7}
│ │  	b.n	22e356 <uniffi_pbcli_checksum_method_api_base@@Base+0xc1ad2>
│ │  	movs	r5, r0
│ │  	b.n	22eb9a <uniffi_pbcli_checksum_method_api_base@@Base+0xc2316>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │  	vaddl.u32	q8, d6, d0
│ │  	b.n	22ef06 <uniffi_pbcli_checksum_method_api_base@@Base+0xc2682>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #448]	@ (22ea2c <uniffi_pbcli_checksum_method_api_base@@Base+0xc21a8>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	22ed8c <uniffi_pbcli_checksum_method_api_base@@Base+0xc2508>
│ │  	ands	r0, r0
│ │ @@ -365466,17 +365466,17 @@
│ │  	b.n	22ec66 <uniffi_pbcli_checksum_method_api_base@@Base+0xc23e2>
│ │  	asrs	r5, r0, #32
│ │  	b.n	22ec6a <uniffi_pbcli_checksum_method_api_base@@Base+0xc23e6>
│ │  	movs	r0, #161	@ 0xa1
│ │  	b.n	22f06e <uniffi_pbcli_checksum_method_api_base@@Base+0xc27ea>
│ │  	ldr	r4, [pc, #448]	@ (22eaf0 <uniffi_pbcli_checksum_method_api_base@@Base+0xc226c>)
│ │  	ldmia.w	sp!, {r0, r2, r5, r6, r8, fp, ip, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xea03f75d
│ │ -	vabdl.u32	<illegal reg q15.5>, d6, d29
│ │ -	vabdl.u32	<illegal reg q15.5>, d6, d1
│ │ +			@ <UNDEFINED> instruction: 0xea03f784
│ │ +	vqshl.u32	<illegal reg q15.5>, q2, #6
│ │ +	vabdl.u32	<illegal reg q15.5>, d6, d24
│ │  	vsubl.u32	<illegal reg q8.5>, d22, d28
│ │  	b.n	22e446 <uniffi_pbcli_checksum_method_api_base@@Base+0xc1bc2>
│ │  	movs	r2, #176	@ 0xb0
│ │  	b.n	22e44a <uniffi_pbcli_checksum_method_api_base@@Base+0xc1bc6>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r3, r0
│ │  	b.n	22eff4 <uniffi_pbcli_checksum_method_api_base@@Base+0xc2770>
│ │ @@ -367213,16 +367213,16 @@
│ │  	movs	r0, r0
│ │  	and.w	r0, r0, r1, lsl #20
│ │  	b.n	22feee <uniffi_pbcli_checksum_method_api_base@@Base+0xc366a>
│ │  	str	r0, [r3, #4]
│ │  	b.n	22f2ec <uniffi_pbcli_checksum_method_api_base@@Base+0xc2a68>
│ │  	stc2	10, cr14, [r7, #-1020]!	@ 0xfffffc04	@ <UNPREDICTABLE>
│ │  	strh	r0, [r3, #0]
│ │ -	vsubl.u32	<illegal reg q15.5>, d23, d13
│ │ -			@ <UNDEFINED> instruction: 0xffe6eb55
│ │ +	vrshr.u64	d31, d20, #25
│ │ +			@ <UNDEFINED> instruction: 0xffe6eb7c
│ │  	vaddw.u32	q9, q11, d20
│ │  	vcvt.f16.u16	d20, d0, #27
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	22fce8 <uniffi_pbcli_checksum_method_api_base@@Base+0xc3464>
│ │  	movs	r2, #216	@ 0xd8
│ │  	b.n	22f2f2 <uniffi_pbcli_checksum_method_api_base@@Base+0xc2a6e>
│ │  	movs	r0, r0
│ │ @@ -368879,15 +368879,15 @@
│ │  	ldr	r2, [sp, #632]	@ 0x278
│ │  	add.w	r0, r2, r4
│ │  	b.n	230942 <uniffi_pbcli_checksum_method_api_base@@Base+0xc40be>
│ │  	beq.n	230624 <uniffi_pbcli_checksum_method_api_base@@Base+0xc3da0>
│ │  	b.n	230a9c <uniffi_pbcli_checksum_method_api_base@@Base+0xc4218>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r2, r7, r8, sl, fp, ip, sp, lr}
│ │ -	vmlsl.u32	q13, d20, d8
│ │ +	vmlsl.u32	q13, d20, d31
│ │  			@ <UNDEFINED> instruction: 0xffe64ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	230b34 <uniffi_pbcli_checksum_method_api_base@@Base+0xc42b0>
│ │  	beq.n	230674 <uniffi_pbcli_checksum_method_api_base@@Base+0xc3df0>
│ │  	b.n	230ab8 <uniffi_pbcli_checksum_method_api_base@@Base+0xc4234>
│ │  	str	r1, [r0, r0]
│ │  	b.n	230962 <uniffi_pbcli_checksum_method_api_base@@Base+0xc40de>
│ │ @@ -372849,142 +372849,142 @@
│ │  	movs	r0, r0
│ │  	b.n	232828 <uniffi_pbcli_checksum_method_api_base@@Base+0xc5fa4>
│ │  	lsls	r4, r0, #4
│ │  	stmia.w	sp, {r0, r2, r3, r5, r6, r8, sl, fp, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeaffcd4d
│ │  			@ <UNDEFINED> instruction: 0xffe56b05
│ │  	vcvt.f16.u16	<illegal reg q15.5>, <illegal reg q8.5>, #28
│ │ -	vabal.u32	<illegal reg q9.5>, d5, d3
│ │ +	vabal.u32	<illegal reg q9.5>, d5, d26
│ │  	vcvt.f32.u32	<illegal reg q12.5>, q14, #25
│ │  	vsri.32	q14, q7, #27
│ │  			@ <UNDEFINED> instruction: 0xffe40924
│ │  	vaddl.u32	q11, d6, d9
│ │  	vqshl.u32	<illegal reg q12.5>, q13, #4
│ │  			@ <UNDEFINED> instruction: 0xffe40f24
│ │  			@ <UNDEFINED> instruction: 0xffe6634d
│ │  			@ <UNDEFINED> instruction: 0xffe467c5
│ │  	vqshlu.s64	d22, d13, #37	@ 0x25
│ │  	vmlal.u32	<illegal reg q15.5>, d4, d13
│ │  	vraddhn.i64	d25, <illegal reg q10.5>, q1
│ │ -	vmull.p64	q10, d20, d5
│ │ +	vmull.p64	q10, d20, d28
│ │  	vrshr.u64	q11, <illegal reg q14.5>, #26
│ │  	vmla.f32	<illegal reg q12.5>, q2, d3[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe44b39
│ │ +			@ <UNDEFINED> instruction: 0xffe44b60
│ │  			@ <UNDEFINED> instruction: 0xffe65fb1
│ │  	vqrdmlah.s32	<illegal reg q10.5>, q2, d7[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe44989
│ │ +			@ <UNDEFINED> instruction: 0xffe449b0
│ │  	vmull.p64	<illegal reg q10.5>, d6, d1
│ │  	vabdl.u32	q11, d20, d31
│ │ -	vqshrn.u64	d20, <illegal reg q14.5>, #27
│ │ +	vmul.f32	q10, <illegal reg q2.5>, d4[1]
│ │  			@ <UNDEFINED> instruction: 0xffe65db5
│ │  	vmla.i32	<illegal reg q15.5>, q2, d5[1]
│ │  	vsri.32	d25, d30, #28
│ │ -	vrsra.u64	q11, <illegal reg q2.5>, #28
│ │ +	vrsra.u64	q11, q14, #28
│ │  	vrshr.u64	d22, d13, #26
│ │ -	vmlsl.u32	<illegal reg q9.5>, d20, d14[0]
│ │ -	vshr.u32	q11, <illegal reg q14.5>, #26
│ │ +	vqshlu.s64	<illegal reg q9.5>, <illegal reg q10.5>, #36	@ 0x24
│ │ +	vaddl.u32	q11, d22, d20
│ │  	vcvt.u32.f32	<illegal reg q10.5>, <illegal reg q8.5>, #26
│ │ -			@ <UNDEFINED> instruction: 0xffe4a8f6
│ │ +	vqshrn.u64	d26, <illegal reg q6.5>, #28
│ │  	vsri.32	d25, d14, #26
│ │  	vcvt.f16.u16	d23, d15, #28
│ │  	vmul.i32	<illegal reg q12.5>, q10, d11[0]
│ │  			@ <UNDEFINED> instruction: 0xffe578bb
│ │  	vcvt.u16.f16	<illegal reg q10.5>, <illegal reg q0.5>, #28
│ │  			@ <UNDEFINED> instruction: 0xffe4dabc
│ │  	vmlal.u32	<illegal reg q11.5>, d21, d15
│ │  	vcvt.u32.f32	d21, d9, #28
│ │  			@ <UNDEFINED> instruction: 0xffe41ff9
│ │  	vqshlu.s64	<illegal reg q11.5>, <illegal reg q5.5>, #37	@ 0x25
│ │  	vmull.u32	q8, d20, d16
│ │  			@ <UNDEFINED> instruction: 0xffe693e2
│ │ -			@ <UNDEFINED> instruction: 0xffe48f91
│ │ +			@ <UNDEFINED> instruction: 0xffe48fb8
│ │  	vmla.i32	q11, q11, d13[1]
│ │  			@ <UNDEFINED> instruction: 0xffe43cbc
│ │ -	vcvt.u32.f32	q12, <illegal reg q12.5>, #27
│ │ -	vmull.u32	<illegal reg q9.5>, d6, d7
│ │ +			@ <UNDEFINED> instruction: 0xffe58fa0
│ │ +	vmull.u32	<illegal reg q9.5>, d6, d30
│ │  	vqshl.u64	d25, d18, #38	@ 0x26
│ │  	vmla.f32	q15, q10, d7[1]
│ │  	vqshlu.s32	d22, d21, #5
│ │  	vmul.i32	q14, q2, d3[1]
│ │  	vsra.u64	d30, d3, #27
│ │  	vmls.f32	q11, <illegal reg q10.5>, d1[1]
│ │  	vmls.f32	q11, q10, d7[1]
│ │  	vmla.f32	q15, q2, d3[1]
│ │  	vabal.u32	q11, d21, d21
│ │  	vqrdmlsh.s32	q11, q2, d11[0]
│ │  	vshr.u64	q15, <illegal reg q15.5>, #27
│ │  	vsli.32	q11, <illegal reg q0.5>, #5
│ │  	vqrshrun.s64	d22, q9, #28
│ │  			@ <UNDEFINED> instruction: 0xffe5d9f7
│ │ -	vrsra.u64	<illegal reg q9.5>, q10, #27
│ │ +	vsri.32	d19, d11, #27
│ │  			@ <UNDEFINED> instruction: 0xffe67f22
│ │  	vsubw.u32	<illegal reg q12.5>, <illegal reg q10.5>, d6
│ │  	vsubw.u32	<illegal reg q15.5>, q10, d31
│ │  	vsubl.u32	q11, d5, d5
│ │  	vmul.f32	<illegal reg q9.5>, q2, d2[1]
│ │  	vaddl.u32	<illegal reg q15.5>, d21, d3
│ │  			@ <UNDEFINED> instruction: 0xffe55ed9
│ │ -	vrsra.u64	d16, d23, #28
│ │ +	vrsra.u64	q8, q7, #28
│ │  	vmlsl.u32	<illegal reg q12.5>, d7, d10[1]
│ │ -	vraddhn.i64	d16, q10, <illegal reg q14.5>
│ │ +	vsri.64	q8, q2, #28
│ │  	vmul.f32	q14, <illegal reg q3.5>, d15[0]
│ │ -	vmls.i32	q8, q2, d5[1]
│ │ +	vraddhn.i64	d16, q10, q6
│ │  	vmls.i32	<illegal reg q12.5>, <illegal reg q11.5>, d6[0]
│ │ -	vsubw.u32	q8, q2, d9
│ │ +	vrsra.u32	d16, d16, #28
│ │  	vshr.u32	<illegal reg q8.5>, q10, #25
│ │  	movs	r0, r0
│ │ -	cbnz	r3, 23286e <uniffi_pbcli_checksum_method_api_base@@Base+0xc5fea>
│ │ +	cbnz	r2, 232878 <uniffi_pbcli_checksum_method_api_base@@Base+0xc5ff4>
│ │  			@ <UNDEFINED> instruction: 0xffe69346
│ │  	vmls.i32	q14, q2, d3[1]
│ │  	vmlsl.u32	q11, d5, d9[1]
│ │  	vsubw.u32	<illegal reg q12.5>, <illegal reg q2.5>, d22
│ │  	vsri.32	d24, d4, #28
│ │  	vaddw.u32	q11, <illegal reg q10.5>, d21
│ │ -	vmlsl.u32	<illegal reg q8.5>, d4, d1[0]
│ │ +	vmlsl.u32	<illegal reg q8.5>, d4, d8[1]
│ │  	vaddw.u32	q12, <illegal reg q3.5>, d8
│ │  			@ <UNDEFINED> instruction: 0xffe55e99
│ │  	vcvt.u16.f16	d16, d2, #28
│ │  	vqshlu.s32	<illegal reg q12.5>, q1, #6
│ │  	vmla.f32	<illegal reg q13.5>, q2, d11[0]
│ │  			@ <UNDEFINED> instruction: 0xffe4c748
│ │  	vshr.u64	<illegal reg q13.5>, <illegal reg q13.5>, #27
│ │  	vsri.64	d22, d1, #28
│ │  			@ <UNDEFINED> instruction: 0xffe4aab3
│ │  	vmlal.u32	<illegal reg q12.5>, d21, d6[1]
│ │  	vsra.u64	q9, <illegal reg q8.5>, #28
│ │ -	vcvt.f32.u32	d27, d6, #26
│ │ +	vcvt.f32.u32	d27, d29, #26
│ │  	vmla.f32	q9, q11, d9[0]
│ │  	vmla.f32	q11, q3, d13[0]
│ │  	vqrdmlah.s32	q10, q2, d9[1]
│ │  	vsubl.u32	<illegal reg q12.5>, d21, d6
│ │  	vmls.f32	q14, q10, d5[0]
│ │  	vmull.u32	q11, d4, d5[0]
│ │  	vrshr.u32	d17, d24, #28
│ │  	movs	r0, r0
│ │  	str	r5, [r0, #8]
│ │  	vmla.f32	<illegal reg q15.5>, q2, d9[0]
│ │  	vabal.u32	q14, d5, d1
│ │  	vmla.f32	<illegal reg q13.5>, q10, d12[0]
│ │  	vmlal.u32	<illegal reg q12.5>, d5, d6[1]
│ │  	vqrdmulh.s32	<illegal reg q14.5>, q10, d7[0]
│ │ -	vrsra.u32	<illegal reg q9.5>, <illegal reg q15.5>, #28
│ │ -	vqrdmlah.s32	q10, q11, d14[0]
│ │ +	vsubw.u32	<illegal reg q9.5>, q10, d22
│ │ +			@ <UNDEFINED> instruction: 0xffe64ef5
│ │  			@ <UNDEFINED> instruction: 0xffe658f6
│ │  	vqshl.u32	d22, d5, #5
│ │  	vmlal.u32	<illegal reg q15.5>, d20, d9
│ │  	vmls.f32	<illegal reg q12.5>, <illegal reg q2.5>, d10[1]
│ │  	vcvt.u16.f16	<illegal reg q11.5>, q3, #28
│ │  	vsubw.u32	<illegal reg q12.5>, q10, d22
│ │ -			@ <UNDEFINED> instruction: 0xffe419ac
│ │ +			@ <UNDEFINED> instruction: 0xffe419d3
│ │  	vsli.32	d25, d2, #7
│ │  	vqdmulh.s32	q8, q10, d12[0]
│ │  	vqshlu.s32	d25, d26, #6
│ │  	vabdl.u32	<illegal reg q10.5>, d4, d3
│ │  	vrsra.u32	q14, <illegal reg q13.5>, #27
│ │ -	vqdmulh.s32	q10, <illegal reg q2.5>, d10[0]
│ │ +	vcvt.f16.u16	q10, <illegal reg q8.5>, #27
│ │  	vaddl.u32	q11, d22, d25
│ │  	vshr.u64	q9, <illegal reg q10.5>, #28
│ │  	vmlsl.u32	<illegal reg q14.5>, d5, d15
│ │  	vqshrun.s64	d25, <illegal reg q8.5>, #27
│ │  	vmlsl.u32	q11, d20, d9[1]
│ │  	vmul.i32	<illegal reg q15.5>, q2, d1[1]
│ │  	vcvt.u32.f32	q8, q8, #27
│ │ @@ -374341,15 +374341,15 @@
│ │  	b.n	233c06 <uniffi_pbcli_checksum_method_api_base@@Base+0xc7382>
│ │  	movs	r4, r0
│ │  	b.n	23380a <uniffi_pbcli_checksum_method_api_base@@Base+0xc6f86>
│ │  	beq.n	2334ec <uniffi_pbcli_checksum_method_api_base@@Base+0xc6c68>
│ │  	b.n	233964 <uniffi_pbcli_checksum_method_api_base@@Base+0xc70e0>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r7, r8, sp, lr, pc}
│ │ -	vsli.32	d25, d2, #5
│ │ +	vsli.32	d25, d25, #5
│ │  	vaddw.u32	q8, q3, d20
│ │  	movs	r0, r0
│ │  	lsls	r0, r5, #4
│ │  	movs	r0, r0
│ │  	lsrs	r0, r3, #2
│ │  	movs	r0, r0
│ │  	lsrs	r4, r2, #2
│ │ @@ -378913,18 +378913,18 @@
│ │  	b.n	2361ca <uniffi_pbcli_checksum_method_api_base@@Base+0xc9946>
│ │  	asrs	r1, r0, #32
│ │  	b.n	235cec <uniffi_pbcli_checksum_method_api_base@@Base+0xc9468>
│ │  	ldr	r4, [sp, #760]	@ 0x2f8
│ │  	add.w	r0, r3, r5
│ │  	b.n	235f16 <uniffi_pbcli_checksum_method_api_base@@Base+0xc9692>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, lr}
│ │ +	ldmia.w	sp!, {r0, r3, r5, lr}
│ │  	vmull.u32	q15, d22, d0[1]
│ │ -	vqrdmlsh.s32	<illegal reg q9.5>, q10, d10[0]
│ │ -	vqrdmlsh.s32	<illegal reg q9.5>, q3, d6[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe43ff1
│ │ +			@ <UNDEFINED> instruction: 0xffe63f8d
│ │  	vaddl.u32	q8, d6, d0
│ │  	b.n	23628e <uniffi_pbcli_checksum_method_api_base@@Base+0xc9a0a>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (235c34 <uniffi_pbcli_checksum_method_api_base@@Base+0xc93b0>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	236114 <uniffi_pbcli_checksum_method_api_base@@Base+0xc9890>
│ │  	ands	r0, r0
│ │ @@ -378938,15 +378938,15 @@
│ │  	b.n	235f4e <uniffi_pbcli_checksum_method_api_base@@Base+0xc96ca>
│ │  	cmp	r7, #165	@ 0xa5
│ │  	b.n	236352 <uniffi_pbcli_checksum_method_api_base@@Base+0xc9ace>
│ │  	asrs	r1, r0, #32
│ │  	b.n	235d34 <uniffi_pbcli_checksum_method_api_base@@Base+0xc94b0>
│ │  	ldr	r4, [pc, #64]	@ (235c58 <uniffi_pbcli_checksum_method_api_base@@Base+0xc93d4>)
│ │  	ldmia.w	sp!, {r0, r1, r3, r5, r7, sl, fp, ip, pc}
│ │ -	and.w	pc, r3, lr, lsr #12
│ │ +	and.w	pc, r3, r5, lsl #13
│ │  			@ <UNDEFINED> instruction: 0xffe648f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	236144 <uniffi_pbcli_checksum_method_api_base@@Base+0xc98c0>
│ │  	beq.n	235c6c <uniffi_pbcli_checksum_method_api_base@@Base+0xc93e8>
│ │  	b.n	2360c8 <uniffi_pbcli_checksum_method_api_base@@Base+0xc9844>
│ │  	ands	r0, r0
│ │  	b.n	235f72 <uniffi_pbcli_checksum_method_api_base@@Base+0xc96ee>
│ │ @@ -379358,39 +379358,39 @@
│ │  	b.n	2362f6 <uniffi_pbcli_checksum_method_api_base@@Base+0xc9a72>
│ │  	movs	r0, #1
│ │  	b.n	2366fa <uniffi_pbcli_checksum_method_api_base@@Base+0xc9e76>
│ │  	adds	r0, #0
│ │  	b.n	2366fe <uniffi_pbcli_checksum_method_api_base@@Base+0xc9e7a>
│ │  	movs	r0, r3
│ │  			@ <UNDEFINED> instruction: 0xeb00ffea
│ │ -			@ <UNDEFINED> instruction: 0xeaff3e86
│ │ +			@ <UNDEFINED> instruction: 0xeaff3ead
│ │  	vabdl.u32	q9, d6, d1
│ │  	vsra.u64	<illegal reg q14.5>, q2, #28
│ │  	vqshl.u64	d27, d1, #36	@ 0x24
│ │ -	vcvt.f32.u32	d19, d30, #27
│ │ +	vqrdmlah.s32	<illegal reg q9.5>, <illegal reg q2.5>, d5[1]
│ │  	vqshlu.s64	d18, d25, #38	@ 0x26
│ │  	vsra.u64	d29, d0, #28
│ │ -	vcvt.f32.u32	d29, d10, #28
│ │ -	vcvt.u16.f16	d19, d26, #26
│ │ +	vqrdmlah.s32	<illegal reg q14.5>, q2, d1[0]
│ │ +	vqrdmulh.s32	<illegal reg q9.5>, q3, d1[1]
│ │  	vsli.64	d18, d21, #38	@ 0x26
│ │  	vshr.u32	<illegal reg q14.5>, q8, #28
│ │  	vrsubhn.i64	d27, q2, <illegal reg q14.5>
│ │  	vcvt.u32.f32	q15, q4, #27
│ │  	movs	r6, r4
│ │  	lsls	r0, r6, #13
│ │  	movs	r0, r0
│ │  	lsls	r0, r0, #13
│ │  	movs	r0, r0
│ │  	lsls	r4, r3, #13
│ │  	movs	r0, r0
│ │ -	subs	r5, #30
│ │ +	subs	r5, #69	@ 0x45
│ │  	vsli.64	d18, d9, #38	@ 0x26
│ │  	vqshlu.s32	d27, d5, #4
│ │  	vraddhn.i64	d27, <illegal reg q10.5>, <illegal reg q14.5>
│ │ -	vqdmulh.s32	<illegal reg q9.5>, <illegal reg q2.5>, d10[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe53c91
│ │  	vmls.i32	q9, q11, d5[1]
│ │  			@ <UNDEFINED> instruction: 0xffe4cfbc
│ │  	vqrdmlah.s32	q9, q10, d13[0]
│ │  			@ <UNDEFINED> instruction: 0xffe548f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	236548 <uniffi_pbcli_checksum_method_api_base@@Base+0xc9cc4>
│ │  	beq.n	236060 <uniffi_pbcli_checksum_method_api_base@@Base+0xc97dc>
│ │ @@ -379446,15 +379446,15 @@
│ │  	b.n	235ba6 <uniffi_pbcli_checksum_method_api_base@@Base+0xc9322>
│ │  	lsls	r4, r3, #1
│ │  	b.n	235c2a <uniffi_pbcli_checksum_method_api_base@@Base+0xc93a6>
│ │  	beq.n	2360c4 <uniffi_pbcli_checksum_method_api_base@@Base+0xc9840>
│ │  	b.n	23653c <uniffi_pbcli_checksum_method_api_base@@Base+0xc9cb8>
│ │  	ldr	r0, [pc, #960]	@ (236468 <uniffi_pbcli_checksum_method_api_base@@Base+0xc9be4>)
│ │  	ldmia.w	sp!, {r0, r7, sl, pc}
│ │ -	and.w	sl, r2, r2, asr #15
│ │ +	and.w	fp, r2, r9, lsl #12
│ │  	vrsra.u32	q9, <illegal reg q6.5>, #26
│ │  	vmull.p64	q14, d4, d28
│ │  	vmull.u32	q10, d4, d16
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2365dc <uniffi_pbcli_checksum_method_api_base@@Base+0xc9d58>
│ │  	movs	r0, r3
│ │  	b.n	235bfc <uniffi_pbcli_checksum_method_api_base@@Base+0xc9378>
│ │ @@ -379921,31 +379921,31 @@
│ │  	b.n	2365dc <uniffi_pbcli_checksum_method_api_base@@Base+0xc9d58>
│ │  	strh	r0, [r6, #20]
│ │  	add.w	r0, r2, r4, lsr #32
│ │  	b.n	236c06 <uniffi_pbcli_checksum_method_api_base@@Base+0xca382>
│ │  	asrs	r1, r7, #3
│ │  	b.n	236c0a <uniffi_pbcli_checksum_method_api_base@@Base+0xca386>
│ │  			@ <UNDEFINED> instruction: 0xffe1eaff
│ │ -	subs	r1, #122	@ 0x7a
│ │ -	vmlal.u32	<illegal reg q9.5>, d22, d26
│ │ +	subs	r1, #161	@ 0xa1
│ │ +			@ <UNDEFINED> instruction: 0xffe638d1
│ │  			@ <UNDEFINED> instruction: 0xffe6436c
│ │ -	vmul.i32	<illegal reg q9.5>, <illegal reg q2.5>, d10[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe53891
│ │  	vsubw.u32	q10, q3, d28
│ │ -	vmlal.u32	<illegal reg q9.5>, d5, d18
│ │ +	vmul.i32	<illegal reg q9.5>, <illegal reg q2.5>, d9[0]
│ │  	vmlal.u32	q10, d22, d4[1]
│ │ -	vsra.u32	d18, d29, #27
│ │ +	vmla.f32	q9, <illegal reg q2.5>, d4[1]
│ │  	vrshr.u64	d30, d5, #26
│ │  	vmlsl.u32	q14, d4, d17
│ │ -	vqshlu.s32	<illegal reg q9.5>, q13, #4
│ │ +	vrsubhn.i64	d19, q10, <illegal reg q8.5>
│ │  	vsra.u32	d20, d28, #26
│ │ -	vqshlu.s64	<illegal reg q9.5>, q9, #37	@ 0x25
│ │ +	vqshl.u32	d19, d9, #5
│ │  	vsra.u64	d20, d20, #26
│ │ -			@ <UNDEFINED> instruction: 0xffe53746
│ │ +			@ <UNDEFINED> instruction: 0xffe5376d
│ │  	vsubl.u32	q10, d6, d8
│ │ -	vrsubhn.i64	d19, <illegal reg q10.5>, q11
│ │ +	vmlsl.u32	<illegal reg q9.5>, d21, d13[0]
│ │  	vaddl.u32	q8, d6, d0
│ │  	b.n	236bb6 <uniffi_pbcli_checksum_method_api_base@@Base+0xca332>
│ │  	movs	r2, r1
│ │  	lsrs	r0, r0, #8
│ │  	ldr	r4, [pc, #64]	@ (23655c <uniffi_pbcli_checksum_method_api_base@@Base+0xc9cd8>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	236a3c <uniffi_pbcli_checksum_method_api_base@@Base+0xca1b8>
│ │ @@ -379963,15 +379963,15 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	23665c <uniffi_pbcli_checksum_method_api_base@@Base+0xc9dd8>
│ │  	ldr	r2, [sp, #392]	@ 0x188
│ │  	add.w	ip, r3, r0, lsr #16
│ │  	ldmia.w	sp!, {r0}
│ │  	b.n	236c8a <uniffi_pbcli_checksum_method_api_base@@Base+0xca406>
│ │  	vrhadd.u16	d14, d14, d31
│ │ -	adds	r5, #246	@ 0xf6
│ │ +	adds	r6, #29
│ │  	vaddl.u32	q8, d6, d0
│ │  	b.n	236c96 <uniffi_pbcli_checksum_method_api_base@@Base+0xca412>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r0, r0
│ │  	b.n	236c9e <uniffi_pbcli_checksum_method_api_base@@Base+0xca41a>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (236624 <uniffi_pbcli_checksum_method_api_base@@Base+0xc9da0>)
│ │ @@ -380039,17 +380039,17 @@
│ │  	b.n	23692e <uniffi_pbcli_checksum_method_api_base@@Base+0xca0aa>
│ │  	movs	r0, #0
│ │  	b.n	236d32 <uniffi_pbcli_checksum_method_api_base@@Base+0xca4ae>
│ │  	strh	r0, [r4, #20]
│ │  	add.w	r0, r2, r0
│ │  	b.n	236d3a <uniffi_pbcli_checksum_method_api_base@@Base+0xca4b6>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r1, r3, r4, r7, r8, sl, ip, sp}
│ │ +	ldmia.w	sp!, {r0, r6, r7, r8, sl, ip, sp}
│ │  			@ <UNDEFINED> instruction: 0xffe64f84
│ │ -	vsli.32	<illegal reg q9.5>, q3, #4
│ │ +	vsli.32	<illegal reg q9.5>, <illegal reg q14.5>, #4
│ │  	vqrdmlsh.s32	q10, q3, d0[0]
│ │  	vaddl.u32	q8, d4, d1
│ │  	b.n	236d52 <uniffi_pbcli_checksum_method_api_base@@Base+0xca4ce>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r0, [pc, #960]	@ (2369d8 <uniffi_pbcli_checksum_method_api_base@@Base+0xca154>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	236b38 <uniffi_pbcli_checksum_method_api_base@@Base+0xca2b4>
│ │ @@ -380387,27 +380387,27 @@
│ │  	movs	r0, #52	@ 0x34
│ │  	b.n	236434 <uniffi_pbcli_checksum_method_api_base@@Base+0xc9bb0>
│ │  	movs	r0, r0
│ │  	b.n	236a18 <uniffi_pbcli_checksum_method_api_base@@Base+0xca194>
│ │  	movs	r0, #2
│ │  	b.n	236a1c <uniffi_pbcli_checksum_method_api_base@@Base+0xca198>
│ │  			@ <UNDEFINED> instruction: 0xffcdeaff
│ │ -	adds	r2, #154	@ 0x9a
│ │ +	adds	r2, #193	@ 0xc1
│ │  	vsri.32	<illegal reg q9.5>, q3, #26
│ │ -	vrshr.u32	<illegal reg q9.5>, q9, #28
│ │ +	vrshr.u64	d19, d9, #28
│ │  	vraddhn.i64	d19, q3, q15
│ │ -	vrsra.u32	<illegal reg q9.5>, q15, #28
│ │ +	vsubw.u32	<illegal reg q9.5>, q10, d21
│ │  	vsli.32	d19, d26, #6
│ │ -	vrshr.u64	<illegal reg q9.5>, q15, #28
│ │ +	vsubw.u32	<illegal reg q9.5>, q2, d21
│ │  	vsri.64	d19, d26, #26
│ │ -			@ <UNDEFINED> instruction: 0xffe4334e
│ │ +	vrsra.u32	<illegal reg q9.5>, <illegal reg q10.5>, #28
│ │  	vabal.u32	<illegal reg q9.5>, d6, d10
│ │ -	vrshr.u32	d19, d26, #28
│ │ +	vmlal.u32	<illegal reg q9.5>, d4, d1[1]
│ │  	vrsra.u64	<illegal reg q9.5>, q11, #26
│ │ -	vsubw.u32	<illegal reg q9.5>, q10, d18
│ │ +			@ <UNDEFINED> instruction: 0xffe433c9
│ │  	vsli.32	<illegal reg q9.5>, q7, #6
│ │  	vshr.u32	d17, d0, #28
│ │  	b.n	236e3e <uniffi_pbcli_checksum_method_api_base@@Base+0xca5ba>
│ │  	movs	r0, #1
│ │  	b.n	237082 <uniffi_pbcli_checksum_method_api_base@@Base+0xca7fe>
│ │  	vpmin.u<illegal width 64>	q7, <illegal reg q9.5>, <illegal reg q15.5>
│ │  	ldr	r7, [pc, #960]	@ (236d08 <uniffi_pbcli_checksum_method_api_base@@Base+0xca484>)
│ │ @@ -380587,15 +380587,15 @@
│ │  	asrs	r6, r0, #25
│ │  	add.w	r0, r1, r0, lsl #24
│ │  	b.n	237202 <uniffi_pbcli_checksum_method_api_base@@Base+0xca97e>
│ │  			@ <UNDEFINED> instruction: 0xffa9eaff
│ │  	str	r1, [r0, #0]
│ │  	b.n	23720a <uniffi_pbcli_checksum_method_api_base@@Base+0xca986>
│ │  			@ <UNDEFINED> instruction: 0xffa7eaff
│ │ -	adds	r0, #178	@ 0xb2
│ │ +	adds	r0, #217	@ 0xd9
│ │  			@ <UNDEFINED> instruction: 0xffe60b36
│ │  	vqshrun.s64	d20, q8, #27
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	236ff8 <uniffi_pbcli_checksum_method_api_base@@Base+0xca774>
│ │  	ands	r0, r0
│ │  	b.n	236e22 <uniffi_pbcli_checksum_method_api_base@@Base+0xca59e>
│ │  	movs	r4, r4
│ │ @@ -380695,17 +380695,17 @@
│ │  	movs	r0, #12
│ │  	b.n	2366f0 <uniffi_pbcli_checksum_method_api_base@@Base+0xc9e6c>
│ │  	movs	r0, r0
│ │  	b.n	236cd4 <uniffi_pbcli_checksum_method_api_base@@Base+0xca450>
│ │  	movs	r0, #2
│ │  	b.n	236cd8 <uniffi_pbcli_checksum_method_api_base@@Base+0xca454>
│ │  			@ <UNDEFINED> instruction: 0xffeaeaff
│ │ -	cmp	r7, #126	@ 0x7e
│ │ +	cmp	r7, #165	@ 0xa5
│ │  	vmlal.u32	<illegal reg q15.5>, d6, d5[0]
│ │ -	vqrdmlsh.s32	q9, q10, d14[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe42ff5
│ │  	vrshr.u64	d31, d5, #26
│ │  	vaddl.u32	q8, d4, d16
│ │  	b.n	2366f2 <uniffi_pbcli_checksum_method_api_base@@Base+0xc9e6e>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (236c98 <uniffi_pbcli_checksum_method_api_base@@Base+0xca414>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2370f8 <uniffi_pbcli_checksum_method_api_base@@Base+0xca874>
│ │ @@ -380813,17 +380813,17 @@
│ │  	b.n	237402 <uniffi_pbcli_checksum_method_api_base@@Base+0xcab7e>
│ │  	str	r0, [r0, #0]
│ │  	b.n	237406 <uniffi_pbcli_checksum_method_api_base@@Base+0xcab82>
│ │  	strh	r3, [r5, #6]
│ │  	add.w	r0, r2, r6
│ │  	b.n	23700e <uniffi_pbcli_checksum_method_api_base@@Base+0xca78a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r2, r3, r6, r7, r9, sl, fp, sp}
│ │ +	ldmia.w	sp!, {r0, r2, r4, r5, r6, r7, r9, sl, fp, sp}
│ │  			@ <UNDEFINED> instruction: 0xffe67bd0
│ │ -	vmull.p64	q9, d20, d6
│ │ +	vmull.p64	q9, d20, d29
│ │  			@ <UNDEFINED> instruction: 0xffe67b88
│ │  	vcvt.u32.f32	d31, d14, #28
│ │  	b.n	236f44 <uniffi_pbcli_checksum_method_api_base@@Base+0xca6c0>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r0, r0
│ │  	b.n	236812 <uniffi_pbcli_checksum_method_api_base@@Base+0xc9f8e>
│ │ @@ -380939,17 +380939,17 @@
│ │  	b.n	23712e <uniffi_pbcli_checksum_method_api_base@@Base+0xca8aa>
│ │  	movs	r0, #0
│ │  	b.n	237532 <uniffi_pbcli_checksum_method_api_base@@Base+0xcacae>
│ │  	strh	r0, [r4, #4]
│ │  	add.w	r0, r2, r0
│ │  	b.n	23753a <uniffi_pbcli_checksum_method_api_base@@Base+0xcacb6>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r1, r3, r4, r7, r8, sl, fp, sp}
│ │ +	ldmia.w	sp!, {r0, r6, r7, r8, sl, fp, sp}
│ │  	vabdl.u32	q13, d22, d24
│ │ -	vcvt.u16.f16	q9, q3, #27
│ │ +	vcvt.u16.f16	q9, <illegal reg q14.5>, #27
│ │  			@ <UNDEFINED> instruction: 0xffe6a764
│ │  	vqshrun.s64	d20, q8, #27
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	237330 <uniffi_pbcli_checksum_method_api_base@@Base+0xcaaac>
│ │  	asrs	r1, r0
│ │  	b.n	23741a <uniffi_pbcli_checksum_method_api_base@@Base+0xcab96>
│ │  	movs	r0, r0
│ │ @@ -381012,18 +381012,18 @@
│ │  	b.n	2371da <uniffi_pbcli_checksum_method_api_base@@Base+0xca956>
│ │  	movs	r0, #0
│ │  	b.n	2375de <uniffi_pbcli_checksum_method_api_base@@Base+0xcad5a>
│ │  	strh	r5, [r6, #2]
│ │  	add.w	r0, r2, r0
│ │  	b.n	2375e6 <uniffi_pbcli_checksum_method_api_base@@Base+0xcad62>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r5, r6, r7, sl, fp, sp}
│ │ -	vshr.u64	q8, <illegal reg q6.5>, #26
│ │ -	vmull.u32	q9, d22, d26
│ │ -	vshr.u64	d16, d9, #26
│ │ +	ldmia.w	sp!, {r0, r2, r4, r8, sl, fp, sp}
│ │ +	vaddw.u32	q8, q3, d4
│ │ +			@ <UNDEFINED> instruction: 0xffe62cd1
│ │ +	vmla.i32	q8, q11, d0[0]
│ │  	vaddl.u32	q8, d6, d1
│ │  	b.n	2375fe <uniffi_pbcli_checksum_method_api_base@@Base+0xcad7a>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r1, r0
│ │  	b.n	237606 <uniffi_pbcli_checksum_method_api_base@@Base+0xcad82>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r0, [pc, #960]	@ (23728c <uniffi_pbcli_checksum_method_api_base@@Base+0xcaa08>)
│ │ @@ -381746,15 +381746,15 @@
│ │  	ands	r0, r0
│ │  	b.n	237c62 <uniffi_pbcli_checksum_method_api_base@@Base+0xcb3de>
│ │  	ldrb	r4, [r2, #27]
│ │  	add.w	r0, r2, r4
│ │  	b.n	23786a <uniffi_pbcli_checksum_method_api_base@@Base+0xcafe6>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r1, r3, r8, ip, sp}
│ │ -			@ <UNDEFINED> instruction: 0xffe56b33
│ │ +			@ <UNDEFINED> instruction: 0xffe56b5a
│ │  	vmlal.u32	q10, d6, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	23787e <uniffi_pbcli_checksum_method_api_base@@Base+0xcaffa>
│ │  	movs	r4, r5
│ │  	b.n	237a42 <uniffi_pbcli_checksum_method_api_base@@Base+0xcb1be>
│ │  	movs	r0, r0
│ │  	b.n	237be8 <uniffi_pbcli_checksum_method_api_base@@Base+0xcb364>
│ │ @@ -389452,16 +389452,16 @@
│ │  	b.n	23bcf6 <uniffi_pbcli_checksum_method_api_base@@Base+0xcf472>
│ │  	ldr	r7, [r5, #104]	@ 0x68
│ │  	add.w	r0, r2, r0, lsl #20
│ │  	b.n	23b146 <uniffi_pbcli_checksum_method_api_base@@Base+0xce8c2>
│ │  	movs	r5, r0
│ │  	b.n	23b902 <uniffi_pbcli_checksum_method_api_base@@Base+0xcf07e>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r4, r8, r9, ip}
│ │ -	vsli.64	d24, d18, #38	@ 0x26
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r5, r8, r9, ip}
│ │ +	vsli.64	q12, <illegal reg q4.5>, #38	@ 0x26
│ │  	vqshrun.s64	d20, q8, #26
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	23baf0 <uniffi_pbcli_checksum_method_api_base@@Base+0xcf26c>
│ │  	b.n	23b5e0 <uniffi_pbcli_checksum_method_api_base@@Base+0xced5c>
│ │  	b.n	23b0fa <uniffi_pbcli_checksum_method_api_base@@Base+0xce876>
│ │  	stmia	r0!, {}
│ │  	b.n	23b91e <uniffi_pbcli_checksum_method_api_base@@Base+0xcf09a>
│ │ @@ -394614,24 +394614,24 @@
│ │  	movs	r0, #0
│ │  	b.n	23e926 <uniffi_pbcli_checksum_method_api_base@@Base+0xd20a2>
│ │  	str	r3, [r4, #56]	@ 0x38
│ │  	add.w	r0, r2, r0, lsl #16
│ │  	b.n	23e92e <uniffi_pbcli_checksum_method_api_base@@Base+0xd20aa>
│ │  			@ <UNDEFINED> instruction: 0xffd0eaff
│ │  	bmi.n	23e27c <uniffi_pbcli_checksum_method_api_base@@Base+0xd19f8>
│ │ -	vrshr.u32	d20, d13, #29
│ │ +	vmlal.u32	q10, d3, d4[0]
│ │  	vabal.u32	<illegal reg q14.5>, d6, d4
│ │ -	vrshr.u64	q10, <illegal reg q6.5>, #29
│ │ +	vsubw.u32	q10, <illegal reg q1.5>, d4
│ │  	vraddhn.i64	d29, q3, q2
│ │ -	vsra.u64	q10, <illegal reg q6.5>, #29
│ │ +	vsubl.u32	q10, d3, d4
│ │  	vsri.64	<illegal reg q14.5>, q4, #26
│ │ -	vrshr.u64	d20, d17, #29
│ │ +	vrshr.u64	q10, q4, #29
│ │  	vshll.u32	q12, d4, #6
│ │  	vsubw.u32	<illegal reg q14.5>, q11, d12
│ │ -	vmla.f32	q10, <illegal reg q1.5>, d5[1]
│ │ +	vaddw.u32	q10, <illegal reg q9.5>, d12
│ │  	vqshrun.s64	d20, q8, #26
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	23e740 <uniffi_pbcli_checksum_method_api_base@@Base+0xd1ebc>
│ │  	beq.n	23e238 <uniffi_pbcli_checksum_method_api_base@@Base+0xd19b4>
│ │  	b.n	23e6c4 <uniffi_pbcli_checksum_method_api_base@@Base+0xd1e40>
│ │  	movs	r0, #8
│ │  	b.n	23dd50 <uniffi_pbcli_checksum_method_api_base@@Base+0xd14cc>
│ │ @@ -396932,15 +396932,15 @@
│ │  	vmull.u32	q11, d19, d7
│ │  	vsra.u32	d28, d24, #28
│ │  	vmlsl.u32	q11, d3, d23
│ │  	vsra.u32	q14, q14, #28
│ │  	vmull.u32	q11, d3, d11[1]
│ │  	vaddw.u32	q14, q2, d12
│ │  			@ <UNDEFINED> instruction: 0xffe369fb
│ │ -	vaddw.u32	<illegal reg q12.5>, q10, d9
│ │ +	vsra.u64	d25, d16, #28
│ │  	vshr.u64	q14, q6, #27
│ │  	vmul.f32	q11, <illegal reg q9.5>, d11[0]
│ │  	vshr.u64	d28, d16, #28
│ │  			@ <UNDEFINED> instruction: 0xffe3699f
│ │  			@ <UNDEFINED> instruction: 0xffe47898
│ │  	vmlal.u32	<illegal reg q11.5>, d22, d16
│ │  	vshr.u32	q14, q12, #26
│ │ @@ -396984,15 +396984,15 @@
│ │  	strb	r4, [r4, #24]
│ │  	add.w	r0, r3, r0
│ │  	b.n	23fce8 <uniffi_pbcli_checksum_method_api_base@@Base+0xd3464>
│ │  	movs	r5, r0
│ │  	b.n	23f982 <uniffi_pbcli_checksum_method_api_base@@Base+0xd30fe>
│ │  			@ <UNDEFINED> instruction: 0xfff81aff
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r8, r9, sl, fp, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r5, r8, r9, sl, fp, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffe54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	23fb70 <uniffi_pbcli_checksum_method_api_base@@Base+0xd32ec>
│ │  	beq.n	23f6b0 <uniffi_pbcli_checksum_method_api_base@@Base+0xd2e2c>
│ │  	b.n	23faf4 <uniffi_pbcli_checksum_method_api_base@@Base+0xd3270>
│ │  	lsls	r0, r4, #2
│ │  	ldmia.w	r1, {sp, pc}
│ │ @@ -397743,18 +397743,18 @@
│ │  	b.n	240162 <uniffi_pbcli_checksum_method_api_base@@Base+0xd38de>
│ │  	movs	r0, r1
│ │  	b.n	23f76a <uniffi_pbcli_checksum_method_api_base@@Base+0xd2ee6>
│ │  	mrc2	10, 7, lr, cr14, cr15, {7}	@ <UNPREDICTABLE>
│ │  	ands	r0, r0
│ │  	b.n	2403ae <uniffi_pbcli_checksum_method_api_base@@Base+0xd3b2a>
│ │  	mrc2	10, 7, lr, cr13, cr15, {7}	@ <UNPREDICTABLE>
│ │ -	cdp2	15, 4, cr15, cr13, cr5, {7}
│ │ -	stc2	15, cr15, [r5, #-916]!	@ 0xfffffc6c
│ │ -	ldr??.w	pc, [r9, #4069]	@ 0xfe5
│ │ -			@ <UNDEFINED> instruction: 0xf929ffe5
│ │ +	cdp2	15, 7, cr15, cr4, cr5, {7}
│ │ +	stc2l	15, cr15, [ip, #-916]	@ 0xfffffc6c
│ │ +			@ <UNDEFINED> instruction: 0xfa20ffe5
│ │ +	ldr??.w	pc, [r0, #229]!
│ │  	ldr	r0, [pc, #192]	@ (23fd44 <uniffi_pbcli_checksum_method_api_base@@Base+0xd34c0>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2401a4 <uniffi_pbcli_checksum_method_api_base@@Base+0xd3920>
│ │  	stmia	r0!, {}
│ │  	b.n	23ffce <uniffi_pbcli_checksum_method_api_base@@Base+0xd374a>
│ │  	movs	r4, r0
│ │  	b.n	23f7b4 <uniffi_pbcli_checksum_method_api_base@@Base+0xd2f30>
│ │ @@ -397833,15 +397833,15 @@
│ │  	movs	r0, #4
│ │  	b.n	23f826 <uniffi_pbcli_checksum_method_api_base@@Base+0xd2fa2>
│ │  	movs	r0, #88	@ 0x58
│ │  	b.n	24046a <uniffi_pbcli_checksum_method_api_base@@Base+0xd3be6>
│ │  	ldr	r0, [pc, #192]	@ (23fdec <uniffi_pbcli_checksum_method_api_base@@Base+0xd3568>)
│ │  	ldmia.w	sp!, {r1, r2, r5, r6, sl, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xea038830
│ │ -	ldmia.w	sp!, {r0, r4, fp, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r3, r4, r5, fp, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffe54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	24025c <uniffi_pbcli_checksum_method_api_base@@Base+0xd39d8>
│ │  	beq.n	23fd6c <uniffi_pbcli_checksum_method_api_base@@Base+0xd34e8>
│ │  	b.n	2401e0 <uniffi_pbcli_checksum_method_api_base@@Base+0xd395c>
│ │  	stmia	r0!, {}
│ │  	b.n	23f86c <uniffi_pbcli_checksum_method_api_base@@Base+0xd2fe8>
│ │ @@ -398080,16 +398080,16 @@
│ │  	b.n	2403c4 <uniffi_pbcli_checksum_method_api_base@@Base+0xd3b40>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {}
│ │  	b.n	240676 <uniffi_pbcli_checksum_method_api_base@@Base+0xd3df2>
│ │  	beq.n	23ff70 <uniffi_pbcli_checksum_method_api_base@@Base+0xd36ec>
│ │  	b.n	2403d0 <uniffi_pbcli_checksum_method_api_base@@Base+0xd3b4c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r5, r8, r9, sl, ip, sp, lr, pc}
│ │ -	vrsubhn.i64	d31, <illegal reg q10.5>, <illegal reg q4.5>
│ │ +	ldmia.w	sp!, {r2, r5, r6, r8, r9, sl, ip, sp, lr, pc}
│ │ +	vqshlu.s64	d31, d16, #37	@ 0x25
│ │  	vqshrun.s64	d20, q8, #27
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	240468 <uniffi_pbcli_checksum_method_api_base@@Base+0xd3be4>
│ │  	stmia	r0!, {r3}
│ │  	b.n	23fa72 <uniffi_pbcli_checksum_method_api_base@@Base+0xd31ee>
│ │  	asrs	r0, r0, #32
│ │  	b.n	240296 <uniffi_pbcli_checksum_method_api_base@@Base+0xd3a12>
│ │ @@ -399539,43 +399539,43 @@
│ │  	b.n	240738 <uniffi_pbcli_checksum_method_api_base@@Base+0xd3eb4>
│ │  	movs	r0, r0
│ │  	b.n	240d1c <uniffi_pbcli_checksum_method_api_base@@Base+0xd4498>
│ │  	movs	r0, #2
│ │  	b.n	240d20 <uniffi_pbcli_checksum_method_api_base@@Base+0xd449c>
│ │  	vpmin.u32	q15, <illegal reg q9.5>, <illegal reg q15.5>
│ │  	add	r5, sp, #484	@ 0x1e4
│ │ -	vrsra.u32	<illegal reg q12.5>, q12, #29
│ │ +	vrsra.u64	d25, d15, #29
│ │  	vsubw.u32	<illegal reg q13.5>, <illegal reg q2.5>, d25
│ │  	vrshr.u32	<illegal reg q13.5>, <illegal reg q10.5>, #29
│ │  	vmla.f32	<illegal reg q13.5>, <illegal reg q9.5>, d13[0]
│ │  	vmull.u32	q13, d3, d1
│ │  	vmls.i32	q12, <illegal reg q1.5>, d11[0]
│ │  	vmla.f32	<illegal reg q13.5>, q2, d13[1]
│ │  			@ <UNDEFINED> instruction: 0xffe3abbd
│ │  	vraddhn.i64	d24, <illegal reg q1.5>, <illegal reg q3.5>
│ │  	vaddw.u32	<illegal reg q13.5>, q2, d21
│ │  	vqdmulh.s32	q13, <illegal reg q9.5>, d5[1]
│ │ -	vmlal.u32	<illegal reg q12.5>, d19, d4[1]
│ │ +	vsubw.u32	<illegal reg q12.5>, <illegal reg q1.5>, d11
│ │  	vmull.u32	q13, d5, d1[1]
│ │ -	vmla.i32	<illegal reg q12.5>, <illegal reg q1.5>, d0[1]
│ │ +	vaddl.u32	<illegal reg q12.5>, d19, d7
│ │  	vqrdmulh.s32	q13, <illegal reg q10.5>, d13[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe393ec
│ │ -	vcvt.u16.f16	d23, d3, #27
│ │ +	vsri.32	d25, d3, #29
│ │ +	vcvt.u16.f16	d23, d26, #27
│ │  			@ <UNDEFINED> instruction: 0xffe5a9b5
│ │ -			@ <UNDEFINED> instruction: 0xffe38fb4
│ │ +			@ <UNDEFINED> instruction: 0xffe38fdb
│ │  	vmul.f32	q13, <illegal reg q10.5>, d1[1]
│ │ -	vqrdmlsh.s32	q12, <illegal reg q9.5>, d0[1]
│ │ +	vaddl.u32	<illegal reg q12.5>, d3, d7
│ │  	vmlsl.u32	q13, d21, d13
│ │ -	vaddl.u32	<illegal reg q12.5>, d19, d12
│ │ +	vshr.u64	d25, d19, #29
│ │  	vqrshrn.u64	d26, <illegal reg q10.5>, #27
│ │ -	vcvt.u32.f32	q12, q10, #29
│ │ +			@ <UNDEFINED> instruction: 0xffe38f9b
│ │  			@ <UNDEFINED> instruction: 0xffe5ab49
│ │ -	vmla.f32	<illegal reg q12.5>, <illegal reg q1.5>, d8[0]
│ │ +	vmla.f32	<illegal reg q12.5>, <illegal reg q1.5>, d15[1]
│ │  	vmull.u32	q13, d21, d13[1]
│ │ -	vmla.i32	<illegal reg q12.5>, <illegal reg q9.5>, d12[1]
│ │ +	vsra.u32	d25, d3, #29
│ │  	vqshrun.s64	d20, q8, #27
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2411a0 <uniffi_pbcli_checksum_method_api_base@@Base+0xd491c>
│ │  	str	r0, [r0, r0]
│ │  	b.n	240fca <uniffi_pbcli_checksum_method_api_base@@Base+0xd4746>
│ │  	lsrs	r1, r0, #4
│ │  	b.n	241334 <uniffi_pbcli_checksum_method_api_base@@Base+0xd4ab0>
│ │ @@ -399982,16 +399982,16 @@
│ │  	b.n	24134a <uniffi_pbcli_checksum_method_api_base@@Base+0xd4ac6>
│ │  	ldc2	11, cr14, [r7], {255}	@ 0xff	@ <UNPREDICTABLE>
│ │  	movs	r5, r0
│ │  	b.n	241352 <uniffi_pbcli_checksum_method_api_base@@Base+0xd4ace>
│ │  	beq.n	24104c <uniffi_pbcli_checksum_method_api_base@@Base+0xd47c8>
│ │  	b.n	2414ac <uniffi_pbcli_checksum_method_api_base@@Base+0xd4c28>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r3, r5, sl, fp, sp}
│ │ -	vqdmulh.s32	q9, q11, d8[0]
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r6, sl, fp, sp}
│ │ +	vqdmulh.s32	q9, q11, d15[1]
│ │  			@ <UNDEFINED> instruction: 0xffe648f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	241544 <uniffi_pbcli_checksum_method_api_base@@Base+0xd4cc0>
│ │  	beq.n	24103c <uniffi_pbcli_checksum_method_api_base@@Base+0xd47b8>
│ │  	b.n	2414c8 <uniffi_pbcli_checksum_method_api_base@@Base+0xd4c44>
│ │  	ands	r1, r0
│ │  	b.n	241372 <uniffi_pbcli_checksum_method_api_base@@Base+0xd4aee>
│ │ @@ -400092,16 +400092,16 @@
│ │  	movs	r0, r3
│ │  	b.n	240c02 <uniffi_pbcli_checksum_method_api_base@@Base+0xd437e>
│ │  	movs	r7, r0
│ │  	b.n	24143e <uniffi_pbcli_checksum_method_api_base@@Base+0xd4bba>
│ │  	beq.n	241120 <uniffi_pbcli_checksum_method_api_base@@Base+0xd489c>
│ │  	b.n	241598 <uniffi_pbcli_checksum_method_api_base@@Base+0xd4d14>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r2, r8, r9, fp, sp}
│ │ -	vmlsl.u32	q9, d22, d28
│ │ +	ldmia.w	sp!, {r0, r1, r3, r5, r8, r9, fp, sp}
│ │ +			@ <UNDEFINED> instruction: 0xffe62ad3
│ │  			@ <UNDEFINED> instruction: 0xffe648f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	241630 <uniffi_pbcli_checksum_method_api_base@@Base+0xd4dac>
│ │  	beq.n	241188 <uniffi_pbcli_checksum_method_api_base@@Base+0xd4904>
│ │  	b.n	2415b4 <uniffi_pbcli_checksum_method_api_base@@Base+0xd4d30>
│ │  	str	r0, [r0, r0]
│ │  	b.n	24145e <uniffi_pbcli_checksum_method_api_base@@Base+0xd4bda>
│ │ @@ -401393,33 +401393,33 @@
│ │  	cbnz	r0, 241c3e <uniffi_pbcli_checksum_method_api_base@@Base+0xd53ba>
│ │  	movs	r1, r5
│ │  	cbnz	r4, 241c40 <uniffi_pbcli_checksum_method_api_base@@Base+0xd53bc>
│ │  	movs	r1, r5
│ │  	subs	r5, r5, r1
│ │  	vmlal.u32	<illegal reg q14.5>, d20, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffe389f3
│ │ -			@ <UNDEFINED> instruction: 0xffe3476c
│ │ -	vmull.u32	<illegal reg q12.5>, d21, d0
│ │ +	vqshl.u64	d20, d3, #35	@ 0x23
│ │ +	vmull.u32	<illegal reg q12.5>, d21, d23
│ │  	vmla.f32	<illegal reg q9.5>, <illegal reg q10.5>, d2[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe45b8f
│ │ -			@ <UNDEFINED> instruction: 0xffe59cbe
│ │ +			@ <UNDEFINED> instruction: 0xffe45bb6
│ │ +	vqdmulh.s32	<illegal reg q12.5>, <illegal reg q10.5>, d5[1]
│ │  	vmla.i32	<illegal reg q12.5>, <illegal reg q10.5>, d1[0]
│ │  	vmull.u32	q15, d4, d13[1]
│ │ -	vqrdmlsh.s32	<illegal reg q8.5>, <illegal reg q9.5>, d0[0]
│ │ +	vqrdmlsh.s32	<illegal reg q8.5>, <illegal reg q9.5>, d7[1]
│ │  	vmlsl.u32	q12, d22, d25
│ │  			@ <UNDEFINED> instruction: 0xffe4cd2f
│ │  	vqshlu.s32	<illegal reg q9.5>, q14, #3
│ │  	movs	r6, r4
│ │  	adds	r5, #92	@ 0x5c
│ │  	movs	r6, r4
│ │ -	movs	r0, #68	@ 0x44
│ │ +	movs	r0, #107	@ 0x6b
│ │  			@ <UNDEFINED> instruction: 0xffe6cb24
│ │ -			@ <UNDEFINED> instruction: 0xffe41ff4
│ │ +	vshr.u32	d18, d11, #28
│ │  			@ <UNDEFINED> instruction: 0xffe6cad4
│ │ -	vrsubhn.i64	d18, q2, q8
│ │ +	vmlsl.u32	q9, d4, d7[0]
│ │  	vaddw.u32	<illegal reg q14.5>, q3, d0
│ │  	vaddl.u32	<illegal reg q8.5>, d4, d12
│ │  	b.n	241766 <uniffi_pbcli_checksum_method_api_base@@Base+0xd4ee2>
│ │  	movs	r4, r2
│ │  	b.n	24176a <uniffi_pbcli_checksum_method_api_base@@Base+0xd4ee6>
│ │  	asrs	r0, r1, #32
│ │  	b.n	241770 <uniffi_pbcli_checksum_method_api_base@@Base+0xd4eec>
│ │ @@ -402163,24 +402163,24 @@
│ │  	movs	r0, #40	@ 0x28
│ │  	b.n	241dc0 <uniffi_pbcli_checksum_method_api_base@@Base+0xd553c>
│ │  	movs	r0, r0
│ │  	b.n	2423a4 <uniffi_pbcli_checksum_method_api_base@@Base+0xd5b20>
│ │  	movs	r0, #2
│ │  	b.n	2423a8 <uniffi_pbcli_checksum_method_api_base@@Base+0xd5b24>
│ │  	vpmin.u32	q15, q8, <illegal reg q15.5>
│ │ -	adds	r0, r4, #0
│ │ -	vaddw.u32	q14, q3, d4
│ │ -			@ <UNDEFINED> instruction: 0xffe51be4
│ │ +	adds	r7, r0, #1
│ │ +	vaddw.u32	q14, q3, d27
│ │ +	vmull.u32	<illegal reg q8.5>, d5, d11
│ │  	vqshlu.s64	q9, <illegal reg q0.5>, #38	@ 0x26
│ │ -	vmull.u32	<illegal reg q8.5>, d20, d12
│ │ -			@ <UNDEFINED> instruction: 0xffe61b6c
│ │ -	vshr.u32	q14, q0, #26
│ │ -			@ <UNDEFINED> instruction: 0xffe518f4
│ │ -			@ <UNDEFINED> instruction: 0xffe6bdd8
│ │ -	vqrshrn.u64	d17, q6, #27
│ │ +			@ <UNDEFINED> instruction: 0xffe41cb3
│ │ +			@ <UNDEFINED> instruction: 0xffe61b93
│ │ +	vshr.u32	q14, <illegal reg q11.5>, #26
│ │ +	vqshrn.u64	d17, <illegal reg q5.5>, #27
│ │ +			@ <UNDEFINED> instruction: 0xffe6bdff
│ │ +			@ <UNDEFINED> instruction: 0xffe51983
│ │  	vcvt.f16.u16	q10, q8, #26
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2427d8 <uniffi_pbcli_checksum_method_api_base@@Base+0xd5f54>
│ │  	ands	r0, r0
│ │  	b.n	242602 <uniffi_pbcli_checksum_method_api_base@@Base+0xd5d7e>
│ │  	str	r3, [r0, #0]
│ │  	b.n	242606 <uniffi_pbcli_checksum_method_api_base@@Base+0xd5d82>
│ │ @@ -402310,19 +402310,19 @@
│ │  	b.n	242b12 <uniffi_pbcli_checksum_method_api_base@@Base+0xd628e>
│ │  	str	r0, [r0, r0]
│ │  	b.n	242b16 <uniffi_pbcli_checksum_method_api_base@@Base+0xd6292>
│ │  	strh	r6, [r5, r2]
│ │  	add.w	r0, r0, r5
│ │  	b.n	24271e <uniffi_pbcli_checksum_method_api_base@@Base+0xd5e9a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r3, r6, fp, ip}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r5, r6, fp, ip}
│ │  	vrsra.u32	d24, d17, #26
│ │ -			@ <UNDEFINED> instruction: 0xffe417c8
│ │ +			@ <UNDEFINED> instruction: 0xffe417ef
│ │  			@ <UNDEFINED> instruction: 0xffe6799b
│ │ -	vqshl.u64	<illegal reg q8.5>, q8, #35	@ 0x23
│ │ +	vqshrun.s64	d17, <illegal reg q3.5>, #29
│ │  	vmul.f32	<illegal reg q11.5>, q11, d3[0]
│ │  			@ <UNDEFINED> instruction: 0xffe34df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	24291c <uniffi_pbcli_checksum_method_api_base@@Base+0xd6098>
│ │  	ands	r0, r0
│ │  	b.n	242746 <uniffi_pbcli_checksum_method_api_base@@Base+0xd5ec2>
│ │  	movs	r0, r0
│ │ @@ -403991,51 +403991,51 @@
│ │  	strh	r0, [r0, #0]
│ │  	b.n	24396e <uniffi_pbcli_checksum_method_api_base@@Base+0xd70ea>
│ │  	movs	r2, r0
│ │  	b.n	243932 <uniffi_pbcli_checksum_method_api_base@@Base+0xd70ae>
│ │  	lsls	r4, r0, #1
│ │  	b.n	242d3e <uniffi_pbcli_checksum_method_api_base@@Base+0xd64ba>
│ │  	vpmin.u8	q7, <illegal reg q13.5>, <illegal reg q15.5>
│ │ -	asrs	r0, r4, #19
│ │ +	asrs	r7, r0, #20
│ │  	vqrdmlsh.s32	q10, q3, d14[0]
│ │ -	vmls.i32	<illegal reg q8.5>, q2, d0[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe60b20
│ │ +	vraddhn.i64	d17, q10, <illegal reg q3.5>
│ │ +			@ <UNDEFINED> instruction: 0xffe60b47
│ │  	vabal.u32	q10, d22, d14
│ │ -			@ <UNDEFINED> instruction: 0xffe40cb4
│ │ +			@ <UNDEFINED> instruction: 0xffe40cdb
│ │  	vabdl.u32	q10, d6, d18
│ │ -	vmull.u32	q8, d20, d8[0]
│ │ +	vmull.u32	q8, d20, d15[1]
│ │  	vsli.32	d20, d22, #6
│ │ -			@ <UNDEFINED> instruction: 0xffe409b4
│ │ +			@ <UNDEFINED> instruction: 0xffe409db
│ │  	vraddhn.i64	d20, q3, q9
│ │ -	vqrdmlsh.s32	q8, q10, d12[0]
│ │ -	vqrdmlsh.s32	q8, q3, d8[1]
│ │ -	vqdmulh.s32	q8, q3, d8[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe40ff3
│ │ +			@ <UNDEFINED> instruction: 0xffe60f8f
│ │ +	vmull.u32	q8, d22, d15
│ │  	vqshlu.s64	q10, q3, #38	@ 0x26
│ │ -	vqdmulh.s32	q8, q2, d8[0]
│ │ +	vqdmulh.s32	q8, q2, d15[1]
│ │  	vqshlu.s64	d20, d22, #38	@ 0x26
│ │ -			@ <UNDEFINED> instruction: 0xffe40af4
│ │ +			@ <UNDEFINED> instruction: 0xffe40b1b
│ │  	vmls.f32	q10, q3, d2[1]
│ │ -	vmull.u32	q8, d4, d0[1]
│ │ +	vmlsl.u32	q8, d20, d7
│ │  	vmls.i32	q10, q11, d14[0]
│ │ -	vmlsl.u32	q8, d4, d24
│ │ +	vmull.u32	q8, d4, d15[0]
│ │  	vsri.64	d20, d6, #26
│ │ -			@ <UNDEFINED> instruction: 0xffe45347
│ │ -	vmul.f32	q8, <illegal reg q2.5>, d12[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe4536e
│ │ +			@ <UNDEFINED> instruction: 0xffe50993
│ │  	vrsra.u64	q10, q5, #26
│ │ -			@ <UNDEFINED> instruction: 0xffe40998
│ │ +			@ <UNDEFINED> instruction: 0xffe409bf
│ │  	vraddhn.i64	d20, q3, q3
│ │ -	vmull.u32	q8, d4, d4
│ │ +	vmull.u32	q8, d4, d27
│ │  	vqshlu.s32	q10, q9, #6
│ │ -			@ <UNDEFINED> instruction: 0xffe40bcc
│ │ +			@ <UNDEFINED> instruction: 0xffe40bf3
│ │  	vqshlu.s32	d20, d26, #6
│ │ -			@ <UNDEFINED> instruction: 0xffe40b74
│ │ +			@ <UNDEFINED> instruction: 0xffe40b9b
│ │  	vmls.f32	q10, q11, d2[1]
│ │ -	vqdmulh.s32	q8, q10, d4[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe40d0b
│ │  	vqshl.u32	q10, q1, #6
│ │ -			@ <UNDEFINED> instruction: 0xffe40b4c
│ │ +			@ <UNDEFINED> instruction: 0xffe40b73
│ │  	vsli.64	d20, d26, #38	@ 0x26
│ │  	vaddl.u32	<illegal reg q8.5>, d4, d0
│ │  	b.n	242df6 <uniffi_pbcli_checksum_method_api_base@@Base+0xd6572>
│ │  	asrs	r4, r1, #32
│ │  	b.n	242dfc <uniffi_pbcli_checksum_method_api_base@@Base+0xd6578>
│ │  	asrs	r4, r6, #1
│ │  	b.n	242e00 <uniffi_pbcli_checksum_method_api_base@@Base+0xd657c>
│ │ @@ -407914,15 +407914,15 @@
│ │  			@ <UNDEFINED> instruction: 0xffe3af01
│ │  			@ <UNDEFINED> instruction: 0xffe43340
│ │  	vqrdmlah.s32	q13, <illegal reg q9.5>, d5[1]
│ │  	vshr.u64	<illegal reg q9.5>, q14, #28
│ │  	vmull.u32	q13, d19, d17
│ │  	vsri.64	d19, d12, #28
│ │  	vmla.i32	<illegal reg q13.5>, <illegal reg q1.5>, d1[0]
│ │ -	vqdmulh.s32	<illegal reg q8.5>, q2, d3[1]
│ │ +	vmull.u32	<illegal reg q8.5>, d20, d10
│ │  	vmla.i32	<illegal reg q9.5>, <illegal reg q2.5>, d4[0]
│ │  			@ <UNDEFINED> instruction: 0xffe3abe9
│ │  			@ <UNDEFINED> instruction: 0xffe44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	245a00 <uniffi_pbcli_checksum_method_api_base@@Base+0xd917c>
│ │  	beq.n	2455a0 <uniffi_pbcli_checksum_method_api_base@@Base+0xd8d1c>
│ │  	b.n	245984 <uniffi_pbcli_checksum_method_api_base@@Base+0xd9100>
│ │ @@ -408169,15 +408169,15 @@
│ │  	b.n	245a42 <uniffi_pbcli_checksum_method_api_base@@Base+0xd91be>
│ │  	beq.n	24573c <uniffi_pbcli_checksum_method_api_base@@Base+0xd8eb8>
│ │  	b.n	245b9c <uniffi_pbcli_checksum_method_api_base@@Base+0xd9318>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {lr}
│ │  	b.n	245e4e <uniffi_pbcli_checksum_method_api_base@@Base+0xd95ca>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │ -			@ <UNDEFINED> instruction: 0xfb47ffe5
│ │ +			@ <UNDEFINED> instruction: 0xfb6effe5
│ │  	ldr	r4, [pc, #64]	@ (245758 <uniffi_pbcli_checksum_method_api_base@@Base+0xd8ed4>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	245c38 <uniffi_pbcli_checksum_method_api_base@@Base+0xd93b4>
│ │  	asrs	r4, r3, #32
│ │  	b.n	245260 <uniffi_pbcli_checksum_method_api_base@@Base+0xd89dc>
│ │  	ands	r0, r0
│ │  	b.n	245a66 <uniffi_pbcli_checksum_method_api_base@@Base+0xd91e2>
│ │ @@ -408189,15 +408189,15 @@
│ │  	b.n	245850 <uniffi_pbcli_checksum_method_api_base@@Base+0xd8fcc>
│ │  	ldrb	r5, [r4, r7]
│ │  	add.w	r0, r3, r0
│ │  	b.n	245e7a <uniffi_pbcli_checksum_method_api_base@@Base+0xd95f6>
│ │  	movs	r0, r0
│ │  	b.n	245246 <uniffi_pbcli_checksum_method_api_base@@Base+0xd89c2>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r6, r8, fp, pc}
│ │ +	ldmia.w	sp!, {r3, r5, r6, r8, fp, pc}
│ │  	vaddl.u32	q9, d5, d0
│ │  	b.n	24526c <uniffi_pbcli_checksum_method_api_base@@Base+0xd89e8>
│ │  	asrs	r4, r0, #32
│ │  	b.n	245270 <uniffi_pbcli_checksum_method_api_base@@Base+0xd89ec>
│ │  	asrs	r6, r4, #32
│ │  	b.n	245252 <uniffi_pbcli_checksum_method_api_base@@Base+0xd89ce>
│ │  	movs	r0, #34	@ 0x22
│ │ @@ -408344,16 +408344,16 @@
│ │  	add.w	r0, r2, r1
│ │  	b.n	245f36 <uniffi_pbcli_checksum_method_api_base@@Base+0xd96b2>
│ │  	movs	r4, r2
│ │  	add	r5, pc, #564	@ (adr r5, 245acc <uniffi_pbcli_checksum_method_api_base@@Base+0xd9248>)
│ │  			@ <UNDEFINED> instruction: 0xffcbeaff
│ │  	ldrb	r6, [r3, #1]
│ │  			@ <UNDEFINED> instruction: 0xffe32beb
│ │ -	vqshrun.s64	d24, <illegal reg q2.5>, #29
│ │ -	vmull.u32	q14, d21, d7[1]
│ │ +	vqshrun.s64	d24, q14, #29
│ │ +			@ <UNDEFINED> instruction: 0xffe5cb0e
│ │  	vmlal.u32	q10, d5, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	245bf6 <uniffi_pbcli_checksum_method_api_base@@Base+0xd9372>
│ │  			@ <UNDEFINED> instruction: 0xb63f
│ │  			@ <UNDEFINED> instruction: 0xeb02b5a9
│ │  	add.w	lr, r2, sl, asr #8
│ │  	b.n	245d42 <uniffi_pbcli_checksum_method_api_base@@Base+0xd94be>
│ │ @@ -408589,19 +408589,19 @@
│ │  	b.n	245df6 <uniffi_pbcli_checksum_method_api_base@@Base+0xd9572>
│ │  	beq.n	245b18 <uniffi_pbcli_checksum_method_api_base@@Base+0xd9294>
│ │  	b.n	245f50 <uniffi_pbcli_checksum_method_api_base@@Base+0xd96cc>
│ │  	ldrh	r4, [r0, #24]
│ │  	ldc	0, cr13, [sp], #16
│ │  	b.n	245fdc <uniffi_pbcli_checksum_method_api_base@@Base+0xd9758>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r4, r5, r6, r7, r9, sl, pc}
│ │ -	vqshlu.s64	q12, <illegal reg q2.5>, #37	@ 0x25
│ │ -	vmls.f32	q12, <illegal reg q10.5>, d5[1]
│ │ +	ldmia.w	sp!, {r3, r4, r8, r9, sl, pc}
│ │ +	vqshlu.s64	q12, q14, #37	@ 0x25
│ │ +	vrsubhn.i64	d24, <illegal reg q2.5>, q6
│ │  	vrshr.u64	d22, d3, #27
│ │ -	vqshlu.s32	q12, <illegal reg q0.5>, #4
│ │ +	vqshlu.s32	q12, q12, #4
│ │  	vcvt.f16.u16	q10, q8, #27
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	245ffc <uniffi_pbcli_checksum_method_api_base@@Base+0xd9778>
│ │  	ands	r0, r0
│ │  	b.n	245e26 <uniffi_pbcli_checksum_method_api_base@@Base+0xd95a2>
│ │  	lsls	r0, r4, #15
│ │  	b.n	24560a <uniffi_pbcli_checksum_method_api_base@@Base+0xd8d86>
│ │ @@ -408690,16 +408690,16 @@
│ │  	b.n	2462da <uniffi_pbcli_checksum_method_api_base@@Base+0xd9a56>
│ │  	str	r0, [r0, r0]
│ │  	b.n	2462de <uniffi_pbcli_checksum_method_api_base@@Base+0xd9a5a>
│ │  	mcr2	11, 7, lr, cr13, cr15, {7}	@ <UNPREDICTABLE>
│ │  	movs	r5, r0
│ │  	b.n	245ee6 <uniffi_pbcli_checksum_method_api_base@@Base+0xd9662>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r4, r5, r8, sl, pc}
│ │ -	vsri.64	q12, <illegal reg q10.5>, #27
│ │ +	ldmia.w	sp!, {r3, r4, r6, r8, sl, pc}
│ │ +	vsli.32	d24, d12, #5
│ │  	vmla.f32	q10, <illegal reg q10.5>, d8[1]
│ │  			@ <UNDEFINED> instruction: 0xffe34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2460d8 <uniffi_pbcli_checksum_method_api_base@@Base+0xd9854>
│ │  	beq.n	245bd8 <uniffi_pbcli_checksum_method_api_base@@Base+0xd9354>
│ │  	b.n	24605c <uniffi_pbcli_checksum_method_api_base@@Base+0xd97d8>
│ │  	str	r0, [sp, #0]
│ │ @@ -409097,21 +409097,21 @@
│ │  	lsrs	r4, r1, #6
│ │  	b.n	245a1a <uniffi_pbcli_checksum_method_api_base@@Base+0xd9196>
│ │  	lsrs	r0, r2, #6
│ │  	b.n	245a1e <uniffi_pbcli_checksum_method_api_base@@Base+0xd919a>
│ │  	lsls	r0, r4, #15
│ │  	b.n	245a22 <uniffi_pbcli_checksum_method_api_base@@Base+0xd919e>
│ │  			@ <UNDEFINED> instruction: 0xff8beaff
│ │ -	strh	r5, [r6, #28]
│ │ -	vmlal.u32	<illegal reg q12.5>, d21, d1
│ │ -	vrsra.u32	q12, <illegal reg q10.5>, #27
│ │ -	vmul.i32	<illegal reg q12.5>, <illegal reg q2.5>, d1[0]
│ │ -	vsubl.u32	q12, d5, d9
│ │ -	vqshlu.s64	<illegal reg q12.5>, <illegal reg q2.5>, #37	@ 0x25
│ │ -	vmla.f32	q12, <illegal reg q2.5>, d13[1]
│ │ +	strh	r4, [r3, #30]
│ │ +	vmlal.u32	<illegal reg q12.5>, d21, d24
│ │ +	vrsra.u64	d24, d12, #27
│ │ +	vmul.i32	<illegal reg q12.5>, <illegal reg q2.5>, d8[1]
│ │ +	vrshr.u32	d24, d16, #27
│ │ +	vqshlu.s64	<illegal reg q12.5>, q14, #37	@ 0x25
│ │ +	vsra.u64	d24, d4, #27
│ │  	vcvt.f16.u16	d20, d0, #27
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	24645c <uniffi_pbcli_checksum_method_api_base@@Base+0xd9bd8>
│ │  	ands	r0, r0
│ │  	b.n	246286 <uniffi_pbcli_checksum_method_api_base@@Base+0xd9a02>
│ │  	movs	r0, r6
│ │  	b.n	245aea <uniffi_pbcli_checksum_method_api_base@@Base+0xd9266>
│ │ @@ -409138,15 +409138,15 @@
│ │  	lsrs	r4, r1, #6
│ │  	b.n	245a82 <uniffi_pbcli_checksum_method_api_base@@Base+0xd91fe>
│ │  	lsrs	r0, r2, #6
│ │  	b.n	245a86 <uniffi_pbcli_checksum_method_api_base@@Base+0xd9202>
│ │  	lsls	r0, r4, #15
│ │  	b.n	245a8a <uniffi_pbcli_checksum_method_api_base@@Base+0xd9206>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r2, r8, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r5, r8, pc}
│ │  			@ <UNDEFINED> instruction: 0xffe54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2464ac <uniffi_pbcli_checksum_method_api_base@@Base+0xd9c28>
│ │  	beq.n	24605c <uniffi_pbcli_checksum_method_api_base@@Base+0xd97d8>
│ │  	b.n	246430 <uniffi_pbcli_checksum_method_api_base@@Base+0xd9bac>
│ │  	add	r0, pc, #0	@ (adr r0, 245f98 <uniffi_pbcli_checksum_method_api_base@@Base+0xd9714>)
│ │  	b.n	2462da <uniffi_pbcli_checksum_method_api_base@@Base+0xd9a56>
│ │ @@ -410365,49 +410365,49 @@
│ │  	b.n	246b08 <uniffi_pbcli_checksum_method_api_base@@Base+0xda284>
│ │  	adcs	r5, r4
│ │  	add.w	r0, r2, r6, lsl #8
│ │  	b.n	246ff2 <uniffi_pbcli_checksum_method_api_base@@Base+0xda76e>
│ │  	movs	r0, #8
│ │  	b.n	247076 <uniffi_pbcli_checksum_method_api_base@@Base+0xda7f2>
│ │  	mrc2	10, 2, lr, cr11, cr15, {7}	@ <UNPREDICTABLE>
│ │ -	ldrb	r5, [r7, #0]
│ │ -			@ <UNDEFINED> instruction: 0xffe5bb30
│ │ -			@ <UNDEFINED> instruction: 0xffe57ad1
│ │ -	vqrdmulh.s32	<illegal reg q13.5>, <illegal reg q10.5>, d4[0]
│ │ -	vqrdmulh.s32	<illegal reg q11.5>, <illegal reg q10.5>, d9[0]
│ │ -	vshr.u64	d28, d28, #27
│ │ -			@ <UNDEFINED> instruction: 0xffe577e1
│ │ -			@ <UNDEFINED> instruction: 0xffe5bad4
│ │ -	vqshl.u64	d23, d17, #37	@ 0x25
│ │ -	vmlsl.u32	<illegal reg q13.5>, d21, d20
│ │ -	vqshl.u32	<illegal reg q11.5>, <illegal reg q4.5>, #5
│ │ -	vmull.u32	<illegal reg q13.5>, d5, d12[0]
│ │ -	vabdl.u32	<illegal reg q11.5>, d21, d5
│ │ -			@ <UNDEFINED> instruction: 0xffe5ba78
│ │ -	vmul.i32	<illegal reg q11.5>, <illegal reg q10.5>, d5[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe5bbd8
│ │ -	vrsubhn.i64	d23, <illegal reg q10.5>, <illegal reg q6.5>
│ │ -			@ <UNDEFINED> instruction: 0xffe5b980
│ │ -			@ <UNDEFINED> instruction: 0xffe578b9
│ │ -			@ <UNDEFINED> instruction: 0xffe5bbac
│ │ -			@ <UNDEFINED> instruction: 0xffe57b5d
│ │ -	vcvt.f32.u32	<illegal reg q13.5>, q0, #27
│ │ -	vqrdmulh.s32	<illegal reg q11.5>, <illegal reg q2.5>, d1[0]
│ │ -	vcvt.u16.f16	d23, d13, #27
│ │ -	vshr.u32	d28, d0, #27
│ │ -			@ <UNDEFINED> instruction: 0xffe579f5
│ │ -	vqdmulh.s32	<illegal reg q13.5>, <illegal reg q10.5>, d8[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe57b31
│ │ -	vmull.p64	<illegal reg q13.5>, d5, d20
│ │ -	vmul.i32	<illegal reg q11.5>, <illegal reg q2.5>, d9[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe5bb5c
│ │ -			@ <UNDEFINED> instruction: 0xffe57b9d
│ │ -			@ <UNDEFINED> instruction: 0xffe5be90
│ │ -			@ <UNDEFINED> instruction: 0xffe579b9
│ │ -	vqrshrn.u64	d23, <illegal reg q12.5>, #27
│ │ +	ldrb	r4, [r4, #1]
│ │ +			@ <UNDEFINED> instruction: 0xffe5bb57
│ │ +			@ <UNDEFINED> instruction: 0xffe57af8
│ │ +	vqrdmulh.s32	<illegal reg q13.5>, <illegal reg q10.5>, d11[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe57df0
│ │ +	vmla.i32	q14, <illegal reg q10.5>, d3[1]
│ │ +	vmlal.u32	<illegal reg q11.5>, d5, d8
│ │ +			@ <UNDEFINED> instruction: 0xffe5bafb
│ │ +	vqshl.u64	<illegal reg q11.5>, q4, #37	@ 0x25
│ │ +	vmull.u32	<illegal reg q13.5>, d21, d11[0]
│ │ +	vabdl.u32	<illegal reg q11.5>, d21, d0
│ │ +			@ <UNDEFINED> instruction: 0xffe5ba73
│ │ +	vabdl.u32	<illegal reg q11.5>, d21, d28
│ │ +			@ <UNDEFINED> instruction: 0xffe5ba9f
│ │ +			@ <UNDEFINED> instruction: 0xffe5790c
│ │ +			@ <UNDEFINED> instruction: 0xffe5bbff
│ │ +	vqshlu.s64	d23, d20, #37	@ 0x25
│ │ +			@ <UNDEFINED> instruction: 0xffe5b9a7
│ │ +	vmul.i32	<illegal reg q11.5>, <illegal reg q10.5>, d0[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe5bbd3
│ │ +			@ <UNDEFINED> instruction: 0xffe57b84
│ │ +	vcvt.f32.u32	<illegal reg q13.5>, <illegal reg q11.5>, #27
│ │ +	vqrdmulh.s32	<illegal reg q11.5>, <illegal reg q2.5>, d8[1]
│ │ +	vqrdmulh.s32	<illegal reg q11.5>, <illegal reg q2.5>, d4[0]
│ │ +	vshr.u32	d28, d23, #27
│ │ +	vshll.u32	<illegal reg q11.5>, d12, #5
│ │ +			@ <UNDEFINED> instruction: 0xffe5bd0f
│ │ +			@ <UNDEFINED> instruction: 0xffe57b58
│ │ +	vqrdmlah.s32	<illegal reg q13.5>, <illegal reg q2.5>, d11[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe57890
│ │ +			@ <UNDEFINED> instruction: 0xffe5bb83
│ │ +			@ <UNDEFINED> instruction: 0xffe57bc4
│ │ +			@ <UNDEFINED> instruction: 0xffe5beb7
│ │ +	vmul.f32	<illegal reg q11.5>, <illegal reg q10.5>, d0[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe579a0
│ │  	vqshrun.s64	d20, q8, #27
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	246fa8 <uniffi_pbcli_checksum_method_api_base@@Base+0xda724>
│ │  	ands	r0, r0
│ │  	b.n	246dd2 <uniffi_pbcli_checksum_method_api_base@@Base+0xda54e>
│ │  	lsrs	r0, r1, #7
│ │  	b.n	2465b6 <uniffi_pbcli_checksum_method_api_base@@Base+0xd9d32>
│ │ @@ -410464,18 +410464,18 @@
│ │  	b.n	246e46 <uniffi_pbcli_checksum_method_api_base@@Base+0xda5c2>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0}
│ │  	b.n	24724e <uniffi_pbcli_checksum_method_api_base@@Base+0xda9ca>
│ │  	adds	r4, r1, r7
│ │  	b.n	24661a <uniffi_pbcli_checksum_method_api_base@@Base+0xd9d96>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r4, r7, r8, sl, ip, sp, lr}
│ │ -	vsri.64	d16, d19, #27
│ │ -	vabal.u32	<illegal reg q11.5>, d21, d29
│ │ -	vmls.i32	q8, <illegal reg q10.5>, d15[0]
│ │ +	ldmia.w	sp!, {r3, r4, r5, r7, r8, sl, ip, sp, lr}
│ │ +	vsri.64	q8, q5, #27
│ │ +	vsli.64	<illegal reg q11.5>, q2, #37	@ 0x25
│ │ +	vsri.64	q8, q11, #27
│ │  	vqshrun.s64	d20, q8, #27
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	247048 <uniffi_pbcli_checksum_method_api_base@@Base+0xda7c4>
│ │  	ands	r0, r0
│ │  	b.n	246e72 <uniffi_pbcli_checksum_method_api_base@@Base+0xda5ee>
│ │  	movs	r4, r1
│ │  	b.n	246656 <uniffi_pbcli_checksum_method_api_base@@Base+0xd9dd2>
│ │ @@ -410538,17 +410538,17 @@
│ │  	b.n	2471b2 <uniffi_pbcli_checksum_method_api_base@@Base+0xda92e>
│ │  	adds	r0, #0
│ │  	b.n	2472f6 <uniffi_pbcli_checksum_method_api_base@@Base+0xdaa72>
│ │  			@ <UNDEFINED> instruction: 0xfae7ebff
│ │  	movs	r5, r0
│ │  	b.n	246efe <uniffi_pbcli_checksum_method_api_base@@Base+0xda67a>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r6, r7, sl, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r8, sl, ip, sp, lr}
│ │  	vmul.f32	q13, <illegal reg q10.5>, d5[0]
│ │ -	vabal.u32	<illegal reg q11.5>, d4, d9
│ │ +	vsli.32	d23, d16, #4
│ │  			@ <UNDEFINED> instruction: 0xffe5a9f5
│ │  	vaddl.u32	q8, d4, d0
│ │  	b.n	247316 <uniffi_pbcli_checksum_method_api_base@@Base+0xdaa92>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r4, [pc, #448]	@ (246d9c <uniffi_pbcli_checksum_method_api_base@@Base+0xda518>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2470fc <uniffi_pbcli_checksum_method_api_base@@Base+0xda878>
│ │ @@ -410627,17 +410627,17 @@
│ │  	b.n	2473c2 <uniffi_pbcli_checksum_method_api_base@@Base+0xdab3e>
│ │  	adds	r0, #0
│ │  	b.n	2473c6 <uniffi_pbcli_checksum_method_api_base@@Base+0xdab42>
│ │  			@ <UNDEFINED> instruction: 0xfab3ebff
│ │  	movs	r5, r0
│ │  	b.n	246fce <uniffi_pbcli_checksum_method_api_base@@Base+0xda74a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r3, r5, r6, sl, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r4, r7, sl, ip, sp, lr}
│ │  	vsri.32	d22, d26, #27
│ │ -	vraddhn.i64	d23, <illegal reg q1.5>, <illegal reg q10.5>
│ │ +	vmls.i32	<illegal reg q11.5>, <illegal reg q1.5>, d12[0]
│ │  	vrsra.u64	q11, q11, #27
│ │  			@ <UNDEFINED> instruction: 0xffe348f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2471c4 <uniffi_pbcli_checksum_method_api_base@@Base+0xda940>
│ │  	beq.n	246cbc <uniffi_pbcli_checksum_method_api_base@@Base+0xda438>
│ │  	b.n	247148 <uniffi_pbcli_checksum_method_api_base@@Base+0xda8c4>
│ │  	str	r1, [r0, #0]
│ │ @@ -410738,18 +410738,18 @@
│ │  	b.n	2474ba <uniffi_pbcli_checksum_method_api_base@@Base+0xdac36>
│ │  			@ <UNDEFINED> instruction: 0xfa76ebff
│ │  	movs	r6, r0
│ │  	b.n	2470c2 <uniffi_pbcli_checksum_method_api_base@@Base+0xda83e>
│ │  	beq.n	246da4 <uniffi_pbcli_checksum_method_api_base@@Base+0xda520>
│ │  	b.n	24721c <uniffi_pbcli_checksum_method_api_base@@Base+0xda998>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r4, r8, r9, ip, sp, lr}
│ │ -	vrsra.u64	d20, d13, #27
│ │ -			@ <UNDEFINED> instruction: 0xffe57345
│ │ -			@ <UNDEFINED> instruction: 0xffe543cd
│ │ +	ldmia.w	sp!, {r2, r3, r4, r5, r8, r9, ip, sp, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffe543c4
│ │ +			@ <UNDEFINED> instruction: 0xffe5736c
│ │ +	vrsra.u64	q10, q10, #27
│ │  			@ <UNDEFINED> instruction: 0xffe54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2472bc <uniffi_pbcli_checksum_method_api_base@@Base+0xdaa38>
│ │  	beq.n	246dac <uniffi_pbcli_checksum_method_api_base@@Base+0xda528>
│ │  	b.n	247240 <uniffi_pbcli_checksum_method_api_base@@Base+0xda9bc>
│ │  	strh	r4, [r2, #0]
│ │  	b.n	2468e0 <uniffi_pbcli_checksum_method_api_base@@Base+0xda05c>
│ │ @@ -410872,15 +410872,15 @@
│ │  	b.n	2475e2 <uniffi_pbcli_checksum_method_api_base@@Base+0xdad5e>
│ │  			@ <UNDEFINED> instruction: 0xfa2cebff
│ │  	movs	r1, r0
│ │  	b.n	24766a <uniffi_pbcli_checksum_method_api_base@@Base+0xdade6>
│ │  	beq.n	246ee4 <uniffi_pbcli_checksum_method_api_base@@Base+0xda660>
│ │  	b.n	247344 <uniffi_pbcli_checksum_method_api_base@@Base+0xdaac0>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r3, r5, r6, r7, r8, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r4, r9, ip, sp, lr}
│ │  	vqrdmlsh.s32	<illegal reg q8.5>, <illegal reg q2.5>, d6[1]
│ │  			@ <UNDEFINED> instruction: 0xffe448f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2473dc <uniffi_pbcli_checksum_method_api_base@@Base+0xdab58>
│ │  	ands	r0, r0
│ │  	b.n	247206 <uniffi_pbcli_checksum_method_api_base@@Base+0xda982>
│ │  	lsrs	r0, r0, #6
│ │ @@ -411022,17 +411022,17 @@
│ │  	add.w	r0, r2, r4
│ │  	b.n	247332 <uniffi_pbcli_checksum_method_api_base@@Base+0xdaaae>
│ │  	asrs	r0, r2, #1
│ │  	b.n	247736 <uniffi_pbcli_checksum_method_api_base@@Base+0xdaeb2>
│ │  	movs	r1, #61	@ 0x3d
│ │  	b.n	2475fa <uniffi_pbcli_checksum_method_api_base@@Base+0xdad76>
│ │  			@ <UNDEFINED> instruction: 0xffcbeaff
│ │ -	strb	r5, [r1, #2]
│ │ +	strb	r4, [r6, #2]
│ │  			@ <UNDEFINED> instruction: 0xffe5ee9a
│ │ -	vsra.u32	<illegal reg q11.5>, <illegal reg q6.5>, #29
│ │ +	vaddw.u32	<illegal reg q11.5>, <illegal reg q9.5>, d4
│ │  	vqrdmlsh.s32	q15, <illegal reg q2.5>, d10[1]
│ │  	vcvt.f16.u16	q10, q8, #29
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	247530 <uniffi_pbcli_checksum_method_api_base@@Base+0xdacac>
│ │  	str	r1, [r0, r0]
│ │  	b.n	24735a <uniffi_pbcli_checksum_method_api_base@@Base+0xdaad6>
│ │  	asrs	r0, r7, #5
│ │ @@ -411204,18 +411204,18 @@
│ │  	subs	r7, #185	@ 0xb9
│ │  	add.w	r0, r2, r6
│ │  	b.n	2474d6 <uniffi_pbcli_checksum_method_api_base@@Base+0xdac52>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r3, r4, r8, sl, fp, ip, sp, pc}
│ │  	vabal.u32	<illegal reg q11.5>, d19, d8
│ │  	vcvt.f16.u16	q9, <illegal reg q3.5>, #29
│ │ -	vmla.i32	q10, <illegal reg q1.5>, d0[1]
│ │ +	vaddl.u32	q10, d19, d7
│ │  	vsli.64	d29, d18, #37	@ 0x25
│ │ -			@ <UNDEFINED> instruction: 0xffe3e9b4
│ │ -			@ <UNDEFINED> instruction: 0xffe46efd
│ │ +			@ <UNDEFINED> instruction: 0xffe3e9db
│ │ +			@ <UNDEFINED> instruction: 0xffe46f24
│ │  	vqrdmulh.s32	<illegal reg q13.5>, <illegal reg q2.5>, d9[1]
│ │  			@ <UNDEFINED> instruction: 0xffe34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2476dc <uniffi_pbcli_checksum_method_api_base@@Base+0xdae58>
│ │  	beq.n	2471fc <uniffi_pbcli_checksum_method_api_base@@Base+0xda978>
│ │  	b.n	247660 <uniffi_pbcli_checksum_method_api_base@@Base+0xdaddc>
│ │  	strb	r1, [r0, #0]
│ │ @@ -411663,24 +411663,24 @@
│ │  	b.n	2478d6 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb052>
│ │  	movs	r5, r3
│ │  	add.w	r0, r0, r1
│ │  	b.n	247d5e <uniffi_pbcli_checksum_method_api_base@@Base+0xdb4da>
│ │  	beq.n	2475d8 <uniffi_pbcli_checksum_method_api_base@@Base+0xdad54>
│ │  	b.n	247a38 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb1b4>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r3, r4, r7, r9, sl, fp, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffe5fb67
│ │ +	ldmia.w	sp!, {r6, r7, r9, sl, fp, sp, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffe5fb8e
│ │  	vqdmulh.s32	q12, q2, d9[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe36af9
│ │ +			@ <UNDEFINED> instruction: 0xffe36b20
│ │  			@ <UNDEFINED> instruction: 0xffe589fd
│ │  			@ <UNDEFINED> instruction: 0xffe46fd3
│ │ -	vcvt.f16.u16	<illegal reg q9.5>, q7, #29
│ │ +	vmull.u32	<illegal reg q9.5>, d19, d5
│ │  	vsra.u64	d19, d17, #27
│ │  	vqrdmlsh.s32	q14, q10, d2[0]
│ │ -	vmul.f32	<illegal reg q15.5>, <illegal reg q1.5>, d10[0]
│ │ +	vqrshrn.u64	d31, <illegal reg q8.5>, #29
│ │  	vqshrun.s64	d20, q8, #28
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	247af0 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb26c>
│ │  	ands	r1, r0
│ │  	b.n	24791a <uniffi_pbcli_checksum_method_api_base@@Base+0xdb096>
│ │  	str	r0, [r0, r0]
│ │  	b.n	24791e <uniffi_pbcli_checksum_method_api_base@@Base+0xdb09a>
│ │ @@ -411845,19 +411845,19 @@
│ │  	b.n	247a86 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb202>
│ │  	movs	r5, #186	@ 0xba
│ │  	b.n	247d4a <uniffi_pbcli_checksum_method_api_base@@Base+0xdb4c6>
│ │  	asrs	r1, r0, #32
│ │  	b.n	24786c <uniffi_pbcli_checksum_method_api_base@@Base+0xdafe8>
│ │  	ldr	r3, [pc, #960]	@ (247b10 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb28c>)
│ │  	ldmia.w	sp!, {r0, r2, r3, r4, r6, r7, r8, sl, ip, lr}
│ │ -	and.w	sl, r3, sp, asr #24
│ │ -	vmlsl.u32	q11, d5, d5
│ │ -			@ <UNDEFINED> instruction: 0xffe569a1
│ │ -	vqrshrn.u64	d22, <illegal reg q4.5>, #27
│ │ -			@ <UNDEFINED> instruction: 0xffe56925
│ │ +	and.w	sl, r3, r4, lsr #25
│ │ +	vmlsl.u32	q11, d5, d28
│ │ +	vmul.f32	q11, <illegal reg q10.5>, d8[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe56980
│ │ +	vmul.f32	q11, <illegal reg q2.5>, d12[0]
│ │  	vqshrun.s64	d20, q8, #27
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	247c8c <uniffi_pbcli_checksum_method_api_base@@Base+0xdb408>
│ │  	beq.n	247784 <uniffi_pbcli_checksum_method_api_base@@Base+0xdaf00>
│ │  	b.n	247c10 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb38c>
│ │  	movs	r0, r0
│ │  	b.n	247e1a <uniffi_pbcli_checksum_method_api_base@@Base+0xdb596>
│ │ @@ -412170,15 +412170,15 @@
│ │  	b.n	248162 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb8de>
│ │  	bf	1c, 254222 <uniffi_pbcli_checksum_method_api_base@@Base+0xe799e>
│ │  	movs	r4, r0
│ │  	b.n	247d6a <uniffi_pbcli_checksum_method_api_base@@Base+0xdb4e6>
│ │  	beq.n	247a64 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb1e0>
│ │  	b.n	247ec4 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb640>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r4, r5, r6, r9, sl, sp, lr}
│ │ +	ldmia.w	sp!, {r3, r4, r7, r9, sl, sp, lr}
│ │  	vqrdmlah.s32	q11, <illegal reg q2.5>, d14[1]
│ │  			@ <UNDEFINED> instruction: 0xffe34df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	247f5c <uniffi_pbcli_checksum_method_api_base@@Base+0xdb6d8>
│ │  	beq.n	247a54 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb1d0>
│ │  	b.n	247ee0 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb65c>
│ │  	strh	r0, [r1, #0]
│ │ @@ -412298,15 +412298,15 @@
│ │  	str	r0, [r0, #0]
│ │  	b.n	24827e <uniffi_pbcli_checksum_method_api_base@@Base+0xdb9fa>
│ │  	movs	r6, r0
│ │  	b.n	247e82 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb5fe>
│ │  	beq.n	247b74 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb2f0>
│ │  	b.n	247fdc <uniffi_pbcli_checksum_method_api_base@@Base+0xdb758>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r3, r4, r6, r8, sl, sp, lr}
│ │ +	ldmia.w	sp!, {r7, r8, sl, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffe56b59
│ │  			@ <UNDEFINED> instruction: 0xffe448f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	248074 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb7f0>
│ │  	beq.n	247b6c <uniffi_pbcli_checksum_method_api_base@@Base+0xdb2e8>
│ │  	b.n	247ff8 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb774>
│ │  	str	r3, [r0, r0]
│ │ @@ -412434,17 +412434,17 @@
│ │  	b.n	2483aa <uniffi_pbcli_checksum_method_api_base@@Base+0xdbb26>
│ │  	bfcsel	1a, 24846a <uniffi_pbcli_checksum_method_api_base@@Base+0xdbbe6>, 1e, al
│ │  	movs	r7, r0
│ │  	b.n	247fb2 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb72e>
│ │  	beq.n	247c94 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb410>
│ │  	b.n	24810c <uniffi_pbcli_checksum_method_api_base@@Base+0xdb888>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r5, sl, sp, lr}
│ │ +	ldmia.w	sp!, {r4, r6, sl, sp, lr}
│ │  	vqshrn.u64	d25, q12, #27
│ │ -	vmls.i32	q11, q2, d13[0]
│ │ +	vsri.32	q11, q10, #28
│ │  	vqrshrn.u64	d25, q6, #27
│ │  			@ <UNDEFINED> instruction: 0xffe44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2481ac <uniffi_pbcli_checksum_method_api_base@@Base+0xdb928>
│ │  	beq.n	247ccc <uniffi_pbcli_checksum_method_api_base@@Base+0xdb448>
│ │  	b.n	248130 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb8ac>
│ │  	add	r0, pc, #0	@ (adr r0, 247c98 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb414>)
│ │ @@ -412706,21 +412706,21 @@
│ │  	movs	r0, #36	@ 0x24
│ │  	b.n	247a04 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb180>
│ │  	movs	r0, r0
│ │  	b.n	247fe8 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb764>
│ │  	movs	r0, #2
│ │  	b.n	247fec <uniffi_pbcli_checksum_method_api_base@@Base+0xdb768>
│ │  			@ <UNDEFINED> instruction: 0xff8deaff
│ │ -	str	r5, [r5, #52]	@ 0x34
│ │ +	str	r4, [r2, #56]	@ 0x38
│ │  			@ <UNDEFINED> instruction: 0xffe56b8f
│ │ -	vmla.f32	q11, <illegal reg q9.5>, d5[0]
│ │ +	vmla.f32	q11, <illegal reg q9.5>, d12[1]
│ │  	vmul.f32	q11, <illegal reg q10.5>, d7[1]
│ │ -	vsubl.u32	q11, d3, d29
│ │ +	vrshr.u32	q11, q2, #29
│ │  	vmull.u32	q11, d5, d15[0]
│ │ -	vaddw.u32	q11, <illegal reg q9.5>, d25
│ │ +	vsra.u64	q11, q0, #29
│ │  	vmul.f32	q11, <illegal reg q10.5>, d11[0]
│ │  			@ <UNDEFINED> instruction: 0xffe34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	248414 <uniffi_pbcli_checksum_method_api_base@@Base+0xdbb90>
│ │  	svc	99	@ 0x63
│ │  	b.n	248398 <uniffi_pbcli_checksum_method_api_base@@Base+0xdbb14>
│ │  	blt.n	247f04 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb680>
│ │ @@ -413261,21 +413261,21 @@
│ │  	b.n	24861a <uniffi_pbcli_checksum_method_api_base@@Base+0xdbd96>
│ │  			@ <UNDEFINED> instruction: 0xfff83aff
│ │  	movs	r1, r1
│ │  	b.n	2486b6 <uniffi_pbcli_checksum_method_api_base@@Base+0xdbe32>
│ │  	beq.n	2483b0 <uniffi_pbcli_checksum_method_api_base@@Base+0xdbb2c>
│ │  	b.n	248810 <uniffi_pbcli_checksum_method_api_base@@Base+0xdbf8c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r6, r7, r8, sl, fp, ip, lr}
│ │ +	ldmia.w	sp!, {r5, r9, sl, fp, ip, lr}
│ │  			@ <UNDEFINED> instruction: 0xffe53abe
│ │ -	vcvt.u16.f16	<illegal reg q10.5>, <illegal reg q0.5>, #28
│ │ +	vcvt.u16.f16	<illegal reg q10.5>, q12, #28
│ │  	vshll.u32	<illegal reg q9.5>, d6, #5
│ │ -			@ <UNDEFINED> instruction: 0xffe45d85
│ │ +			@ <UNDEFINED> instruction: 0xffe45dac
│ │  	vmull.u32	<illegal reg q9.5>, d5, d10[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe45dad
│ │ +			@ <UNDEFINED> instruction: 0xffe45dd4
│ │  			@ <UNDEFINED> instruction: 0xffe53a72
│ │  	vcvt.f16.u16	d20, d0, #28
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2488c0 <uniffi_pbcli_checksum_method_api_base@@Base+0xdc03c>
│ │  	ands	r0, r0
│ │  	b.n	2486ea <uniffi_pbcli_checksum_method_api_base@@Base+0xdbe66>
│ │  	lsls	r0, r3, #15
│ │ @@ -413337,15 +413337,15 @@
│ │  	b.n	248b66 <uniffi_pbcli_checksum_method_api_base@@Base+0xdc2e2>
│ │  	adds	r0, #0
│ │  	b.n	248b6a <uniffi_pbcli_checksum_method_api_base@@Base+0xdc2e6>
│ │  	bf	12, 252c2a <uniffi_pbcli_checksum_method_api_base@@Base+0xe63a6>
│ │  	movs	r1, r0
│ │  	b.n	248bf2 <uniffi_pbcli_checksum_method_api_base@@Base+0xdc36e>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r2, r5, r6, sl, fp, ip, lr}
│ │ +	ldmia.w	sp!, {r2, r3, r7, sl, fp, ip, lr}
│ │  			@ <UNDEFINED> instruction: 0xffe57cba
│ │  			@ <UNDEFINED> instruction: 0xffe34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	248960 <uniffi_pbcli_checksum_method_api_base@@Base+0xdc0dc>
│ │  	beq.n	248450 <uniffi_pbcli_checksum_method_api_base@@Base+0xdbbcc>
│ │  	b.n	2488e4 <uniffi_pbcli_checksum_method_api_base@@Base+0xdc060>
│ │  	ands	r0, r0
│ │ @@ -413661,20 +413661,20 @@
│ │  	str	r0, [sp, #4]
│ │  	b.n	248e32 <uniffi_pbcli_checksum_method_api_base@@Base+0xdc5ae>
│ │  	movs	r1, r1
│ │  	b.n	248a36 <uniffi_pbcli_checksum_method_api_base@@Base+0xdc1b2>
│ │  	beq.n	248730 <uniffi_pbcli_checksum_method_api_base@@Base+0xdbeac>
│ │  	b.n	248b90 <uniffi_pbcli_checksum_method_api_base@@Base+0xdc30c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r6, r7, r8, fp, ip, lr}
│ │ +	ldmia.w	sp!, {r2, r3, r5, r6, r7, r8, fp, ip, lr}
│ │  	vqrdmlsh.s32	q15, <illegal reg q2.5>, d5[1]
│ │  	vqshlu.s64	d17, d26, #35	@ 0x23
│ │ -			@ <UNDEFINED> instruction: 0xffe35a59
│ │ -			@ <UNDEFINED> instruction: 0xffe55af1
│ │ -			@ <UNDEFINED> instruction: 0xffe55ad5
│ │ +	vmlsl.u32	<illegal reg q10.5>, d19, d0
│ │ +			@ <UNDEFINED> instruction: 0xffe55b18
│ │ +			@ <UNDEFINED> instruction: 0xffe55afc
│ │  	vshr.u32	<illegal reg q15.5>, <illegal reg q10.5>, #27
│ │  			@ <UNDEFINED> instruction: 0xffe3099c
│ │  	b.n	24823e <uniffi_pbcli_checksum_method_api_base@@Base+0xdb9ba>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r4, r1
│ │  	b.n	248246 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb9c2>
│ │  	movs	r1, r0
│ │ @@ -413883,15 +413883,15 @@
│ │  	b.n	249022 <uniffi_pbcli_checksum_method_api_base@@Base+0xdc79e>
│ │  	ands	r0, r0
│ │  	b.n	249026 <uniffi_pbcli_checksum_method_api_base@@Base+0xdc7a2>
│ │  	bfcsel	e, 2480e6 <uniffi_pbcli_checksum_method_api_base@@Base+0xdb862>, 12, vs
│ │  	movs	r4, r0
│ │  	b.n	248c2e <uniffi_pbcli_checksum_method_api_base@@Base+0xdc3aa>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r5, r7, r8, r9, sl, ip, lr}
│ │ +	ldmia.w	sp!, {r4, r6, r7, r8, r9, sl, ip, lr}
│ │  	vrsubhn.i64	d26, <illegal reg q2.5>, <illegal reg q10.5>
│ │  	vqshrun.s64	d20, q8, #29
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	248e1c <uniffi_pbcli_checksum_method_api_base@@Base+0xdc598>
│ │  	ands	r0, r0
│ │  	b.n	248c46 <uniffi_pbcli_checksum_method_api_base@@Base+0xdc3c2>
│ │  	movs	r4, r2
│ │ @@ -414082,16 +414082,16 @@
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r2, r3, r6, ip}
│ │  	b.n	2485ca <uniffi_pbcli_checksum_method_api_base@@Base+0xdbd46>
│ │  	movs	r0, r0
│ │  	b.n	249148 <uniffi_pbcli_checksum_method_api_base@@Base+0xdc8c4>
│ │  			@ <UNDEFINED> instruction: 0xffc51aff
│ │  			@ <UNDEFINED> instruction: 0xffe4eaff
│ │ -	ldrsb	r5, [r3, r0]
│ │ -	vqshlu.s32	<illegal reg q10.5>, <illegal reg q0.5>, #5
│ │ +	ldrsb	r4, [r0, r1]
│ │ +	vqshlu.s32	<illegal reg q10.5>, q12, #5
│ │  			@ <UNDEFINED> instruction: 0xffe54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	248fd8 <uniffi_pbcli_checksum_method_api_base@@Base+0xdc754>
│ │  	beq.n	248b38 <uniffi_pbcli_checksum_method_api_base@@Base+0xdc2b4>
│ │  	b.n	248f5c <uniffi_pbcli_checksum_method_api_base@@Base+0xdc6d8>
│ │  	str	r2, [r0, r0]
│ │  	b.n	248e06 <uniffi_pbcli_checksum_method_api_base@@Base+0xdc582>
│ │ @@ -414290,16 +414290,16 @@
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r2, r3, r6, r7, r9, sl, lr}
│ │  	movs	r1, r5
│ │  	mov	r8, r9
│ │  	movs	r1, r5
│ │  	mov	r8, sp
│ │  	movs	r1, r5
│ │ -	strb	r5, [r1, r1]
│ │ -	vqrdmlsh.s32	q13, <illegal reg q2.5>, d10[1]
│ │ +	strb	r4, [r6, r1]
│ │ +			@ <UNDEFINED> instruction: 0xffe5af91
│ │  	vabdl.u32	q10, d5, d12
│ │  	movs	r1, r5
│ │  	ldr	r3, [pc, #960]	@ (24903c <uniffi_pbcli_checksum_method_api_base@@Base+0xdc7b8>)
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	24919c <uniffi_pbcli_checksum_method_api_base@@Base+0xdc918>
│ │  	beq.n	248c94 <uniffi_pbcli_checksum_method_api_base@@Base+0xdc410>
│ │  	b.n	249120 <uniffi_pbcli_checksum_method_api_base@@Base+0xdc89c>
│ │ @@ -414792,15 +414792,15 @@
│ │  	b.n	24980a <uniffi_pbcli_checksum_method_api_base@@Base+0xdcf86>
│ │  	bfcsel	6, 2498ca <uniffi_pbcli_checksum_method_api_base@@Base+0xdd046>, a, hi
│ │  	movs	r5, r0
│ │  	b.n	249412 <uniffi_pbcli_checksum_method_api_base@@Base+0xdcb8e>
│ │  	beq.n	24910c <uniffi_pbcli_checksum_method_api_base@@Base+0xdc888>
│ │  	b.n	24956c <uniffi_pbcli_checksum_method_api_base@@Base+0xdcce8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r5, sp, lr, pc}
│ │  	vmls.f32	q12, q10, d5[1]
│ │  	vcvt.f16.u16	d25, d18, #29
│ │  	vqshlu.s32	d24, d9, #4
│ │  	vqdmulh.s32	<illegal reg q12.5>, <illegal reg q1.5>, d6[1]
│ │  			@ <UNDEFINED> instruction: 0xffe44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	249610 <uniffi_pbcli_checksum_method_api_base@@Base+0xdcd8c>
│ │ @@ -415447,26 +415447,26 @@
│ │  	b.n	249dbe <uniffi_pbcli_checksum_method_api_base@@Base+0xdd53a>
│ │  	adds	r6, #125	@ 0x7d
│ │  	add.w	r0, r2, r6
│ │  	b.n	2499c6 <uniffi_pbcli_checksum_method_api_base@@Base+0xdd142>
│ │  	beq.n	2496c0 <uniffi_pbcli_checksum_method_api_base@@Base+0xdce3c>
│ │  	b.n	249b20 <uniffi_pbcli_checksum_method_api_base@@Base+0xdd29c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r5, r6, r7, r9, sl, lr, pc}
│ │ -	vmlsl.u32	q14, d20, d7[0]
│ │ +	ldmia.w	sp!, {r1, r5, r8, r9, sl, lr, pc}
│ │ +	vmlsl.u32	q14, d20, d14[1]
│ │  	vcvt.u32.f32	d26, d14, #28
│ │  			@ <UNDEFINED> instruction: 0xffe39922
│ │ -	vsri.64	d28, d19, #29
│ │ +	vsri.64	q14, q5, #29
│ │  	vmla.i32	<illegal reg q10.5>, q2, d7[1]
│ │  	vqrdmulh.s32	q15, q2, d12[0]
│ │ -	vsli.64	d28, d19, #34	@ 0x22
│ │ +	vsli.64	q14, q5, #34	@ 0x22
│ │  	vmla.f32	<illegal reg q10.5>, q2, d7[1]
│ │ -	vsri.32	q14, <illegal reg q13.5>, #28
│ │ +	vraddhn.i64	d28, q10, q9
│ │  	vaddl.u32	<illegal reg q10.5>, d4, d31
│ │ -	vsri.64	q14, <illegal reg q3.5>, #28
│ │ +	vsri.64	q14, q15, #28
│ │  	vaddl.u32	<illegal reg q10.5>, d20, d11
│ │  			@ <UNDEFINED> instruction: 0xffe44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	249be4 <uniffi_pbcli_checksum_method_api_base@@Base+0xdd360>
│ │  	beq.n	2497c4 <uniffi_pbcli_checksum_method_api_base@@Base+0xdcf40>
│ │  	b.n	249b68 <uniffi_pbcli_checksum_method_api_base@@Base+0xdd2e4>
│ │  	ands	r0, r0
│ │ @@ -416173,31 +416173,31 @@
│ │  	movs	r0, #76	@ 0x4c
│ │  	b.n	249810 <uniffi_pbcli_checksum_method_api_base@@Base+0xdcf8c>
│ │  	movs	r0, r0
│ │  	b.n	249df4 <uniffi_pbcli_checksum_method_api_base@@Base+0xdd570>
│ │  	movs	r0, #2
│ │  	b.n	249df8 <uniffi_pbcli_checksum_method_api_base@@Base+0xdd574>
│ │  	mrc2	10, 4, lr, cr8, cr15, {7}	@ <UNPREDICTABLE>
│ │ -	stmia	r3!, {r0, r1, r5, r7}
│ │ +	stmia	r3!, {r1, r3, r6, r7}
│ │  	vqrdmlsh.s32	q13, q2, d0[1]
│ │ -	vshr.u64	d28, d15, #29
│ │ +	vmla.i32	q14, <illegal reg q9.5>, d6[0]
│ │  	vcvt.f16.u16	q13, q6, #28
│ │ -	vsubw.u32	q14, <illegal reg q1.5>, d19
│ │ +			@ <UNDEFINED> instruction: 0xffe3c34a
│ │  	vqrdmlah.s32	q13, q10, d0[1]
│ │ -	vmla.i32	q14, <illegal reg q1.5>, d3[0]
│ │ +	vmla.i32	q14, <illegal reg q1.5>, d10[1]
│ │  	vmull.u32	q13, d4, d0
│ │ -	vaddl.u32	q14, d19, d3
│ │ +	vaddl.u32	q14, d19, d26
│ │  	vqdmulh.s32	q13, q2, d0[0]
│ │ -	vshr.u32	d28, d15, #29
│ │ +	vmla.i32	q14, <illegal reg q1.5>, d6[0]
│ │  			@ <UNDEFINED> instruction: 0xffe4abdc
│ │ -	vqrdmlah.s32	<illegal reg q13.5>, <illegal reg q1.5>, d7[1]
│ │ +	vmull.p64	<illegal reg q13.5>, d19, d14
│ │  	vmlsl.u32	q13, d4, d20
│ │ -	vqrdmlah.s32	<illegal reg q13.5>, <illegal reg q1.5>, d11[0]
│ │ +	vcvt.f32.u32	<illegal reg q13.5>, q9, #29
│ │  	vmlsl.u32	q13, d4, d8
│ │ -	vmull.p64	<illegal reg q13.5>, d3, d11
│ │ +	vcvt.f32.u32	d27, d18, #29
│ │  	vmul.f32	q13, q10, d8[0]
│ │  	vqshrun.s64	d20, q8, #29
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	24a248 <uniffi_pbcli_checksum_method_api_base@@Base+0xdd9c4>
│ │  	ands	r0, r0
│ │  	b.n	24a072 <uniffi_pbcli_checksum_method_api_base@@Base+0xdd7ee>
│ │  	movs	r4, r0
│ │ @@ -416305,20 +416305,20 @@
│ │  	b.n	24a412 <uniffi_pbcli_checksum_method_api_base@@Base+0xddb8e>
│ │  	adds	r0, #0
│ │  	b.n	24a556 <uniffi_pbcli_checksum_method_api_base@@Base+0xddcd2>
│ │  	vmov.8	d31[3], lr
│ │  	movs	r5, r0
│ │  	b.n	24a15e <uniffi_pbcli_checksum_method_api_base@@Base+0xdd8da>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r5, r6, r7, sl, fp, ip, sp, pc}
│ │ -	vsra.u64	d29, d22, #28
│ │ -			@ <UNDEFINED> instruction: 0xffe4bd23
│ │ -	vsra.u64	<illegal reg q14.5>, q9, #28
│ │ -	vcvt.u16.f16	<illegal reg q13.5>, <illegal reg q1.5>, #28
│ │ -	vsubl.u32	<illegal reg q14.5>, d4, d18
│ │ +	ldmia.w	sp!, {r1, r2, r3, r8, sl, fp, ip, sp, pc}
│ │ +	vsra.u64	<illegal reg q14.5>, <illegal reg q6.5>, #28
│ │ +	vqrdmulh.s32	<illegal reg q13.5>, q2, d10[0]
│ │ +	vrshr.u32	d29, d9, #28
│ │ +	vcvt.u16.f16	<illegal reg q13.5>, q13, #28
│ │ +	vmlal.u32	<illegal reg q14.5>, d4, d9[0]
│ │  	vqshrun.s64	d20, q8, #28
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	24a35c <uniffi_pbcli_checksum_method_api_base@@Base+0xddad8>
│ │  	ands	r0, r0
│ │  	b.n	24a186 <uniffi_pbcli_checksum_method_api_base@@Base+0xdd902>
│ │  	movs	r0, #4
│ │  	b.n	24996c <uniffi_pbcli_checksum_method_api_base@@Base+0xdd0e8>
│ │ @@ -416421,18 +416421,18 @@
│ │  	b.n	24a51e <uniffi_pbcli_checksum_method_api_base@@Base+0xddc9a>
│ │  	adds	r0, #0
│ │  	b.n	24a662 <uniffi_pbcli_checksum_method_api_base@@Base+0xdddde>
│ │  	vmov.16	d28[1], lr
│ │  	movs	r5, r0
│ │  	b.n	24a26a <uniffi_pbcli_checksum_method_api_base@@Base+0xdd9e6>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r5, r6, sl, fp, ip, sp, pc}
│ │ -	vrsra.u32	<illegal reg q13.5>, <illegal reg q14.5>, #28
│ │ -			@ <UNDEFINED> instruction: 0xffe5bbdb
│ │ -	vmlal.u32	<illegal reg q13.5>, d20, d9[1]
│ │ +	ldmia.w	sp!, {r1, r2, r4, r7, sl, fp, ip, sp, pc}
│ │ +	vsubw.u32	<illegal reg q13.5>, q10, d20
│ │ +	vmull.u32	<illegal reg q13.5>, d5, d2
│ │ +	vrsra.u32	d27, d0, #28
│ │  	vmlsl.u32	q8, d5, d28
│ │  	b.n	249a62 <uniffi_pbcli_checksum_method_api_base@@Base+0xdd1de>
│ │  	movs	r0, r0
│ │  	b.n	24a5e6 <uniffi_pbcli_checksum_method_api_base@@Base+0xddd62>
│ │  	movs	r4, r0
│ │  	lsrs	r0, r0, #8
│ │  	asrs	r0, r0, #32
│ │ @@ -416643,18 +416643,18 @@
│ │  	strb	r1, [r0, #0]
│ │  	b.n	24a84a <uniffi_pbcli_checksum_method_api_base@@Base+0xddfc6>
│ │  	movs	r7, r0
│ │  	b.n	24a44e <uniffi_pbcli_checksum_method_api_base@@Base+0xddbca>
│ │  	beq.n	24a148 <uniffi_pbcli_checksum_method_api_base@@Base+0xdd8c4>
│ │  	b.n	24a5a8 <uniffi_pbcli_checksum_method_api_base@@Base+0xddd24>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r3, r7, r9, fp, ip, sp, pc}
│ │ -	vsubw.u32	q12, q2, d21
│ │ -	vmlsl.u32	<illegal reg q13.5>, d5, d3
│ │ -	vrshr.u64	d24, d13, #28
│ │ +	ldmia.w	sp!, {r1, r4, r5, r7, r9, fp, ip, sp, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffe4834c
│ │ +	vmlsl.u32	<illegal reg q13.5>, d5, d26
│ │ +	vmlal.u32	q12, d20, d4[0]
│ │  	vaddl.u32	q14, d5, d0
│ │  	b.n	249c64 <uniffi_pbcli_checksum_method_api_base@@Base+0xdd3e0>
│ │  	stmia	r0!, {}
│ │  	b.n	249c48 <uniffi_pbcli_checksum_method_api_base@@Base+0xdd3c4>
│ │  	bf	16, 24e72e <uniffi_pbcli_checksum_method_api_base@@Base+0xe1eaa>
│ │  	ldr	r0, [pc, #0]	@ (24a134 <uniffi_pbcli_checksum_method_api_base@@Base+0xdd8b0>)
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │ @@ -417027,18 +417027,18 @@
│ │  	add	r2, pc, #404	@ (adr r2, 24a600 <uniffi_pbcli_checksum_method_api_base@@Base+0xddd7c>)
│ │  	vmlal.u32	q10, d3, d2[1]
│ │  	vraddhn.i64	d26, q10, <illegal reg q10.5>
│ │  	vraddhn.i64	d20, <illegal reg q9.5>, q9
│ │  	vmls.i32	q10, q2, d13[1]
│ │  			@ <UNDEFINED> instruction: 0xffe4eb86
│ │  	vsri.32	d20, d22, #29
│ │ -	vmla.i32	q12, q10, d2[1]
│ │ +	vaddw.u32	q12, q2, d9
│ │  	vrsra.u32	d26, d1, #27
│ │  	vsubw.u32	q10, <illegal reg q1.5>, d14
│ │ -	vmla.i32	q12, q10, d11[0]
│ │ +	vshr.u64	q12, q9, #28
│ │  			@ <UNDEFINED> instruction: 0xffe5a3c1
│ │  	vrsra.u64	d20, d30, #29
│ │  	vmlal.u32	q13, d20, d1[1]
│ │  	vrshr.u64	q10, q7, #29
│ │  	vrsra.u32	d26, d29, #28
│ │  	vrsra.u32	d20, d26, #29
│ │  	vrshr.u64	d26, d29, #28
│ │ @@ -418982,21 +418982,21 @@
│ │  	cmp	r6, #96	@ 0x60
│ │  	add.w	r0, r0, r6
│ │  	b.n	24b856 <uniffi_pbcli_checksum_method_api_base@@Base+0xdefd2>
│ │  	beq.n	24b550 <uniffi_pbcli_checksum_method_api_base@@Base+0xdeccc>
│ │  	b.n	24b9b0 <uniffi_pbcli_checksum_method_api_base@@Base+0xdf12c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r3, r6, r9, fp, ip, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffe3e7c1
│ │ +			@ <UNDEFINED> instruction: 0xffe3e7e8
│ │  	vmlsl.u32	<illegal reg q14.5>, d20, d0
│ │ -	vqshl.u64	q15, <illegal reg q12.5>, #35	@ 0x23
│ │ +	vmlal.u32	q15, d3, d16
│ │  	vqdmulh.s32	<illegal reg q12.5>, q2, d0[1]
│ │  	movs	r5, r4
│ │  	bls.n	24b56c <uniffi_pbcli_checksum_method_api_base@@Base+0xdece8>
│ │ -	vqshlu.s64	d30, d5, #35	@ 0x23
│ │ +	vqshlu.s64	d30, d28, #35	@ 0x23
│ │  			@ <UNDEFINED> instruction: 0xffe44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	24ba5c <uniffi_pbcli_checksum_method_api_base@@Base+0xdf1d8>
│ │  	svc	77	@ 0x4d
│ │  	b.n	24b9e0 <uniffi_pbcli_checksum_method_api_base@@Base+0xdf15c>
│ │  	str	r0, [r0, #0]
│ │  	b.n	24b88a <uniffi_pbcli_checksum_method_api_base@@Base+0xdf006>
│ │ @@ -419632,32 +419632,32 @@
│ │  	movs	r0, #2
│ │  	b.n	24bbc8 <uniffi_pbcli_checksum_method_api_base@@Base+0xdf344>
│ │  	vpmin.u<illegal width 64>	q7, q13, <illegal reg q15.5>
│ │  	strh	r1, [r0, #52]	@ 0x34
│ │  	b.n	24c0b2 <uniffi_pbcli_checksum_method_api_base@@Base+0xdf82e>
│ │  	vpmin.u16	q15, <illegal reg q14.5>, <illegal reg q15.5>
│ │  	bpl.n	24bb80 <uniffi_pbcli_checksum_method_api_base@@Base+0xdf2fc>
│ │ -			@ <UNDEFINED> instruction: 0xffe36af9
│ │ +			@ <UNDEFINED> instruction: 0xffe36b20
│ │  	vmlsl.u32	<illegal reg q13.5>, d5, d5[1]
│ │  	vqshlu.s64	d27, d12, #37	@ 0x25
│ │  	vqshlu.s32	<illegal reg q14.5>, q10, #5
│ │ -	vmull.u32	q11, d3, d9
│ │ +	vcvt.f16.u16	d22, d16, #29
│ │  	vsli.64	<illegal reg q14.5>, q10, #37	@ 0x25
│ │ -			@ <UNDEFINED> instruction: 0xffe36b89
│ │ +			@ <UNDEFINED> instruction: 0xffe36bb0
│ │  	vmls.f32	<illegal reg q14.5>, <illegal reg q10.5>, d8[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe36b5d
│ │ +			@ <UNDEFINED> instruction: 0xffe36b84
│ │  	vrsra.u64	d29, d28, #27
│ │ -	vqrshrn.u64	d22, <illegal reg q0.5>, #29
│ │ +	vqrshrn.u64	d22, q12, #29
│ │  	vmls.i32	<illegal reg q11.5>, <illegal reg q2.5>, d2[1]
│ │  			@ <UNDEFINED> instruction: 0xffe3d364
│ │ -			@ <UNDEFINED> instruction: 0xffe368f9
│ │ +			@ <UNDEFINED> instruction: 0xffe36920
│ │  	vsubw.u32	<illegal reg q14.5>, <illegal reg q10.5>, d16
│ │ -	vqshrn.u64	d22, <illegal reg q10.5>, #29
│ │ +	vqrshrn.u64	d22, q6, #29
│ │  			@ <UNDEFINED> instruction: 0xffe5d3ec
│ │ -			@ <UNDEFINED> instruction: 0xffe36981
│ │ +			@ <UNDEFINED> instruction: 0xffe369a8
│ │  	vcvt.f16.u16	q10, q8, #27
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	24c024 <uniffi_pbcli_checksum_method_api_base@@Base+0xdf7a0>
│ │  	ands	r0, r0
│ │  	b.n	24be4e <uniffi_pbcli_checksum_method_api_base@@Base+0xdf5ca>
│ │  	movs	r0, r7
│ │  	b.n	24b632 <uniffi_pbcli_checksum_method_api_base@@Base+0xdedae>
│ │ @@ -420315,15 +420315,15 @@
│ │  	ands	r0, r0
│ │  	b.n	24c812 <uniffi_pbcli_checksum_method_api_base@@Base+0xdff8e>
│ │  	cmp	r3, #111	@ 0x6f
│ │  	add.w	r0, r0, r4
│ │  	b.n	24c41a <uniffi_pbcli_checksum_method_api_base@@Base+0xdfb96>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r2, r4, r6, r8, sl, fp, lr, pc}
│ │ -	vmull.u32	<illegal reg q12.5>, d3, d7[0]
│ │ +	vmull.u32	<illegal reg q12.5>, d3, d14[1]
│ │  	vshr.u32	d17, d24, #28
│ │  	b.n	24bc0a <uniffi_pbcli_checksum_method_api_base@@Base+0xdf386>
│ │  	movs	r0, r0
│ │  	b.n	24c790 <uniffi_pbcli_checksum_method_api_base@@Base+0xdff0c>
│ │  	asrs	r0, r0, #32
│ │  	lsls	r0, r4, #14
│ │  	adds	r0, r0, r0
│ │ @@ -420563,15 +420563,15 @@
│ │  	lsls	r0, r4, #18
│ │  	b.n	24c340 <uniffi_pbcli_checksum_method_api_base@@Base+0xdfabc>
│ │  	movs	r1, r0
│ │  	b.n	24c922 <uniffi_pbcli_checksum_method_api_base@@Base+0xe009e>
│ │  			@ <UNDEFINED> instruction: 0xffe21aff
│ │  			@ <UNDEFINED> instruction: 0xfff3eaff
│ │  	ldmia	r3!, {r2, r5, r6}
│ │ -	vcvt.f32.u32	q15, q11, #29
│ │ +			@ <UNDEFINED> instruction: 0xffe3ee9d
│ │  	vcvt.f16.u16	d20, d0, #28
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	24c834 <uniffi_pbcli_checksum_method_api_base@@Base+0xdffb0>
│ │  	asrs	r4, r4, #32
│ │  	b.n	24be5c <uniffi_pbcli_checksum_method_api_base@@Base+0xdf5d8>
│ │  	ands	r0, r0
│ │  	b.n	24c662 <uniffi_pbcli_checksum_method_api_base@@Base+0xdfdde>
│ │ @@ -420708,15 +420708,15 @@
│ │  	ands	r0, r0
│ │  	b.n	24cb8e <uniffi_pbcli_checksum_method_api_base@@Base+0xe030a>
│ │  	cmp	r2, #144	@ 0x90
│ │  	add.w	r0, r0, r4
│ │  	b.n	24c796 <uniffi_pbcli_checksum_method_api_base@@Base+0xdff12>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r3, r4, r6, r7, r8, fp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffe38dd7
│ │ +			@ <UNDEFINED> instruction: 0xffe38dfe
│ │  	vqshrun.s64	d20, q8, #27
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	24c984 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0100>
│ │  	lsrs	r2, r0, #12
│ │  	b.n	24cb10 <uniffi_pbcli_checksum_method_api_base@@Base+0xe028c>
│ │  	str	r1, [r0, r0]
│ │  	b.n	24cbb2 <uniffi_pbcli_checksum_method_api_base@@Base+0xe032e>
│ │ @@ -420752,15 +420752,15 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	24cbf6 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0372>
│ │  	cmp	r2, #118	@ 0x76
│ │  	add.w	r0, r0, r5
│ │  	b.n	24c7fe <uniffi_pbcli_checksum_method_api_base@@Base+0xdff7a>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r4, r5, r6, r8, fp, lr, pc}
│ │ -	vshr.u64	d19, d24, #29
│ │ +	vshr.u64	<illegal reg q9.5>, <illegal reg q7.5>, #29
│ │  	vaddl.u32	<illegal reg q8.5>, d5, d0
│ │  	b.n	24cc0e <uniffi_pbcli_checksum_method_api_base@@Base+0xe038a>
│ │  	adds	r4, r1, r1
│ │  	b.n	24bfd2 <uniffi_pbcli_checksum_method_api_base@@Base+0xdf74e>
│ │  	movs	r1, r0
│ │  	b.n	24cc16 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0392>
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -421143,25 +421143,25 @@
│ │  	b.n	24c354 <uniffi_pbcli_checksum_method_api_base@@Base+0xdfad0>
│ │  	movs	r0, r0
│ │  	b.n	24c938 <uniffi_pbcli_checksum_method_api_base@@Base+0xe00b4>
│ │  	movs	r0, #2
│ │  	b.n	24c93c <uniffi_pbcli_checksum_method_api_base@@Base+0xe00b8>
│ │  	vpmin.u16	q15, q12, <illegal reg q15.5>
│ │  	ldmia	r0!, {r3, r6}
│ │ -	vmull.u32	<illegal reg q8.5>, d19, d13[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe31af4
│ │  	vqshl.u64	d28, d20, #37	@ 0x25
│ │ -	vshll.u32	<illegal reg q8.5>, d25, #3
│ │ +	vmull.u32	<illegal reg q8.5>, d3, d0[1]
│ │  	vmlal.u32	q14, d21, d8
│ │ -			@ <UNDEFINED> instruction: 0xffe31b0d
│ │ +			@ <UNDEFINED> instruction: 0xffe31b34
│ │  	vqshlu.s32	q14, q10, #5
│ │ -			@ <UNDEFINED> instruction: 0xffe318f9
│ │ +			@ <UNDEFINED> instruction: 0xffe31920
│ │  	vsli.64	q14, q8, #37	@ 0x25
│ │ -	vqrshrun.s64	d17, <illegal reg q10.5>, #29
│ │ +			@ <UNDEFINED> instruction: 0xffe3189c
│ │  	vqshl.u64	q14, q14, #37	@ 0x25
│ │ -	vmlsl.u32	<illegal reg q8.5>, d19, d1
│ │ +	vmlsl.u32	<illegal reg q8.5>, d19, d24
│ │  	vshr.u32	q8, q0, #27
│ │  	movt	lr, #135	@ 0x87
│ │  	b.n	24cd5a <uniffi_pbcli_checksum_method_api_base@@Base+0xe04d6>
│ │  	lsrs	r7, r1, #10
│ │  	orr.w	r0, r0, #8454144	@ 0x810000
│ │  	b.n	24cfa2 <uniffi_pbcli_checksum_method_api_base@@Base+0xe071e>
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -421698,15 +421698,15 @@
│ │  	b.n	24d44e <uniffi_pbcli_checksum_method_api_base@@Base+0xe0bca>
│ │  	cmp	r0, #96	@ 0x60
│ │  	add.w	r0, r0, r7
│ │  	b.n	24d056 <uniffi_pbcli_checksum_method_api_base@@Base+0xe07d2>
│ │  	beq.n	24cd38 <uniffi_pbcli_checksum_method_api_base@@Base+0xe04b4>
│ │  	b.n	24d1b0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe092c>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r7, fp, sp}
│ │ +	ldmia.w	sp!, {r3, r5, r7, fp, sp}
│ │  	vrshr.u64	d19, d24, #27
│ │  	vcvt.f16.u16	q10, q8, #28
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	24d248 <uniffi_pbcli_checksum_method_api_base@@Base+0xe09c4>
│ │  	beq.n	24cd40 <uniffi_pbcli_checksum_method_api_base@@Base+0xe04bc>
│ │  	b.n	24d1cc <uniffi_pbcli_checksum_method_api_base@@Base+0xe0948>
│ │  	ands	r0, r0
│ │ @@ -421832,16 +421832,16 @@
│ │  	b.n	24d2d0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0a4c>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r1}
│ │  	b.n	24d582 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0cfe>
│ │  	beq.n	24ce64 <uniffi_pbcli_checksum_method_api_base@@Base+0xe05e0>
│ │  	b.n	24d2dc <uniffi_pbcli_checksum_method_api_base@@Base+0xe0a58>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r6, r8, r9, sl, sp}
│ │ -	vsra.u64	d26, d27, #27
│ │ +	ldmia.w	sp!, {r2, r7, r8, r9, sl, sp}
│ │ +	vmla.f32	q13, <illegal reg q10.5>, d2[1]
│ │  	vcvt.f16.u16	q10, q8, #28
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	24d374 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0af0>
│ │  	beq.n	24ce6c <uniffi_pbcli_checksum_method_api_base@@Base+0xe05e8>
│ │  	b.n	24d2f8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0a74>
│ │  	ands	r0, r0
│ │  	b.n	24d1a2 <uniffi_pbcli_checksum_method_api_base@@Base+0xe091e>
│ │ @@ -421928,15 +421928,15 @@
│ │  	and.w	r0, r0, r2, lsl #24
│ │  	b.n	24d656 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0dd2>
│ │  	movs	r6, r0
│ │  	b.n	24d25a <uniffi_pbcli_checksum_method_api_base@@Base+0xe09d6>
│ │  	beq.n	24cf3c <uniffi_pbcli_checksum_method_api_base@@Base+0xe06b8>
│ │  	b.n	24d3b4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0b30>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r7, r9, sl, sp}
│ │ +	ldmia.w	sp!, {r2, r3, r5, r7, r9, sl, sp}
│ │  	vrsra.u32	q8, q6, #27
│ │  	vcvt.f16.u16	q10, q8, #28
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	24d44c <uniffi_pbcli_checksum_method_api_base@@Base+0xe0bc8>
│ │  	beq.n	24cf44 <uniffi_pbcli_checksum_method_api_base@@Base+0xe06c0>
│ │  	b.n	24d3d0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0b4c>
│ │  	ands	r0, r0
│ │ @@ -422054,15 +422054,15 @@
│ │  	b.n	24d4c4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0c40>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r1}
│ │  	b.n	24d776 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0ef2>
│ │  	beq.n	24d058 <uniffi_pbcli_checksum_method_api_base@@Base+0xe07d4>
│ │  	b.n	24d4d0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0c4c>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r3, r5, r6, r8, sl, sp}
│ │ +	ldmia.w	sp!, {r4, r7, r8, sl, sp}
│ │  	vmlsl.u32	<illegal reg q8.5>, d21, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffe44df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	24d568 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0ce4>
│ │  	beq.n	24d080 <uniffi_pbcli_checksum_method_api_base@@Base+0xe07fc>
│ │  	b.n	24d4ec <uniffi_pbcli_checksum_method_api_base@@Base+0xe0c68>
│ │  	strh	r1, [r0, #0]
│ │ @@ -422178,16 +422178,16 @@
│ │  	add.w	r0, r3, r0
│ │  	b.n	24d7ee <uniffi_pbcli_checksum_method_api_base@@Base+0xe0f6a>
│ │  			@ <UNDEFINED> instruction: 0xffd61aff
│ │  			@ <UNDEFINED> instruction: 0xffc8eaff
│ │  	str	r2, [r0, r0]
│ │  	b.n	24d89a <uniffi_pbcli_checksum_method_api_base@@Base+0xe1016>
│ │  			@ <UNDEFINED> instruction: 0xffd3eaff
│ │ -	movs	r4, #225	@ 0xe1
│ │ -	vmull.u32	<illegal reg q9.5>, d21, d27
│ │ +	movs	r5, #8
│ │ +			@ <UNDEFINED> instruction: 0xffe53cd2
│ │  			@ <UNDEFINED> instruction: 0xffe54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	24d688 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0e04>
│ │  	beq.n	24d198 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0914>
│ │  	b.n	24d60c <uniffi_pbcli_checksum_method_api_base@@Base+0xe0d88>
│ │  	strh	r0, [r0, #0]
│ │  	b.n	24d4b6 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0c32>
│ │ @@ -422689,24 +422689,24 @@
│ │  	b.n	24d6d8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0e54>
│ │  	movs	r6, #113	@ 0x71
│ │  	add.w	r1, r2, r3, lsl #8
│ │  	b.n	24dbc2 <uniffi_pbcli_checksum_method_api_base@@Base+0xe133e>
│ │  	str	r0, [r0, #0]
│ │  	b.n	24dd06 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1482>
│ │  			@ <UNDEFINED> instruction: 0xffc4eaff
│ │ -	movs	r2, #73	@ 0x49
│ │ +	movs	r2, #112	@ 0x70
│ │  			@ <UNDEFINED> instruction: 0xffe52db7
│ │ -	vshr.u64	d18, d13, #29
│ │ +	vmla.i32	q9, <illegal reg q9.5>, d4[0]
│ │  	vmull.u32	q9, d5, d11
│ │ -	vaddl.u32	q9, d3, d5
│ │ +	vaddl.u32	q9, d3, d28
│ │  			@ <UNDEFINED> instruction: 0xffe52b73
│ │ -	vaddl.u32	q9, d3, d17
│ │ +	vmla.i32	q9, <illegal reg q1.5>, d8[0]
│ │  			@ <UNDEFINED> instruction: 0xffe52b8f
│ │ -	vsli.32	q12, <illegal reg q15.5>, #3
│ │ -			@ <UNDEFINED> instruction: 0xffe41fb9
│ │ +	vabal.u32	q12, d19, d22
│ │ +	vqrdmlsh.s32	<illegal reg q8.5>, q10, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffe52b27
│ │  			@ <UNDEFINED> instruction: 0xffe34df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	24db18 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1294>
│ │  	beq.n	24d610 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0d8c>
│ │  	b.n	24da9c <uniffi_pbcli_checksum_method_api_base@@Base+0xe1218>
│ │  	strh	r1, [r0, #0]
│ │ @@ -422873,16 +422873,16 @@
│ │  	b.n	24de9e <uniffi_pbcli_checksum_method_api_base@@Base+0xe161a>
│ │  	movs	r5, #204	@ 0xcc
│ │  	add.w	r0, r0, r6
│ │  	b.n	24daa6 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1222>
│ │  	beq.n	24d798 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0f14>
│ │  	b.n	24dc00 <uniffi_pbcli_checksum_method_api_base@@Base+0xe137c>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r3, r4, r6, r7, r9, sl, fp, ip}
│ │ -	vcvt.f32.u32	d17, d17, #27
│ │ +	ldmia.w	sp!, {r8, r9, sl, fp, ip}
│ │ +	vcvt.f32.u32	<illegal reg q8.5>, q4, #27
│ │  			@ <UNDEFINED> instruction: 0xffe5f926
│ │  	vcvt.f16.u16	q10, q8, #30
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	24dc9c <uniffi_pbcli_checksum_method_api_base@@Base+0xe1418>
│ │  	beq.n	24d794 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0f10>
│ │  	b.n	24dc20 <uniffi_pbcli_checksum_method_api_base@@Base+0xe139c>
│ │  	ands	r0, r0
│ │ @@ -423018,16 +423018,16 @@
│ │  	b.n	24dfe6 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1762>
│ │  	movs	r5, #122	@ 0x7a
│ │  	add.w	r0, r0, r0
│ │  	b.n	24dfee <uniffi_pbcli_checksum_method_api_base@@Base+0xe176a>
│ │  	beq.n	24d8d0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe104c>
│ │  	b.n	24dd48 <uniffi_pbcli_checksum_method_api_base@@Base+0xe14c4>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r5, r6, r7, sl, fp, ip}
│ │ -			@ <UNDEFINED> instruction: 0xffe5d89c
│ │ +	ldmia.w	sp!, {r2, r3, r8, sl, fp, ip}
│ │ +	vmul.i32	<illegal reg q14.5>, <illegal reg q10.5>, d3[0]
│ │  			@ <UNDEFINED> instruction: 0xffe44bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	24dde0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe155c>
│ │  	beq.n	24d8e8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1064>
│ │  	b.n	24dd64 <uniffi_pbcli_checksum_method_api_base@@Base+0xe14e0>
│ │  	str	r2, [r0, #0]
│ │  	b.n	24e00e <uniffi_pbcli_checksum_method_api_base@@Base+0xe178a>
│ │ @@ -423310,25 +423310,25 @@
│ │  	movs	r0, #36	@ 0x24
│ │  	b.n	24d678 <uniffi_pbcli_checksum_method_api_base@@Base+0xe0df4>
│ │  	movs	r0, r0
│ │  	b.n	24dc5c <uniffi_pbcli_checksum_method_api_base@@Base+0xe13d8>
│ │  	movs	r0, #2
│ │  	b.n	24dc60 <uniffi_pbcli_checksum_method_api_base@@Base+0xe13dc>
│ │  			@ <UNDEFINED> instruction: 0xffd6eaff
│ │ -	subs	r1, r2, r2
│ │ +	subs	r0, r7, r2
│ │  	vqrdmulh.s32	q8, <illegal reg q10.5>, d8[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe31ad1
│ │ +			@ <UNDEFINED> instruction: 0xffe31af8
│ │  	vmull.p64	q8, d5, d24
│ │ -			@ <UNDEFINED> instruction: 0xffe31a75
│ │ +			@ <UNDEFINED> instruction: 0xffe31a9c
│ │  	vqrdmulh.s32	q8, <illegal reg q10.5>, d12[0]
│ │ -	vshll.u32	<illegal reg q8.5>, d17, #3
│ │ +			@ <UNDEFINED> instruction: 0xffe31a58
│ │  			@ <UNDEFINED> instruction: 0xffe50d88
│ │ -	vmull.u32	<illegal reg q8.5>, d3, d13[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe31a74
│ │  			@ <UNDEFINED> instruction: 0xffe50da4
│ │ -	vmull.u32	<illegal reg q8.5>, d19, d13[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe31b14
│ │  	vqrdmlah.s32	q8, <illegal reg q2.5>, d4[0]
│ │  	vcvt.f16.u16	q10, q8, #29
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	24e098 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1814>
│ │  	beq.n	24db90 <uniffi_pbcli_checksum_method_api_base@@Base+0xe130c>
│ │  	b.n	24e01c <uniffi_pbcli_checksum_method_api_base@@Base+0xe1798>
│ │  	ands	r0, r0
│ │ @@ -423414,15 +423414,15 @@
│ │  	b.n	24e36e <uniffi_pbcli_checksum_method_api_base@@Base+0xe1aea>
│ │  	movs	r4, #152	@ 0x98
│ │  	add.w	r0, r0, r0
│ │  	b.n	24e376 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1af2>
│ │  	beq.n	24dc58 <uniffi_pbcli_checksum_method_api_base@@Base+0xe13d4>
│ │  	b.n	24e0d0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe184c>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r6, r8, fp, ip}
│ │ +	ldmia.w	sp!, {r2, r7, r8, fp, ip}
│ │  	vrsra.u32	d21, d14, #27
│ │  	vcvt.f16.u16	q10, q8, #29
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	24e168 <uniffi_pbcli_checksum_method_api_base@@Base+0xe18e4>
│ │  	beq.n	24dc60 <uniffi_pbcli_checksum_method_api_base@@Base+0xe13dc>
│ │  	b.n	24e0ec <uniffi_pbcli_checksum_method_api_base@@Base+0xe1868>
│ │  	str	r0, [r0, r0]
│ │ @@ -423526,15 +423526,15 @@
│ │  	b.n	24e466 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1be2>
│ │  	movs	r4, #90	@ 0x5a
│ │  	add.w	r0, r0, r4
│ │  	b.n	24e06e <uniffi_pbcli_checksum_method_api_base@@Base+0xe17ea>
│ │  	beq.n	24dd50 <uniffi_pbcli_checksum_method_api_base@@Base+0xe14cc>
│ │  	b.n	24e1c8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1944>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r5, r6, fp, ip}
│ │ +	ldmia.w	sp!, {r2, r3, r7, fp, ip}
│ │  	vrsra.u64	q9, <illegal reg q11.5>, #27
│ │  			@ <UNDEFINED> instruction: 0xffe34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	24e260 <uniffi_pbcli_checksum_method_api_base@@Base+0xe19dc>
│ │  	beq.n	24dd50 <uniffi_pbcli_checksum_method_api_base@@Base+0xe14cc>
│ │  	b.n	24e1e4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1960>
│ │  	str	r1, [r0, r0]
│ │ @@ -423685,16 +423685,16 @@
│ │  	and.w	r0, r0, r2, lsl #16
│ │  	b.n	24e5ce <uniffi_pbcli_checksum_method_api_base@@Base+0xe1d4a>
│ │  	movs	r4, r0
│ │  	b.n	24e1d2 <uniffi_pbcli_checksum_method_api_base@@Base+0xe194e>
│ │  	beq.n	24decc <uniffi_pbcli_checksum_method_api_base@@Base+0xe1648>
│ │  	b.n	24e32c <uniffi_pbcli_checksum_method_api_base@@Base+0xe1aa8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r3, r8, r9, sl, ip}
│ │ -	vqdmulh.s32	<illegal reg q11.5>, <illegal reg q10.5>, d3[1]
│ │ +	ldmia.w	sp!, {r2, r4, r5, r8, r9, sl, ip}
│ │ +			@ <UNDEFINED> instruction: 0xffe57d0a
│ │  	vcvt.f16.u16	q10, q8, #28
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	24e3c4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1b40>
│ │  	beq.n	24debc <uniffi_pbcli_checksum_method_api_base@@Base+0xe1638>
│ │  	b.n	24e348 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1ac4>
│ │  	str	r1, [r0, r0]
│ │  	b.n	24e1f2 <uniffi_pbcli_checksum_method_api_base@@Base+0xe196e>
│ │ @@ -423767,15 +423767,15 @@
│ │  	b.n	24e682 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1dfe>
│ │  	movs	r3, #211	@ 0xd3
│ │  	add.w	r0, r0, r0
│ │  	b.n	24e68a <uniffi_pbcli_checksum_method_api_base@@Base+0xe1e06>
│ │  	beq.n	24df6c <uniffi_pbcli_checksum_method_api_base@@Base+0xe16e8>
│ │  	b.n	24e3e4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1b60>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r3, r6, r9, sl, ip}
│ │ +	ldmia.w	sp!, {r4, r5, r6, r9, sl, ip}
│ │  			@ <UNDEFINED> instruction: 0xffe5f342
│ │  	vcvt.f16.u16	q10, q8, #29
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	24e47c <uniffi_pbcli_checksum_method_api_base@@Base+0xe1bf8>
│ │  	beq.n	24df74 <uniffi_pbcli_checksum_method_api_base@@Base+0xe16f0>
│ │  	b.n	24e400 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1b7c>
│ │  	ands	r0, r0
│ │ @@ -423853,16 +423853,16 @@
│ │  	b.n	24e742 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1ebe>
│ │  	movs	r3, #163	@ 0xa3
│ │  	add.w	r0, r0, r0
│ │  	b.n	24e74a <uniffi_pbcli_checksum_method_api_base@@Base+0xe1ec6>
│ │  	beq.n	24e02c <uniffi_pbcli_checksum_method_api_base@@Base+0xe17a8>
│ │  	b.n	24e4a4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1c20>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r3, r7, r8, sl, ip}
│ │ -			@ <UNDEFINED> instruction: 0xffe5e90a
│ │ +	ldmia.w	sp!, {r4, r5, r7, r8, sl, ip}
│ │ +	vqshrn.u64	d30, <illegal reg q8.5>, #27
│ │  	vcvt.f16.u16	q10, q8, #28
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	24e53c <uniffi_pbcli_checksum_method_api_base@@Base+0xe1cb8>
│ │  	beq.n	24e034 <uniffi_pbcli_checksum_method_api_base@@Base+0xe17b0>
│ │  	b.n	24e4c0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1c3c>
│ │  	str	r1, [r0, r0]
│ │  	b.n	24e36a <uniffi_pbcli_checksum_method_api_base@@Base+0xe1ae6>
│ │ @@ -423935,16 +423935,16 @@
│ │  	b.n	24e7fa <uniffi_pbcli_checksum_method_api_base@@Base+0xe1f76>
│ │  	movs	r3, #117	@ 0x75
│ │  	add.w	r0, r0, r0
│ │  	b.n	24e802 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1f7e>
│ │  	beq.n	24e0e4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1860>
│ │  	b.n	24e55c <uniffi_pbcli_checksum_method_api_base@@Base+0xe1cd8>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r4, r6, r7, sl, ip}
│ │ -			@ <UNDEFINED> instruction: 0xffe52cbc
│ │ +	ldmia.w	sp!, {r3, r4, r5, r6, r7, sl, ip}
│ │ +	vqdmulh.s32	q9, <illegal reg q10.5>, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffe54df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	24e5f4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1d70>
│ │  	beq.n	24e0fc <uniffi_pbcli_checksum_method_api_base@@Base+0xe1878>
│ │  	b.n	24e578 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1cf4>
│ │  	str	r1, [r0, #0]
│ │  	b.n	24e422 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1b9e>
│ │ @@ -424084,15 +424084,15 @@
│ │  	movs	r0, r0
│ │  	b.n	24e8b4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe2030>
│ │  			@ <UNDEFINED> instruction: 0xffc81aff
│ │  			@ <UNDEFINED> instruction: 0xffbaeaff
│ │  	strb	r3, [r1, #9]
│ │  	b.n	24e81e <uniffi_pbcli_checksum_method_api_base@@Base+0xe1f9a>
│ │  			@ <UNDEFINED> instruction: 0xffb8eaff
│ │ -	asrs	r5, r2, #17
│ │ +	asrs	r4, r7, #17
│ │  	vrshr.u64	q13, q11, #27
│ │  			@ <UNDEFINED> instruction: 0xffe24df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	24e74c <uniffi_pbcli_checksum_method_api_base@@Base+0xe1ec8>
│ │  	beq.n	24e244 <uniffi_pbcli_checksum_method_api_base@@Base+0xe19c0>
│ │  	b.n	24e6d0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1e4c>
│ │  	ands	r0, r0
│ │ @@ -424219,15 +424219,15 @@
│ │  	b.n	24ea7e <uniffi_pbcli_checksum_method_api_base@@Base+0xe21fa>
│ │  	movs	r2, #212	@ 0xd4
│ │  	add.w	r0, r0, r5
│ │  	b.n	24e686 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1e02>
│ │  	beq.n	24e378 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1af4>
│ │  	b.n	24e7e0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1f5c>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r2, r3, r6, r9, ip}
│ │ +	ldmia.w	sp!, {r2, r4, r5, r6, r9, ip}
│ │  	vsubw.u32	q11, <illegal reg q10.5>, d26
│ │  			@ <UNDEFINED> instruction: 0xffe34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	24e878 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1ff4>
│ │  	beq.n	24e388 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1b04>
│ │  	b.n	24e7fc <uniffi_pbcli_checksum_method_api_base@@Base+0xe1f78>
│ │  	ands	r0, r0
│ │ @@ -424603,26 +424603,26 @@
│ │  	b.n	24e1cc <uniffi_pbcli_checksum_method_api_base@@Base+0xe1948>
│ │  	asrs	r1, r0, #32
│ │  	b.n	24e7b4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1f30>
│ │  	subs	r2, #12
│ │  	add.w	r0, r3, r0, lsl #24
│ │  	b.n	24edde <uniffi_pbcli_checksum_method_api_base@@Base+0xe255a>
│ │  	vpmin.u<illegal width 64>	q15, <illegal reg q9.5>, <illegal reg q15.5>
│ │ -	asrs	r5, r3, #4
│ │ -	vqdmulh.s32	<illegal reg q15.5>, <illegal reg q2.5>, d13[0]
│ │ -	vmla.i32	<illegal reg q8.5>, q2, d5[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe5fb75
│ │ -	vsra.u32	<illegal reg q8.5>, <illegal reg q4.5>, #28
│ │ +	asrs	r4, r0, #5
│ │ +	vcvt.f16.u16	<illegal reg q15.5>, q10, #27
│ │ +	vmla.i32	<illegal reg q8.5>, q2, d12[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe5fb9c
│ │ +	vaddw.u32	<illegal reg q8.5>, q10, d0
│ │  			@ <UNDEFINED> instruction: 0xffe548fa
│ │ -	vcvt.u32.f32	d16, d9, #28
│ │ +	vqrdmlsh.s32	q8, q2, d0[0]
│ │  	vqshlu.s64	d20, d26, #37	@ 0x25
│ │ -			@ <UNDEFINED> instruction: 0xffe40ed9
│ │ -			@ <UNDEFINED> instruction: 0xffe50fa9
│ │ -	vqrdmlsh.s32	q8, <illegal reg q2.5>, d5[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe5fa95
│ │ +			@ <UNDEFINED> instruction: 0xffe40f00
│ │ +			@ <UNDEFINED> instruction: 0xffe50fd0
│ │ +			@ <UNDEFINED> instruction: 0xffe50f8c
│ │ +			@ <UNDEFINED> instruction: 0xffe5fabc
│ │  	vqshrun.s64	d20, q8, #28
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	24ebf4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe2370>
│ │  	beq.n	24e6ec <uniffi_pbcli_checksum_method_api_base@@Base+0xe1e68>
│ │  	b.n	24eb78 <uniffi_pbcli_checksum_method_api_base@@Base+0xe22f4>
│ │  	ands	r0, r0
│ │  	b.n	24ea22 <uniffi_pbcli_checksum_method_api_base@@Base+0xe219e>
│ │ @@ -424724,17 +424724,17 @@
│ │  	and.w	r0, r0, r2, lsl #20
│ │  	b.n	24eef6 <uniffi_pbcli_checksum_method_api_base@@Base+0xe2672>
│ │  	movs	r5, r0
│ │  	b.n	24eafa <uniffi_pbcli_checksum_method_api_base@@Base+0xe2276>
│ │  	beq.n	24e7cc <uniffi_pbcli_checksum_method_api_base@@Base+0xe1f48>
│ │  	b.n	24ec54 <uniffi_pbcli_checksum_method_api_base@@Base+0xe23d0>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r9, sl, fp}
│ │ +	ldmia.w	sp!, {r2, r3, r5, r9, sl, fp}
│ │  	vqrdmlah.s32	q12, <illegal reg q10.5>, d1[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe30dd1
│ │ +			@ <UNDEFINED> instruction: 0xffe30df8
│ │  			@ <UNDEFINED> instruction: 0xffe54bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	24ecf0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe246c>
│ │  	udf	#50	@ 0x32
│ │  	b.n	24ec74 <uniffi_pbcli_checksum_method_api_base@@Base+0xe23f0>
│ │  	ands	r0, r0
│ │  	b.n	24eb1e <uniffi_pbcli_checksum_method_api_base@@Base+0xe229a>
│ │ @@ -425307,36 +425307,36 @@
│ │  	movs	r4, r0
│ │  	b.n	24effe <uniffi_pbcli_checksum_method_api_base@@Base+0xe277a>
│ │  	asrs	r0, r2, #1
│ │  	b.n	24f402 <uniffi_pbcli_checksum_method_api_base@@Base+0xe2b7e>
│ │  	movs	r0, #222	@ 0xde
│ │  	b.n	24f406 <uniffi_pbcli_checksum_method_api_base@@Base+0xe2b82>
│ │  			@ <UNDEFINED> instruction: 0xffeeeaff
│ │ -	lsrs	r5, r0, #20
│ │ +	lsrs	r4, r5, #20
│ │  	vcvt.f32.u32	d27, d1, #27
│ │ -	vmull.u32	q8, d19, d9
│ │ +			@ <UNDEFINED> instruction: 0xffe30cb0
│ │  			@ <UNDEFINED> instruction: 0xffe5bd95
│ │ -	vmull.u32	q8, d3, d29
│ │ +	vcvt.f16.u16	q8, q2, #29
│ │  	vcvt.u16.f16	d27, d25, #27
│ │ -			@ <UNDEFINED> instruction: 0xffe30905
│ │ +			@ <UNDEFINED> instruction: 0xffe3092c
│ │  	vshll.u32	<illegal reg q13.5>, d1, #5
│ │ -	vmul.f32	q8, <illegal reg q9.5>, d5[1]
│ │ +	vmlsl.u32	q8, d3, d12
│ │  			@ <UNDEFINED> instruction: 0xffe5baf1
│ │ -			@ <UNDEFINED> instruction: 0xffe30b89
│ │ -	vmull.u32	q8, d21, d5[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe30bb0
│ │ +	vmull.u32	q8, d21, d12[1]
│ │  			@ <UNDEFINED> instruction: 0xffe5bbd1
│ │ -			@ <UNDEFINED> instruction: 0xffe30afd
│ │ +			@ <UNDEFINED> instruction: 0xffe30b24
│ │  	vmull.u32	<illegal reg q13.5>, d5, d9
│ │ -			@ <UNDEFINED> instruction: 0xffe30995
│ │ +			@ <UNDEFINED> instruction: 0xffe309bc
│ │  	vmlsl.u32	<illegal reg q13.5>, d21, d17
│ │ -			@ <UNDEFINED> instruction: 0xffe30a7d
│ │ +	vmlsl.u32	q8, d19, d20
│ │  			@ <UNDEFINED> instruction: 0xffe5bb89
│ │ -			@ <UNDEFINED> instruction: 0xffe30921
│ │ +	vmul.f32	q8, <illegal reg q1.5>, d8[0]
│ │  	vmlsl.u32	<illegal reg q13.5>, d5, d29
│ │ -	vmul.i32	q8, <illegal reg q9.5>, d1[0]
│ │ +	vmul.i32	q8, <illegal reg q9.5>, d8[1]
│ │  	vmul.f32	<illegal reg q13.5>, <illegal reg q10.5>, d13[0]
│ │  	vcvt.f16.u16	q10, q8, #29
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	24f248 <uniffi_pbcli_checksum_method_api_base@@Base+0xe29c4>
│ │  	beq.n	24ed50 <uniffi_pbcli_checksum_method_api_base@@Base+0xe24cc>
│ │  	b.n	24f1cc <uniffi_pbcli_checksum_method_api_base@@Base+0xe2948>
│ │  	ands	r0, r0
│ │ @@ -425506,17 +425506,17 @@
│ │  	b.n	24f39a <uniffi_pbcli_checksum_method_api_base@@Base+0xe2b16>
│ │  	movs	r0, r1
│ │  	b.n	24e9b8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe2134>
│ │  			@ <UNDEFINED> instruction: 0xffb7eaff
│ │  	str	r0, [r0, #0]
│ │  	b.n	24f5e6 <uniffi_pbcli_checksum_method_api_base@@Base+0xe2d62>
│ │  			@ <UNDEFINED> instruction: 0xffeaeaff
│ │ -	lsls	r1, r4, #29
│ │ +	lsls	r0, r1, #30
│ │  	vsubw.u32	<illegal reg q8.5>, <illegal reg q2.5>, d11
│ │ -	vqshl.u32	d16, d25, #3
│ │ +			@ <UNDEFINED> instruction: 0xffe30760
│ │  	vmlal.u32	<illegal reg q8.5>, d21, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffe34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	24f3dc <uniffi_pbcli_checksum_method_api_base@@Base+0xe2b58>
│ │  	beq.n	24ef3c <uniffi_pbcli_checksum_method_api_base@@Base+0xe26b8>
│ │  	b.n	24f360 <uniffi_pbcli_checksum_method_api_base@@Base+0xe2adc>
│ │  	ands	r0, r0
│ │ @@ -426174,30 +426174,30 @@
│ │  	b.n	24f568 <uniffi_pbcli_checksum_method_api_base@@Base+0xe2ce4>
│ │  	movs	r0, #2
│ │  	b.n	24f56c <uniffi_pbcli_checksum_method_api_base@@Base+0xe2ce8>
│ │  	mcr2	10, 6, lr, cr15, cr15, {7}	@ <UNPREDICTABLE>
│ │  	strb	r1, [r0, #0]
│ │  	b.n	24fb96 <uniffi_pbcli_checksum_method_api_base@@Base+0xe3312>
│ │  			@ <UNDEFINED> instruction: 0xffe3eaff
│ │ -	lsls	r1, r4, #23
│ │ -	vcvt.f16.u16	d20, d7, #27
│ │ -	vmls.f32	q8, <illegal reg q2.5>, d1[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe54b77
│ │ -	vmlal.u32	q8, d5, d1[0]
│ │ -	vqrshrun.s64	d20, <illegal reg q11.5>, #27
│ │ -	vsli.32	q8, <illegal reg q6.5>, #5
│ │ -			@ <UNDEFINED> instruction: 0xffe54b93
│ │ -	vaddw.u32	q8, <illegal reg q10.5>, d21
│ │ -	vqshl.u64	q10, <illegal reg q5.5>, #37	@ 0x25
│ │ -	vmla.f32	q8, <illegal reg q2.5>, d1[0]
│ │ -	vqshl.u32	q10, <illegal reg q11.5>, #5
│ │ -	vaddw.u32	q8, <illegal reg q2.5>, d21
│ │ -	vqshl.u32	q10, <illegal reg q5.5>, #5
│ │ -	vsra.u32	q8, <illegal reg q6.5>, #27
│ │ -	vqshl.u64	d20, d3, #37	@ 0x25
│ │ +	lsls	r0, r1, #24
│ │ +	vcvt.f16.u16	d20, d30, #27
│ │ +	vmls.f32	q8, <illegal reg q2.5>, d8[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe54b9e
│ │ +	vmlal.u32	q8, d5, d8[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe5489e
│ │ +	vabal.u32	q8, d21, d4
│ │ +			@ <UNDEFINED> instruction: 0xffe54bba
│ │ +	vmla.f32	q8, <illegal reg q10.5>, d12[0]
│ │ +	vmlal.u32	q10, d5, d2
│ │ +	vmla.f32	q8, <illegal reg q2.5>, d8[1]
│ │ +	vqshl.u64	d20, d14, #37	@ 0x25
│ │ +	vmla.f32	q8, <illegal reg q2.5>, d12[0]
│ │ +	vabdl.u32	q10, d21, d2
│ │ +	vaddw.u32	q8, <illegal reg q10.5>, d4
│ │ +	vqshl.u64	d20, d26, #37	@ 0x25
│ │  	vcvt.f16.u16	q10, q8, #27
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	24f9bc <uniffi_pbcli_checksum_method_api_base@@Base+0xe3138>
│ │  	beq.n	24f4b4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe2c30>
│ │  	b.n	24f940 <uniffi_pbcli_checksum_method_api_base@@Base+0xe30bc>
│ │  	str	r0, [r0, r0]
│ │  	b.n	24f7ea <uniffi_pbcli_checksum_method_api_base@@Base+0xe2f66>
│ │ @@ -426274,16 +426274,16 @@
│ │  	and.w	r0, r0, r2, lsl #16
│ │  	b.n	24fc8a <uniffi_pbcli_checksum_method_api_base@@Base+0xe3406>
│ │  	movs	r4, r0
│ │  	b.n	24f88e <uniffi_pbcli_checksum_method_api_base@@Base+0xe300a>
│ │  	beq.n	24f570 <uniffi_pbcli_checksum_method_api_base@@Base+0xe2cec>
│ │  	b.n	24f9e8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe3164>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r3, r6}
│ │ -	vmull.u32	<illegal reg q13.5>, d5, d16
│ │ +	ldmia.w	sp!, {r2, r4, r5, r6}
│ │ +	vqdmulh.s32	<illegal reg q13.5>, <illegal reg q2.5>, d7[0]
│ │  			@ <UNDEFINED> instruction: 0xffe44df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	24fa80 <uniffi_pbcli_checksum_method_api_base@@Base+0xe31fc>
│ │  	movs	r2, #244	@ 0xf4
│ │  	b.n	24f08a <uniffi_pbcli_checksum_method_api_base@@Base+0xe2806>
│ │  	strb	r1, [r0, #0]
│ │  	b.n	24f8ae <uniffi_pbcli_checksum_method_api_base@@Base+0xe302a>
│ │ @@ -426465,25 +426465,25 @@
│ │  	movs	r0, #12
│ │  	b.n	24fd7a <uniffi_pbcli_checksum_method_api_base@@Base+0xe34f6>
│ │  	movs	r4, r0
│ │  	b.n	24fa3e <uniffi_pbcli_checksum_method_api_base@@Base+0xe31ba>
│ │  	asrs	r0, r2, #1
│ │  	b.n	24fe42 <uniffi_pbcli_checksum_method_api_base@@Base+0xe35be>
│ │  			@ <UNDEFINED> instruction: 0xffd9eaff
│ │ -	cdp2	15, 8, cr15, cr9, cr4, {7}
│ │ +	cdp2	15, 11, cr15, cr0, cr4, {7}
│ │  	stmia	r6!, {r0, r2, r7}
│ │ -	vqrdmlsh.s32	<illegal reg q15.5>, <illegal reg q1.5>, d5[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe3ff8c
│ │  			@ <UNDEFINED> instruction: 0xffe4c761
│ │ -	vqrdmlsh.s32	<illegal reg q15.5>, <illegal reg q1.5>, d9[0]
│ │ +	vcvt.u32.f32	<illegal reg q15.5>, q8, #29
│ │  			@ <UNDEFINED> instruction: 0xffe4c745
│ │ -	vcvt.u32.f32	d31, d9, #29
│ │ +	vqrdmlsh.s32	<illegal reg q15.5>, <illegal reg q1.5>, d0[0]
│ │  	vqshl.u32	d28, d5, #4
│ │ -			@ <UNDEFINED> instruction: 0xffe3ff81
│ │ +			@ <UNDEFINED> instruction: 0xffe3ffa8
│ │  	vqshl.u32	q14, <illegal reg q14.5>, #4
│ │ -			@ <UNDEFINED> instruction: 0xffe3feb9
│ │ +	vqrdmlah.s32	<illegal reg q15.5>, <illegal reg q9.5>, d0[1]
│ │  	vqshlu.s64	d28, d21, #36	@ 0x24
│ │  	vqshrun.s64	d20, q8, #29
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	24fc58 <uniffi_pbcli_checksum_method_api_base@@Base+0xe33d4>
│ │  	ands	r0, r0
│ │  	b.n	24fa82 <uniffi_pbcli_checksum_method_api_base@@Base+0xe31fe>
│ │  	movs	r4, r0
│ │ @@ -426574,19 +426574,19 @@
│ │  	b.n	24ff42 <uniffi_pbcli_checksum_method_api_base@@Base+0xe36be>
│ │  	adds	r0, #0
│ │  	b.n	24ff46 <uniffi_pbcli_checksum_method_api_base@@Base+0xe36c2>
│ │  	adds	r2, r4, #6
│ │  	add.w	r0, r0, r5
│ │  	b.n	24fb4e <uniffi_pbcli_checksum_method_api_base@@Base+0xe32ca>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc}
│ │  	vqshlu.s64	q11, <illegal reg q12.5>, #36	@ 0x24
│ │ -			@ <UNDEFINED> instruction: 0xffe3fda5
│ │ +	vqrdmulh.s32	<illegal reg q15.5>, <illegal reg q9.5>, d12[0]
│ │  	vmlsl.u32	q11, d20, d9[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe3fd85
│ │ +			@ <UNDEFINED> instruction: 0xffe3fdac
│ │  	vrsubhn.i64	d22, q10, <illegal reg q12.5>
│ │  	vqshrun.s64	d20, q8, #29
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	24fd4c <uniffi_pbcli_checksum_method_api_base@@Base+0xe34c8>
│ │  	ands	r0, r0
│ │  	b.n	24fb76 <uniffi_pbcli_checksum_method_api_base@@Base+0xe32f2>
│ │  	lsls	r4, r3, #31
│ │ @@ -426699,22 +426699,22 @@
│ │  	movs	r0, #40	@ 0x28
│ │  	b.n	24f468 <uniffi_pbcli_checksum_method_api_base@@Base+0xe2be4>
│ │  	movs	r0, r0
│ │  	b.n	24fa4c <uniffi_pbcli_checksum_method_api_base@@Base+0xe31c8>
│ │  	movs	r0, #2
│ │  	b.n	24fa50 <uniffi_pbcli_checksum_method_api_base@@Base+0xe31cc>
│ │  			@ <UNDEFINED> instruction: 0xffd7eaff
│ │ -	ldc2l	15, cr15, [sp], {228}	@ 0xe4
│ │ +	stc2	15, cr15, [r4, #-912]	@ 0xfffffc70
│ │  	adds	r3, r2, #4
│ │ -			@ <UNDEFINED> instruction: 0xffe4fd0d
│ │ +	vcvt.u16.f16	d31, d20, #28
│ │  	vqrdmulh.s32	<illegal reg q8.5>, q2, d3[0]
│ │ -	vcvt.f16.u16	<illegal reg q15.5>, <illegal reg q14.5>, #28
│ │ +	vmull.u32	<illegal reg q15.5>, d20, d20
│ │  			@ <UNDEFINED> instruction: 0xffe41cb3
│ │ -	vqdmulh.s32	<illegal reg q15.5>, q2, d9[1]
│ │ -	vqdmulh.s32	<illegal reg q15.5>, q2, d1[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe4fc90
│ │ +	vqdmulh.s32	<illegal reg q15.5>, q2, d8[1]
│ │  	vcvt.f16.u16	<illegal reg q8.5>, <illegal reg q11.5>, #28
│ │  			@ <UNDEFINED> instruction: 0xffe44df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	24fe7c <uniffi_pbcli_checksum_method_api_base@@Base+0xe35f8>
│ │  	movs	r0, #4
│ │  	b.n	24f488 <uniffi_pbcli_checksum_method_api_base@@Base+0xe2c04>
│ │  	ands	r0, r0
│ │ @@ -426866,20 +426866,20 @@
│ │  	movs	r4, r0
│ │  	b.n	24fdea <uniffi_pbcli_checksum_method_api_base@@Base+0xe3566>
│ │  	movs	r0, #12
│ │  	b.n	25012e <uniffi_pbcli_checksum_method_api_base@@Base+0xe38aa>
│ │  	asrs	r0, r2, #1
│ │  	b.n	2501f2 <uniffi_pbcli_checksum_method_api_base@@Base+0xe396e>
│ │  			@ <UNDEFINED> instruction: 0xffcaeaff
│ │ -			@ <UNDEFINED> instruction: 0xfba5ffe4
│ │ +			@ <UNDEFINED> instruction: 0xfbccffe4
│ │  	subs	r6, r6, r7
│ │ -			@ <UNDEFINED> instruction: 0xffe4fb09
│ │ +			@ <UNDEFINED> instruction: 0xffe4fb30
│ │  			@ <UNDEFINED> instruction: 0xffe41b5a
│ │ -			@ <UNDEFINED> instruction: 0xffe4fb61
│ │ -			@ <UNDEFINED> instruction: 0xffe4fad5
│ │ +			@ <UNDEFINED> instruction: 0xffe4fb88
│ │ +			@ <UNDEFINED> instruction: 0xffe4fafc
│ │  			@ <UNDEFINED> instruction: 0xffe41b26
│ │  	vcvt.f16.u16	q10, q8, #28
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	24fff4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe3770>
│ │  	ldr	r0, [pc, #176]	@ (24fb8c <uniffi_pbcli_checksum_method_api_base@@Base+0xe3308>)
│ │  	b.n	24f5fe <uniffi_pbcli_checksum_method_api_base@@Base+0xe2d7a>
│ │  	str	r1, [r0, r0]
│ │ @@ -426981,19 +426981,19 @@
│ │  	ldmia.w	sp!, {r0, ip, lr}
│ │  	b.n	2502fa <uniffi_pbcli_checksum_method_api_base@@Base+0xe3a76>
│ │  	movs	r5, r0
│ │  	b.n	24fefe <uniffi_pbcli_checksum_method_api_base@@Base+0xe367a>
│ │  	ldr	r0, [r0, r0]
│ │  	b.n	24f6ce <uniffi_pbcli_checksum_method_api_base@@Base+0xe2e4a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r5, r6, r7, r8, fp, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r3, r9, fp, ip, sp, lr, pc}
│ │  	vsubw.u32	q11, q2, d19
│ │ -	vmlsl.u32	<illegal reg q15.5>, d3, d13
│ │ +	vshll.u32	<illegal reg q15.5>, d20, #3
│ │  			@ <UNDEFINED> instruction: 0xffe4634f
│ │ -	vshll.u32	<illegal reg q15.5>, d25, #3
│ │ +	vmull.u32	<illegal reg q15.5>, d3, d0[1]
│ │  	vrsra.u32	q11, <illegal reg q13.5>, #28
│ │  	vqshrun.s64	d20, q8, #29
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	250100 <uniffi_pbcli_checksum_method_api_base@@Base+0xe387c>
│ │  	str	r1, [r0, r0]
│ │  	b.n	25032a <uniffi_pbcli_checksum_method_api_base@@Base+0xe3aa6>
│ │  	lsrs	r1, r0, #4
│ │ @@ -427094,17 +427094,17 @@
│ │  	ldmia.w	sp!, {r0, ip, lr}
│ │  	b.n	250402 <uniffi_pbcli_checksum_method_api_base@@Base+0xe3b7e>
│ │  	ldrsb	r4, [r5, r7]
│ │  	b.n	24f7ce <uniffi_pbcli_checksum_method_api_base@@Base+0xe2f4a>
│ │  	movs	r5, r0
│ │  	b.n	25000a <uniffi_pbcli_checksum_method_api_base@@Base+0xe3786>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r4, r8, fp, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r3, r4, r5, r8, fp, ip, sp, lr, pc}
│ │  	vmlsl.u32	q15, d20, d18
│ │ -			@ <UNDEFINED> instruction: 0xffe3f8d9
│ │ +			@ <UNDEFINED> instruction: 0xffe3f900
│ │  	vmull.u32	q15, d4, d10[1]
│ │  			@ <UNDEFINED> instruction: 0xffe34df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	250200 <uniffi_pbcli_checksum_method_api_base@@Base+0xe397c>
│ │  	beq.n	24fd08 <uniffi_pbcli_checksum_method_api_base@@Base+0xe3484>
│ │  	b.n	250184 <uniffi_pbcli_checksum_method_api_base@@Base+0xe3900>
│ │  	str	r1, [r0, r0]
│ │ @@ -427299,21 +427299,21 @@
│ │  	str	r1, [r0, r0]
│ │  	b.n	2505ca <uniffi_pbcli_checksum_method_api_base@@Base+0xe3d46>
│ │  	movs	r5, r0
│ │  	b.n	2501ce <uniffi_pbcli_checksum_method_api_base@@Base+0xe394a>
│ │  	beq.n	24fec0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe363c>
│ │  	b.n	250328 <uniffi_pbcli_checksum_method_api_base@@Base+0xe3aa4>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r4, r6, fp, ip, sp, lr, pc}
│ │ -	vmlal.u32	<illegal reg q15.5>, d4, d17
│ │ -	vqshl.u32	<illegal reg q15.5>, <illegal reg q6.5>, #4
│ │ +	ldmia.w	sp!, {r3, r4, r5, r6, fp, ip, sp, lr, pc}
│ │ +	vmul.i32	<illegal reg q15.5>, q2, d8[0]
│ │ +	vabdl.u32	<illegal reg q15.5>, d20, d4
│ │  	vqrdmlah.s32	q9, q10, d11[1]
│ │ -	vqshl.u64	<illegal reg q15.5>, <illegal reg q8.5>, #36	@ 0x24
│ │ +	vqshrun.s64	d31, q4, #28
│ │  	vcvt.u32.f32	q9, <illegal reg q15.5>, #28
│ │ -	vabdl.u32	<illegal reg q15.5>, d4, d29
│ │ +	vqshl.u32	<illegal reg q15.5>, q2, #4
│ │  			@ <UNDEFINED> instruction: 0xffe42ebb
│ │  	vqshrun.s64	d20, q8, #28
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2503d8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe3b54>
│ │  	beq.n	24fee0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe365c>
│ │  	b.n	25035c <uniffi_pbcli_checksum_method_api_base@@Base+0xe3ad8>
│ │  	ands	r0, r0
│ │ @@ -427510,22 +427510,22 @@
│ │  	movs	r4, r0
│ │  	b.n	2503aa <uniffi_pbcli_checksum_method_api_base@@Base+0xe3b26>
│ │  	movs	r0, #12
│ │  	b.n	2506ee <uniffi_pbcli_checksum_method_api_base@@Base+0xe3e6a>
│ │  	asrs	r0, r2, #1
│ │  	b.n	2507b2 <uniffi_pbcli_checksum_method_api_base@@Base+0xe3f2e>
│ │  			@ <UNDEFINED> instruction: 0xffeceaff
│ │ -	bl	5e040 <UNIFFI_META_PBCLI_RECORD_OPTS@@Base-0x7fc0>
│ │ +	bl	85040 <UNIFFI_META_PBCLI_METHOD_API_BASE@@Base+0x1b826>
│ │  	add	r7, pc, #220	@ (adr r7, 250158 <uniffi_pbcli_checksum_method_api_base@@Base+0xe38d4>)
│ │ -	vqshlu.s32	d31, d25, #3
│ │ +	vmlsl.u32	<illegal reg q15.5>, d3, d0[1]
│ │  	vqrdmlah.s32	<illegal reg q12.5>, q2, d6[1]
│ │ -	vsli.32	<illegal reg q15.5>, <illegal reg q6.5>, #2
│ │ +	vabal.u32	<illegal reg q15.5>, d18, d4
│ │  	vrsubhn.i64	d26, q10, <illegal reg q3.5>
│ │ -	vsli.64	d31, d21, #35	@ 0x23
│ │ -	vsli.32	d31, d5, #4
│ │ +	vsli.64	<illegal reg q15.5>, q6, #35	@ 0x23
│ │ +	vsli.32	d31, d28, #4
│ │  	vqshlu.s32	d26, d31, #4
│ │  			@ <UNDEFINED> instruction: 0xffe34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2505bc <uniffi_pbcli_checksum_method_api_base@@Base+0xe3d38>
│ │  	beq.n	2500ac <uniffi_pbcli_checksum_method_api_base@@Base+0xe3828>
│ │  	b.n	250540 <uniffi_pbcli_checksum_method_api_base@@Base+0xe3cbc>
│ │  	add	r0, pc, #0	@ (adr r0, 2500a8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe3824>)
│ │ @@ -427870,31 +427870,31 @@
│ │  	movs	r0, #76	@ 0x4c
│ │  	b.n	24fed4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe3650>
│ │  	movs	r0, r0
│ │  	b.n	2504b8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe3c34>
│ │  	movs	r0, #2
│ │  	b.n	2504bc <uniffi_pbcli_checksum_method_api_base@@Base+0xe3c38>
│ │  			@ <UNDEFINED> instruction: 0xffbdeaff
│ │ -	bl	ffeba36c <uniffi_pbcli_checksum_method_api_base@@Base+0xffd4dae8>
│ │ +	bl	ffee136c <uniffi_pbcli_checksum_method_api_base@@Base+0xffd74ae8>
│ │  	cdp2	15, 11, cr15, cr15, cr3, {7}
│ │ -	bl	ffee6374 <uniffi_pbcli_checksum_method_api_base@@Base+0xffd79af0>
│ │ +	bl	fff0d374 <uniffi_pbcli_checksum_method_api_base@@Base+0xffda0af0>
│ │  	cdp2	15, 14, cr15, cr11, cr3, {7}
│ │ -	bl	58237c <uniffi_pbcli_checksum_method_api_base@@Base+0x415af8>
│ │ +	bl	5a937c <uniffi_pbcli_checksum_method_api_base@@Base+0x43caf8>
│ │  	stc2	15, cr15, [r7, #908]	@ 0x38c
│ │ -	bl	566384 <uniffi_pbcli_checksum_method_api_base@@Base+0x3f9b00>
│ │ +	bl	58d384 <uniffi_pbcli_checksum_method_api_base@@Base+0x420b00>
│ │  	stc2l	15, cr15, [fp, #-908]!	@ 0xfffffc74
│ │ -	bl	5e238c <uniffi_pbcli_checksum_method_api_base@@Base+0x475b08>
│ │ -	bl	52a390 <uniffi_pbcli_checksum_method_api_base@@Base+0x3bdb0c>
│ │ +	bl	60938c <uniffi_pbcli_checksum_method_api_base@@Base+0x49cb08>
│ │ +	bl	551390 <uniffi_pbcli_checksum_method_api_base@@Base+0x3e4b0c>
│ │  	stc2	15, cr15, [pc, #-908]!	@ 250040 <uniffi_pbcli_checksum_method_api_base@@Base+0xe37bc>
│ │ -	bl	59e398 <uniffi_pbcli_checksum_method_api_base@@Base+0x431b14>
│ │ +	bl	5c5398 <uniffi_pbcli_checksum_method_api_base@@Base+0x458b14>
│ │  	stc2	15, cr15, [r3, #908]!	@ 0x38c
│ │ -	bl	4963a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x329b1c>
│ │ +	bl	4bd3a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x350b1c>
│ │  	ldc2	15, cr15, [fp], {227}	@ 0xe3
│ │ -	bl	4623a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x2f5b24>
│ │ -	bl	4263ac <uniffi_pbcli_checksum_method_api_base@@Base+0x2b9b28>
│ │ +	bl	4893a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x31cb24>
│ │ +	bl	44d3ac <uniffi_pbcli_checksum_method_api_base@@Base+0x2e0b28>
│ │  	stc2	15, cr15, [fp], #-908	@ 0xfffffc74
│ │  	ldr	r0, [pc, #960]	@ (2507ac <uniffi_pbcli_checksum_method_api_base@@Base+0xe3f28>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	25090c <uniffi_pbcli_checksum_method_api_base@@Base+0xe4088>
│ │  	ands	r0, r0
│ │  	b.n	250736 <uniffi_pbcli_checksum_method_api_base@@Base+0xe3eb2>
│ │  	movs	r4, r0
│ │ @@ -428069,22 +428069,22 @@
│ │  	b.n	250b6e <uniffi_pbcli_checksum_method_api_base@@Base+0xe42ea>
│ │  			@ <UNDEFINED> instruction: 0xffc4eaff
│ │  	lsrs	r0, r5, #2
│ │  	b.n	25007e <uniffi_pbcli_checksum_method_api_base@@Base+0xe37fa>
│ │  	movs	r1, r0
│ │  	b.n	250cba <uniffi_pbcli_checksum_method_api_base@@Base+0xe4436>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r8, ip, sp, lr, pc}
│ │ -	vsri.64	d28, d9, #28
│ │ -	vshr.u64	d31, d29, #28
│ │ -	vsri.32	q14, <illegal reg q2.5>, #28
│ │ -	vshr.u32	d31, d9, #28
│ │ -	vrsra.u64	d28, d17, #28
│ │ -	vshr.u32	d31, d21, #28
│ │ -			@ <UNDEFINED> instruction: 0xffe4c3cd
│ │ +	ldmia.w	sp!, {r3, r5, r8, ip, sp, lr, pc}
│ │ +	vmls.i32	q14, q10, d0[0]
│ │ +	vmla.i32	<illegal reg q15.5>, q10, d4[1]
│ │ +	vsri.32	q14, q14, #28
│ │ +	vmla.i32	<illegal reg q15.5>, q2, d0[0]
│ │ +	vrsra.u64	q14, q4, #28
│ │ +	vshr.u32	<illegal reg q15.5>, q6, #28
│ │ +	vrsra.u64	q14, q10, #28
│ │  	vabdl.u32	<illegal reg q8.5>, d20, d10
│ │  	b.n	250142 <uniffi_pbcli_checksum_method_api_base@@Base+0xe38be>
│ │  	movs	r0, r1
│ │  	b.n	250bc8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe4344>
│ │  	movs	r2, r1
│ │  	subs	r0, r0, r0
│ │  	asrs	r4, r6, #8
│ │ @@ -428273,19 +428273,19 @@
│ │  	movs	r6, r0
│ │  	b.n	250a82 <uniffi_pbcli_checksum_method_api_base@@Base+0xe41fe>
│ │  	asrs	r7, r5, #32
│ │  	b.n	250e86 <uniffi_pbcli_checksum_method_api_base@@Base+0xe4602>
│ │  	movs	r0, #116	@ 0x74
│ │  	b.n	250e8a <uniffi_pbcli_checksum_method_api_base@@Base+0xe4606>
│ │  			@ <UNDEFINED> instruction: 0xffd5eaff
│ │ -	cdp	15, 14, cr15, cr1, cr4, {7}
│ │ +	vmax.f32	<illegal reg q7.5>, q12, q10
│ │  	strh	r0, [r2, #60]	@ 0x3c
│ │ -	vcvt.f32.u32	d30, d29, #29
│ │ +	vqrdmlah.s32	q15, <illegal reg q1.5>, d4[1]
│ │  	vmlsl.u32	q12, d20, d12[1]
│ │ -	vcvt.f32.u32	q15, <illegal reg q8.5>, #29
│ │ +			@ <UNDEFINED> instruction: 0xffe3ee98
│ │  	vabdl.u32	q12, d4, d16
│ │  			@ <UNDEFINED> instruction: 0xffe34bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	250c88 <uniffi_pbcli_checksum_method_api_base@@Base+0xe4404>
│ │  	beq.n	250790 <uniffi_pbcli_checksum_method_api_base@@Base+0xe3f0c>
│ │  	b.n	250c0c <uniffi_pbcli_checksum_method_api_base@@Base+0xe4388>
│ │  	strh	r0, [r7, r0]
│ │ @@ -428777,35 +428777,35 @@
│ │  			@ <UNDEFINED> instruction: 0xffeeeaff
│ │  	movs	r7, r0
│ │  	b.n	250ee6 <uniffi_pbcli_checksum_method_api_base@@Base+0xe4662>
│ │  			@ <UNDEFINED> instruction: 0xb88f
│ │  	add.w	r0, r2, r0, lsl #24
│ │  	b.n	2512ee <uniffi_pbcli_checksum_method_api_base@@Base+0xe4a6a>
│ │  	vpmin.u8	q7, q10, <illegal reg q15.5>
│ │ -	stcl	15, cr15, [sp, #912]	@ 0x390
│ │ +	ldcl	15, cr15, [r4, #912]!	@ 0x390
│ │  	ldr	r3, [r4, #104]	@ 0x68
│ │ -	vcvt.u16.f16	q15, <illegal reg q12.5>, #29
│ │ +			@ <UNDEFINED> instruction: 0xffe3eda0
│ │  	vqrdmlah.s32	q11, q2, d15[0]
│ │ -	vcvt.f16.u16	d30, d21, #29
│ │ +	vcvt.f16.u16	q15, q6, #29
│ │  			@ <UNDEFINED> instruction: 0xffe46d0b
│ │ -			@ <UNDEFINED> instruction: 0xffe3ebe9
│ │ +	vcvt.f16.u16	d30, d0, #29
│ │  			@ <UNDEFINED> instruction: 0xffe46cbf
│ │ -	vmull.u32	q15, d19, d9[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe3eb10
│ │  			@ <UNDEFINED> instruction: 0xffe46bbf
│ │ -	vcvt.f16.u16	d30, d9, #29
│ │ +	vqdmulh.s32	q15, <illegal reg q1.5>, d0[0]
│ │  	vqdmulh.s32	q11, q10, d15[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe3eab9
│ │ +	vmull.u32	q15, d19, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffe46b8f
│ │ -			@ <UNDEFINED> instruction: 0xffe3eb61
│ │ +			@ <UNDEFINED> instruction: 0xffe3eb88
│ │  	vcvt.f16.u16	d22, d23, #28
│ │ -			@ <UNDEFINED> instruction: 0xffe3ebcd
│ │ +			@ <UNDEFINED> instruction: 0xffe3ebf4
│ │  	vmull.u32	q11, d20, d19
│ │ -	vmlsl.u32	q15, d3, d25
│ │ +			@ <UNDEFINED> instruction: 0xffe3ea50
│ │  			@ <UNDEFINED> instruction: 0xffe46aff
│ │ -	vmul.f32	q15, <illegal reg q9.5>, d9[1]
│ │ +	vshll.u32	q15, d0, #3
│ │  			@ <UNDEFINED> instruction: 0xffe46abf
│ │  			@ <UNDEFINED> instruction: 0xffe348f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	25112c <uniffi_pbcli_checksum_method_api_base@@Base+0xe48a8>
│ │  	movs	r0, #4
│ │  	b.n	250738 <uniffi_pbcli_checksum_method_api_base@@Base+0xe3eb4>
│ │  	ands	r0, r0
│ │ @@ -428902,18 +428902,18 @@
│ │  	b.n	25141a <uniffi_pbcli_checksum_method_api_base@@Base+0xe4b96>
│ │  	str	r0, [r0, #0]
│ │  	b.n	25141e <uniffi_pbcli_checksum_method_api_base@@Base+0xe4b9a>
│ │  	adds	r4, r5, r1
│ │  	add.w	r0, r0, r6
│ │  	b.n	251026 <uniffi_pbcli_checksum_method_api_base@@Base+0xe47a2>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r7, r8, sl, fp, pc}
│ │ -	vqrdmulh.s32	q12, q2, d13[0]
│ │ -	vmlal.u32	q15, d20, d29
│ │ -	vaddl.u32	q8, d20, d31
│ │ +	ldmia.w	sp!, {r2, r3, r5, r7, r8, sl, fp, pc}
│ │ +	vcvt.u16.f16	q12, q10, #28
│ │ +			@ <UNDEFINED> instruction: 0xffe4e8d4
│ │ +	vshr.u64	q8, q3, #28
│ │  	vqshrun.s64	d20, q8, #27
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	25121c <uniffi_pbcli_checksum_method_api_base@@Base+0xe4998>
│ │  	ands	r0, r0
│ │  	b.n	251046 <uniffi_pbcli_checksum_method_api_base@@Base+0xe47c2>
│ │  	movs	r4, r0
│ │  	b.n	25082c <uniffi_pbcli_checksum_method_api_base@@Base+0xe3fa8>
│ │ @@ -429064,22 +429064,22 @@
│ │  	add.w	r0, r2, r0, lsl #20
│ │  	b.n	25158a <uniffi_pbcli_checksum_method_api_base@@Base+0xe4d06>
│ │  	movs	r4, r0
│ │  	b.n	25118e <uniffi_pbcli_checksum_method_api_base@@Base+0xe490a>
│ │  	asrs	r7, r5, #32
│ │  	b.n	251592 <uniffi_pbcli_checksum_method_api_base@@Base+0xe4d0e>
│ │  			@ <UNDEFINED> instruction: 0xffc0eaff
│ │ -			@ <UNDEFINED> instruction: 0xe829ffe4
│ │ -	lsls	r1, r0, #1
│ │ -	vqshl.u32	d30, d17, #5
│ │ -	vqrdmlsh.s32	<illegal reg q15.5>, q2, d9[0]
│ │ -	vqshl.u64	q15, <illegal reg q8.5>, #36	@ 0x24
│ │ -	vaddl.u32	q8, d4, d9
│ │ -	vqshl.u64	d30, d17, #37	@ 0x25
│ │ -	vqrdmlsh.s32	<illegal reg q15.5>, q10, d9[0]
│ │ +	ldrex	pc, [r0, #912]	@ 0x390
│ │ +	lsls	r0, r5, #1
│ │ +	vqshl.u32	q15, q4, #5
│ │ +	vcvt.u32.f32	<illegal reg q15.5>, q8, #28
│ │ +	vqshrun.s64	d30, q4, #28
│ │ +	vshr.u32	d16, d16, #28
│ │ +	vqshl.u64	q15, q4, #37	@ 0x25
│ │ +			@ <UNDEFINED> instruction: 0xffe4fff0
│ │  	vcvt.f16.u16	q10, q8, #28
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	251398 <uniffi_pbcli_checksum_method_api_base@@Base+0xe4b14>
│ │  	ands	r0, r0
│ │  	b.n	2511c2 <uniffi_pbcli_checksum_method_api_base@@Base+0xe493e>
│ │  	movs	r4, r0
│ │  	b.n	2509a8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe4124>
│ │ @@ -429262,19 +429262,19 @@
│ │  	movs	r5, r0
│ │  	b.n	251356 <uniffi_pbcli_checksum_method_api_base@@Base+0xe4ad2>
│ │  	strh	r4, [r5, r5]
│ │  	b.n	250b22 <uniffi_pbcli_checksum_method_api_base@@Base+0xe429e>
│ │  	asrs	r4, r3, #28
│ │  	b.n	250b26 <uniffi_pbcli_checksum_method_api_base@@Base+0xe42a2>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r7, r9, sl, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r6, r7, r9, sl, sp, lr, pc}
│ │  	vrshr.u32	<illegal reg q15.5>, q13, #28
│ │ -	vqshlu.s32	d30, d13, #2
│ │ +	vmlsl.u32	q15, d2, d4[0]
│ │  	vmla.f32	<illegal reg q15.5>, q10, d2[1]
│ │ -	vqshlu.s32	q15, <illegal reg q0.5>, #2
│ │ +	vqshlu.s32	q15, q12, #2
│ │  	vrshr.u32	d31, d6, #28
│ │  	vcvt.f16.u16	q10, q8, #30
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	25155c <uniffi_pbcli_checksum_method_api_base@@Base+0xe4cd8>
│ │  	beq.n	251054 <uniffi_pbcli_checksum_method_api_base@@Base+0xe47d0>
│ │  	b.n	2514e0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe4c5c>
│ │  	str	r0, [r0, r0]
│ │ @@ -429369,15 +429369,15 @@
│ │  	and.w	r0, r0, r2, lsl #16
│ │  	b.n	25184e <uniffi_pbcli_checksum_method_api_base@@Base+0xe4fca>
│ │  	movs	r4, r0
│ │  	b.n	251452 <uniffi_pbcli_checksum_method_api_base@@Base+0xe4bce>
│ │  	beq.n	251134 <uniffi_pbcli_checksum_method_api_base@@Base+0xe48b0>
│ │  	b.n	2515ac <uniffi_pbcli_checksum_method_api_base@@Base+0xe4d28>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r3, r7, sl, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r4, r5, r7, sl, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffe4bfa0
│ │  	vcvt.f16.u16	q10, q8, #30
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	251644 <uniffi_pbcli_checksum_method_api_base@@Base+0xe4dc0>
│ │  	ands	r0, r0
│ │  	b.n	25146e <uniffi_pbcli_checksum_method_api_base@@Base+0xe4bea>
│ │  	movs	r4, r0
│ │ @@ -429487,21 +429487,21 @@
│ │  	b.n	250d58 <uniffi_pbcli_checksum_method_api_base@@Base+0xe44d4>
│ │  	movs	r0, r0
│ │  	b.n	25133c <uniffi_pbcli_checksum_method_api_base@@Base+0xe4ab8>
│ │  	movs	r0, #2
│ │  	b.n	251340 <uniffi_pbcli_checksum_method_api_base@@Base+0xe4abc>
│ │  	asrs	r7, r2, #29
│ │  			@ <UNDEFINED> instruction: 0xeb02ffe4
│ │ -			@ <UNDEFINED> instruction: 0xeaffe3d9
│ │ +			@ <UNDEFINED> instruction: 0xeaffe400
│ │  	vsli.32	d25, d6, #4
│ │ -	vrsra.u32	q15, <illegal reg q0.5>, #29
│ │ +	vrsra.u32	q15, q12, #29
│ │  	vraddhn.i64	d25, q10, q7
│ │ -	vrsra.u64	d30, d29, #29
│ │ +			@ <UNDEFINED> instruction: 0xffe3e3e4
│ │  	vsri.64	<illegal reg q12.5>, q13, #28
│ │ -	vsubw.u32	q15, <illegal reg q9.5>, d1
│ │ +	vsubw.u32	q15, <illegal reg q9.5>, d24
│ │  	vsri.64	d25, d30, #28
│ │  	vcvt.f16.u16	q10, q8, #29
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	25176c <uniffi_pbcli_checksum_method_api_base@@Base+0xe4ee8>
│ │  	beq.n	251264 <uniffi_pbcli_checksum_method_api_base@@Base+0xe49e0>
│ │  	b.n	2516f0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe4e6c>
│ │  	str	r0, [r0, r0]
│ │ @@ -429596,16 +429596,16 @@
│ │  	and.w	r0, r0, r2, lsl #16
│ │  	b.n	251a5e <uniffi_pbcli_checksum_method_api_base@@Base+0xe51da>
│ │  	movs	r4, r0
│ │  	b.n	251662 <uniffi_pbcli_checksum_method_api_base@@Base+0xe4dde>
│ │  	beq.n	251344 <uniffi_pbcli_checksum_method_api_base@@Base+0xe4ac0>
│ │  	b.n	2517bc <uniffi_pbcli_checksum_method_api_base@@Base+0xe4f38>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r6, r9, sp, lr, pc}
│ │ -	vshr.u64	d17, d27, #28
│ │ +	ldmia.w	sp!, {r5, r7, r9, sp, lr, pc}
│ │ +	vmla.i32	<illegal reg q8.5>, q10, d2[1]
│ │  	vcvt.f16.u16	q10, q8, #27
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	251854 <uniffi_pbcli_checksum_method_api_base@@Base+0xe4fd0>
│ │  	ands	r0, r0
│ │  	b.n	25167e <uniffi_pbcli_checksum_method_api_base@@Base+0xe4dfa>
│ │  	movs	r4, r0
│ │  	b.n	250e64 <uniffi_pbcli_checksum_method_api_base@@Base+0xe45e0>
│ │ @@ -429714,21 +429714,21 @@
│ │  	b.n	250f68 <uniffi_pbcli_checksum_method_api_base@@Base+0xe46e4>
│ │  	movs	r0, r0
│ │  	b.n	25154c <uniffi_pbcli_checksum_method_api_base@@Base+0xe4cc8>
│ │  	movs	r0, #2
│ │  	b.n	251550 <uniffi_pbcli_checksum_method_api_base@@Base+0xe4ccc>
│ │  	asrs	r3, r2, #27
│ │  			@ <UNDEFINED> instruction: 0xeb02ffe4
│ │ -			@ <UNDEFINED> instruction: 0xeaffe1c9
│ │ +			@ <UNDEFINED> instruction: 0xeaffe1f0
│ │  	vmls.f32	<illegal reg q14.5>, q2, d2[0]
│ │ -	vmla.f32	q15, q1, d1[0]
│ │ +	vmla.f32	q15, q1, d8[1]
│ │  	vsri.64	d29, d26, #28
│ │ -	vaddw.u32	q15, q9, d29
│ │ +	vsra.u64	q15, q2, #30
│ │  	vabal.u32	<illegal reg q14.5>, d4, d22
│ │ -	vsra.u32	q15, <illegal reg q8.5>, #30
│ │ +	vsra.u64	d30, d8, #30
│ │  	vmls.i32	<illegal reg q14.5>, q10, d10[1]
│ │  	vcvt.f16.u16	d20, d0, #30
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	25197c <uniffi_pbcli_checksum_method_api_base@@Base+0xe50f8>
│ │  	stmia	r0!, {r2}
│ │  	b.n	250f86 <uniffi_pbcli_checksum_method_api_base@@Base+0xe4702>
│ │  	movs	r0, r0
│ │ @@ -429972,17 +429972,17 @@
│ │  	asrs	r1, r1, #24
│ │  	add.w	r0, r0, r5
│ │  	b.n	2519b2 <uniffi_pbcli_checksum_method_api_base@@Base+0xe512e>
│ │  	beq.n	2516ac <uniffi_pbcli_checksum_method_api_base@@Base+0xe4e28>
│ │  	b.n	251b0c <uniffi_pbcli_checksum_method_api_base@@Base+0xe5288>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r5, r6, r8, r9, sl, ip}
│ │ -	vcvt.f16.u16	<illegal reg q9.5>, q3, #28
│ │ +	vcvt.f16.u16	<illegal reg q9.5>, <illegal reg q14.5>, #28
│ │  	vqshlu.s64	<illegal reg q8.5>, q2, #37	@ 0x25
│ │ -			@ <UNDEFINED> instruction: 0xffe43bca
│ │ +			@ <UNDEFINED> instruction: 0xffe43bf1
│ │  			@ <UNDEFINED> instruction: 0xffe54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	251bac <uniffi_pbcli_checksum_method_api_base@@Base+0xe5328>
│ │  	beq.n	25170c <uniffi_pbcli_checksum_method_api_base@@Base+0xe4e88>
│ │  	b.n	251b30 <uniffi_pbcli_checksum_method_api_base@@Base+0xe52ac>
│ │  	add	r6, pc, #688	@ (adr r6, 251948 <uniffi_pbcli_checksum_method_api_base@@Base+0xe50c4>)
│ │  	b.n	2511ba <uniffi_pbcli_checksum_method_api_base@@Base+0xe4936>
│ │ @@ -431695,15 +431695,15 @@
│ │  	add.w	r0, r3, r0
│ │  	b.n	252bfa <uniffi_pbcli_checksum_method_api_base@@Base+0xe6376>
│ │  	movs	r0, r0
│ │  	b.n	252066 <uniffi_pbcli_checksum_method_api_base@@Base+0xe57e2>
│ │  	movs	r1, r0
│ │  	asrs	r0, r0, #12
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r5, r7, sl, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r2, r3, r6, r7, sl, ip, sp, lr}
│ │  	vqshrun.s64	d20, q8, #28
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	252a8c <uniffi_pbcli_checksum_method_api_base@@Base+0xe6208>
│ │  	str	r0, [r0, r0]
│ │  	b.n	2528b6 <uniffi_pbcli_checksum_method_api_base@@Base+0xe6032>
│ │  	movs	r4, r0
│ │  	b.n	25209c <uniffi_pbcli_checksum_method_api_base@@Base+0xe5818>
│ │ @@ -431779,17 +431779,17 @@
│ │  	adds	r0, #0
│ │  	b.n	252d56 <uniffi_pbcli_checksum_method_api_base@@Base+0xe64d2>
│ │  	asrs	r6, r3, #8
│ │  	add.w	r0, r0, r4
│ │  	b.n	25295e <uniffi_pbcli_checksum_method_api_base@@Base+0xe60da>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r4, r6, r7, r8, r9, sl, fp, pc}
│ │ -	vcvt.f16.u16	q9, <illegal reg q5.5>, #30
│ │ +	vmull.u32	q9, d18, d2
│ │  			@ <UNDEFINED> instruction: 0xffe58fa1
│ │ -	vmull.u32	q9, d2, d27
│ │ +	vcvt.f16.u16	q9, q1, #30
│ │  			@ <UNDEFINED> instruction: 0xffe548f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	252b54 <uniffi_pbcli_checksum_method_api_base@@Base+0xe62d0>
│ │  	movs	r0, #4
│ │  	b.n	252160 <uniffi_pbcli_checksum_method_api_base@@Base+0xe58dc>
│ │  	ands	r0, r0
│ │  	b.n	252982 <uniffi_pbcli_checksum_method_api_base@@Base+0xe60fe>
│ │ @@ -431904,15 +431904,15 @@
│ │  	movs	r4, r0
│ │  	b.n	252a72 <uniffi_pbcli_checksum_method_api_base@@Base+0xe61ee>
│ │  	asrs	r0, r2, #1
│ │  	b.n	252e76 <uniffi_pbcli_checksum_method_api_base@@Base+0xe65f2>
│ │  			@ <UNDEFINED> instruction: 0xffdfeaff
│ │  	ldrh	r5, [r7, #54]	@ 0x36
│ │  			@ <UNDEFINED> instruction: 0xffe25d94
│ │ -	vsubw.u32	<illegal reg q11.5>, q1, d5
│ │ +	vsubw.u32	<illegal reg q11.5>, q1, d28
│ │  	vmull.p64	q12, d20, d5
│ │  	vcvt.u16.f16	d21, d12, #30
│ │  			@ <UNDEFINED> instruction: 0xffe24df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	252c70 <uniffi_pbcli_checksum_method_api_base@@Base+0xe63ec>
│ │  	movs	r0, #4
│ │  	b.n	25227c <uniffi_pbcli_checksum_method_api_base@@Base+0xe59f8>
│ │ @@ -432048,15 +432048,15 @@
│ │  	add.w	r0, r0, r0, lsl #24
│ │  	b.n	252fb6 <uniffi_pbcli_checksum_method_api_base@@Base+0xe6732>
│ │  	movs	r6, r0
│ │  	b.n	252bba <uniffi_pbcli_checksum_method_api_base@@Base+0xe6336>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, r3, r4, r6, r7, r8, sl, fp, pc}
│ │  	vqshlu.s32	q11, q13, #2
│ │ -	vmla.f32	<illegal reg q11.5>, <illegal reg q9.5>, d1[1]
│ │ +	vsubl.u32	<illegal reg q11.5>, d3, d8
│ │  	vqrdmulh.s32	q12, q2, d13[0]
│ │  	vmls.f32	q11, q9, d14[1]
│ │  			@ <UNDEFINED> instruction: 0xffe348f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	252db4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe6530>
│ │  	ldr	r4, [r5, #0]
│ │  	b.n	2523be <uniffi_pbcli_checksum_method_api_base@@Base+0xe5b3a>
│ │ @@ -432341,17 +432341,17 @@
│ │  	asrs	r3, r4, #3
│ │  	add.w	r0, r0, r5
│ │  	b.n	252e4a <uniffi_pbcli_checksum_method_api_base@@Base+0xe65c6>
│ │  	beq.n	252b1c <uniffi_pbcli_checksum_method_api_base@@Base+0xe6298>
│ │  	b.n	252fa4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe6720>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r3, r4, r5, r7, r9, fp, pc}
│ │ -	vshr.u64	d23, d22, #30
│ │ +	vshr.u64	<illegal reg q11.5>, <illegal reg q6.5>, #30
│ │  			@ <UNDEFINED> instruction: 0xffe48af1
│ │ -	vmla.i32	<illegal reg q11.5>, q9, d14[1]
│ │ +	vsra.u32	d23, d5, #30
│ │  			@ <UNDEFINED> instruction: 0xffe44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	253044 <uniffi_pbcli_checksum_method_api_base@@Base+0xe67c0>
│ │  	beq.n	252b44 <uniffi_pbcli_checksum_method_api_base@@Base+0xe62c0>
│ │  	b.n	252fc8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe6744>
│ │  	movs	r0, r0
│ │  	b.n	2531d8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe6954>
│ │ @@ -432712,35 +432712,35 @@
│ │  	asrs	r0, r2, #1
│ │  	add.w	r1, r2, r3, lsl #8
│ │  	b.n	253446 <uniffi_pbcli_checksum_method_api_base@@Base+0xe6bc2>
│ │  	movs	r0, #12
│ │  	b.n	2534ca <uniffi_pbcli_checksum_method_api_base@@Base+0xe6c46>
│ │  			@ <UNDEFINED> instruction: 0xffd8eaff
│ │  	ldrh	r5, [r0, #14]
│ │ -	vqrdmulh.s32	<illegal reg q12.5>, q1, d5[0]
│ │ +	vqrdmulh.s32	<illegal reg q12.5>, q1, d12[1]
│ │  	vmul.f32	q12, q10, d1[1]
│ │ -	vqrdmulh.s32	<illegal reg q12.5>, q1, d1[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe29d88
│ │  	vrsubhn.i64	d26, q2, q6
│ │  	movs	r0, r5
│ │  	strh	r5, [r7, #62]	@ 0x3e
│ │ -			@ <UNDEFINED> instruction: 0xffe29b7d
│ │ +			@ <UNDEFINED> instruction: 0xffe29ba4
│ │  			@ <UNDEFINED> instruction: 0xffe487c9
│ │ -			@ <UNDEFINED> instruction: 0xffe29b49
│ │ +			@ <UNDEFINED> instruction: 0xffe29b70
│ │  	vabdl.u32	q12, d20, d29
│ │ -			@ <UNDEFINED> instruction: 0xffe29b2d
│ │ +			@ <UNDEFINED> instruction: 0xffe29b54
│ │  	vabdl.u32	q12, d20, d9
│ │ -			@ <UNDEFINED> instruction: 0xffe29b09
│ │ +			@ <UNDEFINED> instruction: 0xffe29b30
│ │  			@ <UNDEFINED> instruction: 0xffe48765
│ │ -	vmull.u32	<illegal reg q12.5>, d18, d5[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe29b0c
│ │  	vqshrun.s64	d24, <illegal reg q4.5>, #28
│ │ -			@ <UNDEFINED> instruction: 0xffe29b99
│ │ +			@ <UNDEFINED> instruction: 0xffe29bc0
│ │  	vmls.i32	q13, q10, d0[0]
│ │  	movs	r0, r5
│ │  	ldrh	r1, [r7, #0]
│ │ -			@ <UNDEFINED> instruction: 0xffe29bb9
│ │ +			@ <UNDEFINED> instruction: 0xffe29be0
│ │  	vaddw.u32	<illegal reg q8.5>, q10, d20
│ │  	b.n	2529c2 <uniffi_pbcli_checksum_method_api_base@@Base+0xe613e>
│ │  	movs	r0, r0
│ │  	b.n	253548 <uniffi_pbcli_checksum_method_api_base@@Base+0xe6cc4>
│ │  	asrs	r0, r5, #8
│ │  	asrs	r0, r2, #22
│ │  	movs	r0, r0
│ │ @@ -432938,15 +432938,15 @@
│ │  	b.n	25378a <uniffi_pbcli_checksum_method_api_base@@Base+0xe6f06>
│ │  			@ <UNDEFINED> instruction: 0xffc1eaff
│ │  	strh	r1, [r1, #44]	@ 0x2c
│ │  	vsri.32	d21, d19, #30
│ │  	vmlsl.u32	q12, d2, d1[1]
│ │  	vabal.u32	<illegal reg q10.5>, d2, d11
│ │  	vsli.64	q12, <illegal reg q12.5>, #34	@ 0x22
│ │ -	vmlsl.u32	q11, d2, d17
│ │ +	vmull.u32	q11, d2, d8[0]
│ │  	vmls.f32	q12, q2, d13[1]
│ │  	vsri.32	d21, d7, #30
│ │  			@ <UNDEFINED> instruction: 0xffe24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	253590 <uniffi_pbcli_checksum_method_api_base@@Base+0xe6d0c>
│ │  	beq.n	253080 <uniffi_pbcli_checksum_method_api_base@@Base+0xe67fc>
│ │  	b.n	253514 <uniffi_pbcli_checksum_method_api_base@@Base+0xe6c90>
│ │ @@ -433258,15 +433258,15 @@
│ │  	asrs	r0, r4, #14
│ │  	movs	r5, r0
│ │  	b.n	25365e <uniffi_pbcli_checksum_method_api_base@@Base+0xe6dda>
│ │  	ldr	r4, [r1, r1]
│ │  	asrs	r4, r0, #22
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r2, r6, r7, r9, pc}
│ │ -	vmul.i32	q8, q9, d2[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe20909
│ │  			@ <UNDEFINED> instruction: 0xffe54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	253850 <uniffi_pbcli_checksum_method_api_base@@Base+0xe6fcc>
│ │  	beq.n	253370 <uniffi_pbcli_checksum_method_api_base@@Base+0xe6aec>
│ │  	b.n	2537d4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe6f50>
│ │  	ands	r0, r0
│ │  	b.n	25367e <uniffi_pbcli_checksum_method_api_base@@Base+0xe6dfa>
│ │ @@ -433678,31 +433678,31 @@
│ │  	b.n	2539f6 <uniffi_pbcli_checksum_method_api_base@@Base+0xe7172>
│ │  	asrs	r0, r2, #1
│ │  	b.n	253dfa <uniffi_pbcli_checksum_method_api_base@@Base+0xe7576>
│ │  	movs	r1, #58	@ 0x3a
│ │  	b.n	253cbe <uniffi_pbcli_checksum_method_api_base@@Base+0xe743a>
│ │  	vpmin.u32	q15, <illegal reg q14.5>, <illegal reg q15.5>
│ │  	strh	r5, [r4, #16]
│ │ -	vqrdmulh.s32	<illegal reg q11.5>, q9, d15[1]
│ │ +	vcvt.f32.u32	d23, d6, #30
│ │  	vsra.u32	d24, d29, #28
│ │ -			@ <UNDEFINED> instruction: 0xffe27d07
│ │ +			@ <UNDEFINED> instruction: 0xffe27d2e
│ │  	vshr.u64	q12, <illegal reg q14.5>, #28
│ │ -	vqdmulh.s32	<illegal reg q11.5>, q9, d7[0]
│ │ +	vqdmulh.s32	<illegal reg q11.5>, q9, d14[1]
│ │  	vcvt.u32.f32	<illegal reg q11.5>, <illegal reg q2.5>, #28
│ │ -			@ <UNDEFINED> instruction: 0xffe27b1f
│ │ +			@ <UNDEFINED> instruction: 0xffe27b46
│ │  	vmla.f32	q12, q2, d13[1]
│ │ -	vcvt.u16.f16	d23, d23, #30
│ │ +	vcvt.u16.f16	<illegal reg q11.5>, q7, #30
│ │  	vcvt.u32.f32	d23, d5, #28
│ │ -			@ <UNDEFINED> instruction: 0xffe27adf
│ │ +			@ <UNDEFINED> instruction: 0xffe27b06
│ │  	vcvt.u32.f32	d23, d17, #28
│ │ -			@ <UNDEFINED> instruction: 0xffe27afb
│ │ +			@ <UNDEFINED> instruction: 0xffe27b22
│ │  			@ <UNDEFINED> instruction: 0xffe47ef9
│ │ -	vmull.u32	<illegal reg q11.5>, d18, d3[0]
│ │ +	vmull.u32	<illegal reg q11.5>, d18, d10[1]
│ │  			@ <UNDEFINED> instruction: 0xffe47f85
│ │ -			@ <UNDEFINED> instruction: 0xffe27b4f
│ │ +			@ <UNDEFINED> instruction: 0xffe27b76
│ │  			@ <UNDEFINED> instruction: 0xffe44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	253c2c <uniffi_pbcli_checksum_method_api_base@@Base+0xe73a8>
│ │  	svc	83	@ 0x53
│ │  	b.n	253bb0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe732c>
│ │  	bge.n	25371a <uniffi_pbcli_checksum_method_api_base@@Base+0xe6e96>
│ │  	b.n	253bb4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe7330>
│ │ @@ -434873,18 +434873,18 @@
│ │  	lsrs	r5, r2, #13
│ │  	add.w	r0, r0, r5
│ │  	b.n	254482 <uniffi_pbcli_checksum_method_api_base@@Base+0xe7bfe>
│ │  	beq.n	254164 <uniffi_pbcli_checksum_method_api_base@@Base+0xe78e0>
│ │  	b.n	2545dc <uniffi_pbcli_checksum_method_api_base@@Base+0xe7d58>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r7, sl, ip, sp, lr}
│ │ -	vmull.u32	<illegal reg q8.5>, d2, d3[0]
│ │ +	vmull.u32	<illegal reg q8.5>, d2, d10[1]
│ │  	vsri.64	<illegal reg q11.5>, <illegal reg q14.5>, #28
│ │  	vsri.64	d23, d29, #30
│ │ -			@ <UNDEFINED> instruction: 0xffe21a7f
│ │ +	vmlsl.u32	<illegal reg q8.5>, d18, d22
│ │  	vqshrun.s64	d20, q8, #28
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	254680 <uniffi_pbcli_checksum_method_api_base@@Base+0xe7dfc>
│ │  	ands	r0, r0
│ │  	b.n	2544aa <uniffi_pbcli_checksum_method_api_base@@Base+0xe7c26>
│ │  	movs	r4, r0
│ │  	b.n	253c90 <uniffi_pbcli_checksum_method_api_base@@Base+0xe740c>
│ │ @@ -435990,15 +435990,15 @@
│ │  	vrshr.u64	<illegal reg q11.5>, q5, #30
│ │  			@ <UNDEFINED> instruction: 0xffe26b45
│ │  			@ <UNDEFINED> instruction: 0xffe26b5e
│ │  			@ <UNDEFINED> instruction: 0xffe26d81
│ │  			@ <UNDEFINED> instruction: 0xffe26d9a
│ │  	vmull.u32	q11, d18, d21
│ │  			@ <UNDEFINED> instruction: 0xffe26cbe
│ │ -	vabal.u32	<illegal reg q10.5>, d18, d5
│ │ +	vabal.u32	<illegal reg q10.5>, d18, d28
│ │  			@ <UNDEFINED> instruction: 0xffe46b7d
│ │  			@ <UNDEFINED> instruction: 0xffe26b96
│ │  	vshr.u64	<illegal reg q11.5>, <illegal reg q8.5>, #30
│ │  			@ <UNDEFINED> instruction: 0xffe26b1d
│ │  			@ <UNDEFINED> instruction: 0xffe26b36
│ │  	vqdmulh.s32	q11, q9, d1[0]
│ │  			@ <UNDEFINED> instruction: 0xffe26cda
│ │ @@ -436055,15 +436055,15 @@
│ │  	b.n	2552e2 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8a5e>
│ │  	lsrs	r4, r6, #2
│ │  	b.n	2546ae <uniffi_pbcli_checksum_method_api_base@@Base+0xe7e2a>
│ │  	movs	r1, r0
│ │  	b.n	2552ea <uniffi_pbcli_checksum_method_api_base@@Base+0xe8a66>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r3, r5, r9, fp, sp, lr}
│ │ -	vmul.f32	<illegal reg q9.5>, q1, d15[0]
│ │ +	vqrshrn.u64	d19, q11, #30
│ │  	vqshrun.s64	d20, q8, #28
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2550d8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8854>
│ │  	beq.n	254bd0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe834c>
│ │  	b.n	25505c <uniffi_pbcli_checksum_method_api_base@@Base+0xe87d8>
│ │  	ands	r0, r0
│ │  	b.n	254f06 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8682>
│ │ @@ -436178,15 +436178,15 @@
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r1}
│ │  	b.n	2553fa <uniffi_pbcli_checksum_method_api_base@@Base+0xe8b76>
│ │  	beq.n	254ccc <uniffi_pbcli_checksum_method_api_base@@Base+0xe8448>
│ │  	b.n	255154 <uniffi_pbcli_checksum_method_api_base@@Base+0xe88d0>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r2, r4, r8, fp, sp, lr}
│ │ -	vqrshrun.s64	d19, q7, #30
│ │ +	vmlal.u32	<illegal reg q9.5>, d18, d5
│ │  	vcvt.f16.u16	q10, q8, #28
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2551ec <uniffi_pbcli_checksum_method_api_base@@Base+0xe8968>
│ │  	beq.n	254ce4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8460>
│ │  	b.n	255170 <uniffi_pbcli_checksum_method_api_base@@Base+0xe88ec>
│ │  	str	r1, [r0, r0]
│ │  	b.n	25501a <uniffi_pbcli_checksum_method_api_base@@Base+0xe8796>
│ │ @@ -436286,15 +436286,15 @@
│ │  	lsrs	r4, r7, #32
│ │  	add.w	r0, r0, r0
│ │  	b.n	2554e6 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8c62>
│ │  	beq.n	254dc8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8544>
│ │  	b.n	255240 <uniffi_pbcli_checksum_method_api_base@@Base+0xe89bc>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r2, r3, r4, fp, sp, lr}
│ │ -	vrsra.u32	d25, d26, #30
│ │ +			@ <UNDEFINED> instruction: 0xffe29361
│ │  	vcvt.f16.u16	q10, q8, #28
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2552d8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8a54>
│ │  	beq.n	254dd0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe854c>
│ │  	b.n	25525c <uniffi_pbcli_checksum_method_api_base@@Base+0xe89d8>
│ │  	ands	r0, r0
│ │  	b.n	255106 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8882>
│ │ @@ -436387,15 +436387,15 @@
│ │  	b.n	2555c2 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8d3e>
│ │  	movs	r6, r0
│ │  	b.n	2551c6 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8942>
│ │  	beq.n	254ea8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8624>
│ │  	b.n	255320 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8a9c>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r6, r8, r9, sl, sp, lr}
│ │ -	vsli.32	<illegal reg q14.5>, <illegal reg q11.5>, #2
│ │ +	vsli.64	d29, d14, #34	@ 0x22
│ │  	vcvt.f16.u16	q10, q8, #28
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2553b8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8b34>
│ │  	beq.n	254ec0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe863c>
│ │  	b.n	25533c <uniffi_pbcli_checksum_method_api_base@@Base+0xe8ab8>
│ │  	ands	r0, r0
│ │  	b.n	2551e6 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8962>
│ │ @@ -436502,15 +436502,15 @@
│ │  	b.n	2556c2 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8e3e>
│ │  	movs	r6, r0
│ │  	b.n	2552c6 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8a42>
│ │  	beq.n	254fa8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8724>
│ │  	b.n	255420 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8b9c>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r3, r6, r9, sl, sp, lr}
│ │ -	vmull.u32	q15, d18, d3
│ │ +	vmull.u32	q15, d18, d26
│ │  			@ <UNDEFINED> instruction: 0xffe44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2554b8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8c34>
│ │  	beq.n	254fc8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8744>
│ │  	b.n	25543c <uniffi_pbcli_checksum_method_api_base@@Base+0xe8bb8>
│ │  	ands	r0, r0
│ │  	b.n	2552e6 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8a62>
│ │ @@ -436849,15 +436849,15 @@
│ │  	lsls	r7, r7, #27
│ │  	add.w	r0, r0, r0
│ │  	b.n	2559da <uniffi_pbcli_checksum_method_api_base@@Base+0xe9156>
│ │  	beq.n	2552bc <uniffi_pbcli_checksum_method_api_base@@Base+0xe8a38>
│ │  	b.n	255734 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8eb0>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r3, r5, r8, r9, sp, lr}
│ │ -	vqrdmlah.s32	q12, q1, d5[1]
│ │ +	vmull.p64	q12, d18, d12
│ │  	vcvt.f16.u16	q10, q8, #28
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2557cc <uniffi_pbcli_checksum_method_api_base@@Base+0xe8f48>
│ │  	beq.n	2552c4 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8a40>
│ │  	b.n	255750 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8ecc>
│ │  	ands	r0, r0
│ │  	b.n	2555fa <uniffi_pbcli_checksum_method_api_base@@Base+0xe8d76>
│ │ @@ -436995,15 +436995,15 @@
│ │  	lsls	r0, r6, #26
│ │  	add.w	r0, r0, r0
│ │  	b.n	255b16 <uniffi_pbcli_checksum_method_api_base@@Base+0xe9292>
│ │  	beq.n	2553f8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8b74>
│ │  	b.n	255870 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8fec>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r2, r3, r5, r6, r7, r8, sp, lr}
│ │ -	vmul.i32	q15, q1, d8[0]
│ │ +	vmul.i32	q15, q1, d15[1]
│ │  			@ <UNDEFINED> instruction: 0xffe448f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	255908 <uniffi_pbcli_checksum_method_api_base@@Base+0xe9084>
│ │  	beq.n	255410 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8b8c>
│ │  	b.n	25588c <uniffi_pbcli_checksum_method_api_base@@Base+0xe9008>
│ │  	strb	r1, [r0, #0]
│ │  	b.n	255736 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8eb2>
│ │ @@ -437342,15 +437342,15 @@
│ │  	b.n	255e1a <uniffi_pbcli_checksum_method_api_base@@Base+0xe9596>
│ │  	movs	r6, r0
│ │  	b.n	255a1e <uniffi_pbcli_checksum_method_api_base@@Base+0xe919a>
│ │  	beq.n	255700 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8e7c>
│ │  	b.n	255b78 <uniffi_pbcli_checksum_method_api_base@@Base+0xe92f4>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r4, r5, r6, r7, r9, sl, fp, ip, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffe2fb99
│ │ +			@ <UNDEFINED> instruction: 0xffe2fbc0
│ │  	vcvt.f16.u16	q10, q8, #28
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	255c10 <uniffi_pbcli_checksum_method_api_base@@Base+0xe938c>
│ │  	beq.n	255708 <uniffi_pbcli_checksum_method_api_base@@Base+0xe8e84>
│ │  	b.n	255b94 <uniffi_pbcli_checksum_method_api_base@@Base+0xe9310>
│ │  	str	r1, [r0, r0]
│ │  	b.n	255a3e <uniffi_pbcli_checksum_method_api_base@@Base+0xe91ba>
│ │ @@ -437650,15 +437650,15 @@
│ │  	lsls	r4, r0, #21
│ │  	add.w	r0, r0, r6
│ │  	b.n	255cc6 <uniffi_pbcli_checksum_method_api_base@@Base+0xe9442>
│ │  	beq.n	2559a8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe9124>
│ │  	b.n	255e20 <uniffi_pbcli_checksum_method_api_base@@Base+0xe959c>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r6, sl, fp, ip, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffe26fdf
│ │ +	vaddl.u32	<illegal reg q11.5>, d2, d6
│ │  			@ <UNDEFINED> instruction: 0xffe44bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	255eb8 <uniffi_pbcli_checksum_method_api_base@@Base+0xe9634>
│ │  	beq.n	2559c0 <uniffi_pbcli_checksum_method_api_base@@Base+0xe913c>
│ │  	b.n	255e3c <uniffi_pbcli_checksum_method_api_base@@Base+0xe95b8>
│ │  	ands	r0, r0
│ │  	b.n	255ce6 <uniffi_pbcli_checksum_method_api_base@@Base+0xe9462>
│ │ @@ -438942,15 +438942,15 @@
│ │  	add.w	r0, r0, r6
│ │  	b.n	25683a <uniffi_pbcli_checksum_method_api_base@@Base+0xe9fb6>
│ │  	beq.n	25651c <uniffi_pbcli_checksum_method_api_base@@Base+0xe9c98>
│ │  	b.n	256994 <uniffi_pbcli_checksum_method_api_base@@Base+0xea110>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r2, r5, r6, r7, r8, r9, sl}
│ │  	vmla.i32	<illegal reg q10.5>, <illegal reg q10.5>, d13[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe24cb0
│ │ +			@ <UNDEFINED> instruction: 0xffe24cd7
│ │  			@ <UNDEFINED> instruction: 0xffe448f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	256a30 <uniffi_pbcli_checksum_method_api_base@@Base+0xea1ac>
│ │  	beq.n	256528 <uniffi_pbcli_checksum_method_api_base@@Base+0xe9ca4>
│ │  	b.n	2569b4 <uniffi_pbcli_checksum_method_api_base@@Base+0xea130>
│ │  	str	r1, [r0, #0]
│ │  	b.n	25685e <uniffi_pbcli_checksum_method_api_base@@Base+0xe9fda>
│ │ @@ -439081,15 +439081,15 @@
│ │  	b.n	256d6e <uniffi_pbcli_checksum_method_api_base@@Base+0xea4ea>
│ │  	movs	r7, r0
│ │  	b.n	256972 <uniffi_pbcli_checksum_method_api_base@@Base+0xea0ee>
│ │  	beq.n	256654 <uniffi_pbcli_checksum_method_api_base@@Base+0xe9dd0>
│ │  	b.n	256acc <uniffi_pbcli_checksum_method_api_base@@Base+0xea248>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r2, r3, r4, r7, r8, r9, sl, fp, lr}
│ │ -	vsli.64	d19, d18, #34	@ 0x22
│ │ +	vsli.64	<illegal reg q9.5>, <illegal reg q4.5>, #34	@ 0x22
│ │  	vcvt.f16.u16	q10, q8, #28
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	256b64 <uniffi_pbcli_checksum_method_api_base@@Base+0xea2e0>
│ │  	beq.n	25665c <uniffi_pbcli_checksum_method_api_base@@Base+0xe9dd8>
│ │  	b.n	256ae8 <uniffi_pbcli_checksum_method_api_base@@Base+0xea264>
│ │  	ands	r0, r0
│ │  	b.n	256992 <uniffi_pbcli_checksum_method_api_base@@Base+0xea10e>
│ │ @@ -439184,15 +439184,15 @@
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r1}
│ │  	b.n	256e5a <uniffi_pbcli_checksum_method_api_base@@Base+0xea5d6>
│ │  	beq.n	25673c <uniffi_pbcli_checksum_method_api_base@@Base+0xe9eb8>
│ │  	b.n	256bb4 <uniffi_pbcli_checksum_method_api_base@@Base+0xea330>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r2, r4, r5, r7, r9, sl, fp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffe20902
│ │ +			@ <UNDEFINED> instruction: 0xffe20929
│ │  	vcvt.f16.u16	q10, q8, #28
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	256c4c <uniffi_pbcli_checksum_method_api_base@@Base+0xea3c8>
│ │  	beq.n	256744 <uniffi_pbcli_checksum_method_api_base@@Base+0xe9ec0>
│ │  	b.n	256bd0 <uniffi_pbcli_checksum_method_api_base@@Base+0xea34c>
│ │  	ands	r0, r0
│ │  	b.n	256a7a <uniffi_pbcli_checksum_method_api_base@@Base+0xea1f6>
│ │ @@ -439361,17 +439361,17 @@
│ │  	b.n	256426 <uniffi_pbcli_checksum_method_api_base@@Base+0xe9ba2>
│ │  	movs	r6, r0
│ │  	b.n	256be2 <uniffi_pbcli_checksum_method_api_base@@Base+0xea35e>
│ │  	beq.n	2568c4 <uniffi_pbcli_checksum_method_api_base@@Base+0xea040>
│ │  	b.n	256d3c <uniffi_pbcli_checksum_method_api_base@@Base+0xea4b8>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r2, r5, r9, sl, fp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffe21d8d
│ │ +			@ <UNDEFINED> instruction: 0xffe21db4
│ │  	vqrdmulh.s32	q10, q2, d9[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe21cb1
│ │ +			@ <UNDEFINED> instruction: 0xffe21cd8
│ │  			@ <UNDEFINED> instruction: 0xffe44bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	256ddc <uniffi_pbcli_checksum_method_api_base@@Base+0xea558>
│ │  	str	r0, [sp, #0]
│ │  	b.n	256c06 <uniffi_pbcli_checksum_method_api_base@@Base+0xea382>
│ │  	lsrs	r0, r7, #26
│ │  	b.n	2563ea <uniffi_pbcli_checksum_method_api_base@@Base+0xe9b66>
│ │ @@ -439495,17 +439495,17 @@
│ │  	b.n	256560 <uniffi_pbcli_checksum_method_api_base@@Base+0xe9cdc>
│ │  	lsrs	r5, r0, #2
│ │  	b.n	256564 <uniffi_pbcli_checksum_method_api_base@@Base+0xe9ce0>
│ │  	movs	r1, r0
│ │  	b.n	257116 <uniffi_pbcli_checksum_method_api_base@@Base+0xea892>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r0, r2, r3, r4, r5, sl, fp, lr}
│ │ -	vqshl.u64	d23, d11, #34	@ 0x22
│ │ +			@ <UNDEFINED> instruction: 0xffe277c2
│ │  			@ <UNDEFINED> instruction: 0xffe44be5
│ │ -			@ <UNDEFINED> instruction: 0xffe27743
│ │ +			@ <UNDEFINED> instruction: 0xffe2776a
│ │  	vcvt.f16.u16	q10, q8, #28
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	256f0c <uniffi_pbcli_checksum_method_api_base@@Base+0xea688>
│ │  	beq.n	256a04 <uniffi_pbcli_checksum_method_api_base@@Base+0xea180>
│ │  	b.n	256e90 <uniffi_pbcli_checksum_method_api_base@@Base+0xea60c>
│ │  	ands	r0, r0
│ │  	b.n	256d3a <uniffi_pbcli_checksum_method_api_base@@Base+0xea4b6>
│ │ @@ -441806,58 +441806,58 @@
│ │  	b.n	2584ce <uniffi_pbcli_checksum_method_api_base@@Base+0xebc4a>
│ │  	cmp	r4, #1
│ │  	b.n	2584d2 <uniffi_pbcli_checksum_method_api_base@@Base+0xebc4e>
│ │  	adds	r0, #0
│ │  	b.n	2584d6 <uniffi_pbcli_checksum_method_api_base@@Base+0xebc52>
│ │  	ldc2	11, cr14, [lr], #-1020	@ 0xfffffc04	@ <UNPREDICTABLE>
│ │  			@ <UNDEFINED> instruction: 0xffcbeaff
│ │ -	ldr	r7, [r1, #104]	@ 0x68
│ │ +	ldr	r6, [r6, #104]	@ 0x68
│ │  	vcvt.f32.u32	d21, d8, #28
│ │ -	vqrdmlah.s32	q11, q9, d3[0]
│ │ +	vqrdmlah.s32	q11, q9, d10[1]
│ │  	vqrdmlah.s32	<illegal reg q10.5>, q2, d12[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe2674b
│ │ +	vqshl.u32	q11, q9, #2
│ │  	vqshlu.s64	<illegal reg q10.5>, q2, #36	@ 0x24
│ │ -	vqshlu.s64	d22, d31, #34	@ 0x22
│ │ +	vmlsl.u32	q11, d18, d6[1]
│ │  	vmlsl.u32	<illegal reg q10.5>, d4, d8[0]
│ │ -	vmlsl.u32	q11, d2, d7[1]
│ │ +	vrsubhn.i64	d22, q9, q7
│ │  	vsli.64	<illegal reg q10.5>, q8, #36	@ 0x24
│ │ -	vqshlu.s64	q11, <illegal reg q5.5>, #34	@ 0x22
│ │ +	vabdl.u32	q11, d2, d2
│ │  	vmlsl.u32	<illegal reg q10.5>, d4, d4[1]
│ │  			@ <UNDEFINED> instruction: 0xffe25f04
│ │  	movs	r0, r5
│ │  	ldrsh	r0, [r0, r4]
│ │  	movs	r0, r5
│ │  	ldrsh	r4, [r7, r3]
│ │  	movs	r0, r5
│ │  	ldrsh	r0, [r7, r3]
│ │  	movs	r0, r5
│ │  	ldrsh	r4, [r6, r3]
│ │  	movs	r0, r5
│ │ -	str	r3, [r4, #56]	@ 0x38
│ │ +	str	r2, [r1, #60]	@ 0x3c
│ │  	vsubw.u32	<illegal reg q10.5>, q2, d28
│ │ -	vsri.32	d22, d31, #30
│ │ +	vmls.i32	q11, q1, d6[1]
│ │  			@ <UNDEFINED> instruction: 0xffe453c8
│ │  	vcvt.f32.u32	d21, d24, #30
│ │  	movs	r0, r5
│ │  	ldrsh	r4, [r6, r0]
│ │  	movs	r0, r5
│ │  	ldrsh	r4, [r5, r0]
│ │  	movs	r0, r5
│ │  	ldrsh	r0, [r5, r0]
│ │  	movs	r0, r5
│ │ -	str	r3, [r5, #92]	@ 0x5c
│ │ -	vmls.i32	<illegal reg q15.5>, q10, d13[0]
│ │ -	vrsubhn.i64	d22, <illegal reg q9.5>, <illegal reg q7.5>
│ │ -	vsli.32	<illegal reg q15.5>, <illegal reg q8.5>, #4
│ │ -	vabal.u32	q11, d19, d23
│ │ -	vraddhn.i64	d31, q10, <illegal reg q4.5>
│ │ -	vsli.32	q11, <illegal reg q1.5>, #3
│ │ -	vsri.32	d31, d21, #28
│ │ -	vrsubhn.i64	d22, <illegal reg q1.5>, <illegal reg q13.5>
│ │ -	vabal.u32	<illegal reg q15.5>, d4, d13
│ │ +	str	r2, [r2, #96]	@ 0x60
│ │ +	vsri.64	<illegal reg q15.5>, q10, #28
│ │ +	vqshlu.s64	d22, d22, #35	@ 0x23
│ │ +	vsli.64	d31, d8, #36	@ 0x24
│ │ +	vmls.f32	q11, <illegal reg q9.5>, d14[0]
│ │ +	vsri.64	d31, d16, #28
│ │ +	vsli.32	q11, q13, #3
│ │ +	vsri.32	<illegal reg q15.5>, q6, #28
│ │ +	vqshlu.s32	q11, q1, #3
│ │ +	vsli.32	d31, d20, #4
│ │  			@ <UNDEFINED> instruction: 0xffe35924
│ │  	movs	r0, r5
│ │  	ldr	r0, [r4, r4]
│ │  	movs	r0, r5
│ │  	ldr	r4, [r3, r4]
│ │  	movs	r0, r5
│ │  	ldr	r4, [r3, r4]
│ │ @@ -441872,28 +441872,28 @@
│ │  	movs	r0, r5
│ │  	ldrsh	r0, [r7, r2]
│ │  	movs	r0, r5
│ │  	ldrsh	r0, [r6, r2]
│ │  	movs	r0, r5
│ │  	ldrsh	r4, [r5, r2]
│ │  	movs	r0, r5
│ │ -	str	r3, [r1, #76]	@ 0x4c
│ │ -	vcvt.u32.f32	<illegal reg q8.5>, q14, #28
│ │ +	str	r2, [r6, #76]	@ 0x4c
│ │ +			@ <UNDEFINED> instruction: 0xffe41fa3
│ │  			@ <UNDEFINED> instruction: 0xffe458d0
│ │  	movs	r0, r5
│ │  	ldr	r4, [r1, r3]
│ │  	movs	r0, r5
│ │  	ldr	r0, [r1, r3]
│ │  	movs	r0, r5
│ │  	ldr	r4, [r0, r3]
│ │  	movs	r0, r5
│ │  	ldr	r0, [r0, r3]
│ │  	movs	r0, r5
│ │ -	str	r7, [r7, #60]	@ 0x3c
│ │ -	vmlal.u32	<illegal reg q15.5>, d20, d1[1]
│ │ +	str	r6, [r4, #64]	@ 0x40
│ │ +	vsubw.u32	<illegal reg q15.5>, q2, d8
│ │  	vaddl.u32	q8, d3, d0
│ │  	b.n	25851e <uniffi_pbcli_checksum_method_api_base@@Base+0xebc9a>
│ │  	movs	r3, r1
│ │  	lsrs	r0, r0, #8
│ │  	asrs	r0, r0, #32
│ │  	b.n	2579a6 <uniffi_pbcli_checksum_method_api_base@@Base+0xeb122>
│ │  	movs	r1, r0
│ │ @@ -443287,15 +443287,15 @@
│ │  	b.n	258b44 <uniffi_pbcli_checksum_method_api_base@@Base+0xec2c0>
│ │  			@ <UNDEFINED> instruction: 0xff9aeaff
│ │  	stc2	15, cr15, [r9], {225}	@ 0xe1
│ │  	ldrsh	r7, [r7, r2]
│ │  			@ <UNDEFINED> instruction: 0xffe3fa79
│ │  			@ <UNDEFINED> instruction: 0xffe15d2f
│ │  	vqrdmulh.s32	<illegal reg q15.5>, <illegal reg q1.5>, d5[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe159db
│ │ +	vmlsl.u32	<illegal reg q10.5>, d1, d2
│ │  	vcvt.f16.u16	d20, d0, #28
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	258f64 <uniffi_pbcli_checksum_method_api_base@@Base+0xec6e0>
│ │  	beq.n	258abc <uniffi_pbcli_checksum_method_api_base@@Base+0xec238>
│ │  	b.n	258ee8 <uniffi_pbcli_checksum_method_api_base@@Base+0xec664>
│ │  	movs	r0, #108	@ 0x6c
│ │  	b.n	258572 <uniffi_pbcli_checksum_method_api_base@@Base+0xebcee>
│ │ @@ -443898,15 +443898,15 @@
│ │  	b.n	258a56 <uniffi_pbcli_checksum_method_api_base@@Base+0xec1d2>
│ │  	strb	r0, [r7, #9]
│ │  	b.n	258a5a <uniffi_pbcli_checksum_method_api_base@@Base+0xec1d6>
│ │  	movs	r7, r0
│ │  	b.n	259296 <uniffi_pbcli_checksum_method_api_base@@Base+0xeca12>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r2, r3, r4, r7, r8, sl, ip, sp, lr, pc}
│ │ -	vsri.64	<illegal reg q12.5>, <illegal reg q12.5>, #31
│ │ +	vabal.u32	<illegal reg q12.5>, d1, d16
│ │  	vsli.32	<illegal reg q15.5>, <illegal reg q4.5>, #4
│ │  	vqshrun.s64	d20, q8, #31
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	259488 <uniffi_pbcli_checksum_method_api_base@@Base+0xecc04>
│ │  	str	r0, [r0, r0]
│ │  	b.n	2592b2 <uniffi_pbcli_checksum_method_api_base@@Base+0xeca2e>
│ │  	lsls	r4, r5, #1
│ │ @@ -444665,33 +444665,33 @@
│ │  	b.n	259118 <uniffi_pbcli_checksum_method_api_base@@Base+0xec894>
│ │  	movs	r0, r0
│ │  	b.n	2596fc <uniffi_pbcli_checksum_method_api_base@@Base+0xece78>
│ │  	movs	r0, #2
│ │  	b.n	259700 <uniffi_pbcli_checksum_method_api_base@@Base+0xece7c>
│ │  	vpmin.u<illegal width 64>	q15, q8, <illegal reg q15.5>
│ │  	bl	5235aa <uniffi_pbcli_checksum_method_api_base@@Base+0x3b6d26>
│ │ -	ldmia	r1, {r0, r1, r2, r3, r5, r7}
│ │ +	ldmia	r1, {r1, r2, r4, r6, r7}
│ │  	vsra.u32	d31, d1, #29
│ │ -	vqshl.u64	q14, <illegal reg q11.5>, #33	@ 0x21
│ │ +	vqshrun.s64	d28, q7, #31
│ │  	vshr.u64	<illegal reg q15.5>, <illegal reg q10.5>, #29
│ │ -	vqshl.u64	q14, <illegal reg q5.5>, #33	@ 0x21
│ │ +	vmlal.u32	q14, d1, d2
│ │  	vaddw.u32	<illegal reg q15.5>, <illegal reg q1.5>, d29
│ │ -	vqshrun.s64	d28, <illegal reg q1.5>, #31
│ │ +	vqshrun.s64	d28, q13, #31
│ │  	vcvt.u32.f32	q15, <illegal reg q12.5>, #29
│ │ -	vqshlu.s32	q14, <illegal reg q7.5>, #1
│ │ +	vrsubhn.i64	d28, <illegal reg q8.5>, q3
│ │  	vcvt.u32.f32	d30, d21, #29
│ │ -	vqshlu.s32	d28, d11, #1
│ │ +	vmlsl.u32	q14, d1, d2[0]
│ │  	vcvt.u32.f32	d30, d9, #29
│ │ -	vsli.64	q14, <illegal reg q15.5>, #33	@ 0x21
│ │ +	vrsubhn.i64	d28, <illegal reg q0.5>, q11
│ │  			@ <UNDEFINED> instruction: 0xffe3eef5
│ │ -	vsli.64	q14, <illegal reg q5.5>, #33	@ 0x21
│ │ +	vrsubhn.i64	d28, <illegal reg q0.5>, q1
│ │  			@ <UNDEFINED> instruction: 0xffe3eed9
│ │ -	vsli.64	d28, d31, #33	@ 0x21
│ │ +	vmls.f32	q14, <illegal reg q8.5>, d6[1]
│ │  			@ <UNDEFINED> instruction: 0xffe3eebd
│ │ -	vabal.u32	q14, d17, d19
│ │ +	vmls.f32	q14, <illegal reg q8.5>, d10[0]
│ │  	vqshrun.s64	d20, q8, #29
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	259b58 <uniffi_pbcli_checksum_method_api_base@@Base+0xed2d4>
│ │  	ands	r0, r0
│ │  	b.n	259982 <uniffi_pbcli_checksum_method_api_base@@Base+0xed0fe>
│ │  	lsls	r4, r3, #2
│ │  	b.n	259166 <uniffi_pbcli_checksum_method_api_base@@Base+0xec8e2>
│ │ @@ -446595,36 +446595,36 @@
│ │  			@ <UNDEFINED> instruction: 0xffe17ab7
│ │  			@ <UNDEFINED> instruction: 0xffe3e901
│ │  	vmul.i32	q15, <illegal reg q8.5>, d1[1]
│ │  	vrsra.u64	d30, d9, #31
│ │  	vsri.64	<illegal reg q11.5>, <illegal reg q5.5>, #31
│ │  	vmlal.u32	q15, d19, d13
│ │  	vsri.64	d30, d13, #31
│ │ -	vmla.f32	q10, <illegal reg q0.5>, d14[1]
│ │ +	vsra.u64	d20, d5, #31
│ │  	vsli.64	d30, d25, #36	@ 0x24
│ │ -	vsubl.u32	q10, d17, d10
│ │ +	vrshr.u64	d20, d17, #31
│ │  	vsli.64	d23, d17, #36	@ 0x24
│ │  	vsri.64	q15, <illegal reg q12.5>, #29
│ │ -	vmla.f32	q10, <illegal reg q8.5>, d10[0]
│ │ +	vsra.u64	q10, <illegal reg q8.5>, #31
│ │  	vmlal.u32	q15, d4, d13
│ │  	vmls.i32	q15, <illegal reg q8.5>, d1[0]
│ │ -	vsra.u64	d20, d2, #31
│ │ +	vsra.u64	d20, d25, #31
│ │  	vmla.i32	q15, q10, d1[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe13db2
│ │ +			@ <UNDEFINED> instruction: 0xffe13dd9
│ │  	vshr.u64	d30, d17, #28
│ │  	vsri.64	q15, <illegal reg q6.5>, #31
│ │ -	vmull.u32	<illegal reg q15.5>, d1, d24
│ │ +	vqdmulh.s32	<illegal reg q15.5>, <illegal reg q0.5>, d15[0]
│ │  	vraddhn.i64	d30, <illegal reg q9.5>, <illegal reg q0.5>
│ │ -			@ <UNDEFINED> instruction: 0xffe1fbcc
│ │ +			@ <UNDEFINED> instruction: 0xffe1fbf3
│ │  	vsra.u32	q15, <illegal reg q8.5>, #29
│ │ -			@ <UNDEFINED> instruction: 0xffe1f8bc
│ │ +	vmul.i32	<illegal reg q15.5>, <illegal reg q8.5>, d3[1]
│ │  	vaddl.u32	q15, d3, d21
│ │ -	vqshl.u32	<illegal reg q15.5>, q8, #1
│ │ +	vqshl.u64	d31, d7, #33	@ 0x21
│ │  	vmla.i32	q15, <illegal reg q1.5>, d13[1]
│ │ -	vqshl.u64	d31, d24, #33	@ 0x21
│ │ +	vqshl.u64	<illegal reg q15.5>, <illegal reg q7.5>, #33	@ 0x21
│ │  	vmls.f32	q15, <illegal reg q9.5>, d1[1]
│ │  	vrsra.u64	q15, <illegal reg q0.5>, #31
│ │  			@ <UNDEFINED> instruction: 0xffe1e3e6
│ │  	vsra.u32	d30, d25, #31
│ │  	vmla.f32	q15, <illegal reg q0.5>, d14[0]
│ │  			@ <UNDEFINED> instruction: 0xffe1dfdd
│ │  			@ <UNDEFINED> instruction: 0xffe1dff2
│ │ @@ -446723,15 +446723,15 @@
│ │  	bfcsel	6, 25a04a <uniffi_pbcli_checksum_method_api_base@@Base+0xed7c6>, 8, mi
│ │  	movs	r4, r0
│ │  	b.n	25ab92 <uniffi_pbcli_checksum_method_api_base@@Base+0xee30e>
│ │  	beq.n	25a874 <uniffi_pbcli_checksum_method_api_base@@Base+0xedff0>
│ │  	b.n	25acec <uniffi_pbcli_checksum_method_api_base@@Base+0xee468>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r2, r3, r5, r6, sl, fp, ip, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffe193ee
│ │ +	vsri.32	d25, d5, #31
│ │  	vaddl.u32	<illegal reg q8.5>, d4, d0
│ │  	b.n	25aba6 <uniffi_pbcli_checksum_method_api_base@@Base+0xee322>
│ │  	lsls	r4, r5, #1
│ │  	b.n	25a38a <uniffi_pbcli_checksum_method_api_base@@Base+0xedb06>
│ │  	movs	r0, #2
│ │  	b.n	25acee <uniffi_pbcli_checksum_method_api_base@@Base+0xee46a>
│ │  	movs	r0, r0
│ │ @@ -450593,28 +450593,28 @@
│ │  	ldmia	r0, {r0, r4}
│ │  	vsra.u32	d23, d18, #31
│ │  	vabdl.u32	q14, d19, d29
│ │  	vmla.i32	<illegal reg q11.5>, <illegal reg q8.5>, d14[0]
│ │  	vqshlu.s64	q14, <illegal reg q10.5>, #35	@ 0x23
│ │  	vraddhn.i64	d28, <illegal reg q8.5>, <illegal reg q12.5>
│ │  	vqshlu.s32	<illegal reg q13.5>, <illegal reg q15.5>, #1
│ │ -			@ <UNDEFINED> instruction: 0xffe2dcb1
│ │ +			@ <UNDEFINED> instruction: 0xffe2dcd8
│ │  	vabdl.u32	q14, d3, d21
│ │  	vmla.i32	<illegal reg q11.5>, <illegal reg q0.5>, d6[0]
│ │  			@ <UNDEFINED> instruction: 0xffe3bfd5
│ │  	vaddw.u32	<illegal reg q13.5>, <illegal reg q8.5>, d27
│ │  	vqrdmlah.s32	<illegal reg q13.5>, q1, d5[0]
│ │ -	vsubw.u32	q8, <illegal reg q0.5>, d13
│ │ +	vrsra.u32	d16, d20, #31
│ │  	vsli.64	d28, d29, #36	@ 0x24
│ │  	vaddl.u32	q13, d1, d20
│ │  	vmlal.u32	q14, d18, d1[0]
│ │  			@ <UNDEFINED> instruction: 0xffe19d28
│ │  			@ <UNDEFINED> instruction: 0xffe27f90
│ │ -			@ <UNDEFINED> instruction: 0xffe31b48
│ │ -	vqshl.u64	<illegal reg q12.5>, q11, #36	@ 0x24
│ │ +			@ <UNDEFINED> instruction: 0xffe31b6f
│ │ +	vqshrun.s64	d25, <illegal reg q6.5>, #28
│ │  			@ <UNDEFINED> instruction: 0xffe3bfa9
│ │  	vshll.u32	<illegal reg q12.5>, d0, #1
│ │  	vabdl.u32	q8, d18, d2
│ │  	vqdmulh.s32	<illegal reg q13.5>, q9, d5[1]
│ │  			@ <UNDEFINED> instruction: 0xffe1974c
│ │  			@ <UNDEFINED> instruction: 0xffe2bd0d
│ │  	vqshl.u32	<illegal reg q12.5>, q10, #1
│ │ @@ -450629,36 +450629,36 @@
│ │  	vrshr.u32	q14, <illegal reg q10.5>, #30
│ │  	vsli.32	d24, d5, #1
│ │  	vrsra.u32	q14, <illegal reg q12.5>, #30
│ │  	vqshlu.s32	d24, d9, #1
│ │  	vcvt.u32.f32	d27, d1, #30
│ │  	vsra.u64	d24, d17, #31
│ │  	vraddhn.i64	d28, q1, <illegal reg q8.5>
│ │ -	vmul.i32	q8, <illegal reg q8.5>, d9[1]
│ │ +	vqshrn.u64	d16, q0, #31
│ │  	vmull.p64	<illegal reg q13.5>, d4, d9
│ │ -	vrshr.u64	q8, <illegal reg q0.5>, #31
│ │ +	vrshr.u64	q8, q12, #31
│ │  	vcvt.f32.u32	<illegal reg q13.5>, <illegal reg q10.5>, #28
│ │ -	vrsra.u32	d16, d29, #31
│ │ +			@ <UNDEFINED> instruction: 0xffe10364
│ │  	vcvt.u16.f16	d27, d29, #28
│ │ -	vsubl.u32	q8, d1, d5
│ │ +	vsubl.u32	q8, d1, d28
│ │  	vqrdmulh.s32	<illegal reg q13.5>, q2, d1[1]
│ │ -	vsubl.u32	q8, d1, d25
│ │ +	vrshr.u32	q8, q0, #31
│ │  			@ <UNDEFINED> instruction: 0xffe4bb5d
│ │ -	vaddl.u32	q8, d1, d21
│ │ +	vmla.i32	q8, <illegal reg q0.5>, d12[0]
│ │  			@ <UNDEFINED> instruction: 0xffe4bb35
│ │ -			@ <UNDEFINED> instruction: 0xffe1fffd
│ │ -			@ <UNDEFINED> instruction: 0xffe3bb19
│ │ -	vqrdmlsh.s32	<illegal reg q15.5>, <illegal reg q8.5>, d1[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe3bbd5
│ │ +	vaddl.u32	q8, d1, d20
│ │ +			@ <UNDEFINED> instruction: 0xffe4bb19
│ │ +	vaddl.u32	q8, d1, d8
│ │ +			@ <UNDEFINED> instruction: 0xffe4bbd5
│ │  			@ <UNDEFINED> instruction: 0xffe1baf1
│ │ -			@ <UNDEFINED> instruction: 0xffe1ffb9
│ │ +	vqrdmlsh.s32	<illegal reg q15.5>, <illegal reg q8.5>, d0[1]
│ │  	vabal.u32	q14, d19, d13
│ │ -			@ <UNDEFINED> instruction: 0xffe10a55
│ │ +			@ <UNDEFINED> instruction: 0xffe10a7c
│ │  	vqshlu.s64	d28, d13, #36	@ 0x24
│ │ -			@ <UNDEFINED> instruction: 0xffe10b65
│ │ +			@ <UNDEFINED> instruction: 0xffe10b8c
│ │  			@ <UNDEFINED> instruction: 0xffe448f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	25d028 <uniffi_pbcli_checksum_method_api_base@@Base+0xf07a4>
│ │  	beq.n	25cb40 <uniffi_pbcli_checksum_method_api_base@@Base+0xf02bc>
│ │  	b.n	25cfac <uniffi_pbcli_checksum_method_api_base@@Base+0xf0728>
│ │  	ands	r0, r0
│ │  	b.n	25ce56 <uniffi_pbcli_checksum_method_api_base@@Base+0xf05d2>
│ │ @@ -451245,26 +451245,26 @@
│ │  	b.n	25cb40 <uniffi_pbcli_checksum_method_api_base@@Base+0xf02bc>
│ │  	asrs	r1, r0, #32
│ │  	b.n	25d128 <uniffi_pbcli_checksum_method_api_base@@Base+0xf08a4>
│ │  			@ <UNDEFINED> instruction: 0xffafeb02
│ │  	vpmin.u8	q15, q10, <illegal reg q15.5>
│ │  	cbnz	r1, 25d026 <uniffi_pbcli_checksum_method_api_base@@Base+0xf07a2>
│ │  	vmul.i32	<illegal reg q13.5>, <illegal reg q8.5>, d5[1]
│ │ -	vcvt.f16.u16	d28, d13, #31
│ │ -			@ <UNDEFINED> instruction: 0xffe3cbe9
│ │ +	vqdmulh.s32	q14, <illegal reg q0.5>, d4[0]
│ │ +	vcvt.f16.u16	d28, d0, #29
│ │  	vqshlu.s32	<illegal reg q13.5>, <illegal reg q2.5>, #3
│ │  	vcvt.u32.f32	d21, d24, #31
│ │  	vsri.64	d27, d1, #29
│ │  	vmls.i32	<illegal reg q13.5>, <illegal reg q8.5>, d1[1]
│ │  	vsri.64	d27, d25, #31
│ │  			@ <UNDEFINED> instruction: 0xffe15d9c
│ │  	vmul.i32	<illegal reg q13.5>, <illegal reg q1.5>, d13[0]
│ │  	vsra.u32	d22, d16, #31
│ │ -	vcvt.u16.f16	q14, <illegal reg q2.5>, #29
│ │ -			@ <UNDEFINED> instruction: 0xffe3cd21
│ │ +	vcvt.u16.f16	q14, q14, #29
│ │ +	vqrdmulh.s32	q14, <illegal reg q1.5>, d8[0]
│ │  	vabdl.u32	<illegal reg q13.5>, d3, d29
│ │  	vshr.u32	d22, d0, #31
│ │  	vqshl.u32	d27, d1, #3
│ │  			@ <UNDEFINED> instruction: 0xffe15ff4
│ │  	vmls.f32	<illegal reg q13.5>, <illegal reg q1.5>, d13[1]
│ │  	vcvt.f32.u32	<illegal reg q10.5>, q0, #31
│ │  	vsli.64	d27, d13, #35	@ 0x23
│ │ @@ -452221,15 +452221,15 @@
│ │  	adds	r0, #0
│ │  	b.n	25dffa <uniffi_pbcli_checksum_method_api_base@@Base+0xf1776>
│ │  	b.n	25d3a6 <uniffi_pbcli_checksum_method_api_base@@Base+0xf0b22>
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	25e002 <uniffi_pbcli_checksum_method_api_base@@Base+0xf177e>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, fp, sp, pc}
│ │ -	vqshl.u32	<illegal reg q12.5>, q12, #1
│ │ +	vqshl.u64	d25, d15, #33	@ 0x21
│ │  			@ <UNDEFINED> instruction: 0xffe348f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	25ddf0 <uniffi_pbcli_checksum_method_api_base@@Base+0xf156c>
│ │  	beq.n	25d8e8 <uniffi_pbcli_checksum_method_api_base@@Base+0xf1064>
│ │  	b.n	25dd74 <uniffi_pbcli_checksum_method_api_base@@Base+0xf14f0>
│ │  	ands	r0, r0
│ │  	b.n	25dc1e <uniffi_pbcli_checksum_method_api_base@@Base+0xf139a>
│ │ @@ -452664,19 +452664,19 @@
│ │  	b.n	25dfc6 <uniffi_pbcli_checksum_method_api_base@@Base+0xf1742>
│ │  	asrs	r7, r5, #32
│ │  	b.n	25e3ca <uniffi_pbcli_checksum_method_api_base@@Base+0xf1b46>
│ │  	movs	r1, #127	@ 0x7f
│ │  	b.n	25e28e <uniffi_pbcli_checksum_method_api_base@@Base+0xf1a0a>
│ │  			@ <UNDEFINED> instruction: 0xffe7eaff
│ │  	add	r2, sp, #276	@ 0x114
│ │ -	vmul.f32	q10, <illegal reg q8.5>, d3[0]
│ │ +	vmul.f32	q10, <illegal reg q8.5>, d10[1]
│ │  	vmul.f32	q13, q2, d13[1]
│ │ -	vmul.i32	q10, <illegal reg q8.5>, d11[1]
│ │ +	vqshrn.u64	d20, q1, #31
│ │  	vmlal.u32	q13, d20, d1
│ │ -	vqshl.u64	q10, <illegal reg q15.5>, #33	@ 0x21
│ │ +	vmlal.u32	q10, d1, d22
│ │  	vsli.64	d31, d0, #36	@ 0x24
│ │  	movs	r7, r4
│ │  	add	r1, sp, #612	@ 0x264
│ │  	vmull.u32	q8, d1, d27
│ │  	vmlsl.u32	q13, d3, d9
│ │  			@ <UNDEFINED> instruction: 0xffe10c9b
│ │  	vmul.i32	q13, <illegal reg q1.5>, d1[0]
│ │ @@ -454036,15 +454036,15 @@
│ │  	b.n	25eb96 <uniffi_pbcli_checksum_method_api_base@@Base+0xf2312>
│ │  			@ <UNDEFINED> instruction: 0xebff0005
│ │  	b.n	25ebe2 <uniffi_pbcli_checksum_method_api_base@@Base+0xf235e>
│ │  	beq.n	25e8b4 <uniffi_pbcli_checksum_method_api_base@@Base+0xf2030>
│ │  	b.n	25ed3c <uniffi_pbcli_checksum_method_api_base@@Base+0xf24b8>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r2, r3, r4, sl, fp, ip, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffe1f8d7
│ │ +			@ <UNDEFINED> instruction: 0xffe1f8fe
│ │  			@ <UNDEFINED> instruction: 0xffe348f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	25edd4 <uniffi_pbcli_checksum_method_api_base@@Base+0xf2550>
│ │  	beq.n	25e8cc <uniffi_pbcli_checksum_method_api_base@@Base+0xf2048>
│ │  	b.n	25ed58 <uniffi_pbcli_checksum_method_api_base@@Base+0xf24d4>
│ │  	ands	r0, r0
│ │  	b.n	25ec02 <uniffi_pbcli_checksum_method_api_base@@Base+0xf237e>
│ │ @@ -454392,22 +454392,22 @@
│ │  	b.n	25f302 <uniffi_pbcli_checksum_method_api_base@@Base+0xf2a7e>
│ │  	asrs	r6, r0, #32
│ │  	b.n	25ecce <uniffi_pbcli_checksum_method_api_base@@Base+0xf244a>
│ │  	asrs	r0, r0, #32
│ │  	b.n	25e6d4 <uniffi_pbcli_checksum_method_api_base@@Base+0xf1e50>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r2, r7, r8, fp, ip, pc}
│ │ -	vshll.u32	<illegal reg q12.5>, d5, #1
│ │ +	vshll.u32	<illegal reg q12.5>, d28, #1
│ │  	vqrshrn.u64	d25, <illegal reg q2.5>, #29
│ │ -	vmul.f32	<illegal reg q12.5>, <illegal reg q8.5>, d5[1]
│ │ +	vmlsl.u32	<illegal reg q12.5>, d1, d12
│ │  			@ <UNDEFINED> instruction: 0xffe399d5
│ │  	vqshrn.u64	d25, <illegal reg q0.5>, #31
│ │ -			@ <UNDEFINED> instruction: 0xffe199a1
│ │ +	vmul.f32	<illegal reg q12.5>, <illegal reg q8.5>, d8[0]
│ │  			@ <UNDEFINED> instruction: 0xffe399a1
│ │ -	vshll.u32	<illegal reg q12.5>, d17, #1
│ │ +			@ <UNDEFINED> instruction: 0xffe19a58
│ │  	vcvt.f16.u16	q10, q8, #29
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	25f114 <uniffi_pbcli_checksum_method_api_base@@Base+0xf2890>
│ │  	ands	r0, r0
│ │  	b.n	25ef3e <uniffi_pbcli_checksum_method_api_base@@Base+0xf26ba>
│ │  	str	r4, [r0, #0]
│ │  	b.n	25e722 <uniffi_pbcli_checksum_method_api_base@@Base+0xf1e9e>
│ │ @@ -455107,37 +455107,37 @@
│ │  	adds	r0, #0
│ │  	b.n	25f95a <uniffi_pbcli_checksum_method_api_base@@Base+0xf30d6>
│ │  	svc	29
│ │  			@ <UNDEFINED> instruction: 0xebff7020
│ │  	b.n	25f962 <uniffi_pbcli_checksum_method_api_base@@Base+0xf30de>
│ │  			@ <UNDEFINED> instruction: 0xffc0eaff
│ │  	str	r4, [sp, #948]	@ 0x3b4
│ │ -	vrshr.u64	d22, d21, #31
│ │ +	vrshr.u64	q11, q6, #31
│ │  	vsri.64	d25, d21, #28
│ │ -	vrshr.u32	q11, <illegal reg q14.5>, #31
│ │ +	vsubl.u32	q11, d17, d20
│ │  	vqshlu.s32	d25, d25, #4
│ │  	vsri.32	<illegal reg q12.5>, <illegal reg q8.5>, #31
│ │ -	vrshr.u32	d22, d25, #31
│ │ +	vmlal.u32	q11, d1, d0[1]
│ │  	vraddhn.i64	d25, q2, <illegal reg q14.5>
│ │ -	vsra.u64	q11, <illegal reg q10.5>, #31
│ │ +	vrshr.u32	d22, d12, #31
│ │  	vrsra.u64	<illegal reg q12.5>, <illegal reg q10.5>, #28
│ │ -	vsra.u64	d22, d29, #31
│ │ +	vmla.f32	q11, <illegal reg q8.5>, d4[1]
│ │  			@ <UNDEFINED> instruction: 0xffe493c5
│ │ -	vaddw.u32	q11, <illegal reg q8.5>, d13
│ │ +	vsra.u64	d22, d20, #31
│ │  	vrsra.u64	d25, d9, #28
│ │ -	vmla.f32	q11, <illegal reg q0.5>, d1[1]
│ │ +	vaddw.u32	q11, <illegal reg q8.5>, d8
│ │  	vsubw.u32	<illegal reg q12.5>, q2, d29
│ │ -	vshr.u64	q11, <illegal reg q10.5>, #31
│ │ +	vsra.u32	d22, d12, #31
│ │  	vsubw.u32	<illegal reg q12.5>, q2, d1
│ │ -	vmla.i32	q11, <illegal reg q8.5>, d9[0]
│ │ +	vshr.u64	q11, q8, #31
│ │  	vrshr.u64	<illegal reg q12.5>, <illegal reg q2.5>, #28
│ │ -	vshr.u64	d22, d13, #31
│ │ +	vmla.i32	q11, <illegal reg q8.5>, d4[0]
│ │  	vrsra.u32	<illegal reg q12.5>, <illegal reg q2.5>, #28
│ │  	vrshr.u64	d25, d13, #31
│ │ -	vmla.i32	q11, <illegal reg q0.5>, d5[1]
│ │ +	vaddl.u32	q11, d17, d12
│ │  			@ <UNDEFINED> instruction: 0xffe448f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	25f7a8 <uniffi_pbcli_checksum_method_api_base@@Base+0xf2f24>
│ │  	beq.n	25f2a0 <uniffi_pbcli_checksum_method_api_base@@Base+0xf2a1c>
│ │  	b.n	25f72c <uniffi_pbcli_checksum_method_api_base@@Base+0xf2ea8>
│ │  	ands	r0, r0
│ │  	b.n	25f5d6 <uniffi_pbcli_checksum_method_api_base@@Base+0xf2d52>
│ │ @@ -455249,15 +455249,15 @@
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	25fabe <uniffi_pbcli_checksum_method_api_base@@Base+0xf323a>
│ │  	beq.n	25f3a0 <uniffi_pbcli_checksum_method_api_base@@Base+0xf2b1c>
│ │  	b.n	25f818 <uniffi_pbcli_checksum_method_api_base@@Base+0xf2f94>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r2, r4, r7, r8, ip, pc}
│ │  	vsra.u32	d25, d29, #31
│ │ -	vshr.u64	<illegal reg q9.5>, <illegal reg q3.5>, #31
│ │ +	vshr.u64	<illegal reg q9.5>, q15, #31
│ │  	vaddl.u32	q8, d4, d0
│ │  	b.n	25fa36 <uniffi_pbcli_checksum_method_api_base@@Base+0xf31b2>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (25f45c <uniffi_pbcli_checksum_method_api_base@@Base+0xf2bd8>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	25f8bc <uniffi_pbcli_checksum_method_api_base@@Base+0xf3038>
│ │  	str	r0, [r7, r0]
│ │ @@ -461264,18 +461264,18 @@
│ │  	b.n	2622e4 <uniffi_pbcli_checksum_method_api_base@@Base+0xf5a60>
│ │  	movs	r0, r0
│ │  	b.n	2628c8 <uniffi_pbcli_checksum_method_api_base@@Base+0xf6044>
│ │  	movs	r0, #2
│ │  	b.n	2628cc <uniffi_pbcli_checksum_method_api_base@@Base+0xf6048>
│ │  			@ <UNDEFINED> instruction: 0xffe4eaff
│ │  	ldr	r7, [pc, #284]	@ (2628d0 <uniffi_pbcli_checksum_method_api_base@@Base+0xf604c>)
│ │ -	vqshlu.s32	q15, <illegal reg q7.5>, #2
│ │ +	vrsubhn.i64	d30, q9, q3
│ │  	vmlal.u32	q14, d3, d13[1]
│ │  			@ <UNDEFINED> instruction: 0xffe14edf
│ │ -	vsli.64	q15, <illegal reg q11.5>, #34	@ 0x22
│ │ +	vqshlu.s32	d30, d14, #2
│ │  	vqshrun.s64	d20, q8, #29
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	262ce8 <uniffi_pbcli_checksum_method_api_base@@Base+0xf6464>
│ │  	beq.n	2627e0 <uniffi_pbcli_checksum_method_api_base@@Base+0xf5f5c>
│ │  	b.n	262c6c <uniffi_pbcli_checksum_method_api_base@@Base+0xf63e8>
│ │  	cmp	r0, #176	@ 0xb0
│ │  	b.n	2622f6 <uniffi_pbcli_checksum_method_api_base@@Base+0xf5a72>
│ │ @@ -462204,17 +462204,17 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	26373a <uniffi_pbcli_checksum_method_api_base@@Base+0xf6eb6>
│ │  	ldmia	r7, {r0, r2, r5, r7}
│ │  			@ <UNDEFINED> instruction: 0xebff0005
│ │  	b.n	263342 <uniffi_pbcli_checksum_method_api_base@@Base+0xf6abe>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r5, r7, r9, sl, lr}
│ │ -	vsubl.u32	q9, d18, d18
│ │ +	vmlal.u32	q9, d18, d9[0]
│ │  	vabdl.u32	q10, d4, d3
│ │ -	vrshr.u64	q9, q11, #30
│ │ +	vrsra.u32	d18, d13, #30
│ │  	vqshrun.s64	d20, q8, #28
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	263538 <uniffi_pbcli_checksum_method_api_base@@Base+0xf6cb4>
│ │  	beq.n	263030 <uniffi_pbcli_checksum_method_api_base@@Base+0xf67ac>
│ │  	b.n	2634bc <uniffi_pbcli_checksum_method_api_base@@Base+0xf6c38>
│ │  	ands	r0, r0
│ │  	b.n	263366 <uniffi_pbcli_checksum_method_api_base@@Base+0xf6ae2>
│ │ @@ -462260,15 +462260,15 @@
│ │  	b.n	2637be <uniffi_pbcli_checksum_method_api_base@@Base+0xf6f3a>
│ │  	movs	r5, r0
│ │  	b.n	2633c2 <uniffi_pbcli_checksum_method_api_base@@Base+0xf6b3e>
│ │  	beq.n	263094 <uniffi_pbcli_checksum_method_api_base@@Base+0xf6810>
│ │  	b.n	26351c <uniffi_pbcli_checksum_method_api_base@@Base+0xf6c98>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r5, r9, sl, lr}
│ │ -	vmls.i32	<illegal reg q10.5>, q9, d14[1]
│ │ +	vsli.32	d21, d5, #2
│ │  			@ <UNDEFINED> instruction: 0xffe34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2635b4 <uniffi_pbcli_checksum_method_api_base@@Base+0xf6d30>
│ │  	beq.n	2630d4 <uniffi_pbcli_checksum_method_api_base@@Base+0xf6850>
│ │  	b.n	263538 <uniffi_pbcli_checksum_method_api_base@@Base+0xf6cb4>
│ │  	str	r0, [sp, #0]
│ │  	b.n	2633e2 <uniffi_pbcli_checksum_method_api_base@@Base+0xf6b5e>
│ │ @@ -463132,27 +463132,27 @@
│ │  	b.n	263374 <uniffi_pbcli_checksum_method_api_base@@Base+0xf6af0>
│ │  	add.w	r0, r2, r7
│ │  	b.n	263b66 <uniffi_pbcli_checksum_method_api_base@@Base+0xf72e2>
│ │  	beq.n	263848 <uniffi_pbcli_checksum_method_api_base@@Base+0xf6fc4>
│ │  	b.n	263cc0 <uniffi_pbcli_checksum_method_api_base@@Base+0xf743c>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r1, r4, r5, r6, r7, r9, sl, fp, ip, sp}
│ │ -	vmls.i32	q11, q1, d6[1]
│ │ +	vraddhn.i64	d22, q9, <illegal reg q6.5>
│ │  	vqrdmlsh.s32	<illegal reg q9.5>, <illegal reg q1.5>, d11[1]
│ │ -	vsri.64	q11, q7, #30
│ │ +	vabal.u32	q11, d2, d5
│ │  			@ <UNDEFINED> instruction: 0xffe33f2f
│ │ -	vraddhn.i64	d22, q9, q9
│ │ +	vmls.i32	q11, q9, d9[0]
│ │  			@ <UNDEFINED> instruction: 0xffe33ed7
│ │ -	vmls.i32	q11, q1, d10[0]
│ │ +	vsri.32	q11, <illegal reg q8.5>, #30
│ │  			@ <UNDEFINED> instruction: 0xffe33e9f
│ │ -	vsri.32	d22, d2, #30
│ │ +	vsri.32	d22, d25, #30
│ │  			@ <UNDEFINED> instruction: 0xffe33ebb
│ │ -	vraddhn.i64	d22, q1, q15
│ │ +	vsri.32	q11, <illegal reg q2.5>, #30
│ │  			@ <UNDEFINED> instruction: 0xffe33f93
│ │ -	vabal.u32	q11, d2, d6
│ │ +	vabal.u32	q11, d2, d29
│ │  	vqrdmlah.s32	<illegal reg q9.5>, <illegal reg q1.5>, d11[1]
│ │  			@ <UNDEFINED> instruction: 0xffe24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	263d8c <uniffi_pbcli_checksum_method_api_base@@Base+0xf7508>
│ │  	beq.n	26388c <uniffi_pbcli_checksum_method_api_base@@Base+0xf7008>
│ │  	b.n	263d10 <uniffi_pbcli_checksum_method_api_base@@Base+0xf748c>
│ │  	str	r0, [r0, #0]
│ │ @@ -463535,25 +463535,25 @@
│ │  	movs	r6, r0
│ │  	b.n	263f0a <uniffi_pbcli_checksum_method_api_base@@Base+0xf7686>
│ │  	ldrb	r1, [r2, #27]
│ │  			@ <UNDEFINED> instruction: 0xeb049000
│ │  	b.n	264312 <uniffi_pbcli_checksum_method_api_base@@Base+0xf7a8e>
│ │  	vpmin.u16	q15, <illegal reg q9.5>, <illegal reg q15.5>
│ │  	subs	r5, #135	@ 0x87
│ │ -	vmull.u32	<illegal reg q13.5>, d18, d6
│ │ +	vmull.u32	<illegal reg q13.5>, d18, d29
│ │  	vcvt.f16.u16	<illegal reg q9.5>, <illegal reg q13.5>, #29
│ │  	vmull.u32	<illegal reg q9.5>, d18, d15
│ │  			@ <UNDEFINED> instruction: 0xffe23b57
│ │  			@ <UNDEFINED> instruction: 0xffe23b6b
│ │  			@ <UNDEFINED> instruction: 0xffe23b2b
│ │  			@ <UNDEFINED> instruction: 0xffe23b3f
│ │  	vmull.u32	<illegal reg q9.5>, d18, d7[1]
│ │  			@ <UNDEFINED> instruction: 0xffe23afb
│ │  			@ <UNDEFINED> instruction: 0xffe23daf
│ │ -	vmull.u32	<illegal reg q13.5>, d18, d30
│ │ +			@ <UNDEFINED> instruction: 0xffe2bcd5
│ │  			@ <UNDEFINED> instruction: 0xffe34df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	264128 <uniffi_pbcli_checksum_method_api_base@@Base+0xf78a4>
│ │  	strb	r4, [r0, #0]
│ │  	b.n	263732 <uniffi_pbcli_checksum_method_api_base@@Base+0xf6eae>
│ │  	strh	r3, [r0, #0]
│ │  	b.n	263f56 <uniffi_pbcli_checksum_method_api_base@@Base+0xf76d2>
│ │ @@ -466836,25 +466836,25 @@
│ │  	stmia	r5!, {r0, r1, r2, r4, r6, r7}
│ │  	add.w	r0, r1, pc, lsl #8
│ │  	b.n	265e2a <uniffi_pbcli_checksum_method_api_base@@Base+0xf95a6>
│ │  			@ <UNDEFINED> instruction: 0xff9eeaff
│ │  	lsls	r0, r1, #9
│ │  	movs	r0, r0
│ │  	subs	r7, r5, #7
│ │ -	vqrdmlah.s32	q9, q9, d15[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe22ef6
│ │  	vqrdmlah.s32	<illegal reg q8.5>, <illegal reg q9.5>, d11[1]
│ │ -	vqrdmulh.s32	q9, q9, d11[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe22df2
│ │  	vshr.u32	d18, d15, #29
│ │ -			@ <UNDEFINED> instruction: 0xffe22eff
│ │ +			@ <UNDEFINED> instruction: 0xffe22f26
│ │  	vqrdmlah.s32	<illegal reg q8.5>, <illegal reg q9.5>, d15[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe22daf
│ │ +			@ <UNDEFINED> instruction: 0xffe22dd6
│ │  			@ <UNDEFINED> instruction: 0xffe31e97
│ │ -	vcvt.u16.f16	q9, <illegal reg q11.5>, #30
│ │ +			@ <UNDEFINED> instruction: 0xffe22d9e
│ │  	vqrdmlah.s32	<illegal reg q8.5>, <illegal reg q1.5>, d11[1]
│ │ -	vqrdmulh.s32	q9, q1, d11[0]
│ │ +	vcvt.u16.f16	q9, q9, #30
│ │  			@ <UNDEFINED> instruction: 0xffe37b1c
│ │  	movs	r7, r4
│ │  	ldrb	r0, [r6, #9]
│ │  	movs	r7, r4
│ │  	asrs	r0, r0, #32
│ │  	b.n	265390 <uniffi_pbcli_checksum_method_api_base@@Base+0xf8b0c>
│ │  	movs	r0, r0
│ │ @@ -467185,15 +467185,15 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	2662aa <uniffi_pbcli_checksum_method_api_base@@Base+0xf9a26>
│ │  	stmia	r4!, {r0, r3, r6, r7}
│ │  			@ <UNDEFINED> instruction: 0xebff0005
│ │  	b.n	265eb2 <uniffi_pbcli_checksum_method_api_base@@Base+0xf962e>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r8, r9, fp, ip}
│ │ -	vmla.i32	q10, q9, d1[0]
│ │ +	vmla.i32	q10, q9, d8[1]
│ │  			@ <UNDEFINED> instruction: 0xffe34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2660a0 <uniffi_pbcli_checksum_method_api_base@@Base+0xf981c>
│ │  	beq.n	265ba0 <uniffi_pbcli_checksum_method_api_base@@Base+0xf931c>
│ │  	b.n	266024 <uniffi_pbcli_checksum_method_api_base@@Base+0xf97a0>
│ │  	strh	r0, [r1, #0]
│ │  	b.n	2656c4 <uniffi_pbcli_checksum_method_api_base@@Base+0xf8e40>
│ │ @@ -467871,17 +467871,17 @@
│ │  			@ <UNDEFINED> instruction: 0xffed1aff
│ │  	lsls	r4, r5, #1
│ │  	b.n	265c32 <uniffi_pbcli_checksum_method_api_base@@Base+0xf93ae>
│ │  	movs	r1, r0
│ │  	b.n	26686e <uniffi_pbcli_checksum_method_api_base@@Base+0xf9fea>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r1, r7, r8, ip, sp, lr}
│ │ -	vqdmulh.s32	<illegal reg q14.5>, <illegal reg q8.5>, d7[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe1dd0e
│ │  			@ <UNDEFINED> instruction: 0xffe36fde
│ │ -			@ <UNDEFINED> instruction: 0xffe1db43
│ │ +			@ <UNDEFINED> instruction: 0xffe1db6a
│ │  	vqshl.u32	<illegal reg q8.5>, q2, #3
│ │  	b.n	265c66 <uniffi_pbcli_checksum_method_api_base@@Base+0xf93e2>
│ │  	movs	r1, r0
│ │  	b.n	26676c <uniffi_pbcli_checksum_method_api_base@@Base+0xf9ee8>
│ │  	movs	r7, r1
│ │  	lsrs	r0, r0, #8
│ │  	movs	r0, #12
│ │ @@ -468707,15 +468707,15 @@
│ │  	movs	r1, r0
│ │  	b.n	266eda <uniffi_pbcli_checksum_method_api_base@@Base+0xfa656>
│ │  	vpmin.u8	q5, q14, <illegal reg q15.5>
│ │  			@ <UNDEFINED> instruction: 0xffd2eaff
│ │  	ldr	r2, [r0, #52]	@ 0x34
│ │  	vqrdmlsh.s32	<illegal reg q8.5>, <illegal reg q0.5>, d15[0]
│ │  			@ <UNDEFINED> instruction: 0xffe16cd6
│ │ -	vmul.i32	<illegal reg q9.5>, <illegal reg q0.5>, d8[0]
│ │ +	vmul.i32	<illegal reg q9.5>, <illegal reg q0.5>, d15[1]
│ │  	vaddl.u32	<illegal reg q8.5>, d3, d0
│ │  	b.n	266b96 <uniffi_pbcli_checksum_method_api_base@@Base+0xfa312>
│ │  	lsls	r4, r6, #8
│ │  	b.n	26637a <uniffi_pbcli_checksum_method_api_base@@Base+0xf9af6>
│ │  	movs	r0, #16
│ │  	b.n	26637e <uniffi_pbcli_checksum_method_api_base@@Base+0xf9afa>
│ │  	movs	r1, r0
│ │ @@ -469876,15 +469876,15 @@
│ │  	b.n	267144 <uniffi_pbcli_checksum_method_api_base@@Base+0xfa8c0>
│ │  	movs	r0, r0
│ │  	b.n	266d0c <uniffi_pbcli_checksum_method_api_base@@Base+0xfa488>
│ │  	movs	r1, r0
│ │  	b.n	26794e <uniffi_pbcli_checksum_method_api_base@@Base+0xfb0ca>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r1, r2, r5, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffe158d2
│ │ +			@ <UNDEFINED> instruction: 0xffe158f9
│ │  	vsra.u32	d22, d16, #29
│ │  	movs	r7, r4
│ │  	str	r4, [r5, #16]
│ │  	movs	r7, r4
│ │  	str	r0, [r7, #28]
│ │  	movs	r7, r4
│ │  	str	r0, [r5, #28]
│ │ @@ -470317,19 +470317,19 @@
│ │  			@ <UNDEFINED> instruction: 0xfff2eaff
│ │  	str	r1, [r0, #0]
│ │  	b.n	267d02 <uniffi_pbcli_checksum_method_api_base@@Base+0xfb47e>
│ │  			@ <UNDEFINED> instruction: 0xfff0eaff
│ │  	ldrsh	r4, [r3, r2]
│ │  	movs	r7, r4
│ │  	ldrb	r2, [r5, r2]
│ │ -	vaddl.u32	<illegal reg q13.5>, d1, d21
│ │ +	vmla.i32	<illegal reg q13.5>, <illegal reg q0.5>, d12[0]
│ │  	vcvt.f16.u16	<illegal reg q10.5>, q11, #29
│ │ -			@ <UNDEFINED> instruction: 0xffe1aff1
│ │ +	vshr.u32	d27, d8, #31
│ │  			@ <UNDEFINED> instruction: 0xffe35b6a
│ │ -	vqrdmlah.s32	q13, <illegal reg q8.5>, d5[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe1af0c
│ │  			@ <UNDEFINED> instruction: 0xffe348f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	267b04 <uniffi_pbcli_checksum_method_api_base@@Base+0xfb280>
│ │  	beq.n	2675fc <uniffi_pbcli_checksum_method_api_base@@Base+0xfad78>
│ │  	b.n	267a88 <uniffi_pbcli_checksum_method_api_base@@Base+0xfb204>
│ │  	str	r0, [r1, #40]	@ 0x28
│ │  	b.n	267112 <uniffi_pbcli_checksum_method_api_base@@Base+0xfa88e>
│ │ @@ -470475,19 +470475,19 @@
│ │  	movs	r0, #2
│ │  	b.n	267844 <uniffi_pbcli_checksum_method_api_base@@Base+0xfafc0>
│ │  	bkpt	0x0016
│ │  	add.w	r1, r1, r3, lsl #8
│ │  	b.n	267d2e <uniffi_pbcli_checksum_method_api_base@@Base+0xfb4aa>
│ │  			@ <UNDEFINED> instruction: 0xffeceaff
│ │  	ldrh	r2, [r7, r0]
│ │ -	vsubw.u32	<illegal reg q10.5>, <illegal reg q0.5>, d20
│ │ +			@ <UNDEFINED> instruction: 0xffe1534b
│ │  			@ <UNDEFINED> instruction: 0xffe359ae
│ │ -	vrshr.u64	d21, d8, #31
│ │ +	vrshr.u64	d21, d31, #31
│ │  			@ <UNDEFINED> instruction: 0xffe359fa
│ │ -	vmlal.u32	<illegal reg q10.5>, d17, d4[1]
│ │ +	vsubw.u32	<illegal reg q10.5>, <illegal reg q0.5>, d11
│ │  			@ <UNDEFINED> instruction: 0xffe34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	267c6c <uniffi_pbcli_checksum_method_api_base@@Base+0xfb3e8>
│ │  	beq.n	26781c <uniffi_pbcli_checksum_method_api_base@@Base+0xfaf98>
│ │  	b.n	267bf0 <uniffi_pbcli_checksum_method_api_base@@Base+0xfb36c>
│ │  	str	r0, [r0, #0]
│ │  	b.n	267e9a <uniffi_pbcli_checksum_method_api_base@@Base+0xfb616>
│ │ @@ -471787,16 +471787,16 @@
│ │  	vrshr.u32	<illegal reg q10.5>, q3, #31
│ │  			@ <UNDEFINED> instruction: 0xffe11faa
│ │  	vmlal.u32	<illegal reg q10.5>, d17, d10[0]
│ │  	vshr.u32	d18, d14, #31
│ │  			@ <UNDEFINED> instruction: 0xffe14f86
│ │  			@ <UNDEFINED> instruction: 0xffe11cda
│ │  	vrsra.u64	q14, q14, #31
│ │ -			@ <UNDEFINED> instruction: 0xffe25fb4
│ │ -	vcvt.f16.u16	<illegal reg q14.5>, q7, #29
│ │ +			@ <UNDEFINED> instruction: 0xffe25fdb
│ │ +	vmull.u32	<illegal reg q14.5>, d19, d5
│ │  	vqrdmlsh.s32	q10, q9, d6[0]
│ │  	vcvt.u16.f16	d17, d10, #31
│ │  	vrsra.u32	d21, d30, #31
│ │  	vshr.u64	d18, d2, #31
│ │  	vqrdmlsh.s32	q10, <illegal reg q0.5>, d10[1]
│ │  			@ <UNDEFINED> instruction: 0xffe11cbe
│ │  			@ <UNDEFINED> instruction: 0xffe14efa
│ │ @@ -473626,15 +473626,15 @@
│ │  	vmlsl.u32	<illegal reg q8.5>, d17, d0
│ │  	vaddw.u32	q10, q1, d10
│ │  	vabdl.u32	<illegal reg q8.5>, d17, d24
│ │  	vsra.u32	d20, d22, #30
│ │  	vqshl.u64	<illegal reg q8.5>, q2, #33	@ 0x21
│ │  	vaddl.u32	q10, d2, d26
│ │  	vmlsl.u32	<illegal reg q8.5>, d17, d8[0]
│ │ -	vsubw.u32	<illegal reg q15.5>, q9, d11
│ │ +	vrsra.u64	d31, d18, #30
│ │  	vrsra.u32	d21, d27, #30
│ │  	vqrdmlsh.s32	<illegal reg q9.5>, q9, d6[1]
│ │  	vrsubhn.i64	d17, <illegal reg q8.5>, q2
│ │  	vrshr.u32	d20, d26, #30
│ │  			@ <UNDEFINED> instruction: 0xffe118d8
│ │  			@ <UNDEFINED> instruction: 0xffe23e96
│ │  	vqrdmlah.s32	<illegal reg q9.5>, <illegal reg q0.5>, d2[1]
│ │ @@ -473968,15 +473968,15 @@
│ │  	ldr	r4, [pc, #64]	@ (26966c <uniffi_pbcli_checksum_method_api_base@@Base+0xfcde8>)
│ │  	ldmia.w	sp!, {r1, r2, r7, sl, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeaff0004
│ │  	b.n	269976 <uniffi_pbcli_checksum_method_api_base@@Base+0xfd0f2>
│ │  	ldr	r4, [pc, #64]	@ (269678 <uniffi_pbcli_checksum_method_api_base@@Base+0xfcdf4>)
│ │  	ldmia.w	sp!, {r0, r1, r6, r7, r8}
│ │  	and.w	fp, r0, sl, lsr #12
│ │ -			@ <UNDEFINED> instruction: 0xffe11bed
│ │ +	vcvt.f16.u16	d17, d4, #31
│ │  			@ <UNDEFINED> instruction: 0xffe34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	269b68 <uniffi_pbcli_checksum_method_api_base@@Base+0xfd2e4>
│ │  	beq.n	269678 <uniffi_pbcli_checksum_method_api_base@@Base+0xfcdf4>
│ │  	b.n	269aec <uniffi_pbcli_checksum_method_api_base@@Base+0xfd268>
│ │  	str	r0, [r0, r0]
│ │  	b.n	269996 <uniffi_pbcli_checksum_method_api_base@@Base+0xfd112>
│ │ @@ -474737,43 +474737,43 @@
│ │  	b.n	269804 <uniffi_pbcli_checksum_method_api_base@@Base+0xfcf80>
│ │  	movs	r0, r0
│ │  	b.n	269de8 <uniffi_pbcli_checksum_method_api_base@@Base+0xfd564>
│ │  	movs	r0, #2
│ │  	b.n	269dec <uniffi_pbcli_checksum_method_api_base@@Base+0xfd568>
│ │  	mcr2	10, 4, lr, cr14, cr15, {7}	@ <UNPREDICTABLE>
│ │  	adds	r4, #6
│ │ -			@ <UNDEFINED> instruction: 0xffe12cd7
│ │ +			@ <UNDEFINED> instruction: 0xffe12cfe
│ │  	vmull.u32	<illegal reg q9.5>, d3, d6[0]
│ │  	vmul.f32	<illegal reg q9.5>, <illegal reg q8.5>, d6[0]
│ │ -	vrshr.u64	d19, d7, #31
│ │ +	vrshr.u64	d19, d30, #31
│ │  	vqrshrn.u64	d19, q15, #29
│ │ -	vmlal.u32	<illegal reg q9.5>, d1, d15[0]
│ │ +	vrshr.u32	<illegal reg q9.5>, q11, #31
│ │  			@ <UNDEFINED> instruction: 0xffe339f2
│ │ -	vmlal.u32	<illegal reg q9.5>, d17, d3[0]
│ │ +	vmlal.u32	<illegal reg q9.5>, d17, d10[1]
│ │  	vqshrun.s64	d19, q9, #29
│ │ -	vaddw.u32	<illegal reg q9.5>, <illegal reg q0.5>, d3
│ │ +	vaddw.u32	<illegal reg q9.5>, <illegal reg q0.5>, d26
│ │  	vmul.i32	<illegal reg q9.5>, <illegal reg q9.5>, d6[1]
│ │ -	vsra.u64	d19, d23, #31
│ │ +	vsra.u64	<illegal reg q9.5>, q7, #31
│ │  	vqshlu.s64	<illegal reg q9.5>, q15, #35	@ 0x23
│ │ -	vqrdmlsh.s32	q9, <illegal reg q8.5>, d15[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe12ff6
│ │  	vmlsl.u32	<illegal reg q9.5>, d3, d2[1]
│ │ -	vcvt.u32.f32	d18, d19, #31
│ │ +	vcvt.u32.f32	q9, q5, #31
│ │  	vabdl.u32	<illegal reg q9.5>, d19, d10
│ │ -	vshr.u32	<illegal reg q9.5>, <illegal reg q5.5>, #31
│ │ +	vaddl.u32	<illegal reg q9.5>, d17, d2
│ │  	vqshl.u32	<illegal reg q9.5>, q7, #3
│ │  			@ <UNDEFINED> instruction: 0xffe1374a
│ │  	vmls.f32	<illegal reg q9.5>, <illegal reg q8.5>, d10[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe12e9b
│ │ +	vqrdmlah.s32	q9, <illegal reg q8.5>, d2[0]
│ │  	vabal.u32	<illegal reg q9.5>, d3, d30
│ │  	vsli.64	<illegal reg q9.5>, q15, #33	@ 0x21
│ │ -	vqrdmlah.s32	q9, <illegal reg q8.5>, d15[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe12ef6
│ │  	vabal.u32	<illegal reg q9.5>, d19, d2
│ │ -	vcvt.f32.u32	q9, <illegal reg q1.5>, #31
│ │ +	vcvt.f32.u32	q9, q13, #31
│ │  	vraddhn.i64	d19, <illegal reg q9.5>, q3
│ │ -	vcvt.u16.f16	q9, <illegal reg q3.5>, #31
│ │ +	vcvt.u16.f16	q9, q15, #31
│ │  	vrshr.u64	<illegal reg q14.5>, q11, #29
│ │  	vqshrun.s64	d20, q8, #29
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	26a270 <uniffi_pbcli_checksum_method_api_base@@Base+0xfd9ec>
│ │  	ands	r0, r0
│ │  	b.n	26a09a <uniffi_pbcli_checksum_method_api_base@@Base+0xfd816>
│ │  	movs	r4, r0
│ │ @@ -476947,48 +476947,48 @@
│ │  	b.n	26b562 <uniffi_pbcli_checksum_method_api_base@@Base+0xfecde>
│ │  	movs	r1, r1
│ │  	b.n	26b3a6 <uniffi_pbcli_checksum_method_api_base@@Base+0xfeb22>
│ │  	asrs	r0, r2, #1
│ │  	b.n	26b7aa <uniffi_pbcli_checksum_method_api_base@@Base+0xfef26>
│ │  			@ <UNDEFINED> instruction: 0xffe1eaff
│ │  	cmp	r1, #218	@ 0xda
│ │ -	vmlal.u32	q9, d17, d5[1]
│ │ +	vsubw.u32	q9, <illegal reg q0.5>, d12
│ │  			@ <UNDEFINED> instruction: 0xffe329a6
│ │ -	vrshr.u64	d18, d17, #31
│ │ +	vrshr.u64	q9, q4, #31
│ │  			@ <UNDEFINED> instruction: 0xffe328f2
│ │ -	vsra.u64	q9, <illegal reg q14.5>, #31
│ │ -	vrshr.u32	<illegal reg q15.5>, <illegal reg q14.5>, #29
│ │ +	vsubl.u32	q9, d1, d20
│ │ +	vsubl.u32	<illegal reg q15.5>, d19, d20
│ │  	vmul.i32	q9, q9, d6[0]
│ │ -	vsra.u64	q9, <illegal reg q0.5>, #31
│ │ +	vsra.u64	q9, q12, #31
│ │  			@ <UNDEFINED> instruction: 0xffe3290e
│ │ -	vrshr.u32	d18, d9, #31
│ │ +	vmlal.u32	q9, d1, d0[0]
│ │  	vmlal.u32	q9, d19, d2[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe11bed
│ │ +	vcvt.f16.u16	d17, d4, #31
│ │  			@ <UNDEFINED> instruction: 0xffe32896
│ │  	vrshr.u32	q9, q3, #31
│ │ -			@ <UNDEFINED> instruction: 0xffe11b61
│ │ +			@ <UNDEFINED> instruction: 0xffe11b88
│ │  	vqshlu.s64	d18, d2, #35	@ 0x23
│ │  	vsri.64	<illegal reg q13.5>, <illegal reg q8.5>, #31
│ │  	vmls.f32	q9, <illegal reg q0.5>, d10[0]
│ │ -	vqshl.u32	d26, d17, #1
│ │ +	vqshl.u32	q13, q4, #1
│ │  	vmlal.u32	q9, d3, d2
│ │  	vsri.32	d18, d14, #31
│ │ -	vrsubhn.i64	d26, <illegal reg q0.5>, <illegal reg q2.5>
│ │ +	vrsubhn.i64	d26, <illegal reg q0.5>, q14
│ │  	vsri.32	d18, d26, #29
│ │ -	vrsubhn.i64	d26, <illegal reg q0.5>, <illegal reg q8.5>
│ │ +	vmlsl.u32	q13, d1, d8[0]
│ │  	vsubw.u32	q9, <illegal reg q9.5>, d30
│ │ -	vsli.64	d26, d5, #33	@ 0x21
│ │ +	vsli.64	d26, d28, #33	@ 0x21
│ │  			@ <UNDEFINED> instruction: 0xffe323ee
│ │ -	vsli.64	q13, <illegal reg q2.5>, #33	@ 0x21
│ │ +	vsli.64	q13, q14, #33	@ 0x21
│ │  	vmls.i32	q12, <illegal reg q9.5>, d8[1]
│ │  			@ <UNDEFINED> instruction: 0xffe2fdfd
│ │  	vsubl.u32	q9, d17, d22
│ │ -	vraddhn.i64	d26, <illegal reg q8.5>, <illegal reg q6.5>
│ │ +	vsri.64	d26, d20, #31
│ │  	vmla.f32	q9, <illegal reg q1.5>, d14[0]
│ │ -	vrsra.u32	d26, d21, #31
│ │ +	vrsra.u32	q13, q6, #31
│ │  	vmlsl.u32	q9, d19, d14[0]
│ │  	vsli.32	d18, d14, #1
│ │  	vsli.32	d18, d19, #1
│ │  	vsubl.u32	q9, d17, d10
│ │  	vrshr.u64	d18, d15, #31
│ │  	vrshr.u32	d18, d14, #31
│ │  	vrshr.u32	d18, d19, #31
│ │ @@ -477143,19 +477143,19 @@
│ │  	b.n	26b5ba <uniffi_pbcli_checksum_method_api_base@@Base+0xfed36>
│ │  	movs	r0, #12
│ │  	b.n	26b8fe <uniffi_pbcli_checksum_method_api_base@@Base+0xff07a>
│ │  	asrs	r0, r2, #1
│ │  	b.n	26b9c2 <uniffi_pbcli_checksum_method_api_base@@Base+0xff13e>
│ │  			@ <UNDEFINED> instruction: 0xffd8eaff
│ │  	subs	r6, r7, #3
│ │ -	vmla.i32	q13, <illegal reg q8.5>, d14[0]
│ │ -	vqshl.u64	q15, <illegal reg q2.5>, #35	@ 0x23
│ │ -	vabdl.u32	q15, d18, d29
│ │ +	vshr.u64	q13, <illegal reg q10.5>, #31
│ │ +	vqshl.u64	q15, q14, #35	@ 0x23
│ │ +	vqshl.u64	q15, q2, #34	@ 0x22
│ │  	vqrdmlah.s32	<illegal reg q8.5>, q1, d6[1]
│ │ -	vshr.u32	d26, d22, #31
│ │ +	vshr.u32	q13, <illegal reg q6.5>, #31
│ │  	vcvt.f16.u16	d20, d0, #29
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	26b7c0 <uniffi_pbcli_checksum_method_api_base@@Base+0xfef3c>
│ │  	ands	r0, r0
│ │  	b.n	26b5ea <uniffi_pbcli_checksum_method_api_base@@Base+0xfed66>
│ │  	lsls	r4, r5, #1
│ │  	b.n	26adce <uniffi_pbcli_checksum_method_api_base@@Base+0xfe54a>
│ │ @@ -479355,22 +479355,22 @@
│ │  	b.n	26cd4a <uniffi_pbcli_checksum_method_api_base@@Base+0x1004c6>
│ │  	movs	r0, r1
│ │  	b.n	26cc8e <uniffi_pbcli_checksum_method_api_base@@Base+0x10040a>
│ │  	movs	r0, #12
│ │  	b.n	26cd12 <uniffi_pbcli_checksum_method_api_base@@Base+0x10048e>
│ │  			@ <UNDEFINED> instruction: 0xffdaeaff
│ │  	lsrs	r6, r2, #16
│ │ -			@ <UNDEFINED> instruction: 0xffe148fe
│ │ +			@ <UNDEFINED> instruction: 0xffe14925
│ │  			@ <UNDEFINED> instruction: 0xffe30b5e
│ │ -	vmul.i32	q10, <illegal reg q0.5>, d6[0]
│ │ +	vmul.i32	q10, <illegal reg q0.5>, d13[1]
│ │  			@ <UNDEFINED> instruction: 0xffe30b8e
│ │ -	vqrshrun.s64	d20, q11, #31
│ │ +			@ <UNDEFINED> instruction: 0xffe1489d
│ │  			@ <UNDEFINED> instruction: 0xffe30b2e
│ │  			@ <UNDEFINED> instruction: 0xffe10ad6
│ │ -	vqshl.u64	d20, d30, #33	@ 0x21
│ │ +			@ <UNDEFINED> instruction: 0xffe147e5
│ │  			@ <UNDEFINED> instruction: 0xffe34df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	26cb5c <uniffi_pbcli_checksum_method_api_base@@Base+0x1002d8>
│ │  	beq.n	26c6a4 <uniffi_pbcli_checksum_method_api_base@@Base+0xffe20>
│ │  	b.n	26cae0 <uniffi_pbcli_checksum_method_api_base@@Base+0x10025c>
│ │  	ands	r0, r0
│ │  	b.n	26c98a <uniffi_pbcli_checksum_method_api_base@@Base+0x100106>
│ │ @@ -479688,27 +479688,27 @@
│ │  	movs	r0, #2
│ │  	b.n	26ca24 <uniffi_pbcli_checksum_method_api_base@@Base+0x1001a0>
│ │  	add	r1, sp, #632	@ 0x278
│ │  	add.w	r0, r1, r0, lsl #24
│ │  	b.n	26d04e <uniffi_pbcli_checksum_method_api_base@@Base+0x1007ca>
│ │  			@ <UNDEFINED> instruction: 0xff8beaff
│ │  	lsrs	r2, r4, #5
│ │ -	vshll.u32	<illegal reg q8.5>, d4, #1
│ │ +	vshll.u32	<illegal reg q8.5>, d27, #1
│ │  			@ <UNDEFINED> instruction: 0xffe30926
│ │ -			@ <UNDEFINED> instruction: 0xffe119d8
│ │ +			@ <UNDEFINED> instruction: 0xffe119ff
│ │  			@ <UNDEFINED> instruction: 0xffe38d88
│ │  	movs	r3, r4
│ │  	lsrs	r6, r2, #6
│ │ -	vmull.u32	<illegal reg q8.5>, d1, d8[0]
│ │ +	vmull.u32	<illegal reg q8.5>, d1, d15[1]
│ │  	vmlal.u32	q8, d19, d22
│ │ -	vqrshrn.u64	d17, q4, #31
│ │ +	vqrshrn.u64	d17, <illegal reg q15.5>, #31
│ │  	vqrshrun.s64	d16, q13, #29
│ │ -			@ <UNDEFINED> instruction: 0xffe1192c
│ │ +	vqrshrn.u64	d17, <illegal reg q1.5>, #31
│ │  			@ <UNDEFINED> instruction: 0xffe307ce
│ │ -	vmlal.u32	<illegal reg q8.5>, d17, d0
│ │ +	vmlal.u32	<illegal reg q8.5>, d17, d23
│ │  			@ <UNDEFINED> instruction: 0xffe38cb0
│ │  	movs	r3, r4
│ │  	ldr	r5, [pc, #960]	@ (26cd0c <uniffi_pbcli_checksum_method_api_base@@Base+0x100488>)
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	26ce6c <uniffi_pbcli_checksum_method_api_base@@Base+0x1005e8>
│ │  	beq.n	26c9f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x100170>
│ │  	b.n	26cdf0 <uniffi_pbcli_checksum_method_api_base@@Base+0x10056c>
│ │ @@ -483264,18 +483264,18 @@
│ │  	beq.n	26e77c <uniffi_pbcli_checksum_method_api_base@@Base+0x101ef8>
│ │  	b.n	26ebf4 <uniffi_pbcli_checksum_method_api_base@@Base+0x102370>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, ip, sp, lr}
│ │  	b.n	26eea6 <uniffi_pbcli_checksum_method_api_base@@Base+0x102622>
│ │  			@ <UNDEFINED> instruction: 0xffa0eaff
│ │  	lsls	r5, r6, #6
│ │ -			@ <UNDEFINED> instruction: 0xffe2e362
│ │ +	vsubw.u32	q15, q9, d9
│ │  	vsra.u64	q8, <illegal reg q12.5>, #30
│ │  	vsra.u32	d16, d9, #30
│ │ -	vmlal.u32	q15, d18, d6[0]
│ │ +	vmlal.u32	q15, d18, d13[1]
│ │  	vcvt.u16.f16	<illegal reg q10.5>, <illegal reg q10.5>, #30
│ │  	vrsra.u32	<illegal reg q8.5>, <illegal reg q1.5>, #30
│ │  	and.w	ip, r0, r0, lsr #16
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	26eca8 <uniffi_pbcli_checksum_method_api_base@@Base+0x102424>
│ │  	movs	r0, #4
│ │  	b.n	26e2b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x101a2e>
│ │ @@ -484086,23 +484086,23 @@
│ │  	b.n	26f5be <uniffi_pbcli_checksum_method_api_base@@Base+0x102d3a>
│ │  	movs	r5, r1
│ │  	b.n	26f5c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x102d3e>
│ │  	asrs	r0, r4, #3
│ │  	b.n	26f5c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x102d42>
│ │  			@ <UNDEFINED> instruction: 0xff9deaff
│ │  	ldmia	r2, {r0, r1, r2, r4}
│ │ -	vabdl.u32	<illegal reg q9.5>, d16, d24
│ │ +			@ <UNDEFINED> instruction: 0xffe037cf
│ │  	vmul.f32	q14, <illegal reg q9.5>, d7[1]
│ │ -	vqshl.u32	<illegal reg q9.5>, q12, #0
│ │ +	vqshl.u64	d19, d15, #32
│ │  	vmull.u32	q14, d3, d3[0]
│ │  	vabal.u32	<illegal reg q8.5>, d0, d7
│ │  	vmul.i32	q14, <illegal reg q0.5>, d3[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe0db94
│ │ +			@ <UNDEFINED> instruction: 0xffe0dbbb
│ │  	vmlal.u32	q14, d18, d19
│ │ -			@ <UNDEFINED> instruction: 0xffe0dbd4
│ │ +			@ <UNDEFINED> instruction: 0xffe0dbfb
│ │  	vqshrun.s64	d20, q8, #30
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	26f3d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x102b50>
│ │  	movs	r0, r0
│ │  	b.n	26f560 <uniffi_pbcli_checksum_method_api_base@@Base+0x102cdc>
│ │  	movs	r3, r2
│ │  	lsrs	r0, r0, #8
│ │ @@ -485682,23 +485682,23 @@
│ │  			@ <UNDEFINED> instruction: 0xeb02fed8
│ │  			@ <UNDEFINED> instruction: 0xeaff7000
│ │  	b.n	27039e <uniffi_pbcli_checksum_method_api_base@@Base+0x103b1a>
│ │  			@ <UNDEFINED> instruction: 0xfff7eaff
│ │  	ands	r0, r0
│ │  	b.n	2703a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x103b22>
│ │  			@ <UNDEFINED> instruction: 0xfff1eaff
│ │ -	str	r6, [r5, #64]	@ 0x40
│ │ +	str	r5, [r2, #68]	@ 0x44
│ │  			@ <UNDEFINED> instruction: 0xffe21fd3
│ │ -	vraddhn.i64	d22, <illegal reg q0.5>, q1
│ │ +	vraddhn.i64	d22, <illegal reg q0.5>, <illegal reg q12.5>
│ │  			@ <UNDEFINED> instruction: 0xffe21fa7
│ │ -			@ <UNDEFINED> instruction: 0xffe15f8a
│ │ +			@ <UNDEFINED> instruction: 0xffe15fb1
│ │  			@ <UNDEFINED> instruction: 0xffe21b2f
│ │ -	vmla.f32	q11, <illegal reg q8.5>, d6[0]
│ │ -	vcvt.u32.f32	<illegal reg q10.5>, q1, #30
│ │ -	vqrdmlsh.s32	<illegal reg q10.5>, q9, d10[0]
│ │ +	vmla.f32	q11, <illegal reg q8.5>, d13[1]
│ │ +	vcvt.u32.f32	<illegal reg q10.5>, <illegal reg q12.5>, #30
│ │ +			@ <UNDEFINED> instruction: 0xffe25ff1
│ │  	vaddl.u32	<illegal reg q9.5>, d2, d0
│ │  	b.n	2703d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x103b4e>
│ │  	lsrs	r5, r5, #15
│ │  	and.w	sp, r3, r0, ror #19
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2701b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x103934>
│ │  	beq.n	26fd40 <uniffi_pbcli_checksum_method_api_base@@Base+0x1034bc>
│ │ @@ -485847,19 +485847,19 @@
│ │  	add.w	r0, r0, r4, lsl #16
│ │  	b.n	26fee2 <uniffi_pbcli_checksum_method_api_base@@Base+0x10365e>
│ │  	movs	r4, r0
│ │  	b.n	270126 <uniffi_pbcli_checksum_method_api_base@@Base+0x1038a2>
│ │  	beq.n	26fe18 <uniffi_pbcli_checksum_method_api_base@@Base+0x103594>
│ │  	b.n	270280 <uniffi_pbcli_checksum_method_api_base@@Base+0x1039fc>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r1, r4, r7, r9, sl, fp, ip, lr}
│ │ -	vmull.p64	<illegal reg q10.5>, d18, d21
│ │ -	vqrdmlah.s32	<illegal reg q10.5>, q1, d10[0]
│ │ +	ldmia.w	sp!, {r0, r3, r4, r5, r7, r9, sl, fp, ip, lr}
│ │ +	vqrdmlah.s32	<illegal reg q10.5>, q9, d12[0]
│ │ +	vcvt.f32.u32	<illegal reg q10.5>, <illegal reg q8.5>, #30
│ │  			@ <UNDEFINED> instruction: 0xffe2199f
│ │ -	vmull.p64	<illegal reg q10.5>, d1, d6
│ │ +	vmull.p64	<illegal reg q10.5>, d1, d29
│ │  	vrsubhn.i64	d20, q9, q11
│ │  	vcvt.f16.u16	q10, q8, #31
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	270328 <uniffi_pbcli_checksum_method_api_base@@Base+0x103aa4>
│ │  	beq.n	26fe40 <uniffi_pbcli_checksum_method_api_base@@Base+0x1035bc>
│ │  	b.n	2702ac <uniffi_pbcli_checksum_method_api_base@@Base+0x103a28>
│ │  	str	r0, [r0, r0]
│ │ @@ -485938,15 +485938,15 @@
│ │  	b.n	2701f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x10396e>
│ │  	beq.n	26fed4 <uniffi_pbcli_checksum_method_api_base@@Base+0x103650>
│ │  	b.n	27034c <uniffi_pbcli_checksum_method_api_base@@Base+0x103ac8>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {ip, lr}
│ │  	b.n	2705fe <uniffi_pbcli_checksum_method_api_base@@Base+0x103d7a>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │ -	ldrb	r2, [r2, r4]
│ │ +	ldrb	r1, [r7, r4]
│ │  	vrsra.u32	d16, d7, #30
│ │  			@ <UNDEFINED> instruction: 0xffe14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2703ec <uniffi_pbcli_checksum_method_api_base@@Base+0x103b68>
│ │  	beq.n	26ff0c <uniffi_pbcli_checksum_method_api_base@@Base+0x103688>
│ │  	b.n	270370 <uniffi_pbcli_checksum_method_api_base@@Base+0x103aec>
│ │  	movs	r0, r0
│ │ @@ -486243,22 +486243,22 @@
│ │  	lsrs	r0, r0, #8
│ │  	movs	r7, r0
│ │  	b.n	270492 <uniffi_pbcli_checksum_method_api_base@@Base+0x103c0e>
│ │  	movs	r2, r1
│ │  	add.w	r0, r0, r0, lsl #28
│ │  	b.n	27089a <uniffi_pbcli_checksum_method_api_base@@Base+0x104016>
│ │  			@ <UNDEFINED> instruction: 0xff9eeaff
│ │ -	ldrh	r6, [r4, r7]
│ │ +	ldrb	r5, [r1, r0]
│ │  			@ <UNDEFINED> instruction: 0xffe247ee
│ │ -	vmull.u32	<illegal reg q10.5>, d1, d2
│ │ +	vmull.u32	<illegal reg q10.5>, d1, d25
│ │  	vmlal.u32	q10, d2, d10
│ │ -			@ <UNDEFINED> instruction: 0xffe15b9e
│ │ -			@ <UNDEFINED> instruction: 0xffe25b3e
│ │ -	vmull.u32	<illegal reg q10.5>, d18, d2[1]
│ │ -	vmlsl.u32	<illegal reg q10.5>, d18, d2
│ │ +			@ <UNDEFINED> instruction: 0xffe15bc5
│ │ +			@ <UNDEFINED> instruction: 0xffe25b65
│ │ +			@ <UNDEFINED> instruction: 0xffe25b09
│ │ +	vmlsl.u32	<illegal reg q10.5>, d18, d25
│ │  	vrsubhn.i64	d20, q9, q5
│ │  	vqshrun.s64	d20, q8, #31
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2706a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x103e20>
│ │  	movs	r0, r0
│ │  	b.n	27082e <uniffi_pbcli_checksum_method_api_base@@Base+0x103faa>
│ │  	movs	r4, r4
│ │ @@ -486329,17 +486329,17 @@
│ │  	cmp	r6, #23
│ │  	b.n	27095a <uniffi_pbcli_checksum_method_api_base@@Base+0x1040d6>
│ │  	asrs	r1, r0, #32
│ │  	b.n	27033c <uniffi_pbcli_checksum_method_api_base@@Base+0x103ab8>
│ │  	ldr	r0, [pc, #192]	@ (2702e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x103a5c>)
│ │  	ldmia.w	sp!, {r0, r3, r5, r8, r9, ip, sp, pc}
│ │  			@ <UNDEFINED> instruction: 0xea028830
│ │ -	ldmia.w	sp!, {r1, r4, r5, r6, r7, r8, fp, ip, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffe259b2
│ │ -			@ <UNDEFINED> instruction: 0xffe25986
│ │ +	ldmia.w	sp!, {r0, r3, r4, r9, fp, ip, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffe259d9
│ │ +			@ <UNDEFINED> instruction: 0xffe259ad
│ │  	vmlal.u32	q10, d2, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	27057e <uniffi_pbcli_checksum_method_api_base@@Base+0x103cfa>
│ │  	asrs	r0, r4, #32
│ │  	b.n	26fd80 <uniffi_pbcli_checksum_method_api_base@@Base+0x1034fc>
│ │  	movs	r0, r3
│ │  	b.n	270986 <uniffi_pbcli_checksum_method_api_base@@Base+0x104102>
│ │ @@ -486353,15 +486353,15 @@
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	asrs	r1, r0, #32
│ │  	asrs	r0, r4, #14
│ │  	asrs	r4, r2, #32
│ │  	asrs	r0, r0, #22
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r4, r6, r8, fp, ip, lr}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r5, r6, r8, fp, ip, lr}
│ │  	vqrdmulh.s32	q8, q1, d3[0]
│ │  	and.w	ip, r0, r4, lsr #1
│ │  	and.w	pc, r0, r0, ror #19
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	270794 <uniffi_pbcli_checksum_method_api_base@@Base+0x103f10>
│ │  	beq.n	2701a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x103920>
│ │  	b.n	270718 <uniffi_pbcli_checksum_method_api_base@@Base+0x103e94>
│ │ @@ -486852,24 +486852,24 @@
│ │  	b.n	270e5e <uniffi_pbcli_checksum_method_api_base@@Base+0x1045da>
│ │  	movs	r1, r1
│ │  	b.n	2709e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x10415e>
│ │  	beq.n	2706dc <uniffi_pbcli_checksum_method_api_base@@Base+0x103e58>
│ │  	b.n	270b3c <uniffi_pbcli_checksum_method_api_base@@Base+0x1042b8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r1, r4, r8, r9, sl, fp, ip, sp, lr, pc}
│ │ -	vmull.u32	q8, d16, d6[0]
│ │ -	vmlal.u32	q12, d3, d14[1]
│ │ +	vmull.u32	q8, d16, d13[1]
│ │ +	vrshr.u64	d24, d5, #29
│ │  			@ <UNDEFINED> instruction: 0xffe22aff
│ │  	vsubw.u32	<illegal reg q11.5>, q9, d0
│ │ -	vmull.p64	<illegal reg q14.5>, d1, d29
│ │ -	vmul.i32	<illegal reg q9.5>, q9, d13[1]
│ │ +	vcvt.f32.u32	<illegal reg q14.5>, q2, #31
│ │ +	vqshrn.u64	d19, q2, #30
│ │  	vrsra.u64	<illegal reg q8.5>, <illegal reg q0.5>, #29
│ │  	vsubl.u32	<illegal reg q8.5>, d17, d14
│ │  	vcvt.u16.f16	d31, d15, #30
│ │ -	vqrdmlsh.s32	q15, q0, d6[0]
│ │ +	vqrdmlsh.s32	q15, q0, d13[1]
│ │  			@ <UNDEFINED> instruction: 0xffe2fbb7
│ │  	vaddl.u32	<illegal reg q9.5>, d0, d1
│ │  	b.n	270a1e <uniffi_pbcli_checksum_method_api_base@@Base+0x10419a>
│ │  	asrs	r2, r0, #32
│ │  	b.n	270a22 <uniffi_pbcli_checksum_method_api_base@@Base+0x10419e>
│ │  	movs	r0, #3
│ │  	b.n	270a26 <uniffi_pbcli_checksum_method_api_base@@Base+0x1041a2>
│ │ @@ -487289,19 +487289,19 @@
│ │  	str	r0, [r0, r0]
│ │  	mvns	r0, r4
│ │  	movs	r5, r0
│ │  	b.n	270daa <uniffi_pbcli_checksum_method_api_base@@Base+0x104526>
│ │  	beq.n	270aa4 <uniffi_pbcli_checksum_method_api_base@@Base+0x104220>
│ │  	b.n	270f04 <uniffi_pbcli_checksum_method_api_base@@Base+0x104680>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r2, r3, r8, sl, ip, sp}
│ │ +	ldmia.w	sp!, {r0, r1, r4, r5, r8, sl, ip, sp}
│ │  	vmlal.u32	q14, d3, d19
│ │ -	vrsubhn.i64	d22, q8, q14
│ │ -	vsli.64	q11, q14, #34	@ 0x22
│ │ -	vqshlu.s32	d22, d28, #2
│ │ +	vqshlu.s64	q11, <illegal reg q1.5>, #32
│ │ +	vrsubhn.i64	d22, q1, <illegal reg q9.5>
│ │ +	vmlsl.u32	q11, d2, d3[1]
│ │  	vqshl.u32	q11, q2, #2
│ │  			@ <UNDEFINED> instruction: 0xffe39f27
│ │  			@ <UNDEFINED> instruction: 0xffe19edb
│ │  	vcvt.f16.u16	d20, d0, #31
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	270fb4 <uniffi_pbcli_checksum_method_api_base@@Base+0x104730>
│ │  	beq.n	270acc <uniffi_pbcli_checksum_method_api_base@@Base+0x104248>
│ │ @@ -487656,17 +487656,17 @@
│ │  	add.w	r0, r1, r0, lsl #28
│ │  	b.n	271546 <uniffi_pbcli_checksum_method_api_base@@Base+0x104cc2>
│ │  	movs	r7, r0
│ │  	b.n	2710ca <uniffi_pbcli_checksum_method_api_base@@Base+0x104846>
│ │  	beq.n	270dc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x104540>
│ │  	b.n	271224 <uniffi_pbcli_checksum_method_api_base@@Base+0x1049a0>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r4, r6, r7, sl, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r4, r5, r6, r7, sl, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffe20bf5
│ │ -	vrshr.u64	q11, q4, #31
│ │ +	vrshr.u64	q11, <illegal reg q15.5>, #31
│ │  			@ <UNDEFINED> instruction: 0xffe209fd
│ │  	vcvt.f16.u16	d20, d0, #31
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2712c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x104a40>
│ │  	beq.n	270dcc <uniffi_pbcli_checksum_method_api_base@@Base+0x104548>
│ │  	b.n	271248 <uniffi_pbcli_checksum_method_api_base@@Base+0x1049c4>
│ │  	ands	r3, r0
│ │ @@ -487896,15 +487896,15 @@
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r0, r1}
│ │  	b.n	2716e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x104e5e>
│ │  	beq.n	270fb4 <uniffi_pbcli_checksum_method_api_base@@Base+0x104730>
│ │  	b.n	27143c <uniffi_pbcli_checksum_method_api_base@@Base+0x104bb8>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r4, r5, r6, r7, pc}
│ │ -	vqrdmlah.s32	q12, <illegal reg q0.5>, d0[1]
│ │ +	vmull.p64	q12, d17, d7
│ │  	vshr.u32	q11, q8, #30
│ │  	vsra.u32	d21, d1, #29
│ │  	vqrdmlsh.s32	q13, <illegal reg q0.5>, d5[0]
│ │  			@ <UNDEFINED> instruction: 0xffe1ad0f
│ │  	vmlal.u32	q10, d1, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	27130a <uniffi_pbcli_checksum_method_api_base@@Base+0x104a86>
│ │ @@ -488719,44 +488719,44 @@
│ │  	b.n	271ca8 <uniffi_pbcli_checksum_method_api_base@@Base+0x105424>
│ │  	strb	r6, [r3, #0]
│ │  	b.n	271dea <uniffi_pbcli_checksum_method_api_base@@Base+0x105566>
│ │  	movs	r0, r0
│ │  	b.n	271d50 <uniffi_pbcli_checksum_method_api_base@@Base+0x1054cc>
│ │  	vpmin.u<illegal width 64>	<illegal reg q8.5>, <illegal reg q13.5>, <illegal reg q15.5>
│ │  			@ <UNDEFINED> instruction: 0xffcaeaff
│ │ -			@ <UNDEFINED> instruction: 0xb8c7
│ │ +			@ <UNDEFINED> instruction: 0xb8ee
│ │  	vsri.64	q8, q2, #30
│ │ -	vmul.i32	<illegal reg q13.5>, q9, d15[1]
│ │ +	vqshrn.u64	d27, q3, #30
│ │  	vsri.64	q8, q14, #30
│ │ -			@ <UNDEFINED> instruction: 0xffe2b89f
│ │ +	vmul.i32	<illegal reg q13.5>, q9, d6[0]
│ │  	vraddhn.i64	d16, q9, q14
│ │ -	vqshrn.u64	d27, <illegal reg q7.5>, #30
│ │ +	vmul.f32	<illegal reg q13.5>, q1, d6[0]
│ │  	vabal.u32	q8, d2, d28
│ │ -	vqshrun.s64	d27, <illegal reg q15.5>, #30
│ │ +	vmul.i32	<illegal reg q13.5>, q1, d6[1]
│ │  	vmls.i32	q8, q1, d12[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe2fbe2
│ │ -	vsli.64	<illegal reg q13.5>, <illegal reg q7.5>, #34	@ 0x22
│ │ +	vmull.u32	<illegal reg q15.5>, d2, d9
│ │ +	vrsubhn.i64	d27, q1, q3
│ │  	vmla.f32	q8, q9, d12[1]
│ │  	vmlsl.u32	q12, d2, d15
│ │ -	vsri.32	<illegal reg q13.5>, <illegal reg q3.5>, #32
│ │ +	vsri.32	<illegal reg q13.5>, q15, #32
│ │  	vmla.i32	q8, q1, d4[1]
│ │ -	vabal.u32	<illegal reg q13.5>, d2, d3
│ │ +	vabal.u32	<illegal reg q13.5>, d2, d26
│ │  	vsra.u32	d16, d0, #30
│ │  	vmlal.u32	q8, d2, d8[0]
│ │  	movs	r0, r0
│ │  	lsls	r0, r2, #9
│ │  	movs	r0, r0
│ │  	lsls	r4, r3, #9
│ │  	movs	r0, r0
│ │  	lsls	r4, r2, #12
│ │  	movs	r0, r0
│ │  	lsls	r4, r5, #12
│ │  	movs	r0, r0
│ │ -	cbz	r3, 27178c <uniffi_pbcli_checksum_method_api_base@@Base+0x104f08>
│ │ -	vsli.64	d27, d7, #34	@ 0x22
│ │ +	push	{r1, r3}
│ │ +	vsli.64	d27, d30, #34	@ 0x22
│ │  	vaddw.u32	q8, q9, d20
│ │  			@ <UNDEFINED> instruction: 0xffe24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	271c40 <uniffi_pbcli_checksum_method_api_base@@Base+0x1053bc>
│ │  	beq.n	271730 <uniffi_pbcli_checksum_method_api_base@@Base+0x104eac>
│ │  	b.n	271bc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x105340>
│ │  	movs	r0, r0
│ │ @@ -489918,15 +489918,15 @@
│ │  	add.w	r0, r0, r0
│ │  	b.n	271c1e <uniffi_pbcli_checksum_method_api_base@@Base+0x10539a>
│ │  	movs	r4, r0
│ │  	b.n	27245a <uniffi_pbcli_checksum_method_api_base@@Base+0x105bd6>
│ │  	beq.n	27214c <uniffi_pbcli_checksum_method_api_base@@Base+0x1058c8>
│ │  	b.n	2725b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x105d30>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r3, r6, r7, sl, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r5, r6, r7, sl, sp, lr}
│ │  	vmla.i32	q15, q9, d9[0]
│ │  			@ <UNDEFINED> instruction: 0xffe048f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	27264c <uniffi_pbcli_checksum_method_api_base@@Base+0x105dc8>
│ │  	beq.n	272194 <uniffi_pbcli_checksum_method_api_base@@Base+0x105910>
│ │  	b.n	2725d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x105d4c>
│ │  	ands	r0, r0
│ │ @@ -490435,27 +490435,27 @@
│ │  	b.n	272c34 <uniffi_pbcli_checksum_method_api_base@@Base+0x1063b0>
│ │  	movs	r1, r0
│ │  	stmia	r3!, {}
│ │  	beq.n	2725d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x105d4c>
│ │  	b.n	272a30 <uniffi_pbcli_checksum_method_api_base@@Base+0x1061ac>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r2, r4, r5, r6, r9, ip, sp, lr, pc}
│ │ -	vqrdmlsh.s32	q14, <illegal reg q8.5>, d14[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe1cff5
│ │  	vsubl.u32	<illegal reg q15.5>, d18, d8
│ │  	vsubl.u32	<illegal reg q12.5>, d0, d1
│ │ -	vqrdmlsh.s32	q14, q0, d10[1]
│ │ -	vcvt.u16.f16	q9, <illegal reg q12.5>, #30
│ │ -	vaddl.u32	q11, d3, d30
│ │ +			@ <UNDEFINED> instruction: 0xffe0cf91
│ │ +			@ <UNDEFINED> instruction: 0xffe22da0
│ │ +	vshr.u32	q11, <illegal reg q2.5>, #29
│ │  			@ <UNDEFINED> instruction: 0xffe24b24
│ │ -	vaddl.u32	<illegal reg q14.5>, d19, d18
│ │ +	vmla.i32	<illegal reg q14.5>, <illegal reg q9.5>, d9[0]
│ │  	vrsra.u32	<illegal reg q15.5>, q6, #30
│ │ -	vrsubhn.i64	d26, q0, <illegal reg q6.5>
│ │ -	vmla.i32	<illegal reg q14.5>, q1, d6[0]
│ │ +	vqshlu.s32	d26, d20, #0
│ │ +	vmla.i32	<illegal reg q14.5>, q1, d13[1]
│ │  	vmull.u32	q10, d2, d16
│ │ -	vqrdmlah.s32	q9, <illegal reg q1.5>, d13[0]
│ │ +	vcvt.f32.u32	q9, q10, #29
│ │  			@ <UNDEFINED> instruction: 0xffe309bd
│ │  	vmlal.u32	q10, d2, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	272922 <uniffi_pbcli_checksum_method_api_base@@Base+0x10609e>
│ │  	beq.n	2725f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x105d70>
│ │  	b.n	272a80 <uniffi_pbcli_checksum_method_api_base@@Base+0x1061fc>
│ │  	adds	r0, #0
│ │ @@ -491813,20 +491813,20 @@
│ │  			@ <UNDEFINED> instruction: 0xfffa8aff
│ │  	movs	r0, r0
│ │  	b.n	27381e <uniffi_pbcli_checksum_method_api_base@@Base+0x106f9a>
│ │  			@ <UNDEFINED> instruction: 0xffe24aff
│ │  	strh	r6, [r1, #0]
│ │  	b.n	273292 <uniffi_pbcli_checksum_method_api_base@@Base+0x106a0e>
│ │  			@ <UNDEFINED> instruction: 0xffc7eaff
│ │ -	bl	fff0e14c <uniffi_pbcli_checksum_method_api_base@@Base+0xffda18c8>
│ │ -	strh	r0, [r4, #14]
│ │ -			@ <UNDEFINED> instruction: 0xffe2f362
│ │ -	vaddl.u32	q12, d18, d24
│ │ -	vsubw.u32	<illegal reg q15.5>, q9, d30
│ │ -	vshr.u64	q12, q10, #30
│ │ +	bl	fff3514c <uniffi_pbcli_checksum_method_api_base@@Base+0xffdc88c8>
│ │ +	strh	r7, [r0, #16]
│ │ +	vsubw.u32	<illegal reg q15.5>, q9, d9
│ │ +	vmla.i32	q12, q9, d15[0]
│ │ +	vrsra.u64	<illegal reg q15.5>, <illegal reg q2.5>, #30
│ │ +	vsra.u32	d24, d11, #30
│ │  			@ <UNDEFINED> instruction: 0xffe248f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2736c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x106e3c>
│ │  	str	r0, [r1, r0]
│ │  	b.n	272ce0 <uniffi_pbcli_checksum_method_api_base@@Base+0x10645c>
│ │  	movs	r0, r0
│ │  	b.n	273850 <uniffi_pbcli_checksum_method_api_base@@Base+0x106fcc>
│ │ @@ -492192,17 +492192,17 @@
│ │  	b.n	273bfa <uniffi_pbcli_checksum_method_api_base@@Base+0x107376>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	273c02 <uniffi_pbcli_checksum_method_api_base@@Base+0x10737e>
│ │  	strb	r0, [r1, #0]
│ │  	b.n	272fce <uniffi_pbcli_checksum_method_api_base@@Base+0x10674a>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r7, ip, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffe21ed2
│ │ -	vaddl.u32	<illegal reg q15.5>, d3, d10
│ │ +	ldmia.w	sp!, {r0, r3, r5, r7, ip, sp, lr, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffe21ef9
│ │ +	vshr.u32	d31, d17, #29
│ │  	vcvt.f16.u16	q10, q8, #30
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2739f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x107174>
│ │  	movs	r0, r0
│ │  	b.n	273b82 <uniffi_pbcli_checksum_method_api_base@@Base+0x1072fe>
│ │  	movs	r5, r4
│ │  	lsrs	r0, r0, #8
│ │ @@ -492275,17 +492275,17 @@
│ │  	b.n	273b76 <uniffi_pbcli_checksum_method_api_base@@Base+0x1072f2>
│ │  	asrs	r1, r0, #32
│ │  	b.n	273698 <uniffi_pbcli_checksum_method_api_base@@Base+0x106e14>
│ │  	add	r6, pc, #332	@ (adr r6, 2736c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x106e44>)
│ │  	add.w	r0, r2, r0
│ │  	b.n	273cc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x10743e>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r2, r7, r8, r9, sl, fp, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffe2ef22
│ │ -			@ <UNDEFINED> instruction: 0xffe2ef06
│ │ +	ldmia.w	sp!, {r0, r2, r3, r5, r7, r8, r9, sl, fp, sp, lr, pc}
│ │ +	vqrdmlsh.s32	q15, q1, d9[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe2ef2d
│ │  	vmlal.u32	q10, d2, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2738da <uniffi_pbcli_checksum_method_api_base@@Base+0x107056>
│ │  	asrs	r0, r4, #32
│ │  	b.n	2730dc <uniffi_pbcli_checksum_method_api_base@@Base+0x106858>
│ │  	movs	r0, r2
│ │  	b.n	273ce2 <uniffi_pbcli_checksum_method_api_base@@Base+0x10745e>
│ │ @@ -492299,15 +492299,15 @@
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	asrs	r4, r0, #32
│ │  	asrs	r0, r4, #14
│ │  	asrs	r4, r0, #32
│ │  	asrs	r0, r0, #22
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r4, r6, r7, r9, sl, fp, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r5, r6, r7, r9, sl, fp, sp, lr, pc}
│ │  	vqshrun.s64	d20, q8, #30
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	273ae8 <uniffi_pbcli_checksum_method_api_base@@Base+0x107264>
│ │  	movs	r0, r0
│ │  	b.n	273c72 <uniffi_pbcli_checksum_method_api_base@@Base+0x1073ee>
│ │  	movs	r1, r2
│ │  	lsrs	r0, r0, #8
│ │ @@ -492341,16 +492341,16 @@
│ │  	movs	r1, #113	@ 0x71
│ │  	b.n	273c12 <uniffi_pbcli_checksum_method_api_base@@Base+0x10738e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	273734 <uniffi_pbcli_checksum_method_api_base@@Base+0x106eb0>
│ │  	ldr	r0, [pc, #192]	@ (2736d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x106e54>)
│ │  	ldmia.w	sp!, {r0, r1, r3, r5, r9, sl, sp, pc}
│ │  			@ <UNDEFINED> instruction: 0xea028830
│ │ -	ldmia.w	sp!, {r1, r2, r7, r9, sl, fp, sp, lr, pc}
│ │ -	vqrdmlah.s32	q15, q1, d10[1]
│ │ +	ldmia.w	sp!, {r0, r2, r3, r5, r7, r9, sl, fp, sp, lr, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffe2ee91
│ │  	vcvt.f16.u16	q10, q8, #30
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	273b4c <uniffi_pbcli_checksum_method_api_base@@Base+0x1072c8>
│ │  	str	r1, [r0, r0]
│ │  	b.n	273976 <uniffi_pbcli_checksum_method_api_base@@Base+0x1070f2>
│ │  	asrs	r0, r4, #32
│ │  	b.n	273178 <uniffi_pbcli_checksum_method_api_base@@Base+0x1068f4>
│ │ @@ -492366,15 +492366,15 @@
│ │  	b.n	273c4e <uniffi_pbcli_checksum_method_api_base@@Base+0x1073ca>
│ │  	add	r6, pc, #120	@ (adr r6, 2736c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x106e44>)
│ │  	add.w	r0, r2, r0, lsl #16
│ │  	b.n	273162 <uniffi_pbcli_checksum_method_api_base@@Base+0x1068de>
│ │  	str	r0, [r1, r0]
│ │  	b.n	273166 <uniffi_pbcli_checksum_method_api_base@@Base+0x1068e2>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r3, r4, r5, r9, sl, fp, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r5, r6, r9, sl, fp, sp, lr, pc}
│ │  	vcvt.f16.u16	d20, d0, #30
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	273b84 <uniffi_pbcli_checksum_method_api_base@@Base+0x107300>
│ │  	asrs	r0, r4, #32
│ │  	b.n	2731ac <uniffi_pbcli_checksum_method_api_base@@Base+0x106928>
│ │  	ands	r0, r0
│ │  	b.n	2739b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x10712e>
│ │ @@ -492388,15 +492388,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	273d26 <uniffi_pbcli_checksum_method_api_base@@Base+0x1074a2>
│ │  	ands	r4, r0
│ │  	asrs	r0, r0, #22
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r1, r9, sl, fp, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r3, r5, r9, sl, fp, sp, lr, pc}
│ │  	vqshrun.s64	d20, q8, #30
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	273bb8 <uniffi_pbcli_checksum_method_api_base@@Base+0x107334>
│ │  	movs	r0, r0
│ │  	b.n	273d42 <uniffi_pbcli_checksum_method_api_base@@Base+0x1074be>
│ │  	movs	r1, r2
│ │  	lsrs	r0, r0, #8
│ │ @@ -492430,16 +492430,16 @@
│ │  	movs	r1, #113	@ 0x71
│ │  	b.n	273ce2 <uniffi_pbcli_checksum_method_api_base@@Base+0x10745e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	273804 <uniffi_pbcli_checksum_method_api_base@@Base+0x106f80>
│ │  	ldr	r0, [pc, #192]	@ (2737a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x106f24>)
│ │  	ldmia.w	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, sl, sp, pc}
│ │  			@ <UNDEFINED> instruction: 0xea028830
│ │ -	ldmia.w	sp!, {r1, r2, r4, r5, r7, r8, sl, fp, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffe2ed9a
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r6, r7, r8, sl, fp, sp, lr, pc}
│ │ +	vqrdmulh.s32	q15, q9, d1[0]
│ │  	vqshrun.s64	d20, q8, #30
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	273c1c <uniffi_pbcli_checksum_method_api_base@@Base+0x107398>
│ │  	movs	r0, r0
│ │  	b.n	273da6 <uniffi_pbcli_checksum_method_api_base@@Base+0x107522>
│ │  	movs	r1, r3
│ │  	lsrs	r0, r0, #8
│ │ @@ -492488,16 +492488,16 @@
│ │  	movs	r1, #113	@ 0x71
│ │  	b.n	273d66 <uniffi_pbcli_checksum_method_api_base@@Base+0x1074e2>
│ │  	asrs	r1, r0, #32
│ │  	b.n	273888 <uniffi_pbcli_checksum_method_api_base@@Base+0x107004>
│ │  	ldr	r0, [pc, #192]	@ (27382c <uniffi_pbcli_checksum_method_api_base@@Base+0x106fa8>)
│ │  	ldmia.w	sp!, {r1, r2, r4, r6, r7, r8, sl, sp, pc}
│ │  			@ <UNDEFINED> instruction: 0xea028830
│ │ -	ldmia.w	sp!, {r1, r4, r5, r8, sl, fp, sp, lr, pc}
│ │ -	vcvt.u16.f16	d30, d6, #30
│ │ +	ldmia.w	sp!, {r0, r3, r4, r6, r8, sl, fp, sp, lr, pc}
│ │ +	vcvt.u16.f16	d30, d29, #30
│ │  	vqshrun.s64	d20, q8, #30
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	273ca0 <uniffi_pbcli_checksum_method_api_base@@Base+0x10741c>
│ │  	ands	r0, r0
│ │  	b.n	273aca <uniffi_pbcli_checksum_method_api_base@@Base+0x107246>
│ │  	movs	r0, r0
│ │  	b.n	2732b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x106a2c>
│ │ @@ -494013,51 +494013,51 @@
│ │  	b.n	274b7e <uniffi_pbcli_checksum_method_api_base@@Base+0x1082fa>
│ │  			@ <UNDEFINED> instruction: 0xffdaeaff
│ │  	add	r0, pc, #0	@ (adr r0, 274444 <uniffi_pbcli_checksum_method_api_base@@Base+0x107bc0>)
│ │  	b.n	274b86 <uniffi_pbcli_checksum_method_api_base@@Base+0x108302>
│ │  	str	r4, [r0, #0]
│ │  	b.n	27478a <uniffi_pbcli_checksum_method_api_base@@Base+0x107f06>
│ │  			@ <UNDEFINED> instruction: 0xffd5eaff
│ │ -	lsls	r6, r3, #17
│ │ -	vqshrn.u64	d23, q11, #29
│ │ +	lsls	r5, r0, #18
│ │ +	vqrshrn.u64	d23, <illegal reg q6.5>, #29
│ │  	vcvt.u32.f32	d16, d11, #30
│ │  	vmls.f32	q11, <illegal reg q0.5>, d3[0]
│ │  	vsli.32	<illegal reg q15.5>, q14, #0
│ │  	vsri.32	d24, d7, #31
│ │  	vabal.u32	q9, d1, d3
│ │  	vsri.64	q9, <illegal reg q13.5>, #31
│ │  	vqrdmulh.s32	<illegal reg q14.5>, <illegal reg q0.5>, d5[0]
│ │  	vqshrn.u64	d19, q10, #32
│ │  			@ <UNDEFINED> instruction: 0xffe1174c
│ │  	movs	r3, r4
│ │  	strh	r4, [r5, #28]
│ │ -	vmlsl.u32	q10, d1, d6
│ │ -	vshr.u32	q15, <illegal reg q10.5>, #30
│ │ -	vmlsl.u32	q10, d2, d30
│ │ +	vmlsl.u32	q10, d1, d29
│ │ +	vshr.u64	d30, d12, #30
│ │ +			@ <UNDEFINED> instruction: 0xffe24a55
│ │  	vmlsl.u32	<illegal reg q14.5>, d2, d18
│ │ -			@ <UNDEFINED> instruction: 0xffe1ff9c
│ │ -	vmull.u32	<illegal reg q15.5>, d2, d0
│ │ +	vqrdmlsh.s32	<illegal reg q15.5>, <illegal reg q8.5>, d3[0]
│ │ +	vmull.u32	<illegal reg q15.5>, d2, d23
│ │  	vqrdmlah.s32	<illegal reg q13.5>, q9, d2[1]
│ │  	vshr.u32	q12, q11, #31
│ │  			@ <UNDEFINED> instruction: 0xffe1c3e8
│ │  	vmls.i32	<illegal reg q14.5>, q0, d12[1]
│ │ -	vmlsl.u32	<illegal reg q15.5>, d0, d0
│ │ -	vsli.64	d20, d2, #34	@ 0x22
│ │ -	vmull.p64	<illegal reg q15.5>, d2, d28
│ │ +	vmlsl.u32	<illegal reg q15.5>, d0, d23
│ │ +	vsli.64	d20, d25, #34	@ 0x22
│ │ +	vcvt.f32.u32	<illegal reg q15.5>, <illegal reg q1.5>, #30
│ │  	vsra.u64	d31, d15, #30
│ │  	vqshlu.s32	d20, d27, #0
│ │  	vrsubhn.i64	d29, q0, q14
│ │ -			@ <UNDEFINED> instruction: 0xffe0fba8
│ │ +			@ <UNDEFINED> instruction: 0xffe0fbcf
│ │  	vcvt.u32.f32	d30, d15, #30
│ │  	vrsra.u64	d20, d31, #32
│ │ -	vmovl.u32	<illegal reg q8.5>, d19
│ │ +			@ <UNDEFINED> instruction: 0xffe01a5a
│ │  	vaddl.u32	<illegal reg q12.5>, d18, d30
│ │ -	vmlsl.u32	q10, d1, d6[1]
│ │ +	vrsubhn.i64	d20, <illegal reg q8.5>, <illegal reg q6.5>
│ │  	vsli.32	q11, q10, #2
│ │ -	vrshr.u64	q10, q3, #31
│ │ +	vrshr.u64	q10, <illegal reg q14.5>, #31
│ │  			@ <UNDEFINED> instruction: 0xffe27a97
│ │  	vmlal.u32	q10, d1, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	27482a <uniffi_pbcli_checksum_method_api_base@@Base+0x107fa6>
│ │  	beq.n	27450c <uniffi_pbcli_checksum_method_api_base@@Base+0x107c88>
│ │  	b.n	274988 <uniffi_pbcli_checksum_method_api_base@@Base+0x108104>
│ │  	asrs	r4, r0, #32
│ │ @@ -494287,15 +494287,15 @@
│ │  	ldrh	r2, [r4, #18]
│ │  	add.w	r0, r1, r4
│ │  	b.n	274a32 <uniffi_pbcli_checksum_method_api_base@@Base+0x1081ae>
│ │  	beq.n	274704 <uniffi_pbcli_checksum_method_api_base@@Base+0x107e80>
│ │  	b.n	274b8c <uniffi_pbcli_checksum_method_api_base@@Base+0x108308>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r1, r6, r9, sl, fp, ip, sp}
│ │ -			@ <UNDEFINED> instruction: 0xffe0ddd9
│ │ +	vmull.p64	<illegal reg q14.5>, d0, d0
│ │  	vcvt.f16.u16	d20, d0, #30
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	274c24 <uniffi_pbcli_checksum_method_api_base@@Base+0x1083a0>
│ │  	beq.n	27472c <uniffi_pbcli_checksum_method_api_base@@Base+0x107ea8>
│ │  	b.n	274ba8 <uniffi_pbcli_checksum_method_api_base@@Base+0x108324>
│ │  	ands	r0, r0
│ │  	b.n	274232 <uniffi_pbcli_checksum_method_api_base@@Base+0x1079ae>
│ │ @@ -494342,15 +494342,15 @@
│ │  	ldrh	r2, [r0, #18]
│ │  	add.w	r0, r1, r4
│ │  	b.n	274ab2 <uniffi_pbcli_checksum_method_api_base@@Base+0x10822e>
│ │  	beq.n	274784 <uniffi_pbcli_checksum_method_api_base@@Base+0x107f00>
│ │  	b.n	274c0c <uniffi_pbcli_checksum_method_api_base@@Base+0x108388>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r1, r6, r7, r8, sl, fp, ip, sp}
│ │ -	vqshlu.s64	d28, d15, #32
│ │ +	vmlsl.u32	q14, d16, d6[0]
│ │  			@ <UNDEFINED> instruction: 0xffe24bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	274ca4 <uniffi_pbcli_checksum_method_api_base@@Base+0x108420>
│ │  	beq.n	27479c <uniffi_pbcli_checksum_method_api_base@@Base+0x107f18>
│ │  	b.n	274c28 <uniffi_pbcli_checksum_method_api_base@@Base+0x1083a4>
│ │  	ands	r1, r0
│ │  	b.n	274ad2 <uniffi_pbcli_checksum_method_api_base@@Base+0x10824e>
│ │ @@ -494568,20 +494568,20 @@
│ │  	movs	r0, r1
│ │  	b.n	274ff6 <uniffi_pbcli_checksum_method_api_base@@Base+0x108772>
│ │  	asrs	r7, r0, #32
│ │  	b.n	274e7a <uniffi_pbcli_checksum_method_api_base@@Base+0x1085f6>
│ │  	movs	r5, r1
│ │  	b.n	2750be <uniffi_pbcli_checksum_method_api_base@@Base+0x10883a>
│ │  			@ <UNDEFINED> instruction: 0xffbeeaff
│ │ -	add	r5, sp, #804	@ 0x324
│ │ -	vraddhn.i64	d17, q1, <illegal reg q9.5>
│ │ -	vcvt.u16.f16	d26, d21, #30
│ │ -	vsubw.u32	<illegal reg q8.5>, q9, d15
│ │ -	vcvt.f16.u16	d26, d29, #30
│ │ -	vrshr.u64	d17, d7, #30
│ │ +	add	r5, sp, #960	@ 0x3c0
│ │ +	vmls.i32	<illegal reg q8.5>, q1, d10[0]
│ │ +	vcvt.u16.f16	q13, q6, #30
│ │ +	vrsra.u64	d17, d22, #30
│ │ +	vqdmulh.s32	q13, q1, d4[1]
│ │ +	vrshr.u64	d17, d30, #30
│ │  			@ <UNDEFINED> instruction: 0xffe24bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	274ebc <uniffi_pbcli_checksum_method_api_base@@Base+0x108638>
│ │  	beq.n	2749b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x108130>
│ │  	b.n	274e40 <uniffi_pbcli_checksum_method_api_base@@Base+0x1085bc>
│ │  	ands	r0, r1
│ │  	b.n	2744e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x107c5c>
│ │ @@ -495008,15 +495008,15 @@
│ │  	b.n	275492 <uniffi_pbcli_checksum_method_api_base@@Base+0x108c0e>
│ │  	ands	r0, r0
│ │  	b.n	275496 <uniffi_pbcli_checksum_method_api_base@@Base+0x108c12>
│ │  	ldrh	r7, [r0, #6]
│ │  			@ <UNDEFINED> instruction: 0xeb01ffef
│ │  			@ <UNDEFINED> instruction: 0xeaff8694
│ │  	movs	r6, r4
│ │ -	add	r0, sp, #404	@ 0x194
│ │ +	add	r0, sp, #560	@ 0x230
│ │  	vcvt.f16.u16	d25, d31, #30
│ │  	vmlsl.u32	q12, d0, d0[0]
│ │  	movs	r6, r4
│ │  	ldr	r0, [pc, #0]	@ (274d70 <uniffi_pbcli_checksum_method_api_base@@Base+0x1084ec>)
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2750b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x108832>
│ │  	beq.n	274d88 <uniffi_pbcli_checksum_method_api_base@@Base+0x108504>
│ │ @@ -496737,15 +496737,15 @@
│ │  	vrshr.u64	d20, d0, #31
│ │  	vmul.i32	<illegal reg q11.5>, q8, d1[0]
│ │  	vraddhn.i64	d20, <illegal reg q8.5>, q14
│ │  	vqshlu.s64	<illegal reg q11.5>, <illegal reg q12.5>, #32
│ │  	vmlal.u32	q10, d17, d4[1]
│ │  	vabdl.u32	<illegal reg q11.5>, d0, d17
│ │  	vsubw.u32	q10, <illegal reg q0.5>, d12
│ │ -	vmul.f32	<illegal reg q12.5>, q8, d10[1]
│ │ +	vmovl.u32	<illegal reg q12.5>, d1
│ │  			@ <UNDEFINED> instruction: 0xffe2bbdb
│ │  	vmlal.u32	<illegal reg q11.5>, d16, d13
│ │  	vsri.32	q10, q12, #31
│ │  	vabdl.u32	<illegal reg q12.5>, d0, d0
│ │  	vqshl.u64	<illegal reg q11.5>, <illegal reg q8.5>, #33	@ 0x21
│ │  	vrsra.u64	q10, q6, #31
│ │  			@ <UNDEFINED> instruction: 0xffe04ff0
│ │ @@ -498055,31 +498055,31 @@
│ │  	movs	r4, r5
│ │  	b.n	276334 <uniffi_pbcli_checksum_method_api_base@@Base+0x109ab0>
│ │  	asrs	r1, r0, #32
│ │  	b.n	27691c <uniffi_pbcli_checksum_method_api_base@@Base+0x10a098>
│ │  	ldr	r1, [sp, #712]	@ 0x2c8
│ │  			@ <UNDEFINED> instruction: 0xeb02fe35
│ │  			@ <UNDEFINED> instruction: 0xeaff7351
│ │ -	vsubw.u32	<illegal reg q15.5>, <illegal reg q8.5>, d20
│ │ +			@ <UNDEFINED> instruction: 0xffe1f3cb
│ │  	vrsra.u32	d23, d1, #30
│ │ -			@ <UNDEFINED> instruction: 0xffe1f364
│ │ +	vsubw.u32	<illegal reg q15.5>, <illegal reg q8.5>, d11
│ │  	vrshr.u64	<illegal reg q11.5>, <illegal reg q6.5>, #30
│ │ -	vrsra.u32	d31, d16, #31
│ │ +	vrsra.u32	<illegal reg q15.5>, <illegal reg q3.5>, #31
│ │  	vqrdmlsh.s32	q11, q9, d5[1]
│ │ -	vshr.u32	d31, d24, #31
│ │ +	vshr.u32	<illegal reg q15.5>, <illegal reg q7.5>, #31
│ │  	vmla.f32	<illegal reg q11.5>, q9, d1[1]
│ │ -	vrshr.u32	d31, d20, #31
│ │ +	vrshr.u32	<illegal reg q15.5>, <illegal reg q5.5>, #31
│ │  	vmull.p64	q11, d2, d13
│ │  	vmla.f32	<illegal reg q13.5>, <illegal reg q8.5>, d7[0]
│ │  	vaddw.u32	<illegal reg q11.5>, <illegal reg q8.5>, d5
│ │ -	vsra.u64	<illegal reg q15.5>, q4, #31
│ │ +	vsra.u64	<illegal reg q15.5>, <illegal reg q15.5>, #31
│ │  	vshr.u32	d23, d1, #30
│ │ -	vmla.i32	<illegal reg q15.5>, <illegal reg q0.5>, d4[1]
│ │ +	vaddl.u32	<illegal reg q15.5>, d17, d11
│ │  			@ <UNDEFINED> instruction: 0xffe26b2d
│ │ -			@ <UNDEFINED> instruction: 0xffe1eb80
│ │ +			@ <UNDEFINED> instruction: 0xffe1eba7
│ │  	vcvt.u16.f16	d22, d9, #30
│ │  	vsra.u32	<illegal reg q8.5>, q5, #31
│ │  	vqdmulh.s32	q11, <illegal reg q0.5>, d9[1]
│ │  	vaddl.u32	<illegal reg q8.5>, d17, d26
│ │  			@ <UNDEFINED> instruction: 0xffe16c9d
│ │  	vshr.u64	<illegal reg q8.5>, q7, #31
│ │  	vqdmulh.s32	q11, <illegal reg q8.5>, d13[0]
│ │ @@ -498387,21 +498387,21 @@
│ │  	strh	r6, [r3, #8]
│ │  	add.w	r0, r1, sp
│ │  	b.n	27724e <uniffi_pbcli_checksum_method_api_base@@Base+0x10a9ca>
│ │  	asrs	r0, r5, #2
│ │  	b.n	277252 <uniffi_pbcli_checksum_method_api_base@@Base+0x10a9ce>
│ │  			@ <UNDEFINED> instruction: 0xffa4eaff
│ │  	ldr	r1, [r1, #24]
│ │ -			@ <UNDEFINED> instruction: 0xffe1d367
│ │ +	vsubw.u32	<illegal reg q14.5>, <illegal reg q8.5>, d14
│ │  			@ <UNDEFINED> instruction: 0xffe26905
│ │ -	vmlal.u32	<illegal reg q14.5>, d17, d3[1]
│ │ +	vsubw.u32	<illegal reg q14.5>, <illegal reg q0.5>, d10
│ │  	vqrshrun.s64	d22, <illegal reg q0.5>, #30
│ │ -	vsubl.u32	<illegal reg q14.5>, d1, d31
│ │ +	vrshr.u32	<illegal reg q14.5>, q3, #31
│ │  	vqshl.u64	d22, d13, #34	@ 0x22
│ │ -	vsra.u32	<illegal reg q14.5>, <illegal reg q13.5>, #31
│ │ +	vaddw.u32	<illegal reg q14.5>, <illegal reg q8.5>, d18
│ │  			@ <UNDEFINED> instruction: 0xffe24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	277058 <uniffi_pbcli_checksum_method_api_base@@Base+0x10a7d4>
│ │  	beq.n	276ba8 <uniffi_pbcli_checksum_method_api_base@@Base+0x10a324>
│ │  	b.n	276fdc <uniffi_pbcli_checksum_method_api_base@@Base+0x10a758>
│ │  	movs	r0, r0
│ │  	b.n	2771e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x10a962>
│ │ @@ -499210,23 +499210,23 @@
│ │  	movs	r0, #2
│ │  	b.n	277368 <uniffi_pbcli_checksum_method_api_base@@Base+0x10aae4>
│ │  	ldrb	r5, [r1, #29]
│ │  	add.w	r0, r1, r7, lsl #4
│ │  	b.n	277852 <uniffi_pbcli_checksum_method_api_base@@Base+0x10afce>
│ │  			@ <UNDEFINED> instruction: 0xffd1eaff
│ │  	str	r5, [r0, #8]
│ │ -	vcvt.f32.u32	d31, d26, #31
│ │ +	vqrdmlah.s32	<illegal reg q15.5>, <illegal reg q0.5>, d1[1]
│ │  	vaddw.u32	q11, <illegal reg q0.5>, d13
│ │ -	vqrdmlah.s32	<illegal reg q15.5>, <illegal reg q8.5>, d2[0]
│ │ +	vqrdmlah.s32	<illegal reg q15.5>, <illegal reg q8.5>, d9[1]
│ │  	vshr.u64	q11, <illegal reg q6.5>, #31
│ │ -			@ <UNDEFINED> instruction: 0xffe1fe92
│ │ +			@ <UNDEFINED> instruction: 0xffe1feb9
│ │  	vshr.u32	q11, <illegal reg q4.5>, #31
│ │  	vabal.u32	<illegal reg q14.5>, d17, d10
│ │  	vsra.u32	d22, d25, #32
│ │ -	vqrdmlah.s32	<illegal reg q15.5>, <illegal reg q8.5>, d14[1]
│ │ +	vcvt.u32.f32	d31, d5, #31
│ │  	vshr.u32	<illegal reg q15.5>, q0, #31
│ │  			@ <UNDEFINED> instruction: 0xeaff4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2777a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x10af20>
│ │  	movs	r0, r0
│ │  	b.n	27792e <uniffi_pbcli_checksum_method_api_base@@Base+0x10b0aa>
│ │  	movs	r1, r2
│ │ @@ -499503,16 +499503,16 @@
│ │  	strh	r0, [r0, #0]
│ │  	b.n	276fda <uniffi_pbcli_checksum_method_api_base@@Base+0x10a756>
│ │  			@ <UNDEFINED> instruction: 0xffd7eaff
│ │  	movs	r0, r0
│ │  	b.n	277b90 <uniffi_pbcli_checksum_method_api_base@@Base+0x10b30c>
│ │  			@ <UNDEFINED> instruction: 0xffc21aff
│ │  			@ <UNDEFINED> instruction: 0xffcceaff
│ │ -	ldmia	r0, {r0, r1, r4}
│ │ -	vmlal.u32	q14, d18, d11
│ │ +	ldmia	r0!, {r1, r3, r4, r5}
│ │ +			@ <UNDEFINED> instruction: 0xffe2c8b2
│ │  			@ <UNDEFINED> instruction: 0xffe22a98
│ │  			@ <UNDEFINED> instruction: 0xffe04ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	277a18 <uniffi_pbcli_checksum_method_api_base@@Base+0x10b194>
│ │  	beq.n	277508 <uniffi_pbcli_checksum_method_api_base@@Base+0x10ac84>
│ │  	b.n	27799c <uniffi_pbcli_checksum_method_api_base@@Base+0x10b118>
│ │  	str	r0, [r0, r0]
│ │ @@ -499644,15 +499644,15 @@
│ │  	and.w	r0, r0, r1, lsl #20
│ │  	b.n	277d4a <uniffi_pbcli_checksum_method_api_base@@Base+0x10b4c6>
│ │  	movs	r5, r0
│ │  	b.n	27794e <uniffi_pbcli_checksum_method_api_base@@Base+0x10b0ca>
│ │  	beq.n	277648 <uniffi_pbcli_checksum_method_api_base@@Base+0x10adc4>
│ │  	b.n	277aa8 <uniffi_pbcli_checksum_method_api_base@@Base+0x10b224>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r4, r8, r9, sl, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r4, r5, r8, r9, sl, lr, pc}
│ │  	vaddl.u32	q9, d2, d0
│ │  	b.n	27795e <uniffi_pbcli_checksum_method_api_base@@Base+0x10b0da>
│ │  	movs	r0, r0
│ │  	b.n	277d62 <uniffi_pbcli_checksum_method_api_base@@Base+0x10b4de>
│ │  	movs	r0, r0
│ │  	b.n	277cc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x10b444>
│ │  	movs	r4, r1
│ │ @@ -500285,17 +500285,17 @@
│ │  	str	r0, [r0, #0]
│ │  	b.n	277eba <uniffi_pbcli_checksum_method_api_base@@Base+0x10b636>
│ │  			@ <UNDEFINED> instruction: 0xff8aeaff
│ │  	str	r0, [r1, #0]
│ │  	b.n	2776bc <uniffi_pbcli_checksum_method_api_base@@Base+0x10ae38>
│ │  			@ <UNDEFINED> instruction: 0xff88eaff
│ │  	subs	r6, #200	@ 0xc8
│ │ -	vmul.f32	q11, q0, d4[0]
│ │ +	vmul.f32	q11, q0, d11[1]
│ │  	vcvt.u32.f32	d19, d0, #30
│ │ -			@ <UNDEFINED> instruction: 0xffe0698c
│ │ +			@ <UNDEFINED> instruction: 0xffe069b3
│ │  			@ <UNDEFINED> instruction: 0xffe24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2780b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x10b834>
│ │  	beq.n	277c18 <uniffi_pbcli_checksum_method_api_base@@Base+0x10b394>
│ │  	b.n	27803c <uniffi_pbcli_checksum_method_api_base@@Base+0x10b7b8>
│ │  	str	r0, [sp, #0]
│ │  	b.n	2776ca <uniffi_pbcli_checksum_method_api_base@@Base+0x10ae46>
│ │ @@ -502414,19 +502414,19 @@
│ │  	b.n	279112 <uniffi_pbcli_checksum_method_api_base@@Base+0x10c88e>
│ │  	beq.n	278e0c <uniffi_pbcli_checksum_method_api_base@@Base+0x10c588>
│ │  	b.n	27926c <uniffi_pbcli_checksum_method_api_base@@Base+0x10c9e8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {lr}
│ │  	b.n	27951e <uniffi_pbcli_checksum_method_api_base@@Base+0x10cc9a>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │ -	ldr	r5, [r1, #0]
│ │ -	vsubl.u32	q15, d18, d31
│ │ -			@ <UNDEFINED> instruction: 0xffe168bd
│ │ -			@ <UNDEFINED> instruction: 0xffe2698d
│ │ -	vqshrun.s64	d22, <illegal reg q10.5>, #30
│ │ +	ldr	r4, [r6, #0]
│ │ +	vrshr.u64	q15, q3, #30
│ │ +	vmul.i32	q11, <illegal reg q8.5>, d4[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe269b4
│ │ +	vqrshrun.s64	d22, q6, #30
│ │  	vmlal.u32	q10, d2, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	27913e <uniffi_pbcli_checksum_method_api_base@@Base+0x10c8ba>
│ │  	beq.n	278e10 <uniffi_pbcli_checksum_method_api_base@@Base+0x10c58c>
│ │  	b.n	27929c <uniffi_pbcli_checksum_method_api_base@@Base+0x10ca18>
│ │  	stmia	r0!, {r1}
│ │  	b.n	279146 <uniffi_pbcli_checksum_method_api_base@@Base+0x10c8c2>
│ │ @@ -502614,15 +502614,15 @@
│ │  	b.n	278ac0 <uniffi_pbcli_checksum_method_api_base@@Base+0x10c23c>
│ │  	movs	r1, r0
│ │  	b.n	279642 <uniffi_pbcli_checksum_method_api_base@@Base+0x10cdbe>
│ │  			@ <UNDEFINED> instruction: 0xffde1aff
│ │  	movs	r4, r2
│ │  	b.n	278acc <uniffi_pbcli_checksum_method_api_base@@Base+0x10c248>
│ │  			@ <UNDEFINED> instruction: 0xffddeaff
│ │ -	str	r1, [r6, #112]	@ 0x70
│ │ +	str	r0, [r3, #116]	@ 0x74
│ │  	vqshlu.s32	<illegal reg q13.5>, <illegal reg q7.5>, #2
│ │  	vcvt.f16.u16	q10, q8, #31
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2794d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x10cc54>
│ │  	str	r0, [r0, #0]
│ │  	b.n	279702 <uniffi_pbcli_checksum_method_api_base@@Base+0x10ce7e>
│ │  	movs	r0, r0
│ │ @@ -502782,15 +502782,15 @@
│ │  	b.n	279862 <uniffi_pbcli_checksum_method_api_base@@Base+0x10cfde>
│ │  	b.n	278bb8 <uniffi_pbcli_checksum_method_api_base@@Base+0x10c334>
│ │  	add.w	r0, r2, r0
│ │  	b.n	278c32 <uniffi_pbcli_checksum_method_api_base@@Base+0x10c3ae>
│ │  	movs	r1, r0
│ │  	b.n	27986e <uniffi_pbcli_checksum_method_api_base@@Base+0x10cfea>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r4, r8, sl, sp, lr}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r5, r8, sl, sp, lr}
│ │  	vaddl.u32	q8, d2, d4
│ │  	b.n	278c78 <uniffi_pbcli_checksum_method_api_base@@Base+0x10c3f4>
│ │  	movs	r0, r0
│ │  	b.n	27925c <uniffi_pbcli_checksum_method_api_base@@Base+0x10c9d8>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	stmia	r4!, {r2, r3, r4, r5, r7}
│ │  	movs	r2, r4
│ │ @@ -503157,15 +503157,15 @@
│ │  	b.n	279994 <uniffi_pbcli_checksum_method_api_base@@Base+0x10d110>
│ │  	subs	r4, r2, #6
│ │  	b.n	279796 <uniffi_pbcli_checksum_method_api_base@@Base+0x10cf12>
│ │  	movs	r0, r0
│ │  	b.n	279b3c <uniffi_pbcli_checksum_method_api_base@@Base+0x10d2b8>
│ │  			@ <UNDEFINED> instruction: 0xfffa1aff
│ │  			@ <UNDEFINED> instruction: 0xffc8eaff
│ │ -	bgt.n	27955a <uniffi_pbcli_checksum_method_api_base@@Base+0x10ccd6>
│ │ +	bgt.n	2793a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x10cb24>
│ │  	vqdmulh.s32	q11, <illegal reg q0.5>, d12[1]
│ │  	vaddl.u32	q8, d1, d0
│ │  	b.n	279b4e <uniffi_pbcli_checksum_method_api_base@@Base+0x10d2ca>
│ │  	movs	r0, r0
│ │  	asrs	r0, r2, #22
│ │  	movs	r0, r0
│ │  	asrs	r0, r2, #13
│ │ @@ -503233,15 +503233,15 @@
│ │  	asrs	r0, r0, #32
│ │  	b.n	27904a <uniffi_pbcli_checksum_method_api_base@@Base+0x10c7c6>
│ │  	asrs	r4, r0, #32
│ │  	b.n	27904e <uniffi_pbcli_checksum_method_api_base@@Base+0x10c7ca>
│ │  	movs	r0, r1
│ │  	b.n	279052 <uniffi_pbcli_checksum_method_api_base@@Base+0x10c7ce>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r6, r8, r9, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r5, r6, r8, r9, fp, ip, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffe148f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	279a74 <uniffi_pbcli_checksum_method_api_base@@Base+0x10d1f0>
│ │  	movs	r0, r0
│ │  	b.n	279bfe <uniffi_pbcli_checksum_method_api_base@@Base+0x10d37a>
│ │  	str	r1, [r0, #0]
│ │  	b.n	279ca2 <uniffi_pbcli_checksum_method_api_base@@Base+0x10d41e>
│ │ @@ -503309,16 +503309,16 @@
│ │  	ands	r4, r0
│ │  	b.n	2790fc <uniffi_pbcli_checksum_method_api_base@@Base+0x10c878>
│ │  	movs	r0, r1
│ │  	b.n	279100 <uniffi_pbcli_checksum_method_api_base@@Base+0x10c87c>
│ │  	movs	r6, r0
│ │  	b.n	279936 <uniffi_pbcli_checksum_method_api_base@@Base+0x10d0b2>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r1, r5, r6, r7, r9, fp, ip, lr, pc}
│ │ -	vmull.u32	<illegal reg q14.5>, d17, d3[0]
│ │ +	ldmia.w	sp!, {r1, r3, r8, r9, fp, ip, lr, pc}
│ │ +	vmull.u32	<illegal reg q14.5>, d17, d10[1]
│ │  	vcvt.f16.u16	q10, q8, #31
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	279b24 <uniffi_pbcli_checksum_method_api_base@@Base+0x10d2a0>
│ │  	movs	r0, r0
│ │  	b.n	279cb2 <uniffi_pbcli_checksum_method_api_base@@Base+0x10d42e>
│ │  	ands	r0, r0
│ │  	b.n	279952 <uniffi_pbcli_checksum_method_api_base@@Base+0x10d0ce>
│ │ @@ -503521,18 +503521,18 @@
│ │  	and.w	r0, r0, r0, lsl #24
│ │  	b.n	279f0a <uniffi_pbcli_checksum_method_api_base@@Base+0x10d686>
│ │  	movs	r6, r0
│ │  	b.n	279b0e <uniffi_pbcli_checksum_method_api_base@@Base+0x10d28a>
│ │  	beq.n	2797f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x10cf6c>
│ │  	b.n	279c68 <uniffi_pbcli_checksum_method_api_base@@Base+0x10d3e4>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, fp, ip, lr, pc}
│ │ -	vsli.32	d26, d10, #1
│ │ -	vmul.i32	<illegal reg q14.5>, q9, d3[1]
│ │ -	vsri.64	q13, q15, #31
│ │ +	ldmia.w	sp!, {r1, r2, r5, r8, fp, ip, lr, pc}
│ │ +	vmls.f32	q13, <illegal reg q0.5>, d1[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe2d90a
│ │ +	vabal.u32	q13, d1, d21
│ │  	vaddl.u32	q8, d2, d4
│ │  	b.n	279328 <uniffi_pbcli_checksum_method_api_base@@Base+0x10caa4>
│ │  	movs	r0, r0
│ │  	b.n	27990c <uniffi_pbcli_checksum_method_api_base@@Base+0x10d088>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	stmia	r0!, {r3, r6}
│ │  	movs	r2, r4
│ │ @@ -503846,15 +503846,15 @@
│ │  	b.n	2795b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x10cd30>
│ │  	movs	r4, r0
│ │  	b.n	279dee <uniffi_pbcli_checksum_method_api_base@@Base+0x10d56a>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {}
│ │  	b.n	27a1f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x10d972>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r4, r6, r7, r9, sl, pc}
│ │ +	ldmia.w	sp!, {r3, r4, r5, r6, r7, r9, sl, pc}
│ │  			@ <UNDEFINED> instruction: 0xffe2bdd0
│ │  	movs	r2, r4
│ │  	movs	r0, r0
│ │  	b.n	27a166 <uniffi_pbcli_checksum_method_api_base@@Base+0x10d8e2>
│ │  	movs	r2, r1
│ │  	lsrs	r0, r0, #8
│ │  	ldr	r4, [pc, #64]	@ (279b0c <uniffi_pbcli_checksum_method_api_base@@Base+0x10d288>)
│ │ @@ -504088,16 +504088,16 @@
│ │  	b.n	2797e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x10cf60>
│ │  	ldc2l	11, cr14, [ip, #-1020]!	@ 0xfffffc04	@ <UNPREDICTABLE>
│ │  	movs	r0, r0
│ │  	b.n	27a422 <uniffi_pbcli_checksum_method_api_base@@Base+0x10db9e>
│ │  	movs	r4, r0
│ │  	b.n	2797f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x10cf6c>
│ │  			@ <UNDEFINED> instruction: 0xffbbeaff
│ │ -	strh	r1, [r5, #42]	@ 0x2a
│ │ -	vsli.32	q12, <illegal reg q0.5>, #2
│ │ +	strh	r0, [r2, #44]	@ 0x2c
│ │ +	vsli.32	q12, q12, #2
│ │  	vcvt.f16.u16	d27, d4, #30
│ │  	movs	r2, r4
│ │  	pop	{r2, r3, r6}
│ │  	movs	r2, r4
│ │  	cbnz	r0, 279d5e <uniffi_pbcli_checksum_method_api_base@@Base+0x10d4da>
│ │  	movs	r2, r4
│ │  	movs	r4, r0
│ │ @@ -504737,15 +504737,15 @@
│ │  	movs	r4, r4
│ │  	ldmia.w	r1, {r0, r1, ip}
│ │  	b.n	27a5ce <uniffi_pbcli_checksum_method_api_base@@Base+0x10dd4a>
│ │  	adds	r0, #5
│ │  	b.n	27a5d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x10dd4e>
│ │  	ldr	r4, [pc, #128]	@ (27a314 <uniffi_pbcli_checksum_method_api_base@@Base+0x10da90>)
│ │  	ldmia.w	sp!, {r0, r1, r3, r4, r6, r7, r8, sl, fp}
│ │ -			@ <UNDEFINED> instruction: 0xea009a43
│ │ +			@ <UNDEFINED> instruction: 0xea009a6a
│ │  	vqdmulh.s32	q12, q1, d2[0]
│ │  			@ <UNDEFINED> instruction: 0xffe14bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	27a7c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x10df40>
│ │  	strb	r2, [r0, #0]
│ │  	b.n	27a5ee <uniffi_pbcli_checksum_method_api_base@@Base+0x10dd6a>
│ │  	str	r0, [sp, #4]
│ │ @@ -505132,28 +505132,28 @@
│ │  	str	r4, [r0, #0]
│ │  	b.n	27a0fe <uniffi_pbcli_checksum_method_api_base@@Base+0x10d87a>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r9, ip, pc}
│ │  	movs	r6, r4
│ │  	lsls	r0, r7, #28
│ │  	movs	r0, r0
│ │ -	cbnz	r6, 27a60a <uniffi_pbcli_checksum_method_api_base@@Base+0x10dd86>
│ │ +	cbnz	r5, 27a614 <uniffi_pbcli_checksum_method_api_base@@Base+0x10dd90>
│ │  	vaddw.u32	<illegal reg q12.5>, <illegal reg q8.5>, d12
│ │  	movs	r6, r4
│ │ -			@ <UNDEFINED> instruction: 0xb8da
│ │ -	vqshrun.s64	d27, q1, #31
│ │ +	cbnz	r1, 27a60c <uniffi_pbcli_checksum_method_api_base@@Base+0x10dd88>
│ │ +	vqshrun.s64	d27, <illegal reg q12.5>, #31
│ │  	vsubw.u32	<illegal reg q11.5>, <illegal reg q8.5>, d13
│ │  	vaddl.u32	<illegal reg q12.5>, d16, d0
│ │  	movs	r6, r4
│ │  	str	r0, [sp, #336]	@ 0x150
│ │  	movs	r6, r4
│ │ -			@ <UNDEFINED> instruction: 0xb726
│ │ -	vabdl.u32	<illegal reg q13.5>, d1, d6
│ │ -	vabdl.u32	<illegal reg q13.5>, d17, d10
│ │ -	vrsubhn.i64	d27, <illegal reg q8.5>, q9
│ │ +			@ <UNDEFINED> instruction: 0xb74d
│ │ +	vabdl.u32	<illegal reg q13.5>, d1, d29
│ │ +	vqshl.u64	d27, d17, #33	@ 0x21
│ │ +	vmlsl.u32	<illegal reg q13.5>, d17, d9[0]
│ │  	vrshr.u32	d23, d13, #31
│ │  	vqshrun.s64	d20, q8, #32
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	27ab54 <uniffi_pbcli_checksum_method_api_base@@Base+0x10e2d0>
│ │  	ands	r0, r0
│ │  	b.n	27a97e <uniffi_pbcli_checksum_method_api_base@@Base+0x10e0fa>
│ │  	lsls	r0, r6, #1
│ │ @@ -505206,17 +505206,17 @@
│ │  	b.n	27ad2a <uniffi_pbcli_checksum_method_api_base@@Base+0x10e4a6>
│ │  	movs	r0, #0
│ │  	b.n	27adee <uniffi_pbcli_checksum_method_api_base@@Base+0x10e56a>
│ │  	ldr	r0, [pc, #192]	@ (27a770 <uniffi_pbcli_checksum_method_api_base@@Base+0x10deec>)
│ │  	ldmia.w	sp!, {r4, r5, r6, r9, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xea018e9c
│ │  	movs	r6, r4
│ │ -	push	{r1, r3, r4, r5, r7, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffe13b15
│ │ -	vmls.f32	<illegal reg q13.5>, q9, d10[1]
│ │ +	push	{r0, r5, r6, r7, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffe13b3c
│ │ +	vqshlu.s32	d27, d1, #2
│ │  	vcvt.f16.u16	d20, d0, #31
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	27abe8 <uniffi_pbcli_checksum_method_api_base@@Base+0x10e364>
│ │  	lsls	r4, r5, #1
│ │  	b.n	27a210 <uniffi_pbcli_checksum_method_api_base@@Base+0x10d98c>
│ │  	movs	r0, r0
│ │  	b.n	27a7f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x10df70>
│ │ @@ -505265,15 +505265,15 @@
│ │  	b.n	27ae76 <uniffi_pbcli_checksum_method_api_base@@Base+0x10e5f2>
│ │  	strb	r7, [r1, #9]
│ │  	add.w	r0, r1, r4
│ │  	b.n	27aa7e <uniffi_pbcli_checksum_method_api_base@@Base+0x10e1fa>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r3, r9, sl, fp, pc}
│ │  	movs	r6, r4
│ │ -	push	{r1, r4, r5, lr}
│ │ +	push	{r0, r3, r4, r6, lr}
│ │  	vaddl.u32	q8, d17, d28
│ │  	vcvt.f16.u16	d20, d0, #31
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	27ac70 <uniffi_pbcli_checksum_method_api_base@@Base+0x10e3ec>
│ │  	lsls	r0, r2, #1
│ │  	b.n	27a298 <uniffi_pbcli_checksum_method_api_base@@Base+0x10da14>
│ │  	asrs	r0, r0, #32
│ │ @@ -505589,29 +505589,29 @@
│ │  	b.n	27ad4e <uniffi_pbcli_checksum_method_api_base@@Base+0x10e4ca>
│ │  	movs	r1, #115	@ 0x73
│ │  	b.n	27b012 <uniffi_pbcli_checksum_method_api_base@@Base+0x10e78e>
│ │  	ldrh	r5, [r5, #8]
│ │  	add.w	r0, r2, r5
│ │  	b.n	27ad5a <uniffi_pbcli_checksum_method_api_base@@Base+0x10e4d6>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r2, r6, sl, ip, sp, pc}
│ │ -	vmul.f32	q8, <illegal reg q8.5>, d4[1]
│ │ +	ldmia.w	sp!, {r0, r2, r3, r5, r6, sl, ip, sp, pc}
│ │ +	vmlsl.u32	q8, d1, d11
│ │  	vmla.f32	q8, q9, d8[1]
│ │  	movs	r0, r0
│ │ -	cbz	r6, 27aa9e <uniffi_pbcli_checksum_method_api_base@@Base+0x10e21a>
│ │ -	vmlal.u32	<illegal reg q13.5>, d1, d10[1]
│ │ -	vmlal.u32	q8, d1, d8
│ │ -	vsubw.u32	<illegal reg q13.5>, q9, d6
│ │ -			@ <UNDEFINED> instruction: 0xffe1b366
│ │ +	cbz	r5, 27aaa8 <uniffi_pbcli_checksum_method_api_base@@Base+0x10e224>
│ │ +	vrshr.u64	d27, d1, #31
│ │ +	vmlal.u32	q8, d1, d31
│ │ +	vsubw.u32	<illegal reg q13.5>, q9, d29
│ │ +	vsubw.u32	<illegal reg q13.5>, <illegal reg q8.5>, d13
│ │  			@ <UNDEFINED> instruction: 0xffe18bc4
│ │  	movs	r6, r4
│ │ -	cbz	r6, 27aa86 <uniffi_pbcli_checksum_method_api_base@@Base+0x10e202>
│ │ -	vmlal.u32	q8, d17, d28
│ │ -	vmlal.u32	<illegal reg q13.5>, d18, d14[0]
│ │ -	vsubl.u32	<illegal reg q13.5>, d17, d2
│ │ +	cbz	r5, 27aa90 <uniffi_pbcli_checksum_method_api_base@@Base+0x10e20c>
│ │ +			@ <UNDEFINED> instruction: 0xffe108d3
│ │ +	vrshr.u64	<illegal reg q13.5>, <illegal reg q10.5>, #30
│ │ +	vsubl.u32	<illegal reg q13.5>, d17, d25
│ │  	vcvt.f16.u16	q10, q8, #31
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	27af74 <uniffi_pbcli_checksum_method_api_base@@Base+0x10e6f0>
│ │  	lsls	r4, r3, #3
│ │  	b.n	27a59c <uniffi_pbcli_checksum_method_api_base@@Base+0x10dd18>
│ │  	movs	r0, r0
│ │  	b.n	27ab80 <uniffi_pbcli_checksum_method_api_base@@Base+0x10e2fc>
│ │ @@ -505708,21 +505708,21 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	27ac50 <uniffi_pbcli_checksum_method_api_base@@Base+0x10e3cc>
│ │  	ldr	r4, [pc, #448]	@ (27acf4 <uniffi_pbcli_checksum_method_api_base@@Base+0x10e470>)
│ │  	ldmia.w	sp!, {r2, r5, r6, r7, fp, pc}
│ │  			@ <UNDEFINED> instruction: 0xea028c70
│ │  	ldmia.w	sp!, {r7, r9, fp, pc}
│ │  	movs	r6, r4
│ │ -	cbz	r2, 27ab72 <uniffi_pbcli_checksum_method_api_base@@Base+0x10e2ee>
│ │ -	vmla.f32	<illegal reg q13.5>, <illegal reg q0.5>, d14[1]
│ │ +	cbz	r1, 27ab7c <uniffi_pbcli_checksum_method_api_base@@Base+0x10e2f8>
│ │ +	vsra.u64	d27, d5, #31
│ │  			@ <UNDEFINED> instruction: 0xffe189f0
│ │  	movs	r6, r4
│ │  	ldrh	r4, [r3, #14]
│ │  	movs	r6, r4
│ │ -	cbz	r6, 27ab5a <uniffi_pbcli_checksum_method_api_base@@Base+0x10e2d6>
│ │ +	cbz	r5, 27ab64 <uniffi_pbcli_checksum_method_api_base@@Base+0x10e2e0>
│ │  	vcvt.f16.u16	d20, d0, #31
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	27b078 <uniffi_pbcli_checksum_method_api_base@@Base+0x10e7f4>
│ │  	lsrs	r1, r0, #16
│ │  	b.n	27b2a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x10ea1e>
│ │  	asrs	r0, r0, #32
│ │  	b.n	27b2a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x10ea22>
│ │ @@ -507072,21 +507072,21 @@
│ │  	b.n	27ba26 <uniffi_pbcli_checksum_method_api_base@@Base+0x10f1a2>
│ │  	movs	r1, #75	@ 0x4b
│ │  	b.n	27bcea <uniffi_pbcli_checksum_method_api_base@@Base+0x10f466>
│ │  	asrs	r1, r0, #32
│ │  	b.n	27b80c <uniffi_pbcli_checksum_method_api_base@@Base+0x10ef88>
│ │  	strh	r6, [r6, #46]	@ 0x2e
│ │  			@ <UNDEFINED> instruction: 0xeb02fff2
│ │ -			@ <UNDEFINED> instruction: 0xeaffa6df
│ │ -	vqshlu.s64	d26, d31, #33	@ 0x21
│ │ -	vmlsl.u32	q13, d1, d11[0]
│ │ -	vqshlu.s32	d26, d7, #1
│ │ -	vsli.32	q13, <illegal reg q11.5>, #1
│ │ -	vmls.f32	q13, <illegal reg q8.5>, d15[1]
│ │ -	vsli.64	d26, d27, #33	@ 0x21
│ │ +			@ <UNDEFINED> instruction: 0xeaffa706
│ │ +	vmlsl.u32	q13, d17, d6[1]
│ │ +	vqshlu.s32	q13, q9, #1
│ │ +	vqshlu.s32	d26, d30, #1
│ │ +	vsli.64	d26, d14, #33	@ 0x21
│ │ +	vqshlu.s32	d26, d6, #1
│ │ +	vmls.f32	q13, <illegal reg q8.5>, d2[1]
│ │  			@ <UNDEFINED> instruction: 0xffe14df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	27bc34 <uniffi_pbcli_checksum_method_api_base@@Base+0x10f3b0>
│ │  	asrs	r0, r2, #3
│ │  	b.n	27b25c <uniffi_pbcli_checksum_method_api_base@@Base+0x10e9d8>
│ │  	str	r0, [r0, #0]
│ │  	b.n	27ba62 <uniffi_pbcli_checksum_method_api_base@@Base+0x10f1de>
│ │ @@ -507182,19 +507182,19 @@
│ │  	b.n	27bb22 <uniffi_pbcli_checksum_method_api_base@@Base+0x10f29e>
│ │  	movs	r0, #61	@ 0x3d
│ │  	b.n	27bf26 <uniffi_pbcli_checksum_method_api_base@@Base+0x10f6a2>
│ │  	strh	r0, [r7, #44]	@ 0x2c
│ │  	add.w	r0, r2, r4
│ │  	b.n	27bb2e <uniffi_pbcli_checksum_method_api_base@@Base+0x10f2aa>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r8, sl, sp, pc}
│ │ -	vsli.32	d26, d3, #1
│ │ -	vraddhn.i64	d26, <illegal reg q8.5>, <illegal reg q11.5>
│ │ -	vmls.i32	q13, <illegal reg q8.5>, d7[1]
│ │ -	vsri.64	d26, d3, #31
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r6, r8, sl, sp, pc}
│ │ +	vsli.32	d26, d26, #1
│ │ +	vmls.i32	q13, <illegal reg q8.5>, d14[0]
│ │ +	vabal.u32	q13, d1, d14
│ │ +	vsri.64	d26, d26, #31
│ │  	vaddl.u32	q8, d1, d0
│ │  	b.n	27beaa <uniffi_pbcli_checksum_method_api_base@@Base+0x10f626>
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #448]	@ (27b9d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x10f150>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │ @@ -507235,15 +507235,15 @@
│ │  	movs	r4, r2
│ │  	b.n	27b36e <uniffi_pbcli_checksum_method_api_base@@Base+0x10eaea>
│ │  	movs	r0, r5
│ │  	b.n	27b372 <uniffi_pbcli_checksum_method_api_base@@Base+0x10eaee>
│ │  	movs	r1, r0
│ │  	b.n	27bfae <uniffi_pbcli_checksum_method_api_base@@Base+0x10f72a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r4, r5, sl, sp, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r4, r6, sl, sp, pc}
│ │  	vaddl.u32	q8, d1, d28
│ │  	b.n	27b39a <uniffi_pbcli_checksum_method_api_base@@Base+0x10eb16>
│ │  	movs	r0, r0
│ │  	b.n	27bf1e <uniffi_pbcli_checksum_method_api_base@@Base+0x10f69a>
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │ @@ -507446,16 +507446,16 @@
│ │  	b.n	27bd76 <uniffi_pbcli_checksum_method_api_base@@Base+0x10f4f2>
│ │  	adds	r0, #4
│ │  	b.n	27bd7a <uniffi_pbcli_checksum_method_api_base@@Base+0x10f4f6>
│ │  	beq.n	27ba74 <uniffi_pbcli_checksum_method_api_base@@Base+0x10f1f0>
│ │  	b.n	27bed4 <uniffi_pbcli_checksum_method_api_base@@Base+0x10f650>
│ │  	ldr	r7, [pc, #960]	@ (27be00 <uniffi_pbcli_checksum_method_api_base@@Base+0x10f57c>)
│ │  	ldmia.w	sp!, {r0, r2, r3, r5, r7, r8, r9}
│ │ -			@ <UNDEFINED> instruction: 0xea0099a6
│ │ -			@ <UNDEFINED> instruction: 0xffe23b46
│ │ +			@ <UNDEFINED> instruction: 0xea0099cd
│ │ +			@ <UNDEFINED> instruction: 0xffe23b6d
│ │  	vcvt.f16.u16	q10, q8, #30
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	27bf70 <uniffi_pbcli_checksum_method_api_base@@Base+0x10f6ec>
│ │  	ands	r3, r0
│ │  	b.n	27bd9a <uniffi_pbcli_checksum_method_api_base@@Base+0x10f516>
│ │  	str	r2, [r0, r0]
│ │  	b.n	27bd9e <uniffi_pbcli_checksum_method_api_base@@Base+0x10f51a>
│ │ @@ -508005,16 +508005,16 @@
│ │  	and.w	r0, r0, r0, lsl #4
│ │  	b.n	27c26a <uniffi_pbcli_checksum_method_api_base@@Base+0x10f9e6>
│ │  	movs	r1, r0
│ │  	b.n	27c26e <uniffi_pbcli_checksum_method_api_base@@Base+0x10f9ea>
│ │  	beq.n	27bf68 <uniffi_pbcli_checksum_method_api_base@@Base+0x10f6e4>
│ │  	b.n	27c3c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x10fb44>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r8, r9, sl, ip, sp}
│ │ -	vmla.i32	<illegal reg q10.5>, q1, d3[1]
│ │ +	ldmia.w	sp!, {r0, r2, r6, r8, r9, sl, ip, sp}
│ │ +	vaddl.u32	<illegal reg q10.5>, d18, d10
│ │  	vshr.u64	<illegal reg q11.5>, q11, #30
│ │  	vmlal.u32	q10, d1, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	27c28a <uniffi_pbcli_checksum_method_api_base@@Base+0x10fa06>
│ │  	beq.n	27bf5c <uniffi_pbcli_checksum_method_api_base@@Base+0x10f6d8>
│ │  	b.n	27c3e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x10fb64>
│ │  	stmia	r0!, {r1}
│ │ @@ -508185,19 +508185,19 @@
│ │  	lsls	r3, r2, #25
│ │  	add.w	r0, r0, r1
│ │  	b.n	27c7fe <uniffi_pbcli_checksum_method_api_base@@Base+0x10ff7a>
│ │  	beq.n	27c0f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x10f874>
│ │  	b.n	27c558 <uniffi_pbcli_checksum_method_api_base@@Base+0x10fcd4>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r2, r3, r7, fp, sp}
│ │ -	vrshr.u64	<illegal reg q12.5>, q1, #31
│ │ -	vsri.32	<illegal reg q9.5>, q9, #30
│ │ -	vsli.32	d28, d2, #2
│ │ -	vmlal.u32	<illegal reg q12.5>, d1, d14[1]
│ │ -	vraddhn.i64	d19, q1, q7
│ │ +	vrshr.u64	<illegal reg q12.5>, <illegal reg q12.5>, #31
│ │ +	vsri.64	d19, d9, #30
│ │ +	vsli.32	d28, d25, #2
│ │ +	vrshr.u64	d25, d5, #31
│ │ +	vsri.32	d19, d21, #30
│ │  	vabal.u32	<illegal reg q10.5>, d18, d18
│ │  	vmlal.u32	q10, d1, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	27c42a <uniffi_pbcli_checksum_method_api_base@@Base+0x10fba6>
│ │  	lsls	r4, r4, #1
│ │  	b.n	27c6ee <uniffi_pbcli_checksum_method_api_base@@Base+0x10fe6a>
│ │  	movs	r0, r0
│ │ @@ -508346,15 +508346,15 @@
│ │  	b.n	27c350 <uniffi_pbcli_checksum_method_api_base@@Base+0x10facc>
│ │  	strh	r5, [r4, #24]
│ │  	add.w	r0, r2, r0
│ │  	b.n	27c97a <uniffi_pbcli_checksum_method_api_base@@Base+0x1100f6>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r3, r4, r5, r7, r8, sl, ip, sp, pc}
│ │  	vsli.32	d27, d13, #0
│ │ -	vmlsl.u32	<illegal reg q14.5>, d16, d8
│ │ +	vmlsl.u32	<illegal reg q14.5>, d16, d31
│ │  	vmls.i32	<illegal reg q13.5>, <illegal reg q8.5>, d1[1]
│ │  	vaddl.u32	<illegal reg q8.5>, d0, d0
│ │  	b.n	27c592 <uniffi_pbcli_checksum_method_api_base@@Base+0x10fd0e>
│ │  	movs	r0, r0
│ │  	b.n	27c996 <uniffi_pbcli_checksum_method_api_base@@Base+0x110112>
│ │  			@ <UNDEFINED> instruction: 0xffb8eaff
│ │  	ldr	r4, [pc, #448]	@ (27c41c <uniffi_pbcli_checksum_method_api_base@@Base+0x10fb98>)
│ │ @@ -508817,15 +508817,15 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	27ce0e <uniffi_pbcli_checksum_method_api_base@@Base+0x11058a>
│ │  			@ <UNDEFINED> instruction: 0xffa4eaff
│ │  	str	r0, [r0, r0]
│ │  	b.n	27c996 <uniffi_pbcli_checksum_method_api_base@@Base+0x110112>
│ │  			@ <UNDEFINED> instruction: 0xffa2eaff
│ │  	sxtb	r5, r0
│ │ -	vsra.u32	<illegal reg q9.5>, q9, #32
│ │ +	vsra.u64	d19, d9, #32
│ │  	vmlal.u32	q10, d2, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	27c9aa <uniffi_pbcli_checksum_method_api_base@@Base+0x110126>
│ │  	vqrdmlah.s32	q15, q14, <illegal reg q15.5>
│ │  	asrs	r0, r0, #32
│ │  	b.n	27cdb2 <uniffi_pbcli_checksum_method_api_base@@Base+0x11052e>
│ │  	movs	r0, r0
│ │ @@ -509116,17 +509116,17 @@
│ │  	beq.n	27c910 <uniffi_pbcli_checksum_method_api_base@@Base+0x11008c>
│ │  	b.n	27cd78 <uniffi_pbcli_checksum_method_api_base@@Base+0x1104f4>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r0}
│ │  	b.n	27cc2a <uniffi_pbcli_checksum_method_api_base@@Base+0x1103a6>
│ │  			@ <UNDEFINED> instruction: 0xfff8eaff
│ │  	add	sp, #4
│ │ -	vmul.f32	q13, q8, d10[1]
│ │ +	vmovl.u32	q13, d1
│ │  	vmull.p64	q13, d17, d13
│ │ -	vqrshrun.s64	d26, q11, #32
│ │ +			@ <UNDEFINED> instruction: 0xffe0a89d
│ │  	vqshrun.s64	d20, q8, #31
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	27ce20 <uniffi_pbcli_checksum_method_api_base@@Base+0x11059c>
│ │  	ands	r2, r0
│ │  	b.n	27cc4a <uniffi_pbcli_checksum_method_api_base@@Base+0x1103c6>
│ │  	str	r0, [r0, r0]
│ │  	b.n	27cc4e <uniffi_pbcli_checksum_method_api_base@@Base+0x1103ca>
│ │ @@ -509392,19 +509392,19 @@
│ │  	movs	r4, r0
│ │  	b.n	27ce8a <uniffi_pbcli_checksum_method_api_base@@Base+0x110606>
│ │  	vrhadd.u<illegal width 64>	d14, d7, d31
│ │  	str	r0, [r0, r0]
│ │  	b.n	27ce92 <uniffi_pbcli_checksum_method_api_base@@Base+0x11060e>
│ │  			@ <UNDEFINED> instruction: 0xff9eeaff
│ │  	add	r5, sp, #372	@ 0x174
│ │ -	vshr.u64	d16, d29, #32
│ │ +	vmla.i32	q8, q8, d4[1]
│ │  			@ <UNDEFINED> instruction: 0xffe2ad8d
│ │ -	vmla.i32	q8, q8, d13[1]
│ │ +	vsra.u32	d16, d4, #32
│ │  	vmull.u32	q13, d2, d13
│ │ -	vqrdmlsh.s32	<illegal reg q15.5>, q0, d13[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe0ff94
│ │  			@ <UNDEFINED> instruction: 0xffe14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	27d090 <uniffi_pbcli_checksum_method_api_base@@Base+0x11080c>
│ │  	beq.n	27cbe0 <uniffi_pbcli_checksum_method_api_base@@Base+0x11035c>
│ │  	b.n	27d014 <uniffi_pbcli_checksum_method_api_base@@Base+0x110790>
│ │  	strh	r0, [r2, #0]
│ │  	b.n	27c6b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x10fe30>
│ │ @@ -509839,15 +509839,15 @@
│ │  	strb	r4, [r0, #0]
│ │  	b.n	27ca4c <uniffi_pbcli_checksum_method_api_base@@Base+0x1101c8>
│ │  	vrhadd.u<illegal width 64>	d14, d9, d31
│ │  	beq.n	27cf70 <uniffi_pbcli_checksum_method_api_base@@Base+0x1106ec>
│ │  	b.n	27d3d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x110b4c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r5, r8, fp, sp, pc}
│ │ -	vsubw.u32	q13, q0, d1
│ │ +	vsubw.u32	q13, q0, d24
│ │  	vaddl.u32	<illegal reg q9.5>, d1, d1
│ │  	b.n	27d28a <uniffi_pbcli_checksum_method_api_base@@Base+0x110a06>
│ │  	asrs	r4, r3, #1
│ │  	b.n	27d68e <uniffi_pbcli_checksum_method_api_base@@Base+0x110e0a>
│ │  	movs	r0, #0
│ │  	b.n	27d692 <uniffi_pbcli_checksum_method_api_base@@Base+0x110e0e>
│ │  			@ <UNDEFINED> instruction: 0xff96eaff
│ │ @@ -510110,21 +510110,21 @@
│ │  	str	r5, [r7, #116]	@ 0x74
│ │  	add.w	r0, r1, r0, asr #32
│ │  	b.n	27d8d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x11104e>
│ │  	asrs	r6, r4, #1
│ │  	b.n	27d8d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x111052>
│ │  			@ <UNDEFINED> instruction: 0xff93eaff
│ │  	add	r7, pc, #244	@ (adr r7, 27d290 <uniffi_pbcli_checksum_method_api_base@@Base+0x110a0c>)
│ │ -	vqshlu.s32	q9, q4, #0
│ │ +	vqshlu.s32	q9, <illegal reg q15.5>, #0
│ │  	vqshl.u32	q13, <illegal reg q10.5>, #2
│ │ -	vqshlu.s64	d18, d0, #32
│ │ +	vqshlu.s64	d18, d23, #32
│ │  	vmlsl.u32	q13, d2, d1[0]
│ │ -	vsli.32	q9, q6, #0
│ │ +	vabal.u32	q9, d16, d3
│ │  	vabal.u32	q13, d18, d13
│ │ -	vraddhn.i64	d18, q8, q12
│ │ +	vmls.i32	q9, q8, d15[0]
│ │  			@ <UNDEFINED> instruction: 0xffe24df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	27d6dc <uniffi_pbcli_checksum_method_api_base@@Base+0x110e58>
│ │  	beq.n	27d1f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x110970>
│ │  	b.n	27d660 <uniffi_pbcli_checksum_method_api_base@@Base+0x110ddc>
│ │  	str	r0, [r0, #0]
│ │  	b.n	27d50a <uniffi_pbcli_checksum_method_api_base@@Base+0x110c86>
│ │ @@ -510402,21 +510402,21 @@
│ │  	b.n	27daba <uniffi_pbcli_checksum_method_api_base@@Base+0x111236>
│ │  	movs	r1, r0
│ │  	add	r1, pc, #640	@ (adr r1, 27d69c <uniffi_pbcli_checksum_method_api_base@@Base+0x110e18>)
│ │  	beq.n	27d450 <uniffi_pbcli_checksum_method_api_base@@Base+0x110bcc>
│ │  	b.n	27d8b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x111034>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, r3, r4, r6, r7, sl, sp, pc}
│ │ -	vrsra.u64	q9, <illegal reg q14.5>, #32
│ │ +	vraddhn.i64	d18, q0, q10
│ │  	vsli.32	d26, d1, #2
│ │ -	vsri.32	d18, d21, #32
│ │ +	vsri.32	q9, q6, #32
│ │  	vmls.i32	q13, q1, d13[0]
│ │ -	vrsra.u32	q9, <illegal reg q8.5>, #32
│ │ +	vrsra.u64	d18, d8, #32
│ │  	vrsra.u64	d26, d17, #30
│ │ -	vrshr.u64	q9, <illegal reg q2.5>, #32
│ │ +	vrshr.u64	q9, q14, #32
│ │  	vcvt.f16.u16	q10, q8, #30
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	27d968 <uniffi_pbcli_checksum_method_api_base@@Base+0x1110e4>
│ │  	str	r0, [r0, r1]
│ │  	b.n	27cf90 <uniffi_pbcli_checksum_method_api_base@@Base+0x11070c>
│ │  	ands	r0, r0
│ │  	b.n	27d796 <uniffi_pbcli_checksum_method_api_base@@Base+0x110f12>
│ │ @@ -510635,15 +510635,15 @@
│ │  	b.n	27d96e <uniffi_pbcli_checksum_method_api_base@@Base+0x1110ea>
│ │  	movs	r5, r0
│ │  	b.n	27d972 <uniffi_pbcli_checksum_method_api_base@@Base+0x1110ee>
│ │  	beq.n	27d654 <uniffi_pbcli_checksum_method_api_base@@Base+0x110dd0>
│ │  	b.n	27dacc <uniffi_pbcli_checksum_method_api_base@@Base+0x111248>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r2, r6, r7, r8, sp, pc}
│ │ -	vcvt.u32.f32	q10, <illegal reg q14.5>, #32
│ │ +			@ <UNDEFINED> instruction: 0xffe04fa4
│ │  	vcvt.f16.u16	d20, d0, #30
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	27db64 <uniffi_pbcli_checksum_method_api_base@@Base+0x1112e0>
│ │  	movs	r0, r0
│ │  	b.n	27dcee <uniffi_pbcli_checksum_method_api_base@@Base+0x11146a>
│ │  	movs	r5, r1
│ │  	lsrs	r0, r0, #8
│ │ @@ -511161,16 +511161,16 @@
│ │  	ands	r0, r0
│ │  	b.n	27de2e <uniffi_pbcli_checksum_method_api_base@@Base+0x1115aa>
│ │  	movs	r4, r0
│ │  	b.n	27de32 <uniffi_pbcli_checksum_method_api_base@@Base+0x1115ae>
│ │  	beq.n	27db04 <uniffi_pbcli_checksum_method_api_base@@Base+0x111280>
│ │  	b.n	27df8c <uniffi_pbcli_checksum_method_api_base@@Base+0x111708>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r6, r8, r9, ip, sp}
│ │ -			@ <UNDEFINED> instruction: 0xffe23362
│ │ +	ldmia.w	sp!, {r0, r2, r4, r5, r6, r8, r9, ip, sp}
│ │ +	vsubw.u32	<illegal reg q9.5>, q9, d9
│ │  			@ <UNDEFINED> instruction: 0xffe24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	27e024 <uniffi_pbcli_checksum_method_api_base@@Base+0x1117a0>
│ │  	beq.n	27db84 <uniffi_pbcli_checksum_method_api_base@@Base+0x111300>
│ │  	b.n	27dfa8 <uniffi_pbcli_checksum_method_api_base@@Base+0x111724>
│ │  	movs	r4, r4
│ │  	b.n	27d62c <uniffi_pbcli_checksum_method_api_base@@Base+0x110da8>
│ │ @@ -512294,15 +512294,15 @@
│ │  	b.n	27e892 <uniffi_pbcli_checksum_method_api_base@@Base+0x11200e>
│ │  	beq.n	27e58c <uniffi_pbcli_checksum_method_api_base@@Base+0x111d08>
│ │  	b.n	27e9ec <uniffi_pbcli_checksum_method_api_base@@Base+0x112168>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {lr}
│ │  	b.n	27ec9e <uniffi_pbcli_checksum_method_api_base@@Base+0x11241a>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │ -	vpmax.f32	<illegal reg q15.5>, <illegal reg q9.5>, <illegal reg q8.5>
│ │ +	vpmin.f32	<illegal reg q15.5>, q13, <illegal reg q8.5>
│ │  	beq.n	27e570 <uniffi_pbcli_checksum_method_api_base@@Base+0x111cec>
│ │  	b.n	27ea04 <uniffi_pbcli_checksum_method_api_base@@Base+0x112180>
│ │  	ldr	r0, [pc, #0]	@ (27e56c <uniffi_pbcli_checksum_method_api_base@@Base+0x111ce8>)
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	27e8b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x11202e>
│ │  	beq.n	27e5bc <uniffi_pbcli_checksum_method_api_base@@Base+0x111d38>
│ │  	b.n	27ea10 <uniffi_pbcli_checksum_method_api_base@@Base+0x11218c>
│ │ @@ -512518,15 +512518,15 @@
│ │  	asrs	r0, r0, #32
│ │  	lsls	r5, r2, #22
│ │  	movs	r4, r0
│ │  	b.n	27e6bc <uniffi_pbcli_checksum_method_api_base@@Base+0x111e38>
│ │  	movs	r6, r0
│ │  	b.n	27ea7e <uniffi_pbcli_checksum_method_api_base@@Base+0x1121fa>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r5, r6, r8, r9, sl, sp}
│ │ +	ldmia.w	sp!, {r0, r2, r4, r7, r8, r9, sl, sp}
│ │  			@ <UNDEFINED> instruction: 0xffe24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	27ec68 <uniffi_pbcli_checksum_method_api_base@@Base+0x1123e4>
│ │  	beq.n	27e7d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x111f54>
│ │  	b.n	27ebec <uniffi_pbcli_checksum_method_api_base@@Base+0x112368>
│ │  	adds	r0, #12
│ │  	b.n	27e270 <uniffi_pbcli_checksum_method_api_base@@Base+0x1119ec>
│ │ @@ -512914,20 +512914,20 @@
│ │  	movs	r0, r0
│ │  	b.n	27f11a <uniffi_pbcli_checksum_method_api_base@@Base+0x112896>
│ │  			@ <UNDEFINED> instruction: 0xffef0aff
│ │  	str	r1, [r0, r0]
│ │  	b.n	27efac <uniffi_pbcli_checksum_method_api_base@@Base+0x112728>
│ │  			@ <UNDEFINED> instruction: 0xfff53aff
│ │  			@ <UNDEFINED> instruction: 0xffedeaff
│ │ -	ldrh	r3, [r2, #8]
│ │ -	vmull.u32	q8, d17, d26
│ │ +	ldrh	r2, [r7, #8]
│ │ +			@ <UNDEFINED> instruction: 0xffe10cd1
│ │  	vmla.f32	q10, q9, d6[1]
│ │  	vcvt.u16.f16	<illegal reg q10.5>, q0, #31
│ │  	vmls.i32	<illegal reg q14.5>, <illegal reg q0.5>, d10[1]
│ │ -	vcvt.f16.u16	d16, d2, #32
│ │ +	vcvt.f16.u16	d16, d25, #32
│ │  			@ <UNDEFINED> instruction: 0xffe24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	27efc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x112740>
│ │  	beq.n	27eb74 <uniffi_pbcli_checksum_method_api_base@@Base+0x1122f0>
│ │  	b.n	27ef48 <uniffi_pbcli_checksum_method_api_base@@Base+0x1126c4>
│ │  	lsrs	r0, r0, #13
│ │  	cdp	0, 11, cr14, cr5, cr12, {0}
│ │ @@ -513886,19 +513886,19 @@
│ │  	b.n	27fae2 <uniffi_pbcli_checksum_method_api_base@@Base+0x11325e>
│ │  	movs	r4, r0
│ │  	b.n	27f666 <uniffi_pbcli_checksum_method_api_base@@Base+0x112de2>
│ │  	beq.n	27f348 <uniffi_pbcli_checksum_method_api_base@@Base+0x112ac4>
│ │  	b.n	27f7c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x112f3c>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r1, r3, r4, r5, r6, r8, sl, ip, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffe0a9af
│ │ +			@ <UNDEFINED> instruction: 0xffe0a9d6
│ │  	vsli.32	<illegal reg q10.5>, q1, #1
│ │ -			@ <UNDEFINED> instruction: 0xffe0a987
│ │ +			@ <UNDEFINED> instruction: 0xffe0a9ae
│ │  	vsli.64	d21, d22, #33	@ 0x21
│ │ -	vmul.f32	q13, q8, d11[1]
│ │ +	vmovl.u32	q13, d2
│ │  			@ <UNDEFINED> instruction: 0xffe148f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	27f868 <uniffi_pbcli_checksum_method_api_base@@Base+0x112fe4>
│ │  	str	r0, [r0, r0]
│ │  	b.n	27f692 <uniffi_pbcli_checksum_method_api_base@@Base+0x112e0e>
│ │  	movs	r0, r0
│ │  	b.n	27fa00 <uniffi_pbcli_checksum_method_api_base@@Base+0x11317c>
│ │ @@ -514319,19 +514319,19 @@
│ │  	add	r4, pc, #464	@ (adr r4, 27f8c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x11303c>)
│ │  	add.w	r0, r2, r4
│ │  	b.n	27fa36 <uniffi_pbcli_checksum_method_api_base@@Base+0x1131b2>
│ │  	beq.n	27f730 <uniffi_pbcli_checksum_method_api_base@@Base+0x112eac>
│ │  	b.n	27fb90 <uniffi_pbcli_checksum_method_api_base@@Base+0x11330c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r1, r2, r9, ip, lr}
│ │ -	vqshlu.s32	q10, <illegal reg q11.5>, #0
│ │ +	vqshlu.s64	d20, d14, #32
│ │  	vaddw.u32	<illegal reg q10.5>, q9, d6
│ │ -	vsli.64	q10, <illegal reg q11.5>, #32
│ │ +	vqshlu.s32	d20, d14, #0
│ │  	vsra.u64	<illegal reg q10.5>, q5, #30
│ │ -	vmlsl.u32	q10, d0, d11[0]
│ │ +	vqshlu.s32	q10, q9, #0
│ │  			@ <UNDEFINED> instruction: 0xffe24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	27fc38 <uniffi_pbcli_checksum_method_api_base@@Base+0x1133b4>
│ │  	beq.n	27f6f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x112e74>
│ │  	b.n	27fbbc <uniffi_pbcli_checksum_method_api_base@@Base+0x113338>
│ │  	add	r0, pc, #52	@ (adr r0, 27f758 <uniffi_pbcli_checksum_method_api_base@@Base+0x112ed4>)
│ │  	b.n	27fa66 <uniffi_pbcli_checksum_method_api_base@@Base+0x1131e2>
│ │ @@ -515996,15 +515996,15 @@
│ │  	b.n	280c2e <uniffi_pbcli_checksum_method_api_base@@Base+0x1143aa>
│ │  	movs	r4, r0
│ │  	b.n	280832 <uniffi_pbcli_checksum_method_api_base@@Base+0x113fae>
│ │  	beq.n	28052c <uniffi_pbcli_checksum_method_api_base@@Base+0x113ca8>
│ │  	b.n	28098c <uniffi_pbcli_checksum_method_api_base@@Base+0x114108>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r1, r2, r3, r4, sl, lr}
│ │ -	vqrdmlah.s32	q10, q8, d14[1]
│ │ +	vcvt.u32.f32	d20, d5, #32
│ │  			@ <UNDEFINED> instruction: 0xffe248f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	280a24 <uniffi_pbcli_checksum_method_api_base@@Base+0x1141a0>
│ │  	beq.n	28051c <uniffi_pbcli_checksum_method_api_base@@Base+0x113c98>
│ │  	b.n	2809a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x114124>
│ │  	movs	r1, r0
│ │  	b.n	280bf6 <uniffi_pbcli_checksum_method_api_base@@Base+0x114372>
│ │ @@ -516117,19 +516117,19 @@
│ │  	b.n	280dc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x11453e>
│ │  	movs	r4, r0
│ │  	b.n	280946 <uniffi_pbcli_checksum_method_api_base@@Base+0x1140c2>
│ │  	beq.n	280628 <uniffi_pbcli_checksum_method_api_base@@Base+0x113da4>
│ │  	b.n	280aa0 <uniffi_pbcli_checksum_method_api_base@@Base+0x11421c>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r1, r3, r4, r7, r9, lr}
│ │ -	vmull.u32	<illegal reg q14.5>, d0, d10
│ │ +	vcvt.f16.u16	d29, d17, #32
│ │  	vrshr.u32	q10, q9, #31
│ │ -			@ <UNDEFINED> instruction: 0xffe0dbe2
│ │ +	vmull.u32	<illegal reg q14.5>, d0, d9
│ │  	vrshr.u64	q10, q3, #31
│ │ -	vqdmulh.s32	<illegal reg q14.5>, q0, d6[0]
│ │ +	vqdmulh.s32	<illegal reg q14.5>, q0, d13[1]
│ │  	vsri.64	<illegal reg q14.5>, q2, #31
│ │  	bmi.n	2805d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x113d4e>
│ │  	bmi.n	2805d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x113d50>
│ │  	bmi.n	2805d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x113d52>
│ │  	bmi.n	2805d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x113d54>
│ │  	bmi.n	2805da <uniffi_pbcli_checksum_method_api_base@@Base+0x113d56>
│ │  	ldr	r4, [pc, #448]	@ (2807f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x113f70>)
│ │ @@ -516378,15 +516378,15 @@
│ │  	add.w	r0, r1, r5
│ │  	b.n	280bb6 <uniffi_pbcli_checksum_method_api_base@@Base+0x114332>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {}
│ │  	b.n	280fbe <uniffi_pbcli_checksum_method_api_base@@Base+0x11473a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r1, r2, r3, r4, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffe07d98
│ │ +			@ <UNDEFINED> instruction: 0xffe07dbf
│ │  	vsubw.u32	<illegal reg q10.5>, <illegal reg q8.5>, d12
│ │  	movs	r2, r4
│ │  	ldr	r5, [pc, #960]	@ (280c50 <uniffi_pbcli_checksum_method_api_base@@Base+0x1143cc>)
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	280db0 <uniffi_pbcli_checksum_method_api_base@@Base+0x11452c>
│ │  	str	r0, [r0, #0]
│ │  	b.n	280bda <uniffi_pbcli_checksum_method_api_base@@Base+0x114356>
│ │ @@ -516520,17 +516520,17 @@
│ │  	b.n	2804e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x113c5e>
│ │  	movs	r0, #0
│ │  	b.n	2804c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x113c42>
│ │  	adds	r0, #4
│ │  	b.n	2804cc <uniffi_pbcli_checksum_method_api_base@@Base+0x113c48>
│ │  			@ <UNDEFINED> instruction: 0xffc6eaff
│ │  	subs	r7, #50	@ 0x32
│ │ -			@ <UNDEFINED> instruction: 0xffe07cbc
│ │ +	vqdmulh.s32	<illegal reg q11.5>, q8, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffe13ef6
│ │ -	vmull.u32	<illegal reg q11.5>, d16, d0
│ │ +	vmull.u32	<illegal reg q11.5>, d16, d23
│ │  			@ <UNDEFINED> instruction: 0xffe14df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	280f00 <uniffi_pbcli_checksum_method_api_base@@Base+0x11467c>
│ │  	str	r0, [r0, r0]
│ │  	b.n	280d2a <uniffi_pbcli_checksum_method_api_base@@Base+0x1144a6>
│ │  	movs	r4, r3
│ │  	b.n	28050e <uniffi_pbcli_checksum_method_api_base@@Base+0x113c8a>
│ │ @@ -517879,15 +517879,15 @@
│ │  	movs	r0, #4
│ │  	b.n	281072 <uniffi_pbcli_checksum_method_api_base@@Base+0x1147ee>
│ │  	movs	r4, r0
│ │  	b.n	2818a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x115022>
│ │  	beq.n	2815a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x114d1c>
│ │  	b.n	281a00 <uniffi_pbcli_checksum_method_api_base@@Base+0x11517c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r3, r5, r8, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r4, r6, r8, sp, lr, pc}
│ │  	vmla.f32	q8, <illegal reg q0.5>, d15[1]
│ │  			@ <UNDEFINED> instruction: 0xffe14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	281a98 <uniffi_pbcli_checksum_method_api_base@@Base+0x115214>
│ │  	beq.n	281588 <uniffi_pbcli_checksum_method_api_base@@Base+0x114d04>
│ │  	b.n	281a1c <uniffi_pbcli_checksum_method_api_base@@Base+0x115198>
│ │  	str	r0, [sp, #0]
│ │ @@ -521230,17 +521230,17 @@
│ │  	b.n	282c2a <uniffi_pbcli_checksum_method_api_base@@Base+0x1163a6>
│ │  	movs	r5, r0
│ │  	b.n	2833e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x116b5e>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	2837ea <uniffi_pbcli_checksum_method_api_base@@Base+0x116f66>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r6, r7, r9, sl, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r4, r5, r6, r7, r9, sl, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffe18d0a
│ │ -	vmlsl.u32	q14, d16, d9[1]
│ │ +	vqshl.u32	d28, d0, #0
│ │  			@ <UNDEFINED> instruction: 0xffe14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2835dc <uniffi_pbcli_checksum_method_api_base@@Base+0x116d58>
│ │  	beq.n	2830cc <uniffi_pbcli_checksum_method_api_base@@Base+0x116848>
│ │  	b.n	283560 <uniffi_pbcli_checksum_method_api_base@@Base+0x116cdc>
│ │  	str	r0, [r0, #0]
│ │  	b.n	28340a <uniffi_pbcli_checksum_method_api_base@@Base+0x116b86>
│ │ @@ -521473,21 +521473,21 @@
│ │  	b.n	283a06 <uniffi_pbcli_checksum_method_api_base@@Base+0x117182>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2833e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x116b64>
│ │  	str	r7, [r7, #108]	@ 0x6c
│ │  	add.w	r0, r2, r6
│ │  	b.n	283612 <uniffi_pbcli_checksum_method_api_base@@Base+0x116d8e>
│ │  			@ <UNDEFINED> instruction: 0xffa6eaff
│ │ -	stmia	r5!, {r0, r2, r4, r5, r6}
│ │ +	stmia	r5!, {r2, r3, r4, r7}
│ │  	vcvt.u32.f32	d25, d10, #31
│ │ -			@ <UNDEFINED> instruction: 0xffdf2a5b
│ │ -	vsri.64	d28, d5, #31
│ │ -	vrsra.u64	d28, d13, #31
│ │ -	vsri.64	q14, <illegal reg q14.5>, #31
│ │ -	vmls.i32	q14, <illegal reg q8.5>, d1[1]
│ │ +	vmlsl.u16	q9, d31, d2
│ │ +	vsri.64	d28, d28, #31
│ │ +			@ <UNDEFINED> instruction: 0xffe1c3c4
│ │ +	vabal.u32	q14, d1, d20
│ │ +	vabal.u32	q14, d1, d8
│ │  			@ <UNDEFINED> instruction: 0xffe14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	283814 <uniffi_pbcli_checksum_method_api_base@@Base+0x116f90>
│ │  	beq.n	283334 <uniffi_pbcli_checksum_method_api_base@@Base+0x116ab0>
│ │  	b.n	283798 <uniffi_pbcli_checksum_method_api_base@@Base+0x116f14>
│ │  	movs	r0, r0
│ │  	b.n	2839a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x117120>
│ │ @@ -521814,15 +521814,15 @@
│ │  	str	r0, [r0, #0]
│ │  	b.n	2830cc <uniffi_pbcli_checksum_method_api_base@@Base+0x116848>
│ │  	movs	r4, r1
│ │  	asrs	r6, r0, #22
│ │  	str	r4, [r1, #0]
│ │  	b.n	28310c <uniffi_pbcli_checksum_method_api_base@@Base+0x116888>
│ │  			@ <UNDEFINED> instruction: 0xff8eeaff
│ │ -	stmia	r2!, {r0, r2, r6, r7}
│ │ +	stmia	r2!, {r2, r3, r5, r6, r7}
│ │  	vmla.f32	<illegal reg q10.5>, <illegal reg q8.5>, d10[1]
│ │  			@ <UNDEFINED> instruction: 0xffdf4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	283b00 <uniffi_pbcli_checksum_method_api_base@@Base+0x11727c>
│ │  	beq.n	2835f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x116d6c>
│ │  	b.n	283a84 <uniffi_pbcli_checksum_method_api_base@@Base+0x117200>
│ │  	movs	r0, r0
│ │ @@ -523095,17 +523095,17 @@
│ │  	b.n	284886 <uniffi_pbcli_checksum_method_api_base@@Base+0x118002>
│ │  	asrs	r3, r5, #1
│ │  	b.n	28488a <uniffi_pbcli_checksum_method_api_base@@Base+0x118006>
│ │  			@ <UNDEFINED> instruction: 0xffd7eaff
│ │  	str	r0, [r0, r0]
│ │  	b.n	284892 <uniffi_pbcli_checksum_method_api_base@@Base+0x11800e>
│ │  			@ <UNDEFINED> instruction: 0xffd7eaff
│ │ -	ldmia	r5!, {r0, r2, r4, r7}
│ │ +	ldmia	r5, {r2, r3, r4, r5, r7}
│ │  	vsri.64	q10, q14, #31
│ │ -			@ <UNDEFINED> instruction: 0xffdfccf9
│ │ +			@ <UNDEFINED> instruction: 0xffdfcd20
│ │  	vmls.i32	q10, <illegal reg q0.5>, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffdf4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	284688 <uniffi_pbcli_checksum_method_api_base@@Base+0x117e04>
│ │  	beq.n	2841e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x117964>
│ │  	b.n	28460c <uniffi_pbcli_checksum_method_api_base@@Base+0x117d88>
│ │  	ands	r0, r1
│ │ @@ -524238,18 +524238,18 @@
│ │  	b.n	2851be <uniffi_pbcli_checksum_method_api_base@@Base+0x11893a>
│ │  	ands	r0, r1
│ │  	b.n	284e62 <uniffi_pbcli_checksum_method_api_base@@Base+0x1185de>
│ │  			@ <UNDEFINED> instruction: 0xffda1aff
│ │  	str	r0, [r0, r0]
│ │  	b.n	28526a <uniffi_pbcli_checksum_method_api_base@@Base+0x1189e6>
│ │  			@ <UNDEFINED> instruction: 0xffe0eaff
│ │ -	subs	r7, #110	@ 0x6e
│ │ -	vrsubhn.i64	d21, <illegal reg q0.5>, q0
│ │ -	vmull.p64	<illegal reg q9.5>, d17, d2
│ │ -	vsli.32	d21, d4, #1
│ │ +	subs	r7, #149	@ 0x95
│ │ +	vrsubhn.i64	d21, <illegal reg q0.5>, <illegal reg q11.5>
│ │ +	vmull.p64	<illegal reg q9.5>, d17, d25
│ │ +	vsli.32	d21, d27, #1
│ │  			@ <UNDEFINED> instruction: 0xffe14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	285060 <uniffi_pbcli_checksum_method_api_base@@Base+0x1187dc>
│ │  	beq.n	284a80 <uniffi_pbcli_checksum_method_api_base@@Base+0x1181fc>
│ │  	b.n	284fe4 <uniffi_pbcli_checksum_method_api_base@@Base+0x118760>
│ │  	str	r0, [r0, r0]
│ │  	b.n	284e8e <uniffi_pbcli_checksum_method_api_base@@Base+0x11860a>
│ │ @@ -525077,15 +525077,15 @@
│ │  	b.n	285582 <uniffi_pbcli_checksum_method_api_base@@Base+0x118cfe>
│ │  			@ <UNDEFINED> instruction: 0xfa80ebff
│ │  	movs	r6, r0
│ │  	b.n	28558a <uniffi_pbcli_checksum_method_api_base@@Base+0x118d06>
│ │  	beq.n	285284 <uniffi_pbcli_checksum_method_api_base@@Base+0x118a00>
│ │  	b.n	2856e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x118e60>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r2, r4, r9, fp, ip, sp}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r5, r9, fp, ip, sp}
│ │  	vrsra.u32	d30, d28, #31
│ │  			@ <UNDEFINED> instruction: 0xffe04ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	28577c <uniffi_pbcli_checksum_method_api_base@@Base+0x118ef8>
│ │  	beq.n	2851ec <uniffi_pbcli_checksum_method_api_base@@Base+0x118968>
│ │  	b.n	285700 <uniffi_pbcli_checksum_method_api_base@@Base+0x118e7c>
│ │  	str	r0, [sp, #4]
│ │ @@ -525819,15 +525819,15 @@
│ │  	movs	r2, r1
│ │  	b.n	285bda <uniffi_pbcli_checksum_method_api_base@@Base+0x119356>
│ │  	str??.w	lr, [sl, #3071]	@ 0xbff
│ │  	movs	r0, r2
│ │  	b.n	285dbc <uniffi_pbcli_checksum_method_api_base@@Base+0x119538>
│ │  	subs	r2, r0, #7
│ │  			@ <UNDEFINED> instruction: 0xeb00fe8f
│ │ -			@ <UNDEFINED> instruction: 0xeaff333e
│ │ +			@ <UNDEFINED> instruction: 0xeaff3365
│ │  	vmull.u32	q10, d1, d28
│ │  			@ <UNDEFINED> instruction: 0xffdf4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	285dd4 <uniffi_pbcli_checksum_method_api_base@@Base+0x119550>
│ │  	beq.n	285984 <uniffi_pbcli_checksum_method_api_base@@Base+0x119100>
│ │  	b.n	285d58 <uniffi_pbcli_checksum_method_api_base@@Base+0x1194d4>
│ │  	str	r0, [sp, #0]
│ │ @@ -526875,18 +526875,18 @@
│ │  	b.n	285b98 <uniffi_pbcli_checksum_method_api_base@@Base+0x119314>
│ │  	bfcsel	1a, 286962 <uniffi_pbcli_checksum_method_api_base@@Base+0x11a0de>, 1c, al
│ │  	movs	r1, r1
│ │  	b.n	2864aa <uniffi_pbcli_checksum_method_api_base@@Base+0x119c26>
│ │  	beq.n	2861a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x119920>
│ │  	b.n	286604 <uniffi_pbcli_checksum_method_api_base@@Base+0x119d80>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r6, r7, sl, fp, sp}
│ │ +	ldmia.w	sp!, {r0, r2, r8, sl, fp, sp}
│ │  	vrsubhn.i64	d16, <illegal reg q8.5>, q1
│ │ -			@ <UNDEFINED> instruction: 0xffe02b16
│ │ -	vraddhn.i64	d18, <illegal reg q8.5>, q15
│ │ +			@ <UNDEFINED> instruction: 0xffe02b3d
│ │ +	vsri.64	q9, <illegal reg q2.5>, #31
│ │  	vmlal.u32	q10, d1, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2864ca <uniffi_pbcli_checksum_method_api_base@@Base+0x119c46>
│ │  	movs	r0, #0
│ │  	b.n	2864ce <uniffi_pbcli_checksum_method_api_base@@Base+0x119c4a>
│ │  	movs	r0, r0
│ │  	b.n	2868d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x11a04e>
│ │ @@ -529328,17 +529328,17 @@
│ │  	b.n	2879b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x11b12e>
│ │  	movs	r0, #222	@ 0xde
│ │  	b.n	287db6 <uniffi_pbcli_checksum_method_api_base@@Base+0x11b532>
│ │  	asrs	r1, r0, #32
│ │  	b.n	287798 <uniffi_pbcli_checksum_method_api_base@@Base+0x11af14>
│ │  	ldr	r4, [pc, #64]	@ (2876bc <uniffi_pbcli_checksum_method_api_base@@Base+0x11ae38>)
│ │  	ldmia.w	sp!, {r1, r4, r9, sl, ip, lr}
│ │ -			@ <UNDEFINED> instruction: 0xea02802d
│ │ -	vmla.i32	q12, <illegal reg q0.5>, d5[0]
│ │ -	vaddl.u32	q12, d1, d1
│ │ +			@ <UNDEFINED> instruction: 0xea028054
│ │ +	vmla.i32	q12, <illegal reg q0.5>, d12[1]
│ │ +	vaddl.u32	q12, d1, d24
│ │  	vshr.u32	d16, d0, #31
│ │  	b.n	2871b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x11a92e>
│ │  	movs	r1, r0
│ │  	b.n	287696 <uniffi_pbcli_checksum_method_api_base@@Base+0x11ae12>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (2876dc <uniffi_pbcli_checksum_method_api_base@@Base+0x11ae58>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │ @@ -529393,17 +529393,17 @@
│ │  	b.n	287a4a <uniffi_pbcli_checksum_method_api_base@@Base+0x11b1c6>
│ │  	movs	r0, #233	@ 0xe9
│ │  	b.n	287e4e <uniffi_pbcli_checksum_method_api_base@@Base+0x11b5ca>
│ │  	asrs	r1, r0, #32
│ │  	b.n	287830 <uniffi_pbcli_checksum_method_api_base@@Base+0x11afac>
│ │  	ldr	r4, [pc, #64]	@ (287754 <uniffi_pbcli_checksum_method_api_base@@Base+0x11aed0>)
│ │  	ldmia.w	sp!, {r2, r3, r5, r6, r7, r8, sl, ip, lr}
│ │ -	and.w	pc, r2, sp, lsl #30
│ │ -			@ <UNDEFINED> instruction: 0xffe17fa9
│ │ -	vqrdmlsh.s32	<illegal reg q11.5>, <illegal reg q0.5>, d9[1]
│ │ +	and.w	pc, r2, r4, ror #30
│ │ +			@ <UNDEFINED> instruction: 0xffe17fd0
│ │ +			@ <UNDEFINED> instruction: 0xffe17f90
│ │  	vshr.u32	q8, q0, #31
│ │  	movt	r0, #256	@ 0x100
│ │  	b.n	287e6e <uniffi_pbcli_checksum_method_api_base@@Base+0x11b5ea>
│ │  	lsrs	r5, r1, #10
│ │  	orr.w	r0, r0, #2097152	@ 0x200000
│ │  	b.n	287236 <uniffi_pbcli_checksum_method_api_base@@Base+0x11a9b2>
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -529424,15 +529424,15 @@
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	asrs	r1, r0, #32
│ │  	asrs	r0, r4, #14
│ │  	asrs	r0, r2, #32
│ │  	asrs	r0, r0, #22
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r5, r8, r9, sl, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r4, r6, r8, r9, sl, fp, ip, sp, lr}
│ │  	vmlal.u32	q10, d1, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	287ab6 <uniffi_pbcli_checksum_method_api_base@@Base+0x11b232>
│ │  	asrs	r0, r4, #32
│ │  	b.n	2872b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x11aa34>
│ │  	movs	r4, r2
│ │  	b.n	287ebe <uniffi_pbcli_checksum_method_api_base@@Base+0x11b63a>
│ │ @@ -529446,15 +529446,15 @@
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	asrs	r1, r1, #32
│ │  	asrs	r0, r4, #14
│ │  	asrs	r0, r2, #32
│ │  	asrs	r0, r0, #22
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r6, r7, r9, sl, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r8, r9, sl, fp, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffe148f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	287cc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x11b440>
│ │  	ands	r0, r0
│ │  	b.n	287aee <uniffi_pbcli_checksum_method_api_base@@Base+0x11b26a>
│ │  	movs	r0, r1
│ │  	b.n	2872d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x11aa4e>
│ │ @@ -529605,22 +529605,22 @@
│ │  	add.w	r0, r2, r8, lsl #20
│ │  	b.n	2873fe <uniffi_pbcli_checksum_method_api_base@@Base+0x11ab7a>
│ │  	str	r0, [r0, #0]
│ │  	b.n	287402 <uniffi_pbcli_checksum_method_api_base@@Base+0x11ab7e>
│ │  	movs	r4, r0
│ │  	b.n	287c3e <uniffi_pbcli_checksum_method_api_base@@Base+0x11b3ba>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r5, r7, r9, sl, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r3, r6, r7, r9, sl, fp, ip, sp, lr}
│ │  	vabdl.u32	<illegal reg q8.5>, d1, d17
│ │ -	vqrdmlah.s32	<illegal reg q11.5>, q0, d9[0]
│ │ +	vcvt.f32.u32	<illegal reg q11.5>, q8, #32
│ │  	vmlsl.u32	<illegal reg q8.5>, d17, d9[0]
│ │ -	vcvt.f32.u32	d23, d9, #32
│ │ -	vqrdmlah.s32	<illegal reg q11.5>, <illegal reg q0.5>, d5[1]
│ │ -			@ <UNDEFINED> instruction: 0xffe17d8d
│ │ -			@ <UNDEFINED> instruction: 0xffe17da5
│ │ +	vqrdmlah.s32	<illegal reg q11.5>, q0, d0[0]
│ │ +	vmull.p64	<illegal reg q11.5>, d17, d12
│ │ +			@ <UNDEFINED> instruction: 0xffe17db4
│ │ +	vqrdmulh.s32	<illegal reg q11.5>, <illegal reg q8.5>, d12[0]
│ │  	vcvt.f16.u16	q10, q8, #31
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	287e44 <uniffi_pbcli_checksum_method_api_base@@Base+0x11b5c0>
│ │  	movs	r0, r0
│ │  	b.n	287fce <uniffi_pbcli_checksum_method_api_base@@Base+0x11b74a>
│ │  	lsls	r3, r0, #1
│ │  	lsrs	r0, r0, #8
│ │ @@ -529750,18 +529750,18 @@
│ │  	b.n	28817a <uniffi_pbcli_checksum_method_api_base@@Base+0x11b8f6>
│ │  	asrs	r1, r0, #32
│ │  	b.n	287b5c <uniffi_pbcli_checksum_method_api_base@@Base+0x11b2d8>
│ │  	strb	r2, [r4, r4]
│ │  	add.w	r0, r2, r0
│ │  	b.n	288186 <uniffi_pbcli_checksum_method_api_base@@Base+0x11b902>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r4, r5, r8, sl, fp, ip, sp, lr}
│ │ -	vqdmulh.s32	<illegal reg q11.5>, <illegal reg q0.5>, d1[1]
│ │ -	vcvt.f16.u16	<illegal reg q11.5>, <illegal reg q12.5>, #31
│ │ -	vcvt.f16.u16	d23, d29, #31
│ │ +	ldmia.w	sp!, {r3, r4, r6, r8, sl, fp, ip, sp, lr}
│ │ +	vmull.u32	<illegal reg q11.5>, d17, d8
│ │ +	vmull.u32	<illegal reg q11.5>, d17, d16
│ │ +	vqdmulh.s32	<illegal reg q11.5>, <illegal reg q0.5>, d4[1]
│ │  	vcvt.f16.u16	q10, q8, #31
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	287f7c <uniffi_pbcli_checksum_method_api_base@@Base+0x11b6f8>
│ │  	str	r1, [r0, r0]
│ │  	b.n	287da6 <uniffi_pbcli_checksum_method_api_base@@Base+0x11b522>
│ │  	asrs	r0, r2, #32
│ │  	b.n	28760c <uniffi_pbcli_checksum_method_api_base@@Base+0x11ad88>
│ │ @@ -530312,18 +530312,18 @@
│ │  	b.n	288646 <uniffi_pbcli_checksum_method_api_base@@Base+0x11bdc2>
│ │  	asrs	r1, r0, #32
│ │  	b.n	288028 <uniffi_pbcli_checksum_method_api_base@@Base+0x11b7a4>
│ │  	strh	r7, [r5, r7]
│ │  			@ <UNDEFINED> instruction: 0xeb02c000
│ │  	b.n	288652 <uniffi_pbcli_checksum_method_api_base@@Base+0x11bdce>
│ │  			@ <UNDEFINED> instruction: 0xffdceaff
│ │ -	ldrb	r5, [r6, #8]
│ │ -	vqshl.u64	d23, d13, #33	@ 0x21
│ │ -	vqshl.u64	d23, d21, #33	@ 0x21
│ │ -	vqshl.u32	<illegal reg q11.5>, <illegal reg q8.5>, #1
│ │ +	ldrb	r4, [r3, #9]
│ │ +			@ <UNDEFINED> instruction: 0xffe177c4
│ │ +	vqshl.u64	<illegal reg q11.5>, q6, #33	@ 0x21
│ │ +	vqshl.u64	d23, d8, #33	@ 0x21
│ │  	vaddl.u32	q8, d1, d0
│ │  	b.n	2885ce <uniffi_pbcli_checksum_method_api_base@@Base+0x11bd4a>
│ │  	movs	r0, r0
│ │  	mvns	r0, r4
│ │  	vrhadd.u16	d4, d14, d31
│ │  	ldr	r0, [pc, #0]	@ (287f34 <uniffi_pbcli_checksum_method_api_base@@Base+0x11b6b0>)
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │ @@ -531791,26 +531791,26 @@
│ │  	movs	r4, r1
│ │  	b.n	2892da <uniffi_pbcli_checksum_method_api_base@@Base+0x11ca56>
│ │  	movs	r4, #74	@ 0x4a
│ │  	b.n	28919e <uniffi_pbcli_checksum_method_api_base@@Base+0x11c91a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	288cc0 <uniffi_pbcli_checksum_method_api_base@@Base+0x11c43c>
│ │  	ldr	r7, [pc, #728]	@ (288e7c <uniffi_pbcli_checksum_method_api_base@@Base+0x11c5f8>)
│ │ -	and.w	sl, r2, r9, lsr #27
│ │ +	and.w	fp, r2, r0, lsl #24
│ │  	vaddl.u32	q8, d1, d0
│ │  	b.n	28924e <uniffi_pbcli_checksum_method_api_base@@Base+0x11c9ca>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	asrs	r0, r1, #32
│ │  	b.n	2886f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x11be70>
│ │  	movs	r4, #84	@ 0x54
│ │  	b.n	2891ba <uniffi_pbcli_checksum_method_api_base@@Base+0x11c936>
│ │  	asrs	r1, r0, #32
│ │  	b.n	288cdc <uniffi_pbcli_checksum_method_api_base@@Base+0x11c458>
│ │  	str	r2, [r0, r3]
│ │ -	and.w	sl, r2, sp, ror #26
│ │ +	and.w	sl, r2, r4, asr #27
│ │  	vshr.u32	d18, d0, #31
│ │  	b.n	2886ea <uniffi_pbcli_checksum_method_api_base@@Base+0x11be66>
│ │  	asrs	r1, r0, #32
│ │  	b.n	288ed2 <uniffi_pbcli_checksum_method_api_base@@Base+0x11c64e>
│ │  	asrs	r0, r2, #32
│ │  	b.n	2886d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x11be4e>
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -538105,17 +538105,17 @@
│ │  			@ <UNDEFINED> instruction: 0xebfffe3d
│ │  			@ <UNDEFINED> instruction: 0xeaff0001
│ │  	b.n	28ccde <uniffi_pbcli_checksum_method_api_base@@Base+0x12045a>
│ │  	strb	r1, [r0, #0]
│ │  	asrs	r0, r4, #14
│ │  			@ <UNDEFINED> instruction: 0xfff4eaff
│ │  			@ <UNDEFINED> instruction: 0xb8b3
│ │ -	vabdl.u16	q14, d31, d13
│ │ +	vqshl.u64	d28, d20, #31
│ │  	vmul.i32	<illegal reg q13.5>, q0, d7[1]
│ │ -			@ <UNDEFINED> instruction: 0xffdfc741
│ │ +			@ <UNDEFINED> instruction: 0xffdfc768
│ │  	vmlal.u32	<illegal reg q13.5>, d0, d31
│ │  	vqshrun.s32	d30, q0, #1
│ │  	vsli.32	d30, d4, #1
│ │  	vsri.64	d30, d20, #31
│ │  	vrsubhn.i64	d30, <illegal reg q8.5>, q8
│ │  	vqshlu.s32	d30, d24, #1
│ │  	vsra.u32	<illegal reg q13.5>, <illegal reg q1.5>, #31
│ │ @@ -539179,18 +539179,18 @@
│ │  	b.n	28d09c <uniffi_pbcli_checksum_method_api_base@@Base+0x120818>
│ │  	eors	r6, r5
│ │  	add.w	r0, r2, r5
│ │  	b.n	28d2c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x120a42>
│ │  	beq.n	28cfc0 <uniffi_pbcli_checksum_method_api_base@@Base+0x12073c>
│ │  	b.n	28d420 <uniffi_pbcli_checksum_method_api_base@@Base+0x120b9c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r2, r7, sl, sp, lr, pc}
│ │ -	vsubl.u32	q15, d16, d19
│ │ -	vsri.32	d30, d3, #32
│ │ -	vqshrun.s64	d27, <illegal reg q7.5>, #32
│ │ +	ldmia.w	sp!, {r1, r2, r3, r5, r7, sl, sp, lr, pc}
│ │ +	vmlal.u32	q15, d16, d10[0]
│ │ +	vsri.32	d30, d26, #32
│ │ +	vmul.i32	<illegal reg q13.5>, q0, d6[0]
│ │  	vmlal.u32	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	28d2e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x120a62>
│ │  	beq.n	28cfc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x120744>
│ │  	b.n	28d444 <uniffi_pbcli_checksum_method_api_base@@Base+0x120bc0>
│ │  	stmia	r0!, {r1}
│ │  	b.n	28d2ee <uniffi_pbcli_checksum_method_api_base@@Base+0x120a6a>
│ │ @@ -539462,22 +539462,22 @@
│ │  	movs	r0, #36	@ 0x24
│ │  	b.n	28cd50 <uniffi_pbcli_checksum_method_api_base@@Base+0x1204cc>
│ │  	movs	r0, r0
│ │  	b.n	28d334 <uniffi_pbcli_checksum_method_api_base@@Base+0x120ab0>
│ │  	movs	r0, #2
│ │  	b.n	28d338 <uniffi_pbcli_checksum_method_api_base@@Base+0x120ab4>
│ │  			@ <UNDEFINED> instruction: 0xffc7eaff
│ │ -	b.n	28d5ae <uniffi_pbcli_checksum_method_api_base@@Base+0x120d2a>
│ │ -	vmull.u32	<illegal reg q15.5>, d0, d6[0]
│ │ -	vsra.u64	q15, <illegal reg q9.5>, #32
│ │ -			@ <UNDEFINED> instruction: 0xffe0fa72
│ │ -	vmla.i32	q15, q8, d7[1]
│ │ -	vmul.f32	<illegal reg q15.5>, q0, d6[1]
│ │ -	vaddl.u32	q15, d0, d11
│ │ -	vmlal.u32	<illegal reg q15.5>, d16, d10
│ │ +	b.n	28d5fc <uniffi_pbcli_checksum_method_api_base@@Base+0x120d78>
│ │ +	vmull.u32	<illegal reg q15.5>, d0, d13[1]
│ │ +	vrshr.u32	d30, d10, #32
│ │ +			@ <UNDEFINED> instruction: 0xffe0fa99
│ │ +	vaddw.u32	q15, q0, d14
│ │ +			@ <UNDEFINED> instruction: 0xffe0f98d
│ │ +	vshr.u32	d30, d18, #32
│ │ +			@ <UNDEFINED> instruction: 0xffe0f8b1
│ │  	vmlal.u32	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	28d586 <uniffi_pbcli_checksum_method_api_base@@Base+0x120d02>
│ │  	beq.n	28d258 <uniffi_pbcli_checksum_method_api_base@@Base+0x1209d4>
│ │  	b.n	28d6e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x120e60>
│ │  	stmia	r0!, {r1}
│ │  	b.n	28d58e <uniffi_pbcli_checksum_method_api_base@@Base+0x120d0a>
│ │ @@ -539648,20 +539648,20 @@
│ │  	add.w	r0, r1, r0, lsl #16
│ │  	b.n	28db0a <uniffi_pbcli_checksum_method_api_base@@Base+0x121286>
│ │  	movs	r3, r0
│ │  	b.n	28db0e <uniffi_pbcli_checksum_method_api_base@@Base+0x12128a>
│ │  	asrs	r1, r6, #1
│ │  	b.n	28db12 <uniffi_pbcli_checksum_method_api_base@@Base+0x12128e>
│ │  			@ <UNDEFINED> instruction: 0xffcbeaff
│ │ -	svc	51	@ 0x33
│ │ -	vqrdmlsh.s32	<illegal reg q14.5>, q0, d3[0]
│ │ -	vcvt.u32.f32	<illegal reg q14.5>, <illegal reg q7.5>, #32
│ │ -	vqrdmlsh.s32	<illegal reg q14.5>, q0, d15[1]
│ │ -	vqrdmlah.s32	<illegal reg q14.5>, q0, d3[1]
│ │ -	vcvt.f32.u32	<illegal reg q14.5>, <illegal reg q9.5>, #32
│ │ +	svc	90	@ 0x5a
│ │ +	vqrdmlsh.s32	<illegal reg q14.5>, q0, d10[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe0df86
│ │ +			@ <UNDEFINED> instruction: 0xffe0df96
│ │ +	vmull.p64	<illegal reg q14.5>, d16, d10
│ │ +			@ <UNDEFINED> instruction: 0xffe0de9a
│ │  			@ <UNDEFINED> instruction: 0xffe04ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	28d910 <uniffi_pbcli_checksum_method_api_base@@Base+0x12108c>
│ │  	svc	65	@ 0x41
│ │  	b.n	28d894 <uniffi_pbcli_checksum_method_api_base@@Base+0x121010>
│ │  	adds	r0, #20
│ │  	b.n	28cf18 <uniffi_pbcli_checksum_method_api_base@@Base+0x120694>
│ │ @@ -540047,23 +540047,23 @@
│ │  			@ <UNDEFINED> instruction: 0xea00a001
│ │  	b.n	28de8a <uniffi_pbcli_checksum_method_api_base@@Base+0x121606>
│ │  	str	r0, [r3, #0]
│ │  	b.n	28d288 <uniffi_pbcli_checksum_method_api_base@@Base+0x120a04>
│ │  	str	r0, [r2, r0]
│ │  	b.n	28d28c <uniffi_pbcli_checksum_method_api_base@@Base+0x120a08>
│ │  			@ <UNDEFINED> instruction: 0xffe3eaff
│ │ -	ble.n	28d6e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x120e62>
│ │ -			@ <UNDEFINED> instruction: 0xffe0db8b
│ │ -			@ <UNDEFINED> instruction: 0xffe0f3ea
│ │ -			@ <UNDEFINED> instruction: 0xffe0ddbd
│ │ -			@ <UNDEFINED> instruction: 0xffe0dbcf
│ │ -	vraddhn.i64	d31, q0, q15
│ │ -			@ <UNDEFINED> instruction: 0xffe0db17
│ │ -			@ <UNDEFINED> instruction: 0xffe0db5f
│ │ -	vrsra.u64	d31, d30, #32
│ │ +	ble.n	28d734 <uniffi_pbcli_checksum_method_api_base@@Base+0x120eb0>
│ │ +			@ <UNDEFINED> instruction: 0xffe0dbb2
│ │ +	vsri.32	d31, d1, #32
│ │ +	vqrdmulh.s32	<illegal reg q14.5>, q8, d4[1]
│ │ +			@ <UNDEFINED> instruction: 0xffe0dbf6
│ │ +	vsri.32	<illegal reg q15.5>, <illegal reg q2.5>, #32
│ │ +			@ <UNDEFINED> instruction: 0xffe0db3e
│ │ +			@ <UNDEFINED> instruction: 0xffe0db86
│ │ +			@ <UNDEFINED> instruction: 0xffe0f3e5
│ │  	vcvt.f16.u16	d20, d0, #32
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	28dc9c <uniffi_pbcli_checksum_method_api_base@@Base+0x121418>
│ │  	lsls	r0, r2, #1
│ │  	movt	r0, #1024	@ 0x400
│ │  	b.n	28daca <uniffi_pbcli_checksum_method_api_base@@Base+0x121246>
│ │  	asrs	r0, r0, #32
│ │ @@ -540106,15 +540106,15 @@
│ │  	movs	r0, #40	@ 0x28
│ │  	b.n	28df2a <uniffi_pbcli_checksum_method_api_base@@Base+0x1216a6>
│ │  	asrs	r1, r0, #32
│ │  	b.n	28d90c <uniffi_pbcli_checksum_method_api_base@@Base+0x121088>
│ │  	ldr	r4, [pc, #64]	@ (28d830 <uniffi_pbcli_checksum_method_api_base@@Base+0x120fac>)
│ │  	ldmia.w	sp!, {r0, r2, r4, r5, r7, r8, sl, fp, ip, sp}
│ │  			@ <UNDEFINED> instruction: 0xea028c10
│ │ -	ldmia.w	sp!, {r0, r1, r6, r7, r9, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r5, r6, r7, r9, ip, sp, lr, pc}
│ │  	vcvt.f16.u16	q10, q8, #32
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	28dd20 <uniffi_pbcli_checksum_method_api_base@@Base+0x12149c>
│ │  	ands	r0, r0
│ │  	b.n	28db4a <uniffi_pbcli_checksum_method_api_base@@Base+0x1212c6>
│ │  	movs	r1, r0
│ │  	b.n	28db4e <uniffi_pbcli_checksum_method_api_base@@Base+0x1212ca>
│ │ @@ -540645,15 +540645,15 @@
│ │  	asrs	r4, r1, #32
│ │  	b.n	28d7d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x120f54>
│ │  	movs	r4, r1
│ │  	b.n	28d7a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x120f20>
│ │  	movs	r1, r0
│ │  	b.n	28e3e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x121b62>
│ │  			@ <UNDEFINED> instruction: 0xffe1eaff
│ │ -	cdp	15, 12, cr15, cr11, cr0, {7}
│ │ +	cdp	15, 15, cr15, cr2, cr0, {7}
│ │  	lsrs	r4, r1, #19
│ │  	vcvt.f16.u16	q10, q8, #32
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	28e1d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x121950>
│ │  	str	r1, [r0, r0]
│ │  	b.n	28dffe <uniffi_pbcli_checksum_method_api_base@@Base+0x12177a>
│ │  	str	r0, [r0, #0]
│ │ @@ -541383,15 +541383,15 @@
│ │  	ldmia.w	sl, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, fp, sp, lr, pc}
│ │  	movs	r5, r0
│ │  	b.n	28e66a <uniffi_pbcli_checksum_method_api_base@@Base+0x121de6>
│ │  	beq.n	28e364 <uniffi_pbcli_checksum_method_api_base@@Base+0x121ae0>
│ │  	b.n	28e7c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x121f40>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r1, r4, r5, r7, r8, sl, ip, sp}
│ │ -	vqshrun.s32	d30, <illegal reg q9.5>, #1
│ │ +	vqrshrun.s32	d30, q5, #1
│ │  			@ <UNDEFINED> instruction: 0xffe04ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	28e85c <uniffi_pbcli_checksum_method_api_base@@Base+0x121fd8>
│ │  	beq.n	28e35c <uniffi_pbcli_checksum_method_api_base@@Base+0x121ad8>
│ │  	b.n	28e7e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x121f5c>
│ │  	str	r0, [sp, #0]
│ │  	b.n	28e68a <uniffi_pbcli_checksum_method_api_base@@Base+0x121e06>
│ │ @@ -544141,15 +544141,15 @@
│ │  	b.n	28f660 <uniffi_pbcli_checksum_method_api_base@@Base+0x122ddc>
│ │  	movs	r4, r0
│ │  	b.n	28fe9a <uniffi_pbcli_checksum_method_api_base@@Base+0x123616>
│ │  	beq.n	28fb8c <uniffi_pbcli_checksum_method_api_base@@Base+0x123308>
│ │  	b.n	28fff4 <uniffi_pbcli_checksum_method_api_base@@Base+0x123770>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r1, r3, r5, r7, r8, r9, sl, fp, sp, lr, pc}
│ │ -	vqdmulh.s16	<illegal reg q15.5>, q7, d4[0]
│ │ +	vqdmulh.s16	<illegal reg q15.5>, q7, d3[3]
│ │  			@ <UNDEFINED> instruction: 0xffe0ef06
│ │  			@ <UNDEFINED> instruction: 0xffdeeeb6
│ │  			@ <UNDEFINED> instruction: 0xffdeef22
│ │  	vqshrun.s32	d20, q8, #2
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	290098 <uniffi_pbcli_checksum_method_api_base@@Base+0x123814>
│ │  	movs	r0, r0
│ │ @@ -544603,17 +544603,17 @@
│ │  	b.n	29069a <uniffi_pbcli_checksum_method_api_base@@Base+0x123e16>
│ │  			@ <UNDEFINED> instruction: 0xffe7eaff
│ │  	str	r3, [r7, r1]
│ │  	b.n	2906a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x123e1e>
│ │  	str	r0, [sp, #712]	@ 0x2c8
│ │  	b.n	2906a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x123e22>
│ │  			@ <UNDEFINED> instruction: 0xffe4eaff
│ │ -	subs	r6, #47	@ 0x2f
│ │ +	subs	r6, #86	@ 0x56
│ │  	vsubl.u32	<illegal reg q14.5>, d17, d20
│ │ -	vqrdmulh.s16	<illegal reg q9.5>, q15, d3[1]
│ │ +			@ <UNDEFINED> instruction: 0xffde3df2
│ │  	vmlal.u32	<illegal reg q14.5>, d1, d0[0]
│ │  			@ <UNDEFINED> instruction: 0xffde48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	29049c <uniffi_pbcli_checksum_method_api_base@@Base+0x123c18>
│ │  	beq.n	28ffa4 <uniffi_pbcli_checksum_method_api_base@@Base+0x123720>
│ │  	b.n	290420 <uniffi_pbcli_checksum_method_api_base@@Base+0x123b9c>
│ │  	strb	r0, [r0, #0]
│ │ @@ -545678,31 +545678,31 @@
│ │  	b.n	290998 <uniffi_pbcli_checksum_method_api_base@@Base+0x124114>
│ │  	cbz	r5, 2908a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x124024>
│ │  			@ <UNDEFINED> instruction: 0xebff0001
│ │  	b.n	290f22 <uniffi_pbcli_checksum_method_api_base@@Base+0x12469e>
│ │  	ands	r1, r0
│ │  	add	r3, pc, #640	@ (adr r3, 290b04 <uniffi_pbcli_checksum_method_api_base@@Base+0x124280>)
│ │  			@ <UNDEFINED> instruction: 0xff82eaff
│ │ -	ldr	r0, [r4, #104]	@ 0x68
│ │ -			@ <UNDEFINED> instruction: 0xffe0db61
│ │ -	vsli.64	d19, d12, #32
│ │ +	ldr	r7, [r0, #108]	@ 0x6c
│ │ +			@ <UNDEFINED> instruction: 0xffe0db88
│ │ +	vmls.f32	<illegal reg q9.5>, q8, d3[0]
│ │  	vqshl.u32	d24, d12, #1
│ │  	vqrdmlsh.s16	q11, <illegal reg q7.5>, d4[0]
│ │  			@ <UNDEFINED> instruction: 0xffdf3d57
│ │ -			@ <UNDEFINED> instruction: 0xffe07dfe
│ │ -			@ <UNDEFINED> instruction: 0xffe07d02
│ │ -			@ <UNDEFINED> instruction: 0xffe0eeb2
│ │ -	vcvt.u32.f32	<illegal reg q11.5>, q1, #32
│ │ +	vmull.p64	<illegal reg q11.5>, d0, d21
│ │ +			@ <UNDEFINED> instruction: 0xffe07d29
│ │ +			@ <UNDEFINED> instruction: 0xffe0eed9
│ │ +	vcvt.u32.f32	<illegal reg q11.5>, <illegal reg q12.5>, #32
│ │  	vsra.u64	d24, d7, #32
│ │  			@ <UNDEFINED> instruction: 0xffdeceb8
│ │  			@ <UNDEFINED> instruction: 0xffdf2af0
│ │ -	vrsra.u32	d24, d30, #32
│ │ +			@ <UNDEFINED> instruction: 0xffe08365
│ │  			@ <UNDEFINED> instruction: 0xffe029f4
│ │ -	vcvt.u32.f32	q15, q3, #32
│ │ -	vsubw.u32	<illegal reg q15.5>, q0, d15
│ │ +	vcvt.u32.f32	q15, <illegal reg q14.5>, #32
│ │ +	vrsra.u32	d31, d22, #32
│ │  			@ <UNDEFINED> instruction: 0xffe04bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	290df0 <uniffi_pbcli_checksum_method_api_base@@Base+0x12456c>
│ │  	strh	r3, [r0, #0]
│ │  	b.n	290c1a <uniffi_pbcli_checksum_method_api_base@@Base+0x124396>
│ │  	str	r0, [sp, #8]
│ │  	b.n	290c1e <uniffi_pbcli_checksum_method_api_base@@Base+0x12439a>
│ │ @@ -545839,15 +545839,15 @@
│ │  	b.n	290d36 <uniffi_pbcli_checksum_method_api_base@@Base+0x1244b2>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	29113e <uniffi_pbcli_checksum_method_api_base@@Base+0x1248ba>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r2, r4, r7, r9, sl, fp, sp, pc}
│ │  	vcvt.f32.u32	q13, q2, #31
│ │ -	vrsra.u32	d21, d11, #31
│ │ +			@ <UNDEFINED> instruction: 0xffe15342
│ │  	vmls.f32	q9, q0, d10[1]
│ │  			@ <UNDEFINED> instruction: 0xffe04ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	290f34 <uniffi_pbcli_checksum_method_api_base@@Base+0x1246b0>
│ │  	beq.n	290a64 <uniffi_pbcli_checksum_method_api_base@@Base+0x1241e0>
│ │  	b.n	290eb8 <uniffi_pbcli_checksum_method_api_base@@Base+0x124634>
│ │  	add	r0, pc, #0	@ (adr r0, 290a20 <uniffi_pbcli_checksum_method_api_base@@Base+0x12419c>)
│ │ @@ -546124,27 +546124,27 @@
│ │  			@ <UNDEFINED> instruction: 0xea009000
│ │  	b.n	2913a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x124b1e>
│ │  	movs	r1, r1
│ │  	b.n	290fa6 <uniffi_pbcli_checksum_method_api_base@@Base+0x124722>
│ │  	beq.n	290ca0 <uniffi_pbcli_checksum_method_api_base@@Base+0x12441c>
│ │  	b.n	291100 <uniffi_pbcli_checksum_method_api_base@@Base+0x12487c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r2, r3, r6, r8, r9}
│ │ -			@ <UNDEFINED> instruction: 0xffe1e9b2
│ │ +	ldmia.w	sp!, {r0, r1, r4, r5, r6, r8, r9}
│ │ +			@ <UNDEFINED> instruction: 0xffe1e9d9
│ │  	vsli.32	<illegal reg q15.5>, q13, #0
│ │  	vqrdmlah.s16	<illegal reg q14.5>, <illegal reg q7.5>, d6[2]
│ │  	vmull.u16	q13, d30, d21
│ │ -	vmlsl.u16	q15, d14, d14
│ │ -	vmovl.u32	<illegal reg q11.5>, d2
│ │ -	vshr.u64	<illegal reg q10.5>, <illegal reg q0.5>, #32
│ │ +	vshll.u16	q15, d21, #14
│ │ +	vmovl.u32	<illegal reg q11.5>, d25
│ │ +	vshr.u64	<illegal reg q10.5>, q12, #32
│ │  	vmull.p64	<illegal reg q14.5>, d0, d9
│ │  	vmls.f16	q14, q7, d2[2]
│ │ -	vmlal.u16	q15, d30, d22
│ │ +	vmul.i16	q15, q15, d5[1]
│ │  	vsubw.u32	q9, q0, d0
│ │ -	vmul.i32	q15, q0, d6[1]
│ │ +	vmlal.u32	q15, d16, d13
│ │  	vcvt.f16.u16	q10, q8, #32
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2911c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x124940>
│ │  	str	r0, [r0, #0]
│ │  	b.n	290fee <uniffi_pbcli_checksum_method_api_base@@Base+0x12476a>
│ │  	movs	r0, r0
│ │  	b.n	2913f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x124b6e>
│ │ @@ -546178,15 +546178,15 @@
│ │  	movs	r0, r0
│ │  	b.n	29139e <uniffi_pbcli_checksum_method_api_base@@Base+0x124b1a>
│ │  	ands	r1, r0
│ │  	stmia	r3!, {}
│ │  	movs	r4, r0
│ │  	b.n	29103a <uniffi_pbcli_checksum_method_api_base@@Base+0x1247b6>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r2, r6, r7, r8, r9, sl, fp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r5, r6, r7, r8, r9, sl, fp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffe048f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	291224 <uniffi_pbcli_checksum_method_api_base@@Base+0x1249a0>
│ │  	beq.n	290dac <uniffi_pbcli_checksum_method_api_base@@Base+0x124528>
│ │  	b.n	2911a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x124924>
│ │  	ands	r0, r0
│ │  	b.n	291052 <uniffi_pbcli_checksum_method_api_base@@Base+0x1247ce>
│ │ @@ -546233,15 +546233,15 @@
│ │  	asrs	r1, r0, #32
│ │  	stmia	r3!, {}
│ │  	movs	r1, r0
│ │  	b.n	2910b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x12482e>
│ │  	beq.n	290d94 <uniffi_pbcli_checksum_method_api_base@@Base+0x124510>
│ │  	b.n	29120c <uniffi_pbcli_checksum_method_api_base@@Base+0x124988>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r6, r8, r9, sl, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r7, r8, r9, sl, sp, lr, pc}
│ │  	vsra.u32	<illegal reg q13.5>, q12, #32
│ │  			@ <UNDEFINED> instruction: 0xffdf4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2912a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x124a20>
│ │  	str	r0, [r0, r0]
│ │  	b.n	2910ce <uniffi_pbcli_checksum_method_api_base@@Base+0x12484a>
│ │  	movs	r4, r0
│ │ @@ -546301,15 +546301,15 @@
│ │  	movs	r1, r0
│ │  	b.n	291546 <uniffi_pbcli_checksum_method_api_base@@Base+0x124cc2>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {}
│ │  	b.n	29154e <uniffi_pbcli_checksum_method_api_base@@Base+0x124cca>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r4, r7, sl, ip, sp, lr, pc}
│ │ -	vabdl.u16	<illegal reg q11.5>, d30, d26
│ │ +	vqshl.u64	<illegal reg q11.5>, <illegal reg q0.5>, #30
│ │  	vaddl.u32	q8, d0, d4
│ │  	b.n	29095c <uniffi_pbcli_checksum_method_api_base@@Base+0x1240d8>
│ │  	movs	r0, r0
│ │  	b.n	290f40 <uniffi_pbcli_checksum_method_api_base@@Base+0x1246bc>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	str	r0, [r6, r2]
│ │  	movs	r1, r4
│ │ @@ -546746,36 +546746,36 @@
│ │  	b.n	29187a <uniffi_pbcli_checksum_method_api_base@@Base+0x124ff6>
│ │  	movs	r5, r1
│ │  	b.n	29193e <uniffi_pbcli_checksum_method_api_base@@Base+0x1250ba>
│ │  	movs	r0, #0
│ │  	b.n	291942 <uniffi_pbcli_checksum_method_api_base@@Base+0x1250be>
│ │  	asrs	r4, r3, #30
│ │  			@ <UNDEFINED> instruction: 0xeb01ffc8
│ │ -			@ <UNDEFINED> instruction: 0xeaffe78c
│ │ -	vqrdmulh.s32	q9, q8, d6[0]
│ │ +			@ <UNDEFINED> instruction: 0xeaffe7b3
│ │ +	vqrdmulh.s32	q9, q8, d13[1]
│ │  	vaddl.u32	<illegal reg q10.5>, d1, d16
│ │  	movs	r1, r4
│ │ -	b.n	2910d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x124854>
│ │ -			@ <UNDEFINED> instruction: 0xffe02d9a
│ │ -	vabdl.u32	q15, d1, d16
│ │ -	vcvt.u16.f16	q9, q5, #32
│ │ -	vsli.64	d30, d16, #33	@ 0x21
│ │ -			@ <UNDEFINED> instruction: 0xffe02bea
│ │ +	b.n	291126 <uniffi_pbcli_checksum_method_api_base@@Base+0x1248a2>
│ │ +	vqrdmulh.s32	q9, q8, d1[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe1e747
│ │ +			@ <UNDEFINED> instruction: 0xffe02d81
│ │ +	vsli.64	q15, <illegal reg q3.5>, #33	@ 0x21
│ │ +	vcvt.f16.u16	d18, d1, #32
│ │  			@ <UNDEFINED> instruction: 0xffe14d90
│ │  	movs	r1, r4
│ │ -	b.n	290cbc <uniffi_pbcli_checksum_method_api_base@@Base+0x124438>
│ │ -			@ <UNDEFINED> instruction: 0xffe02b7e
│ │ -	vsli.32	d30, d8, #1
│ │ -			@ <UNDEFINED> instruction: 0xffe02b52
│ │ -	vsri.64	q15, q14, #31
│ │ -			@ <UNDEFINED> instruction: 0xffe02b36
│ │ +	b.n	290d0a <uniffi_pbcli_checksum_method_api_base@@Base+0x124486>
│ │ +			@ <UNDEFINED> instruction: 0xffe02ba5
│ │ +	vsli.32	d30, d31, #1
│ │ +			@ <UNDEFINED> instruction: 0xffe02b79
│ │ +	vabal.u32	q15, d1, d19
│ │ +			@ <UNDEFINED> instruction: 0xffe02b5d
│ │  	vmull.p64	q10, d1, d8
│ │  	movs	r1, r4
│ │ -	b.n	290bf0 <uniffi_pbcli_checksum_method_api_base@@Base+0x12436c>
│ │ -			@ <UNDEFINED> instruction: 0xffe02b0a
│ │ +	b.n	290c3e <uniffi_pbcli_checksum_method_api_base@@Base+0x1243ba>
│ │ +			@ <UNDEFINED> instruction: 0xffe02b31
│ │  	vqrdmulh.s32	q10, <illegal reg q8.5>, d8[1]
│ │  	movs	r1, r4
│ │  	ldr	r7, [pc, #960]	@ (29161c <uniffi_pbcli_checksum_method_api_base@@Base+0x124d98>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	29177c <uniffi_pbcli_checksum_method_api_base@@Base+0x124ef8>
│ │  	beq.n	29126c <uniffi_pbcli_checksum_method_api_base@@Base+0x1249e8>
│ │  	b.n	291700 <uniffi_pbcli_checksum_method_api_base@@Base+0x124e7c>
│ │ @@ -547044,18 +547044,18 @@
│ │  	movs	r6, r0
│ │  	b.n	2917f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x124f6e>
│ │  	beq.n	2914ec <uniffi_pbcli_checksum_method_api_base@@Base+0x124c68>
│ │  	b.n	29194c <uniffi_pbcli_checksum_method_api_base@@Base+0x1250c8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r2, r4, r5, r6, sl, fp, lr}
│ │  	movs	r1, r4
│ │ -	b.n	291c78 <uniffi_pbcli_checksum_method_api_base@@Base+0x1253f4>
│ │ +	b.n	290cc6 <uniffi_pbcli_checksum_method_api_base@@Base+0x124442>
│ │  			@ <UNDEFINED> instruction: 0xffe04af8
│ │  	movs	r1, r4
│ │ -	b.n	291940 <uniffi_pbcli_checksum_method_api_base@@Base+0x1250bc>
│ │ +	b.n	29198e <uniffi_pbcli_checksum_method_api_base@@Base+0x12510a>
│ │  	vrshr.u64	q11, q5, #32
│ │  			@ <UNDEFINED> instruction: 0xffdf4a50
│ │  	movs	r1, r4
│ │  	ldr	r2, [pc, #864]	@ (291834 <uniffi_pbcli_checksum_method_api_base@@Base+0x124fb0>)
│ │  	movs	r1, r4
│ │  	ldr	r5, [pc, #960]	@ (291898 <uniffi_pbcli_checksum_method_api_base@@Base+0x125014>)
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │ @@ -549217,15 +549217,15 @@
│ │  	b.n	292274 <uniffi_pbcli_checksum_method_api_base@@Base+0x1259f0>
│ │  	str	r0, [sp, #48]	@ 0x30
│ │  	b.n	292278 <uniffi_pbcli_checksum_method_api_base@@Base+0x1259f4>
│ │  	vpmin.u<illegal width 64>	q15, <illegal reg q15.5>, <illegal reg q15.5>
│ │  	strb	r0, [r5, #0]
│ │  	b.n	292280 <uniffi_pbcli_checksum_method_api_base@@Base+0x1259fc>
│ │  			@ <UNDEFINED> instruction: 0xffcbeaff
│ │ -	cbz	r5, 2927ae <uniffi_pbcli_checksum_method_api_base@@Base+0x125f2a>
│ │ +	cbz	r4, 2927b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x125f34>
│ │  	vcvt.f32.u32	d18, d15, #32
│ │  	vaddl.u32	q10, d0, d28
│ │  	b.n	292270 <uniffi_pbcli_checksum_method_api_base@@Base+0x1259ec>
│ │  	movs	r6, r1
│ │  	and.w	r1, r0, ip, lsl #7
│ │  	add.w	r2, r1, r4, asr #2
│ │  	b.n	2922a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x125a1c>
│ │ @@ -549477,20 +549477,20 @@
│ │  	vshr.u16	q9, <illegal reg q7.5>, #2
│ │  	vrshr.u32	d25, d21, #32
│ │  			@ <UNDEFINED> instruction: 0xffde1d5f
│ │  	vcvt.u32.f32	d24, d21, #32
│ │  	vmull.u16	<illegal reg q8.5>, d14, d11
│ │  	vqrdmulh.s32	q12, q8, d1[1]
│ │  	vrsubhn.i32	d27, q7, q1
│ │ -			@ <UNDEFINED> instruction: 0xffdf1ff7
│ │ +	vshr.u16	d18, d14, #1
│ │  	vmls.i32	q9, <illegal reg q8.5>, d6[1]
│ │  	vraddhn.i64	d18, q8, <illegal reg q13.5>
│ │  	vcvt.f32.u32	<illegal reg q8.5>, <illegal reg q7.5>, #32
│ │  	vshr.u32	d25, d21, #32
│ │ -			@ <UNDEFINED> instruction: 0xffdeee9f
│ │ +	vqrdmlah.s16	q15, q15, d6[0]
│ │  	vmull.u32	q14, d0, d4[0]
│ │  	vmls.f16	q11, q15, d6[1]
│ │  	vmls.f16	q9, q7, d7[2]
│ │  	vmull.u32	<illegal reg q8.5>, d16, d11
│ │  	vsli.32	<illegal reg q12.5>, q15, #0
│ │  	vrsra.u16	q9, <illegal reg q9.5>, #2
│ │  			@ <UNDEFINED> instruction: 0xffe01cf3
│ │ @@ -549507,15 +549507,15 @@
│ │  	vcvt.u32.f32	q12, <illegal reg q6.5>, #32
│ │  	vqrdmulh.s16	<illegal reg q8.5>, q15, d3[0]
│ │  			@ <UNDEFINED> instruction: 0xffe08f99
│ │  	vmull.p<illegal width 16>	<illegal reg q8.5>, d30, d7
│ │  	vshr.u32	d18, d7, #32
│ │  	vqrdmlsh.s32	<illegal reg q8.5>, q8, d3[0]
│ │  			@ <UNDEFINED> instruction: 0xffe0ab95
│ │ -			@ <UNDEFINED> instruction: 0xffde2d55
│ │ +			@ <UNDEFINED> instruction: 0xffde2d7c
│ │  	vcvt.u32.f32	d17, d27, #31
│ │  	vmlal.u32	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	292d8a <uniffi_pbcli_checksum_method_api_base@@Base+0x126506>
│ │  	adds	r0, #1
│ │  	b.n	292d8e <uniffi_pbcli_checksum_method_api_base@@Base+0x12650a>
│ │  	asrs	r0, r3, #32
│ │ @@ -549793,15 +549793,15 @@
│ │  	b.n	2927c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x125f42>
│ │  	movs	r6, r0
│ │  	b.n	293002 <uniffi_pbcli_checksum_method_api_base@@Base+0x12677e>
│ │  	beq.n	292cfc <uniffi_pbcli_checksum_method_api_base@@Base+0x126478>
│ │  	b.n	29315c <uniffi_pbcli_checksum_method_api_base@@Base+0x1268d8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r5, r7, sl, fp, ip, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffdf9e9d
│ │ +	vqrdmlah.s16	<illegal reg q12.5>, <illegal reg q15.5>, d4[0]
│ │  			@ <UNDEFINED> instruction: 0xffe0190f
│ │  			@ <UNDEFINED> instruction: 0xffe08ab6
│ │  			@ <UNDEFINED> instruction: 0xffde19df
│ │  			@ <UNDEFINED> instruction: 0xffe0199b
│ │  	vmlal.u32	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	29302a <uniffi_pbcli_checksum_method_api_base@@Base+0x1267a6>
│ │ @@ -550462,15 +550462,15 @@
│ │  	bfx	4, fp
│ │  	movs	r7, r0
│ │  	b.n	2935be <uniffi_pbcli_checksum_method_api_base@@Base+0x126d3a>
│ │  	beq.n	2932b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x126a34>
│ │  	b.n	293718 <uniffi_pbcli_checksum_method_api_base@@Base+0x126e94>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r1, r3, r4, r8, r9, ip}
│ │ -			@ <UNDEFINED> instruction: 0xffe0af89
│ │ +			@ <UNDEFINED> instruction: 0xffe0afb0
│ │  	vsubw.u32	<illegal reg q8.5>, q8, d15
│ │  	vmlal.u32	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2935da <uniffi_pbcli_checksum_method_api_base@@Base+0x126d56>
│ │  	movs	r0, #1
│ │  	b.n	293720 <uniffi_pbcli_checksum_method_api_base@@Base+0x126e9c>
│ │  	movs	r0, r0
│ │ @@ -550604,18 +550604,18 @@
│ │  	ldmia.w	sp!, {r2}
│ │  	b.n	2936fe <uniffi_pbcli_checksum_method_api_base@@Base+0x126e7a>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	292ecc <uniffi_pbcli_checksum_method_api_base@@Base+0x126648>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r3, r4, r5, r6, r7, r9, sl, ip, sp, pc}
│ │  	vrshr.u16	<illegal reg q13.5>, <illegal reg q1.5>, #2
│ │ -	vmlal.u16	<illegal reg q10.5>, d31, d6[2]
│ │ +	vsubw.u16	<illegal reg q10.5>, <illegal reg q7.5>, d13
│ │  	vmull.u32	<illegal reg q15.5>, d16, d2[1]
│ │  	vsra.u64	<illegal reg q8.5>, <illegal reg q7.5>, #34
│ │ -	vcvt.f32.u32	q13, q3, #32
│ │ +	vcvt.f32.u32	q13, <illegal reg q14.5>, #32
│ │  	vcvt.f16.u16	q10, q8, #32
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	293900 <uniffi_pbcli_checksum_method_api_base@@Base+0x12707c>
│ │  	beq.n	2934b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x126c34>
│ │  	b.n	293884 <uniffi_pbcli_checksum_method_api_base@@Base+0x127000>
│ │  	str	r1, [r0, #0]
│ │  	b.n	29372e <uniffi_pbcli_checksum_method_api_base@@Base+0x126eaa>
│ │ @@ -550714,18 +550714,18 @@
│ │  			@ <UNDEFINED> instruction: 0xfff10aff
│ │  	ands	r0, r0
│ │  	b.n	292fd0 <uniffi_pbcli_checksum_method_api_base@@Base+0x12674c>
│ │  	beq.n	2934e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x126c64>
│ │  	b.n	293960 <uniffi_pbcli_checksum_method_api_base@@Base+0x1270dc>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r8, ip}
│ │ -	vaddl.u32	<illegal reg q15.5>, d16, d1
│ │ -	vmlal.u32	q14, d0, d11[0]
│ │ +	vaddl.u32	<illegal reg q15.5>, d16, d24
│ │ +	vrshr.u32	q14, q9, #32
│ │  	vsra.u32	d17, d31, #32
│ │ -	vshr.u64	d31, d17, #32
│ │ +	vshr.u64	<illegal reg q15.5>, q4, #32
│ │  	vmull.p64	q14, d0, d13
│ │  	vshr.u64	<illegal reg q8.5>, <illegal reg q15.5>, #34
│ │  	vmlal.u32	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	293832 <uniffi_pbcli_checksum_method_api_base@@Base+0x126fae>
│ │  	beq.n	293504 <uniffi_pbcli_checksum_method_api_base@@Base+0x126c80>
│ │  	b.n	293990 <uniffi_pbcli_checksum_method_api_base@@Base+0x12710c>
│ │ @@ -551001,15 +551001,15 @@
│ │  	b.n	293e9a <uniffi_pbcli_checksum_method_api_base@@Base+0x127616>
│ │  	movs	r0, r1
│ │  	asrs	r1, r2, #22
│ │  	beq.n	293780 <uniffi_pbcli_checksum_method_api_base@@Base+0x126efc>
│ │  	b.n	293bf8 <uniffi_pbcli_checksum_method_api_base@@Base+0x127374>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r9, ip, sp, pc}
│ │ -	vrsra.u64	d25, d13, #34
│ │ +			@ <UNDEFINED> instruction: 0xffde93c4
│ │  	vqshrun.s64	d20, q8, #32
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	293c90 <uniffi_pbcli_checksum_method_api_base@@Base+0x12740c>
│ │  	beq.n	293788 <uniffi_pbcli_checksum_method_api_base@@Base+0x126f04>
│ │  	b.n	293c14 <uniffi_pbcli_checksum_method_api_base@@Base+0x127390>
│ │  	ands	r0, r0
│ │  	b.n	293ebe <uniffi_pbcli_checksum_method_api_base@@Base+0x12763a>
│ │ @@ -551528,16 +551528,16 @@
│ │  	lsrs	r4, r2, #20
│ │  	add.w	r0, r1, r4
│ │  	b.n	293f6a <uniffi_pbcli_checksum_method_api_base@@Base+0x1276e6>
│ │  	beq.n	293c4c <uniffi_pbcli_checksum_method_api_base@@Base+0x1273c8>
│ │  	b.n	2940c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x127840>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r2, r3, r4, r6, r8, r9, ip, lr}
│ │ -	vsli.16	<illegal reg q9.5>, <illegal reg q2.5>, #15
│ │ -	vqshlu.s32	<illegal reg q11.5>, q6, #0
│ │ +	vsli.16	<illegal reg q9.5>, q14, #15
│ │ +	vrsubhn.i64	d23, q8, <illegal reg q1.5>
│ │  			@ <UNDEFINED> instruction: 0xffe04ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	294160 <uniffi_pbcli_checksum_method_api_base@@Base+0x1278dc>
│ │  	beq.n	293c50 <uniffi_pbcli_checksum_method_api_base@@Base+0x1273cc>
│ │  	b.n	2940e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x127860>
│ │  	movs	r0, r0
│ │  	b.n	2942f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x127a70>
│ │ @@ -551802,15 +551802,15 @@
│ │  	movs	r0, #0
│ │  	b.n	2945d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x127d52>
│ │  	lsrs	r7, r6, #17
│ │  	add.w	r0, r1, r4
│ │  	b.n	2941de <uniffi_pbcli_checksum_method_api_base@@Base+0x12795a>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r2, r3, r4, r5, r7, ip, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffdf1e57
│ │ +			@ <UNDEFINED> instruction: 0xffdf1e7e
│ │  	vaddl.u32	q8, d0, d0
│ │  	b.n	29454e <uniffi_pbcli_checksum_method_api_base@@Base+0x127cca>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	asrs	r0, r0, #32
│ │  	b.n	2939d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x127152>
│ │  	asrs	r4, r1, #32
│ │  	b.n	2939dc <uniffi_pbcli_checksum_method_api_base@@Base+0x127158>
│ │ @@ -552625,66 +552625,66 @@
│ │  	movs	r0, r1
│ │  	b.n	294922 <uniffi_pbcli_checksum_method_api_base@@Base+0x12809e>
│ │  	beq.n	29461c <uniffi_pbcli_checksum_method_api_base@@Base+0x127d98>
│ │  	b.n	294a7c <uniffi_pbcli_checksum_method_api_base@@Base+0x1281f8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r2, r3, r5, r9, sl}
│ │  	vshr.u32	<illegal reg q15.5>, <illegal reg q2.5>, #32
│ │ -			@ <UNDEFINED> instruction: 0xffde2baa
│ │ -			@ <UNDEFINED> instruction: 0xffe00dbb
│ │ +			@ <UNDEFINED> instruction: 0xffde2bd1
│ │ +	vqrdmulh.s32	q8, q8, d2[1]
│ │  	vmlsl.u32	q15, d17, d26
│ │  	vsri.64	d31, d0, #34
│ │  	movs	r4, r4
│ │  	lsrs	r0, r6, #28
│ │  	movs	r0, r0
│ │  	orrs.w	r0, r8, #10747904	@ 0xa40000
│ │  			@ <UNDEFINED> instruction: 0xf3f40024
│ │  	lsrs	r0, r7, #26
│ │  	movs	r0, r0
│ │  			@ <UNDEFINED> instruction: 0xf3e40024
│ │  			@ <UNDEFINED> instruction: 0xf3200024
│ │  			@ <UNDEFINED> instruction: 0xf3180024
│ │  			@ <UNDEFINED> instruction: 0xf28c0024
│ │  			@ <UNDEFINED> instruction: 0xf2880024
│ │ -	cmp	r6, #202	@ 0xca
│ │ +	cmp	r6, #241	@ 0xf1
│ │  	vrshr.u64	d31, d24, #32
│ │  	movs	r4, r4
│ │  	subw	r0, ip, #36	@ 0x24
│ │  	lsrs	r0, r2, #21
│ │  	movs	r0, r0
│ │ -	ldmia	r5, {r2, r5}
│ │ +	ldmia	r5!, {r0, r1, r3, r6}
│ │  	vqshlu.s64	<illegal reg q14.5>, q4, #32
│ │  	vmlsl.u16	<illegal reg q14.5>, d30, d1[1]
│ │ -	vmull.p<illegal width 16>	q9, d14, d26
│ │ -	vmla.i32	<illegal reg q8.5>, q0, d13[0]
│ │ +			@ <UNDEFINED> instruction: 0xffde2e51
│ │ +	vshr.u32	<illegal reg q8.5>, q10, #32
│ │  	vsli.32	d29, d20, #1
│ │  			@ <UNDEFINED> instruction: 0xffde0c50
│ │  	movs	r0, r0
│ │ -	cmp	r5, #218	@ 0xda
│ │ -	vrshr.u64	q10, q1, #32
│ │ +	cmp	r6, #1
│ │ +	vrshr.u64	q10, <illegal reg q12.5>, #32
│ │  	vqrdmlah.s32	<illegal reg q13.5>, q8, d5[1]
│ │  	vmla.f16	<illegal reg q15.5>, q7, d4[2]
│ │  	movs	r4, r4
│ │  	lsrs	r0, r5, #16
│ │  	movs	r0, r0
│ │  	adcs.w	r0, r4, #36	@ 0x24
│ │  	orns	r0, r8, #36	@ 0x24
│ │  	eor.w	r0, r4, #36	@ 0x24
│ │  	vaddl.s16	q8, d0, d20
│ │  	vext.8	d0, d12, d20, #0
│ │ -	cmp	r3, #242	@ 0xf2
│ │ -	vqshl.u32	<illegal reg q10.5>, q7, #0
│ │ +	cmp	r4, #25
│ │ +	vabdl.u32	<illegal reg q10.5>, d16, d5
│ │  	vsra.u32	d31, d16, #32
│ │  	movs	r4, r4
│ │ -	cmp	r5, #98	@ 0x62
│ │ +	cmp	r5, #137	@ 0x89
│ │  			@ <UNDEFINED> instruction: 0xffe00b78
│ │  	movs	r0, r0
│ │ -	cmp	r5, #10
│ │ -	vsubl.u32	q10, d0, d2
│ │ -	vmlal.u32	<illegal reg q8.5>, d16, d4
│ │ +	cmp	r5, #49	@ 0x31
│ │ +	vsubl.u32	q10, d0, d25
│ │ +	vmlal.u32	<illegal reg q8.5>, d16, d27
│ │  	vaddl.u32	<illegal reg q15.5>, d0, d28
│ │  	movs	r4, r4
│ │  	and.w	r0, r8, #36	@ 0x24
│ │  	vext.8	d16, d12, d20, #0
│ │  	vaddl.s32	q8, d8, d20
│ │  	lsrs	r4, r1, #10
│ │  	movs	r0, r0
│ │ @@ -552838,15 +552838,15 @@
│ │  	add.w	r0, r1, r0
│ │  	and.w	fp, r0, r7
│ │  	add.w	r0, r1, r4
│ │  	b.n	294b42 <uniffi_pbcli_checksum_method_api_base@@Base+0x1282be>
│ │  	beq.n	29483c <uniffi_pbcli_checksum_method_api_base@@Base+0x127fb8>
│ │  	b.n	294c9c <uniffi_pbcli_checksum_method_api_base@@Base+0x128418>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r5, r6, r8, fp, sp}
│ │ +	ldmia.w	sp!, {r0, r2, r5, r7, r8, fp, sp}
│ │  	vcvt.f16.u16	q10, q8, #32
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	294d30 <uniffi_pbcli_checksum_method_api_base@@Base+0x1284ac>
│ │  	beq.n	294828 <uniffi_pbcli_checksum_method_api_base@@Base+0x127fa4>
│ │  	b.n	294cb4 <uniffi_pbcli_checksum_method_api_base@@Base+0x128430>
│ │  	lsls	r4, r6, #2
│ │  	b.n	29435c <uniffi_pbcli_checksum_method_api_base@@Base+0x127ad8>
│ │ @@ -552928,21 +552928,21 @@
│ │  	b.n	29500a <uniffi_pbcli_checksum_method_api_base@@Base+0x128786>
│ │  	movs	r5, r0
│ │  	b.n	294c0e <uniffi_pbcli_checksum_method_api_base@@Base+0x12838a>
│ │  	beq.n	2948f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x12806c>
│ │  	b.n	294d68 <uniffi_pbcli_checksum_method_api_base@@Base+0x1284e4>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r2, r3, r4, r5, r9, fp, ip, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffde290e
│ │ -			@ <UNDEFINED> instruction: 0xffe0abf2
│ │ -	vmlal.u32	q9, d16, d6
│ │ -			@ <UNDEFINED> instruction: 0xffe028de
│ │ +	vqshrn.u32	d18, <illegal reg q10.5>, #2
│ │ +	vcvt.f16.u16	d26, d9, #32
│ │ +	vmlal.u32	q9, d16, d29
│ │ +			@ <UNDEFINED> instruction: 0xffe02905
│ │  			@ <UNDEFINED> instruction: 0xffe03d2d
│ │  	vqrdmlah.s16	q11, q15, d6[0]
│ │ -	vmls.f16	q14, q15, d0[0]
│ │ +	vmls.f16	q14, q15, d7[2]
│ │  			@ <UNDEFINED> instruction: 0xffe04ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	294e18 <uniffi_pbcli_checksum_method_api_base@@Base+0x128594>
│ │  	beq.n	294908 <uniffi_pbcli_checksum_method_api_base@@Base+0x128084>
│ │  	b.n	294d9c <uniffi_pbcli_checksum_method_api_base@@Base+0x128518>
│ │  	add	r0, pc, #0	@ (adr r0, 294904 <uniffi_pbcli_checksum_method_api_base@@Base+0x128080>)
│ │  	b.n	294c46 <uniffi_pbcli_checksum_method_api_base@@Base+0x1283c2>
│ │ @@ -553233,15 +553233,15 @@
│ │  	lsls	r0, r0, #21
│ │  	movs	r0, r0
│ │  	orn	r0, r8, r4, asr #32
│ │  	orr.w	r0, r8, r4, asr #32
│ │  	orr.w	r0, ip, r4, asr #32
│ │  	ands.w	r0, r4, r4, asr #32
│ │  	and.w	r0, r8, r4, asr #32
│ │ -	movs	r6, #70	@ 0x46
│ │ +	movs	r6, #109	@ 0x6d
│ │  	vqshrun.s64	d20, q8, #32
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2950e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x12885c>
│ │  	ands	r0, r0
│ │  	b.n	294f0a <uniffi_pbcli_checksum_method_api_base@@Base+0x128686>
│ │  	movs	r0, r0
│ │  	b.n	2946ee <uniffi_pbcli_checksum_method_api_base@@Base+0x127e6a>
│ │ @@ -553261,15 +553261,15 @@
│ │  	b.n	294f2e <uniffi_pbcli_checksum_method_api_base@@Base+0x1286aa>
│ │  	asrs	r5, r0, #32
│ │  	b.n	294f32 <uniffi_pbcli_checksum_method_api_base@@Base+0x1286ae>
│ │  	cmp	r7, #142	@ 0x8e
│ │  	b.n	295336 <uniffi_pbcli_checksum_method_api_base@@Base+0x128ab2>
│ │  	ldr	r0, [pc, #192]	@ (294cb8 <uniffi_pbcli_checksum_method_api_base@@Base+0x128434>)
│ │  	ldmia.w	sp!, {r0, r1, r4, r5, r7, sp}
│ │ -	and.w	r5, r2, r6, asr #9
│ │ +	and.w	r5, r2, sp, lsl #10
│ │  	vmlal.u32	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	294f4a <uniffi_pbcli_checksum_method_api_base@@Base+0x1286c6>
│ │  	adds	r0, #2
│ │  	b.n	294f4e <uniffi_pbcli_checksum_method_api_base@@Base+0x1286ca>
│ │  	movs	r0, #1
│ │  	b.n	294f52 <uniffi_pbcli_checksum_method_api_base@@Base+0x1286ce>
│ │ @@ -553455,27 +553455,27 @@
│ │  	ldmia.w	sp!, {r2, r4, r5, r7, fp, sp, lr, pc}
│ │  	movs	r4, r4
│ │  	lsls	r4, r6, #13
│ │  	movs	r0, r0
│ │  	ldmia.w	r8, {r2, r5}
│ │  	ldrd	r0, r0, [r4], #-144	@ 0x90
│ │  	strd	r0, r0, [ip], #-144	@ 0x90
│ │ -	movs	r4, #126	@ 0x7e
│ │ -	vsri.32	q9, q7, #32
│ │ +	movs	r4, #165	@ 0xa5
│ │ +	vraddhn.i64	d18, q8, <illegal reg q2.5>
│ │  			@ <UNDEFINED> instruction: 0xffe0e7cc
│ │  	movs	r4, r4
│ │  	b.n	294d44 <uniffi_pbcli_checksum_method_api_base@@Base+0x1284c0>
│ │  	movs	r4, r4
│ │  	b.n	294d30 <uniffi_pbcli_checksum_method_api_base@@Base+0x1284ac>
│ │  	movs	r4, r4
│ │  	b.n	294cfc <uniffi_pbcli_checksum_method_api_base@@Base+0x128478>
│ │  	movs	r4, r4
│ │  	b.n	294ce0 <uniffi_pbcli_checksum_method_api_base@@Base+0x12845c>
│ │  	movs	r4, r4
│ │ -	movs	r3, #202	@ 0xca
│ │ +	movs	r3, #241	@ 0xf1
│ │  	vcvt.f16.u16	d20, d0, #32
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	295300 <uniffi_pbcli_checksum_method_api_base@@Base+0x128a7c>
│ │  	movs	r1, r0
│ │  	b.n	29552a <uniffi_pbcli_checksum_method_api_base@@Base+0x128ca6>
│ │  	mcr2	11, 6, lr, cr1, cr15, {7}	@ <UNPREDICTABLE>
│ │  	lsls	r0, r1, #1
│ │ @@ -553665,15 +553665,15 @@
│ │  	b.n	2956ca <uniffi_pbcli_checksum_method_api_base@@Base+0x128e46>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	2956ce <uniffi_pbcli_checksum_method_api_base@@Base+0x128e4a>
│ │  	lsrs	r1, r7, #32
│ │  	add.w	r0, r1, r7
│ │  	b.n	2952d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x128a52>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r1, r4, r6, r7, r8, sp}
│ │ +	ldmia.w	sp!, {r0, r3, r4, r5, r6, r7, r8, sp}
│ │  			@ <UNDEFINED> instruction: 0xffe067e4
│ │  	vmlal.u16	q10, d14, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2952ea <uniffi_pbcli_checksum_method_api_base@@Base+0x128a66>
│ │  	movs	r6, r4
│ │  			@ <UNDEFINED> instruction: 0xeb00f3fb
│ │  	add.w	r0, r0, ip
│ │ @@ -553735,16 +553735,16 @@
│ │  	movs	r0, r0
│ │  	b.n	295150 <uniffi_pbcli_checksum_method_api_base@@Base+0x1288cc>
│ │  	ands	r0, r0
│ │  	b.n	294b36 <uniffi_pbcli_checksum_method_api_base@@Base+0x1282b2>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r8, sl, sp, lr, pc}
│ │  	movs	r4, r4
│ │ -	movs	r1, #62	@ 0x3e
│ │ -			@ <UNDEFINED> instruction: 0xffe00cf9
│ │ +	movs	r1, #101	@ 0x65
│ │ +			@ <UNDEFINED> instruction: 0xffe00d20
│ │  	vsri.64	q15, q0, #32
│ │  	movs	r4, r4
│ │  	ldr	r0, [pc, #0]	@ (29504c <uniffi_pbcli_checksum_method_api_base@@Base+0x1287c8>)
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	295392 <uniffi_pbcli_checksum_method_api_base@@Base+0x128b0e>
│ │  	movs	r6, r0
│ │  	add.w	r0, r0, r7, lsr #2
│ │ @@ -554019,15 +554019,15 @@
│ │  	movs	r0, r0
│ │  	b.n	2953e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x128b64>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2953ec <uniffi_pbcli_checksum_method_api_base@@Base+0x128b68>
│ │  	movs	r0, #2
│ │  	b.n	2953f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x128b6c>
│ │  	mcr2	10, 2, lr, cr10, cr15, {7}	@ <UNPREDICTABLE>
│ │ -	adds	r3, #133	@ 0x85
│ │ +	adds	r3, #172	@ 0xac
│ │  	vshr.u32	d16, d0, #32
│ │  	movs	r0, r0
│ │  	lsls	r0, r2, #16
│ │  	movs	r0, r0
│ │  	ldr	r7, [pc, #960]	@ (2956a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x128e20>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	295804 <uniffi_pbcli_checksum_method_api_base@@Base+0x128f80>
│ │ @@ -554446,35 +554446,35 @@
│ │  	b.n	295d06 <uniffi_pbcli_checksum_method_api_base@@Base+0x129482>
│ │  	movs	r0, #0
│ │  	b.n	295dca <uniffi_pbcli_checksum_method_api_base@@Base+0x129546>
│ │  	lsls	r2, r7, #25
│ │  			@ <UNDEFINED> instruction: 0xeb01ffce
│ │  			@ <UNDEFINED> instruction: 0xeaff8074
│ │  	movs	r4, r4
│ │ -	strb	r6, [r7, #21]
│ │ +	strb	r5, [r4, #22]
│ │  			@ <UNDEFINED> instruction: 0xffe0ab8e
│ │  			@ <UNDEFINED> instruction: 0xffdfad07
│ │  			@ <UNDEFINED> instruction: 0xffdf4b18
│ │  	vaddw.u16	<illegal reg q9.5>, q15, d8
│ │ -	vsli.16	<illegal reg q11.5>, q1, #14
│ │ -	vqshl.u32	q15, q10, #0
│ │ +	vsli.16	<illegal reg q11.5>, <illegal reg q12.5>, #14
│ │ +	vqshl.u64	d30, d11, #32
│ │  	vaddw.u32	q9, q8, d30
│ │  			@ <UNDEFINED> instruction: 0xffdf8ff5
│ │ -			@ <UNDEFINED> instruction: 0xffdeff11
│ │ +			@ <UNDEFINED> instruction: 0xffdeff38
│ │  			@ <UNDEFINED> instruction: 0xffe07e94
│ │  	movs	r4, r4
│ │ -	strb	r2, [r7, #17]
│ │ -	vqshlu.s64	d30, d12, #32
│ │ +	strb	r1, [r4, #18]
│ │ +	vmlsl.u32	q15, d16, d3[0]
│ │  	vqrdmulh.s32	<illegal reg q11.5>, q8, d8[0]
│ │  	movs	r4, r4
│ │ -	strb	r2, [r7, #19]
│ │ +	strb	r1, [r4, #20]
│ │  			@ <UNDEFINED> instruction: 0xffe0ab0a
│ │ -	vsri.64	d23, d30, #33
│ │ -	vmlsl.u32	q15, d16, d0[1]
│ │ -	vsri.64	d23, d26, #32
│ │ +	vmls.i16	<illegal reg q11.5>, <illegal reg q15.5>, d5[2]
│ │ +	vabdl.u32	q15, d0, d7
│ │ +	vmls.i32	<illegal reg q11.5>, q8, d1[1]
│ │  	vrsra.u64	q14, <illegal reg q15.5>, #32
│ │  	vsli.64	d16, d19, #30
│ │  	and.w	r8, r0, r0, ror #16
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	295c0c <uniffi_pbcli_checksum_method_api_base@@Base+0x129388>
│ │  	beq.n	295704 <uniffi_pbcli_checksum_method_api_base@@Base+0x128e80>
│ │  	b.n	295b90 <uniffi_pbcli_checksum_method_api_base@@Base+0x12930c>
│ │ @@ -555558,15 +555558,15 @@
│ │  	lsrs	r4, r7, #9
│ │  	movs	r0, r0
│ │  	cmp	r1, #241	@ 0xf1
│ │  	vqshl.u16	<illegal reg q11.5>, q4, #14
│ │  	movs	r4, r4
│ │  	cmp	r4, #225	@ 0xe1
│ │  	vqshl.u16	q8, <illegal reg q2.5>, #14
│ │ -			@ <UNDEFINED> instruction: 0xffdf9c92
│ │ +			@ <UNDEFINED> instruction: 0xffdf9cb9
│ │  	vqrshrn.u64	d18, <illegal reg q10.5>, #32
│ │  			@ <UNDEFINED> instruction: 0xffde03e9
│ │  	vmlal.u16	q9, d31, d21
│ │  	vrsra.u16	d16, d9, #2
│ │  			@ <UNDEFINED> instruction: 0xffdf2b8d
│ │  	vrsubhn.i32	d16, q7, <illegal reg q0.5>
│ │  	vqshlu.s64	d26, d23, #31
│ │ @@ -556312,17 +556312,17 @@
│ │  	vsra.u64	q9, <illegal reg q6.5>, #33
│ │  	vrshr.u64	d27, d19, #34
│ │  	vshr.u64	d18, d29, #33
│ │  			@ <UNDEFINED> instruction: 0xffde59de
│ │  			@ <UNDEFINED> instruction: 0xffdf1fa5
│ │  	vshr.u16	<illegal reg q13.5>, <illegal reg q13.5>, #2
│ │  			@ <UNDEFINED> instruction: 0xffdfb348
│ │ -			@ <UNDEFINED> instruction: 0xffdef7c2
│ │ +			@ <UNDEFINED> instruction: 0xffdef7e9
│ │  	vshr.u16	d30, d20, #1
│ │ -	vqrdmulh.s16	q15, <illegal reg q15.5>, d0[3]
│ │ +	vmull.p<illegal width 16>	q15, d15, d15
│ │  	vaddl.u32	q9, d0, d13
│ │  	vmla.i16	<illegal reg q13.5>, q15, d3[2]
│ │  			@ <UNDEFINED> instruction: 0xffdf4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	296c4c <uniffi_pbcli_checksum_method_api_base@@Base+0x12a3c8>
│ │  	beq.n	296744 <uniffi_pbcli_checksum_method_api_base@@Base+0x129ec0>
│ │  	b.n	296bd0 <uniffi_pbcli_checksum_method_api_base@@Base+0x12a34c>
│ │ @@ -556493,18 +556493,18 @@
│ │  	asrs	r2, r7, #2
│ │  	b.n	296fde <uniffi_pbcli_checksum_method_api_base@@Base+0x12a75a>
│ │  	movs	r0, #2
│ │  	b.n	2969c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x12a13c>
│ │  	lsls	r4, r6, #7
│ │  			@ <UNDEFINED> instruction: 0xeb01ffcc
│ │  			@ <UNDEFINED> instruction: 0xeaff1e09
│ │ -	vmls.f16	<illegal reg q14.5>, q7, d4[2]
│ │ +	vabal.u16	<illegal reg q14.5>, d30, d11
│ │  	vqrdmulh.s32	<illegal reg q8.5>, q0, d5[0]
│ │ -	vraddhn.i32	d29, q15, q8
│ │ -	vcvt.f16.u16	<illegal reg q13.5>, <illegal reg q4.5>, #32
│ │ +	vmls.i16	<illegal reg q14.5>, q15, d7[0]
│ │ +	vmull.u32	<illegal reg q13.5>, d16, d0
│ │  	vqshrun.s64	d20, q8, #32
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	296de0 <uniffi_pbcli_checksum_method_api_base@@Base+0x12a55c>
│ │  	stmia	r0!, {r2, r3}
│ │  	b.n	296400 <uniffi_pbcli_checksum_method_api_base@@Base+0x129b7c>
│ │  	ands	r0, r0
│ │  	b.n	2963ee <uniffi_pbcli_checksum_method_api_base@@Base+0x129b6a>
│ │ @@ -557070,15 +557070,15 @@
│ │  	vaddw.u32	q8, <illegal reg q8.5>, d16
│ │  	movs	r0, r0
│ │  	str	r6, [r3, #80]	@ 0x50
│ │  	vqrshrun.s32	d28, q2, #2
│ │  	movs	r4, r4
│ │  	str	r2, [r0, #76]	@ 0x4c
│ │  	vraddhn.i32	d22, q15, q13
│ │ -	vsli.16	q10, <illegal reg q6.5>, #14
│ │ +	vabal.u16	q10, d30, d4
│ │  	vaddl.u32	q8, d0, d20
│ │  	b.n	2968fc <uniffi_pbcli_checksum_method_api_base@@Base+0x12a078>
│ │  	movs	r0, r0
│ │  	b.n	296d00 <uniffi_pbcli_checksum_method_api_base@@Base+0x12a47c>
│ │  	movs	r0, r0
│ │  	b.n	297466 <uniffi_pbcli_checksum_method_api_base@@Base+0x12abe2>
│ │  	vrhadd.u16	d0, d14, d31
│ │ @@ -557538,28 +557538,28 @@
│ │  	ldmia.w	sp!, {r0}
│ │  	b.n	2978f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x12b072>
│ │  	beq.n	2971f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x12a96c>
│ │  	b.n	297650 <uniffi_pbcli_checksum_method_api_base@@Base+0x12adcc>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r3, r6, r8, sl, sp, pc}
│ │  	vqrdmulh.s16	q9, <illegal reg q15.5>, d4[1]
│ │ -	vsubl.u16	q15, d14, d7
│ │ +	vsubl.u16	q15, d14, d30
│ │  			@ <UNDEFINED> instruction: 0xffe0a744
│ │  	vabal.u16	q14, d31, d0
│ │  	movs	r4, r4
│ │  	stmia	r5!, {r4, r5, r6}
│ │  	movs	r4, r4
│ │  	add	r6, pc, #832	@ (adr r6, 297518 <uniffi_pbcli_checksum_method_api_base@@Base+0x12ac94>)
│ │  	vsri.16	d28, d28, #1
│ │  	movs	r4, r4
│ │  	stmia	r4!, {r2, r5}
│ │  	movs	r4, r4
│ │  	add	r5, pc, #576	@ (adr r5, 297424 <uniffi_pbcli_checksum_method_api_base@@Base+0x12aba0>)
│ │  			@ <UNDEFINED> instruction: 0xffdf2e14
│ │ -			@ <UNDEFINED> instruction: 0xffde59b2
│ │ +			@ <UNDEFINED> instruction: 0xffde59d9
│ │  			@ <UNDEFINED> instruction: 0xffe04df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	297710 <uniffi_pbcli_checksum_method_api_base@@Base+0x12ae8c>
│ │  	lsrs	r4, r6
│ │  	b.n	296d38 <uniffi_pbcli_checksum_method_api_base@@Base+0x12a4b4>
│ │  	ands	r4, r0
│ │  	b.n	29713c <uniffi_pbcli_checksum_method_api_base@@Base+0x12a8b8>
│ │ @@ -558458,15 +558458,15 @@
│ │  	movs	r0, #48	@ 0x30
│ │  	b.n	297504 <uniffi_pbcli_checksum_method_api_base@@Base+0x12ac80>
│ │  	bl	fff75dea <uniffi_pbcli_checksum_method_api_base@@Base+0xffe09566>
│ │  	movs	r4, r0
│ │  	b.n	297d22 <uniffi_pbcli_checksum_method_api_base@@Base+0x12b49e>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r2, r4, r5, r7, sl, fp}
│ │ -			@ <UNDEFINED> instruction: 0xffde0d36
│ │ +			@ <UNDEFINED> instruction: 0xffde0d5d
│ │  	vmull.u32	q8, d16, d12
│ │  	vqdmulh.s16	q8, q7, d4[1]
│ │  			@ <UNDEFINED> instruction: 0xffde48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	297f18 <uniffi_pbcli_checksum_method_api_base@@Base+0x12b694>
│ │  	beq.n	297a10 <uniffi_pbcli_checksum_method_api_base@@Base+0x12b18c>
│ │  	b.n	297e9c <uniffi_pbcli_checksum_method_api_base@@Base+0x12b618>
│ │ @@ -558677,15 +558677,15 @@
│ │  	beq.n	297be0 <uniffi_pbcli_checksum_method_api_base@@Base+0x12b35c>
│ │  	b.n	298058 <uniffi_pbcli_checksum_method_api_base@@Base+0x12b7d4>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {sp, lr}
│ │  	b.n	29830a <uniffi_pbcli_checksum_method_api_base@@Base+0x12ba86>
│ │  			@ <UNDEFINED> instruction: 0xffa5eaff
│ │  	lsrs	r4, r2, #14
│ │ -			@ <UNDEFINED> instruction: 0xffdeaab1
│ │ +			@ <UNDEFINED> instruction: 0xffdeaad8
│ │  			@ <UNDEFINED> instruction: 0xffe00b20
│ │  			@ <UNDEFINED> instruction: 0xffde0b6c
│ │  			@ <UNDEFINED> instruction: 0xffde4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	298100 <uniffi_pbcli_checksum_method_api_base@@Base+0x12b87c>
│ │  	str	r1, [r0, #0]
│ │  	b.n	297f2a <uniffi_pbcli_checksum_method_api_base@@Base+0x12b6a6>
│ │ @@ -558891,21 +558891,21 @@
│ │  	add.w	r0, r0, r0
│ │  	b.n	2984ea <uniffi_pbcli_checksum_method_api_base@@Base+0x12bc66>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r2}
│ │  	b.n	2980f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x12b86e>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r2, r3, r6, r7, r8, fp}
│ │ -	vmull.u16	<illegal reg q11.5>, d30, d4[0]
│ │ +	vmull.u16	<illegal reg q11.5>, d30, d3[3]
│ │  	vmul.i32	q8, q8, d0[1]
│ │ -			@ <UNDEFINED> instruction: 0xffde79d8
│ │ +			@ <UNDEFINED> instruction: 0xffde79ff
│ │  	vmlal.u32	q8, d16, d12
│ │ -			@ <UNDEFINED> instruction: 0xffde7984
│ │ +			@ <UNDEFINED> instruction: 0xffde79ab
│ │  	vqrshrun.s64	d16, q8, #32
│ │ -	vmul.f16	<illegal reg q11.5>, q7, d0[3]
│ │ +			@ <UNDEFINED> instruction: 0xffde798f
│ │  			@ <UNDEFINED> instruction: 0xffe04ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2982f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x12ba74>
│ │  	beq.n	297de8 <uniffi_pbcli_checksum_method_api_base@@Base+0x12b564>
│ │  	b.n	29827c <uniffi_pbcli_checksum_method_api_base@@Base+0x12b9f8>
│ │  	add	r0, pc, #0	@ (adr r0, 297de4 <uniffi_pbcli_checksum_method_api_base@@Base+0x12b560>)
│ │  	b.n	298526 <uniffi_pbcli_checksum_method_api_base@@Base+0x12bca2>
│ │ @@ -559241,19 +559241,19 @@
│ │  	movs	r6, r0
│ │  	b.n	298406 <uniffi_pbcli_checksum_method_api_base@@Base+0x12bb82>
│ │  	beq.n	298100 <uniffi_pbcli_checksum_method_api_base@@Base+0x12b87c>
│ │  	b.n	298560 <uniffi_pbcli_checksum_method_api_base@@Base+0x12bcdc>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r3, r5, r7, r8, sl}
│ │  	vsli.16	q8, q14, #14
│ │ -	vsri.64	d26, d9, #34
│ │ +	vmls.i16	q13, q15, d0[0]
│ │  	vsli.32	d16, d28, #0
│ │  	vaddw.u16	<illegal reg q10.5>, q7, d25
│ │  	vqshlu.s16	d16, d4, #14
│ │ -	vsli.16	d26, d17, #14
│ │ +	vsli.16	q13, q4, #14
│ │  	vmls.f32	q8, q8, d12[0]
│ │  			@ <UNDEFINED> instruction: 0xffde48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	298610 <uniffi_pbcli_checksum_method_api_base@@Base+0x12bd8c>
│ │  	beq.n	298108 <uniffi_pbcli_checksum_method_api_base@@Base+0x12b884>
│ │  	b.n	298594 <uniffi_pbcli_checksum_method_api_base@@Base+0x12bd10>
│ │  	strb	r0, [r0, #0]
│ │ @@ -560091,17 +560091,17 @@
│ │  	b.n	29896c <uniffi_pbcli_checksum_method_api_base@@Base+0x12c0e8>
│ │  	asrs	r6, r3, #6
│ │  	add.w	r0, r2, r0, lsl #16
│ │  	b.n	298f96 <uniffi_pbcli_checksum_method_api_base@@Base+0x12c712>
│ │  	movs	r4, r0
│ │  	b.n	298b9a <uniffi_pbcli_checksum_method_api_base@@Base+0x12c316>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r6, r9, sl, pc}
│ │ -	vmlsl.u32	q12, d0, d5[0]
│ │ -	vqshlu.s32	d24, d13, #0
│ │ +	ldmia.w	sp!, {r2, r3, r4, r7, r9, sl, pc}
│ │ +	vmlsl.u32	q12, d0, d12[1]
│ │ +	vmlsl.u32	q12, d0, d4[0]
│ │  	vaddl.u32	q8, d0, d0
│ │  	b.n	298f0e <uniffi_pbcli_checksum_method_api_base@@Base+0x12c68a>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (298934 <uniffi_pbcli_checksum_method_api_base@@Base+0x12c0b0>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	298d94 <uniffi_pbcli_checksum_method_api_base@@Base+0x12c510>
│ │  	ands	r0, r0
│ │ @@ -560152,15 +560152,15 @@
│ │  	b.n	298c22 <uniffi_pbcli_checksum_method_api_base@@Base+0x12c39e>
│ │  	asrs	r5, r0, #32
│ │  	b.n	298c26 <uniffi_pbcli_checksum_method_api_base@@Base+0x12c3a2>
│ │  	movs	r0, #52	@ 0x34
│ │  	b.n	29902a <uniffi_pbcli_checksum_method_api_base@@Base+0x12c7a6>
│ │  	ldr	r0, [pc, #192]	@ (2989ac <uniffi_pbcli_checksum_method_api_base@@Base+0x12c128>)
│ │  	ldmia.w	sp!, {r1, r2, r4, r5, r6, r8, ip}
│ │ -			@ <UNDEFINED> instruction: 0xea0285d5
│ │ +			@ <UNDEFINED> instruction: 0xea0285fc
│ │  			@ <UNDEFINED> instruction: 0xffe04ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	298e18 <uniffi_pbcli_checksum_method_api_base@@Base+0x12c594>
│ │  	beq.n	298918 <uniffi_pbcli_checksum_method_api_base@@Base+0x12c094>
│ │  	b.n	298d9c <uniffi_pbcli_checksum_method_api_base@@Base+0x12c518>
│ │  	str	r0, [r0, r0]
│ │  	b.n	299046 <uniffi_pbcli_checksum_method_api_base@@Base+0x12c7c2>
│ │ @@ -560356,16 +560356,16 @@
│ │  	movs	r1, r0
│ │  	b.n	2991ee <uniffi_pbcli_checksum_method_api_base@@Base+0x12c96a>
│ │  	ands	r0, r4
│ │  	b.n	2985c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x12bd40>
│ │  	beq.n	298aec <uniffi_pbcli_checksum_method_api_base@@Base+0x12c268>
│ │  	b.n	298f4c <uniffi_pbcli_checksum_method_api_base@@Base+0x12c6c8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, sl, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffe083ed
│ │ +	ldmia.w	sp!, {r5, r6, sl, pc}
│ │ +	vsri.32	d24, d4, #32
│ │  			@ <UNDEFINED> instruction: 0xffe04bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	298fe4 <uniffi_pbcli_checksum_method_api_base@@Base+0x12c760>
│ │  	movs	r0, r0
│ │  	b.n	299170 <uniffi_pbcli_checksum_method_api_base@@Base+0x12c8ec>
│ │  	movs	r2, r4
│ │  	lsrs	r0, r0, #8
│ │ @@ -560655,17 +560655,17 @@
│ │  	asrs	r0, r4, #1
│ │  	add.w	r0, r2, r4
│ │  	b.n	29908e <uniffi_pbcli_checksum_method_api_base@@Base+0x12c80a>
│ │  	beq.n	298d80 <uniffi_pbcli_checksum_method_api_base@@Base+0x12c4fc>
│ │  	b.n	2991e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x12c964>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r0, r3, r5, r6, r7, r8, lr}
│ │ -	vmla.f16	q12, <illegal reg q15.5>, d1[3]
│ │ -	vsra.u32	q12, <illegal reg q14.5>, #32
│ │ -	vsra.u32	d24, d25, #32
│ │ +	vrshr.u16	d24, d0, #1
│ │ +	vaddw.u32	q12, q8, d20
│ │ +	vmla.f32	q12, q0, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffe048f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	299288 <uniffi_pbcli_checksum_method_api_base@@Base+0x12ca04>
│ │  	str	r0, [r0, r0]
│ │  	b.n	2990b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x12c82e>
│ │  	movs	r1, r0
│ │  	b.n	2990b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x12c832>
│ │ @@ -560944,25 +560944,25 @@
│ │  	movs	r0, r0
│ │  	and.w	r0, r0, r0, lsl #24
│ │  	b.n	29971e <uniffi_pbcli_checksum_method_api_base@@Base+0x12ce9a>
│ │  	movs	r7, r0
│ │  	b.n	299322 <uniffi_pbcli_checksum_method_api_base@@Base+0x12ca9e>
│ │  	lsls	r1, r0, #15
│ │  			@ <UNDEFINED> instruction: 0xeb01ff97
│ │ -			@ <UNDEFINED> instruction: 0xeaff0e9d
│ │ -	vrsra.u32	d30, d23, #32
│ │ -	vqrdmlah.s16	q8, <illegal reg q7.5>, d5[0]
│ │ -	vrshr.u64	q15, <illegal reg q7.5>, #32
│ │ -			@ <UNDEFINED> instruction: 0xffdf0df5
│ │ -	vsubl.u32	q15, d16, d15
│ │ -			@ <UNDEFINED> instruction: 0xffdf0db5
│ │ -	vmlal.u32	q15, d0, d15[0]
│ │ +			@ <UNDEFINED> instruction: 0xeaff0ec4
│ │ +	vrsra.u32	q15, q7, #32
│ │ +	vqrdmlah.s16	q8, <illegal reg q7.5>, d4[3]
│ │ +	vsubw.u32	q15, q0, d6
│ │ +			@ <UNDEFINED> instruction: 0xffdf0e1c
│ │ +	vrshr.u64	d30, d22, #32
│ │ +			@ <UNDEFINED> instruction: 0xffdf0ddc
│ │ +	vrshr.u32	q15, q11, #32
│ │  	vqrdmlah.s16	<illegal reg q9.5>, <illegal reg q15.5>, d1[1]
│ │ -			@ <UNDEFINED> instruction: 0xffdf0d11
│ │ -	vaddw.u32	q15, q8, d27
│ │ +			@ <UNDEFINED> instruction: 0xffdf0d38
│ │ +	vsra.u64	q15, q1, #32
│ │  			@ <UNDEFINED> instruction: 0xffdf4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	299538 <uniffi_pbcli_checksum_method_api_base@@Base+0x12ccb4>
│ │  	beq.n	299040 <uniffi_pbcli_checksum_method_api_base@@Base+0x12c7bc>
│ │  	b.n	2994bc <uniffi_pbcli_checksum_method_api_base@@Base+0x12cc38>
│ │  	str	r0, [r0, r0]
│ │  	b.n	299366 <uniffi_pbcli_checksum_method_api_base@@Base+0x12cae2>
│ │ @@ -561378,18 +561378,18 @@
│ │  	b.n	299ac6 <uniffi_pbcli_checksum_method_api_base@@Base+0x12d242>
│ │  	blx	1d4988 <uniffi_pbcli_checksum_method_api_base@@Base+0x68104>
│ │  	movs	r4, r0
│ │  	b.n	2996ce <uniffi_pbcli_checksum_method_api_base@@Base+0x12ce4a>
│ │  	beq.n	2993c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x12cb44>
│ │  	b.n	299828 <uniffi_pbcli_checksum_method_api_base@@Base+0x12cfa4>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r6, r7, fp, ip, sp}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r5, r6, r7, fp, ip, sp}
│ │  	vqshlu.s32	d27, d25, #0
│ │  			@ <UNDEFINED> instruction: 0xffde57c4
│ │ -			@ <UNDEFINED> instruction: 0xffde0a54
│ │ +			@ <UNDEFINED> instruction: 0xffde0a7b
│ │  	vcvt.f32.u32	q11, <illegal reg q13.5>, #32
│ │  	vrsra.u16	d31, d15, #1
│ │  	vsri.16	q15, q2, #3
│ │  	vrshr.u64	d31, d3, #34
│ │  	vmls.f16	<illegal reg q10.5>, <illegal reg q6.5>, d7[2]
│ │  			@ <UNDEFINED> instruction: 0xffdf4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │ @@ -562003,23 +562003,23 @@
│ │  	adds	r0, #217	@ 0xd9
│ │  	b.n	29a06a <uniffi_pbcli_checksum_method_api_base@@Base+0x12d7e6>
│ │  	movs	r0, #2
│ │  	b.n	299a4c <uniffi_pbcli_checksum_method_api_base@@Base+0x12d1c8>
│ │  	lsrs	r2, r0, #24
│ │  			@ <UNDEFINED> instruction: 0xeb02fff3
│ │  			@ <UNDEFINED> instruction: 0xeaffee0b
│ │ -	vrsubhn.i32	d23, <illegal reg q14.5>, q4
│ │ +	vrsubhn.i32	d23, <illegal reg q14.5>, <illegal reg q15.5>
│ │  			@ <UNDEFINED> instruction: 0xffe03b68
│ │  	movs	r4, r4
│ │  	ldcl	15, cr15, [fp, #-884]	@ 0xfffffc8c
│ │ -	strb	r0, [r3, #23]
│ │ +	strb	r7, [r7, #23]
│ │  			@ <UNDEFINED> instruction: 0xffe0ed2f
│ │ -	vabal.u16	<illegal reg q11.5>, d29, d28
│ │ +	vsli.64	<illegal reg q11.5>, <illegal reg q1.5>, #29
│ │  	vcvt.u16.f16	d30, d3, #32
│ │ -	vsli.64	d23, d0, #29
│ │ +	vsli.64	d23, d23, #29
│ │  			@ <UNDEFINED> instruction: 0xffe0ecd3
│ │  	vshr.u16	d17, d4, #3
│ │  	b.n	299484 <uniffi_pbcli_checksum_method_api_base@@Base+0x12cc00>
│ │  	adds	r0, #2
│ │  	b.n	29a0a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x12d822>
│ │  	mcr2	10, 0, lr, cr13, cr15, {7}	@ <UNPREDICTABLE>
│ │  	movs	r4, r2
│ │ @@ -562293,15 +562293,15 @@
│ │  	movs	r0, #0
│ │  	b.n	29a30a <uniffi_pbcli_checksum_method_api_base@@Base+0x12da86>
│ │  	blx	fffc41cc <uniffi_pbcli_checksum_method_api_base@@Base+0xffe57948>
│ │  	movs	r0, r0
│ │  	b.n	29a312 <uniffi_pbcli_checksum_method_api_base@@Base+0x12da8e>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r1, r3, r6, r9, fp, sp, lr, pc}
│ │ -	vqrshrn.u32	d24, <illegal reg q0.5>, #3
│ │ +	vqrshrn.u32	d24, q12, #3
│ │  	vshr.u32	d16, d4, #32
│ │  	b.n	299702 <uniffi_pbcli_checksum_method_api_base@@Base+0x12ce7e>
│ │  	lsls	r0, r2, #26
│ │  	and.w	r0, r0, r4, lsr #32
│ │  	b.n	29970a <uniffi_pbcli_checksum_method_api_base@@Base+0x12ce86>
│ │  	lsls	r0, r6, #1
│ │  	b.n	29970e <uniffi_pbcli_checksum_method_api_base@@Base+0x12ce8a>
│ │ @@ -562499,19 +562499,19 @@
│ │  	b.n	29a0d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x12d852>
│ │  	movs	r6, #125	@ 0x7d
│ │  	add.w	r0, r2, r7
│ │  	b.n	29a0de <uniffi_pbcli_checksum_method_api_base@@Base+0x12d85a>
│ │  	subs	r4, r4, r1
│ │  			@ <UNDEFINED> instruction: 0xeb02ffad
│ │  			@ <UNDEFINED> instruction: 0xeaffa674
│ │ -	vsubl.u16	q10, d15, d24
│ │ +	vmlal.u16	q10, d15, d7[1]
│ │  	vrshr.u64	d31, d1, #32
│ │ -			@ <UNDEFINED> instruction: 0xffde59f5
│ │ -	vcvt.f32.u32	<illegal reg q13.5>, q9, #32
│ │ -			@ <UNDEFINED> instruction: 0xffdf87ca
│ │ +	vshll.u16	<illegal reg q10.5>, d12, #14
│ │ +			@ <UNDEFINED> instruction: 0xffe0be99
│ │ +	vqshl.u64	q12, <illegal reg q8.5>, #31
│ │  	vshr.u32	d18, d12, #32
│ │  	b.n	29a502 <uniffi_pbcli_checksum_method_api_base@@Base+0x12dc7e>
│ │  	movs	r4, r3
│ │  	and.w	ip, r0, r0, ror #17
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	29a2e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x12da64>
│ │  	str	r0, [r0, r0]
│ │ @@ -562662,15 +562662,15 @@
│ │  	str	r0, [r0, #0]
│ │  	b.n	29a65e <uniffi_pbcli_checksum_method_api_base@@Base+0x12ddda>
│ │  	blx	ffeef520 <uniffi_pbcli_checksum_method_api_base@@Base+0xffd82c9c>
│ │  	movs	r6, r0
│ │  	b.n	29a266 <uniffi_pbcli_checksum_method_api_base@@Base+0x12d9e2>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r9, sl, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffdd6f8b
│ │ +			@ <UNDEFINED> instruction: 0xffdd6fb2
│ │  			@ <UNDEFINED> instruction: 0xffe04ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	29a454 <uniffi_pbcli_checksum_method_api_base@@Base+0x12dbd0>
│ │  	beq.n	299f44 <uniffi_pbcli_checksum_method_api_base@@Base+0x12d6c0>
│ │  	b.n	29a3d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x12db54>
│ │  	ands	r0, r0
│ │  	b.n	29a282 <uniffi_pbcli_checksum_method_api_base@@Base+0x12d9fe>
│ │ @@ -562783,19 +562783,19 @@
│ │  	b.n	29a4b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x12dc34>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {}
│ │  	b.n	29a76a <uniffi_pbcli_checksum_method_api_base@@Base+0x12dee6>
│ │  	beq.n	29a064 <uniffi_pbcli_checksum_method_api_base@@Base+0x12d7e0>
│ │  	b.n	29a4c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x12dc40>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r2, r3, r6, r8, sl, ip, lr}
│ │ -	vmls.f32	q15, q8, d6[1]
│ │ -			@ <UNDEFINED> instruction: 0xffdf9c98
│ │ -	vqshl.u32	d21, d10, #0
│ │ -	vsli.32	q15, q9, #0
│ │ +	ldmia.w	sp!, {r0, r2, r4, r5, r6, r8, sl, ip, lr}
│ │ +	vrsubhn.i64	d30, q0, <illegal reg q6.5>
│ │ +			@ <UNDEFINED> instruction: 0xffdf9cbf
│ │ +			@ <UNDEFINED> instruction: 0xffe05741
│ │ +	vsli.64	d30, d9, #32
│ │  			@ <UNDEFINED> instruction: 0xffdf4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	29a568 <uniffi_pbcli_checksum_method_api_base@@Base+0x12dce4>
│ │  	beq.n	29a078 <uniffi_pbcli_checksum_method_api_base@@Base+0x12d7f4>
│ │  	b.n	29a4ec <uniffi_pbcli_checksum_method_api_base@@Base+0x12dc68>
│ │  	movs	r0, r0
│ │  	b.n	29a6fa <uniffi_pbcli_checksum_method_api_base@@Base+0x12de76>
│ │ @@ -563009,20 +563009,20 @@
│ │  	adds	r0, #91	@ 0x5b
│ │  	b.n	29a95e <uniffi_pbcli_checksum_method_api_base@@Base+0x12e0da>
│ │  	movs	r0, #2
│ │  	b.n	29a340 <uniffi_pbcli_checksum_method_api_base@@Base+0x12dabc>
│ │  	lsrs	r5, r0, #15
│ │  			@ <UNDEFINED> instruction: 0xeb02ffc0
│ │  			@ <UNDEFINED> instruction: 0xeaff8f87
│ │ -	vraddhn.i32	d21, q7, q9
│ │ +	vmls.i16	<illegal reg q10.5>, q7, d1[1]
│ │  			@ <UNDEFINED> instruction: 0xffe0fe94
│ │ -	vmls.f16	<illegal reg q10.5>, <illegal reg q14.5>, d1[2]
│ │ +	vrsubhn.i32	d21, <illegal reg q6.5>, q4
│ │  	vmull.p64	<illegal reg q15.5>, d0, d10
│ │  	vqrdmlah.s16	<illegal reg q13.5>, <illegal reg q14.5>, d7[0]
│ │ -	vqrdmlsh.s16	q14, q15, d2[3]
│ │ +	vshr.u16	d29, d1, #2
│ │  			@ <UNDEFINED> instruction: 0xffdffd3a
│ │  			@ <UNDEFINED> instruction: 0xffdd4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	29a76c <uniffi_pbcli_checksum_method_api_base@@Base+0x12dee8>
│ │  	beq.n	29a28c <uniffi_pbcli_checksum_method_api_base@@Base+0x12da08>
│ │  	b.n	29a6f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x12de6c>
│ │  	str	r2, [r0, r0]
│ │ @@ -563428,15 +563428,15 @@
│ │  	ands	r0, r0
│ │  	b.n	29ad1e <uniffi_pbcli_checksum_method_api_base@@Base+0x12e49a>
│ │  	blx	53fbe0 <uniffi_pbcli_checksum_method_api_base@@Base+0x3d335c>
│ │  	movs	r4, r0
│ │  	b.n	29a926 <uniffi_pbcli_checksum_method_api_base@@Base+0x12e0a2>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r2, r4, r6, sp, lr, pc}
│ │ -	vmls.f16	q9, <illegal reg q6.5>, d2[2]
│ │ +	vabal.u16	q9, d29, d9
│ │  	vaddl.u32	<illegal reg q9.5>, d0, d4
│ │  	b.n	29a134 <uniffi_pbcli_checksum_method_api_base@@Base+0x12d8b0>
│ │  	adds	r0, #3
│ │  	b.n	29a718 <uniffi_pbcli_checksum_method_api_base@@Base+0x12de94>
│ │  	ldr	r1, [r4, #40]	@ 0x28
│ │  			@ <UNDEFINED> instruction: 0xeaffbd60
│ │  	movs	r0, r4
│ │ @@ -563960,15 +563960,15 @@
│ │  	b.n	29b140 <uniffi_pbcli_checksum_method_api_base@@Base+0x12e8bc>
│ │  	movs	r1, r0
│ │  	stmia	r3!, {}
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	29b1ea <uniffi_pbcli_checksum_method_api_base@@Base+0x12e966>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r5, r6, r7, r9, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r4, r8, r9, fp, ip, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffdf4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	29afd4 <uniffi_pbcli_checksum_method_api_base@@Base+0x12e750>
│ │  	ands	r0, r0
│ │  	b.n	29adfe <uniffi_pbcli_checksum_method_api_base@@Base+0x12e57a>
│ │  	cbz	r2, 29ab0a <uniffi_pbcli_checksum_method_api_base@@Base+0x12e286>
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │ @@ -564401,15 +564401,15 @@
│ │  	and.w	r0, r0, r1, lsl #16
│ │  	b.n	29b5b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x12ed32>
│ │  	movs	r4, r0
│ │  	b.n	29b1ba <uniffi_pbcli_checksum_method_api_base@@Base+0x12e936>
│ │  	beq.n	29ae9c <uniffi_pbcli_checksum_method_api_base@@Base+0x12e618>
│ │  	b.n	29b314 <uniffi_pbcli_checksum_method_api_base@@Base+0x12ea90>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r3, r5, r7, fp, lr}
│ │ +	ldmia.w	sp!, {r2, r4, r6, r7, fp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffe048f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	29b3a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x12eb24>
│ │  	beq.n	29aea0 <uniffi_pbcli_checksum_method_api_base@@Base+0x12e61c>
│ │  	b.n	29b32c <uniffi_pbcli_checksum_method_api_base@@Base+0x12eaa8>
│ │  	ands	r0, r0
│ │  	b.n	29b1d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x12e952>
│ │ @@ -564501,16 +564501,16 @@
│ │  	b.n	29aa90 <uniffi_pbcli_checksum_method_api_base@@Base+0x12e20c>
│ │  	cbz	r7, 29af8a <uniffi_pbcli_checksum_method_api_base@@Base+0x12e706>
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	29b69e <uniffi_pbcli_checksum_method_api_base@@Base+0x12ee1a>
│ │  	beq.n	29af80 <uniffi_pbcli_checksum_method_api_base@@Base+0x12e6fc>
│ │  	b.n	29b3f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x12eb74>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r5, r6, r9, sl, ip, sp, lr}
│ │ -	vqdmulh.s32	q13, q8, d14[0]
│ │ +	ldmia.w	sp!, {r0, r3, r7, r9, sl, ip, sp, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffe0acf5
│ │  			@ <UNDEFINED> instruction: 0xffdf48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	29b490 <uniffi_pbcli_checksum_method_api_base@@Base+0x12ec0c>
│ │  	ands	r2, r0
│ │  	b.n	29b2ba <uniffi_pbcli_checksum_method_api_base@@Base+0x12ea36>
│ │  	str	r1, [r0, r0]
│ │  	b.n	29b2be <uniffi_pbcli_checksum_method_api_base@@Base+0x12ea3a>
│ │ @@ -564556,15 +564556,15 @@
│ │  	b.n	29b316 <uniffi_pbcli_checksum_method_api_base@@Base+0x12ea92>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, sp, lr}
│ │  	b.n	29b71e <uniffi_pbcli_checksum_method_api_base@@Base+0x12ee9a>
│ │  	movs	r6, r0
│ │  	b.n	29b322 <uniffi_pbcli_checksum_method_api_base@@Base+0x12ea9e>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r5, r8, r9, sl, lr}
│ │ +	ldmia.w	sp!, {r2, r3, r6, r8, r9, sl, lr}
│ │  			@ <UNDEFINED> instruction: 0xffe048f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	29b50c <uniffi_pbcli_checksum_method_api_base@@Base+0x12ec88>
│ │  	beq.n	29b004 <uniffi_pbcli_checksum_method_api_base@@Base+0x12e780>
│ │  	b.n	29b490 <uniffi_pbcli_checksum_method_api_base@@Base+0x12ec0c>
│ │  	ands	r0, r0
│ │  	b.n	29b73a <uniffi_pbcli_checksum_method_api_base@@Base+0x12eeb6>
│ │ @@ -564631,16 +564631,16 @@
│ │  	and.w	r0, r0, r1, lsl #16
│ │  	b.n	29b7c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x12ef3e>
│ │  	movs	r4, r0
│ │  	b.n	29b3c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x12eb42>
│ │  	beq.n	29b0a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x12e824>
│ │  	b.n	29b520 <uniffi_pbcli_checksum_method_api_base@@Base+0x12ec9c>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r4, r5, r7, sl, ip, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffe0ab52
│ │ +	ldmia.w	sp!, {r0, r3, r4, r6, r7, sl, ip, sp, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffe0ab79
│ │  			@ <UNDEFINED> instruction: 0xffdf4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	29b5b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x12ed34>
│ │  	movs	r0, #96	@ 0x60
│ │  	b.n	29abc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x12e33e>
│ │  	asrs	r0, r0, #32
│ │  	b.n	29b3e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x12eb62>
│ │ @@ -566034,15 +566034,15 @@
│ │  	b.n	29c42e <uniffi_pbcli_checksum_method_api_base@@Base+0x12fbaa>
│ │  	movs	r0, r0
│ │  	b.n	29b83a <uniffi_pbcli_checksum_method_api_base@@Base+0x12efb6>
│ │  	movs	r1, r0
│ │  	b.n	29c476 <uniffi_pbcli_checksum_method_api_base@@Base+0x12fbf2>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r4, r5, r6, r7, r9, fp, ip, sp, pc}
│ │ -	vmull.u16	<illegal reg q9.5>, d14, d1[0]
│ │ +	vmull.u16	<illegal reg q9.5>, d14, d0[3]
│ │  	vcvt.f16.u16	d20, d0, #32
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	29c264 <uniffi_pbcli_checksum_method_api_base@@Base+0x12f9e0>
│ │  	movs	r0, r1
│ │  	b.n	29c24e <uniffi_pbcli_checksum_method_api_base@@Base+0x12f9ca>
│ │  	ands	r2, r0
│ │  	b.n	29c092 <uniffi_pbcli_checksum_method_api_base@@Base+0x12f80e>
│ │ @@ -566645,21 +566645,21 @@
│ │  	b.n	29c5e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x12fd5e>
│ │  	lsls	r1, r0, #10
│ │  	b.n	29c568 <uniffi_pbcli_checksum_method_api_base@@Base+0x12fce4>
│ │  	asrs	r0, r0, #1
│ │  	b.n	29bdb4 <uniffi_pbcli_checksum_method_api_base@@Base+0x12f530>
│ │  			@ <UNDEFINED> instruction: 0xffb8eaff
│ │  	mrc2	15, 5, pc, cr0, cr14, {6}
│ │ -	str	r7, [r7, #72]	@ 0x48
│ │ +	str	r6, [r4, #76]	@ 0x4c
│ │  	vcvt.f32.u32	<illegal reg q15.5>, q14, #32
│ │ -	vraddhn.i32	d22, q15, <illegal reg q5.5>
│ │ +	vsri.64	d22, d18, #34
│ │  	vqrdmulh.s32	<illegal reg q15.5>, q8, d12[0]
│ │ -	vrsra.u64	q11, <illegal reg q5.5>, #34
│ │ +	vraddhn.i32	d22, q7, q1
│ │  			@ <UNDEFINED> instruction: 0xffe0fda0
│ │ -	vsubw.u16	q11, q15, d31
│ │ +	vrsra.u64	q11, q3, #34
│ │  	vqshrun.s64	d20, q8, #32
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	29c7f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x12ff6c>
│ │  	ands	r0, r0
│ │  	b.n	29c61a <uniffi_pbcli_checksum_method_api_base@@Base+0x12fd96>
│ │  	movs	r1, r0
│ │  	b.n	29c61e <uniffi_pbcli_checksum_method_api_base@@Base+0x12fd9a>
│ │ @@ -567129,26 +567129,26 @@
│ │  	b.n	29ce42 <uniffi_pbcli_checksum_method_api_base@@Base+0x1305be>
│ │  	asrs	r0, r1, #32
│ │  	b.n	29cd86 <uniffi_pbcli_checksum_method_api_base@@Base+0x130502>
│ │  	movs	r0, #0
│ │  	b.n	29ce4a <uniffi_pbcli_checksum_method_api_base@@Base+0x1305c6>
│ │  			@ <UNDEFINED> instruction: 0xea5aeb00
│ │  	vpmin.u<illegal width 64>	q15, q10, <illegal reg q15.5>
│ │ -	ldrb	r6, [r7, #2]
│ │ -	vmull.p64	q15, d0, d11
│ │ -	vqrshrun.s32	d23, q11, #1
│ │ -	vqrdmulh.s32	q15, q8, d3[0]
│ │ -	vmlal.u16	<illegal reg q11.5>, d15, d10
│ │ -	vcvt.u16.f16	q15, <illegal reg q3.5>, #32
│ │ -	vqshlu.s64	d23, d6, #31
│ │ -			@ <UNDEFINED> instruction: 0xffe0ebe3
│ │ -	vmlsl.u16	<illegal reg q11.5>, d15, d6[0]
│ │ -			@ <UNDEFINED> instruction: 0xffe0eb93
│ │ -	vmlsl.u16	<illegal reg q11.5>, d15, d6[3]
│ │ -			@ <UNDEFINED> instruction: 0xffe0ebbb
│ │ +	ldrb	r5, [r4, #3]
│ │ +	vcvt.f32.u32	d30, d18, #32
│ │ +			@ <UNDEFINED> instruction: 0xffdf789d
│ │ +	vqrdmulh.s32	q15, q8, d10[1]
│ │ +	vqshrun.s32	d23, <illegal reg q8.5>, #1
│ │ +	vcvt.u16.f16	q15, q15, #32
│ │ +	vqshlu.s64	d23, d29, #31
│ │ +	vmull.u32	q15, d0, d10
│ │ +	vmlsl.u16	<illegal reg q11.5>, d15, d5[3]
│ │ +			@ <UNDEFINED> instruction: 0xffe0ebba
│ │ +	vqshlu.s64	d23, d5, #31
│ │ +			@ <UNDEFINED> instruction: 0xffe0ebe2
│ │  			@ <UNDEFINED> instruction: 0xffdf4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	29cc64 <uniffi_pbcli_checksum_method_api_base@@Base+0x1303e0>
│ │  	beq.n	29c75c <uniffi_pbcli_checksum_method_api_base@@Base+0x12fed8>
│ │  	b.n	29cbe8 <uniffi_pbcli_checksum_method_api_base@@Base+0x130364>
│ │  	str	r0, [r0, #0]
│ │  	b.n	29ce92 <uniffi_pbcli_checksum_method_api_base@@Base+0x13060e>
│ │ @@ -567485,15 +567485,15 @@
│ │  	b.n	29cd6e <uniffi_pbcli_checksum_method_api_base@@Base+0x1304ea>
│ │  	add	r3, sp, #100	@ 0x64
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	29d176 <uniffi_pbcli_checksum_method_api_base@@Base+0x1308f2>
│ │  	beq.n	29ca58 <uniffi_pbcli_checksum_method_api_base@@Base+0x1301d4>
│ │  	b.n	29ced0 <uniffi_pbcli_checksum_method_api_base@@Base+0x13064c>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r2, r5, r8, r9, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r6, r8, r9, ip, sp, lr}
│ │  	vmla.i32	q9, q0, d11[0]
│ │  			@ <UNDEFINED> instruction: 0xffde4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	29cf68 <uniffi_pbcli_checksum_method_api_base@@Base+0x1306e4>
│ │  	beq.n	29ca60 <uniffi_pbcli_checksum_method_api_base@@Base+0x1301dc>
│ │  	b.n	29ceec <uniffi_pbcli_checksum_method_api_base@@Base+0x130668>
│ │  	strb	r3, [r0, #0]
│ │ @@ -567681,21 +567681,21 @@
│ │  	ands	r0, r0
│ │  	b.n	29d332 <uniffi_pbcli_checksum_method_api_base@@Base+0x130aae>
│ │  	movs	r5, r0
│ │  	b.n	29d336 <uniffi_pbcli_checksum_method_api_base@@Base+0x130ab2>
│ │  	asrs	r2, r5, #1
│ │  	b.n	29d33a <uniffi_pbcli_checksum_method_api_base@@Base+0x130ab6>
│ │  			@ <UNDEFINED> instruction: 0xffafeaff
│ │ -	strb	r2, [r1, #10]
│ │ +	strb	r1, [r6, #10]
│ │  	vraddhn.i64	d31, q8, <illegal reg q4.5>
│ │ -	vaddw.u16	<illegal reg q11.5>, q15, d22
│ │ +	vmla.f16	<illegal reg q11.5>, q15, d5[1]
│ │  	vsubw.u32	<illegal reg q15.5>, q8, d21
│ │ -	vsubl.u16	<illegal reg q11.5>, d14, d14
│ │ -	vsra.u64	<illegal reg q11.5>, q3, #32
│ │ -	vsra.u32	<illegal reg q11.5>, q1, #32
│ │ +	vrshr.u16	d23, d21, #2
│ │ +	vsra.u64	<illegal reg q11.5>, <illegal reg q14.5>, #32
│ │ +	vsra.u32	<illegal reg q11.5>, <illegal reg q12.5>, #32
│ │  	vrsra.u32	<illegal reg q15.5>, <illegal reg q0.5>, #32
│ │  			@ <UNDEFINED> instruction: 0xffde4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	29d140 <uniffi_pbcli_checksum_method_api_base@@Base+0x1308bc>
│ │  	beq.n	29cc40 <uniffi_pbcli_checksum_method_api_base@@Base+0x1303bc>
│ │  	b.n	29d0c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x130840>
│ │  	ands	r0, r0
│ │ @@ -568063,22 +568063,22 @@
│ │  	movs	r0, r1
│ │  	b.n	29d296 <uniffi_pbcli_checksum_method_api_base@@Base+0x130a12>
│ │  	add	r1, sp, #828	@ 0x33c
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	29d29e <uniffi_pbcli_checksum_method_api_base@@Base+0x130a1a>
│ │  	ldr	r2, [sp, #516]	@ 0x204
│ │  			@ <UNDEFINED> instruction: 0xebffff64
│ │ -			@ <UNDEFINED> instruction: 0xeaff70de
│ │ -	vmla.i32	<illegal reg q11.5>, q8, d13[1]
│ │ -	vshr.u64	d23, d6, #32
│ │ -	vaddl.u32	<illegal reg q11.5>, d16, d21
│ │ -	vshr.u32	<illegal reg q11.5>, q5, #32
│ │ -	vmla.i32	<illegal reg q11.5>, q0, d9[1]
│ │ -	vmull.p64	q11, d0, d26
│ │ -	vcvt.f32.u32	d22, d25, #32
│ │ +			@ <UNDEFINED> instruction: 0xeaff7105
│ │ +	vsra.u32	d23, d4, #32
│ │ +	vshr.u64	d23, d29, #32
│ │ +	vmla.i32	<illegal reg q11.5>, q8, d12[0]
│ │ +	vaddl.u32	<illegal reg q11.5>, d16, d1
│ │ +	vshr.u64	d23, d0, #32
│ │ +	vcvt.f32.u32	q11, <illegal reg q0.5>, #32
│ │ +	vqrdmlah.s32	q11, q0, d0[1]
│ │  	vmlal.u32	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	29d2ce <uniffi_pbcli_checksum_method_api_base@@Base+0x130a4a>
│ │  	beq.n	29cfa0 <uniffi_pbcli_checksum_method_api_base@@Base+0x13071c>
│ │  	b.n	29d42c <uniffi_pbcli_checksum_method_api_base@@Base+0x130ba8>
│ │  	stmia	r0!, {r0, r1}
│ │  	b.n	29d2d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x130a52>
│ │ @@ -568317,17 +568317,17 @@
│ │  	add.w	r0, r0, r0, lsl #16
│ │  	b.n	29d8ee <uniffi_pbcli_checksum_method_api_base@@Base+0x13106a>
│ │  	movs	r4, r0
│ │  	b.n	29d4f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x130c6e>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r3, r4, r6, r8, r9, sl, sp, lr, pc}
│ │  	vqshlu.s64	q15, <illegal reg q0.5>, #29
│ │ -	vmlsl.u16	<illegal reg q15.5>, d29, d11
│ │ +			@ <UNDEFINED> instruction: 0xffddfab2
│ │  	vsli.64	q15, <illegal reg q10.5>, #31
│ │ -			@ <UNDEFINED> instruction: 0xffddf9af
│ │ +			@ <UNDEFINED> instruction: 0xffddf9d6
│ │  	vaddl.u16	<illegal reg q8.5>, d15, d0
│ │  	b.n	29d50e <uniffi_pbcli_checksum_method_api_base@@Base+0x130c8a>
│ │  	movs	r0, r0
│ │  	b.n	29d912 <uniffi_pbcli_checksum_method_api_base@@Base+0x13108e>
│ │  			@ <UNDEFINED> instruction: 0xff8ceaff
│ │  	ldr	r4, [pc, #64]	@ (29d218 <uniffi_pbcli_checksum_method_api_base@@Base+0x130994>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │ @@ -569255,23 +569255,23 @@
│ │  	ldrsb	r6, [r4, r3]
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	29e16e <uniffi_pbcli_checksum_method_api_base@@Base+0x1318ea>
│ │  	beq.n	29da50 <uniffi_pbcli_checksum_method_api_base@@Base+0x1311cc>
│ │  	b.n	29dec8 <uniffi_pbcli_checksum_method_api_base@@Base+0x131644>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r1, r4, r5, ip}
│ │ -	vsli.64	<illegal reg q9.5>, q10, #31
│ │ +	vqshlu.s16	d19, d11, #15
│ │  	vqrdmlsh.s32	q8, q0, d11[0]
│ │ -	vabal.u16	<illegal reg q9.5>, d15, d12
│ │ +	vsli.16	d19, d19, #15
│ │  			@ <UNDEFINED> instruction: 0xffe00f23
│ │ -	vmls.i16	<illegal reg q9.5>, <illegal reg q15.5>, d4[2]
│ │ +	vabal.u16	<illegal reg q9.5>, d15, d11
│ │  			@ <UNDEFINED> instruction: 0xffe00ef7
│ │ -	vsri.64	d19, d24, #33
│ │ +	vsri.64	<illegal reg q9.5>, <illegal reg q7.5>, #33
│ │  			@ <UNDEFINED> instruction: 0xffe00edb
│ │ -	vsri.64	d19, d12, #33
│ │ +	vmls.i16	<illegal reg q9.5>, <illegal reg q15.5>, d3[0]
│ │  	vqrdmlsh.s32	q8, q0, d7[1]
│ │  	vshr.u16	d17, d4, #1
│ │  	b.n	29d588 <uniffi_pbcli_checksum_method_api_base@@Base+0x130d04>
│ │  	adds	r0, #2
│ │  	b.n	29e1aa <uniffi_pbcli_checksum_method_api_base@@Base+0x131926>
│ │  	lsls	r6, r6, #5
│ │  	and.w	r0, r0, r4, lsr #32
│ │ @@ -569535,19 +569535,19 @@
│ │  	and.w	r0, r0, r0, lsl #24
│ │  	b.n	29e3f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x131b6e>
│ │  	movs	r6, r0
│ │  	b.n	29dff6 <uniffi_pbcli_checksum_method_api_base@@Base+0x131772>
│ │  	beq.n	29dce8 <uniffi_pbcli_checksum_method_api_base@@Base+0x131464>
│ │  	b.n	29e150 <uniffi_pbcli_checksum_method_api_base@@Base+0x1318cc>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r1, r4, r8, fp, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffdfa986
│ │ +	ldmia.w	sp!, {r0, r3, r4, r5, r8, fp, sp, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffdfa9ad
│ │  			@ <UNDEFINED> instruction: 0xffdfdb7a
│ │  			@ <UNDEFINED> instruction: 0xffddcbf1
│ │ -			@ <UNDEFINED> instruction: 0xffdea8f2
│ │ +	vqshrn.u32	d26, <illegal reg q4.5>, #2
│ │  	vshr.u16	d16, d4, #1
│ │  	b.n	29d7f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x130f72>
│ │  	lsls	r4, r2, #14
│ │  	and.w	r0, r0, r1
│ │  	b.n	29e49e <uniffi_pbcli_checksum_method_api_base@@Base+0x131c1a>
│ │  	movs	r3, r0
│ │  	b.n	29e384 <uniffi_pbcli_checksum_method_api_base@@Base+0x131b00>
│ │ @@ -569609,15 +569609,15 @@
│ │  	movs	r0, #0
│ │  	b.n	29e4a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x131c1e>
│ │  	b.n	29d6ec <uniffi_pbcli_checksum_method_api_base@@Base+0x130e68>
│ │  	add.w	r0, r0, r4
│ │  	b.n	29e0aa <uniffi_pbcli_checksum_method_api_base@@Base+0x131826>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r1, r3, r4, r7, r8, r9, fp}
│ │ -			@ <UNDEFINED> instruction: 0xffdfbfac
│ │ +			@ <UNDEFINED> instruction: 0xffdfbfd3
│ │  	vshr.u16	d16, d4, #1
│ │  	b.n	29d89a <uniffi_pbcli_checksum_method_api_base@@Base+0x131016>
│ │  	lsls	r5, r1, #4
│ │  	and.w	r0, r0, r4, lsr #32
│ │  	b.n	29d8a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x13101e>
│ │  	lsls	r4, r5, #1
│ │  	b.n	29d8a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x131022>
│ │ @@ -569788,17 +569788,17 @@
│ │  	asrs	r6, r4, #24
│ │  	add.w	r0, r2, r7
│ │  	b.n	29e23a <uniffi_pbcli_checksum_method_api_base@@Base+0x1319b6>
│ │  	lsrs	r5, r1, #8
│ │  			@ <UNDEFINED> instruction: 0xeb02ffbb
│ │  			@ <UNDEFINED> instruction: 0xeaff64e0
│ │  	vaddw.u16	<illegal reg q13.5>, <illegal reg q7.5>, d17
│ │ -	vshr.u16	q8, q12, #2
│ │ -	vcvt.u16.f16	d23, d14, #32
│ │ -	vmlsl.u16	q10, d15, d6[3]
│ │ +	vshr.u64	d16, d15, #34
│ │ +	vqrdmulh.s32	<illegal reg q11.5>, q0, d5[0]
│ │ +	vqshlu.s64	d20, d5, #31
│ │  			@ <UNDEFINED> instruction: 0xffe048f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	29e438 <uniffi_pbcli_checksum_method_api_base@@Base+0x131bb4>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	29e262 <uniffi_pbcli_checksum_method_api_base@@Base+0x1319de>
│ │  	movs	r1, r0
│ │  	b.n	29e266 <uniffi_pbcli_checksum_method_api_base@@Base+0x1319e2>
│ │ @@ -569881,15 +569881,15 @@
│ │  	str	r0, [r0, #0]
│ │  	b.n	29e716 <uniffi_pbcli_checksum_method_api_base@@Base+0x131e92>
│ │  	b.n	29d826 <uniffi_pbcli_checksum_method_api_base@@Base+0x130fa2>
│ │  	add.w	r0, r0, r6
│ │  	b.n	29e31e <uniffi_pbcli_checksum_method_api_base@@Base+0x131a9a>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r1, r3, r5, r8, fp}
│ │ -			@ <UNDEFINED> instruction: 0xffdf2efc
│ │ +			@ <UNDEFINED> instruction: 0xffdf2f23
│ │  	vqshrun.s64	d20, q8, #32
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	29e50c <uniffi_pbcli_checksum_method_api_base@@Base+0x131c88>
│ │  	str	r0, [r0, r0]
│ │  	b.n	29e336 <uniffi_pbcli_checksum_method_api_base@@Base+0x131ab2>
│ │  	movs	r4, r2
│ │  	b.n	29db1c <uniffi_pbcli_checksum_method_api_base@@Base+0x131298>
│ │ @@ -570077,16 +570077,16 @@
│ │  	strb	r1, [r0, #0]
│ │  	asrs	r0, r0, #12
│ │  	movs	r7, r0
│ │  	b.n	29e4ca <uniffi_pbcli_checksum_method_api_base@@Base+0x131c46>
│ │  	beq.n	29e1c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x131940>
│ │  	b.n	29e624 <uniffi_pbcli_checksum_method_api_base@@Base+0x131da0>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r2, r4, sl, fp, ip, sp, pc}
│ │ -	vmull.u16	<illegal reg q13.5>, d15, d16
│ │ +	ldmia.w	sp!, {r0, r1, r3, r4, r5, sl, fp, ip, sp, pc}
│ │ +	vqdmulh.s16	<illegal reg q13.5>, <illegal reg q7.5>, d7[0]
│ │  	vabdl.u16	<illegal reg q9.5>, d31, d18
│ │  	vmlsl.u16	<illegal reg q14.5>, d14, d4[2]
│ │  	vsra.u64	<illegal reg q15.5>, <illegal reg q6.5>, #35
│ │  	vaddl.u16	<illegal reg q9.5>, d14, d4
│ │  	b.n	29dce8 <uniffi_pbcli_checksum_method_api_base@@Base+0x131464>
│ │  	adds	r0, #3
│ │  	b.n	29e2cc <uniffi_pbcli_checksum_method_api_base@@Base+0x131a48>
│ │ @@ -570260,16 +570260,16 @@
│ │  			@ <UNDEFINED> instruction: 0xebff5000
│ │  	b.n	29ea6a <uniffi_pbcli_checksum_method_api_base@@Base+0x1321e6>
│ │  	movs	r5, r0
│ │  	b.n	29e66e <uniffi_pbcli_checksum_method_api_base@@Base+0x131dea>
│ │  	beq.n	29e350 <uniffi_pbcli_checksum_method_api_base@@Base+0x131acc>
│ │  	b.n	29e7c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x131f44>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r3, r7, r9, lr}
│ │ -	vmul.i32	<illegal reg q11.5>, q8, d14[1]
│ │ +	ldmia.w	sp!, {r0, r4, r5, r7, r9, lr}
│ │ +	vqshrn.u64	d23, <illegal reg q2.5>, #32
│ │  			@ <UNDEFINED> instruction: 0xffdf4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	29e860 <uniffi_pbcli_checksum_method_api_base@@Base+0x131fdc>
│ │  	movs	r0, #96	@ 0x60
│ │  	b.n	29de6a <uniffi_pbcli_checksum_method_api_base@@Base+0x1315e6>
│ │  	asrs	r0, r0, #32
│ │  	b.n	29e68e <uniffi_pbcli_checksum_method_api_base@@Base+0x131e0a>
│ │ @@ -571142,18 +571142,18 @@
│ │  	b.n	29ee32 <uniffi_pbcli_checksum_method_api_base@@Base+0x1325ae>
│ │  	movs	r5, r1
│ │  	add.w	r0, r0, r0, lsl #16
│ │  	b.n	29f23a <uniffi_pbcli_checksum_method_api_base@@Base+0x1329b6>
│ │  	movs	r4, r0
│ │  	b.n	29ee3e <uniffi_pbcli_checksum_method_api_base@@Base+0x1325ba>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r1, r2, r6, r9, fp, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffe069bb
│ │ +	ldmia.w	sp!, {r1, r2, r3, r5, r6, r9, fp, sp, lr}
│ │ +	vmul.f32	q11, q8, d2[1]
│ │  	vqrdmlah.s32	<illegal reg q13.5>, q0, d3[0]
│ │ -			@ <UNDEFINED> instruction: 0xffde68d7
│ │ +			@ <UNDEFINED> instruction: 0xffde68fe
│ │  	vcvt.u16.f16	<illegal reg q13.5>, <illegal reg q7.5>, #32
│ │  	vaddl.u16	<illegal reg q8.5>, d14, d0
│ │  	b.n	29ee5a <uniffi_pbcli_checksum_method_api_base@@Base+0x1325d6>
│ │  	movs	r0, r0
│ │  	b.n	29f25e <uniffi_pbcli_checksum_method_api_base@@Base+0x1329da>
│ │  			@ <UNDEFINED> instruction: 0xff89eaff
│ │  	movs	r0, r0
│ │ @@ -571231,15 +571231,15 @@
│ │  	b.n	29ef0e <uniffi_pbcli_checksum_method_api_base@@Base+0x13268a>
│ │  	movs	r0, #242	@ 0xf2
│ │  	b.n	29f312 <uniffi_pbcli_checksum_method_api_base@@Base+0x132a8e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	29ecf4 <uniffi_pbcli_checksum_method_api_base@@Base+0x132470>
│ │  	ldr	r4, [pc, #64]	@ (29ec18 <uniffi_pbcli_checksum_method_api_base@@Base+0x132394>)
│ │  	ldmia.w	sp!, {r0, r1, r3, r4, r5, r7, fp, ip, sp, lr, pc}
│ │ -	and.w	r7, r1, r7, lsr #27
│ │ +	and.w	r7, r1, lr, ror #27
│ │  	vshr.u32	q8, q0, #32
│ │  	b.n	29f0e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x132862>
│ │  	subs	r7, r3, #6
│ │  	b.n	29ef0a <uniffi_pbcli_checksum_method_api_base@@Base+0x132686>
│ │  	movs	r0, #1
│ │  	b.n	29f0f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x13286c>
│ │  	subs	r7, #146	@ 0x92
│ │ @@ -571845,16 +571845,16 @@
│ │  	b.n	29f73e <uniffi_pbcli_checksum_method_api_base@@Base+0x132eba>
│ │  	add	r0, pc, #32	@ (adr r0, 29f160 <uniffi_pbcli_checksum_method_api_base@@Base+0x1328dc>)
│ │  	b.n	29f7c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x132f3e>
│ │  	vpmin.u32	q7, q13, <illegal reg q15.5>
│ │  	strh	r1, [r1, #0]
│ │  	b.n	29f48a <uniffi_pbcli_checksum_method_api_base@@Base+0x132c06>
│ │  	vpmin.u<illegal width 64>	q7, q11, <illegal reg q15.5>
│ │ -	ldr	r0, [sp, #464]	@ 0x1d0
│ │ -			@ <UNDEFINED> instruction: 0xffdfaf04
│ │ +	ldr	r0, [sp, #620]	@ 0x26c
│ │ +			@ <UNDEFINED> instruction: 0xffdfaf2b
│ │  			@ <UNDEFINED> instruction: 0xffdf4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	29f678 <uniffi_pbcli_checksum_method_api_base@@Base+0x132df4>
│ │  	beq.n	29f1a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x132924>
│ │  	b.n	29f5fc <uniffi_pbcli_checksum_method_api_base@@Base+0x132d78>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	29f4a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x132c22>
│ │ @@ -572320,22 +572320,22 @@
│ │  			@ <UNDEFINED> instruction: 0xebff0009
│ │  	b.n	29f8a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x13301e>
│ │  	add	r0, pc, #132	@ (adr r0, 29f5e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x132d64>)
│ │  			@ <UNDEFINED> instruction: 0xebff0020
│ │  	b.n	29f0a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x132820>
│ │  	add	r0, pc, #124	@ (adr r0, 29f5e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x132d64>)
│ │  			@ <UNDEFINED> instruction: 0xebffff0e
│ │ -			@ <UNDEFINED> instruction: 0xeaff94e8
│ │ -			@ <UNDEFINED> instruction: 0xffdf1d39
│ │ -	vsri.32	d25, d28, #32
│ │ -	vmull.u16	<illegal reg q8.5>, d31, d13
│ │ -	vsra.u64	<illegal reg q12.5>, q10, #32
│ │ -	vmull.u16	<illegal reg q8.5>, d15, d5[0]
│ │ -	vmla.f32	<illegal reg q12.5>, q0, d8[0]
│ │ -			@ <UNDEFINED> instruction: 0xffdf1999
│ │ +			@ <UNDEFINED> instruction: 0xeaff950f
│ │ +	vqrdmulh.s16	<illegal reg q8.5>, <illegal reg q7.5>, d0[2]
│ │ +	vmls.i32	<illegal reg q12.5>, q0, d3[1]
│ │ +			@ <UNDEFINED> instruction: 0xffdf1cb4
│ │ +	vrshr.u32	d25, d11, #32
│ │ +	vmull.u16	<illegal reg q8.5>, d15, d4[3]
│ │ +	vmla.f32	<illegal reg q12.5>, q0, d15[1]
│ │ +	vmul.f16	<illegal reg q8.5>, <illegal reg q15.5>, d0[0]
│ │  	vmlal.u32	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	29f8da <uniffi_pbcli_checksum_method_api_base@@Base+0x133056>
│ │  	beq.n	29f5bc <uniffi_pbcli_checksum_method_api_base@@Base+0x132d38>
│ │  	b.n	29fa38 <uniffi_pbcli_checksum_method_api_base@@Base+0x1331b4>
│ │  	adds	r0, #0
│ │  	b.n	29fce2 <uniffi_pbcli_checksum_method_api_base@@Base+0x13345e>
│ │ @@ -572761,21 +572761,21 @@
│ │  	b.n	29fca2 <uniffi_pbcli_checksum_method_api_base@@Base+0x13341e>
│ │  	add	r2, pc, #404	@ (adr r2, 29faf8 <uniffi_pbcli_checksum_method_api_base@@Base+0x133274>)
│ │  			@ <UNDEFINED> instruction: 0xebff0f10
│ │  	b.n	29fc48 <uniffi_pbcli_checksum_method_api_base@@Base+0x1333c4>
│ │  	str	r2, [sp, #640]	@ 0x280
│ │  	b.n	29fcae <uniffi_pbcli_checksum_method_api_base@@Base+0x13342a>
│ │  	vpmin.u<illegal width 64>	q15, q9, <illegal reg q15.5>
│ │ -	str	r0, [sp, #304]	@ 0x130
│ │ +	str	r0, [sp, #460]	@ 0x1cc
│ │  	vsubl.u16	q9, d31, d12
│ │ -			@ <UNDEFINED> instruction: 0xffde8f04
│ │ +			@ <UNDEFINED> instruction: 0xffde8f2b
│ │  	vmla.f16	q9, <illegal reg q7.5>, d4[0]
│ │ -	vqrdmlsh.s16	q12, q15, d4[1]
│ │ +			@ <UNDEFINED> instruction: 0xffde8ff3
│ │  	vsubl.u16	q9, d15, d12
│ │ -			@ <UNDEFINED> instruction: 0xffde8f5c
│ │ +			@ <UNDEFINED> instruction: 0xffde8f83
│ │  	vsra.u64	d18, d12, #33
│ │  	vmla.i16	<illegal reg q8.5>, q7, d0[1]
│ │  	b.n	29f4b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x132c32>
│ │  	movs	r0, #108	@ 0x6c
│ │  	b.n	29f4ba <uniffi_pbcli_checksum_method_api_base@@Base+0x132c36>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2a00a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x13381c>
│ │ @@ -574501,15 +574501,15 @@
│ │  	add.w	r0, r0, r0, lsl #16
│ │  	b.n	2a0fca <uniffi_pbcli_checksum_method_api_base@@Base+0x134746>
│ │  	movs	r4, r0
│ │  	b.n	2a0bce <uniffi_pbcli_checksum_method_api_base@@Base+0x13434a>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r3, r5, r6, r7, r8, r9, sl, sp}
│ │  	vqshl.u16	q9, <illegal reg q10.5>, #15
│ │ -			@ <UNDEFINED> instruction: 0xffdf4b74
│ │ +			@ <UNDEFINED> instruction: 0xffdf4b9b
│ │  	vcvt.f16.u16	q10, q8, #32
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2a0dc0 <uniffi_pbcli_checksum_method_api_base@@Base+0x13453c>
│ │  	ands	r1, r0
│ │  	b.n	2a0fea <uniffi_pbcli_checksum_method_api_base@@Base+0x134766>
│ │  	movs	r0, r0
│ │  	b.n	2a0f4e <uniffi_pbcli_checksum_method_api_base@@Base+0x1346ca>
│ │ @@ -574643,17 +574643,17 @@
│ │  	movs	r0, #0
│ │  	b.n	2a110e <uniffi_pbcli_checksum_method_api_base@@Base+0x13488a>
│ │  	bls.n	2a0922 <uniffi_pbcli_checksum_method_api_base@@Base+0x13409e>
│ │  	add.w	r0, r0, r4
│ │  	b.n	2a0d16 <uniffi_pbcli_checksum_method_api_base@@Base+0x134492>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r3, r9, sl, sp}
│ │ -			@ <UNDEFINED> instruction: 0xffdf1b80
│ │ +			@ <UNDEFINED> instruction: 0xffdf1ba7
│ │  	vqshlu.s32	d18, d21, #0
│ │ -			@ <UNDEFINED> instruction: 0xffdf1bac
│ │ +			@ <UNDEFINED> instruction: 0xffdf1bd3
│ │  	vqshlu.s32	q9, <illegal reg q12.5>, #0
│ │  	vaddl.u16	q8, d15, d0
│ │  	b.n	2a1092 <uniffi_pbcli_checksum_method_api_base@@Base+0x13480e>
│ │  	movs	r4, r1
│ │  	asrs	r0, r2, #22
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │ @@ -574836,21 +574836,21 @@
│ │  			@ <UNDEFINED> instruction: 0xffd3eaff
│ │  	str	r7, [r4, #4]
│ │  	b.n	2a12ce <uniffi_pbcli_checksum_method_api_base@@Base+0x134a4a>
│ │  	strb	r3, [r2, #2]
│ │  	b.n	2a12d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x134a4e>
│ │  			@ <UNDEFINED> instruction: 0xffd0eaff
│ │  	movs	r5, #21
│ │ -	vshr.u64	d28, d13, #33
│ │ +	vmla.i16	q14, <illegal reg q15.5>, d4[0]
│ │  	vmls.f16	q9, <illegal reg q7.5>, d5[1]
│ │  			@ <UNDEFINED> instruction: 0xffdfad28
│ │  	vsri.64	d18, d1, #35
│ │  	vsri.16	q9, <illegal reg q8.5>, #1
│ │  	vsri.64	q9, <illegal reg q0.5>, #33
│ │ -	vshr.u16	q14, <illegal reg q4.5>, #1
│ │ +	vaddl.u16	q14, d31, d0
│ │  	vmlal.u16	q10, d15, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2a0efe <uniffi_pbcli_checksum_method_api_base@@Base+0x13467a>
│ │  	movs	r0, r0
│ │  	b.n	2a1262 <uniffi_pbcli_checksum_method_api_base@@Base+0x1349de>
│ │  	movs	r5, r2
│ │  	lsrs	r0, r0, #8
│ │ @@ -575037,15 +575037,15 @@
│ │  	ands	r0, r0
│ │  	b.n	2a14aa <uniffi_pbcli_checksum_method_api_base@@Base+0x134c26>
│ │  	bhi.n	2a0cf0 <uniffi_pbcli_checksum_method_api_base@@Base+0x13446c>
│ │  	add.w	r0, r0, r4
│ │  	b.n	2a10b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x13482e>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r0, r4, r5, r6, r9, sp}
│ │ -	vsri.64	d29, d17, #33
│ │ +	vsri.64	<illegal reg q14.5>, q4, #33
│ │  	vmlal.u16	q10, d15, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2a10c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x134842>
│ │  	movs	r0, r0
│ │  	b.n	2a142a <uniffi_pbcli_checksum_method_api_base@@Base+0x134ba6>
│ │  	movs	r0, r0
│ │  	asrs	r1, r2, #13
│ │ @@ -575093,15 +575093,15 @@
│ │  	movs	r0, r0
│ │  	b.n	2a1494 <uniffi_pbcli_checksum_method_api_base@@Base+0x134c10>
│ │  			@ <UNDEFINED> instruction: 0xfff30aff
│ │  	ldr	r0, [pc, #0]	@ (2a0df4 <uniffi_pbcli_checksum_method_api_base@@Base+0x134570>)
│ │  	ldmia.w	sp!, {r0, r1, r4, r8, r9, sl, fp, ip, sp, lr, pc}
│ │  	b.n	2a1058 <uniffi_pbcli_checksum_method_api_base@@Base+0x1347d4>
│ │  	movs	r2, #25
│ │ -			@ <UNDEFINED> instruction: 0xffdf4f7f
│ │ +			@ <UNDEFINED> instruction: 0xffdf4fa6
│ │  	vqshrun.s32	d20, q8, #1
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2a1324 <uniffi_pbcli_checksum_method_api_base@@Base+0x134aa0>
│ │  	movs	r0, r0
│ │  	b.n	2a14ae <uniffi_pbcli_checksum_method_api_base@@Base+0x134c2a>
│ │  	movs	r7, r3
│ │  	lsrs	r0, r0, #8
│ │ @@ -575366,21 +575366,21 @@
│ │  	b.n	2a13a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x134b1e>
│ │  	ble.n	2a10a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x13481c>
│ │  	add.w	r0, r7, r6
│ │  	b.n	2a13aa <uniffi_pbcli_checksum_method_api_base@@Base+0x134b26>
│ │  	beq.n	2a109c <uniffi_pbcli_checksum_method_api_base@@Base+0x134818>
│ │  	b.n	2a1504 <uniffi_pbcli_checksum_method_api_base@@Base+0x134c80>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r7, r8, sl, ip}
│ │ +	ldmia.w	sp!, {r2, r6, r7, r8, sl, ip}
│ │  	vrsubhn.i64	d23, q8, <illegal reg q9.5>
│ │ -	vmls.f16	<illegal reg q8.5>, <illegal reg q6.5>, d5[3]
│ │ +	vsli.64	d17, d4, #29
│ │  	vqshlu.s32	<illegal reg q11.5>, <illegal reg q9.5>, #0
│ │  			@ <UNDEFINED> instruction: 0xffddc360
│ │ -	vsli.16	d17, d21, #14
│ │ -	vsli.32	d17, d5, #0
│ │ +	vsli.16	<illegal reg q8.5>, q6, #14
│ │ +	vsli.32	d17, d28, #0
│ │  	vqshlu.s32	d23, d11, #0
│ │  	vqshrun.s32	d20, q8, #3
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2a15b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x134d30>
│ │  	movs	r0, r0
│ │  	b.n	2a173e <uniffi_pbcli_checksum_method_api_base@@Base+0x134eba>
│ │  	movs	r4, r1
│ │ @@ -575458,17 +575458,17 @@
│ │  	b.n	2a0c70 <uniffi_pbcli_checksum_method_api_base@@Base+0x1343ec>
│ │  	asrs	r0, r0, #32
│ │  	b.n	2a188a <uniffi_pbcli_checksum_method_api_base@@Base+0x135006>
│ │  	lsrs	r0, r1, #1
│ │  	add.w	r0, r3, r4
│ │  	b.n	2a1492 <uniffi_pbcli_checksum_method_api_base@@Base+0x134c0e>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r6, sl, ip}
│ │ +	ldmia.w	sp!, {r7, sl, ip}
│ │  	vcvt.f32.u32	<illegal reg q11.5>, <illegal reg q11.5>, #32
│ │ -	vsri.16	d17, d13, #2
│ │ +	vmls.i16	<illegal reg q8.5>, q7, d4[0]
│ │  	vcvt.f32.u32	d23, d27, #32
│ │  	vqshrun.s32	d20, q8, #2
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2a1688 <uniffi_pbcli_checksum_method_api_base@@Base+0x134e04>
│ │  	beq.n	2a1180 <uniffi_pbcli_checksum_method_api_base@@Base+0x1348fc>
│ │  	b.n	2a160c <uniffi_pbcli_checksum_method_api_base@@Base+0x134d88>
│ │  	movs	r0, r0
│ │ @@ -575603,23 +575603,23 @@
│ │  	b.n	2a13b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x134b34>
│ │  	adds	r0, #4
│ │  	b.n	2a15de <uniffi_pbcli_checksum_method_api_base@@Base+0x134d5a>
│ │  	bvc.n	2a138a <uniffi_pbcli_checksum_method_api_base@@Base+0x134b06>
│ │  	add.w	r0, r0, r0, lsl #20
│ │  	b.n	2a19e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x135162>
│ │  			@ <UNDEFINED> instruction: 0xffebeaff
│ │ -	asrs	r5, r5, #14
│ │ +	asrs	r4, r2, #15
│ │  			@ <UNDEFINED> instruction: 0xffe04ed8
│ │ -	vrsra.u16	d17, d17, #2
│ │ +	vrsra.u16	<illegal reg q8.5>, q4, #2
│ │  	vcvt.f32.u32	q10, q6, #32
│ │ -	vsubw.u16	<illegal reg q8.5>, q7, d5
│ │ +	vsubw.u16	<illegal reg q8.5>, q7, d28
│ │  	vcvt.f32.u32	d20, d16, #32
│ │ -	vmlal.u16	<illegal reg q8.5>, d30, d1[1]
│ │ +	vrshr.u64	<illegal reg q8.5>, q8, #34
│ │  			@ <UNDEFINED> instruction: 0xffe04df4
│ │ -			@ <UNDEFINED> instruction: 0xffdecf7a
│ │ +			@ <UNDEFINED> instruction: 0xffdecfa1
│ │  			@ <UNDEFINED> instruction: 0xffdf48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2a17f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x134f6c>
│ │  	str	r0, [r0, #0]
│ │  	b.n	2a161a <uniffi_pbcli_checksum_method_api_base@@Base+0x134d96>
│ │  	movs	r1, r0
│ │  	b.n	2a161e <uniffi_pbcli_checksum_method_api_base@@Base+0x134d9a>
│ │ @@ -575733,20 +575733,20 @@
│ │  	b.n	2a170e <uniffi_pbcli_checksum_method_api_base@@Base+0x134e8a>
│ │  	adds	r0, #4
│ │  	b.n	2a1712 <uniffi_pbcli_checksum_method_api_base@@Base+0x134e8e>
│ │  	strb	r3, [r4, #17]
│ │  			@ <UNDEFINED> instruction: 0xebff0005
│ │  	b.n	2a171a <uniffi_pbcli_checksum_method_api_base@@Base+0x134e96>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r4, r5, r6, r7, r8, ip}
│ │ +	ldmia.w	sp!, {r3, r4, r9, ip}
│ │  	vabal.u32	<illegal reg q14.5>, d16, d15
│ │ -	vrshr.u16	d17, d21, #2
│ │ -	vaddw.u32	<illegal reg q8.5>, q8, d25
│ │ +	vrshr.u16	<illegal reg q8.5>, q6, #2
│ │ +	vsra.u64	<illegal reg q8.5>, q0, #32
│ │  	vsli.32	<illegal reg q14.5>, q7, #0
│ │ -			@ <UNDEFINED> instruction: 0xffdefb18
│ │ +			@ <UNDEFINED> instruction: 0xffdefb3f
│ │  			@ <UNDEFINED> instruction: 0xffdfef2d
│ │  			@ <UNDEFINED> instruction: 0xffdd4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2a191c <uniffi_pbcli_checksum_method_api_base@@Base+0x135098>
│ │  	movs	r2, r0
│ │  	b.n	2a1728 <uniffi_pbcli_checksum_method_api_base@@Base+0x134ea4>
│ │  	movs	r5, r1
│ │ @@ -575883,19 +575883,19 @@
│ │  	b.n	2a186a <uniffi_pbcli_checksum_method_api_base@@Base+0x134fe6>
│ │  	blt.n	2a1494 <uniffi_pbcli_checksum_method_api_base@@Base+0x134c10>
│ │  	add.w	r0, r7, r7, lsl #24
│ │  	b.n	2a1872 <uniffi_pbcli_checksum_method_api_base@@Base+0x134fee>
│ │  	movs	r6, r0
│ │  	b.n	2a1876 <uniffi_pbcli_checksum_method_api_base@@Base+0x134ff2>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r2, r3, r5, r6, r7, ip}
│ │ -	vaddw.u32	<illegal reg q8.5>, q0, d0
│ │ -	vaddw.u32	<illegal reg q8.5>, q0, d5
│ │ -	vshr.u64	d17, d21, #32
│ │ -	vmla.i32	<illegal reg q8.5>, q0, d5[0]
│ │ +	ldmia.w	sp!, {r2, r4, r8, ip}
│ │ +	vaddw.u32	<illegal reg q8.5>, q0, d23
│ │ +	vaddw.u32	<illegal reg q8.5>, q0, d28
│ │ +	vshr.u64	<illegal reg q8.5>, q6, #32
│ │ +	vmla.i32	<illegal reg q8.5>, q0, d12[1]
│ │  	vaddl.u32	q8, d0, d0
│ │  	b.n	2a1d12 <uniffi_pbcli_checksum_method_api_base@@Base+0x13548e>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (2a1618 <uniffi_pbcli_checksum_method_api_base@@Base+0x134d94>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2a1a78 <uniffi_pbcli_checksum_method_api_base@@Base+0x1351f4>
│ │  	ands	r0, r0
│ │ @@ -576172,15 +576172,15 @@
│ │  	str	r0, [r2, #0]
│ │  	b.n	2a12fc <uniffi_pbcli_checksum_method_api_base@@Base+0x134a78>
│ │  	movs	r0, r2
│ │  	b.n	2a1e72 <uniffi_pbcli_checksum_method_api_base@@Base+0x1355ee>
│ │  			@ <UNDEFINED> instruction: 0xffe20aff
│ │  			@ <UNDEFINED> instruction: 0xffe3eaff
│ │  	rev16	r1, r7
│ │ -			@ <UNDEFINED> instruction: 0xffdddf8e
│ │ +			@ <UNDEFINED> instruction: 0xffdddfb5
│ │  			@ <UNDEFINED> instruction: 0xffdfbb1d
│ │  			@ <UNDEFINED> instruction: 0xffddba99
│ │  			@ <UNDEFINED> instruction: 0xffdd4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2a1d00 <uniffi_pbcli_checksum_method_api_base@@Base+0x13547c>
│ │  	str	r0, [r0, r0]
│ │  	b.n	2a1b2a <uniffi_pbcli_checksum_method_api_base@@Base+0x1352a6>
│ │ @@ -576790,15 +576790,15 @@
│ │  	movs	r0, #0
│ │  	b.n	2a24c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x135c3e>
│ │  	bmi.n	2a1cfc <uniffi_pbcli_checksum_method_api_base@@Base+0x135478>
│ │  	add.w	r0, r0, r0
│ │  	b.n	2a24ca <uniffi_pbcli_checksum_method_api_base@@Base+0x135c46>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r3, r4, r7, sl, ip, sp, pc}
│ │ -	vqrdmlsh.s16	<illegal reg q9.5>, <illegal reg q14.5>, d1[0]
│ │ +	vqrdmlsh.s16	<illegal reg q9.5>, <illegal reg q14.5>, d0[3]
│ │  	vshr.u16	d16, d4, #1
│ │  	b.n	2a18ba <uniffi_pbcli_checksum_method_api_base@@Base+0x135036>
│ │  	movs	r0, r7
│ │  	b.n	2a18be <uniffi_pbcli_checksum_method_api_base@@Base+0x13503a>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r7, [pc, #960]	@ (2a2164 <uniffi_pbcli_checksum_method_api_base@@Base+0x1358e0>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │ @@ -577026,16 +577026,16 @@
│ │  	movs	r4, r0
│ │  	b.n	2a22da <uniffi_pbcli_checksum_method_api_base@@Base+0x135a56>
│ │  	strh	r2, [r5, #56]	@ 0x38
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	2a22e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x135a5e>
│ │  	strh	r0, [r6, #50]	@ 0x32
│ │  			@ <UNDEFINED> instruction: 0xebffff87
│ │ -			@ <UNDEFINED> instruction: 0xeaff3cee
│ │ -	vrsubhn.i32	d16, <illegal reg q7.5>, q15
│ │ +			@ <UNDEFINED> instruction: 0xeaff3d15
│ │ +	vqshlu.s16	q8, <illegal reg q2.5>, #15
│ │  	vmla.i32	<illegal reg q8.5>, q8, d8[0]
│ │  	vsubl.u16	<illegal reg q13.5>, d31, d13
│ │  			@ <UNDEFINED> instruction: 0xffdd48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2a24dc <uniffi_pbcli_checksum_method_api_base@@Base+0x135c58>
│ │  	str	r0, [r0, #0]
│ │  	b.n	2a2306 <uniffi_pbcli_checksum_method_api_base@@Base+0x135a82>
│ │ @@ -577514,25 +577514,25 @@
│ │  			@ <UNDEFINED> instruction: 0xeab9eb01
│ │  	movs	r4, r0
│ │  	b.n	2a272a <uniffi_pbcli_checksum_method_api_base@@Base+0x135ea6>
│ │  	beq.n	2a2424 <uniffi_pbcli_checksum_method_api_base@@Base+0x135ba0>
│ │  	b.n	2a2884 <uniffi_pbcli_checksum_method_api_base@@Base+0x136000>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r4, r6, r7, r9, sl, fp, sp, pc}
│ │ -	vrsra.u16	q11, q3, #3
│ │ +	vrsra.u16	q11, <illegal reg q14.5>, #3
│ │  	vqshlu.s64	q14, q8, #31
│ │  	vqrdmulh.s16	<illegal reg q12.5>, q7, d4[1]
│ │ -			@ <UNDEFINED> instruction: 0xffde7a98
│ │ -			@ <UNDEFINED> instruction: 0xffdf7ab0
│ │ +			@ <UNDEFINED> instruction: 0xffde7abf
│ │ +			@ <UNDEFINED> instruction: 0xffdf7ad7
│ │  			@ <UNDEFINED> instruction: 0xffdf6cf9
│ │ -	vsubl.u16	<illegal reg q14.5>, d14, d18
│ │ -	vshr.u64	<illegal reg q9.5>, <illegal reg q13.5>, #33
│ │ -	vsra.u64	<illegal reg q14.5>, q3, #32
│ │ +	vmlal.u16	<illegal reg q14.5>, d14, d1[1]
│ │ +	vaddw.u16	<illegal reg q9.5>, <illegal reg q7.5>, d18
│ │ +	vsra.u64	<illegal reg q14.5>, <illegal reg q14.5>, #32
│ │  	vqrdmlah.s16	q13, <illegal reg q7.5>, d5[3]
│ │ -	vrshr.u64	q11, q9, #35
│ │ +	vrsra.u16	d22, d9, #3
│ │  			@ <UNDEFINED> instruction: 0xffdfae3d
│ │  			@ <UNDEFINED> instruction: 0xffdd48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2a2948 <uniffi_pbcli_checksum_method_api_base@@Base+0x1360c4>
│ │  	movs	r0, r0
│ │  	b.n	2a2ad6 <uniffi_pbcli_checksum_method_api_base@@Base+0x136252>
│ │  	movs	r0, r3
│ │ @@ -578698,39 +578698,39 @@
│ │  	b.n	2a298a <uniffi_pbcli_checksum_method_api_base@@Base+0x136106>
│ │  	mcr2	10, 7, lr, cr4, cr15, {7}	@ <UNPREDICTABLE>
│ │  	bics	r0, r4
│ │  	movs	r0, r4
│ │  	ldrh	r3, [r3, #58]	@ 0x3a
│ │  	vabdl.u16	<illegal reg q12.5>, d13, d19
│ │  			@ <UNDEFINED> instruction: 0xffde8f27
│ │ -	vmls.i16	<illegal reg q9.5>, <illegal reg q14.5>, d6[0]
│ │ +	vmls.i16	<illegal reg q9.5>, <illegal reg q14.5>, d5[3]
│ │  	vmull.p<illegal width 16>	q12, d15, d31
│ │ -			@ <UNDEFINED> instruction: 0xffdd33ce
│ │ +	vrsra.u64	<illegal reg q9.5>, <illegal reg q10.5>, #35
│ │  	vqrdmulh.s16	q12, <illegal reg q15.5>, d7[2]
│ │ -	vsubw.u16	<illegal reg q9.5>, <illegal reg q14.5>, d6
│ │ +	vsubw.u16	<illegal reg q9.5>, <illegal reg q14.5>, d29
│ │  			@ <UNDEFINED> instruction: 0xffdf8d37
│ │ -	vrshr.u64	<illegal reg q9.5>, q3, #35
│ │ +	vrshr.u64	<illegal reg q9.5>, <illegal reg q14.5>, #35
│ │  	vrshr.u16	d20, d24, #1
│ │  	movs	r0, r4
│ │  	ldrh	r3, [r1, #48]	@ 0x30
│ │ -	vsubw.u16	<illegal reg q9.5>, <illegal reg q14.5>, d26
│ │ +	vrsra.u64	<illegal reg q9.5>, <illegal reg q0.5>, #35
│ │  	vqrdmulh.s16	q12, <illegal reg q15.5>, d7[0]
│ │ -			@ <UNDEFINED> instruction: 0xffdd3366
│ │ +	vsubw.u16	<illegal reg q9.5>, <illegal reg q14.5>, d13
│ │  			@ <UNDEFINED> instruction: 0xffdf8d13
│ │ -	vrshr.u64	d19, d18, #35
│ │ +	vrshr.u64	<illegal reg q9.5>, <illegal reg q4.5>, #35
│ │  	vmull.u16	q12, d15, d3
│ │ -	vaddw.u16	<illegal reg q9.5>, <illegal reg q14.5>, d18
│ │ +	vmla.f16	<illegal reg q9.5>, <illegal reg q14.5>, d1[1]
│ │  	vqrdmlsh.s16	<illegal reg q9.5>, <illegal reg q15.5>, d0[0]
│ │  	movs	r0, r4
│ │  	ldrh	r7, [r4, #30]
│ │ -	vaddw.u16	<illegal reg q9.5>, <illegal reg q14.5>, d6
│ │ +	vaddw.u16	<illegal reg q9.5>, <illegal reg q14.5>, d29
│ │  	vmull.u16	q12, d31, d7
│ │ -	vsubl.u16	<illegal reg q9.5>, d13, d22
│ │ +	vmlal.u16	<illegal reg q9.5>, d13, d5[1]
│ │  			@ <UNDEFINED> instruction: 0xffdf8e5b
│ │ -	vrsra.u64	<illegal reg q9.5>, q13, #35
│ │ +	vraddhn.i32	d19, <illegal reg q6.5>, <illegal reg q8.5>
│ │  	vqdmulh.s16	q12, <illegal reg q7.5>, d7[2]
│ │  	vqshl.u16	<illegal reg q14.5>, q9, #13
│ │  			@ <UNDEFINED> instruction: 0xffdd8bb3
│ │  	vqshlu.s64	d29, d30, #29
│ │  	vmla.i16	<illegal reg q12.5>, <illegal reg q6.5>, d7[2]
│ │  	vmla.i16	<illegal reg q12.5>, <illegal reg q6.5>, d3[0]
│ │  			@ <UNDEFINED> instruction: 0xffdd8b4b
│ │ @@ -578907,19 +578907,19 @@
│ │  	b.n	2a37ea <uniffi_pbcli_checksum_method_api_base@@Base+0x136f66>
│ │  	movs	r4, r0
│ │  	b.n	2a33ee <uniffi_pbcli_checksum_method_api_base@@Base+0x136b6a>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r3, r4, r5, r7, r9, fp, ip, sp}
│ │  	movs	r0, r4
│ │  	ldrh	r3, [r2, #0]
│ │ -			@ <UNDEFINED> instruction: 0xffdddf36
│ │ +			@ <UNDEFINED> instruction: 0xffdddf5d
│ │  	vmul.f16	<illegal reg q9.5>, <illegal reg q15.5>, d4[0]
│ │  	movs	r0, r4
│ │  	strh	r7, [r7, #56]	@ 0x38
│ │ -	vqrdmlah.s16	<illegal reg q14.5>, <illegal reg q6.5>, d2[2]
│ │ +	vmull.p<illegal width 16>	<illegal reg q14.5>, d29, d9
│ │  			@ <UNDEFINED> instruction: 0xffdf399c
│ │  	movs	r0, r4
│ │  	ldr	r7, [pc, #960]	@ (2a3490 <uniffi_pbcli_checksum_method_api_base@@Base+0x136c0c>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2a35f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x136d6c>
│ │  	beq.n	2a3110 <uniffi_pbcli_checksum_method_api_base@@Base+0x13688c>
│ │  	b.n	2a3574 <uniffi_pbcli_checksum_method_api_base@@Base+0x136cf0>
│ │ @@ -579920,15 +579920,15 @@
│ │  	b.n	2a3488 <uniffi_pbcli_checksum_method_api_base@@Base+0x136c04>
│ │  	str	r0, [r1, #0]
│ │  	b.n	2a348c <uniffi_pbcli_checksum_method_api_base@@Base+0x136c08>
│ │  	str	r0, [sp, #16]
│ │  	b.n	2a3490 <uniffi_pbcli_checksum_method_api_base@@Base+0x136c0c>
│ │  	mcr2	10, 0, lr, cr0, cr15, {7}	@ <UNPREDICTABLE>
│ │  	strh	r3, [r1, #50]	@ 0x32
│ │ -	vmla.f16	q12, <illegal reg q6.5>, d4[0]
│ │ +	vmla.f16	q12, <illegal reg q6.5>, d3[3]
│ │  	vrshr.u64	d24, d3, #33
│ │  			@ <UNDEFINED> instruction: 0xffdd4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2a3e88 <uniffi_pbcli_checksum_method_api_base@@Base+0x137604>
│ │  	movs	r0, r0
│ │  	b.n	2a4012 <uniffi_pbcli_checksum_method_api_base@@Base+0x13778e>
│ │  	movs	r6, r1
│ │ @@ -580245,19 +580245,19 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	2a3d64 <uniffi_pbcli_checksum_method_api_base@@Base+0x1374e0>
│ │  	strh	r2, [r7, r0]
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	2a3f8e <uniffi_pbcli_checksum_method_api_base@@Base+0x13770a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r1, r4, r6, r7, r8, r9, fp, ip, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffdd17ec
│ │ +	vqshrun.s32	d17, <illegal reg q1.5>, #3
│ │  	vcvt.f32.u32	q9, q14, #32
│ │  	movs	r0, r4
│ │  	ldrb	r7, [r3, #14]
│ │ -	vqshl.u64	d17, d24, #29
│ │ +	vqshl.u64	<illegal reg q8.5>, <illegal reg q7.5>, #29
│ │  			@ <UNDEFINED> instruction: 0xffe02df8
│ │  	movs	r0, r4
│ │  	ldr	r7, [pc, #960]	@ (2a402c <uniffi_pbcli_checksum_method_api_base@@Base+0x1377a8>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2a418c <uniffi_pbcli_checksum_method_api_base@@Base+0x137908>
│ │  	beq.n	2a3c7c <uniffi_pbcli_checksum_method_api_base@@Base+0x1373f8>
│ │  	b.n	2a4110 <uniffi_pbcli_checksum_method_api_base@@Base+0x13788c>
│ │ @@ -580847,34 +580847,34 @@
│ │  	ldmia	r3, {r2, r3, r4, r5, r6}
│ │  	add.w	r0, r0, r0, lsr #4
│ │  	b.n	2a4796 <uniffi_pbcli_checksum_method_api_base@@Base+0x137f12>
│ │  	asrs	r0, r1, #32
│ │  	b.n	2a481a <uniffi_pbcli_checksum_method_api_base@@Base+0x137f96>
│ │  			@ <UNDEFINED> instruction: 0xfff1eaff
│ │  	ldrb	r3, [r5, #2]
│ │ -	vsri.64	<illegal reg q8.5>, <illegal reg q3.5>, #35
│ │ +	vsri.64	<illegal reg q8.5>, q15, #35
│ │  	vcvt.u16.f16	d18, d12, #32
│ │  	movs	r0, r4
│ │  	strb	r3, [r3, #28]
│ │ -			@ <UNDEFINED> instruction: 0xffdd1347
│ │ +			@ <UNDEFINED> instruction: 0xffdd136e
│ │  	vmlsl.u32	<illegal reg q11.5>, d16, d15[1]
│ │ -	vrsra.u16	d17, d11, #3
│ │ +			@ <UNDEFINED> instruction: 0xffdd1342
│ │  	vmlsl.u32	<illegal reg q11.5>, d0, d15[1]
│ │ -	vrshr.u64	d17, d11, #35
│ │ +	vmlal.u16	<illegal reg q8.5>, d29, d2[0]
│ │  	vqshlu.s32	d23, d19, #0
│ │ -	vrshr.u16	<illegal reg q8.5>, <illegal reg q7.5>, #3
│ │ +	vsubl.u16	<illegal reg q8.5>, d29, d6
│ │  	vqdmulh.s32	q9, q0, d0[0]
│ │  	movs	r0, r4
│ │  	strb	r3, [r6, #26]
│ │ -	vrshr.u64	<illegal reg q8.5>, <illegal reg q7.5>, #35
│ │ +	vsubw.u16	<illegal reg q8.5>, <illegal reg q6.5>, d6
│ │  	vqrshrun.s64	d23, <illegal reg q9.5>, #32
│ │  	vqrdmulh.s16	q9, <illegal reg q6.5>, d4[1]
│ │  	movs	r0, r4
│ │  	strb	r7, [r2, #26]
│ │ -	vmlal.u16	<illegal reg q8.5>, d29, d3[0]
│ │ +	vmlal.u16	<illegal reg q8.5>, d29, d2[3]
│ │  	vmlal.u32	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2a452e <uniffi_pbcli_checksum_method_api_base@@Base+0x137caa>
│ │  	movs	r0, r0
│ │  	b.n	2a4892 <uniffi_pbcli_checksum_method_api_base@@Base+0x13800e>
│ │  	movs	r2, r0
│ │  	lsrs	r0, r0, #8
│ │ @@ -580903,15 +580903,15 @@
│ │  	movs	r0, #0
│ │  	b.n	2a496e <uniffi_pbcli_checksum_method_api_base@@Base+0x1380ea>
│ │  	ldmia	r3!, {r0, r4, r7}
│ │  	add.w	r0, r0, r0
│ │  	b.n	2a4976 <uniffi_pbcli_checksum_method_api_base@@Base+0x1380f2>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r1, r2, r5, r7, r8, sl, ip, sp, lr}
│ │ -	vshr.u64	d23, d31, #35
│ │ +	vmla.i16	<illegal reg q11.5>, <illegal reg q14.5>, d6[2]
│ │  			@ <UNDEFINED> instruction: 0xffdf48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2a4764 <uniffi_pbcli_checksum_method_api_base@@Base+0x137ee0>
│ │  	movs	r0, r0
│ │  	b.n	2a48f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x13806c>
│ │  	movs	r6, r2
│ │  	lsrs	r0, r0, #8
│ │ @@ -581057,17 +581057,17 @@
│ │  	b.n	2a488a <uniffi_pbcli_checksum_method_api_base@@Base+0x138006>
│ │  	movs	r0, r7
│ │  	b.n	2a3e96 <uniffi_pbcli_checksum_method_api_base@@Base+0x137612>
│ │  	movs	r0, r0
│ │  	b.n	2a4ad2 <uniffi_pbcli_checksum_method_api_base@@Base+0x13824e>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r1, r3, r4, r5, r6, r7, sl, ip, sp, lr}
│ │ -	vaddl.u16	<illegal reg q11.5>, d13, d20
│ │ +	vmla.i16	<illegal reg q11.5>, <illegal reg q6.5>, d3[1]
│ │  	vmls.i16	<illegal reg q11.5>, <illegal reg q7.5>, d7[1]
│ │ -			@ <UNDEFINED> instruction: 0xffdd6f78
│ │ +			@ <UNDEFINED> instruction: 0xffdd6f9f
│ │  			@ <UNDEFINED> instruction: 0xffdf48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2a48c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x138044>
│ │  	movs	r0, r0
│ │  	b.n	2a4a52 <uniffi_pbcli_checksum_method_api_base@@Base+0x1381ce>
│ │  	strb	r0, [r0, #0]
│ │  	asrs	r0, r2, #22
│ │ @@ -581313,18 +581313,18 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	2a40da <uniffi_pbcli_checksum_method_api_base@@Base+0x137856>
│ │  			@ <UNDEFINED> instruction: 0xffcbeaff
│ │  	str	r0, [r0, r0]
│ │  	b.n	2a4d1a <uniffi_pbcli_checksum_method_api_base@@Base+0x138496>
│ │  			@ <UNDEFINED> instruction: 0xffc9eaff
│ │  	strb	r7, [r2, #11]
│ │ -	vshr.u16	q15, <illegal reg q14.5>, #3
│ │ +	vaddl.u16	q15, d29, d20
│ │  	vsubl.u16	<illegal reg q11.5>, d31, d11
│ │  	vsubl.u16	<illegal reg q11.5>, d13, d27
│ │ -			@ <UNDEFINED> instruction: 0xffdddfd1
│ │ +			@ <UNDEFINED> instruction: 0xffdddff8
│ │  	vsra.u64	<illegal reg q11.5>, <illegal reg q11.5>, #33
│ │  	vaddl.u16	<illegal reg q8.5>, d13, d12
│ │  	b.n	2a4138 <uniffi_pbcli_checksum_method_api_base@@Base+0x1378b4>
│ │  	movs	r0, r1
│ │  	b.n	2a4d3e <uniffi_pbcli_checksum_method_api_base@@Base+0x1384ba>
│ │  	movs	r4, #173	@ 0xad
│ │  	b.n	2a4c02 <uniffi_pbcli_checksum_method_api_base@@Base+0x13837e>
│ │ @@ -581768,15 +581768,15 @@
│ │  	asrs	r4, r1, #32
│ │  	b.n	2a4528 <uniffi_pbcli_checksum_method_api_base@@Base+0x137ca4>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2a4b0c <uniffi_pbcli_checksum_method_api_base@@Base+0x138288>
│ │  	lsls	r0, r0, #6
│ │  	b.n	2a4914 <uniffi_pbcli_checksum_method_api_base@@Base+0x138090>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r4, r6, r7, r8, r9, ip}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, ip}
│ │  	vrsra.u16	d18, d24, #1
│ │  	movs	r0, r4
│ │  	str	r5, [r5, r6]
│ │  	vaddl.u16	q8, d13, d0
│ │  	b.n	2a50a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x138822>
│ │  	movs	r7, r0
│ │  	lsrs	r0, r0, #8
│ │ @@ -581882,17 +581882,17 @@
│ │  	b.n	2a4e26 <uniffi_pbcli_checksum_method_api_base@@Base+0x1385a2>
│ │  	asrs	r5, r0, #32
│ │  	b.n	2a4e2a <uniffi_pbcli_checksum_method_api_base@@Base+0x1385a6>
│ │  	subs	r0, r3, r4
│ │  	add.w	r0, r0, r1
│ │  	b.n	2a5232 <uniffi_pbcli_checksum_method_api_base@@Base+0x1389ae>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r6, pc}
│ │ -	vabdl.u16	q9, d15, d2
│ │ -	vmlal.u16	<illegal reg q8.5>, d31, d5[2]
│ │ +	ldmia.w	sp!, {r2, r3, r4, r7, pc}
│ │ +	vabdl.u16	q9, d15, d25
│ │ +	vsubw.u16	<illegal reg q8.5>, <illegal reg q7.5>, d12
│ │  	vmlal.u16	q9, d15, d4[2]
│ │  	movs	r0, r4
│ │  	ldr	r4, [pc, #64]	@ (2a4b48 <uniffi_pbcli_checksum_method_api_base@@Base+0x1382c4>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2a5028 <uniffi_pbcli_checksum_method_api_base@@Base+0x1387a4>
│ │  	movs	r0, r0
│ │  	b.n	2a51b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x13892e>
│ │ @@ -582628,31 +582628,31 @@
│ │  			@ <UNDEFINED> instruction: 0xffde9be1
│ │  			@ <UNDEFINED> instruction: 0xffde9bf4
│ │  	vrsra.u64	d17, d25, #34
│ │  			@ <UNDEFINED> instruction: 0xffde9d14
│ │  	vsubw.u16	<illegal reg q8.5>, <illegal reg q14.5>, d10
│ │  	vsli.16	<illegal reg q15.5>, q12, #14
│ │  	vmlal.u16	<illegal reg q15.5>, d14, d24
│ │ -	vmul.i16	<illegal reg q9.5>, q15, d6[3]
│ │ +	vqshrn.u32	d19, <illegal reg q2.5>, #2
│ │  	vmls.i16	<illegal reg q15.5>, <illegal reg q15.5>, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffdef768
│ │ -	vmlal.u16	<illegal reg q9.5>, d14, d18
│ │ -	vmlal.u16	q13, d31, d3
│ │ -	vmul.i16	q13, <illegal reg q7.5>, d7[1]
│ │ +	vmul.i16	<illegal reg q9.5>, q7, d1[1]
│ │ +	vmlal.u16	q13, d31, d26
│ │ +	vqrshrun.s32	d26, q11, #1
│ │  	vaddl.u16	<illegal reg q10.5>, d31, d26
│ │  	vaddl.u16	<illegal reg q10.5>, d29, d6
│ │ -	vrshr.u16	q9, q2, #3
│ │ -	vmla.f16	q9, <illegal reg q15.5>, d0[3]
│ │ +	vrshr.u16	q9, <illegal reg q13.5>, #3
│ │ +	vsubl.u16	q9, d15, d15
│ │  	vmul.i16	q9, <illegal reg q7.5>, d3[1]
│ │  	vqshrun.s32	d18, <illegal reg q3.5>, #2
│ │  	vmls.i16	<illegal reg q12.5>, q15, d2[2]
│ │  	vrsra.u64	<illegal reg q12.5>, q9, #34
│ │  	vmlal.u16	<illegal reg q12.5>, d14, d13
│ │  	vmul.f16	<illegal reg q12.5>, q7, d0[3]
│ │ -	vqshlu.s16	d19, d28, #13
│ │ +	vmlsl.u16	<illegal reg q9.5>, d13, d3[2]
│ │  			@ <UNDEFINED> instruction: 0xffdf98b5
│ │  	vmul.i16	<illegal reg q12.5>, q15, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffde4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2a5700 <uniffi_pbcli_checksum_method_api_base@@Base+0x138e7c>
│ │  	str	r1, [r0, #0]
│ │  	b.n	2a552a <uniffi_pbcli_checksum_method_api_base@@Base+0x138ca6>
│ │ @@ -582908,16 +582908,16 @@
│ │  	add.w	r0, r0, r0
│ │  	b.n	2a5ace <uniffi_pbcli_checksum_method_api_base@@Base+0x13924a>
│ │  			@ <UNDEFINED> instruction: 0xffc31aff
│ │  			@ <UNDEFINED> instruction: 0xffcceaff
│ │  	add	r0, pc, #0	@ (adr r0, 2a5438 <uniffi_pbcli_checksum_method_api_base@@Base+0x138bb4>)
│ │  	b.n	2a5b7a <uniffi_pbcli_checksum_method_api_base@@Base+0x1392f6>
│ │  			@ <UNDEFINED> instruction: 0xffcaeaff
│ │ -	lsrs	r6, r2, #4
│ │ -	vrshr.u16	<illegal reg q14.5>, q9, #1
│ │ +	lsrs	r5, r7, #4
│ │ +	vrshr.u64	d29, d9, #33
│ │  	vsli.64	d25, d17, #31
│ │  			@ <UNDEFINED> instruction: 0xffde4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2a596c <uniffi_pbcli_checksum_method_api_base@@Base+0x1390e8>
│ │  	movs	r0, r0
│ │  	b.n	2a5af6 <uniffi_pbcli_checksum_method_api_base@@Base+0x139272>
│ │  	movs	r4, r2
│ │ @@ -583230,21 +583230,21 @@
│ │  	beq.n	2a572c <uniffi_pbcli_checksum_method_api_base@@Base+0x138ea8>
│ │  	b.n	2a5ba4 <uniffi_pbcli_checksum_method_api_base@@Base+0x139320>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r2, r8, r9, fp, ip, lr, pc}
│ │  	vsubw.u16	<illegal reg q10.5>, q7, d0
│ │  	vshr.u64	d19, d28, #34
│ │  	vmull.u16	<illegal reg q14.5>, d13, d0[0]
│ │ -	vsri.16	<illegal reg q11.5>, <illegal reg q6.5>, #2
│ │ -	vmull.u16	<illegal reg q8.5>, d31, d2[3]
│ │ -	vmlsl.u16	q8, d31, d5[1]
│ │ +	vraddhn.i32	d23, q15, q2
│ │ +			@ <UNDEFINED> instruction: 0xffdf1b11
│ │ +	vqshlu.s64	q8, q10, #31
│ │  	vmlsl.u16	<illegal reg q8.5>, d15, d4[1]
│ │  	movs	r0, r4
│ │  	str	r3, [sp, #4]
│ │ -			@ <UNDEFINED> instruction: 0xffdee740
│ │ +			@ <UNDEFINED> instruction: 0xffdee767
│ │  			@ <UNDEFINED> instruction: 0xffdf4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2a5c5c <uniffi_pbcli_checksum_method_api_base@@Base+0x1393d8>
│ │  	movs	r0, #4
│ │  	b.n	2a5266 <uniffi_pbcli_checksum_method_api_base@@Base+0x1389e2>
│ │  	asrs	r0, r0, #32
│ │  	b.n	2a5a8a <uniffi_pbcli_checksum_method_api_base@@Base+0x139206>
│ │ @@ -583579,15 +583579,15 @@
│ │  	movs	r0, r0
│ │  	b.n	2a552e <uniffi_pbcli_checksum_method_api_base@@Base+0x138caa>
│ │  	movs	r5, r0
│ │  	b.n	2a5d6a <uniffi_pbcli_checksum_method_api_base@@Base+0x1394e6>
│ │  	beq.n	2a5a3c <uniffi_pbcli_checksum_method_api_base@@Base+0x1391b8>
│ │  	b.n	2a5ec4 <uniffi_pbcli_checksum_method_api_base@@Base+0x139640>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r3, r4, r7, r8, r9}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r7, r8, r9}
│ │  	vsra.u16	q10, <illegal reg q10.5>, #1
│ │  	vsubw.u16	<illegal reg q8.5>, <illegal reg q6.5>, d12
│ │  	movs	r0, r4
│ │  	ldr	r0, [pc, #192]	@ (2a5b00 <uniffi_pbcli_checksum_method_api_base@@Base+0x13927c>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2a5f60 <uniffi_pbcli_checksum_method_api_base@@Base+0x1396dc>
│ │  	beq.n	2a5a58 <uniffi_pbcli_checksum_method_api_base@@Base+0x1391d4>
│ │ @@ -583965,19 +583965,19 @@
│ │  	b.n	2a64ca <uniffi_pbcli_checksum_method_api_base@@Base+0x139c46>
│ │  	movs	r4, r0
│ │  	b.n	2a60ce <uniffi_pbcli_checksum_method_api_base@@Base+0x13984a>
│ │  	beq.n	2a5db0 <uniffi_pbcli_checksum_method_api_base@@Base+0x13952c>
│ │  	b.n	2a6228 <uniffi_pbcli_checksum_method_api_base@@Base+0x1399a4>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r3, r5, r7, sl, fp, pc}
│ │ -	vmlsl.u16	<illegal reg q10.5>, d14, d5[2]
│ │ +	vrsubhn.i32	d21, q15, q6
│ │  			@ <UNDEFINED> instruction: 0xffdf8bf1
│ │ -	vabal.u16	<illegal reg q10.5>, d30, d29
│ │ +	vsli.64	<illegal reg q10.5>, q2, #30
│ │  	vmull.u16	q12, d15, d21
│ │ -	vmls.f16	<illegal reg q10.5>, q15, d1[2]
│ │ +	vrsubhn.i32	d21, q7, q4
│ │  			@ <UNDEFINED> instruction: 0xffdf4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2a62d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x139a4c>
│ │  	beq.n	2a5de8 <uniffi_pbcli_checksum_method_api_base@@Base+0x139564>
│ │  	b.n	2a6254 <uniffi_pbcli_checksum_method_api_base@@Base+0x1399d0>
│ │  	str	r2, [r0, r0]
│ │  	b.n	2a60fe <uniffi_pbcli_checksum_method_api_base@@Base+0x13987a>
│ │ @@ -584159,17 +584159,17 @@
│ │  	b.n	2a668a <uniffi_pbcli_checksum_method_api_base@@Base+0x139e06>
│ │  	movs	r0, #0
│ │  	b.n	2a668e <uniffi_pbcli_checksum_method_api_base@@Base+0x139e0a>
│ │  	stmia	r4!, {r0, r3, r6}
│ │  	add.w	r0, r0, r4
│ │  	b.n	2a6296 <uniffi_pbcli_checksum_method_api_base@@Base+0x139a12>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, ip, sp, pc}
│ │  	vaddl.u16	q10, d31, d17
│ │ -	vqrdmlsh.s16	q13, <illegal reg q14.5>, d2[1]
│ │ +			@ <UNDEFINED> instruction: 0xffddaff1
│ │  	vshr.u16	q10, <illegal reg q10.5>, #1
│ │  			@ <UNDEFINED> instruction: 0xffdd4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2a648c <uniffi_pbcli_checksum_method_api_base@@Base+0x139c08>
│ │  	beq.n	2a5f84 <uniffi_pbcli_checksum_method_api_base@@Base+0x139700>
│ │  	b.n	2a6410 <uniffi_pbcli_checksum_method_api_base@@Base+0x139b8c>
│ │  	movs	r0, r0
│ │ @@ -584376,18 +584376,18 @@
│ │  	b.n	2a67de <uniffi_pbcli_checksum_method_api_base@@Base+0x139f5a>
│ │  			@ <UNDEFINED> instruction: 0xffe41aff
│ │  	str	r2, [r7, #4]
│ │  	b.n	2a6886 <uniffi_pbcli_checksum_method_api_base@@Base+0x13a002>
│ │  	eors	r3, r5
│ │  	b.n	2a688a <uniffi_pbcli_checksum_method_api_base@@Base+0x13a006>
│ │  			@ <UNDEFINED> instruction: 0xffd5eaff
│ │ -	add	r7, sp, #392	@ 0x188
│ │ -			@ <UNDEFINED> instruction: 0xffdf6bb2
│ │ -	vqrdmlah.s16	q13, <illegal reg q7.5>, d6[0]
│ │ -			@ <UNDEFINED> instruction: 0xffdf6a96
│ │ +	add	r7, sp, #548	@ 0x224
│ │ +			@ <UNDEFINED> instruction: 0xffdf6bd9
│ │ +	vqrdmlah.s16	q13, <illegal reg q7.5>, d5[3]
│ │ +			@ <UNDEFINED> instruction: 0xffdf6abd
│ │  			@ <UNDEFINED> instruction: 0xffdf4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2a6680 <uniffi_pbcli_checksum_method_api_base@@Base+0x139dfc>
│ │  	beq.n	2a61e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x13995c>
│ │  	b.n	2a6604 <uniffi_pbcli_checksum_method_api_base@@Base+0x139d80>
│ │  	ands	r2, r0
│ │  	b.n	2a64ae <uniffi_pbcli_checksum_method_api_base@@Base+0x139c2a>
│ │ @@ -585254,17 +585254,17 @@
│ │  	lsrs	r5, r1, #19
│ │  	b.n	2a6eb6 <uniffi_pbcli_checksum_method_api_base@@Base+0x13a632>
│ │  	movs	r4, r4
│ │  	b.n	2a63d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x139b50>
│ │  			@ <UNDEFINED> instruction: 0xffc1eaff
│ │  	lsrs	r4, r3, #15
│ │  	movs	r0, r4
│ │ -	ldrh	r5, [r3, #58]	@ 0x3a
│ │ +	ldrh	r4, [r0, #60]	@ 0x3c
│ │  			@ <UNDEFINED> instruction: 0xffdf57c5
│ │ -	vabal.u16	<illegal reg q12.5>, d30, d1
│ │ +	vabal.u16	<illegal reg q12.5>, d30, d24
│ │  	vqshlu.s16	d21, d16, #15
│ │  	vrshr.u64	d24, d19, #35
│ │  	vaddl.u16	q9, d14, d0
│ │  	b.n	2a6c1a <uniffi_pbcli_checksum_method_api_base@@Base+0x13a396>
│ │  	movs	r0, r0
│ │  	b.n	2a701e <uniffi_pbcli_checksum_method_api_base@@Base+0x13a79a>
│ │  	asrs	r0, r0, #32
│ │ @@ -585663,18 +585663,18 @@
│ │  	b.n	2a6f8a <uniffi_pbcli_checksum_method_api_base@@Base+0x13a706>
│ │  	strb	r6, [r7, #15]
│ │  			@ <UNDEFINED> instruction: 0xebff0020
│ │  	b.n	2a6688 <uniffi_pbcli_checksum_method_api_base@@Base+0x139e04>
│ │  	beq.n	2a6c8c <uniffi_pbcli_checksum_method_api_base@@Base+0x13a408>
│ │  	b.n	2a70ec <uniffi_pbcli_checksum_method_api_base@@Base+0x13a868>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r3, r5, r7, r8, sl, fp, pc}
│ │ +	ldmia.w	sp!, {r4, r6, r7, r8, sl, fp, pc}
│ │  	vsubl.u16	q8, d15, d28
│ │  	movs	r0, r4
│ │ -	ldrh	r5, [r6, #22]
│ │ +	ldrh	r4, [r3, #24]
│ │  			@ <UNDEFINED> instruction: 0xffdf4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2a7188 <uniffi_pbcli_checksum_method_api_base@@Base+0x13a904>
│ │  	beq.n	2a6c80 <uniffi_pbcli_checksum_method_api_base@@Base+0x13a3fc>
│ │  	b.n	2a710c <uniffi_pbcli_checksum_method_api_base@@Base+0x13a888>
│ │  	strb	r3, [r0, #0]
│ │  	b.n	2a6fb6 <uniffi_pbcli_checksum_method_api_base@@Base+0x13a732>
│ │ @@ -586093,16 +586093,16 @@
│ │  	b.n	2a7762 <uniffi_pbcli_checksum_method_api_base@@Base+0x13aede>
│ │  	ands	r0, r0
│ │  	b.n	2a7766 <uniffi_pbcli_checksum_method_api_base@@Base+0x13aee2>
│ │  	stmia	r0!, {r0, r1, r4}
│ │  	add.w	r0, r0, r4
│ │  	b.n	2a736e <uniffi_pbcli_checksum_method_api_base@@Base+0x13aaea>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r2, r5, r6, r8, r9, sl, pc}
│ │ -	vsra.u64	q8, <illegal reg q6.5>, #33
│ │ +	ldmia.w	sp!, {r2, r3, r7, r8, r9, sl, pc}
│ │ +	vsubl.u16	q8, d15, d4
│ │  			@ <UNDEFINED> instruction: 0xffdf4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2a755c <uniffi_pbcli_checksum_method_api_base@@Base+0x13acd8>
│ │  	ands	r3, r0
│ │  	b.n	2a7386 <uniffi_pbcli_checksum_method_api_base@@Base+0x13ab02>
│ │  	str	r2, [r0, #0]
│ │  	b.n	2a738a <uniffi_pbcli_checksum_method_api_base@@Base+0x13ab06>
│ │ @@ -586250,15 +586250,15 @@
│ │  	strb	r7, [r5, #10]
│ │  			@ <UNDEFINED> instruction: 0xebff0006
│ │  	b.n	2a74ce <uniffi_pbcli_checksum_method_api_base@@Base+0x13ac4a>
│ │  	strb	r5, [r6, #7]
│ │  			@ <UNDEFINED> instruction: 0xebff0008
│ │  	b.n	2a74d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x13ac52>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r3, r4, r9, sl, pc}
│ │ +	ldmia.w	sp!, {r6, r9, sl, pc}
│ │  	vqshlu.s64	q10, q2, #31
│ │  			@ <UNDEFINED> instruction: 0xffdd4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2a76c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x13ae40>
│ │  	ands	r0, r0
│ │  	b.n	2a74ee <uniffi_pbcli_checksum_method_api_base@@Base+0x13ac6a>
│ │  	strh	r1, [r4, #10]
│ │ @@ -586489,16 +586489,16 @@
│ │  	b.n	2a6ec6 <uniffi_pbcli_checksum_method_api_base@@Base+0x13a642>
│ │  	movs	r5, r0
│ │  	b.n	2a7702 <uniffi_pbcli_checksum_method_api_base@@Base+0x13ae7e>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {}
│ │  	b.n	2a7b0a <uniffi_pbcli_checksum_method_api_base@@Base+0x13b286>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r3, r4, r6, sl, pc}
│ │ -	vmul.i16	<illegal reg q10.5>, <illegal reg q7.5>, d5[3]
│ │ +	ldmia.w	sp!, {r7, sl, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffdf5894
│ │  			@ <UNDEFINED> instruction: 0xffdf48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2a78f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x13b074>
│ │  	ands	r3, r0
│ │  	b.n	2a7722 <uniffi_pbcli_checksum_method_api_base@@Base+0x13ae9e>
│ │  	str	r2, [r0, #0]
│ │  	b.n	2a7726 <uniffi_pbcli_checksum_method_api_base@@Base+0x13aea2>
│ │ @@ -586607,18 +586607,18 @@
│ │  	strh	r3, [r1, #36]	@ 0x24
│ │  			@ <UNDEFINED> instruction: 0xebff0006
│ │  	b.n	2a7812 <uniffi_pbcli_checksum_method_api_base@@Base+0x13af8e>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	2a7c1a <uniffi_pbcli_checksum_method_api_base@@Base+0x13b396>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r5, r6, r8, r9, pc}
│ │ -	vaddw.u16	<illegal reg q13.5>, <illegal reg q15.5>, d22
│ │ -	vsubw.u16	q12, <illegal reg q7.5>, d17
│ │ -	vsra.u16	<illegal reg q13.5>, q7, #1
│ │ +	ldmia.w	sp!, {r4, r7, r8, r9, pc}
│ │ +	vmla.f16	<illegal reg q13.5>, <illegal reg q15.5>, d5[1]
│ │ +			@ <UNDEFINED> instruction: 0xffdf8348
│ │ +	vaddw.u16	<illegal reg q13.5>, <illegal reg q15.5>, d5
│ │  			@ <UNDEFINED> instruction: 0xffdf4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2a7a10 <uniffi_pbcli_checksum_method_api_base@@Base+0x13b18c>
│ │  	beq.n	2a7550 <uniffi_pbcli_checksum_method_api_base@@Base+0x13accc>
│ │  	b.n	2a7994 <uniffi_pbcli_checksum_method_api_base@@Base+0x13b110>
│ │  	strb	r1, [r0, #0]
│ │  	b.n	2a783e <uniffi_pbcli_checksum_method_api_base@@Base+0x13afba>
│ │ @@ -587933,15 +587933,15 @@
│ │  	b.n	2a839e <uniffi_pbcli_checksum_method_api_base@@Base+0x13bb1a>
│ │  	asrs	r7, r7, #2
│ │  	add.w	r0, r0, r4
│ │  	b.n	2a83a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x13bb22>
│ │  	beq.n	2a80a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x13b81c>
│ │  	b.n	2a8500 <uniffi_pbcli_checksum_method_api_base@@Base+0x13bc7c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r6, r8, r9, sl, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r3, r5, r6, r8, r9, sl, ip, sp, lr}
│ │  	vsli.64	q14, <illegal reg q7.5>, #31
│ │  			@ <UNDEFINED> instruction: 0xffde4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2a8598 <uniffi_pbcli_checksum_method_api_base@@Base+0x13bd14>
│ │  	ands	r2, r0
│ │  	b.n	2a83c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x13bb3e>
│ │  	movs	r0, #40	@ 0x28
│ │ @@ -587978,15 +587978,15 @@
│ │  	b.n	2a880a <uniffi_pbcli_checksum_method_api_base@@Base+0x13bf86>
│ │  	movs	r0, #0
│ │  	b.n	2a880e <uniffi_pbcli_checksum_method_api_base@@Base+0x13bf8a>
│ │  	cbnz	r1, 2a814a <uniffi_pbcli_checksum_method_api_base@@Base+0x13b8c6>
│ │  	add.w	r0, r0, r4
│ │  	b.n	2a8416 <uniffi_pbcli_checksum_method_api_base@@Base+0x13bb92>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r7, r9, sl, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r5, r6, r7, r9, sl, ip, sp, lr}
│ │  	vqshlu.s64	<illegal reg q12.5>, q9, #31
│ │  			@ <UNDEFINED> instruction: 0xffde4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2a8604 <uniffi_pbcli_checksum_method_api_base@@Base+0x13bd80>
│ │  	beq.n	2a8104 <uniffi_pbcli_checksum_method_api_base@@Base+0x13b880>
│ │  	b.n	2a8588 <uniffi_pbcli_checksum_method_api_base@@Base+0x13bd04>
│ │  	str	r0, [r0, #0]
│ │ @@ -588251,18 +588251,18 @@
│ │  	movs	r0, #20
│ │  	b.n	2a7e68 <uniffi_pbcli_checksum_method_api_base@@Base+0x13b5e4>
│ │  	movs	r0, r0
│ │  	b.n	2a844c <uniffi_pbcli_checksum_method_api_base@@Base+0x13bbc8>
│ │  	movs	r0, #2
│ │  	b.n	2a8450 <uniffi_pbcli_checksum_method_api_base@@Base+0x13bbcc>
│ │  			@ <UNDEFINED> instruction: 0xffeeeaff
│ │ -	strb	r5, [r0, #18]
│ │ -	vmul.i16	q10, <illegal reg q15.5>, d2[1]
│ │ -	vmls.i16	<illegal reg q11.5>, <illegal reg q7.5>, d5[0]
│ │ -	vmlal.u16	q10, d31, d10
│ │ +	strb	r4, [r5, #18]
│ │ +			@ <UNDEFINED> instruction: 0xffdf48f1
│ │ +	vmls.i16	<illegal reg q11.5>, <illegal reg q7.5>, d4[3]
│ │ +			@ <UNDEFINED> instruction: 0xffdf48b1
│ │  			@ <UNDEFINED> instruction: 0xffdf4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2a8868 <uniffi_pbcli_checksum_method_api_base@@Base+0x13bfe4>
│ │  	beq.n	2a8358 <uniffi_pbcli_checksum_method_api_base@@Base+0x13bad4>
│ │  	b.n	2a87ec <uniffi_pbcli_checksum_method_api_base@@Base+0x13bf68>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	2a8696 <uniffi_pbcli_checksum_method_api_base@@Base+0x13be12>
│ │ @@ -588995,17 +588995,17 @@
│ │  	b.n	2a8cb6 <uniffi_pbcli_checksum_method_api_base@@Base+0x13c432>
│ │  	ldr	r3, [r6, #72]	@ 0x48
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	2a8cbe <uniffi_pbcli_checksum_method_api_base@@Base+0x13c43a>
│ │  	beq.n	2a89b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x13c134>
│ │  	b.n	2a8e18 <uniffi_pbcli_checksum_method_api_base@@Base+0x13c594>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r6, r8, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r7, r8, ip, sp, lr}
│ │  	vsri.64	q11, <illegal reg q3.5>, #33
│ │ -			@ <UNDEFINED> instruction: 0xffdd6e35
│ │ +			@ <UNDEFINED> instruction: 0xffdd6e5c
│ │  	vsra.u64	d22, d7, #33
│ │  			@ <UNDEFINED> instruction: 0xffdd4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2a8eb8 <uniffi_pbcli_checksum_method_api_base@@Base+0x13c634>
│ │  	strh	r0, [r0, #0]
│ │  	b.n	2a8ce2 <uniffi_pbcli_checksum_method_api_base@@Base+0x13c45e>
│ │  	str	r2, [r0, r0]
│ │ @@ -589524,15 +589524,15 @@
│ │  	b.n	2a9532 <uniffi_pbcli_checksum_method_api_base@@Base+0x13ccae>
│ │  			@ <UNDEFINED> instruction: 0xb8a0
│ │  	add.w	r0, r0, r4
│ │  	b.n	2a913a <uniffi_pbcli_checksum_method_api_base@@Base+0x13c8b6>
│ │  	beq.n	2a8e2c <uniffi_pbcli_checksum_method_api_base@@Base+0x13c5a8>
│ │  	b.n	2a9294 <uniffi_pbcli_checksum_method_api_base@@Base+0x13ca10>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r5, r7, r8, fp, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r2, r4, r6, r7, r8, fp, sp, lr}
│ │  	vrshr.u16	<illegal reg q8.5>, <illegal reg q7.5>, #1
│ │  			@ <UNDEFINED> instruction: 0xffdd4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2a932c <uniffi_pbcli_checksum_method_api_base@@Base+0x13caa8>
│ │  	str	r2, [r0, r0]
│ │  	b.n	2a9156 <uniffi_pbcli_checksum_method_api_base@@Base+0x13c8d2>
│ │  	strh	r1, [r0, #0]
│ │ @@ -590465,18 +590465,18 @@
│ │  	b.n	2a91c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x13c944>
│ │  	movs	r2, r1
│ │  	b.n	2a99f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x13d16e>
│ │  	mcr2	11, 0, lr, cr12, cr15, {7}	@ <UNPREDICTABLE>
│ │  	str	r0, [r0, #0]
│ │  	b.n	2a99fa <uniffi_pbcli_checksum_method_api_base@@Base+0x13d176>
│ │  			@ <UNDEFINED> instruction: 0xffe5eaff
│ │ -	str	r2, [r7, #32]
│ │ -	vmla.f16	q11, <illegal reg q7.5>, d2[1]
│ │ +	str	r1, [r4, #36]	@ 0x24
│ │ +	vsra.u16	q11, <illegal reg q8.5>, #1
│ │  	vsra.u64	q15, q12, #33
│ │ -	vaddw.u16	q11, <illegal reg q6.5>, d18
│ │ +	vmla.f16	q11, <illegal reg q6.5>, d1[1]
│ │  			@ <UNDEFINED> instruction: 0xffdf4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2a9bf0 <uniffi_pbcli_checksum_method_api_base@@Base+0x13d36c>
│ │  	beq.n	2a97a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x13cf1c>
│ │  	b.n	2a9b74 <uniffi_pbcli_checksum_method_api_base@@Base+0x13d2f0>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	2a9a1e <uniffi_pbcli_checksum_method_api_base@@Base+0x13d19a>
│ │ @@ -592315,18 +592315,18 @@
│ │  			@ <UNDEFINED> instruction: 0xebff4000
│ │  	b.n	2aa9f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x13e16e>
│ │  	movs	r0, r0
│ │  	b.n	2aad56 <uniffi_pbcli_checksum_method_api_base@@Base+0x13e4d2>
│ │  	ands	r1, r0
│ │  	asrs	r0, r0, #12
│ │  	mrc2	10, 5, lr, cr10, cr15, {7}	@ <UNPREDICTABLE>
│ │ -	strh	r2, [r5, r0]
│ │ -			@ <UNDEFINED> instruction: 0xffdf3cf2
│ │ -	vmlal.u16	<illegal reg q10.5>, d31, d2[0]
│ │ -			@ <UNDEFINED> instruction: 0xffdf3d8a
│ │ +	strh	r1, [r2, r1]
│ │ +			@ <UNDEFINED> instruction: 0xffdf3d19
│ │ +	vmlal.u16	<illegal reg q10.5>, d31, d1[3]
│ │ +			@ <UNDEFINED> instruction: 0xffdf3db1
│ │  	vsri.64	<illegal reg q14.5>, q2, #33
│ │  	bmi.n	2aa67a <uniffi_pbcli_checksum_method_api_base@@Base+0x13ddf6>
│ │  	bmi.n	2aa67c <uniffi_pbcli_checksum_method_api_base@@Base+0x13ddf8>
│ │  	bmi.n	2aa67e <uniffi_pbcli_checksum_method_api_base@@Base+0x13ddfa>
│ │  	bmi.n	2aa680 <uniffi_pbcli_checksum_method_api_base@@Base+0x13ddfc>
│ │  	bmi.n	2aa682 <uniffi_pbcli_checksum_method_api_base@@Base+0x13ddfe>
│ │  	bmi.n	2aa684 <uniffi_pbcli_checksum_method_api_base@@Base+0x13de00>
│ │ @@ -594011,15 +594011,15 @@
│ │  	movs	r5, r0
│ │  	b.n	2ab956 <uniffi_pbcli_checksum_method_api_base@@Base+0x13f0d2>
│ │  	str	r3, [r2, #12]
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	2ab95e <uniffi_pbcli_checksum_method_api_base@@Base+0x13f0da>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r3, r8, r9, fp, sp, pc}
│ │ -	vmull.u16	q9, d29, d13
│ │ +			@ <UNDEFINED> instruction: 0xffdd2cb4
│ │  	vqshrun.s32	d20, q8, #1
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2abb4c <uniffi_pbcli_checksum_method_api_base@@Base+0x13f2c8>
│ │  	ands	r0, r0
│ │  	b.n	2ab976 <uniffi_pbcli_checksum_method_api_base@@Base+0x13f0f2>
│ │  	movs	r0, r0
│ │  	b.n	2ab15a <uniffi_pbcli_checksum_method_api_base@@Base+0x13e8d6>
│ │ @@ -594528,15 +594528,15 @@
│ │  	ands	r0, r0
│ │  	b.n	2ac1ee <uniffi_pbcli_checksum_method_api_base@@Base+0x13f96a>
│ │  	add	r5, sp, #452	@ 0x1c4
│ │  	add.w	r0, r0, r4
│ │  	b.n	2abdf6 <uniffi_pbcli_checksum_method_api_base@@Base+0x13f572>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r4, r6, r9, sl, sp, pc}
│ │ -	vqshl.u16	<illegal reg q13.5>, <illegal reg q12.5>, #13
│ │ +	vabdl.u16	<illegal reg q13.5>, d29, d16
│ │  	vqshrun.s32	d20, q8, #2
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2abfe4 <uniffi_pbcli_checksum_method_api_base@@Base+0x13f760>
│ │  	ands	r0, r0
│ │  	b.n	2abe0e <uniffi_pbcli_checksum_method_api_base@@Base+0x13f58a>
│ │  	movs	r4, r1
│ │  	b.n	2ab5f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x13ed6e>
│ │ @@ -594600,15 +594600,15 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	2ac292 <uniffi_pbcli_checksum_method_api_base@@Base+0x13fa0e>
│ │  	add	r5, sp, #288	@ 0x120
│ │  	add.w	r0, r0, r5
│ │  	b.n	2abe9a <uniffi_pbcli_checksum_method_api_base@@Base+0x13f616>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r4, r5, r7, r8, sl, sp, pc}
│ │ -	vsubl.u16	q13, d29, d1
│ │ +	vsubl.u16	q13, d29, d24
│ │  			@ <UNDEFINED> instruction: 0xffde4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2ac088 <uniffi_pbcli_checksum_method_api_base@@Base+0x13f804>
│ │  	str	r2, [r0, r0]
│ │  	b.n	2abeb2 <uniffi_pbcli_checksum_method_api_base@@Base+0x13f62e>
│ │  	movs	r0, #20
│ │  	b.n	2ab696 <uniffi_pbcli_checksum_method_api_base@@Base+0x13ee12>
│ │ @@ -594682,17 +594682,17 @@
│ │  	ands	r0, r0
│ │  	b.n	2ac34e <uniffi_pbcli_checksum_method_api_base@@Base+0x13faca>
│ │  	add	r5, sp, #100	@ 0x64
│ │  	add.w	r0, r0, r4
│ │  	b.n	2abf56 <uniffi_pbcli_checksum_method_api_base@@Base+0x13f6d2>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r2, r4, r5, r6, r7, sl, sp, pc}
│ │ -	vrshr.u16	d24, d7, #3
│ │ +	vrshr.u16	d24, d30, #3
│ │  	vsli.16	d26, d0, #15
│ │ -	vrshr.u16	d24, d19, #3
│ │ +	vrshr.u16	q12, q5, #3
│ │  			@ <UNDEFINED> instruction: 0xffdf4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2ac14c <uniffi_pbcli_checksum_method_api_base@@Base+0x13f8c8>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	2abf76 <uniffi_pbcli_checksum_method_api_base@@Base+0x13f6f2>
│ │  	movs	r4, r1
│ │  	b.n	2ab75a <uniffi_pbcli_checksum_method_api_base@@Base+0x13eed6>
│ │ @@ -595351,21 +595351,21 @@
│ │  	b.n	2ac946 <uniffi_pbcli_checksum_method_api_base@@Base+0x1400c2>
│ │  	stmia	r3!, {r4, r5}
│ │  	add.w	r0, r1, r0, lsl #16
│ │  	b.n	2ac94e <uniffi_pbcli_checksum_method_api_base@@Base+0x1400ca>
│ │  	movs	r4, r0
│ │  	b.n	2ac552 <uniffi_pbcli_checksum_method_api_base@@Base+0x13fcce>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r5, r7, sl, fp, ip, sp, lr}
│ │ -	vmls.i16	q11, <illegal reg q7.5>, d3[2]
│ │ -			@ <UNDEFINED> instruction: 0xffdf7c7f
│ │ -	vsri.16	d22, d23, #1
│ │ -			@ <UNDEFINED> instruction: 0xffdf7d57
│ │ -			@ <UNDEFINED> instruction: 0xffdf7d2b
│ │ -			@ <UNDEFINED> instruction: 0xffdf7c37
│ │ +	ldmia.w	sp!, {r1, r4, r6, r7, sl, fp, ip, sp, lr}
│ │ +	vraddhn.i32	d22, <illegal reg q15.5>, q5
│ │ +	vmull.u16	<illegal reg q11.5>, d31, d22
│ │ +	vsri.16	q11, q7, #1
│ │ +			@ <UNDEFINED> instruction: 0xffdf7d7e
│ │ +			@ <UNDEFINED> instruction: 0xffdf7d52
│ │ +			@ <UNDEFINED> instruction: 0xffdf7c5e
│ │  			@ <UNDEFINED> instruction: 0xffdf4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2ac754 <uniffi_pbcli_checksum_method_api_base@@Base+0x13fed0>
│ │  	ands	r0, r0
│ │  	b.n	2ac57e <uniffi_pbcli_checksum_method_api_base@@Base+0x13fcfa>
│ │  	lsls	r0, r4, #1
│ │  	b.n	2abd62 <uniffi_pbcli_checksum_method_api_base@@Base+0x13f4de>
│ │ @@ -595486,16 +595486,16 @@
│ │  	b.n	2ac68a <uniffi_pbcli_checksum_method_api_base@@Base+0x13fe06>
│ │  	asrs	r5, r0, #32
│ │  	b.n	2ac68e <uniffi_pbcli_checksum_method_api_base@@Base+0x13fe0a>
│ │  	movs	r0, #137	@ 0x89
│ │  	b.n	2aca92 <uniffi_pbcli_checksum_method_api_base@@Base+0x14020e>
│ │  	ldr	r0, [pc, #192]	@ (2ac414 <uniffi_pbcli_checksum_method_api_base@@Base+0x13fb90>)
│ │  	ldmia.w	sp!, {r2, r3, r4, r6, r7, r9, lr, pc}
│ │ -	and.w	fp, r1, pc, lsr #28
│ │ -			@ <UNDEFINED> instruction: 0xffdf7afb
│ │ +	and.w	fp, r1, r6, lsl #29
│ │ +			@ <UNDEFINED> instruction: 0xffdf7b22
│ │  	vaddl.u16	q8, d15, d0
│ │  	b.n	2aca06 <uniffi_pbcli_checksum_method_api_base@@Base+0x140182>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (2ac3ac <uniffi_pbcli_checksum_method_api_base@@Base+0x13fb28>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2ac88c <uniffi_pbcli_checksum_method_api_base@@Base+0x140008>
│ │  	ands	r0, r0
│ │ @@ -595517,15 +595517,15 @@
│ │  	b.n	2ac6d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x13fe52>
│ │  	movs	r2, #242	@ 0xf2
│ │  	b.n	2ac99a <uniffi_pbcli_checksum_method_api_base@@Base+0x140116>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2ac4bc <uniffi_pbcli_checksum_method_api_base@@Base+0x13fc38>
│ │  	ldr	r4, [pc, #64]	@ (2ac3e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x13fb5c>)
│ │  	ldmia.w	sp!, {r0, r3, r6, r7, r9, lr, pc}
│ │ -	and.w	sl, r1, fp, lsl #30
│ │ +	and.w	sl, r1, r2, ror #30
│ │  	vaddl.u16	q8, d15, d0
│ │  	b.n	2aca4e <uniffi_pbcli_checksum_method_api_base@@Base+0x1401ca>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (2ac3f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x13fb70>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2ac8d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x140050>
│ │  	ands	r0, r0
│ │ @@ -595553,15 +595553,15 @@
│ │  	b.n	2acb2a <uniffi_pbcli_checksum_method_api_base@@Base+0x1402a6>
│ │  	adds	r2, #255	@ 0xff
│ │  	b.n	2ac9ee <uniffi_pbcli_checksum_method_api_base@@Base+0x14016a>
│ │  	movs	r0, #2
│ │  	b.n	2ac510 <uniffi_pbcli_checksum_method_api_base@@Base+0x13fc8c>
│ │  	ldr	r4, [pc, #64]	@ (2ac434 <uniffi_pbcli_checksum_method_api_base@@Base+0x13fbb0>)
│ │  	ldmia.w	sp!, {r4, r6, r8, r9, lr, pc}
│ │ -	and.w	sl, r1, r7, ror #28
│ │ +	and.w	sl, r1, lr, lsr #29
│ │  			@ <UNDEFINED> instruction: 0xffdf4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2ac920 <uniffi_pbcli_checksum_method_api_base@@Base+0x14009c>
│ │  	str	r0, [r0, r0]
│ │  	b.n	2ac74a <uniffi_pbcli_checksum_method_api_base@@Base+0x13fec6>
│ │  	movs	r0, r0
│ │  	b.n	2abf2e <uniffi_pbcli_checksum_method_api_base@@Base+0x13f6aa>
│ │ @@ -595861,21 +595861,21 @@
│ │  	movs	r0, #20
│ │  	b.n	2ac1be <uniffi_pbcli_checksum_method_api_base@@Base+0x13f93a>
│ │  	movs	r5, r0
│ │  	b.n	2ac9e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x14015e>
│ │  	ldr	r4, [pc, #448]	@ (2ac864 <uniffi_pbcli_checksum_method_api_base@@Base+0x13ffe0>)
│ │  	ldmia.w	sp!, {r1, r4, r8, r9, sl, fp, ip, sp, lr, pc}
│ │  	b.n	2ac908 <uniffi_pbcli_checksum_method_api_base@@Base+0x140084>
│ │ -	ldrb	r7, [r7, #6]
│ │ +	ldrb	r6, [r4, #7]
│ │  	vqdmulh.s16	q11, <illegal reg q15.5>, d2[1]
│ │ -	vmul.f16	<illegal reg q11.5>, <illegal reg q14.5>, d3[3]
│ │ +	vshll.u16	<illegal reg q11.5>, d2, #13
│ │  			@ <UNDEFINED> instruction: 0xffdf6cf6
│ │ -	vmul.i16	<illegal reg q11.5>, <illegal reg q6.5>, d3[2]
│ │ -	vqshl.u64	<illegal reg q11.5>, <illegal reg q9.5>, #31
│ │ -	vabdl.u16	<illegal reg q11.5>, d31, d23
│ │ +	vmlal.u16	<illegal reg q11.5>, d29, d10
│ │ +	vqshrun.s32	d23, q5, #1
│ │ +			@ <UNDEFINED> instruction: 0xffdf77ce
│ │  	vqshrun.s32	d20, q8, #1
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2acbe8 <uniffi_pbcli_checksum_method_api_base@@Base+0x140364>
│ │  	movs	r0, r0
│ │  	b.n	2acd72 <uniffi_pbcli_checksum_method_api_base@@Base+0x1404ee>
│ │  	movs	r6, r2
│ │  	lsrs	r0, r0, #8
│ │ @@ -595976,20 +595976,20 @@
│ │  	b.n	2ac8c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x140044>
│ │  	stmia	r1!, {r0, r1, r2, r6, r7}
│ │  	add.w	r0, r1, r0, lsl #16
│ │  	b.n	2acef2 <uniffi_pbcli_checksum_method_api_base@@Base+0x14066e>
│ │  	movs	r4, r0
│ │  	b.n	2acaf6 <uniffi_pbcli_checksum_method_api_base@@Base+0x140272>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r5, r6, r7, r9, sl, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r3, r8, r9, sl, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffdf69fc
│ │ -	vqshlu.s64	d23, d23, #29
│ │ +	vqshlu.s64	<illegal reg q11.5>, q7, #29
│ │  			@ <UNDEFINED> instruction: 0xffdf69d0
│ │ -	vabdl.u16	<illegal reg q11.5>, d13, d31
│ │ -	vqshlu.s16	<illegal reg q11.5>, <illegal reg q15.5>, #15
│ │ +	vqshl.u16	<illegal reg q11.5>, q3, #13
│ │ +	vrsubhn.i32	d23, <illegal reg q15.5>, q11
│ │  			@ <UNDEFINED> instruction: 0xffdf4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2accf4 <uniffi_pbcli_checksum_method_api_base@@Base+0x140470>
│ │  	adds	r0, #0
│ │  	b.n	2ac2fe <uniffi_pbcli_checksum_method_api_base@@Base+0x13fa7a>
│ │  	movs	r0, #56	@ 0x38
│ │  	b.n	2ac308 <uniffi_pbcli_checksum_method_api_base@@Base+0x13fa84>
│ │ @@ -596068,17 +596068,17 @@
│ │  	add	r1, sp, #1012	@ 0x3f4
│ │  	add.w	r0, r0, r4
│ │  	b.n	2acbc6 <uniffi_pbcli_checksum_method_api_base@@Base+0x140342>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r0}
│ │  	b.n	2acfce <uniffi_pbcli_checksum_method_api_base@@Base+0x14074a>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r6, r7, r8, sl, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r5, r6, r7, r8, sl, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffdf4f7c
│ │ -	vsli.64	<illegal reg q11.5>, <illegal reg q9.5>, #30
│ │ +	vqshlu.s16	d23, d10, #14
│ │  			@ <UNDEFINED> instruction: 0xffdf4fa8
│ │  			@ <UNDEFINED> instruction: 0xffde4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2acdc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x140540>
│ │  	ands	r0, r0
│ │  	b.n	2acfee <uniffi_pbcli_checksum_method_api_base@@Base+0x14076a>
│ │  	movs	r0, r0
│ │ @@ -596362,22 +596362,22 @@
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	2ad26e <uniffi_pbcli_checksum_method_api_base@@Base+0x1409ea>
│ │  	lsls	r4, r3, #1
│ │  	b.n	2ac63a <uniffi_pbcli_checksum_method_api_base@@Base+0x13fdb6>
│ │  	movs	r1, r0
│ │  	b.n	2ad276 <uniffi_pbcli_checksum_method_api_base@@Base+0x1409f2>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r1, r5, r7, sl, ip, sp, lr}
│ │ -	vsri.64	d23, d18, #33
│ │ -	vmls.i16	<illegal reg q11.5>, <illegal reg q15.5>, d7[1]
│ │ -	vsri.64	<illegal reg q11.5>, q7, #33
│ │ -	vsri.16	d23, d15, #1
│ │ -	vraddhn.i32	d23, <illegal reg q7.5>, q15
│ │ -	vrsra.u64	<illegal reg q11.5>, <illegal reg q5.5>, #33
│ │ -			@ <UNDEFINED> instruction: 0xffdf73ea
│ │ +	ldmia.w	sp!, {r1, r3, r6, r7, sl, ip, sp, lr}
│ │ +	vsri.64	<illegal reg q11.5>, <illegal reg q4.5>, #33
│ │ +	vsri.64	<illegal reg q11.5>, q11, #33
│ │ +	vabal.u16	<illegal reg q11.5>, d15, d5
│ │ +	vmls.i16	<illegal reg q11.5>, <illegal reg q7.5>, d6[0]
│ │ +	vsri.16	<illegal reg q11.5>, <illegal reg q2.5>, #1
│ │ +	vraddhn.i32	d23, <illegal reg q7.5>, q1
│ │ +	vsri.16	d23, d1, #1
│ │  			@ <UNDEFINED> instruction: 0xffdf48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2ad07c <uniffi_pbcli_checksum_method_api_base@@Base+0x1407f8>
│ │  	beq.n	2acb74 <uniffi_pbcli_checksum_method_api_base@@Base+0x1402f0>
│ │  	b.n	2ad000 <uniffi_pbcli_checksum_method_api_base@@Base+0x14077c>
│ │  	str	r0, [r0, r0]
│ │  	b.n	2aceaa <uniffi_pbcli_checksum_method_api_base@@Base+0x140626>
│ │ @@ -596745,16 +596745,16 @@
│ │  	b.n	2ad1ea <uniffi_pbcli_checksum_method_api_base@@Base+0x140966>
│ │  	ands	r4, r4
│ │  	b.n	2ac9b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x140134>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {}
│ │  	b.n	2ad5f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x140d72>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r6, r7, r8, r9, sl, fp, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffdf6f9f
│ │ +	ldmia.w	sp!, {r1, ip, sp, lr}
│ │ +	vqrdmlsh.s16	q11, <illegal reg q15.5>, d6[0]
│ │  	vaddl.u16	q8, d15, d16
│ │  	b.n	2ac9e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x140162>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r4, r4
│ │  	b.n	2ac9ee <uniffi_pbcli_checksum_method_api_base@@Base+0x14016a>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r0, [pc, #0]	@ (2aced4 <uniffi_pbcli_checksum_method_api_base@@Base+0x140650>)
│ │ @@ -596795,15 +596795,15 @@
│ │  	b.n	2ad5a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x140d1e>
│ │  	movs	r0, #0
│ │  	b.n	2ad666 <uniffi_pbcli_checksum_method_api_base@@Base+0x140de2>
│ │  	add	r0, sp, #332	@ 0x14c
│ │  	add.w	r0, r0, r0
│ │  	b.n	2ad66e <uniffi_pbcli_checksum_method_api_base@@Base+0x140dea>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r8, r9, sl, fp, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r6, r8, r9, sl, fp, sp, lr}
│ │  	vmlsl.u16	<illegal reg q11.5>, d15, d5
│ │  	vmlal.u16	q10, d13, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2ad282 <uniffi_pbcli_checksum_method_api_base@@Base+0x1409fe>
│ │  	stmia	r0!, {}
│ │  	b.n	2aca66 <uniffi_pbcli_checksum_method_api_base@@Base+0x1401e2>
│ │  	stmia	r0!, {r2, r3, r4}
│ │ @@ -596839,16 +596839,16 @@
│ │  	b.n	2ad60a <uniffi_pbcli_checksum_method_api_base@@Base+0x140d86>
│ │  	movs	r0, #0
│ │  	b.n	2ad6ce <uniffi_pbcli_checksum_method_api_base@@Base+0x140e4a>
│ │  	add	r0, sp, #228	@ 0xe4
│ │  	add.w	r0, r0, r0
│ │  	b.n	2ad6d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x140e52>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r4, r5, r7, r9, sl, fp, sp, lr}
│ │ -	vrshr.u64	d26, d21, #33
│ │ +	ldmia.w	sp!, {r1, r3, r4, r6, r7, r9, sl, fp, sp, lr}
│ │ +	vrshr.u64	q13, q6, #33
│ │  	vmlal.u16	q10, d14, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2ad2ea <uniffi_pbcli_checksum_method_api_base@@Base+0x140a66>
│ │  	asrs	r0, r0, #32
│ │  	b.n	2acace <uniffi_pbcli_checksum_method_api_base@@Base+0x14024a>
│ │  	asrs	r0, r4, #32
│ │  	b.n	2acad4 <uniffi_pbcli_checksum_method_api_base@@Base+0x140250>
│ │ @@ -596879,16 +596879,16 @@
│ │  	b.n	2ad66a <uniffi_pbcli_checksum_method_api_base@@Base+0x140de6>
│ │  	movs	r0, #0
│ │  	b.n	2ad72e <uniffi_pbcli_checksum_method_api_base@@Base+0x140eaa>
│ │  	add	r0, sp, #132	@ 0x84
│ │  	add.w	r0, r0, r0
│ │  	b.n	2ad736 <uniffi_pbcli_checksum_method_api_base@@Base+0x140eb2>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r4, r6, r9, sl, fp, sp, lr}
│ │ -	vmlal.u16	q13, d15, d0[3]
│ │ +	ldmia.w	sp!, {r1, r3, r4, r5, r6, r9, sl, fp, sp, lr}
│ │ +	vsubl.u16	q13, d31, d15
│ │  	vmlal.u16	q10, d14, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2ad34a <uniffi_pbcli_checksum_method_api_base@@Base+0x140ac6>
│ │  	movs	r0, #0
│ │  	b.n	2acb2e <uniffi_pbcli_checksum_method_api_base@@Base+0x1402aa>
│ │  	movs	r0, #40	@ 0x28
│ │  	b.n	2acb36 <uniffi_pbcli_checksum_method_api_base@@Base+0x1402b2>
│ │ @@ -596919,15 +596919,15 @@
│ │  	b.n	2ad6ca <uniffi_pbcli_checksum_method_api_base@@Base+0x140e46>
│ │  	movs	r0, #0
│ │  	b.n	2ad78e <uniffi_pbcli_checksum_method_api_base@@Base+0x140f0a>
│ │  	add	r0, sp, #36	@ 0x24
│ │  	add.w	r0, r0, r0
│ │  	b.n	2ad796 <uniffi_pbcli_checksum_method_api_base@@Base+0x140f12>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r4, r5, r6, r7, r8, sl, fp, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r3, r4, r9, sl, fp, sp, lr}
│ │  	vshr.u16	q11, <illegal reg q6.5>, #1
│ │  			@ <UNDEFINED> instruction: 0xffde4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2ad584 <uniffi_pbcli_checksum_method_api_base@@Base+0x140d00>
│ │  	beq.n	2ad0b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x140830>
│ │  	b.n	2ad508 <uniffi_pbcli_checksum_method_api_base@@Base+0x140c84>
│ │  	strb	r1, [r0, #0]
│ │ @@ -597273,17 +597273,17 @@
│ │  	b.n	2adaa2 <uniffi_pbcli_checksum_method_api_base@@Base+0x14121e>
│ │  	movs	r0, #0
│ │  	b.n	2adaa6 <uniffi_pbcli_checksum_method_api_base@@Base+0x141222>
│ │  	add	r7, pc, #268	@ (adr r7, 2ad474 <uniffi_pbcli_checksum_method_api_base@@Base+0x140bf0>)
│ │  	add.w	r0, r0, r0
│ │  	b.n	2adb2e <uniffi_pbcli_checksum_method_api_base@@Base+0x1412aa>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r8, r9, fp, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r4, r5, r8, r9, fp, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffdf8df4
│ │ -			@ <UNDEFINED> instruction: 0xffdd6ad7
│ │ +			@ <UNDEFINED> instruction: 0xffdd6afe
│ │  			@ <UNDEFINED> instruction: 0xffdf8dbc
│ │  			@ <UNDEFINED> instruction: 0xffdd4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2ad8a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x141020>
│ │  	ands	r0, r0
│ │  	b.n	2adace <uniffi_pbcli_checksum_method_api_base@@Base+0x14124a>
│ │  	movs	r0, r0
│ │ @@ -597330,15 +597330,15 @@
│ │  	b.n	2ad9ea <uniffi_pbcli_checksum_method_api_base@@Base+0x141166>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2ad50c <uniffi_pbcli_checksum_method_api_base@@Base+0x140c88>
│ │  	bkpt	0x00b6
│ │  	add.w	r0, r1, r4
│ │  	b.n	2ad736 <uniffi_pbcli_checksum_method_api_base@@Base+0x140eb2>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r5, r9, fp, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r5, r6, r9, fp, sp, lr}
│ │  	vmlal.u16	q10, d15, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2ad746 <uniffi_pbcli_checksum_method_api_base@@Base+0x140ec2>
│ │  	adds	r0, #0
│ │  	b.n	2acf2a <uniffi_pbcli_checksum_method_api_base@@Base+0x1406a6>
│ │  	stmia	r0!, {r2, r3, r4, r5}
│ │  	b.n	2acf34 <uniffi_pbcli_checksum_method_api_base@@Base+0x1406b0>
│ │ @@ -597392,17 +597392,17 @@
│ │  	add	r6, pc, #1020	@ (adr r6, 2ad874 <uniffi_pbcli_checksum_method_api_base@@Base+0x140ff0>)
│ │  	add.w	r0, r0, r0
│ │  	b.n	2adbbe <uniffi_pbcli_checksum_method_api_base@@Base+0x14133a>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {fp, lr}
│ │  	ldmia.w	sp!, {r2, r3, r4, r8, r9, sl, fp, ip, sp, lr, pc}
│ │  	b.n	2ad6e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x140e64>
│ │ -	ldr	r3, [r1, #28]
│ │ +	ldr	r2, [r6, #28]
│ │  			@ <UNDEFINED> instruction: 0xffdf8c97
│ │ -			@ <UNDEFINED> instruction: 0xffdd69f3
│ │ +	vshll.u16	q11, d10, #13
│ │  			@ <UNDEFINED> instruction: 0xffdf8cbf
│ │  	vqshrun.s32	d20, q8, #3
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2ad9bc <uniffi_pbcli_checksum_method_api_base@@Base+0x141138>
│ │  	ands	r0, r0
│ │  	b.n	2acfc6 <uniffi_pbcli_checksum_method_api_base@@Base+0x140742>
│ │  	str	r6, [r2, r6]
│ │ @@ -597479,17 +597479,17 @@
│ │  			@ <UNDEFINED> instruction: 0xffde1aff
│ │  	b.n	2ad560 <uniffi_pbcli_checksum_method_api_base@@Base+0x140cdc>
│ │  	b.n	2ad060 <uniffi_pbcli_checksum_method_api_base@@Base+0x1407dc>
│ │  	stmia	r0!, {r3}
│ │  	b.n	2ad064 <uniffi_pbcli_checksum_method_api_base@@Base+0x1407e0>
│ │  	ldr	r0, [pc, #192]	@ (2ad610 <uniffi_pbcli_checksum_method_api_base@@Base+0x140d8c>)
│ │  	ldmia.w	sp!, {r1, r2, r5, r8, fp, ip, sp}
│ │ -	and.w	r9, r0, fp, asr #24
│ │ +	and.w	r9, r0, r2, lsr #25
│ │  			@ <UNDEFINED> instruction: 0xffdffda8
│ │ -	vqrshrn.u32	d22, <illegal reg q1.5>, #4
│ │ +	vqrshrn.u32	d22, q13, #4
│ │  			@ <UNDEFINED> instruction: 0xffdffdd0
│ │  			@ <UNDEFINED> instruction: 0xffdc4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2ada88 <uniffi_pbcli_checksum_method_api_base@@Base+0x141204>
│ │  	beq.n	2ad580 <uniffi_pbcli_checksum_method_api_base@@Base+0x140cfc>
│ │  	b.n	2ada0c <uniffi_pbcli_checksum_method_api_base@@Base+0x141188>
│ │  	str	r0, [r0, #0]
│ │ @@ -597590,15 +597590,15 @@
│ │  	ldmia.w	sp!, {r0}
│ │  	b.n	2ad8e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x14105e>
│ │  			@ <UNDEFINED> instruction: 0xffee1aff
│ │  			@ <UNDEFINED> instruction: 0xffd9eaff
│ │  	str	r0, [r0, r0]
│ │  	b.n	2add8e <uniffi_pbcli_checksum_method_api_base@@Base+0x14150a>
│ │  			@ <UNDEFINED> instruction: 0xfff7eaff
│ │ -	ldr	r3, [r2, #0]
│ │ +	ldr	r2, [r7, #0]
│ │  	vaddl.u16	<illegal reg q13.5>, d31, d31
│ │  	vmlal.u16	q10, d12, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2ad9a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x14111e>
│ │  	b.n	2ad664 <uniffi_pbcli_checksum_method_api_base@@Base+0x140de0>
│ │  	b.n	2ad186 <uniffi_pbcli_checksum_method_api_base@@Base+0x140902>
│ │  	stmia	r0!, {r2, r5, r6}
│ │ @@ -597666,17 +597666,17 @@
│ │  	b.n	2addae <uniffi_pbcli_checksum_method_api_base@@Base+0x14152a>
│ │  	movs	r6, r1
│ │  	asrs	r3, r2, #5
│ │  			@ <UNDEFINED> instruction: 0xffe01aff
│ │  	ldr	r0, [pc, #0]	@ (2ad6fc <uniffi_pbcli_checksum_method_api_base@@Base+0x140e78>)
│ │  	ldmia.w	sp!, {r2, r3, r4, r8, r9, sl, fp, ip, sp, lr, pc}
│ │  	b.n	2ad960 <uniffi_pbcli_checksum_method_api_base@@Base+0x1410dc>
│ │ -	str	r7, [r5, #116]	@ 0x74
│ │ +	str	r6, [r2, #120]	@ 0x78
│ │  	vmlsl.u16	q9, d31, d21
│ │ -	vqshl.u64	d22, d7, #30
│ │ +	vqshl.u64	d22, d30, #30
│ │  	vmull.u16	q9, d31, d5[1]
│ │  			@ <UNDEFINED> instruction: 0xffde4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2adc34 <uniffi_pbcli_checksum_method_api_base@@Base+0x1413b0>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	2ada5e <uniffi_pbcli_checksum_method_api_base@@Base+0x1411da>
│ │  	movs	r0, r0
│ │ @@ -597794,19 +597794,19 @@
│ │  	movs	r7, r0
│ │  	b.n	2adb5a <uniffi_pbcli_checksum_method_api_base@@Base+0x1412d6>
│ │  	strh	r0, [r1, #0]
│ │  	b.n	2ad334 <uniffi_pbcli_checksum_method_api_base@@Base+0x140ab0>
│ │  	ldr	r5, [pc, #960]	@ (2adbe0 <uniffi_pbcli_checksum_method_api_base@@Base+0x14135c>)
│ │  	ldmia.w	sp!, {r2, r3, r4, r8, r9, sl, fp, ip, sp, lr, pc}
│ │  	b.n	2ada84 <uniffi_pbcli_checksum_method_api_base@@Base+0x141200>
│ │ -	str	r7, [r5, #104]	@ 0x68
│ │ +	str	r6, [r2, #108]	@ 0x6c
│ │  	vmla.i16	q15, <illegal reg q15.5>, d1[2]
│ │ -	vqshlu.s64	q11, <illegal reg q3.5>, #28
│ │ +	vqshlu.s64	q11, q15, #28
│ │  	vaddw.u16	q15, <illegal reg q7.5>, d9
│ │ -	vmlsl.u16	q11, d12, d7[0]
│ │ +	vmlsl.u16	q11, d12, d6[3]
│ │  	vshr.u16	q15, <illegal reg q12.5>, #1
│ │  	vmlal.u16	q10, d12, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2adb86 <uniffi_pbcli_checksum_method_api_base@@Base+0x141302>
│ │  	adds	r0, #0
│ │  	b.n	2ad36a <uniffi_pbcli_checksum_method_api_base@@Base+0x140ae6>
│ │  	stmia	r0!, {r5, r6}
│ │ @@ -597874,17 +597874,17 @@
│ │  	b.n	2adf7a <uniffi_pbcli_checksum_method_api_base@@Base+0x1416f6>
│ │  	movs	r2, r0
│ │  	asrs	r3, r2, #5
│ │  			@ <UNDEFINED> instruction: 0xffe01aff
│ │  	ldr	r0, [pc, #0]	@ (2ad8e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x14105c>)
│ │  	ldmia.w	sp!, {r2, r3, r4, r8, r9, sl, fp, ip, sp, lr, pc}
│ │  	b.n	2adb44 <uniffi_pbcli_checksum_method_api_base@@Base+0x1412c0>
│ │ -	str	r3, [r1, #88]	@ 0x58
│ │ +	str	r2, [r6, #88]	@ 0x58
│ │  	vrshr.u16	<illegal reg q8.5>, q1, #1
│ │ -	vsli.64	d22, d19, #29
│ │ +	vsli.64	q11, q5, #29
│ │  	vrshr.u16	<illegal reg q8.5>, q13, #1
│ │  			@ <UNDEFINED> instruction: 0xffdd4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2ade18 <uniffi_pbcli_checksum_method_api_base@@Base+0x141594>
│ │  	ands	r0, r0
│ │  	b.n	2ad422 <uniffi_pbcli_checksum_method_api_base@@Base+0x140b9e>
│ │  	stmia	r0!, {r2, r4, r6}
│ │ @@ -597990,17 +597990,17 @@
│ │  	b.n	2ae11a <uniffi_pbcli_checksum_method_api_base@@Base+0x141896>
│ │  	movs	r0, #0
│ │  	b.n	2ae11e <uniffi_pbcli_checksum_method_api_base@@Base+0x14189a>
│ │  	add	r5, pc, #660	@ (adr r5, 2adc74 <uniffi_pbcli_checksum_method_api_base@@Base+0x1413f0>)
│ │  	add.w	r0, r0, r0
│ │  	b.n	2ae126 <uniffi_pbcli_checksum_method_api_base@@Base+0x1418a2>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r7, sl, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r6, r7, sl, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffdf6f9c
│ │ -	vsri.16	q11, <illegal reg q7.5>, #3
│ │ +	vraddhn.i32	d22, <illegal reg q14.5>, q3
│ │  			@ <UNDEFINED> instruction: 0xffdf6f5c
│ │  	vqshrun.s32	d20, q8, #3
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2adf1c <uniffi_pbcli_checksum_method_api_base@@Base+0x141698>
│ │  	b.n	2ada04 <uniffi_pbcli_checksum_method_api_base@@Base+0x141180>
│ │  	b.n	2ad526 <uniffi_pbcli_checksum_method_api_base@@Base+0x140ca2>
│ │  	stmia	r0!, {r3, r4, r6}
│ │ @@ -598086,17 +598086,17 @@
│ │  	b.n	2ae1f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x141972>
│ │  	movs	r0, #0
│ │  	b.n	2ae1fa <uniffi_pbcli_checksum_method_api_base@@Base+0x141976>
│ │  	add	r5, pc, #440	@ (adr r5, 2adc74 <uniffi_pbcli_checksum_method_api_base@@Base+0x1413f0>)
│ │  	add.w	r0, r0, r0
│ │  	b.n	2ae202 <uniffi_pbcli_checksum_method_api_base@@Base+0x14197e>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r5, r7, r8, r9, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r5, r6, r7, r8, r9, sp, lr}
│ │  	vmul.i16	<illegal reg q15.5>, <illegal reg q7.5>, d1[2]
│ │ -	vsubw.u16	q11, q14, d3
│ │ +	vsubw.u16	q11, q14, d26
│ │  	vmlal.u16	<illegal reg q15.5>, d15, d25
│ │  	vmlal.u16	q10, d12, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2ade1e <uniffi_pbcli_checksum_method_api_base@@Base+0x14159a>
│ │  	b.n	2adae0 <uniffi_pbcli_checksum_method_api_base@@Base+0x14125c>
│ │  	b.n	2ad602 <uniffi_pbcli_checksum_method_api_base@@Base+0x140d7e>
│ │  	stmia	r0!, {r2, r3, r4, r6}
│ │ @@ -598164,18 +598164,18 @@
│ │  	b.n	2ae22a <uniffi_pbcli_checksum_method_api_base@@Base+0x1419a6>
│ │  	movs	r6, r1
│ │  	asrs	r3, r2, #5
│ │  			@ <UNDEFINED> instruction: 0xffe01aff
│ │  	ldr	r0, [pc, #0]	@ (2adb78 <uniffi_pbcli_checksum_method_api_base@@Base+0x1412f4>)
│ │  	ldmia.w	sp!, {r2, r3, r4, r8, r9, sl, fp, ip, sp, lr, pc}
│ │  	b.n	2adddc <uniffi_pbcli_checksum_method_api_base@@Base+0x141558>
│ │ -	str	r3, [r6, #44]	@ 0x2c
│ │ -	vrsra.u16	d22, d9, #1
│ │ -	vrsra.u16	d22, d11, #1
│ │ -			@ <UNDEFINED> instruction: 0xffdf6341
│ │ +	str	r2, [r3, #48]	@ 0x30
│ │ +			@ <UNDEFINED> instruction: 0xffdf6340
│ │ +			@ <UNDEFINED> instruction: 0xffdf6342
│ │ +			@ <UNDEFINED> instruction: 0xffdf6368
│ │  			@ <UNDEFINED> instruction: 0xffdf4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2ae0b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x14182c>
│ │  	beq.n	2adbb8 <uniffi_pbcli_checksum_method_api_base@@Base+0x141334>
│ │  	b.n	2ae034 <uniffi_pbcli_checksum_method_api_base@@Base+0x1417b0>
│ │  	str	r0, [r0, #0]
│ │  	b.n	2adede <uniffi_pbcli_checksum_method_api_base@@Base+0x14165a>
│ │ @@ -598356,18 +598356,18 @@
│ │  	ands	r0, r0
│ │  	b.n	2ae462 <uniffi_pbcli_checksum_method_api_base@@Base+0x141bde>
│ │  	asrs	r4, r1, #32
│ │  	b.n	2ae3a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x141b22>
│ │  	movs	r0, r2
│ │  	b.n	2ae46a <uniffi_pbcli_checksum_method_api_base@@Base+0x141be6>
│ │  			@ <UNDEFINED> instruction: 0xffaeeaff
│ │ -	str	r3, [r2, #36]	@ 0x24
│ │ -	vqshlu.s16	<illegal reg q12.5>, q14, #15
│ │ -	vsra.u16	d22, d7, #2
│ │ -	vmls.f16	<illegal reg q12.5>, <illegal reg q7.5>, d0[0]
│ │ +	str	r2, [r7, #36]	@ 0x24
│ │ +	vrsubhn.i32	d25, <illegal reg q15.5>, <illegal reg q9.5>
│ │ +	vsra.u16	d22, d30, #2
│ │ +	vmls.f16	<illegal reg q12.5>, <illegal reg q7.5>, d7[2]
│ │  	vaddl.u16	q8, d14, d8
│ │  	b.n	2ad862 <uniffi_pbcli_checksum_method_api_base@@Base+0x140fde>
│ │  	movs	r0, r0
│ │  	b.n	2ae3e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x141b62>
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │ @@ -598616,15 +598616,15 @@
│ │  	movs	r0, r0
│ │  	b.n	2ae60c <uniffi_pbcli_checksum_method_api_base@@Base+0x141d88>
│ │  	movs	r4, r0
│ │  	b.n	2ae2ae <uniffi_pbcli_checksum_method_api_base@@Base+0x141a2a>
│ │  	movs	r0, #0
│ │  	asrs	r1, r0, #22
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r8, r9, sl, fp, ip, lr}
│ │ +	ldmia.w	sp!, {r1, r3, r5, r8, r9, sl, fp, ip, lr}
│ │  	vsra.u64	q12, <illegal reg q10.5>, #33
│ │  			@ <UNDEFINED> instruction: 0xffdd4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2ae4a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x141c1c>
│ │  	movs	r0, r0
│ │  	b.n	2ae62a <uniffi_pbcli_checksum_method_api_base@@Base+0x141da6>
│ │  	movs	r5, r3
│ │ @@ -598710,15 +598710,15 @@
│ │  	movs	r0, r6
│ │  	asrs	r0, r2, #22
│ │  	movs	r0, r0
│ │  	asrs	r3, r0, #22
│ │  	movs	r4, r0
│ │  	b.n	2ae382 <uniffi_pbcli_checksum_method_api_base@@Base+0x141afe>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r6, r9, sl, fp, ip, lr}
│ │ +	ldmia.w	sp!, {r1, r4, r5, r6, r9, sl, fp, ip, lr}
│ │  	vmul.f16	<illegal reg q9.5>, <illegal reg q7.5>, d6[3]
│ │  			@ <UNDEFINED> instruction: 0xffdd48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2ae570 <uniffi_pbcli_checksum_method_api_base@@Base+0x141cec>
│ │  	beq.n	2ae068 <uniffi_pbcli_checksum_method_api_base@@Base+0x1417e4>
│ │  	b.n	2ae4f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x141c70>
│ │  	str	r1, [r0, r0]
│ │ @@ -598896,24 +598896,24 @@
│ │  	add	r3, pc, #672	@ (adr r3, 2ae474 <uniffi_pbcli_checksum_method_api_base@@Base+0x141bf0>)
│ │  	add.w	r0, r0, r5
│ │  	b.n	2ae51a <uniffi_pbcli_checksum_method_api_base@@Base+0x141c96>
│ │  	beq.n	2ae1fc <uniffi_pbcli_checksum_method_api_base@@Base+0x141978>
│ │  	b.n	2ae674 <uniffi_pbcli_checksum_method_api_base@@Base+0x141df0>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, sl, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffdc5cb7
│ │ -	vsra.u64	<illegal reg q14.5>, <illegal reg q0.5>, #33
│ │ +			@ <UNDEFINED> instruction: 0xffdc5cde
│ │ +	vsra.u64	<illegal reg q14.5>, q12, #33
│ │  			@ <UNDEFINED> instruction: 0xffde7fd8
│ │ -	vqdmulh.s16	<illegal reg q10.5>, <illegal reg q6.5>, d7[3]
│ │ -	vaddw.u16	<illegal reg q14.5>, <illegal reg q15.5>, d9
│ │ +			@ <UNDEFINED> instruction: 0xffdd5c96
│ │ +	vsra.u64	d29, d16, #33
│ │  	vraddhn.i32	d16, q7, q7
│ │ -			@ <UNDEFINED> instruction: 0xffde5d1b
│ │ -	vqdmulh.s16	<illegal reg q10.5>, <illegal reg q15.5>, d7[3]
│ │ -			@ <UNDEFINED> instruction: 0xffdf5c9b
│ │ -	vsra.u64	d29, d21, #33
│ │ +	vqrdmulh.s16	<illegal reg q10.5>, q7, d2[0]
│ │ +			@ <UNDEFINED> instruction: 0xffdf5d16
│ │ +	vqdmulh.s16	<illegal reg q10.5>, <illegal reg q15.5>, d2[0]
│ │ +	vsra.u64	<illegal reg q14.5>, q6, #33
│ │  			@ <UNDEFINED> instruction: 0xffde4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2ae730 <uniffi_pbcli_checksum_method_api_base@@Base+0x141eac>
│ │  	beq.n	2ae270 <uniffi_pbcli_checksum_method_api_base@@Base+0x1419ec>
│ │  	b.n	2ae6b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x141e30>
│ │  	strb	r1, [r0, #0]
│ │  	b.n	2ae55e <uniffi_pbcli_checksum_method_api_base@@Base+0x141cda>
│ │ @@ -599823,59 +599823,59 @@
│ │  	b.n	2ae52a <uniffi_pbcli_checksum_method_api_base@@Base+0x141ca6>
│ │  			@ <UNDEFINED> instruction: 0xffe0eaff
│ │  	add	r0, pc, #408	@ (adr r0, 2aebb8 <uniffi_pbcli_checksum_method_api_base@@Base+0x142334>)
│ │  	b.n	2af162 <uniffi_pbcli_checksum_method_api_base@@Base+0x1428de>
│ │  	str	r1, [r1, #108]	@ 0x6c
│ │  	b.n	2af026 <uniffi_pbcli_checksum_method_api_base@@Base+0x1427a2>
│ │  			@ <UNDEFINED> instruction: 0xff96eaff
│ │ -	add	r4, pc, #464	@ (adr r4, 2aebfc <uniffi_pbcli_checksum_method_api_base@@Base+0x142378>)
│ │ -			@ <UNDEFINED> instruction: 0xffde59bb
│ │ +	add	r4, pc, #620	@ (adr r4, 2aec98 <uniffi_pbcli_checksum_method_api_base@@Base+0x142414>)
│ │ +	vmul.f16	<illegal reg q10.5>, q15, d2[2]
│ │  	vsli.16	d16, d23, #15
│ │  	vqdmulh.s16	<illegal reg q11.5>, q15, d1[1]
│ │ -	vqrshrun.s32	d21, <illegal reg q9.5>, #3
│ │ +			@ <UNDEFINED> instruction: 0xffdd589a
│ │  	vaddl.u16	q11, d31, d16
│ │ -	vshll.u16	<illegal reg q10.5>, d15, #14
│ │ +	vmull.u16	<illegal reg q10.5>, d14, d6[0]
│ │  	vmlal.u16	q11, d15, d4[1]
│ │ -			@ <UNDEFINED> instruction: 0xffde598b
│ │ +			@ <UNDEFINED> instruction: 0xffde59b2
│ │  	vsra.u64	d22, d24, #33
│ │  			@ <UNDEFINED> instruction: 0xffdebcb6
│ │ -	vmul.f16	<illegal reg q10.5>, q14, d7[2]
│ │ +	vmlsl.u16	<illegal reg q10.5>, d12, d14
│ │  	vrshr.u16	d22, d4, #1
│ │  	vqshl.u16	q8, q12, #14
│ │  			@ <UNDEFINED> instruction: 0xffdd7d76
│ │ -			@ <UNDEFINED> instruction: 0xffdd5ad7
│ │ +			@ <UNDEFINED> instruction: 0xffdd5afe
│ │  	vsubw.u16	q11, <illegal reg q7.5>, d4
│ │  	vshr.u64	q11, q6, #34
│ │ -	vmlal.u16	<illegal reg q10.5>, d14, d31
│ │ +	vqrshrun.s32	d21, q3, #2
│ │  	vshr.u16	q11, q6, #1
│ │ -	vsra.u64	d26, d6, #34
│ │ -	vmlal.u16	<illegal reg q10.5>, d14, d3
│ │ +	vsra.u64	d26, d29, #34
│ │ +	vmlal.u16	<illegal reg q10.5>, d14, d26
│ │  	vshr.u16	d22, d16, #1
│ │  			@ <UNDEFINED> instruction: 0xffde5dd8
│ │ -	vqshl.u64	<illegal reg q10.5>, <illegal reg q3.5>, #30
│ │ +	vqshl.u64	<illegal reg q10.5>, q15, #30
│ │  	vaddl.u16	q11, d15, d4
│ │ -	vqshl.u64	d21, d15, #30
│ │ +			@ <UNDEFINED> instruction: 0xffde57c6
│ │  	vqrdmlsh.s16	<illegal reg q10.5>, <illegal reg q15.5>, d4[1]
│ │ -	vqshl.u16	<illegal reg q10.5>, <illegal reg q5.5>, #14
│ │ +	vabdl.u16	<illegal reg q10.5>, d30, d2
│ │  			@ <UNDEFINED> instruction: 0xffdf5f88
│ │ -			@ <UNDEFINED> instruction: 0xffde589b
│ │ +	vmul.i16	<illegal reg q10.5>, q15, d2[0]
│ │  	vmla.i16	q11, <illegal reg q15.5>, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffdefdde
│ │ -	vmls.f16	<illegal reg q10.5>, <illegal reg q14.5>, d7[0]
│ │ +	vmls.f16	<illegal reg q10.5>, <illegal reg q14.5>, d6[3]
│ │  			@ <UNDEFINED> instruction: 0xffdf5df4
│ │ -	vmull.u16	q12, d14, d4[0]
│ │ -	vmls.f16	<illegal reg q10.5>, q15, d7[3]
│ │ +	vmull.u16	q12, d14, d3[3]
│ │ +	vqshlu.s16	d21, d6, #14
│ │  			@ <UNDEFINED> instruction: 0xffdf5e1c
│ │ -	vabal.u16	<illegal reg q10.5>, d30, d15
│ │ +	vsli.64	d21, d22, #30
│ │  			@ <UNDEFINED> instruction: 0xffdf5dbc
│ │ -			@ <UNDEFINED> instruction: 0xffde0f7b
│ │ +			@ <UNDEFINED> instruction: 0xffde0fa2
│ │  	vqrdmlah.s16	q12, <illegal reg q15.5>, d7[3]
│ │  	vrsubhn.i32	d23, <illegal reg q14.5>, q12
│ │ -	vmls.f16	<illegal reg q10.5>, <illegal reg q6.5>, d3[0]
│ │ -	vqshlu.s16	d21, d11, #15
│ │ +	vmls.f16	<illegal reg q10.5>, <illegal reg q6.5>, d2[3]
│ │ +	vmlsl.u16	<illegal reg q10.5>, d15, d2[0]
│ │  	vqrdmlah.s16	<illegal reg q10.5>, <illegal reg q7.5>, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffde4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2af004 <uniffi_pbcli_checksum_method_api_base@@Base+0x142780>
│ │  	beq.n	2aeb04 <uniffi_pbcli_checksum_method_api_base@@Base+0x142280>
│ │  	b.n	2aef88 <uniffi_pbcli_checksum_method_api_base@@Base+0x142704>
│ │  	movs	r0, #8
│ │ @@ -600007,16 +600007,16 @@
│ │  	b.n	2af346 <uniffi_pbcli_checksum_method_api_base@@Base+0x142ac2>
│ │  	bfcsel	16, 2ae406 <uniffi_pbcli_checksum_method_api_base@@Base+0x141b82>, 18, vs
│ │  	movs	r6, r0
│ │  	b.n	2aef4e <uniffi_pbcli_checksum_method_api_base@@Base+0x1426ca>
│ │  	beq.n	2aec48 <uniffi_pbcli_checksum_method_api_base@@Base+0x1423c4>
│ │  	b.n	2af0a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x142824>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r6, r7, r9, ip, lr}
│ │ -	vrshr.u16	<illegal reg q10.5>, <illegal reg q5.5>, #1
│ │ +	ldmia.w	sp!, {r1, r8, r9, ip, lr}
│ │ +	vsubl.u16	<illegal reg q10.5>, d31, d2
│ │  	vaddl.u16	q8, d15, d0
│ │  	b.n	2af2c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x142a3e>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	asrs	r0, r3, #32
│ │  	b.n	2af12a <uniffi_pbcli_checksum_method_api_base@@Base+0x1428a6>
│ │  	cmp	r7, #159	@ 0x9f
│ │  	b.n	2aef50 <uniffi_pbcli_checksum_method_api_base@@Base+0x1426cc>
│ │ @@ -600094,16 +600094,16 @@
│ │  	b.n	2af012 <uniffi_pbcli_checksum_method_api_base@@Base+0x14278e>
│ │  	movs	r0, #101	@ 0x65
│ │  	b.n	2af416 <uniffi_pbcli_checksum_method_api_base@@Base+0x142b92>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2aedf8 <uniffi_pbcli_checksum_method_api_base@@Base+0x142574>
│ │  	ldr	r0, [pc, #192]	@ (2aed9c <uniffi_pbcli_checksum_method_api_base@@Base+0x142518>)
│ │  	ldmia.w	sp!, {r1, r3, r4, r5, r6, fp, ip, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xea01c69a
│ │ -	vrsubhn.i32	d28, q15, q3
│ │ +			@ <UNDEFINED> instruction: 0xea01c6c1
│ │ +	vrsubhn.i32	d28, q15, <illegal reg q14.5>
│ │  			@ <UNDEFINED> instruction: 0xffde4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2af20c <uniffi_pbcli_checksum_method_api_base@@Base+0x142988>
│ │  	beq.n	2aed3c <uniffi_pbcli_checksum_method_api_base@@Base+0x1424b8>
│ │  	b.n	2af190 <uniffi_pbcli_checksum_method_api_base@@Base+0x14290c>
│ │  	add	r0, pc, #32	@ (adr r0, 2aed18 <uniffi_pbcli_checksum_method_api_base@@Base+0x142494>)
│ │  	b.n	2ae830 <uniffi_pbcli_checksum_method_api_base@@Base+0x141fac>
│ │ @@ -600883,20 +600883,20 @@
│ │  	b.n	2aeeec <uniffi_pbcli_checksum_method_api_base@@Base+0x142668>
│ │  			@ <UNDEFINED> instruction: 0xffa7eaff
│ │  	str	r0, [r1, #8]
│ │  	b.n	2afafa <uniffi_pbcli_checksum_method_api_base@@Base+0x143276>
│ │  	str	r1, [sp, #444]	@ 0x1bc
│ │  	b.n	2af9be <uniffi_pbcli_checksum_method_api_base@@Base+0x14313a>
│ │  			@ <UNDEFINED> instruction: 0xffd0eaff
│ │ -	stmia	r6!, {r1}
│ │ -			@ <UNDEFINED> instruction: 0xffdede74
│ │ -	vmls.f16	q14, q15, d6[0]
│ │ -			@ <UNDEFINED> instruction: 0xffdede38
│ │ -	vaddw.u16	q14, q7, d18
│ │ -			@ <UNDEFINED> instruction: 0xffded994
│ │ +	stmia	r6!, {r0, r3, r5}
│ │ +			@ <UNDEFINED> instruction: 0xffdede9b
│ │ +	vmls.f16	q14, q15, d5[3]
│ │ +			@ <UNDEFINED> instruction: 0xffdede5f
│ │ +	vmla.f16	q14, q7, d1[1]
│ │ +			@ <UNDEFINED> instruction: 0xffded9bb
│ │  			@ <UNDEFINED> instruction: 0xffde48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2af8fc <uniffi_pbcli_checksum_method_api_base@@Base+0x143078>
│ │  	str	r0, [r0, #0]
│ │  	b.n	2af726 <uniffi_pbcli_checksum_method_api_base@@Base+0x142ea2>
│ │  	movs	r0, r0
│ │  	b.n	2aef0a <uniffi_pbcli_checksum_method_api_base@@Base+0x142686>
│ │ @@ -602573,42 +602573,42 @@
│ │  	lsrs	r0, r0, #8
│ │  	str	r1, [r0, r0]
│ │  	b.n	2b0946 <uniffi_pbcli_checksum_method_api_base@@Base+0x1440c2>
│ │  	mrc2	10, 7, lr, cr4, cr15, {7}	@ <UNPREDICTABLE>
│ │  	str	r0, [r0, r0]
│ │  	b.n	2b094e <uniffi_pbcli_checksum_method_api_base@@Base+0x1440ca>
│ │  	mrc2	10, 7, lr, cr2, cr15, {7}	@ <UNPREDICTABLE>
│ │ -	pop	{r1, r5, r6, pc}
│ │ -	vqshrn.u32	d17, <illegal reg q13.5>, #2
│ │ -	vmull.u16	<illegal reg q13.5>, d15, d30
│ │ -	vmul.i16	<illegal reg q13.5>, q7, d6[2]
│ │ -	vsri.16	d17, d31, #2
│ │ -	vmlal.u16	<illegal reg q13.5>, d15, d30
│ │ -	vraddhn.i32	d17, q7, <illegal reg q3.5>
│ │ -	vmul.i16	<illegal reg q13.5>, <illegal reg q15.5>, d2[2]
│ │ -	vsri.64	d17, d27, #34
│ │ -	vmlal.u16	<illegal reg q13.5>, d15, d2[1]
│ │ -	vmull.p<illegal width 16>	q8, d14, d19
│ │ -	vabdl.u16	<illegal reg q13.5>, d15, d2
│ │ -	vmlal.u16	<illegal reg q13.5>, d30, d2[0]
│ │ -	vsubl.u16	<illegal reg q13.5>, d30, d26
│ │ -	vmull.p<illegal width 16>	q8, d30, d3
│ │ -	vrsubhn.i32	d27, <illegal reg q15.5>, q5
│ │ -	vmlsl.u16	<illegal reg q13.5>, d14, d6[2]
│ │ -	vsli.64	d27, d30, #30
│ │ -	vsra.u64	d17, d7, #34
│ │ -	vmla.f16	<illegal reg q13.5>, <illegal reg q15.5>, d2[2]
│ │ -			@ <UNDEFINED> instruction: 0xffde0dbb
│ │ -			@ <UNDEFINED> instruction: 0xffdfbb92
│ │ -			@ <UNDEFINED> instruction: 0xffdebb56
│ │ -			@ <UNDEFINED> instruction: 0xffdebb2e
│ │ -	vmull.u16	<illegal reg q13.5>, d30, d6[3]
│ │ -			@ <UNDEFINED> instruction: 0xffdebada
│ │ -	vqshl.u64	<illegal reg q13.5>, q13, #30
│ │ -	vrsra.u64	<illegal reg q8.5>, <illegal reg q1.5>, #34
│ │ +	pop	{r0, r3, r7, pc}
│ │ +	vmul.f16	<illegal reg q8.5>, q7, d2[2]
│ │ +			@ <UNDEFINED> instruction: 0xffdfbc55
│ │ +	vmlal.u16	<illegal reg q13.5>, d30, d13
│ │ +	vmls.i16	<illegal reg q8.5>, q7, d6[2]
│ │ +	vqrshrun.s32	d27, <illegal reg q2.5>, #1
│ │ +	vraddhn.i32	d17, q7, q15
│ │ +			@ <UNDEFINED> instruction: 0xffdfb909
│ │ +	vmls.i16	<illegal reg q8.5>, q15, d2[2]
│ │ +	vrshr.u16	<illegal reg q13.5>, <illegal reg q8.5>, #1
│ │ +	vqrdmlah.s16	q8, q7, d2[1]
│ │ +	vabdl.u16	<illegal reg q13.5>, d15, d25
│ │ +	vmlal.u16	<illegal reg q13.5>, d30, d1[3]
│ │ +	vrshr.u64	<illegal reg q13.5>, <illegal reg q0.5>, #34
│ │ +	vmull.p<illegal width 16>	q8, d30, d26
│ │ +	vqshlu.s64	d27, d17, #31
│ │ +	vrsubhn.i32	d27, q15, <illegal reg q6.5>
│ │ +	vmls.f16	<illegal reg q13.5>, q15, d5[2]
│ │ +	vsra.u64	d17, d30, #34
│ │ +	vsubl.u16	<illegal reg q13.5>, d15, d9
│ │ +	vqrdmulh.s16	q8, q15, d2[2]
│ │ +			@ <UNDEFINED> instruction: 0xffdfbbb9
│ │ +			@ <UNDEFINED> instruction: 0xffdebb7d
│ │ +			@ <UNDEFINED> instruction: 0xffdebb55
│ │ +			@ <UNDEFINED> instruction: 0xffdebb15
│ │ +			@ <UNDEFINED> instruction: 0xffdebb01
│ │ +	vmlal.u16	<illegal reg q13.5>, d14, d17
│ │ +	vrsra.u64	<illegal reg q8.5>, q13, #34
│ │  			@ <UNDEFINED> instruction: 0xffdf4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2b07a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x143f20>
│ │  	ands	r0, r0
│ │  	b.n	2afdae <uniffi_pbcli_checksum_method_api_base@@Base+0x14352a>
│ │  	b.n	2b02a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x143a1c>
│ │  	b.n	2afdc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x143544>
│ │ @@ -602705,18 +602705,18 @@
│ │  	b.n	2afe70 <uniffi_pbcli_checksum_method_api_base@@Base+0x1435ec>
│ │  	ldr	r4, [pc, #448]	@ (2b051c <uniffi_pbcli_checksum_method_api_base@@Base+0x143c98>)
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r6, r7, r8, sl, fp, ip}
│ │  			@ <UNDEFINED> instruction: 0xea00e008
│ │  	b.n	2afe7c <uniffi_pbcli_checksum_method_api_base@@Base+0x1435f8>
│ │  	ldr	r4, [pc, #448]	@ (2b0528 <uniffi_pbcli_checksum_method_api_base@@Base+0x143ca4>)
│ │  	ldmia.w	sp!, {r0, r6, r7}
│ │ -	and.w	ip, r0, ip, asr #32
│ │ -	vshr.u64	<illegal reg q10.5>, q4, #33
│ │ -	vmull.u16	q8, d31, d8
│ │ -	vsra.u16	d21, d20, #1
│ │ +	and.w	ip, r0, r3, lsr #1
│ │ +	vshr.u64	<illegal reg q10.5>, <illegal reg q15.5>, #33
│ │ +	vmull.u16	q8, d31, d31
│ │ +	vsra.u16	<illegal reg q10.5>, <illegal reg q5.5>, #1
│ │  			@ <UNDEFINED> instruction: 0xffdf48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2b08a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x14401c>
│ │  	movs	r0, r0
│ │  	b.n	2b0a2c <uniffi_pbcli_checksum_method_api_base@@Base+0x1441a8>
│ │  	movs	r4, r2
│ │  	lsrs	r0, r0, #8
│ │ @@ -602844,19 +602844,19 @@
│ │  	ldmia.w	sp!, {r1, r3, r5, r7, r9, sl, fp, ip}
│ │  			@ <UNDEFINED> instruction: 0xea00e00c
│ │  	b.n	2affb8 <uniffi_pbcli_checksum_method_api_base@@Base+0x143734>
│ │  	ands	r0, r1
│ │  	b.n	2affbc <uniffi_pbcli_checksum_method_api_base@@Base+0x143738>
│ │  	ldr	r0, [pc, #960]	@ (2b0868 <uniffi_pbcli_checksum_method_api_base@@Base+0x143fe4>)
│ │  	ldmia.w	sp!, {r0, r4, r5, r8}
│ │ -	and.w	fp, r0, r8, lsr #1
│ │ +	and.w	fp, r0, pc, ror #1
│ │  			@ <UNDEFINED> instruction: 0xffdffd7e
│ │ -			@ <UNDEFINED> instruction: 0xffdd0af4
│ │ +			@ <UNDEFINED> instruction: 0xffdd0b1b
│ │  			@ <UNDEFINED> instruction: 0xffdffd1a
│ │ -			@ <UNDEFINED> instruction: 0xffdd0b80
│ │ +			@ <UNDEFINED> instruction: 0xffdd0ba7
│ │  			@ <UNDEFINED> instruction: 0xffdffda6
│ │  			@ <UNDEFINED> instruction: 0xffdd4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2b09e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x144164>
│ │  	ands	r0, r0
│ │  	b.n	2afff2 <uniffi_pbcli_checksum_method_api_base@@Base+0x14376e>
│ │  	b.n	2b04e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x143c60>
│ │ @@ -602954,17 +602954,17 @@
│ │  	b.n	2b00b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x143830>
│ │  	ldr	r4, [pc, #448]	@ (2b0760 <uniffi_pbcli_checksum_method_api_base@@Base+0x143edc>)
│ │  	ldmia.w	sp!, {r1, r6, r8, r9, sl, fp, ip}
│ │  			@ <UNDEFINED> instruction: 0xea00e008
│ │  	b.n	2b00c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x14383c>
│ │  	ldr	r4, [pc, #448]	@ (2b076c <uniffi_pbcli_checksum_method_api_base@@Base+0x143ee8>)
│ │  	ldmia.w	sp!, {r0, r1, r3, r4, r6, r7, r8}
│ │ -	and.w	r9, r0, r8, asr #3
│ │ +	and.w	sl, r0, pc
│ │  			@ <UNDEFINED> instruction: 0xffdfcd76
│ │ -	vmull.u16	q8, d12, d4[0]
│ │ +	vmull.u16	q8, d12, d3[3]
│ │  			@ <UNDEFINED> instruction: 0xffdfcdd2
│ │  			@ <UNDEFINED> instruction: 0xffdc4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2b0ae4 <uniffi_pbcli_checksum_method_api_base@@Base+0x144260>
│ │  	beq.n	2b05e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x143d60>
│ │  	b.n	2b0a68 <uniffi_pbcli_checksum_method_api_base@@Base+0x1441e4>
│ │  	ands	r0, r0
│ │ @@ -603037,16 +603037,16 @@
│ │  	b.n	2b077c <uniffi_pbcli_checksum_method_api_base@@Base+0x143ef8>
│ │  	sxth	r2, r3
│ │  	add.w	r0, r1, r4
│ │  	b.n	2b09a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x144122>
│ │  	beq.n	2b06a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x143e1c>
│ │  	b.n	2b0b00 <uniffi_pbcli_checksum_method_api_base@@Base+0x14427c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r2, r6, r8, fp}
│ │ -			@ <UNDEFINED> instruction: 0xffdf08f0
│ │ +	ldmia.w	sp!, {r0, r1, r3, r5, r6, r8, fp}
│ │ +	vqshrn.u32	d16, <illegal reg q3.5>, #1
│ │  			@ <UNDEFINED> instruction: 0xffdf4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2b0b98 <uniffi_pbcli_checksum_method_api_base@@Base+0x144314>
│ │  	beq.n	2b06b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x143e34>
│ │  	b.n	2b0b1c <uniffi_pbcli_checksum_method_api_base@@Base+0x144298>
│ │  	ands	r0, r1
│ │  	b.n	2b01bc <uniffi_pbcli_checksum_method_api_base@@Base+0x143938>
│ │ @@ -603375,17 +603375,17 @@
│ │  	b.n	2b0fd6 <uniffi_pbcli_checksum_method_api_base@@Base+0x144752>
│ │  	movs	r0, r2
│ │  	b.n	2b109a <uniffi_pbcli_checksum_method_api_base@@Base+0x144816>
│ │  	movs	r0, #0
│ │  	b.n	2b109e <uniffi_pbcli_checksum_method_api_base@@Base+0x14481a>
│ │  	ldr	r1, [sp, #788]	@ 0x314
│ │  			@ <UNDEFINED> instruction: 0xeb00ffd7
│ │ -			@ <UNDEFINED> instruction: 0xeaff1ce8
│ │ +			@ <UNDEFINED> instruction: 0xeaff1d0f
│ │  	vqshl.u16	d25, d19, #15
│ │ -			@ <UNDEFINED> instruction: 0xffdc1cb8
│ │ +			@ <UNDEFINED> instruction: 0xffdc1cdf
│ │  	vabdl.u16	<illegal reg q12.5>, d15, d3
│ │  			@ <UNDEFINED> instruction: 0xffdc4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2b0e98 <uniffi_pbcli_checksum_method_api_base@@Base+0x144614>
│ │  	beq.n	2b09b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x144134>
│ │  	b.n	2b0e1c <uniffi_pbcli_checksum_method_api_base@@Base+0x144598>
│ │  	movs	r6, r0
│ │ @@ -603789,22 +603789,22 @@
│ │  	ldr	r0, [sp, #900]	@ 0x384
│ │  	add.w	r0, r0, r8, lsr #32
│ │  	b.n	2b0830 <uniffi_pbcli_checksum_method_api_base@@Base+0x143fac>
│ │  	ldr	r3, [pc, #844]	@ (2b1044 <uniffi_pbcli_checksum_method_api_base@@Base+0x1447c0>)
│ │  			@ <UNDEFINED> instruction: 0xebff4014
│ │  	b.n	2b0838 <uniffi_pbcli_checksum_method_api_base@@Base+0x143fb4>
│ │  	vpmin.u16	q15, <illegal reg q14.5>, <illegal reg q15.5>
│ │ -	subs	r4, r3, r6
│ │ -	vmlal.u16	<illegal reg q14.5>, d15, d26
│ │ -			@ <UNDEFINED> instruction: 0xffde1b5c
│ │ -			@ <UNDEFINED> instruction: 0xffdfd7ea
│ │ -			@ <UNDEFINED> instruction: 0xffde1bc8
│ │ -	vqrshrun.s32	d29, q3, #1
│ │ -			@ <UNDEFINED> instruction: 0xffde1924
│ │ -	vsli.64	d29, d18, #31
│ │ +	subs	r3, r0, r7
│ │ +	vqrshrun.s32	d29, <illegal reg q0.5>, #1
│ │ +			@ <UNDEFINED> instruction: 0xffde1b83
│ │ +	vqshrun.s32	d29, <illegal reg q0.5>, #1
│ │ +			@ <UNDEFINED> instruction: 0xffde1bef
│ │ +	vqrshrun.s32	d29, <illegal reg q14.5>, #1
│ │ +	vmul.f16	<illegal reg q8.5>, q7, d3[1]
│ │ +	vsli.64	<illegal reg q14.5>, <illegal reg q4.5>, #31
│ │  			@ <UNDEFINED> instruction: 0xffde4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2b1244 <uniffi_pbcli_checksum_method_api_base@@Base+0x1449c0>
│ │  	beq.n	2b0d64 <uniffi_pbcli_checksum_method_api_base@@Base+0x1444e0>
│ │  	b.n	2b11c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x144944>
│ │  	movs	r0, r0
│ │  	b.n	2b13d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x144b54>
│ │ @@ -604206,31 +604206,31 @@
│ │  	movs	r0, #76	@ 0x4c
│ │  	b.n	2b0be4 <uniffi_pbcli_checksum_method_api_base@@Base+0x144360>
│ │  	movs	r0, r0
│ │  	b.n	2b11c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x144944>
│ │  	movs	r0, #2
│ │  	b.n	2b11cc <uniffi_pbcli_checksum_method_api_base@@Base+0x144948>
│ │  			@ <UNDEFINED> instruction: 0xff83eaff
│ │ -	adds	r4, r5, r1
│ │ +	adds	r3, r2, r2
│ │  	vsubw.u16	q9, <illegal reg q7.5>, d17
│ │ -	vmul.i16	<illegal reg q8.5>, q7, d0[0]
│ │ +	vmul.i16	<illegal reg q8.5>, q7, d7[2]
│ │  	vrshr.u64	q9, <illegal reg q10.5>, #33
│ │ -	vmlal.u16	<illegal reg q8.5>, d30, d8
│ │ +	vmlal.u16	<illegal reg q8.5>, d30, d31
│ │  	vrsra.u16	d18, d29, #1
│ │ -	vqshlu.s64	<illegal reg q8.5>, q2, #30
│ │ +	vqshlu.s64	<illegal reg q8.5>, <illegal reg q13.5>, #30
│ │  	vaddw.u16	q9, <illegal reg q15.5>, d9
│ │ -	vqshlu.s64	<illegal reg q8.5>, q8, #30
│ │ +	vqshl.u16	d17, d7, #14
│ │  	vaddw.u16	q9, <illegal reg q15.5>, d21
│ │ -	vqshl.u16	d17, d28, #14
│ │ +			@ <UNDEFINED> instruction: 0xffde1763
│ │  	vsra.u64	q9, <illegal reg q8.5>, #33
│ │ -	vrsubhn.i32	d17, q7, q12
│ │ +	vmlsl.u16	<illegal reg q8.5>, d14, d7[1]
│ │  	vshr.u64	q9, <illegal reg q6.5>, #33
│ │ -	vmls.f16	<illegal reg q8.5>, q15, d0[3]
│ │ +	vrsubhn.i32	d17, q7, <illegal reg q7.5>
│ │  	vshr.u64	d18, d13, #33
│ │ -	vsli.16	<illegal reg q8.5>, q0, #14
│ │ +	vsli.16	<illegal reg q8.5>, <illegal reg q11.5>, #14
│ │  	vaddl.u16	q9, d15, d5
│ │  	vmlal.u16	q10, d14, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2b1442 <uniffi_pbcli_checksum_method_api_base@@Base+0x144bbe>
│ │  	stmia	r0!, {r2, r3}
│ │  	b.n	2b0c2c <uniffi_pbcli_checksum_method_api_base@@Base+0x1443a8>
│ │  	stmia	r0!, {}
│ │ @@ -604744,15 +604744,15 @@
│ │  	movs	r0, #0
│ │  	b.n	2b1cee <uniffi_pbcli_checksum_method_api_base@@Base+0x14546a>
│ │  	str	r6, [sp, #708]	@ 0x2c4
│ │  	add.w	r0, r0, r0
│ │  	b.n	2b1cf6 <uniffi_pbcli_checksum_method_api_base@@Base+0x145472>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r1, r2, r4, r6, r9}
│ │ -	vsra.u16	<illegal reg q11.5>, <illegal reg q6.5>, #2
│ │ +	vaddw.u16	<illegal reg q11.5>, q15, d4
│ │  	vmlal.u16	q10, d14, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2b190a <uniffi_pbcli_checksum_method_api_base@@Base+0x145086>
│ │  	b.n	2b15dc <uniffi_pbcli_checksum_method_api_base@@Base+0x144d58>
│ │  	b.n	2b1104 <uniffi_pbcli_checksum_method_api_base@@Base+0x144880>
│ │  	stmia	r0!, {r2, r3}
│ │  	b.n	2b110e <uniffi_pbcli_checksum_method_api_base@@Base+0x14488a>
│ │ @@ -604788,15 +604788,15 @@
│ │  	movs	r0, #0
│ │  	b.n	2b1d56 <uniffi_pbcli_checksum_method_api_base@@Base+0x1454d2>
│ │  	str	r6, [sp, #604]	@ 0x25c
│ │  	add.w	r0, r0, r0
│ │  	b.n	2b1d5e <uniffi_pbcli_checksum_method_api_base@@Base+0x1454da>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r1, r2, r3, r5, r6, r7, r8}
│ │ -			@ <UNDEFINED> instruction: 0xffde5c5d
│ │ +	vmull.u16	<illegal reg q10.5>, d30, d4
│ │  	vmlal.u16	q10, d14, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2b1972 <uniffi_pbcli_checksum_method_api_base@@Base+0x1450ee>
│ │  	stmia	r0!, {r2, r3}
│ │  	b.n	2b115c <uniffi_pbcli_checksum_method_api_base@@Base+0x1448d8>
│ │  	stmia	r0!, {}
│ │  	b.n	2b1172 <uniffi_pbcli_checksum_method_api_base@@Base+0x1448ee>
│ │ @@ -604828,15 +604828,15 @@
│ │  	movs	r0, #0
│ │  	b.n	2b1db6 <uniffi_pbcli_checksum_method_api_base@@Base+0x145532>
│ │  	str	r6, [sp, #508]	@ 0x1fc
│ │  	add.w	r0, r0, r0
│ │  	b.n	2b1dbe <uniffi_pbcli_checksum_method_api_base@@Base+0x14553a>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r1, r2, r3, r7, r8}
│ │ -			@ <UNDEFINED> instruction: 0xffde5c11
│ │ +			@ <UNDEFINED> instruction: 0xffde5c38
│ │  			@ <UNDEFINED> instruction: 0xffde4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2b1bac <uniffi_pbcli_checksum_method_api_base@@Base+0x145328>
│ │  	beq.n	2b16a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x144e20>
│ │  	b.n	2b1b30 <uniffi_pbcli_checksum_method_api_base@@Base+0x1452ac>
│ │  	ands	r3, r0
│ │  	b.n	2b19da <uniffi_pbcli_checksum_method_api_base@@Base+0x145156>
│ │ @@ -605052,17 +605052,17 @@
│ │  	ldrsb	r0, [r4, r5]
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	2b1bae <uniffi_pbcli_checksum_method_api_base@@Base+0x14532a>
│ │  	beq.n	2b18a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x145024>
│ │  	b.n	2b1d08 <uniffi_pbcli_checksum_method_api_base@@Base+0x145484>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r1, r2, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffdd3c14
│ │ +			@ <UNDEFINED> instruction: 0xffdd3c3b
│ │  			@ <UNDEFINED> instruction: 0xffdfffba
│ │ -			@ <UNDEFINED> instruction: 0xffdd3be8
│ │ +	vmull.u16	<illegal reg q9.5>, d13, d15
│ │  			@ <UNDEFINED> instruction: 0xffdf4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2b1da8 <uniffi_pbcli_checksum_method_api_base@@Base+0x145524>
│ │  	beq.n	2b18e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x145064>
│ │  	b.n	2b1d2c <uniffi_pbcli_checksum_method_api_base@@Base+0x1454a8>
│ │  	movs	r0, r0
│ │  	b.n	2b1f36 <uniffi_pbcli_checksum_method_api_base@@Base+0x1456b2>
│ │ @@ -605586,23 +605586,23 @@
│ │  	b.n	2b239a <uniffi_pbcli_checksum_method_api_base@@Base+0x145b16>
│ │  	str	r4, [r3, #0]
│ │  	b.n	2b1858 <uniffi_pbcli_checksum_method_api_base@@Base+0x144fd4>
│ │  	add	r0, pc, #80	@ (adr r0, 2b1d70 <uniffi_pbcli_checksum_method_api_base@@Base+0x1454ec>)
│ │  	b.n	2b185c <uniffi_pbcli_checksum_method_api_base@@Base+0x144fd8>
│ │  	vpmin.u16	q15, q10, <illegal reg q15.5>
│ │  	mrc2	15, 2, pc, cr10, cr13, {6}
│ │ -	ldmia	r1!, {r4}
│ │ +	ldmia	r1, {r0, r1, r2, r4, r5}
│ │  			@ <UNDEFINED> instruction: 0xffdefe1a
│ │ -			@ <UNDEFINED> instruction: 0xffddc8d0
│ │ +			@ <UNDEFINED> instruction: 0xffddc8f7
│ │  	vqrdmulh.s16	<illegal reg q15.5>, q15, d6[3]
│ │ -	vmlal.u16	q14, d29, d20
│ │ +	vmul.i16	q14, <illegal reg q14.5>, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffdefdaa
│ │ -	vmul.i16	q14, <illegal reg q6.5>, d0[2]
│ │ +	vmlal.u16	q14, d29, d7
│ │  	vqrdmulh.s16	<illegal reg q15.5>, q7, d2[2]
│ │ -	vqshrun.s32	d28, q4, #3
│ │ +	vqshrun.s32	d28, <illegal reg q15.5>, #3
│ │  	vmlal.u16	q10, d14, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2b2096 <uniffi_pbcli_checksum_method_api_base@@Base+0x145812>
│ │  	beq.n	2b1d88 <uniffi_pbcli_checksum_method_api_base@@Base+0x145504>
│ │  	b.n	2b21f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x145970>
│ │  	stmia	r0!, {}
│ │  	b.n	2b249e <uniffi_pbcli_checksum_method_api_base@@Base+0x145c1a>
│ │ @@ -606282,45 +606282,45 @@
│ │  	b.n	2b267e <uniffi_pbcli_checksum_method_api_base@@Base+0x145dfa>
│ │  	strb	r2, [r5, r2]
│ │  			@ <UNDEFINED> instruction: 0xebff0007
│ │  	b.n	2b2686 <uniffi_pbcli_checksum_method_api_base@@Base+0x145e02>
│ │  	strb	r0, [r5, r2]
│ │  			@ <UNDEFINED> instruction: 0xebfffee2
│ │  			@ <UNDEFINED> instruction: 0xeafff98a
│ │ -	vqshrn.u32	d29, q9, #3
│ │ +	vqrshrn.u32	d29, <illegal reg q4.5>, #3
│ │  	vqrshrn.u32	d31, q7, #2
│ │ -			@ <UNDEFINED> instruction: 0xffddd906
│ │ +			@ <UNDEFINED> instruction: 0xffddd92d
│ │  	vqshrn.u32	d31, q9, #2
│ │ -			@ <UNDEFINED> instruction: 0xffddd8da
│ │ +			@ <UNDEFINED> instruction: 0xffddd901
│ │  			@ <UNDEFINED> instruction: 0xffdef8f6
│ │ -			@ <UNDEFINED> instruction: 0xffddd89e
│ │ +	vmul.i16	<illegal reg q14.5>, <illegal reg q14.5>, d5[0]
│ │  	vmul.f16	<illegal reg q15.5>, q15, d2[1]
│ │ -	vqrshrn.u32	d29, q9, #3
│ │ +			@ <UNDEFINED> instruction: 0xffddd999
│ │  	vrsubhn.i32	d31, q15, q1
│ │ -	vrsubhn.i32	d29, <illegal reg q6.5>, q13
│ │ +	vqshlu.s16	<illegal reg q14.5>, <illegal reg q0.5>, #13
│ │  	vmlsl.u16	<illegal reg q15.5>, d14, d2[0]
│ │ -	vmls.f16	<illegal reg q14.5>, <illegal reg q14.5>, d2[3]
│ │ +	vqshlu.s16	d29, d1, #13
│ │  	vqshlu.s16	d31, d6, #14
│ │ -	vsli.64	d29, d30, #29
│ │ +	vmls.f16	<illegal reg q14.5>, <illegal reg q14.5>, d5[2]
│ │  	vsli.64	<illegal reg q15.5>, q7, #30
│ │ -	vabal.u16	<illegal reg q14.5>, d29, d6
│ │ +	vabal.u16	<illegal reg q14.5>, d29, d29
│ │  	vabal.u16	<illegal reg q15.5>, d14, d30
│ │ -	vsri.64	<illegal reg q14.5>, q3, #35
│ │ +	vsri.64	<illegal reg q14.5>, <illegal reg q14.5>, #35
│ │  	vsri.64	<illegal reg q15.5>, q9, #34
│ │ -	vsri.64	d29, d10, #35
│ │ +	vmls.i16	<illegal reg q14.5>, <illegal reg q14.5>, d1[0]
│ │  	vsli.64	<illegal reg q15.5>, q13, #30
│ │ -	vabal.u16	<illegal reg q14.5>, d29, d18
│ │ +	vmls.f16	<illegal reg q14.5>, <illegal reg q14.5>, d1[1]
│ │  	vabal.u16	<illegal reg q15.5>, d30, d2
│ │ -	vabal.u16	<illegal reg q14.5>, d13, d26
│ │ +	vsli.16	<illegal reg q14.5>, <illegal reg q0.5>, #13
│ │  	vsli.64	d31, d14, #30
│ │ -	vmls.f16	<illegal reg q14.5>, <illegal reg q6.5>, d6[0]
│ │ +	vmls.f16	<illegal reg q14.5>, <illegal reg q6.5>, d5[3]
│ │  	vsli.16	<illegal reg q15.5>, q3, #14
│ │ -	vsri.64	<illegal reg q14.5>, q15, #35
│ │ +	vabal.u16	<illegal reg q14.5>, d13, d21
│ │  	vrsubhn.i32	d31, q15, q13
│ │ -	vqshlu.s16	<illegal reg q14.5>, q1, #13
│ │ +	vqshlu.s16	<illegal reg q14.5>, <illegal reg q12.5>, #13
│ │  			@ <UNDEFINED> instruction: 0xffde4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2b28f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x14606c>
│ │  	beq.n	2b23f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x145b74>
│ │  	b.n	2b2874 <uniffi_pbcli_checksum_method_api_base@@Base+0x145ff0>
│ │  	movs	r0, r0
│ │  	b.n	2b2b1e <uniffi_pbcli_checksum_method_api_base@@Base+0x14629a>
│ │ @@ -607021,16 +607021,16 @@
│ │  	b.n	2b317a <uniffi_pbcli_checksum_method_api_base@@Base+0x1468f6>
│ │  	movs	r0, #0
│ │  	b.n	2b317e <uniffi_pbcli_checksum_method_api_base@@Base+0x1468fa>
│ │  	str	r1, [sp, #564]	@ 0x234
│ │  	add.w	r0, r0, r0
│ │  	b.n	2b3186 <uniffi_pbcli_checksum_method_api_base@@Base+0x146902>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r6, r7, r9, ip, sp, lr}
│ │ -	vshll.u16	q9, d2, #14
│ │ +	ldmia.w	sp!, {r5, r8, r9, ip, sp, lr}
│ │ +	vshll.u16	q9, d25, #14
│ │  	vqshrun.s32	d20, q8, #1
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2b2f74 <uniffi_pbcli_checksum_method_api_base@@Base+0x1466f0>
│ │  	beq.n	2b2a7c <uniffi_pbcli_checksum_method_api_base@@Base+0x1461f8>
│ │  	b.n	2b2ef8 <uniffi_pbcli_checksum_method_api_base@@Base+0x146674>
│ │  	b.n	2b2a78 <uniffi_pbcli_checksum_method_api_base@@Base+0x1461f4>
│ │  	b.n	2b2598 <uniffi_pbcli_checksum_method_api_base@@Base+0x145d14>
│ │ @@ -607075,15 +607075,15 @@
│ │  	b.n	2b31fa <uniffi_pbcli_checksum_method_api_base@@Base+0x146976>
│ │  	str	r1, [sp, #440]	@ 0x1b8
│ │  	add.w	r0, r0, r0
│ │  	b.n	2b3202 <uniffi_pbcli_checksum_method_api_base@@Base+0x14697e>
│ │  	beq.n	2b2ad4 <uniffi_pbcli_checksum_method_api_base@@Base+0x146250>
│ │  	b.n	2b2f5c <uniffi_pbcli_checksum_method_api_base@@Base+0x1466d8>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r5, r6, r9, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r2, r5, r7, r9, ip, sp, lr}
│ │  	vrsubhn.i32	d16, q15, <illegal reg q12.5>
│ │  			@ <UNDEFINED> instruction: 0xffdd4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2b2ff4 <uniffi_pbcli_checksum_method_api_base@@Base+0x146770>
│ │  	b.n	2b2b04 <uniffi_pbcli_checksum_method_api_base@@Base+0x146280>
│ │  	b.n	2b2614 <uniffi_pbcli_checksum_method_api_base@@Base+0x145d90>
│ │  	stmia	r0!, {}
│ │ @@ -607129,15 +607129,15 @@
│ │  	b.n	2b3276 <uniffi_pbcli_checksum_method_api_base@@Base+0x1469f2>
│ │  	movs	r0, #0
│ │  	b.n	2b327a <uniffi_pbcli_checksum_method_api_base@@Base+0x1469f6>
│ │  	str	r1, [sp, #312]	@ 0x138
│ │  	add.w	r0, r0, r0
│ │  	b.n	2b3282 <uniffi_pbcli_checksum_method_api_base@@Base+0x1469fe>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r5, r6, r7, r8, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r2, r5, r9, ip, sp, lr}
│ │  	vrsubhn.i32	d16, q7, <illegal reg q12.5>
│ │  	vmlal.u16	q10, d13, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2b2e96 <uniffi_pbcli_checksum_method_api_base@@Base+0x146612>
│ │  	stmia	r0!, {}
│ │  	b.n	2b2680 <uniffi_pbcli_checksum_method_api_base@@Base+0x145dfc>
│ │  	stmia	r0!, {r3, r4, r5}
│ │ @@ -607167,15 +607167,15 @@
│ │  	b.n	2b32d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x146a4e>
│ │  	movs	r0, #0
│ │  	b.n	2b32d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x146a52>
│ │  	str	r1, [sp, #220]	@ 0xdc
│ │  	add.w	r0, r0, r0
│ │  	b.n	2b335e <uniffi_pbcli_checksum_method_api_base@@Base+0x146ada>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r8, r9, sl, lr}
│ │ +	ldmia.w	sp!, {r1, r4, r5, r8, r9, sl, lr}
│ │  	vmull.u16	<illegal reg q8.5>, d30, d5[3]
│ │  			@ <UNDEFINED> instruction: 0xffde4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2b30cc <uniffi_pbcli_checksum_method_api_base@@Base+0x146848>
│ │  	b.n	2b2bcc <uniffi_pbcli_checksum_method_api_base@@Base+0x146348>
│ │  	b.n	2b26ec <uniffi_pbcli_checksum_method_api_base@@Base+0x145e68>
│ │  	stmia	r0!, {}
│ │ @@ -607213,15 +607213,15 @@
│ │  	b.n	2b333e <uniffi_pbcli_checksum_method_api_base@@Base+0x146aba>
│ │  	movs	r0, #0
│ │  	b.n	2b3342 <uniffi_pbcli_checksum_method_api_base@@Base+0x146abe>
│ │  	str	r1, [sp, #112]	@ 0x70
│ │  	add.w	r0, r0, r0
│ │  	b.n	2b33ca <uniffi_pbcli_checksum_method_api_base@@Base+0x146b46>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r7, r9, sl, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r6, r7, r9, sl, lr}
│ │  			@ <UNDEFINED> instruction: 0xffde1a91
│ │  			@ <UNDEFINED> instruction: 0xffde4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2b3138 <uniffi_pbcli_checksum_method_api_base@@Base+0x1468b4>
│ │  	beq.n	2b2c88 <uniffi_pbcli_checksum_method_api_base@@Base+0x146404>
│ │  	b.n	2b30bc <uniffi_pbcli_checksum_method_api_base@@Base+0x146838>
│ │  	str	r0, [r0, #0]
│ │ @@ -607863,26 +607863,26 @@
│ │  	b.n	2b3846 <uniffi_pbcli_checksum_method_api_base@@Base+0x146fc2>
│ │  	vpmin.u16	<illegal reg q8.5>, <illegal reg q14.5>, <illegal reg q15.5>
│ │  	vpmin.u16	q15, q8, <illegal reg q15.5>
│ │  	str	r0, [r5, r0]
│ │  	b.n	2b2cec <uniffi_pbcli_checksum_method_api_base@@Base+0x146468>
│ │  	vpmin.u8	q15, q15, <illegal reg q15.5>
│ │  	bvs.n	2b30de <uniffi_pbcli_checksum_method_api_base@@Base+0x14685a>
│ │ -			@ <UNDEFINED> instruction: 0xffdc58b6
│ │ +			@ <UNDEFINED> instruction: 0xffdc58dd
│ │  	vqrshrn.u32	d17, q15, #2
│ │  	vmla.f16	<illegal reg q14.5>, q15, d5[2]
│ │  	vsra.u16	q8, <illegal reg q1.5>, #3
│ │  			@ <UNDEFINED> instruction: 0xffdd8fdf
│ │ -	vqrdmulh.s16	q9, <illegal reg q6.5>, d1[3]
│ │ +			@ <UNDEFINED> instruction: 0xffdd2d90
│ │  	vshr.u64	<illegal reg q9.5>, <illegal reg q5.5>, #34
│ │  			@ <UNDEFINED> instruction: 0xffdd5faa
│ │  	vshr.u16	<illegal reg q9.5>, <illegal reg q9.5>, #3
│ │  	vshll.u16	<illegal reg q13.5>, d14, #13
│ │ -	vqrdmlah.s16	<illegal reg q14.5>, q6, d3[3]
│ │ -	vmull.u16	q9, d30, d16
│ │ +			@ <UNDEFINED> instruction: 0xffdcde92
│ │ +	vqdmulh.s16	q9, q15, d7[0]
│ │  	vsubl.u16	q13, d30, d3
│ │  	vqrdmlsh.s16	q9, <illegal reg q14.5>, d1[2]
│ │  	vmla.f16	q8, <illegal reg q14.5>, d3[1]
│ │  	vmlsl.u16	<illegal reg q8.5>, d14, d29
│ │  	vaddw.u16	q8, <illegal reg q14.5>, d3
│ │  			@ <UNDEFINED> instruction: 0xffde4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │ @@ -608062,18 +608062,18 @@
│ │  	stmia	r3!, {}
│ │  	movs	r1, r1
│ │  	b.n	2b36be <uniffi_pbcli_checksum_method_api_base@@Base+0x146e3a>
│ │  	beq.n	2b33b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x146b34>
│ │  	b.n	2b3818 <uniffi_pbcli_checksum_method_api_base@@Base+0x146f94>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r2, r3, r4, r6, r7, r8, r9, sl, fp, lr, pc}
│ │ -	vsri.16	d28, d26, #4
│ │ -	vsra.u64	q14, q9, #34
│ │ -			@ <UNDEFINED> instruction: 0xffde0990
│ │ -	vrshr.u16	d21, d2, #1
│ │ +	vmls.i16	q14, q6, d1[2]
│ │ +	vrshr.u16	d28, d9, #2
│ │ +			@ <UNDEFINED> instruction: 0xffde09b7
│ │ +	vrshr.u16	d21, d25, #1
│ │  	vaddl.u16	q8, d14, d4
│ │  	b.n	2b2edc <uniffi_pbcli_checksum_method_api_base@@Base+0x146658>
│ │  	movs	r0, r0
│ │  	b.n	2b34c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x146c3c>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ands	r4, r0
│ │  	movs	r7, r3
│ │ @@ -608386,16 +608386,16 @@
│ │  	b.n	2b39aa <uniffi_pbcli_checksum_method_api_base@@Base+0x147126>
│ │  	ldr	r0, [r5, r5]
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	2b39b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x14712e>
│ │  	beq.n	2b36ac <uniffi_pbcli_checksum_method_api_base@@Base+0x146e28>
│ │  	b.n	2b3b0c <uniffi_pbcli_checksum_method_api_base@@Base+0x147288>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r4, r6, r7, sl, fp, sp, pc}
│ │ -	vrsubhn.i32	d25, q7, q1
│ │ +	ldmia.w	sp!, {r3, r4, r5, r6, r7, sl, fp, sp, pc}
│ │ +	vrsubhn.i32	d25, q7, <illegal reg q12.5>
│ │  	vmlal.u16	q10, d14, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2b39ca <uniffi_pbcli_checksum_method_api_base@@Base+0x147146>
│ │  	stmia	r0!, {r4, r6}
│ │  	b.n	2b31ae <uniffi_pbcli_checksum_method_api_base@@Base+0x14692a>
│ │  	movs	r0, r0
│ │  	b.n	2b3d4a <uniffi_pbcli_checksum_method_api_base@@Base+0x1474c6>
│ │ @@ -608433,16 +608433,16 @@
│ │  	b.n	2b3e1a <uniffi_pbcli_checksum_method_api_base@@Base+0x147596>
│ │  	movs	r0, #0
│ │  	b.n	2b3e1e <uniffi_pbcli_checksum_method_api_base@@Base+0x14759a>
│ │  	ldrh	r5, [r4, #50]	@ 0x32
│ │  	add.w	r0, r0, r0
│ │  	b.n	2b3e26 <uniffi_pbcli_checksum_method_api_base@@Base+0x1475a2>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r4, r5, r6, r7, r8, r9, fp, sp, pc}
│ │ -	vmull.u16	<illegal reg q11.5>, d30, d22
│ │ +	ldmia.w	sp!, {r3, r4, sl, fp, sp, pc}
│ │ +	vqdmulh.s16	<illegal reg q11.5>, q15, d5[1]
│ │  	vmlal.u16	q10, d14, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2b3a3a <uniffi_pbcli_checksum_method_api_base@@Base+0x1471b6>
│ │  	beq.n	2b370c <uniffi_pbcli_checksum_method_api_base@@Base+0x146e88>
│ │  	b.n	2b3b98 <uniffi_pbcli_checksum_method_api_base@@Base+0x147314>
│ │  	stmia	r0!, {r0, r1}
│ │  	b.n	2b3a42 <uniffi_pbcli_checksum_method_api_base@@Base+0x1471be>
│ │ @@ -608482,16 +608482,16 @@
│ │  	b.n	2b3e8e <uniffi_pbcli_checksum_method_api_base@@Base+0x14760a>
│ │  	ldrh	r1, [r1, #50]	@ 0x32
│ │  	add.w	r0, r0, r0
│ │  	b.n	2b3e96 <uniffi_pbcli_checksum_method_api_base@@Base+0x147612>
│ │  	beq.n	2b376e <uniffi_pbcli_checksum_method_api_base@@Base+0x146eea>
│ │  	b.n	2b3a9a <uniffi_pbcli_checksum_method_api_base@@Base+0x147216>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r7, r8, r9, fp, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffdeeed0
│ │ +	ldmia.w	sp!, {r3, r5, r7, r8, r9, fp, sp, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffdeeef7
│ │  			@ <UNDEFINED> instruction: 0xffde4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2b3c88 <uniffi_pbcli_checksum_method_api_base@@Base+0x147404>
│ │  	beq.n	2b3788 <uniffi_pbcli_checksum_method_api_base@@Base+0x146f04>
│ │  	b.n	2b3c0c <uniffi_pbcli_checksum_method_api_base@@Base+0x147388>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	2b3ab6 <uniffi_pbcli_checksum_method_api_base@@Base+0x147232>
│ │ @@ -608616,16 +608616,16 @@
│ │  	b.n	2b3bbe <uniffi_pbcli_checksum_method_api_base@@Base+0x14733a>
│ │  	ands	r1, r7
│ │  			@ <UNDEFINED> instruction: 0xebff0006
│ │  	b.n	2b3bc6 <uniffi_pbcli_checksum_method_api_base@@Base+0x147342>
│ │  	beq.n	2b38c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x14703c>
│ │  	b.n	2b3d20 <uniffi_pbcli_checksum_method_api_base@@Base+0x14749c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r6, r9, fp, sp, pc}
│ │ -	vqrdmlah.s16	q10, q15, d7[0]
│ │ +	ldmia.w	sp!, {r2, r3, r4, r7, r9, fp, sp, pc}
│ │ +	vqrdmlah.s16	q10, q15, d6[3]
│ │  	vmlal.u16	q10, d14, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2b3bde <uniffi_pbcli_checksum_method_api_base@@Base+0x14735a>
│ │  	stmia	r0!, {r4, r6}
│ │  	b.n	2b33c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x146b3e>
│ │  	movs	r0, r0
│ │  	b.n	2b3f5e <uniffi_pbcli_checksum_method_api_base@@Base+0x1476da>
│ │ @@ -608657,16 +608657,16 @@
│ │  	b.n	2b4022 <uniffi_pbcli_checksum_method_api_base@@Base+0x14779e>
│ │  	movs	r0, #0
│ │  	b.n	2b4026 <uniffi_pbcli_checksum_method_api_base@@Base+0x1477a2>
│ │  	ldrh	r3, [r4, #46]	@ 0x2e
│ │  	add.w	r0, r0, r0
│ │  	b.n	2b402e <uniffi_pbcli_checksum_method_api_base@@Base+0x1477aa>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r5, r6, r7, r8, fp, sp, pc}
│ │ -	vqrdmlah.s16	<illegal reg q13.5>, q15, d1[2]
│ │ +	ldmia.w	sp!, {r4, r9, fp, sp, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffdebf08
│ │  	vmlal.u16	q10, d14, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2b3c42 <uniffi_pbcli_checksum_method_api_base@@Base+0x1473be>
│ │  	stmia	r0!, {r4, r6}
│ │  	b.n	2b3426 <uniffi_pbcli_checksum_method_api_base@@Base+0x146ba2>
│ │  	movs	r0, r0
│ │  	b.n	2b3fc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x14773e>
│ │ @@ -608698,15 +608698,15 @@
│ │  	b.n	2b4086 <uniffi_pbcli_checksum_method_api_base@@Base+0x147802>
│ │  	movs	r0, #0
│ │  	b.n	2b408a <uniffi_pbcli_checksum_method_api_base@@Base+0x147806>
│ │  	ldrh	r2, [r1, #46]	@ 0x2e
│ │  	add.w	r0, r0, r0
│ │  	b.n	2b4092 <uniffi_pbcli_checksum_method_api_base@@Base+0x14780e>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r7, r8, fp, sp, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r5, r7, r8, fp, sp, pc}
│ │  	vqrdmlsh.s16	<illegal reg q11.5>, q7, d5[0]
│ │  			@ <UNDEFINED> instruction: 0xffdc4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2b3e80 <uniffi_pbcli_checksum_method_api_base@@Base+0x1475fc>
│ │  	movs	r0, #84	@ 0x54
│ │  	b.n	2b348a <uniffi_pbcli_checksum_method_api_base@@Base+0x146c06>
│ │  	movs	r0, r0
│ │ @@ -608747,15 +608747,15 @@
│ │  	b.n	2b40fa <uniffi_pbcli_checksum_method_api_base@@Base+0x147876>
│ │  	ands	r0, r0
│ │  	b.n	2b40fe <uniffi_pbcli_checksum_method_api_base@@Base+0x14787a>
│ │  	ldrh	r5, [r5, #44]	@ 0x2c
│ │  	add.w	r0, r0, r4
│ │  	b.n	2b3d06 <uniffi_pbcli_checksum_method_api_base@@Base+0x147482>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r2, r4, r8, fp, sp, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r5, r8, fp, sp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffdede5d
│ │  	vaddl.u16	q8, d13, d0
│ │  	b.n	2b4076 <uniffi_pbcli_checksum_method_api_base@@Base+0x1477f2>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	asrs	r0, r2, #32
│ │  	b.n	2b3ede <uniffi_pbcli_checksum_method_api_base@@Base+0x14765a>
│ │  	cmp	r7, #159	@ 0x9f
│ │ @@ -611509,22 +611509,22 @@
│ │  	b.n	2b59aa <uniffi_pbcli_checksum_method_api_base@@Base+0x149126>
│ │  	add	r0, pc, #240	@ (adr r0, 2b535c <uniffi_pbcli_checksum_method_api_base@@Base+0x148ad8>)
│ │  	b.n	2b4da8 <uniffi_pbcli_checksum_method_api_base@@Base+0x148524>
│ │  	str	r0, [r4, r0]
│ │  	b.n	2b4dac <uniffi_pbcli_checksum_method_api_base@@Base+0x148528>
│ │  	mcr2	10, 7, lr, cr6, cr15, {7}	@ <UNPREDICTABLE>
│ │  	ldrh	r2, [r4, #60]	@ 0x3c
│ │ -			@ <UNDEFINED> instruction: 0xffdc2f31
│ │ +			@ <UNDEFINED> instruction: 0xffdc2f58
│ │  	vqshlu.s64	q12, q1, #30
│ │ -	vmlsl.u16	q9, d12, d1[2]
│ │ +	vrsubhn.i32	d18, q14, q4
│ │  	vabal.u16	<illegal reg q13.5>, d14, d8
│ │  			@ <UNDEFINED> instruction: 0xffdf8f34
│ │  	movs	r2, r4
│ │  	strh	r6, [r1, #44]	@ 0x2c
│ │ -	vsli.16	d18, d13, #12
│ │ +	vmls.f16	q9, q6, d4[0]
│ │  	vmlsl.u16	q12, d14, d2[1]
│ │  	vrsubhn.i32	d24, q6, q9
│ │  			@ <UNDEFINED> instruction: 0xffdc8b12
│ │  	vmls.i16	q12, q14, d6[2]
│ │  	vmull.u16	q12, d28, d6[2]
│ │  	vmull.u16	q12, d28, d6[0]
│ │  	vabal.u16	q12, d12, d18
│ │ @@ -612059,21 +612059,21 @@
│ │  	b.n	2b5e86 <uniffi_pbcli_checksum_method_api_base@@Base+0x149602>
│ │  	strh	r0, [r2, #0]
│ │  	b.n	2b5284 <uniffi_pbcli_checksum_method_api_base@@Base+0x148a00>
│ │  	str	r4, [r2, #0]
│ │  	b.n	2b5288 <uniffi_pbcli_checksum_method_api_base@@Base+0x148a04>
│ │  	vpmin.u16	q7, <illegal reg q14.5>, <illegal reg q15.5>
│ │  	ldrb	r2, [r6, #27]
│ │ -	vsubw.u16	<illegal reg q9.5>, q6, d10
│ │ +	vrsra.u16	d19, d17, #4
│ │  			@ <UNDEFINED> instruction: 0xffde7ffe
│ │  	vqrdmlsh.s16	<illegal reg q11.5>, q6, d6[3]
│ │ -	vsubw.u16	<illegal reg q9.5>, q14, d6
│ │ +	vsubw.u16	<illegal reg q9.5>, q14, d29
│ │  	vqrdmlah.s16	<illegal reg q11.5>, q7, d2[2]
│ │  			@ <UNDEFINED> instruction: 0xffdc7be6
│ │ -			@ <UNDEFINED> instruction: 0xffdc2ffe
│ │ +	vaddl.u16	<illegal reg q9.5>, d12, d21
│ │  			@ <UNDEFINED> instruction: 0xffde7eb6
│ │  	vmull.p<illegal width 16>	<illegal reg q11.5>, d28, d14
│ │  			@ <UNDEFINED> instruction: 0xffdc4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2b5c9c <uniffi_pbcli_checksum_method_api_base@@Base+0x149418>
│ │  	ands	r0, r0
│ │  	b.n	2b5ac6 <uniffi_pbcli_checksum_method_api_base@@Base+0x149242>
│ │ @@ -616683,23 +616683,23 @@
│ │  	asrs	r6, r5, #1
│ │  	b.n	2b8656 <uniffi_pbcli_checksum_method_api_base@@Base+0x14bdd2>
│ │  	movs	r0, #0
│ │  	b.n	2b865a <uniffi_pbcli_checksum_method_api_base@@Base+0x14bdd6>
│ │  	ldrb	r6, [r2, #17]
│ │  			@ <UNDEFINED> instruction: 0xeb00ffaa
│ │  			@ <UNDEFINED> instruction: 0xeaffcb36
│ │ -	vsri.64	d22, d22, #36
│ │ +	vsri.64	q11, <illegal reg q6.5>, #36
│ │  			@ <UNDEFINED> instruction: 0xffdeca92
│ │ -	vsri.16	d22, d2, #4
│ │ +	vsri.16	d22, d25, #4
│ │  	vmull.u16	q14, d30, d2[3]
│ │ -	vmls.i16	q11, q6, d2[3]
│ │ +	vsri.64	d22, d1, #36
│ │  	vmull.u16	q14, d14, d2[1]
│ │ -			@ <UNDEFINED> instruction: 0xffdc63ca
│ │ +	vrsra.u64	q11, <illegal reg q8.5>, #36
│ │  			@ <UNDEFINED> instruction: 0xffdecabe
│ │ -	vsri.16	d22, d30, #4
│ │ +	vmls.i16	q11, q6, d5[2]
│ │  			@ <UNDEFINED> instruction: 0xffde4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2b846c <uniffi_pbcli_checksum_method_api_base@@Base+0x14bbe8>
│ │  	beq.n	2b7f8c <uniffi_pbcli_checksum_method_api_base@@Base+0x14b708>
│ │  	b.n	2b83f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x14bb6c>
│ │  	movs	r6, r0
│ │  	b.n	2b85fe <uniffi_pbcli_checksum_method_api_base@@Base+0x14bd7a>
│ │ @@ -617434,29 +617434,29 @@
│ │  	b.n	2b80fc <uniffi_pbcli_checksum_method_api_base@@Base+0x14b878>
│ │  	movs	r0, r0
│ │  	b.n	2b86e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x14be5c>
│ │  	movs	r0, #2
│ │  	b.n	2b86e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x14be60>
│ │  			@ <UNDEFINED> instruction: 0xff9deaff
│ │  	stmia	r6!, {r1, r2, r3, r5}
│ │ -			@ <UNDEFINED> instruction: 0xffdc5fdc
│ │ +	vaddl.u16	q11, d12, d3
│ │  	vrsubhn.i32	d28, q7, q1
│ │ -			@ <UNDEFINED> instruction: 0xffdc5fb0
│ │ +			@ <UNDEFINED> instruction: 0xffdc5fd7
│ │  	vmlsl.u16	q14, d14, d2[1]
│ │ -			@ <UNDEFINED> instruction: 0xffdc5ff8
│ │ +	vshr.u16	d22, d15, #4
│ │  	vraddhn.i32	d28, q15, q9
│ │ -			@ <UNDEFINED> instruction: 0xffdc5e50
│ │ +			@ <UNDEFINED> instruction: 0xffdc5e77
│ │  	vsri.64	d28, d30, #34
│ │ -	vqrdmlah.s16	<illegal reg q10.5>, q6, d4[3]
│ │ +			@ <UNDEFINED> instruction: 0xffdc5e93
│ │  	vabal.u16	q14, d14, d14
│ │ -			@ <UNDEFINED> instruction: 0xffdc5ebc
│ │ +	vqrdmlah.s16	<illegal reg q10.5>, q14, d3[2]
│ │  	vrsra.u64	q14, q11, #34
│ │ -			@ <UNDEFINED> instruction: 0xffdc5da4
│ │ +	vqrdmulh.s16	<illegal reg q10.5>, q14, d3[1]
│ │  	vsubw.u16	q14, q15, d10
│ │ -			@ <UNDEFINED> instruction: 0xffdc5d38
│ │ +			@ <UNDEFINED> instruction: 0xffdc5d5f
│ │  			@ <UNDEFINED> instruction: 0xffde4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2b8b2c <uniffi_pbcli_checksum_method_api_base@@Base+0x14c2a8>
│ │  	ands	r0, r0
│ │  	b.n	2b8956 <uniffi_pbcli_checksum_method_api_base@@Base+0x14c0d2>
│ │  	subs	r4, #71	@ 0x47
│ │  			@ <UNDEFINED> instruction: 0xebff0028
│ │ @@ -617780,15 +617780,15 @@
│ │  	b.n	2b842c <uniffi_pbcli_checksum_method_api_base@@Base+0x14bba8>
│ │  	cmp	r4, #28
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	2b8c3a <uniffi_pbcli_checksum_method_api_base@@Base+0x14c3b6>
│ │  	beq.n	2b8934 <uniffi_pbcli_checksum_method_api_base@@Base+0x14c0b0>
│ │  	b.n	2b8d94 <uniffi_pbcli_checksum_method_api_base@@Base+0x14c510>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r3, r7, r9, fp, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r4, r5, r7, r9, fp, sp, lr, pc}
│ │  	vaddw.u16	q11, <illegal reg q14.5>, d7
│ │  			@ <UNDEFINED> instruction: 0xffdd4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2b8e2c <uniffi_pbcli_checksum_method_api_base@@Base+0x14c5a8>
│ │  	str	r3, [r0, r0]
│ │  	b.n	2b8c56 <uniffi_pbcli_checksum_method_api_base@@Base+0x14c3d2>
│ │  	strb	r2, [r0, #0]
│ │ @@ -618196,16 +618196,16 @@
│ │  	movs	r7, r0
│ │  	b.n	2b8fde <uniffi_pbcli_checksum_method_api_base@@Base+0x14c75a>
│ │  	subs	r2, #78	@ 0x4e
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	2b9346 <uniffi_pbcli_checksum_method_api_base@@Base+0x14cac2>
│ │  			@ <UNDEFINED> instruction: 0xffb41aff
│ │  			@ <UNDEFINED> instruction: 0xffcdeaff
│ │ -	b.n	2b8ac2 <uniffi_pbcli_checksum_method_api_base@@Base+0x14c23e>
│ │ -	vsubl.u16	<illegal reg q13.5>, d29, d29
│ │ +	b.n	2b8b10 <uniffi_pbcli_checksum_method_api_base@@Base+0x14c28c>
│ │ +	vrshr.u64	<illegal reg q13.5>, q2, #35
│ │  			@ <UNDEFINED> instruction: 0xffde4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2b91d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x14c954>
│ │  	ands	r0, r0
│ │  	b.n	2b9002 <uniffi_pbcli_checksum_method_api_base@@Base+0x14c77e>
│ │  	subs	r2, #156	@ 0x9c
│ │  			@ <UNDEFINED> instruction: 0xebff0008
│ │ @@ -618401,15 +618401,15 @@
│ │  	b.n	2b91c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x14c942>
│ │  	adds	r0, #4
│ │  	b.n	2b91ca <uniffi_pbcli_checksum_method_api_base@@Base+0x14c946>
│ │  	bne.n	2b8d90 <uniffi_pbcli_checksum_method_api_base@@Base+0x14c50c>
│ │  			@ <UNDEFINED> instruction: 0xebffd018
│ │  	b.n	2b9328 <uniffi_pbcli_checksum_method_api_base@@Base+0x14caa4>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r7, sl, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r3, r5, r7, sl, sp, lr, pc}
│ │  	vqdmulh.s16	<illegal reg q10.5>, <illegal reg q14.5>, d2[2]
│ │  			@ <UNDEFINED> instruction: 0xffdc4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2b93c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x14cb3c>
│ │  	beq.n	2b8ee0 <uniffi_pbcli_checksum_method_api_base@@Base+0x14c65c>
│ │  	b.n	2b9344 <uniffi_pbcli_checksum_method_api_base@@Base+0x14cac0>
│ │  	ands	r3, r0
│ │ @@ -618795,18 +618795,18 @@
│ │  	str	r0, [r0, r2]
│ │  	b.n	2b8d12 <uniffi_pbcli_checksum_method_api_base@@Base+0x14c48e>
│ │  	movs	r7, r0
│ │  	b.n	2b9536 <uniffi_pbcli_checksum_method_api_base@@Base+0x14ccb2>
│ │  	str	r0, [r0, #0]
│ │  	b.n	2b8d14 <uniffi_pbcli_checksum_method_api_base@@Base+0x14c490>
│ │  			@ <UNDEFINED> instruction: 0xff85eaff
│ │ -	b.n	2b99c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x14d13e>
│ │ -	vshr.u64	d24, d13, #35
│ │ -	vmla.f16	q15, q15, d5[3]
│ │ -	vmull.p<illegal width 16>	<illegal reg q11.5>, d29, d25
│ │ +	b.n	2b8a10 <uniffi_pbcli_checksum_method_api_base@@Base+0x14c18c>
│ │ +	vmla.i16	q12, <illegal reg q14.5>, d4[0]
│ │ +	vrshr.u16	d30, d4, #2
│ │ +			@ <UNDEFINED> instruction: 0xffdd7ed0
│ │  			@ <UNDEFINED> instruction: 0xffde4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2b9730 <uniffi_pbcli_checksum_method_api_base@@Base+0x14ceac>
│ │  	beq.n	2b9280 <uniffi_pbcli_checksum_method_api_base@@Base+0x14c9fc>
│ │  	b.n	2b96b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x14ce30>
│ │  	str	r0, [sp, #32]
│ │  	b.n	2b8d54 <uniffi_pbcli_checksum_method_api_base@@Base+0x14c4d0>
│ │ @@ -621023,15 +621023,15 @@
│ │  	b.n	2ba84a <uniffi_pbcli_checksum_method_api_base@@Base+0x14dfc6>
│ │  	beq.n	2ba544 <uniffi_pbcli_checksum_method_api_base@@Base+0x14dcc0>
│ │  	b.n	2ba9a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x14e120>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {lr}
│ │  	b.n	2bac56 <uniffi_pbcli_checksum_method_api_base@@Base+0x14e3d2>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │ -	ldmia	r5, {r0, r2, r5, r6, r7}
│ │ +	ldmia	r6!, {r2, r3}
│ │  	vmls.i16	q8, <illegal reg q6.5>, d1[1]
│ │  			@ <UNDEFINED> instruction: 0xffdd4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2baa44 <uniffi_pbcli_checksum_method_api_base@@Base+0x14e1c0>
│ │  	beq.n	2ba564 <uniffi_pbcli_checksum_method_api_base@@Base+0x14dce0>
│ │  	b.n	2ba9c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x14e144>
│ │  	movs	r0, r0
│ │ @@ -621609,18 +621609,18 @@
│ │  	movs	r0, #8
│ │  	b.n	2bad6e <uniffi_pbcli_checksum_method_api_base@@Base+0x14e4ea>
│ │  	vrhadd.u<illegal width 64>	d14, d3, d31
│ │  	movs	r0, r0
│ │  	b.n	2bb0d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x14e852>
│ │  			@ <UNDEFINED> instruction: 0xffbb1aff
│ │  	mrc2	10, 7, lr, cr9, cr15, {7}	@ <UNPREDICTABLE>
│ │ -	ldmia	r5!, {r0, r2, r4}
│ │ -	vmlsl.u16	q14, d13, d13
│ │ +	ldmia	r5, {r2, r3, r4, r5}
│ │ +	vshll.u16	q14, d20, #13
│ │  			@ <UNDEFINED> instruction: 0xffddde37
│ │ -	vqdmulh.s16	q14, <illegal reg q5.5>, d1[0]
│ │ +	vqdmulh.s16	q14, <illegal reg q5.5>, d0[3]
│ │  			@ <UNDEFINED> instruction: 0xffdd4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2baf70 <uniffi_pbcli_checksum_method_api_base@@Base+0x14e6ec>
│ │  	beq.n	2baa68 <uniffi_pbcli_checksum_method_api_base@@Base+0x14e1e4>
│ │  	b.n	2baef4 <uniffi_pbcli_checksum_method_api_base@@Base+0x14e670>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	2bad9e <uniffi_pbcli_checksum_method_api_base@@Base+0x14e51a>
│ │ @@ -621816,16 +621816,16 @@
│ │  	b.n	2baf3e <uniffi_pbcli_checksum_method_api_base@@Base+0x14e6ba>
│ │  	movs	r4, #17
│ │  			@ <UNDEFINED> instruction: 0xebff0006
│ │  	b.n	2baf46 <uniffi_pbcli_checksum_method_api_base@@Base+0x14e6c2>
│ │  	beq.n	2bac38 <uniffi_pbcli_checksum_method_api_base@@Base+0x14e3b4>
│ │  	b.n	2bb0a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x14e81c>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r0, r5, r6, r7, r9, sl, lr, pc}
│ │ -	vqrshrun.s32	d26, <illegal reg q9.5>, #3
│ │ +	ldmia.w	sp!, {r3, r8, r9, sl, lr, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffdda89a
│ │  			@ <UNDEFINED> instruction: 0xffde4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2bb138 <uniffi_pbcli_checksum_method_api_base@@Base+0x14e8b4>
│ │  	beq.n	2bac48 <uniffi_pbcli_checksum_method_api_base@@Base+0x14e3c4>
│ │  	b.n	2bb0bc <uniffi_pbcli_checksum_method_api_base@@Base+0x14e838>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	2baf66 <uniffi_pbcli_checksum_method_api_base@@Base+0x14e6e2>
│ │ @@ -623881,15 +623881,15 @@
│ │  	b.n	2bbffe <uniffi_pbcli_checksum_method_api_base@@Base+0x14f77a>
│ │  	asrs	r0, r7, #32
│ │  	lsls	r0, r0, #12
│ │  			@ <UNDEFINED> instruction: 0xffbeeaff
│ │  	ldmia	r2, {r0, r2, r5, r7}
│ │  	vmlsl.u16	q14, d11, d17
│ │  			@ <UNDEFINED> instruction: 0xffdbc9f1
│ │ -	vqrdmlah.s16	q8, <illegal reg q13.5>, d7[3]
│ │ +			@ <UNDEFINED> instruction: 0xffdb0f16
│ │  	vmlal.u16	q10, d14, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2bc0ba <uniffi_pbcli_checksum_method_api_base@@Base+0x14f836>
│ │  	adds	r0, #20
│ │  	b.n	2bb89e <uniffi_pbcli_checksum_method_api_base@@Base+0x14f01a>
│ │  	movs	r0, #0
│ │  	b.n	2bc0c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x14f83e>
│ │ @@ -624753,16 +624753,16 @@
│ │  	str	r0, [sp, #600]	@ 0x258
│ │  	add.w	r0, r1, r7
│ │  	b.n	2bc81e <uniffi_pbcli_checksum_method_api_base@@Base+0x14ff9a>
│ │  	ldr	r4, [sp, #684]	@ 0x2ac
│ │  	add.w	r0, r1, r5
│ │  	b.n	2bc826 <uniffi_pbcli_checksum_method_api_base@@Base+0x14ffa2>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r5, r8, r9, sl, ip, pc}
│ │ -	vshr.u64	d22, d6, #35
│ │ +	ldmia.w	sp!, {r0, r2, r5, r6, r8, r9, sl, ip, pc}
│ │ +	vshr.u64	d22, d29, #35
│ │  	vraddhn.i32	d18, q7, q5
│ │  	b.n	2bcaf6 <uniffi_pbcli_checksum_method_api_base@@Base+0x150272>
│ │  	lsls	r2, r7, #4
│ │  	and.w	ip, r0, r0, ror #17
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2bca1c <uniffi_pbcli_checksum_method_api_base@@Base+0x150198>
│ │  	str	r0, [r0, r0]
│ │ @@ -625300,24 +625300,24 @@
│ │  	b.n	2bd0ee <uniffi_pbcli_checksum_method_api_base@@Base+0x15086a>
│ │  	movs	r3, r0
│ │  	b.n	2bcc52 <uniffi_pbcli_checksum_method_api_base@@Base+0x1503ce>
│ │  	movs	r0, #56	@ 0x38
│ │  	lsls	r0, r0, #12
│ │  			@ <UNDEFINED> instruction: 0xffbdeaff
│ │  	bhi.n	2bca40 <uniffi_pbcli_checksum_method_api_base@@Base+0x1501bc>
│ │ -			@ <UNDEFINED> instruction: 0xffdb2b26
│ │ +			@ <UNDEFINED> instruction: 0xffdb2b4d
│ │  	vshr.u16	q12, q13, #2
│ │ -			@ <UNDEFINED> instruction: 0xffdc2bc2
│ │ +			@ <UNDEFINED> instruction: 0xffdc2be9
│ │  	vmlsl.u16	q14, d14, d5[3]
│ │ -			@ <UNDEFINED> instruction: 0xffdc2b96
│ │ -			@ <UNDEFINED> instruction: 0xffde8b53
│ │ -	vmull.u16	q9, d14, d30
│ │ +			@ <UNDEFINED> instruction: 0xffdc2bbd
│ │ +			@ <UNDEFINED> instruction: 0xffde8b7a
│ │ +			@ <UNDEFINED> instruction: 0xffde2c55
│ │  	vqshlu.s64	q14, q11, #30
│ │  	vqshrun.s32	d28, <illegal reg q11.5>, #4
│ │ -			@ <UNDEFINED> instruction: 0xffdc2c56
│ │ +			@ <UNDEFINED> instruction: 0xffdc2c7d
│ │  			@ <UNDEFINED> instruction: 0xffde4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2bcf08 <uniffi_pbcli_checksum_method_api_base@@Base+0x150684>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	2bcd32 <uniffi_pbcli_checksum_method_api_base@@Base+0x1504ae>
│ │  	movs	r1, r0
│ │  	b.n	2bcd36 <uniffi_pbcli_checksum_method_api_base@@Base+0x1504b2>
│ │ @@ -625424,15 +625424,15 @@
│ │  	cmp	r5, r8
│ │  	add.w	r0, r0, r0, lsl #20
│ │  	b.n	2bd21a <uniffi_pbcli_checksum_method_api_base@@Base+0x150996>
│ │  	movs	r5, r0
│ │  	b.n	2bce1e <uniffi_pbcli_checksum_method_api_base@@Base+0x15059a>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, r2, r5, r6, sl, fp, ip, sp, pc}
│ │ -	vmlal.u16	q13, d11, d18
│ │ +	vmul.i16	q13, <illegal reg q5.5>, d1[1]
│ │  			@ <UNDEFINED> instruction: 0xffdd4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2bd00c <uniffi_pbcli_checksum_method_api_base@@Base+0x150788>
│ │  	beq.n	2bcb14 <uniffi_pbcli_checksum_method_api_base@@Base+0x150290>
│ │  	b.n	2bcf90 <uniffi_pbcli_checksum_method_api_base@@Base+0x15070c>
│ │  	str	r0, [r0, r0]
│ │  	b.n	2bce3a <uniffi_pbcli_checksum_method_api_base@@Base+0x1505b6>
│ │ @@ -625634,19 +625634,19 @@
│ │  	movs	r0, #0
│ │  	b.n	2bd3ee <uniffi_pbcli_checksum_method_api_base@@Base+0x150b6a>
│ │  	ldr	r1, [r6, #12]
│ │  	add.w	r0, r0, r4
│ │  	b.n	2bcff6 <uniffi_pbcli_checksum_method_api_base@@Base+0x150772>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r4, r8, r9, fp, ip, sp, pc}
│ │ -	vmlsl.u16	<illegal reg q10.5>, d11, d23
│ │ +	vmull.u16	<illegal reg q10.5>, d11, d6[1]
│ │  	vmull.u16	<illegal reg q13.5>, d30, d1[0]
│ │ -			@ <UNDEFINED> instruction: 0xffdb59d7
│ │ +			@ <UNDEFINED> instruction: 0xffdb59fe
│ │  			@ <UNDEFINED> instruction: 0xffdeba79
│ │ -			@ <UNDEFINED> instruction: 0xffdb598f
│ │ +			@ <UNDEFINED> instruction: 0xffdb59b6
│ │  			@ <UNDEFINED> instruction: 0xffde4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2bd1f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x150970>
│ │  	beq.n	2bccec <uniffi_pbcli_checksum_method_api_base@@Base+0x150468>
│ │  	b.n	2bd178 <uniffi_pbcli_checksum_method_api_base@@Base+0x1508f4>
│ │  	str	r1, [r0, #0]
│ │  	b.n	2bd022 <uniffi_pbcli_checksum_method_api_base@@Base+0x15079e>
│ │ @@ -626045,17 +626045,17 @@
│ │  	b.n	2bcb66 <uniffi_pbcli_checksum_method_api_base@@Base+0x1502e2>
│ │  	movs	r7, r0
│ │  	b.n	2bd3a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x150b1e>
│ │  	beq.n	2bd084 <uniffi_pbcli_checksum_method_api_base@@Base+0x150800>
│ │  	b.n	2bd4fc <uniffi_pbcli_checksum_method_api_base@@Base+0x150c78>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r2, r3, r4, r8, r9, sl, ip, sp, pc}
│ │ -	vrshr.u64	q13, q9, #37
│ │ +	vrsra.u16	d26, d9, #5
│ │  			@ <UNDEFINED> instruction: 0xffddb749
│ │ -	vrsra.u16	d26, d14, #5
│ │ +			@ <UNDEFINED> instruction: 0xffdba345
│ │  			@ <UNDEFINED> instruction: 0xffdd4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2bd59c <uniffi_pbcli_checksum_method_api_base@@Base+0x150d18>
│ │  	beq.n	2bd0b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x150830>
│ │  	b.n	2bd520 <uniffi_pbcli_checksum_method_api_base@@Base+0x150c9c>
│ │  	str	r3, [r0, r0]
│ │  	b.n	2bd3ca <uniffi_pbcli_checksum_method_api_base@@Base+0x150b46>
│ │ @@ -626230,17 +626230,17 @@
│ │  	ands	r0, r0
│ │  	b.n	2bd952 <uniffi_pbcli_checksum_method_api_base@@Base+0x1510ce>
│ │  	str	r0, [r3, #120]	@ 0x78
│ │  	add.w	r0, r0, r4
│ │  	b.n	2bd55a <uniffi_pbcli_checksum_method_api_base@@Base+0x150cd6>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r0, r1, r2, r4, r5, r6, r8, r9, sl, fp, ip, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffdc3dad
│ │ +			@ <UNDEFINED> instruction: 0xffdc3dd4
│ │  			@ <UNDEFINED> instruction: 0xffde5f93
│ │ -	vqrdmulh.s16	<illegal reg q9.5>, q14, d1[1]
│ │ +			@ <UNDEFINED> instruction: 0xffdc3df0
│ │  			@ <UNDEFINED> instruction: 0xffde4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2bd750 <uniffi_pbcli_checksum_method_api_base@@Base+0x150ecc>
│ │  	beq.n	2bd258 <uniffi_pbcli_checksum_method_api_base@@Base+0x1509d4>
│ │  	b.n	2bd6d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x150e50>
│ │  	ands	r0, r0
│ │  	b.n	2bd97e <uniffi_pbcli_checksum_method_api_base@@Base+0x1510fa>
│ │ @@ -626368,16 +626368,16 @@
│ │  	b.n	2bd468 <uniffi_pbcli_checksum_method_api_base@@Base+0x150be4>
│ │  	strh	r2, [r3, #30]
│ │  	add.w	r0, r1, r0, lsl #16
│ │  	b.n	2bda92 <uniffi_pbcli_checksum_method_api_base@@Base+0x15120e>
│ │  	ands	r0, r0
│ │  	b.n	2bce64 <uniffi_pbcli_checksum_method_api_base@@Base+0x1505e0>
│ │  			@ <UNDEFINED> instruction: 0xffceeaff
│ │ -	ldrh	r6, [r7, #8]
│ │ -	vrshr.u64	d21, d6, #35
│ │ +	ldrh	r5, [r4, #10]
│ │ +	vrshr.u64	d21, d29, #35
│ │  	vmull.p<illegal width 16>	<illegal reg q10.5>, d14, d23
│ │  			@ <UNDEFINED> instruction: 0xffdc4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2bd888 <uniffi_pbcli_checksum_method_api_base@@Base+0x151004>
│ │  	str	r1, [r0, #0]
│ │  	b.n	2bd6b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x150e2e>
│ │  	asrs	r0, r1, #5
│ │ @@ -626525,15 +626525,15 @@
│ │  	b.n	2bdbfa <uniffi_pbcli_checksum_method_api_base@@Base+0x151376>
│ │  	movs	r4, r0
│ │  	b.n	2bd7fe <uniffi_pbcli_checksum_method_api_base@@Base+0x150f7a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r5, r6, r7, r8, sl, fp, ip, lr}
│ │  			@ <UNDEFINED> instruction: 0xffdc5d8f
│ │  			@ <UNDEFINED> instruction: 0xffdc5cdf
│ │ -	vrshr.u64	d27, d19, #36
│ │ +	vrshr.u64	<illegal reg q13.5>, q5, #36
│ │  			@ <UNDEFINED> instruction: 0xffdd4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2bd9f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x151170>
│ │  	beq.n	2bd4e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x150c60>
│ │  	b.n	2bd978 <uniffi_pbcli_checksum_method_api_base@@Base+0x1510f4>
│ │  	strh	r0, [r1, #0]
│ │  	b.n	2bd018 <uniffi_pbcli_checksum_method_api_base@@Base+0x150794>
│ │ @@ -626888,21 +626888,21 @@
│ │  	b.n	2bdf22 <uniffi_pbcli_checksum_method_api_base@@Base+0x15169e>
│ │  	movs	r0, r0
│ │  	b.n	2bda90 <uniffi_pbcli_checksum_method_api_base@@Base+0x15120c>
│ │  	movs	r0, #56	@ 0x38
│ │  	lsls	r0, r0, #12
│ │  	vpmin.u<illegal width 64>	q15, <illegal reg q14.5>, <illegal reg q15.5>
│ │  	ldrh	r7, [r4, r0]
│ │ -	vrsubhn.i32	d24, q14, q6
│ │ +	vqshlu.s64	d24, d19, #28
│ │  	vmull.u16	<illegal reg q10.5>, d13, d3
│ │ -	vmul.i16	q12, q6, d0[3]
│ │ +	vmlal.u16	q12, d28, d15
│ │  			@ <UNDEFINED> instruction: 0xffdd5b33
│ │ -	vqshl.u64	d24, d8, #28
│ │ +	vqshl.u64	d24, d31, #28
│ │  			@ <UNDEFINED> instruction: 0xffdd5a73
│ │ -	vqshlu.s64	q12, q4, #28
│ │ +	vqshlu.s64	q12, <illegal reg q15.5>, #28
│ │  			@ <UNDEFINED> instruction: 0xffdd48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2bdd30 <uniffi_pbcli_checksum_method_api_base@@Base+0x1514ac>
│ │  	beq.n	2bd848 <uniffi_pbcli_checksum_method_api_base@@Base+0x150fc4>
│ │  	b.n	2bdcb4 <uniffi_pbcli_checksum_method_api_base@@Base+0x151430>
│ │  	ands	r2, r0
│ │  	b.n	2bdb5e <uniffi_pbcli_checksum_method_api_base@@Base+0x1512da>
│ │ @@ -627305,15 +627305,15 @@
│ │  	lsls	r1, r6, #24
│ │  	add.w	r0, r0, r1, lsl #28
│ │  	b.n	2be2ee <uniffi_pbcli_checksum_method_api_base@@Base+0x151a6a>
│ │  	vpmin.u32	q15, q10, <illegal reg q15.5>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	2be2f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x151a72>
│ │  	vpmin.u32	q15, q9, <illegal reg q15.5>
│ │ -	bls.n	2bdc8e <uniffi_pbcli_checksum_method_api_base@@Base+0x15140a>
│ │ +	bls.n	2bdadc <uniffi_pbcli_checksum_method_api_base@@Base+0x151258>
│ │  	vsri.64	d25, d24, #35
│ │  			@ <UNDEFINED> instruction: 0xffde48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2be0e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x151860>
│ │  	beq.n	2bdc2c <uniffi_pbcli_checksum_method_api_base@@Base+0x1513a8>
│ │  	b.n	2be068 <uniffi_pbcli_checksum_method_api_base@@Base+0x1517e4>
│ │  	str	r0, [r0, r0]
│ │ @@ -636534,15 +636534,15 @@
│ │  	ldrsh	r0, [r1, r1]
│ │  	add.w	r0, r0, r4
│ │  	b.n	2c290e <uniffi_pbcli_checksum_method_api_base@@Base+0x15608a>
│ │  	beq.n	2c2608 <uniffi_pbcli_checksum_method_api_base@@Base+0x155d84>
│ │  	b.n	2c2a68 <uniffi_pbcli_checksum_method_api_base@@Base+0x1561e4>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r2, r3, r4, r8, sl, fp, sp}
│ │ -	vqrdmlah.s32	q12, <illegal reg q8.5>, d13[0]
│ │ +			@ <UNDEFINED> instruction: 0xffe18ef4
│ │  			@ <UNDEFINED> instruction: 0xffdd4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2c2b00 <uniffi_pbcli_checksum_method_api_base@@Base+0x15627c>
│ │  	svc	87	@ 0x57
│ │  	b.n	2c2a84 <uniffi_pbcli_checksum_method_api_base@@Base+0x156200>
│ │  	blt.n	2c25f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x155d6c>
│ │  	b.n	2c2a88 <uniffi_pbcli_checksum_method_api_base@@Base+0x156204>
│ │ @@ -638678,15 +638678,15 @@
│ │  	and.w	r0, r0, r0, lsl #20
│ │  	b.n	2c3f16 <uniffi_pbcli_checksum_method_api_base@@Base+0x157692>
│ │  	movs	r5, r0
│ │  	b.n	2c3b1a <uniffi_pbcli_checksum_method_api_base@@Base+0x157296>
│ │  	beq.n	2c380c <uniffi_pbcli_checksum_method_api_base@@Base+0x156f88>
│ │  	b.n	2c3c74 <uniffi_pbcli_checksum_method_api_base@@Base+0x1573f0>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r5, r6, r8, r9, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r3, r7, r8, r9, fp, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffdd4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2c3d08 <uniffi_pbcli_checksum_method_api_base@@Base+0x157484>
│ │  	svc	139	@ 0x8b
│ │  	b.n	2c3c8c <uniffi_pbcli_checksum_method_api_base@@Base+0x157408>
│ │  	lsrs	r5, r1, #8
│ │  	orn	r0, r1, #516	@ 0x204
│ │ @@ -659036,23 +659036,23 @@
│ │  	b.n	2ce95a <uniffi_pbcli_checksum_method_api_base@@Base+0x1620d6>
│ │  	movs	r1, r7
│ │  	b.n	2ce95e <uniffi_pbcli_checksum_method_api_base@@Base+0x1620da>
│ │  	asrs	r4, r4, #2
│ │  	b.n	2ce962 <uniffi_pbcli_checksum_method_api_base@@Base+0x1620de>
│ │  			@ <UNDEFINED> instruction: 0xffb9eaff
│ │  	str	r7, [r1, r2]
│ │ -			@ <UNDEFINED> instruction: 0xffdbbc3c
│ │ +	vqdmulh.s16	<illegal reg q13.5>, <illegal reg q5.5>, d3[2]
│ │  			@ <UNDEFINED> instruction: 0xffdc4ff7
│ │ -			@ <UNDEFINED> instruction: 0xffdbbba4
│ │ +			@ <UNDEFINED> instruction: 0xffdbbbcb
│ │  	vaddl.u16	<illegal reg q10.5>, d12, d19
│ │ -			@ <UNDEFINED> instruction: 0xffdbbbd0
│ │ +			@ <UNDEFINED> instruction: 0xffdbbbf7
│ │  			@ <UNDEFINED> instruction: 0xffdc4faf
│ │ -			@ <UNDEFINED> instruction: 0xffdbbb5c
│ │ +			@ <UNDEFINED> instruction: 0xffdbbb83
│ │  			@ <UNDEFINED> instruction: 0xffdc4f7b
│ │ -			@ <UNDEFINED> instruction: 0xffdbbb28
│ │ +			@ <UNDEFINED> instruction: 0xffdbbb4f
│ │  			@ <UNDEFINED> instruction: 0xffdc4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2ce770 <uniffi_pbcli_checksum_method_api_base@@Base+0x161eec>
│ │  	beq.n	2ce2c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x161a3c>
│ │  	b.n	2ce6f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x161e70>
│ │  	movs	r0, r0
│ │  	b.n	2ce900 <uniffi_pbcli_checksum_method_api_base@@Base+0x16207c>
│ │ @@ -659314,19 +659314,19 @@
│ │  			@ <UNDEFINED> instruction: 0xeaff6000
│ │  	b.n	2cebda <uniffi_pbcli_checksum_method_api_base@@Base+0x162356>
│ │  			@ <UNDEFINED> instruction: 0xff90eaff
│ │  	ldr	r6, [pc, #360]	@ (2ce608 <uniffi_pbcli_checksum_method_api_base@@Base+0x161d84>)
│ │  	vmlsl.u16	<illegal reg q9.5>, d28, d2[0]
│ │  			@ <UNDEFINED> instruction: 0xffdb4e92
│ │  	vqshlu.s64	<illegal reg q9.5>, q13, #28
│ │ -	vaddw.u16	<illegal reg q14.5>, <illegal reg q5.5>, d5
│ │ -	vshr.u64	d29, d6, #36
│ │ +	vaddw.u16	<illegal reg q14.5>, <illegal reg q5.5>, d28
│ │ +	vshr.u64	d29, d29, #36
│ │  	vsli.16	d29, d23, #12
│ │ -	vaddw.u16	<illegal reg q8.5>, q5, d2
│ │ -			@ <UNDEFINED> instruction: 0xffddfdbd
│ │ +	vaddw.u16	<illegal reg q8.5>, q5, d25
│ │ +	vqrdmulh.s16	<illegal reg q15.5>, <illegal reg q14.5>, d4[2]
│ │  			@ <UNDEFINED> instruction: 0xffdc1dd3
│ │  	vqdmulh.s16	q10, <illegal reg q13.5>, d2[3]
│ │  	vsli.16	<illegal reg q9.5>, q1, #12
│ │  	vabal.u16	q11, d11, d22
│ │  	vaddl.u16	q8, d11, d0
│ │  	b.n	2ceb76 <uniffi_pbcli_checksum_method_api_base@@Base+0x1622f2>
│ │  	movs	r4, r1
│ │ @@ -659880,16 +659880,16 @@
│ │  	b.n	2cf0c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x162842>
│ │  	vpmin.u<illegal width 64>	q15, <illegal reg q14.5>, <illegal reg q15.5>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	2ce4c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x161c44>
│ │  	vpmin.u<illegal width 64>	q15, <illegal reg q13.5>, <illegal reg q15.5>
│ │  	movs	r2, #161	@ 0xa1
│ │  			@ <UNDEFINED> instruction: 0xeb00ff79
│ │ -			@ <UNDEFINED> instruction: 0xeaff9dc8
│ │ -			@ <UNDEFINED> instruction: 0xffdcce3c
│ │ +			@ <UNDEFINED> instruction: 0xeaff9def
│ │ +	vqrdmlah.s16	q14, q6, d3[2]
│ │  	vabal.u16	q8, d12, d30
│ │  	vsra.u16	q14, q3, #5
│ │  	vmul.f16	q10, <illegal reg q13.5>, d2[2]
│ │  	vmul.f16	<illegal reg q13.5>, q6, d4[2]
│ │  			@ <UNDEFINED> instruction: 0xffda49be
│ │  	vmul.f16	<illegal reg q13.5>, q6, d0[0]
│ │  	vmull.u16	q15, d26, d4[1]
│ │ @@ -660014,15 +660014,15 @@
│ │  	ands	r0, r0
│ │  	b.n	2cf20e <uniffi_pbcli_checksum_method_api_base@@Base+0x16298a>
│ │  	movs	r1, #105	@ 0x69
│ │  	add.w	r0, r0, r4
│ │  	b.n	2cee16 <uniffi_pbcli_checksum_method_api_base@@Base+0x162592>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r1, r3, r5, r6, r9, sl, lr}
│ │ -	vmul.i16	q12, q6, d1[1]
│ │ +	vqrshrun.s32	d24, q8, #4
│ │  			@ <UNDEFINED> instruction: 0xffdc4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2cf004 <uniffi_pbcli_checksum_method_api_base@@Base+0x162780>
│ │  	movs	r0, r0
│ │  	b.n	2cf18e <uniffi_pbcli_checksum_method_api_base@@Base+0x16290a>
│ │  	asrs	r0, r0, #32
│ │  	asrs	r0, r0, #22
│ │ @@ -660344,18 +660344,18 @@
│ │  			@ <UNDEFINED> instruction: 0xeb00ffee
│ │  			@ <UNDEFINED> instruction: 0xeaff4376
│ │  	vmlsl.u16	q15, d12, d4[3]
│ │  	vsli.16	q10, q5, #11
│ │  	vraddhn.i32	d20, q14, q7
│ │  	vabdl.u16	q15, d28, d4
│ │  	vqshlu.s16	q15, <illegal reg q11.5>, #11
│ │ -	vqshl.u16	d24, d8, #10
│ │ +	vqshl.u16	d24, d31, #10
│ │  	vmls.i16	q10, q6, d2[1]
│ │  			@ <UNDEFINED> instruction: 0xffdce740
│ │ -	vqshrn.u32	d19, <illegal reg q13.5>, #5
│ │ +	vmul.f16	<illegal reg q9.5>, <illegal reg q5.5>, d2[2]
│ │  	vqrdmulh.s16	<illegal reg q10.5>, <illegal reg q6.5>, d4[2]
│ │  	vrsra.u64	q10, q11, #37
│ │  	vmlsl.u16	q15, d28, d4[3]
│ │  	vrsra.u64	d20, d10, #37
│ │  	vaddl.u16	q8, d12, d0
│ │  	b.n	2cf4a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x162c22>
│ │  	vrhadd.u16	d0, d14, d31
│ │ @@ -660504,17 +660504,17 @@
│ │  	add.w	r0, r1, r0, lsl #16
│ │  	b.n	2cf69e <uniffi_pbcli_checksum_method_api_base@@Base+0x162e1a>
│ │  	movs	r4, r0
│ │  	b.n	2cf2a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x162a1e>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r1, r2, r3, r4, r7, r9, lr}
│ │  	vsubl.u16	q10, d12, d30
│ │ -			@ <UNDEFINED> instruction: 0xffdc6ef8
│ │ +			@ <UNDEFINED> instruction: 0xffdc6f1f
│ │  	vsra.u64	q10, q13, #36
│ │ -	vqrdmlah.s16	q11, q14, d4[0]
│ │ +	vqrdmlah.s16	q11, q14, d3[3]
│ │  	vmla.f16	q10, q14, d6[0]
│ │  	vqshrun.s32	d20, q8, #4
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2cf4a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x162c1c>
│ │  	str	r0, [r0, r0]
│ │  	b.n	2cf2ca <uniffi_pbcli_checksum_method_api_base@@Base+0x162a46>
│ │  	movs	r4, r1
│ │ @@ -661061,15 +661061,15 @@
│ │  	ands	r0, r0
│ │  	b.n	2cfb9e <uniffi_pbcli_checksum_method_api_base@@Base+0x16331a>
│ │  	subs	r5, r0, #4
│ │  	add.w	r0, r0, r4
│ │  	b.n	2cf7a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x162f22>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r1, r3, r4, r6, r7, sl, fp, ip, sp}
│ │ -	vqshl.u64	<illegal reg q14.5>, q5, #28
│ │ +	vmlal.u16	<illegal reg q14.5>, d12, d1
│ │  			@ <UNDEFINED> instruction: 0xffdc4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2cf994 <uniffi_pbcli_checksum_method_api_base@@Base+0x163110>
│ │  	movs	r0, r0
│ │  	b.n	2cfb1e <uniffi_pbcli_checksum_method_api_base@@Base+0x16329a>
│ │  	asrs	r0, r3, #32
│ │  	asrs	r0, r0, #22
│ │ @@ -661139,15 +661139,15 @@
│ │  	ands	r0, r0
│ │  	b.n	2cfc56 <uniffi_pbcli_checksum_method_api_base@@Base+0x1633d2>
│ │  	subs	r7, r2, #3
│ │  	add.w	r0, r0, r4
│ │  	b.n	2cf85e <uniffi_pbcli_checksum_method_api_base@@Base+0x162fda>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r1, r5, sl, fp, ip, sp}
│ │ -	vmull.u16	<illegal reg q8.5>, d28, d2[1]
│ │ +			@ <UNDEFINED> instruction: 0xffdc1af1
│ │  	vaddl.u16	q8, d13, d0
│ │  	b.n	2cfbce <uniffi_pbcli_checksum_method_api_base@@Base+0x16334a>
│ │  	movs	r0, r2
│ │  	asrs	r0, r2, #22
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -661352,15 +661352,15 @@
│ │  	b.n	2cfe2a <uniffi_pbcli_checksum_method_api_base@@Base+0x1635a6>
│ │  			@ <UNDEFINED> instruction: 0xffb6eaff
│ │  	movs	r0, r0
│ │  	b.n	2cfda2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16351e>
│ │  	ands	r0, r1
│ │  	stmia	r1!, {r5, r7}
│ │  			@ <UNDEFINED> instruction: 0xffb3eaff
│ │ -	str	r0, [sp, #848]	@ 0x350
│ │ +	str	r0, [sp, #1004]	@ 0x3ec
│ │  	vaddl.u16	q8, d12, d0
│ │  	b.n	2cfe42 <uniffi_pbcli_checksum_method_api_base@@Base+0x1635be>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r7, [pc, #960]	@ (2cfac8 <uniffi_pbcli_checksum_method_api_base@@Base+0x163244>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2cfc28 <uniffi_pbcli_checksum_method_api_base@@Base+0x1633a4>
│ │  	beq.n	2cf728 <uniffi_pbcli_checksum_method_api_base@@Base+0x162ea4>
│ │ @@ -661594,15 +661594,15 @@
│ │  	movs	r2, r1
│ │  	b.n	2cf9f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16316e>
│ │  	movs	r0, r0
│ │  	b.n	2cff96 <uniffi_pbcli_checksum_method_api_base@@Base+0x163712>
│ │  	str	r0, [r0, #0]
│ │  	stmia	r1!, {r5, r7}
│ │  			@ <UNDEFINED> instruction: 0xff8feaff
│ │ -	ldrh	r4, [r4, #56]	@ 0x38
│ │ +	ldrh	r3, [r1, #58]	@ 0x3a
│ │  			@ <UNDEFINED> instruction: 0xffdc4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2cfe24 <uniffi_pbcli_checksum_method_api_base@@Base+0x1635a0>
│ │  	b.n	2cf95c <uniffi_pbcli_checksum_method_api_base@@Base+0x1630d8>
│ │  	b.n	2cf42e <uniffi_pbcli_checksum_method_api_base@@Base+0x162baa>
│ │  	stmia	r0!, {}
│ │  	b.n	2cfc52 <uniffi_pbcli_checksum_method_api_base@@Base+0x1633ce>
│ │ @@ -661779,17 +661779,17 @@
│ │  	b.n	2d01ca <uniffi_pbcli_checksum_method_api_base@@Base+0x163946>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2cfbac <uniffi_pbcli_checksum_method_api_base@@Base+0x163328>
│ │  	adds	r5, #14
│ │  	add.w	r0, r1, r4
│ │  	b.n	2cfdd6 <uniffi_pbcli_checksum_method_api_base@@Base+0x163552>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r2, r4, r5, r8, sl, fp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffdc8d10
│ │ -	vqdmulh.s16	q12, q14, d4[1]
│ │ +	ldmia.w	sp!, {r0, r1, r3, r4, r6, r8, sl, fp, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffdc8d37
│ │ +			@ <UNDEFINED> instruction: 0xffdc8cf3
│ │  	vaddl.u16	q8, d12, d0
│ │  	b.n	2d014a <uniffi_pbcli_checksum_method_api_base@@Base+0x1638c6>
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (2cfb74 <uniffi_pbcli_checksum_method_api_base@@Base+0x1632f0>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │ @@ -661823,15 +661823,15 @@
│ │  	movs	r4, r2
│ │  	b.n	2cf5fe <uniffi_pbcli_checksum_method_api_base@@Base+0x162d7a>
│ │  	movs	r0, r5
│ │  	b.n	2cf602 <uniffi_pbcli_checksum_method_api_base@@Base+0x162d7e>
│ │  	movs	r1, r0
│ │  	b.n	2d023e <uniffi_pbcli_checksum_method_api_base@@Base+0x1639ba>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r3, r7, sl, fp, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r5, r7, sl, fp, pc}
│ │  	vaddl.u16	q8, d12, d28
│ │  	b.n	2cf62a <uniffi_pbcli_checksum_method_api_base@@Base+0x162da6>
│ │  	movs	r0, r0
│ │  	b.n	2d01ae <uniffi_pbcli_checksum_method_api_base@@Base+0x16392a>
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │ @@ -662183,15 +662183,15 @@
│ │  	b.n	2d0196 <uniffi_pbcli_checksum_method_api_base@@Base+0x163912>
│ │  	asrs	r5, r0, #32
│ │  	b.n	2d019a <uniffi_pbcli_checksum_method_api_base@@Base+0x163916>
│ │  	movs	r0, #64	@ 0x40
│ │  	b.n	2d059e <uniffi_pbcli_checksum_method_api_base@@Base+0x163d1a>
│ │  	ldr	r0, [pc, #192]	@ (2cff20 <uniffi_pbcli_checksum_method_api_base@@Base+0x16369c>)
│ │  	ldmia.w	sp!, {r0, r3, r4, sl, ip, sp}
│ │ -			@ <UNDEFINED> instruction: 0xea01b616
│ │ +			@ <UNDEFINED> instruction: 0xea01b63d
│ │  			@ <UNDEFINED> instruction: 0xffdc4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2d038c <uniffi_pbcli_checksum_method_api_base@@Base+0x163b08>
│ │  	beq.n	2cfe7c <uniffi_pbcli_checksum_method_api_base@@Base+0x1635f8>
│ │  	b.n	2d0310 <uniffi_pbcli_checksum_method_api_base@@Base+0x163a8c>
│ │  	str	r0, [r0, #0]
│ │  	b.n	2d01ba <uniffi_pbcli_checksum_method_api_base@@Base+0x163936>
│ │ @@ -662586,19 +662586,19 @@
│ │  	beq.n	2d0240 <uniffi_pbcli_checksum_method_api_base@@Base+0x1639bc>
│ │  	b.n	2d06a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x163e1c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r2}
│ │  	b.n	2d0552 <uniffi_pbcli_checksum_method_api_base@@Base+0x163cce>
│ │  	mrc2	11, 7, lr, cr3, cr15, {7}	@ <UNPREDICTABLE>
│ │  			@ <UNDEFINED> instruction: 0xfff9eaff
│ │ -	push	{r1, r2, r3, r5, r7, lr}
│ │ -	vsubw.u16	<illegal reg q13.5>, q14, d10
│ │ -	vrshr.u16	<illegal reg q13.5>, q11, #4
│ │ -	vmlal.u16	<illegal reg q13.5>, d28, d2[3]
│ │ -	vsubl.u16	<illegal reg q13.5>, d28, d30
│ │ +	push	{r0, r2, r4, r6, r7, lr}
│ │ +	vrsra.u64	d27, d17, #36
│ │ +	vrshr.u64	d27, d13, #36
│ │ +	vrsra.u16	d27, d1, #4
│ │ +	vrshr.u64	<illegal reg q13.5>, <illegal reg q2.5>, #36
│ │  	vsli.64	d24, d14, #28
│ │  			@ <UNDEFINED> instruction: 0xffda4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2d0754 <uniffi_pbcli_checksum_method_api_base@@Base+0x163ed0>
│ │  	beq.n	2d02b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x163a30>
│ │  	b.n	2d06d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x163e54>
│ │  	str	r0, [r0, #0]
│ │ @@ -662880,27 +662880,27 @@
│ │  			@ <UNDEFINED> instruction: 0xeb008020
│ │  	b.n	2cfed4 <uniffi_pbcli_checksum_method_api_base@@Base+0x163650>
│ │  	movs	r0, r1
│ │  	b.n	2d07e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x163f5e>
│ │  	beq.n	2d04dc <uniffi_pbcli_checksum_method_api_base@@Base+0x163c58>
│ │  	b.n	2d093c <uniffi_pbcli_checksum_method_api_base@@Base+0x1640b8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r5, r9, ip, sp, lr, pc}
│ │ -	vsra.u64	d27, d22, #36
│ │ +	ldmia.w	sp!, {r0, r2, r5, r6, r9, ip, sp, lr, pc}
│ │ +	vsra.u64	<illegal reg q13.5>, <illegal reg q6.5>, #36
│ │  	vmls.f16	<illegal reg q8.5>, q14, d1[2]
│ │  	vqshl.u16	d23, d0, #12
│ │  	movs	r5, r3
│ │  	lsrs	r4, r7, #2
│ │  	movs	r0, r0
│ │  	lsrs	r0, r2, #3
│ │  	movs	r0, r0
│ │ -	add	sp, #8
│ │ +	add	sp, #164	@ 0xa4
│ │  	vraddhn.i32	d17, q6, <illegal reg q14.5>
│ │ -			@ <UNDEFINED> instruction: 0xffdc6edd
│ │ -	vsubw.u16	q12, q6, d5
│ │ +			@ <UNDEFINED> instruction: 0xffdc6f04
│ │ +	vsubw.u16	q12, q6, d28
│ │  	vmlal.u16	q10, d12, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2d081a <uniffi_pbcli_checksum_method_api_base@@Base+0x163f96>
│ │  	asrs	r3, r1, #32
│ │  	b.n	2d0c1e <uniffi_pbcli_checksum_method_api_base@@Base+0x16439a>
│ │  	lsls	r2, r7, #7
│ │  	add.w	r0, r1, r0
│ │ @@ -662963,15 +662963,15 @@
│ │  	b.n	2d0cae <uniffi_pbcli_checksum_method_api_base@@Base+0x16442a>
│ │  	ands	r0, r0
│ │  	b.n	2d0cb2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16442e>
│ │  	subs	r0, r0, r3
│ │  	add.w	r0, r0, r4
│ │  	b.n	2d08ba <uniffi_pbcli_checksum_method_api_base@@Base+0x164036>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r1, r3, r4, r5, r6, r7, r9, sl, fp, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r5, r8, r9, sl, fp, sp, pc}
│ │  	vmls.i16	q10, q6, d6[1]
│ │  			@ <UNDEFINED> instruction: 0xffdb4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2d0aa8 <uniffi_pbcli_checksum_method_api_base@@Base+0x164224>
│ │  	movs	r0, r0
│ │  	b.n	2d0c32 <uniffi_pbcli_checksum_method_api_base@@Base+0x1643ae>
│ │  	movs	r4, r1
│ │ @@ -663002,15 +663002,15 @@
│ │  	b.n	2d0d0a <uniffi_pbcli_checksum_method_api_base@@Base+0x164486>
│ │  	ands	r0, r0
│ │  	b.n	2d0d0e <uniffi_pbcli_checksum_method_api_base@@Base+0x16448a>
│ │  	subs	r1, r5, r2
│ │  	add.w	r0, r0, r4
│ │  	b.n	2d0916 <uniffi_pbcli_checksum_method_api_base@@Base+0x164092>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r7, r9, sl, fp, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r6, r7, r9, sl, fp, sp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffdc13e8
│ │  			@ <UNDEFINED> instruction: 0xffdb4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2d0b04 <uniffi_pbcli_checksum_method_api_base@@Base+0x164280>
│ │  	movs	r0, r0
│ │  	b.n	2d0c8e <uniffi_pbcli_checksum_method_api_base@@Base+0x16440a>
│ │  	movs	r0, r2
│ │ @@ -663039,15 +663039,15 @@
│ │  	b.n	2d0d62 <uniffi_pbcli_checksum_method_api_base@@Base+0x1644de>
│ │  	ands	r0, r0
│ │  	b.n	2d0d66 <uniffi_pbcli_checksum_method_api_base@@Base+0x1644e2>
│ │  	subs	r3, r2, r2
│ │  	add.w	r0, r0, r4
│ │  	b.n	2d096e <uniffi_pbcli_checksum_method_api_base@@Base+0x1640ea>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r1, r2, r6, r9, sl, fp, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r5, r6, r9, sl, fp, sp, pc}
│ │  	vsubl.u16	<illegal reg q11.5>, d28, d10
│ │  	vaddl.u16	q8, d11, d8
│ │  	b.n	2d015e <uniffi_pbcli_checksum_method_api_base@@Base+0x1638da>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (2d0704 <uniffi_pbcli_checksum_method_api_base@@Base+0x163e80>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2d0b64 <uniffi_pbcli_checksum_method_api_base@@Base+0x1642e0>
│ │ @@ -663144,16 +663144,16 @@
│ │  	b.n	2d09f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x164174>
│ │  	lsls	r0, r4, #10
│ │  	b.n	2d0a5e <uniffi_pbcli_checksum_method_api_base@@Base+0x1641da>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	2d0e66 <uniffi_pbcli_checksum_method_api_base@@Base+0x1645e2>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r4, r7, r8, sl, fp, sp, pc}
│ │ -	vqdmulh.s16	q11, q6, d5[3]
│ │ +	ldmia.w	sp!, {r0, r3, r4, r5, r7, r8, sl, fp, sp, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffdc6c94
│ │  			@ <UNDEFINED> instruction: 0xffdc4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2d0c54 <uniffi_pbcli_checksum_method_api_base@@Base+0x1643d0>
│ │  	beq.n	2d077c <uniffi_pbcli_checksum_method_api_base@@Base+0x163ef8>
│ │  	b.n	2d0bd8 <uniffi_pbcli_checksum_method_api_base@@Base+0x164354>
│ │  	ands	r0, r0
│ │  	b.n	2d0a82 <uniffi_pbcli_checksum_method_api_base@@Base+0x1641fe>
│ │ @@ -663229,15 +663229,15 @@
│ │  	movs	r4, r6
│ │  	b.n	2d0f1e <uniffi_pbcli_checksum_method_api_base@@Base+0x16469a>
│ │  	movs	r2, #114	@ 0x72
│ │  	b.n	2d0de2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16455e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2d0904 <uniffi_pbcli_checksum_method_api_base@@Base+0x164080>
│ │  	adds	r0, #222	@ 0xde
│ │ -			@ <UNDEFINED> instruction: 0xea01ac6a
│ │ +			@ <UNDEFINED> instruction: 0xea01ac91
│ │  			@ <UNDEFINED> instruction: 0xffdc4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2d0d10 <uniffi_pbcli_checksum_method_api_base@@Base+0x16448c>
│ │  	beq.n	2d0800 <uniffi_pbcli_checksum_method_api_base@@Base+0x163f7c>
│ │  	b.n	2d0c94 <uniffi_pbcli_checksum_method_api_base@@Base+0x164410>
│ │  	movs	r0, r0
│ │  	b.n	2d0e9e <uniffi_pbcli_checksum_method_api_base@@Base+0x16461a>
│ │ @@ -663327,15 +663327,15 @@
│ │  	b.n	2d0ffa <uniffi_pbcli_checksum_method_api_base@@Base+0x164776>
│ │  	adds	r6, r5, r7
│ │  	add.w	r0, r0, r9
│ │  	b.n	2d0c02 <uniffi_pbcli_checksum_method_api_base@@Base+0x16437e>
│ │  	beq.n	2d08fc <uniffi_pbcli_checksum_method_api_base@@Base+0x164078>
│ │  	b.n	2d0d5c <uniffi_pbcli_checksum_method_api_base@@Base+0x1644d8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r4, r5, r7, r8, r9, fp, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r3, r4, r6, r7, r8, r9, fp, sp, pc}
│ │  	vmlal.u16	q15, d28, d5[1]
│ │  	vaddl.u16	q8, d10, d0
│ │  	b.n	2d0f76 <uniffi_pbcli_checksum_method_api_base@@Base+0x1646f2>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (2d091c <uniffi_pbcli_checksum_method_api_base@@Base+0x164098>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2d0dfc <uniffi_pbcli_checksum_method_api_base@@Base+0x164578>
│ │ @@ -663368,15 +663368,15 @@
│ │  	b.n	2d0f1e <uniffi_pbcli_checksum_method_api_base@@Base+0x16469a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2d0a40 <uniffi_pbcli_checksum_method_api_base@@Base+0x1641bc>
│ │  	ldr	r4, [pc, #64]	@ (2d0964 <uniffi_pbcli_checksum_method_api_base@@Base+0x1640e0>)
│ │  	ldmia.w	sp!, {r3, r5, r6, r8, ip, sp}
│ │  			@ <UNDEFINED> instruction: 0xea01caf0
│ │  	movs	r0, r4
│ │ -	add	r3, sp, #184	@ 0xb8
│ │ +	add	r3, sp, #340	@ 0x154
│ │  			@ <UNDEFINED> instruction: 0xffdc4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2d0e54 <uniffi_pbcli_checksum_method_api_base@@Base+0x1645d0>
│ │  	ands	r0, r0
│ │  	b.n	2d0c7e <uniffi_pbcli_checksum_method_api_base@@Base+0x1643fa>
│ │  	movs	r0, r2
│ │  	b.n	2d0462 <uniffi_pbcli_checksum_method_api_base@@Base+0x163bde>
│ │ @@ -663738,15 +663738,15 @@
│ │  	b.n	2d0fb2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16472e>
│ │  	asrs	r5, r0, #32
│ │  	b.n	2d0fb6 <uniffi_pbcli_checksum_method_api_base@@Base+0x164732>
│ │  	movs	r0, #64	@ 0x40
│ │  	b.n	2d13ba <uniffi_pbcli_checksum_method_api_base@@Base+0x164b36>
│ │  	ldr	r0, [pc, #192]	@ (2d0d3c <uniffi_pbcli_checksum_method_api_base@@Base+0x1644b8>)
│ │  	ldmia.w	sp!, {r1, r4, r7, ip, sp}
│ │ -			@ <UNDEFINED> instruction: 0xea01a7fa
│ │ +			@ <UNDEFINED> instruction: 0xea01a821
│ │  	vshr.u16	d16, d4, #4
│ │  	b.n	2d118a <uniffi_pbcli_checksum_method_api_base@@Base+0x164906>
│ │  	subs	r7, r3, #6
│ │  	b.n	2d0fae <uniffi_pbcli_checksum_method_api_base@@Base+0x16472a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2d1194 <uniffi_pbcli_checksum_method_api_base@@Base+0x164910>
│ │  	cmp	r7, #145	@ 0x91
│ │ @@ -663807,15 +663807,15 @@
│ │  	b.n	2d1056 <uniffi_pbcli_checksum_method_api_base@@Base+0x1647d2>
│ │  	asrs	r5, r0, #32
│ │  	b.n	2d105a <uniffi_pbcli_checksum_method_api_base@@Base+0x1647d6>
│ │  	movs	r0, #64	@ 0x40
│ │  	b.n	2d145e <uniffi_pbcli_checksum_method_api_base@@Base+0x164bda>
│ │  	ldr	r0, [pc, #192]	@ (2d0de0 <uniffi_pbcli_checksum_method_api_base@@Base+0x16455c>)
│ │  	ldmia.w	sp!, {r0, r3, r5, r6, ip, sp}
│ │ -			@ <UNDEFINED> instruction: 0xea01a756
│ │ +			@ <UNDEFINED> instruction: 0xea01a77d
│ │  	vshr.u16	d16, d12, #4
│ │  	b.n	2d122e <uniffi_pbcli_checksum_method_api_base@@Base+0x1649aa>
│ │  	ldr	r3, [pc, #872]	@ (2d1098 <uniffi_pbcli_checksum_method_api_base@@Base+0x164814>)
│ │  	and.w	r0, r1, ip, lsr #32
│ │  	b.n	2d1236 <uniffi_pbcli_checksum_method_api_base@@Base+0x1649b2>
│ │  	ldr	r4, [pc, #40]	@ (2d0d60 <uniffi_pbcli_checksum_method_api_base@@Base+0x1644dc>)
│ │  	and.w	ip, r1, r0, ror #17
│ │ @@ -663902,28 +663902,28 @@
│ │  	b.n	2d0f0c <uniffi_pbcli_checksum_method_api_base@@Base+0x164688>
│ │  	adds	r0, #54	@ 0x36
│ │  	add.w	r0, r1, r4
│ │  	b.n	2d1136 <uniffi_pbcli_checksum_method_api_base@@Base+0x1648b2>
│ │  	beq.n	2d0e18 <uniffi_pbcli_checksum_method_api_base@@Base+0x164594>
│ │  	b.n	2d1290 <uniffi_pbcli_checksum_method_api_base@@Base+0x164a0c>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r4, r5, r8, fp, ip}
│ │ +	ldmia.w	sp!, {r3, r4, r6, r8, fp, ip}
│ │  	vshr.u64	d16, d0, #35
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #4
│ │  	movs	r0, r0
│ │  	lsrs	r0, r1, #20
│ │  	movs	r0, r0
│ │  	lsrs	r4, r0, #20
│ │  	movs	r0, r0
│ │  	lsrs	r4, r0, #20
│ │  	movs	r0, r0
│ │  	lsrs	r4, r0, #20
│ │  	movs	r0, r0
│ │ -	adds	r1, r3, r2
│ │ +	adds	r0, r0, r3
│ │  			@ <UNDEFINED> instruction: 0xffdd48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2d1340 <uniffi_pbcli_checksum_method_api_base@@Base+0x164abc>
│ │  	ands	r0, r0
│ │  	b.n	2d116a <uniffi_pbcli_checksum_method_api_base@@Base+0x1648e6>
│ │  	movs	r0, r2
│ │  	b.n	2d094e <uniffi_pbcli_checksum_method_api_base@@Base+0x1640ca>
│ │ @@ -664150,15 +664150,15 @@
│ │  	b.n	2d175e <uniffi_pbcli_checksum_method_api_base@@Base+0x164eda>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2d1140 <uniffi_pbcli_checksum_method_api_base@@Base+0x1648bc>
│ │  	ldr	r4, [pc, #64]	@ (2d1064 <uniffi_pbcli_checksum_method_api_base@@Base+0x1647e0>)
│ │  	ldmia.w	sp!, {r3, r5, r7, r8, r9, sl, fp, sp}
│ │  	and.w	r0, r1, r0, rrx
│ │  	movs	r0, r0
│ │ -	asrs	r5, r4, #25
│ │ +	asrs	r4, r1, #26
│ │  	vaddl.u16	q8, d13, d0
│ │  	b.n	2d16d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x164e52>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (2d10fc <uniffi_pbcli_checksum_method_api_base@@Base+0x164878>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2d155c <uniffi_pbcli_checksum_method_api_base@@Base+0x164cd8>
│ │  	str	r0, [r4, r1]
│ │ @@ -664202,15 +664202,15 @@
│ │  	b.n	2d13da <uniffi_pbcli_checksum_method_api_base@@Base+0x164b56>
│ │  	asrs	r5, r0, #32
│ │  	b.n	2d13de <uniffi_pbcli_checksum_method_api_base@@Base+0x164b5a>
│ │  	movs	r2, #101	@ 0x65
│ │  	b.n	2d16a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x164e1e>
│ │  	ldr	r0, [pc, #192]	@ (2d1164 <uniffi_pbcli_checksum_method_api_base@@Base+0x1648e0>)
│ │  	ldmia.w	sp!, {r3, r7, r8, r9, sl, fp, sp}
│ │ -	and.w	r6, r1, r1, ror #4
│ │ +	and.w	r6, r1, r8, lsr #5
│ │  			@ <UNDEFINED> instruction: 0xffdd4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2d15d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x164d4c>
│ │  	asrs	r4, r2, #32
│ │  	b.n	2d17fa <uniffi_pbcli_checksum_method_api_base@@Base+0x164f76>
│ │  	vqrdmulh.s<illegal width 8>	d14, d3, d0
│ │  	movs	r0, r0
│ │ @@ -664267,16 +664267,16 @@
│ │  	b.n	2d1876 <uniffi_pbcli_checksum_method_api_base@@Base+0x164ff2>
│ │  	ands	r0, r0
│ │  	b.n	2d187a <uniffi_pbcli_checksum_method_api_base@@Base+0x164ff6>
│ │  	asrs	r6, r1, #31
│ │  	add.w	r0, r0, r4
│ │  	b.n	2d1482 <uniffi_pbcli_checksum_method_api_base@@Base+0x164bfe>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r3, r5, r6, r8, sl, ip}
│ │ -	vqshlu.s64	d30, d19, #29
│ │ +	ldmia.w	sp!, {r4, r7, r8, sl, ip}
│ │ +	vqshlu.s64	q15, q5, #29
│ │  	vqrdmlsh.s16	<illegal reg q15.5>, q6, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffff4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2d1674 <uniffi_pbcli_checksum_method_api_base@@Base+0x164df0>
│ │  	beq.n	2d1244 <uniffi_pbcli_checksum_method_api_base@@Base+0x1649c0>
│ │  	b.n	2d15f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x164d74>
│ │  	lsls	r0, r2, #1
│ │ @@ -665255,71 +665255,71 @@
│ │  	ldc2	11, cr14, [r3, #1020]	@ 0x3fc	@ <UNPREDICTABLE>
│ │  	movs	r7, r0
│ │  	b.n	2d1d26 <uniffi_pbcli_checksum_method_api_base@@Base+0x1654a2>
│ │  			@ <UNDEFINED> instruction: 0xfbb9ebff
│ │  	str	r0, [r0, #0]
│ │  	b.n	2d212e <uniffi_pbcli_checksum_method_api_base@@Base+0x1658aa>
│ │  			@ <UNDEFINED> instruction: 0xff9feaff
│ │ -	asrs	r5, r7, #10
│ │ -	vqrshrun.s32	d27, <illegal reg q8.5>, #3
│ │ -	vrshr.u64	d30, d5, #36
│ │ -	vrshr.u64	d17, d5, #36
│ │ -	vmul.i16	<illegal reg q13.5>, <illegal reg q6.5>, d1[1]
│ │ -	vshr.u64	d17, d9, #36
│ │ -	vmlsl.u16	<illegal reg q13.5>, d13, d5[1]
│ │ -	vsra.u64	<illegal reg q8.5>, <illegal reg q14.5>, #36
│ │ -	vmla.f16	<illegal reg q8.5>, <illegal reg q14.5>, d5[0]
│ │ -	vaddl.u16	<illegal reg q8.5>, d13, d9
│ │ +	asrs	r4, r4, #11
│ │ +			@ <UNDEFINED> instruction: 0xffddb898
│ │ +	vrshr.u64	d30, d28, #36
│ │ +	vrshr.u64	d17, d28, #36
│ │ +	vqrshrun.s32	d27, q8, #3
│ │ +	vmla.i16	<illegal reg q8.5>, q14, d0[0]
│ │ +	vqshlu.s16	<illegal reg q13.5>, q10, #13
│ │ +	vsubl.u16	<illegal reg q8.5>, d12, d20
│ │ +	vmla.f16	<illegal reg q8.5>, <illegal reg q14.5>, d4[3]
│ │ +	vshr.u16	d17, d16, #3
│ │  	vshll.u16	q12, d16, #13
│ │  			@ <UNDEFINED> instruction: 0xffdabb98
│ │  	movs	r0, r4
│ │ -	lsrs	r1, r1, #31
│ │ -			@ <UNDEFINED> instruction: 0xffdd0e39
│ │ -			@ <UNDEFINED> instruction: 0xffddb3ed
│ │ +	lsrs	r0, r6, #31
│ │ +	vqrdmlah.s16	q8, <illegal reg q6.5>, d0[2]
│ │ +	vsri.16	d27, d4, #3
│ │  	vmls.f16	q8, q14, d0[0]
│ │  	movs	r0, r0
│ │  	lsls	r4, r6, #25
│ │  	movs	r0, r0
│ │  	lsls	r0, r0, #15
│ │  	movs	r0, r0
│ │  	lsls	r0, r2, #23
│ │  	movs	r0, r0
│ │ -	lsrs	r1, r0, #29
│ │ -			@ <UNDEFINED> instruction: 0xffdd0f19
│ │ -	vqrdmlah.s16	q8, <illegal reg q14.5>, d1[3]
│ │ -	vqrdmlah.s16	q8, <illegal reg q14.5>, d1[0]
│ │ -			@ <UNDEFINED> instruction: 0xffdd0e99
│ │ -	vqdmulh.s16	q8, <illegal reg q14.5>, d1[1]
│ │ -	vrshr.u16	<illegal reg q13.5>, <illegal reg q14.5>, #3
│ │ -	vshr.u64	<illegal reg q8.5>, <illegal reg q4.5>, #36
│ │ -	vshr.u64	<illegal reg q8.5>, <illegal reg q12.5>, #35
│ │ -	vsra.u16	d17, d9, #3
│ │ -	vsra.u16	d17, d25, #3
│ │ +	lsrs	r0, r5, #29
│ │ +	vqrdmlsh.s16	q8, <illegal reg q6.5>, d0[0]
│ │ +			@ <UNDEFINED> instruction: 0xffdd0f10
│ │ +	vqrdmlah.s16	q8, <illegal reg q14.5>, d0[3]
│ │ +	vqrdmlah.s16	q8, <illegal reg q14.5>, d0[0]
│ │ +			@ <UNDEFINED> instruction: 0xffdd0cf0
│ │ +	vsubl.u16	<illegal reg q13.5>, d29, d20
│ │ +	vaddw.u16	<illegal reg q8.5>, q6, d0
│ │ +	vaddw.u16	<illegal reg q8.5>, <illegal reg q6.5>, d16
│ │ +	vmla.f16	<illegal reg q8.5>, <illegal reg q6.5>, d0[0]
│ │ +	vmla.f16	<illegal reg q8.5>, <illegal reg q6.5>, d0[2]
│ │  	vmla.f16	q14, <illegal reg q6.5>, d4[3]
│ │  	movs	r0, r4
│ │  	stmia	r1!, {r5, r6}
│ │  	movs	r0, r4
│ │ -	asrs	r1, r2, #1
│ │ -	vshr.u16	<illegal reg q8.5>, <illegal reg q8.5>, #3
│ │ -	vmla.i16	<illegal reg q8.5>, <illegal reg q6.5>, d5[3]
│ │ -	vaddl.u16	<illegal reg q8.5>, d29, d13
│ │ -	vrsra.u64	d17, d13, #35
│ │ -	vshr.u16	d17, d21, #3
│ │ -	vshr.u16	<illegal reg q8.5>, <illegal reg q2.5>, #3
│ │ -			@ <UNDEFINED> instruction: 0xffdd136d
│ │ -			@ <UNDEFINED> instruction: 0xffdd0dd9
│ │ -			@ <UNDEFINED> instruction: 0xffdd0df9
│ │ +	asrs	r0, r7, #1
│ │ +	vshr.u64	d17, d8, #35
│ │ +	vshr.u64	d17, d4, #35
│ │ +	vshr.u64	d17, d20, #35
│ │ +			@ <UNDEFINED> instruction: 0xffdd13c4
│ │ +	vshr.u16	<illegal reg q8.5>, q6, #3
│ │ +	vshr.u16	<illegal reg q8.5>, q14, #3
│ │ +	vrsra.u64	d17, d4, #35
│ │ +	vmull.p<illegal width 16>	q8, d13, d0
│ │ +	vmull.p<illegal width 16>	q8, d13, d16
│ │  	vqrshrn.u32	d27, q4, #3
│ │  	movs	r0, r4
│ │  	lsrs	r0, r0, #17
│ │  	movs	r0, r0
│ │  	bkpt	0x00f8
│ │  	movs	r0, r4
│ │ -	asrs	r1, r3, #11
│ │ -	vrshr.u64	<illegal reg q8.5>, <illegal reg q12.5>, #35
│ │ +	asrs	r0, r0, #12
│ │ +	vsubw.u16	<illegal reg q8.5>, <illegal reg q6.5>, d16
│ │  			@ <UNDEFINED> instruction: 0xffddff11
│ │  	b.n	2d1d10 <uniffi_pbcli_checksum_method_api_base@@Base+0x16548c>
│ │  	vrhadd.u16	d14, d2, d31
│ │  	vrhadd.u16	d14, d1, d31
│ │  	vrhadd.u16	d14, d2, d31
│ │  	ldr	r0, [pc, #960]	@ (2d1e80 <uniffi_pbcli_checksum_method_api_base@@Base+0x1655fc>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │ @@ -665807,16 +665807,16 @@
│ │  	b.n	2d223e <uniffi_pbcli_checksum_method_api_base@@Base+0x1659ba>
│ │  	beq.n	2d1f38 <uniffi_pbcli_checksum_method_api_base@@Base+0x1656b4>
│ │  	b.n	2d2398 <uniffi_pbcli_checksum_method_api_base@@Base+0x165b14>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {sp, lr}
│ │  	b.n	2d264a <uniffi_pbcli_checksum_method_api_base@@Base+0x165dc6>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │ -	str	r7, [sp, #128]	@ 0x80
│ │ -			@ <UNDEFINED> instruction: 0xffdc0929
│ │ +	str	r7, [sp, #284]	@ 0x11c
│ │ +	vqrshrn.u32	d16, q0, #4
│ │  			@ <UNDEFINED> instruction: 0xffdd9b99
│ │  	vabal.u16	<illegal reg q13.5>, d26, d4
│ │  	movs	r0, r4
│ │  	movs	r0, r0
│ │  	b.n	2d25c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x165d3e>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (2d1fe8 <uniffi_pbcli_checksum_method_api_base@@Base+0x165764>)
│ │ @@ -665855,15 +665855,15 @@
│ │  	b.n	2d22b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x165a2e>
│ │  	movs	r0, #202	@ 0xca
│ │  	b.n	2d26b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x165e32>
│ │  	ldr	r0, [pc, #192]	@ (2d2038 <uniffi_pbcli_checksum_method_api_base@@Base+0x1657b4>)
│ │  	ldmia.w	sp!, {r0, r1, r4, r6, r7, r8, r9, fp, sp}
│ │  			@ <UNDEFINED> instruction: 0xea01b300
│ │  	movs	r0, r4
│ │ -	lsls	r5, r6, #28
│ │ +	lsls	r4, r3, #29
│ │  			@ <UNDEFINED> instruction: 0xffdd4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2d24a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x165c24>
│ │  	ands	r0, r0
│ │  	b.n	2d22d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x165a4e>
│ │  	add	r0, pc, #96	@ (adr r0, 2d1ff4 <uniffi_pbcli_checksum_method_api_base@@Base+0x165770>)
│ │  	add.w	r0, r0, r0
│ │ @@ -666480,43 +666480,43 @@
│ │  	asrs	r6, r3, #11
│ │  			@ <UNDEFINED> instruction: 0xeb008004
│ │  	b.n	2d2842 <uniffi_pbcli_checksum_method_api_base@@Base+0x165fbe>
│ │  			@ <UNDEFINED> instruction: 0xffeaeaff
│ │  	strh	r0, [r4, #42]	@ 0x2a
│ │  	vsli.64	q9, <illegal reg q6.5>, #27
│ │  	vabal.u16	q12, d11, d20
│ │ -			@ <UNDEFINED> instruction: 0xffdbbef9
│ │ -	vrsra.u64	<illegal reg q12.5>, q1, #36
│ │ +			@ <UNDEFINED> instruction: 0xffdbbf20
│ │ +	vrsra.u64	<illegal reg q12.5>, <illegal reg q12.5>, #36
│ │  	vshr.u16	d17, d21, #4
│ │  	vrshr.u16	q15, q0, #4
│ │  	vqshl.u64	q9, q12, #26
│ │  	vqshlu.s64	d31, d6, #27
│ │  	vsra.u16	d27, d25, #5
│ │  	vqshlu.s16	<illegal reg q15.5>, q13, #10
│ │  	vqshl.u64	q14, q6, #27
│ │ -	vrshr.u16	d21, d17, #5
│ │ -			@ <UNDEFINED> instruction: 0xffdc3b51
│ │ -	vsra.u64	<illegal reg q12.5>, q15, #36
│ │ +	vrshr.u16	<illegal reg q10.5>, q4, #5
│ │ +			@ <UNDEFINED> instruction: 0xffdc3b78
│ │ +	vsubl.u16	<illegal reg q12.5>, d12, d21
│ │  	vrshr.u16	<illegal reg q8.5>, q8, #4
│ │  	movs	r1, r4
│ │  	asrs	r0, r3, #9
│ │  	movs	r1, r4
│ │  	ldrsb	r1, [r2, r4]
│ │ -	vsra.u16	<illegal reg q12.5>, q13, #5
│ │ +	vaddw.u16	<illegal reg q12.5>, <illegal reg q13.5>, d17
│ │  	vsra.u64	<illegal reg q8.5>, q0, #36
│ │  	movs	r1, r4
│ │  	asrs	r4, r6, #6
│ │  	movs	r1, r4
│ │  	strh	r4, [r3, #34]	@ 0x22
│ │ -			@ <UNDEFINED> instruction: 0xffdbbe31
│ │ +			@ <UNDEFINED> instruction: 0xffdbbe58
│ │  	vmls.i16	q12, q14, d4[2]
│ │ -			@ <UNDEFINED> instruction: 0xffdbbeb9
│ │ +	vqrdmlah.s16	<illegal reg q13.5>, <illegal reg q13.5>, d0[2]
│ │  	vsri.64	d24, d24, #36
│ │ -	vmull.p<illegal width 16>	<illegal reg q13.5>, d27, d13
│ │ -	vrshr.u64	q11, q0, #36
│ │ +			@ <UNDEFINED> instruction: 0xffdbbeb4
│ │ +	vrshr.u64	q11, <illegal reg q11.5>, #36
│ │  	vmlal.u16	q10, d12, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2d28be <uniffi_pbcli_checksum_method_api_base@@Base+0x16603a>
│ │  	movs	r4, r6
│ │  	b.n	2d20c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x16583c>
│ │  	movs	r0, r0
│ │  	b.n	2d24c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x165c40>
│ │ @@ -666941,30 +666941,30 @@
│ │  	b.n	2d2a46 <uniffi_pbcli_checksum_method_api_base@@Base+0x1661c2>
│ │  	movs	r4, r1
│ │  	b.n	2d2452 <uniffi_pbcli_checksum_method_api_base@@Base+0x165bce>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {}
│ │  	b.n	2d307a <uniffi_pbcli_checksum_method_api_base@@Base+0x1667f6>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r4, r5, r6, r7, sl, fp, ip, sp, pc}
│ │ -	vsra.u16	q11, q3, #4
│ │ -			@ <UNDEFINED> instruction: 0xffdcbbf2
│ │ +	ldmia.w	sp!, {r0, r3, r4, r8, sl, fp, ip, sp, pc}
│ │ +	vsra.u16	q11, <illegal reg q14.5>, #4
│ │ +			@ <UNDEFINED> instruction: 0xffdcbc19
│ │  			@ <UNDEFINED> instruction: 0xffdcdc3d
│ │ -			@ <UNDEFINED> instruction: 0xffdabc32
│ │ +			@ <UNDEFINED> instruction: 0xffdabc59
│ │  			@ <UNDEFINED> instruction: 0xffdcdc7d
│ │ -	vmull.u16	<illegal reg q13.5>, d26, d2[2]
│ │ +			@ <UNDEFINED> instruction: 0xffdabb09
│ │  			@ <UNDEFINED> instruction: 0xffdcdb2d
│ │ -			@ <UNDEFINED> instruction: 0xffdacbba
│ │ -			@ <UNDEFINED> instruction: 0xffdccb9a
│ │ -			@ <UNDEFINED> instruction: 0xffdcba7e
│ │ +			@ <UNDEFINED> instruction: 0xffdacbe1
│ │ +			@ <UNDEFINED> instruction: 0xffdccbc1
│ │ +	vmlsl.u16	<illegal reg q13.5>, d28, d21
│ │  	vmull.u16	<illegal reg q14.5>, d28, d1[1]
│ │ -			@ <UNDEFINED> instruction: 0xffdabcba
│ │ -	vsra.u16	d22, d14, #4
│ │ -			@ <UNDEFINED> instruction: 0xffdcbb1e
│ │ -			@ <UNDEFINED> instruction: 0xffdc5f82
│ │ +	vqdmulh.s16	<illegal reg q13.5>, q13, d1[2]
│ │ +	vmla.f16	q11, q6, d5[0]
│ │ +			@ <UNDEFINED> instruction: 0xffdcbb45
│ │ +			@ <UNDEFINED> instruction: 0xffdc5fa9
│ │  			@ <UNDEFINED> instruction: 0xffdc4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2d2ea0 <uniffi_pbcli_checksum_method_api_base@@Base+0x16661c>
│ │  	beq.n	2d2998 <uniffi_pbcli_checksum_method_api_base@@Base+0x166114>
│ │  	b.n	2d2e24 <uniffi_pbcli_checksum_method_api_base@@Base+0x1665a0>
│ │  	movs	r0, r0
│ │  	b.n	2d302e <uniffi_pbcli_checksum_method_api_base@@Base+0x1667aa>
│ │ @@ -667298,31 +667298,31 @@
│ │  	movs	r5, r0
│ │  	b.n	2d2faa <uniffi_pbcli_checksum_method_api_base@@Base+0x166726>
│ │  	asrs	r0, r1, #32
│ │  	b.n	2d2fae <uniffi_pbcli_checksum_method_api_base@@Base+0x16672a>
│ │  	ands	r0, r0
│ │  	b.n	2d278c <uniffi_pbcli_checksum_method_api_base@@Base+0x165f08>
│ │  			@ <UNDEFINED> instruction: 0xffd8eaff
│ │ -	cbnz	r6, 2d2c96 <uniffi_pbcli_checksum_method_api_base@@Base+0x166412>
│ │ +	cbnz	r5, 2d2ca0 <uniffi_pbcli_checksum_method_api_base@@Base+0x16641c>
│ │  			@ <UNDEFINED> instruction: 0xffdca9ae
│ │ -	vmul.i16	<illegal reg q13.5>, q5, d2[2]
│ │ +	vmlal.u16	<illegal reg q13.5>, d26, d9
│ │  			@ <UNDEFINED> instruction: 0xffdca892
│ │ -	vqshrun.s32	d27, q11, #6
│ │ +	vqrshrun.s32	d27, <illegal reg q6.5>, #6
│ │  	vsli.16	d25, d15, #12
│ │ -	vmlal.u16	<illegal reg q13.5>, d11, d10
│ │ +	vqshrun.s32	d27, <illegal reg q8.5>, #5
│ │  	vqshrun.s32	d26, q13, #4
│ │ -	vqshl.u64	<illegal reg q13.5>, q7, #26
│ │ +	vmlal.u16	<illegal reg q13.5>, d10, d5
│ │  	vmlal.u16	q13, d12, d14
│ │ -	vabdl.u16	<illegal reg q13.5>, d26, d30
│ │ +	vqshl.u64	<illegal reg q13.5>, <illegal reg q2.5>, #26
│ │  	vqshl.u64	q13, q7, #28
│ │ -	vabdl.u16	<illegal reg q13.5>, d26, d2
│ │ +	vabdl.u16	<illegal reg q13.5>, d26, d25
│ │  	vqshl.u64	d26, d18, #28
│ │ -			@ <UNDEFINED> instruction: 0xffdab89a
│ │ +	vmul.i16	<illegal reg q13.5>, q13, d1[0]
│ │  	vmul.i16	q13, q14, d2[1]
│ │ -	vmlsl.u16	<illegal reg q13.5>, d26, d6[2]
│ │ +	vabdl.u16	<illegal reg q13.5>, d10, d13
│ │  	vqshl.u16	d26, d6, #12
│ │  	vqshrun.s32	d20, q8, #6
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2d31e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x16695c>
│ │  	str	r1, [r0, r0]
│ │  	b.n	2d300a <uniffi_pbcli_checksum_method_api_base@@Base+0x166786>
│ │  	ands	r0, r0
│ │ @@ -667499,15 +667499,15 @@
│ │  	b.n	2d3186 <uniffi_pbcli_checksum_method_api_base@@Base+0x166902>
│ │  	beq.n	2d2e68 <uniffi_pbcli_checksum_method_api_base@@Base+0x1665e4>
│ │  	b.n	2d32e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x166a5c>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r2, r7}
│ │  	movs	r0, r0
│ │  	ldrb	r0, [r7, #12]
│ │ -			@ <UNDEFINED> instruction: 0xffdb2fde
│ │ +	vaddl.u16	<illegal reg q9.5>, d11, d5
│ │  	vmul.i16	<illegal reg q8.5>, q6, d2[2]
│ │  			@ <UNDEFINED> instruction: 0xffdc48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2d3380 <uniffi_pbcli_checksum_method_api_base@@Base+0x166afc>
│ │  	str	r0, [r0, r0]
│ │  	b.n	2d35aa <uniffi_pbcli_checksum_method_api_base@@Base+0x166d26>
│ │  	movs	r0, r0
│ │ @@ -667708,15 +667708,15 @@
│ │  	vrsra.u16	q15, <illegal reg q14.5>, #6
│ │  	vaddw.u16	<illegal reg q10.5>, <illegal reg q13.5>, d27
│ │  			@ <UNDEFINED> instruction: 0xffda9c7e
│ │  	vmull.p<illegal width 16>	<illegal reg q15.5>, d26, d27
│ │  	vmull.u16	<illegal reg q13.5>, d26, d7
│ │  	vsubl.u16	<illegal reg q14.5>, d26, d12
│ │  	vmlsl.u16	<illegal reg q11.5>, d11, d20
│ │ -	vshr.u16	q15, <illegal reg q13.5>, #5
│ │ +	vaddl.u16	q15, d27, d18
│ │  			@ <UNDEFINED> instruction: 0xffdc79f4
│ │  	vrsra.u64	q13, <illegal reg q4.5>, #37
│ │  			@ <UNDEFINED> instruction: 0xffda4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2d3568 <uniffi_pbcli_checksum_method_api_base@@Base+0x166ce4>
│ │  	lsls	r6, r1, #11
│ │  	add.w	r0, r0, r0
│ │ @@ -668058,23 +668058,23 @@
│ │  	movs	r0, r0
│ │  	b.n	2d3aa6 <uniffi_pbcli_checksum_method_api_base@@Base+0x167222>
│ │  			@ <UNDEFINED> instruction: 0xffe5eaff
│ │  	str	r0, [r0, r0]
│ │  	b.n	2d3aae <uniffi_pbcli_checksum_method_api_base@@Base+0x16722a>
│ │  			@ <UNDEFINED> instruction: 0xffebeaff
│ │  			@ <UNDEFINED> instruction: 0xb775
│ │ -	vsri.16	d31, d3, #5
│ │ +	vsri.16	d31, d26, #5
│ │  	vmla.f16	q13, q14, d0[1]
│ │  	movs	r0, r4
│ │  	add	r1, pc, #784	@ (adr r1, 2d3690 <uniffi_pbcli_checksum_method_api_base@@Base+0x166e0c>)
│ │  	movs	r0, r4
│ │  	add	r1, pc, #736	@ (adr r1, 2d3664 <uniffi_pbcli_checksum_method_api_base@@Base+0x166de0>)
│ │  	movs	r0, r4
│ │  			@ <UNDEFINED> instruction: 0xb79d
│ │ -	vsri.16	d31, d27, #5
│ │ +	vmls.i16	<illegal reg q15.5>, <illegal reg q5.5>, d2[2]
│ │  	vsra.u16	d26, d20, #4
│ │  	movs	r0, r4
│ │  	ldr	r0, [pc, #192]	@ (2d3454 <uniffi_pbcli_checksum_method_api_base@@Base+0x166bd0>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2d38b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x167030>
│ │  	movs	r0, r0
│ │  	b.n	2d3a3e <uniffi_pbcli_checksum_method_api_base@@Base+0x1671ba>
│ │ @@ -668139,15 +668139,15 @@
│ │  	lsrs	r4, r2, #28
│ │  	add.w	r0, r0, r4
│ │  	b.n	2d376a <uniffi_pbcli_checksum_method_api_base@@Base+0x166ee6>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r3, r5, r6, sp, pc}
│ │  	movs	r0, r4
│ │  			@ <UNDEFINED> instruction: 0xb61d
│ │ -	vshll.u16	q9, d0, #11
│ │ +	vshll.u16	q9, d23, #11
│ │  	vmlal.u16	q10, d12, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2d3782 <uniffi_pbcli_checksum_method_api_base@@Base+0x166efe>
│ │  	strb	r7, [r6, r3]
│ │  	add.w	r0, r1, ip, lsr #4
│ │  	b.n	2d2f88 <uniffi_pbcli_checksum_method_api_base@@Base+0x166704>
│ │  	movs	r0, r0
│ │ @@ -669054,15 +669054,15 @@
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r2, r3, r4, r5, r6, fp, ip, pc}
│ │  	movs	r0, r4
│ │  	ldr	r0, [sp, #480]	@ 0x1e0
│ │  	movs	r0, r4
│ │  	ldr	r0, [sp, #432]	@ 0x1b0
│ │  	movs	r0, r4
│ │ -	adds	r7, #154	@ 0x9a
│ │ +	adds	r7, #193	@ 0xc1
│ │  			@ <UNDEFINED> instruction: 0xffdc4b86
│ │  	vqshrun.s32	d25, q0, #6
│ │  	movs	r0, r4
│ │  	ldrsb.w	r0, [ip, r0, lsl #2]
│ │  	ldr	r4, [pc, #448]	@ (2d3e34 <uniffi_pbcli_checksum_method_api_base@@Base+0x1675b0>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2d4194 <uniffi_pbcli_checksum_method_api_base@@Base+0x167910>
│ │ @@ -669134,15 +669134,15 @@
│ │  	lsrs	r2, r3, #19
│ │  	add.w	r0, r0, r4
│ │  	b.n	2d4052 <uniffi_pbcli_checksum_method_api_base@@Base+0x1677ce>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {}
│ │  	b.n	2d445a <uniffi_pbcli_checksum_method_api_base@@Base+0x167bd6>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r7, r9, sl, ip, sp}
│ │ +	ldmia.w	sp!, {r0, r3, r5, r7, r9, sl, ip, sp}
│ │  	vmul.f16	q8, q14, d3[0]
│ │  	vabdl.u16	<illegal reg q12.5>, d28, d8
│ │  	movs	r0, r4
│ │  	ldr	r0, [pc, #960]	@ (2d40ec <uniffi_pbcli_checksum_method_api_base@@Base+0x167868>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2d424c <uniffi_pbcli_checksum_method_api_base@@Base+0x1679c8>
│ │  	movs	r0, r0
│ │ @@ -669423,30 +669423,30 @@
│ │  	b.n	2d4636 <uniffi_pbcli_checksum_method_api_base@@Base+0x167db2>
│ │  			@ <UNDEFINED> instruction: 0xfffa1aff
│ │  	str	r6, [r5, r1]
│ │  	b.n	2d46da <uniffi_pbcli_checksum_method_api_base@@Base+0x167e56>
│ │  	eors	r1, r4
│ │  	b.n	2d46de <uniffi_pbcli_checksum_method_api_base@@Base+0x167e5a>
│ │  			@ <UNDEFINED> instruction: 0xffc4eaff
│ │ -	adds	r5, #222	@ 0xde
│ │ -	vshr.u64	q8, <illegal reg q12.5>, #36
│ │ -	vrsubhn.i32	d19, <illegal reg q6.5>, q5
│ │ -	vaddw.u16	q8, q6, d21
│ │ +	adds	r6, #5
│ │ +	vaddw.u16	q8, q6, d16
│ │ +	vqshlu.s16	d19, d17, #13
│ │ +	vmla.f16	q8, q6, d4[1]
│ │  	vqshlu.s16	<illegal reg q12.5>, q2, #13
│ │  	movs	r0, r4
│ │  			@ <UNDEFINED> instruction: 0xf7600020
│ │  	subw	r0, ip, #2080	@ 0x820
│ │  	lsls	r4, r4, #24
│ │  	movs	r0, r0
│ │  	rsbs	r0, ip, #10485760	@ 0xa00000
│ │  	rsbs	r0, r0, #10485760	@ 0xa00000
│ │  			@ <UNDEFINED> instruction: 0xf7140020
│ │ -	adds	r4, #138	@ 0x8a
│ │ -			@ <UNDEFINED> instruction: 0xffdc48ba
│ │ -			@ <UNDEFINED> instruction: 0xffdcff75
│ │ +	adds	r4, #177	@ 0xb1
│ │ +	vmul.i16	q10, q14, d1[2]
│ │ +			@ <UNDEFINED> instruction: 0xffdcff9c
│ │  			@ <UNDEFINED> instruction: 0xffdc4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2d44fc <uniffi_pbcli_checksum_method_api_base@@Base+0x167c78>
│ │  	movs	r0, r0
│ │  	b.n	2d4686 <uniffi_pbcli_checksum_method_api_base@@Base+0x167e02>
│ │  	movs	r1, r5
│ │  	lsrs	r0, r0, #8
│ │ @@ -669601,24 +669601,24 @@
│ │  	lsrs	r1, r2, #15
│ │  	add.w	r0, r0, r0
│ │  	b.n	2d3c62 <uniffi_pbcli_checksum_method_api_base@@Base+0x1673de>
│ │  	str	r2, [r4, r7]
│ │  	add.w	r0, r1, r4
│ │  	b.n	2d447e <uniffi_pbcli_checksum_method_api_base@@Base+0x167bfa>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r3, r6, r7, r9, ip, sp}
│ │ +	ldmia.w	sp!, {r0, r4, r5, r6, r7, r9, ip, sp}
│ │  			@ <UNDEFINED> instruction: 0xffdc4ff2
│ │  	vraddhn.i32	d25, <illegal reg q5.5>, q8
│ │  	movs	r0, r4
│ │  			@ <UNDEFINED> instruction: 0xf52c0020
│ │  			@ <UNDEFINED> instruction: 0xf4ec0020
│ │  			@ <UNDEFINED> instruction: 0xf4d80020
│ │  			@ <UNDEFINED> instruction: 0xf4d00020
│ │  			@ <UNDEFINED> instruction: 0xf4c40020
│ │ -	adds	r2, #134	@ 0x86
│ │ +	adds	r2, #173	@ 0xad
│ │  			@ <UNDEFINED> instruction: 0xffdc4fbc
│ │  			@ <UNDEFINED> instruction: 0xffdb4f7e
│ │  			@ <UNDEFINED> instruction: 0xffdb48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2d4690 <uniffi_pbcli_checksum_method_api_base@@Base+0x167e0c>
│ │  	movs	r0, r0
│ │  	b.n	2d481a <uniffi_pbcli_checksum_method_api_base@@Base+0x167f96>
│ │ @@ -669909,38 +669909,38 @@
│ │  	movs	r1, r3
│ │  	add.w	r0, r0, r0
│ │  	b.n	2d3f28 <uniffi_pbcli_checksum_method_api_base@@Base+0x1676a4>
│ │  	str	r1, [r6, r4]
│ │  	add.w	r0, r1, r5
│ │  	b.n	2d4742 <uniffi_pbcli_checksum_method_api_base@@Base+0x167ebe>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r7, r8, ip, sp}
│ │ +	ldmia.w	sp!, {r0, r3, r5, r7, r8, ip, sp}
│ │  	vqshlu.s64	<illegal reg q9.5>, q4, #28
│ │  	vsubl.u16	<illegal reg q12.5>, d27, d12
│ │  	movs	r0, r4
│ │  	str	r2, [sp, #544]	@ 0x220
│ │  	movs	r0, r4
│ │  	str	r2, [sp, #496]	@ 0x1f0
│ │  	movs	r0, r4
│ │ -	adds	r1, #170	@ 0xaa
│ │ +	adds	r1, #209	@ 0xd1
│ │  	vabdl.u16	<illegal reg q9.5>, d12, d0
│ │  	vsra.u64	<illegal reg q12.5>, q12, #37
│ │  	movs	r0, r4
│ │  			@ <UNDEFINED> instruction: 0xf3040020
│ │  	lsls	r0, r5, #29
│ │  	vsra.u16	d25, d3, #5
│ │  	vqshl.u16	d16, d16, #10
│ │  	vmla.f16	<illegal reg q12.5>, <illegal reg q5.5>, d6[2]
│ │ -	vshr.u64	d19, d15, #37
│ │ +	vmla.i16	<illegal reg q9.5>, <illegal reg q13.5>, d6[0]
│ │  	vsli.64	d29, d18, #28
│ │  			@ <UNDEFINED> instruction: 0xffdbbeb8
│ │  	vaddl.u16	<illegal reg q12.5>, d11, d29
│ │ -	vmla.i16	<illegal reg q9.5>, q5, d0[2]
│ │ +	vaddl.u16	<illegal reg q9.5>, d26, d7
│ │  	vqshlu.s64	q13, q0, #28
│ │ -			@ <UNDEFINED> instruction: 0xffdb2fbe
│ │ +	vqrdmlsh.s16	q9, <illegal reg q13.5>, d5[2]
│ │  	vsli.16	d19, d4, #12
│ │  	vsubw.u16	q10, <illegal reg q13.5>, d19
│ │  			@ <UNDEFINED> instruction: 0xffda48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2d4980 <uniffi_pbcli_checksum_method_api_base@@Base+0x1680fc>
│ │  	str	r4, [r1, r0]
│ │  	ldmia.w	r1, {sp}
│ │ @@ -670591,15 +670591,15 @@
│ │  	ldmia.w	sp!, {r3, r4, r6, r7, r9, fp, pc}
│ │  	movs	r0, r4
│ │  	ldrh	r4, [r2, #22]
│ │  	movs	r0, r4
│ │  	ldrh	r0, [r1, #22]
│ │  	movs	r0, r4
│ │  	cmp	r7, #93	@ 0x5d
│ │ -	vraddhn.i32	d17, <illegal reg q13.5>, q15
│ │ +	vsri.64	<illegal reg q8.5>, <illegal reg q2.5>, #37
│ │  			@ <UNDEFINED> instruction: 0xffdc8a74
│ │  	movs	r0, r4
│ │  	lsls	r4, r4, #1
│ │  	movs	r0, r0
│ │  	sbcs.w	r0, ip, r0, asr #32
│ │  	ldr	r7, [pc, #960]	@ (2d4dec <uniffi_pbcli_checksum_method_api_base@@Base+0x168568>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │ @@ -670995,15 +670995,15 @@
│ │  	lsls	r4, r7, #14
│ │  	movs	r0, r0
│ │  	lsls	r4, r7, #14
│ │  	movs	r0, r0
│ │  	strb	r4, [r2, #18]
│ │  	vrshr.u64	<illegal reg q11.5>, q12, #37
│ │  	vsubw.u16	<illegal reg q11.5>, <illegal reg q5.5>, d24
│ │ -	vmlsl.u16	<illegal reg q9.5>, d27, d18
│ │ +	vmull.u16	<illegal reg q9.5>, d27, d1[1]
│ │  	vmlsl.u16	q12, d28, d4[1]
│ │  	movs	r0, r4
│ │  	strb	r0, [r0, #11]
│ │  	vqshlu.s64	d24, d0, #27
│ │  	movs	r0, r4
│ │  	ldr	r0, [pc, #192]	@ (2d4e84 <uniffi_pbcli_checksum_method_api_base@@Base+0x168600>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │ @@ -671732,15 +671732,15 @@
│ │  	movs	r0, r0
│ │  	b.n	2d5558 <uniffi_pbcli_checksum_method_api_base@@Base+0x168cd4>
│ │  	movs	r0, #2
│ │  	b.n	2d555c <uniffi_pbcli_checksum_method_api_base@@Base+0x168cd8>
│ │  	mcr2	10, 4, lr, cr11, cr15, {7}	@ <UNPREDICTABLE>
│ │  	b.n	2d5674 <uniffi_pbcli_checksum_method_api_base@@Base+0x168df0>
│ │  	movs	r0, r4
│ │ -	str	r0, [r0, #4]
│ │ +	str	r7, [r4, #4]
│ │  			@ <UNDEFINED> instruction: 0xffdc4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2d596c <uniffi_pbcli_checksum_method_api_base@@Base+0x1690e8>
│ │  	beq.n	2d5464 <uniffi_pbcli_checksum_method_api_base@@Base+0x168be0>
│ │  	b.n	2d58f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x16906c>
│ │  	ands	r0, r4
│ │  	b.n	2d4f7a <uniffi_pbcli_checksum_method_api_base@@Base+0x1686f6>
│ │ @@ -671784,16 +671784,16 @@
│ │  	b.n	2d5bee <uniffi_pbcli_checksum_method_api_base@@Base+0x16936a>
│ │  	lsls	r1, r6, #27
│ │  	add.w	r0, r0, r4
│ │  	b.n	2d57f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x168f72>
│ │  	beq.n	2d54c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x168c44>
│ │  	b.n	2d5950 <uniffi_pbcli_checksum_method_api_base@@Base+0x1690cc>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r3, r5, r6, r7, r8, r9, sl, fp, ip, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffdc09ac
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, sp, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffdc09d3
│ │  	vaddl.u16	<illegal reg q8.5>, d12, d16
│ │  	b.n	2d4fca <uniffi_pbcli_checksum_method_api_base@@Base+0x168746>
│ │  	movs	r1, r0
│ │  	b.n	2d5c0e <uniffi_pbcli_checksum_method_api_base@@Base+0x16938a>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r0, [pc, #0]	@ (2d54d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x168c50>)
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │ @@ -673712,15 +673712,15 @@
│ │  	asrs	r1, r0, #23
│ │  	asrs	r1, r0, #32
│ │  	asrs	r0, r4, #14
│ │  	asrs	r0, r0, #32
│ │  	asrs	r0, r0, #22
│ │  			@ <UNDEFINED> instruction: 0xffafeaff
│ │  	mrc2	15, 5, pc, cr13, cr10, {6}
│ │ -	str	r0, [sp, #40]	@ 0x28
│ │ +	str	r0, [sp, #196]	@ 0xc4
│ │  	vmlal.u16	q10, d12, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2d68ca <uniffi_pbcli_checksum_method_api_base@@Base+0x16a046>
│ │  	beq.n	2d659c <uniffi_pbcli_checksum_method_api_base@@Base+0x169d18>
│ │  	b.n	2d6a28 <uniffi_pbcli_checksum_method_api_base@@Base+0x16a1a4>
│ │  	stmia	r0!, {r1}
│ │  	b.n	2d68d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16a04e>
│ │ @@ -673989,18 +673989,18 @@
│ │  	movs	r0, r4
│ │  	ldmia	r5, {r2, r5, r6, r7}
│ │  	movs	r0, r4
│ │  	ldmia	r5!, {r4, r6, r7}
│ │  	movs	r0, r4
│ │  	ldmia	r5, {r2, r3, r4, r5, r7}
│ │  	movs	r0, r4
│ │ -	adds	r6, #189	@ 0xbd
│ │ +	adds	r6, #228	@ 0xe4
│ │  	vqrdmlsh.s16	<illegal reg q14.5>, q14, d7[2]
│ │  	vmull.u16	q14, d11, d5[2]
│ │ -	vshr.u64	d25, d24, #37
│ │ +	vshr.u64	<illegal reg q12.5>, <illegal reg q7.5>, #37
│ │  	vqshrun.s32	d20, q8, #4
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2d6d18 <uniffi_pbcli_checksum_method_api_base@@Base+0x16a494>
│ │  	beq.n	2d6810 <uniffi_pbcli_checksum_method_api_base@@Base+0x169f8c>
│ │  	b.n	2d6c9c <uniffi_pbcli_checksum_method_api_base@@Base+0x16a418>
│ │  	str	r0, [r0, r0]
│ │  	b.n	2d6b46 <uniffi_pbcli_checksum_method_api_base@@Base+0x16a2c2>
│ │ @@ -674666,15 +674666,15 @@
│ │  	b.n	2d74fe <uniffi_pbcli_checksum_method_api_base@@Base+0x16ac7a>
│ │  	movs	r0, r0
│ │  	b.n	2d68ca <uniffi_pbcli_checksum_method_api_base@@Base+0x16a046>
│ │  	beq.n	2d6dfc <uniffi_pbcli_checksum_method_api_base@@Base+0x16a578>
│ │  	b.n	2d725c <uniffi_pbcli_checksum_method_api_base@@Base+0x16a9d8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r1, r2, r3, r4, r6, r8, sl, fp, ip, sp, lr}
│ │ -	vmls.f16	<illegal reg q11.5>, <illegal reg q5.5>, d7[0]
│ │ +	vmls.f16	<illegal reg q11.5>, <illegal reg q5.5>, d6[3]
│ │  			@ <UNDEFINED> instruction: 0xffdc7d9a
│ │  			@ <UNDEFINED> instruction: 0xffdb7d76
│ │  	vrsra.u64	<illegal reg q15.5>, <illegal reg q10.5>, #37
│ │  	vqdmulh.s16	<illegal reg q11.5>, q13, d6[3]
│ │  			@ <UNDEFINED> instruction: 0xffdb4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2d7304 <uniffi_pbcli_checksum_method_api_base@@Base+0x16aa80>
│ │ @@ -675203,16 +675203,16 @@
│ │  	add	r1, pc, #0	@ (adr r1, 2d7258 <uniffi_pbcli_checksum_method_api_base@@Base+0x16a9d4>)
│ │  	b.n	2d6d68 <uniffi_pbcli_checksum_method_api_base@@Base+0x16a4e4>
│ │  	strh	r0, [r0, #6]
│ │  	b.n	2d6d6c <uniffi_pbcli_checksum_method_api_base@@Base+0x16a4e8>
│ │  	beq.n	2d7298 <uniffi_pbcli_checksum_method_api_base@@Base+0x16aa14>
│ │  	b.n	2d76f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x16ae74>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r5, r8, sl, fp, sp, lr, pc}
│ │ -	vqdmulh.s16	q15, <illegal reg q13.5>, d2[1]
│ │ +	ldmia.w	sp!, {r0, r2, r5, r6, r8, sl, fp, sp, lr, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffdbecf1
│ │  			@ <UNDEFINED> instruction: 0xffdbef51
│ │  	vmlal.u16	q10, d10, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2d75ba <uniffi_pbcli_checksum_method_api_base@@Base+0x16ad36>
│ │  			@ <UNDEFINED> instruction: 0xfbacebff
│ │  	asrs	r0, r0, #32
│ │  	b.n	2d75c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16ad3e>
│ │ @@ -676883,47 +676883,47 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	2d8822 <uniffi_pbcli_checksum_method_api_base@@Base+0x16bf9e>
│ │  	asrs	r4, r1, #32
│ │  	b.n	2d8766 <uniffi_pbcli_checksum_method_api_base@@Base+0x16bee2>
│ │  	movs	r6, r0
│ │  	b.n	2d882a <uniffi_pbcli_checksum_method_api_base@@Base+0x16bfa6>
│ │  			@ <UNDEFINED> instruction: 0xff94eaff
│ │ -	bl	3b0a6 <UNIFFI_META_PBCLI_RECORD_OPTS@@Base-0x2af5a>
│ │ +	bl	620a6 <UNIFFI_META_PBCLI_RECORD_OPTS@@Base-0x3f5a>
│ │  	strh	r1, [r3, #30]
│ │ -	vmls.f16	<illegal reg q15.5>, <illegal reg q5.5>, d2[0]
│ │ +	vmls.f16	<illegal reg q15.5>, <illegal reg q5.5>, d1[3]
│ │  	vrsra.u64	d24, d25, #37
│ │ -	vrshr.u64	<illegal reg q15.5>, q3, #37
│ │ +	vrshr.u64	<illegal reg q15.5>, <illegal reg q14.5>, #37
│ │  	vmla.f16	q12, <illegal reg q5.5>, d5[1]
│ │ -	vqshl.u16	<illegal reg q15.5>, q11, #11
│ │ +	vqshl.u64	d31, d13, #27
│ │  	vqrshrn.u32	d16, q0, #5
│ │  	movs	r0, r0
│ │  	ldrsb	r4, [r5, r5]
│ │  	movs	r0, r4
│ │  	ldrsb	r4, [r4, r5]
│ │  	movs	r0, r4
│ │  	lsrs	r0, r7, #3
│ │  	movs	r0, r0
│ │  	ldrsb	r4, [r2, r4]
│ │  	movs	r0, r4
│ │  	ldrsb	r4, [r1, r4]
│ │  	movs	r0, r4
│ │ -	bl	fff070da <uniffi_pbcli_checksum_method_api_base@@Base+0xffd9a856>
│ │ -	bl	6ab0de <uniffi_pbcli_checksum_method_api_base@@Base+0x53e85a>
│ │ +	bl	fff2e0da <uniffi_pbcli_checksum_method_api_base@@Base+0xffdc1856>
│ │ +	bl	6d20de <uniffi_pbcli_checksum_method_api_base@@Base+0x56585a>
│ │  	strh	r1, [r1, #18]
│ │ -	vmls.i16	<illegal reg q15.5>, <illegal reg q13.5>, d6[0]
│ │ +	vmls.i16	<illegal reg q15.5>, <illegal reg q13.5>, d5[3]
│ │  	vrsra.u16	d24, d29, #5
│ │ -	vsli.16	<illegal reg q15.5>, q15, #11
│ │ +	vabal.u16	<illegal reg q15.5>, d27, d21
│ │  	vrsra.u64	q12, <illegal reg q10.5>, #37
│ │ -	vsubw.u16	<illegal reg q15.5>, <illegal reg q5.5>, d14
│ │ +	vrsra.u16	d31, d21, #5
│ │  	vaddw.u16	q12, <illegal reg q13.5>, d5
│ │ -	vsri.16	<illegal reg q15.5>, q13, #5
│ │ +	vraddhn.i32	d31, <illegal reg q13.5>, <illegal reg q8.5>
│ │  	vrshr.u64	q12, <illegal reg q8.5>, #37
│ │ -			@ <UNDEFINED> instruction: 0xffdbf34a
│ │ +	vrsra.u16	<illegal reg q15.5>, <illegal reg q8.5>, #5
│ │  	vmla.f16	q12, <illegal reg q13.5>, d1[0]
│ │ -	vsli.16	d31, d2, #11
│ │ +	vsli.16	d31, d25, #11
│ │  	vsubw.u16	q12, <illegal reg q13.5>, d9
│ │  			@ <UNDEFINED> instruction: 0xffdb4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2d8680 <uniffi_pbcli_checksum_method_api_base@@Base+0x16bdfc>
│ │  	beq.n	2d8178 <uniffi_pbcli_checksum_method_api_base@@Base+0x16b8f4>
│ │  	b.n	2d8604 <uniffi_pbcli_checksum_method_api_base@@Base+0x16bd80>
│ │  	movs	r0, r0
│ │ @@ -677127,23 +677127,23 @@
│ │  	b.n	2d8a62 <uniffi_pbcli_checksum_method_api_base@@Base+0x16c1de>
│ │  			@ <UNDEFINED> instruction: 0xffc1eaff
│ │  	lsls	r0, r0, #1
│ │  	b.n	2d7e58 <uniffi_pbcli_checksum_method_api_base@@Base+0x16b5d4>
│ │  	stmia	r0!, {r4, r6}
│ │  	b.n	2d7e4e <uniffi_pbcli_checksum_method_api_base@@Base+0x16b5ca>
│ │  			@ <UNDEFINED> instruction: 0xffd0eaff
│ │ -	bl	4a32ea <uniffi_pbcli_checksum_method_api_base@@Base+0x336a66>
│ │ +	bl	4ca2ea <uniffi_pbcli_checksum_method_api_base@@Base+0x35da66>
│ │  	bl	2532ec <uniffi_pbcli_checksum_method_api_base@@Base+0xe6a68>
│ │ -	bl	46f2f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x302a6e>
│ │ +	bl	4962f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x329a6e>
│ │  	bl	21f2f4 <uniffi_pbcli_checksum_method_api_base@@Base+0xb2a70>
│ │ -	bl	41f2fa <uniffi_pbcli_checksum_method_api_base@@Base+0x2b2a76>
│ │ +	bl	4462fa <uniffi_pbcli_checksum_method_api_base@@Base+0x2d9a76>
│ │  	bl	1cf2fc <uniffi_pbcli_checksum_method_api_base@@Base+0x62a78>
│ │ -	bl	387302 <uniffi_pbcli_checksum_method_api_base@@Base+0x21aa7e>
│ │ +	bl	3ae302 <uniffi_pbcli_checksum_method_api_base@@Base+0x241a7e>
│ │  	bl	137304 <UNIFFI_META_PBCLI_METHOD_API_BASE@@Base+0xcdaea>
│ │ -	bl	3b330a <uniffi_pbcli_checksum_method_api_base@@Base+0x246a86>
│ │ +	bl	3da30a <uniffi_pbcli_checksum_method_api_base@@Base+0x26da86>
│ │  	bl	16330c <ffi_pbcli_rust_future_free_void@@Base+0x45e6>
│ │  	subs	r1, r0, r4
│ │  	b.n	2d8a9e <uniffi_pbcli_checksum_method_api_base@@Base+0x16c21a>
│ │  	movs	r0, #0
│ │  	b.n	2d8aa2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16c21e>
│ │  	mcr2	10, 0, lr, cr15, cr15, {7}	@ <UNPREDICTABLE>
│ │  	ldr	r5, [pc, #960]	@ (2d8728 <uniffi_pbcli_checksum_method_api_base@@Base+0x16bea4>)
│ │ @@ -677352,24 +677352,24 @@
│ │  	b.n	2d8c6a <uniffi_pbcli_checksum_method_api_base@@Base+0x16c3e6>
│ │  			@ <UNDEFINED> instruction: 0xffc1eaff
│ │  	lsls	r0, r0, #1
│ │  	b.n	2d8060 <uniffi_pbcli_checksum_method_api_base@@Base+0x16b7dc>
│ │  	stmia	r0!, {r3, r4, r6}
│ │  	b.n	2d8056 <uniffi_pbcli_checksum_method_api_base@@Base+0x16b7d2>
│ │  			@ <UNDEFINED> instruction: 0xffd0eaff
│ │ -			@ <UNDEFINED> instruction: 0xefc2ffdb
│ │ -	strb	r6, [r4, #16]
│ │ -			@ <UNDEFINED> instruction: 0xffdcef8e
│ │ -	vrsra.u64	<illegal reg q11.5>, q9, #37
│ │ -			@ <UNDEFINED> instruction: 0xffdcef3e
│ │ -	vsubw.u16	<illegal reg q11.5>, <illegal reg q13.5>, d18
│ │ -	vmull.p<illegal width 16>	q15, d28, d22
│ │ -	vsubw.u16	<illegal reg q11.5>, <illegal reg q5.5>, d10
│ │ -			@ <UNDEFINED> instruction: 0xffdceed2
│ │ -	vrsra.u16	d23, d22, #5
│ │ +			@ <UNDEFINED> instruction: 0xefe9ffdb
│ │ +	strb	r5, [r1, #17]
│ │ +			@ <UNDEFINED> instruction: 0xffdcefb5
│ │ +	vsri.16	d23, d9, #5
│ │ +	vqrdmlsh.s16	q15, q6, d5[2]
│ │ +			@ <UNDEFINED> instruction: 0xffdb73c9
│ │ +	vqrdmlah.s16	q15, q14, d5[1]
│ │ +	vrsra.u16	d23, d17, #5
│ │ +			@ <UNDEFINED> instruction: 0xffdceef9
│ │ +	vrsra.u16	<illegal reg q11.5>, <illegal reg q6.5>, #5
│ │  	vqshrun.s32	d20, q8, #4
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2d8a84 <uniffi_pbcli_checksum_method_api_base@@Base+0x16c200>
│ │  	movs	r0, r0
│ │  	b.n	2d8c0e <uniffi_pbcli_checksum_method_api_base@@Base+0x16c38a>
│ │  	movs	r2, r1
│ │  	lsrs	r0, r0, #8
│ │ @@ -677413,15 +677413,15 @@
│ │  	b.n	2d890a <uniffi_pbcli_checksum_method_api_base@@Base+0x16c086>
│ │  	asrs	r5, r0, #32
│ │  	b.n	2d890e <uniffi_pbcli_checksum_method_api_base@@Base+0x16c08a>
│ │  	movs	r1, #210	@ 0xd2
│ │  	b.n	2d8bd2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16c34e>
│ │  	ldr	r0, [pc, #192]	@ (2d8694 <uniffi_pbcli_checksum_method_api_base@@Base+0x16be10>)
│ │  	ldmia.w	sp!, {r2, r3, r4, r5, r9, ip}
│ │ -			@ <UNDEFINED> instruction: 0xea01edf2
│ │ +			@ <UNDEFINED> instruction: 0xea01ee19
│ │  	vshr.u16	d16, d0, #5
│ │  	b.n	2d8ae2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16c25e>
│ │  	subs	r7, r3, #6
│ │  	b.n	2d8906 <uniffi_pbcli_checksum_method_api_base@@Base+0x16c082>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2d8aec <uniffi_pbcli_checksum_method_api_base@@Base+0x16c268>
│ │  	cmp	r7, #145	@ 0x91
│ │ @@ -677799,20 +677799,20 @@
│ │  	b.n	2d9072 <uniffi_pbcli_checksum_method_api_base@@Base+0x16c7ee>
│ │  	movs	r6, r0
│ │  	b.n	2d8c76 <uniffi_pbcli_checksum_method_api_base@@Base+0x16c3f2>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r2}
│ │  	b.n	2d8c7e <uniffi_pbcli_checksum_method_api_base@@Base+0x16c3fa>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r5, r6, r8, sl, fp, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffdbeada
│ │ +	ldmia.w	sp!, {r0, r2, r5, r7, r8, sl, fp, sp, lr, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffdbeb01
│ │  	vmull.p<illegal width 16>	<illegal reg q13.5>, d11, d12
│ │ -			@ <UNDEFINED> instruction: 0xffdbeb32
│ │ +			@ <UNDEFINED> instruction: 0xffdbeb59
│ │  	vqrdmlah.s16	<illegal reg q13.5>, <illegal reg q5.5>, d4[2]
│ │ -			@ <UNDEFINED> instruction: 0xffdbea9a
│ │ +	vmull.u16	q15, d27, d1[0]
│ │  	vaddl.u16	q8, d11, d4
│ │  	b.n	2d849c <uniffi_pbcli_checksum_method_api_base@@Base+0x16bc18>
│ │  	movs	r0, r0
│ │  	b.n	2d8a80 <uniffi_pbcli_checksum_method_api_base@@Base+0x16c1fc>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	add.w	r0, r0, #28
│ │  	ldr	r7, [pc, #960]	@ (2d8d2c <uniffi_pbcli_checksum_method_api_base@@Base+0x16c4a8>)
│ │ @@ -679562,15 +679562,15 @@
│ │  	asrs	r5, r0, #32
│ │  	b.n	2d9bf2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16d36e>
│ │  			@ <UNDEFINED> instruction: 0xb65e
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	2d9d50 <uniffi_pbcli_checksum_method_api_base@@Base+0x16d4cc>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r1, r4, r6, r7, r9, sl, fp, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffdbefb1
│ │ +			@ <UNDEFINED> instruction: 0xffdbefd8
│ │  			@ <UNDEFINED> instruction: 0xffdbf8b5
│ │  			@ <UNDEFINED> instruction: 0xffda4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2d9dec <uniffi_pbcli_checksum_method_api_base@@Base+0x16d568>
│ │  	beq.n	2d9954 <uniffi_pbcli_checksum_method_api_base@@Base+0x16d0d0>
│ │  	b.n	2d9d70 <uniffi_pbcli_checksum_method_api_base@@Base+0x16d4ec>
│ │  	movs	r0, r0
│ │ @@ -679656,15 +679656,15 @@
│ │  	asrs	r5, r0, #32
│ │  	b.n	2d9cca <uniffi_pbcli_checksum_method_api_base@@Base+0x16d446>
│ │  			@ <UNDEFINED> instruction: 0xb628
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	2d9e28 <uniffi_pbcli_checksum_method_api_base@@Base+0x16d5a4>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r1, r3, r4, r5, r6, r7, r8, sl, fp, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffdbeed9
│ │ +			@ <UNDEFINED> instruction: 0xffdbef00
│ │  	vshr.u16	d30, d3, #5
│ │  			@ <UNDEFINED> instruction: 0xffda4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2d9ec4 <uniffi_pbcli_checksum_method_api_base@@Base+0x16d640>
│ │  	beq.n	2d9a2c <uniffi_pbcli_checksum_method_api_base@@Base+0x16d1a8>
│ │  	b.n	2d9e48 <uniffi_pbcli_checksum_method_api_base@@Base+0x16d5c4>
│ │  	movs	r0, r0
│ │ @@ -679750,15 +679750,15 @@
│ │  	asrs	r5, r0, #32
│ │  	b.n	2d9da2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16d51e>
│ │  	push	{r1, r4, r5, r6, r7, lr}
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	2d9f00 <uniffi_pbcli_checksum_method_api_base@@Base+0x16d67c>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r1, r5, r8, sl, fp, sp, pc}
│ │ -	vmull.p<illegal width 16>	q15, d11, d1
│ │ +	vmull.p<illegal width 16>	q15, d11, d24
│ │  			@ <UNDEFINED> instruction: 0xffdb9746
│ │  			@ <UNDEFINED> instruction: 0xffdb4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2d9f9c <uniffi_pbcli_checksum_method_api_base@@Base+0x16d718>
│ │  	beq.n	2d9b04 <uniffi_pbcli_checksum_method_api_base@@Base+0x16d280>
│ │  	b.n	2d9f20 <uniffi_pbcli_checksum_method_api_base@@Base+0x16d69c>
│ │  	movs	r0, r0
│ │ @@ -680004,15 +680004,15 @@
│ │  	b.n	2d9dbc <uniffi_pbcli_checksum_method_api_base@@Base+0x16d538>
│ │  	lsrs	r6, r4, #20
│ │  	add.w	r0, r1, r0
│ │  	b.n	2da3e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x16db62>
│ │  	movs	r0, r2
│ │  	b.n	2d97b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16cf2e>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r1, r3, r4, r5, r6, r7, r8, r9, sl, fp, sp}
│ │ +	ldmia.w	sp!, {r0, r5, ip, sp}
│ │  	vaddl.u16	q8, d12, d0
│ │  	b.n	2da356 <uniffi_pbcli_checksum_method_api_base@@Base+0x16dad2>
│ │  	movs	r5, r1
│ │  	lsrs	r0, r0, #8
│ │  	asrs	r0, r2, #32
│ │  	b.n	2d97de <uniffi_pbcli_checksum_method_api_base@@Base+0x16cf5a>
│ │  	movs	r0, r0
│ │ @@ -680232,30 +680232,30 @@
│ │  	b.n	2da5ee <uniffi_pbcli_checksum_method_api_base@@Base+0x16dd6a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2d9fd0 <uniffi_pbcli_checksum_method_api_base@@Base+0x16d74c>
│ │  	lsrs	r5, r0, #16
│ │  	add.w	r0, r1, r0
│ │  	b.n	2da5fa <uniffi_pbcli_checksum_method_api_base@@Base+0x16dd76>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r1, r2, r5, r8, r9, sl, fp, sp}
│ │ -	vqrdmlah.s16	q9, q6, d2[2]
│ │ +	ldmia.w	sp!, {r0, r2, r3, r6, r8, r9, sl, fp, sp}
│ │ +	vmull.p<illegal width 16>	q9, d28, d9
│ │  	vrsra.u64	d25, d8, #36
│ │ -	vqrdmulh.s16	q9, q13, d6[2]
│ │ -	vmull.p<illegal width 16>	q9, d28, d22
│ │ +	vmull.p<illegal width 16>	q9, d10, d13
│ │ +	vqrdmlah.s16	q9, q14, d5[1]
│ │  	vrsra.u64	<illegal reg q12.5>, q6, #36
│ │  	vaddl.u16	<illegal reg q8.5>, d10, d12
│ │  	b.n	2d9a18 <uniffi_pbcli_checksum_method_api_base@@Base+0x16d194>
│ │  	movs	r4, r4
│ │  	b.n	2da61e <uniffi_pbcli_checksum_method_api_base@@Base+0x16dd9a>
│ │  	movs	r0, #131	@ 0x83
│ │  	b.n	2da622 <uniffi_pbcli_checksum_method_api_base@@Base+0x16dd9e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2da004 <uniffi_pbcli_checksum_method_api_base@@Base+0x16d780>
│ │  	lsrs	r6, r3, #12
│ │ -	and.w	sp, r1, r2, ror #10
│ │ +	and.w	sp, r1, r9, lsr #11
│ │  	vaddl.u16	q8, d12, d0
│ │  	b.n	2da592 <uniffi_pbcli_checksum_method_api_base@@Base+0x16dd0e>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (2d9f38 <uniffi_pbcli_checksum_method_api_base@@Base+0x16d6b4>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2da418 <uniffi_pbcli_checksum_method_api_base@@Base+0x16db94>
│ │  	subs	r1, r0, r4
│ │ @@ -680292,15 +680292,15 @@
│ │  	b.n	2da286 <uniffi_pbcli_checksum_method_api_base@@Base+0x16da02>
│ │  	movs	r0, #140	@ 0x8c
│ │  	b.n	2da68a <uniffi_pbcli_checksum_method_api_base@@Base+0x16de06>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2da06c <uniffi_pbcli_checksum_method_api_base@@Base+0x16d7e8>
│ │  	ldr	r4, [pc, #64]	@ (2d9f90 <uniffi_pbcli_checksum_method_api_base@@Base+0x16d70c>)
│ │  	ldmia.w	sp!, {r0, r2, r3, r4, r6, r7, r8, r9, fp}
│ │ -	and.w	sp, r1, sl, lsl #9
│ │ +	and.w	sp, r1, r1, ror #9
│ │  	vqshrun.s32	d20, q8, #4
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2da47c <uniffi_pbcli_checksum_method_api_base@@Base+0x16dbf8>
│ │  	str	r0, [r0, r0]
│ │  	b.n	2da2a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x16da22>
│ │  	movs	r4, r3
│ │  	b.n	2d9a8a <uniffi_pbcli_checksum_method_api_base@@Base+0x16d206>
│ │ @@ -680350,15 +680350,15 @@
│ │  	b.n	2da70a <uniffi_pbcli_checksum_method_api_base@@Base+0x16de86>
│ │  	ands	r0, r0
│ │  	b.n	2da70e <uniffi_pbcli_checksum_method_api_base@@Base+0x16de8a>
│ │  	bfcsel	10, 2d97ce <uniffi_pbcli_checksum_method_api_base@@Base+0x16cf4a>, 12, ge
│ │  	movs	r4, r0
│ │  	b.n	2da316 <uniffi_pbcli_checksum_method_api_base@@Base+0x16da92>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r1, r5, r6, r7, sl, fp, sp}
│ │ +	ldmia.w	sp!, {r0, r3, r8, sl, fp, sp}
│ │  	vsubl.u16	<illegal reg q12.5>, d12, d26
│ │  	vaddl.u16	<illegal reg q9.5>, d10, d0
│ │  	b.n	2da726 <uniffi_pbcli_checksum_method_api_base@@Base+0x16dea2>
│ │  			@ <UNDEFINED> instruction: 0xffffeaff
│ │  	ldr	r3, [pc, #960]	@ (2da3ac <uniffi_pbcli_checksum_method_api_base@@Base+0x16db28>)
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2da50c <uniffi_pbcli_checksum_method_api_base@@Base+0x16dc88>
│ │ @@ -681120,42 +681120,42 @@
│ │  	movs	r0, #48	@ 0x30
│ │  	b.n	2da1a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x16d920>
│ │  	movs	r0, r0
│ │  	b.n	2da788 <uniffi_pbcli_checksum_method_api_base@@Base+0x16df04>
│ │  	movs	r0, #2
│ │  	b.n	2da78c <uniffi_pbcli_checksum_method_api_base@@Base+0x16df08>
│ │  	mrc2	10, 6, lr, cr13, cr15, {7}	@ <UNPREDICTABLE>
│ │ -	cmp	r0, #174	@ 0xae
│ │ +	cmp	r0, #213	@ 0xd5
│ │  	vmull.p<illegal width 16>	<illegal reg q13.5>, d12, d21
│ │ -			@ <UNDEFINED> instruction: 0xffda2b06
│ │ +			@ <UNDEFINED> instruction: 0xffda2b2d
│ │  	vshr.u16	q14, <illegal reg q14.5>, #4
│ │ -	vmlsl.u16	q9, d10, d2[1]
│ │ +	vqshlu.s16	q9, <illegal reg q8.5>, #10
│ │  			@ <UNDEFINED> instruction: 0xffdc8b92
│ │ -			@ <UNDEFINED> instruction: 0xffda2ab2
│ │ +			@ <UNDEFINED> instruction: 0xffda2ad9
│ │  	vaddl.u16	q14, d12, d25
│ │ -	vmlal.u16	q9, d10, d10
│ │ -	vrsubhn.i32	d18, q6, q15
│ │ +	vqshrun.s32	d18, <illegal reg q8.5>, #6
│ │ +	vqshlu.s16	q9, <illegal reg q2.5>, #12
│ │  			@ <UNDEFINED> instruction: 0xffdcbba5
│ │  			@ <UNDEFINED> instruction: 0xffda9db6
│ │  	vsri.16	d17, d4, #6
│ │  	movs	r0, r0
│ │ -	ldr	r6, [pc, #872]	@ (2daa10 <uniffi_pbcli_checksum_method_api_base@@Base+0x16e18c>)
│ │ +	ldr	r7, [pc, #4]	@ (2da6ac <uniffi_pbcli_checksum_method_api_base@@Base+0x16de28>)
│ │  	vmul.f16	<illegal reg q8.5>, q14, d0[0]
│ │  	movs	r0, r0
│ │  	adds	r0, r5, r7
│ │  	movs	r0, r0
│ │ -	movs	r6, #106	@ 0x6a
│ │ +	movs	r6, #145	@ 0x91
│ │  			@ <UNDEFINED> instruction: 0xffdcbbe1
│ │ -	vabdl.u16	q9, d10, d10
│ │ +	vqshl.u16	d18, d17, #10
│ │  	vmull.u16	<illegal reg q13.5>, d28, d1
│ │ -			@ <UNDEFINED> instruction: 0xffda29aa
│ │ -	vqrshrn.u32	d18, q11, #4
│ │ -			@ <UNDEFINED> instruction: 0xffdc2a5e
│ │ +			@ <UNDEFINED> instruction: 0xffda29d1
│ │ +			@ <UNDEFINED> instruction: 0xffdc299d
│ │ +	vmlsl.u16	q9, d28, d5
│ │  			@ <UNDEFINED> instruction: 0xffdcbfd5
│ │ -	vmlsl.u16	q9, d26, d6[3]
│ │ +	vqshl.u16	d18, d5, #10
│ │  	vqdmulh.s16	<illegal reg q13.5>, q6, d5[2]
│ │  	vqshrun.s32	d20, q8, #6
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2dabfc <uniffi_pbcli_checksum_method_api_base@@Base+0x16e378>
│ │  	ands	r1, r0
│ │  	b.n	2daa26 <uniffi_pbcli_checksum_method_api_base@@Base+0x16e1a2>
│ │  	str	r0, [r0, r0]
│ │ @@ -681333,19 +681333,19 @@
│ │  	movs	r0, #20
│ │  	b.n	2da3b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x16db2c>
│ │  	movs	r0, r0
│ │  	b.n	2da994 <uniffi_pbcli_checksum_method_api_base@@Base+0x16e110>
│ │  	movs	r0, #2
│ │  	b.n	2da998 <uniffi_pbcli_checksum_method_api_base@@Base+0x16e114>
│ │  			@ <UNDEFINED> instruction: 0xffd7eaff
│ │ -	movs	r4, #190	@ 0xbe
│ │ +	movs	r4, #229	@ 0xe5
│ │  	vmull.u16	<illegal reg q10.5>, d12, d20
│ │ -	vraddhn.i32	d18, q5, q9
│ │ +	vmls.i16	q9, q5, d1[1]
│ │  			@ <UNDEFINED> instruction: 0xffdc5b88
│ │ -	vmls.i16	q9, q5, d6[0]
│ │ +	vmls.i16	q9, q5, d5[3]
│ │  			@ <UNDEFINED> instruction: 0xffdc5bac
│ │  	vqshrun.s32	d20, q8, #6
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2dadb8 <uniffi_pbcli_checksum_method_api_base@@Base+0x16e534>
│ │  	ands	r0, r0
│ │  	b.n	2dabe2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16e35e>
│ │  	movs	r4, r2
│ │ @@ -681546,20 +681546,20 @@
│ │  	asrs	r4, r3, #32
│ │  	b.n	2da594 <uniffi_pbcli_checksum_method_api_base@@Base+0x16dd10>
│ │  	movs	r0, r0
│ │  	b.n	2dab78 <uniffi_pbcli_checksum_method_api_base@@Base+0x16e2f4>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2dab7c <uniffi_pbcli_checksum_method_api_base@@Base+0x16e2f8>
│ │  	b.n	2db190 <uniffi_pbcli_checksum_method_api_base@@Base+0x16e90c>
│ │ -	add.w	r2, r0, r2, lsr #10
│ │ +	add.w	r2, r0, r9, ror #10
│ │  	vqshrun.s32	d21, <illegal reg q9.5>, #4
│ │ -	vrshr.u16	q9, q11, #5
│ │ +	vrshr.u64	d18, d13, #37
│ │  	vqshrun.s32	d21, <illegal reg q3.5>, #4
│ │  			@ <UNDEFINED> instruction: 0xffdb6fa9
│ │ -	vrshr.u16	d18, d26, #6
│ │ +	vmlal.u16	q9, d10, d1[2]
│ │  			@ <UNDEFINED> instruction: 0xffdc48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2daf9c <uniffi_pbcli_checksum_method_api_base@@Base+0x16e718>
│ │  	beq.n	2dab04 <uniffi_pbcli_checksum_method_api_base@@Base+0x16e280>
│ │  	b.n	2daf20 <uniffi_pbcli_checksum_method_api_base@@Base+0x16e69c>
│ │  	ands	r0, r0
│ │  	b.n	2dadca <uniffi_pbcli_checksum_method_api_base@@Base+0x16e546>
│ │ @@ -681818,23 +681818,23 @@
│ │  	movs	r4, r1
│ │  	b.n	2da7e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16df5e>
│ │  	lsrs	r2, r0, #12
│ │  	b.n	2db3be <uniffi_pbcli_checksum_method_api_base@@Base+0x16eb3a>
│ │  	movs	r4, r1
│ │  	b.n	2da7ca <uniffi_pbcli_checksum_method_api_base@@Base+0x16df46>
│ │  			@ <UNDEFINED> instruction: 0xfff7eaff
│ │ -	movs	r1, #14
│ │ -	vqdmulh.s16	<illegal reg q14.5>, q6, d3[2]
│ │ -	vaddl.u16	q9, d11, d26
│ │ -			@ <UNDEFINED> instruction: 0xffdcdb7f
│ │ -	vaddl.u16	q9, d11, d14
│ │ -			@ <UNDEFINED> instruction: 0xffdcdb63
│ │ +	movs	r1, #53	@ 0x35
│ │ +	vmull.u16	<illegal reg q14.5>, d28, d10
│ │ +	vshr.u16	q9, <illegal reg q0.5>, #5
│ │ +			@ <UNDEFINED> instruction: 0xffdcdba6
│ │ +	vshr.u16	d18, d21, #5
│ │ +			@ <UNDEFINED> instruction: 0xffdcdb8a
│ │  			@ <UNDEFINED> instruction: 0xffdb9c58
│ │ -	vshr.u16	q9, q3, #5
│ │ -			@ <UNDEFINED> instruction: 0xffdcdbab
│ │ +	vshr.u16	q9, <illegal reg q14.5>, #5
│ │ +			@ <UNDEFINED> instruction: 0xffdcdbd2
│ │  	vshr.u16	d19, d4, #5
│ │  	b.n	2da80e <uniffi_pbcli_checksum_method_api_base@@Base+0x16df8a>
│ │  	movs	r0, r0
│ │  	b.n	2db398 <uniffi_pbcli_checksum_method_api_base@@Base+0x16eb14>
│ │  	movs	r1, r1
│ │  	lsrs	r0, r0, #8
│ │  	movs	r0, #0
│ │ @@ -682535,25 +682535,25 @@
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r0, r2, r5, r6, r7, r9, sl, fp, ip, sp, lr, pc}
│ │  	ldmia	r2, {r0, r1, r2, r3, r4, r5, r6, r7}
│ │  	movs	r5, r0
│ │  	b.n	2db652 <uniffi_pbcli_checksum_method_api_base@@Base+0x16edce>
│ │  	ldrsh	r7, [r1, r5]
│ │  			@ <UNDEFINED> instruction: 0xeb00fee2
│ │ -			@ <UNDEFINED> instruction: 0xeaff1d62
│ │ +			@ <UNDEFINED> instruction: 0xeaff1d89
│ │  			@ <UNDEFINED> instruction: 0xffdc6af5
│ │ -			@ <UNDEFINED> instruction: 0xffda1a92
│ │ +			@ <UNDEFINED> instruction: 0xffda1ab9
│ │  	vmlal.u16	q11, d12, d21
│ │ -			@ <UNDEFINED> instruction: 0xffda1b1a
│ │ +			@ <UNDEFINED> instruction: 0xffda1b41
│ │  	vmlal.u16	q11, d28, d29
│ │ -	vmull.p<illegal width 16>	<illegal reg q8.5>, d10, d18
│ │ -			@ <UNDEFINED> instruction: 0xffdc1d7e
│ │ +	vqrdmlah.s16	<illegal reg q8.5>, q5, d1[1]
│ │ +			@ <UNDEFINED> instruction: 0xffdc1da5
│ │  			@ <UNDEFINED> instruction: 0xffdc6b11
│ │ -	vmul.f16	<illegal reg q8.5>, q13, d2[0]
│ │ -			@ <UNDEFINED> instruction: 0xffdc1b86
│ │ +	vmul.f16	<illegal reg q8.5>, q13, d1[3]
│ │ +			@ <UNDEFINED> instruction: 0xffdc1bad
│ │  	vqshrn.u32	d22, <illegal reg q4.5>, #4
│ │  	vqshrun.s32	d20, q8, #6
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2db86c <uniffi_pbcli_checksum_method_api_base@@Base+0x16efe8>
│ │  	ands	r1, r0
│ │  	b.n	2db696 <uniffi_pbcli_checksum_method_api_base@@Base+0x16ee12>
│ │  	str	r0, [r0, r0]
│ │ @@ -682733,16 +682733,16 @@
│ │  	and.w	r0, r0, r0, lsl #20
│ │  	b.n	2dbc1e <uniffi_pbcli_checksum_method_api_base@@Base+0x16f39a>
│ │  	movs	r5, r0
│ │  	b.n	2db822 <uniffi_pbcli_checksum_method_api_base@@Base+0x16ef9e>
│ │  	beq.n	2db51c <uniffi_pbcli_checksum_method_api_base@@Base+0x16ec98>
│ │  	b.n	2db97c <uniffi_pbcli_checksum_method_api_base@@Base+0x16f0f8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r3, r4, r7, fp, ip}
│ │ -			@ <UNDEFINED> instruction: 0xffdc17c6
│ │ +	ldmia.w	sp!, {r0, r6, r7, fp, ip}
│ │ +			@ <UNDEFINED> instruction: 0xffdc17ed
│ │  			@ <UNDEFINED> instruction: 0xffdc48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2dba14 <uniffi_pbcli_checksum_method_api_base@@Base+0x16f190>
│ │  	beq.n	2db51c <uniffi_pbcli_checksum_method_api_base@@Base+0x16ec98>
│ │  	b.n	2db998 <uniffi_pbcli_checksum_method_api_base@@Base+0x16f114>
│ │  	str	r3, [r0, #0]
│ │  	b.n	2db842 <uniffi_pbcli_checksum_method_api_base@@Base+0x16efbe>
│ │ @@ -683272,20 +683272,20 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	2dc0c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16f83e>
│ │  	movs	r6, r0
│ │  	b.n	2dc0c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x16f842>
│ │  	asrs	r4, r0, #2
│ │  	b.n	2dc0ca <uniffi_pbcli_checksum_method_api_base@@Base+0x16f846>
│ │  			@ <UNDEFINED> instruction: 0xffaaeaff
│ │ -	asrs	r2, r6, #17
│ │ +	asrs	r1, r3, #18
│ │  			@ <UNDEFINED> instruction: 0xffdca9d9
│ │  			@ <UNDEFINED> instruction: 0xffda8f20
│ │ -			@ <UNDEFINED> instruction: 0xffdb6e77
│ │ +			@ <UNDEFINED> instruction: 0xffdb6e9e
│ │  			@ <UNDEFINED> instruction: 0xffdc1b01
│ │ -	vsubw.u16	<illegal reg q8.5>, q5, d18
│ │ +			@ <UNDEFINED> instruction: 0xffda1349
│ │  	vmlal.u16	q13, d28, d9
│ │  	vmlal.u16	q10, d10, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2dbcf2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16f46e>
│ │  	asrs	r0, r5, #32
│ │  	b.n	2db4f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x16ec70>
│ │  	lsls	r0, r0, #2
│ │ @@ -683302,15 +683302,15 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	2dc112 <uniffi_pbcli_checksum_method_api_base@@Base+0x16f88e>
│ │  	bl	7374d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x5cac4e>
│ │  	asrs	r4, r0, #1
│ │  	b.n	2db4da <uniffi_pbcli_checksum_method_api_base@@Base+0x16ec56>
│ │  	bl	7374da <uniffi_pbcli_checksum_method_api_base@@Base+0x5cac56>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r4, r6, r7, r9, ip}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r5, r6, r7, r9, ip}
│ │  			@ <UNDEFINED> instruction: 0xffdc4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2dbf08 <uniffi_pbcli_checksum_method_api_base@@Base+0x16f684>
│ │  	beq.n	2db910 <uniffi_pbcli_checksum_method_api_base@@Base+0x16f08c>
│ │  	b.n	2dbe8c <uniffi_pbcli_checksum_method_api_base@@Base+0x16f608>
│ │  	strb	r1, [r0, #0]
│ │  	b.n	2dbd36 <uniffi_pbcli_checksum_method_api_base@@Base+0x16f4b2>
│ │ @@ -683926,28 +683926,28 @@
│ │  	str	r0, [r0, #0]
│ │  	b.n	2dc69a <uniffi_pbcli_checksum_method_api_base@@Base+0x16fe16>
│ │  	movs	r6, r0
│ │  	b.n	2dc69e <uniffi_pbcli_checksum_method_api_base@@Base+0x16fe1a>
│ │  	asrs	r1, r0, #3
│ │  	b.n	2dc6a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16fe1e>
│ │  	mcr2	10, 7, lr, cr2, cr15, {7}	@ <UNPREDICTABLE>
│ │ -	asrs	r2, r1, #10
│ │ -	vsra.u64	d17, d30, #36
│ │ +	asrs	r1, r6, #10
│ │ +	vmla.f16	<illegal reg q8.5>, q14, d5[2]
│ │  			@ <UNDEFINED> instruction: 0xffdc2fd0
│ │  	vqshl.u16	d16, d16, #11
│ │  	movs	r0, r0
│ │ -	asrs	r2, r4, #8
│ │ +	asrs	r1, r1, #9
│ │  	vshr.u16	d19, d20, #4
│ │ -	vqrdmulh.s16	q8, <illegal reg q5.5>, d2[1]
│ │ +			@ <UNDEFINED> instruction: 0xffdb0d71
│ │  			@ <UNDEFINED> instruction: 0xffdc2b5c
│ │  			@ <UNDEFINED> instruction: 0xffdb2d9a
│ │  	vqshl.u16	<illegal reg q8.5>, <illegal reg q6.5>, #11
│ │  			@ <UNDEFINED> instruction: 0xffdb5cd0
│ │  	vqshlu.s16	q10, <illegal reg q10.5>, #10
│ │ -			@ <UNDEFINED> instruction: 0xffda0d82
│ │ +			@ <UNDEFINED> instruction: 0xffda0da9
│ │  			@ <UNDEFINED> instruction: 0xffdc2b94
│ │  	vshr.u16	d17, d0, #5
│ │  	b.n	2dbac2 <uniffi_pbcli_checksum_method_api_base@@Base+0x16f23e>
│ │  	movs	r0, r0
│ │  	b.n	2dc648 <uniffi_pbcli_checksum_method_api_base@@Base+0x16fdc4>
│ │  	movs	r5, r0
│ │  	subs	r0, r0, r0
│ │ @@ -684677,16 +684677,16 @@
│ │  	movs	r0, r4
│ │  	lsrs	r4, r2, #24
│ │  	movs	r0, r4
│ │  	lsrs	r0, r5, #24
│ │  	movs	r0, r4
│ │  	lsrs	r4, r1, #22
│ │  	movs	r0, r4
│ │ -	ldrh	r0, [r6, #54]	@ 0x36
│ │ -	vrshr.u16	<illegal reg q9.5>, <illegal reg q5.5>, #4
│ │ +	ldrh	r7, [r2, #56]	@ 0x38
│ │ +	vsubl.u16	<illegal reg q9.5>, d28, d2
│ │  			@ <UNDEFINED> instruction: 0xffdc4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2dcb3c <uniffi_pbcli_checksum_method_api_base@@Base+0x1702b8>
│ │  	beq.n	2dc634 <uniffi_pbcli_checksum_method_api_base@@Base+0x16fdb0>
│ │  	b.n	2dcac0 <uniffi_pbcli_checksum_method_api_base@@Base+0x17023c>
│ │  	strh	r3, [r0, #0]
│ │  	b.n	2dc96a <uniffi_pbcli_checksum_method_api_base@@Base+0x1700e6>
│ │ @@ -685380,15 +685380,15 @@
│ │  	lsls	r4, r7, #10
│ │  	b.n	2dc744 <uniffi_pbcli_checksum_method_api_base@@Base+0x16fec0>
│ │  	strb	r4, [r7, #3]
│ │  	b.n	2dc748 <uniffi_pbcli_checksum_method_api_base@@Base+0x16fec4>
│ │  	movs	r7, r0
│ │  	b.n	2dcf7a <uniffi_pbcli_checksum_method_api_base@@Base+0x1706f6>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r3, r5, r8, fp, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r6, r8, fp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffdc4eb8
│ │  	vqrshrun.s32	d16, q2, #6
│ │  	movs	r0, r4
│ │  	lsls	r4, r1, #29
│ │  	movs	r0, r4
│ │  	lsls	r0, r2, #29
│ │  	movs	r0, r4
│ │ @@ -685777,15 +685777,15 @@
│ │  	asrs	r4, r0, #32
│ │  	b.n	2dd2ee <uniffi_pbcli_checksum_method_api_base@@Base+0x170a6a>
│ │  	ldmia	r3!, {r1, r5, r6, r7}
│ │  			@ <UNDEFINED> instruction: 0xeb00ff85
│ │  			@ <UNDEFINED> instruction: 0xeaff8004
│ │  	b.n	2dd2fa <uniffi_pbcli_checksum_method_api_base@@Base+0x170a76>
│ │  			@ <UNDEFINED> instruction: 0xff83eaff
│ │ -	strh	r0, [r6, #60]	@ 0x3c
│ │ +	strh	r7, [r2, #62]	@ 0x3e
│ │  	vmls.f16	<illegal reg q9.5>, q6, d2[1]
│ │  	vqshrun.s32	d20, q8, #5
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2dd4e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x170c64>
│ │  	ands	r0, r0
│ │  	b.n	2dd312 <uniffi_pbcli_checksum_method_api_base@@Base+0x170a8e>
│ │  	ldrsb	r6, [r7, r3]
│ │ @@ -685819,15 +685819,15 @@
│ │  			@ <UNDEFINED> instruction: 0xffaeeb00
│ │  	movs	r4, r0
│ │  	b.n	2dd356 <uniffi_pbcli_checksum_method_api_base@@Base+0x170ad2>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	2dd75e <uniffi_pbcli_checksum_method_api_base@@Base+0x170eda>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r2, r5, r7, sl, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r6, r7, sl, pc}
│ │  			@ <UNDEFINED> instruction: 0xffdc4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2dd548 <uniffi_pbcli_checksum_method_api_base@@Base+0x170cc4>
│ │  	strh	r3, [r0, #0]
│ │  	b.n	2dd372 <uniffi_pbcli_checksum_method_api_base@@Base+0x170aee>
│ │  	str	r2, [r0, #0]
│ │  	b.n	2dd376 <uniffi_pbcli_checksum_method_api_base@@Base+0x170af2>
│ │ @@ -686399,17 +686399,17 @@
│ │  	b.n	2dd9fe <uniffi_pbcli_checksum_method_api_base@@Base+0x17117a>
│ │  	lsls	r0, r6, #10
│ │  	b.n	2dcffe <uniffi_pbcli_checksum_method_api_base@@Base+0x17077a>
│ │  			@ <UNDEFINED> instruction: 0xffafeaff
│ │  	movs	r0, r0
│ │  	b.n	2ddc3a <uniffi_pbcli_checksum_method_api_base@@Base+0x1713b6>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r4, r5, r6, r7, r9, pc}
│ │ -	vrshr.u64	q12, q6, #36
│ │ -			@ <UNDEFINED> instruction: 0xffdc8348
│ │ +	ldmia.w	sp!, {r0, r1, r2, r4, r8, r9, pc}
│ │ +	vsubw.u16	q12, q6, d3
│ │ +			@ <UNDEFINED> instruction: 0xffdc836f
│ │  			@ <UNDEFINED> instruction: 0xffdc4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2dda2c <uniffi_pbcli_checksum_method_api_base@@Base+0x1711a8>
│ │  	beq.n	2dd51c <uniffi_pbcli_checksum_method_api_base@@Base+0x170c98>
│ │  	b.n	2dd9b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x17112c>
│ │  	str	r0, [sp, #12]
│ │  	b.n	2dd85a <uniffi_pbcli_checksum_method_api_base@@Base+0x170fd6>
│ │ @@ -686655,17 +686655,17 @@
│ │  	b.n	2ddc2e <uniffi_pbcli_checksum_method_api_base@@Base+0x1713aa>
│ │  	lsrs	r7, r1, #8
│ │  	orr.w	r0, r0, #8912896	@ 0x880000
│ │  	b.n	2dda6a <uniffi_pbcli_checksum_method_api_base@@Base+0x1711e6>
│ │  	beq.n	2dd764 <uniffi_pbcli_checksum_method_api_base@@Base+0x170ee0>
│ │  	b.n	2ddbc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x171340>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r3, r4, r6, r7, r9, sl, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r9, sl, fp, ip, sp, lr}
│ │  	vmls.f16	<illegal reg q8.5>, q14, d1[2]
│ │ -	vqrdmlah.s16	<illegal reg q11.5>, q5, d0[0]
│ │ +	vqrdmlah.s16	<illegal reg q11.5>, q5, d7[2]
│ │  	vmls.f16	<illegal reg q8.5>, q6, d1[1]
│ │  			@ <UNDEFINED> instruction: 0xffdafddc
│ │  	movs	r7, r3
│ │  	stc2l	0, cr0, [ip, #-124]	@ 0xffffff84
│ │  	stc2l	0, cr0, [r4], #-124	@ 0xffffff84
│ │  	mcrr2	0, 1, r0, r4, cr15
│ │  	ldc2l	0, cr0, [r0, #-124]!	@ 0xffffff84
│ │ @@ -686784,15 +686784,15 @@
│ │  	b.n	2dd370 <uniffi_pbcli_checksum_method_api_base@@Base+0x170aec>
│ │  	ldr	r7, [pc, #840]	@ (2ddba0 <uniffi_pbcli_checksum_method_api_base@@Base+0x17131c>)
│ │  	add.w	r0, r1, r0
│ │  	b.n	2ddefe <uniffi_pbcli_checksum_method_api_base@@Base+0x17167a>
│ │  	ands	r1, r0
│ │  	lsls	r0, r4, #14
│ │  			@ <UNDEFINED> instruction: 0xffd5eaff
│ │ -	ldrb	r4, [r1, #19]
│ │ +	ldrb	r3, [r6, #19]
│ │  	vaddw.u16	q13, q14, d9
│ │  			@ <UNDEFINED> instruction: 0xffda4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2ddd90 <uniffi_pbcli_checksum_method_api_base@@Base+0x17150c>
│ │  	str	r3, [r0, r0]
│ │  	b.n	2ddbba <uniffi_pbcli_checksum_method_api_base@@Base+0x171336>
│ │  	str	r1, [r0, #0]
│ │ @@ -686984,16 +686984,16 @@
│ │  	b.n	2ddd56 <uniffi_pbcli_checksum_method_api_base@@Base+0x1714d2>
│ │  	beq.n	2dda48 <uniffi_pbcli_checksum_method_api_base@@Base+0x1711c4>
│ │  	b.n	2ddeb0 <uniffi_pbcli_checksum_method_api_base@@Base+0x17162c>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r2, r4, r9, fp, ip, sp, lr, pc}
│ │  	movs	r7, r3
│ │  	vst4.8	{d16-d19}, [r8 :64]
│ │ -	ldrb	r0, [r4, #12]
│ │ -			@ <UNDEFINED> instruction: 0xffdc7b2f
│ │ +	ldrb	r7, [r0, #13]
│ │ +			@ <UNDEFINED> instruction: 0xffdc7b56
│ │  			@ <UNDEFINED> instruction: 0xffdcf980
│ │  	movs	r7, r3
│ │  	ldr	r7, [pc, #960]	@ (2dddf4 <uniffi_pbcli_checksum_method_api_base@@Base+0x171570>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2ddf54 <uniffi_pbcli_checksum_method_api_base@@Base+0x1716d0>
│ │  	beq.n	2dda64 <uniffi_pbcli_checksum_method_api_base@@Base+0x1711e0>
│ │  	b.n	2dded8 <uniffi_pbcli_checksum_method_api_base@@Base+0x171654>
│ │ @@ -687884,16 +687884,16 @@
│ │  	lsls	r0, r7, #3
│ │  	b.n	2ddd06 <uniffi_pbcli_checksum_method_api_base@@Base+0x171482>
│ │  	movs	r2, r1
│ │  	b.n	2de53a <uniffi_pbcli_checksum_method_api_base@@Base+0x171cb6>
│ │  	beq.n	2de234 <uniffi_pbcli_checksum_method_api_base@@Base+0x1719b0>
│ │  	b.n	2de694 <uniffi_pbcli_checksum_method_api_base@@Base+0x171e10>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r4, r5, r8, r9, ip, sp, lr}
│ │ -	vrsra.u16	<illegal reg q11.5>, q0, #4
│ │ +	ldmia.w	sp!, {r0, r1, r2, r4, r6, r8, r9, ip, sp, lr}
│ │ +	vrsra.u16	<illegal reg q11.5>, <illegal reg q11.5>, #4
│ │  			@ <UNDEFINED> instruction: 0xffdc4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2de72c <uniffi_pbcli_checksum_method_api_base@@Base+0x171ea8>
│ │  	beq.n	2de22c <uniffi_pbcli_checksum_method_api_base@@Base+0x1719a8>
│ │  	b.n	2de6b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x171e2c>
│ │  	str	r3, [r0, #0]
│ │  	b.n	2de55a <uniffi_pbcli_checksum_method_api_base@@Base+0x171cd6>
│ │ @@ -688086,15 +688086,15 @@
│ │  	strb	r0, [r0, #0]
│ │  	lsls	r0, r4, #15
│ │  	movs	r7, r0
│ │  	b.n	2de6fe <uniffi_pbcli_checksum_method_api_base@@Base+0x171e7a>
│ │  	beq.n	2de3f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x171b74>
│ │  	b.n	2de858 <uniffi_pbcli_checksum_method_api_base@@Base+0x171fd4>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r9, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r5, r9, ip, sp, lr}
│ │  	vmull.p<illegal width 16>	q13, d28, d7
│ │  			@ <UNDEFINED> instruction: 0xffdaeff4
│ │  	movs	r7, r3
│ │  	vmov.i32	d0, #79	@ 0x0000004f
│ │  	vshr.s32	d0, d15, #20
│ │  	vqadd.s32	d16, d0, d15
│ │  	ldr	r3, [pc, #960]	@ (2de7a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x171f1c>)
│ │ @@ -688304,15 +688304,15 @@
│ │  	str	r4, [r6, #28]
│ │  	b.n	2de0b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x17182c>
│ │  	movs	r6, r0
│ │  	b.n	2de8e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x17205e>
│ │  	beq.n	2de5d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x171d50>
│ │  	b.n	2dea3c <uniffi_pbcli_checksum_method_api_base@@Base+0x1721b8>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r2, r4, r5, r6, r7, r8, r9, sl, fp, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r4, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffdcef2d
│ │  			@ <UNDEFINED> instruction: 0xffd9ef3c
│ │  	movs	r7, r3
│ │  	mcr	0, 0, r0, cr0, cr15, {0}
│ │  	stcl	0, cr0, [ip, #124]!	@ 0x7c
│ │  	mcr	0, 4, r0, cr12, cr15, {0}
│ │  	mrc	0, 3, r0, cr8, cr15, {0}
│ │ @@ -688670,16 +688670,16 @@
│ │  	b.n	2dec22 <uniffi_pbcli_checksum_method_api_base@@Base+0x17239e>
│ │  	movs	r0, #4
│ │  	b.n	2dec26 <uniffi_pbcli_checksum_method_api_base@@Base+0x1723a2>
│ │  	bls.n	2de91e <uniffi_pbcli_checksum_method_api_base@@Base+0x17209a>
│ │  			@ <UNDEFINED> instruction: 0xfa064000
│ │  	b.n	2de402 <uniffi_pbcli_checksum_method_api_base@@Base+0x171b7e>
│ │  	vpmin.u8	q15, <illegal reg q9.5>, <illegal reg q15.5>
│ │ -	ldr	r0, [r4, #100]	@ 0x64
│ │ -	vqrdmulh.s16	q12, q6, d2[3]
│ │ +	ldr	r7, [r0, #104]	@ 0x68
│ │ +			@ <UNDEFINED> instruction: 0xffdc8d91
│ │  	vmlal.u16	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2dec42 <uniffi_pbcli_checksum_method_api_base@@Base+0x1723be>
│ │  	str	r2, [r6, r2]
│ │  	add.w	pc, r0, lr, ror #1
│ │  	b.n	2dee0a <uniffi_pbcli_checksum_method_api_base@@Base+0x172586>
│ │  	ldr	r1, [pc, #212]	@ (2de9e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x17215c>)
│ │ @@ -700641,19 +700641,19 @@
│ │  	b.n	2e5832 <uniffi_pbcli_checksum_method_api_base@@Base+0x178fae>
│ │  	movs	r0, #2
│ │  	b.n	2e5d5c <uniffi_pbcli_checksum_method_api_base@@Base+0x1794d8>
│ │  	movs	r7, r0
│ │  	stmia.w	r3, {r4}
│ │  	b.n	2e6456 <uniffi_pbcli_checksum_method_api_base@@Base+0x179bd2>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r1, r3, r4, r6, r7, r8, ip, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffdb6ff6
│ │ +	ldmia.w	sp!, {r0, r9, ip, sp, lr}
│ │ +	vshr.u16	d23, d13, #5
│ │  	vqshl.u64	<illegal reg q11.5>, q15, #27
│ │ -	vmla.f16	<illegal reg q11.5>, q5, d6[3]
│ │ -	vmla.f16	<illegal reg q11.5>, <illegal reg q5.5>, d6[0]
│ │ +	vsra.u64	d23, d5, #38
│ │ +	vmla.f16	<illegal reg q11.5>, <illegal reg q5.5>, d5[3]
│ │  	vmul.f16	<illegal reg q11.5>, <illegal reg q5.5>, d6[1]
│ │  	vsri.64	<illegal reg q14.5>, q2, #38
│ │  	bmi.n	2e5cde <uniffi_pbcli_checksum_method_api_base@@Base+0x17945a>
│ │  	bmi.n	2e5ce0 <uniffi_pbcli_checksum_method_api_base@@Base+0x17945c>
│ │  	bmi.n	2e5ce2 <uniffi_pbcli_checksum_method_api_base@@Base+0x17945e>
│ │  	bmi.n	2e5ce4 <uniffi_pbcli_checksum_method_api_base@@Base+0x179460>
│ │  	bmi.n	2e5ce6 <uniffi_pbcli_checksum_method_api_base@@Base+0x179462>
│ │ @@ -713833,25 +713833,25 @@
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r1, r2, r4, r5, r6, fp, sp, lr}
│ │  	vmlsl.u16	<illegal reg q14.5>, d26, d4[0]
│ │  	movs	r3, r3
│ │  	bkpt	0x00ba
│ │  			@ <UNDEFINED> instruction: 0xffd898bf
│ │  	vmlal.u16	<illegal reg q12.5>, d25, d29
│ │ -	vmls.i16	<illegal reg q12.5>, <illegal reg q12.5>, d0[0]
│ │ +	vmls.i16	<illegal reg q12.5>, <illegal reg q12.5>, d7[2]
│ │  			@ <UNDEFINED> instruction: 0xffda0a7d
│ │  			@ <UNDEFINED> instruction: 0xffd94f00
│ │  	vqrshrun.s32	d25, <illegal reg q1.5>, #6
│ │ -	vqrshrn.u32	d17, <illegal reg q5.5>, #7
│ │ +			@ <UNDEFINED> instruction: 0xffd91982
│ │  	vmull.p<illegal width 16>	<illegal reg q13.5>, d11, d0
│ │  			@ <UNDEFINED> instruction: 0xffd87ffe
│ │  			@ <UNDEFINED> instruction: 0xffd9df5e
│ │  	vqshrun.s32	d19, <illegal reg q7.5>, #7
│ │  			@ <UNDEFINED> instruction: 0xffdaaf1f
│ │ -	vmls.f16	q10, <illegal reg q12.5>, d2[2]
│ │ +	vrsubhn.i32	d20, <illegal reg q4.5>, <illegal reg q4.5>
│ │  	vaddl.u16	<illegal reg q8.5>, d11, d0
│ │  	b.n	2ececa <uniffi_pbcli_checksum_method_api_base@@Base+0x180646>
│ │  	lsls	r1, r1, #11
│ │  	b.n	2ed18e <uniffi_pbcli_checksum_method_api_base@@Base+0x18090a>
│ │  	movs	r0, #0
│ │  	b.n	2ecc14 <uniffi_pbcli_checksum_method_api_base@@Base+0x180390>
│ │  	movs	r0, r0
│ │ @@ -713975,24 +713975,24 @@
│ │  	lsls	r0, r4, #1
│ │  	b.n	2ed3e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x180b5e>
│ │  	movs	r0, #129	@ 0x81
│ │  	b.n	2ed3e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x180b62>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2ecdc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x180544>
│ │  	iteet	ge
│ │ -	andge.w	r2, r0, r7, asr #28
│ │ +	andge.w	r2, r0, lr, lsl #29
│ │  	vaddllt.u16	<illegal reg q8.5>, d11, d8
│ │  	blt.n	2ec7f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x17ff70>	@ unpredictable branch in IT block
│ │  
│ │  	movge	r0, #134	@ 0x86
│ │  	b.n	2ed3fa <uniffi_pbcli_checksum_method_api_base@@Base+0x180b76>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2ecddc <uniffi_pbcli_checksum_method_api_base@@Base+0x180558>
│ │  	stmia	r0!, {r1, r7}
│ │ -	and.w	r2, r0, r3, lsr #28
│ │ +	and.w	r2, r0, sl, ror #28
│ │  	vaddl.u16	<illegal reg q8.5>, d11, d0
│ │  	b.n	2ed40a <uniffi_pbcli_checksum_method_api_base@@Base+0x180b86>
│ │  	movs	r0, #48	@ 0x30
│ │  	b.n	2ed40e <uniffi_pbcli_checksum_method_api_base@@Base+0x180b8a>
│ │  	asrs	r0, r3, #1
│ │  	b.n	2ec7d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x17ff4e>
│ │  	asrs	r4, r3, #1
│ │ @@ -714198,16 +714198,16 @@
│ │  	asrs	r4, r1, #32
│ │  	b.n	2ec9bc <uniffi_pbcli_checksum_method_api_base@@Base+0x180138>
│ │  	movs	r0, r0
│ │  	b.n	2ecfa0 <uniffi_pbcli_checksum_method_api_base@@Base+0x18071c>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2ecfa4 <uniffi_pbcli_checksum_method_api_base@@Base+0x180720>
│ │  	ldr	r2, [sp, #568]	@ 0x238
│ │ -			@ <UNDEFINED> instruction: 0xeb00a558
│ │ -	vmla.i16	<illegal reg q11.5>, q5, d3[1]
│ │ +			@ <UNDEFINED> instruction: 0xeb00a57f
│ │ +	vshr.u16	<illegal reg q11.5>, q9, #6
│ │  			@ <UNDEFINED> instruction: 0xffdb4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2ed3b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x180b30>
│ │  	movs	r0, r0
│ │  	b.n	2ed53e <uniffi_pbcli_checksum_method_api_base@@Base+0x180cba>
│ │  	lsls	r4, r3, #1
│ │  	asrs	r0, r2, #23
│ │ @@ -714900,15 +714900,15 @@
│ │  	asrs	r4, r1, #32
│ │  	b.n	2ecf9c <uniffi_pbcli_checksum_method_api_base@@Base+0x180718>
│ │  	movs	r0, r0
│ │  	b.n	2ed580 <uniffi_pbcli_checksum_method_api_base@@Base+0x180cfc>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2ed584 <uniffi_pbcli_checksum_method_api_base@@Base+0x180d00>
│ │  	ldr	r5, [sp, #916]	@ 0x394
│ │ -			@ <UNDEFINED> instruction: 0xeafe23ed
│ │ +			@ <UNDEFINED> instruction: 0xeafe2414
│ │  	vaddl.u16	q8, d11, d8
│ │  	movs	r0, r0
│ │  	ldr	r7, [pc, #960]	@ (2ed834 <uniffi_pbcli_checksum_method_api_base@@Base+0x180fb0>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2ed994 <uniffi_pbcli_checksum_method_api_base@@Base+0x181110>
│ │  	beq.n	2ed494 <uniffi_pbcli_checksum_method_api_base@@Base+0x180c10>
│ │  	b.n	2ed918 <uniffi_pbcli_checksum_method_api_base@@Base+0x181094>
│ │ @@ -715103,23 +715103,23 @@
│ │  			@ <UNDEFINED> instruction: 0xebff0008
│ │  	b.n	2ed972 <uniffi_pbcli_checksum_method_api_base@@Base+0x1810ee>
│ │  	beq.n	2ed66c <uniffi_pbcli_checksum_method_api_base@@Base+0x180de8>
│ │  	b.n	2edacc <uniffi_pbcli_checksum_method_api_base@@Base+0x181248>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r2, r5, r6, r7, r8, sl, fp, sp}
│ │  	vmla.f16	<illegal reg q11.5>, q13, d0[0]
│ │ -	vqrshrn.u32	d22, <illegal reg q5.5>, #6
│ │ -			@ <UNDEFINED> instruction: 0xffdb3b8c
│ │ +			@ <UNDEFINED> instruction: 0xffda6982
│ │ +			@ <UNDEFINED> instruction: 0xffdb3bb3
│ │  	vsra.u16	d23, d20, #5
│ │ -	vmul.i16	q11, q13, d7[1]
│ │ +			@ <UNDEFINED> instruction: 0xffda68f6
│ │  	vsra.u16	<illegal reg q11.5>, q12, #5
│ │ -	vqshrn.u32	d22, <illegal reg q1.5>, #6
│ │ -	vsli.16	d31, d2, #11
│ │ +	vqshrn.u32	d22, q13, #6
│ │ +	vsli.16	d31, d25, #11
│ │  	vaddw.u16	<illegal reg q11.5>, q13, d20
│ │ -	vqshrn.u32	d22, <illegal reg q15.5>, #6
│ │ +	vmul.f16	q11, q5, d6[2]
│ │  			@ <UNDEFINED> instruction: 0xffdb48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2edb88 <uniffi_pbcli_checksum_method_api_base@@Base+0x181304>
│ │  	ands	r1, r0
│ │  	b.n	2eddb2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18152e>
│ │  	movs	r0, r0
│ │  	b.n	2edd16 <uniffi_pbcli_checksum_method_api_base@@Base+0x181492>
│ │ @@ -715258,16 +715258,16 @@
│ │  	b.n	2edada <uniffi_pbcli_checksum_method_api_base@@Base+0x181256>
│ │  	asrs	r7, r0, #32
│ │  	b.n	2edade <uniffi_pbcli_checksum_method_api_base@@Base+0x18125a>
│ │  	movs	r6, #201	@ 0xc9
│ │  	b.n	2edda2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18151e>
│ │  	pop	{r0, r3, r6, r7, pc}
│ │  			@ <UNDEFINED> instruction: 0xeb00ffe8
│ │ -			@ <UNDEFINED> instruction: 0xeaff676f
│ │ -	vqshl.u64	d22, d19, #27
│ │ +			@ <UNDEFINED> instruction: 0xeaff6796
│ │ +	vqshl.u64	q11, q5, #27
│ │  	vqshrun.s32	d20, q8, #5
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2edcd4 <uniffi_pbcli_checksum_method_api_base@@Base+0x181450>
│ │  	movs	r0, r0
│ │  	b.n	2ede5e <uniffi_pbcli_checksum_method_api_base@@Base+0x1815da>
│ │  	movs	r6, r1
│ │  	lsrs	r0, r0, #8
│ │ @@ -715317,15 +715317,15 @@
│ │  	b.n	2edb66 <uniffi_pbcli_checksum_method_api_base@@Base+0x1812e2>
│ │  	asrs	r5, r0, #32
│ │  	b.n	2edb6a <uniffi_pbcli_checksum_method_api_base@@Base+0x1812e6>
│ │  	movs	r6, #201	@ 0xc9
│ │  	b.n	2ede2e <uniffi_pbcli_checksum_method_api_base@@Base+0x1815aa>
│ │  	ldr	r0, [pc, #192]	@ (2ed8f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x18106c>)
│ │  	ldmia.w	sp!, {r0, r2, r5, r7, r8, sl, fp, ip, sp, pc}
│ │ -	and.w	r6, r0, r3, asr #27
│ │ +	and.w	r7, r0, sl, lsl #24
│ │  	vmlal.u16	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2edb82 <uniffi_pbcli_checksum_method_api_base@@Base+0x1812fe>
│ │  	asrs	r0, r4, #32
│ │  	b.n	2ed384 <uniffi_pbcli_checksum_method_api_base@@Base+0x180b00>
│ │  	lsls	r0, r3, #2
│ │  	b.n	2edf8a <uniffi_pbcli_checksum_method_api_base@@Base+0x181706>
│ │ @@ -715339,15 +715339,15 @@
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	asrs	r0, r0, #32
│ │  	asrs	r0, r4, #15
│ │  	asrs	r4, r3, #1
│ │  	asrs	r0, r0, #22
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r5, r7, r9, sl, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r3, r6, r7, r9, sl, sp, lr}
│ │  	vaddl.u16	q8, d11, d0
│ │  	b.n	2edf12 <uniffi_pbcli_checksum_method_api_base@@Base+0x18168e>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (2ed8b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x181034>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2edd98 <uniffi_pbcli_checksum_method_api_base@@Base+0x181514>
│ │  	ands	r0, r0
│ │ @@ -715359,15 +715359,15 @@
│ │  	b.n	2edbce <uniffi_pbcli_checksum_method_api_base@@Base+0x18134a>
│ │  	movs	r0, #89	@ 0x59
│ │  	b.n	2edfd2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18174e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2ed9b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x181130>
│ │  	ldr	r4, [pc, #64]	@ (2ed8d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x181054>)
│ │  	ldmia.w	sp!, {r0, r1, r3, r7, r8, sl, fp, ip, sp, pc}
│ │ -	and.w	r6, r0, pc, lsr #25
│ │ +	and.w	r6, r0, r6, lsl #26
│ │  			@ <UNDEFINED> instruction: 0xffdb4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2eddc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x181540>
│ │  	beq.n	2ed954 <uniffi_pbcli_checksum_method_api_base@@Base+0x1810d0>
│ │  	b.n	2edd48 <uniffi_pbcli_checksum_method_api_base@@Base+0x1814c4>
│ │  	add	r0, pc, #48	@ (adr r0, 2ed8e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x18105c>)
│ │  	b.n	2ed3e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x180b64>
│ │ @@ -716487,57 +716487,57 @@
│ │  	asrs	r4, r4, #2
│ │  	b.n	2edd88 <uniffi_pbcli_checksum_method_api_base@@Base+0x181504>
│ │  	movs	r0, r0
│ │  	b.n	2ee36c <uniffi_pbcli_checksum_method_api_base@@Base+0x181ae8>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2ee370 <uniffi_pbcli_checksum_method_api_base@@Base+0x181aec>
│ │  	str	r5, [sp, #620]	@ 0x26c
│ │ -	add.w	r4, r0, r7, asr #27
│ │ +	add.w	r5, r0, lr, lsl #24
│ │  			@ <UNDEFINED> instruction: 0xffdb9fa5
│ │ -	vsri.64	d22, d27, #39
│ │ -	vsri.64	d22, d15, #37
│ │ -	vsri.16	d22, d23, #5
│ │ +	vmls.i16	q11, <illegal reg q12.5>, d2[2]
│ │ +	vmls.i16	q11, <illegal reg q13.5>, d6[0]
│ │ +	vsri.16	q11, q7, #5
│ │  			@ <UNDEFINED> instruction: 0xffdb9ef5
│ │ -	vmla.f16	q11, <illegal reg q12.5>, d3[2]
│ │ +	vsubl.u16	q11, d9, d10
│ │  	vsli.16	d22, d26, #11
│ │  	vmls.f16	q9, <illegal reg q4.5>, d0[3]
│ │  	movs	r0, r0
│ │ -	asrs	r6, r3, #25
│ │ +	asrs	r5, r0, #26
│ │  			@ <UNDEFINED> instruction: 0xffdb2ad0
│ │  	movs	r0, r0
│ │  	cmp	r2, #248	@ 0xf8
│ │  	movs	r0, r0
│ │ -	str	r3, [r2, #0]
│ │ -			@ <UNDEFINED> instruction: 0xffdb5cbf
│ │ +	str	r2, [r7, #0]
│ │ +	vqdmulh.s16	<illegal reg q10.5>, <illegal reg q13.5>, d6[2]
│ │  	vqshl.u16	<illegal reg q12.5>, <illegal reg q14.5>, #11
│ │ -			@ <UNDEFINED> instruction: 0xffd95f5f
│ │ -			@ <UNDEFINED> instruction: 0xffdb5d33
│ │ +			@ <UNDEFINED> instruction: 0xffd95f86
│ │ +			@ <UNDEFINED> instruction: 0xffdb5d5a
│ │  	vqshl.u64	<illegal reg q12.5>, <illegal reg q8.5>, #27
│ │  	vmull.p<illegal width 16>	<illegal reg q8.5>, d25, d6
│ │ -	vsri.16	<illegal reg q11.5>, q7, #6
│ │ -	vmull.u16	q15, d11, d17
│ │ -			@ <UNDEFINED> instruction: 0xffda5d17
│ │ +	vraddhn.i32	d23, q13, <illegal reg q2.5>
│ │ +	vqdmulh.s16	q15, <illegal reg q5.5>, d0[1]
│ │ +			@ <UNDEFINED> instruction: 0xffda5d3e
│ │  	vqshl.u64	<illegal reg q12.5>, <illegal reg q2.5>, #27
│ │ -			@ <UNDEFINED> instruction: 0xffd95db7
│ │ +			@ <UNDEFINED> instruction: 0xffd95dde
│ │  	vqrshrun.s32	d25, <illegal reg q10.5>, #5
│ │ -			@ <UNDEFINED> instruction: 0xffd95cdb
│ │ +			@ <UNDEFINED> instruction: 0xffd95d02
│ │  	vqshl.u64	d25, d9, #27
│ │ -	vrsra.u64	d22, d15, #39
│ │ -	vrsra.u64	q11, <illegal reg q11.5>, #37
│ │ +			@ <UNDEFINED> instruction: 0xffd963c6
│ │ +	vsri.16	d22, d14, #5
│ │  			@ <UNDEFINED> instruction: 0xffdb9eb5
│ │ -	vsra.u64	d22, d11, #39
│ │ +	vmla.f16	q11, <illegal reg q12.5>, d2[0]
│ │  			@ <UNDEFINED> instruction: 0xffdb9c59
│ │ -	vmlal.u16	q11, d25, d3[1]
│ │ +	vrshr.u64	q11, q9, #39
│ │  			@ <UNDEFINED> instruction: 0xffdb9d89
│ │ -	vrshr.u16	d22, d27, #7
│ │ +	vmlal.u16	q11, d9, d2[2]
│ │  			@ <UNDEFINED> instruction: 0xffdb9cf9
│ │ -	vmla.i16	q11, <illegal reg q12.5>, d7[1]
│ │ +	vshr.u64	q11, q11, #39
│ │  			@ <UNDEFINED> instruction: 0xffdb9b8d
│ │  			@ <UNDEFINED> instruction: 0xffd9de5f
│ │ -	vmull.u16	<illegal reg q10.5>, d25, d19
│ │ +	vqdmulh.s16	<illegal reg q10.5>, <illegal reg q12.5>, d2[1]
│ │  			@ <UNDEFINED> instruction: 0xffdb4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2ee818 <uniffi_pbcli_checksum_method_api_base@@Base+0x181f94>
│ │  	beq.n	2ee320 <uniffi_pbcli_checksum_method_api_base@@Base+0x181a9c>
│ │  	b.n	2ee79c <uniffi_pbcli_checksum_method_api_base@@Base+0x181f18>
│ │  	stmia	r0!, {r3}
│ │  	b.n	2ede3c <uniffi_pbcli_checksum_method_api_base@@Base+0x1815b8>
│ │ @@ -716747,24 +716747,24 @@
│ │  	b.n	2ee5f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x181d70>
│ │  	movs	r0, #2
│ │  	b.n	2ee5f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x181d74>
│ │  			@ <UNDEFINED> instruction: 0xffc9eaff
│ │  	ands	r0, r0
│ │  	b.n	2eec22 <uniffi_pbcli_checksum_method_api_base@@Base+0x18239e>
│ │  			@ <UNDEFINED> instruction: 0xffcdeaff
│ │ -	ldrh	r7, [r0, r2]
│ │ -	vmlsl.u16	<illegal reg q11.5>, d11, d14
│ │ -			@ <UNDEFINED> instruction: 0xffda5a5f
│ │ -	vmul.f16	<illegal reg q11.5>, <illegal reg q13.5>, d6[2]
│ │ -	vshll.u16	<illegal reg q10.5>, d15, #10
│ │ -			@ <UNDEFINED> instruction: 0xffdb79a6
│ │ -			@ <UNDEFINED> instruction: 0xffda5af3
│ │ -			@ <UNDEFINED> instruction: 0xffdb7a7a
│ │ -			@ <UNDEFINED> instruction: 0xffda5ab7
│ │ -	vshll.u16	<illegal reg q11.5>, d30, #11
│ │ +	ldrh	r6, [r5, r2]
│ │ +	vshll.u16	<illegal reg q11.5>, d21, #11
│ │ +	vmlsl.u16	<illegal reg q10.5>, d26, d6
│ │ +	vmlsl.u16	<illegal reg q11.5>, d11, d13
│ │ +	vmull.u16	<illegal reg q10.5>, d10, d6[0]
│ │ +	vmul.f16	<illegal reg q11.5>, <illegal reg q13.5>, d5[1]
│ │ +			@ <UNDEFINED> instruction: 0xffda5b1a
│ │ +	vmlsl.u16	<illegal reg q11.5>, d27, d17
│ │ +			@ <UNDEFINED> instruction: 0xffda5ade
│ │ +	vmull.u16	<illegal reg q11.5>, d11, d5[2]
│ │  			@ <UNDEFINED> instruction: 0xffda4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2eea30 <uniffi_pbcli_checksum_method_api_base@@Base+0x1821ac>
│ │  	beq.n	2ee540 <uniffi_pbcli_checksum_method_api_base@@Base+0x181cbc>
│ │  	b.n	2ee9b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x182130>
│ │  	movs	r0, r0
│ │  	b.n	2eebc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18233e>
│ │ @@ -717238,32 +717238,32 @@
│ │  	asrs	r4, r1, #1
│ │  	b.n	2ee454 <uniffi_pbcli_checksum_method_api_base@@Base+0x181bd0>
│ │  	movs	r0, r0
│ │  	b.n	2eea38 <uniffi_pbcli_checksum_method_api_base@@Base+0x1821b4>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2eea3c <uniffi_pbcli_checksum_method_api_base@@Base+0x1821b8>
│ │  	str	r3, [sp, #928]	@ 0x3a0
│ │ -	add.w	r8, r0, fp, asr #22
│ │ +	add.w	r8, r0, r2, lsr #23
│ │  	vmls.i16	q8, <illegal reg q13.5>, d2[0]
│ │ -	vmlal.u16	<illegal reg q10.5>, d26, d3
│ │ +	vmlal.u16	<illegal reg q10.5>, d26, d26
│ │  	vsri.64	d16, d10, #37
│ │ -	vqshl.u16	<illegal reg q10.5>, <illegal reg q15.5>, #10
│ │ +	vabdl.u16	<illegal reg q10.5>, d26, d22
│ │  	vrsra.u64	d16, d6, #37
│ │ -	vqshrn.u32	d21, <illegal reg q3.5>, #6
│ │ +	vqshrn.u32	d21, q15, #6
│ │  	vabal.u16	q8, d11, d30
│ │ -	vabdl.u16	<illegal reg q10.5>, d10, d19
│ │ +			@ <UNDEFINED> instruction: 0xffda574a
│ │  	vrsra.u16	d16, d26, #5
│ │ -	vqshlu.s64	d21, d11, #26
│ │ +	vmlsl.u16	<illegal reg q10.5>, d26, d2[0]
│ │  	vrshr.u64	d16, d18, #37
│ │ -	vabdl.u16	<illegal reg q10.5>, d26, d27
│ │ +	vqshl.u64	<illegal reg q10.5>, q1, #26
│ │  			@ <UNDEFINED> instruction: 0xffdb03c2
│ │ -			@ <UNDEFINED> instruction: 0xffda58db
│ │ +			@ <UNDEFINED> instruction: 0xffda5902
│ │  	vsri.64	q8, q9, #37
│ │  	vmul.i16	q13, q5, d7[0]
│ │ -	vsli.64	<illegal reg q10.5>, <illegal reg q3.5>, #25
│ │ +	vsli.64	<illegal reg q10.5>, q15, #25
│ │  	vaddl.u16	<illegal reg q9.5>, d11, d8
│ │  	b.n	2ee48e <uniffi_pbcli_checksum_method_api_base@@Base+0x181c0a>
│ │  	movs	r0, r0
│ │  	b.n	2ef018 <uniffi_pbcli_checksum_method_api_base@@Base+0x182794>
│ │  	movs	r0, r0
│ │  	lsrs	r0, r0, #8
│ │  	movs	r0, r0
│ │ @@ -717553,28 +717553,28 @@
│ │  	asrs	r4, r7, #32
│ │  	b.n	2ee730 <uniffi_pbcli_checksum_method_api_base@@Base+0x181eac>
│ │  	movs	r0, r0
│ │  	b.n	2eed14 <uniffi_pbcli_checksum_method_api_base@@Base+0x182490>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2eed18 <uniffi_pbcli_checksum_method_api_base@@Base+0x182494>
│ │  	str	r3, [sp, #196]	@ 0xc4
│ │ -	add.w	r4, r0, fp, lsl #22
│ │ -	vqshlu.s16	d18, d23, #11
│ │ -	vmls.i16	<illegal reg q10.5>, <illegal reg q5.5>, d3[2]
│ │ -	vrsubhn.i32	d18, <illegal reg q5.5>, <illegal reg q7.5>
│ │ -	vsri.16	d21, d23, #5
│ │ -	vmls.f16	q9, <illegal reg q13.5>, d3[2]
│ │ -			@ <UNDEFINED> instruction: 0xffdb534b
│ │ -	vsri.64	q9, <illegal reg q11.5>, #37
│ │ -	vsubw.u16	<illegal reg q10.5>, <illegal reg q5.5>, d23
│ │ -	vsri.64	q9, <illegal reg q1.5>, #37
│ │ -	vsri.64	d21, d27, #37
│ │ -	vmlsl.u16	q9, d11, d7[2]
│ │ +	add.w	r4, r0, r2, ror #22
│ │ +	vqshlu.s16	q9, q7, #11
│ │ +	vraddhn.i32	d21, <illegal reg q13.5>, q5
│ │ +	vqshlu.s16	d18, d22, #11
│ │ +	vsri.16	<illegal reg q10.5>, q7, #5
│ │ +	vrsubhn.i32	d18, <illegal reg q5.5>, q5
│ │ +	vrsra.u16	<illegal reg q10.5>, q9, #5
│ │ +	vsli.16	d18, d14, #11
│ │ +			@ <UNDEFINED> instruction: 0xffdb534e
│ │ +	vsri.64	q9, q13, #37
│ │ +	vmls.i16	<illegal reg q10.5>, <illegal reg q13.5>, d2[2]
│ │ +	vrsubhn.i32	d18, <illegal reg q13.5>, q7
│ │  	vqdmulh.s16	<illegal reg q12.5>, <illegal reg q5.5>, d2[0]
│ │ -	vrshr.u64	<illegal reg q10.5>, <illegal reg q13.5>, #40
│ │ +	vsubw.u16	<illegal reg q10.5>, q4, d18
│ │  			@ <UNDEFINED> instruction: 0xffdb4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2ef158 <uniffi_pbcli_checksum_method_api_base@@Base+0x1828d4>
│ │  	beq.n	2eec50 <uniffi_pbcli_checksum_method_api_base@@Base+0x1823cc>
│ │  	b.n	2ef0dc <uniffi_pbcli_checksum_method_api_base@@Base+0x182858>
│ │  	movs	r0, r0
│ │  	b.n	2ef2ea <uniffi_pbcli_checksum_method_api_base@@Base+0x182a66>
│ │ @@ -717975,34 +717975,34 @@
│ │  	asrs	r4, r2, #1
│ │  	b.n	2eeaec <uniffi_pbcli_checksum_method_api_base@@Base+0x182268>
│ │  	movs	r0, r0
│ │  	b.n	2ef0d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x18284c>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2ef0d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x182850>
│ │  	str	r2, [sp, #264]	@ 0x108
│ │ -	add.w	r2, r0, fp, ror #21
│ │ -			@ <UNDEFINED> instruction: 0xffdb9bac
│ │ -	vsra.u64	d21, d11, #38
│ │ -	vmull.u16	<illegal reg q12.5>, d27, d4[1]
│ │ -	vmla.f16	<illegal reg q10.5>, q5, d7[3]
│ │ -	vmlsl.u16	<illegal reg q12.5>, d27, d16
│ │ -	vshr.u16	<illegal reg q10.5>, <illegal reg q15.5>, #6
│ │ -			@ <UNDEFINED> instruction: 0xffdb99b0
│ │ -	vaddl.u16	<illegal reg q10.5>, d26, d27
│ │ -			@ <UNDEFINED> instruction: 0xffdb99dc
│ │ -	vaddw.u16	<illegal reg q10.5>, q5, d15
│ │ -	vmull.u16	<illegal reg q12.5>, d11, d0[0]
│ │ -			@ <UNDEFINED> instruction: 0xffda4f87
│ │ -			@ <UNDEFINED> instruction: 0xffdb98b8
│ │ -	vqrdmlsh.s16	q10, q5, d3[3]
│ │ -			@ <UNDEFINED> instruction: 0xffdb989c
│ │ -	vrshr.u16	<illegal reg q10.5>, <illegal reg q1.5>, #6
│ │ -			@ <UNDEFINED> instruction: 0xffdb9b84
│ │ +	add.w	r2, r0, r2, asr #22
│ │ +			@ <UNDEFINED> instruction: 0xffdb9bd3
│ │ +	vmla.f16	<illegal reg q10.5>, q13, d2[0]
│ │ +			@ <UNDEFINED> instruction: 0xffdb9af3
│ │ +	vsra.u64	d21, d6, #38
│ │ +	vmull.u16	<illegal reg q12.5>, d27, d7[0]
│ │ +	vaddl.u16	<illegal reg q10.5>, d26, d22
│ │ +			@ <UNDEFINED> instruction: 0xffdb99d7
│ │ +	vshr.u64	<illegal reg q10.5>, q1, #38
│ │ +	vmlsl.u16	<illegal reg q12.5>, d11, d3
│ │ +	vsra.u16	d21, d22, #6
│ │ +	vmull.u16	<illegal reg q12.5>, d11, d7[2]
│ │ +			@ <UNDEFINED> instruction: 0xffda4fae
│ │ +			@ <UNDEFINED> instruction: 0xffdb98df
│ │ +			@ <UNDEFINED> instruction: 0xffda4f92
│ │ +	vmul.i16	<illegal reg q12.5>, <illegal reg q13.5>, d3[0]
│ │ +	vrshr.u16	<illegal reg q10.5>, q13, #6
│ │ +			@ <UNDEFINED> instruction: 0xffdb9bab
│ │  	vaddw.u16	q13, q13, d31
│ │ -			@ <UNDEFINED> instruction: 0xffd94f3f
│ │ +	vqrdmlsh.s16	q10, <illegal reg q4.5>, d6[2]
│ │  			@ <UNDEFINED> instruction: 0xffdbfe5b
│ │  			@ <UNDEFINED> instruction: 0xeaffff08
│ │  			@ <UNDEFINED> instruction: 0xeaff4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2ef534 <uniffi_pbcli_checksum_method_api_base@@Base+0x182cb0>
│ │  	beq.n	2ef03c <uniffi_pbcli_checksum_method_api_base@@Base+0x1827b8>
│ │  	b.n	2ef4b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x182c34>
│ │ @@ -718496,21 +718496,21 @@
│ │  	b.n	2eef4a <uniffi_pbcli_checksum_method_api_base@@Base+0x1826c6>
│ │  			@ <UNDEFINED> instruction: 0xffc3eaff
│ │  	ands	r0, r0
│ │  	b.n	2efb82 <uniffi_pbcli_checksum_method_api_base@@Base+0x1832fe>
│ │  	ands	r0, r0
│ │  	b.n	2eef56 <uniffi_pbcli_checksum_method_api_base@@Base+0x1826d2>
│ │  			@ <UNDEFINED> instruction: 0xffefeaff
│ │ -	ldr	r3, [pc, #940]	@ (2ef7f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x182f74>)
│ │ +	ldr	r4, [pc, #72]	@ (2ef494 <uniffi_pbcli_checksum_method_api_base@@Base+0x182c10>)
│ │  	vmull.p<illegal width 16>	q14, d11, d15
│ │ -	vqdmulh.s16	q10, <illegal reg q12.5>, d3[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd94d12
│ │  			@ <UNDEFINED> instruction: 0xffdbcf0f
│ │  	vqshlu.s64	q14, <illegal reg q11.5>, #25
│ │ -			@ <UNDEFINED> instruction: 0xffd84c93
│ │ -			@ <UNDEFINED> instruction: 0xffdb4c5f
│ │ +			@ <UNDEFINED> instruction: 0xffd84cba
│ │ +	vmull.u16	q10, d27, d6
│ │  	vmull.p<illegal width 16>	q14, d27, d3
│ │  	vaddl.u16	q8, d9, d1
│ │  	b.n	2efb0e <uniffi_pbcli_checksum_method_api_base@@Base+0x18328a>
│ │  	movs	r1, r1
│ │  	rev	r0, r0
│ │  	lsls	r2, r5, #4
│ │  	b.n	2efb56 <uniffi_pbcli_checksum_method_api_base@@Base+0x1832d2>
│ │ @@ -718727,20 +718727,20 @@
│ │  	b.n	2ef98e <uniffi_pbcli_checksum_method_api_base@@Base+0x18310a>
│ │  	beq.n	2ef670 <uniffi_pbcli_checksum_method_api_base@@Base+0x182dec>
│ │  	b.n	2efae8 <uniffi_pbcli_checksum_method_api_base@@Base+0x183264>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r3, r4, r6, lr}
│ │  	b.n	2ef164 <uniffi_pbcli_checksum_method_api_base@@Base+0x1828e0>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │ -	ldrsh	r2, [r3, r6]
│ │ -	vmul.i16	q10, <illegal reg q13.5>, d7[0]
│ │ -	vmlsl.u16	<illegal reg q8.5>, d27, d7
│ │ -			@ <UNDEFINED> instruction: 0xffdb5f7e
│ │ -			@ <UNDEFINED> instruction: 0xffdb48ff
│ │ -			@ <UNDEFINED> instruction: 0xffdb1abf
│ │ +	ldrsh	r1, [r0, r7]
│ │ +	vmul.i16	q10, <illegal reg q13.5>, d6[3]
│ │ +	vmlsl.u16	<illegal reg q8.5>, d27, d30
│ │ +			@ <UNDEFINED> instruction: 0xffdb5fa5
│ │ +			@ <UNDEFINED> instruction: 0xffdb4926
│ │ +	vmull.u16	<illegal reg q8.5>, d27, d6[2]
│ │  			@ <UNDEFINED> instruction: 0xffdb4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2efb98 <uniffi_pbcli_checksum_method_api_base@@Base+0x183314>
│ │  	beq.n	2ef760 <uniffi_pbcli_checksum_method_api_base@@Base+0x182edc>
│ │  	b.n	2efb1c <uniffi_pbcli_checksum_method_api_base@@Base+0x183298>
│ │  	lsls	r0, r2, #1
│ │  	movt	r0, #1304	@ 0x518
│ │ @@ -719533,43 +719533,43 @@
│ │  	mrc2	10, 2, lr, cr5, cr15, {7}	@ <UNPREDICTABLE>
│ │  	str	r0, [r0, #0]
│ │  	b.n	2f00d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x183852>
│ │  	mrc2	10, 2, lr, cr3, cr15, {7}	@ <UNPREDICTABLE>
│ │  	str	r0, [r0, #0]
│ │  	b.n	2f055e <uniffi_pbcli_checksum_method_api_base@@Base+0x183cda>
│ │  	mrc2	10, 2, lr, cr1, cr15, {7}	@ <UNPREDICTABLE>
│ │ -	ldr	r0, [pc, #156]	@ (2efe40 <uniffi_pbcli_checksum_method_api_base@@Base+0x1835bc>)
│ │ +	ldr	r0, [pc, #312]	@ (2efedc <uniffi_pbcli_checksum_method_api_base@@Base+0x183658>)
│ │  	vsli.64	d31, d17, #27
│ │ -			@ <UNDEFINED> instruction: 0xffd85cfe
│ │ -			@ <UNDEFINED> instruction: 0xffdb7b64
│ │ -	vsri.16	d29, d9, #6
│ │ -			@ <UNDEFINED> instruction: 0xffdad369
│ │ +			@ <UNDEFINED> instruction: 0xffd85d25
│ │ +			@ <UNDEFINED> instruction: 0xffdb7b8b
│ │ +	vmls.i16	<illegal reg q14.5>, q5, d0[0]
│ │ +	vrsra.u64	d29, d0, #38
│ │  	vmla.f16	q9, q5, d2[3]
│ │  	vshr.u64	d27, d8, #39
│ │  	vmlsl.u16	q14, d9, d2[0]
│ │  			@ <UNDEFINED> instruction: 0xffd9dbbf
│ │  	vmull.u16	q13, d24, d21
│ │  	vsubw.u16	<illegal reg q15.5>, <illegal reg q12.5>, d25
│ │  	vmla.f16	<illegal reg q15.5>, q4, d0[2]
│ │  	vqshl.u64	<illegal reg q9.5>, q0, #25
│ │  	vraddhn.i32	d31, q5, <illegal reg q14.5>
│ │  	vmls.f16	q11, q12, d1[3]
│ │ -	vqshrun.s32	d21, <illegal reg q12.5>, #7
│ │ +	vmul.i16	<illegal reg q10.5>, <illegal reg q4.5>, d0[2]
│ │  			@ <UNDEFINED> instruction: 0xffdbaf3f
│ │  			@ <UNDEFINED> instruction: 0xffd90981
│ │  	vsra.u64	d31, d5, #39
│ │  			@ <UNDEFINED> instruction: 0xffd8090d
│ │  	vqrdmulh.s16	<illegal reg q8.5>, <illegal reg q4.5>, d2[3]
│ │  			@ <UNDEFINED> instruction: 0xffda4ba9
│ │  	vmul.i16	q8, q5, d5[2]
│ │ -	vqshl.u16	q15, <illegal reg q2.5>, #9
│ │ +	vqshl.u16	q15, q14, #9
│ │  			@ <UNDEFINED> instruction: 0xffda1eb0
│ │ -	vqshlu.s64	d20, d23, #26
│ │ +	vqshlu.s64	q10, q7, #26
│ │  	vmls.i16	<illegal reg q15.5>, <illegal reg q5.5>, d1[0]
│ │ -	vaddw.u16	q10, q12, d3
│ │ +	vaddw.u16	q10, q12, d26
│ │  			@ <UNDEFINED> instruction: 0xffdbef0d
│ │  	vqshrun.s32	d20, q8, #8
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2f033c <uniffi_pbcli_checksum_method_api_base@@Base+0x183ab8>
│ │  	beq.n	2efe84 <uniffi_pbcli_checksum_method_api_base@@Base+0x183600>
│ │  	b.n	2f02c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x183a3c>
│ │  	lsls	r0, r2, #1
│ │ @@ -719725,16 +719725,16 @@
│ │  	ands	r0, r0
│ │  	b.n	2f06be <uniffi_pbcli_checksum_method_api_base@@Base+0x183e3a>
│ │  	movs	r0, r0
│ │  	b.n	2efa90 <uniffi_pbcli_checksum_method_api_base@@Base+0x18320c>
│ │  	movs	r4, r0
│ │  	b.n	2f02c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x183a42>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r5, r7, r8, sl, ip, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffdbcd95
│ │ +	ldmia.w	sp!, {r0, r2, r5, r6, r7, r8, sl, ip, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffdbcdbc
│ │  	vaddl.u16	q9, d10, d0
│ │  	b.n	2efab6 <uniffi_pbcli_checksum_method_api_base@@Base+0x183232>
│ │  	movs	r0, r0
│ │  	b.n	2f063e <uniffi_pbcli_checksum_method_api_base@@Base+0x183dba>
│ │  	movs	r0, #112	@ 0x70
│ │  	asrs	r2, r2, #22
│ │  	movs	r0, r0
│ │ @@ -720097,25 +720097,25 @@
│ │  			@ <UNDEFINED> instruction: 0xeaff6000
│ │  	b.n	2f0a0a <uniffi_pbcli_checksum_method_api_base@@Base+0x184186>
│ │  	movs	r6, r0
│ │  	b.n	2f060e <uniffi_pbcli_checksum_method_api_base@@Base+0x183d8a>
│ │  	str	r0, [r0, #0]
│ │  	b.n	2efdda <uniffi_pbcli_checksum_method_api_base@@Base+0x183556>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r1, r4, r5, r7, r8, sl, fp, ip, sp}
│ │ -	vrsra.u64	d21, d28, #37
│ │ -	vqdmulh.s16	<illegal reg q9.5>, <illegal reg q13.5>, d3[0]
│ │ -	vmlal.u16	<illegal reg q10.5>, d27, d4[1]
│ │ -	vmull.u16	<illegal reg q9.5>, d27, d23
│ │ -	vrshr.u64	d21, d16, #37
│ │ -			@ <UNDEFINED> instruction: 0xffdb3c7b
│ │ -	vsubl.u16	<illegal reg q10.5>, d27, d4
│ │ -			@ <UNDEFINED> instruction: 0xffdb3c53
│ │ -			@ <UNDEFINED> instruction: 0xffdb3cfb
│ │ -	vsubw.u16	<illegal reg q10.5>, <illegal reg q5.5>, d4
│ │ +	ldmia.w	sp!, {r1, r3, r4, r6, r7, r8, sl, fp, ip, sp}
│ │ +			@ <UNDEFINED> instruction: 0xffdb53e3
│ │ +	vqdmulh.s16	<illegal reg q9.5>, <illegal reg q13.5>, d2[3]
│ │ +	vrshr.u64	<illegal reg q10.5>, <illegal reg q9.5>, #37
│ │ +	vqdmulh.s16	<illegal reg q9.5>, <illegal reg q13.5>, d6[1]
│ │ +	vrshr.u64	<illegal reg q10.5>, <illegal reg q3.5>, #37
│ │ +	vmull.u16	<illegal reg q9.5>, d27, d18
│ │ +	vsubl.u16	<illegal reg q10.5>, d27, d27
│ │ +			@ <UNDEFINED> instruction: 0xffdb3c7a
│ │ +			@ <UNDEFINED> instruction: 0xffdb3d22
│ │ +	vsubw.u16	<illegal reg q10.5>, <illegal reg q5.5>, d27
│ │  	vshr.u16	d17, d4, #5
│ │  	b.n	2efe26 <uniffi_pbcli_checksum_method_api_base@@Base+0x1835a2>
│ │  	movs	r0, r0
│ │  	b.n	2f09ac <uniffi_pbcli_checksum_method_api_base@@Base+0x184128>
│ │  	movs	r5, r0
│ │  	subs	r0, r0, r0
│ │  	lsls	r0, r1, #1
│ │ @@ -720151,15 +720151,15 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	2f0a96 <uniffi_pbcli_checksum_method_api_base@@Base+0x184212>
│ │  	bl	74be56 <uniffi_pbcli_checksum_method_api_base@@Base+0x5df5d2>
│ │  	asrs	r0, r1, #1
│ │  	b.n	2efe5e <uniffi_pbcli_checksum_method_api_base@@Base+0x1835da>
│ │  	bl	74be5e <uniffi_pbcli_checksum_method_api_base@@Base+0x5df5da>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r5, r7, r8, r9, fp, ip, sp}
│ │ +	ldmia.w	sp!, {r1, r2, r4, r6, r7, r8, r9, fp, ip, sp}
│ │  	vmlal.u16	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2f06b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x183e2e>
│ │  	beq.n	2f0394 <uniffi_pbcli_checksum_method_api_base@@Base+0x183b10>
│ │  	b.n	2f0810 <uniffi_pbcli_checksum_method_api_base@@Base+0x183f8c>
│ │  	adds	r0, #2
│ │  	b.n	2f06ba <uniffi_pbcli_checksum_method_api_base@@Base+0x183e36>
│ │ @@ -720775,28 +720775,28 @@
│ │  			@ <UNDEFINED> instruction: 0xebff6000
│ │  	b.n	2f1026 <uniffi_pbcli_checksum_method_api_base@@Base+0x1847a2>
│ │  	movs	r6, r0
│ │  	b.n	2f102a <uniffi_pbcli_checksum_method_api_base@@Base+0x1847a6>
│ │  	asrs	r1, r4, #3
│ │  	b.n	2f102e <uniffi_pbcli_checksum_method_api_base@@Base+0x1847aa>
│ │  			@ <UNDEFINED> instruction: 0xffd3eaff
│ │ -	subs	r3, #27
│ │ -	vmull.u16	<illegal reg q9.5>, d11, d7[3]
│ │ +	subs	r3, #66	@ 0x42
│ │ +			@ <UNDEFINED> instruction: 0xffdb3a96
│ │  			@ <UNDEFINED> instruction: 0xffdbcfd2
│ │  	vrsubhn.i32	d16, q4, q8
│ │  	movs	r0, r0
│ │ -	subs	r2, #179	@ 0xb3
│ │ +	subs	r2, #218	@ 0xda
│ │  	vshr.u16	d29, d6, #5
│ │ -			@ <UNDEFINED> instruction: 0xffd83767
│ │ -	vrsubhn.i32	d19, <illegal reg q13.5>, <illegal reg q5.5>
│ │ -	vqshlu.s64	<illegal reg q9.5>, <illegal reg q13.5>, #27
│ │ -	vmlsl.u16	<illegal reg q9.5>, d27, d7[0]
│ │ +	vabdl.u16	<illegal reg q9.5>, d24, d14
│ │ +	vqshlu.s64	d19, d18, #27
│ │ +	vabdl.u16	<illegal reg q9.5>, d11, d18
│ │ +	vmlsl.u16	<illegal reg q9.5>, d27, d6[3]
│ │  	vmull.u16	q14, d11, d26
│ │ -	vmlsl.u16	<illegal reg q9.5>, d8, d7[1]
│ │ -	vqshlu.s16	d19, d11, #11
│ │ +	vqshlu.s16	<illegal reg q9.5>, q11, #8
│ │ +	vmlsl.u16	<illegal reg q9.5>, d11, d2[0]
│ │  			@ <UNDEFINED> instruction: 0xffdbcb7e
│ │  	vshr.u16	d17, d4, #8
│ │  	b.n	2f044e <uniffi_pbcli_checksum_method_api_base@@Base+0x183bca>
│ │  	movs	r0, r0
│ │  	b.n	2f0fd4 <uniffi_pbcli_checksum_method_api_base@@Base+0x184750>
│ │  	movs	r5, r0
│ │  	subs	r0, r0, r0
│ │ @@ -720867,15 +720867,15 @@
│ │  	b.n	2f0d0a <uniffi_pbcli_checksum_method_api_base@@Base+0x184486>
│ │  	asrs	r5, r0, #32
│ │  	b.n	2f0d0e <uniffi_pbcli_checksum_method_api_base@@Base+0x18448a>
│ │  	movs	r6, #201	@ 0xc9
│ │  	b.n	2f0fd2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18474e>
│ │  	ldr	r0, [pc, #192]	@ (2f0a94 <uniffi_pbcli_checksum_method_api_base@@Base+0x184210>)
│ │  	ldmia.w	sp!, {r2, r3, r4, r5, r8, ip, sp, pc}
│ │ -	and.w	r5, r0, pc, ror #12
│ │ +	and.w	r5, r0, r6, asr #13
│ │  	vqshrun.s32	d20, q8, #5
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2f0f00 <uniffi_pbcli_checksum_method_api_base@@Base+0x18467c>
│ │  	str	r0, [r6, r0]
│ │  	b.n	2f0528 <uniffi_pbcli_checksum_method_api_base@@Base+0x183ca4>
│ │  	ands	r0, r0
│ │  	b.n	2f0d2e <uniffi_pbcli_checksum_method_api_base@@Base+0x1844aa>
│ │ @@ -720895,15 +720895,15 @@
│ │  	b.n	2f0d4e <uniffi_pbcli_checksum_method_api_base@@Base+0x1844ca>
│ │  	asrs	r5, r0, #32
│ │  	b.n	2f0d52 <uniffi_pbcli_checksum_method_api_base@@Base+0x1844ce>
│ │  	movs	r6, #201	@ 0xc9
│ │  	b.n	2f1016 <uniffi_pbcli_checksum_method_api_base@@Base+0x184792>
│ │  	ldr	r0, [pc, #192]	@ (2f0ad8 <uniffi_pbcli_checksum_method_api_base@@Base+0x184254>)
│ │  	ldmia.w	sp!, {r0, r1, r3, r5, r8, ip, sp, pc}
│ │ -	and.w	r4, r0, fp, ror #15
│ │ +	and.w	r5, r0, r2, asr #12
│ │  			@ <UNDEFINED> instruction: 0xffdb4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2f0f44 <uniffi_pbcli_checksum_method_api_base@@Base+0x1846c0>
│ │  	ands	r1, r0
│ │  	b.n	2f0d6e <uniffi_pbcli_checksum_method_api_base@@Base+0x1844ea>
│ │  	asrs	r2, r0, #32
│ │  	b.n	2f1172 <uniffi_pbcli_checksum_method_api_base@@Base+0x1848ee>
│ │ @@ -721396,30 +721396,30 @@
│ │  	movs	r0, #24
│ │  	b.n	2f099c <uniffi_pbcli_checksum_method_api_base@@Base+0x184118>
│ │  	movs	r0, r0
│ │  	b.n	2f0f80 <uniffi_pbcli_checksum_method_api_base@@Base+0x1846fc>
│ │  	movs	r0, #2
│ │  	b.n	2f0f84 <uniffi_pbcli_checksum_method_api_base@@Base+0x184700>
│ │  	vpmin.u16	q15, q12, <illegal reg q15.5>
│ │ -			@ <UNDEFINED> instruction: 0xe99affda
│ │ -	str	r2, [sp, #424]	@ 0x1a8
│ │ +	strd	pc, pc, [r1, #872]	@ 0x368
│ │ +	str	r2, [sp, #580]	@ 0x244
│ │  	vqshlu.s64	d18, d6, #26
│ │ -	vqrdmlsh.s16	q12, q5, d6[1]
│ │ +			@ <UNDEFINED> instruction: 0xffda8f75
│ │  	vrsra.u16	q9, q13, #6
│ │ -	vmla.f16	<illegal reg q12.5>, q13, d6[2]
│ │ +	vsubl.u16	<illegal reg q12.5>, d10, d13
│ │  	vqshlu.s16	d18, d2, #10
│ │  	vqshlu.s16	<illegal reg q12.5>, q8, #10
│ │  	movs	r3, r3
│ │ -	str	r0, [sp, #424]	@ 0x1a8
│ │ +	str	r0, [sp, #580]	@ 0x244
│ │  	vsri.64	d18, d6, #38
│ │  	vqrdmulh.s16	<illegal reg q14.5>, q13, d7[0]
│ │ -	vqrdmlsh.s16	q12, <illegal reg q12.5>, d6[0]
│ │ +	vqrdmlsh.s16	q12, <illegal reg q12.5>, d5[3]
│ │  	vrsra.u64	q9, q9, #38
│ │  	vsri.16	q9, <illegal reg q2.5>, #6
│ │ -	vmul.f16	<illegal reg q11.5>, <illegal reg q4.5>, d1[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd97990
│ │  			@ <UNDEFINED> instruction: 0xffda48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2f13c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x184b44>
│ │  	beq.n	2f0f20 <uniffi_pbcli_checksum_method_api_base@@Base+0x18469c>
│ │  	b.n	2f134c <uniffi_pbcli_checksum_method_api_base@@Base+0x184ac8>
│ │  	ands	r3, r0
│ │  	b.n	2f11f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x184972>
│ │ @@ -721573,15 +721573,15 @@
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r1, r2}
│ │  	b.n	2f1352 <uniffi_pbcli_checksum_method_api_base@@Base+0x184ace>
│ │  	subs	r1, #31
│ │  	add.w	r0, r1, r0
│ │  	b.n	2f175a <uniffi_pbcli_checksum_method_api_base@@Base+0x184ed6>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r5, r6, r7, r8, sl, fp, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r4, r9, sl, fp, pc}
│ │  	vmlal.u16	q9, d10, d4[3]
│ │  			@ <UNDEFINED> instruction: 0xffd94bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2f1548 <uniffi_pbcli_checksum_method_api_base@@Base+0x184cc4>
│ │  	strh	r1, [r0, #0]
│ │  	b.n	2f1372 <uniffi_pbcli_checksum_method_api_base@@Base+0x184aee>
│ │  	asrs	r0, r0, #32
│ │ @@ -721744,21 +721744,21 @@
│ │  	movs	r4, r0
│ │  	b.n	2f14de <uniffi_pbcli_checksum_method_api_base@@Base+0x184c5a>
│ │  	asrs	r1, r2, #7
│ │  	b.n	2f17a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x184f1e>
│ │  	movs	r0, #2
│ │  	b.n	2f12c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x184a40>
│ │  			@ <UNDEFINED> instruction: 0xffb3eaff
│ │ -	ldrh	r6, [r0, #38]	@ 0x26
│ │ -			@ <UNDEFINED> instruction: 0xffda8c3e
│ │ +	ldrh	r5, [r5, #38]	@ 0x26
│ │ +	vqdmulh.s16	q12, q5, d5[2]
│ │  	vaddw.u16	q9, q5, d10
│ │ -	vmull.u16	q12, d9, d22
│ │ +	vqdmulh.s16	q12, <illegal reg q4.5>, d5[1]
│ │  	vshr.u64	q9, q5, #38
│ │ -			@ <UNDEFINED> instruction: 0xffd98c7e
│ │ -			@ <UNDEFINED> instruction: 0xffda8d3a
│ │ +	vmull.u16	q12, d25, d21
│ │ +	vqrdmulh.s16	q12, q5, d1[2]
│ │  	vsubl.u16	q9, d10, d6
│ │  			@ <UNDEFINED> instruction: 0xffd948f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2f16ec <uniffi_pbcli_checksum_method_api_base@@Base+0x184e68>
│ │  	ands	r0, r0
│ │  	b.n	2f1516 <uniffi_pbcli_checksum_method_api_base@@Base+0x184c92>
│ │  	lsls	r4, r4, #5
│ │ @@ -721921,19 +721921,19 @@
│ │  	b.n	2f1a76 <uniffi_pbcli_checksum_method_api_base@@Base+0x1851f2>
│ │  	str	r7, [sp, #316]	@ 0x13c
│ │  			@ <UNDEFINED> instruction: 0xebff0005
│ │  	b.n	2f167e <uniffi_pbcli_checksum_method_api_base@@Base+0x184dfa>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r1, r2, r5, r6, r9, ip, sp, lr, pc}
│ │  	vmla.i16	q9, q4, d3[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd98ade
│ │ +			@ <UNDEFINED> instruction: 0xffd98b05
│ │  			@ <UNDEFINED> instruction: 0xffda1f5c
│ │ -	vmull.u16	q12, d25, d2[0]
│ │ +	vmull.u16	q12, d25, d1[3]
│ │  	vmla.f16	<illegal reg q15.5>, q5, d3[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd88a96
│ │ +			@ <UNDEFINED> instruction: 0xffd88abd
│ │  	vsra.u16	d31, d23, #6
│ │  			@ <UNDEFINED> instruction: 0xffd84df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2f1884 <uniffi_pbcli_checksum_method_api_base@@Base+0x185000>
│ │  	str	r0, [r0, r0]
│ │  	b.n	2f16ae <uniffi_pbcli_checksum_method_api_base@@Base+0x184e2a>
│ │  	cmp	r6, #84	@ 0x54
│ │ @@ -722058,21 +722058,21 @@
│ │  	b.n	2f17ba <uniffi_pbcli_checksum_method_api_base@@Base+0x184f36>
│ │  	movs	r2, #66	@ 0x42
│ │  	b.n	2f1a7e <uniffi_pbcli_checksum_method_api_base@@Base+0x1851fa>
│ │  	add	r6, sp, #584	@ 0x248
│ │  	add.w	r0, r0, r4
│ │  	b.n	2f17c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x184f42>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r7, r8, fp, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r6, r7, r8, fp, pc}
│ │  	vmla.i16	q14, q5, d0[2]
│ │ -	vmlsl.u16	q12, d8, d2
│ │ -	vmul.f16	q12, q5, d2[2]
│ │ +	vmlsl.u16	q12, d8, d25
│ │ +			@ <UNDEFINED> instruction: 0xffda8989
│ │  	vaddl.u16	q14, d10, d20
│ │ -	vshr.u64	d30, d30, #40
│ │ -			@ <UNDEFINED> instruction: 0xffda89ba
│ │ +	vmla.i16	q15, q12, d5[2]
│ │ +	vmul.f16	q12, q13, d1[2]
│ │  			@ <UNDEFINED> instruction: 0xffda48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2f19c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x185144>
│ │  	beq.n	2f1540 <uniffi_pbcli_checksum_method_api_base@@Base+0x184cbc>
│ │  	b.n	2f194c <uniffi_pbcli_checksum_method_api_base@@Base+0x1850c8>
│ │  	str	r2, [r0, #0]
│ │  	b.n	2f17f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x184f72>
│ │ @@ -723010,15 +723010,15 @@
│ │  	movs	r0, r0
│ │  	b.n	2f1dec <uniffi_pbcli_checksum_method_api_base@@Base+0x185568>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2f1df0 <uniffi_pbcli_checksum_method_api_base@@Base+0x18556c>
│ │  	strh	r3, [r7, #54]	@ 0x36
│ │  			@ <UNDEFINED> instruction: 0xeb00d002
│ │  			@ <UNDEFINED> instruction: 0xffd86ba6
│ │ -	vraddhn.i32	d31, q4, <illegal reg q4.5>
│ │ +	vsri.16	d31, d16, #8
│ │  			@ <UNDEFINED> instruction: 0xffda6b8e
│ │  	vaddl.u16	q9, d8, d0
│ │  	b.n	2f242a <uniffi_pbcli_checksum_method_api_base@@Base+0x185ba6>
│ │  			@ <UNDEFINED> instruction: 0xffffeaff
│ │  	ldr	r0, [pc, #960]	@ (2f20b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x18582c>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2f2210 <uniffi_pbcli_checksum_method_api_base@@Base+0x18598c>
│ │ @@ -723581,15 +723581,15 @@
│ │  	b.n	2f28c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18603e>
│ │  			@ <UNDEFINED> instruction: 0xfff90aff
│ │  	movs	r0, r0
│ │  	b.n	2f29aa <uniffi_pbcli_checksum_method_api_base@@Base+0x186126>
│ │  	beq.n	2f21fc <uniffi_pbcli_checksum_method_api_base@@Base+0x185978>
│ │  	b.n	2f2684 <uniffi_pbcli_checksum_method_api_base@@Base+0x185e00>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r7, r8, r9, fp, sp, pc}
│ │ +	ldmia.w	sp!, {r4, r5, r7, r8, r9, fp, sp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffda48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2f2718 <uniffi_pbcli_checksum_method_api_base@@Base+0x185e94>
│ │  	beq.n	2f2260 <uniffi_pbcli_checksum_method_api_base@@Base+0x1859dc>
│ │  	b.n	2f269c <uniffi_pbcli_checksum_method_api_base@@Base+0x185e18>
│ │  	movs	r0, r0
│ │  	b.n	2f28a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x186024>
│ │ @@ -723672,15 +723672,15 @@
│ │  	b.n	2f1df0 <uniffi_pbcli_checksum_method_api_base@@Base+0x18556c>
│ │  	movs	r0, r0
│ │  	b.n	2f23d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x185b50>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2f23d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x185b54>
│ │  	strh	r1, [r0, #44]	@ 0x2c
│ │  	add.w	r6, r0, r3, lsr #25
│ │ -	vsri.16	q8, <illegal reg q2.5>, #8
│ │ +	vsri.16	q8, q14, #8
│ │  			@ <UNDEFINED> instruction: 0xffdb3fb6
│ │  	vaddl.u16	q8, d9, d0
│ │  	b.n	2f296e <uniffi_pbcli_checksum_method_api_base@@Base+0x1860ea>
│ │  	movs	r0, r2
│ │  	asrs	r0, r2, #22
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │ @@ -724570,22 +724570,22 @@
│ │  	stmia	r3!, {}
│ │  	movs	r4, r0
│ │  	b.n	2f2dd6 <uniffi_pbcli_checksum_method_api_base@@Base+0x186552>
│ │  	beq.n	2f2ac8 <uniffi_pbcli_checksum_method_api_base@@Base+0x186244>
│ │  	b.n	2f2f30 <uniffi_pbcli_checksum_method_api_base@@Base+0x1866ac>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r1, r5, r7, r9, lr, pc}
│ │ -	vraddhn.i32	d26, <illegal reg q12.5>, <illegal reg q2.5>
│ │ -	vqdmulh.s16	q9, q5, d6[2]
│ │ +	vraddhn.i32	d26, <illegal reg q12.5>, q14
│ │ +	vmull.u16	q9, d26, d13
│ │  			@ <UNDEFINED> instruction: 0xffdbbd2c
│ │ -	vsli.64	d19, d24, #24
│ │ -	vmlsl.u16	<illegal reg q13.5>, d26, d6
│ │ +	vsli.64	<illegal reg q9.5>, <illegal reg q7.5>, #24
│ │ +	vmlsl.u16	<illegal reg q13.5>, d26, d29
│ │  	vqrshrn.u32	d29, <illegal reg q11.5>, #6
│ │ -	vqshl.u64	d30, d16, #25
│ │ -			@ <UNDEFINED> instruction: 0xffda4a94
│ │ +	vqshl.u64	q15, <illegal reg q3.5>, #25
│ │ +			@ <UNDEFINED> instruction: 0xffda4abb
│ │  			@ <UNDEFINED> instruction: 0xffda5dff
│ │  	vaddl.u16	q8, d8, d0
│ │  	b.n	2f316a <uniffi_pbcli_checksum_method_api_base@@Base+0x1868e6>
│ │  	movs	r4, r0
│ │  	asrs	r0, r2, #22
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │ @@ -724866,15 +724866,15 @@
│ │  	asrs	r0, r0, #32
│ │  	lsls	r0, r4, #15
│ │  	movs	r1, r0
│ │  	b.n	2f308e <uniffi_pbcli_checksum_method_api_base@@Base+0x18680a>
│ │  	beq.n	2f2d60 <uniffi_pbcli_checksum_method_api_base@@Base+0x1864dc>
│ │  	b.n	2f31e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x186964>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r2, r4, r8, r9, sl, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r4, r5, r8, r9, sl, lr}
│ │  	vqshrun.s32	d20, q8, #6
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2f327c <uniffi_pbcli_checksum_method_api_base@@Base+0x1869f8>
│ │  	beq.n	2f2dc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x186540>
│ │  	b.n	2f3200 <uniffi_pbcli_checksum_method_api_base@@Base+0x18697c>
│ │  	lsls	r0, r2, #1
│ │  	movt	r0, #1293	@ 0x50d
│ │ @@ -724920,15 +724920,15 @@
│ │  	movs	r0, r0
│ │  	b.n	2f3466 <uniffi_pbcli_checksum_method_api_base@@Base+0x186be2>
│ │  	movs	r1, r0
│ │  	asrs	r0, r0, #12
│ │  	beq.n	2f2ddc <uniffi_pbcli_checksum_method_api_base@@Base+0x186558>
│ │  	b.n	2f3264 <uniffi_pbcli_checksum_method_api_base@@Base+0x1869e0>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r2, r5, r7, r9, sl, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r6, r7, r9, sl, lr}
│ │  	vaddl.u16	q8, d10, d8
│ │  	b.n	2f28fa <uniffi_pbcli_checksum_method_api_base@@Base+0x186076>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r4, [pc, #448]	@ (2f2fa0 <uniffi_pbcli_checksum_method_api_base@@Base+0x18671c>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2f3300 <uniffi_pbcli_checksum_method_api_base@@Base+0x186a7c>
│ │  	beq.n	2f2e48 <uniffi_pbcli_checksum_method_api_base@@Base+0x1865c4>
│ │ @@ -725012,15 +725012,15 @@
│ │  	b.n	2f332c <uniffi_pbcli_checksum_method_api_base@@Base+0x186aa8>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {}
│ │  	b.n	2f365e <uniffi_pbcli_checksum_method_api_base@@Base+0x186dda>
│ │  	beq.n	2f2ec0 <uniffi_pbcli_checksum_method_api_base@@Base+0x18663c>
│ │  	b.n	2f3338 <uniffi_pbcli_checksum_method_api_base@@Base+0x186ab4>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r7, r9, sl, sp}
│ │ +	ldmia.w	sp!, {r0, r2, r6, r7, r9, sl, sp}
│ │  	vaddl.u16	q8, d11, d0
│ │  	b.n	2f29ce <uniffi_pbcli_checksum_method_api_base@@Base+0x18614a>
│ │  	movs	r0, r0
│ │  	b.n	2f3552 <uniffi_pbcli_checksum_method_api_base@@Base+0x186cce>
│ │  	movs	r0, r0
│ │  	asrs	r0, r2, #22
│ │  	movs	r0, r0
│ │ @@ -725132,15 +725132,15 @@
│ │  	movs	r0, #0
│ │  	b.n	2f36f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x186e6e>
│ │  	str	r0, [sp, #192]	@ 0xc0
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	2f377a <uniffi_pbcli_checksum_method_api_base@@Base+0x186ef6>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r1, r4, r6, r7, r9, ip, sp}
│ │ -			@ <UNDEFINED> instruction: 0xffd9589c
│ │ +	vmul.i16	<illegal reg q10.5>, <illegal reg q12.5>, d3[0]
│ │  	vmlal.u16	q10, d10, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2f330e <uniffi_pbcli_checksum_method_api_base@@Base+0x186a8a>
│ │  	movs	r0, r0
│ │  	b.n	2f3672 <uniffi_pbcli_checksum_method_api_base@@Base+0x186dee>
│ │  	movs	r0, r1
│ │  	asrs	r0, r2, #22
│ │ @@ -725614,16 +725614,16 @@
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	2f3bce <uniffi_pbcli_checksum_method_api_base@@Base+0x18734a>
│ │  	beq.n	2f3420 <uniffi_pbcli_checksum_method_api_base@@Base+0x186b9c>
│ │  	b.n	2f38a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x187024>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r1, r2, r3, r4, r5, r7, r9, sl, fp, sp}
│ │ -	vshr.u64	q12, q11, #39
│ │ -	vrshr.u64	d21, d16, #38
│ │ +	vsra.u16	d24, d13, #7
│ │ +	vrshr.u64	<illegal reg q10.5>, <illegal reg q3.5>, #38
│ │  			@ <UNDEFINED> instruction: 0xffda4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2f3944 <uniffi_pbcli_checksum_method_api_base@@Base+0x1870c0>
│ │  	strb	r2, [r0, #0]
│ │  	b.n	2f376e <uniffi_pbcli_checksum_method_api_base@@Base+0x186eea>
│ │  	str	r1, [r0, #0]
│ │  	b.n	2f3772 <uniffi_pbcli_checksum_method_api_base@@Base+0x186eee>
│ │ @@ -726044,15 +726044,15 @@
│ │  	b.n	2f3b0a <uniffi_pbcli_checksum_method_api_base@@Base+0x187286>
│ │  	beq.n	2f3804 <uniffi_pbcli_checksum_method_api_base@@Base+0x186f80>
│ │  	b.n	2f3c64 <uniffi_pbcli_checksum_method_api_base@@Base+0x1873e0>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r3, r5, r7, r8, r9, fp, sp, lr}
│ │  	movs	r3, r3
│ │  	ldr	r1, [r6, r7]
│ │ -			@ <UNDEFINED> instruction: 0xffd91d78
│ │ +			@ <UNDEFINED> instruction: 0xffd91d9f
│ │  			@ <UNDEFINED> instruction: 0xffdb6b14
│ │  	movs	r3, r3
│ │  	ldr	r7, [pc, #960]	@ (2f3ba4 <uniffi_pbcli_checksum_method_api_base@@Base+0x187320>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2f3d04 <uniffi_pbcli_checksum_method_api_base@@Base+0x187480>
│ │  	beq.n	2f38d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x187050>
│ │  	b.n	2f3c88 <uniffi_pbcli_checksum_method_api_base@@Base+0x187404>
│ │ @@ -726395,15 +726395,15 @@
│ │  	ldr	r4, [r6, #40]	@ 0x28
│ │  	movs	r3, r3
│ │  	lsls	r0, r1, #16
│ │  	movs	r0, r0
│ │  	lsrs	r2, r1, #7
│ │  			@ <UNDEFINED> instruction: 0xffd99aff
│ │  	vshr.u64	q15, <illegal reg q4.5>, #40
│ │ -	vqshl.u16	d29, d30, #8
│ │ +			@ <UNDEFINED> instruction: 0xffd8d765
│ │  	vshll.u16	<illegal reg q12.5>, d27, #10
│ │  	vshr.u16	d30, d5, #8
│ │  			@ <UNDEFINED> instruction: 0xffd899ff
│ │  			@ <UNDEFINED> instruction: 0xffd8dfd9
│ │  			@ <UNDEFINED> instruction: 0xffd84c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2f4038 <uniffi_pbcli_checksum_method_api_base@@Base+0x1877b4>
│ │ @@ -726903,25 +726903,25 @@
│ │  			@ <UNDEFINED> instruction: 0xffd20aff
│ │  	lsls	r0, r3, #1
│ │  	b.n	2f4484 <uniffi_pbcli_checksum_method_api_base@@Base+0x187c00>
│ │  	asrs	r0, r1, #32
│ │  	b.n	2f42ae <uniffi_pbcli_checksum_method_api_base@@Base+0x187a2a>
│ │  	ldr	r2, [r6, #124]	@ 0x7c
│ │  			@ <UNDEFINED> instruction: 0xeb00ffce
│ │ -			@ <UNDEFINED> instruction: 0xeaffd2ba
│ │ +			@ <UNDEFINED> instruction: 0xeaffd2e1
│ │  			@ <UNDEFINED> instruction: 0xffdaacf6
│ │  			@ <UNDEFINED> instruction: 0xffd96980
│ │  	movs	r3, r3
│ │ -	bcs.n	2f3ea0 <uniffi_pbcli_checksum_method_api_base@@Base+0x18761c>
│ │ +	bcs.n	2f3eee <uniffi_pbcli_checksum_method_api_base@@Base+0x18766a>
│ │  	vqdmulh.s16	q13, q13, d2[1]
│ │ -	vrshr.u16	d29, d30, #7
│ │ +	vmlal.u16	<illegal reg q14.5>, d9, d5[2]
│ │  			@ <UNDEFINED> instruction: 0xffdaac7a
│ │ -	vsra.u64	<illegal reg q14.5>, q7, #39
│ │ +	vsubl.u16	<illegal reg q14.5>, d9, d5
│ │  			@ <UNDEFINED> instruction: 0xffdaac1a
│ │ -	vsubl.u16	<illegal reg q14.5>, d9, d10
│ │ +	vrshr.u16	d29, d17, #7
│ │  	vqdmulh.s16	q13, q5, d6[0]
│ │  	vabdl.u16	q11, d25, d12
│ │  	movs	r3, r3
│ │  	ldr	r0, [pc, #0]	@ (2f3fa8 <uniffi_pbcli_checksum_method_api_base@@Base+0x187724>)
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2f42ee <uniffi_pbcli_checksum_method_api_base@@Base+0x187a6a>
│ │  	beq.n	2f3fe0 <uniffi_pbcli_checksum_method_api_base@@Base+0x18775c>
│ │ @@ -727125,22 +727125,22 @@
│ │  	cmp	r3, #29
│ │  	add.w	r0, r0, r8
│ │  	b.n	2f44b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x187c32>
│ │  	beq.n	2f41a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x187924>
│ │  	b.n	2f4610 <uniffi_pbcli_checksum_method_api_base@@Base+0x187d8c>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r1, r2, r4, r7, r8, fp, sp, lr}
│ │ -	vrsra.u16	d26, d4, #7
│ │ +	vrsra.u16	d26, d27, #7
│ │  	vmul.f16	q11, q5, d2[1]
│ │ -	vmlal.u16	q13, d25, d0[1]
│ │ -	vshr.u16	d29, d18, #6
│ │ +	vmlal.u16	q13, d25, d7[3]
│ │ +	vshr.u16	<illegal reg q14.5>, <illegal reg q4.5>, #6
│ │  	vmul.i16	q11, q13, d2[0]
│ │ -	vmlal.u16	q13, d9, d0[0]
│ │ +	vmlal.u16	q13, d9, d7[2]
│ │  	vmul.i16	q11, q13, d2[3]
│ │ -	vmlal.u16	q13, d9, d0[3]
│ │ +	vsubl.u16	q13, d25, d15
│ │  			@ <UNDEFINED> instruction: 0xffda4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2f46c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x187e40>
│ │  	beq.n	2f425c <uniffi_pbcli_checksum_method_api_base@@Base+0x1879d8>
│ │  	b.n	2f4648 <uniffi_pbcli_checksum_method_api_base@@Base+0x187dc4>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	2f48f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18806e>
│ │ @@ -727841,27 +727841,27 @@
│ │  	vmlal.u16	<illegal reg q14.5>, d24, d1[3]
│ │  	vrsra.u16	<illegal reg q11.5>, <illegal reg q2.5>, #7
│ │  	vmlal.u16	q10, d8, d6[0]
│ │  	vsli.16	d29, d17, #8
│ │  	vsli.64	d23, d13, #25
│ │  	vraddhn.i32	d29, q12, <illegal reg q4.5>
│ │  	vsubl.u16	<illegal reg q14.5>, d25, d29
│ │ -	vqshl.u16	<illegal reg q10.5>, q11, #9
│ │ +	vqshl.u64	d21, d13, #25
│ │  	vrsra.u16	q8, q2, #6
│ │  	movs	r0, r0
│ │  	bcc.n	2f47ae <uniffi_pbcli_checksum_method_api_base@@Base+0x187f2a>
│ │  	vmlal.u16	q8, d25, d4[1]
│ │  	movs	r0, r0
│ │  	bcc.n	2f488e <uniffi_pbcli_checksum_method_api_base@@Base+0x18800a>
│ │  	vrshr.u64	q8, q4, #39
│ │  	movs	r0, r0
│ │  	lsls	r0, r2, #13
│ │  	movs	r0, r0
│ │  	bcc.n	2f4842 <uniffi_pbcli_checksum_method_api_base@@Base+0x187fbe>
│ │ -			@ <UNDEFINED> instruction: 0xffd957e6
│ │ +	vmlal.u16	<illegal reg q10.5>, d9, d13
│ │  	vsra.u64	<illegal reg q14.5>, <illegal reg q10.5>, #38
│ │  	vsra.u64	<illegal reg q14.5>, <illegal reg q0.5>, #39
│ │  			@ <UNDEFINED> instruction: 0xffd9a3e2
│ │  			@ <UNDEFINED> instruction: 0xffd94c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2f4d3c <uniffi_pbcli_checksum_method_api_base@@Base+0x1884b8>
│ │  	movs	r0, #4
│ │ @@ -728494,27 +728494,27 @@
│ │  			@ <UNDEFINED> instruction: 0xebff8020
│ │  	b.n	2f47d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x187f54>
│ │  	movs	r0, r1
│ │  	b.n	2f50e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x188862>
│ │  	beq.n	2f4de0 <uniffi_pbcli_checksum_method_api_base@@Base+0x18855c>
│ │  	b.n	2f5240 <uniffi_pbcli_checksum_method_api_base@@Base+0x1889bc>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r3, r4, r8, fp, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r6, r8, fp, sp, pc}
│ │  	vqshrn.u32	d24, q2, #6
│ │  			@ <UNDEFINED> instruction: 0xffd86ddf
│ │  			@ <UNDEFINED> instruction: 0xffd85a74
│ │  	movs	r3, r3
│ │  	lsrs	r0, r7, #14
│ │  	movs	r0, r0
│ │  	lsrs	r4, r2, #15
│ │  	movs	r0, r0
│ │  	strh	r0, [r0, #60]	@ 0x3c
│ │  	vqdmulh.s16	q11, q4, d3[1]
│ │ -	vsli.64	q9, <illegal reg q4.5>, #24
│ │ -	vmlsl.u16	<illegal reg q9.5>, d10, d1
│ │ +	vrsubhn.i32	d18, q4, q0
│ │ +	vmlsl.u16	<illegal reg q9.5>, d10, d24
│ │  	vmlal.u16	q10, d10, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2f511e <uniffi_pbcli_checksum_method_api_base@@Base+0x18889a>
│ │  	asrs	r2, r1, #32
│ │  	b.n	2f5522 <uniffi_pbcli_checksum_method_api_base@@Base+0x188c9e>
│ │  	ldr	r1, [r7, #120]	@ 0x78
│ │  	add.w	r0, r0, r0
│ │ @@ -728578,15 +728578,15 @@
│ │  	ands	r0, r0
│ │  	b.n	2f55b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x188d32>
│ │  	ldrh	r7, [r7, #2]
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	2f51be <uniffi_pbcli_checksum_method_api_base@@Base+0x18893a>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r3, r4, r5, r6, r9, sl, pc}
│ │ -	vrshr.u64	q14, q5, #40
│ │ +	vsubw.u16	q14, q4, d1
│ │  			@ <UNDEFINED> instruction: 0xffda4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2f53ac <uniffi_pbcli_checksum_method_api_base@@Base+0x188b28>
│ │  	movs	r0, r0
│ │  	b.n	2f5536 <uniffi_pbcli_checksum_method_api_base@@Base+0x188cb2>
│ │  	movs	r4, r1
│ │  	asrs	r0, r2, #22
│ │ @@ -728870,15 +728870,15 @@
│ │  	strh	r7, [r2, #62]	@ 0x3e
│ │  			@ <UNDEFINED> instruction: 0xebff0009
│ │  	b.n	2f545e <uniffi_pbcli_checksum_method_api_base@@Base+0x188bda>
│ │  	beq.n	2f5158 <uniffi_pbcli_checksum_method_api_base@@Base+0x1888d4>
│ │  	b.n	2f55b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x188d34>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r3, r4, r6, r7, r8, r9, pc}
│ │ -	vrsra.u16	d18, d16, #8
│ │ +	vrsra.u16	q9, <illegal reg q3.5>, #8
│ │  	vaddl.u16	q8, d10, d0
│ │  	b.n	2f57d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x188f4e>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (2f51f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x188974>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2f5658 <uniffi_pbcli_checksum_method_api_base@@Base+0x188dd4>
│ │  	ands	r0, r0
│ │ @@ -729859,15 +729859,15 @@
│ │  	movs	r0, r0
│ │  	b.n	2f60c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18983e>
│ │  	ands	r1, r0
│ │  	stmia	r3!, {}
│ │  			@ <UNDEFINED> instruction: 0xffdfeaff
│ │  	lsrs	r3, r4, #4
│ │  	vqshrn.u32	d29, q2, #7
│ │ -			@ <UNDEFINED> instruction: 0xffd89eb9
│ │ +	vqrdmlah.s16	<illegal reg q12.5>, q12, d0[2]
│ │  			@ <UNDEFINED> instruction: 0xffda08bf
│ │  			@ <UNDEFINED> instruction: 0xffd9d8b0
│ │  	vaddl.u16	q8, d8, d0
│ │  	b.n	2f60e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18985e>
│ │  	movs	r4, r1
│ │  	asrs	r0, r2, #22
│ │  	movs	r0, r0
│ │ @@ -730397,18 +730397,18 @@
│ │  	b.n	2f6612 <uniffi_pbcli_checksum_method_api_base@@Base+0x189d8e>
│ │  	ands	r0, r0
│ │  	b.n	2f6616 <uniffi_pbcli_checksum_method_api_base@@Base+0x189d92>
│ │  	str	r0, [r0, r0]
│ │  	b.n	2f661a <uniffi_pbcli_checksum_method_api_base@@Base+0x189d96>
│ │  			@ <UNDEFINED> instruction: 0xffcaeaff
│ │  	lsls	r7, r7, #15
│ │ -	vqrshrun.s32	d28, q15, #7
│ │ -			@ <UNDEFINED> instruction: 0xffda57e8
│ │ +	vmlal.u16	q14, d25, d21
│ │ +	vmlal.u16	<illegal reg q10.5>, d10, d15
│ │  			@ <UNDEFINED> instruction: 0xffda8ed6
│ │ -	vmlsl.u16	q9, d24, d0[1]
│ │ +	vmlsl.u16	q9, d24, d7[3]
│ │  	vqshlu.s16	<illegal reg q11.5>, q10, #10
│ │  	movs	r6, r3
│ │  	lsls	r3, r2, #18
│ │  			@ <UNDEFINED> instruction: 0xffd94df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2f641c <uniffi_pbcli_checksum_method_api_base@@Base+0x189b98>
│ │  	beq.n	2f5f14 <uniffi_pbcli_checksum_method_api_base@@Base+0x189690>
│ │ @@ -730614,17 +730614,17 @@
│ │  	strh	r0, [r6, #28]
│ │  			@ <UNDEFINED> instruction: 0xebff1102
│ │  	b.n	2f66c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x189e42>
│ │  	asrs	r4, r1, #32
│ │  	b.n	2f674a <uniffi_pbcli_checksum_method_api_base@@Base+0x189ec6>
│ │  			@ <UNDEFINED> instruction: 0xffefeaff
│ │  	lsls	r3, r6, #7
│ │ -	vshr.u64	d27, d5, #39
│ │ +	vshr.u64	d27, d28, #39
│ │  	vsubl.u16	q8, d10, d31
│ │ -	vshr.u64	<illegal reg q13.5>, <illegal reg q0.5>, #39
│ │ +	vshr.u64	<illegal reg q13.5>, q12, #39
│ │  			@ <UNDEFINED> instruction: 0xffda4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2f6600 <uniffi_pbcli_checksum_method_api_base@@Base+0x189d7c>
│ │  	movs	r0, r0
│ │  	b.n	2f678a <uniffi_pbcli_checksum_method_api_base@@Base+0x189f06>
│ │  	movs	r0, r0
│ │  	asrs	r1, r2, #13
│ │ @@ -731078,21 +731078,21 @@
│ │  	b.n	2f6c2e <uniffi_pbcli_checksum_method_api_base@@Base+0x18a3aa>
│ │  	strh	r1, [r4, #22]
│ │  			@ <UNDEFINED> instruction: 0xebffffd3
│ │  			@ <UNDEFINED> instruction: 0xeafffddb
│ │  	vqdmulh.s16	q9, q12, d5[3]
│ │  	vshr.u16	q8, <illegal reg q5.5>, #7
│ │  	vqrdmlsh.s16	<illegal reg q15.5>, <illegal reg q4.5>, d7[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd8fb4d
│ │ +			@ <UNDEFINED> instruction: 0xffd8fb74
│ │  			@ <UNDEFINED> instruction: 0xffd9ff2f
│ │ -			@ <UNDEFINED> instruction: 0xffd8fb15
│ │ +			@ <UNDEFINED> instruction: 0xffd8fb3c
│ │  	vmul.f16	q12, <illegal reg q4.5>, d3[0]
│ │  			@ <UNDEFINED> instruction: 0xffd85e94
│ │  	vqrdmlah.s16	<illegal reg q15.5>, <illegal reg q12.5>, d7[3]
│ │ -			@ <UNDEFINED> instruction: 0xffd8fad5
│ │ +			@ <UNDEFINED> instruction: 0xffd8fafc
│ │  	vsubw.u16	q15, <illegal reg q12.5>, d11
│ │  			@ <UNDEFINED> instruction: 0xffd9fe77
│ │  	vqshlu.s64	q15, q0, #24
│ │  	vqrdmlah.s16	<illegal reg q15.5>, q4, d7[0]
│ │  	vmls.i16	<illegal reg q13.5>, q12, d5[1]
│ │  			@ <UNDEFINED> instruction: 0xffd9fdf7
│ │  	vaddl.u16	q8, d8, d1
│ │ @@ -731396,15 +731396,15 @@
│ │  	ands	r0, r0
│ │  	b.n	2f6f36 <uniffi_pbcli_checksum_method_api_base@@Base+0x18a6b2>
│ │  	strh	r7, [r3, #16]
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	2f6b3e <uniffi_pbcli_checksum_method_api_base@@Base+0x18a2ba>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r2, r3, r4, r6, r7, r8, ip, lr}
│ │ -	vqdmulh.s16	q8, q4, d0[3]
│ │ +	vmull.u16	q8, d24, d15
│ │  			@ <UNDEFINED> instruction: 0xffda4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2f6d2c <uniffi_pbcli_checksum_method_api_base@@Base+0x18a4a8>
│ │  	movs	r0, r0
│ │  	b.n	2f6eb6 <uniffi_pbcli_checksum_method_api_base@@Base+0x18a632>
│ │  	movs	r0, r1
│ │  	lsrs	r0, r0, #8
│ │ @@ -731504,15 +731504,15 @@
│ │  	b.n	2f6c36 <uniffi_pbcli_checksum_method_api_base@@Base+0x18a3b2>
│ │  	asrs	r5, r0, #32
│ │  	b.n	2f6c3a <uniffi_pbcli_checksum_method_api_base@@Base+0x18a3b6>
│ │  	movs	r0, #154	@ 0x9a
│ │  	b.n	2f703e <uniffi_pbcli_checksum_method_api_base@@Base+0x18a7ba>
│ │  	ldr	r0, [pc, #192]	@ (2f69c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x18a13c>)
│ │  	ldmia.w	sp!, {r0, r4, r5, r6, r8, fp, ip, pc}
│ │ -	and.w	fp, r0, pc, asr #1
│ │ +	and.w	fp, r0, r6, lsr #2
│ │  	vshr.u16	d16, d0, #6
│ │  	b.n	2f6e0e <uniffi_pbcli_checksum_method_api_base@@Base+0x18a58a>
│ │  	subs	r7, r3, #6
│ │  	b.n	2f6c32 <uniffi_pbcli_checksum_method_api_base@@Base+0x18a3ae>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2f6e18 <uniffi_pbcli_checksum_method_api_base@@Base+0x18a594>
│ │  	cmp	r7, #145	@ 0x91
│ │ @@ -731883,20 +731883,20 @@
│ │  	b.n	2f7392 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ab0e>
│ │  	movs	r6, r0
│ │  	b.n	2f6f96 <uniffi_pbcli_checksum_method_api_base@@Base+0x18a712>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r2}
│ │  	b.n	2f6f9e <uniffi_pbcli_checksum_method_api_base@@Base+0x18a71a>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r1, r2, r5, r7, r9, fp}
│ │ -	vmul.i16	q8, q5, d3[2]
│ │ -	vqshl.u64	d23, d26, #26
│ │ -			@ <UNDEFINED> instruction: 0xffda08bb
│ │ -	vqshrun.s32	d23, q1, #6
│ │ -	vmlal.u16	q8, d10, d19
│ │ +	ldmia.w	sp!, {r1, r2, r3, r6, r7, r9, fp}
│ │ +	vmlal.u16	q8, d26, d10
│ │ +			@ <UNDEFINED> instruction: 0xffda77e1
│ │ +	vmul.i16	q8, q13, d2[2]
│ │ +	vqshrun.s32	d23, <illegal reg q12.5>, #6
│ │ +	vmul.i16	q8, q5, d2[1]
│ │  	vaddl.u16	<illegal reg q8.5>, d10, d0
│ │  	b.n	2f73be <uniffi_pbcli_checksum_method_api_base@@Base+0x18ab3a>
│ │  			@ <UNDEFINED> instruction: 0xffffeaff
│ │  	ldr	r7, [pc, #960]	@ (2f7044 <uniffi_pbcli_checksum_method_api_base@@Base+0x18a7c0>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2f71a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x18a920>
│ │  	beq.n	2f6cc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x18a440>
│ │ @@ -732415,37 +732415,37 @@
│ │  	b.n	2f744e <uniffi_pbcli_checksum_method_api_base@@Base+0x18abca>
│ │  	beq.n	2f7148 <uniffi_pbcli_checksum_method_api_base@@Base+0x18a8c4>
│ │  	b.n	2f75a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ad24>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, ip, lr}
│ │  	b.n	2f785a <uniffi_pbcli_checksum_method_api_base@@Base+0x18afd6>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │ -	lsls	r7, r3, #28
│ │ +	lsls	r6, r0, #29
│ │  	vmull.u16	q13, d10, d19
│ │ -	vqshlu.s16	q8, <illegal reg q9.5>, #9
│ │ -			@ <UNDEFINED> instruction: 0xffda074f
│ │ +	vqshlu.s64	d16, d10, #25
│ │ +	vqshl.u16	q8, q11, #10
│ │  			@ <UNDEFINED> instruction: 0xffdaac53
│ │  			@ <UNDEFINED> instruction: 0xffd9fb24
│ │  	vsli.64	q11, q6, #63	@ 0x3f
│ │  	movs	r6, r3
│ │  	str	r4, [r6, #56]	@ 0x38
│ │  	movs	r6, r3
│ │  			@ <UNDEFINED> instruction: 0xfaccffff
│ │  	str	r4, [r0, #88]	@ 0x58
│ │  	movs	r6, r3
│ │  	str	r4, [r3, #52]	@ 0x34
│ │  	movs	r6, r3
│ │ -	lsls	r7, r3, #15
│ │ -	vrsra.u64	d16, d3, #38
│ │ +	lsls	r6, r0, #16
│ │ +	vrsra.u64	d16, d26, #38
│ │  			@ <UNDEFINED> instruction: 0xffdaa897
│ │ -	vraddhn.i32	d16, <illegal reg q4.5>, <illegal reg q9.5>
│ │ +	vmls.i16	q8, <illegal reg q4.5>, d2[1]
│ │  			@ <UNDEFINED> instruction: 0xffdaa927
│ │ -	vrsubhn.i32	d16, <illegal reg q12.5>, <illegal reg q11.5>
│ │ +	vmlsl.u16	q8, d25, d6[1]
│ │  			@ <UNDEFINED> instruction: 0xffdaabab
│ │ -	vmls.i16	q8, <illegal reg q4.5>, d7[3]
│ │ +	vsri.64	d16, d6, #39
│ │  	vqrshrn.u32	d26, <illegal reg q9.5>, #6
│ │  			@ <UNDEFINED> instruction: 0xffd94df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2f7690 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ae0c>
│ │  	beq.n	2f7188 <uniffi_pbcli_checksum_method_api_base@@Base+0x18a904>
│ │  	b.n	2f7614 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ad90>
│ │  	ands	r0, r0
│ │ @@ -732805,28 +732805,28 @@
│ │  	b.n	2f75b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ad30>
│ │  	ldrb	r2, [r7, #26]
│ │  			@ <UNDEFINED> instruction: 0xebff0006
│ │  	b.n	2f7bde <uniffi_pbcli_checksum_method_api_base@@Base+0x18b35a>
│ │  	asrs	r1, r3, #2
│ │  	b.n	2f7be2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18b35e>
│ │  			@ <UNDEFINED> instruction: 0xff84eaff
│ │ -	lsls	r3, r5, #6
│ │ -	vqrdmlah.s16	<illegal reg q12.5>, q13, d0[1]
│ │ -	vshr.u64	d16, d23, #38
│ │ -			@ <UNDEFINED> instruction: 0xffda9dd4
│ │ -	vaddl.u16	q8, d26, d15
│ │ -			@ <UNDEFINED> instruction: 0xffda9dac
│ │ -	vshr.u16	q8, <illegal reg q1.5>, #6
│ │ -			@ <UNDEFINED> instruction: 0xffda9d70
│ │ -	vshr.u16	d16, d15, #6
│ │ -			@ <UNDEFINED> instruction: 0xffda9d3c
│ │ -			@ <UNDEFINED> instruction: 0xffdafff7
│ │ -			@ <UNDEFINED> instruction: 0xffd99d14
│ │ -			@ <UNDEFINED> instruction: 0xffdaffbf
│ │ -			@ <UNDEFINED> instruction: 0xffd99cdc
│ │ +	lsls	r2, r2, #7
│ │ +	vqrdmlah.s16	<illegal reg q12.5>, q13, d7[3]
│ │ +	vshr.u64	q8, q7, #38
│ │ +			@ <UNDEFINED> instruction: 0xffda9dfb
│ │ +	vshr.u64	d16, d22, #38
│ │ +			@ <UNDEFINED> instruction: 0xffda9dd3
│ │ +	vshr.u16	q8, q13, #6
│ │ +			@ <UNDEFINED> instruction: 0xffda9d97
│ │ +	vmla.i16	q8, q5, d6[0]
│ │ +	vqrdmulh.s16	<illegal reg q12.5>, q5, d3[2]
│ │ +	vshr.u16	d16, d14, #6
│ │ +			@ <UNDEFINED> instruction: 0xffda9d3b
│ │ +	vqrdmlsh.s16	<illegal reg q15.5>, q13, d6[2]
│ │ +			@ <UNDEFINED> instruction: 0xffd99d03
│ │  	vaddl.u16	q9, d10, d1
│ │  	b.n	2f7c22 <uniffi_pbcli_checksum_method_api_base@@Base+0x18b39e>
│ │  	vpmin.u32	q7, <illegal reg q8.5>, <illegal reg q15.5>
│ │  	ldr	r4, [pc, #448]	@ (2f76a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ae24>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2f7a08 <uniffi_pbcli_checksum_method_api_base@@Base+0x18b184>
│ │  	movs	r0, r0
│ │ @@ -733024,23 +733024,23 @@
│ │  	b.n	2f7dda <uniffi_pbcli_checksum_method_api_base@@Base+0x18b556>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r6}
│ │  	b.n	2f71ce <uniffi_pbcli_checksum_method_api_base@@Base+0x18a94a>
│ │  	adds	r0, #96	@ 0x60
│ │  	b.n	2f71c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x18a942>
│ │  			@ <UNDEFINED> instruction: 0xffd2eaff
│ │ -	vminnm.f16	<illegal reg q7.5>, <illegal reg q15.5>, <illegal reg q4.5>
│ │ +	vminnm.f32	<illegal reg q15.5>, q11, <illegal reg q4.5>
│ │  	lsls	r3, r2, #20
│ │ -			@ <UNDEFINED> instruction: 0xffd9ff03
│ │ +			@ <UNDEFINED> instruction: 0xffd9ff2a
│ │  	vsri.64	q8, <illegal reg q3.5>, #39
│ │ -	vmull.p<illegal width 16>	<illegal reg q15.5>, d25, d7
│ │ +	vmull.p<illegal width 16>	<illegal reg q15.5>, d25, d30
│ │  	vsri.16	q8, <illegal reg q5.5>, #7
│ │ -	vqrdmulh.s16	<illegal reg q15.5>, <illegal reg q12.5>, d3[2]
│ │ +	vmull.p<illegal width 16>	<illegal reg q15.5>, d9, d10
│ │  	vrsra.u64	d16, d23, #39
│ │ -	vmull.p<illegal width 16>	<illegal reg q15.5>, d9, d15
│ │ +			@ <UNDEFINED> instruction: 0xffd9fe36
│ │  			@ <UNDEFINED> instruction: 0xffd903e3
│ │  			@ <UNDEFINED> instruction: 0xffd948f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2f7bf4 <uniffi_pbcli_checksum_method_api_base@@Base+0x18b370>
│ │  	ands	r0, r0
│ │  	b.n	2f7e1e <uniffi_pbcli_checksum_method_api_base@@Base+0x18b59a>
│ │  	movs	r0, r0
│ │ @@ -733303,15 +733303,15 @@
│ │  	b.n	2f7c72 <uniffi_pbcli_checksum_method_api_base@@Base+0x18b3ee>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2f7a54 <uniffi_pbcli_checksum_method_api_base@@Base+0x18b1d0>
│ │  	str	r5, [sp, #400]	@ 0x190
│ │  			@ <UNDEFINED> instruction: 0xeb00ffca
│ │  			@ <UNDEFINED> instruction: 0xeaff414b
│ │  	vmla.i16	q10, q12, d7[0]
│ │ -			@ <UNDEFINED> instruction: 0xffd853e3
│ │ +	vraddhn.i32	d21, q4, q5
│ │  	vshr.u64	d20, d11, #38
│ │  	vaddl.u16	q8, d8, d0
│ │  	b.n	2f7472 <uniffi_pbcli_checksum_method_api_base@@Base+0x18abee>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (2f7a18 <uniffi_pbcli_checksum_method_api_base@@Base+0x18b194>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2f7e78 <uniffi_pbcli_checksum_method_api_base@@Base+0x18b5f4>
│ │ @@ -734653,51 +734653,51 @@
│ │  	b.n	2f8084 <uniffi_pbcli_checksum_method_api_base@@Base+0x18b800>
│ │  	movs	r0, r0
│ │  	b.n	2f8668 <uniffi_pbcli_checksum_method_api_base@@Base+0x18bde4>
│ │  	movs	r0, #2
│ │  	b.n	2f866c <uniffi_pbcli_checksum_method_api_base@@Base+0x18bde8>
│ │  			@ <UNDEFINED> instruction: 0xff91eaff
│ │  	b.n	2f8b7c <uniffi_pbcli_checksum_method_api_base@@Base+0x18c2f8>
│ │ -			@ <UNDEFINED> instruction: 0xffd878f2
│ │ +	vqshrn.u32	d23, <illegal reg q4.5>, #8
│ │  	vmlal.u16	q15, d10, d4[2]
│ │ -	vmul.i16	<illegal reg q11.5>, q4, d2[0]
│ │ +	vmul.i16	<illegal reg q11.5>, q4, d1[3]
│ │  	vqrdmlsh.s16	<illegal reg q14.5>, q13, d0[0]
│ │ -	vsli.64	d23, d14, #24
│ │ +	vmls.f16	<illegal reg q11.5>, q12, d5[0]
│ │  	vsubl.u16	q15, d10, d12
│ │  	vrshr.u64	d30, d4, #40
│ │ -	vqrshrun.s32	d23, q9, #8
│ │ +			@ <UNDEFINED> instruction: 0xffd87899
│ │  			@ <UNDEFINED> instruction: 0xffdadfdc
│ │ -	vsli.64	d23, d26, #24
│ │ +	vmls.f16	<illegal reg q11.5>, q12, d1[2]
│ │  	vmlsl.u16	q8, d26, d0[1]
│ │  	movs	r0, r0
│ │  	strh	r0, [r1, r3]
│ │  	movs	r6, r3
│ │  	strh	r0, [r7, r2]
│ │  	movs	r6, r3
│ │  	lsls	r0, r6, #25
│ │  	movs	r0, r0
│ │  	strh	r0, [r6, r1]
│ │  	movs	r6, r3
│ │  	strh	r0, [r4, r1]
│ │  	movs	r6, r3
│ │  	svc	112	@ 0x70
│ │ -	vmls.f16	<illegal reg q11.5>, q4, d6[1]
│ │ +	vsli.16	<illegal reg q11.5>, <illegal reg q10.5>, #8
│ │  			@ <UNDEFINED> instruction: 0xffdadeb0
│ │  			@ <UNDEFINED> instruction: 0xffd8de7c
│ │ -	vsri.16	<illegal reg q11.5>, q5, #8
│ │ +	vraddhn.i32	d23, q12, <illegal reg q0.5>
│ │  			@ <UNDEFINED> instruction: 0xffdadf8c
│ │ -	vmls.f16	<illegal reg q11.5>, q4, d2[3]
│ │ +	vsli.64	d23, d1, #24
│ │  			@ <UNDEFINED> instruction: 0xffdadf3c
│ │ -	vsli.16	d23, d10, #8
│ │ +	vmls.f16	<illegal reg q11.5>, q4, d1[0]
│ │  			@ <UNDEFINED> instruction: 0xffdade18
│ │ -	vrsra.u64	<illegal reg q11.5>, q11, #40
│ │ +	vsri.16	d23, d13, #8
│ │  			@ <UNDEFINED> instruction: 0xffdaddbc
│ │ -	vrsra.u64	d23, d10, #40
│ │ +			@ <UNDEFINED> instruction: 0xffd873c1
│ │  	vqrdmlah.s16	<illegal reg q14.5>, q13, d4[1]
│ │ -	vraddhn.i32	d23, q12, q13
│ │ +	vsri.64	<illegal reg q11.5>, <illegal reg q0.5>, #40
│ │  	vaddl.u16	q9, d10, d1
│ │  	b.n	2f8916 <uniffi_pbcli_checksum_method_api_base@@Base+0x18c092>
│ │  	subs	r1, r0, r0
│ │  	b.n	2f8d1a <uniffi_pbcli_checksum_method_api_base@@Base+0x18c496>
│ │  	adds	r0, #0
│ │  	b.n	2f8d1e <uniffi_pbcli_checksum_method_api_base@@Base+0x18c49a>
│ │  	mrc2	10, 3, lr, cr4, cr15, {7}	@ <UNPREDICTABLE>
│ │ @@ -734786,17 +734786,17 @@
│ │  	movs	r0, #0
│ │  	b.n	2f8dda <uniffi_pbcli_checksum_method_api_base@@Base+0x18c556>
│ │  	ldrb	r6, [r6, #9]
│ │  			@ <UNDEFINED> instruction: 0xebff0001
│ │  	b.n	2f8e62 <uniffi_pbcli_checksum_method_api_base@@Base+0x18c5de>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r2, r4, r5, r7, sl, fp, ip, lr, pc}
│ │ -	vabdl.u16	<illegal reg q8.5>, d24, d26
│ │ +	vqshl.u64	<illegal reg q8.5>, <illegal reg q0.5>, #24
│ │  	vmull.u16	<illegal reg q14.5>, d26, d0
│ │ -	vqshl.u16	<illegal reg q8.5>, q11, #8
│ │ +	vqshl.u64	d17, d13, #24
│ │  	vaddl.u16	q9, d10, d1
│ │  	b.n	2f89fa <uniffi_pbcli_checksum_method_api_base@@Base+0x18c176>
│ │  	subs	r2, r0, r0
│ │  	b.n	2f8dfe <uniffi_pbcli_checksum_method_api_base@@Base+0x18c57a>
│ │  	adds	r0, #0
│ │  	b.n	2f8e02 <uniffi_pbcli_checksum_method_api_base@@Base+0x18c57e>
│ │  	mrc2	10, 1, lr, cr11, cr15, {7}	@ <UNPREDICTABLE>
│ │ @@ -735442,15 +735442,15 @@
│ │  	b.n	2f93c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18cb3e>
│ │  	str	r0, [r0, r0]
│ │  	b.n	2f93c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x18cb42>
│ │  	ldrb	r3, [r7, #3]
│ │  			@ <UNDEFINED> instruction: 0xebff0005
│ │  	b.n	2f8fce <uniffi_pbcli_checksum_method_api_base@@Base+0x18c74a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r5, r7, r9, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r6, r7, r9, ip, sp, pc}
│ │  	vsli.16	q8, <illegal reg q12.5>, #10
│ │  			@ <UNDEFINED> instruction: 0xffd94c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2f91bc <uniffi_pbcli_checksum_method_api_base@@Base+0x18c938>
│ │  	beq.n	2f8d94 <uniffi_pbcli_checksum_method_api_base@@Base+0x18c510>
│ │  	b.n	2f9140 <uniffi_pbcli_checksum_method_api_base@@Base+0x18c8bc>
│ │  	ands	r0, r0
│ │ @@ -735627,15 +735627,15 @@
│ │  	ldrb	r2, [r2, #2]
│ │  			@ <UNDEFINED> instruction: 0xebff0005
│ │  	b.n	2f9172 <uniffi_pbcli_checksum_method_api_base@@Base+0x18c8ee>
│ │  	asrs	r4, r5, #31
│ │  	add.w	r0, r0, r4
│ │  	b.n	2f917a <uniffi_pbcli_checksum_method_api_base@@Base+0x18c8f6>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r3, r4, r5, r6, r7, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r4, r8, ip, sp, pc}
│ │  	vmull.u16	q15, d10, d19
│ │  			@ <UNDEFINED> instruction: 0xffd84bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2f9368 <uniffi_pbcli_checksum_method_api_base@@Base+0x18cae4>
│ │  	beq.n	2f8e70 <uniffi_pbcli_checksum_method_api_base@@Base+0x18c5ec>
│ │  	b.n	2f92ec <uniffi_pbcli_checksum_method_api_base@@Base+0x18ca68>
│ │  	movs	r0, r0
│ │ @@ -736114,16 +736114,16 @@
│ │  	b.n	2f9390 <uniffi_pbcli_checksum_method_api_base@@Base+0x18cb0c>
│ │  	ldrh	r5, [r2, #56]	@ 0x38
│ │  	add.w	r0, r0, r0, lsl #16
│ │  	b.n	2f99ba <uniffi_pbcli_checksum_method_api_base@@Base+0x18d136>
│ │  	movs	r4, r0
│ │  	b.n	2f95be <uniffi_pbcli_checksum_method_api_base@@Base+0x18cd3a>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r2, r3, r4, r5, r6, r7, sl, fp, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffdaac98
│ │ +	ldmia.w	sp!, {r0, r1, r5, r8, sl, fp, sp, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffdaacbf
│ │  			@ <UNDEFINED> instruction: 0xffda4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2f97ac <uniffi_pbcli_checksum_method_api_base@@Base+0x18cf28>
│ │  	ands	r0, r0
│ │  	b.n	2f95d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x18cd52>
│ │  	movs	r0, r0
│ │  	b.n	2f8dba <uniffi_pbcli_checksum_method_api_base@@Base+0x18c536>
│ │ @@ -736139,15 +736139,15 @@
│ │  	b.n	2f95f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18cd6e>
│ │  	movs	r0, #219	@ 0xdb
│ │  	b.n	2f99f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x18d172>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2f93d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x18cb54>
│ │  	ldr	r4, [pc, #64]	@ (2f92fc <uniffi_pbcli_checksum_method_api_base@@Base+0x18ca78>)
│ │  	ldmia.w	sp!, {r1, r8, r9, sl, fp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xea00ac50
│ │ +			@ <UNDEFINED> instruction: 0xea00ac77
│ │  			@ <UNDEFINED> instruction: 0xffda4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2f97e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x18cf64>
│ │  	strh	r0, [r0, #0]
│ │  	b.n	2f9612 <uniffi_pbcli_checksum_method_api_base@@Base+0x18cd8e>
│ │  	movs	r1, r0
│ │  	b.n	2f9616 <uniffi_pbcli_checksum_method_api_base@@Base+0x18cd92>
│ │ @@ -736224,15 +736224,15 @@
│ │  	b.n	2f96b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ce32>
│ │  	ands	r4, r7
│ │  	b.n	2f8e8a <uniffi_pbcli_checksum_method_api_base@@Base+0x18c606>
│ │  	mcr2	11, 2, lr, cr6, cr15, {7}	@ <UNPREDICTABLE>
│ │  	movs	r4, r0
│ │  	b.n	2f96c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ce3e>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r2, r3, r4, r6, r7, r8, r9, fp, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r1, sl, fp, sp, pc}
│ │  	vabdl.u16	q15, d10, d7
│ │  	vaddl.u16	q9, d8, d1
│ │  	b.n	2f96d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ce4e>
│ │  	asrs	r0, r0, #32
│ │  	b.n	2f96d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ce52>
│ │  	movs	r0, r7
│ │  	b.n	2f8eba <uniffi_pbcli_checksum_method_api_base@@Base+0x18c636>
│ │ @@ -736450,15 +736450,15 @@
│ │  	ldr	r7, [pc, #960]	@ (2f9928 <uniffi_pbcli_checksum_method_api_base@@Base+0x18d0a4>)
│ │  	ldmia.w	sp!, {r0, r3, r4, r5, r6, r8, r9}
│ │  			@ <UNDEFINED> instruction: 0xea009000
│ │  	b.n	2f9cb2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18d42e>
│ │  	str	r5, [r0, #0]
│ │  	b.n	2f98b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x18d032>
│ │  			@ <UNDEFINED> instruction: 0xffdbeaff
│ │ -	add	r2, sp, #480	@ 0x1e0
│ │ +	add	r2, sp, #636	@ 0x27c
│ │  	vqrdmlah.s16	q11, q5, d6[0]
│ │  			@ <UNDEFINED> instruction: 0xffd94ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2f9aa4 <uniffi_pbcli_checksum_method_api_base@@Base+0x18d220>
│ │  	beq.n	2f95b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x18cd30>
│ │  	b.n	2f9a28 <uniffi_pbcli_checksum_method_api_base@@Base+0x18d1a4>
│ │  	movs	r0, r0
│ │ @@ -736620,16 +736620,16 @@
│ │  	b.n	2f9a26 <uniffi_pbcli_checksum_method_api_base@@Base+0x18d1a2>
│ │  	lsls	r4, r7, #10
│ │  	add.w	r0, r0, r0, lsl #24
│ │  	b.n	2f9e2e <uniffi_pbcli_checksum_method_api_base@@Base+0x18d5aa>
│ │  			@ <UNDEFINED> instruction: 0xffaceaff
│ │  	subs	r5, #184	@ 0xb8
│ │  	movs	r6, r3
│ │ -	add	r0, sp, #304	@ 0x130
│ │ -			@ <UNDEFINED> instruction: 0xffda1e13
│ │ +	add	r0, sp, #460	@ 0x1cc
│ │ +			@ <UNDEFINED> instruction: 0xffda1e3a
│ │  			@ <UNDEFINED> instruction: 0xffda4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2f9c20 <uniffi_pbcli_checksum_method_api_base@@Base+0x18d39c>
│ │  	ands	r3, r0
│ │  	b.n	2f9a4a <uniffi_pbcli_checksum_method_api_base@@Base+0x18d1c6>
│ │  	adds	r0, #8
│ │  	b.n	2f9244 <uniffi_pbcli_checksum_method_api_base@@Base+0x18c9c0>
│ │ @@ -736697,15 +736697,15 @@
│ │  	b.n	2f9ada <uniffi_pbcli_checksum_method_api_base@@Base+0x18d256>
│ │  	ands	r4, r7
│ │  	b.n	2f92aa <uniffi_pbcli_checksum_method_api_base@@Base+0x18ca26>
│ │  	ldc2	11, cr14, [sp, #-1020]!	@ 0xfffffc04	@ <UNPREDICTABLE>
│ │  	movs	r4, r0
│ │  	b.n	2f9ae6 <uniffi_pbcli_checksum_method_api_base@@Base+0x18d262>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r3, r4, r5, r7, r8, r9, sl, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r4, r6, r7, r8, r9, sl, sp, pc}
│ │  	vmlal.u16	q15, d26, d3[2]
│ │  			@ <UNDEFINED> instruction: 0xffd84ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2f9cd4 <uniffi_pbcli_checksum_method_api_base@@Base+0x18d450>
│ │  	svc	77	@ 0x4d
│ │  	b.n	2f9c58 <uniffi_pbcli_checksum_method_api_base@@Base+0x18d3d4>
│ │  	movs	r4, r1
│ │ @@ -737606,15 +737606,15 @@
│ │  	asrs	r0, r1, #32
│ │  	b.n	2f9ae6 <uniffi_pbcli_checksum_method_api_base@@Base+0x18d262>
│ │  			@ <UNDEFINED> instruction: 0xffdaeaff
│ │  	add	sp, #464	@ 0x1d0
│ │  			@ <UNDEFINED> instruction: 0xffd8ab24
│ │  			@ <UNDEFINED> instruction: 0xffd8ab90
│ │  			@ <UNDEFINED> instruction: 0xffd8ab5c
│ │ -	vmlsl.u16	<illegal reg q13.5>, d8, d3[0]
│ │ +	vmlsl.u16	<illegal reg q13.5>, d8, d2[3]
│ │  	vraddhn.i32	d16, q5, q10
│ │  	movs	r0, r0
│ │  	movs	r0, r3
│ │  	b.n	2fa4fe <uniffi_pbcli_checksum_method_api_base@@Base+0x18dc7a>
│ │  	subs	r7, r3, #6
│ │  	b.n	2fa322 <uniffi_pbcli_checksum_method_api_base@@Base+0x18da9e>
│ │  	asrs	r1, r0, #32
│ │ @@ -739620,42 +739620,42 @@
│ │  	movs	r0, #72	@ 0x48
│ │  	b.n	2fad98 <uniffi_pbcli_checksum_method_api_base@@Base+0x18e514>
│ │  	movs	r0, r0
│ │  	b.n	2fb37c <uniffi_pbcli_checksum_method_api_base@@Base+0x18eaf8>
│ │  	movs	r0, #2
│ │  	b.n	2fb380 <uniffi_pbcli_checksum_method_api_base@@Base+0x18eafc>
│ │  			@ <UNDEFINED> instruction: 0xffe4eaff
│ │ -	ble.n	2fb2d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ea50>
│ │ +	ble.n	2fb322 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ea9e>
│ │  	vqshlu.s64	q12, q10, #25
│ │  	vmlal.u16	<illegal reg q10.5>, d9, d5
│ │ -	vqdmulh.s16	<illegal reg q14.5>, <illegal reg q12.5>, d2[2]
│ │ +			@ <UNDEFINED> instruction: 0xffd9dd09
│ │  	vrsubhn.i32	d24, <illegal reg q12.5>, q8
│ │ -			@ <UNDEFINED> instruction: 0xffd9dc1e
│ │ +	vqdmulh.s16	<illegal reg q14.5>, <illegal reg q4.5>, d5[0]
│ │  	vsli.64	q12, q6, #25
│ │ -			@ <UNDEFINED> instruction: 0xffd9d8d6
│ │ +			@ <UNDEFINED> instruction: 0xffd9d8fd
│ │  	vrshr.u64	d24, d4, #39
│ │ -	vqshl.u16	<illegal reg q14.5>, q7, #9
│ │ +	vabdl.u16	<illegal reg q14.5>, d25, d5
│ │  	vsra.u16	d24, d12, #7
│ │  	vrshr.u64	<illegal reg q10.5>, <illegal reg q2.5>, #39
│ │ -	vabdl.u16	<illegal reg q14.5>, d9, d6
│ │ +	vabdl.u16	<illegal reg q14.5>, d9, d29
│ │  	vmla.i16	q12, <illegal reg q12.5>, d4[0]
│ │  	vmlal.u16	<illegal reg q10.5>, d9, d1[2]
│ │ -	vsli.64	<illegal reg q14.5>, q11, #25
│ │ +	vqshlu.s16	d29, d13, #9
│ │  			@ <UNDEFINED> instruction: 0xffd97fb4
│ │ -	vqshlu.s16	<illegal reg q14.5>, q7, #9
│ │ +	vrsubhn.i32	d29, <illegal reg q12.5>, <illegal reg q2.5>
│ │  	vshr.u16	d24, d12, #7
│ │ -	vqshlu.s64	d29, d18, #25
│ │ +	vqshlu.s64	<illegal reg q14.5>, <illegal reg q4.5>, #25
│ │  	vshr.u16	q12, q8, #7
│ │ -			@ <UNDEFINED> instruction: 0xffd9dabe
│ │ +	vmull.u16	<illegal reg q14.5>, d25, d5[2]
│ │  	vsri.16	q12, q14, #7
│ │  			@ <UNDEFINED> instruction: 0xffd90ff8
│ │  	movs	r0, r0
│ │  	lsrs	r4, r3, #31
│ │  	movs	r0, r0
│ │ -	bge.n	2fb320 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ea9c>
│ │ +	bge.n	2fb36e <uniffi_pbcli_checksum_method_api_base@@Base+0x18eaea>
│ │  			@ <UNDEFINED> instruction: 0xffd983e8
│ │  	vmlal.u16	q10, d9, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2fb61a <uniffi_pbcli_checksum_method_api_base@@Base+0x18ed96>
│ │  	beq.n	2fb30c <uniffi_pbcli_checksum_method_api_base@@Base+0x18ea88>
│ │  	b.n	2fb778 <uniffi_pbcli_checksum_method_api_base@@Base+0x18eef4>
│ │  	b.n	2fb2e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ea5c>
│ │ @@ -739861,17 +739861,17 @@
│ │  			@ <UNDEFINED> instruction: 0xebff1101
│ │  	b.n	2fba9a <uniffi_pbcli_checksum_method_api_base@@Base+0x18f216>
│ │  	movs	r6, r0
│ │  	b.n	2fbbde <uniffi_pbcli_checksum_method_api_base@@Base+0x18f35a>
│ │  	asrs	r4, r1, #32
│ │  	b.n	2fbb22 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f29e>
│ │  			@ <UNDEFINED> instruction: 0xffe9eaff
│ │ -	bmi.n	2fb4d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ec50>
│ │ +	bmi.n	2fb522 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ec9e>
│ │  	vqrdmlah.s16	q13, <illegal reg q12.5>, d4[3]
│ │ -			@ <UNDEFINED> instruction: 0xffd8d3c6
│ │ +			@ <UNDEFINED> instruction: 0xffd8d3ed
│ │  			@ <UNDEFINED> instruction: 0xffd9ae9c
│ │  			@ <UNDEFINED> instruction: 0xffd848f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2fb9d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f154>
│ │  	str	r0, [r0, #0]
│ │  	b.n	2fb802 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ef7e>
│ │  	movs	r5, r1
│ │ @@ -739989,18 +739989,18 @@
│ │  			@ <UNDEFINED> instruction: 0xebff1101
│ │  	b.n	2fbbba <uniffi_pbcli_checksum_method_api_base@@Base+0x18f336>
│ │  	movs	r6, r0
│ │  	b.n	2fbcfe <uniffi_pbcli_checksum_method_api_base@@Base+0x18f47a>
│ │  	asrs	r4, r1, #32
│ │  	b.n	2fbc42 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f3be>
│ │  			@ <UNDEFINED> instruction: 0xffe9eaff
│ │ -	bcs.n	2fb5b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ed30>
│ │ -	vrsra.u64	d20, d3, #39
│ │ -	vsubl.u16	<illegal reg q14.5>, d26, d22
│ │ -			@ <UNDEFINED> instruction: 0xffd94343
│ │ +	bcc.n	2fb602 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ed7e>
│ │ +	vrsra.u64	d20, d26, #39
│ │ +	vmlal.u16	<illegal reg q14.5>, d26, d5[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd9436a
│ │  			@ <UNDEFINED> instruction: 0xffda4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2fbaf8 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f274>
│ │  	beq.n	2fb678 <uniffi_pbcli_checksum_method_api_base@@Base+0x18edf4>
│ │  	b.n	2fba7c <uniffi_pbcli_checksum_method_api_base@@Base+0x18f1f8>
│ │  	str	r1, [r0, r0]
│ │  	b.n	2fb926 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f0a2>
│ │ @@ -740413,18 +740413,18 @@
│ │  	bge.n	2fb966 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f0e2>
│ │  	ands	r1, r0
│ │  	b.n	2fc0aa <uniffi_pbcli_checksum_method_api_base@@Base+0x18f826>
│ │  	vpmin.u<illegal width 64>	q15, <illegal reg q8.5>, <illegal reg q15.5>
│ │  	ands	r0, r0
│ │  	b.n	2fc0b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f82e>
│ │  	vpmin.u32	q15, <illegal reg q15.5>, <illegal reg q15.5>
│ │ -	bne.n	2fba44 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f1c0>
│ │ -			@ <UNDEFINED> instruction: 0xffd9bd75
│ │ -	vsra.u16	d29, d26, #7
│ │ -	vqrdmulh.s16	<illegal reg q13.5>, <illegal reg q4.5>, d1[1]
│ │ +	bne.n	2fb892 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f00e>
│ │ +			@ <UNDEFINED> instruction: 0xffd9bd9c
│ │ +	vmla.f16	<illegal reg q14.5>, <illegal reg q4.5>, d1[2]
│ │ +			@ <UNDEFINED> instruction: 0xffd9bd70
│ │  			@ <UNDEFINED> instruction: 0xffd948f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2fbea8 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f624>
│ │  	beq.n	2fb9a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f11c>
│ │  	b.n	2fbe2c <uniffi_pbcli_checksum_method_api_base@@Base+0x18f5a8>
│ │  	str	r1, [r0, r0]
│ │  	b.n	2fbcd6 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f452>
│ │ @@ -740566,16 +740566,16 @@
│ │  	b.n	2fbdfa <uniffi_pbcli_checksum_method_api_base@@Base+0x18f576>
│ │  	adds	r0, #6
│ │  	b.n	2fbdfe <uniffi_pbcli_checksum_method_api_base@@Base+0x18f57a>
│ │  	vrhadd.u<illegal width 64>	d14, d12, d31
│ │  	beq.n	2fbae4 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f260>
│ │  	b.n	2fbf5c <uniffi_pbcli_checksum_method_api_base@@Base+0x18f6d8>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r9, sl, fp, lr, pc}
│ │ -	vsri.16	q13, <illegal reg q11.5>, #7
│ │ +	ldmia.w	sp!, {r0, r2, r6, r9, sl, fp, lr, pc}
│ │ +	vsri.64	d26, d14, #39
│ │  			@ <UNDEFINED> instruction: 0xffd94ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2fbff4 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f770>
│ │  	beq.n	2fbb74 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f2f0>
│ │  	b.n	2fbf78 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f6f4>
│ │  	str	r1, [r0, r0]
│ │  	b.n	2fbe22 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f59e>
│ │ @@ -740847,18 +740847,18 @@
│ │  	b.n	2fc06e <uniffi_pbcli_checksum_method_api_base@@Base+0x18f7ea>
│ │  	movs	r0, #8
│ │  	b.n	2fc072 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f7ee>
│ │  	subs	r6, #142	@ 0x8e
│ │  	add.w	r0, r0, r0, lsl #28
│ │  	b.n	2fc07a <uniffi_pbcli_checksum_method_api_base@@Base+0x18f7f6>
│ │  			@ <UNDEFINED> instruction: 0xffb7eaff
│ │ -	ldmia	r4, {r1, r3, r4, r5, r6}
│ │ -	vqrshrn.u32	d25, q9, #7
│ │ -			@ <UNDEFINED> instruction: 0xffdacc52
│ │ -	vmul.f16	<illegal reg q12.5>, <illegal reg q4.5>, d2[1]
│ │ +	ldmia	r4!, {r0, r5, r7}
│ │ +			@ <UNDEFINED> instruction: 0xffd99999
│ │ +			@ <UNDEFINED> instruction: 0xffdacc79
│ │ +	vqrshrn.u32	d25, <illegal reg q8.5>, #7
│ │  			@ <UNDEFINED> instruction: 0xffda48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2fc270 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f9ec>
│ │  	str	r0, [r0, #0]
│ │  	b.n	2fc09a <uniffi_pbcli_checksum_method_api_base@@Base+0x18f816>
│ │  	movs	r4, r1
│ │  	b.n	2fb87e <uniffi_pbcli_checksum_method_api_base@@Base+0x18effa>
│ │ @@ -740971,16 +740971,16 @@
│ │  	str	r4, [r2, #0]
│ │  	b.n	2fb96c <uniffi_pbcli_checksum_method_api_base@@Base+0x18f0e8>
│ │  	movs	r0, r3
│ │  	b.n	2fb970 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f0ec>
│ │  	stmia	r0!, {r2, r5, r6}
│ │  	b.n	2fb97e <uniffi_pbcli_checksum_method_api_base@@Base+0x18f0fa>
│ │  			@ <UNDEFINED> instruction: 0xffefeaff
│ │ -	ldmia	r2, {r1, r2, r5, r6}
│ │ -	vrsubhn.i32	d27, <illegal reg q12.5>, <illegal reg q4.5>
│ │ +	ldmia	r2, {r0, r2, r3, r7}
│ │ +	vqshlu.s64	d27, d16, #25
│ │  	vmlal.u16	q10, d9, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2fc1a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f922>
│ │  	ldr	r1, [r1, #64]	@ 0x40
│ │  			@ <UNDEFINED> instruction: 0xebff0028
│ │  	b.n	2fb9ac <uniffi_pbcli_checksum_method_api_base@@Base+0x18f128>
│ │  	asrs	r6, r2, #32
│ │ @@ -740998,15 +740998,15 @@
│ │  	b.n	2fc5ca <uniffi_pbcli_checksum_method_api_base@@Base+0x18fd46>
│ │  	movs	r0, #0
│ │  	b.n	2fc5ce <uniffi_pbcli_checksum_method_api_base@@Base+0x18fd4a>
│ │  	ldr	r1, [r7, #68]	@ 0x44
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	2fc5d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x18fd52>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r3, r4, r6, r7, r8, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r9, fp, lr, pc}
│ │  	vsubw.u16	<illegal reg q11.5>, <illegal reg q12.5>, d23
│ │  			@ <UNDEFINED> instruction: 0xffd94c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2fc3c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x18fb40>
│ │  	asrs	r4, r6, #2
│ │  	b.n	2fb9ec <uniffi_pbcli_checksum_method_api_base@@Base+0x18f168>
│ │  	str	r0, [r0, r0]
│ │ @@ -741087,17 +741087,17 @@
│ │  	b.n	2fc696 <uniffi_pbcli_checksum_method_api_base@@Base+0x18fe12>
│ │  	strh	r4, [r3, #30]
│ │  	add.w	r0, r0, r0, lsl #16
│ │  	b.n	2fc69e <uniffi_pbcli_checksum_method_api_base@@Base+0x18fe1a>
│ │  	movs	r4, r0
│ │  	b.n	2fc2a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18fa1e>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r6, r9, sl, fp}
│ │ -			@ <UNDEFINED> instruction: 0xffda0dd7
│ │ -	vqrdmlah.s16	<illegal reg q14.5>, q13, d7[2]
│ │ +	ldmia.w	sp!, {r1, r3, r5, r6, r9, sl, fp}
│ │ +			@ <UNDEFINED> instruction: 0xffda0dfe
│ │ +			@ <UNDEFINED> instruction: 0xffdadf0e
│ │  	vaddl.u16	q8, d9, d0
│ │  	b.n	2fc616 <uniffi_pbcli_checksum_method_api_base@@Base+0x18fd92>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (2fbfbc <uniffi_pbcli_checksum_method_api_base@@Base+0x18f738>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2fc49c <uniffi_pbcli_checksum_method_api_base@@Base+0x18fc18>
│ │  	asrs	r0, r0, #32
│ │ @@ -741122,15 +741122,15 @@
│ │  	b.n	2fc2ee <uniffi_pbcli_checksum_method_api_base@@Base+0x18fa6a>
│ │  	movs	r0, #47	@ 0x2f
│ │  	b.n	2fc6f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18fe6e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2fc0d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f850>
│ │  	ldr	r4, [pc, #64]	@ (2fbff8 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f774>)
│ │  	ldmia.w	sp!, {r0, r1, r6, r7, r8, r9, pc}
│ │ -	and.w	sp, r0, fp, lsl #1
│ │ +	and.w	sp, r0, r2, ror #1
│ │  			@ <UNDEFINED> instruction: 0xffda4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2fc4e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x18fc60>
│ │  	str	r0, [r0, #0]
│ │  	b.n	2fc30e <uniffi_pbcli_checksum_method_api_base@@Base+0x18fa8a>
│ │  	movs	r4, r0
│ │  	b.n	2fbaf2 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f26e>
│ │ @@ -741230,18 +741230,18 @@
│ │  	b.n	2fc1c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f93c>
│ │  	strh	r1, [r1, #28]
│ │  	add.w	r0, r0, r0, lsl #16
│ │  	b.n	2fc7ea <uniffi_pbcli_checksum_method_api_base@@Base+0x18ff66>
│ │  	movs	r4, r0
│ │  	b.n	2fc3ee <uniffi_pbcli_checksum_method_api_base@@Base+0x18fb6a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r8, sl, fp}
│ │ -	vmull.u16	q8, d26, d31
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r5, r8, sl, fp}
│ │ +			@ <UNDEFINED> instruction: 0xffda0cd6
│ │  	vaddw.u16	<illegal reg q14.5>, q13, d29
│ │ -			@ <UNDEFINED> instruction: 0xffd80c5f
│ │ +	vmull.u16	q8, d24, d6
│ │  	vaddl.u16	q8, d10, d0
│ │  	b.n	2fbbe6 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f362>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (2fc18c <uniffi_pbcli_checksum_method_api_base@@Base+0x18f908>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2fc5ec <uniffi_pbcli_checksum_method_api_base@@Base+0x18fd68>
│ │  	beq.n	2fc134 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f8b0>
│ │ @@ -741612,26 +741612,26 @@
│ │  			@ <UNDEFINED> instruction: 0xebff5000
│ │  	b.n	2fcb4a <uniffi_pbcli_checksum_method_api_base@@Base+0x1902c6>
│ │  	movs	r6, r0
│ │  	b.n	2fcb4e <uniffi_pbcli_checksum_method_api_base@@Base+0x1902ca>
│ │  	asrs	r3, r4, #3
│ │  	b.n	2fcb52 <uniffi_pbcli_checksum_method_api_base@@Base+0x1902ce>
│ │  	vpmin.u<illegal width 64>	q15, <illegal reg q12.5>, <illegal reg q15.5>
│ │ -	lsrs	r7, r2, #12
│ │ -	vqshlu.s16	q14, q14, #10
│ │ -	vmull.u16	q8, d9, d3[2]
│ │ -	vmls.f16	q14, q13, d0[1]
│ │ +	lsrs	r6, r7, #12
│ │ +	vrsubhn.i32	d28, q13, <illegal reg q9.5>
│ │ +	vmlsl.u16	q8, d25, d10
│ │ +	vmls.f16	q14, q13, d7[3]
│ │  	vrshr.u16	<illegal reg q8.5>, <illegal reg q4.5>, #7
│ │ -	vqshrn.u32	d16, <illegal reg q9.5>, #7
│ │ -	vsri.64	d28, d8, #38
│ │ -	vmlsl.u16	q8, d9, d7
│ │ -	vmls.f16	q14, q5, d4[3]
│ │ +	vqrshrn.u32	d16, q5, #7
│ │ +	vsri.64	d28, d31, #38
│ │ +	vmlsl.u16	q8, d9, d30
│ │ +	vsli.64	d28, d3, #26
│ │  	vabdl.u16	<illegal reg q10.5>, d9, d4
│ │ -			@ <UNDEFINED> instruction: 0xffd80903
│ │ -	vmls.i16	q14, q5, d0[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd8092a
│ │ +	vraddhn.i32	d28, q13, <illegal reg q7.5>
│ │  	vaddl.u16	q9, d9, d0
│ │  	b.n	2fbf6a <uniffi_pbcli_checksum_method_api_base@@Base+0x18f6e6>
│ │  	movs	r0, #64	@ 0x40
│ │  	b.n	2fbf72 <uniffi_pbcli_checksum_method_api_base@@Base+0x18f6ee>
│ │  	movs	r0, r0
│ │  	b.n	2fcaf6 <uniffi_pbcli_checksum_method_api_base@@Base+0x190272>
│ │  	movs	r1, r0
│ │ @@ -741965,19 +741965,19 @@
│ │  	movs	r1, #31
│ │  	b.n	2fcd2e <uniffi_pbcli_checksum_method_api_base@@Base+0x1904aa>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2fc850 <uniffi_pbcli_checksum_method_api_base@@Base+0x18ffcc>
│ │  	strh	r5, [r4, #14]
│ │  			@ <UNDEFINED> instruction: 0xeb00ffc5
│ │  			@ <UNDEFINED> instruction: 0xeaffbd14
│ │ -	vrsra.u16	<illegal reg q14.5>, q9, #9
│ │ -	vqshlu.s16	d16, d7, #9
│ │ -	vmls.f16	q8, q13, d7[1]
│ │ -	vqshlu.s16	q8, <illegal reg q15.5>, #10
│ │ -	vqshlu.s16	q8, <illegal reg q5.5>, #10
│ │ +	vrsra.u64	d29, d9, #41
│ │ +	vqshlu.s16	d16, d30, #9
│ │ +	vsli.64	q8, q11, #26
│ │ +	vrsubhn.i32	d16, q13, q11
│ │ +	vrsubhn.i32	d16, q13, q1
│ │  	vrsra.u64	d24, d30, #38
│ │  	vmlal.u16	q10, d8, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2fca9e <uniffi_pbcli_checksum_method_api_base@@Base+0x19021a>
│ │  	beq.n	2fc780 <uniffi_pbcli_checksum_method_api_base@@Base+0x18fefc>
│ │  	b.n	2fcbfc <uniffi_pbcli_checksum_method_api_base@@Base+0x190378>
│ │  	adds	r0, #2
│ │ @@ -742375,21 +742375,21 @@
│ │  	b.n	2fd222 <uniffi_pbcli_checksum_method_api_base@@Base+0x19099e>
│ │  	movs	r0, #0
│ │  	b.n	2fd226 <uniffi_pbcli_checksum_method_api_base@@Base+0x1909a2>
│ │  	ldr	r3, [r4, #20]
│ │  			@ <UNDEFINED> instruction: 0xebff0005
│ │  	b.n	2fce2e <uniffi_pbcli_checksum_method_api_base@@Base+0x1905aa>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r4, r6, r8, sl}
│ │ -	vsubw.u16	q8, q5, d12
│ │ -	vsri.64	d25, d18, #38
│ │ -	vrshr.u64	d16, d20, #39
│ │ -	vrshr.u16	q8, q14, #6
│ │ -	vmlal.u16	q8, d10, d0[1]
│ │ -			@ <UNDEFINED> instruction: 0xffda93ee
│ │ +	ldmia.w	sp!, {r0, r1, r2, r4, r5, r6, r8, sl}
│ │ +	vrsra.u16	d16, d19, #6
│ │ +	vsri.64	<illegal reg q12.5>, <illegal reg q4.5>, #38
│ │ +	vrshr.u64	q8, <illegal reg q5.5>, #39
│ │ +	vsubl.u16	q8, d26, d19
│ │ +	vmlal.u16	q8, d10, d7[3]
│ │ +	vsri.16	d25, d5, #6
│ │  	vshr.u16	d16, d0, #7
│ │  	b.n	2fd012 <uniffi_pbcli_checksum_method_api_base@@Base+0x19078e>
│ │  	subs	r7, r3, #6
│ │  	b.n	2fce36 <uniffi_pbcli_checksum_method_api_base@@Base+0x1905b2>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2fd01c <uniffi_pbcli_checksum_method_api_base@@Base+0x190798>
│ │  	cmp	r7, #145	@ 0x91
│ │ @@ -742447,15 +742447,15 @@
│ │  	b.n	2fced6 <uniffi_pbcli_checksum_method_api_base@@Base+0x190652>
│ │  	asrs	r5, r0, #32
│ │  	b.n	2fceda <uniffi_pbcli_checksum_method_api_base@@Base+0x190656>
│ │  	movs	r0, #42	@ 0x2a
│ │  	b.n	2fd2de <uniffi_pbcli_checksum_method_api_base@@Base+0x190a5a>
│ │  	ldr	r0, [pc, #192]	@ (2fcc60 <uniffi_pbcli_checksum_method_api_base@@Base+0x1903dc>)
│ │  	ldmia.w	sp!, {r0, r3, r6, r7, pc}
│ │ -	and.w	r1, r0, r4, lsr #2
│ │ +	and.w	r1, r0, fp, ror #2
│ │  	vshr.u16	d16, d0, #6
│ │  	b.n	2fd0ae <uniffi_pbcli_checksum_method_api_base@@Base+0x19082a>
│ │  	subs	r7, r3, #6
│ │  	b.n	2fced2 <uniffi_pbcli_checksum_method_api_base@@Base+0x19064e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	2fd0b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x190834>
│ │  	cmp	r7, #145	@ 0x91
│ │ @@ -742513,15 +742513,15 @@
│ │  	b.n	2fcf72 <uniffi_pbcli_checksum_method_api_base@@Base+0x1906ee>
│ │  	asrs	r5, r0, #32
│ │  	b.n	2fcf76 <uniffi_pbcli_checksum_method_api_base@@Base+0x1906f2>
│ │  	movs	r0, #42	@ 0x2a
│ │  	b.n	2fd37a <uniffi_pbcli_checksum_method_api_base@@Base+0x190af6>
│ │  	ldr	r0, [pc, #192]	@ (2fccfc <uniffi_pbcli_checksum_method_api_base@@Base+0x190478>)
│ │  	ldmia.w	sp!, {r1, r5, r7, pc}
│ │ -	and.w	r0, r0, r8, ror #3
│ │ +	and.w	r1, r0, pc, lsr #32
│ │  			@ <UNDEFINED> instruction: 0xffda4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2fd168 <uniffi_pbcli_checksum_method_api_base@@Base+0x1908e4>
│ │  	ands	r0, r0
│ │  	b.n	2fcf92 <uniffi_pbcli_checksum_method_api_base@@Base+0x19070e>
│ │  	movs	r4, r6
│ │  	b.n	2fc776 <uniffi_pbcli_checksum_method_api_base@@Base+0x18fef2>
│ │ @@ -743287,26 +743287,26 @@
│ │  	ldr	r3, [pc, #8]	@ (2fd338 <uniffi_pbcli_checksum_method_api_base@@Base+0x190ab4>)
│ │  			@ <UNDEFINED> instruction: 0xeb00a001
│ │  	b.n	2fda76 <uniffi_pbcli_checksum_method_api_base@@Base+0x1911f2>
│ │  	vpmin.u<illegal width 64>	q15, q9, <illegal reg q15.5>
│ │  	add	r0, pc, #0	@ (adr r0, 2fd33c <uniffi_pbcli_checksum_method_api_base@@Base+0x190ab8>)
│ │  	b.n	2fda7e <uniffi_pbcli_checksum_method_api_base@@Base+0x1911fa>
│ │  	vpmin.u32	q15, <illegal reg q15.5>, <illegal reg q15.5>
│ │ -	ldmia	r5, {r0, r1, r3, r5, r7}
│ │ +	ldmia	r5!, {r1, r4, r6, r7}
│ │  			@ <UNDEFINED> instruction: 0xffd91cb0
│ │ -	vqrdmulh.s16	q14, q4, d7[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd8cd96
│ │  			@ <UNDEFINED> instruction: 0xffd91c74
│ │ -			@ <UNDEFINED> instruction: 0xffd8cdd7
│ │ +			@ <UNDEFINED> instruction: 0xffd8cdfe
│ │  			@ <UNDEFINED> instruction: 0xffd91cdc
│ │ -			@ <UNDEFINED> instruction: 0xffd8cd3f
│ │ +	vqrdmulh.s16	q14, q4, d6[2]
│ │  	vqdmulh.s16	<illegal reg q8.5>, <illegal reg q4.5>, d4[0]
│ │  	vsra.u64	d25, d9, #40
│ │  			@ <UNDEFINED> instruction: 0xffd87894
│ │  	vmul.f16	q14, q12, d3[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd7ca99
│ │ +	vmull.u16	q14, d23, d0[0]
│ │  	vqrdmlsh.s16	q13, <illegal reg q12.5>, d4[1]
│ │  	vqshrun.s32	d20, q8, #9
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2fd898 <uniffi_pbcli_checksum_method_api_base@@Base+0x191014>
│ │  	beq.n	2fd3b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x190b2c>
│ │  	b.n	2fd81c <uniffi_pbcli_checksum_method_api_base@@Base+0x190f98>
│ │  	stmia	r0!, {r3}
│ │ @@ -743572,26 +743572,26 @@
│ │  	strb	r4, [r0, #0]
│ │  	b.n	2fd90e <uniffi_pbcli_checksum_method_api_base@@Base+0x19108a>
│ │  	str	r2, [r1, #0]
│ │  	b.n	2fd912 <uniffi_pbcli_checksum_method_api_base@@Base+0x19108e>
│ │  			@ <UNDEFINED> instruction: 0xffc4eaff
│ │  	bge.n	2fd5d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x190d4c>
│ │  	movs	r2, r3
│ │ -	strh	r2, [r6, r2]
│ │ +	strh	r1, [r3, r3]
│ │  	vmla.i16	q8, q5, d0[1]
│ │ -	vrshr.u16	<illegal reg q10.5>, q13, #7
│ │ +	vsubl.u16	<illegal reg q10.5>, d25, d17
│ │  	vshr.u16	d16, d0, #6
│ │ -	vrshr.u64	<illegal reg q10.5>, q9, #39
│ │ +	vrsra.u16	d21, d9, #7
│ │  			@ <UNDEFINED> instruction: 0xffdad98c
│ │  	movs	r2, r3
│ │ -	str	r6, [r7, r5]
│ │ +	str	r5, [r4, r6]
│ │  			@ <UNDEFINED> instruction: 0xffdaff14
│ │  	vqrshrn.u32	d29, q10, #8
│ │  	movs	r2, r3
│ │ -	strh	r6, [r0, r1]
│ │ +	strh	r5, [r5, r1]
│ │  	vmul.f16	<illegal reg q14.5>, q13, d0[2]
│ │  	movs	r2, r3
│ │  	ldr	r5, [pc, #960]	@ (2fd9c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x191144>)
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	2fdb28 <uniffi_pbcli_checksum_method_api_base@@Base+0x1912a4>
│ │  	beq.n	2fd620 <uniffi_pbcli_checksum_method_api_base@@Base+0x190d9c>
│ │  	b.n	2fdaac <uniffi_pbcli_checksum_method_api_base@@Base+0x191228>
│ │ @@ -743659,16 +743659,16 @@
│ │  	b.n	2fddda <uniffi_pbcli_checksum_method_api_base@@Base+0x191556>
│ │  	str	r6, [r6, #100]	@ 0x64
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	2fd9e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x19115e>
│ │  	beq.n	2fd6d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x190e50>
│ │  	b.n	2fdb3c <uniffi_pbcli_checksum_method_api_base@@Base+0x1912b8>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r1, r6, r7, ip, lr}
│ │ -	vmull.p<illegal width 16>	<illegal reg q12.5>, d10, d10
│ │ +	ldmia.w	sp!, {r0, r3, r5, r6, r7, ip, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffda9e31
│ │  			@ <UNDEFINED> instruction: 0xffd94ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2fdbd4 <uniffi_pbcli_checksum_method_api_base@@Base+0x191350>
│ │  	beq.n	2fd5f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x190d70>
│ │  	b.n	2fdb58 <uniffi_pbcli_checksum_method_api_base@@Base+0x1912d4>
│ │  	str	r0, [r0, r0]
│ │  	b.n	2fda02 <uniffi_pbcli_checksum_method_api_base@@Base+0x19117e>
│ │ @@ -743885,20 +743885,20 @@
│ │  	cmp	r0, r4
│ │  	b.n	2fdbda <uniffi_pbcli_checksum_method_api_base@@Base+0x191356>
│ │  	movs	r4, r0
│ │  	b.n	2fdbde <uniffi_pbcli_checksum_method_api_base@@Base+0x19135a>
│ │  	beq.n	2fd8d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x191054>
│ │  	b.n	2fdd38 <uniffi_pbcli_checksum_method_api_base@@Base+0x1914b4>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r2, r4, r5, r7, r8, sl, fp, ip}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r6, r7, r8, sl, fp, ip}
│ │  			@ <UNDEFINED> instruction: 0xffdabad5
│ │  	vmlal.u16	<illegal reg q11.5>, d24, d0[3]
│ │  	vqrdmulh.s16	<illegal reg q15.5>, q4, d4[1]
│ │  	vsri.16	d28, d7, #8
│ │ -	vsri.64	d28, d29, #41
│ │ +	vmls.i16	q14, <illegal reg q11.5>, d4[2]
│ │  			@ <UNDEFINED> instruction: 0xffd9a9f8
│ │  			@ <UNDEFINED> instruction: 0xffd74c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2fdde4 <uniffi_pbcli_checksum_method_api_base@@Base+0x191560>
│ │  	beq.n	2fd8fc <uniffi_pbcli_checksum_method_api_base@@Base+0x191078>
│ │  	b.n	2fdd68 <uniffi_pbcli_checksum_method_api_base@@Base+0x1914e4>
│ │  	stmia	r0!, {r2, r3}
│ │ @@ -744615,15 +744615,15 @@
│ │  	vqshl.u64	<illegal reg q15.5>, <illegal reg q3.5>, #24
│ │  			@ <UNDEFINED> instruction: 0xffd79bfd
│ │  	vqshlu.s64	d31, d15, #24
│ │  			@ <UNDEFINED> instruction: 0xffd79b85
│ │  	vrsubhn.i32	d31, q4, <illegal reg q11.5>
│ │  			@ <UNDEFINED> instruction: 0xffd79bc9
│ │  	vmlsl.u16	<illegal reg q15.5>, d8, d3[3]
│ │ -	vqrdmlsh.s16	<illegal reg q11.5>, <illegal reg q11.5>, d1[0]
│ │ +	vqrdmlsh.s16	<illegal reg q11.5>, <illegal reg q11.5>, d0[3]
│ │  			@ <UNDEFINED> instruction: 0xffd99b4d
│ │  	vmlal.u16	q10, d8, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2fe2a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x191a22>
│ │  	beq.n	2fdf98 <uniffi_pbcli_checksum_method_api_base@@Base+0x191714>
│ │  	b.n	2fe404 <uniffi_pbcli_checksum_method_api_base@@Base+0x191b80>
│ │  	b.n	2fdf6c <uniffi_pbcli_checksum_method_api_base@@Base+0x1916e8>
│ │ @@ -744783,15 +744783,15 @@
│ │  	movs	r0, #0
│ │  	b.n	2fe822 <uniffi_pbcli_checksum_method_api_base@@Base+0x191f9e>
│ │  	str	r4, [r4, #60]	@ 0x3c
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	2fe82a <uniffi_pbcli_checksum_method_api_base@@Base+0x191fa6>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r0, r2, r7, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd85e51
│ │ +			@ <UNDEFINED> instruction: 0xffd85e78
│ │  			@ <UNDEFINED> instruction: 0xffda4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2fe618 <uniffi_pbcli_checksum_method_api_base@@Base+0x191d94>
│ │  	ands	r0, r0
│ │  	b.n	2fe442 <uniffi_pbcli_checksum_method_api_base@@Base+0x191bbe>
│ │  	lsls	r2, r4, #28
│ │  	add.w	pc, r0, r6, asr #1
│ │ @@ -744821,15 +744821,15 @@
│ │  	movs	r0, #0
│ │  	b.n	2fe882 <uniffi_pbcli_checksum_method_api_base@@Base+0x191ffe>
│ │  	str	r4, [r1, #60]	@ 0x3c
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	2fe88a <uniffi_pbcli_checksum_method_api_base@@Base+0x192006>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r0, r2, r5, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd85df1
│ │ +			@ <UNDEFINED> instruction: 0xffd85e18
│ │  	vqshrun.s32	d20, q8, #6
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2fe678 <uniffi_pbcli_checksum_method_api_base@@Base+0x191df4>
│ │  	ands	r0, r0
│ │  	b.n	2fe4a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x191c1e>
│ │  	lsls	r2, r1, #28
│ │  	add.w	pc, r0, r6, asr #1
│ │ @@ -744879,15 +744879,15 @@
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	2fe50e <uniffi_pbcli_checksum_method_api_base@@Base+0x191c8a>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	2fe916 <uniffi_pbcli_checksum_method_api_base@@Base+0x192092>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r2, r5, r7, r8, r9, sl, fp, ip, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd85d71
│ │ +			@ <UNDEFINED> instruction: 0xffd85d98
│ │  			@ <UNDEFINED> instruction: 0xffda4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2fe704 <uniffi_pbcli_checksum_method_api_base@@Base+0x191e80>
│ │  	movs	r0, r0
│ │  	b.n	2fe88e <uniffi_pbcli_checksum_method_api_base@@Base+0x19200a>
│ │  	movs	r5, r1
│ │  	lsrs	r0, r0, #8
│ │ @@ -744997,15 +744997,15 @@
│ │  	ands	r0, r0
│ │  	b.n	2fea1e <uniffi_pbcli_checksum_method_api_base@@Base+0x19219a>
│ │  	str	r5, [r4, #52]	@ 0x34
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	2fe626 <uniffi_pbcli_checksum_method_api_base@@Base+0x191da2>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r1, r4, r5, r9, ip, sp, lr, pc}
│ │ -	vqrdmlah.s16	q9, q12, d4[0]
│ │ +	vqrdmlah.s16	q9, q12, d3[3]
│ │  			@ <UNDEFINED> instruction: 0xffda4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	2fe814 <uniffi_pbcli_checksum_method_api_base@@Base+0x191f90>
│ │  	beq.n	2fe31c <uniffi_pbcli_checksum_method_api_base@@Base+0x191a98>
│ │  	b.n	2fe798 <uniffi_pbcli_checksum_method_api_base@@Base+0x191f14>
│ │  	ands	r0, r0
│ │  	b.n	2fe642 <uniffi_pbcli_checksum_method_api_base@@Base+0x191dbe>
│ │ @@ -745708,20 +745708,20 @@
│ │  			@ <UNDEFINED> instruction: 0xeaffebfe
│ │  	vqshrn.u32	d26, q6, #8
│ │  	vshr.u64	<illegal reg q14.5>, q0, #40
│ │  			@ <UNDEFINED> instruction: 0xffd7ecf6
│ │  	vshll.u16	q13, d4, #8
│ │  			@ <UNDEFINED> instruction: 0xffd8ecbe
│ │  			@ <UNDEFINED> instruction: 0xffd8a9dc
│ │ -	vaddl.u16	q13, d8, d18
│ │ +	vmla.i16	q13, q4, d1[1]
│ │  	vmull.u16	q15, d25, d6
│ │  			@ <UNDEFINED> instruction: 0xffd8a9a4
│ │  	vqdmulh.s16	q15, q4, d6[1]
│ │  	vmul.f16	q13, q4, d4[3]
│ │ -			@ <UNDEFINED> instruction: 0xffd89fb2
│ │ +			@ <UNDEFINED> instruction: 0xffd89fd9
│ │  	vmlal.u16	q10, d9, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2fec9e <uniffi_pbcli_checksum_method_api_base@@Base+0x19241a>
│ │  	beq.n	2fe970 <uniffi_pbcli_checksum_method_api_base@@Base+0x1920ec>
│ │  	b.n	2fedfc <uniffi_pbcli_checksum_method_api_base@@Base+0x192578>
│ │  	movs	r0, #1
│ │  	b.n	2feca6 <uniffi_pbcli_checksum_method_api_base@@Base+0x192422>
│ │ @@ -745825,15 +745825,15 @@
│ │  	b.n	2fed82 <uniffi_pbcli_checksum_method_api_base@@Base+0x1924fe>
│ │  	beq.n	2fea64 <uniffi_pbcli_checksum_method_api_base@@Base+0x1921e0>
│ │  	b.n	2feedc <uniffi_pbcli_checksum_method_api_base@@Base+0x192658>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r6, r9, sl, fp, ip}
│ │  	movs	r0, r0
│ │  			@ <UNDEFINED> instruction: 0xeafaffd8
│ │ -	subs	r5, #83	@ 0x53
│ │ +	subs	r5, #122	@ 0x7a
│ │  	vmlal.u16	q10, d10, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2fed9e <uniffi_pbcli_checksum_method_api_base@@Base+0x19251a>
│ │  	asrs	r0, r0, #32
│ │  	b.n	2feda2 <uniffi_pbcli_checksum_method_api_base@@Base+0x19251e>
│ │  	movs	r0, r0
│ │  	b.n	2ff1a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x192922>
│ │ @@ -746973,28 +746973,28 @@
│ │  	b.n	2ff56c <uniffi_pbcli_checksum_method_api_base@@Base+0x192ce8>
│ │  	ldrsh	r4, [r1, r3]
│ │  			@ <UNDEFINED> instruction: 0xebff0006
│ │  	b.n	2ffb96 <uniffi_pbcli_checksum_method_api_base@@Base+0x193312>
│ │  	asrs	r6, r2, #2
│ │  	b.n	2ffb9a <uniffi_pbcli_checksum_method_api_base@@Base+0x193316>
│ │  			@ <UNDEFINED> instruction: 0xffd0eaff
│ │ -	ldr	r2, [r2, #20]
│ │ -	vmlal.u16	<illegal reg q9.5>, d25, d6[1]
│ │ +	ldr	r1, [r7, #20]
│ │ +	vrshr.u64	<illegal reg q9.5>, <illegal reg q10.5>, #39
│ │  	vmlal.u16	q15, d10, d6[0]
│ │ -	vrshr.u64	q11, <illegal reg q4.5>, #40
│ │ +	vsubw.u16	q11, q4, d0
│ │  	vmla.f16	q15, q5, d6[3]
│ │ -	vsubl.u16	q11, d8, d1
│ │ +	vsubl.u16	q11, d8, d24
│ │  	vmla.i16	q15, q13, d2[1]
│ │ -	vsra.u16	q11, <illegal reg q6.5>, #8
│ │ +	vaddw.u16	q11, q12, d4
│ │  	vaddw.u16	q15, q13, d10
│ │ -	vrshr.u16	d22, d13, #8
│ │ +	vmlal.u16	q11, d8, d4[0]
│ │  	vaddl.u16	q15, d26, d30
│ │ -	vmla.f16	q11, q4, d1[0]
│ │ +	vmla.f16	q11, q4, d0[3]
│ │  	vshr.u64	q15, q9, #38
│ │ -	vaddw.u16	q11, q12, d5
│ │ +	vaddw.u16	q11, q12, d28
│ │  			@ <UNDEFINED> instruction: 0xffda4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	2ff9b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x193134>
│ │  	beq.n	2ff4a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x192c24>
│ │  	b.n	2ff93c <uniffi_pbcli_checksum_method_api_base@@Base+0x1930b8>
│ │  	strb	r4, [r1, #0]
│ │  	b.n	2fefdc <uniffi_pbcli_checksum_method_api_base@@Base+0x192758>
│ │ @@ -747283,21 +747283,21 @@
│ │  	b.n	2ff258 <uniffi_pbcli_checksum_method_api_base@@Base+0x1929d4>
│ │  	movs	r0, r0
│ │  	b.n	2ff83c <uniffi_pbcli_checksum_method_api_base@@Base+0x192fb8>
│ │  	movs	r0, #2
│ │  	b.n	2ff840 <uniffi_pbcli_checksum_method_api_base@@Base+0x192fbc>
│ │  			@ <UNDEFINED> instruction: 0xffd8eaff
│ │  	ble.n	2ff6dc <uniffi_pbcli_checksum_method_api_base@@Base+0x192e58>
│ │ -			@ <UNDEFINED> instruction: 0xffd85e7d
│ │ +	vmull.p<illegal width 16>	<illegal reg q10.5>, d24, d20
│ │  			@ <UNDEFINED> instruction: 0xffdadef6
│ │ -			@ <UNDEFINED> instruction: 0xffd85f99
│ │ +	vqrdmlsh.s16	<illegal reg q10.5>, q12, d0[0]
│ │  			@ <UNDEFINED> instruction: 0xffdade72
│ │ -			@ <UNDEFINED> instruction: 0xffd85f15
│ │ +			@ <UNDEFINED> instruction: 0xffd85f3c
│ │  			@ <UNDEFINED> instruction: 0xffdade16
│ │ -			@ <UNDEFINED> instruction: 0xffd85eb9
│ │ +	vqrdmlah.s16	<illegal reg q10.5>, q12, d0[2]
│ │  	vmlal.u16	q10, d10, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2ffa8e <uniffi_pbcli_checksum_method_api_base@@Base+0x19320a>
│ │  	beq.n	2ff760 <uniffi_pbcli_checksum_method_api_base@@Base+0x192edc>
│ │  	b.n	2ffbec <uniffi_pbcli_checksum_method_api_base@@Base+0x193368>
│ │  	adds	r0, #1
│ │  	b.n	2ffa96 <uniffi_pbcli_checksum_method_api_base@@Base+0x193212>
│ │ @@ -747656,15 +747656,15 @@
│ │  	movs	r0, #0
│ │  	b.n	3001a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x193922>
│ │  	ldrb	r3, [r0, r6]
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	3001ae <uniffi_pbcli_checksum_method_api_base@@Base+0x19392a>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r1, r2, r5, r7, r9, fp, ip, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd8febf
│ │ +	vqrdmlah.s16	<illegal reg q15.5>, q12, d6[2]
│ │  	vqshrun.s32	d20, q8, #7
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	2fff9c <uniffi_pbcli_checksum_method_api_base@@Base+0x193718>
│ │  	ands	r1, r0
│ │  	b.n	2ffdc6 <uniffi_pbcli_checksum_method_api_base@@Base+0x193542>
│ │  	asrs	r4, r6, #1
│ │  	b.n	3001ca <uniffi_pbcli_checksum_method_api_base@@Base+0x193946>
│ │ @@ -747727,15 +747727,15 @@
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	2ffe52 <uniffi_pbcli_checksum_method_api_base@@Base+0x1935ce>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	30025a <uniffi_pbcli_checksum_method_api_base@@Base+0x1939d6>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r1, r2, r9, fp, ip, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd8fe1f
│ │ +	vqrdmlah.s16	<illegal reg q15.5>, q4, d6[0]
│ │  	vraddhn.i32	d17, <illegal reg q4.5>, q5
│ │  	b.n	30012a <uniffi_pbcli_checksum_method_api_base@@Base+0x1938a6>
│ │  			@ <UNDEFINED> instruction: 0xffffeaff
│ │  	ldr	r4, [pc, #448]	@ (2ffcf0 <uniffi_pbcli_checksum_method_api_base@@Base+0x19346c>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	300050 <uniffi_pbcli_checksum_method_api_base@@Base+0x1937cc>
│ │  	beq.n	2ffb48 <uniffi_pbcli_checksum_method_api_base@@Base+0x1932c4>
│ │ @@ -747805,15 +747805,15 @@
│ │  	b.n	30030a <uniffi_pbcli_checksum_method_api_base@@Base+0x193a86>
│ │  	movs	r4, r0
│ │  	b.n	2fff0e <uniffi_pbcli_checksum_method_api_base@@Base+0x19368a>
│ │  	beq.n	2ffbf0 <uniffi_pbcli_checksum_method_api_base@@Base+0x19336c>
│ │  	b.n	300068 <uniffi_pbcli_checksum_method_api_base@@Base+0x1937e4>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r1, r4, r6, r8, fp, ip, lr, pc}
│ │ -	vsli.64	<illegal reg q8.5>, <illegal reg q15.5>, #24
│ │ +	vrsubhn.i32	d17, q4, q11
│ │  	vraddhn.i32	d17, q5, <illegal reg q5.5>
│ │  	b.n	3001e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x19395e>
│ │  			@ <UNDEFINED> instruction: 0xffd1eaff
│ │  	asrs	r7, r7, #16
│ │  	b.n	3001ea <uniffi_pbcli_checksum_method_api_base@@Base+0x193966>
│ │  			@ <UNDEFINED> instruction: 0xffcfeaff
│ │  	adds	r1, r2, #4
│ │ @@ -747893,15 +747893,15 @@
│ │  	movs	r0, #0
│ │  	b.n	3003de <uniffi_pbcli_checksum_method_api_base@@Base+0x193b5a>
│ │  	ldrb	r5, [r6, r3]
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	3003e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x193b62>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r1, r2, r3, r5, r6, fp, ip, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd858d8
│ │ +			@ <UNDEFINED> instruction: 0xffd858ff
│ │  	vmlal.u16	q10, d10, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	2ffffa <uniffi_pbcli_checksum_method_api_base@@Base+0x193776>
│ │  	asrs	r0, r0, #32
│ │  	b.n	2ff7de <uniffi_pbcli_checksum_method_api_base@@Base+0x192f5a>
│ │  	movs	r4, r3
│ │  	b.n	300364 <uniffi_pbcli_checksum_method_api_base@@Base+0x193ae0>
│ │ @@ -747930,15 +747930,15 @@
│ │  	movs	r0, #0
│ │  	b.n	30043a <uniffi_pbcli_checksum_method_api_base@@Base+0x193bb6>
│ │  	ldrb	r6, [r3, r3]
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	300442 <uniffi_pbcli_checksum_method_api_base@@Base+0x193bbe>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r1, r4, fp, ip, lr, pc}
│ │ -	vqrshrun.s32	d21, q14, #8
│ │ +	vmlal.u16	<illegal reg q10.5>, d24, d19
│ │  			@ <UNDEFINED> instruction: 0xffda4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	300230 <uniffi_pbcli_checksum_method_api_base@@Base+0x1939ac>
│ │  	asrs	r0, r0, #32
│ │  	b.n	2ff83a <uniffi_pbcli_checksum_method_api_base@@Base+0x192fb6>
│ │  	movs	r4, r3
│ │  	b.n	3003c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x193b3c>
│ │ @@ -747981,15 +747981,15 @@
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	3000b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x193832>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3004be <uniffi_pbcli_checksum_method_api_base@@Base+0x193c3a>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r1, r5, r7, r8, r9, sl, ip, lr, pc}
│ │ -	vmlal.u16	<illegal reg q10.5>, d8, d12
│ │ +	vqshrun.s32	d21, <illegal reg q9.5>, #8
│ │  	vaddl.u16	q8, d10, d0
│ │  	b.n	2ff8ae <uniffi_pbcli_checksum_method_api_base@@Base+0x19302a>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (2ffdd4 <uniffi_pbcli_checksum_method_api_base@@Base+0x193550>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3002b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x193a30>
│ │  	beq.n	2ffdac <uniffi_pbcli_checksum_method_api_base@@Base+0x193528>
│ │ @@ -748245,18 +748245,18 @@
│ │  			@ <UNDEFINED> instruction: 0xffd9af9c
│ │  	movs	r2, r3
│ │  	bcs.n	3000b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x19382c>
│ │  			@ <UNDEFINED> instruction: 0xffd82f93
│ │  	vmls.f16	<illegal reg q14.5>, q12, d2[1]
│ │  	vsubl.u16	<illegal reg q12.5>, d8, d24
│ │  	vrsubhn.i32	d23, q12, <illegal reg q1.5>
│ │ -			@ <UNDEFINED> instruction: 0xffd83b32
│ │ +			@ <UNDEFINED> instruction: 0xffd83b59
│ │  	vrsra.u16	d19, d23, #6
│ │  			@ <UNDEFINED> instruction: 0xffd8ccba
│ │ -	vmls.i16	<illegal reg q10.5>, <illegal reg q11.5>, d2[3]
│ │ +	vsli.16	d21, d1, #7
│ │  			@ <UNDEFINED> instruction: 0xffda9361
│ │  	vaddw.u16	q12, q12, d3
│ │  	vqrdmlsh.s16	q8, <illegal reg q11.5>, d6[2]
│ │  	b.n	3006ae <uniffi_pbcli_checksum_method_api_base@@Base+0x193e2a>
│ │  	movs	r4, r1
│ │  	rev	r0, r0
│ │  	asrs	r6, r7, #16
│ │ @@ -748628,15 +748628,15 @@
│ │  	b.n	300692 <uniffi_pbcli_checksum_method_api_base@@Base+0x193e0e>
│ │  	beq.n	300384 <uniffi_pbcli_checksum_method_api_base@@Base+0x193b00>
│ │  	b.n	3007ec <uniffi_pbcli_checksum_method_api_base@@Base+0x193f68>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r0, r1, ip}
│ │  	b.n	30069e <uniffi_pbcli_checksum_method_api_base@@Base+0x193e1a>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │ -	strh	r4, [r7, #30]
│ │ +	strh	r3, [r4, #32]
│ │  			@ <UNDEFINED> instruction: 0xffd94df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	300888 <uniffi_pbcli_checksum_method_api_base@@Base+0x194004>
│ │  	beq.n	300390 <uniffi_pbcli_checksum_method_api_base@@Base+0x193b0c>
│ │  	b.n	30080c <uniffi_pbcli_checksum_method_api_base@@Base+0x193f88>
│ │  	strb	r3, [r0, #0]
│ │  	b.n	3006b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x193e32>
│ │ @@ -748745,15 +748745,15 @@
│ │  	movs	r0, r0
│ │  	b.n	300afe <uniffi_pbcli_checksum_method_api_base@@Base+0x19427a>
│ │  	asrs	r0, r0, #32
│ │  	bcc.n	3003a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x193b1e>
│ │  	movs	r1, r0
│ │  	b.n	3007a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x193f22>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r5, r6, r7, r9, fp, ip, lr}
│ │ +	ldmia.w	sp!, {r4, r8, r9, fp, ip, lr}
│ │  			@ <UNDEFINED> instruction: 0xffd94c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	300990 <uniffi_pbcli_checksum_method_api_base@@Base+0x19410c>
│ │  	beq.n	3004f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x193c74>
│ │  	b.n	300914 <uniffi_pbcli_checksum_method_api_base@@Base+0x194090>
│ │  	movs	r0, r0
│ │  	b.n	300b20 <uniffi_pbcli_checksum_method_api_base@@Base+0x19429c>
│ │ @@ -749008,17 +749008,17 @@
│ │  	b.n	3007cc <uniffi_pbcli_checksum_method_api_base@@Base+0x193f48>
│ │  	strb	r6, [r0, #8]
│ │  	add.w	r0, r0, r4
│ │  	b.n	3009f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x194172>
│ │  	beq.n	3006f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x193e6c>
│ │  	b.n	300b50 <uniffi_pbcli_checksum_method_api_base@@Base+0x1942cc>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r4, r7, r8, fp, ip, lr}
│ │ +	ldmia.w	sp!, {r3, r4, r5, r7, r8, fp, ip, lr}
│ │  			@ <UNDEFINED> instruction: 0xffd9cf12
│ │ -			@ <UNDEFINED> instruction: 0xffd858f5
│ │ +	vqshrn.u32	d21, q6, #8
│ │  	vqrdmlah.s16	q14, <illegal reg q4.5>, d2[1]
│ │  			@ <UNDEFINED> instruction: 0xffd84c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	300bf0 <uniffi_pbcli_checksum_method_api_base@@Base+0x19436c>
│ │  	asrs	r0, r7, #3
│ │  	b.n	300218 <uniffi_pbcli_checksum_method_api_base@@Base+0x193994>
│ │  	lsls	r0, r3, #1
│ │ @@ -749213,15 +749213,15 @@
│ │  	and.w	r0, r0, r0, lsl #20
│ │  	b.n	3003a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x193b1e>
│ │  	ldrh	r5, [r0, r2]
│ │  			@ <UNDEFINED> instruction: 0xebffd010
│ │  	b.n	300d38 <uniffi_pbcli_checksum_method_api_base@@Base+0x1944b4>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r1, r2, r3, r4, r5, r6, sl, fp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd84d21
│ │ +	vqrdmulh.s16	q10, q4, d0[1]
│ │  	vshr.u16	d16, d12, #6
│ │  	b.n	300db2 <uniffi_pbcli_checksum_method_api_base@@Base+0x19452e>
│ │  	subs	r7, r3, #6
│ │  	b.n	300bd6 <uniffi_pbcli_checksum_method_api_base@@Base+0x194352>
│ │  	movs	r0, #1
│ │  	b.n	300dbc <uniffi_pbcli_checksum_method_api_base@@Base+0x194538>
│ │  	subs	r7, #146	@ 0x92
│ │ @@ -749607,15 +749607,15 @@
│ │  	ands	r0, r0
│ │  	b.n	301366 <uniffi_pbcli_checksum_method_api_base@@Base+0x194ae2>
│ │  	ldr	r3, [r2, r4]
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	300f6e <uniffi_pbcli_checksum_method_api_base@@Base+0x1946ea>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r1, r3, r5, r6, r7, fp, lr, pc}
│ │ -	vmul.f16	q10, q4, d1[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd84990
│ │  			@ <UNDEFINED> instruction: 0xffda48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	30115c <uniffi_pbcli_checksum_method_api_base@@Base+0x1948d8>
│ │  	beq.n	300cc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x194440>
│ │  	b.n	3010e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x19485c>
│ │  	ands	r0, r0
│ │  	b.n	30138a <uniffi_pbcli_checksum_method_api_base@@Base+0x194b06>
│ │ @@ -750351,15 +750351,15 @@
│ │  	b.n	301606 <uniffi_pbcli_checksum_method_api_base@@Base+0x194d82>
│ │  	beq.n	3012f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x194a74>
│ │  	b.n	301760 <uniffi_pbcli_checksum_method_api_base@@Base+0x194edc>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r2, r3, r9, sl, fp, ip, pc}
│ │  	movs	r2, r3
│ │  	ldr	r3, [r7, #0]
│ │ -	vaddw.u16	<illegal reg q14.5>, q12, d1
│ │ +	vaddw.u16	<illegal reg q14.5>, q12, d24
│ │  	vsra.u16	d16, d8, #7
│ │  	movs	r0, r0
│ │  	str	r7, [r7, #120]	@ 0x78
│ │  			@ <UNDEFINED> instruction: 0xffd84ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	301804 <uniffi_pbcli_checksum_method_api_base@@Base+0x194f80>
│ │  	beq.n	301334 <uniffi_pbcli_checksum_method_api_base@@Base+0x194ab0>
│ │ @@ -751296,31 +751296,31 @@
│ │  	vmls.i16	<illegal reg q14.5>, q12, d3[3]
│ │  	vrsra.u64	d22, d15, #40
│ │  			@ <UNDEFINED> instruction: 0xffd89348
│ │  	vsra.u64	q11, <illegal reg q7.5>, #40
│ │  			@ <UNDEFINED> instruction: 0xffd85fdb
│ │  	vaddl.u16	q11, d8, d15
│ │  			@ <UNDEFINED> instruction: 0xffd88fb8
│ │ -			@ <UNDEFINED> instruction: 0xffd83b2b
│ │ +			@ <UNDEFINED> instruction: 0xffd83b52
│ │  	vsri.16	d22, d3, #6
│ │  	vrsra.u64	d25, d28, #40
│ │  			@ <UNDEFINED> instruction: 0xffd8aadb
│ │  	vrshr.u64	q11, <illegal reg q13.5>, #40
│ │  	vsubl.u16	<illegal reg q12.5>, d24, d20
│ │  			@ <UNDEFINED> instruction: 0xffd8eb57
│ │  	vmls.i16	q11, q12, d3[3]
│ │  	vsri.64	d25, d4, #40
│ │  	vsubl.u16	q11, d24, d15
│ │  	vrshr.u16	d25, d24, #8
│ │ -			@ <UNDEFINED> instruction: 0xffd8f9b1
│ │ +			@ <UNDEFINED> instruction: 0xffd8f9d8
│ │  			@ <UNDEFINED> instruction: 0xffd95fb7
│ │  	vqrdmlsh.s16	q12, q4, d0[2]
│ │  	vshr.u64	d22, d27, #40
│ │  	vmla.i16	<illegal reg q12.5>, q4, d4[2]
│ │ -	vqshrun.s32	d31, <illegal reg q3.5>, #8
│ │ +	vqshrun.s32	d31, q15, #8
│ │  			@ <UNDEFINED> instruction: 0xffd94ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	302080 <uniffi_pbcli_checksum_method_api_base@@Base+0x1957fc>
│ │  	beq.n	301ae0 <uniffi_pbcli_checksum_method_api_base@@Base+0x19525c>
│ │  	b.n	302004 <uniffi_pbcli_checksum_method_api_base@@Base+0x195780>
│ │  	lsls	r0, r2, #1
│ │  	blt.w	301b6e <uniffi_pbcli_checksum_method_api_base@@Base+0x1952ea>
│ │ @@ -752305,15 +752305,15 @@
│ │  	movs	r0, r0
│ │  	b.n	302b3e <uniffi_pbcli_checksum_method_api_base@@Base+0x1962ba>
│ │  	movs	r4, r2
│ │  	b.n	301f0a <uniffi_pbcli_checksum_method_api_base@@Base+0x195686>
│ │  	movs	r7, r0
│ │  	b.n	302746 <uniffi_pbcli_checksum_method_api_base@@Base+0x195ec2>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r2, r4, r6, r8, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r5, r6, r8, ip, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd94df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	302930 <uniffi_pbcli_checksum_method_api_base@@Base+0x1960ac>
│ │  	ands	r2, r0
│ │  	b.n	30275a <uniffi_pbcli_checksum_method_api_base@@Base+0x195ed6>
│ │  	strb	r1, [r0, #0]
│ │  	b.n	30275e <uniffi_pbcli_checksum_method_api_base@@Base+0x195eda>
│ │ @@ -752475,15 +752475,15 @@
│ │  	strb	r0, [r0, #0]
│ │  	b.n	302cba <uniffi_pbcli_checksum_method_api_base@@Base+0x196436>
│ │  	strh	r6, [r7, r2]
│ │  			@ <UNDEFINED> instruction: 0xebff0007
│ │  	b.n	3028c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x19603e>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r1, r3, r4, r8, sl, ip, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffd8d3e4
│ │ +	vraddhn.i32	d29, q4, <illegal reg q5.5>
│ │  			@ <UNDEFINED> instruction: 0xffd948f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	302ab0 <uniffi_pbcli_checksum_method_api_base@@Base+0x19622c>
│ │  	ands	r2, r0
│ │  	b.n	3028da <uniffi_pbcli_checksum_method_api_base@@Base+0x196056>
│ │  	str	r1, [r0, r0]
│ │  	b.n	3028de <uniffi_pbcli_checksum_method_api_base@@Base+0x19605a>
│ │ @@ -752588,17 +752588,17 @@
│ │  	strb	r0, [r0, #0]
│ │  	b.n	302dc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x19653e>
│ │  	strh	r4, [r7, r1]
│ │  			@ <UNDEFINED> instruction: 0xebff0007
│ │  	b.n	3029ca <uniffi_pbcli_checksum_method_api_base@@Base+0x196146>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6, sl, ip, lr}
│ │ -	vrsra.u16	<illegal reg q14.5>, <illegal reg q6.5>, #8
│ │ +	vsubw.u16	<illegal reg q14.5>, q12, d4
│ │  	vsri.16	d21, d3, #7
│ │ -	vrshr.u64	<illegal reg q14.5>, <illegal reg q8.5>, #40
│ │ +	vrsra.u16	d29, d8, #8
│ │  			@ <UNDEFINED> instruction: 0xffd948f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	302bc0 <uniffi_pbcli_checksum_method_api_base@@Base+0x19633c>
│ │  	ands	r2, r0
│ │  	b.n	3029ea <uniffi_pbcli_checksum_method_api_base@@Base+0x196166>
│ │  	str	r1, [r0, r0]
│ │  	b.n	3029ee <uniffi_pbcli_checksum_method_api_base@@Base+0x19616a>
│ │ @@ -752812,17 +752812,17 @@
│ │  	movs	r0, r0
│ │  	b.n	302fc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x19673e>
│ │  	movs	r0, r3
│ │  	b.n	30238e <uniffi_pbcli_checksum_method_api_base@@Base+0x195b0a>
│ │  	movs	r5, r0
│ │  	b.n	302bca <uniffi_pbcli_checksum_method_api_base@@Base+0x196346>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r3, r5, r8, sl, ip, sp}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r6, r8, sl, ip, sp}
│ │  			@ <UNDEFINED> instruction: 0xffd973c9
│ │ -	vabal.u16	<illegal reg q9.5>, d23, d16
│ │ +	vmls.f16	<illegal reg q9.5>, <illegal reg q11.5>, d7[0]
│ │  	vrsra.u16	<illegal reg q11.5>, <illegal reg q12.5>, #7
│ │  	vrshr.u16	<illegal reg q10.5>, <illegal reg q5.5>, #9
│ │  	vrsra.u64	d28, d9, #40
│ │  			@ <UNDEFINED> instruction: 0xffd848f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	302dc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x196544>
│ │  	beq.n	3028c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x19603c>
│ │ @@ -753430,25 +753430,25 @@
│ │  	ldmia.w	sp!, {r0, r1, r3, r6, r7, r9, sl, fp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffd8ef50
│ │  			@ <UNDEFINED> instruction: 0xffd78e7c
│ │  			@ <UNDEFINED> instruction: 0xffd74cf3
│ │  			@ <UNDEFINED> instruction: 0xffd8ed78
│ │  	vaddw.u16	<illegal reg q12.5>, <illegal reg q3.5>, d24
│ │  	movs	r2, r3
│ │ -	ldr	r0, [pc, #296]	@ (302f20 <uniffi_pbcli_checksum_method_api_base@@Base+0x19669c>)
│ │ +	ldr	r0, [pc, #452]	@ (302fbc <uniffi_pbcli_checksum_method_api_base@@Base+0x196738>)
│ │  	vmull.u16	q15, d9, d11
│ │ -	vmul.i16	q12, <illegal reg q3.5>, d2[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd78891
│ │  			@ <UNDEFINED> instruction: 0xffd97db4
│ │ -	vrshr.u16	<illegal reg q8.5>, <illegal reg q14.5>, #8
│ │ -	vmlal.u16	<illegal reg q8.5>, d10, d2[3]
│ │ +	vsubl.u16	<illegal reg q8.5>, d24, d20
│ │ +	vrshr.u64	d17, d1, #38
│ │  			@ <UNDEFINED> instruction: 0xffda8f74
│ │  	movs	r2, r3
│ │  	ldr	r5, [pc, #444]	@ (302fd0 <uniffi_pbcli_checksum_method_api_base@@Base+0x19674c>)
│ │  			@ <UNDEFINED> instruction: 0xffd8edf4
│ │ -			@ <UNDEFINED> instruction: 0xffd75b54
│ │ +			@ <UNDEFINED> instruction: 0xffd75b7b
│ │  			@ <UNDEFINED> instruction: 0xffd948f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	303340 <uniffi_pbcli_checksum_method_api_base@@Base+0x196abc>
│ │  	ands	r2, r0
│ │  	b.n	30316a <uniffi_pbcli_checksum_method_api_base@@Base+0x1968e6>
│ │  	strb	r1, [r0, #0]
│ │  	b.n	30316e <uniffi_pbcli_checksum_method_api_base@@Base+0x1968ea>
│ │ @@ -753797,16 +753797,16 @@
│ │  	movs	r2, r0
│ │  	b.n	3037cc <uniffi_pbcli_checksum_method_api_base@@Base+0x196f48>
│ │  			@ <UNDEFINED> instruction: 0xfff41aff
│ │  			@ <UNDEFINED> instruction: 0xfff7eaff
│ │  	ldrh	r4, [r0, #42]	@ 0x2a
│ │  	movs	r2, r3
│ │  	str	r0, [r6, #24]
│ │ -			@ <UNDEFINED> instruction: 0xffd82e5d
│ │ -	vmlal.u16	q14, d25, d20
│ │ +	vmull.p<illegal width 16>	q9, d24, d4
│ │ +	vmul.i16	q14, <illegal reg q12.5>, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffd98c7c
│ │  	movs	r2, r3
│ │  	ldr	r0, [pc, #960]	@ (303500 <uniffi_pbcli_checksum_method_api_base@@Base+0x196c7c>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	303660 <uniffi_pbcli_checksum_method_api_base@@Base+0x196ddc>
│ │  	ands	r2, r0
│ │  	b.n	30348a <uniffi_pbcli_checksum_method_api_base@@Base+0x196c06>
│ │ @@ -753939,15 +753939,15 @@
│ │  	movs	r0, r0
│ │  	b.n	30399e <uniffi_pbcli_checksum_method_api_base@@Base+0x19711a>
│ │  	movs	r4, r2
│ │  	b.n	302d6a <uniffi_pbcli_checksum_method_api_base@@Base+0x1964e6>
│ │  	movs	r7, r0
│ │  	b.n	3035a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x196d22>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r2, r4, r5, r6, r7, r9, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r8, r9, lr, pc}
│ │  	vqshrun.s32	d20, q8, #7
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	303790 <uniffi_pbcli_checksum_method_api_base@@Base+0x196f0c>
│ │  	beq.n	303288 <uniffi_pbcli_checksum_method_api_base@@Base+0x196a04>
│ │  	b.n	303714 <uniffi_pbcli_checksum_method_api_base@@Base+0x196e90>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3039be <uniffi_pbcli_checksum_method_api_base@@Base+0x19713a>
│ │ @@ -754414,15 +754414,15 @@
│ │  	movs	r0, #0
│ │  	b.n	303dd2 <uniffi_pbcli_checksum_method_api_base@@Base+0x19754e>
│ │  	ldr	r6, [pc, #480]	@ (303874 <uniffi_pbcli_checksum_method_api_base@@Base+0x196ff0>)
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	303dda <uniffi_pbcli_checksum_method_api_base@@Base+0x197556>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, lr}
│ │ -	vmull.p<illegal width 16>	<illegal reg q9.5>, d8, d28
│ │ +			@ <UNDEFINED> instruction: 0xffd83e53
│ │  			@ <UNDEFINED> instruction: 0xffd94ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	303bc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x197344>
│ │  	beq.n	3036c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x196e44>
│ │  	b.n	303b4c <uniffi_pbcli_checksum_method_api_base@@Base+0x1972c8>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3031da <uniffi_pbcli_checksum_method_api_base@@Base+0x196956>
│ │ @@ -754605,15 +754605,15 @@
│ │  	str	r1, [r4, #88]	@ 0x58
│ │  	add.w	r0, r0, r7
│ │  	b.n	303b8a <uniffi_pbcli_checksum_method_api_base@@Base+0x197306>
│ │  	beq.n	303884 <uniffi_pbcli_checksum_method_api_base@@Base+0x197000>
│ │  	b.n	303ce4 <uniffi_pbcli_checksum_method_api_base@@Base+0x197460>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r7, r9, lr}
│ │ -	vmlsl.u16	q11, d8, d0[2]
│ │ +	vrsubhn.i32	d22, q12, <illegal reg q3.5>
│ │  	vrshr.u16	d20, d27, #7
│ │  			@ <UNDEFINED> instruction: 0xffd84ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	303d80 <uniffi_pbcli_checksum_method_api_base@@Base+0x1974fc>
│ │  	beq.n	303880 <uniffi_pbcli_checksum_method_api_base@@Base+0x196ffc>
│ │  	b.n	303d04 <uniffi_pbcli_checksum_method_api_base@@Base+0x197480>
│ │  	strh	r0, [r0, #0]
│ │ @@ -754765,16 +754765,16 @@
│ │  			@ <UNDEFINED> instruction: 0xebff0005
│ │  	b.n	303cf2 <uniffi_pbcli_checksum_method_api_base@@Base+0x19746e>
│ │  	beq.n	3039ec <uniffi_pbcli_checksum_method_api_base@@Base+0x197168>
│ │  	b.n	303e4c <uniffi_pbcli_checksum_method_api_base@@Base+0x1975c8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r1, r3, r5, r6, r7, lr}
│ │  	vqshrun.s32	d24, q4, #8
│ │ -			@ <UNDEFINED> instruction: 0xffd8ee5f
│ │ -	vsli.64	q8, q15, #25
│ │ +	vmull.p<illegal width 16>	q15, d24, d6
│ │ +	vrsubhn.i32	d16, <illegal reg q4.5>, <illegal reg q10.5>
│ │  			@ <UNDEFINED> instruction: 0xffda48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	303eec <uniffi_pbcli_checksum_method_api_base@@Base+0x197668>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3034fa <uniffi_pbcli_checksum_method_api_base@@Base+0x196c76>
│ │  	str	r0, [r0, #0]
│ │  	b.n	303d1a <uniffi_pbcli_checksum_method_api_base@@Base+0x197496>
│ │ @@ -757559,20 +757559,20 @@
│ │  			@ <UNDEFINED> instruction: 0xffeaeaff
│ │  	movs	r1, r0
│ │  	b.n	305986 <uniffi_pbcli_checksum_method_api_base@@Base+0x199102>
│ │  			@ <UNDEFINED> instruction: 0xffe8eaff
│ │  	movs	r2, r0
│ │  	b.n	30598e <uniffi_pbcli_checksum_method_api_base@@Base+0x19910a>
│ │  			@ <UNDEFINED> instruction: 0xffe6eaff
│ │ -	adds	r4, #248	@ 0xf8
│ │ +	adds	r5, #31
│ │  	vsubl.u16	<illegal reg q11.5>, d9, d4
│ │  	movs	r2, r3
│ │ -	subs	r4, r6, #6
│ │ -	vsri.16	d16, d4, #7
│ │ -			@ <UNDEFINED> instruction: 0xffda7b14
│ │ +	subs	r3, r3, #7
│ │ +	vsri.16	d16, d27, #7
│ │ +			@ <UNDEFINED> instruction: 0xffda7b3b
│ │  			@ <UNDEFINED> instruction: 0xffd94ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	305788 <uniffi_pbcli_checksum_method_api_base@@Base+0x198f04>
│ │  	beq.n	305308 <uniffi_pbcli_checksum_method_api_base@@Base+0x198a84>
│ │  	b.n	30570c <uniffi_pbcli_checksum_method_api_base@@Base+0x198e88>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	3059b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x199132>
│ │ @@ -757736,15 +757736,15 @@
│ │  	b.n	305b16 <uniffi_pbcli_checksum_method_api_base@@Base+0x199292>
│ │  	bx	r4
│ │  			@ <UNDEFINED> instruction: 0xebffffee
│ │  			@ <UNDEFINED> instruction: 0xeaff7000
│ │  	b.n	305b22 <uniffi_pbcli_checksum_method_api_base@@Base+0x19929e>
│ │  			@ <UNDEFINED> instruction: 0xffeceaff
│ │  	svc	82	@ 0x52
│ │ -	vmull.p<illegal width 16>	<illegal reg q13.5>, d23, d10
│ │ +			@ <UNDEFINED> instruction: 0xffd7beb1
│ │  			@ <UNDEFINED> instruction: 0xffd94ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	305910 <uniffi_pbcli_checksum_method_api_base@@Base+0x19908c>
│ │  	beq.n	305390 <uniffi_pbcli_checksum_method_api_base@@Base+0x198b0c>
│ │  	b.n	305894 <uniffi_pbcli_checksum_method_api_base@@Base+0x199010>
│ │  	strb	r0, [r2, #0]
│ │  	b.n	305914 <uniffi_pbcli_checksum_method_api_base@@Base+0x199090>
│ │ @@ -758006,22 +758006,22 @@
│ │  	movs	r4, r0
│ │  	b.n	30597e <uniffi_pbcli_checksum_method_api_base@@Base+0x1990fa>
│ │  	beq.n	305678 <uniffi_pbcli_checksum_method_api_base@@Base+0x198df4>
│ │  	b.n	305ad8 <uniffi_pbcli_checksum_method_api_base@@Base+0x199254>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r1, r2, r6, r7, r8, r9, fp, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffd8aeb3
│ │ -	vshr.u16	q13, q3, #9
│ │ -	vmlsl.u16	q8, d25, d6
│ │ +	vshr.u16	q13, <illegal reg q14.5>, #9
│ │ +	vmlsl.u16	q8, d25, d29
│ │  	vabal.u16	<illegal reg q15.5>, d25, d24
│ │  	vqshlu.s64	q10, <illegal reg q11.5>, #23
│ │  			@ <UNDEFINED> instruction: 0xffd7dd2d
│ │  	vmla.i16	<illegal reg q15.5>, q4, d7[3]
│ │  			@ <UNDEFINED> instruction: 0xffd8eda4
│ │ -	vrsra.u64	d26, d19, #40
│ │ +	vrsra.u64	q13, q5, #40
│ │  	vaddl.u16	<illegal reg q8.5>, d9, d0
│ │  	b.n	305db2 <uniffi_pbcli_checksum_method_api_base@@Base+0x19952e>
│ │  			@ <UNDEFINED> instruction: 0xffffeaff
│ │  	ldr	r4, [pc, #448]	@ (305838 <uniffi_pbcli_checksum_method_api_base@@Base+0x198fb4>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	305b98 <uniffi_pbcli_checksum_method_api_base@@Base+0x199314>
│ │  	eors	r0, r1
│ │ @@ -758849,15 +758849,15 @@
│ │  	and.w	r0, r0, r1, lsl #20
│ │  	b.n	306516 <uniffi_pbcli_checksum_method_api_base@@Base+0x199c92>
│ │  	movs	r5, r0
│ │  	b.n	30611a <uniffi_pbcli_checksum_method_api_base@@Base+0x199896>
│ │  	beq.n	305dfc <uniffi_pbcli_checksum_method_api_base@@Base+0x199578>
│ │  	b.n	306274 <uniffi_pbcli_checksum_method_api_base@@Base+0x1999f0>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r6, r7, sl, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r8, sl, ip, sp, pc}
│ │  	vabal.u16	<illegal reg q9.5>, d9, d27
│ │  	vmlal.u16	q10, d8, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	306132 <uniffi_pbcli_checksum_method_api_base@@Base+0x1998ae>
│ │  	movs	r0, #0
│ │  	b.n	305916 <uniffi_pbcli_checksum_method_api_base@@Base+0x199092>
│ │  	movs	r2, r0
│ │ @@ -759090,15 +759090,15 @@
│ │  	movs	r0, #0
│ │  	b.n	30674e <uniffi_pbcli_checksum_method_api_base@@Base+0x199eca>
│ │  	add	r1, r3
│ │  			@ <UNDEFINED> instruction: 0xebff0001
│ │  	b.n	3067d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x199f52>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r1, r4, r5, r8, r9, fp, ip, sp, pc}
│ │ -	vqrdmulh.s16	q11, <illegal reg q3.5>, d6[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd76d75
│ │  			@ <UNDEFINED> instruction: 0xffd94bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	306544 <uniffi_pbcli_checksum_method_api_base@@Base+0x199cc0>
│ │  	movs	r0, r0
│ │  	b.n	3066ce <uniffi_pbcli_checksum_method_api_base@@Base+0x199e4a>
│ │  	str	r0, [r0, #0]
│ │  	asrs	r0, r4, #6
│ │ @@ -760564,15 +760564,15 @@
│ │  	mcr2	11, 6, lr, cr13, cr15, {7}	@ <UNPREDICTABLE>
│ │  	movs	r5, r0
│ │  	b.n	30704a <uniffi_pbcli_checksum_method_api_base@@Base+0x19a7c6>
│ │  	beq.n	306d2c <uniffi_pbcli_checksum_method_api_base@@Base+0x19a4a8>
│ │  	b.n	3071a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x19a920>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r2, r3, r5, r6, r7, r9, sl, ip, sp}
│ │ -	vmls.i16	<illegal reg q15.5>, <illegal reg q3.5>, d5[3]
│ │ +	vsri.64	d31, d4, #41
│ │  	vqshl.u64	<illegal reg q9.5>, q6, #24
│ │  	vabdl.u16	<illegal reg q9.5>, d23, d4
│ │  	vshr.u16	d16, d4, #9
│ │  	b.n	306864 <uniffi_pbcli_checksum_method_api_base@@Base+0x199fe0>
│ │  	movs	r0, r0
│ │  	b.n	306c68 <uniffi_pbcli_checksum_method_api_base@@Base+0x19a3e4>
│ │  	movs	r0, r0
│ │ @@ -761418,15 +761418,15 @@
│ │  	ands	r4, r0
│ │  	b.n	306f9c <uniffi_pbcli_checksum_method_api_base@@Base+0x19a718>
│ │  	lsls	r5, r3, #7
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	307920 <uniffi_pbcli_checksum_method_api_base@@Base+0x19b09c>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r2, r4, r7, r8, sl, fp, sp}
│ │ -			@ <UNDEFINED> instruction: 0xffd79e55
│ │ +			@ <UNDEFINED> instruction: 0xffd79e7c
│ │  	vmull.p<illegal width 16>	q8, d25, d4
│ │  			@ <UNDEFINED> instruction: 0xffd72d54
│ │  	vmlsl.u16	q8, d7, d3[2]
│ │  			@ <UNDEFINED> instruction: 0xffd84ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3079c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x19b140>
│ │  	beq.n	3074c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x19ac40>
│ │ @@ -761690,16 +761690,16 @@
│ │  	asrs	r5, r0, #32
│ │  	b.n	307a42 <uniffi_pbcli_checksum_method_api_base@@Base+0x19b1be>
│ │  	ldc2	11, cr14, [pc, #1020]	@ 307b00 <uniffi_pbcli_checksum_method_api_base@@Base+0x19b27c>	@ <UNPREDICTABLE>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	307a4a <uniffi_pbcli_checksum_method_api_base@@Base+0x19b1c6>
│ │  			@ <UNDEFINED> instruction: 0xffd1eaff
│ │  	cmp	r3, #100	@ 0x64
│ │ -	vmlal.u16	q9, d7, d27
│ │ -	vqrdmulh.s16	<illegal reg q11.5>, <illegal reg q12.5>, d6[3]
│ │ +	vqrshrun.s32	d18, q1, #9
│ │ +			@ <UNDEFINED> instruction: 0xffd97e15
│ │  			@ <UNDEFINED> instruction: 0xffd90b4c
│ │  			@ <UNDEFINED> instruction: 0xffd74bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	307c40 <uniffi_pbcli_checksum_method_api_base@@Base+0x19b3bc>
│ │  	beq.n	3077c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x19af44>
│ │  	b.n	307bc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x19b340>
│ │  	movs	r0, r0
│ │ @@ -761883,15 +761883,15 @@
│ │  	b.n	307c0e <uniffi_pbcli_checksum_method_api_base@@Base+0x19b38a>
│ │  	adds	r0, #4
│ │  	b.n	308012 <uniffi_pbcli_checksum_method_api_base@@Base+0x19b78e>
│ │  			@ <UNDEFINED> instruction: 0xff91ebff
│ │  	beq.n	3078ee <uniffi_pbcli_checksum_method_api_base@@Base+0x19b06a>
│ │  	b.n	307c1a <uniffi_pbcli_checksum_method_api_base@@Base+0x19b396>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r6, sl, fp, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r7, sl, fp, sp, pc}
│ │  	vmlal.u16	q10, d9, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	307c2a <uniffi_pbcli_checksum_method_api_base@@Base+0x19b3a6>
│ │  	beq.n	3078fc <uniffi_pbcli_checksum_method_api_base@@Base+0x19b078>
│ │  	b.n	307d88 <uniffi_pbcli_checksum_method_api_base@@Base+0x19b504>
│ │  	movs	r0, #0
│ │  	b.n	30740c <uniffi_pbcli_checksum_method_api_base@@Base+0x19ab88>
│ │ @@ -763482,17 +763482,17 @@
│ │  	subs	r7, #114	@ 0x72
│ │  	b.n	308e42 <uniffi_pbcli_checksum_method_api_base@@Base+0x19c5be>
│ │  	movs	r0, #2
│ │  	b.n	308824 <uniffi_pbcli_checksum_method_api_base@@Base+0x19bfa0>
│ │  	strh	r4, [r1, r2]
│ │  			@ <UNDEFINED> instruction: 0xeb00ff9b
│ │  			@ <UNDEFINED> instruction: 0xeaff03fe
│ │ -	vmul.f16	<illegal reg q14.5>, <illegal reg q11.5>, d6[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd7d9f5
│ │  	vrsra.u16	q8, q7, #8
│ │ -			@ <UNDEFINED> instruction: 0xffd7d92e
│ │ +	vqrshrn.u32	d29, <illegal reg q2.5>, #9
│ │  	vsubw.u16	q8, q4, d14
│ │  	vrshr.u16	q8, q5, #9
│ │  			@ <UNDEFINED> instruction: 0xffd748f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	308c48 <uniffi_pbcli_checksum_method_api_base@@Base+0x19c3c4>
│ │  	str	r2, [r0, r0]
│ │  	b.n	308a72 <uniffi_pbcli_checksum_method_api_base@@Base+0x19c1ee>
│ │ @@ -763897,20 +763897,20 @@
│ │  	add.w	r0, r6, r0, lsl #4
│ │  	b.n	308e06 <uniffi_pbcli_checksum_method_api_base@@Base+0x19c582>
│ │  	movs	r4, r0
│ │  	b.n	308e0a <uniffi_pbcli_checksum_method_api_base@@Base+0x19c586>
│ │  	ldr	r4, [pc, #448]	@ (308c8c <uniffi_pbcli_checksum_method_api_base@@Base+0x19c408>)
│ │  	ldmia.w	sp!, {r2, r3, r4, r5, r8, r9, lr}
│ │  			@ <UNDEFINED> instruction: 0xeaff30f3
│ │ -			@ <UNDEFINED> instruction: 0xffd7eb47
│ │ +			@ <UNDEFINED> instruction: 0xffd7eb6e
│ │  	vshr.u16	d25, d7, #8
│ │  	vqrdmlah.s16	<illegal reg q15.5>, q12, d6[0]
│ │ -	vraddhn.i32	d29, q11, <illegal reg q10.5>
│ │ +	vmls.i16	<illegal reg q14.5>, q11, d4[1]
│ │  	vmla.f16	<illegal reg q12.5>, q4, d0[1]
│ │ -			@ <UNDEFINED> instruction: 0xffd78891
│ │ +			@ <UNDEFINED> instruction: 0xffd788b8
│ │  	vmla.i16	<illegal reg q9.5>, <illegal reg q4.5>, d6[2]
│ │  	vmla.i16	q9, <illegal reg q3.5>, d7[3]
│ │  			@ <UNDEFINED> instruction: 0xffd84ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	309018 <uniffi_pbcli_checksum_method_api_base@@Base+0x19c794>
│ │  	beq.n	308a08 <uniffi_pbcli_checksum_method_api_base@@Base+0x19c184>
│ │  	b.n	308f9c <uniffi_pbcli_checksum_method_api_base@@Base+0x19c718>
│ │ @@ -764075,15 +764075,15 @@
│ │  	b.n	308faa <uniffi_pbcli_checksum_method_api_base@@Base+0x19c726>
│ │  	pop	{r1, r4, r7}
│ │  			@ <UNDEFINED> instruction: 0xebff0007
│ │  	b.n	308fb2 <uniffi_pbcli_checksum_method_api_base@@Base+0x19c72e>
│ │  	beq.n	308cac <uniffi_pbcli_checksum_method_api_base@@Base+0x19c428>
│ │  	b.n	30910c <uniffi_pbcli_checksum_method_api_base@@Base+0x19c888>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r5, r6, r7, r9, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r8, r9, fp, lr, pc}
│ │  	vrsubhn.i32	d31, <illegal reg q12.5>, q14
│ │  			@ <UNDEFINED> instruction: 0xffd689aa
│ │  	vqdmulh.s16	<illegal reg q13.5>, <illegal reg q3.5>, d1[2]
│ │  			@ <UNDEFINED> instruction: 0xffd88d80
│ │  			@ <UNDEFINED> instruction: 0xffd84ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3091b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x19c92c>
│ │ @@ -764962,15 +764962,15 @@
│ │  	b.n	309b92 <uniffi_pbcli_checksum_method_api_base@@Base+0x19d30e>
│ │  	str	r0, [r0, #0]
│ │  	b.n	309b96 <uniffi_pbcli_checksum_method_api_base@@Base+0x19d312>
│ │  	adds	r7, #7
│ │  			@ <UNDEFINED> instruction: 0xebff0006
│ │  	b.n	30979e <uniffi_pbcli_checksum_method_api_base@@Base+0x19cf1a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r2, r4, r6, ip, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r4, r5, r6, ip, lr}
│ │  	vshr.u64	<illegal reg q11.5>, q15, #39
│ │  			@ <UNDEFINED> instruction: 0xffd75982
│ │  	vrsra.u64	<illegal reg q13.5>, <illegal reg q10.5>, #41
│ │  	vqshlu.s16	<illegal reg q13.5>, q6, #8
│ │  			@ <UNDEFINED> instruction: 0xffd74c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	309998 <uniffi_pbcli_checksum_method_api_base@@Base+0x19d114>
│ │ @@ -765053,15 +765053,15 @@
│ │  	asrs	r5, r0, #32
│ │  	b.n	30986a <uniffi_pbcli_checksum_method_api_base@@Base+0x19cfe6>
│ │  	bfcsel	18, 308d2a <uniffi_pbcli_checksum_method_api_base@@Base+0x19c4a6>, 1a, pl
│ │  	beq.n	309550 <uniffi_pbcli_checksum_method_api_base@@Base+0x19cccc>
│ │  	b.n	3099c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x19d144>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r1, r2, r6, r7, r9, sl, fp, lr, pc}
│ │ -	vmlsl.u16	q14, d23, d18
│ │ +	vmull.u16	q14, d23, d1[1]
│ │  			@ <UNDEFINED> instruction: 0xffd8fc3d
│ │  			@ <UNDEFINED> instruction: 0xffd74c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	309a64 <uniffi_pbcli_checksum_method_api_base@@Base+0x19d1e0>
│ │  	beq.n	3095cc <uniffi_pbcli_checksum_method_api_base@@Base+0x19cd48>
│ │  	b.n	3099e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x19d164>
│ │  	movs	r0, r0
│ │ @@ -765141,15 +765141,15 @@
│ │  	asrs	r5, r0, #32
│ │  	b.n	309936 <uniffi_pbcli_checksum_method_api_base@@Base+0x19d0b2>
│ │  			@ <UNDEFINED> instruction: 0xf5e2ebff
│ │  	beq.n	30961c <uniffi_pbcli_checksum_method_api_base@@Base+0x19cd98>
│ │  	b.n	309a94 <uniffi_pbcli_checksum_method_api_base@@Base+0x19d210>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r1, r3, r4, r5, r6, r7, r8, sl, fp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd7c9d6
│ │ +			@ <UNDEFINED> instruction: 0xffd7c9fd
│ │  	vsubw.u16	q15, q12, d23
│ │  	vmlal.u16	q10, d7, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	309956 <uniffi_pbcli_checksum_method_api_base@@Base+0x19d0d2>
│ │  	beq.n	309628 <uniffi_pbcli_checksum_method_api_base@@Base+0x19cda4>
│ │  	b.n	309ab4 <uniffi_pbcli_checksum_method_api_base@@Base+0x19d230>
│ │  	movs	r0, #0
│ │ @@ -765431,15 +765431,15 @@
│ │  	strh	r5, [r7, #34]	@ 0x22
│ │  			@ <UNDEFINED> instruction: 0xebfe6000
│ │  	b.n	309fca <uniffi_pbcli_checksum_method_api_base@@Base+0x19d746>
│ │  	movs	r6, r0
│ │  	b.n	309bce <uniffi_pbcli_checksum_method_api_base@@Base+0x19d34a>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r1, r2, r8, r9, pc}
│ │ -	vshr.u16	<illegal reg q15.5>, <illegal reg q7.5>, #9
│ │ +	vaddl.u16	<illegal reg q15.5>, d23, d6
│ │  			@ <UNDEFINED> instruction: 0xffd848f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	309dbc <uniffi_pbcli_checksum_method_api_base@@Base+0x19d538>
│ │  	str	r0, [r0, #0]
│ │  	b.n	309be6 <uniffi_pbcli_checksum_method_api_base@@Base+0x19d362>
│ │  	lsls	r0, r1, #1
│ │  	b.n	3093ca <uniffi_pbcli_checksum_method_api_base@@Base+0x19cb46>
│ │ @@ -765526,15 +765526,15 @@
│ │  	ldmia.w	sp!, {r2}
│ │  	b.n	309ca6 <uniffi_pbcli_checksum_method_api_base@@Base+0x19d422>
│ │  	strh	r4, [r0, #34]	@ 0x22
│ │  			@ <UNDEFINED> instruction: 0xebfe0000
│ │  	b.n	30a0ae <uniffi_pbcli_checksum_method_api_base@@Base+0x19d82a>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r1, r2, r3, r4, r9, pc}
│ │ -	vmla.i16	q11, <illegal reg q3.5>, d0[0]
│ │ +	vmla.i16	q11, <illegal reg q3.5>, d7[2]
│ │  			@ <UNDEFINED> instruction: 0xffd94bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	309e9c <uniffi_pbcli_checksum_method_api_base@@Base+0x19d618>
│ │  	beq.n	3099a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x19d120>
│ │  	b.n	309e20 <uniffi_pbcli_checksum_method_api_base@@Base+0x19d59c>
│ │  	str	r1, [r0, r0]
│ │  	b.n	309cca <uniffi_pbcli_checksum_method_api_base@@Base+0x19d446>
│ │ @@ -766276,22 +766276,22 @@
│ │  	b.n	30a74e <uniffi_pbcli_checksum_method_api_base@@Base+0x19deca>
│ │  	movs	r0, r2
│ │  	b.n	30a752 <uniffi_pbcli_checksum_method_api_base@@Base+0x19dece>
│ │  	asrs	r2, r1, #2
│ │  	b.n	30a756 <uniffi_pbcli_checksum_method_api_base@@Base+0x19ded2>
│ │  			@ <UNDEFINED> instruction: 0xffceeaff
│ │  	ldrb	r2, [r1, #17]
│ │ -			@ <UNDEFINED> instruction: 0xffd75a7b
│ │ +	vmlsl.u16	<illegal reg q10.5>, d23, d18
│ │  			@ <UNDEFINED> instruction: 0xffd97c1e
│ │ -	vmull.u16	<illegal reg q10.5>, d7, d7[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd75a76
│ │  			@ <UNDEFINED> instruction: 0xffd97c96
│ │ -	vmull.u16	<illegal reg q10.5>, d23, d7[0]
│ │ +	vmull.u16	<illegal reg q10.5>, d23, d6[3]
│ │  			@ <UNDEFINED> instruction: 0xffd97dde
│ │  			@ <UNDEFINED> instruction: 0xffd77b5e
│ │ -			@ <UNDEFINED> instruction: 0xffd7598f
│ │ +			@ <UNDEFINED> instruction: 0xffd759b6
│ │  			@ <UNDEFINED> instruction: 0xffd94c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	30a560 <uniffi_pbcli_checksum_method_api_base@@Base+0x19dcdc>
│ │  	str	r1, [r0, #0]
│ │  	b.n	30a38a <uniffi_pbcli_checksum_method_api_base@@Base+0x19db06>
│ │  	asrs	r4, r3, #6
│ │  	b.n	309b8c <uniffi_pbcli_checksum_method_api_base@@Base+0x19d308>
│ │ @@ -766475,15 +766475,15 @@
│ │  			@ <UNDEFINED> instruction: 0xebff0006
│ │  	b.n	30a52a <uniffi_pbcli_checksum_method_api_base@@Base+0x19dca6>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r4, r5, r7, sl, ip, sp}
│ │  			@ <UNDEFINED> instruction: 0xffd87996
│ │  	vmlal.u16	q8, d23, d19
│ │  	vqrshrun.s32	d30, q3, #8
│ │ -			@ <UNDEFINED> instruction: 0xffd6bc54
│ │ +			@ <UNDEFINED> instruction: 0xffd6bc7b
│ │  	vshll.u16	<illegal reg q15.5>, d17, #8
│ │  			@ <UNDEFINED> instruction: 0xffd67a56
│ │  	vmul.f16	<illegal reg q11.5>, <illegal reg q11.5>, d2[0]
│ │  	vmul.i16	q8, <illegal reg q11.5>, d7[1]
│ │  	vqshl.u16	d26, d14, #8
│ │  			@ <UNDEFINED> instruction: 0xffd84df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │ @@ -766613,17 +766613,17 @@
│ │  	movs	r0, r0
│ │  	b.n	309e42 <uniffi_pbcli_checksum_method_api_base@@Base+0x19d5be>
│ │  			@ <UNDEFINED> instruction: 0xffcceaff
│ │  	str	r0, [r0, #0]
│ │  	b.n	30aa7a <uniffi_pbcli_checksum_method_api_base@@Base+0x19e1f6>
│ │  			@ <UNDEFINED> instruction: 0xffcaeaff
│ │  	ldrb	r2, [r2, #4]
│ │ -			@ <UNDEFINED> instruction: 0xffd7b3e2
│ │ +	vraddhn.i32	d27, <illegal reg q3.5>, <illegal reg q4.5>
│ │  	vqrshrun.s32	d23, q11, #7
│ │ -			@ <UNDEFINED> instruction: 0xffd7b346
│ │ +			@ <UNDEFINED> instruction: 0xffd7b36d
│ │  			@ <UNDEFINED> instruction: 0xffd94ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	30a870 <uniffi_pbcli_checksum_method_api_base@@Base+0x19dfec>
│ │  	beq.n	30a440 <uniffi_pbcli_checksum_method_api_base@@Base+0x19dbbc>
│ │  	b.n	30a7f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x19df70>
│ │  	str	r0, [sp, #0]
│ │  	b.n	30a69e <uniffi_pbcli_checksum_method_api_base@@Base+0x19de1a>
│ │ @@ -766812,15 +766812,15 @@
│ │  	b.n	30a846 <uniffi_pbcli_checksum_method_api_base@@Base+0x19dfc2>
│ │  	asrs	r5, r0, #32
│ │  	b.n	30a84a <uniffi_pbcli_checksum_method_api_base@@Base+0x19dfc6>
│ │  	movs	r1, #130	@ 0x82
│ │  	b.n	30ab0e <uniffi_pbcli_checksum_method_api_base@@Base+0x19e28a>
│ │  	ldr	r0, [pc, #192]	@ (30a5d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x19dd4c>)
│ │  	ldmia.w	sp!, {r0, r2, r3, r5, r6, r9, fp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xea00e3dc
│ │ +			@ <UNDEFINED> instruction: 0xea00e403
│ │  	vshr.u16	d16, d0, #8
│ │  	b.n	30aa1e <uniffi_pbcli_checksum_method_api_base@@Base+0x19e19a>
│ │  	subs	r7, r3, #6
│ │  	b.n	30a842 <uniffi_pbcli_checksum_method_api_base@@Base+0x19dfbe>
│ │  	asrs	r1, r0, #32
│ │  	b.n	30aa28 <uniffi_pbcli_checksum_method_api_base@@Base+0x19e1a4>
│ │  	cmp	r7, #145	@ 0x91
│ │ @@ -767653,20 +767653,20 @@
│ │  	movs	r0, r0
│ │  	b.n	30b31e <uniffi_pbcli_checksum_method_api_base@@Base+0x19ea9a>
│ │  			@ <UNDEFINED> instruction: 0xffd11aff
│ │  	movs	r0, r0
│ │  	b.n	30b328 <uniffi_pbcli_checksum_method_api_base@@Base+0x19eaa4>
│ │  	vpmin.u32	q8, <illegal reg q12.5>, <illegal reg q15.5>
│ │  			@ <UNDEFINED> instruction: 0xffceeaff
│ │ -	b.n	30b2b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x19ea34>
│ │ -	vmull.p<illegal width 16>	<illegal reg q14.5>, d24, d8
│ │ +	b.n	30b306 <uniffi_pbcli_checksum_method_api_base@@Base+0x19ea82>
│ │ +	vmull.p<illegal width 16>	<illegal reg q14.5>, d24, d31
│ │  			@ <UNDEFINED> instruction: 0xffd82afb
│ │ -			@ <UNDEFINED> instruction: 0xffd8de34
│ │ +			@ <UNDEFINED> instruction: 0xffd8de5b
│ │  	vmlsl.u16	q9, d24, d23
│ │ -			@ <UNDEFINED> instruction: 0xffd8ddf4
│ │ +			@ <UNDEFINED> instruction: 0xffd8de1b
│ │  	vmlal.u16	q10, d8, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	30afee <uniffi_pbcli_checksum_method_api_base@@Base+0x19e76a>
│ │  	beq.n	30acd0 <uniffi_pbcli_checksum_method_api_base@@Base+0x19e44c>
│ │  	b.n	30b14c <uniffi_pbcli_checksum_method_api_base@@Base+0x19e8c8>
│ │  	stmia	r0!, {r2, r4, r5}
│ │  	b.n	30a7f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x19df70>
│ │ @@ -768557,57 +768557,57 @@
│ │  	movs	r4, r1
│ │  	b.n	30bafe <uniffi_pbcli_checksum_method_api_base@@Base+0x19f27a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	30bb82 <uniffi_pbcli_checksum_method_api_base@@Base+0x19f2fe>
│ │  	movs	r6, r0
│ │  	b.n	30bbc6 <uniffi_pbcli_checksum_method_api_base@@Base+0x19f342>
│ │  			@ <UNDEFINED> instruction: 0xffd9eaff
│ │ -	bge.n	30b42c <uniffi_pbcli_checksum_method_api_base@@Base+0x19eba8>
│ │ -	vsri.16	q11, <illegal reg q15.5>, #8
│ │ -	vabdl.u16	<illegal reg q14.5>, d9, d12
│ │ -	vshr.u64	d22, d27, #40
│ │ -	vmlal.u16	<illegal reg q14.5>, d9, d8
│ │ -	vsra.u64	d22, d23, #40
│ │ -	vmlal.u16	<illegal reg q14.5>, d25, d12
│ │ -	vrshr.u16	d22, d27, #8
│ │ -			@ <UNDEFINED> instruction: 0xffd9d7e8
│ │ -	vsra.u64	d22, d7, #40
│ │ -	vmls.i16	<illegal reg q14.5>, <illegal reg q4.5>, d4[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd85e13
│ │ -	vshll.u16	<illegal reg q14.5>, d4, #9
│ │ +	bge.n	30b47a <uniffi_pbcli_checksum_method_api_base@@Base+0x19ebf6>
│ │ +	vraddhn.i32	d22, q12, q11
│ │ +	vqshl.u16	d29, d19, #9
│ │ +	vmla.i16	q11, q12, d2[2]
│ │ +	vmlal.u16	<illegal reg q14.5>, d9, d31
│ │ +	vsra.u64	q11, q7, #40
│ │ +			@ <UNDEFINED> instruction: 0xffd9d8b3
│ │ +	vmlal.u16	q11, d8, d2[2]
│ │ +	vmlal.u16	<illegal reg q14.5>, d9, d15
│ │ +	vsra.u64	d22, d30, #40
│ │ +	vraddhn.i32	d29, <illegal reg q12.5>, <illegal reg q5.5>
│ │ +			@ <UNDEFINED> instruction: 0xffd85e3a
│ │ +	vshll.u16	<illegal reg q14.5>, d27, #9
│ │  	vqshlu.s64	d31, d0, #24
│ │  	vsli.32	q9, q0, #31
│ │  	movs	r5, r3
│ │  	movs	r3, #12
│ │  	movs	r5, r3
│ │  	bl	1444ca <UNIFFI_META_PBCLI_METHOD_API_BASE@@Base+0xdacb0>
│ │  	movs	r4, #248	@ 0xf8
│ │  	movs	r5, r3
│ │  	movs	r2, #180	@ 0xb4
│ │  	movs	r5, r3
│ │ -	bvs.n	30b4a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x19ec1c>
│ │ -	vshr.u64	d22, d3, #40
│ │ -	vrsubhn.i32	d29, <illegal reg q12.5>, q14
│ │ -	vshr.u16	q11, <illegal reg q5.5>, #8
│ │ -	vabdl.u16	<illegal reg q14.5>, d9, d24
│ │ -	vshr.u64	q11, <illegal reg q3.5>, #40
│ │ -	vsri.64	d29, d12, #39
│ │ -	vqrdmlah.s16	<illegal reg q10.5>, q4, d3[1]
│ │ -	vsli.16	<illegal reg q14.5>, q6, #9
│ │ -			@ <UNDEFINED> instruction: 0xffd85f0b
│ │ -	vabal.u16	<illegal reg q14.5>, d25, d4
│ │ -			@ <UNDEFINED> instruction: 0xffd85f33
│ │ -	vsri.64	<illegal reg q14.5>, q8, #39
│ │ -			@ <UNDEFINED> instruction: 0xffd85e9f
│ │ -	vmls.f16	<illegal reg q14.5>, <illegal reg q12.5>, d0[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd85f8f
│ │ -	vabal.u16	<illegal reg q14.5>, d25, d28
│ │ -			@ <UNDEFINED> instruction: 0xffd85f5b
│ │ -	vqshl.u64	d29, d24, #25
│ │ -	vmla.f16	q11, q4, d7[2]
│ │ +	bvc.n	30b4ee <uniffi_pbcli_checksum_method_api_base@@Base+0x19ec6a>
│ │ +	vshr.u64	d22, d26, #40
│ │ +	vqshlu.s64	<illegal reg q14.5>, <illegal reg q1.5>, #25
│ │ +	vaddl.u16	q11, d24, d2
│ │ +			@ <UNDEFINED> instruction: 0xffd9d74f
│ │ +	vshr.u64	q11, q15, #40
│ │ +	vmls.i16	<illegal reg q14.5>, <illegal reg q12.5>, d3[0]
│ │ +			@ <UNDEFINED> instruction: 0xffd85e72
│ │ +	vabal.u16	<illegal reg q14.5>, d25, d3
│ │ +			@ <UNDEFINED> instruction: 0xffd85f32
│ │ +	vabal.u16	<illegal reg q14.5>, d25, d27
│ │ +			@ <UNDEFINED> instruction: 0xffd85f5a
│ │ +	vsli.16	d29, d7, #9
│ │ +	vqrdmlah.s16	<illegal reg q10.5>, q12, d6[0]
│ │ +	vrsubhn.i32	d29, <illegal reg q4.5>, <illegal reg q3.5>
│ │ +			@ <UNDEFINED> instruction: 0xffd85fb6
│ │ +	vsli.64	<illegal reg q14.5>, <illegal reg q1.5>, #25
│ │ +			@ <UNDEFINED> instruction: 0xffd85f82
│ │ +	vqshl.u64	<illegal reg q14.5>, <illegal reg q7.5>, #25
│ │ +	vaddw.u16	q11, q12, d14
│ │  			@ <UNDEFINED> instruction: 0xffd94df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	30ba48 <uniffi_pbcli_checksum_method_api_base@@Base+0x19f1c4>
│ │  	beq.n	30b540 <uniffi_pbcli_checksum_method_api_base@@Base+0x19ecbc>
│ │  	b.n	30b9cc <uniffi_pbcli_checksum_method_api_base@@Base+0x19f148>
│ │  	movs	r0, r0
│ │  	b.n	30bbd6 <uniffi_pbcli_checksum_method_api_base@@Base+0x19f352>
│ │ @@ -768835,25 +768835,25 @@
│ │  	b.n	30be62 <uniffi_pbcli_checksum_method_api_base@@Base+0x19f5de>
│ │  			@ <UNDEFINED> instruction: 0xffcdeaff
│ │  	lsls	r0, r0, #1
│ │  	b.n	30b258 <uniffi_pbcli_checksum_method_api_base@@Base+0x19e9d4>
│ │  	stmia	r0!, {r3, r5}
│ │  	b.n	30b24e <uniffi_pbcli_checksum_method_api_base@@Base+0x19e9ca>
│ │  			@ <UNDEFINED> instruction: 0xffd0eaff
│ │ -	bcc.n	30b76c <uniffi_pbcli_checksum_method_api_base@@Base+0x19eee8>
│ │ +	bcc.n	30b7ba <uniffi_pbcli_checksum_method_api_base@@Base+0x19ef36>
│ │  	vrsubhn.i32	d19, q4, <illegal reg q14.5>
│ │ -	vmlal.u16	<illegal reg q14.5>, d24, d0[0]
│ │ +	vmlal.u16	<illegal reg q14.5>, d24, d7[2]
│ │  	vsli.64	<illegal reg q9.5>, <illegal reg q0.5>, #24
│ │ -	vsubl.u16	<illegal reg q14.5>, d24, d12
│ │ +	vrshr.u64	d29, d19, #40
│ │  	vsli.64	d19, d13, #24
│ │ -	vrshr.u64	<illegal reg q14.5>, q6, #40
│ │ +	vsubw.u16	<illegal reg q14.5>, q4, d3
│ │  	vmls.f16	<illegal reg q9.5>, q12, d5[3]
│ │ -	vsra.u64	<illegal reg q14.5>, q2, #40
│ │ +	vsra.u64	<illegal reg q14.5>, <illegal reg q13.5>, #40
│ │  	vmls.i16	<illegal reg q9.5>, q12, d5[2]
│ │ -	vsubl.u16	<illegal reg q14.5>, d8, d0
│ │ +	vsubl.u16	<illegal reg q14.5>, d8, d23
│ │  	vsli.16	d19, d1, #8
│ │  	vaddl.u16	<illegal reg q8.5>, d8, d0
│ │  	b.n	30bea6 <uniffi_pbcli_checksum_method_api_base@@Base+0x19f622>
│ │  	movs	r0, #32
│ │  	b.n	30beaa <uniffi_pbcli_checksum_method_api_base@@Base+0x19f626>
│ │  	adds	r0, #0
│ │  	b.n	30beae <uniffi_pbcli_checksum_method_api_base@@Base+0x19f62a>
│ │ @@ -768986,22 +768986,22 @@
│ │  	b.n	30c04a <uniffi_pbcli_checksum_method_api_base@@Base+0x19f7c6>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r3, sp, lr, pc}
│ │  	b.n	30b3a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x19eb24>
│ │  	ldr	r0, [pc, #0]	@ (30b894 <uniffi_pbcli_checksum_method_api_base@@Base+0x19f010>)
│ │  	ldmia.w	sp!, {r2, r3, r4, r8, r9, sl, fp, ip, sp, lr, pc}
│ │  	b.n	30baf8 <uniffi_pbcli_checksum_method_api_base@@Base+0x19f274>
│ │ -	beq.n	30b87c <uniffi_pbcli_checksum_method_api_base@@Base+0x19eff8>
│ │ -	vqdmulh.s16	<illegal reg q13.5>, q12, d4[2]
│ │ -	vshr.u64	d29, d4, #40
│ │ -	vmull.u16	<illegal reg q13.5>, d24, d8
│ │ -	vmla.i16	<illegal reg q14.5>, q4, d0[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd8bc54
│ │ -	vshr.u64	d29, d16, #40
│ │ -	vmull.u16	<illegal reg q13.5>, d24, d20
│ │ +	bne.n	30b8ca <uniffi_pbcli_checksum_method_api_base@@Base+0x19f046>
│ │ +			@ <UNDEFINED> instruction: 0xffd8bd0b
│ │ +	vshr.u64	d29, d27, #40
│ │ +	vmull.u16	<illegal reg q13.5>, d24, d31
│ │ +	vaddl.u16	<illegal reg q14.5>, d24, d7
│ │ +			@ <UNDEFINED> instruction: 0xffd8bc7b
│ │ +	vshr.u64	<illegal reg q14.5>, <illegal reg q3.5>, #40
│ │ +	vqdmulh.s16	<illegal reg q13.5>, q12, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffd84df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	30bddc <uniffi_pbcli_checksum_method_api_base@@Base+0x19f558>
│ │  	beq.n	30b8f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x19f070>
│ │  	b.n	30bd60 <uniffi_pbcli_checksum_method_api_base@@Base+0x19f4dc>
│ │  	str	r1, [r0, r0]
│ │  	b.n	30bc0a <uniffi_pbcli_checksum_method_api_base@@Base+0x19f386>
│ │ @@ -769385,28 +769385,28 @@
│ │  	b.n	30bf4a <uniffi_pbcli_checksum_method_api_base@@Base+0x19f6c6>
│ │  	lsls	r0, r3, #10
│ │  	add.w	r0, r0, r1
│ │  	b.n	30c352 <uniffi_pbcli_checksum_method_api_base@@Base+0x19face>
│ │  	beq.n	30bc44 <uniffi_pbcli_checksum_method_api_base@@Base+0x19f3c0>
│ │  	b.n	30c0ac <uniffi_pbcli_checksum_method_api_base@@Base+0x19f828>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r3, r6, r7, r8, sl, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r5, r6, r7, r8, sl, fp, lr, pc}
│ │  	vmul.f16	q12, q12, d4[0]
│ │ -	vabal.u16	q9, d24, d4
│ │ +	vabal.u16	q9, d24, d27
│ │  	vsli.64	<illegal reg q14.5>, <illegal reg q14.5>, #25
│ │  			@ <UNDEFINED> instruction: 0xffd71b86
│ │ -			@ <UNDEFINED> instruction: 0xffd76d9a
│ │ -	vrshr.u64	d30, d30, #39
│ │ +	vqrdmulh.s16	q11, <illegal reg q11.5>, d1[0]
│ │ +	vmlal.u16	q15, d25, d5[2]
│ │  			@ <UNDEFINED> instruction: 0xffd8490a
│ │  	vmull.u16	q9, d8, d2[2]
│ │ -	vraddhn.i32	d26, q12, <illegal reg q10.5>
│ │ +	vmls.i16	q13, q12, d4[1]
│ │  	vqshlu.s64	q8, <illegal reg q13.5>, #24
│ │  	vmla.i16	q11, q4, d3[0]
│ │  	vqshlu.s64	d28, d20, #23
│ │ -	vmul.i16	<illegal reg q9.5>, q11, d5[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd638f4
│ │  	vqshrun.s32	d20, q8, #7
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	30c174 <uniffi_pbcli_checksum_method_api_base@@Base+0x19f8f0>
│ │  	ands	r0, r0
│ │  	b.n	30bf9e <uniffi_pbcli_checksum_method_api_base@@Base+0x19f71a>
│ │  	lsls	r0, r1, #7
│ │  	b.n	30b7a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x19ef1c>
│ │ @@ -769614,18 +769614,18 @@
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r3, r4, r6, r9, sl, fp, ip, sp, lr, pc}
│ │  	vqrshrun.s32	d16, q10, #10
│ │  	movs	r2, r3
│ │  	strb	r6, [r3, #26]
│ │  			@ <UNDEFINED> instruction: 0xffd709ac
│ │  	movs	r2, r3
│ │ -	ldmia	r4!, {r0, r1, r6}
│ │ -	vmul.i16	<illegal reg q15.5>, q4, d3[2]
│ │ -	vsubl.u16	q12, d24, d10
│ │ -			@ <UNDEFINED> instruction: 0xffd93cb8
│ │ +	ldmia	r4!, {r1, r3, r5, r6}
│ │ +	vmlal.u16	<illegal reg q15.5>, d24, d10
│ │ +	vrshr.u64	d24, d17, #40
│ │ +			@ <UNDEFINED> instruction: 0xffd93cdf
│ │  	vqrdmlah.s16	q9, <illegal reg q12.5>, d7[3]
│ │  			@ <UNDEFINED> instruction: 0xffd8fdb3
│ │  	vsli.64	<illegal reg q11.5>, q12, #22
│ │  			@ <UNDEFINED> instruction: 0xffd75c78
│ │  	vrsubhn.i32	d26, q4, <illegal reg q12.5>
│ │  			@ <UNDEFINED> instruction: 0xffd78ad0
│ │  			@ <UNDEFINED> instruction: 0xffd84765
│ │ @@ -771326,26 +771326,26 @@
│ │  	b.n	30d1ac <uniffi_pbcli_checksum_method_api_base@@Base+0x1a0928>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, ip, sp, lr}
│ │  	b.n	30d45e <uniffi_pbcli_checksum_method_api_base@@Base+0x1a0bda>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │  	ldrb	r4, [r1, #0]
│ │  	vmls.i16	q14, q4, d5[0]
│ │ -	vrsra.u64	d17, d0, #41
│ │ -	vsra.u16	<illegal reg q14.5>, q15, #7
│ │ +	vrsra.u64	d17, d23, #41
│ │ +	vaddw.u16	<illegal reg q14.5>, <illegal reg q12.5>, d21
│ │  	vmul.f16	q8, q12, d6[0]
│ │ -			@ <UNDEFINED> instruction: 0xffd75be6
│ │ +	vmull.u16	<illegal reg q10.5>, d7, d13
│ │  	vabdl.u16	<illegal reg q9.5>, d25, d14
│ │  	vmul.i16	<illegal reg q8.5>, q12, d6[2]
│ │ -	vmull.u16	<illegal reg q13.5>, d8, d4[2]
│ │ -	vsubw.u16	<illegal reg q12.5>, q4, d5
│ │ +	vmlsl.u16	<illegal reg q13.5>, d24, d11
│ │ +	vsubw.u16	<illegal reg q12.5>, q4, d28
│ │  	vsli.16	<illegal reg q15.5>, <illegal reg q9.5>, #8
│ │  	vqrdmlah.s16	q10, <illegal reg q11.5>, d7[1]
│ │  	vmls.f16	<illegal reg q13.5>, <illegal reg q3.5>, d4[1]
│ │ -			@ <UNDEFINED> instruction: 0xffd62765
│ │ +	vabdl.u16	q9, d22, d12
│ │  			@ <UNDEFINED> instruction: 0xffd94ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	30d27c <uniffi_pbcli_checksum_method_api_base@@Base+0x1a09f8>
│ │  	beq.n	30cd7c <uniffi_pbcli_checksum_method_api_base@@Base+0x1a04f8>
│ │  	b.n	30d200 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a097c>
│ │  	str	r2, [r0, #0]
│ │  	b.n	30d0aa <uniffi_pbcli_checksum_method_api_base@@Base+0x1a0826>
│ │ @@ -771594,25 +771594,25 @@
│ │  	and.w	r0, r0, r0, lsl #28
│ │  	b.n	30d6b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a0e2e>
│ │  	movs	r7, r0
│ │  	b.n	30d2b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a0a32>
│ │  	beq.n	30cfb0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a072c>
│ │  	b.n	30d410 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a0b8c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r3, r5, r6, r8, r9, fp, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r4, r7, r8, r9, fp, ip, sp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd87ab8
│ │  			@ <UNDEFINED> instruction: 0xffd87a99
│ │ -	vmla.f16	<illegal reg q11.5>, q4, d4[2]
│ │ +	vaddw.u16	<illegal reg q11.5>, q12, d11
│ │  	vmull.u16	<illegal reg q11.5>, d9, d3[0]
│ │ -			@ <UNDEFINED> instruction: 0xffd82892
│ │ -	vqshlu.s64	d27, d14, #25
│ │ -	vqrdmulh.s16	q11, q12, d4[2]
│ │ -	vrsubhn.i32	d18, <illegal reg q4.5>, q11
│ │ -	vmlsl.u16	<illegal reg q13.5>, d9, d2[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd8b99a
│ │ +			@ <UNDEFINED> instruction: 0xffd828b9
│ │ +	vmlsl.u16	<illegal reg q13.5>, d25, d5[0]
│ │ +	vmull.p<illegal width 16>	q11, d8, d11
│ │ +	vmlsl.u16	q9, d9, d5[1]
│ │ +	vrsubhn.i32	d27, <illegal reg q12.5>, <illegal reg q4.5>
│ │ +	vmul.f16	<illegal reg q13.5>, q12, d1[0]
│ │  			@ <UNDEFINED> instruction: 0xffd84ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	30d4cc <uniffi_pbcli_checksum_method_api_base@@Base+0x1a0c48>
│ │  	beq.n	30d08c <uniffi_pbcli_checksum_method_api_base@@Base+0x1a0808>
│ │  	b.n	30d450 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a0bcc>
│ │  	strb	r1, [r0, #0]
│ │  	b.n	30d2fa <uniffi_pbcli_checksum_method_api_base@@Base+0x1a0a76>
│ │ @@ -772841,17 +772841,17 @@
│ │  	str	r0, [r7, r0]
│ │  	b.n	30d438 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a0bb4>
│ │  	movs	r0, #64	@ 0x40
│ │  	b.n	30d43c <uniffi_pbcli_checksum_method_api_base@@Base+0x1a0bb8>
│ │  	ands	r0, r0
│ │  	b.n	30e14a <uniffi_pbcli_checksum_method_api_base@@Base+0x1a18c6>
│ │  	mrc2	10, 5, lr, cr15, cr15, {7}	@ <UNPREDICTABLE>
│ │ -	str	r5, [r2, r0]
│ │ +	str	r4, [r7, r0]
│ │  	vmull.u16	<illegal reg q8.5>, d25, d21
│ │ -			@ <UNDEFINED> instruction: 0xffd7b7ef
│ │ +	vqshrun.s32	d27, q3, #9
│ │  	vmul.f16	q10, q4, d2[0]
│ │  	vqshl.u64	<illegal reg q11.5>, <illegal reg q12.5>, #24
│ │  	vqrshrun.s32	d20, q3, #8
│ │  	vabdl.u16	<illegal reg q11.5>, d8, d13
│ │  	vraddhn.i32	d20, q12, q13
│ │  	vrsra.u64	q10, q11, #40
│ │  	vqshl.u16	d20, d14, #8
│ │ @@ -774669,17 +774669,17 @@
│ │  			@ <UNDEFINED> instruction: 0xffee0aff
│ │  	lsrs	r2, r0, #8
│ │  	b.n	30f0e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a2862>
│ │  			@ <UNDEFINED> instruction: 0xffc0eaff
│ │  	lsrs	r1, r0, #32
│ │  	b.n	30f0ee <uniffi_pbcli_checksum_method_api_base@@Base+0x1a286a>
│ │  			@ <UNDEFINED> instruction: 0xffbeeaff
│ │ -	subs	r6, #165	@ 0xa5
│ │ +	subs	r6, #204	@ 0xcc
│ │  			@ <UNDEFINED> instruction: 0xffd90b49
│ │ -	vrsubhn.i32	d26, <illegal reg q11.5>, <illegal reg q1.5>
│ │ +	vrsubhn.i32	d26, <illegal reg q11.5>, q13
│ │  			@ <UNDEFINED> instruction: 0xffd84c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	30eee0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a265c>
│ │  	beq.n	30e9e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a2164>
│ │  	b.n	30ee64 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a25e0>
│ │  	stmia	r0!, {r1}
│ │  	b.n	30ed0e <uniffi_pbcli_checksum_method_api_base@@Base+0x1a248a>
│ │ @@ -778978,18 +778978,18 @@
│ │  	movs	r7, #28
│ │  	movs	r5, r3
│ │  	movs	r7, #4
│ │  	movs	r5, r3
│ │  	ldr	r2, [sp, #960]	@ 0x3c0
│ │  	vmlsl.u16	q9, d7, d0[0]
│ │  	movs	r5, r3
│ │ -	ldrd	pc, pc, [sl, #864]!	@ 0x360
│ │ +			@ <UNDEFINED> instruction: 0xea21ffd8
│ │  	movs	r6, #248	@ 0xf8
│ │  	movs	r5, r3
│ │ -	ldrd	pc, pc, [lr, #864]	@ 0x360
│ │ +			@ <UNDEFINED> instruction: 0xea05ffd8
│ │  	movs	r7, #144	@ 0x90
│ │  	movs	r5, r3
│ │  	ldc2l	15, cr15, [ip], #-1020	@ 0xfffffc04
│ │  	movs	r7, #124	@ 0x7c
│ │  	movs	r5, r3
│ │  	movs	r7, #100	@ 0x64
│ │  	movs	r5, r3
│ │ @@ -779413,15 +779413,15 @@
│ │  	asrs	r0, r1, #32
│ │  	b.n	310ef0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a466c>
│ │  	movs	r0, #53	@ 0x35
│ │  	b.n	311af6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a5272>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3114d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a4c54>
│ │  	cmp	r6, #195	@ 0xc3
│ │ -	and.w	r1, r0, ip, lsr #24
│ │ +	and.w	r1, r0, r3, lsl #25
│ │  			@ <UNDEFINED> instruction: 0xffd84c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3118e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a5060>
│ │  	beq.n	31140c <uniffi_pbcli_checksum_method_api_base@@Base+0x1a4b88>
│ │  	b.n	311868 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a4fe4>
│ │  	ands	r2, r0
│ │  	b.n	311712 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a4e8e>
│ │ @@ -779901,15 +779901,15 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	311f1e <uniffi_pbcli_checksum_method_api_base@@Base+0x1a569a>
│ │  	asrs	r5, r4, #24
│ │  			@ <UNDEFINED> instruction: 0xebff0005
│ │  	b.n	311b26 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a52a2>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r1, r2, r3, r5, r6, r7, r9, ip, sp}
│ │ -			@ <UNDEFINED> instruction: 0xffd73e7d
│ │ +	vmull.p<illegal width 16>	<illegal reg q9.5>, d23, d20
│ │  			@ <UNDEFINED> instruction: 0xffd94c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	311d14 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a5490>
│ │  	ands	r1, r0
│ │  	b.n	311b3e <uniffi_pbcli_checksum_method_api_base@@Base+0x1a52ba>
│ │  	movs	r0, r0
│ │  	b.n	311ea2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a561e>
│ │ @@ -780080,15 +780080,15 @@
│ │  	ands	r0, r0
│ │  	b.n	3120ae <uniffi_pbcli_checksum_method_api_base@@Base+0x1a582a>
│ │  	asrs	r1, r0, #23
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	311cb6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a5432>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r1, r2, r3, r4, r6, r8, ip, sp}
│ │ -	vabal.u16	q12, d7, d23
│ │ +	vmls.f16	q12, <illegal reg q3.5>, d6[1]
│ │  	vmlal.u16	q10, d8, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	311cca <uniffi_pbcli_checksum_method_api_base@@Base+0x1a5446>
│ │  	movs	r4, r0
│ │  	add.w	r0, r0, r0
│ │  	b.n	312032 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a57ae>
│ │  	asrs	r0, r0, #32
│ │ @@ -781413,15 +781413,15 @@
│ │  	vqshl.u16	d28, d25, #7
│ │  	vrsra.u64	q9, <illegal reg q0.5>, #41
│ │  	vmul.i16	q14, q4, d1[0]
│ │  	vsri.64	q9, <illegal reg q4.5>, #41
│ │  	vaddw.u16	q15, q4, d29
│ │  	vabdl.u16	q14, d22, d1
│ │  	vsri.16	d18, d9, #9
│ │ -	vshr.u64	d25, d1, #40
│ │ +	vshr.u64	d25, d24, #40
│ │  	vabdl.u16	q14, d8, d1
│ │  			@ <UNDEFINED> instruction: 0xffd74c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	312aa0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a621c>
│ │  	ands	r1, r0
│ │  	b.n	3128ca <uniffi_pbcli_checksum_method_api_base@@Base+0x1a6046>
│ │  	asrs	r0, r0, #32
│ │ @@ -783818,27 +783818,27 @@
│ │  	lsls	r0, r4, #6
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r2, r3, r5}
│ │  	b.n	313574 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a6cf0>
│ │  	movs	r0, r0
│ │  	b.n	313b58 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a72d4>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r2, r5, r6, r7, r8, r9, ip, pc}
│ │ -	vshr.u16	d28, d9, #8
│ │ -			@ <UNDEFINED> instruction: 0xffd81c90
│ │ -			@ <UNDEFINED> instruction: 0xffd92e74
│ │ -			@ <UNDEFINED> instruction: 0xffddd8b7
│ │ -	vsri.64	d22, d19, #40
│ │ +	ldmia.w	sp!, {r0, r1, r3, sl, ip, pc}
│ │ +	vmla.i16	q14, q4, d0[0]
│ │ +			@ <UNDEFINED> instruction: 0xffd80ed8
│ │ +			@ <UNDEFINED> instruction: 0xffd82e74
│ │ +			@ <UNDEFINED> instruction: 0xffddd8de
│ │ +	vsri.64	q11, q5, #40
│ │  	vmul.f16	q14, q4, d5[3]
│ │  			@ <UNDEFINED> instruction: 0xffd74f84
│ │  	vmul.i16	<illegal reg q15.5>, q3, d3[1]
│ │  	vshll.u16	<illegal reg q12.5>, d24, #7
│ │  	movs	r4, r3
│ │ -	stcl	15, cr15, [r7, #-864]!	@ 0xfffffca0
│ │ -	stmia	r0!, {r0, r1, r4}
│ │ +	stc	15, cr15, [lr, #864]	@ 0x360
│ │ +	stmia	r0!, {r1, r3, r4, r5}
│ │  	vaddl.u16	q8, d8, d4
│ │  	b.n	3135b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a6d2c>
│ │  	movs	r0, r0
│ │  	b.n	313b94 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a7310>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	str	r7, [r7, #112]	@ 0x70
│ │  	vaddl.u16	q8, d6, d4
│ │ @@ -783848,15 +783848,15 @@
│ │  	vrhadd.u16	d14, d14, d31
│ │  	b.n	313cc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a743e>
│ │  	vaddl.u16	q8, d6, d4
│ │  	b.n	3135d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a6d4c>
│ │  	movs	r0, r0
│ │  	b.n	313bb4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a7330>
│ │  	vrhadd.u16	d14, d14, d31
│ │ -	subs	r2, #86	@ 0x56
│ │ +	subs	r2, #125	@ 0x7d
│ │  	vaddl.u16	q8, d8, d4
│ │  	b.n	3135e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a6d5c>
│ │  	movs	r0, r0
│ │  	b.n	313bc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a7340>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldmia	r1!, {r0, r3, r4, r5, r6}
│ │  			@ <UNDEFINED> instruction: 0xffd74ff0
│ │ @@ -784297,17 +784297,17 @@
│ │  			@ <UNDEFINED> instruction: 0xebffffc2
│ │  			@ <UNDEFINED> instruction: 0xeaff8000
│ │  	b.n	3145ba <uniffi_pbcli_checksum_method_api_base@@Base+0x1a7d36>
│ │  	str	r0, [r1, #0]
│ │  	b.n	3139b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a7134>
│ │  			@ <UNDEFINED> instruction: 0xffc2eaff
│ │  	udf	#239	@ 0xef
│ │ -			@ <UNDEFINED> instruction: 0xffd7eb9e
│ │ +			@ <UNDEFINED> instruction: 0xffd7ebc5
│ │  	vmls.f16	q10, q12, d0[0]
│ │ -	vqshl.u64	<illegal reg q13.5>, <illegal reg q6.5>, #22
│ │ +	vmlal.u16	<illegal reg q13.5>, d6, d4
│ │  			@ <UNDEFINED> instruction: 0xffd83e3e
│ │  	vmul.i16	q14, <illegal reg q3.5>, d4[2]
│ │  	vqdmulh.s16	<illegal reg q14.5>, q3, d3[0]
│ │  			@ <UNDEFINED> instruction: 0xffd74c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3143c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a7b3c>
│ │  			@ <UNDEFINED> instruction: 0xf3e9ebff
│ │ @@ -785657,23 +785657,23 @@
│ │  	movs	r4, r0
│ │  	b.n	3151ee <uniffi_pbcli_checksum_method_api_base@@Base+0x1a896a>
│ │  	movs	r0, #25
│ │  	b.n	3151f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a896e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	314bd4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a8350>
│ │  	movs	r0, #42	@ 0x2a
│ │ -			@ <UNDEFINED> instruction: 0xea00dd10
│ │ +			@ <UNDEFINED> instruction: 0xea00dd37
│ │  	vaddl.u16	<illegal reg q8.5>, d8, d8
│ │  	b.n	314600 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a7d7c>
│ │  	movs	r0, #31
│ │  	b.n	315206 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a8982>
│ │  	asrs	r1, r0, #32
│ │  	b.n	314be8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a8364>
│ │  	movs	r0, #255	@ 0xff
│ │ -			@ <UNDEFINED> instruction: 0xea00dcfc
│ │ +			@ <UNDEFINED> instruction: 0xea00dd23
│ │  			@ <UNDEFINED> instruction: 0xffd84c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	314ff4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a8770>
│ │  	ands	r1, r0
│ │  	b.n	314e1e <uniffi_pbcli_checksum_method_api_base@@Base+0x1a859a>
│ │  	asrs	r6, r2, #32
│ │  	b.n	315222 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a899e>
│ │ @@ -785872,15 +785872,15 @@
│ │  	movs	r0, r0
│ │  	b.n	314dbc <uniffi_pbcli_checksum_method_api_base@@Base+0x1a8538>
│ │  	ands	r0, r0
│ │  	b.n	3147a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a7f1e>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r4, r5, r6, r8, r9, sl, pc}
│ │  	movs	r4, r3
│ │ -	stc2	15, cr15, [r0], #860	@ 0x35c
│ │ +	stc2l	15, cr15, [r7], {215}	@ 0xd7
│ │  	ldrh	r0, [r2, #2]
│ │  	movs	r4, r3
│ │  	asrs	r3, r6, #29
│ │  	vqshlu.s16	d30, d20, #7
│ │  	vmull.u16	q15, d23, d4[1]
│ │  	movs	r4, r3
│ │  			@ <UNDEFINED> instruction: 0xeab0001c
│ │ @@ -788522,77 +788522,77 @@
│ │  	b.n	3166bc <uniffi_pbcli_checksum_method_api_base@@Base+0x1a9e38>
│ │  	ldr	r3, [r1, #104]	@ 0x68
│ │  	add.w	r9, r0, ip, asr #14
│ │  			@ <UNDEFINED> instruction: 0xebff99b5
│ │  			@ <UNDEFINED> instruction: 0xebff39ae
│ │  			@ <UNDEFINED> instruction: 0xebff4c10
│ │  	ldmia.w	sp!, {r1, r4, r5, r7, r8, fp, ip, pc}
│ │ -			@ <UNDEFINED> instruction: 0xeaffebb7
│ │ +			@ <UNDEFINED> instruction: 0xeaffebde
│ │  	vqrdmlsh.s16	<illegal reg q13.5>, <illegal reg q3.5>, d6[2]
│ │  	vmla.f16	<illegal reg q12.5>, q3, d2[3]
│ │ -	vaddw.u16	q8, q11, d29
│ │ +	vsra.u64	q8, q2, #42
│ │  	vmlsl.u16	<illegal reg q14.5>, d8, d3[3]
│ │  			@ <UNDEFINED> instruction: 0xffd64e34
│ │ -	vmls.i16	<illegal reg q13.5>, <illegal reg q11.5>, d2[3]
│ │ -			@ <UNDEFINED> instruction: 0xffd89c72
│ │ +	vsli.16	d27, d1, #7
│ │ +			@ <UNDEFINED> instruction: 0xffd89c99
│ │  	vabal.u16	q10, d8, d11
│ │  			@ <UNDEFINED> instruction: 0xffd62c53
│ │ -	vsli.64	q12, q6, #22
│ │ +	vrsubhn.i32	d24, q3, <illegal reg q1.5>
│ │  			@ <UNDEFINED> instruction: 0xffd88f15
│ │  	vmull.u16	q15, d23, d27
│ │  	vshr.u64	d25, d7, #42
│ │ -	vsli.64	d24, d4, #22
│ │ +	vsli.64	d24, d27, #22
│ │  	vqrdmulh.s16	q10, q4, d4[2]
│ │  	vsubl.u16	<illegal reg q14.5>, d7, d18
│ │  	vraddhn.i32	d20, <illegal reg q3.5>, q10
│ │  	vshr.u16	d25, d0, #10
│ │ -	vrsubhn.i32	d17, q11, <illegal reg q12.5>
│ │ +	vqshlu.s64	<illegal reg q8.5>, q0, #22
│ │  	vaddw.u16	q15, q12, d3
│ │ -	vshll.u16	q9, d3, #7
│ │ +	vshll.u16	q9, d26, #7
│ │  	vrsubhn.i32	d23, q12, q15
│ │  	vqshlu.s64	d23, d14, #22
│ │ -			@ <UNDEFINED> instruction: 0xffd63f89
│ │ +			@ <UNDEFINED> instruction: 0xffd63fb0
│ │  			@ <UNDEFINED> instruction: 0xffd85c16
│ │ -			@ <UNDEFINED> instruction: 0xffd6ffad
│ │ +			@ <UNDEFINED> instruction: 0xffd6ffd4
│ │  			@ <UNDEFINED> instruction: 0xffd7bbaf
│ │ -	vmla.i16	q15, <illegal reg q3.5>, d0[2]
│ │ +	vaddl.u16	q15, d23, d7
│ │  			@ <UNDEFINED> instruction: 0xffd8bb82
│ │ -			@ <UNDEFINED> instruction: 0xffd73f24
│ │ -	vsli.64	<illegal reg q10.5>, q0, #24
│ │ -			@ <UNDEFINED> instruction: 0xffd83edf
│ │ +	vqrdmlsh.s16	<illegal reg q9.5>, <illegal reg q3.5>, d3[1]
│ │ +	vsli.64	<illegal reg q10.5>, <illegal reg q11.5>, #24
│ │ +			@ <UNDEFINED> instruction: 0xffd83f06
│ │  	vrsra.u16	<illegal reg q9.5>, q2, #8
│ │  	vrshr.u64	<illegal reg q14.5>, q10, #41
│ │  	vsubl.u16	q11, d23, d0
│ │  	vsubl.u16	q10, d23, d12
│ │  	vmull.u16	<illegal reg q8.5>, d6, d4[3]
│ │ -	vmull.p<illegal width 16>	<illegal reg q9.5>, d7, d24
│ │ -	vsri.64	d17, d9, #40
│ │ +	vqrdmlah.s16	<illegal reg q9.5>, <illegal reg q3.5>, d7[1]
│ │ +	vmls.i16	<illegal reg q8.5>, q12, d0[0]
│ │  	vrshr.u16	d29, d25, #8
│ │  			@ <UNDEFINED> instruction: 0xffd728be
│ │  	vmla.f16	q10, <illegal reg q11.5>, d5[2]
│ │ -	vqshrun.s32	d18, <illegal reg q5.5>, #10
│ │ +	vmul.i16	q9, q3, d2[0]
│ │  	vsli.16	<illegal reg q15.5>, <illegal reg q8.5>, #8
│ │ -	vrsubhn.i32	d28, q12, q8
│ │ +	vmlsl.u16	q14, d24, d7[0]
│ │  	vmla.f16	<illegal reg q9.5>, q12, d2[1]
│ │ -			@ <UNDEFINED> instruction: 0xffd713e5
│ │ -	vqrdmulh.s16	<illegal reg q9.5>, q4, d3[0]
│ │ +	vraddhn.i32	d17, <illegal reg q3.5>, q6
│ │ +	vqrdmulh.s16	<illegal reg q9.5>, q4, d2[3]
│ │  	vsra.u16	<illegal reg q14.5>, q10, #8
│ │ -			@ <UNDEFINED> instruction: 0xffd73d2e
│ │ +			@ <UNDEFINED> instruction: 0xffd73d55
│ │  			@ <UNDEFINED> instruction: 0xffd8ba5b
│ │  	vsra.u64	d29, d3, #42
│ │  	vsri.64	d31, d5, #42
│ │ -			@ <UNDEFINED> instruction: 0xffd8dd9b
│ │ -	vrsubhn.i32	d26, q12, <illegal reg q0.5>
│ │ -	vqrdmlsh.s16	<illegal reg q8.5>, q4, d3[3]
│ │ +	vqrdmulh.s16	<illegal reg q14.5>, q12, d2[0]
│ │ +	vrsubhn.i32	d26, q12, q12
│ │ +			@ <UNDEFINED> instruction: 0xffd81f92
│ │  	vabdl.u16	q9, d24, d27
│ │ -			@ <UNDEFINED> instruction: 0xffd61d82
│ │ +			@ <UNDEFINED> instruction: 0xffd61da9
│ │  	vmlsl.u16	q12, d8, d9
│ │ -	vqrdmlsh.s16	q13, <illegal reg q3.5>, d3[2]
│ │ -	vmla.i16	q12, q4, d5[1]
│ │ -	vsubl.u16	<illegal reg q8.5>, d8, d8
│ │ +			@ <UNDEFINED> instruction: 0xffd7af8a
│ │ +	vshr.u16	q12, q10, #8
│ │ +	vsubl.u16	<illegal reg q8.5>, d8, d31
│ │  	vrsubhn.i32	d18, q12, q9
│ │  			@ <UNDEFINED> instruction: 0xffd60dae
│ │  	vrshr.u16	d23, d17, #9
│ │  			@ <UNDEFINED> instruction: 0xffd7890e
│ │  	vaddl.u16	q8, d7, d4
│ │  	b.n	316204 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a9980>
│ │  	movs	r0, r0
│ │ @@ -790046,15 +790046,15 @@
│ │  	b.n	316e98 <uniffi_pbcli_checksum_method_api_base@@Base+0x1aa614>
│ │  	movs	r0, r0
│ │  	b.n	31747c <uniffi_pbcli_checksum_method_api_base@@Base+0x1aabf8>
│ │  	asrs	r1, r0, #32
│ │  	b.n	317480 <uniffi_pbcli_checksum_method_api_base@@Base+0x1aabfc>
│ │  	bf	4, 30eb62 <uniffi_pbcli_checksum_method_api_base@@Base+0x1a22de>
│ │  	adds	r1, #65	@ 0x41
│ │ -	vmla.i16	q13, q11, d7[3]
│ │ +	vsra.u16	d26, d6, #10
│ │  			@ <UNDEFINED> instruction: 0xffd893ec
│ │  	vaddw.u16	<illegal reg q9.5>, q3, d5
│ │  			@ <UNDEFINED> instruction: 0xffd64c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	317898 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ab014>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3176c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1aae3e>
│ │ @@ -790620,15 +790620,15 @@
│ │  	b.n	317fbe <uniffi_pbcli_checksum_method_api_base@@Base+0x1ab73a>
│ │  	ands	r0, r0
│ │  	b.n	317fc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ab73e>
│ │  	ldc2l	11, cr14, [ip, #1016]!	@ 0x3f8	@ <UNPREDICTABLE>
│ │  	movs	r4, r0
│ │  	b.n	317bca <uniffi_pbcli_checksum_method_api_base@@Base+0x1ab346>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r3, r4, fp, sp}
│ │ +	ldmia.w	sp!, {r6, fp, sp}
│ │  	vshr.u16	d30, d9, #8
│ │  			@ <UNDEFINED> instruction: 0xffd84ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	317db8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ab534>
│ │  	beq.n	3178b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ab034>
│ │  	b.n	317d3c <uniffi_pbcli_checksum_method_api_base@@Base+0x1ab4b8>
│ │  	str	r0, [sp, #128]	@ 0x80
│ │ @@ -792536,15 +792536,15 @@
│ │  	strb	r4, [r3, #4]
│ │  	b.n	318434 <uniffi_pbcli_checksum_method_api_base@@Base+0x1abbb0>
│ │  	movs	r7, r0
│ │  	b.n	318c66 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ac3e2>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r3, r4, r6, r7, r9, fp, lr}
│ │  	movs	r4, r3
│ │ -	asrs	r5, r4, #30
│ │ +	asrs	r4, r1, #31
│ │  	vrsra.u64	<illegal reg q15.5>, q0, #40
│ │  			@ <UNDEFINED> instruction: 0xffd64ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	318e58 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ac5d4>
│ │  	beq.n	318948 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ac0c4>
│ │  	b.n	318ddc <uniffi_pbcli_checksum_method_api_base@@Base+0x1ac558>
│ │  	add	r0, pc, #12	@ (adr r0, 318950 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ac0cc>)
│ │ @@ -792847,15 +792847,15 @@
│ │  	b.n	3191e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ac95e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	318d04 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ac480>
│ │  	asrs	r0, r7, #2
│ │  	add.w	r0, r0, r1
│ │  	b.n	31932e <uniffi_pbcli_checksum_method_api_base@@Base+0x1acaaa>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r7, sl, ip}
│ │ +	ldmia.w	sp!, {r2, r6, r7, sl, ip}
│ │  			@ <UNDEFINED> instruction: 0xffd84bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	319118 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ac894>
│ │  	strh	r3, [r0, #0]
│ │  	b.n	318f42 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ac6be>
│ │  	str	r2, [r0, #0]
│ │  	b.n	318f46 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ac6c2>
│ │ @@ -793445,17 +793445,17 @@
│ │  	b.n	31960a <uniffi_pbcli_checksum_method_api_base@@Base+0x1acd86>
│ │  	lsls	r0, r2, #11
│ │  	b.n	318c0a <uniffi_pbcli_checksum_method_api_base@@Base+0x1ac386>
│ │  			@ <UNDEFINED> instruction: 0xffafeaff
│ │  	movs	r0, r0
│ │  	b.n	319846 <uniffi_pbcli_checksum_method_api_base@@Base+0x1acfc2>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r0, r4, r5, r6, r7, r9, ip}
│ │ -	vrshr.u64	<illegal reg q8.5>, <illegal reg q6.5>, #40
│ │ -			@ <UNDEFINED> instruction: 0xffd81349
│ │ +	ldmia.w	sp!, {r3, r4, r8, r9, ip}
│ │ +	vsubw.u16	<illegal reg q8.5>, q4, d4
│ │ +	vrsra.u16	<illegal reg q8.5>, q8, #8
│ │  			@ <UNDEFINED> instruction: 0xffd84bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	319638 <uniffi_pbcli_checksum_method_api_base@@Base+0x1acdb4>
│ │  	beq.n	319130 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ac8ac>
│ │  	b.n	3195bc <uniffi_pbcli_checksum_method_api_base@@Base+0x1acd38>
│ │  	str	r0, [sp, #8]
│ │  	b.n	319466 <uniffi_pbcli_checksum_method_api_base@@Base+0x1acbe2>
│ │ @@ -793559,15 +793559,15 @@
│ │  	movs	r0, r1
│ │  	b.n	31953e <uniffi_pbcli_checksum_method_api_base@@Base+0x1accba>
│ │  	beq.n	319230 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ac9ac>
│ │  	b.n	319698 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ace14>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r2, r4, r5, r7, r8, lr}
│ │  	movs	r4, r3
│ │ -	lsrs	r5, r4, #26
│ │ +	lsrs	r4, r1, #27
│ │  	vmull.u16	q12, d24, d1[1]
│ │  			@ <UNDEFINED> instruction: 0xffd74ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	319734 <uniffi_pbcli_checksum_method_api_base@@Base+0x1aceb0>
│ │  	beq.n	319244 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ac9c0>
│ │  	b.n	3196b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ace34>
│ │  	strh	r3, [r0, #0]
│ │ @@ -796858,19 +796858,19 @@
│ │  			@ <UNDEFINED> instruction: 0xebff87de
│ │  			@ <UNDEFINED> instruction: 0xebff7e3e
│ │  			@ <UNDEFINED> instruction: 0xebff4c10
│ │  	ldmia.w	sp!, {r0, r1, r3, r4, r6, r7, r8, r9, sl, pc}
│ │  			@ <UNDEFINED> instruction: 0xeaff2b6e
│ │  	vqshl.u16	d19, d19, #7
│ │  	vrshr.u16	d20, d22, #9
│ │ -	vsri.64	d23, d9, #41
│ │ -			@ <UNDEFINED> instruction: 0xffd80a91
│ │ +	vmls.i16	<illegal reg q11.5>, <illegal reg q11.5>, d0[0]
│ │ +			@ <UNDEFINED> instruction: 0xffd80ab8
│ │  			@ <UNDEFINED> instruction: 0xffd8f7e0
│ │  			@ <UNDEFINED> instruction: 0xffd59f94
│ │ -	vmlal.u16	q9, d6, d4[1]
│ │ +	vrshr.u16	q9, <illegal reg q9.5>, #10
│ │  			@ <UNDEFINED> instruction: 0xffd8abbb
│ │  	vaddl.u16	q8, d8, d4
│ │  	b.n	31a8c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ae044>
│ │  	movs	r0, r0
│ │  	b.n	31aeac <uniffi_pbcli_checksum_method_api_base@@Base+0x1ae628>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	add	r0, sl
│ │ @@ -797332,16 +797332,16 @@
│ │  			@ <UNDEFINED> instruction: 0xebfe4c10
│ │  	ldmia.w	sp!, {r0, r1, r3, r5, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeafe0004
│ │  	b.n	31b54a <uniffi_pbcli_checksum_method_api_base@@Base+0x1aecc6>
│ │  	ldr	r4, [pc, #64]	@ (31b24c <uniffi_pbcli_checksum_method_api_base@@Base+0x1ae9c8>)
│ │  	ldmia.w	sp!, {r1, r2, r3, r8, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeafe8c10
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r7, r9, fp, lr}
│ │ -	vmlal.u16	<illegal reg q11.5>, d24, d15
│ │ +	ldmia.w	sp!, {r1, r2, r6, r7, r9, fp, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffd878b6
│ │  	vshr.u64	q8, q8, #40
│ │  	movs	r0, r0
│ │  	lsls	r4, r2, #3
│ │  	movs	r0, r0
│ │  	lsls	r4, r0, #7
│ │  	movs	r0, r0
│ │  	ldr	r4, [pc, #64]	@ (31b26c <uniffi_pbcli_checksum_method_api_base@@Base+0x1ae9e8>)
│ │ @@ -799111,15 +799111,15 @@
│ │  	str	r0, [r0, #4]
│ │  	movs	r4, r3
│ │  	str	r4, [r5, #0]
│ │  	movs	r4, r3
│ │  	lsls	r1, r0, #11
│ │  	vaddw.u16	q8, q11, d9
│ │  	vmlsl.u16	<illegal reg q11.5>, d6, d7
│ │ -			@ <UNDEFINED> instruction: 0xffd66f57
│ │ +			@ <UNDEFINED> instruction: 0xffd66f7e
│ │  			@ <UNDEFINED> instruction: 0xffd81d5b
│ │  			@ <UNDEFINED> instruction: 0xffd719a0
│ │  	movs	r4, r3
│ │  	ldrsh	r0, [r6, r6]
│ │  	movs	r4, r3
│ │  	ldrsh	r0, [r1, r1]
│ │  	movs	r4, r3
│ │ @@ -799135,24 +799135,24 @@
│ │  	vshr.u16	q8, <illegal reg q4.5>, #11
│ │  			@ <UNDEFINED> instruction: 0xffd6fe99
│ │  	vshr.u16	d16, d17, #11
│ │  	vmlal.u16	<illegal reg q11.5>, d22, d18
│ │  	vqrdmlsh.s16	<illegal reg q15.5>, q3, d5[1]
│ │  			@ <UNDEFINED> instruction: 0xffd5fd75
│ │  	vqdmulh.s16	<illegal reg q15.5>, <illegal reg q2.5>, d5[2]
│ │ -	vaddw.u16	q12, <illegal reg q2.5>, d2
│ │ +	vaddw.u16	q12, <illegal reg q2.5>, d25
│ │  			@ <UNDEFINED> instruction: 0xffd8fdb9
│ │ -	vrshr.u16	q12, q3, #11
│ │ -	vmull.u16	<illegal reg q9.5>, d8, d3[3]
│ │ +	vrshr.u16	q12, <illegal reg q14.5>, #11
│ │ +			@ <UNDEFINED> instruction: 0xffd83a92
│ │  			@ <UNDEFINED> instruction: 0xffd8fb71
│ │ -	vaddl.u16	q12, d5, d14
│ │ +	vshr.u16	d24, d21, #11
│ │  			@ <UNDEFINED> instruction: 0xffd8fc19
│ │ -	vshr.u64	d24, d22, #43
│ │ +	vshr.u64	q12, <illegal reg q6.5>, #43
│ │  	vmull.u16	<illegal reg q15.5>, d24, d21
│ │ -	vmla.f16	q12, <illegal reg q2.5>, d2[0]
│ │ +	vmla.f16	q12, <illegal reg q2.5>, d1[3]
│ │  	vaddl.u16	q8, d8, d13
│ │  	vqrshrun.s32	d23, q15, #10
│ │  	vqrdmlsh.s16	<illegal reg q15.5>, q11, d1[2]
│ │  	vqrshrun.s32	d23, q1, #11
│ │  			@ <UNDEFINED> instruction: 0xffd6fe5d
│ │  	vmull.p<illegal width 16>	<illegal reg q15.5>, d5, d21
│ │  	vqshlu.s16	<illegal reg q11.5>, q15, #5
│ │ @@ -801784,45 +801784,45 @@
│ │  	movs	r4, r3
│ │  	str	r0, [r7, #112]	@ 0x70
│ │  	movs	r4, r3
│ │  	str	r0, [r7, #52]	@ 0x34
│ │  	movs	r4, r3
│ │  	str	r0, [r7, #56]	@ 0x38
│ │  	movs	r4, r3
│ │ -	bl	1888c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c03e>
│ │ +	bl	1af8c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x4303e>
│ │  	add	r4, pc, #232	@ (adr r4, 31da00 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b117c>)
│ │  	vrsubhn.i32	d22, q11, q14
│ │  	movs	r4, r3
│ │  	str	r0, [r5, #104]	@ 0x68
│ │  	movs	r4, r3
│ │  	str	r4, [r2, #104]	@ 0x68
│ │  	movs	r4, r3
│ │ -	ldrh	r0, [r0, #14]
│ │ +	ldrh	r7, [r4, #14]
│ │  	vrsubhn.i32	d26, <illegal reg q3.5>, q7
│ │ -	vmlal.u16	q14, d22, d25
│ │ +			@ <UNDEFINED> instruction: 0xffd6c8d0
│ │  	vsri.64	q13, q13, #41
│ │  	vsli.16	d29, d26, #6
│ │  	vmls.i16	q13, q11, d2[2]
│ │  	vqdmulh.s16	q12, q11, d0[3]
│ │  	vmls.i16	q13, q11, d2[1]
│ │ -	vmul.f16	q11, q3, d7[1]
│ │ +	vqrshrn.u32	d22, q11, #10
│ │  	vraddhn.i32	d26, q4, q9
│ │  	vrsubhn.i32	d17, q11, q4
│ │  	vsri.64	d26, d18, #41
│ │  			@ <UNDEFINED> instruction: 0xffd68cb8
│ │  	vsri.64	d26, d10, #42
│ │  	vsli.64	q10, <illegal reg q12.5>, #22
│ │  	vraddhn.i32	d26, q11, q1
│ │  	vmull.u16	q12, d22, d8
│ │  	vmls.i16	q13, q3, d2[3]
│ │  	vmls.f16	q10, q11, d1[1]
│ │  	vsri.16	q13, q1, #10
│ │ -	vmlal.u16	q9, d22, d0[2]
│ │ +	vsubw.u16	q9, q3, d7
│ │  	vraddhn.i32	d26, q4, q5
│ │ -			@ <UNDEFINED> instruction: 0xffd668f9
│ │ +			@ <UNDEFINED> instruction: 0xffd66920
│ │  	vrsra.u64	q13, q9, #40
│ │  			@ <UNDEFINED> instruction: 0xffd64ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	31dea8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b1624>
│ │  	beq.n	31d998 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b1114>
│ │  	b.n	31de2c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b15a8>
│ │  	movs	r1, #120	@ 0x78
│ │ @@ -802006,27 +802006,27 @@
│ │  	movs	r0, r0
│ │  	b.n	31dc28 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b13a4>
│ │  	asrs	r1, r0, #32
│ │  	b.n	31dc2c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b13a8>
│ │  	bvc.n	31dbe8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b1364>
│ │  			@ <UNDEFINED> instruction: 0xebff6074
│ │  	movs	r4, r3
│ │ -	add	sp, #416	@ 0x1a0
│ │ +	sub	sp, #60	@ 0x3c
│ │  	vrshr.u16	d26, d30, #9
│ │  			@ <UNDEFINED> instruction: 0xffd65fb4
│ │  	movs	r4, r3
│ │  	cbz	r6, 31db26 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b12a2>
│ │  	vsubl.u16	q13, d5, d22
│ │ -	vmls.f16	q12, q11, d0[0]
│ │ +	vmls.f16	q12, q11, d7[2]
│ │  	vsubl.u16	q13, d7, d14
│ │ -	vabal.u16	q14, d22, d21
│ │ +	vmls.f16	q14, q11, d4[1]
│ │  	vsra.u64	q13, q11, #41
│ │  	vrshr.u16	d29, d22, #10
│ │  	vsra.u64	q13, q7, #42
│ │ -	vmull.u16	q8, d22, d5[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd60af4
│ │  	vrshr.u16	q13, q3, #8
│ │  	vshr.u16	d19, d4, #10
│ │  	b.n	31d68c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b0e08>
│ │  	adds	r0, #3
│ │  	b.n	31dc70 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b13ec>
│ │  	adds	r0, #0
│ │  	b.n	31d6fc <uniffi_pbcli_checksum_method_api_base@@Base+0x1b0e78>
│ │ @@ -802872,45 +802872,45 @@
│ │  	movs	r0, r0
│ │  	b.n	31e35c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b1ad8>
│ │  	asrs	r1, r0, #32
│ │  	b.n	31e360 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b1adc>
│ │  	bpl.n	31e182 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b18fe>
│ │  			@ <UNDEFINED> instruction: 0xebff5d54
│ │  	movs	r4, r3
│ │ -	add	r1, sp, #688	@ 0x2b0
│ │ +	add	r1, sp, #844	@ 0x34c
│ │  			@ <UNDEFINED> instruction: 0xffd79b82
│ │  	vmull.u16	<illegal reg q10.5>, d22, d16
│ │  	movs	r4, r3
│ │  	ldrh	r4, [r5, r7]
│ │  	movs	r4, r3
│ │  	ldrh	r4, [r0, r5]
│ │  	movs	r4, r3
│ │  	ldrh	r4, [r5, r5]
│ │  	movs	r4, r3
│ │ -	add	r1, sp, #740	@ 0x2e4
│ │ +	add	r1, sp, #896	@ 0x380
│ │  			@ <UNDEFINED> instruction: 0xffd79bba
│ │  	vmul.f16	q13, q11, d2[0]
│ │  			@ <UNDEFINED> instruction: 0xffd59ada
│ │ -			@ <UNDEFINED> instruction: 0xffd67f54
│ │ +			@ <UNDEFINED> instruction: 0xffd67f7b
│ │  			@ <UNDEFINED> instruction: 0xffd79ba2
│ │ -			@ <UNDEFINED> instruction: 0xffd6bf19
│ │ +	vqrdmlsh.s16	<illegal reg q13.5>, q3, d0[0]
│ │  			@ <UNDEFINED> instruction: 0xffd79b6a
│ │  			@ <UNDEFINED> instruction: 0xffd6cbaa
│ │  			@ <UNDEFINED> instruction: 0xffd69b52
│ │ -	vrsra.u16	d16, d25, #10
│ │ +			@ <UNDEFINED> instruction: 0xffd60360
│ │  	vmull.u16	<illegal reg q12.5>, d24, d2[0]
│ │  	vrsra.u64	d27, d3, #42
│ │  			@ <UNDEFINED> instruction: 0xffd69b3a
│ │ -	vmul.i16	q13, q11, d2[3]
│ │ +	vqshrn.u32	d26, <illegal reg q0.5>, #10
│ │  			@ <UNDEFINED> instruction: 0xffd79b22
│ │ -	vshr.u16	d22, d15, #10
│ │ +	vmla.i16	q11, q3, d6[0]
│ │  			@ <UNDEFINED> instruction: 0xffd89af2
│ │ -			@ <UNDEFINED> instruction: 0xffd6a8d2
│ │ +			@ <UNDEFINED> instruction: 0xffd6a8f9
│ │  			@ <UNDEFINED> instruction: 0xffd79b0a
│ │ -	vqrshrun.s32	d26, q9, #10
│ │ +			@ <UNDEFINED> instruction: 0xffd6a899
│ │  	vmlsl.u16	<illegal reg q12.5>, d23, d26
│ │  			@ <UNDEFINED> instruction: 0xffd64c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	31e7dc <uniffi_pbcli_checksum_method_api_base@@Base+0x1b1f58>
│ │  	movs	r0, r0
│ │  	b.n	31e966 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b20e2>
│ │  	movs	r6, r5
│ │ @@ -803125,17 +803125,17 @@
│ │  	movs	r0, r0
│ │  	b.n	31e5a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b1d24>
│ │  	asrs	r1, r0, #32
│ │  	b.n	31e5ac <uniffi_pbcli_checksum_method_api_base@@Base+0x1b1d28>
│ │  	bpl.n	31e4a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b1c24>
│ │  			@ <UNDEFINED> instruction: 0xebff5650
│ │  	movs	r4, r3
│ │ -	ldrb	r0, [r0, #17]
│ │ +	ldrb	r7, [r4, #17]
│ │  	vmlal.u16	<illegal reg q12.5>, d23, d14
│ │ -	vmull.u16	<illegal reg q13.5>, d6, d21
│ │ +	vqdmulh.s16	<illegal reg q13.5>, q3, d4[1]
│ │  	vqrshrun.s32	d25, q11, #9
│ │  			@ <UNDEFINED> instruction: 0xffd6c8b6
│ │  	vqrshrun.s32	d25, q7, #10
│ │  	vshr.u64	d28, d5, #42
│ │  	vmlal.u16	<illegal reg q12.5>, d21, d22
│ │  	vmlal.u16	q10, d6, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │ @@ -803375,17 +803375,17 @@
│ │  	movs	r0, r0
│ │  	b.n	31e7d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b1f50>
│ │  	asrs	r1, r0, #32
│ │  	b.n	31e7d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b1f54>
│ │  	bmi.n	31e5be <uniffi_pbcli_checksum_method_api_base@@Base+0x1b1d3a>
│ │  			@ <UNDEFINED> instruction: 0xebff5424
│ │  	movs	r4, r3
│ │ -	ldrb	r4, [r2, #8]
│ │ +	ldrb	r3, [r7, #8]
│ │  	vmlsl.u16	<illegal reg q12.5>, d7, d2[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd6b9f9
│ │ +	vmlsl.u16	<illegal reg q13.5>, d6, d16
│ │  	vmlsl.u16	<illegal reg q12.5>, d7, d2[1]
│ │  	vrsubhn.i32	d28, q11, q5
│ │  	vqshlu.s16	d25, d18, #6
│ │  	vabdl.u16	q14, d6, d6
│ │  	vqshlu.s16	<illegal reg q12.5>, q13, #6
│ │  			@ <UNDEFINED> instruction: 0xffd64c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │ @@ -804077,20 +804077,20 @@
│ │  	b.n	31f422 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2b9e>
│ │  	asrs	r4, r6, #1
│ │  	b.n	31f426 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2ba2>
│ │  	movs	r0, #0
│ │  	b.n	31f42a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2ba6>
│ │  	b.n	31eeb0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b262c>
│ │  			@ <UNDEFINED> instruction: 0xebfeffd9
│ │ -			@ <UNDEFINED> instruction: 0xeaff55eb
│ │ -	vmlsl.u16	q12, d24, d21
│ │ -	vsli.64	d21, d31, #23
│ │ -			@ <UNDEFINED> instruction: 0xffd88a79
│ │ -	vsli.64	d21, d3, #23
│ │ -	vmull.u16	q12, d8, d5[1]
│ │ +			@ <UNDEFINED> instruction: 0xeaff5612
│ │ +	vmull.u16	q12, d24, d4[1]
│ │ +	vmls.f16	<illegal reg q10.5>, <illegal reg q11.5>, d6[2]
│ │ +	vmlsl.u16	q12, d24, d16
│ │ +	vsli.64	d21, d26, #23
│ │ +			@ <UNDEFINED> instruction: 0xffd88a74
│ │  			@ <UNDEFINED> instruction: 0xffd74bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	31f22c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b29a8>
│ │  	beq.n	31ed24 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b24a0>
│ │  	b.n	31f1b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b292c>
│ │  	strh	r2, [r0, #0]
│ │  	b.n	31f05a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b27d6>
│ │ @@ -804206,18 +804206,18 @@
│ │  	b.n	31ef28 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b26a4>
│ │  	strh.w	lr, [pc, #-3071]	@ 31e20d <uniffi_pbcli_checksum_method_api_base@@Base+0x1b1989>
│ │  	movs	r4, r0
│ │  	b.n	31f152 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b28ce>
│ │  	beq.n	31ee44 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b25c0>
│ │  	b.n	31f2ac <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2a28>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r7, sl, ip, lr}
│ │ -	vrsra.u16	d23, d15, #8
│ │ -	vsli.16	d21, d15, #7
│ │ -	vsri.16	<illegal reg q10.5>, <illegal reg q5.5>, #8
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r6, r7, sl, ip, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffd87346
│ │ +	vmls.f16	<illegal reg q10.5>, <illegal reg q3.5>, d6[0]
│ │ +	vraddhn.i32	d21, q12, q1
│ │  	vshr.u16	d18, d26, #8
│ │  	b.n	31f56e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2cea>
│ │  			@ <UNDEFINED> instruction: 0xffb5eaff
│ │  	movs	r0, r0
│ │  	b.n	31f4d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2c54>
│ │  	movs	r7, r4
│ │  	lsrs	r0, r0, #8
│ │ @@ -804341,19 +804341,19 @@
│ │  	movs	r1, r0
│ │  	asrs	r0, r0, #9
│ │  	asrs	r0, r0, #32
│ │  	b.n	31eabe <uniffi_pbcli_checksum_method_api_base@@Base+0x1b223a>
│ │  	movs	r0, r1
│ │  	b.n	31f282 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b29fe>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r1, sl, ip, lr}
│ │ -	vrshr.u16	d24, d7, #8
│ │ -	vrsra.u64	d21, d31, #41
│ │ +	ldmia.w	sp!, {r1, r3, r5, sl, ip, lr}
│ │ +	vrshr.u16	d24, d30, #8
│ │ +			@ <UNDEFINED> instruction: 0xffd753e6
│ │  	vqshlu.s64	d23, d5, #24
│ │ -	vrsra.u16	<illegal reg q10.5>, <illegal reg q13.5>, #10
│ │ +	vsubw.u16	<illegal reg q10.5>, q11, d18
│ │  	vshr.u16	d18, d26, #8
│ │  	b.n	31f69e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2e1a>
│ │  			@ <UNDEFINED> instruction: 0xffb3eaff
│ │  	ldr	r4, [pc, #448]	@ (31f124 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b28a0>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	31f484 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2c00>
│ │  	str	r0, [r0, r0]
│ │ @@ -804479,15 +804479,15 @@
│ │  	adds	r0, #1
│ │  	b.n	31ebfa <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2376>
│ │  	asrs	r0, r0, #32
│ │  	b.n	31ebfe <uniffi_pbcli_checksum_method_api_base@@Base+0x1b237a>
│ │  	movs	r2, r0
│ │  	b.n	31f7c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2f3e>
│ │  	vrhadd.u16	d14, d14, d31
│ │ -	strh	r3, [r4, #4]
│ │ +	strh	r2, [r1, #6]
│ │  			@ <UNDEFINED> instruction: 0xffd74c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	31f5ac <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2d28>
│ │  	ands	r1, r0
│ │  	b.n	31f3d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2b52>
│ │  	b.n	31eb22 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b229e>
│ │  	add.w	r0, r5, r0
│ │ @@ -805413,15 +805413,15 @@
│ │  	b.n	31ff62 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b36de>
│ │  	lsls	r3, r6, #5
│ │  	add.w	r0, r0, r0
│ │  	b.n	31feca <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3646>
│ │  	str	r0, [r0, #0]
│ │  	lsls	r0, r4, #14
│ │  			@ <UNDEFINED> instruction: 0xfff5eaff
│ │ -	str	r3, [sp, #916]	@ 0x394
│ │ +	str	r4, [sp, #48]	@ 0x30
│ │  			@ <UNDEFINED> instruction: 0xffd74c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	31fd58 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b34d4>
│ │  	beq.n	31f850 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2fcc>
│ │  	b.n	31fcdc <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3458>
│ │  	str	r0, [r0, r0]
│ │  	b.n	31fb86 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3302>
│ │ @@ -805507,15 +805507,15 @@
│ │  	ands	r1, r0
│ │  	b.n	32002e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b37aa>
│ │  	movs	r4, r0
│ │  	b.n	31fc32 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b33ae>
│ │  	beq.n	31f914 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3090>
│ │  	b.n	31fd8c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3508>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r7, r9, ip, pc}
│ │ +	ldmia.w	sp!, {r5, r6, r7, r9, ip, pc}
│ │  	vshr.u16	d17, d4, #9
│ │  	b.n	31f422 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2b9e>
│ │  	movs	r0, r0
│ │  	b.n	31ffa8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3724>
│ │  	movs	r0, #0
│ │  	asrs	r1, r2, #22
│ │  	movs	r0, r0
│ │ @@ -805726,16 +805726,16 @@
│ │  	b.n	31fbe0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b335c>
│ │  	bfcsel	14, 31f2c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2a3e>, 16, eq
│ │  	str	r0, [r0, r0]
│ │  	b.n	32020a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3986>
│ │  	str	r4, [r2, r0]
│ │  	b.n	31f5d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2d52>
│ │  			@ <UNDEFINED> instruction: 0xffe2eaff
│ │ -	str	r1, [sp, #84]	@ 0x54
│ │ -	vshr.u16	<illegal reg q12.5>, <illegal reg q8.5>, #9
│ │ +	str	r1, [sp, #240]	@ 0xf0
│ │ +	vshr.u64	d25, d8, #41
│ │  			@ <UNDEFINED> instruction: 0xffd74c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	31fffc <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3778>
│ │  	movs	r0, r0
│ │  	b.n	320188 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3904>
│ │  	ands	r0, r0
│ │  	b.n	31fe2a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b35a6>
│ │ @@ -805775,15 +805775,15 @@
│ │  	movs	r0, r0
│ │  	b.n	3201d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3952>
│ │  	movs	r4, r2
│ │  	b.n	31f642 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2dbe>
│ │  	movs	r1, r0
│ │  	asrs	r0, r0, #12
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r3, r5, ip, pc}
│ │ +	ldmia.w	sp!, {r4, r6, ip, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd74c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	320068 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b37e4>
│ │  	beq.n	31fb60 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b32dc>
│ │  	b.n	31ffec <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3768>
│ │  	movs	r0, r0
│ │  	b.n	3201f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3974>
│ │ @@ -805895,16 +805895,16 @@
│ │  	b.n	320376 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3af2>
│ │  	ands	r4, r2
│ │  	b.n	31f744 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2ec0>
│ │  			@ <UNDEFINED> instruction: 0xffe2eaff
│ │  	ands	r0, r0
│ │  	b.n	320382 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3afe>
│ │  			@ <UNDEFINED> instruction: 0xffe0eaff
│ │ -	ldrh	r5, [r5, #60]	@ 0x3c
│ │ -			@ <UNDEFINED> instruction: 0xffd78f05
│ │ +	ldrh	r4, [r2, #62]	@ 0x3e
│ │ +			@ <UNDEFINED> instruction: 0xffd78f2c
│ │  	vaddl.u16	q8, d7, d0
│ │  	b.n	3202f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3a70>
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (31fc9c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3418>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │ @@ -805942,15 +805942,15 @@
│ │  	movs	r0, r0
│ │  	b.n	320346 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3ac2>
│ │  	movs	r4, r2
│ │  	b.n	31f7b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2f2e>
│ │  	movs	r1, r0
│ │  	asrs	r0, r0, #12
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r5, r7, r9, sl, fp, pc}
│ │ +	ldmia.w	sp!, {r2, r5, r6, r7, r9, sl, fp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd74c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3201d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3954>
│ │  	stmia	r0!, {r2, r5, r6}
│ │  	b.n	31f800 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2f7c>
│ │  	ands	r0, r0
│ │  	b.n	320006 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3782>
│ │ @@ -805998,15 +805998,15 @@
│ │  	movs	r0, r0
│ │  	b.n	3203be <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3b3a>
│ │  	movs	r4, r2
│ │  	b.n	31f82a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2fa6>
│ │  	movs	r1, r0
│ │  	asrs	r0, r0, #12
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r6, r9, sl, fp, pc}
│ │ +	ldmia.w	sp!, {r2, r4, r5, r6, r9, sl, fp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd74c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	320250 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b39cc>
│ │  	ands	r0, r0
│ │  	b.n	32007a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b37f6>
│ │  	asrs	r4, r0, #1
│ │  	b.n	31f87c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b2ff8>
│ │ @@ -806040,15 +806040,15 @@
│ │  	movs	r0, r0
│ │  	b.n	32041a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3b96>
│ │  	movs	r4, r2
│ │  	b.n	31f886 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3002>
│ │  	movs	r1, r0
│ │  	asrs	r0, r0, #12
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r2, r5, r6, r7, r8, sl, fp, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r9, sl, fp, pc}
│ │  	vshr.u16	d16, d4, #9
│ │  	b.n	31f8ae <uniffi_pbcli_checksum_method_api_base@@Base+0x1b302a>
│ │  	movs	r0, r0
│ │  	b.n	320432 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3bae>
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	asrs	r0, r2, #32
│ │ @@ -806409,15 +806409,15 @@
│ │  	asrs	r0, r0, #32
│ │  	b.n	31fc12 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b338e>
│ │  			@ <UNDEFINED> instruction: 0xffb59aff
│ │  			@ <UNDEFINED> instruction: 0xffbeeaff
│ │  	str	r0, [r0, #0]
│ │  	b.n	3207de <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3f5a>
│ │  			@ <UNDEFINED> instruction: 0xffbceaff
│ │ -	ldrh	r1, [r5, #28]
│ │ +	ldrh	r0, [r2, #30]
│ │  			@ <UNDEFINED> instruction: 0xffd74c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3205c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3d44>
│ │  	asrs	r4, r2, #32
│ │  	b.n	31fbd2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b334e>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3207f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3f72>
│ │ @@ -806460,15 +806460,15 @@
│ │  	str	r6, [r0, r0]
│ │  	b.n	32044a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3bc6>
│ │  	movs	r4, r2
│ │  	b.n	31fc16 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3392>
│ │  	movs	r5, r0
│ │  	b.n	320452 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3bce>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r9, fp, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r6, r9, fp, pc}
│ │  	vqshrun.s32	d20, q8, #9
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	32063c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3db8>
│ │  	ands	r0, r0
│ │  	b.n	320466 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3be2>
│ │  	movs	r4, r2
│ │  	b.n	31fc4a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b33c6>
│ │ @@ -806508,15 +806508,15 @@
│ │  	asrs	r0, r1, #32
│ │  	b.n	31fc72 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b33ee>
│ │  	movs	r0, #12
│ │  	b.n	31fc76 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b33f2>
│ │  	movs	r5, r0
│ │  	b.n	3204ba <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3c36>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r5, r6, r7, r8, fp, pc}
│ │ +	ldmia.w	sp!, {r2, r4, r9, fp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd74df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3206a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3e20>
│ │  	beq.n	32019c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3918>
│ │  	b.n	320628 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3da4>
│ │  	str	r0, [r1, r0]
│ │  	b.n	31fcc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3444>
│ │ @@ -806978,15 +806978,15 @@
│ │  	b.n	320c9a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b4416>
│ │  	mcr2	11, 1, lr, cr5, cr15, {7}	@ <UNPREDICTABLE>
│ │  	movs	r0, r0
│ │  	b.n	320c02 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b437e>
│ │  	str	r0, [r0, r0]
│ │  	lsls	r0, r4, #14
│ │  			@ <UNDEFINED> instruction: 0xfff5eaff
│ │ -	strh	r1, [r2, #54]	@ 0x36
│ │ +	strh	r0, [r7, #54]	@ 0x36
│ │  	vaddl.u16	q8, d7, d0
│ │  	b.n	320c14 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b4390>
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	movs	r4, r1
│ │  	asrs	r0, r2, #22
│ │  	movs	r0, r0
│ │ @@ -807058,15 +807058,15 @@
│ │  	b.n	32094a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b40c6>
│ │  			@ <UNDEFINED> instruction: 0xfff81aff
│ │  	movs	r0, r0
│ │  	b.n	320d52 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b44ce>
│ │  	movs	r4, r2
│ │  	b.n	32011e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b389a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r6, r8, sl, pc}
│ │ +	ldmia.w	sp!, {r3, r5, r6, r8, sl, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd748f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	320b40 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b42bc>
│ │  	beq.n	320638 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b3db4>
│ │  	b.n	320ac4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b4240>
│ │  	str	r0, [r0, #0]
│ │  	b.n	32096e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b40ea>
│ │ @@ -807671,20 +807671,20 @@
│ │  	beq.n	320ba8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b4324>
│ │  	b.n	321008 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b4784>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {pc}
│ │  	b.n	3212ba <uniffi_pbcli_checksum_method_api_base@@Base+0x1b4a36>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │  	ldrh	r6, [r6, #26]
│ │ -	vmla.f16	<illegal reg q15.5>, q11, d7[3]
│ │ +	vrshr.u16	d31, d6, #10
│ │  	vrsra.u16	q13, q14, #9
│ │  			@ <UNDEFINED> instruction: 0xffd68b2a
│ │ -	vaddw.u16	<illegal reg q15.5>, q11, d19
│ │ +	vmla.f16	<illegal reg q15.5>, q11, d2[1]
│ │  			@ <UNDEFINED> instruction: 0xffd78ade
│ │ -	vsra.u16	<illegal reg q15.5>, <illegal reg q3.5>, #10
│ │ +	vsra.u16	<illegal reg q15.5>, q15, #10
│ │  	vmlsl.u16	q12, d23, d10
│ │  	vshll.u16	q12, d2, #6
│ │  			@ <UNDEFINED> instruction: 0xffd648f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3210c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b4840>
│ │  	beq.n	320bbc <uniffi_pbcli_checksum_method_api_base@@Base+0x1b4338>
│ │  	b.n	321048 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b47c4>
│ │ @@ -808476,16 +808476,16 @@
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r2, r3, ip, lr}
│ │  	b.n	320db2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b452e>
│ │  	asrs	r4, r0, #32
│ │  	b.n	3215f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b4d72>
│ │  	ldr	r0, [pc, #192]	@ (321378 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b4af4>)
│ │  	ldmia.w	sp!, {r4, r5, r6, r8, sl}
│ │ -	and.w	pc, r0, r2, ror #11
│ │ -			@ <UNDEFINED> instruction: 0xffd84e5f
│ │ +	and.w	r0, r0, r9, lsr #12
│ │ +	vmull.p<illegal width 16>	q10, d24, d6
│ │  			@ <UNDEFINED> instruction: 0xffd74c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3217e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b4f64>
│ │  	ands	r3, r0
│ │  	b.n	321612 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b4d8e>
│ │  	movs	r0, r0
│ │  	b.n	321976 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b50f2>
│ │ @@ -808974,30 +808974,30 @@
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │  	stmia	r1!, {r5, r6, r7}
│ │  	movs	r0, r0
│ │  			@ <UNDEFINED> instruction: 0xffc0ffff
│ │  	rors	r7, r3
│ │ -	b.n	3214e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b4c5e>
│ │ -			@ <UNDEFINED> instruction: 0xffd78bab
│ │ -	vmlsl.u16	q15, d7, d3[3]
│ │ -			@ <UNDEFINED> instruction: 0xffd78b4b
│ │ -	vsli.16	d30, d19, #7
│ │ -	vshll.u16	q12, d3, #7
│ │ -	vmls.f16	q15, <illegal reg q11.5>, d3[0]
│ │ -	vmlsl.u16	q12, d23, d19
│ │ -	vsri.64	q15, <illegal reg q5.5>, #41
│ │ -			@ <UNDEFINED> instruction: 0xffd789bb
│ │ -	vsli.16	d30, d7, #7
│ │ -			@ <UNDEFINED> instruction: 0xffd789f7
│ │ -	vmls.f16	q15, <illegal reg q3.5>, d7[3]
│ │ -	vmull.u16	q12, d7, d7[1]
│ │ -	vabal.u16	q15, d23, d23
│ │ -	vmlsl.u16	q12, d23, d7
│ │ +	b.n	321530 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b4cac>
│ │ +			@ <UNDEFINED> instruction: 0xffd78bd2
│ │ +	vqshlu.s64	d30, d2, #23
│ │ +			@ <UNDEFINED> instruction: 0xffd78b72
│ │ +	vsli.16	q15, q5, #7
│ │ +	vshll.u16	q12, d26, #7
│ │ +	vmls.f16	q15, <illegal reg q11.5>, d2[3]
│ │ +	vmull.u16	q12, d23, d2[1]
│ │ +	vabal.u16	q15, d7, d2
│ │ +	vmul.f16	q12, <illegal reg q11.5>, d2[2]
│ │ +	vsli.16	d30, d30, #7
│ │ +	vshll.u16	q12, d14, #7
│ │ +	vsli.64	d30, d6, #23
│ │ +			@ <UNDEFINED> instruction: 0xffd78a76
│ │ +	vmls.f16	q15, <illegal reg q11.5>, d6[1]
│ │ +	vmlsl.u16	q12, d23, d30
│ │  			@ <UNDEFINED> instruction: 0xffd7ffff
│ │  			@ <UNDEFINED> instruction: 0xeaff4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	321cb0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b542c>
│ │  	beq.n	3217a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b4f24>
│ │  	b.n	321c34 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b53b0>
│ │  	movs	r0, r0
│ │ @@ -809186,20 +809186,20 @@
│ │  			@ <UNDEFINED> instruction: 0xebfe4000
│ │  	b.n	322076 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b57f2>
│ │  	movs	r7, r1
│ │  	b.n	32207a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b57f6>
│ │  	asrs	r2, r0, #2
│ │  	b.n	32207e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b57fa>
│ │  			@ <UNDEFINED> instruction: 0xffb6eaff
│ │ -	b.n	322132 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b58ae>
│ │ -	vmlsl.u16	q9, d23, d3
│ │ -	vrshr.u64	q15, <illegal reg q1.5>, #40
│ │ -	vqrshrn.u32	d18, <illegal reg q7.5>, #9
│ │ -	vsubw.u16	q15, q4, d27
│ │ -			@ <UNDEFINED> instruction: 0xffd729b7
│ │ +	b.n	321180 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b48fc>
│ │ +	vmlsl.u16	q9, d23, d26
│ │ +	vrshr.u64	q15, q13, #40
│ │ +			@ <UNDEFINED> instruction: 0xffd72986
│ │ +	vrsra.u16	q15, q1, #8
│ │ +			@ <UNDEFINED> instruction: 0xffd729de
│ │  	vmlal.u16	q10, d8, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	321ca2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b541e>
│ │  	stmia	r0!, {}
│ │  	b.n	322126 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b58a2>
│ │  	b.n	321970 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b50ec>
│ │  	b.n	3220aa <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5826>
│ │ @@ -809470,29 +809470,29 @@
│ │  	b.n	322312 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5a8e>
│ │  	asrs	r5, r7, #1
│ │  	b.n	322316 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5a92>
│ │  			@ <UNDEFINED> instruction: 0xff92eaff
│ │  	movs	r0, r0
│ │  			@ <UNDEFINED> instruction: 0xffe0ffff
│ │  	rors	r7, r5
│ │ -	b.n	32207a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b57f6>
│ │ +	b.n	3220c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5844>
│ │  			@ <UNDEFINED> instruction: 0xffd7be51
│ │ -	vmla.f16	q15, q11, d7[3]
│ │ +	vrshr.u16	d30, d6, #10
│ │  			@ <UNDEFINED> instruction: 0xffd7bdf5
│ │ -	vshr.u64	d30, d3, #42
│ │ +	vshr.u64	d30, d26, #42
│ │  			@ <UNDEFINED> instruction: 0xffd7bc99
│ │ -	vsra.u64	d30, d3, #42
│ │ +	vsra.u64	d30, d26, #42
│ │  			@ <UNDEFINED> instruction: 0xffd7bd99
│ │ -	vshr.u16	q15, <illegal reg q5.5>, #10
│ │ +	vaddl.u16	q15, d22, d2
│ │  	vqdmulh.s16	<illegal reg q13.5>, <illegal reg q3.5>, d1[2]
│ │ -	vmla.i16	q15, q11, d3[1]
│ │ +	vshr.u64	q15, q9, #42
│ │  			@ <UNDEFINED> instruction: 0xffd7bcd1
│ │ -	vshr.u64	q15, <illegal reg q11.5>, #42
│ │ +	vsra.u16	d30, d14, #10
│ │  			@ <UNDEFINED> instruction: 0xffd7bcfd
│ │ -	vaddw.u16	q15, q3, d31
│ │ +	vsra.u16	q15, q3, #10
│ │  			@ <UNDEFINED> instruction: 0xffd7bd35
│ │  			@ <UNDEFINED> instruction: 0xffd6ffff
│ │  			@ <UNDEFINED> instruction: 0xeaff4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	322148 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b58c4>
│ │  	beq.n	321c40 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b53bc>
│ │  	b.n	3220cc <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5848>
│ │ @@ -809694,21 +809694,21 @@
│ │  	b.n	322522 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5c9e>
│ │  	bmi.n	321d2c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b54a8>
│ │  			@ <UNDEFINED> instruction: 0xebfe0004
│ │  	b.n	32212a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b58a6>
│ │  	beq.n	321dfc <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5578>
│ │  	b.n	322284 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5a00>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r4, r6, r8, r9, sl, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r4, r5, r6, r8, r9, sl, fp, ip, lr, pc}
│ │  	vaddl.u16	q8, d7, d19
│ │ -			@ <UNDEFINED> instruction: 0xffd7de33
│ │ +			@ <UNDEFINED> instruction: 0xffd7de5a
│ │  			@ <UNDEFINED> instruction: 0xffd7ff03
│ │ -			@ <UNDEFINED> instruction: 0xffd6de5f
│ │ +	vmull.p<illegal width 16>	<illegal reg q14.5>, d22, d6
│ │  			@ <UNDEFINED> instruction: 0xffd7ff2f
│ │ -			@ <UNDEFINED> instruction: 0xffd6deb3
│ │ +			@ <UNDEFINED> instruction: 0xffd6deda
│ │  			@ <UNDEFINED> instruction: 0xffd7ff83
│ │  	vmlal.u16	q10, d6, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	32215a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b58d6>
│ │  	stmia	r0!, {}
│ │  	b.n	3225de <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5d5a>
│ │  	b.n	321e28 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b55a4>
│ │ @@ -809909,20 +809909,20 @@
│ │  	b.n	322712 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5e8e>
│ │  	movs	r0, #0
│ │  	b.n	322716 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5e92>
│ │  	bmi.n	322026 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b57a2>
│ │  			@ <UNDEFINED> instruction: 0xebfe0004
│ │  	b.n	32231e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5a9a>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r6, r8, sl, fp, ip, lr, pc}
│ │ -	vrsra.u64	q9, q8, #41
│ │ -			@ <UNDEFINED> instruction: 0xffd8dc3f
│ │ +	ldmia.w	sp!, {r1, r2, r4, r5, r6, r8, sl, fp, ip, lr, pc}
│ │ +	vsri.16	d18, d7, #9
│ │ +	vqdmulh.s16	<illegal reg q14.5>, q4, d6[2]
│ │  			@ <UNDEFINED> instruction: 0xffd738f5
│ │ -			@ <UNDEFINED> instruction: 0xffd8dcf7
│ │ -	vrsra.u64	d18, d8, #41
│ │ +			@ <UNDEFINED> instruction: 0xffd8dd1e
│ │ +	vrsra.u64	d18, d31, #41
│ │  			@ <UNDEFINED> instruction: 0xffd84bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	32251c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5c98>
│ │  	strb	r0, [r1, #0]
│ │  	b.n	321b26 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b52a2>
│ │  	movs	r0, #16
│ │  	b.n	321b0a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5286>
│ │ @@ -810071,17 +810071,17 @@
│ │  	b.n	322882 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5ffe>
│ │  	bcc.n	3220dc <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5858>
│ │  			@ <UNDEFINED> instruction: 0xebfe0006
│ │  	b.n	32248a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5c06>
│ │  	str	r0, [sp, #64]	@ 0x40
│ │  	b.n	321c56 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b53d2>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r0, r1, r4, r6, r7, r9, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r4, r5, r6, r7, r9, fp, ip, lr, pc}
│ │  	vabdl.u16	<illegal reg q9.5>, d23, d9
│ │ -			@ <UNDEFINED> instruction: 0xffd8db57
│ │ +			@ <UNDEFINED> instruction: 0xffd8db7e
│ │  	vmls.i16	q12, <illegal reg q3.5>, d2[3]
│ │  			@ <UNDEFINED> instruction: 0xffd54c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	322684 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5e00>
│ │  	ands	r0, r1
│ │  	b.n	321c8e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b540a>
│ │  	movs	r0, r0
│ │ @@ -810213,20 +810213,20 @@
│ │  			@ <UNDEFINED> instruction: 0xebfe4000
│ │  	b.n	3229ce <uniffi_pbcli_checksum_method_api_base@@Base+0x1b614a>
│ │  	movs	r7, r1
│ │  	b.n	3229d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b614e>
│ │  	asrs	r6, r7, #1
│ │  	b.n	3229d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6152>
│ │  			@ <UNDEFINED> instruction: 0xffe2eaff
│ │ -	bge.n	322322 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5a9e>
│ │ -	vabal.u16	<illegal reg q12.5>, d23, d24
│ │ -	vqrshrn.u32	d29, <illegal reg q13.5>, #9
│ │ +	bge.n	322370 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5aec>
│ │ +	vmls.f16	<illegal reg q12.5>, <illegal reg q11.5>, d7[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd7d9a2
│ │  	vqshlu.s16	d19, d17, #7
│ │ -	vmul.f16	<illegal reg q14.5>, q12, d3[3]
│ │ -	vsli.16	<illegal reg q12.5>, q0, #7
│ │ +	vshll.u16	<illegal reg q14.5>, d2, #8
│ │ +	vsli.16	<illegal reg q12.5>, <illegal reg q11.5>, #7
│ │  			@ <UNDEFINED> instruction: 0xffd748f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3227d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5f50>
│ │  	strb	r0, [r1, #0]
│ │  	b.n	321dde <uniffi_pbcli_checksum_method_api_base@@Base+0x1b555a>
│ │  	movs	r0, #16
│ │  	b.n	321dc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b553e>
│ │ @@ -810369,17 +810369,17 @@
│ │  	str	r1, [r0, #0]
│ │  	b.n	322b32 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b62ae>
│ │  	movs	r6, r0
│ │  	b.n	322736 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5eb2>
│ │  	str	r0, [r2, r0]
│ │  	b.n	321f02 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b567e>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r7, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r5, r6, r7, fp, ip, lr, pc}
│ │  	vsli.16	<illegal reg q9.5>, <illegal reg q10.5>, #7
│ │ -	vmul.i16	<illegal reg q14.5>, q4, d3[2]
│ │ +	vmlal.u16	<illegal reg q14.5>, d24, d10
│ │  	vsubl.u16	<illegal reg q11.5>, d7, d1
│ │  	vmlal.u16	q10, d6, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	322756 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5ed2>
│ │  	stmia	r0!, {}
│ │  	b.n	322bda <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6356>
│ │  	b.n	322424 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5ba0>
│ │ @@ -810656,27 +810656,27 @@
│ │  	b.n	322dd2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b654e>
│ │  			@ <UNDEFINED> instruction: 0xff96eaff
│ │  	blx	722cd8 <uniffi_pbcli_checksum_method_api_base@@Base+0x5b6454>
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │  	mvns	r0, r6
│ │ -	bvc.n	3225ca <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5d46>
│ │ +	bvc.n	322618 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5d94>
│ │  	vshr.u64	d24, d0, #41
│ │ -	vabdl.u16	<illegal reg q14.5>, d5, d19
│ │ +			@ <UNDEFINED> instruction: 0xffd5d74a
│ │  	vaddl.u16	q12, d7, d16
│ │ -	vsli.64	d29, d11, #21
│ │ +	vmls.f16	<illegal reg q14.5>, <illegal reg q10.5>, d2[0]
│ │  			@ <UNDEFINED> instruction: 0xffd77e98
│ │ -	vsli.16	<illegal reg q14.5>, <illegal reg q15.5>, #5
│ │ +	vabal.u16	<illegal reg q14.5>, d21, d22
│ │  			@ <UNDEFINED> instruction: 0xffd77e7c
│ │ -	vsli.64	<illegal reg q14.5>, <illegal reg q9.5>, #21
│ │ +	vqshlu.s16	d29, d10, #5
│ │  			@ <UNDEFINED> instruction: 0xffd77ef0
│ │ -	vqshlu.s16	d29, d15, #5
│ │ +	vmlsl.u16	<illegal reg q14.5>, d5, d6[0]
│ │  			@ <UNDEFINED> instruction: 0xffd77f1c
│ │ -	vqshlu.s16	<illegal reg q14.5>, <illegal reg q7.5>, #5
│ │ +	vrsubhn.i32	d29, <illegal reg q10.5>, q3
│ │  			@ <UNDEFINED> instruction: 0xffd77f5c
│ │  	vmlal.u16	q10, d5, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	322a22 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b619e>
│ │  	stmia	r0!, {}
│ │  	b.n	322ea6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6622>
│ │  	b.n	3226f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5e74>
│ │ @@ -810841,19 +810841,19 @@
│ │  	b.n	322978 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b60f4>
│ │  	bne.n	3227ee <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5f6a>
│ │  			@ <UNDEFINED> instruction: 0xebfe1003
│ │  	b.n	322e62 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b65de>
│ │  	asrs	r0, r1, #32
│ │  	b.n	322ee6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6662>
│ │  			@ <UNDEFINED> instruction: 0xffcceaff
│ │ -	bmi.n	32294a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b60c6>
│ │ +	bmi.n	322798 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b5f14>
│ │  	vmls.i16	q9, <illegal reg q11.5>, d7[0]
│ │ -	vrsra.u64	<illegal reg q14.5>, <illegal reg q1.5>, #42
│ │ +	vrsra.u64	<illegal reg q14.5>, q13, #42
│ │  	vraddhn.i32	d18, <illegal reg q3.5>, <illegal reg q13.5>
│ │ -	vsubw.u16	<illegal reg q14.5>, q11, d23
│ │ +			@ <UNDEFINED> instruction: 0xffd6d3ce
│ │  	vrsra.u64	q9, <illegal reg q15.5>, #41
│ │  			@ <UNDEFINED> instruction: 0xffd648f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	322da4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6520>
│ │  	str	r2, [r0, #16]
│ │  	b.n	322e8e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b660a>
│ │  	movs	r0, r0
│ │ @@ -810996,15 +810996,15 @@
│ │  	b.n	322fbe <uniffi_pbcli_checksum_method_api_base@@Base+0x1b673a>
│ │  			@ <UNDEFINED> instruction: 0xffdeeaff
│ │  	str	r1, [r0, #8]
│ │  	b.n	323106 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6882>
│ │  	add	r6, lr
│ │  	b.n	322fca <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6746>
│ │  			@ <UNDEFINED> instruction: 0xffdbeaff
│ │ -	bcs.n	322926 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b60a2>
│ │ +	bcs.n	322974 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b60f0>
│ │  			@ <UNDEFINED> instruction: 0xffd76c37
│ │  	vmlal.u16	q10, d6, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	322d1e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b649a>
│ │  	b.n	3229e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6160>
│ │  	b.n	323122 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b689e>
│ │  	ands	r2, r0
│ │ @@ -811088,15 +811088,15 @@
│ │  	b.n	3231d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b694e>
│ │  	bne.n	322b84 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6300>
│ │  			@ <UNDEFINED> instruction: 0xebfe0006
│ │  	b.n	322dda <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6556>
│ │  	beq.n	322abc <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6238>
│ │  	b.n	322f34 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b66b0>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r7, r8, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r5, r7, r8, ip, lr, pc}
│ │  	vmull.u16	q8, d7, d7[0]
│ │  			@ <UNDEFINED> instruction: 0xffd74bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	322fcc <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6748>
│ │  	movs	r0, r0
│ │  	b.n	323156 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b68d2>
│ │  	movs	r5, r4
│ │ @@ -811272,22 +811272,22 @@
│ │  	ldmia	r0, {r0, r1, r3, r6}
│ │  			@ <UNDEFINED> instruction: 0xfa050004
│ │  	b.n	322f6e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b66ea>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	323376 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6af2>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r7, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r5, r7, ip, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd7dc1a
│ │ -	vmla.i16	<illegal reg q14.5>, <illegal reg q2.5>, d7[2]
│ │ +	vaddl.u16	<illegal reg q14.5>, d21, d14
│ │  			@ <UNDEFINED> instruction: 0xffd7dbea
│ │ -	vaddl.u16	<illegal reg q14.5>, d5, d31
│ │ +	vshr.u16	<illegal reg q14.5>, q3, #11
│ │  			@ <UNDEFINED> instruction: 0xffd7dbb2
│ │ -			@ <UNDEFINED> instruction: 0xffd5cfff
│ │ -	vmla.i16	<illegal reg q14.5>, <illegal reg q11.5>, d3[0]
│ │ +	vaddl.u16	<illegal reg q14.5>, d5, d22
│ │ +	vmla.i16	<illegal reg q14.5>, <illegal reg q11.5>, d2[3]
│ │  	vqdmulh.s16	<illegal reg q14.5>, <illegal reg q3.5>, d6[0]
│ │  	vmlal.u16	q10, d5, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	322fa6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6722>
│ │  	beq.n	322c78 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b63f4>
│ │  	b.n	323104 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6880>
│ │  	movs	r0, #4
│ │ @@ -811366,17 +811366,17 @@
│ │  	b.n	323392 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6b0e>
│ │  	movs	r0, #0
│ │  	b.n	323456 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6bd2>
│ │  	beq.n	322cc6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6442>
│ │  			@ <UNDEFINED> instruction: 0xebfe0000
│ │  	b.n	32345e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6bda>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r8, r9, sl, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r6, r8, r9, sl, fp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd72bb6
│ │ -			@ <UNDEFINED> instruction: 0xffd8ceff
│ │ +			@ <UNDEFINED> instruction: 0xffd8cf26
│ │  			@ <UNDEFINED> instruction: 0xffd72b9a
│ │  			@ <UNDEFINED> instruction: 0xffd848f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	323254 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b69d0>
│ │  	str	r0, [r0, #0]
│ │  	b.n	32307e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b67fa>
│ │  	movs	r0, #16
│ │ @@ -811464,18 +811464,18 @@
│ │  	asrs	r0, r0, #32
│ │  	strh	r0, [r4, #28]
│ │  	asrs	r5, r0, #32
│ │  	strh	r0, [r0, #62]	@ 0x3e
│ │  	movs	r4, r0
│ │  	b.n	32313e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b68ba>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r6, r9, sl, fp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd749a9
│ │ -			@ <UNDEFINED> instruction: 0xffd7ce77
│ │ -			@ <UNDEFINED> instruction: 0xffd749d5
│ │ +	ldmia.w	sp!, {r1, r4, r5, r6, r9, sl, fp, lr, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffd749d0
│ │ +			@ <UNDEFINED> instruction: 0xffd7ce9e
│ │ +			@ <UNDEFINED> instruction: 0xffd749fc
│ │  	vmlal.u16	q10, d7, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	32315a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b68d6>
│ │  	movs	r0, r0
│ │  	b.n	3234be <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6c3a>
│ │  	movs	r6, r0
│ │  	lsrs	r0, r0, #8
│ │ @@ -811523,17 +811523,17 @@
│ │  	b.n	323502 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6c7e>
│ │  	movs	r0, #0
│ │  	b.n	3235c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6d42>
│ │  	beq.n	322f7e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b66fa>
│ │  			@ <UNDEFINED> instruction: 0xebfe0000
│ │  	b.n	3235ce <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6d4a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r5, r7, r8, sl, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r4, r6, r7, r8, sl, fp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd78eb5
│ │ -			@ <UNDEFINED> instruction: 0xffd5cd8f
│ │ +			@ <UNDEFINED> instruction: 0xffd5cdb6
│ │  			@ <UNDEFINED> instruction: 0xffd78e99
│ │  			@ <UNDEFINED> instruction: 0xffd54c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3233c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6b40>
│ │  	str	r2, [r0, r0]
│ │  	b.n	3231ee <uniffi_pbcli_checksum_method_api_base@@Base+0x1b696a>
│ │  	str	r1, [r0, #0]
│ │ @@ -811651,18 +811651,18 @@
│ │  	b.n	3236ee <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6e6a>
│ │  	movs	r0, #0
│ │  	b.n	3236f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6e6e>
│ │  	beq.n	323014 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6790>
│ │  			@ <UNDEFINED> instruction: 0xebfe0004
│ │  	b.n	3232fa <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6a76>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r7, sl, fp, lr, pc}
│ │ -	vqdmulh.s16	q14, <illegal reg q11.5>, d3[1]
│ │ -	vqdmulh.s16	q14, <illegal reg q3.5>, d3[2]
│ │ -	vqdmulh.s16	q14, <illegal reg q3.5>, d7[3]
│ │ +	ldmia.w	sp!, {r1, r2, r5, r6, r7, sl, fp, lr, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffd7ccf2
│ │ +	vmull.u16	q14, d23, d10
│ │ +			@ <UNDEFINED> instruction: 0xffd7cc96
│ │  	vaddl.u16	<illegal reg q9.5>, d7, d7
│ │  	b.n	323712 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6e8e>
│ │  			@ <UNDEFINED> instruction: 0xffcfeaff
│ │  	ldr	r0, [pc, #192]	@ (323098 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6814>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3234f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6c74>
│ │  	movs	r0, r0
│ │ @@ -811744,17 +811744,17 @@
│ │  	b.n	3237c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6f42>
│ │  	movs	r0, #0
│ │  	b.n	3237ca <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6f46>
│ │  	ldmia	r7, {r1, r3, r4, r5, r6, r7}
│ │  			@ <UNDEFINED> instruction: 0xebfe0005
│ │  	b.n	3233d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6b4e>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r5, r7, r8, r9, fp, lr, pc}
│ │ -	vmlsl.u16	q10, d23, d4[3]
│ │ -			@ <UNDEFINED> instruction: 0xffd7cb8b
│ │ +	ldmia.w	sp!, {r1, r5, r6, r7, r8, r9, fp, lr, pc}
│ │ +	vqshl.u16	d20, d3, #7
│ │ +			@ <UNDEFINED> instruction: 0xffd7cbb2
│ │  	vsli.16	d16, d4, #7
│ │  			@ <UNDEFINED> instruction: 0xffd64c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3235c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6d44>
│ │  	movs	r0, r0
│ │  	b.n	323752 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6ece>
│ │  	movs	r1, r1
│ │ @@ -811819,17 +811819,17 @@
│ │  	b.n	323876 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6ff2>
│ │  	movs	r0, #0
│ │  	b.n	32387a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6ff6>
│ │  	ldmia	r7, {r1, r2, r3, r6, r7}
│ │  			@ <UNDEFINED> instruction: 0xebfe0004
│ │  	b.n	323482 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6bfe>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r8, r9, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r4, r5, r8, r9, fp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd78c31
│ │ -			@ <UNDEFINED> instruction: 0xffd5cadb
│ │ +			@ <UNDEFINED> instruction: 0xffd5cb02
│ │  	vmls.i16	q8, <illegal reg q3.5>, d4[2]
│ │  	vmlal.u16	q10, d6, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	32349e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6c1a>
│ │  	b.n	32316c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b68e8>
│ │  	b.n	3238a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b701e>
│ │  	ands	r2, r0
│ │ @@ -811947,15 +811947,15 @@
│ │  	strb	r4, [r1, #0]
│ │  	b.n	322d7c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b64f8>
│ │  	mrc2	11, 0, lr, cr0, cr15, {7}	@ <UNPREDICTABLE>
│ │  	movs	r0, r0
│ │  	b.n	32390a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7086>
│ │  			@ <UNDEFINED> instruction: 0xffe81aff
│ │  			@ <UNDEFINED> instruction: 0xffd2eaff
│ │ -	ldmia	r1, {r0, r1, r2, r4, r6, r7}
│ │ +	ldmia	r1, {r1, r2, r3, r4, r5, r6, r7}
│ │  			@ <UNDEFINED> instruction: 0xffd74bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	323798 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6f14>
│ │  	beq.n	323290 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6a0c>
│ │  	b.n	32371c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6e98>
│ │  	movs	r0, r0
│ │  	b.n	323926 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b70a2>
│ │ @@ -812089,17 +812089,17 @@
│ │  	str	r1, [r0, #0]
│ │  	b.n	323ae6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7262>
│ │  	str	r0, [sp, #0]
│ │  	b.n	322eb4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6630>
│ │  	movs	r0, r0
│ │  	b.n	322ebe <uniffi_pbcli_checksum_method_api_base@@Base+0x1b663a>
│ │  			@ <UNDEFINED> instruction: 0xffbceaff
│ │ -	ldmia	r0, {r0, r1, r2, r3, r4, r6, r7}
│ │ -	vmul.i16	q14, <illegal reg q3.5>, d3[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd7c897
│ │ +	ldmia	r1, {r1, r2}
│ │ +	vmlal.u16	q14, d23, d10
│ │ +			@ <UNDEFINED> instruction: 0xffd7c8be
│ │  			@ <UNDEFINED> instruction: 0xffd74bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3238e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b705c>
│ │  	beq.n	323408 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6b84>
│ │  	b.n	323864 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6fe0>
│ │  	str	r0, [sp, #12]
│ │  	b.n	32370e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6e8a>
│ │ @@ -812348,17 +812348,17 @@
│ │  	b.n	323d32 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b74ae>
│ │  	movs	r0, #0
│ │  	b.n	323d36 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b74b2>
│ │  	ldmia	r6!, {r0, r1, r2, r3, r4, r7}
│ │  			@ <UNDEFINED> instruction: 0xebfe0004
│ │  	b.n	32393e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b70ba>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r6, r9, sl, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r7, r9, sl, lr, pc}
│ │  	vshr.u16	d16, d1, #9
│ │ -	vqshlu.s16	d28, d15, #6
│ │ +	vmlsl.u16	q14, d6, d6[0]
│ │  			@ <UNDEFINED> instruction: 0xffd7ffb9
│ │  			@ <UNDEFINED> instruction: 0xffd548f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	323b34 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b72b0>
│ │  	ands	r2, r0
│ │  	b.n	32395e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b70da>
│ │  	str	r1, [r0, r0]
│ │ @@ -812498,17 +812498,17 @@
│ │  	b.n	323e8e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b760a>
│ │  	movs	r0, #0
│ │  	b.n	323e92 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b760e>
│ │  	ldmia	r6, {r3, r6}
│ │  			@ <UNDEFINED> instruction: 0xebfe0004
│ │  	b.n	323a9a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7216>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r2, r5, r8, sl, lr, pc}
│ │ -	vshr.u16	q10, q8, #9
│ │ -	vmls.i16	q14, <illegal reg q11.5>, d3[0]
│ │ +	ldmia.w	sp!, {r1, r2, r3, r6, r8, sl, lr, pc}
│ │ +	vshr.u64	d20, d7, #41
│ │ +	vmls.i16	q14, <illegal reg q11.5>, d2[3]
│ │  	vsra.u16	q9, <illegal reg q12.5>, #9
│ │  	vaddl.u16	q8, d8, d7
│ │  	b.n	323c72 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b73ee>
│ │  	lsls	r0, r4, #6
│ │  	b.n	323ab6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7232>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	adds	r0, #0
│ │ @@ -812558,16 +812558,16 @@
│ │  	b.n	323b22 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b729e>
│ │  	movs	r0, #234	@ 0xea
│ │  	b.n	323f26 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b76a2>
│ │  	asrs	r1, r0, #32
│ │  	b.n	323908 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7084>
│ │  	ldr	r4, [pc, #64]	@ (32382c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6fa8>)
│ │  	ldmia.w	sp!, {r1, r2, r4, r5, r7, r8, sl, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xeaff129a
│ │ -	vsubl.u16	<illegal reg q8.5>, d23, d6
│ │ +			@ <UNDEFINED> instruction: 0xeaff12c1
│ │ +	vsubl.u16	<illegal reg q8.5>, d23, d29
│ │  			@ <UNDEFINED> instruction: 0xffd74ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	323d1c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7498>
│ │  	beq.n	32382c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6fa8>
│ │  	b.n	323ca0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b741c>
│ │  	movs	r0, r0
│ │  	b.n	323eaa <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7626>
│ │ @@ -813001,21 +813001,21 @@
│ │  	b.n	324302 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7a7e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	323ce4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7460>
│ │  	b.n	323548 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b6cc4>
│ │  			@ <UNDEFINED> instruction: 0xebffffe9
│ │  			@ <UNDEFINED> instruction: 0xeaff208a
│ │  			@ <UNDEFINED> instruction: 0xffd88b15
│ │ -	vqshlu.s16	d25, d31, #6
│ │ +	vmlsl.u16	<illegal reg q12.5>, d6, d6[2]
│ │  	vmlsl.u16	q12, d7, d17
│ │ -	vmls.f16	<illegal reg q12.5>, q3, d3[1]
│ │ +	vsli.16	<illegal reg q12.5>, q9, #6
│ │  			@ <UNDEFINED> instruction: 0xffd78ad5
│ │ -	vsli.64	<illegal reg q12.5>, <illegal reg q15.5>, #22
│ │ +	vrsubhn.i32	d25, q3, q11
│ │  	vmlsl.u16	q12, d23, d25
│ │ -	vsli.64	<illegal reg q12.5>, <illegal reg q1.5>, #22
│ │ +	vsli.64	<illegal reg q12.5>, q13, #22
│ │  	vmul.f16	q12, <illegal reg q11.5>, d1[3]
│ │  	vqrshrun.s32	d24, <illegal reg q10.5>, #10
│ │  	vaddl.u16	q8, d6, d0
│ │  	b.n	32429e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7a1a>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (323c44 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b73c0>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │ @@ -813333,15 +813333,15 @@
│ │  	movs	r1, r0
│ │  	b.n	32461a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7d96>
│ │  	lsls	r2, r0, #1
│ │  	stmia.w	r4, {r3, ip, lr}
│ │  	b.n	3239ea <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7166>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r1, r3, r6, r7, r9, sl, sp, lr}
│ │ -	vmls.f16	<illegal reg q14.5>, <illegal reg q10.5>, d5[1]
│ │ +	vsli.64	<illegal reg q14.5>, q10, #21
│ │  	vqshlu.s16	q11, q15, #7
│ │  	vmlsl.u16	q11, d5, d6[2]
│ │  	vaddl.u16	<illegal reg q8.5>, d5, d12
│ │  	b.n	323a9a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7216>
│ │  	asrs	r1, r0, #32
│ │  	b.n	324600 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7d7c>
│ │  	asrs	r4, r1, #32
│ │ @@ -814022,26 +814022,26 @@
│ │  	b.n	324c1e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b839a>
│ │  	strh	r0, [r0, #0]
│ │  	b.n	324c22 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b839e>
│ │  	ldmia	r2, {r2, r5, r6, r7}
│ │  			@ <UNDEFINED> instruction: 0xebfeff8b
│ │  			@ <UNDEFINED> instruction: 0xeaffdb5f
│ │  	vmls.i16	q11, <illegal reg q10.5>, d6[0]
│ │ -	vqshl.u16	d23, d5, #5
│ │ -	vabal.u16	q13, d7, d22
│ │ +	vqshl.u16	d23, d28, #5
│ │ +	vmls.f16	q13, <illegal reg q3.5>, d5[1]
│ │  	vabal.u16	q11, d7, d22
│ │ -	vqshl.u16	<illegal reg q11.5>, <illegal reg q10.5>, #5
│ │ +	vqshl.u64	d23, d12, #21
│ │  	vmls.i16	q11, <illegal reg q3.5>, d6[1]
│ │ -	vqshlu.s64	d23, d13, #21
│ │ -	vmla.f16	q8, <illegal reg q11.5>, d4[1]
│ │ +	vmlsl.u16	<illegal reg q11.5>, d21, d4[0]
│ │ +	vsra.u64	q8, <illegal reg q9.5>, #41
│ │  	vsri.16	q11, q11, #8
│ │  			@ <UNDEFINED> instruction: 0xffd5ae39
│ │  	vrshr.u64	d22, d26, #42
│ │  			@ <UNDEFINED> instruction: 0xffd5ac7d
│ │ -	vmls.i16	q13, q3, d2[3]
│ │ +	vsri.64	d26, d1, #42
│ │  	vsubl.u16	q11, d23, d2
│ │  	vqdmulh.s16	q13, <illegal reg q2.5>, d5[0]
│ │  	vrsra.u64	d22, d22, #42
│ │  	vrshr.u16	d22, d18, #11
│ │  			@ <UNDEFINED> instruction: 0xffd5abf5
│ │  	vrsra.u16	q11, q5, #10
│ │  	vmlal.u16	q11, d21, d6[2]
│ │ @@ -814212,15 +814212,15 @@
│ │  	movs	r4, r5
│ │  	b.n	324e16 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8592>
│ │  	movs	r0, #39	@ 0x27
│ │  	b.n	324e1a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8596>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3247fc <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7f78>
│ │  	b.n	324920 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b809c>
│ │ -			@ <UNDEFINED> instruction: 0xeaff03a6
│ │ +			@ <UNDEFINED> instruction: 0xeaff03cd
│ │  			@ <UNDEFINED> instruction: 0xffd74c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	324c08 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8384>
│ │  	ands	r0, r0
│ │  	b.n	324a32 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b81ae>
│ │  	movs	r0, r1
│ │  	b.n	324216 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7992>
│ │ @@ -814231,15 +814231,15 @@
│ │  	b.n	324a42 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b81be>
│ │  	movs	r0, #47	@ 0x2f
│ │  	b.n	324e46 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b85c2>
│ │  	asrs	r1, r0, #32
│ │  	b.n	324828 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7fa4>
│ │  	ldr	r4, [pc, #64]	@ (32474c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7ec8>)
│ │  	ldmia.w	sp!, {r1, r2, r3, r5, r6, r7, r8, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xeaff037a
│ │ +			@ <UNDEFINED> instruction: 0xeaff03a1
│ │  			@ <UNDEFINED> instruction: 0xffd74c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	324c38 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b83b4>
│ │  	ands	r1, r0
│ │  	b.n	324a62 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b81de>
│ │  	str	r0, [r0, r0]
│ │  	b.n	324a66 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b81e2>
│ │ @@ -814356,16 +814356,16 @@
│ │  	b.n	324f66 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b86e2>
│ │  	asrs	r1, r0, #32
│ │  	b.n	324948 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b80c4>
│ │  	b.n	324b7a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b82f6>
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	324b72 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b82ee>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r4, r6, r8, r9, lr}
│ │ -	vrsra.u16	d20, d9, #9
│ │ +	ldmia.w	sp!, {r3, r4, r5, r6, r8, r9, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffd74340
│ │  			@ <UNDEFINED> instruction: 0xffd74c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	324d60 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b84dc>
│ │  	ands	r0, r0
│ │  	b.n	324b8a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8306>
│ │  	movs	r4, r0
│ │  	b.n	32436e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7aea>
│ │ @@ -814385,27 +814385,27 @@
│ │  	b.n	324fae <uniffi_pbcli_checksum_method_api_base@@Base+0x1b872a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	324990 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b810c>
│ │  	ldr	r4, [pc, #64]	@ (3248b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8030>)
│ │  	ldmia.w	sp!, {r2, r4, r7, r8, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeaff8ba8
│ │  	movs	r3, r3
│ │ -	cmn	r1, r2
│ │ +	cmn	r0, r7
│ │  	vshr.u16	d16, d0, #9
│ │  	b.n	3243c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7b40>
│ │  	movs	r0, #0
│ │  	b.n	324fca <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8746>
│ │  	asrs	r4, r1, #32
│ │  	b.n	3243cc <uniffi_pbcli_checksum_method_api_base@@Base+0x1b7b48>
│ │  	movs	r0, r0
│ │  	b.n	3249b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b812c>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3249b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8130>
│ │  	stmia	r0!, {r0, r3, r4, r6, r7}
│ │ -			@ <UNDEFINED> instruction: 0xeafd020a
│ │ +			@ <UNDEFINED> instruction: 0xeafd0231
│ │  	vaddl.u16	q8, d7, d8
│ │  	movs	r0, r0
│ │  	ldr	r7, [pc, #960]	@ (324c64 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b83e0>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	324dc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8540>
│ │  	beq.n	3248b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8030>
│ │  	b.n	324d48 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b84c4>
│ │ @@ -815151,27 +815151,27 @@
│ │  	b.n	32526e <uniffi_pbcli_checksum_method_api_base@@Base+0x1b89ea>
│ │  	beq.n	324f90 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b870c>
│ │  	b.n	3253c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8b44>
│ │  	ldrh	r4, [r0, #24]
│ │  	ldc	0, cr13, [sp], #16
│ │  	b.n	325454 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8bd0>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r6, sl, fp, ip, sp}
│ │ -	vmull.u16	<illegal reg q9.5>, d23, d12
│ │ -	vabdl.u16	<illegal reg q8.5>, d23, d18
│ │ +	ldmia.w	sp!, {r5, r7, sl, fp, ip, sp}
│ │ +			@ <UNDEFINED> instruction: 0xffd73cb3
│ │ +			@ <UNDEFINED> instruction: 0xffd717c9
│ │  			@ <UNDEFINED> instruction: 0xffd7e765
│ │  			@ <UNDEFINED> instruction: 0xffd65b46
│ │ -	vqrdmlsh.s16	<illegal reg q14.5>, <illegal reg q10.5>, d7[0]
│ │ -	vqrdmlah.s16	<illegal reg q9.5>, <illegal reg q11.5>, d1[0]
│ │ +	vqrdmlsh.s16	<illegal reg q14.5>, <illegal reg q10.5>, d6[3]
│ │ +	vqrdmlah.s16	<illegal reg q9.5>, <illegal reg q11.5>, d0[3]
│ │  	vmul.i16	<illegal reg q8.5>, <illegal reg q11.5>, d3[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd63d3d
│ │ -			@ <UNDEFINED> instruction: 0xffd73e5d
│ │ -			@ <UNDEFINED> instruction: 0xffd73e39
│ │ -			@ <UNDEFINED> instruction: 0xffd73c3d
│ │ -	vsra.u64	<illegal reg q8.5>, <illegal reg q11.5>, #41
│ │ +	vqrdmulh.s16	<illegal reg q9.5>, q3, d4[2]
│ │ +	vmull.p<illegal width 16>	<illegal reg q9.5>, d23, d4
│ │ +	vqrdmlah.s16	<illegal reg q9.5>, <illegal reg q3.5>, d0[2]
│ │ +	vqdmulh.s16	<illegal reg q9.5>, <illegal reg q3.5>, d4[2]
│ │ +	vrshr.u16	d17, d14, #9
│ │  			@ <UNDEFINED> instruction: 0xffd709a6
│ │  			@ <UNDEFINED> instruction: 0xffd84df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	325498 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8c14>
│ │  	strh	r0, [r0, #0]
│ │  	b.n	3252c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8a3e>
│ │  	movs	r0, r0
│ │ @@ -815393,32 +815393,32 @@
│ │  	b.n	32549a <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8c16>
│ │  	movs	r0, #2
│ │  	b.n	32527c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b89f8>
│ │  	stmia	r7!, {r0, r2, r6, r7}
│ │  			@ <UNDEFINED> instruction: 0xebfe0000
│ │  	b.n	3258a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b9022>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r9, fp, ip, sp}
│ │ +	ldmia.w	sp!, {r3, r5, r9, fp, ip, sp}
│ │  			@ <UNDEFINED> instruction: 0xffd7cba1
│ │  			@ <UNDEFINED> instruction: 0xffd66be2
│ │ -	vrsra.u64	q9, q10, #43
│ │ +	vsri.16	d18, d11, #11
│ │  	vaddl.u16	q13, d23, d8
│ │  	vsli.64	q15, <illegal reg q10.5>, #21
│ │  	vsli.64	d25, d11, #21
│ │  			@ <UNDEFINED> instruction: 0xffd63f14
│ │  	vmul.f16	<illegal reg q12.5>, q11, d0[3]
│ │ -	vshr.u64	<illegal reg q8.5>, <illegal reg q1.5>, #43
│ │ +	vshr.u64	<illegal reg q8.5>, q13, #43
│ │  			@ <UNDEFINED> instruction: 0xffd76c1e
│ │  	vrsra.u64	<illegal reg q11.5>, <illegal reg q1.5>, #42
│ │  	vqrdmlah.s16	<illegal reg q12.5>, q3, d2[2]
│ │  			@ <UNDEFINED> instruction: 0xffd6dda6
│ │  	vrsubhn.i32	d18, <illegal reg q10.5>, q4
│ │ -	vsli.16	<illegal reg q9.5>, q7, #6
│ │ +	vabal.u16	<illegal reg q9.5>, d22, d5
│ │  	vabdl.u16	q12, d7, d19
│ │ -	vmlsl.u16	<illegal reg q9.5>, d6, d25
│ │ +			@ <UNDEFINED> instruction: 0xffd63a50
│ │  			@ <UNDEFINED> instruction: 0xffd7cbc9
│ │  			@ <UNDEFINED> instruction: 0xffd64ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3256d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8e54>
│ │  	svc	133	@ 0x85
│ │  	b.n	32565c <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8dd8>
│ │  	asrs	r4, r1, #32
│ │ @@ -815641,15 +815641,15 @@
│ │  	b.n	3256f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8e6e>
│ │  	blx	2f29b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x186130>
│ │  	movs	r6, r0
│ │  	b.n	3256fa <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8e76>
│ │  	beq.n	3253f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8b70>
│ │  	b.n	325854 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8fd0>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r3, r7, fp, ip, sp}
│ │ +	ldmia.w	sp!, {r4, r5, r7, fp, ip, sp}
│ │  	vmlsl.u16	q11, d23, d25
│ │  			@ <UNDEFINED> instruction: 0xffd56b13
│ │  	vqshrun.s32	d20, q8, #11
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3258f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b906c>
│ │  	str	r0, [r7, r0]
│ │  	b.n	324f18 <uniffi_pbcli_checksum_method_api_base@@Base+0x1b8694>
│ │ @@ -818326,15 +818326,15 @@
│ │  	vrsra.u16	<illegal reg q13.5>, q1, #11
│ │  	vsubw.u16	<illegal reg q13.5>, <illegal reg q2.5>, d10
│ │  			@ <UNDEFINED> instruction: 0xffd59c12
│ │  	vmul.i16	<illegal reg q11.5>, <illegal reg q10.5>, d7[3]
│ │  	vmls.i16	q9, q11, d6[1]
│ │  	vabal.u16	<illegal reg q13.5>, d5, d18
│ │  	vmull.p<illegal width 16>	<illegal reg q12.5>, d5, d26
│ │ -	vqshl.u64	d31, d10, #21
│ │ +			@ <UNDEFINED> instruction: 0xffd5f7c1
│ │  			@ <UNDEFINED> instruction: 0xffd68e10
│ │  	movs	r0, r3
│ │  	push	{r1, r2, r4, r5, r6, r7, lr}
│ │  			@ <UNDEFINED> instruction: 0xffd59efe
│ │  			@ <UNDEFINED> instruction: 0xffd57bdb
│ │  	vsri.64	<illegal reg q13.5>, q1, #42
│ │  			@ <UNDEFINED> instruction: 0xffd54bf0
│ │ @@ -819623,17 +819623,17 @@
│ │  	b.n	3272b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1baa30>
│ │  	vmov.s16	lr, d18[1]
│ │  			@ <UNDEFINED> instruction: 0xffeeeaff
│ │  	movs	r1, r0
│ │  	b.n	327ed2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1bb64e>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r1, r2, r4, r7, r8, sl, fp, lr}
│ │ -	vrshr.u64	q12, <illegal reg q10.5>, #42
│ │ +	vrsra.u16	d24, d12, #10
│ │  	vabal.u16	<illegal reg q14.5>, d23, d5
│ │ -			@ <UNDEFINED> instruction: 0xffd529f0
│ │ +	vshll.u16	q9, d7, #5
│ │  	vaddl.u16	q8, d7, d24
│ │  	b.n	3272ca <uniffi_pbcli_checksum_method_api_base@@Base+0x1baa46>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	adds	r0, #1
│ │  	b.n	327af2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1bb26e>
│ │  	asrs	r2, r0, #32
│ │  	b.n	327af6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1bb272>
│ │ @@ -820517,23 +820517,23 @@
│ │  	movs	r0, r1
│ │  	b.n	3286c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1bbe42>
│ │  	movs	r0, #38	@ 0x26
│ │  	b.n	3286ca <uniffi_pbcli_checksum_method_api_base@@Base+0x1bbe46>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3280ac <uniffi_pbcli_checksum_method_api_base@@Base+0x1bb828>
│ │  	bcs.n	327f78 <uniffi_pbcli_checksum_method_api_base@@Base+0x1bb6f4>
│ │ -			@ <UNDEFINED> instruction: 0xeaffcb18
│ │ +			@ <UNDEFINED> instruction: 0xeaffcb3f
│ │  	vaddl.u16	<illegal reg q8.5>, d6, d8
│ │  	b.n	327ad8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1bb254>
│ │  	movs	r0, #44	@ 0x2c
│ │  	b.n	3286de <uniffi_pbcli_checksum_method_api_base@@Base+0x1bbe5a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3280c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1bb83c>
│ │  	bcc.n	327f36 <uniffi_pbcli_checksum_method_api_base@@Base+0x1bb6b2>
│ │ -			@ <UNDEFINED> instruction: 0xeaffcb04
│ │ +			@ <UNDEFINED> instruction: 0xeaffcb2b
│ │  	vqshrun.s32	d20, q8, #10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3284cc <uniffi_pbcli_checksum_method_api_base@@Base+0x1bbc48>
│ │  	str	r1, [r0, r0]
│ │  	b.n	3282f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1bba72>
│ │  	asrs	r4, r1, #32
│ │  	b.n	3286fa <uniffi_pbcli_checksum_method_api_base@@Base+0x1bbe76>
│ │ @@ -821781,15 +821781,15 @@
│ │  	str	r0, [r6, #12]
│ │  	b.n	328e56 <uniffi_pbcli_checksum_method_api_base@@Base+0x1bc5d2>
│ │  	beq.n	328af0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1bc26c>
│ │  	b.n	328f68 <uniffi_pbcli_checksum_method_api_base@@Base+0x1bc6e4>
│ │  	ldrh	r0, [r2, #38]	@ 0x26
│ │  	ldmia.w	sp!, {r0, r1, r5, r6, r9, sl, fp, lr, pc}
│ │  	vmul.f16	<illegal reg q9.5>, <illegal reg q11.5>, d2[3]
│ │ -	vqshrun.s32	d27, <illegal reg q12.5>, #10
│ │ +	vmul.i16	<illegal reg q13.5>, q3, d0[2]
│ │  			@ <UNDEFINED> instruction: 0xffd7ff1e
│ │  	b.n	328d44 <uniffi_pbcli_checksum_method_api_base@@Base+0x1bc4c0>
│ │  	movs	r0, r0
│ │  	b.n	32922a <uniffi_pbcli_checksum_method_api_base@@Base+0x1bc9a6>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r0, [pc, #0]	@ (328af0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1bc26c>)
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │ @@ -839560,28 +839560,28 @@
│ │  	b.n	332472 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c5bee>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r4, r6, r9, fp, ip}
│ │  	movs	r3, r3
│ │  	ldc2	15, cr15, [ip], {255}	@ 0xff
│ │  	subs	r0, r7, r0
│ │  	movs	r3, r3
│ │ -	strh	r4, [r3, #6]
│ │ +	strh	r3, [r0, #8]
│ │  			@ <UNDEFINED> instruction: 0xffd619f4
│ │  	movs	r3, r3
│ │ -	strh	r4, [r3, #0]
│ │ +	strh	r3, [r0, #2]
│ │  	vmul.f16	<illegal reg q8.5>, q11, d4[2]
│ │  	movs	r3, r3
│ │  	adds	r0, r1, r7
│ │  	movs	r3, r3
│ │  	adds	r0, r5, r6
│ │  	movs	r3, r3
│ │ -	strh	r0, [r7, #0]
│ │ +	strh	r7, [r3, #2]
│ │  	vqrshrn.u32	d17, q0, #10
│ │  	movs	r3, r3
│ │ -	ldrb	r4, [r5, #31]
│ │ +	strh	r3, [r2, #0]
│ │  	vqshrn.u32	d17, q6, #10
│ │  	movs	r3, r3
│ │  	ldr	r4, [pc, #448]	@ (33232c <uniffi_pbcli_checksum_method_api_base@@Base+0x1c5aa8>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	33268c <uniffi_pbcli_checksum_method_api_base@@Base+0x1c5e08>
│ │  	beq.n	332194 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c5910>
│ │  	b.n	332610 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c5d8c>
│ │ @@ -839702,15 +839702,15 @@
│ │  	movs	r3, r3
│ │  	adds	r4, r5, r1
│ │  	movs	r3, r3
│ │  	adds	r0, r2, r1
│ │  	movs	r3, r3
│ │  	adds	r0, r6, r0
│ │  	movs	r3, r3
│ │ -	ldrb	r0, [r0, #27]
│ │ +	ldrb	r7, [r4, #27]
│ │  			@ <UNDEFINED> instruction: 0xffd617e8
│ │  	movs	r3, r3
│ │  	ldr	r0, [pc, #0]	@ (33228c <uniffi_pbcli_checksum_method_api_base@@Base+0x1c5a08>)
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3325d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c5d4e>
│ │  	beq.n	3322b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c5a30>
│ │  	b.n	332730 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c5eac>
│ │ @@ -839893,15 +839893,15 @@
│ │  	asrs	r0, r1, #32
│ │  	b.n	331f5c <uniffi_pbcli_checksum_method_api_base@@Base+0x1c56d8>
│ │  	cmp	r7, #91	@ 0x5b
│ │  	b.n	332b62 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c62de>
│ │  	asrs	r1, r0, #32
│ │  	b.n	332544 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c5cc0>
│ │  	add	r2, sp, #672	@ 0x2a0
│ │ -			@ <UNDEFINED> instruction: 0xeaff7ce0
│ │ +			@ <UNDEFINED> instruction: 0xeaff7d07
│ │  			@ <UNDEFINED> instruction: 0xffd64c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	332950 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c60cc>
│ │  	ands	r0, r0
│ │  	b.n	33277a <uniffi_pbcli_checksum_method_api_base@@Base+0x1c5ef6>
│ │  	lsls	r0, r1, #1
│ │  	b.n	331f7c <uniffi_pbcli_checksum_method_api_base@@Base+0x1c56f8>
│ │ @@ -840309,21 +840309,21 @@
│ │  	asrs	r4, r5, #19
│ │  	movs	r0, r0
│ │  	asrs	r4, r6, #13
│ │  	movs	r3, r3
│ │  	asrs	r0, r4, #12
│ │  	movs	r3, r3
│ │  	b.n	332908 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c6084>
│ │ -			@ <UNDEFINED> instruction: 0xffd4ed33
│ │ +			@ <UNDEFINED> instruction: 0xffd4ed5a
│ │  	vsubw.u16	<illegal reg q8.5>, q3, d8
│ │  	movs	r3, r3
│ │  	asrs	r4, r2, #11
│ │  	movs	r3, r3
│ │  	b.n	3327f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c5f6c>
│ │ -			@ <UNDEFINED> instruction: 0xffd4ec9f
│ │ +	vqdmulh.s16	q15, q10, d6[0]
│ │  	vrshr.u64	<illegal reg q8.5>, q8, #42
│ │  	movs	r3, r3
│ │  	ldr	r0, [pc, #0]	@ (3327ec <uniffi_pbcli_checksum_method_api_base@@Base+0x1c5f68>)
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	332b32 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c62ae>
│ │  			@ <UNDEFINED> instruction: 0xff96ebff
│ │  	movs	r0, r0
│ │ @@ -843154,19 +843154,19 @@
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r2}
│ │  	b.n	3343da <uniffi_pbcli_checksum_method_api_base@@Base+0x1c7b56>
│ │  	blx	36c894 <uniffi_pbcli_checksum_method_api_base@@Base+0x200010>
│ │  	movs	r4, r0
│ │  	b.n	3343e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c7b5e>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r6, r7, r8, ip, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r5, r6, r7, r8, ip, pc}
│ │  	vmla.i16	<illegal reg q10.5>, q3, d6[1]
│ │ -	vmlal.u16	<illegal reg q12.5>, d4, d5[1]
│ │ -	vrshr.u16	d25, d9, #10
│ │ -	vsra.u64	<illegal reg q12.5>, <illegal reg q8.5>, #42
│ │ +	vrshr.u16	<illegal reg q12.5>, q10, #12
│ │ +	vmlal.u16	<illegal reg q12.5>, d6, d0[0]
│ │ +	vrshr.u16	d25, d8, #10
│ │  	vaddl.u16	<illegal reg q9.5>, d6, d12
│ │  	b.n	333be0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c735c>
│ │  	movs	r0, #12
│ │  	b.n	333be2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c735e>
│ │  	adds	r0, #3
│ │  	b.n	33416a <uniffi_pbcli_checksum_method_api_base@@Base+0x1c78e6>
│ │  	movs	r3, r0
│ │ @@ -844506,44 +844506,44 @@
│ │  	b.n	33533a <uniffi_pbcli_checksum_method_api_base@@Base+0x1c8ab6>
│ │  	movs	r5, r1
│ │  	b.n	3353fe <uniffi_pbcli_checksum_method_api_base@@Base+0x1c8b7a>
│ │  	movs	r0, #0
│ │  	b.n	335402 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c8b7e>
│ │  	ldrh	r4, [r5, #6]
│ │  			@ <UNDEFINED> instruction: 0xebfeffc9
│ │ -			@ <UNDEFINED> instruction: 0xeaffb659
│ │ +			@ <UNDEFINED> instruction: 0xeaffb680
│ │  	vshr.u16	d28, d28, #10
│ │ -	vabdl.u16	<illegal reg q13.5>, d5, d17
│ │ +			@ <UNDEFINED> instruction: 0xffd5b748
│ │  	vaddw.u16	q14, q3, d4
│ │ -	vqshlu.s16	d27, d13, #5
│ │ +	vmlsl.u16	<illegal reg q13.5>, d5, d4[0]
│ │  	vaddl.u16	q14, d6, d0
│ │ -	vsli.16	<illegal reg q13.5>, <illegal reg q2.5>, #5
│ │ +	vsli.16	<illegal reg q13.5>, q14, #5
│ │  			@ <UNDEFINED> instruction: 0xffd6bf38
│ │ -	vmls.i16	<illegal reg q13.5>, <illegal reg q2.5>, d5[0]
│ │ +	vmls.i16	<illegal reg q13.5>, <illegal reg q2.5>, d4[3]
│ │  	vmull.p<illegal width 16>	<illegal reg q13.5>, d6, d24
│ │ -			@ <UNDEFINED> instruction: 0xffd5b34d
│ │ +	vrsra.u16	<illegal reg q13.5>, q10, #11
│ │  			@ <UNDEFINED> instruction: 0xffd6bd30
│ │  	vmlal.u16	q14, d5, d5
│ │  	vrsubhn.i32	d24, <illegal reg q2.5>, q14
│ │ -			@ <UNDEFINED> instruction: 0xffd5b369
│ │ +	vrsra.u64	d27, d0, #43
│ │  	vqrdmulh.s16	<illegal reg q13.5>, q3, d4[1]
│ │ -	vsli.16	<illegal reg q13.5>, <illegal reg q14.5>, #5
│ │ +	vabal.u16	<illegal reg q13.5>, d21, d20
│ │  	vqrdmlsh.s16	<illegal reg q13.5>, q3, d0[2]
│ │ -	vsri.64	d27, d25, #43
│ │ +	vmls.i16	<illegal reg q13.5>, <illegal reg q10.5>, d0[2]
│ │  			@ <UNDEFINED> instruction: 0xffd6be9c
│ │ -	vqshlu.s64	d27, d5, #21
│ │ +	vqshlu.s64	d27, d28, #21
│ │  	vshr.u16	q14, q12, #10
│ │  	vqshrn.u32	d29, <illegal reg q11.5>, #11
│ │ -	vraddhn.i32	d27, q10, <illegal reg q0.5>
│ │ +	vraddhn.i32	d27, q10, q12
│ │  	vqrdmlah.s16	<illegal reg q13.5>, q3, d4[2]
│ │ -	vraddhn.i32	d27, <illegal reg q2.5>, <illegal reg q12.5>
│ │ +	vsri.16	<illegal reg q13.5>, q0, #11
│ │  	vmull.p<illegal width 16>	<illegal reg q13.5>, d6, d12
│ │ -			@ <UNDEFINED> instruction: 0xffd5b3c5
│ │ +			@ <UNDEFINED> instruction: 0xffd5b3ec
│ │  			@ <UNDEFINED> instruction: 0xffd6bda8
│ │ -			@ <UNDEFINED> instruction: 0xffd5b3ed
│ │ +	vsri.16	d27, d4, #11
│ │  	vmlal.u16	q10, d6, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	33508a <uniffi_pbcli_checksum_method_api_base@@Base+0x1c8806>
│ │  	beq.n	334d5c <uniffi_pbcli_checksum_method_api_base@@Base+0x1c84d8>
│ │  	b.n	3351e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c8964>
│ │  	stmia	r0!, {r0}
│ │  	b.n	335092 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c880e>
│ │ @@ -844724,16 +844724,16 @@
│ │  	ldmia.w	sp!, {r2}
│ │  	b.n	335222 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c899e>
│ │  	beq.n	334f04 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c8680>
│ │  	b.n	33537c <uniffi_pbcli_checksum_method_api_base@@Base+0x1c8af8>
│ │  	ldr	r0, [pc, #960]	@ (3352a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c8a24>)
│ │  	ldmia.w	sp!, {r2, r4, r6, r7, sl, fp, pc}
│ │  	and.w	r3, r5, r5, asr #14
│ │ -	vmla.f16	<illegal reg q13.5>, <illegal reg q2.5>, d0[2]
│ │ -	vqshl.u16	d31, d30, #6
│ │ +	vaddw.u16	<illegal reg q13.5>, <illegal reg q10.5>, d7
│ │ +			@ <UNDEFINED> instruction: 0xffd6f765
│ │  	vqshrun.s32	d20, q8, #10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	33541c <uniffi_pbcli_checksum_method_api_base@@Base+0x1c8b98>
│ │  	beq.n	334f24 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c86a0>
│ │  	b.n	3353a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c8b1c>
│ │  	stmia	r0!, {r3}
│ │  	b.n	334a40 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c81bc>
│ │ @@ -845371,42 +845371,42 @@
│ │  			@ <UNDEFINED> instruction: 0xebff8001
│ │  	b.n	335bca <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9346>
│ │  	movs	r0, r1
│ │  	b.n	3357ce <uniffi_pbcli_checksum_method_api_base@@Base+0x1c8f4a>
│ │  	beq.n	3354c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c8c44>
│ │  	b.n	335928 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c90a4>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r2, r5, r7, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r6, r7, ip, sp, pc}
│ │  	vrsra.u64	d23, d24, #42
│ │  	vshr.u16	d29, d7, #11
│ │ -	vrsra.u16	d21, d22, #11
│ │ -	vrshr.u16	<illegal reg q8.5>, q5, #10
│ │ -	vsubl.u16	<illegal reg q8.5>, d6, d26
│ │ +	vrsra.u16	<illegal reg q10.5>, <illegal reg q6.5>, #11
│ │ +	vsubl.u16	<illegal reg q8.5>, d22, d1
│ │ +	vrshr.u16	<illegal reg q8.5>, <illegal reg q0.5>, #10
│ │  	vaddw.u16	q11, q11, d31
│ │  	vqrdmlsh.s16	<illegal reg q10.5>, <illegal reg q2.5>, d7[1]
│ │  			@ <UNDEFINED> instruction: 0xffd58b8f
│ │ -	vsli.16	<illegal reg q15.5>, <illegal reg q13.5>, #5
│ │ +	vabal.u16	<illegal reg q15.5>, d21, d18
│ │  	vsubl.u16	q13, d6, d14
│ │  	vrshr.u16	d29, d3, #11
│ │  			@ <UNDEFINED> instruction: 0xffd4ffba
│ │  			@ <UNDEFINED> instruction: 0xffd45890
│ │  	vmla.f16	<illegal reg q14.5>, q10, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffd40b83
│ │  			@ <UNDEFINED> instruction: 0xffd70b63
│ │ -			@ <UNDEFINED> instruction: 0xffd753ec
│ │ -			@ <UNDEFINED> instruction: 0xffd628f3
│ │ -	vrsra.u64	d21, d28, #42
│ │ -	vmlal.u16	<illegal reg q8.5>, d22, d6[1]
│ │ -	vsubw.u16	<illegal reg q10.5>, q11, d4
│ │ -	vrshr.u64	d17, d10, #42
│ │ -	vmull.u16	q13, d6, d20
│ │ -			@ <UNDEFINED> instruction: 0xffd6aba4
│ │ -			@ <UNDEFINED> instruction: 0xffd6ab88
│ │ -	vmull.u16	q13, d22, d0
│ │ -			@ <UNDEFINED> instruction: 0xffd6abec
│ │ +	vsri.16	d21, d3, #9
│ │ +	vqshrn.u32	d18, q5, #10
│ │ +			@ <UNDEFINED> instruction: 0xffd653e3
│ │ +	vrshr.u64	<illegal reg q8.5>, <illegal reg q10.5>, #42
│ │ +	vsubw.u16	<illegal reg q10.5>, q11, d27
│ │ +	vmlal.u16	<illegal reg q8.5>, d22, d1[0]
│ │ +	vqdmulh.s16	q13, q3, d3[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd6abcb
│ │ +			@ <UNDEFINED> instruction: 0xffd6abaf
│ │ +	vmull.u16	q13, d22, d23
│ │ +			@ <UNDEFINED> instruction: 0xffd6ac13
│ │  	vqshrun.s32	d20, q8, #10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	335a28 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c91a4>
│ │  	beq.n	335530 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c8cac>
│ │  	b.n	3359ac <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9128>
│ │  	stmia	r0!, {r3}
│ │  	b.n	33504c <uniffi_pbcli_checksum_method_api_base@@Base+0x1c87c8>
│ │ @@ -845950,25 +845950,25 @@
│ │  	b.n	3354f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c8c6c>
│ │  	strb	r4, [r2, #0]
│ │  	b.n	3354f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c8c70>
│ │  	vpmin.u8	q15, <illegal reg q8.5>, <illegal reg q15.5>
│ │  	strh	r1, [r1, #0]
│ │  	b.n	335d02 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c947e>
│ │  	vpmin.u<illegal width 64>	q7, <illegal reg q15.5>, <illegal reg q15.5>
│ │ -	add	r2, sp, #96	@ 0x60
│ │ +	add	r2, sp, #252	@ 0xfc
│ │  			@ <UNDEFINED> instruction: 0xffd65bf0
│ │ -	vqrshrn.u32	d26, q8, #11
│ │ +			@ <UNDEFINED> instruction: 0xffd5a997
│ │  			@ <UNDEFINED> instruction: 0xffd65b48
│ │ -			@ <UNDEFINED> instruction: 0xffd5a9d0
│ │ -			@ <UNDEFINED> instruction: 0xffd663ed
│ │ +			@ <UNDEFINED> instruction: 0xffd5a9f7
│ │ +	vsri.16	d22, d4, #10
│ │  	vmull.u16	<illegal reg q12.5>, d6, d4[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd5a7c9
│ │ +	vqshl.u64	q13, q8, #21
│ │  			@ <UNDEFINED> instruction: 0xffd6bdd2
│ │ -			@ <UNDEFINED> instruction: 0xffd5a904
│ │ -	vrsubhn.i32	d26, q11, q4
│ │ +			@ <UNDEFINED> instruction: 0xffd5a92b
│ │ +	vrsubhn.i32	d26, q11, <illegal reg q15.5>
│ │  	vmul.i16	<illegal reg q10.5>, q3, d0[2]
│ │  			@ <UNDEFINED> instruction: 0xffd54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	335f18 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9694>
│ │  	beq.n	335a48 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c91c4>
│ │  	b.n	335e9c <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9618>
│ │  	str	r0, [r4, r0]
│ │ @@ -846324,21 +846324,21 @@
│ │  	str	r0, [r3, #0]
│ │  	b.n	33583c <uniffi_pbcli_checksum_method_api_base@@Base+0x1c8fb8>
│ │  	str	r0, [sp, #112]	@ 0x70
│ │  	b.n	335840 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c8fbc>
│ │  			@ <UNDEFINED> instruction: 0xff92eaff
│ │  	subs	r7, #21
│ │  			@ <UNDEFINED> instruction: 0xffd54ed9
│ │ -	vmlsl.u16	q9, d20, d14
│ │ -	vabal.u16	q13, d6, d0
│ │ -	vraddhn.i32	d26, q11, q8
│ │ -	vshr.u64	d22, d18, #42
│ │ +			@ <UNDEFINED> instruction: 0xffd42ab5
│ │ +	vabal.u16	q13, d6, d23
│ │ +	vmls.i16	q13, q11, d7[0]
│ │ +	vshr.u64	q11, <illegal reg q4.5>, #42
│ │  	vrsra.u64	q11, q11, #42
│ │  	vmull.u16	q10, d20, d17
│ │ -	vmls.i16	q13, q2, d4[3]
│ │ +	vsri.64	d26, d3, #44
│ │  			@ <UNDEFINED> instruction: 0xffd64ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	336250 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c99cc>
│ │  	beq.n	335df0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c956c>
│ │  	b.n	3361d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9950>
│ │  	blt.n	335d3e <uniffi_pbcli_checksum_method_api_base@@Base+0x1c94ba>
│ │  	b.n	3361d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9954>
│ │ @@ -846538,18 +846538,18 @@
│ │  	b.n	33662a <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9da6>
│ │  	ldr	r3, [r2, #0]
│ │  			@ <UNDEFINED> instruction: 0xebff0008
│ │  	b.n	336232 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c99ae>
│ │  	beq.n	335f2c <uniffi_pbcli_checksum_method_api_base@@Base+0x1c96a8>
│ │  	b.n	33638c <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9b08>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r3, r7, r8, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd6cfaa
│ │ -	vsra.u16	q13, q2, #10
│ │ -			@ <UNDEFINED> instruction: 0xffd6cf76
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r5, r7, r8, sp, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffd6cfd1
│ │ +	vsra.u16	q13, <illegal reg q13.5>, #10
│ │ +			@ <UNDEFINED> instruction: 0xffd6cf9d
│ │  			@ <UNDEFINED> instruction: 0xffd64bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	33642c <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9ba8>
│ │  	beq.n	335f24 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c96a0>
│ │  	b.n	3363b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9b2c>
│ │  	lsls	r0, r2, #1
│ │  	movt	r0, #1536	@ 0x600
│ │ @@ -846907,31 +846907,31 @@
│ │  	b.n	33696e <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca0ea>
│ │  	vpmin.u16	q15, q13, <illegal reg q15.5>
│ │  	stmia	r3!, {r4, r6}
│ │  	vmlal.u16	<illegal reg q10.5>, d4, d3[0]
│ │  	vsubl.u16	<illegal reg q10.5>, d5, d15
│ │  	vrshr.u64	d25, d0, #43
│ │  	vsra.u64	d21, d22, #43
│ │ -	vqrdmlsh.s16	<illegal reg q12.5>, <illegal reg q10.5>, d0[3]
│ │ +	vaddl.u16	q13, d5, d15
│ │  	vmla.i16	q11, q3, d6[1]
│ │  			@ <UNDEFINED> instruction: 0xffd44909
│ │ -			@ <UNDEFINED> instruction: 0xffd49f38
│ │ +			@ <UNDEFINED> instruction: 0xffd49f5f
│ │  			@ <UNDEFINED> instruction: 0xffd65f9e
│ │ -			@ <UNDEFINED> instruction: 0xffd403e0
│ │ +	vraddhn.i32	d16, q2, <illegal reg q3.5>
│ │  	vaddw.u16	<illegal reg q10.5>, q3, d3
│ │  	vsra.u64	d28, d23, #43
│ │ -			@ <UNDEFINED> instruction: 0xffd49e54
│ │ +			@ <UNDEFINED> instruction: 0xffd49e7b
│ │  			@ <UNDEFINED> instruction: 0xffd65eba
│ │ -	vmull.p<illegal width 16>	<illegal reg q12.5>, d20, d0
│ │ +	vmull.p<illegal width 16>	<illegal reg q12.5>, d20, d23
│ │  	vqrdmlah.s16	<illegal reg q10.5>, q11, d6[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd49df0
│ │ +			@ <UNDEFINED> instruction: 0xffd49e17
│ │  			@ <UNDEFINED> instruction: 0xffd65e56
│ │ -	vaddl.u16	q13, d20, d0
│ │ +	vaddl.u16	q13, d20, d23
│ │  	vmla.i16	q11, q11, d6[2]
│ │ -	vqrdmlsh.s16	<illegal reg q12.5>, q2, d4[2]
│ │ +			@ <UNDEFINED> instruction: 0xffd49f8b
│ │  	vqrdmlsh.s16	<illegal reg q10.5>, q11, d2[1]
│ │  			@ <UNDEFINED> instruction: 0xffd44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3367b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9f2c>
│ │  	beq.n	3362a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9a1c>
│ │  	b.n	336734 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9eb0>
│ │  	add	r0, pc, #0	@ (adr r0, 33629c <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9a18>)
│ │ @@ -847016,16 +847016,16 @@
│ │  	b.n	336a86 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca202>
│ │  	strh	r3, [r1, #26]
│ │  			@ <UNDEFINED> instruction: 0xebfe0004
│ │  	b.n	33668e <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9e0a>
│ │  	beq.n	336388 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9b04>
│ │  	b.n	3367e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9f64>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r2, r3, r4, r6, r7, sl, fp, ip, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd6eb33
│ │ +	ldmia.w	sp!, {r0, r1, r8, sl, fp, ip, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffd6eb5a
│ │  			@ <UNDEFINED> instruction: 0xffd54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	336880 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9ffc>
│ │  	beq.n	3363f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9b6c>
│ │  	b.n	336804 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9f80>
│ │  	str	r1, [r0, #0]
│ │  	b.n	3366ae <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9e2a>
│ │ @@ -848049,62 +848049,62 @@
│ │  	movs	r0, #84	@ 0x54
│ │  	b.n	336778 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9ef4>
│ │  	movs	r0, r0
│ │  	b.n	336d5c <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca4d8>
│ │  	movs	r0, #2
│ │  	b.n	336d60 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca4dc>
│ │  	vpmin.u8	q15, q14, <illegal reg q15.5>
│ │ -	ldr	r4, [sp, #336]	@ 0x150
│ │ +	ldr	r4, [sp, #492]	@ 0x1ec
│ │  			@ <UNDEFINED> instruction: 0xffd68ede
│ │ -			@ <UNDEFINED> instruction: 0xffd59bcc
│ │ +			@ <UNDEFINED> instruction: 0xffd59bf3
│ │  			@ <UNDEFINED> instruction: 0xffd68e56
│ │ -			@ <UNDEFINED> instruction: 0xffd59b5c
│ │ +			@ <UNDEFINED> instruction: 0xffd59b83
│ │  	vmls.i16	<illegal reg q9.5>, q3, d1[3]
│ │  	vmls.i16	q10, <illegal reg q2.5>, d1[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd499fc
│ │ -	vmls.i16	<illegal reg q8.5>, q3, d7[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd698dc
│ │ -	vmull.u16	<illegal reg q12.5>, d6, d0[2]
│ │ -	vmul.f16	<illegal reg q12.5>, q11, d4[0]
│ │ -			@ <UNDEFINED> instruction: 0xffd699a0
│ │ -	vmul.f16	<illegal reg q12.5>, q3, d4[1]
│ │ -	vmlsl.u16	<illegal reg q12.5>, d6, d28
│ │ +	vmlsl.u16	<illegal reg q12.5>, d4, d19
│ │ +	vraddhn.i32	d17, q11, q7
│ │ +			@ <UNDEFINED> instruction: 0xffd69903
│ │ +	vmlsl.u16	<illegal reg q12.5>, d22, d7
│ │ +	vmul.f16	<illegal reg q12.5>, q11, d3[3]
│ │ +	vmul.f16	<illegal reg q12.5>, q11, d7[0]
│ │ +	vqrshrn.u32	d25, <illegal reg q9.5>, #10
│ │ +			@ <UNDEFINED> instruction: 0xffd69a53
│ │  	vmul.i16	<illegal reg q10.5>, q11, d2[1]
│ │ -			@ <UNDEFINED> instruction: 0xffd49740
│ │ +			@ <UNDEFINED> instruction: 0xffd49767
│ │  	vaddw.u16	<illegal reg q14.5>, q3, d16
│ │ -			@ <UNDEFINED> instruction: 0xffd493cc
│ │ +	vrsra.u64	<illegal reg q12.5>, <illegal reg q9.5>, #44
│ │  			@ <UNDEFINED> instruction: 0xffd6cdac
│ │  	vmla.i16	q10, q2, d5[1]
│ │ -	vmlsl.u16	<illegal reg q12.5>, d20, d0[1]
│ │ +	vmlsl.u16	<illegal reg q12.5>, d20, d7[3]
│ │  	vaddl.u16	<illegal reg q14.5>, d22, d24
│ │ -	vqshlu.s64	d25, d4, #20
│ │ +	vqshlu.s64	d25, d27, #20
│ │  	vshr.u16	<illegal reg q14.5>, q10, #10
│ │ -	vqshlu.s16	d25, d28, #4
│ │ -	vqshlu.s16	<illegal reg q12.5>, q4, #6
│ │ -	vsri.64	d25, d4, #42
│ │ +	vmlsl.u16	<illegal reg q12.5>, d4, d3[2]
│ │ +	vqshlu.s16	<illegal reg q12.5>, <illegal reg q15.5>, #6
│ │ +	vsri.64	d25, d27, #42
│ │  	vqshl.u16	d24, d14, #6
│ │ -	vmls.i16	<illegal reg q12.5>, <illegal reg q10.5>, d0[1]
│ │ +	vmls.i16	<illegal reg q12.5>, <illegal reg q10.5>, d7[3]
│ │  	vqshl.u16	q12, q1, #6
│ │ -			@ <UNDEFINED> instruction: 0xffd59b7c
│ │ +			@ <UNDEFINED> instruction: 0xffd59ba3
│ │  	vaddl.u16	q8, d6, d1
│ │  	b.n	3372ec <uniffi_pbcli_checksum_method_api_base@@Base+0x1caa68>
│ │  	movs	r2, r0
│ │  	subs	r0, r0, r0
│ │  	asrs	r4, r2, #32
│ │  	b.n	336810 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9f8c>
│ │  	asrs	r1, r0, #32
│ │  	b.n	336df4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca570>
│ │  	str	r7, [sp, #420]	@ 0x1a4
│ │  			@ <UNDEFINED> instruction: 0xeaff1004
│ │  	b.n	33681c <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9f98>
│ │  	asrs	r1, r0, #32
│ │  	b.n	336e00 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca57c>
│ │  	ldr	r1, [sp, #412]	@ 0x19c
│ │ -			@ <UNDEFINED> instruction: 0xeaff9328
│ │ -	vrsra.u16	d25, d20, #10
│ │ +			@ <UNDEFINED> instruction: 0xeaff934f
│ │ +	vrsra.u16	<illegal reg q12.5>, <illegal reg q5.5>, #10
│ │  	vaddl.u16	q8, d6, d1
│ │  	b.n	337314 <uniffi_pbcli_checksum_method_api_base@@Base+0x1caa90>
│ │  	movs	r3, r0
│ │  	subs	r0, r0, r0
│ │  	asrs	r0, r4, #32
│ │  	b.n	336838 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9fb4>
│ │  	movs	r0, #3
│ │ @@ -848117,16 +848117,16 @@
│ │  	asrs	r2, r0, #32
│ │  	b.n	33704e <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca7ca>
│ │  	stmia	r0!, {r2, r3}
│ │  	b.n	336e30 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca5ac>
│ │  	movs	r0, #12
│ │  	b.n	337056 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca7d2>
│ │  	ldr	r5, [sp, #412]	@ 0x19c
│ │ -			@ <UNDEFINED> instruction: 0xeaff92f8
│ │ -	vsubw.u16	<illegal reg q12.5>, q3, d8
│ │ +			@ <UNDEFINED> instruction: 0xeaff931f
│ │ +	vsubw.u16	<illegal reg q12.5>, q3, d31
│ │  	vmlal.u16	q10, d6, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	33706a <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca7e6>
│ │  	beq.n	336d3c <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca4b8>
│ │  	b.n	3371c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca944>
│ │  	stmia	r0!, {r3}
│ │  	b.n	336868 <uniffi_pbcli_checksum_method_api_base@@Base+0x1c9fe4>
│ │ @@ -848440,15 +848440,15 @@
│ │  	b.n	336b1c <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca298>
│ │  	movs	r0, r0
│ │  	b.n	336f20 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca69c>
│ │  	ldr??.w	lr, [r4], #255
│ │  	beq.n	336ffe <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca77a>
│ │  	b.n	33732a <uniffi_pbcli_checksum_method_api_base@@Base+0x1caaa6>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r5, r6, r8, sl, ip, sp}
│ │ +	ldmia.w	sp!, {r0, r3, r7, r8, sl, ip, sp}
│ │  			@ <UNDEFINED> instruction: 0xffd66368
│ │  	movs	r2, r3
│ │  	ldr	r0, [pc, #0]	@ (336ff8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca774>)
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	33733e <uniffi_pbcli_checksum_method_api_base@@Base+0x1caaba>
│ │  	beq.n	337030 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca7ac>
│ │  	b.n	33749c <uniffi_pbcli_checksum_method_api_base@@Base+0x1cac18>
│ │ @@ -848476,15 +848476,15 @@
│ │  	b.n	336b6c <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca2e8>
│ │  	movs	r0, r0
│ │  	b.n	336f70 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca6ec>
│ │  			@ <UNDEFINED> instruction: 0xf940ebff
│ │  	beq.n	33704e <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca7ca>
│ │  	b.n	33737a <uniffi_pbcli_checksum_method_api_base@@Base+0x1caaf6>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r6, sl, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r4, r5, r6, sl, ip, sp, lr, pc}
│ │  	vrsra.u16	d22, d0, #11
│ │  	movs	r2, r3
│ │  	movs	r4, r0
│ │  	b.n	336b88 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca304>
│ │  	movs	r0, r0
│ │  	b.n	33716c <uniffi_pbcli_checksum_method_api_base@@Base+0x1ca8e8>
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -849300,32 +849300,32 @@
│ │  	b.n	337aae <uniffi_pbcli_checksum_method_api_base@@Base+0x1cb22a>
│ │  			@ <UNDEFINED> instruction: 0xffd5eaff
│ │  	str	r0, [r2, #52]	@ 0x34
│ │  	movs	r2, r3
│ │  	bcs.n	337758 <uniffi_pbcli_checksum_method_api_base@@Base+0x1caed4>
│ │  	vsubl.u16	q11, d20, d8
│ │  	movs	r2, r3
│ │ -	beq.n	337682 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cadfe>
│ │ -			@ <UNDEFINED> instruction: 0xffd68a9f
│ │ +	beq.n	3376d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cae4c>
│ │ +	vmull.u16	q12, d22, d6[0]
│ │  			@ <UNDEFINED> instruction: 0xffd6ac13
│ │  	vaddl.u16	q11, d5, d20
│ │  	movs	r2, r3
│ │  	subs	r6, #179	@ 0xb3
│ │  			@ <UNDEFINED> instruction: 0xffd567c0
│ │  	vaddw.u16	q11, q2, d4
│ │  	movs	r2, r3
│ │ -	bl	412746 <uniffi_pbcli_checksum_method_api_base@@Base+0x2a5ec2>
│ │ -	adds	r1, #126	@ 0x7e
│ │ -	vshr.u64	d31, d14, #42
│ │ -	vaddl.u16	<illegal reg q14.5>, d5, d1
│ │ -	vrsubhn.i32	d20, q3, q8
│ │ +	bl	439746 <uniffi_pbcli_checksum_method_api_base@@Base+0x2ccec2>
│ │ +	adds	r1, #165	@ 0xa5
│ │ +	vmla.i16	<illegal reg q15.5>, q11, d5[0]
│ │ +	vaddl.u16	<illegal reg q14.5>, d5, d24
│ │ +	vmlsl.u16	q10, d6, d7[0]
│ │  			@ <UNDEFINED> instruction: 0xffd63bbf
│ │ -	vqrdmlsh.s16	q14, <illegal reg q2.5>, d5[2]
│ │ -	vabal.u16	q10, d22, d4
│ │ -			@ <UNDEFINED> instruction: 0xffd6cf31
│ │ +			@ <UNDEFINED> instruction: 0xffd5cf8c
│ │ +	vabal.u16	q10, d22, d27
│ │ +			@ <UNDEFINED> instruction: 0xffd6cf58
│ │  			@ <UNDEFINED> instruction: 0xffd64c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	337ce0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cb45c>
│ │  	beq.n	3377e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1caf64>
│ │  	b.n	337c64 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cb3e0>
│ │  	stmia	r0!, {r3}
│ │  	b.n	337304 <uniffi_pbcli_checksum_method_api_base@@Base+0x1caa80>
│ │ @@ -849735,19 +849735,19 @@
│ │  	b.n	3382a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cba1e>
│ │  	str	r5, [r6, #12]
│ │  			@ <UNDEFINED> instruction: 0xebff0005
│ │  	b.n	337eaa <uniffi_pbcli_checksum_method_api_base@@Base+0x1cb626>
│ │  	beq.n	337ba4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cb320>
│ │  	b.n	338004 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cb780>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r2, r3, r7, r8, r9, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r4, r5, r7, r8, r9, ip, sp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd6ef19
│ │ -	vrsra.u16	<illegal reg q13.5>, q4, #12
│ │ +	vrsra.u16	<illegal reg q13.5>, <illegal reg q15.5>, #12
│ │  	vqrdmlah.s16	q15, q11, d5[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd4b3c0
│ │ +			@ <UNDEFINED> instruction: 0xffd4b3e7
│ │  	vqrdmlsh.s16	q15, q3, d5[1]
│ │  	vqshrun.s32	d20, q8, #12
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3380ac <uniffi_pbcli_checksum_method_api_base@@Base+0x1cb828>
│ │  	beq.n	337bc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cb340>
│ │  	b.n	338030 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cb7ac>
│ │  	stmia	r0!, {r3}
│ │ @@ -850097,17 +850097,17 @@
│ │  	add	r2, sp, #628	@ 0x274
│ │  	add.w	r0, r0, r0, lsl #20
│ │  	b.n	338606 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbd82>
│ │  	movs	r5, r0
│ │  	b.n	33820a <uniffi_pbcli_checksum_method_api_base@@Base+0x1cb986>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, r2, r3, r6, sl, fp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd4cfff
│ │ +	vaddl.u16	<illegal reg q14.5>, d4, d22
│ │  	vmull.u16	q12, d5, d17
│ │ -			@ <UNDEFINED> instruction: 0xffd4cfd3
│ │ +			@ <UNDEFINED> instruction: 0xffd4cffa
│ │  			@ <UNDEFINED> instruction: 0xffd54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	338400 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbb7c>
│ │  	beq.n	337f20 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cb69c>
│ │  	b.n	338384 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbb00>
│ │  	str	r0, [sp, #12]
│ │  	b.n	33822e <uniffi_pbcli_checksum_method_api_base@@Base+0x1cb9aa>
│ │ @@ -850487,32 +850487,32 @@
│ │  	b.n	338354 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbad0>
│ │  	ldrb	r2, [r2, #13]
│ │  			@ <UNDEFINED> instruction: 0xebfe1103
│ │  	b.n	33883e <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbfba>
│ │  	asrs	r4, r1, #32
│ │  	b.n	3388c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc03e>
│ │  			@ <UNDEFINED> instruction: 0xff9feaff
│ │ -	strh	r0, [r3, r0]
│ │ +	strh	r7, [r7, r0]
│ │  	vshr.u16	<illegal reg q8.5>, q1, #10
│ │ -	vmla.f16	<illegal reg q10.5>, q10, d0[3]
│ │ +	vsubl.u16	<illegal reg q10.5>, d4, d15
│ │  	vaddl.u16	<illegal reg q8.5>, d6, d18
│ │ -	vsra.u64	d21, d12, #44
│ │ +	vmla.f16	<illegal reg q10.5>, q10, d3[0]
│ │  			@ <UNDEFINED> instruction: 0xffd60fd6
│ │ -	vmlal.u16	<illegal reg q10.5>, d20, d4[2]
│ │ -	vsra.u16	d21, d28, #10
│ │ +	vsubw.u16	<illegal reg q10.5>, q2, d11
│ │ +	vmla.f16	<illegal reg q10.5>, q3, d3[2]
│ │  			@ <UNDEFINED> instruction: 0xffd60f76
│ │ -	vshr.u64	d21, d8, #44
│ │ +	vshr.u64	d21, d31, #44
│ │  			@ <UNDEFINED> instruction: 0xffd60ed2
│ │ -	vsra.u16	<illegal reg q10.5>, q12, #12
│ │ +	vsra.u64	d21, d15, #44
│ │  			@ <UNDEFINED> instruction: 0xffd60f9a
│ │ -	vsra.u16	d21, d4, #12
│ │ +	vsra.u16	d21, d27, #12
│ │  			@ <UNDEFINED> instruction: 0xffd60f36
│ │ -	vshr.u64	<illegal reg q10.5>, <illegal reg q12.5>, #44
│ │ +	vaddw.u16	<illegal reg q10.5>, q2, d16
│ │  			@ <UNDEFINED> instruction: 0xffd627cc
│ │ -	vaddl.u16	<illegal reg q10.5>, d20, d0
│ │ +	vaddl.u16	<illegal reg q10.5>, d20, d23
│ │  	vmull.p<illegal width 16>	q8, d22, d18
│ │  			@ <UNDEFINED> instruction: 0xffd44c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3387b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbf30>
│ │  	beq.n	3382cc <uniffi_pbcli_checksum_method_api_base@@Base+0x1cba48>
│ │  	b.n	338738 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbeb4>
│ │  	stmia	r0!, {r2, r3}
│ │ @@ -850641,17 +850641,17 @@
│ │  	b.n	3384cc <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbc48>
│ │  	str	r2, [sp, #792]	@ 0x318
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	3386f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbe72>
│ │  	beq.n	3383e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbb64>
│ │  	b.n	338850 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbfcc>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r2, r4, r8, r9, sl, fp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r4, r5, r8, r9, sl, fp, lr}
│ │  	vmlsl.u16	q15, d6, d0[3]
│ │ -	vqrdmlah.s16	q10, q10, d4[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd44f13
│ │  			@ <UNDEFINED> instruction: 0xffd64bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3388ec <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc068>
│ │  	beq.n	338414 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbb90>
│ │  	b.n	338870 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbfec>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	33871a <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbe96>
│ │ @@ -850812,21 +850812,21 @@
│ │  			@ <UNDEFINED> instruction: 0xebfd4000
│ │  	b.n	338c76 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc3f2>
│ │  	movs	r4, r0
│ │  	b.n	33887a <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbff6>
│ │  	beq.n	33856c <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbce8>
│ │  	b.n	3389d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc150>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, sl, fp, lr}
│ │ -	vshr.u64	d18, d21, #42
│ │ -	vqrdmulh.s16	q10, q11, d4[1]
│ │ -	vaddl.u16	q9, d22, d9
│ │ -			@ <UNDEFINED> instruction: 0xffd64d9c
│ │ -	vshr.u16	q9, <illegal reg q4.5>, #10
│ │ -			@ <UNDEFINED> instruction: 0xffd64e14
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r4, r9, sl, fp, lr}
│ │ +	vshr.u64	q9, q6, #42
│ │ +			@ <UNDEFINED> instruction: 0xffd64df3
│ │ +	vshr.u64	d18, d16, #42
│ │ +	vqrdmulh.s16	q10, q11, d3[0]
│ │ +	vaddl.u16	q9, d22, d0
│ │ +			@ <UNDEFINED> instruction: 0xffd64e3b
│ │  			@ <UNDEFINED> instruction: 0xffd64ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	338a80 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc1fc>
│ │  	beq.n	338490 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbc0c>
│ │  	b.n	338a04 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc180>
│ │  	str	r0, [sp, #0]
│ │  	b.n	3388ae <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc02a>
│ │ @@ -850997,20 +850997,20 @@
│ │  	strb	r1, [r0, #0]
│ │  	asrs	r0, r0, #12
│ │  	movs	r7, r0
│ │  	b.n	338a2a <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc1a6>
│ │  	beq.n	338724 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbea0>
│ │  	b.n	338b84 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc300>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r8, r9, ip, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r6, r8, r9, ip, pc}
│ │  	vqdmulh.s16	<illegal reg q15.5>, q3, d0[0]
│ │  	vsri.16	q14, q12, #13
│ │  	vsli.64	d17, d31, #20
│ │  			@ <UNDEFINED> instruction: 0xffd4e3c3
│ │ -	vqshlu.s16	d17, d29, #4
│ │ +	vmlsl.u16	<illegal reg q8.5>, d4, d4[2]
│ │  			@ <UNDEFINED> instruction: 0xffd64df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	338c2c <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc3a8>
│ │  	beq.n	338764 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbee0>
│ │  	b.n	338bb0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc32c>
│ │  	ands	r3, r0
│ │  	b.n	338a5a <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc1d6>
│ │ @@ -851112,15 +851112,15 @@
│ │  			@ <UNDEFINED> instruction: 0xebfe0004
│ │  	b.n	338b32 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc2ae>
│ │  	beq.n	338824 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbfa0>
│ │  	b.n	338c8c <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc408>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r1, r2, r3, r8, fp, ip, sp}
│ │  	vmul.i16	<illegal reg q9.5>, q10, d6[2]
│ │ -	vqrdmlah.s16	<illegal reg q13.5>, q2, d7[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd4be76
│ │  			@ <UNDEFINED> instruction: 0xffd64ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	338d28 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc4a4>
│ │  	beq.n	338838 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cbfb4>
│ │  	b.n	338cac <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc428>
│ │  	movs	r0, r0
│ │  	b.n	338eba <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc636>
│ │ @@ -851573,30 +851573,30 @@
│ │  	add.w	r0, r0, r0, lsl #16
│ │  	b.n	33934e <uniffi_pbcli_checksum_method_api_base@@Base+0x1ccaca>
│ │  	movs	r4, r0
│ │  	b.n	338f52 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc6ce>
│ │  	beq.n	338c4c <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc3c8>
│ │  	b.n	3390ac <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc828>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r3, r5, r6, r7, r8, sl}
│ │ +	ldmia.w	sp!, {r4, r9, sl}
│ │  	vmul.f16	q11, q11, d6[3]
│ │ -			@ <UNDEFINED> instruction: 0xffd56c1e
│ │ -	vrsubhn.i32	d16, q3, <illegal reg q4.5>
│ │ +	vqdmulh.s16	q11, <illegal reg q2.5>, d5[0]
│ │ +	vqshlu.s16	d16, d16, #6
│ │  	vmlsl.u16	q11, d6, d14
│ │ -	vrsra.u16	d16, d5, #11
│ │ +	vrsra.u16	d16, d28, #11
│ │  	vqshl.u16	d22, d10, #6
│ │ -			@ <UNDEFINED> instruction: 0xffd50345
│ │ +			@ <UNDEFINED> instruction: 0xffd5036c
│ │  			@ <UNDEFINED> instruction: 0xffd6674a
│ │  			@ <UNDEFINED> instruction: 0xffd54a98
│ │  	movs	r2, r3
│ │  	bxns	fp
│ │  	movs	r2, r3
│ │  	blxns	fp
│ │  	movs	r2, r3
│ │ -	lsls	r1, r1, #17
│ │ +	lsls	r0, r6, #17
│ │  	vmul.i16	q11, q3, d6[1]
│ │  			@ <UNDEFINED> instruction: 0xffd54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	339174 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc8f0>
│ │  	beq.n	338c84 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc400>
│ │  	b.n	3390f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc874>
│ │  	adds	r0, #12
│ │ @@ -851857,15 +851857,15 @@
│ │  	beq.n	338ee8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc664>
│ │  	b.n	339348 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ccac4>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r2}
│ │  	b.n	3391fa <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc976>
│ │  	str	r7, [r5, r5]
│ │  			@ <UNDEFINED> instruction: 0xeb01fff9
│ │ -			@ <UNDEFINED> instruction: 0xeaff0061
│ │ +			@ <UNDEFINED> instruction: 0xeaff0088
│ │  	vaddl.u16	q8, d6, d4
│ │  	b.n	3389ea <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc166>
│ │  	movs	r0, r0
│ │  	b.n	33956e <uniffi_pbcli_checksum_method_api_base@@Base+0x1cccea>
│ │  	movs	r1, r0
│ │  	asrs	r0, r0, #12
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -851963,17 +851963,17 @@
│ │  	ldrsh	r6, [r5, r6]
│ │  			@ <UNDEFINED> instruction: 0xebfd0005
│ │  	b.n	3392f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cca6e>
│ │  	beq.n	338fc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cc740>
│ │  	b.n	33944c <uniffi_pbcli_checksum_method_api_base@@Base+0x1ccbc8>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r5, r6, r7, r9, ip, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd42cf7
│ │ +			@ <UNDEFINED> instruction: 0xffd42d1e
│ │  	vsubl.u16	<illegal reg q15.5>, d22, d24
│ │ -			@ <UNDEFINED> instruction: 0xffd42cbf
│ │ +	vqdmulh.s16	q9, q10, d6[2]
│ │  			@ <UNDEFINED> instruction: 0xffd64ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3394ec <uniffi_pbcli_checksum_method_api_base@@Base+0x1ccc68>
│ │  	svc	69	@ 0x45
│ │  	b.n	339470 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ccbec>
│ │  	str	r0, [r0, #0]
│ │  	b.n	33931a <uniffi_pbcli_checksum_method_api_base@@Base+0x1cca96>
│ │ @@ -852656,28 +852656,28 @@
│ │  	movs	r0, #0
│ │  	b.n	339d02 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cd47e>
│ │  	str	r0, [sp, #0]
│ │  	b.n	339d06 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cd482>
│ │  	strb	r3, [r5, #26]
│ │  			@ <UNDEFINED> instruction: 0xebfeffd3
│ │  			@ <UNDEFINED> instruction: 0xeafff1e8
│ │ -	vsri.16	d29, d21, #12
│ │ +	vsri.16	<illegal reg q14.5>, q6, #12
│ │  	vsra.u64	d31, d28, #43
│ │ -	vraddhn.i32	d29, q2, <illegal reg q4.5>
│ │ +	vsri.16	d29, d16, #12
│ │  	vqrdmlsh.s16	q15, <illegal reg q2.5>, d0[0]
│ │ -	vaddw.u16	<illegal reg q14.5>, q10, d13
│ │ +	vsra.u64	d29, d20, #44
│ │  	vqrdmulh.s16	q15, <illegal reg q10.5>, d0[0]
│ │ -	vmlsl.u16	<illegal reg q13.5>, d4, d15
│ │ +	vshll.u16	<illegal reg q13.5>, d22, #4
│ │  	vmull.p<illegal width 16>	q12, d5, d27
│ │  			@ <UNDEFINED> instruction: 0xffd5eed4
│ │ -	vaddw.u16	<illegal reg q14.5>, q2, d17
│ │ +	vmla.f16	<illegal reg q14.5>, q2, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffd5ee70
│ │ -	vshr.u64	d29, d29, #44
│ │ +	vmla.i16	<illegal reg q14.5>, q10, d4[2]
│ │  	vmull.u16	q15, d21, d4
│ │ -			@ <UNDEFINED> instruction: 0xffd4ced1
│ │ +			@ <UNDEFINED> instruction: 0xffd4cef8
│ │  			@ <UNDEFINED> instruction: 0xffd54df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	339b2c <uniffi_pbcli_checksum_method_api_base@@Base+0x1cd2a8>
│ │  	beq.n	3396d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cce50>
│ │  	b.n	339ab0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cd22c>
│ │  	ands	r0, r0
│ │  	b.n	33995a <uniffi_pbcli_checksum_method_api_base@@Base+0x1cd0d6>
│ │ @@ -852910,21 +852910,21 @@
│ │  	b.n	339f5e <uniffi_pbcli_checksum_method_api_base@@Base+0x1cd6da>
│ │  	strb	r5, [r2, #24]
│ │  			@ <UNDEFINED> instruction: 0xebfe0007
│ │  	b.n	339b66 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cd2e2>
│ │  	ldrb	r7, [r1, r6]
│ │  			@ <UNDEFINED> instruction: 0xebfdffed
│ │  			@ <UNDEFINED> instruction: 0xeaffeb40
│ │ -	vsli.16	q9, q8, #4
│ │ +	vsli.64	d18, d7, #20
│ │  			@ <UNDEFINED> instruction: 0xffd6ea98
│ │ -	vmls.i16	q9, q10, d0[1]
│ │ +	vmls.i16	q9, q10, d7[3]
│ │  	vmlsl.u16	q15, d6, d28
│ │ -	vsri.16	q9, q6, #12
│ │ +	vraddhn.i32	d18, q10, <illegal reg q1.5>
│ │  	vmull.u16	q15, d6, d0[3]
│ │ -	vsri.64	d18, d8, #44
│ │ +	vsri.64	d18, d31, #44
│ │  			@ <UNDEFINED> instruction: 0xffd648f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	339d70 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cd4ec>
│ │  	beq.n	339938 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cd0b4>
│ │  	b.n	339cf4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cd470>
│ │  	ands	r0, r1
│ │  	b.n	339394 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ccb10>
│ │ @@ -853222,19 +853222,19 @@
│ │  	strb	r7, [r3, #21]
│ │  			@ <UNDEFINED> instruction: 0xebfe0004
│ │  	b.n	339e3e <uniffi_pbcli_checksum_method_api_base@@Base+0x1cd5ba>
│ │  	beq.n	339b38 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cd2b4>
│ │  	b.n	339f98 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cd714>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r1, r4, r9, sl, ip, sp, lr, pc}
│ │ -	vqrdmulh.s16	<illegal reg q11.5>, <illegal reg q9.5>, d0[2]
│ │ +	vmull.p<illegal width 16>	<illegal reg q11.5>, d3, d7
│ │  	vrsubhn.i32	d31, q3, q15
│ │ -			@ <UNDEFINED> instruction: 0xffd37dfc
│ │ +	vmull.p<illegal width 16>	<illegal reg q11.5>, d3, d19
│ │  	vqshlu.s16	<illegal reg q15.5>, q3, #6
│ │ -	vmull.p<illegal width 16>	<illegal reg q11.5>, d3, d20
│ │ +	vqrdmlah.s16	<illegal reg q11.5>, <illegal reg q1.5>, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffd64bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	33a040 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cd7bc>
│ │  	beq.n	339b48 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cd2c4>
│ │  	b.n	339fc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cd740>
│ │  	ands	r3, r0
│ │  	b.n	339e6e <uniffi_pbcli_checksum_method_api_base@@Base+0x1cd5ea>
│ │ @@ -853779,17 +853779,17 @@
│ │  	str	r0, [sp, #0]
│ │  	asrs	r5, r0, #22
│ │  	movs	r1, r1
│ │  	b.n	33a31e <uniffi_pbcli_checksum_method_api_base@@Base+0x1cda9a>
│ │  	beq.n	33a018 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cd794>
│ │  	b.n	33a478 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cdbf4>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r4, r5, r6, r7, r8, r9, sl, fp, sp, lr, pc}
│ │ -	vsra.u16	d31, d10, #11
│ │ -	vmla.i16	<illegal reg q15.5>, <illegal reg q2.5>, d6[0]
│ │ +	ldmia.w	sp!, {r0, r3, r4, ip, sp, lr, pc}
│ │ +	vmla.f16	<illegal reg q15.5>, <illegal reg q2.5>, d1[0]
│ │ +	vmla.i16	<illegal reg q15.5>, <illegal reg q2.5>, d5[3]
│ │  	vmlal.u16	q10, d5, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	33a33a <uniffi_pbcli_checksum_method_api_base@@Base+0x1cdab6>
│ │  	lsls	r3, r6, #1
│ │  	b.n	33a5fe <uniffi_pbcli_checksum_method_api_base@@Base+0x1cdd7a>
│ │  	lsls	r0, r0, #6
│ │  	b.n	33a684 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cde00>
│ │ @@ -854866,29 +854866,29 @@
│ │  	movs	r0, #148	@ 0x94
│ │  	b.n	33b0c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ce83e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	33aaa4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ce220>
│ │  	ldrh	r0, [r2, #10]
│ │  			@ <UNDEFINED> instruction: 0xebffff8b
│ │  			@ <UNDEFINED> instruction: 0xeaffee36
│ │ -	vqshl.u64	d29, d0, #19
│ │ +	vqshl.u64	d29, d23, #19
│ │  	vmull.p<illegal width 16>	q15, d5, d14
│ │ -			@ <UNDEFINED> instruction: 0xffd3d768
│ │ +	vabdl.u16	<illegal reg q14.5>, d19, d15
│ │  			@ <UNDEFINED> instruction: 0xffd5e8f6
│ │ -	vrshr.u16	<illegal reg q14.5>, q0, #13
│ │ +	vrshr.u16	<illegal reg q14.5>, <illegal reg q11.5>, #13
│ │  	vqshrn.u32	d30, q1, #11
│ │ -	vmlal.u16	<illegal reg q14.5>, d3, d4[3]
│ │ +	vrshr.u64	d29, d3, #45
│ │  	vmul.f16	q15, <illegal reg q2.5>, d2[1]
│ │ -	vsubl.u16	<illegal reg q14.5>, d19, d20
│ │ +	vmlal.u16	<illegal reg q14.5>, d19, d3[1]
│ │  	vmlsl.u16	q15, d5, d10
│ │  			@ <UNDEFINED> instruction: 0xffd3e9ae
│ │  			@ <UNDEFINED> instruction: 0xffd3e8b2
│ │  	vqshl.u64	d30, d14, #19
│ │  			@ <UNDEFINED> instruction: 0xffd3edda
│ │ -	vqshl.u16	d29, d20, #3
│ │ +	vqshl.u16	<illegal reg q14.5>, <illegal reg q5.5>, #3
│ │  			@ <UNDEFINED> instruction: 0xffd54df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	33aef0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ce66c>
│ │  	beq.n	33aa48 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ce1c4>
│ │  	b.n	33ae74 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ce5f0>
│ │  	str	r2, [r0, #0]
│ │  	b.n	33ad1e <uniffi_pbcli_checksum_method_api_base@@Base+0x1ce49a>
│ │ @@ -855073,21 +855073,21 @@
│ │  	b.n	33a6bc <uniffi_pbcli_checksum_method_api_base@@Base+0x1cde38>
│ │  	movs	r0, r0
│ │  	b.n	33aca0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ce41c>
│ │  	movs	r0, #2
│ │  	b.n	33aca4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ce420>
│ │  			@ <UNDEFINED> instruction: 0xffcfeaff
│ │  	b.n	33a848 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cdfc4>
│ │ -	vmull.u16	<illegal reg q15.5>, d19, d2[0]
│ │ +	vmull.u16	<illegal reg q15.5>, d19, d1[3]
│ │  	vmls.f16	q15, <illegal reg q10.5>, d2[1]
│ │ -	vmlsl.u16	<illegal reg q15.5>, d3, d30
│ │ +			@ <UNDEFINED> instruction: 0xffd3fa55
│ │  	vrsubhn.i32	d30, <illegal reg q2.5>, q13
│ │ -	vmlsl.u16	<illegal reg q15.5>, d19, d14
│ │ +			@ <UNDEFINED> instruction: 0xffd3fab5
│ │  	vabal.u16	q15, d21, d18
│ │ -	vmlsl.u16	<illegal reg q15.5>, d3, d6
│ │ +	vmlsl.u16	<illegal reg q15.5>, d3, d29
│ │  			@ <UNDEFINED> instruction: 0xffd54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	33b0cc <uniffi_pbcli_checksum_method_api_base@@Base+0x1ce848>
│ │  	beq.n	33ac8c <uniffi_pbcli_checksum_method_api_base@@Base+0x1ce408>
│ │  	b.n	33b050 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ce7cc>
│ │  	movs	r0, r0
│ │  	b.n	33b25a <uniffi_pbcli_checksum_method_api_base@@Base+0x1ce9d6>
│ │ @@ -855973,15 +855973,15 @@
│ │  	ands	r0, r0
│ │  	b.n	33bace <uniffi_pbcli_checksum_method_api_base@@Base+0x1cf24a>
│ │  	ldr	r1, [r7, #112]	@ 0x70
│ │  			@ <UNDEFINED> instruction: 0xebfe0004
│ │  	b.n	33b6d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cee52>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r1, r2, r3, r5, r7, r8, sl, fp, ip, lr, pc}
│ │ -	vqshrn.u32	d16, <illegal reg q2.5>, #13
│ │ +	vqshrn.u32	d16, q14, #13
│ │  			@ <UNDEFINED> instruction: 0xffd64bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	33b8c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cf040>
│ │  	beq.n	33b3dc <uniffi_pbcli_checksum_method_api_base@@Base+0x1ceb58>
│ │  	b.n	33b848 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cefc4>
│ │  	str	r0, [r0, #0]
│ │  	b.n	33b6f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cee6e>
│ │ @@ -856364,15 +856364,15 @@
│ │  	b.n	33bd92 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cf50e>
│ │  	movs	r0, #0
│ │  	b.n	33be56 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cf5d2>
│ │  	ldr	r7, [r2, #100]	@ 0x64
│ │  			@ <UNDEFINED> instruction: 0xebfe0004
│ │  	b.n	33ba5e <uniffi_pbcli_checksum_method_api_base@@Base+0x1cf1da>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r5, r7, r8, sl}
│ │ +	ldmia.w	sp!, {r1, r3, r6, r7, r8, sl}
│ │  	vmul.f16	q8, q11, d5[3]
│ │  			@ <UNDEFINED> instruction: 0xffd448f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	33bc4c <uniffi_pbcli_checksum_method_api_base@@Base+0x1cf3c8>
│ │  	str	r2, [r0, #0]
│ │  	b.n	33ba76 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cf1f2>
│ │  	strb	r1, [r0, #0]
│ │ @@ -856562,20 +856562,20 @@
│ │  	ldmia.w	sp!, {r0, lr}
│ │  	b.n	33c016 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cf792>
│ │  	movs	r4, r0
│ │  	b.n	33bc1a <uniffi_pbcli_checksum_method_api_base@@Base+0x1cf396>
│ │  	ands	r4, r1
│ │  	b.n	33b3e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ceb64>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r2, r3, r9, sl, ip, sp, lr}
│ │ -	vsra.u64	d19, d1, #42
│ │ -	vsli.64	<illegal reg q11.5>, q8, #22
│ │ -	vsra.u16	<illegal reg q9.5>, <illegal reg q10.5>, #10
│ │ -	vqshlu.s16	d23, d24, #6
│ │ -	vsra.u64	d19, d29, #42
│ │ +	ldmia.w	sp!, {r0, r1, r4, r5, r9, sl, ip, sp, lr}
│ │ +	vsra.u64	d19, d24, #42
│ │ +	vqshlu.s16	d23, d7, #6
│ │ +	vsra.u64	d19, d12, #42
│ │ +	vqshlu.s16	<illegal reg q11.5>, <illegal reg q7.5>, #6
│ │ +	vmla.f16	<illegal reg q9.5>, q11, d4[2]
│ │  	vaddl.u16	q8, d6, d0
│ │  	b.n	33bf9e <uniffi_pbcli_checksum_method_api_base@@Base+0x1cf71a>
│ │  	movs	r0, r3
│ │  	asrs	r0, r0, #10
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r7, [pc, #960]	@ (33bcc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cf444>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │ @@ -856844,16 +856844,16 @@
│ │  	vqrdmlah.s32	q15, <illegal reg q12.5>, <illegal reg q15.5>
│ │  	movs	r1, r0
│ │  	b.n	33c2a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cfa1e>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	33c2aa <uniffi_pbcli_checksum_method_api_base@@Base+0x1cfa26>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r2, r4, r5, r6, r8, r9, ip, sp, lr}
│ │ -	vrsra.u16	<illegal reg q11.5>, q0, #10
│ │ +	ldmia.w	sp!, {r0, r1, r3, r4, r7, r8, r9, ip, sp, lr}
│ │ +	vrsra.u16	<illegal reg q11.5>, <illegal reg q11.5>, #10
│ │  			@ <UNDEFINED> instruction: 0xffd64c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	33c098 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cf814>
│ │  	ands	r0, r0
│ │  	b.n	33bec2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cf63e>
│ │  	movs	r0, r2
│ │  	b.n	33b6a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1cee24>
│ │ @@ -859136,15 +859136,15 @@
│ │  			@ <UNDEFINED> instruction: 0xebff7000
│ │  	b.n	33d966 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d10e2>
│ │  	movs	r7, r0
│ │  	b.n	33d56a <uniffi_pbcli_checksum_method_api_base@@Base+0x1d0ce6>
│ │  	beq.n	33d264 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d09e0>
│ │  	b.n	33d6c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d0e40>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r4, r5, r8, sl, sp}
│ │ +	ldmia.w	sp!, {r0, r3, r4, r6, r8, sl, sp}
│ │  			@ <UNDEFINED> instruction: 0xffd68d55
│ │  			@ <UNDEFINED> instruction: 0xffd60c38
│ │  	movs	r0, r0
│ │  	ldrh	r1, [r2, #28]
│ │  	vmla.f16	q8, q3, d4[1]
│ │  	movs	r0, r0
│ │  	lsrs	r0, r0, #10
│ │ @@ -862554,15 +862554,15 @@
│ │  	movs	r6, r0
│ │  	b.n	33f366 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d2ae2>
│ │  	beq.n	33f060 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d27dc>
│ │  	b.n	33f4c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d2c3c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r1, r3, r4, r5, r6, r9, fp, sp, pc}
│ │  	vmul.f16	q13, q10, d6[1]
│ │ -	vmlsl.u16	<illegal reg q10.5>, d4, d2[1]
│ │ +	vqshlu.s16	<illegal reg q10.5>, <illegal reg q8.5>, #4
│ │  	vsubl.u16	q14, d6, d29
│ │  	vaddl.u16	<illegal reg q8.5>, d4, d8
│ │  	b.n	33eb80 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d22fc>
│ │  	movs	r1, #46	@ 0x2e
│ │  	b.n	33f646 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d2dc2>
│ │  	asrs	r1, r0, #32
│ │  	b.n	33f168 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d28e4>
│ │ @@ -862877,17 +862877,17 @@
│ │  	add.w	r0, r0, r6
│ │  	b.n	33f63a <uniffi_pbcli_checksum_method_api_base@@Base+0x1d2db6>
│ │  	beq.n	33f334 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d2ab0>
│ │  	b.n	33f794 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d2f10>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r3, r8, sl, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffffa8d6
│ │ -			@ <UNDEFINED> instruction: 0xffd49d70
│ │ +			@ <UNDEFINED> instruction: 0xffd49d97
│ │  	vqshl.u16	d26, d2, #5
│ │ -	vqshl.u64	d31, d8, #20
│ │ +	vqshl.u64	d31, d31, #20
│ │  			@ <UNDEFINED> instruction: 0xffd56d3d
│ │  	vqshlu.s64	d26, d30, #20
│ │  	vqrdmulh.s16	<illegal reg q15.5>, q2, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffff4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	33f844 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d2fc0>
│ │  	beq.n	33f334 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d2ab0>
│ │ @@ -863350,17 +863350,17 @@
│ │  	ldmia.w	sp!, {ip, lr}
│ │  	b.n	33fe52 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d35ce>
│ │  	movs	r5, r0
│ │  	b.n	33fa56 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d31d2>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r5, sl, ip}
│ │  	vsri.64	d25, d10, #43
│ │ -	vrshr.u64	d18, d30, #44
│ │ +	vmlal.u16	q9, d20, d5[2]
│ │  			@ <UNDEFINED> instruction: 0xffd6cab0
│ │ -			@ <UNDEFINED> instruction: 0xffd47c7c
│ │ +	vmull.u16	<illegal reg q11.5>, d20, d19
│ │  	vmlal.u16	<illegal reg q10.5>, d21, d0[2]
│ │  	vmul.f16	<illegal reg q15.5>, q2, d0[3]
│ │  			@ <UNDEFINED> instruction: 0xffd3cd5b
│ │  			@ <UNDEFINED> instruction: 0xffd44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	33fc5c <uniffi_pbcli_checksum_method_api_base@@Base+0x1d33d8>
│ │  	beq.n	33f78c <uniffi_pbcli_checksum_method_api_base@@Base+0x1d2f08>
│ │ @@ -864391,15 +864391,15 @@
│ │  	b.n	34032e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3aaa>
│ │  	ldr	r0, [pc, #192]	@ (3400b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d382c>)
│ │  	ldmia.w	sp!, {r0, r2, r4, r5, r7, r8, r9, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xeaff0500
│ │  	movs	r0, r0
│ │  	lsls	r4, r2, #19
│ │  	movs	r0, r0
│ │ -			@ <UNDEFINED> instruction: 0xea55ffd5
│ │ +			@ <UNDEFINED> instruction: 0xea7cffd5
│ │  	ldr	r7, [pc, #960]	@ (3403c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3b40>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	340524 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3ca0>
│ │  	beq.n	340014 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3790>
│ │  	b.n	3404a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3c24>
│ │  	asrs	r0, r7, #3
│ │  	b.n	33fb50 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d32cc>
│ │ @@ -864514,15 +864514,15 @@
│ │  	b.n	34043e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3bba>
│ │  	beq.n	340138 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d38b4>
│ │  	b.n	340598 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3d14>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r2, pc}
│ │  	b.n	34044a <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3bc6>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │ -			@ <UNDEFINED> instruction: 0xea1dffd5
│ │ +			@ <UNDEFINED> instruction: 0xea44ffd5
│ │  	lsls	r4, r5, #3
│ │  	movs	r0, r0
│ │  	lsls	r4, r5, #3
│ │  	movs	r0, r0
│ │  	lsls	r0, r7, #16
│ │  	movs	r0, r0
│ │  	lsls	r0, r0, #17
│ │ @@ -864802,22 +864802,22 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	3404a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3c20>
│ │  	strb	r0, [r2, #11]
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	33feb8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3634>
│ │  	add	r1, pc, #304	@ (adr r1, 3404c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3c3c>)
│ │  			@ <UNDEFINED> instruction: 0xebffffba
│ │ -			@ <UNDEFINED> instruction: 0xeaffe811
│ │ +			@ <UNDEFINED> instruction: 0xeaffe838
│ │  	vaddl.u16	<illegal reg q13.5>, d5, d22
│ │ -	vqshl.u64	q15, <illegal reg q6.5>, #20
│ │ +	vmlal.u16	q15, d4, d4
│ │  			@ <UNDEFINED> instruction: 0xffd5aff2
│ │ -	vqshl.u64	d30, d1, #20
│ │ -	vqshl.u16	d30, d25, #5
│ │ -	vqshlu.s64	d30, d21, #21
│ │ -	vmlsl.u16	q15, d21, d1[2]
│ │ +	vqshl.u64	d30, d24, #20
│ │ +			@ <UNDEFINED> instruction: 0xffd5e760
│ │ +	vqshlu.s64	q15, q6, #21
│ │ +	vabdl.u16	q15, d5, d8
│ │  	vaddl.u16	q9, d5, d1
│ │  	b.n	3406fa <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3e76>
│ │  	asrs	r0, r0, #32
│ │  	b.n	3406fe <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3e7a>
│ │  	movs	r1, r0
│ │  	b.n	340b02 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d427e>
│ │  			@ <UNDEFINED> instruction: 0xffffeaff
│ │ @@ -864885,15 +864885,15 @@
│ │  	b.n	340ad2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d424e>
│ │  	movs	r0, #0
│ │  	b.n	340b96 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d4312>
│ │  	ldrh	r7, [r0, r4]
│ │  			@ <UNDEFINED> instruction: 0xebfe0000
│ │  	b.n	340b9e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d431a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r5, r6, r7, r8, sl, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r5, r9, sl, sp, lr, pc}
│ │  	vqrdmulh.s16	q12, <illegal reg q2.5>, d5[0]
│ │  	vaddl.u16	<illegal reg q9.5>, d3, d1
│ │  	b.n	3407ae <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3f2a>
│ │  	asrs	r0, r0, #32
│ │  	b.n	340bb2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d432e>
│ │  	vpmin.u<illegal width 64>	q7, <illegal reg q11.5>, <illegal reg q15.5>
│ │  	movs	r0, #1
│ │ @@ -864906,15 +864906,15 @@
│ │  	asrs	r0, r1, #32
│ │  	b.n	33ffc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3744>
│ │  	movs	r0, #62	@ 0x3e
│ │  	b.n	340bce <uniffi_pbcli_checksum_method_api_base@@Base+0x1d434a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3405b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3d2c>
│ │  	strb	r5, [r1, #10]
│ │ -			@ <UNDEFINED> instruction: 0xeaffe5a9
│ │ +			@ <UNDEFINED> instruction: 0xeaffe5d0
│ │  			@ <UNDEFINED> instruction: 0xffd5ff11
│ │  	b.n	3406fc <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3e78>
│ │  	vrhadd.u16	d14, d2, d31
│ │  	vrhadd.u16	d14, d1, d31
│ │  	vrhadd.u16	d14, d2, d31
│ │  	ldr	r4, [pc, #448]	@ (34066c <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3de8>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │ @@ -864984,15 +864984,15 @@
│ │  	b.n	340c82 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d43fe>
│ │  	movs	r5, r0
│ │  	b.n	340886 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d4002>
│ │  	lsrs	r3, r2, #8
│ │  	add.w	r0, r0, r6
│ │  	b.n	34088e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d400a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r4, r6, r7, r8, sl, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r5, r6, r7, r8, sl, fp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd57d80
│ │  			@ <UNDEFINED> instruction: 0xffd44df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	340a7c <uniffi_pbcli_checksum_method_api_base@@Base+0x1d41f8>
│ │  	beq.n	340584 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3d00>
│ │  	b.n	340a00 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d417c>
│ │  	strh	r3, [r0, #0]
│ │ @@ -865058,15 +865058,15 @@
│ │  	asrs	r3, r0, #32
│ │  	b.n	34092e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d40aa>
│ │  	movs	r0, #2
│ │  	b.n	340710 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3e8c>
│ │  	adds	r0, #60	@ 0x3c
│ │  	b.n	340d36 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d44b2>
│ │  	strb	r7, [r5, #28]
│ │ -			@ <UNDEFINED> instruction: 0xeaffccf9
│ │ +			@ <UNDEFINED> instruction: 0xeaffcd20
│ │  			@ <UNDEFINED> instruction: 0xffd54c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	340b20 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d429c>
│ │  	ands	r2, r0
│ │  	b.n	34094a <uniffi_pbcli_checksum_method_api_base@@Base+0x1d40c6>
│ │  	str	r1, [r0, r0]
│ │  	b.n	34094e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d40ca>
│ │ @@ -865098,15 +865098,15 @@
│ │  	b.n	34098a <uniffi_pbcli_checksum_method_api_base@@Base+0x1d4106>
│ │  	adds	r0, #71	@ 0x47
│ │  	b.n	340d8e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d450a>
│ │  	movs	r0, #2
│ │  	b.n	340770 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3eec>
│ │  	ldr	r4, [pc, #448]	@ (340814 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3f90>)
│ │  	ldmia.w	sp!, {r0, r1, r2, r4, r8, r9, sl, ip, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xeaffcc99
│ │ +			@ <UNDEFINED> instruction: 0xeaffccc0
│ │  			@ <UNDEFINED> instruction: 0xffd54c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	340b80 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d42fc>
│ │  	str	r1, [r0, r0]
│ │  	b.n	3409aa <uniffi_pbcli_checksum_method_api_base@@Base+0x1d4126>
│ │  	movs	r0, r0
│ │  	b.n	340dae <uniffi_pbcli_checksum_method_api_base@@Base+0x1d452a>
│ │ @@ -865183,15 +865183,15 @@
│ │  	b.n	340e4e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d45ca>
│ │  	ands	r0, r0
│ │  	b.n	340e52 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d45ce>
│ │  	ldrh	r0, [r3, r1]
│ │  			@ <UNDEFINED> instruction: 0xebfe0004
│ │  	b.n	340a5a <uniffi_pbcli_checksum_method_api_base@@Base+0x1d41d6>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r6, r7, r8, r9, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r4, sl, fp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd549f3
│ │  			@ <UNDEFINED> instruction: 0xffd44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	340c48 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d43c4>
│ │  	beq.n	340748 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3ec4>
│ │  	b.n	340bcc <uniffi_pbcli_checksum_method_api_base@@Base+0x1d4348>
│ │  	strb	r3, [r0, #0]
│ │ @@ -865276,44 +865276,44 @@
│ │  	b.n	340900 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d407c>
│ │  	strb	r1, [r7, #6]
│ │  			@ <UNDEFINED> instruction: 0xebff0009
│ │  	b.n	340b2a <uniffi_pbcli_checksum_method_api_base@@Base+0x1d42a6>
│ │  	beq.n	340824 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3fa0>
│ │  	b.n	340c84 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d4400>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r7, r8, r9, fp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd5cb09
│ │ +	ldmia.w	sp!, {r2, r3, r5, r7, r8, r9, fp, lr, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffd5cb30
│ │  	vaddl.u16	<illegal reg q9.5>, d5, d2
│ │  	b.n	340b3e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d42ba>
│ │  	movs	r0, #16
│ │  	b.n	340340 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3abc>
│ │  	movs	r1, r0
│ │  	b.n	340b46 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d42c2>
│ │  	asrs	r3, r0, #32
│ │  	b.n	340b4a <uniffi_pbcli_checksum_method_api_base@@Base+0x1d42c6>
│ │  	movs	r0, #2
│ │  	b.n	34092c <uniffi_pbcli_checksum_method_api_base@@Base+0x1d40a8>
│ │  	adds	r0, #125	@ 0x7d
│ │  	b.n	340f52 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d46ce>
│ │  	strb	r1, [r1, #9]
│ │ -			@ <UNDEFINED> instruction: 0xeaffcadd
│ │ +			@ <UNDEFINED> instruction: 0xeaffcb04
│ │  	vaddl.u16	<illegal reg q9.5>, d5, d2
│ │  	b.n	340b5e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d42da>
│ │  	movs	r0, #16
│ │  	b.n	340360 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3adc>
│ │  	movs	r1, r0
│ │  	b.n	340b66 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d42e2>
│ │  	asrs	r3, r0, #32
│ │  	b.n	340b6a <uniffi_pbcli_checksum_method_api_base@@Base+0x1d42e6>
│ │  	movs	r0, #2
│ │  	b.n	34094c <uniffi_pbcli_checksum_method_api_base@@Base+0x1d40c8>
│ │  	adds	r0, #131	@ 0x83
│ │  	b.n	340f72 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d46ee>
│ │  	strb	r1, [r0, #9]
│ │ -			@ <UNDEFINED> instruction: 0xeaffcabd
│ │ +			@ <UNDEFINED> instruction: 0xeaffcae4
│ │  	vmlal.u16	q10, d5, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	340b82 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d42fe>
│ │  	asrs	r0, r0, #32
│ │  	b.n	340366 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3ae2>
│ │  	asrs	r4, r6, #32
│ │  	b.n	34036c <uniffi_pbcli_checksum_method_api_base@@Base+0x1d3ae8>
│ │ @@ -865917,22 +865917,22 @@
│ │  			@ <UNDEFINED> instruction: 0xebfe1103
│ │  	b.n	3413aa <uniffi_pbcli_checksum_method_api_base@@Base+0x1d4b26>
│ │  	asrs	r4, r1, #32
│ │  	b.n	34142e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d4baa>
│ │  			@ <UNDEFINED> instruction: 0xffa2eaff
│ │  	adds	r3, r4, r7
│ │  	vqshlu.s64	d17, d31, #20
│ │ -	vqrshrun.s32	d21, q13, #12
│ │ +	vmlal.u16	<illegal reg q10.5>, d20, d17
│ │  	vsli.64	d17, d31, #21
│ │  	vqshlu.s16	d17, d23, #4
│ │  	vrsubhn.i32	d17, q2, <illegal reg q1.5>
│ │ -	vqshl.u64	d21, d30, #20
│ │ +			@ <UNDEFINED> instruction: 0xffd457e5
│ │  	vabal.u16	<illegal reg q8.5>, d21, d3
│ │  	vmls.f16	<illegal reg q8.5>, q2, d7[1]
│ │ -	vabdl.u16	<illegal reg q10.5>, d4, d10
│ │ +	vqshl.u16	d21, d17, #4
│ │  	vaddl.u16	q8, d5, d0
│ │  	b.n	34147e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d4bfa>
│ │  	movs	r5, r0
│ │  	lsrs	r0, r0, #8
│ │  	movs	r0, r2
│ │  	b.n	3412e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d4a62>
│ │  	subs	r7, r3, #6
│ │ @@ -866202,18 +866202,18 @@
│ │  			@ <UNDEFINED> instruction: 0xebff0009
│ │  	b.n	34138e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d4b0a>
│ │  	movs	r6, r0
│ │  	add.w	r0, r0, r0
│ │  	b.n	341796 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d4f12>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r0, r1, r3, r5, r6, r8, r9, ip}
│ │ -	vaddw.u16	<illegal reg q15.5>, q2, d23
│ │ +	vmla.f16	<illegal reg q15.5>, q2, d6[1]
│ │  			@ <UNDEFINED> instruction: 0xffd513cf
│ │  	vrshr.u64	<illegal reg q8.5>, <illegal reg q7.5>, #44
│ │ -	vshr.u64	d31, d11, #44
│ │ +	vmla.i16	<illegal reg q15.5>, q10, d2[0]
│ │  			@ <UNDEFINED> instruction: 0xffd54df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	341590 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d4d0c>
│ │  	movs	r0, r0
│ │  	b.n	34171a <uniffi_pbcli_checksum_method_api_base@@Base+0x1d4e96>
│ │  	movs	r3, r6
│ │  	lsrs	r0, r0, #8
│ │ @@ -866646,15 +866646,15 @@
│ │  	b.n	341b76 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d52f2>
│ │  	subs	r7, r1, #6
│ │  	b.n	341b7a <uniffi_pbcli_checksum_method_api_base@@Base+0x1d52f6>
│ │  			@ <UNDEFINED> instruction: 0xffc2eaff
│ │  	ands	r1, r0
│ │  	b.n	341b82 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d52fe>
│ │  			@ <UNDEFINED> instruction: 0xffcceaff
│ │ -	bvc.n	341506 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d4c82>
│ │ +	bvc.n	341354 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d4ad0>
│ │  			@ <UNDEFINED> instruction: 0xffd50f8b
│ │  	vmul.i16	q14, q2, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffd34df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	341974 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d50f0>
│ │  	beq.n	34146c <uniffi_pbcli_checksum_method_api_base@@Base+0x1d4be8>
│ │  	b.n	3418f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d5074>
│ │ @@ -867444,15 +867444,15 @@
│ │  			@ <UNDEFINED> instruction: 0xebfe0005
│ │  	b.n	341e7a <uniffi_pbcli_checksum_method_api_base@@Base+0x1d55f6>
│ │  	stc2l	11, cr14, [fp, #-1020]	@ 0xfffffc04	@ <UNPREDICTABLE>
│ │  	str	r0, [r1, #0]
│ │  	b.n	34164a <uniffi_pbcli_checksum_method_api_base@@Base+0x1d4dc6>
│ │  			@ <UNDEFINED> instruction: 0xffd3eaff
│ │  	subs	r5, r0, #6
│ │ -			@ <UNDEFINED> instruction: 0xffd42b44
│ │ +			@ <UNDEFINED> instruction: 0xffd42b6b
│ │  			@ <UNDEFINED> instruction: 0xffd64df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	342070 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d57ec>
│ │  	beq.n	341b78 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d52f4>
│ │  	b.n	341ff4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d5770>
│ │  	strh	r3, [r0, #0]
│ │  	b.n	341e9e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d561a>
│ │ @@ -867540,15 +867540,15 @@
│ │  	strb	r0, [r3, r4]
│ │  			@ <UNDEFINED> instruction: 0xebfe0000
│ │  	b.n	3423da <uniffi_pbcli_checksum_method_api_base@@Base+0x1d5b56>
│ │  	beq.n	341c4c <uniffi_pbcli_checksum_method_api_base@@Base+0x1d53c8>
│ │  	b.n	3420b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d5830>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, r5, r7, r9, sl, fp, ip}
│ │ -	vmull.u16	q9, d4, d5[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd42a74
│ │  			@ <UNDEFINED> instruction: 0xffd64df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	34214c <uniffi_pbcli_checksum_method_api_base@@Base+0x1d58c8>
│ │  	asrs	r5, r0, #32
│ │  	b.n	342376 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d5af2>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	341f7a <uniffi_pbcli_checksum_method_api_base@@Base+0x1d56f6>
│ │ @@ -868756,20 +868756,20 @@
│ │  	b.n	342ba4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6320>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, r2, r3, r4, r7, r8, fp, ip, sp}
│ │  	vrsubhn.i32	d17, q3, <illegal reg q2.5>
│ │  			@ <UNDEFINED> instruction: 0xffd42c7a
│ │  	vsli.64	<illegal reg q8.5>, <illegal reg q4.5>, #20
│ │  	vqdmulh.s16	q9, q2, d6[1]
│ │ -	vsri.16	<illegal reg q11.5>, q5, #12
│ │ -	vsli.64	<illegal reg q12.5>, q10, #21
│ │ -	vraddhn.i32	d23, <illegal reg q2.5>, q15
│ │ +	vraddhn.i32	d23, q10, <illegal reg q0.5>
│ │ +	vqshlu.s16	d25, d11, #5
│ │ +	vsri.16	<illegal reg q11.5>, <illegal reg q2.5>, #11
│ │  			@ <UNDEFINED> instruction: 0xffd55d1c
│ │  			@ <UNDEFINED> instruction: 0xffd35cf8
│ │ -			@ <UNDEFINED> instruction: 0xffd3cefd
│ │ +			@ <UNDEFINED> instruction: 0xffd3cf24
│ │  	vabal.u16	q15, d5, d17
│ │  	vabal.u16	q15, d3, d1
│ │  			@ <UNDEFINED> instruction: 0xffd307ee
│ │  	vrsubhn.i32	d27, q10, <illegal reg q7.5>
│ │  	vqshlu.s16	<illegal reg q13.5>, <illegal reg q9.5>, #4
│ │  			@ <UNDEFINED> instruction: 0xffd42af0
│ │  			@ <UNDEFINED> instruction: 0xffd4736b
│ │ @@ -869212,24 +869212,24 @@
│ │  	b.n	34265c <uniffi_pbcli_checksum_method_api_base@@Base+0x1d5dd8>
│ │  	movs	r0, r1
│ │  	b.n	342680 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d5dfc>
│ │  	beq.n	342b80 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d62fc>
│ │  	b.n	342fe0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d675c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r4, r7, r8, r9, sl, fp}
│ │ -	vsri.16	q8, q0, #12
│ │ +	vsri.16	q8, <illegal reg q11.5>, #12
│ │  	vrsra.u16	<illegal reg q13.5>, <illegal reg q12.5>, #10
│ │  	vrshr.u16	d17, d17, #13
│ │ -	vqrdmlsh.s16	q11, q10, d2[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd46ff1
│ │  	vqshrn.u32	d21, q12, #11
│ │ -			@ <UNDEFINED> instruction: 0xffd3cb61
│ │ +			@ <UNDEFINED> instruction: 0xffd3cb88
│ │  			@ <UNDEFINED> instruction: 0xffd5bbd2
│ │ -	vsubw.u16	<illegal reg q12.5>, q10, d11
│ │ -	vqshlu.s16	d16, d4, #5
│ │ -	vsra.u64	d26, d6, #42
│ │ +	vrsra.u64	d25, d18, #44
│ │ +	vqshlu.s16	d16, d27, #5
│ │ +	vsra.u64	d26, d29, #42
│ │  			@ <UNDEFINED> instruction: 0xffd5ff1e
│ │  	b.n	342ddc <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6558>
│ │  	ldr	r0, [pc, #192]	@ (342c40 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d63bc>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3430a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d681c>
│ │  	beq.n	342b98 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6314>
│ │  	b.n	343024 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d67a0>
│ │ @@ -869460,17 +869460,17 @@
│ │  	b.n	3434be <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6c3a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	342ea0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d661c>
│ │  	ldr	r1, [r2, #4]
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	3434ca <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6c46>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r3, r4, r6, r7, r8, r9, ip, lr, pc}
│ │ -	vsubw.u16	<illegal reg q14.5>, <illegal reg q10.5>, d0
│ │ -	vrsra.u16	d29, d28, #11
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, ip, lr, pc}
│ │ +	vsubw.u16	<illegal reg q14.5>, <illegal reg q10.5>, d23
│ │ +			@ <UNDEFINED> instruction: 0xffd5d363
│ │  	vaddl.u16	q8, d5, d0
│ │  	b.n	34343e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6bba>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (342de4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6560>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3432c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6a40>
│ │  	ands	r0, r0
│ │ @@ -869512,17 +869512,17 @@
│ │  	b.n	34313a <uniffi_pbcli_checksum_method_api_base@@Base+0x1d68b6>
│ │  	movs	r0, #106	@ 0x6a
│ │  	b.n	34353e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6cba>
│ │  	asrs	r1, r0, #32
│ │  	b.n	342f20 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d669c>
│ │  	ldr	r4, [pc, #64]	@ (342e44 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d65c0>)
│ │  	ldmia.w	sp!, {r4, r5, fp, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xeaffd2e4
│ │ -	vrshr.u64	<illegal reg q14.5>, q0, #43
│ │ -	vrshr.u64	d29, d28, #43
│ │ +			@ <UNDEFINED> instruction: 0xeaffd30b
│ │ +	vrshr.u64	<illegal reg q14.5>, <illegal reg q11.5>, #43
│ │ +	vmlal.u16	<illegal reg q14.5>, d21, d3[2]
│ │  	vaddl.u16	q8, d5, d0
│ │  	b.n	34293a <uniffi_pbcli_checksum_method_api_base@@Base+0x1d60b6>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r4, r0
│ │  	b.n	342942 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d60be>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	asrs	r0, r0, #32
│ │ @@ -869679,19 +869679,19 @@
│ │  	str	r4, [r0, r0]
│ │  	lsls	r4, r0, #22
│ │  	movs	r5, r0
│ │  	b.n	3432b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6a32>
│ │  	beq.n	342fa8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6724>
│ │  	b.n	343410 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6b8c>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r2, r3, r4, r7, r8, ip, lr, pc}
│ │ -	vsri.16	q13, <illegal reg q5.5>, #11
│ │ -	vmla.f16	<illegal reg q14.5>, <illegal reg q10.5>, d4[3]
│ │ -	vraddhn.i32	d26, <illegal reg q10.5>, <illegal reg q13.5>
│ │ -			@ <UNDEFINED> instruction: 0xffd58dd3
│ │ +	ldmia.w	sp!, {r0, r1, r6, r7, r8, ip, lr, pc}
│ │ +	vraddhn.i32	d26, <illegal reg q10.5>, q1
│ │ +	vrshr.u16	d29, d3, #11
│ │ +	vsri.64	q13, q1, #43
│ │ +			@ <UNDEFINED> instruction: 0xffd58dfa
│ │  			@ <UNDEFINED> instruction: 0xffd54df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3434b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6c30>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3432de <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6a5a>
│ │  	movs	r4, r0
│ │  	b.n	342ac2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d623e>
│ │ @@ -869825,17 +869825,17 @@
│ │  			@ <UNDEFINED> instruction: 0xebff6018
│ │  	b.n	342bc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6344>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	342bcc <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6348>
│ │  	movs	r4, r0
│ │  	b.n	343406 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6b82>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r2, r3, r4, r5, r7, ip, lr, pc}
│ │ -	vaddl.u16	<illegal reg q14.5>, d5, d28
│ │ -	vshr.u64	d29, d4, #43
│ │ +	ldmia.w	sp!, {r0, r1, r5, r6, r7, ip, lr, pc}
│ │ +	vshr.u16	<illegal reg q14.5>, <illegal reg q1.5>, #11
│ │ +	vshr.u64	d29, d27, #43
│ │  			@ <UNDEFINED> instruction: 0xffd5da59
│ │  			@ <UNDEFINED> instruction: 0xffd44df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3435fc <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6d78>
│ │  	str	r0, [r0, #0]
│ │  	b.n	343426 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6ba2>
│ │  	str	r1, [r0, r0]
│ │ @@ -869966,20 +869966,20 @@
│ │  	b.n	342d06 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6482>
│ │  	movs	r4, r0
│ │  	b.n	34353e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6cba>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {}
│ │  	b.n	343946 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d70c2>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r2, r3, r5, r7, r8, r9, sl, fp, lr, pc}
│ │ -	vsubl.u16	q13, d21, d7
│ │ -			@ <UNDEFINED> instruction: 0xffd5cf2c
│ │ -	vsubl.u16	q13, d5, d7
│ │ -	vqrdmlsh.s16	q14, <illegal reg q2.5>, d0[1]
│ │ -	vsubl.u16	q13, d5, d19
│ │ +	ldmia.w	sp!, {r0, r1, r4, r6, r7, r8, r9, sl, fp, lr, pc}
│ │ +	vsubl.u16	q13, d21, d30
│ │ +			@ <UNDEFINED> instruction: 0xffd5cf53
│ │ +	vsubl.u16	q13, d5, d30
│ │ +	vqrdmlsh.s16	q14, <illegal reg q2.5>, d7[3]
│ │ +	vmlal.u16	q13, d5, d2[1]
│ │  	vqshrun.s32	d20, q8, #11
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	343744 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6ec0>
│ │  	ands	r0, r0
│ │  	b.n	34396e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d70ea>
│ │  	movs	r0, r0
│ │  	b.n	3438d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d7050>
│ │ @@ -870056,18 +870056,18 @@
│ │  	b.n	343a0e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d718a>
│ │  	movs	r0, #0
│ │  	b.n	343a12 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d718e>
│ │  	ldr	r7, [pc, #416]	@ (343474 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6bf0>)
│ │  			@ <UNDEFINED> instruction: 0xebfe0004
│ │  	b.n	34361a <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6d96>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r2, r3, r4, r6, r9, sl, fp, lr, pc}
│ │ -	vraddhn.i32	d17, <illegal reg q2.5>, q7
│ │ -	vmull.p<illegal width 16>	q14, d6, d8
│ │ -	vrsra.u64	d17, d26, #43
│ │ +	ldmia.w	sp!, {r0, r1, r7, r9, sl, fp, lr, pc}
│ │ +	vsri.16	d17, d21, #11
│ │ +	vmull.p<illegal width 16>	q14, d6, d31
│ │ +			@ <UNDEFINED> instruction: 0xffd513e1
│ │  			@ <UNDEFINED> instruction: 0xffd64c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	343810 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6f8c>
│ │  	adds	r0, #4
│ │  	b.n	342e1a <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6596>
│ │  	ands	r0, r3
│ │  	b.n	342e1e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d659a>
│ │ @@ -870114,15 +870114,15 @@
│ │  	asrs	r2, r0, #32
│ │  	asrs	r4, r1, #2
│ │  	asrs	r4, r3, #32
│ │  	asrs	r0, r0, #22
│ │  	movs	r4, r0
│ │  	b.n	3436a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6e1e>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r5, r7, r8, sl, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r6, r7, r8, sl, fp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd51e14
│ │  			@ <UNDEFINED> instruction: 0xffd44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	343890 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d700c>
│ │  	beq.n	343390 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6b0c>
│ │  	b.n	343814 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d6f90>
│ │  	str	r0, [sp, #32]
│ │ @@ -875587,21 +875587,21 @@
│ │  	mvns	r6, r4
│ │  			@ <UNDEFINED> instruction: 0xebfe0004
│ │  	b.n	34672e <uniffi_pbcli_checksum_method_api_base@@Base+0x1d9eaa>
│ │  	asrs	r6, r3, #2
│ │  	b.n	346732 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d9eae>
│ │  			@ <UNDEFINED> instruction: 0xffcfeaff
│ │  	ldrb	r3, [r3, #23]
│ │ -	vsubl.u16	q13, d4, d16
│ │ +	vmlal.u16	q13, d4, d7[0]
│ │  			@ <UNDEFINED> instruction: 0xffd57d93
│ │  	vrsra.u64	d18, d18, #44
│ │  	vqrdmulh.s16	<illegal reg q11.5>, q2, d7[2]
│ │ -	vaddw.u16	q13, q10, d28
│ │ +	vsra.u64	q13, <illegal reg q1.5>, #44
│ │  	vmull.u16	<illegal reg q11.5>, d21, d27
│ │ -	vshr.u64	q13, q8, #44
│ │ +	vsra.u16	d26, d7, #12
│ │  	vqshrun.s32	d20, q8, #11
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	346538 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d9cb4>
│ │  	beq.n	346030 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d97ac>
│ │  	b.n	3464bc <uniffi_pbcli_checksum_method_api_base@@Base+0x1d9c38>
│ │  	str	r3, [r0, r0]
│ │  	b.n	346366 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d9ae2>
│ │ @@ -876124,17 +876124,17 @@
│ │  	push	{r0, r2, r6}
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3467f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d9f6e>
│ │  	beq.n	3464d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d9c50>
│ │  	b.n	34694c <uniffi_pbcli_checksum_method_api_base@@Base+0x1da0c8>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r1, r2, fp, ip, sp, lr}
│ │ -	vqdmulh.s16	<illegal reg q12.5>, q2, d0[2]
│ │ +	vmull.u16	<illegal reg q12.5>, d20, d7
│ │  	vqrshrun.s32	d23, <illegal reg q7.5>, #11
│ │ -			@ <UNDEFINED> instruction: 0xffd49cb8
│ │ +			@ <UNDEFINED> instruction: 0xffd49cdf
│ │  	vaddl.u16	<illegal reg q9.5>, d5, d1
│ │  	b.n	346c0e <uniffi_pbcli_checksum_method_api_base@@Base+0x1da38a>
│ │  	lsls	r6, r3, #6
│ │  	and.w	r0, r0, r4, lsr #32
│ │  	b.n	345ff6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d9772>
│ │  	lsrs	r3, r7, #18
│ │  	and.w	r0, r0, r4, lsr #32
│ │ @@ -876218,15 +876218,15 @@
│ │  	b.n	346cce <uniffi_pbcli_checksum_method_api_base@@Base+0x1da44a>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {ip, sp, lr}
│ │  	b.n	346cd6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1da452>
│ │  	movs	r7, r0
│ │  	b.n	3468da <uniffi_pbcli_checksum_method_api_base@@Base+0x1da056>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r1, r3, r4, sp}
│ │ +	ldmia.w	sp!, {r0, r6, sp}
│ │  	vshr.u16	d16, d4, #11
│ │  	b.n	3460c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d9842>
│ │  	asrs	r2, r1, #18
│ │  	and.w	ip, r0, r0, ror #17
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	346acc <uniffi_pbcli_checksum_method_api_base@@Base+0x1da248>
│ │  	beq.n	3465e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d9d60>
│ │ @@ -877350,32 +877350,32 @@
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {ip, sp, lr}
│ │  	b.n	3476a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dae1e>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │  	add	r6, pc, #388	@ (adr r6, 3470ec <uniffi_pbcli_checksum_method_api_base@@Base+0x1da868>)
│ │  	vsri.64	d22, d8, #44
│ │  	vsra.u64	<illegal reg q15.5>, <illegal reg q6.5>, #44
│ │ -			@ <UNDEFINED> instruction: 0xffd57e5a
│ │ -	vqshl.u16	q11, q3, #5
│ │ +	vmull.p<illegal width 16>	<illegal reg q11.5>, d21, d1
│ │ +	vqshl.u16	q11, <illegal reg q14.5>, #5
│ │  	vmlsl.u16	<illegal reg q13.5>, d21, d2[2]
│ │  	vmull.u16	q13, d19, d18
│ │  	vshr.u64	d23, d9, #45
│ │  	vqshl.u16	d24, d5, #4
│ │  	vmls.i16	q9, q10, d4[2]
│ │  			@ <UNDEFINED> instruction: 0xffd39e12
│ │  	vabal.u16	<illegal reg q8.5>, d19, d23
│ │ -	vqrdmulh.s16	<illegal reg q11.5>, q2, d4[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd47d93
│ │  			@ <UNDEFINED> instruction: 0xffd59d96
│ │  			@ <UNDEFINED> instruction: 0xffd39cf4
│ │  	vqrdmlsh.s16	q15, q2, d5[1]
│ │ -	vqshlu.s16	d24, d10, #5
│ │ +	vmlsl.u16	q12, d5, d1[0]
│ │  	vsubw.u16	q9, <illegal reg q2.5>, d2
│ │ -	vsli.64	d24, d26, #19
│ │ +	vmls.f16	q12, <illegal reg q9.5>, d1[2]
│ │  	vrsra.u64	d18, d29, #43
│ │ -	vqshlu.s16	q12, q13, #3
│ │ +	vrsubhn.i32	d24, <illegal reg q9.5>, <illegal reg q8.5>
│ │  			@ <UNDEFINED> instruction: 0xffd54bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3474dc <uniffi_pbcli_checksum_method_api_base@@Base+0x1dac58>
│ │  	strh	r2, [r0, #0]
│ │  	b.n	347306 <uniffi_pbcli_checksum_method_api_base@@Base+0x1daa82>
│ │  	str	r1, [r0, r0]
│ │  	b.n	34730a <uniffi_pbcli_checksum_method_api_base@@Base+0x1daa86>
│ │ @@ -877728,32 +877728,32 @@
│ │  	b.n	3473f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dab70>
│ │  	bvc.n	347314 <uniffi_pbcli_checksum_method_api_base@@Base+0x1daa90>
│ │  			@ <UNDEFINED> instruction: 0xebfc7001
│ │  	b.n	347a1e <uniffi_pbcli_checksum_method_api_base@@Base+0x1db19a>
│ │  			@ <UNDEFINED> instruction: 0xffabeaff
│ │  	strh	r7, [r4, #20]
│ │  	vmlal.u16	q10, d4, d7[2]
│ │ -	vshll.u16	<illegal reg q11.5>, d11, #4
│ │ -	vsli.16	<illegal reg q8.5>, q1, #5
│ │ -	vrsra.u16	q11, <illegal reg q3.5>, #11
│ │ -	vsri.64	<illegal reg q9.5>, <illegal reg q1.5>, #43
│ │ -	vsri.64	d17, d6, #43
│ │ -	vqshrun.s32	d26, <illegal reg q3.5>, #11
│ │ +	vmull.u16	<illegal reg q11.5>, d4, d2[0]
│ │ +	vsli.16	<illegal reg q8.5>, <illegal reg q12.5>, #5
│ │ +	vrsra.u16	q11, q15, #11
│ │ +	vsri.64	<illegal reg q9.5>, q13, #43
│ │ +	vsri.64	d17, d29, #43
│ │ +	vqshrun.s32	d26, q15, #11
│ │  	vmul.f16	q14, <illegal reg q2.5>, d0[3]
│ │  	vsli.64	<illegal reg q10.5>, <illegal reg q3.5>, #19
│ │  	vsubw.u16	q12, q10, d25
│ │ -	vsubw.u16	<illegal reg q8.5>, <illegal reg q9.5>, d30
│ │ +	vrsra.u64	<illegal reg q8.5>, <illegal reg q2.5>, #45
│ │  	vqshrun.s32	d28, <illegal reg q2.5>, #11
│ │ -	vsubl.u16	q12, d20, d26
│ │ -	vqshl.u16	d26, d20, #5
│ │ -			@ <UNDEFINED> instruction: 0xffd53362
│ │ -	vrsra.u16	d17, d6, #11
│ │ +	vrshr.u64	q12, <illegal reg q0.5>, #44
│ │ +	vqshl.u16	q13, <illegal reg q5.5>, #5
│ │ +	vsubw.u16	<illegal reg q9.5>, <illegal reg q10.5>, d9
│ │ +	vrsra.u16	d17, d29, #11
│ │  	vqrshrn.u32	d22, q6, #11
│ │  			@ <UNDEFINED> instruction: 0xffd3c761
│ │ -	vsubl.u16	<illegal reg q8.5>, d20, d22
│ │ +	vmlal.u16	<illegal reg q8.5>, d20, d5[1]
│ │  			@ <UNDEFINED> instruction: 0xffd54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	347854 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dafd0>
│ │  	beq.n	347394 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dab10>
│ │  	b.n	3477d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1daf54>
│ │  	str	r0, [sp, #8]
│ │  	b.n	347682 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dadfe>
│ │ @@ -879169,47 +879169,47 @@
│ │  	b.n	348646 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dbdc2>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3486ca <uniffi_pbcli_checksum_method_api_base@@Base+0x1dbe46>
│ │  			@ <UNDEFINED> instruction: 0xffa8eaff
│ │  			@ <UNDEFINED> instruction: 0xb8dd
│ │  			@ <UNDEFINED> instruction: 0xffd489be
│ │  	vaddl.u16	<illegal reg q9.5>, d4, d28
│ │ -	vmull.u16	q9, d3, d15
│ │ +			@ <UNDEFINED> instruction: 0xffd32c36
│ │  	vrsubhn.i32	d26, <illegal reg q10.5>, q3
│ │ -	vsubl.u16	<illegal reg q10.5>, d20, d30
│ │ +	vrshr.u64	<illegal reg q10.5>, <illegal reg q2.5>, #44
│ │  			@ <UNDEFINED> instruction: 0xffd52d9c
│ │ -	vqrshrn.u32	d18, <illegal reg q15.5>, #13
│ │ +			@ <UNDEFINED> instruction: 0xffd329a6
│ │  			@ <UNDEFINED> instruction: 0xffd5cd3b
│ │ -			@ <UNDEFINED> instruction: 0xffd47e90
│ │ +			@ <UNDEFINED> instruction: 0xffd47eb7
│ │  			@ <UNDEFINED> instruction: 0xffd52eb0
│ │ -			@ <UNDEFINED> instruction: 0xffd32a93
│ │ +			@ <UNDEFINED> instruction: 0xffd32aba
│ │  			@ <UNDEFINED> instruction: 0xffd55908
│ │  	movs	r1, r3
│ │  	ldr	r4, [r4, r1]
│ │  	movs	r1, r3
│ │  	ldr	r0, [r1, r1]
│ │  	movs	r1, r3
│ │  	cmp	r3, #168	@ 0xa8
│ │ -	vabdl.u16	q9, d19, d11
│ │ +	vqshl.u64	d18, d18, #19
│ │  			@ <UNDEFINED> instruction: 0xffd52b74
│ │ -	vqshl.u16	q9, <illegal reg q3.5>, #3
│ │ +	vqshl.u16	q9, q15, #3
│ │  	vshll.u16	q9, d28, #5
│ │ -	vqshlu.s16	d18, d15, #3
│ │ +	vmlsl.u16	q9, d3, d6[0]
│ │  	vmull.u16	q9, d21, d4[1]
│ │ -	vrsubhn.i32	d18, <illegal reg q9.5>, <illegal reg q15.5>
│ │ +	vqshlu.s64	q9, q3, #19
│ │  	vmlsl.u16	q9, d5, d16
│ │ -	vrsubhn.i32	d18, <illegal reg q1.5>, <illegal reg q1.5>
│ │ +	vrsubhn.i32	d18, <illegal reg q1.5>, q13
│ │  			@ <UNDEFINED> instruction: 0xffd52a58
│ │ -	vqshlu.s16	d18, d27, #3
│ │ +	vmlsl.u16	q9, d3, d2[2]
│ │  			@ <UNDEFINED> instruction: 0xffd52cb8
│ │ -			@ <UNDEFINED> instruction: 0xffd3289b
│ │ +	vmul.i16	q9, <illegal reg q9.5>, d2[0]
│ │  	vqrdmulh.s16	q12, <illegal reg q2.5>, d1[0]
│ │  	vmull.u16	q9, d4, d4
│ │ -			@ <UNDEFINED> instruction: 0xffd327e7
│ │ -			@ <UNDEFINED> instruction: 0xffd59b67
│ │ +	vmlal.u16	q9, d3, d14
│ │ +			@ <UNDEFINED> instruction: 0xffd59b8e
│ │  	vmul.i16	<illegal reg q10.5>, <illegal reg q2.5>, d0[1]
│ │  	movs	r1, r3
│ │  	ldr	r3, [pc, #960]	@ (348418 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dbb94>)
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	348578 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dbcf4>
│ │  	beq.n	348070 <uniffi_pbcli_checksum_method_api_base@@Base+0x1db7ec>
│ │  	b.n	3484fc <uniffi_pbcli_checksum_method_api_base@@Base+0x1dbc78>
│ │ @@ -879444,15 +879444,15 @@
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	34890a <uniffi_pbcli_checksum_method_api_base@@Base+0x1dc086>
│ │  	ands	r1, r0
│ │  	asrs	r0, r4, #14
│ │  			@ <UNDEFINED> instruction: 0xffb5eaff
│ │  	sub	sp, #36	@ 0x24
│ │  	vmla.f16	q12, q2, d2[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd44b32
│ │ +			@ <UNDEFINED> instruction: 0xffd44b59
│ │  	vrshr.u64	d21, d4, #43
│ │  	movs	r1, r3
│ │  	strh	r0, [r7, r1]
│ │  	movs	r1, r3
│ │  	strh	r4, [r3, r1]
│ │  	movs	r1, r3
│ │  	ldr	r7, [pc, #960]	@ (34864c <uniffi_pbcli_checksum_method_api_base@@Base+0x1dbdc8>)
│ │ @@ -879628,16 +879628,16 @@
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {}
│ │  	b.n	348b4a <uniffi_pbcli_checksum_method_api_base@@Base+0x1dc2c6>
│ │  	beq.n	348444 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dbbc0>
│ │  	b.n	3488a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dc020>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r2, r3, r4, r7, r9, sl, fp, ip, sp, lr, pc}
│ │ -	vqshl.u16	d22, d22, #2
│ │ -	vrshr.u16	d29, d6, #11
│ │ +	vqshl.u16	q11, <illegal reg q6.5>, #2
│ │ +	vrshr.u16	d29, d29, #11
│ │  	vqrdmlah.s16	q8, <illegal reg q2.5>, d5[0]
│ │  			@ <UNDEFINED> instruction: 0xffd44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	348944 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dc0c0>
│ │  	beq.n	348454 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dbbd0>
│ │  	b.n	3488c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dc044>
│ │  	movs	r0, r0
│ │ @@ -879967,18 +879967,18 @@
│ │  	b.n	348a3a <uniffi_pbcli_checksum_method_api_base@@Base+0x1dc1b6>
│ │  	cmp	r4, sp
│ │  			@ <UNDEFINED> instruction: 0xebfe0005
│ │  	b.n	348a42 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dc1be>
│ │  	beq.n	34873c <uniffi_pbcli_checksum_method_api_base@@Base+0x1dbeb8>
│ │  	b.n	348b9c <uniffi_pbcli_checksum_method_api_base@@Base+0x1dc318>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r3, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r2, r4, r5, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffd5fdb8
│ │ -	vmlsl.u16	q11, d2, d6[2]
│ │ -	vsra.u16	<illegal reg q14.5>, q5, #11
│ │ +	vrsubhn.i32	d22, q9, <illegal reg q6.5>
│ │ +	vaddw.u16	<illegal reg q14.5>, <illegal reg q10.5>, d1
│ │  			@ <UNDEFINED> instruction: 0xffd50d95
│ │  			@ <UNDEFINED> instruction: 0xffd44c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	348c40 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dc3bc>
│ │  	movs	r0, #16
│ │  	b.n	34824a <uniffi_pbcli_checksum_method_api_base@@Base+0x1db9c6>
│ │  	asrs	r0, r0, #32
│ │ @@ -880657,15 +880657,15 @@
│ │  	b.n	349056 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dc7d2>
│ │  			@ <UNDEFINED> instruction: 0xfab9ebff
│ │  	movs	r0, r0
│ │  	b.n	34945e <uniffi_pbcli_checksum_method_api_base@@Base+0x1dcbda>
│ │  			@ <UNDEFINED> instruction: 0xfab7ebff
│ │  			@ <UNDEFINED> instruction: 0xffe7eaff
│ │  	adds	r0, r6, #3
│ │ -	vshr.u16	d19, d24, #13
│ │ +	vshr.u16	<illegal reg q9.5>, <illegal reg q7.5>, #13
│ │  	vqshrun.s32	d20, q8, #11
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	349250 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dc9cc>
│ │  	beq.n	348d58 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dc4d4>
│ │  	b.n	3491d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dc950>
│ │  	asrs	r4, r1, #32
│ │  	b.n	349258 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dc9d4>
│ │ @@ -882371,15 +882371,15 @@
│ │  	b.n	34a3d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ddb4e>
│ │  	ldr	r4, [pc, #564]	@ (349ec8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dd644>)
│ │  			@ <UNDEFINED> instruction: 0xebff0009
│ │  	b.n	349fda <uniffi_pbcli_checksum_method_api_base@@Base+0x1dd756>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r1, r2, r6, r7, sl, fp, sp}
│ │  			@ <UNDEFINED> instruction: 0xffd42bbe
│ │ -			@ <UNDEFINED> instruction: 0xffd4de90
│ │ +			@ <UNDEFINED> instruction: 0xffd4deb7
│ │  			@ <UNDEFINED> instruction: 0xffd42bd6
│ │  			@ <UNDEFINED> instruction: 0xffd44c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	34a1d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dd94c>
│ │  	ands	r0, r0
│ │  	b.n	349ffa <uniffi_pbcli_checksum_method_api_base@@Base+0x1dd776>
│ │  	ldrb	r7, [r4, #12]
│ │ @@ -884535,28 +884535,28 @@
│ │  			@ <UNDEFINED> instruction: 0xebfe0009
│ │  	b.n	34b2d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dea4e>
│ │  	b.n	34b5ec <uniffi_pbcli_checksum_method_api_base@@Base+0x1ded68>
│ │  			@ <UNDEFINED> instruction: 0xebfc0009
│ │  	b.n	34b2da <uniffi_pbcli_checksum_method_api_base@@Base+0x1dea56>
│ │  	b.n	34b480 <uniffi_pbcli_checksum_method_api_base@@Base+0x1debfc>
│ │  			@ <UNDEFINED> instruction: 0xebfcfd7f
│ │ -			@ <UNDEFINED> instruction: 0xeaffc03f
│ │ -			@ <UNDEFINED> instruction: 0xffd45c74
│ │ -			@ <UNDEFINED> instruction: 0xffd5bf77
│ │ -			@ <UNDEFINED> instruction: 0xffd45bac
│ │ -			@ <UNDEFINED> instruction: 0xffd5bfa3
│ │ -			@ <UNDEFINED> instruction: 0xffd45bd8
│ │ -	vqrdmlsh.s16	<illegal reg q13.5>, <illegal reg q10.5>, d7[1]
│ │ -	vmull.u16	<illegal reg q10.5>, d4, d4
│ │ +			@ <UNDEFINED> instruction: 0xeaffc066
│ │ +			@ <UNDEFINED> instruction: 0xffd45c9b
│ │ +			@ <UNDEFINED> instruction: 0xffd5bf9e
│ │ +			@ <UNDEFINED> instruction: 0xffd45bd3
│ │ +	vqrdmlsh.s16	<illegal reg q13.5>, <illegal reg q10.5>, d2[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd45bff
│ │ +			@ <UNDEFINED> instruction: 0xffd5bff6
│ │ +	vmull.u16	<illegal reg q10.5>, d4, d27
│ │  			@ <UNDEFINED> instruction: 0xffd52d00
│ │  	movs	r1, r3
│ │  	movs	r6, #48	@ 0x30
│ │  	movs	r1, r3
│ │ -	push	{r0, r1, r2, r3, r7, lr}
│ │ -	vmla.f16	<illegal reg q10.5>, q10, d4[0]
│ │ +	push	{r1, r2, r4, r5, r7, lr}
│ │ +	vmla.f16	<illegal reg q10.5>, q10, d3[3]
│ │  			@ <UNDEFINED> instruction: 0xffd54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	34b4f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dec70>
│ │  	beq.n	34b024 <uniffi_pbcli_checksum_method_api_base@@Base+0x1de7a0>
│ │  	b.n	34b478 <uniffi_pbcli_checksum_method_api_base@@Base+0x1debf4>
│ │  	str	r0, [r0, r0]
│ │  	b.n	34b322 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dea9e>
│ │ @@ -885437,17 +885437,17 @@
│ │  	add.w	r0, r0, r0, lsl #16
│ │  	b.n	34bee6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1df662>
│ │  	movs	r4, r0
│ │  	b.n	34baea <uniffi_pbcli_checksum_method_api_base@@Base+0x1df266>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r1, r5, r9, sl, sp}
│ │  	vsli.64	d18, d6, #19
│ │ -	vrshr.u64	q11, q4, #45
│ │ +	vrshr.u64	q11, <illegal reg q15.5>, #45
│ │  	vsri.64	d18, d30, #43
│ │ -	vsubl.u16	q11, d3, d0
│ │ +	vsubl.u16	q11, d3, d23
│ │  	vaddl.u16	q8, d5, d12
│ │  	b.n	34b2e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1dea62>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	asrs	r0, r0, #32
│ │  	b.n	34bb0e <uniffi_pbcli_checksum_method_api_base@@Base+0x1df28a>
│ │  	movs	r0, r0
│ │  	b.n	34bf12 <uniffi_pbcli_checksum_method_api_base@@Base+0x1df68e>
│ │ @@ -887757,15 +887757,15 @@
│ │  	beq.n	34cbbc <uniffi_pbcli_checksum_method_api_base@@Base+0x1e0338>
│ │  	b.n	34d034 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e07b0>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r1, r3, r5, r6, r8, ip}
│ │  	vqrdmlsh.s16	q14, <illegal reg q1.5>, d1[2]
│ │  	vqshl.u16	d20, d5, #3
│ │  	vqrdmlah.s16	q10, q2, d0[2]
│ │ -	vqrshrn.u32	d18, q13, #12
│ │ +			@ <UNDEFINED> instruction: 0xffd429a1
│ │  	vshr.u64	d17, d26, #43
│ │  	vmlal.u16	q10, d3, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	34cf02 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e067e>
│ │  	beq.n	34cbd4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e0350>
│ │  	b.n	34d060 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e07dc>
│ │  	movs	r0, r0
│ │ @@ -889836,25 +889836,25 @@
│ │  	movs	r4, #137	@ 0x89
│ │  			@ <UNDEFINED> instruction: 0xebfe0008
│ │  	b.n	34e196 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e1912>
│ │  	b.n	34da76 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e11f2>
│ │  			@ <UNDEFINED> instruction: 0xebfcff40
│ │  			@ <UNDEFINED> instruction: 0xeaff608d
│ │  			@ <UNDEFINED> instruction: 0xffd35f89
│ │ -	vmul.f16	q12, <illegal reg q9.5>, d4[0]
│ │ +	vmul.f16	q12, <illegal reg q9.5>, d3[3]
│ │  			@ <UNDEFINED> instruction: 0xffd45fb1
│ │ -	vmul.f16	q12, <illegal reg q9.5>, d4[3]
│ │ +	vshll.u16	q12, d3, #3
│ │  			@ <UNDEFINED> instruction: 0xffd45db1
│ │ -			@ <UNDEFINED> instruction: 0xffd387ec
│ │ +	vqshrun.s32	d24, <illegal reg q1.5>, #13
│ │  	vqdmulh.s16	<illegal reg q10.5>, q10, d5[0]
│ │ -	vabdl.u16	q12, d3, d0
│ │ +	vabdl.u16	q12, d3, d23
│ │  	vqdmulh.s16	<illegal reg q10.5>, q10, d1[2]
│ │ -	vqshl.u16	d24, d12, #3
│ │ +			@ <UNDEFINED> instruction: 0xffd38743
│ │  			@ <UNDEFINED> instruction: 0xffd45c99
│ │ -	vqshlu.s64	q12, q2, #19
│ │ +	vqshlu.s64	q12, <illegal reg q13.5>, #19
│ │  	vqrdmlsh.s16	<illegal reg q10.5>, q2, d1[1]
│ │  			@ <UNDEFINED> instruction: 0xffd34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	34e3b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e1b34>
│ │  	beq.n	34df48 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e16c4>
│ │  	b.n	34e33c <uniffi_pbcli_checksum_method_api_base@@Base+0x1e1ab8>
│ │  	lsls	r0, r2, #1
│ │ @@ -890539,34 +890539,34 @@
│ │  			@ <UNDEFINED> instruction: 0xebfe0007
│ │  	b.n	34e852 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e1fce>
│ │  	lsrs	r0, r4, #30
│ │  	b.n	34e7d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e1f52>
│ │  	movs	r2, #81	@ 0x51
│ │  			@ <UNDEFINED> instruction: 0xebfefef7
│ │  			@ <UNDEFINED> instruction: 0xeaff5b19
│ │ -			@ <UNDEFINED> instruction: 0xffd3dd7a
│ │ +			@ <UNDEFINED> instruction: 0xffd3dda1
│ │  			@ <UNDEFINED> instruction: 0xffd45b8d
│ │  			@ <UNDEFINED> instruction: 0xffd35b4d
│ │ -			@ <UNDEFINED> instruction: 0xffd3ddae
│ │ +			@ <UNDEFINED> instruction: 0xffd3ddd5
│ │  			@ <UNDEFINED> instruction: 0xffd45a79
│ │ -			@ <UNDEFINED> instruction: 0xffd3dcda
│ │ +			@ <UNDEFINED> instruction: 0xffd3dd01
│ │  	vmlsl.u16	<illegal reg q10.5>, d20, d17
│ │ -			@ <UNDEFINED> instruction: 0xffd3dd02
│ │ +			@ <UNDEFINED> instruction: 0xffd3dd29
│ │  	vqshrun.s32	d21, <illegal reg q14.5>, #12
│ │ -			@ <UNDEFINED> instruction: 0xffd3da9e
│ │ +	vmull.u16	<illegal reg q14.5>, d19, d5[0]
│ │  	vqshl.u16	<illegal reg q10.5>, <illegal reg q0.5>, #4
│ │ -			@ <UNDEFINED> instruction: 0xffd3d9b2
│ │ +			@ <UNDEFINED> instruction: 0xffd3d9d9
│ │  			@ <UNDEFINED> instruction: 0xffd4576d
│ │ -	vmul.f16	<illegal reg q14.5>, <illegal reg q9.5>, d6[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd3d9f5
│ │  	vabdl.u16	<illegal reg q10.5>, d4, d17
│ │ -			@ <UNDEFINED> instruction: 0xffd3d982
│ │ +			@ <UNDEFINED> instruction: 0xffd3d9a9
│ │  	vmlsl.u16	<illegal reg q10.5>, d20, d1[3]
│ │ -	vmul.f16	<illegal reg q14.5>, <illegal reg q1.5>, d2[1]
│ │ +	vqrshrn.u32	d29, <illegal reg q8.5>, #13
│ │  	vqshlu.s16	<illegal reg q10.5>, <illegal reg q6.5>, #4
│ │ -			@ <UNDEFINED> instruction: 0xffd3d8be
│ │ +	vmul.i16	<illegal reg q14.5>, <illegal reg q9.5>, d5[2]
│ │  	vshll.u16	<illegal reg q10.5>, d17, #4
│ │  			@ <UNDEFINED> instruction: 0xffd34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	34ea18 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e2194>
│ │  	beq.n	34e598 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e1d14>
│ │  	b.n	34e99c <uniffi_pbcli_checksum_method_api_base@@Base+0x1e2118>
│ │  	str	r0, [r0, r0]
│ │ @@ -892671,19 +892671,19 @@
│ │  	b.n	34fed6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e3652>
│ │  	add	r0, pc, #0	@ (adr r0, 34f798 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e2f14>)
│ │  	b.n	34feda <uniffi_pbcli_checksum_method_api_base@@Base+0x1e3656>
│ │  	movs	r0, r3
│ │  	b.n	34f2b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e2a34>
│ │  			@ <UNDEFINED> instruction: 0xfff1eaff
│ │  	mov	r2, r1
│ │ -	vraddhn.i32	d18, <illegal reg q9.5>, <illegal reg q11.5>
│ │ +	vmls.i16	q9, <illegal reg q9.5>, d6[1]
│ │  	vqshlu.s16	d20, d18, #5
│ │ -	vmls.i16	q9, <illegal reg q9.5>, d7[1]
│ │ +	vsri.64	q9, q11, #45
│ │  	vrsra.u64	d20, d30, #43
│ │ -	vrshr.u16	q9, <illegal reg q5.5>, #13
│ │ +	vsubl.u16	q9, d19, d2
│ │  	vabal.u16	q10, d5, d18
│ │  			@ <UNDEFINED> instruction: 0xffd3436a
│ │  			@ <UNDEFINED> instruction: 0xffd34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	34fce4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e3460>
│ │  	beq.n	34f874 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e2ff0>
│ │  	b.n	34fc68 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e33e4>
│ │ @@ -893654,19 +893654,19 @@
│ │  	str	r4, [r4, #0]
│ │  	b.n	34fb24 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e32a0>
│ │  	vpmin.u8	q7, <illegal reg q8.5>, <illegal reg q15.5>
│ │  	str	r4, [r6, r0]
│ │  	b.n	34fb2c <uniffi_pbcli_checksum_method_api_base@@Base+0x1e32a8>
│ │  	mrc2	10, 7, lr, cr13, cr15, {7}	@ <UNPREDICTABLE>
│ │  	lsrs	r6, r3
│ │ -			@ <UNDEFINED> instruction: 0xffd36b11
│ │ +			@ <UNDEFINED> instruction: 0xffd36b38
│ │  	vaddl.u16	q10, d20, d30
│ │  	vshr.u16	q10, q13, #13
│ │  			@ <UNDEFINED> instruction: 0xffd33b32
│ │ -	vmls.f16	q11, <illegal reg q1.5>, d5[2]
│ │ +	vabal.u16	q11, d19, d12
│ │  			@ <UNDEFINED> instruction: 0xffd43ede
│ │  			@ <UNDEFINED> instruction: 0xffd34c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	350534 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e3cb0>
│ │  	movs	r1, r0
│ │  	b.n	3502c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e3a40>
│ │  	movs	r2, r1
│ │ @@ -893720,18 +893720,18 @@
│ │  	b.n	3503ce <uniffi_pbcli_checksum_method_api_base@@Base+0x1e3b4a>
│ │  	movs	r0, #3
│ │  	b.n	3503d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e3b4e>
│ │  	asrs	r0, r6, #12
│ │  			@ <UNDEFINED> instruction: 0xfa050001
│ │  	b.n	3507da <uniffi_pbcli_checksum_method_api_base@@Base+0x1e3f56>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r8, sl, fp, ip, sp, pc}
│ │ -	vmlsl.u16	q10, d4, d6[3]
│ │ -	vqdmulh.s16	<illegal reg q13.5>, <illegal reg q10.5>, d3[3]
│ │ -	vqshlu.s16	d20, d30, #4
│ │ +	ldmia.w	sp!, {r1, r6, r8, sl, fp, ip, sp, pc}
│ │ +	vqshlu.s64	d20, d5, #20
│ │ +			@ <UNDEFINED> instruction: 0xffd5bd12
│ │ +	vmlsl.u16	q10, d4, d5[2]
│ │  			@ <UNDEFINED> instruction: 0xffd548f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3505d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e3d4c>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3503fa <uniffi_pbcli_checksum_method_api_base@@Base+0x1e3b76>
│ │  	movs	r3, r1
│ │  	b.n	350540 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e3cbc>
│ │ @@ -893997,25 +893997,25 @@
│ │  	asrs	r3, r2, #10
│ │  			@ <UNDEFINED> instruction: 0xfa056005
│ │  	b.n	35064e <uniffi_pbcli_checksum_method_api_base@@Base+0x1e3dca>
│ │  	movs	r6, r0
│ │  	b.n	350652 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e3dce>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r1, r3, r5, r6, r7, r8, ip, sp, lr, pc}
│ │ -	vmlal.u16	<illegal reg q8.5>, d3, d19
│ │ +	vmul.i16	<illegal reg q8.5>, <illegal reg q1.5>, d2[1]
│ │  	vaddw.u16	<illegal reg q15.5>, <illegal reg q10.5>, d22
│ │ -	vqshl.u64	<illegal reg q8.5>, <illegal reg q7.5>, #19
│ │ +	vmlal.u16	<illegal reg q8.5>, d3, d6
│ │  	vshr.u64	d31, d6, #43
│ │ -	vmlsl.u16	<illegal reg q8.5>, d19, d7[1]
│ │ +	vqshlu.s64	<illegal reg q8.5>, q11, #19
│ │  	vshr.u64	d31, d30, #43
│ │ -	vqshlu.s64	<illegal reg q8.5>, <illegal reg q11.5>, #19
│ │ +	vqshl.u16	d17, d14, #3
│ │  	vsra.u16	d31, d18, #11
│ │ -			@ <UNDEFINED> instruction: 0xffd3176b
│ │ +	vqshl.u64	d17, d2, #19
│ │  	vmla.i16	<illegal reg q15.5>, <illegal reg q10.5>, d6[2]
│ │ -	vqshl.u16	d17, d15, #3
│ │ +			@ <UNDEFINED> instruction: 0xffd31746
│ │  			@ <UNDEFINED> instruction: 0xffd54ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	350868 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e3fe4>
│ │  	beq.n	350358 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e3ad4>
│ │  	b.n	3507ec <uniffi_pbcli_checksum_method_api_base@@Base+0x1e3f68>
│ │  	str	r0, [sp, #32]
│ │  	b.n	34fe8c <uniffi_pbcli_checksum_method_api_base@@Base+0x1e3608>
│ │ @@ -894989,22 +894989,22 @@
│ │  	b.n	35118e <uniffi_pbcli_checksum_method_api_base@@Base+0x1e490a>
│ │  	movs	r4, r1
│ │  	b.n	351212 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e498e>
│ │  	asrs	r3, r0, #32
│ │  	b.n	351016 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e4792>
│ │  	vpmin.u32	q7, q13, <illegal reg q15.5>
│ │  			@ <UNDEFINED> instruction: 0xeb4affd3
│ │ -	ldrb	r3, [r2, r4]
│ │ +	ldrb	r2, [r7, r4]
│ │  			@ <UNDEFINED> instruction: 0xffd4eafe
│ │  	vqshl.u64	q15, q15, #19
│ │ -	vmul.f16	<illegal reg q10.5>, <illegal reg q9.5>, d7[0]
│ │ +	vmul.f16	<illegal reg q10.5>, <illegal reg q9.5>, d6[3]
│ │  			@ <UNDEFINED> instruction: 0xffd41abe
│ │  			@ <UNDEFINED> instruction: 0xffd3abac
│ │  	vmul.i16	q15, q1, d2[1]
│ │ -	vshll.u16	<illegal reg q10.5>, d3, #3
│ │ +	vshll.u16	<illegal reg q10.5>, d26, #3
│ │  	vqshrun.s32	d30, q5, #12
│ │  			@ <UNDEFINED> instruction: 0xffd34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3510e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e4860>
│ │  	beq.n	350c44 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e43c0>
│ │  	b.n	351068 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e47e4>
│ │  	str	r0, [r0, r0]
│ │ @@ -895399,34 +895399,34 @@
│ │  	b.n	3516f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e4e72>
│ │  	strb	r0, [r1, #0]
│ │  	b.n	350a74 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e41f0>
│ │  	strh	r0, [r2, #0]
│ │  	b.n	350a78 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e41f4>
│ │  			@ <UNDEFINED> instruction: 0xffabeaff
│ │  	b.n	350d48 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e44c4>
│ │ -	vmul.i16	<illegal reg q10.5>, <illegal reg q9.5>, d7[3]
│ │ +	vqshrn.u32	d21, q3, #13
│ │  	vsli.64	q15, q3, #20
│ │ -			@ <UNDEFINED> instruction: 0xffd357c3
│ │ +			@ <UNDEFINED> instruction: 0xffd357ea
│ │  			@ <UNDEFINED> instruction: 0xffd49af1
│ │  	vabal.u16	q15, d18, d30
│ │ -	vqshl.u64	d21, d11, #19
│ │ +			@ <UNDEFINED> instruction: 0xffd357c2
│ │  	vsli.16	q15, q7, #4
│ │ -			@ <UNDEFINED> instruction: 0xffd3574b
│ │ +	vqshl.u16	<illegal reg q10.5>, q9, #3
│ │  	vsli.16	d30, d6, #4
│ │ -	vabdl.u16	<illegal reg q10.5>, d3, d3
│ │ +	vabdl.u16	<illegal reg q10.5>, d3, d26
│ │  	vsri.64	q15, q13, #44
│ │ -	vmlsl.u16	<illegal reg q10.5>, d19, d7[2]
│ │ +	vabdl.u16	<illegal reg q10.5>, d3, d14
│ │  	vsri.64	q15, q7, #44
│ │ -	vmlsl.u16	<illegal reg q10.5>, d19, d3[1]
│ │ +	vqshlu.s64	<illegal reg q10.5>, q9, #19
│ │  	vmls.i16	q15, q10, d2[0]
│ │ -	vrsubhn.i32	d21, <illegal reg q9.5>, <illegal reg q15.5>
│ │ +	vqshlu.s64	<illegal reg q10.5>, q3, #19
│ │  	vmls.i16	q15, q2, d2[3]
│ │ -	vqshlu.s16	<illegal reg q10.5>, <illegal reg q3.5>, #3
│ │ +	vqshlu.s16	<illegal reg q10.5>, q15, #3
│ │  	vraddhn.i32	d30, q10, q3
│ │ -	vqshlu.s16	<illegal reg q10.5>, <illegal reg q9.5>, #3
│ │ +	vqshlu.s64	d21, d10, #19
│ │  			@ <UNDEFINED> instruction: 0xffd44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3514b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e4c34>
│ │  	beq.n	351008 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e4784>
│ │  	b.n	35143c <uniffi_pbcli_checksum_method_api_base@@Base+0x1e4bb8>
│ │  	movs	r0, r6
│ │  	b.n	35164a <uniffi_pbcli_checksum_method_api_base@@Base+0x1e4dc6>
│ │ @@ -895698,17 +895698,17 @@
│ │  	orr.w	sl, r4, #36608	@ 0x8f00
│ │  	orr.w	r0, r7, #11534336	@ 0xb00000
│ │  	b.n	351956 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e50d2>
│ │  	beq.n	351250 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e49cc>
│ │  	b.n	3516b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e4e2c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r1, r3, r4, r5, r7, r8, r9, sp, lr, pc}
│ │ -	vqshlu.s64	<illegal reg q9.5>, <illegal reg q9.5>, #19
│ │ +	vqshl.u16	d19, d10, #3
│ │  	vsra.u64	q15, q11, #43
│ │ -	vabal.u16	<illegal reg q9.5>, d3, d31
│ │ +	vsli.16	<illegal reg q9.5>, q3, #3
│ │  	vaddl.u16	q8, d5, d4
│ │  	b.n	350d70 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e44ec>
│ │  	movs	r0, r0
│ │  	b.n	351354 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e4ad0>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldrb	r4, [r0, #10]
│ │  	movs	r6, r2
│ │ @@ -895779,15 +895779,15 @@
│ │  	b.n	350dce <uniffi_pbcli_checksum_method_api_base@@Base+0x1e454a>
│ │  	b.n	351338 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e4ab4>
│ │  	b.n	350dd2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e454e>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	351a12 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e518e>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r8, sl, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r5, r8, sl, fp, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffd44df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3517fc <uniffi_pbcli_checksum_method_api_base@@Base+0x1e4f78>
│ │  	strb	r1, [r0, #0]
│ │  	b.n	351626 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e4da2>
│ │  	asrs	r0, r1, #4
│ │  	b.n	350e28 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e45a4>
│ │ @@ -895914,16 +895914,16 @@
│ │  	movs	r0, r6
│ │  	b.n	350ef4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e4670>
│ │  	strh	r1, [r0, #0]
│ │  	b.n	351b2e <uniffi_pbcli_checksum_method_api_base@@Base+0x1e52aa>
│ │  	movs	r0, r1
│ │  	b.n	351732 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e4eae>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r5, r6, sl, fp, ip, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffd47bb7
│ │ +	ldmia.w	sp!, {r1, r5, r7, sl, fp, ip, sp, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffd47bde
│ │  	vqshrun.s32	d20, q8, #12
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	351920 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e509c>
│ │  	eors	r0, r2
│ │  	b.n	350f2a <uniffi_pbcli_checksum_method_api_base@@Base+0x1e46a6>
│ │  	movs	r0, r0
│ │  	b.n	351ab6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5232>
│ │ @@ -895955,15 +895955,15 @@
│ │  	asrs	r5, r0, #32
│ │  	b.n	35178a <uniffi_pbcli_checksum_method_api_base@@Base+0x1e4f06>
│ │  	movs	r0, #131	@ 0x83
│ │  	b.n	351b8e <uniffi_pbcli_checksum_method_api_base@@Base+0x1e530a>
│ │  	ldr	r0, [pc, #192]	@ (351510 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e4c8c>)
│ │  	ldmia.w	sp!, {r0, r2, r3, r4, r7, r9, sl, fp, sp}
│ │  			@ <UNDEFINED> instruction: 0xeaff8830
│ │ -	ldmia.w	sp!, {r0, r1, r2, r6, r8, r9, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r5, r6, r8, r9, fp, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffd44bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	351980 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e50fc>
│ │  	beq.n	351478 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e4bf4>
│ │  	b.n	351904 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5080>
│ │  	str	r0, [r2, #4]
│ │  	b.n	350f8e <uniffi_pbcli_checksum_method_api_base@@Base+0x1e470a>
│ │ @@ -896408,23 +896408,23 @@
│ │  	b.n	351f96 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5712>
│ │  	asrs	r0, r1, #32
│ │  	b.n	351eda <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5656>
│ │  	movs	r0, #0
│ │  	b.n	351f9e <uniffi_pbcli_checksum_method_api_base@@Base+0x1e571a>
│ │  	asrs	r5, r0, #24
│ │  			@ <UNDEFINED> instruction: 0xebfeff99
│ │ -			@ <UNDEFINED> instruction: 0xeaff78db
│ │ -			@ <UNDEFINED> instruction: 0xffd4eab2
│ │ -			@ <UNDEFINED> instruction: 0xffd478bf
│ │ -			@ <UNDEFINED> instruction: 0xffd4ea96
│ │ -	vmul.i16	<illegal reg q11.5>, q2, d7[1]
│ │ -	vmlsl.u16	q15, d4, d22
│ │ -	vabdl.u16	<illegal reg q11.5>, d4, d27
│ │ -			@ <UNDEFINED> instruction: 0xffd4e902
│ │ -	vqshl.u64	<illegal reg q11.5>, <illegal reg q7.5>, #20
│ │ +			@ <UNDEFINED> instruction: 0xeaff7902
│ │ +			@ <UNDEFINED> instruction: 0xffd4ead9
│ │ +	vmul.i16	<illegal reg q11.5>, q10, d6[2]
│ │ +			@ <UNDEFINED> instruction: 0xffd4eabd
│ │ +	vqrshrun.s32	d23, q11, #12
│ │ +	vmull.u16	q15, d4, d5[1]
│ │ +	vqshl.u16	<illegal reg q11.5>, q1, #4
│ │ +			@ <UNDEFINED> instruction: 0xffd4e929
│ │ +	vmlal.u16	<illegal reg q11.5>, d4, d6
│ │  			@ <UNDEFINED> instruction: 0xffd44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	351dac <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5528>
│ │  	beq.n	3518ac <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5028>
│ │  	b.n	351d30 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e54ac>
│ │  	str	r0, [r0, r0]
│ │  	b.n	351bda <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5356>
│ │ @@ -896676,20 +896676,20 @@
│ │  	and.w	r0, r0, r0, lsl #16
│ │  	b.n	3521fa <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5976>
│ │  	movs	r4, r0
│ │  	b.n	351dfe <uniffi_pbcli_checksum_method_api_base@@Base+0x1e557a>
│ │  	beq.n	351af8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5274>
│ │  	b.n	351f58 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e56d4>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r7, r8, sl, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r3, r5, r7, r8, sl, ip, sp, lr}
│ │  	vqrshrn.u32	d16, q13, #12
│ │ -	vmls.f16	<illegal reg q11.5>, <illegal reg q1.5>, d7[2]
│ │ +	vabal.u16	<illegal reg q11.5>, d19, d14
│ │  	vqrshrn.u32	d16, q7, #12
│ │ -	vabal.u16	<illegal reg q11.5>, d3, d19
│ │ -	vqshlu.s16	<illegal reg q11.5>, <illegal reg q3.5>, #4
│ │ +	vmls.f16	<illegal reg q11.5>, <illegal reg q1.5>, d2[1]
│ │ +	vqshlu.s16	<illegal reg q11.5>, q15, #4
│ │  			@ <UNDEFINED> instruction: 0xffd44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	352000 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e577c>
│ │  	beq.n	351b20 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e529c>
│ │  	b.n	351f84 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5700>
│ │  	str	r0, [r0, r0]
│ │  	b.n	351e2e <uniffi_pbcli_checksum_method_api_base@@Base+0x1e55aa>
│ │ @@ -896897,18 +896897,18 @@
│ │  	b.n	3523ee <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5b6a>
│ │  	asrs	r7, r1, #2
│ │  	b.n	3523f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5b6e>
│ │  	movs	r0, #0
│ │  	b.n	3523f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5b72>
│ │  	asrs	r7, r5, #19
│ │  			@ <UNDEFINED> instruction: 0xebfeffe2
│ │ -			@ <UNDEFINED> instruction: 0xeaff7417
│ │ -	vrshr.u64	<illegal reg q11.5>, <illegal reg q15.5>, #44
│ │ +			@ <UNDEFINED> instruction: 0xeaff743e
│ │ +	vsubw.u16	<illegal reg q11.5>, q2, d22
│ │  			@ <UNDEFINED> instruction: 0xffd4bff7
│ │ -	vrshr.u64	<illegal reg q11.5>, <illegal reg q1.5>, #46
│ │ +	vrshr.u64	<illegal reg q11.5>, q13, #46
│ │  	vqrdmlsh.s16	<illegal reg q13.5>, q10, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffd24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3521f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5970>
│ │  	beq.n	351d04 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5480>
│ │  	b.n	352178 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e58f4>
│ │  	ands	r0, r0
│ │ @@ -897014,15 +897014,15 @@
│ │  	b.n	352250 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e59cc>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {}
│ │  	b.n	352582 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5cfe>
│ │  	beq.n	351dfc <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5578>
│ │  	b.n	35225c <uniffi_pbcli_checksum_method_api_base@@Base+0x1e59d8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r4, r5, r9, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r3, r4, r6, r9, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffd44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3522f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5a6c>
│ │  	beq.n	351e00 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e557c>
│ │  	b.n	352274 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e59f0>
│ │  	str	r0, [r0, r0]
│ │  	b.n	35211e <uniffi_pbcli_checksum_method_api_base@@Base+0x1e589a>
│ │ @@ -897157,15 +897157,15 @@
│ │  	b.n	352232 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e59ae>
│ │  	beq.n	351f2c <uniffi_pbcli_checksum_method_api_base@@Base+0x1e56a8>
│ │  	b.n	35238c <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5b08>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {ip}
│ │  	b.n	3526be <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5e3a>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │ -	strb	r3, [r7, #4]
│ │ +	strb	r2, [r4, #5]
│ │  			@ <UNDEFINED> instruction: 0xffd44df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	352428 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5ba4>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	352252 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e59ce>
│ │  	movs	r1, r0
│ │  	b.n	352518 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5c94>
│ │ @@ -897881,49 +897881,49 @@
│ │  	b.n	3527e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5f64>
│ │  			@ <UNDEFINED> instruction: 0xff81caff
│ │  	movs	r0, r1
│ │  	b.n	35288e <uniffi_pbcli_checksum_method_api_base@@Base+0x1e600a>
│ │  	str	r0, [r4, #0]
│ │  	b.n	35205a <uniffi_pbcli_checksum_method_api_base@@Base+0x1e57d6>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r6, r7, r9, fp, sp, lr}
│ │ -	vrshr.u16	d18, d31, #12
│ │ -			@ <UNDEFINED> instruction: 0xffd56d0b
│ │ -	vsri.16	q9, <illegal reg q13.5>, #12
│ │ -	vshll.u16	q11, d27, #5
│ │ -	vaddw.u16	q9, q10, d27
│ │ -	vmull.u16	q11, d5, d3[2]
│ │ -	vsra.u64	q9, <illegal reg q1.5>, #44
│ │ -	vmull.u16	q11, d5, d11
│ │ -	vrsra.u16	q9, <illegal reg q13.5>, #12
│ │ -			@ <UNDEFINED> instruction: 0xffd56e3b
│ │ -	vabal.u16	q9, d20, d27
│ │ -	vqrdmulh.s16	q11, <illegal reg q10.5>, d3[3]
│ │ -	vsli.16	q9, <illegal reg q5.5>, #4
│ │ -	vqrdmulh.s16	q11, <illegal reg q2.5>, d7[0]
│ │ -	vsri.64	d18, d23, #44
│ │ -	vqdmulh.s16	q11, <illegal reg q10.5>, d3[2]
│ │ -	vsri.16	q9, <illegal reg q1.5>, #12
│ │ -			@ <UNDEFINED> instruction: 0xffd56ebb
│ │ -	vrsubhn.i32	d18, q2, <illegal reg q13.5>
│ │ -			@ <UNDEFINED> instruction: 0xffd56cbb
│ │ -	vraddhn.i32	d18, q2, <illegal reg q13.5>
│ │ -			@ <UNDEFINED> instruction: 0xffd56b47
│ │ -	vrshr.u64	d18, d23, #44
│ │ -			@ <UNDEFINED> instruction: 0xffd56bd3
│ │ -			@ <UNDEFINED> instruction: 0xffd42343
│ │ -			@ <UNDEFINED> instruction: 0xffd56db3
│ │ -			@ <UNDEFINED> instruction: 0xffd46bb7
│ │ -	vsubw.u16	q9, q2, d23
│ │ -			@ <UNDEFINED> instruction: 0xffd56b1b
│ │ -	vsubl.u16	q9, d20, d11
│ │ -			@ <UNDEFINED> instruction: 0xffd56b8f
│ │ -	vrshr.u64	q9, <illegal reg q15.5>, #44
│ │ -	vqrdmlsh.s16	q11, <illegal reg q2.5>, d3[3]
│ │ -	vqshlu.s64	q9, <illegal reg q5.5>, #20
│ │ +	ldmia.w	sp!, {r1, r2, r4, r5, r6, r7, r9, fp, sp, lr}
│ │ +	vmlal.u16	q9, d4, d6[2]
│ │ +			@ <UNDEFINED> instruction: 0xffd56d32
│ │ +	vraddhn.i32	d18, q10, q9
│ │ +	vmull.u16	q11, d5, d2[2]
│ │ +	vsra.u64	q9, q1, #44
│ │ +	vmlsl.u16	q11, d21, d10
│ │ +	vsra.u64	q9, q13, #44
│ │ +			@ <UNDEFINED> instruction: 0xffd56c32
│ │ +	vsubw.u16	q9, q10, d18
│ │ +	vqrdmlah.s16	q11, <illegal reg q2.5>, d2[2]
│ │ +	vsli.64	q9, q1, #20
│ │ +			@ <UNDEFINED> instruction: 0xffd56e12
│ │ +	vabal.u16	q9, d20, d2
│ │ +	vqrdmulh.s16	q11, <illegal reg q2.5>, d6[3]
│ │ +	vsri.64	q9, q7, #44
│ │ +			@ <UNDEFINED> instruction: 0xffd56d0a
│ │ +	vsri.16	q9, q13, #12
│ │ +	vqrdmlah.s16	q11, <illegal reg q10.5>, d2[2]
│ │ +	vqshlu.s16	q9, q1, #4
│ │ +	vqdmulh.s16	q11, <illegal reg q10.5>, d2[2]
│ │ +	vsri.16	q9, q1, #12
│ │ +			@ <UNDEFINED> instruction: 0xffd56b6e
│ │ +	vrshr.u64	q9, q7, #44
│ │ +			@ <UNDEFINED> instruction: 0xffd56bfa
│ │ +			@ <UNDEFINED> instruction: 0xffd4236a
│ │ +			@ <UNDEFINED> instruction: 0xffd56dda
│ │ +			@ <UNDEFINED> instruction: 0xffd46bde
│ │ +			@ <UNDEFINED> instruction: 0xffd4234e
│ │ +			@ <UNDEFINED> instruction: 0xffd56b42
│ │ +	vrshr.u64	d18, d18, #44
│ │ +			@ <UNDEFINED> instruction: 0xffd56bb6
│ │ +	vsubw.u16	q9, q2, d22
│ │ +			@ <UNDEFINED> instruction: 0xffd56f92
│ │ +	vabdl.u16	q9, d4, d2
│ │  			@ <UNDEFINED> instruction: 0xffd54c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	352b04 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e6280>
│ │  	beq.n	3525fc <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5d78>
│ │  	b.n	352a88 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e6204>
│ │  	movs	r0, r0
│ │  	b.n	352c96 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e6412>
│ │ @@ -898374,38 +898374,38 @@
│ │  	beq.n	352a04 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e6180>
│ │  	b.n	352e7c <uniffi_pbcli_checksum_method_api_base@@Base+0x1e65f8>
│ │  	ldr	r4, [pc, #448]	@ (352ba8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e6324>)
│ │  	ldmia.w	sp!, {r0, r5, r7, fp, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeaff6000
│ │  	b.n	353132 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e68ae>
│ │  	vpmin.u32	q15, q12, <illegal reg q15.5>
│ │ -	str	r3, [r6, #124]	@ 0x7c
│ │ +	ldr	r2, [r3, #0]
│ │  	vmull.u16	q9, d4, d0[3]
│ │ -	vqrdmlah.s16	q12, <illegal reg q9.5>, d1[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd44cf6
│ │ +			@ <UNDEFINED> instruction: 0xffd38f08
│ │ +			@ <UNDEFINED> instruction: 0xffd44d1d
│ │  	vshr.u64	d31, d27, #44
│ │  	vrshr.u16	q12, q14, #14
│ │ -			@ <UNDEFINED> instruction: 0xffd38cfe
│ │ -	vabdl.u16	<illegal reg q8.5>, d4, d25
│ │ -	vqshl.u16	d17, d6, #5
│ │ -	vqshrun.s32	d23, q2, #11
│ │ +			@ <UNDEFINED> instruction: 0xffd38d25
│ │ +	vqshl.u16	<illegal reg q8.5>, q0, #4
│ │ +	vqshl.u16	d17, d29, #5
│ │ +	vqshrun.s32	d23, <illegal reg q13.5>, #11
│ │  			@ <UNDEFINED> instruction: 0xffd459a4
│ │  	vrsubhn.i32	d23, q9, q14
│ │  	vsri.64	d16, d26, #46
│ │  	vrshr.u64	d22, d11, #45
│ │  	vsra.u64	d18, d14, #46
│ │  	vrsra.u64	q12, q3, #44
│ │  			@ <UNDEFINED> instruction: 0xffd33cd8
│ │  	vmull.u16	<illegal reg q11.5>, d19, d3[1]
│ │ -	vmlal.u16	<illegal reg q14.5>, d2, d5[2]
│ │ -	vshr.u64	d16, d4, #44
│ │ +	vsubl.u16	<illegal reg q14.5>, d18, d12
│ │ +	vshr.u64	d16, d27, #44
│ │  	vmull.p<illegal width 16>	q13, d5, d23
│ │  	vrsra.u16	d25, d21, #13
│ │ -	vmlal.u16	q11, d2, d15
│ │ -	vabdl.u16	q11, d4, d19
│ │ +	vqshrun.s32	d22, q11, #14
│ │ +			@ <UNDEFINED> instruction: 0xffd4674a
│ │  			@ <UNDEFINED> instruction: 0xffd42998
│ │  			@ <UNDEFINED> instruction: 0xffd34c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	352f7c <uniffi_pbcli_checksum_method_api_base@@Base+0x1e66f8>
│ │  	movs	r0, #40	@ 0x28
│ │  	b.n	352586 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5d02>
│ │  	ands	r0, r0
│ │ @@ -898430,15 +898430,15 @@
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	353136 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e68b2>
│ │  	movs	r0, r5
│ │  	b.n	3525a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e5d1e>
│ │  	movs	r1, r0
│ │  	asrs	r0, r0, #12
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r5, r6, r7, sl, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r3, r8, sl, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffd44c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	352fc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e6744>
│ │  	ands	r1, r0
│ │  	b.n	3531f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e696e>
│ │  	movs	r0, r0
│ │  	b.n	353156 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e68d2>
│ │ @@ -898542,15 +898542,15 @@
│ │  	b.n	3532d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e6a52>
│ │  	movs	r0, #72	@ 0x48
│ │  	b.n	35321a <uniffi_pbcli_checksum_method_api_base@@Base+0x1e6996>
│ │  	lsls	r3, r2, #4
│ │  	b.n	352dc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e653e>
│ │  			@ <UNDEFINED> instruction: 0xffce1aff
│ │  			@ <UNDEFINED> instruction: 0xffe3eaff
│ │ -	str	r7, [r0, #64]	@ 0x40
│ │ +	str	r6, [r5, #64]	@ 0x40
│ │  	vqrdmlah.s16	q8, q10, d0[3]
│ │  			@ <UNDEFINED> instruction: 0xffd44c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3530d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e684c>
│ │  	beq.n	352bd8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e6354>
│ │  	b.n	353054 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e67d0>
│ │  	asrs	r0, r0, #1
│ │ @@ -898672,17 +898672,17 @@
│ │  	ands	r1, r0
│ │  	b.n	3533fe <uniffi_pbcli_checksum_method_api_base@@Base+0x1e6b7a>
│ │  	movs	r4, r0
│ │  	b.n	353002 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e677e>
│ │  	beq.n	352ce4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e6460>
│ │  	b.n	35315c <uniffi_pbcli_checksum_method_api_base@@Base+0x1e68d8>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r5, r6, r7, r9, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r4, r8, r9, sp, lr}
│ │  	vsli.16	<illegal reg q12.5>, <illegal reg q6.5>, #4
│ │ -	vrsra.u16	d22, d11, #14
│ │ +			@ <UNDEFINED> instruction: 0xffd26342
│ │  	vabal.u16	<illegal reg q12.5>, d20, d9
│ │  	vmlal.u16	q10, d2, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	353022 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e679e>
│ │  	beq.n	352cf4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e6470>
│ │  	b.n	353180 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e68fc>
│ │  	stmia	r0!, {r3}
│ │ @@ -900032,18 +900032,18 @@
│ │  	b.n	3539d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e714c>
│ │  	movs	r6, #33	@ 0x21
│ │  			@ <UNDEFINED> instruction: 0xebff0004
│ │  	b.n	353bfa <uniffi_pbcli_checksum_method_api_base@@Base+0x1e7376>
│ │  	beq.n	3538ec <uniffi_pbcli_checksum_method_api_base@@Base+0x1e7068>
│ │  	b.n	353d54 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e74d0>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r1, r3, r5, r6, r7, r9, ip, sp, pc}
│ │ -	vabdl.u16	<illegal reg q15.5>, d20, d14
│ │ -	vrshr.u64	d27, d26, #44
│ │ -	vrshr.u16	<illegal reg q13.5>, q3, #12
│ │ +	ldmia.w	sp!, {r0, r4, r8, r9, ip, sp, pc}
│ │ +	vqshl.u64	d31, d21, #20
│ │ +	vmlal.u16	<illegal reg q13.5>, d20, d1[2]
│ │ +	vrshr.u16	<illegal reg q13.5>, <illegal reg q14.5>, #12
│ │  			@ <UNDEFINED> instruction: 0xffd44c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	353df4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e7570>
│ │  	movs	r0, r0
│ │  	b.n	353f7e <uniffi_pbcli_checksum_method_api_base@@Base+0x1e76fa>
│ │  	movs	r4, r6
│ │  	lsrs	r0, r0, #8
│ │ @@ -900144,21 +900144,21 @@
│ │  	b.n	353acc <uniffi_pbcli_checksum_method_api_base@@Base+0x1e7248>
│ │  	lsls	r1, r0, #6
│ │  	b.n	3538d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e704e>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3540fa <uniffi_pbcli_checksum_method_api_base@@Base+0x1e7876>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r5, fp, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r4, r6, fp, sp, lr, pc}
│ │  	vsri.16	d21, d4, #12
│ │  	movs	r6, r2
│ │  	adds	r6, r2, r4
│ │  	vabal.u16	<illegal reg q12.5>, d3, d1
│ │  	vsra.u16	<illegal reg q9.5>, q12, #13
│ │ -	vmull.u16	q9, d3, d16
│ │ +	vqdmulh.s16	q9, <illegal reg q1.5>, d7[0]
│ │  	vmla.i16	q11, q10, d2[2]
│ │  	vsra.u16	q8, q10, #13
│ │  	vaddl.u16	<illegal reg q8.5>, d3, d0
│ │  	b.n	353d22 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e749e>
│ │  	movs	r4, #69	@ 0x45
│ │  	b.n	353fe6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e7762>
│ │  	movs	r0, r0
│ │ @@ -900239,15 +900239,15 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	353bb0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e732c>
│ │  	asrs	r0, r0, #32
│ │  	asrs	r0, r4, #14
│ │  	movs	r1, r0
│ │  	b.n	353dda <uniffi_pbcli_checksum_method_api_base@@Base+0x1e7556>
│ │  	vrhadd.u16	d14, d14, d31
│ │ -	str	r6, [sp, #516]	@ 0x204
│ │ +	str	r6, [sp, #672]	@ 0x2a0
│ │  			@ <UNDEFINED> instruction: 0xffd44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	353fc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e7740>
│ │  	beq.n	353ad4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e7250>
│ │  	b.n	353f48 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e76c4>
│ │  	strh	r4, [r1, #0]
│ │  	b.n	3535e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e6d64>
│ │ @@ -900831,29 +900831,29 @@
│ │  	beq.n	353fd4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e7750>
│ │  	b.n	354434 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e7bb0>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r5, r6, r7, r9, sl, fp, ip, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd99d5c
│ │  	vqrdmulh.s16	<illegal reg q12.5>, <illegal reg q4.5>, d2[0]
│ │  	vqshl.u16	<illegal reg q13.5>, <illegal reg q8.5>, #9
│ │ -	vrsra.u16	d28, d16, #14
│ │ +	vrsra.u16	q14, <illegal reg q3.5>, #14
│ │  	vqdmulh.s16	<illegal reg q12.5>, q10, d1[0]
│ │  	vqrdmulh.s16	<illegal reg q12.5>, <illegal reg q4.5>, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffd99cb2
│ │  			@ <UNDEFINED> instruction: 0xffd99df9
│ │  			@ <UNDEFINED> instruction: 0xffd99cf8
│ │  			@ <UNDEFINED> instruction: 0xffd99cfb
│ │  			@ <UNDEFINED> instruction: 0xffd99e72
│ │  			@ <UNDEFINED> instruction: 0xffd99da5
│ │  			@ <UNDEFINED> instruction: 0xffd99da4
│ │  			@ <UNDEFINED> instruction: 0xffd99da3
│ │  			@ <UNDEFINED> instruction: 0xffd99da2
│ │  			@ <UNDEFINED> instruction: 0xffd99da1
│ │  	vqshlu.s16	d27, d13, #9
│ │ -	vsra.u64	q14, q6, #46
│ │ +	vsubl.u16	q14, d2, d3
│ │  			@ <UNDEFINED> instruction: 0xffd49c72
│ │  	vqshlu.s16	<illegal reg q13.5>, <illegal reg q14.5>, #9
│ │  			@ <UNDEFINED> instruction: 0xffd24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	354518 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e7c94>
│ │  	beq.n	354028 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e77a4>
│ │  	b.n	35449c <uniffi_pbcli_checksum_method_api_base@@Base+0x1e7c18>
│ │ @@ -901835,23 +901835,23 @@
│ │  	movs	r0, #0
│ │  	b.n	354ff6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e8772>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	354ffa <uniffi_pbcli_checksum_method_api_base@@Base+0x1e8776>
│ │  	lsrs	r6, r5, #7
│ │  			@ <UNDEFINED> instruction: 0xebfeffa9
│ │  			@ <UNDEFINED> instruction: 0xeaffc4a7
│ │ -	vqshlu.s16	<illegal reg q11.5>, <illegal reg q10.5>, #2
│ │ +	vqshlu.s64	d23, d12, #18
│ │  	vrsra.u64	q14, <illegal reg q3.5>, #44
│ │ -	vabal.u16	<illegal reg q11.5>, d18, d21
│ │ +	vmls.f16	<illegal reg q11.5>, q9, d4[1]
│ │  	vraddhn.i32	d28, q2, <illegal reg q1.5>
│ │ -	vsli.64	<illegal reg q11.5>, <illegal reg q0.5>, #18
│ │ +	vsli.64	<illegal reg q11.5>, q12, #18
│ │  	vrshr.u64	q14, <illegal reg q9.5>, #44
│ │ -	vmls.i16	<illegal reg q11.5>, q9, d1[0]
│ │ +	vmls.i16	<illegal reg q11.5>, q9, d0[3]
│ │  	vsubw.u16	q14, q2, d23
│ │ -	vsri.64	<illegal reg q11.5>, <illegal reg q10.5>, #46
│ │ +	vsli.16	d23, d12, #2
│ │  			@ <UNDEFINED> instruction: 0xffd44c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	354e0c <uniffi_pbcli_checksum_method_api_base@@Base+0x1e8588>
│ │  	str	r4, [r3, #0]
│ │  	b.n	354416 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e7b92>
│ │  	ands	r0, r0
│ │  	b.n	35503a <uniffi_pbcli_checksum_method_api_base@@Base+0x1e87b6>
│ │ @@ -902812,15 +902812,15 @@
│ │  			@ <UNDEFINED> instruction: 0xebfeffeb
│ │  			@ <UNDEFINED> instruction: 0xeaffffee
│ │  			@ <UNDEFINED> instruction: 0xeaff84a0
│ │  	movs	r0, r3
│ │  	strh	r4, [r0, #36]	@ 0x24
│ │  	movs	r0, r3
│ │  	strb	r0, [r6, #3]
│ │ -			@ <UNDEFINED> instruction: 0xffd2fe10
│ │ +			@ <UNDEFINED> instruction: 0xffd2fe37
│ │  			@ <UNDEFINED> instruction: 0xffd34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	35566c <uniffi_pbcli_checksum_method_api_base@@Base+0x1e8de8>
│ │  	beq.n	35518c <uniffi_pbcli_checksum_method_api_base@@Base+0x1e8908>
│ │  	b.n	3555f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e8d6c>
│ │  	lsrs	r2, r0, #12
│ │  	b.n	3557fe <uniffi_pbcli_checksum_method_api_base@@Base+0x1e8f7a>
│ │ @@ -903127,17 +903127,17 @@
│ │  	lsls	r0, r7, #1
│ │  	b.n	354f06 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e8682>
│ │  			@ <UNDEFINED> instruction: 0xff90eaff
│ │  	strh	r0, [r0, #0]
│ │  	b.n	355b46 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e92c2>
│ │  			@ <UNDEFINED> instruction: 0xff8eeaff
│ │  	strb	r1, [r6, #2]
│ │ -			@ <UNDEFINED> instruction: 0xffd299a8
│ │ +	vmul.f16	<illegal reg q12.5>, q9, d7[1]
│ │  			@ <UNDEFINED> instruction: 0xffd46f81
│ │ -	vqrshrun.s32	d25, q12, #14
│ │ +			@ <UNDEFINED> instruction: 0xffd2989f
│ │  			@ <UNDEFINED> instruction: 0xffd44ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	35593c <uniffi_pbcli_checksum_method_api_base@@Base+0x1e90b8>
│ │  	beq.n	35547c <uniffi_pbcli_checksum_method_api_base@@Base+0x1e8bf8>
│ │  	b.n	3558c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e903c>
│ │  	str	r0, [r0, r0]
│ │  	b.n	35576a <uniffi_pbcli_checksum_method_api_base@@Base+0x1e8ee6>
│ │ @@ -903724,15 +903724,15 @@
│ │  	beq.n	355970 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e90ec>
│ │  	b.n	355de8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e9564>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, ip, lr}
│ │  	b.n	35609a <uniffi_pbcli_checksum_method_api_base@@Base+0x1e9816>
│ │  			@ <UNDEFINED> instruction: 0xfff8eaff
│ │  	ldr	r5, [r0, #16]
│ │ -	vqdmulh.s16	q8, q1, d5[2]
│ │ +	vmull.u16	q8, d18, d12
│ │  			@ <UNDEFINED> instruction: 0xffd448f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	355e88 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e9604>
│ │  	str	r0, [r0, #0]
│ │  	b.n	355cb2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e942e>
│ │  	movs	r3, r0
│ │  	b.n	3559f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e9174>
│ │ @@ -903808,16 +903808,16 @@
│ │  	lsls	r4, r1, #3
│ │  	b.n	356152 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e98ce>
│ │  	movs	r4, r0
│ │  	b.n	3559a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e911e>
│ │  	movs	r1, r0
│ │  	b.n	35615a <uniffi_pbcli_checksum_method_api_base@@Base+0x1e98d6>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r2, r4, r5, r6, r7, r8, sl, ip, sp}
│ │ -	vrsubhn.i32	d19, q2, q4
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r9, sl, ip, sp}
│ │ +	vrsubhn.i32	d19, q2, <illegal reg q15.5>
│ │  			@ <UNDEFINED> instruction: 0xffd44c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	355f48 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e96c4>
│ │  	ands	r0, r1
│ │  	b.n	355568 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e8ce4>
│ │  	movs	r3, r0
│ │  	b.n	355cde <uniffi_pbcli_checksum_method_api_base@@Base+0x1e945a>
│ │ @@ -903956,21 +903956,21 @@
│ │  	b.n	355c7c <uniffi_pbcli_checksum_method_api_base@@Base+0x1e93f8>
│ │  	lsls	r0, r1, #20
│ │  			@ <UNDEFINED> instruction: 0xebfe0004
│ │  	b.n	3562a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e9a22>
│ │  	asrs	r2, r1, #2
│ │  	b.n	3562aa <uniffi_pbcli_checksum_method_api_base@@Base+0x1e9a26>
│ │  			@ <UNDEFINED> instruction: 0xffd0eaff
│ │ -	adds	r4, #230	@ 0xe6
│ │ +	adds	r5, #13
│ │  	vqrshrun.s32	d21, <illegal reg q12.5>, #12
│ │ -	vraddhn.i32	d19, <illegal reg q1.5>, q15
│ │ +	vsri.16	<illegal reg q9.5>, <illegal reg q2.5>, #13
│ │  			@ <UNDEFINED> instruction: 0xffd457c1
│ │ -	vmls.i16	<illegal reg q9.5>, <illegal reg q1.5>, d2[1]
│ │ +	vsri.16	<illegal reg q9.5>, <illegal reg q8.5>, #13
│ │  	vqshl.u64	<illegal reg q10.5>, <illegal reg q6.5>, #20
│ │ -	vraddhn.i32	d19, <illegal reg q9.5>, q7
│ │ +	vsri.64	d19, d21, #45
│ │  	vmlal.u16	<illegal reg q10.5>, d4, d17
│ │  	vmull.p<illegal width 16>	q8, d3, d26
│ │  	b.n	356232 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e99ae>
│ │  	movs	r7, r0
│ │  	ldmia	r2!, {}
│ │  	lsls	r0, r0, #1
│ │  	b.n	35623a <uniffi_pbcli_checksum_method_api_base@@Base+0x1e99b6>
│ │ @@ -926224,17 +926224,17 @@
│ │  	b.n	361f14 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f5690>
│ │  			@ <UNDEFINED> instruction: 0xec34ebfe
│ │  	movs	r7, r0
│ │  	b.n	36213e <uniffi_pbcli_checksum_method_api_base@@Base+0x1f58ba>
│ │  	beq.n	361e38 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f55b4>
│ │  	b.n	362298 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f5a14>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r3, r6, sl}
│ │ -			@ <UNDEFINED> instruction: 0xffd48898
│ │ -			@ <UNDEFINED> instruction: 0xffd387e8
│ │ +	ldmia.w	sp!, {r4, r5, r6, sl}
│ │ +			@ <UNDEFINED> instruction: 0xffd488bf
│ │ +	vmlal.u16	q12, d3, d15
│ │  			@ <UNDEFINED> instruction: 0xffd34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	362334 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f5ab0>
│ │  	beq.n	361e24 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f55a0>
│ │  	b.n	3622b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f5a34>
│ │  	str	r0, [r0, r0]
│ │  	b.n	362162 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f58de>
│ │ @@ -926749,18 +926749,18 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	3623a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f5b24>
│ │  			@ <UNDEFINED> instruction: 0xeb0febfe
│ │  	movs	r2, r1
│ │  	b.n	3625d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f5d4e>
│ │  	svc	21
│ │  			@ <UNDEFINED> instruction: 0xebfdff86
│ │ -			@ <UNDEFINED> instruction: 0xeaff84ec
│ │ -			@ <UNDEFINED> instruction: 0xffd3fffd
│ │ -			@ <UNDEFINED> instruction: 0xffd31af0
│ │ -	vrsra.u16	q12, q2, #12
│ │ +			@ <UNDEFINED> instruction: 0xeaff8513
│ │ +	vaddl.u16	q8, d3, d20
│ │ +			@ <UNDEFINED> instruction: 0xffd41b17
│ │ +	vrsra.u16	q12, <illegal reg q13.5>, #12
│ │  			@ <UNDEFINED> instruction: 0xffd34bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3627cc <uniffi_pbcli_checksum_method_api_base@@Base+0x1f5f48>
│ │  	beq.n	3622c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f5a40>
│ │  	b.n	362750 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f5ecc>
│ │  	ands	r0, r0
│ │  	b.n	3629fa <uniffi_pbcli_checksum_method_api_base@@Base+0x1f6176>
│ │ @@ -929408,20 +929408,20 @@
│ │  	b.n	364126 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f78a2>
│ │  	b.n	363458 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f6bd4>
│ │  			@ <UNDEFINED> instruction: 0xebfe0005
│ │  	b.n	363d2e <uniffi_pbcli_checksum_method_api_base@@Base+0x1f74aa>
│ │  	beq.n	363a28 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f71a4>
│ │  	b.n	363e88 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f7604>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r3, r5, r6, r8, ip}
│ │ -	vaddw.u16	<illegal reg q8.5>, q2, d17
│ │ +	ldmia.w	sp!, {r2, r4, r7, r8, ip}
│ │ +	vmla.f16	<illegal reg q8.5>, q2, d0[1]
│ │  	vmls.f16	<illegal reg q14.5>, q10, d4[0]
│ │  			@ <UNDEFINED> instruction: 0xffd189be
│ │  	vsri.16	d26, d15, #15
│ │ -			@ <UNDEFINED> instruction: 0xffd1bcb9
│ │ +	vqdmulh.s16	<illegal reg q13.5>, <illegal reg q8.5>, d0[2]
│ │  	vqdmulh.s16	<illegal reg q12.5>, <illegal reg q9.5>, d0[3]
│ │  	movs	r7, r2
│ │  	ldrh	r2, [r5, #10]
│ │  	vmul.f16	q12, <illegal reg q8.5>, d2[3]
│ │  			@ <UNDEFINED> instruction: 0xffd19898
│ │  	movs	r7, r2
│ │  	ldrh	r2, [r6, #4]
│ │ @@ -929796,15 +929796,15 @@
│ │  	vqrdmlsh.s16	<illegal reg q15.5>, <illegal reg q8.5>, d7[3]
│ │  	vqshlu.s64	q12, q15, #18
│ │  			@ <UNDEFINED> instruction: 0xffd1ff23
│ │  	vqshlu.s64	d24, d2, #18
│ │  			@ <UNDEFINED> instruction: 0xffd1feb7
│ │  	vqrdmulh.s16	q12, q1, d7[3]
│ │  	vshr.u16	<illegal reg q10.5>, <illegal reg q2.5>, #14
│ │ -	vqshlu.s16	<illegal reg q12.5>, q13, #2
│ │ +	vrsubhn.i32	d25, q9, <illegal reg q8.5>
│ │  	vsli.16	q10, q14, #3
│ │  	vqshlu.s16	<illegal reg q11.5>, q12, #1
│ │  			@ <UNDEFINED> instruction: 0xffd2ce50
│ │  	vsli.16	d24, d14, #2
│ │  	vmlsl.u16	q12, d1, d2[3]
│ │  	vmull.p<illegal width 16>	<illegal reg q15.5>, d17, d15
│ │  			@ <UNDEFINED> instruction: 0xffd24ff0
│ │ @@ -930469,15 +930469,15 @@
│ │  	b.n	364ac6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8242>
│ │  	ldmia	r3, {r0, r1, r3, r4, r5}
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3646ce <uniffi_pbcli_checksum_method_api_base@@Base+0x1f7e4a>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r1, r5, r8, r9, sl, fp, ip, sp, lr}
│ │  	vqrdmlah.s16	<illegal reg q11.5>, <illegal reg q8.5>, d6[3]
│ │ -			@ <UNDEFINED> instruction: 0xffd1ec71
│ │ +			@ <UNDEFINED> instruction: 0xffd1ec98
│ │  	vqshrun.s32	d20, q8, #13
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3648c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f803c>
│ │  	asrs	r0, r5, #1
│ │  	b.n	363ee8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f7664>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3646ee <uniffi_pbcli_checksum_method_api_base@@Base+0x1f7e6a>
│ │ @@ -930579,15 +930579,15 @@
│ │  	b.n	364bce <uniffi_pbcli_checksum_method_api_base@@Base+0x1f834a>
│ │  	ldmia	r2!, {r0, r3, r4, r5, r6, r7}
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3647d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f7f52>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r1, r3, r4, r9, sl, fp, ip, sp, lr}
│ │  	vqrdmulh.s16	<illegal reg q11.5>, <illegal reg q8.5>, d6[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd1bcf1
│ │ +			@ <UNDEFINED> instruction: 0xffd1bd18
│ │  	vaddl.u16	q9, d3, d0
│ │  	b.n	363fca <uniffi_pbcli_checksum_method_api_base@@Base+0x1f7746>
│ │  	asrs	r0, r0, #32
│ │  	b.n	3647ee <uniffi_pbcli_checksum_method_api_base@@Base+0x1f7f6a>
│ │  	movs	r0, r0
│ │  	b.n	364bf2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f836e>
│ │  	movs	r1, r0
│ │ @@ -930690,15 +930690,15 @@
│ │  	b.n	3648d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f804e>
│ │  	movs	r0, #39	@ 0x27
│ │  	b.n	364cd6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8452>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3646b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f7e34>
│ │  	ldr	r0, [pc, #192]	@ (36465c <uniffi_pbcli_checksum_method_api_base@@Base+0x1f7dd8>)
│ │  	ldmia.w	sp!, {r1, r3, r6, r9, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xeafe4a23
│ │ +			@ <UNDEFINED> instruction: 0xeafe4a4a
│ │  			@ <UNDEFINED> instruction: 0xffd34c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	364ac8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8244>
│ │  	beq.n	3645e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f7d5c>
│ │  	b.n	364a4c <uniffi_pbcli_checksum_method_api_base@@Base+0x1f81c8>
│ │  	adds	r0, #0
│ │  	b.n	364cf6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8472>
│ │ @@ -931009,29 +931009,29 @@
│ │  			@ <UNDEFINED> instruction: 0xebfd8020
│ │  	b.n	364288 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f7a04>
│ │  	movs	r0, r1
│ │  	b.n	364b96 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8312>
│ │  	beq.n	364890 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f800c>
│ │  	b.n	364cf0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f846c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r2, r7, r9, sl, fp, sp, pc}
│ │ -	vmul.f16	q10, <illegal reg q1.5>, d3[3]
│ │ +	ldmia.w	sp!, {r0, r2, r3, r5, r7, r9, sl, fp, sp, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffd34992
│ │  	vraddhn.i32	d22, <illegal reg q1.5>, q12
│ │  			@ <UNDEFINED> instruction: 0xffd14928
│ │  	movs	r5, r2
│ │  	lsls	r4, r3, #27
│ │  	movs	r0, r0
│ │  	lsls	r4, r0, #28
│ │  	movs	r0, r0
│ │ -	add	r5, sp, #56	@ 0x38
│ │ -			@ <UNDEFINED> instruction: 0xffd3add6
│ │ +	add	r5, sp, #212	@ 0xd4
│ │ +			@ <UNDEFINED> instruction: 0xffd3adfd
│ │  			@ <UNDEFINED> instruction: 0xffd37a9f
│ │ -	vqshl.u64	d20, d19, #17
│ │ +	vqshl.u64	q10, q5, #17
│ │  	vrshr.u16	q11, q8, #13
│ │ -			@ <UNDEFINED> instruction: 0xffd13f51
│ │ +			@ <UNDEFINED> instruction: 0xffd13f78
│ │  	vsubw.u16	q14, <illegal reg q1.5>, d7
│ │  	vmlal.u16	q10, d2, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	364bda <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8356>
│ │  	asrs	r7, r1, #32
│ │  	b.n	364fde <uniffi_pbcli_checksum_method_api_base@@Base+0x1f875a>
│ │  	cbz	r2, 3648a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f801e>
│ │ @@ -931095,16 +931095,16 @@
│ │  	b.n	36506e <uniffi_pbcli_checksum_method_api_base@@Base+0x1f87ea>
│ │  	ands	r0, r0
│ │  	b.n	365072 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f87ee>
│ │  	ldmia	r1!, {r4, r6, r7}
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	364c7a <uniffi_pbcli_checksum_method_api_base@@Base+0x1f83f6>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r5, r7, r9, sl, lr}
│ │ -	vrshr.u16	d26, d24, #13
│ │ +	ldmia.w	sp!, {r1, r2, r3, r6, r7, r9, sl, lr}
│ │ +	vrshr.u16	q13, <illegal reg q7.5>, #13
│ │  			@ <UNDEFINED> instruction: 0xffd34c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	364e68 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f85e4>
│ │  	ands	r0, r0
│ │  	b.n	364c92 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f840e>
│ │  	movs	r0, r2
│ │  	b.n	364476 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f7bf2>
│ │ @@ -931612,19 +931612,19 @@
│ │  	b.n	36510a <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8886>
│ │  	beq.n	364e04 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8580>
│ │  	b.n	365264 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f89e0>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r1, r2, pc}
│ │  	b.n	365116 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8892>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │ -	add	r3, r8
│ │ -	vrshr.u16	q10, <illegal reg q3.5>, #13
│ │ -	vrshr.u16	d20, d19, #13
│ │ -	vrshr.u16	d20, d11, #13
│ │ -	vrshr.u16	q15, q1, #13
│ │ +	add	r2, sp
│ │ +	vrshr.u16	q10, q15, #13
│ │ +	vrshr.u16	q10, q5, #13
│ │ +	vmlal.u16	q10, d3, d2[0]
│ │ +	vrshr.u16	q15, <illegal reg q12.5>, #13
│ │  	vqshrun.s32	d20, q8, #13
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	365310 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8a8c>
│ │  	str	r0, [r0, r0]
│ │  	b.n	36513a <uniffi_pbcli_checksum_method_api_base@@Base+0x1f88b6>
│ │  	movs	r0, r0
│ │  	b.n	36549e <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8c1a>
│ │ @@ -931662,15 +931662,15 @@
│ │  	b.n	365186 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8902>
│ │  	movs	r0, #39	@ 0x27
│ │  	b.n	36558a <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8d06>
│ │  	asrs	r1, r0, #32
│ │  	b.n	364f6c <uniffi_pbcli_checksum_method_api_base@@Base+0x1f86e8>
│ │  	ldr	r0, [pc, #192]	@ (364f10 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f868c>)
│ │  	ldmia.w	sp!, {r0, r2, r3, r4, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xeafe416f
│ │ +			@ <UNDEFINED> instruction: 0xeafe4196
│ │  	vshr.u16	d17, d16, #13
│ │  	b.n	36497e <uniffi_pbcli_checksum_method_api_base@@Base+0x1f80fa>
│ │  	movs	r0, r0
│ │  	b.n	365504 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8c80>
│ │  	movs	r5, r0
│ │  	lsrs	r0, r0, #8
│ │  	lsls	r0, r0, #1
│ │ @@ -931728,15 +931728,15 @@
│ │  	b.n	36521e <uniffi_pbcli_checksum_method_api_base@@Base+0x1f899a>
│ │  	movs	r0, #39	@ 0x27
│ │  	b.n	365622 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8d9e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	365004 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8780>
│ │  	ldr	r0, [pc, #192]	@ (364fa8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8724>)
│ │  	ldmia.w	sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xeafe40d7
│ │ +			@ <UNDEFINED> instruction: 0xeafe40fe
│ │  	vmlal.u16	q10, d3, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	36523a <uniffi_pbcli_checksum_method_api_base@@Base+0x1f89b6>
│ │  	lsrs	r1, r1, #25
│ │  			@ <UNDEFINED> instruction: 0xebff101c
│ │  	b.n	364a40 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f81bc>
│ │  	movs	r0, r0
│ │ @@ -931943,15 +931943,15 @@
│ │  	b.n	365554 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8cd0>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r2, r4, r5, r6, r8, r9, fp, sp, lr, pc}
│ │  	movs	r7, r2
│ │  			@ <UNDEFINED> instruction: 0xff9cffff
│ │  	adc.w	r0, ip, r7, lsr #32
│ │  	bcc.n	3650c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f883e>
│ │ -			@ <UNDEFINED> instruction: 0xffd16df1
│ │ +			@ <UNDEFINED> instruction: 0xffd16e18
│ │  			@ <UNDEFINED> instruction: 0xffd3eb0c
│ │  	movs	r7, r2
│ │  			@ <UNDEFINED> instruction: 0xeafc0017
│ │  	lsls	r4, r7, #5
│ │  	movs	r0, r0
│ │  	lsls	r0, r0, #6
│ │  	movs	r0, r0
│ │ @@ -931961,17 +931961,17 @@
│ │  	movs	r0, r0
│ │  	lsls	r4, r6, #5
│ │  	movs	r0, r0
│ │  	lsls	r4, r6, #5
│ │  	movs	r0, r0
│ │  			@ <UNDEFINED> instruction: 0xeaac0017
│ │  	bcc.n	3650fe <uniffi_pbcli_checksum_method_api_base@@Base+0x1f887a>
│ │ -			@ <UNDEFINED> instruction: 0xffd16cf9
│ │ +			@ <UNDEFINED> instruction: 0xffd16d20
│ │  	vrsra.u16	d29, d29, #13
│ │ -			@ <UNDEFINED> instruction: 0xffd16d35
│ │ +			@ <UNDEFINED> instruction: 0xffd16d5c
│ │  	vrsra.u16	d26, d27, #13
│ │  	vshll.u16	q15, d4, #2
│ │  	movs	r7, r2
│ │  	ldr	r4, [pc, #64]	@ (365154 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f88d0>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	365634 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f8db0>
│ │  	movs	r0, r6
│ │ @@ -933431,17 +933431,17 @@
│ │  	b.n	366512 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9c8e>
│ │  	movs	r0, #0
│ │  	b.n	366516 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9c92>
│ │  	ands	r0, r0
│ │  	b.n	36651a <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9c96>
│ │  	stmia	r4!, {r1, r2, r5, r7}
│ │  			@ <UNDEFINED> instruction: 0xebfdff14
│ │ -			@ <UNDEFINED> instruction: 0xeaffbb01
│ │ -	vrshr.u16	d22, d24, #13
│ │ -	vmla.f16	<illegal reg q9.5>, <illegal reg q1.5>, d4[1]
│ │ +			@ <UNDEFINED> instruction: 0xeaffbb28
│ │ +	vrshr.u16	q11, <illegal reg q7.5>, #13
│ │ +	vsra.u16	<illegal reg q9.5>, <illegal reg q9.5>, #13
│ │  	vmul.i16	<illegal reg q12.5>, <illegal reg q9.5>, d2[2]
│ │  	vmlsl.u16	q11, d1, d1[3]
│ │  	vqshl.u64	q10, q4, #17
│ │  	vmla.f16	q13, q9, d0[2]
│ │  	vsra.u64	d26, d24, #47
│ │  			@ <UNDEFINED> instruction: 0xffd19cb4
│ │  			@ <UNDEFINED> instruction: 0xffd17b98
│ │ @@ -933460,28 +933460,28 @@
│ │  	vqshl.u16	<illegal reg q11.5>, q12, #1
│ │  	movs	r7, r2
│ │  	ldrb	r4, [r6, #0]
│ │  	movs	r7, r2
│ │  	ldrb	r0, [r6, #0]
│ │  	movs	r7, r2
│ │  	lsls	r7, r6, #31
│ │ -			@ <UNDEFINED> instruction: 0xffd49f02
│ │ +			@ <UNDEFINED> instruction: 0xffd49f29
│ │  			@ <UNDEFINED> instruction: 0xffd3bf87
│ │  	vshr.u16	d28, d12, #15
│ │  	movs	r7, r2
│ │  	str	r7, [sp, #960]	@ 0x3c0
│ │  	vmlal.u16	<illegal reg q12.5>, d1, d8
│ │  			@ <UNDEFINED> instruction: 0xffd199bc
│ │  			@ <UNDEFINED> instruction: 0xffd199d4
│ │ -	vrsubhn.i32	d23, <illegal reg q8.5>, <illegal reg q10.5>
│ │ +	vmlsl.u16	<illegal reg q11.5>, d17, d4[1]
│ │  			@ <UNDEFINED> instruction: 0xffd34d78
│ │  	vmlal.u16	<illegal reg q11.5>, d1, d0
│ │  	movs	r7, r2
│ │  	add	r2, pc, #144	@ (adr r2, 365ef4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9670>)
│ │ -	vmlal.u16	<illegal reg q8.5>, d1, d1[1]
│ │ +	vrshr.u16	<illegal reg q8.5>, q8, #15
│ │  			@ <UNDEFINED> instruction: 0xffd348f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	36638c <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9b08>
│ │  	beq.n	365ea4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9620>
│ │  	b.n	366310 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9a8c>
│ │  	asrs	r0, r4, #2
│ │  	b.n	3659b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9134>
│ │ @@ -933620,17 +933620,17 @@
│ │  	asrs	r4, r1, #32
│ │  	b.n	365ae4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9260>
│ │  	movs	r0, r0
│ │  	b.n	3660c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9844>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3660cc <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9848>
│ │  			@ <UNDEFINED> instruction: 0xb644
│ │ -			@ <UNDEFINED> instruction: 0xebfe5df8
│ │ +			@ <UNDEFINED> instruction: 0xebfe5e1f
│ │  	vrsra.u64	d21, d4, #45
│ │ -			@ <UNDEFINED> instruction: 0xffd25e10
│ │ +			@ <UNDEFINED> instruction: 0xffd25e37
│ │  	vsubw.u16	<illegal reg q10.5>, <illegal reg q9.5>, d28
│ │  			@ <UNDEFINED> instruction: 0xffd24c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3664e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9c60>
│ │  	beq.n	365fdc <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9758>
│ │  	b.n	366468 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9be4>
│ │  	movs	r0, r0
│ │ @@ -933723,15 +933723,15 @@
│ │  	asrs	r4, r1, #32
│ │  	b.n	365bd8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9354>
│ │  	movs	r0, r0
│ │  	b.n	3661bc <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9938>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3661c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f993c>
│ │  			@ <UNDEFINED> instruction: 0xb607
│ │ -			@ <UNDEFINED> instruction: 0xebfe5d04
│ │ +			@ <UNDEFINED> instruction: 0xebfe5d2b
│ │  	vsubl.u16	<illegal reg q10.5>, d19, d16
│ │  	vmlal.u16	q10, d2, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3663f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9b72>
│ │  	ldmia	r1!, {r0, r2, r6}
│ │  	add.w	r0, r4, r0
│ │  	b.n	36675e <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9eda>
│ │ @@ -933744,15 +933744,15 @@
│ │  	asrs	r4, r1, #32
│ │  	b.n	365c0c <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9388>
│ │  	movs	r0, r0
│ │  	b.n	3661f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f996c>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3661f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9970>
│ │  	push	{r1, r3, r4, r5, r6, r7, lr}
│ │ -			@ <UNDEFINED> instruction: 0xebfe5cd0
│ │ +			@ <UNDEFINED> instruction: 0xebfe5cf7
│ │  	vmlal.u16	<illegal reg q10.5>, d3, d4[3]
│ │  	vaddl.u16	q8, d2, d0
│ │  	b.n	366786 <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9f02>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (36612c <uniffi_pbcli_checksum_method_api_base@@Base+0x1f98a8>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	36660c <uniffi_pbcli_checksum_method_api_base@@Base+0x1f9d88>
│ │ @@ -935185,17 +935185,17 @@
│ │  	movs	r0, #0
│ │  	b.n	3674fa <uniffi_pbcli_checksum_method_api_base@@Base+0x1fac76>
│ │  	stmia	r0!, {r1, r2, r3, r5, r7}
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	367582 <uniffi_pbcli_checksum_method_api_base@@Base+0x1facfe>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r1, r2, r3, r5, r8, sl, fp, lr, pc}
│ │ -	vqshl.u16	d22, d9, #2
│ │ +			@ <UNDEFINED> instruction: 0xffd26740
│ │  			@ <UNDEFINED> instruction: 0xffd3cd06
│ │ -	vqshlu.s64	q11, <illegal reg q8.5>, #18
│ │ +	vqshl.u16	d22, d8, #2
│ │  			@ <UNDEFINED> instruction: 0xffd34df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3672f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1faa74>
│ │  	ands	r0, r0
│ │  	b.n	367122 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fa89e>
│ │  	movs	r0, r0
│ │  	b.n	366906 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fa082>
│ │ @@ -935439,18 +935439,18 @@
│ │  	b.n	367732 <uniffi_pbcli_checksum_method_api_base@@Base+0x1faeae>
│ │  	strh	r5, [r0, #0]
│ │  	b.n	367336 <uniffi_pbcli_checksum_method_api_base@@Base+0x1faab2>
│ │  			@ <UNDEFINED> instruction: 0xffdceaff
│ │  	subs	r3, #96	@ 0x60
│ │  	vsubl.u16	q8, d1, d4
│ │  	movs	r0, r0
│ │ -	str	r3, [sp, #276]	@ 0x114
│ │ -			@ <UNDEFINED> instruction: 0xffd3f743
│ │ -	vsra.u16	d18, d12, #14
│ │ -	vmla.i16	q15, <illegal reg q1.5>, d7[3]
│ │ +	str	r3, [sp, #432]	@ 0x1b0
│ │ +			@ <UNDEFINED> instruction: 0xffd3f76a
│ │ +	vmla.f16	q9, q1, d3[0]
│ │ +	vshr.u64	d30, d6, #45
│ │  	vrsra.u64	d21, d15, #46
│ │  			@ <UNDEFINED> instruction: 0xffd1cafa
│ │  			@ <UNDEFINED> instruction: 0xffd2cbb0
│ │  	vmlal.u16	q9, d1, d5[2]
│ │  	vmlal.u16	q10, d1, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	36736a <uniffi_pbcli_checksum_method_api_base@@Base+0x1faae6>
│ │ @@ -935990,23 +935990,23 @@
│ │  	b.n	367056 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fa7d2>
│ │  	movs	r1, r1
│ │  	b.n	36781a <uniffi_pbcli_checksum_method_api_base@@Base+0x1faf96>
│ │  	beq.n	36750c <uniffi_pbcli_checksum_method_api_base@@Base+0x1fac88>
│ │  	b.n	367974 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fb0f0>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r1, r3, r5, r9, sl, lr, pc}
│ │ -	vaddl.u16	q11, d2, d26
│ │ +	vshr.u16	q11, <illegal reg q0.5>, #14
│ │  	vqshl.u16	q14, q7, #3
│ │ -	vsra.u16	q11, q7, #14
│ │ +	vaddw.u16	q11, q9, d5
│ │  			@ <UNDEFINED> instruction: 0xffd36989
│ │  	vrsubhn.i32	d28, <illegal reg q8.5>, q9
│ │ -	vaddl.u16	q11, d18, d18
│ │ +	vmla.i16	q11, q9, d1[1]
│ │  	vmul.i16	q11, <illegal reg q9.5>, d5[1]
│ │  	vrsubhn.i32	d28, <illegal reg q0.5>, q7
│ │ -	vaddl.u16	q11, d2, d14
│ │ +	vshr.u16	d22, d21, #14
│ │  			@ <UNDEFINED> instruction: 0xffd34bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	367a2c <uniffi_pbcli_checksum_method_api_base@@Base+0x1fb1a8>
│ │  	movs	r0, r0
│ │  	b.n	367bb6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fb332>
│ │  	movs	r4, r2
│ │  	lsrs	r0, r0, #8
│ │ @@ -936098,17 +936098,17 @@
│ │  			@ <UNDEFINED> instruction: 0xe9804020
│ │  	b.n	3670da <uniffi_pbcli_checksum_method_api_base@@Base+0x1fa856>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	367d22 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fb49e>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r1, r3, r5, r8, sl, lr, pc}
│ │ -	vmlsl.u16	<illegal reg q13.5>, d18, d27
│ │ +			@ <UNDEFINED> instruction: 0xffd2bad2
│ │  	vsli.16	q14, q3, #3
│ │ -			@ <UNDEFINED> instruction: 0xffd2bad7
│ │ +			@ <UNDEFINED> instruction: 0xffd2bafe
│ │  	vsri.64	q14, q9, #45
│ │  			@ <UNDEFINED> instruction: 0xffd24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	367b1c <uniffi_pbcli_checksum_method_api_base@@Base+0x1fb298>
│ │  	beq.n	36764c <uniffi_pbcli_checksum_method_api_base@@Base+0x1fadc8>
│ │  	b.n	367aa0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fb21c>
│ │  	bge.n	36760a <uniffi_pbcli_checksum_method_api_base@@Base+0x1fad86>
│ │ @@ -936242,17 +936242,17 @@
│ │  	vrhadd.u<illegal width 64>	d14, d5, d31
│ │  	movs	r0, r0
│ │  	b.n	367dc6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fb542>
│ │  			@ <UNDEFINED> instruction: 0xffbccaff
│ │  	beq.n	367764 <uniffi_pbcli_checksum_method_api_base@@Base+0x1faee0>
│ │  	b.n	367bc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fb340>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r2, r6, r9, sl, fp, ip, sp, lr}
│ │ -	vmla.i16	<illegal reg q8.5>, <illegal reg q9.5>, d1[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd3a346
│ │ +	ldmia.w	sp!, {r0, r2, r3, r5, r6, r9, sl, fp, ip, sp, lr}
│ │ +	vaddw.u16	<illegal reg q8.5>, <illegal reg q1.5>, d8
│ │ +			@ <UNDEFINED> instruction: 0xffd3a36d
│ │  			@ <UNDEFINED> instruction: 0xffd3aabb
│ │  	vmull.u16	q10, d2, d14
│ │  	vaddl.u16	q8, d1, d4
│ │  	b.n	367288 <uniffi_pbcli_checksum_method_api_base@@Base+0x1faa04>
│ │  	movs	r0, r0
│ │  	b.n	36786c <uniffi_pbcli_checksum_method_api_base@@Base+0x1fafe8>
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -936455,31 +936455,31 @@
│ │  	b.n	367a14 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fb190>
│ │  	pop	{r0, r1, r2, r3, r4, r6, r7, pc}
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	367c3e <uniffi_pbcli_checksum_method_api_base@@Base+0x1fb3ba>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r3, r4, r5, r8, r9, lr, pc}
│ │  	movs	r7, r2
│ │ -	strb	r0, [r3, #15]
│ │ +	strb	r7, [r7, #15]
│ │  	vmull.p<illegal width 16>	q14, d3, d3
│ │  	vsubw.u16	q14, q1, d16
│ │  	movs	r7, r2
│ │  	ldrb	r4, [r4, r4]
│ │  	movs	r7, r2
│ │ -	strb	r4, [r3, #14]
│ │ +	strb	r3, [r0, #15]
│ │  	vmls.f16	q11, <illegal reg q1.5>, d4[1]
│ │  	vmlal.u16	q14, d18, d4[3]
│ │  	movs	r7, r2
│ │  	ldrb	r0, [r6, r3]
│ │  	movs	r7, r2
│ │  	stmia	r2!, {r3, r6, r7}
│ │  	movs	r7, r2
│ │  	stmia	r2!, {r2, r6, r7}
│ │  	movs	r7, r2
│ │ -	ldrh	r7, [r4, r7]
│ │ +	ldrb	r6, [r1, r0]
│ │  	vsra.u64	<illegal reg q9.5>, q2, #45
│ │  	vmlsl.u16	q8, d17, d25
│ │  			@ <UNDEFINED> instruction: 0xffd24c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	367e5c <uniffi_pbcli_checksum_method_api_base@@Base+0x1fb5d8>
│ │  	movs	r1, r0
│ │  	b.n	367c86 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fb402>
│ │ @@ -937302,16 +937302,16 @@
│ │  	b.n	367fa0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fb71c>
│ │  	movs	r7, r0
│ │  	asrs	r0, r4, #6
│ │  	lsls	r1, r0, #4
│ │  	stmia.w	r5, {r2}
│ │  	b.n	3683ae <uniffi_pbcli_checksum_method_api_base@@Base+0x1fbb2a>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r1, r2, r3, r7, r9, fp, ip, pc}
│ │ -	vrshr.u16	d24, d9, #13
│ │ +	ldmia.w	sp!, {r0, r2, r4, r5, r7, r9, fp, ip, pc}
│ │ +	vmlal.u16	q12, d3, d0[0]
│ │  	vaddw.u16	q8, <illegal reg q1.5>, d8
│ │  	movs	r0, r0
│ │  	lsls	r0, r7, #3
│ │  	movs	r0, r0
│ │  	lsls	r4, r6, #6
│ │  	movs	r0, r0
│ │  	lsls	r4, r4, #6
│ │ @@ -937320,15 +937320,15 @@
│ │  	movs	r7, r2
│ │  	lsls	r0, r2, #6
│ │  	movs	r0, r0
│ │  	pop	{r2, r3, r5, pc}
│ │  	movs	r7, r2
│ │  	ldr	r3, [sp, #592]	@ 0x250
│ │  	movs	r7, r2
│ │ -	ldr	r1, [sp, #712]	@ 0x2c8
│ │ +	ldr	r1, [sp, #868]	@ 0x364
│ │  	vsri.16	d21, d24, #13
│ │  	movs	r7, r2
│ │  	movs	r1, r0
│ │  	b.n	3687e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fbf62>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r3, [pc, #960]	@ (36846c <uniffi_pbcli_checksum_method_api_base@@Base+0x1fbbe8>)
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │ @@ -937515,25 +937515,25 @@
│ │  	b.n	3688e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fc05c>
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	36898a <uniffi_pbcli_checksum_method_api_base@@Base+0x1fc106>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r1, r2, r4, r5, r7, r8, r9, sl, ip, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r6, r7, r8, r9, sl, ip, pc}
│ │  	vaddl.u16	q8, d3, d1
│ │  	b.n	368596 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fbd12>
│ │  	asrs	r0, r1, #32
│ │  	b.n	367d98 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fb514>
│ │  	movs	r0, #85	@ 0x55
│ │  	b.n	36899e <uniffi_pbcli_checksum_method_api_base@@Base+0x1fc11a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	368380 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fbafc>
│ │  	bcc.n	368296 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fba12>
│ │ -			@ <UNDEFINED> instruction: 0xeafe977e
│ │ +			@ <UNDEFINED> instruction: 0xeafe97a5
│ │  	vmlal.u16	q10, d3, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3685b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fbd2e>
│ │  	asrs	r0, r5, #2
│ │  	b.n	3689b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fc132>
│ │  	cbz	r7, 3682bc <uniffi_pbcli_checksum_method_api_base@@Base+0x1fba38>
│ │  			@ <UNDEFINED> instruction: 0xfa040001
│ │ @@ -942359,27 +942359,27 @@
│ │  	b.n	36b12e <uniffi_pbcli_checksum_method_api_base@@Base+0x1fe8aa>
│ │  	movs	r3, r1
│ │  	b.n	36b172 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fe8ee>
│ │  	ands	r0, r0
│ │  	b.n	36b176 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fe8f2>
│ │  	cbz	r7, 36aa5a <uniffi_pbcli_checksum_method_api_base@@Base+0x1fe1d6>
│ │  			@ <UNDEFINED> instruction: 0xebfdffcf
│ │ -			@ <UNDEFINED> instruction: 0xeaff4f42
│ │ +			@ <UNDEFINED> instruction: 0xeaff4f69
│ │  	vshr.u16	d26, d3, #13
│ │  	vrsubhn.i32	d27, q1, q7
│ │ -	vqrdmulh.s16	<illegal reg q15.5>, <illegal reg q1.5>, d6[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd3fd75
│ │  	vsli.64	<illegal reg q13.5>, q7, #18
│ │ -			@ <UNDEFINED> instruction: 0xffd3fd1e
│ │ +	vqrdmulh.s16	<illegal reg q15.5>, <illegal reg q1.5>, d5[0]
│ │  	vsli.64	d27, d2, #18
│ │ -			@ <UNDEFINED> instruction: 0xffd3fcd2
│ │ +			@ <UNDEFINED> instruction: 0xffd3fcf9
│ │  	vsubw.u16	<illegal reg q12.5>, q9, d25
│ │  			@ <UNDEFINED> instruction: 0xffd29341
│ │  	vqshlu.s16	<illegal reg q13.5>, q5, #2
│ │  	vsri.64	<illegal reg q13.5>, q1, #45
│ │ -			@ <UNDEFINED> instruction: 0xffd3fbf6
│ │ +			@ <UNDEFINED> instruction: 0xffd3fc1d
│ │  	vqshrun.s32	d20, q8, #14
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	36af94 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fe710>
│ │  	str	r0, [r7, r0]
│ │  	b.n	36a5bc <uniffi_pbcli_checksum_method_api_base@@Base+0x1fdd38>
│ │  	ands	r0, r0
│ │  	b.n	36adc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fe53e>
│ │ @@ -943036,16 +943036,16 @@
│ │  	beq.n	36b090 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fe80c>
│ │  	b.n	36b4f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fec6c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r1, r3, r5, r7, r9, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffd28bbc
│ │  	vrshr.u16	<illegal reg q11.5>, q13, #14
│ │  			@ <UNDEFINED> instruction: 0xffd28b8c
│ │ -	vmlsl.u16	q10, d2, d2[2]
│ │ -	vmlsl.u16	q10, d3, d2[0]
│ │ +	vrsubhn.i32	d20, q9, <illegal reg q4.5>
│ │ +	vmlsl.u16	q10, d3, d1[3]
│ │  	vsra.u64	<illegal reg q11.5>, q3, #45
│ │  	vmull.u16	q12, d18, d0[3]
│ │  	vsra.u64	d23, d10, #46
│ │  	vmlsl.u16	q12, d18, d28
│ │  	vsra.u64	<illegal reg q11.5>, q11, #46
│ │  			@ <UNDEFINED> instruction: 0xffd28b08
│ │  	vsubl.u16	<illegal reg q11.5>, d2, d18
│ │ @@ -943283,16 +943283,16 @@
│ │  	movs	r3, r1
│ │  	b.n	36b9e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff162>
│ │  	asrs	r1, r1, #2
│ │  	b.n	36b9ea <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff166>
│ │  			@ <UNDEFINED> instruction: 0xffc3eaff
│ │  	strb	r6, [r2, #0]
│ │  	vshr.u64	d30, d6, #46
│ │ -	vrsra.u64	d20, d18, #48
│ │ -	vrsra.u64	d20, d2, #45
│ │ +	vrsra.u64	q10, <illegal reg q4.5>, #48
│ │ +	vrsra.u64	d20, d25, #45
│ │  	vqrdmlsh.s16	q11, <illegal reg q1.5>, d6[0]
│ │  	vqrdmlsh.s16	<illegal reg q14.5>, q9, d6[0]
│ │  	vqrdmlsh.s16	q11, q0, d6[2]
│ │  	vqrdmlsh.s16	<illegal reg q14.5>, q9, d6[2]
│ │  			@ <UNDEFINED> instruction: 0xffd06f92
│ │  	vshr.u16	d30, d2, #14
│ │  			@ <UNDEFINED> instruction: 0xffd04df0
│ │ @@ -943496,15 +943496,15 @@
│ │  	b.n	36b7da <uniffi_pbcli_checksum_method_api_base@@Base+0x1fef56>
│ │  	beq.n	36b4cc <uniffi_pbcli_checksum_method_api_base@@Base+0x1fec48>
│ │  	b.n	36b934 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff0b0>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r7, r9, ip, pc}
│ │  	vqrdmulh.s16	q11, q9, d2[0]
│ │  	vabal.u16	<illegal reg q8.5>, d2, d4
│ │ -	vaddw.u16	q10, q9, d10
│ │ +	vsra.u64	d20, d17, #46
│ │  			@ <UNDEFINED> instruction: 0xffd36d92
│ │  	vsri.64	<illegal reg q8.5>, q2, #46
│ │  	vqrdmulh.s16	q11, q1, d6[1]
│ │  	vsri.64	d17, d0, #46
│ │  			@ <UNDEFINED> instruction: 0xffd21eb4
│ │  	movs	r7, r2
│ │  	ldr	r0, [pc, #0]	@ (36b4c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fec44>)
│ │ @@ -944275,45 +944275,45 @@
│ │  	asrs	r0, r1, #32
│ │  	b.n	36c1fe <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff97a>
│ │  	movs	r0, #0
│ │  	b.n	36c2c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ffa3e>
│ │  	add	r5, sp, #240	@ 0xf0
│ │  			@ <UNDEFINED> instruction: 0xebfdffc1
│ │  			@ <UNDEFINED> instruction: 0xeaff3980
│ │ -			@ <UNDEFINED> instruction: 0xffd28c92
│ │ +			@ <UNDEFINED> instruction: 0xffd28cb9
│ │  	vqdmulh.s16	q11, <illegal reg q1.5>, d7[1]
│ │  	vqshlu.s16	d26, d7, #1
│ │  			@ <UNDEFINED> instruction: 0xffd33bfe
│ │  	vshll.u16	<illegal reg q8.5>, d8, #2
│ │  	movs	r7, r2
│ │  	adds	r0, r0, #3
│ │  	movs	r7, r2
│ │  	ldmia	r3, {r0, r1, r2, r3, r5}
│ │  	vmlal.u16	<illegal reg q8.5>, d1, d12
│ │  	movs	r7, r2
│ │ -	add	r5, sp, #504	@ 0x1f8
│ │ +	add	r5, sp, #660	@ 0x294
│ │  	vmls.f16	q13, q1, d3[3]
│ │ -	vmull.u16	q15, d19, d10
│ │ -	vmull.u16	q15, d2, d26
│ │ +			@ <UNDEFINED> instruction: 0xffd3ecb1
│ │ +			@ <UNDEFINED> instruction: 0xffd2ec51
│ │  	vmul.i16	<illegal reg q8.5>, q9, d0[2]
│ │  	movs	r7, r2
│ │  	subs	r0, #120	@ 0x78
│ │ -			@ <UNDEFINED> instruction: 0xffd28b8a
│ │ +			@ <UNDEFINED> instruction: 0xffd28bb1
│ │  	vmlsl.u16	<illegal reg q9.5>, d19, d0
│ │  	vmul.i16	<illegal reg q9.5>, q9, d4[3]
│ │  	vaddl.u16	<illegal reg q8.5>, d2, d12
│ │  	b.n	36b714 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fee90>
│ │  	movs	r0, r5
│ │  	b.n	36c31a <uniffi_pbcli_checksum_method_api_base@@Base+0x1ffa96>
│ │  	movs	r0, #20
│ │  	b.n	36c31e <uniffi_pbcli_checksum_method_api_base@@Base+0x1ffa9a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	36bd00 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff47c>
│ │  	stmia	r3!, {r0, r1, r2, r3, r4, r6, r7}
│ │ -			@ <UNDEFINED> instruction: 0xeafeea45
│ │ +			@ <UNDEFINED> instruction: 0xeafeea6c
│ │  	vaddl.u16	q8, d2, d0
│ │  	b.n	36c28e <uniffi_pbcli_checksum_method_api_base@@Base+0x1ffa0a>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (36bcb4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff430>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	36c114 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff890>
│ │  	ands	r0, r0
│ │ @@ -944342,15 +944342,15 @@
│ │  	b.n	36bf72 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff6ee>
│ │  	asrs	r5, r0, #32
│ │  	b.n	36bf76 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff6f2>
│ │  	movs	r0, #36	@ 0x24
│ │  	b.n	36c37a <uniffi_pbcli_checksum_method_api_base@@Base+0x1ffaf6>
│ │  	ldr	r0, [pc, #192]	@ (36bcfc <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff478>)
│ │  	ldmia.w	sp!, {r1, r5, r7, sl, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xeafeea01
│ │ +			@ <UNDEFINED> instruction: 0xeafeea28
│ │  			@ <UNDEFINED> instruction: 0xffd24c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	36c168 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff8e4>
│ │  	asrs	r4, r1, #3
│ │  	b.n	36b790 <uniffi_pbcli_checksum_method_api_base@@Base+0x1fef0c>
│ │  	movs	r0, r6
│ │  	b.n	36c396 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ffb12>
│ │ @@ -944439,17 +944439,17 @@
│ │  	add	r4, sp, #868	@ 0x364
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	36c056 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff7d2>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {}
│ │  	b.n	36c45e <uniffi_pbcli_checksum_method_api_base@@Base+0x1ffbda>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r2, r4, r7, r8, sl, fp, ip, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffd35d2e
│ │ -			@ <UNDEFINED> instruction: 0xffd35d1a
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r5, r7, r8, sl, fp, ip, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffd35d55
│ │ +	vqrdmulh.s16	<illegal reg q10.5>, <illegal reg q1.5>, d1[0]
│ │  	vmlsl.u16	q11, d19, d1[2]
│ │  	vaddl.u16	q8, d1, d0
│ │  	b.n	36c3d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ffb52>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (36bd7c <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff4f8>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	36c25c <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff9d8>
│ │ @@ -944485,16 +944485,16 @@
│ │  	b.n	36c0c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff842>
│ │  	movs	r0, #45	@ 0x2d
│ │  	b.n	36c4ca <uniffi_pbcli_checksum_method_api_base@@Base+0x1ffc46>
│ │  	asrs	r1, r0, #32
│ │  	b.n	36beac <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff628>
│ │  	ldr	r4, [pc, #64]	@ (36bdd0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff54c>)
│ │  	ldmia.w	sp!, {r0, r2, r3, r6, sl, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xeafe5c7a
│ │ -	vqdmulh.s16	<illegal reg q10.5>, <illegal reg q1.5>, d6[2]
│ │ +			@ <UNDEFINED> instruction: 0xeafe5ca1
│ │ +	vmull.u16	<illegal reg q10.5>, d19, d13
│ │  	vaddl.u16	q8, d3, d4
│ │  	b.n	36b8e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff05c>
│ │  	movs	r0, r0
│ │  	b.n	36bec4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff640>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldrsh	r4, [r3, r2]
│ │  	movs	r7, r2
│ │ @@ -945234,19 +945234,19 @@
│ │  	lsrs	r0, r2, #28
│ │  	b.n	36c700 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ffe7c>
│ │  	lsls	r0, r4, #10
│ │  	b.n	36c766 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ffee2>
│ │  	beq.n	36c460 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ffbdc>
│ │  	b.n	36c8c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20003c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r2, r3, r6, r8, ip, sp}
│ │ -	vaddw.u16	q14, <illegal reg q9.5>, d14
│ │ -			@ <UNDEFINED> instruction: 0xffd278d4
│ │ -	vrsra.u16	<illegal reg q9.5>, q5, #13
│ │ -	vmla.f16	q14, <illegal reg q1.5>, d6[2]
│ │ +	ldmia.w	sp!, {r0, r2, r4, r5, r6, r8, ip, sp}
│ │ +	vsra.u64	d28, d21, #45
│ │ +			@ <UNDEFINED> instruction: 0xffd278fb
│ │ +	vsubw.u16	<illegal reg q9.5>, <illegal reg q9.5>, d1
│ │ +	vaddw.u16	q14, <illegal reg q9.5>, d13
│ │  	vmlal.u16	q10, d2, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	36c78a <uniffi_pbcli_checksum_method_api_base@@Base+0x1fff06>
│ │  	movs	r0, #0
│ │  	b.n	36c78e <uniffi_pbcli_checksum_method_api_base@@Base+0x1fff0a>
│ │  	movs	r0, r3
│ │  	b.n	36bf72 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff6ee>
│ │ @@ -945284,15 +945284,15 @@
│ │  	b.n	36bfbe <uniffi_pbcli_checksum_method_api_base@@Base+0x1ff73a>
│ │  	movs	r0, r0
│ │  	b.n	36cb42 <uniffi_pbcli_checksum_method_api_base@@Base+0x2002be>
│ │  			@ <UNDEFINED> instruction: 0xffef0aff
│ │  	ldr	r0, [pc, #0]	@ (36c4a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ffc20>)
│ │  	ldmia.w	sp!, {r1, r4, r8, r9, sl, fp, ip, sp, lr, pc}
│ │  	b.n	36c708 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ffe84>
│ │ -	strb	r3, [r2, r6]
│ │ +	strb	r2, [r7, r6]
│ │  			@ <UNDEFINED> instruction: 0xffd35d54
│ │  	vaddl.u16	q8, d2, d0
│ │  	b.n	36cb58 <uniffi_pbcli_checksum_method_api_base@@Base+0x2002d4>
│ │  	movs	r0, #20
│ │  	asrs	r0, r2, #22
│ │  	movs	r0, #12
│ │  	asrs	r2, r2, #22
│ │ @@ -945447,19 +945447,19 @@
│ │  			@ <UNDEFINED> instruction: 0xeb00ffde
│ │  			@ <UNDEFINED> instruction: 0xeaff0001
│ │  	b.n	36cd56 <uniffi_pbcli_checksum_method_api_base@@Base+0x2004d2>
│ │  	beq.n	36c650 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ffdcc>
│ │  	b.n	36cab0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20022c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r2, r4, r9, sl, fp, ip, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd02f7e
│ │ -	vaddl.u16	q14, d3, d18
│ │ -			@ <UNDEFINED> instruction: 0xffd2bff2
│ │ +			@ <UNDEFINED> instruction: 0xffd02fa5
│ │ +	vmla.i16	q14, <illegal reg q1.5>, d1[1]
│ │ +	vshr.u16	d28, d9, #14
│ │  			@ <UNDEFINED> instruction: 0xffd2fd70
│ │ -			@ <UNDEFINED> instruction: 0xffd02eda
│ │ +			@ <UNDEFINED> instruction: 0xffd02f01
│ │  			@ <UNDEFINED> instruction: 0xffd34ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	36cb58 <uniffi_pbcli_checksum_method_api_base@@Base+0x2002d4>
│ │  	beq.n	36c6b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x1ffe34>
│ │  	b.n	36cadc <uniffi_pbcli_checksum_method_api_base@@Base+0x200258>
│ │  	movs	r2, r0
│ │  	b.n	36c986 <uniffi_pbcli_checksum_method_api_base@@Base+0x200102>
│ │ @@ -947003,15 +947003,15 @@
│ │  	b.n	36d878 <uniffi_pbcli_checksum_method_api_base@@Base+0x200ff4>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r1, r2, r5, r6, r7, sl, lr}
│ │  	vsri.16	d30, d5, #14
│ │  			@ <UNDEFINED> instruction: 0xffd03daa
│ │  			@ <UNDEFINED> instruction: 0xffd2dcd9
│ │  	vqshl.u64	q9, <illegal reg q11.5>, #16
│ │ -	vmla.f16	q12, <illegal reg q0.5>, d3[1]
│ │ +	vsra.u16	q12, q9, #15
│ │  			@ <UNDEFINED> instruction: 0xffd23df6
│ │  			@ <UNDEFINED> instruction: 0xffd2dd25
│ │  			@ <UNDEFINED> instruction: 0xffd02ef1
│ │  	vsli.64	q8, q6, #17
│ │  	movs	r7, r2
│ │  	subs	r4, #222	@ 0xde
│ │  	vmull.u16	<illegal reg q14.5>, d2, d13
│ │ @@ -947020,15 +947020,15 @@
│ │  	movs	r4, r2
│ │  	cmp	r4, #66	@ 0x42
│ │  	vqrshrn.u32	d19, q5, #14
│ │  	vqshrn.u32	d25, <illegal reg q8.5>, #14
│ │  			@ <UNDEFINED> instruction: 0xffd13bbe
│ │  			@ <UNDEFINED> instruction: 0xffd29b95
│ │  	vmull.u16	q11, d17, d7[0]
│ │ -	vqrdmlsh.s16	<illegal reg q11.5>, q1, d0[1]
│ │ +	vqrdmlsh.s16	<illegal reg q11.5>, q1, d7[3]
│ │  	vrsra.u16	<illegal reg q13.5>, q11, #14
│ │  	vrsra.u16	d23, d12, #15
│ │  			@ <UNDEFINED> instruction: 0xffd2c9b4
│ │  	movs	r4, r2
│ │  	subs	r1, #186	@ 0xba
│ │  			@ <UNDEFINED> instruction: 0xffd29991
│ │  			@ <UNDEFINED> instruction: 0xffd1399e
│ │ @@ -947043,62 +947043,62 @@
│ │  			@ <UNDEFINED> instruction: 0xffd13be6
│ │  			@ <UNDEFINED> instruction: 0xffd29bbd
│ │  			@ <UNDEFINED> instruction: 0xffd13b96
│ │  			@ <UNDEFINED> instruction: 0xffd29b6d
│ │  	vmull.u16	q14, d1, d0[2]
│ │  	movs	r4, r2
│ │  	subs	r3, #54	@ 0x36
│ │ -	vsra.u16	<illegal reg q9.5>, q7, #14
│ │ +	vaddw.u16	<illegal reg q9.5>, q9, d5
│ │  			@ <UNDEFINED> instruction: 0xffd33b1a
│ │ -	vmla.f16	<illegal reg q9.5>, q1, d2[0]
│ │ +	vmla.f16	<illegal reg q9.5>, q1, d1[3]
│ │  	vmull.u16	q14, d3, d4[1]
│ │  	movs	r4, r2
│ │  	subs	r2, #242	@ 0xf2
│ │ -	vsra.u16	d19, d10, #14
│ │ -	vmlsl.u16	q14, d3, d6[3]
│ │ -	vsra.u16	<illegal reg q12.5>, q1, #14
│ │ -	vqshl.u16	q12, q4, #2
│ │ +	vmla.f16	<illegal reg q9.5>, q1, d1[0]
│ │ +	vqshlu.s64	d28, d5, #19
│ │ +	vsra.u16	<illegal reg q12.5>, <illegal reg q12.5>, #14
│ │ +	vqshl.u16	q12, <illegal reg q15.5>, #2
│ │  	vrsra.u16	d31, d16, #13
│ │  			@ <UNDEFINED> instruction: 0xffd14b7a
│ │ -	vsra.u16	d23, d16, #15
│ │ +	vsra.u16	<illegal reg q11.5>, <illegal reg q3.5>, #15
│ │  			@ <UNDEFINED> instruction: 0xffd34b24
│ │  			@ <UNDEFINED> instruction: 0xffd139f2
│ │ -	vshr.u16	d19, d10, #14
│ │ +	vmla.i16	<illegal reg q9.5>, q1, d1[0]
│ │  			@ <UNDEFINED> instruction: 0xffd339d6
│ │ -			@ <UNDEFINED> instruction: 0xffd22ffe
│ │ +	vaddl.u16	<illegal reg q9.5>, d2, d21
│ │  	vqrdmlsh.s16	<illegal reg q15.5>, <illegal reg q1.5>, d3[3]
│ │  	vqshl.u64	d28, d16, #17
│ │  	movs	r4, r2
│ │  	subs	r0, #58	@ 0x3a
│ │ -	vqrdmlah.s16	q9, q1, d2[2]
│ │ +	vmull.p<illegal width 16>	q9, d18, d9
│ │  			@ <UNDEFINED> instruction: 0xffd338de
│ │ -			@ <UNDEFINED> instruction: 0xffd22f06
│ │ +			@ <UNDEFINED> instruction: 0xffd22f2d
│ │  	vqdmulh.s16	q9, <illegal reg q1.5>, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffd1c8d4
│ │  	movs	r4, r2
│ │  	subs	r0, #86	@ 0x56
│ │ -			@ <UNDEFINED> instruction: 0xffd22e7e
│ │ +	vmull.p<illegal width 16>	q9, d18, d21
│ │  			@ <UNDEFINED> instruction: 0xffd33a5a
│ │ -	vaddl.u16	<illegal reg q9.5>, d18, d2
│ │ +	vaddl.u16	<illegal reg q9.5>, d18, d25
│ │  	vraddhn.i32	d18, <illegal reg q9.5>, <illegal reg q11.5>
│ │ -			@ <UNDEFINED> instruction: 0xffd17dfb
│ │ +	vmull.p<illegal width 16>	<illegal reg q11.5>, d1, d18
│ │  	vsubl.u16	q8, d2, d24
│ │  	movs	r7, r2
│ │  	subs	r5, #38	@ 0x26
│ │  			@ <UNDEFINED> instruction: 0xffd23d39
│ │  	vsli.16	d16, d8, #2
│ │  	movs	r7, r2
│ │  	subs	r2, #190	@ 0xbe
│ │ -	vmla.i16	<illegal reg q9.5>, q9, d6[2]
│ │ +	vaddw.u16	<illegal reg q9.5>, q1, d13
│ │  	vabal.u16	q9, d3, d11
│ │ -			@ <UNDEFINED> instruction: 0xffd17e5f
│ │ +	vmull.p<illegal width 16>	<illegal reg q11.5>, d17, d6
│ │  	vmull.u16	q8, d2, d0[1]
│ │  	movs	r7, r2
│ │  	subs	r0, #194	@ 0xc2
│ │ -	vqrdmlah.s16	q9, q9, d2[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd22f11
│ │  			@ <UNDEFINED> instruction: 0xffd3befc
│ │  	movs	r4, r2
│ │  	subs	r0, #154	@ 0x9a
│ │  	vqrshrun.s32	d25, <illegal reg q8.5>, #14
│ │  	vmull.u16	<illegal reg q9.5>, d1, d14
│ │  			@ <UNDEFINED> instruction: 0xffd29be5
│ │  			@ <UNDEFINED> instruction: 0xffd13c72
│ │ @@ -947458,30 +947458,30 @@
│ │  	adds	r0, #3
│ │  	b.n	36d984 <uniffi_pbcli_checksum_method_api_base@@Base+0x201100>
│ │  	eors	r7, r4
│ │  			@ <UNDEFINED> instruction: 0xebfcff76
│ │  			@ <UNDEFINED> instruction: 0xeaffd01c
│ │  	b.n	36dd08 <uniffi_pbcli_checksum_method_api_base@@Base+0x201484>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r2, r5, r7, r8, r9, sl, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd2af0a
│ │ -			@ <UNDEFINED> instruction: 0xffd259a4
│ │ +	ldmia.w	sp!, {r0, r2, r3, r6, r7, r8, r9, sl, sp, lr, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffd2af31
│ │ +	vmul.f16	<illegal reg q10.5>, q9, d3[1]
│ │  	vmlal.u16	<illegal reg q15.5>, d3, d4[1]
│ │ -			@ <UNDEFINED> instruction: 0xffd11dd2
│ │ +			@ <UNDEFINED> instruction: 0xffd11df9
│ │  			@ <UNDEFINED> instruction: 0xffd3bb2d
│ │ -			@ <UNDEFINED> instruction: 0xffd01d8a
│ │ +			@ <UNDEFINED> instruction: 0xffd01db1
│ │  	vraddhn.i32	d22, <illegal reg q1.5>, <illegal reg q9.5>
│ │ -			@ <UNDEFINED> instruction: 0xffd1cedf
│ │ -			@ <UNDEFINED> instruction: 0xffd209d1
│ │ +			@ <UNDEFINED> instruction: 0xffd1cf06
│ │ +			@ <UNDEFINED> instruction: 0xffd209f8
│ │  	vsubw.u16	<illegal reg q9.5>, <illegal reg q9.5>, d2
│ │ -	vqrdmulh.s16	q13, q1, d6[1]
│ │ -	vrsra.u16	d26, d26, #14
│ │ -	vqdmulh.s16	<illegal reg q8.5>, q1, d2[1]
│ │ -	vqshrn.u32	d23, <illegal reg q15.5>, #13
│ │ -			@ <UNDEFINED> instruction: 0xffd21e76
│ │ +			@ <UNDEFINED> instruction: 0xffd2ad75
│ │ +			@ <UNDEFINED> instruction: 0xffd2a361
│ │ +			@ <UNDEFINED> instruction: 0xffd21c71
│ │ +	vmul.f16	<illegal reg q11.5>, <illegal reg q1.5>, d6[2]
│ │ +			@ <UNDEFINED> instruction: 0xffd21e9d
│ │  	vaddl.u16	q8, d3, d4
│ │  	b.n	36d3f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x200b74>
│ │  	movs	r0, r0
│ │  	b.n	36d9dc <uniffi_pbcli_checksum_method_api_base@@Base+0x201158>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	hlt	0x0000
│ │  	movs	r4, r2
│ │ @@ -947890,17 +947890,17 @@
│ │  	b.n	36db98 <uniffi_pbcli_checksum_method_api_base@@Base+0x201314>
│ │  	bpl.n	36dbb6 <uniffi_pbcli_checksum_method_api_base@@Base+0x201332>
│ │  			@ <UNDEFINED> instruction: 0xebff0008
│ │  	b.n	36dfa2 <uniffi_pbcli_checksum_method_api_base@@Base+0x20171e>
│ │  	beq.n	36dc9c <uniffi_pbcli_checksum_method_api_base@@Base+0x201418>
│ │  	b.n	36e0fc <uniffi_pbcli_checksum_method_api_base@@Base+0x201878>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r2, r3, sl, fp, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffd36b0a
│ │ -	vsri.16	<illegal reg q10.5>, q15, #13
│ │ +	ldmia.w	sp!, {r0, r2, r4, r5, sl, fp, sp, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffd36b31
│ │ +	vraddhn.i32	d21, <illegal reg q9.5>, <illegal reg q10.5>
│ │  			@ <UNDEFINED> instruction: 0xffd3f748
│ │  	movs	r6, r2
│ │  	ldr	r0, [pc, #328]	@ (36ddc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x201540>)
│ │  			@ <UNDEFINED> instruction: 0xffd14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	36e1a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20191c>
│ │  	beq.n	36dcc0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20143c>
│ │ @@ -948140,26 +948140,26 @@
│ │  	movs	r4, r0
│ │  	b.n	36e1d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x201952>
│ │  	beq.n	36ded0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20164c>
│ │  	b.n	36e330 <uniffi_pbcli_checksum_method_api_base@@Base+0x201aac>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r3, r8, fp, ip, sp, pc}
│ │  	movs	r4, r2
│ │ -	ldr	r6, [r5, #16]
│ │ +	ldr	r5, [r2, #20]
│ │  			@ <UNDEFINED> instruction: 0xffd38d84
│ │ -			@ <UNDEFINED> instruction: 0xffd16902
│ │ +			@ <UNDEFINED> instruction: 0xffd16929
│ │  			@ <UNDEFINED> instruction: 0xffd38d58
│ │ -	vmul.f16	q11, <illegal reg q8.5>, d2[0]
│ │ -			@ <UNDEFINED> instruction: 0xffd368d2
│ │ +	vmul.f16	q11, <illegal reg q8.5>, d1[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd368f9
│ │  			@ <UNDEFINED> instruction: 0xffd38d28
│ │  			@ <UNDEFINED> instruction: 0xffd15d09
│ │  	vrsubhn.i32	d31, <illegal reg q0.5>, q2
│ │  	movs	r6, r2
│ │ -	ldr	r6, [r1, #24]
│ │ -	vmul.f16	q11, <illegal reg q1.5>, d6[2]
│ │ +	ldr	r5, [r6, #24]
│ │ +			@ <UNDEFINED> instruction: 0xffd3698d
│ │  			@ <UNDEFINED> instruction: 0xffd38dbc
│ │  	vaddl.u16	q8, d1, d4
│ │  	b.n	36da14 <uniffi_pbcli_checksum_method_api_base@@Base+0x201190>
│ │  	movs	r0, r0
│ │  	b.n	36dff8 <uniffi_pbcli_checksum_method_api_base@@Base+0x201774>
│ │  	vrhadd.u16	d14, d14, d31
│ │  			@ <UNDEFINED> instruction: 0xb70c
│ │ @@ -948754,19 +948754,19 @@
│ │  	b.n	36eb56 <uniffi_pbcli_checksum_method_api_base@@Base+0x2022d2>
│ │  	add	r3, pc, #92	@ (adr r3, 36e474 <uniffi_pbcli_checksum_method_api_base@@Base+0x201bf0>)
│ │  			@ <UNDEFINED> instruction: 0xebfd0005
│ │  	b.n	36e75e <uniffi_pbcli_checksum_method_api_base@@Base+0x201eda>
│ │  	cmp	r3, #113	@ 0x71
│ │  			@ <UNDEFINED> instruction: 0xebfcffec
│ │  			@ <UNDEFINED> instruction: 0xeaff580e
│ │ -			@ <UNDEFINED> instruction: 0xffd163c0
│ │ +			@ <UNDEFINED> instruction: 0xffd163e7
│ │  	vabdl.u16	<illegal reg q10.5>, d19, d2
│ │ -	vrsra.u16	d22, d20, #15
│ │ +	vrsra.u16	q11, <illegal reg q5.5>, #15
│ │  	vqshl.u64	<illegal reg q10.5>, q3, #19
│ │ -	vsubw.u16	q11, <illegal reg q8.5>, d8
│ │ +	vsubw.u16	q11, <illegal reg q8.5>, d31
│ │  			@ <UNDEFINED> instruction: 0xffd31e99
│ │  			@ <UNDEFINED> instruction: 0xffd14c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	36e964 <uniffi_pbcli_checksum_method_api_base@@Base+0x2020e0>
│ │  	ands	r0, r0
│ │  	b.n	36eb8e <uniffi_pbcli_checksum_method_api_base@@Base+0x20230a>
│ │  	movs	r0, r0
│ │ @@ -948808,15 +948808,15 @@
│ │  	movs	r4, r0
│ │  	b.n	36e42a <uniffi_pbcli_checksum_method_api_base@@Base+0x201ba6>
│ │  	ands	r6, r0
│ │  	b.n	36e7e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x201f5e>
│ │  	movs	r4, r0
│ │  	b.n	36e7e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x201f62>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r7, r8, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r5, r7, r8, pc}
│ │  	vqshrun.s32	d20, q8, #14
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	36e9d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20214c>
│ │  	movs	r0, r0
│ │  	b.n	36eb5e <uniffi_pbcli_checksum_method_api_base@@Base+0x2022da>
│ │  	movs	r6, r1
│ │  	lsrs	r0, r0, #8
│ │ @@ -948895,18 +948895,18 @@
│ │  	b.n	36e8a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x202022>
│ │  	cmp	r3, #49	@ 0x31
│ │  			@ <UNDEFINED> instruction: 0xebfc4000
│ │  	b.n	36ecae <uniffi_pbcli_checksum_method_api_base@@Base+0x20242a>
│ │  	movs	r4, r0
│ │  	b.n	36e8b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x20202e>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, pc}
│ │ -	vsli.16	d19, d22, #2
│ │ -	vshr.u64	q12, <illegal reg q1.5>, #45
│ │ -	vabal.u16	<illegal reg q9.5>, d2, d10
│ │ +	ldmia.w	sp!, {r1, r2, r5, r8, pc}
│ │ +	vsli.16	<illegal reg q9.5>, <illegal reg q6.5>, #2
│ │ +	vshr.u64	q12, q13, #45
│ │ +	vsli.16	d19, d17, #2
│ │  	vaddl.u16	q8, d3, d4
│ │  	b.n	36e0c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x201844>
│ │  	movs	r0, r0
│ │  	b.n	36e6ac <uniffi_pbcli_checksum_method_api_base@@Base+0x201e28>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	cbz	r4, 36e5e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x201d5c>
│ │  	movs	r4, r2
│ │ @@ -948940,15 +948940,15 @@
│ │  	b.n	36e6f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x201e6c>
│ │  	subs	r4, #184	@ 0xb8
│ │  	add.w	r0, r0, r4
│ │  	b.n	36e114 <uniffi_pbcli_checksum_method_api_base@@Base+0x201890>
│ │  	beq.n	36e5ec <uniffi_pbcli_checksum_method_api_base@@Base+0x201d68>
│ │  	b.n	36ea74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2021f0>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r2, r4, r6, r8, r9, sl, fp, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r4, r5, r6, r8, r9, sl, fp, sp, lr, pc}
│ │  	vsli.16	<illegal reg q13.5>, q2, #2
│ │  			@ <UNDEFINED> instruction: 0xffd14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	36eb0c <uniffi_pbcli_checksum_method_api_base@@Base+0x202288>
│ │  	beq.n	36e5fc <uniffi_pbcli_checksum_method_api_base@@Base+0x201d78>
│ │  	b.n	36ea90 <uniffi_pbcli_checksum_method_api_base@@Base+0x20220c>
│ │  	lsls	r0, r4, #5
│ │ @@ -949108,23 +949108,23 @@
│ │  	movs	r2, r1
│ │  	b.n	36ea96 <uniffi_pbcli_checksum_method_api_base@@Base+0x202212>
│ │  	beq.n	36e790 <uniffi_pbcli_checksum_method_api_base@@Base+0x201f0c>
│ │  	b.n	36ebf0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20236c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r6, r7, r9, ip, sp, pc}
│ │  	movs	r4, r2
│ │ -	mrc	15, 6, APSR_nzcv, cr8, cr2, {6}
│ │ +	mrc	15, 7, APSR_nzcv, cr15, cr2, {6}
│ │  	push	{r6, r7}
│ │ -			@ <UNDEFINED> instruction: 0xffd149b7
│ │ +			@ <UNDEFINED> instruction: 0xffd149de
│ │  			@ <UNDEFINED> instruction: 0xffd33d13
│ │  			@ <UNDEFINED> instruction: 0xffd10ed7
│ │ -	vmlal.u16	q11, d1, d27
│ │ +	vqrshrun.s32	d22, q1, #15
│ │  	vsra.u16	<illegal reg q13.5>, q12, #14
│ │  	movs	r4, r2
│ │ -	ldr	r1, [pc, #956]	@ (36eb3c <uniffi_pbcli_checksum_method_api_base@@Base+0x2022b8>)
│ │ +	ldr	r2, [pc, #88]	@ (36e7d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x201f54>)
│ │  	vqrdmulh.s16	<illegal reg q9.5>, <illegal reg q1.5>, d3[1]
│ │  	vaddl.u16	<illegal reg q8.5>, d1, d4
│ │  	b.n	36e2c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x201a44>
│ │  	asrs	r1, r0, #32
│ │  	b.n	36e8ac <uniffi_pbcli_checksum_method_api_base@@Base+0x202028>
│ │  	movs	r7, #104	@ 0x68
│ │  			@ <UNDEFINED> instruction: 0xeafcb134
│ │ @@ -949363,24 +949363,24 @@
│ │  	b.n	36ecda <uniffi_pbcli_checksum_method_api_base@@Base+0x202456>
│ │  	movs	r0, #75	@ 0x4b
│ │  	b.n	36f0de <uniffi_pbcli_checksum_method_api_base@@Base+0x20285a>
│ │  	cbnz	r2, 36e9b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x20212e>
│ │  			@ <UNDEFINED> instruction: 0xebfefff1
│ │  			@ <UNDEFINED> instruction: 0xeaffe13d
│ │  			@ <UNDEFINED> instruction: 0xffd10bff
│ │ -	vsubw.u16	q8, q9, d13
│ │ -			@ <UNDEFINED> instruction: 0xffd30341
│ │ +	vrsra.u64	d16, d20, #46
│ │ +			@ <UNDEFINED> instruction: 0xffd30368
│ │  	vshr.u16	q15, <illegal reg q0.5>, #13
│ │  			@ <UNDEFINED> instruction: 0xffd10afb
│ │  	vmla.i16	q15, q9, d1[2]
│ │  	vshr.u16	d30, d13, #15
│ │  			@ <UNDEFINED> instruction: 0xffd10adf
│ │  			@ <UNDEFINED> instruction: 0xffd2dff5
│ │  			@ <UNDEFINED> instruction: 0xffd10ab7
│ │ -	vmlsl.u16	q15, d2, d26
│ │ +			@ <UNDEFINED> instruction: 0xffd2ea51
│ │  	vshr.u16	q15, <illegal reg q12.5>, #14
│ │  	vshll.u16	q15, d12, #1
│ │  	movs	r6, r2
│ │  	ldr	r7, [pc, #960]	@ (36eda0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20251c>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	36ef00 <uniffi_pbcli_checksum_method_api_base@@Base+0x20267c>
│ │  	beq.n	36ea20 <uniffi_pbcli_checksum_method_api_base@@Base+0x20219c>
│ │ @@ -950032,15 +950032,15 @@
│ │  	add	r0, pc, #232	@ (adr r0, 36f074 <uniffi_pbcli_checksum_method_api_base@@Base+0x2027f0>)
│ │  			@ <UNDEFINED> instruction: 0xebfdff46
│ │  			@ <UNDEFINED> instruction: 0xeaff2e4b
│ │  			@ <UNDEFINED> instruction: 0xffd1398d
│ │  			@ <UNDEFINED> instruction: 0xffd1dcd9
│ │  	vmlsl.u16	q11, d1, d3[2]
│ │  	vmull.p<illegal width 16>	q13, d17, d16
│ │ -	vshr.u64	d16, d29, #47
│ │ +	vmla.i16	q8, <illegal reg q8.5>, d4[2]
│ │  			@ <UNDEFINED> instruction: 0xffd37ebb
│ │  			@ <UNDEFINED> instruction: 0xffd12d5b
│ │  	vqrdmulh.s16	<illegal reg q14.5>, <illegal reg q8.5>, d5[3]
│ │  	vqshl.u16	q11, <illegal reg q11.5>, #1
│ │  	vqshrn.u32	d31, <illegal reg q3.5>, #15
│ │  			@ <UNDEFINED> instruction: 0xffd1ddb1
│ │  	vqshl.u16	d22, d27, #1
│ │ @@ -950464,15 +950464,15 @@
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	36fada <uniffi_pbcli_checksum_method_api_base@@Base+0x203256>
│ │  	beq.n	36f3d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x202b50>
│ │  	b.n	36f834 <uniffi_pbcli_checksum_method_api_base@@Base+0x202fb0>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r2, r3, r7, r8, fp, sp, pc}
│ │  	movs	r4, r2
│ │ -	ldrb	r1, [r1, r7]
│ │ +	ldrb	r0, [r6, r7]
│ │  			@ <UNDEFINED> instruction: 0xffd249ab
│ │  	vqshrn.u32	d17, <illegal reg q9.5>, #15
│ │  	vmul.f16	<illegal reg q8.5>, <illegal reg q0.5>, d5[0]
│ │  			@ <UNDEFINED> instruction: 0xffd1190b
│ │  	vqshrn.u32	d17, <illegal reg q6.5>, #15
│ │  			@ <UNDEFINED> instruction: 0xffd1a9f0
│ │  	movs	r4, r2
│ │ @@ -950653,21 +950653,21 @@
│ │  	subs	r5, #244	@ 0xf4
│ │  			@ <UNDEFINED> instruction: 0xeb00ffd8
│ │  			@ <UNDEFINED> instruction: 0xeaff0001
│ │  	b.n	36fc92 <uniffi_pbcli_checksum_method_api_base@@Base+0x20340e>
│ │  	beq.n	36f58c <uniffi_pbcli_checksum_method_api_base@@Base+0x202d08>
│ │  	b.n	36f9ec <uniffi_pbcli_checksum_method_api_base@@Base+0x203168>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r3, r7, r8, r9, fp, ip, lr}
│ │ -	vsubl.u16	<illegal reg q13.5>, d2, d5
│ │ -	vshr.u16	d16, d26, #14
│ │ -	vshr.u64	<illegal reg q12.5>, q1, #45
│ │ -			@ <UNDEFINED> instruction: 0xffd25b2b
│ │ -	vmla.f16	<illegal reg q13.5>, q1, d5[0]
│ │ -			@ <UNDEFINED> instruction: 0xffd2ff7a
│ │ +	ldmia.w	sp!, {r1, r4, r5, r7, r8, r9, fp, ip, lr}
│ │ +	vsubl.u16	<illegal reg q13.5>, d2, d28
│ │ +	vmla.i16	q8, q1, d1[2]
│ │ +	vshr.u64	<illegal reg q12.5>, <illegal reg q12.5>, #45
│ │ +			@ <UNDEFINED> instruction: 0xffd25b52
│ │ +	vmla.f16	<illegal reg q13.5>, q1, d4[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd2ffa1
│ │  	vaddl.u16	q8, d2, d4
│ │  	b.n	36f0b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x202834>
│ │  	movs	r0, r0
│ │  	b.n	36f69c <uniffi_pbcli_checksum_method_api_base@@Base+0x202e18>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	add	r5, pc, #192	@ (adr r5, 36f644 <uniffi_pbcli_checksum_method_api_base@@Base+0x202dc0>)
│ │  	movs	r4, r2
│ │ @@ -950948,22 +950948,22 @@
│ │  	adds	r0, #3
│ │  	b.n	36f914 <uniffi_pbcli_checksum_method_api_base@@Base+0x203090>
│ │  	ldr	r4, [sp, #924]	@ 0x39c
│ │  			@ <UNDEFINED> instruction: 0xebfdffe2
│ │  			@ <UNDEFINED> instruction: 0xeaffa52c
│ │  	movs	r4, r2
│ │  	push	{r0, r2, r3, r4, r5}
│ │ -	vqrdmlah.s16	<illegal reg q14.5>, q0, d3[0]
│ │ -			@ <UNDEFINED> instruction: 0xffd2de32
│ │ +	vqrdmlah.s16	<illegal reg q14.5>, q0, d2[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd2de59
│ │  	vmls.i16	<illegal reg q11.5>, q9, d7[0]
│ │ -	vshr.u16	<illegal reg q10.5>, q4, #15
│ │ +	vshr.u16	<illegal reg q10.5>, <illegal reg q15.5>, #15
│ │  	vsri.16	<illegal reg q8.5>, <illegal reg q3.5>, #13
│ │  	vmlsl.u16	<illegal reg q12.5>, d17, d27
│ │  			@ <UNDEFINED> instruction: 0xffd0fe1b
│ │ -			@ <UNDEFINED> instruction: 0xffd0576f
│ │ +	vqshl.u64	d21, d6, #16
│ │  	vraddhn.i32	d17, q9, <illegal reg q11.5>
│ │  			@ <UNDEFINED> instruction: 0xffd19afb
│ │  	vsubw.u16	q13, q8, d8
│ │  	movs	r4, r2
│ │  	ldr	r4, [pc, #448]	@ (36f9f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x203170>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	36fd54 <uniffi_pbcli_checksum_method_api_base@@Base+0x2034d0>
│ │ @@ -951120,24 +951120,24 @@
│ │  	adds	r0, #3
│ │  	b.n	36fa9c <uniffi_pbcli_checksum_method_api_base@@Base+0x203218>
│ │  	subs	r0, #33	@ 0x21
│ │  			@ <UNDEFINED> instruction: 0xebfc0001
│ │  	b.n	3700c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x203842>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r1, r3, r4, r5, r7, r8, r9, ip}
│ │ -			@ <UNDEFINED> instruction: 0xffd1fc32
│ │ +			@ <UNDEFINED> instruction: 0xffd1fc59
│ │  			@ <UNDEFINED> instruction: 0xffd2fb7b
│ │ -	vmull.u16	<illegal reg q15.5>, d1, d10
│ │ -	vmlal.u16	<illegal reg q15.5>, d18, d7[0]
│ │ -			@ <UNDEFINED> instruction: 0xffd2fbe2
│ │ +			@ <UNDEFINED> instruction: 0xffd1fc31
│ │ +	vmlal.u16	<illegal reg q15.5>, d18, d6[3]
│ │ +	vmull.u16	<illegal reg q15.5>, d2, d9
│ │  			@ <UNDEFINED> instruction: 0xffd28af7
│ │ -	vqrdmulh.s16	q13, <illegal reg q0.5>, d5[0]
│ │ -			@ <UNDEFINED> instruction: 0xffd2fb9a
│ │ -	vrshr.u16	q12, q2, #14
│ │ -			@ <UNDEFINED> instruction: 0xffd2fb32
│ │ +	vqrdmulh.s16	q13, <illegal reg q0.5>, d4[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd2fbc1
│ │ +	vrshr.u16	q12, <illegal reg q13.5>, #14
│ │ +			@ <UNDEFINED> instruction: 0xffd2fb59
│ │  			@ <UNDEFINED> instruction: 0xffd248f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	36fed8 <uniffi_pbcli_checksum_method_api_base@@Base+0x203654>
│ │  	ands	r1, r0
│ │  	b.n	370102 <uniffi_pbcli_checksum_method_api_base@@Base+0x20387e>
│ │  	movs	r0, r0
│ │  	b.n	370066 <uniffi_pbcli_checksum_method_api_base@@Base+0x2037e2>
│ │ @@ -951759,21 +951759,21 @@
│ │  	movs	r4, r2
│ │  	subs	r5, #138	@ 0x8a
│ │  			@ <UNDEFINED> instruction: 0xffd29d08
│ │  	movs	r4, r2
│ │  	svc	169	@ 0xa9
│ │  			@ <UNDEFINED> instruction: 0xffd09cf8
│ │  	movs	r4, r2
│ │ -	str	r2, [sp, #236]	@ 0xec
│ │ +	str	r2, [sp, #392]	@ 0x188
│ │  	vqdmulh.s16	<illegal reg q12.5>, q9, d0[3]
│ │  	movs	r4, r2
│ │  	strh	r2, [r4, #46]	@ 0x2e
│ │  			@ <UNDEFINED> instruction: 0xffd19cd8
│ │  	movs	r4, r2
│ │ -	ldcl	15, cr15, [fp, #-840]!	@ 0xfffffcb8
│ │ +	stc	15, cr15, [r2, #840]!	@ 0x348
│ │  	ldr	r4, [sp, #800]	@ 0x320
│ │  	movs	r4, r2
│ │  	lsrs	r0, r1, #23
│ │  			@ <UNDEFINED> instruction: 0xffd29cb8
│ │  	movs	r4, r2
│ │  	add	r4, sp, #688	@ 0x2b0
│ │  			@ <UNDEFINED> instruction: 0xffd09d28
│ │ @@ -951862,15 +951862,15 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	36ff68 <uniffi_pbcli_checksum_method_api_base@@Base+0x2036e4>
│ │  	ldmia	r4, {r0, r3, r4, r5, r7}
│ │  			@ <UNDEFINED> instruction: 0xebff0007
│ │  	b.n	370372 <uniffi_pbcli_checksum_method_api_base@@Base+0x203aee>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r1, r3, r4, sl, fp}
│ │ -	vsra.u64	q8, q14, #47
│ │ +	vsubl.u16	q8, d1, d19
│ │  	vrsra.u16	<illegal reg q14.5>, q12, #13
│ │  	movs	r6, r2
│ │  	ldr	r0, [pc, #0]	@ (370044 <uniffi_pbcli_checksum_method_api_base@@Base+0x2037c0>)
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	37038a <uniffi_pbcli_checksum_method_api_base@@Base+0x203b06>
│ │  	asrs	r0, r0, #32
│ │  	b.n	36fb70 <uniffi_pbcli_checksum_method_api_base@@Base+0x2032ec>
│ │ @@ -951972,19 +951972,19 @@
│ │  	b.n	370462 <uniffi_pbcli_checksum_method_api_base@@Base+0x203bde>
│ │  	movs	r0, #5
│ │  	b.n	370466 <uniffi_pbcli_checksum_method_api_base@@Base+0x203be2>
│ │  	beq.n	370148 <uniffi_pbcli_checksum_method_api_base@@Base+0x2038c4>
│ │  	b.n	3705c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x203d3c>
│ │  	ldr	r4, [pc, #448]	@ (3702ec <uniffi_pbcli_checksum_method_api_base@@Base+0x203a68>)
│ │  	ldmia.w	sp!, {r1, r3, r4, r5, r6, r7, r9, fp, ip, sp}
│ │ -			@ <UNDEFINED> instruction: 0xea00f3f6
│ │ +			@ <UNDEFINED> instruction: 0xea00f41d
│ │  			@ <UNDEFINED> instruction: 0xffd2c897
│ │ -	vraddhn.i32	d24, <illegal reg q8.5>, q5
│ │ -	vraddhn.i32	d29, q1, <illegal reg q4.5>
│ │ -	vrsra.u64	d31, d10, #46
│ │ +	vsri.64	d24, d17, #47
│ │ +	vsri.16	d29, d16, #14
│ │ +			@ <UNDEFINED> instruction: 0xffd2f3c1
│ │  			@ <UNDEFINED> instruction: 0xffd24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	370668 <uniffi_pbcli_checksum_method_api_base@@Base+0x203de4>
│ │  	beq.n	370168 <uniffi_pbcli_checksum_method_api_base@@Base+0x2038e4>
│ │  	b.n	3705ec <uniffi_pbcli_checksum_method_api_base@@Base+0x203d68>
│ │  	str	r2, [r0, r0]
│ │  	b.n	370496 <uniffi_pbcli_checksum_method_api_base@@Base+0x203c12>
│ │ @@ -952104,19 +952104,19 @@
│ │  	movs	r1, r1
│ │  	b.n	370596 <uniffi_pbcli_checksum_method_api_base@@Base+0x203d12>
│ │  	beq.n	370290 <uniffi_pbcli_checksum_method_api_base@@Base+0x203a0c>
│ │  	b.n	3706f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x203e6c>
│ │  	ldr	r7, [pc, #960]	@ (37061c <uniffi_pbcli_checksum_method_api_base@@Base+0x203d98>)
│ │  	ldmia.w	sp!, {r2, r3, r4, r5, r8, r9, ip, sp}
│ │  			@ <UNDEFINED> instruction: 0xeafcf4e5
│ │ -			@ <UNDEFINED> instruction: 0xffd0f342
│ │ +			@ <UNDEFINED> instruction: 0xffd0f369
│ │  			@ <UNDEFINED> instruction: 0xffd299d8
│ │  	movs	r4, r2
│ │ -	svc	249	@ 0xf9
│ │ -	vrsra.u16	d24, d22, #14
│ │ +	b.n	3702b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x203a2c>
│ │ +	vrsra.u16	q12, <illegal reg q6.5>, #14
│ │  	vqrshrn.u32	d22, <illegal reg q13.5>, #14
│ │  	vaddl.u16	q8, d1, d4
│ │  	b.n	36fdbc <uniffi_pbcli_checksum_method_api_base@@Base+0x203538>
│ │  	movs	r0, r0
│ │  	b.n	3703a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x203b1c>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r3, [sp, #224]	@ 0xe0
│ │ @@ -952514,22 +952514,22 @@
│ │  	movs	r5, r0
│ │  	b.n	37093e <uniffi_pbcli_checksum_method_api_base@@Base+0x2040ba>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0}
│ │  	b.n	370d46 <uniffi_pbcli_checksum_method_api_base@@Base+0x2044c2>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r1, r3, r4, r5, r6, r7, r8, sl, fp, lr}
│ │ -	vqrdmlsh.s16	q15, <illegal reg q8.5>, d2[0]
│ │ -	vshr.u16	q12, q7, #14
│ │ -	vshr.u64	q11, q4, #46
│ │ -	vqrdmlsh.s16	q15, q1, d2[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd27ffe
│ │ +	vqrdmlsh.s16	q15, <illegal reg q8.5>, d1[3]
│ │ +	vaddl.u16	q12, d18, d5
│ │ +	vshr.u64	q11, <illegal reg q15.5>, #46
│ │ +			@ <UNDEFINED> instruction: 0xffd2ef89
│ │ +	vaddl.u16	q12, d2, d21
│ │  	vmull.p<illegal width 16>	<illegal reg q8.5>, d18, d16
│ │ -			@ <UNDEFINED> instruction: 0xffd1ef02
│ │ -			@ <UNDEFINED> instruction: 0xffd27f9a
│ │ +			@ <UNDEFINED> instruction: 0xffd1ef29
│ │ +	vqrdmlsh.s16	<illegal reg q11.5>, q9, d1[0]
│ │  			@ <UNDEFINED> instruction: 0xffd24c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	370b50 <uniffi_pbcli_checksum_method_api_base@@Base+0x2042cc>
│ │  	str	r1, [r0, #0]
│ │  	b.n	37097a <uniffi_pbcli_checksum_method_api_base@@Base+0x2040f6>
│ │  	asrs	r4, r0, #1
│ │  	b.n	37017c <uniffi_pbcli_checksum_method_api_base@@Base+0x2038f8>
│ │ @@ -952561,16 +952561,16 @@
│ │  	b.n	370d16 <uniffi_pbcli_checksum_method_api_base@@Base+0x204492>
│ │  	movs	r1, r0
│ │  	asrs	r0, r0, #12
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {}
│ │  	b.n	370dc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x20453e>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r6, r7, sl, fp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffd3ee5e
│ │ +	ldmia.w	sp!, {r0, r3, r5, r6, r7, sl, fp, lr}
│ │ +	vmull.p<illegal width 16>	q15, d19, d5
│ │  			@ <UNDEFINED> instruction: 0xffd24c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	370bb0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20432c>
│ │  	str	r1, [r0, #0]
│ │  	b.n	3709da <uniffi_pbcli_checksum_method_api_base@@Base+0x204156>
│ │  	asrs	r4, r1, #1
│ │  	b.n	3701dc <uniffi_pbcli_checksum_method_api_base@@Base+0x203958>
│ │ @@ -952606,16 +952606,16 @@
│ │  	b.n	370d80 <uniffi_pbcli_checksum_method_api_base@@Base+0x2044fc>
│ │  	movs	r1, r0
│ │  	stmia	r3!, {}
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {}
│ │  	b.n	370e2a <uniffi_pbcli_checksum_method_api_base@@Base+0x2045a6>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r5, r6, sl, fp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffd3edfe
│ │ +	ldmia.w	sp!, {r0, r3, r7, sl, fp, lr}
│ │ +	vmull.p<illegal width 16>	q15, d3, d21
│ │  	vrshr.u64	d18, d10, #46
│ │  			@ <UNDEFINED> instruction: 0xeafc229b
│ │  			@ <UNDEFINED> instruction: 0xeafc48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	370c20 <uniffi_pbcli_checksum_method_api_base@@Base+0x20439c>
│ │  	str	r0, [r0, r0]
│ │  	b.n	370a4a <uniffi_pbcli_checksum_method_api_base@@Base+0x2041c6>
│ │ @@ -952699,15 +952699,15 @@
│ │  	b.n	370ef2 <uniffi_pbcli_checksum_method_api_base@@Base+0x20466e>
│ │  	ands	r0, r0
│ │  	b.n	370ef6 <uniffi_pbcli_checksum_method_api_base@@Base+0x204672>
│ │  	ldr	r2, [sp, #188]	@ 0xbc
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	370afe <uniffi_pbcli_checksum_method_api_base@@Base+0x20427a>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r6, r9, fp, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r7, r9, fp, ip, sp, lr, pc}
│ │  	vsli.64	d29, d28, #18
│ │  	vqshrun.s32	d20, q8, #15
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	370cec <uniffi_pbcli_checksum_method_api_base@@Base+0x204468>
│ │  	str	r0, [r0, r0]
│ │  	b.n	370b16 <uniffi_pbcli_checksum_method_api_base@@Base+0x204292>
│ │  	movs	r0, r0
│ │ @@ -952776,16 +952776,16 @@
│ │  	b.n	370f04 <uniffi_pbcli_checksum_method_api_base@@Base+0x204680>
│ │  	movs	r1, r0
│ │  	stmia	r3!, {}
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {}
│ │  	b.n	370fae <uniffi_pbcli_checksum_method_api_base@@Base+0x20472a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r5, r6, r7, r9, fp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffd3ec7e
│ │ +	ldmia.w	sp!, {r0, r3, r8, r9, fp, lr}
│ │ +	vmull.u16	q15, d19, d21
│ │  	vrshr.u16	q9, q12, #14
│ │  			@ <UNDEFINED> instruction: 0xeafc0001
│ │  	b.n	370fc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x20473e>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r7, [pc, #960]	@ (370c48 <uniffi_pbcli_checksum_method_api_base@@Base+0x2043c4>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	370da8 <uniffi_pbcli_checksum_method_api_base@@Base+0x204524>
│ │ @@ -952911,19 +952911,19 @@
│ │  	and.w	r0, r0, r0, lsl #24
│ │  	b.n	3710d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x204852>
│ │  	movs	r6, r0
│ │  	b.n	370cda <uniffi_pbcli_checksum_method_api_base@@Base+0x204456>
│ │  	beq.n	3709d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x204150>
│ │  	b.n	370e34 <uniffi_pbcli_checksum_method_api_base@@Base+0x2045b0>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r6, r7, r9, sl, fp, ip, sp}
│ │ -	vmull.u16	q15, d3, d2
│ │ -			@ <UNDEFINED> instruction: 0xffd2eba6
│ │ +	ldmia.w	sp!, {r2, r8, r9, sl, fp, ip, sp}
│ │ +	vmull.u16	q15, d3, d25
│ │ +			@ <UNDEFINED> instruction: 0xffd2ebcd
│ │  			@ <UNDEFINED> instruction: 0xffd218f3
│ │ -	vmlsl.u16	q12, d18, d2[0]
│ │ +	vmlsl.u16	q12, d18, d1[3]
│ │  			@ <UNDEFINED> instruction: 0xffd24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	370ed8 <uniffi_pbcli_checksum_method_api_base@@Base+0x204654>
│ │  	beq.n	3709c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x204144>
│ │  	b.n	370e5c <uniffi_pbcli_checksum_method_api_base@@Base+0x2045d8>
│ │  	ands	r0, r0
│ │  	b.n	371106 <uniffi_pbcli_checksum_method_api_base@@Base+0x204882>
│ │ @@ -955987,71 +955987,71 @@
│ │  	movs	r0, #0
│ │  	b.n	372b4a <uniffi_pbcli_checksum_method_api_base@@Base+0x2062c6>
│ │  	str	r3, [sp, #104]	@ 0x68
│ │  			@ <UNDEFINED> instruction: 0xebfdff46
│ │  			@ <UNDEFINED> instruction: 0xeafffb14
│ │  	vqshlu.s32	d23, d11, #31
│ │  			@ <UNDEFINED> instruction: 0xffd01da8
│ │ -			@ <UNDEFINED> instruction: 0xffd829d5
│ │ +			@ <UNDEFINED> instruction: 0xffd829fc
│ │  	vqshlu.s16	<illegal reg q12.5>, <illegal reg q10.5>, #3
│ │  			@ <UNDEFINED> instruction: 0xffd11d9c
│ │ -	vmul.i16	q10, q12, d4[3]
│ │ +	vqshrn.u32	d20, <illegal reg q1.5>, #8
│ │  			@ <UNDEFINED> instruction: 0xffd21d54
│ │  	vshr.u16	d28, d17, #8
│ │  	vqrdmulh.s16	<illegal reg q8.5>, q8, d4[1]
│ │ -	vsli.64	d18, d5, #24
│ │ +	vsli.64	d18, d28, #24
│ │  			@ <UNDEFINED> instruction: 0xffd3bb7c
│ │  			@ <UNDEFINED> instruction: 0xffd093e3
│ │ -	vqshlu.s16	d18, d9, #1
│ │ +	vmlsl.u16	q9, d1, d0[0]
│ │  	vmull.u16	<illegal reg q13.5>, d3, d0
│ │  	vsri.16	<illegal reg q14.5>, <illegal reg q7.5>, #16
│ │ -			@ <UNDEFINED> instruction: 0xffd02db3
│ │ +			@ <UNDEFINED> instruction: 0xffd02dda
│ │  	vrsra.u64	d25, d23, #46
│ │ -	vqshrn.u32	d18, <illegal reg q10.5>, #15
│ │ +	vqrshrn.u32	d18, q6, #15
│ │  			@ <UNDEFINED> instruction: 0xffd37cd1
│ │ -	vqshlu.s64	d18, d13, #17
│ │ +	vmlsl.u16	q9, d17, d4[0]
│ │  	vmull.u16	<illegal reg q13.5>, d19, d4
│ │  	vmls.i16	<illegal reg q14.5>, q8, d7[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd02e3b
│ │ +	vqrdmlah.s16	q9, q0, d2[2]
│ │  			@ <UNDEFINED> instruction: 0xffd29343
│ │ -	vsli.64	d18, d29, #17
│ │ +	vmls.f16	q9, <illegal reg q8.5>, d4[2]
│ │  			@ <UNDEFINED> instruction: 0xffd3bba4
│ │ -	vsli.16	q9, <illegal reg q6.5>, #0
│ │ +	vabal.u16	q9, d16, d4
│ │  			@ <UNDEFINED> instruction: 0xffd3bb44
│ │  	vsubw.u16	<illegal reg q11.5>, q0, d3
│ │ -	vsri.16	q9, <illegal reg q10.5>, #16
│ │ +	vsri.64	d18, d12, #48
│ │  			@ <UNDEFINED> instruction: 0xffd3ba5c
│ │  	vrshr.u16	d25, d11, #16
│ │ -	vmls.f16	q9, <illegal reg q0.5>, d1[0]
│ │ +	vmls.f16	q9, <illegal reg q0.5>, d0[3]
│ │  			@ <UNDEFINED> instruction: 0xffd3bb28
│ │  	vsubw.u16	<illegal reg q14.5>, q8, d15
│ │ -			@ <UNDEFINED> instruction: 0xffd02cdb
│ │ -	vsri.16	q9, <illegal reg q4.5>, #14
│ │ +			@ <UNDEFINED> instruction: 0xffd02d02
│ │ +	vraddhn.i32	d18, q9, q0
│ │  	vmull.u16	<illegal reg q13.5>, d3, d0[0]
│ │  	vsubl.u16	<illegal reg q14.5>, d16, d23
│ │ -			@ <UNDEFINED> instruction: 0xffd02bf3
│ │ -	vrsra.u64	q9, <illegal reg q12.5>, #46
│ │ +			@ <UNDEFINED> instruction: 0xffd02c1a
│ │ +	vraddhn.i32	d18, q1, q8
│ │  	vmul.f16	<illegal reg q13.5>, <illegal reg q9.5>, d0[2]
│ │  	vsra.u64	<illegal reg q11.5>, <illegal reg q15.5>, #48
│ │ -	vrsra.u64	d18, d13, #48
│ │ +			@ <UNDEFINED> instruction: 0xffd023c4
│ │  			@ <UNDEFINED> instruction: 0xffd3b984
│ │  	vabal.u16	<illegal reg q11.5>, d16, d19
│ │ -	vraddhn.i32	d18, q8, <illegal reg q14.5>
│ │ +	vsri.64	q9, q2, #48
│ │  			@ <UNDEFINED> instruction: 0xffd3ba94
│ │ -	vsri.64	d18, d1, #48
│ │ +	vsri.64	d18, d24, #48
│ │  			@ <UNDEFINED> instruction: 0xffd3ba78
│ │  	vmlal.u16	<illegal reg q14.5>, d0, d7[0]
│ │ -			@ <UNDEFINED> instruction: 0xffd02b93
│ │ -	vmlsl.u16	q9, d18, d29
│ │ -	vqshlu.s16	q9, <illegal reg q0.5>, #3
│ │ +			@ <UNDEFINED> instruction: 0xffd02bba
│ │ +			@ <UNDEFINED> instruction: 0xffd22ad4
│ │ +	vqshlu.s16	q9, q12, #3
│ │  	vsubw.u16	<illegal reg q13.5>, <illegal reg q9.5>, d24
│ │  	movs	r6, r2
│ │ -	cmp	r3, #25
│ │ +	cmp	r3, #64	@ 0x40
│ │  	vaddw.u16	q14, <illegal reg q1.5>, d0
│ │ -	vmls.i16	q9, q8, d5[2]
│ │ +	vabal.u16	q9, d0, d12
│ │  	vmull.u16	<illegal reg q13.5>, d19, d4[1]
│ │  			@ <UNDEFINED> instruction: 0xffd0df95
│ │  			@ <UNDEFINED> instruction: 0xffd04ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	372a28 <uniffi_pbcli_checksum_method_api_base@@Base+0x2061a4>
│ │  	beq.n	372538 <uniffi_pbcli_checksum_method_api_base@@Base+0x205cb4>
│ │  	b.n	3729ac <uniffi_pbcli_checksum_method_api_base@@Base+0x206128>
│ │ @@ -956581,35 +956581,35 @@
│ │  	b.n	3730ba <uniffi_pbcli_checksum_method_api_base@@Base+0x206836>
│ │  	movs	r5, r0
│ │  	b.n	372cbe <uniffi_pbcli_checksum_method_api_base@@Base+0x20643a>
│ │  	beq.n	3729b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x206134>
│ │  	b.n	372e18 <uniffi_pbcli_checksum_method_api_base@@Base+0x206594>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r5, r9, sl, sp, lr, pc}
│ │ -	vqrdmlah.s16	q14, <illegal reg q8.5>, d2[1]
│ │ -	vqshlu.s64	d18, d31, #18
│ │ -			@ <UNDEFINED> instruction: 0xffd2cb46
│ │ +			@ <UNDEFINED> instruction: 0xffd1cef1
│ │ +	vmlsl.u16	q9, d18, d6[2]
│ │ +			@ <UNDEFINED> instruction: 0xffd2cb6d
│ │  			@ <UNDEFINED> instruction: 0xffd28d9a
│ │ -	vmull.p<illegal width 16>	q14, d17, d18
│ │ +	vqrdmlah.s16	q14, <illegal reg q8.5>, d1[1]
│ │  			@ <UNDEFINED> instruction: 0xffd2fcf6
│ │ -	vrsubhn.i32	d25, q8, q4
│ │ +	vrsubhn.i32	d25, q8, <illegal reg q15.5>
│ │  	vmls.i16	<illegal reg q8.5>, q1, d2[1]
│ │  			@ <UNDEFINED> instruction: 0xffd18365
│ │  			@ <UNDEFINED> instruction: 0xffd0836a
│ │  	vqshl.u16	d19, d29, #0
│ │  	vsli.64	d27, d31, #19
│ │  	vmls.i16	q15, q0, d1[3]
│ │  	vsri.16	q10, q2, #16
│ │  	vsra.u16	q13, <illegal reg q6.5>, #15
│ │ -	vmls.f16	<illegal reg q12.5>, <illegal reg q8.5>, d7[0]
│ │ -	vmlsl.u16	q9, d18, d10
│ │ -	vmull.u16	q14, d3, d22
│ │ -			@ <UNDEFINED> instruction: 0xffd27db1
│ │ +	vmls.f16	<illegal reg q12.5>, <illegal reg q8.5>, d6[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd22ab1
│ │ +	vqdmulh.s16	q14, <illegal reg q1.5>, d5[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd27dd8
│ │  	vqshlu.s64	q8, <illegal reg q9.5>, #18
│ │ -			@ <UNDEFINED> instruction: 0xffd15c32
│ │ +			@ <UNDEFINED> instruction: 0xffd15c59
│ │  			@ <UNDEFINED> instruction: 0xffd24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	372f00 <uniffi_pbcli_checksum_method_api_base@@Base+0x20667c>
│ │  	beq.n	372a70 <uniffi_pbcli_checksum_method_api_base@@Base+0x2061ec>
│ │  	b.n	372e84 <uniffi_pbcli_checksum_method_api_base@@Base+0x206600>
│ │  	movs	r0, r0
│ │  	b.n	373090 <uniffi_pbcli_checksum_method_api_base@@Base+0x20680c>
│ │ @@ -957371,15 +957371,15 @@
│ │  	str	r0, [sp, #16]
│ │  	b.n	372bb8 <uniffi_pbcli_checksum_method_api_base@@Base+0x206334>
│ │  			@ <UNDEFINED> instruction: 0xffcaeaff
│ │  	add	r0, pc, #0	@ (adr r0, 373084 <uniffi_pbcli_checksum_method_api_base@@Base+0x206800>)
│ │  	b.n	3737c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x206f42>
│ │  			@ <UNDEFINED> instruction: 0xfff4eaff
│ │  			@ <UNDEFINED> instruction: 0xeb28ffff
│ │ -	subs	r1, r6, r3
│ │ +	subs	r0, r3, r4
│ │  	vmls.f16	q11, <illegal reg q9.5>, d4[2]
│ │  	vmul.f16	q15, q8, d0[2]
│ │  	vaddl.u<illegal width 64>	<illegal reg q8.5>, d15, d0
│ │  	b.n	372bc0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20633c>
│ │  	movs	r0, #4
│ │  	b.n	3737e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x206f5e>
│ │  	movs	r0, r0
│ │ @@ -958220,37 +958220,37 @@
│ │  	b.n	3738a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x207024>
│ │  	movs	r5, #241	@ 0xf1
│ │  			@ <UNDEFINED> instruction: 0xebfc0001
│ │  	b.n	373ed2 <uniffi_pbcli_checksum_method_api_base@@Base+0x20764e>
│ │  	beq.n	3737cc <uniffi_pbcli_checksum_method_api_base@@Base+0x206f48>
│ │  	b.n	373c2c <uniffi_pbcli_checksum_method_api_base@@Base+0x2073a8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r4, r5, r6, fp}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r4, r7, fp}
│ │  	vqshl.u16	q8, <illegal reg q2.5>, #3
│ │ -	vaddl.u16	q14, d18, d30
│ │ -			@ <UNDEFINED> instruction: 0xffd289aa
│ │ +	vshr.u64	q14, <illegal reg q2.5>, #46
│ │ +			@ <UNDEFINED> instruction: 0xffd289d1
│ │  	vmull.u16	<illegal reg q10.5>, d18, d24
│ │  	vrsra.u16	d25, d28, #16
│ │ -	vrsubhn.i32	d16, <illegal reg q0.5>, q12
│ │ +	vmlsl.u16	q8, d1, d7[1]
│ │  	vrsra.u16	d25, d0, #13
│ │ -	vsli.64	q8, q14, #17
│ │ +	vrsubhn.i32	d16, <illegal reg q0.5>, <illegal reg q9.5>
│ │  	vmlal.u16	<illegal reg q12.5>, d19, d4[2]
│ │ -	vsli.64	q8, q0, #17
│ │ +	vsli.64	q8, <illegal reg q11.5>, #17
│ │  	vrshr.u64	d25, d24, #45
│ │ -	vabal.u16	q8, d17, d20
│ │ +	vmls.f16	q8, <illegal reg q8.5>, d3[1]
│ │  	vsubl.u16	<illegal reg q12.5>, d19, d12
│ │ -	vsli.16	q8, q12, #1
│ │ +	vsli.64	d16, d15, #17
│ │  	vmlal.u16	<illegal reg q12.5>, d3, d0[2]
│ │ -	vmls.f16	q8, <illegal reg q0.5>, d4[1]
│ │ +	vsli.16	q8, <illegal reg q9.5>, #1
│ │  	vrshr.u16	d25, d20, #13
│ │ -	vabal.u16	q8, d1, d16
│ │ +	vmls.f16	q8, <illegal reg q0.5>, d7[0]
│ │  	vsubl.u16	<illegal reg q12.5>, d3, d8
│ │ -			@ <UNDEFINED> instruction: 0xffd1bd3a
│ │ -	vmls.i16	q8, q9, d0[2]
│ │ -	vabdl.u16	q8, d3, d16
│ │ +	vqrdmulh.s16	<illegal reg q13.5>, <illegal reg q0.5>, d1[2]
│ │ +	vabal.u16	q8, d2, d7
│ │ +			@ <UNDEFINED> instruction: 0xffd30747
│ │  	vaddl.u16	q8, d3, d4
│ │  	b.n	373338 <uniffi_pbcli_checksum_method_api_base@@Base+0x206ab4>
│ │  	movs	r0, r0
│ │  	b.n	37391c <uniffi_pbcli_checksum_method_api_base@@Base+0x207098>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r4, [r3, #20]
│ │  	movs	r4, r2
│ │ @@ -958833,15 +958833,15 @@
│ │  	b.n	374046 <uniffi_pbcli_checksum_method_api_base@@Base+0x2077c2>
│ │  	ldr	r6, [pc, #396]	@ (373e94 <uniffi_pbcli_checksum_method_api_base@@Base+0x207610>)
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	373848 <uniffi_pbcli_checksum_method_api_base@@Base+0x206fc4>
│ │  	beq.n	373d48 <uniffi_pbcli_checksum_method_api_base@@Base+0x2074c4>
│ │  	b.n	3741a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x207924>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r6, r7, r9, fp}
│ │ +	ldmia.w	sp!, {r1, r2, r4, r5, r6, r7, r9, fp}
│ │  	vmull.u16	q12, d19, d25
│ │  			@ <UNDEFINED> instruction: 0xffd14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	374240 <uniffi_pbcli_checksum_method_api_base@@Base+0x2079bc>
│ │  	beq.n	373d50 <uniffi_pbcli_checksum_method_api_base@@Base+0x2074cc>
│ │  	b.n	3741c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x207940>
│ │  	movs	r0, r0
│ │ @@ -959299,23 +959299,23 @@
│ │  	ldr	r5, [pc, #372]	@ (374294 <uniffi_pbcli_checksum_method_api_base@@Base+0x207a10>)
│ │  			@ <UNDEFINED> instruction: 0xebfcff06
│ │  			@ <UNDEFINED> instruction: 0xeaff9010
│ │  	b.n	373c64 <uniffi_pbcli_checksum_method_api_base@@Base+0x2073e0>
│ │  	ands	r0, r0
│ │  	b.n	37486e <uniffi_pbcli_checksum_method_api_base@@Base+0x207fea>
│ │  			@ <UNDEFINED> instruction: 0xfff7eaff
│ │ -	lsrs	r3, r7, #7
│ │ -	vmull.p<illegal width 16>	<illegal reg q9.5>, d3, d28
│ │ -	vabdl.u16	q8, d2, d27
│ │ -			@ <UNDEFINED> instruction: 0xffd33b5c
│ │ -	vqshlu.s64	d16, d19, #18
│ │ -	vmull.u16	<illegal reg q9.5>, d19, d4[2]
│ │ -	vmlsl.u16	q8, d18, d7[3]
│ │ -			@ <UNDEFINED> instruction: 0xffd33b20
│ │ -	vqshrun.s32	d16, <illegal reg q11.5>, #14
│ │ +	lsrs	r2, r4, #8
│ │ +			@ <UNDEFINED> instruction: 0xffd33e53
│ │ +	vqshl.u16	q8, q1, #2
│ │ +			@ <UNDEFINED> instruction: 0xffd33b83
│ │ +	vqshlu.s64	q8, q5, #18
│ │ +			@ <UNDEFINED> instruction: 0xffd33b0b
│ │ +	vqshl.u16	d16, d6, #2
│ │ +			@ <UNDEFINED> instruction: 0xffd33b47
│ │ +	vqrshrun.s32	d16, q7, #14
│ │  	vsra.u64	d22, d0, #45
│ │  	movs	r4, r2
│ │  	ldr	r7, [pc, #960]	@ (37451c <uniffi_pbcli_checksum_method_api_base@@Base+0x207c98>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	37467c <uniffi_pbcli_checksum_method_api_base@@Base+0x207df8>
│ │  	beq.n	37418c <uniffi_pbcli_checksum_method_api_base@@Base+0x207908>
│ │  	b.n	374600 <uniffi_pbcli_checksum_method_api_base@@Base+0x207d7c>
│ │ @@ -959896,50 +959896,50 @@
│ │  	b.n	3749ae <uniffi_pbcli_checksum_method_api_base@@Base+0x20812a>
│ │  	beq.n	3746a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x207e24>
│ │  	b.n	374b08 <uniffi_pbcli_checksum_method_api_base@@Base+0x208284>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r2, r4, r5, sp, lr}
│ │  	movs	r4, r2
│ │  	b.n	374b86 <uniffi_pbcli_checksum_method_api_base@@Base+0x208302>
│ │ -	vsubw.u16	<illegal reg q12.5>, q0, d18
│ │ -	vsubw.u16	q8, q1, d27
│ │ -	vshr.u64	d25, d28, #45
│ │ +			@ <UNDEFINED> instruction: 0xffd09349
│ │ +	vrsra.u16	q8, q1, #14
│ │ +	vmla.i16	<illegal reg q12.5>, <illegal reg q9.5>, d3[2]
│ │  	vqrdmlsh.s16	q13, q9, d7[1]
│ │ -			@ <UNDEFINED> instruction: 0xffd00923
│ │ -	vrsra.u16	q8, <illegal reg q3.5>, #14
│ │ -	vmla.i16	<illegal reg q12.5>, <illegal reg q9.5>, d0[3]
│ │ +	vmul.f16	q8, q0, d2[1]
│ │ +	vrsra.u16	q8, q15, #14
│ │ +	vaddw.u16	<illegal reg q12.5>, <illegal reg q1.5>, d15
│ │  			@ <UNDEFINED> instruction: 0xffd25905
│ │  			@ <UNDEFINED> instruction: 0xffd15df0
│ │  	movs	r4, r2
│ │  	ldrh	r4, [r5, r6]
│ │  	movs	r4, r2
│ │ -	lsls	r7, r3, #6
│ │ -			@ <UNDEFINED> instruction: 0xffd38f30
│ │ +	lsls	r6, r0, #7
│ │ +			@ <UNDEFINED> instruction: 0xffd38f57
│ │  			@ <UNDEFINED> instruction: 0xffd2bfbe
│ │  	vqrdmlsh.s16	q11, q0, d7[3]
│ │ -	vrshr.u64	q8, <illegal reg q5.5>, #47
│ │ -	vmla.i16	<illegal reg q12.5>, <illegal reg q1.5>, d4[3]
│ │ +	vsubw.u16	q8, <illegal reg q0.5>, d2
│ │ +	vshr.u64	d25, d3, #45
│ │  	vqrdmlsh.s16	<illegal reg q13.5>, q1, d6[2]
│ │ -	vsubl.u16	q8, d16, d31
│ │ -	vmla.i16	<illegal reg q12.5>, <illegal reg q1.5>, d0[0]
│ │ +	vrshr.u64	q8, q3, #48
│ │ +	vmla.i16	<illegal reg q12.5>, <illegal reg q1.5>, d7[2]
│ │  	vshr.u64	<illegal reg q13.5>, <illegal reg q7.5>, #46
│ │ -	vmovl.u16	q8, d19
│ │ +			@ <UNDEFINED> instruction: 0xffd00a5a
│ │  			@ <UNDEFINED> instruction: 0xffd25b5c
│ │  	movs	r4, r2
│ │ -	lsls	r7, r5, #7
│ │ -			@ <UNDEFINED> instruction: 0xffd38f80
│ │ -	vsri.64	d16, d31, #46
│ │ -	vmlal.u16	q8, d3, d7[1]
│ │ -	vqrdmlsh.s16	q12, <illegal reg q9.5>, d0[2]
│ │ -	vrshr.u64	q8, <illegal reg q15.5>, #46
│ │ -	vshr.u64	d25, d0, #45
│ │ -	vrsra.u64	d16, d27, #46
│ │ -	vmla.f16	<illegal reg q12.5>, <illegal reg q1.5>, d4[1]
│ │ -	vsubl.u16	q8, d2, d19
│ │ -			@ <UNDEFINED> instruction: 0xffd38fb4
│ │ +	lsls	r6, r2, #8
│ │ +			@ <UNDEFINED> instruction: 0xffd38fa7
│ │ +	vmls.i16	q8, q9, d6[2]
│ │ +	vrshr.u16	q8, q11, #13
│ │ +	vaddl.u16	<illegal reg q12.5>, d3, d7
│ │ +	vsubw.u16	q8, q1, d22
│ │ +	vshr.u64	d25, d23, #45
│ │ +			@ <UNDEFINED> instruction: 0xffd203e2
│ │ +	vsra.u16	<illegal reg q12.5>, <illegal reg q9.5>, #13
│ │ +	vmlal.u16	q8, d2, d2[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd38fdb
│ │  			@ <UNDEFINED> instruction: 0xffd24c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	374c24 <uniffi_pbcli_checksum_method_api_base@@Base+0x2083a0>
│ │  	ands	r3, r0
│ │  	b.n	374a4e <uniffi_pbcli_checksum_method_api_base@@Base+0x2081ca>
│ │  	adds	r0, #76	@ 0x4c
│ │  	b.n	374250 <uniffi_pbcli_checksum_method_api_base@@Base+0x2079cc>
│ │ @@ -959975,15 +959975,15 @@
│ │  	b.n	374df2 <uniffi_pbcli_checksum_method_api_base@@Base+0x20856e>
│ │  	movs	r1, r0
│ │  	asrs	r0, r0, #12
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {}
│ │  	b.n	374e9e <uniffi_pbcli_checksum_method_api_base@@Base+0x20861a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r2, r8, r9, fp, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r5, r8, r9, fp, ip, sp, pc}
│ │  	vsri.64	d18, d15, #46
│ │  			@ <UNDEFINED> instruction: 0xffd14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	374c8c <uniffi_pbcli_checksum_method_api_base@@Base+0x208408>
│ │  	beq.n	37477c <uniffi_pbcli_checksum_method_api_base@@Base+0x207ef8>
│ │  	b.n	374c10 <uniffi_pbcli_checksum_method_api_base@@Base+0x20838c>
│ │  	movs	r0, r0
│ │ @@ -961059,25 +961059,25 @@
│ │  	beq.n	3750b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20882c>
│ │  	b.n	375510 <uniffi_pbcli_checksum_method_api_base@@Base+0x208c8c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {sp, pc}
│ │  	b.n	3757c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x208f3e>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │  	ldr	r1, [r4, #4]
│ │ -	vmls.f16	q13, q8, d6[0]
│ │ +	vmls.f16	q13, q8, d5[3]
│ │  			@ <UNDEFINED> instruction: 0xffd20364
│ │ -	vsli.16	d26, d2, #1
│ │ -	vqshl.u64	<illegal reg q15.5>, <illegal reg q9.5>, #18
│ │ -			@ <UNDEFINED> instruction: 0xffd29bba
│ │ -	vsri.64	d26, d30, #46
│ │ -	vqshl.u64	d31, d15, #18
│ │ -	vabdl.u16	<illegal reg q15.5>, d18, d13
│ │ -	vqshl.u16	<illegal reg q15.5>, <illegal reg q3.5>, #2
│ │ -	vqshl.u16	<illegal reg q15.5>, <illegal reg q2.5>, #2
│ │ -	vmls.i16	q13, q1, d6[0]
│ │ +	vsli.16	d26, d25, #1
│ │ +	vqshrun.s32	d31, q5, #14
│ │ +			@ <UNDEFINED> instruction: 0xffd29be1
│ │ +	vmls.i16	q13, q9, d5[2]
│ │ +			@ <UNDEFINED> instruction: 0xffd2f7c6
│ │ +	vqshl.u64	d31, d20, #18
│ │ +	vqshl.u16	<illegal reg q15.5>, q15, #2
│ │ +	vqshl.u16	<illegal reg q15.5>, q14, #2
│ │ +	vmls.i16	q13, q1, d5[3]
│ │  	vaddl.u16	q8, d2, d4
│ │  	b.n	374bf8 <uniffi_pbcli_checksum_method_api_base@@Base+0x208374>
│ │  	movs	r0, r0
│ │  	b.n	3751dc <uniffi_pbcli_checksum_method_api_base@@Base+0x208958>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	str	r4, [r4, r7]
│ │  	movs	r4, r2
│ │ @@ -961651,42 +961651,42 @@
│ │  	vrhadd.u<illegal width 64>	d14, d6, d31
│ │  			@ <UNDEFINED> instruction: 0xfff4eaff
│ │  	movs	r1, r0
│ │  	b.n	375cf2 <uniffi_pbcli_checksum_method_api_base@@Base+0x20946e>
│ │  	beq.n	3755ec <uniffi_pbcli_checksum_method_api_base@@Base+0x208d68>
│ │  	b.n	375a4c <uniffi_pbcli_checksum_method_api_base@@Base+0x2091c8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r3, r5, r6, r8, r9, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r4, r7, r8, r9, sp, pc}
│ │  	vrshr.u64	q13, <illegal reg q6.5>, #46
│ │  	vqrshrn.u32	d20, <illegal reg q4.5>, #15
│ │ -	vsubw.u16	q12, <illegal reg q0.5>, d14
│ │ -	vqrdmlah.s16	<illegal reg q9.5>, q1, d2[3]
│ │ +	vrsra.u16	d24, d21, #15
│ │ +			@ <UNDEFINED> instruction: 0xffd23e91
│ │  	vshll.u16	<illegal reg q13.5>, d7, #2
│ │ -	vshr.u64	d16, d6, #48
│ │ -			@ <UNDEFINED> instruction: 0xffd33da0
│ │ +	vshr.u64	d16, d29, #48
│ │ +	vqrdmulh.s16	<illegal reg q9.5>, <illegal reg q9.5>, d7[0]
│ │  	vmla.f16	<illegal reg q9.5>, q1, d5[1]
│ │ -	vsubl.u16	<illegal reg q9.5>, d17, d18
│ │ +	vmlal.u16	<illegal reg q9.5>, d17, d1[1]
│ │  	vaddl.u16	<illegal reg q11.5>, d18, d11
│ │ -	vmlal.u16	<illegal reg q9.5>, d0, d6[2]
│ │ +	vsubl.u16	<illegal reg q9.5>, d16, d13
│ │  	vqrdmlah.s16	q14, q9, d0[3]
│ │ -	vrshr.u16	d19, d10, #15
│ │ -	vmla.f16	q12, q9, d2[1]
│ │ -	vsra.u64	<illegal reg q9.5>, q5, #46
│ │ -	vshll.u16	q11, d19, #2
│ │ -	vmull.u16	<illegal reg q15.5>, d18, d7[0]
│ │ +	vmlal.u16	<illegal reg q9.5>, d1, d1[0]
│ │ +	vsra.u64	q12, <illegal reg q8.5>, #46
│ │ +	vsubl.u16	<illegal reg q9.5>, d2, d1
│ │ +			@ <UNDEFINED> instruction: 0xffd26a5a
│ │ +	vmull.u16	<illegal reg q15.5>, d18, d6[3]
│ │  			@ <UNDEFINED> instruction: 0xffd1fdbd
│ │  	vaddl.u16	<illegal reg q10.5>, d16, d12
│ │  	movs	r4, r2
│ │  	ldr	r2, [r3, #116]	@ 0x74
│ │ -	vaddw.u16	<illegal reg q9.5>, q0, d14
│ │ +	vsra.u16	d19, d21, #16
│ │  			@ <UNDEFINED> instruction: 0xffd23e1c
│ │ -	vmla.i16	<illegal reg q9.5>, q8, d6[0]
│ │ -			@ <UNDEFINED> instruction: 0xffd2ad96
│ │ -	vmla.i16	<illegal reg q9.5>, q1, d2[1]
│ │ -	vsubw.u16	<illegal reg q9.5>, q9, d18
│ │ +	vmla.i16	<illegal reg q9.5>, q8, d5[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd2adbd
│ │ +	vshr.u16	<illegal reg q9.5>, <illegal reg q8.5>, #14
│ │ +			@ <UNDEFINED> instruction: 0xffd233c9
│ │  	vaddl.u16	q8, d2, d4
│ │  	b.n	375168 <uniffi_pbcli_checksum_method_api_base@@Base+0x2088e4>
│ │  	movs	r0, r0
│ │  	b.n	37574c <uniffi_pbcli_checksum_method_api_base@@Base+0x208ec8>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r5, [pc, #240]	@ (375724 <uniffi_pbcli_checksum_method_api_base@@Base+0x208ea0>)
│ │  	movs	r4, r2
│ │ @@ -961782,28 +961782,28 @@
│ │  	b.n	375a46 <uniffi_pbcli_checksum_method_api_base@@Base+0x2091c2>
│ │  	lsls	r4, r0, #4
│ │  	add.w	r0, r0, r1
│ │  	b.n	375e4e <uniffi_pbcli_checksum_method_api_base@@Base+0x2095ca>
│ │  	beq.n	375726 <uniffi_pbcli_checksum_method_api_base@@Base+0x208ea2>
│ │  	b.n	375a52 <uniffi_pbcli_checksum_method_api_base@@Base+0x2091ce>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r7, r9, sl, fp, sp}
│ │ +	ldmia.w	sp!, {r0, r3, r5, r7, r9, sl, fp, sp}
│ │  	vshr.u16	d16, d0, #14
│ │  	b.n	37525c <uniffi_pbcli_checksum_method_api_base@@Base+0x2089d8>
│ │  	movs	r0, #18
│ │  	b.n	375e62 <uniffi_pbcli_checksum_method_api_base@@Base+0x2095de>
│ │  	asrs	r4, r1, #32
│ │  	b.n	375264 <uniffi_pbcli_checksum_method_api_base@@Base+0x2089e0>
│ │  	movs	r0, r0
│ │  	b.n	375848 <uniffi_pbcli_checksum_method_api_base@@Base+0x208fc4>
│ │  	asrs	r1, r0, #32
│ │  	b.n	37584c <uniffi_pbcli_checksum_method_api_base@@Base+0x208fc8>
│ │  	add	r4, pc, #232	@ (adr r4, 375818 <uniffi_pbcli_checksum_method_api_base@@Base+0x208f94>)
│ │  			@ <UNDEFINED> instruction: 0xeafeec46
│ │ -			@ <UNDEFINED> instruction: 0xffd00f0a
│ │ +			@ <UNDEFINED> instruction: 0xffd00f31
│ │  	vqrdmlah.s16	q8, q9, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xeafc4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	375c60 <uniffi_pbcli_checksum_method_api_base@@Base+0x2093dc>
│ │  	str	r0, [r0, r0]
│ │  	b.n	375a8a <uniffi_pbcli_checksum_method_api_base@@Base+0x209206>
│ │  	ldrh	r7, [r4, #18]
│ │ @@ -962205,35 +962205,35 @@
│ │  	b.n	375dfa <uniffi_pbcli_checksum_method_api_base@@Base+0x209576>
│ │  	movs	r0, #16
│ │  	b.n	3761fe <uniffi_pbcli_checksum_method_api_base@@Base+0x20997a>
│ │  	adds	r1, r0, r5
│ │  			@ <UNDEFINED> instruction: 0xebfcd01c
│ │  	b.n	375f5c <uniffi_pbcli_checksum_method_api_base@@Base+0x2096d8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r7, r8, r9, sl, fp, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd29c9a
│ │ -			@ <UNDEFINED> instruction: 0xffd2efba
│ │ +	ldmia.w	sp!, {r5, r6, r7, r8, r9, sl, fp, sp, lr, pc}
│ │ +	vqdmulh.s16	<illegal reg q12.5>, q9, d1[0]
│ │ +	vqrdmlsh.s16	q15, q9, d1[2]
│ │  			@ <UNDEFINED> instruction: 0xffd22bbf
│ │ -	vqdmulh.s16	<illegal reg q12.5>, <illegal reg q0.5>, d6[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd19c75
│ │  	vsubl.u16	<illegal reg q10.5>, d18, d22
│ │ -	vqrshrun.s32	d29, q12, #16
│ │ -	vmull.u16	<illegal reg q12.5>, d2, d2
│ │ +			@ <UNDEFINED> instruction: 0xffd0d89f
│ │ +	vmull.u16	<illegal reg q12.5>, d2, d25
│ │  			@ <UNDEFINED> instruction: 0xffd29b9a
│ │ -			@ <UNDEFINED> instruction: 0xffd19be2
│ │ -	vsubw.u16	q9, q1, d6
│ │ +	vmull.u16	<illegal reg q12.5>, d1, d9
│ │ +	vsubw.u16	q9, q1, d29
│ │  	vmlal.u16	<illegal reg q13.5>, d18, d4[2]
│ │  	vmul.f16	<illegal reg q10.5>, q8, d4[1]
│ │ -	vmull.u16	<illegal reg q12.5>, d17, d2[0]
│ │ +	vmull.u16	<illegal reg q12.5>, d17, d1[3]
│ │  			@ <UNDEFINED> instruction: 0xffd2be5f
│ │ -	vqshlu.s64	<illegal reg q14.5>, <illegal reg q9.5>, #16
│ │ -	vmull.u16	<illegal reg q12.5>, d2, d6[3]
│ │ +	vqshl.u16	d29, d10, #0
│ │ +			@ <UNDEFINED> instruction: 0xffd29a95
│ │  	vsubw.u16	q12, q1, d3
│ │  	vqshl.u64	q13, <illegal reg q8.5>, #17
│ │  			@ <UNDEFINED> instruction: 0xffd02987
│ │ -	vmlsl.u16	<illegal reg q12.5>, d1, d14
│ │ +	vshll.u16	<illegal reg q12.5>, d21, #1
│ │  			@ <UNDEFINED> instruction: 0xffd24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	376040 <uniffi_pbcli_checksum_method_api_base@@Base+0x2097bc>
│ │  	beq.n	375b30 <uniffi_pbcli_checksum_method_api_base@@Base+0x2092ac>
│ │  	b.n	375fc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x209740>
│ │  	strh	r3, [r0, #0]
│ │  	b.n	375e6e <uniffi_pbcli_checksum_method_api_base@@Base+0x2095ea>
│ │ @@ -962512,17 +962512,17 @@
│ │  	ands	r0, r1
│ │  	b.n	376426 <uniffi_pbcli_checksum_method_api_base@@Base+0x209ba2>
│ │  	lsrs	r1, r7
│ │  	b.n	3762b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x209a2e>
│ │  			@ <UNDEFINED> instruction: 0xffd7eaff
│ │  	ldr	r1, [pc, #528]	@ (375fc0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20973c>)
│ │  	movs	r4, r2
│ │ -	lsrs	r0, r2, #8
│ │ +	lsrs	r7, r6, #8
│ │  	vmlsl.u16	<illegal reg q9.5>, d2, d1[2]
│ │ -	vrsubhn.i32	d26, q0, q4
│ │ +	vrsubhn.i32	d26, q0, <illegal reg q15.5>
│ │  	vabal.u16	q14, d18, d24
│ │  	vsli.16	d28, d11, #1
│ │  	vaddl.u16	q12, d17, d25
│ │  	vqshrun.s32	d20, q4, #16
│ │  	movs	r4, r2
│ │  	stmia	r4!, {r0, r1, r2, r4, r6, r7}
│ │  	vmla.i16	q12, <illegal reg q0.5>, d5[2]
│ │ @@ -962732,24 +962732,24 @@
│ │  	movs	r0, r0
│ │  	b.n	376636 <uniffi_pbcli_checksum_method_api_base@@Base+0x209db2>
│ │  			@ <UNDEFINED> instruction: 0xffea1aff
│ │  			@ <UNDEFINED> instruction: 0xfff5eaff
│ │  	stmia	r3!, {r0, r1, r4, r6, r7}
│ │  	vqshlu.s16	d28, d23, #1
│ │  	vaddw.u16	q8, q0, d11
│ │ -	vqshlu.s64	d25, d10, #19
│ │ -	vabdl.u16	q9, d2, d30
│ │ -	vaddw.u16	<illegal reg q15.5>, q9, d15
│ │ -	vsli.64	<illegal reg q12.5>, q11, #17
│ │ -	vrsubhn.i32	d18, q9, q5
│ │ +	vmlsl.u16	<illegal reg q12.5>, d19, d1[0]
│ │ +	vqshl.u16	q9, <illegal reg q2.5>, #2
│ │ +	vsra.u64	d31, d22, #46
│ │ +	vqshlu.s16	d25, d13, #1
│ │ +	vqshlu.s64	d18, d17, #18
│ │  	vrsra.u64	d19, d24, #46
│ │ -	vabal.u16	<illegal reg q12.5>, d16, d18
│ │ -	vqshlu.s16	d18, d26, #2
│ │ -	vmla.i16	<illegal reg q9.5>, q9, d5[3]
│ │ -	vsli.16	<illegal reg q12.5>, q1, #2
│ │ +	vmls.f16	<illegal reg q12.5>, q8, d1[1]
│ │ +	vmlsl.u16	q9, d2, d1[2]
│ │ +	vsra.u16	d19, d4, #14
│ │ +	vsli.16	<illegal reg q12.5>, <illegal reg q12.5>, #2
│ │  	vaddl.u16	q8, d2, d4
│ │  	b.n	375b14 <uniffi_pbcli_checksum_method_api_base@@Base+0x209290>
│ │  	movs	r0, r0
│ │  	b.n	3760f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x209874>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	mov	r4, r5
│ │  	movs	r4, r2
│ │ @@ -963312,40 +963312,40 @@
│ │  	b.n	376bda <uniffi_pbcli_checksum_method_api_base@@Base+0x20a356>
│ │  	movs	r1, r0
│ │  	b.n	3767de <uniffi_pbcli_checksum_method_api_base@@Base+0x209f5a>
│ │  	beq.n	3764d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x209c54>
│ │  	b.n	376938 <uniffi_pbcli_checksum_method_api_base@@Base+0x20a0b4>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r1, r2, r3, r5, r9, sl, ip, pc}
│ │ -	vmls.i16	<illegal reg q12.5>, q0, d2[2]
│ │ +	vraddhn.i32	d25, q8, <illegal reg q4.5>
│ │  	vrsra.u64	q9, <illegal reg q2.5>, #46
│ │ -	vsri.16	d25, d26, #15
│ │ -	vsri.64	q9, q5, #46
│ │ +	vmls.i16	<illegal reg q12.5>, <illegal reg q0.5>, d1[2]
│ │ +	vabal.u16	q9, d2, d1
│ │  	vmlal.u16	<illegal reg q15.5>, d2, d0[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd093ce
│ │ +	vrsra.u64	<illegal reg q12.5>, <illegal reg q10.5>, #48
│ │  			@ <UNDEFINED> instruction: 0xffd20b2c
│ │ -	vrshr.u16	d16, d3, #15
│ │ +	vrshr.u16	d16, d26, #15
│ │  			@ <UNDEFINED> instruction: 0xffd2eebc
│ │  	vqshl.u64	d16, d0, #16
│ │ -	vabal.u16	q8, d1, d31
│ │ +	vsli.16	q8, q3, #1
│ │  			@ <UNDEFINED> instruction: 0xffd2ab30
│ │ -			@ <UNDEFINED> instruction: 0xffd023e2
│ │ +	vraddhn.i32	d18, q0, <illegal reg q4.5>
│ │  	vaddw.u16	q11, q9, d22
│ │  			@ <UNDEFINED> instruction: 0xffd0a9df
│ │ -	vrsra.u16	d18, d6, #15
│ │ +	vrsra.u16	d18, d29, #15
│ │  	vmull.u16	<illegal reg q15.5>, d18, d8
│ │ -	vsra.u64	<illegal reg q12.5>, q11, #46
│ │ -	vsra.u64	d25, d22, #46
│ │ -	vrshr.u16	q9, q1, #14
│ │ -	vsra.u16	<illegal reg q12.5>, q3, #14
│ │ +	vrshr.u16	d25, d13, #14
│ │ +	vsra.u64	<illegal reg q12.5>, <illegal reg q6.5>, #46
│ │ +	vrshr.u16	q9, <illegal reg q12.5>, #14
│ │ +	vsra.u16	<illegal reg q12.5>, <illegal reg q14.5>, #14
│ │  	vshr.u16	<illegal reg q10.5>, <illegal reg q2.5>, #14
│ │ -	vmla.i16	<illegal reg q12.5>, <illegal reg q8.5>, d2[2]
│ │ -	vmlal.u16	q13, d18, d27
│ │ +	vaddw.u16	<illegal reg q12.5>, <illegal reg q0.5>, d9
│ │ +			@ <UNDEFINED> instruction: 0xffd2a8d2
│ │  	vmul.i16	<illegal reg q10.5>, q1, d7[1]
│ │ -	vsra.u16	<illegal reg q11.5>, <illegal reg q3.5>, #15
│ │ +	vsra.u16	<illegal reg q11.5>, q15, #15
│ │  			@ <UNDEFINED> instruction: 0xffd24bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	376a34 <uniffi_pbcli_checksum_method_api_base@@Base+0x20a1b0>
│ │  	beq.n	37642c <uniffi_pbcli_checksum_method_api_base@@Base+0x209ba8>
│ │  	b.n	3769b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x20a134>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	376c62 <uniffi_pbcli_checksum_method_api_base@@Base+0x20a3de>
│ │ @@ -963560,26 +963560,26 @@
│ │  	ldmia.w	sp!, {r2}
│ │  	b.n	37620c <uniffi_pbcli_checksum_method_api_base@@Base+0x209988>
│ │  	movs	r0, r0
│ │  	b.n	376d86 <uniffi_pbcli_checksum_method_api_base@@Base+0x20a502>
│ │  			@ <UNDEFINED> instruction: 0xff971aff
│ │  			@ <UNDEFINED> instruction: 0xfff8eaff
│ │  	ldrsh	r4, [r6, r1]
│ │ -	vqrdmlsh.s16	q12, q0, d6[1]
│ │ -	vmlal.u16	<illegal reg q10.5>, d18, d4
│ │ -			@ <UNDEFINED> instruction: 0xffd28f12
│ │ -	vqshlu.s64	d26, d23, #18
│ │ +			@ <UNDEFINED> instruction: 0xffd08f75
│ │ +	vmlal.u16	<illegal reg q10.5>, d18, d27
│ │ +			@ <UNDEFINED> instruction: 0xffd28f39
│ │ +	vqshlu.s64	q13, q7, #18
│ │  			@ <UNDEFINED> instruction: 0xffd2bedf
│ │  	vqshlu.s16	<illegal reg q10.5>, <illegal reg q7.5>, #0
│ │  	vrsubhn.i32	d16, <illegal reg q0.5>, q1
│ │ -			@ <UNDEFINED> instruction: 0xffd18e7e
│ │ -			@ <UNDEFINED> instruction: 0xffd21f1e
│ │ -	vmul.f16	q9, q9, d3[1]
│ │ -			@ <UNDEFINED> instruction: 0xffd28e1e
│ │ -			@ <UNDEFINED> instruction: 0xffd21ebe
│ │ +	vmull.p<illegal width 16>	q12, d17, d21
│ │ +	vqrdmlsh.s16	<illegal reg q8.5>, q1, d5[0]
│ │ +			@ <UNDEFINED> instruction: 0xffd229f2
│ │ +	vqrdmlah.s16	q12, q1, d5[0]
│ │ +	vqrdmlah.s16	<illegal reg q8.5>, q9, d5[2]
│ │  	vaddl.u16	q8, d2, d4
│ │  	b.n	376264 <uniffi_pbcli_checksum_method_api_base@@Base+0x2099e0>
│ │  	movs	r0, r0
│ │  	b.n	376848 <uniffi_pbcli_checksum_method_api_base@@Base+0x209fc4>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	lsrs	r0, r0
│ │  	movs	r4, r2
│ │ @@ -963613,15 +963613,15 @@
│ │  	b.n	37688c <uniffi_pbcli_checksum_method_api_base@@Base+0x20a008>
│ │  	adds	r1, r2, #1
│ │  	add.w	r0, r0, r4
│ │  	b.n	3762b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x209a2c>
│ │  	beq.n	376788 <uniffi_pbcli_checksum_method_api_base@@Base+0x209f04>
│ │  	b.n	376c10 <uniffi_pbcli_checksum_method_api_base@@Base+0x20a38c>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r6, r8, r9, fp, ip, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r5, r6, r8, r9, fp, ip, pc}
│ │  	vrsra.u64	d19, d24, #46
│ │  			@ <UNDEFINED> instruction: 0xffd14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	376ca8 <uniffi_pbcli_checksum_method_api_base@@Base+0x20a424>
│ │  	beq.n	376798 <uniffi_pbcli_checksum_method_api_base@@Base+0x209f14>
│ │  	b.n	376c2c <uniffi_pbcli_checksum_method_api_base@@Base+0x20a3a8>
│ │  	lsls	r0, r4, #5
│ │ @@ -963781,20 +963781,20 @@
│ │  	movs	r2, r1
│ │  	b.n	376c32 <uniffi_pbcli_checksum_method_api_base@@Base+0x20a3ae>
│ │  	beq.n	37692c <uniffi_pbcli_checksum_method_api_base@@Base+0x20a0a8>
│ │  	b.n	376d8c <uniffi_pbcli_checksum_method_api_base@@Base+0x20a508>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r2, r3, r6, lr}
│ │  	movs	r4, r2
│ │ -	ldr	r2, [sp, #808]	@ 0x328
│ │ +	ldr	r2, [sp, #964]	@ 0x3c4
│ │  	vsubw.u16	<illegal reg q9.5>, q1, d20
│ │  	vsri.64	<illegal reg q11.5>, q10, #47
│ │  			@ <UNDEFINED> instruction: 0xffd15b45
│ │  			@ <UNDEFINED> instruction: 0xffd08d3b
│ │ -	vrsubhn.i32	d30, q8, <illegal reg q7.5>
│ │ +	vqshlu.s64	d30, d22, #16
│ │  			@ <UNDEFINED> instruction: 0xffd13f04
│ │  	movs	r4, r2
│ │  	strb	r4, [r5, #20]
│ │  			@ <UNDEFINED> instruction: 0xffd15b7d
│ │  	vshr.u16	d16, d0, #16
│ │  	b.n	376464 <uniffi_pbcli_checksum_method_api_base@@Base+0x209be0>
│ │  	movs	r0, #32
│ │ @@ -963803,15 +963803,15 @@
│ │  	b.n	37646c <uniffi_pbcli_checksum_method_api_base@@Base+0x209be8>
│ │  	movs	r0, r0
│ │  	b.n	376a50 <uniffi_pbcli_checksum_method_api_base@@Base+0x20a1cc>
│ │  	asrs	r1, r0, #32
│ │  	b.n	376a54 <uniffi_pbcli_checksum_method_api_base@@Base+0x20a1d0>
│ │  	ldr	r7, [sp, #736]	@ 0x2e0
│ │  			@ <UNDEFINED> instruction: 0xeafeda3e
│ │ -	vmla.f16	<illegal reg q13.5>, q0, d6[1]
│ │ +	vsra.u16	<illegal reg q13.5>, <illegal reg q10.5>, #16
│ │  	vmull.u16	q8, d2, d6[0]
│ │  			@ <UNDEFINED> instruction: 0xeafc0001
│ │  	b.n	37708a <uniffi_pbcli_checksum_method_api_base@@Base+0x20a806>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	lsrs	r3, r0, #9
│ │  			@ <UNDEFINED> instruction: 0xeafc4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │ @@ -963862,17 +963862,17 @@
│ │  	movs	r0, r0
│ │  	b.n	37705a <uniffi_pbcli_checksum_method_api_base@@Base+0x20a7d6>
│ │  	str	r1, [r0, r0]
│ │  	stmia	r3!, {}
│ │  	movs	r5, r0
│ │  	b.n	376d02 <uniffi_pbcli_checksum_method_api_base@@Base+0x20a47e>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r7, r8, fp, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd28b3a
│ │ -			@ <UNDEFINED> instruction: 0xffd21bce
│ │ +	ldmia.w	sp!, {r0, r2, r6, r7, r8, fp, sp, lr, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffd28b61
│ │ +			@ <UNDEFINED> instruction: 0xffd21bf5
│ │  	vshr.u16	d16, d0, #14
│ │  	b.n	376514 <uniffi_pbcli_checksum_method_api_base@@Base+0x209c90>
│ │  	movs	r0, #32
│ │  	b.n	37711a <uniffi_pbcli_checksum_method_api_base@@Base+0x20a896>
│ │  	asrs	r4, r1, #32
│ │  	b.n	37651c <uniffi_pbcli_checksum_method_api_base@@Base+0x209c98>
│ │  	movs	r0, r0
│ │ @@ -964185,15 +964185,15 @@
│ │  	ldmia.w	sp!, {r3, r5, r6, r8, r9, sl, fp, ip, sp}
│ │  	movs	r4, r2
│ │  	ldrsh	r2, [r5, r4]
│ │  	vmull.p<illegal width 16>	<illegal reg q9.5>, d17, d8
│ │  	movs	r4, r2
│ │  	ldrsb	r5, [r5, r7]
│ │  	vaddl.u16	q13, d16, d8
│ │ -			@ <UNDEFINED> instruction: 0xffd06ade
│ │ +			@ <UNDEFINED> instruction: 0xffd06b05
│ │  	vmul.i16	<illegal reg q10.5>, q1, d5[0]
│ │  	vmla.i16	q13, q8, d0[2]
│ │  			@ <UNDEFINED> instruction: 0xffd057c1
│ │  	vshr.u16	q13, q6, #16
│ │  	vqshrun.s32	d21, <illegal reg q4.5>, #16
│ │  	vshr.u64	d26, d20, #48
│ │  	vqrshrun.s32	d21, <illegal reg q14.5>, #16
│ │ @@ -964250,15 +964250,15 @@
│ │  	adds	r0, #3
│ │  	b.n	376e58 <uniffi_pbcli_checksum_method_api_base@@Base+0x20a5d4>
│ │  	lsls	r3, r2, #6
│ │  	add.w	r0, r0, r1
│ │  	b.n	377482 <uniffi_pbcli_checksum_method_api_base@@Base+0x20abfe>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r5, r6, r8, sl, ip, sp, pc}
│ │ -	vqrshrun.s32	d17, q5, #15
│ │ +	vmlal.u16	<illegal reg q8.5>, d17, d1
│ │  			@ <UNDEFINED> instruction: 0xffd29f17
│ │  	vaddl.u16	q8, d1, d4
│ │  	b.n	376894 <uniffi_pbcli_checksum_method_api_base@@Base+0x20a010>
│ │  	movs	r0, r0
│ │  	b.n	376e78 <uniffi_pbcli_checksum_method_api_base@@Base+0x20a5f4>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	subs	r4, #36	@ 0x24
│ │ @@ -965236,26 +965236,26 @@
│ │  	ands	r4, r0
│ │  	b.n	377710 <uniffi_pbcli_checksum_method_api_base@@Base+0x20ae8c>
│ │  			@ <UNDEFINED> instruction: 0xffbfeaff
│ │  	beq.n	377630 <uniffi_pbcli_checksum_method_api_base@@Base+0x20adac>
│ │  	b.n	377a90 <uniffi_pbcli_checksum_method_api_base@@Base+0x20b20c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r3, r4, r5, r6, r8, r9, lr}
│ │ -	vshr.u64	q12, q7, #48
│ │ -			@ <UNDEFINED> instruction: 0xffd2df02
│ │ -	vshr.u64	d24, d14, #46
│ │ +	vaddw.u16	q12, q0, d5
│ │ +			@ <UNDEFINED> instruction: 0xffd2df29
│ │ +	vmla.i16	q12, q9, d5[0]
│ │  	vsubl.u16	q12, d2, d10
│ │  	vqrdmlsh.s16	q10, q0, d5[3]
│ │ -	vshr.u64	d17, d14, #48
│ │ -	vmull.p<illegal width 16>	<illegal reg q14.5>, d2, d22
│ │ -			@ <UNDEFINED> instruction: 0xffd27f7a
│ │ +	vmla.i16	<illegal reg q8.5>, q8, d5[0]
│ │ +	vqrdmlah.s16	<illegal reg q14.5>, q1, d5[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd27fa1
│ │  	vmla.i16	q12, q9, d2[2]
│ │  	vqrdmlah.s16	q10, q0, d5[0]
│ │ -			@ <UNDEFINED> instruction: 0xffd00f8e
│ │ -			@ <UNDEFINED> instruction: 0xffd2dd1a
│ │ +			@ <UNDEFINED> instruction: 0xffd00fb5
│ │ +	vqrdmulh.s16	<illegal reg q14.5>, q1, d1[0]
│ │  			@ <UNDEFINED> instruction: 0xffd24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	377b54 <uniffi_pbcli_checksum_method_api_base@@Base+0x20b2d0>
│ │  	svc	67	@ 0x43
│ │  	b.n	377ad8 <uniffi_pbcli_checksum_method_api_base@@Base+0x20b254>
│ │  	adds	r0, #0
│ │  	b.n	377164 <uniffi_pbcli_checksum_method_api_base@@Base+0x20a8e0>
│ │ @@ -966808,15 +966808,15 @@
│ │  	b.n	378840 <uniffi_pbcli_checksum_method_api_base@@Base+0x20bfbc>
│ │  	add	r0, pc, #676	@ (adr r0, 3785cc <uniffi_pbcli_checksum_method_api_base@@Base+0x20bd48>)
│ │  			@ <UNDEFINED> instruction: 0xebfe0004
│ │  	b.n	37866e <uniffi_pbcli_checksum_method_api_base@@Base+0x20bdea>
│ │  	beq.n	378368 <uniffi_pbcli_checksum_method_api_base@@Base+0x20bae4>
│ │  	b.n	3787c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x20bf44>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r5, r7, r8, sl, sp}
│ │ +	ldmia.w	sp!, {r3, r6, r7, r8, sl, sp}
│ │  	vshr.u16	d16, d0, #14
│ │  	b.n	377e7c <uniffi_pbcli_checksum_method_api_base@@Base+0x20b5f8>
│ │  	movs	r0, #32
│ │  	b.n	378a82 <uniffi_pbcli_checksum_method_api_base@@Base+0x20c1fe>
│ │  	asrs	r4, r1, #32
│ │  	b.n	377e84 <uniffi_pbcli_checksum_method_api_base@@Base+0x20b600>
│ │  	movs	r0, r0
│ │ @@ -966946,22 +966946,22 @@
│ │  	b.n	3787aa <uniffi_pbcli_checksum_method_api_base@@Base+0x20bf26>
│ │  	asrs	r6, r4, #21
│ │  			@ <UNDEFINED> instruction: 0xebfc0001
│ │  	b.n	378bb2 <uniffi_pbcli_checksum_method_api_base@@Base+0x20c32e>
│ │  	beq.n	378494 <uniffi_pbcli_checksum_method_api_base@@Base+0x20bc10>
│ │  	b.n	37890c <uniffi_pbcli_checksum_method_api_base@@Base+0x20c088>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r6, r7, r8, r9, sl, sp, lr}
│ │ -	vmla.i16	<illegal reg q11.5>, q9, d6[3]
│ │ -	vraddhn.i32	d28, q1, <illegal reg q5.5>
│ │ -	vsra.u16	q8, q13, #14
│ │ +	ldmia.w	sp!, {r2, r3, r4, fp, sp, lr}
│ │ +	vsra.u16	d23, d5, #14
│ │ +	vsri.16	d28, d18, #14
│ │ +	vaddw.u16	q8, q9, d17
│ │  			@ <UNDEFINED> instruction: 0xffd25992
│ │ -	vshr.u64	d23, d2, #47
│ │ +	vshr.u64	d23, d25, #47
│ │  			@ <UNDEFINED> instruction: 0xffd2cf0c
│ │ -	vmla.i16	<illegal reg q11.5>, q0, d2[1]
│ │ +	vshr.u16	<illegal reg q11.5>, <illegal reg q8.5>, #16
│ │  			@ <UNDEFINED> instruction: 0xffd24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3789bc <uniffi_pbcli_checksum_method_api_base@@Base+0x20c138>
│ │  	beq.n	3784dc <uniffi_pbcli_checksum_method_api_base@@Base+0x20bc58>
│ │  	b.n	378940 <uniffi_pbcli_checksum_method_api_base@@Base+0x20c0bc>
│ │  	str	r0, [r0, #0]
│ │  	b.n	378bea <uniffi_pbcli_checksum_method_api_base@@Base+0x20c366>
│ │ @@ -967279,15 +967279,15 @@
│ │  	b.n	378dee <uniffi_pbcli_checksum_method_api_base@@Base+0x20c56a>
│ │  			@ <UNDEFINED> instruction: 0xffb0eaff
│ │  	asrs	r3, r0, #21
│ │  	vmls.i16	q9, <illegal reg q8.5>, d7[3]
│ │  	vsli.16	<illegal reg q8.5>, <illegal reg q9.5>, #0
│ │  	vsli.16	d18, d15, #1
│ │  	vsri.16	d27, d31, #16
│ │ -	vmul.i16	q14, <illegal reg q8.5>, d0[0]
│ │ +	vmul.i16	q14, <illegal reg q8.5>, d7[2]
│ │  	vqdmulh.s16	<illegal reg q15.5>, <illegal reg q8.5>, d6[3]
│ │  	vabal.u16	<illegal reg q8.5>, d16, d27
│ │  	vsli.16	q9, <illegal reg q3.5>, #1
│ │  	vsri.16	d17, d31, #16
│ │  			@ <UNDEFINED> instruction: 0xffd123eb
│ │  	vmull.u16	q10, d16, d20
│ │  	movs	r6, r2
│ │ @@ -968016,59 +968016,59 @@
│ │  	stmia.w	sp, {r3, ip, lr}
│ │  	b.n	378900 <uniffi_pbcli_checksum_method_api_base@@Base+0x20c07c>
│ │  	strb	r3, [r5, #29]
│ │  			@ <UNDEFINED> instruction: 0xebfd0007
│ │  	b.n	37912e <uniffi_pbcli_checksum_method_api_base@@Base+0x20c8aa>
│ │  	asrs	r7, r5, #9
│ │  			@ <UNDEFINED> instruction: 0xebfcffc3
│ │ -			@ <UNDEFINED> instruction: 0xeaffc89d
│ │ +			@ <UNDEFINED> instruction: 0xeaffc8c4
│ │  	vrshr.u64	d17, d27, #47
│ │ -			@ <UNDEFINED> instruction: 0xffd1dda8
│ │ +	vqrdmulh.s16	<illegal reg q14.5>, <illegal reg q8.5>, d7[1]
│ │  	vaddw.u16	<illegal reg q13.5>, <illegal reg q8.5>, d19
│ │ -	vrsubhn.i32	d28, <illegal reg q0.5>, q10
│ │ +	vmlsl.u16	q14, d1, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffd1fa52
│ │  	vsra.u64	<illegal reg q8.5>, <illegal reg q13.5>, #48
│ │ -	vqdmulh.s16	<illegal reg q14.5>, <illegal reg q8.5>, d0[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd1dd0f
│ │  	vsra.u16	d27, d15, #15
│ │ -	vabal.u16	q14, d17, d20
│ │ +	vmls.f16	q14, <illegal reg q8.5>, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffd1f9d2
│ │  	vrsra.u16	d17, d20, #16
│ │  	vsubl.u16	<illegal reg q8.5>, d17, d3
│ │ -			@ <UNDEFINED> instruction: 0xffd1dd70
│ │ +			@ <UNDEFINED> instruction: 0xffd1dd97
│ │  	vaddw.u16	<illegal reg q8.5>, <illegal reg q8.5>, d3
│ │ -			@ <UNDEFINED> instruction: 0xffd1dc70
│ │ +			@ <UNDEFINED> instruction: 0xffd1dc97
│ │  	vsri.64	d24, d17, #47
│ │  	vqrdmlah.s16	q11, q0, d7[0]
│ │  			@ <UNDEFINED> instruction: 0xffd0adff
│ │ -	vsubl.u16	q14, d17, d4
│ │ +	vsubl.u16	q14, d17, d27
│ │  	vrsubhn.i32	d31, <illegal reg q8.5>, q15
│ │  	vaddw.u16	<illegal reg q8.5>, q0, d31
│ │  			@ <UNDEFINED> instruction: 0xffd10f33
│ │  	vsli.16	<illegal reg q10.5>, <illegal reg q1.5>, #1
│ │  	vmull.u16	<illegal reg q13.5>, d17, d3[0]
│ │  			@ <UNDEFINED> instruction: 0xffd10f03
│ │ -			@ <UNDEFINED> instruction: 0xffd1d9f0
│ │ +	vshll.u16	<illegal reg q14.5>, d7, #1
│ │  	vmla.i16	<illegal reg q8.5>, <illegal reg q0.5>, d7[0]
│ │  			@ <UNDEFINED> instruction: 0xffd10df3
│ │  	vsli.64	<illegal reg q15.5>, q5, #17
│ │  			@ <UNDEFINED> instruction: 0xffd0ad13
│ │ -	vsra.u64	d28, d4, #47
│ │ +	vsra.u64	d28, d27, #47
│ │  			@ <UNDEFINED> instruction: 0xffd10edf
│ │ -	vmul.f16	<illegal reg q14.5>, <illegal reg q8.5>, d4[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd1d9f3
│ │  			@ <UNDEFINED> instruction: 0xffd1caf2
│ │  			@ <UNDEFINED> instruction: 0xffd00f97
│ │  	vqrdmlah.s16	q8, <illegal reg q0.5>, d3[1]
│ │  	vrsubhn.i32	d31, <illegal reg q0.5>, q13
│ │  			@ <UNDEFINED> instruction: 0xffd0ad5f
│ │ -	vmla.f16	q14, <illegal reg q8.5>, d4[2]
│ │ +	vsubl.u16	q14, d1, d11
│ │  	vmlal.u16	<illegal reg q8.5>, d17, d7[3]
│ │ -			@ <UNDEFINED> instruction: 0xffd1dddc
│ │ +	vmull.p<illegal width 16>	<illegal reg q14.5>, d1, d3
│ │  	vshr.u64	<illegal reg q8.5>, <illegal reg q5.5>, #47
│ │  			@ <UNDEFINED> instruction: 0xffd10fdf
│ │ -	vmull.u16	<illegal reg q14.5>, d17, d4[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd1daf3
│ │  	vaddl.u16	q8, d1, d4
│ │  	b.n	3789ec <uniffi_pbcli_checksum_method_api_base@@Base+0x20c168>
│ │  	movs	r0, r0
│ │  	b.n	378fd0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20c74c>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	adds	r0, r2, #0
│ │  	movs	r4, r2
│ │ @@ -968130,15 +968130,15 @@
│ │  	b.n	379054 <uniffi_pbcli_checksum_method_api_base@@Base+0x20c7d0>
│ │  	asrs	r7, r3, #9
│ │  	add.w	r0, r0, r4
│ │  	b.n	378a78 <uniffi_pbcli_checksum_method_api_base@@Base+0x20c1f4>
│ │  	beq.n	378f50 <uniffi_pbcli_checksum_method_api_base@@Base+0x20c6cc>
│ │  	b.n	3793d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x20cb54>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r6, r8}
│ │ +	ldmia.w	sp!, {r7, r8}
│ │  	vsli.16	d22, d31, #2
│ │  			@ <UNDEFINED> instruction: 0xffd14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	379470 <uniffi_pbcli_checksum_method_api_base@@Base+0x20cbec>
│ │  	beq.n	378f60 <uniffi_pbcli_checksum_method_api_base@@Base+0x20c6dc>
│ │  	b.n	3793f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x20cb70>
│ │  	lsls	r0, r7, #5
│ │ @@ -968312,15 +968312,15 @@
│ │  	b.n	37956c <uniffi_pbcli_checksum_method_api_base@@Base+0x20cce8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r2, r3, r4, sl, fp, ip}
│ │  	movs	r4, r2
│ │  	ldmia	r7, {r1, r2, r3, r4, r5, r7}
│ │  			@ <UNDEFINED> instruction: 0xffd2abbb
│ │  			@ <UNDEFINED> instruction: 0xffd04d91
│ │ -	vqrdmlah.s16	q9, <illegal reg q0.5>, d4[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd12e93
│ │  			@ <UNDEFINED> instruction: 0xffd2ab53
│ │  			@ <UNDEFINED> instruction: 0xffd04d29
│ │  	vaddw.u16	<illegal reg q11.5>, <illegal reg q8.5>, d21
│ │  			@ <UNDEFINED> instruction: 0xffd01abc
│ │  	movs	r4, r2
│ │  	add	r3, sp, #556	@ 0x22c
│ │  	vqrdmulh.s16	q10, q0, d1[2]
│ │ @@ -968414,18 +968414,18 @@
│ │  	b.n	378cf0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20c46c>
│ │  	movs	r6, r0
│ │  	b.n	37950a <uniffi_pbcli_checksum_method_api_base@@Base+0x20cc86>
│ │  	bmi.n	3791a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20c91c>
│ │  			@ <UNDEFINED> instruction: 0xebfb0001
│ │  	b.n	379912 <uniffi_pbcli_checksum_method_api_base@@Base+0x20d08e>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r3, r6, r7, r8, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd26366
│ │ -	vmull.u16	q15, d18, d2[0]
│ │ -			@ <UNDEFINED> instruction: 0xffd14ffd
│ │ +	ldmia.w	sp!, {r0, r4, r5, r6, r7, r8, lr, pc}
│ │ +	vsubw.u16	q11, q9, d13
│ │ +	vmull.u16	q15, d18, d1[3]
│ │ +	vaddl.u16	<illegal reg q10.5>, d1, d20
│ │  			@ <UNDEFINED> instruction: 0xffd219a0
│ │  	vaddl.u16	q8, d0, d4
│ │  	b.n	378d2c <uniffi_pbcli_checksum_method_api_base@@Base+0x20c4a8>
│ │  	movs	r0, r0
│ │  	b.n	379310 <uniffi_pbcli_checksum_method_api_base@@Base+0x20ca8c>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	subs	r4, r4, r2
│ │ @@ -968701,27 +968701,27 @@
│ │  	b.n	379b9e <uniffi_pbcli_checksum_method_api_base@@Base+0x20d31a>
│ │  	movs	r0, r1
│ │  	b.n	3797a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x20cf1e>
│ │  	beq.n	37949c <uniffi_pbcli_checksum_method_api_base@@Base+0x20cc18>
│ │  	b.n	3798fc <uniffi_pbcli_checksum_method_api_base@@Base+0x20d078>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r1, r3, r4, r5, r6, r7, sp, lr}
│ │ -	vrshr.u64	<illegal reg q14.5>, q9, #47
│ │ +	vrsra.u16	d29, d9, #15
│ │  			@ <UNDEFINED> instruction: 0xffd16e99
│ │  	vshr.u64	d22, d26, #48
│ │ -	vrshr.u64	d29, d18, #47
│ │ +	vrshr.u64	<illegal reg q14.5>, <illegal reg q4.5>, #47
│ │  			@ <UNDEFINED> instruction: 0xffd16e59
│ │  	vshr.u64	d20, d20, #48
│ │  	movs	r6, r2
│ │  	adds	r0, r2, r5
│ │  	movs	r4, r2
│ │  	str	r2, [r0, #8]
│ │ -	vrshr.u16	<illegal reg q14.5>, q13, #15
│ │ +	vsubl.u16	<illegal reg q14.5>, d17, d17
│ │  	vsra.u16	d22, d18, #15
│ │ -	vsubw.u16	<illegal reg q14.5>, <illegal reg q0.5>, d26
│ │ +	vrsra.u16	<illegal reg q14.5>, <illegal reg q0.5>, #15
│ │  	vaddl.u16	q8, d1, d4
│ │  	b.n	378fdc <uniffi_pbcli_checksum_method_api_base@@Base+0x20c758>
│ │  	movs	r0, r0
│ │  	b.n	3795c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20cd3c>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	asrs	r0, r3, #31
│ │  	movs	r4, r2
│ │ @@ -969926,27 +969926,27 @@
│ │  	asrs	r7, r1, #2
│ │  	b.n	37a696 <uniffi_pbcli_checksum_method_api_base@@Base+0x20de12>
│ │  	movs	r0, #0
│ │  	b.n	37a69a <uniffi_pbcli_checksum_method_api_base@@Base+0x20de16>
│ │  	strb	r6, [r0, #17]
│ │  			@ <UNDEFINED> instruction: 0xebfdff29
│ │  			@ <UNDEFINED> instruction: 0xeafffc4a
│ │ -	vmull.u<illegal width 8>	<illegal reg q12.5>, d31, d1[2]
│ │ +			@ <UNDEFINED> instruction: 0xffcf9af0
│ │  	vmlsl.u16	<illegal reg q15.5>, d18, d30
│ │ -			@ <UNDEFINED> instruction: 0xffcf992d
│ │ +	vqrshrn.u16	d25, q2, #1
│ │  			@ <UNDEFINED> instruction: 0xffd237c0
│ │  	movs	r6, r2
│ │  	bl	708f16 <uniffi_pbcli_checksum_method_api_base@@Base+0x59c692>
│ │ -	ldr	r4, [pc, #580]	@ (37a1c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20d93c>)
│ │ +	ldr	r4, [pc, #736]	@ (37a25c <uniffi_pbcli_checksum_method_api_base@@Base+0x20d9d8>)
│ │  			@ <UNDEFINED> instruction: 0xffd29d7c
│ │  			@ <UNDEFINED> instruction: 0xffd70c7c
│ │  	movs	r0, r0
│ │  	ldr	r4, [sp, #976]	@ 0x3d0
│ │  			@ <UNDEFINED> instruction: 0xffd7f3c2
│ │ -	vmlal.u<illegal width 8>	<illegal reg q12.5>, d15, d1[0]
│ │ +	vmlal.u<illegal width 8>	<illegal reg q12.5>, d15, d0[6]
│ │  	vmlal.u16	q10, d2, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	37a2da <uniffi_pbcli_checksum_method_api_base@@Base+0x20da56>
│ │  	beq.n	379fdc <uniffi_pbcli_checksum_method_api_base@@Base+0x20d758>
│ │  	b.n	37a438 <uniffi_pbcli_checksum_method_api_base@@Base+0x20dbb4>
│ │  	asrs	r0, r0, #32
│ │  	b.n	37a2e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x20da5e>
│ │ @@ -971521,20 +971521,20 @@
│ │  	b.n	37b46e <uniffi_pbcli_checksum_method_api_base@@Base+0x20ebea>
│ │  	movs	r4, r0
│ │  	b.n	37b072 <uniffi_pbcli_checksum_method_api_base@@Base+0x20e7ee>
│ │  	beq.n	37ad6c <uniffi_pbcli_checksum_method_api_base@@Base+0x20e4e8>
│ │  	b.n	37b1cc <uniffi_pbcli_checksum_method_api_base@@Base+0x20e948>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r2, r4, r5, r6, r7, r8, sl, ip, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffd19b7c
│ │ +			@ <UNDEFINED> instruction: 0xffd19ba3
│ │  	vsri.64	d18, d20, #46
│ │  	movs	r6, r2
│ │  	ldrh	r5, [r3, #58]	@ 0x3a
│ │ -			@ <UNDEFINED> instruction: 0xffd0cf57
│ │ -			@ <UNDEFINED> instruction: 0xffd16db1
│ │ +			@ <UNDEFINED> instruction: 0xffd0cf7e
│ │ +			@ <UNDEFINED> instruction: 0xffd16dd8
│ │  			@ <UNDEFINED> instruction: 0xffd24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	37b274 <uniffi_pbcli_checksum_method_api_base@@Base+0x20e9f0>
│ │  	beq.n	37ad84 <uniffi_pbcli_checksum_method_api_base@@Base+0x20e500>
│ │  	b.n	37b1f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x20e974>
│ │  	movs	r4, r1
│ │  	b.n	37a87c <uniffi_pbcli_checksum_method_api_base@@Base+0x20dff8>
│ │ @@ -971810,22 +971810,22 @@
│ │  	b.n	37b702 <uniffi_pbcli_checksum_method_api_base@@Base+0x20ee7e>
│ │  	movs	r7, r0
│ │  	b.n	37b306 <uniffi_pbcli_checksum_method_api_base@@Base+0x20ea82>
│ │  	beq.n	37b000 <uniffi_pbcli_checksum_method_api_base@@Base+0x20e77c>
│ │  	b.n	37b460 <uniffi_pbcli_checksum_method_api_base@@Base+0x20ebdc>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r1, sl, fp, ip, sp, pc}
│ │ -	vmlsl.u16	<illegal reg q12.5>, d0, d0
│ │ +	vmlsl.u16	<illegal reg q12.5>, d0, d23
│ │  			@ <UNDEFINED> instruction: 0xffd2bb2b
│ │ -			@ <UNDEFINED> instruction: 0xffd0ccb7
│ │ -	vqdmulh.s16	q14, <illegal reg q8.5>, d0[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd0ccde
│ │ +	vqdmulh.s16	q14, <illegal reg q8.5>, d7[3]
│ │  	vsubl.u16	q9, d1, d16
│ │  	movs	r6, r2
│ │  	hlt	0x0003
│ │ -			@ <UNDEFINED> instruction: 0xffd0cd0b
│ │ +			@ <UNDEFINED> instruction: 0xffd0cd32
│ │  			@ <UNDEFINED> instruction: 0xffd1476e
│ │  			@ <UNDEFINED> instruction: 0xffd04c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	37b514 <uniffi_pbcli_checksum_method_api_base@@Base+0x20ec90>
│ │  	udf	#35	@ 0x23
│ │  	b.n	37b498 <uniffi_pbcli_checksum_method_api_base@@Base+0x20ec14>
│ │  	movs	r0, r0
│ │ @@ -972254,30 +972254,30 @@
│ │  	b.n	37aed0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20e64c>
│ │  	lsrs	r1, r0, #16
│ │  	b.n	37b8b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20f02c>
│ │  	asrs	r1, r0, #32
│ │  	b.n	37b4b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x20ec34>
│ │  	vpmin.u32	q15, q9, <illegal reg q15.5>
│ │  	bcs.n	37b498 <uniffi_pbcli_checksum_method_api_base@@Base+0x20ec14>
│ │ -	vqrdmlsh.s16	<illegal reg q12.5>, q8, d6[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd09ff5
│ │  			@ <UNDEFINED> instruction: 0xffd12b84
│ │  	vsra.u16	q8, <illegal reg q14.5>, #15
│ │ -	vraddhn.i32	d27, <illegal reg q0.5>, q1
│ │ -			@ <UNDEFINED> instruction: 0xffd17e75
│ │ -	vqrdmlah.s16	<illegal reg q11.5>, q1, d3[3]
│ │ +	vraddhn.i32	d27, <illegal reg q0.5>, <illegal reg q12.5>
│ │ +			@ <UNDEFINED> instruction: 0xffd17e9c
│ │ +			@ <UNDEFINED> instruction: 0xffd27e92
│ │  	vsra.u16	d29, d11, #14
│ │ -	vmull.u16	<illegal reg q9.5>, d16, d6[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd03af5
│ │  	vsubw.u16	<illegal reg q14.5>, q9, d11
│ │  			@ <UNDEFINED> instruction: 0xffd073ce
│ │  	vmla.i16	<illegal reg q11.5>, q8, d1[2]
│ │  			@ <UNDEFINED> instruction: 0xffd12d34
│ │ -	vsli.64	d31, d24, #17
│ │ +	vsli.64	<illegal reg q15.5>, <illegal reg q7.5>, #17
│ │  	vmull.p<illegal width 16>	q13, d17, d15
│ │ -	vqdmulh.s16	q8, q9, d5[0]
│ │ -			@ <UNDEFINED> instruction: 0xffd2ca9f
│ │ +	vqdmulh.s16	q8, q9, d4[3]
│ │ +	vmull.u16	q14, d18, d6[0]
│ │  			@ <UNDEFINED> instruction: 0xffd12c1f
│ │  			@ <UNDEFINED> instruction: 0xffd04c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	37b908 <uniffi_pbcli_checksum_method_api_base@@Base+0x20f084>
│ │  	str	r0, [r0, r0]
│ │  	b.n	37b732 <uniffi_pbcli_checksum_method_api_base@@Base+0x20eeae>
│ │  	movs	r0, r0
│ │ @@ -972530,25 +972530,25 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	37b738 <uniffi_pbcli_checksum_method_api_base@@Base+0x20eeb4>
│ │  			@ <UNDEFINED> instruction: 0xff93eaff
│ │  			@ <UNDEFINED> instruction: 0xb7dd
│ │  	vmls.f16	q15, q8, d6[2]
│ │  	vmul.i16	q9, q0, d4[0]
│ │  			@ <UNDEFINED> instruction: 0xffd1a9a3
│ │ -			@ <UNDEFINED> instruction: 0xffd29a75
│ │ +			@ <UNDEFINED> instruction: 0xffd29a9c
│ │  	vqdmulh.s16	q11, <illegal reg q0.5>, d2[3]
│ │  	vshr.u16	d29, d13, #15
│ │  			@ <UNDEFINED> instruction: 0xffd028d5
│ │  	vabal.u16	<illegal reg q8.5>, d0, d28
│ │  			@ <UNDEFINED> instruction: 0xffd1ff80
│ │  	vmlsl.u16	q12, d16, d0[2]
│ │  	vmull.u16	q13, d16, d7[2]
│ │ -	vaddl.u16	q9, d18, d7
│ │ -	vabdl.u16	q14, d2, d31
│ │ -	vshr.u16	d18, d25, #15
│ │ +	vaddl.u16	q9, d18, d30
│ │ +	vqshl.u16	q14, q3, #2
│ │ +	vmla.i16	q9, <illegal reg q0.5>, d0[2]
│ │  			@ <UNDEFINED> instruction: 0xffd24ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	37bb7c <uniffi_pbcli_checksum_method_api_base@@Base+0x20f2f8>
│ │  	beq.n	37b66c <uniffi_pbcli_checksum_method_api_base@@Base+0x20ede8>
│ │  	b.n	37bb00 <uniffi_pbcli_checksum_method_api_base@@Base+0x20f27c>
│ │  	str	r0, [sp, #0]
│ │  	b.n	37b9aa <uniffi_pbcli_checksum_method_api_base@@Base+0x20f126>
│ │ @@ -972648,15 +972648,15 @@
│ │  	movs	r4, r0
│ │  	b.n	37ba82 <uniffi_pbcli_checksum_method_api_base@@Base+0x20f1fe>
│ │  	beq.n	37b77c <uniffi_pbcli_checksum_method_api_base@@Base+0x20eef8>
│ │  	b.n	37bbdc <uniffi_pbcli_checksum_method_api_base@@Base+0x20f358>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r2, r5, r7, r9, fp, ip}
│ │  	movs	r6, r2
│ │ -	stmia	r5!, {r0, r1, r2, r6}
│ │ +	stmia	r5!, {r1, r2, r3, r5, r6}
│ │  			@ <UNDEFINED> instruction: 0xffd1dbf6
│ │  	vmlal.u8	q10, d15, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	37ba9e <uniffi_pbcli_checksum_method_api_base@@Base+0x20f21a>
│ │  	beq.n	37b770 <uniffi_pbcli_checksum_method_api_base@@Base+0x20eeec>
│ │  	b.n	37bbfc <uniffi_pbcli_checksum_method_api_base@@Base+0x20f378>
│ │  	adds	r0, #2
│ │ @@ -972847,25 +972847,25 @@
│ │  	b.n	37bc46 <uniffi_pbcli_checksum_method_api_base@@Base+0x20f3c2>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	37b424 <uniffi_pbcli_checksum_method_api_base@@Base+0x20eba0>
│ │  	movs	r5, r1
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	37bda8 <uniffi_pbcli_checksum_method_api_base@@Base+0x20f524>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r5, r7, r8, r9, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd178f5
│ │ +	ldmia.w	sp!, {r1, r4, r6, r7, r8, r9, lr, pc}
│ │ +	vqshrn.u32	d23, q6, #15
│ │  	vshll.u16	q11, d25, #2
│ │ -			@ <UNDEFINED> instruction: 0xffd1ef30
│ │ +			@ <UNDEFINED> instruction: 0xffd1ef57
│ │  	vrsubhn.i32	d18, <illegal reg q0.5>, q6
│ │ -	vmlsl.u16	q10, d17, d31
│ │ +			@ <UNDEFINED> instruction: 0xffd14ad6
│ │  			@ <UNDEFINED> instruction: 0xffd23e97
│ │ -	vmlsl.u16	q10, d16, d3
│ │ +	vmlsl.u16	q10, d16, d26
│ │  	vsubw.u16	q15, q9, d22
│ │ -			@ <UNDEFINED> instruction: 0xffd0c3e3
│ │ -			@ <UNDEFINED> instruction: 0xffd1792d
│ │ +	vraddhn.i32	d28, q0, q5
│ │ +	vqrshrn.u32	d23, q2, #15
│ │  	vmull.u16	q9, d2, d11
│ │  			@ <UNDEFINED> instruction: 0xffd14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	37be68 <uniffi_pbcli_checksum_method_api_base@@Base+0x20f5e4>
│ │  	beq.n	37b958 <uniffi_pbcli_checksum_method_api_base@@Base+0x20f0d4>
│ │  	b.n	37bdec <uniffi_pbcli_checksum_method_api_base@@Base+0x20f568>
│ │  	strh	r0, [r1, #0]
│ │ @@ -973314,36 +973314,36 @@
│ │  			@ <UNDEFINED> instruction: 0xebff4000
│ │  	b.n	37c47e <uniffi_pbcli_checksum_method_api_base@@Base+0x20fbfa>
│ │  	movs	r4, r0
│ │  	b.n	37c082 <uniffi_pbcli_checksum_method_api_base@@Base+0x20f7fe>
│ │  	beq.n	37bd7c <uniffi_pbcli_checksum_method_api_base@@Base+0x20f4f8>
│ │  	b.n	37c1dc <uniffi_pbcli_checksum_method_api_base@@Base+0x20f958>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r9, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r5, r9, lr, pc}
│ │  	vmul.i16	<illegal reg q14.5>, <illegal reg q8.5>, d4[0]
│ │ -	vmla.f<illegal width 8>	q14, <illegal reg q15.5>, d3[3]
│ │ +	vsra.u64	q14, q11, #49
│ │  			@ <UNDEFINED> instruction: 0xffd1d890
│ │ -			@ <UNDEFINED> instruction: 0xffcfbff3
│ │ +	vshr.u8	d28, d10, #1
│ │  	vqshlu.s64	d29, d20, #17
│ │  			@ <UNDEFINED> instruction: 0xffcf7f05
│ │ -	vqrdmlsh.s16	<illegal reg q13.5>, q8, d3[0]
│ │ +	vqrdmlsh.s16	<illegal reg q13.5>, q8, d2[3]
│ │  	vrsubhn.i32	d29, <illegal reg q8.5>, q2
│ │  			@ <UNDEFINED> instruction: 0xffcf7ed5
│ │ -			@ <UNDEFINED> instruction: 0xffd0bf83
│ │ +			@ <UNDEFINED> instruction: 0xffd0bfaa
│ │  	vqshrun.s32	d28, q0, #15
│ │ -	vqshlu.s64	d25, d23, #16
│ │ -			@ <UNDEFINED> instruction: 0xffd2bf37
│ │ +	vqshlu.s64	<illegal reg q12.5>, q7, #16
│ │ +			@ <UNDEFINED> instruction: 0xffd2bf5e
│ │  	vsli.64	<illegal reg q14.5>, q12, #17
│ │ -	vsra.u8	q14, <illegal reg q1.5>, #1
│ │ -	vaddw.u16	q14, <illegal reg q0.5>, d31
│ │ -	vmla.i16	q14, <illegal reg q8.5>, d3[3]
│ │ +	vsra.u8	q14, q13, #1
│ │ +	vsra.u16	q14, q3, #15
│ │ +	vsra.u16	d28, d2, #15
│ │  	vabdl.u16	<illegal reg q14.5>, d17, d28
│ │ -	vmla.i<illegal width 8>	q14, <illegal reg q15.5>, d3[0]
│ │ +	vmla.i<illegal width 8>	q14, <illegal reg q15.5>, d2[6]
│ │  	vabdl.u16	<illegal reg q14.5>, d17, d4
│ │ -	vsubl.u8	q14, d15, d31
│ │ +	vrshr.u8	q14, q3, #1
│ │  			@ <UNDEFINED> instruction: 0xffd1d8f0
│ │  			@ <UNDEFINED> instruction: 0xffcf4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	37c2c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x20fa44>
│ │  	asrs	r4, r0, #32
│ │  	b.n	37b80c <uniffi_pbcli_checksum_method_api_base@@Base+0x20ef88>
│ │  	movs	r0, r0
│ │ @@ -973513,18 +973513,18 @@
│ │  	and.w	r0, r0, r1, lsl #28
│ │  	b.n	37c66e <uniffi_pbcli_checksum_method_api_base@@Base+0x20fdea>
│ │  	movs	r7, r0
│ │  	b.n	37c272 <uniffi_pbcli_checksum_method_api_base@@Base+0x20f9ee>
│ │  	beq.n	37bf6c <uniffi_pbcli_checksum_method_api_base@@Base+0x20f6e8>
│ │  	b.n	37c3cc <uniffi_pbcli_checksum_method_api_base@@Base+0x20fb48>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r3, r7, r8, sl, fp, ip, sp, pc}
│ │ -	vmla.f16	<illegal reg q12.5>, <illegal reg q8.5>, d5[2]
│ │ -	vqrdmulh.s16	<illegal reg q13.5>, <illegal reg q0.5>, d3[1]
│ │ -	vaddw.u16	<illegal reg q12.5>, <illegal reg q8.5>, d21
│ │ +	ldmia.w	sp!, {r1, r4, r5, r7, r8, sl, fp, ip, sp, pc}
│ │ +	vsubl.u16	<illegal reg q12.5>, d1, d12
│ │ +			@ <UNDEFINED> instruction: 0xffd1bd72
│ │ +	vmla.f16	<illegal reg q12.5>, <illegal reg q8.5>, d4[1]
│ │  	vaddl.u16	q8, d1, d4
│ │  	b.n	37ba8c <uniffi_pbcli_checksum_method_api_base@@Base+0x20f208>
│ │  	movs	r0, r0
│ │  	b.n	37c070 <uniffi_pbcli_checksum_method_api_base@@Base+0x20f7ec>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	mcr	0, 2, r0, cr4, cr3, {0}
│ │  	ldr	r7, [pc, #960]	@ (37c31c <uniffi_pbcli_checksum_method_api_base@@Base+0x20fa98>)
│ │ @@ -973755,23 +973755,23 @@
│ │  	b.n	37c492 <uniffi_pbcli_checksum_method_api_base@@Base+0x20fc0e>
│ │  	beq.n	37c18c <uniffi_pbcli_checksum_method_api_base@@Base+0x20f908>
│ │  	b.n	37c5ec <uniffi_pbcli_checksum_method_api_base@@Base+0x20fd68>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {pc}
│ │  	b.n	37c89e <uniffi_pbcli_checksum_method_api_base@@Base+0x21001a>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │ -	stc2	15, cr15, [r8, #-836]!	@ 0xfffffcbc
│ │ +	stc2l	15, cr15, [pc, #-836]	@ 37be20 <uniffi_pbcli_checksum_method_api_base@@Base+0x20f59c>
│ │  	stmia	r3!, {r0, r1, r3, r5, r7}
│ │ -	vsubw.u16	<illegal reg q12.5>, q0, d18
│ │ -	vmls.i16	<illegal reg q9.5>, q9, d2[0]
│ │ -			@ <UNDEFINED> instruction: 0xffd2fd9f
│ │ +			@ <UNDEFINED> instruction: 0xffd09349
│ │ +	vmls.i16	<illegal reg q9.5>, q9, d1[3]
│ │ +	vqrdmulh.s16	<illegal reg q15.5>, q9, d6[0]
│ │  	vmlal.u16	q11, d1, d5[3]
│ │ -	vmls.i16	q14, <illegal reg q8.5>, d2[0]
│ │ +	vmls.i16	q14, <illegal reg q8.5>, d1[3]
│ │  			@ <UNDEFINED> instruction: 0xffd133c5
│ │ -	vrsra.u64	d19, d26, #47
│ │ +			@ <UNDEFINED> instruction: 0xffd133e1
│ │  	vshr.u16	d16, d0, #14
│ │  	b.n	37bcc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x20f444>
│ │  	movs	r0, #32
│ │  	b.n	37c8ce <uniffi_pbcli_checksum_method_api_base@@Base+0x21004a>
│ │  	asrs	r4, r1, #32
│ │  	b.n	37bcd0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20f44c>
│ │  	movs	r0, r0
│ │ @@ -973935,18 +973935,18 @@
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	37c646 <uniffi_pbcli_checksum_method_api_base@@Base+0x20fdc2>
│ │  	beq.n	37c318 <uniffi_pbcli_checksum_method_api_base@@Base+0x20fa94>
│ │  	b.n	37c7a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20ff1c>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r7, r9, sl, ip, lr}
│ │  	vmull.u16	<illegal reg q8.5>, d0, d16
│ │ -			@ <UNDEFINED> instruction: 0xffd06f25
│ │ -	vsubw.u16	<illegal reg q8.5>, q1, d16
│ │ -	vqrdmlah.s16	q11, q9, d5[0]
│ │ -			@ <UNDEFINED> instruction: 0xffd26ed7
│ │ +	vqrdmlsh.s16	q11, q0, d4[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd21347
│ │ +	vqrdmlah.s16	q11, q9, d4[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd26efe
│ │  	vqshrun.s32	d20, q8, #14
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	37c848 <uniffi_pbcli_checksum_method_api_base@@Base+0x20ffc4>
│ │  	beq.n	37c340 <uniffi_pbcli_checksum_method_api_base@@Base+0x20fabc>
│ │  	b.n	37c7cc <uniffi_pbcli_checksum_method_api_base@@Base+0x20ff48>
│ │  	str	r2, [r0, r0]
│ │  	b.n	37c676 <uniffi_pbcli_checksum_method_api_base@@Base+0x20fdf2>
│ │ @@ -974003,16 +974003,16 @@
│ │  	ands	r0, r0
│ │  	b.n	37caee <uniffi_pbcli_checksum_method_api_base@@Base+0x21026a>
│ │  	movs	r4, r0
│ │  	b.n	37c6f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x20fe6e>
│ │  	beq.n	37c3c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x20fb40>
│ │  	b.n	37c84c <uniffi_pbcli_checksum_method_api_base@@Base+0x20ffc8>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r5, r9, sl, fp, sp, lr}
│ │ -	vsubl.u16	<illegal reg q8.5>, d2, d24
│ │ +	ldmia.w	sp!, {r2, r4, r6, r9, sl, fp, sp, lr}
│ │ +	vmlal.u16	<illegal reg q8.5>, d2, d7[1]
│ │  			@ <UNDEFINED> instruction: 0xffd248f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	37c8e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x210060>
│ │  	beq.n	37c48c <uniffi_pbcli_checksum_method_api_base@@Base+0x20fc08>
│ │  	b.n	37c868 <uniffi_pbcli_checksum_method_api_base@@Base+0x20ffe4>
│ │  	movs	r0, r0
│ │  	b.n	37ca72 <uniffi_pbcli_checksum_method_api_base@@Base+0x2101ee>
│ │ @@ -974135,17 +974135,17 @@
│ │  			@ <UNDEFINED> instruction: 0xeaff0005
│ │  	b.n	37c81a <uniffi_pbcli_checksum_method_api_base@@Base+0x20ff96>
│ │  	strb	r4, [r6, #23]
│ │  			@ <UNDEFINED> instruction: 0xebfd0006
│ │  	b.n	37c822 <uniffi_pbcli_checksum_method_api_base@@Base+0x20ff9e>
│ │  	bfcsel	c, 37bcda <uniffi_pbcli_checksum_method_api_base@@Base+0x20f456>, e, hi
│ │  			@ <UNDEFINED> instruction: 0xfff4eaff
│ │ -	ldr	r1, [r1, #80]	@ 0x50
│ │ -	vmull.u16	q12, d2, d12
│ │ -			@ <UNDEFINED> instruction: 0xffd15d15
│ │ +	ldr	r0, [r6, #80]	@ 0x50
│ │ +			@ <UNDEFINED> instruction: 0xffd28c33
│ │ +			@ <UNDEFINED> instruction: 0xffd15d3c
│ │  	vshr.u16	d16, d0, #14
│ │  	b.n	37c038 <uniffi_pbcli_checksum_method_api_base@@Base+0x20f7b4>
│ │  	movs	r0, #32
│ │  	b.n	37cc3e <uniffi_pbcli_checksum_method_api_base@@Base+0x2103ba>
│ │  	asrs	r4, r1, #32
│ │  	b.n	37c040 <uniffi_pbcli_checksum_method_api_base@@Base+0x20f7bc>
│ │  	movs	r0, r0
│ │ @@ -974260,15 +974260,15 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	37cd4e <uniffi_pbcli_checksum_method_api_base@@Base+0x2104ca>
│ │  	movs	r5, r0
│ │  	b.n	37c952 <uniffi_pbcli_checksum_method_api_base@@Base+0x2100ce>
│ │  	beq.n	37c644 <uniffi_pbcli_checksum_method_api_base@@Base+0x20fdc0>
│ │  	b.n	37caac <uniffi_pbcli_checksum_method_api_base@@Base+0x210228>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r2, r3, r5, r8, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r4, r6, r8, sp, lr, pc}
│ │  	vqshlu.s16	d29, d12, #1
│ │  			@ <UNDEFINED> instruction: 0xffd0e92c
│ │  	movs	r3, r2
│ │  	ldr	r7, [pc, #960]	@ (37c9e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x210164>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	37cb48 <uniffi_pbcli_checksum_method_api_base@@Base+0x2102c4>
│ │  	beq.n	37c658 <uniffi_pbcli_checksum_method_api_base@@Base+0x20fdd4>
│ │ @@ -974413,20 +974413,20 @@
│ │  	b.n	37ce9e <uniffi_pbcli_checksum_method_api_base@@Base+0x21061a>
│ │  	movs	r1, r0
│ │  	b.n	37caa2 <uniffi_pbcli_checksum_method_api_base@@Base+0x21021e>
│ │  	beq.n	37c79c <uniffi_pbcli_checksum_method_api_base@@Base+0x20ff18>
│ │  	b.n	37cbfc <uniffi_pbcli_checksum_method_api_base@@Base+0x210378>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r2, r4, r5, r6, r8, sl, fp, ip, sp, lr, pc}
│ │ -	vmull.p8	q9, d15, d2
│ │ +	vmull.p8	q9, d15, d25
│ │  	vabal.u16	<illegal reg q11.5>, d18, d29
│ │ -			@ <UNDEFINED> instruction: 0xffd02e1a
│ │ -	vaddl.u16	q15, d2, d24
│ │ -	vrsra.u64	d21, d13, #47
│ │ -			@ <UNDEFINED> instruction: 0xffd22d92
│ │ +	vqrdmlah.s16	q9, q0, d1[0]
│ │ +	vmla.i16	q15, q1, d7[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd153c4
│ │ +			@ <UNDEFINED> instruction: 0xffd22db9
│ │  	vaddl.u16	q8, d2, d4
│ │  	b.n	37c2c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x20fa44>
│ │  	movs	r0, r0
│ │  	b.n	37c8ac <uniffi_pbcli_checksum_method_api_base@@Base+0x210028>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	b.n	37c6a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x20fe20>
│ │  	movs	r3, r2
│ │ @@ -974718,25 +974718,25 @@
│ │  	b.n	37c55c <uniffi_pbcli_checksum_method_api_base@@Base+0x20fcd8>
│ │  	movs	r5, r0
│ │  	b.n	37cd62 <uniffi_pbcli_checksum_method_api_base@@Base+0x2104de>
│ │  	asrs	r1, r0, #32
│ │  	b.n	37cb44 <uniffi_pbcli_checksum_method_api_base@@Base+0x2102c0>
│ │  			@ <UNDEFINED> instruction: 0xeec2ebfb
│ │  	vpmin.u32	q15, q14, <illegal reg q15.5>
│ │ -	svc	60	@ 0x3c
│ │ +	svc	99	@ 0x63
│ │  	vmlsl.u16	<illegal reg q8.5>, d1, d3[1]
│ │ -			@ <UNDEFINED> instruction: 0xffd1dedc
│ │ +			@ <UNDEFINED> instruction: 0xffd1df03
│ │  	vmls.f16	<illegal reg q8.5>, <illegal reg q8.5>, d3[3]
│ │  	vqshlu.s16	q15, q14, #1
│ │  	movs	r3, r2
│ │ -	ble.n	37ca24 <uniffi_pbcli_checksum_method_api_base@@Base+0x2101a0>
│ │ +	udf	#23
│ │  	vsri.64	<illegal reg q8.5>, <illegal reg q15.5>, #47
│ │  	vsli.64	q15, q6, #17
│ │  	movs	r3, r2
│ │ -	ble.n	37ca90 <uniffi_pbcli_checksum_method_api_base@@Base+0x21020c>
│ │ +	ble.n	37cade <uniffi_pbcli_checksum_method_api_base@@Base+0x21025a>
│ │  	vraddhn.i32	d17, <illegal reg q0.5>, <illegal reg q15.5>
│ │  	vabal.u16	q15, d1, d12
│ │  	movs	r3, r2
│ │  	b.n	37c474 <uniffi_pbcli_checksum_method_api_base@@Base+0x20fbf0>
│ │  	movs	r3, r2
│ │  	movs	r4, r0
│ │  	b.n	37c5a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x20fd1c>
│ │ @@ -975057,26 +975057,26 @@
│ │  	strh	r0, [r0, #0]
│ │  	b.n	37d46e <uniffi_pbcli_checksum_method_api_base@@Base+0x210bea>
│ │  	movs	r0, r1
│ │  	b.n	37d072 <uniffi_pbcli_checksum_method_api_base@@Base+0x2107ee>
│ │  	beq.n	37cd6c <uniffi_pbcli_checksum_method_api_base@@Base+0x2104e8>
│ │  	b.n	37d1cc <uniffi_pbcli_checksum_method_api_base@@Base+0x210948>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r3, ip, sp, pc}
│ │ -	vsubl.u16	<illegal reg q15.5>, d1, d1
│ │ +	ldmia.w	sp!, {r2, r4, r5, ip, sp, pc}
│ │ +	vsubl.u16	<illegal reg q15.5>, d1, d24
│ │  	vmla.i16	q13, <illegal reg q8.5>, d0[3]
│ │  	vmlal.u16	q15, d16, d13
│ │  	vraddhn.i32	d30, q0, q6
│ │  	movs	r3, r2
│ │ -	add	r7, sp, #836	@ 0x344
│ │ -	vmla.f16	<illegal reg q15.5>, <illegal reg q8.5>, d5[0]
│ │ -			@ <UNDEFINED> instruction: 0xffd1af9d
│ │ -	vsra.u64	d31, d1, #47
│ │ +	add	r7, sp, #992	@ 0x3e0
│ │ +	vmla.f16	<illegal reg q15.5>, <illegal reg q8.5>, d4[3]
│ │ +	vqrdmlsh.s16	q13, <illegal reg q8.5>, d4[0]
│ │ +	vsra.u64	d31, d24, #47
│ │  			@ <UNDEFINED> instruction: 0xffd12903
│ │ -	vrshr.u16	q12, <illegal reg q3.5>, #16
│ │ +	vrshr.u16	q12, q15, #16
│ │  	vqshlu.s16	d16, d8, #1
│ │  	movs	r6, r2
│ │  	movs	r4, r0
│ │  	b.n	37c8ac <uniffi_pbcli_checksum_method_api_base@@Base+0x210028>
│ │  	movs	r0, r0
│ │  	b.n	37ce90 <uniffi_pbcli_checksum_method_api_base@@Base+0x21060c>
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -975391,26 +975391,26 @@
│ │  	b.n	37d74e <uniffi_pbcli_checksum_method_api_base@@Base+0x210eca>
│ │  	movs	r5, r0
│ │  	b.n	37d352 <uniffi_pbcli_checksum_method_api_base@@Base+0x210ace>
│ │  	beq.n	37d04c <uniffi_pbcli_checksum_method_api_base@@Base+0x2107c8>
│ │  	b.n	37d4ac <uniffi_pbcli_checksum_method_api_base@@Base+0x210c28>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r3, r4, r5, r6, r9, sl, fp, lr, pc}
│ │ -	vabdl.u16	q9, d0, d14
│ │ -	vqrdmlsh.s16	q15, q9, d2[3]
│ │ +	vqshl.u16	d18, d21, #0
│ │ +	vshr.u16	d31, d1, #14
│ │  			@ <UNDEFINED> instruction: 0xffd19e93
│ │  	vsri.16	d28, d5, #16
│ │ -	vqshlu.s8	q9, q9, #7
│ │ +	vqshlu.s64	d18, d9, #15
│ │  			@ <UNDEFINED> instruction: 0xffd26d03
│ │ -			@ <UNDEFINED> instruction: 0xffd0d7c3
│ │ -	vmlal.u16	<illegal reg q8.5>, d17, d1[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd0d7ea
│ │ +	vrshr.u64	<illegal reg q8.5>, q8, #47
│ │  	vqdmulh.s16	<illegal reg q12.5>, q1, d7[3]
│ │ -	vrsubhn.i32	d27, q0, q5
│ │ -			@ <UNDEFINED> instruction: 0xffd1abe6
│ │ -	vsri.64	q9, q13, #47
│ │ +	vqshlu.s16	d27, d17, #0
│ │ +	vmull.u16	q13, d1, d13
│ │ +	vabal.u16	q9, d1, d17
│ │  			@ <UNDEFINED> instruction: 0xffd20e5c
│ │  			@ <UNDEFINED> instruction: 0xffd14c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	37d574 <uniffi_pbcli_checksum_method_api_base@@Base+0x210cf0>
│ │  	movs	r0, r0
│ │  	b.n	37d700 <uniffi_pbcli_checksum_method_api_base@@Base+0x210e7c>
│ │  	movs	r0, r0
│ │ @@ -975476,15 +975476,15 @@
│ │  	movs	r4, r0
│ │  	b.n	37d426 <uniffi_pbcli_checksum_method_api_base@@Base+0x210ba2>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {}
│ │  	b.n	37d82e <uniffi_pbcli_checksum_method_api_base@@Base+0x210faa>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, fp, ip, sp}
│ │ -			@ <UNDEFINED> instruction: 0xffd11b67
│ │ +			@ <UNDEFINED> instruction: 0xffd11b8e
│ │  			@ <UNDEFINED> instruction: 0xffd23bb8
│ │  	vqshrun.s32	d20, q8, #15
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	37d620 <uniffi_pbcli_checksum_method_api_base@@Base+0x210d9c>
│ │  	movs	r0, r0
│ │  	b.n	37d7ae <uniffi_pbcli_checksum_method_api_base@@Base+0x210f2a>
│ │  	movs	r6, r3
│ │ @@ -975585,19 +975585,19 @@
│ │  	movs	r0, #0
│ │  	b.n	37d926 <uniffi_pbcli_checksum_method_api_base@@Base+0x2110a2>
│ │  	str	r3, [r4, #120]	@ 0x78
│ │  			@ <UNDEFINED> instruction: 0xebfd0005
│ │  	b.n	37d52e <uniffi_pbcli_checksum_method_api_base@@Base+0x210caa>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r2, r4, r6, r7, r9, fp, ip, sp}
│ │ -	vsra.u16	d19, d7, #15
│ │ +	vsra.u16	d19, d30, #15
│ │  	vmlsl.u16	<illegal reg q9.5>, d18, d24
│ │ -	vmla.i16	<illegal reg q9.5>, <illegal reg q8.5>, d3[3]
│ │ +	vsra.u16	d19, d2, #15
│ │  			@ <UNDEFINED> instruction: 0xffd23b18
│ │ -	vsra.u16	<illegal reg q9.5>, <illegal reg q5.5>, #15
│ │ +	vaddw.u16	<illegal reg q9.5>, <illegal reg q8.5>, d2
│ │  			@ <UNDEFINED> instruction: 0xffd24c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	37d72c <uniffi_pbcli_checksum_method_api_base@@Base+0x210ea8>
│ │  	ands	r2, r0
│ │  	b.n	37d556 <uniffi_pbcli_checksum_method_api_base@@Base+0x210cd2>
│ │  	str	r1, [r0, r0]
│ │  	b.n	37d55a <uniffi_pbcli_checksum_method_api_base@@Base+0x210cd6>
│ │ @@ -975810,15 +975810,15 @@
│ │  	b.n	37db26 <uniffi_pbcli_checksum_method_api_base@@Base+0x2112a2>
│ │  	str	r3, [r4, #112]	@ 0x70
│ │  			@ <UNDEFINED> instruction: 0xebfdffdd
│ │  			@ <UNDEFINED> instruction: 0xeaffe1b3
│ │  	vmla.f16	q15, q0, d3[3]
│ │  	vmla.f16	q15, q0, d3[1]
│ │  	vmla.i16	q15, q0, d3[3]
│ │ -	vmlal.u16	<illegal reg q8.5>, d0, d31
│ │ +	vqrshrun.s32	d17, q3, #16
│ │  	vshr.u64	d30, d19, #46
│ │  			@ <UNDEFINED> instruction: 0xffd0ff90
│ │  			@ <UNDEFINED> instruction: 0xeaff0000
│ │  	b.n	37daae <uniffi_pbcli_checksum_method_api_base@@Base+0x21122a>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (37d4d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x210c50>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │ @@ -976050,15 +976050,15 @@
│ │  	b.n	37d740 <uniffi_pbcli_checksum_method_api_base@@Base+0x210ebc>
│ │  	ldrb	r1, [r5, #24]
│ │  			@ <UNDEFINED> instruction: 0xebfe0005
│ │  	b.n	37d96a <uniffi_pbcli_checksum_method_api_base@@Base+0x2110e6>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r1, r5, r7, r9, sl, fp, ip, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd0de57
│ │ -	vsra.u16	<illegal reg q14.5>, q5, #16
│ │ +	vaddw.u16	<illegal reg q14.5>, q8, d1
│ │  	vqrdmlsh.s16	q11, <illegal reg q0.5>, d0[3]
│ │  			@ <UNDEFINED> instruction: 0xffd1de17
│ │  			@ <UNDEFINED> instruction: 0xffd04c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	37db64 <uniffi_pbcli_checksum_method_api_base@@Base+0x2112e0>
│ │  	movs	r0, r0
│ │  	b.n	37dcf0 <uniffi_pbcli_checksum_method_api_base@@Base+0x21146c>
│ │ @@ -976122,15 +976122,15 @@
│ │  	movs	r4, r0
│ │  	b.n	37da12 <uniffi_pbcli_checksum_method_api_base@@Base+0x21118e>
│ │  	movs	r7, #240	@ 0xf0
│ │  			@ <UNDEFINED> instruction: 0xebfc0006
│ │  	b.n	37da1a <uniffi_pbcli_checksum_method_api_base@@Base+0x211196>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r1, r2, r7, r8, sl, fp, ip, lr, pc}
│ │ -	vmls.f16	q13, q8, d7[1]
│ │ +	vsli.64	q13, q11, #16
│ │  			@ <UNDEFINED> instruction: 0xffd14c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	37dc08 <uniffi_pbcli_checksum_method_api_base@@Base+0x211384>
│ │  	beq.n	37d700 <uniffi_pbcli_checksum_method_api_base@@Base+0x210e7c>
│ │  	b.n	37db8c <uniffi_pbcli_checksum_method_api_base@@Base+0x211308>
│ │  	movs	r0, r0
│ │  	b.n	37dd98 <uniffi_pbcli_checksum_method_api_base@@Base+0x211514>
│ │ @@ -976319,21 +976319,21 @@
│ │  	str	r5, [r7, #88]	@ 0x58
│ │  			@ <UNDEFINED> instruction: 0xebfd0022
│ │  	b.n	37dfd2 <uniffi_pbcli_checksum_method_api_base@@Base+0x21174e>
│ │  	asrs	r5, r4, #1
│ │  	b.n	37dfd6 <uniffi_pbcli_checksum_method_api_base@@Base+0x211752>
│ │  			@ <UNDEFINED> instruction: 0xffd9eaff
│ │  	bgt.n	37d83a <uniffi_pbcli_checksum_method_api_base@@Base+0x210fb6>
│ │ -			@ <UNDEFINED> instruction: 0xffd0fe52
│ │ +			@ <UNDEFINED> instruction: 0xffd0fe79
│ │  	vqdmulh.s16	<illegal reg q14.5>, <illegal reg q0.5>, d7[1]
│ │ -			@ <UNDEFINED> instruction: 0xffd0fdd2
│ │ +			@ <UNDEFINED> instruction: 0xffd0fdf9
│ │  			@ <UNDEFINED> instruction: 0xffd1dc7b
│ │ -			@ <UNDEFINED> instruction: 0xffd0fdfe
│ │ +	vmull.p<illegal width 16>	<illegal reg q15.5>, d0, d21
│ │  			@ <UNDEFINED> instruction: 0xffd1dbb3
│ │ -			@ <UNDEFINED> instruction: 0xffd0fd36
│ │ +			@ <UNDEFINED> instruction: 0xffd0fd5d
│ │  			@ <UNDEFINED> instruction: 0xffd14bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	37dddc <uniffi_pbcli_checksum_method_api_base@@Base+0x211558>
│ │  	movs	r0, r0
│ │  	b.n	37df68 <uniffi_pbcli_checksum_method_api_base@@Base+0x2116e4>
│ │  	movs	r0, r4
│ │  	lsrs	r0, r0, #8
│ │ @@ -976428,15 +976428,15 @@
│ │  			@ <UNDEFINED> instruction: 0xebfd0005
│ │  	b.n	37dcd6 <uniffi_pbcli_checksum_method_api_base@@Base+0x211452>
│ │  	movs	r7, #63	@ 0x3f
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	37dcde <uniffi_pbcli_checksum_method_api_base@@Base+0x21145a>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r7, r9, fp, ip, lr, pc}
│ │ -	vsubw.u16	q13, q0, d7
│ │ +	vsubw.u16	q13, q0, d30
│ │  			@ <UNDEFINED> instruction: 0xffd1daf7
│ │  			@ <UNDEFINED> instruction: 0xffd04c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	37ded0 <uniffi_pbcli_checksum_method_api_base@@Base+0x21164c>
│ │  	beq.n	37d9c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x211144>
│ │  	b.n	37de54 <uniffi_pbcli_checksum_method_api_base@@Base+0x2115d0>
│ │  	str	r0, [r1, #0]
│ │ @@ -976632,28 +976632,28 @@
│ │  	b.n	37dff0 <uniffi_pbcli_checksum_method_api_base@@Base+0x21176c>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {}
│ │  	b.n	37e2a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x211a1e>
│ │  			@ <UNDEFINED> instruction: 0xfff8eaff
│ │  	push	{r2, r3, r6, lr}
│ │  			@ <UNDEFINED> instruction: 0xffd00b9f
│ │ -			@ <UNDEFINED> instruction: 0xffd1cd14
│ │ +			@ <UNDEFINED> instruction: 0xffd1cd3b
│ │  	vsubl.u16	<illegal reg q9.5>, d17, d26
│ │  			@ <UNDEFINED> instruction: 0xffd05b95
│ │  	vsli.64	<illegal reg q8.5>, q10, #16
│ │  	vqdmulh.s16	<illegal reg q12.5>, q8, d0[3]
│ │  	vrsra.u64	<illegal reg q10.5>, q3, #48
│ │  	vqrshrun.s32	d21, <illegal reg q4.5>, #16
│ │  	vabdl.u16	<illegal reg q10.5>, d16, d1
│ │  	vsri.16	d17, d18, #15
│ │  	vqrshrn.u32	d30, <illegal reg q9.5>, #15
│ │  	vqshrn.u32	d29, <illegal reg q11.5>, #16
│ │  	vrsra.u16	d16, d13, #16
│ │  			@ <UNDEFINED> instruction: 0xffd01ad3
│ │ -	vraddhn.i32	d23, q0, <illegal reg q11.5>
│ │ +	vmls.i16	<illegal reg q11.5>, q0, d6[1]
│ │  	vqshrun.s32	d20, q8, #15
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	37e0c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x211844>
│ │  	beq.n	37dbc0 <uniffi_pbcli_checksum_method_api_base@@Base+0x21133c>
│ │  	b.n	37e04c <uniffi_pbcli_checksum_method_api_base@@Base+0x2117c8>
│ │  	str	r1, [r0, r0]
│ │  	b.n	37def6 <uniffi_pbcli_checksum_method_api_base@@Base+0x211672>
│ │ @@ -976692,15 +976692,15 @@
│ │  	str	r6, [r4, #60]	@ 0x3c
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	37e342 <uniffi_pbcli_checksum_method_api_base@@Base+0x211abe>
│ │  	beq.n	37dc14 <uniffi_pbcli_checksum_method_api_base@@Base+0x211390>
│ │  	b.n	37e09c <uniffi_pbcli_checksum_method_api_base@@Base+0x211818>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r1, r2, r4, r9, fp, ip}
│ │ -			@ <UNDEFINED> instruction: 0xffd0736b
│ │ +	vrsra.u64	d23, d2, #48
│ │  			@ <UNDEFINED> instruction: 0xffd14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	37e134 <uniffi_pbcli_checksum_method_api_base@@Base+0x2118b0>
│ │  	beq.n	37dc24 <uniffi_pbcli_checksum_method_api_base@@Base+0x2113a0>
│ │  	b.n	37e0b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x211834>
│ │  	asrs	r4, r5, #17
│ │  	b.n	37d760 <uniffi_pbcli_checksum_method_api_base@@Base+0x210edc>
│ │ @@ -978162,21 +978162,21 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	37e9c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x212144>
│ │  	ldrb	r3, [r3, #31]
│ │  			@ <UNDEFINED> instruction: 0xebfed010
│ │  	b.n	37ed48 <uniffi_pbcli_checksum_method_api_base@@Base+0x2124c4>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r3, r5, r6, r8, r9, fp, sp, pc}
│ │ -	vqrshrn.u16	d26, q8, #1
│ │ -	vmul.f16	q13, <illegal reg q0.5>, d0[0]
│ │ -	vqshrn.u32	d26, q0, #15
│ │ -	vmul.i16	q13, <illegal reg q8.5>, d0[2]
│ │ -			@ <UNDEFINED> instruction: 0xffd1a8b0
│ │ -	vmlal.u16	q13, d17, d0
│ │ -	vqrshrun.s32	d26, q0, #15
│ │ +			@ <UNDEFINED> instruction: 0xffcfa997
│ │ +	vmul.f16	q13, <illegal reg q0.5>, d7[2]
│ │ +	vqshrn.u32	d26, <illegal reg q11.5>, #15
│ │ +			@ <UNDEFINED> instruction: 0xffd1a907
│ │ +			@ <UNDEFINED> instruction: 0xffd1a8d7
│ │ +	vmlal.u16	q13, d17, d23
│ │ +	vqrshrun.s32	d26, <illegal reg q11.5>, #15
│ │  			@ <UNDEFINED> instruction: 0xffd13c9f
│ │  			@ <UNDEFINED> instruction: 0xffd039fe
│ │  			@ <UNDEFINED> instruction: 0xffd1cb8f
│ │  			@ <UNDEFINED> instruction: 0xffd04c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	37ee04 <uniffi_pbcli_checksum_method_api_base@@Base+0x212580>
│ │  	beq.n	37e90c <uniffi_pbcli_checksum_method_api_base@@Base+0x212088>
│ │ @@ -978759,19 +978759,19 @@
│ │  	b.n	37f0a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x21281c>
│ │  			@ <UNDEFINED> instruction: 0xffecbaff
│ │  	movs	r1, r0
│ │  	b.n	37f53a <uniffi_pbcli_checksum_method_api_base@@Base+0x212cb6>
│ │  	beq.n	37ee34 <uniffi_pbcli_checksum_method_api_base@@Base+0x2125b0>
│ │  	b.n	37f294 <uniffi_pbcli_checksum_method_api_base@@Base+0x212a10>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r4, r5, r7, r8, sl, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffd2074e
│ │ -	vqshl.u64	<illegal reg q12.5>, q5, #18
│ │ -	vmls.f16	q11, <illegal reg q0.5>, d6[2]
│ │ -	vabdl.u16	q8, d2, d6
│ │ +	ldmia.w	sp!, {r0, r3, r4, r6, r7, r8, sl, sp, lr}
│ │ +	vqshl.u16	q8, <illegal reg q10.5>, #2
│ │ +	vmlal.u16	<illegal reg q12.5>, d2, d1
│ │ +	vabal.u16	q11, d17, d13
│ │ +	vabdl.u16	q8, d2, d29
│ │  			@ <UNDEFINED> instruction: 0xffd24bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	37f338 <uniffi_pbcli_checksum_method_api_base@@Base+0x212ab4>
│ │  	stmia	r0!, {}
│ │  	b.n	37f562 <uniffi_pbcli_checksum_method_api_base@@Base+0x212cde>
│ │  	movs	r3, r0
│ │  	b.n	37f0c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x212844>
│ │ @@ -979554,16 +979554,16 @@
│ │  	b.n	37f7ee <uniffi_pbcli_checksum_method_api_base@@Base+0x212f6a>
│ │  	movs	r0, r0
│ │  	b.n	37f4b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x212c30>
│ │  	movs	r1, r0
│ │  	b.n	37fb56 <uniffi_pbcli_checksum_method_api_base@@Base+0x2132d2>
│ │  			@ <UNDEFINED> instruction: 0xffea0aff
│ │  	vpmin.u8	q15, <illegal reg q9.5>, <illegal reg q15.5>
│ │ -	push	{r0, r6, r7, lr}
│ │ -	vmlal.u16	<illegal reg q13.5>, d17, d1[3]
│ │ +	push	{r3, r5, r6, r7, lr}
│ │ +	vrsra.u16	d27, d0, #15
│ │  			@ <UNDEFINED> instruction: 0xffd14c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	37f9e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x213164>
│ │  	ands	r0, r1
│ │  	b.n	37f008 <uniffi_pbcli_checksum_method_api_base@@Base+0x212784>
│ │  	stmia	r0!, {r0}
│ │  	b.n	37f816 <uniffi_pbcli_checksum_method_api_base@@Base+0x212f92>
│ │ @@ -980394,15 +980394,15 @@
│ │  	b.n	37ff5e <uniffi_pbcli_checksum_method_api_base@@Base+0x2136da>
│ │  	ldr	r3, [r4, #0]
│ │  			@ <UNDEFINED> instruction: 0xebfd0006
│ │  	b.n	37ff66 <uniffi_pbcli_checksum_method_api_base@@Base+0x2136e2>
│ │  	beq.n	37fc48 <uniffi_pbcli_checksum_method_api_base@@Base+0x2133c4>
│ │  	b.n	3800c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x21383c>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r5, r6, r8, sl, sp}
│ │ +	ldmia.w	sp!, {r3, r7, r8, sl, sp}
│ │  	vaddl.u16	q8, d2, d24
│ │  	b.n	37f756 <uniffi_pbcli_checksum_method_api_base@@Base+0x212ed2>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r4, r0
│ │  	b.n	38013e <uniffi_pbcli_checksum_method_api_base@@Base+0x2138ba>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r4, [pc, #448]	@ (37fe04 <uniffi_pbcli_checksum_method_api_base@@Base+0x213580>)
│ │ @@ -980893,15 +980893,15 @@
│ │  	movs	r0, #0
│ │  	b.n	3807ea <uniffi_pbcli_checksum_method_api_base@@Base+0x213f66>
│ │  	ldrh	r2, [r6, r7]
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	3807f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x213f6e>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r0, r1, r4, r6, r7, r8, r9, ip, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd0ebb1
│ │ +			@ <UNDEFINED> instruction: 0xffd0ebd8
│ │  			@ <UNDEFINED> instruction: 0xffd14c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3805e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x213d5c>
│ │  	movs	r0, r0
│ │  	b.n	38076a <uniffi_pbcli_checksum_method_api_base@@Base+0x213ee6>
│ │  	movs	r1, r3
│ │  	lsrs	r0, r0, #8
│ │ @@ -981796,15 +981796,15 @@
│ │  	vrhadd.u16	d14, d14, d31
│ │  	str	r3, [sp, #644]	@ 0x284
│ │  	vaddl.u16	q8, d0, d4
│ │  	b.n	3803f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x213b6c>
│ │  	movs	r0, r0
│ │  	b.n	3809d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x214150>
│ │  	vrhadd.u16	d14, d14, d31
│ │ -	b.n	381014 <uniffi_pbcli_checksum_method_api_base@@Base+0x214790>
│ │ +	b.n	381062 <uniffi_pbcli_checksum_method_api_base@@Base+0x2147de>
│ │  	vaddl.u16	q8, d1, d4
│ │  	b.n	380400 <uniffi_pbcli_checksum_method_api_base@@Base+0x213b7c>
│ │  	movs	r0, r0
│ │  	b.n	3809e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x214160>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldrh	r1, [r5, #20]
│ │  	vaddl.u8	q8, d15, d4
│ │ @@ -982117,18 +982117,18 @@
│ │  	b.n	380ee2 <uniffi_pbcli_checksum_method_api_base@@Base+0x21465e>
│ │  	movs	r0, #222	@ 0xde
│ │  	b.n	3812e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x214a62>
│ │  	strb	r0, [r1, #3]
│ │  			@ <UNDEFINED> instruction: 0xebfe0006
│ │  	b.n	380eee <uniffi_pbcli_checksum_method_api_base@@Base+0x21466a>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r6, r7, r9, sl, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r5, r6, r7, r9, sl, pc}
│ │  	vaddw.u16	q8, <illegal reg q0.5>, d24
│ │  	movs	r0, r0
│ │ -	strh	r1, [r5, #46]	@ 0x2e
│ │ +	strh	r0, [r2, #48]	@ 0x30
│ │  	vsra.u16	q11, q2, #15
│ │  	vaddl.u16	q9, d0, d0
│ │  	b.n	3806e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x213e62>
│ │  	asrs	r0, r0, #32
│ │  	b.n	3806ec <uniffi_pbcli_checksum_method_api_base@@Base+0x213e68>
│ │  	adds	r0, #0
│ │  	b.n	3806f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x213e6e>
│ │ @@ -982283,18 +982283,18 @@
│ │  	b.n	38106a <uniffi_pbcli_checksum_method_api_base@@Base+0x2147e6>
│ │  	movs	r0, #253	@ 0xfd
│ │  	b.n	38146e <uniffi_pbcli_checksum_method_api_base@@Base+0x214bea>
│ │  	asrs	r1, r0, #32
│ │  	b.n	380e50 <uniffi_pbcli_checksum_method_api_base@@Base+0x2145cc>
│ │  	ldr	r5, [pc, #960]	@ (3810f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x214870>)
│ │  	ldmia.w	sp!, {r2, r5, r6, ip, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xeafe84d5
│ │ +			@ <UNDEFINED> instruction: 0xeafe84fc
│ │  	vqshrun.s32	d28, q0, #15
│ │  	movs	r5, r2
│ │ -	strh	r1, [r2, #32]
│ │ +	strh	r0, [r7, #32]
│ │  			@ <UNDEFINED> instruction: 0xffd14c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	381268 <uniffi_pbcli_checksum_method_api_base@@Base+0x2149e4>
│ │  	ands	r0, r0
│ │  	b.n	381092 <uniffi_pbcli_checksum_method_api_base@@Base+0x21480e>
│ │  	movs	r0, r0
│ │  	b.n	3813f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x214b72>
│ │ @@ -982323,15 +982323,15 @@
│ │  	b.n	3810ca <uniffi_pbcli_checksum_method_api_base@@Base+0x214846>
│ │  	movs	r2, #19
│ │  	b.n	38138e <uniffi_pbcli_checksum_method_api_base@@Base+0x214b0a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	380eb0 <uniffi_pbcli_checksum_method_api_base@@Base+0x21462c>
│ │  	ldr	r4, [pc, #64]	@ (380dd4 <uniffi_pbcli_checksum_method_api_base@@Base+0x214550>)
│ │  	ldmia.w	sp!, {r2, r3, r6, ip, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xeafe83b1
│ │ +			@ <UNDEFINED> instruction: 0xeafe83d8
│ │  	vmla.i16	q8, <illegal reg q0.5>, d0[1]
│ │  	b.n	3812a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x214a1e>
│ │  	subs	r7, r3, #6
│ │  	b.n	3810c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x214842>
│ │  	movs	r0, #1
│ │  	b.n	3812ac <uniffi_pbcli_checksum_method_api_base@@Base+0x214a28>
│ │  	subs	r7, #146	@ 0x92
│ │ @@ -982510,21 +982510,21 @@
│ │  	b.n	38166e <uniffi_pbcli_checksum_method_api_base@@Base+0x214dea>
│ │  	ands	r0, r0
│ │  	b.n	381672 <uniffi_pbcli_checksum_method_api_base@@Base+0x214dee>
│ │  	ldr	r0, [r2, r1]
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	38127a <uniffi_pbcli_checksum_method_api_base@@Base+0x2149f6>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r2, r4, r8, r9, pc}
│ │ -	vmlal.u16	q12, d1, d5[0]
│ │ -	vsubl.u16	q12, d1, d29
│ │ -	vrshr.u16	d24, d31, #15
│ │ -	vrshr.u64	d24, d17, #47
│ │ -	vmlal.u16	q12, d17, d3[0]
│ │ -	vmlal.u16	q12, d1, d5[2]
│ │ +	ldmia.w	sp!, {r2, r3, r4, r5, r8, r9, pc}
│ │ +	vmlal.u16	q12, d1, d4[3]
│ │ +	vrshr.u16	q12, q2, #15
│ │ +	vmlal.u16	q12, d1, d6[2]
│ │ +	vrshr.u64	q12, q4, #47
│ │ +	vmlal.u16	q12, d17, d2[3]
│ │ +	vsubl.u16	q12, d17, d12
│ │  			@ <UNDEFINED> instruction: 0xffd14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	38147c <uniffi_pbcli_checksum_method_api_base@@Base+0x214bf8>
│ │  	svc	103	@ 0x67
│ │  	b.n	381400 <uniffi_pbcli_checksum_method_api_base@@Base+0x214b7c>
│ │  	str	r0, [sp, #0]
│ │  	b.n	380a8a <uniffi_pbcli_checksum_method_api_base@@Base+0x214206>
│ │ @@ -982806,16 +982806,16 @@
│ │  	b.n	381852 <uniffi_pbcli_checksum_method_api_base@@Base+0x214fce>
│ │  	movs	r0, #0
│ │  	b.n	381916 <uniffi_pbcli_checksum_method_api_base@@Base+0x215092>
│ │  	ldrsb	r7, [r4, r6]
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	38191e <uniffi_pbcli_checksum_method_api_base@@Base+0x21509a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r7, r8, r9, sl, fp, ip, sp, lr}
│ │ -	vsri.16	d28, d13, #15
│ │ +	ldmia.w	sp!, {r2, r3, r5, r7, r8, r9, sl, fp, ip, sp, lr}
│ │ +	vmls.i16	q14, <illegal reg q0.5>, d4[0]
│ │  			@ <UNDEFINED> instruction: 0xffd14df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	38170c <uniffi_pbcli_checksum_method_api_base@@Base+0x214e88>
│ │  	str	r0, [r0, r0]
│ │  	b.n	381936 <uniffi_pbcli_checksum_method_api_base@@Base+0x2150b2>
│ │  	movs	r0, r0
│ │  	b.n	38189c <uniffi_pbcli_checksum_method_api_base@@Base+0x215018>
│ │ @@ -982937,16 +982937,16 @@
│ │  	b.n	380e2a <uniffi_pbcli_checksum_method_api_base@@Base+0x2145a6>
│ │  	adds	r0, #93	@ 0x5d
│ │  			@ <UNDEFINED> instruction: 0xeb00ffe7
│ │  			@ <UNDEFINED> instruction: 0xeaff0004
│ │  	b.n	380e36 <uniffi_pbcli_checksum_method_api_base@@Base+0x2145b2>
│ │  	movs	r4, #236	@ 0xec
│ │  			@ <UNDEFINED> instruction: 0xeb00ffe4
│ │ -			@ <UNDEFINED> instruction: 0xeaff7f31
│ │ -	vmull.p<illegal width 16>	<illegal reg q11.5>, d17, d9
│ │ +			@ <UNDEFINED> instruction: 0xeaff7f58
│ │ +			@ <UNDEFINED> instruction: 0xffd17eb0
│ │  			@ <UNDEFINED> instruction: 0xffd14c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	381840 <uniffi_pbcli_checksum_method_api_base@@Base+0x214fbc>
│ │  	movs	r0, #1
│ │  	b.n	381a6a <uniffi_pbcli_checksum_method_api_base@@Base+0x2151e6>
│ │  	ands	r1, r0
│ │  	b.n	381a6e <uniffi_pbcli_checksum_method_api_base@@Base+0x2151ea>
│ │ @@ -982980,16 +982980,16 @@
│ │  	b.n	381aae <uniffi_pbcli_checksum_method_api_base@@Base+0x21522a>
│ │  	ands	r0, r0
│ │  	b.n	381ab2 <uniffi_pbcli_checksum_method_api_base@@Base+0x21522e>
│ │  	ldrsb	r0, [r0, r5]
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3816ba <uniffi_pbcli_checksum_method_api_base@@Base+0x214e36>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r5, r6, r7, r8, sl, fp, ip, sp, lr}
│ │ -	vrshr.u64	d28, d9, #47
│ │ +	ldmia.w	sp!, {r2, r4, r9, sl, fp, ip, sp, lr}
│ │ +	vmlal.u16	q14, d17, d0[0]
│ │  			@ <UNDEFINED> instruction: 0xffd14c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3818a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x215024>
│ │  	str	r0, [r0, #0]
│ │  	b.n	381ad2 <uniffi_pbcli_checksum_method_api_base@@Base+0x21524e>
│ │  	movs	r0, r0
│ │  	b.n	381a36 <uniffi_pbcli_checksum_method_api_base@@Base+0x2151b2>
│ │ @@ -983380,17 +983380,17 @@
│ │  	strh	r0, [r0, #40]	@ 0x28
│ │  			@ <UNDEFINED> instruction: 0xebff4000
│ │  	b.n	381a46 <uniffi_pbcli_checksum_method_api_base@@Base+0x2151c2>
│ │  			@ <UNDEFINED> instruction: 0xffc8eaff
│ │  	ands	r0, r0
│ │  	b.n	381e4e <uniffi_pbcli_checksum_method_api_base@@Base+0x2155ca>
│ │  			@ <UNDEFINED> instruction: 0xffc6eaff
│ │ -	ldrb	r1, [r0, #14]
│ │ -			@ <UNDEFINED> instruction: 0xffd17a51
│ │ -			@ <UNDEFINED> instruction: 0xffd17abd
│ │ +	ldrb	r0, [r5, #14]
│ │ +			@ <UNDEFINED> instruction: 0xffd17a78
│ │ +	vmull.u16	<illegal reg q11.5>, d17, d4[2]
│ │  			@ <UNDEFINED> instruction: 0xffd14df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	381c40 <uniffi_pbcli_checksum_method_api_base@@Base+0x2153bc>
│ │  	beq.n	381668 <uniffi_pbcli_checksum_method_api_base@@Base+0x214de4>
│ │  	b.n	381bc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x215340>
│ │  	str	r1, [r0, r0]
│ │  	b.n	381a6e <uniffi_pbcli_checksum_method_api_base@@Base+0x2151ea>
│ │ @@ -983592,17 +983592,17 @@
│ │  	b.n	381428 <uniffi_pbcli_checksum_method_api_base@@Base+0x214ba4>
│ │  	movs	r4, r0
│ │  	b.n	381c2e <uniffi_pbcli_checksum_method_api_base@@Base+0x2153aa>
│ │  	asrs	r1, r0, #32
│ │  	b.n	381830 <uniffi_pbcli_checksum_method_api_base@@Base+0x214fac>
│ │  	strh	r7, [r0, #52]	@ 0x34
│ │  			@ <UNDEFINED> instruction: 0xebffffef
│ │ -			@ <UNDEFINED> instruction: 0xeaff79f9
│ │ -			@ <UNDEFINED> instruction: 0xffd17895
│ │ -	vmul.f16	<illegal reg q11.5>, <illegal reg q0.5>, d1[2]
│ │ +			@ <UNDEFINED> instruction: 0xeaff7a20
│ │ +			@ <UNDEFINED> instruction: 0xffd178bc
│ │ +			@ <UNDEFINED> instruction: 0xffd17988
│ │  	vmlsl.u16	<illegal reg q13.5>, d17, d20
│ │  	movs	r5, r2
│ │  	ldr	r5, [pc, #960]	@ (381ccc <uniffi_pbcli_checksum_method_api_base@@Base+0x215448>)
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	381e2c <uniffi_pbcli_checksum_method_api_base@@Base+0x2155a8>
│ │  	str	r1, [r0, r0]
│ │  	b.n	381c56 <uniffi_pbcli_checksum_method_api_base@@Base+0x2153d2>
│ │ @@ -984022,18 +984022,18 @@
│ │  	b.n	3823f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x215b72>
│ │  	movs	r0, r0
│ │  	b.n	3817ca <uniffi_pbcli_checksum_method_api_base@@Base+0x214f46>
│ │  	movs	r0, r0
│ │  	b.n	38235e <uniffi_pbcli_checksum_method_api_base@@Base+0x215ada>
│ │  			@ <UNDEFINED> instruction: 0xfff21aff
│ │  			@ <UNDEFINED> instruction: 0xfff6eaff
│ │ -	strb	r1, [r4, #28]
│ │ -	vrsubhn.i32	d23, <illegal reg q0.5>, <illegal reg q4.5>
│ │ -	vrsubhn.i32	d23, <illegal reg q8.5>, <illegal reg q0.5>
│ │ -	vmls.f16	<illegal reg q11.5>, <illegal reg q8.5>, d1[2]
│ │ +	strb	r0, [r1, #29]
│ │ +	vqshlu.s16	d23, d16, #1
│ │ +	vrsubhn.i32	d23, <illegal reg q8.5>, q12
│ │ +	vrsubhn.i32	d23, <illegal reg q0.5>, q4
│ │  	vsri.64	<illegal reg q14.5>, q2, #47
│ │  	bmi.n	381c82 <uniffi_pbcli_checksum_method_api_base@@Base+0x2153fe>
│ │  	bmi.n	381c84 <uniffi_pbcli_checksum_method_api_base@@Base+0x215400>
│ │  	bmi.n	381c86 <uniffi_pbcli_checksum_method_api_base@@Base+0x215402>
│ │  	bmi.n	381c88 <uniffi_pbcli_checksum_method_api_base@@Base+0x215404>
│ │  	bmi.n	381c8a <uniffi_pbcli_checksum_method_api_base@@Base+0x215406>
│ │  	ldr	r7, [pc, #960]	@ (3820a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x215820>)
│ │ @@ -984572,17 +984572,17 @@
│ │  	b.n	3827ca <uniffi_pbcli_checksum_method_api_base@@Base+0x215f46>
│ │  	blx	7827cc <uniffi_pbcli_checksum_method_api_base@@Base+0x615f48>
│ │  	blx	7827d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x615f4c>
│ │  	...
│ │  	movs	r1, r0
│ │  	movs	r0, r0
│ │  	subs	r1, r5, r3
│ │ -			@ <UNDEFINED> instruction: 0xffd12742
│ │ +			@ <UNDEFINED> instruction: 0xffd12769
│ │  			@ <UNDEFINED> instruction: 0xffd21b55
│ │ -	vqrdmulh.s16	<illegal reg q12.5>, <illegal reg q8.5>, d0[0]
│ │ +	vqrdmulh.s16	<illegal reg q12.5>, <illegal reg q8.5>, d7[2]
│ │  			@ <UNDEFINED> instruction: 0xffd11b79
│ │  	vshr.u16	d16, d0, #15
│ │  	b.n	381cda <uniffi_pbcli_checksum_method_api_base@@Base+0x215456>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r0, r0
│ │  	b.n	381ce2 <uniffi_pbcli_checksum_method_api_base@@Base+0x21545e>
│ │  	cbz	r2, 38223a <uniffi_pbcli_checksum_method_api_base@@Base+0x2159b6>
│ │ @@ -984916,19 +984916,19 @@
│ │  	blx	782aec <uniffi_pbcli_checksum_method_api_base@@Base+0x616268>
│ │  	blx	782af0 <uniffi_pbcli_checksum_method_api_base@@Base+0x61626c>
│ │  	...
│ │  			@ <UNDEFINED> instruction: 0xffffffff
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │  	cbnz	r1, 382510 <uniffi_pbcli_checksum_method_api_base@@Base+0x215c8c>
│ │ -	vmls.i<illegal width 8>	q12, <illegal reg q7.5>, d1[2]
│ │ +	vsri.8	q12, q8, #1
│ │  			@ <UNDEFINED> instruction: 0xffd1ba7d
│ │ -	vrsra.u64	d24, d5, #49
│ │ +	vrsra.u64	d24, d28, #49
│ │  	vmul.f16	<illegal reg q13.5>, <illegal reg q8.5>, d1[2]
│ │ -	vrshr.u64	q12, <illegal reg q12.5>, #49
│ │ +	vsubw.u8	q12, <illegal reg q7.5>, d16
│ │  			@ <UNDEFINED> instruction: 0xffd14c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3829fc <uniffi_pbcli_checksum_method_api_base@@Base+0x216178>
│ │  	beq.n	382514 <uniffi_pbcli_checksum_method_api_base@@Base+0x215c90>
│ │  	b.n	382980 <uniffi_pbcli_checksum_method_api_base@@Base+0x2160fc>
│ │  	ands	r2, r0
│ │  	b.n	38282a <uniffi_pbcli_checksum_method_api_base@@Base+0x215fa6>
│ │ @@ -985230,15 +985230,15 @@
│ │  	asrs	r4, r1, #32
│ │  	b.n	3822c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x215a44>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3828ac <uniffi_pbcli_checksum_method_api_base@@Base+0x216028>
│ │  	lsls	r0, r0, #4
│ │  	b.n	3826b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x215e30>
│ │  	vrhadd.u16	d14, d14, d31
│ │ -	blt.n	382742 <uniffi_pbcli_checksum_method_api_base@@Base+0x215ebe>
│ │ +	blt.n	382790 <uniffi_pbcli_checksum_method_api_base@@Base+0x215f0c>
│ │  			@ <UNDEFINED> instruction: 0xffd18cd8
│ │  	movs	r3, r2
│ │  	movs	r0, r0
│ │  	b.n	382e42 <uniffi_pbcli_checksum_method_api_base@@Base+0x2165be>
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │ @@ -985469,16 +985469,16 @@
│ │  	str	r0, [r6, r6]
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	38317a <uniffi_pbcli_checksum_method_api_base@@Base+0x2168f6>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0}
│ │  	b.n	383102 <uniffi_pbcli_checksum_method_api_base@@Base+0x21687e>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r3, r6, r8, r9, sl, fp, ip}
│ │ -	vmla.f16	<illegal reg q15.5>, q9, d3[0]
│ │ +	ldmia.w	sp!, {r0, r4, r5, r6, r8, r9, sl, fp, ip}
│ │ +	vmla.f16	<illegal reg q15.5>, q9, d2[3]
│ │  			@ <UNDEFINED> instruction: 0xffd14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	382ef0 <uniffi_pbcli_checksum_method_api_base@@Base+0x21666c>
│ │  	beq.n	382a90 <uniffi_pbcli_checksum_method_api_base@@Base+0x21620c>
│ │  	b.n	382e74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2165f0>
│ │  	ands	r0, r0
│ │  	b.n	382d1e <uniffi_pbcli_checksum_method_api_base@@Base+0x21649a>
│ │ @@ -985804,17 +985804,17 @@
│ │  	b.n	382796 <uniffi_pbcli_checksum_method_api_base@@Base+0x215f12>
│ │  	movs	r5, r0
│ │  	b.n	382fd2 <uniffi_pbcli_checksum_method_api_base@@Base+0x21674e>
│ │  	beq.n	382ccc <uniffi_pbcli_checksum_method_api_base@@Base+0x216448>
│ │  	b.n	38312c <uniffi_pbcli_checksum_method_api_base@@Base+0x2168a8>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r2, r4, r5, r7, r8, ip}
│ │ -	vqdmulh.s16	<illegal reg q8.5>, <illegal reg q11.5>, d6[3]
│ │ -			@ <UNDEFINED> instruction: 0xffd21c72
│ │ -			@ <UNDEFINED> instruction: 0xffd21d32
│ │ +			@ <UNDEFINED> instruction: 0xffd71d15
│ │ +			@ <UNDEFINED> instruction: 0xffd21c99
│ │ +			@ <UNDEFINED> instruction: 0xffd21d59
│ │  			@ <UNDEFINED> instruction: 0xffd24bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3831cc <uniffi_pbcli_checksum_method_api_base@@Base+0x216948>
│ │  	asrs	r4, r0, #32
│ │  	b.n	3827d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x215f52>
│ │  	ands	r0, r0
│ │  	b.n	382ffa <uniffi_pbcli_checksum_method_api_base@@Base+0x216776>
│ │ @@ -986204,18 +986204,18 @@
│ │  	movs	r1, r0
│ │  	lsls	r0, r4, #14
│ │  	lsls	r0, r4, #1
│ │  	lsls	r4, r0, #22
│ │  	movs	r7, r0
│ │  	b.n	383346 <uniffi_pbcli_checksum_method_api_base@@Base+0x216ac2>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r1, r2, r4, r6, r7, r8, r9, fp, ip}
│ │ -			@ <UNDEFINED> instruction: 0xffd23a55
│ │ -	vmull.u16	<illegal reg q8.5>, d1, d2
│ │ -	vmlsl.u16	<illegal reg q9.5>, d18, d1
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, fp, ip}
│ │ +			@ <UNDEFINED> instruction: 0xffd23a7c
│ │ +	vmull.u16	<illegal reg q8.5>, d1, d25
│ │ +	vmlsl.u16	<illegal reg q9.5>, d18, d24
│ │  			@ <UNDEFINED> instruction: 0xffd10e38
│ │  	vmlal.u16	q10, d7, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	383366 <uniffi_pbcli_checksum_method_api_base@@Base+0x216ae2>
│ │  	movs	r0, r0
│ │  	b.n	3836ca <uniffi_pbcli_checksum_method_api_base@@Base+0x216e46>
│ │  	movs	r4, r0
│ │ @@ -986250,15 +986250,15 @@
│ │  	b.n	3837ae <uniffi_pbcli_checksum_method_api_base@@Base+0x216f2a>
│ │  	str	r1, [r0, r0]
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	383836 <uniffi_pbcli_checksum_method_api_base@@Base+0x216fb2>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {fp, lr}
│ │  	ldmia.w	sp!, {r0, r3, r8, r9, sl, fp, ip, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xeaff1892
│ │ +			@ <UNDEFINED> instruction: 0xeaff18b9
│ │  	vsri.16	q12, q7, #14
│ │  			@ <UNDEFINED> instruction: 0xffd04df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3835ac <uniffi_pbcli_checksum_method_api_base@@Base+0x216d28>
│ │  	strh	r1, [r0, #0]
│ │  	b.n	3833d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x216b52>
│ │  	asrs	r0, r2, #32
│ │ @@ -986804,17 +986804,17 @@
│ │  	asrs	r7, r0, #32
│ │  	b.n	38388a <uniffi_pbcli_checksum_method_api_base@@Base+0x217006>
│ │  	ldr	r0, [pc, #960]	@ (38390c <uniffi_pbcli_checksum_method_api_base@@Base+0x217088>)
│ │  	ldmia.w	sp!, {r0, r1, r2, r5, r6, r8, r9, fp, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeafd0001
│ │  	b.n	383c96 <uniffi_pbcli_checksum_method_api_base@@Base+0x217412>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r4, r6, r7, r8, r9, ip}
│ │ +	ldmia.w	sp!, {r0, r3, r4, r5, r6, r7, r8, r9, ip}
│ │  	vmlal.u16	<illegal reg q14.5>, d18, d6
│ │ -	vraddhn.i16	d17, <illegal reg q7.5>, q15
│ │ +	vsri.8	<illegal reg q8.5>, <illegal reg q2.5>, #1
│ │  	vmul.i16	<illegal reg q14.5>, q9, d2[2]
│ │  			@ <UNDEFINED> instruction: 0xffcf4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	383a8c <uniffi_pbcli_checksum_method_api_base@@Base+0x217208>
│ │  	ands	r1, r0
│ │  	b.n	3838b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x217032>
│ │  	strb	r2, [r0, #0]
│ │ @@ -986990,17 +986990,17 @@
│ │  	b.n	383818 <uniffi_pbcli_checksum_method_api_base@@Base+0x216f94>
│ │  	str	r3, [r6, #92]	@ 0x5c
│ │  			@ <UNDEFINED> instruction: 0xebfe4000
│ │  	b.n	383e42 <uniffi_pbcli_checksum_method_api_base@@Base+0x2175be>
│ │  	movs	r4, r0
│ │  	b.n	383a46 <uniffi_pbcli_checksum_method_api_base@@Base+0x2171c2>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r2, r6, r9, ip}
│ │ -	vrshr.u16	d17, d6, #14
│ │ -	vmla.f16	<illegal reg q8.5>, q9, d6[3]
│ │ +	ldmia.w	sp!, {r0, r2, r3, r5, r6, r9, ip}
│ │ +	vrshr.u16	d17, d29, #14
│ │ +	vrshr.u16	d17, d5, #14
│ │  	vaddl.u16	q8, d2, d0
│ │  	b.n	383dba <uniffi_pbcli_checksum_method_api_base@@Base+0x217536>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #448]	@ (3838e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x21705c>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	383c40 <uniffi_pbcli_checksum_method_api_base@@Base+0x2173bc>
│ │  	asrs	r4, r0, #1
│ │ @@ -987073,15 +987073,15 @@
│ │  	b.n	383afa <uniffi_pbcli_checksum_method_api_base@@Base+0x217276>
│ │  	asrs	r5, r0, #32
│ │  	b.n	383afe <uniffi_pbcli_checksum_method_api_base@@Base+0x21727a>
│ │  	cmp	r1, #113	@ 0x71
│ │  	b.n	383dc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x21753e>
│ │  	ldr	r4, [pc, #448]	@ (383984 <uniffi_pbcli_checksum_method_api_base@@Base+0x217100>)
│ │  	ldmia.w	sp!, {r6, r7, r8, sl, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xeafe113e
│ │ +			@ <UNDEFINED> instruction: 0xeafe1165
│ │  			@ <UNDEFINED> instruction: 0xffd24c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	383cf0 <uniffi_pbcli_checksum_method_api_base@@Base+0x21746c>
│ │  	ands	r2, r0
│ │  	b.n	383b1a <uniffi_pbcli_checksum_method_api_base@@Base+0x217296>
│ │  	movs	r0, #0
│ │  	b.n	383f1e <uniffi_pbcli_checksum_method_api_base@@Base+0x21769a>
│ │ @@ -987608,16 +987608,16 @@
│ │  	str	r4, [r0, r0]
│ │  	b.n	38375a <uniffi_pbcli_checksum_method_api_base@@Base+0x216ed6>
│ │  	movs	r5, r0
│ │  	b.n	383f8e <uniffi_pbcli_checksum_method_api_base@@Base+0x21770a>
│ │  	beq.n	383c88 <uniffi_pbcli_checksum_method_api_base@@Base+0x217404>
│ │  	b.n	3840e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x217864>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r3, r4, r5, r6, r7, r9, sl, fp}
│ │ -	vmull.p<illegal width 16>	q11, d2, d21
│ │ +	ldmia.w	sp!, {r0, r5, r8, r9, sl, fp}
│ │ +	vqrdmlah.s16	q11, q1, d4[1]
│ │  			@ <UNDEFINED> instruction: 0xffd10cb8
│ │  	movs	r0, r0
│ │  	lsrs	r4, r6, #15
│ │  	movs	r0, r0
│ │  	lsrs	r4, r7, #32
│ │  	movs	r0, r0
│ │  	lsls	r0, r1, #21
│ │ @@ -987648,23 +987648,23 @@
│ │  	movs	r0, r0
│ │  	lsrs	r0, r3, #21
│ │  	movs	r0, r0
│ │  	ldr	r3, [sp, #496]	@ 0x1f0
│ │  	movs	r5, r2
│ │  	ldr	r2, [sp, #544]	@ 0x220
│ │  	movs	r5, r2
│ │ -	lsrs	r6, r2, #24
│ │ -	vqrdmulh.s16	q11, q1, d1[0]
│ │ -			@ <UNDEFINED> instruction: 0xffd18fd9
│ │ -			@ <UNDEFINED> instruction: 0xffd10d36
│ │ -	vqrdmlsh.s16	<illegal reg q14.5>, q9, d0[0]
│ │ +	lsrs	r5, r7, #24
│ │ +	vqrdmulh.s16	q11, q1, d0[3]
│ │ +	vaddl.u16	<illegal reg q12.5>, d1, d0
│ │ +			@ <UNDEFINED> instruction: 0xffd10d5d
│ │ +	vqrdmlsh.s16	<illegal reg q14.5>, q9, d7[2]
│ │  			@ <UNDEFINED> instruction: 0xffd1a8bf
│ │ -			@ <UNDEFINED> instruction: 0xffd08f0d
│ │ -	vqrdmulh.s16	q8, <illegal reg q0.5>, d2[2]
│ │ -	vmull.u16	q11, d18, d13
│ │ +			@ <UNDEFINED> instruction: 0xffd08f34
│ │ +			@ <UNDEFINED> instruction: 0xffd10d89
│ │ +			@ <UNDEFINED> instruction: 0xffd26cb4
│ │  	vmlal.u16	q10, d1, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	384016 <uniffi_pbcli_checksum_method_api_base@@Base+0x217792>
│ │  	movs	r2, r0
│ │  	b.n	38401a <uniffi_pbcli_checksum_method_api_base@@Base+0x217796>
│ │  	bls.n	383d98 <uniffi_pbcli_checksum_method_api_base@@Base+0x217514>
│ │  			@ <UNDEFINED> instruction: 0xebff0f10
│ │ @@ -989088,19 +989088,19 @@
│ │  	b.n	384f8a <uniffi_pbcli_checksum_method_api_base@@Base+0x218706>
│ │  	movs	r0, #0
│ │  	b.n	38504e <uniffi_pbcli_checksum_method_api_base@@Base+0x2187ca>
│ │  	str	r0, [r0, r0]
│ │  	b.n	385052 <uniffi_pbcli_checksum_method_api_base@@Base+0x2187ce>
│ │  	ldr	r1, [pc, #864]	@ (384c74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2183f0>)
│ │  			@ <UNDEFINED> instruction: 0xebfdff78
│ │ -			@ <UNDEFINED> instruction: 0xeaff010e
│ │ +			@ <UNDEFINED> instruction: 0xeaff0135
│ │  	vsli.16	<illegal reg q15.5>, q4, #2
│ │ -			@ <UNDEFINED> instruction: 0xffcffff2
│ │ -	vsri.16	d31, d28, #15
│ │ -	vshr.u64	q8, q1, #49
│ │ +	vshr.u8	d16, d9, #1
│ │ +	vsri.16	d31, d28, #14
│ │ +	vshr.u64	q8, <illegal reg q12.5>, #49
│ │  	vsli.16	d31, d12, #2
│ │  	vqshrun.s16	d20, q8, #1
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	384e54 <uniffi_pbcli_checksum_method_api_base@@Base+0x2185d0>
│ │  	str	r0, [r0, r0]
│ │  	b.n	384c7e <uniffi_pbcli_checksum_method_api_base@@Base+0x2183fa>
│ │  	movs	r1, r0
│ │ @@ -989140,16 +989140,16 @@
│ │  	b.n	384cce <uniffi_pbcli_checksum_method_api_base@@Base+0x21844a>
│ │  	movs	r0, #2
│ │  	b.n	384ab0 <uniffi_pbcli_checksum_method_api_base@@Base+0x21822c>
│ │  	ldr	r1, [pc, #736]	@ (384c74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2183f0>)
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	3850da <uniffi_pbcli_checksum_method_api_base@@Base+0x218856>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r1, r4, r5, r6, r8, r9, sl, fp, ip, sp, lr, pc}
│ │ -	vsra.u64	<illegal reg q14.5>, q14, #47
│ │ +	ldmia.w	sp!, {r0, r3, r4, r7, r8, r9, sl, fp, ip, sp, lr, pc}
│ │ +	vsubl.u16	<illegal reg q14.5>, d1, d19
│ │  			@ <UNDEFINED> instruction: 0xffd19afb
│ │  	vshr.u16	d16, d0, #16
│ │  	b.n	3844ce <uniffi_pbcli_checksum_method_api_base@@Base+0x217c4a>
│ │  	asrs	r7, r7, #11
│ │  	and.w	r0, r0, ip, lsr #4
│ │  	b.n	3844b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x217c32>
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -990167,30 +990167,30 @@
│ │  	vpmin.u32	q15, q14, <illegal reg q15.5>
│ │  	movs	r0, r4
│ │  	b.n	384dc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x218544>
│ │  	movs	r0, #122	@ 0x7a
│ │  	add.w	r0, r0, r5, lsl #24
│ │  	b.n	3855d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x218d52>
│ │  	ldc2l	10, cr14, [r7, #1020]	@ 0x3fc	@ <UNPREDICTABLE>
│ │ -	ldr??.w	pc, [sl, #209]!
│ │ -	ldr	r5, [sp, #388]	@ 0x184
│ │ -			@ <UNDEFINED> instruction: 0xffd1f8fe
│ │ -			@ <UNDEFINED> instruction: 0xffd19d05
│ │ -			@ <UNDEFINED> instruction: 0xffd1f92a
│ │ -			@ <UNDEFINED> instruction: 0xffd19d31
│ │ -	vqshl.u16	d31, d14, #1
│ │ -			@ <UNDEFINED> instruction: 0xffd1c997
│ │ -			@ <UNDEFINED> instruction: 0xffd1feda
│ │ -	vmlal.u16	q13, d17, d1[2]
│ │ -	vqshlu.s64	<illegal reg q15.5>, q3, #17
│ │ -			@ <UNDEFINED> instruction: 0xffd19add
│ │ -	vqshlu.s64	d31, d18, #17
│ │ -			@ <UNDEFINED> instruction: 0xffd1c92b
│ │ -	vmull.u16	<illegal reg q15.5>, d1, d6[3]
│ │ -	vqdmulh.s16	q14, <illegal reg q8.5>, d7[2]
│ │ +	vst4.<illegal width 64>	{d15[0],d17[0],d19[0],d21[0]}, [r1 :256], r1
│ │ +	ldr	r5, [sp, #544]	@ 0x220
│ │ +			@ <UNDEFINED> instruction: 0xffd1f925
│ │ +			@ <UNDEFINED> instruction: 0xffd19d2c
│ │ +	vqrshrn.u32	d31, <illegal reg q0.5>, #15
│ │ +			@ <UNDEFINED> instruction: 0xffd19d58
│ │ +			@ <UNDEFINED> instruction: 0xffd1f745
│ │ +			@ <UNDEFINED> instruction: 0xffd1c9be
│ │ +			@ <UNDEFINED> instruction: 0xffd1ff01
│ │ +	vsubw.u16	q13, <illegal reg q0.5>, d8
│ │ +	vqshlu.s64	<illegal reg q15.5>, <illegal reg q14.5>, #17
│ │ +			@ <UNDEFINED> instruction: 0xffd19b04
│ │ +	vqshlu.s64	<illegal reg q15.5>, <illegal reg q4.5>, #17
│ │ +	vqrshrn.u32	d28, q1, #15
│ │ +			@ <UNDEFINED> instruction: 0xffd1fa95
│ │ +			@ <UNDEFINED> instruction: 0xffd1cd0e
│ │  			@ <UNDEFINED> instruction: 0xffd14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3857fc <uniffi_pbcli_checksum_method_api_base@@Base+0x218f78>
│ │  	beq.n	38532c <uniffi_pbcli_checksum_method_api_base@@Base+0x218aa8>
│ │  	b.n	385780 <uniffi_pbcli_checksum_method_api_base@@Base+0x218efc>
│ │  	ands	r0, r0
│ │  	b.n	38562a <uniffi_pbcli_checksum_method_api_base@@Base+0x218da6>
│ │ @@ -991881,15 +991881,15 @@
│ │  	b.n	386906 <uniffi_pbcli_checksum_method_api_base@@Base+0x21a082>
│ │  	lsls	r0, r4, #1
│ │  	b.n	385c52 <uniffi_pbcli_checksum_method_api_base@@Base+0x2193ce>
│ │  			@ <UNDEFINED> instruction: 0xffeceaff
│ │  	lsrs	r5, r7, #13
│ │  			@ <UNDEFINED> instruction: 0xffd0deb4
│ │  			@ <UNDEFINED> instruction: 0xffd6ddfc
│ │ -			@ <UNDEFINED> instruction: 0xffd6e7c6
│ │ +			@ <UNDEFINED> instruction: 0xffd6e7ed
│ │  			@ <UNDEFINED> instruction: 0xffd1dbf9
│ │  			@ <UNDEFINED> instruction: 0xffcf4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	386684 <uniffi_pbcli_checksum_method_api_base@@Base+0x219e00>
│ │  	beq.n	386264 <uniffi_pbcli_checksum_method_api_base@@Base+0x2199e0>
│ │  	b.n	386608 <uniffi_pbcli_checksum_method_api_base@@Base+0x219d84>
│ │  	str	r4, [r0, #8]
│ │ @@ -992277,19 +992277,19 @@
│ │  	ldrh	r2, [r1, r2]
│ │  			@ <UNDEFINED> instruction: 0xebfe0010
│ │  	b.n	385fe0 <uniffi_pbcli_checksum_method_api_base@@Base+0x21975c>
│ │  	movs	r0, r2
│ │  	b.n	385fb6 <uniffi_pbcli_checksum_method_api_base@@Base+0x219732>
│ │  	vpadd.i16	q15, q9, <illegal reg q15.5>
│ │  			@ <UNDEFINED> instruction: 0xffd3eaff
│ │ -	b.n	386108 <uniffi_pbcli_checksum_method_api_base@@Base+0x219884>
│ │ -	vraddhn.i32	d30, <illegal reg q8.5>, q3
│ │ +	b.n	386156 <uniffi_pbcli_checksum_method_api_base@@Base+0x2198d2>
│ │ +	vraddhn.i32	d30, <illegal reg q8.5>, <illegal reg q14.5>
│ │  			@ <UNDEFINED> instruction: 0xffd17a95
│ │ -	vsri.16	q15, q3, #16
│ │ -	vsri.64	d30, d26, #47
│ │ +	vsri.16	q15, <illegal reg q14.5>, #16
│ │ +	vmls.i16	q15, <illegal reg q8.5>, d1[2]
│ │  			@ <UNDEFINED> instruction: 0xffd14bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3869e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x21a164>
│ │  	beq.n	3864e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x219c5c>
│ │  	b.n	38696c <uniffi_pbcli_checksum_method_api_base@@Base+0x21a0e8>
│ │  	str	r0, [r2, r0]
│ │  	b.n	385ff6 <uniffi_pbcli_checksum_method_api_base@@Base+0x219772>
│ │ @@ -992498,15 +992498,15 @@
│ │  	str	r1, [r0, #0]
│ │  	asrs	r0, r4, #14
│ │  	movs	r6, r0
│ │  	b.n	3869ce <uniffi_pbcli_checksum_method_api_base@@Base+0x21a14a>
│ │  	beq.n	3866c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x219e3c>
│ │  	b.n	386b28 <uniffi_pbcli_checksum_method_api_base@@Base+0x21a2a4>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r1, r3, r4, r6, r7, r8, r9, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, sl, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	386bbc <uniffi_pbcli_checksum_method_api_base@@Base+0x21a338>
│ │  	beq.n	38673c <uniffi_pbcli_checksum_method_api_base@@Base+0x219eb8>
│ │  	b.n	386b40 <uniffi_pbcli_checksum_method_api_base@@Base+0x21a2bc>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3869ea <uniffi_pbcli_checksum_method_api_base@@Base+0x21a166>
│ │ @@ -996037,20 +996037,20 @@
│ │  	b.n	3886b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x21be34>
│ │  	strh	r3, [r1, r1]
│ │  			@ <UNDEFINED> instruction: 0xebfe0008
│ │  	b.n	3888e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c05e>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r0, r4, r5, r8, fp, ip}
│ │  	vmlal.u16	<illegal reg q8.5>, d0, d13
│ │ -	vqrdmlah.s16	<illegal reg q11.5>, q0, d4[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd07e93
│ │  			@ <UNDEFINED> instruction: 0xffd1fe7c
│ │  	vqshl.u64	d17, d17, #63	@ 0x3f
│ │ -			@ <UNDEFINED> instruction: 0xffd07e10
│ │ +			@ <UNDEFINED> instruction: 0xffd07e37
│ │  	vqshrun.s32	d17, <illegal reg q12.5>, #15
│ │ -			@ <UNDEFINED> instruction: 0xffd07e98
│ │ +			@ <UNDEFINED> instruction: 0xffd07ebf
│ │  	vabdl.u16	<illegal reg q8.5>, d17, d1
│ │  	vaddl.u16	<illegal reg q8.5>, d0, d8
│ │  	b.n	38810c <uniffi_pbcli_checksum_method_api_base@@Base+0x21b888>
│ │  	movs	r0, #130	@ 0x82
│ │  	b.n	388d12 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c48e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3886f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x21be70>
│ │ @@ -996161,15 +996161,15 @@
│ │  	b.n	3887e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x21bf64>
│ │  	ldr	r4, [pc, #64]	@ (38870c <uniffi_pbcli_checksum_method_api_base@@Base+0x21be88>)
│ │  	ldmia.w	sp!, {r1, r2, r3, r4, r5, r6, r7, r8, ip, lr}
│ │  			@ <UNDEFINED> instruction: 0xeafe4e58
│ │  	movs	r5, r2
│ │  	ldr	r3, [pc, #208]	@ (3887a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x21bf24>)
│ │  	movs	r5, r2
│ │ -	str	r5, [r6, #96]	@ 0x60
│ │ +	str	r4, [r3, #100]	@ 0x64
│ │  			@ <UNDEFINED> instruction: 0xffd148f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	388c00 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c37c>
│ │  	movs	r0, r0
│ │  	b.n	388d8a <uniffi_pbcli_checksum_method_api_base@@Base+0x21c506>
│ │  	strb	r2, [r0, #0]
│ │  	b.n	388a2e <uniffi_pbcli_checksum_method_api_base@@Base+0x21c1aa>
│ │ @@ -996295,16 +996295,16 @@
│ │  	movs	r0, r0
│ │  	asrs	r0, r4, #14
│ │  	movs	r4, r0
│ │  	asrs	r4, r0, #22
│ │  	movs	r5, r0
│ │  	b.n	388b42 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c2be>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r6, r7, r8, sl, sp, lr}
│ │ -	vmls.f16	q11, <illegal reg q0.5>, d5[3]
│ │ +	ldmia.w	sp!, {r4, r5, r6, r7, r8, sl, sp, lr}
│ │ +	vsli.64	d22, d4, #17
│ │  	vsri.64	d18, d4, #47
│ │  	vaddl.u8	q8, d15, d0
│ │  	b.n	388eb6 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c632>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (38885c <uniffi_pbcli_checksum_method_api_base@@Base+0x21bfd8>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	388d3c <uniffi_pbcli_checksum_method_api_base@@Base+0x21c4b8>
│ │ @@ -996328,15 +996328,15 @@
│ │  	b.n	388f8a <uniffi_pbcli_checksum_method_api_base@@Base+0x21c706>
│ │  	asrs	r1, r0, #32
│ │  	b.n	38896c <uniffi_pbcli_checksum_method_api_base@@Base+0x21c0e8>
│ │  	ldr	r4, [pc, #64]	@ (388890 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c00c>)
│ │  	ldmia.w	sp!, {r0, r2, r3, r4, r7, r8, ip, lr}
│ │  			@ <UNDEFINED> instruction: 0xeafe4cb4
│ │  	movs	r5, r2
│ │ -	str	r3, [sp, #268]	@ 0x10c
│ │ +	str	r3, [sp, #424]	@ 0x1a8
│ │  			@ <UNDEFINED> instruction: 0xffd14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	388d80 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c4fc>
│ │  	beq.n	388890 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c00c>
│ │  	b.n	388d04 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c480>
│ │  	ands	r0, r0
│ │  	b.n	388bae <uniffi_pbcli_checksum_method_api_base@@Base+0x21c32a>
│ │ @@ -996817,22 +996817,22 @@
│ │  	b.n	3887aa <uniffi_pbcli_checksum_method_api_base@@Base+0x21bf26>
│ │  	ldrb	r7, [r1, #28]
│ │  			@ <UNDEFINED> instruction: 0xebfe009c
│ │  	b.n	3887b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x21bf2e>
│ │  	beq.n	388cc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c440>
│ │  	b.n	389124 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c8a0>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r5, r6, r7, r9, ip, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r8, r9, ip, pc}
│ │  	vsubw.u16	q8, <illegal reg q0.5>, d16
│ │  	movs	r0, r0
│ │  	ldr	r1, [pc, #496]	@ (388e8c <uniffi_pbcli_checksum_method_api_base@@Base+0x21c608>)
│ │  	movs	r5, r2
│ │ -	str	r1, [sp, #12]
│ │ +	str	r1, [sp, #168]	@ 0xa8
│ │  	vmlal.u16	<illegal reg q13.5>, d1, d7[2]
│ │ -	vaddl.u16	<illegal reg q12.5>, d16, d11
│ │ +	vshr.u64	d25, d18, #48
│ │  	vmla.f16	<illegal reg q13.5>, <illegal reg q8.5>, d7[3]
│ │  			@ <UNDEFINED> instruction: 0xffd049d0
│ │  	movs	r5, r2
│ │  	ldr	r1, [pc, #320]	@ (388df4 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c570>)
│ │  	movs	r5, r2
│ │  	ldr	r4, [pc, #64]	@ (388cf8 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c474>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │ @@ -997066,15 +997066,15 @@
│ │  	b.n	3889ba <uniffi_pbcli_checksum_method_api_base@@Base+0x21c136>
│ │  	asrs	r4, r3, #32
│ │  	b.n	3889be <uniffi_pbcli_checksum_method_api_base@@Base+0x21c13a>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	389606 <uniffi_pbcli_checksum_method_api_base@@Base+0x21cd82>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r5, r6, r9, fp, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r3, r7, r9, fp, ip, sp, pc}
│ │  	vaddl.u16	q8, d1, d0
│ │  	b.n	389572 <uniffi_pbcli_checksum_method_api_base@@Base+0x21ccee>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (388f98 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c714>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3893f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x21cb74>
│ │  	ands	r0, r0
│ │ @@ -997126,23 +997126,23 @@
│ │  	b.n	389686 <uniffi_pbcli_checksum_method_api_base@@Base+0x21ce02>
│ │  	ldr	r0, [pc, #192]	@ (389008 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c784>)
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r6, r7, r8, r9, sl, fp, lr}
│ │  			@ <UNDEFINED> instruction: 0xeafe42fc
│ │  	movs	r5, r2
│ │  	lsls	r0, r3, #1
│ │  	movs	r0, r0
│ │ -	cbnz	r5, 388f92 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c70e>
│ │ +	rev	r4, r2
│ │  	vaddl.u16	<illegal reg q8.5>, d1, d8
│ │  	b.n	388a9c <uniffi_pbcli_checksum_method_api_base@@Base+0x21c218>
│ │  	movs	r0, #33	@ 0x21
│ │  	b.n	3896a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x21ce1e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	389084 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c800>
│ │  	ldr	r7, [pc, #864]	@ (3892c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x21ca44>)
│ │ -			@ <UNDEFINED> instruction: 0xeafeb999
│ │ +			@ <UNDEFINED> instruction: 0xeafeb9c0
│ │  			@ <UNDEFINED> instruction: 0xffd14ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	389490 <uniffi_pbcli_checksum_method_api_base@@Base+0x21cc0c>
│ │  	beq.n	388f90 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c70c>
│ │  	b.n	389414 <uniffi_pbcli_checksum_method_api_base@@Base+0x21cb90>
│ │  	str	r1, [r0, #0]
│ │  	b.n	3896be <uniffi_pbcli_checksum_method_api_base@@Base+0x21ce3a>
│ │ @@ -997566,16 +997566,16 @@
│ │  	beq.n	389328 <uniffi_pbcli_checksum_method_api_base@@Base+0x21caa4>
│ │  	b.n	389788 <uniffi_pbcli_checksum_method_api_base@@Base+0x21cf04>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r3, r6, r7, r8, sl, fp, ip, sp, lr, pc}
│ │  	vrshr.u32	q8, q10, #1
│ │  	movs	r0, r0
│ │  	stc2	15, cr15, [r0, #1020]!	@ 0x3fc
│ │ -			@ <UNDEFINED> instruction: 0xb6b9
│ │ -	vqshlu.s16	<illegal reg q13.5>, <illegal reg q12.5>, #1
│ │ +			@ <UNDEFINED> instruction: 0xb6e0
│ │ +	vrsubhn.i32	d27, <illegal reg q8.5>, q8
│ │  			@ <UNDEFINED> instruction: 0xffd14df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	38982c <uniffi_pbcli_checksum_method_api_base@@Base+0x21cfa8>
│ │  	movs	r0, r0
│ │  	b.n	3899b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x21d132>
│ │  	movs	r6, r4
│ │  	lsrs	r0, r0, #8
│ │ @@ -997688,26 +997688,26 @@
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r1, r2}
│ │  	b.n	389752 <uniffi_pbcli_checksum_method_api_base@@Base+0x21cece>
│ │  	ldr	r3, [sp, #360]	@ 0x168
│ │  			@ <UNDEFINED> instruction: 0xebfb0008
│ │  	b.n	38975a <uniffi_pbcli_checksum_method_api_base@@Base+0x21ced6>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r8, sl, ip, sp, pc}
│ │ -	vmull.u16	q9, d1, d4
│ │ +	ldmia.w	sp!, {r2, r3, r4, r6, r8, sl, ip, sp, pc}
│ │ +	vmull.u16	q9, d1, d27
│ │  			@ <UNDEFINED> instruction: 0xffd13ebc
│ │  	movs	r5, r2
│ │  	asrs	r0, r1, #32
│ │  	b.n	388f6c <uniffi_pbcli_checksum_method_api_base@@Base+0x21c6e8>
│ │  	movs	r0, #28
│ │  	b.n	389b72 <uniffi_pbcli_checksum_method_api_base@@Base+0x21d2ee>
│ │  	asrs	r1, r0, #32
│ │  	b.n	389554 <uniffi_pbcli_checksum_method_api_base@@Base+0x21ccd0>
│ │  	strb	r0, [r7, r3]
│ │ -			@ <UNDEFINED> instruction: 0xeafeb4c9
│ │ +			@ <UNDEFINED> instruction: 0xeafeb4f0
│ │  			@ <UNDEFINED> instruction: 0xffd148f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	389960 <uniffi_pbcli_checksum_method_api_base@@Base+0x21d0dc>
│ │  	movs	r0, r2
│ │  	b.n	389aee <uniffi_pbcli_checksum_method_api_base@@Base+0x21d26a>
│ │  	movs	r7, r4
│ │  	ldrh	r0, [r0, #16]
│ │ @@ -997810,18 +997810,18 @@
│ │  	adds	r6, #213	@ 0xd5
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	389866 <uniffi_pbcli_checksum_method_api_base@@Base+0x21cfe2>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	389c6e <uniffi_pbcli_checksum_method_api_base@@Base+0x21d3ea>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r5, r6, r7, r8, r9, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r2, r5, sl, ip, sp, pc}
│ │  	vshr.u16	<illegal reg q9.5>, q10, #15
│ │ -	vmls.i<illegal width 8>	<illegal reg q13.5>, <illegal reg q7.5>, d1[5]
│ │ -	vraddhn.i32	d27, <illegal reg q0.5>, <illegal reg q10.5>
│ │ +	vraddhn.i16	d27, <illegal reg q15.5>, q6
│ │ +	vmls.i16	<illegal reg q13.5>, <illegal reg q0.5>, d4[1]
│ │  	vqshrun.s32	d20, q8, #15
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	389a64 <uniffi_pbcli_checksum_method_api_base@@Base+0x21d1e0>
│ │  	movs	r0, r0
│ │  	b.n	389bee <uniffi_pbcli_checksum_method_api_base@@Base+0x21d36a>
│ │  	movs	r7, r0
│ │  	lsrs	r0, r0, #8
│ │ @@ -997859,16 +997859,16 @@
│ │  	b.n	389c1a <uniffi_pbcli_checksum_method_api_base@@Base+0x21d396>
│ │  	movs	r0, #0
│ │  	b.n	389cde <uniffi_pbcli_checksum_method_api_base@@Base+0x21d45a>
│ │  	adds	r6, #181	@ 0xb5
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	389ce6 <uniffi_pbcli_checksum_method_api_base@@Base+0x21d462>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r6, r8, r9, ip, sp, pc}
│ │ -	vabdl.u16	<illegal reg q10.5>, d17, d12
│ │ +	ldmia.w	sp!, {r5, r7, r8, r9, ip, sp, pc}
│ │ +	vqshl.u64	d21, d19, #17
│ │  	vaddl.u16	q9, d1, d12
│ │  	b.n	3890d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c852>
│ │  	lsrs	r6, r3, #20
│ │  	b.n	389bdc <uniffi_pbcli_checksum_method_api_base@@Base+0x21d358>
│ │  	movs	r0, #1
│ │  	b.n	3898c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x21d03e>
│ │  	movs	r0, #128	@ 0x80
│ │ @@ -998046,17 +998046,17 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	389860 <uniffi_pbcli_checksum_method_api_base@@Base+0x21cfdc>
│ │  	ldr	r5, [pc, #900]	@ (389ac8 <uniffi_pbcli_checksum_method_api_base@@Base+0x21d244>)
│ │  			@ <UNDEFINED> instruction: 0xebfe0000
│ │  	b.n	389e8a <uniffi_pbcli_checksum_method_api_base@@Base+0x21d606>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r3, r4, r6, r7, fp, ip, sp, lr, pc}
│ │ -	vrshr.u32	<illegal reg q13.5>, <illegal reg q0.5>, #1
│ │ -	vsra.u64	d27, d29, #47
│ │ -	vsubl.u16	<illegal reg q13.5>, d1, d5
│ │ +	vrshr.u32	<illegal reg q13.5>, q12, #1
│ │ +	vmla.f16	<illegal reg q13.5>, <illegal reg q8.5>, d4[2]
│ │ +	vsubl.u16	<illegal reg q13.5>, d1, d28
│ │  	vaddl.u16	<illegal reg q8.5>, d1, d24
│ │  	b.n	389262 <uniffi_pbcli_checksum_method_api_base@@Base+0x21c9de>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r4, [pc, #448]	@ (389928 <uniffi_pbcli_checksum_method_api_base@@Base+0x21d0a4>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	389c88 <uniffi_pbcli_checksum_method_api_base@@Base+0x21d404>
│ │  	str	r0, [r0, r0]
│ │ @@ -998087,15 +998087,15 @@
│ │  	movs	r0, r0
│ │  	b.n	389e4e <uniffi_pbcli_checksum_method_api_base@@Base+0x21d5ca>
│ │  	movs	r0, r0
│ │  	asrs	r0, r4, #14
│ │  	movs	r4, r5
│ │  	asrs	r4, r0, #22
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r5, r6, r8, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r7, r8, ip, sp, pc}
│ │  	vmlal.u16	q10, d1, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	389afe <uniffi_pbcli_checksum_method_api_base@@Base+0x21d27a>
│ │  	beq.n	389850 <uniffi_pbcli_checksum_method_api_base@@Base+0x21cfcc>
│ │  	b.n	389c5c <uniffi_pbcli_checksum_method_api_base@@Base+0x21d3d8>
│ │  	movs	r0, r1
│ │  	b.n	3892e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x21ca5c>
│ │ @@ -998571,15 +998571,15 @@
│ │  	lsls	r1, r6, #20
│ │  	add.w	r0, r0, r8
│ │  	b.n	389f2e <uniffi_pbcli_checksum_method_api_base@@Base+0x21d6aa>
│ │  	beq.n	389c28 <uniffi_pbcli_checksum_method_api_base@@Base+0x21d3a4>
│ │  	b.n	38a088 <uniffi_pbcli_checksum_method_api_base@@Base+0x21d804>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r1, r4, r5, r7, fp, ip, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffcecbb2
│ │ +			@ <UNDEFINED> instruction: 0xffcecbd9
│ │  			@ <UNDEFINED> instruction: 0xffd04df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	38a120 <uniffi_pbcli_checksum_method_api_base@@Base+0x21d89c>
│ │  	strh	r0, [r0, #0]
│ │  	b.n	389f4a <uniffi_pbcli_checksum_method_api_base@@Base+0x21d6c6>
│ │  	str	r1, [r0, #0]
│ │  	b.n	389f4e <uniffi_pbcli_checksum_method_api_base@@Base+0x21d6ca>
│ │ @@ -998947,15 +998947,15 @@
│ │  	b.n	38a28e <uniffi_pbcli_checksum_method_api_base@@Base+0x21da0a>
│ │  	str	r0, [r0, #0]
│ │  	b.n	389a6c <uniffi_pbcli_checksum_method_api_base@@Base+0x21d1e8>
│ │  	adds	r7, r3, #5
│ │  			@ <UNDEFINED> instruction: 0xebfcd010
│ │  	b.n	38a3f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x21db6c>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r6, r9, pc}
│ │ +	ldmia.w	sp!, {r3, r5, r6, r9, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd148f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	38a484 <uniffi_pbcli_checksum_method_api_base@@Base+0x21dc00>
│ │  	beq.n	389f8c <uniffi_pbcli_checksum_method_api_base@@Base+0x21d708>
│ │  	b.n	38a408 <uniffi_pbcli_checksum_method_api_base@@Base+0x21db84>
│ │  	movs	r0, r0
│ │  	b.n	38a614 <uniffi_pbcli_checksum_method_api_base@@Base+0x21dd90>
│ │ @@ -999051,17 +999051,17 @@
│ │  	b.n	38a77a <uniffi_pbcli_checksum_method_api_base@@Base+0x21def6>
│ │  	adds	r4, #14
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	38a382 <uniffi_pbcli_checksum_method_api_base@@Base+0x21dafe>
│ │  	beq.n	38a064 <uniffi_pbcli_checksum_method_api_base@@Base+0x21d7e0>
│ │  	b.n	38a4dc <uniffi_pbcli_checksum_method_api_base@@Base+0x21dc58>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r3, fp}
│ │ -	vsra.u64	<illegal reg q12.5>, <illegal reg q4.5>, #47
│ │ -	vsra.u64	d24, d1, #47
│ │ +	ldmia.w	sp!, {r2, r4, r5, fp}
│ │ +	vsubl.u16	<illegal reg q12.5>, d1, d0
│ │ +	vsra.u64	d24, d24, #47
│ │  	vaddl.u16	q9, d1, d1
│ │  	b.n	38a39a <uniffi_pbcli_checksum_method_api_base@@Base+0x21db16>
│ │  	asrs	r0, r0, #32
│ │  	b.n	38a39e <uniffi_pbcli_checksum_method_api_base@@Base+0x21db1a>
│ │  	movs	r4, r0
│ │  	b.n	389ba0 <uniffi_pbcli_checksum_method_api_base@@Base+0x21d31c>
│ │  	movs	r0, r0
│ │ @@ -999737,36 +999737,36 @@
│ │  	movs	r4, r0
│ │  	b.n	38a95e <uniffi_pbcli_checksum_method_api_base@@Base+0x21e0da>
│ │  	asrs	r1, r0, #32
│ │  	b.n	38a740 <uniffi_pbcli_checksum_method_api_base@@Base+0x21debc>
│ │  	ldmia	r4, {r3, r4, r5, r6, r7}
│ │  			@ <UNDEFINED> instruction: 0xebfbff20
│ │  			@ <UNDEFINED> instruction: 0xeaff6a80
│ │ -	vshr.u8	d21, d30, #1
│ │ -	vmlsl.u16	<illegal reg q14.5>, d17, d5[3]
│ │ -	vqrdmlah.s16	q10, q8, d6[0]
│ │ -	vshr.u16	d27, d22, #15
│ │ -	vsra.u64	<illegal reg q10.5>, q3, #47
│ │ +	vmla.i<illegal width 8>	<illegal reg q10.5>, <illegal reg q7.5>, d1[5]
│ │ +	vqshl.u16	d29, d4, #1
│ │ +	vqrdmlah.s16	q10, q8, d5[3]
│ │ +	vshr.u16	<illegal reg q13.5>, <illegal reg q6.5>, #15
│ │ +	vsra.u64	<illegal reg q10.5>, <illegal reg q14.5>, #47
│ │  			@ <UNDEFINED> instruction: 0xffd1add6
│ │  	vshll.u8	q11, d8, #7
│ │ -			@ <UNDEFINED> instruction: 0xffcfafaa
│ │ -	vmla.f16	<illegal reg q10.5>, <illegal reg q0.5>, d2[1]
│ │ -			@ <UNDEFINED> instruction: 0xffd1afde
│ │ -	vsra.u16	<illegal reg q10.5>, q15, #15
│ │ +			@ <UNDEFINED> instruction: 0xffcfafd1
│ │ +	vsra.u16	<illegal reg q10.5>, <illegal reg q8.5>, #15
│ │ +	vaddl.u16	<illegal reg q13.5>, d1, d5
│ │ +	vaddw.u16	<illegal reg q10.5>, <illegal reg q8.5>, d21
│ │  	vqrdmlsh.s16	<illegal reg q11.5>, <illegal reg q0.5>, d5[3]
│ │ -			@ <UNDEFINED> instruction: 0xffd0af26
│ │ -	vmla.i16	<illegal reg q10.5>, <illegal reg q8.5>, d6[0]
│ │ +	vqrdmlsh.s16	q13, q0, d5[1]
│ │ +	vmla.i16	<illegal reg q10.5>, <illegal reg q8.5>, d5[3]
│ │  			@ <UNDEFINED> instruction: 0xffd11a94
│ │  			@ <UNDEFINED> instruction: 0xffd05c39
│ │ -	vaddw.u8	<illegal reg q9.5>, <illegal reg q15.5>, d20
│ │ -	vaddw.u16	q14, <illegal reg q8.5>, d14
│ │ -	vabal.u16	q14, d0, d2
│ │ -	vrshr.u16	d21, d2, #16
│ │ -	vmlal.u16	<illegal reg q14.5>, d17, d14
│ │ -	vshr.u16	<illegal reg q10.5>, q5, #16
│ │ +	vmla.f<illegal width 8>	<illegal reg q9.5>, <illegal reg q15.5>, d3[2]
│ │ +	vsra.u64	d28, d21, #47
│ │ +	vabal.u16	q14, d0, d25
│ │ +	vrshr.u16	d21, d25, #16
│ │ +			@ <UNDEFINED> instruction: 0xffd1d8b5
│ │ +	vaddl.u16	<illegal reg q10.5>, d16, d1
│ │  	vaddl.u16	q8, d1, d4
│ │  	b.n	38a1c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x21d944>
│ │  	movs	r0, r0
│ │  	b.n	38a7ac <uniffi_pbcli_checksum_method_api_base@@Base+0x21df28>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	asrs	r0, r4, #5
│ │  	movs	r3, r2
│ │ @@ -999849,16 +999849,16 @@
│ │  	b.n	38aa7e <uniffi_pbcli_checksum_method_api_base@@Base+0x21e1fa>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, sp, lr}
│ │  	b.n	38ae86 <uniffi_pbcli_checksum_method_api_base@@Base+0x21e602>
│ │  	movs	r6, r0
│ │  	b.n	38aa8a <uniffi_pbcli_checksum_method_api_base@@Base+0x21e206>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r6, r8}
│ │ -	vsra.u16	d16, d5, #15
│ │ +	ldmia.w	sp!, {r2, r3, r5, r6, r8}
│ │ +	vsra.u16	d16, d28, #15
│ │  	vaddl.u16	<illegal reg q8.5>, d1, d0
│ │  	b.n	38a27c <uniffi_pbcli_checksum_method_api_base@@Base+0x21d9f8>
│ │  	movs	r0, r0
│ │  	b.n	38a27e <uniffi_pbcli_checksum_method_api_base@@Base+0x21d9fa>
│ │  	add	r4, pc, #24	@ (adr r4, 38a778 <uniffi_pbcli_checksum_method_api_base@@Base+0x21def4>)
│ │  			@ <UNDEFINED> instruction: 0xeafb207c
│ │  	b.n	38a286 <uniffi_pbcli_checksum_method_api_base@@Base+0x21da02>
│ │ @@ -1000661,17 +1000661,17 @@
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r4, r5, r6, r9, fp, sp}
│ │  	movs	r5, r2
│ │  	strb	r4, [r2, #30]
│ │  	movs	r5, r2
│ │  	cmp	r2, #216	@ 0xd8
│ │  	movs	r5, r2
│ │ -	vminnm.f32	<illegal reg q15.5>, <illegal reg q12.5>, q0
│ │ -	mcr2	15, 0, pc, cr9, cr0, {6}	@ <UNPREDICTABLE>
│ │ -	stc2l	15, cr15, [r5, #832]!	@ 0x340
│ │ +			@ <UNDEFINED> instruction: 0xff90ffd0
│ │ +	mrc2	15, 1, pc, cr0, cr0, {6}
│ │ +	mcr2	15, 0, pc, cr12, cr0, {6}	@ <UNPREDICTABLE>
│ │  	ldr	r7, [pc, #960]	@ (38b224 <uniffi_pbcli_checksum_method_api_base@@Base+0x21e9a0>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	38b384 <uniffi_pbcli_checksum_method_api_base@@Base+0x21eb00>
│ │  	beq.n	38aed4 <uniffi_pbcli_checksum_method_api_base@@Base+0x21e650>
│ │  	b.n	38b308 <uniffi_pbcli_checksum_method_api_base@@Base+0x21ea84>
│ │  	add	r0, pc, #0	@ (adr r0, 38ae70 <uniffi_pbcli_checksum_method_api_base@@Base+0x21e5ec>)
│ │  	b.n	38b1b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x21e92e>
│ │ @@ -1001191,15 +1001191,15 @@
│ │  	b.n	38b41c <uniffi_pbcli_checksum_method_api_base@@Base+0x21eb98>
│ │  	mov	sl, lr
│ │  			@ <UNDEFINED> instruction: 0xebfe0005
│ │  	b.n	38b646 <uniffi_pbcli_checksum_method_api_base@@Base+0x21edc2>
│ │  	beq.n	38b340 <uniffi_pbcli_checksum_method_api_base@@Base+0x21eabc>
│ │  	b.n	38b7a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x21ef1c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r3, r8, r9, sl, fp, sp}
│ │ +	ldmia.w	sp!, {r2, r4, r5, r8, r9, sl, fp, sp}
│ │  	vsubl.u16	q8, d1, d8
│ │  	vmlsl.u16	<illegal reg q13.5>, d0, d20
│ │  	vsra.u64	q8, q4, #49
│ │  			@ <UNDEFINED> instruction: 0xffd04df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	38b840 <uniffi_pbcli_checksum_method_api_base@@Base+0x21efbc>
│ │  	asrs	r0, r1, #3
│ │ @@ -1003066,36 +1003066,36 @@
│ │  	b.n	38caee <uniffi_pbcli_checksum_method_api_base@@Base+0x22026a>
│ │  	movs	r4, r0
│ │  	b.n	38c6f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x21fe6e>
│ │  	beq.n	38c3d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x21fb50>
│ │  	b.n	38c84c <uniffi_pbcli_checksum_method_api_base@@Base+0x21ffc8>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r3, sl, ip, sp}
│ │ -			@ <UNDEFINED> instruction: 0xffd02bb3
│ │ +			@ <UNDEFINED> instruction: 0xffd02bda
│ │  	vqshrn.u32	d31, q12, #15
│ │  	movs	r2, r2
│ │  	adds	r2, #133	@ 0x85
│ │ -	vmlsl.u16	q9, d0, d31
│ │ +			@ <UNDEFINED> instruction: 0xffd02a56
│ │  			@ <UNDEFINED> instruction: 0xffd1f744
│ │  	movs	r2, r2
│ │  	adds	r3, #133	@ 0x85
│ │ -			@ <UNDEFINED> instruction: 0xffd02b2f
│ │ +			@ <UNDEFINED> instruction: 0xffd02b56
│ │  	vsubl.u16	<illegal reg q9.5>, d1, d29
│ │ -			@ <UNDEFINED> instruction: 0xffd029d7
│ │ +			@ <UNDEFINED> instruction: 0xffd029fe
│ │  	vsri.64	d27, d18, #47
│ │  			@ <UNDEFINED> instruction: 0xffcf3360
│ │  	vqrshrun.s32	d31, q12, #16
│ │  	movs	r2, r2
│ │  	adds	r2, #229	@ 0xe5
│ │  	vrshr.u16	<illegal reg q9.5>, <illegal reg q4.5>, #16
│ │ -	vmlsl.u16	q9, d0, d3
│ │ +	vmlsl.u16	q9, d0, d26
│ │  	vqshrun.s32	d31, q12, #15
│ │  	movs	r2, r2
│ │  	adds	r2, #5
│ │ -			@ <UNDEFINED> instruction: 0xffd029af
│ │ +			@ <UNDEFINED> instruction: 0xffd029d6
│ │  			@ <UNDEFINED> instruction: 0xffd14c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	38c928 <uniffi_pbcli_checksum_method_api_base@@Base+0x2200a4>
│ │  	movs	r0, r0
│ │  	b.n	38cab2 <uniffi_pbcli_checksum_method_api_base@@Base+0x22022e>
│ │  	movs	r4, r0
│ │  	lsrs	r0, r0, #8
│ │ @@ -1003201,15 +1003201,15 @@
│ │  	ands	r0, r0
│ │  	b.n	38cc46 <uniffi_pbcli_checksum_method_api_base@@Base+0x2203c2>
│ │  	cmp	r2, #219	@ 0xdb
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	38c84e <uniffi_pbcli_checksum_method_api_base@@Base+0x21ffca>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r0, r2, r4, r7, ip, sp}
│ │ -	vmlal.u16	q13, d16, d3[2]
│ │ +	vsubw.u16	q13, q0, d10
│ │  	vmlal.u16	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	38c862 <uniffi_pbcli_checksum_method_api_base@@Base+0x21ffde>
│ │  	beq.n	38c534 <uniffi_pbcli_checksum_method_api_base@@Base+0x21fcb0>
│ │  	b.n	38c9c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22013c>
│ │  	adds	r0, #0
│ │  	b.n	38cc6a <uniffi_pbcli_checksum_method_api_base@@Base+0x2203e6>
│ │ @@ -1003426,15 +1003426,15 @@
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r2, r3, r5, r6, r7, r8, r9, sl, fp, sp}
│ │  	vqrdmlsh.s16	q9, q8, d1[1]
│ │  			@ <UNDEFINED> instruction: 0xffd02fa1
│ │  	vmls.i16	<illegal reg q15.5>, q8, d4[0]
│ │  	movs	r2, r2
│ │  	cmp	r6, #209	@ 0xd1
│ │ -	vsra.u16	d26, d15, #16
│ │ +	vmla.f16	q13, q0, d6[0]
│ │  	vsri.16	d31, d4, #16
│ │  	movs	r2, r2
│ │  	eor.w	r0, ip, #9568256	@ 0x920000
│ │  			@ <UNDEFINED> instruction: 0xf3fc0012
│ │  	ldr	r0, [pc, #0]	@ (38c724 <uniffi_pbcli_checksum_method_api_base@@Base+0x21fea0>)
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	38ca6a <uniffi_pbcli_checksum_method_api_base@@Base+0x2201e6>
│ │ @@ -1004910,24 +1004910,24 @@
│ │  	movs	r6, #223	@ 0xdf
│ │  			@ <UNDEFINED> instruction: 0xebfd1103
│ │  	b.n	38da0a <uniffi_pbcli_checksum_method_api_base@@Base+0x221186>
│ │  	asrs	r4, r1, #32
│ │  	b.n	38da8e <uniffi_pbcli_checksum_method_api_base@@Base+0x22120a>
│ │  			@ <UNDEFINED> instruction: 0xffaaeaff
│ │  	movs	r2, #209	@ 0xd1
│ │ -	vqrdmlah.s16	<illegal reg q11.5>, q8, d0[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd07f0f
│ │  	vmul.f16	q15, q0, d0[2]
│ │  	movs	r2, r2
│ │  	movs	r1, #129	@ 0x81
│ │ -			@ <UNDEFINED> instruction: 0xffd07d98
│ │ +			@ <UNDEFINED> instruction: 0xffd07dbf
│ │  	vsubw.u16	q9, q0, d13
│ │  	vrsra.u64	d26, d18, #48
│ │  	vrshr.u8	q9, q4, #1
│ │  	vsra.u64	d18, d21, #48
│ │ -	vqrdmulh.s16	<illegal reg q11.5>, q8, d4[1]
│ │ +			@ <UNDEFINED> instruction: 0xffd07df3
│ │  	vmla.f16	q9, q8, d1[3]
│ │  	vaddl.u16	q8, d0, d4
│ │  	b.n	38cf80 <uniffi_pbcli_checksum_method_api_base@@Base+0x2206fc>
│ │  	movs	r0, r0
│ │  	b.n	38d564 <uniffi_pbcli_checksum_method_api_base@@Base+0x220ce0>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	b.n	38d29c <uniffi_pbcli_checksum_method_api_base@@Base+0x220a18>
│ │ @@ -1005020,16 +1005020,16 @@
│ │  	b.n	38d84a <uniffi_pbcli_checksum_method_api_base@@Base+0x220fc6>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, sp, lr}
│ │  	b.n	38dc52 <uniffi_pbcli_checksum_method_api_base@@Base+0x2213ce>
│ │  	movs	r6, r0
│ │  	b.n	38d856 <uniffi_pbcli_checksum_method_api_base@@Base+0x220fd2>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r8, r9, ip, pc}
│ │ -	vmlal.u16	<illegal reg q12.5>, d16, d3[3]
│ │ +	ldmia.w	sp!, {r1, r6, r8, r9, ip, pc}
│ │ +	vrsra.u16	d25, d2, #16
│ │  			@ <UNDEFINED> instruction: 0xffd04c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	38da44 <uniffi_pbcli_checksum_method_api_base@@Base+0x2211c0>
│ │  	str	r0, [r0, #0]
│ │  	b.n	38d86e <uniffi_pbcli_checksum_method_api_base@@Base+0x220fea>
│ │  	lsls	r0, r1, #2
│ │  	b.n	38d070 <uniffi_pbcli_checksum_method_api_base@@Base+0x2207ec>
│ │ @@ -1005095,16 +1005095,16 @@
│ │  			@ <UNDEFINED> instruction: 0xebfb4000
│ │  	b.n	38dcf6 <uniffi_pbcli_checksum_method_api_base@@Base+0x221472>
│ │  	movs	r4, r0
│ │  	b.n	38d8fa <uniffi_pbcli_checksum_method_api_base@@Base+0x221076>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r2, r3, r6, r9, sl, sp, lr, pc}
│ │  	movs	r2, r2
│ │ -	str	r2, [sp, #508]	@ 0x1fc
│ │ -	vrshr.u16	<illegal reg q12.5>, <illegal reg q3.5>, #16
│ │ +	str	r2, [sp, #664]	@ 0x298
│ │ +	vrshr.u16	<illegal reg q12.5>, q15, #16
│ │  	vsli.64	q15, q6, #16
│ │  	movs	r2, r2
│ │  	ldr	r5, [pc, #960]	@ (38d990 <uniffi_pbcli_checksum_method_api_base@@Base+0x22110c>)
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	38daf0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22126c>
│ │  	beq.n	38d5e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x220d64>
│ │  	b.n	38da74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2211f0>
│ │ @@ -1005444,17 +1005444,17 @@
│ │  	b.n	38e00e <uniffi_pbcli_checksum_method_api_base@@Base+0x22178a>
│ │  	movs	r5, r0
│ │  	b.n	38dc12 <uniffi_pbcli_checksum_method_api_base@@Base+0x22138e>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r3, r4, r5, r6, r7, sl, fp, ip, sp, lr, pc}
│ │  	movs	r4, r2
│ │  	ldc2l	0, cr0, [r8, #-80]!	@ 0xffffffb0
│ │ -	str	r0, [sp, #252]	@ 0xfc
│ │ -			@ <UNDEFINED> instruction: 0xffd08f57
│ │ -			@ <UNDEFINED> instruction: 0xffd08f33
│ │ +	str	r0, [sp, #408]	@ 0x198
│ │ +			@ <UNDEFINED> instruction: 0xffd08f7e
│ │ +			@ <UNDEFINED> instruction: 0xffd08f5a
│ │  	vaddl.u16	<illegal reg q9.5>, d0, d4
│ │  	b.n	38d42c <uniffi_pbcli_checksum_method_api_base@@Base+0x220ba8>
│ │  	adds	r0, #3
│ │  	b.n	38da10 <uniffi_pbcli_checksum_method_api_base@@Base+0x22118c>
│ │  	ldr	r5, [sp, #908]	@ 0x38c
│ │  			@ <UNDEFINED> instruction: 0xeafbe3d4
│ │  	movs	r2, r2
│ │ @@ -1006129,15 +1006129,15 @@
│ │  	ldrsh	r5, [r1, r7]
│ │  	b.n	38e606 <uniffi_pbcli_checksum_method_api_base@@Base+0x221d82>
│ │  			@ <UNDEFINED> instruction: 0xffb6eaff
│ │  	str	r0, [r1, #40]	@ 0x28
│ │  	movs	r5, r2
│ │  	str	r4, [r6, #36]	@ 0x24
│ │  	movs	r5, r2
│ │ -			@ <UNDEFINED> instruction: 0xb6c6
│ │ +			@ <UNDEFINED> instruction: 0xb6ed
│ │  	vmull.u16	<illegal reg q11.5>, d0, d1[1]
│ │  	vmlal.u<illegal width 8>	q11, d15, d0[1]
│ │  	movs	r5, r2
│ │  	bls.n	38deac <uniffi_pbcli_checksum_method_api_base@@Base+0x221628>
│ │  	vrshr.u8	q15, <illegal reg q1.5>, #1
│ │  	vrshr.u8	d30, d19, #2
│ │  	vrshr.u8	d30, d3, #2
│ │ @@ -1006146,37 +1006146,37 @@
│ │  	movs	r4, r2
│ │  	cmp	r1, r3
│ │  	vrsubhn.i32	d23, q8, <illegal reg q10.5>
│ │  	vqrdmlah.s<illegal width 8>	<illegal reg q10.5>, <illegal reg q15.5>, d0[6]
│ │  	movs	r5, r2
│ │  	ldrsh	r4, [r2, r3]
│ │  	movs	r5, r2
│ │ -	cbz	r6, 38df50 <uniffi_pbcli_checksum_method_api_base@@Base+0x2216cc>
│ │ +	cbz	r5, 38df5a <uniffi_pbcli_checksum_method_api_base@@Base+0x2216d6>
│ │  	vrsubhn.i32	d23, q8, <illegal reg q12.5>
│ │  	vmull.p8	<illegal reg q10.5>, d31, d20
│ │  	movs	r5, r2
│ │  	bvs.n	38dfa0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22171c>
│ │  	vaddl.u8	q11, d15, d0
│ │  	movs	r5, r2
│ │  	ldrsh	r4, [r5, r7]
│ │  	movs	r5, r2
│ │ -	push	{r1, r2, r3, r4, r5}
│ │ +	push	{r0, r2, r5, r6}
│ │  			@ <UNDEFINED> instruction: 0xffd077c1
│ │  			@ <UNDEFINED> instruction: 0xffcf5fbc
│ │  	movs	r5, r2
│ │  	bvc.n	38dfe8 <uniffi_pbcli_checksum_method_api_base@@Base+0x221764>
│ │  	vsra.u8	d22, d20, #1
│ │  	movs	r5, r2
│ │  	str	r0, [r4, #16]
│ │  	movs	r5, r2
│ │  	str	r0, [r3, #16]
│ │  	movs	r5, r2
│ │  	add	r8, r3
│ │  	movs	r5, r2
│ │ -	asrs	r3, r3, #3
│ │ +	asrs	r2, r0, #4
│ │  	vabdl.u16	q10, d1, d15
│ │  	vrsra.u16	q8, q8, #16
│ │  	movs	r0, r0
│ │  	lsls	r0, r3, #15
│ │  	movs	r0, r0
│ │  	lsls	r0, r1, #15
│ │  	movs	r0, r0
│ │ @@ -1006186,15 +1006186,15 @@
│ │  	movs	r5, r2
│ │  	lsls	r4, r6, #18
│ │  	movs	r0, r0
│ │  	ldrsh	r4, [r3, r6]
│ │  	movs	r5, r2
│ │  	ldrsh	r0, [r1, r6]
│ │  	movs	r5, r2
│ │ -	cbz	r2, 38dfde <uniffi_pbcli_checksum_method_api_base@@Base+0x22175a>
│ │ +	push	{r0}
│ │  	vqshl.u16	<illegal reg q11.5>, <illegal reg q6.5>, #0
│ │  			@ <UNDEFINED> instruction: 0xffcf5f58
│ │  	movs	r5, r2
│ │  	bvs.n	38df60 <uniffi_pbcli_checksum_method_api_base@@Base+0x2216dc>
│ │  	vqshrun.s16	d20, q8, #1
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	38e498 <uniffi_pbcli_checksum_method_api_base@@Base+0x221c14>
│ │ @@ -1006248,15 +1006248,15 @@
│ │  	b.n	38e104 <uniffi_pbcli_checksum_method_api_base@@Base+0x221880>
│ │  	ldr	r0, [pc, #192]	@ (38e0a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x221824>)
│ │  	ldmia.w	sp!, {r0, r2, r5, r6, r7, r8, r9, sp}
│ │  			@ <UNDEFINED> instruction: 0xeafd5dbc
│ │  	movs	r5, r2
│ │  	ldrb	r0, [r5, r6]
│ │  	movs	r5, r2
│ │ -	cbz	r2, 38e036 <uniffi_pbcli_checksum_method_api_base@@Base+0x2217b2>
│ │ +	sxth	r1, r4
│ │  	vsli.16	<illegal reg q11.5>, <illegal reg q14.5>, #0
│ │  			@ <UNDEFINED> instruction: 0xffcf5d78
│ │  	movs	r5, r2
│ │  	bpl.n	38e030 <uniffi_pbcli_checksum_method_api_base@@Base+0x2217ac>
│ │  	vqshrun.s16	d20, q8, #1
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	38e528 <uniffi_pbcli_checksum_method_api_base@@Base+0x221ca4>
│ │ @@ -1006905,46 +1006905,46 @@
│ │  	movs	r7, #9
│ │  	add.w	r0, r4, r8
│ │  	b.n	38e0d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x221852>
│ │  	movs	r7, #7
│ │  	add.w	r0, r4, r0, lsl #28
│ │  	b.n	38ecf6 <uniffi_pbcli_checksum_method_api_base@@Base+0x222472>
│ │  	vpmin.u32	q7, <illegal reg q12.5>, <illegal reg q15.5>
│ │ -	str	r2, [r5, #96]	@ 0x60
│ │ -	vshll.u16	q8, d5, #1
│ │ +	str	r1, [r2, #100]	@ 0x64
│ │ +	vshll.u16	q8, d28, #1
│ │  	vrsubhn.i32	d30, <illegal reg q8.5>, q10
│ │  	vaddw.u8	<illegal reg q14.5>, <illegal reg q7.5>, d14
│ │  	vshr.u64	<illegal reg q15.5>, q12, #49
│ │  	movs	r4, r2
│ │  	asrs	r7, r2, #13
│ │  	vshr.u64	<illegal reg q14.5>, q3, #49
│ │  	vmla.i<illegal width 8>	<illegal reg q15.5>, <illegal reg q15.5>, d0[0]
│ │  	movs	r4, r2
│ │ -	stmia	r4!, {r0, r2, r3, r5}
│ │ +	stmia	r4!, {r2, r4, r6}
│ │  	vshr.u64	d29, d14, #48
│ │  	vaddl.u8	<illegal reg q15.5>, d31, d8
│ │  	movs	r4, r2
│ │  	ldr	r0, [r1, r3]
│ │  	movs	r5, r2
│ │  	ldr	r4, [r6, r2]
│ │  	movs	r5, r2
│ │ -	add	r5, sp, #24
│ │ +	add	r5, sp, #180	@ 0xb4
│ │  	vaddl.u16	<illegal reg q11.5>, d16, d9
│ │  	vmlal.u8	<illegal reg q10.5>, d31, d4
│ │  	movs	r5, r2
│ │  	beq.n	38e640 <uniffi_pbcli_checksum_method_api_base@@Base+0x221dbc>
│ │ -	vrshr.u64	q12, q0, #49
│ │ +	vrshr.u64	q12, <illegal reg q11.5>, #49
│ │  			@ <UNDEFINED> instruction: 0xffd0cfd2
│ │  			@ <UNDEFINED> instruction: 0xffcfefbc
│ │  	movs	r4, r2
│ │  	ldr	r4, [r0, r0]
│ │  	movs	r5, r2
│ │  	ldrsb	r0, [r6, r7]
│ │  	movs	r5, r2
│ │ -	add	r4, sp, #264	@ 0x108
│ │ +	add	r4, sp, #420	@ 0x1a4
│ │  	vqrdmlsh.s16	q11, q8, d5[0]
│ │  			@ <UNDEFINED> instruction: 0xffcf57c0
│ │  	movs	r5, r2
│ │  	ldmia	r7!, {r1, r2, r3, r4, r6}
│ │  			@ <UNDEFINED> instruction: 0xffcf4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	38eb44 <uniffi_pbcli_checksum_method_api_base@@Base+0x2222c0>
│ │ @@ -1007969,31 +1007969,31 @@
│ │  	str	r3, [r0, r0]
│ │  	b.n	38f656 <uniffi_pbcli_checksum_method_api_base@@Base+0x222dd2>
│ │  			@ <UNDEFINED> instruction: 0xfff3eaff
│ │  	blt.n	38efc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x22273e>
│ │  	vmlsl.u8	q14, d30, d14
│ │  			@ <UNDEFINED> instruction: 0xffcfea78
│ │  	movs	r4, r2
│ │ -	lsls	r3, r5, #20
│ │ -			@ <UNDEFINED> instruction: 0xffd1bb47
│ │ +	lsls	r2, r2, #21
│ │ +			@ <UNDEFINED> instruction: 0xffd1bb6e
│ │  	vabdl.u16	q14, d16, d14
│ │  	vqshl.u8	q15, q12, #7
│ │  	movs	r4, r2
│ │ -	lsls	r7, r0, #7
│ │ +	lsls	r6, r5, #7
│ │  	vmls.f16	q8, <illegal reg q8.5>, d0[2]
│ │  	movs	r0, r0
│ │ -	cbnz	r3, 38efb6 <uniffi_pbcli_checksum_method_api_base@@Base+0x222732>
│ │ +	pop	{r1}
│ │  	vmlal.u16	q14, d0, d18
│ │  	vmlal.u8	q15, d15, d12
│ │  	movs	r4, r2
│ │  	str	r4, [r2, r1]
│ │  	movs	r5, r2
│ │  	str	r0, [r0, r1]
│ │  	movs	r5, r2
│ │ -	add	r4, pc, #584	@ (adr r4, 38f19c <uniffi_pbcli_checksum_method_api_base@@Base+0x222918>)
│ │ +	add	r4, pc, #740	@ (adr r4, 38f238 <uniffi_pbcli_checksum_method_api_base@@Base+0x2229b4>)
│ │  	vqshrun.s32	d22, <illegal reg q2.5>, #16
│ │  	vshr.u8	d21, d0, #1
│ │  	movs	r5, r2
│ │  	stmia	r7!, {r1, r2, r3, r5, r7}
│ │  	vqshrn.u16	d16, q0, #1
│ │  	vqrshrun.s32	d28, q3, #16
│ │  	vmul.i<illegal width 8>	q15, <illegal reg q7.5>, d0[0]
│ │ @@ -1008003,30 +1008003,30 @@
│ │  	movs	r4, r2
│ │  	stmia	r5!, {r1, r2, r3, r5, r6, r7}
│ │  	vsubw.u8	q11, <illegal reg q7.5>, d26
│ │  	vqrdmlsh.s<illegal width 8>	q10, <illegal reg q7.5>, d0[4]
│ │  	movs	r5, r2
│ │  	ldr	r7, [pc, #288]	@ (38f0a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x222820>)
│ │  	movs	r5, r2
│ │ -	add	r3, pc, #616	@ (adr r3, 38f1f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22296c>)
│ │ +	add	r3, pc, #772	@ (adr r3, 38f28c <uniffi_pbcli_checksum_method_api_base@@Base+0x222a08>)
│ │  	vqshl.u16	d22, d13, #0
│ │  			@ <UNDEFINED> instruction: 0xffcf4f14
│ │  	movs	r5, r2
│ │  	stmia	r6!, {r1, r4, r5, r7}
│ │ -	vrsra.u8	q11, <illegal reg q7.5>, #1
│ │ +	vsubw.u8	q11, <illegal reg q15.5>, d6
│ │  	vrsubhn.i32	d28, q8, q12
│ │  	vqrdmlah.s<illegal width 8>	q10, <illegal reg q15.5>, d0[2]
│ │  	movs	r5, r2
│ │ -	add	r3, pc, #104	@ (adr r3, 38f00c <uniffi_pbcli_checksum_method_api_base@@Base+0x222788>)
│ │ +	add	r3, pc, #260	@ (adr r3, 38f0a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x222824>)
│ │  	vqshlu.s64	d22, d13, #16
│ │  			@ <UNDEFINED> instruction: 0xffcf4e94
│ │  	movs	r5, r2
│ │  	stmia	r6!, {r1, r4, r5}
│ │ -	vqrdmlah.s<illegal width 8>	<illegal reg q15.5>, <illegal reg q7.5>, d2[7]
│ │ -	vrshr.u16	<illegal reg q9.5>, q12, #16
│ │ +			@ <UNDEFINED> instruction: 0xffcffe95
│ │ +	vrshr.u64	d19, d15, #48
│ │  			@ <UNDEFINED> instruction: 0xffd1cbb2
│ │  			@ <UNDEFINED> instruction: 0xffcfeb9c
│ │  	movs	r4, r2
│ │  	bge.n	38f02c <uniffi_pbcli_checksum_method_api_base@@Base+0x2227a8>
│ │  	vqshrn.u16	d28, q11, #2
│ │  			@ <UNDEFINED> instruction: 0xffcfe920
│ │  	movs	r4, r2
│ │ @@ -1008192,15 +1008192,15 @@
│ │  	vmls.i<illegal width 8>	q14, <illegal reg q7.5>, d2[1]
│ │  	vsri.8	d30, d16, #1
│ │  	movs	r4, r2
│ │  	ldr	r4, [pc, #464]	@ (38f318 <uniffi_pbcli_checksum_method_api_base@@Base+0x222a94>)
│ │  	movs	r5, r2
│ │  	ldr	r4, [pc, #384]	@ (38f2cc <uniffi_pbcli_checksum_method_api_base@@Base+0x222a48>)
│ │  	movs	r5, r2
│ │ -	add	r0, pc, #712	@ (adr r0, 38f418 <uniffi_pbcli_checksum_method_api_base@@Base+0x222b94>)
│ │ +	add	r0, pc, #868	@ (adr r0, 38f4b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x222c30>)
│ │  	vsri.16	d22, d21, #16
│ │  			@ <UNDEFINED> instruction: 0xffcf4c30
│ │  	movs	r5, r2
│ │  	stmia	r3!, {r1, r2, r3, r6, r7}
│ │  	vaddl.u8	q8, d15, d2
│ │  	b.n	38f4a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x222c1e>
│ │  	movs	r4, #26
│ │ @@ -1008452,17 +1008452,17 @@
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	38fade <uniffi_pbcli_checksum_method_api_base@@Base+0x22325a>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r0, r3, r4, r5, r7, r8, fp, ip, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcfebdd
│ │  	vqshl.u64	<illegal reg q12.5>, q3, #14
│ │ -	vrsubhn.i16	d16, <illegal reg q15.5>, <illegal reg q10.5>
│ │ +	vmlsl.u<illegal width 8>	q8, d31, d0[3]
│ │  	vmlal.u16	<illegal reg q9.5>, d1, d1[1]
│ │ -	vqshlu.s8	q8, <illegal reg q12.5>, #7
│ │ +	vrsubhn.i16	d16, <illegal reg q15.5>, q8
│ │  	vsra.u16	d26, d21, #15
│ │  	vaddl.u8	<illegal reg q8.5>, d14, d5
│ │  	b.n	38f844 <uniffi_pbcli_checksum_method_api_base@@Base+0x222fc0>
│ │  	movs	r0, r0
│ │  	b.n	38fb06 <uniffi_pbcli_checksum_method_api_base@@Base+0x223282>
│ │  	movs	r1, r2
│ │  	b.n	38fa6c <uniffi_pbcli_checksum_method_api_base@@Base+0x2231e8>
│ │ @@ -1008807,19 +1008807,19 @@
│ │  	movs	r1, r0
│ │  	b.n	38fe06 <uniffi_pbcli_checksum_method_api_base@@Base+0x223582>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	38fe0e <uniffi_pbcli_checksum_method_api_base@@Base+0x22358a>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r0, r3, r7, r9, sl, ip, pc}
│ │ -	vqshlu.s64	d18, d2, #15
│ │ +	vqshlu.s64	d18, d25, #15
│ │  	vraddhn.i32	d25, <illegal reg q8.5>, q11
│ │ -	vrsra.u8	q8, <illegal reg q10.5>, #1
│ │ +	vrsra.u64	d16, d12, #49
│ │  			@ <UNDEFINED> instruction: 0xffd12f19
│ │ -			@ <UNDEFINED> instruction: 0xffcf0349
│ │ +	vrsra.u8	q8, q8, #1
│ │  	vmull.p<illegal width 16>	<illegal reg q12.5>, d1, d5
│ │  	vaddl.u8	q8, d14, d0
│ │  	b.n	38fe32 <uniffi_pbcli_checksum_method_api_base@@Base+0x2235ae>
│ │  	asrs	r1, r0, #32
│ │  	b.n	38fb78 <uniffi_pbcli_checksum_method_api_base@@Base+0x2232f4>
│ │  	movs	r0, r0
│ │  	b.n	38f1fe <uniffi_pbcli_checksum_method_api_base@@Base+0x22297a>
│ │ @@ -1008944,17 +1008944,17 @@
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	38ff4e <uniffi_pbcli_checksum_method_api_base@@Base+0x2236ca>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r0, r3, r6, r8, sl, ip, pc}
│ │  	vabdl.u8	<illegal reg q11.5>, d31, d4
│ │  			@ <UNDEFINED> instruction: 0xffcf9366
│ │ -	vrshr.u8	d16, d21, #1
│ │ +	vrshr.u8	q8, q6, #1
│ │  			@ <UNDEFINED> instruction: 0xffd12dd9
│ │ -	vsubl.u8	q8, d15, d9
│ │ +	vrshr.u8	d16, d16, #1
│ │  	vqdmulh.s16	<illegal reg q12.5>, <illegal reg q8.5>, d5[0]
│ │  	vaddl.u8	q8, d14, d0
│ │  	b.n	38ff72 <uniffi_pbcli_checksum_method_api_base@@Base+0x2236ee>
│ │  	movs	r0, r0
│ │  	b.n	38f33a <uniffi_pbcli_checksum_method_api_base@@Base+0x222ab6>
│ │  	movs	r0, r0
│ │  	b.n	38ff7a <uniffi_pbcli_checksum_method_api_base@@Base+0x2236f6>
│ │ @@ -1009377,15 +1009377,15 @@
│ │  	b.n	38ff56 <uniffi_pbcli_checksum_method_api_base@@Base+0x2236d2>
│ │  			@ <UNDEFINED> instruction: 0xb727
│ │  			@ <UNDEFINED> instruction: 0xebfb4000
│ │  	b.n	39035e <uniffi_pbcli_checksum_method_api_base@@Base+0x223ada>
│ │  	movs	r4, r0
│ │  	b.n	38ff62 <uniffi_pbcli_checksum_method_api_base@@Base+0x2236de>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r1, r5, r6, r8, sl, fp, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r3, r7, r8, sl, fp, sp, lr}
│ │  	vmla.i16	q8, q8, d4[1]
│ │  	movs	r0, r0
│ │  	lsls	r4, r7, #3
│ │  	movs	r0, r0
│ │  	lsls	r4, r5, #4
│ │  	movs	r0, r0
│ │  	lsls	r4, r1, #5
│ │ @@ -1010292,15 +1010292,15 @@
│ │  	str	r1, [r0, #0]
│ │  	asrs	r0, r0, #12
│ │  	movs	r6, r0
│ │  	b.n	39076e <uniffi_pbcli_checksum_method_api_base@@Base+0x223eea>
│ │  	beq.n	390450 <uniffi_pbcli_checksum_method_api_base@@Base+0x223bcc>
│ │  	b.n	3908c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x224044>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r8, sl, ip, pc}
│ │ +	ldmia.w	sp!, {r0, r3, r5, r8, sl, ip, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd048f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	39095c <uniffi_pbcli_checksum_method_api_base@@Base+0x2240d8>
│ │  	strb	r1, [r0, #0]
│ │  	b.n	390786 <uniffi_pbcli_checksum_method_api_base@@Base+0x223f02>
│ │  	asrs	r0, r5, #2
│ │  	b.n	38ff88 <uniffi_pbcli_checksum_method_api_base@@Base+0x223704>
│ │ @@ -1010378,16 +1010378,16 @@
│ │  	lsls	r4, r0, #22
│ │  	movs	r5, r0
│ │  	b.n	39082a <uniffi_pbcli_checksum_method_api_base@@Base+0x223fa6>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0}
│ │  	b.n	390c32 <uniffi_pbcli_checksum_method_api_base@@Base+0x2243ae>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, ip, sp, lr, pc}
│ │ -	vqrdmulh.s16	<illegal reg q13.5>, q8, d1[1]
│ │ +	ldmia.w	sp!, {r4, r5, ip, sp, lr, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffd0bdf0
│ │  	vaddl.u16	q8, d0, d0
│ │  	b.n	390022 <uniffi_pbcli_checksum_method_api_base@@Base+0x22379e>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r0, r1
│ │  	b.n	39002a <uniffi_pbcli_checksum_method_api_base@@Base+0x2237a6>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (3905d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x223d4c>)
│ │ @@ -1010865,20 +1010865,20 @@
│ │  	str	r0, [r0, #0]
│ │  	b.n	391086 <uniffi_pbcli_checksum_method_api_base@@Base+0x224802>
│ │  	vpmin.u<illegal width 64>	q15, q11, <illegal reg q15.5>
│ │  	str	r0, [sp, #0]
│ │  	b.n	39108e <uniffi_pbcli_checksum_method_api_base@@Base+0x22480a>
│ │  	vpmin.u<illegal width 64>	q15, q11, <illegal reg q15.5>
│ │  	ldrb	r4, [r6, #5]
│ │ -			@ <UNDEFINED> instruction: 0xffce8fba
│ │ -	vqrshrn.u32	d27, <illegal reg q0.5>, #16
│ │ +	vqrdmlsh.s<illegal width 8>	q12, q15, d1[4]
│ │ +	vqrshrn.u32	d27, q12, #16
│ │  			@ <UNDEFINED> instruction: 0xffd07ad4
│ │ -	vsra.u8	d25, d10, #2
│ │ -	vmull.u16	q15, d16, d25
│ │ -			@ <UNDEFINED> instruction: 0xffd0ba5d
│ │ +	vmla.f<illegal width 8>	<illegal reg q12.5>, q7, d1[0]
│ │ +			@ <UNDEFINED> instruction: 0xffd0ecd0
│ │ +	vmlsl.u16	<illegal reg q13.5>, d16, d4
│ │  			@ <UNDEFINED> instruction: 0xffd00cf6
│ │  			@ <UNDEFINED> instruction: 0xffcf4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	390e94 <uniffi_pbcli_checksum_method_api_base@@Base+0x224610>
│ │  	beq.n	39099c <uniffi_pbcli_checksum_method_api_base@@Base+0x224118>
│ │  	b.n	390e18 <uniffi_pbcli_checksum_method_api_base@@Base+0x224594>
│ │  	strh	r3, [r0, #0]
│ │ @@ -1011020,15 +1011020,15 @@
│ │  	beq.n	390ad8 <uniffi_pbcli_checksum_method_api_base@@Base+0x224254>
│ │  	b.n	390f40 <uniffi_pbcli_checksum_method_api_base@@Base+0x2246bc>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {ip, sp, lr}
│ │  	b.n	3911f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x22496e>
│ │  			@ <UNDEFINED> instruction: 0xffb7eaff
│ │  	lsls	r1, r1, #3
│ │ -			@ <UNDEFINED> instruction: 0xffcfeabd
│ │ +	vmull.u<illegal width 8>	q15, d31, d0[5]
│ │  			@ <UNDEFINED> instruction: 0xffd04c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	390fe0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22475c>
│ │  	str	r0, [r0, r0]
│ │  	b.n	390e0a <uniffi_pbcli_checksum_method_api_base@@Base+0x224586>
│ │  	movs	r0, r0
│ │  	b.n	3905f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x223d6c>
│ │ @@ -1011372,15 +1011372,15 @@
│ │  	b.n	39150e <uniffi_pbcli_checksum_method_api_base@@Base+0x224c8a>
│ │  	asrs	r4, r1, #32
│ │  	b.n	391452 <uniffi_pbcli_checksum_method_api_base@@Base+0x224bce>
│ │  			@ <UNDEFINED> instruction: 0xffe3eaff
│ │  	rev	r4, r5
│ │  	vmla.f<illegal width 8>	<illegal reg q12.5>, q15, d0[3]
│ │  			@ <UNDEFINED> instruction: 0xffcfbb38
│ │ -			@ <UNDEFINED> instruction: 0xffce5c59
│ │ +	vmull.u8	<illegal reg q10.5>, d30, d0
│ │  			@ <UNDEFINED> instruction: 0xffd0b9d8
│ │  	vmla.f<illegal width 8>	<illegal reg q12.5>, q7, d0[4]
│ │  			@ <UNDEFINED> instruction: 0xffcfb9fc
│ │  			@ <UNDEFINED> instruction: 0xffceba90
│ │  			@ <UNDEFINED> instruction: 0xffce3b01
│ │  	b.n	39153a <uniffi_pbcli_checksum_method_api_base@@Base+0x224cb6>
│ │  	lsls	r7, r0, #11
│ │ @@ -1011755,15 +1011755,15 @@
│ │  			@ <UNDEFINED> instruction: 0xffcfb768
│ │  	vaddl.u8	<illegal reg q14.5>, d30, d31
│ │  	vmul.i<illegal width 8>	<illegal reg q13.5>, <illegal reg q15.5>, d0[5]
│ │  	vsubl.u8	<illegal reg q14.5>, d14, d27
│ │  	vmlal.u8	<illegal reg q13.5>, d31, d8
│ │  	vabdl.u8	<illegal reg q13.5>, d30, d28
│ │  	vshr.u64	<illegal reg q14.5>, <illegal reg q5.5>, #50
│ │ -	vqrshrn.u16	d21, <illegal reg q10.5>, #1
│ │ +			@ <UNDEFINED> instruction: 0xffcf599c
│ │  	vrsubhn.i32	d27, q8, q2
│ │  			@ <UNDEFINED> instruction: 0xffcecfb3
│ │  	vmlsl.u<illegal width 8>	<illegal reg q13.5>, d31, d0[2]
│ │  	vaddl.u8	<illegal reg q14.5>, d14, d15
│ │  	vqshl.u8	d27, d0, #7
│ │  	vqshrun.s16	d20, q8, #2
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │ @@ -1012164,23 +1012164,23 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	391614 <uniffi_pbcli_checksum_method_api_base@@Base+0x224d90>
│ │  			@ <UNDEFINED> instruction: 0xffc7eaff
│ │  	lsrs	r2, r2, #32
│ │  	vmull.u<illegal width 8>	<illegal reg q15.5>, d31, d0[7]
│ │  	movs	r2, r2
│ │  	push	{r2}
│ │ -	vsli.8	<illegal reg q10.5>, <illegal reg q3.5>, #6
│ │ +	vsli.8	<illegal reg q10.5>, q15, #6
│ │  			@ <UNDEFINED> instruction: 0xffd06e7c
│ │ -	vshr.u64	q15, q7, #50
│ │ -	vsra.u64	q10, q13, #48
│ │ -			@ <UNDEFINED> instruction: 0xffd1dfba
│ │ +	vaddw.u8	q15, q7, d5
│ │ +	vsubl.u16	q10, d0, d17
│ │ +	vqrdmlsh.s16	<illegal reg q14.5>, <illegal reg q8.5>, d1[2]
│ │  	vsli.16	q8, q4, #0
│ │  			@ <UNDEFINED> instruction: 0xffd019bc
│ │  	vrshr.u64	<illegal reg q12.5>, <illegal reg q0.5>, #48
│ │ -	vmla.f<illegal width 8>	q10, <illegal reg q7.5>, d2[0]
│ │ +	vmla.f<illegal width 8>	q10, <illegal reg q7.5>, d1[6]
│ │  	vaddl.u16	q8, d1, d4
│ │  	b.n	39106c <uniffi_pbcli_checksum_method_api_base@@Base+0x2247e8>
│ │  	movs	r0, r0
│ │  	b.n	391650 <uniffi_pbcli_checksum_method_api_base@@Base+0x224dcc>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	vld4.8	{d0-d3}, [ip :64], r2
│ │  	ldr	r5, [pc, #960]	@ (3918fc <uniffi_pbcli_checksum_method_api_base@@Base+0x225078>)
│ │ @@ -1012603,28 +1012603,28 @@
│ │  	b.n	391c06 <uniffi_pbcli_checksum_method_api_base@@Base+0x225382>
│ │  	beq.n	3918f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x225074>
│ │  	b.n	391d60 <uniffi_pbcli_checksum_method_api_base@@Base+0x2254dc>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r3, r4, r7, sl, fp, sp, lr}
│ │  	vqshrn.u16	d18, q8, #2
│ │  	vmls.i<illegal width 8>	q8, <illegal reg q15.5>, d2[4]
│ │ -			@ <UNDEFINED> instruction: 0xffcf5e3a
│ │ +	vqrdmlah.s<illegal width 8>	<illegal reg q10.5>, <illegal reg q7.5>, d1[4]
│ │  			@ <UNDEFINED> instruction: 0xffd0f74c
│ │  	movs	r2, r2
│ │ -	lsrs	r1, r7, #7
│ │ -	vmull.p<illegal width 16>	<illegal reg q9.5>, d17, d18
│ │ +	lsrs	r0, r4, #8
│ │ +	vqrdmlah.s16	<illegal reg q9.5>, <illegal reg q8.5>, d1[1]
│ │  	vsra.u64	q8, <illegal reg q15.5>, #47
│ │ -			@ <UNDEFINED> instruction: 0xffcf9e5e
│ │ +	vmull.p8	<illegal reg q12.5>, d31, d5
│ │  	vsubw.u16	<illegal reg q12.5>, q8, d24
│ │  			@ <UNDEFINED> instruction: 0xffcff76f
│ │  	vsra.u64	d16, d20, #49
│ │  	vqrdmlsh.s16	q13, q0, d0[3]
│ │  	vmls.f<illegal width 8>	<illegal reg q8.5>, q15, d0[6]
│ │  			@ <UNDEFINED> instruction: 0xffd08ef5
│ │ -			@ <UNDEFINED> instruction: 0xffcf3d5e
│ │ +			@ <UNDEFINED> instruction: 0xffcf3d85
│ │  	vaddl.u16	q8, d1, d4
│ │  	b.n	391450 <uniffi_pbcli_checksum_method_api_base@@Base+0x224bcc>
│ │  	movs	r0, r0
│ │  	b.n	391a34 <uniffi_pbcli_checksum_method_api_base@@Base+0x2251b0>
│ │  	vrhadd.u16	d14, d14, d31
│ │  			@ <UNDEFINED> instruction: 0xf5e80012
│ │  	ldr	r5, [pc, #960]	@ (391ce0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22545c>)
│ │ @@ -1012856,15 +1012856,15 @@
│ │  	movs	r1, r0
│ │  	b.n	392262 <uniffi_pbcli_checksum_method_api_base@@Base+0x2259de>
│ │  	str	r0, [r0, #0]
│ │  	b.n	391630 <uniffi_pbcli_checksum_method_api_base@@Base+0x224dac>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r1, r3, r4, r5, r8, r9, sl, lr}
│ │  			@ <UNDEFINED> instruction: 0xffd19ba8
│ │ -	vabdl.u8	q13, d31, d16
│ │ +			@ <UNDEFINED> instruction: 0xffcfa7c7
│ │  	vqshlu.s64	q10, <illegal reg q11.5>, #16
│ │  			@ <UNDEFINED> instruction: 0xffd19b64
│ │  	vsubl.u8	<illegal reg q12.5>, d31, d4
│ │  	vqshrun.s16	d20, q8, #2
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	392064 <uniffi_pbcli_checksum_method_api_base@@Base+0x2257e0>
│ │  	asrs	r0, r6, #32
│ │ @@ -1013280,15 +1013280,15 @@
│ │  	b.n	392596 <uniffi_pbcli_checksum_method_api_base@@Base+0x225d12>
│ │  	ands	r1, r0
│ │  	asrs	r0, r4, #14
│ │  	movs	r4, r0
│ │  	b.n	39223e <uniffi_pbcli_checksum_method_api_base@@Base+0x2259ba>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r3, r4, r5, r6, r8, r9, sp, lr}
│ │ -	vmls.f<illegal width 8>	<illegal reg q14.5>, q15, d2[1]
│ │ +	vmls.f<illegal width 8>	<illegal reg q14.5>, q15, d1[7]
│ │  	vaddl.u16	q8, d0, d4
│ │  	b.n	391a4c <uniffi_pbcli_checksum_method_api_base@@Base+0x2251c8>
│ │  	movs	r0, r0
│ │  	b.n	392030 <uniffi_pbcli_checksum_method_api_base@@Base+0x2257ac>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	adds.w	r0, r4, #18
│ │  	movs	r0, r0
│ │ @@ -1013380,15 +1013380,15 @@
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	392326 <uniffi_pbcli_checksum_method_api_base@@Base+0x225aa2>
│ │  	beq.n	391ff8 <uniffi_pbcli_checksum_method_api_base@@Base+0x225774>
│ │  	b.n	392480 <uniffi_pbcli_checksum_method_api_base@@Base+0x225bfc>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r5, r8, ip, sp, lr, pc}
│ │  	movs	r2, r2
│ │ -	strb	r0, [r5, #18]
│ │ +	strb	r7, [r1, #19]
│ │  	vqrdmulh.s16	q12, q8, d6[1]
│ │  	vshr.u64	<illegal reg q15.5>, q14, #50
│ │  	movs	r2, r2
│ │  	ldr	r5, [pc, #960]	@ (3923c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x225b3c>)
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	392520 <uniffi_pbcli_checksum_method_api_base@@Base+0x225c9c>
│ │  	strh	r3, [r0, #0]
│ │ @@ -1014698,47 +1014698,47 @@
│ │  			@ <UNDEFINED> instruction: 0xebfd8044
│ │  	b.n	392584 <uniffi_pbcli_checksum_method_api_base@@Base+0x225d00>
│ │  	str	r0, [r2, r1]
│ │  	b.n	39268c <uniffi_pbcli_checksum_method_api_base@@Base+0x225e08>
│ │  	strb	r4, [r0, #1]
│ │  	b.n	392690 <uniffi_pbcli_checksum_method_api_base@@Base+0x225e0c>
│ │  			@ <UNDEFINED> instruction: 0xffb8eaff
│ │ -	strb	r4, [r3, #10]
│ │ +	strb	r3, [r0, #11]
│ │  			@ <UNDEFINED> instruction: 0xffd08bda
│ │ -	vrshr.u64	<illegal reg q11.5>, q14, #50
│ │ +	vsubw.u8	<illegal reg q11.5>, q7, d19
│ │  			@ <UNDEFINED> instruction: 0xffd08c3a
│ │ -	vsra.u64	d23, d4, #50
│ │ +	vsra.u64	d23, d27, #50
│ │  			@ <UNDEFINED> instruction: 0xffd08ad2
│ │ -			@ <UNDEFINED> instruction: 0xffce6ffc
│ │ +	vaddl.u8	<illegal reg q11.5>, d14, d19
│ │  	vqshrn.u32	d24, q13, #16
│ │ -			@ <UNDEFINED> instruction: 0xffce6f9c
│ │ +	vqrdmlsh.s<illegal width 8>	q11, q15, d3[0]
│ │  			@ <UNDEFINED> instruction: 0xffd088da
│ │ -	vmla.i<illegal width 8>	<illegal reg q11.5>, q15, d0[5]
│ │ -	vshr.u16	<illegal reg q11.5>, q10, #16
│ │ -			@ <UNDEFINED> instruction: 0xffd06cbc
│ │ +	vaddw.u8	<illegal reg q11.5>, q7, d11
│ │ +	vshr.u64	d23, d11, #48
│ │ +	vqdmulh.s16	q11, q8, d3[2]
│ │  	vsli.64	q12, q13, #16
│ │ -	vqdmulh.s<illegal width 8>	q11, q7, d0[4]
│ │ +	vmull.u8	q11, d30, d7
│ │  	vsli.64	d24, d14, #16
│ │ -			@ <UNDEFINED> instruction: 0xffce6c38
│ │ +			@ <UNDEFINED> instruction: 0xffce6c5f
│ │  	vsli.16	q12, q11, #0
│ │ -	vshll.u8	q11, d0, #6
│ │ +	vshll.u8	q11, d23, #6
│ │  			@ <UNDEFINED> instruction: 0xffd0834e
│ │ -			@ <UNDEFINED> instruction: 0xffce6d04
│ │ +			@ <UNDEFINED> instruction: 0xffce6d2b
│ │  	vmlsl.u16	q12, d0, d2[0]
│ │ -	vmull.u<illegal width 8>	q11, d14, d0[4]
│ │ +	vmlsl.u8	q11, d30, d7
│ │  	vrsra.u64	d24, d14, #48
│ │ -	vmlsl.u8	q11, d30, d12
│ │ +			@ <UNDEFINED> instruction: 0xffce6ab3
│ │  			@ <UNDEFINED> instruction: 0xffd083ca
│ │ -	vmul.f<illegal width 8>	q11, q7, d0[6]
│ │ +			@ <UNDEFINED> instruction: 0xffce698f
│ │  	vsubl.u16	q12, d16, d22
│ │  	vmls.f<illegal width 8>	q15, q15, d0[2]
│ │  	movs	r2, r2
│ │ -	ldr	r4, [r1, #20]
│ │ +	ldr	r3, [r6, #20]
│ │  	vsubl.u16	q12, d16, d10
│ │ -	vsubl.u8	<illegal reg q11.5>, d14, d28
│ │ +	vrshr.u8	<illegal reg q11.5>, <illegal reg q1.5>, #2
│ │  			@ <UNDEFINED> instruction: 0xffd04ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3930fc <uniffi_pbcli_checksum_method_api_base@@Base+0x226878>
│ │  	beq.n	392cac <uniffi_pbcli_checksum_method_api_base@@Base+0x226428>
│ │  	b.n	393080 <uniffi_pbcli_checksum_method_api_base@@Base+0x2267fc>
│ │  	add	r0, pc, #12	@ (adr r0, 392bf4 <uniffi_pbcli_checksum_method_api_base@@Base+0x226370>)
│ │  	b.n	392f2a <uniffi_pbcli_checksum_method_api_base@@Base+0x2266a6>
│ │ @@ -1015623,18 +1015623,18 @@
│ │  	strh	r4, [r5, #0]
│ │  	b.n	392e9c <uniffi_pbcli_checksum_method_api_base@@Base+0x226618>
│ │  	asrs	r0, r0, #32
│ │  	b.n	392e66 <uniffi_pbcli_checksum_method_api_base@@Base+0x2265e2>
│ │  	mrc2	10, 4, lr, cr7, cr15, {7}	@ <UNPREDICTABLE>
│ │  	b.n	393b3c <uniffi_pbcli_checksum_method_api_base@@Base+0x2272b8>
│ │  	movs	r2, r2
│ │ -	str	r0, [r1, #92]	@ 0x5c
│ │ -	vqshlu.s64	q11, q2, #16
│ │ +	str	r7, [r5, #92]	@ 0x5c
│ │ +	vqshlu.s64	q11, <illegal reg q13.5>, #16
│ │  			@ <UNDEFINED> instruction: 0xffd0cbfd
│ │ -	vqshlu.s64	d22, d8, #14
│ │ +	vqshlu.s64	d22, d31, #14
│ │  	vsubl.u16	q15, d16, d0
│ │  	movs	r2, r2
│ │  	ldr	r4, [pc, #448]	@ (393544 <uniffi_pbcli_checksum_method_api_base@@Base+0x226cc0>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3938a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x227020>
│ │  	beq.n	3933bc <uniffi_pbcli_checksum_method_api_base@@Base+0x226b38>
│ │  	b.n	393828 <uniffi_pbcli_checksum_method_api_base@@Base+0x226fa4>
│ │ @@ -1017699,16 +1017699,16 @@
│ │  	movs	r0, #0
│ │  	b.n	394cd6 <uniffi_pbcli_checksum_method_api_base@@Base+0x228452>
│ │  	lsrs	r7, r6, #10
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	394cde <uniffi_pbcli_checksum_method_api_base@@Base+0x22845a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r1, r2, r3, r4, r6, r8, ip, sp, lr}
│ │ -	vqshl.u64	<illegal reg q14.5>, <illegal reg q15.5>, #15
│ │ -	vmul.f16	q13, q0, d4[2]
│ │ +	vmlal.u8	<illegal reg q14.5>, d15, d22
│ │ +			@ <UNDEFINED> instruction: 0xffd0a98b
│ │  	vqshrun.s32	d20, q8, #16
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	394ad0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22824c>
│ │  	ands	r1, r0
│ │  	b.n	3948fa <uniffi_pbcli_checksum_method_api_base@@Base+0x228076>
│ │  	asrs	r0, r7, #1
│ │  	b.n	3940fc <uniffi_pbcli_checksum_method_api_base@@Base+0x227878>
│ │ @@ -1017763,16 +1017763,16 @@
│ │  	movs	r0, #0
│ │  	b.n	394d6e <uniffi_pbcli_checksum_method_api_base@@Base+0x2284ea>
│ │  	lsrs	r1, r2, #10
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	394d76 <uniffi_pbcli_checksum_method_api_base@@Base+0x2284f2>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r1, r2, r3, r4, r5, r7, ip, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffcfd767
│ │ -	vmlal.u16	q9, d16, d2[1]
│ │ +	vabdl.u8	<illegal reg q14.5>, d31, d14
│ │ +	vrshr.u64	q9, <illegal reg q8.5>, #48
│ │  	vaddl.u16	q8, d0, d4
│ │  	b.n	394188 <uniffi_pbcli_checksum_method_api_base@@Base+0x227904>
│ │  	movs	r0, r0
│ │  	b.n	39476c <uniffi_pbcli_checksum_method_api_base@@Base+0x227ee8>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	bpl.n	39464c <uniffi_pbcli_checksum_method_api_base@@Base+0x227dc8>
│ │  	movs	r2, r2
│ │ @@ -1018808,15 +1018808,15 @@
│ │  	movs	r4, r1
│ │  	b.n	394a8a <uniffi_pbcli_checksum_method_api_base@@Base+0x228206>
│ │  	ands	r0, r2
│ │  	b.n	394a8e <uniffi_pbcli_checksum_method_api_base@@Base+0x22820a>
│ │  	movs	r5, r0
│ │  	b.n	3952c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x228a42>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r8, r9, sl, fp, sp}
│ │ +	ldmia.w	sp!, {r5, r6, r8, r9, sl, fp, sp}
│ │  	vaddl.u16	q8, d0, d0
│ │  	b.n	395632 <uniffi_pbcli_checksum_method_api_base@@Base+0x228dae>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (395058 <uniffi_pbcli_checksum_method_api_base@@Base+0x2287d4>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3954b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x228c34>
│ │  	ands	r0, r0
│ │ @@ -1018847,15 +1018847,15 @@
│ │  	b.n	395716 <uniffi_pbcli_checksum_method_api_base@@Base+0x228e92>
│ │  	movs	r0, #5
│ │  	b.n	39531a <uniffi_pbcli_checksum_method_api_base@@Base+0x228a96>
│ │  	adds	r0, #53	@ 0x35
│ │  	b.n	39571e <uniffi_pbcli_checksum_method_api_base@@Base+0x228e9a>
│ │  	ldr	r0, [pc, #192]	@ (3950a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22881c>)
│ │  	ldmia.w	sp!, {r0, r2, r4, r6, sp}
│ │ -			@ <UNDEFINED> instruction: 0xeafe2ecd
│ │ +			@ <UNDEFINED> instruction: 0xeafe2ef4
│ │  			@ <UNDEFINED> instruction: 0xffd048f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	39550c <uniffi_pbcli_checksum_method_api_base@@Base+0x228c88>
│ │  	str	r0, [r0, r0]
│ │  	b.n	395336 <uniffi_pbcli_checksum_method_api_base@@Base+0x228ab2>
│ │  			@ <UNDEFINED> instruction: 0xea11ebff
│ │  	movs	r0, r0
│ │ @@ -1018959,17 +1018959,17 @@
│ │  	b.n	39580e <uniffi_pbcli_checksum_method_api_base@@Base+0x228f8a>
│ │  	subs	r6, r7, #5
│ │  			@ <UNDEFINED> instruction: 0xebfe6000
│ │  	b.n	395816 <uniffi_pbcli_checksum_method_api_base@@Base+0x228f92>
│ │  	movs	r6, r0
│ │  	b.n	39541a <uniffi_pbcli_checksum_method_api_base@@Base+0x228b96>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r6, r9, sl, fp, sp}
│ │ -			@ <UNDEFINED> instruction: 0xffd02e1d
│ │ -	vqrdmulh.s16	q9, q8, d1[1]
│ │ +	ldmia.w	sp!, {r7, r9, sl, fp, sp}
│ │ +	vqrdmlah.s16	q9, q0, d4[0]
│ │ +			@ <UNDEFINED> instruction: 0xffd02df0
│ │  			@ <UNDEFINED> instruction: 0xffd04c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	39560c <uniffi_pbcli_checksum_method_api_base@@Base+0x228d88>
│ │  	beq.n	395114 <uniffi_pbcli_checksum_method_api_base@@Base+0x228890>
│ │  	b.n	395590 <uniffi_pbcli_checksum_method_api_base@@Base+0x228d0c>
│ │  	stmia	r0!, {r3}
│ │  	b.n	394c30 <uniffi_pbcli_checksum_method_api_base@@Base+0x2283ac>
│ │ @@ -1019092,15 +1019092,15 @@
│ │  	movs	r0, r0
│ │  	b.n	3958b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22902c>
│ │  	str	r1, [r0, r0]
│ │  	asrs	r0, r0, #12
│ │  	movs	r5, r0
│ │  	b.n	39554e <uniffi_pbcli_checksum_method_api_base@@Base+0x228cca>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r6, r7, sl, fp, sp}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r8, sl, fp, sp}
│ │  			@ <UNDEFINED> instruction: 0xffd04d9c
│ │  			@ <UNDEFINED> instruction: 0xffcf48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	39573c <uniffi_pbcli_checksum_method_api_base@@Base+0x228eb8>
│ │  	strb	r2, [r0, #0]
│ │  	b.n	395566 <uniffi_pbcli_checksum_method_api_base@@Base+0x228ce2>
│ │  	str	r1, [r0, r0]
│ │ @@ -1019285,17 +1019285,17 @@
│ │  	b.n	395af2 <uniffi_pbcli_checksum_method_api_base@@Base+0x22926e>
│ │  	lsls	r0, r6, #28
│ │  			@ <UNDEFINED> instruction: 0xebfd0005
│ │  	b.n	3956fa <uniffi_pbcli_checksum_method_api_base@@Base+0x228e76>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r6, r7, r8, fp, ip, pc}
│ │  			@ <UNDEFINED> instruction: 0xffce8cd0
│ │ -	vsra.u64	d16, d6, #50
│ │ -	vmull.u16	q9, d17, d1[3]
│ │ -	vabdl.u16	<illegal reg q15.5>, d0, d31
│ │ +	vsra.u64	d16, d29, #50
│ │ +			@ <UNDEFINED> instruction: 0xffd12b10
│ │ +	vqshl.u16	<illegal reg q15.5>, q3, #0
│ │  	vaddl.u16	q8, d0, d4
│ │  	b.n	394f14 <uniffi_pbcli_checksum_method_api_base@@Base+0x228690>
│ │  	movs	r0, r0
│ │  	b.n	3954f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x228c74>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldmia	r5!, {r3, r6, r7}
│ │  	movs	r2, r2
│ │ @@ -1019481,23 +1019481,23 @@
│ │  	lsls	r2, r0, #27
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3958b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x22902e>
│ │  	beq.n	395594 <uniffi_pbcli_checksum_method_api_base@@Base+0x228d10>
│ │  	b.n	395a0c <uniffi_pbcli_checksum_method_api_base@@Base+0x229188>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r7, fp, ip, pc}
│ │ -	vshll.u8	q9, d25, #6
│ │ +	vmull.u<illegal width 8>	q9, d14, d0[4]
│ │  			@ <UNDEFINED> instruction: 0xffd04af8
│ │  	vmls.f<illegal width 8>	<illegal reg q10.5>, <illegal reg q7.5>, d1[2]
│ │ -	vmul.f<illegal width 8>	q9, <illegal reg q7.5>, d1[3]
│ │ +	vqrshrn.u16	d18, q10, #1
│ │  	vmlsl.u16	q10, d0, d12
│ │ -	vshr.u8	d16, d14, #1
│ │ -	vqshrn.u32	d18, <illegal reg q8.5>, #15
│ │ +	vmla.i<illegal width 8>	q8, <illegal reg q7.5>, d1[1]
│ │ +	vqrshrn.u32	d18, q4, #15
│ │  			@ <UNDEFINED> instruction: 0xffd049f0
│ │ -	vqrshrn.u16	d18, <illegal reg q12.5>, #1
│ │ +			@ <UNDEFINED> instruction: 0xffcf29a0
│ │  	vmovl.u16	q10, d24
│ │  	vaddl.u8	q8, d15, d4
│ │  	b.n	3950e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x228864>
│ │  	movs	r0, r0
│ │  	b.n	3956cc <uniffi_pbcli_checksum_method_api_base@@Base+0x228e48>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldmia	r4!, {r2, r6}
│ │ @@ -1019546,15 +1019546,15 @@
│ │  	movs	r4, r1
│ │  	b.n	395122 <uniffi_pbcli_checksum_method_api_base@@Base+0x22889e>
│ │  	ands	r0, r2
│ │  	b.n	395126 <uniffi_pbcli_checksum_method_api_base@@Base+0x2288a2>
│ │  	movs	r5, r0
│ │  	b.n	39595e <uniffi_pbcli_checksum_method_api_base@@Base+0x2290da>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r5, r7, fp, sp}
│ │ +	ldmia.w	sp!, {r3, r6, r7, fp, sp}
│ │  	vmlal.u16	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	39596e <uniffi_pbcli_checksum_method_api_base@@Base+0x2290ea>
│ │  	beq.n	395650 <uniffi_pbcli_checksum_method_api_base@@Base+0x228dcc>
│ │  	b.n	395acc <uniffi_pbcli_checksum_method_api_base@@Base+0x229248>
│ │  	asrs	r0, r4, #1
│ │  	b.n	395d76 <uniffi_pbcli_checksum_method_api_base@@Base+0x2294f2>
│ │ @@ -1019624,15 +1019624,15 @@
│ │  	movs	r4, r1
│ │  	b.n	3951d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x22894e>
│ │  	ands	r0, r2
│ │  	b.n	3951d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x228952>
│ │  	movs	r5, r0
│ │  	b.n	395a0e <uniffi_pbcli_checksum_method_api_base@@Base+0x22918a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r4, r5, r6, r7, r8, r9, sl, sp}
│ │ +	ldmia.w	sp!, {r3, r4, fp, sp}
│ │  	vmlal.u16	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	395a1e <uniffi_pbcli_checksum_method_api_base@@Base+0x22919a>
│ │  	beq.n	395700 <uniffi_pbcli_checksum_method_api_base@@Base+0x228e7c>
│ │  	b.n	395b7c <uniffi_pbcli_checksum_method_api_base@@Base+0x2292f8>
│ │  	asrs	r0, r4, #1
│ │  	b.n	395e26 <uniffi_pbcli_checksum_method_api_base@@Base+0x2295a2>
│ │ @@ -1019781,18 +1019781,18 @@
│ │  	b.n	395f62 <uniffi_pbcli_checksum_method_api_base@@Base+0x2296de>
│ │  	lsls	r4, r2, #24
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	395f6a <uniffi_pbcli_checksum_method_api_base@@Base+0x2296e6>
│ │  	beq.n	395864 <uniffi_pbcli_checksum_method_api_base@@Base+0x228fe0>
│ │  	b.n	395cc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x229440>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r7, r9, sl, sp}
│ │ -	vmlal.u16	<illegal reg q15.5>, d16, d5[1]
│ │ -	vqshlu.s16	q9, <illegal reg q10.5>, #0
│ │ -	vsubl.u16	<illegal reg q15.5>, d16, d21
│ │ +	ldmia.w	sp!, {r2, r6, r7, r9, sl, sp}
│ │ +	vrshr.u64	<illegal reg q15.5>, q10, #48
│ │ +	vqshlu.s64	d18, d12, #16
│ │ +	vmlal.u16	<illegal reg q15.5>, d16, d4[1]
│ │  	vaddl.u16	q8, d0, d4
│ │  	b.n	395384 <uniffi_pbcli_checksum_method_api_base@@Base+0x228b00>
│ │  	movs	r0, r0
│ │  	b.n	395968 <uniffi_pbcli_checksum_method_api_base@@Base+0x2290e4>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldmia	r1!, {r3, r4, r5, r6, r7}
│ │  	movs	r2, r2
│ │ @@ -1020030,17 +1020030,17 @@
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	396186 <uniffi_pbcli_checksum_method_api_base@@Base+0x229902>
│ │  	movs	r0, r0
│ │  	b.n	395552 <uniffi_pbcli_checksum_method_api_base@@Base+0x228cce>
│ │  	beq.n	395a84 <uniffi_pbcli_checksum_method_api_base@@Base+0x229200>
│ │  	b.n	395ee4 <uniffi_pbcli_checksum_method_api_base@@Base+0x229660>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r2, r3, ip, sp, lr}
│ │ -	vraddhn.i32	d19, q0, q1
│ │ -	vmull.u16	q9, d0, d7
│ │ +	ldmia.w	sp!, {r0, r2, r4, r5, ip, sp, lr}
│ │ +	vraddhn.i32	d19, q0, <illegal reg q12.5>
│ │ +	vmull.u16	q9, d0, d30
│ │  			@ <UNDEFINED> instruction: 0xffd04ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	395f80 <uniffi_pbcli_checksum_method_api_base@@Base+0x2296fc>
│ │  	beq.n	395b60 <uniffi_pbcli_checksum_method_api_base@@Base+0x2292dc>
│ │  	b.n	395f04 <uniffi_pbcli_checksum_method_api_base@@Base+0x229680>
│ │  	ands	r0, r0
│ │  	b.n	395dae <uniffi_pbcli_checksum_method_api_base@@Base+0x22952a>
│ │ @@ -1021577,15 +1021577,15 @@
│ │  	movs	r4, r2
│ │  	ldr	r0, [r2, #76]	@ 0x4c
│ │  	movs	r4, r2
│ │  	ldr	r4, [r4, #76]	@ 0x4c
│ │  	movs	r4, r2
│ │  	ldr	r4, [r5, #68]	@ 0x44
│ │  	movs	r4, r2
│ │ -	strh	r3, [r6, #62]	@ 0x3e
│ │ +	ldrh	r2, [r3, #0]
│ │  	vrsubhn.i32	d20, q8, <illegal reg q15.5>
│ │  			@ <UNDEFINED> instruction: 0xffce4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	396c94 <uniffi_pbcli_checksum_method_api_base@@Base+0x22a410>
│ │  	cmp	r5, #6
│ │  	b.n	396ebe <uniffi_pbcli_checksum_method_api_base@@Base+0x22a63a>
│ │  	ands	r0, r0
│ │ @@ -1022009,21 +1022009,21 @@
│ │  	lsls	r0, r3, #5
│ │  			@ <UNDEFINED> instruction: 0xebfdff65
│ │  			@ <UNDEFINED> instruction: 0xeaff0e54
│ │  	movs	r0, r0
│ │  	lsrs	r4, r5, #25
│ │  	movs	r0, r0
│ │  	cmp	r4, #57	@ 0x39
│ │ -			@ <UNDEFINED> instruction: 0xffce6ed4
│ │ +			@ <UNDEFINED> instruction: 0xffce6efb
│ │  			@ <UNDEFINED> instruction: 0xffd02ad5
│ │ -			@ <UNDEFINED> instruction: 0xffce6d70
│ │ +			@ <UNDEFINED> instruction: 0xffce6d97
│ │  			@ <UNDEFINED> instruction: 0xffd02bf1
│ │ -	vmull.p8	q11, d30, d12
│ │ +			@ <UNDEFINED> instruction: 0xffce6eb3
│ │  			@ <UNDEFINED> instruction: 0xffd02af1
│ │ -			@ <UNDEFINED> instruction: 0xffce6d8c
│ │ +			@ <UNDEFINED> instruction: 0xffce6db3
│ │  			@ <UNDEFINED> instruction: 0xffd048f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	397064 <uniffi_pbcli_checksum_method_api_base@@Base+0x22a7e0>
│ │  	str	r2, [r0, #0]
│ │  	b.n	396e8e <uniffi_pbcli_checksum_method_api_base@@Base+0x22a60a>
│ │  	strb	r1, [r0, #0]
│ │  	b.n	396e92 <uniffi_pbcli_checksum_method_api_base@@Base+0x22a60e>
│ │ @@ -1022275,17 +1022275,17 @@
│ │  	movs	r0, #0
│ │  	b.n	3974ba <uniffi_pbcli_checksum_method_api_base@@Base+0x22ac36>
│ │  	lsls	r6, r7, #2
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3970c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x22a83e>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, r3, r5, r6, r7, fp, sp}
│ │ -	vqshlu.s64	q8, q3, #14
│ │ +	vqshlu.s64	q8, <illegal reg q14.5>, #14
│ │  	vmul.i16	q9, q0, d5[3]
│ │ -	vqshlu.s8	q8, q5, #6
│ │ +	vrsubhn.i16	d16, q15, <illegal reg q0.5>
│ │  	vaddl.u16	q8, d0, d0
│ │  	b.n	39743a <uniffi_pbcli_checksum_method_api_base@@Base+0x22abb6>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (396de0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22a55c>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3972c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22aa3c>
│ │  	ands	r0, r0
│ │ @@ -1022724,18 +1022724,18 @@
│ │  	movs	r0, #80	@ 0x50
│ │  	b.n	396cb8 <uniffi_pbcli_checksum_method_api_base@@Base+0x22a434>
│ │  	movs	r0, r0
│ │  	b.n	39729c <uniffi_pbcli_checksum_method_api_base@@Base+0x22aa18>
│ │  	movs	r0, #2
│ │  	b.n	3972a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22aa1c>
│ │  			@ <UNDEFINED> instruction: 0xffb1eaff
│ │ -	ldrsh	r5, [r4, r0]
│ │ +	ldrsh	r4, [r1, r1]
│ │  	vmlsl.u16	q9, d0, d1[0]
│ │  			@ <UNDEFINED> instruction: 0xffce5c7d
│ │ -	vsli.64	q15, q13, #15
│ │ +	vrsubhn.i16	d30, <illegal reg q7.5>, <illegal reg q8.5>
│ │  	vrsubhn.i32	d18, q0, <illegal reg q10.5>
│ │  	vqdmulh.s<illegal width 8>	<illegal reg q10.5>, q7, d1[4]
│ │  	vmla.i<illegal width 8>	<illegal reg q11.5>, <illegal reg q15.5>, d0[5]
│ │  	vabal.u8	q9, d30, d5
│ │  			@ <UNDEFINED> instruction: 0xffce5bc1
│ │  	vmul.f<illegal width 8>	<illegal reg q8.5>, <illegal reg q7.5>, d3[2]
│ │  	vqshlu.s8	q9, <illegal reg q6.5>, #6
│ │ @@ -1023000,29 +1023000,29 @@
│ │  	movs	r1, r7
│ │  	b.n	397b4a <uniffi_pbcli_checksum_method_api_base@@Base+0x22b2c6>
│ │  	asrs	r1, r5, #1
│ │  	b.n	397b4e <uniffi_pbcli_checksum_method_api_base@@Base+0x22b2ca>
│ │  			@ <UNDEFINED> instruction: 0xffe4eaff
│ │  	ldrb	r1, [r1, #10]
│ │  			@ <UNDEFINED> instruction: 0xffce2361
│ │ -	vqdmulh.s<illegal width 8>	q8, q7, d0[2]
│ │ +	vqdmulh.s<illegal width 8>	q8, q7, d3[7]
│ │  	vrsra.u16	d18, d25, #16
│ │ -	vmull.u8	q8, d14, d16
│ │ +	vqdmulh.s<illegal width 8>	q8, q7, d3[1]
│ │  	vrsra.u16	d18, d13, #16
│ │ -	vmull.u8	q8, d14, d4
│ │ +	vmull.u8	q8, d14, d27
│ │  	vsubl.u16	q9, d0, d1
│ │ -	vmull.u<illegal width 8>	q8, d30, d0[6]
│ │ -	vmlsl.u16	<illegal reg q10.5>, d0, d13
│ │ +			@ <UNDEFINED> instruction: 0xffce0b0f
│ │ +	vmovl.u16	<illegal reg q10.5>, d20
│ │  	vrshr.u16	q9, <illegal reg q4.5>, #16
│ │ -			@ <UNDEFINED> instruction: 0xffce0b40
│ │ -	vsra.u64	d30, d26, #48
│ │ +			@ <UNDEFINED> instruction: 0xffce0b67
│ │ +	vmla.f16	q15, q8, d1[2]
│ │  	vrshr.u16	d18, d29, #16
│ │ -			@ <UNDEFINED> instruction: 0xffce0b24
│ │ +			@ <UNDEFINED> instruction: 0xffce0b4b
│ │  	vsra.u64	q9, <illegal reg q2.5>, #48
│ │ -			@ <UNDEFINED> instruction: 0xffce0abc
│ │ +	vmull.u<illegal width 8>	q8, d30, d3[4]
│ │  	vaddl.u16	q8, d0, d4
│ │  	b.n	396f98 <uniffi_pbcli_checksum_method_api_base@@Base+0x22a714>
│ │  	movs	r0, r0
│ │  	b.n	39757c <uniffi_pbcli_checksum_method_api_base@@Base+0x22acf8>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	add	r7, sp, #704	@ 0x2c0
│ │  	movs	r2, r2
│ │ @@ -1023998,15 +1023998,15 @@
│ │  	b.n	398422 <uniffi_pbcli_checksum_method_api_base@@Base+0x22bb9e>
│ │  	stc2l	11, cr14, [r4], #1008	@ 0x3f0	@ <UNPREDICTABLE>
│ │  	movs	r5, r0
│ │  	b.n	39802a <uniffi_pbcli_checksum_method_api_base@@Base+0x22b7a6>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r4, r7, ip, sp, lr}
│ │  	vsubw.u8	q11, q15, d16
│ │ -	vmul.i<illegal width 8>	<illegal reg q14.5>, q7, d2[5]
│ │ +	vmlal.u8	<illegal reg q14.5>, d30, d13
│ │  	vsubl.u16	q14, d0, d29
│ │  			@ <UNDEFINED> instruction: 0xffce4b50
│ │  	vaddl.u8	q8, d14, d4
│ │  	b.n	397844 <uniffi_pbcli_checksum_method_api_base@@Base+0x22afc0>
│ │  	movs	r0, r0
│ │  	b.n	397e28 <uniffi_pbcli_checksum_method_api_base@@Base+0x22b5a4>
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -1024176,21 +1024176,21 @@
│ │  	movs	r6, r0
│ │  	b.n	3981ba <uniffi_pbcli_checksum_method_api_base@@Base+0x22b936>
│ │  	beq.n	397e9c <uniffi_pbcli_checksum_method_api_base@@Base+0x22b618>
│ │  	b.n	398314 <uniffi_pbcli_checksum_method_api_base@@Base+0x22ba90>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r4, r6, r8, r9, sl, fp, sp, lr}
│ │  	vshr.u64	q14, <illegal reg q6.5>, #50
│ │ -	vqdmulh.s<illegal width 8>	q14, q15, d3[3]
│ │ +			@ <UNDEFINED> instruction: 0xffceccf6
│ │  			@ <UNDEFINED> instruction: 0xffd02c39
│ │  	vshr.u64	d28, d25, #49
│ │ -	vmull.u8	q14, d30, d27
│ │ -	vqshl.u16	d29, d6, #0
│ │ +			@ <UNDEFINED> instruction: 0xffceccd2
│ │ +	vqshl.u16	d29, d29, #0
│ │  	vshr.u64	d28, d13, #48
│ │ -	vmull.u8	q14, d30, d15
│ │ +			@ <UNDEFINED> instruction: 0xffceccb6
│ │  	vaddl.u16	q8, d0, d4
│ │  	b.n	3979e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x22b164>
│ │  	movs	r0, r0
│ │  	b.n	397fcc <uniffi_pbcli_checksum_method_api_base@@Base+0x22b748>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	add	r0, sp, #0
│ │  	movs	r2, r2
│ │ @@ -1024440,15 +1024440,15 @@
│ │  	movs	r0, #0
│ │  	b.n	398816 <uniffi_pbcli_checksum_method_api_base@@Base+0x22bf92>
│ │  			@ <UNDEFINED> instruction: 0xfbe7ebfc
│ │  	movs	r0, r0
│ │  	b.n	39881e <uniffi_pbcli_checksum_method_api_base@@Base+0x22bf9a>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, r2, r4, r5, r9, sl, fp, ip, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffce57c6
│ │ +			@ <UNDEFINED> instruction: 0xffce57ed
│ │  	vaddl.u16	q8, d0, d4
│ │  	b.n	397c2c <uniffi_pbcli_checksum_method_api_base@@Base+0x22b3a8>
│ │  	movs	r0, r0
│ │  	b.n	398210 <uniffi_pbcli_checksum_method_api_base@@Base+0x22b98c>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	add	r6, pc, #48	@ (adr r6, 398128 <uniffi_pbcli_checksum_method_api_base@@Base+0x22b8a4>)
│ │  	movs	r2, r2
│ │ @@ -1024561,20 +1024561,20 @@
│ │  	b.n	398522 <uniffi_pbcli_checksum_method_api_base@@Base+0x22bc9e>
│ │  	movs	r0, #7
│ │  	b.n	398526 <uniffi_pbcli_checksum_method_api_base@@Base+0x22bca2>
│ │  	lsls	r2, r2, #1
│ │  			@ <UNDEFINED> instruction: 0xeb00d018
│ │  	b.n	398684 <uniffi_pbcli_checksum_method_api_base@@Base+0x22be00>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r2, r3, r4, r6, r7, fp, ip, sp}
│ │ +	ldmia.w	sp!, {r0, r1, r8, fp, ip, sp}
│ │  	vmlal.u16	q9, d16, d5[2]
│ │  	vqdmulh.s<illegal width 8>	q8, q15, d2[5]
│ │  			@ <UNDEFINED> instruction: 0xffceb348
│ │ -			@ <UNDEFINED> instruction: 0xffcf38d4
│ │ -	vsra.u64	q8, <illegal reg q7.5>, #48
│ │ +			@ <UNDEFINED> instruction: 0xffcf38fb
│ │ +	vsubl.u16	q8, d0, d6
│ │  	vmlal.u16	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	398552 <uniffi_pbcli_checksum_method_api_base@@Base+0x22bcce>
│ │  	stmia	r0!, {r0}
│ │  	b.n	398556 <uniffi_pbcli_checksum_method_api_base@@Base+0x22bcd2>
│ │  	asrs	r0, r0, #32
│ │  	b.n	39855a <uniffi_pbcli_checksum_method_api_base@@Base+0x22bcd6>
│ │ @@ -1024931,17 +1024931,17 @@
│ │  	b.n	39806a <uniffi_pbcli_checksum_method_api_base@@Base+0x22b7e6>
│ │  	str	r1, [sp, #648]	@ 0x288
│ │  			@ <UNDEFINED> instruction: 0xebfd0005
│ │  	b.n	398882 <uniffi_pbcli_checksum_method_api_base@@Base+0x22bffe>
│ │  	beq.n	39857c <uniffi_pbcli_checksum_method_api_base@@Base+0x22bcf8>
│ │  	b.n	3989dc <uniffi_pbcli_checksum_method_api_base@@Base+0x22c158>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r3, r6, r7, sl, ip}
│ │ +	ldmia.w	sp!, {r0, r4, r5, r6, r7, sl, ip}
│ │  	vmla.f16	<illegal reg q12.5>, q0, d6[0]
│ │ -			@ <UNDEFINED> instruction: 0xffcedef5
│ │ +			@ <UNDEFINED> instruction: 0xffcedf1c
│ │  			@ <UNDEFINED> instruction: 0xffcfbad0
│ │  			@ <UNDEFINED> instruction: 0xffd54c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	398a7c <uniffi_pbcli_checksum_method_api_base@@Base+0x22c1f8>
│ │  	ands	r0, r0
│ │  	b.n	3988a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x22c022>
│ │  	lsrs	r7, r1, #11
│ │ @@ -1025714,15 +1025714,15 @@
│ │  	lsls	r0, r2, #1
│ │  	b.n	398792 <uniffi_pbcli_checksum_method_api_base@@Base+0x22bf0e>
│ │  	movs	r5, r0
│ │  	b.n	398f4e <uniffi_pbcli_checksum_method_api_base@@Base+0x22c6ca>
│ │  	beq.n	398c20 <uniffi_pbcli_checksum_method_api_base@@Base+0x22c39c>
│ │  	b.n	3990a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x22c824>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r6, r7, sl, fp, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r8, sl, fp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffd04c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	39913c <uniffi_pbcli_checksum_method_api_base@@Base+0x22c8b8>
│ │  	beq.n	398c44 <uniffi_pbcli_checksum_method_api_base@@Base+0x22c3c0>
│ │  	b.n	3990c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22c83c>
│ │  	stmia	r0!, {r3}
│ │  	b.n	398760 <uniffi_pbcli_checksum_method_api_base@@Base+0x22bedc>
│ │ @@ -1025956,24 +1025956,24 @@
│ │  	b.n	3994d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cc4e>
│ │  	movs	r7, r0
│ │  	asrs	r1, r0, #15
│ │  	movs	r0, r1
│ │  	b.n	399356 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cad2>
│ │  			@ <UNDEFINED> instruction: 0xffd21aff
│ │  			@ <UNDEFINED> instruction: 0xffd3eaff
│ │ -	ldr	r3, [pc, #828]	@ (39917c <uniffi_pbcli_checksum_method_api_base@@Base+0x22c8f8>)
│ │ +	ldr	r3, [pc, #984]	@ (399218 <uniffi_pbcli_checksum_method_api_base@@Base+0x22c994>)
│ │  	vsri.16	q8, <illegal reg q9.5>, #16
│ │ -			@ <UNDEFINED> instruction: 0xffcf4b2b
│ │ -	vsli.16	d19, d6, #0
│ │ -			@ <UNDEFINED> instruction: 0xffd04b47
│ │ -	vsli.16	d19, d18, #0
│ │ -	vmlsl.u16	q10, d16, d3
│ │ -	vmls.i16	<illegal reg q9.5>, q0, d6[3]
│ │ -	vmlsl.u16	q10, d16, d27
│ │ -	vsri.64	d19, d6, #48
│ │ +			@ <UNDEFINED> instruction: 0xffcf4b52
│ │ +	vsli.16	d19, d29, #0
│ │ +			@ <UNDEFINED> instruction: 0xffd04b6e
│ │ +	vsli.16	<illegal reg q9.5>, <illegal reg q4.5>, #0
│ │ +	vmlsl.u16	q10, d16, d26
│ │ +	vsri.64	d19, d5, #48
│ │ +			@ <UNDEFINED> instruction: 0xffd04ad2
│ │ +	vsri.64	d19, d29, #48
│ │  			@ <UNDEFINED> instruction: 0xffd04c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	399388 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cb04>
│ │  	ands	r2, r0
│ │  	b.n	3991b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x22c92e>
│ │  	bge.n	398f58 <uniffi_pbcli_checksum_method_api_base@@Base+0x22c6d4>
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │ @@ -1026004,15 +1026004,15 @@
│ │  	b.n	3995f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cd6e>
│ │  	adds	r0, #97	@ 0x61
│ │  	b.n	3995f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cd72>
│ │  	movs	r0, #2
│ │  	b.n	398fd8 <uniffi_pbcli_checksum_method_api_base@@Base+0x22c754>
│ │  	ldr	r4, [pc, #64]	@ (398efc <uniffi_pbcli_checksum_method_api_base@@Base+0x22c678>)
│ │  	ldmia.w	sp!, {r1, r2, r3, r4, r7, ip}
│ │ -			@ <UNDEFINED> instruction: 0xeafe49db
│ │ +			@ <UNDEFINED> instruction: 0xeafe4a02
│ │  	vqshrun.s32	d20, q8, #16
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3993e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cb64>
│ │  	str	r0, [r0, r0]
│ │  	b.n	399212 <uniffi_pbcli_checksum_method_api_base@@Base+0x22c98e>
│ │  	bge.n	398f88 <uniffi_pbcli_checksum_method_api_base@@Base+0x22c704>
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │ @@ -1026076,17 +1026076,17 @@
│ │  	b.n	399074 <uniffi_pbcli_checksum_method_api_base@@Base+0x22c7f0>
│ │  	lsrs	r4, r3, #31
│ │  			@ <UNDEFINED> instruction: 0xebfe4000
│ │  	b.n	39969e <uniffi_pbcli_checksum_method_api_base@@Base+0x22ce1a>
│ │  	movs	r4, r0
│ │  	b.n	3992a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x22ca1e>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r4, r7, r8, fp, lr}
│ │ -	vqrshrn.u32	d20, <illegal reg q7.5>, #16
│ │ -	vqshrn.u32	d20, <illegal reg q15.5>, #16
│ │ +	ldmia.w	sp!, {r1, r3, r4, r5, r7, r8, fp, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffd04986
│ │ +	vmul.f16	q10, q0, d6[2]
│ │  	vmlal.u16	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3992ba <uniffi_pbcli_checksum_method_api_base@@Base+0x22ca36>
│ │  	beq.n	398f9c <uniffi_pbcli_checksum_method_api_base@@Base+0x22c718>
│ │  	b.n	399418 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cb94>
│ │  	asrs	r0, r0, #1
│ │  	b.n	3996c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x22ce3e>
│ │ @@ -1026186,16 +1026186,16 @@
│ │  	b.n	39978e <uniffi_pbcli_checksum_method_api_base@@Base+0x22cf0a>
│ │  	strb.w	lr, [r9], #252
│ │  	movs	r4, r0
│ │  	b.n	399396 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cb12>
│ │  	beq.n	399068 <uniffi_pbcli_checksum_method_api_base@@Base+0x22c7e4>
│ │  	b.n	3994f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cc6c>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r1, r3, r8, sl, lr, pc}
│ │ -	vqrshrun.s32	d20, <illegal reg q7.5>, #16
│ │ +	ldmia.w	sp!, {r0, r4, r5, r8, sl, lr, pc}
│ │ +	vmlal.u16	q10, d16, d6
│ │  			@ <UNDEFINED> instruction: 0xffd0f742
│ │  	vqshrun.s16	d20, q8, #2
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	39958c <uniffi_pbcli_checksum_method_api_base@@Base+0x22cd08>
│ │  	beq.n	3990a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x22c820>
│ │  	b.n	399510 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cc8c>
│ │  	bls.n	39905a <uniffi_pbcli_checksum_method_api_base@@Base+0x22c7d6>
│ │ @@ -1026266,15 +1026266,15 @@
│ │  	lsls	r0, r2, #1
│ │  	b.n	398c8a <uniffi_pbcli_checksum_method_api_base@@Base+0x22c406>
│ │  	movs	r5, r0
│ │  	b.n	399446 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cbc2>
│ │  	beq.n	399118 <uniffi_pbcli_checksum_method_api_base@@Base+0x22c894>
│ │  	b.n	3995a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cd1c>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r5, fp, lr}
│ │  	vmlal.u16	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	39945a <uniffi_pbcli_checksum_method_api_base@@Base+0x22cbd6>
│ │  	beq.n	39913c <uniffi_pbcli_checksum_method_api_base@@Base+0x22c8b8>
│ │  	b.n	3995b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cd34>
│ │  	asrs	r0, r0, #1
│ │  	b.n	399862 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cfde>
│ │ @@ -1026371,15 +1026371,15 @@
│ │  	lsls	r0, r2, #1
│ │  	b.n	398d6e <uniffi_pbcli_checksum_method_api_base@@Base+0x22c4ea>
│ │  	movs	r5, r0
│ │  	b.n	39952a <uniffi_pbcli_checksum_method_api_base@@Base+0x22cca6>
│ │  	beq.n	3991fc <uniffi_pbcli_checksum_method_api_base@@Base+0x22c978>
│ │  	b.n	399684 <uniffi_pbcli_checksum_method_api_base@@Base+0x22ce00>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r8, r9, sl, lr}
│ │ +	ldmia.w	sp!, {r1, r6, r8, r9, sl, lr}
│ │  	vmlal.u16	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	39953e <uniffi_pbcli_checksum_method_api_base@@Base+0x22ccba>
│ │  	beq.n	399220 <uniffi_pbcli_checksum_method_api_base@@Base+0x22c99c>
│ │  	b.n	39969c <uniffi_pbcli_checksum_method_api_base@@Base+0x22ce18>
│ │  	asrs	r0, r0, #1
│ │  	b.n	399946 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d0c2>
│ │ @@ -1026476,15 +1026476,15 @@
│ │  	lsls	r0, r2, #1
│ │  	b.n	398e52 <uniffi_pbcli_checksum_method_api_base@@Base+0x22c5ce>
│ │  	movs	r5, r0
│ │  	b.n	39960e <uniffi_pbcli_checksum_method_api_base@@Base+0x22cd8a>
│ │  	beq.n	3992e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22ca5c>
│ │  	b.n	399768 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cee4>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r9, sl, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r6, r9, sl, lr}
│ │  	vmlal.u16	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	399622 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cd9e>
│ │  	beq.n	399304 <uniffi_pbcli_checksum_method_api_base@@Base+0x22ca80>
│ │  	b.n	399780 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cefc>
│ │  	asrs	r0, r4, #32
│ │  	b.n	399a2a <uniffi_pbcli_checksum_method_api_base@@Base+0x22d1a6>
│ │ @@ -1026583,15 +1026583,15 @@
│ │  	lsls	r0, r2, #1
│ │  	b.n	398f3a <uniffi_pbcli_checksum_method_api_base@@Base+0x22c6b6>
│ │  	movs	r5, r0
│ │  	b.n	3996f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x22ce72>
│ │  	beq.n	3993c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cb44>
│ │  	b.n	399850 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cfcc>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r6, r8, sl, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r4, r5, r6, r8, sl, lr}
│ │  	vmlal.u16	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	39970a <uniffi_pbcli_checksum_method_api_base@@Base+0x22ce86>
│ │  	beq.n	3993ec <uniffi_pbcli_checksum_method_api_base@@Base+0x22cb68>
│ │  	b.n	399868 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cfe4>
│ │  	asrs	r0, r4, #32
│ │  	b.n	399b12 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d28e>
│ │ @@ -1026690,15 +1026690,15 @@
│ │  	lsls	r0, r2, #1
│ │  	b.n	399022 <uniffi_pbcli_checksum_method_api_base@@Base+0x22c79e>
│ │  	movs	r5, r0
│ │  	b.n	3997de <uniffi_pbcli_checksum_method_api_base@@Base+0x22cf5a>
│ │  	beq.n	3994b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cc2c>
│ │  	b.n	399938 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d0b4>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r5, r6, sl, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r7, sl, lr}
│ │  	vmlal.u16	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3997f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cf6e>
│ │  	beq.n	3994d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cc50>
│ │  	b.n	399950 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d0cc>
│ │  	asrs	r0, r4, #32
│ │  	b.n	399bfa <uniffi_pbcli_checksum_method_api_base@@Base+0x22d376>
│ │ @@ -1026797,15 +1026797,15 @@
│ │  	lsls	r0, r2, #1
│ │  	b.n	39910a <uniffi_pbcli_checksum_method_api_base@@Base+0x22c886>
│ │  	movs	r5, r0
│ │  	b.n	3998c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d042>
│ │  	beq.n	399598 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cd14>
│ │  	b.n	399a20 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d19c>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6, r8, r9, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r5, r7, r8, r9, lr}
│ │  	vmlal.u16	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3998da <uniffi_pbcli_checksum_method_api_base@@Base+0x22d056>
│ │  	beq.n	3995bc <uniffi_pbcli_checksum_method_api_base@@Base+0x22cd38>
│ │  	b.n	399a38 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d1b4>
│ │  	asrs	r0, r0, #1
│ │  	b.n	399ce2 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d45e>
│ │ @@ -1026902,15 +1026902,15 @@
│ │  	lsls	r0, r2, #1
│ │  	b.n	3991ee <uniffi_pbcli_checksum_method_api_base@@Base+0x22c96a>
│ │  	movs	r5, r0
│ │  	b.n	3999aa <uniffi_pbcli_checksum_method_api_base@@Base+0x22d126>
│ │  	beq.n	39967c <uniffi_pbcli_checksum_method_api_base@@Base+0x22cdf8>
│ │  	b.n	399b04 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d280>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r7, r9, lr}
│ │ +	ldmia.w	sp!, {r1, r6, r7, r9, lr}
│ │  	vmlal.u16	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3999be <uniffi_pbcli_checksum_method_api_base@@Base+0x22d13a>
│ │  	beq.n	3996a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22ce1c>
│ │  	b.n	399b1c <uniffi_pbcli_checksum_method_api_base@@Base+0x22d298>
│ │  	asrs	r0, r0, #1
│ │  	b.n	399dc6 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d542>
│ │ @@ -1027007,15 +1027007,15 @@
│ │  	lsls	r0, r2, #1
│ │  	b.n	3992d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x22ca4e>
│ │  	movs	r5, r0
│ │  	b.n	399a8e <uniffi_pbcli_checksum_method_api_base@@Base+0x22d20a>
│ │  	beq.n	399760 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cedc>
│ │  	b.n	399be8 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d364>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r7, r8, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r6, r7, r8, lr}
│ │  	vmlal.u16	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	399aa2 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d21e>
│ │  	beq.n	399784 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cf00>
│ │  	b.n	399c00 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d37c>
│ │  	asrs	r0, r0, #1
│ │  	b.n	399eaa <uniffi_pbcli_checksum_method_api_base@@Base+0x22d626>
│ │ @@ -1027112,15 +1027112,15 @@
│ │  	lsls	r0, r2, #1
│ │  	b.n	3993b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cb32>
│ │  	movs	r5, r0
│ │  	b.n	399b72 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d2ee>
│ │  	beq.n	399844 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cfc0>
│ │  	b.n	399ccc <uniffi_pbcli_checksum_method_api_base@@Base+0x22d448>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r4, r6, r7, lr}
│ │ +	ldmia.w	sp!, {r1, r3, r4, r5, r6, r7, lr}
│ │  	vmlal.u16	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	399b86 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d302>
│ │  	beq.n	399868 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cfe4>
│ │  	b.n	399ce4 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d460>
│ │  	asrs	r0, r4, #32
│ │  	b.n	399f8e <uniffi_pbcli_checksum_method_api_base@@Base+0x22d70a>
│ │ @@ -1027219,15 +1027219,15 @@
│ │  	lsls	r0, r2, #1
│ │  	b.n	39949e <uniffi_pbcli_checksum_method_api_base@@Base+0x22cc1a>
│ │  	movs	r5, r0
│ │  	b.n	399c5a <uniffi_pbcli_checksum_method_api_base@@Base+0x22d3d6>
│ │  	beq.n	39992c <uniffi_pbcli_checksum_method_api_base@@Base+0x22d0a8>
│ │  	b.n	399db4 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d530>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r5, r6, r7, r8, r9, sl, fp, ip, sp}
│ │ +	ldmia.w	sp!, {r1, r4, lr}
│ │  	vmlal.u16	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	399c6e <uniffi_pbcli_checksum_method_api_base@@Base+0x22d3ea>
│ │  	beq.n	399950 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d0cc>
│ │  	b.n	399dcc <uniffi_pbcli_checksum_method_api_base@@Base+0x22d548>
│ │  	asrs	r0, r4, #32
│ │  	b.n	39a076 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d7f2>
│ │ @@ -1027326,15 +1027326,15 @@
│ │  	lsls	r0, r2, #1
│ │  	b.n	399586 <uniffi_pbcli_checksum_method_api_base@@Base+0x22cd02>
│ │  	movs	r5, r0
│ │  	b.n	399d42 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d4be>
│ │  	beq.n	399a14 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d190>
│ │  	b.n	399e9c <uniffi_pbcli_checksum_method_api_base@@Base+0x22d618>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r8, r9, sl, fp, ip, sp}
│ │ +	ldmia.w	sp!, {r1, r3, r5, r8, r9, sl, fp, ip, sp}
│ │  	vmlal.u16	q10, d0, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	399d56 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d4d2>
│ │  	beq.n	399a38 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d1b4>
│ │  	b.n	399eb4 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d630>
│ │  	asrs	r0, r4, #32
│ │  	b.n	39a15e <uniffi_pbcli_checksum_method_api_base@@Base+0x22d8da>
│ │ @@ -1027572,20 +1027572,20 @@
│ │  	movs	r4, r2
│ │  	subs	r1, #148	@ 0x94
│ │  	movs	r4, r2
│ │  	subs	r1, #136	@ 0x88
│ │  	movs	r4, r2
│ │  	adds	r7, #144	@ 0x90
│ │  	movs	r4, r2
│ │ -	subs	r5, #83	@ 0x53
│ │ +	subs	r5, #122	@ 0x7a
│ │  			@ <UNDEFINED> instruction: 0xffd0fabc
│ │  	vqshl.u64	<illegal reg q9.5>, q2, #13
│ │  	movs	r4, r2
│ │ -	cbnz	r2, 399c42 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d3be>
│ │ -			@ <UNDEFINED> instruction: 0xffd03cb3
│ │ +	cbnz	r1, 399c4c <uniffi_pbcli_checksum_method_api_base@@Base+0x22d3c8>
│ │ +			@ <UNDEFINED> instruction: 0xffd03cda
│ │  			@ <UNDEFINED> instruction: 0xffd0eb96
│ │  	vqshrun.s16	d20, q8, #2
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	39a158 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d8d4>
│ │  	beq.n	399c70 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d3ec>
│ │  	b.n	39a0dc <uniffi_pbcli_checksum_method_api_base@@Base+0x22d858>
│ │  	bvs.n	399c40 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d3bc>
│ │ @@ -1028062,15 +1028062,15 @@
│ │  	b.n	39a7b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x22df32>
│ │  	blx	799870 <uniffi_pbcli_checksum_method_api_base@@Base+0x62cfec>
│ │  	movs	r5, r0
│ │  	b.n	39a3be <uniffi_pbcli_checksum_method_api_base@@Base+0x22db3a>
│ │  	beq.n	39a090 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d80c>
│ │  	b.n	39a518 <uniffi_pbcli_checksum_method_api_base@@Base+0x22dc94>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r6, r7, sl, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r8, sl, ip, sp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffd03fa3
│ │  			@ <UNDEFINED> instruction: 0xffce9e35
│ │  	vaddl.u8	q8, d15, d4
│ │  	b.n	399bd4 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d350>
│ │  	movs	r0, r0
│ │  	b.n	39a1b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d934>
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -1028367,15 +1028367,15 @@
│ │  			@ <UNDEFINED> instruction: 0xffe4eaff
│ │  	subs	r5, #99	@ 0x63
│ │  	vqdmulh.s<illegal width 8>	q14, q7, d2[4]
│ │  	vrsra.u8	<illegal reg q9.5>, q2, #2
│ │  	movs	r4, r2
│ │  	subs	r4, #251	@ 0xfb
│ │  	vsra.u8	q12, q3, #2
│ │ -	vrshr.u64	d27, d6, #49
│ │ +	vrshr.u64	d27, d29, #49
│ │  			@ <UNDEFINED> instruction: 0xffd03d27
│ │  			@ <UNDEFINED> instruction: 0xffce9bb9
│ │  	vaddl.u8	q8, d15, d4
│ │  	b.n	399e80 <uniffi_pbcli_checksum_method_api_base@@Base+0x22d5fc>
│ │  	movs	r0, r0
│ │  	b.n	39a464 <uniffi_pbcli_checksum_method_api_base@@Base+0x22dbe0>
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -1030527,25 +1030527,25 @@
│ │  	b.n	39bd36 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f4b2>
│ │  	ldr	r4, [pc, #724]	@ (39b8cc <uniffi_pbcli_checksum_method_api_base@@Base+0x22f048>)
│ │  	add.w	r0, r1, r5, lsl #16
│ │  	b.n	39b93e <uniffi_pbcli_checksum_method_api_base@@Base+0x22f0ba>
│ │  	movs	r4, r0
│ │  	b.n	39b942 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f0be>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r7, r9, sl, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r6, r7, r9, sl, fp, ip, lr, pc}
│ │  	vaddl.u8	q9, d15, d12
│ │  	b.n	39b14c <uniffi_pbcli_checksum_method_api_base@@Base+0x22e8c8>
│ │  	subs	r2, r4, #5
│ │  	b.n	39bd52 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f4ce>
│ │  	adds	r0, #50	@ 0x32
│ │  	b.n	39bd56 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f4d2>
│ │  	movs	r0, #2
│ │  	b.n	39b738 <uniffi_pbcli_checksum_method_api_base@@Base+0x22eeb4>
│ │  	lsls	r7, r0, #27
│ │ -			@ <UNDEFINED> instruction: 0xeafede6f
│ │ +			@ <UNDEFINED> instruction: 0xeafede96
│ │  			@ <UNDEFINED> instruction: 0xffcf4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	39bb44 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f2c0>
│ │  	ands	r0, r0
│ │  	b.n	39bd6e <uniffi_pbcli_checksum_method_api_base@@Base+0x22f4ea>
│ │  	movs	r0, r0
│ │  	b.n	39bcd2 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f44e>
│ │ @@ -1030573,15 +1030573,15 @@
│ │  	asrs	r0, r6, #1
│ │  	asrs	r0, r0, #10
│ │  	asrs	r4, r4, #1
│ │  	asrs	r0, r0, #22
│ │  	movs	r4, r0
│ │  	b.n	39b9aa <uniffi_pbcli_checksum_method_api_base@@Base+0x22f126>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r6, r9, sl, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r5, r6, r9, sl, fp, ip, lr, pc}
│ │  	vmlal.u8	q10, d15, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	39b9ba <uniffi_pbcli_checksum_method_api_base@@Base+0x22f136>
│ │  	beq.n	39b69c <uniffi_pbcli_checksum_method_api_base@@Base+0x22ee18>
│ │  	b.n	39bb18 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f294>
│ │  	asrs	r0, r4, #1
│ │  	b.n	39bdc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f53e>
│ │ @@ -1030641,15 +1030641,15 @@
│ │  	b.n	39be3a <uniffi_pbcli_checksum_method_api_base@@Base+0x22f5b6>
│ │  	ldr	r4, [pc, #464]	@ (39b8cc <uniffi_pbcli_checksum_method_api_base@@Base+0x22f048>)
│ │  	add.w	r0, r1, r5, lsl #16
│ │  	b.n	39ba42 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f1be>
│ │  	movs	r4, r0
│ │  	b.n	39ba46 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f1c2>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r4, r5, r7, r8, sl, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r4, r6, r7, r8, sl, fp, ip, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcf4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	39bc30 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f3ac>
│ │  	ands	r0, r0
│ │  	b.n	39be5a <uniffi_pbcli_checksum_method_api_base@@Base+0x22f5d6>
│ │  	movs	r0, r0
│ │  	b.n	39bdbe <uniffi_pbcli_checksum_method_api_base@@Base+0x22f53a>
│ │ @@ -1030677,15 +1030677,15 @@
│ │  	asrs	r0, r6, #1
│ │  	asrs	r0, r0, #10
│ │  	asrs	r4, r4, #1
│ │  	asrs	r0, r0, #22
│ │  	movs	r4, r0
│ │  	b.n	39ba96 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f212>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r6, r8, sl, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r5, r6, r8, sl, fp, ip, lr, pc}
│ │  	vmlal.u8	q10, d15, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	39baa6 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f222>
│ │  	beq.n	39b788 <uniffi_pbcli_checksum_method_api_base@@Base+0x22ef04>
│ │  	b.n	39bc04 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f380>
│ │  	asrs	r0, r4, #1
│ │  	b.n	39beae <uniffi_pbcli_checksum_method_api_base@@Base+0x22f62a>
│ │ @@ -1030745,15 +1030745,15 @@
│ │  	b.n	39bf26 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f6a2>
│ │  	ldr	r4, [pc, #228]	@ (39b8cc <uniffi_pbcli_checksum_method_api_base@@Base+0x22f048>)
│ │  	add.w	r0, r1, r5, lsl #16
│ │  	b.n	39bb2e <uniffi_pbcli_checksum_method_api_base@@Base+0x22f2aa>
│ │  	movs	r4, r0
│ │  	b.n	39bb32 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f2ae>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r6, r7, sl, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r5, r6, r7, sl, fp, ip, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcf4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	39bd1c <uniffi_pbcli_checksum_method_api_base@@Base+0x22f498>
│ │  	ands	r0, r0
│ │  	b.n	39bf46 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f6c2>
│ │  	movs	r0, r0
│ │  	b.n	39beaa <uniffi_pbcli_checksum_method_api_base@@Base+0x22f626>
│ │ @@ -1030781,15 +1030781,15 @@
│ │  	asrs	r0, r6, #1
│ │  	asrs	r0, r0, #10
│ │  	asrs	r4, r4, #1
│ │  	asrs	r0, r0, #22
│ │  	movs	r4, r0
│ │  	b.n	39bb82 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f2fe>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r5, r6, sl, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r4, r7, sl, fp, ip, lr, pc}
│ │  	vmlal.u8	q10, d15, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	39bb92 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f30e>
│ │  	beq.n	39b874 <uniffi_pbcli_checksum_method_api_base@@Base+0x22eff0>
│ │  	b.n	39bcf0 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f46c>
│ │  	asrs	r0, r4, #1
│ │  	b.n	39bf9a <uniffi_pbcli_checksum_method_api_base@@Base+0x22f716>
│ │ @@ -1031590,18 +1031590,18 @@
│ │  	b.n	39c696 <uniffi_pbcli_checksum_method_api_base@@Base+0x22fe12>
│ │  	mcrr	11, 15, lr, r7, cr12
│ │  	movs	r4, r0
│ │  	b.n	39c29e <uniffi_pbcli_checksum_method_api_base@@Base+0x22fa1a>
│ │  	beq.n	39bf70 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f6ec>
│ │  	b.n	39c3f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x22fb74>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r6, r9, sl, ip, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffd00e15
│ │ +	ldmia.w	sp!, {r0, r2, r3, r5, r6, r9, sl, ip, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffd00e3c
│ │  	vsra.u64	d18, d7, #48
│ │ -	vsri.64	d23, d9, #49
│ │ +	vmls.i<illegal width 8>	<illegal reg q11.5>, <illegal reg q15.5>, d0[0]
│ │  			@ <UNDEFINED> instruction: 0xffd048f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	39c498 <uniffi_pbcli_checksum_method_api_base@@Base+0x22fc14>
│ │  	beq.n	39bf90 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f70c>
│ │  	b.n	39c41c <uniffi_pbcli_checksum_method_api_base@@Base+0x22fb98>
│ │  	ands	r0, r0
│ │  	b.n	39c2c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x22fa42>
│ │ @@ -1031901,18 +1031901,18 @@
│ │  	b.n	39c966 <uniffi_pbcli_checksum_method_api_base@@Base+0x2300e2>
│ │  	ands	r0, r0
│ │  	b.n	39c96a <uniffi_pbcli_checksum_method_api_base@@Base+0x2300e6>
│ │  			@ <UNDEFINED> instruction: 0xeb92ebfc
│ │  	movs	r4, r0
│ │  	b.n	39c572 <uniffi_pbcli_checksum_method_api_base@@Base+0x22fcee>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r3, r6, r8, r9, fp}
│ │ -	vrsra.u16	d25, d14, #16
│ │ +	ldmia.w	sp!, {r4, r5, r6, r8, r9, fp}
│ │ +			@ <UNDEFINED> instruction: 0xffd09345
│ │  	vqrdmlah.s16	<illegal reg q8.5>, q8, d3[0]
│ │ -	vqshlu.s64	d17, d18, #15
│ │ +	vqshlu.s64	<illegal reg q8.5>, <illegal reg q4.5>, #15
│ │  	vaddl.u16	q8, d0, d4
│ │  	b.n	39bd88 <uniffi_pbcli_checksum_method_api_base@@Base+0x22f504>
│ │  	movs	r0, r0
│ │  	b.n	39c36c <uniffi_pbcli_checksum_method_api_base@@Base+0x22fae8>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldrb	r0, [r2, #3]
│ │  	movs	r2, r2
│ │ @@ -1033060,18 +1033060,18 @@
│ │  	b.n	39c752 <uniffi_pbcli_checksum_method_api_base@@Base+0x22fece>
│ │  	subs	r5, r3, #6
│ │  	b.n	39d13e <uniffi_pbcli_checksum_method_api_base@@Base+0x2308ba>
│ │  	b.n	39ccc6 <uniffi_pbcli_checksum_method_api_base@@Base+0x230442>
│ │  			@ <UNDEFINED> instruction: 0xfa030005
│ │  	b.n	39cf7e <uniffi_pbcli_checksum_method_api_base@@Base+0x2306fa>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r4, r7, r9}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r5, r7, r9}
│ │  	vsri.64	<illegal reg q8.5>, q3, #48
│ │  	vrsubhn.i16	d25, q15, q12
│ │ -	vmull.u16	q12, d0, d2[3]
│ │ +			@ <UNDEFINED> instruction: 0xffd08a91
│ │  	vsri.64	d17, d26, #48
│ │  	vrsubhn.i16	d25, q15, q6
│ │  	vsli.16	<illegal reg q8.5>, q2, #0
│ │  	vsri.64	d17, d14, #50
│ │  	vqshlu.s8	<illegal reg q12.5>, q8, #6
│ │  	vabdl.u16	q11, d0, d8
│ │  	vraddhn.i16	d17, <illegal reg q15.5>, q1
│ │ @@ -1033341,21 +1033341,21 @@
│ │  	b.n	39d5fe <uniffi_pbcli_checksum_method_api_base@@Base+0x230d7a>
│ │  	strd	lr, fp, [sp], #-1008	@ 0x3f0
│ │  	movs	r4, r0
│ │  	b.n	39d206 <uniffi_pbcli_checksum_method_api_base@@Base+0x230982>
│ │  	beq.n	39cef8 <uniffi_pbcli_checksum_method_api_base@@Base+0x230674>
│ │  	b.n	39d360 <uniffi_pbcli_checksum_method_api_base@@Base+0x230adc>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r1, r3, r4, fp, pc}
│ │ -	vqrdmlsh.s16	<illegal reg q15.5>, q8, d1[3]
│ │ -	vqrdmlsh.s<illegal width 8>	<illegal reg q8.5>, <illegal reg q7.5>, d1[4]
│ │ +	ldmia.w	sp!, {r0, r6, fp, pc}
│ │ +	vshr.u16	d16, d0, #16
│ │ +	vqrdmlsh.s16	<illegal reg q8.5>, q0, d1[2]
│ │  	vqrdmulh.s<illegal width 8>	<illegal reg q8.5>, q7, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffcf4c5a
│ │  	vaddw.u8	<illegal reg q8.5>, q15, d14
│ │ -	vsli.8	d24, d31, #6
│ │ +	vmls.f<illegal width 8>	q12, q7, d2[5]
│ │  	vaddl.u8	q8, d15, d4
│ │  	b.n	39ca2c <uniffi_pbcli_checksum_method_api_base@@Base+0x2301a8>
│ │  	movs	r0, r0
│ │  	b.n	39d010 <uniffi_pbcli_checksum_method_api_base@@Base+0x23078c>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r4, [r4, #88]	@ 0x58
│ │  	movs	r2, r2
│ │ @@ -1035477,23 +1035477,23 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	39e270 <uniffi_pbcli_checksum_method_api_base@@Base+0x2319ec>
│ │  	ldr	r0, [pc, #0]	@ (39e154 <uniffi_pbcli_checksum_method_api_base@@Base+0x2318d0>)
│ │  	ldmia.w	sp!, {r1, r7, r9, fp, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeafd0000
│ │  	b.n	39e89e <uniffi_pbcli_checksum_method_api_base@@Base+0x23201a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6, r8, sl, fp, ip, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r5, r7, r8, sl, fp, ip, pc}
│ │  	vaddl.u8	<illegal reg q8.5>, d15, d8
│ │  	b.n	39dca8 <uniffi_pbcli_checksum_method_api_base@@Base+0x231424>
│ │  	movs	r0, #36	@ 0x24
│ │  	b.n	39e8ae <uniffi_pbcli_checksum_method_api_base@@Base+0x23202a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	39e290 <uniffi_pbcli_checksum_method_api_base@@Base+0x231a0c>
│ │  			@ <UNDEFINED> instruction: 0xfb55eafd
│ │ -	ldr	r5, [sp, #380]	@ 0x17c
│ │ +	ldr	r5, [sp, #536]	@ 0x218
│ │  			@ <UNDEFINED> instruction: 0xffcf4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	39e69c <uniffi_pbcli_checksum_method_api_base@@Base+0x231e18>
│ │  	ands	r0, r0
│ │  	b.n	39e4c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x231c42>
│ │  	stmia	r5!, {r0, r2, r3, r5, r7}
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │ @@ -1035721,19 +1035721,19 @@
│ │  	b.n	39eac6 <uniffi_pbcli_checksum_method_api_base@@Base+0x232242>
│ │  	str	r0, [r0, r0]
│ │  	b.n	39eaca <uniffi_pbcli_checksum_method_api_base@@Base+0x232246>
│ │  	b.n	39ea00 <uniffi_pbcli_checksum_method_api_base@@Base+0x23217c>
│ │  			@ <UNDEFINED> instruction: 0xebfc0005
│ │  	b.n	39e6d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x231e4e>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r9, fp, sp, lr, pc}
│ │ -	vsra.u64	<illegal reg q11.5>, q9, #49
│ │ -			@ <UNDEFINED> instruction: 0xffd08c73
│ │ -			@ <UNDEFINED> instruction: 0xffcf9b5f
│ │ -	vsubl.u8	q9, d15, d26
│ │ +	ldmia.w	sp!, {r2, r6, r9, fp, sp, lr, pc}
│ │ +	vrshr.u8	d23, d9, #1
│ │ +			@ <UNDEFINED> instruction: 0xffd08c9a
│ │ +			@ <UNDEFINED> instruction: 0xffcf9b86
│ │ +	vrshr.u8	q9, <illegal reg q0.5>, #1
│ │  	vaddl.u16	q8, d0, d4
│ │  	b.n	39deec <uniffi_pbcli_checksum_method_api_base@@Base+0x231668>
│ │  	movs	r0, r0
│ │  	b.n	39e4d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x231c4c>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r0, [r2, r6]
│ │  	movs	r2, r2
│ │ @@ -1035788,15 +1035788,15 @@
│ │  	ands	r0, r0
│ │  	b.n	39eb6a <uniffi_pbcli_checksum_method_api_base@@Base+0x2322e6>
│ │  	b.n	39ea50 <uniffi_pbcli_checksum_method_api_base@@Base+0x2321cc>
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	39e772 <uniffi_pbcli_checksum_method_api_base@@Base+0x231eee>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffcd9abf
│ │ +	vmull.u<illegal width 8>	<illegal reg q12.5>, d29, d2[5]
│ │  			@ <UNDEFINED> instruction: 0xffcf7e15
│ │  	vaddl.u16	q8, d0, d4
│ │  	b.n	39df84 <uniffi_pbcli_checksum_method_api_base@@Base+0x231700>
│ │  	movs	r0, r0
│ │  	b.n	39e568 <uniffi_pbcli_checksum_method_api_base@@Base+0x231ce4>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r0, [r1, r5]
│ │ @@ -1036929,15 +1036929,15 @@
│ │  	b.n	39ef5c <uniffi_pbcli_checksum_method_api_base@@Base+0x2326d8>
│ │  			@ <UNDEFINED> instruction: 0xebfc0005
│ │  	b.n	39f18a <uniffi_pbcli_checksum_method_api_base@@Base+0x232906>
│ │  	beq.n	39ee5c <uniffi_pbcli_checksum_method_api_base@@Base+0x2325d8>
│ │  	b.n	39f2e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x232a60>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r2, r6, r7, r8, fp, ip, sp}
│ │ -	vaddw.u8	q8, q7, d9
│ │ +	vsra.u8	d16, d16, #2
│ │  			@ <UNDEFINED> instruction: 0xffd04c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	39f37c <uniffi_pbcli_checksum_method_api_base@@Base+0x232af8>
│ │  	ands	r2, r0
│ │  	b.n	39f1a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x232922>
│ │  	stmia	r2!, {r0, r2, r4, r5, r6}
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │ @@ -1037097,15 +1037097,15 @@
│ │  	b.n	39eadc <uniffi_pbcli_checksum_method_api_base@@Base+0x232258>
│ │  	lsls	r5, r1, #3
│ │  	add.w	r0, r0, r0
│ │  	b.n	39f66a <uniffi_pbcli_checksum_method_api_base@@Base+0x232de6>
│ │  			@ <UNDEFINED> instruction: 0xffbe1aff
│ │  			@ <UNDEFINED> instruction: 0xfff2eaff
│ │  	subs	r0, #213	@ 0xd5
│ │ -	vrsra.u8	<illegal reg q14.5>, <illegal reg q15.5>, #2
│ │ +	vsubw.u8	<illegal reg q14.5>, q15, d22
│ │  			@ <UNDEFINED> instruction: 0xffcf4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	39f4fc <uniffi_pbcli_checksum_method_api_base@@Base+0x232c78>
│ │  	ands	r0, r0
│ │  	b.n	39f326 <uniffi_pbcli_checksum_method_api_base@@Base+0x232aa2>
│ │  	adds	r5, #227	@ 0xe3
│ │  	add.w	r0, r1, r4, lsr #8
│ │ @@ -1037331,19 +1037331,19 @@
│ │  	movs	r4, r0
│ │  	b.n	39f51a <uniffi_pbcli_checksum_method_api_base@@Base+0x232c96>
│ │  	beq.n	39f1ec <uniffi_pbcli_checksum_method_api_base@@Base+0x232968>
│ │  	b.n	39f674 <uniffi_pbcli_checksum_method_api_base@@Base+0x232df0>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r4, r5, r7, r9, sl, sp, lr}
│ │  	vmlsl.u<illegal width 8>	<illegal reg q9.5>, d14, d1[2]
│ │ -	vraddhn.i16	d17, q7, q5
│ │ -			@ <UNDEFINED> instruction: 0xffd0fe13
│ │ +	vsri.8	d17, d17, #2
│ │ +			@ <UNDEFINED> instruction: 0xffd0fe3a
│ │  	vmull.u8	<illegal reg q13.5>, d31, d9
│ │  	vqshlu.s8	<illegal reg q9.5>, <illegal reg q14.5>, #5
│ │ -	vsri.8	d17, d30, #2
│ │ +	vmls.i<illegal width 8>	<illegal reg q8.5>, q7, d1[5]
│ │  	vaddl.u16	q8, d0, d4
│ │  	b.n	39ed40 <uniffi_pbcli_checksum_method_api_base@@Base+0x2324bc>
│ │  	movs	r0, r0
│ │  	b.n	39f324 <uniffi_pbcli_checksum_method_api_base@@Base+0x232aa0>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r7, [pc, #896]	@ (39f58c <uniffi_pbcli_checksum_method_api_base@@Base+0x232d08>)
│ │  	movs	r2, r2
│ │ @@ -1038721,15 +1038721,15 @@
│ │  	ands	r0, r0
│ │  	b.n	3a04fe <uniffi_pbcli_checksum_method_api_base@@Base+0x233c7a>
│ │  	bgt.n	39fd1a <uniffi_pbcli_checksum_method_api_base@@Base+0x233496>
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3a0106 <uniffi_pbcli_checksum_method_api_base@@Base+0x233882>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r4, r6, r7, r8, fp, ip, sp, lr, pc}
│ │ -	vabal.u8	q14, d14, d2
│ │ +	vabal.u8	q14, d14, d25
│ │  			@ <UNDEFINED> instruction: 0xffcf4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3a02f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x233a70>
│ │  	beq.n	39fdfc <uniffi_pbcli_checksum_method_api_base@@Base+0x233578>
│ │  	b.n	3a0278 <uniffi_pbcli_checksum_method_api_base@@Base+0x2339f4>
│ │  	stmia	r0!, {r3}
│ │  	b.n	39f918 <uniffi_pbcli_checksum_method_api_base@@Base+0x233094>
│ │ @@ -1038840,15 +1038840,15 @@
│ │  	b.n	3a0612 <uniffi_pbcli_checksum_method_api_base@@Base+0x233d8e>
│ │  	ands	r0, r0
│ │  	b.n	3a0616 <uniffi_pbcli_checksum_method_api_base@@Base+0x233d92>
│ │  	bgt.n	39ffa6 <uniffi_pbcli_checksum_method_api_base@@Base+0x233722>
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3a021e <uniffi_pbcli_checksum_method_api_base@@Base+0x23399a>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r5, r6, r7, r8, sl, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r9, sl, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffcff8b8
│ │  	vrsra.u8	q11, <illegal reg q14.5>, #2
│ │  	vaddl.u16	q8, d0, d4
│ │  	b.n	39fa30 <uniffi_pbcli_checksum_method_api_base@@Base+0x2331ac>
│ │  	movs	r0, r0
│ │  	b.n	3a0014 <uniffi_pbcli_checksum_method_api_base@@Base+0x233790>
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -1038922,15 +1038922,15 @@
│ │  	b.n	3a06d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x233e52>
│ │  	bgt.n	3a0006 <uniffi_pbcli_checksum_method_api_base@@Base+0x233782>
│ │  			@ <UNDEFINED> instruction: 0xebfc0000
│ │  	b.n	3a06de <uniffi_pbcli_checksum_method_api_base@@Base+0x233e5a>
│ │  	beq.n	39ffd8 <uniffi_pbcli_checksum_method_api_base@@Base+0x233754>
│ │  	b.n	3a0438 <uniffi_pbcli_checksum_method_api_base@@Base+0x233bb4>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r5, r6, r7, sl, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r5, r8, sl, ip, sp, lr, pc}
│ │  	vqshl.u64	<illegal reg q15.5>, q10, #15
│ │  	vmlal.u8	<illegal reg q15.5>, d14, d23
│ │  			@ <UNDEFINED> instruction: 0xffce4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3a04d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x233c50>
│ │  	beq.n	39ffec <uniffi_pbcli_checksum_method_api_base@@Base+0x233768>
│ │  	b.n	3a0458 <uniffi_pbcli_checksum_method_api_base@@Base+0x233bd4>
│ │ @@ -1040503,15 +1040503,15 @@
│ │  	str	r0, [r0, r0]
│ │  	add	r5, pc, #544	@ (adr r5, 3a0f58 <uniffi_pbcli_checksum_method_api_base@@Base+0x2346d4>)
│ │  	movs	r4, r0
│ │  	b.n	3a107e <uniffi_pbcli_checksum_method_api_base@@Base+0x2347fa>
│ │  	beq.n	3a0d78 <uniffi_pbcli_checksum_method_api_base@@Base+0x2344f4>
│ │  	b.n	3a11d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x234954>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r3, r5, r6, r8, r9, ip}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r7, r8, r9, ip}
│ │  			@ <UNDEFINED> instruction: 0xffd01dd0
│ │  			@ <UNDEFINED> instruction: 0xffce4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3a1270 <uniffi_pbcli_checksum_method_api_base@@Base+0x2349ec>
│ │  	beq.n	3a0d88 <uniffi_pbcli_checksum_method_api_base@@Base+0x234504>
│ │  	b.n	3a11f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x234970>
│ │  	ands	r0, r0
│ │ @@ -1040606,15 +1040606,15 @@
│ │  	b.n	3a155e <uniffi_pbcli_checksum_method_api_base@@Base+0x234cda>
│ │  	bhi.n	3a0d4a <uniffi_pbcli_checksum_method_api_base@@Base+0x2344c6>
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3a1166 <uniffi_pbcli_checksum_method_api_base@@Base+0x2348e2>
│ │  	beq.n	3a0e38 <uniffi_pbcli_checksum_method_api_base@@Base+0x2345b4>
│ │  	b.n	3a12c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x234a3c>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r4, r6, r7, r8, r9, sl, fp}
│ │  			@ <UNDEFINED> instruction: 0xffd0eba6
│ │  	vmlal.u8	q10, d13, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3a117e <uniffi_pbcli_checksum_method_api_base@@Base+0x2348fa>
│ │  	beq.n	3a0e60 <uniffi_pbcli_checksum_method_api_base@@Base+0x2345dc>
│ │  	b.n	3a12dc <uniffi_pbcli_checksum_method_api_base@@Base+0x234a58>
│ │  	asrs	r0, r0, #32
│ │ @@ -1040724,15 +1040724,15 @@
│ │  	ands	r0, r0
│ │  	b.n	3a166e <uniffi_pbcli_checksum_method_api_base@@Base+0x234dea>
│ │  	bhi.n	3a0fd2 <uniffi_pbcli_checksum_method_api_base@@Base+0x23474e>
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3a1276 <uniffi_pbcli_checksum_method_api_base@@Base+0x2349f2>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r5, r6, r7, r8, sl, lr, pc}
│ │ -	vshr.u8	d30, d26, #2
│ │ +	vmla.i<illegal width 8>	q15, q7, d1[4]
│ │  	vqshlu.s64	q12, q11, #15
│ │  	vqshrun.s16	d20, q8, #3
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3a1468 <uniffi_pbcli_checksum_method_api_base@@Base+0x234be4>
│ │  	beq.n	3a0f60 <uniffi_pbcli_checksum_method_api_base@@Base+0x2346dc>
│ │  	b.n	3a13ec <uniffi_pbcli_checksum_method_api_base@@Base+0x234b68>
│ │  	movs	r0, r0
│ │ @@ -1040826,18 +1040826,18 @@
│ │  	asrs	r6, r1, #30
│ │  	add.w	r0, r0, r4
│ │  	b.n	3a135e <uniffi_pbcli_checksum_method_api_base@@Base+0x234ada>
│ │  	beq.n	3a1030 <uniffi_pbcli_checksum_method_api_base@@Base+0x2347ac>
│ │  	b.n	3a14b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x234c34>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r2, r3, r4, r5, r8, sl, lr, pc}
│ │ -	vqrdmlsh.s<illegal width 8>	<illegal reg q14.5>, q7, d2[4]
│ │ -	vmlal.u<illegal width 8>	<illegal reg q13.5>, d31, d0[1]
│ │ -			@ <UNDEFINED> instruction: 0xffcfdf96
│ │ -	vrshr.u64	<illegal reg q13.5>, q12, #49
│ │ +			@ <UNDEFINED> instruction: 0xffcedf89
│ │ +	vmlal.u<illegal width 8>	<illegal reg q13.5>, d31, d3[6]
│ │ +			@ <UNDEFINED> instruction: 0xffcfdfbd
│ │ +	vrsra.u8	d27, d15, #1
│ │  	vmlal.u8	q10, d15, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3a1382 <uniffi_pbcli_checksum_method_api_base@@Base+0x234afe>
│ │  	cbnz	r6, 3a1082 <uniffi_pbcli_checksum_method_api_base@@Base+0x2347fe>
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	3a16ea <uniffi_pbcli_checksum_method_api_base@@Base+0x234e66>
│ │  	movs	r5, r0
│ │ @@ -1040851,15 +1040851,15 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	3a117c <uniffi_pbcli_checksum_method_api_base@@Base+0x2348f8>
│ │  	ldr	r0, [pc, #0]	@ (3a1060 <uniffi_pbcli_checksum_method_api_base@@Base+0x2347dc>)
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r7, r9, sl, fp, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeafd0000
│ │  	b.n	3a17aa <uniffi_pbcli_checksum_method_api_base@@Base+0x234f26>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r4, r5, r6, r7, r9, sl, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r3, r4, r8, r9, sl, fp, ip, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcf48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3a1594 <uniffi_pbcli_checksum_method_api_base@@Base+0x234d10>
│ │  	str	r3, [r0, #0]
│ │  	b.n	3a13be <uniffi_pbcli_checksum_method_api_base@@Base+0x234b3a>
│ │  	strb	r2, [r0, #0]
│ │  	b.n	3a13c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x234b3e>
│ │ @@ -1040916,26 +1040916,26 @@
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r2}
│ │  	b.n	3a143a <uniffi_pbcli_checksum_method_api_base@@Base+0x234bb6>
│ │  	asrs	r4, r0, #32
│ │  	b.n	3a143e <uniffi_pbcli_checksum_method_api_base@@Base+0x234bba>
│ │  	ldr	r0, [pc, #960]	@ (3a14c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x234c3c>)
│ │  	ldmia.w	sp!, {r0, r1, r2, r6, r7, r8, sl, fp, ip}
│ │ -			@ <UNDEFINED> instruction: 0xea00de8e
│ │ -	vsubw.u8	q9, <illegal reg q7.5>, d29
│ │ +			@ <UNDEFINED> instruction: 0xea00deb5
│ │ +	vrsra.u8	q9, q2, #1
│ │  	vaddl.u16	q9, d0, d12
│ │  	b.n	3a0c50 <uniffi_pbcli_checksum_method_api_base@@Base+0x2343cc>
│ │  	asrs	r0, r3, #2
│ │  	b.n	3a1856 <uniffi_pbcli_checksum_method_api_base@@Base+0x234fd2>
│ │  	adds	r0, #187	@ 0xbb
│ │  	b.n	3a185a <uniffi_pbcli_checksum_method_api_base@@Base+0x234fd6>
│ │  	movs	r0, #2
│ │  	b.n	3a123c <uniffi_pbcli_checksum_method_api_base@@Base+0x2349b8>
│ │  	bfcsel	0, 3a171a <uniffi_pbcli_checksum_method_api_base@@Base+0x234e96>, 4, ne
│ │ -	udf	#50	@ 0x32
│ │ +	udf	#89	@ 0x59
│ │  			@ <UNDEFINED> instruction: 0xffcf4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3a1648 <uniffi_pbcli_checksum_method_api_base@@Base+0x234dc4>
│ │  	ands	r0, r0
│ │  	b.n	3a1472 <uniffi_pbcli_checksum_method_api_base@@Base+0x234bee>
│ │  	cbnz	r2, 3a1164 <uniffi_pbcli_checksum_method_api_base@@Base+0x2348e0>
│ │  			@ <UNDEFINED> instruction: 0xebff5000
│ │ @@ -1040965,15 +1040965,15 @@
│ │  	b.n	3a14aa <uniffi_pbcli_checksum_method_api_base@@Base+0x234c26>
│ │  	ldmia	r7!, {r1, r2, r3, r4}
│ │  			@ <UNDEFINED> instruction: 0xfa035006
│ │  	b.n	3a14b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x234c2e>
│ │  	movs	r5, r0
│ │  	b.n	3a14b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x234c32>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r5, r6, r7, r8, sl, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r5, r9, sl, fp, ip, lr, pc}
│ │  	vmla.i<illegal width 8>	<illegal reg q8.5>, <illegal reg q7.5>, d0[0]
│ │  	b.n	3a18c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x23503e>
│ │  	movs	r0, #32
│ │  	b.n	3a18c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x235042>
│ │  	adds	r0, #0
│ │  	b.n	3a18ca <uniffi_pbcli_checksum_method_api_base@@Base+0x235046>
│ │  	ldr	r7, [pc, #136]	@ (3a1214 <uniffi_pbcli_checksum_method_api_base@@Base+0x234990>)
│ │ @@ -1041101,16 +1041101,16 @@
│ │  	ands	r0, r0
│ │  	b.n	3a19e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x23515e>
│ │  	bvc.n	3a138c <uniffi_pbcli_checksum_method_api_base@@Base+0x234b08>
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3a15ea <uniffi_pbcli_checksum_method_api_base@@Base+0x234d66>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r2, r3, r5, r6, r9, lr, pc}
│ │ -	vqdmulh.s<illegal width 8>	<illegal reg q14.5>, q15, d2[1]
│ │ -	vqshl.u64	d25, d27, #15
│ │ +	vqdmulh.s<illegal width 8>	<illegal reg q14.5>, q15, d1[7]
│ │ +			@ <UNDEFINED> instruction: 0xffcf97e2
│ │  	vqshrun.s16	d20, q8, #1
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3a17dc <uniffi_pbcli_checksum_method_api_base@@Base+0x234f58>
│ │  	beq.n	3a12d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x234a50>
│ │  	b.n	3a1760 <uniffi_pbcli_checksum_method_api_base@@Base+0x234edc>
│ │  	movs	r0, r0
│ │  	b.n	3a196a <uniffi_pbcli_checksum_method_api_base@@Base+0x2350e6>
│ │ @@ -1041203,17 +1041203,17 @@
│ │  	lsls	r1, r0, #2
│ │  	add.w	r0, r0, r4
│ │  	b.n	3a16d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x234e4e>
│ │  	beq.n	3a13a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x234b20>
│ │  	b.n	3a182c <uniffi_pbcli_checksum_method_api_base@@Base+0x234fa8>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r3, r6, r7, r8, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffcedbee
│ │ +			@ <UNDEFINED> instruction: 0xffcedc15
│ │  			@ <UNDEFINED> instruction: 0xffcfb8ff
│ │ -	vmull.u8	<illegal reg q14.5>, d14, d18
│ │ +	vqdmulh.s<illegal width 8>	<illegal reg q14.5>, q7, d1[2]
│ │  	vqshrn.u16	d27, <illegal reg q9.5>, #1
│ │  	vmlal.u8	q10, d14, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3a16f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x234e72>
│ │  	cbnz	r1, 3a13c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x234b3c>
│ │  			@ <UNDEFINED> instruction: 0xebff0000
│ │  	b.n	3a1a5e <uniffi_pbcli_checksum_method_api_base@@Base+0x2351da>
│ │ @@ -1041228,15 +1041228,15 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	3a14f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x234c6c>
│ │  	ldr	r0, [pc, #0]	@ (3a13d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x234b50>)
│ │  	ldmia.w	sp!, {r1, r5, r6, r7, r8, sl, fp, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeafd0000
│ │  	b.n	3a1b1e <uniffi_pbcli_checksum_method_api_base@@Base+0x23529a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r5, r6, r8, r9, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r5, r7, r8, r9, fp, ip, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcf48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3a1908 <uniffi_pbcli_checksum_method_api_base@@Base+0x235084>
│ │  	str	r3, [r0, #0]
│ │  	b.n	3a1732 <uniffi_pbcli_checksum_method_api_base@@Base+0x234eae>
│ │  	strb	r2, [r0, #0]
│ │  	b.n	3a1736 <uniffi_pbcli_checksum_method_api_base@@Base+0x234eb2>
│ │ @@ -1041293,26 +1041293,26 @@
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r2}
│ │  	b.n	3a17ae <uniffi_pbcli_checksum_method_api_base@@Base+0x234f2a>
│ │  	asrs	r4, r0, #32
│ │  	b.n	3a17b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x234f2e>
│ │  	ldr	r0, [pc, #960]	@ (3a1834 <uniffi_pbcli_checksum_method_api_base@@Base+0x234fb0>)
│ │  	ldmia.w	sp!, {r1, r5, r9, sl, ip}
│ │ -			@ <UNDEFINED> instruction: 0xea00db1a
│ │ +			@ <UNDEFINED> instruction: 0xea00db41
│ │  			@ <UNDEFINED> instruction: 0xffcf2af0
│ │  	vaddl.u8	q9, d14, d12
│ │  	b.n	3a0fc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x234740>
│ │  	subs	r2, r1, #5
│ │  	b.n	3a1bca <uniffi_pbcli_checksum_method_api_base@@Base+0x235346>
│ │  	adds	r0, #188	@ 0xbc
│ │  	b.n	3a1bce <uniffi_pbcli_checksum_method_api_base@@Base+0x23534a>
│ │  	movs	r0, #2
│ │  	b.n	3a15b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x234d2c>
│ │  	vpmin.s32	q7, <illegal reg q12.5>, <illegal reg q14.5>
│ │ -	bge.n	3a1414 <uniffi_pbcli_checksum_method_api_base@@Base+0x234b90>
│ │ +	bge.n	3a1462 <uniffi_pbcli_checksum_method_api_base@@Base+0x234bde>
│ │  			@ <UNDEFINED> instruction: 0xffcf4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3a19bc <uniffi_pbcli_checksum_method_api_base@@Base+0x235138>
│ │  	ands	r0, r0
│ │  	b.n	3a17e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x234f62>
│ │  			@ <UNDEFINED> instruction: 0xb8e5
│ │  			@ <UNDEFINED> instruction: 0xebff5000
│ │ @@ -1041342,15 +1041342,15 @@
│ │  	b.n	3a181e <uniffi_pbcli_checksum_method_api_base@@Base+0x234f9a>
│ │  	ldmia	r6!, {r0, r1, r2, r3, r4, r5}
│ │  			@ <UNDEFINED> instruction: 0xfa035006
│ │  	b.n	3a1826 <uniffi_pbcli_checksum_method_api_base@@Base+0x234fa2>
│ │  	movs	r5, r0
│ │  	b.n	3a182a <uniffi_pbcli_checksum_method_api_base@@Base+0x234fa6>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r3, r7, r9, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r4, r5, r7, r9, fp, ip, lr, pc}
│ │  	vaddl.u8	<illegal reg q8.5>, d31, d0
│ │  	b.n	3a1c36 <uniffi_pbcli_checksum_method_api_base@@Base+0x2353b2>
│ │  	movs	r0, #64	@ 0x40
│ │  	b.n	3a1c3a <uniffi_pbcli_checksum_method_api_base@@Base+0x2353b6>
│ │  	adds	r0, #0
│ │  	b.n	3a1c3e <uniffi_pbcli_checksum_method_api_base@@Base+0x2353ba>
│ │  	ldr	r6, [pc, #276]	@ (3a1614 <uniffi_pbcli_checksum_method_api_base@@Base+0x234d90>)
│ │ @@ -1057887,15 +1057887,15 @@
│ │  	b.n	3a9542 <uniffi_pbcli_checksum_method_api_base@@Base+0x23ccbe>
│ │  	lsls	r0, r1, #6
│ │  	b.n	3a9530 <uniffi_pbcli_checksum_method_api_base@@Base+0x23ccac>
│ │  	lsrs	r0, r4, #13
│ │  	stcl	0, cr0, [r5, #16]
│ │  	b.n	3a9d6e <uniffi_pbcli_checksum_method_api_base@@Base+0x23d4ea>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r6, r7, r9, fp, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r4, r5, r6, r7, r9, fp, ip, sp, lr, pc}
│ │  	vqshl.u64	d27, d12, #14
│ │  	movs	r1, r2
│ │  	ldr	r3, [pc, #960]	@ (3a9dfc <uniffi_pbcli_checksum_method_api_base@@Base+0x23d578>)
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3a9f5c <uniffi_pbcli_checksum_method_api_base@@Base+0x23d6d8>
│ │  	movs	r0, r0
│ │  	b.n	3aa0ea <uniffi_pbcli_checksum_method_api_base@@Base+0x23d866>
│ │ @@ -1058054,26 +1058054,26 @@
│ │  	ldmia.w	sp!, {r0, ip, lr}
│ │  	b.n	3aa2da <uniffi_pbcli_checksum_method_api_base@@Base+0x23da56>
│ │  	movs	r5, r0
│ │  	b.n	3a9ede <uniffi_pbcli_checksum_method_api_base@@Base+0x23d65a>
│ │  	movs	r0, #0
│ │  	b.n	3a96aa <uniffi_pbcli_checksum_method_api_base@@Base+0x23ce26>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r6, r8, fp, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r4, r5, r6, r8, fp, ip, sp, lr, pc}
│ │  	vmls.i<illegal width 8>	<illegal reg q11.5>, q15, d2[5]
│ │  	vaddl.u8	q9, d13, d12
│ │  	b.n	3a96f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x23ce6c>
│ │  	subs	r1, r3, #0
│ │  	b.n	3aa2f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x23da72>
│ │  	subs	r6, #35	@ 0x23
│ │  	b.n	3aa2fa <uniffi_pbcli_checksum_method_api_base@@Base+0x23da76>
│ │  	movs	r0, #2
│ │  	b.n	3a9cdc <uniffi_pbcli_checksum_method_api_base@@Base+0x23d458>
│ │  	ldmia	r5!, {r1, r2, r3, r4, r6}
│ │ -			@ <UNDEFINED> instruction: 0xeafdf8ff
│ │ +			@ <UNDEFINED> instruction: 0xeafdf926
│ │  			@ <UNDEFINED> instruction: 0xffce4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3aa0e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d864>
│ │  	ands	r0, r0
│ │  	b.n	3a9f12 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d68e>
│ │  	str	r7, [sp, #104]	@ 0x68
│ │  			@ <UNDEFINED> instruction: 0xebff5000
│ │ @@ -1058103,15 +1058103,15 @@
│ │  	b.n	3a9f4a <uniffi_pbcli_checksum_method_api_base@@Base+0x23d6c6>
│ │  	add	r4, sp, #464	@ 0x1d0
│ │  			@ <UNDEFINED> instruction: 0xfa035006
│ │  	b.n	3a9f52 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d6ce>
│ │  	movs	r5, r0
│ │  	b.n	3a9f56 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d6d2>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r3, r6, r7, fp, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r4, r5, r6, r7, fp, ip, sp, lr, pc}
│ │  	vshr.u64	d17, d0, #50
│ │  	b.n	3aa362 <uniffi_pbcli_checksum_method_api_base@@Base+0x23dade>
│ │  	movs	r0, #28
│ │  	b.n	3aa366 <uniffi_pbcli_checksum_method_api_base@@Base+0x23dae2>
│ │  	adds	r0, #2
│ │  	b.n	3aa36a <uniffi_pbcli_checksum_method_api_base@@Base+0x23dae6>
│ │  	cmp	r4, #122	@ 0x7a
│ │ @@ -1058177,15 +1058177,15 @@
│ │  	b.n	3a97d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x23cf52>
│ │  	lsls	r0, r1, #6
│ │  	b.n	3a97c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x23cf40>
│ │  	lsrs	r0, r4, #13
│ │  	stcl	0, cr0, [r5, #16]
│ │  	b.n	3aa002 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d77e>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, fp, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r6, fp, ip, sp, lr, pc}
│ │  	vabal.u8	<illegal reg q13.5>, d14, d8
│ │  	movs	r1, r2
│ │  	asrs	r0, r1, #2
│ │  	b.n	3aa412 <uniffi_pbcli_checksum_method_api_base@@Base+0x23db8e>
│ │  	movs	r0, #32
│ │  	b.n	3aa416 <uniffi_pbcli_checksum_method_api_base@@Base+0x23db92>
│ │  	adds	r0, #2
│ │ @@ -1058232,15 +1058232,15 @@
│ │  	b.n	3a9856 <uniffi_pbcli_checksum_method_api_base@@Base+0x23cfd2>
│ │  	lsls	r0, r1, #6
│ │  	b.n	3a9844 <uniffi_pbcli_checksum_method_api_base@@Base+0x23cfc0>
│ │  	lsrs	r0, r4, #13
│ │  	stcl	0, cr0, [r5, #16]
│ │  	b.n	3aa082 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d7fe>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r6, r7, r8, r9, sl, ip, sp, lr, pc}
│ │  	vraddhn.i16	d27, q15, q4
│ │  	movs	r1, r2
│ │  	asrs	r0, r5, #1
│ │  	b.n	3aa492 <uniffi_pbcli_checksum_method_api_base@@Base+0x23dc0e>
│ │  	movs	r0, #48	@ 0x30
│ │  	b.n	3aa496 <uniffi_pbcli_checksum_method_api_base@@Base+0x23dc12>
│ │  	adds	r0, #2
│ │ @@ -1058287,15 +1058287,15 @@
│ │  	b.n	3a98d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d052>
│ │  	lsls	r0, r1, #6
│ │  	b.n	3a98c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d040>
│ │  	lsrs	r0, r4, #13
│ │  	stcl	0, cr0, [r5, #16]
│ │  	b.n	3aa102 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d87e>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r8, r9, sl, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r6, r8, r9, sl, ip, sp, lr, pc}
│ │  	vraddhn.i16	d27, q7, q4
│ │  	movs	r1, r2
│ │  	asrs	r0, r1, #1
│ │  	b.n	3aa512 <uniffi_pbcli_checksum_method_api_base@@Base+0x23dc8e>
│ │  	movs	r0, #64	@ 0x40
│ │  	b.n	3aa516 <uniffi_pbcli_checksum_method_api_base@@Base+0x23dc92>
│ │  	adds	r0, #2
│ │ @@ -1058342,15 +1058342,15 @@
│ │  	b.n	3a9956 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d0d2>
│ │  	lsls	r0, r1, #6
│ │  	b.n	3a9944 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d0c0>
│ │  	lsrs	r0, r4, #13
│ │  	stcl	0, cr0, [r5, #16]
│ │  	b.n	3aa182 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d8fe>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r7, r9, sl, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r6, r7, r9, sl, ip, sp, lr, pc}
│ │  	vsubw.u8	<illegal reg q13.5>, q15, d8
│ │  	movs	r1, r2
│ │  	asrs	r0, r2, #2
│ │  	b.n	3aa592 <uniffi_pbcli_checksum_method_api_base@@Base+0x23dd0e>
│ │  	movs	r0, #28
│ │  	b.n	3aa596 <uniffi_pbcli_checksum_method_api_base@@Base+0x23dd12>
│ │  	adds	r0, #2
│ │ @@ -1058397,15 +1058397,15 @@
│ │  	b.n	3a99d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d152>
│ │  	lsls	r0, r1, #6
│ │  	b.n	3a99c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d140>
│ │  	lsrs	r0, r4, #13
│ │  	stcl	0, cr0, [r5, #16]
│ │  	b.n	3aa202 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d97e>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r9, sl, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r6, r9, sl, ip, sp, lr, pc}
│ │  	vsubw.u8	<illegal reg q13.5>, q7, d8
│ │  	movs	r1, r2
│ │  	asrs	r0, r1, #2
│ │  	b.n	3aa612 <uniffi_pbcli_checksum_method_api_base@@Base+0x23dd8e>
│ │  	movs	r0, #32
│ │  	b.n	3aa616 <uniffi_pbcli_checksum_method_api_base@@Base+0x23dd92>
│ │  	adds	r0, #2
│ │ @@ -1058452,15 +1058452,15 @@
│ │  	b.n	3a9a56 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d1d2>
│ │  	lsls	r0, r1, #6
│ │  	b.n	3a9a44 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d1c0>
│ │  	lsrs	r0, r4, #13
│ │  	stcl	0, cr0, [r5, #16]
│ │  	b.n	3aa282 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d9fe>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r7, r8, sl, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r6, r7, r8, sl, ip, sp, lr, pc}
│ │  	vsubl.u8	<illegal reg q13.5>, d30, d8
│ │  	movs	r1, r2
│ │  	asrs	r0, r5, #1
│ │  	b.n	3aa692 <uniffi_pbcli_checksum_method_api_base@@Base+0x23de0e>
│ │  	movs	r0, #48	@ 0x30
│ │  	b.n	3aa696 <uniffi_pbcli_checksum_method_api_base@@Base+0x23de12>
│ │  	adds	r0, #2
│ │ @@ -1058507,15 +1058507,15 @@
│ │  	b.n	3a9ad6 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d252>
│ │  	lsls	r0, r1, #6
│ │  	b.n	3a9ac4 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d240>
│ │  	lsrs	r0, r4, #13
│ │  	stcl	0, cr0, [r5, #16]
│ │  	b.n	3aa302 <uniffi_pbcli_checksum_method_api_base@@Base+0x23da7e>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r8, sl, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r6, r8, sl, ip, sp, lr, pc}
│ │  	vsubl.u8	<illegal reg q13.5>, d14, d8
│ │  	movs	r1, r2
│ │  	asrs	r0, r1, #1
│ │  	b.n	3aa712 <uniffi_pbcli_checksum_method_api_base@@Base+0x23de8e>
│ │  	movs	r0, #64	@ 0x40
│ │  	b.n	3aa716 <uniffi_pbcli_checksum_method_api_base@@Base+0x23de92>
│ │  	adds	r0, #2
│ │ @@ -1058568,15 +1058568,15 @@
│ │  	b.n	3a9b62 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d2de>
│ │  	lsls	r0, r1, #6
│ │  	b.n	3a9b4e <uniffi_pbcli_checksum_method_api_base@@Base+0x23d2ca>
│ │  	lsrs	r0, r4, #13
│ │  	stcl	0, cr0, [r4, #20]
│ │  	b.n	3aa38e <uniffi_pbcli_checksum_method_api_base@@Base+0x23db0a>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r7, sl, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r6, r7, sl, ip, sp, lr, pc}
│ │  	vaddw.u8	<illegal reg q13.5>, q15, d12
│ │  	movs	r1, r2
│ │  	asrs	r0, r5, #2
│ │  	b.n	3aa79e <uniffi_pbcli_checksum_method_api_base@@Base+0x23df1a>
│ │  	movs	r0, #0
│ │  	b.n	3aa7a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x23df1e>
│ │  	adds	r0, #1
│ │ @@ -1058728,15 +1058728,15 @@
│ │  	b.n	3aa8f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x23e06e>
│ │  	cbz	r0, 3aa220 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d99c>
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3aa4fa <uniffi_pbcli_checksum_method_api_base@@Base+0x23dc76>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r3, r5, r6, r7, r8, sl, sp, pc}
│ │  	vrsra.u8	<illegal reg q9.5>, <illegal reg q4.5>, #2
│ │ -	vsubw.u8	<illegal reg q15.5>, q7, d19
│ │ +			@ <UNDEFINED> instruction: 0xffcef34a
│ │  	vrsubhn.i16	d21, q7, q10
│ │  	vaddl.u8	q8, d14, d4
│ │  	b.n	3a9d10 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d48c>
│ │  	movs	r0, r0
│ │  	b.n	3aa2f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x23da70>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	add	r7, sp, #1008	@ 0x3f0
│ │ @@ -1058827,15 +1058827,15 @@
│ │  	b.n	3aa9da <uniffi_pbcli_checksum_method_api_base@@Base+0x23e156>
│ │  	cbz	r6, 3aa2f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x23da74>
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3aa5e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x23dd5e>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r2, r3, r4, r8, sl, sp, pc}
│ │  	vrshr.u8	<illegal reg q9.5>, <illegal reg q14.5>, #2
│ │ -	vrshr.u8	d31, d27, #2
│ │ +	vmlal.u<illegal width 8>	<illegal reg q15.5>, d14, d2[4]
│ │  	vmull.u8	q14, d30, d11
│ │  	vaddl.u8	q8, d13, d4
│ │  	b.n	3a9df8 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d574>
│ │  	movs	r0, r0
│ │  	b.n	3aa3dc <uniffi_pbcli_checksum_method_api_base@@Base+0x23db58>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	add	r7, sp, #320	@ 0x140
│ │ @@ -1058887,15 +1058887,15 @@
│ │  	b.n	3a9e4a <uniffi_pbcli_checksum_method_api_base@@Base+0x23d5c6>
│ │  	lsls	r0, r1, #6
│ │  	b.n	3a9e36 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d5b2>
│ │  	lsrs	r0, r4, #13
│ │  	stcl	0, cr0, [r4, #20]
│ │  	b.n	3aa676 <uniffi_pbcli_checksum_method_api_base@@Base+0x23ddf2>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r6, r7, r8, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r4, r5, r6, r7, r8, ip, sp, lr, pc}
│ │  	vmull.p8	q13, d30, d20
│ │  	movs	r1, r2
│ │  	asrs	r0, r1, #2
│ │  	b.n	3aaa86 <uniffi_pbcli_checksum_method_api_base@@Base+0x23e202>
│ │  	movs	r0, #0
│ │  	b.n	3aaa8a <uniffi_pbcli_checksum_method_api_base@@Base+0x23e206>
│ │  	adds	r0, #1
│ │ @@ -1058944,15 +1058944,15 @@
│ │  	b.n	3a9ece <uniffi_pbcli_checksum_method_api_base@@Base+0x23d64a>
│ │  	lsls	r0, r1, #6
│ │  	b.n	3a9ebc <uniffi_pbcli_checksum_method_api_base@@Base+0x23d638>
│ │  	lsrs	r0, r4, #13
│ │  	stcl	0, cr0, [r5, #16]
│ │  	b.n	3aa6fa <uniffi_pbcli_checksum_method_api_base@@Base+0x23de76>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r6, r8, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r5, r6, r8, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffceae10
│ │  	movs	r1, r2
│ │  	asrs	r0, r5, #2
│ │  	b.n	3aab0a <uniffi_pbcli_checksum_method_api_base@@Base+0x23e286>
│ │  	movs	r0, #32
│ │  	b.n	3aab0e <uniffi_pbcli_checksum_method_api_base@@Base+0x23e28a>
│ │  	adds	r0, #1
│ │ @@ -1059001,15 +1059001,15 @@
│ │  	b.n	3a9f52 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d6ce>
│ │  	lsls	r0, r1, #6
│ │  	b.n	3a9f40 <uniffi_pbcli_checksum_method_api_base@@Base+0x23d6bc>
│ │  	lsrs	r0, r4, #13
│ │  	stcl	0, cr0, [r5, #16]
│ │  	b.n	3aa77e <uniffi_pbcli_checksum_method_api_base@@Base+0x23defa>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r7, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r5, r6, r7, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcead8c
│ │  	movs	r1, r2
│ │  	asrs	r0, r1, #2
│ │  	b.n	3aab8e <uniffi_pbcli_checksum_method_api_base@@Base+0x23e30a>
│ │  	movs	r0, #64	@ 0x40
│ │  	b.n	3aab92 <uniffi_pbcli_checksum_method_api_base@@Base+0x23e30e>
│ │  	adds	r0, #1
│ │ @@ -1059646,20 +1059646,20 @@
│ │  	b.n	3aaafc <uniffi_pbcli_checksum_method_api_base@@Base+0x23e278>
│ │  	movs	r0, #2
│ │  	b.n	3aab00 <uniffi_pbcli_checksum_method_api_base@@Base+0x23e27c>
│ │  			@ <UNDEFINED> instruction: 0xffcaeaff
│ │  	str	r7, [r7, #124]	@ 0x7c
│ │  	vmul.i<illegal width 8>	<illegal reg q12.5>, q7, d2[0]
│ │  	vmlsl.u<illegal width 8>	q11, d13, d3[7]
│ │ -	vraddhn.i16	d22, q7, <illegal reg q10.5>
│ │ +	vmls.i<illegal width 8>	q11, q7, d0[3]
│ │  	vmls.i<illegal width 8>	q12, <illegal reg q15.5>, d3[3]
│ │ -			@ <UNDEFINED> instruction: 0xffcd0b34
│ │ +			@ <UNDEFINED> instruction: 0xffcd0b5b
│ │  	vqrdmlsh.s<illegal width 8>	q8, <illegal reg q15.5>, d1[2]
│ │  	vmls.f<illegal width 8>	q11, <illegal reg q6.5>, d3[0]
│ │ -	vmull.u<illegal width 8>	q8, d14, d0[6]
│ │ +	vmlsl.u8	q8, d30, d15
│ │  	vqshl.u64	q12, <illegal reg q7.5>, #15
│ │  			@ <UNDEFINED> instruction: 0xffcd48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3aaf30 <uniffi_pbcli_checksum_method_api_base@@Base+0x23e6ac>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3aad5a <uniffi_pbcli_checksum_method_api_base@@Base+0x23e4d6>
│ │  	lsls	r4, r0, #4
│ │ @@ -1059745,15 +1059745,15 @@
│ │  	b.n	3aae0a <uniffi_pbcli_checksum_method_api_base@@Base+0x23e586>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3ab212 <uniffi_pbcli_checksum_method_api_base@@Base+0x23e98e>
│ │  	beq.n	3aaaea <uniffi_pbcli_checksum_method_api_base@@Base+0x23e266>
│ │  	b.n	3aae16 <uniffi_pbcli_checksum_method_api_base@@Base+0x23e592>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r6, r7, r8, fp, lr}
│ │ +	ldmia.w	sp!, {r3, r5, r6, r7, r8, fp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffcf4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3ab000 <uniffi_pbcli_checksum_method_api_base@@Base+0x23e77c>
│ │  	asrs	r0, r5, #32
│ │  	b.n	3aa628 <uniffi_pbcli_checksum_method_api_base@@Base+0x23dda4>
│ │  	ands	r0, r0
│ │  	b.n	3aae2e <uniffi_pbcli_checksum_method_api_base@@Base+0x23e5aa>
│ │ @@ -1061775,21 +1061775,21 @@
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3ac016 <uniffi_pbcli_checksum_method_api_base@@Base+0x23f792>
│ │  	beq.n	3abd10 <uniffi_pbcli_checksum_method_api_base@@Base+0x23f48c>
│ │  	b.n	3ac170 <uniffi_pbcli_checksum_method_api_base@@Base+0x23f8ec>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r5, r9, sl, fp}
│ │  			@ <UNDEFINED> instruction: 0xffcd0d0b
│ │ -			@ <UNDEFINED> instruction: 0xffcd4a99
│ │ +	vmull.u<illegal width 8>	q10, d29, d0[0]
│ │  	vqrdmulh.s<illegal width 8>	q8, <illegal reg q7.5>, d3[1]
│ │ -	vqrshrun.s16	d31, q4, #3
│ │ +	vqrshrun.s16	d31, <illegal reg q15.5>, #3
│ │  			@ <UNDEFINED> instruction: 0xffce2f56
│ │  	vqdmulh.s<illegal width 8>	q9, <illegal reg q6.5>, d1[3]
│ │ -	vqshl.u8	q14, q2, #6
│ │ -	vshr.u8	<illegal reg q10.5>, <illegal reg q14.5>, #2
│ │ +	vqshl.u8	q14, <illegal reg q13.5>, #6
│ │ +	vaddl.u8	<illegal reg q10.5>, d30, d20
│ │  			@ <UNDEFINED> instruction: 0xffcf0b6b
│ │  	vaddl.u8	q8, d13, d4
│ │  	b.n	3ab848 <uniffi_pbcli_checksum_method_api_base@@Base+0x23efc4>
│ │  	movs	r0, r0
│ │  	b.n	3abe2c <uniffi_pbcli_checksum_method_api_base@@Base+0x23f5a8>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	add	r4, pc, #832	@ (adr r4, 3ac054 <uniffi_pbcli_checksum_method_api_base@@Base+0x23f7d0>)
│ │ @@ -1061831,15 +1061831,15 @@
│ │  	b.n	3ac0a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x23f81e>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3ac4aa <uniffi_pbcli_checksum_method_api_base@@Base+0x23fc26>
│ │  	beq.n	3abd82 <uniffi_pbcli_checksum_method_api_base@@Base+0x23f4fe>
│ │  	b.n	3ac0ae <uniffi_pbcli_checksum_method_api_base@@Base+0x23f82a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r5, r8, r9, sl, ip, sp}
│ │ +	ldmia.w	sp!, {r4, r6, r8, r9, sl, ip, sp}
│ │  			@ <UNDEFINED> instruction: 0xffcf4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3ac298 <uniffi_pbcli_checksum_method_api_base@@Base+0x23fa14>
│ │  	asrs	r0, r5, #32
│ │  	b.n	3ab8c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x23f03c>
│ │  	ands	r0, r0
│ │  	b.n	3ac0c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x23f842>
│ │ @@ -1061857,25 +1061857,25 @@
│ │  	ands	r0, r0
│ │  	asrs	r0, r0, #22
│ │  	asrs	r1, r0, #32
│ │  	asrs	r7, r1, #2
│ │  	asrs	r4, r0, #32
│ │  	asrs	r0, r0, #22
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r5, r6, r9, sl, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r5, r7, r9, sl, ip, sp, lr}
│ │  	vmls.i<illegal width 8>	q13, <illegal reg q15.5>, d0[0]
│ │  	movs	r1, r2
│ │  	asrs	r0, r1, #32
│ │  	b.n	3ab8f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x23f074>
│ │  	movs	r0, #79	@ 0x4f
│ │  	b.n	3ac4fe <uniffi_pbcli_checksum_method_api_base@@Base+0x23fc7a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3abee0 <uniffi_pbcli_checksum_method_api_base@@Base+0x23f65c>
│ │  	stmia	r4!, {r0, r6}
│ │ -			@ <UNDEFINED> instruction: 0xeafd764b
│ │ +			@ <UNDEFINED> instruction: 0xeafd7672
│ │  			@ <UNDEFINED> instruction: 0xffcf0f11
│ │  	b.n	3ac0ac <uniffi_pbcli_checksum_method_api_base@@Base+0x23f828>
│ │  	asrs	r3, r0, #32
│ │  	b.n	3ac1f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x23f970>
│ │  	asrs	r1, r0, #32
│ │  	asrs	r0, r0, #12
│ │  	lsls	r0, r4, #10
│ │ @@ -1062362,26 +1062362,26 @@
│ │  	vpmin.u<illegal width 64>	q15, <illegal reg q8.5>, <illegal reg q15.5>
│ │  	movs	r0, r0
│ │  	b.n	3ac8aa <uniffi_pbcli_checksum_method_api_base@@Base+0x240026>
│ │  			@ <UNDEFINED> instruction: 0xffe01aff
│ │  	str	r0, [r0, r0]
│ │  	b.n	3ac94e <uniffi_pbcli_checksum_method_api_base@@Base+0x2400ca>
│ │  	vpmin.u<illegal width 64>	q7, <illegal reg q8.5>, <illegal reg q15.5>
│ │ -	strb	r3, [r2, #21]
│ │ +	strb	r2, [r7, #21]
│ │  	vshr.u64	d24, d5, #49
│ │ -	vrsra.u64	<illegal reg q11.5>, <illegal reg q3.5>, #51
│ │ +	vrsra.u64	<illegal reg q11.5>, q15, #51
│ │  			@ <UNDEFINED> instruction: 0xffcf7f19
│ │ -	vsubw.u8	<illegal reg q11.5>, <illegal reg q14.5>, d31
│ │ -			@ <UNDEFINED> instruction: 0xffcf7343
│ │ +	vrsra.u64	<illegal reg q11.5>, q3, #51
│ │ +			@ <UNDEFINED> instruction: 0xffcf736a
│ │  	vmull.p8	<illegal reg q11.5>, d31, d5
│ │ -	vabal.u8	<illegal reg q11.5>, d13, d19
│ │ -	vqrdmulh.s<illegal width 8>	q10, <illegal reg q15.5>, d1[2]
│ │ -	vabal.u8	<illegal reg q15.5>, d15, d4
│ │ +	vmls.f<illegal width 8>	<illegal reg q11.5>, <illegal reg q6.5>, d2[2]
│ │ +			@ <UNDEFINED> instruction: 0xffcf4df0
│ │ +	vabal.u8	<illegal reg q15.5>, d15, d27
│ │  			@ <UNDEFINED> instruction: 0xffcef9ad
│ │ -	vraddhn.i16	d23, q6, <illegal reg q13.5>
│ │ +	vsri.8	<illegal reg q11.5>, q1, #4
│ │  			@ <UNDEFINED> instruction: 0xffcf48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3ac764 <uniffi_pbcli_checksum_method_api_base@@Base+0x23fee0>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3ac58e <uniffi_pbcli_checksum_method_api_base@@Base+0x23fd0a>
│ │  	movs	r4, r0
│ │  	b.n	3abd72 <uniffi_pbcli_checksum_method_api_base@@Base+0x23f4ee>
│ │ @@ -1062443,15 +1062443,15 @@
│ │  	ands	r0, r0
│ │  	asrs	r0, r0, #22
│ │  	asrs	r1, r0, #32
│ │  	asrs	r7, r1, #2
│ │  	asrs	r4, r0, #32
│ │  	asrs	r0, r0, #22
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r6, r8, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r4, r5, r6, r8, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffcf9fb0
│ │  	movs	r1, r2
│ │  	ldr	r4, [pc, #64]	@ (3ac324 <uniffi_pbcli_checksum_method_api_base@@Base+0x23faa0>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3ac804 <uniffi_pbcli_checksum_method_api_base@@Base+0x23ff80>
│ │  	ands	r0, r0
│ │  	b.n	3ac62e <uniffi_pbcli_checksum_method_api_base@@Base+0x23fdaa>
│ │ @@ -1062786,31 +1062786,31 @@
│ │  	movs	r0, #0
│ │  	b.n	3accfe <uniffi_pbcli_checksum_method_api_base@@Base+0x24047a>
│ │  	add	r2, sp, #692	@ 0x2b4
│ │  			@ <UNDEFINED> instruction: 0xebfc0000
│ │  	b.n	3acd86 <uniffi_pbcli_checksum_method_api_base@@Base+0x240502>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r0, r3, r4, sl, fp, ip, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffcdff74
│ │ +			@ <UNDEFINED> instruction: 0xffcdff9b
│ │  			@ <UNDEFINED> instruction: 0xffcedbdd
│ │ -			@ <UNDEFINED> instruction: 0xffcdff38
│ │ +			@ <UNDEFINED> instruction: 0xffcdff5f
│ │  			@ <UNDEFINED> instruction: 0xffcedb39
│ │ -			@ <UNDEFINED> instruction: 0xffcdfe94
│ │ +			@ <UNDEFINED> instruction: 0xffcdfebb
│ │  			@ <UNDEFINED> instruction: 0xffcedb55
│ │ -			@ <UNDEFINED> instruction: 0xffcdfeb0
│ │ +			@ <UNDEFINED> instruction: 0xffcdfed7
│ │  			@ <UNDEFINED> instruction: 0xffcedad9
│ │ -			@ <UNDEFINED> instruction: 0xffcdfe34
│ │ +			@ <UNDEFINED> instruction: 0xffcdfe5b
│ │  	vshll.u8	<illegal reg q14.5>, d25, #6
│ │ -			@ <UNDEFINED> instruction: 0xffcdfd94
│ │ +			@ <UNDEFINED> instruction: 0xffcdfdbb
│ │  	vmull.u<illegal width 8>	<illegal reg q14.5>, d14, d1[5]
│ │ -	vqrdmulh.s<illegal width 8>	<illegal reg q15.5>, <illegal reg q14.5>, d0[0]
│ │ +	vqrdmulh.s<illegal width 8>	<illegal reg q15.5>, <illegal reg q14.5>, d3[5]
│ │  	vmlsl.u8	<illegal reg q14.5>, d14, d13
│ │ -	vqrdmulh.s<illegal width 8>	<illegal reg q15.5>, <illegal reg q6.5>, d0[6]
│ │ +			@ <UNDEFINED> instruction: 0xffcdfd8f
│ │  	vmul.f<illegal width 8>	<illegal reg q14.5>, q15, d1[2]
│ │ -			@ <UNDEFINED> instruction: 0xffcdfd24
│ │ +	vqrdmulh.s<illegal width 8>	<illegal reg q15.5>, <illegal reg q6.5>, d3[2]
│ │  	vaddl.u8	<illegal reg q9.5>, d14, d7
│ │  	b.n	3acb16 <uniffi_pbcli_checksum_method_api_base@@Base+0x240292>
│ │  	movs	r0, r0
│ │  	b.n	3accbc <uniffi_pbcli_checksum_method_api_base@@Base+0x240438>
│ │  	adds	r1, #163	@ 0xa3
│ │  	b.n	3ac95e <uniffi_pbcli_checksum_method_api_base@@Base+0x2400da>
│ │  	movs	r5, r0
│ │ @@ -1063502,15 +1063502,15 @@
│ │  	b.n	3acf2e <uniffi_pbcli_checksum_method_api_base@@Base+0x2406aa>
│ │  	ldmia	r6!, {r0, r1, r2, r3, r4}
│ │  	b.n	3ad332 <uniffi_pbcli_checksum_method_api_base@@Base+0x240aae>
│ │  	movs	r0, r1
│ │  	b.n	3acf36 <uniffi_pbcli_checksum_method_api_base@@Base+0x2406b2>
│ │  	vpmin.u<illegal width 64>	q7, q14, <illegal reg q15.5>
│ │  	bvs.n	3acca6 <uniffi_pbcli_checksum_method_api_base@@Base+0x240422>
│ │ -	vmull.u<illegal width 8>	q12, d29, d0[6]
│ │ +			@ <UNDEFINED> instruction: 0xffcd8b0f
│ │  			@ <UNDEFINED> instruction: 0xffce4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3ad124 <uniffi_pbcli_checksum_method_api_base@@Base+0x2408a0>
│ │  	beq.n	3acc44 <uniffi_pbcli_checksum_method_api_base@@Base+0x2403c0>
│ │  	b.n	3ad0a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x240824>
│ │  	ands	r3, r0
│ │  	b.n	3ad212 <uniffi_pbcli_checksum_method_api_base@@Base+0x24098e>
│ │ @@ -1063901,15 +1063901,15 @@
│ │  	b.n	3ad69a <uniffi_pbcli_checksum_method_api_base@@Base+0x240e16>
│ │  	str	r0, [sp, #32]
│ │  	b.n	3aca98 <uniffi_pbcli_checksum_method_api_base@@Base+0x240214>
│ │  	add	r0, pc, #16	@ (adr r0, 3acf70 <uniffi_pbcli_checksum_method_api_base@@Base+0x2406ec>)
│ │  	b.n	3aca9c <uniffi_pbcli_checksum_method_api_base@@Base+0x240218>
│ │  			@ <UNDEFINED> instruction: 0xff8ceaff
│ │  	bne.n	3acef2 <uniffi_pbcli_checksum_method_api_base@@Base+0x24066e>
│ │ -	vqshl.u8	d28, d25, #5
│ │ +			@ <UNDEFINED> instruction: 0xffcdc760
│ │  	vqshrun.s16	d20, q8, #2
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3ad490 <uniffi_pbcli_checksum_method_api_base@@Base+0x240c0c>
│ │  	beq.n	3acf88 <uniffi_pbcli_checksum_method_api_base@@Base+0x240704>
│ │  	b.n	3ad414 <uniffi_pbcli_checksum_method_api_base@@Base+0x240b90>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3ad2be <uniffi_pbcli_checksum_method_api_base@@Base+0x240a3a>
│ │ @@ -1064735,19 +1064735,19 @@
│ │  	vpmin.u<illegal width 64>	q15, <illegal reg q14.5>, <illegal reg q15.5>
│ │  	ldmia	r4, {r0, r4, r5, r6}
│ │  	vrsra.u64	d30, d27, #51
│ │  			@ <UNDEFINED> instruction: 0xffcdccfd
│ │  			@ <UNDEFINED> instruction: 0xffcdcc3d
│ │  	vsubw.u8	q15, <illegal reg q14.5>, d7
│ │  	vmull.u8	q14, d13, d9
│ │ -			@ <UNDEFINED> instruction: 0xffcdef78
│ │ +			@ <UNDEFINED> instruction: 0xffcdef9f
│ │  			@ <UNDEFINED> instruction: 0xffcecb99
│ │ -	vmlal.u8	<illegal reg q12.5>, d13, d2
│ │ +	vmlal.u8	<illegal reg q12.5>, d13, d25
│ │  			@ <UNDEFINED> instruction: 0xffcecb05
│ │ -			@ <UNDEFINED> instruction: 0xffcdee74
│ │ +			@ <UNDEFINED> instruction: 0xffcdee9b
│ │  	vmlsl.u8	q14, d30, d21
│ │  	vmlsl.u8	q14, d29, d13
│ │  	vmlal.u8	q10, d13, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3ada16 <uniffi_pbcli_checksum_method_api_base@@Base+0x241192>
│ │  	beq.n	3ad708 <uniffi_pbcli_checksum_method_api_base@@Base+0x240e84>
│ │  	b.n	3adb74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2412f0>
│ │ @@ -1065188,15 +1065188,15 @@
│ │  			@ <UNDEFINED> instruction: 0xffd1eaff
│ │  	strh	r2, [r1, #0]
│ │  	b.n	3addd2 <uniffi_pbcli_checksum_method_api_base@@Base+0x24154e>
│ │  			@ <UNDEFINED> instruction: 0xffceeaff
│ │  	ldmia	r0, {r0, r2, r3, r4}
│ │  	vsli.64	d28, d29, #13
│ │  			@ <UNDEFINED> instruction: 0xffcd4ad9
│ │ -	vraddhn.i16	d25, q7, q11
│ │ +	vmls.i<illegal width 8>	<illegal reg q12.5>, q7, d1[3]
│ │  	vmls.f<illegal width 8>	q14, q7, d1[6]
│ │  	vsli.8	d28, d25, #5
│ │  	vsli.8	d28, d9, #5
│ │  	vqshl.u64	q12, q13, #13
│ │  			@ <UNDEFINED> instruction: 0xffcf4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3adfd8 <uniffi_pbcli_checksum_method_api_base@@Base+0x241754>
│ │ @@ -1065907,15 +1065907,15 @@
│ │  	b.n	3ae80e <uniffi_pbcli_checksum_method_api_base@@Base+0x241f8a>
│ │  	mcr2	10, 7, lr, cr6, cr15, {7}	@ <UNPREDICTABLE>
│ │  	adds	r7, #77	@ 0x4d
│ │  	vmls.i<illegal width 8>	q14, q7, d1[2]
│ │  			@ <UNDEFINED> instruction: 0xffcd4d05
│ │  	vsli.8	d26, d7, #5
│ │  			@ <UNDEFINED> instruction: 0xffccbef1
│ │ -	vsri.8	<illegal reg q13.5>, <illegal reg q15.5>, #3
│ │ +	vraddhn.i16	d27, <illegal reg q14.5>, q11
│ │  	vrshr.u64	q14, <illegal reg q0.5>, #50
│ │  			@ <UNDEFINED> instruction: 0xffcd4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3ae610 <uniffi_pbcli_checksum_method_api_base@@Base+0x241d8c>
│ │  	beq.n	3ae000 <uniffi_pbcli_checksum_method_api_base@@Base+0x24177c>
│ │  	b.n	3ae594 <uniffi_pbcli_checksum_method_api_base@@Base+0x241d10>
│ │  	strb	r1, [r0, #0]
│ │ @@ -1066063,20 +1066063,20 @@
│ │  	b.n	3ae57a <uniffi_pbcli_checksum_method_api_base@@Base+0x241cf6>
│ │  	movs	r5, #107	@ 0x6b
│ │  			@ <UNDEFINED> instruction: 0xebfd0005
│ │  	b.n	3ae582 <uniffi_pbcli_checksum_method_api_base@@Base+0x241cfe>
│ │  	beq.n	3ae27c <uniffi_pbcli_checksum_method_api_base@@Base+0x2419f8>
│ │  	b.n	3ae6dc <uniffi_pbcli_checksum_method_api_base@@Base+0x241e58>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r8, r9, ip, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r6, r8, r9, ip, lr}
│ │  	vmlsl.u8	<illegal reg q13.5>, d31, d3
│ │  			@ <UNDEFINED> instruction: 0xffcc68f4
│ │  	vshr.u8	q13, q14, #3
│ │ -			@ <UNDEFINED> instruction: 0xffcc3f75
│ │ -	vsubl.u8	<illegal reg q8.5>, d31, d9
│ │ +			@ <UNDEFINED> instruction: 0xffcc3f9c
│ │ +	vrshr.u64	d17, d16, #49
│ │  			@ <UNDEFINED> instruction: 0xffcf4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3ae784 <uniffi_pbcli_checksum_method_api_base@@Base+0x241f00>
│ │  	asrs	r4, r3, #32
│ │  	b.n	3addac <uniffi_pbcli_checksum_method_api_base@@Base+0x241528>
│ │  	ands	r0, r0
│ │  	b.n	3ae5b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x241d2e>
│ │ @@ -1066589,37 +1066589,37 @@
│ │  			@ <UNDEFINED> instruction: 0xebfd0005
│ │  	b.n	3aea2a <uniffi_pbcli_checksum_method_api_base@@Base+0x2421a6>
│ │  	beq.n	3ae71c <uniffi_pbcli_checksum_method_api_base@@Base+0x241e98>
│ │  	b.n	3aeb84 <uniffi_pbcli_checksum_method_api_base@@Base+0x242300>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r2, r5, r6, r7, r8, r9}
│ │  	movs	r0, r0
│ │ -	stmia	r1!, {r1, r2, r3, r5, r7}
│ │ -	vmla.i<illegal width 8>	q12, q15, d2[3]
│ │ +	stmia	r1!, {r0, r2, r4, r6, r7}
│ │ +	vshr.u64	q12, <illegal reg q10.5>, #50
│ │  			@ <UNDEFINED> instruction: 0xffcef760
│ │ -	vsubl.u8	q11, d12, d31
│ │ +	vrshr.u8	q11, q3, #4
│ │  	vqshrun.s16	d31, <illegal reg q1.5>, #1
│ │  	vrshr.u64	<illegal reg q14.5>, q1, #51
│ │  	vrshr.u8	d27, d6, #3
│ │ -	vsri.64	q12, <illegal reg q2.5>, #52
│ │ +	vsri.64	q12, q14, #52
│ │  			@ <UNDEFINED> instruction: 0xffce2b29
│ │  			@ <UNDEFINED> instruction: 0xffce5ab7
│ │ -	vmls.f<illegal width 8>	q14, q15, d3[7]
│ │ +	vqshlu.s8	d28, d6, #6
│ │  	vrsra.u64	d20, d22, #50
│ │ -			@ <UNDEFINED> instruction: 0xffcdde50
│ │ +			@ <UNDEFINED> instruction: 0xffcdde77
│ │  	vmull.p8	<illegal reg q9.5>, d14, d11
│ │  			@ <UNDEFINED> instruction: 0xffcd77c7
│ │  			@ <UNDEFINED> instruction: 0xffcf0dba
│ │  			@ <UNDEFINED> instruction: 0xffce9cff
│ │  			@ <UNDEFINED> instruction: 0xffcd7d10
│ │  	movs	r1, r2
│ │ -	ldmia	r6, {r2, r3, r4, r6}
│ │ +	ldmia	r6!, {r0, r1, r7}
│ │  	vsli.8	q8, q5, #6
│ │ -			@ <UNDEFINED> instruction: 0xffcd9d58
│ │ -	vrsubhn.i16	d18, q15, <illegal reg q2.5>
│ │ +			@ <UNDEFINED> instruction: 0xffcd9d7f
│ │ +	vrsubhn.i16	d18, q15, q14
│ │  	vqrshrun.s16	d18, q12, #1
│ │  	vmlal.u8	q10, d14, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3aea9a <uniffi_pbcli_checksum_method_api_base@@Base+0x242216>
│ │  	beq.n	3ae76c <uniffi_pbcli_checksum_method_api_base@@Base+0x241ee8>
│ │  	b.n	3aebf8 <uniffi_pbcli_checksum_method_api_base@@Base+0x242374>
│ │  	movs	r0, r0
│ │ @@ -1066946,16 +1066946,16 @@
│ │  	movs	r5, r0
│ │  	b.n	3aed6e <uniffi_pbcli_checksum_method_api_base@@Base+0x2424ea>
│ │  	beq.n	3aea68 <uniffi_pbcli_checksum_method_api_base@@Base+0x2421e4>
│ │  	b.n	3aeec8 <uniffi_pbcli_checksum_method_api_base@@Base+0x242644>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r2, r5, r7, r8, r9, fp, sp, lr, pc}
│ │  	movs	r2, r2
│ │ -	movs	r3, #125	@ 0x7d
│ │ -	vmull.u<illegal width 8>	q14, d31, d0[0]
│ │ +	movs	r3, #164	@ 0xa4
│ │ +	vmull.u<illegal width 8>	q14, d31, d3[5]
│ │  	vqrdmlsh.s<illegal width 8>	q14, q7, d1[6]
│ │  			@ <UNDEFINED> instruction: 0xffcc48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3aef68 <uniffi_pbcli_checksum_method_api_base@@Base+0x2426e4>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3aed92 <uniffi_pbcli_checksum_method_api_base@@Base+0x24250e>
│ │  	lsls	r4, r0, #4
│ │ @@ -1067041,15 +1067041,15 @@
│ │  	b.n	3aee42 <uniffi_pbcli_checksum_method_api_base@@Base+0x2425be>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3af24a <uniffi_pbcli_checksum_method_api_base@@Base+0x2429c6>
│ │  	beq.n	3aeb22 <uniffi_pbcli_checksum_method_api_base@@Base+0x24229e>
│ │  	b.n	3aee4e <uniffi_pbcli_checksum_method_api_base@@Base+0x2425ca>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r7, r8, fp}
│ │ +	ldmia.w	sp!, {r4, r5, r7, r8, fp}
│ │  			@ <UNDEFINED> instruction: 0xffcf4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3af038 <uniffi_pbcli_checksum_method_api_base@@Base+0x2427b4>
│ │  	asrs	r0, r5, #32
│ │  	b.n	3ae660 <uniffi_pbcli_checksum_method_api_base@@Base+0x241ddc>
│ │  	ands	r0, r0
│ │  	b.n	3aee66 <uniffi_pbcli_checksum_method_api_base@@Base+0x2425e2>
│ │ @@ -1067103,23 +1067103,23 @@
│ │  	b.n	3aecb4 <uniffi_pbcli_checksum_method_api_base@@Base+0x242430>
│ │  			@ <UNDEFINED> instruction: 0xb7f2
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	3af23e <uniffi_pbcli_checksum_method_api_base@@Base+0x2429ba>
│ │  	ands	r0, r0
│ │  	asrs	r0, r0, #22
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r6, r7, r9, sl, fp, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r8, r9, sl, fp, ip, sp, pc}
│ │  	vaddl.u8	<illegal reg q8.5>, d14, d8
│ │  	b.n	3ae6ec <uniffi_pbcli_checksum_method_api_base@@Base+0x241e68>
│ │  	movs	r0, #51	@ 0x33
│ │  	b.n	3af2f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x242a6e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3aecd4 <uniffi_pbcli_checksum_method_api_base@@Base+0x242450>
│ │  			@ <UNDEFINED> instruction: 0xb8c4
│ │ -			@ <UNDEFINED> instruction: 0xeafdbebe
│ │ +			@ <UNDEFINED> instruction: 0xeafdbee5
│ │  			@ <UNDEFINED> instruction: 0xffce4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3af0e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24285c>
│ │  	beq.n	3aeb68 <uniffi_pbcli_checksum_method_api_base@@Base+0x2422e4>
│ │  	b.n	3af064 <uniffi_pbcli_checksum_method_api_base@@Base+0x2427e0>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3aef0e <uniffi_pbcli_checksum_method_api_base@@Base+0x24268a>
│ │ @@ -1067357,20 +1067357,20 @@
│ │  	b.n	3aeef4 <uniffi_pbcli_checksum_method_api_base@@Base+0x242670>
│ │  			@ <UNDEFINED> instruction: 0xb83c
│ │  			@ <UNDEFINED> instruction: 0xebfd0006
│ │  	b.n	3af11e <uniffi_pbcli_checksum_method_api_base@@Base+0x24289a>
│ │  	beq.n	3aee10 <uniffi_pbcli_checksum_method_api_base@@Base+0x24258c>
│ │  	b.n	3af278 <uniffi_pbcli_checksum_method_api_base@@Base+0x2429f4>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r2, r3, r4, r6, r8, r9, sl, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r7, r8, r9, sl, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcefe56
│ │  	vmlal.u8	q8, d28, d4
│ │ -	vqshlu.s8	<illegal reg q12.5>, q0, #6
│ │ -			@ <UNDEFINED> instruction: 0xffce1f7d
│ │ -			@ <UNDEFINED> instruction: 0xffcfbc9e
│ │ +	vqshlu.s8	<illegal reg q12.5>, <illegal reg q11.5>, #6
│ │ +			@ <UNDEFINED> instruction: 0xffce1fa4
│ │ +	vqdmulh.s<illegal width 8>	<illegal reg q13.5>, <illegal reg q15.5>, d1[1]
│ │  	vaddl.u8	q8, d14, d4
│ │  	b.n	3ae940 <uniffi_pbcli_checksum_method_api_base@@Base+0x2420bc>
│ │  	movs	r0, r0
│ │  	b.n	3aef24 <uniffi_pbcli_checksum_method_api_base@@Base+0x2426a0>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	strb	r0, [r2, #27]
│ │  	movs	r1, r2
│ │ @@ -1067411,15 +1067411,15 @@
│ │  	b.n	3af19a <uniffi_pbcli_checksum_method_api_base@@Base+0x242916>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3af5a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x242d1e>
│ │  	beq.n	3aee7a <uniffi_pbcli_checksum_method_api_base@@Base+0x2425f6>
│ │  	b.n	3af1a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x242922>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r4, r5, r9, sl}
│ │ +	ldmia.w	sp!, {r3, r4, r6, r9, sl}
│ │  			@ <UNDEFINED> instruction: 0xffcf4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3af390 <uniffi_pbcli_checksum_method_api_base@@Base+0x242b0c>
│ │  	asrs	r4, r4, #32
│ │  	b.n	3ae9b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x242134>
│ │  	ands	r0, r0
│ │  	b.n	3af1be <uniffi_pbcli_checksum_method_api_base@@Base+0x24293a>
│ │ @@ -1067435,15 +1067435,15 @@
│ │  	asrs	r1, r0, #32
│ │  	asrs	r0, r4, #14
│ │  	ands	r0, r0
│ │  	asrs	r0, r0, #22
│ │  	asrs	r4, r0, #32
│ │  	asrs	r0, r0, #22
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r4, r6, r8, r9, sl, ip}
│ │ +	ldmia.w	sp!, {r3, r4, r5, r6, r8, r9, sl, ip}
│ │  			@ <UNDEFINED> instruction: 0xffcf4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3af3c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x242b44>
│ │  	ands	r0, r0
│ │  	b.n	3af1f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x24296e>
│ │  	movs	r0, r2
│ │  	b.n	3af3b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x242b32>
│ │ @@ -1067457,15 +1067457,15 @@
│ │  	b.n	3af20a <uniffi_pbcli_checksum_method_api_base@@Base+0x242986>
│ │  	movs	r3, #193	@ 0xc1
│ │  	b.n	3af4ce <uniffi_pbcli_checksum_method_api_base@@Base+0x242c4a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3aeff0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24276c>
│ │  	ldr	r4, [pc, #64]	@ (3aef14 <uniffi_pbcli_checksum_method_api_base@@Base+0x242690>)
│ │  	ldmia.w	sp!, {r2, r3, r4, r5, r6, r7, r8, r9, sl, ip, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xeafd1709
│ │ +			@ <UNDEFINED> instruction: 0xeafd1730
│ │  	vaddl.u8	q8, d15, d4
│ │  	b.n	3aea20 <uniffi_pbcli_checksum_method_api_base@@Base+0x24219c>
│ │  	movs	r0, r0
│ │  	b.n	3af004 <uniffi_pbcli_checksum_method_api_base@@Base+0x242780>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	str	r1, [sp, #672]	@ 0x2a0
│ │  	movs	r1, r2
│ │ @@ -1067591,16 +1067591,16 @@
│ │  	and.w	r0, r0, r0, lsl #28
│ │  	b.n	3af736 <uniffi_pbcli_checksum_method_api_base@@Base+0x242eb2>
│ │  	movs	r7, r0
│ │  	b.n	3af33a <uniffi_pbcli_checksum_method_api_base@@Base+0x242ab6>
│ │  	beq.n	3af02c <uniffi_pbcli_checksum_method_api_base@@Base+0x2427a8>
│ │  	b.n	3af494 <uniffi_pbcli_checksum_method_api_base@@Base+0x242c10>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r5, r6, r8, fp, sp, pc}
│ │ -	vsli.8	d16, d17, #6
│ │ +	ldmia.w	sp!, {r0, r2, r5, r7, r8, fp, sp, pc}
│ │ +	vsli.8	q8, q4, #6
│ │  			@ <UNDEFINED> instruction: 0xffcffc3a
│ │  			@ <UNDEFINED> instruction: 0xffcd0f11
│ │  	b.n	3af2f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x242a6c>
│ │  	asrs	r3, r0, #32
│ │  	b.n	3af438 <uniffi_pbcli_checksum_method_api_base@@Base+0x242bb4>
│ │  	asrs	r1, r0, #32
│ │  	asrs	r0, r0, #12
│ │ @@ -1067744,22 +1067744,22 @@
│ │  	movs	r0, r0
│ │  	strh	r4, [r0, #58]	@ 0x3a
│ │  	movs	r0, r0
│ │  	b.n	3af840 <uniffi_pbcli_checksum_method_api_base@@Base+0x242fbc>
│ │  	movs	r2, r2
│ │  	strh	r0, [r2, #52]	@ 0x34
│ │  	movs	r0, r0
│ │ -	bcs.n	3af188 <uniffi_pbcli_checksum_method_api_base@@Base+0x242904>
│ │ +	bcs.n	3af1d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x242952>
│ │  	vmlsl.u<illegal width 8>	q12, d30, d0[1]
│ │  	movs	r0, r0
│ │  	strh	r0, [r6, #58]	@ 0x3a
│ │  	movs	r0, r0
│ │  	b.n	3af8b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x243030>
│ │  	movs	r2, r2
│ │ -	asrs	r1, r3, #21
│ │ +	asrs	r0, r0, #22
│ │  	vsli.64	d26, d21, #15
│ │  	vaddl.u8	q8, d12, d0
│ │  	b.n	3af814 <uniffi_pbcli_checksum_method_api_base@@Base+0x242f90>
│ │  	movs	r1, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	movs	r0, r0
│ │ @@ -1067977,23 +1067977,23 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	3afa9a <uniffi_pbcli_checksum_method_api_base@@Base+0x243216>
│ │  	ldr	r7, [sp, #280]	@ 0x118
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3af6a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x242e1e>
│ │  	adds	r3, #188	@ 0xbc
│ │  			@ <UNDEFINED> instruction: 0xebfbffa8
│ │ -			@ <UNDEFINED> instruction: 0xeaff135d
│ │ -	vrshr.u64	d26, d4, #49
│ │ -	vsubl.u8	<illegal reg q8.5>, d30, d17
│ │ +			@ <UNDEFINED> instruction: 0xeaff1384
│ │ +	vrshr.u64	d26, d27, #49
│ │ +	vmlal.u<illegal width 8>	<illegal reg q8.5>, d30, d0[2]
│ │  	vsubw.u8	q13, <illegal reg q7.5>, d21
│ │ -	vmlal.u<illegal width 8>	<illegal reg q8.5>, d28, d1[2]
│ │ -	vrsra.u8	<illegal reg q8.5>, <illegal reg q12.5>, #1
│ │ -	vrshr.u64	d26, d16, #49
│ │ -			@ <UNDEFINED> instruction: 0xffce13ed
│ │ -	vrshr.u8	q10, q7, #1
│ │ +	vrshr.u64	<illegal reg q8.5>, q8, #52
│ │ +	vsubw.u8	<illegal reg q8.5>, <illegal reg q15.5>, d16
│ │ +	vrshr.u64	q13, <illegal reg q3.5>, #49
│ │ +	vsri.8	d17, d4, #2
│ │ +	vsubl.u8	q10, d31, d5
│ │  	vaddl.u8	q8, d15, d0
│ │  	b.n	3afa34 <uniffi_pbcli_checksum_method_api_base@@Base+0x2431b0>
│ │  	movs	r1, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	movs	r0, r0
│ │  	b.n	3afade <uniffi_pbcli_checksum_method_api_base@@Base+0x24325a>
│ │ @@ -1068210,22 +1068210,22 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	3afcba <uniffi_pbcli_checksum_method_api_base@@Base+0x243436>
│ │  	ldr	r6, [sp, #760]	@ 0x2f8
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3af8c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x24303e>
│ │  	adds	r3, #52	@ 0x34
│ │  			@ <UNDEFINED> instruction: 0xebfbffa8
│ │ -			@ <UNDEFINED> instruction: 0xeaff1115
│ │ -	vmla.i<illegal width 8>	q13, <illegal reg q7.5>, d0[3]
│ │ -	vaddl.u8	<illegal reg q8.5>, d30, d1
│ │ +			@ <UNDEFINED> instruction: 0xeaff113c
│ │ +	vshr.u8	q13, <illegal reg q9.5>, #1
│ │ +	vaddl.u8	<illegal reg q8.5>, d30, d24
│ │  	vaddw.u8	q13, <illegal reg q7.5>, d5
│ │ -	vaddl.u8	<illegal reg q8.5>, d28, d25
│ │ -	vmla.i<illegal width 8>	<illegal reg q8.5>, <illegal reg q15.5>, d1[7]
│ │ -	vaddl.u8	q13, d15, d20
│ │ -	vmla.f<illegal width 8>	<illegal reg q8.5>, q15, d1[3]
│ │ +	vshr.u64	<illegal reg q8.5>, q0, #52
│ │ +	vsra.u8	d17, d4, #1
│ │ +	vmla.i<illegal width 8>	q13, <illegal reg q7.5>, d3[2]
│ │ +	vsra.u64	<illegal reg q8.5>, q10, #50
│ │  	vrsra.u64	q8, q15, #49
│ │  			@ <UNDEFINED> instruction: 0xffce0f11
│ │  	b.n	3af890 <uniffi_pbcli_checksum_method_api_base@@Base+0x24300c>
│ │  	asrs	r7, r0, #2
│ │  	b.n	3af9d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x243154>
│ │  	asrs	r1, r0, #32
│ │  	asrs	r0, r0, #12
│ │ @@ -1068457,20 +1068457,20 @@
│ │  	ldr	r7, [sp, #40]	@ 0x28
│ │  	vaddl.u8	q12, d28, d0
│ │  	movs	r0, r0
│ │  	strh	r0, [r3, #26]
│ │  	movs	r0, r0
│ │  	bgt.n	3af6d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x242e4c>
│ │  	movs	r2, r2
│ │ -	lsrs	r5, r4, #25
│ │ -			@ <UNDEFINED> instruction: 0xffcf9d9c
│ │ -	vrshr.u8	<illegal reg q11.5>, <illegal reg q2.5>, #2
│ │ +	lsrs	r4, r1, #26
│ │ +	vqrdmulh.s<illegal width 8>	<illegal reg q12.5>, <illegal reg q15.5>, d3[0]
│ │ +	vrshr.u8	<illegal reg q11.5>, q14, #2
│ │  			@ <UNDEFINED> instruction: 0xffcedd00
│ │  	movs	r2, r2
│ │ -	lsrs	r1, r7, #30
│ │ +	lsrs	r0, r4, #31
│ │  			@ <UNDEFINED> instruction: 0xffcf48fd
│ │  	vaddl.u8	q8, d14, d1
│ │  	b.n	3aff16 <uniffi_pbcli_checksum_method_api_base@@Base+0x243692>
│ │  	movs	r0, r0
│ │  	b.n	3afe7c <uniffi_pbcli_checksum_method_api_base@@Base+0x2435f8>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	movs	r1, r0
│ │ @@ -1068691,20 +1068691,20 @@
│ │  	movs	r1, r7
│ │  	b.n	3b00fe <uniffi_pbcli_checksum_method_api_base@@Base+0x24387a>
│ │  	ldr	r5, [sp, #692]	@ 0x2b4
│ │  			@ <UNDEFINED> instruction: 0xebfc0005
│ │  	b.n	3afd06 <uniffi_pbcli_checksum_method_api_base@@Base+0x243482>
│ │  	adds	r2, #35	@ 0x23
│ │  			@ <UNDEFINED> instruction: 0xebfbffab
│ │ -			@ <UNDEFINED> instruction: 0xeaff0c61
│ │ -			@ <UNDEFINED> instruction: 0xffcf9b98
│ │ -			@ <UNDEFINED> instruction: 0xffce0c39
│ │ +			@ <UNDEFINED> instruction: 0xeaff0c88
│ │ +			@ <UNDEFINED> instruction: 0xffcf9bbf
│ │ +	vqdmulh.s<illegal width 8>	q8, q7, d0[4]
│ │  			@ <UNDEFINED> instruction: 0xffcf9cbd
│ │ -			@ <UNDEFINED> instruction: 0xffcc0cdd
│ │ -			@ <UNDEFINED> instruction: 0xffcf0d7d
│ │ +			@ <UNDEFINED> instruction: 0xffcc0d04
│ │ +			@ <UNDEFINED> instruction: 0xffcf0da4
│ │  	vsra.u64	d16, d12, #49
│ │  	vmlsl.u<illegal width 8>	<illegal reg q8.5>, d13, d1[3]
│ │  	vmull.p8	<illegal reg q11.5>, d30, d0
│ │  	movs	r0, r0
│ │  	strh	r0, [r1, #20]
│ │  	movs	r0, r0
│ │  	bge.n	3af930 <uniffi_pbcli_checksum_method_api_base@@Base+0x2430ac>
│ │ @@ -1068932,21 +1068932,21 @@
│ │  	movs	r1, r7
│ │  	b.n	3b0326 <uniffi_pbcli_checksum_method_api_base@@Base+0x243aa2>
│ │  	ldr	r5, [sp, #140]	@ 0x8c
│ │  			@ <UNDEFINED> instruction: 0xebfc0005
│ │  	b.n	3aff2e <uniffi_pbcli_checksum_method_api_base@@Base+0x2436aa>
│ │  	adds	r1, #153	@ 0x99
│ │  			@ <UNDEFINED> instruction: 0xebfbffab
│ │ -			@ <UNDEFINED> instruction: 0xeaff0a39
│ │ -	vqrshrn.u16	d25, q8, #1
│ │ -	vshll.u8	q8, d1, #6
│ │ +			@ <UNDEFINED> instruction: 0xeaff0a60
│ │ +			@ <UNDEFINED> instruction: 0xffcf9997
│ │ +	vshll.u8	q8, d24, #6
│ │  			@ <UNDEFINED> instruction: 0xffcf9a95
│ │ -			@ <UNDEFINED> instruction: 0xffcc0ab5
│ │ -			@ <UNDEFINED> instruction: 0xffcf0b55
│ │ -	vmul.f<illegal width 8>	<illegal reg q9.5>, <illegal reg q15.5>, d0[7]
│ │ +			@ <UNDEFINED> instruction: 0xffcc0adc
│ │ +			@ <UNDEFINED> instruction: 0xffcf0b7c
│ │ +	vshll.u8	<illegal reg q9.5>, d3, #7
│ │  			@ <UNDEFINED> instruction: 0xffcf2d0a
│ │  			@ <UNDEFINED> instruction: 0xffcd7c58
│ │  	movs	r0, r0
│ │  	strh	r0, [r4, #2]
│ │  	movs	r0, r0
│ │  	bhi.n	3afd08 <uniffi_pbcli_checksum_method_api_base@@Base+0x243484>
│ │  	movs	r2, r2
│ │ @@ -1069203,28 +1069203,28 @@
│ │  	b.n	3b04ea <uniffi_pbcli_checksum_method_api_base@@Base+0x243c66>
│ │  	ands	r1, r0
│ │  	stmia	r3!, {}
│ │  	movs	r1, r1
│ │  	b.n	3b0192 <uniffi_pbcli_checksum_method_api_base@@Base+0x24390e>
│ │  	adds	r1, #0
│ │  			@ <UNDEFINED> instruction: 0xebfbff96
│ │ -			@ <UNDEFINED> instruction: 0xeaff0825
│ │ -	vqshl.u8	<illegal reg q12.5>, q6, #7
│ │ +			@ <UNDEFINED> instruction: 0xeaff084c
│ │ +	vabdl.u8	<illegal reg q12.5>, d31, d3
│ │  	vmlsl.u8	q9, d14, d18
│ │  	vmlsl.u<illegal width 8>	<illegal reg q14.5>, d13, d0[1]
│ │  	movs	r2, r2
│ │  	bvs.n	3aff1c <uniffi_pbcli_checksum_method_api_base@@Base+0x243698>
│ │  	movs	r2, r2
│ │ -	stmia	r5!, {r2, r5, r7}
│ │ +	stmia	r5!, {r0, r1, r3, r6, r7}
│ │  	vqshl.u8	d29, d16, #6
│ │  	movs	r2, r2
│ │ -	lsrs	r1, r0, #1
│ │ -	vqshl.u8	<illegal reg q12.5>, q12, #7
│ │ -	vmul.f<illegal width 8>	q8, q7, d1[1]
│ │ -	vmlal.u<illegal width 8>	<illegal reg q15.5>, d31, d2[5]
│ │ +	lsrs	r0, r5, #1
│ │ +	vqshl.u64	d25, d15, #15
│ │ +	vmul.f<illegal width 8>	q8, q7, d0[7]
│ │ +	vsubw.u8	<illegal reg q15.5>, <illegal reg q7.5>, d13
│ │  	vaddl.u8	q8, d14, d0
│ │  	b.n	3b052c <uniffi_pbcli_checksum_method_api_base@@Base+0x243ca8>
│ │  	movs	r1, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	movs	r0, r0
│ │  	b.n	3b05d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x243d52>
│ │ @@ -1069393,23 +1069393,23 @@
│ │  	movs	r0, r0
│ │  	and.w	r0, r0, r0, lsl #16
│ │  	b.n	3b0746 <uniffi_pbcli_checksum_method_api_base@@Base+0x243ec2>
│ │  	movs	r6, r0
│ │  	b.n	3b034a <uniffi_pbcli_checksum_method_api_base@@Base+0x243ac6>
│ │  	adds	r0, #146	@ 0x92
│ │  			@ <UNDEFINED> instruction: 0xebfbffc4
│ │ -			@ <UNDEFINED> instruction: 0xeaff0645
│ │ -	vsli.8	<illegal reg q12.5>, q14, #7
│ │ +			@ <UNDEFINED> instruction: 0xeaff066c
│ │ +	vabal.u8	<illegal reg q12.5>, d31, d19
│ │  	vmull.u<illegal width 8>	<illegal reg q11.5>, d14, d0[7]
│ │  	movs	r0, r0
│ │ -	mov	r7, r2
│ │ -	vmlsl.u<illegal width 8>	q8, d15, d1[4]
│ │ -	vsli.64	d25, d8, #15
│ │ -	vqshlu.s64	q8, <illegal reg q2.5>, #14
│ │ -			@ <UNDEFINED> instruction: 0xffcfd9d6
│ │ +	mov	r6, r7
│ │ +	vrsubhn.i16	d16, <illegal reg q15.5>, q4
│ │ +	vsli.64	d25, d31, #15
│ │ +	vqshlu.s64	q8, q14, #14
│ │ +			@ <UNDEFINED> instruction: 0xffcfd9fd
│ │  	vaddl.u8	q8, d14, d0
│ │  	b.n	3b06d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x243e54>
│ │  	movs	r1, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	movs	r0, r0
│ │  	b.n	3b0782 <uniffi_pbcli_checksum_method_api_base@@Base+0x243efe>
│ │ @@ -1069578,23 +1069578,23 @@
│ │  			@ <UNDEFINED> instruction: 0xffc1eaff
│ │  	ands	r0, r0
│ │  	b.n	3b08f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x24406e>
│ │  	movs	r6, r0
│ │  	b.n	3b04f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x243c72>
│ │  	adds	r0, #39	@ 0x27
│ │  			@ <UNDEFINED> instruction: 0xebfbffc4
│ │ -			@ <UNDEFINED> instruction: 0xeaff045d
│ │ -	vrsra.u64	d25, d4, #49
│ │ +			@ <UNDEFINED> instruction: 0xeaff0484
│ │ +	vrsra.u64	d25, d27, #49
│ │  			@ <UNDEFINED> instruction: 0xffce7904
│ │  	movs	r0, r0
│ │  	bge.n	3b0122 <uniffi_pbcli_checksum_method_api_base@@Base+0x24389e>
│ │ -	vsri.8	d16, d21, #3
│ │ -			@ <UNDEFINED> instruction: 0xffcf936c
│ │ -	vabal.u8	q8, d14, d25
│ │ -			@ <UNDEFINED> instruction: 0xffcfeef2
│ │ +	vsri.8	q8, q6, #3
│ │ +	vrsra.u64	d25, d3, #49
│ │ +	vsli.8	q8, q0, #6
│ │ +			@ <UNDEFINED> instruction: 0xffcfef19
│ │  			@ <UNDEFINED> instruction: 0xffce0f11
│ │  	b.n	3b04c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x243c3c>
│ │  	asrs	r7, r0, #2
│ │  	b.n	3b0608 <uniffi_pbcli_checksum_method_api_base@@Base+0x243d84>
│ │  	asrs	r1, r0, #32
│ │  	asrs	r0, r0, #12
│ │  	lsls	r0, r4, #10
│ │ @@ -1069851,28 +1069851,28 @@
│ │  	b.n	3b0a12 <uniffi_pbcli_checksum_method_api_base@@Base+0x24418e>
│ │  	asrs	r4, r1, #32
│ │  	b.n	3b0a96 <uniffi_pbcli_checksum_method_api_base@@Base+0x244212>
│ │  			@ <UNDEFINED> instruction: 0xff91eaff
│ │  	ands	r0, r0
│ │  	b.n	3b0b5e <uniffi_pbcli_checksum_method_api_base@@Base+0x2442da>
│ │  			@ <UNDEFINED> instruction: 0xffeeeaff
│ │ -	lsls	r5, r2, #7
│ │ -	vaddw.u8	<illegal reg q12.5>, <illegal reg q7.5>, d12
│ │ +	lsls	r4, r7, #7
│ │ +	vsra.u8	d25, d19, #1
│ │  	vsubw.u8	<illegal reg q13.5>, q15, d10
│ │  	vaddw.u8	<illegal reg q14.5>, <illegal reg q6.5>, d16
│ │  	movs	r2, r2
│ │  	beq.n	3b04ec <uniffi_pbcli_checksum_method_api_base@@Base+0x243c68>
│ │  	movs	r2, r2
│ │  	str	r2, [sp, #472]	@ 0x1d8
│ │  			@ <UNDEFINED> instruction: 0xffcccff4
│ │  	movs	r2, r2
│ │ -	str	r1, [r6, #96]	@ 0x60
│ │ +	str	r0, [r3, #100]	@ 0x64
│ │  	vmla.i<illegal width 8>	<illegal reg q14.5>, q15, d0[3]
│ │  	movs	r2, r2
│ │ -	lsls	r1, r1, #14
│ │ +	lsls	r0, r6, #14
│ │  	vmlal.u<illegal width 8>	q9, d15, d1[1]
│ │  	vaddl.u8	q8, d14, d1
│ │  	b.n	3b0b92 <uniffi_pbcli_checksum_method_api_base@@Base+0x24430e>
│ │  	movs	r0, r0
│ │  	b.n	3b0af8 <uniffi_pbcli_checksum_method_api_base@@Base+0x244274>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	movs	r1, r0
│ │ @@ -1070082,26 +1070082,26 @@
│ │  			@ <UNDEFINED> instruction: 0xffb2eaff
│ │  	ands	r0, r0
│ │  	b.n	3b0d62 <uniffi_pbcli_checksum_method_api_base@@Base+0x2444de>
│ │  	movs	r7, r0
│ │  	b.n	3b0966 <uniffi_pbcli_checksum_method_api_base@@Base+0x2440e2>
│ │  	cmp	r7, #11
│ │  			@ <UNDEFINED> instruction: 0xebfbffb2
│ │ -			@ <UNDEFINED> instruction: 0xeaffffd1
│ │ -			@ <UNDEFINED> instruction: 0xffce8f08
│ │ +			@ <UNDEFINED> instruction: 0xeafffff8
│ │ +			@ <UNDEFINED> instruction: 0xffce8f2f
│ │  			@ <UNDEFINED> instruction: 0xffce09a9
│ │  	vmull.p8	q14, d30, d16
│ │  	movs	r2, r2
│ │  	ldmia	r5, {r3, r4, r5, r6, r7}
│ │  	movs	r2, r2
│ │  	subs	r1, #195	@ 0xc3
│ │  			@ <UNDEFINED> instruction: 0xffcece74
│ │  	movs	r2, r2
│ │ -	lsls	r1, r0, #4
│ │ -	vmla.i<illegal width 8>	<illegal reg q12.5>, <illegal reg q7.5>, d3[1]
│ │ +	lsls	r0, r5, #4
│ │ +	vmla.i<illegal width 8>	<illegal reg q12.5>, <illegal reg q7.5>, d2[7]
│ │  	vaddl.u8	q8, d14, d1
│ │  	b.n	3b0d96 <uniffi_pbcli_checksum_method_api_base@@Base+0x244512>
│ │  	movs	r0, r0
│ │  	b.n	3b0cfc <uniffi_pbcli_checksum_method_api_base@@Base+0x244478>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	movs	r1, r0
│ │  	b.n	3b0c84 <uniffi_pbcli_checksum_method_api_base@@Base+0x244400>
│ │ @@ -1070310,25 +1070310,25 @@
│ │  			@ <UNDEFINED> instruction: 0xffb2eaff
│ │  	ands	r0, r0
│ │  	b.n	3b0f66 <uniffi_pbcli_checksum_method_api_base@@Base+0x2446e2>
│ │  	movs	r7, r0
│ │  	b.n	3b0b6a <uniffi_pbcli_checksum_method_api_base@@Base+0x2442e6>
│ │  	cmp	r6, #138	@ 0x8a
│ │  			@ <UNDEFINED> instruction: 0xebfbffb2
│ │ -			@ <UNDEFINED> instruction: 0xeafffdcd
│ │ -			@ <UNDEFINED> instruction: 0xffce8d04
│ │ +			@ <UNDEFINED> instruction: 0xeafffdf4
│ │ +			@ <UNDEFINED> instruction: 0xffce8d2b
│ │  	vaddl.u8	q9, d30, d10
│ │  			@ <UNDEFINED> instruction: 0xffcdcc9c
│ │  	movs	r2, r2
│ │  	ldmia	r3!, {r2, r4, r5, r6, r7}
│ │  	movs	r2, r2
│ │ -	add	r3, pc, #60	@ (adr r3, 3b0884 <uniffi_pbcli_checksum_method_api_base@@Base+0x244000>)
│ │ +	add	r3, pc, #216	@ (adr r3, 3b0920 <uniffi_pbcli_checksum_method_api_base@@Base+0x24409c>)
│ │  			@ <UNDEFINED> instruction: 0xffcecc70
│ │  	movs	r2, r2
│ │ -	cdp2	15, 15, cr15, cr13, cr14, {6}
│ │ +	vpmin.f32	<illegal reg q7.5>, q10, q7
│ │  	add	r6, pc, #1016	@ (adr r6, 3b0c4c <uniffi_pbcli_checksum_method_api_base@@Base+0x2443c8>)
│ │  			@ <UNDEFINED> instruction: 0xffcc0f11
│ │  	b.n	3b0b38 <uniffi_pbcli_checksum_method_api_base@@Base+0x2442b4>
│ │  	lsls	r0, r4, #10
│ │  	b.n	3b0b9e <uniffi_pbcli_checksum_method_api_base@@Base+0x24431a>
│ │  	movs	r1, r0
│ │  	b.n	3b0b62 <uniffi_pbcli_checksum_method_api_base@@Base+0x2442de>
│ │ @@ -1070435,15 +1070435,15 @@
│ │  	b.n	3b0458 <uniffi_pbcli_checksum_method_api_base@@Base+0x243bd4>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b045c <uniffi_pbcli_checksum_method_api_base@@Base+0x243bd8>
│ │  	subs	r2, r7, r4
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b0de0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24455c>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r8, sl, fp, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r4, r5, r8, sl, fp, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffce1f8e
│ │  			@ <UNDEFINED> instruction: 0xffcd6e5c
│ │  	movs	r0, r0
│ │  	subs	r2, r6, #4
│ │  	vraddhn.i16	d23, <illegal reg q6.5>, q8
│ │  	movs	r0, r0
│ │  	ldr	r0, [r7, #112]	@ 0x70
│ │ @@ -1070559,15 +1070559,15 @@
│ │  	b.n	3b056c <uniffi_pbcli_checksum_method_api_base@@Base+0x243ce8>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b0570 <uniffi_pbcli_checksum_method_api_base@@Base+0x243cec>
│ │  	subs	r5, r6, r3
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b0ef4 <uniffi_pbcli_checksum_method_api_base@@Base+0x244670>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r6, r7, r8, r9, fp, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r4, sl, fp, ip, sp, lr, pc}
│ │  	vmull.p8	<illegal reg q8.5>, d30, d20
│ │  	vqrdmulh.s<illegal width 8>	q11, <illegal reg q6.5>, d0[2]
│ │  	movs	r0, r0
│ │  	subs	r6, r3, #0
│ │  	vsli.64	<illegal reg q11.5>, q8, #13
│ │  	movs	r0, r0
│ │  	ldr	r4, [r4, #96]	@ 0x60
│ │ @@ -1070683,16 +1070683,16 @@
│ │  	b.n	3b0680 <uniffi_pbcli_checksum_method_api_base@@Base+0x243dfc>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b0684 <uniffi_pbcli_checksum_method_api_base@@Base+0x243e00>
│ │  	subs	r0, r6, r2
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b1008 <uniffi_pbcli_checksum_method_api_base@@Base+0x244784>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r5, r6, r7, r9, fp, ip, sp, lr, pc}
│ │ -	vmlal.u<illegal width 8>	<illegal reg q8.5>, d30, d1[7]
│ │ +	ldmia.w	sp!, {r3, r8, r9, fp, ip, sp, lr, pc}
│ │ +	vrsra.u8	d17, d4, #2
│ │  			@ <UNDEFINED> instruction: 0xffcf6c34
│ │  	movs	r0, r0
│ │  	adds	r2, r1, #4
│ │  	vabal.u8	<illegal reg q11.5>, d29, d16
│ │  	movs	r0, r0
│ │  	ldr	r0, [r2, #80]	@ 0x50
│ │  	movs	r0, r0
│ │ @@ -1070807,16 +1070807,16 @@
│ │  	b.n	3b0794 <uniffi_pbcli_checksum_method_api_base@@Base+0x243f10>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b0798 <uniffi_pbcli_checksum_method_api_base@@Base+0x243f14>
│ │  	subs	r3, r5, r1
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b111c <uniffi_pbcli_checksum_method_api_base@@Base+0x244898>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r6, r7, r8, fp, ip, sp, lr, pc}
│ │ -	vqshrn.u16	d24, <illegal reg q12.5>, #2
│ │ +	ldmia.w	sp!, {r2, r4, r5, r6, r7, r8, fp, ip, sp, lr, pc}
│ │ +	vmul.f<illegal width 8>	q12, q7, d0[4]
│ │  			@ <UNDEFINED> instruction: 0xffce6b20
│ │  	movs	r0, r0
│ │  	subs	r6, r6, r7
│ │  	vrsubhn.i16	d23, <illegal reg q6.5>, q0
│ │  	movs	r0, r0
│ │  	ldr	r4, [r7, #60]	@ 0x3c
│ │  	movs	r0, r0
│ │ @@ -1070934,19 +1070934,19 @@
│ │  	b.n	3b08b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24402c>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b08b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x244030>
│ │  	subs	r4, r4, r0
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b1238 <uniffi_pbcli_checksum_method_api_base@@Base+0x2449b4>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r4, r5, r7, fp, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r3, r4, r6, r7, fp, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcebf80
│ │  	vmlsl.u8	q11, d13, d4
│ │  	movs	r0, r0
│ │ -	push	{r2, r3, r7, lr}
│ │ +	push	{r0, r1, r4, r5, r7, lr}
│ │  	vqshlu.s8	<illegal reg q11.5>, q4, #6
│ │  	movs	r0, r0
│ │  	ldr	r0, [r4, #44]	@ 0x2c
│ │  	movs	r0, r0
│ │  	stmia	r7!, {r2, r4}
│ │  	movs	r2, r2
│ │  	movs	r0, r0
│ │ @@ -1071061,19 +1071061,19 @@
│ │  	b.n	3b09cc <uniffi_pbcli_checksum_method_api_base@@Base+0x244148>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b09d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24414c>
│ │  	adds	r5, r3, r7
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b1354 <uniffi_pbcli_checksum_method_api_base@@Base+0x244ad0>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r4, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffcecabc
│ │ +	ldmia.w	sp!, {r2, r3, r4, r5, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ +	vmull.u<illegal width 8>	q14, d30, d3[4]
│ │  	vmul.i<illegal width 8>	q11, q15, d0[6]
│ │  	movs	r0, r0
│ │ -	push	{r4, r5, r6}
│ │ +	push	{r0, r1, r2, r4, r7}
│ │  	vqshlu.s64	<illegal reg q11.5>, q2, #14
│ │  	movs	r0, r0
│ │  	ldr	r4, [r0, #28]
│ │  	movs	r0, r0
│ │  	stmia	r5!, {r3, r4, r5, r6, r7}
│ │  	movs	r2, r2
│ │  	lsrs	r1, r2, #28
│ │ @@ -1071185,19 +1071185,19 @@
│ │  	b.n	3b0ae0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24425c>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b0ae4 <uniffi_pbcli_checksum_method_api_base@@Base+0x244260>
│ │  	adds	r0, r3, r6
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b1468 <uniffi_pbcli_checksum_method_api_base@@Base+0x244be4>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r7, r9, sl, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r3, r5, r7, r9, sl, ip, sp, lr, pc}
│ │  	vrsra.u8	d21, d7, #2
│ │  	vqshl.u64	q11, q2, #15
│ │  	movs	r0, r0
│ │ -	bl	22bf80 <uniffi_pbcli_checksum_method_api_base@@Base+0xbf6fc>
│ │ +	bl	252f80 <uniffi_pbcli_checksum_method_api_base@@Base+0xe66fc>
│ │  	ldr	r0, [r3, #88]	@ 0x58
│ │  	movs	r0, r0
│ │  	ldr	r0, [r6, #8]
│ │  	movs	r0, r0
│ │  	stmia	r4!, {r5, r6, r7}
│ │  	movs	r2, r2
│ │  	lsrs	r1, r2, #28
│ │ @@ -1071309,19 +1071309,19 @@
│ │  	b.n	3b0bf4 <uniffi_pbcli_checksum_method_api_base@@Base+0x244370>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b0bf8 <uniffi_pbcli_checksum_method_api_base@@Base+0x244374>
│ │  	adds	r3, r2, r5
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b157c <uniffi_pbcli_checksum_method_api_base@@Base+0x244cf8>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r5, r6, r8, sl, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r4, r7, r8, sl, ip, sp, lr, pc}
│ │  	vqrdmlah.s<illegal width 8>	<illegal reg q10.5>, q15, d0[3]
│ │  	vmlsl.u<illegal width 8>	q11, d29, d0[0]
│ │  	movs	r0, r0
│ │ -	bl	118094 <UNIFFI_META_PBCLI_METHOD_API_BASE@@Base+0xae87a>
│ │ +	bl	13f094 <UNIFFI_META_PBCLI_METHOD_API_BASE@@Base+0xd587a>
│ │  	ldr	r0, [r5, #116]	@ 0x74
│ │  	movs	r0, r0
│ │  	str	r4, [r3, #120]	@ 0x78
│ │  	movs	r0, r0
│ │  	stmia	r3!, {r2, r3, r6, r7}
│ │  	movs	r2, r2
│ │  	lsrs	r1, r2, #28
│ │ @@ -1071433,19 +1071433,19 @@
│ │  	b.n	3b0d08 <uniffi_pbcli_checksum_method_api_base@@Base+0x244484>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b0d0c <uniffi_pbcli_checksum_method_api_base@@Base+0x244488>
│ │  	adds	r6, r1, r4
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b1690 <uniffi_pbcli_checksum_method_api_base@@Base+0x244e0c>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r6, sl, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r7, sl, ip, sp, lr, pc}
│ │  	vqshl.u8	d17, d18, #6
│ │  	vabal.u8	q11, d29, d28
│ │  	movs	r0, r0
│ │ -	bl	41a8 <UNIFFI_META_PBCLI_RECORD_OPTS@@Base-0x61e58>
│ │ +	bl	2b1a8 <UNIFFI_META_PBCLI_RECORD_OPTS@@Base-0x3ae58>
│ │  	ldr	r0, [r3, #112]	@ 0x70
│ │  	movs	r0, r0
│ │  	str	r0, [r1, #104]	@ 0x68
│ │  	movs	r0, r0
│ │  	stmia	r2!, {r3, r4, r5, r7}
│ │  	movs	r2, r2
│ │  	lsrs	r1, r2, #28
│ │ @@ -1071557,19 +1071557,19 @@
│ │  	b.n	3b0e1c <uniffi_pbcli_checksum_method_api_base@@Base+0x244598>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b0e20 <uniffi_pbcli_checksum_method_api_base@@Base+0x24459c>
│ │  	adds	r1, r1, r3
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b17a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x244f20>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r6, r8, r9, ip, sp, lr, pc}
│ │ -	vsubw.u8	<illegal reg q15.5>, q15, d14
│ │ +	ldmia.w	sp!, {r2, r3, r5, r6, r8, r9, ip, sp, lr, pc}
│ │ +	vrsra.u64	d31, d21, #50
│ │  	vsri.64	d22, d8, #50
│ │  	movs	r0, r0
│ │ -	bl	6f02bc <uniffi_pbcli_checksum_method_api_base@@Base+0x583a38>
│ │ +	bl	7172bc <uniffi_pbcli_checksum_method_api_base@@Base+0x5aaa38>
│ │  	ldr	r0, [r7, #116]	@ 0x74
│ │  	movs	r0, r0
│ │  	str	r4, [r6, #84]	@ 0x54
│ │  	movs	r0, r0
│ │  	stmia	r1!, {r2, r5, r7}
│ │  	movs	r2, r2
│ │  	movs	r0, r0
│ │ @@ -1071684,16 +1071684,16 @@
│ │  	b.n	3b0f38 <uniffi_pbcli_checksum_method_api_base@@Base+0x2446b4>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b0f3c <uniffi_pbcli_checksum_method_api_base@@Base+0x2446b8>
│ │  	adds	r2, r0, r2
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b18c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24503c>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r5, r9, ip, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffce376e
│ │ +	ldmia.w	sp!, {r4, r6, r9, ip, sp, lr, pc}
│ │ +	vqshl.u64	d19, d5, #14
│ │  	vrsra.u8	q11, q14, #1
│ │  	movs	r0, r0
│ │  	strb	r1, [r7, #14]
│ │  			@ <UNDEFINED> instruction: 0xffcd6fd0
│ │  	movs	r0, r0
│ │  	str	r0, [r3, #68]	@ 0x44
│ │  	movs	r0, r0
│ │ @@ -1071811,16 +1071811,16 @@
│ │  	b.n	3b1054 <uniffi_pbcli_checksum_method_api_base@@Base+0x2447d0>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b1058 <uniffi_pbcli_checksum_method_api_base@@Base+0x2447d4>
│ │  	adds	r3, r7, r0
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b19dc <uniffi_pbcli_checksum_method_api_base@@Base+0x245158>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r8, ip, sp, lr, pc}
│ │ -	vmls.f<illegal width 8>	<illegal reg q12.5>, q15, d1[4]
│ │ +	ldmia.w	sp!, {r2, r4, r5, r8, ip, sp, lr, pc}
│ │ +	vrsubhn.i16	d25, q7, q4
│ │  	vmlal.u<illegal width 8>	q11, d14, d0[4]
│ │  	movs	r0, r0
│ │  	strb	r5, [r3, #10]
│ │  	vmla.i<illegal width 8>	<illegal reg q11.5>, <illegal reg q6.5>, d0[3]
│ │  	movs	r0, r0
│ │  	str	r4, [r7, #48]	@ 0x30
│ │  	movs	r0, r0
│ │ @@ -1071940,16 +1071940,16 @@
│ │  	b.n	3b1170 <uniffi_pbcli_checksum_method_api_base@@Base+0x2448ec>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b1174 <uniffi_pbcli_checksum_method_api_base@@Base+0x2448f0>
│ │  	asrs	r4, r6, #31
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b1af8 <uniffi_pbcli_checksum_method_api_base@@Base+0x245274>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r6, r7, r8, r9, sl, fp, sp, lr, pc}
│ │ -	vsubw.u8	<illegal reg q10.5>, q7, d28
│ │ +	ldmia.w	sp!, {r5, ip, sp, lr, pc}
│ │ +	vrsra.u8	<illegal reg q10.5>, <illegal reg q1.5>, #2
│ │  	vabdl.u8	q11, d14, d16
│ │  	movs	r0, r0
│ │  	str	r4, [r6, #60]	@ 0x3c
│ │  	movs	r0, r0
│ │  	add	r0, pc, #728	@ (adr r0, 3b1950 <uniffi_pbcli_checksum_method_api_base@@Base+0x2450cc>)
│ │  	vaddl.u8	<illegal reg q11.5>, d13, d12
│ │  	movs	r0, r0
│ │ @@ -1072069,16 +1072069,16 @@
│ │  	b.n	3b128c <uniffi_pbcli_checksum_method_api_base@@Base+0x244a08>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b1290 <uniffi_pbcli_checksum_method_api_base@@Base+0x244a0c>
│ │  	asrs	r5, r5, #30
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b1c14 <uniffi_pbcli_checksum_method_api_base@@Base+0x245390>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r6, r7, r9, sl, fp, sp, lr, pc}
│ │ -	vmls.i<illegal width 8>	<illegal reg q9.5>, q7, d0[3]
│ │ +	ldmia.w	sp!, {r2, r8, r9, sl, fp, sp, lr, pc}
│ │ +	vsri.8	<illegal reg q9.5>, <illegal reg q9.5>, #2
│ │  	vmul.i<illegal width 8>	q11, <illegal reg q15.5>, d0[6]
│ │  	movs	r0, r0
│ │  	str	r0, [r3, #44]	@ 0x2c
│ │  	movs	r0, r0
│ │  	ldr	r7, [sp, #616]	@ 0x268
│ │  			@ <UNDEFINED> instruction: 0xffcd6ef0
│ │  	movs	r0, r0
│ │ @@ -1072198,15 +1072198,15 @@
│ │  	b.n	3b13a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x244b24>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b13ac <uniffi_pbcli_checksum_method_api_base@@Base+0x244b28>
│ │  	asrs	r6, r4, #29
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b1d30 <uniffi_pbcli_checksum_method_api_base@@Base+0x2454ac>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r6, r7, r8, sl, fp, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r3, r5, r6, r7, r8, sl, fp, sp, lr, pc}
│ │  	vshr.u8	d30, d9, #2
│ │  			@ <UNDEFINED> instruction: 0xffcd6890
│ │  	movs	r0, r0
│ │  	str	r4, [r7, #24]
│ │  	movs	r0, r0
│ │  	ldr	r6, [sp, #504]	@ 0x1f8
│ │  			@ <UNDEFINED> instruction: 0xffcd6dd4
│ │ @@ -1072327,16 +1072327,16 @@
│ │  	b.n	3b14c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x244c40>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b14c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x244c44>
│ │  	asrs	r7, r3, #28
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b1e4c <uniffi_pbcli_checksum_method_api_base@@Base+0x2455c8>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r5, r7, sl, fp, sp, lr, pc}
│ │ -	vaddw.u8	<illegal reg q12.5>, q15, d19
│ │ +	ldmia.w	sp!, {r2, r3, r6, r7, sl, fp, sp, lr, pc}
│ │ +	vmla.f<illegal width 8>	<illegal reg q12.5>, q15, d2[2]
│ │  	vmul.i<illegal width 8>	q11, q15, d0[6]
│ │  	movs	r0, r0
│ │  	str	r0, [r4, #8]
│ │  	movs	r0, r0
│ │  	ldr	r5, [sp, #392]	@ 0x188
│ │  			@ <UNDEFINED> instruction: 0xffcd6cb8
│ │  	movs	r0, r0
│ │ @@ -1072459,21 +1072459,21 @@
│ │  	b.n	3b15e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x244d64>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b15ec <uniffi_pbcli_checksum_method_api_base@@Base+0x244d68>
│ │  	asrs	r6, r2, #27
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b1f70 <uniffi_pbcli_checksum_method_api_base@@Base+0x2456ec>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r7, r8, r9, fp, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r3, r5, r7, r8, r9, fp, sp, lr, pc}
│ │  	vabal.u8	<illegal reg q15.5>, d14, d16
│ │  	vqshrn.u16	d22, q12, #3
│ │  	movs	r0, r0
│ │  	ldrsh	r4, [r7, r5]
│ │  	movs	r0, r0
│ │ -	str	r7, [r3, #68]	@ 0x44
│ │ +	str	r6, [r0, #72]	@ 0x48
│ │  			@ <UNDEFINED> instruction: 0xffce6b94
│ │  	movs	r0, r0
│ │  	ldr	r0, [r7, #80]	@ 0x50
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │  	b.n	3b21a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24591c>
│ │  	movs	r1, r0
│ │ @@ -1072591,21 +1072591,21 @@
│ │  	b.n	3b170c <uniffi_pbcli_checksum_method_api_base@@Base+0x244e88>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b1710 <uniffi_pbcli_checksum_method_api_base@@Base+0x244e8c>
│ │  	asrs	r5, r1, #26
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b2094 <uniffi_pbcli_checksum_method_api_base@@Base+0x245810>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r6, r9, fp, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffce8f7b
│ │ +	ldmia.w	sp!, {r2, r7, r9, fp, sp, lr, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffce8fa2
│ │  			@ <UNDEFINED> instruction: 0xffce69ac
│ │  	movs	r0, r0
│ │  	ldrsh	r0, [r3, r1]
│ │  	movs	r0, r0
│ │ -	str	r3, [r7, #48]	@ 0x30
│ │ +	str	r2, [r4, #52]	@ 0x34
│ │  			@ <UNDEFINED> instruction: 0xffce6a70
│ │  	movs	r0, r0
│ │  	ldr	r4, [r2, #64]	@ 0x40
│ │  	movs	r0, r0
│ │  	lsrs	r1, r2, #28
│ │  	b.n	3b1f00 <uniffi_pbcli_checksum_method_api_base@@Base+0x24567c>
│ │  	lsls	r0, r4, #10
│ │ @@ -1072720,16 +1072720,16 @@
│ │  	b.n	3b1828 <uniffi_pbcli_checksum_method_api_base@@Base+0x244fa4>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b182c <uniffi_pbcli_checksum_method_api_base@@Base+0x244fa8>
│ │  	asrs	r6, r0, #25
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b21b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24592c>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r6, r8, fp, sp, lr, pc}
│ │ -	vmull.p8	q12, d30, d5
│ │ +	ldmia.w	sp!, {r3, r5, r6, r8, fp, sp, lr, pc}
│ │ +	vmull.p8	q12, d30, d28
│ │  	vmla.i<illegal width 8>	q11, q7, d0[6]
│ │  	movs	r0, r0
│ │  	ldrb	r4, [r7, r4]
│ │  	movs	r0, r0
│ │  	ldr	r2, [sp, #52]	@ 0x34
│ │  	vqrshrn.u16	d22, q2, #3
│ │  	movs	r0, r0
│ │ @@ -1072849,16 +1072849,16 @@
│ │  	b.n	3b1944 <uniffi_pbcli_checksum_method_api_base@@Base+0x2450c0>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b1948 <uniffi_pbcli_checksum_method_api_base@@Base+0x2450c4>
│ │  	asrs	r7, r7, #23
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b22cc <uniffi_pbcli_checksum_method_api_base@@Base+0x245a48>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r5, fp, sp, lr, pc}
│ │ -	vsubl.u8	<illegal reg q14.5>, d14, d21
│ │ +	ldmia.w	sp!, {r2, r3, r6, fp, sp, lr, pc}
│ │ +	vmlal.u<illegal width 8>	<illegal reg q14.5>, d14, d0[3]
│ │  	vrshr.u8	d22, d16, #2
│ │  	movs	r0, r0
│ │  	ldrb	r0, [r4, r0]
│ │  	movs	r0, r0
│ │  	ldr	r0, [sp, #964]	@ 0x3c4
│ │  	vqshrun.s16	d22, q12, #3
│ │  	movs	r0, r0
│ │ @@ -1072978,15 +1072978,15 @@
│ │  	b.n	3b1a60 <uniffi_pbcli_checksum_method_api_base@@Base+0x2451dc>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b1a64 <uniffi_pbcli_checksum_method_api_base@@Base+0x2451e0>
│ │  	asrs	r0, r7, #22
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b23e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x245b64>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r8, r9, sl, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r4, r5, r8, r9, sl, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffce8f31
│ │  	vsra.u64	q11, q4, #52
│ │  	movs	r0, r0
│ │  	ldrh	r4, [r0, r4]
│ │  	movs	r0, r0
│ │  	str	r7, [sp, #852]	@ 0x354
│ │  	vqshl.u8	d22, d12, #5
│ │ @@ -1073107,15 +1073107,15 @@
│ │  	b.n	3b1b7c <uniffi_pbcli_checksum_method_api_base@@Base+0x2452f8>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b1b80 <uniffi_pbcli_checksum_method_api_base@@Base+0x2452fc>
│ │  	asrs	r1, r6, #21
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b2504 <uniffi_pbcli_checksum_method_api_base@@Base+0x245c80>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r5, r6, r7, r8, sl, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r4, r9, sl, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffce4f79
│ │  	vrshr.u8	d22, d16, #3
│ │  	movs	r0, r0
│ │  	ldr	r0, [r5, r7]
│ │  	movs	r0, r0
│ │  	str	r6, [sp, #740]	@ 0x2e4
│ │  	vrsubhn.i16	d22, <illegal reg q6.5>, q0
│ │ @@ -1073239,15 +1073239,15 @@
│ │  	b.n	3b1ca0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24541c>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b1ca4 <uniffi_pbcli_checksum_method_api_base@@Base+0x245420>
│ │  	asrs	r0, r5, #20
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b2628 <uniffi_pbcli_checksum_method_api_base@@Base+0x245da4>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r6, r7, sl, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r4, r5, r6, r7, sl, sp, lr, pc}
│ │  	vqshl.u8	q13, q8, #6
│ │  	vsubl.u8	q11, d28, d0
│ │  	movs	r0, r0
│ │  	ldr	r4, [r0, r3]
│ │  	movs	r0, r0
│ │  	bhi.n	3b213c <uniffi_pbcli_checksum_method_api_base@@Base+0x2458b8>
│ │  	vsri.64	q11, q6, #52
│ │ @@ -1073371,15 +1073371,15 @@
│ │  	b.n	3b1dc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x245540>
│ │  	strb	r0, [r3, #0]
│ │  	b.n	3b1dc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x245544>
│ │  	asrs	r7, r3, #19
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b274c <uniffi_pbcli_checksum_method_api_base@@Base+0x245ec8>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r5, r7, r8, r9, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r6, r7, r8, r9, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffce4d52
│ │  	vrshr.u64	q11, q10, #51
│ │  	movs	r0, r0
│ │  	ldrsb	r0, [r4, r6]
│ │  	movs	r0, r0
│ │  	bvc.n	3b2218 <uniffi_pbcli_checksum_method_api_base@@Base+0x245994>
│ │  	vrsra.u64	d22, d24, #52
│ │ @@ -1073495,15 +1073495,15 @@
│ │  	b.n	3b1ed8 <uniffi_pbcli_checksum_method_api_base@@Base+0x245654>
│ │  	str	r0, [r3, #0]
│ │  	b.n	3b1edc <uniffi_pbcli_checksum_method_api_base@@Base+0x245658>
│ │  	asrs	r2, r3, #18
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b2860 <uniffi_pbcli_checksum_method_api_base@@Base+0x245fdc>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r7, r9, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r4, r5, r7, r9, sp, lr, pc}
│ │  	vsubw.u8	<illegal reg q12.5>, q15, d30
│ │  			@ <UNDEFINED> instruction: 0xffcd59ac
│ │  	movs	r0, r0
│ │  	str	r3, [sp, #232]	@ 0xe8
│ │  	vmlsl.u<illegal width 8>	<illegal reg q10.5>, d29, d0[6]
│ │  	movs	r0, r0
│ │  	str	r0, [r7, #76]	@ 0x4c
│ │ @@ -1073617,16 +1073617,16 @@
│ │  	b.n	3b1fe8 <uniffi_pbcli_checksum_method_api_base@@Base+0x245764>
│ │  	str	r0, [r3, #0]
│ │  	b.n	3b1fec <uniffi_pbcli_checksum_method_api_base@@Base+0x245768>
│ │  	asrs	r6, r2, #17
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b2970 <uniffi_pbcli_checksum_method_api_base@@Base+0x2460ec>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r6, r8, sp, lr, pc}
│ │ -	vmls.i<illegal width 8>	q10, q15, d0[6]
│ │ +	ldmia.w	sp!, {r5, r7, r8, sp, lr, pc}
│ │ +	vabal.u8	q10, d14, d15
│ │  			@ <UNDEFINED> instruction: 0xffce5b80
│ │  	movs	r0, r0
│ │  	str	r2, [sp, #168]	@ 0xa8
│ │  	vsli.64	<illegal reg q10.5>, q4, #13
│ │  	movs	r0, r0
│ │  	str	r0, [r5, #60]	@ 0x3c
│ │  	movs	r0, r0
│ │ @@ -1073739,16 +1073739,16 @@
│ │  	b.n	3b20f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x245874>
│ │  	str	r0, [r3, #0]
│ │  	b.n	3b20fc <uniffi_pbcli_checksum_method_api_base@@Base+0x245878>
│ │  	asrs	r2, r2, #16
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b2a80 <uniffi_pbcli_checksum_method_api_base@@Base+0x2461fc>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r5, r6, sp, lr, pc}
│ │ -	vsli.64	q12, <illegal reg q3.5>, #14
│ │ +	ldmia.w	sp!, {r4, r7, sp, lr, pc}
│ │ +	vsli.64	q12, q15, #14
│ │  			@ <UNDEFINED> instruction: 0xffce5b34
│ │  	movs	r0, r0
│ │  	str	r1, [sp, #104]	@ 0x68
│ │  	vmls.i<illegal width 8>	<illegal reg q10.5>, <illegal reg q14.5>, d0[2]
│ │  	movs	r0, r0
│ │  	str	r0, [r3, #44]	@ 0x2c
│ │  	movs	r0, r0
│ │ @@ -1073861,15 +1073861,15 @@
│ │  	b.n	3b2208 <uniffi_pbcli_checksum_method_api_base@@Base+0x245984>
│ │  	str	r0, [r3, #0]
│ │  	b.n	3b220c <uniffi_pbcli_checksum_method_api_base@@Base+0x245988>
│ │  	asrs	r6, r1, #15
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b2b90 <uniffi_pbcli_checksum_method_api_base@@Base+0x24630c>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r6, r8, r9, sl, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r7, r8, r9, sl, fp, ip, lr, pc}
│ │  	vmul.i<illegal width 8>	<illegal reg q8.5>, q15, d2[6]
│ │  			@ <UNDEFINED> instruction: 0xffcd5b98
│ │  	movs	r0, r0
│ │  	str	r0, [sp, #40]	@ 0x28
│ │  	vrsra.u64	d21, d24, #51
│ │  	movs	r0, r0
│ │  	str	r0, [r1, #28]
│ │ @@ -1073986,15 +1073986,15 @@
│ │  	b.n	3b2320 <uniffi_pbcli_checksum_method_api_base@@Base+0x245a9c>
│ │  	str	r0, [r3, #0]
│ │  	b.n	3b2324 <uniffi_pbcli_checksum_method_api_base@@Base+0x245aa0>
│ │  	asrs	r0, r1, #14
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b2ca8 <uniffi_pbcli_checksum_method_api_base@@Base+0x246424>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r6, r9, sl, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r3, r5, r6, r9, sl, fp, ip, lr, pc}
│ │  	vshr.u64	d29, d25, #50
│ │  			@ <UNDEFINED> instruction: 0xffcd5bf4
│ │  	movs	r0, r0
│ │  	ldr	r6, [r1, #100]	@ 0x64
│ │  	vsubl.u8	<illegal reg q10.5>, d28, d16
│ │  	movs	r0, r0
│ │  	str	r4, [r4, #20]
│ │ @@ -1074111,15 +1074111,15 @@
│ │  	b.n	3b2438 <uniffi_pbcli_checksum_method_api_base@@Base+0x245bb4>
│ │  	str	r0, [r3, #0]
│ │  	b.n	3b243c <uniffi_pbcli_checksum_method_api_base@@Base+0x245bb8>
│ │  	asrs	r2, r0, #13
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b2dc0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24653c>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r5, r8, sl, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r4, r6, r8, sl, fp, ip, lr, pc}
│ │  	vqshlu.s64	<illegal reg q8.5>, <illegal reg q5.5>, #14
│ │  			@ <UNDEFINED> instruction: 0xffcd5c74
│ │  	movs	r0, r0
│ │  	ldr	r6, [r6, #80]	@ 0x50
│ │  	vaddw.u8	<illegal reg q10.5>, q14, d8
│ │  	movs	r0, r0
│ │  	str	r4, [r1, #4]
│ │ @@ -1074233,15 +1074233,15 @@
│ │  	b.n	3b2548 <uniffi_pbcli_checksum_method_api_base@@Base+0x245cc4>
│ │  	str	r0, [r3, #0]
│ │  	b.n	3b254c <uniffi_pbcli_checksum_method_api_base@@Base+0x245cc8>
│ │  	asrs	r6, r7, #11
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b2ed0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24664c>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r4, sl, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r6, sl, fp, ip, lr, pc}
│ │  	vsli.64	<illegal reg q11.5>, q6, #14
│ │  	vrsra.u8	d21, d28, #3
│ │  	movs	r0, r0
│ │  	b.n	3b251e <uniffi_pbcli_checksum_method_api_base@@Base+0x245c9a>
│ │  	vaddw.u8	<illegal reg q10.5>, <illegal reg q14.5>, d24
│ │  	movs	r0, r0
│ │  	ldrsh	r0, [r6, r7]
│ │ @@ -1074355,15 +1074355,15 @@
│ │  	b.n	3b2658 <uniffi_pbcli_checksum_method_api_base@@Base+0x245dd4>
│ │  	str	r0, [r3, #0]
│ │  	b.n	3b265c <uniffi_pbcli_checksum_method_api_base@@Base+0x245dd8>
│ │  	asrs	r2, r7, #10
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b2fe0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24675c>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r8, r9, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r4, r5, r8, r9, fp, ip, lr, pc}
│ │  	vmls.i<illegal width 8>	q15, q15, d2[3]
│ │  	vsli.8	d21, d0, #5
│ │  	movs	r0, r0
│ │  	b.n	3b240e <uniffi_pbcli_checksum_method_api_base@@Base+0x245b8a>
│ │  	vshr.u64	d21, d8, #51
│ │  	movs	r0, r0
│ │  	ldrsh	r0, [r4, r3]
│ │ @@ -1074477,16 +1074477,16 @@
│ │  	b.n	3b2768 <uniffi_pbcli_checksum_method_api_base@@Base+0x245ee4>
│ │  	str	r0, [r3, #0]
│ │  	b.n	3b276c <uniffi_pbcli_checksum_method_api_base@@Base+0x245ee8>
│ │  	asrs	r6, r6, #9
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b30f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24686c>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r6, r7, r8, fp, ip, lr, pc}
│ │ -	vsubw.u8	<illegal reg q10.5>, q7, d25
│ │ +	ldmia.w	sp!, {r5, r9, fp, ip, lr, pc}
│ │ +	vrsra.u8	<illegal reg q10.5>, q0, #2
│ │  	vmls.i<illegal width 8>	<illegal reg q10.5>, q15, d0[1]
│ │  	movs	r0, r0
│ │  	b.n	3b32fe <uniffi_pbcli_checksum_method_api_base@@Base+0x246a7a>
│ │  			@ <UNDEFINED> instruction: 0xffcd4f88
│ │  	movs	r0, r0
│ │  	ldrb	r0, [r2, r7]
│ │  	movs	r0, r0
│ │ @@ -1074599,15 +1074599,15 @@
│ │  	b.n	3b2878 <uniffi_pbcli_checksum_method_api_base@@Base+0x245ff4>
│ │  	str	r0, [r3, #0]
│ │  	b.n	3b287c <uniffi_pbcli_checksum_method_api_base@@Base+0x245ff8>
│ │  	asrs	r2, r6, #8
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b3200 <uniffi_pbcli_checksum_method_api_base@@Base+0x24697c>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r5, r6, r7, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r4, r8, fp, ip, lr, pc}
│ │  	vrsra.u64	<illegal reg q13.5>, q6, #50
│ │  	vabal.u8	<illegal reg q10.5>, d12, d24
│ │  	movs	r0, r0
│ │  	b.n	3b31ee <uniffi_pbcli_checksum_method_api_base@@Base+0x24696a>
│ │  			@ <UNDEFINED> instruction: 0xffcd4e78
│ │  	movs	r0, r0
│ │  	ldrb	r0, [r0, r3]
│ │ @@ -1074724,15 +1074724,15 @@
│ │  	b.n	3b2990 <uniffi_pbcli_checksum_method_api_base@@Base+0x24610c>
│ │  	str	r0, [r3, #0]
│ │  	b.n	3b2994 <uniffi_pbcli_checksum_method_api_base@@Base+0x246110>
│ │  	asrs	r4, r5, #7
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b3318 <uniffi_pbcli_checksum_method_api_base@@Base+0x246a94>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r4, r6, r7, r8, r9, sl, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, ip, lr, pc}
│ │  	vaddw.u8	<illegal reg q8.5>, q15, d26
│ │  	vabal.u8	<illegal reg q10.5>, d29, d4
│ │  	movs	r0, r0
│ │  	ldr	r2, [sp, #380]	@ 0x17c
│ │  	vqrdmulh.s<illegal width 8>	q10, q6, d0[4]
│ │  	movs	r0, r0
│ │  	ldrh	r0, [r6, r7]
│ │ @@ -1074849,16 +1074849,16 @@
│ │  	b.n	3b2aa8 <uniffi_pbcli_checksum_method_api_base@@Base+0x246224>
│ │  	str	r0, [r3, #0]
│ │  	b.n	3b2aac <uniffi_pbcli_checksum_method_api_base@@Base+0x246228>
│ │  	asrs	r6, r4, #6
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b3430 <uniffi_pbcli_checksum_method_api_base@@Base+0x246bac>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r7, r9, sl, ip, lr, pc}
│ │ -	vsli.8	d18, d0, #6
│ │ +	ldmia.w	sp!, {r5, r6, r7, r9, sl, ip, lr, pc}
│ │ +	vsli.8	d18, d23, #6
│ │  	vrsubhn.i16	d21, q7, q2
│ │  	movs	r0, r0
│ │  	ldr	r1, [sp, #284]	@ 0x11c
│ │  	vqdmulh.s<illegal width 8>	q10, q6, d0[2]
│ │  	movs	r0, r0
│ │  	ldrh	r0, [r3, r3]
│ │  	movs	r0, r0
│ │ @@ -1074971,15 +1074971,15 @@
│ │  	b.n	3b2bb8 <uniffi_pbcli_checksum_method_api_base@@Base+0x246334>
│ │  	str	r0, [r3, #0]
│ │  	b.n	3b2bbc <uniffi_pbcli_checksum_method_api_base@@Base+0x246338>
│ │  	asrs	r2, r4, #5
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b3540 <uniffi_pbcli_checksum_method_api_base@@Base+0x246cbc>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r5, r7, r8, sl, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r4, r6, r7, r8, sl, ip, lr, pc}
│ │  	vmlsl.u<illegal width 8>	q11, d14, d2[2]
│ │  	vqdmulh.s<illegal width 8>	q10, q14, d0[3]
│ │  	movs	r0, r0
│ │  	bl	392054 <uniffi_pbcli_checksum_method_api_base@@Base+0x2257d0>
│ │  	ldr	r3, [pc, #224]	@ (3b31a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24691c>)
│ │  	movs	r0, r0
│ │  	ldr	r0, [r0, r6]
│ │ @@ -1075093,16 +1075093,16 @@
│ │  	b.n	3b2cc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x246444>
│ │  	str	r0, [r3, #0]
│ │  	b.n	3b2ccc <uniffi_pbcli_checksum_method_api_base@@Base+0x246448>
│ │  	asrs	r6, r3, #4
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b3650 <uniffi_pbcli_checksum_method_api_base@@Base+0x246dcc>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r7, sl, ip, lr, pc}
│ │ -	vsli.8	d29, d8, #6
│ │ +	ldmia.w	sp!, {r6, r7, sl, ip, lr, pc}
│ │ +	vsli.8	d29, d31, #6
│ │  	vmull.p8	q10, d30, d16
│ │  	movs	r0, r0
│ │  	bl	282164 <uniffi_pbcli_checksum_method_api_base@@Base+0x1158e0>
│ │  	ldr	r2, [pc, #160]	@ (3b3270 <uniffi_pbcli_checksum_method_api_base@@Base+0x2469ec>)
│ │  	movs	r0, r0
│ │  	ldr	r0, [r6, r1]
│ │  	movs	r0, r0
│ │ @@ -1075215,16 +1075215,16 @@
│ │  	b.n	3b2dd8 <uniffi_pbcli_checksum_method_api_base@@Base+0x246554>
│ │  	str	r0, [r3, #0]
│ │  	b.n	3b2ddc <uniffi_pbcli_checksum_method_api_base@@Base+0x246558>
│ │  	asrs	r2, r3, #3
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b3760 <uniffi_pbcli_checksum_method_api_base@@Base+0x246edc>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r7, r8, r9, ip, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffcebdb3
│ │ +	ldmia.w	sp!, {r4, r5, r7, r8, r9, ip, lr, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffcebdda
│ │  			@ <UNDEFINED> instruction: 0xffce4e54
│ │  	movs	r0, r0
│ │  	bl	172274 <uniffi_pbcli_checksum_method_api_base@@Base+0x59f0>
│ │  	ldr	r1, [pc, #96]	@ (3b3340 <uniffi_pbcli_checksum_method_api_base@@Base+0x246abc>)
│ │  	movs	r0, r0
│ │  	ldrsb	r0, [r4, r5]
│ │  	movs	r0, r0
│ │ @@ -1075337,15 +1075337,15 @@
│ │  	b.n	3b2ee8 <uniffi_pbcli_checksum_method_api_base@@Base+0x246664>
│ │  	str	r0, [r3, #0]
│ │  	b.n	3b2eec <uniffi_pbcli_checksum_method_api_base@@Base+0x246668>
│ │  	asrs	r6, r2, #2
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b3870 <uniffi_pbcli_checksum_method_api_base@@Base+0x246fec>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r6, r9, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r5, r7, r9, ip, lr, pc}
│ │  	vsra.u8	<illegal reg q15.5>, <illegal reg q2.5>, #2
│ │  			@ <UNDEFINED> instruction: 0xffcd4eb8
│ │  	movs	r0, r0
│ │  	bl	62384 <UNIFFI_META_PBCLI_RECORD_OPTS@@Base-0x3c7c>
│ │  	ldr	r0, [pc, #32]	@ (3b3410 <uniffi_pbcli_checksum_method_api_base@@Base+0x246b8c>)
│ │  	movs	r0, r0
│ │  	ldrsb	r0, [r2, r1]
│ │ @@ -1075462,16 +1075462,16 @@
│ │  	b.n	3b3000 <uniffi_pbcli_checksum_method_api_base@@Base+0x24677c>
│ │  	str	r0, [r3, #0]
│ │  	b.n	3b3004 <uniffi_pbcli_checksum_method_api_base@@Base+0x246780>
│ │  	asrs	r0, r2, #1
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b3988 <uniffi_pbcli_checksum_method_api_base@@Base+0x247104>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r5, r6, r8, ip, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffcebbac
│ │ +	ldmia.w	sp!, {r3, r7, r8, ip, lr, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffcebbd3
│ │  			@ <UNDEFINED> instruction: 0xffce4f14
│ │  	movs	r0, r0
│ │  	stmia	r3!, {r6, r7}
│ │  	vqshlu.s64	q10, q8, #13
│ │  	movs	r0, r0
│ │  	strb	r0, [r0, r6]
│ │  	movs	r0, r0
│ │ @@ -1075587,15 +1075587,15 @@
│ │  	b.n	3b3118 <uniffi_pbcli_checksum_method_api_base@@Base+0x246894>
│ │  	str	r0, [r3, #0]
│ │  	b.n	3b311c <uniffi_pbcli_checksum_method_api_base@@Base+0x246898>
│ │  	asrs	r2, r1, #32
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b3aa0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24721c>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r6, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r4, r5, r6, ip, lr, pc}
│ │  	vsra.u8	d22, d4, #2
│ │  			@ <UNDEFINED> instruction: 0xffcc4f94
│ │  	movs	r0, r0
│ │  	stmia	r2!, {r3, r5, r7}
│ │  	vsli.64	q10, q4, #13
│ │  	movs	r0, r0
│ │  	strb	r0, [r5, r1]
│ │ @@ -1075705,16 +1075705,16 @@
│ │  	b.n	3b3220 <uniffi_pbcli_checksum_method_api_base@@Base+0x24699c>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b3224 <uniffi_pbcli_checksum_method_api_base@@Base+0x2469a0>
│ │  	lsrs	r0, r1, #31
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b3ba8 <uniffi_pbcli_checksum_method_api_base@@Base+0x247324>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r8, r9, sl, fp, lr, pc}
│ │ -	vsubl.u8	q13, d30, d7
│ │ +	ldmia.w	sp!, {r5, r6, r8, r9, sl, fp, lr, pc}
│ │ +	vsubl.u8	q13, d30, d30
│ │  	vmul.i<illegal width 8>	q11, q15, d1[7]
│ │  	vqshlu.s8	q10, q2, #5
│ │  	movs	r0, r0
│ │  	strh	r0, [r1, r7]
│ │  	movs	r0, r0
│ │  	lsrs	r1, r2, #28
│ │  	b.n	3b3a0c <uniffi_pbcli_checksum_method_api_base@@Base+0x247188>
│ │ @@ -1075821,16 +1075821,16 @@
│ │  	b.n	3b3324 <uniffi_pbcli_checksum_method_api_base@@Base+0x246aa0>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b3328 <uniffi_pbcli_checksum_method_api_base@@Base+0x246aa4>
│ │  	lsrs	r7, r0, #30
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b3cac <uniffi_pbcli_checksum_method_api_base@@Base+0x247428>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r9, sl, fp, lr, pc}
│ │ -	vsra.u64	d26, d17, #50
│ │ +	ldmia.w	sp!, {r2, r3, r4, r6, r9, sl, fp, lr, pc}
│ │ +	vsra.u64	q13, q4, #50
│ │  			@ <UNDEFINED> instruction: 0xffce67e9
│ │  	vqshrun.s16	d20, q10, #3
│ │  	movs	r0, r0
│ │  	strh	r4, [r0, r3]
│ │  	movs	r0, r0
│ │  	lsrs	r1, r2, #28
│ │  	b.n	3b3b10 <uniffi_pbcli_checksum_method_api_base@@Base+0x24728c>
│ │ @@ -1075937,15 +1075937,15 @@
│ │  	b.n	3b3428 <uniffi_pbcli_checksum_method_api_base@@Base+0x246ba4>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b342c <uniffi_pbcli_checksum_method_api_base@@Base+0x246ba8>
│ │  	lsrs	r6, r0, #29
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b3db0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24752c>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r4, r5, r8, sl, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r3, r4, r6, r8, sl, fp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffce4f23
│ │  	vmlsl.u<illegal width 8>	q11, d29, d1[5]
│ │  	vqshl.u64	q10, q10, #13
│ │  	movs	r0, r0
│ │  	str	r0, [r0, r7]
│ │  	movs	r0, r0
│ │  	lsrs	r1, r2, #28
│ │ @@ -1076053,16 +1076053,16 @@
│ │  	b.n	3b352c <uniffi_pbcli_checksum_method_api_base@@Base+0x246ca8>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b3530 <uniffi_pbcli_checksum_method_api_base@@Base+0x246cac>
│ │  	lsrs	r5, r0, #28
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b3eb4 <uniffi_pbcli_checksum_method_api_base@@Base+0x247630>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r3, r5, sl, fp, lr, pc}
│ │ -	vqrdmlsh.s<illegal width 8>	q9, q15, d2[1]
│ │ +	ldmia.w	sp!, {r2, r4, r6, sl, fp, lr, pc}
│ │ +	vqrdmlsh.s<illegal width 8>	q9, q15, d1[7]
│ │  	vmls.f<illegal width 8>	q11, q15, d1[4]
│ │  	vmul.i<illegal width 8>	q10, <illegal reg q6.5>, d0[5]
│ │  	movs	r0, r0
│ │  	str	r4, [r7, r2]
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │  	b.n	3b40dc <uniffi_pbcli_checksum_method_api_base@@Base+0x247858>
│ │ @@ -1076172,17 +1076172,17 @@
│ │  	b.n	3b3638 <uniffi_pbcli_checksum_method_api_base@@Base+0x246db4>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b363c <uniffi_pbcli_checksum_method_api_base@@Base+0x246db8>
│ │  	lsrs	r2, r0, #27
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b3fc0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24773c>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r5, r8, r9, fp, lr, pc}
│ │ -	vshr.u64	d23, d16, #50
│ │ -	vmlsl.u8	<illegal reg q10.5>, d30, d10
│ │ +	ldmia.w	sp!, {r3, r6, r8, r9, fp, lr, pc}
│ │ +	vshr.u64	<illegal reg q11.5>, <illegal reg q3.5>, #50
│ │ +			@ <UNDEFINED> instruction: 0xffce5ab1
│ │  	vmul.i<illegal width 8>	q10, q15, d0[3]
│ │  	movs	r0, r0
│ │  	str	r4, [r7, r1]
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │  	b.n	3b41e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x247964>
│ │  	movs	r1, r0
│ │ @@ -1076291,17 +1076291,17 @@
│ │  	b.n	3b3744 <uniffi_pbcli_checksum_method_api_base@@Base+0x246ec0>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b3748 <uniffi_pbcli_checksum_method_api_base@@Base+0x246ec4>
│ │  	lsrs	r7, r7, #25
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b40cc <uniffi_pbcli_checksum_method_api_base@@Base+0x247848>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r4, r9, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r5, r9, fp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffceed12
│ │ -	vqrshrn.u16	d21, q15, #4
│ │ +			@ <UNDEFINED> instruction: 0xffcc59a5
│ │  	vqrshrn.u16	d20, q4, #2
│ │  	movs	r0, r0
│ │  	ldr	r7, [pc, #448]	@ (3b3e0c <uniffi_pbcli_checksum_method_api_base@@Base+0x247588>)
│ │  	movs	r0, r0
│ │  	lsrs	r1, r2, #28
│ │  	b.n	3b3f30 <uniffi_pbcli_checksum_method_api_base@@Base+0x2476ac>
│ │  	lsls	r0, r4, #10
│ │ @@ -1076407,17 +1076407,17 @@
│ │  	b.n	3b3848 <uniffi_pbcli_checksum_method_api_base@@Base+0x246fc4>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b384c <uniffi_pbcli_checksum_method_api_base@@Base+0x246fc8>
│ │  	lsrs	r6, r7, #24
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b41d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24794c>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r4, r8, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r3, r4, r5, r8, fp, lr, pc}
│ │  	vmls.f<illegal width 8>	q9, q15, d3[5]
│ │ -			@ <UNDEFINED> instruction: 0xffcfc982
│ │ +			@ <UNDEFINED> instruction: 0xffcfc9a9
│ │  	vaddl.u8	q10, d14, d28
│ │  	movs	r0, r0
│ │  	ldr	r5, [pc, #640]	@ (3b3fd0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24774c>)
│ │  	movs	r0, r0
│ │  	lsrs	r1, r2, #28
│ │  	b.n	3b4034 <uniffi_pbcli_checksum_method_api_base@@Base+0x2477b0>
│ │  	lsls	r0, r4, #10
│ │ @@ -1076523,17 +1076523,17 @@
│ │  	b.n	3b394c <uniffi_pbcli_checksum_method_api_base@@Base+0x2470c8>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b3950 <uniffi_pbcli_checksum_method_api_base@@Base+0x2470cc>
│ │  	lsrs	r5, r7, #23
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b42d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x247a50>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r3, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r4, r5, fp, lr, pc}
│ │  	vsubw.u8	q13, q7, d16
│ │ -	vqrshrun.s16	d28, q15, #4
│ │ +	vmlal.u8	q14, d28, d21
│ │  	vsubl.u8	q10, d14, d12
│ │  	movs	r0, r0
│ │  	ldr	r4, [pc, #624]	@ (3b40c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x247840>)
│ │  	movs	r0, r0
│ │  	lsrs	r1, r2, #28
│ │  	b.n	3b4138 <uniffi_pbcli_checksum_method_api_base@@Base+0x2478b4>
│ │  	lsls	r0, r4, #10
│ │ @@ -1076639,17 +1076639,17 @@
│ │  	b.n	3b3a50 <uniffi_pbcli_checksum_method_api_base@@Base+0x2471cc>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b3a54 <uniffi_pbcli_checksum_method_api_base@@Base+0x2471d0>
│ │  	lsrs	r4, r7, #22
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b43d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x247b54>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r3, r8, r9, sl, lr, pc}
│ │ +	ldmia.w	sp!, {r4, r5, r8, r9, sl, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffce4920
│ │ -	vqshl.u8	q14, q13, #5
│ │ +	vabdl.u8	q14, d29, d17
│ │  	vmla.f<illegal width 8>	q10, q15, d0[3]
│ │  	movs	r0, r0
│ │  	ldr	r3, [pc, #608]	@ (3b41b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x247934>)
│ │  	movs	r0, r0
│ │  	lsrs	r1, r2, #28
│ │  	b.n	3b423c <uniffi_pbcli_checksum_method_api_base@@Base+0x2479b8>
│ │  	lsls	r0, r4, #10
│ │ @@ -1076755,17 +1076755,17 @@
│ │  	b.n	3b3b54 <uniffi_pbcli_checksum_method_api_base@@Base+0x2472d0>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b3b58 <uniffi_pbcli_checksum_method_api_base@@Base+0x2472d4>
│ │  	lsrs	r3, r7, #21
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b44dc <uniffi_pbcli_checksum_method_api_base@@Base+0x247c58>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r9, sl, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r5, r9, sl, lr, pc}
│ │  	vqshlu.s64	<illegal reg q10.5>, <illegal reg q11.5>, #14
│ │ -	vqshlu.s8	q14, q11, #4
│ │ +	vqshlu.s64	d28, d13, #12
│ │  	vrshr.u8	d20, d28, #2
│ │  	movs	r0, r0
│ │  	ldr	r2, [pc, #592]	@ (3b42ac <uniffi_pbcli_checksum_method_api_base@@Base+0x247a28>)
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │  	b.n	3b4704 <uniffi_pbcli_checksum_method_api_base@@Base+0x247e80>
│ │  	movs	r1, r0
│ │ @@ -1076874,15 +1076874,15 @@
│ │  	b.n	3b3c60 <uniffi_pbcli_checksum_method_api_base@@Base+0x2473dc>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b3c64 <uniffi_pbcli_checksum_method_api_base@@Base+0x2473e0>
│ │  	lsrs	r0, r7, #20
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b45e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x247d64>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r6, r7, sl, lr, pc}
│ │ +	ldmia.w	sp!, {r5, r8, sl, lr, pc}
│ │  	vqshl.u64	q12, <illegal reg q2.5>, #14
│ │  	vqshrn.u16	d27, q5, #4
│ │  	vsubl.u8	q10, d28, d20
│ │  	movs	r0, r0
│ │  	ldr	r2, [pc, #336]	@ (3b42b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x247a34>)
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │ @@ -1076993,15 +1076993,15 @@
│ │  	b.n	3b3d6c <uniffi_pbcli_checksum_method_api_base@@Base+0x2474e8>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b3d70 <uniffi_pbcli_checksum_method_api_base@@Base+0x2474ec>
│ │  	lsrs	r5, r6, #19
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b46f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x247e70>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r3, r5, r6, r7, r8, r9, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r4, sl, lr, pc}
│ │  	vsli.8	<illegal reg q11.5>, q0, #6
│ │  	vmlal.u8	<illegal reg q13.5>, d13, d14
│ │  	vrsra.u8	d20, d16, #4
│ │  	movs	r0, r0
│ │  	ldr	r1, [pc, #288]	@ (3b4394 <uniffi_pbcli_checksum_method_api_base@@Base+0x247b10>)
│ │  	movs	r0, r0
│ │  	lsrs	r1, r2, #28
│ │ @@ -1077109,17 +1077109,17 @@
│ │  	b.n	3b3e70 <uniffi_pbcli_checksum_method_api_base@@Base+0x2475ec>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b3e74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2475f0>
│ │  	lsrs	r4, r6, #18
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b47f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x247f74>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r3, r5, r6, r7, r9, lr, pc}
│ │ -	vrsubhn.i16	d18, q15, <illegal reg q11.5>
│ │ -	vqrshrun.s16	d16, <illegal reg q6.5>, #2
│ │ +	ldmia.w	sp!, {r4, r8, r9, lr, pc}
│ │ +	vmlsl.u<illegal width 8>	q9, d30, d2[3]
│ │ +	vmlal.u8	q8, d30, d4
│ │  	vmlsl.u8	<illegal reg q9.5>, d15, d4
│ │  	movs	r0, r0
│ │  	bx	pc
│ │  	movs	r0, r0
│ │  	lsrs	r1, r2, #28
│ │  	b.n	3b465c <uniffi_pbcli_checksum_method_api_base@@Base+0x247dd8>
│ │  	lsls	r0, r4, #10
│ │ @@ -1077225,17 +1077225,17 @@
│ │  	b.n	3b3f74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2476f0>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b3f78 <uniffi_pbcli_checksum_method_api_base@@Base+0x2476f4>
│ │  	lsrs	r3, r6, #17
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b48fc <uniffi_pbcli_checksum_method_api_base@@Base+0x248078>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r5, r6, r7, r8, lr, pc}
│ │ -	vsubl.u8	q14, d30, d16
│ │ -	vqshl.u8	q8, <illegal reg q4.5>, #6
│ │ +	ldmia.w	sp!, {r2, r3, r9, lr, pc}
│ │ +	vmlal.u<illegal width 8>	q14, d30, d3[1]
│ │ +	vabdl.u8	q8, d30, d0
│ │  			@ <UNDEFINED> instruction: 0xffcf3be4
│ │  	movs	r0, r0
│ │  	mov	r4, lr
│ │  	movs	r0, r0
│ │  	lsrs	r1, r2, #28
│ │  	b.n	3b4760 <uniffi_pbcli_checksum_method_api_base@@Base+0x247edc>
│ │  	lsls	r0, r4, #10
│ │ @@ -1077341,17 +1077341,17 @@
│ │  	b.n	3b4078 <uniffi_pbcli_checksum_method_api_base@@Base+0x2477f4>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b407c <uniffi_pbcli_checksum_method_api_base@@Base+0x2477f8>
│ │  	lsrs	r2, r6, #16
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b4a00 <uniffi_pbcli_checksum_method_api_base@@Base+0x24817c>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r5, r6, r7, lr, pc}
│ │ +	ldmia.w	sp!, {r3, r8, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffce692a
│ │ -	vqshlu.s8	q8, <illegal reg q2.5>, #4
│ │ +	vqshlu.s8	q8, q14, #4
│ │  			@ <UNDEFINED> instruction: 0xffcf3ba4
│ │  	movs	r0, r0
│ │  	cmp	r0, lr
│ │  	movs	r0, r0
│ │  	lsrs	r1, r2, #28
│ │  	b.n	3b4864 <uniffi_pbcli_checksum_method_api_base@@Base+0x247fe0>
│ │  	lsls	r0, r4, #10
│ │ @@ -1077457,17 +1077457,17 @@
│ │  	b.n	3b417c <uniffi_pbcli_checksum_method_api_base@@Base+0x2478f8>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b4180 <uniffi_pbcli_checksum_method_api_base@@Base+0x2478fc>
│ │  	lsrs	r1, r6, #15
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b4b04 <uniffi_pbcli_checksum_method_api_base@@Base+0x248280>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r6, r7, r8, r9, sl, fp, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r2, lr, pc}
│ │  	vmla.f<illegal width 8>	<illegal reg q8.5>, q15, d0[5]
│ │ -	vsli.8	q8, <illegal reg q0.5>, #5
│ │ +	vsli.8	q8, q12, #5
│ │  			@ <UNDEFINED> instruction: 0xffcf3c14
│ │  	movs	r0, r0
│ │  	add	r4, sp
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │  	b.n	3b4d2c <uniffi_pbcli_checksum_method_api_base@@Base+0x2484a8>
│ │  	movs	r1, r0
│ │ @@ -1077576,15 +1077576,15 @@
│ │  	b.n	3b4288 <uniffi_pbcli_checksum_method_api_base@@Base+0x247a04>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b428c <uniffi_pbcli_checksum_method_api_base@@Base+0x247a08>
│ │  	lsrs	r6, r5, #14
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b4c10 <uniffi_pbcli_checksum_method_api_base@@Base+0x24838c>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r4, r6, r7, r9, sl, fp, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r3, r4, r5, r6, r7, r9, sl, fp, ip, sp, pc}
│ │  	vsra.u64	q12, q3, #50
│ │  			@ <UNDEFINED> instruction: 0xffccdd96
│ │  			@ <UNDEFINED> instruction: 0xffcd3c7c
│ │  	movs	r0, r0
│ │  	add	r4, r5
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │ @@ -1077695,15 +1077695,15 @@
│ │  	b.n	3b4394 <uniffi_pbcli_checksum_method_api_base@@Base+0x247b10>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b4398 <uniffi_pbcli_checksum_method_api_base@@Base+0x247b14>
│ │  	lsrs	r3, r5, #13
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b4d1c <uniffi_pbcli_checksum_method_api_base@@Base+0x248498>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r6, r7, r8, sl, fp, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r5, r6, r7, r8, sl, fp, ip, sp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffce9904
│ │  	vmull.u8	<illegal reg q14.5>, d28, d10
│ │  			@ <UNDEFINED> instruction: 0xffcd3d08
│ │  	movs	r0, r0
│ │  	orrs	r0, r4
│ │  	movs	r0, r0
│ │  	lsrs	r1, r2, #28
│ │ @@ -1077811,17 +1077811,17 @@
│ │  	b.n	3b4498 <uniffi_pbcli_checksum_method_api_base@@Base+0x247c14>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b449c <uniffi_pbcli_checksum_method_api_base@@Base+0x247c18>
│ │  	lsrs	r2, r5, #12
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b4e20 <uniffi_pbcli_checksum_method_api_base@@Base+0x24859c>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r6, r7, sl, fp, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r3, r5, r6, r7, sl, fp, ip, sp, pc}
│ │  	vqrdmlsh.s<illegal width 8>	q13, q7, d3[7]
│ │ -			@ <UNDEFINED> instruction: 0xffcd4c51
│ │ +			@ <UNDEFINED> instruction: 0xffcd4c78
│ │  	vrsra.u64	<illegal reg q9.5>, q6, #50
│ │  	movs	r0, r0
│ │  	adcs	r0, r2
│ │  	movs	r0, r0
│ │  	lsrs	r1, r2, #28
│ │  	b.n	3b4c84 <uniffi_pbcli_checksum_method_api_base@@Base+0x248400>
│ │  	lsls	r0, r4, #10
│ │ @@ -1077927,17 +1077927,17 @@
│ │  	b.n	3b459c <uniffi_pbcli_checksum_method_api_base@@Base+0x247d18>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b45a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x247d1c>
│ │  	lsrs	r1, r5, #11
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b4f24 <uniffi_pbcli_checksum_method_api_base@@Base+0x2486a0>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r5, r7, r8, r9, fp, ip, sp, pc}
│ │ -	vabal.u8	<illegal reg q9.5>, d14, d13
│ │ -			@ <UNDEFINED> instruction: 0xffce4b4d
│ │ +	ldmia.w	sp!, {r2, r5, r6, r7, r8, r9, fp, ip, sp, pc}
│ │ +	vsli.8	d19, d20, #6
│ │ +			@ <UNDEFINED> instruction: 0xffce4b74
│ │  	vsli.64	d19, d28, #14
│ │  	movs	r0, r0
│ │  	eors	r4, r1
│ │  	movs	r0, r0
│ │  	lsrs	r1, r2, #28
│ │  	b.n	3b4d88 <uniffi_pbcli_checksum_method_api_base@@Base+0x248504>
│ │  	lsls	r0, r4, #10
│ │ @@ -1078043,17 +1078043,17 @@
│ │  	b.n	3b46a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x247e1c>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b46a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x247e20>
│ │  	lsrs	r0, r5, #10
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b5028 <uniffi_pbcli_checksum_method_api_base@@Base+0x2487a4>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r7, r9, fp, ip, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffcebba1
│ │ -	vmull.u<illegal width 8>	q10, d14, d1[2]
│ │ +	ldmia.w	sp!, {r5, r6, r7, r9, fp, ip, sp, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffcebbc8
│ │ +			@ <UNDEFINED> instruction: 0xffce4a70
│ │  	vsli.8	<illegal reg q9.5>, q14, #6
│ │  	movs	r0, r0
│ │  	subs	r7, #72	@ 0x48
│ │  	movs	r0, r0
│ │  	lsrs	r1, r2, #28
│ │  	b.n	3b4e8c <uniffi_pbcli_checksum_method_api_base@@Base+0x248608>
│ │  	lsls	r0, r4, #10
│ │ @@ -1078159,17 +1078159,17 @@
│ │  	b.n	3b47a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x247f20>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b47a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x247f24>
│ │  	lsrs	r7, r4, #9
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b512c <uniffi_pbcli_checksum_method_api_base@@Base+0x2488a8>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r7, r8, fp, ip, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffcebabf
│ │ -	vmul.f<illegal width 8>	q10, q7, d1[1]
│ │ +	ldmia.w	sp!, {r2, r3, r4, r6, r7, r8, fp, ip, sp, pc}
│ │ +	vmull.u<illegal width 8>	<illegal reg q13.5>, d30, d2[5]
│ │ +	vmul.f<illegal width 8>	q10, q7, d0[7]
│ │  	vmls.f<illegal width 8>	<illegal reg q9.5>, q15, d0[7]
│ │  	movs	r0, r0
│ │  	subs	r6, #68	@ 0x44
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │  	b.n	3b5354 <uniffi_pbcli_checksum_method_api_base@@Base+0x248ad0>
│ │  	movs	r1, r0
│ │ @@ -1078278,15 +1078278,15 @@
│ │  	b.n	3b48b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24802c>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b48b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x248030>
│ │  	lsrs	r4, r4, #8
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b5238 <uniffi_pbcli_checksum_method_api_base@@Base+0x2489b4>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r3, r5, r7, fp, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r4, r6, r7, fp, ip, sp, pc}
│ │  	vsubl.u8	<illegal reg q10.5>, d30, d25
│ │  	vabdl.u8	<illegal reg q14.5>, d29, d0
│ │  	vqshlu.s8	<illegal reg q9.5>, q2, #5
│ │  	movs	r0, r0
│ │  	subs	r6, #4
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │ @@ -1078397,16 +1078397,16 @@
│ │  	b.n	3b49bc <uniffi_pbcli_checksum_method_api_base@@Base+0x248138>
│ │  	str	r0, [r3, r0]
│ │  	b.n	3b49c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24813c>
│ │  	lsrs	r1, r4, #7
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b5344 <uniffi_pbcli_checksum_method_api_base@@Base+0x248ac0>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r7, r8, r9, sl, ip, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffcefd5c
│ │ +	ldmia.w	sp!, {r2, r6, r7, r8, r9, sl, ip, sp, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffcefd83
│ │  	vqshlu.s8	<illegal reg q14.5>, q10, #6
│ │  	vmlsl.u<illegal width 8>	<illegal reg q9.5>, d29, d0[4]
│ │  	movs	r0, r0
│ │  	subs	r4, #248	@ 0xf8
│ │  	movs	r0, r0
│ │  	lsrs	r1, r2, #28
│ │  	b.n	3b51a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x248924>
│ │ @@ -1078554,22 +1078554,22 @@
│ │  	movs	r0, r0
│ │  	cmp	r0, #140	@ 0x8c
│ │  	movs	r0, r0
│ │  	strh	r0, [r0, #38]	@ 0x26
│ │  	movs	r2, r2
│ │  	movs	r7, #216	@ 0xd8
│ │  	movs	r0, r0
│ │ -	strb	r0, [r4, #13]
│ │ +	strb	r7, [r0, #14]
│ │  	vmlal.u8	q9, d14, d12
│ │  	movs	r0, r0
│ │  	cmp	r0, #184	@ 0xb8
│ │  	movs	r0, r0
│ │  	strh	r0, [r6, #38]	@ 0x26
│ │  	movs	r2, r2
│ │ -			@ <UNDEFINED> instruction: 0xb6a1
│ │ +			@ <UNDEFINED> instruction: 0xb6c8
│ │  	vmul.f<illegal width 8>	<illegal reg q14.5>, q15, d1[2]
│ │  			@ <UNDEFINED> instruction: 0xffcc0f11
│ │  	b.n	3b5308 <uniffi_pbcli_checksum_method_api_base@@Base+0x248a84>
│ │  	asrs	r3, r0, #32
│ │  	b.n	3b5450 <uniffi_pbcli_checksum_method_api_base@@Base+0x248bcc>
│ │  	asrs	r1, r0, #32
│ │  	asrs	r0, r0, #12
│ │ @@ -1078820,27 +1078820,27 @@
│ │  	b.n	3b58ee <uniffi_pbcli_checksum_method_api_base@@Base+0x24906a>
│ │  	ands	r1, r0
│ │  	stmia	r3!, {}
│ │  	movs	r1, r1
│ │  	b.n	3b5596 <uniffi_pbcli_checksum_method_api_base@@Base+0x248d12>
│ │  	subs	r7, r7, r7
│ │  			@ <UNDEFINED> instruction: 0xebfbff96
│ │ -			@ <UNDEFINED> instruction: 0xeaffb421
│ │ -	vrsra.u8	q10, q4, #2
│ │ +			@ <UNDEFINED> instruction: 0xeaffb448
│ │ +	vrsra.u8	q10, <illegal reg q15.5>, #2
│ │  	vqshlu.s8	d29, d14, #6
│ │  	vmlal.u<illegal width 8>	q12, d12, d0[0]
│ │  	movs	r2, r2
│ │  	strh	r4, [r2, #18]
│ │  	movs	r2, r2
│ │ -	strb	r0, [r4, #6]
│ │ +	strb	r7, [r0, #7]
│ │  	vsubw.u8	q12, q7, d28
│ │  	movs	r2, r2
│ │ -	push	{r0, r2, r3, r4, r5}
│ │ -	vrsra.u8	q10, q10, #2
│ │ -	vmls.f<illegal width 8>	<illegal reg q13.5>, q7, d1[0]
│ │ +	push	{r2, r5, r6}
│ │ +	vrsra.u64	d20, d11, #50
│ │ +	vmls.f<illegal width 8>	<illegal reg q13.5>, q7, d0[6]
│ │  	vmull.p8	q15, d30, d21
│ │  	vaddl.u8	q8, d13, d0
│ │  	b.n	3b5930 <uniffi_pbcli_checksum_method_api_base@@Base+0x2490ac>
│ │  	movs	r1, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	movs	r0, r0
│ │ @@ -1079058,22 +1079058,22 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	3b5bb6 <uniffi_pbcli_checksum_method_api_base@@Base+0x249332>
│ │  	strh	r7, [r7, #54]	@ 0x36
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3b57be <uniffi_pbcli_checksum_method_api_base@@Base+0x248f3a>
│ │  	subs	r5, r6, r5
│ │  			@ <UNDEFINED> instruction: 0xebfbffa8
│ │ -			@ <UNDEFINED> instruction: 0xeaffb241
│ │ -	vsra.u8	q10, q12, #2
│ │ -	vaddw.u8	<illegal reg q13.5>, q15, d5
│ │ +			@ <UNDEFINED> instruction: 0xeaffb268
│ │ +	vsra.u64	d20, d15, #50
│ │ +	vaddw.u8	<illegal reg q13.5>, q15, d28
│ │  	vsubl.u8	q10, d14, d9
│ │ -	vaddw.u8	<illegal reg q13.5>, q14, d29
│ │ -	vrshr.u8	<illegal reg q13.5>, <illegal reg q6.5>, #2
│ │ -	vsra.u64	d20, d4, #50
│ │ -	vrshr.u64	<illegal reg q13.5>, <illegal reg q0.5>, #50
│ │ +	vsra.u64	<illegal reg q13.5>, q2, #52
│ │ +	vsubl.u8	<illegal reg q13.5>, d30, d4
│ │ +	vsra.u64	d20, d27, #50
│ │ +	vrshr.u64	<illegal reg q13.5>, q12, #50
│ │  	vsra.u64	<illegal reg q14.5>, q8, #50
│ │  	vaddl.u8	q8, d13, d0
│ │  	b.n	3b5b50 <uniffi_pbcli_checksum_method_api_base@@Base+0x2492cc>
│ │  	movs	r1, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	movs	r0, r0
│ │ @@ -1079243,23 +1079243,23 @@
│ │  	movs	r0, r0
│ │  	and.w	r0, r0, r0, lsl #16
│ │  	b.n	3b5d6a <uniffi_pbcli_checksum_method_api_base@@Base+0x2494e6>
│ │  	movs	r6, r0
│ │  	b.n	3b596e <uniffi_pbcli_checksum_method_api_base@@Base+0x2490ea>
│ │  	subs	r1, r1, r4
│ │  			@ <UNDEFINED> instruction: 0xebfbffc4
│ │ -			@ <UNDEFINED> instruction: 0xeaffb021
│ │ -			@ <UNDEFINED> instruction: 0xffce3f58
│ │ +			@ <UNDEFINED> instruction: 0xeaffb048
│ │ +			@ <UNDEFINED> instruction: 0xffce3f7f
│ │  	vmls.i<illegal width 8>	q9, q7, d0[2]
│ │  	movs	r0, r0
│ │ -	vext.8	<illegal reg q15.5>, <illegal reg q9.5>, q7, #15
│ │ -	add	sp, #244	@ 0xf4
│ │ -			@ <UNDEFINED> instruction: 0xffce3f74
│ │ -	vshr.u64	d27, d17, #50
│ │ -			@ <UNDEFINED> instruction: 0xffcec8de
│ │ +	bl	3d05e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x263d5c>
│ │ +	add	sp, #400	@ 0x190
│ │ +			@ <UNDEFINED> instruction: 0xffce3f9b
│ │ +	vshr.u64	<illegal reg q13.5>, q4, #50
│ │ +			@ <UNDEFINED> instruction: 0xffcec905
│ │  	vaddl.u8	q8, d14, d0
│ │  	b.n	3b5cfc <uniffi_pbcli_checksum_method_api_base@@Base+0x249478>
│ │  	movs	r1, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	movs	r0, r0
│ │  	b.n	3b5da6 <uniffi_pbcli_checksum_method_api_base@@Base+0x249522>
│ │ @@ -1079476,23 +1079476,23 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	3b5f82 <uniffi_pbcli_checksum_method_api_base@@Base+0x2496fe>
│ │  	strh	r4, [r1, #48]	@ 0x30
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3b5b8a <uniffi_pbcli_checksum_method_api_base@@Base+0x249306>
│ │  	subs	r2, r0, r2
│ │  			@ <UNDEFINED> instruction: 0xebfbffa8
│ │ -			@ <UNDEFINED> instruction: 0xeaffae4d
│ │ -			@ <UNDEFINED> instruction: 0xffce3d84
│ │ -			@ <UNDEFINED> instruction: 0xffceadb9
│ │ +			@ <UNDEFINED> instruction: 0xeaffae74
│ │ +			@ <UNDEFINED> instruction: 0xffce3dab
│ │ +	vqrdmulh.s<illegal width 8>	q13, q15, d0[4]
│ │  			@ <UNDEFINED> instruction: 0xffce3e3d
│ │ -	vqrdmulh.s<illegal width 8>	q13, q14, d1[4]
│ │ -	vmull.p8	q13, d14, d21
│ │ -			@ <UNDEFINED> instruction: 0xffce3d5c
│ │ -			@ <UNDEFINED> instruction: 0xffceaf05
│ │ -			@ <UNDEFINED> instruction: 0xffcefd82
│ │ +	vmull.p8	q13, d12, d8
│ │ +	vqrdmlah.s<illegal width 8>	q13, q7, d0[3]
│ │ +			@ <UNDEFINED> instruction: 0xffce3d83
│ │ +			@ <UNDEFINED> instruction: 0xffceaf2c
│ │ +			@ <UNDEFINED> instruction: 0xffcefda9
│ │  	vaddl.u8	q8, d13, d0
│ │  	b.n	3b5f1c <uniffi_pbcli_checksum_method_api_base@@Base+0x249698>
│ │  	movs	r1, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	movs	r0, r0
│ │  	b.n	3b5fc6 <uniffi_pbcli_checksum_method_api_base@@Base+0x249742>
│ │ @@ -1079661,22 +1079661,22 @@
│ │  			@ <UNDEFINED> instruction: 0xffc1eaff
│ │  	ands	r0, r0
│ │  	b.n	3b6136 <uniffi_pbcli_checksum_method_api_base@@Base+0x2498b2>
│ │  	movs	r6, r0
│ │  	b.n	3b5d3a <uniffi_pbcli_checksum_method_api_base@@Base+0x2494b6>
│ │  	subs	r6, r2, r0
│ │  			@ <UNDEFINED> instruction: 0xebfbffc4
│ │ -			@ <UNDEFINED> instruction: 0xeaffac19
│ │ -			@ <UNDEFINED> instruction: 0xffce3b50
│ │ +			@ <UNDEFINED> instruction: 0xeaffac40
│ │ +			@ <UNDEFINED> instruction: 0xffce3b77
│ │  	vmla.i<illegal width 8>	q9, q15, d0[0]
│ │  	movs	r0, r0
│ │  	strh	r7, [r4, #18]
│ │ -			@ <UNDEFINED> instruction: 0xffcdabf1
│ │ -			@ <UNDEFINED> instruction: 0xffce3b28
│ │ -	vqdmulh.s<illegal width 8>	q13, q15, d1[5]
│ │ +			@ <UNDEFINED> instruction: 0xffcdac18
│ │ +			@ <UNDEFINED> instruction: 0xffce3b4f
│ │ +			@ <UNDEFINED> instruction: 0xffcead0c
│ │  	vmlal.u8	q12, d14, d15
│ │  			@ <UNDEFINED> instruction: 0xffcd0f11
│ │  	b.n	3b5d04 <uniffi_pbcli_checksum_method_api_base@@Base+0x249480>
│ │  	asrs	r7, r0, #2
│ │  	b.n	3b5e4c <uniffi_pbcli_checksum_method_api_base@@Base+0x2495c8>
│ │  	asrs	r1, r0, #32
│ │  	asrs	r0, r0, #12
│ │ @@ -1079908,20 +1079908,20 @@
│ │  	subs	r2, #150	@ 0x96
│ │  	vmull.u8	<illegal reg q8.5>, d12, d12
│ │  	movs	r0, r0
│ │  	subs	r4, r4, #3
│ │  	movs	r0, r0
│ │  	ldrb	r0, [r3, #0]
│ │  	movs	r2, r2
│ │ -	add	r1, sp, #964	@ 0x3c4
│ │ -			@ <UNDEFINED> instruction: 0xffce3928
│ │ -	vqrdmulh.s<illegal width 8>	q8, q15, d1[4]
│ │ +	add	r2, sp, #96	@ 0x60
│ │ +	vmul.f<illegal width 8>	<illegal reg q9.5>, q7, d3[3]
│ │ +	vmull.p8	q8, d14, d8
│ │  	vmlal.u8	<illegal reg q11.5>, d30, d12
│ │  	movs	r2, r2
│ │ -	add	r3, sp, #276	@ 0x114
│ │ +	add	r3, sp, #432	@ 0x1b0
│ │  	vsli.8	d27, d19, #6
│ │  			@ <UNDEFINED> instruction: 0xffcd0f11
│ │  	b.n	3b5f28 <uniffi_pbcli_checksum_method_api_base@@Base+0x2496a4>
│ │  	asrs	r7, r0, #2
│ │  	b.n	3b6070 <uniffi_pbcli_checksum_method_api_base@@Base+0x2497ec>
│ │  	asrs	r1, r0, #32
│ │  	asrs	r0, r0, #12
│ │ @@ -1080179,28 +1080179,28 @@
│ │  	b.n	3b647a <uniffi_pbcli_checksum_method_api_base@@Base+0x249bf6>
│ │  	asrs	r4, r1, #32
│ │  	b.n	3b64fe <uniffi_pbcli_checksum_method_api_base@@Base+0x249c7a>
│ │  			@ <UNDEFINED> instruction: 0xff91eaff
│ │  	ands	r0, r0
│ │  	b.n	3b65c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x249d42>
│ │  			@ <UNDEFINED> instruction: 0xffeeeaff
│ │ -	add	r7, pc, #436	@ (adr r7, 3b6040 <uniffi_pbcli_checksum_method_api_base@@Base+0x2497bc>)
│ │ -	vrsubhn.i16	d19, q15, q10
│ │ +	add	r7, pc, #592	@ (adr r7, 3b60dc <uniffi_pbcli_checksum_method_api_base@@Base+0x249858>)
│ │ +	vmlsl.u<illegal width 8>	<illegal reg q9.5>, d30, d3[2]
│ │  			@ <UNDEFINED> instruction: 0xffce5922
│ │  	vqshlu.s64	d23, d24, #13
│ │  	movs	r2, r2
│ │  	strb	r4, [r6, #23]
│ │  	movs	r2, r2
│ │  	subs	r0, #14
│ │  	vabal.u8	<illegal reg q11.5>, d28, d12
│ │  	movs	r2, r2
│ │ -	lsrs	r1, r1, #15
│ │ +	lsrs	r0, r6, #15
│ │  	vmlsl.u<illegal width 8>	<illegal reg q11.5>, d14, d0[5]
│ │  	movs	r2, r2
│ │ -	add	r1, sp, #132	@ 0x84
│ │ +	add	r1, sp, #288	@ 0x120
│ │  	vqrshrun.s16	d28, q2, #2
│ │  	vaddl.u8	q8, d13, d1
│ │  	b.n	3b65fa <uniffi_pbcli_checksum_method_api_base@@Base+0x249d76>
│ │  	movs	r0, r0
│ │  	b.n	3b6560 <uniffi_pbcli_checksum_method_api_base@@Base+0x249cdc>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	movs	r1, r0
│ │ @@ -1080421,20 +1080421,20 @@
│ │  	movs	r1, r7
│ │  	b.n	3b67e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x249f5e>
│ │  	strh	r4, [r6, #30]
│ │  			@ <UNDEFINED> instruction: 0xebfc0005
│ │  	b.n	3b63ea <uniffi_pbcli_checksum_method_api_base@@Base+0x249b66>
│ │  	adds	r2, r5, r1
│ │  			@ <UNDEFINED> instruction: 0xebfbffab
│ │ -			@ <UNDEFINED> instruction: 0xeaffa57d
│ │ -	vsri.64	d19, d20, #50
│ │ -	vsli.8	q13, <illegal reg q2.5>, #6
│ │ +			@ <UNDEFINED> instruction: 0xeaffa5a4
│ │ +	vsri.64	<illegal reg q9.5>, <illegal reg q5.5>, #50
│ │ +	vsli.8	q13, q14, #6
│ │  	vsli.64	<illegal reg q9.5>, <illegal reg q4.5>, #14
│ │ -	vsli.64	q13, <illegal reg q12.5>, #12
│ │ -	vqshlu.s64	d26, d9, #14
│ │ +	vrsubhn.i16	d26, q6, q8
│ │ +	vmlsl.u<illegal width 8>	q13, d30, d0[0]
│ │  			@ <UNDEFINED> instruction: 0xffcec9d7
│ │  	vqrdmlsh.s<illegal width 8>	q13, q6, d1[6]
│ │  	vqshl.u64	d17, d12, #13
│ │  	movs	r0, r0
│ │  	subs	r4, r4, r6
│ │  	movs	r0, r0
│ │  	strb	r0, [r7, #14]
│ │ @@ -1080651,26 +1080651,26 @@
│ │  			@ <UNDEFINED> instruction: 0xffb2eaff
│ │  	ands	r0, r0
│ │  	b.n	3b69f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x24a16e>
│ │  	movs	r7, r0
│ │  	b.n	3b65f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x249d72>
│ │  	asrs	r7, r4, #31
│ │  			@ <UNDEFINED> instruction: 0xebfbffb2
│ │ -			@ <UNDEFINED> instruction: 0xeaffa341
│ │ -	vrshr.u8	<illegal reg q9.5>, q12, #2
│ │ +			@ <UNDEFINED> instruction: 0xeaffa368
│ │ +	vrshr.u64	d19, d15, #50
│ │  			@ <UNDEFINED> instruction: 0xffcead19
│ │  	vrshr.u8	d23, d0, #3
│ │  	movs	r2, r2
│ │  	strb	r0, [r5, #5]
│ │  	movs	r2, r2
│ │  	ble.n	3b633a <uniffi_pbcli_checksum_method_api_base@@Base+0x249ab6>
│ │  	vmla.f<illegal width 8>	<illegal reg q11.5>, <illegal reg q14.5>, d0[5]
│ │  	movs	r2, r2
│ │ -	add	r4, pc, #452	@ (adr r4, 3b64a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x249c1c>)
│ │ -			@ <UNDEFINED> instruction: 0xffceea58
│ │ +	add	r4, pc, #608	@ (adr r4, 3b653c <uniffi_pbcli_checksum_method_api_base@@Base+0x249cb8>)
│ │ +			@ <UNDEFINED> instruction: 0xffceea7f
│ │  			@ <UNDEFINED> instruction: 0xffce0f11
│ │  	b.n	3b65c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x249d40>
│ │  	asrs	r3, r0, #32
│ │  	b.n	3b670c <uniffi_pbcli_checksum_method_api_base@@Base+0x249e88>
│ │  	asrs	r1, r0, #32
│ │  	asrs	r0, r0, #12
│ │  	lsls	r0, r4, #10
│ │ @@ -1080813,22 +1080813,22 @@
│ │  	movs	r0, r0
│ │  	asrs	r0, r6, #17
│ │  	movs	r0, r0
│ │  	strb	r4, [r4, #2]
│ │  	movs	r2, r2
│ │  	asrs	r4, r7, #14
│ │  	movs	r0, r0
│ │ -	ldrsh	r4, [r0, r5]
│ │ +	ldrsh	r3, [r5, r5]
│ │  	vrsra.u64	<illegal reg q8.5>, q8, #50
│ │  	movs	r0, r0
│ │  	asrs	r4, r3, #18
│ │  	movs	r0, r0
│ │  	strb	r4, [r2, #3]
│ │  	movs	r2, r2
│ │ -	add	r2, pc, #532	@ (adr r2, 3b6650 <uniffi_pbcli_checksum_method_api_base@@Base+0x249dcc>)
│ │ +	add	r2, pc, #688	@ (adr r2, 3b66ec <uniffi_pbcli_checksum_method_api_base@@Base+0x249e68>)
│ │  	vmlsl.u<illegal width 8>	<illegal reg q12.5>, d30, d3[7]
│ │  			@ <UNDEFINED> instruction: 0xffcc0f11
│ │  	b.n	3b6724 <uniffi_pbcli_checksum_method_api_base@@Base+0x249ea0>
│ │  	asrs	r3, r0, #32
│ │  	b.n	3b686c <uniffi_pbcli_checksum_method_api_base@@Base+0x249fe8>
│ │  	asrs	r1, r0, #32
│ │  	asrs	r0, r0, #12
│ │ @@ -1081079,27 +1081079,27 @@
│ │  	b.n	3b6d0a <uniffi_pbcli_checksum_method_api_base@@Base+0x24a486>
│ │  	ands	r1, r0
│ │  	stmia	r3!, {}
│ │  	movs	r1, r1
│ │  	b.n	3b69b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x24a12e>
│ │  	asrs	r0, r7, #27
│ │  			@ <UNDEFINED> instruction: 0xebfbff96
│ │ -			@ <UNDEFINED> instruction: 0xeaffa005
│ │ -			@ <UNDEFINED> instruction: 0xffce2f3c
│ │ +			@ <UNDEFINED> instruction: 0xeaffa02c
│ │ +	vqrdmlsh.s<illegal width 8>	q9, q7, d3[4]
│ │  	vsubl.u8	q14, d14, d2
│ │  	vmull.p8	q11, d12, d20
│ │  	movs	r2, r2
│ │  	ldr	r0, [r7, #96]	@ 0x60
│ │  	movs	r2, r2
│ │ -	ldrb	r4, [r0, r6]
│ │ +	ldrb	r3, [r5, r6]
│ │  			@ <UNDEFINED> instruction: 0xffce6f10
│ │  	movs	r2, r2
│ │ -	add	r0, pc, #132	@ (adr r0, 3b671c <uniffi_pbcli_checksum_method_api_base@@Base+0x249e98>)
│ │ -			@ <UNDEFINED> instruction: 0xffce2f58
│ │ -	vaddw.u8	q13, q7, d21
│ │ +	add	r0, pc, #288	@ (adr r0, 3b67b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x249f34>)
│ │ +			@ <UNDEFINED> instruction: 0xffce2f7f
│ │ +	vmla.f<illegal width 8>	q13, q7, d0[3]
│ │  	vmla.i<illegal width 8>	q14, q7, d2[7]
│ │  			@ <UNDEFINED> instruction: 0xffcd0f11
│ │  	b.n	3b6988 <uniffi_pbcli_checksum_method_api_base@@Base+0x24a104>
│ │  	asrs	r3, r0, #32
│ │  	b.n	3b6ad0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24a24c>
│ │  	asrs	r1, r0, #32
│ │  	asrs	r0, r0, #12
│ │ @@ -1081234,15 +1081234,15 @@
│ │  	b.n	3b62e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x249a60>
│ │  	lsls	r0, r3, #14
│ │  			@ <UNDEFINED> instruction: 0xeb00d010
│ │  	b.n	3b6c68 <uniffi_pbcli_checksum_method_api_base@@Base+0x24a3e4>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r2, r3, r6, r7, r8, r9, sl, fp}
│ │  	movs	r0, r0
│ │ -	ldr	r6, [sp, #456]	@ 0x1c8
│ │ +	ldr	r6, [sp, #612]	@ 0x264
│ │  	vaddl.u8	<illegal reg q8.5>, d14, d0
│ │  	movs	r0, r0
│ │  	asrs	r4, r5, #2
│ │  	movs	r0, r0
│ │  	ldr	r0, [r4, #76]	@ 0x4c
│ │  	movs	r2, r2
│ │  	lsrs	r0, r7, #31
│ │ @@ -1081250,15 +1081250,15 @@
│ │  	movs	r0, #53	@ 0x35
│ │  	vaddl.u8	<illegal reg q8.5>, d13, d28
│ │  	movs	r0, r0
│ │  	asrs	r0, r3, #3
│ │  	movs	r0, r0
│ │  	ldr	r0, [r2, #80]	@ 0x50
│ │  	movs	r2, r2
│ │ -	ldr	r6, [sp, #772]	@ 0x304
│ │ +	ldr	r6, [sp, #928]	@ 0x3a0
│ │  	vsli.64	d22, d23, #14
│ │  			@ <UNDEFINED> instruction: 0xffcd0f11
│ │  	b.n	3b6ae8 <uniffi_pbcli_checksum_method_api_base@@Base+0x24a264>
│ │  	asrs	r3, r0, #32
│ │  	b.n	3b6c30 <uniffi_pbcli_checksum_method_api_base@@Base+0x24a3ac>
│ │  	asrs	r1, r0, #32
│ │  	asrs	r0, r0, #12
│ │ @@ -1081512,28 +1081512,28 @@
│ │  	movs	r0, #40	@ 0x28
│ │  	b.n	3b6574 <uniffi_pbcli_checksum_method_api_base@@Base+0x249cf0>
│ │  	movs	r0, r0
│ │  	b.n	3b6b58 <uniffi_pbcli_checksum_method_api_base@@Base+0x24a2d4>
│ │  	movs	r0, #2
│ │  	b.n	3b6b5c <uniffi_pbcli_checksum_method_api_base@@Base+0x24a2d8>
│ │  			@ <UNDEFINED> instruction: 0xff8eeaff
│ │ -	ldr	r3, [sp, #804]	@ 0x324
│ │ -			@ <UNDEFINED> instruction: 0xffce2b00
│ │ -	vqdmulh.s<illegal width 8>	<illegal reg q12.5>, q7, d2[3]
│ │ +	ldr	r3, [sp, #960]	@ 0x3c0
│ │ +			@ <UNDEFINED> instruction: 0xffce2b27
│ │ +			@ <UNDEFINED> instruction: 0xffce9c75
│ │  	vmlsl.u8	q11, d30, d16
│ │  	movs	r2, r2
│ │  	ldr	r4, [r6, #40]	@ 0x28
│ │  	movs	r2, r2
│ │  	subs	r1, r6, #1
│ │  			@ <UNDEFINED> instruction: 0xffcd6b48
│ │  	movs	r2, r2
│ │ -	ldr	r3, [sp, #644]	@ 0x284
│ │ -			@ <UNDEFINED> instruction: 0xffce2ad8
│ │ -	vqrdmulh.s<illegal width 8>	<illegal reg q12.5>, q7, d1[4]
│ │ -	vqshlu.s64	<illegal reg q8.5>, q6, #14
│ │ +	ldr	r3, [sp, #800]	@ 0x320
│ │ +			@ <UNDEFINED> instruction: 0xffce2aff
│ │ +			@ <UNDEFINED> instruction: 0xffce9d88
│ │ +	vabdl.u8	<illegal reg q8.5>, d14, d3
│ │  	vaddl.u8	q8, d14, d0
│ │  	b.n	3b7114 <uniffi_pbcli_checksum_method_api_base@@Base+0x24a890>
│ │  	movs	r1, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	movs	r0, r0
│ │  	b.n	3b71be <uniffi_pbcli_checksum_method_api_base@@Base+0x24a93a>
│ │ @@ -1081750,22 +1081750,22 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	3b739a <uniffi_pbcli_checksum_method_api_base@@Base+0x24ab16>
│ │  	strh	r6, [r0, #8]
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3b6fa2 <uniffi_pbcli_checksum_method_api_base@@Base+0x24a71e>
│ │  	asrs	r4, r7, #21
│ │  			@ <UNDEFINED> instruction: 0xebfbffa8
│ │ -			@ <UNDEFINED> instruction: 0xeaff9a5d
│ │ -			@ <UNDEFINED> instruction: 0xffce2994
│ │ -			@ <UNDEFINED> instruction: 0xffce99a1
│ │ +			@ <UNDEFINED> instruction: 0xeaff9a84
│ │ +			@ <UNDEFINED> instruction: 0xffce29bb
│ │ +	vmul.f<illegal width 8>	<illegal reg q12.5>, q15, d0[2]
│ │  	vmlsl.u8	q9, d14, d21
│ │ -	vmul.f<illegal width 8>	<illegal reg q12.5>, q14, d1[2]
│ │ -			@ <UNDEFINED> instruction: 0xffce9a79
│ │ -			@ <UNDEFINED> instruction: 0xffce29b0
│ │ -	vmull.u<illegal width 8>	<illegal reg q12.5>, d30, d1[7]
│ │ +			@ <UNDEFINED> instruction: 0xffcc99f0
│ │ +	vmlsl.u8	<illegal reg q12.5>, d30, d16
│ │ +			@ <UNDEFINED> instruction: 0xffce29d7
│ │ +			@ <UNDEFINED> instruction: 0xffce9b14
│ │  	vqrdmulh.s<illegal width 8>	q12, q15, d2[1]
│ │  	vaddl.u8	q8, d13, d0
│ │  	b.n	3b7334 <uniffi_pbcli_checksum_method_api_base@@Base+0x24aab0>
│ │  	movs	r1, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	movs	r0, r0
│ │ @@ -1081935,22 +1081935,22 @@
│ │  	movs	r0, r0
│ │  	and.w	r0, r0, r0, lsl #16
│ │  	b.n	3b754e <uniffi_pbcli_checksum_method_api_base@@Base+0x24acca>
│ │  	movs	r6, r0
│ │  	b.n	3b7152 <uniffi_pbcli_checksum_method_api_base@@Base+0x24a8ce>
│ │  	asrs	r0, r2, #20
│ │  			@ <UNDEFINED> instruction: 0xebfbffc4
│ │ -			@ <UNDEFINED> instruction: 0xeaff983d
│ │ -	vqshl.u8	q9, q10, #6
│ │ +			@ <UNDEFINED> instruction: 0xeaff9864
│ │ +	vqshl.u64	d18, d11, #14
│ │  	vqdmulh.s<illegal width 8>	q8, q7, d0[5]
│ │  	movs	r0, r0
│ │ -	bhi.n	3b6e46 <uniffi_pbcli_checksum_method_api_base@@Base+0x24a5c2>
│ │ -	vqrshrun.s16	d25, <illegal reg q4.5>, #2
│ │ -	vqshl.u64	d18, d0, #14
│ │ -	vmul.i<illegal width 8>	<illegal reg q12.5>, q15, d1[3]
│ │ +	bhi.n	3b6e94 <uniffi_pbcli_checksum_method_api_base@@Base+0x24a610>
│ │ +	vmlal.u8	<illegal reg q12.5>, d30, d0
│ │ +	vqshl.u64	d18, d23, #14
│ │ +			@ <UNDEFINED> instruction: 0xffce98f4
│ │  	vsubl.u8	q8, d30, d17
│ │  	vaddl.u8	q8, d13, d0
│ │  	b.n	3b74e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24ac5c>
│ │  	movs	r1, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	movs	r0, r0
│ │ @@ -1082168,22 +1082168,22 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	3b7766 <uniffi_pbcli_checksum_method_api_base@@Base+0x24aee2>
│ │  	strh	r3, [r2, #0]
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3b736e <uniffi_pbcli_checksum_method_api_base@@Base+0x24aaea>
│ │  	asrs	r1, r1, #18
│ │  			@ <UNDEFINED> instruction: 0xebfbffa8
│ │ -			@ <UNDEFINED> instruction: 0xeaff9669
│ │ -	vabal.u8	q9, d30, d16
│ │ -	vsli.64	<illegal reg q12.5>, <illegal reg q2.5>, #14
│ │ +			@ <UNDEFINED> instruction: 0xeaff9690
│ │ +	vmls.f<illegal width 8>	q9, q15, d3[1]
│ │ +	vsli.64	<illegal reg q12.5>, q14, #14
│ │  	vqshlu.s8	q9, <illegal reg q4.5>, #6
│ │ -	vsli.64	<illegal reg q12.5>, <illegal reg q14.5>, #12
│ │ -	vmlsl.u<illegal width 8>	<illegal reg q12.5>, d14, d1[0]
│ │ -	vsli.8	q9, q12, #6
│ │ -	vabdl.u8	<illegal reg q12.5>, d14, d17
│ │ +	vrsubhn.i16	d25, q6, q10
│ │ +	vmlsl.u<illegal width 8>	<illegal reg q12.5>, d14, d0[6]
│ │ +	vsli.64	d18, d15, #14
│ │ +			@ <UNDEFINED> instruction: 0xffce9748
│ │  			@ <UNDEFINED> instruction: 0xffce8ba3
│ │  	vaddl.u8	q8, d12, d0
│ │  	b.n	3b7700 <uniffi_pbcli_checksum_method_api_base@@Base+0x24ae7c>
│ │  	movs	r1, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	movs	r0, r0
│ │ @@ -1082353,23 +1082353,23 @@
│ │  			@ <UNDEFINED> instruction: 0xffc1eaff
│ │  	ands	r0, r0
│ │  	b.n	3b791a <uniffi_pbcli_checksum_method_api_base@@Base+0x24b096>
│ │  	movs	r6, r0
│ │  	b.n	3b751e <uniffi_pbcli_checksum_method_api_base@@Base+0x24ac9a>
│ │  	asrs	r5, r3, #16
│ │  			@ <UNDEFINED> instruction: 0xebfbffc4
│ │ -			@ <UNDEFINED> instruction: 0xeaff9435
│ │ -			@ <UNDEFINED> instruction: 0xffce236c
│ │ +			@ <UNDEFINED> instruction: 0xeaff945c
│ │ +	vrsra.u64	d18, d3, #50
│ │  			@ <UNDEFINED> instruction: 0xffce08dc
│ │  	movs	r0, r0
│ │  	ldr	r3, [r0, #40]	@ 0x28
│ │ -	vraddhn.i16	d25, <illegal reg q6.5>, <illegal reg q6.5>
│ │ -			@ <UNDEFINED> instruction: 0xffce2344
│ │ -	vabal.u8	<illegal reg q12.5>, d14, d1
│ │ -	vsubl.u8	<illegal reg q10.5>, d14, d23
│ │ +	vsri.8	d25, d20, #3
│ │ +			@ <UNDEFINED> instruction: 0xffce236b
│ │ +	vabal.u8	<illegal reg q12.5>, d14, d24
│ │ +	vmlal.u<illegal width 8>	<illegal reg q10.5>, d14, d2[3]
│ │  	vaddl.u8	q8, d14, d1
│ │  	b.n	3b794a <uniffi_pbcli_checksum_method_api_base@@Base+0x24b0c6>
│ │  	movs	r0, r0
│ │  	b.n	3b78b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b02c>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	movs	r1, r0
│ │  	b.n	3b7838 <uniffi_pbcli_checksum_method_api_base@@Base+0x24afb4>
│ │ @@ -1082589,21 +1082589,21 @@
│ │  	movs	r1, r7
│ │  	b.n	3b7b32 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b2ae>
│ │  	ldrb	r0, [r4, #28]
│ │  			@ <UNDEFINED> instruction: 0xebfc0005
│ │  	b.n	3b773a <uniffi_pbcli_checksum_method_api_base@@Base+0x24aeb6>
│ │  	asrs	r6, r2, #14
│ │  			@ <UNDEFINED> instruction: 0xebfbffab
│ │ -			@ <UNDEFINED> instruction: 0xeaff922d
│ │ -	vmla.f<illegal width 8>	q9, q7, d0[5]
│ │ -	vsubl.u8	<illegal reg q12.5>, d14, d5
│ │ +			@ <UNDEFINED> instruction: 0xeaff9254
│ │ +	vaddw.u8	q9, q15, d11
│ │ +	vsubl.u8	<illegal reg q12.5>, d14, d28
│ │  	vsubl.u8	q9, d30, d9
│ │ -	vsubl.u8	<illegal reg q12.5>, d28, d25
│ │ -			@ <UNDEFINED> instruction: 0xffce9349
│ │ -	vsra.u64	q15, q6, #50
│ │ +	vrshr.u64	<illegal reg q12.5>, q0, #52
│ │ +	vrsra.u8	<illegal reg q12.5>, q8, #2
│ │ +	vsubl.u8	q15, d14, d3
│ │  			@ <UNDEFINED> instruction: 0xffcd9c19
│ │  	vmls.i<illegal width 8>	q8, <illegal reg q6.5>, d0[3]
│ │  	movs	r0, r0
│ │  	lsrs	r4, r2, #1
│ │  	movs	r0, r0
│ │  	str	r0, [r5, #4]
│ │  	movs	r2, r2
│ │ @@ -1082819,25 +1082819,25 @@
│ │  			@ <UNDEFINED> instruction: 0xffb2eaff
│ │  	ands	r0, r0
│ │  	b.n	3b7d42 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b4be>
│ │  	movs	r7, r0
│ │  	b.n	3b7946 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b0c2>
│ │  	asrs	r3, r2, #12
│ │  			@ <UNDEFINED> instruction: 0xebfbffb2
│ │ -			@ <UNDEFINED> instruction: 0xeaff8ff1
│ │ -			@ <UNDEFINED> instruction: 0xffce1f28
│ │ +			@ <UNDEFINED> instruction: 0xeaff9018
│ │ +	vqrdmlsh.s<illegal width 8>	<illegal reg q8.5>, q7, d3[3]
│ │  	vmul.f<illegal width 8>	<illegal reg q12.5>, q15, d1[2]
│ │  	vqrdmlah.s<illegal width 8>	<illegal reg q10.5>, <illegal reg q14.5>, d0[0]
│ │  	movs	r2, r2
│ │  	ldrsh	r0, [r3, r0]
│ │  	movs	r2, r2
│ │  	ldmia	r1, {r0, r1, r5, r6, r7}
│ │  			@ <UNDEFINED> instruction: 0xffcd5e94
│ │  	movs	r2, r2
│ │ -	str	r1, [sp, #132]	@ 0x84
│ │ +	str	r1, [sp, #288]	@ 0x120
│ │  			@ <UNDEFINED> instruction: 0xffcefb0c
│ │  			@ <UNDEFINED> instruction: 0xffcc4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3b7b54 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b2d0>
│ │  	beq.n	3b765c <uniffi_pbcli_checksum_method_api_base@@Base+0x24add8>
│ │  	b.n	3b7ad8 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b254>
│ │  	movs	r0, r0
│ │ @@ -1082964,18 +1082964,18 @@
│ │  	b.n	3b7e8a <uniffi_pbcli_checksum_method_api_base@@Base+0x24b606>
│ │  	ldrb	r2, [r1, #25]
│ │  			@ <UNDEFINED> instruction: 0xebfc0007
│ │  	b.n	3b7a92 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b20e>
│ │  	beq.n	3b7784 <uniffi_pbcli_checksum_method_api_base@@Base+0x24af00>
│ │  	b.n	3b7bec <uniffi_pbcli_checksum_method_api_base@@Base+0x24b368>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r0, r2, r4, r6, r7, r9, sl, fp, pc}
│ │ -	vmull.p8	<illegal reg q8.5>, d14, d12
│ │ -	vmull.p8	q12, d30, d29
│ │ -	vqrdmulh.s<illegal width 8>	<illegal reg q8.5>, q15, d0[5]
│ │ +	ldmia.w	sp!, {r2, r3, r4, r5, r6, r7, r9, sl, fp, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffce1e33
│ │ +			@ <UNDEFINED> instruction: 0xffce8ed4
│ │ +	vmull.p8	<illegal reg q8.5>, d14, d11
│ │  			@ <UNDEFINED> instruction: 0xffce4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3b7c8c <uniffi_pbcli_checksum_method_api_base@@Base+0x24b408>
│ │  	ands	r1, r0
│ │  	b.n	3b7ab6 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b232>
│ │  	subs	r7, r1, r0
│ │  	b.n	3b7eba <uniffi_pbcli_checksum_method_api_base@@Base+0x24b636>
│ │ @@ -1083071,17 +1083071,17 @@
│ │  	b.n	3b7f82 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b6fe>
│ │  	ldrb	r4, [r1, #24]
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3b7b8a <uniffi_pbcli_checksum_method_api_base@@Base+0x24b306>
│ │  	beq.n	3b785c <uniffi_pbcli_checksum_method_api_base@@Base+0x24afd8>
│ │  	b.n	3b7ce4 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b460>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r4, r5, r7, r8, sl, fp, pc}
│ │ +	ldmia.w	sp!, {r3, r4, r6, r7, r8, sl, fp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffce1e35
│ │ -			@ <UNDEFINED> instruction: 0xffcc8dd5
│ │ +			@ <UNDEFINED> instruction: 0xffcc8dfc
│ │  			@ <UNDEFINED> instruction: 0xffce4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3b7d80 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b4fc>
│ │  	beq.n	3b78a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b024>
│ │  	b.n	3b7d04 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b480>
│ │  	str	r3, [r0, r0]
│ │  	b.n	3b7bae <uniffi_pbcli_checksum_method_api_base@@Base+0x24b32a>
│ │ @@ -1083267,16 +1083267,16 @@
│ │  	b.n	3b750e <uniffi_pbcli_checksum_method_api_base@@Base+0x24ac8a>
│ │  	movs	r7, r0
│ │  	b.n	3b7d46 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b4c2>
│ │  	vpadd.i8	q7, <illegal reg q11.5>, q13
│ │  	strb	r0, [r0, #0]
│ │  	b.n	3b7518 <uniffi_pbcli_checksum_method_api_base@@Base+0x24ac94>
│ │  			@ <UNDEFINED> instruction: 0xffabeaff
│ │ -	ldrh	r5, [r1, #36]	@ 0x24
│ │ -	vmull.u8	q12, d14, d5
│ │ +	ldrh	r4, [r6, #36]	@ 0x24
│ │ +	vmull.u8	q12, d14, d28
│ │  			@ <UNDEFINED> instruction: 0xffce4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3b7f3c <uniffi_pbcli_checksum_method_api_base@@Base+0x24b6b8>
│ │  	ands	r1, r0
│ │  	b.n	3b7d66 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b4e2>
│ │  	subs	r1, r0, r0
│ │  	b.n	3b816a <uniffi_pbcli_checksum_method_api_base@@Base+0x24b8e6>
│ │ @@ -1083443,18 +1083443,18 @@
│ │  	ldrb	r7, [r6, #20]
│ │  			@ <UNDEFINED> instruction: 0xebfc0006
│ │  	b.n	3b7ede <uniffi_pbcli_checksum_method_api_base@@Base+0x24b65a>
│ │  			@ <UNDEFINED> instruction: 0xee88ebfa
│ │  	movs	r4, r0
│ │  	b.n	3b7ee6 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b662>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r7, r9, fp, pc}
│ │ -	vqrdmlsh.s<illegal width 8>	q14, q15, d2[0]
│ │ -	vmull.u<illegal width 8>	q12, d14, d1[4]
│ │ -			@ <UNDEFINED> instruction: 0xffcecf86
│ │ +	ldmia.w	sp!, {r2, r6, r7, r9, fp, pc}
│ │ +	vqrdmlsh.s<illegal width 8>	q14, q15, d1[6]
│ │ +	vmlsl.u8	q12, d30, d8
│ │ +			@ <UNDEFINED> instruction: 0xffcecfad
│ │  			@ <UNDEFINED> instruction: 0xffce4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3b80dc <uniffi_pbcli_checksum_method_api_base@@Base+0x24b858>
│ │  	strh	r3, [r0, #0]
│ │  	b.n	3b7f06 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b682>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3b7f0a <uniffi_pbcli_checksum_method_api_base@@Base+0x24b686>
│ │ @@ -1083605,19 +1083605,19 @@
│ │  	ldrb	r0, [r3, #19]
│ │  			@ <UNDEFINED> instruction: 0xebfc0007
│ │  	b.n	3b805a <uniffi_pbcli_checksum_method_api_base@@Base+0x24b7d6>
│ │  	b.n	3b7f4c <uniffi_pbcli_checksum_method_api_base@@Base+0x24b6c8>
│ │  			@ <UNDEFINED> instruction: 0xebfa0005
│ │  	b.n	3b8062 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b7de>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r0, r5, r6, r7, fp, pc}
│ │ -	vabdl.u8	<illegal reg q14.5>, d14, d22
│ │ -			@ <UNDEFINED> instruction: 0xffcd8989
│ │ +	ldmia.w	sp!, {r3, r8, fp, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffced74d
│ │ +			@ <UNDEFINED> instruction: 0xffcd89b0
│ │  	vrsra.u8	d18, d17, #2
│ │ -			@ <UNDEFINED> instruction: 0xffcd8925
│ │ +	vmul.f<illegal width 8>	q12, <illegal reg q6.5>, d0[3]
│ │  	vmlal.u<illegal width 8>	q9, d30, d1[3]
│ │  			@ <UNDEFINED> instruction: 0xffcd4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3b8260 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b9dc>
│ │  	beq.n	3b7d68 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b4e4>
│ │  	b.n	3b81e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b960>
│ │  	str	r0, [r2, r0]
│ │ @@ -1083836,16 +1083836,16 @@
│ │  	beq.n	3b7f50 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b6cc>
│ │  	b.n	3b83b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x24bb34>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r1, r2}
│ │  	b.n	3b826a <uniffi_pbcli_checksum_method_api_base@@Base+0x24b9e6>
│ │  			@ <UNDEFINED> instruction: 0xeda5ebfa
│ │  			@ <UNDEFINED> instruction: 0xfff9eaff
│ │ -	strh	r1, [r4, #54]	@ 0x36
│ │ -	vshr.u64	<illegal reg q11.5>, <illegal reg q0.5>, #50
│ │ +	strh	r0, [r1, #56]	@ 0x38
│ │ +	vshr.u64	<illegal reg q11.5>, q12, #50
│ │  			@ <UNDEFINED> instruction: 0xffce4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3b845c <uniffi_pbcli_checksum_method_api_base@@Base+0x24bbd8>
│ │  	beq.n	3b7f64 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b6e0>
│ │  	b.n	3b83e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24bb5c>
│ │  	ands	r0, r0
│ │  	b.n	3b868a <uniffi_pbcli_checksum_method_api_base@@Base+0x24be06>
│ │ @@ -1083937,15 +1083937,15 @@
│ │  	b.n	3b874a <uniffi_pbcli_checksum_method_api_base@@Base+0x24bec6>
│ │  	str	r3, [sp, #700]	@ 0x2bc
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3b8352 <uniffi_pbcli_checksum_method_api_base@@Base+0x24bace>
│ │  	beq.n	3b8044 <uniffi_pbcli_checksum_method_api_base@@Base+0x24b7c0>
│ │  	b.n	3b84ac <uniffi_pbcli_checksum_method_api_base@@Base+0x24bc28>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r0, r2, r9, sl, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r5, r9, sl, pc}
│ │  	vsubl.u8	q15, d30, d13
│ │  			@ <UNDEFINED> instruction: 0xffce4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3b8544 <uniffi_pbcli_checksum_method_api_base@@Base+0x24bcc0>
│ │  	beq.n	3b804c <uniffi_pbcli_checksum_method_api_base@@Base+0x24b7c8>
│ │  	b.n	3b84c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x24bc44>
│ │  	str	r0, [r2, r0]
│ │ @@ -1084543,16 +1084543,16 @@
│ │  	b.n	3b8c8e <uniffi_pbcli_checksum_method_api_base@@Base+0x24c40a>
│ │  	str	r2, [sp, #376]	@ 0x178
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3b8896 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c012>
│ │  	beq.n	3b8588 <uniffi_pbcli_checksum_method_api_base@@Base+0x24bd04>
│ │  	b.n	3b89f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c16c>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r0, r6, r7, pc}
│ │ -	vsli.64	q14, q12, #14
│ │ +	ldmia.w	sp!, {r3, r5, r6, r7, pc}
│ │ +	vqshlu.s8	d28, d15, #6
│ │  			@ <UNDEFINED> instruction: 0xffce48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3b8a88 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c204>
│ │  	beq.n	3b8590 <uniffi_pbcli_checksum_method_api_base@@Base+0x24bd0c>
│ │  	b.n	3b8a0c <uniffi_pbcli_checksum_method_api_base@@Base+0x24c188>
│ │  	ands	r0, r1
│ │  	b.n	3b80ac <uniffi_pbcli_checksum_method_api_base@@Base+0x24b828>
│ │ @@ -1084744,18 +1084744,18 @@
│ │  	ldrb	r7, [r2, #9]
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3b8a5e <uniffi_pbcli_checksum_method_api_base@@Base+0x24c1da>
│ │  			@ <UNDEFINED> instruction: 0xeba8ebfa
│ │  	movs	r5, r0
│ │  	b.n	3b8a66 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c1e2>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r6, r8, r9, sl, fp, ip, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffce7fb6
│ │ -	vqrdmlah.s<illegal width 8>	<illegal reg q11.5>, q15, d1[4]
│ │ -	vqrdmlsh.s<illegal width 8>	<illegal reg q11.5>, q7, d2[3]
│ │ +	ldmia.w	sp!, {r4, r5, r6, r8, r9, sl, fp, ip, sp, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffce7fdd
│ │ +			@ <UNDEFINED> instruction: 0xffce7f08
│ │ +			@ <UNDEFINED> instruction: 0xffce7f75
│ │  	vqshrun.s16	d20, q8, #2
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3b8c5c <uniffi_pbcli_checksum_method_api_base@@Base+0x24c3d8>
│ │  	ands	r1, r0
│ │  	b.n	3b8a86 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c202>
│ │  	str	r3, [sp, #260]	@ 0x104
│ │  			@ <UNDEFINED> instruction: 0xebfb0000
│ │ @@ -1084817,17 +1084817,17 @@
│ │  	b.n	3b8f0e <uniffi_pbcli_checksum_method_api_base@@Base+0x24c68a>
│ │  	movs	r0, #0
│ │  	b.n	3b8f12 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c68e>
│ │  	ldrb	r0, [r5, #8]
│ │  			@ <UNDEFINED> instruction: 0xebfc0000
│ │  	b.n	3b8f1a <uniffi_pbcli_checksum_method_api_base@@Base+0x24c696>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r6, r9, sl, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r2, r3, r5, r6, r9, sl, fp, ip, sp, lr}
│ │  	vaddl.u8	q8, d14, d20
│ │ -			@ <UNDEFINED> instruction: 0xffcd7e1d
│ │ +	vqrdmlah.s<illegal width 8>	<illegal reg q11.5>, <illegal reg q6.5>, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffcefffc
│ │  	vqshrun.s16	d20, q8, #4
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3b8d10 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c48c>
│ │  	ands	r1, r0
│ │  	b.n	3b8b3a <uniffi_pbcli_checksum_method_api_base@@Base+0x24c2b6>
│ │  	str	r3, [sp, #88]	@ 0x58
│ │ @@ -1084890,18 +1084890,18 @@
│ │  	b.n	3b8fc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c73e>
│ │  	movs	r0, #0
│ │  	b.n	3b8fc6 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c742>
│ │  	ldrb	r3, [r7, #7]
│ │  			@ <UNDEFINED> instruction: 0xebfc0000
│ │  	b.n	3b8fce <uniffi_pbcli_checksum_method_api_base@@Base+0x24c74a>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r4, r7, r8, sl, fp, ip, sp, lr}
│ │ -	vmla.i<illegal width 8>	q15, q15, d1[7]
│ │ -	vqrdmulh.s<illegal width 8>	<illegal reg q11.5>, <illegal reg q6.5>, d1[6]
│ │ -	vmla.i<illegal width 8>	q15, q15, d1[1]
│ │ +	ldmia.w	sp!, {r3, r4, r5, r7, r8, sl, fp, ip, sp, lr}
│ │ +	vsra.u8	d30, d4, #2
│ │ +			@ <UNDEFINED> instruction: 0xffcd7d90
│ │ +	vmla.i<illegal width 8>	q15, q15, d0[7]
│ │  	vqshrun.s16	d20, q8, #3
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3b8dc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c540>
│ │  	ands	r1, r0
│ │  	b.n	3b8bee <uniffi_pbcli_checksum_method_api_base@@Base+0x24c36a>
│ │  	ldr	r0, [sp, #984]	@ 0x3d8
│ │  			@ <UNDEFINED> instruction: 0xebfb0000
│ │ @@ -1084963,17 +1084963,17 @@
│ │  	b.n	3b9076 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c7f2>
│ │  	movs	r0, #0
│ │  	b.n	3b907a <uniffi_pbcli_checksum_method_api_base@@Base+0x24c7f6>
│ │  	ldrb	r6, [r1, #7]
│ │  			@ <UNDEFINED> instruction: 0xebfc0000
│ │  	b.n	3b9082 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c7fe>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r6, r7, sl, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r2, r8, sl, fp, ip, sp, lr}
│ │  	vmull.p8	q9, d14, d28
│ │ -			@ <UNDEFINED> instruction: 0xffcd7cb5
│ │ +			@ <UNDEFINED> instruction: 0xffcd7cdc
│ │  	vmull.p8	q9, d14, d4
│ │  	vqshrun.s16	d20, q8, #3
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3b8e78 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c5f4>
│ │  	ands	r1, r0
│ │  	b.n	3b8ca2 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c41e>
│ │  	ldr	r0, [sp, #796]	@ 0x31c
│ │ @@ -1085036,18 +1085036,18 @@
│ │  	b.n	3b912a <uniffi_pbcli_checksum_method_api_base@@Base+0x24c8a6>
│ │  	movs	r0, #0
│ │  	b.n	3b912e <uniffi_pbcli_checksum_method_api_base@@Base+0x24c8aa>
│ │  	ldrb	r1, [r4, #6]
│ │  			@ <UNDEFINED> instruction: 0xebfc0000
│ │  	b.n	3b9136 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c8b2>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r5, sl, fp, ip, sp, lr}
│ │ -	vmla.f<illegal width 8>	q14, q15, d1[0]
│ │ -	vmull.u8	<illegal reg q11.5>, d14, d1
│ │ -	vsra.u64	d28, d9, #50
│ │ +	ldmia.w	sp!, {r4, r6, sl, fp, ip, sp, lr}
│ │ +	vmla.f<illegal width 8>	q14, q15, d0[6]
│ │ +	vmull.u8	<illegal reg q11.5>, d14, d24
│ │ +	vmla.f<illegal width 8>	q14, q15, d0[0]
│ │  			@ <UNDEFINED> instruction: 0xffce4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3b8f2c <uniffi_pbcli_checksum_method_api_base@@Base+0x24c6a8>
│ │  	ands	r1, r0
│ │  	b.n	3b8d56 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c4d2>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3b8d5a <uniffi_pbcli_checksum_method_api_base@@Base+0x24c4d6>
│ │ @@ -1085110,15 +1085110,15 @@
│ │  	b.n	3b91e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c95e>
│ │  	movs	r0, #0
│ │  	b.n	3b91e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c962>
│ │  	ldrb	r3, [r6, #5]
│ │  			@ <UNDEFINED> instruction: 0xebfc0000
│ │  	b.n	3b91ee <uniffi_pbcli_checksum_method_api_base@@Base+0x24c96a>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r6, r8, r9, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r4, r5, r6, r8, r9, fp, ip, sp, lr}
│ │  	vmlal.u8	<illegal reg q14.5>, d14, d12
│ │  			@ <UNDEFINED> instruction: 0xffce4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3b8fdc <uniffi_pbcli_checksum_method_api_base@@Base+0x24c758>
│ │  	beq.n	3b8ae4 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c260>
│ │  	b.n	3b8f60 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c6dc>
│ │  	movs	r0, r0
│ │ @@ -1085196,18 +1085196,18 @@
│ │  			@ <UNDEFINED> instruction: 0xebfc4000
│ │  	b.n	3b92aa <uniffi_pbcli_checksum_method_api_base@@Base+0x24ca26>
│ │  	movs	r4, r0
│ │  	b.n	3b8eae <uniffi_pbcli_checksum_method_api_base@@Base+0x24c62a>
│ │  	beq.n	3b8b80 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c2fc>
│ │  	b.n	3b9008 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c784>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r4, r5, r6, r7, r9, fp, ip, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffce0a7e
│ │ -			@ <UNDEFINED> instruction: 0xffce7a91
│ │ -	vshll.u8	q8, d14, #6
│ │ +	ldmia.w	sp!, {r3, r4, r8, r9, fp, ip, sp, lr}
│ │ +	vmlsl.u8	q8, d30, d21
│ │ +			@ <UNDEFINED> instruction: 0xffce7ab8
│ │ +	vmull.u<illegal width 8>	q8, d14, d1[1]
│ │  	vqshrun.s16	d20, q8, #2
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3b90a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c824>
│ │  	movs	r0, r0
│ │  	b.n	3b9232 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c9ae>
│ │  	movs	r5, r1
│ │  	lsrs	r0, r0, #8
│ │ @@ -1085259,17 +1085259,17 @@
│ │  	b.n	3b933a <uniffi_pbcli_checksum_method_api_base@@Base+0x24cab6>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3b933e <uniffi_pbcli_checksum_method_api_base@@Base+0x24caba>
│ │  	ldrb	r5, [r3, #4]
│ │  			@ <UNDEFINED> instruction: 0xebfc0005
│ │  	b.n	3b8f46 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c6c2>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r6, r7, r8, fp, ip, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffce09ad
│ │ -	vmlsl.u8	<illegal reg q11.5>, d14, d25
│ │ +	ldmia.w	sp!, {r5, r9, fp, ip, sp, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffce09d4
│ │ +			@ <UNDEFINED> instruction: 0xffce7a50
│ │  			@ <UNDEFINED> instruction: 0xffceff1e
│ │  	b.n	3b8e78 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c5f4>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r0, r0
│ │  	b.n	3b92c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x24ca40>
│ │  	movs	r1, r0
│ │  	lsls	r0, r4, #14
│ │ @@ -1085397,15 +1085397,15 @@
│ │  	str	r0, [sp, #404]	@ 0x194
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3b907a <uniffi_pbcli_checksum_method_api_base@@Base+0x24c7f6>
│ │  	beq.n	3b8d6c <uniffi_pbcli_checksum_method_api_base@@Base+0x24c4e8>
│ │  	b.n	3b91d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c950>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r2, r4, r5, r6, sl, fp, ip, sp}
│ │ -	vmull.u<illegal width 8>	<illegal reg q11.5>, d12, d1[7]
│ │ +			@ <UNDEFINED> instruction: 0xffcc7a94
│ │  			@ <UNDEFINED> instruction: 0xffce3bdc
│ │  	vaddl.u8	q8, d12, d0
│ │  	b.n	3b93f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x24cb70>
│ │  	movs	r1, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	movs	r0, r0
│ │ @@ -1085556,15 +1085556,15 @@
│ │  	asrs	r2, r0, #32
│ │  	asrs	r0, r4, #14
│ │  	ands	r0, r0
│ │  	asrs	r0, r0, #22
│ │  	asrs	r4, r0, #32
│ │  	asrs	r0, r0, #22
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r5, r6, r7, r8, sl, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r4, r9, sl, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcd4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3b93d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x24cb54>
│ │  	ands	r0, r0
│ │  	b.n	3b9202 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c97e>
│ │  	movs	r0, r1
│ │  	b.n	3b93c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x24cb42>
│ │ @@ -1085575,15 +1085575,15 @@
│ │  	b.n	3b9212 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c98e>
│ │  	movs	r0, #88	@ 0x58
│ │  	b.n	3b9616 <uniffi_pbcli_checksum_method_api_base@@Base+0x24cd92>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3b8ff8 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c774>
│ │  	ldr	r4, [pc, #64]	@ (3b8f1c <uniffi_pbcli_checksum_method_api_base@@Base+0x24c698>)
│ │  	ldmia.w	sp!, {r1, r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xeafdc5af
│ │ +			@ <UNDEFINED> instruction: 0xeafdc5d6
│ │  	vaddl.u8	q8, d13, d4
│ │  	b.n	3b8a28 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c1a4>
│ │  	movs	r0, r0
│ │  	b.n	3b900c <uniffi_pbcli_checksum_method_api_base@@Base+0x24c788>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	sbfx	r0, ip, #0, #17
│ │  	ldr	r4, [pc, #64]	@ (3b8f38 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c6b4>)
│ │ @@ -1085704,16 +1085704,16 @@
│ │  	b.n	3b933a <uniffi_pbcli_checksum_method_api_base@@Base+0x24cab6>
│ │  	movs	r0, #14
│ │  	b.n	3b933e <uniffi_pbcli_checksum_method_api_base@@Base+0x24caba>
│ │  	lsls	r2, r2, #2
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3b9346 <uniffi_pbcli_checksum_method_api_base@@Base+0x24cac2>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r5, r6, r7, sl, lr, pc}
│ │ -	vrsra.u8	<illegal reg q9.5>, <illegal reg q9.5>, #3
│ │ +	ldmia.w	sp!, {r1, r3, r8, sl, lr, pc}
│ │ +	vrsra.u64	d19, d10, #51
│ │  	vmls.i<illegal width 8>	q10, q7, d0[6]
│ │  	movs	r2, r2
│ │  	adds	r0, #2
│ │  	b.n	3b935a <uniffi_pbcli_checksum_method_api_base@@Base+0x24cad6>
│ │  	movs	r0, #1
│ │  	b.n	3b935e <uniffi_pbcli_checksum_method_api_base@@Base+0x24cada>
│ │  	asrs	r0, r0, #32
│ │ @@ -1085785,15 +1085785,15 @@
│ │  	b.n	3b93f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x24cb6e>
│ │  	adds	r0, #12
│ │  	b.n	3b93f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x24cb72>
│ │  	lsls	r4, r3, #2
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3b93fe <uniffi_pbcli_checksum_method_api_base@@Base+0x24cb7a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, sl, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r6, sl, lr, pc}
│ │  	vshr.u64	<illegal reg q10.5>, q3, #51
│ │  	vrsra.u64	d20, d20, #52
│ │  	movs	r2, r2
│ │  	adds	r0, #2
│ │  	b.n	3b9412 <uniffi_pbcli_checksum_method_api_base@@Base+0x24cb8e>
│ │  	movs	r0, #1
│ │  	b.n	3b9416 <uniffi_pbcli_checksum_method_api_base@@Base+0x24cb92>
│ │ @@ -1085874,15 +1085874,15 @@
│ │  	b.n	3b94ba <uniffi_pbcli_checksum_method_api_base@@Base+0x24cc36>
│ │  	movs	r0, #14
│ │  	b.n	3b94be <uniffi_pbcli_checksum_method_api_base@@Base+0x24cc3a>
│ │  	movs	r2, r6
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3b94c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x24cc42>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r5, r6, r8, r9, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r7, r8, r9, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcdaeb4
│ │  	vmlal.u<illegal width 8>	q10, d28, d0[4]
│ │  	movs	r2, r2
│ │  	adds	r0, #2
│ │  	b.n	3b94da <uniffi_pbcli_checksum_method_api_base@@Base+0x24cc56>
│ │  	movs	r0, #1
│ │  	b.n	3b94de <uniffi_pbcli_checksum_method_api_base@@Base+0x24cc5a>
│ │ @@ -1085955,16 +1085955,16 @@
│ │  	b.n	3b9572 <uniffi_pbcli_checksum_method_api_base@@Base+0x24ccee>
│ │  	adds	r0, #12
│ │  	b.n	3b9576 <uniffi_pbcli_checksum_method_api_base@@Base+0x24ccf2>
│ │  	movs	r4, r7
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3b957e <uniffi_pbcli_checksum_method_api_base@@Base+0x24ccfa>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r7, r9, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffcd03c6
│ │ +	ldmia.w	sp!, {r1, r6, r7, r9, lr, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffcd03ed
│ │  	vsubl.u8	q10, d14, d28
│ │  	movs	r2, r2
│ │  	ldr	r3, [pc, #960]	@ (3b9610 <uniffi_pbcli_checksum_method_api_base@@Base+0x24cd8c>)
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3b9770 <uniffi_pbcli_checksum_method_api_base@@Base+0x24ceec>
│ │  	beq.n	3b9278 <uniffi_pbcli_checksum_method_api_base@@Base+0x24c9f4>
│ │  	b.n	3b96f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x24ce70>
│ │ @@ -1086614,29 +1086614,29 @@
│ │  	beq.n	3b9848 <uniffi_pbcli_checksum_method_api_base@@Base+0x24cfc4>
│ │  	b.n	3b9ca8 <uniffi_pbcli_checksum_method_api_base@@Base+0x24d424>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, ip, lr}
│ │  	b.n	3b9f5a <uniffi_pbcli_checksum_method_api_base@@Base+0x24d6d6>
│ │  			@ <UNDEFINED> instruction: 0xfff8eaff
│ │  	add	r1, sp, #732	@ 0x2dc
│ │ -			@ <UNDEFINED> instruction: 0xffcd5ab0
│ │ +			@ <UNDEFINED> instruction: 0xffcd5ad7
│ │  			@ <UNDEFINED> instruction: 0xffcea92f
│ │  			@ <UNDEFINED> instruction: 0xffcd8f21
│ │  	vqshrn.u16	d18, q0, #3
│ │ -	vrsubhn.i16	d16, <illegal reg q14.5>, q6
│ │ +	vqshlu.s64	d16, d19, #13
│ │  			@ <UNDEFINED> instruction: 0xffcea7cb
│ │  			@ <UNDEFINED> instruction: 0xffcd8dbd
│ │  	vrsra.u8	<illegal reg q9.5>, <illegal reg q2.5>, #3
│ │  	vqshl.u64	q13, <illegal reg q11.5>, #12
│ │  	vqrdmulh.s<illegal width 8>	q12, <illegal reg q14.5>, d1[6]
│ │  	vqshl.u8	q13, <illegal reg q9.5>, #5
│ │  	vqrdmulh.s<illegal width 8>	q12, <illegal reg q6.5>, d1[5]
│ │  	vqshl.u64	d26, d15, #13
│ │  			@ <UNDEFINED> instruction: 0xffcd8d91
│ │ -	vrsubhn.i16	d16, <illegal reg q6.5>, q4
│ │ +	vrsubhn.i16	d16, <illegal reg q6.5>, <illegal reg q15.5>
│ │  	vshr.u64	d18, d4, #50
│ │  			@ <UNDEFINED> instruction: 0xffcc3c11
│ │  	vaddl.u8	<illegal reg q9.5>, d13, d2
│ │  	b.n	3b9baa <uniffi_pbcli_checksum_method_api_base@@Base+0x24d326>
│ │  	movs	r0, #1
│ │  	b.n	3b9bae <uniffi_pbcli_checksum_method_api_base@@Base+0x24d32a>
│ │  	asrs	r0, r0, #32
│ │ @@ -1086706,15 +1086706,15 @@
│ │  	movs	r5, r0
│ │  	b.n	3b9c46 <uniffi_pbcli_checksum_method_api_base@@Base+0x24d3c2>
│ │  	lsrs	r3, r2, #9
│ │  			@ <UNDEFINED> instruction: 0xebfb0004
│ │  	b.n	3b9c4e <uniffi_pbcli_checksum_method_api_base@@Base+0x24d3ca>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r7, r9, sl, sp, pc}
│ │ -	vabdl.u8	<illegal reg q10.5>, d29, d24
│ │ +			@ <UNDEFINED> instruction: 0xffcd57cf
│ │  	vaddl.u8	<illegal reg q9.5>, d14, d2
│ │  	b.n	3b9c5e <uniffi_pbcli_checksum_method_api_base@@Base+0x24d3da>
│ │  	movs	r0, #1
│ │  	b.n	3b9c62 <uniffi_pbcli_checksum_method_api_base@@Base+0x24d3de>
│ │  	asrs	r0, r0, #32
│ │  	b.n	3b9c66 <uniffi_pbcli_checksum_method_api_base@@Base+0x24d3e2>
│ │  	movs	r4, r0
│ │ @@ -1087086,15 +1087086,15 @@
│ │  	movs	r5, r0
│ │  	b.n	3b9fca <uniffi_pbcli_checksum_method_api_base@@Base+0x24d746>
│ │  	lsrs	r2, r6, #5
│ │  			@ <UNDEFINED> instruction: 0xebfb0004
│ │  	b.n	3b9fd2 <uniffi_pbcli_checksum_method_api_base@@Base+0x24d74e>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r1, r3, r4, r8, r9, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffcd0f57
│ │ +			@ <UNDEFINED> instruction: 0xffcd0f7e
│ │  	vaddl.u8	<illegal reg q9.5>, d14, d2
│ │  	b.n	3b9fe2 <uniffi_pbcli_checksum_method_api_base@@Base+0x24d75e>
│ │  	movs	r0, #1
│ │  	b.n	3b9fe6 <uniffi_pbcli_checksum_method_api_base@@Base+0x24d762>
│ │  	asrs	r0, r0, #32
│ │  	b.n	3b9fea <uniffi_pbcli_checksum_method_api_base@@Base+0x24d766>
│ │  	movs	r4, r0
│ │ @@ -1087238,15 +1087238,15 @@
│ │  	movs	r5, r0
│ │  	b.n	3ba132 <uniffi_pbcli_checksum_method_api_base@@Base+0x24d8ae>
│ │  	lsrs	r0, r3, #4
│ │  			@ <UNDEFINED> instruction: 0xebfb0004
│ │  	b.n	3ba13a <uniffi_pbcli_checksum_method_api_base@@Base+0x24d8b6>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r1, r4, r5, r7, r8, sp, pc}
│ │ -	vmull.p8	q8, d13, d12
│ │ +			@ <UNDEFINED> instruction: 0xffcd0e33
│ │  			@ <UNDEFINED> instruction: 0xffce4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3ba328 <uniffi_pbcli_checksum_method_api_base@@Base+0x24daa4>
│ │  	beq.n	3b9e18 <uniffi_pbcli_checksum_method_api_base@@Base+0x24d594>
│ │  	b.n	3ba2ac <uniffi_pbcli_checksum_method_api_base@@Base+0x24da28>
│ │  	movs	r0, r0
│ │  	b.n	3ba4b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x24dc32>
│ │ @@ -1087525,22 +1087525,22 @@
│ │  	vpmin.u<illegal width 64>	q15, <illegal reg q10.5>, <illegal reg q15.5>
│ │  	add	r1, pc, #140	@ (adr r1, 3ba10c <uniffi_pbcli_checksum_method_api_base@@Base+0x24d888>)
│ │  	vaddw.u8	<illegal reg q11.5>, <illegal reg q14.5>, d25
│ │  			@ <UNDEFINED> instruction: 0xffcda9dd
│ │  			@ <UNDEFINED> instruction: 0xffcc4b78
│ │  			@ <UNDEFINED> instruction: 0xffcc9f7f
│ │  	vaddl.u8	<illegal reg q11.5>, d13, d5
│ │ -			@ <UNDEFINED> instruction: 0xffcd2c90
│ │ +			@ <UNDEFINED> instruction: 0xffcd2cb7
│ │  			@ <UNDEFINED> instruction: 0xffce9f53
│ │  			@ <UNDEFINED> instruction: 0xffcd6fd9
│ │  			@ <UNDEFINED> instruction: 0xffcd9efb
│ │  			@ <UNDEFINED> instruction: 0xffcd6f81
│ │  			@ <UNDEFINED> instruction: 0xffcd9f27
│ │  			@ <UNDEFINED> instruction: 0xffcd6fad
│ │ -			@ <UNDEFINED> instruction: 0xffcdfdbc
│ │ +	vqrdmulh.s<illegal width 8>	<illegal reg q15.5>, <illegal reg q14.5>, d3[4]
│ │  	vsra.u64	q11, <illegal reg q5.5>, #51
│ │  	vrsubhn.i16	d30, <illegal reg q14.5>, <illegal reg q3.5>
│ │  			@ <UNDEFINED> instruction: 0xffcb2d3a
│ │  			@ <UNDEFINED> instruction: 0xffcd4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3ba5e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x24dd60>
│ │  	beq.n	3ba104 <uniffi_pbcli_checksum_method_api_base@@Base+0x24d880>
│ │ @@ -1087850,28 +1087850,28 @@
│ │  	ldrh	r5, [r3, #22]
│ │  			@ <UNDEFINED> instruction: 0xebfd0006
│ │  	b.n	3ba69a <uniffi_pbcli_checksum_method_api_base@@Base+0x24de16>
│ │  	beq.n	3ba394 <uniffi_pbcli_checksum_method_api_base@@Base+0x24db10>
│ │  	b.n	3ba7f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x24df70>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r1, r3, r4, r5, r7, sp, lr}
│ │ -	vsubw.u8	<illegal reg q10.5>, q14, d22
│ │ -			@ <UNDEFINED> instruction: 0xffcecfa2
│ │ +			@ <UNDEFINED> instruction: 0xffcc53cd
│ │ +	vqrdmlsh.s<illegal width 8>	q14, q15, d1[2]
│ │  	vqrdmlah.s<illegal width 8>	<illegal reg q13.5>, <illegal reg q6.5>, d3[7]
│ │  	vshr.u8	q11, <illegal reg q2.5>, #4
│ │  			@ <UNDEFINED> instruction: 0xffcca34a
│ │  			@ <UNDEFINED> instruction: 0xffcc6d78
│ │ -			@ <UNDEFINED> instruction: 0xffcd4da3
│ │ -			@ <UNDEFINED> instruction: 0xffce9998
│ │ -	vrshr.u8	q15, q1, #2
│ │ +	vqrdmulh.s<illegal width 8>	q10, <illegal reg q14.5>, d2[2]
│ │ +			@ <UNDEFINED> instruction: 0xffce99bf
│ │ +	vrshr.u8	q15, <illegal reg q12.5>, #2
│ │  	vmull.u8	<illegal reg q12.5>, d13, d7
│ │  			@ <UNDEFINED> instruction: 0xffcd0d16
│ │  	vmull.p8	q12, d28, d15
│ │  			@ <UNDEFINED> instruction: 0xffcc27c2
│ │ -	vsubw.u8	<illegal reg q10.5>, q6, d18
│ │ +			@ <UNDEFINED> instruction: 0xffcc5349
│ │  	vqshrun.s16	d20, q8, #2
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3ba8c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24e03c>
│ │  	ands	r0, r0
│ │  	b.n	3ba6ea <uniffi_pbcli_checksum_method_api_base@@Base+0x24de66>
│ │  	movs	r4, r3
│ │  	b.n	3b9ed0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24d64c>
│ │ @@ -1088035,22 +1088035,22 @@
│ │  			@ <UNDEFINED> instruction: 0xebfbffb5
│ │  			@ <UNDEFINED> instruction: 0xeaff5000
│ │  	b.n	3bac4a <uniffi_pbcli_checksum_method_api_base@@Base+0x24e3c6>
│ │  	movs	r5, r0
│ │  	b.n	3ba84e <uniffi_pbcli_checksum_method_api_base@@Base+0x24dfca>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r1, r3, r8, r9, sl, fp, ip, sp, pc}
│ │ -	vrsra.u8	d22, d8, #2
│ │ -			@ <UNDEFINED> instruction: 0xffcedb4f
│ │ +	vrsra.u8	d22, d31, #2
│ │ +			@ <UNDEFINED> instruction: 0xffcedb76
│ │  			@ <UNDEFINED> instruction: 0xffcd3d18
│ │ -	vshr.u8	d25, d23, #4
│ │ -	vshr.u8	d27, d19, #2
│ │ +	vshr.u8	<illegal reg q12.5>, q7, #4
│ │ +	vshr.u8	<illegal reg q13.5>, q5, #2
│ │  	vmull.u8	<illegal reg q9.5>, d29, d30
│ │  			@ <UNDEFINED> instruction: 0xffcc9abd
│ │ -	vraddhn.i16	d19, <illegal reg q14.5>, <illegal reg q5.5>
│ │ +	vsri.64	d19, d18, #51
│ │  			@ <UNDEFINED> instruction: 0xffce4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3baa58 <uniffi_pbcli_checksum_method_api_base@@Base+0x24e1d4>
│ │  	beq.n	3ba548 <uniffi_pbcli_checksum_method_api_base@@Base+0x24dcc4>
│ │  	b.n	3ba9dc <uniffi_pbcli_checksum_method_api_base@@Base+0x24e158>
│ │  	str	r2, [r0, #0]
│ │  	b.n	3ba886 <uniffi_pbcli_checksum_method_api_base@@Base+0x24e002>
│ │ @@ -1088172,21 +1088172,21 @@
│ │  	b.n	3baad0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24e24c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3bad82 <uniffi_pbcli_checksum_method_api_base@@Base+0x24e4fe>
│ │  	beq.n	3ba67c <uniffi_pbcli_checksum_method_api_base@@Base+0x24ddf8>
│ │  	b.n	3baadc <uniffi_pbcli_checksum_method_api_base@@Base+0x24e258>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r3, r5, r6, r9, sp, pc}
│ │ -	vsra.u8	<illegal reg q10.5>, q9, #2
│ │ -			@ <UNDEFINED> instruction: 0xffce4f2a
│ │ -	vqrdmlsh.s<illegal width 8>	<illegal reg q14.5>, q15, d2[1]
│ │ +	ldmia.w	sp!, {r2, r4, r7, r9, sp, pc}
│ │ +	vsra.u64	d21, d9, #50
│ │ +			@ <UNDEFINED> instruction: 0xffce4f51
│ │ +	vqrdmlsh.s<illegal width 8>	<illegal reg q14.5>, q15, d1[7]
│ │  	vqshl.u64	d27, d20, #13
│ │ -	vqshlu.s8	<illegal reg q12.5>, q12, #4
│ │ -			@ <UNDEFINED> instruction: 0xffcedf5a
│ │ +	vqshlu.s64	d25, d15, #12
│ │ +			@ <UNDEFINED> instruction: 0xffcedf81
│ │  			@ <UNDEFINED> instruction: 0xffcd4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3bab88 <uniffi_pbcli_checksum_method_api_base@@Base+0x24e304>
│ │  	beq.n	3ba6c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x24de44>
│ │  	b.n	3bab0c <uniffi_pbcli_checksum_method_api_base@@Base+0x24e288>
│ │  	movs	r0, r0
│ │  	b.n	3bad16 <uniffi_pbcli_checksum_method_api_base@@Base+0x24e492>
│ │ @@ -1088940,42 +1088940,42 @@
│ │  	str	r0, [sp, #112]	@ 0x70
│ │  	b.n	3ba834 <uniffi_pbcli_checksum_method_api_base@@Base+0x24dfb0>
│ │  			@ <UNDEFINED> instruction: 0xff86eaff
│ │  	str	r1, [r0, #0]
│ │  	b.n	3bb442 <uniffi_pbcli_checksum_method_api_base@@Base+0x24ebbe>
│ │  			@ <UNDEFINED> instruction: 0xff84eaff
│ │  	ldr	r0, [sp, #732]	@ 0x2dc
│ │ -	vsli.8	d26, d20, #5
│ │ +	vsli.8	q13, <illegal reg q5.5>, #5
│ │  	vqshrun.s16	d25, <illegal reg q15.5>, #2
│ │ -	vsri.64	d26, d28, #51
│ │ +	vmls.i<illegal width 8>	q13, <illegal reg q14.5>, d3[4]
│ │  			@ <UNDEFINED> instruction: 0xffce17e4
│ │  	vsli.8	<illegal reg q12.5>, <illegal reg q9.5>, #5
│ │ -	vsra.u64	q13, q8, #51
│ │ -	vabal.u8	<illegal reg q15.5>, d30, d0
│ │ +	vrshr.u8	d26, d7, #3
│ │ +	vabal.u8	<illegal reg q15.5>, d30, d23
│ │  	vabal.u8	<illegal reg q15.5>, d29, d29
│ │  	vsli.8	d25, d27, #4
│ │ -	vsra.u64	d26, d24, #51
│ │ -	vsri.64	<illegal reg q15.5>, q6, #50
│ │ +	vsra.u64	q13, <illegal reg q7.5>, #51
│ │ +	vabal.u8	<illegal reg q15.5>, d14, d3
│ │  	vqrdmlsh.s<illegal width 8>	q8, <illegal reg q6.5>, d0[6]
│ │  	vmull.p8	q15, d28, d18
│ │  	vqshlu.s8	<illegal reg q9.5>, <illegal reg q6.5>, #3
│ │  	vrshr.u8	q9, q0, #3
│ │  	vrsubhn.i16	d19, <illegal reg q6.5>, <illegal reg q12.5>
│ │  	vsri.64	q11, <illegal reg q13.5>, #51
│ │  	vqrshrun.s16	d21, <illegal reg q14.5>, #3
│ │ -	vrshr.u8	<illegal reg q13.5>, <illegal reg q2.5>, #3
│ │ +	vrshr.u8	<illegal reg q13.5>, q14, #3
│ │  	vqshl.u64	d24, d23, #13
│ │  	vmlsl.u<illegal width 8>	<illegal reg q8.5>, d12, d3[3]
│ │  	vsli.64	<illegal reg q13.5>, <illegal reg q5.5>, #13
│ │  	vsri.64	d30, d18, #52
│ │  	vmls.f<illegal width 8>	<illegal reg q13.5>, q6, d3[0]
│ │ -	vrsra.u8	q11, <illegal reg q3.5>, #4
│ │ +	vrsra.u8	q11, q15, #4
│ │  	vqrdmlah.s<illegal width 8>	<illegal reg q9.5>, q15, d2[6]
│ │  	vmlal.u<illegal width 8>	<illegal reg q12.5>, d28, d3[6]
│ │ -	vmla.f<illegal width 8>	<illegal reg q13.5>, <illegal reg q6.5>, d0[1]
│ │ +	vmla.f<illegal width 8>	<illegal reg q13.5>, <illegal reg q6.5>, d3[6]
│ │  	vqshl.u8	d18, d19, #5
│ │  	vsri.64	d27, d1, #51
│ │  	vsri.8	d25, d11, #4
│ │  			@ <UNDEFINED> instruction: 0xffcd4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3bb2a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x24ea24>
│ │  	movs	r0, r0
│ │ @@ -1089160,15 +1089160,15 @@
│ │  	str	r0, [sp, #716]	@ 0x2cc
│ │  	vsri.8	<illegal reg q13.5>, q1, #3
│ │  			@ <UNDEFINED> instruction: 0xffce4c1f
│ │  	vqshrn.u16	d16, q2, #4
│ │  	vmlal.u8	q15, d12, d10
│ │  	vaddw.u8	<illegal reg q12.5>, <illegal reg q5.5>, d31
│ │  	vmls.i<illegal width 8>	<illegal reg q13.5>, <illegal reg q14.5>, d2[3]
│ │ -			@ <UNDEFINED> instruction: 0xffce9d1b
│ │ +	vqrdmulh.s<illegal width 8>	<illegal reg q12.5>, q7, d2[0]
│ │  			@ <UNDEFINED> instruction: 0xffce4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3bb45c <uniffi_pbcli_checksum_method_api_base@@Base+0x24ebd8>
│ │  	beq.n	3baf9c <uniffi_pbcli_checksum_method_api_base@@Base+0x24e718>
│ │  	b.n	3bb3e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24eb5c>
│ │  	strh	r0, [r0, #0]
│ │  	b.n	3bb68a <uniffi_pbcli_checksum_method_api_base@@Base+0x24ee06>
│ │ @@ -1089877,49 +1089877,49 @@
│ │  	b.n	3bb89e <uniffi_pbcli_checksum_method_api_base@@Base+0x24f01a>
│ │  	lsrs	r1, r5, #4
│ │  			@ <UNDEFINED> instruction: 0xebfb0001
│ │  	b.n	3bbc06 <uniffi_pbcli_checksum_method_api_base@@Base+0x24f382>
│ │  	vpmin.u16	q5, <illegal reg q8.5>, <illegal reg q15.5>
│ │  	vpmin.u16	q7, q10, <illegal reg q15.5>
│ │  	ldrh	r7, [r1, #62]	@ 0x3e
│ │ -			@ <UNDEFINED> instruction: 0xffcdfc1c
│ │ +	vqdmulh.s<illegal width 8>	<illegal reg q15.5>, <illegal reg q6.5>, d3[0]
│ │  	vqrdmlsh.s<illegal width 8>	q12, <illegal reg q6.5>, d3[4]
│ │ -			@ <UNDEFINED> instruction: 0xffcdfbb0
│ │ -	vmull.u8	q15, d29, d0
│ │ -	vrsra.u8	d18, d30, #3
│ │ +			@ <UNDEFINED> instruction: 0xffcdfbd7
│ │ +	vmull.u8	q15, d29, d23
│ │ +			@ <UNDEFINED> instruction: 0xffcd2365
│ │  	vmlal.u<illegal width 8>	<illegal reg q11.5>, d30, d2[0]
│ │  	vsubl.u8	<illegal reg q13.5>, d28, d30
│ │  			@ <UNDEFINED> instruction: 0xffce0ef0
│ │  	vmull.u8	q9, d13, d21
│ │  	vrshr.u64	d20, d9, #51
│ │  			@ <UNDEFINED> instruction: 0xffcdef0b
│ │ -			@ <UNDEFINED> instruction: 0xffccebe4
│ │ +	vmull.u8	q15, d12, d11
│ │  			@ <UNDEFINED> instruction: 0xffcddfbc
│ │  	vmul.i<illegal width 8>	<illegal reg q10.5>, <illegal reg q13.5>, d2[4]
│ │  	vshr.u8	<illegal reg q14.5>, <illegal reg q13.5>, #4
│ │ -	vmul.i<illegal width 8>	<illegal reg q9.5>, q6, d0[1]
│ │ +	vmul.i<illegal width 8>	<illegal reg q9.5>, q6, d3[6]
│ │  	vqrshrun.s16	d21, q9, #2
│ │  	vqshl.u64	<illegal reg q10.5>, q2, #12
│ │  	vqrdmlah.s<illegal width 8>	<illegal reg q14.5>, <illegal reg q14.5>, d1[3]
│ │  			@ <UNDEFINED> instruction: 0xffcbaa79
│ │  	vqrdmlah.s<illegal width 8>	<illegal reg q14.5>, q7, d2[1]
│ │ -	vqshrn.u16	d19, <illegal reg q5.5>, #5
│ │ +	vmul.f<illegal width 8>	<illegal reg q9.5>, <illegal reg q5.5>, d2[0]
│ │  			@ <UNDEFINED> instruction: 0xffce3f5f
│ │ -			@ <UNDEFINED> instruction: 0xffcd3c37
│ │ -	vmla.i<illegal width 8>	q10, q7, d2[2]
│ │ +			@ <UNDEFINED> instruction: 0xffcd3c5e
│ │ +	vshr.u8	q10, <illegal reg q8.5>, #2
│ │  			@ <UNDEFINED> instruction: 0xffce8b83
│ │  			@ <UNDEFINED> instruction: 0xffcc2cfe
│ │ -			@ <UNDEFINED> instruction: 0xffcc3ff6
│ │ +	vshr.u8	d20, d13, #4
│ │  			@ <UNDEFINED> instruction: 0xffce8b2b
│ │  	vsri.8	<illegal reg q8.5>, q12, #4
│ │ -	vsri.64	d27, d28, #52
│ │ -			@ <UNDEFINED> instruction: 0xffcd3f96
│ │ +	vmls.i<illegal width 8>	<illegal reg q13.5>, q14, d3[4]
│ │ +			@ <UNDEFINED> instruction: 0xffcd3fbd
│ │  	vmull.u<illegal width 8>	q12, d30, d3[3]
│ │  	vmla.f<illegal width 8>	q15, q14, d2[1]
│ │ -			@ <UNDEFINED> instruction: 0xffcb3f5e
│ │ +			@ <UNDEFINED> instruction: 0xffcb3f85
│ │  			@ <UNDEFINED> instruction: 0xffce8a97
│ │  	vaddl.u8	q8, d12, d4
│ │  	b.n	3bbb06 <uniffi_pbcli_checksum_method_api_base@@Base+0x24f282>
│ │  	asrs	r4, r0, #32
│ │  	b.n	3bb02a <uniffi_pbcli_checksum_method_api_base@@Base+0x24e7a6>
│ │  	movs	r0, r0
│ │  	b.n	3bbcb0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24f42c>
│ │ @@ -1091160,21 +1091160,21 @@
│ │  	b.n	3bc7a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x24ff22>
│ │  	movs	r4, r4
│ │  	b.n	3bbc12 <uniffi_pbcli_checksum_method_api_base@@Base+0x24f38e>
│ │  	str	r1, [r0, #0]
│ │  	asrs	r0, r4, #14
│ │  			@ <UNDEFINED> instruction: 0xffe0eaff
│ │  	mov	r5, lr
│ │ -	vabdl.u8	<illegal reg q12.5>, d28, d23
│ │ +			@ <UNDEFINED> instruction: 0xffcc97ce
│ │  	vmull.u8	<illegal reg q10.5>, d14, d29
│ │ -	vmls.i<illegal width 8>	q8, q6, d2[0]
│ │ +	vmls.i<illegal width 8>	q8, q6, d1[6]
│ │  			@ <UNDEFINED> instruction: 0xffce69f3
│ │ -	vsli.8	<illegal reg q12.5>, <illegal reg q10.5>, #4
│ │ +	vsli.64	d25, d12, #12
│ │  	vsubw.u8	q10, <illegal reg q14.5>, d23
│ │ -			@ <UNDEFINED> instruction: 0xffcd0d82
│ │ +			@ <UNDEFINED> instruction: 0xffcd0da9
│ │  	vqrshrn.u16	d22, <illegal reg q11.5>, #2
│ │  	vmlsl.u8	<illegal reg q10.5>, d12, d1
│ │  	vqshrn.u16	d21, q12, #4
│ │  			@ <UNDEFINED> instruction: 0xffcd68db
│ │  	vmul.i<illegal width 8>	q11, q6, d3[0]
│ │  	vaddl.u8	q8, d12, d4
│ │  	b.n	3bbc88 <uniffi_pbcli_checksum_method_api_base@@Base+0x24f404>
│ │ @@ -1091334,22 +1091334,22 @@
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, lr}
│ │  	b.n	3bc9e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x25015e>
│ │  	movs	r4, r0
│ │  	b.n	3bc5e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x24fd62>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r5, r8, r9, lr}
│ │ -	vrshr.u64	<illegal reg q9.5>, q15, #52
│ │ -	vmls.i<illegal width 8>	<illegal reg q12.5>, q7, d3[6]
│ │ +	vsubw.u8	<illegal reg q9.5>, q6, d21
│ │ +	vsri.64	d25, d2, #50
│ │  			@ <UNDEFINED> instruction: 0xffce58f9
│ │ -	vrshr.u64	d19, d22, #52
│ │ +	vrshr.u64	<illegal reg q9.5>, <illegal reg q6.5>, #52
│ │  	vaddw.u8	q10, q7, d11
│ │ -	vmull.u<illegal width 8>	q8, d29, d2[7]
│ │ +			@ <UNDEFINED> instruction: 0xffcd0b15
│ │  	vqshl.u8	d21, d4, #6
│ │ -	vsubl.u8	<illegal reg q9.5>, d13, d26
│ │ +	vrshr.u8	<illegal reg q9.5>, <illegal reg q0.5>, #3
│ │  	vaddl.u8	q8, d14, d4
│ │  	b.n	3bbe10 <uniffi_pbcli_checksum_method_api_base@@Base+0x24f58c>
│ │  	movs	r0, r0
│ │  	b.n	3bc3f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x24fb70>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	stmia	r2!, {r2, r5, r7}
│ │  	movs	r0, r2
│ │ @@ -1091777,15 +1091777,15 @@
│ │  	adds	r2, #103	@ 0x67
│ │  	b.n	3bcc96 <uniffi_pbcli_checksum_method_api_base@@Base+0x250412>
│ │  	movs	r0, #2
│ │  	b.n	3bc7b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x24ff34>
│ │  	strh	r6, [r0, #56]	@ 0x38
│ │  			@ <UNDEFINED> instruction: 0xebfdffc8
│ │  			@ <UNDEFINED> instruction: 0xeaffaa83
│ │ -	vqrdmlsh.s<illegal width 8>	q11, q6, d1[0]
│ │ +	vqrdmlsh.s<illegal width 8>	q11, q6, d0[6]
│ │  	vshll.u8	q13, d23, #6
│ │  	vmull.u<illegal width 8>	q10, d28, d3[2]
│ │  			@ <UNDEFINED> instruction: 0xffcca9db
│ │  	vmul.f<illegal width 8>	q13, q6, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffcc4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3bcbdc <uniffi_pbcli_checksum_method_api_base@@Base+0x250358>
│ │ @@ -1091916,17 +1091916,17 @@
│ │  	b.n	3bcf26 <uniffi_pbcli_checksum_method_api_base@@Base+0x2506a2>
│ │  	str	r0, [r1, r0]
│ │  	b.n	3bc2f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x24fa72>
│ │  	movs	r4, r0
│ │  	b.n	3bcb2e <uniffi_pbcli_checksum_method_api_base@@Base+0x2502aa>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r6, fp, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffcc6d33
│ │ +			@ <UNDEFINED> instruction: 0xffcc6d5a
│ │  			@ <UNDEFINED> instruction: 0xffcea89f
│ │ -			@ <UNDEFINED> instruction: 0xffcc6d73
│ │ +			@ <UNDEFINED> instruction: 0xffcc6d9a
│ │  	vqshrun.s16	d20, q8, #2
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3bcd24 <uniffi_pbcli_checksum_method_api_base@@Base+0x2504a0>
│ │  	ands	r0, r0
│ │  	b.n	3bcb4e <uniffi_pbcli_checksum_method_api_base@@Base+0x2502ca>
│ │  	movs	r4, r0
│ │  	b.n	3bc332 <uniffi_pbcli_checksum_method_api_base@@Base+0x24faae>
│ │ @@ -1092421,19 +1092421,19 @@
│ │  	beq.n	3bcc90 <uniffi_pbcli_checksum_method_api_base@@Base+0x25040c>
│ │  	b.n	3bd108 <uniffi_pbcli_checksum_method_api_base@@Base+0x250884>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r1, r3, r4, r5, r7, r9, sl, ip, lr, pc}
│ │  	vshll.u8	<illegal reg q9.5>, d9, #3
│ │  	vmlal.u8	q11, d12, d31
│ │  			@ <UNDEFINED> instruction: 0xffcc4fd1
│ │ -			@ <UNDEFINED> instruction: 0xffccf7e6
│ │ +	vmlal.u8	<illegal reg q15.5>, d12, d13
│ │  	vsri.8	d26, d23, #3
│ │  	vmls.i<illegal width 8>	<illegal reg q11.5>, q6, d2[2]
│ │  			@ <UNDEFINED> instruction: 0xffcc374b
│ │ -	vaddw.u8	q8, <illegal reg q6.5>, d22
│ │ +	vmla.f<illegal width 8>	q8, <illegal reg q6.5>, d1[3]
│ │  	vrsra.u64	d26, d15, #50
│ │  	vaddl.u8	q8, d12, d4
│ │  	b.n	3bc7e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x24ff5c>
│ │  	movs	r0, r0
│ │  	b.n	3bcdc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x250540>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	cbnz	r4, 3bccd4 <uniffi_pbcli_checksum_method_api_base@@Base+0x250450>
│ │ @@ -1092595,20 +1092595,20 @@
│ │  	ldmia.w	sp!, {r0, lr}
│ │  	b.n	3bd546 <uniffi_pbcli_checksum_method_api_base@@Base+0x250cc2>
│ │  	movs	r4, r0
│ │  	b.n	3bd14a <uniffi_pbcli_checksum_method_api_base@@Base+0x2508c6>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r5, sl, ip, lr, pc}
│ │  	vabdl.u8	<illegal reg q9.5>, d27, d5
│ │ -			@ <UNDEFINED> instruction: 0xffcc2762
│ │ +	vabdl.u8	q9, d28, d9
│ │  	vsli.64	d22, d19, #14
│ │  			@ <UNDEFINED> instruction: 0xffcc4d5d
│ │ -	vqshl.u8	d18, d10, #4
│ │ +			@ <UNDEFINED> instruction: 0xffcc2741
│ │  	vmls.f<illegal width 8>	<illegal reg q9.5>, q7, d3[7]
│ │ -			@ <UNDEFINED> instruction: 0xffcdff52
│ │ +			@ <UNDEFINED> instruction: 0xffcdff79
│ │  	vaddl.u8	q8, d13, d4
│ │  	b.n	3bc970 <uniffi_pbcli_checksum_method_api_base@@Base+0x2500ec>
│ │  	movs	r0, r0
│ │  	b.n	3bcf54 <uniffi_pbcli_checksum_method_api_base@@Base+0x2506d0>
│ │  	vrhadd.u16	d14, d14, d31
│ │  			@ <UNDEFINED> instruction: 0xb8a0
│ │  	movs	r0, r2
│ │ @@ -1092808,15 +1092808,15 @@
│ │  	ands	r0, r0
│ │  	asrs	r0, r4, #6
│ │  	asrs	r0, r0, #32
│ │  	asrs	r0, r0, #22
│ │  	movs	r4, r0
│ │  	b.n	3bd34a <uniffi_pbcli_checksum_method_api_base@@Base+0x250ac6>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, sl, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r3, r5, sl, fp, ip, sp, lr}
│ │  	vshr.u64	d16, d17, #50
│ │  	and.w	r8, r0, r0, ror #19
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3bd538 <uniffi_pbcli_checksum_method_api_base@@Base+0x250cb4>
│ │  	beq.n	3bd030 <uniffi_pbcli_checksum_method_api_base@@Base+0x2507ac>
│ │  	b.n	3bd4bc <uniffi_pbcli_checksum_method_api_base@@Base+0x250c38>
│ │  	str	r3, [r0, r0]
│ │ @@ -1092917,16 +1092917,16 @@
│ │  	b.n	3bcc28 <uniffi_pbcli_checksum_method_api_base@@Base+0x2503a4>
│ │  	bics	r2, r7
│ │  			@ <UNDEFINED> instruction: 0xebfc0001
│ │  	b.n	3bd846 <uniffi_pbcli_checksum_method_api_base@@Base+0x250fc2>
│ │  	ands	r0, r1
│ │  	b.n	3bcc14 <uniffi_pbcli_checksum_method_api_base@@Base+0x250390>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r6, r8, r9, fp, ip, sp, lr}
│ │ -	vqshlu.s8	<illegal reg q9.5>, q9, #6
│ │ +	ldmia.w	sp!, {r1, r4, r5, r6, r8, r9, fp, ip, sp, lr}
│ │ +	vqshlu.s64	d19, d9, #14
│ │  			@ <UNDEFINED> instruction: 0xffce4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3bd638 <uniffi_pbcli_checksum_method_api_base@@Base+0x250db4>
│ │  	ands	r0, r0
│ │  	b.n	3bd462 <uniffi_pbcli_checksum_method_api_base@@Base+0x250bde>
│ │  	movs	r4, r0
│ │  	b.n	3bcc46 <uniffi_pbcli_checksum_method_api_base@@Base+0x2503c2>
│ │ @@ -1092940,15 +1092940,15 @@
│ │  	b.n	3bd47a <uniffi_pbcli_checksum_method_api_base@@Base+0x250bf6>
│ │  	movs	r0, #148	@ 0x94
│ │  	b.n	3bd87e <uniffi_pbcli_checksum_method_api_base@@Base+0x250ffa>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3bd260 <uniffi_pbcli_checksum_method_api_base@@Base+0x2509dc>
│ │  	ldr	r4, [pc, #64]	@ (3bd184 <uniffi_pbcli_checksum_method_api_base@@Base+0x250900>)
│ │  	ldmia.w	sp!, {r5, r6, r8, r9, sl, fp, ip, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xeafd7ab3
│ │ +			@ <UNDEFINED> instruction: 0xeafd7ada
│ │  			@ <UNDEFINED> instruction: 0xffce4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3bd670 <uniffi_pbcli_checksum_method_api_base@@Base+0x250dec>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3bd49a <uniffi_pbcli_checksum_method_api_base@@Base+0x250c16>
│ │  	ldr	r1, [pc, #736]	@ (3bd43c <uniffi_pbcli_checksum_method_api_base@@Base+0x250bb8>)
│ │  			@ <UNDEFINED> instruction: 0xebff4000
│ │ @@ -1093061,20 +1093061,20 @@
│ │  	b.n	3bd592 <uniffi_pbcli_checksum_method_api_base@@Base+0x250d0e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3bd374 <uniffi_pbcli_checksum_method_api_base@@Base+0x250af0>
│ │  	ldrb	r4, [r3, #28]
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3bd59e <uniffi_pbcli_checksum_method_api_base@@Base+0x250d1a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r5, r6, r9, fp, ip, sp, lr}
│ │ -	vmlsl.u8	<illegal reg q11.5>, d14, d11
│ │ -	vshll.u8	<illegal reg q11.5>, d21, #6
│ │ -			@ <UNDEFINED> instruction: 0xffce79d3
│ │ -			@ <UNDEFINED> instruction: 0xffce79fd
│ │ -			@ <UNDEFINED> instruction: 0xffce799f
│ │ +	ldmia.w	sp!, {r1, r5, r7, r9, fp, ip, sp, lr}
│ │ +	vshll.u8	<illegal reg q11.5>, d18, #6
│ │ +			@ <UNDEFINED> instruction: 0xffce7a5c
│ │ +			@ <UNDEFINED> instruction: 0xffce79fa
│ │ +	vmlsl.u8	<illegal reg q11.5>, d14, d20
│ │ +	vmul.f<illegal width 8>	<illegal reg q11.5>, q15, d2[1]
│ │  	vaddl.u8	q8, d14, d1
│ │  	b.n	3bd9be <uniffi_pbcli_checksum_method_api_base@@Base+0x25113a>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r4, r0
│ │  	b.n	3bcdc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x250540>
│ │  	movs	r0, r0
│ │  	b.n	3bd3a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x250b24>
│ │ @@ -1093106,15 +1093106,15 @@
│ │  	ands	r0, r0
│ │  	asrs	r0, r4, #6
│ │  	asrs	r0, r0, #32
│ │  	asrs	r0, r0, #22
│ │  	movs	r4, r0
│ │  	b.n	3bd612 <uniffi_pbcli_checksum_method_api_base@@Base+0x250d8e>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r5, r8, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r5, r6, r8, fp, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffceffff
│ │  			@ <UNDEFINED> instruction: 0xeaff4830
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3bd800 <uniffi_pbcli_checksum_method_api_base@@Base+0x250f7c>
│ │  	ands	r1, r0
│ │  	b.n	3bd62a <uniffi_pbcli_checksum_method_api_base@@Base+0x250da6>
│ │  	str	r0, [r0, r0]
│ │ @@ -1093176,24 +1093176,24 @@
│ │  	b.n	3bce98 <uniffi_pbcli_checksum_method_api_base@@Base+0x250614>
│ │  	orrs	r6, r3
│ │  			@ <UNDEFINED> instruction: 0xebfc0001
│ │  	b.n	3bdab6 <uniffi_pbcli_checksum_method_api_base@@Base+0x251232>
│ │  	ands	r4, r0
│ │  	b.n	3bce84 <uniffi_pbcli_checksum_method_api_base@@Base+0x250600>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r6, r7, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r8, fp, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffce9cf2
│ │  	vaddl.u8	<illegal reg q8.5>, d12, d0
│ │  	b.n	3bd6ca <uniffi_pbcli_checksum_method_api_base@@Base+0x250e46>
│ │  	movs	r4, r0
│ │  	b.n	3bcecc <uniffi_pbcli_checksum_method_api_base@@Base+0x250648>
│ │  	movs	r0, r0
│ │  	b.n	3bd4b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x250c2c>
│ │  	lsls	r6, r0, #4
│ │ -	and.w	ip, r0, r4, lsr #30
│ │ +	and.w	ip, r0, fp, ror #30
│ │  			@ <UNDEFINED> instruction: 0xffce4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3bd8bc <uniffi_pbcli_checksum_method_api_base@@Base+0x251038>
│ │  	ands	r2, r0
│ │  	b.n	3bd6e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x250e62>
│ │  	str	r1, [r0, #0]
│ │  	b.n	3bd6ea <uniffi_pbcli_checksum_method_api_base@@Base+0x250e66>
│ │ @@ -1093438,15 +1093438,15 @@
│ │  			@ <UNDEFINED> instruction: 0xea34ebfc
│ │  	movs	r5, r0
│ │  	b.n	3bd92a <uniffi_pbcli_checksum_method_api_base@@Base+0x2510a6>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3bdd32 <uniffi_pbcli_checksum_method_api_base@@Base+0x2514ae>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r5, r6, r9, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r7, r9, fp, ip, sp, lr}
│ │  	vqshrun.s16	d20, q8, #2
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3bdb1c <uniffi_pbcli_checksum_method_api_base@@Base+0x251298>
│ │  	movs	r1, r0
│ │  	b.n	3bd946 <uniffi_pbcli_checksum_method_api_base@@Base+0x2510c2>
│ │  	cbnz	r1, 3bd64e <uniffi_pbcli_checksum_method_api_base@@Base+0x250dca>
│ │  	add.w	r0, r0, r4, ror #4
│ │ @@ -1093470,15 +1093470,15 @@
│ │  			@ <UNDEFINED> instruction: 0xea20ebfc
│ │  	movs	r5, r0
│ │  	b.n	3bd97a <uniffi_pbcli_checksum_method_api_base@@Base+0x2510f6>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3bdd82 <uniffi_pbcli_checksum_method_api_base@@Base+0x2514fe>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r4, r9, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r4, r5, r9, fp, ip, sp, lr}
│ │  	vaddl.u8	<illegal reg q8.5>, d14, d0
│ │  	b.n	3bd98e <uniffi_pbcli_checksum_method_api_base@@Base+0x25110a>
│ │  	movs	r4, r0
│ │  	b.n	3bd190 <uniffi_pbcli_checksum_method_api_base@@Base+0x25090c>
│ │  	movs	r0, r0
│ │  	b.n	3bd774 <uniffi_pbcli_checksum_method_api_base@@Base+0x250ef0>
│ │  	lsls	r5, r2, #1
│ │ @@ -1093550,15 +1093550,15 @@
│ │  	vaddl.u8	<illegal reg q8.5>, d12, d0
│ │  	b.n	3bda42 <uniffi_pbcli_checksum_method_api_base@@Base+0x2511be>
│ │  	movs	r4, r0
│ │  	b.n	3bd244 <uniffi_pbcli_checksum_method_api_base@@Base+0x2509c0>
│ │  	movs	r0, r0
│ │  	b.n	3bd828 <uniffi_pbcli_checksum_method_api_base@@Base+0x250fa4>
│ │  	movs	r0, r5
│ │ -			@ <UNDEFINED> instruction: 0xea008812
│ │ +			@ <UNDEFINED> instruction: 0xea008839
│ │  	vqshrun.s16	d20, q8, #3
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3bdc34 <uniffi_pbcli_checksum_method_api_base@@Base+0x2513b0>
│ │  	movs	r1, r0
│ │  	b.n	3bda5e <uniffi_pbcli_checksum_method_api_base@@Base+0x2511da>
│ │  	revsh	r3, r2
│ │  	add.w	r0, r0, r4, ror #4
│ │ @@ -1093582,15 +1093582,15 @@
│ │  	ldrd	lr, fp, [sl, #1008]	@ 0x3f0
│ │  	movs	r5, r0
│ │  	b.n	3bda92 <uniffi_pbcli_checksum_method_api_base@@Base+0x25120e>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3bde9a <uniffi_pbcli_checksum_method_api_base@@Base+0x251616>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r5, r6, r7, r8, r9, sl, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r4, fp, pc}
│ │  	vqshrun.s16	d20, q8, #3
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3bdc84 <uniffi_pbcli_checksum_method_api_base@@Base+0x251400>
│ │  	movs	r1, r0
│ │  	b.n	3bdaae <uniffi_pbcli_checksum_method_api_base@@Base+0x25122a>
│ │  	hlt	0x003f
│ │  	add.w	r0, r0, r4, ror #4
│ │ @@ -1093614,15 +1093614,15 @@
│ │  	strd	lr, fp, [r6, #1008]	@ 0x3f0
│ │  	movs	r5, r0
│ │  	b.n	3bdae2 <uniffi_pbcli_checksum_method_api_base@@Base+0x25125e>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3bdeea <uniffi_pbcli_checksum_method_api_base@@Base+0x251666>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r7, r8, r9, sl, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r6, r7, r8, r9, sl, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcd48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3bdcd4 <uniffi_pbcli_checksum_method_api_base@@Base+0x251450>
│ │  	strb	r1, [r0, #0]
│ │  	b.n	3bdafe <uniffi_pbcli_checksum_method_api_base@@Base+0x25127a>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3bdb02 <uniffi_pbcli_checksum_method_api_base@@Base+0x25127e>
│ │ @@ -1093801,15 +1093801,15 @@
│ │  	movs	r0, r0
│ │  	movs	r1, r0
│ │  	movs	r0, r0
│ │  	movs	r1, r0
│ │  	movs	r0, r0
│ │  	movs	r0, #69	@ 0x45
│ │  			@ <UNDEFINED> instruction: 0xffcd1fad
│ │ -	vmla.i<illegal width 8>	<illegal reg q12.5>, <illegal reg q14.5>, d1[0]
│ │ +	vmla.i<illegal width 8>	<illegal reg q12.5>, <illegal reg q14.5>, d0[6]
│ │  	vaddl.u8	q8, d13, d0
│ │  	b.n	3be012 <uniffi_pbcli_checksum_method_api_base@@Base+0x25178e>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (3bda38 <uniffi_pbcli_checksum_method_api_base@@Base+0x2511b4>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3bde98 <uniffi_pbcli_checksum_method_api_base@@Base+0x251614>
│ │  	ands	r0, r0
│ │ @@ -1094434,36 +1094434,36 @@
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3be252 <uniffi_pbcli_checksum_method_api_base@@Base+0x2519ce>
│ │  	beq.n	3bdf44 <uniffi_pbcli_checksum_method_api_base@@Base+0x2516c0>
│ │  	b.n	3be3ac <uniffi_pbcli_checksum_method_api_base@@Base+0x251b28>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r1, r3, r6, r7, r8, r9, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcb1b55
│ │ -			@ <UNDEFINED> instruction: 0xffcd574d
│ │ +	vqshl.u8	<illegal reg q10.5>, q10, #5
│ │  	vrshr.u8	q11, q13, #2
│ │  			@ <UNDEFINED> instruction: 0xffcce9ff
│ │  			@ <UNDEFINED> instruction: 0xffcc1b21
│ │ -	vqshl.u8	d21, d9, #5
│ │ +			@ <UNDEFINED> instruction: 0xffcd5740
│ │  	vmlal.u<illegal width 8>	q14, d14, d0[6]
│ │  	vqdmulh.s<illegal width 8>	<illegal reg q8.5>, q6, d1[2]
│ │ -	vmul.i<illegal width 8>	<illegal reg q10.5>, <illegal reg q6.5>, d1[0]
│ │ +	vmul.i<illegal width 8>	<illegal reg q10.5>, <illegal reg q6.5>, d0[6]
│ │  	vabdl.u8	<illegal reg q15.5>, d30, d5
│ │  			@ <UNDEFINED> instruction: 0xffcc1b81
│ │ -	vqshl.u8	<illegal reg q10.5>, <illegal reg q12.5>, #5
│ │ +	vabdl.u8	<illegal reg q10.5>, d29, d16
│ │  	vmull.u<illegal width 8>	<illegal reg q8.5>, d30, d1[7]
│ │ -	vmlsl.u<illegal width 8>	<illegal reg q10.5>, d29, d1[5]
│ │ -	vqshl.u64	<illegal reg q13.5>, q0, #14
│ │ +	vabdl.u8	<illegal reg q10.5>, d13, d12
│ │ +	vqshl.u64	<illegal reg q13.5>, <illegal reg q11.5>, #14
│ │  			@ <UNDEFINED> instruction: 0xffcd1a91
│ │ -	vrsubhn.i16	d21, <illegal reg q14.5>, <illegal reg q4.5>
│ │ -	vrshr.u8	d17, d28, #2
│ │ +	vqshlu.s64	d21, d16, #13
│ │ +	vmlal.u<illegal width 8>	<illegal reg q8.5>, d14, d3[4]
│ │  			@ <UNDEFINED> instruction: 0xffce1bdd
│ │ -	vqshl.u64	<illegal reg q10.5>, <illegal reg q2.5>, #13
│ │ +	vqshl.u64	<illegal reg q10.5>, q14, #13
│ │  	vrshr.u64	<illegal reg q12.5>, <illegal reg q15.5>, #50
│ │  	vmul.f<illegal width 8>	<illegal reg q8.5>, q14, d1[6]
│ │ -	vmls.f<illegal width 8>	<illegal reg q10.5>, <illegal reg q14.5>, d1[4]
│ │ +	vrsubhn.i16	d21, <illegal reg q6.5>, q4
│ │  			@ <UNDEFINED> instruction: 0xffce1bae
│ │  	vaddl.u8	q8, d12, d4
│ │  	b.n	3bdac0 <uniffi_pbcli_checksum_method_api_base@@Base+0x25123c>
│ │  	movs	r0, r0
│ │  	b.n	3be0a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x251820>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	add	r2, sp, #128	@ 0x80
│ │ @@ -1095151,36 +1095151,36 @@
│ │  	vabdl.u8	<illegal reg q8.5>, d28, d1
│ │  	vmull.p8	<illegal reg q10.5>, d13, d19
│ │  	vabdl.u8	<illegal reg q8.5>, d13, d5
│ │  	vsubl.u8	<illegal reg q15.5>, d29, d25
│ │  	vrsubhn.i16	d17, q14, <illegal reg q2.5>
│ │  			@ <UNDEFINED> instruction: 0xffcd2e3d
│ │  			@ <UNDEFINED> instruction: 0xffcceab9
│ │ -	vshll.u8	<illegal reg q13.5>, d21, #4
│ │ +			@ <UNDEFINED> instruction: 0xffccba5c
│ │  	vsli.64	d17, d13, #13
│ │  	vmls.f<illegal width 8>	<illegal reg q8.5>, <illegal reg q14.5>, d1[2]
│ │  			@ <UNDEFINED> instruction: 0xffcde9d5
│ │  	vqshlu.s8	d17, d29, #4
│ │  	vmls.f<illegal width 8>	<illegal reg q8.5>, <illegal reg q6.5>, d1[7]
│ │ -			@ <UNDEFINED> instruction: 0xffcddfd7
│ │ +			@ <UNDEFINED> instruction: 0xffcddffe
│ │  	vqdmulh.s<illegal width 8>	q12, <illegal reg q14.5>, d3[0]
│ │  	vmls.f<illegal width 8>	<illegal reg q8.5>, q14, d1[3]
│ │ -	vshr.u8	d30, d23, #3
│ │ +	vshr.u8	q15, q7, #3
│ │  			@ <UNDEFINED> instruction: 0xffcd8d33
│ │  	vsri.64	d26, d1, #52
│ │  	vsri.64	<illegal reg q8.5>, <illegal reg q12.5>, #52
│ │  	vsri.8	<illegal reg q11.5>, q2, #3
│ │  	vabal.u8	q15, d28, d28
│ │  	vsubw.u8	<illegal reg q8.5>, <illegal reg q13.5>, d29
│ │  	vsubw.u8	<illegal reg q11.5>, <illegal reg q6.5>, d8
│ │  	vmls.i<illegal width 8>	q15, q6, d2[7]
│ │  	vrsra.u8	<illegal reg q14.5>, <illegal reg q4.5>, #5
│ │ -	vqshl.u64	q11, q6, #12
│ │ +	vmlal.u8	q11, d12, d3
│ │  	vqshlu.s8	q13, q7, #6
│ │ -			@ <UNDEFINED> instruction: 0xffcc0f95
│ │ +			@ <UNDEFINED> instruction: 0xffcc0fbc
│ │  	vaddl.u8	q8, d14, d4
│ │  	b.n	3be11c <uniffi_pbcli_checksum_method_api_base@@Base+0x251898>
│ │  	movs	r0, r0
│ │  	b.n	3be700 <uniffi_pbcli_checksum_method_api_base@@Base+0x251e7c>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	add	r4, pc, #800	@ (adr r4, 3be908 <uniffi_pbcli_checksum_method_api_base@@Base+0x252084>)
│ │  	movs	r0, r2
│ │ @@ -1096084,15 +1096084,15 @@
│ │  	beq.n	3bede8 <uniffi_pbcli_checksum_method_api_base@@Base+0x252564>
│ │  	b.n	3bf248 <uniffi_pbcli_checksum_method_api_base@@Base+0x2529c4>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r2, r4, r5, r6, r7, r8, r9, sl, fp}
│ │  			@ <UNDEFINED> instruction: 0xffcd0fd9
│ │  			@ <UNDEFINED> instruction: 0xffcd0b41
│ │  	vrsra.u8	d18, d7, #3
│ │ -			@ <UNDEFINED> instruction: 0xffcc1987
│ │ +			@ <UNDEFINED> instruction: 0xffcc19ae
│ │  			@ <UNDEFINED> instruction: 0xffce4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3bf2ec <uniffi_pbcli_checksum_method_api_base@@Base+0x252a68>
│ │  	beq.n	3bedec <uniffi_pbcli_checksum_method_api_base@@Base+0x252568>
│ │  	b.n	3bf270 <uniffi_pbcli_checksum_method_api_base@@Base+0x2529ec>
│ │  	ands	r0, r0
│ │  	b.n	3bf11a <uniffi_pbcli_checksum_method_api_base@@Base+0x252896>
│ │ @@ -1100061,15 +1100061,15 @@
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r2, r3, r5, ip}
│ │  	b.n	3c0946 <uniffi_pbcli_checksum_method_api_base@@Base+0x2540c2>
│ │  	movs	r1, r0
│ │  	b.n	3c158a <uniffi_pbcli_checksum_method_api_base@@Base+0x254d06>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r2, r4, r5, r7, r9, fp, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffcc87c0
│ │ +			@ <UNDEFINED> instruction: 0xffcc87e7
│ │  	vqrdmlah.s<illegal width 8>	<illegal reg q13.5>, <illegal reg q14.5>, d1[6]
│ │  	vmlal.u8	q10, d12, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3c11a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x25491e>
│ │  	movs	r3, r2
│ │  	b.n	3c1508 <uniffi_pbcli_checksum_method_api_base@@Base+0x254c84>
│ │  	movs	r0, r2
│ │ @@ -1100102,15 +1100102,15 @@
│ │  	b.n	3c0fc0 <uniffi_pbcli_checksum_method_api_base@@Base+0x25473c>
│ │  	ldr	r4, [r6, r1]
│ │  			@ <UNDEFINED> instruction: 0xebfc0000
│ │  	b.n	3c15ea <uniffi_pbcli_checksum_method_api_base@@Base+0x254d66>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r2, r6, r9, fp, sp, lr, pc}
│ │  	vaddw.u8	q8, q14, d10
│ │ -	vsri.64	d27, d22, #51
│ │ +	vsri.64	<illegal reg q13.5>, <illegal reg q6.5>, #51
│ │  			@ <UNDEFINED> instruction: 0xffcd4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3c13dc <uniffi_pbcli_checksum_method_api_base@@Base+0x254b58>
│ │  	str	r1, [r0, #0]
│ │  	b.n	3c1206 <uniffi_pbcli_checksum_method_api_base@@Base+0x254982>
│ │  	asrs	r0, r5, #1
│ │  	b.n	3c0a08 <uniffi_pbcli_checksum_method_api_base@@Base+0x254184>
│ │ @@ -1100191,15 +1100191,15 @@
│ │  	str	r0, [r0, r0]
│ │  	asrs	r0, r4, #6
│ │  	ands	r0, r0
│ │  	asrs	r0, r0, #22
│ │  	movs	r5, r0
│ │  	b.n	3c12be <uniffi_pbcli_checksum_method_api_base@@Base+0x254a3a>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r4, r5, r7, r9, sl, fp}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r6, r7, r9, sl, fp}
│ │  			@ <UNDEFINED> instruction: 0xffce48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3c14a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x254c24>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3c12d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x254a4e>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	3c0ab6 <uniffi_pbcli_checksum_method_api_base@@Base+0x254232>
│ │ @@ -1100332,16 +1100332,16 @@
│ │  	b.n	3c17ea <uniffi_pbcli_checksum_method_api_base@@Base+0x254f66>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3c11cc <uniffi_pbcli_checksum_method_api_base@@Base+0x254948>
│ │  	ldr	r6, [r0, #120]	@ 0x78
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3c13f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x254b72>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r3, r5, r6, r9, sl, fp}
│ │ -			@ <UNDEFINED> instruction: 0xffce0d72
│ │ +	ldmia.w	sp!, {r0, r4, r7, r9, sl, fp}
│ │ +			@ <UNDEFINED> instruction: 0xffce0d99
│ │  	vaddl.u8	q8, d14, d0
│ │  	b.n	3c1766 <uniffi_pbcli_checksum_method_api_base@@Base+0x254ee2>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (3c110c <uniffi_pbcli_checksum_method_api_base@@Base+0x254888>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3c15ec <uniffi_pbcli_checksum_method_api_base@@Base+0x254d68>
│ │  	ands	r0, r0
│ │ @@ -1100353,15 +1100353,15 @@
│ │  	b.n	3c1422 <uniffi_pbcli_checksum_method_api_base@@Base+0x254b9e>
│ │  	movs	r0, #121	@ 0x79
│ │  	b.n	3c1826 <uniffi_pbcli_checksum_method_api_base@@Base+0x254fa2>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3c1208 <uniffi_pbcli_checksum_method_api_base@@Base+0x254984>
│ │  	ldr	r4, [pc, #64]	@ (3c112c <uniffi_pbcli_checksum_method_api_base@@Base+0x2548a8>)
│ │  	ldmia.w	sp!, {r1, r2, r4, r5, r6, r8, r9, sl, fp, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xeafd0d36
│ │ +			@ <UNDEFINED> instruction: 0xeafd0d5d
│ │  			@ <UNDEFINED> instruction: 0xffce4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3c1618 <uniffi_pbcli_checksum_method_api_base@@Base+0x254d94>
│ │  	ands	r0, r0
│ │  	b.n	3c1442 <uniffi_pbcli_checksum_method_api_base@@Base+0x254bbe>
│ │  	strh	r0, [r1, #0]
│ │  	b.n	3c0a26 <uniffi_pbcli_checksum_method_api_base@@Base+0x2541a2>
│ │ @@ -1100430,15 +1100430,15 @@
│ │  	strh	r0, [r0, #0]
│ │  	b.n	3c0c9e <uniffi_pbcli_checksum_method_api_base@@Base+0x25441a>
│ │  	lsrs	r7, r1, #10
│ │  	orr.w	sl, r5, #4685824	@ 0x478000
│ │  	orr.w	sl, r6, #4685824	@ 0x478000
│ │  	orr.w	sl, r7, #4685824	@ 0x478000
│ │  	bne.w	341986 <uniffi_pbcli_checksum_method_api_base@@Base+0x1d5102>
│ │ -	ldmia.w	sp!, {r1, r8, sl, fp}
│ │ +	ldmia.w	sp!, {r0, r3, r5, r8, sl, fp}
│ │  			@ <UNDEFINED> instruction: 0xffce4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3c16d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x254e4c>
│ │  	beq.n	3c1280 <uniffi_pbcli_checksum_method_api_base@@Base+0x2549fc>
│ │  	b.n	3c1654 <uniffi_pbcli_checksum_method_api_base@@Base+0x254dd0>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3c14fe <uniffi_pbcli_checksum_method_api_base@@Base+0x254c7a>
│ │ @@ -1100690,20 +1100690,20 @@
│ │  	movs	r7, r0
│ │  	b.n	3c1722 <uniffi_pbcli_checksum_method_api_base@@Base+0x254e9e>
│ │  	asrs	r0, r0, #1
│ │  	b.n	3c1b26 <uniffi_pbcli_checksum_method_api_base@@Base+0x2552a2>
│ │  	subs	r2, #212	@ 0xd4
│ │  			@ <UNDEFINED> instruction: 0xebfdffc8
│ │  			@ <UNDEFINED> instruction: 0xeaff08e3
│ │ -			@ <UNDEFINED> instruction: 0xffcc0b82
│ │ -			@ <UNDEFINED> instruction: 0xffcede31
│ │ -			@ <UNDEFINED> instruction: 0xffcd0b56
│ │ -	vmull.p8	<illegal reg q14.5>, d14, d5
│ │ -			@ <UNDEFINED> instruction: 0xffcd0b2a
│ │ -			@ <UNDEFINED> instruction: 0xffceddd9
│ │ +			@ <UNDEFINED> instruction: 0xffcc0ba9
│ │ +			@ <UNDEFINED> instruction: 0xffcede58
│ │ +			@ <UNDEFINED> instruction: 0xffcd0b7d
│ │ +	vmull.p8	<illegal reg q14.5>, d14, d28
│ │ +			@ <UNDEFINED> instruction: 0xffcd0b51
│ │ +	vmull.p8	<illegal reg q14.5>, d14, d0
│ │  	vaddl.u8	q8, d13, d4
│ │  	b.n	3c0f4c <uniffi_pbcli_checksum_method_api_base@@Base+0x2546c8>
│ │  	movs	r0, r0
│ │  	b.n	3c1530 <uniffi_pbcli_checksum_method_api_base@@Base+0x254cac>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	strb	r0, [r4, #29]
│ │  	movs	r0, r2
│ │ @@ -1101059,15 +1101059,15 @@
│ │  	b.n	3c1240 <uniffi_pbcli_checksum_method_api_base@@Base+0x2549bc>
│ │  	str	r0, [sp, #48]	@ 0x30
│ │  	b.n	3c1244 <uniffi_pbcli_checksum_method_api_base@@Base+0x2549c0>
│ │  	lsls	r1, r0, #2
│ │  	add.w	r0, r0, r0, lsl #28
│ │  	b.n	3c1a72 <uniffi_pbcli_checksum_method_api_base@@Base+0x2551ee>
│ │  			@ <UNDEFINED> instruction: 0xffe3eaff
│ │ -	lsls	r6, r6, #29
│ │ +	lsls	r5, r3, #30
│ │  	vaddl.u8	q12, d30, d5
│ │  			@ <UNDEFINED> instruction: 0xffcb2afc
│ │  	vmul.f16	q9, <illegal reg q1.5>, d4[3]
│ │  	vaddl.u16	q8, d3, d4
│ │  	b.n	3c1288 <uniffi_pbcli_checksum_method_api_base@@Base+0x254a04>
│ │  	movs	r0, r0
│ │  	b.n	3c186c <uniffi_pbcli_checksum_method_api_base@@Base+0x254fe8>
│ │ @@ -1101250,22 +1101250,22 @@
│ │  	b.n	3c1c12 <uniffi_pbcli_checksum_method_api_base@@Base+0x25538e>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, sp, lr}
│ │  	b.n	3c201a <uniffi_pbcli_checksum_method_api_base@@Base+0x255796>
│ │  	movs	r6, r0
│ │  	b.n	3c1c1e <uniffi_pbcli_checksum_method_api_base@@Base+0x25539a>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r1, r2, r3, r5, r6, r8, sl}
│ │ +	ldmia.w	sp!, {r0, r2, r4, r7, r8, sl}
│ │  	vmlal.u<illegal width 8>	q15, d14, d1[2]
│ │ -			@ <UNDEFINED> instruction: 0xffcbafa7
│ │ -	vmlsl.u<illegal width 8>	q8, d13, d2[6]
│ │ +	vqrdmlsh.s<illegal width 8>	q13, <illegal reg q13.5>, d2[3]
│ │ +	vqshlu.s64	d16, d1, #13
│ │  			@ <UNDEFINED> instruction: 0xffce5d09
│ │ -	vqshlu.s8	d16, d2, #4
│ │ -	vmls.f<illegal width 8>	q8, q15, d2[3]
│ │ -			@ <UNDEFINED> instruction: 0xffce6b1c
│ │ +	vqshlu.s8	d16, d25, #4
│ │ +	vsli.64	q8, <illegal reg q10.5>, #14
│ │ +			@ <UNDEFINED> instruction: 0xffce6b43
│ │  	vaddl.u8	q8, d13, d4
│ │  	b.n	3c1444 <uniffi_pbcli_checksum_method_api_base@@Base+0x254bc0>
│ │  	movs	r0, r0
│ │  	b.n	3c1a28 <uniffi_pbcli_checksum_method_api_base@@Base+0x2551a4>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	strb	r4, [r1, #16]
│ │  	movs	r0, r2
│ │ @@ -1101378,15 +1101378,15 @@
│ │  	b.n	3c2146 <uniffi_pbcli_checksum_method_api_base@@Base+0x2558c2>
│ │  	strb	r3, [r3, r6]
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3c1d4e <uniffi_pbcli_checksum_method_api_base@@Base+0x2554ca>
│ │  	beq.n	3c1a48 <uniffi_pbcli_checksum_method_api_base@@Base+0x2551c4>
│ │  	b.n	3c1ea8 <uniffi_pbcli_checksum_method_api_base@@Base+0x255624>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r4, r5, sl}
│ │ +	ldmia.w	sp!, {r0, r3, r4, r6, sl}
│ │  			@ <UNDEFINED> instruction: 0xffce0b74
│ │  	vraddhn.i16	d17, <illegal reg q6.5>, q5
│ │  			@ <UNDEFINED> instruction: 0xffcc4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3c1f44 <uniffi_pbcli_checksum_method_api_base@@Base+0x2556c0>
│ │  	beq.n	3c1ae4 <uniffi_pbcli_checksum_method_api_base@@Base+0x255260>
│ │  	b.n	3c1ec8 <uniffi_pbcli_checksum_method_api_base@@Base+0x255644>
│ │ @@ -1101875,29 +1101875,29 @@
│ │  	strh	r2, [r0, #28]
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	3c24f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x255c72>
│ │  	str	r1, [r0, #0]
│ │  	asrs	r0, r4, #14
│ │  			@ <UNDEFINED> instruction: 0xffedeaff
│ │  	str	r0, [r4, #96]	@ 0x60
│ │ -	vsra.u64	q8, q1, #53
│ │ +	vsra.u64	q8, <illegal reg q12.5>, #53
│ │  			@ <UNDEFINED> instruction: 0xffcede92
│ │  	vmul.f<illegal width 8>	q14, <illegal reg q5.5>, d0[6]
│ │  	vabal.u8	<illegal reg q11.5>, d27, d28
│ │  	vabdl.u8	<illegal reg q15.5>, d28, d22
│ │ -	vmla.i<illegal width 8>	q8, <illegal reg q5.5>, d2[5]
│ │ +	vaddl.u8	q8, d27, d13
│ │  	vqrdmulh.s<illegal width 8>	<illegal reg q11.5>, q15, d3[7]
│ │ -	vqrdmlsh.s<illegal width 8>	<illegal reg q15.5>, <illegal reg q13.5>, d2[7]
│ │ -	vrshr.u8	q10, <illegal reg q6.5>, #3
│ │ -	vmull.u8	<illegal reg q14.5>, d29, d20
│ │ -	vsra.u8	d16, d22, #3
│ │ +	vshr.u8	d16, d5, #5
│ │ +	vsubl.u8	q10, d30, d4
│ │ +	vqdmulh.s<illegal width 8>	<illegal reg q14.5>, <illegal reg q14.5>, d3[2]
│ │ +	vsra.u8	q8, <illegal reg q6.5>, #3
│ │  			@ <UNDEFINED> instruction: 0xffceddf6
│ │ -	vshr.u64	q8, q9, #53
│ │ +	vsra.u8	d16, d9, #5
│ │  			@ <UNDEFINED> instruction: 0xffceddb2
│ │ -	vmla.i<illegal width 8>	q8, <illegal reg q13.5>, d2[3]
│ │ +	vshr.u64	q8, <illegal reg q10.5>, #53
│ │  			@ <UNDEFINED> instruction: 0xffcedd8e
│ │  			@ <UNDEFINED> instruction: 0xffcb48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3c23c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x255b40>
│ │  	ands	r1, r0
│ │  	b.n	3c25ee <uniffi_pbcli_checksum_method_api_base@@Base+0x255d6a>
│ │  	movs	r0, r0
│ │ @@ -1102012,15 +1102012,15 @@
│ │  	b.n	3c2642 <uniffi_pbcli_checksum_method_api_base@@Base+0x255dbe>
│ │  	ands	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	movs	r4, r0
│ │  	b.n	3c22ea <uniffi_pbcli_checksum_method_api_base@@Base+0x255a66>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r3, r5, r6, r7, r8, sl, ip, sp, pc}
│ │ -	vmull.p8	<illegal reg q15.5>, d28, d26
│ │ +			@ <UNDEFINED> instruction: 0xffccfed1
│ │  	vabdl.u8	<illegal reg q11.5>, d29, d27
│ │  			@ <UNDEFINED> instruction: 0xffcbfbd3
│ │  			@ <UNDEFINED> instruction: 0xffcb4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3c24e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x255c5c>
│ │  	udf	#131	@ 0x83
│ │  	b.n	3c2464 <uniffi_pbcli_checksum_method_api_base@@Base+0x255be0>
│ │ @@ -1102212,16 +1102212,16 @@
│ │  	strh	r4, [r0, r7]
│ │  			@ <UNDEFINED> instruction: 0xebfc0005
│ │  	b.n	3c24aa <uniffi_pbcli_checksum_method_api_base@@Base+0x255c26>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3c28b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x25602e>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r5, r9, sl, sp, lr, pc}
│ │ -	vrsubhn.i16	d30, <illegal reg q6.5>, <illegal reg q3.5>
│ │ +	ldmia.w	sp!, {r1, r4, r6, r9, sl, sp, lr, pc}
│ │ +	vrsubhn.i16	d30, <illegal reg q6.5>, q15
│ │  			@ <UNDEFINED> instruction: 0xffcdeefa
│ │  	vaddl.u8	q8, d12, d0
│ │  	b.n	3c2826 <uniffi_pbcli_checksum_method_api_base@@Base+0x255fa2>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #448]	@ (3c234c <uniffi_pbcli_checksum_method_api_base@@Base+0x255ac8>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3c26ac <uniffi_pbcli_checksum_method_api_base@@Base+0x255e28>
│ │ @@ -1102268,15 +1102268,15 @@
│ │  	b.n	3c252e <uniffi_pbcli_checksum_method_api_base@@Base+0x255caa>
│ │  	asrs	r5, r0, #32
│ │  	b.n	3c2532 <uniffi_pbcli_checksum_method_api_base@@Base+0x255cae>
│ │  	movs	r0, #76	@ 0x4c
│ │  	b.n	3c2936 <uniffi_pbcli_checksum_method_api_base@@Base+0x2560b2>
│ │  	ldr	r4, [pc, #448]	@ (3c23b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x255b34>)
│ │  	ldmia.w	sp!, {r0, r1, r4, r5, r8, r9, fp, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xeafde58f
│ │ +			@ <UNDEFINED> instruction: 0xeafde5b6
│ │  			@ <UNDEFINED> instruction: 0xffcd48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3c2724 <uniffi_pbcli_checksum_method_api_base@@Base+0x255ea0>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3c254e <uniffi_pbcli_checksum_method_api_base@@Base+0x255cca>
│ │  	strb	r4, [r2, #2]
│ │  	b.n	3c1d32 <uniffi_pbcli_checksum_method_api_base@@Base+0x2554ae>
│ │ @@ -1102452,18 +1102452,18 @@
│ │  	b.n	3c2ae6 <uniffi_pbcli_checksum_method_api_base@@Base+0x256262>
│ │  	ands	r0, r0
│ │  	b.n	3c2aea <uniffi_pbcli_checksum_method_api_base@@Base+0x256266>
│ │  	strh	r2, [r6, r4]
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3c26f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x255e6e>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r8, sl, sp, lr, pc}
│ │ -	vrsra.u64	d30, d31, #51
│ │ +	ldmia.w	sp!, {r1, r6, r8, sl, sp, lr, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffcde3e6
│ │  			@ <UNDEFINED> instruction: 0xffcdecb2
│ │ -	vsri.8	d30, d7, #4
│ │ +	vsri.8	d30, d30, #4
│ │  			@ <UNDEFINED> instruction: 0xffcd4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3c28e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x256064>
│ │  	ands	r0, r0
│ │  	b.n	3c2712 <uniffi_pbcli_checksum_method_api_base@@Base+0x255e8e>
│ │  	movs	r0, r0
│ │  	b.n	3c1ef6 <uniffi_pbcli_checksum_method_api_base@@Base+0x255672>
│ │ @@ -1102499,15 +1102499,15 @@
│ │  	b.n	3c275a <uniffi_pbcli_checksum_method_api_base@@Base+0x255ed6>
│ │  	asrs	r4, r5, #2
│ │  	b.n	3c2b5e <uniffi_pbcli_checksum_method_api_base@@Base+0x2562da>
│ │  	adds	r6, #198	@ 0xc6
│ │  			@ <UNDEFINED> instruction: 0xebfd6094
│ │  	b.n	3c1f2e <uniffi_pbcli_checksum_method_api_base@@Base+0x2556aa>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r4, r6, r8, r9, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r4, r5, r6, r8, r9, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcd48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3c2950 <uniffi_pbcli_checksum_method_api_base@@Base+0x2560cc>
│ │  	beq.n	3c2458 <uniffi_pbcli_checksum_method_api_base@@Base+0x255bd4>
│ │  	b.n	3c28d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x256050>
│ │  	strb	r3, [r0, #0]
│ │  	b.n	3c277e <uniffi_pbcli_checksum_method_api_base@@Base+0x255efa>
│ │ @@ -1102810,20 +1102810,20 @@
│ │  	b.n	3c2a0a <uniffi_pbcli_checksum_method_api_base@@Base+0x256186>
│ │  	movs	r7, r0
│ │  	b.n	3c2a0e <uniffi_pbcli_checksum_method_api_base@@Base+0x25618a>
│ │  	beq.n	3c2700 <uniffi_pbcli_checksum_method_api_base@@Base+0x255e7c>
│ │  	b.n	3c2b68 <uniffi_pbcli_checksum_method_api_base@@Base+0x2562e4>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r1, r2, r5, r7, r8, sl, ip, lr}
│ │ -	vmla.f<illegal width 8>	q15, q14, d3[2]
│ │ +	vsra.u64	q15, q9, #52
│ │  			@ <UNDEFINED> instruction: 0xffcddf8c
│ │ -	vmla.f<illegal width 8>	q15, <illegal reg q5.5>, d3[5]
│ │ +	vaddw.u8	q15, <illegal reg q13.5>, d14
│ │  			@ <UNDEFINED> instruction: 0xffcd5c10
│ │ -	vshr.u64	q15, <illegal reg q5.5>, #53
│ │ -			@ <UNDEFINED> instruction: 0xffcd6f82
│ │ +	vaddw.u8	q15, <illegal reg q5.5>, d2
│ │ +			@ <UNDEFINED> instruction: 0xffcd6fa9
│ │  	vmlsl.u<illegal width 8>	q8, d29, d2[7]
│ │  	vaddl.u8	q8, d12, d4
│ │  	b.n	3c2238 <uniffi_pbcli_checksum_method_api_base@@Base+0x2559b4>
│ │  	movs	r0, r0
│ │  	b.n	3c281c <uniffi_pbcli_checksum_method_api_base@@Base+0x255f98>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	str	r0, [r1, #112]	@ 0x70
│ │ @@ -1102951,15 +1102951,15 @@
│ │  	movs	r0, #52	@ 0x34
│ │  	b.n	3c231a <uniffi_pbcli_checksum_method_api_base@@Base+0x255a96>
│ │  	asrs	r0, r7, #32
│ │  	b.n	3c231e <uniffi_pbcli_checksum_method_api_base@@Base+0x255a9a>
│ │  	movs	r5, r0
│ │  	b.n	3c2b62 <uniffi_pbcli_checksum_method_api_base@@Base+0x2562de>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r7, r8, r9, sl, ip, lr}
│ │ +	ldmia.w	sp!, {r2, r4, r5, r7, r8, r9, sl, ip, lr}
│ │  			@ <UNDEFINED> instruction: 0xffcd4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3c2d4c <uniffi_pbcli_checksum_method_api_base@@Base+0x2564c8>
│ │  	beq.n	3c283c <uniffi_pbcli_checksum_method_api_base@@Base+0x255fb8>
│ │  	b.n	3c2cd0 <uniffi_pbcli_checksum_method_api_base@@Base+0x25644c>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3c2b7a <uniffi_pbcli_checksum_method_api_base@@Base+0x2562f6>
│ │ @@ -1103160,16 +1103160,16 @@
│ │  	b.n	3c24f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x255c72>
│ │  	ldr	r0, [r7, #16]
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3c2d2e <uniffi_pbcli_checksum_method_api_base@@Base+0x2564aa>
│ │  	beq.n	3c2a28 <uniffi_pbcli_checksum_method_api_base@@Base+0x2561a4>
│ │  	b.n	3c2e88 <uniffi_pbcli_checksum_method_api_base@@Base+0x256604>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r8, r9, sl, ip, lr}
│ │ -	vqshlu.s8	d21, d13, #5
│ │ +	ldmia.w	sp!, {r2, r6, r8, r9, sl, ip, lr}
│ │ +	vmlsl.u<illegal width 8>	<illegal reg q10.5>, d13, d0[1]
│ │  	vaddl.u8	q8, d13, d0
│ │  	b.n	3c30a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x25681e>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r5, [pc, #960]	@ (3c2dc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x256544>)
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3c2f28 <uniffi_pbcli_checksum_method_api_base@@Base+0x2566a4>
│ │  	ands	r0, r0
│ │ @@ -1103251,15 +1103251,15 @@
│ │  	b.n	3c2dfa <uniffi_pbcli_checksum_method_api_base@@Base+0x256576>
│ │  	movs	r0, r0
│ │  	b.n	3c25ca <uniffi_pbcli_checksum_method_api_base@@Base+0x255d46>
│ │  	movs	r4, r0
│ │  	b.n	3c2e02 <uniffi_pbcli_checksum_method_api_base@@Base+0x25657e>
│ │  	ldr	r5, [pc, #960]	@ (3c2e84 <uniffi_pbcli_checksum_method_api_base@@Base+0x256600>)
│ │  	ldmia.w	sp!, {r8, fp, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xeafd5545
│ │ +			@ <UNDEFINED> instruction: 0xeafd556c
│ │  			@ <UNDEFINED> instruction: 0xffcd4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3c2ff0 <uniffi_pbcli_checksum_method_api_base@@Base+0x25676c>
│ │  	ands	r0, r0
│ │  	b.n	3c2e1a <uniffi_pbcli_checksum_method_api_base@@Base+0x256596>
│ │  	strh	r0, [r0, #0]
│ │  	b.n	3c25fe <uniffi_pbcli_checksum_method_api_base@@Base+0x255d7a>
│ │ @@ -1103331,15 +1103331,15 @@
│ │  	b.n	3c2672 <uniffi_pbcli_checksum_method_api_base@@Base+0x255dee>
│ │  	movs	r0, r0
│ │  	b.n	3c32b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x256a32>
│ │  	lsrs	r1, r0, #10
│ │  	orr.w	r0, r6, #8388608	@ 0x800000
│ │  	b.n	3c268a <uniffi_pbcli_checksum_method_api_base@@Base+0x255e06>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r5, r6, sl, ip, lr}
│ │ +	ldmia.w	sp!, {r2, r5, r7, sl, ip, lr}
│ │  			@ <UNDEFINED> instruction: 0xffcd4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3c30a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x256824>
│ │  	beq.n	3c2c88 <uniffi_pbcli_checksum_method_api_base@@Base+0x256404>
│ │  	b.n	3c302c <uniffi_pbcli_checksum_method_api_base@@Base+0x2567a8>
│ │  	str	r3, [r0, r0]
│ │  	b.n	3c2ed6 <uniffi_pbcli_checksum_method_api_base@@Base+0x256652>
│ │ @@ -1103699,25 +1103699,25 @@
│ │  	b.n	3c2fbc <uniffi_pbcli_checksum_method_api_base@@Base+0x256738>
│ │  	ldr	r6, [r4, #8]
│ │  			@ <UNDEFINED> instruction: 0xebfd0006
│ │  	b.n	3c31e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x256962>
│ │  	beq.n	3c2ee0 <uniffi_pbcli_checksum_method_api_base@@Base+0x25665c>
│ │  	b.n	3c3340 <uniffi_pbcli_checksum_method_api_base@@Base+0x256abc>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r5, r7, r9, ip, lr}
│ │ +	ldmia.w	sp!, {r2, r5, r6, r7, r9, ip, lr}
│ │  	vrshr.u64	<illegal reg q8.5>, q9, #51
│ │ -	vsra.u64	d21, d9, #51
│ │ +	vmla.f<illegal width 8>	<illegal reg q10.5>, <illegal reg q14.5>, d0[0]
│ │  	vmla.f<illegal width 8>	<illegal reg q8.5>, <illegal reg q14.5>, d2[3]
│ │ -	vrshr.u64	d21, d1, #51
│ │ +	vrshr.u64	d21, d24, #51
│ │  	vmlal.u<illegal width 8>	<illegal reg q8.5>, d29, d2[1]
│ │  	vmlal.u8	q13, d29, d29
│ │ -	vaddw.u8	<illegal reg q10.5>, q6, d17
│ │ +	vmla.f<illegal width 8>	<illegal reg q10.5>, q6, d0[2]
│ │  	vsra.u8	<illegal reg q8.5>, q3, #3
│ │ -	vrshr.u8	d21, d21, #3
│ │ -	vshr.u64	<illegal reg q10.5>, <illegal reg q6.5>, #51
│ │ +	vrshr.u8	<illegal reg q10.5>, q6, #3
│ │ +	vaddw.u8	<illegal reg q10.5>, <illegal reg q6.5>, d4
│ │  	vaddl.u8	q8, d13, d4
│ │  	b.n	3c2a1c <uniffi_pbcli_checksum_method_api_base@@Base+0x256198>
│ │  	movs	r0, r0
│ │  	b.n	3c3000 <uniffi_pbcli_checksum_method_api_base@@Base+0x25677c>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldrsh	r0, [r6, r6]
│ │  	movs	r0, r2
│ │ @@ -1104100,32 +1104100,32 @@
│ │  	b.n	3c396a <uniffi_pbcli_checksum_method_api_base@@Base+0x2570e6>
│ │  	b.n	3c39c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x257142>
│ │  			@ <UNDEFINED> instruction: 0xebfc0000
│ │  	b.n	3c38d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x25704e>
│ │  	strb	r1, [r0, #0]
│ │  	asrs	r0, r4, #14
│ │  			@ <UNDEFINED> instruction: 0xffd1eaff
│ │ -	rev	r5, r5
│ │ -	vsli.8	<illegal reg q11.5>, <illegal reg q7.5>, #5
│ │ +	rev16	r4, r2
│ │ +	vabal.u8	<illegal reg q11.5>, d29, d6
│ │  	vmlsl.u<illegal width 8>	<illegal reg q13.5>, d13, d0[0]
│ │ -			@ <UNDEFINED> instruction: 0xffcb9b7b
│ │ +			@ <UNDEFINED> instruction: 0xffcb9ba2
│ │  	vmull.u8	<illegal reg q15.5>, d13, d10
│ │ -	vaddw.u8	<illegal reg q9.5>, <illegal reg q13.5>, d9
│ │ -			@ <UNDEFINED> instruction: 0xffcd4da1
│ │ +	vsra.u64	d19, d16, #53
│ │ +	vqrdmulh.s<illegal width 8>	q10, <illegal reg q14.5>, d0[2]
│ │  	vsra.u8	d19, d18, #3
│ │ -			@ <UNDEFINED> instruction: 0xffceee70
│ │ +			@ <UNDEFINED> instruction: 0xffceee97
│ │  	vabal.u8	q15, d13, d2
│ │  	vmls.i<illegal width 8>	q15, <illegal reg q13.5>, d2[5]
│ │  			@ <UNDEFINED> instruction: 0xffcb6b6f
│ │  	vmull.u<illegal width 8>	q15, d11, d3[4]
│ │  	vraddhn.i16	d27, <illegal reg q5.5>, q13
│ │ -			@ <UNDEFINED> instruction: 0xffcca8ba
│ │ +	vmul.i<illegal width 8>	q13, q14, d1[4]
│ │  	vraddhn.i16	d17, <illegal reg q14.5>, <illegal reg q9.5>
│ │ -	vqrshrun.s16	d26, q0, #3
│ │ -			@ <UNDEFINED> instruction: 0xffcd4f85
│ │ +	vqrshrun.s16	d26, <illegal reg q11.5>, #3
│ │ +			@ <UNDEFINED> instruction: 0xffcd4fac
│ │  	vrsra.u8	d19, d6, #3
│ │  	vaddl.u8	q8, d14, d4
│ │  	b.n	3c2dc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x256544>
│ │  	movs	r0, r0
│ │  	b.n	3c33ac <uniffi_pbcli_checksum_method_api_base@@Base+0x256b28>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldrb	r0, [r1, r4]
│ │ @@ -1105642,15 +1105642,15 @@
│ │  	ldmia.w	sp!, {r0, sp, lr}
│ │  	b.n	3c470e <uniffi_pbcli_checksum_method_api_base@@Base+0x257e8a>
│ │  	movs	r6, r0
│ │  	b.n	3c4312 <uniffi_pbcli_checksum_method_api_base@@Base+0x257a8e>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r1, r4, r5, r9, sl, ip, lr, pc}
│ │  	vrsra.u64	q9, <illegal reg q11.5>, #53
│ │ -			@ <UNDEFINED> instruction: 0xffce2a91
│ │ +			@ <UNDEFINED> instruction: 0xffce2ab8
│ │  	vrsra.u64	d18, d7, #51
│ │  	vaddl.u8	q8, d14, d4
│ │  	b.n	3c3b28 <uniffi_pbcli_checksum_method_api_base@@Base+0x2572a4>
│ │  	movs	r0, r0
│ │  	b.n	3c410c <uniffi_pbcli_checksum_method_api_base@@Base+0x257888>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	str	r4, [r0, r2]
│ │ @@ -1105787,15 +1105787,15 @@
│ │  	movs	r6, r0
│ │  	b.n	3c4462 <uniffi_pbcli_checksum_method_api_base@@Base+0x257bde>
│ │  	beq.n	3c4154 <uniffi_pbcli_checksum_method_api_base@@Base+0x2578d0>
│ │  	b.n	3c45bc <uniffi_pbcli_checksum_method_api_base@@Base+0x257d38>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r0, r6, ip, lr, pc}
│ │  	vmla.f<illegal width 8>	q10, <illegal reg q5.5>, d0[2]
│ │ -	vshr.u8	d30, d29, #5
│ │ +	vmla.i<illegal width 8>	q15, <illegal reg q5.5>, d0[5]
│ │  	vmls.i<illegal width 8>	<illegal reg q12.5>, <illegal reg q6.5>, d0[0]
│ │  	movs	r1, r2
│ │  	ldr	r0, [pc, #960]	@ (3c44fc <uniffi_pbcli_checksum_method_api_base@@Base+0x257c78>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3c465c <uniffi_pbcli_checksum_method_api_base@@Base+0x257dd8>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3c4486 <uniffi_pbcli_checksum_method_api_base@@Base+0x257c02>
│ │ @@ -1106049,15 +1106049,15 @@
│ │  	movs	r4, r5
│ │  	b.n	3c3e9e <uniffi_pbcli_checksum_method_api_base@@Base+0x25761a>
│ │  	beq.n	3c43c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x257b44>
│ │  	b.n	3c4830 <uniffi_pbcli_checksum_method_api_base@@Base+0x257fac>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r0, r3, r4, r6, r7, r8, sl, fp, lr, pc}
│ │  	vqrdmlah.s<illegal width 8>	<illegal reg q9.5>, <illegal reg q13.5>, d0[3]
│ │ -	vqrdmulh.s<illegal width 8>	<illegal reg q14.5>, <illegal reg q13.5>, d1[0]
│ │ +	vqrdmulh.s<illegal width 8>	<illegal reg q14.5>, <illegal reg q13.5>, d0[6]
│ │  	vmla.f<illegal width 8>	<illegal reg q12.5>, <illegal reg q14.5>, d0[2]
│ │  	movs	r1, r2
│ │  	ldr	r7, [pc, #960]	@ (3c4770 <uniffi_pbcli_checksum_method_api_base@@Base+0x257eec>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3c48d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x25804c>
│ │  	beq.n	3c44a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x257c1c>
│ │  	b.n	3c4854 <uniffi_pbcli_checksum_method_api_base@@Base+0x257fd0>
│ │ @@ -1106906,15 +1106906,15 @@
│ │  	vabdl.u8	q14, d28, d25
│ │  			@ <UNDEFINED> instruction: 0xffcbc74d
│ │  	vmlal.u<illegal width 8>	<illegal reg q10.5>, d11, d3[2]
│ │  	vqshlu.s64	q14, <illegal reg q10.5>, #11
│ │  	vqshl.u8	d28, d9, #3
│ │  	vmlsl.u<illegal width 8>	q14, d27, d1[0]
│ │  	vmlsl.u<illegal width 8>	q14, d11, d1[7]
│ │ -	vmlal.u<illegal width 8>	<illegal reg q10.5>, d11, d1[0]
│ │ +	vmlal.u<illegal width 8>	<illegal reg q10.5>, d11, d0[6]
│ │  	vrsubhn.i16	d28, <illegal reg q6.5>, <illegal reg q0.5>
│ │  	vrsubhn.i16	d28, <illegal reg q5.5>, <illegal reg q10.5>
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3c467c <uniffi_pbcli_checksum_method_api_base@@Base+0x257df8>
│ │  	movs	r0, r0
│ │  	b.n	3c4c60 <uniffi_pbcli_checksum_method_api_base@@Base+0x2583dc>
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -1106974,15 +1106974,15 @@
│ │  	str	r0, [r0, r0]
│ │  	asrs	r0, r4, #6
│ │  	ands	r0, r0
│ │  	asrs	r0, r0, #22
│ │  	movs	r5, r0
│ │  	b.n	3c4f0e <uniffi_pbcli_checksum_method_api_base@@Base+0x25868a>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r4, r7, r9, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r5, r7, r9, ip, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcd48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3c50f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x258874>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3c4f22 <uniffi_pbcli_checksum_method_api_base@@Base+0x25869e>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	3c4706 <uniffi_pbcli_checksum_method_api_base@@Base+0x257e82>
│ │ @@ -1107085,16 +1107085,16 @@
│ │  	lsrs	r5, r1, #11
│ │  	orr.w	sl, r7, #6782976	@ 0x678000
│ │  	orr.w	sl, r5, #6782976	@ 0x678000
│ │  	orr.w	r0, r7, #4080	@ 0xff0
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3c5012 <uniffi_pbcli_checksum_method_api_base@@Base+0x25878e>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r6, r9, ip, lr, pc}
│ │ -	vmla.f<illegal width 8>	<illegal reg q14.5>, <illegal reg q14.5>, d1[0]
│ │ +	ldmia.w	sp!, {r4, r5, r6, r9, ip, lr, pc}
│ │ +	vmla.f<illegal width 8>	<illegal reg q14.5>, <illegal reg q14.5>, d0[6]
│ │  	vaddl.u8	q8, d13, d0
│ │  	b.n	3c5382 <uniffi_pbcli_checksum_method_api_base@@Base+0x258afe>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #448]	@ (3c4ea8 <uniffi_pbcli_checksum_method_api_base@@Base+0x258624>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3c5208 <uniffi_pbcli_checksum_method_api_base@@Base+0x258984>
│ │  	ands	r0, r0
│ │ @@ -1107132,15 +1107132,15 @@
│ │  	movs	r0, #165	@ 0xa5
│ │  	b.n	3c547a <uniffi_pbcli_checksum_method_api_base@@Base+0x258bf6>
│ │  	lsrs	r5, r1, #11
│ │  	orr.w	sl, r6, #6782976	@ 0x678000
│ │  	orr.w	sl, r4, #6782976	@ 0x678000
│ │  	orr.w	ip, r6, #61440	@ 0xf000
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r6, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xeafdd145
│ │ +			@ <UNDEFINED> instruction: 0xeafdd16c
│ │  			@ <UNDEFINED> instruction: 0xffcd48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3c5274 <uniffi_pbcli_checksum_method_api_base@@Base+0x2589f0>
│ │  	ands	r0, r0
│ │  	b.n	3c509e <uniffi_pbcli_checksum_method_api_base@@Base+0x25881a>
│ │  	str	r4, [r0, #0]
│ │  	b.n	3c4682 <uniffi_pbcli_checksum_method_api_base@@Base+0x257dfe>
│ │ @@ -1107170,15 +1107170,15 @@
│ │  			@ <UNDEFINED> instruction: 0xebfd0050
│ │  	movt	sl, #207	@ 0xcf
│ │  	orr.w	r0, r4, #2048	@ 0x800
│ │  	b.n	3c48aa <uniffi_pbcli_checksum_method_api_base@@Base+0x258026>
│ │  	lsrs	r5, r1, #11
│ │  	orr.w	sl, r7, #6782976	@ 0x678000
│ │  	bne.w	34bf8a <uniffi_pbcli_checksum_method_api_base@@Base+0x1df706>
│ │ -	ldmia.w	sp!, {r0, r3, r4, r6, r7, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r8, ip, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcd4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3c52d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x258a50>
│ │  	beq.n	3c4e44 <uniffi_pbcli_checksum_method_api_base@@Base+0x2585c0>
│ │  	b.n	3c5258 <uniffi_pbcli_checksum_method_api_base@@Base+0x2589d4>
│ │  	ands	r3, r0
│ │  	b.n	3c5102 <uniffi_pbcli_checksum_method_api_base@@Base+0x25887e>
│ │ @@ -1107830,23 +1107830,23 @@
│ │  	str	r0, [r4, #0]
│ │  	b.n	3c4e74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2585f0>
│ │  	strb	r4, [r3, #0]
│ │  	b.n	3c4e78 <uniffi_pbcli_checksum_method_api_base@@Base+0x2585f4>
│ │  	str	r0, [r2, r0]
│ │  	b.n	3c4e7c <uniffi_pbcli_checksum_method_api_base@@Base+0x2585f8>
│ │  	vpmin.u<illegal width 64>	q7, <illegal reg q11.5>, <illegal reg q15.5>
│ │ -	ldmia	r6, {r0, r6, r7}
│ │ -	vqrdmlah.s<illegal width 8>	q14, <illegal reg q14.5>, d0[6]
│ │ -			@ <UNDEFINED> instruction: 0xffcdce95
│ │ +	ldmia	r6, {r3, r5, r6, r7}
│ │ +			@ <UNDEFINED> instruction: 0xffcdcf0f
│ │  			@ <UNDEFINED> instruction: 0xffcdcebc
│ │ -			@ <UNDEFINED> instruction: 0xffcdce55
│ │ +	vqrdmlah.s<illegal width 8>	q14, <illegal reg q14.5>, d3[4]
│ │ +			@ <UNDEFINED> instruction: 0xffcdce7c
│ │  	vmull.p8	<illegal reg q10.5>, d29, d18
│ │ -			@ <UNDEFINED> instruction: 0xffcbcfa9
│ │ -			@ <UNDEFINED> instruction: 0xffcdcf19
│ │ -			@ <UNDEFINED> instruction: 0xffcdce15
│ │ +			@ <UNDEFINED> instruction: 0xffcbcfd0
│ │ +	vqrdmlsh.s<illegal width 8>	q14, <illegal reg q6.5>, d0[0]
│ │ +			@ <UNDEFINED> instruction: 0xffcdce3c
│ │  	vaddl.u8	q8, d13, d4
│ │  	b.n	3c4eac <uniffi_pbcli_checksum_method_api_base@@Base+0x258628>
│ │  	movs	r0, r0
│ │  	b.n	3c5490 <uniffi_pbcli_checksum_method_api_base@@Base+0x258c0c>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	subs	r6, #124	@ 0x7c
│ │  	movs	r0, r2
│ │ @@ -1108077,21 +1108077,21 @@
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r0, sp, lr}
│ │  	b.n	3c5caa <uniffi_pbcli_checksum_method_api_base@@Base+0x259426>
│ │  	movs	r6, r0
│ │  	b.n	3c58ae <uniffi_pbcli_checksum_method_api_base@@Base+0x25902a>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r4, r5, r7, r9, sl, ip, sp, lr, pc}
│ │ -	vmull.u<illegal width 8>	q14, d11, d1[4]
│ │ -	vmlsl.u8	q14, d13, d1
│ │ +	vmlsl.u8	q14, d27, d8
│ │ +	vmlsl.u8	q14, d13, d24
│ │  	vqshl.u8	q10, <illegal reg q9.5>, #5
│ │ -			@ <UNDEFINED> instruction: 0xffcbc9b9
│ │ -	vqrshrn.u16	d28, <illegal reg q6.5>, #3
│ │ +	vmul.f<illegal width 8>	q14, <illegal reg q13.5>, d0[4]
│ │ +			@ <UNDEFINED> instruction: 0xffcdc984
│ │  	vsri.64	<illegal reg q8.5>, <illegal reg q15.5>, #51
│ │ -	vqshl.u8	q10, <illegal reg q14.5>, #4
│ │ +	vabdl.u8	q10, d28, d20
│ │  	vaddl.u8	q8, d13, d4
│ │  	b.n	3c50d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x258850>
│ │  	movs	r0, r0
│ │  	b.n	3c56b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x258e34>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	subs	r4, #224	@ 0xe0
│ │  	movs	r0, r2
│ │ @@ -1109419,28 +1109419,28 @@
│ │  	ldrb	r1, [r1, r0]
│ │  			@ <UNDEFINED> instruction: 0xebfdfef3
│ │  			@ <UNDEFINED> instruction: 0xeaff6eeb
│ │  	vqrshrun.s16	d16, q12, #5
│ │  			@ <UNDEFINED> instruction: 0xffce6ebf
│ │  	vmul.i<illegal width 8>	q8, <illegal reg q5.5>, d0[3]
│ │  			@ <UNDEFINED> instruction: 0xffce6f0b
│ │ -			@ <UNDEFINED> instruction: 0xffcb68b9
│ │ +	vmul.i<illegal width 8>	q11, <illegal reg q13.5>, d0[4]
│ │  			@ <UNDEFINED> instruction: 0xffcd6e37
│ │ -			@ <UNDEFINED> instruction: 0xffcb67e5
│ │ +	vmlal.u8	q11, d11, d12
│ │  			@ <UNDEFINED> instruction: 0xffcd6df7
│ │ -	vabdl.u8	q11, d27, d21
│ │ +			@ <UNDEFINED> instruction: 0xffcb67cc
│ │  			@ <UNDEFINED> instruction: 0xffcd6dab
│ │ -	vqshl.u8	q11, <illegal reg q4.5>, #3
│ │ +	vabdl.u8	q11, d27, d0
│ │  	vqrdmulh.s<illegal width 8>	q11, <illegal reg q6.5>, d3[1]
│ │ -	vqshlu.s64	q11, <illegal reg q10.5>, #11
│ │ +	vqshl.u8	d22, d12, #3
│ │  	vqdmulh.s<illegal width 8>	q11, <illegal reg q14.5>, d3[7]
│ │ -	vqshlu.s64	d22, d13, #11
│ │ +	vmlsl.u<illegal width 8>	q11, d27, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffcd6c97
│ │  			@ <UNDEFINED> instruction: 0xffcb68db
│ │ -	vsubl.u8	q11, d27, d9
│ │ +	vrshr.u64	d22, d16, #53
│ │  	vmlal.u8	q11, d29, d27
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3c5cac <uniffi_pbcli_checksum_method_api_base@@Base+0x259428>
│ │  	movs	r0, r0
│ │  	b.n	3c6290 <uniffi_pbcli_checksum_method_api_base@@Base+0x259a0c>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	adds	r1, #128	@ 0x80
│ │ @@ -1109852,16 +1109852,16 @@
│ │  	vabdl.u8	q11, d27, d15
│ │  			@ <UNDEFINED> instruction: 0xffcb3993
│ │  			@ <UNDEFINED> instruction: 0xffcb6747
│ │  	vmlsl.u<illegal width 8>	q11, d27, d3[6]
│ │  	vqrdmlsh.s<illegal width 8>	q14, <illegal reg q5.5>, d1[0]
│ │  	vsra.u64	q15, <illegal reg q15.5>, #52
│ │  			@ <UNDEFINED> instruction: 0xffccdf28
│ │ -	vabal.u8	<illegal reg q12.5>, d12, d27
│ │ -	vshr.u8	d25, d5, #3
│ │ +	vsli.8	<illegal reg q12.5>, q1, #4
│ │ +	vshr.u8	d25, d28, #3
│ │  	vmls.f<illegal width 8>	q11, <illegal reg q6.5>, d3[0]
│ │  	vsli.8	d22, d15, #3
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3c6048 <uniffi_pbcli_checksum_method_api_base@@Base+0x2597c4>
│ │  	movs	r0, r0
│ │  	b.n	3c662c <uniffi_pbcli_checksum_method_api_base@@Base+0x259da8>
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -1111232,23 +1111232,23 @@
│ │  			@ <UNDEFINED> instruction: 0xebfdffc6
│ │  			@ <UNDEFINED> instruction: 0xeaff2008
│ │  	b.n	3c7174 <uniffi_pbcli_checksum_method_api_base@@Base+0x25a8f0>
│ │  	asrs	r0, r3, #32
│ │  	b.n	3c7608 <uniffi_pbcli_checksum_method_api_base@@Base+0x25ad84>
│ │  			@ <UNDEFINED> instruction: 0xff89eaff
│ │  	adds	r7, r6, r3
│ │ -			@ <UNDEFINED> instruction: 0xffccdd00
│ │ +			@ <UNDEFINED> instruction: 0xffccdd27
│ │  	vmul.i<illegal width 8>	<illegal reg q8.5>, <illegal reg q14.5>, d3[2]
│ │ -			@ <UNDEFINED> instruction: 0xffccdcd4
│ │ +			@ <UNDEFINED> instruction: 0xffccdcfb
│ │  			@ <UNDEFINED> instruction: 0xffcd189f
│ │ -	vmull.u8	<illegal reg q14.5>, d28, d24
│ │ +	vqdmulh.s<illegal width 8>	<illegal reg q14.5>, q14, d3[3]
│ │  	vqrshrun.s16	d17, <illegal reg q9.5>, #3
│ │ -			@ <UNDEFINED> instruction: 0xffccdc7c
│ │ +	vmull.u8	<illegal reg q14.5>, d28, d19
│ │  	vmul.i<illegal width 8>	<illegal reg q8.5>, <illegal reg q6.5>, d3[1]
│ │ -			@ <UNDEFINED> instruction: 0xffccdc50
│ │ +			@ <UNDEFINED> instruction: 0xffccdc77
│ │  	vaddl.u8	q8, d13, d4
│ │  	b.n	3c6c5c <uniffi_pbcli_checksum_method_api_base@@Base+0x25a3d8>
│ │  	movs	r0, r0
│ │  	b.n	3c7240 <uniffi_pbcli_checksum_method_api_base@@Base+0x25a9bc>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r2, #232	@ 0xe8
│ │  	movs	r0, r2
│ │ @@ -1111535,24 +1111535,24 @@
│ │  			@ <UNDEFINED> instruction: 0xeaff0020
│ │  	b.n	3c6f26 <uniffi_pbcli_checksum_method_api_base@@Base+0x25a6a2>
│ │  	str	r1, [r0, #0]
│ │  	b.n	3c7ada <uniffi_pbcli_checksum_method_api_base@@Base+0x25b256>
│ │  			@ <UNDEFINED> instruction: 0xffe6eaff
│ │  	asrs	r0, r0, #3
│ │  	vqshlu.s8	<illegal reg q8.5>, <illegal reg q15.5>, #3
│ │ -			@ <UNDEFINED> instruction: 0xffcc7f31
│ │ +			@ <UNDEFINED> instruction: 0xffcc7f58
│ │  	vrsra.u8	q13, q5, #3
│ │  	vrsubhn.i16	d17, <illegal reg q5.5>, <illegal reg q11.5>
│ │  	vqrdmlsh.s<illegal width 8>	q11, q6, d2[1]
│ │  	vmls.f<illegal width 8>	<illegal reg q8.5>, <illegal reg q13.5>, d3[0]
│ │ -			@ <UNDEFINED> instruction: 0xffcc6a74
│ │ +			@ <UNDEFINED> instruction: 0xffcc6a9b
│ │  	vsli.8	<illegal reg q8.5>, <illegal reg q7.5>, #5
│ │ -			@ <UNDEFINED> instruction: 0xffcc99d5
│ │ +			@ <UNDEFINED> instruction: 0xffcc99fc
│ │  	vsri.64	d17, d23, #51
│ │ -	vqrdmulh.s<illegal width 8>	<illegal reg q11.5>, q6, d1[6]
│ │ +			@ <UNDEFINED> instruction: 0xffcc7d90
│ │  	vaddl.u8	q8, d13, d4
│ │  	b.n	3c6f10 <uniffi_pbcli_checksum_method_api_base@@Base+0x25a68c>
│ │  	movs	r0, r0
│ │  	b.n	3c74f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x25ac70>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r0, #192	@ 0xc0
│ │  	movs	r0, r2
│ │ @@ -1111610,15 +1111610,15 @@
│ │  	str	r0, [r0, r0]
│ │  	asrs	r0, r4, #6
│ │  	ands	r0, r0
│ │  	asrs	r0, r0, #22
│ │  	movs	r5, r0
│ │  	b.n	3c77a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x25af1e>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r4, r6, r8, sl, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r5, r6, r8, sl, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffcd4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3c798c <uniffi_pbcli_checksum_method_api_base@@Base+0x25b108>
│ │  	beq.n	3c747c <uniffi_pbcli_checksum_method_api_base@@Base+0x25abf8>
│ │  	b.n	3c7910 <uniffi_pbcli_checksum_method_api_base@@Base+0x25b08c>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3c77ba <uniffi_pbcli_checksum_method_api_base@@Base+0x25af36>
│ │ @@ -1111779,16 +1111779,16 @@
│ │  	orr.w	sl, r4, #4685824	@ 0x478000
│ │  	orr.w	r6, r7, #12096	@ 0x2f40
│ │  			@ <UNDEFINED> instruction: 0xebfd0009
│ │  	b.n	3c791a <uniffi_pbcli_checksum_method_api_base@@Base+0x25b096>
│ │  	beq.n	3c7614 <uniffi_pbcli_checksum_method_api_base@@Base+0x25ad90>
│ │  	b.n	3c7a74 <uniffi_pbcli_checksum_method_api_base@@Base+0x25b1f0>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r2, r8, sl, sp, lr}
│ │ -	vraddhn.i16	d22, <illegal reg q6.5>, q11
│ │ +	ldmia.w	sp!, {r0, r2, r3, r5, r8, sl, sp, lr}
│ │ +	vmls.i<illegal width 8>	q11, <illegal reg q6.5>, d1[3]
│ │  	vaddl.u8	q8, d13, d0
│ │  	b.n	3c7c8e <uniffi_pbcli_checksum_method_api_base@@Base+0x25b40a>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r3, [pc, #960]	@ (3c79b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x25b130>)
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3c7b14 <uniffi_pbcli_checksum_method_api_base@@Base+0x25b290>
│ │  	strb	r0, [r0, #0]
│ │ @@ -1111848,15 +1111848,15 @@
│ │  	movs	r1, #87	@ 0x57
│ │  	b.n	3c7c76 <uniffi_pbcli_checksum_method_api_base@@Base+0x25b3f2>
│ │  	lsrs	r7, r1, #10
│ │  	orr.w	sl, r5, #4685824	@ 0x478000
│ │  	orr.w	sl, r6, #4685824	@ 0x478000
│ │  	orr.w	fp, r7, #30720	@ 0x7800
│ │  	ldmia.w	sp!, {r4, r9, sl, ip, lr}
│ │ -			@ <UNDEFINED> instruction: 0xeafd6376
│ │ +			@ <UNDEFINED> instruction: 0xeafd639d
│ │  			@ <UNDEFINED> instruction: 0xffcd4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3c7bb0 <uniffi_pbcli_checksum_method_api_base@@Base+0x25b32c>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	3c79da <uniffi_pbcli_checksum_method_api_base@@Base+0x25b156>
│ │  	ands	r0, r0
│ │  	b.n	3c79de <uniffi_pbcli_checksum_method_api_base@@Base+0x25b15a>
│ │ @@ -1111906,15 +1111906,15 @@
│ │  			@ <UNDEFINED> instruction: 0xebfd0050
│ │  	blt.w	3c7702 <uniffi_pbcli_checksum_method_api_base@@Base+0x25ae7e>
│ │  	b.n	3c720e <uniffi_pbcli_checksum_method_api_base@@Base+0x25a98a>
│ │  	lsrs	r7, r1, #10
│ │  	orr.w	sl, r5, #4685824	@ 0x478000
│ │  	orr.w	sl, r6, #4685824	@ 0x478000
│ │  	bne.w	34eef2 <uniffi_pbcli_checksum_method_api_base@@Base+0x1e266e>
│ │ -	ldmia.w	sp!, {r1, r3, r4, r6, r7, r9, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r8, r9, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffcd4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3c7c3c <uniffi_pbcli_checksum_method_api_base@@Base+0x25b3b8>
│ │  	beq.n	3c763c <uniffi_pbcli_checksum_method_api_base@@Base+0x25adb8>
│ │  	b.n	3c7bc0 <uniffi_pbcli_checksum_method_api_base@@Base+0x25b33c>
│ │  	ands	r3, r0
│ │  	b.n	3c7a6a <uniffi_pbcli_checksum_method_api_base@@Base+0x25b1e6>
│ │ @@ -1112525,30 +1112525,30 @@
│ │  	b.n	3c7f92 <uniffi_pbcli_checksum_method_api_base@@Base+0x25b70e>
│ │  	adds	r4, #64	@ 0x40
│ │  			@ <UNDEFINED> instruction: 0xfa036001
│ │  	b.n	3c839a <uniffi_pbcli_checksum_method_api_base@@Base+0x25bb16>
│ │  	strb	r1, [r1, #0]
│ │  	b.n	3c7f9e <uniffi_pbcli_checksum_method_api_base@@Base+0x25b71a>
│ │  			@ <UNDEFINED> instruction: 0xffc1eaff
│ │ -	str	r6, [r7, #24]
│ │ -	vrsra.u64	<illegal reg q9.5>, <illegal reg q7.5>, #51
│ │ +	str	r5, [r4, #28]
│ │ +	vraddhn.i16	d19, <illegal reg q6.5>, q3
│ │  	vqshlu.s8	d27, d2, #5
│ │ -	vqrdmlsh.s<illegal width 8>	<illegal reg q10.5>, <illegal reg q5.5>, d2[0]
│ │ -	vmla.f<illegal width 8>	<illegal reg q9.5>, <illegal reg q6.5>, d3[4]
│ │ -	vmla.f<illegal width 8>	<illegal reg q11.5>, <illegal reg q6.5>, d1[2]
│ │ +	vqrdmlsh.s<illegal width 8>	<illegal reg q10.5>, <illegal reg q5.5>, d1[6]
│ │ +	vaddw.u8	<illegal reg q9.5>, <illegal reg q14.5>, d10
│ │ +	vsra.u8	<illegal reg q11.5>, q8, #3
│ │  	vqrshrun.s16	d28, q10, #3
│ │ -	vsra.u16	d22, d14, #14
│ │ +	vmla.f16	q11, q1, d5[0]
│ │  			@ <UNDEFINED> instruction: 0xffcd4ed4
│ │  	vqshrn.u16	d21, <illegal reg q0.5>, #5
│ │ -			@ <UNDEFINED> instruction: 0xffcc5db2
│ │ -			@ <UNDEFINED> instruction: 0xffcd5e1e
│ │ -			@ <UNDEFINED> instruction: 0xffcd5f26
│ │ -	vmla.f<illegal width 8>	<illegal reg q9.5>, <illegal reg q6.5>, d3[1]
│ │ -			@ <UNDEFINED> instruction: 0xffcd5efa
│ │ -	vsra.u8	d19, d11, #3
│ │ +			@ <UNDEFINED> instruction: 0xffcc5dd9
│ │ +	vqrdmlah.s<illegal width 8>	<illegal reg q10.5>, <illegal reg q6.5>, d1[1]
│ │ +	vqrdmlsh.s<illegal width 8>	<illegal reg q10.5>, <illegal reg q6.5>, d1[3]
│ │ +	vmla.f<illegal width 8>	<illegal reg q9.5>, <illegal reg q6.5>, d2[7]
│ │ +			@ <UNDEFINED> instruction: 0xffcd5f21
│ │ +	vmla.f<illegal width 8>	<illegal reg q9.5>, <illegal reg q6.5>, d2[0]
│ │  	vaddl.u8	q8, d13, d4
│ │  	b.n	3c77e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x25af60>
│ │  	movs	r0, r0
│ │  	b.n	3c7dc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x25b544>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	adds	r4, r6, r2
│ │  	movs	r0, r2
│ │ @@ -1112708,19 +1112708,19 @@
│ │  	b.n	3c8556 <uniffi_pbcli_checksum_method_api_base@@Base+0x25bcd2>
│ │  	subs	r4, #151	@ 0x97
│ │  			@ <UNDEFINED> instruction: 0xebfc0000
│ │  	b.n	3c855e <uniffi_pbcli_checksum_method_api_base@@Base+0x25bcda>
│ │  	beq.n	3c7e40 <uniffi_pbcli_checksum_method_api_base@@Base+0x25b5bc>
│ │  	b.n	3c82b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x25ba34>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, sl, fp, ip, lr}
│ │ +	ldmia.w	sp!, {r0, r3, r5, sl, fp, ip, lr}
│ │  			@ <UNDEFINED> instruction: 0xffcd7d73
│ │ -	vmull.u8	<illegal reg q10.5>, d11, d26
│ │ +			@ <UNDEFINED> instruction: 0xffcb5c51
│ │  			@ <UNDEFINED> instruction: 0xffcd7d9b
│ │ -			@ <UNDEFINED> instruction: 0xffcb5ba2
│ │ +			@ <UNDEFINED> instruction: 0xffcb5bc9
│ │  			@ <UNDEFINED> instruction: 0xffcd7d13
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3c7980 <uniffi_pbcli_checksum_method_api_base@@Base+0x25b0fc>
│ │  	movs	r0, r0
│ │  	b.n	3c7f64 <uniffi_pbcli_checksum_method_api_base@@Base+0x25b6e0>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	asrs	r4, r6, #31
│ │ @@ -1113210,19 +1113210,19 @@
│ │  	strh	r1, [r0, #0]
│ │  	b.n	3c89c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x25c142>
│ │  	movs	r0, r1
│ │  	b.n	3c85ca <uniffi_pbcli_checksum_method_api_base@@Base+0x25bd46>
│ │  	beq.n	3c82bc <uniffi_pbcli_checksum_method_api_base@@Base+0x25ba38>
│ │  	b.n	3c8724 <uniffi_pbcli_checksum_method_api_base@@Base+0x25bea0>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r6, fp, sp, lr}
│ │ -	vsubw.u8	q9, <illegal reg q14.5>, d27
│ │ +	ldmia.w	sp!, {r5, r7, fp, sp, lr}
│ │ +	vrsra.u64	q9, q1, #51
│ │  	vshr.u64	q8, q0, #51
│ │ -	vmlal.u8	<illegal reg q10.5>, d11, d6
│ │ -	vsra.u64	q10, q4, #51
│ │ +	vmlal.u8	<illegal reg q10.5>, d11, d29
│ │ +	vsra.u64	q10, <illegal reg q15.5>, #51
│ │  	vsubw.u8	<illegal reg q12.5>, <illegal reg q14.5>, d25
│ │  	vrsra.u8	d25, d26, #5
│ │  			@ <UNDEFINED> instruction: 0xffcb98df
│ │  			@ <UNDEFINED> instruction: 0xffcb199b
│ │  	vmls.f<illegal width 8>	<illegal reg q14.5>, <illegal reg q13.5>, d1[7]
│ │  			@ <UNDEFINED> instruction: 0xffcb48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │ @@ -1113299,16 +1113299,16 @@
│ │  	b.n	3c89fe <uniffi_pbcli_checksum_method_api_base@@Base+0x25c17a>
│ │  	ands	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	movs	r4, r0
│ │  	b.n	3c86a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x25be22>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r2, r4, r6, r7, r8, ip, lr}
│ │ -	vqshlu.s8	<illegal reg q10.5>, q9, #4
│ │ -	vqdmulh.s<illegal width 8>	<illegal reg q15.5>, <illegal reg q6.5>, d0[7]
│ │ +	vqshlu.s64	d21, d9, #12
│ │ +			@ <UNDEFINED> instruction: 0xffcdfc93
│ │  	vqshrun.s16	d20, q8, #4
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3c8898 <uniffi_pbcli_checksum_method_api_base@@Base+0x25c014>
│ │  	ands	r0, r0
│ │  	b.n	3c86c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x25be3e>
│ │  	adds	r6, r5, #4
│ │  			@ <UNDEFINED> instruction: 0xebff5000
│ │ @@ -1114185,15 +1114185,15 @@
│ │  	b.n	3c8fdc <uniffi_pbcli_checksum_method_api_base@@Base+0x25c758>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r2, r3, r4, r5, r8, fp, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffca0d24
│ │  	vmls.i<illegal width 8>	q13, q6, d2[7]
│ │  	vmull.u<illegal width 8>	<illegal reg q10.5>, d11, d3[3]
│ │  	vmls.i<illegal width 8>	q13, q6, d2[2]
│ │ -	vqshl.u64	d25, d25, #11
│ │ +			@ <UNDEFINED> instruction: 0xffcb97e0
│ │  	vraddhn.i16	d26, <illegal reg q14.5>, q3
│ │  	vqshlu.s8	<illegal reg q8.5>, q12, #3
│ │  	vmls.f<illegal width 8>	<illegal reg q13.5>, q14, d3[7]
│ │  			@ <UNDEFINED> instruction: 0xffcc8b71
│ │  	vqshlu.s8	d17, d0, #3
│ │  			@ <UNDEFINED> instruction: 0xffcc5a7e
│ │  			@ <UNDEFINED> instruction: 0xffcc5a5e
│ │ @@ -1115619,28 +1115619,28 @@
│ │  			@ <UNDEFINED> instruction: 0xff96eaff
│ │  	cdp	15, 4, cr15, cr12, cr10, {6}
│ │  	subs	r1, #5
│ │  	vmull.u8	q13, d12, d14
│ │  	vaddw.u8	q12, <illegal reg q5.5>, d29
│ │  	vmla.i<illegal width 8>	q12, <illegal reg q13.5>, d2[2]
│ │  	vrsubhn.i16	d19, <illegal reg q13.5>, <illegal reg q14.5>
│ │ -			@ <UNDEFINED> instruction: 0xffcc89f2
│ │ +	vshll.u8	q12, d9, #4
│ │  	vrsubhn.i16	d19, <illegal reg q6.5>, <illegal reg q10.5>
│ │  	vsri.64	d25, d22, #52
│ │  			@ <UNDEFINED> instruction: 0xffcbb349
│ │  	vmlsl.u<illegal width 8>	<illegal reg q9.5>, d12, d1[6]
│ │ -	vmlal.u<illegal width 8>	<illegal reg q11.5>, d12, d1[5]
│ │ +	vsubl.u8	<illegal reg q11.5>, d28, d12
│ │  	vmls.f<illegal width 8>	<illegal reg q9.5>, <illegal reg q14.5>, d1[4]
│ │ -			@ <UNDEFINED> instruction: 0xffcc5bb7
│ │ +			@ <UNDEFINED> instruction: 0xffcc5bde
│ │  	vmull.u<illegal width 8>	q13, d13, d3[7]
│ │  	vsli.64	d19, d13, #12
│ │ -	vmla.f<illegal width 8>	<illegal reg q11.5>, q14, d1[4]
│ │ +	vsubl.u8	<illegal reg q11.5>, d12, d8
│ │  	vsli.8	<illegal reg q9.5>, <illegal reg q4.5>, #5
│ │  	vsubw.u8	q12, q14, d24
│ │ -			@ <UNDEFINED> instruction: 0xffcc5e5d
│ │ +	vmull.p8	<illegal reg q10.5>, d28, d4
│ │  	vsubw.u8	q8, <illegal reg q6.5>, d12
│ │  	movs	r0, r2
│ │  	movs	r4, r0
│ │  	b.n	3c9390 <uniffi_pbcli_checksum_method_api_base@@Base+0x25cb0c>
│ │  	movs	r0, r0
│ │  	b.n	3c9974 <uniffi_pbcli_checksum_method_api_base@@Base+0x25d0f0>
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -1115711,15 +1115711,15 @@
│ │  	b.n	3ca02e <uniffi_pbcli_checksum_method_api_base@@Base+0x25d7aa>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3ca036 <uniffi_pbcli_checksum_method_api_base@@Base+0x25d7b2>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r3, r4, r5, sl, fp, ip, sp}
│ │  	vmls.i<illegal width 8>	<illegal reg q9.5>, q6, d1[7]
│ │ -	vrsra.u8	d17, d8, #4
│ │ +	vrsra.u8	d17, d31, #4
│ │  			@ <UNDEFINED> instruction: 0xffcd4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3c9e28 <uniffi_pbcli_checksum_method_api_base@@Base+0x25d5a4>
│ │  	beq.n	3c99c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x25d144>
│ │  	b.n	3c9dac <uniffi_pbcli_checksum_method_api_base@@Base+0x25d528>
│ │  	ands	r0, r0
│ │  	b.n	3ca056 <uniffi_pbcli_checksum_method_api_base@@Base+0x25d7d2>
│ │ @@ -1116453,18 +1116453,18 @@
│ │  	adds	r4, #72	@ 0x48
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3ca29a <uniffi_pbcli_checksum_method_api_base@@Base+0x25da16>
│ │  	ldrh	r4, [r2, #48]	@ 0x30
│ │  			@ <UNDEFINED> instruction: 0xebfc0005
│ │  	b.n	3ca2a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x25da1e>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r6, r8, r9, sl, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r7, r8, r9, sl, ip, sp, lr, pc}
│ │  	vmlal.u<illegal width 8>	q10, d12, d1[6]
│ │ -	vshr.u64	d30, d31, #52
│ │ -	vmull.u<illegal width 8>	<illegal reg q9.5>, d28, d1[0]
│ │ +	vmla.i<illegal width 8>	q15, q14, d2[5]
│ │ +	vmull.u<illegal width 8>	<illegal reg q9.5>, d28, d0[6]
│ │  	vqrdmulh.s<illegal width 8>	q9, <illegal reg q14.5>, d1[7]
│ │  	vsra.u8	d16, d18, #4
│ │  			@ <UNDEFINED> instruction: 0xffcc4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3ca4a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x25dc1c>
│ │  	beq.n	3c9fa8 <uniffi_pbcli_checksum_method_api_base@@Base+0x25d724>
│ │  	b.n	3ca424 <uniffi_pbcli_checksum_method_api_base@@Base+0x25dba0>
│ │ @@ -1118073,21 +1118073,21 @@
│ │  	b.n	3ca892 <uniffi_pbcli_checksum_method_api_base@@Base+0x25e00e>
│ │  	movs	r0, r0
│ │  	b.n	3ca87a <uniffi_pbcli_checksum_method_api_base@@Base+0x25dff6>
│ │  	movs	r4, r3
│ │  	b.n	3ca8a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x25e020>
│ │  			@ <UNDEFINED> instruction: 0xffe3eaff
│ │  	ldrb	r6, [r0, #12]
│ │ -	vmla.f<illegal width 8>	q8, q6, d1[4]
│ │ +	vaddw.u8	q8, q14, d8
│ │  	vqrdmlah.s<illegal width 8>	q10, <illegal reg q14.5>, d0[2]
│ │  	vmull.u<illegal width 8>	<illegal reg q11.5>, d12, d2[7]
│ │ -	vmla.i<illegal width 8>	q8, q14, d1[2]
│ │ +	vshr.u64	q8, q8, #52
│ │  	vsli.8	d22, d27, #5
│ │  			@ <UNDEFINED> instruction: 0xffcc78b6
│ │ -			@ <UNDEFINED> instruction: 0xffccff11
│ │ +			@ <UNDEFINED> instruction: 0xffccff38
│ │  	vmul.i<illegal width 8>	<illegal reg q11.5>, q14, d1[1]
│ │  			@ <UNDEFINED> instruction: 0xffcc7ade
│ │  			@ <UNDEFINED> instruction: 0xffcc4e9a
│ │  			@ <UNDEFINED> instruction: 0xffcc48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3cb2bc <uniffi_pbcli_checksum_method_api_base@@Base+0x25ea38>
│ │  	ands	r2, r0
│ │ @@ -1118399,15 +1118399,15 @@
│ │  	vrshr.u64	d22, d31, #52
│ │  	vmull.u<illegal width 8>	q10, d27, d0[4]
│ │  	vabal.u8	<illegal reg q11.5>, d28, d30
│ │  	vmla.f<illegal width 8>	q11, q6, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffcb19f7
│ │  	vsli.8	<illegal reg q11.5>, q1, #3
│ │  	vmla.i<illegal width 8>	q11, q14, d3[6]
│ │ -	vrsra.u8	<illegal reg q8.5>, q5, #5
│ │ +	vsubw.u8	<illegal reg q8.5>, <illegal reg q13.5>, d1
│ │  	vqshlu.s64	<illegal reg q11.5>, q11, #13
│ │  	vsra.u64	q14, <illegal reg q4.5>, #52
│ │  			@ <UNDEFINED> instruction: 0xffcb4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3cb5a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x25ed1c>
│ │  	ands	r0, r0
│ │  	b.n	3cb3ca <uniffi_pbcli_checksum_method_api_base@@Base+0x25eb46>
│ │ @@ -1118550,15 +1118550,15 @@
│ │  	ldrsh	r1, [r5, r2]
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	3cb85a <uniffi_pbcli_checksum_method_api_base@@Base+0x25efd6>
│ │  			@ <UNDEFINED> instruction: 0xffdb1aff
│ │  			@ <UNDEFINED> instruction: 0xfff4eaff
│ │  	lsls	r7, r7, #25
│ │  	vmls.i<illegal width 8>	<illegal reg q11.5>, q6, d2[0]
│ │ -	vrsra.u8	q12, <illegal reg q13.5>, #4
│ │ +	vsubw.u8	q12, q14, d18
│ │  	vaddl.u8	q8, d13, d4
│ │  	b.n	3cad10 <uniffi_pbcli_checksum_method_api_base@@Base+0x25e48c>
│ │  	movs	r0, r0
│ │  	b.n	3cb2f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x25ea70>
│ │  	vrhadd.u16	d14, d14, d31
│ │  			@ <UNDEFINED> instruction: 0xe830000f
│ │  	ldr	r0, [pc, #0]	@ (3cb1e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x25e95c>)
│ │ @@ -1119231,18 +1119231,18 @@
│ │  	b.n	3cbc60 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f3dc>
│ │  	asrs	r6, r0, #32
│ │  	b.n	3cbb0e <uniffi_pbcli_checksum_method_api_base@@Base+0x25f28a>
│ │  	asrs	r2, r3, #7
│ │  			@ <UNDEFINED> instruction: 0xebfdfff1
│ │  			@ <UNDEFINED> instruction: 0xeaff6e0a
│ │  			@ <UNDEFINED> instruction: 0xffccb8df
│ │ -	vsri.64	d25, d26, #53
│ │ -	vqshl.u64	q11, q6, #13
│ │ +	vmls.i<illegal width 8>	<illegal reg q12.5>, <illegal reg q13.5>, d1[4]
│ │ +	vmlal.u8	q11, d13, d3
│ │  			@ <UNDEFINED> instruction: 0xffcd89ff
│ │ -			@ <UNDEFINED> instruction: 0xffd20c74
│ │ +			@ <UNDEFINED> instruction: 0xffd20c9b
│ │  			@ <UNDEFINED> instruction: 0xffcd4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3cbd10 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f48c>
│ │  	beq.n	3cb800 <uniffi_pbcli_checksum_method_api_base@@Base+0x25ef7c>
│ │  	b.n	3cbc94 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f410>
│ │  	str	r3, [r0, r0]
│ │  	b.n	3cbb3e <uniffi_pbcli_checksum_method_api_base@@Base+0x25f2ba>
│ │ @@ -1119344,16 +1119344,16 @@
│ │  	b.n	3cc016 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f792>
│ │  	movs	r5, r0
│ │  	b.n	3cbc1a <uniffi_pbcli_checksum_method_api_base@@Base+0x25f396>
│ │  	beq.n	3cb914 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f090>
│ │  	b.n	3cbd74 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f4f0>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r1, r2, r3, r6, r7, sl, fp, sp, lr}
│ │ -	vsli.64	q11, q6, #12
│ │ -	vaddw.u8	q9, <illegal reg q6.5>, d7
│ │ +	vrsubhn.i16	d22, q6, <illegal reg q1.5>
│ │ +	vaddw.u8	q9, <illegal reg q6.5>, d30
│ │  			@ <UNDEFINED> instruction: 0xffcd4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3cbe10 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f58c>
│ │  	asrs	r0, r4, #3
│ │  	b.n	3cb438 <uniffi_pbcli_checksum_method_api_base@@Base+0x25ebb4>
│ │  	ands	r0, r0
│ │  	b.n	3cbc3e <uniffi_pbcli_checksum_method_api_base@@Base+0x25f3ba>
│ │ @@ -1119453,20 +1119453,20 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	3cbaf4 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f270>
│ │  	lsls	r0, r0, #4
│ │  	b.n	3cbadc <uniffi_pbcli_checksum_method_api_base@@Base+0x25f258>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r0, r1, r2, r4, r7, r8, fp, lr}
│ │  	vshr.u64	d28, d7, #52
│ │ -	vqshl.u8	<illegal reg q10.5>, q5, #3
│ │ +	vabdl.u8	<illegal reg q10.5>, d27, d1
│ │  			@ <UNDEFINED> instruction: 0xffcdbb93
│ │ -	vmla.i<illegal width 8>	q12, <illegal reg q5.5>, d2[0]
│ │ +	vmla.i<illegal width 8>	q12, <illegal reg q5.5>, d1[6]
│ │  	vmla.i<illegal width 8>	q15, <illegal reg q6.5>, d0[7]
│ │  	movs	r7, r1
│ │ -	bgt.n	3cb938 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f0b4>
│ │ +	bgt.n	3cb986 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f102>
│ │  	vqrdmlah.s<illegal width 8>	q14, q14, d3[3]
│ │  			@ <UNDEFINED> instruction: 0xffcb4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3cbf20 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f69c>
│ │  	beq.n	3cbb00 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f27c>
│ │  	b.n	3cbea4 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f620>
│ │  	str	r0, [sp, #4]
│ │ @@ -1119631,15 +1119631,15 @@
│ │  	beq.n	3cbba8 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f324>
│ │  	b.n	3cc008 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f784>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r2, r3, r4, r5, r7, r8, r9, fp, sp}
│ │  	vaddw.u8	q15, <illegal reg q13.5>, d3
│ │  	vmlsl.u8	<illegal reg q10.5>, d26, d18
│ │  	vaddl.u8	q11, d11, d31
│ │ -			@ <UNDEFINED> instruction: 0xffcbdad8
│ │ +			@ <UNDEFINED> instruction: 0xffcbdaff
│ │  	vmlsl.u8	q11, d12, d13
│ │  			@ <UNDEFINED> instruction: 0xffcc4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3cc0b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f82c>
│ │  	beq.n	3cbc30 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f3ac>
│ │  	b.n	3cc034 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f7b0>
│ │  	str	r0, [sp, #48]	@ 0x30
│ │ @@ -1119852,19 +1119852,19 @@
│ │  	and.w	r0, r0, r0, lsl #20
│ │  	b.n	3cc4a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x25fc22>
│ │  	movs	r5, r0
│ │  	b.n	3cc0aa <uniffi_pbcli_checksum_method_api_base@@Base+0x25f826>
│ │  	beq.n	3cbda4 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f520>
│ │  	b.n	3cc204 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f980>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r2, r4, r5, r9, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r4, r6, r9, fp, ip, lr, pc}
│ │  	vsri.64	d24, d11, #52
│ │ -			@ <UNDEFINED> instruction: 0xffd2d904
│ │ +			@ <UNDEFINED> instruction: 0xffd2d92b
│ │  			@ <UNDEFINED> instruction: 0xffcc689c
│ │ -	vmul.i<illegal width 8>	<illegal reg q14.5>, q14, d0[2]
│ │ +	vmul.i<illegal width 8>	<illegal reg q14.5>, q14, d3[7]
│ │  			@ <UNDEFINED> instruction: 0xffcc4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3cc2a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x25fa24>
│ │  	beq.n	3cbe18 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f594>
│ │  	b.n	3cc22c <uniffi_pbcli_checksum_method_api_base@@Base+0x25f9a8>
│ │  	adds	r0, #28
│ │  	b.n	3cb8b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f02c>
│ │ @@ -1120093,19 +1120093,19 @@
│ │  	and.w	r0, r0, r0, lsl #28
│ │  	b.n	3cc6be <uniffi_pbcli_checksum_method_api_base@@Base+0x25fe3a>
│ │  	movs	r7, r0
│ │  	b.n	3cc2c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x25fa3e>
│ │  	beq.n	3cbfbc <uniffi_pbcli_checksum_method_api_base@@Base+0x25f738>
│ │  	b.n	3cc41c <uniffi_pbcli_checksum_method_api_base@@Base+0x25fb98>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r2, r4, r5, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r4, r6, fp, ip, lr, pc}
│ │  	vrshr.u8	q12, <illegal reg q13.5>, #4
│ │ -	vmlsl.u16	<illegal reg q14.5>, d18, d0[2]
│ │ +	vabdl.u16	<illegal reg q14.5>, d2, d7
│ │  	vrshr.u8	d18, d7, #4
│ │ -	vqshlu.s64	d29, d16, #12
│ │ +	vqshlu.s64	<illegal reg q14.5>, <illegal reg q3.5>, #12
│ │  			@ <UNDEFINED> instruction: 0xffcc4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3cc4c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x25fc3c>
│ │  	beq.n	3cc048 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f7c4>
│ │  	b.n	3cc444 <uniffi_pbcli_checksum_method_api_base@@Base+0x25fbc0>
│ │  	str	r1, [r0, #0]
│ │  	b.n	3cc2ee <uniffi_pbcli_checksum_method_api_base@@Base+0x25fa6a>
│ │ @@ -1120226,18 +1120226,18 @@
│ │  	b.n	3cc7f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x25ff6e>
│ │  	cmp	r3, #240	@ 0xf0
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3cc3fa <uniffi_pbcli_checksum_method_api_base@@Base+0x25fb76>
│ │  	beq.n	3cc0ec <uniffi_pbcli_checksum_method_api_base@@Base+0x25f868>
│ │  	b.n	3cc554 <uniffi_pbcli_checksum_method_api_base@@Base+0x25fcd0>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r2, r3, r7, r8, sl, ip, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffccbf20
│ │ +	ldmia.w	sp!, {r0, r1, r4, r5, r7, r8, sl, ip, lr, pc}
│ │ +	vqrdmlsh.s<illegal width 8>	<illegal reg q13.5>, q6, d3[1]
│ │  	vsubl.u8	q14, d12, d16
│ │ -	vsri.8	d19, d25, #6
│ │ +	vmls.i<illegal width 8>	<illegal reg q9.5>, q5, d0[4]
│ │  			@ <UNDEFINED> instruction: 0xffcd4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3cc5f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x25fd70>
│ │  	beq.n	3cc1a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f920>
│ │  	b.n	3cc578 <uniffi_pbcli_checksum_method_api_base@@Base+0x25fcf4>
│ │  	strh	r1, [r0, #0]
│ │  	b.n	3cc422 <uniffi_pbcli_checksum_method_api_base@@Base+0x25fb9e>
│ │ @@ -1120409,22 +1120409,22 @@
│ │  	b.n	3cc98e <uniffi_pbcli_checksum_method_api_base@@Base+0x26010a>
│ │  	movs	r4, r0
│ │  	b.n	3cc592 <uniffi_pbcli_checksum_method_api_base@@Base+0x25fd0e>
│ │  	beq.n	3cc28c <uniffi_pbcli_checksum_method_api_base@@Base+0x25fa08>
│ │  	b.n	3cc6ec <uniffi_pbcli_checksum_method_api_base@@Base+0x25fe68>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r1, r5, r6, r7, r8, r9, ip, sp, pc}
│ │ -	vmlal.u8	<illegal reg q11.5>, d27, d22
│ │ -			@ <UNDEFINED> instruction: 0xffcd18b4
│ │ +	vmul.i<illegal width 8>	<illegal reg q11.5>, <illegal reg q13.5>, d1[3]
│ │ +			@ <UNDEFINED> instruction: 0xffcd18db
│ │  	vraddhn.i16	d22, <illegal reg q14.5>, q9
│ │  			@ <UNDEFINED> instruction: 0xffcc37c3
│ │  			@ <UNDEFINED> instruction: 0xffcc9c33
│ │  	vqrdmlsh.s<illegal width 8>	q10, <illegal reg q5.5>, d3[6]
│ │  			@ <UNDEFINED> instruction: 0xffcb7f2b
│ │ -	vrshr.u64	<illegal reg q12.5>, <illegal reg q3.5>, #46
│ │ +	vrshr.u64	<illegal reg q12.5>, q15, #46
│ │  			@ <UNDEFINED> instruction: 0xffcc7ed3
│ │  	vqshrun.s32	d20, q8, #14
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3cc7a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x25ff20>
│ │  	asrs	r0, r6, #32
│ │  	b.n	3cbdcc <uniffi_pbcli_checksum_method_api_base@@Base+0x25f548>
│ │  	ands	r0, r0
│ │ @@ -1120446,15 +1120446,15 @@
│ │  	b.n	3cc5f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x25fd6e>
│ │  	ldrb	r6, [r5, #31]
│ │  	add.w	r0, r0, r8
│ │  	b.n	3cbdc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f540>
│ │  	movs	r5, r0
│ │  	b.n	3cc5fe <uniffi_pbcli_checksum_method_api_base@@Base+0x25fd7a>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r3, r6, r8, r9, sl, ip}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r5, r6, r8, r9, sl, ip}
│ │  			@ <UNDEFINED> instruction: 0xffcd48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3cc7e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x25ff64>
│ │  	ands	r2, r0
│ │  	b.n	3cc612 <uniffi_pbcli_checksum_method_api_base@@Base+0x25fd8e>
│ │  	str	r1, [r0, #0]
│ │  	b.n	3cc616 <uniffi_pbcli_checksum_method_api_base@@Base+0x25fd92>
│ │ @@ -1120523,15 +1120523,15 @@
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0}
│ │  	b.n	3ccb26 <uniffi_pbcli_checksum_method_api_base@@Base+0x2602a2>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r1, r2}
│ │  	b.n	3cc6ae <uniffi_pbcli_checksum_method_api_base@@Base+0x25fe2a>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r5, r7, r9, sl, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r3, r6, r7, r9, sl, ip, sp, lr}
│ │  	vsra.u64	<illegal reg q13.5>, <illegal reg q3.5>, #51
│ │  			@ <UNDEFINED> instruction: 0xffcb9a7b
│ │  			@ <UNDEFINED> instruction: 0xffcb4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3cc8a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x26001c>
│ │  	beq.n	3cc450 <uniffi_pbcli_checksum_method_api_base@@Base+0x25fbcc>
│ │  	b.n	3cc824 <uniffi_pbcli_checksum_method_api_base@@Base+0x25ffa0>
│ │ @@ -1120901,26 +1120901,26 @@
│ │  	movs	r0, r0
│ │  	b.n	3cc1b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f932>
│ │  	movs	r0, r2
│ │  	b.n	3cc1e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f962>
│ │  	movs	r0, r0
│ │  	b.n	3cc1b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x25f934>
│ │  			@ <UNDEFINED> instruction: 0xffdfeaff
│ │ -	asrs	r0, r2, #24
│ │ -	vmlal.u8	q15, d13, d9
│ │ +	asrs	r7, r6, #24
│ │ +	vqshrun.s16	d30, q8, #3
│ │  	vsli.8	<illegal reg q9.5>, q8, #4
│ │ -	vsli.8	<illegal reg q8.5>, q12, #4
│ │ -	vqshl.u8	q15, <illegal reg q8.5>, #5
│ │ +	vsli.64	d17, d15, #12
│ │ +	vqshl.u64	d30, d8, #13
│ │  			@ <UNDEFINED> instruction: 0xffcc4be3
│ │ -	vraddhn.i16	d17, q6, q6
│ │ +	vsri.8	d17, d19, #4
│ │  	vrshr.u8	<illegal reg q12.5>, q8, #3
│ │ -			@ <UNDEFINED> instruction: 0xffcb13c8
│ │ +			@ <UNDEFINED> instruction: 0xffcb13ef
│ │  	vsubl.u8	<illegal reg q12.5>, d13, d28
│ │ -	vmls.f<illegal width 8>	<illegal reg q8.5>, <illegal reg q13.5>, d0[6]
│ │ -	vmla.i<illegal width 8>	<illegal reg q11.5>, <illegal reg q14.5>, d1[5]
│ │ +	vrsubhn.i16	d17, <illegal reg q5.5>, <illegal reg q7.5>
│ │ +	vaddw.u8	<illegal reg q11.5>, <illegal reg q6.5>, d12
│ │  			@ <UNDEFINED> instruction: 0xffcd48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3ccc0c <uniffi_pbcli_checksum_method_api_base@@Base+0x260388>
│ │  	ands	r2, r0
│ │  	b.n	3cca36 <uniffi_pbcli_checksum_method_api_base@@Base+0x2601b2>
│ │  	str	r1, [r0, #0]
│ │  	b.n	3cca3a <uniffi_pbcli_checksum_method_api_base@@Base+0x2601b6>
│ │ @@ -1120991,15 +1120991,15 @@
│ │  	asrs	r4, r0, #32
│ │  	b.n	3ccaca <uniffi_pbcli_checksum_method_api_base@@Base+0x260246>
│ │  	ldr	r0, [pc, #960]	@ (3ccb4c <uniffi_pbcli_checksum_method_api_base@@Base+0x2602c8>)
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r5, r7}
│ │  	and.w	r0, r0, r1
│ │  	b.n	3ccf56 <uniffi_pbcli_checksum_method_api_base@@Base+0x2606d2>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r3, r5, r6, r9, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r4, r7, r9, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffcdad9f
│ │  	vmlsl.u<illegal width 8>	<illegal reg q12.5>, d11, d3[0]
│ │  			@ <UNDEFINED> instruction: 0xffcb4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3cccc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x260444>
│ │  	beq.n	3cc858 <uniffi_pbcli_checksum_method_api_base@@Base+0x25ffd4>
│ │  	b.n	3ccc4c <uniffi_pbcli_checksum_method_api_base@@Base+0x2603c8>
│ │ @@ -1121238,24 +1121238,24 @@
│ │  	movs	r0, r2
│ │  	b.n	3cc4f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x25fc6e>
│ │  	movs	r0, r0
│ │  	b.n	3cc4ca <uniffi_pbcli_checksum_method_api_base@@Base+0x25fc46>
│ │  	ands	r1, r0
│ │  	b.n	3cd106 <uniffi_pbcli_checksum_method_api_base@@Base+0x260882>
│ │  			@ <UNDEFINED> instruction: 0xffeaeaff
│ │ -	asrs	r4, r5, #7
│ │ +	asrs	r3, r2, #8
│ │  			@ <UNDEFINED> instruction: 0xffcd4923
│ │  	vmla.f<illegal width 8>	<illegal reg q9.5>, <illegal reg q5.5>, d0[1]
│ │ -	vaddl.u8	<illegal reg q8.5>, d28, d20
│ │ +	vmla.i<illegal width 8>	<illegal reg q8.5>, q14, d3[2]
│ │  	vqshl.u64	q10, <illegal reg q5.5>, #13
│ │  	vaddl.u8	q8, d27, d11
│ │ -	vrsra.u8	d25, d6, #5
│ │ -	vshr.u64	<illegal reg q8.5>, q4, #52
│ │ +	vrsra.u8	d25, d29, #5
│ │ +	vshr.u64	<illegal reg q8.5>, <illegal reg q15.5>, #52
│ │  			@ <UNDEFINED> instruction: 0xffcd8f3c
│ │ -	vsra.u64	d17, d28, #53
│ │ +	vmla.f<illegal width 8>	<illegal reg q8.5>, <illegal reg q13.5>, d3[4]
│ │  	vqshrun.s16	d23, <illegal reg q6.5>, #3
│ │  			@ <UNDEFINED> instruction: 0xffcb4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3ccf18 <uniffi_pbcli_checksum_method_api_base@@Base+0x260694>
│ │  	ands	r0, r0
│ │  	b.n	3ccd42 <uniffi_pbcli_checksum_method_api_base@@Base+0x2604be>
│ │  	movs	r0, r3
│ │ @@ -1121287,15 +1121287,15 @@
│ │  	b.n	3ccd7e <uniffi_pbcli_checksum_method_api_base@@Base+0x2604fa>
│ │  	asrs	r5, r0, #32
│ │  	b.n	3ccd82 <uniffi_pbcli_checksum_method_api_base@@Base+0x2604fe>
│ │  	movs	r0, #176	@ 0xb0
│ │  	b.n	3cd186 <uniffi_pbcli_checksum_method_api_base@@Base+0x260902>
│ │  	ldr	r4, [pc, #448]	@ (3ccc08 <uniffi_pbcli_checksum_method_api_base@@Base+0x260384>)
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r8, lr}
│ │ -			@ <UNDEFINED> instruction: 0xeafd0fd0
│ │ +			@ <UNDEFINED> instruction: 0xeafd0ff7
│ │  			@ <UNDEFINED> instruction: 0xffcd4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3ccf74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2606f0>
│ │  	beq.n	3cca6c <uniffi_pbcli_checksum_method_api_base@@Base+0x2601e8>
│ │  	b.n	3ccef8 <uniffi_pbcli_checksum_method_api_base@@Base+0x260674>
│ │  	ands	r0, r0
│ │  	b.n	3cd1a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x26091e>
│ │ @@ -1121400,16 +1121400,16 @@
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	3cd1d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x260952>
│ │  			@ <UNDEFINED> instruction: 0xffdd1aff
│ │  	ands	r0, r0
│ │  	b.n	3cd27e <uniffi_pbcli_checksum_method_api_base@@Base+0x2609fa>
│ │  			@ <UNDEFINED> instruction: 0xfff4eaff
│ │  	ldcl	15, cr15, [fp], #812	@ 0x32c
│ │ -	lsrs	r0, r4, #28
│ │ -			@ <UNDEFINED> instruction: 0xffcd69f7
│ │ +	lsrs	r7, r0, #29
│ │ +	vshll.u8	q11, d14, #5
│ │  	vaddl.u8	q8, d13, d4
│ │  	b.n	3cc690 <uniffi_pbcli_checksum_method_api_base@@Base+0x25fe0c>
│ │  	movs	r0, r0
│ │  	b.n	3ccc74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2603f0>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldmia	r7, {r3, r4, r5, r6, r7}
│ │  	movs	r7, r1
│ │ @@ -1121575,15 +1121575,15 @@
│ │  	ldr	r3, [pc, #960]	@ (3cd078 <uniffi_pbcli_checksum_method_api_base@@Base+0x2607f4>)
│ │  	ldmia.w	sp!, {r2, r5, r6, r8, r9, sl, fp, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeaff7001
│ │  	b.n	3cd482 <uniffi_pbcli_checksum_method_api_base@@Base+0x260bfe>
│ │  	movs	r7, r0
│ │  	b.n	3cd006 <uniffi_pbcli_checksum_method_api_base@@Base+0x260782>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r1, r2, r4, r7, r8, sl, fp, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r5, r7, r8, sl, fp, sp, lr}
│ │  	vmul.i<illegal width 8>	q13, <illegal reg q14.5>, d3[2]
│ │  	vmla.f<illegal width 8>	<illegal reg q12.5>, <illegal reg q5.5>, d3[7]
│ │  			@ <UNDEFINED> instruction: 0xffcb4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3cd1f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x260974>
│ │  	svc	97	@ 0x61
│ │  	b.n	3cd17c <uniffi_pbcli_checksum_method_api_base@@Base+0x2608f8>
│ │ @@ -1121897,19 +1121897,19 @@
│ │  			@ <UNDEFINED> instruction: 0xff98eaff
│ │  	lsls	r2, r4, #1
│ │  	b.n	3cd418 <uniffi_pbcli_checksum_method_api_base@@Base+0x260b94>
│ │  	asrs	r5, r0, #32
│ │  	b.n	3cd2c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x260a42>
│ │  	lsrs	r4, r5, #15
│ │  			@ <UNDEFINED> instruction: 0xebfdff94
│ │ -			@ <UNDEFINED> instruction: 0xeaff0c48
│ │ +			@ <UNDEFINED> instruction: 0xeaff0c6f
│ │  	vmlsl.u8	q12, d29, d28
│ │ -			@ <UNDEFINED> instruction: 0xffcb4fd0
│ │ +			@ <UNDEFINED> instruction: 0xffcb4ff7
│ │  	vsra.u64	<illegal reg q11.5>, <illegal reg q13.5>, #51
│ │ -	vsri.16	<illegal reg q15.5>, q8, #14
│ │ +	vsri.64	d31, d7, #46
│ │  	vaddw.u8	<illegal reg q11.5>, q14, d27
│ │  	vaddl.u16	q8, d2, d0
│ │  	b.n	3cd64a <uniffi_pbcli_checksum_method_api_base@@Base+0x260dc6>
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r0, [pc, #0]	@ (3ccfb4 <uniffi_pbcli_checksum_method_api_base@@Base+0x260730>)
│ │ @@ -1121963,15 +1121963,15 @@
│ │  	asrs	r0, r1, #32
│ │  	b.n	3ccb32 <uniffi_pbcli_checksum_method_api_base@@Base+0x2602ae>
│ │  	movs	r0, r0
│ │  	b.n	3ccb36 <uniffi_pbcli_checksum_method_api_base@@Base+0x2602b2>
│ │  	movs	r5, r0
│ │  	b.n	3cd36e <uniffi_pbcli_checksum_method_api_base@@Base+0x260aea>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r3, r4, r6, r7, sl, pc}
│ │ +	ldmia.w	sp!, {r0, r8, sl, pc}
│ │  	vmlsl.u8	<illegal reg q9.5>, d12, d1
│ │  	b.n	3cd77a <uniffi_pbcli_checksum_method_api_base@@Base+0x260ef6>
│ │  	lsls	r4, r2, #5
│ │  	and.w	pc, r0, r0, ror #19
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3cd560 <uniffi_pbcli_checksum_method_api_base@@Base+0x260cdc>
│ │  	beq.n	3cd060 <uniffi_pbcli_checksum_method_api_base@@Base+0x2607dc>
│ │ @@ -1122233,18 +1122233,18 @@
│ │  			@ <UNDEFINED> instruction: 0xebfaffea
│ │  			@ <UNDEFINED> instruction: 0xeaff000a
│ │  	b.n	3cd5ca <uniffi_pbcli_checksum_method_api_base@@Base+0x260d46>
│ │  	asrs	r4, r0, #32
│ │  	b.n	3cd5ce <uniffi_pbcli_checksum_method_api_base@@Base+0x260d4a>
│ │  	lsrs	r2, r5, #12
│ │  			@ <UNDEFINED> instruction: 0xebfdffe6
│ │ -			@ <UNDEFINED> instruction: 0xeaff828a
│ │ -	vsubl.u8	q11, d28, d20
│ │ -	vraddhn.i16	d24, <illegal reg q6.5>, q11
│ │ -	vmls.i<illegal width 8>	q11, q6, d0[0]
│ │ +			@ <UNDEFINED> instruction: 0xeaff82b1
│ │ +	vmlal.u<illegal width 8>	q11, d28, d3[2]
│ │ +	vmls.i<illegal width 8>	q12, <illegal reg q6.5>, d1[3]
│ │ +	vmls.i<illegal width 8>	q11, q6, d3[5]
│ │  	vmlsl.u8	<illegal reg q9.5>, d13, d2
│ │  	b.n	3cd9ea <uniffi_pbcli_checksum_method_api_base@@Base+0x261166>
│ │  	lsls	r0, r7, #2
│ │  	and.w	sp, r0, r0, ror #19
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3cd7d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x260f4c>
│ │  	beq.n	3cd2c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x260a44>
│ │ @@ -1122393,19 +1122393,19 @@
│ │  	b.n	3cdb32 <uniffi_pbcli_checksum_method_api_base@@Base+0x2612ae>
│ │  	movs	r7, #32
│ │  			@ <UNDEFINED> instruction: 0xebfc0007
│ │  	b.n	3cd73a <uniffi_pbcli_checksum_method_api_base@@Base+0x260eb6>
│ │  	beq.n	3cd42c <uniffi_pbcli_checksum_method_api_base@@Base+0x260ba8>
│ │  	b.n	3cd894 <uniffi_pbcli_checksum_method_api_base@@Base+0x261010>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r1, r8, pc}
│ │ +	ldmia.w	sp!, {r0, r3, r5, r8, pc}
│ │  	vabal.u8	q9, d28, d13
│ │ -	vmla.f<illegal width 8>	q12, q6, d2[5]
│ │ +	vaddw.u8	q12, q14, d13
│ │  	vsli.64	q9, <illegal reg q8.5>, #12
│ │ -	vaddw.u8	q12, q14, d30
│ │ +	vsra.u64	q12, <illegal reg q2.5>, #52
│ │  	vqshlu.s8	d18, d25, #4
│ │  			@ <UNDEFINED> instruction: 0xffcc4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3cd93c <uniffi_pbcli_checksum_method_api_base@@Base+0x2610b8>
│ │  	ands	r0, r0
│ │  	b.n	3cd766 <uniffi_pbcli_checksum_method_api_base@@Base+0x260ee2>
│ │  	movs	r4, r0
│ │ @@ -1122417,15 +1122417,15 @@
│ │  	b.n	3cd776 <uniffi_pbcli_checksum_method_api_base@@Base+0x260ef2>
│ │  	movs	r0, #106	@ 0x6a
│ │  	b.n	3cdb7a <uniffi_pbcli_checksum_method_api_base@@Base+0x2612f6>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3cd55c <uniffi_pbcli_checksum_method_api_base@@Base+0x260cd8>
│ │  	ldr	r4, [pc, #64]	@ (3cd480 <uniffi_pbcli_checksum_method_api_base@@Base+0x260bfc>)
│ │  	ldmia.w	sp!, {r0, r5, r7, r9, sl, fp, ip, sp}
│ │ -			@ <UNDEFINED> instruction: 0xeafd809e
│ │ +			@ <UNDEFINED> instruction: 0xeafd80c5
│ │  			@ <UNDEFINED> instruction: 0xffcc4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3cd96c <uniffi_pbcli_checksum_method_api_base@@Base+0x2610e8>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3cd796 <uniffi_pbcli_checksum_method_api_base@@Base+0x260f12>
│ │  	lsrs	r1, r7, #3
│ │  			@ <UNDEFINED> instruction: 0xebff4000
│ │ @@ -1122477,16 +1122477,16 @@
│ │  	b.n	3cdc02 <uniffi_pbcli_checksum_method_api_base@@Base+0x26137e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3cd5e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x260d60>
│ │  	subs	r6, #128	@ 0x80
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3cd80e <uniffi_pbcli_checksum_method_api_base@@Base+0x260f8a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r2, r5, r6, pc}
│ │ -	vshr.u8	d24, d6, #4
│ │ +	ldmia.w	sp!, {r0, r2, r3, r7, pc}
│ │ +	vshr.u8	d24, d29, #4
│ │  	vaddl.u8	q8, d12, d0
│ │  	b.n	3cdb7e <uniffi_pbcli_checksum_method_api_base@@Base+0x2612fa>
│ │  	movs	r1, r0
│ │  	asrs	r0, r0, #12
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r4, r0
│ │  	b.n	3cd028 <uniffi_pbcli_checksum_method_api_base@@Base+0x2607a4>
│ │ @@ -1122551,16 +1122551,16 @@
│ │  	movs	r0, r1
│ │  	b.n	3cd078 <uniffi_pbcli_checksum_method_api_base@@Base+0x2607f4>
│ │  	ands	r1, r0
│ │  	b.n	3cdcb2 <uniffi_pbcli_checksum_method_api_base@@Base+0x26142e>
│ │  	movs	r4, r0
│ │  	b.n	3cd8b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x261032>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r5, r7, r8, r9, sl, fp, ip, lr}
│ │ -	vmla.i<illegal width 8>	q14, <illegal reg q14.5>, d0[6]
│ │ +	ldmia.w	sp!, {r1, r5, r6, r7, r8, r9, sl, fp, ip, lr}
│ │ +	vaddw.u8	q14, <illegal reg q6.5>, d15
│ │  	vaddl.u8	q8, d12, d4
│ │  	b.n	3cd0c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x260840>
│ │  	movs	r0, r0
│ │  	b.n	3cd6a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x260e24>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	stmia	r6!, {r5, r6}
│ │  	movs	r7, r1
│ │ @@ -1122654,16 +1122654,16 @@
│ │  	movs	r0, r0
│ │  	b.n	3cdd9e <uniffi_pbcli_checksum_method_api_base@@Base+0x26151a>
│ │  	movs	r0, r1
│ │  	b.n	3cd16c <uniffi_pbcli_checksum_method_api_base@@Base+0x2608e8>
│ │  	ands	r1, r0
│ │  	b.n	3cdda6 <uniffi_pbcli_checksum_method_api_base@@Base+0x261522>
│ │  			@ <UNDEFINED> instruction: 0xffd8eaff
│ │ -	ldrsh	r3, [r7, r2]
│ │ -	vqrdmlsh.s<illegal width 8>	<illegal reg q13.5>, <illegal reg q14.5>, d0[7]
│ │ +	ldrsh	r2, [r4, r3]
│ │ +	vshr.u8	d28, d3, #3
│ │  	vqshrun.s16	d20, q8, #4
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3cdb94 <uniffi_pbcli_checksum_method_api_base@@Base+0x261310>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3cd9be <uniffi_pbcli_checksum_method_api_base@@Base+0x26113a>
│ │  	lsrs	r7, r5, #1
│ │  			@ <UNDEFINED> instruction: 0xebff4000
│ │ @@ -1122865,20 +1122865,20 @@
│ │  	b.n	3cdb7e <uniffi_pbcli_checksum_method_api_base@@Base+0x2612fa>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0}
│ │  	b.n	3cdf86 <uniffi_pbcli_checksum_method_api_base@@Base+0x261702>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r1, r2, r4, r5, r9, fp, ip, lr}
│ │  	vqrdmulh.s<illegal width 8>	<illegal reg q15.5>, q14, d2[6]
│ │ -	vshr.u8	d21, d6, #6
│ │ +	vshr.u8	d21, d29, #6
│ │  			@ <UNDEFINED> instruction: 0xffcd2bc6
│ │  			@ <UNDEFINED> instruction: 0xffcc0d36
│ │  	vaddw.u8	q13, q14, d19
│ │  	vshll.u8	q13, d28, #3
│ │ -	vqdmulh.s<illegal width 8>	<illegal reg q8.5>, q5, d1[5]
│ │ +	vmull.u8	<illegal reg q8.5>, d26, d12
│ │  	vqrshrn.u16	d16, q9, #3
│ │  			@ <UNDEFINED> instruction: 0xffcb390f
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3cd3b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x260b30>
│ │  	movs	r0, r0
│ │  	b.n	3cd998 <uniffi_pbcli_checksum_method_api_base@@Base+0x261114>
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -1123201,15 +1123201,15 @@
│ │  	b.n	3ce286 <uniffi_pbcli_checksum_method_api_base@@Base+0x261a02>
│ │  	movs	r0, #2
│ │  	b.n	3cdc68 <uniffi_pbcli_checksum_method_api_base@@Base+0x2613e4>
│ │  	movs	r5, #74	@ 0x4a
│ │  			@ <UNDEFINED> instruction: 0xebfcff56
│ │  			@ <UNDEFINED> instruction: 0xeaff0662
│ │  	vqshrun.s16	d24, q15, #5
│ │ -			@ <UNDEFINED> instruction: 0xffcdbaf7
│ │ +			@ <UNDEFINED> instruction: 0xffcdbb1e
│ │  	vqrdmlah.s<illegal width 8>	q8, q14, d0[3]
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │  	b.n	3ce206 <uniffi_pbcli_checksum_method_api_base@@Base+0x261982>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (3cdc2c <uniffi_pbcli_checksum_method_api_base@@Base+0x2613a8>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │ @@ -1123431,15 +1123431,15 @@
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3ce496 <uniffi_pbcli_checksum_method_api_base@@Base+0x261c12>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r5, r6, r7, r8, sl, ip, lr}
│ │  			@ <UNDEFINED> instruction: 0xffcc0f32
│ │  	vmlsl.u<illegal width 8>	q9, d12, d1[0]
│ │ -	vrshr.u8	d24, d21, #4
│ │ +	vrshr.u8	q12, q6, #4
│ │  	vaddl.u8	q8, d12, d4
│ │  	b.n	3cd8ac <uniffi_pbcli_checksum_method_api_base@@Base+0x261028>
│ │  	movs	r0, r0
│ │  	b.n	3cde90 <uniffi_pbcli_checksum_method_api_base@@Base+0x26160c>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	stmia	r0!, {r7}
│ │  	movs	r7, r1
│ │ @@ -1123484,15 +1123484,15 @@
│ │  	b.n	3ce10e <uniffi_pbcli_checksum_method_api_base@@Base+0x26188a>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, lr}
│ │  	b.n	3ce516 <uniffi_pbcli_checksum_method_api_base@@Base+0x261c92>
│ │  	movs	r4, r0
│ │  	b.n	3ce11a <uniffi_pbcli_checksum_method_api_base@@Base+0x261896>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r5, r6, r8, pc}
│ │ +	ldmia.w	sp!, {r4, r7, r8, pc}
│ │  	vaddl.u8	q8, d12, d4
│ │  	b.n	3cd924 <uniffi_pbcli_checksum_method_api_base@@Base+0x2610a0>
│ │  	movs	r0, r0
│ │  	b.n	3cdf08 <uniffi_pbcli_checksum_method_api_base@@Base+0x261684>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	stmia	r1!, {r2, r3, r4, r6}
│ │  	movs	r7, r1
│ │ @@ -1124398,23 +1124398,23 @@
│ │  	movs	r1, r0
│ │  	b.n	3ced0a <uniffi_pbcli_checksum_method_api_base@@Base+0x262486>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3ced12 <uniffi_pbcli_checksum_method_api_base@@Base+0x26248e>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r1, r2, r4, r5, r7, r8, ip, sp, lr, pc}
│ │ -	vrsra.u64	q10, q1, #54
│ │ +	vrsra.u64	q10, <illegal reg q12.5>, #54
│ │  			@ <UNDEFINED> instruction: 0xffcd1f72
│ │  	vshr.u64	q8, q1, #52
│ │  	vqrdmulh.s<illegal width 8>	<illegal reg q15.5>, q6, d2[0]
│ │  			@ <UNDEFINED> instruction: 0xffcafbde
│ │  	vsri.64	<illegal reg q12.5>, <illegal reg q13.5>, #54
│ │  			@ <UNDEFINED> instruction: 0xffcb9d84
│ │  	vqdmulh.s<illegal width 8>	<illegal reg q15.5>, q13, d2[1]
│ │ -	vqrdmlsh.s<illegal width 8>	q8, q5, d1[6]
│ │ +			@ <UNDEFINED> instruction: 0xffca0f90
│ │  	vqdmulh.s<illegal width 8>	<illegal reg q15.5>, <illegal reg q6.5>, d2[6]
│ │  	vmull.u8	q10, d10, d22
│ │  			@ <UNDEFINED> instruction: 0xffccfc1a
│ │  	vsli.64	d17, d18, #10
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3ce150 <uniffi_pbcli_checksum_method_api_base@@Base+0x2618cc>
│ │  	movs	r0, r0
│ │ @@ -1124710,23 +1124710,23 @@
│ │  	b.n	3cefd6 <uniffi_pbcli_checksum_method_api_base@@Base+0x262752>
│ │  	ands	r0, r0
│ │  	b.n	3cefda <uniffi_pbcli_checksum_method_api_base@@Base+0x262756>
│ │  	movs	r1, #246	@ 0xf6
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3cebe2 <uniffi_pbcli_checksum_method_api_base@@Base+0x26235e>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r3, r4, r7, r8, sl, sp}
│ │ -	vrsra.u8	q15, <illegal reg q12.5>, #3
│ │ -			@ <UNDEFINED> instruction: 0xffcc9edc
│ │ +	ldmia.w	sp!, {r6, r7, r8, sl, sp}
│ │ +	vsubw.u8	q15, <illegal reg q14.5>, d16
│ │ +			@ <UNDEFINED> instruction: 0xffcc9f03
│ │  			@ <UNDEFINED> instruction: 0xffccf90e
│ │  	vqshl.u64	<illegal reg q13.5>, q13, #10
│ │  	vmul.f<illegal width 8>	<illegal reg q15.5>, <illegal reg q13.5>, d2[6]
│ │  			@ <UNDEFINED> instruction: 0xffcab8d6
│ │  			@ <UNDEFINED> instruction: 0xffcba925
│ │ -			@ <UNDEFINED> instruction: 0xffcb0eb1
│ │ +			@ <UNDEFINED> instruction: 0xffcb0ed8
│ │  			@ <UNDEFINED> instruction: 0xffcd4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3cedec <uniffi_pbcli_checksum_method_api_base@@Base+0x262568>
│ │  	beq.n	3ce994 <uniffi_pbcli_checksum_method_api_base@@Base+0x262110>
│ │  	b.n	3ced70 <uniffi_pbcli_checksum_method_api_base@@Base+0x2624ec>
│ │  	movs	r4, r2
│ │  	b.n	3ce2f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x261a6c>
│ │ @@ -1124782,15 +1124782,15 @@
│ │  	b.n	3ce47a <uniffi_pbcli_checksum_method_api_base@@Base+0x261bf6>
│ │  	asrs	r4, r0, #1
│ │  	b.n	3ce47e <uniffi_pbcli_checksum_method_api_base@@Base+0x261bfa>
│ │  	vrhadd.u<illegal width 64>	d14, d2, d31
│ │  	beq.n	3ce97c <uniffi_pbcli_checksum_method_api_base@@Base+0x2620f8>
│ │  	b.n	3cedf4 <uniffi_pbcli_checksum_method_api_base@@Base+0x262570>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r4, r6, r8, fp, sp}
│ │ +	ldmia.w	sp!, {r1, r3, r4, r5, r6, r8, fp, sp}
│ │  			@ <UNDEFINED> instruction: 0xffcda987
│ │  			@ <UNDEFINED> instruction: 0xffcb4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3cee8c <uniffi_pbcli_checksum_method_api_base@@Base+0x262608>
│ │  	ands	r0, r0
│ │  	b.n	3cecb6 <uniffi_pbcli_checksum_method_api_base@@Base+0x262432>
│ │  	lsls	r1, r6, #14
│ │ @@ -1124895,16 +1124895,16 @@
│ │  	blx	7cf0a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x66281c>
│ │  			@ <UNDEFINED> instruction: 0xffffffff
│ │  	movs	r2, r0
│ │  	movs	r0, r0
│ │  			@ <UNDEFINED> instruction: 0xffffffff
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │ -	str	r5, [r0, #40]	@ 0x28
│ │ -	vsubl.u8	q11, d13, d17
│ │ +	str	r4, [r5, #40]	@ 0x28
│ │ +	vmlal.u<illegal width 8>	q11, d13, d0[2]
│ │  	vqshrun.s16	d20, q8, #3
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3cef9c <uniffi_pbcli_checksum_method_api_base@@Base+0x262718>
│ │  	str	r1, [r0, r0]
│ │  	b.n	3cedc6 <uniffi_pbcli_checksum_method_api_base@@Base+0x262542>
│ │  	ands	r0, r0
│ │  	b.n	3cedca <uniffi_pbcli_checksum_method_api_base@@Base+0x262546>
│ │ @@ -1125292,33 +1125292,33 @@
│ │  	lsrs	r0, r0, #8
│ │  	strh	r0, [r3, #0]
│ │  	b.n	3ce8dc <uniffi_pbcli_checksum_method_api_base@@Base+0x262058>
│ │  			@ <UNDEFINED> instruction: 0xffaeeaff
│ │  	movs	r0, r0
│ │  	b.n	3cf51a <uniffi_pbcli_checksum_method_api_base@@Base+0x262c96>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r3, r5, r6, r7, r8, sp}
│ │ -	vqrdmlsh.s<illegal width 8>	<illegal reg q14.5>, <illegal reg q14.5>, d1[2]
│ │ -			@ <UNDEFINED> instruction: 0xffcc6af4
│ │ -	vsra.u64	q15, q10, #51
│ │ +	ldmia.w	sp!, {r4, r9, sp}
│ │ +			@ <UNDEFINED> instruction: 0xffcddff0
│ │ +			@ <UNDEFINED> instruction: 0xffcc6b1b
│ │ +	vrshr.u8	d30, d11, #3
│ │  	vabdl.u8	<illegal reg q13.5>, d28, d8
│ │  	movs	r7, r1
│ │  			@ <UNDEFINED> instruction: 0xe98affca
│ │ -	subs	r3, #166	@ 0xa6
│ │ +	subs	r3, #205	@ 0xcd
│ │  			@ <UNDEFINED> instruction: 0xffcd1746
│ │  	vmlal.u8	<illegal reg q15.5>, d28, d22
│ │ -			@ <UNDEFINED> instruction: 0xffcb5ff5
│ │ -	vmull.p8	<illegal reg q10.5>, d29, d29
│ │ +	vshr.u8	d22, d12, #5
│ │ +			@ <UNDEFINED> instruction: 0xffcd5ed4
│ │  	vsri.64	d26, d9, #51
│ │  	vmull.u8	q12, d27, d23
│ │  	vsli.8	d25, d16, #3
│ │ -			@ <UNDEFINED> instruction: 0xffca5f51
│ │ -	vqshl.u8	d16, d5, #5
│ │ -			@ <UNDEFINED> instruction: 0xffcd5ef5
│ │ -	vshr.u64	q11, <illegal reg q14.5>, #51
│ │ +			@ <UNDEFINED> instruction: 0xffca5f78
│ │ +	vqshl.u8	d16, d28, #5
│ │ +			@ <UNDEFINED> instruction: 0xffcd5f1c
│ │ +	vaddw.u8	q11, <illegal reg q6.5>, d20
│ │  			@ <UNDEFINED> instruction: 0xffcdabd9
│ │  	vaddl.u8	q8, d10, d4
│ │  	b.n	3ce96c <uniffi_pbcli_checksum_method_api_base@@Base+0x2620e8>
│ │  	movs	r0, r0
│ │  	b.n	3cef50 <uniffi_pbcli_checksum_method_api_base@@Base+0x2626cc>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	adds	r3, #56	@ 0x38
│ │ @@ -1125578,17 +1125578,17 @@
│ │  	b.n	3cf7ae <uniffi_pbcli_checksum_method_api_base@@Base+0x262f2a>
│ │  	movs	r0, #2
│ │  	b.n	3cf190 <uniffi_pbcli_checksum_method_api_base@@Base+0x26290c>
│ │  	movs	r0, #0
│ │  			@ <UNDEFINED> instruction: 0xebfcff81
│ │  			@ <UNDEFINED> instruction: 0xeaff09b8
│ │  	movs	r0, r0
│ │ -	ldrb	r1, [r3, r0]
│ │ +	ldrb	r0, [r0, r1]
│ │  			@ <UNDEFINED> instruction: 0xffcdd9a6
│ │ -	vmls.f<illegal width 8>	q13, q13, d3[3]
│ │ +	vsli.64	q13, q11, #10
│ │  	vaddl.u8	q8, d12, d0
│ │  	b.n	3cf72e <uniffi_pbcli_checksum_method_api_base@@Base+0x262eaa>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (3cf154 <uniffi_pbcli_checksum_method_api_base@@Base+0x2628d0>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3cf5b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x262d30>
│ │  	str	r4, [r1, r1]
│ │ @@ -1125624,15 +1125624,15 @@
│ │  	b.n	3cf41e <uniffi_pbcli_checksum_method_api_base@@Base+0x262b9a>
│ │  	asrs	r5, r0, #32
│ │  	b.n	3cf422 <uniffi_pbcli_checksum_method_api_base@@Base+0x262b9e>
│ │  	movs	r2, #187	@ 0xbb
│ │  	b.n	3cf6e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x262e62>
│ │  	ldr	r0, [pc, #192]	@ (3cf1a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x262924>)
│ │  	ldmia.w	sp!, {r0, r1, r2, r4, r5, r6, r8, r9, sl, ip, sp}
│ │ -			@ <UNDEFINED> instruction: 0xeafd5bbd
│ │ +			@ <UNDEFINED> instruction: 0xeafd5be4
│ │  	vqshrun.s16	d20, q8, #3
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3cf614 <uniffi_pbcli_checksum_method_api_base@@Base+0x262d90>
│ │  	str	r1, [r0, r0]
│ │  	b.n	3cf43e <uniffi_pbcli_checksum_method_api_base@@Base+0x262bba>
│ │  	ands	r0, r0
│ │  	b.n	3cf442 <uniffi_pbcli_checksum_method_api_base@@Base+0x262bbe>
│ │ @@ -1125844,16 +1125844,16 @@
│ │  	b.n	3cfa0a <uniffi_pbcli_checksum_method_api_base@@Base+0x263186>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │  	lsrs	r3, r0
│ │  	vmlsl.u8	<illegal reg q15.5>, d12, d6
│ │  	vsra.u8	d17, d5, #5
│ │  			@ <UNDEFINED> instruction: 0xffccf9a4
│ │  	vaddw.u8	<illegal reg q15.5>, <illegal reg q13.5>, d7
│ │ -	vsubl.u8	<illegal reg q9.5>, d27, d22
│ │ -			@ <UNDEFINED> instruction: 0xffcd68fa
│ │ +	vmlal.u<illegal width 8>	<illegal reg q9.5>, d27, d1[3]
│ │ +			@ <UNDEFINED> instruction: 0xffcd6921
│ │  	vaddl.u8	q8, d12, d4
│ │  	b.n	3cee2c <uniffi_pbcli_checksum_method_api_base@@Base+0x2625a8>
│ │  	movs	r0, r0
│ │  	b.n	3cf410 <uniffi_pbcli_checksum_method_api_base@@Base+0x262b8c>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	add	sp, #384	@ 0x180
│ │  	movs	r7, r1
│ │ @@ -1126472,16 +1126472,16 @@
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	and.w	r0, r0, r0, lsl #20
│ │  	b.n	3cff86 <uniffi_pbcli_checksum_method_api_base@@Base+0x263702>
│ │  	movs	r2, r1
│ │  	b.n	3cfb8a <uniffi_pbcli_checksum_method_api_base@@Base+0x263306>
│ │  	bics	r1, r7
│ │  			@ <UNDEFINED> instruction: 0xebfdffb4
│ │ -			@ <UNDEFINED> instruction: 0xeaff2d26
│ │ -			@ <UNDEFINED> instruction: 0xffcd63ca
│ │ +			@ <UNDEFINED> instruction: 0xeaff2d4d
│ │ +	vrsra.u64	q11, <illegal reg q8.5>, #51
│ │  	vaddl.u8	q9, d28, d4
│ │  	b.n	3cfc7e <uniffi_pbcli_checksum_method_api_base@@Base+0x2633fa>
│ │  	asrs	r4, r2, #32
│ │  	b.n	3cf3a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x262b1c>
│ │  	movs	r0, #1
│ │  	asrs	r0, r0, #12
│ │  	movs	r3, r0
│ │ @@ -1126575,15 +1126575,15 @@
│ │  	b.n	3cf462 <uniffi_pbcli_checksum_method_api_base@@Base+0x262bde>
│ │  	asrs	r0, r7, #32
│ │  	b.n	3cf466 <uniffi_pbcli_checksum_method_api_base@@Base+0x262be2>
│ │  	vrhadd.u<illegal width 64>	d14, d2, d31
│ │  	beq.n	3cf964 <uniffi_pbcli_checksum_method_api_base@@Base+0x2630e0>
│ │  	b.n	3cfddc <uniffi_pbcli_checksum_method_api_base@@Base+0x263558>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r3, r5, r6, r8, fp, ip}
│ │ +	ldmia.w	sp!, {r1, r4, r7, r8, fp, ip}
│ │  			@ <UNDEFINED> instruction: 0xffcd999f
│ │  			@ <UNDEFINED> instruction: 0xffcb4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3cfe74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2635f0>
│ │  	str	r1, [r0, r0]
│ │  	b.n	3cfc9e <uniffi_pbcli_checksum_method_api_base@@Base+0x26341a>
│ │  	asrs	r2, r0, #32
│ │ @@ -1126691,16 +1126691,16 @@
│ │  	b.n	3cfcf4 <uniffi_pbcli_checksum_method_api_base@@Base+0x263470>
│ │  			@ <UNDEFINED> instruction: 0xffeebaff
│ │  	str	r6, [r4, r1]
│ │  	b.n	3d0192 <uniffi_pbcli_checksum_method_api_base@@Base+0x26390e>
│ │  	str	r5, [r4, #0]
│ │  	b.n	3d0196 <uniffi_pbcli_checksum_method_api_base@@Base+0x263912>
│ │  			@ <UNDEFINED> instruction: 0xffddeaff
│ │ -	strh	r0, [r5, #46]	@ 0x2e
│ │ -	vshr.u8	d23, d6, #4
│ │ +	strh	r7, [r1, #48]	@ 0x30
│ │ +	vshr.u8	d23, d29, #4
│ │  			@ <UNDEFINED> instruction: 0xffcc48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3cff84 <uniffi_pbcli_checksum_method_api_base@@Base+0x263700>
│ │  	str	r1, [r0, #0]
│ │  	b.n	3cfdae <uniffi_pbcli_checksum_method_api_base@@Base+0x26352a>
│ │  	asrs	r2, r0, #32
│ │  	b.n	3cfdb2 <uniffi_pbcli_checksum_method_api_base@@Base+0x26352e>
│ │ @@ -1127010,15 +1127010,15 @@
│ │  	str	r0, [r0, r0]
│ │  	b.n	3d046e <uniffi_pbcli_checksum_method_api_base@@Base+0x263bea>
│ │  	adds	r1, r2, #3
│ │  			@ <UNDEFINED> instruction: 0xebfc0005
│ │  	b.n	3d0076 <uniffi_pbcli_checksum_method_api_base@@Base+0x2637f2>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r2, r5, r6, sl, fp, ip, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffcb0a7b
│ │ +	vmlsl.u8	q8, d27, d18
│ │  			@ <UNDEFINED> instruction: 0xffcd4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3d0264 <uniffi_pbcli_checksum_method_api_base@@Base+0x2639e0>
│ │  	str	r1, [r0, r0]
│ │  	b.n	3d008e <uniffi_pbcli_checksum_method_api_base@@Base+0x26380a>
│ │  	asrs	r4, r5, #19
│ │  	b.n	3cf890 <uniffi_pbcli_checksum_method_api_base@@Base+0x26300c>
│ │ @@ -1127606,32 +1127606,32 @@
│ │  			@ <UNDEFINED> instruction: 0xebfb0006
│ │  	b.n	3d0576 <uniffi_pbcli_checksum_method_api_base@@Base+0x263cf2>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, sp, lr}
│ │  	b.n	3d097e <uniffi_pbcli_checksum_method_api_base@@Base+0x2640fa>
│ │  			@ <UNDEFINED> instruction: 0xfff9eaff
│ │  	adds	r2, #136	@ 0x88
│ │ -	vqshrn.u16	d24, q6, #4
│ │ +	vmul.f<illegal width 8>	q12, q6, d3[0]
│ │  			@ <UNDEFINED> instruction: 0xffccfbc4
│ │  	vsra.u64	d26, d30, #53
│ │  			@ <UNDEFINED> instruction: 0xffcafb64
│ │  	vrshr.u8	d22, d28, #5
│ │  			@ <UNDEFINED> instruction: 0xffcbfb04
│ │  			@ <UNDEFINED> instruction: 0xffcb87c0
│ │  	vmlsl.u8	<illegal reg q15.5>, d26, d20
│ │  	vsra.u8	d19, d8, #5
│ │  	vmull.u<illegal width 8>	<illegal reg q15.5>, d12, d0[1]
│ │  	vrsra.u64	d20, d12, #53
│ │  	vqshlu.s8	d20, d0, #4
│ │ -	vqshlu.s64	d24, d10, #12
│ │ -	vqshlu.s64	<illegal reg q15.5>, <illegal reg q5.5>, #12
│ │ +	vmlsl.u<illegal width 8>	q12, d28, d1[0]
│ │ +	vabdl.u8	<illegal reg q15.5>, d12, d2
│ │  	vqshl.u8	<illegal reg q11.5>, <illegal reg q7.5>, #4
│ │  	vrsra.u64	q15, q9, #53
│ │  	vqrshrun.s16	d31, q2, #5
│ │ -	vaddl.u8	<illegal reg q11.5>, d11, d28
│ │ +	vshr.u8	<illegal reg q11.5>, <illegal reg q1.5>, #5
│ │  			@ <UNDEFINED> instruction: 0xffccf7ec
│ │  	vrsubhn.i16	d24, <illegal reg q13.5>, <illegal reg q14.5>
│ │  	vabdl.u8	<illegal reg q15.5>, d27, d4
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3cfddc <uniffi_pbcli_checksum_method_api_base@@Base+0x263558>
│ │  	movs	r0, r0
│ │  	b.n	3d03c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x263b3c>
│ │ @@ -1127851,15 +1127851,15 @@
│ │  	ldmia.w	sp!, {r0, r2}
│ │  	b.n	3d07c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x263f42>
│ │  	ldr	r4, [r7, #20]
│ │  			@ <UNDEFINED> instruction: 0xebfb0004
│ │  	b.n	3d07ce <uniffi_pbcli_checksum_method_api_base@@Base+0x263f4a>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r4, r6, r7, r8, sl, ip, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffcb7c37
│ │ +			@ <UNDEFINED> instruction: 0xffcb7c5e
│ │  	vaddl.u8	q8, d12, d0
│ │  	b.n	3d0b3e <uniffi_pbcli_checksum_method_api_base@@Base+0x2642ba>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (3d0564 <uniffi_pbcli_checksum_method_api_base@@Base+0x263ce0>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3d09c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x264140>
│ │  	ands	r0, r0
│ │ @@ -1128079,15 +1128079,15 @@
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r3}
│ │  	b.n	3d09e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x26415e>
│ │  	ldmia	r4, {r4, r5, r7}
│ │  			@ <UNDEFINED> instruction: 0xebfa0004
│ │  	b.n	3d09ea <uniffi_pbcli_checksum_method_api_base@@Base+0x264166>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r4, r6, r7, fp, ip, lr}
│ │ +	ldmia.w	sp!, {r3, r4, r5, r6, r7, fp, ip, lr}
│ │  	vaddl.u8	q8, d12, d4
│ │  	b.n	3d01f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x263970>
│ │  	movs	r0, r0
│ │  	b.n	3d07d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x263f54>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	add	r3, pc, #560	@ (adr r3, 3d08f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x26406c>)
│ │  	movs	r7, r1
│ │ @@ -1128904,15 +1128904,15 @@
│ │  	ands	r0, r0
│ │  	b.n	3d1532 <uniffi_pbcli_checksum_method_api_base@@Base+0x264cae>
│ │  	movs	r4, r0
│ │  	b.n	3d1136 <uniffi_pbcli_checksum_method_api_base@@Base+0x2648b2>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r3, r4, sl, fp, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcbeba0
│ │ -	vmls.i<illegal width 8>	q14, <illegal reg q5.5>, d2[0]
│ │ +	vmls.i<illegal width 8>	q14, <illegal reg q5.5>, d1[6]
│ │  			@ <UNDEFINED> instruction: 0xffccebc8
│ │  			@ <UNDEFINED> instruction: 0xffcb4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3d132c <uniffi_pbcli_checksum_method_api_base@@Base+0x264aa8>
│ │  	movs	r0, r0
│ │  	b.n	3d14b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x264c32>
│ │  	movs	r5, r3
│ │ @@ -1129036,15 +1129036,15 @@
│ │  	ldmia.w	sp!, {r0}
│ │  	b.n	3d15c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x264d42>
│ │  			@ <UNDEFINED> instruction: 0xfff9baff
│ │  	movs	r5, r0
│ │  	b.n	3d126e <uniffi_pbcli_checksum_method_api_base@@Base+0x2649ea>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r7, r9, fp, sp, lr, pc}
│ │ -	vmla.i<illegal width 8>	<illegal reg q11.5>, <illegal reg q13.5>, d3[5]
│ │ +	vaddw.u8	<illegal reg q11.5>, <illegal reg q5.5>, d14
│ │  			@ <UNDEFINED> instruction: 0xffcc4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3d145c <uniffi_pbcli_checksum_method_api_base@@Base+0x264bd8>
│ │  	str	r1, [r0, #0]
│ │  	b.n	3d1286 <uniffi_pbcli_checksum_method_api_base@@Base+0x264a02>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3d128a <uniffi_pbcli_checksum_method_api_base@@Base+0x264a06>
│ │ @@ -1129518,23 +1129518,23 @@
│ │  	subs	r6, #106	@ 0x6a
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	3d1a06 <uniffi_pbcli_checksum_method_api_base@@Base+0x265182>
│ │  			@ <UNDEFINED> instruction: 0xff971aff
│ │  			@ <UNDEFINED> instruction: 0xffbeeaff
│ │  	ldr	r7, [pc, #112]	@ (3d13e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x264b5c>)
│ │  	vsri.64	<illegal reg q11.5>, q2, #53
│ │ -	vmls.i<illegal width 8>	<illegal reg q11.5>, q13, d0[5]
│ │ +	vabal.u8	<illegal reg q11.5>, d10, d11
│ │  	vqrdmulh.s<illegal width 8>	q12, q6, d2[7]
│ │  	vmla.i<illegal width 8>	<illegal reg q9.5>, q5, d0[7]
│ │  	vrsra.u8	d19, d4, #4
│ │ -	vrsra.u64	<illegal reg q11.5>, q1, #52
│ │ -	vmls.i<illegal width 8>	q15, q6, d3[1]
│ │ +	vrsra.u64	<illegal reg q11.5>, <illegal reg q12.5>, #52
│ │ +	vmls.i<illegal width 8>	q15, q6, d2[7]
│ │  	vsri.64	q11, <illegal reg q11.5>, #52
│ │  	vsra.u64	d29, d18, #53
│ │ -	vmull.p8	<illegal reg q10.5>, d11, d28
│ │ +			@ <UNDEFINED> instruction: 0xffcb5e53
│ │  			@ <UNDEFINED> instruction: 0xffcc4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3d18bc <uniffi_pbcli_checksum_method_api_base@@Base+0x265038>
│ │  	beq.n	3d13fc <uniffi_pbcli_checksum_method_api_base@@Base+0x264b78>
│ │  	b.n	3d1840 <uniffi_pbcli_checksum_method_api_base@@Base+0x264fbc>
│ │  	ands	r0, r0
│ │  	b.n	3d1aea <uniffi_pbcli_checksum_method_api_base@@Base+0x265266>
│ │ @@ -1130087,28 +1130087,28 @@
│ │  	b.n	3d1bba <uniffi_pbcli_checksum_method_api_base@@Base+0x265336>
│ │  	movs	r0, r0
│ │  	b.n	3d1f1e <uniffi_pbcli_checksum_method_api_base@@Base+0x26569a>
│ │  	ands	r1, r0
│ │  	asrs	r0, r0, #12
│ │  	vpmin.u<illegal width 64>	q15, <illegal reg q12.5>, <illegal reg q15.5>
│ │  	b.n	3d10c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x264844>
│ │ -	vmlal.u<illegal width 8>	<illegal reg q15.5>, d11, d0[2]
│ │ +	vmlal.u<illegal width 8>	<illegal reg q15.5>, d11, d3[7]
│ │  	vqrdmlah.s<illegal width 8>	q15, q14, d1[1]
│ │  	vqrdmulh.s<illegal width 8>	<illegal reg q8.5>, <illegal reg q13.5>, d3[2]
│ │  	vabdl.u8	<illegal reg q14.5>, d12, d14
│ │  			@ <UNDEFINED> instruction: 0xffcb4bbd
│ │  	vrsubhn.i16	d29, <illegal reg q13.5>, q4
│ │  	vmull.p8	q14, d11, d7
│ │  			@ <UNDEFINED> instruction: 0xffcb9ba2
│ │  	vmull.u<illegal width 8>	<illegal reg q8.5>, d11, d0[1]
│ │ -			@ <UNDEFINED> instruction: 0xffcc4925
│ │ +	vmul.f<illegal width 8>	q10, q6, d0[3]
│ │  	vsubl.u8	q15, d28, d12
│ │ -	vshr.u64	d31, d20, #53
│ │ +	vshr.u64	<illegal reg q15.5>, <illegal reg q5.5>, #53
│ │  	vaddl.u8	<illegal reg q12.5>, d28, d28
│ │ -			@ <UNDEFINED> instruction: 0xffcab998
│ │ +			@ <UNDEFINED> instruction: 0xffcab9bf
│ │  	vmul.i<illegal width 8>	<illegal reg q8.5>, q14, d3[1]
│ │  	vshll.u8	q14, d8, #4
│ │  	vqrdmlsh.s<illegal width 8>	<illegal reg q11.5>, <illegal reg q13.5>, d0[2]
│ │  	vmul.f<illegal width 8>	q15, q5, d0[7]
│ │  			@ <UNDEFINED> instruction: 0xffcb2ddd
│ │  			@ <UNDEFINED> instruction: 0xffcc6e5a
│ │  	vrshr.u64	q15, q14, #54
│ │ @@ -1130414,21 +1130414,21 @@
│ │  	b.n	3d1ea2 <uniffi_pbcli_checksum_method_api_base@@Base+0x26561e>
│ │  	stmia	r7!, {r7}
│ │  			@ <UNDEFINED> instruction: 0xebfa0004
│ │  	b.n	3d1eaa <uniffi_pbcli_checksum_method_api_base@@Base+0x265626>
│ │  	beq.n	3d1ba4 <uniffi_pbcli_checksum_method_api_base@@Base+0x265320>
│ │  	b.n	3d2004 <uniffi_pbcli_checksum_method_api_base@@Base+0x265780>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r5, r9, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffcc0df3
│ │ -	vsli.64	d18, d10, #13
│ │ -	vsra.u64	d20, d6, #51
│ │ -	vqdmulh.s<illegal width 8>	q8, q14, d3[2]
│ │ -	vmls.i<illegal width 8>	q9, <illegal reg q6.5>, d2[4]
│ │ -	vmul.f<illegal width 8>	q8, <illegal reg q14.5>, d2[6]
│ │ +	ldmia.w	sp!, {r0, r3, r6, r9, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffcc0e1a
│ │ +	vmls.f<illegal width 8>	q9, <illegal reg q14.5>, d1[0]
│ │ +	vsra.u64	d20, d29, #51
│ │ +			@ <UNDEFINED> instruction: 0xffcc0cf2
│ │ +	vraddhn.i16	d18, <illegal reg q14.5>, <illegal reg q4.5>
│ │ +	vshll.u8	q8, d1, #5
│ │  			@ <UNDEFINED> instruction: 0xffcd4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3d20b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x26582c>
│ │  	movs	r0, r0
│ │  	b.n	3d223a <uniffi_pbcli_checksum_method_api_base@@Base+0x2659b6>
│ │  	movs	r1, r6
│ │  	lsrs	r0, r0, #8
│ │ @@ -1130757,17 +1130757,17 @@
│ │  	b.n	3d25be <uniffi_pbcli_checksum_method_api_base@@Base+0x265d3a>
│ │  	movs	r4, r0
│ │  	b.n	3d21c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x26593e>
│ │  	bvs.n	3d1e8c <uniffi_pbcli_checksum_method_api_base@@Base+0x265608>
│ │  			@ <UNDEFINED> instruction: 0xebfa0006
│ │  	b.n	3d21ca <uniffi_pbcli_checksum_method_api_base@@Base+0x265946>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r6, r7, r8, r9, fp, lr}
│ │ +	ldmia.w	sp!, {r0, r3, r5, r6, r7, r8, r9, fp, lr}
│ │  	vsubl.u8	q9, d12, d8
│ │ -			@ <UNDEFINED> instruction: 0xffcb4bf6
│ │ +			@ <UNDEFINED> instruction: 0xffcb4c1d
│ │  	vrshr.u8	d18, d28, #4
│ │  			@ <UNDEFINED> instruction: 0xffcb4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3d23c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x265b3c>
│ │  	ands	r0, r0
│ │  	b.n	3d21ea <uniffi_pbcli_checksum_method_api_base@@Base+0x265966>
│ │  	blx	2366a8 <uniffi_pbcli_checksum_method_api_base@@Base+0xc9e24>
│ │ @@ -1131144,16 +1131144,16 @@
│ │  	movs	r0, #2
│ │  	b.n	3d2308 <uniffi_pbcli_checksum_method_api_base@@Base+0x265a84>
│ │  	subs	r3, #246	@ 0xf6
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	3d2892 <uniffi_pbcli_checksum_method_api_base@@Base+0x26600e>
│ │  			@ <UNDEFINED> instruction: 0xffe71aff
│ │  			@ <UNDEFINED> instruction: 0xfff1eaff
│ │ -	subs	r2, #46	@ 0x2e
│ │ -	vrsra.u8	d16, d22, #4
│ │ +	subs	r2, #85	@ 0x55
│ │ +	vrsra.u8	q8, <illegal reg q6.5>, #4
│ │  			@ <UNDEFINED> instruction: 0xffcd4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3d2724 <uniffi_pbcli_checksum_method_api_base@@Base+0x265ea0>
│ │  	str	r2, [r0, r0]
│ │  	b.n	3d254e <uniffi_pbcli_checksum_method_api_base@@Base+0x265cca>
│ │  	strh	r1, [r0, #0]
│ │  	b.n	3d2552 <uniffi_pbcli_checksum_method_api_base@@Base+0x265cce>
│ │ @@ -1131392,20 +1131392,20 @@
│ │  			@ <UNDEFINED> instruction: 0xebfd0000
│ │  	b.n	3d2ab6 <uniffi_pbcli_checksum_method_api_base@@Base+0x266232>
│ │  	str	r1, [r0, r0]
│ │  	asrs	r0, r4, #14
│ │  	movs	r5, r0
│ │  	b.n	3d275e <uniffi_pbcli_checksum_method_api_base@@Base+0x265eda>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r2, r5, r6, r7, r8, r9, sp, lr}
│ │ -	vshr.u64	<illegal reg q9.5>, q8, #52
│ │ -	vaddw.u8	<illegal reg q11.5>, q14, d7
│ │ +	ldmia.w	sp!, {r0, r1, r3, sl, sp, lr}
│ │ +	vsra.u8	d19, d7, #4
│ │ +	vaddw.u8	<illegal reg q11.5>, q14, d30
│ │  			@ <UNDEFINED> instruction: 0xffccee1d
│ │  	vsri.8	d23, d27, #6
│ │ -	vaddw.u8	<illegal reg q14.5>, q5, d9
│ │ +	vsra.u8	d29, d16, #6
│ │  			@ <UNDEFINED> instruction: 0xffccedbd
│ │  	vmls.i<illegal width 8>	q11, q13, d1[0]
│ │  	vqrdmulh.s<illegal width 8>	q15, <illegal reg q5.5>, d1[3]
│ │  	vaddl.u8	q8, d10, d4
│ │  	b.n	3d1f88 <uniffi_pbcli_checksum_method_api_base@@Base+0x265704>
│ │  	movs	r0, r0
│ │  	b.n	3d256c <uniffi_pbcli_checksum_method_api_base@@Base+0x265ce8>
│ │ @@ -1131723,15 +1131723,15 @@
│ │  	b.n	3d2e76 <uniffi_pbcli_checksum_method_api_base@@Base+0x2665f2>
│ │  	movs	r4, r0
│ │  	b.n	3d2a7a <uniffi_pbcli_checksum_method_api_base@@Base+0x2661f6>
│ │  	beq.n	3d274c <uniffi_pbcli_checksum_method_api_base@@Base+0x265ec8>
│ │  	b.n	3d2bd4 <uniffi_pbcli_checksum_method_api_base@@Base+0x266350>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r3, r6, r8, r9, ip, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffcbcd8e
│ │ +			@ <UNDEFINED> instruction: 0xffcbcdb5
│ │  	vaddl.u8	q8, d12, d4
│ │  	b.n	3d228c <uniffi_pbcli_checksum_method_api_base@@Base+0x265a08>
│ │  	movs	r0, r0
│ │  	b.n	3d2870 <uniffi_pbcli_checksum_method_api_base@@Base+0x265fec>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	str	r4, [sp, #688]	@ 0x2b0
│ │  	movs	r7, r1
│ │ @@ -1131903,15 +1131903,15 @@
│ │  	b.n	3d3022 <uniffi_pbcli_checksum_method_api_base@@Base+0x26679e>
│ │  	movs	r4, r0
│ │  	b.n	3d2c26 <uniffi_pbcli_checksum_method_api_base@@Base+0x2663a2>
│ │  	beq.n	3d28f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x266074>
│ │  	b.n	3d2d80 <uniffi_pbcli_checksum_method_api_base@@Base+0x2664fc>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r2, r3, r4, r7, r8, ip, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffcbcbe2
│ │ +	vmull.u8	q14, d11, d9
│ │  	vaddl.u8	q8, d12, d4
│ │  	b.n	3d2438 <uniffi_pbcli_checksum_method_api_base@@Base+0x265bb4>
│ │  	movs	r0, r0
│ │  	b.n	3d2a1c <uniffi_pbcli_checksum_method_api_base@@Base+0x266198>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	str	r3, [sp, #0]
│ │  	movs	r7, r1
│ │ @@ -1132162,17 +1132162,17 @@
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, sp, lr}
│ │  	b.n	3d3276 <uniffi_pbcli_checksum_method_api_base@@Base+0x2669f2>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │  	lsrs	r7, r0, #32
│ │  	vsra.u8	q14, q1, #4
│ │  	vqrshrun.s16	d29, <illegal reg q8.5>, #5
│ │ -	vsri.8	<illegal reg q9.5>, <illegal reg q10.5>, #5
│ │ -	vmla.i<illegal width 8>	<illegal reg q9.5>, q14, d2[3]
│ │ -	vshll.u8	<illegal reg q15.5>, d6, #4
│ │ +	vsri.64	d19, d12, #53
│ │ +	vshr.u64	<illegal reg q9.5>, <illegal reg q10.5>, #52
│ │ +	vshll.u8	<illegal reg q15.5>, d29, #4
│ │  			@ <UNDEFINED> instruction: 0xffcc48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3d3074 <uniffi_pbcli_checksum_method_api_base@@Base+0x2667f0>
│ │  	beq.n	3d2b6c <uniffi_pbcli_checksum_method_api_base@@Base+0x2662e8>
│ │  	b.n	3d2ff8 <uniffi_pbcli_checksum_method_api_base@@Base+0x266774>
│ │  	str	r1, [r0, r0]
│ │  	b.n	3d32a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x266a1e>
│ │ @@ -1132300,17 +1132300,17 @@
│ │  	and.w	r0, r0, r0, lsl #20
│ │  	b.n	3d33a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x266b22>
│ │  	movs	r5, r0
│ │  	b.n	3d2faa <uniffi_pbcli_checksum_method_api_base@@Base+0x266726>
│ │  	beq.n	3d2c8c <uniffi_pbcli_checksum_method_api_base@@Base+0x266408>
│ │  	b.n	3d3104 <uniffi_pbcli_checksum_method_api_base@@Base+0x266880>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r7, r8, r9, ip, sp}
│ │ +	ldmia.w	sp!, {r3, r5, r7, r8, r9, ip, sp}
│ │  	vmls.f<illegal width 8>	q15, q6, d1[7]
│ │ -	vmul.i<illegal width 8>	q14, q5, d1[7]
│ │ +			@ <UNDEFINED> instruction: 0xffcac894
│ │  	vsli.8	d30, d13, #4
│ │  	vsri.64	q15, <illegal reg q10.5>, #54
│ │  			@ <UNDEFINED> instruction: 0xffca4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3d31a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x266924>
│ │  	beq.n	3d2d10 <uniffi_pbcli_checksum_method_api_base@@Base+0x26648c>
│ │  	b.n	3d312c <uniffi_pbcli_checksum_method_api_base@@Base+0x2668a8>
│ │ @@ -1132685,17 +1132685,17 @@
│ │  	b.n	3d36de <uniffi_pbcli_checksum_method_api_base@@Base+0x266e5a>
│ │  	movs	r0, r1
│ │  	b.n	3d2b6a <uniffi_pbcli_checksum_method_api_base@@Base+0x2662e6>
│ │  	movs	r4, r0
│ │  	b.n	3d3326 <uniffi_pbcli_checksum_method_api_base@@Base+0x266aa2>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r3, r6, r9, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffca3b2f
│ │ +			@ <UNDEFINED> instruction: 0xffca3b56
│ │  	vrshr.u8	d30, d1, #4
│ │ -			@ <UNDEFINED> instruction: 0xffca3af7
│ │ +			@ <UNDEFINED> instruction: 0xffca3b1e
│ │  	vaddl.u8	q8, d12, d0
│ │  	b.n	3d369e <uniffi_pbcli_checksum_method_api_base@@Base+0x266e1a>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	stmia	r0!, {r2}
│ │  	b.n	3d3506 <uniffi_pbcli_checksum_method_api_base@@Base+0x266c82>
│ │  	cmp	r7, #159	@ 0x9f
│ │  	b.n	3d3342 <uniffi_pbcli_checksum_method_api_base@@Base+0x266abe>
│ │ @@ -1132718,15 +1132718,15 @@
│ │  	asrs	r0, r1, #32
│ │  	b.n	3d2b74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2662f0>
│ │  	movs	r0, #61	@ 0x3d
│ │  	b.n	3d377a <uniffi_pbcli_checksum_method_api_base@@Base+0x266ef6>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3d315c <uniffi_pbcli_checksum_method_api_base@@Base+0x2668d8>
│ │  	movs	r7, #162	@ 0xa2
│ │ -			@ <UNDEFINED> instruction: 0xeafd6628
│ │ +			@ <UNDEFINED> instruction: 0xeafd664f
│ │  			@ <UNDEFINED> instruction: 0xffcc4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3d3568 <uniffi_pbcli_checksum_method_api_base@@Base+0x266ce4>
│ │  	ands	r0, r0
│ │  	b.n	3d3392 <uniffi_pbcli_checksum_method_api_base@@Base+0x266b0e>
│ │  	blx	5cd850 <uniffi_pbcli_checksum_method_api_base@@Base+0x460fcc>
│ │  	movs	r0, r0
│ │ @@ -1132789,15 +1132789,15 @@
│ │  	add.w	r0, r0, r6, lsl #20
│ │  	b.n	3d341e <uniffi_pbcli_checksum_method_api_base@@Base+0x266b9a>
│ │  	movs	r0, r0
│ │  	b.n	3d2bee <uniffi_pbcli_checksum_method_api_base@@Base+0x26636a>
│ │  	movs	r5, r0
│ │  	b.n	3d3426 <uniffi_pbcli_checksum_method_api_base@@Base+0x266ba2>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r2, r4, r5, r7, r8, sl, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r4, r6, r7, r8, sl, sp, lr}
│ │  	vaddl.u8	q8, d12, d0
│ │  	b.n	3d3792 <uniffi_pbcli_checksum_method_api_base@@Base+0x266f0e>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	stmia	r0!, {r2}
│ │  	b.n	3d35fa <uniffi_pbcli_checksum_method_api_base@@Base+0x266d76>
│ │  	cmp	r7, #159	@ 0x9f
│ │  	b.n	3d3436 <uniffi_pbcli_checksum_method_api_base@@Base+0x266bb2>
│ │ @@ -1132820,15 +1132820,15 @@
│ │  	asrs	r0, r1, #32
│ │  	b.n	3d2c68 <uniffi_pbcli_checksum_method_api_base@@Base+0x2663e4>
│ │  	movs	r0, #61	@ 0x3d
│ │  	b.n	3d386e <uniffi_pbcli_checksum_method_api_base@@Base+0x266fea>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3d3250 <uniffi_pbcli_checksum_method_api_base@@Base+0x2669cc>
│ │  	movs	r7, #101	@ 0x65
│ │ -			@ <UNDEFINED> instruction: 0xeafd6534
│ │ +			@ <UNDEFINED> instruction: 0xeafd655b
│ │  	vaddl.u8	q8, d12, d1
│ │  	b.n	3d387e <uniffi_pbcli_checksum_method_api_base@@Base+0x266ffa>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r0, [pc, #192]	@ (3d3204 <uniffi_pbcli_checksum_method_api_base@@Base+0x266980>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3d3664 <uniffi_pbcli_checksum_method_api_base@@Base+0x266de0>
│ │  	movs	r0, r0
│ │ @@ -1133063,15 +1133063,15 @@
│ │  	ldmia.w	sp!, {r1, r3, r4, r6, r9}
│ │  	and.w	r0, r0, r0
│ │  	b.n	3d3aaa <uniffi_pbcli_checksum_method_api_base@@Base+0x267226>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0}
│ │  	b.n	3d3ab2 <uniffi_pbcli_checksum_method_api_base@@Base+0x26722e>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r4, r6, r7, r8, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r5, r6, r7, r8, ip, sp, lr, pc}
│ │  	vaddl.u8	q8, d12, d4
│ │  	b.n	3d2ebc <uniffi_pbcli_checksum_method_api_base@@Base+0x266638>
│ │  	movs	r0, r0
│ │  	b.n	3d34a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x266c1c>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldrh	r4, [r3, #18]
│ │  	movs	r7, r1
│ │ @@ -1133476,15 +1133476,15 @@
│ │  	b.n	3d3e4e <uniffi_pbcli_checksum_method_api_base@@Base+0x2675ca>
│ │  	ands	r0, r0
│ │  	b.n	3d3e52 <uniffi_pbcli_checksum_method_api_base@@Base+0x2675ce>
│ │  	lsrs	r0, r3, #25
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3d3a5a <uniffi_pbcli_checksum_method_api_base@@Base+0x2671d6>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r7, r9, sl, fp, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r6, r7, r9, sl, fp, sp, lr, pc}
│ │  	vqrshrn.u16	d29, <illegal reg q14.5>, #4
│ │  	vrshr.u64	d31, d2, #53
│ │  	vmul.f<illegal width 8>	<illegal reg q14.5>, q13, d1[0]
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3d3270 <uniffi_pbcli_checksum_method_api_base@@Base+0x2669ec>
│ │  	movs	r0, r0
│ │  	b.n	3d3854 <uniffi_pbcli_checksum_method_api_base@@Base+0x266fd0>
│ │ @@ -1134096,17 +1134096,17 @@
│ │  	and.w	r0, r0, r1, lsl #16
│ │  	b.n	3d43fa <uniffi_pbcli_checksum_method_api_base@@Base+0x267b76>
│ │  	movs	r4, r0
│ │  	b.n	3d3ffe <uniffi_pbcli_checksum_method_api_base@@Base+0x26777a>
│ │  	beq.n	3d3ce0 <uniffi_pbcli_checksum_method_api_base@@Base+0x26745c>
│ │  	b.n	3d4158 <uniffi_pbcli_checksum_method_api_base@@Base+0x2678d4>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r3, r4, r6, r7, fp, sp, lr, pc}
│ │ -	vmull.u8	<illegal reg q10.5>, d12, d18
│ │ -	vsli.64	d24, d29, #12
│ │ +	ldmia.w	sp!, {r0, r8, fp, sp, lr, pc}
│ │ +	vqdmulh.s<illegal width 8>	<illegal reg q10.5>, q6, d1[2]
│ │ +	vmls.f<illegal width 8>	q12, q14, d0[5]
│ │  			@ <UNDEFINED> instruction: 0xffcc48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3d41f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x267970>
│ │  	str	r1, [r0, r0]
│ │  	b.n	3d401e <uniffi_pbcli_checksum_method_api_base@@Base+0x26779a>
│ │  	asrs	r0, r1, #6
│ │  	b.n	3d3820 <uniffi_pbcli_checksum_method_api_base@@Base+0x266f9c>
│ │ @@ -1134286,24 +1134286,24 @@
│ │  	b.n	3d459e <uniffi_pbcli_checksum_method_api_base@@Base+0x267d1a>
│ │  	ands	r0, r0
│ │  	b.n	3d45a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x267d1e>
│ │  	lsrs	r4, r0, #18
│ │  			@ <UNDEFINED> instruction: 0xebfc0004
│ │  	b.n	3d41aa <uniffi_pbcli_checksum_method_api_base@@Base+0x267926>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r4, r5, fp, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r3, r4, r6, fp, sp, lr, pc}
│ │  	vmlal.u<illegal width 8>	<illegal reg q14.5>, d12, d1[7]
│ │ -	vqrdmulh.s<illegal width 8>	q11, <illegal reg q13.5>, d1[5]
│ │ +	vmull.p8	q11, d11, d12
│ │  	vrsra.u8	<illegal reg q14.5>, <illegal reg q2.5>, #4
│ │ -	vqshlu.s64	<illegal reg q13.5>, <illegal reg q10.5>, #11
│ │ +	vqshl.u8	d27, d12, #3
│ │  	vmlal.u<illegal width 8>	<illegal reg q14.5>, d12, d1[2]
│ │ -	vqrdmulh.s<illegal width 8>	q11, <illegal reg q13.5>, d1[0]
│ │ +	vqrdmulh.s<illegal width 8>	q11, <illegal reg q13.5>, d0[6]
│ │  	vrshr.u64	<illegal reg q14.5>, <illegal reg q6.5>, #52
│ │  	vsubl.u8	<illegal reg q14.5>, d11, d29
│ │ -			@ <UNDEFINED> instruction: 0xffcb6da5
│ │ +	vqrdmulh.s<illegal width 8>	q11, <illegal reg q13.5>, d0[3]
│ │  			@ <UNDEFINED> instruction: 0xffcc4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3d43b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x267b34>
│ │  	str	r3, [r6, #12]
│ │  	add.w	r0, r0, r0, lsl #16
│ │  	b.n	3d41e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x267962>
│ │  	vmov.8	d21[7], lr
│ │ @@ -1134463,15 +1134463,15 @@
│ │  	b.n	3d4342 <uniffi_pbcli_checksum_method_api_base@@Base+0x267abe>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3d474a <uniffi_pbcli_checksum_method_api_base@@Base+0x267ec6>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r5, r6, r7, r9, ip, sp, lr, pc}
│ │  	vmlal.u8	<illegal reg q10.5>, d11, d14
│ │ -	vabal.u8	<illegal reg q15.5>, d26, d16
│ │ +	vmls.f<illegal width 8>	<illegal reg q15.5>, q13, d3[1]
│ │  	vqrshrn.u16	d20, <illegal reg q5.5>, #4
│ │  	vrsra.u8	q14, q11, #6
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3d3b64 <uniffi_pbcli_checksum_method_api_base@@Base+0x2672e0>
│ │  	movs	r0, r0
│ │  	b.n	3d4148 <uniffi_pbcli_checksum_method_api_base@@Base+0x2678c4>
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -1135738,15 +1135738,15 @@
│ │  	b.n	3d469e <uniffi_pbcli_checksum_method_api_base@@Base+0x267e1a>
│ │  	asrs	r4, r6, #32
│ │  	b.n	3d46a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x267e1e>
│ │  	vrhadd.u<illegal width 64>	d14, d2, d31
│ │  	beq.n	3d4ba0 <uniffi_pbcli_checksum_method_api_base@@Base+0x26831c>
│ │  	b.n	3d5018 <uniffi_pbcli_checksum_method_api_base@@Base+0x268794>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r5, r8, r9, sl, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r4, r6, r8, r9, sl, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcc4763
│ │  	vqshrun.s16	d20, q8, #5
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3d50b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x26882c>
│ │  			@ <UNDEFINED> instruction: 0xeb29ebfe
│ │  	ands	r0, r0
│ │  	b.n	3d52de <uniffi_pbcli_checksum_method_api_base@@Base+0x268a5a>
│ │ @@ -1135773,15 +1135773,15 @@
│ │  	b.n	3d50ca <uniffi_pbcli_checksum_method_api_base@@Base+0x268846>
│ │  	adds	r2, #103	@ 0x67
│ │  			@ <UNDEFINED> instruction: 0xebff4005
│ │  	b.n	3d4f12 <uniffi_pbcli_checksum_method_api_base@@Base+0x26868e>
│ │  	movs	r4, r0
│ │  	b.n	3d4f16 <uniffi_pbcli_checksum_method_api_base@@Base+0x268692>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r5, r6, r7, r9, fp, lr}
│ │ +	ldmia.w	sp!, {r2, r3, r8, r9, fp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffcc4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3d5100 <uniffi_pbcli_checksum_method_api_base@@Base+0x26887c>
│ │  	ands	r0, r0
│ │  	b.n	3d4f2a <uniffi_pbcli_checksum_method_api_base@@Base+0x2686a6>
│ │  			@ <UNDEFINED> instruction: 0xeb14ebfe
│ │  	str	r0, [r0, r0]
│ │ @@ -1135811,15 +1135811,15 @@
│ │  	b.n	3d4f62 <uniffi_pbcli_checksum_method_api_base@@Base+0x2686de>
│ │  	lsls	r6, r5, #1
│ │  			@ <UNDEFINED> instruction: 0xfa035006
│ │  	b.n	3d4f6a <uniffi_pbcli_checksum_method_api_base@@Base+0x2686e6>
│ │  	movs	r5, r0
│ │  	b.n	3d4f6e <uniffi_pbcli_checksum_method_api_base@@Base+0x2686ea>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r4, r7, r9, fp, lr}
│ │ +	ldmia.w	sp!, {r3, r4, r5, r7, r9, fp, lr}
│ │  	vaddl.u8	q8, d12, d0
│ │  	b.n	3d52da <uniffi_pbcli_checksum_method_api_base@@Base+0x268a56>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (3d4c80 <uniffi_pbcli_checksum_method_api_base@@Base+0x2683fc>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3d5160 <uniffi_pbcli_checksum_method_api_base@@Base+0x2688dc>
│ │  	ands	r0, r0
│ │ @@ -1135835,15 +1135835,15 @@
│ │  	b.n	3d4f9e <uniffi_pbcli_checksum_method_api_base@@Base+0x26871a>
│ │  	movs	r0, #79	@ 0x4f
│ │  	b.n	3d53a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x268b1e>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3d4d84 <uniffi_pbcli_checksum_method_api_base@@Base+0x268500>
│ │  	ldr	r4, [pc, #64]	@ (3d4ca8 <uniffi_pbcli_checksum_method_api_base@@Base+0x268424>)
│ │  	ldmia.w	sp!, {r0, r1, r2, r4, r7, sp}
│ │ -			@ <UNDEFINED> instruction: 0xeafd4a35
│ │ +			@ <UNDEFINED> instruction: 0xeafd4a5c
│ │  			@ <UNDEFINED> instruction: 0xffcc48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3d5194 <uniffi_pbcli_checksum_method_api_base@@Base+0x268910>
│ │  	strb	r3, [r0, #0]
│ │  	b.n	3d4fbe <uniffi_pbcli_checksum_method_api_base@@Base+0x26873a>
│ │  	str	r2, [r0, r0]
│ │  	b.n	3d4fc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x26873e>
│ │ @@ -1135947,17 +1135947,17 @@
│ │  	b.n	3d5266 <uniffi_pbcli_checksum_method_api_base@@Base+0x2689e2>
│ │  	cmp	r7, #74	@ 0x4a
│ │  	b.n	3d526a <uniffi_pbcli_checksum_method_api_base@@Base+0x2689e6>
│ │  	movs	r4, r0
│ │  	b.n	3d50a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x268822>
│ │  	ldr	r0, [pc, #960]	@ (3d5128 <uniffi_pbcli_checksum_method_api_base@@Base+0x2688a4>)
│ │  	ldmia.w	sp!, {r1, r2, r7, r9, ip, sp}
│ │ -			@ <UNDEFINED> instruction: 0xeaff49c9
│ │ +			@ <UNDEFINED> instruction: 0xeaff49f0
│ │  	vmull.u<illegal width 8>	q10, d28, d0[3]
│ │ -			@ <UNDEFINED> instruction: 0xffca4995
│ │ +			@ <UNDEFINED> instruction: 0xffca49bc
│ │  			@ <UNDEFINED> instruction: 0xffcc3b73
│ │  	vaddl.u8	q8, d11, d0
│ │  	b.n	3d5426 <uniffi_pbcli_checksum_method_api_base@@Base+0x268ba2>
│ │  	movs	r1, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	adds	r2, #251	@ 0xfb
│ │ @@ -1136265,25 +1136265,25 @@
│ │  	ldmia.w	sp!, {r3, ip}
│ │  	b.n	3d4b5e <uniffi_pbcli_checksum_method_api_base@@Base+0x2682da>
│ │  	lsls	r0, r5, #3
│ │  	b.n	3d554c <uniffi_pbcli_checksum_method_api_base@@Base+0x268cc8>
│ │  	adds	r1, #97	@ 0x61
│ │  			@ <UNDEFINED> instruction: 0xebfffff8
│ │  			@ <UNDEFINED> instruction: 0xeaff8621
│ │ -	vqshl.u64	q10, <illegal reg q0.5>, #11
│ │ -	vrshr.u8	d26, d27, #4
│ │ +	vqshl.u64	q10, q12, #11
│ │ +	vmlal.u<illegal width 8>	q13, d12, d2[4]
│ │  	vqshlu.s8	d28, d18, #4
│ │ -			@ <UNDEFINED> instruction: 0xffca4769
│ │ +	vqshl.u64	d20, d0, #10
│ │  	vmul.i<illegal width 8>	q10, q6, d0[7]
│ │  	vmlsl.u8	<illegal reg q11.5>, d10, d28
│ │ -	vmlsl.u<illegal width 8>	q10, d26, d1[5]
│ │ -	vmla.f<illegal width 8>	q13, q6, d3[3]
│ │ +	vabdl.u8	q10, d10, d12
│ │ +	vsra.u8	q13, q11, #4
│ │  			@ <UNDEFINED> instruction: 0xffcc4bf7
│ │ -	vrsubhn.i16	d20, q13, <illegal reg q4.5>
│ │ -	vshr.u64	q13, <illegal reg q9.5>, #52
│ │ +	vqshlu.s64	d20, d16, #10
│ │ +	vsra.u8	d26, d10, #4
│ │  	vqshrun.s16	d20, q8, #4
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3d559c <uniffi_pbcli_checksum_method_api_base@@Base+0x268d18>
│ │  	strd	lr, fp, [lr, #1016]!	@ 0x3f8
│ │  	ands	r0, r0
│ │  	b.n	3d57ca <uniffi_pbcli_checksum_method_api_base@@Base+0x268f46>
│ │  	movs	r0, r0
│ │ @@ -1136309,15 +1136309,15 @@
│ │  	b.n	3d55b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x268d32>
│ │  	bx	fp
│ │  			@ <UNDEFINED> instruction: 0xebff4005
│ │  	b.n	3d53fe <uniffi_pbcli_checksum_method_api_base@@Base+0x268b7a>
│ │  	movs	r4, r0
│ │  	b.n	3d5402 <uniffi_pbcli_checksum_method_api_base@@Base+0x268b7e>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r6, r7, r8, sl, lr}
│ │ +	ldmia.w	sp!, {r5, r9, sl, lr}
│ │  			@ <UNDEFINED> instruction: 0xffcc4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3d55ec <uniffi_pbcli_checksum_method_api_base@@Base+0x268d68>
│ │  	ands	r0, r0
│ │  	b.n	3d5416 <uniffi_pbcli_checksum_method_api_base@@Base+0x268b92>
│ │  	ldrd	lr, fp, [r9, #1016]	@ 0x3f8
│ │  	str	r0, [r0, r0]
│ │ @@ -1136347,15 +1136347,15 @@
│ │  	b.n	3d544e <uniffi_pbcli_checksum_method_api_base@@Base+0x268bca>
│ │  	vpmax.u<illegal width 64>	d15, d5, d2
│ │  	str	r6, [r0, r0]
│ │  	b.n	3d5456 <uniffi_pbcli_checksum_method_api_base@@Base+0x268bd2>
│ │  	movs	r5, r0
│ │  	b.n	3d545a <uniffi_pbcli_checksum_method_api_base@@Base+0x268bd6>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r2, r5, r7, r8, sl, lr}
│ │ +	ldmia.w	sp!, {r2, r3, r6, r7, r8, sl, lr}
│ │  	vaddl.u8	q8, d12, d0
│ │  	b.n	3d57c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x268f42>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (3d516c <uniffi_pbcli_checksum_method_api_base@@Base+0x2688e8>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3d564c <uniffi_pbcli_checksum_method_api_base@@Base+0x268dc8>
│ │  	ands	r0, r0
│ │ @@ -1136371,15 +1136371,15 @@
│ │  	b.n	3d548a <uniffi_pbcli_checksum_method_api_base@@Base+0x268c06>
│ │  	movs	r0, #79	@ 0x4f
│ │  	b.n	3d588e <uniffi_pbcli_checksum_method_api_base@@Base+0x26900a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3d5270 <uniffi_pbcli_checksum_method_api_base@@Base+0x2689ec>
│ │  	ldr	r4, [pc, #64]	@ (3d5194 <uniffi_pbcli_checksum_method_api_base@@Base+0x268910>)
│ │  	ldmia.w	sp!, {r2, r3, r4, r6, r8, r9, sl, fp, ip}
│ │ -			@ <UNDEFINED> instruction: 0xeafd4549
│ │ +			@ <UNDEFINED> instruction: 0xeafd4570
│ │  			@ <UNDEFINED> instruction: 0xffcc48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3d5680 <uniffi_pbcli_checksum_method_api_base@@Base+0x268dfc>
│ │  	strb	r3, [r0, #0]
│ │  	b.n	3d54aa <uniffi_pbcli_checksum_method_api_base@@Base+0x268c26>
│ │  	str	r2, [r0, r0]
│ │  	b.n	3d54ae <uniffi_pbcli_checksum_method_api_base@@Base+0x268c2a>
│ │ @@ -1136483,17 +1136483,17 @@
│ │  	b.n	3d5752 <uniffi_pbcli_checksum_method_api_base@@Base+0x268ece>
│ │  	movs	r0, #152	@ 0x98
│ │  	b.n	3d5756 <uniffi_pbcli_checksum_method_api_base@@Base+0x268ed2>
│ │  	movs	r4, r0
│ │  	b.n	3d5592 <uniffi_pbcli_checksum_method_api_base@@Base+0x268d0e>
│ │  	ldr	r0, [pc, #960]	@ (3d5614 <uniffi_pbcli_checksum_method_api_base@@Base+0x268d90>)
│ │  	ldmia.w	sp!, {r3, r4, r6, r8, r9, sl, lr}
│ │ -			@ <UNDEFINED> instruction: 0xeaff44dd
│ │ +			@ <UNDEFINED> instruction: 0xeaff4504
│ │  	vmls.f<illegal width 8>	q10, q14, d0[4]
│ │ -	vraddhn.i16	d20, q13, <illegal reg q12.5>
│ │ +	vsri.64	q10, q0, #54
│ │  	vrsubhn.i16	d19, q14, <illegal reg q3.5>
│ │  	vaddl.u8	q8, d11, d0
│ │  	b.n	3d5912 <uniffi_pbcli_checksum_method_api_base@@Base+0x26908e>
│ │  	movs	r1, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  			@ <UNDEFINED> instruction: 0x47af
│ │ @@ -1136801,25 +1136801,25 @@
│ │  	ldmia.w	sp!, {r3, ip}
│ │  	b.n	3d504a <uniffi_pbcli_checksum_method_api_base@@Base+0x2687c6>
│ │  	lsls	r0, r7, #1
│ │  	b.n	3d5a38 <uniffi_pbcli_checksum_method_api_base@@Base+0x2691b4>
│ │  	mov	r6, sl
│ │  			@ <UNDEFINED> instruction: 0xebfffff8
│ │  			@ <UNDEFINED> instruction: 0xeaff8135
│ │ -	vmlal.u<illegal width 8>	q10, d27, d1[5]
│ │ -	vqrdmulh.s<illegal width 8>	<illegal reg q12.5>, q6, d3[3]
│ │ +	vsubw.u8	q10, <illegal reg q5.5>, d12
│ │ +			@ <UNDEFINED> instruction: 0xffcc9d76
│ │  	vmla.f<illegal width 8>	q14, q6, d2[1]
│ │ -	vrshr.u8	q10, <illegal reg q14.5>, #6
│ │ +	vsubl.u8	q10, d26, d20
│ │  	vsubw.u8	q10, q14, d0
│ │  	vmls.f<illegal width 8>	<illegal reg q11.5>, q5, d0[0]
│ │ -	vsra.u64	q10, <illegal reg q12.5>, #54
│ │ -	vqdmulh.s<illegal width 8>	<illegal reg q12.5>, q6, d3[4]
│ │ +	vsubl.u8	q10, d10, d16
│ │ +	vmull.u8	<illegal reg q12.5>, d28, d10
│ │  	vabdl.u8	q10, d12, d11
│ │ -	vsra.u64	d20, d13, #54
│ │ -	vmull.u8	<illegal reg q12.5>, d12, d7
│ │ +	vmla.f<illegal width 8>	q10, q13, d0[1]
│ │ +	vmull.u8	<illegal reg q12.5>, d12, d30
│ │  			@ <UNDEFINED> instruction: 0xffcc4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3d5a88 <uniffi_pbcli_checksum_method_api_base@@Base+0x269204>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3d58b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x26902e>
│ │  	ldmia.w	r2!, {r1, r2, r3, r4, r5, r6, r7, r8, r9, fp, sp, lr, pc}
│ │  	ands	r0, r0
│ │ @@ -1137349,17 +1137349,17 @@
│ │  	b.n	3d6172 <uniffi_pbcli_checksum_method_api_base@@Base+0x2698ee>
│ │  	lsls	r0, r2, #22
│ │  			@ <UNDEFINED> instruction: 0xebfc0008
│ │  	b.n	3d5d7a <uniffi_pbcli_checksum_method_api_base@@Base+0x2694f6>
│ │  	beq.n	3d5a6c <uniffi_pbcli_checksum_method_api_base@@Base+0x2691e8>
│ │  	b.n	3d5ed4 <uniffi_pbcli_checksum_method_api_base@@Base+0x269650>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r1, r2, r4, r6, r8, r9, sl, fp, ip, sp}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r5, r6, r8, r9, sl, fp, ip, sp}
│ │  	vqshlu.s8	q10, <illegal reg q13.5>, #4
│ │ -			@ <UNDEFINED> instruction: 0xffcbad9a
│ │ +	vqrdmulh.s<illegal width 8>	q13, <illegal reg q13.5>, d1[0]
│ │  			@ <UNDEFINED> instruction: 0xffccbbaa
│ │  	vqshrun.s16	d20, q8, #6
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3d5f74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2696f0>
│ │  	asrs	r4, r3, #1
│ │  	b.n	3d559c <uniffi_pbcli_checksum_method_api_base@@Base+0x268d18>
│ │  	lsls	r0, r1, #2
│ │ @@ -1138400,16 +1138400,16 @@
│ │  	b.n	3d6a8a <uniffi_pbcli_checksum_method_api_base@@Base+0x26a206>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3d646c <uniffi_pbcli_checksum_method_api_base@@Base+0x269be8>
│ │  	subs	r6, r3, r3
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3d6696 <uniffi_pbcli_checksum_method_api_base@@Base+0x269e12>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, sl, fp, ip}
│ │ -	vmull.u8	<illegal reg q8.5>, d28, d27
│ │ +	ldmia.w	sp!, {r1, r2, r5, r8, sl, fp, ip}
│ │ +			@ <UNDEFINED> instruction: 0xffcc1cd2
│ │  			@ <UNDEFINED> instruction: 0xffcc4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3d6884 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a000>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3d66ae <uniffi_pbcli_checksum_method_api_base@@Base+0x269e2a>
│ │  	b.n	3d5dd6 <uniffi_pbcli_checksum_method_api_base@@Base+0x269552>
│ │  			@ <UNDEFINED> instruction: 0xebfe4000
│ │ @@ -1138462,15 +1138462,15 @@
│ │  	b.n	3d6b1e <uniffi_pbcli_checksum_method_api_base@@Base+0x26a29a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3d6500 <uniffi_pbcli_checksum_method_api_base@@Base+0x269c7c>
│ │  	subs	r1, r7, r2
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3d672a <uniffi_pbcli_checksum_method_api_base@@Base+0x269ea6>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, sl, fp, ip}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r5, sl, fp, ip}
│ │  	vaddl.u8	q8, d12, d0
│ │  	b.n	3d6a96 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a212>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (3d643c <uniffi_pbcli_checksum_method_api_base@@Base+0x269bb8>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3d691c <uniffi_pbcli_checksum_method_api_base@@Base+0x26a098>
│ │  	ands	r0, r0
│ │ @@ -1138487,15 +1138487,15 @@
│ │  	b.n	3d675e <uniffi_pbcli_checksum_method_api_base@@Base+0x269eda>
│ │  	movs	r0, #54	@ 0x36
│ │  	b.n	3d6b62 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a2de>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3d6544 <uniffi_pbcli_checksum_method_api_base@@Base+0x269cc0>
│ │  	ldr	r4, [pc, #64]	@ (3d6468 <uniffi_pbcli_checksum_method_api_base@@Base+0x269be4>)
│ │  	ldmia.w	sp!, {r0, r1, r2, r5, r7, r9, fp, ip}
│ │ -			@ <UNDEFINED> instruction: 0xeafd1bd3
│ │ +			@ <UNDEFINED> instruction: 0xeafd1bfa
│ │  			@ <UNDEFINED> instruction: 0xffcc4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3d6954 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a0d0>
│ │  	beq.n	3d644c <uniffi_pbcli_checksum_method_api_base@@Base+0x269bc8>
│ │  	b.n	3d68d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a054>
│ │  	str	r3, [r0, #0]
│ │  	b.n	3d6782 <uniffi_pbcli_checksum_method_api_base@@Base+0x269efe>
│ │ @@ -1138592,16 +1138592,16 @@
│ │  	b.n	3d6c4a <uniffi_pbcli_checksum_method_api_base@@Base+0x26a3c6>
│ │  	lsls	r2, r3, #11
│ │  			@ <UNDEFINED> instruction: 0xebfc0005
│ │  	b.n	3d6852 <uniffi_pbcli_checksum_method_api_base@@Base+0x269fce>
│ │  	beq.n	3d6544 <uniffi_pbcli_checksum_method_api_base@@Base+0x269cc0>
│ │  	b.n	3d69ac <uniffi_pbcli_checksum_method_api_base@@Base+0x26a128>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r1, r2, r8, r9, fp, ip}
│ │ -	vsra.u64	<illegal reg q9.5>, q3, #52
│ │ +	ldmia.w	sp!, {r1, r2, r3, r5, r8, r9, fp, ip}
│ │ +	vsra.u64	<illegal reg q9.5>, <illegal reg q14.5>, #52
│ │  			@ <UNDEFINED> instruction: 0xffcc4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3d6a44 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a1c0>
│ │  	beq.n	3d653c <uniffi_pbcli_checksum_method_api_base@@Base+0x269cb8>
│ │  	b.n	3d69c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a144>
│ │  	movs	r0, r0
│ │  	b.n	3d6bd6 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a352>
│ │ @@ -1139007,20 +1139007,20 @@
│ │  	b.n	3d6fee <uniffi_pbcli_checksum_method_api_base@@Base+0x26a76a>
│ │  	lsls	r1, r6, #7
│ │  			@ <UNDEFINED> instruction: 0xebfc0007
│ │  	b.n	3d6bf6 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a372>
│ │  	beq.n	3d68e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a064>
│ │  	b.n	3d6d50 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a4cc>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r1, r5, r7, r8, ip, sp}
│ │ -	vqshl.u64	d17, d7, #12
│ │ +	ldmia.w	sp!, {r0, r3, r6, r7, r8, ip, sp}
│ │ +	vqshl.u64	d17, d30, #12
│ │  	vqshrun.s16	d29, <illegal reg q1.5>, #4
│ │  			@ <UNDEFINED> instruction: 0xffcaadbe
│ │ -			@ <UNDEFINED> instruction: 0xffca1763
│ │ -			@ <UNDEFINED> instruction: 0xffcc2e32
│ │ +	vabdl.u8	<illegal reg q8.5>, d26, d10
│ │ +			@ <UNDEFINED> instruction: 0xffcc2e59
│ │  	vaddl.u8	q9, d28, d31
│ │  			@ <UNDEFINED> instruction: 0xffca4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3d6dfc <uniffi_pbcli_checksum_method_api_base@@Base+0x26a578>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3d6c26 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a3a2>
│ │  	b.n	3d7092 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a80e>
│ │ @@ -1139648,15 +1139648,15 @@
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, lr}
│ │  	b.n	3d75be <uniffi_pbcli_checksum_method_api_base@@Base+0x26ad3a>
│ │  	movs	r4, r0
│ │  	b.n	3d71c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a93e>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r1, r3, r4, r8, r9, sl, sp, pc}
│ │ -	vsubw.u8	q15, q13, d15
│ │ +	vrsra.u64	d30, d22, #54
│ │  			@ <UNDEFINED> instruction: 0xffcc4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3d73b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x26ab2c>
│ │  	beq.n	3d6ea8 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a624>
│ │  	b.n	3d7334 <uniffi_pbcli_checksum_method_api_base@@Base+0x26aab0>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3d71de <uniffi_pbcli_checksum_method_api_base@@Base+0x26a95a>
│ │ @@ -1139844,15 +1139844,15 @@
│ │  	asrs	r1, r0, #32
│ │  	b.n	3d7160 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a8dc>
│ │  	asrs	r1, r4, #30
│ │  			@ <UNDEFINED> instruction: 0xebfd0005
│ │  	b.n	3d738a <uniffi_pbcli_checksum_method_api_base@@Base+0x26ab06>
│ │  	ldrh	r4, [r0, #24]
│ │  	ldc	12, cr8, [sp], #448	@ 0x1c0
│ │ -	ldmia.w	sp!, {r1, r3, r7, r8, r9, sl, ip, pc}
│ │ +	ldmia.w	sp!, {r0, r4, r5, r7, r8, r9, sl, ip, pc}
│ │  	vaddl.u8	q8, d12, d0
│ │  	b.n	3d76fa <uniffi_pbcli_checksum_method_api_base@@Base+0x26ae76>
│ │  	vrhadd.u16	d0, d14, d31
│ │  	ldr	r4, [pc, #64]	@ (3d70a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a81c>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3d7580 <uniffi_pbcli_checksum_method_api_base@@Base+0x26acfc>
│ │  	ands	r0, r0
│ │ @@ -1139879,15 +1139879,15 @@
│ │  	b.n	3d73da <uniffi_pbcli_checksum_method_api_base@@Base+0x26ab56>
│ │  	movs	r0, #163	@ 0xa3
│ │  	b.n	3d77de <uniffi_pbcli_checksum_method_api_base@@Base+0x26af5a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3d71c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a93c>
│ │  	ldr	r4, [pc, #64]	@ (3d70e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a860>)
│ │  	ldmia.w	sp!, {r3, r7, r8, r9, sl, ip}
│ │ -			@ <UNDEFINED> instruction: 0xeafd972a
│ │ +			@ <UNDEFINED> instruction: 0xeafd9751
│ │  			@ <UNDEFINED> instruction: 0xffcc4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3d75d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x26ad4c>
│ │  	beq.n	3d7120 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a89c>
│ │  	b.n	3d7554 <uniffi_pbcli_checksum_method_api_base@@Base+0x26acd0>
│ │  	ands	r3, r0
│ │  	b.n	3d73fe <uniffi_pbcli_checksum_method_api_base@@Base+0x26ab7a>
│ │ @@ -1140179,22 +1140179,22 @@
│ │  	b.n	3d7a6e <uniffi_pbcli_checksum_method_api_base@@Base+0x26b1ea>
│ │  	vqrdmlah.s16	q15, <illegal reg q8.5>, <illegal reg q13.5>
│ │  	movs	r1, r1
│ │  	b.n	3d7676 <uniffi_pbcli_checksum_method_api_base@@Base+0x26adf2>
│ │  	beq.n	3d7370 <uniffi_pbcli_checksum_method_api_base@@Base+0x26aaec>
│ │  	b.n	3d77d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x26af4c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r5, r6, r7, sl, ip, pc}
│ │ +	ldmia.w	sp!, {r0, r3, r8, sl, ip, pc}
│ │  	vraddhn.i16	d20, q14, <illegal reg q11.5>
│ │ -	vsri.64	d25, d22, #53
│ │ +	vsri.64	<illegal reg q12.5>, <illegal reg q6.5>, #53
│ │  	vsri.8	q10, <illegal reg q13.5>, #4
│ │ -	vrsra.u8	d24, d10, #5
│ │ +			@ <UNDEFINED> instruction: 0xffcb8341
│ │  	vqshrun.s16	d21, q6, #4
│ │ -	vmls.f<illegal width 8>	<illegal reg q12.5>, q13, d2[6]
│ │ -	vsri.64	<illegal reg q12.5>, q15, #52
│ │ +	vqshlu.s8	d25, d1, #2
│ │ +	vabal.u8	<illegal reg q12.5>, d12, d21
│ │  	vaddl.u8	q8, d12, d4
│ │  	b.n	3d6e82 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a5fe>
│ │  	lsrs	r3, r7, #19
│ │  			@ <UNDEFINED> instruction: 0xeafc4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3d7888 <uniffi_pbcli_checksum_method_api_base@@Base+0x26b004>
│ │  	beq.n	3d7380 <uniffi_pbcli_checksum_method_api_base@@Base+0x26aafc>
│ │ @@ -1140369,15 +1140369,15 @@
│ │  	movs	r0, r0
│ │  	b.n	3d6ff6 <uniffi_pbcli_checksum_method_api_base@@Base+0x26a772>
│ │  	movs	r6, r0
│ │  	b.n	3d782a <uniffi_pbcli_checksum_method_api_base@@Base+0x26afa6>
│ │  	beq.n	3d751c <uniffi_pbcli_checksum_method_api_base@@Base+0x26ac98>
│ │  	b.n	3d7984 <uniffi_pbcli_checksum_method_api_base@@Base+0x26b100>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r1, r3, r8, r9, ip, pc}
│ │ +	ldmia.w	sp!, {r0, r4, r5, r8, r9, ip, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcc9be2
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3d703c <uniffi_pbcli_checksum_method_api_base@@Base+0x26a7b8>
│ │  	movs	r0, r0
│ │  	b.n	3d7620 <uniffi_pbcli_checksum_method_api_base@@Base+0x26ad9c>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldrsb	r4, [r2, r1]
│ │ @@ -1140693,22 +1140693,22 @@
│ │  	lsrs	r2, r4, #10
│ │  	b.n	3d7a60 <uniffi_pbcli_checksum_method_api_base@@Base+0x26b1dc>
│ │  	movs	r4, r0
│ │  	asrs	r0, r0, #12
│ │  			@ <UNDEFINED> instruction: 0xffcfeaff
│ │  	add	r4, pc, #464	@ (adr r4, 3d7994 <uniffi_pbcli_checksum_method_api_base@@Base+0x26b110>)
│ │  			@ <UNDEFINED> instruction: 0xffca5ebd
│ │ -	vsra.u64	d25, d2, #53
│ │ -	vsra.u64	d25, d25, #52
│ │ +	vsra.u64	d25, d25, #53
│ │ +	vmla.f<illegal width 8>	<illegal reg q12.5>, q14, d0[4]
│ │  			@ <UNDEFINED> instruction: 0xffcc9ed6
│ │  	vsubw.u8	<illegal reg q10.5>, q5, d24
│ │ -	vsra.u8	d25, d2, #6
│ │ -	vsra.u8	d25, d25, #4
│ │ -	vaddl.u8	<illegal reg q12.5>, d28, d22
│ │ -	vsubw.u8	<illegal reg q15.5>, q6, d7
│ │ +	vsra.u8	d25, d25, #6
│ │ +	vmla.f<illegal width 8>	<illegal reg q12.5>, q6, d0[4]
│ │ +	vmla.i<illegal width 8>	<illegal reg q12.5>, q14, d1[3]
│ │ +	vsubw.u8	<illegal reg q15.5>, q6, d30
│ │  	vaddl.u8	<illegal reg q8.5>, d11, d4
│ │  	b.n	3d732c <uniffi_pbcli_checksum_method_api_base@@Base+0x26aaa8>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3d7910 <uniffi_pbcli_checksum_method_api_base@@Base+0x26b08c>
│ │  	movs	r0, r0
│ │  	and.w	r4, r0, r4, lsl #20
│ │  	movs	r7, r1
│ │ @@ -1140783,15 +1140783,15 @@
│ │  	b.n	3d7fda <uniffi_pbcli_checksum_method_api_base@@Base+0x26b756>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3d79bc <uniffi_pbcli_checksum_method_api_base@@Base+0x26b138>
│ │  	asrs	r2, r1, #22
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3d7be6 <uniffi_pbcli_checksum_method_api_base@@Base+0x26b362>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r5, r8, r9, sl, fp, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r4, r6, r8, r9, sl, fp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcc4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3d7dd0 <uniffi_pbcli_checksum_method_api_base@@Base+0x26b54c>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3d7bfa <uniffi_pbcli_checksum_method_api_base@@Base+0x26b376>
│ │  	svc	224	@ 0xe0
│ │  			@ <UNDEFINED> instruction: 0xebfe4000
│ │ @@ -1140855,16 +1140855,16 @@
│ │  	b.n	3d8082 <uniffi_pbcli_checksum_method_api_base@@Base+0x26b7fe>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3d7a64 <uniffi_pbcli_checksum_method_api_base@@Base+0x26b1e0>
│ │  	asrs	r0, r4, #21
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3d7c8e <uniffi_pbcli_checksum_method_api_base@@Base+0x26b40a>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r4, r5, r6, r7, r9, sl, fp, pc}
│ │ -	vmull.p8	q12, d28, d6
│ │ +	ldmia.w	sp!, {r0, r3, r4, r8, r9, sl, fp, pc}
│ │ +	vmull.p8	q12, d28, d29
│ │  			@ <UNDEFINED> instruction: 0xffcc4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3d7e7c <uniffi_pbcli_checksum_method_api_base@@Base+0x26b5f8>
│ │  	svc	130	@ 0x82
│ │  	b.n	3d7e00 <uniffi_pbcli_checksum_method_api_base@@Base+0x26b57c>
│ │  	ands	r0, r0
│ │  	b.n	3d7caa <uniffi_pbcli_checksum_method_api_base@@Base+0x26b426>
│ │ @@ -1141090,20 +1141090,20 @@
│ │  	movs	r3, r0
│ │  	b.n	3d828e <uniffi_pbcli_checksum_method_api_base@@Base+0x26ba0a>
│ │  	lsrs	r6, r4, #10
│ │  	b.n	3d7df4 <uniffi_pbcli_checksum_method_api_base@@Base+0x26b570>
│ │  	movs	r4, r0
│ │  	asrs	r0, r0, #12
│ │  			@ <UNDEFINED> instruction: 0xffa3eaff
│ │ -	ldrh	r6, [r3, #48]	@ 0x30
│ │ -	vshr.u8	q11, q6, #4
│ │ -			@ <UNDEFINED> instruction: 0xffcc8d8e
│ │ -	vqrdmlsh.s<illegal width 8>	<illegal reg q10.5>, q14, d0[3]
│ │ -			@ <UNDEFINED> instruction: 0xffcc8dbe
│ │ -	vshr.u8	d31, d15, #4
│ │ +	ldrh	r5, [r0, #50]	@ 0x32
│ │ +	vaddl.u8	q11, d28, d3
│ │ +			@ <UNDEFINED> instruction: 0xffcc8db5
│ │ +			@ <UNDEFINED> instruction: 0xffcc5ff3
│ │ +	vqrdmulh.s<illegal width 8>	q12, q14, d1[5]
│ │ +	vmla.i<illegal width 8>	<illegal reg q15.5>, q6, d2[1]
│ │  	vqshrun.s16	d20, q8, #5
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3d8094 <uniffi_pbcli_checksum_method_api_base@@Base+0x26b810>
│ │  	ands	r0, r0
│ │  	b.n	3d7ebe <uniffi_pbcli_checksum_method_api_base@@Base+0x26b63a>
│ │  	svc	47	@ 0x2f
│ │  			@ <UNDEFINED> instruction: 0xebfe5000
│ │ @@ -1141727,15 +1141727,15 @@
│ │  	b.n	3d886e <uniffi_pbcli_checksum_method_api_base@@Base+0x26bfea>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3d8876 <uniffi_pbcli_checksum_method_api_base@@Base+0x26bff2>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r2, r4, sl, ip, lr}
│ │  			@ <UNDEFINED> instruction: 0xffcbbf14
│ │ -	vrsra.u64	<illegal reg q14.5>, q15, #53
│ │ +	vraddhn.i16	d29, <illegal reg q5.5>, <illegal reg q10.5>
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3d7c88 <uniffi_pbcli_checksum_method_api_base@@Base+0x26b404>
│ │  	movs	r0, r0
│ │  	b.n	3d826c <uniffi_pbcli_checksum_method_api_base@@Base+0x26b9e8>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r4, [pc, #128]	@ (3d81d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x26b950>)
│ │  	movs	r7, r1
│ │ @@ -1141888,15 +1141888,15 @@
│ │  	movs	r6, r0
│ │  	b.n	3d85e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x26bd62>
│ │  	beq.n	3d82c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x26ba44>
│ │  	b.n	3d8740 <uniffi_pbcli_checksum_method_api_base@@Base+0x26bebc>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r2, r4, r5, r8, r9, ip, lr}
│ │  			@ <UNDEFINED> instruction: 0xffcbbe18
│ │ -	vsubw.u8	<illegal reg q14.5>, <illegal reg q5.5>, d10
│ │ +	vrsra.u8	d29, d17, #5
│ │  	vrsra.u8	d25, d2, #5
│ │  	vaddl.u8	q8, d10, d28
│ │  	b.n	3d7de2 <uniffi_pbcli_checksum_method_api_base@@Base+0x26b55e>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r0, r0
│ │  	b.n	3d896c <uniffi_pbcli_checksum_method_api_base@@Base+0x26c0e8>
│ │  	asrs	r0, r2, #32
│ │ @@ -1143044,15 +1143044,15 @@
│ │  	movs	r4, r0
│ │  	b.n	3d8f4a <uniffi_pbcli_checksum_method_api_base@@Base+0x26c6c6>
│ │  	beq.n	3d8c2c <uniffi_pbcli_checksum_method_api_base@@Base+0x26c3a8>
│ │  	b.n	3d90a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x26c820>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, r2, r3, r7, sl, ip, sp, pc}
│ │  	vraddhn.i16	d27, <illegal reg q5.5>, <illegal reg q8.5>
│ │ -	vmlal.u<illegal width 8>	<illegal reg q12.5>, d27, d0[0]
│ │ +	vmlal.u<illegal width 8>	<illegal reg q12.5>, d27, d3[5]
│ │  			@ <UNDEFINED> instruction: 0xffcc4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3d9140 <uniffi_pbcli_checksum_method_api_base@@Base+0x26c8bc>
│ │  	beq.n	3d8c38 <uniffi_pbcli_checksum_method_api_base@@Base+0x26c3b4>
│ │  	b.n	3d90c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x26c840>
│ │  	str	r3, [r0, #0]
│ │  	b.n	3d8f6e <uniffi_pbcli_checksum_method_api_base@@Base+0x26c6ea>
│ │ @@ -1143942,35 +1143942,35 @@
│ │  	b.n	3d96cc <uniffi_pbcli_checksum_method_api_base@@Base+0x26ce48>
│ │  	lsls	r0, r4, #10
│ │  	b.n	3d9732 <uniffi_pbcli_checksum_method_api_base@@Base+0x26ceae>
│ │  	beq.n	3d942c <uniffi_pbcli_checksum_method_api_base@@Base+0x26cba8>
│ │  	b.n	3d988c <uniffi_pbcli_checksum_method_api_base@@Base+0x26d008>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r0, r2, r7, r8, r9, sl, fp, sp, pc}
│ │ -	vqrdmlah.s<illegal width 8>	q12, <illegal reg q5.5>, d3[3]
│ │ +			@ <UNDEFINED> instruction: 0xffcb8e76
│ │  	vshr.u64	d27, d28, #52
│ │  			@ <UNDEFINED> instruction: 0xffd1af39
│ │ -	vmull.p8	q12, d11, d3
│ │ +	vmull.p8	q12, d11, d26
│ │  			@ <UNDEFINED> instruction: 0xffccaef9
│ │ -	vqrdmulh.s<illegal width 8>	q12, <illegal reg q13.5>, d3[0]
│ │ +	vqrdmulh.s<illegal width 8>	q12, <illegal reg q13.5>, d2[6]
│ │  	vmull.p8	q13, d12, d13
│ │ -			@ <UNDEFINED> instruction: 0xffcb8cd7
│ │ +			@ <UNDEFINED> instruction: 0xffcb8cfe
│ │  	vqrdmulh.s<illegal width 8>	q13, q14, d1[1]
│ │ -	vmull.u8	q12, d27, d15
│ │ +			@ <UNDEFINED> instruction: 0xffcb8cb6
│ │  			@ <UNDEFINED> instruction: 0xffccae79
│ │  			@ <UNDEFINED> instruction: 0xffcbada9
│ │ -			@ <UNDEFINED> instruction: 0xffcb8c73
│ │ +			@ <UNDEFINED> instruction: 0xffcb8c9a
│ │  	vmull.p8	q13, d12, d25
│ │ -			@ <UNDEFINED> instruction: 0xffcb8cf3
│ │ +			@ <UNDEFINED> instruction: 0xffcb8d1a
│ │  	vqdmulh.s<illegal width 8>	q13, q6, d1[6]
│ │ -			@ <UNDEFINED> instruction: 0xffcb8b33
│ │ +			@ <UNDEFINED> instruction: 0xffcb8b5a
│ │  	vqdmulh.s<illegal width 8>	q13, q6, d1[0]
│ │ -			@ <UNDEFINED> instruction: 0xffcb8b0b
│ │ +			@ <UNDEFINED> instruction: 0xffcb8b32
│ │  			@ <UNDEFINED> instruction: 0xffccad3d
│ │ -	vmull.u8	q12, d11, d7
│ │ +	vmull.u8	q12, d11, d30
│ │  			@ <UNDEFINED> instruction: 0xffcc4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3d9974 <uniffi_pbcli_checksum_method_api_base@@Base+0x26d0f0>
│ │  	beq.n	3d9484 <uniffi_pbcli_checksum_method_api_base@@Base+0x26cc00>
│ │  	b.n	3d98f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x26d074>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	3d97a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x26cf1e>
│ │ @@ -1144958,15 +1144958,15 @@
│ │  	lsls	r0, r4, #15
│ │  	beq.n	3d9d24 <uniffi_pbcli_checksum_method_api_base@@Base+0x26d4a0>
│ │  	b.n	3da1ac <uniffi_pbcli_checksum_method_api_base@@Base+0x26d928>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r1, r2, r5, r6, sl, ip, lr, pc}
│ │  	vrsra.u8	d26, d17, #6
│ │  	vmull.p8	<illegal reg q10.5>, d27, d8
│ │ -	vqrdmulh.s<illegal width 8>	q14, q5, d1[3]
│ │ +			@ <UNDEFINED> instruction: 0xffcacd74
│ │  	vqshrun.s16	d20, q8, #5
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3da24c <uniffi_pbcli_checksum_method_api_base@@Base+0x26d9c8>
│ │  	ands	r1, r0
│ │  	b.n	3da476 <uniffi_pbcli_checksum_method_api_base@@Base+0x26dbf2>
│ │  	movs	r0, r0
│ │  	b.n	3da3da <uniffi_pbcli_checksum_method_api_base@@Base+0x26db56>
│ │ @@ -1145032,15 +1145032,15 @@
│ │  	ands	r0, r0
│ │  	b.n	3da502 <uniffi_pbcli_checksum_method_api_base@@Base+0x26dc7e>
│ │  	bfcsel	12, 3da5ba <uniffi_pbcli_checksum_method_api_base@@Base+0x26dd36>, 14, lt
│ │  	movs	r4, r0
│ │  	b.n	3da10a <uniffi_pbcli_checksum_method_api_base@@Base+0x26d886>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r3, r6, r9, sp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffcb6a5d
│ │ +	vmlsl.u8	q11, d27, d4
│ │  	vsri.64	<illegal reg q14.5>, q2, #52
│ │  	bmi.n	3d9d82 <uniffi_pbcli_checksum_method_api_base@@Base+0x26d4fe>
│ │  	bmi.n	3d9d84 <uniffi_pbcli_checksum_method_api_base@@Base+0x26d500>
│ │  	bmi.n	3d9d86 <uniffi_pbcli_checksum_method_api_base@@Base+0x26d502>
│ │  	bmi.n	3d9d88 <uniffi_pbcli_checksum_method_api_base@@Base+0x26d504>
│ │  	bmi.n	3d9d8a <uniffi_pbcli_checksum_method_api_base@@Base+0x26d506>
│ │  	ldr	r5, [pc, #960]	@ (3da1a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x26d920>)
│ │ @@ -1145510,15 +1145510,15 @@
│ │  	movs	r1, r7
│ │  	b.n	3da942 <uniffi_pbcli_checksum_method_api_base@@Base+0x26e0be>
│ │  	asrs	r1, r1, #3
│ │  	b.n	3da946 <uniffi_pbcli_checksum_method_api_base@@Base+0x26e0c2>
│ │  			@ <UNDEFINED> instruction: 0xffe1eaff
│ │  	ldr	r6, [sp, #452]	@ 0x1c4
│ │  	vqshlu.s64	<illegal reg q13.5>, q15, #11
│ │ -	vabdl.u8	q11, d10, d26
│ │ +	vqshl.u8	q11, <illegal reg q0.5>, #2
│ │  	vmull.p8	<illegal reg q12.5>, d12, d29
│ │  			@ <UNDEFINED> instruction: 0xffcb5984
│ │  	vrsubhn.i16	d27, q13, q5
│ │  			@ <UNDEFINED> instruction: 0xffca9e95
│ │  	vabdl.u8	<illegal reg q13.5>, d11, d18
│ │  	vaddl.u8	q8, d10, d0
│ │  	b.n	3da8ce <uniffi_pbcli_checksum_method_api_base@@Base+0x26e04a>
│ │ @@ -1145750,19 +1145750,19 @@
│ │  	movs	r1, r0
│ │  	b.n	3dab6e <uniffi_pbcli_checksum_method_api_base@@Base+0x26e2ea>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3dab76 <uniffi_pbcli_checksum_method_api_base@@Base+0x26e2f2>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r4, r5, r7, r9, ip, lr, pc}
│ │ -	vsli.8	q11, q15, #2
│ │ +	vabal.u8	q11, d26, d21
│ │  			@ <UNDEFINED> instruction: 0xffcccdaf
│ │  			@ <UNDEFINED> instruction: 0xffcafdda
│ │ -	vqshlu.s64	<illegal reg q9.5>, q14, #10
│ │ -	vshr.u8	q9, <illegal reg q13.5>, #4
│ │ +	vabdl.u8	<illegal reg q9.5>, d10, d19
│ │ +	vaddl.u8	q9, d28, d18
│ │  			@ <UNDEFINED> instruction: 0xffcccd1e
│ │  	vsri.8	d17, d23, #6
│ │  	vqrdmulh.s<illegal width 8>	q13, <illegal reg q5.5>, d0[6]
│ │  	vqshlu.s8	d18, d14, #2
│ │  	vsli.64	d31, d19, #10
│ │  			@ <UNDEFINED> instruction: 0xffca48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │ @@ -1145828,15 +1145828,15 @@
│ │  	b.n	3d9ff6 <uniffi_pbcli_checksum_method_api_base@@Base+0x26d772>
│ │  	movs	r1, r0
│ │  	b.n	3dac32 <uniffi_pbcli_checksum_method_api_base@@Base+0x26e3ae>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3dac3a <uniffi_pbcli_checksum_method_api_base@@Base+0x26e3b6>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r6, r7, r8, sl, lr}
│ │ +	ldmia.w	sp!, {r1, r9, sl, lr}
│ │  			@ <UNDEFINED> instruction: 0xffcccbde
│ │  			@ <UNDEFINED> instruction: 0xffca4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3daa28 <uniffi_pbcli_checksum_method_api_base@@Base+0x26e1a4>
│ │  	ands	r1, r0
│ │  	b.n	3dac52 <uniffi_pbcli_checksum_method_api_base@@Base+0x26e3ce>
│ │  	movs	r0, r0
│ │ @@ -1146023,15 +1146023,15 @@
│ │  	movs	r0, #2
│ │  	b.n	3da7d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x26df50>
│ │  	lsrs	r7, r7, #27
│ │  			@ <UNDEFINED> instruction: 0xebfd0004
│ │  	b.n	3da9fe <uniffi_pbcli_checksum_method_api_base@@Base+0x26e17a>
│ │  	ldr	r0, [pc, #192]	@ (3da780 <uniffi_pbcli_checksum_method_api_base@@Base+0x26defc>)
│ │  	ldmia.w	sp!, {r3, r4, r6, r7, r9, sl, fp, ip, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xeaff4a6d
│ │ +			@ <UNDEFINED> instruction: 0xeaff4a94
│ │  			@ <UNDEFINED> instruction: 0xffcc4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3dabec <uniffi_pbcli_checksum_method_api_base@@Base+0x26e368>
│ │  	beq.n	3da6e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x26de60>
│ │  	b.n	3dab70 <uniffi_pbcli_checksum_method_api_base@@Base+0x26e2ec>
│ │  	ands	r0, r0
│ │  	b.n	3daa1a <uniffi_pbcli_checksum_method_api_base@@Base+0x26e196>
│ │ @@ -1146351,15 +1146351,15 @@
│ │  	adds	r7, #200	@ 0xc8
│ │  			@ <UNDEFINED> instruction: 0xebfd0006
│ │  	b.n	3dace6 <uniffi_pbcli_checksum_method_api_base@@Base+0x26e462>
│ │  	beq.n	3da9d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x26e154>
│ │  	b.n	3dae40 <uniffi_pbcli_checksum_method_api_base@@Base+0x26e5bc>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, r1, r3, r4, r6, r8, r9, ip, sp}
│ │ -			@ <UNDEFINED> instruction: 0xffcbef56
│ │ +			@ <UNDEFINED> instruction: 0xffcbef7d
│ │  			@ <UNDEFINED> instruction: 0xffcb4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3daed8 <uniffi_pbcli_checksum_method_api_base@@Base+0x26e654>
│ │  	ands	r0, r0
│ │  	b.n	3dad02 <uniffi_pbcli_checksum_method_api_base@@Base+0x26e47e>
│ │  	movs	r0, r0
│ │  	b.n	3da4e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x26dc62>
│ │ @@ -1146638,15 +1146638,15 @@
│ │  	movs	r0, r0
│ │  	movs	r1, r0
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │  			@ <UNDEFINED> instruction: 0xffff7fff
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │ -	cmp	r5, ip
│ │ +	cmp	ip, r1
│ │  			@ <UNDEFINED> instruction: 0xffcc4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3db158 <uniffi_pbcli_checksum_method_api_base@@Base+0x26e8d4>
│ │  	beq.n	3dac68 <uniffi_pbcli_checksum_method_api_base@@Base+0x26e3e4>
│ │  	b.n	3db0dc <uniffi_pbcli_checksum_method_api_base@@Base+0x26e858>
│ │  	movs	r0, r0
│ │  	b.n	3db2e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x26ea64>
│ │ @@ -1149802,27 +1149802,27 @@
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │  			@ <UNDEFINED> instruction: 0xffff7fff
│ │  	movs	r0, r0
│ │  	movs	r0, r0
│ │  			@ <UNDEFINED> instruction: 0xffff7fff
│ │  	adds	r3, r4, r7
│ │ -	vaddw.u8	<illegal reg q9.5>, <illegal reg q13.5>, d13
│ │ -	vsli.64	d29, d2, #12
│ │ +	vsra.u64	d19, d20, #53
│ │ +	vsli.64	d29, d25, #12
│ │  	vsli.8	<illegal reg q12.5>, q3, #3
│ │ -			@ <UNDEFINED> instruction: 0xffca2dbd
│ │ +	vqrdmulh.s<illegal width 8>	q9, q13, d0[5]
│ │  	vshll.u8	q8, d9, #4
│ │ -			@ <UNDEFINED> instruction: 0xffcb2d75
│ │ -			@ <UNDEFINED> instruction: 0xffcc2d05
│ │ -			@ <UNDEFINED> instruction: 0xffcc2cd9
│ │ +			@ <UNDEFINED> instruction: 0xffcb2d9c
│ │ +			@ <UNDEFINED> instruction: 0xffcc2d2c
│ │ +			@ <UNDEFINED> instruction: 0xffcc2d00
│ │  	vqshrn.u16	d16, <illegal reg q10.5>, #4
│ │ -			@ <UNDEFINED> instruction: 0xffcb2bfd
│ │ -	vmull.p8	<illegal reg q15.5>, d28, d20
│ │ -	vqdmulh.s<illegal width 8>	q9, <illegal reg q5.5>, d1[2]
│ │ -			@ <UNDEFINED> instruction: 0xffccfef0
│ │ +	vmull.u8	q9, d11, d20
│ │ +	vqrdmlah.s<illegal width 8>	<illegal reg q15.5>, q14, d3[2]
│ │ +			@ <UNDEFINED> instruction: 0xffcb2c70
│ │ +			@ <UNDEFINED> instruction: 0xffccff17
│ │  			@ <UNDEFINED> instruction: 0xffcb7b75
│ │  			@ <UNDEFINED> instruction: 0xffd14c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3dcc10 <uniffi_pbcli_checksum_method_api_base@@Base+0x27038c>
│ │  	beq.n	3dc728 <uniffi_pbcli_checksum_method_api_base@@Base+0x26fea4>
│ │  	b.n	3dcb94 <uniffi_pbcli_checksum_method_api_base@@Base+0x270310>
│ │  	stmia	r0!, {r2, r6}
│ │ @@ -1151447,15 +1151447,15 @@
│ │  	b.n	3dd2ac <uniffi_pbcli_checksum_method_api_base@@Base+0x270a28>
│ │  			@ <UNDEFINED> instruction: 0xebfb0005
│ │  	b.n	3dd82a <uniffi_pbcli_checksum_method_api_base@@Base+0x270fa6>
│ │  	beq.n	3dd524 <uniffi_pbcli_checksum_method_api_base@@Base+0x270ca0>
│ │  	b.n	3dd984 <uniffi_pbcli_checksum_method_api_base@@Base+0x271100>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {r1, r2, r5, r6, r7, r9, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffc977cb
│ │ +	vqshl.u64	<illegal reg q11.5>, q9, #9
│ │  			@ <UNDEFINED> instruction: 0xffcc4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3dda1c <uniffi_pbcli_checksum_method_api_base@@Base+0x271198>
│ │  	beq.n	3dd53c <uniffi_pbcli_checksum_method_api_base@@Base+0x270cb8>
│ │  	b.n	3dd9a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27111c>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3dd84a <uniffi_pbcli_checksum_method_api_base@@Base+0x270fc6>
│ │ @@ -1152843,15 +1152843,15 @@
│ │  	asrs	r0, r0, #3
│ │  	lsls	r0, r0, #12
│ │  	b.n	3de8d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x272050>
│ │  			@ <UNDEFINED> instruction: 0xebfb0005
│ │  	b.n	3de47a <uniffi_pbcli_checksum_method_api_base@@Base+0x271bf6>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r1, r8, fp, sp, lr, pc}
│ │ -	vraddhn.i16	d21, <illegal reg q4.5>, <illegal reg q5.5>
│ │ +	vsri.8	d21, d18, #7
│ │  	vaddl.u8	q8, d12, d1
│ │  	b.n	3de88a <uniffi_pbcli_checksum_method_api_base@@Base+0x272006>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r1, r0
│ │  	b.n	3de892 <uniffi_pbcli_checksum_method_api_base@@Base+0x27200e>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	vrhadd.u16	d14, d14, d31
│ │ @@ -1152925,16 +1152925,16 @@
│ │  	movs	r1, r0
│ │  	b.n	3de936 <uniffi_pbcli_checksum_method_api_base@@Base+0x2720b2>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3de93e <uniffi_pbcli_checksum_method_api_base@@Base+0x2720ba>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r3, r5, r7, r8, r9, ip, pc}
│ │ -	vqshlu.s8	q9, q11, #2
│ │ -	vmlal.u8	q8, d28, d7
│ │ +	vqshlu.s64	d18, d13, #10
│ │ +	vmlal.u8	q8, d28, d30
│ │  	vaddl.u8	q8, d12, d1
│ │  	b.n	3de952 <uniffi_pbcli_checksum_method_api_base@@Base+0x2720ce>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r7, [pc, #960]	@ (3de5d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x271d54>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3de738 <uniffi_pbcli_checksum_method_api_base@@Base+0x271eb4>
│ │  	beq.n	3de228 <uniffi_pbcli_checksum_method_api_base@@Base+0x2719a4>
│ │ @@ -1153586,20 +1153586,20 @@
│ │  	and.w	r0, r0, r0, lsl #24
│ │  	b.n	3def16 <uniffi_pbcli_checksum_method_api_base@@Base+0x272692>
│ │  	movs	r6, r0
│ │  	b.n	3deb1a <uniffi_pbcli_checksum_method_api_base@@Base+0x272296>
│ │  	beq.n	3de7fc <uniffi_pbcli_checksum_method_api_base@@Base+0x271f78>
│ │  	b.n	3dec74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2723f0>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r1, r2, r3, r4, r5, r6, r8, sp}
│ │ +	ldmia.w	sp!, {r0, r2, r5, r7, r8, sp}
│ │  	vmul.f<illegal width 8>	q9, q14, d3[5]
│ │  	vqrdmlsh.s<illegal width 8>	<illegal reg q9.5>, <illegal reg q5.5>, d2[2]
│ │ -	vabdl.u8	<illegal reg q9.5>, d27, d30
│ │ +	vqshl.u64	<illegal reg q9.5>, <illegal reg q2.5>, #11
│ │  	vqrdmlah.s<illegal width 8>	<illegal reg q9.5>, q14, d2[6]
│ │ -	vrshr.u64	q8, <illegal reg q3.5>, #53
│ │ +	vrshr.u64	q8, q15, #53
│ │  			@ <UNDEFINED> instruction: 0xffcc58df
│ │  	vaddl.u8	q8, d10, d4
│ │  	b.n	3de340 <uniffi_pbcli_checksum_method_api_base@@Base+0x271abc>
│ │  	movs	r0, r0
│ │  	b.n	3de924 <uniffi_pbcli_checksum_method_api_base@@Base+0x2720a0>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	cdp	0, 2, cr0, cr12, cr14, {0}
│ │ @@ -1153685,16 +1153685,16 @@
│ │  	movs	r1, r0
│ │  	b.n	3df002 <uniffi_pbcli_checksum_method_api_base@@Base+0x27277e>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3df00a <uniffi_pbcli_checksum_method_api_base@@Base+0x272786>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r2, r8, sl, fp, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffca1fd2
│ │ -	vmla.f<illegal width 8>	q8, q14, d3[4]
│ │ +			@ <UNDEFINED> instruction: 0xffca1ff9
│ │ +	vsubl.u8	q8, d12, d10
│ │  			@ <UNDEFINED> instruction: 0xffcc57eb
│ │  	vaddl.u8	q8, d10, d1
│ │  	b.n	3df022 <uniffi_pbcli_checksum_method_api_base@@Base+0x27279e>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	movs	r0, #20
│ │  	b.n	3de40a <uniffi_pbcli_checksum_method_api_base@@Base+0x271b86>
│ │  	movs	r4, r3
│ │ @@ -1154401,17 +1154401,17 @@
│ │  	b.n	3df62a <uniffi_pbcli_checksum_method_api_base@@Base+0x272da6>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3df00c <uniffi_pbcli_checksum_method_api_base@@Base+0x272788>
│ │  	blx	3d56e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x268e64>
│ │  	movs	r4, r0
│ │  	b.n	3df236 <uniffi_pbcli_checksum_method_api_base@@Base+0x2729b2>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r5, r7, r9, sl, lr}
│ │ -	vmlsl.u<illegal width 8>	q10, d12, d3[5]
│ │ -	vqshlu.s8	d20, d31, #4
│ │ +	ldmia.w	sp!, {r1, r2, r3, r6, r7, r9, sl, lr}
│ │ +	vrsubhn.i16	d20, q14, q7
│ │ +	vmlsl.u<illegal width 8>	q10, d12, d2[5]
│ │  	vmlal.u8	q10, d12, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3df24e <uniffi_pbcli_checksum_method_api_base@@Base+0x2729ca>
│ │  	beq.n	3def20 <uniffi_pbcli_checksum_method_api_base@@Base+0x27269c>
│ │  	b.n	3df3ac <uniffi_pbcli_checksum_method_api_base@@Base+0x272b28>
│ │  	stmia	r0!, {r1}
│ │  	b.n	3df256 <uniffi_pbcli_checksum_method_api_base@@Base+0x2729d2>
│ │ @@ -1154940,15 +1154940,15 @@
│ │  	b.n	3df6ee <uniffi_pbcli_checksum_method_api_base@@Base+0x272e6a>
│ │  	asrs	r5, r0, #32
│ │  	b.n	3df6f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x272e6e>
│ │  	movs	r2, #111	@ 0x6f
│ │  	b.n	3df9b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x273132>
│ │  	ldr	r0, [pc, #192]	@ (3df478 <uniffi_pbcli_checksum_method_api_base@@Base+0x272bf4>)
│ │  	ldmia.w	sp!, {r0, r1, r6, r7, r9, sl, ip, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xeafc41a3
│ │ +			@ <UNDEFINED> instruction: 0xeafc41ca
│ │  			@ <UNDEFINED> instruction: 0xffcc48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3df8e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x273060>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3df70e <uniffi_pbcli_checksum_method_api_base@@Base+0x272e8a>
│ │  	stmia	r1!, {r0, r1, r3, r4}
│ │  			@ <UNDEFINED> instruction: 0xebfe7000
│ │ @@ -1155096,17 +1155096,17 @@
│ │  	b.n	3df84a <uniffi_pbcli_checksum_method_api_base@@Base+0x272fc6>
│ │  	movs	r2, #111	@ 0x6f
│ │  	b.n	3dfb0e <uniffi_pbcli_checksum_method_api_base@@Base+0x27328a>
│ │  	blx	24dd08 <uniffi_pbcli_checksum_method_api_base@@Base+0xe1484>
│ │  	movs	r7, r0
│ │  	b.n	3df856 <uniffi_pbcli_checksum_method_api_base@@Base+0x272fd2>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r8, lr}
│ │ -	vmla.i<illegal width 8>	q10, q6, d3[3]
│ │ -	vaddl.u8	q10, d28, d15
│ │ +	ldmia.w	sp!, {r1, r2, r5, r6, r8, lr}
│ │ +	vshr.u8	q10, q11, #4
│ │ +	vshr.u64	d20, d22, #52
│ │  			@ <UNDEFINED> instruction: 0xffcc4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3dfa48 <uniffi_pbcli_checksum_method_api_base@@Base+0x2731c4>
│ │  	ands	r0, r0
│ │  	b.n	3dfc72 <uniffi_pbcli_checksum_method_api_base@@Base+0x2733ee>
│ │  	movs	r0, r0
│ │  	b.n	3dfbd6 <uniffi_pbcli_checksum_method_api_base@@Base+0x273352>
│ │ @@ -1155182,15 +1155182,15 @@
│ │  	ldmia.w	sp!, {r0, lr}
│ │  	b.n	3dfd12 <uniffi_pbcli_checksum_method_api_base@@Base+0x27348e>
│ │  	movs	r4, r0
│ │  	b.n	3df916 <uniffi_pbcli_checksum_method_api_base@@Base+0x273092>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r3, r4, r7, sl, sp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffca8c9c
│ │ -			@ <UNDEFINED> instruction: 0xffc9fbb1
│ │ +			@ <UNDEFINED> instruction: 0xffc9fbd8
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3df128 <uniffi_pbcli_checksum_method_api_base@@Base+0x2728a4>
│ │  	movs	r0, r0
│ │  	b.n	3df70c <uniffi_pbcli_checksum_method_api_base@@Base+0x272e88>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	b.n	3df374 <uniffi_pbcli_checksum_method_api_base@@Base+0x272af0>
│ │  	movs	r6, r1
│ │ @@ -1155319,17 +1155319,17 @@
│ │  	b.n	3dfa46 <uniffi_pbcli_checksum_method_api_base@@Base+0x2731c2>
│ │  	beq.n	3df738 <uniffi_pbcli_checksum_method_api_base@@Base+0x272eb4>
│ │  	b.n	3dfba0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27331c>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {ip, lr}
│ │  	b.n	3dfe52 <uniffi_pbcli_checksum_method_api_base@@Base+0x2735ce>
│ │  			@ <UNDEFINED> instruction: 0xfffaeaff
│ │ -			@ <UNDEFINED> instruction: 0xfb31ffcb
│ │ +			@ <UNDEFINED> instruction: 0xfb58ffcb
│ │  	ldrh	r4, [r1, #30]
│ │ -			@ <UNDEFINED> instruction: 0xffc9fdb9
│ │ +	vqrdmulh.s<illegal width 8>	<illegal reg q15.5>, <illegal reg q12.5>, d0[4]
│ │  	vaddl.u8	q8, d11, d0
│ │  	b.n	3dfdc6 <uniffi_pbcli_checksum_method_api_base@@Base+0x273542>
│ │  	movs	r4, r0
│ │  	lsrs	r0, r0, #8
│ │  	movs	r0, r2
│ │  	b.n	3df2ce <uniffi_pbcli_checksum_method_api_base@@Base+0x272a4a>
│ │  	movs	r2, r0
│ │ @@ -1155392,15 +1155392,15 @@
│ │  	b.n	3df2d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x272a50>
│ │  	adds	r0, #3
│ │  	b.n	3df8dc <uniffi_pbcli_checksum_method_api_base@@Base+0x273058>
│ │  	lsls	r7, r0, #14
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3dfb06 <uniffi_pbcli_checksum_method_api_base@@Base+0x273282>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r6, r8, fp, sp}
│ │ +	ldmia.w	sp!, {r2, r7, r8, fp, sp}
│ │  	vmlal.u8	q10, d12, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3dfb16 <uniffi_pbcli_checksum_method_api_base@@Base+0x273292>
│ │  	beq.n	3df7e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x272f64>
│ │  	b.n	3dfc74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2733f0>
│ │  	adds	r0, #20
│ │  	b.n	3df31c <uniffi_pbcli_checksum_method_api_base@@Base+0x272a98>
│ │ @@ -1155410,15 +1155410,15 @@
│ │  	b.n	3df300 <uniffi_pbcli_checksum_method_api_base@@Base+0x272a7c>
│ │  	adds	r0, #3
│ │  	b.n	3df908 <uniffi_pbcli_checksum_method_api_base@@Base+0x273084>
│ │  	lsls	r4, r7, #13
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3dfb32 <uniffi_pbcli_checksum_method_api_base@@Base+0x2732ae>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r4, r5, r8, fp, sp}
│ │ +	ldmia.w	sp!, {r3, r4, r6, r8, fp, sp}
│ │  	vaddl.u8	q8, d12, d0
│ │  	b.n	3dfe9e <uniffi_pbcli_checksum_method_api_base@@Base+0x27361a>
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	lsls	r4, r2, #5
│ │  	b.n	3df32a <uniffi_pbcli_checksum_method_api_base@@Base+0x272aa6>
│ │ @@ -1155510,15 +1155510,15 @@
│ │  	b.n	3df3e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x272b60>
│ │  	adds	r0, #3
│ │  	b.n	3df9ec <uniffi_pbcli_checksum_method_api_base@@Base+0x273168>
│ │  	lsls	r3, r0, #13
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3dfc16 <uniffi_pbcli_checksum_method_api_base@@Base+0x273392>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r6, fp, sp}
│ │ +	ldmia.w	sp!, {r2, r4, r5, r6, fp, sp}
│ │  	vmlal.u8	q10, d12, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3dfc26 <uniffi_pbcli_checksum_method_api_base@@Base+0x2733a2>
│ │  	beq.n	3df8f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x273074>
│ │  	b.n	3dfd84 <uniffi_pbcli_checksum_method_api_base@@Base+0x273500>
│ │  	adds	r0, #20
│ │  	b.n	3df42c <uniffi_pbcli_checksum_method_api_base@@Base+0x272ba8>
│ │ @@ -1155528,15 +1155528,15 @@
│ │  	b.n	3df410 <uniffi_pbcli_checksum_method_api_base@@Base+0x272b8c>
│ │  	adds	r0, #3
│ │  	b.n	3dfa18 <uniffi_pbcli_checksum_method_api_base@@Base+0x273194>
│ │  	lsls	r0, r7, #12
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3dfc42 <uniffi_pbcli_checksum_method_api_base@@Base+0x2733be>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r5, fp, sp}
│ │ +	ldmia.w	sp!, {r3, r6, fp, sp}
│ │  			@ <UNDEFINED> instruction: 0xffcc4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3dfe2c <uniffi_pbcli_checksum_method_api_base@@Base+0x2735a8>
│ │  	beq.n	3df9b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x273130>
│ │  	b.n	3dfdb0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27352c>
│ │  	ands	r0, r0
│ │  	b.n	3e005a <uniffi_pbcli_checksum_method_api_base@@Base+0x2737d6>
│ │ @@ -1155713,17 +1155713,17 @@
│ │  	b.n	3dfdce <uniffi_pbcli_checksum_method_api_base@@Base+0x27354a>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, ip, lr}
│ │  	b.n	3e01d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x273952>
│ │  	movs	r5, r0
│ │  	b.n	3dfdda <uniffi_pbcli_checksum_method_api_base@@Base+0x273556>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r4, r6, r8, r9, sl, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r5, r6, r8, r9, sl, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcb0f3c
│ │ -			@ <UNDEFINED> instruction: 0xffcb3ad3
│ │ +			@ <UNDEFINED> instruction: 0xffcb3afa
│ │  	vaddl.u8	q8, d12, d0
│ │  	b.n	3e014e <uniffi_pbcli_checksum_method_api_base@@Base+0x2738ca>
│ │  	movs	r4, r0
│ │  	lsrs	r0, r0, #8
│ │  	movs	r4, r1
│ │  	b.n	3df5d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x272d52>
│ │  	lsrs	r2, r0, #4
│ │ @@ -1155967,15 +1155967,15 @@
│ │  	b.n	3df814 <uniffi_pbcli_checksum_method_api_base@@Base+0x272f90>
│ │  	adds	r0, #3
│ │  	b.n	3dfe1c <uniffi_pbcli_checksum_method_api_base@@Base+0x273598>
│ │  	lsls	r7, r6, #8
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e0046 <uniffi_pbcli_checksum_method_api_base@@Base+0x2737c2>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r7, fp, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r5, r7, fp, sp, lr}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e0056 <uniffi_pbcli_checksum_method_api_base@@Base+0x2737d2>
│ │  	beq.n	3dfd28 <uniffi_pbcli_checksum_method_api_base@@Base+0x2734a4>
│ │  	b.n	3e01b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x273930>
│ │  	adds	r0, #20
│ │  	b.n	3df85c <uniffi_pbcli_checksum_method_api_base@@Base+0x272fd8>
│ │ @@ -1155985,15 +1155985,15 @@
│ │  	b.n	3df840 <uniffi_pbcli_checksum_method_api_base@@Base+0x272fbc>
│ │  	adds	r0, #3
│ │  	b.n	3dfe48 <uniffi_pbcli_checksum_method_api_base@@Base+0x2735c4>
│ │  	lsls	r4, r5, #8
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e0072 <uniffi_pbcli_checksum_method_api_base@@Base+0x2737ee>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r2, r4, r6, fp, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r4, r5, r6, fp, sp, lr}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e0082 <uniffi_pbcli_checksum_method_api_base@@Base+0x2737fe>
│ │  	beq.n	3dfd54 <uniffi_pbcli_checksum_method_api_base@@Base+0x2734d0>
│ │  	b.n	3e01e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27395c>
│ │  	adds	r0, #20
│ │  	b.n	3df888 <uniffi_pbcli_checksum_method_api_base@@Base+0x273004>
│ │ @@ -1156003,15 +1156003,15 @@
│ │  	b.n	3df86c <uniffi_pbcli_checksum_method_api_base@@Base+0x272fe8>
│ │  	adds	r0, #3
│ │  	b.n	3dfe74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2735f0>
│ │  	lsls	r1, r4, #8
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e009e <uniffi_pbcli_checksum_method_api_base@@Base+0x27381a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r3, r5, fp, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r6, fp, sp, lr}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e00ae <uniffi_pbcli_checksum_method_api_base@@Base+0x27382a>
│ │  	beq.n	3dfd80 <uniffi_pbcli_checksum_method_api_base@@Base+0x2734fc>
│ │  	b.n	3e020c <uniffi_pbcli_checksum_method_api_base@@Base+0x273988>
│ │  	adds	r0, #20
│ │  	b.n	3df8b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x273030>
│ │ @@ -1156021,15 +1156021,15 @@
│ │  	b.n	3df898 <uniffi_pbcli_checksum_method_api_base@@Base+0x273014>
│ │  	adds	r0, #3
│ │  	b.n	3dfea0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27361c>
│ │  	lsls	r6, r2, #8
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e00ca <uniffi_pbcli_checksum_method_api_base@@Base+0x273846>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r2, r3, r4, r5, r6, r7, r8, r9, sl, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r5, fp, sp, lr}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e00da <uniffi_pbcli_checksum_method_api_base@@Base+0x273856>
│ │  	beq.n	3dfdac <uniffi_pbcli_checksum_method_api_base@@Base+0x273528>
│ │  	b.n	3e0238 <uniffi_pbcli_checksum_method_api_base@@Base+0x2739b4>
│ │  	adds	r0, #20
│ │  	b.n	3df8e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27305c>
│ │ @@ -1156111,15 +1156111,15 @@
│ │  	b.n	3df974 <uniffi_pbcli_checksum_method_api_base@@Base+0x2730f0>
│ │  	adds	r0, #3
│ │  	b.n	3dff7c <uniffi_pbcli_checksum_method_api_base@@Base+0x2736f8>
│ │  	lsls	r7, r3, #7
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e01a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x273922>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r6, r7, r9, fp, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r5, r6, r7, r9, fp, sp, lr, pc}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e01b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x273932>
│ │  	beq.n	3dfe88 <uniffi_pbcli_checksum_method_api_base@@Base+0x273604>
│ │  	b.n	3e0314 <uniffi_pbcli_checksum_method_api_base@@Base+0x273a90>
│ │  	adds	r0, #20
│ │  	b.n	3df9bc <uniffi_pbcli_checksum_method_api_base@@Base+0x273138>
│ │ @@ -1156129,15 +1156129,15 @@
│ │  	b.n	3df9a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27311c>
│ │  	adds	r0, #3
│ │  	b.n	3dffa8 <uniffi_pbcli_checksum_method_api_base@@Base+0x273724>
│ │  	lsls	r4, r2, #7
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e01d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x27394e>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r7, r9, fp, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r5, r7, r9, fp, sp, lr, pc}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e01e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x27395e>
│ │  	beq.n	3dfeb4 <uniffi_pbcli_checksum_method_api_base@@Base+0x273630>
│ │  	b.n	3e0340 <uniffi_pbcli_checksum_method_api_base@@Base+0x273abc>
│ │  	adds	r0, #20
│ │  	b.n	3df9e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x273164>
│ │ @@ -1156147,15 +1156147,15 @@
│ │  	b.n	3df9cc <uniffi_pbcli_checksum_method_api_base@@Base+0x273148>
│ │  	adds	r0, #3
│ │  	b.n	3dffd4 <uniffi_pbcli_checksum_method_api_base@@Base+0x273750>
│ │  	lsls	r1, r1, #7
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e01fe <uniffi_pbcli_checksum_method_api_base@@Base+0x27397a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r5, r6, r9, fp, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r4, r7, r9, fp, sp, lr, pc}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e020e <uniffi_pbcli_checksum_method_api_base@@Base+0x27398a>
│ │  	beq.n	3dfee0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27365c>
│ │  	b.n	3e036c <uniffi_pbcli_checksum_method_api_base@@Base+0x273ae8>
│ │  	adds	r0, #20
│ │  	b.n	3dfa14 <uniffi_pbcli_checksum_method_api_base@@Base+0x273190>
│ │ @@ -1156165,15 +1156165,15 @@
│ │  	b.n	3df9f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x273174>
│ │  	adds	r0, #3
│ │  	b.n	3e0000 <uniffi_pbcli_checksum_method_api_base@@Base+0x27377c>
│ │  	lsls	r6, r7, #6
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e022a <uniffi_pbcli_checksum_method_api_base@@Base+0x2739a6>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r9, fp, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r5, r6, r9, fp, sp, lr, pc}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e023a <uniffi_pbcli_checksum_method_api_base@@Base+0x2739b6>
│ │  	beq.n	3dff0c <uniffi_pbcli_checksum_method_api_base@@Base+0x273688>
│ │  	b.n	3e0398 <uniffi_pbcli_checksum_method_api_base@@Base+0x273b14>
│ │  	adds	r0, #20
│ │  	b.n	3dfa40 <uniffi_pbcli_checksum_method_api_base@@Base+0x2731bc>
│ │ @@ -1156255,15 +1156255,15 @@
│ │  	b.n	3dfad4 <uniffi_pbcli_checksum_method_api_base@@Base+0x273250>
│ │  	adds	r0, #3
│ │  	b.n	3e00dc <uniffi_pbcli_checksum_method_api_base@@Base+0x273858>
│ │  	lsls	r7, r0, #6
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e0306 <uniffi_pbcli_checksum_method_api_base@@Base+0x273a82>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r6, r7, r8, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r3, r5, r6, r7, r8, fp, ip, sp, lr}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e0316 <uniffi_pbcli_checksum_method_api_base@@Base+0x273a92>
│ │  	beq.n	3dffe8 <uniffi_pbcli_checksum_method_api_base@@Base+0x273764>
│ │  	b.n	3e0474 <uniffi_pbcli_checksum_method_api_base@@Base+0x273bf0>
│ │  	adds	r0, #20
│ │  	b.n	3dfb1c <uniffi_pbcli_checksum_method_api_base@@Base+0x273298>
│ │ @@ -1156273,15 +1156273,15 @@
│ │  	b.n	3dfb00 <uniffi_pbcli_checksum_method_api_base@@Base+0x27327c>
│ │  	adds	r0, #3
│ │  	b.n	3e0108 <uniffi_pbcli_checksum_method_api_base@@Base+0x273884>
│ │  	lsls	r4, r7, #5
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e0332 <uniffi_pbcli_checksum_method_api_base@@Base+0x273aae>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r7, r8, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r5, r7, r8, fp, ip, sp, lr}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e0342 <uniffi_pbcli_checksum_method_api_base@@Base+0x273abe>
│ │  	beq.n	3e0014 <uniffi_pbcli_checksum_method_api_base@@Base+0x273790>
│ │  	b.n	3e04a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x273c1c>
│ │  	adds	r0, #20
│ │  	b.n	3dfb48 <uniffi_pbcli_checksum_method_api_base@@Base+0x2732c4>
│ │ @@ -1156291,15 +1156291,15 @@
│ │  	b.n	3dfb2c <uniffi_pbcli_checksum_method_api_base@@Base+0x2732a8>
│ │  	adds	r0, #3
│ │  	b.n	3e0134 <uniffi_pbcli_checksum_method_api_base@@Base+0x2738b0>
│ │  	lsls	r1, r6, #5
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e035e <uniffi_pbcli_checksum_method_api_base@@Base+0x273ada>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r5, r6, r8, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r4, r7, r8, fp, ip, sp, lr}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e036e <uniffi_pbcli_checksum_method_api_base@@Base+0x273aea>
│ │  	beq.n	3e0040 <uniffi_pbcli_checksum_method_api_base@@Base+0x2737bc>
│ │  	b.n	3e04cc <uniffi_pbcli_checksum_method_api_base@@Base+0x273c48>
│ │  	adds	r0, #20
│ │  	b.n	3dfb74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2732f0>
│ │ @@ -1156309,15 +1156309,15 @@
│ │  	b.n	3dfb58 <uniffi_pbcli_checksum_method_api_base@@Base+0x2732d4>
│ │  	adds	r0, #3
│ │  	b.n	3e0160 <uniffi_pbcli_checksum_method_api_base@@Base+0x2738dc>
│ │  	lsls	r6, r4, #5
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e038a <uniffi_pbcli_checksum_method_api_base@@Base+0x273b06>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r8, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r5, r6, r8, fp, ip, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffcb4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3e0574 <uniffi_pbcli_checksum_method_api_base@@Base+0x273cf0>
│ │  	str	r3, [r0, r0]
│ │  	b.n	3e039e <uniffi_pbcli_checksum_method_api_base@@Base+0x273b1a>
│ │  	strh	r2, [r0, #0]
│ │  	b.n	3e03a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x273b1e>
│ │ @@ -1156397,15 +1156397,15 @@
│ │  	b.n	3e084a <uniffi_pbcli_checksum_method_api_base@@Base+0x273fc6>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3e084e <uniffi_pbcli_checksum_method_api_base@@Base+0x273fca>
│ │  	blt.n	3e00c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x27383e>
│ │  			@ <UNDEFINED> instruction: 0xebfb0006
│ │  	b.n	3e0456 <uniffi_pbcli_checksum_method_api_base@@Base+0x273bd2>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, sl, ip, sp}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r6, sl, ip, sp}
│ │  			@ <UNDEFINED> instruction: 0xffcc6fad
│ │  			@ <UNDEFINED> instruction: 0xffca4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3e0644 <uniffi_pbcli_checksum_method_api_base@@Base+0x273dc0>
│ │  	beq.n	3e0164 <uniffi_pbcli_checksum_method_api_base@@Base+0x2738e0>
│ │  	b.n	3e05c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x273d44>
│ │  	strb	r0, [r0, #0]
│ │ @@ -1156919,26 +1156919,26 @@
│ │  	str	r0, [r0, #0]
│ │  	b.n	3e00b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x273834>
│ │  	asrs	r6, r5, #2
│ │  	b.n	3e0ce2 <uniffi_pbcli_checksum_method_api_base@@Base+0x27445e>
│ │  	movs	r0, #2
│ │  	b.n	3e06c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x273e40>
│ │  			@ <UNDEFINED> instruction: 0xffb6eaff
│ │ -	adds	r1, #55	@ 0x37
│ │ +	adds	r1, #94	@ 0x5e
│ │  			@ <UNDEFINED> instruction: 0xffccddd7
│ │  	vrsra.u64	<illegal reg q13.5>, <illegal reg q9.5>, #55
│ │ -	vshr.u64	<illegal reg q9.5>, <illegal reg q13.5>, #54
│ │ +	vaddw.u8	<illegal reg q9.5>, q5, d18
│ │  			@ <UNDEFINED> instruction: 0xffccdd9b
│ │ -	vsubl.u8	<illegal reg q12.5>, d25, d10
│ │ -	vshr.u64	d19, d31, #53
│ │ +	vrshr.u64	d25, d17, #55
│ │ +	vmla.i<illegal width 8>	<illegal reg q9.5>, <illegal reg q13.5>, d2[5]
│ │  			@ <UNDEFINED> instruction: 0xffccdd5f
│ │  			@ <UNDEFINED> instruction: 0xffc93c10
│ │ -	vsra.u64	d19, d27, #54
│ │ +	vmla.f<illegal width 8>	<illegal reg q9.5>, q13, d2[4]
│ │  			@ <UNDEFINED> instruction: 0xffccde5b
│ │ -			@ <UNDEFINED> instruction: 0xffc92fa3
│ │ +	vqrdmlsh.s<illegal width 8>	q9, <illegal reg q12.5>, d2[2]
│ │  	vqdmulh.s<illegal width 8>	<illegal reg q14.5>, q6, d3[0]
│ │  			@ <UNDEFINED> instruction: 0xffc9dc38
│ │  			@ <UNDEFINED> instruction: 0xffc94df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3e0b04 <uniffi_pbcli_checksum_method_api_base@@Base+0x274280>
│ │  	beq.n	3e05fc <uniffi_pbcli_checksum_method_api_base@@Base+0x273d78>
│ │  	b.n	3e0a88 <uniffi_pbcli_checksum_method_api_base@@Base+0x274204>
│ │ @@ -1157231,27 +1157231,27 @@
│ │  	b.n	3e0980 <uniffi_pbcli_checksum_method_api_base@@Base+0x2740fc>
│ │  	lsls	r1, r0, #6
│ │  	b.n	3e0786 <uniffi_pbcli_checksum_method_api_base@@Base+0x273f02>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3e0fae <uniffi_pbcli_checksum_method_api_base@@Base+0x27472a>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r3, r5, r6, r7, r8, fp, ip}
│ │ +	ldmia.w	sp!, {r4, r9, fp, ip}
│ │  	vabal.u8	<illegal reg q14.5>, d12, d24
│ │  	movs	r6, r1
│ │  	ldr	r2, [pc, #840]	@ (3e0bc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x274340>)
│ │  	vqshlu.s64	d28, d29, #10
│ │  	vrsra.u8	d22, d20, #6
│ │ -			@ <UNDEFINED> instruction: 0xffca5ddc
│ │ +	vmull.p8	<illegal reg q10.5>, d10, d3
│ │  	vrshr.u64	d25, d14, #53
│ │  	vrsra.u8	d19, d16, #6
│ │  	vaddw.u8	<illegal reg q9.5>, q5, d7
│ │ -	vaddw.u8	q15, q5, d15
│ │ +	vsra.u8	d30, d22, #6
│ │  	vshr.u64	d16, d10, #53
│ │ -	vsra.u8	d23, d23, #5
│ │ +	vsra.u8	<illegal reg q11.5>, q7, #5
│ │  			@ <UNDEFINED> instruction: 0xffcb48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3e0dc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x274540>
│ │  	str	r1, [r0, r0]
│ │  	b.n	3e0bee <uniffi_pbcli_checksum_method_api_base@@Base+0x27436a>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	3e0bf2 <uniffi_pbcli_checksum_method_api_base@@Base+0x27436e>
│ │ @@ -1158149,17 +1158149,17 @@
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, lr}
│ │  	b.n	3e17e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x274f5e>
│ │  	movs	r4, r0
│ │  	b.n	3e13e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x274b62>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r4, r9, fp, pc}
│ │ -	vsra.u8	q15, q6, #6
│ │ +	vaddw.u8	q15, q13, d3
│ │  	vmla.f<illegal width 8>	<illegal reg q11.5>, <illegal reg q13.5>, d0[7]
│ │ -	vmla.i<illegal width 8>	q15, <illegal reg q12.5>, d1[4]
│ │ +	vaddw.u8	q15, <illegal reg q4.5>, d8
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3e0bfc <uniffi_pbcli_checksum_method_api_base@@Base+0x274378>
│ │  	movs	r0, r0
│ │  	b.n	3e11e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27495c>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	bcc.n	3e1118 <uniffi_pbcli_checksum_method_api_base@@Base+0x274894>
│ │  	movs	r6, r1
│ │ @@ -1158324,18 +1158324,18 @@
│ │  	and.w	r0, r0, r0, lsl #16
│ │  	b.n	3e196a <uniffi_pbcli_checksum_method_api_base@@Base+0x2750e6>
│ │  	movs	r4, r0
│ │  	b.n	3e156e <uniffi_pbcli_checksum_method_api_base@@Base+0x274cea>
│ │  	beq.n	3e1260 <uniffi_pbcli_checksum_method_api_base@@Base+0x2749dc>
│ │  	b.n	3e16c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x274e44>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r3, r4, r6, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r7, sp, lr, pc}
│ │  	vshr.u64	<illegal reg q11.5>, q10, #53
│ │ -	vmlal.u<illegal width 8>	q15, d25, d1[4]
│ │ -			@ <UNDEFINED> instruction: 0xffcbdf84
│ │ +	vsubw.u8	q15, <illegal reg q4.5>, d8
│ │ +			@ <UNDEFINED> instruction: 0xffcbdfab
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3e0d88 <uniffi_pbcli_checksum_method_api_base@@Base+0x274504>
│ │  	movs	r0, r0
│ │  	b.n	3e136c <uniffi_pbcli_checksum_method_api_base@@Base+0x274ae8>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	bcs.n	3e1254 <uniffi_pbcli_checksum_method_api_base@@Base+0x2749d0>
│ │  	movs	r6, r1
│ │ @@ -1158384,15 +1158384,15 @@
│ │  	b.n	3e0dd8 <uniffi_pbcli_checksum_method_api_base@@Base+0x274554>
│ │  	adds	r0, #3
│ │  	b.n	3e13e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x274b5c>
│ │  	lsls	r7, r2, #14
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e160a <uniffi_pbcli_checksum_method_api_base@@Base+0x274d86>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r6, r9, sl, fp}
│ │ +	ldmia.w	sp!, {r7, r9, sl, fp}
│ │  	vmlal.u8	q10, d12, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e161a <uniffi_pbcli_checksum_method_api_base@@Base+0x274d96>
│ │  	beq.n	3e12ec <uniffi_pbcli_checksum_method_api_base@@Base+0x274a68>
│ │  	b.n	3e1778 <uniffi_pbcli_checksum_method_api_base@@Base+0x274ef4>
│ │  	adds	r0, #20
│ │  	b.n	3e0e20 <uniffi_pbcli_checksum_method_api_base@@Base+0x27459c>
│ │ @@ -1158402,15 +1158402,15 @@
│ │  	b.n	3e0e04 <uniffi_pbcli_checksum_method_api_base@@Base+0x274580>
│ │  	adds	r0, #3
│ │  	b.n	3e140c <uniffi_pbcli_checksum_method_api_base@@Base+0x274b88>
│ │  	lsls	r4, r1, #14
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e1636 <uniffi_pbcli_checksum_method_api_base@@Base+0x274db2>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r5, r9, sl, fp}
│ │ +	ldmia.w	sp!, {r2, r4, r6, r9, sl, fp}
│ │  	vaddl.u8	q8, d12, d0
│ │  	b.n	3e19a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x27511e>
│ │  	movs	r0, r0
│ │  	lsls	r0, r4, #14
│ │  	vrhadd.u16	d0, d14, d31
│ │  	lsls	r0, r2, #5
│ │  	b.n	3e0e2e <uniffi_pbcli_checksum_method_api_base@@Base+0x2745aa>
│ │ @@ -1158502,15 +1158502,15 @@
│ │  	b.n	3e0ee8 <uniffi_pbcli_checksum_method_api_base@@Base+0x274664>
│ │  	adds	r0, #3
│ │  	b.n	3e14f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x274c6c>
│ │  	lsls	r3, r2, #13
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e171a <uniffi_pbcli_checksum_method_api_base@@Base+0x274e96>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r6, r8, sl, fp}
│ │ +	ldmia.w	sp!, {r4, r5, r6, r8, sl, fp}
│ │  	vmlal.u8	q10, d12, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e172a <uniffi_pbcli_checksum_method_api_base@@Base+0x274ea6>
│ │  	beq.n	3e13fc <uniffi_pbcli_checksum_method_api_base@@Base+0x274b78>
│ │  	b.n	3e1888 <uniffi_pbcli_checksum_method_api_base@@Base+0x275004>
│ │  	adds	r0, #20
│ │  	b.n	3e0f30 <uniffi_pbcli_checksum_method_api_base@@Base+0x2746ac>
│ │ @@ -1158520,15 +1158520,15 @@
│ │  	b.n	3e0f14 <uniffi_pbcli_checksum_method_api_base@@Base+0x274690>
│ │  	adds	r0, #3
│ │  	b.n	3e151c <uniffi_pbcli_checksum_method_api_base@@Base+0x274c98>
│ │  	lsls	r0, r1, #13
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e1746 <uniffi_pbcli_checksum_method_api_base@@Base+0x274ec2>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r8, sl, fp}
│ │ +	ldmia.w	sp!, {r2, r6, r8, sl, fp}
│ │  			@ <UNDEFINED> instruction: 0xffcc4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3e1930 <uniffi_pbcli_checksum_method_api_base@@Base+0x2750ac>
│ │  	beq.n	3e14b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x274c34>
│ │  	b.n	3e18b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x275030>
│ │  	ands	r0, r0
│ │  	b.n	3e1b5e <uniffi_pbcli_checksum_method_api_base@@Base+0x2752da>
│ │ @@ -1158692,15 +1158692,15 @@
│ │  	b.n	3e18ba <uniffi_pbcli_checksum_method_api_base@@Base+0x275036>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {r0, ip, lr}
│ │  	b.n	3e1cc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x27543e>
│ │  	movs	r5, r0
│ │  	b.n	3e18c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x275042>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r3, r5, r6, sl, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r4, r7, sl, fp, ip, lr, pc}
│ │  	vsri.8	<illegal reg q15.5>, q0, #5
│ │  			@ <UNDEFINED> instruction: 0xffca999f
│ │  	vaddl.u8	q8, d9, d0
│ │  	b.n	3e1c3a <uniffi_pbcli_checksum_method_api_base@@Base+0x2753b6>
│ │  	movs	r4, r0
│ │  	lsrs	r0, r0, #8
│ │  	movs	r4, r1
│ │ @@ -1158946,15 +1158946,15 @@
│ │  	b.n	3e1300 <uniffi_pbcli_checksum_method_api_base@@Base+0x274a7c>
│ │  	adds	r0, #3
│ │  	b.n	3e1908 <uniffi_pbcli_checksum_method_api_base@@Base+0x275084>
│ │  	lsls	r5, r1, #9
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e1b32 <uniffi_pbcli_checksum_method_api_base@@Base+0x2752ae>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r2, r4, r7, r8, sl, fp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r4, r5, r7, r8, sl, fp, lr}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e1b42 <uniffi_pbcli_checksum_method_api_base@@Base+0x2752be>
│ │  	beq.n	3e1814 <uniffi_pbcli_checksum_method_api_base@@Base+0x274f90>
│ │  	b.n	3e1ca0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27541c>
│ │  	adds	r0, #20
│ │  	b.n	3e1348 <uniffi_pbcli_checksum_method_api_base@@Base+0x274ac4>
│ │ @@ -1158964,15 +1158964,15 @@
│ │  	b.n	3e132c <uniffi_pbcli_checksum_method_api_base@@Base+0x274aa8>
│ │  	adds	r0, #3
│ │  	b.n	3e1934 <uniffi_pbcli_checksum_method_api_base@@Base+0x2750b0>
│ │  	lsls	r2, r0, #9
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e1b5e <uniffi_pbcli_checksum_method_api_base@@Base+0x2752da>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r3, r5, r6, r8, sl, fp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r7, r8, sl, fp, lr}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e1b6e <uniffi_pbcli_checksum_method_api_base@@Base+0x2752ea>
│ │  	beq.n	3e1840 <uniffi_pbcli_checksum_method_api_base@@Base+0x274fbc>
│ │  	b.n	3e1ccc <uniffi_pbcli_checksum_method_api_base@@Base+0x275448>
│ │  	adds	r0, #20
│ │  	b.n	3e1374 <uniffi_pbcli_checksum_method_api_base@@Base+0x274af0>
│ │ @@ -1158982,15 +1158982,15 @@
│ │  	b.n	3e1358 <uniffi_pbcli_checksum_method_api_base@@Base+0x274ad4>
│ │  	adds	r0, #3
│ │  	b.n	3e1960 <uniffi_pbcli_checksum_method_api_base@@Base+0x2750dc>
│ │  	lsls	r7, r6, #8
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e1b8a <uniffi_pbcli_checksum_method_api_base@@Base+0x275306>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r2, r3, r4, r5, r8, sl, fp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r5, r6, r8, sl, fp, lr}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e1b9a <uniffi_pbcli_checksum_method_api_base@@Base+0x275316>
│ │  	beq.n	3e186c <uniffi_pbcli_checksum_method_api_base@@Base+0x274fe8>
│ │  	b.n	3e1cf8 <uniffi_pbcli_checksum_method_api_base@@Base+0x275474>
│ │  	adds	r0, #20
│ │  	b.n	3e13a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x274b1c>
│ │ @@ -1159000,15 +1159000,15 @@
│ │  	b.n	3e1384 <uniffi_pbcli_checksum_method_api_base@@Base+0x274b00>
│ │  	adds	r0, #3
│ │  	b.n	3e198c <uniffi_pbcli_checksum_method_api_base@@Base+0x275108>
│ │  	lsls	r4, r5, #8
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e1bb6 <uniffi_pbcli_checksum_method_api_base@@Base+0x275332>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r4, r8, sl, fp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r4, r5, r8, sl, fp, lr}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e1bc6 <uniffi_pbcli_checksum_method_api_base@@Base+0x275342>
│ │  	beq.n	3e1898 <uniffi_pbcli_checksum_method_api_base@@Base+0x275014>
│ │  	b.n	3e1d24 <uniffi_pbcli_checksum_method_api_base@@Base+0x2754a0>
│ │  	adds	r0, #20
│ │  	b.n	3e13cc <uniffi_pbcli_checksum_method_api_base@@Base+0x274b48>
│ │ @@ -1159090,15 +1159090,15 @@
│ │  	b.n	3e1460 <uniffi_pbcli_checksum_method_api_base@@Base+0x274bdc>
│ │  	adds	r0, #3
│ │  	b.n	3e1a68 <uniffi_pbcli_checksum_method_api_base@@Base+0x2751e4>
│ │  	lsls	r5, r6, #7
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e1c92 <uniffi_pbcli_checksum_method_api_base@@Base+0x27540e>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r6, r7, r8, r9, sl, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, lr, pc}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e1ca2 <uniffi_pbcli_checksum_method_api_base@@Base+0x27541e>
│ │  	beq.n	3e1974 <uniffi_pbcli_checksum_method_api_base@@Base+0x2750f0>
│ │  	b.n	3e1e00 <uniffi_pbcli_checksum_method_api_base@@Base+0x27557c>
│ │  	adds	r0, #20
│ │  	b.n	3e14a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x274c24>
│ │ @@ -1159108,15 +1159108,15 @@
│ │  	b.n	3e148c <uniffi_pbcli_checksum_method_api_base@@Base+0x274c08>
│ │  	adds	r0, #3
│ │  	b.n	3e1a94 <uniffi_pbcli_checksum_method_api_base@@Base+0x275210>
│ │  	lsls	r2, r5, #7
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e1cbe <uniffi_pbcli_checksum_method_api_base@@Base+0x27543a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r5, r7, r8, r9, sl, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r4, r6, r7, r8, r9, sl, fp, lr, pc}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e1cce <uniffi_pbcli_checksum_method_api_base@@Base+0x27544a>
│ │  	beq.n	3e19a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27511c>
│ │  	b.n	3e1e2c <uniffi_pbcli_checksum_method_api_base@@Base+0x2755a8>
│ │  	adds	r0, #20
│ │  	b.n	3e14d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x274c50>
│ │ @@ -1159126,15 +1159126,15 @@
│ │  	b.n	3e14b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x274c34>
│ │  	adds	r0, #3
│ │  	b.n	3e1ac0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27523c>
│ │  	lsls	r7, r3, #7
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e1cea <uniffi_pbcli_checksum_method_api_base@@Base+0x275466>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6, r8, r9, sl, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r5, r7, r8, r9, sl, fp, lr, pc}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e1cfa <uniffi_pbcli_checksum_method_api_base@@Base+0x275476>
│ │  	beq.n	3e19cc <uniffi_pbcli_checksum_method_api_base@@Base+0x275148>
│ │  	b.n	3e1e58 <uniffi_pbcli_checksum_method_api_base@@Base+0x2755d4>
│ │  	adds	r0, #20
│ │  	b.n	3e1500 <uniffi_pbcli_checksum_method_api_base@@Base+0x274c7c>
│ │ @@ -1159144,15 +1159144,15 @@
│ │  	b.n	3e14e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x274c60>
│ │  	adds	r0, #3
│ │  	b.n	3e1aec <uniffi_pbcli_checksum_method_api_base@@Base+0x275268>
│ │  	lsls	r4, r2, #7
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e1d16 <uniffi_pbcli_checksum_method_api_base@@Base+0x275492>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r4, r6, r8, r9, sl, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r4, r5, r6, r8, r9, sl, fp, lr, pc}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e1d26 <uniffi_pbcli_checksum_method_api_base@@Base+0x2754a2>
│ │  	beq.n	3e19f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x275174>
│ │  	b.n	3e1e84 <uniffi_pbcli_checksum_method_api_base@@Base+0x275600>
│ │  	adds	r0, #20
│ │  	b.n	3e152c <uniffi_pbcli_checksum_method_api_base@@Base+0x274ca8>
│ │ @@ -1159234,15 +1159234,15 @@
│ │  	b.n	3e15c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x274d3c>
│ │  	adds	r0, #3
│ │  	b.n	3e1bc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x275344>
│ │  	lsls	r5, r3, #6
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e1df2 <uniffi_pbcli_checksum_method_api_base@@Base+0x27556e>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r6, r7, r9, sl, fp, ip, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r5, r6, r7, r9, sl, fp, ip, lr}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e1e02 <uniffi_pbcli_checksum_method_api_base@@Base+0x27557e>
│ │  	beq.n	3e1ad4 <uniffi_pbcli_checksum_method_api_base@@Base+0x275250>
│ │  	b.n	3e1f60 <uniffi_pbcli_checksum_method_api_base@@Base+0x2756dc>
│ │  	adds	r0, #20
│ │  	b.n	3e1608 <uniffi_pbcli_checksum_method_api_base@@Base+0x274d84>
│ │ @@ -1159252,15 +1159252,15 @@
│ │  	b.n	3e15ec <uniffi_pbcli_checksum_method_api_base@@Base+0x274d68>
│ │  	adds	r0, #3
│ │  	b.n	3e1bf4 <uniffi_pbcli_checksum_method_api_base@@Base+0x275370>
│ │  	lsls	r2, r2, #6
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e1e1e <uniffi_pbcli_checksum_method_api_base@@Base+0x27559a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r5, r7, r9, sl, fp, ip, lr}
│ │ +	ldmia.w	sp!, {r1, r4, r6, r7, r9, sl, fp, ip, lr}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e1e2e <uniffi_pbcli_checksum_method_api_base@@Base+0x2755aa>
│ │  	beq.n	3e1b00 <uniffi_pbcli_checksum_method_api_base@@Base+0x27527c>
│ │  	b.n	3e1f8c <uniffi_pbcli_checksum_method_api_base@@Base+0x275708>
│ │  	adds	r0, #20
│ │  	b.n	3e1634 <uniffi_pbcli_checksum_method_api_base@@Base+0x274db0>
│ │ @@ -1159270,15 +1159270,15 @@
│ │  	b.n	3e1618 <uniffi_pbcli_checksum_method_api_base@@Base+0x274d94>
│ │  	adds	r0, #3
│ │  	b.n	3e1c20 <uniffi_pbcli_checksum_method_api_base@@Base+0x27539c>
│ │  	lsls	r7, r0, #6
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e1e4a <uniffi_pbcli_checksum_method_api_base@@Base+0x2755c6>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6, r9, sl, fp, ip, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r5, r7, r9, sl, fp, ip, lr}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e1e5a <uniffi_pbcli_checksum_method_api_base@@Base+0x2755d6>
│ │  	beq.n	3e1b2c <uniffi_pbcli_checksum_method_api_base@@Base+0x2752a8>
│ │  	b.n	3e1fb8 <uniffi_pbcli_checksum_method_api_base@@Base+0x275734>
│ │  	adds	r0, #20
│ │  	b.n	3e1660 <uniffi_pbcli_checksum_method_api_base@@Base+0x274ddc>
│ │ @@ -1159288,15 +1159288,15 @@
│ │  	b.n	3e1644 <uniffi_pbcli_checksum_method_api_base@@Base+0x274dc0>
│ │  	adds	r0, #3
│ │  	b.n	3e1c4c <uniffi_pbcli_checksum_method_api_base@@Base+0x2753c8>
│ │  	lsls	r4, r7, #5
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e1e76 <uniffi_pbcli_checksum_method_api_base@@Base+0x2755f2>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r4, r6, r9, sl, fp, ip, lr}
│ │ +	ldmia.w	sp!, {r1, r3, r4, r5, r6, r9, sl, fp, ip, lr}
│ │  			@ <UNDEFINED> instruction: 0xffcb4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3e2060 <uniffi_pbcli_checksum_method_api_base@@Base+0x2757dc>
│ │  	str	r3, [r0, r0]
│ │  	b.n	3e1e8a <uniffi_pbcli_checksum_method_api_base@@Base+0x275606>
│ │  	strh	r2, [r0, #0]
│ │  	b.n	3e1e8e <uniffi_pbcli_checksum_method_api_base@@Base+0x27560a>
│ │ @@ -1159377,15 +1159377,15 @@
│ │  	str	r0, [r0, #0]
│ │  	b.n	3e233a <uniffi_pbcli_checksum_method_api_base@@Base+0x275ab6>
│ │  	bpl.n	3e1c38 <uniffi_pbcli_checksum_method_api_base@@Base+0x2753b4>
│ │  			@ <UNDEFINED> instruction: 0xebfb0006
│ │  	b.n	3e1f42 <uniffi_pbcli_checksum_method_api_base@@Base+0x2756be>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, r1, r8, r9, ip, pc}
│ │ -	vsri.8	d22, d30, #7
│ │ +	vmls.i<illegal width 8>	q11, <illegal reg q4.5>, d1[5]
│ │  			@ <UNDEFINED> instruction: 0xffcb4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3e2130 <uniffi_pbcli_checksum_method_api_base@@Base+0x2758ac>
│ │  	beq.n	3e1c48 <uniffi_pbcli_checksum_method_api_base@@Base+0x2753c4>
│ │  	b.n	3e20b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x275830>
│ │  	strb	r0, [r0, #0]
│ │  	b.n	3e1f5e <uniffi_pbcli_checksum_method_api_base@@Base+0x2756da>
│ │ @@ -1159942,15 +1159942,15 @@
│ │  	vaddl.u8	<illegal reg q12.5>, d9, d15
│ │  			@ <UNDEFINED> instruction: 0xffc998f3
│ │  			@ <UNDEFINED> instruction: 0xffca8fab
│ │  			@ <UNDEFINED> instruction: 0xffc98fd7
│ │  	vsri.8	d20, d27, #7
│ │  			@ <UNDEFINED> instruction: 0xffcc8f77
│ │  			@ <UNDEFINED> instruction: 0xffc98fa3
│ │ -	vqshl.u8	<illegal reg q11.5>, q5, #1
│ │ +	vabdl.u8	<illegal reg q11.5>, d25, d1
│ │  	vshr.u8	d25, d3, #5
│ │  	vshr.u8	d25, d31, #7
│ │  			@ <UNDEFINED> instruction: 0xffc98e1b
│ │  	vqrdmlah.s<illegal width 8>	q12, <illegal reg q4.5>, d3[1]
│ │  	vaddw.u8	q14, <illegal reg q4.5>, d0
│ │  			@ <UNDEFINED> instruction: 0xffc94df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │ @@ -1160085,15 +1160085,15 @@
│ │  	add.w	r0, r0, r6, lsl #20
│ │  	b.n	3e258a <uniffi_pbcli_checksum_method_api_base@@Base+0x275d06>
│ │  	movs	r0, r0
│ │  	b.n	3e1d5a <uniffi_pbcli_checksum_method_api_base@@Base+0x2754d6>
│ │  	movs	r5, r0
│ │  	b.n	3e2592 <uniffi_pbcli_checksum_method_api_base@@Base+0x275d0e>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6, r9, fp, sp}
│ │ +	ldmia.w	sp!, {r1, r2, r5, r7, r9, fp, sp}
│ │  	vqshrun.s16	d20, q8, #4
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3e277c <uniffi_pbcli_checksum_method_api_base@@Base+0x275ef8>
│ │  	ands	r2, r0
│ │  	b.n	3e25a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x275d22>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3e25aa <uniffi_pbcli_checksum_method_api_base@@Base+0x275d26>
│ │ @@ -1160400,27 +1160400,27 @@
│ │  	b.n	3e2c3e <uniffi_pbcli_checksum_method_api_base@@Base+0x2763ba>
│ │  	bcs.n	3e24ba <uniffi_pbcli_checksum_method_api_base@@Base+0x275c36>
│ │  			@ <UNDEFINED> instruction: 0xebfb0004
│ │  	b.n	3e2846 <uniffi_pbcli_checksum_method_api_base@@Base+0x275fc2>
│ │  	beq.n	3e2538 <uniffi_pbcli_checksum_method_api_base@@Base+0x275cb4>
│ │  	b.n	3e29a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27611c>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r7, r8, fp, sp}
│ │ -	vqrdmlah.s<illegal width 8>	q14, q6, d0[4]
│ │ -			@ <UNDEFINED> instruction: 0xffcb290f
│ │ -			@ <UNDEFINED> instruction: 0xffcccdd0
│ │ -			@ <UNDEFINED> instruction: 0xffcb8e7d
│ │ -	vqshrun.s16	d18, <illegal reg q3.5>, #5
│ │ -			@ <UNDEFINED> instruction: 0xffccccd8
│ │ -			@ <UNDEFINED> instruction: 0xffcb27ef
│ │ -			@ <UNDEFINED> instruction: 0xffccccb0
│ │ -			@ <UNDEFINED> instruction: 0xffcb27c7
│ │ -	vmull.u8	q14, d28, d8
│ │ -	vqshrn.u16	d18, <illegal reg q13.5>, #5
│ │ -			@ <UNDEFINED> instruction: 0xffcccdfc
│ │ +	ldmia.w	sp!, {r1, r2, r6, r7, r8, fp, sp}
│ │ +	vmull.p8	q14, d28, d7
│ │ +	vqshrn.u16	d18, q11, #5
│ │ +			@ <UNDEFINED> instruction: 0xffcccdf7
│ │ +	vmull.p8	q12, d27, d20
│ │ +	vqshrun.s16	d18, q15, #5
│ │ +			@ <UNDEFINED> instruction: 0xffccccff
│ │ +	vqshrun.s16	d18, q3, #5
│ │ +			@ <UNDEFINED> instruction: 0xffccccd7
│ │ +			@ <UNDEFINED> instruction: 0xffcb27ee
│ │ +	vmull.u8	q14, d28, d31
│ │ +	vmul.f<illegal width 8>	q9, <illegal reg q5.5>, d2[4]
│ │ +	vmull.p8	q14, d12, d19
│ │  			@ <UNDEFINED> instruction: 0xffcb4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3e2a64 <uniffi_pbcli_checksum_method_api_base@@Base+0x2761e0>
│ │  	beq.n	3e260c <uniffi_pbcli_checksum_method_api_base@@Base+0x275d88>
│ │  	b.n	3e29e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x276164>
│ │  	str	r3, [r0, #0]
│ │  	b.n	3e2892 <uniffi_pbcli_checksum_method_api_base@@Base+0x27600e>
│ │ @@ -1160601,21 +1160601,21 @@
│ │  	b.n	3e2e0e <uniffi_pbcli_checksum_method_api_base@@Base+0x27658a>
│ │  	bcs.n	3e27a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x275f1e>
│ │  			@ <UNDEFINED> instruction: 0xebfb0007
│ │  	b.n	3e2a16 <uniffi_pbcli_checksum_method_api_base@@Base+0x276192>
│ │  	beq.n	3e2708 <uniffi_pbcli_checksum_method_api_base@@Base+0x275e84>
│ │  	b.n	3e2b70 <uniffi_pbcli_checksum_method_api_base@@Base+0x2762ec>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r5, r6, sl, fp, pc}
│ │ -	vqshlu.s8	d18, d15, #3
│ │ -			@ <UNDEFINED> instruction: 0xffcc43c5
│ │ -	vsli.64	q9, <illegal reg q11.5>, #11
│ │ -	vrsra.u64	d20, d13, #52
│ │ -	vqshlu.s64	q9, <illegal reg q15.5>, #11
│ │ -	vraddhn.i16	d20, q14, <illegal reg q10.5>
│ │ +	ldmia.w	sp!, {r2, r4, r7, sl, fp, pc}
│ │ +	vmlsl.u<illegal width 8>	q9, d11, d2[1]
│ │ +			@ <UNDEFINED> instruction: 0xffcc43ec
│ │ +	vqshlu.s8	d18, d14, #3
│ │ +			@ <UNDEFINED> instruction: 0xffcc43c4
│ │ +	vabdl.u8	q9, d11, d22
│ │ +	vmls.i<illegal width 8>	q10, q14, d0[3]
│ │  			@ <UNDEFINED> instruction: 0xffcb4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3e2c1c <uniffi_pbcli_checksum_method_api_base@@Base+0x276398>
│ │  	ands	r0, r0
│ │  	b.n	3e2a46 <uniffi_pbcli_checksum_method_api_base@@Base+0x2761c2>
│ │  	movs	r4, r0
│ │  	b.n	3e222a <uniffi_pbcli_checksum_method_api_base@@Base+0x2759a6>
│ │ @@ -1160626,15 +1160626,15 @@
│ │  	b.n	3e2a56 <uniffi_pbcli_checksum_method_api_base@@Base+0x2761d2>
│ │  	movs	r2, #233	@ 0xe9
│ │  	b.n	3e2d1a <uniffi_pbcli_checksum_method_api_base@@Base+0x276496>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3e283c <uniffi_pbcli_checksum_method_api_base@@Base+0x275fb8>
│ │  	ldr	r4, [pc, #64]	@ (3e2760 <uniffi_pbcli_checksum_method_api_base@@Base+0x275edc>)
│ │  	ldmia.w	sp!, {r0, r3, r5, r6, r7, r8, fp, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xeafc258f
│ │ +			@ <UNDEFINED> instruction: 0xeafc25b6
│ │  			@ <UNDEFINED> instruction: 0xffcc4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3e2c4c <uniffi_pbcli_checksum_method_api_base@@Base+0x2763c8>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3e2a76 <uniffi_pbcli_checksum_method_api_base@@Base+0x2761f2>
│ │  	push	{r0, r6}
│ │  			@ <UNDEFINED> instruction: 0xebfe6000
│ │ @@ -1160721,17 +1160721,17 @@
│ │  	b.n	3e2b2e <uniffi_pbcli_checksum_method_api_base@@Base+0x2762aa>
│ │  	movs	r2, #233	@ 0xe9
│ │  	b.n	3e2df2 <uniffi_pbcli_checksum_method_api_base@@Base+0x27656e>
│ │  			@ <UNDEFINED> instruction: 0xe9b5ebfc
│ │  	movs	r6, r0
│ │  	b.n	3e2b3a <uniffi_pbcli_checksum_method_api_base@@Base+0x2762b6>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r6, r8, sl, sp}
│ │ -	vsri.64	q9, <illegal reg q9.5>, #52
│ │ -			@ <UNDEFINED> instruction: 0xffcc2d53
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r5, r6, r8, sl, sp}
│ │ +	vsli.8	d18, d10, #4
│ │ +			@ <UNDEFINED> instruction: 0xffcc2d7a
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3e234c <uniffi_pbcli_checksum_method_api_base@@Base+0x275ac8>
│ │  	movs	r0, r0
│ │  	b.n	3e2930 <uniffi_pbcli_checksum_method_api_base@@Base+0x2760ac>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	stc2	0, cr0, [r8, #-60]	@ 0xffffffc4
│ │  	ldr	r0, [pc, #192]	@ (3e28dc <uniffi_pbcli_checksum_method_api_base@@Base+0x276058>)
│ │ @@ -1160871,15 +1160871,15 @@
│ │  			@ <UNDEFINED> instruction: 0xffd80aff
│ │  	movs	r5, r0
│ │  	b.n	3e2c86 <uniffi_pbcli_checksum_method_api_base@@Base+0x276402>
│ │  	asrs	r4, r0, #32
│ │  	b.n	3e2c8a <uniffi_pbcli_checksum_method_api_base@@Base+0x276406>
│ │  	ldr	r0, [pc, #192]	@ (3e2a0c <uniffi_pbcli_checksum_method_api_base@@Base+0x276188>)
│ │  	ldmia.w	sp!, {r0, r1, r3, r5}
│ │ -	and.w	r3, r0, fp, lsr #10
│ │ +	and.w	r3, r0, r2, lsl #11
│ │  	vqrdmulh.s<illegal width 8>	<illegal reg q15.5>, q6, d1[5]
│ │  			@ <UNDEFINED> instruction: 0xffca2f72
│ │  	vmlal.u8	q10, d10, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e2ca6 <uniffi_pbcli_checksum_method_api_base@@Base+0x276422>
│ │  	stmia	r0!, {r3}
│ │  	b.n	3e24a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x275c1c>
│ │ @@ -1161217,20 +1161217,20 @@
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {sp, lr}
│ │  	b.n	3e338a <uniffi_pbcli_checksum_method_api_base@@Base+0x276b06>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3e2756 <uniffi_pbcli_checksum_method_api_base@@Base+0x275ed2>
│ │  			@ <UNDEFINED> instruction: 0xfff9eaff
│ │  	stc2l	15, cr15, [r8], #-808	@ 0xfffffcd8
│ │ -	movs	r1, #115	@ 0x73
│ │ +	movs	r1, #154	@ 0x9a
│ │  			@ <UNDEFINED> instruction: 0xffcc83e6
│ │ -	vmul.f<illegal width 8>	q9, <illegal reg q12.5>, d0[2]
│ │ -			@ <UNDEFINED> instruction: 0xffcbaf99
│ │ -			@ <UNDEFINED> instruction: 0xffcb2ab4
│ │ -			@ <UNDEFINED> instruction: 0xffcbaf71
│ │ +	vmul.f<illegal width 8>	q9, <illegal reg q12.5>, d3[7]
│ │ +	vqrdmlsh.s<illegal width 8>	q13, <illegal reg q13.5>, d0[0]
│ │ +			@ <UNDEFINED> instruction: 0xffcb2adb
│ │ +			@ <UNDEFINED> instruction: 0xffcbaf98
│ │  			@ <UNDEFINED> instruction: 0xffcbfbcd
│ │  	vqrdmlah.s<illegal width 8>	q14, q13, d3[1]
│ │  	vqrdmlsh.s<illegal width 8>	q14, q5, d2[4]
│ │  	vaddl.u8	q8, d9, d4
│ │  	b.n	3e27bc <uniffi_pbcli_checksum_method_api_base@@Base+0x275f38>
│ │  	movs	r0, r0
│ │  	b.n	3e2da0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27651c>
│ │ @@ -1161651,24 +1161651,24 @@
│ │  	b.n	3e374e <uniffi_pbcli_checksum_method_api_base@@Base+0x276eca>
│ │  	beq.n	3e3042 <uniffi_pbcli_checksum_method_api_base@@Base+0x2767be>
│ │  			@ <UNDEFINED> instruction: 0xebfb0006
│ │  	b.n	3e3356 <uniffi_pbcli_checksum_method_api_base@@Base+0x276ad2>
│ │  	beq.n	3e3050 <uniffi_pbcli_checksum_method_api_base@@Base+0x2767cc>
│ │  	b.n	3e34b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x276c2c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r5, r9, sl, fp, ip}
│ │ -	vqshlu.s64	q8, <illegal reg q4.5>, #12
│ │ -			@ <UNDEFINED> instruction: 0xffcc1da7
│ │ -	vqshlu.s8	q8, <illegal reg q0.5>, #4
│ │ -	vqdmulh.s<illegal width 8>	<illegal reg q8.5>, q14, d3[4]
│ │ -	vabal.u8	q8, d28, d13
│ │ -			@ <UNDEFINED> instruction: 0xffcc1cb7
│ │ -	vmls.f<illegal width 8>	q8, q6, d1[4]
│ │ -			@ <UNDEFINED> instruction: 0xffcc1dd3
│ │ -	vqshlu.s8	q8, <illegal reg q14.5>, #4
│ │ +	ldmia.w	sp!, {r1, r2, r4, r6, r9, sl, fp, ip}
│ │ +	vabdl.u8	q8, d12, d0
│ │ +	vqrdmulh.s<illegal width 8>	<illegal reg q8.5>, q14, d2[3]
│ │ +	vqshlu.s8	q8, q12, #4
│ │ +			@ <UNDEFINED> instruction: 0xffcc1d0a
│ │ +	vsli.64	d16, d20, #12
│ │ +			@ <UNDEFINED> instruction: 0xffcc1cde
│ │ +	vabal.u8	q8, d28, d8
│ │ +			@ <UNDEFINED> instruction: 0xffcc1dfa
│ │ +	vrsubhn.i16	d16, q14, q10
│ │  			@ <UNDEFINED> instruction: 0xffcc4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3e3568 <uniffi_pbcli_checksum_method_api_base@@Base+0x276ce4>
│ │  	beq.n	3e30f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x276874>
│ │  	b.n	3e34ec <uniffi_pbcli_checksum_method_api_base@@Base+0x276c68>
│ │  	str	r3, [r0, #0]
│ │  	b.n	3e3396 <uniffi_pbcli_checksum_method_api_base@@Base+0x276b12>
│ │ @@ -1161812,18 +1161812,18 @@
│ │  	b.n	3e38be <uniffi_pbcli_checksum_method_api_base@@Base+0x27703a>
│ │  	ldmia	r7, {r0, r2, r3, r4, r5, r7}
│ │  			@ <UNDEFINED> instruction: 0xebfb0007
│ │  	b.n	3e34c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x276c42>
│ │  	beq.n	3e31c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27693c>
│ │  	b.n	3e3620 <uniffi_pbcli_checksum_method_api_base@@Base+0x276d9c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r1, r2, r6, r8, r9, fp, ip}
│ │ -			@ <UNDEFINED> instruction: 0xffcc38fc
│ │ -			@ <UNDEFINED> instruction: 0xffcb1bfb
│ │ -			@ <UNDEFINED> instruction: 0xffcc39b0
│ │ +	ldmia.w	sp!, {r1, r2, r3, r5, r6, r8, r9, fp, ip}
│ │ +			@ <UNDEFINED> instruction: 0xffcc3923
│ │ +	vmull.u8	<illegal reg q8.5>, d11, d18
│ │ +			@ <UNDEFINED> instruction: 0xffcc39d7
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3e2ce0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27645c>
│ │  	movs	r0, r0
│ │  	b.n	3e32c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x276a40>
│ │  	vrhadd.u16	d14, d14, d31
│ │  			@ <UNDEFINED> instruction: 0xf37c000f
│ │  	ldr	r0, [pc, #192]	@ (3e3270 <uniffi_pbcli_checksum_method_api_base@@Base+0x2769ec>)
│ │ @@ -1161963,16 +1161963,16 @@
│ │  			@ <UNDEFINED> instruction: 0xffd80aff
│ │  	movs	r5, r0
│ │  	b.n	3e361a <uniffi_pbcli_checksum_method_api_base@@Base+0x276d96>
│ │  	asrs	r4, r0, #32
│ │  	b.n	3e361e <uniffi_pbcli_checksum_method_api_base@@Base+0x276d9a>
│ │  	ldr	r0, [pc, #192]	@ (3e33a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x276b1c>)
│ │  	ldmia.w	sp!, {r1, r2, r6, r7, r8, sl, fp, ip, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xeaff1a07
│ │ -			@ <UNDEFINED> instruction: 0xffccbed5
│ │ +			@ <UNDEFINED> instruction: 0xeaff1a2e
│ │ +			@ <UNDEFINED> instruction: 0xffccbefc
│ │  	vsli.64	q9, q7, #11
│ │  	vmlal.u8	q10, d10, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e363a <uniffi_pbcli_checksum_method_api_base@@Base+0x276db6>
│ │  	stmia	r0!, {r3}
│ │  	b.n	3e2e34 <uniffi_pbcli_checksum_method_api_base@@Base+0x2765b0>
│ │  	b.n	3e3318 <uniffi_pbcli_checksum_method_api_base@@Base+0x276a94>
│ │ @@ -1162290,19 +1162290,19 @@
│ │  			@ <UNDEFINED> instruction: 0xebfb5004
│ │  	b.n	3e30cc <uniffi_pbcli_checksum_method_api_base@@Base+0x276848>
│ │  	movs	r5, r0
│ │  	b.n	3e3902 <uniffi_pbcli_checksum_method_api_base@@Base+0x27707e>
│ │  	beq.n	3e35f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x276d70>
│ │  	b.n	3e3a5c <uniffi_pbcli_checksum_method_api_base@@Base+0x2771d8>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r1, r2, fp, ip}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r5, fp, ip}
│ │  	vrsra.u8	q12, <illegal reg q9.5>, #4
│ │ -	vqshl.u64	<illegal reg q8.5>, <illegal reg q5.5>, #10
│ │ +	vmlal.u8	<illegal reg q8.5>, d10, d2
│ │  			@ <UNDEFINED> instruction: 0xffcc8347
│ │ -	vqshl.u8	d17, d11, #2
│ │ +			@ <UNDEFINED> instruction: 0xffca1742
│ │  	vsubl.u8	q12, d28, d7
│ │  			@ <UNDEFINED> instruction: 0xffca4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3e3b04 <uniffi_pbcli_checksum_method_api_base@@Base+0x277280>
│ │  	strh	r3, [r0, #0]
│ │  	b.n	3e392e <uniffi_pbcli_checksum_method_api_base@@Base+0x2770aa>
│ │  	str	r0, [sp, #8]
│ │ @@ -1162844,15 +1162844,15 @@
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r2, r4, r6, r8, r9, sp, lr}
│ │  	vaddl.u8	q9, d10, d4
│ │  	b.n	3e3620 <uniffi_pbcli_checksum_method_api_base@@Base+0x276d9c>
│ │  	movs	r0, #2
│ │  	b.n	3e3c04 <uniffi_pbcli_checksum_method_api_base@@Base+0x277380>
│ │  	movs	r4, r2
│ │ -	and.w	r8, r0, sp, lsr #9
│ │ +	and.w	r8, r0, r4, lsl #10
│ │  	vqshrun.s16	d20, q8, #5
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3e4010 <uniffi_pbcli_checksum_method_api_base@@Base+0x27778c>
│ │  	movs	r1, r0
│ │  	b.n	3e3e3a <uniffi_pbcli_checksum_method_api_base@@Base+0x2775b6>
│ │  	movs	r1, #220	@ 0xdc
│ │  	add.w	r0, r0, r4, ror #4
│ │ @@ -1162876,15 +1162876,15 @@
│ │  	str	r7, [r4, #64]	@ 0x40
│ │  			@ <UNDEFINED> instruction: 0xebfc0005
│ │  	b.n	3e3e6e <uniffi_pbcli_checksum_method_api_base@@Base+0x2775ea>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3e4276 <uniffi_pbcli_checksum_method_api_base@@Base+0x2779f2>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, fp, sp}
│ │ +	ldmia.w	sp!, {r5, r6, fp, sp}
│ │  			@ <UNDEFINED> instruction: 0xffcb4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3e4060 <uniffi_pbcli_checksum_method_api_base@@Base+0x2777dc>
│ │  	strb	r2, [r0, #0]
│ │  	b.n	3e3e8a <uniffi_pbcli_checksum_method_api_base@@Base+0x277606>
│ │  	str	r1, [r0, #0]
│ │  	b.n	3e3e8e <uniffi_pbcli_checksum_method_api_base@@Base+0x27760a>
│ │ @@ -1163256,15 +1163256,15 @@
│ │  	b.n	3e452a <uniffi_pbcli_checksum_method_api_base@@Base+0x277ca6>
│ │  	ands	r1, r0
│ │  	asrs	r0, r0, #12
│ │  			@ <UNDEFINED> instruction: 0xffb7eaff
│ │  	strb	r3, [r3, #6]
│ │  	vrsra.u8	d16, d15, #7
│ │  	vsra.u8	d23, d31, #6
│ │ -	vqshl.u64	d17, d25, #9
│ │ +			@ <UNDEFINED> instruction: 0xffc917e0
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e41ea <uniffi_pbcli_checksum_method_api_base@@Base+0x277966>
│ │  	beq.n	3e3ebc <uniffi_pbcli_checksum_method_api_base@@Base+0x277638>
│ │  	b.n	3e4348 <uniffi_pbcli_checksum_method_api_base@@Base+0x277ac4>
│ │  	stmia	r0!, {r1}
│ │  	b.n	3e41f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x27796e>
│ │ @@ -1163419,15 +1163419,15 @@
│ │  	asrs	r0, r0, #12
│ │  	movs	r4, r0
│ │  	b.n	3e4346 <uniffi_pbcli_checksum_method_api_base@@Base+0x277ac2>
│ │  	ldrh	r0, [r6, #30]
│ │  	ldmia.w	sp!, {r0, r1, r3, ip, sp, lr}
│ │  	vsri.8	q9, <illegal reg q12.5>, #7
│ │  			@ <UNDEFINED> instruction: 0xffcc6f9b
│ │ -	vqshlu.s8	d17, d5, #1
│ │ +	vqshlu.s8	d17, d28, #1
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e4362 <uniffi_pbcli_checksum_method_api_base@@Base+0x277ade>
│ │  	beq.n	3e4034 <uniffi_pbcli_checksum_method_api_base@@Base+0x2777b0>
│ │  	b.n	3e44c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x277c3c>
│ │  	stmia	r0!, {r1}
│ │  	b.n	3e436a <uniffi_pbcli_checksum_method_api_base@@Base+0x277ae6>
│ │ @@ -1163879,15 +1163879,15 @@
│ │  	adds	r0, #16
│ │  	b.n	3e3fae <uniffi_pbcli_checksum_method_api_base@@Base+0x27772a>
│ │  	movs	r4, r1
│ │  	b.n	3e4772 <uniffi_pbcli_checksum_method_api_base@@Base+0x277eee>
│ │  	ldr	r0, [pc, #0]	@ (3e4434 <uniffi_pbcli_checksum_method_api_base@@Base+0x277bb0>)
│ │  	ldmia.w	sp!, {r1, r2, r6, r7, fp, ip, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeafb6b33
│ │ -	vaddw.u8	<illegal reg q8.5>, <illegal reg q12.5>, d29
│ │ +	vsra.u64	<illegal reg q8.5>, q2, #55
│ │  	vqshrun.s16	d20, q8, #5
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3e4964 <uniffi_pbcli_checksum_method_api_base@@Base+0x2780e0>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3e478e <uniffi_pbcli_checksum_method_api_base@@Base+0x277f0a>
│ │  	movs	r0, r0
│ │  	b.n	3e4b92 <uniffi_pbcli_checksum_method_api_base@@Base+0x27830e>
│ │ @@ -1164004,15 +1164004,15 @@
│ │  	adds	r0, #16
│ │  	b.n	3e40ca <uniffi_pbcli_checksum_method_api_base@@Base+0x277846>
│ │  	movs	r4, r1
│ │  	b.n	3e488e <uniffi_pbcli_checksum_method_api_base@@Base+0x27800a>
│ │  	ldr	r0, [pc, #0]	@ (3e4550 <uniffi_pbcli_checksum_method_api_base@@Base+0x277ccc>)
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6, fp, ip, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeafb6a17
│ │ -	vshr.u64	d17, d1, #55
│ │ +	vshr.u64	d17, d24, #55
│ │  			@ <UNDEFINED> instruction: 0xffcb4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3e4a80 <uniffi_pbcli_checksum_method_api_base@@Base+0x2781fc>
│ │  	ands	r0, r0
│ │  	b.n	3e48aa <uniffi_pbcli_checksum_method_api_base@@Base+0x278026>
│ │  	movs	r0, r0
│ │  	b.n	3e4cae <uniffi_pbcli_checksum_method_api_base@@Base+0x27842a>
│ │ @@ -1164911,39 +1164911,39 @@
│ │  	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, ip, lr}
│ │  	vrsubhn.i16	d22, q5, <illegal reg q5.5>
│ │  			@ <UNDEFINED> instruction: 0xffc96f01
│ │  	vmls.f<illegal width 8>	q11, q5, d3[2]
│ │  	vqrdmlah.s<illegal width 8>	q11, <illegal reg q4.5>, d1[0]
│ │  			@ <UNDEFINED> instruction: 0xffcadc9f
│ │  	vmlal.u<illegal width 8>	q11, d10, d3[0]
│ │ -			@ <UNDEFINED> instruction: 0xffc9bb52
│ │ +			@ <UNDEFINED> instruction: 0xffc9bb79
│ │  	vsubl.u8	q11, d11, d23
│ │ -			@ <UNDEFINED> instruction: 0xffc9bb36
│ │ +			@ <UNDEFINED> instruction: 0xffc9bb5d
│ │  	vraddhn.i16	d22, <illegal reg q13.5>, <illegal reg q15.5>
│ │ -			@ <UNDEFINED> instruction: 0xffc9bdbe
│ │ +	vqrdmulh.s<illegal width 8>	<illegal reg q13.5>, <illegal reg q12.5>, d1[5]
│ │  	vsri.64	q11, <illegal reg q3.5>, #53
│ │ -	vqrdmulh.s<illegal width 8>	<illegal reg q13.5>, <illegal reg q12.5>, d2[5]
│ │ +	vmull.p8	<illegal reg q13.5>, d9, d13
│ │  	vsubw.u8	q11, <illegal reg q5.5>, d19
│ │ -			@ <UNDEFINED> instruction: 0xffc9bc32
│ │ +			@ <UNDEFINED> instruction: 0xffc9bc59
│ │  	vrsra.u8	q11, <illegal reg q7.5>, #5
│ │ -	vqdmulh.s<illegal width 8>	<illegal reg q13.5>, <illegal reg q4.5>, d2[7]
│ │ -			@ <UNDEFINED> instruction: 0xffcb098d
│ │ +			@ <UNDEFINED> instruction: 0xffc9bc95
│ │ +			@ <UNDEFINED> instruction: 0xffcb09b4
│ │  	vrshr.u64	d22, d7, #53
│ │  			@ <UNDEFINED> instruction: 0xffc96b8d
│ │  	vsli.64	d22, d7, #10
│ │  	vmull.p8	q11, d25, d13
│ │  	vmlal.u8	<illegal reg q12.5>, d26, d2
│ │  	vmlal.u<illegal width 8>	<illegal reg q14.5>, d9, d2[3]
│ │  	vabdl.u8	<illegal reg q15.5>, d9, d12
│ │  	vmul.i16	q13, q0, d4[0]
│ │  	movs	r6, r1
│ │  	str	r7, [r7, #96]	@ 0x60
│ │ -			@ <UNDEFINED> instruction: 0xffc91fd7
│ │ +			@ <UNDEFINED> instruction: 0xffc91ffe
│ │  	vqshl.u8	<illegal reg q9.5>, q4, #3
│ │ -			@ <UNDEFINED> instruction: 0xffc90afa
│ │ +			@ <UNDEFINED> instruction: 0xffc90b21
│ │  	vabdl.u8	q10, d12, d17
│ │  	vmull.u8	<illegal reg q9.5>, d10, d22
│ │  	vmul.f<illegal width 8>	q13, <illegal reg q4.5>, d0[1]
│ │  	movs	r6, r1
│ │  	movs	r4, r0
│ │  	b.n	3e4908 <uniffi_pbcli_checksum_method_api_base@@Base+0x278084>
│ │  	movs	r0, r0
│ │ @@ -1165698,55 +1165698,55 @@
│ │  	lsls	r3, r1, #23
│ │  	add.w	r0, r0, r0
│ │  	b.n	3e5afe <uniffi_pbcli_checksum_method_api_base@@Base+0x27927a>
│ │  	ands	r1, r0
│ │  	asrs	r0, r4, #14
│ │  	mrc2	10, 5, lr, cr0, cr15, {7}	@ <UNPREDICTABLE>
│ │  	adds	r3, #164	@ 0xa4
│ │ -	vmls.f<illegal width 8>	q13, <illegal reg q12.5>, d1[1]
│ │ +	vmls.f<illegal width 8>	q13, <illegal reg q12.5>, d0[7]
│ │  	vmull.u8	q14, d11, d2
│ │ -	vsli.8	q9, q1, #1
│ │ +	vsli.8	q9, <illegal reg q12.5>, #1
│ │  	vrsra.u8	d26, d12, #5
│ │  	movs	r6, r1
│ │  	lsrs	r1, r7, #4
│ │ -	vmls.f<illegal width 8>	q15, q5, d0[7]
│ │ +	vsli.64	d30, d3, #10
│ │  	vqshrn.u16	d28, <illegal reg q3.5>, #5
│ │ -			@ <UNDEFINED> instruction: 0xffc9efb9
│ │ -			@ <UNDEFINED> instruction: 0xffcbefa6
│ │ +	vqrdmlsh.s<illegal width 8>	q15, <illegal reg q12.5>, d0[4]
│ │ +	vqrdmlsh.s<illegal width 8>	q15, <illegal reg q13.5>, d1[3]
│ │  			@ <UNDEFINED> instruction: 0xffcbee53
│ │  			@ <UNDEFINED> instruction: 0xffcaab67
│ │  	vqrshrun.s16	d19, <illegal reg q15.5>, #7
│ │  			@ <UNDEFINED> instruction: 0xffca5eb7
│ │ -			@ <UNDEFINED> instruction: 0xffc9fc57
│ │ +			@ <UNDEFINED> instruction: 0xffc9fc7e
│ │  			@ <UNDEFINED> instruction: 0xffcb5f03
│ │ -	vmull.u8	<illegal reg q15.5>, d25, d19
│ │ +	vqdmulh.s<illegal width 8>	<illegal reg q15.5>, <illegal reg q12.5>, d2[2]
│ │  	vsra.u8	q10, <illegal reg q14.5>, #5
│ │  	vmull.p8	<illegal reg q10.5>, d10, d23
│ │ -			@ <UNDEFINED> instruction: 0xffc9fbc7
│ │ +			@ <UNDEFINED> instruction: 0xffc9fbee
│ │  	vqshl.u8	d20, d8, #3
│ │  	vmla.i<illegal width 8>	<illegal reg q9.5>, <illegal reg q12.5>, d0[4]
│ │  	vqrdmulh.s<illegal width 8>	q10, <illegal reg q12.5>, d0[5]
│ │  			@ <UNDEFINED> instruction: 0xffc9dbf2
│ │  	vqrdmlsh.s<illegal width 8>	<illegal reg q13.5>, <illegal reg q12.5>, d3[4]
│ │  	vqdmulh.s<illegal width 8>	<illegal reg q10.5>, <illegal reg q12.5>, d3[7]
│ │ -	vmlsl.u8	<illegal reg q15.5>, d25, d15
│ │ -	vqshrun.s16	d17, <illegal reg q0.5>, #5
│ │ +			@ <UNDEFINED> instruction: 0xffc9fab6
│ │ +	vqshrun.s16	d17, q12, #5
│ │  			@ <UNDEFINED> instruction: 0xffcb5d7b
│ │ -			@ <UNDEFINED> instruction: 0xffc9fb1b
│ │ +			@ <UNDEFINED> instruction: 0xffc9fb42
│ │  	vmull.u8	<illegal reg q10.5>, d27, d27
│ │ -	vmull.u<illegal width 8>	<illegal reg q15.5>, d9, d3[2]
│ │ +			@ <UNDEFINED> instruction: 0xffc9fa72
│ │  	vqdmulh.s<illegal width 8>	<illegal reg q10.5>, <illegal reg q13.5>, d3[0]
│ │  			@ <UNDEFINED> instruction: 0xffc95c53
│ │ -			@ <UNDEFINED> instruction: 0xffc9f9f3
│ │ -	vshr.u64	<illegal reg q11.5>, <illegal reg q6.5>, #53
│ │ -	vmlal.u<illegal width 8>	q8, d27, d2[2]
│ │ -			@ <UNDEFINED> instruction: 0xffcccd1d
│ │ +	vshll.u8	<illegal reg q15.5>, d10, #1
│ │ +	vaddw.u8	<illegal reg q11.5>, <illegal reg q5.5>, d4
│ │ +	vrshr.u64	q8, <illegal reg q8.5>, #53
│ │ +	vqrdmulh.s<illegal width 8>	q14, q6, d0[1]
│ │  			@ <UNDEFINED> instruction: 0xffcbbbaf
│ │  			@ <UNDEFINED> instruction: 0xffca5b8b
│ │ -			@ <UNDEFINED> instruction: 0xffc9f92b
│ │ +	vqrshrn.u16	d31, q1, #7
│ │  	vaddl.u8	q8, d11, d0
│ │  	b.n	3e5bae <uniffi_pbcli_checksum_method_api_base@@Base+0x27932a>
│ │  	movs	r4, r0
│ │  	lsrs	r0, r0, #8
│ │  	movs	r0, r2
│ │  	b.n	3e50b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x278832>
│ │  	movs	r2, r0
│ │ @@ -1165810,15 +1165810,15 @@
│ │  	b.n	3e50bc <uniffi_pbcli_checksum_method_api_base@@Base+0x278838>
│ │  	adds	r0, #3
│ │  	b.n	3e56c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x278e40>
│ │  	lsrs	r6, r4, #1
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e58ee <uniffi_pbcli_checksum_method_api_base@@Base+0x27906a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r3, r5, r6, r8, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r7, r8, fp, ip, sp, lr}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e58fe <uniffi_pbcli_checksum_method_api_base@@Base+0x27907a>
│ │  	beq.n	3e55d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x278d4c>
│ │  	b.n	3e5a5c <uniffi_pbcli_checksum_method_api_base@@Base+0x2791d8>
│ │  	adds	r0, #20
│ │  	b.n	3e5104 <uniffi_pbcli_checksum_method_api_base@@Base+0x278880>
│ │ @@ -1165828,15 +1165828,15 @@
│ │  	b.n	3e50e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x278864>
│ │  	adds	r0, #3
│ │  	b.n	3e56f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x278e6c>
│ │  	lsrs	r3, r3, #1
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e591a <uniffi_pbcli_checksum_method_api_base@@Base+0x279096>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r2, r3, r4, r5, r8, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r5, r6, r8, fp, ip, sp, lr}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e592a <uniffi_pbcli_checksum_method_api_base@@Base+0x2790a6>
│ │  	movs	r0, r0
│ │  	b.n	3e5c8e <uniffi_pbcli_checksum_method_api_base@@Base+0x27940a>
│ │  	b.n	3e5620 <uniffi_pbcli_checksum_method_api_base@@Base+0x278d9c>
│ │  	asrs	r0, r2, #22
│ │ @@ -1165880,15 +1165880,15 @@
│ │  	adds	r0, #16
│ │  	b.n	3e51ca <uniffi_pbcli_checksum_method_api_base@@Base+0x278946>
│ │  	movs	r6, r1
│ │  	b.n	3e598e <uniffi_pbcli_checksum_method_api_base@@Base+0x27910a>
│ │  	ldr	r0, [pc, #0]	@ (3e5650 <uniffi_pbcli_checksum_method_api_base@@Base+0x278dcc>)
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, sl, ip, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xeafb5917
│ │ -			@ <UNDEFINED> instruction: 0xffc9ff91
│ │ +			@ <UNDEFINED> instruction: 0xffc9ffb8
│ │  			@ <UNDEFINED> instruction: 0xffca4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3e5b80 <uniffi_pbcli_checksum_method_api_base@@Base+0x2792fc>
│ │  	beq.n	3e5708 <uniffi_pbcli_checksum_method_api_base@@Base+0x278e84>
│ │  	b.n	3e5b04 <uniffi_pbcli_checksum_method_api_base@@Base+0x279280>
│ │  	ands	r0, r0
│ │  	b.n	3e5dae <uniffi_pbcli_checksum_method_api_base@@Base+0x27952a>
│ │ @@ -1166008,15 +1166008,15 @@
│ │  	b.n	3e5288 <uniffi_pbcli_checksum_method_api_base@@Base+0x278a04>
│ │  	adds	r0, #3
│ │  	b.n	3e5890 <uniffi_pbcli_checksum_method_api_base@@Base+0x27900c>
│ │  	lsls	r3, r6, #31
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e5aba <uniffi_pbcli_checksum_method_api_base@@Base+0x279236>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r2, r3, r4, r7, r8, r9, sl, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r6, r7, r8, r9, sl, ip, sp, lr}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e5aca <uniffi_pbcli_checksum_method_api_base@@Base+0x279246>
│ │  	beq.n	3e579c <uniffi_pbcli_checksum_method_api_base@@Base+0x278f18>
│ │  	b.n	3e5c28 <uniffi_pbcli_checksum_method_api_base@@Base+0x2793a4>
│ │  	adds	r0, #20
│ │  	b.n	3e52d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x278a4c>
│ │ @@ -1166026,15 +1166026,15 @@
│ │  	b.n	3e52b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x278a30>
│ │  	adds	r0, #3
│ │  	b.n	3e58bc <uniffi_pbcli_checksum_method_api_base@@Base+0x279038>
│ │  	lsls	r0, r5, #31
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e5ae6 <uniffi_pbcli_checksum_method_api_base@@Base+0x279262>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r4, r5, r6, r8, r9, sl, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r4, r7, r8, r9, sl, ip, sp, lr}
│ │  	vqshrun.s16	d20, q8, #5
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3e5cd0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27944c>
│ │  	beq.n	3e5848 <uniffi_pbcli_checksum_method_api_base@@Base+0x278fc4>
│ │  	b.n	3e5c54 <uniffi_pbcli_checksum_method_api_base@@Base+0x2793d0>
│ │  	ands	r0, r0
│ │  	b.n	3e5efe <uniffi_pbcli_checksum_method_api_base@@Base+0x27967a>
│ │ @@ -1166115,15 +1166115,15 @@
│ │  	adds	r0, #8
│ │  	b.n	3e5d80 <uniffi_pbcli_checksum_method_api_base@@Base+0x2794fc>
│ │  	lsls	r7, r4, #26
│ │  	add.w	r0, r0, r0, lsl #16
│ │  	b.n	3e5bae <uniffi_pbcli_checksum_method_api_base@@Base+0x27932a>
│ │  			@ <UNDEFINED> instruction: 0xffdbeaff
│ │  	ldrsb	r3, [r5, r4]
│ │ -	vsubl.u8	<illegal reg q8.5>, d25, d5
│ │ +	vsubl.u8	<illegal reg q8.5>, d25, d28
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e5bc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x27933e>
│ │  	beq.n	3e5894 <uniffi_pbcli_checksum_method_api_base@@Base+0x279010>
│ │  	b.n	3e5d20 <uniffi_pbcli_checksum_method_api_base@@Base+0x27949c>
│ │  	adds	r0, #20
│ │  	b.n	3e53c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x278b44>
│ │ @@ -1166133,15 +1166133,15 @@
│ │  	b.n	3e53ac <uniffi_pbcli_checksum_method_api_base@@Base+0x278b28>
│ │  	adds	r0, #3
│ │  	b.n	3e59b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x279130>
│ │  	lsls	r2, r5, #30
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e5bde <uniffi_pbcli_checksum_method_api_base@@Base+0x27935a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r3, r4, r5, r6, r9, sl, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r4, r7, r9, sl, ip, sp, lr}
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3e53e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x278b64>
│ │  	movs	r0, r0
│ │  	b.n	3e59cc <uniffi_pbcli_checksum_method_api_base@@Base+0x279148>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldmia	r4, {r2, r3, r4, r5, r6}
│ │  	movs	r7, r1
│ │ @@ -1166252,15 +1166252,15 @@
│ │  	b.n	3e54b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x278c34>
│ │  	adds	r0, #3
│ │  	b.n	3e5ac0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27923c>
│ │  	lsls	r7, r4, #29
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e5cea <uniffi_pbcli_checksum_method_api_base@@Base+0x279466>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r6, r8, r9, sl, lr, pc}
│ │ +	ldmia.w	sp!, {r5, r7, r8, r9, sl, lr, pc}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e5cfa <uniffi_pbcli_checksum_method_api_base@@Base+0x279476>
│ │  	beq.n	3e59cc <uniffi_pbcli_checksum_method_api_base@@Base+0x279148>
│ │  	b.n	3e5e58 <uniffi_pbcli_checksum_method_api_base@@Base+0x2795d4>
│ │  	adds	r0, #20
│ │  	b.n	3e5500 <uniffi_pbcli_checksum_method_api_base@@Base+0x278c7c>
│ │ @@ -1166270,15 +1166270,15 @@
│ │  	b.n	3e54e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x278c60>
│ │  	adds	r0, #3
│ │  	b.n	3e5aec <uniffi_pbcli_checksum_method_api_base@@Base+0x279268>
│ │  	lsls	r4, r3, #29
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e5d16 <uniffi_pbcli_checksum_method_api_base@@Base+0x279492>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r6, r8, r9, sl, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r4, r5, r6, r8, r9, sl, lr, pc}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e5d26 <uniffi_pbcli_checksum_method_api_base@@Base+0x2794a2>
│ │  	beq.n	3e59f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x279174>
│ │  	b.n	3e5e84 <uniffi_pbcli_checksum_method_api_base@@Base+0x279600>
│ │  	adds	r0, #20
│ │  	b.n	3e552c <uniffi_pbcli_checksum_method_api_base@@Base+0x278ca8>
│ │ @@ -1166288,15 +1166288,15 @@
│ │  	b.n	3e5510 <uniffi_pbcli_checksum_method_api_base@@Base+0x278c8c>
│ │  	adds	r0, #3
│ │  	b.n	3e5b18 <uniffi_pbcli_checksum_method_api_base@@Base+0x279294>
│ │  	lsls	r1, r2, #29
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e5d42 <uniffi_pbcli_checksum_method_api_base@@Base+0x2794be>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r5, r8, r9, sl, lr, pc}
│ │ +	ldmia.w	sp!, {r3, r6, r8, r9, sl, lr, pc}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e5d52 <uniffi_pbcli_checksum_method_api_base@@Base+0x2794ce>
│ │  	beq.n	3e5a24 <uniffi_pbcli_checksum_method_api_base@@Base+0x2791a0>
│ │  	b.n	3e5eb0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27962c>
│ │  	adds	r0, #20
│ │  	b.n	3e5558 <uniffi_pbcli_checksum_method_api_base@@Base+0x278cd4>
│ │ @@ -1166306,15 +1166306,15 @@
│ │  	b.n	3e553c <uniffi_pbcli_checksum_method_api_base@@Base+0x278cb8>
│ │  	adds	r0, #3
│ │  	b.n	3e5b44 <uniffi_pbcli_checksum_method_api_base@@Base+0x2792c0>
│ │  	lsls	r6, r0, #29
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e5d6e <uniffi_pbcli_checksum_method_api_base@@Base+0x2794ea>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r6, r7, r9, sl, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r8, r9, sl, lr, pc}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e5d7e <uniffi_pbcli_checksum_method_api_base@@Base+0x2794fa>
│ │  	beq.n	3e5a50 <uniffi_pbcli_checksum_method_api_base@@Base+0x2791cc>
│ │  	b.n	3e5edc <uniffi_pbcli_checksum_method_api_base@@Base+0x279658>
│ │  	adds	r0, #20
│ │  	b.n	3e5584 <uniffi_pbcli_checksum_method_api_base@@Base+0x278d00>
│ │ @@ -1166324,15 +1166324,15 @@
│ │  	b.n	3e5568 <uniffi_pbcli_checksum_method_api_base@@Base+0x278ce4>
│ │  	adds	r0, #3
│ │  	b.n	3e5b70 <uniffi_pbcli_checksum_method_api_base@@Base+0x2792ec>
│ │  	lsls	r3, r7, #28
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e5d9a <uniffi_pbcli_checksum_method_api_base@@Base+0x279516>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r6, r7, r9, sl, lr, pc}
│ │ +	ldmia.w	sp!, {r4, r5, r6, r7, r9, sl, lr, pc}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e5daa <uniffi_pbcli_checksum_method_api_base@@Base+0x279526>
│ │  	beq.n	3e5a7c <uniffi_pbcli_checksum_method_api_base@@Base+0x2791f8>
│ │  	b.n	3e5f08 <uniffi_pbcli_checksum_method_api_base@@Base+0x279684>
│ │  	adds	r0, #20
│ │  	b.n	3e55b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x278d2c>
│ │ @@ -1166612,15 +1166612,15 @@
│ │  	b.n	3e5828 <uniffi_pbcli_checksum_method_api_base@@Base+0x278fa4>
│ │  	adds	r0, #3
│ │  	b.n	3e5e30 <uniffi_pbcli_checksum_method_api_base@@Base+0x2795ac>
│ │  	lsls	r3, r1, #26
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e605a <uniffi_pbcli_checksum_method_api_base@@Base+0x2797d6>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r2, r3, r5, r6, fp}
│ │ +	ldmia.w	sp!, {r0, r1, r4, r7, fp}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e606a <uniffi_pbcli_checksum_method_api_base@@Base+0x2797e6>
│ │  	beq.n	3e5d3c <uniffi_pbcli_checksum_method_api_base@@Base+0x2794b8>
│ │  	b.n	3e61c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x279944>
│ │  	adds	r0, #20
│ │  	b.n	3e5870 <uniffi_pbcli_checksum_method_api_base@@Base+0x278fec>
│ │ @@ -1166630,15 +1166630,15 @@
│ │  	b.n	3e5854 <uniffi_pbcli_checksum_method_api_base@@Base+0x278fd0>
│ │  	adds	r0, #3
│ │  	b.n	3e5e5c <uniffi_pbcli_checksum_method_api_base@@Base+0x2795d8>
│ │  	lsls	r0, r0, #26
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e6086 <uniffi_pbcli_checksum_method_api_base@@Base+0x279802>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r6, fp}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r5, r6, fp}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e6096 <uniffi_pbcli_checksum_method_api_base@@Base+0x279812>
│ │  	beq.n	3e5d68 <uniffi_pbcli_checksum_method_api_base@@Base+0x2794e4>
│ │  	b.n	3e61f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x279970>
│ │  	adds	r0, #20
│ │  	b.n	3e589c <uniffi_pbcli_checksum_method_api_base@@Base+0x279018>
│ │ @@ -1166648,15 +1166648,15 @@
│ │  	b.n	3e5880 <uniffi_pbcli_checksum_method_api_base@@Base+0x278ffc>
│ │  	adds	r0, #3
│ │  	b.n	3e5e88 <uniffi_pbcli_checksum_method_api_base@@Base+0x279604>
│ │  	lsls	r5, r6, #25
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e60b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x27982e>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r2, r4, fp}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r4, r5, fp}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e60c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x27983e>
│ │  	beq.n	3e5d94 <uniffi_pbcli_checksum_method_api_base@@Base+0x279510>
│ │  	b.n	3e6220 <uniffi_pbcli_checksum_method_api_base@@Base+0x27999c>
│ │  	adds	r0, #20
│ │  	b.n	3e58c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x279044>
│ │ @@ -1166666,15 +1166666,15 @@
│ │  	b.n	3e58ac <uniffi_pbcli_checksum_method_api_base@@Base+0x279028>
│ │  	adds	r0, #3
│ │  	b.n	3e5eb4 <uniffi_pbcli_checksum_method_api_base@@Base+0x279630>
│ │  	lsls	r2, r5, #25
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e60de <uniffi_pbcli_checksum_method_api_base@@Base+0x27985a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r3, r5, r6, r7, r8, r9, sl}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, fp}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e60ee <uniffi_pbcli_checksum_method_api_base@@Base+0x27986a>
│ │  	beq.n	3e5dc0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27953c>
│ │  	b.n	3e624c <uniffi_pbcli_checksum_method_api_base@@Base+0x2799c8>
│ │  	adds	r0, #20
│ │  	b.n	3e58f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x279070>
│ │ @@ -1166684,15 +1166684,15 @@
│ │  	b.n	3e58d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x279054>
│ │  	adds	r0, #3
│ │  	b.n	3e5ee0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27965c>
│ │  	lsls	r7, r3, #25
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e610a <uniffi_pbcli_checksum_method_api_base@@Base+0x279886>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r2, r3, r4, r5, r7, r8, r9, sl}
│ │ +	ldmia.w	sp!, {r0, r1, r5, r6, r7, r8, r9, sl}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e611a <uniffi_pbcli_checksum_method_api_base@@Base+0x279896>
│ │  	beq.n	3e5dec <uniffi_pbcli_checksum_method_api_base@@Base+0x279568>
│ │  	b.n	3e6278 <uniffi_pbcli_checksum_method_api_base@@Base+0x2799f4>
│ │  	adds	r0, #20
│ │  	b.n	3e5920 <uniffi_pbcli_checksum_method_api_base@@Base+0x27909c>
│ │ @@ -1166972,15 +1166972,15 @@
│ │  	b.n	3e5b98 <uniffi_pbcli_checksum_method_api_base@@Base+0x279314>
│ │  	adds	r0, #3
│ │  	b.n	3e61a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27991c>
│ │  	lsls	r7, r5, #22
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e63ca <uniffi_pbcli_checksum_method_api_base@@Base+0x279b46>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r4, r7, fp, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r6, r7, fp, pc}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e63da <uniffi_pbcli_checksum_method_api_base@@Base+0x279b56>
│ │  	beq.n	3e60ac <uniffi_pbcli_checksum_method_api_base@@Base+0x279828>
│ │  	b.n	3e6538 <uniffi_pbcli_checksum_method_api_base@@Base+0x279cb4>
│ │  	adds	r0, #20
│ │  	b.n	3e5be0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27935c>
│ │ @@ -1166990,15 +1166990,15 @@
│ │  	b.n	3e5bc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x279340>
│ │  	adds	r0, #3
│ │  	b.n	3e61cc <uniffi_pbcli_checksum_method_api_base@@Base+0x279948>
│ │  	lsls	r4, r4, #22
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e63f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x279b72>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r4, r5, r6, fp, pc}
│ │ +	ldmia.w	sp!, {r1, r3, r4, r7, fp, pc}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e6406 <uniffi_pbcli_checksum_method_api_base@@Base+0x279b82>
│ │  	beq.n	3e60d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x279854>
│ │  	b.n	3e6564 <uniffi_pbcli_checksum_method_api_base@@Base+0x279ce0>
│ │  	adds	r0, #20
│ │  	b.n	3e5c0c <uniffi_pbcli_checksum_method_api_base@@Base+0x279388>
│ │ @@ -1167008,15 +1167008,15 @@
│ │  	b.n	3e5bf0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27936c>
│ │  	adds	r0, #3
│ │  	b.n	3e61f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x279974>
│ │  	lsls	r1, r3, #22
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e6422 <uniffi_pbcli_checksum_method_api_base@@Base+0x279b9e>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r6, fp, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r5, r6, fp, pc}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e6432 <uniffi_pbcli_checksum_method_api_base@@Base+0x279bae>
│ │  	beq.n	3e6104 <uniffi_pbcli_checksum_method_api_base@@Base+0x279880>
│ │  	b.n	3e6590 <uniffi_pbcli_checksum_method_api_base@@Base+0x279d0c>
│ │  	adds	r0, #20
│ │  	b.n	3e5c38 <uniffi_pbcli_checksum_method_api_base@@Base+0x2793b4>
│ │ @@ -1167026,15 +1167026,15 @@
│ │  	b.n	3e5c1c <uniffi_pbcli_checksum_method_api_base@@Base+0x279398>
│ │  	adds	r0, #3
│ │  	b.n	3e6224 <uniffi_pbcli_checksum_method_api_base@@Base+0x2799a0>
│ │  	lsls	r6, r1, #22
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e644e <uniffi_pbcli_checksum_method_api_base@@Base+0x279bca>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, fp, pc}
│ │ +	ldmia.w	sp!, {r1, r6, fp, pc}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e645e <uniffi_pbcli_checksum_method_api_base@@Base+0x279bda>
│ │  	beq.n	3e6130 <uniffi_pbcli_checksum_method_api_base@@Base+0x2798ac>
│ │  	b.n	3e65bc <uniffi_pbcli_checksum_method_api_base@@Base+0x279d38>
│ │  	adds	r0, #20
│ │  	b.n	3e5c64 <uniffi_pbcli_checksum_method_api_base@@Base+0x2793e0>
│ │ @@ -1167044,15 +1167044,15 @@
│ │  	b.n	3e5c48 <uniffi_pbcli_checksum_method_api_base@@Base+0x2793c4>
│ │  	adds	r0, #3
│ │  	b.n	3e6250 <uniffi_pbcli_checksum_method_api_base@@Base+0x2799cc>
│ │  	lsls	r3, r0, #22
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e647a <uniffi_pbcli_checksum_method_api_base@@Base+0x279bf6>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r5, r6, r7, r8, r9, sl, pc}
│ │ +	ldmia.w	sp!, {r1, r2, r4, fp, pc}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e648a <uniffi_pbcli_checksum_method_api_base@@Base+0x279c06>
│ │  	beq.n	3e615c <uniffi_pbcli_checksum_method_api_base@@Base+0x2798d8>
│ │  	b.n	3e65e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x279d64>
│ │  	adds	r0, #20
│ │  	b.n	3e5c90 <uniffi_pbcli_checksum_method_api_base@@Base+0x27940c>
│ │ @@ -1167152,15 +1167152,15 @@
│ │  	b.n	3e5d50 <uniffi_pbcli_checksum_method_api_base@@Base+0x2794cc>
│ │  	adds	r0, #3
│ │  	b.n	3e6358 <uniffi_pbcli_checksum_method_api_base@@Base+0x279ad4>
│ │  	lsls	r1, r0, #21
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e6582 <uniffi_pbcli_checksum_method_api_base@@Base+0x279cfe>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r6, r8, r9, sl, ip}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r5, r6, r8, r9, sl, ip}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e6592 <uniffi_pbcli_checksum_method_api_base@@Base+0x279d0e>
│ │  	beq.n	3e6264 <uniffi_pbcli_checksum_method_api_base@@Base+0x2799e0>
│ │  	b.n	3e66f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x279e6c>
│ │  	adds	r0, #20
│ │  	b.n	3e5d98 <uniffi_pbcli_checksum_method_api_base@@Base+0x279514>
│ │ @@ -1167170,15 +1167170,15 @@
│ │  	b.n	3e5d7c <uniffi_pbcli_checksum_method_api_base@@Base+0x2794f8>
│ │  	adds	r0, #3
│ │  	b.n	3e6384 <uniffi_pbcli_checksum_method_api_base@@Base+0x279b00>
│ │  	lsls	r6, r6, #20
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e65ae <uniffi_pbcli_checksum_method_api_base@@Base+0x279d2a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r8, r9, sl, ip}
│ │ +	ldmia.w	sp!, {r1, r6, r8, r9, sl, ip}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e65be <uniffi_pbcli_checksum_method_api_base@@Base+0x279d3a>
│ │  	beq.n	3e6290 <uniffi_pbcli_checksum_method_api_base@@Base+0x279a0c>
│ │  	b.n	3e671c <uniffi_pbcli_checksum_method_api_base@@Base+0x279e98>
│ │  	adds	r0, #20
│ │  	b.n	3e5dc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x279540>
│ │ @@ -1167188,15 +1167188,15 @@
│ │  	b.n	3e5da8 <uniffi_pbcli_checksum_method_api_base@@Base+0x279524>
│ │  	adds	r0, #3
│ │  	b.n	3e63b0 <uniffi_pbcli_checksum_method_api_base@@Base+0x279b2c>
│ │  	lsls	r3, r5, #20
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e65da <uniffi_pbcli_checksum_method_api_base@@Base+0x279d56>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r5, r6, r7, r9, sl, ip}
│ │ +	ldmia.w	sp!, {r1, r2, r4, r8, r9, sl, ip}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e65ea <uniffi_pbcli_checksum_method_api_base@@Base+0x279d66>
│ │  	beq.n	3e62bc <uniffi_pbcli_checksum_method_api_base@@Base+0x279a38>
│ │  	b.n	3e6748 <uniffi_pbcli_checksum_method_api_base@@Base+0x279ec4>
│ │  	adds	r0, #20
│ │  	b.n	3e5df0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27956c>
│ │ @@ -1167206,15 +1167206,15 @@
│ │  	b.n	3e5dd4 <uniffi_pbcli_checksum_method_api_base@@Base+0x279550>
│ │  	adds	r0, #3
│ │  	b.n	3e63dc <uniffi_pbcli_checksum_method_api_base@@Base+0x279b58>
│ │  	lsls	r0, r4, #20
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e6606 <uniffi_pbcli_checksum_method_api_base@@Base+0x279d82>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r6, r7, r9, sl, ip}
│ │ +	ldmia.w	sp!, {r1, r3, r5, r6, r7, r9, sl, ip}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e6616 <uniffi_pbcli_checksum_method_api_base@@Base+0x279d92>
│ │  	beq.n	3e62e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x279a64>
│ │  	b.n	3e6774 <uniffi_pbcli_checksum_method_api_base@@Base+0x279ef0>
│ │  	adds	r0, #20
│ │  	b.n	3e5e1c <uniffi_pbcli_checksum_method_api_base@@Base+0x279598>
│ │ @@ -1167224,15 +1167224,15 @@
│ │  	b.n	3e5e00 <uniffi_pbcli_checksum_method_api_base@@Base+0x27957c>
│ │  	adds	r0, #3
│ │  	b.n	3e6408 <uniffi_pbcli_checksum_method_api_base@@Base+0x279b84>
│ │  	lsls	r5, r2, #20
│ │  			@ <UNDEFINED> instruction: 0xeb00d00b
│ │  	b.n	3e6632 <uniffi_pbcli_checksum_method_api_base@@Base+0x279dae>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r7, r9, sl, ip}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r5, r7, r9, sl, ip}
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3e6642 <uniffi_pbcli_checksum_method_api_base@@Base+0x279dbe>
│ │  	beq.n	3e6314 <uniffi_pbcli_checksum_method_api_base@@Base+0x279a90>
│ │  	b.n	3e67a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x279f1c>
│ │  	adds	r0, #20
│ │  	b.n	3e5e48 <uniffi_pbcli_checksum_method_api_base@@Base+0x2795c4>
│ │ @@ -1167651,15 +1167651,15 @@
│ │  			@ <UNDEFINED> instruction: 0xffc93ada
│ │  			@ <UNDEFINED> instruction: 0xffca7bd0
│ │  	vqrshrn.u16	d20, <illegal reg q13.5>, #7
│ │  			@ <UNDEFINED> instruction: 0xffc93b2a
│ │  	vmlal.u<illegal width 8>	q9, d26, d2[6]
│ │  	vmul.i<illegal width 8>	q10, q13, d3[6]
│ │  			@ <UNDEFINED> instruction: 0xffc93a9a
│ │ -			@ <UNDEFINED> instruction: 0xffcaef07
│ │ +			@ <UNDEFINED> instruction: 0xffcaef2e
│ │  	vshll.u8	q10, d3, #2
│ │  			@ <UNDEFINED> instruction: 0xffc93bc2
│ │  			@ <UNDEFINED> instruction: 0xffca48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3e6c20 <uniffi_pbcli_checksum_method_api_base@@Base+0x27a39c>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3e6a4a <uniffi_pbcli_checksum_method_api_base@@Base+0x27a1c6>
│ │ @@ -1167807,15 +1167807,15 @@
│ │  			@ <UNDEFINED> instruction: 0xffc90901
│ │  	vshr.u8	d21, d19, #6
│ │  	vqshl.u64	d20, d19, #10
│ │  	vqshrn.u16	d16, <illegal reg q8.5>, #7
│ │  			@ <UNDEFINED> instruction: 0xffcad8f8
│ │  			@ <UNDEFINED> instruction: 0xffc94747
│ │  	vmul.i<illegal width 8>	q8, <illegal reg q12.5>, d1[1]
│ │ -	vqrdmlah.s<illegal width 8>	q9, q13, d2[3]
│ │ +			@ <UNDEFINED> instruction: 0xffca2ef5
│ │  			@ <UNDEFINED> instruction: 0xffcb4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3e6d8c <uniffi_pbcli_checksum_method_api_base@@Base+0x27a508>
│ │  	beq.n	3e6884 <uniffi_pbcli_checksum_method_api_base@@Base+0x27a000>
│ │  	b.n	3e6d10 <uniffi_pbcli_checksum_method_api_base@@Base+0x27a48c>
│ │  	ands	r2, r0
│ │  	b.n	3e6bba <uniffi_pbcli_checksum_method_api_base@@Base+0x27a336>
│ │ @@ -1168065,15 +1168065,15 @@
│ │  	b.n	3e6bc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x27a340>
│ │  			@ <UNDEFINED> instruction: 0xffaeeaff
│ │  	mov	r3, r2
│ │  	vabdl.u8	<illegal reg q14.5>, d25, d10
│ │  	vqrdmlah.s<illegal width 8>	q10, <illegal reg q12.5>, d3[3]
│ │  	vmls.f<illegal width 8>	q10, q13, d3[4]
│ │  	vqshl.u8	<illegal reg q14.5>, q5, #1
│ │ -			@ <UNDEFINED> instruction: 0xffc92d72
│ │ +			@ <UNDEFINED> instruction: 0xffc92d99
│ │  	vmlsl.u<illegal width 8>	q10, d11, d3[0]
│ │  	vqshl.u64	d29, d26, #9
│ │  	vsli.8	q10, <illegal reg q9.5>, #1
│ │  	vmlsl.u<illegal width 8>	<illegal reg q14.5>, d25, d2[6]
│ │  	vmlsl.u<illegal width 8>	<illegal reg q14.5>, d25, d0[0]
│ │  	vraddhn.i16	d20, <illegal reg q12.5>, <illegal reg q11.5>
│ │  	vqshlu.s8	d29, d14, #1
│ │ @@ -1168799,26 +1168799,26 @@
│ │  	bhi.n	3e772e <uniffi_pbcli_checksum_method_api_base@@Base+0x27aeaa>	@ unpredictable branch in IT block
│ │  
│ │  	asrls	r0, r1, #32
│ │  	b.n	3e77b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x27af2e>
│ │  	vpmin.u<illegal width 64>	q7, q11, <illegal reg q15.5>
│ │  	negs	r7, r0
│ │  	vrshr.u8	q10, <illegal reg q8.5>, #7
│ │ -			@ <UNDEFINED> instruction: 0xffc99b1f
│ │ +			@ <UNDEFINED> instruction: 0xffc99b46
│ │  	vmla.f<illegal width 8>	q10, <illegal reg q5.5>, d3[5]
│ │  	vsra.u64	d20, d1, #55
│ │ -			@ <UNDEFINED> instruction: 0xffc98f34
│ │ +			@ <UNDEFINED> instruction: 0xffc98f5b
│ │  	vaddl.u8	q10, d27, d7
│ │  	vshr.u64	d20, d17, #55
│ │  	vmull.u<illegal width 8>	q15, d9, d1[0]
│ │  	vshr.u8	q10, <illegal reg q7.5>, #7
│ │  	vaddl.u8	q10, d25, d9
│ │  	vmla.i<illegal width 8>	q10, <illegal reg q12.5>, d3[2]
│ │  	vshr.u64	q10, <illegal reg q10.5>, #55
│ │ -			@ <UNDEFINED> instruction: 0xffc96ba7
│ │ +			@ <UNDEFINED> instruction: 0xffc96bce
│ │  			@ <UNDEFINED> instruction: 0xffcb3f0b
│ │  			@ <UNDEFINED> instruction: 0xffc93f35
│ │  			@ <UNDEFINED> instruction: 0xffc93f27
│ │  			@ <UNDEFINED> instruction: 0xffc93f51
│ │  	vqrdmlsh.s<illegal width 8>	<illegal reg q9.5>, <illegal reg q12.5>, d3[5]
│ │  	vshr.u8	d20, d1, #7
│ │  	vmul.i<illegal width 8>	q9, <illegal reg q4.5>, d2[4]
│ │ @@ -1170827,15 +1170827,15 @@
│ │  	b.n	3e89de <uniffi_pbcli_checksum_method_api_base@@Base+0x27c15a>
│ │  	ands	r1, r0
│ │  	asrs	r0, r4, #14
│ │  	movs	r4, r0
│ │  	b.n	3e8686 <uniffi_pbcli_checksum_method_api_base@@Base+0x27be02>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r3, r6, r8, r9, sl, ip}
│ │ -			@ <UNDEFINED> instruction: 0xffca6e94
│ │ +			@ <UNDEFINED> instruction: 0xffca6ebb
│ │  			@ <UNDEFINED> instruction: 0xffcbff24
│ │  	vaddl.u8	q8, d8, d4
│ │  	b.n	3e7e98 <uniffi_pbcli_checksum_method_api_base@@Base+0x27b614>
│ │  	movs	r0, r0
│ │  	b.n	3e847c <uniffi_pbcli_checksum_method_api_base@@Base+0x27bbf8>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	strb	r4, [r7, #8]
│ │ @@ -1171002,15 +1171002,15 @@
│ │  	b.n	3e8bfe <uniffi_pbcli_checksum_method_api_base@@Base+0x27c37a>
│ │  	asrs	r1, r0, #32
│ │  	b.n	3e85e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27bd5c>
│ │  	bcs.n	3e83c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x27bb42>
│ │  			@ <UNDEFINED> instruction: 0xebfcfff7
│ │  			@ <UNDEFINED> instruction: 0xeaffae96
│ │  	vmul.f<illegal width 8>	q10, q13, d3[3]
│ │ -			@ <UNDEFINED> instruction: 0xffca6d58
│ │ +			@ <UNDEFINED> instruction: 0xffca6d7f
│ │  			@ <UNDEFINED> instruction: 0xffcbfdd4
│ │  			@ <UNDEFINED> instruction: 0xffc848fb
│ │  			@ <UNDEFINED> instruction: 0xffca4923
│ │  	vaddl.u8	q8, d10, d4
│ │  	b.n	3e8024 <uniffi_pbcli_checksum_method_api_base@@Base+0x27b7a0>
│ │  	movs	r0, r0
│ │  	b.n	3e8608 <uniffi_pbcli_checksum_method_api_base@@Base+0x27bd84>
│ │ @@ -1171159,18 +1171159,18 @@
│ │  	movs	r0, #2
│ │  	b.n	3e8758 <uniffi_pbcli_checksum_method_api_base@@Base+0x27bed4>
│ │  	hlt	0x000e
│ │  			@ <UNDEFINED> instruction: 0xebfb0000
│ │  	b.n	3e8d82 <uniffi_pbcli_checksum_method_api_base@@Base+0x27c4fe>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r1, r2, r5, fp, lr}
│ │ -	vshr.u8	d29, d27, #6
│ │ +	vmla.i<illegal width 8>	<illegal reg q14.5>, q5, d2[4]
│ │  	vqshl.u64	d20, d15, #10
│ │ -			@ <UNDEFINED> instruction: 0xffcacfb3
│ │ -	vshr.u64	d17, d14, #54
│ │ +			@ <UNDEFINED> instruction: 0xffcacfda
│ │ +	vmla.i<illegal width 8>	<illegal reg q8.5>, q13, d1[1]
│ │  			@ <UNDEFINED> instruction: 0xffcb4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3e8b7c <uniffi_pbcli_checksum_method_api_base@@Base+0x27c2f8>
│ │  	beq.n	3e8674 <uniffi_pbcli_checksum_method_api_base@@Base+0x27bdf0>
│ │  	b.n	3e8b00 <uniffi_pbcli_checksum_method_api_base@@Base+0x27c27c>
│ │  	movs	r0, #12
│ │  	b.n	3e820a <uniffi_pbcli_checksum_method_api_base@@Base+0x27b986>
│ │ @@ -1171858,38 +1171858,38 @@
│ │  	b.n	3e8f9e <uniffi_pbcli_checksum_method_api_base@@Base+0x27c71a>
│ │  	beq.n	3e8c98 <uniffi_pbcli_checksum_method_api_base@@Base+0x27c414>
│ │  	b.n	3e90f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x27c874>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │  	ldmia.w	sp!, {lr}
│ │  	b.n	3e93aa <uniffi_pbcli_checksum_method_api_base@@Base+0x27cb26>
│ │  			@ <UNDEFINED> instruction: 0xfff0eaff
│ │ -	bl	3e5c04 <uniffi_pbcli_checksum_method_api_base@@Base+0x279380>
│ │ -	add	r5, sp, #340	@ 0x154
│ │ -	vqshl.u64	<illegal reg q15.5>, q2, #11
│ │ -			@ <UNDEFINED> instruction: 0xffcaad2d
│ │ -	vqshl.u64	d31, d4, #11
│ │ -	vqdmulh.s<illegal width 8>	q13, q13, d1[7]
│ │ -	vqshl.u8	<illegal reg q15.5>, q2, #3
│ │ -	vmull.u8	q13, d26, d29
│ │ -	vabdl.u8	<illegal reg q15.5>, d11, d24
│ │ -	vmull.u8	q13, d26, d1
│ │ -	vmlal.u8	<illegal reg q15.5>, d11, d24
│ │ -			@ <UNDEFINED> instruction: 0xffcaad81
│ │ -	vraddhn.i16	d31, <illegal reg q13.5>, q6
│ │ -	vmul.f<illegal width 8>	q13, q13, d1[5]
│ │ -	vsri.8	<illegal reg q15.5>, q8, #5
│ │ -	vmul.f<illegal width 8>	q13, q13, d1[2]
│ │ -	vraddhn.i16	d31, <illegal reg q5.5>, q12
│ │ -			@ <UNDEFINED> instruction: 0xffcaa981
│ │ -	vsri.8	<illegal reg q15.5>, q2, #5
│ │ -			@ <UNDEFINED> instruction: 0xffcaa9ad
│ │ -	vrsubhn.i16	d31, <illegal reg q13.5>, q0
│ │ -	vmls.i<illegal width 8>	<illegal reg q15.5>, q13, d0[2]
│ │ -	vmlsl.u8	q13, d10, d17
│ │ -	vrsra.u64	<illegal reg q15.5>, q10, #53
│ │ +	strh.w	pc, [r3, #202]!
│ │ +	add	r5, sp, #496	@ 0x1f0
│ │ +	vqshl.u64	<illegal reg q15.5>, <illegal reg q13.5>, #11
│ │ +			@ <UNDEFINED> instruction: 0xffcaad54
│ │ +	vqshl.u64	d31, d27, #11
│ │ +			@ <UNDEFINED> instruction: 0xffcaad14
│ │ +	vqshl.u8	<illegal reg q15.5>, <illegal reg q13.5>, #3
│ │ +			@ <UNDEFINED> instruction: 0xffcaacd4
│ │ +			@ <UNDEFINED> instruction: 0xffcbf74f
│ │ +	vmull.u8	q13, d26, d24
│ │ +	vmul.i<illegal width 8>	<illegal reg q15.5>, <illegal reg q5.5>, d3[3]
│ │ +			@ <UNDEFINED> instruction: 0xffcaada8
│ │ +	vsri.64	d31, d19, #53
│ │ +	vmlsl.u8	q13, d10, d12
│ │ +	vsri.64	d31, d7, #53
│ │ +			@ <UNDEFINED> instruction: 0xffcaa9f0
│ │ +	vmls.i<illegal width 8>	<illegal reg q15.5>, <illegal reg q5.5>, d3[3]
│ │ +			@ <UNDEFINED> instruction: 0xffcaa9a8
│ │ +	vsri.8	<illegal reg q15.5>, <illegal reg q13.5>, #5
│ │ +			@ <UNDEFINED> instruction: 0xffcaa9d4
│ │ +	vrsubhn.i16	d31, <illegal reg q13.5>, <illegal reg q11.5>
│ │ +	vmls.i<illegal width 8>	<illegal reg q15.5>, q13, d3[7]
│ │ +	vmull.u<illegal width 8>	q13, d10, d0[2]
│ │ +	vsri.8	d31, d11, #5
│ │  			@ <UNDEFINED> instruction: 0xffca4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3e91f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27c96c>
│ │  	beq.n	3e8d30 <uniffi_pbcli_checksum_method_api_base@@Base+0x27c4ac>
│ │  	b.n	3e9174 <uniffi_pbcli_checksum_method_api_base@@Base+0x27c8f0>
│ │  	asrs	r4, r4, #32
│ │  	b.n	3e87f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x27bf74>
│ │ @@ -1172370,15 +1172370,15 @@
│ │  	add	r1, pc, #200	@ (adr r1, 3e91cc <uniffi_pbcli_checksum_method_api_base@@Base+0x27c948>)
│ │  	b.n	3e9706 <uniffi_pbcli_checksum_method_api_base@@Base+0x27ce82>
│ │  	ands	r0, r1
│ │  	b.n	3e978a <uniffi_pbcli_checksum_method_api_base@@Base+0x27cf06>
│ │  	ands	r7, r4
│ │  	b.n	3e9616 <uniffi_pbcli_checksum_method_api_base@@Base+0x27cd92>
│ │  			@ <UNDEFINED> instruction: 0xfff5eaff
│ │ -	bl	44e0a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x2e1824>
│ │ +	bl	4750a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x308824>
│ │  	cbz	r0, 3e9124 <uniffi_pbcli_checksum_method_api_base@@Base+0x27c8a0>
│ │  			@ <UNDEFINED> instruction: 0xffc94ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3e963c <uniffi_pbcli_checksum_method_api_base@@Base+0x27cdb8>
│ │  	beq.n	3e915c <uniffi_pbcli_checksum_method_api_base@@Base+0x27c8d8>
│ │  	b.n	3e95c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27cd3c>
│ │  	ands	r2, r0
│ │ @@ -1172697,27 +1172697,27 @@
│ │  	movs	r0, #60	@ 0x3c
│ │  	b.n	3e8f34 <uniffi_pbcli_checksum_method_api_base@@Base+0x27c6b0>
│ │  	movs	r0, r0
│ │  	b.n	3e9518 <uniffi_pbcli_checksum_method_api_base@@Base+0x27cc94>
│ │  	movs	r0, #2
│ │  	b.n	3e951c <uniffi_pbcli_checksum_method_api_base@@Base+0x27cc98>
│ │  			@ <UNDEFINED> instruction: 0xffb4eaff
│ │ -	cdp	15, 11, cr15, cr0, cr10, {6}
│ │ +	cdp	15, 13, cr15, cr7, cr10, {6}
│ │  	str	r5, [sp, #256]	@ 0x100
│ │ -	vqrdmulh.s<illegal width 8>	q15, q5, d0[6]
│ │ +			@ <UNDEFINED> instruction: 0xffcaed8f
│ │  	vrsra.u64	<illegal reg q12.5>, q12, #54
│ │ -			@ <UNDEFINED> instruction: 0xffcaed94
│ │ +			@ <UNDEFINED> instruction: 0xffcaedbb
│ │  	vraddhn.i16	d25, q5, q10
│ │ -			@ <UNDEFINED> instruction: 0xffcaed10
│ │ +			@ <UNDEFINED> instruction: 0xffcaed37
│ │  	vsubw.u8	<illegal reg q12.5>, q13, d16
│ │ -			@ <UNDEFINED> instruction: 0xffcaedb0
│ │ +			@ <UNDEFINED> instruction: 0xffcaedd7
│ │  	vmls.i<illegal width 8>	<illegal reg q12.5>, q5, d0[0]
│ │ -	vqdmulh.s<illegal width 8>	q15, q5, d0[7]
│ │ +			@ <UNDEFINED> instruction: 0xffcaec93
│ │  	vrshr.u64	<illegal reg q12.5>, q14, #54
│ │ -	vqdmulh.s<illegal width 8>	q15, q5, d0[0]
│ │ +	vqdmulh.s<illegal width 8>	q15, q5, d3[5]
│ │  	vrshr.u64	<illegal reg q12.5>, q0, #54
│ │  			@ <UNDEFINED> instruction: 0xffca4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3e995c <uniffi_pbcli_checksum_method_api_base@@Base+0x27d0d8>
│ │  	beq.n	3e9454 <uniffi_pbcli_checksum_method_api_base@@Base+0x27cbd0>
│ │  	b.n	3e98e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27d05c>
│ │  	movs	r0, r0
│ │ @@ -1172856,21 +1172856,21 @@
│ │  	b.n	3e98b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x27d032>
│ │  	ldrb	r7, [r0, #1]
│ │  			@ <UNDEFINED> instruction: 0xebfa0006
│ │  	b.n	3e98be <uniffi_pbcli_checksum_method_api_base@@Base+0x27d03a>
│ │  	beq.n	3e95a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27cd1c>
│ │  	b.n	3e9a18 <uniffi_pbcli_checksum_method_api_base@@Base+0x27d194>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │ -	ldmia.w	sp!, {r2, r7, r8, r9, fp, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r5, r7, r8, r9, fp, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcaac39
│ │ -			@ <UNDEFINED> instruction: 0xffc9eb54
│ │ +			@ <UNDEFINED> instruction: 0xffc9eb7b
│ │  	vmull.u8	q13, d10, d9
│ │ -			@ <UNDEFINED> instruction: 0xffc9eb18
│ │ +			@ <UNDEFINED> instruction: 0xffc9eb3f
│ │  			@ <UNDEFINED> instruction: 0xffcaabcd
│ │ -			@ <UNDEFINED> instruction: 0xffc9eaf0
│ │ +			@ <UNDEFINED> instruction: 0xffc9eb17
│ │  			@ <UNDEFINED> instruction: 0xffcaaba5
│ │  			@ <UNDEFINED> instruction: 0xffc94df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3e9ac8 <uniffi_pbcli_checksum_method_api_base@@Base+0x27d244>
│ │  	beq.n	3e95d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27cd4c>
│ │  	b.n	3e9a4c <uniffi_pbcli_checksum_method_api_base@@Base+0x27d1c8>
│ │  	ands	r0, r0
│ │ @@ -1173041,23 +1173041,23 @@
│ │  	b.n	3e9844 <uniffi_pbcli_checksum_method_api_base@@Base+0x27cfc0>
│ │  			@ <UNDEFINED> instruction: 0xb616
│ │  			@ <UNDEFINED> instruction: 0xebfb1003
│ │  	b.n	3e9d2e <uniffi_pbcli_checksum_method_api_base@@Base+0x27d4aa>
│ │  	asrs	r0, r1, #32
│ │  	b.n	3e9db2 <uniffi_pbcli_checksum_method_api_base@@Base+0x27d52e>
│ │  			@ <UNDEFINED> instruction: 0xffcbeaff
│ │ -	strd	pc, pc, [r8, #808]!	@ 0x328
│ │ +			@ <UNDEFINED> instruction: 0xea0fffca
│ │  	bl	6906ce <uniffi_pbcli_checksum_method_api_base@@Base+0x523e4a>
│ │ -			@ <UNDEFINED> instruction: 0xe9b8ffca
│ │ +	ldrd	pc, pc, [pc, #808]	@ 3e9a68 <uniffi_pbcli_checksum_method_api_base@@Base+0x27d1e4>	@ 0x328
│ │  	bl	6606d6 <uniffi_pbcli_checksum_method_api_base@@Base+0x4f3e52>
│ │ -			@ <UNDEFINED> instruction: 0xea04ffca
│ │ +			@ <UNDEFINED> instruction: 0xea2bffca
│ │  	bl	6ac6de <uniffi_pbcli_checksum_method_api_base@@Base+0x53fe5a>
│ │ -	ldmdb	r8, {r1, r3, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}
│ │ +	ldmdb	pc!, {r1, r3, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}
│ │  	bl	5c06e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x453e62>
│ │ -			@ <UNDEFINED> instruction: 0xe988ffca
│ │ +			@ <UNDEFINED> instruction: 0xe9afffca
│ │  	ldr	r4, [pc, #448]	@ (3e991c <uniffi_pbcli_checksum_method_api_base@@Base+0x27d098>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3e9c7c <uniffi_pbcli_checksum_method_api_base@@Base+0x27d3f8>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3e9aa6 <uniffi_pbcli_checksum_method_api_base@@Base+0x27d222>
│ │  	lsls	r7, r6, #17
│ │  	b.n	3e9d6a <uniffi_pbcli_checksum_method_api_base@@Base+0x27d4e6>
│ │ @@ -1173591,35 +1173591,35 @@
│ │  			@ <UNDEFINED> instruction: 0xfff9eaff
│ │  	cmp	pc, r8
│ │  	vrsra.u64	d23, d4, #54
│ │  			@ <UNDEFINED> instruction: 0xffc908ba
│ │  			@ <UNDEFINED> instruction: 0xffca1ef6
│ │  	vqrdmulh.s<illegal width 8>	q12, <illegal reg q12.5>, d3[1]
│ │  			@ <UNDEFINED> instruction: 0xffca48d3
│ │ -			@ <UNDEFINED> instruction: 0xffca5d97
│ │ +			@ <UNDEFINED> instruction: 0xffca5dbe
│ │  			@ <UNDEFINED> instruction: 0xffcb8c17
│ │  	vabdl.u8	q10, d10, d19
│ │ -	vsra.u8	d17, d14, #6
│ │ +	vmla.f<illegal width 8>	<illegal reg q8.5>, q5, d1[1]
│ │  			@ <UNDEFINED> instruction: 0xffcb8e53
│ │  	vqrshrn.u16	d20, <illegal reg q7.5>, #6
│ │  	vqrdmulh.s<illegal width 8>	q12, q5, d3[1]
│ │  	vqrshrun.s16	d20, <illegal reg q1.5>, #6
│ │ -			@ <UNDEFINED> instruction: 0xffca5d17
│ │ +			@ <UNDEFINED> instruction: 0xffca5d3e
│ │  	vqdmulh.s<illegal width 8>	q12, <illegal reg q13.5>, d3[4]
│ │  			@ <UNDEFINED> instruction: 0xffca8cbb
│ │  			@ <UNDEFINED> instruction: 0xffca8b5f
│ │  	vsri.8	d17, d26, #6
│ │  			@ <UNDEFINED> instruction: 0xffc98c5b
│ │  	vsli.8	d17, d22, #2
│ │  	vqshlu.s64	<illegal reg q11.5>, q7, #9
│ │  	vmls.i<illegal width 8>	<illegal reg q15.5>, <illegal reg q4.5>, d1[0]
│ │  			@ <UNDEFINED> instruction: 0xffc98bc7
│ │  			@ <UNDEFINED> instruction: 0xffca8b9f
│ │  			@ <UNDEFINED> instruction: 0xffca8b1f
│ │ -	vmla.i<illegal width 8>	<illegal reg q8.5>, q5, d0[3]
│ │ +	vshr.u8	<illegal reg q8.5>, <illegal reg q9.5>, #6
│ │  			@ <UNDEFINED> instruction: 0xffcb4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3ea18c <uniffi_pbcli_checksum_method_api_base@@Base+0x27d908>
│ │  	str	r0, [r0, #0]
│ │  	b.n	3e9fb6 <uniffi_pbcli_checksum_method_api_base@@Base+0x27d732>
│ │  	ldr	r0, [sp, #364]	@ 0x16c
│ │  			@ <UNDEFINED> instruction: 0xebfe0000
│ │ @@ -1173687,15 +1173687,15 @@
│ │  	b.n	3ea046 <uniffi_pbcli_checksum_method_api_base@@Base+0x27d7c2>
│ │  	ldr	r1, [pc, #332]	@ (3e9e54 <uniffi_pbcli_checksum_method_api_base@@Base+0x27d5d0>)
│ │  			@ <UNDEFINED> instruction: 0xebfa0005
│ │  	b.n	3ea04e <uniffi_pbcli_checksum_method_api_base@@Base+0x27d7ca>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r0, r1, r2, r6, r9, fp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffca89f7
│ │ -			@ <UNDEFINED> instruction: 0xffca0f24
│ │ +	vqrdmlsh.s<illegal width 8>	q8, q5, d3[2]
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3e9860 <uniffi_pbcli_checksum_method_api_base@@Base+0x27cfdc>
│ │  	movs	r0, r0
│ │  	b.n	3e9e44 <uniffi_pbcli_checksum_method_api_base@@Base+0x27d5c0>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	ldr	r4, [r2, r5]
│ │  	movs	r6, r1
│ │ @@ -1173922,17 +1173922,17 @@
│ │  	b.n	3ea652 <uniffi_pbcli_checksum_method_api_base@@Base+0x27ddce>
│ │  	push	{r3, r4, r6}
│ │  			@ <UNDEFINED> instruction: 0xebfb0005
│ │  	b.n	3ea25a <uniffi_pbcli_checksum_method_api_base@@Base+0x27d9d6>
│ │  	beq.n	3e9f4c <uniffi_pbcli_checksum_method_api_base@@Base+0x27d6c8>
│ │  	b.n	3ea3b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x27db30>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r6, r7, r9, sl, ip, lr}
│ │ +	ldmia.w	sp!, {r5, r8, r9, sl, ip, lr}
│ │  	vqrshrn.u16	d24, <illegal reg q3.5>, #5
│ │ -			@ <UNDEFINED> instruction: 0xffca53e2
│ │ +	vraddhn.i16	d21, q5, <illegal reg q4.5>
│ │  			@ <UNDEFINED> instruction: 0xffcb8903
│ │  	vabal.u8	q14, d26, d24
│ │  			@ <UNDEFINED> instruction: 0xffcb2a7b
│ │  	vqshl.u64	q12, <illegal reg q7.5>, #10
│ │  			@ <UNDEFINED> instruction: 0xffca8adf
│ │  	vrshr.u8	d23, d13, #7
│ │  			@ <UNDEFINED> instruction: 0xffca4ff0
│ │ @@ -1174575,15 +1174575,15 @@
│ │  	lsls	r0, r5, #11
│ │  	movs	r0, r0
│ │  	ldrsb	r4, [r7, r2]
│ │  	movs	r6, r1
│ │  	strh	r3, [r4, #36]	@ 0x24
│ │  	vqrdmlah.s<illegal width 8>	<illegal reg q15.5>, q13, d1[3]
│ │  	vabal.u8	q12, d9, d23
│ │ -	vmlal.u<illegal width 8>	<illegal reg q10.5>, d26, d2[1]
│ │ +	vmlal.u<illegal width 8>	<illegal reg q10.5>, d26, d1[7]
│ │  	vmls.f<illegal width 8>	<illegal reg q8.5>, <illegal reg q5.5>, d2[7]
│ │  	vsri.8	q12, <illegal reg q5.5>, #7
│ │  	vmlal.u<illegal width 8>	q12, d10, d3[7]
│ │  	vrshr.u64	d24, d12, #54
│ │  	vqshrun.s16	d20, q8, #6
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3eaa50 <uniffi_pbcli_checksum_method_api_base@@Base+0x27e1cc>
│ │ @@ -1174911,16 +1174911,16 @@
│ │  	and.w	r0, r0, r1, lsl #24
│ │  	b.n	3eaf62 <uniffi_pbcli_checksum_method_api_base@@Base+0x27e6de>
│ │  	movs	r6, r0
│ │  	b.n	3eab66 <uniffi_pbcli_checksum_method_api_base@@Base+0x27e2e2>
│ │  	beq.n	3ea858 <uniffi_pbcli_checksum_method_api_base@@Base+0x27dfd4>
│ │  	b.n	3eacc0 <uniffi_pbcli_checksum_method_api_base@@Base+0x27e43c>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r4, r5, r8, sl, sp, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffcbdbbc
│ │ +	ldmia.w	sp!, {r3, r4, r6, r8, sl, sp, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffcbdbe3
│ │  			@ <UNDEFINED> instruction: 0xffca4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3ead58 <uniffi_pbcli_checksum_method_api_base@@Base+0x27e4d4>
│ │  	beq.n	3ea930 <uniffi_pbcli_checksum_method_api_base@@Base+0x27e0ac>
│ │  	b.n	3eacdc <uniffi_pbcli_checksum_method_api_base@@Base+0x27e458>
│ │  	str	r0, [sp, #12]
│ │  	b.n	3eab86 <uniffi_pbcli_checksum_method_api_base@@Base+0x27e302>
│ │ @@ -1175151,16 +1175151,16 @@
│ │  	movs	r0, #2
│ │  	b.n	3eab6c <uniffi_pbcli_checksum_method_api_base@@Base+0x27e2e8>
│ │  			@ <UNDEFINED> instruction: 0xffe5eaff
│ │  	lsrs	r0, r5, #25
│ │  			@ <UNDEFINED> instruction: 0xffca7d38
│ │  	vmull.p8	q8, d10, d4
│ │  			@ <UNDEFINED> instruction: 0xffca7cd4
│ │ -	vrsra.u8	q11, <illegal reg q14.5>, #6
│ │ -	vmlsl.u8	<illegal reg q14.5>, d11, d0
│ │ +	vsubw.u8	q11, q13, d20
│ │ +	vmlsl.u8	<illegal reg q14.5>, d11, d23
│ │  			@ <UNDEFINED> instruction: 0xffca4bf0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3eaf8c <uniffi_pbcli_checksum_method_api_base@@Base+0x27e708>
│ │  	beq.n	3eab44 <uniffi_pbcli_checksum_method_api_base@@Base+0x27e2c0>
│ │  	b.n	3eaf10 <uniffi_pbcli_checksum_method_api_base@@Base+0x27e68c>
│ │  	str	r0, [sp, #12]
│ │  	b.n	3eadba <uniffi_pbcli_checksum_method_api_base@@Base+0x27e536>
│ │ @@ -1175378,16 +1175378,16 @@
│ │  	movs	r0, #2
│ │  	b.n	3ead84 <uniffi_pbcli_checksum_method_api_base@@Base+0x27e500>
│ │  			@ <UNDEFINED> instruction: 0xffe5eaff
│ │  	lsrs	r0, r2, #17
│ │  	vmull.u8	q15, d26, d10
│ │  			@ <UNDEFINED> instruction: 0xffc80bec
│ │  	vmull.u8	q15, d10, d22
│ │ -	vmla.f<illegal width 8>	q11, q4, d1[5]
│ │ -			@ <UNDEFINED> instruction: 0xffcbd7e8
│ │ +	vaddw.u8	q11, q12, d12
│ │ +	vmlal.u8	<illegal reg q14.5>, d11, d15
│ │  			@ <UNDEFINED> instruction: 0xffca4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3eb1a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x27e920>
│ │  	svc	205	@ 0xcd
│ │  	b.n	3eb128 <uniffi_pbcli_checksum_method_api_base@@Base+0x27e8a4>
│ │  	strh	r0, [r2, #0]
│ │  	b.n	3ea7c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x27df44>
│ │ @@ -1176589,15 +1176589,15 @@
│ │  	asrs	r7, r0, #22
│ │  			@ <UNDEFINED> instruction: 0xfff7eaff
│ │  	adds	r6, #215	@ 0xd7
│ │  	vmull.u<illegal width 8>	q8, d10, d0[4]
│ │  	movs	r0, r0
│ │  	movs	r7, #120	@ 0x78
│ │  	movs	r7, r1
│ │ -	strb	r1, [r6, #15]
│ │ +	strb	r0, [r3, #16]
│ │  	vmlsl.u8	q8, d27, d0
│ │  	movs	r0, r0
│ │  	movs	r7, #88	@ 0x58
│ │  	movs	r7, r1
│ │  	add	r4, pc, #632	@ (adr r4, 3eb99c <uniffi_pbcli_checksum_method_api_base@@Base+0x27f118>)
│ │  	vmull.u<illegal width 8>	q8, d25, d0[4]
│ │  	movs	r0, r0
│ │ @@ -1176609,15 +1176609,15 @@
│ │  	movs	r6, #172	@ 0xac
│ │  	movs	r7, r1
│ │  	push	{r4, r7}
│ │  	vrsra.u8	q8, q6, #7
│ │  	movs	r0, r0
│ │  	subs	r0, r4, #1
│ │  	movs	r7, r1
│ │ -	add	r6, sp, #1008	@ 0x3f0
│ │ +	add	r7, sp, #140	@ 0x8c
│ │  	vsubw.u8	q8, q5, d4
│ │  	movs	r0, r0
│ │  	subs	r0, r1, #0
│ │  	movs	r7, r1
│ │  	movs	r0, #0
│ │  	b.n	3eb276 <uniffi_pbcli_checksum_method_api_base@@Base+0x27e9f2>
│ │  	movs	r0, #0
│ │ @@ -1177765,17 +1177765,17 @@
│ │  			@ <UNDEFINED> instruction: 0xebff4000
│ │  	b.n	3ec43e <uniffi_pbcli_checksum_method_api_base@@Base+0x27fbba>
│ │  	movs	r0, r0
│ │  	b.n	3ec7a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x27ff1e>
│ │  	ands	r1, r0
│ │  	asrs	r0, r0, #12
│ │  	vpmin.u<illegal width 64>	q15, q14, <illegal reg q15.5>
│ │ -	str	r7, [sp, #196]	@ 0xc4
│ │ +	str	r7, [sp, #352]	@ 0x160
│ │  	vmul.f<illegal width 8>	<illegal reg q14.5>, q13, d1[4]
│ │ -	vabdl.u8	<illegal reg q12.5>, d8, d5
│ │ +	vabdl.u8	<illegal reg q12.5>, d8, d28
│ │  			@ <UNDEFINED> instruction: 0xffcad9b5
│ │  	vrsubhn.i16	d17, q12, q12
│ │  	movs	r7, r1
│ │  	asrs	r0, r1, #27
│ │  	movs	r7, r1
│ │  	asrs	r4, r6, #25
│ │  	movs	r7, r1
│ │ @@ -1178201,24 +1178201,24 @@
│ │  	ands	r0, r0
│ │  	b.n	3ecc2e <uniffi_pbcli_checksum_method_api_base@@Base+0x2803aa>
│ │  	add	r2, sp, #900	@ 0x384
│ │  			@ <UNDEFINED> instruction: 0xebfb0004
│ │  	b.n	3ec836 <uniffi_pbcli_checksum_method_api_base@@Base+0x27ffb2>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r4, r6, r7, r9, sp}
│ │ -			@ <UNDEFINED> instruction: 0xffc99b60
│ │ -	vshr.u8	d18, d18, #6
│ │ +			@ <UNDEFINED> instruction: 0xffc99b87
│ │ +	vshr.u8	q9, <illegal reg q4.5>, #6
│ │  			@ <UNDEFINED> instruction: 0xffcb3f27
│ │ -	vqrdmulh.s<illegal width 8>	q10, q5, d0[5]
│ │ -	vmla.i<illegal width 8>	<illegal reg q13.5>, <illegal reg q5.5>, d0[3]
│ │ -	vmla.i<illegal width 8>	<illegal reg q12.5>, q13, d2[7]
│ │ +			@ <UNDEFINED> instruction: 0xffca4d8b
│ │ +	vshr.u8	<illegal reg q13.5>, <illegal reg q9.5>, #5
│ │ +	vsra.u8	d25, d5, #6
│ │  	vqshlu.s64	d18, d14, #11
│ │ -			@ <UNDEFINED> instruction: 0xffca0899
│ │ +	vmul.i<illegal width 8>	q8, q13, d0[0]
│ │  			@ <UNDEFINED> instruction: 0xffcb1dd7
│ │ -	vsli.64	<illegal reg q8.5>, <illegal reg q6.5>, #9
│ │ +	vrsubhn.i16	d17, <illegal reg q4.5>, q2
│ │  	vaddl.u8	q8, d11, d4
│ │  	b.n	3ec068 <uniffi_pbcli_checksum_method_api_base@@Base+0x27f7e4>
│ │  	movs	r0, r0
│ │  	b.n	3ec64c <uniffi_pbcli_checksum_method_api_base@@Base+0x27fdc8>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	adds	r7, #164	@ 0xa4
│ │  	movs	r6, r1
│ │ @@ -1178439,27 +1178439,27 @@
│ │  			@ <UNDEFINED> instruction: 0xebfb0004
│ │  	b.n	3eca56 <uniffi_pbcli_checksum_method_api_base@@Base+0x2801d2>
│ │  	beq.n	3ec738 <uniffi_pbcli_checksum_method_api_base@@Base+0x27feb4>
│ │  	b.n	3ecbb0 <uniffi_pbcli_checksum_method_api_base@@Base+0x28032c>
│ │  	ldrh	r0, [r6, #34]	@ 0x22
│ │  	ldmia.w	sp!, {r1, r2, r4, r6, r8, fp, ip, sp}
│ │  	vmull.u8	<illegal reg q8.5>, d10, d23
│ │ -			@ <UNDEFINED> instruction: 0xffc98fa2
│ │ +	vqrdmlsh.s<illegal width 8>	q12, <illegal reg q12.5>, d1[2]
│ │  	vsubw.u8	<illegal reg q15.5>, q5, d11
│ │  	vmull.u8	<illegal reg q8.5>, d9, d11
│ │ -			@ <UNDEFINED> instruction: 0xffc98f86
│ │ +			@ <UNDEFINED> instruction: 0xffc98fad
│ │  	vmull.u<illegal width 8>	q8, d10, d2[0]
│ │  			@ <UNDEFINED> instruction: 0xffc91bef
│ │ -	vqrdmlsh.s<illegal width 8>	q12, <illegal reg q4.5>, d2[6]
│ │ +			@ <UNDEFINED> instruction: 0xffc98f91
│ │  	vqrdmulh.s<illegal width 8>	<illegal reg q13.5>, q13, d3[0]
│ │  			@ <UNDEFINED> instruction: 0xffc81bd3
│ │ -	vqrdmlsh.s<illegal width 8>	q12, <illegal reg q4.5>, d2[3]
│ │ -	vqrdmulh.s<illegal width 8>	q13, q13, d0[4]
│ │ +			@ <UNDEFINED> instruction: 0xffc98f75
│ │ +	vmull.p8	q13, d10, d7
│ │  			@ <UNDEFINED> instruction: 0xffca1bb7
│ │ -			@ <UNDEFINED> instruction: 0xffc98f32
│ │ +			@ <UNDEFINED> instruction: 0xffc98f59
│ │  	vaddl.u8	q8, d10, d4
│ │  	b.n	3ec29c <uniffi_pbcli_checksum_method_api_base@@Base+0x27fa18>
│ │  	movs	r0, r0
│ │  	b.n	3ec880 <uniffi_pbcli_checksum_method_api_base@@Base+0x27fffc>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	adds	r6, #136	@ 0x88
│ │  	movs	r6, r1
│ │ @@ -1179643,29 +1179643,29 @@
│ │  	b.n	3ecd00 <uniffi_pbcli_checksum_method_api_base@@Base+0x28047c>
│ │  	movs	r0, r0
│ │  	b.n	3ed2e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x280a60>
│ │  	movs	r0, #2
│ │  	b.n	3ed2e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x280a64>
│ │  	vpmin.u<illegal width 64>	q15, <illegal reg q15.5>, <illegal reg q15.5>
│ │  	asrs	r3, r3, #12
│ │ -			@ <UNDEFINED> instruction: 0xffc90b40
│ │ +			@ <UNDEFINED> instruction: 0xffc90b67
│ │  	vmlal.u<illegal width 8>	<illegal reg q8.5>, d27, d3[4]
│ │ -			@ <UNDEFINED> instruction: 0xffc90b08
│ │ +			@ <UNDEFINED> instruction: 0xffc90b2f
│ │  	vsra.u64	d17, d19, #53
│ │ -			@ <UNDEFINED> instruction: 0xffc909d8
│ │ +			@ <UNDEFINED> instruction: 0xffc909ff
│ │  	vsra.u64	<illegal reg q8.5>, <illegal reg q15.5>, #53
│ │ -	vmlsl.u8	q8, d9, d20
│ │ +	vmull.u<illegal width 8>	q8, d9, d3[2]
│ │  	vmla.i<illegal width 8>	<illegal reg q8.5>, <illegal reg q13.5>, d3[5]
│ │ -			@ <UNDEFINED> instruction: 0xffc9090c
│ │ +	vqshrn.u16	d16, <illegal reg q9.5>, #7
│ │  	vsra.u8	<illegal reg q8.5>, <illegal reg q1.5>, #5
│ │ -	vqrshrn.u16	d16, q12, #7
│ │ +			@ <UNDEFINED> instruction: 0xffc9099f
│ │  	vaddw.u8	<illegal reg q8.5>, <illegal reg q5.5>, d23
│ │ -	vmul.f<illegal width 8>	q8, <illegal reg q4.5>, d0[3]
│ │ +	vqrshrn.u16	d16, <illegal reg q9.5>, #7
│ │  	vrshr.u8	d17, d23, #5
│ │ -			@ <UNDEFINED> instruction: 0xffc90a5c
│ │ +	vmlsl.u8	q8, d25, d3
│ │  			@ <UNDEFINED> instruction: 0xffcb4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3ed730 <uniffi_pbcli_checksum_method_api_base@@Base+0x280eac>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3ed55a <uniffi_pbcli_checksum_method_api_base@@Base+0x280cd6>
│ │  	lsls	r0, r2, #1
│ │  	b.n	3ecdbe <uniffi_pbcli_checksum_method_api_base@@Base+0x28053a>
│ │ @@ -1179840,19 +1179840,19 @@
│ │  			@ <UNDEFINED> instruction: 0xebfb0006
│ │  	b.n	3ed6ca <uniffi_pbcli_checksum_method_api_base@@Base+0x280e46>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3edad2 <uniffi_pbcli_checksum_method_api_base@@Base+0x28124e>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, r1, r4, r5, r6, ip}
│ │ -			@ <UNDEFINED> instruction: 0xffc908b8
│ │ +			@ <UNDEFINED> instruction: 0xffc908df
│ │  	vaddl.u8	<illegal reg q8.5>, d11, d31
│ │ -	vqrshrun.s16	d16, q10, #7
│ │ +			@ <UNDEFINED> instruction: 0xffc9089b
│ │  	vqrdmlsh.s<illegal width 8>	q8, <illegal reg q5.5>, d3[0]
│ │ -	vabdl.u8	q8, d25, d8
│ │ +	vabdl.u8	q8, d25, d31
│ │  	vqshrun.s16	d20, q8, #5
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3ed8d0 <uniffi_pbcli_checksum_method_api_base@@Base+0x28104c>
│ │  	ands	r2, r0
│ │  	b.n	3ed6fa <uniffi_pbcli_checksum_method_api_base@@Base+0x280e76>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3ed6fe <uniffi_pbcli_checksum_method_api_base@@Base+0x280e7a>
│ │ @@ -1179898,15 +1179898,15 @@
│ │  	b.n	3edb5a <uniffi_pbcli_checksum_method_api_base@@Base+0x2812d6>
│ │  	movs	r0, r0
│ │  	b.n	3ecf26 <uniffi_pbcli_checksum_method_api_base@@Base+0x2806a2>
│ │  	movs	r1, r0
│ │  	b.n	3edb62 <uniffi_pbcli_checksum_method_api_base@@Base+0x2812de>
│ │  	ldrh	r0, [r6, #0]
│ │  	ldmia.w	sp!, {r0, r1, r6, r7, r9, sl, fp}
│ │ -	vqrshrn.u16	d23, q6, #7
│ │ +			@ <UNDEFINED> instruction: 0xffc97983
│ │  			@ <UNDEFINED> instruction: 0xffcb4df0
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	3ed950 <uniffi_pbcli_checksum_method_api_base@@Base+0x2810cc>
│ │  	strb	r3, [r0, #0]
│ │  	b.n	3ed77a <uniffi_pbcli_checksum_method_api_base@@Base+0x280ef6>
│ │  	ands	r2, r0
│ │  	b.n	3ed77e <uniffi_pbcli_checksum_method_api_base@@Base+0x280efa>
│ │ @@ -1180015,19 +1180015,19 @@
│ │  	movs	r0, #0
│ │  	b.n	3edc66 <uniffi_pbcli_checksum_method_api_base@@Base+0x2813e2>
│ │  	add	r6, pc, #844	@ (adr r6, 3ed874 <uniffi_pbcli_checksum_method_api_base@@Base+0x280ff0>)
│ │  			@ <UNDEFINED> instruction: 0xebfb0004
│ │  	b.n	3ed86e <uniffi_pbcli_checksum_method_api_base@@Base+0x280fea>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │  	ldmia.w	sp!, {r0, r1, r3, r4, r5, r9, sl, fp}
│ │ -			@ <UNDEFINED> instruction: 0xffc978f5
│ │ +	vqshrn.u16	d23, q6, #7
│ │  			@ <UNDEFINED> instruction: 0xffcb0dfb
│ │ -			@ <UNDEFINED> instruction: 0xffc978b5
│ │ +			@ <UNDEFINED> instruction: 0xffc978dc
│ │  			@ <UNDEFINED> instruction: 0xffcb0d9f
│ │ -	vqrshrun.s16	d23, <illegal reg q4.5>, #7
│ │ +	vmlal.u8	<illegal reg q11.5>, d25, d0
│ │  			@ <UNDEFINED> instruction: 0xffcb48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3eda6c <uniffi_pbcli_checksum_method_api_base@@Base+0x2811e8>
│ │  	str	r1, [r0, r0]
│ │  	b.n	3ed896 <uniffi_pbcli_checksum_method_api_base@@Base+0x281012>
│ │  	asrs	r0, r3, #7
│ │  	b.n	3ed098 <uniffi_pbcli_checksum_method_api_base@@Base+0x280814>
│ │ @@ -1180238,21 +1180238,21 @@
│ │  	b.n	3ede66 <uniffi_pbcli_checksum_method_api_base@@Base+0x2815e2>
│ │  	str	r0, [r0, r0]
│ │  	b.n	3ede6a <uniffi_pbcli_checksum_method_api_base@@Base+0x2815e6>
│ │  	add	r6, pc, #328	@ (adr r6, 3ed874 <uniffi_pbcli_checksum_method_api_base@@Base+0x280ff0>)
│ │  			@ <UNDEFINED> instruction: 0xebfb0005
│ │  	b.n	3eda72 <uniffi_pbcli_checksum_method_api_base@@Base+0x2811ee>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r7, r8, r9, sl, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r5, r7, r8, r9, sl, ip, sp, lr, pc}
│ │  	vqshrn.u16	d18, q13, #6
│ │  	vmlal.u<illegal width 8>	<illegal reg q13.5>, d26, d3[3]
│ │  	vrsra.u64	<illegal reg q14.5>, <illegal reg q14.5>, #56
│ │ -			@ <UNDEFINED> instruction: 0xffc99ddc
│ │ -			@ <UNDEFINED> instruction: 0xffca7e72
│ │ -			@ <UNDEFINED> instruction: 0xffcb98f3
│ │ +	vmull.p8	<illegal reg q12.5>, d9, d3
│ │ +			@ <UNDEFINED> instruction: 0xffca7e99
│ │ +	vqshrn.u16	d25, q5, #5
│ │  			@ <UNDEFINED> instruction: 0xffca0b9b
│ │  	vsubw.u8	<illegal reg q15.5>, <illegal reg q12.5>, d25
│ │  			@ <UNDEFINED> instruction: 0xffc84c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3edc7c <uniffi_pbcli_checksum_method_api_base@@Base+0x2813f8>
│ │  	movs	r0, r2
│ │  	b.n	3ede0a <uniffi_pbcli_checksum_method_api_base@@Base+0x281586>
│ │ @@ -1180494,16 +1180494,16 @@
│ │  	movs	r0, r0
│ │  	b.n	3ee0aa <uniffi_pbcli_checksum_method_api_base@@Base+0x281826>
│ │  	movs	r0, r0
│ │  	b.n	3ed47e <uniffi_pbcli_checksum_method_api_base@@Base+0x280bfa>
│ │  	movs	r6, r0
│ │  	b.n	3edcb2 <uniffi_pbcli_checksum_method_api_base@@Base+0x28142e>
│ │  	ldrh	r0, [r6, #46]	@ 0x2e
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r6, r7, r8, sl, fp, ip, sp, pc}
│ │ -	vrsubhn.i16	d20, q5, <illegal reg q1.5>
│ │ +	ldmia.w	sp!, {r2, r3, r4, r9, sl, fp, ip, sp, pc}
│ │ +	vrsubhn.i16	d20, q5, q13
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3edcc6 <uniffi_pbcli_checksum_method_api_base@@Base+0x281442>
│ │  	adds	r0, #0
│ │  	b.n	3ed4ac <uniffi_pbcli_checksum_method_api_base@@Base+0x280c28>
│ │  	asrs	r3, r0, #32
│ │  	b.n	3eda32 <uniffi_pbcli_checksum_method_api_base@@Base+0x2811ae>
│ │ @@ -1180609,19 +1180609,19 @@
│ │  	b.n	3ee1ae <uniffi_pbcli_checksum_method_api_base@@Base+0x28192a>
│ │  	movs	r0, #0
│ │  	b.n	3ee1b2 <uniffi_pbcli_checksum_method_api_base@@Base+0x28192e>
│ │  	add	r5, pc, #512	@ (adr r5, 3edc74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2813f0>)
│ │  			@ <UNDEFINED> instruction: 0xebfb0004
│ │  	b.n	3eddba <uniffi_pbcli_checksum_method_api_base@@Base+0x281536>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r3, r8, sl, fp, ip, sp, pc}
│ │ +	ldmia.w	sp!, {r4, r5, r8, sl, fp, ip, sp, pc}
│ │  	vqshlu.s64	<illegal reg q9.5>, <illegal reg q11.5>, #10
│ │ -			@ <UNDEFINED> instruction: 0xffcabcd9
│ │ +			@ <UNDEFINED> instruction: 0xffcabd00
│ │  	vmlsl.u<illegal width 8>	<illegal reg q9.5>, d26, d3[1]
│ │ -			@ <UNDEFINED> instruction: 0xffcabcbd
│ │ +	vqdmulh.s<illegal width 8>	<illegal reg q13.5>, q13, d0[5]
│ │  	vrsubhn.i16	d19, q13, <illegal reg q13.5>
│ │  			@ <UNDEFINED> instruction: 0xffca4c70
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3edfb8 <uniffi_pbcli_checksum_method_api_base@@Base+0x281734>
│ │  	beq.n	3edad0 <uniffi_pbcli_checksum_method_api_base@@Base+0x28124c>
│ │  	b.n	3edf3c <uniffi_pbcli_checksum_method_api_base@@Base+0x2816b8>
│ │  	b.n	3edacc <uniffi_pbcli_checksum_method_api_base@@Base+0x281248>
│ │ @@ -1181089,35 +1181089,35 @@
│ │  	b.n	3ed9dc <uniffi_pbcli_checksum_method_api_base@@Base+0x281158>
│ │  	movs	r0, r0
│ │  	b.n	3edfc0 <uniffi_pbcli_checksum_method_api_base@@Base+0x28173c>
│ │  	movs	r0, #2
│ │  	b.n	3edfc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x281740>
│ │  	vpmin.u32	q15, <illegal reg q12.5>, <illegal reg q15.5>
│ │  	asrs	r1, r7, #3
│ │ -	vmlal.u<illegal width 8>	q10, d25, d0[2]
│ │ -			@ <UNDEFINED> instruction: 0xffcb8e3e
│ │ -	vsubl.u8	q10, d26, d28
│ │ -	vmull.p8	q12, d11, d18
│ │ -	vaddw.u8	q10, q13, d0
│ │ -			@ <UNDEFINED> instruction: 0xffcb8cf6
│ │ -	vshr.u64	<illegal reg q15.5>, <illegal reg q6.5>, #54
│ │ -	vsubl.u8	q10, d26, d0
│ │ -			@ <UNDEFINED> instruction: 0xffcb8df6
│ │ -	vrshr.u64	q10, q10, #54
│ │ -	vqrdmlah.s<illegal width 8>	q12, <illegal reg q5.5>, d2[6]
│ │ +	vmlal.u<illegal width 8>	q10, d25, d3[7]
│ │ +	vqrdmlah.s<illegal width 8>	q12, <illegal reg q5.5>, d1[5]
│ │ +	vrshr.u64	q10, <illegal reg q1.5>, #54
│ │ +	vqrdmlah.s<illegal width 8>	q12, <illegal reg q5.5>, d1[2]
│ │ +	vaddw.u8	q10, q13, d23
│ │ +			@ <UNDEFINED> instruction: 0xffcb8d1d
│ │ +	vaddw.u8	<illegal reg q15.5>, q5, d4
│ │ +	vsubl.u8	q10, d26, d23
│ │ +			@ <UNDEFINED> instruction: 0xffcb8e1d
│ │ +	vrsra.u8	d20, d11, #6
│ │ +			@ <UNDEFINED> instruction: 0xffcb8e91
│ │  			@ <UNDEFINED> instruction: 0xffca0e30
│ │ -	vsra.u64	d20, d12, #54
│ │ -			@ <UNDEFINED> instruction: 0xffcb8d12
│ │ -	vmla.f<illegal width 8>	q10, q13, d0[2]
│ │ -			@ <UNDEFINED> instruction: 0xffcb8d3e
│ │ +	vmla.f<illegal width 8>	q10, q13, d3[0]
│ │ +			@ <UNDEFINED> instruction: 0xffcb8d39
│ │ +	vmla.f<illegal width 8>	q10, q13, d3[7]
│ │ +	vqrdmulh.s<illegal width 8>	q12, <illegal reg q5.5>, d1[5]
│ │  	vqdmulh.s<illegal width 8>	<illegal reg q9.5>, q5, d2[4]
│ │ -	vshr.u64	q10, q6, #55
│ │ -			@ <UNDEFINED> instruction: 0xffcb8c52
│ │ -	vaddl.u8	q10, d26, d16
│ │ -			@ <UNDEFINED> instruction: 0xffcb8c16
│ │ +	vaddw.u8	q10, <illegal reg q4.5>, d3
│ │ +			@ <UNDEFINED> instruction: 0xffcb8c79
│ │ +	vmla.i<illegal width 8>	q10, q13, d3[1]
│ │ +			@ <UNDEFINED> instruction: 0xffcb8c3d
│ │  			@ <UNDEFINED> instruction: 0xffca48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3ee424 <uniffi_pbcli_checksum_method_api_base@@Base+0x281ba0>
│ │  	str	r1, [r0, r0]
│ │  	b.n	3ee24e <uniffi_pbcli_checksum_method_api_base@@Base+0x2819ca>
│ │  	asrs	r0, r5, #12
│ │  	b.n	3eda50 <uniffi_pbcli_checksum_method_api_base@@Base+0x2811cc>
│ │ @@ -1181481,41 +1181481,41 @@
│ │  	add	r3, pc, #584	@ (adr r3, 3ee474 <uniffi_pbcli_checksum_method_api_base@@Base+0x281bf0>)
│ │  			@ <UNDEFINED> instruction: 0xebfb0005
│ │  	b.n	3ee572 <uniffi_pbcli_checksum_method_api_base@@Base+0x281cee>
│ │  	ldrh	r0, [r6, #6]
│ │  	ldmia.w	sp!, {}
│ │  	b.n	3ee97a <uniffi_pbcli_checksum_method_api_base@@Base+0x2820f6>
│ │  	ldrh	r0, [r6, #6]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r6, r7, r8, sl, fp, sp, lr, pc}
│ │ -			@ <UNDEFINED> instruction: 0xffca3f7c
│ │ -	vrsubhn.i16	d23, <illegal reg q13.5>, <illegal reg q2.5>
│ │ +	ldmia.w	sp!, {r2, r4, r5, r6, r7, r8, sl, fp, sp, lr, pc}
│ │ +			@ <UNDEFINED> instruction: 0xffca3fa3
│ │ +	vrsubhn.i16	d23, <illegal reg q13.5>, q14
│ │  	vshr.u64	d16, d16, #54
│ │ -			@ <UNDEFINED> instruction: 0xffc93ed4
│ │ -	vsli.64	<illegal reg q11.5>, <illegal reg q6.5>, #11
│ │ +			@ <UNDEFINED> instruction: 0xffc93efb
│ │ +	vrsubhn.i16	d23, <illegal reg q5.5>, q2
│ │  	vqshrn.u16	d26, <illegal reg q3.5>, #6
│ │ -			@ <UNDEFINED> instruction: 0xffc83f98
│ │ -	vrsubhn.i16	d23, <illegal reg q13.5>, <illegal reg q8.5>
│ │ -	vqrdmulh.s<illegal width 8>	<illegal reg q9.5>, q5, d0[6]
│ │ -	vsri.8	<illegal reg q11.5>, <illegal reg q8.5>, #5
│ │ +			@ <UNDEFINED> instruction: 0xffc83fbf
│ │ +	vmlsl.u<illegal width 8>	<illegal reg q11.5>, d27, d0[2]
│ │ +			@ <UNDEFINED> instruction: 0xffca3d8f
│ │ +	vsri.64	d23, d8, #53
│ │  			@ <UNDEFINED> instruction: 0xffcac9f5
│ │ -			@ <UNDEFINED> instruction: 0xffc93f00
│ │ -	vrsubhn.i16	d23, <illegal reg q5.5>, <illegal reg q4.5>
│ │ -			@ <UNDEFINED> instruction: 0xffca3d30
│ │ -	vsri.8	d23, d25, #5
│ │ -	vsri.8	d23, d22, #6
│ │ -	vqrdmulh.s<illegal width 8>	<illegal reg q9.5>, <illegal reg q13.5>, d0[3]
│ │ -	vsri.64	<illegal reg q11.5>, <illegal reg q2.5>, #53
│ │ +			@ <UNDEFINED> instruction: 0xffc93f27
│ │ +	vqshlu.s8	d23, d16, #3
│ │ +			@ <UNDEFINED> instruction: 0xffca3d57
│ │ +	vmls.i<illegal width 8>	<illegal reg q11.5>, <illegal reg q5.5>, d0[4]
│ │ +	vsri.8	<illegal reg q11.5>, <illegal reg q6.5>, #6
│ │ +			@ <UNDEFINED> instruction: 0xffcb3df3
│ │ +	vsri.64	<illegal reg q11.5>, q14, #53
│ │  	vshr.u64	<illegal reg q10.5>, q14, #54
│ │ -			@ <UNDEFINED> instruction: 0xffca3d84
│ │ -	vraddhn.i16	d23, <illegal reg q13.5>, <illegal reg q6.5>
│ │ +			@ <UNDEFINED> instruction: 0xffca3dab
│ │ +	vsri.64	d23, d20, #53
│ │  			@ <UNDEFINED> instruction: 0xffca0b95
│ │ -			@ <UNDEFINED> instruction: 0xffc93db0
│ │ -	vsri.64	d23, d25, #53
│ │ -	vqrdmulh.s<illegal width 8>	<illegal reg q9.5>, q5, d0[3]
│ │ -	vsri.8	<illegal reg q11.5>, <illegal reg q2.5>, #5
│ │ +			@ <UNDEFINED> instruction: 0xffc93dd7
│ │ +	vmls.i<illegal width 8>	<illegal reg q11.5>, <illegal reg q13.5>, d0[4]
│ │ +			@ <UNDEFINED> instruction: 0xffca3d73
│ │ +	vsri.8	<illegal reg q11.5>, q14, #5
│ │  			@ <UNDEFINED> instruction: 0xffca4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3ee7cc <uniffi_pbcli_checksum_method_api_base@@Base+0x281f48>
│ │  	beq.n	3ee2d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x281a50>
│ │  	b.n	3ee750 <uniffi_pbcli_checksum_method_api_base@@Base+0x281ecc>
│ │  	stmia	r0!, {r3}
│ │  	b.n	3eddf0 <uniffi_pbcli_checksum_method_api_base@@Base+0x28156c>
│ │ @@ -1181655,18 +1181655,18 @@
│ │  	b.n	3eeb22 <uniffi_pbcli_checksum_method_api_base@@Base+0x28229e>
│ │  	add	r3, pc, #144	@ (adr r3, 3ee474 <uniffi_pbcli_checksum_method_api_base@@Base+0x281bf0>)
│ │  			@ <UNDEFINED> instruction: 0xebfb0000
│ │  	b.n	3eeb2a <uniffi_pbcli_checksum_method_api_base@@Base+0x2822a6>
│ │  	beq.n	3ee424 <uniffi_pbcli_checksum_method_api_base@@Base+0x281ba0>
│ │  	b.n	3ee884 <uniffi_pbcli_checksum_method_api_base@@Base+0x282000>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r2, r3, r4, r7, r8, r9, fp, ip, sp}
│ │ -			@ <UNDEFINED> instruction: 0xffcb69dc
│ │ -			@ <UNDEFINED> instruction: 0xffcb3b74
│ │ -			@ <UNDEFINED> instruction: 0xffcb69b4
│ │ +	ldmia.w	sp!, {r0, r1, r6, r7, r8, r9, fp, ip, sp}
│ │ +	vmlsl.u8	q11, d11, d3
│ │ +			@ <UNDEFINED> instruction: 0xffcb3b9b
│ │ +			@ <UNDEFINED> instruction: 0xffcb69db
│ │  			@ <UNDEFINED> instruction: 0xffcb4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3ee924 <uniffi_pbcli_checksum_method_api_base@@Base+0x2820a0>
│ │  	beq.n	3ee42c <uniffi_pbcli_checksum_method_api_base@@Base+0x281ba8>
│ │  	b.n	3ee8a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x282024>
│ │  	stmia	r0!, {r3}
│ │  	b.n	3edf48 <uniffi_pbcli_checksum_method_api_base@@Base+0x2816c4>
│ │ @@ -1181734,15 +1181734,15 @@
│ │  	b.n	3eebde <uniffi_pbcli_checksum_method_api_base@@Base+0x28235a>
│ │  	add	r2, pc, #980	@ (adr r2, 3ee874 <uniffi_pbcli_checksum_method_api_base@@Base+0x281ff0>)
│ │  			@ <UNDEFINED> instruction: 0xebfb0005
│ │  	b.n	3ee7e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x281f62>
│ │  	beq.n	3ee4b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x281c34>
│ │  	b.n	3ee940 <uniffi_pbcli_checksum_method_api_base@@Base+0x2820bc>
│ │  	ldrh	r0, [r6, #0]
│ │ -	ldmia.w	sp!, {r2, r3, r4, r5, r7, r9, fp, ip, sp}
│ │ +	ldmia.w	sp!, {r0, r1, r5, r6, r7, r9, fp, ip, sp}
│ │  	vsli.8	<illegal reg q11.5>, <illegal reg q0.5>, #3
│ │  			@ <UNDEFINED> instruction: 0xffc94ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3ee9d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x282154>
│ │  	beq.n	3ee4d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x281c54>
│ │  	b.n	3ee95c <uniffi_pbcli_checksum_method_api_base@@Base+0x2820d8>
│ │  	str	r1, [r0, #0]
│ │ @@ -1182222,15 +1182222,15 @@
│ │  	str	r0, [sp, #0]
│ │  	add	r5, pc, #544	@ (adr r5, 3eeadc <uniffi_pbcli_checksum_method_api_base@@Base+0x282258>)
│ │  	movs	r4, r0
│ │  	b.n	3eec02 <uniffi_pbcli_checksum_method_api_base@@Base+0x28237e>
│ │  	beq.n	3ee8f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x282070>
│ │  	b.n	3eed5c <uniffi_pbcli_checksum_method_api_base@@Base+0x2824d8>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r3, r6, r7, r9, sl, ip, sp}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r5, r6, r7, r9, sl, ip, sp}
│ │  			@ <UNDEFINED> instruction: 0xffcb7b58
│ │  	vmlal.u8	q10, d11, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3eec1a <uniffi_pbcli_checksum_method_api_base@@Base+0x282396>
│ │  	adds	r0, #0
│ │  	b.n	3ee47e <uniffi_pbcli_checksum_method_api_base@@Base+0x281bfa>
│ │  	stmia	r0!, {}
│ │ @@ -1182600,17 +1182600,17 @@
│ │  	b.n	3ef352 <uniffi_pbcli_checksum_method_api_base@@Base+0x282ace>
│ │  	add	r1, pc, #96	@ (adr r1, 3eec74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2823f0>)
│ │  			@ <UNDEFINED> instruction: 0xebfb0000
│ │  	b.n	3ef35a <uniffi_pbcli_checksum_method_api_base@@Base+0x282ad6>
│ │  	beq.n	3eec54 <uniffi_pbcli_checksum_method_api_base@@Base+0x2823d0>
│ │  	b.n	3ef0b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x282830>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r4, r5, r6, r9, sl}
│ │ +	ldmia.w	sp!, {r3, r4, r7, r9, sl}
│ │  			@ <UNDEFINED> instruction: 0xffcb0e9c
│ │ -	vsli.64	q8, <illegal reg q4.5>, #10
│ │ +	vrsubhn.i16	d16, q5, q0
│ │  	vmull.p8	q8, d11, d4
│ │  			@ <UNDEFINED> instruction: 0xffca4c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3ef154 <uniffi_pbcli_checksum_method_api_base@@Base+0x2828d0>
│ │  	beq.n	3eec5c <uniffi_pbcli_checksum_method_api_base@@Base+0x2823d8>
│ │  	b.n	3ef0d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x282854>
│ │  	stmia	r0!, {r3}
│ │ @@ -1183083,15 +1183083,15 @@
│ │  	b.n	3ef7c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x282f42>
│ │  	ldr	r7, [sp, #1004]	@ 0x3ec
│ │  			@ <UNDEFINED> instruction: 0xebfb0007
│ │  	b.n	3ef3ce <uniffi_pbcli_checksum_method_api_base@@Base+0x282b4a>
│ │  	beq.n	3ef0c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x282844>
│ │  	b.n	3ef528 <uniffi_pbcli_checksum_method_api_base@@Base+0x282ca4>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r3, r5, r6, r8}
│ │ +	ldmia.w	sp!, {r4, r7, r8}
│ │  	vmla.i<illegal width 8>	<illegal reg q13.5>, <illegal reg q13.5>, d1[5]
│ │  			@ <UNDEFINED> instruction: 0xffc94ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3ef5c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x282d3c>
│ │  	beq.n	3ef0c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x28283c>
│ │  	b.n	3ef544 <uniffi_pbcli_checksum_method_api_base@@Base+0x282cc0>
│ │  	str	r1, [r0, #0]
│ │ @@ -1183474,15 +1183474,15 @@
│ │  	b.n	3efb36 <uniffi_pbcli_checksum_method_api_base@@Base+0x2832b2>
│ │  	ldr	r7, [sp, #124]	@ 0x7c
│ │  			@ <UNDEFINED> instruction: 0xebfb0006
│ │  	b.n	3ef73e <uniffi_pbcli_checksum_method_api_base@@Base+0x282eba>
│ │  	beq.n	3ef438 <uniffi_pbcli_checksum_method_api_base@@Base+0x282bb4>
│ │  	b.n	3ef898 <uniffi_pbcli_checksum_method_api_base@@Base+0x283014>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r0, r3, r4, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r5, r9, sl, fp, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcaee39
│ │  			@ <UNDEFINED> instruction: 0xffc94c10
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	3ef930 <uniffi_pbcli_checksum_method_api_base@@Base+0x2830ac>
│ │  	beq.n	3ef428 <uniffi_pbcli_checksum_method_api_base@@Base+0x282ba4>
│ │  	b.n	3ef8b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x283030>
│ │  	ands	r4, r1
│ │ @@ -1183554,17 +1183554,17 @@
│ │  	b.n	3efbee <uniffi_pbcli_checksum_method_api_base@@Base+0x28336a>
│ │  	ldr	r6, [sp, #964]	@ 0x3c4
│ │  			@ <UNDEFINED> instruction: 0xebfb0004
│ │  	b.n	3ef7f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x282f72>
│ │  	beq.n	3ef4c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x282c44>
│ │  	b.n	3ef950 <uniffi_pbcli_checksum_method_api_base@@Base+0x2830cc>
│ │  	ldrh	r0, [r2, #32]
│ │ -	ldmia.w	sp!, {r0, r2, r4, r7, r8, sl, fp, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r5, r7, r8, sl, fp, ip, sp, lr, pc}
│ │  	vabal.u8	q11, d26, d28
│ │ -	vqrdmulh.s<illegal width 8>	<illegal reg q15.5>, <illegal reg q4.5>, d1[0]
│ │ +	vqrdmulh.s<illegal width 8>	<illegal reg q15.5>, <illegal reg q4.5>, d0[6]
│ │  	vsli.8	q11, q4, #2
│ │  			@ <UNDEFINED> instruction: 0xffc94ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3ef9f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x28316c>
│ │  	beq.n	3ef500 <uniffi_pbcli_checksum_method_api_base@@Base+0x282c7c>
│ │  	b.n	3ef974 <uniffi_pbcli_checksum_method_api_base@@Base+0x2830f0>
│ │  	str	r0, [r0, r0]
│ │ @@ -1184014,16 +1184014,16 @@
│ │  	vpmin.u16	<illegal reg q0.5>, <illegal reg q12.5>, <illegal reg q15.5>
│ │  	movs	r6, r0
│ │  	b.n	3efbea <uniffi_pbcli_checksum_method_api_base@@Base+0x283366>
│ │  	asrs	r4, r0, #32
│ │  	b.n	3efbee <uniffi_pbcli_checksum_method_api_base@@Base+0x28336a>
│ │  	strh	r2, [r4, #12]
│ │  			@ <UNDEFINED> instruction: 0xebfcff15
│ │ -			@ <UNDEFINED> instruction: 0xeafffad9
│ │ -	vmla.f<illegal width 8>	<illegal reg q8.5>, q13, d2[6]
│ │ +			@ <UNDEFINED> instruction: 0xeafffb00
│ │ +	vrshr.u8	d17, d1, #6
│ │  			@ <UNDEFINED> instruction: 0xffcb48f0
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	3efde0 <uniffi_pbcli_checksum_method_api_base@@Base+0x28355c>
│ │  	beq.n	3ef8d8 <uniffi_pbcli_checksum_method_api_base@@Base+0x283054>
│ │  	b.n	3efd64 <uniffi_pbcli_checksum_method_api_base@@Base+0x2834e0>
│ │  	ands	r2, r0
│ │  	b.n	3efc0e <uniffi_pbcli_checksum_method_api_base@@Base+0x28338a>
│ │ @@ -1184128,15 +1184128,15 @@
│ │  	str	r0, [sp, #0]
│ │  	add	r5, pc, #544	@ (adr r5, 3efbc8 <uniffi_pbcli_checksum_method_api_base@@Base+0x283344>)
│ │  	movs	r4, r0
│ │  	b.n	3efcee <uniffi_pbcli_checksum_method_api_base@@Base+0x28346a>
│ │  	beq.n	3ef9e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x28315c>
│ │  	b.n	3efe48 <uniffi_pbcli_checksum_method_api_base@@Base+0x2835c4>
│ │  	ldrh	r0, [r6, #30]
│ │ -	ldmia.w	sp!, {r0, r4, r5, r6, fp, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r3, r4, r7, fp, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffca4765
│ │  	vmlal.u8	q10, d10, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3efd06 <uniffi_pbcli_checksum_method_api_base@@Base+0x283482>
│ │  	asrs	r0, r0, #32
│ │  	b.n	3ef56a <uniffi_pbcli_checksum_method_api_base@@Base+0x282ce6>
│ │  	asrs	r1, r4, #1
│ │ @@ -1186186,15 +1186186,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f1112 <uniffi_pbcli_checksum_method_api_base@@Base+0x28488e>
│ │  	lsrs	r4, r6, #24
│ │  	subs	r0, r0, r0
│ │  	movs	r2, r4
│ │  	b.n	3f11ba <uniffi_pbcli_checksum_method_api_base@@Base+0x284936>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r5, r7, r8, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r6, r7, r8, fp, lr, pc}
│ │  	vaddl.u8	q8, d10, d2
│ │  	b.n	3f0626 <uniffi_pbcli_checksum_method_api_base@@Base+0x283da2>
│ │  	movs	r0, r0
│ │  	b.n	3f112a <uniffi_pbcli_checksum_method_api_base@@Base+0x2848a6>
│ │  	lsrs	r6, r5, #24
│ │  	subs	r0, r0, r0
│ │  	lsls	r7, r5, #1
│ │ @@ -1186252,15 +1186252,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f11a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x28491e>
│ │  	lsrs	r0, r2, #24
│ │  	subs	r0, r0, r0
│ │  	lsls	r6, r5, #2
│ │  	b.n	3f124a <uniffi_pbcli_checksum_method_api_base@@Base+0x2849c6>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r4, r5, r7, r9, fp, ip, sp}
│ │ +	ldmia.w	sp!, {r1, r2, r3, r4, r6, r7, r9, fp, ip, sp}
│ │  	vaddl.u8	<illegal reg q8.5>, d11, d2
│ │  	b.n	3f06b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x283e32>
│ │  	lsls	r7, r5, #1
│ │  	b.n	3f11bc <uniffi_pbcli_checksum_method_api_base@@Base+0x284938>
│ │  	lsrs	r2, r1, #24
│ │  	subs	r0, r0, r0
│ │  	asrs	r3, r0, #32
│ │ @@ -1186644,15 +1186644,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f14d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x284c4e>
│ │  	lsrs	r4, r0, #21
│ │  	subs	r0, r0, r0
│ │  	lsls	r0, r6, #1
│ │  	b.n	3f157a <uniffi_pbcli_checksum_method_api_base@@Base+0x284cf6>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r7, sl, fp, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r5, r7, sl, fp, sp, lr}
│ │  	vaddl.u8	<illegal reg q8.5>, d10, d2
│ │  	b.n	3f09e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x284162>
│ │  	lsls	r4, r4, #1
│ │  	b.n	3f14ec <uniffi_pbcli_checksum_method_api_base@@Base+0x284c68>
│ │  	lsrs	r6, r7, #20
│ │  	subs	r0, r0, r0
│ │  	asrs	r3, r0, #32
│ │ @@ -1186777,15 +1186777,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f15f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x284d72>
│ │  	lsrs	r3, r7, #19
│ │  	subs	r0, r0, r0
│ │  	lsls	r5, r7, #2
│ │  	b.n	3f169e <uniffi_pbcli_checksum_method_api_base@@Base+0x284e1a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r4, r5, r6, r7, r9, sl, ip, lr}
│ │ +	ldmia.w	sp!, {r2, r5, r8, r9, sl, ip, lr}
│ │  	vaddl.u8	<illegal reg q8.5>, d10, d2
│ │  	b.n	3f0b0a <uniffi_pbcli_checksum_method_api_base@@Base+0x284286>
│ │  	lsls	r3, r6, #1
│ │  	b.n	3f1610 <uniffi_pbcli_checksum_method_api_base@@Base+0x284d8c>
│ │  	lsrs	r5, r6, #19
│ │  	subs	r0, r0, r0
│ │  	asrs	r3, r0, #32
│ │ @@ -1186856,15 +1186856,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f169e <uniffi_pbcli_checksum_method_api_base@@Base+0x284e1a>
│ │  	lsrs	r1, r2, #19
│ │  	subs	r0, r0, r0
│ │  	movs	r0, r6
│ │  	b.n	3f1746 <uniffi_pbcli_checksum_method_api_base@@Base+0x284ec2>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r8, r9, sl, ip, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r4, r5, r8, r9, sl, ip, pc}
│ │  	vaddl.u8	<illegal reg q8.5>, d10, d2
│ │  	b.n	3f0bb2 <uniffi_pbcli_checksum_method_api_base@@Base+0x28432e>
│ │  	lsls	r4, r4, #1
│ │  	b.n	3f16b8 <uniffi_pbcli_checksum_method_api_base@@Base+0x284e34>
│ │  	asrs	r3, r0, #32
│ │  	lsls	r0, r2, #23
│ │  	lsls	r0, r5, #1
│ │ @@ -1186959,15 +1186959,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f1776 <uniffi_pbcli_checksum_method_api_base@@Base+0x284ef2>
│ │  	lsrs	r3, r3, #18
│ │  	subs	r0, r0, r0
│ │  	lsls	r7, r6, #1
│ │  	b.n	3f181e <uniffi_pbcli_checksum_method_api_base@@Base+0x284f9a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r8, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r3, r5, r8, ip, sp, lr, pc}
│ │  	vqshl.u64	d24, d31, #10
│ │  	vaddl.u8	<illegal reg q8.5>, d9, d2
│ │  	b.n	3f0c8e <uniffi_pbcli_checksum_method_api_base@@Base+0x28440a>
│ │  	lsls	r4, r6, #1
│ │  	b.n	3f1794 <uniffi_pbcli_checksum_method_api_base@@Base+0x284f10>
│ │  	lsls	r7, r1, #17
│ │  	lsrs	r0, r0, #8
│ │ @@ -1187031,15 +1187031,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f1812 <uniffi_pbcli_checksum_method_api_base@@Base+0x284f8e>
│ │  	lsrs	r4, r6, #17
│ │  	subs	r0, r0, r0
│ │  	lsrs	r1, r2, #29
│ │  	b.n	3f18ba <uniffi_pbcli_checksum_method_api_base@@Base+0x285036>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r6, ip, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r7, ip, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffca2fd8
│ │  	b.n	3f0cc4 <uniffi_pbcli_checksum_method_api_base@@Base+0x284440>
│ │  	asrs	r2, r0, #32
│ │  	b.n	3f168a <uniffi_pbcli_checksum_method_api_base@@Base+0x284e06>
│ │  	movs	r0, #2
│ │  	b.n	3f12ac <uniffi_pbcli_checksum_method_api_base@@Base+0x284a28>
│ │  	movs	r2, r0
│ │ @@ -1187297,15 +1187297,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f1a52 <uniffi_pbcli_checksum_method_api_base@@Base+0x2851ce>
│ │  	lsrs	r4, r4, #15
│ │  	subs	r0, r0, r0
│ │  	movs	r3, r4
│ │  	b.n	3f1afa <uniffi_pbcli_checksum_method_api_base@@Base+0x285276>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r2, r4, r9, ip, sp}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r4, r5, r9, ip, sp}
│ │  			@ <UNDEFINED> instruction: 0xffcb2fd0
│ │  	b.n	3f0f04 <uniffi_pbcli_checksum_method_api_base@@Base+0x284680>
│ │  	asrs	r2, r0, #32
│ │  	b.n	3f18ca <uniffi_pbcli_checksum_method_api_base@@Base+0x285046>
│ │  	movs	r0, #2
│ │  	b.n	3f14ec <uniffi_pbcli_checksum_method_api_base@@Base+0x284c68>
│ │  	movs	r2, r0
│ │ @@ -1187327,15 +1187327,15 @@
│ │  	lsrs	r4, r2, #15
│ │  	ldrh	r0, [r0, #16]
│ │  	movs	r0, #8
│ │  	b.n	3f1918 <uniffi_pbcli_checksum_method_api_base@@Base+0x285094>
│ │  	asrs	r1, r0, #4
│ │  	b.n	3f1322 <uniffi_pbcli_checksum_method_api_base@@Base+0x284a9e>
│ │  	blx	7f2504 <uniffi_pbcli_checksum_method_api_base@@Base+0x685c80>
│ │ -	ldr	r1, [pc, #580]	@ (3f1648 <uniffi_pbcli_checksum_method_api_base@@Base+0x284dc4>)
│ │ +	ldr	r1, [pc, #736]	@ (3f16e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x284e60>)
│ │  	vmla.i<illegal width 8>	q8, <illegal reg q5.5>, d0[1]
│ │  	movs	r0, r0
│ │  	cmp	r7, #68	@ 0x44
│ │  	movs	r0, r0
│ │  	cmp	r7, #68	@ 0x44
│ │  	movs	r0, r0
│ │  	asrs	r4, r3, #3
│ │ @@ -1187627,15 +1187627,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f1d12 <uniffi_pbcli_checksum_method_api_base@@Base+0x28548e>
│ │  	lsrs	r4, r6, #12
│ │  	subs	r0, r0, r0
│ │  	lsls	r6, r2, #3
│ │  	b.n	3f1dba <uniffi_pbcli_checksum_method_api_base@@Base+0x285536>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r3, r4, r5, r7, ip, pc}
│ │ +	ldmia.w	sp!, {r0, r5, r6, r7, ip, pc}
│ │  	vaddl.u8	<illegal reg q8.5>, d10, d2
│ │  	b.n	3f1226 <uniffi_pbcli_checksum_method_api_base@@Base+0x2849a2>
│ │  	lsls	r0, r6, #1
│ │  	b.n	3f1d2c <uniffi_pbcli_checksum_method_api_base@@Base+0x2854a8>
│ │  	lsls	r5, r0, #10
│ │  	lsrs	r0, r0, #8
│ │  	lsls	r2, r4, #1
│ │ @@ -1187757,15 +1187757,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f1e2e <uniffi_pbcli_checksum_method_api_base@@Base+0x2855aa>
│ │  	lsrs	r5, r5, #11
│ │  	subs	r0, r0, r0
│ │  	lsls	r5, r5, #4
│ │  	b.n	3f1d96 <uniffi_pbcli_checksum_method_api_base@@Base+0x285512>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r3, r4, r5, r9, sl, fp, sp}
│ │ +	ldmia.w	sp!, {r0, r5, r6, r9, sl, fp, sp}
│ │  	vqrdmlsh.s<illegal width 8>	q9, <illegal reg q13.5>, d0[1]
│ │  	b.n	3f12e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x284a5c>
│ │  	asrs	r2, r0, #32
│ │  	b.n	3f1ca6 <uniffi_pbcli_checksum_method_api_base@@Base+0x285422>
│ │  	movs	r0, #2
│ │  	b.n	3f18c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x285044>
│ │  	movs	r2, r0
│ │ @@ -1187806,15 +1187806,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f1e9e <uniffi_pbcli_checksum_method_api_base@@Base+0x28561a>
│ │  	lsrs	r1, r2, #11
│ │  	subs	r0, r0, r0
│ │  	lsls	r5, r0, #5
│ │  	b.n	3f1e06 <uniffi_pbcli_checksum_method_api_base@@Base+0x285582>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r2, r3, r4, r5, r6, r8, r9, sl, ip}
│ │ +	ldmia.w	sp!, {r0, r1, r5, r7, r8, r9, sl, ip}
│ │  	vmull.u8	q14, d11, d15
│ │  	vaddl.u8	<illegal reg q8.5>, d8, d2
│ │  	b.n	3f13b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x284b32>
│ │  	lsls	r3, r6, #1
│ │  	b.n	3f1ebc <uniffi_pbcli_checksum_method_api_base@@Base+0x285638>
│ │  	lsrs	r2, r1, #11
│ │  	subs	r0, r0, r0
│ │ @@ -1187866,15 +1187866,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f1f22 <uniffi_pbcli_checksum_method_api_base@@Base+0x28569e>
│ │  	lsrs	r0, r6, #10
│ │  	subs	r0, r0, r0
│ │  	lsls	r7, r1, #2
│ │  	b.n	3f1fca <uniffi_pbcli_checksum_method_api_base@@Base+0x285746>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r3, r5, fp, ip, sp, lr}
│ │  	vmla.f<illegal width 8>	<illegal reg q15.5>, q5, d3[6]
│ │  	vaddl.u8	<illegal reg q8.5>, d9, d2
│ │  	b.n	3f143a <uniffi_pbcli_checksum_method_api_base@@Base+0x284bb6>
│ │  	lsls	r3, r6, #1
│ │  	b.n	3f1f40 <uniffi_pbcli_checksum_method_api_base@@Base+0x2856bc>
│ │  	lsrs	r1, r5, #10
│ │  	subs	r0, r0, r0
│ │ @@ -1188008,15 +1188008,15 @@
│ │  	b.n	3f204e <uniffi_pbcli_checksum_method_api_base@@Base+0x2857ca>
│ │  	lsrs	r5, r4, #9
│ │  	subs	r0, r0, r0
│ │  	lsls	r4, r2, #3
│ │  	b.n	3f20f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x285872>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r7, r9, fp, lr, pc}
│ │ -	vqrdmulh.s<illegal width 8>	q12, q4, d1[0]
│ │ +	vqrdmulh.s<illegal width 8>	q12, q4, d0[6]
│ │  	vaddl.u8	<illegal reg q8.5>, d10, d2
│ │  	b.n	3f1566 <uniffi_pbcli_checksum_method_api_base@@Base+0x284ce2>
│ │  	lsls	r3, r6, #1
│ │  	b.n	3f206c <uniffi_pbcli_checksum_method_api_base@@Base+0x2857e8>
│ │  	lsls	r7, r3, #11
│ │  	lsrs	r0, r0, #8
│ │  	lsls	r6, r4, #1
│ │ @@ -1188213,15 +1188213,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f220e <uniffi_pbcli_checksum_method_api_base@@Base+0x28598a>
│ │  	lsrs	r5, r6, #7
│ │  	subs	r0, r0, r0
│ │  	lsls	r0, r5, #1
│ │  	b.n	3f22b6 <uniffi_pbcli_checksum_method_api_base@@Base+0x285a32>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r9, lr}
│ │ +	ldmia.w	sp!, {r2, r4, r5, r9, lr}
│ │  	vaddl.u8	q8, d11, d2
│ │  	b.n	3f1722 <uniffi_pbcli_checksum_method_api_base@@Base+0x284e9e>
│ │  	movs	r0, r0
│ │  	b.n	3f2226 <uniffi_pbcli_checksum_method_api_base@@Base+0x2859a2>
│ │  	lsrs	r7, r5, #7
│ │  	subs	r0, r0, r0
│ │  	lsls	r1, r7, #2
│ │ @@ -1188596,15 +1188596,15 @@
│ │  	b.n	3f2556 <uniffi_pbcli_checksum_method_api_base@@Base+0x285cd2>
│ │  	lsrs	r3, r4, #4
│ │  	subs	r0, r0, r0
│ │  	lsls	r3, r0, #5
│ │  	b.n	3f24be <uniffi_pbcli_checksum_method_api_base@@Base+0x285c3a>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r1, r2, r4, r8, r9}
│ │ -			@ <UNDEFINED> instruction: 0xffc95bf4
│ │ +			@ <UNDEFINED> instruction: 0xffc95c1b
│ │  			@ <UNDEFINED> instruction: 0xffca2ff4
│ │  	b.n	3f1a0c <uniffi_pbcli_checksum_method_api_base@@Base+0x285188>
│ │  	asrs	r4, r0, #32
│ │  	b.n	3f23d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x285b4e>
│ │  	movs	r0, #2
│ │  	b.n	3f1ff4 <uniffi_pbcli_checksum_method_api_base@@Base+0x285770>
│ │  	movs	r2, r0
│ │ @@ -1188883,15 +1188883,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f27ca <uniffi_pbcli_checksum_method_api_base@@Base+0x285f46>
│ │  	lsrs	r6, r0, #2
│ │  	subs	r0, r0, r0
│ │  	lsls	r3, r4, #1
│ │  	b.n	3f2872 <uniffi_pbcli_checksum_method_api_base@@Base+0x285fee>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r4, r5, r9, sl, fp}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r6, r9, sl, fp}
│ │  			@ <UNDEFINED> instruction: 0xffcb2fb8
│ │  	b.n	3f1c7c <uniffi_pbcli_checksum_method_api_base@@Base+0x2853f8>
│ │  	asrs	r3, r0, #32
│ │  	b.n	3f2642 <uniffi_pbcli_checksum_method_api_base@@Base+0x285dbe>
│ │  	movs	r0, #2
│ │  	b.n	3f2264 <uniffi_pbcli_checksum_method_api_base@@Base+0x2859e0>
│ │  	movs	r2, r0
│ │ @@ -1189045,15 +1189045,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f292a <uniffi_pbcli_checksum_method_api_base@@Base+0x2860a6>
│ │  	lsrs	r6, r5, #32
│ │  	subs	r0, r0, r0
│ │  	lsls	r4, r2, #1
│ │  	b.n	3f29d2 <uniffi_pbcli_checksum_method_api_base@@Base+0x28614e>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r5, r6, r8, r9, sl, fp, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r4, r7, r8, r9, sl, fp, ip, lr, pc}
│ │  	vmla.f<illegal width 8>	<illegal reg q10.5>, q5, d0[3]
│ │  			@ <UNDEFINED> instruction: 0xffcb2ff8
│ │  	b.n	3f1de0 <uniffi_pbcli_checksum_method_api_base@@Base+0x28555c>
│ │  	asrs	r3, r0, #32
│ │  	b.n	3f27a6 <uniffi_pbcli_checksum_method_api_base@@Base+0x285f22>
│ │  	movs	r0, #2
│ │  	b.n	3f23c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x285b44>
│ │ @@ -1189272,15 +1189272,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f2b26 <uniffi_pbcli_checksum_method_api_base@@Base+0x2862a2>
│ │  	lsls	r7, r5, #30
│ │  	subs	r0, r0, r0
│ │  	lsls	r2, r5, #4
│ │  	b.n	3f2a8e <uniffi_pbcli_checksum_method_api_base@@Base+0x28620a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r6, r7, r8, lr}
│ │ +	ldmia.w	sp!, {r0, r2, r4, r5, r6, r7, r8, lr}
│ │  	vqrdmlsh.s<illegal width 8>	q9, q13, d0[3]
│ │  	b.n	3f1fd8 <uniffi_pbcli_checksum_method_api_base@@Base+0x285754>
│ │  	asrs	r3, r0, #32
│ │  	b.n	3f299e <uniffi_pbcli_checksum_method_api_base@@Base+0x28611a>
│ │  	movs	r0, #2
│ │  	b.n	3f25c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x285d3c>
│ │  	movs	r2, r0
│ │ @@ -1189518,15 +1189518,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f2d4a <uniffi_pbcli_checksum_method_api_base@@Base+0x2864c6>
│ │  	lsls	r6, r4, #28
│ │  	subs	r0, r0, r0
│ │  	lsls	r3, r1, #2
│ │  	b.n	3f2df2 <uniffi_pbcli_checksum_method_api_base@@Base+0x28656e>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r2, r6, r8, r9, sl, fp, ip}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r5, r6, r8, r9, sl, fp, ip}
│ │  	vqrdmlsh.s<illegal width 8>	q9, <illegal reg q13.5>, d0[4]
│ │  	b.n	3f21fc <uniffi_pbcli_checksum_method_api_base@@Base+0x285978>
│ │  	asrs	r3, r0, #32
│ │  	b.n	3f2bc2 <uniffi_pbcli_checksum_method_api_base@@Base+0x28633e>
│ │  	movs	r0, #2
│ │  	b.n	3f27e4 <uniffi_pbcli_checksum_method_api_base@@Base+0x285f60>
│ │  	movs	r2, r0
│ │ @@ -1189594,15 +1189594,15 @@
│ │  	b.n	3f2dfa <uniffi_pbcli_checksum_method_api_base@@Base+0x286576>
│ │  	lsls	r2, r7, #27
│ │  	subs	r0, r0, r0
│ │  	lsls	r2, r0, #2
│ │  	b.n	3f2ea2 <uniffi_pbcli_checksum_method_api_base@@Base+0x28661e>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r1, r2, r4, r5, r7, r9, lr}
│ │ -	vrsra.u64	d28, d2, #55
│ │ +	vrsra.u64	d28, d25, #55
│ │  	vaddl.u8	<illegal reg q8.5>, d10, d3
│ │  	b.n	3f2312 <uniffi_pbcli_checksum_method_api_base@@Base+0x285a8e>
│ │  	lsls	r4, r6, #1
│ │  	b.n	3f2e18 <uniffi_pbcli_checksum_method_api_base@@Base+0x286594>
│ │  	asrs	r4, r0, #32
│ │  	lsls	r0, r2, #23
│ │  	lsls	r1, r7, #1
│ │ @@ -1189893,15 +1189893,15 @@
│ │  	b.n	3f308a <uniffi_pbcli_checksum_method_api_base@@Base+0x286806>
│ │  	lsls	r6, r2, #25
│ │  	subs	r0, r0, r0
│ │  	movs	r2, r6
│ │  	b.n	3f3132 <uniffi_pbcli_checksum_method_api_base@@Base+0x2868ae>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r1, r2, r3, r8, r9, sl, ip, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffc9eede
│ │ +			@ <UNDEFINED> instruction: 0xffc9ef05
│ │  			@ <UNDEFINED> instruction: 0xffca2ff0
│ │  	b.n	3f2540 <uniffi_pbcli_checksum_method_api_base@@Base+0x285cbc>
│ │  	asrs	r5, r0, #32
│ │  	b.n	3f2f06 <uniffi_pbcli_checksum_method_api_base@@Base+0x286682>
│ │  	movs	r0, #2
│ │  	b.n	3f2b28 <uniffi_pbcli_checksum_method_api_base@@Base+0x2862a4>
│ │  	movs	r2, r0
│ │ @@ -1189913,15 +1189913,15 @@
│ │  	subs	r0, r0, r0
│ │  	lsls	r6, r3, #1
│ │  	b.n	3f315e <uniffi_pbcli_checksum_method_api_base@@Base+0x2868da>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r6}
│ │  	b.n	3f3166 <uniffi_pbcli_checksum_method_api_base@@Base+0x2868e2>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r3, r6, r7, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r4, r5, r6, r7, lr, pc}
│ │  	vqrdmlsh.s<illegal width 8>	q9, q13, d0[6]
│ │  	b.n	3f2570 <uniffi_pbcli_checksum_method_api_base@@Base+0x285cec>
│ │  	asrs	r4, r0, #32
│ │  	b.n	3f2f36 <uniffi_pbcli_checksum_method_api_base@@Base+0x2866b2>
│ │  	movs	r0, #2
│ │  	b.n	3f2b58 <uniffi_pbcli_checksum_method_api_base@@Base+0x2862d4>
│ │  	movs	r2, r0
│ │ @@ -1190056,15 +1190056,15 @@
│ │  	movs	r0, r0
│ │  	adds	r0, r0, r1
│ │  	movs	r0, r0
│ │  	adds	r0, r0, r1
│ │  	movs	r0, r0
│ │  	lsrs	r0, r3, #24
│ │  	movs	r0, r0
│ │ -	str	r0, [sp, #920]	@ 0x398
│ │ +	str	r1, [sp, #52]	@ 0x34
│ │  	vqrdmlsh.s<illegal width 8>	q9, q13, d0[6]
│ │  	b.n	3f26a0 <uniffi_pbcli_checksum_method_api_base@@Base+0x285e1c>
│ │  	asrs	r5, r0, #32
│ │  	b.n	3f3066 <uniffi_pbcli_checksum_method_api_base@@Base+0x2867e2>
│ │  	movs	r0, #2
│ │  	b.n	3f2c88 <uniffi_pbcli_checksum_method_api_base@@Base+0x286404>
│ │  	movs	r2, r0
│ │ @@ -1190095,15 +1190095,15 @@
│ │  	subs	r0, r0, r0
│ │  	movs	r1, r6
│ │  	b.n	3f32ea <uniffi_pbcli_checksum_method_api_base@@Base+0x286a66>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r1, r2}
│ │  	b.n	3f32f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x286a6e>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r9, fp, ip}
│ │ +	ldmia.w	sp!, {r0, r3, r5, r9, fp, ip}
│ │  	vqrdmlsh.s<illegal width 8>	q9, <illegal reg q13.5>, d0[4]
│ │  	b.n	3f26fc <uniffi_pbcli_checksum_method_api_base@@Base+0x285e78>
│ │  	asrs	r4, r0, #32
│ │  	b.n	3f30c2 <uniffi_pbcli_checksum_method_api_base@@Base+0x28683e>
│ │  	movs	r0, #2
│ │  	b.n	3f2ce4 <uniffi_pbcli_checksum_method_api_base@@Base+0x286460>
│ │  	movs	r2, r0
│ │ @@ -1190167,15 +1190167,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f32ea <uniffi_pbcli_checksum_method_api_base@@Base+0x286a66>
│ │  	lsls	r6, r7, #22
│ │  	subs	r0, r0, r0
│ │  	lsls	r7, r1, #4
│ │  	b.n	3f3252 <uniffi_pbcli_checksum_method_api_base@@Base+0x2869ce>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r5, r9, fp, sp, lr}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r6, r9, fp, sp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffca2ffc
│ │  	b.n	3f279c <uniffi_pbcli_checksum_method_api_base@@Base+0x285f18>
│ │  	asrs	r4, r0, #32
│ │  	b.n	3f3162 <uniffi_pbcli_checksum_method_api_base@@Base+0x2868de>
│ │  	movs	r0, #2
│ │  	b.n	3f2d84 <uniffi_pbcli_checksum_method_api_base@@Base+0x286500>
│ │  	movs	r2, r0
│ │ @@ -1190263,15 +1190263,15 @@
│ │  	subs	r0, r0, r0
│ │  	lsls	r2, r6, #2
│ │  	b.n	3f3466 <uniffi_pbcli_checksum_method_api_base@@Base+0x286be2>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r2, r4, r5, r6}
│ │  	b.n	3f346e <uniffi_pbcli_checksum_method_api_base@@Base+0x286bea>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r3, r8, r9, sl, fp, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r5, r8, r9, sl, fp, pc}
│ │  	vqrdmlsh.s<illegal width 8>	q9, q13, d0[7]
│ │  	b.n	3f2878 <uniffi_pbcli_checksum_method_api_base@@Base+0x285ff4>
│ │  	asrs	r4, r0, #32
│ │  	b.n	3f323e <uniffi_pbcli_checksum_method_api_base@@Base+0x2869ba>
│ │  	movs	r0, #2
│ │  	b.n	3f2e60 <uniffi_pbcli_checksum_method_api_base@@Base+0x2865dc>
│ │  	movs	r2, r0
│ │ @@ -1190392,15 +1190392,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f34f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x286c6e>
│ │  	lsls	r4, r7, #20
│ │  	subs	r0, r0, r0
│ │  	lsls	r1, r3, #4
│ │  	b.n	3f345a <uniffi_pbcli_checksum_method_api_base@@Base+0x286bd6>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r6, r9, sl, fp, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r7, r9, sl, fp, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffcadb6c
│ │  	vaddl.u8	<illegal reg q8.5>, d9, d5
│ │  	b.n	3f2a0a <uniffi_pbcli_checksum_method_api_base@@Base+0x286186>
│ │  	lsls	r4, r6, #1
│ │  	b.n	3f3510 <uniffi_pbcli_checksum_method_api_base@@Base+0x286c8c>
│ │  	asrs	r6, r0, #32
│ │  	lsls	r0, r2, #23
│ │ @@ -1190460,15 +1190460,15 @@
│ │  	subs	r0, r0, r0
│ │  	lsls	r4, r3, #1
│ │  	b.n	3f362a <uniffi_pbcli_checksum_method_api_base@@Base+0x286da6>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r1, r2, r7}
│ │  	b.n	3f3632 <uniffi_pbcli_checksum_method_api_base@@Base+0x286dae>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r5, r6, r7, r8, fp, sp, lr, pc}
│ │ +	ldmia.w	sp!, {r4, r9, fp, sp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffca2fb4
│ │  	b.n	3f2a3c <uniffi_pbcli_checksum_method_api_base@@Base+0x2861b8>
│ │  	asrs	r5, r0, #32
│ │  	b.n	3f3402 <uniffi_pbcli_checksum_method_api_base@@Base+0x286b7e>
│ │  	movs	r0, #2
│ │  	b.n	3f3024 <uniffi_pbcli_checksum_method_api_base@@Base+0x2867a0>
│ │  	movs	r2, r0
│ │ @@ -1190564,15 +1190564,15 @@
│ │  	b.n	3f34ec <uniffi_pbcli_checksum_method_api_base@@Base+0x286c68>
│ │  	asrs	r5, r5, #3
│ │  	b.n	3f3712 <uniffi_pbcli_checksum_method_api_base@@Base+0x286e8e>
│ │  	movs	r1, #2
│ │  	b.n	3f2efc <uniffi_pbcli_checksum_method_api_base@@Base+0x286678>
│ │  	bfcsel	0, 3f30dc <uniffi_pbcli_checksum_method_api_base@@Base+0x286858>, 4, eq
│ │  	bl	5a2f6c <uniffi_pbcli_checksum_method_api_base@@Base+0x4366e8>
│ │ -	strb	r7, [r7, #27]
│ │ +	strb	r6, [r4, #28]
│ │  	vsubl.u8	q15, d26, d22
│ │  	vsli.8	d30, d20, #1
│ │  			@ <UNDEFINED> instruction: 0xffff1364
│ │  	movs	r0, r0
│ │  	asrs	r4, r4, #13
│ │  	movs	r0, r0
│ │  	asrs	r4, r4, #13
│ │ @@ -1190699,15 +1190699,15 @@
│ │  	movs	r0, r0
│ │  	lsls	r0, r2, #13
│ │  	lsls	r6, r2, #18
│ │  	subs	r0, r0, r0
│ │  	lsls	r7, r5, #3
│ │  	b.n	3f3832 <uniffi_pbcli_checksum_method_api_base@@Base+0x286fae>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r6, r7, r8, fp, lr}
│ │ +	ldmia.w	sp!, {r2, r4, r5, r6, r7, r8, fp, lr}
│ │  			@ <UNDEFINED> instruction: 0xffca1f99
│ │  	vaddl.u8	<illegal reg q8.5>, d10, d5
│ │  	b.n	3f2ca2 <uniffi_pbcli_checksum_method_api_base@@Base+0x28641e>
│ │  	lsls	r1, r4, #1
│ │  	b.n	3f37a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x286f24>
│ │  	lsls	r7, r1, #18
│ │  	subs	r0, r0, r0
│ │ @@ -1190740,16 +1190740,16 @@
│ │  	adds	r0, #16
│ │  	b.n	3f3660 <uniffi_pbcli_checksum_method_api_base@@Base+0x286ddc>
│ │  	asrs	r0, r7, #3
│ │  	b.n	3f3886 <uniffi_pbcli_checksum_method_api_base@@Base+0x287002>
│ │  	movs	r1, #2
│ │  	b.n	3f3070 <uniffi_pbcli_checksum_method_api_base@@Base+0x2867ec>
│ │  	bfcsel	0, 3f3250 <uniffi_pbcli_checksum_method_api_base@@Base+0x2869cc>, 4, eq
│ │ -	cbnz	r1, 3f315c <uniffi_pbcli_checksum_method_api_base@@Base+0x2868d8>
│ │ -	vsubl.u8	q13, d10, d21
│ │ +	cbnz	r0, 3f3166 <uniffi_pbcli_checksum_method_api_base@@Base+0x2868e2>
│ │ +	vmlal.u<illegal width 8>	q13, d10, d0[3]
│ │  			@ <UNDEFINED> instruction: 0xffcae3c4
│ │  	vsra.u64	<illegal reg q8.5>, q10, #1
│ │  	movs	r0, r0
│ │  	asrs	r4, r6, #7
│ │  	movs	r0, r0
│ │  	asrs	r4, r6, #7
│ │  	movs	r0, r0
│ │ @@ -1190901,15 +1190901,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f3932 <uniffi_pbcli_checksum_method_api_base@@Base+0x2870ae>
│ │  	lsls	r4, r5, #16
│ │  	subs	r0, r0, r0
│ │  	lsrs	r2, r2, #24
│ │  	b.n	3f39da <uniffi_pbcli_checksum_method_api_base@@Base+0x287156>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r2, r4, r5, fp, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r4, r6, fp, lr}
│ │  	vqrdmlsh.s<illegal width 8>	q9, q13, d0[4]
│ │  	b.n	3f2de4 <uniffi_pbcli_checksum_method_api_base@@Base+0x286560>
│ │  	asrs	r5, r0, #32
│ │  	b.n	3f37aa <uniffi_pbcli_checksum_method_api_base@@Base+0x286f26>
│ │  	movs	r0, #2
│ │  	b.n	3f33cc <uniffi_pbcli_checksum_method_api_base@@Base+0x286b48>
│ │  	movs	r2, r0
│ │ @@ -1190934,15 +1190934,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f397e <uniffi_pbcli_checksum_method_api_base@@Base+0x2870fa>
│ │  	lsls	r1, r3, #16
│ │  	subs	r0, r0, r0
│ │  	lsls	r1, r5, #1
│ │  	b.n	3f3a26 <uniffi_pbcli_checksum_method_api_base@@Base+0x2871a2>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r3, r4, r5, r6, r7, r9, sl, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r5, r8, r9, sl, fp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffca2fdc
│ │  	b.n	3f2e30 <uniffi_pbcli_checksum_method_api_base@@Base+0x2865ac>
│ │  	asrs	r5, r0, #32
│ │  	b.n	3f37f6 <uniffi_pbcli_checksum_method_api_base@@Base+0x286f72>
│ │  	movs	r0, #2
│ │  	b.n	3f3418 <uniffi_pbcli_checksum_method_api_base@@Base+0x286b94>
│ │  	movs	r2, r0
│ │ @@ -1190987,15 +1190987,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f39fa <uniffi_pbcli_checksum_method_api_base@@Base+0x287176>
│ │  	lsls	r2, r7, #15
│ │  	subs	r0, r0, r0
│ │  	movs	r5, r5
│ │  	b.n	3f3aa2 <uniffi_pbcli_checksum_method_api_base@@Base+0x28721e>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r7, r9, sl, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r4, r5, r7, r9, sl, fp, lr, pc}
│ │  	vqrdmlsh.s<illegal width 8>	q9, q13, d0[7]
│ │  	b.n	3f2eac <uniffi_pbcli_checksum_method_api_base@@Base+0x286628>
│ │  	asrs	r6, r0, #32
│ │  	b.n	3f3872 <uniffi_pbcli_checksum_method_api_base@@Base+0x286fee>
│ │  	movs	r0, #2
│ │  	b.n	3f3494 <uniffi_pbcli_checksum_method_api_base@@Base+0x286c10>
│ │  	movs	r2, r0
│ │ @@ -1191020,15 +1191020,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f3a46 <uniffi_pbcli_checksum_method_api_base@@Base+0x2871c2>
│ │  	lsls	r7, r4, #15
│ │  	subs	r0, r0, r0
│ │  	lsls	r3, r7, #4
│ │  	b.n	3f39ae <uniffi_pbcli_checksum_method_api_base@@Base+0x28712a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r5, r7, r9, ip, sp}
│ │ +	ldmia.w	sp!, {r1, r4, r6, r7, r9, ip, sp}
│ │  			@ <UNDEFINED> instruction: 0xffca2ff8
│ │  	b.n	3f2ef8 <uniffi_pbcli_checksum_method_api_base@@Base+0x286674>
│ │  	asrs	r6, r0, #32
│ │  	b.n	3f38be <uniffi_pbcli_checksum_method_api_base@@Base+0x28703a>
│ │  	movs	r0, #2
│ │  	b.n	3f34e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x286c5c>
│ │  	movs	r2, r0
│ │ @@ -1191144,15 +1191144,15 @@
│ │  	subs	r0, r0, r0
│ │  	lsls	r0, r0, #1
│ │  	b.n	3f3bf6 <uniffi_pbcli_checksum_method_api_base@@Base+0x287372>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r4, r5, r9, sl, sp, pc}
│ │  	vmull.u8	<illegal reg q8.5>, d8, d1
│ │  	vrsra.u64	d23, d30, #54
│ │ -	vrshr.u8	d23, d8, #8
│ │ +	vrshr.u8	d23, d31, #8
│ │  	vaddl.u8	<illegal reg q8.5>, d10, d5
│ │  	b.n	3f306e <uniffi_pbcli_checksum_method_api_base@@Base+0x2867ea>
│ │  	movs	r5, r5
│ │  	b.n	3f3b74 <uniffi_pbcli_checksum_method_api_base@@Base+0x2872f0>
│ │  	lsls	r4, r3, #14
│ │  	subs	r0, r0, r0
│ │  	asrs	r6, r0, #32
│ │ @@ -1191200,15 +1191200,15 @@
│ │  	subs	r0, r0, r0
│ │  	lsls	r6, r5, #4
│ │  	b.n	3f3b32 <uniffi_pbcli_checksum_method_api_base@@Base+0x2872ae>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r1, r2, r3, r4, r6, r7}
│ │  	b.n	3f3c7a <uniffi_pbcli_checksum_method_api_base@@Base+0x2873f6>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r2, r3, r6, r8, r9, fp, ip, lr}
│ │ +	ldmia.w	sp!, {r1, r2, r4, r5, r6, r8, r9, fp, ip, lr}
│ │  			@ <UNDEFINED> instruction: 0xffca2f54
│ │  	b.n	3f3084 <uniffi_pbcli_checksum_method_api_base@@Base+0x286800>
│ │  	asrs	r6, r0, #32
│ │  	b.n	3f3a4a <uniffi_pbcli_checksum_method_api_base@@Base+0x2871c6>
│ │  	movs	r0, #2
│ │  	b.n	3f366c <uniffi_pbcli_checksum_method_api_base@@Base+0x286de8>
│ │  	movs	r2, r0
│ │ @@ -1191220,15 +1191220,15 @@
│ │  	subs	r0, r0, r0
│ │  	lsls	r3, r5, #2
│ │  	b.n	3f3ca2 <uniffi_pbcli_checksum_method_api_base@@Base+0x28741e>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r2, r5, r7}
│ │  	b.n	3f3caa <uniffi_pbcli_checksum_method_api_base@@Base+0x287426>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r4, fp, sp}
│ │ +	ldmia.w	sp!, {r6, fp, sp}
│ │  	vqrdmlsh.s<illegal width 8>	q9, <illegal reg q5.5>, d0[4]
│ │  	b.n	3f30b4 <uniffi_pbcli_checksum_method_api_base@@Base+0x286830>
│ │  	asrs	r5, r0, #32
│ │  	b.n	3f3a7a <uniffi_pbcli_checksum_method_api_base@@Base+0x2871f6>
│ │  	movs	r0, #2
│ │  	b.n	3f369c <uniffi_pbcli_checksum_method_api_base@@Base+0x286e18>
│ │  	movs	r2, r0
│ │ @@ -1191237,15 +1191237,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f3c2a <uniffi_pbcli_checksum_method_api_base@@Base+0x2873a6>
│ │  	lsls	r6, r5, #13
│ │  	subs	r0, r0, r0
│ │  	lsls	r7, r1, #1
│ │  	b.n	3f3cd2 <uniffi_pbcli_checksum_method_api_base@@Base+0x28744e>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r2, fp, sp}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r5, fp, sp}
│ │  			@ <UNDEFINED> instruction: 0xffcb2f50
│ │  	b.n	3f30dc <uniffi_pbcli_checksum_method_api_base@@Base+0x286858>
│ │  	asrs	r6, r0, #32
│ │  	b.n	3f3aa2 <uniffi_pbcli_checksum_method_api_base@@Base+0x28721e>
│ │  	movs	r0, #2
│ │  	b.n	3f36c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x286e40>
│ │  	movs	r2, r0
│ │ @@ -1191254,15 +1191254,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f3c52 <uniffi_pbcli_checksum_method_api_base@@Base+0x2873ce>
│ │  	lsls	r4, r4, #13
│ │  	subs	r0, r0, r0
│ │  	lsls	r5, r7, #4
│ │  	b.n	3f3bba <uniffi_pbcli_checksum_method_api_base@@Base+0x287336>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r4, r5, sl, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r3, r4, r6, sl, fp, lr, pc}
│ │  			@ <UNDEFINED> instruction: 0xffca2f20
│ │  	b.n	3f3104 <uniffi_pbcli_checksum_method_api_base@@Base+0x286880>
│ │  	asrs	r6, r0, #32
│ │  	b.n	3f3aca <uniffi_pbcli_checksum_method_api_base@@Base+0x287246>
│ │  	movs	r0, #2
│ │  	b.n	3f36ec <uniffi_pbcli_checksum_method_api_base@@Base+0x286e68>
│ │  	movs	r2, r0
│ │ @@ -1191336,15 +1191336,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f3d0e <uniffi_pbcli_checksum_method_api_base@@Base+0x28748a>
│ │  	lsls	r5, r6, #12
│ │  	subs	r0, r0, r0
│ │  	lsls	r1, r0, #3
│ │  	b.n	3f3db6 <uniffi_pbcli_checksum_method_api_base@@Base+0x287532>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r4, r7, r9, sl, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r5, r7, r9, sl, sp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffca2efc
│ │  	b.n	3f31c0 <uniffi_pbcli_checksum_method_api_base@@Base+0x28693c>
│ │  	asrs	r6, r0, #32
│ │  	b.n	3f3b86 <uniffi_pbcli_checksum_method_api_base@@Base+0x287302>
│ │  	movs	r0, #2
│ │  	b.n	3f37a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x286f24>
│ │  	movs	r2, r0
│ │ @@ -1191370,15 +1191370,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f3d5e <uniffi_pbcli_checksum_method_api_base@@Base+0x2874da>
│ │  	lsls	r1, r4, #12
│ │  	subs	r0, r0, r0
│ │  	movs	r1, r5
│ │  	b.n	3f3e06 <uniffi_pbcli_checksum_method_api_base@@Base+0x287582>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r4, r5, r8, r9, fp, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r3, r4, r6, r8, r9, fp, lr, pc}
│ │  	vmull.p8	q9, d10, d28
│ │  	b.n	3f3210 <uniffi_pbcli_checksum_method_api_base@@Base+0x28698c>
│ │  	asrs	r5, r0, #32
│ │  	b.n	3f3bd6 <uniffi_pbcli_checksum_method_api_base@@Base+0x287352>
│ │  	movs	r0, #2
│ │  	b.n	3f37f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x286f74>
│ │  	movs	r2, r0
│ │ @@ -1191466,15 +1191466,15 @@
│ │  	movs	r0, r0
│ │  	lsrs	r0, r0, #16
│ │  	movs	r0, r0
│ │  	lsrs	r0, r0, #16
│ │  	movs	r0, r0
│ │  	lsrs	r0, r5, #3
│ │  	movs	r0, r0
│ │ -	ldr	r4, [sp, #700]	@ 0x2bc
│ │ +	ldr	r4, [sp, #856]	@ 0x358
│ │  	vqrdmulh.s<illegal width 8>	q9, q5, d0[5]
│ │  	b.n	3f32dc <uniffi_pbcli_checksum_method_api_base@@Base+0x286a58>
│ │  	asrs	r3, r1, #32
│ │  	b.n	3f3ca2 <uniffi_pbcli_checksum_method_api_base@@Base+0x28741e>
│ │  	movs	r0, #2
│ │  	b.n	3f38c4 <uniffi_pbcli_checksum_method_api_base@@Base+0x287040>
│ │  	movs	r2, r0
│ │ @@ -1191483,15 +1191483,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f3e52 <uniffi_pbcli_checksum_method_api_base@@Base+0x2875ce>
│ │  	lsls	r4, r4, #11
│ │  	subs	r0, r0, r0
│ │  	movs	r5, r1
│ │  	b.n	3f3efa <uniffi_pbcli_checksum_method_api_base@@Base+0x287676>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r4, r6, r7, fp, ip, lr}
│ │ +	ldmia.w	sp!, {r2, r3, r4, r5, r6, r7, fp, ip, lr}
│ │  			@ <UNDEFINED> instruction: 0xffca1987
│ │  	vaddl.u8	<illegal reg q8.5>, d9, d5
│ │  	b.n	3f336a <uniffi_pbcli_checksum_method_api_base@@Base+0x286ae6>
│ │  	lsls	r5, r6, #1
│ │  	b.n	3f3e70 <uniffi_pbcli_checksum_method_api_base@@Base+0x2875ec>
│ │  	lsls	r5, r2, #3
│ │  	lsrs	r0, r0, #8
│ │ @@ -1191553,15 +1191553,15 @@
│ │  	lsls	r7, r7, #10
│ │  	subs	r0, r0, r0
│ │  	movs	r4, r1
│ │  	b.n	3f3f8e <uniffi_pbcli_checksum_method_api_base@@Base+0x28770a>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r6, r7, r8, ip, sp}
│ │  			@ <UNDEFINED> instruction: 0xffc9e89e
│ │ -	vsubl.u8	<illegal reg q13.5>, d25, d8
│ │ +	vsubl.u8	<illegal reg q13.5>, d25, d31
│ │  	vaddl.u8	<illegal reg q8.5>, d10, d5
│ │  	b.n	3f3402 <uniffi_pbcli_checksum_method_api_base@@Base+0x286b7e>
│ │  	lsls	r1, r5, #1
│ │  	b.n	3f3f08 <uniffi_pbcli_checksum_method_api_base@@Base+0x287684>
│ │  	asrs	r6, r0, #32
│ │  	lsls	r0, r2, #23
│ │  	lsls	r7, r4, #1
│ │ @@ -1191681,15 +1191681,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f4002 <uniffi_pbcli_checksum_method_api_base@@Base+0x28777e>
│ │  	lsls	r0, r7, #9
│ │  	subs	r0, r0, r0
│ │  	lsls	r3, r5, #4
│ │  	b.n	3f3f6a <uniffi_pbcli_checksum_method_api_base@@Base+0x2876e6>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r2, r7, r8, lr}
│ │ +	ldmia.w	sp!, {r0, r1, r3, r5, r7, r8, lr}
│ │  	vaddl.u8	<illegal reg q8.5>, d10, d5
│ │  	b.n	3f3516 <uniffi_pbcli_checksum_method_api_base@@Base+0x286c92>
│ │  	lsls	r6, r5, #1
│ │  	b.n	3f401c <uniffi_pbcli_checksum_method_api_base@@Base+0x287798>
│ │  	lsls	r1, r4, #1
│ │  	lsrs	r0, r0, #8
│ │  	lsls	r1, r4, #1
│ │ @@ -1191892,16 +1191892,16 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f41e2 <uniffi_pbcli_checksum_method_api_base@@Base+0x28795e>
│ │  	lsls	r0, r0, #8
│ │  	subs	r0, r0, r0
│ │  	movs	r6, r7
│ │  	b.n	3f428a <uniffi_pbcli_checksum_method_api_base@@Base+0x287a06>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r4, r6, r8, sl, ip, lr}
│ │ -			@ <UNDEFINED> instruction: 0xffca2ad1
│ │ +	ldmia.w	sp!, {r7, r8, sl, ip, lr}
│ │ +			@ <UNDEFINED> instruction: 0xffca2af8
│ │  	vaddl.u8	<illegal reg q8.5>, d10, d6
│ │  	b.n	3f36fa <uniffi_pbcli_checksum_method_api_base@@Base+0x286e76>
│ │  	lsls	r6, r5, #1
│ │  	b.n	3f4200 <uniffi_pbcli_checksum_method_api_base@@Base+0x28797c>
│ │  	asrs	r7, r0, #32
│ │  	lsls	r0, r2, #23
│ │  	movs	r5, r5
│ │ @@ -1191930,15 +1191930,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f4236 <uniffi_pbcli_checksum_method_api_base@@Base+0x2879b2>
│ │  	lsls	r3, r5, #7
│ │  	subs	r0, r0, r0
│ │  	movs	r2, r2
│ │  	b.n	3f42de <uniffi_pbcli_checksum_method_api_base@@Base+0x287a5a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r6, r9, sl, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r5, r6, r9, sl, lr, pc}
│ │  	vmul.f<illegal width 8>	q9, q13, d0[4]
│ │  	b.n	3f36e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x286e64>
│ │  	asrs	r1, r1, #32
│ │  	b.n	3f40ae <uniffi_pbcli_checksum_method_api_base@@Base+0x28782a>
│ │  	movs	r0, #2
│ │  	b.n	3f3cd0 <uniffi_pbcli_checksum_method_api_base@@Base+0x28744c>
│ │  	movs	r2, r0
│ │ @@ -1192012,16 +1192012,16 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f42f2 <uniffi_pbcli_checksum_method_api_base@@Base+0x287a6e>
│ │  	lsls	r4, r7, #6
│ │  	subs	r0, r0, r0
│ │  	lsls	r7, r4, #2
│ │  	b.n	3f439a <uniffi_pbcli_checksum_method_api_base@@Base+0x287b16>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r4, r5, r6, r8, fp}
│ │ -	vsri.8	d21, d20, #5
│ │ +	ldmia.w	sp!, {r0, r2, r3, r4, r7, r8, fp}
│ │ +	vsri.8	<illegal reg q10.5>, <illegal reg q5.5>, #5
│ │  	vqshrun.s16	d18, q14, #6
│ │  	b.n	3f37a8 <uniffi_pbcli_checksum_method_api_base@@Base+0x286f24>
│ │  	asrs	r0, r1, #32
│ │  	b.n	3f416e <uniffi_pbcli_checksum_method_api_base@@Base+0x2878ea>
│ │  	movs	r0, #2
│ │  	b.n	3f3d90 <uniffi_pbcli_checksum_method_api_base@@Base+0x28750c>
│ │  	movs	r2, r0
│ │ @@ -1192047,15 +1192047,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f4346 <uniffi_pbcli_checksum_method_api_base@@Base+0x287ac2>
│ │  	lsls	r7, r4, #6
│ │  	subs	r0, r0, r0
│ │  	lsls	r3, r6, #2
│ │  	b.n	3f43ee <uniffi_pbcli_checksum_method_api_base@@Base+0x287b6a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r2, r3, r4, r5, r8, sl, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r5, r6, r8, sl, lr, pc}
│ │  	vqshl.u64	q9, q14, #10
│ │  	b.n	3f37f8 <uniffi_pbcli_checksum_method_api_base@@Base+0x286f74>
│ │  	asrs	r1, r1, #32
│ │  	b.n	3f41be <uniffi_pbcli_checksum_method_api_base@@Base+0x28793a>
│ │  	movs	r0, #2
│ │  	b.n	3f3de0 <uniffi_pbcli_checksum_method_api_base@@Base+0x28755c>
│ │  	movs	r2, r0
│ │ @@ -1192064,15 +1192064,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f436e <uniffi_pbcli_checksum_method_api_base@@Base+0x287aea>
│ │  	lsls	r5, r3, #6
│ │  	subs	r0, r0, r0
│ │  	lsls	r4, r4, #1
│ │  	b.n	3f4416 <uniffi_pbcli_checksum_method_api_base@@Base+0x287b92>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r5, r9, sl, fp, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r3, r6, r9, sl, fp, sp, pc}
│ │  	vaddl.u8	<illegal reg q8.5>, d10, d7
│ │  	b.n	3f3882 <uniffi_pbcli_checksum_method_api_base@@Base+0x286ffe>
│ │  	movs	r5, r5
│ │  	b.n	3f4388 <uniffi_pbcli_checksum_method_api_base@@Base+0x287b04>
│ │  	lsls	r7, r2, #6
│ │  	subs	r0, r0, r0
│ │  	asrs	r0, r1, #32
│ │ @@ -1192120,15 +1192120,15 @@
│ │  	subs	r0, r0, r0
│ │  	lsls	r3, r4, #4
│ │  	b.n	3f434e <uniffi_pbcli_checksum_method_api_base@@Base+0x287aca>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r1, r2, r6}
│ │  	b.n	3f4496 <uniffi_pbcli_checksum_method_api_base@@Base+0x287c12>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r3, r6, r7, r8, sl, fp, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r1, r2, r3, r5, r6, r7, r8, sl, fp, sp, pc}
│ │  	vmla.i<illegal width 8>	q8, q5, d3[5]
│ │  	b.n	3f44a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x287c1e>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r5, r7, sl, fp, sp}
│ │  	vqshl.u64	q9, q8, #9
│ │  	b.n	3f38ac <uniffi_pbcli_checksum_method_api_base@@Base+0x287028>
│ │  	asrs	r2, r1, #32
│ │ @@ -1192141,15 +1192141,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f4422 <uniffi_pbcli_checksum_method_api_base@@Base+0x287b9e>
│ │  	lsls	r0, r6, #5
│ │  	subs	r0, r0, r0
│ │  	lsls	r2, r6, #4
│ │  	b.n	3f438a <uniffi_pbcli_checksum_method_api_base@@Base+0x287b06>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r4, r8, r9, ip, lr}
│ │ +	ldmia.w	sp!, {r1, r6, r8, r9, ip, lr}
│ │  			@ <UNDEFINED> instruction: 0xffca27c4
│ │  	b.n	3f38d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x287050>
│ │  	asrs	r2, r1, #32
│ │  	b.n	3f429a <uniffi_pbcli_checksum_method_api_base@@Base+0x287a16>
│ │  	movs	r0, #2
│ │  	b.n	3f3ebc <uniffi_pbcli_checksum_method_api_base@@Base+0x287638>
│ │  	movs	r2, r0
│ │ @@ -1192174,15 +1192174,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f446e <uniffi_pbcli_checksum_method_api_base@@Base+0x287bea>
│ │  	lsls	r5, r3, #5
│ │  	subs	r0, r0, r0
│ │  	movs	r3, r2
│ │  	b.n	3f4516 <uniffi_pbcli_checksum_method_api_base@@Base+0x287c92>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r2, r3, r5, r6, r9, sl, fp, ip, sp, lr}
│ │ +	ldmia.w	sp!, {r2, r4, r7, r9, sl, fp, ip, sp, lr}
│ │  	vqshl.u8	d18, d24, #2
│ │  	b.n	3f3920 <uniffi_pbcli_checksum_method_api_base@@Base+0x28709c>
│ │  	asrs	r1, r1, #32
│ │  	b.n	3f42e6 <uniffi_pbcli_checksum_method_api_base@@Base+0x287a62>
│ │  	movs	r0, #2
│ │  	b.n	3f3f08 <uniffi_pbcli_checksum_method_api_base@@Base+0x287684>
│ │  	movs	r2, r0
│ │ @@ -1192211,15 +1192211,15 @@
│ │  	subs	r0, r0, r0
│ │  	lsls	r7, r5, #4
│ │  	b.n	3f4426 <uniffi_pbcli_checksum_method_api_base@@Base+0x287ba2>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r5, r6}
│ │  	b.n	3f456e <uniffi_pbcli_checksum_method_api_base@@Base+0x287cea>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r3, r5, r7, r8, r9, sl}
│ │ +	ldmia.w	sp!, {r0, r4, r6, r7, r8, r9, sl}
│ │  	vaddl.u8	<illegal reg q8.5>, d11, d11
│ │  	b.n	3f39da <uniffi_pbcli_checksum_method_api_base@@Base+0x287156>
│ │  	lsls	r6, r5, #1
│ │  	b.n	3f44e0 <uniffi_pbcli_checksum_method_api_base@@Base+0x287c5c>
│ │  	asrs	r4, r1, #32
│ │  	lsls	r0, r2, #23
│ │  	lsls	r3, r4, #1
│ │ @@ -1192270,15 +1192270,15 @@
│ │  	b.n	3f4546 <uniffi_pbcli_checksum_method_api_base@@Base+0x287cc2>
│ │  	lsls	r7, r4, #4
│ │  	subs	r0, r0, r0
│ │  	lsls	r4, r0, #1
│ │  	b.n	3f45ee <uniffi_pbcli_checksum_method_api_base@@Base+0x287d6a>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r4, r7, r9, ip, sp, lr}
│ │ -	vaddl.u8	<illegal reg q15.5>, d25, d4
│ │ +	vaddl.u8	<illegal reg q15.5>, d25, d27
│ │  	vaddl.u8	<illegal reg q8.5>, d10, d11
│ │  	b.n	3f3a5e <uniffi_pbcli_checksum_method_api_base@@Base+0x2871da>
│ │  	lsls	r1, r4, #1
│ │  	b.n	3f4564 <uniffi_pbcli_checksum_method_api_base@@Base+0x287ce0>
│ │  	asrs	r4, r1, #32
│ │  	lsls	r0, r2, #23
│ │  	lsls	r0, r7, #1
│ │ @@ -1192717,15 +1192717,15 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f491e <uniffi_pbcli_checksum_method_api_base@@Base+0x28809a>
│ │  	movs	r1, r6
│ │  	subs	r0, r0, r0
│ │  	movs	r6, r3
│ │  	b.n	3f49c6 <uniffi_pbcli_checksum_method_api_base@@Base+0x288142>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r3, r5, r7, r8, ip, pc}
│ │ +	ldmia.w	sp!, {r4, r6, r7, r8, ip, pc}
│ │  	vaddl.u8	<illegal reg q8.5>, d10, d12
│ │  	b.n	3f3e32 <uniffi_pbcli_checksum_method_api_base@@Base+0x2875ae>
│ │  	lsls	r1, r5, #1
│ │  	b.n	3f4938 <uniffi_pbcli_checksum_method_api_base@@Base+0x2880b4>
│ │  	movs	r6, r4
│ │  	lsrs	r0, r0, #8
│ │  	lsls	r5, r4, #1
│ │ @@ -1192744,19 +1192744,19 @@
│ │  	add.w	r0, r2, r0
│ │  	b.n	3f495a <uniffi_pbcli_checksum_method_api_base@@Base+0x2880d6>
│ │  	movs	r2, r4
│ │  	subs	r0, r0, r0
│ │  	movs	r7, r3
│ │  	b.n	3f4a02 <uniffi_pbcli_checksum_method_api_base@@Base+0x28817e>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r0, r1, r3, r5, r6, r8, ip, pc}
│ │ +	ldmia.w	sp!, {r1, r4, r7, r8, ip, pc}
│ │  	vshr.u8	d16, d31, #6
│ │  	b.n	3f4a0e <uniffi_pbcli_checksum_method_api_base@@Base+0x28818a>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r5, r6, r7, r9}
│ │ +	ldmia.w	sp!, {r0, r3, r8, r9}
│ │  	vrshr.u64	d18, d12, #53
│ │  	b.n	3f3e18 <uniffi_pbcli_checksum_method_api_base@@Base+0x287594>
│ │  	asrs	r6, r1, #32
│ │  	b.n	3f47de <uniffi_pbcli_checksum_method_api_base@@Base+0x287f5a>
│ │  	movs	r0, #2
│ │  	b.n	3f4400 <uniffi_pbcli_checksum_method_api_base@@Base+0x287b7c>
│ │  	movs	r2, r0
│ │ @@ -1192850,15 +1192850,15 @@
│ │  	b.n	3f3f5e <uniffi_pbcli_checksum_method_api_base@@Base+0x2876da>
│ │  	movs	r0, r0
│ │  	b.n	3f4a62 <uniffi_pbcli_checksum_method_api_base@@Base+0x2881de>
│ │  			@ <UNDEFINED> instruction: 0xffe01aff
│ │  	lsls	r6, r4, #3
│ │  	b.n	3f4b0a <uniffi_pbcli_checksum_method_api_base@@Base+0x288286>
│ │  	ldrh	r0, [r0, #0]
│ │ -	ldmia.w	sp!, {r1, r2, r3, r5, r8, sl, ip, lr, pc}
│ │ +	ldmia.w	sp!, {r0, r2, r4, r6, r8, sl, ip, lr, pc}
│ │  	vshr.u8	d16, d0, #6
│ │  	b.n	3f3f76 <uniffi_pbcli_checksum_method_api_base@@Base+0x2876f2>
│ │  	movs	r0, r0
│ │  	b.n	3f4a7a <uniffi_pbcli_checksum_method_api_base@@Base+0x2881f6>
│ │  			@ <UNDEFINED> instruction: 0xffda1aff
│ │  	lsls	r7, r4, #3
│ │  	b.n	3f4b22 <uniffi_pbcli_checksum_method_api_base@@Base+0x28829e>
│ │ @@ -1192934,75 +1192934,75 @@
│ │  	b.n	3f4bca <uniffi_pbcli_checksum_method_api_base@@Base+0x288346>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r1, r3, r4}
│ │  	b.n	3f4bd2 <uniffi_pbcli_checksum_method_api_base@@Base+0x28834e>
│ │  	ldrh	r0, [r0, #0]
│ │  	ldmia.w	sp!, {r0, r1, r2, r3, r5, r6, r9, sl, ip, pc}
│ │  	vrsra.u64	d22, d10, #56
│ │ -	vaddl.u8	q8, d24, d14
│ │ +	vshr.u64	d16, d21, #56
│ │  	vsli.64	d29, d28, #11
│ │  			@ <UNDEFINED> instruction: 0xffc8eb12
│ │  	vaddw.u8	<illegal reg q12.5>, <illegal reg q12.5>, d6
│ │  			@ <UNDEFINED> instruction: 0xffc97c30
│ │  	vsubw.u8	q9, <illegal reg q12.5>, d13
│ │ -	vqrdmlah.s<illegal width 8>	q12, <illegal reg q5.5>, d0[2]
│ │ -	vqdmulh.s<illegal width 8>	q14, q5, d2[1]
│ │ +	vqrdmlah.s<illegal width 8>	q12, <illegal reg q5.5>, d3[7]
│ │ +	vqdmulh.s<illegal width 8>	q14, q5, d1[7]
│ │  			@ <UNDEFINED> instruction: 0xffca0f3f
│ │ -	vmls.f<illegal width 8>	q15, q13, d3[7]
│ │ +	vqshlu.s8	d30, d6, #2
│ │  			@ <UNDEFINED> instruction: 0xffcaec5a
│ │  	vshr.u8	q14, <illegal reg q8.5>, #7
│ │  	vqshl.u64	d22, d7, #9
│ │ -			@ <UNDEFINED> instruction: 0xffc9cf07
│ │ +			@ <UNDEFINED> instruction: 0xffc9cf2e
│ │  	vshr.u64	d25, d24, #54
│ │ -	vshr.u8	q8, q7, #8
│ │ -			@ <UNDEFINED> instruction: 0xffcb8e3b
│ │ +	vaddl.u8	q8, d24, d5
│ │ +	vqrdmlah.s<illegal width 8>	q12, <illegal reg q5.5>, d2[4]
│ │  	vmlsl.u<illegal width 8>	<illegal reg q14.5>, d10, d2[5]
│ │  	vabal.u8	<illegal reg q11.5>, d25, d12
│ │  	vsubw.u8	q12, q4, d11
│ │  	vmls.i<illegal width 8>	q11, <illegal reg q4.5>, d2[2]
│ │  			@ <UNDEFINED> instruction: 0xffc98343
│ │ -			@ <UNDEFINED> instruction: 0xffc9fb02
│ │ -			@ <UNDEFINED> instruction: 0xffcafc9a
│ │ -	vmlal.u<illegal width 8>	<illegal reg q14.5>, d26, d0[5]
│ │ -	vaddl.u8	q11, d26, d14
│ │ +			@ <UNDEFINED> instruction: 0xffc9fb29
│ │ +	vqdmulh.s<illegal width 8>	<illegal reg q15.5>, q13, d1[0]
│ │ +	vsubw.u8	<illegal reg q14.5>, q5, d11
│ │ +	vshr.u64	d22, d21, #54
│ │  	vmul.f<illegal width 8>	q11, q13, d0[5]
│ │ -	vmlsl.u<illegal width 8>	<illegal reg q10.5>, d9, d3[0]
│ │ +	vmlsl.u<illegal width 8>	<illegal reg q10.5>, d9, d2[6]
│ │  	vqshl.u8	q15, q10, #2
│ │  			@ <UNDEFINED> instruction: 0xffc923c8
│ │  			@ <UNDEFINED> instruction: 0xffcb9c9d
│ │ -			@ <UNDEFINED> instruction: 0xffc9f904
│ │ +			@ <UNDEFINED> instruction: 0xffc9f92b
│ │  	vshr.u8	d25, d3, #6
│ │ -	vmlsl.u8	<illegal reg q15.5>, d25, d4
│ │ +	vmlsl.u8	<illegal reg q15.5>, d25, d27
│ │  	vshr.u8	d25, d27, #6
│ │ -			@ <UNDEFINED> instruction: 0xffc91b45
│ │ -	vmla.i<illegal width 8>	<illegal reg q14.5>, q13, d2[6]
│ │ +			@ <UNDEFINED> instruction: 0xffc91b6c
│ │ +	vsra.u8	d29, d1, #6
│ │  	vsubw.u8	q14, q5, d4
│ │  	vmul.i<illegal width 8>	q15, q12, d0[3]
│ │  	vsli.64	d18, d7, #8
│ │  			@ <UNDEFINED> instruction: 0xffc95fdb
│ │ -			@ <UNDEFINED> instruction: 0xffc90b8c
│ │ +			@ <UNDEFINED> instruction: 0xffc90bb3
│ │  	vqshrun.s16	d30, q0, #5
│ │  	vqshl.u64	d18, d11, #8
│ │ -	vrsra.u64	<illegal reg q8.5>, <illegal reg q0.5>, #55
│ │ +	vrsra.u64	<illegal reg q8.5>, q12, #55
│ │  	vrsubhn.i16	d30, q5, q14
│ │  	vsli.64	d18, d27, #8
│ │  	vmlal.u<illegal width 8>	q14, d25, d2[5]
│ │ -	vmul.i<illegal width 8>	<illegal reg q8.5>, q12, d0[6]
│ │ -	vqrshrun.s16	d31, q13, #6
│ │ -	vqshl.u64	<illegal reg q15.5>, q7, #10
│ │ +			@ <UNDEFINED> instruction: 0xffc8190f
│ │ +	vmlal.u8	<illegal reg q15.5>, d26, d17
│ │ +	vmlal.u8	<illegal reg q15.5>, d10, d5
│ │  			@ <UNDEFINED> instruction: 0xffcaf3c1
│ │ -			@ <UNDEFINED> instruction: 0xffc9aef2
│ │ -			@ <UNDEFINED> instruction: 0xffca0f1c
│ │ +			@ <UNDEFINED> instruction: 0xffc9af19
│ │ +	vqrdmlsh.s<illegal width 8>	q8, q5, d3[0]
│ │  	vmull.u8	q12, d11, d26
│ │ -	vaddw.u8	q12, q12, d11
│ │ -			@ <UNDEFINED> instruction: 0xffcabb5a
│ │ -	vmls.f<illegal width 8>	<illegal reg q11.5>, q13, d2[3]
│ │ +	vsra.u64	d24, d18, #56
│ │ +			@ <UNDEFINED> instruction: 0xffcabb81
│ │ +	vsli.64	<illegal reg q11.5>, <illegal reg q10.5>, #10
│ │  	vmls.f<illegal width 8>	q11, q13, d2[3]
│ │  			@ <UNDEFINED> instruction: 0xffc95369
│ │ -	vshll.u8	<illegal reg q15.5>, d30, #1
│ │ +	vmull.u<illegal width 8>	<illegal reg q15.5>, d9, d1[5]
│ │  	vmlal.u8	q10, d10, d0
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	3f48da <uniffi_pbcli_checksum_method_api_base@@Base+0x288056>
│ │  	lsls	r0, r2, #3
│ │  	b.n	3f4a9e <uniffi_pbcli_checksum_method_api_base@@Base+0x28821a>
│ │  	b.n	3f4ca8 <uniffi_pbcli_checksum_method_api_base@@Base+0x288424>
│ │  			@ <UNDEFINED> instruction: 0xebfc0001
│ │ @@ -1194503,15 +1194503,15 @@
│ │  	ands	r1, r0
│ │  	b.n	3f5992 <uniffi_pbcli_checksum_method_api_base@@Base+0x28910e>
│ │  	movs	r4, r0
│ │  	b.n	3f5596 <uniffi_pbcli_checksum_method_api_base@@Base+0x288d12>
│ │  	beq.n	3f5290 <uniffi_pbcli_checksum_method_api_base@@Base+0x288a0c>
│ │  	b.n	3f56f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x288e6c>
│ │  	ldrh	r0, [r6, #62]	@ 0x3e
│ │ -	ldmia.w	sp!, {r1, r4, r5, r6, r8, sp, pc}
│ │ +	ldmia.w	sp!, {r0, r3, r4, r7, r8, sp, pc}
│ │  			@ <UNDEFINED> instruction: 0xffca4ff0
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	3f5784 <uniffi_pbcli_checksum_method_api_base@@Base+0x288f00>
│ │  	beq.n	3f52a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x288a20>
│ │  	b.n	3f5708 <uniffi_pbcli_checksum_method_api_base@@Base+0x288e84>
│ │  	ands	r0, r2
│ │  	b.n	3f4da8 <uniffi_pbcli_checksum_method_api_base@@Base+0x288524>
│ │ @@ -1445143,15 +1445143,15 @@
│ │  	lsrs	r6, r1, #12
│ │  	add.w	r0, r0, r4
│ │  	b.n	495eda <uniffi_pbcli_checksum_method_api_base@@Base+0x329656>
│ │  	lsrs	r0, r1, #12
│ │  	add.w	sl, r0, fp, lsr #1
│ │  			@ <UNDEFINED> instruction: 0xeb009ed0
│ │  	vrsubhn.i<illegal width 128>	d11, <illegal reg q15.5>, <illegal reg q4.5>
│ │ -	vtbl.8	d13, {d30-<overflow reg d32}, d12
│ │ +			@ <UNDEFINED> instruction: 0xffbedab3
│ │  			@ <UNDEFINED> instruction: 0xffc07b08
│ │  	movs	r4, r0
│ │  	ldr	r4, [pc, #448]	@ (495d74 <uniffi_pbcli_checksum_method_api_base@@Base+0x3294f0>)
│ │  	stmdb	sp!, {r4, ip, sp, pc}
│ │  	b.n	4960d4 <uniffi_pbcli_checksum_method_api_base@@Base+0x329850>
│ │  	str	r0, [r1, #0]
│ │  	b.n	4956f4 <uniffi_pbcli_checksum_method_api_base@@Base+0x328e70>
│ │ @@ -1445267,15 +1445267,15 @@
│ │  	lsrs	r7, r0, #11
│ │  	add.w	r0, r0, r4
│ │  	b.n	495ff6 <uniffi_pbcli_checksum_method_api_base@@Base+0x329772>
│ │  	lsrs	r1, r0, #11
│ │  	add.w	sl, r0, r4, lsr #32
│ │  			@ <UNDEFINED> instruction: 0xeb009db4
│ │  	vqrdmulh.s<illegal width 64>	<illegal reg q4.5>, <illegal reg q15.5>, d0[0]
│ │ -	vqrshrn.u64	d13, q8, #1
│ │ +			@ <UNDEFINED> instruction: 0xffbfd997
│ │  	vmul.f<illegal width 8>	<illegal reg q11.5>, q8, d0[7]
│ │  	movs	r4, r0
│ │  	ldr	r7, [pc, #960]	@ (496090 <uniffi_pbcli_checksum_method_api_base@@Base+0x32980c>)
│ │  	stmdb	sp!, {r2, r3, r4, ip, sp, pc}
│ │  	b.n	4961f0 <uniffi_pbcli_checksum_method_api_base@@Base+0x32996c>
│ │  	beq.n	495d00 <uniffi_pbcli_checksum_method_api_base@@Base+0x32947c>
│ │  	b.n	496174 <uniffi_pbcli_checksum_method_api_base@@Base+0x3298f0>
│ │ @@ -1445857,15 +1445857,15 @@
│ │  	lsrs	r1, r0, #6
│ │  	add.w	r0, r0, r4
│ │  	b.n	49650e <uniffi_pbcli_checksum_method_api_base@@Base+0x329c8a>
│ │  	lsrs	r3, r7, #5
│ │  	add.w	r8, r0, lr, lsl #3
│ │  			@ <UNDEFINED> instruction: 0xeb00989c
│ │  	vaddl.u<illegal width 64>	q4, d31, d14
│ │ -	vsri.32	<illegal reg q6.5>, q4, #1
│ │ +	vsri.32	<illegal reg q6.5>, <illegal reg q15.5>, #1
│ │  	vsri.64	<illegal reg q11.5>, q2, #64
│ │  	movs	r4, r0
│ │  	ldr	r0, [pc, #0]	@ (4961e8 <uniffi_pbcli_checksum_method_api_base@@Base+0x329964>)
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	49652e <uniffi_pbcli_checksum_method_api_base@@Base+0x329caa>
│ │  	movs	r1, r0
│ │  	b.n	496532 <uniffi_pbcli_checksum_method_api_base@@Base+0x329cae>
│ │ @@ -1446124,20 +1446124,20 @@
│ │  	b.n	496756 <uniffi_pbcli_checksum_method_api_base@@Base+0x329ed2>
│ │  	lsrs	r5, r5, #3
│ │  	add.w	r0, r0, r4
│ │  	b.n	49675e <uniffi_pbcli_checksum_method_api_base@@Base+0x329eda>
│ │  	lsrs	r7, r4, #3
│ │  	add.w	r8, r0, sl, rrx
│ │  			@ <UNDEFINED> instruction: 0xeb00964c
│ │ -	vqshl.u32	d0, d9, #31
│ │ -			@ <UNDEFINED> instruction: 0xffc0bb8f
│ │ +			@ <UNDEFINED> instruction: 0xffbf0740
│ │ +			@ <UNDEFINED> instruction: 0xffc0bbb6
│ │  	vsubl.u8	<illegal reg q11.5>, d16, d4
│ │  	movs	r4, r0
│ │  	str	r6, [sp, #528]	@ 0x210
│ │ -	vqshl.u32	q0, <illegal reg q0.5>, #31
│ │ +	vqshl.u32	q0, q12, #31
│ │  			@ <UNDEFINED> instruction: 0xffc0674f
│ │  	vrshr.u64	d7, d28, #2
│ │  	movs	r4, r0
│ │  	ldr	r0, [pc, #0]	@ (496448 <uniffi_pbcli_checksum_method_api_base@@Base+0x329bc4>)
│ │  	stmdb	sp!, {r0, r2, r3, ip, sp, pc}
│ │  	b.n	49678e <uniffi_pbcli_checksum_method_api_base@@Base+0x329f0a>
│ │  	movs	r1, r0
│ │ @@ -1446473,16 +1446473,16 @@
│ │  	b.n	496a7e <uniffi_pbcli_checksum_method_api_base@@Base+0x32a1fa>
│ │  	lsrs	r3, r4, #32
│ │  	add.w	r0, r0, r4
│ │  	b.n	496a86 <uniffi_pbcli_checksum_method_api_base@@Base+0x32a202>
│ │  	lsrs	r5, r3, #32
│ │  	add.w	r7, r0, r0, ror #1
│ │  			@ <UNDEFINED> instruction: 0xeb009324
│ │ -	vmla.i<illegal width 64>	<illegal reg q1.5>, <illegal reg q7.5>, d8[0]
│ │ -			@ <UNDEFINED> instruction: 0xffc003cf
│ │ +	vmla.i<illegal width 64>	<illegal reg q1.5>, <illegal reg q7.5>, d31[0]
│ │ +	vrsra.u64	q8, q11, #64
│ │  	vmov.f32	q11, #-3.5	@ 0xc0600000
│ │  	movs	r4, r0
│ │  	ldr	r5, [pc, #960]	@ (496b20 <uniffi_pbcli_checksum_method_api_base@@Base+0x32a29c>)
│ │  	stmdb	sp!, {r3, r4, ip, sp, pc}
│ │  	b.n	496c80 <uniffi_pbcli_checksum_method_api_base@@Base+0x32a3fc>
│ │  	beq.n	4967c8 <uniffi_pbcli_checksum_method_api_base@@Base+0x329f44>
│ │  	b.n	496c04 <uniffi_pbcli_checksum_method_api_base@@Base+0x32a380>
│ │ @@ -1447130,15 +1447130,15 @@
│ │  	add.w	r5, r0, ip, ror #3
│ │  	add.w	r0, r0, r0, lsl #1
│ │  	b.n	497222 <uniffi_pbcli_checksum_method_api_base@@Base+0x32a99e>
│ │  	movs	r0, r0
│ │  	b.n	496846 <uniffi_pbcli_checksum_method_api_base@@Base+0x329fc2>
│ │  	ldrh	r0, [r2, #32]
│ │  	ldmia.w	sp!, {r2, r4, r6, r8, sl, fp, pc}
│ │ -	vmla.i<illegal width 64>	q7, <illegal reg q15.5>, d2[0]
│ │ +	vmla.i<illegal width 64>	q7, <illegal reg q15.5>, d25[0]
│ │  	vmov.i32	<illegal reg q13.5>, #9240575	@ 0x008cffff
│ │  	vtbl.8	d6, {d30-d31}, d12
│ │  	movs	r4, r0
│ │  	ldr	r4, [pc, #64]	@ (496d7c <uniffi_pbcli_checksum_method_api_base@@Base+0x32a4f8>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	49725c <uniffi_pbcli_checksum_method_api_base@@Base+0x32a9d8>
│ │  	adds	r0, #2
│ │ @@ -1447957,15 +1447957,15 @@
│ │  	add.w	r4, r0, lr, asr #32
│ │  	add.w	r3, r0, r8, lsl #24
│ │  	movs	r4, r0
│ │  	str	r0, [r6, #48]	@ 0x30
│ │  	movs	r4, r0
│ │  	strh	r4, [r3, #48]	@ 0x30
│ │  	vtbx.8	d5, {d31-<overflow reg d32}, d14
│ │ -	vsra.u64	q6, <illegal reg q9.5>, #1
│ │ +	vrshr.u32	d12, d10, #1
│ │  	vmov.i32	q11, #33792	@ 0x00008400
│ │  	movs	r4, r0
│ │  	str	r0, [r5, #48]	@ 0x30
│ │  	movs	r4, r0
│ │  	strh	r4, [r2, #50]	@ 0x32
│ │  	vtbl.8	d5, {d15-d17}, d6
│ │  	vcvt.f32.u32	d9, d19, #1
│ │ @@ -1448966,15 +1448966,15 @@
│ │  	lsls	r0, r0, #5
│ │  	b.n	497824 <uniffi_pbcli_checksum_method_api_base@@Base+0x32afa0>
│ │  	movs	r0, r0
│ │  	b.n	497e08 <uniffi_pbcli_checksum_method_api_base@@Base+0x32b584>
│ │  	vrhadd.u16	d14, d14, d31
│ │  	strh	r4, [r1, #46]	@ 0x2e
│ │  			@ <UNDEFINED> instruction: 0xffbff765
│ │ -	vmovn.i<illegal width 128>	d6, <illegal reg q4.5>
│ │ +	vrshr.u32	d6, d16, #2
│ │  	vbic.i16	d25, #133	@ 0x0085
│ │  			@ <UNDEFINED> instruction: 0xffbe3faf
│ │  	vtbl.8	d6, {d31-<overflow reg d32}, d23
│ │  	vqrshrun.s64	d2, q0, #2
│ │  	vtbx.8	d14, {d31-<overflow reg d33}, d2
│ │  			@ <UNDEFINED> instruction: 0xffc098fc
│ │  			@ <UNDEFINED> instruction: 0xffbe98f3
│ │ @@ -1448983,76 +1448983,76 @@
│ │  	vcvt.u32.f32	<illegal reg q1.5>, q1, #2
│ │  			@ <UNDEFINED> instruction: 0xffbfc748
│ │  	vqshrn.u64	d6, q15, #1
│ │  			@ <UNDEFINED> instruction: 0xffbe9766
│ │  			@ <UNDEFINED> instruction: 0xffbf1ef8
│ │  	vshr.u32	<illegal reg q5.5>, <illegal reg q10.5>, #2
│ │  	vraddhn.i<illegal width 128>	d5, q7, q7
│ │ -	vcvt.u32.f32	d8, d12, #1
│ │ +	vqrdmlsh.s<illegal width 64>	q4, <illegal reg q7.5>, d3[0]
│ │  	vmov.i16	<illegal reg q12.5>, #138	@ 0x008a
│ │  	vtbl.8	d14, {d14-d16}, d5
│ │  	vmvn.i32	d19, #-1962934272	@ 0x8b000000
│ │ -	vrsubhn.i<illegal width 128>	d0, q15, q7
│ │ -	vqrdmlah.s<illegal width 8>	q12, q8, d3[4]
│ │ +	vqshlu.s64	d0, d21, #62	@ 0x3e
│ │ +			@ <UNDEFINED> instruction: 0xffc08f0a
│ │  	vqshlu.s64	<illegal reg q12.5>, q5, #0
│ │  	vqshrun.s64	d9, <illegal reg q2.5>, #1
│ │  	vcvt.u16.f16	d10, d13, #2
│ │  	vsli.64	<illegal reg q1.5>, q11, #63	@ 0x3f
│ │  	vqshlu.s64	d15, d20, #62	@ 0x3e
│ │ -	vsli.32	d10, d9, #30
│ │ -	vorr.i32	d26, #8454144	@ 0x00810000
│ │ +			@ <UNDEFINED> instruction: 0xffbea540
│ │ +	vbic.i32	d26, #8912896	@ 0x00880000
│ │  	vqshlu.s64	d31, d4, #0
│ │ -	vshll.i<illegal width 64>	<illegal reg q6.5>, d10, #<illegal width 64>
│ │ +	vrsra.u32	d13, d17, #2
│ │  	vsli.64	d19, d18, #0
│ │  	vabdl.u<illegal width 64>	<illegal reg q4.5>, d30, d29
│ │  	vrsra.u32	d5, d25, #2
│ │  			@ <UNDEFINED> instruction: 0xffbfaf88
│ │  	vrsubhn.i<illegal width 128>	d12, q15, q11
│ │  	vqshlu.s32	d9, d21, #30
│ │  	vsra.u32	d8, d6, #1
│ │  	vuzp.<illegal width 64>	d8, d14
│ │  	vqshl.u64	q3, q5, #62	@ 0x3e
│ │ -	vtbl.8	d11, {d14-d17}, d15
│ │ -	vqshlu.s64	<illegal reg q11.5>, <illegal reg q13.5>, #0
│ │ +			@ <UNDEFINED> instruction: 0xffbebb36
│ │ +	vabdl.u8	<illegal reg q11.5>, d0, d18
│ │  	vqrdmlsh.s<illegal width 8>	q10, q8, d2[7]
│ │  			@ <UNDEFINED> instruction: 0xffbe1d93
│ │  	vsli.64	<illegal reg q4.5>, <illegal reg q4.5>, #62	@ 0x3e
│ │  			@ <UNDEFINED> instruction: 0xffbf0e0f
│ │ -	vmlal.u<illegal width 64>	<illegal reg q6.5>, d15, d14[0]
│ │ -			@ <UNDEFINED> instruction: 0xffc01bf7
│ │ +	vrshr.u32	<illegal reg q6.5>, <illegal reg q10.5>, #1
│ │ +	vmov.i32	d17, #36607	@ 0x00008eff
│ │  	vshr.u64	d24, d10, #64
│ │ -			@ <UNDEFINED> instruction: 0xffbedaf8
│ │ +			@ <UNDEFINED> instruction: 0xffbedb1f
│ │  	vqrdmulh.s<illegal width 64>	<illegal reg q0.5>, <illegal reg q7.5>, d3[0]
│ │  	vqrdmlah.s<illegal width 64>	q5, q15, d0[0]
│ │  	vabal.u<illegal width 64>	<illegal reg q7.5>, d30, d4
│ │  			@ <UNDEFINED> instruction: 0xffbe1d22
│ │  	vqshlu.s32	q3, q9, #30
│ │  			@ <UNDEFINED> instruction: 0xffbf0d9a
│ │  	vqshl.u32	d6, d2, #31
│ │ -	vtbl.8	d1, {d30-<overflow reg d33}, d2
│ │ +	vtbl.8	d1, {d30-<overflow reg d33}, d25
│ │  	vmvn.i32	<illegal reg q12.5>, #-1996488704	@ 0x89000000
│ │  			@ <UNDEFINED> instruction: 0xffbeab7d
│ │ -	vrsra.u64	d10, d5, #1
│ │ +	vrsra.u64	d10, d28, #1
│ │  	vqrdmlah.s<illegal width 8>	q13, q0, d3[2]
│ │ -			@ <UNDEFINED> instruction: 0xffbeda5f
│ │ -	vqdmulh.s<illegal width 64>	q4, <illegal reg q15.5>, d30[0]
│ │ +	vtbl.8	d13, {d30-<overflow reg d32}, d6
│ │ +	vcvt.u16.f16	d8, d5, #1
│ │  			@ <UNDEFINED> instruction: 0xffc0ab45
│ │  	vsra.u64	d5, d29, #1
│ │ -	vqdmulh.s<illegal width 64>	q4, <illegal reg q15.5>, d14[0]
│ │ -	vmov.i32	q8, #9240576	@ 0x008d0000
│ │ +			@ <UNDEFINED> instruction: 0xffbf8cf5
│ │ +	vraddhn.i16	d16, q8, q2
│ │  	vmvn.i32	q14, #9175040	@ 0x008c0000
│ │ -	vmull.u<illegal width 64>	q4, d31, d30
│ │ +			@ <UNDEFINED> instruction: 0xffbf8cd5
│ │  	vmlsl.u<illegal width 8>	q11, d0, d2[7]
│ │ -			@ <UNDEFINED> instruction: 0xffbeb99f
│ │ -			@ <UNDEFINED> instruction: 0xffc0b997
│ │ -	vrshr.u64	q13, <illegal reg q14.5>, #64
│ │ +	vtbx.8	d11, {d30-d31}, d6
│ │ +			@ <UNDEFINED> instruction: 0xffc0b9be
│ │ +	vsubw.u8	q13, q0, d20
│ │  	vmvn.i32	d19, #33279	@ 0x000081ff
│ │  	vmull.u<illegal width 64>	q0, d31, d30
│ │  	vmull.u<illegal width 64>	q0, d31, d22
│ │ -			@ <UNDEFINED> instruction: 0xffbfd3e9
│ │ +	vsri.32	d13, d0, #1
│ │  	vmov.i32	d20, #33023	@ 0x000080ff
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	498354 <uniffi_pbcli_checksum_method_api_base@@Base+0x32bad0>
│ │  	asrs	r0, r6, #32
│ │  	b.n	49797c <uniffi_pbcli_checksum_method_api_base@@Base+0x32b0f8>
│ │  	movs	r0, #48	@ 0x30
│ │  	b.n	497980 <uniffi_pbcli_checksum_method_api_base@@Base+0x32b0fc>
│ │ @@ -1449074,15 +1449074,15 @@
│ │  	b.n	4981a2 <uniffi_pbcli_checksum_method_api_base@@Base+0x32b91e>
│ │  	lsls	r2, r3, #9
│ │  	add.w	r0, r0, r4
│ │  	b.n	4981aa <uniffi_pbcli_checksum_method_api_base@@Base+0x32b926>
│ │  	lsls	r4, r2, #9
│ │  	add.w	r1, r0, r7, asr #2
│ │  	add.w	ip, r0, r0, lsl #28
│ │ -			@ <UNDEFINED> instruction: 0xffbf8af6
│ │ +			@ <UNDEFINED> instruction: 0xffbf8b1d
│ │  	vraddhn.i16	d22, q0, <illegal reg q0.5>
│ │  	vqshrun.s64	d5, q12, #1
│ │  	movs	r4, r0
│ │  	ldr	r4, [pc, #64]	@ (497ec4 <uniffi_pbcli_checksum_method_api_base@@Base+0x32b640>)
│ │  	stmdb	sp!, {r3, ip, sp, pc}
│ │  	b.n	4983a4 <uniffi_pbcli_checksum_method_api_base@@Base+0x32bb20>
│ │  	asrs	r0, r6, #32
│ ├── readelf --wide --decompress --hex-dump=.data.rel.ro {}
│ │ @@ -2069,42 +2069,42 @@
│ │    0x004a1b30 28352000 c4702500 80b81f00 f8b91f00 (5 ..p%.........
│ │    0x004a1b40 f0b61f00 e88c1f00 18ba1f00 d4b71f00 ................
│ │    0x004a1b50 0c012400 2c8e1f00 2c8f1f00 2c871f00 ..$.,...,...,...
│ │    0x004a1b60 e8a01f00 a4ad1f00 2cae1f00 9c1c2400 ........,.....$.
│ │    0x004a1b70 34931f00 3c931f00 f4821f00 c81b4a00 4...<.........J.
│ │    0x004a1b80 0c742000 54a01f00 cca91f00 00000000 .t .T...........
│ │    0x004a1b90 20da2000 30e02000 70d72000 34dc2000  . .0. .p. .4. .
│ │ -  0x004a1ba0 61090a00 0f000000 872a0800 0f000000 a........*......
│ │ +  0x004a1ba0 88090a00 0f000000 872a0800 0f000000 .........*......
│ │    0x004a1bb0 f0e32000 74e12000 08000000 a8092600 .. .t. .......&.
│ │    0x004a1bc0 740a2600 ec821f00 20da2000 30e02000 t.&..... . .0. .
│ │ -  0x004a1bd0 70d72000 34dc2000 61090a00 0f000000 p. .4. .a.......
│ │ +  0x004a1bd0 70d72000 34dc2000 88090a00 0f000000 p. .4. .........
│ │    0x004a1be0 872a0800 0f000000 f0e32000 74e12000 .*........ .t. .
│ │    0x004a1bf0 1e000000 a8092600 740a2600 ec821f00 ......&.t.&.....
│ │    0x004a1c00 01000000 10000000 1c1c4a00 1a000000 ..........J.....
│ │    0x004a1c10 00000000 80000000 34fd0700 00100000 ........4.......
│ │    0x004a1c20 00000000 00000000 ea8a0800 0c9d2700 ..............'.
│ │ -  0x004a1c30 00100000 00000000 04000000 074f0a00 .............O..
│ │ +  0x004a1c30 00100000 00000000 04000000 2e4f0a00 .............O..
│ │    0x004a1c40 fc9c2700 00000000 00000000 08000000 ..'.............
│ │ -  0x004a1c50 9a980900 34912700 00000000 00000000 ....4.'.........
│ │ -  0x004a1c60 14000000 18dd0900 34912700 00000000 ........4.'.....
│ │ -  0x004a1c70 00000000 10000000 d4370a00 34912700 .........7..4.'.
│ │ -  0x004a1c80 89000000 00000000 18000000 23dd0900 ............#...
│ │ +  0x004a1c50 c1980900 34912700 00000000 00000000 ....4.'.........
│ │ +  0x004a1c60 14000000 3fdd0900 34912700 00000000 ....?...4.'.....
│ │ +  0x004a1c70 00000000 10000000 fb370a00 34912700 .........7..4.'.
│ │ +  0x004a1c80 89000000 00000000 18000000 4add0900 ............J...
│ │    0x004a1c90 34912700 91100000 01000000 20000000 4.'......... ...
│ │ -  0x004a1ca0 22580900 3c9d2700 91100000 02000000 "X..<.'.........
│ │ +  0x004a1ca0 49580900 3c9d2700 91100000 02000000 IX..<.'.........
│ │    0x004a1cb0 28000000 685b0800 3c9d2700 91000000 (...h[..<.'.....
│ │    0x004a1cc0 03000000 30000000 32cf0800 4cd43800 ....0...2...L.8.
│ │    0x004a1cd0 91000000 04000000 34000000 705b0800 ........4...p[..
│ │    0x004a1ce0 34912700 91100000 05000000 38000000 4.'.........8...
│ │ -  0x004a1cf0 e2c50900 1c9d2700 91000000 06000000 ......'.........
│ │ +  0x004a1cf0 09c60900 1c9d2700 91000000 06000000 ......'.........
│ │    0x004a1d00 3c000000 65e30800 34912700 91000000 <...e...4.'.....
│ │    0x004a1d10 07000000 50000000 45fd0700 34912700 ....P...E...4.'.
│ │    0x004a1d20 91000000 08000000 54000000 ba130800 ........T.......
│ │    0x004a1d30 34912700 91100000 09000000 40000000 4.'.........@...
│ │    0x004a1d40 75e30800 4c9d2700 91000000 0a000000 u...L.'.........
│ │ -  0x004a1d50 4c000000 11210a00 34912700 91000000 L....!..4.'.....
│ │ +  0x004a1d50 4c000000 38210a00 34912700 91000000 L...8!..4.'.....
│ │    0x004a1d60 0b000000 0c000000 47800700 34912700 ........G...4.'.
│ │    0x004a1d70 91000000 0c000000 58000000 76cc0700 ........X...v...
│ │    0x004a1d80 34912700 91100000 0d000000 60000000 4.'.........`...
│ │    0x004a1d90 4de40700 4c9d2700 91100000 0e000000 M...L.'.........
│ │    0x004a1da0 48000000 bab90800 2c9d2700 91100000 H.......,.'.....
│ │    0x004a1db0 0f000000 68000000 53e40700 2c9d2700 ....h...S...,.'.
│ │    0x004a1dc0 91000000 10000000 6c000000 0cfc0800 ........l.......
│ │ @@ -2141,43 +2141,43 @@
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│ │ -  0x004a20a0 00000000 00000000 c7ad0900 00000000 ................
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│ │    0x004a23c0 00000000 00000000 00000000 00000000 ................
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│ │    0x004a2430 00000000 00000000 20000000 00000000 ........ .......
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│ │    0x004a2450 00000000 00000000 00000000 00000000 ................
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│ │    0x004a2490 00000000 00000000 00000000 00000000 ................
│ │ -  0x004a24a0 00000000 00000000 d4ad0900 00000000 ................
│ │ +  0x004a24a0 00000000 00000000 fbad0900 00000000 ................
│ │    0x004a24b0 00000000 00000000 a0000000 00000000 ................
│ │    0x004a24c0 00000000 00000000 00000000 00000000 ................
│ │    0x004a24d0 00000000 00000000 00000000 00000000 ................
│ │    0x004a24e0 00000000 00000000 122c0800 00000000 .........,......
│ │    0x004a24f0 00000000 00000000 40000000 00000000 ........@.......
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│ │ +  0x004a25a0 00000000 00000000 27c60900 00000000 ........'.......
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│ │    0x004a25c0 00000000 00000000 00000000 00000000 ................
│ │    0x004a25d0 00000000 00000000 00000000 00000000 ................
│ │    0x004a25e0 00000000 00000000 73800700 00000000 ........s.......
│ │    0x004a25f0 00000000 04000000 fbffffff 00000000 ................
│ │    0x004a2600 00000000 00000000 00000000 00000000 ................
│ │    0x004a2610 00000000 00000000 00000000 00000000 ................
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│ │    0x004a26a0 00000000 00000000 a5a30800 00000000 ................
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│ │    0x004a2730 00000000 c8010000 00000000 00000000 ................
│ │    0x004a2740 00000000 00000000 00000000 00000000 ................
│ │    0x004a2750 00000000 00000000 00000000 00000000 ................
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│ │    0x004a27b0 00000000 00000000 00000000 02000000 ................
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│ │    0x004a27d0 00000000 00000000 00000000 00000000 ................
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│ │    0x004a2810 00000000 00000000 00000000 00000000 ................
│ │    0x004a2820 00000000 00000000 0f420900 00000000 .........B......
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│ │    0x004a2840 00000000 00000000 00000000 00000000 ................
│ │    0x004a2850 00000000 00000000 00000000 00000000 ................
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│ │ +  0x004a2860 00000000 00000000 38820900 00000000 ........8.......
│ │    0x004a2870 00000000 00000000 00000000 10000000 ................
│ │    0x004a2880 00000000 00000000 00000000 00000000 ................
│ │    0x004a2890 00000000 00000000 00000000 00000000 ................
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│ │    0x004a28b0 00000000 00000000 00000000 00080000 ................
│ │    0x004a28c0 00000000 00000000 00000000 00000000 ................
│ │    0x004a28d0 00000000 00000000 00000000 00000000 ................
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│ │    0x004a28f0 00000000 00000000 00000000 20000000 ............ ...
│ │    0x004a2900 00000000 00000000 00000000 00000000 ................
│ │    0x004a2910 00000000 00000000 00000000 00000000 ................
│ │ -  0x004a2920 00000000 00000000 2d580900 00000000 ........-X......
│ │ +  0x004a2920 00000000 00000000 54580900 00000000 ........TX......
│ │    0x004a2930 00000000 00000000 00000000 0004c400 ................
│ │    0x004a2940 00000000 00000000 00000000 00000000 ................
│ │    0x004a2950 00000000 00000000 00000000 00000000 ................
│ │    0x004a2960 00000000 00000000 328b0800 00000000 ........2.......
│ │    0x004a2970 00000000 00000000 00000000 40500100 ............@P..
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│ │    0x004a2990 00000000 00000000 00000000 00000000 ................
│ │ -  0x004a29a0 00000000 00000000 7d0a0a00 00000000 ........}.......
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│ │    0x004a29e0 00000000 00000000 a9a30800 00000000 ................
│ │    0x004a29f0 00000000 00000000 00000000 c0f00300 ................
│ │    0x004a2a00 00000000 00000000 00000000 00000000 ................
│ │    0x004a2a10 00000000 00000000 00000000 00000000 ................
│ │ @@ -2313,15 +2313,15 @@
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│ │    0x004a2a80 00000000 00000000 00000000 00000000 ................
│ │    0x004a2a90 00000000 00000000 00000000 00000000 ................
│ │    0x004a2aa0 00000000 00000000 9ae30800 00000000 ................
│ │    0x004a2ab0 00000000 00000000 00000000 00000300 ................
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│ │    0x004a2b30 00000000 00000000 00000000 00020000 ................
│ │    0x004a2b40 00000000 00000000 00000000 00000000 ................
│ │    0x004a2b50 00000000 00000000 00000000 00000000 ................
│ │ @@ -2341,15 +2341,15 @@
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│ │    0x004a2c50 00000000 00000000 00000000 00000000 ................
│ │    0x004a2c60 00000000 00000000 aecc0700 00000000 ................
│ │    0x004a2c70 00000000 00000000 00000000 00003000 ..............0.
│ │    0x004a2c80 00000000 00000000 00000000 00000000 ................
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│ │ +  0x004a2ca0 00000000 00000000 3d820900 00000000 ........=.......
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│ │    0x004a2cf0 00000000 00000000 00000000 00002000 .............. .
│ │    0x004a2d00 00000000 00000000 00000000 00000000 ................
│ │    0x004a2d10 00000000 00000000 00000000 00000000 ................
│ │ @@ -2357,51 +2357,51 @@
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│ │    0x004a2d40 00000000 00000000 00000000 00000000 ................
│ │    0x004a2d50 00000000 00000000 00000000 00000000 ................
│ │    0x004a2d60 00000000 00000000 8fe30800 00000000 ................
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│ │    0x004a2d90 00000000 00000000 00000000 00000000 ................
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│ │    0x004a2e10 00000000 00000000 00000000 00000000 ................
│ │    0x004a2e20 00000000 00000000 89cc0700 00000000 ................
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│ │    0x004a2e50 00000000 00000000 00000000 00000000 ................
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│ │ +  0x004a2e60 00000000 00000000 5b580900 00000000 ........[X......
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│ │    0x004a2e90 00000000 00000000 00000000 00000000 ................
│ │    0x004a2ea0 00000000 00000000 93e30800 00000000 ................
│ │    0x004a2eb0 00000000 00000000 00000000 00000000 ................
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│ │    0x004a2ed0 00000000 00000000 00000000 00000000 ................
│ │ -  0x004a2ee0 00000000 00000000 760a0a00 00000000 ........v.......
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│ │    0x004a2f00 20000000 00000000 00000000 00000000  ...............
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│ │ -  0x004a2f20 00000000 00000000 6f0a0a00 00000000 ........o.......
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│ │    0x004a2f40 80000000 00000000 00000000 00000000 ................
│ │    0x004a2f50 00000000 00000000 00000000 00000000 ................
│ │    0x004a2f60 00000000 00000000 6be40700 00000000 ........k.......
│ │    0x004a2f70 00000000 00000000 00000000 00000000 ................
│ │    0x004a2f80 00000000 00030000 00000000 00000000 ................
│ │    0x004a2f90 00000000 00000000 00000000 00000000 ................
│ │    0x004a2fa0 00000000 00000000 172c0800 00000000 .........,......
│ │    0x004a2fb0 00000000 00000000 00000000 00000000 ................
│ │    0x004a2fc0 00000000 01030000 00000000 00000000 ................
│ │    0x004a2fd0 00000000 00000000 00000000 00000000 ................
│ │ -  0x004a2fe0 00000000 00000000 0e6d0900 00000000 .........m......
│ │ +  0x004a2fe0 00000000 00000000 356d0900 00000000 ........5m......
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│ │    0x004a3000 00000000 01030000 00000000 00000000 ................
│ │    0x004a3010 00000000 00000000 00000000 00000000 ................
│ │    0x004a3020 00000000 00000000 ac5b0800 00000000 .........[......
│ │    0x004a3030 00000000 00000000 00000000 00000000 ................
│ │    0x004a3040 00000000 03030000 00000000 00000000 ................
│ │    0x004a3050 00000000 00000000 00000000 00000000 ................
│ │ @@ -2417,395 +2417,395 @@
│ │    0x004a30f0 00000000 00000000 00000000 00000000 ................
│ │    0x004a3100 00000000 00000000 00000000 00000000 ................
│ │    0x004a3110 00000000 08000000 00000000 00000000 ................
│ │    0x004a3120 00000000 00000000 d9130800 00000000 ................
│ │    0x004a3130 00000000 00000000 00000000 dfffffff ................
│ │    0x004a3140 00000000 00000000 00000000 00000000 ................
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│ │    0x004a3170 00000000 02000000 02000000 02000000 ................
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│ │    0x004a3190 00000000 18000000 00000000 00000000 ................
│ │    0x004a31a0 00000000 00000000 659a0700 00000000 ........e.......
│ │    0x004a31b0 00000000 02000000 01000000 02000000 ................
│ │    0x004a31c0 02000000 00000000 00000000 00000000 ................
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│ │    0x004a31e0 00000000 2301000a 71e40700 6400000a ....#...q...d...
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│ │    0x004a32d0 12ba0800 bb01000a 512c0800 7700000a ........Q,..w...
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│ │ -  0x004a3320 c6cc0700 fd00000a 3e580900 8000000a ........>X......
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│ │ -  0x004a3340 840a0a00 ea00000a fb980900 6d00000a ............m...
│ │ +  0x004a3320 c6cc0700 fd00000a 65580900 8000000a ........eX......
│ │ +  0x004a3330 c4e40700 8100000a 2dc60900 8200000a ........-.......
│ │ +  0x004a3340 ab0a0a00 ea00000a 22990900 6d00000a ........"...m...
│ │    0x004a3350 1d290900 2b01000a b3430800 8300000a .)..+....C......
│ │ -  0x004a3360 1e820900 8d01000a 50210a00 8e01000a ........P!......
│ │ -  0x004a3370 65fd0700 8500000a f2ad0900 8600000a e...............
│ │ -  0x004a3380 55580900 7901000a 6f580900 8700000a UX..y...oX......
│ │ +  0x004a3360 45820900 8d01000a 77210a00 8e01000a E.......w!......
│ │ +  0x004a3370 65fd0700 8500000a 19ae0900 8600000a e...............
│ │ +  0x004a3380 7c580900 7901000a 96580900 8700000a |X..y....X......
│ │    0x004a3390 34ba0800 da00000a 54fc0800 8900000a 4.......T.......
│ │    0x004a33a0 73fc0800 e200000a 3a730800 8c00000a s.......:s......
│ │ -  0x004a33b0 7a9a0700 5701000a 05ae0900 8d00000a z...W...........
│ │ +  0x004a33b0 7a9a0700 5701000a 2cae0900 8d00000a z...W...,.......
│ │    0x004a33c0 3e120900 3301000a fe130800 8e00000a >...3...........
│ │    0x004a33d0 f6b10700 9000000a b45b0800 6401000a .........[..d...
│ │    0x004a33e0 32290900 a700000a d0e40700 9001000a 2)..............
│ │    0x004a33f0 bde30800 3401000a c9a30800 2801000a ....4.......(...
│ │    0x004a3400 49ba0800 ce00000a 959a0700 ac00000a I...............
│ │    0x004a3410 74fd0700 ad00000a 608b0800 af00000a t.......`.......
│ │ -  0x004a3420 60ba0800 b400000a 7d580900 b800000a `.......}X......
│ │ +  0x004a3420 60ba0800 b400000a a4580900 b800000a `........X......
│ │    0x004a3430 d9a30800 bd00000a 26140800 c000000a ........&.......
│ │ -  0x004a3440 92800700 c800000a 34820900 c900000a ........4.......
│ │ +  0x004a3440 92800700 c800000a 5b820900 c900000a ........[.......
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│ │ -  0x004a3460 a3fc0800 9100000a 50820900 9200000a ........P.......
│ │ -  0x004a3470 354f0a00 9300000a f9a30800 1901000a 5O..............
│ │ -  0x004a3480 18f30900 8a01000a 8d2c0800 9400000a .........,......
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│ │ -  0x004ab330 00000000 02000000 01100000 e4e30900 ................
│ │ +  0x004ab330 00000000 02000000 01100000 0be40900 ................
│ │    0x004ab340 00000000 39910800 02000000 00000000 ....9...........
│ │    0x004ab350 02000000 74000000 00000000 02000000 ....t...........
│ │    0x004ab360 02100000 aa040800 00000000 6f790800 ............oy..
│ │    0x004ab370 02000000 00000000 02000000 74000000 ............t...
│ │    0x004ab380 00000000 02000000 03100000 46ed0700 ............F...
│ │    0x004ab390 00000000 20820700 04000000 dc223000 .... ........"0.
│ │    0x004ab3a0 02000000 98010000 00000000 06000000 ................
│ │    0x004ab3b0 02100000 ce880700 00000000 84600800 .............`..
│ │    0x004ab3c0 04000000 4c273000 02000000 98010000 ....L'0.........
│ │    0x004ab3d0 00000000 06000000 01100000 0dd50800 ................
│ │ -  0x004ab3e0 00000000 a4860900 04000000 a4283000 .............(0.
│ │ +  0x004ab3e0 00000000 cb860900 04000000 a4283000 .............(0.
│ │    0x004ab3f0 00000000 98010000 00000000 00080000 ................
│ │    0x004ab400 03100000 c6470900 00000000 07a10700 .....G..........
│ │    0x004ab410 01000000 68293000 00000000 98010000 ....h)0.........
│ │    0x004ab420 00000000 00080000 04100000 00000000 ................
│ │    0x004ab430 00000000 a1040800 04000000 682a3000 ............h*0.
│ │    0x004ab440 02000000 98010000 00000000 00080000 ................
│ │    0x004ab450 05100000 e61a0800 00000000 c51a0800 ................
│ │ @@ -4522,23 +4522,23 @@
│ │    0x004ab480 00000000 c51a0800 04000000 dc223000 ............."0.
│ │    0x004ab490 02000000 98010000 00000000 00080000 ................
│ │    0x004ab4a0 07100000 00000000 00000000 23030900 ............#...
│ │    0x004ab4b0 02000000 00000000 01000000 98010000 ................
│ │    0x004ab4c0 00000000 00080000 08100000 00000000 ................
│ │    0x004ab4d0 00000000 23030900 02000000 00000000 ....#...........
│ │    0x004ab4e0 02000000 98010000 00000000 00080000 ................
│ │ -  0x004ab4f0 09100000 00000000 00000000 2ecd0900 ................
│ │ +  0x004ab4f0 09100000 00000000 00000000 55cd0900 ............U...
│ │    0x004ab500 05000000 00000000 01000000 98010000 ................
│ │    0x004ab510 00000000 00080000 0a100000 00000000 ................
│ │ -  0x004ab520 00000000 2ecd0900 07000000 00000000 ................
│ │ +  0x004ab520 00000000 55cd0900 07000000 00000000 ....U...........
│ │    0x004ab530 02000000 94040000 00000000 06000000 ................
│ │    0x004ab540 02100000 ce880700 00000000 84600800 .............`..
│ │    0x004ab550 04000000 4c273000 02000000 94040000 ....L'0.........
│ │    0x004ab560 00000000 06000000 01100000 0dd50800 ................
│ │ -  0x004ab570 00000000 a4860900 04000000 a4283000 .............(0.
│ │ +  0x004ab570 00000000 cb860900 04000000 a4283000 .............(0.
│ │    0x004ab580 00000000 94040000 00000000 00080000 ................
│ │    0x004ab590 03100000 c6470900 00000000 07a10700 .....G..........
│ │    0x004ab5a0 01000000 68293000 00000000 94040000 ....h)0.........
│ │    0x004ab5b0 00000000 00080000 04100000 00000000 ................
│ │    0x004ab5c0 00000000 a1040800 04000000 682a3000 ............h*0.
│ │    0x004ab5d0 02000000 94040000 00000000 00080000 ................
│ │    0x004ab5e0 05100000 e61a0800 00000000 c51a0800 ................
│ │ @@ -4547,80 +4547,80 @@
│ │    0x004ab610 00000000 c51a0800 04000000 dc223000 ............."0.
│ │    0x004ab620 02000000 94040000 00000000 00080000 ................
│ │    0x004ab630 07100000 00000000 00000000 23030900 ............#...
│ │    0x004ab640 02000000 00000000 01000000 94040000 ................
│ │    0x004ab650 00000000 00080000 08100000 00000000 ................
│ │    0x004ab660 00000000 23030900 02000000 00000000 ....#...........
│ │    0x004ab670 02000000 94040000 00000000 00080000 ................
│ │ -  0x004ab680 09100000 00000000 00000000 2ecd0900 ................
│ │ +  0x004ab680 09100000 00000000 00000000 55cd0900 ............U...
│ │    0x004ab690 05000000 00000000 01000000 94040000 ................
│ │    0x004ab6a0 00000000 00080000 0a100000 00000000 ................
│ │ -  0x004ab6b0 00000000 2ecd0900 07000000 00000000 ................
│ │ +  0x004ab6b0 00000000 55cd0900 07000000 00000000 ....U...........
│ │    0x004ab6c0 02000000 06000000 90030000 f0c70000 ................
│ │ -  0x004ab6d0 01100000 edb40900 00000000 f21a0800 ................
│ │ +  0x004ab6d0 01100000 14b50900 00000000 f21a0800 ................
│ │    0x004ab6e0 04000000 782a3000 01000000 06000000 ....x*0.........
│ │    0x004ab6f0 90030000 f0c70000 06100000 00000000 ................
│ │    0x004ab700 00000000 f21a0800 04000000 782a3000 ............x*0.
│ │    0x004ab710 02000000 06000000 90030000 f0c70000 ................
│ │ -  0x004ab720 05100000 60630800 00000000 ea550a00 ....`c.......U..
│ │ +  0x004ab720 05100000 60630800 00000000 11560a00 ....`c.......V..
│ │    0x004ab730 04000000 dc223000 01000000 06000000 ....."0.........
│ │    0x004ab740 90030000 f0c70000 08100000 00000000 ................
│ │ -  0x004ab750 00000000 ea550a00 04000000 dc223000 .....U......."0.
│ │ +  0x004ab750 00000000 11560a00 04000000 dc223000 .....V......."0.
│ │    0x004ab760 02000000 06000000 90030000 f0c10000 ................
│ │ -  0x004ab770 02100000 3c9e0900 00000000 39920800 ....<.......9...
│ │ +  0x004ab770 02100000 639e0900 00000000 39920800 ....c.......9...
│ │    0x004ab780 04000000 1c2e3000 01000000 06000000 ......0.........
│ │    0x004ab790 90030000 f0c10000 07100000 00000000 ................
│ │    0x004ab7a0 00000000 39920800 04000000 1c2e3000 ....9.........0.
│ │    0x004ab7b0 02000000 06000000 00000000 00060000 ................
│ │    0x004ab7c0 09100000 1fd50800 00000000 20820700 ............ ...
│ │    0x004ab7d0 04000000 dc223000 01000000 06000000 ....."0.........
│ │    0x004ab7e0 00000000 00060000 0b100000 00000000 ................
│ │    0x004ab7f0 00000000 20820700 04000000 dc223000 .... ........"0.
│ │    0x004ab800 02000000 06000000 00000000 00060000 ................
│ │    0x004ab810 0a100000 00000000 45ba0700 90190900 ........E.......
│ │    0x004ab820 05000000 00000000 01000000 06000000 ................
│ │    0x004ab830 00000000 00060000 0c100000 00000000 ................
│ │    0x004ab840 00000000 90190900 07000000 00000000 ................
│ │    0x004ab850 02000000 06000000 00000000 00060000 ................
│ │ -  0x004ab860 0e100000 00000000 d9470900 f6550a00 .........G...U..
│ │ +  0x004ab860 0e100000 00000000 d9470900 1d560a00 .........G...V..
│ │    0x004ab870 02000000 00000000 02000000 90030000 ................
│ │ -  0x004ab880 00000000 06000000 01000000 2df90900 ............-...
│ │ +  0x004ab880 00000000 06000000 01000000 54f90900 ............T...
│ │    0x004ab890 00000000 20820700 04000000 dc223000 .... ........"0.
│ │    0x004ab8a0 02000000 90030000 00000000 06000000 ................
│ │ -  0x004ab8b0 05100000 7ba10700 00000000 ea550a00 ....{........U..
│ │ +  0x004ab8b0 05100000 7ba10700 00000000 11560a00 ....{........V..
│ │    0x004ab8c0 04000000 dc223000 02000000 90030000 ....."0.........
│ │ -  0x004ab8d0 00000000 06000000 02100000 74270a00 ............t'..
│ │ +  0x004ab8d0 00000000 06000000 02100000 9b270a00 .............'..
│ │    0x004ab8e0 00000000 39920800 01000000 00000000 ....9...........
│ │    0x004ab8f0 02000000 06000000 90030000 04000000 ................
│ │    0x004ab900 03100000 db880700 00000000 13320900 .............2..
│ │    0x004ab910 02000000 00000000 02000000 06000000 ................
│ │    0x004ab920 90030000 04000000 04100000 f6470900 .............G..
│ │    0x004ab930 00000000 2e030900 02000000 00000000 ................
│ │    0x004ab940 02000000 06000000 90030000 04000000 ................
│ │    0x004ab950 0d100000 46aa0800 00000000 eb880700 ....F...........
│ │    0x004ab960 02000000 00000000 02000000 ffffffff ................
│ │    0x004ab970 ffffffff f0c10000 0e000000 08480900 .............H..
│ │    0x004ab980 00000000 b5d40800 02000000 00000000 ................
│ │    0x004ab990 02000000 ffffffff ffffffff 00080000 ................
│ │ -  0x004ab9a0 00100000 3e3f0a00 00000000 20820700 ....>?...... ...
│ │ +  0x004ab9a0 00100000 653f0a00 00000000 20820700 ....e?...... ...
│ │    0x004ab9b0 04000000 dc223000 02000000 ffffffff ....."0.........
│ │    0x004ab9c0 ffffffff 00080000 01100000 7d150800 ............}...
│ │ -  0x004ab9d0 09560a00 7d150800 05000000 00000000 .V..}...........
│ │ +  0x004ab9d0 30560a00 7d150800 05000000 00000000 0V..}...........
│ │    0x004ab9e0 02000000 ffffffff ffffffff 00080000 ................
│ │    0x004ab9f0 02100000 eae40800 58aa0800 eae40800 ........X.......
│ │    0x004aba00 05000000 00000000 02000000 ffffffff ................
│ │ -  0x004aba10 ffffffff 00080000 03100000 3e3f0a00 ............>?..
│ │ +  0x004aba10 ffffffff 00080000 03100000 653f0a00 ............e?..
│ │    0x004aba20 00000000 20820700 04000000 dc223000 .... ........"0.
│ │    0x004aba30 02000000 ffffffff ffffffff 00080000 ................
│ │    0x004aba40 04100000 df9b0700 9b190900 df9b0700 ................
│ │    0x004aba50 05000000 00000000 02000000 ffffffff ................
│ │    0x004aba60 ffffffff 00080000 05100000 36150800 ............6...
│ │    0x004aba70 41920800 36150800 05000000 00000000 A...6...........
│ │    0x004aba80 02000000 ffffffff ffffffff 00080000 ................
│ │ -  0x004aba90 06100000 fb1a0800 4c9e0900 fb1a0800 ........L.......
│ │ +  0x004aba90 06100000 fb1a0800 739e0900 fb1a0800 ........s.......
│ │    0x004abaa0 05000000 00000000 02000000 ffffffff ................
│ │    0x004abab0 ffffffff 00080000 07100000 dce50700 ................
│ │    0x004abac0 00000000 dce50700 01000000 e42f3000 ............./0.
│ │    0x004abad0 02000000 ffffffff ffffffff 00080000 ................
│ │    0x004abae0 08100000 744a0800 001b0800 744a0800 ....tJ......tJ..
│ │    0x004abaf0 05000000 00000000 02000000 ffffffff ................
│ │    0x004abb00 ffffffff 00080000 09100000 df9b0700 ................
│ │ @@ -4629,151 +4629,151 @@
│ │    0x004abb30 0a100000 f5320800 00000000 35320900 .....2......52..
│ │    0x004abb40 02000000 00000000 02000000 ffffffff ................
│ │    0x004abb50 ffffffff 00080000 0b100000 a3450900 .............E..
│ │    0x004abb60 00000000 a3450900 02000000 00000000 .....E..........
│ │    0x004abb70 02000000 ffffffff ffffffff 00080000 ................
│ │    0x004abb80 0c100000 04430900 00000000 04430900 .....C.......C..
│ │    0x004abb90 02000000 00000000 02000000 ffffffff ................
│ │ -  0x004abba0 ffffffff 00080000 0d100000 3ff90900 ............?...
│ │ -  0x004abbb0 00000000 3ff90900 02000000 00000000 ....?...........
│ │ +  0x004abba0 ffffffff 00080000 0d100000 66f90900 ............f...
│ │ +  0x004abbb0 00000000 66f90900 02000000 00000000 ....f...........
│ │    0x004abbc0 02000000 ffffffff ffffffff 04060000 ................
│ │ -  0x004abbd0 0c000000 00000000 00000000 9a980900 ................
│ │ +  0x004abbd0 0c000000 00000000 00000000 c1980900 ................
│ │    0x004abbe0 04000000 3c313000 02000000 ffffffff ....<10.........
│ │    0x004abbf0 ffffffff 04000000 06000000 36150800 ............6...
│ │ -  0x004abc00 41920800 22250a00 05000000 00000000 A..."%..........
│ │ +  0x004abc00 41920800 49250a00 05000000 00000000 A...I%..........
│ │    0x004abc10 02000000 ffffffff ffffffff f0c10000 ................
│ │    0x004abc20 01000000 00000000 00000000 20820700 ............ ...
│ │    0x004abc30 04000000 dc223000 01000000 ffffffff ....."0.........
│ │    0x004abc40 ffffffff f0c10000 0d000000 00000000 ................
│ │    0x004abc50 00000000 20820700 04000000 dc223000 .... ........"0.
│ │    0x004abc60 02000000 0a040000 0a040000 04000000 ................
│ │ -  0x004abc70 ffffffff 00000000 00000000 a4860900 ................
│ │ +  0x004abc70 ffffffff 00000000 00000000 cb860900 ................
│ │    0x004abc80 04000000 6c323000 02000000 0a040000 ....l20.........
│ │    0x004abc90 0a040000 02000000 ffffffff 00000000 ................
│ │ -  0x004abca0 00000000 a4860900 04000000 6c323000 ............l20.
│ │ +  0x004abca0 00000000 cb860900 04000000 6c323000 ............l20.
│ │    0x004abcb0 02000000 0b040000 0b040000 04000000 ................
│ │ -  0x004abcc0 ffffffff 00000000 00000000 a4860900 ................
│ │ +  0x004abcc0 ffffffff 00000000 00000000 cb860900 ................
│ │    0x004abcd0 04000000 6c323000 02000000 0b040000 ....l20.........
│ │    0x004abce0 0b040000 02000000 ffffffff 00000000 ................
│ │ -  0x004abcf0 00000000 a4860900 04000000 6c323000 ............l20.
│ │ -  0x004abd00 01000000 b2f40900 02000000 13560a00 .............V..
│ │ -  0x004abd10 00000000 00000000 01000000 b2f40900 ................
│ │ +  0x004abcf0 00000000 cb860900 04000000 6c323000 ............l20.
│ │ +  0x004abd00 01000000 d9f40900 02000000 3a560a00 ............:V..
│ │ +  0x004abd10 00000000 00000000 01000000 d9f40900 ................
│ │    0x004abd20 02000000 f7320800 00000000 00000000 .....2..........
│ │ -  0x004abd30 01000000 aa740900 03000000 87180800 .....t..........
│ │ -  0x004abd40 04000000 feb40900 04000000 60aa0800 ............`...
│ │ -  0x004abd50 05000000 413f0a00 06000000 463f0a00 ....A?......F?..
│ │ +  0x004abd30 01000000 d1740900 03000000 87180800 .....t..........
│ │ +  0x004abd40 04000000 25b50900 04000000 60aa0800 ....%.......`...
│ │ +  0x004abd50 05000000 683f0a00 06000000 6d3f0a00 ....h?......m?..
│ │    0x004abd60 07000000 00000000 ffffffff 20820700 ............ ...
│ │    0x004abd70 fdffffff 409f0700 feffffff 662d0800 ....@.......f-..
│ │ -  0x004abd80 00000000 48920800 01000000 115f0900 ....H........_..
│ │ -  0x004abd90 02000000 70f90900 01000000 ffffffff ....p...........
│ │ +  0x004abd80 00000000 48920800 01000000 385f0900 ....H.......8_..
│ │ +  0x004abd90 02000000 97f90900 01000000 ffffffff ................
│ │    0x004abda0 ffffffff ffffffff 00000000 00000000 ................
│ │ -  0x004abdb0 00000000 a4860900 04000000 f4343000 .............40.
│ │ +  0x004abdb0 00000000 cb860900 04000000 f4343000 .............40.
│ │    0x004abdc0 01000000 ffffffff ffffffff ffffffff ................
│ │ -  0x004abdd0 00000000 00000000 00000000 22250a00 ............"%..
│ │ +  0x004abdd0 00000000 00000000 00000000 49250a00 ............I%..
│ │    0x004abde0 02000000 ec353000 01000000 ffffffff .....50.........
│ │    0x004abdf0 ffffffff ffffffff 00000000 00000000 ................
│ │ -  0x004abe00 00000000 a25b0900 00000000 a4363000 .....[.......60.
│ │ +  0x004abe00 00000000 c95b0900 00000000 a4363000 .....[.......60.
│ │    0x004abe10 01000000 ffffffff ffffffff ffffffff ................
│ │ -  0x004abe20 00000000 00000000 00000000 8b270a00 .............'..
│ │ +  0x004abe20 00000000 00000000 00000000 b2270a00 .............'..
│ │    0x004abe30 02000000 5c383000 01000000 ffffffff ....\80.........
│ │    0x004abe40 ffffffff ffffffff 00000000 00000000 ................
│ │ -  0x004abe50 00000000 4a3f0a00 02000000 5c383000 ....J?......\80.
│ │ +  0x004abe50 00000000 713f0a00 02000000 5c383000 ....q?......\80.
│ │    0x004abe60 01000000 ffffffff ffffffff ffffffff ................
│ │    0x004abe70 00000000 00000000 00000000 04430900 .............C..
│ │    0x004abe80 02000000 c8393000 01000000 ffffffff .....90.........
│ │    0x004abe90 ffffffff ffffffff 00000000 00000000 ................
│ │ -  0x004abea0 00000000 d8de0900 02000000 8c3a3000 .............:0.
│ │ +  0x004abea0 00000000 ffde0900 02000000 8c3a3000 .............:0.
│ │    0x004abeb0 01000000 ffffffff ffffffff ffffffff ................
│ │    0x004abec0 00000000 00000000 00000000 658f0800 ............e...
│ │    0x004abed0 02000000 143b3000 01000000 ffffffff .....;0.........
│ │    0x004abee0 ffffffff ffffffff 00000000 00000000 ................
│ │    0x004abef0 00000000 35320900 02000000 9c3b3000 ....52.......;0.
│ │    0x004abf00 01000000 ffffffff ffffffff ffffffff ................
│ │    0x004abf10 00000000 00000000 00000000 2e030900 ................
│ │    0x004abf20 02000000 143c3000 01000000 ffffffff .....<0.........
│ │    0x004abf30 ffffffff ffffffff 00000000 00000000 ................
│ │ -  0x004abf40 00000000 36cd0900 02000000 8c3c3000 ....6........<0.
│ │ +  0x004abf40 00000000 5dcd0900 02000000 8c3c3000 ....]........<0.
│ │    0x004abf50 01000000 ffffffff ffffffff ffffffff ................
│ │    0x004abf60 00000000 00000000 00000000 13480900 .............H..
│ │    0x004abf70 02000000 043d3000 01000000 ffffffff .....=0.........
│ │    0x004abf80 ffffffff ffffffff 00000000 00000000 ................
│ │ -  0x004abf90 00000000 7cf90900 02000000 7c3d3000 ....|.......|=0.
│ │ +  0x004abf90 00000000 a3f90900 02000000 7c3d3000 ............|=0.
│ │    0x004abfa0 01000000 ffffffff ffffffff ffffffff ................
│ │ -  0x004abfb0 00000000 00000000 00000000 8e270a00 .............'..
│ │ +  0x004abfb0 00000000 00000000 00000000 b5270a00 .............'..
│ │    0x004abfc0 02000000 f43d3000 01000000 ffffffff .....=0.........
│ │    0x004abfd0 ffffffff ffffffff 00000000 00000000 ................
│ │ -  0x004abfe0 00000000 38cd0900 02000000 a83e3000 ....8........>0.
│ │ +  0x004abfe0 00000000 5fcd0900 02000000 a83e3000 ...._........>0.
│ │    0x004abff0 01000000 ffffffff ffffffff ffffffff ................
│ │    0x004ac000 00000000 00000000 00000000 834a0800 .............J..
│ │    0x004ac010 02000000 5c3f3000 01000000 ffffffff ....\?0.........
│ │    0x004ac020 ffffffff ffffffff 00000000 00000000 ................
│ │    0x004ac030 00000000 96c10800 02000000 10403000 .............@0.
│ │    0x004ac040 01000000 ffffffff ffffffff ffffffff ................
│ │    0x004ac050 00000000 00000000 00000000 5b920800 ............[...
│ │    0x004ac060 02000000 c4403000 01000000 ffffffff .....@0.........
│ │    0x004ac070 ffffffff ffffffff 00000000 00000000 ................
│ │ -  0x004ac080 00000000 20560a00 02000000 78413000 .... V......xA0.
│ │ +  0x004ac080 00000000 47560a00 02000000 78413000 ....GV......xA0.
│ │    0x004ac090 01000000 ffffffff ffffffff ffffffff ................
│ │    0x004ac0a0 00000000 00000000 00000000 f5880700 ................
│ │    0x004ac0b0 02000000 2c423000 01000000 ffffffff ....,B0.........
│ │    0x004ac0c0 ffffffff ffffffff 00000000 00000000 ................
│ │    0x004ac0d0 00000000 30030900 02000000 e0423000 ....0........B0.
│ │    0x004ac0e0 01000000 ffffffff ffffffff ffffffff ................
│ │ -  0x004ac0f0 00000000 00000000 00000000 03b50900 ................
│ │ +  0x004ac0f0 00000000 00000000 00000000 2ab50900 ............*...
│ │    0x004ac100 02000000 94433000 01000000 ffffffff .....C0.........
│ │    0x004ac110 ffffffff ffffffff 00000000 00000000 ................
│ │    0x004ac120 00000000 92a10700 02000000 0c443000 .............D0.
│ │    0x004ac130 01000000 ffffffff ffffffff ffffffff ................
│ │    0x004ac140 00000000 00000000 00000000 2bd50800 ............+...
│ │    0x004ac150 02000000 84443000 01000000 ffffffff .....D0.........
│ │    0x004ac160 ffffffff ffffffff 00000000 00000000 ................
│ │    0x004ac170 00000000 01890700 02000000 3c453000 ............<E0.
│ │    0x004ac180 01000000 ffffffff ffffffff ffffffff ................
│ │    0x004ac190 00000000 00000000 00000000 0f890700 ................
│ │    0x004ac1a0 02000000 f4453000 01000000 ffffffff .....E0.........
│ │    0x004ac1b0 ffffffff ffffffff 00000000 00000000 ................
│ │ -  0x004ac1c0 00000000 11b50900 02000000 ac463000 .............F0.
│ │ +  0x004ac1c0 00000000 38b50900 02000000 ac463000 ....8........F0.
│ │    0x004ac1d0 01000000 ffffffff ffffffff ffffffff ................
│ │    0x004ac1e0 00000000 00000000 00000000 65aa0800 ............e...
│ │    0x004ac1f0 02000000 64473000 01000000 ffffffff ....dG0.........
│ │    0x004ac200 ffffffff ffffffff 00000000 00000000 ................
│ │    0x004ac210 00000000 a2c10800 02000000 1c483000 .............H0.
│ │    0x004ac220 01000000 ffffffff ffffffff ffffffff ................
│ │    0x004ac230 00000000 00000000 00000000 39d50800 ............9...
│ │    0x004ac240 02000000 d4483000 01000000 ffffffff .....H0.........
│ │    0x004ac250 ffffffff ffffffff 00000000 00000000 ................
│ │    0x004ac260 00000000 ff320800 02000000 8c493000 .....2.......I0.
│ │    0x004ac270 01000000 ffffffff ffffffff ffffffff ................
│ │    0x004ac280 00000000 00000000 00000000 67920800 ............g...
│ │    0x004ac290 02000000 444a3000 01000000 ffffffff ....DJ0.........
│ │    0x004ac2a0 ffffffff ffffffff 00000000 00000000 ................
│ │ -  0x004ac2b0 00000000 4d3f0a00 02000000 bc4a3000 ....M?.......J0.
│ │ +  0x004ac2b0 00000000 743f0a00 02000000 bc4a3000 ....t?.......J0.
│ │    0x004ac2c0 01000000 ffffffff ffffffff ffffffff ................
│ │    0x004ac2d0 00000000 00000000 00000000 a27a0800 .............z..
│ │    0x004ac2e0 02000000 744b3000 01000000 ffffffff ....tK0.........
│ │    0x004ac2f0 ffffffff ffffffff 00000000 00000000 ................
│ │    0x004ac300 00000000 a3190900 02000000 2c4c3000 ............,L0.
│ │    0x004ac310 01000000 ffffffff ffffffff ffffffff ................
│ │    0x004ac320 00000000 00000000 00000000 be040800 ................
│ │    0x004ac330 02000000 e44c3000 01000000 ffffffff .....L0.........
│ │    0x004ac340 ffffffff ffffffff 00000000 00000000 ................
│ │ -  0x004ac350 00000000 ae880900 02000000 9c4d3000 .............M0.
│ │ +  0x004ac350 00000000 d5880900 02000000 9c4d3000 .............M0.
│ │    0x004ac360 01000000 ffffffff ffffffff ffffffff ................
│ │    0x004ac370 00000000 00000000 00000000 8f4a0800 .............J..
│ │    0x004ac380 02000000 544e3000 01000000 ffffffff ....TN0.........
│ │    0x004ac390 ffffffff ffffffff 00000000 00000000 ................
│ │    0x004ac3a0 00000000 56ed0700 02000000 0c4f3000 ....V........O0.
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│ │    0x004ac3c0 00000000 00000000 00000000 1d1b0800 ................
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│ │    0x004b0610 57a70e00 00000000 d3650800 d3650800 W........e...e..
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│ │ -  0x004b1060 75ab0e00 00000000 a8770900 a8770900 u........w...w..
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│ │ +  0x004b1120 afab0e00 00000000 3b8c0900 3b8c0900 ........;...;...
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│ │    0x004b1160 12010000 08000000 c7ab0e00 00000000 ................
│ │ -  0x004b1170 5d4b0900 5d4b0900 13010000 08000000 ]K..]K..........
│ │ -  0x004b1180 cfab0e00 00000000 dc2a0a00 dc2a0a00 .........*...*..
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│ │ +  0x004b1180 cfab0e00 00000000 032b0a00 032b0a00 .........+...+..
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│ │    0x004b11b0 dfab0e00 00000000 9b060900 9b060900 ................
│ │    0x004b11c0 16010000 08000000 e7ab0e00 00000000 ................
│ │    0x004b11d0 1ef10700 1ef10700 17010000 08000000 ................
│ │ -  0x004b11e0 efab0e00 00000000 8eb80900 8eb80900 ................
│ │ +  0x004b11e0 efab0e00 00000000 b5b80900 b5b80900 ................
│ │    0x004b11f0 18010000 08000000 f7ab0e00 00000000 ................
│ │    0x004b1200 01360900 01360900 19010000 08000000 .6...6..........
│ │    0x004b1210 ffab0e00 00000000 bbd80800 bbd80800 ................
│ │    0x004b1220 1a010000 08000000 07ac0e00 00000000 ................
│ │    0x004b1230 dfef0800 dfef0800 1b010000 08000000 ................
│ │ -  0x004b1240 0fac0e00 00000000 d5610900 d5610900 .........a...a..
│ │ +  0x004b1240 0fac0e00 00000000 fc610900 fc610900 .........a...a..
│ │    0x004b1250 1c010000 08000000 17ac0e00 00000000 ................
│ │    0x004b1260 584d0800 b4060900 1d010000 08000000 XM..............
│ │ -  0x004b1270 1fac0e00 00000000 e4610900 e4610900 .........a...a..
│ │ +  0x004b1270 1fac0e00 00000000 0b620900 0b620900 .........b...b..
│ │    0x004b1280 1e010000 08000000 27ac0e00 00000000 ........'.......
│ │    0x004b1290 8d080800 7e590a00 1f010000 08000000 ....~Y..........
│ │ -  0x004b12a0 2fac0e00 00000000 298c0900 298c0900 /.......)...)...
│ │ +  0x004b12a0 2fac0e00 00000000 508c0900 508c0900 /.......P...P...
│ │    0x004b12b0 20010000 08000000 37ac0e00 00000000  .......7.......
│ │    0x004b12c0 caae0800 caae0800 21010000 08000000 ........!.......
│ │ -  0x004b12d0 3fac0e00 00000000 38e60900 38e60900 ?.......8...8...
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│ │ +  0x004b1ed0 deaf0e00 00000000 cdc80900 40370800 ............@7..
│ │    0x004b1ee0 a2010000 09000000 e7af0e00 00000000 ................
│ │ -  0x004b1ef0 5da40700 828c0900 a3010000 09000000 ]...............
│ │ +  0x004b1ef0 5da40700 a98c0900 a3010000 09000000 ]...............
│ │    0x004b1f00 f0af0e00 00000000 2b070900 d6590a00 ........+....Y..
│ │    0x004b1f10 a4010000 09000000 f9af0e00 00000000 ................
│ │ -  0x004b1f20 d48c0700 0ab90900 a5010000 09000000 ................
│ │ -  0x004b1f30 02b00e00 00000000 8e8c0900 4c370800 ............L7..
│ │ +  0x004b1f20 d48c0700 31b90900 a5010000 09000000 ....1...........
│ │ +  0x004b1f30 02b00e00 00000000 b58c0900 4c370800 ............L7..
│ │    0x004b1f40 a6010000 09000000 0bb00e00 00000000 ................
│ │    0x004b1f50 ac340900 e08c0700 a7010000 09000000 .4..............
│ │ -  0x004b1f60 14b00e00 00000000 ecae0800 9a8c0900 ................
│ │ +  0x004b1f60 14b00e00 00000000 ecae0800 c18c0900 ................
│ │    0x004b1f70 a8010000 09000000 1db00e00 00000000 ................
│ │ -  0x004b1f80 7da60700 99fd0900 a9010000 09000000 }...............
│ │ -  0x004b1f90 26b00e00 00000000 ab840900 f8ae0800 &...............
│ │ +  0x004b1f80 7da60700 c0fd0900 a9010000 09000000 }...............
│ │ +  0x004b1f90 26b00e00 00000000 d2840900 f8ae0800 &...............
│ │    0x004b1fa0 aa010000 09000000 2fb00e00 00000000 ......../.......
│ │ -  0x004b1fb0 6b830900 ec8c0700 ab010000 09000000 k...............
│ │ +  0x004b1fb0 92830900 ec8c0700 ab010000 09000000 ................
│ │    0x004b1fc0 38b00e00 00000000 fa1d0900 fc960800 8...............
│ │    0x004b1fd0 ac010000 09000000 41b00e00 00000000 ........A.......
│ │    0x004b1fe0 58370800 64360900 ad010000 09000000 X7..d6..........
│ │ -  0x004b1ff0 4ab00e00 00000000 96150a00 35a20900 J...........5...
│ │ +  0x004b1ff0 4ab00e00 00000000 bd150a00 5ca20900 J...........\...
│ │    0x004b2000 ae010000 03000000 53b00e00 00000000 ........S.......
│ │ -  0x004b2010 acf10700 4ba20900 af010000 07000000 ....K...........
│ │ +  0x004b2010 acf10700 72a20900 af010000 07000000 ....r...........
│ │    0x004b2020 56b00e00 00000000 e6080800 01f00800 V...............
│ │    0x004b2030 b0010000 07000000 5db00e00 00000000 ........].......
│ │ -  0x004b2040 1f620900 16b90900 b1010000 07000000 .b..............
│ │ -  0x004b2050 64b00e00 00000000 88830900 88830900 d...............
│ │ +  0x004b2040 46620900 3db90900 b1010000 07000000 Fb..=...........
│ │ +  0x004b2050 64b00e00 00000000 af830900 af830900 d...............
│ │    0x004b2060 b2010000 01000000 6bb00e00 00000000 ........k.......
│ │ -  0x004b2070 463f0a00 463f0a00 b3010000 03000000 F?..F?..........
│ │ +  0x004b2070 6d3f0a00 6d3f0a00 b3010000 03000000 m?..m?..........
│ │    0x004b2080 6cb00e00 00000000 c0f10700 c0f10700 l...............
│ │    0x004b2090 b4010000 07000000 6fb00e00 00000000 ........o.......
│ │    0x004b20a0 f1660800 f1660800 b5010000 08000000 .f...f..........
│ │    0x004b20b0 76b00e00 00000000 50be0700 50be0700 v.......P...P...
│ │    0x004b20c0 b6010000 09000000 7eb00e00 00000000 ........~.......
│ │ -  0x004b20d0 11440a00 11440a00 b7010000 09000000 .D...D..........
│ │ -  0x004b20e0 87b00e00 00000000 cde60900 cde60900 ................
│ │ +  0x004b20d0 38440a00 38440a00 b7010000 09000000 8D..8D..........
│ │ +  0x004b20e0 87b00e00 00000000 f4e60900 f4e60900 ................
│ │    0x004b20f0 b8010000 09000000 90b00e00 00000000 ................
│ │ -  0x004b2100 022b0a00 022b0a00 b9010000 09000000 .+...+..........
│ │ +  0x004b2100 292b0a00 292b0a00 b9010000 09000000 )+..)+..........
│ │    0x004b2110 99b00e00 00000000 f7660800 f7660800 .........f...f..
│ │    0x004b2120 ba010000 0a000000 a2b00e00 00000000 ................
│ │ -  0x004b2130 26780900 26780900 bb010000 0a000000 &x..&x..........
│ │ -  0x004b2140 acb00e00 00000000 0e2b0a00 0e2b0a00 .........+...+..
│ │ +  0x004b2130 4d780900 4d780900 bb010000 0a000000 Mx..Mx..........
│ │ +  0x004b2140 acb00e00 00000000 352b0a00 352b0a00 ........5+..5+..
│ │    0x004b2150 bc010000 0a000000 b6b00e00 00000000 ................
│ │    0x004b2160 e2590a00 e2590a00 bd010000 0a000000 .Y...Y..........
│ │ -  0x004b2170 c0b00e00 00000000 a5fd0900 a5fd0900 ................
│ │ +  0x004b2170 c0b00e00 00000000 ccfd0900 ccfd0900 ................
│ │    0x004b2180 be010000 0a000000 cab00e00 00000000 ................
│ │    0x004b2190 b51f0800 b51f0800 bf010000 0a000000 ................
│ │    0x004b21a0 d4b00e00 00000000 04af0800 04af0800 ................
│ │    0x004b21b0 c0010000 0a000000 deb00e00 00000000 ................
│ │    0x004b21c0 844d0800 844d0800 c1010000 0a000000 .M...M..........
│ │    0x004b21d0 e8b00e00 00000000 061e0900 061e0900 ................
│ │    0x004b21e0 c2010000 0a000000 f2b00e00 00000000 ................
│ │    0x004b21f0 1ef00800 1ef00800 c3010000 0a000000 ................
│ │ -  0x004b2200 fcb00e00 00000000 35620900 35620900 ........5b..5b..
│ │ +  0x004b2200 fcb00e00 00000000 5c620900 5c620900 ........\b..\b..
│ │    0x004b2210 c4010000 0a000000 06b10e00 00000000 ................
│ │    0x004b2220 00090800 00090800 c5010000 0a000000 ................
│ │ -  0x004b2230 10b10e00 00000000 dee60900 dee60900 ................
│ │ +  0x004b2230 10b10e00 00000000 05e70900 05e70900 ................
│ │    0x004b2240 c6010000 0a000000 1ab10e00 00000000 ................
│ │    0x004b2250 fdd80800 fdd80800 c7010000 0a000000 ................
│ │    0x004b2260 24b10e00 00000000 28f00800 28f00800 $.......(...(...
│ │    0x004b2270 c8010000 0a000000 2eb10e00 00000000 ................
│ │    0x004b2280 37070900 37070900 c9010000 0a000000 7...7...........
│ │    0x004b2290 38b10e00 00000000 63be0700 07670800 8.......c....g..
│ │    0x004b22a0 ca010000 0a000000 42b10e00 00000000 ........B.......
│ │    0x004b22b0 70360900 70360900 cb010000 0a000000 p6..p6..........
│ │ -  0x004b22c0 4cb10e00 00000000 f3e60900 89a60700 L...............
│ │ +  0x004b22c0 4cb10e00 00000000 1ae70900 89a60700 L...............
│ │    0x004b22d0 cc010000 0a000000 56b10e00 00000000 ........V.......
│ │    0x004b22e0 fb1a0800 fb1a0800 cd010000 0a000000 ................
│ │    0x004b22f0 60b10e00 00000000 67be0700 67be0700 `.......g...g...
│ │    0x004b2300 ce010000 0a000000 6ab10e00 00000000 ........j.......
│ │ -  0x004b2310 2eb90900 2eb90900 cf010000 0a000000 ................
│ │ +  0x004b2310 55b90900 55b90900 cf010000 0a000000 U...U...........
│ │    0x004b2320 74b10e00 00000000 0e670800 0e670800 t........g...g..
│ │    0x004b2330 d0010000 0a000000 7eb10e00 00000000 ........~.......
│ │    0x004b2340 934d0800 934d0800 d1010000 0a000000 .M...M..........
│ │    0x004b2350 88b10e00 00000000 161e0900 161e0900 ................
│ │    0x004b2360 d2010000 0a000000 92b10e00 00000000 ................
│ │ -  0x004b2370 39b90900 39b90900 d3010000 0a000000 9...9...........
│ │ +  0x004b2370 60b90900 60b90900 d3010000 0a000000 `...`...........
│ │    0x004b2380 9cb10e00 00000000 10090800 10090800 ................
│ │    0x004b2390 d4010000 0a000000 a6b10e00 00000000 ................
│ │ -  0x004b23a0 2ed00900 2ed00900 d5010000 0a000000 ................
│ │ -  0x004b23b0 b0b10e00 00000000 f8e60900 f8e60900 ................
│ │ +  0x004b23a0 55d00900 55d00900 d5010000 0a000000 U...U...........
│ │ +  0x004b23b0 b0b10e00 00000000 1fe70900 1fe70900 ................
│ │    0x004b23c0 d6010000 0a000000 bab10e00 00000000 ................
│ │ -  0x004b23d0 61a20900 61a20900 d7010000 0a000000 a...a...........
│ │ +  0x004b23d0 88a20900 88a20900 d7010000 0a000000 ................
│ │    0x004b23e0 c4b10e00 00000000 97a60700 97a60700 ................
│ │    0x004b23f0 d8010000 0a000000 ceb10e00 00000000 ................
│ │    0x004b2400 f88c0700 f88c0700 d9010000 0a000000 ................
│ │ -  0x004b2410 d8b10e00 00000000 3cd00900 3cd00900 ........<...<...
│ │ +  0x004b2410 d8b10e00 00000000 63d00900 63d00900 ........c...c...
│ │    0x004b2420 da010000 0a000000 e2b10e00 00000000 ................
│ │    0x004b2430 0c8d0700 0c8d0700 db010000 0a000000 ................
│ │ -  0x004b2440 ecb10e00 00000000 08e70900 08e70900 ................
│ │ +  0x004b2440 ecb10e00 00000000 2fe70900 2fe70900 ......../.../...
│ │    0x004b2450 dc010000 0a000000 f6b10e00 00000000 ................
│ │    0x004b2460 76be0700 76be0700 dd010000 0a000000 v...v...........
│ │    0x004b2470 00b20e00 00000000 927e0800 927e0800 .........~...~..
│ │    0x004b2480 de010000 0a000000 0ab20e00 00000000 ................
│ │    0x004b2490 198d0700 198d0700 df010000 0a000000 ................
│ │ -  0x004b24a0 14b20e00 00000000 aa150a00 aa150a00 ................
│ │ +  0x004b24a0 14b20e00 00000000 d1150a00 d1150a00 ................
│ │    0x004b24b0 e0010000 0a000000 1eb20e00 00000000 ................
│ │    0x004b24c0 31f00800 31f00800 e1010000 0a000000 1...1...........
│ │    0x004b24d0 28b20e00 00000000 9d4d0800 9d4d0800 (........M...M..
│ │    0x004b24e0 e2010000 0a000000 32b20e00 00000000 ........2.......
│ │    0x004b24f0 0bc50800 0bc50800 e3010000 0a000000 ................
│ │ -  0x004b2500 3cb20e00 00000000 40780900 40780900 <.......@x..@x..
│ │ +  0x004b2500 3cb20e00 00000000 67780900 67780900 <.......gx..gx..
│ │    0x004b2510 e4010000 0a000000 46b20e00 00000000 ........F.......
│ │    0x004b2520 4b070900 4b070900 e5010000 0a000000 K...K...........
│ │    0x004b2530 50b20e00 00000000 ee590a00 ee590a00 P........Y...Y..
│ │    0x004b2540 e6010000 0a000000 5ab20e00 00000000 ........Z.......
│ │    0x004b2550 09af0800 09af0800 e7010000 0a000000 ................
│ │    0x004b2560 64b20e00 00000000 005a0a00 005a0a00 d........Z...Z..
│ │    0x004b2570 e8010000 0a000000 6eb20e00 00000000 ........n.......
│ │ -  0x004b2580 a14b0900 a14b0900 e9010000 0a000000 .K...K..........
│ │ +  0x004b2580 c84b0900 c84b0900 e9010000 0a000000 .K...K..........
│ │    0x004b2590 78b20e00 00000000 3af00800 3af00800 x.......:...:...
│ │    0x004b25a0 ea010000 0a000000 82b20e00 00000000 ................
│ │    0x004b25b0 c4f10700 c4f10700 eb010000 0a000000 ................
│ │ -  0x004b25c0 8cb20e00 00000000 1a2b0a00 1a2b0a00 .........+...+..
│ │ +  0x004b25c0 8cb20e00 00000000 412b0a00 412b0a00 ........A+..A+..
│ │    0x004b25d0 ec010000 0a000000 96b20e00 00000000 ................
│ │    0x004b25e0 d9f10700 d9f10700 ed010000 0a000000 ................
│ │    0x004b25f0 a0b20e00 00000000 9a7e0800 9a7e0800 .........~...~..
│ │    0x004b2600 ee010000 0a000000 aab20e00 00000000 ................
│ │    0x004b2610 14670800 14670800 ef010000 0a000000 .g...g..........
│ │    0x004b2620 b4b20e00 00000000 a74d0800 a74d0800 .........M...M..
│ │    0x004b2630 f0010000 0a000000 beb20e00 00000000 ................
│ │ -  0x004b2640 adfd0900 adfd0900 f1010000 0a000000 ................
│ │ -  0x004b2650 c8b20e00 00000000 70a20900 70a20900 ........p...p...
│ │ +  0x004b2640 d4fd0900 d4fd0900 f1010000 0a000000 ................
│ │ +  0x004b2650 c8b20e00 00000000 97a20900 97a20900 ................
│ │    0x004b2660 f2010000 0a000000 d2b20e00 00000000 ................
│ │    0x004b2670 be1f0800 be1f0800 f3010000 0a000000 ................
│ │    0x004b2680 dcb20e00 00000000 4ef00800 4ef00800 ........N...N...
│ │    0x004b2690 f4010000 0a000000 e6b20e00 00000000 ................
│ │    0x004b26a0 64370800 64370800 f5010000 0a000000 d7..d7..........
│ │    0x004b26b0 f0b20e00 00000000 1f670800 1f670800 .........g...g..
│ │    0x004b26c0 f6010000 0a000000 fab20e00 00000000 ................
│ │    0x004b26d0 6a370800 6a370800 f7010000 03000000 j7..j7..........
│ │ -  0x004b26e0 04b30e00 00000000 1b1e0900 b64b0900 .............K..
│ │ +  0x004b26e0 04b30e00 00000000 1b1e0900 dd4b0900 .............K..
│ │    0x004b26f0 f8010000 05000000 07b30e00 00000000 ................
│ │    0x004b2700 0fd90800 0fd90800 f9010000 06000000 ................
│ │    0x004b2710 0cb30e00 00000000 a8a60700 a8a60700 ................
│ │    0x004b2720 fa010000 06000000 12b30e00 00000000 ................
│ │    0x004b2730 85be0700 85be0700 fb010000 07000000 ................
│ │ -  0x004b2740 18b30e00 00000000 49620900 49620900 ........Ib..Ib..
│ │ +  0x004b2740 18b30e00 00000000 70620900 70620900 ........pb..pb..
│ │    0x004b2750 fc010000 07000000 1fb30e00 00000000 ................
│ │ -  0x004b2760 26440a00 26440a00 fd010000 03000000 &D..&D..........
│ │ -  0x004b2770 26b30e00 00000000 a68c0900 a68c0900 &...............
│ │ +  0x004b2760 4d440a00 4d440a00 fd010000 03000000 MD..MD..........
│ │ +  0x004b2770 26b30e00 00000000 cd8c0900 cd8c0900 &...............
│ │    0x004b2780 fe010000 03000000 29b30e00 00000000 ........).......
│ │    0x004b2790 00000000 00000000 00000000 00000000 ................
│ │ -  0x004b27a0 00000000 00000000 17c50800 b08c0900 ................
│ │ +  0x004b27a0 00000000 00000000 17c50800 d78c0900 ................
│ │    0x004b27b0 00020000 02000000 2cb30e00 00000000 ........,.......
│ │ -  0x004b27c0 b3150a00 41b90900 01020000 03000000 ....A...........
│ │ +  0x004b27c0 da150a00 68b90900 01020000 03000000 ....h...........
│ │    0x004b27d0 2eb30e00 00000000 eef10700 ba4d0800 .............M..
│ │    0x004b27e0 02020000 03000000 31b30e00 00000000 ........1.......
│ │ -  0x004b27f0 62620900 62620900 03020000 03000000 bb..bb..........
│ │ -  0x004b2800 34b30e00 00000000 86a20900 86a20900 4...............
│ │ +  0x004b27f0 89620900 89620900 03020000 03000000 .b...b..........
│ │ +  0x004b2800 34b30e00 00000000 ada20900 ada20900 4...............
│ │    0x004b2810 04020000 03000000 37b30e00 00000000 ........7.......
│ │    0x004b2820 1ec50800 2ac50800 05020000 03000000 ....*...........
│ │    0x004b2830 3ab30e00 00000000 b8a60700 b8a60700 :...............
│ │    0x004b2840 06020000 03000000 3db30e00 00000000 ........=.......
│ │    0x004b2850 85360900 85360900 07020000 04000000 .6...6..........
│ │    0x004b2860 40b30e00 00000000 31670800 31670800 @.......1g..1g..
│ │    0x004b2870 08020000 04000000 44b30e00 00000000 ........D.......
│ │    0x004b2880 f9f10700 f9f10700 09020000 04000000 ................
│ │    0x004b2890 48b30e00 00000000 07f20700 07f20700 H...............
│ │    0x004b28a0 0a020000 04000000 4cb30e00 00000000 ........L.......
│ │ -  0x004b28b0 91a20900 91a20900 0b020000 04000000 ................
│ │ +  0x004b28b0 b8a20900 b8a20900 0b020000 04000000 ................
│ │    0x004b28c0 50b30e00 00000000 d01f0800 d01f0800 P...............
│ │    0x004b28d0 0c020000 04000000 54b30e00 00000000 ........T.......
│ │ -  0x004b28e0 4fb90900 4fb90900 0d020000 04000000 O...O...........
│ │ -  0x004b28f0 58b30e00 00000000 272b0a00 272b0a00 X.......'+..'+..
│ │ +  0x004b28e0 76b90900 76b90900 0d020000 04000000 v...v...........
│ │ +  0x004b28f0 58b30e00 00000000 4e2b0a00 4e2b0a00 X.......N+..N+..
│ │    0x004b2900 0e020000 04000000 5cb30e00 00000000 ........\.......
│ │    0x004b2910 14f20700 14f20700 0f020000 04000000 ................
│ │ -  0x004b2920 60b30e00 00000000 6b620900 6b620900 `.......kb..kb..
│ │ +  0x004b2920 60b30e00 00000000 92620900 92620900 `........b...b..
│ │    0x004b2930 10020000 04000000 64b30e00 00000000 ........d.......
│ │ -  0x004b2940 3a440a00 3a440a00 11020000 04000000 :D..:D..........
│ │ +  0x004b2940 61440a00 61440a00 11020000 04000000 aD..aD..........
│ │    0x004b2950 68b30e00 00000000 dd1f0800 dd1f0800 h...............
│ │    0x004b2960 12020000 04000000 6cb30e00 00000000 ........l.......
│ │ -  0x004b2970 46d00900 46d00900 13020000 04000000 F...F...........
│ │ +  0x004b2970 6dd00900 6dd00900 13020000 04000000 m...m...........
│ │    0x004b2980 70b30e00 00000000 a77e0800 a77e0800 p........~...~..
│ │    0x004b2990 14020000 04000000 74b30e00 00000000 ........t.......
│ │ -  0x004b29a0 362b0a00 362b0a00 15020000 04000000 6+..6+..........
│ │ +  0x004b29a0 5d2b0a00 5d2b0a00 15020000 04000000 ]+..]+..........
│ │    0x004b29b0 78b30e00 00000000 29f20700 29f20700 x.......)...)...
│ │    0x004b29c0 16020000 04000000 7cb30e00 00000000 ........|.......
│ │    0x004b29d0 08970800 08970800 17020000 04000000 ................
│ │    0x004b29e0 80b30e00 00000000 93360900 93360900 .........6...6..
│ │    0x004b29f0 18020000 04000000 84b30e00 00000000 ................
│ │ -  0x004b2a00 9aa20900 9aa20900 19020000 04000000 ................
│ │ +  0x004b2a00 c1a20900 c1a20900 19020000 04000000 ................
│ │    0x004b2a10 88b30e00 00000000 5a070900 5a070900 ........Z...Z...
│ │    0x004b2a20 1a020000 04000000 8cb30e00 00000000 ................
│ │    0x004b2a30 0bd90700 0bd90700 1b020000 04000000 ................
│ │    0x004b2a40 90b30e00 00000000 cd4d0800 cd4d0800 .........M...M..
│ │    0x004b2a50 1c020000 04000000 94b30e00 00000000 ................
│ │    0x004b2a60 6d070900 6d070900 1d020000 04000000 m...m...........
│ │    0x004b2a70 98b30e00 00000000 b47e0800 b47e0800 .........~...~..
│ │ @@ -6419,1096 +6419,1096 @@
│ │    0x004b2b10 24020000 04000000 b4b30e00 00000000 $...............
│ │    0x004b2b20 5af00800 5af00800 25020000 04000000 Z...Z...%.......
│ │    0x004b2b30 b8b30e00 00000000 19970800 19970800 ................
│ │    0x004b2b40 26020000 04000000 bcb30e00 00000000 &...............
│ │    0x004b2b50 c97e0800 c97e0800 27020000 04000000 .~...~..'.......
│ │    0x004b2b60 c0b30e00 00000000 2e8d0700 2e8d0700 ................
│ │    0x004b2b70 28020000 04000000 c4b30e00 00000000 (...............
│ │ -  0x004b2b80 64b90900 64b90900 29020000 04000000 d...d...).......
│ │ +  0x004b2b80 8bb90900 8bb90900 29020000 04000000 ........).......
│ │    0x004b2b90 c8b30e00 00000000 1dd90700 1dd90700 ................
│ │    0x004b2ba0 2a020000 04000000 ccb30e00 00000000 *...............
│ │ -  0x004b2bb0 bd150a00 bd150a00 2b020000 04000000 ........+.......
│ │ +  0x004b2bb0 e4150a00 e4150a00 2b020000 04000000 ........+.......
│ │    0x004b2bc0 d0b30e00 00000000 241e0900 241e0900 ........$...$...
│ │    0x004b2bd0 2c020000 04000000 d4b30e00 00000000 ,...............
│ │    0x004b2be0 81070900 81070900 2d020000 04000000 ........-.......
│ │ -  0x004b2bf0 d8b30e00 00000000 59d00900 59d00900 ........Y...Y...
│ │ +  0x004b2bf0 d8b30e00 00000000 80d00900 80d00900 ................
│ │    0x004b2c00 2e020000 04000000 dcb30e00 00000000 ................
│ │    0x004b2c10 db7e0800 db7e0800 2f020000 04000000 .~...~../.......
│ │ -  0x004b2c20 e0b30e00 00000000 51780900 51780900 ........Qx..Qx..
│ │ +  0x004b2c20 e0b30e00 00000000 78780900 78780900 ........xx..xx..
│ │    0x004b2c30 30020000 04000000 e4b30e00 00000000 0...............
│ │    0x004b2c40 27af0800 27af0800 31020000 04000000 '...'...1.......
│ │    0x004b2c50 e8b30e00 00000000 93070900 93070900 ................
│ │    0x004b2c60 32020000 04000000 ecb30e00 00000000 2...............
│ │ -  0x004b2c70 ada20900 ada20900 33020000 04000000 ........3.......
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│ │    0x004b2cc0 36020000 04000000 fcb30e00 00000000 6...............
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│ │    0x004b2cf0 38020000 04000000 04b40e00 00000000 8...............
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│ │    0x004b34e0 628d0700 434e0800 8d020000 00000000 b...CN..........
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│ │    0x004b36f0 b2f20700 66670800 a3020000 09000000 ....fg..........
│ │ -  0x004b3700 d7b50e00 00000000 374c0900 374c0900 ........7L..7L..
│ │ +  0x004b3700 d7b50e00 00000000 5e4c0900 5e4c0900 ........^L..^L..
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│ │ -  0x004b3720 11fe0900 11fe0900 a5020000 03000000 ................
│ │ +  0x004b3720 38fe0900 38fe0900 a5020000 03000000 8...8...........
│ │    0x004b3730 e1b50e00 00000000 10a70700 10a70700 ................
│ │    0x004b3740 a6020000 02000000 e4b50e00 00000000 ................
│ │ -  0x004b3750 21630900 21630900 a7020000 03000000 !c..!c..........
│ │ +  0x004b3750 48630900 48630900 a7020000 03000000 Hc..Hc..........
│ │    0x004b3760 e6b50e00 00000000 73af0800 73af0800 ........s...s...
│ │    0x004b3770 a8020000 08000000 e9b50e00 00000000 ................
│ │    0x004b3780 7d8d0700 7d8d0700 a9020000 09000000 }...}...........
│ │    0x004b3790 f1b50e00 00000000 14a70700 14a70700 ................
│ │    0x004b37a0 aa020000 09000000 fab50e00 00000000 ................
│ │ -  0x004b37b0 bcd00900 bcd00900 ab020000 09000000 ................
│ │ +  0x004b37b0 e3d00900 e3d00900 ab020000 09000000 ................
│ │    0x004b37c0 03b60e00 00000000 2a620800 2a620800 ........*b..*b..
│ │    0x004b37d0 ac020000 08000000 0cb60e00 00000000 ................
│ │    0x004b37e0 d2eb0700 d2eb0700 ad020000 08000000 ................
│ │    0x004b37f0 14b60e00 00000000 35620800 35620800 ........5b..5b..
│ │    0x004b3800 ae020000 08000000 1cb60e00 00000000 ................
│ │ -  0x004b3810 859d0900 859d0900 af020000 08000000 ................
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│ │    0x004b3820 24b60e00 00000000 40620800 40620800 $.......@b..@b..
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│ │    0x004b3bb0 15b70e00 00000000 304a0800 304a0800 ........0J..0J..
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│ │    0x004b43d0 2c030000 06000000 19b90e00 00000000 ,...............
│ │ -  0x004b43e0 dabe0700 d0440a00 2d030000 06000000 .....D..-.......
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│ │    0x004b4480 3db90e00 00000000 497f0800 497f0800 =.......I...I...
│ │    0x004b4490 34030000 07000000 44b90e00 00000000 4.......D.......
│ │    0x004b44a0 7b970800 7b970800 35030000 07000000 {...{...5.......
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│ │ +  0x004b44b0 4bb90e00 00000000 31ba0900 31ba0900 K.......1...1...
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│ │    0x004b5070 ccd90700 ccd90700 b3030000 00000000 ................
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│ │    0x004b50a0 62b00800 fabe0700 b5030000 00000000 b...............
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│ │    0x004b51c0 4e1f0900 917f0800 c1030000 08000000 N...............
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│ │ -  0x004b5320 00000000 00000000 026d0900 026d0900 .........m...m..
│ │ +  0x004b5320 00000000 00000000 296d0900 296d0900 ........)m..)m..
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│ │ +  0x004b5340 65d10900 65d10900 d1030000 06000000 e...e...........
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│ │ +  0x004b5370 c7130800 ace80900 d3030000 08000000 ................
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│ │    0x004b53a0 36210800 36210800 d5030000 07000000 6!..6!..........
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│ │    0x004b53f0 d8030000 07000000 20bd0e00 00000000 ........ .......
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│ │    0x004b5430 74da0800 74da0800 db030000 07000000 t...t...........
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│ │ +  0x004b5460 70790900 80da0800 dd030000 08000000 py..............
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│ │ +  0x004b54c0 31a40900 31a40900 e1030000 08000000 1...1...........
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│ │    0x004b5500 72bd0e00 00000000 a6380800 a6380800 r........8...8..
│ │    0x004b5510 e4030000 08000000 79bd0e00 00000000 ........y.......
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│ │ +  0x004b5530 81bd0e00 00000000 50450a00 9dda0800 ........PE......
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│ │ -  0x004b5560 93bd0e00 00000000 75d10900 75d10900 ........u...u...
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│ │ +  0x004b5560 93bd0e00 00000000 9cd10900 9cd10900 ................
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│ │    0x004b5580 5f1f0900 5f1f0900 e9030000 07000000 _..._...........
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│ │    0x004b55e0 cb380800 cb380800 ed030000 05000000 .8...8..........
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│ │ -  0x004b5610 35ff0900 78210800 ef030000 05000000 5...x!..........
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│ │ -  0x004b56b0 00000000 00000000 4a630900 4a630900 ........Jc..Jc..
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│ │ -  0x004b5730 6f9b0900 59630900 fb030000 00000000 o...Yc..........
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│ │ +  0x004b57d0 f7bd0e00 00000000 118f0700 f7e80900 ................
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│ │    0x004b58e0 5e4f0800 588f0700 0d040000 00000000 ^O..X...........
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│ │ +  0x004b5b50 df8d0900 c3210800 27040000 00000000 .....!..'.......
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│ │    0x004b5b70 28040000 00000000 00000000 00000000 (...............
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│ │ +  0x004b5b80 e4380800 c0d10900 29040000 09000000 .8......).......
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│ │    0x004b5ba0 2a040000 09000000 81be0e00 00000000 *...............
│ │    0x004b5bb0 78c60800 85c60800 2b040000 09000000 x.......+.......
│ │ -  0x004b5bc0 8abe0e00 00000000 5f8f0700 962c0a00 ........_....,..
│ │ +  0x004b5bc0 8abe0e00 00000000 5f8f0700 bd2c0a00 ........_....,..
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│ │ +  0x004b5be0 49f10800 22e90900 2d040000 09000000 I..."...-.......
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│ │ -  0x004b5c10 18770900 69790900 2f040000 09000000 .w..iy../.......
│ │ -  0x004b5c20 aebe0e00 00000000 a6d10900 a32c0a00 .............,..
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│ │    0x004b5c90 34040000 09000000 dbbe0e00 00000000 4...............
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│ │ +  0x004b5ca0 29da0700 dad10900 35040000 09000000 ).......5.......
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│ │ -  0x004b5ce0 f6be0e00 00000000 1c800800 b02c0a00 .............,..
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│ │ +  0x004b5ce0 f6be0e00 00000000 1c800800 d72c0a00 .............,..
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│ │ +  0x004b5d00 f44d0900 3ce90900 39040000 00000000 .M..<...9.......
│ │    0x004b5d10 00000000 00000000 6c8f0700 7a8f0700 ........l...z...
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│ │    0x004b5d30 a0980800 f1380800 3b040000 00000000 .....8..;.......
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│ │    0x004b5d50 3c040000 00000000 00000000 00000000 <...............
│ │ -  0x004b5d60 62a40900 f5da0800 3d040000 00000000 b.......=.......
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│ │ @@ -7520,230 +7520,230 @@
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│ │ +  0x004b7170 4ad20900 488e0900 13050000 03000000 J...H...........
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│ │ +  0x004b74a0 00000000 14000000 2c640900 01000000 ........,d......
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│ │    0x004b7520 00000000 00000000 39a90700 e4972700 ........9.....'.
│ │    0x004b7530 00100000 00000000 08000000 9e390800 .............9..
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│ │ -  0x004b7570 00000000 00000000 15640900 70922700 .........d..p.'.
│ │ +  0x004b7570 00000000 00000000 3c640900 70922700 ........<d..p.'.
│ │    0x004b7580 00000000 00000000 04000000 84390900 .............9..
│ │    0x004b7590 34912700 00000000 00000000 00000000 4.'.............
│ │ -  0x004b75a0 c8450a00 ac912700 91000000 00000000 .E....'.........
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│ │ -  0x004b75c0 01000000 04000000 c8bb0900 d4b03800 ..............8.
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│ │ +  0x004b75c0 01000000 04000000 efbb0900 d4b03800 ..............8.
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│ │    0x004b75e0 34912700 00000000 00000000 00000000 4.'.............
│ │    0x004b75f0 e0810800 34922700 91000000 00000000 ....4.'.........
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│ │ -  0x004b7640 22640900 50922700 00000000 00000000 "d..P.'.........
│ │ +  0x004b7640 49640900 50922700 00000000 00000000 Id..P.'.........
│ │    0x004b7650 00000000 92220800 cc453300 00000000 ....."...E3.....
│ │ -  0x004b7660 00000000 04000000 27a50900 5c463300 ........'...\F3.
│ │ +  0x004b7660 00000000 04000000 4ea50900 5c463300 ........N...\F3.
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│ │    0x004b7680 34922700 91000000 00000000 0c000000 4.'.............
│ │    0x004b7690 5c500800 34922700 95000000 01000000 \P..4.'.........
│ │    0x004b76a0 10000000 45c70800 50b03800 91000000 ....E...P.8.....
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│ │    0x004b76d0 0c463300 00000000 00000000 0c000000 .F3.............
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│ │ +  0x004b76f0 10000000 57640900 6c463300 95000000 ....Wd..lF3.....
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│ │    0x004b7720 7c463300 00100000 00000000 18000000 |F3.............
│ │    0x004b7730 8d690800 e4972700 00000000 00000000 .i....'.........
│ │    0x004b7740 20000000 78090900 d0912700 95000000  ...x.....'.....
│ │    0x004b7750 00000000 24000000 33a90700 4cd43800 ....$...3...L.8.
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│ │    0x004bc1d0 00000000 a72d0800 e2f50800 38724c00 .....-......8rL.
│ │ -  0x004bc1e0 00000000 df740800 127d0900 90774c00 .....t...}...wL.
│ │ +  0x004bc1e0 00000000 df740800 397d0900 90774c00 .....t..9}...wL.
│ │    0x004bc1f0 00000000 df740800 260e0800 d8774c00 .....t..&....wL.
│ │ -  0x004bc200 00000000 df740800 0d320a00 20784c00 .....t...2.. xL.
│ │ +  0x004bc200 00000000 df740800 34320a00 20784c00 .....t..42.. xL.
│ │    0x004bc210 00000000 df740800 93250800 68784c00 .....t...%..hxL.
│ │ -  0x004bc220 00000000 df740800 54ed0900 b0784c00 .....t..T....xL.
│ │ +  0x004bc220 00000000 df740800 7bed0900 b0784c00 .....t..{....xL.
│ │    0x004bc230 00000000 df740800 e2f50800 f8784c00 .....t.......xL.
│ │ -  0x004bc240 00000000 a6390a00 127d0900 40794c00 .....9...}..@yL.
│ │ -  0x004bc250 00000000 a6390a00 260e0800 88794c00 .....9..&....yL.
│ │ -  0x004bc260 00000000 a6390a00 0d320a00 d0794c00 .....9...2...yL.
│ │ -  0x004bc270 00000000 a6390a00 93250800 187a4c00 .....9...%...zL.
│ │ -  0x004bc280 00000000 a6390a00 54ed0900 607a4c00 .....9..T...`zL.
│ │ -  0x004bc290 00000000 a6390a00 e2f50800 a87a4c00 .....9.......zL.
│ │ -  0x004bc2a0 00000000 f6d30800 127d0900 30744c00 .........}..0tL.
│ │ +  0x004bc240 00000000 cd390a00 397d0900 40794c00 .....9..9}..@yL.
│ │ +  0x004bc250 00000000 cd390a00 260e0800 88794c00 .....9..&....yL.
│ │ +  0x004bc260 00000000 cd390a00 34320a00 d0794c00 .....9..42...yL.
│ │ +  0x004bc270 00000000 cd390a00 93250800 187a4c00 .....9...%...zL.
│ │ +  0x004bc280 00000000 cd390a00 7bed0900 607a4c00 .....9..{...`zL.
│ │ +  0x004bc290 00000000 cd390a00 e2f50800 a87a4c00 .....9.......zL.
│ │ +  0x004bc2a0 00000000 f6d30800 397d0900 30744c00 ........9}..0tL.
│ │    0x004bc2b0 00000000 f6d30800 260e0800 78744c00 ........&...xtL.
│ │ -  0x004bc2c0 00000000 f6d30800 0d320a00 c0744c00 .........2...tL.
│ │ +  0x004bc2c0 00000000 f6d30800 34320a00 c0744c00 ........42...tL.
│ │    0x004bc2d0 00000000 f6d30800 93250800 08754c00 .........%...uL.
│ │ -  0x004bc2e0 00000000 f6d30800 54ed0900 50754c00 ........T...PuL.
│ │ +  0x004bc2e0 00000000 f6d30800 7bed0900 50754c00 ........{...PuL.
│ │    0x004bc2f0 00000000 f6d30800 e2f50800 98754c00 .............uL.
│ │ -  0x004bc300 00000000 6c900800 127d0900 e0754c00 ....l....}...uL.
│ │ +  0x004bc300 00000000 6c900800 397d0900 e0754c00 ....l...9}...uL.
│ │    0x004bc310 00000000 6c900800 260e0800 28764c00 ....l...&...(vL.
│ │ -  0x004bc320 00000000 6c900800 0d320a00 70764c00 ....l....2..pvL.
│ │ +  0x004bc320 00000000 6c900800 34320a00 70764c00 ....l...42..pvL.
│ │    0x004bc330 00000000 6c900800 93250800 b8764c00 ....l....%...vL.
│ │ -  0x004bc340 00000000 6c900800 54ed0900 00774c00 ....l...T....wL.
│ │ +  0x004bc340 00000000 6c900800 7bed0900 00774c00 ....l...{....wL.
│ │    0x004bc350 00000000 6c900800 e2f50800 48774c00 ....l.......HwL.
│ │ -  0x004bc360 00000000 c3310800 48320a00 80724c00 .....1..H2...rL.
│ │ +  0x004bc360 00000000 c3310800 6f320a00 80724c00 .....1..o2...rL.
│ │    0x004bc370 00000000 c3310800 ce250800 c8724c00 .....1...%...rL.
│ │    0x004bc380 00000000 c3310800 7c3d0900 10734c00 .....1..|=...sL.
│ │    0x004bc390 00000000 c3310800 23f60800 58734c00 .....1..#...XsL.
│ │ -  0x004bc3a0 00000000 c3310800 dc910900 a0734c00 .....1.......sL.
│ │ +  0x004bc3a0 00000000 c3310800 03920900 a0734c00 .....1.......sL.
│ │    0x004bc3b0 00000000 c3310800 5df60800 e8734c00 .....1..]....sL.
│ │    0x004bc3c0 00000000 25120900 bf850800 f07a4c00 ....%........zL.
│ │    0x004bc3d0 00000000 25120900 679d0800 387b4c00 ....%...g...8{L.
│ │    0x004bc3e0 00000000 5ecb0700 bbca0800 807b4c00 ....^........{L.
│ │    0x004bc3f0 00000000 5ecb0700 979d0800 c87b4c00 ....^........{L.
│ │ -  0x004bc400 00000000 35920800 1bd60900 107c4c00 ....5........|L.
│ │ -  0x004bc410 00000000 35920800 b6030a00 587c4c00 ....5.......X|L.
│ │ -  0x004bc420 00000000 6f800700 231c0a00 a07c4c00 ....o...#....|L.
│ │ +  0x004bc400 00000000 35920800 42d60900 107c4c00 ....5...B....|L.
│ │ +  0x004bc410 00000000 35920800 dd030a00 587c4c00 ....5.......X|L.
│ │ +  0x004bc420 00000000 6f800700 4a1c0a00 a07c4c00 ....o...J....|L.
│ │    0x004bc430 00000000 6f800700 6a0e0800 e87c4c00 ....o...j....|L.
│ │ -  0x004bc440 00000000 a72d0800 567d0900 307d4c00 .....-..V}..0}L.
│ │ +  0x004bc440 00000000 a72d0800 7d7d0900 307d4c00 .....-..}}..0}L.
│ │    0x004bc450 00000000 a72d0800 923d0800 787d4c00 .....-...=..x}L.
│ │ -  0x004bc460 00000000 25120900 531c0a00 c07d4c00 ....%...S....}L.
│ │ +  0x004bc460 00000000 25120900 7a1c0a00 c07d4c00 ....%...z....}L.
│ │    0x004bc470 00000000 25120900 4cb50800 087e4c00 ....%...L....~L.
│ │ -  0x004bc480 00000000 64d00800 531c0a00 507e4c00 ....d...S...P~L.
│ │ +  0x004bc480 00000000 64d00800 7a1c0a00 507e4c00 ....d...z...P~L.
│ │    0x004bc490 00000000 64d00800 4cb50800 987e4c00 ....d...L....~L.
│ │    0x004bc4a0 00000000 5ecb0700 66df0800 e07e4c00 ....^...f....~L.
│ │ -  0x004bc4b0 00000000 5ecb0700 95ed0900 287f4c00 ....^.......(.L.
│ │ -  0x004bc4c0 00000000 35920800 4bd60900 707f4c00 ....5...K...p.L.
│ │ +  0x004bc4b0 00000000 5ecb0700 bced0900 287f4c00 ....^.......(.L.
│ │ +  0x004bc4c0 00000000 35920800 72d60900 707f4c00 ....5...r...p.L.
│ │    0x004bc4d0 00000000 35920800 8fac0700 b87f4c00 ....5.........L.
│ │    0x004bc4e0 00000000 a72d0800 eaca0800 00804c00 .....-........L.
│ │ -  0x004bc4f0 00000000 a72d0800 1c920900 48804c00 .....-......H.L.
│ │ +  0x004bc4f0 00000000 a72d0800 43920900 48804c00 .....-..C...H.L.
│ │    0x004bc500 00000000 00000000 00000000 00000000 ................
│ │ -  0x004bc510 00000000 5ecb0700 27490a00 94524c00 ....^...'I...RL.
│ │ +  0x004bc510 00000000 5ecb0700 4e490a00 94524c00 ....^...NI...RL.
│ │    0x004bc520 00000000 5ecb0700 a0230900 d4524c00 ....^....#...RL.
│ │    0x004bc530 00000000 5ecb0700 6f550800 14534c00 ....^...oU...SL.
│ │    0x004bc540 00000000 5ecb0700 efde0700 54534c00 ....^.......TSL.
│ │ -  0x004bc550 00000000 35920800 27490a00 94534c00 ....5...'I...SL.
│ │ +  0x004bc550 00000000 35920800 4e490a00 94534c00 ....5...NI...SL.
│ │    0x004bc560 00000000 35920800 a0230900 d4534c00 ....5....#...SL.
│ │    0x004bc570 00000000 35920800 6f550800 14544c00 ....5...oU...TL.
│ │ -  0x004bc580 00000000 35920800 4e920900 54544c00 ....5...N...TTL.
│ │ -  0x004bc590 00000000 6f800700 27490a00 94544c00 ....o...'I...TL.
│ │ +  0x004bc580 00000000 35920800 75920900 54544c00 ....5...u...TTL.
│ │ +  0x004bc590 00000000 6f800700 4e490a00 94544c00 ....o...NI...TL.
│ │    0x004bc5a0 00000000 6f800700 a0230900 d4544c00 ....o....#...TL.
│ │    0x004bc5b0 00000000 6f800700 6f550800 14554c00 ....o...oU...UL.
│ │ -  0x004bc5c0 00000000 6f800700 29680900 54554c00 ....o...)h..TUL.
│ │ +  0x004bc5c0 00000000 6f800700 50680900 54554c00 ....o...Ph..TUL.
│ │    0x004bc5d0 00000000 6f800700 a8550800 08624c00 ....o....U...bL.
│ │ -  0x004bc5e0 00000000 6f800700 dea80900 d0634c00 ....o........cL.
│ │ -  0x004bc5f0 00000000 a72d0800 27490a00 94554c00 .....-..'I...UL.
│ │ +  0x004bc5e0 00000000 6f800700 05a90900 d0634c00 ....o........cL.
│ │ +  0x004bc5f0 00000000 a72d0800 4e490a00 94554c00 .....-..NI...UL.
│ │    0x004bc600 00000000 a72d0800 a0230900 d4554c00 .....-...#...UL.
│ │    0x004bc610 00000000 a72d0800 6f550800 14564c00 .....-..oU...VL.
│ │    0x004bc620 00000000 a72d0800 c1ac0700 54564c00 .....-......TVL.
│ │ -  0x004bc630 00000000 f6d30800 27490a00 94574c00 ........'I...WL.
│ │ +  0x004bc630 00000000 f6d30800 4e490a00 94574c00 ........NI...WL.
│ │    0x004bc640 00000000 f6d30800 a0230900 d4574c00 .........#...WL.
│ │ -  0x004bc650 00000000 6c900800 27490a00 14584c00 ....l...'I...XL.
│ │ +  0x004bc650 00000000 6c900800 4e490a00 14584c00 ....l...NI...XL.
│ │    0x004bc660 00000000 6c900800 a0230900 54584c00 ....l....#..TXL.
│ │ -  0x004bc670 00000000 df740800 27490a00 94564c00 .....t..'I...VL.
│ │ +  0x004bc670 00000000 df740800 4e490a00 94564c00 .....t..NI...VL.
│ │    0x004bc680 00000000 df740800 a0230900 d4564c00 .....t...#...VL.
│ │ -  0x004bc690 00000000 a6390a00 27490a00 14574c00 .....9..'I...WL.
│ │ -  0x004bc6a0 00000000 a6390a00 a0230900 54574c00 .....9...#..TWL.
│ │ -  0x004bc6b0 00000000 c3310800 851c0a00 94584c00 .....1.......XL.
│ │ +  0x004bc690 00000000 cd390a00 4e490a00 14574c00 .....9..NI...WL.
│ │ +  0x004bc6a0 00000000 cd390a00 a0230900 54574c00 .....9...#..TWL.
│ │ +  0x004bc6b0 00000000 c3310800 ac1c0a00 94584c00 .....1.......XL.
│ │    0x004bc6c0 00000000 c3310800 a6f70700 d4584c00 .....1.......XL.
│ │ -  0x004bc6d0 00000000 c3310800 7d920900 14594c00 .....1..}....YL.
│ │ -  0x004bc6e0 00000000 25120900 27490a00 54594c00 ....%...'I..TYL.
│ │ +  0x004bc6d0 00000000 c3310800 a4920900 14594c00 .....1.......YL.
│ │ +  0x004bc6e0 00000000 25120900 4e490a00 54594c00 ....%...NI..TYL.
│ │    0x004bc6f0 00000000 25120900 a0230900 94594c00 ....%....#...YL.
│ │    0x004bc700 00000000 25120900 6f550800 d4594c00 ....%...oU...YL.
│ │ -  0x004bc710 00000000 25120900 f5510900 145a4c00 ....%....Q...ZL.
│ │ -  0x004bc720 00000000 64d00800 27490a00 545a4c00 ....d...'I..TZL.
│ │ +  0x004bc710 00000000 25120900 1c520900 145a4c00 ....%....R...ZL.
│ │ +  0x004bc720 00000000 64d00800 4e490a00 545a4c00 ....d...NI..TZL.
│ │    0x004bc730 00000000 64d00800 a0230900 945a4c00 ....d....#...ZL.
│ │    0x004bc740 00000000 25120900 a8550800 38624c00 ....%....U..8bL.
│ │ -  0x004bc750 00000000 25120900 dea80900 10644c00 ....%........dL.
│ │ +  0x004bc750 00000000 25120900 05a90900 10644c00 ....%........dL.
│ │    0x004bc760 00000000 e2760800 a0230900 a8644c00 .....v...#...dL.
│ │ -  0x004bc770 00000000 e2760800 24520900 a0624c00 .....v..$R...bL.
│ │ -  0x004bc780 00000000 e2760800 16c00900 b0614c00 .....v.......aL.
│ │ +  0x004bc770 00000000 e2760800 4b520900 a0624c00 .....v..KR...bL.
│ │ +  0x004bc780 00000000 e2760800 3dc00900 b0614c00 .....v..=....aL.
│ │    0x004bc790 00000000 00000000 00000000 00000000 ................
│ │ -  0x004bc7a0 00000000 f5460a00 e5f70700 3cf64c00 .....F......<.L.
│ │ +  0x004bc7a0 00000000 1c470a00 e5f70700 3cf64c00 .....G......<.L.
│ │    0x004bc7b0 00000000 00000000 00000000 00000000 ................
│ │    0x004bc7c0 00000000 4cf50700 11260800 6cd44c00 ....L....&..l.L.
│ │    0x004bc7d0 00000000 00000000 00000000 00000000 ................
│ │    0x004bc7e0 00000000 00040000 ccf53800 01040000 ..........8.....
│ │    0x004bc7f0 ecf53800 02040000 fcf53800 03040000 ..8.......8.....
│ │    0x004bc800 ecf63800 06040000 60fe3800 00000000 ..8.....`.8.....
│ │    0x004bc810 00000000 72430800 e0230900 cc3c4c00 ....rC...#...<L.
│ │    0x004bc820 00000000 00000000 4bdf0700 e0230900 ........K....#..
│ │ -  0x004bc830 0c114c00 00000000 00000000 5f1d0a00 ..L........._...
│ │ +  0x004bc830 0c114c00 00000000 00000000 861d0a00 ..L.............
│ │    0x004bc840 e0230900 84114c00 00000000 00000000 .#....L.........
│ │ -  0x004bc850 78680900 e0230900 fc114c00 00000000 xh...#....L.....
│ │ -  0x004bc860 00000000 9da90900 e0230900 74124c00 .........#..t.L.
│ │ +  0x004bc850 9f680900 e0230900 fc114c00 00000000 .h...#....L.....
│ │ +  0x004bc860 00000000 c4a90900 e0230900 74124c00 .........#..t.L.
│ │    0x004bc870 00000000 00000000 516e0800 e0230900 ........Qn...#..
│ │    0x004bc880 ec124c00 00000000 00000000 c99e0800 ..L.............
│ │    0x004bc890 e0230900 64134c00 00000000 00000000 .#..d.L.........
│ │    0x004bc8a0 f39e0800 e0230900 d41b4c00 00000000 .....#....L.....
│ │    0x004bc8b0 00000000 4a950700 e0230900 5c1b4c00 ....J....#..\.L.
│ │    0x004bc8c0 00000000 00000000 70e00800 e0230900 ........p....#..
│ │ -  0x004bc8d0 e41a4c00 00000000 00000000 bed70900 ..L.............
│ │ +  0x004bc8d0 e41a4c00 00000000 00000000 e5d70900 ..L.............
│ │    0x004bc8e0 e0230900 dc134c00 00000000 00000000 .#....L.........
│ │ -  0x004bc8f0 5d050a00 e0230900 54144c00 00000000 ]....#..T.L.....
│ │ +  0x004bc8f0 84050a00 e0230900 54144c00 00000000 .....#..T.L.....
│ │    0x004bc900 00000000 6fdf0700 e0230900 cc144c00 ....o....#....L.
│ │    0x004bc910 00000000 00000000 e2b50800 e0230900 .............#..
│ │    0x004bc920 44154c00 00000000 00000000 06b60800 D.L.............
│ │    0x004bc930 e0230900 bc154c00 00000000 00000000 .#....L.........
│ │    0x004bc940 cbcb0800 e0230900 34164c00 00000000 .....#..4.L.....
│ │    0x004bc950 00000000 64090800 e0230900 ac164c00 ....d....#....L.
│ │ -  0x004bc960 00000000 00000000 78780900 e0230900 ........xx...#..
│ │ +  0x004bc960 00000000 00000000 9f780900 e0230900 .........x...#..
│ │    0x004bc970 24174c00 00000000 00000000 dba60700 $.L.............
│ │    0x004bc980 e0230900 9c174c00 00000000 00000000 .#....L.........
│ │    0x004bc990 9cbe0700 e0230900 14184c00 00000000 .....#....L.....
│ │ -  0x004bc9a0 00000000 b9b90900 e0230900 8c184c00 .........#....L.
│ │ +  0x004bc9a0 00000000 e0b90900 e0230900 8c184c00 .........#....L.
│ │    0x004bc9b0 00000000 00000000 628d0700 e0230900 ........b....#..
│ │ -  0x004bc9c0 04194c00 00000000 00000000 5cba0900 ..L.........\...
│ │ +  0x004bc9c0 04194c00 00000000 00000000 83ba0900 ..L.............
│ │    0x004bc9d0 e0230900 7c194c00 00000000 00000000 .#..|.L.........
│ │    0x004bc9e0 468e0700 e0230900 f4194c00 00000000 F....#....L.....
│ │ -  0x004bc9f0 00000000 50ba0900 e0230900 6c1a4c00 ....P....#..l.L.
│ │ +  0x004bc9f0 00000000 77ba0900 e0230900 6c1a4c00 ....w....#..l.L.
│ │    0x004bca00 00000000 00000000 02570800 e0230900 .........W...#..
│ │ -  0x004bca10 582c4c00 00000000 00000000 51330a00 X,L.........Q3..
│ │ +  0x004bca10 582c4c00 00000000 00000000 78330a00 X,L.........x3..
│ │    0x004bca20 e0230900 d02c4c00 00000000 00000000 .#...,L.........
│ │ -  0x004bca30 c0fe0900 e0230900 a8224c00 00000000 .....#..."L.....
│ │ +  0x004bca30 e7fe0900 e0230900 a8224c00 00000000 .....#..."L.....
│ │    0x004bca40 00000000 efa70700 e0230900 20234c00 .........#.. #L.
│ │    0x004bca50 00000000 00000000 2af30700 e0230900 ........*....#..
│ │    0x004bca60 98234c00 00000000 00000000 d4a80700 .#L.............
│ │    0x004bca70 e0230900 f8244c00 00000000 00000000 .#...$L.........
│ │    0x004bca80 51b10800 e0230900 70254c00 00000000 Q....#..p%L.....
│ │ -  0x004bca90 00000000 c4630900 e0230900 e8254c00 .....c...#...%L.
│ │ +  0x004bca90 00000000 eb630900 e0230900 e8254c00 .....c...#...%L.
│ │    0x004bcaa0 00000000 00000000 d2f60800 e0230900 .............#..
│ │ -  0x004bcab0 3c204c00 00000000 00000000 e2d70900 < L.............
│ │ +  0x004bcab0 3c204c00 00000000 00000000 09d80900 < L.............
│ │    0x004bcac0 e0230900 b4204c00 00000000 00000000 .#... L.........
│ │ -  0x004bcad0 d9ee0900 e0230900 2c214c00 00000000 .....#..,!L.....
│ │ -  0x004bcae0 00000000 c8a90900 e0230900 ac1f4c00 .........#....L.
│ │ +  0x004bcad0 00ef0900 e0230900 2c214c00 00000000 .....#..,!L.....
│ │ +  0x004bcae0 00000000 efa90900 e0230900 ac1f4c00 .........#....L.
│ │    0x004bcaf0 00000000 00000000 48870800 e0230900 ........H....#..
│ │ -  0x004bcb00 341f4c00 00000000 00000000 faa90900 4.L.............
│ │ +  0x004bcb00 341f4c00 00000000 00000000 21aa0900 4.L.........!...
│ │    0x004bcb10 e0230900 bc1e4c00 00000000 00000000 .#....L.........
│ │ -  0x004bcb20 f2d70900 e0230900 2c1e4c00 00000000 .....#..,.L.....
│ │ +  0x004bcb20 19d80900 e0230900 2c1e4c00 00000000 .....#..,.L.....
│ │    0x004bcb30 00000000 2ab60800 e0230900 b41d4c00 ....*....#....L.
│ │    0x004bcb40 00000000 00000000 910e0900 e0230900 .............#..
│ │ -  0x004bcb50 3c1d4c00 00000000 00000000 b9930900 <.L.............
│ │ +  0x004bcb50 3c1d4c00 00000000 00000000 e0930900 <.L.............
│ │    0x004bcb60 e0230900 18274c00 00000000 00000000 .#...'L.........
│ │    0x004bcb70 e2f60800 e0230900 88274c00 00000000 .....#...'L.....
│ │    0x004bcb80 00000000 92df0700 e0230900 f8274c00 .........#...'L.
│ │ -  0x004bcb90 00000000 00000000 24d80900 e0230900 ........$....#..
│ │ -  0x004bcba0 68284c00 00000000 00000000 f9930900 h(L.............
│ │ +  0x004bcb90 00000000 00000000 4bd80900 e0230900 ........K....#..
│ │ +  0x004bcba0 68284c00 00000000 00000000 20940900 h(L......... ...
│ │    0x004bcbb0 e0230900 d8284c00 00000000 00000000 .#...(L.........
│ │    0x004bcbc0 80e00800 e0230900 48294c00 00000000 .....#..H)L.....
│ │    0x004bcbd0 00000000 5fc70700 e0230900 b8294c00 ...._....#...)L.
│ │ -  0x004bcbe0 00000000 00000000 81050a00 e0230900 .............#..
│ │ -  0x004bcbf0 282a4c00 00000000 00000000 5a530900 (*L.........ZS..
│ │ +  0x004bcbe0 00000000 00000000 a8050a00 e0230900 .............#..
│ │ +  0x004bcbf0 282a4c00 00000000 00000000 81530900 (*L..........S..
│ │    0x004bcc00 e0230900 982a4c00 00000000 00000000 .#...*L.........
│ │    0x004bcc10 7c6e0800 e0230900 082b4c00 00000000 |n...#...+L.....
│ │    0x004bcc20 00000000 a56e0800 e0230900 782b4c00 .....n...#..x+L.
│ │    0x004bcc30 00000000 00000000 23570800 e0230900 ........#W...#..
│ │ -  0x004bcc40 e82b4c00 00000000 00000000 3d4d0900 .+L.........=M..
│ │ +  0x004bcc40 e82b4c00 00000000 00000000 644d0900 .+L.........dM..
│ │    0x004bcc50 e0230900 803f0f00 00000000 d0463900 .#...?.......F9.
│ │    0x004bcc60 34680800 e0230900 883f0f00 00000000 4h...#...?......
│ │ -  0x004bcc70 d0463900 4d2c0a00 e0230900 903f0f00 .F9.M,...#...?..
│ │ +  0x004bcc70 d0463900 742c0a00 e0230900 903f0f00 .F9.t,...#...?..
│ │    0x004bcc80 00000000 d8463900 caa70700 e0230900 .....F9......#..
│ │    0x004bcc90 983f0f00 00000000 d8463900 22f70800 .?.......F9."...
│ │    0x004bcca0 e0230900 c4394c00 00000000 00000000 .#...9L.........
│ │ -  0x004bccb0 9b680900 e0230900 4c394c00 00000000 .h...#..L9L.....
│ │ +  0x004bccb0 c2680900 e0230900 4c394c00 00000000 .h...#..L9L.....
│ │    0x004bccc0 00000000 eecb0800 e0230900 d4384c00 .........#...8L.
│ │ -  0x004bccd0 00000000 00000000 257e0900 e0230900 ........%~...#..
│ │ +  0x004bccd0 00000000 00000000 4c7e0900 e0230900 ........L~...#..
│ │    0x004bcce0 44384c00 00000000 00000000 c03e0800 D8L..........>..
│ │    0x004bccf0 e0230900 cc374c00 00000000 00000000 .#...7L.........
│ │ -  0x004bcd00 72330a00 e0230900 54374c00 00000000 r3...#..T7L.....
│ │ +  0x004bcd00 99330a00 e0230900 54374c00 00000000 .3...#..T7L.....
│ │    0x004bcd10 00000000 4bf90700 e0230900 7c2d4c00 ....K....#..|-L.
│ │    0x004bcd20 00000000 00000000 1d240900 e0230900 .........$...#..
│ │    0x004bcd30 f42d4c00 00000000 00000000 6ef90700 .-L.........n...
│ │    0x004bcd40 e0230900 6c2e4c00 00000000 00000000 .#..l.L.........
│ │    0x004bcd50 d1df0700 e0230900 e42e4c00 00000000 .....#....L.....
│ │ -  0x004bcd60 00000000 95330a00 e0230900 5c2f4c00 .....3...#..\/L.
│ │ -  0x004bcd70 00000000 00000000 45940900 e0230900 ........E....#..
│ │ -  0x004bcd80 d42f4c00 00000000 00000000 964a0a00 ./L..........J..
│ │ +  0x004bcd60 00000000 bc330a00 e0230900 5c2f4c00 .....3...#..\/L.
│ │ +  0x004bcd70 00000000 00000000 6c940900 e0230900 ........l....#..
│ │ +  0x004bcd80 d42f4c00 00000000 00000000 bd4a0a00 ./L..........J..
│ │    0x004bcd90 e0230900 4c304c00 00000000 00000000 .#..L0L.........
│ │    0x004bcda0 4c570800 e0230900 c4304c00 00000000 LW...#...0L.....
│ │ -  0x004bcdb0 00000000 7b530900 e0230900 3c314c00 ....{S...#..<1L.
│ │ +  0x004bcdb0 00000000 a2530900 e0230900 3c314c00 .....S...#..<1L.
│ │    0x004bcdc0 00000000 00000000 3f240900 e0230900 ........?$...#..
│ │    0x004bcdd0 b4314c00 00000000 00000000 5f270800 .1L........._'..
│ │    0x004bcde0 e0230900 2c324c00 00000000 00000000 .#..,2L.........
│ │    0x004bcdf0 ce6e0800 e0230900 a4324c00 00000000 .n...#...2L.....
│ │    0x004bce00 00000000 6c8f0700 e0230900 1c334c00 ....l....#...3L.
│ │ -  0x004bce10 00000000 00000000 cd4d0900 e0230900 .........M...#..
│ │ +  0x004bce10 00000000 00000000 f44d0900 e0230900 .........M...#..
│ │    0x004bce20 94334c00 00000000 00000000 1c800800 .3L.............
│ │    0x004bce30 e0230900 0c344c00 00000000 00000000 .#...4L.........
│ │ -  0x004bce40 62a40900 e0230900 84344c00 00000000 b....#...4L.....
│ │ +  0x004bce40 89a40900 e0230900 84344c00 00000000 .....#...4L.....
│ │    0x004bce50 00000000 725b0a00 e0230900 fc344c00 ....r[...#...4L.
│ │    0x004bce60 00000000 00000000 a0980800 e0230900 .............#..
│ │ -  0x004bce70 74354c00 00000000 00000000 42c20900 t5L.........B...
│ │ +  0x004bce70 74354c00 00000000 00000000 69c20900 t5L.........i...
│ │    0x004bce80 e0230900 ec354c00 00000000 00000000 .#...5L.........
│ │    0x004bce90 c00f0800 e0230900 64364c00 00000000 .....#..d6L.....
│ │ -  0x004bcea0 00000000 9d530900 e0230900 dc364c00 .....S...#...6L.
│ │ -  0x004bceb0 00000000 00000000 2baa0900 e0230900 ........+....#..
│ │ -  0x004bcec0 1c424c00 00000000 00000000 bf530900 .BL..........S..
│ │ +  0x004bcea0 00000000 c4530900 e0230900 dc364c00 .....S...#...6L.
│ │ +  0x004bceb0 00000000 00000000 52aa0900 e0230900 ........R....#..
│ │ +  0x004bcec0 1c424c00 00000000 00000000 e6530900 .BL..........S..
│ │    0x004bced0 e0230900 94424c00 00000000 00000000 .#...BL.........
│ │    0x004bcee0 0a080800 e0230900 10444c00 00000000 .....#...DL.....
│ │    0x004bcef0 00000000 22ef0800 e0230900 88444c00 ...."....#...DL.
│ │    0x004bcf00 00000000 00000000 65af0800 e0230900 ........e....#..
│ │    0x004bcf10 78454c00 00000000 00000000 5bd90700 xEL.........[...
│ │    0x004bcf20 e0230900 00454c00 00000000 00000000 .#...EL.........
│ │ -  0x004bcf30 487e0900 e0230900 48484c00 00000000 H~...#..HHL.....
│ │ +  0x004bcf30 6f7e0900 e0230900 48484c00 00000000 o~...#..HHL.....
│ │    0x004bcf40 00000000 a7610a00 e0230900 f0454c00 .....a...#...EL.
│ │ -  0x004bcf50 00000000 00000000 07430a00 e0230900 .........C...#..
│ │ +  0x004bcf50 00000000 00000000 2e430a00 e0230900 .........C...#..
│ │    0x004bcf60 68464c00 00000000 00000000 89c40800 hFL.............
│ │    0x004bcf70 e0230900 e0464c00 00000000 00000000 .#...FL.........
│ │    0x004bcf80 7aa50700 e0230900 58474c00 00000000 z....#..XGL.....
│ │    0x004bcf90 00000000 72ad0700 e0230900 a4404c00 ....r....#...@L.
│ │    0x004bcfa0 00000000 00000000 e30f0800 e0230900 .............#..
│ │ -  0x004bcfb0 14404c00 00000000 00000000 bf330a00 .@L..........3..
│ │ +  0x004bcfb0 14404c00 00000000 00000000 e6330a00 .@L..........3..
│ │    0x004bcfc0 e0230900 bc3d4c00 00000000 00000000 .#...=L.........
│ │    0x004bcfd0 c9610a00 e0230900 343e4c00 00000000 .a...#..4>L.....
│ │    0x004bcfe0 00000000 5a950700 e0230900 ac3e4c00 ....Z....#...>L.
│ │    0x004bcff0 00000000 00000000 6e570800 e0230900 ........nW...#..
│ │    0x004bd000 243f4c00 00000000 00000000 c20e0900 $?L.............
│ │    0x004bd010 e0230900 9c3f4c00 00000000 00000000 .#...?L.........
│ │    0x004bd020 78950700 e0230900 70414c00 00000000 x....#..pAL.....
│ │ -  0x004bd030 00000000 6f9b0900 e0230900 a83a4c00 ....o....#...:L.
│ │ -  0x004bd040 00000000 00000000 b86e0900 e0230900 .........n...#..
│ │ +  0x004bd030 00000000 969b0900 e0230900 a83a4c00 .........#...:L.
│ │ +  0x004bd040 00000000 00000000 df6e0900 e0230900 .........n...#..
│ │    0x004bd050 a83b4c00 00000000 00000000 00000000 .;L.............
│ │    0x004bd060 00000000 00000000 00000000 00000000 ................
│ │    0x004bd070 a18c0800 06000000 00000000 00000000 ................
│ │    0x004bd080 ffffffff ea8a0800 06000000 00000000 ................
│ │    0x004bd090 00000000 ffffffff 89250800 06000000 .........%......
│ │    0x004bd0a0 00000000 00000000 ffffffff a1940700 ................
│ │    0x004bd0b0 01000000 00000000 00000000 ffffffff ................
│ │    0x004bd0c0 00000000 00000000 00000000 00000000 ................
│ │ -  0x004bd0d0 00000000 59c00900 e0230900 3c4b4c00 ....Y....#..<KL.
│ │ +  0x004bd0d0 00000000 80c00900 e0230900 3c4b4c00 .........#..<KL.
│ │    0x004bd0e0 00000000 b63d0900 e0230900 944b4c00 .....=...#...KL.
│ │    0x004bd0f0 00000000 c69d0800 e0230900 dc4b4c00 .........#...KL.
│ │    0x004bd100 00000000 3fc60700 e0230900 244c4c00 ....?....#..$LL.
│ │ -  0x004bd110 00000000 8b320a00 e0230900 6c4c4c00 .....2...#..lLL.
│ │ -  0x004bd120 00000000 e6030a00 e0230900 b44c4c00 .........#...LL.
│ │ +  0x004bd110 00000000 b2320a00 e0230900 6c4c4c00 .....2...#..lLL.
│ │ +  0x004bd120 00000000 0d040a00 e0230900 b44c4c00 .........#...LL.
│ │    0x004bd130 00000000 efac0700 e0230900 fc4c4c00 .........#...LL.
│ │    0x004bd140 00000000 1ccb0800 e0230900 444d4c00 .........#..DML.
│ │ -  0x004bd150 00000000 15040a00 e0230900 b44d4c00 .........#...ML.
│ │ -  0x004bd160 00000000 58680900 e0230900 fc4d4c00 ....Xh...#...ML.
│ │ -  0x004bd170 00000000 61490a00 e0230900 444e4c00 ....aI...#..DNL.
│ │ +  0x004bd150 00000000 3c040a00 e0230900 b44d4c00 ....<....#...ML.
│ │ +  0x004bd160 00000000 7f680900 e0230900 fc4d4c00 .....h...#...ML.
│ │ +  0x004bd170 00000000 88490a00 e0230900 444e4c00 .....I...#..DNL.
│ │    0x004bd180 00000000 a8940700 e0230900 8c4e4c00 .........#...NL.
│ │ -  0x004bd190 00000000 35040a00 e0230900 d44e4c00 ....5....#...NL.
│ │ -  0x004bd1a0 00000000 7dd60900 e0230900 1c4f4c00 ....}....#...OL.
│ │ +  0x004bd190 00000000 5c040a00 e0230900 d44e4c00 ....\....#...NL.
│ │ +  0x004bd1a0 00000000 a4d60900 e0230900 1c4f4c00 .........#...OL.
│ │    0x004bd1b0 00000000 f59d0800 e0230900 644f4c00 .........#..dOL.
│ │    0x004bd1c0 00000000 260d0900 e0230900 ac4f4c00 ....&....#...OL.
│ │ -  0x004bd1d0 00000000 88d60900 e0230900 d4504c00 .........#...PL.
│ │ +  0x004bd1d0 00000000 afd60900 e0230900 d4504c00 .........#...PL.
│ │    0x004bd1e0 00000000 310d0900 e0230900 44514c00 ....1....#..DQL.
│ │    0x004bd1f0 00000000 7eb50800 e0230900 f44f4c00 ....~....#...OL.
│ │ -  0x004bd200 00000000 ffa80900 e0230900 64504c00 .........#..dPL.
│ │ +  0x004bd200 00000000 26a90900 e0230900 64504c00 ....&....#..dPL.
│ │    0x004bd210 00000000 9a0e0800 e0230900 ec484c00 .........#...HL.
│ │ -  0x004bd220 00000000 7cc00900 e0230900 7c494c00 ....|....#..|IL.
│ │ +  0x004bd220 00000000 a3c00900 e0230900 7c494c00 .........#..|IL.
│ │    0x004bd230 00000000 9df60800 e0230900 4c524c00 .........#..LRL.
│ │ -  0x004bd240 00000000 b5920900 e0230900 e4494c00 .........#...IL.
│ │ +  0x004bd240 00000000 dc920900 e0230900 e4494c00 .........#...IL.
│ │    0x004bd250 00000000 20960800 e0230900 2c4a4c00 .... ....#..,JL.
│ │ -  0x004bd260 00000000 aec00900 e0230900 f44a4c00 .........#...JL.
│ │ +  0x004bd260 00000000 d5c00900 e0230900 f44a4c00 .........#...JL.
│ │    0x004bd270 00000000 72430800 e0230900 ac4a4c00 ....rC...#...JL.
│ │    0x004bd280 00000000 00000000 00000000 00000000 ................
│ │    0x004bd290 00000000 e53d0900 e0230900 a8c54c00 .....=...#....L.
│ │    0x004bd2a0 00000000 98df0800 e0230900 a0c64c00 .........#....L.
│ │ -  0x004bd2b0 00000000 45630900 e0230900 98c74c00 ....Ec...#....L.
│ │ -  0x004bd2c0 00000000 a7d60900 e0230900 7cc84c00 .........#..|.L.
│ │ +  0x004bd2b0 00000000 6c630900 e0230900 98c74c00 ....lc...#....L.
│ │ +  0x004bd2c0 00000000 ced60900 e0230900 7cc84c00 .........#..|.L.
│ │    0x004bd2d0 00000000 aa2d0800 e0230900 60c94c00 .....-...#..`.L.
│ │    0x004bd2e0 00000000 1f260800 e0230900 80ca4c00 .....&...#....L.
│ │    0x004bd2f0 00000000 63c60700 e0230900 d8ca4c00 ....c....#....L.
│ │    0x004bd300 00000000 f1230900 e0230900 c8cc4c00 .....#...#....L.
│ │    0x004bd310 00000000 009e0800 e0230900 20cc4c00 .........#.. .L.
│ │    0x004bd320 00000000 00000000 00000000 00000000 ................
│ │    0x004bd330 00000000 a75d0800 e0230900 d48a4c00 .....]...#....L.
│ │ -  0x004bd340 00000000 97500a00 e0230900 248b4c00 .....P...#..$.L.
│ │ +  0x004bd340 00000000 be500a00 e0230900 248b4c00 .....P...#..$.L.
│ │    0x004bd350 00000000 de1f0900 e0230900 c0944c00 .........#....L.
│ │    0x004bd360 00000000 b5f60800 e0230900 9c904c00 .........#....L.
│ │ -  0x004bd370 00000000 b6180a00 e0230900 a0914c00 .........#....L.
│ │ +  0x004bd370 00000000 dd180a00 e0230900 a0914c00 .........#....L.
│ │    0x004bd380 00000000 e0a80700 e0230900 bc934c00 .........#....L.
│ │ -  0x004bd390 00000000 dec00900 e0230900 10954c00 .........#....L.
│ │ -  0x004bd3a0 00000000 28500a00 e0230900 18974c00 ....(P...#....L.
│ │ +  0x004bd390 00000000 05c10900 e0230900 10954c00 .........#....L.
│ │ +  0x004bd3a0 00000000 4f500a00 e0230900 18974c00 ....OP...#....L.
│ │    0x004bd3b0 00000000 500d0900 e0230900 448e4c00 ....P....#..D.L.
│ │ -  0x004bd3c0 00000000 b9d60900 e0230900 f4974c00 .........#....L.
│ │ -  0x004bd3d0 00000000 c7ed0900 e0230900 a4924c00 .........#....L.
│ │ +  0x004bd3c0 00000000 e0d60900 e0230900 f4974c00 .........#....L.
│ │ +  0x004bd3d0 00000000 eeed0900 e0230900 a4924c00 .........#....L.
│ │    0x004bd3e0 00000000 cc550800 e0230900 c08f4c00 .....U...#....L.
│ │ -  0x004bd3f0 00000000 ba270a00 e0230900 548d4c00 .....'...#..T.L.
│ │ +  0x004bd3f0 00000000 e1270a00 e0230900 548d4c00 .....'...#..T.L.
│ │    0x004bd400 00000000 8cc60700 e0230900 d0884c00 .........#....L.
│ │    0x004bd410 00000000 94c60700 e0230900 18894c00 .........#....L.
│ │ -  0x004bd420 00000000 857d0900 e0230900 60894c00 .....}...#..`.L.
│ │ +  0x004bd420 00000000 ac7d0900 e0230900 60894c00 .....}...#..`.L.
│ │    0x004bd430 00000000 00000000 00000000 00000000 ................
│ │    0x004bd440 00000000 955d0a00 e0230900 d4cd4c00 .....]...#....L.
│ │    0x004bd450 00000000 1ddf0700 e0230900 14d04c00 .........#....L.
│ │    0x004bd460 00000000 c9940700 e0230900 2cd24c00 .........#..,.L.
│ │    0x004bd470 00000000 4cf50700 e0230900 6cd44c00 ....L....#..l.L.
│ │    0x004bd480 00000000 086d0800 e0230900 34d54c00 .....m...#..4.L.
│ │    0x004bd490 00000000 00000000 00000000 00000000 ................
│ │    0x004bd4a0 00000000 57cb0800 e0230900 149c4c00 ....W....#....L.
│ │    0x004bd4b0 a9b50800 7ecb0800 e0230900 c49c4c00 ....~....#....L.
│ │ -  0x004bd4c0 efed0900 d5920900 e0230900 8ca24c00 .........#....L.
│ │ -  0x004bd4d0 81490a00 099e0800 e0230900 f8be4c00 .I.......#....L.
│ │ -  0x004bd4e0 9cc60700 ced60900 e0230900 90bf4c00 .........#....L.
│ │ +  0x004bd4c0 16ee0900 fc920900 e0230900 8ca24c00 .........#....L.
│ │ +  0x004bd4d0 a8490a00 099e0800 e0230900 f8be4c00 .I.......#....L.
│ │ +  0x004bd4e0 9cc60700 f5d60900 e0230900 90bf4c00 .........#....L.
│ │    0x004bd4f0 accb0800 d2600a00 e0230900 5ca64c00 .....`...#..\.L.
│ │    0x004bd500 d4550800 fcf70700 e0230900 48b84c00 .U.......#..H.L.
│ │ -  0x004bd510 126d0800 9c490a00 e0230900 f0b84c00 .m...I...#....L.
│ │ -  0x004bd520 d71c0a00 309e0800 e0230900 98b94c00 ....0....#....L.
│ │ -  0x004bd530 f6600a00 f7d60900 e0230900 40ba4c00 .`.......#..@.L.
│ │ -  0x004bd540 ef850800 28500a00 e0230900 78bc4c00 ....(P...#..x.L.
│ │ +  0x004bd510 126d0800 c3490a00 e0230900 f0b84c00 .m...I...#....L.
│ │ +  0x004bd520 fe1c0a00 309e0800 e0230900 98b94c00 ....0....#....L.
│ │ +  0x004bd530 f6600a00 1ed70900 e0230900 40ba4c00 .`.......#..@.L.
│ │ +  0x004bd540 ef850800 4f500a00 e0230900 78bc4c00 ....OP...#..x.L.
│ │    0x004bd550 48260800 a75d0800 e0230900 78bc4c00 H&...]...#..x.L.
│ │ -  0x004bd560 ee550800 c7ed0900 e0230900 78bc4c00 .U.......#..x.L.
│ │ -  0x004bd570 09d70900 aa2d0800 e0230900 98bc4c00 .....-...#....L.
│ │ +  0x004bd560 ee550800 eeed0900 e0230900 78bc4c00 .U.......#..x.L.
│ │ +  0x004bd570 30d70900 aa2d0800 e0230900 98bc4c00 0....-...#....L.
│ │    0x004bd580 cb0e0800 f1230900 e0230900 98bc4c00 .....#...#....L.
│ │    0x004bd590 306d0800 009e0800 e0230900 98bc4c00 0m.......#....L.
│ │ -  0x004bd5a0 17560800 45630900 e0230900 28bd4c00 .V..Ec...#..(.L.
│ │ -  0x004bd5b0 ba320a00 cab50800 e0230900 24a74c00 .2.......#..$.L.
│ │ -  0x004bd5c0 45520900 00000000 00000000 00000000 ER..............
│ │ +  0x004bd5a0 17560800 6c630900 e0230900 28bd4c00 .V..lc...#..(.L.
│ │ +  0x004bd5b0 e1320a00 cab50800 e0230900 24a74c00 .2.......#..$.L.
│ │ +  0x004bd5c0 6c520900 00000000 00000000 00000000 lR..............
│ │    0x004bd5d0 00000000 57cb0800 e0230900 84844c00 ....W....#....L.
│ │    0x004bd5e0 00000000 62e40700 e0230900 f4854c00 ....b....#....L.
│ │    0x004bd5f0 00000000 fcf70700 e0230900 50874c00 .........#..P.L.
│ │ -  0x004bd600 00000000 9c490a00 e0230900 98874c00 .....I...#....L.
│ │ -  0x004bd610 00000000 28500a00 e0230900 e0874c00 ....(P...#....L.
│ │ +  0x004bd600 00000000 c3490a00 e0230900 98874c00 .....I...#....L.
│ │ +  0x004bd610 00000000 4f500a00 e0230900 e0874c00 ....OP...#....L.
│ │    0x004bd620 00000000 a75d0800 e0230900 30884c00 .....]...#..0.L.
│ │ -  0x004bd630 00000000 c7ed0900 e0230900 80884c00 .........#....L.
│ │ +  0x004bd630 00000000 eeed0900 e0230900 80884c00 .........#....L.
│ │    0x004bd640 00000000 00000000 00000000 00000000 ................
│ │ -  0x004bd650 00000000 d5920900 e0230900 a8d64c00 .........#....L.
│ │ +  0x004bd650 00000000 fc920900 e0230900 a8d64c00 .........#....L.
│ │    0x004bd660 00000000 5c6d0800 e0230900 58d74c00 ....\m...#..X.L.
│ │ -  0x004bd670 00000000 f5c00900 e0230900 f0d74c00 .........#....L.
│ │ -  0x004bd680 00000000 60520900 e0230900 88d84c00 ....`R...#....L.
│ │ -  0x004bd690 00000000 f9920900 e0230900 20d94c00 .........#.. .L.
│ │ -  0x004bd6a0 00000000 34c10900 e0230900 b8d94c00 ....4....#....L.
│ │ +  0x004bd670 00000000 1cc10900 e0230900 f0d74c00 .........#....L.
│ │ +  0x004bd680 00000000 87520900 e0230900 88d84c00 .....R...#....L.
│ │ +  0x004bd690 00000000 20930900 e0230900 20d94c00 .... ....#.. .L.
│ │ +  0x004bd6a0 00000000 5bc10900 e0230900 b8d94c00 ....[....#....L.
│ │    0x004bd6b0 00000000 0ff80700 e0230900 50da4c00 .........#..P.L.
│ │    0x004bd6c0 00000000 5af80700 e0230900 e8da4c00 ....Z....#....L.
│ │ -  0x004bd6d0 00000000 2aa90900 e0230900 80db4c00 ....*....#....L.
│ │ -  0x004bd6e0 00000000 9f520900 e0230900 18dc4c00 .....R...#....L.
│ │ +  0x004bd6d0 00000000 51a90900 e0230900 80db4c00 ....Q....#....L.
│ │ +  0x004bd6e0 00000000 c6520900 e0230900 18dc4c00 .....R...#....L.
│ │    0x004bd6f0 00000000 099e0800 e0230900 a4e94c00 .........#....L.
│ │ -  0x004bd700 00000000 40040a00 e0230900 64ea4c00 ....@....#..d.L.
│ │ -  0x004bd710 00000000 ad490a00 e0230900 0ceb4c00 .....I...#....L.
│ │ +  0x004bd700 00000000 67040a00 e0230900 64ea4c00 ....g....#..d.L.
│ │ +  0x004bd710 00000000 d4490a00 e0230900 0ceb4c00 .....I...#....L.
│ │    0x004bd720 00000000 0c860800 e0230900 b4eb4c00 .........#....L.
│ │    0x004bd730 00000000 15610a00 e0230900 5cec4c00 .....a...#..\.L.
│ │ -  0x004bd740 00000000 f31c0a00 e0230900 04ed4c00 .........#....L.
│ │ +  0x004bd740 00000000 1a1d0a00 e0230900 04ed4c00 .........#....L.
│ │    0x004bd750 00000000 44560800 e0230900 aced4c00 ....DV...#....L.
│ │    0x004bd760 00000000 083e0900 e0230900 54ee4c00 .....>...#..T.L.
│ │    0x004bd770 00000000 f40e0800 e0230900 fcee4c00 .........#....L.
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│ │ -  0x004bd790 00000000 85c10900 e0230900 4cf04c00 .........#..L.L.
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│ │ +  0x004be1e0 00000000 a72d0800 3c330a00 14564c00 .....-..<3...VL.
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│ │ -  0x004be200 00000000 f6d30800 59ee0900 94574c00 ........Y....WL.
│ │ -  0x004be210 00000000 f6d30800 96ee0900 d4574c00 .............WL.
│ │ -  0x004be220 00000000 6c900800 59ee0900 14584c00 ....l...Y....XL.
│ │ -  0x004be230 00000000 6c900800 96ee0900 54584c00 ....l.......TXL.
│ │ -  0x004be240 00000000 df740800 59ee0900 94564c00 .....t..Y....VL.
│ │ -  0x004be250 00000000 df740800 96ee0900 d4564c00 .....t.......VL.
│ │ -  0x004be260 00000000 a6390a00 59ee0900 14574c00 .....9..Y....WL.
│ │ -  0x004be270 00000000 a6390a00 96ee0900 54574c00 .....9......TWL.
│ │ +  0x004be200 00000000 f6d30800 80ee0900 94574c00 .............WL.
│ │ +  0x004be210 00000000 f6d30800 bdee0900 d4574c00 .............WL.
│ │ +  0x004be220 00000000 6c900800 80ee0900 14584c00 ....l........XL.
│ │ +  0x004be230 00000000 6c900800 bdee0900 54584c00 ....l.......TXL.
│ │ +  0x004be240 00000000 df740800 80ee0900 94564c00 .....t.......VL.
│ │ +  0x004be250 00000000 df740800 bdee0900 d4564c00 .....t.......VL.
│ │ +  0x004be260 00000000 cd390a00 80ee0900 14574c00 .....9.......WL.
│ │ +  0x004be270 00000000 cd390a00 bdee0900 54574c00 .....9......TWL.
│ │    0x004be280 00000000 c3310800 0c870800 94584c00 .....1.......XL.
│ │    0x004be290 00000000 c3310800 383e0800 d4584c00 .....1..8>...XL.
│ │ -  0x004be2a0 00000000 c3310800 ea7d0900 14594c00 .....1...}...YL.
│ │ -  0x004be2b0 00000000 25120900 59ee0900 54594c00 ....%...Y...TYL.
│ │ -  0x004be2c0 00000000 25120900 96ee0900 94594c00 ....%........YL.
│ │ -  0x004be2d0 00000000 25120900 15330a00 d4594c00 ....%....3...YL.
│ │ +  0x004be2a0 00000000 c3310800 117e0900 14594c00 .....1...~...YL.
│ │ +  0x004be2b0 00000000 25120900 80ee0900 54594c00 ....%.......TYL.
│ │ +  0x004be2c0 00000000 25120900 bdee0900 94594c00 ....%........YL.
│ │ +  0x004be2d0 00000000 25120900 3c330a00 d4594c00 ....%...<3...YL.
│ │    0x004be2e0 00000000 25120900 2dc70700 145a4c00 ....%...-....ZL.
│ │ -  0x004be2f0 00000000 64d00800 59ee0900 545a4c00 ....d...Y...TZL.
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│ │ -  0x004be310 00000000 25120900 c37d0900 38624c00 ....%....}..8bL.
│ │ +  0x004be2f0 00000000 64d00800 80ee0900 545a4c00 ....d.......TZL.
│ │ +  0x004be300 00000000 64d00800 bdee0900 945a4c00 ....d........ZL.
│ │ +  0x004be310 00000000 25120900 ea7d0900 38624c00 ....%....}..8bL.
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│ │ +  0x004be330 00000000 e2760800 bdee0900 a8644c00 .....v.......dL.
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│ │    0x004be350 00000000 e2760800 7a3e0800 b0614c00 .....v..z>...aL.
│ │    0x004be360 00000000 00000000 00000000 00000000 ................
│ │ -  0x004be370 00000000 f5460a00 8d610a00 3cf64c00 .....F...a..<.L.
│ │ +  0x004be370 00000000 1c470a00 8d610a00 3cf64c00 .....G...a..<.L.
│ │    0x004be380 00000000 00000000 00000000 00000000 ................
│ │    0x004be390 00000000 d4d04b00 643d4e00 94d24b00 ......K.d=N...K.
│ │    0x004be3a0 34d34b00 44d44b00 00000000 00000000 4.K.D.K.........
│ │    0x004be3b0 00000000 00000000 a4d44b00 d4d54b00 ..........K...K.
│ │    0x004be3c0 54d64b00 24d94b00 54d94b00 00000000 T.K.$.K.T.K.....
│ │    0x004be3d0 00000000 00000000 00000000 00000000 ................
│ │    0x004be3e0 a4d94b00 e4e04b00 74e34b00 01040000 ..K...K.t.K.....
│ │ @@ -9379,727 +9379,727 @@
│ │    0x004be410 06000000 00000000 00000000 ffffffff ................
│ │    0x004be420 ea8a0800 06000000 00000000 00000000 ................
│ │    0x004be430 ffffffff 89250800 06000000 00000000 .....%..........
│ │    0x004be440 00000000 ffffffff a1940700 01000000 ................
│ │    0x004be450 00000000 00000000 ffffffff 00000000 ................
│ │    0x004be460 00000000 00000000 00000000 00000000 ................
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│ │ -  0x004be480 ffffffff 509a0900 04000000 84790800 ....P........y..
│ │ +  0x004be480 ffffffff 779a0900 04000000 84790800 ....w........y..
│ │    0x004be490 0a000000 ffffffff 56d00800 04000000 ........V.......
│ │    0x004be4a0 a72d0800 03000000 ffffffff be2d0800 .-...........-..
│ │    0x004be4b0 02000000 f03b0f00 04000000 ffffffff .....;..........
│ │    0x004be4c0 4fce0700 02000000 f43b0f00 04000000 O........;......
│ │    0x004be4d0 ffffffff d3bb0800 01000000 f83b0f00 .............;..
│ │    0x004be4e0 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004be4f0 fc3b0f00 04000000 ffffffff 689a0900 .;..........h...
│ │ +  0x004be4f0 fc3b0f00 04000000 ffffffff 8f9a0900 .;..............
│ │    0x004be500 01000000 003c0f00 04000000 ffffffff .....<..........
│ │    0x004be510 efe40800 01000000 043c0f00 04000000 .........<......
│ │    0x004be520 ffffffff 00000000 00000000 00000000 ................
│ │    0x004be530 00000000 00000000 af2d0800 04000000 .........-......
│ │ -  0x004be540 51d40700 06000000 ffffffff 509a0900 Q...........P...
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│ │    0x004be550 04000000 84790800 0a000000 ffffffff .....y..........
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│ │    0x004be570 ffffffff be2d0800 02000000 f03b0f00 .....-.......;..
│ │    0x004be580 04000000 ffffffff 4fce0700 02000000 ........O.......
│ │    0x004be590 f43b0f00 04000000 ffffffff d3bb0800 .;..............
│ │    0x004be5a0 01000000 f83b0f00 04000000 ffffffff .....;..........
│ │    0x004be5b0 cafe0700 01000000 fc3b0f00 04000000 .........;......
│ │ -  0x004be5c0 ffffffff 689a0900 01000000 003c0f00 ....h........<..
│ │ +  0x004be5c0 ffffffff 8f9a0900 01000000 003c0f00 .............<..
│ │    0x004be5d0 04000000 ffffffff efe40800 01000000 ................
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│ │    0x004be5f0 00000000 00000000 00000000 00000000 ................
│ │    0x004be600 af2d0800 04000000 8cc00800 0a000000 .-..............
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│ │    0x004be620 0a000000 ffffffff 56d00800 04000000 ........V.......
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│ │    0x004be650 4fce0700 02000000 0c3c0f00 04000000 O........<......
│ │    0x004be660 ffffffff d3bb0800 01000000 103c0f00 .............<..
│ │    0x004be670 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004be680 143c0f00 04000000 ffffffff 689a0900 .<..........h...
│ │ +  0x004be680 143c0f00 04000000 ffffffff 8f9a0900 .<..............
│ │    0x004be690 01000000 183c0f00 04000000 ffffffff .....<..........
│ │    0x004be6a0 efe40800 01000000 1c3c0f00 04000000 .........<......
│ │    0x004be6b0 ffffffff 00000000 00000000 00000000 ................
│ │    0x004be6c0 00000000 00000000 af2d0800 04000000 .........-......
│ │ -  0x004be6d0 33470900 0a000000 ffffffff 509a0900 3G..........P...
│ │ +  0x004be6d0 33470900 0a000000 ffffffff 779a0900 3G..........w...
│ │    0x004be6e0 04000000 33470900 0a000000 ffffffff ....3G..........
│ │    0x004be6f0 56d00800 04000000 a72d0800 03000000 V........-......
│ │    0x004be700 ffffffff be2d0800 02000000 203c0f00 .....-...... <..
│ │    0x004be710 04000000 ffffffff 4fce0700 02000000 ........O.......
│ │    0x004be720 243c0f00 04000000 ffffffff d3bb0800 $<..............
│ │    0x004be730 01000000 283c0f00 04000000 ffffffff ....(<..........
│ │    0x004be740 cafe0700 01000000 2c3c0f00 04000000 ........,<......
│ │ -  0x004be750 ffffffff 689a0900 01000000 303c0f00 ....h.......0<..
│ │ +  0x004be750 ffffffff 8f9a0900 01000000 303c0f00 ............0<..
│ │    0x004be760 04000000 ffffffff efe40800 01000000 ................
│ │    0x004be770 343c0f00 04000000 ffffffff 00000000 4<..............
│ │    0x004be780 00000000 00000000 00000000 00000000 ................
│ │    0x004be790 af2d0800 04000000 d2310900 06000000 .-.......1......
│ │ -  0x004be7a0 ffffffff 509a0900 04000000 33470900 ....P.......3G..
│ │ +  0x004be7a0 ffffffff 779a0900 04000000 33470900 ....w.......3G..
│ │    0x004be7b0 0a000000 ffffffff 56d00800 04000000 ........V.......
│ │    0x004be7c0 a72d0800 03000000 ffffffff be2d0800 .-...........-..
│ │    0x004be7d0 02000000 203c0f00 04000000 ffffffff .... <..........
│ │    0x004be7e0 4fce0700 02000000 243c0f00 04000000 O.......$<......
│ │    0x004be7f0 ffffffff d3bb0800 01000000 283c0f00 ............(<..
│ │    0x004be800 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004be810 2c3c0f00 04000000 ffffffff 689a0900 ,<..........h...
│ │ +  0x004be810 2c3c0f00 04000000 ffffffff 8f9a0900 ,<..............
│ │    0x004be820 01000000 303c0f00 04000000 ffffffff ....0<..........
│ │    0x004be830 efe40800 01000000 343c0f00 04000000 ........4<......
│ │    0x004be840 ffffffff 00000000 00000000 00000000 ................
│ │    0x004be850 00000000 00000000 af2d0800 04000000 .........-......
│ │ -  0x004be860 c93e0a00 0a000000 ffffffff 509a0900 .>..........P...
│ │ -  0x004be870 04000000 c93e0a00 0a000000 ffffffff .....>..........
│ │ +  0x004be860 f03e0a00 0a000000 ffffffff 779a0900 .>..........w...
│ │ +  0x004be870 04000000 f03e0a00 0a000000 ffffffff .....>..........
│ │    0x004be880 56d00800 04000000 a72d0800 03000000 V........-......
│ │    0x004be890 ffffffff be2d0800 02000000 383c0f00 .....-......8<..
│ │    0x004be8a0 04000000 ffffffff 4fce0700 02000000 ........O.......
│ │    0x004be8b0 3c3c0f00 04000000 ffffffff d3bb0800 <<..............
│ │    0x004be8c0 01000000 403c0f00 04000000 ffffffff ....@<..........
│ │    0x004be8d0 cafe0700 01000000 443c0f00 04000000 ........D<......
│ │ -  0x004be8e0 ffffffff 689a0900 01000000 483c0f00 ....h.......H<..
│ │ +  0x004be8e0 ffffffff 8f9a0900 01000000 483c0f00 ............H<..
│ │    0x004be8f0 04000000 ffffffff efe40800 01000000 ................
│ │    0x004be900 4c3c0f00 04000000 ffffffff 00000000 L<..............
│ │    0x004be910 00000000 00000000 00000000 00000000 ................
│ │    0x004be920 af2d0800 04000000 24a10700 0a000000 .-......$.......
│ │ -  0x004be930 ffffffff 509a0900 04000000 24a10700 ....P.......$...
│ │ +  0x004be930 ffffffff 779a0900 04000000 24a10700 ....w.......$...
│ │    0x004be940 0a000000 ffffffff 56d00800 04000000 ........V.......
│ │    0x004be950 a72d0800 03000000 ffffffff be2d0800 .-...........-..
│ │    0x004be960 02000000 503c0f00 04000000 ffffffff ....P<..........
│ │    0x004be970 4fce0700 02000000 543c0f00 04000000 O.......T<......
│ │    0x004be980 ffffffff d3bb0800 01000000 583c0f00 ............X<..
│ │    0x004be990 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004be9a0 5c3c0f00 04000000 ffffffff 689a0900 \<..........h...
│ │ +  0x004be9a0 5c3c0f00 04000000 ffffffff 8f9a0900 \<..............
│ │    0x004be9b0 01000000 603c0f00 04000000 ffffffff ....`<..........
│ │    0x004be9c0 efe40800 01000000 643c0f00 04000000 ........d<......
│ │    0x004be9d0 ffffffff 00000000 00000000 00000000 ................
│ │    0x004be9e0 00000000 00000000 af2d0800 04000000 .........-......
│ │ -  0x004be9f0 304a0800 0a000000 ffffffff 509a0900 0J..........P...
│ │ +  0x004be9f0 304a0800 0a000000 ffffffff 779a0900 0J..........w...
│ │    0x004bea00 04000000 304a0800 0a000000 ffffffff ....0J..........
│ │    0x004bea10 56d00800 04000000 a72d0800 03000000 V........-......
│ │    0x004bea20 ffffffff be2d0800 02000000 683c0f00 .....-......h<..
│ │    0x004bea30 04000000 ffffffff 4fce0700 02000000 ........O.......
│ │    0x004bea40 6c3c0f00 04000000 ffffffff d3bb0800 l<..............
│ │    0x004bea50 01000000 703c0f00 04000000 ffffffff ....p<..........
│ │    0x004bea60 cafe0700 01000000 743c0f00 04000000 ........t<......
│ │ -  0x004bea70 ffffffff 689a0900 01000000 783c0f00 ....h.......x<..
│ │ +  0x004bea70 ffffffff 8f9a0900 01000000 783c0f00 ............x<..
│ │    0x004bea80 04000000 ffffffff efe40800 01000000 ................
│ │    0x004bea90 7c3c0f00 04000000 ffffffff 00000000 |<..............
│ │    0x004beaa0 00000000 00000000 00000000 00000000 ................
│ │    0x004beab0 af2d0800 04000000 ec180900 06000000 .-..............
│ │ -  0x004beac0 ffffffff 509a0900 04000000 304a0800 ....P.......0J..
│ │ +  0x004beac0 ffffffff 779a0900 04000000 304a0800 ....w.......0J..
│ │    0x004bead0 0a000000 ffffffff 56d00800 04000000 ........V.......
│ │    0x004beae0 a72d0800 03000000 ffffffff be2d0800 .-...........-..
│ │    0x004beaf0 02000000 683c0f00 04000000 ffffffff ....h<..........
│ │    0x004beb00 4fce0700 02000000 6c3c0f00 04000000 O.......l<......
│ │    0x004beb10 ffffffff d3bb0800 01000000 703c0f00 ............p<..
│ │    0x004beb20 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004beb30 743c0f00 04000000 ffffffff 689a0900 t<..........h...
│ │ +  0x004beb30 743c0f00 04000000 ffffffff 8f9a0900 t<..............
│ │    0x004beb40 01000000 783c0f00 04000000 ffffffff ....x<..........
│ │    0x004beb50 efe40800 01000000 7c3c0f00 04000000 ........|<......
│ │    0x004beb60 ffffffff 00000000 00000000 00000000 ................
│ │    0x004beb70 00000000 00000000 af2d0800 04000000 .........-......
│ │ -  0x004beb80 8e790800 0a000000 ffffffff 509a0900 .y..........P...
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│ │    0x004beb90 04000000 8e790800 0a000000 ffffffff .....y..........
│ │    0x004beba0 56d00800 04000000 a72d0800 03000000 V........-......
│ │    0x004bebb0 ffffffff be2d0800 02000000 803c0f00 .....-.......<..
│ │    0x004bebc0 04000000 ffffffff 4fce0700 02000000 ........O.......
│ │    0x004bebd0 843c0f00 04000000 ffffffff d3bb0800 .<..............
│ │    0x004bebe0 01000000 883c0f00 04000000 ffffffff .....<..........
│ │    0x004bebf0 cafe0700 01000000 8c3c0f00 04000000 .........<......
│ │ -  0x004bec00 ffffffff 689a0900 01000000 903c0f00 ....h........<..
│ │ +  0x004bec00 ffffffff 8f9a0900 01000000 903c0f00 .............<..
│ │    0x004bec10 04000000 ffffffff efe40800 01000000 ................
│ │    0x004bec20 943c0f00 04000000 ffffffff 00000000 .<..............
│ │    0x004bec30 00000000 00000000 00000000 00000000 ................
│ │    0x004bec40 af2d0800 04000000 2e880700 06000000 .-..............
│ │ -  0x004bec50 ffffffff 509a0900 04000000 8e790800 ....P........y..
│ │ +  0x004bec50 ffffffff 779a0900 04000000 8e790800 ....w........y..
│ │    0x004bec60 0a000000 ffffffff 56d00800 04000000 ........V.......
│ │    0x004bec70 a72d0800 03000000 ffffffff be2d0800 .-...........-..
│ │    0x004bec80 02000000 803c0f00 04000000 ffffffff .....<..........
│ │    0x004bec90 4fce0700 02000000 843c0f00 04000000 O........<......
│ │    0x004beca0 ffffffff d3bb0800 01000000 883c0f00 .............<..
│ │    0x004becb0 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004becc0 8c3c0f00 04000000 ffffffff 689a0900 .<..........h...
│ │ +  0x004becc0 8c3c0f00 04000000 ffffffff 8f9a0900 .<..............
│ │    0x004becd0 01000000 903c0f00 04000000 ffffffff .....<..........
│ │    0x004bece0 efe40800 01000000 943c0f00 04000000 .........<......
│ │    0x004becf0 ffffffff 00000000 00000000 00000000 ................
│ │    0x004bed00 00000000 00000000 af2d0800 04000000 .........-......
│ │ -  0x004bed10 daea0800 0a000000 ffffffff 509a0900 ............P...
│ │ +  0x004bed10 daea0800 0a000000 ffffffff 779a0900 ............w...
│ │    0x004bed20 04000000 daea0800 0a000000 ffffffff ................
│ │    0x004bed30 56d00800 04000000 a72d0800 03000000 V........-......
│ │    0x004bed40 ffffffff be2d0800 02000000 983c0f00 .....-.......<..
│ │    0x004bed50 04000000 ffffffff 4fce0700 02000000 ........O.......
│ │    0x004bed60 9c3c0f00 04000000 ffffffff d3bb0800 .<..............
│ │    0x004bed70 01000000 a03c0f00 04000000 ffffffff .....<..........
│ │    0x004bed80 cafe0700 01000000 a43c0f00 04000000 .........<......
│ │ -  0x004bed90 ffffffff 689a0900 01000000 a83c0f00 ....h........<..
│ │ +  0x004bed90 ffffffff 8f9a0900 01000000 a83c0f00 .............<..
│ │    0x004beda0 04000000 ffffffff efe40800 01000000 ................
│ │    0x004bedb0 ac3c0f00 04000000 ffffffff 00000000 .<..............
│ │    0x004bedc0 00000000 00000000 00000000 00000000 ................
│ │ -  0x004bedd0 af2d0800 04000000 30f80900 0a000000 .-......0.......
│ │ -  0x004bede0 ffffffff 509a0900 04000000 30f80900 ....P.......0...
│ │ +  0x004bedd0 af2d0800 04000000 57f80900 0a000000 .-......W.......
│ │ +  0x004bede0 ffffffff 779a0900 04000000 57f80900 ....w.......W...
│ │    0x004bedf0 0a000000 ffffffff 56d00800 04000000 ........V.......
│ │    0x004bee00 a72d0800 03000000 ffffffff be2d0800 .-...........-..
│ │    0x004bee10 02000000 b03c0f00 04000000 ffffffff .....<..........
│ │    0x004bee20 4fce0700 02000000 b43c0f00 04000000 O........<......
│ │    0x004bee30 ffffffff d3bb0800 01000000 b83c0f00 .............<..
│ │    0x004bee40 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004bee50 bc3c0f00 04000000 ffffffff 689a0900 .<..........h...
│ │ +  0x004bee50 bc3c0f00 04000000 ffffffff 8f9a0900 .<..............
│ │    0x004bee60 01000000 c03c0f00 04000000 ffffffff .....<..........
│ │    0x004bee70 efe40800 01000000 c43c0f00 04000000 .........<......
│ │    0x004bee80 ffffffff 00000000 00000000 00000000 ................
│ │    0x004bee90 00000000 00000000 af2d0800 04000000 .........-......
│ │ -  0x004beea0 57620800 06000000 ffffffff 509a0900 Wb..........P...
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│ │ +  0x004beea0 57620800 06000000 ffffffff 779a0900 Wb..........w...
│ │ +  0x004beeb0 04000000 57f80900 0a000000 ffffffff ....W...........
│ │    0x004beec0 56d00800 04000000 a72d0800 03000000 V........-......
│ │    0x004beed0 ffffffff be2d0800 02000000 b03c0f00 .....-.......<..
│ │    0x004beee0 04000000 ffffffff 4fce0700 02000000 ........O.......
│ │    0x004beef0 b43c0f00 04000000 ffffffff d3bb0800 .<..............
│ │    0x004bef00 01000000 b83c0f00 04000000 ffffffff .....<..........
│ │    0x004bef10 cafe0700 01000000 bc3c0f00 04000000 .........<......
│ │ -  0x004bef20 ffffffff 689a0900 01000000 c03c0f00 ....h........<..
│ │ +  0x004bef20 ffffffff 8f9a0900 01000000 c03c0f00 .............<..
│ │    0x004bef30 04000000 ffffffff efe40800 01000000 ................
│ │    0x004bef40 c43c0f00 04000000 ffffffff 00000000 .<..............
│ │    0x004bef50 00000000 00000000 00000000 00000000 ................
│ │    0x004bef60 af2d0800 04000000 781a0800 0a000000 .-......x.......
│ │ -  0x004bef70 ffffffff 509a0900 04000000 781a0800 ....P.......x...
│ │ +  0x004bef70 ffffffff 779a0900 04000000 781a0800 ....w.......x...
│ │    0x004bef80 0a000000 ffffffff 56d00800 04000000 ........V.......
│ │    0x004bef90 a72d0800 03000000 ffffffff be2d0800 .-...........-..
│ │    0x004befa0 02000000 c83c0f00 04000000 ffffffff .....<..........
│ │    0x004befb0 4fce0700 02000000 cc3c0f00 04000000 O........<......
│ │    0x004befc0 ffffffff d3bb0800 01000000 d03c0f00 .............<..
│ │    0x004befd0 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004befe0 d43c0f00 04000000 ffffffff 689a0900 .<..........h...
│ │ +  0x004befe0 d43c0f00 04000000 ffffffff 8f9a0900 .<..............
│ │    0x004beff0 01000000 d83c0f00 04000000 ffffffff .....<..........
│ │    0x004bf000 efe40800 01000000 dc3c0f00 04000000 .........<......
│ │    0x004bf010 ffffffff 00000000 00000000 00000000 ................
│ │    0x004bf020 00000000 00000000 af2d0800 04000000 .........-......
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│ │    0x004bf040 04000000 781a0800 0a000000 ffffffff ....x...........
│ │    0x004bf050 56d00800 04000000 a72d0800 03000000 V........-......
│ │    0x004bf060 ffffffff be2d0800 02000000 c83c0f00 .....-.......<..
│ │    0x004bf070 04000000 ffffffff 4fce0700 02000000 ........O.......
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│ │    0x004bf090 01000000 d03c0f00 04000000 ffffffff .....<..........
│ │    0x004bf0a0 cafe0700 01000000 d43c0f00 04000000 .........<......
│ │ -  0x004bf0b0 ffffffff 689a0900 01000000 d83c0f00 ....h........<..
│ │ +  0x004bf0b0 ffffffff 8f9a0900 01000000 d83c0f00 .............<..
│ │    0x004bf0c0 04000000 ffffffff efe40800 01000000 ................
│ │    0x004bf0d0 dc3c0f00 04000000 ffffffff 00000000 .<..............
│ │    0x004bf0e0 00000000 00000000 00000000 00000000 ................
│ │ -  0x004bf0f0 af2d0800 04000000 1e100a00 0a000000 .-..............
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│ │ +  0x004bf0f0 af2d0800 04000000 45100a00 0a000000 .-......E.......
│ │ +  0x004bf100 ffffffff 779a0900 04000000 45100a00 ....w.......E...
│ │    0x004bf110 0a000000 ffffffff 56d00800 04000000 ........V.......
│ │    0x004bf120 a72d0800 03000000 ffffffff be2d0800 .-...........-..
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│ │    0x004bf150 ffffffff d3bb0800 01000000 e83c0f00 .............<..
│ │    0x004bf160 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004bf170 ec3c0f00 04000000 ffffffff 689a0900 .<..........h...
│ │ +  0x004bf170 ec3c0f00 04000000 ffffffff 8f9a0900 .<..............
│ │    0x004bf180 01000000 f03c0f00 04000000 ffffffff .....<..........
│ │    0x004bf190 efe40800 01000000 f43c0f00 04000000 .........<......
│ │    0x004bf1a0 ffffffff 00000000 00000000 00000000 ................
│ │    0x004bf1b0 00000000 00000000 af2d0800 04000000 .........-......
│ │ -  0x004bf1c0 77e30900 06000000 ffffffff 509a0900 w...........P...
│ │ -  0x004bf1d0 04000000 1e100a00 0a000000 ffffffff ................
│ │ +  0x004bf1c0 9ee30900 06000000 ffffffff 779a0900 ............w...
│ │ +  0x004bf1d0 04000000 45100a00 0a000000 ffffffff ....E...........
│ │    0x004bf1e0 56d00800 04000000 a72d0800 03000000 V........-......
│ │    0x004bf1f0 ffffffff be2d0800 02000000 e03c0f00 .....-.......<..
│ │    0x004bf200 04000000 ffffffff 4fce0700 02000000 ........O.......
│ │    0x004bf210 e43c0f00 04000000 ffffffff d3bb0800 .<..............
│ │    0x004bf220 01000000 e83c0f00 04000000 ffffffff .....<..........
│ │    0x004bf230 cafe0700 01000000 ec3c0f00 04000000 .........<......
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│ │ +  0x004bf240 ffffffff 8f9a0900 01000000 f03c0f00 .............<..
│ │    0x004bf250 04000000 ffffffff efe40800 01000000 ................
│ │    0x004bf260 f43c0f00 04000000 ffffffff 00000000 .<..............
│ │    0x004bf270 00000000 00000000 00000000 00000000 ................
│ │    0x004bf280 af2d0800 04000000 b8310900 0a000000 .-.......1......
│ │ -  0x004bf290 ffffffff 509a0900 04000000 b8310900 ....P........1..
│ │ +  0x004bf290 ffffffff 779a0900 04000000 b8310900 ....w........1..
│ │    0x004bf2a0 0a000000 ffffffff 56d00800 04000000 ........V.......
│ │    0x004bf2b0 a72d0800 03000000 ffffffff be2d0800 .-...........-..
│ │    0x004bf2c0 02000000 f83c0f00 04000000 ffffffff .....<..........
│ │    0x004bf2d0 4fce0700 02000000 fc3c0f00 04000000 O........<......
│ │    0x004bf2e0 ffffffff d3bb0800 01000000 003d0f00 .............=..
│ │    0x004bf2f0 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004bf300 043d0f00 04000000 ffffffff 689a0900 .=..........h...
│ │ +  0x004bf300 043d0f00 04000000 ffffffff 8f9a0900 .=..............
│ │    0x004bf310 01000000 083d0f00 04000000 ffffffff .....=..........
│ │    0x004bf320 efe40800 01000000 0c3d0f00 04000000 .........=......
│ │    0x004bf330 ffffffff 00000000 00000000 00000000 ................
│ │    0x004bf340 00000000 00000000 af2d0800 04000000 .........-......
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│ │ +  0x004bf350 51620800 06000000 ffffffff 779a0900 Qb..........w...
│ │    0x004bf360 04000000 b8310900 0a000000 ffffffff .....1..........
│ │    0x004bf370 56d00800 04000000 a72d0800 03000000 V........-......
│ │    0x004bf380 ffffffff be2d0800 02000000 f83c0f00 .....-.......<..
│ │    0x004bf390 04000000 ffffffff 4fce0700 02000000 ........O.......
│ │    0x004bf3a0 fc3c0f00 04000000 ffffffff d3bb0800 .<..............
│ │    0x004bf3b0 01000000 003d0f00 04000000 ffffffff .....=..........
│ │    0x004bf3c0 cafe0700 01000000 043d0f00 04000000 .........=......
│ │ -  0x004bf3d0 ffffffff 689a0900 01000000 083d0f00 ....h........=..
│ │ +  0x004bf3d0 ffffffff 8f9a0900 01000000 083d0f00 .............=..
│ │    0x004bf3e0 04000000 ffffffff efe40800 01000000 ................
│ │    0x004bf3f0 0c3d0f00 04000000 ffffffff 00000000 .=..............
│ │    0x004bf400 00000000 00000000 00000000 00000000 ................
│ │    0x004bf410 af2d0800 04000000 0dd40700 0a000000 .-..............
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│ │    0x004bf440 a72d0800 03000000 ffffffff be2d0800 .-...........-..
│ │    0x004bf450 02000000 103d0f00 04000000 ffffffff .....=..........
│ │    0x004bf460 4fce0700 02000000 143d0f00 04000000 O........=......
│ │    0x004bf470 ffffffff d3bb0800 01000000 183d0f00 .............=..
│ │    0x004bf480 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004bf490 1c3d0f00 04000000 ffffffff 689a0900 .=..........h...
│ │ +  0x004bf490 1c3d0f00 04000000 ffffffff 8f9a0900 .=..............
│ │    0x004bf4a0 01000000 203d0f00 04000000 ffffffff .... =..........
│ │    0x004bf4b0 efe40800 01000000 243d0f00 04000000 ........$=......
│ │    0x004bf4c0 ffffffff 00000000 00000000 00000000 ................
│ │    0x004bf4d0 00000000 00000000 af2d0800 04000000 .........-......
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│ │    0x004bf4f0 04000000 0dd40700 0a000000 ffffffff ................
│ │    0x004bf500 56d00800 04000000 a72d0800 03000000 V........-......
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│ │    0x004bf520 04000000 ffffffff 4fce0700 02000000 ........O.......
│ │    0x004bf530 143d0f00 04000000 ffffffff d3bb0800 .=..............
│ │    0x004bf540 01000000 183d0f00 04000000 ffffffff .....=..........
│ │    0x004bf550 cafe0700 01000000 1c3d0f00 04000000 .........=......
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│ │ +  0x004bf560 ffffffff 8f9a0900 01000000 203d0f00 ............ =..
│ │    0x004bf570 04000000 ffffffff efe40800 01000000 ................
│ │    0x004bf580 243d0f00 04000000 ffffffff 00000000 $=..............
│ │    0x004bf590 00000000 00000000 00000000 00000000 ................
│ │    0x004bf5a0 af2d0800 04000000 17d40700 0a000000 .-..............
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│ │    0x004bf5c0 0a000000 ffffffff 56d00800 04000000 ........V.......
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│ │    0x004bf5e0 02000000 283d0f00 04000000 ffffffff ....(=..........
│ │    0x004bf5f0 4fce0700 02000000 2c3d0f00 04000000 O.......,=......
│ │    0x004bf600 ffffffff d3bb0800 01000000 303d0f00 ............0=..
│ │    0x004bf610 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004bf620 343d0f00 04000000 ffffffff 689a0900 4=..........h...
│ │ +  0x004bf620 343d0f00 04000000 ffffffff 8f9a0900 4=..............
│ │    0x004bf630 01000000 383d0f00 04000000 ffffffff ....8=..........
│ │    0x004bf640 efe40800 01000000 3c3d0f00 04000000 ........<=......
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│ │    0x004bf660 00000000 00000000 af2d0800 04000000 .........-......
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│ │    0x004bf680 04000000 17d40700 0a000000 ffffffff ................
│ │    0x004bf690 56d00800 04000000 a72d0800 03000000 V........-......
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│ │    0x004bf6b0 04000000 ffffffff 4fce0700 02000000 ........O.......
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│ │    0x004bf6d0 01000000 303d0f00 04000000 ffffffff ....0=..........
│ │    0x004bf6e0 cafe0700 01000000 343d0f00 04000000 ........4=......
│ │ -  0x004bf6f0 ffffffff 689a0900 01000000 383d0f00 ....h.......8=..
│ │ +  0x004bf6f0 ffffffff 8f9a0900 01000000 383d0f00 ............8=..
│ │    0x004bf700 04000000 ffffffff efe40800 01000000 ................
│ │    0x004bf710 3c3d0f00 04000000 ffffffff 00000000 <=..............
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│ │ +  0x004bf740 ffffffff 779a0900 04000000 591a0800 ....w.......Y...
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│ │    0x004bf760 a72d0800 03000000 ffffffff be2d0800 .-...........-..
│ │    0x004bf770 02000000 403d0f00 04000000 ffffffff ....@=..........
│ │    0x004bf780 4fce0700 02000000 443d0f00 04000000 O.......D=......
│ │    0x004bf790 ffffffff d3bb0800 01000000 483d0f00 ............H=..
│ │    0x004bf7a0 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004bf7b0 4c3d0f00 04000000 ffffffff 689a0900 L=..........h...
│ │ +  0x004bf7b0 4c3d0f00 04000000 ffffffff 8f9a0900 L=..............
│ │    0x004bf7c0 01000000 503d0f00 04000000 ffffffff ....P=..........
│ │    0x004bf7d0 efe40800 01000000 543d0f00 04000000 ........T=......
│ │    0x004bf7e0 ffffffff 00000000 00000000 00000000 ................
│ │    0x004bf7f0 00000000 00000000 af2d0800 04000000 .........-......
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│ │    0x004bf820 56d00800 04000000 a72d0800 03000000 V........-......
│ │    0x004bf830 ffffffff be2d0800 02000000 583d0f00 .....-......X=..
│ │    0x004bf840 04000000 ffffffff 4fce0700 02000000 ........O.......
│ │    0x004bf850 5c3d0f00 04000000 ffffffff d3bb0800 \=..............
│ │    0x004bf860 01000000 603d0f00 04000000 ffffffff ....`=..........
│ │    0x004bf870 cafe0700 01000000 643d0f00 04000000 ........d=......
│ │ -  0x004bf880 ffffffff 689a0900 01000000 683d0f00 ....h.......h=..
│ │ +  0x004bf880 ffffffff 8f9a0900 01000000 683d0f00 ............h=..
│ │    0x004bf890 04000000 ffffffff efe40800 01000000 ................
│ │    0x004bf8a0 6c3d0f00 04000000 ffffffff 00000000 l=..............
│ │    0x004bf8b0 00000000 00000000 00000000 00000000 ................
│ │ -  0x004bf8c0 af2d0800 04000000 a93e0a00 0a000000 .-.......>......
│ │ -  0x004bf8d0 ffffffff 509a0900 04000000 a93e0a00 ....P........>..
│ │ +  0x004bf8c0 af2d0800 04000000 d03e0a00 0a000000 .-.......>......
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│ │    0x004bf8e0 0a000000 ffffffff 56d00800 04000000 ........V.......
│ │    0x004bf8f0 a72d0800 03000000 ffffffff be2d0800 .-...........-..
│ │    0x004bf900 02000000 703d0f00 04000000 ffffffff ....p=..........
│ │    0x004bf910 4fce0700 02000000 743d0f00 04000000 O.......t=......
│ │    0x004bf920 ffffffff d3bb0800 01000000 783d0f00 ............x=..
│ │    0x004bf930 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004bf940 7c3d0f00 04000000 ffffffff 689a0900 |=..........h...
│ │ +  0x004bf940 7c3d0f00 04000000 ffffffff 8f9a0900 |=..............
│ │    0x004bf950 01000000 803d0f00 04000000 ffffffff .....=..........
│ │    0x004bf960 efe40800 01000000 843d0f00 04000000 .........=......
│ │    0x004bf970 ffffffff 00000000 00000000 00000000 ................
│ │    0x004bf980 00000000 00000000 af2d0800 04000000 .........-......
│ │ -  0x004bf990 52e30900 0a000000 ffffffff 509a0900 R...........P...
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│ │ +  0x004bf990 79e30900 0a000000 ffffffff 779a0900 y...........w...
│ │ +  0x004bf9a0 04000000 79e30900 0a000000 ffffffff ....y...........
│ │    0x004bf9b0 56d00800 04000000 a72d0800 03000000 V........-......
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│ │    0x004bf9d0 04000000 ffffffff 4fce0700 02000000 ........O.......
│ │    0x004bf9e0 8c3d0f00 04000000 ffffffff d3bb0800 .=..............
│ │    0x004bf9f0 01000000 903d0f00 04000000 ffffffff .....=..........
│ │    0x004bfa00 cafe0700 01000000 943d0f00 04000000 .........=......
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│ │ +  0x004bfa10 ffffffff 8f9a0900 01000000 983d0f00 .............=..
│ │    0x004bfa20 04000000 ffffffff efe40800 01000000 ................
│ │    0x004bfa30 9c3d0f00 04000000 ffffffff 00000000 .=..............
│ │    0x004bfa40 00000000 00000000 00000000 00000000 ................
│ │    0x004bfa50 af2d0800 04000000 81270800 0a000000 .-.......'......
│ │ -  0x004bfa60 ffffffff 509a0900 04000000 02d40700 ....P...........
│ │ +  0x004bfa60 ffffffff 779a0900 04000000 02d40700 ....w...........
│ │    0x004bfa70 0b000000 ffffffff 56d00800 04000000 ........V.......
│ │    0x004bfa80 a72d0800 03000000 ffffffff be2d0800 .-...........-..
│ │    0x004bfa90 02000000 a03d0f00 04000000 ffffffff .....=..........
│ │    0x004bfaa0 4fce0700 02000000 a43d0f00 04000000 O........=......
│ │    0x004bfab0 ffffffff d3bb0800 01000000 a83d0f00 .............=..
│ │    0x004bfac0 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004bfad0 ac3d0f00 04000000 ffffffff 689a0900 .=..........h...
│ │ +  0x004bfad0 ac3d0f00 04000000 ffffffff 8f9a0900 .=..............
│ │    0x004bfae0 01000000 b03d0f00 04000000 ffffffff .....=..........
│ │    0x004bfaf0 efe40800 01000000 b43d0f00 04000000 .........=......
│ │    0x004bfb00 ffffffff 00000000 00000000 00000000 ................
│ │    0x004bfb10 00000000 00000000 af2d0800 04000000 .........-......
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│ │ +  0x004bfb20 4a4a0800 06000000 ffffffff 779a0900 JJ..........w...
│ │    0x004bfb30 04000000 02d40700 0b000000 ffffffff ................
│ │    0x004bfb40 56d00800 04000000 a72d0800 03000000 V........-......
│ │    0x004bfb50 ffffffff be2d0800 02000000 a03d0f00 .....-.......=..
│ │    0x004bfb60 04000000 ffffffff 4fce0700 02000000 ........O.......
│ │    0x004bfb70 a43d0f00 04000000 ffffffff d3bb0800 .=..............
│ │    0x004bfb80 01000000 a83d0f00 04000000 ffffffff .....=..........
│ │    0x004bfb90 cafe0700 01000000 ac3d0f00 04000000 .........=......
│ │ -  0x004bfba0 ffffffff 689a0900 01000000 b03d0f00 ....h........=..
│ │ +  0x004bfba0 ffffffff 8f9a0900 01000000 b03d0f00 .............=..
│ │    0x004bfbb0 04000000 ffffffff efe40800 01000000 ................
│ │    0x004bfbc0 b43d0f00 04000000 ffffffff 00000000 .=..............
│ │    0x004bfbd0 00000000 00000000 00000000 00000000 ................
│ │    0x004bfbe0 af2d0800 04000000 59910800 0a000000 .-......Y.......
│ │ -  0x004bfbf0 ffffffff 509a0900 04000000 59910800 ....P.......Y...
│ │ +  0x004bfbf0 ffffffff 779a0900 04000000 59910800 ....w.......Y...
│ │    0x004bfc00 0a000000 ffffffff 56d00800 04000000 ........V.......
│ │    0x004bfc10 a72d0800 03000000 ffffffff be2d0800 .-...........-..
│ │    0x004bfc20 02000000 b83d0f00 04000000 ffffffff .....=..........
│ │    0x004bfc30 4fce0700 02000000 bc3d0f00 04000000 O........=......
│ │    0x004bfc40 ffffffff d3bb0800 01000000 c03d0f00 .............=..
│ │    0x004bfc50 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004bfc60 c43d0f00 04000000 ffffffff 689a0900 .=..........h...
│ │ +  0x004bfc60 c43d0f00 04000000 ffffffff 8f9a0900 .=..............
│ │    0x004bfc70 01000000 c83d0f00 04000000 ffffffff .....=..........
│ │    0x004bfc80 efe40800 01000000 cc3d0f00 04000000 .........=......
│ │    0x004bfc90 ffffffff 00000000 00000000 00000000 ................
│ │    0x004bfca0 00000000 00000000 af2d0800 04000000 .........-......
│ │ -  0x004bfcb0 24880700 0a000000 ffffffff 509a0900 $...........P...
│ │ +  0x004bfcb0 24880700 0a000000 ffffffff 779a0900 $...........w...
│ │    0x004bfcc0 04000000 24880700 0a000000 ffffffff ....$...........
│ │    0x004bfcd0 56d00800 04000000 a72d0800 03000000 V........-......
│ │    0x004bfce0 ffffffff be2d0800 02000000 d03d0f00 .....-.......=..
│ │    0x004bfcf0 04000000 ffffffff 4fce0700 02000000 ........O.......
│ │    0x004bfd00 d43d0f00 04000000 ffffffff d3bb0800 .=..............
│ │    0x004bfd10 01000000 d83d0f00 04000000 ffffffff .....=..........
│ │    0x004bfd20 cafe0700 01000000 dc3d0f00 04000000 .........=......
│ │ -  0x004bfd30 ffffffff 689a0900 01000000 e03d0f00 ....h........=..
│ │ +  0x004bfd30 ffffffff 8f9a0900 01000000 e03d0f00 .............=..
│ │    0x004bfd40 04000000 ffffffff efe40800 01000000 ................
│ │    0x004bfd50 e43d0f00 04000000 ffffffff 00000000 .=..............
│ │    0x004bfd60 00000000 00000000 00000000 00000000 ................
│ │    0x004bfd70 af2d0800 04000000 c2a90800 06000000 .-..............
│ │ -  0x004bfd80 ffffffff 509a0900 04000000 24880700 ....P.......$...
│ │ +  0x004bfd80 ffffffff 779a0900 04000000 24880700 ....w.......$...
│ │    0x004bfd90 0a000000 ffffffff 56d00800 04000000 ........V.......
│ │    0x004bfda0 a72d0800 03000000 ffffffff be2d0800 .-...........-..
│ │    0x004bfdb0 02000000 d03d0f00 04000000 ffffffff .....=..........
│ │    0x004bfdc0 4fce0700 02000000 d43d0f00 04000000 O........=......
│ │    0x004bfdd0 ffffffff d3bb0800 01000000 d83d0f00 .............=..
│ │    0x004bfde0 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004bfdf0 dc3d0f00 04000000 ffffffff 689a0900 .=..........h...
│ │ +  0x004bfdf0 dc3d0f00 04000000 ffffffff 8f9a0900 .=..............
│ │    0x004bfe00 01000000 e03d0f00 04000000 ffffffff .....=..........
│ │    0x004bfe10 efe40800 01000000 e43d0f00 04000000 .........=......
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│ │    0x004bfed0 04000000 ffffffff efe40800 01000000 ................
│ │    0x004bfee0 fc3d0f00 04000000 ffffffff 00000000 .=..............
│ │    0x004bfef0 00000000 00000000 00000000 00000000 ................
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│ │    0x004bff30 a72d0800 03000000 ffffffff be2d0800 .-...........-..
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│ │    0x004bff50 4fce0700 02000000 043e0f00 04000000 O........>......
│ │    0x004bff60 ffffffff d3bb0800 01000000 083e0f00 .............>..
│ │    0x004bff70 04000000 ffffffff cafe0700 01000000 ................
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│ │    0x004bffb0 ffffffff 00000000 00000000 00000000 ................
│ │    0x004bffc0 00000000 00000000 af2d0800 04000000 .........-......
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│ │ +  0x004c0050 ffffffff 8f9a0900 01000000 103e0f00 .............>..
│ │    0x004c0060 04000000 ffffffff efe40800 01000000 ................
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│ │    0x004c00f0 ffffffff d3bb0800 01000000 203e0f00 ............ >..
│ │    0x004c0100 04000000 ffffffff cafe0700 01000000 ................
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│ │    0x004c0130 efe40800 01000000 2c3e0f00 04000000 ........,>......
│ │    0x004c0140 ffffffff 00000000 00000000 00000000 ................
│ │    0x004c0150 00000000 00000000 af2d0800 04000000 .........-......
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│ │    0x004c01c0 01000000 203e0f00 04000000 ffffffff .... >..........
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│ │    0x004c0280 ffffffff d3bb0800 01000000 383e0f00 ............8>..
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│ │    0x004c0390 443e0f00 04000000 ffffffff 00000000 D>..............
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│ │ -  0x004c03b0 af2d0800 04000000 6e100a00 10000000 .-......n.......
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│ │    0x004c0410 ffffffff d3bb0800 01000000 503e0f00 ............P>..
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│ │ +  0x004c0430 543e0f00 04000000 ffffffff 8f9a0900 T>..............
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│ │ +  0x004c0490 04000000 04cd0900 10000000 ffffffff ................
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│ │ +  0x004c0500 ffffffff 8f9a0900 01000000 703e0f00 ............p>..
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│ │    0x004c0520 743e0f00 04000000 ffffffff 00000000 t>..............
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│ │    0x004c05a0 ffffffff d3bb0800 01000000 803e0f00 .............>..
│ │    0x004c05b0 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004c05c0 843e0f00 04000000 ffffffff 689a0900 .>..........h...
│ │ +  0x004c05c0 843e0f00 04000000 ffffffff 8f9a0900 .>..............
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│ │    0x004c0600 00000000 00000000 af2d0800 04000000 .........-......
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│ │ +  0x004c0690 ffffffff 8f9a0900 01000000 a03e0f00 .............>..
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│ │    0x004c06b0 a43e0f00 04000000 ffffffff 00000000 .>..............
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│ │ -  0x004c06d0 af2d0800 04000000 6f940900 05000000 .-......o.......
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│ │    0x004c06f0 05000000 ffffffff 56d00800 04000000 ........V.......
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│ │ +  0x004c0700 cd390a00 05000000 ffffffff be2d0800 .9...........-..
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│ │    0x004c0720 4fce0700 02000000 ac3e0f00 04000000 O........>......
│ │    0x004c0730 ffffffff d3bb0800 01000000 b03e0f00 .............>..
│ │    0x004c0740 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004c0750 b43e0f00 04000000 ffffffff 689a0900 .>..........h...
│ │ +  0x004c0750 b43e0f00 04000000 ffffffff 8f9a0900 .>..............
│ │    0x004c0760 01000000 b83e0f00 04000000 ffffffff .....>..........
│ │    0x004c0770 efe40800 01000000 bc3e0f00 04000000 .........>......
│ │    0x004c0780 ffffffff 00000000 00000000 00000000 ................
│ │    0x004c0790 00000000 00000000 af2d0800 04000000 .........-......
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│ │ +  0x004c07b0 04000000 95100a00 10000000 ffffffff ................
│ │    0x004c07c0 56d00800 04000000 a72d0800 03000000 V........-......
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│ │    0x004c07f0 c43e0f00 04000000 ffffffff d3bb0800 .>..............
│ │    0x004c0800 01000000 c83e0f00 04000000 ffffffff .....>..........
│ │    0x004c0810 cafe0700 01000000 cc3e0f00 04000000 .........>......
│ │ -  0x004c0820 ffffffff 689a0900 01000000 d03e0f00 ....h........>..
│ │ +  0x004c0820 ffffffff 8f9a0900 01000000 d03e0f00 .............>..
│ │    0x004c0830 04000000 ffffffff efe40800 01000000 ................
│ │    0x004c0840 d43e0f00 04000000 ffffffff 00000000 .>..............
│ │    0x004c0850 00000000 00000000 00000000 00000000 ................
│ │    0x004c0860 af2d0800 04000000 f21f0900 15000000 .-..............
│ │ -  0x004c0870 ffffffff 509a0900 04000000 ddcc0900 ....P...........
│ │ +  0x004c0870 ffffffff 779a0900 04000000 04cd0900 ....w...........
│ │    0x004c0880 10000000 ffffffff 56d00800 04000000 ........V.......
│ │    0x004c0890 a72d0800 03000000 ffffffff be2d0800 .-...........-..
│ │    0x004c08a0 02000000 d83e0f00 04000000 ffffffff .....>..........
│ │    0x004c08b0 4fce0700 02000000 dc3e0f00 04000000 O........>......
│ │    0x004c08c0 ffffffff d3bb0800 01000000 e03e0f00 .............>..
│ │    0x004c08d0 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004c08e0 e43e0f00 04000000 ffffffff 689a0900 .>..........h...
│ │ +  0x004c08e0 e43e0f00 04000000 ffffffff 8f9a0900 .>..............
│ │    0x004c08f0 01000000 e83e0f00 04000000 ffffffff .....>..........
│ │    0x004c0900 efe40800 01000000 ec3e0f00 04000000 .........>......
│ │    0x004c0910 ffffffff 00000000 00000000 00000000 ................
│ │    0x004c0920 00000000 00000000 af2d0800 04000000 .........-......
│ │ -  0x004c0930 f2a40900 15000000 ffffffff 509a0900 ............P...
│ │ +  0x004c0930 19a50900 15000000 ffffffff 779a0900 ............w...
│ │    0x004c0940 04000000 41d40700 10000000 ffffffff ....A...........
│ │    0x004c0950 56d00800 04000000 a72d0800 03000000 V........-......
│ │    0x004c0960 ffffffff be2d0800 02000000 f03e0f00 .....-.......>..
│ │    0x004c0970 04000000 ffffffff 4fce0700 02000000 ........O.......
│ │    0x004c0980 f43e0f00 04000000 ffffffff d3bb0800 .>..............
│ │    0x004c0990 01000000 f83e0f00 04000000 ffffffff .....>..........
│ │    0x004c09a0 cafe0700 01000000 fc3e0f00 04000000 .........>......
│ │ -  0x004c09b0 ffffffff 689a0900 01000000 003f0f00 ....h........?..
│ │ +  0x004c09b0 ffffffff 8f9a0900 01000000 003f0f00 .............?..
│ │    0x004c09c0 04000000 ffffffff efe40800 01000000 ................
│ │    0x004c09d0 043f0f00 04000000 ffffffff 00000000 .?..............
│ │    0x004c09e0 00000000 00000000 00000000 00000000 ................
│ │    0x004c09f0 af2d0800 04000000 c5ba0700 0a000000 .-..............
│ │ -  0x004c0a00 ffffffff 509a0900 04000000 c5ba0700 ....P...........
│ │ +  0x004c0a00 ffffffff 779a0900 04000000 c5ba0700 ....w...........
│ │    0x004c0a10 0a000000 ffffffff 56d00800 04000000 ........V.......
│ │    0x004c0a20 5ecb0700 03000000 ffffffff be2d0800 ^............-..
│ │    0x004c0a30 02000000 083f0f00 04000000 ffffffff .....?..........
│ │    0x004c0a40 4fce0700 02000000 0c3f0f00 04000000 O........?......
│ │    0x004c0a50 ffffffff d3bb0800 01000000 103f0f00 .............?..
│ │    0x004c0a60 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004c0a70 143f0f00 04000000 ffffffff 689a0900 .?..........h...
│ │ +  0x004c0a70 143f0f00 04000000 ffffffff 8f9a0900 .?..............
│ │    0x004c0a80 01000000 183f0f00 04000000 ffffffff .....?..........
│ │    0x004c0a90 efe40800 01000000 1c3f0f00 04000000 .........?......
│ │    0x004c0aa0 ffffffff 00000000 00000000 00000000 ................
│ │    0x004c0ab0 00000000 00000000 af2d0800 04000000 .........-......
│ │ -  0x004c0ac0 22330800 0a000000 ffffffff 509a0900 "3..........P...
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│ │    0x004c0ad0 04000000 22330800 0a000000 ffffffff ...."3..........
│ │    0x004c0ae0 56d00800 04000000 5ecb0700 03000000 V.......^.......
│ │    0x004c0af0 ffffffff be2d0800 02000000 203f0f00 .....-...... ?..
│ │    0x004c0b00 04000000 ffffffff 4fce0700 02000000 ........O.......
│ │    0x004c0b10 243f0f00 04000000 ffffffff d3bb0800 $?..............
│ │    0x004c0b20 01000000 283f0f00 04000000 ffffffff ....(?..........
│ │    0x004c0b30 cafe0700 01000000 2c3f0f00 04000000 ........,?......
│ │ -  0x004c0b40 ffffffff 689a0900 01000000 303f0f00 ....h.......0?..
│ │ +  0x004c0b40 ffffffff 8f9a0900 01000000 303f0f00 ............0?..
│ │    0x004c0b50 04000000 ffffffff efe40800 01000000 ................
│ │    0x004c0b60 343f0f00 04000000 ffffffff 00000000 4?..............
│ │    0x004c0b70 00000000 00000000 00000000 00000000 ................
│ │ -  0x004c0b80 af2d0800 04000000 e7880900 0a000000 .-..............
│ │ -  0x004c0b90 ffffffff 509a0900 04000000 e7880900 ....P...........
│ │ +  0x004c0b80 af2d0800 04000000 0e890900 0a000000 .-..............
│ │ +  0x004c0b90 ffffffff 779a0900 04000000 0e890900 ....w...........
│ │    0x004c0ba0 0a000000 ffffffff 56d00800 04000000 ........V.......
│ │    0x004c0bb0 5ecb0700 03000000 ffffffff be2d0800 ^............-..
│ │    0x004c0bc0 02000000 383f0f00 04000000 ffffffff ....8?..........
│ │    0x004c0bd0 4fce0700 02000000 3c3f0f00 04000000 O.......<?......
│ │    0x004c0be0 ffffffff d3bb0800 01000000 403f0f00 ............@?..
│ │    0x004c0bf0 04000000 ffffffff cafe0700 01000000 ................
│ │ -  0x004c0c00 443f0f00 04000000 ffffffff 689a0900 D?..........h...
│ │ +  0x004c0c00 443f0f00 04000000 ffffffff 8f9a0900 D?..............
│ │    0x004c0c10 01000000 483f0f00 04000000 ffffffff ....H?..........
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│ │    0x004c1cd0 00000000 ffffffff 00000000 00000000 ................
│ │    0x004c1ce0 00000000 00000000 00000000 cafe0800 ................
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│ │    0x004c2240 00000000 50583900 5c5a3900 70623900 ....PX9.\Z9.pb9.
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│ │    0x004c26a0 00000000 00000000 00000000 00000000 ................
│ │ -  0x004c26b0 ea540a00 02000000 00000000 04000000 .T..............
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│ │    0x004c26d0 04000000 ffffffff 99ec0700 05000000 ................
│ │    0x004c26e0 00000000 00000000 ffffffff 00000000 ................
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│ │ +  0x004c3b20 11550a00 02000000 00000000 04000000 .U..............
│ │ +  0x004c3b30 ffffffff 14cd0900 02000000 00000000 ................
│ │    0x004c3b40 04000000 ffffffff 00000000 00000000 ................
│ │ -  0x004c3b50 00000000 00000000 00000000 ea540a00 .............T..
│ │ +  0x004c3b50 00000000 00000000 00000000 11550a00 .............U..
│ │    0x004c3b60 02000000 00000000 04000000 ffffffff ................
│ │ -  0x004c3b70 edcc0900 02000000 00000000 04000000 ................
│ │ +  0x004c3b70 14cd0900 02000000 00000000 04000000 ................
│ │    0x004c3b80 ffffffff 00000000 00000000 00000000 ................
│ │    0x004c3b90 00000000 00000000 74c23900 ccc23900 ........t.9...9.
│ │    0x004c3ba0 00000000 24c63900 01000000 60c63900 ....$.9.....`.9.
│ │    0x004c3bb0 07000000 f8c63900 08000000 30c73900 ......9.....0.9.
│ │    0x004c3bc0 02000000 c8c73900 03000000 48c83900 ......9.....H.9.
│ │    0x004c3bd0 04000000 c8c83900 05000000 90c93900 ......9.......9.
│ │    0x004c3be0 06000000 c8c83900 09000000 fcc93900 ......9.......9.
│ │    0x004c3bf0 0c000000 dcc23e00 0a000000 38ca3900 ......>.....8.9.
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│ │    0x004c3c10 0e000000 68c73e00 00000000 00000000 ....h.>.........
│ │ -  0x004c3c20 ea540a00 02000000 00000000 04000000 .T..............
│ │ -  0x004c3c30 ffffffff edcc0900 02000000 00000000 ................
│ │ +  0x004c3c20 11550a00 02000000 00000000 04000000 .U..............
│ │ +  0x004c3c30 ffffffff 14cd0900 02000000 00000000 ................
│ │    0x004c3c40 04000000 ffffffff fcdf0700 02000000 ................
│ │    0x004c3c50 00000000 04000000 ffffffff 99ec0700 ................
│ │    0x004c3c60 05000000 00000000 00000000 ffffffff ................
│ │    0x004c3c70 d8310900 02000000 00000000 04000000 .1..............
│ │    0x004c3c80 ffffffff 00000000 00000000 00000000 ................
│ │    0x004c3c90 00000000 00000000 f8ce3900 00000000 ..........9.....
│ │    0x004c3ca0 00000000 68cf3900 a8d83900 60d93900 ....h.9...9.`.9.
│ │ @@ -10799,17 +10799,17 @@
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│ │    0x004c3d30 b8e33900 0e000000 40e43900 00000000 ..9.....@.9.....
│ │ -  0x004c3d40 00000000 ea540a00 02000000 00000000 .....T..........
│ │ -  0x004c3d50 04000000 ffffffff edcc0900 02000000 ................
│ │ -  0x004c3d60 00000000 04000000 ffffffff 936f0900 .............o..
│ │ +  0x004c3d40 00000000 11550a00 02000000 00000000 .....U..........
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│ │ +  0x004c3d60 00000000 04000000 ffffffff ba6f0900 .............o..
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│ │    0x004c3d80 00000000 00000000 00000000 00000000 ................
│ │    0x004c3d90 00000000 e7830700 02000000 00000000 ................
│ │    0x004c3da0 04000000 ffffffff 00000000 00000000 ................
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│ │    0x004c8440 00000000 01000000 d8933b00 02000000 ..........;.....
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│ │ -  0x004c8510 00000000 ffffffff 2ec30900 04000000 ................
│ │ +  0x004c8510 00000000 ffffffff 55c30900 04000000 ........U.......
│ │    0x004c8520 00000000 00000000 ffffffff 23030900 ............#...
│ │    0x004c8530 02000000 00000000 04000000 ffffffff ................
│ │ -  0x004c8540 2ecd0900 05000000 00000000 00000000 ................
│ │ +  0x004c8540 55cd0900 05000000 00000000 00000000 U...............
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│ │    0x004c8560 00000000 ffffffff 00000000 00000000 ................
│ │    0x004c8570 00000000 00000000 00000000 a1040800 ................
│ │    0x004c8580 04000000 00000000 00000000 ffffffff ................
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│ │    0x004c85a0 ffffffff 23030900 02000000 00000000 ....#...........
│ │ -  0x004c85b0 04000000 ffffffff 2ecd0900 07000000 ................
│ │ +  0x004c85b0 04000000 ffffffff 55cd0900 07000000 ........U.......
│ │    0x004c85c0 00000000 00000000 ffffffff 80190900 ................
│ │    0x004c85d0 04000000 00000000 00000000 ffffffff ................
│ │    0x004c85e0 00000000 00000000 00000000 00000000 ................
│ │    0x004c85f0 00000000 01000000 f0c33b00 02000000 ..........;.....
│ │    0x004c8600 58c43b00 03000000 ecc43b00 04000000 X.;.......;.....
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│ │    0x004c8630 9ccc3b00 09000000 accc3b00 0a000000 ..;.......;.....
│ │    0x004c8640 2cce3b00 00000000 00000000 07a10700 ,.;.............
│ │    0x004c8650 01000000 00000000 04000000 ffffffff ................
│ │    0x004c8660 a1040800 04000000 00000000 00000000 ................
│ │    0x004c8670 ffffffff c51a0800 04000000 00000000 ................
│ │ -  0x004c8680 00000000 ffffffff 2ec30900 04000000 ................
│ │ +  0x004c8680 00000000 ffffffff 55c30900 04000000 ........U.......
│ │    0x004c8690 00000000 00000000 ffffffff 23030900 ............#...
│ │    0x004c86a0 02000000 00000000 04000000 ffffffff ................
│ │ -  0x004c86b0 2ecd0900 05000000 00000000 00000000 ................
│ │ +  0x004c86b0 55cd0900 05000000 00000000 00000000 U...............
│ │    0x004c86c0 ffffffff 00000000 00000000 00000000 ................
│ │    0x004c86d0 00000000 00000000 07a10700 01000000 ................
│ │    0x004c86e0 00000000 04000000 ffffffff a1040800 ................
│ │    0x004c86f0 04000000 00000000 00000000 ffffffff ................
│ │    0x004c8700 c51a0800 04000000 00000000 00000000 ................
│ │    0x004c8710 ffffffff 23030900 02000000 00000000 ....#...........
│ │ -  0x004c8720 04000000 ffffffff 2ecd0900 07000000 ................
│ │ +  0x004c8720 04000000 ffffffff 55cd0900 07000000 ........U.......
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│ │    0x004c8740 00000000 00000000 00000000 00000000 ................
│ │    0x004c8750 01000000 c8cf3b00 02000000 10d03b00 ......;.......;.
│ │    0x004c8760 03000000 14d03b00 04000000 6cd03b00 ......;.....l.;.
│ │    0x004c8770 05000000 14d13b00 06000000 4cd13b00 ......;.....L.;.
│ │    0x004c8780 09000000 78d23b00 0a000000 80d23b00 ....x.;.......;.
│ │    0x004c8790 00000000 00000000 01000000 90d23b00 ..............;.
│ │ @@ -12027,23 +12027,23 @@
│ │    0x004c8990 07000000 d8e53b00 0a000000 e8e53b00 ......;.......;.
│ │    0x004c89a0 00000000 00000000 744a0800 05000000 ........tJ......
│ │    0x004c89b0 00000000 00000000 ffffffff df9b0700 ................
│ │    0x004c89c0 05000000 00000000 00000000 ffffffff ................
│ │    0x004c89d0 7d150800 05000000 00000000 00000000 }...............
│ │    0x004c89e0 ffffffff b33f0900 05000000 00000000 .....?..........
│ │    0x004c89f0 00000000 ffffffff b5d40800 02000000 ................
│ │ -  0x004c8a00 00000000 04000000 ffffffff b59c0900 ................
│ │ +  0x004c8a00 00000000 04000000 ffffffff dc9c0900 ................
│ │    0x004c8a10 02000000 00000000 04000000 ffffffff ................
│ │    0x004c8a20 f9f80800 02000000 00000000 04000000 ................
│ │    0x004c8a30 ffffffff 29880800 02000000 00000000 ....)...........
│ │    0x004c8a40 04000000 ffffffff 6db70800 02000000 ........m.......
│ │ -  0x004c8a50 00000000 04000000 ffffffff 304c0a00 ............0L..
│ │ +  0x004c8a50 00000000 04000000 ffffffff 574c0a00 ............WL..
│ │    0x004c8a60 02000000 00000000 04000000 ffffffff ................
│ │    0x004c8a70 ea8a0800 02000000 00000000 04000000 ................
│ │ -  0x004c8a80 ffffffff 61f40900 04000000 00000000 ....a...........
│ │ +  0x004c8a80 ffffffff 88f40900 04000000 00000000 ................
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│ │    0x004c8ab0 02000000 00000000 04000000 ffffffff ................
│ │    0x004c8ac0 00000000 00000000 00000000 00000000 ................
│ │    0x004c8ad0 00000000 01000000 3c0f3c00 02000000 ........<.<.....
│ │    0x004c8ae0 840f3c00 03000000 c0103c00 04000000 ..<.......<.....
│ │    0x004c8af0 f4103c00 05000000 ac113c00 08000000 ..<.......<.....
│ │ @@ -12052,52 +12052,52 @@
│ │    0x004c8b20 00000000 01000000 3c0f3c00 02000000 ........<.<.....
│ │    0x004c8b30 840f3c00 03000000 c0103c00 04000000 ..<.......<.....
│ │    0x004c8b40 f4103c00 05000000 c0143c00 08000000 ..<.......<.....
│ │    0x004c8b50 44173c00 0b000000 54173c00 07000000 D.<.....T.<.....
│ │    0x004c8b60 00193c00 0a000000 10193c00 00000000 ..<.......<.....
│ │    0x004c8b70 00000000 dce50700 04000000 00000000 ................
│ │    0x004c8b80 00000000 ffffffff dce50700 01000000 ................
│ │ -  0x004c8b90 00000000 04000000 ffffffff 61f40900 ............a...
│ │ +  0x004c8b90 00000000 04000000 ffffffff 88f40900 ................
│ │    0x004c8ba0 04000000 00000000 00000000 ffffffff ................
│ │    0x004c8bb0 20820700 04000000 00000000 00000000  ...............
│ │    0x004c8bc0 ffffffff 36150800 05000000 00000000 ....6...........
│ │    0x004c8bd0 00000000 ffffffff df9b0700 05000000 ................
│ │    0x004c8be0 00000000 00000000 ffffffff fb1a0800 ................
│ │    0x004c8bf0 05000000 00000000 00000000 ffffffff ................
│ │    0x004c8c00 00000000 00000000 00000000 00000000 ................
│ │    0x004c8c10 00000000 b5d40800 02000000 00000000 ................
│ │    0x004c8c20 04000000 ffffffff fb1a0800 05000000 ................
│ │    0x004c8c30 00000000 00000000 ffffffff 00000000 ................
│ │    0x004c8c40 00000000 00000000 00000000 00000000 ................
│ │    0x004c8c50 dce50700 04000000 00000000 00000000 ................
│ │    0x004c8c60 ffffffff dce50700 01000000 00000000 ................
│ │ -  0x004c8c70 04000000 ffffffff 61f40900 04000000 ........a.......
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│ │ -  0x004c9d90 a4860900 04000000 00000000 00000000 ................
│ │ -  0x004c9da0 ffffffff edf60900 01000000 00000000 ................
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│ │ +  0x004c9da0 ffffffff 14f70900 01000000 00000000 ................
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│ │ +  0x004caf90 00000000 00000000 ffffffff b3710900 .............q..
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│ │ +  0x004cb1c0 00000000 00000000 ffffffff c9860900 ................
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│ │ +  0x004cb440 00000000 00000000 ffffffff c9860900 ................
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│ │ -  0x004cb760 00000000 00000000 ffffffff 33f70900 ............3...
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│ │ +  0x004cb760 00000000 00000000 ffffffff 5af70900 ............Z...
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│ │ +  0x004cb7b0 00000000 04000000 ffffffff c95b0900 .............[..
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│ │ -  0x004cbb30 00000000 ffffffff 015f0900 05000000 ........._......
│ │ -  0x004cbb40 00000000 00000000 ffffffff a25b0900 .............[..
│ │ +  0x004cbb30 00000000 ffffffff 285f0900 05000000 ........(_......
│ │ +  0x004cbb40 00000000 00000000 ffffffff c95b0900 .............[..
│ │    0x004cbb50 05000000 00000000 00000000 ffffffff ................
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│ │ -  0x004cbb80 00000000 00000000 015f0900 05000000 ........._......
│ │ -  0x004cbb90 00000000 00000000 ffffffff 61f40900 ............a...
│ │ +  0x004cbb80 00000000 00000000 285f0900 05000000 ........(_......
│ │ +  0x004cbb90 00000000 00000000 ffffffff 88f40900 ................
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│ │ -  0x004cbbc0 00000000 a25b0900 05000000 00000000 .....[..........
│ │ -  0x004cbbd0 00000000 ffffffff 22250a00 05000000 ........"%......
│ │ +  0x004cbbc0 00000000 c95b0900 05000000 00000000 .....[..........
│ │ +  0x004cbbd0 00000000 ffffffff 49250a00 05000000 ........I%......
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│ │    0x004cbbf0 00000000 00000000 00000000 00000000 ................
│ │    0x004cbc00 13320900 01000000 00000000 04000000 .2..............
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│ │    0x004cbc20 04000000 ffffffff d5020900 01000000 ................
│ │ -  0x004cbc30 00000000 04000000 ffffffff a25b0900 .............[..
│ │ +  0x004cbc30 00000000 04000000 ffffffff c95b0900 .............[..
│ │    0x004cbc40 05000000 00000000 00000000 ffffffff ................
│ │ -  0x004cbc50 22250a00 05000000 00000000 00000000 "%..............
│ │ +  0x004cbc50 49250a00 05000000 00000000 00000000 I%..............
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│ │    0x004cbc70 00000000 00000000 01000000 84303d00 .............0=.
│ │    0x004cbc80 0a000000 ec303d00 15000000 38313d00 .....0=.....81=.
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│ │    0x004cbd50 0e000000 78333d00 15000000 88333d00 ....x3=......3=.
│ │    0x004cbd60 17000000 d0333d00 28000000 d0343d00 .....3=.(....4=.
│ │    0x004cbd70 29000000 6c3a3d00 2a000000 30353d00 )...l:=.*...05=.
│ │    0x004cbd80 2b000000 6c3a3d00 02000000 883a3d00 +...l:=......:=.
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│ │ -  0x004cbdb0 00000000 00000000 22250a00 05000000 ........"%......
│ │ +  0x004cbdb0 00000000 00000000 49250a00 05000000 ........I%......
│ │    0x004cbdc0 00000000 00000000 ffffffff 00000000 ................
│ │    0x004cbdd0 00000000 00000000 00000000 00000000 ................
│ │ -  0x004cbde0 22250a00 05000000 00000000 00000000 "%..............
│ │ +  0x004cbde0 49250a00 05000000 00000000 00000000 I%..............
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│ │ -  0x004cbe00 00000000 00000000 22250a00 05000000 ........"%......
│ │ -  0x004cbe10 00000000 00000000 ffffffff 61f40900 ............a...
│ │ +  0x004cbe00 00000000 00000000 49250a00 05000000 ........I%......
│ │ +  0x004cbe10 00000000 00000000 ffffffff 88f40900 ................
│ │    0x004cbe20 04000000 00000000 00000000 ffffffff ................
│ │    0x004cbe30 00000000 00000000 00000000 00000000 ................
│ │ -  0x004cbe40 00000000 22250a00 05000000 00000000 ...."%..........
│ │ -  0x004cbe50 00000000 ffffffff 9a980900 04000000 ................
│ │ -  0x004cbe60 00000000 00000000 ffffffff 65c20900 ............e...
│ │ +  0x004cbe40 00000000 49250a00 05000000 00000000 ....I%..........
│ │ +  0x004cbe50 00000000 ffffffff c1980900 04000000 ................
│ │ +  0x004cbe60 00000000 00000000 ffffffff 8cc20900 ................
│ │    0x004cbe70 04000000 00000000 00000000 ffffffff ................
│ │    0x004cbe80 00000000 00000000 00000000 00000000 ................
│ │ -  0x004cbe90 00000000 22250a00 05000000 00000000 ...."%..........
│ │ -  0x004cbea0 00000000 ffffffff 9a980900 04000000 ................
│ │ -  0x004cbeb0 00000000 00000000 ffffffff 65c20900 ............e...
│ │ +  0x004cbe90 00000000 49250a00 05000000 00000000 ....I%..........
│ │ +  0x004cbea0 00000000 ffffffff c1980900 04000000 ................
│ │ +  0x004cbeb0 00000000 00000000 ffffffff 8cc20900 ................
│ │    0x004cbec0 04000000 00000000 00000000 ffffffff ................
│ │ -  0x004cbed0 61f40900 04000000 00000000 00000000 a...............
│ │ +  0x004cbed0 88f40900 04000000 00000000 00000000 ................
│ │    0x004cbee0 ffffffff 00000000 00000000 00000000 ................
│ │    0x004cbef0 00000000 00000000 01000000 943e3d00 .............>=.
│ │    0x004cbf00 02000000 ec3e3d00 04000000 f83e3d00 .....>=......>=.
│ │    0x004cbf10 05000000 20403d00 06000000 30403d00 .... @=.....0@=.
│ │    0x004cbf20 07000000 58413d00 08000000 90413d00 ....XA=......A=.
│ │    0x004cbf30 0a000000 e0413d00 0b000000 e4413d00 .....A=......A=.
│ │    0x004cbf40 0c000000 28443d00 15000000 38443d00 ....(D=.....8D=.
│ │ @@ -12901,89 +12901,89 @@
│ │    0x004cc030 13320900 01000000 00000000 04000000 .2..............
│ │    0x004cc040 ffffffff 8eeb0800 01000000 00000000 ................
│ │    0x004cc050 04000000 ffffffff d5020900 01000000 ................
│ │    0x004cc060 00000000 04000000 ffffffff 9ceb0800 ................
│ │    0x004cc070 04000000 00000000 00000000 ffffffff ................
│ │    0x004cc080 35320900 02000000 00000000 00000000 52..............
│ │    0x004cc090 ffffffff 2e030900 02000000 00000000 ................
│ │ -  0x004cc0a0 00000000 ffffffff 36cd0900 02000000 ........6.......
│ │ +  0x004cc0a0 00000000 ffffffff 5dcd0900 02000000 ........].......
│ │    0x004cc0b0 00000000 00000000 ffffffff 13480900 .............H..
│ │    0x004cc0c0 02000000 00000000 00000000 ffffffff ................
│ │ -  0x004cc0d0 7cf90900 02000000 00000000 00000000 |...............
│ │ -  0x004cc0e0 ffffffff 8e270a00 02000000 00000000 .....'..........
│ │ -  0x004cc0f0 00000000 ffffffff 38cd0900 02000000 ........8.......
│ │ +  0x004cc0d0 a3f90900 02000000 00000000 00000000 ................
│ │ +  0x004cc0e0 ffffffff b5270a00 02000000 00000000 .....'..........
│ │ +  0x004cc0f0 00000000 ffffffff 5fcd0900 02000000 ........_.......
│ │    0x004cc100 00000000 00000000 ffffffff 834a0800 .............J..
│ │    0x004cc110 02000000 00000000 00000000 ffffffff ................
│ │    0x004cc120 96c10800 02000000 00000000 00000000 ................
│ │    0x004cc130 ffffffff 5b920800 02000000 00000000 ....[...........
│ │ -  0x004cc140 00000000 ffffffff 20560a00 02000000 ........ V......
│ │ +  0x004cc140 00000000 ffffffff 47560a00 02000000 ........GV......
│ │    0x004cc150 00000000 00000000 ffffffff f5880700 ................
│ │    0x004cc160 02000000 00000000 00000000 ffffffff ................
│ │    0x004cc170 30030900 02000000 00000000 00000000 0...............
│ │ -  0x004cc180 ffffffff 03b50900 02000000 00000000 ................
│ │ +  0x004cc180 ffffffff 2ab50900 02000000 00000000 ....*...........
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│ │    0x004cc210 a2c10800 02000000 00000000 00000000 ................
│ │    0x004cc220 ffffffff 39d50800 02000000 00000000 ....9...........
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│ │    0x004cc240 00000000 00000000 ffffffff 67920800 ............g...
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│ │ -  0x004cc260 4d3f0a00 02000000 00000000 00000000 M?..............
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│ │    0x004cc7f0 b5d40800 02000000 00000000 04000000 ................
│ │    0x004cc800 ffffffff 45fb0700 02000000 00000000 ....E...........
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│ │    0x004cc890 f0633d00 04000000 30643d00 05000000 .c=.....0d=.....
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│ │ -  0x004cc910 61f40900 04000000 00000000 00000000 a...............
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│ │    0x004cc9f0 00000000 20820700 04000000 00000000 .... ...........
│ │ -  0x004cca00 00000000 ffffffff 61f40900 04000000 ........a.......
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│ │    0x004cca10 00000000 00000000 ffffffff 36150800 ............6...
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│ │    0x004cca30 a9f90800 01000000 00000000 04000000 ................
│ │    0x004cca40 ffffffff 88b70800 01000000 00000000 ................
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│ │ +  0x004cca50 04000000 ffffffff 0e520a00 02000000 .........R......
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│ │    0x004ccd00 08000000 80803d00 0c000000 44813d00 ......=.....D.=.
│ │    0x004ccd10 09000000 54813d00 00000000 00000000 ....T.=.........
│ │    0x004ccd20 b5d40800 02000000 00000000 04000000 ................
│ │    0x004ccd30 ffffffff ec3f0900 02000000 00000000 .....?..........
│ │ -  0x004ccd40 04000000 ffffffff 06550900 02000000 .........U......
│ │ +  0x004ccd40 04000000 ffffffff 2d550900 02000000 ........-U......
│ │    0x004ccd50 00000000 04000000 ffffffff 00000000 ................
│ │    0x004ccd60 00000000 00000000 00000000 00000000 ................
│ │    0x004ccd70 b5d40800 02000000 00000000 04000000 ................
│ │    0x004ccd80 ffffffff 36150800 05000000 00000000 ....6...........
│ │    0x004ccd90 00000000 ffffffff ec3f0900 02000000 .........?......
│ │ -  0x004ccda0 00000000 04000000 ffffffff 06550900 .............U..
│ │ +  0x004ccda0 00000000 04000000 ffffffff 2d550900 ............-U..
│ │    0x004ccdb0 02000000 00000000 04000000 ffffffff ................
│ │    0x004ccdc0 00000000 00000000 00000000 00000000 ................
│ │    0x004ccdd0 00000000 01000000 eca53d00 02000000 ..........=.....
│ │    0x004ccde0 5ca63d00 03000000 c8a63d00 04000000 \.=.......=.....
│ │    0x004ccdf0 64a73d00 05000000 f0a73d00 06000000 d.=.......=.....
│ │    0x004cce00 18a83d00 08000000 289d3d00 09000000 ..=.....(.=.....
│ │    0x004cce10 148b3d00 0a000000 1c8b3d00 0d000000 ..=.......=.....
│ │    0x004cce20 38a83d00 10000000 48a83d00 0c000000 8.=.....H.=.....
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│ │ -  0x004cce50 748f3d00 00000000 00000000 61f40900 t.=.........a...
│ │ +  0x004cce50 748f3d00 00000000 00000000 88f40900 t.=.............
│ │    0x004cce60 04000000 00000000 00000000 ffffffff ................
│ │ -  0x004cce70 9a980900 04000000 00000000 00000000 ................
│ │ +  0x004cce70 c1980900 04000000 00000000 00000000 ................
│ │    0x004cce80 ffffffff 77dc0800 01000000 00000000 ....w...........
│ │    0x004cce90 04000000 ffffffff 28510800 02000000 ........(Q......
│ │    0x004ccea0 00000000 04000000 ffffffff c3990800 ................
│ │    0x004cceb0 02000000 00000000 08000000 ffffffff ................
│ │    0x004ccec0 00000000 00000000 00000000 00000000 ................
│ │ -  0x004cced0 00000000 9a980900 04000000 00000000 ................
│ │ +  0x004cced0 00000000 c1980900 04000000 00000000 ................
│ │    0x004ccee0 00000000 ffffffff 77dc0800 01000000 ........w.......
│ │    0x004ccef0 00000000 04000000 ffffffff 31750800 ............1u..
│ │    0x004ccf00 01000000 00000000 04000000 ffffffff ................
│ │ -  0x004ccf10 26080a00 02000000 00000000 04000000 &...............
│ │ -  0x004ccf20 ffffffff 5fea0900 02000000 00000000 ...._...........
│ │ +  0x004ccf10 4d080a00 02000000 00000000 04000000 M...............
│ │ +  0x004ccf20 ffffffff 86ea0900 02000000 00000000 ................
│ │    0x004ccf30 04000000 ffffffff 7f700800 02000000 .........p......
│ │    0x004ccf40 00000000 04000000 ffffffff d2a00800 ................
│ │    0x004ccf50 02000000 00000000 04000000 ffffffff ................
│ │ -  0x004ccf60 1cda0900 02000000 00000000 04000000 ................
│ │ -  0x004ccf70 ffffffff c3c30900 02000000 00000000 ................
│ │ +  0x004ccf60 43da0900 02000000 00000000 04000000 C...............
│ │ +  0x004ccf70 ffffffff eac30900 02000000 00000000 ................
│ │    0x004ccf80 04000000 ffffffff 8e700800 02000000 .........p......
│ │    0x004ccf90 00000000 04000000 ffffffff cfb70800 ................
│ │    0x004ccfa0 02000000 00000000 04000000 ffffffff ................
│ │    0x004ccfb0 9a700800 02000000 00000000 04000000 .p..............
│ │    0x004ccfc0 ffffffff 06ca0700 01000000 00000000 ................
│ │    0x004ccfd0 04000000 ffffffff 28510800 02000000 ........(Q......
│ │    0x004ccfe0 00000000 04000000 ffffffff c3990800 ................
│ │ @@ -13156,30 +13156,30 @@
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│ │    0x004cd030 4cc83d00 05000000 c4c83d00 06000000 L.=.......=.....
│ │    0x004cd040 ecc83d00 08000000 289d3d00 09000000 ..=.....(.=.....
│ │    0x004cd050 148b3d00 0a000000 1c8b3d00 0d000000 ..=.......=.....
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│ │    0x004cd070 74c93d00 0f000000 84c93d00 11000000 t.=.......=.....
│ │    0x004cd080 58ca3d00 12000000 208b3d00 13000000 X.=..... .=.....
│ │ -  0x004cd090 748f3d00 00000000 00000000 61f40900 t.=.........a...
│ │ +  0x004cd090 748f3d00 00000000 00000000 88f40900 t.=.............
│ │    0x004cd0a0 04000000 00000000 00000000 ffffffff ................
│ │    0x004cd0b0 20820700 04000000 00000000 00000000  ...............
│ │    0x004cd0c0 ffffffff 28510800 02000000 00000000 ....(Q..........
│ │    0x004cd0d0 04000000 ffffffff c3990800 02000000 ................
│ │    0x004cd0e0 00000000 08000000 ffffffff 00000000 ................
│ │    0x004cd0f0 00000000 00000000 00000000 00000000 ................
│ │    0x004cd100 20820700 04000000 00000000 00000000  ...............
│ │    0x004cd110 ffffffff 31750800 01000000 00000000 ....1u..........
│ │ -  0x004cd120 04000000 ffffffff 26080a00 02000000 ........&.......
│ │ -  0x004cd130 00000000 04000000 ffffffff 5fea0900 ............_...
│ │ +  0x004cd120 04000000 ffffffff 4d080a00 02000000 ........M.......
│ │ +  0x004cd130 00000000 04000000 ffffffff 86ea0900 ................
│ │    0x004cd140 02000000 00000000 04000000 ffffffff ................
│ │    0x004cd150 7f700800 02000000 00000000 04000000 .p..............
│ │    0x004cd160 ffffffff d2a00800 02000000 00000000 ................
│ │ -  0x004cd170 04000000 ffffffff 1cda0900 02000000 ................
│ │ -  0x004cd180 00000000 04000000 ffffffff c3c30900 ................
│ │ +  0x004cd170 04000000 ffffffff 43da0900 02000000 ........C.......
│ │ +  0x004cd180 00000000 04000000 ffffffff eac30900 ................
│ │    0x004cd190 02000000 00000000 04000000 ffffffff ................
│ │    0x004cd1a0 8e700800 02000000 00000000 04000000 .p..............
│ │    0x004cd1b0 ffffffff cfb70800 02000000 00000000 ................
│ │    0x004cd1c0 04000000 ffffffff 9a700800 02000000 .........p......
│ │    0x004cd1d0 00000000 04000000 ffffffff 06ca0700 ................
│ │    0x004cd1e0 01000000 00000000 04000000 ffffffff ................
│ │    0x004cd1f0 28510800 02000000 00000000 04000000 (Q..............
│ │ @@ -13190,32 +13190,32 @@
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│ │    0x004cd250 b0d83d00 06000000 d8d83d00 08000000 ..=.......=.....
│ │    0x004cd260 289d3d00 09000000 148b3d00 0a000000 (.=.......=.....
│ │    0x004cd270 1c8b3d00 0d000000 f8d83d00 10000000 ..=.......=.....
│ │    0x004cd280 08d93d00 0c000000 60d93d00 0f000000 ..=.....`.=.....
│ │    0x004cd290 70d93d00 11000000 90da3d00 12000000 p.=.......=.....
│ │    0x004cd2a0 208b3d00 13000000 748f3d00 00000000  .=.....t.=.....
│ │ -  0x004cd2b0 00000000 61f40900 04000000 00000000 ....a...........
│ │ +  0x004cd2b0 00000000 88f40900 04000000 00000000 ................
│ │    0x004cd2c0 00000000 ffffffff 20820700 04000000 ........ .......
│ │    0x004cd2d0 00000000 00000000 ffffffff b50a0800 ................
│ │    0x004cd2e0 04000000 00000000 00000000 ffffffff ................
│ │    0x004cd2f0 28510800 02000000 00000000 04000000 (Q..............
│ │    0x004cd300 ffffffff c3990800 02000000 00000000 ................
│ │    0x004cd310 08000000 ffffffff 00000000 00000000 ................
│ │    0x004cd320 00000000 00000000 00000000 b50a0800 ................
│ │    0x004cd330 04000000 00000000 00000000 ffffffff ................
│ │    0x004cd340 20820700 04000000 00000000 00000000  ...............
│ │    0x004cd350 ffffffff 31750800 01000000 00000000 ....1u..........
│ │ -  0x004cd360 04000000 ffffffff 26080a00 02000000 ........&.......
│ │ -  0x004cd370 00000000 04000000 ffffffff 5fea0900 ............_...
│ │ +  0x004cd360 04000000 ffffffff 4d080a00 02000000 ........M.......
│ │ +  0x004cd370 00000000 04000000 ffffffff 86ea0900 ................
│ │    0x004cd380 02000000 00000000 04000000 ffffffff ................
│ │    0x004cd390 7f700800 02000000 00000000 04000000 .p..............
│ │    0x004cd3a0 ffffffff d2a00800 02000000 00000000 ................
│ │ -  0x004cd3b0 04000000 ffffffff 1cda0900 02000000 ................
│ │ -  0x004cd3c0 00000000 04000000 ffffffff c3c30900 ................
│ │ +  0x004cd3b0 04000000 ffffffff 43da0900 02000000 ........C.......
│ │ +  0x004cd3c0 00000000 04000000 ffffffff eac30900 ................
│ │    0x004cd3d0 02000000 00000000 04000000 ffffffff ................
│ │    0x004cd3e0 8e700800 02000000 00000000 04000000 .p..............
│ │    0x004cd3f0 ffffffff cfb70800 02000000 00000000 ................
│ │    0x004cd400 04000000 ffffffff 9a700800 02000000 .........p......
│ │    0x004cd410 00000000 04000000 ffffffff 06ca0700 ................
│ │    0x004cd420 01000000 00000000 04000000 ffffffff ................
│ │    0x004cd430 28510800 02000000 00000000 04000000 (Q..............
│ │ @@ -13226,42 +13226,42 @@
│ │    0x004cd480 bcdf3d00 04000000 ccdf3d00 05000000 ..=.......=.....
│ │    0x004cd490 dcdf3d00 06000000 dce03d00 08000000 ..=.......=.....
│ │    0x004cd4a0 44e13d00 09000000 4ce13d00 0a000000 D.=.....L.=.....
│ │    0x004cd4b0 54e13d00 0c000000 58e13d00 0f000000 T.=.....X.=.....
│ │    0x004cd4c0 68e13d00 11000000 0ce23d00 12000000 h.=.......=.....
│ │    0x004cd4d0 14e23d00 13000000 5ce33d00 00000000 ..=.....\.=.....
│ │    0x004cd4e0 00000000 31750800 01000000 00000000 ....1u..........
│ │ -  0x004cd4f0 04000000 ffffffff 26080a00 02000000 ........&.......
│ │ -  0x004cd500 00000000 04000000 ffffffff 5fea0900 ............_...
│ │ +  0x004cd4f0 04000000 ffffffff 4d080a00 02000000 ........M.......
│ │ +  0x004cd500 00000000 04000000 ffffffff 86ea0900 ................
│ │    0x004cd510 02000000 00000000 04000000 ffffffff ................
│ │    0x004cd520 00000000 00000000 00000000 00000000 ................
│ │    0x004cd530 00000000 01000000 7ce33d00 02000000 ........|.=.....
│ │    0x004cd540 bce33d00 03000000 18e43d00 04000000 ..=.......=.....
│ │    0x004cd550 6ce43d00 05000000 80e43d00 06000000 l.=.......=.....
│ │    0x004cd560 1ce53d00 07000000 24e53d00 08000000 ..=.....$.=.....
│ │    0x004cd570 b4e53d00 09000000 30e63d00 0a000000 ..=.....0.=.....
│ │    0x004cd580 48e63d00 0d000000 5ce63d00 10000000 H.=.....\.=.....
│ │    0x004cd590 6ce63d00 0c000000 fce73d00 0f000000 l.=.......=.....
│ │    0x004cd5a0 0ce83d00 11000000 dce83d00 12000000 ..=.......=.....
│ │    0x004cd5b0 e4e83d00 00000000 00000000 b7100900 ..=.............
│ │    0x004cd5c0 05000000 00000000 00000000 ffffffff ................
│ │ -  0x004cd5d0 de1e0a00 05000000 00000000 00000000 ................
│ │ -  0x004cd5e0 ffffffff 26080a00 02000000 00000000 ....&...........
│ │ -  0x004cd5f0 04000000 ffffffff 5fea0900 02000000 ........_.......
│ │ +  0x004cd5d0 051f0a00 05000000 00000000 00000000 ................
│ │ +  0x004cd5e0 ffffffff 4d080a00 02000000 00000000 ....M...........
│ │ +  0x004cd5f0 04000000 ffffffff 86ea0900 02000000 ................
│ │    0x004cd600 00000000 04000000 ffffffff 8f400800 .............@..
│ │    0x004cd610 02000000 00000000 04000000 ffffffff ................
│ │    0x004cd620 00000000 00000000 00000000 00000000 ................
│ │    0x004cd630 00000000 31750800 01000000 00000000 ....1u..........
│ │ -  0x004cd640 04000000 ffffffff 26080a00 02000000 ........&.......
│ │ -  0x004cd650 00000000 04000000 ffffffff 5fea0900 ............_...
│ │ +  0x004cd640 04000000 ffffffff 4d080a00 02000000 ........M.......
│ │ +  0x004cd650 00000000 04000000 ffffffff 86ea0900 ................
│ │    0x004cd660 02000000 00000000 04000000 ffffffff ................
│ │    0x004cd670 8f400800 02000000 00000000 04000000 .@..............
│ │    0x004cd680 ffffffff 00000000 00000000 00000000 ................
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│ │ -  0x004cfab0 d4080a00 f200801c 122a0800 7200801c .........*..r...
│ │ -  0x004cfac0 30ab0800 b100801c 9b3f0a00 ef00801c 0........?......
│ │ -  0x004cfad0 91800900 b200801c 727b0800 6a00801c ........r{..j...
│ │ -  0x004cfae0 a9110800 e400801c f3960900 bb00801c ................
│ │ -  0x004cfaf0 0c560900 b600801c 27230800 c200801c .V......'#......
│ │ +  0x004cfa90 6aeb0900 c100801c 06c80800 e200801c j...............
│ │ +  0x004cfaa0 829a0800 8800801c 2b4d0a00 7100801c ........+M..q...
│ │ +  0x004cfab0 fb080a00 f200801c 122a0800 7200801c .........*..r...
│ │ +  0x004cfac0 30ab0800 b100801c c23f0a00 ef00801c 0........?......
│ │ +  0x004cfad0 b8800900 b200801c 727b0800 6a00801c ........r{..j...
│ │ +  0x004cfae0 a9110800 e400801c 1a970900 bb00801c ................
│ │ +  0x004cfaf0 33560900 b600801c 27230800 c200801c 3V......'#......
│ │    0x004cfb00 4b3a0800 db00801c dedc0800 c300801c K:..............
│ │ -  0x004cfb10 1e2f0a00 ac00801c b4c10700 c400801c ./..............
│ │ +  0x004cfb10 452f0a00 ac00801c b4c10700 c400801c E/..............
│ │    0x004cfb20 7a5d0a00 ce00801c f3100900 c500801c z]..............
│ │ -  0x004cfb30 3e2f0a00 de00801c 3d520800 e500801c >/......=R......
│ │ -  0x004cfb40 124d0a00 d700801c 84410800 d800801c .M.......A......
│ │ +  0x004cfb30 652f0a00 de00801c 3d520800 e500801c e/......=R......
│ │ +  0x004cfb40 394d0a00 d700801c 84410800 d800801c 9M.......A......
│ │    0x004cfb50 262a0800 7800801c a4590800 7700801c &*..x....Y..w...
│ │    0x004cfb60 87400900 7e00801c d8630800 cf00801c .@..~....c......
│ │ -  0x004cfb70 06e20800 c700801c 65d30900 9f00801c ........e.......
│ │ +  0x004cfb70 06e20800 c700801c 8cd30900 9f00801c ................
│ │    0x004cfb80 07b00700 d000801c 93400900 9300801c .........@......
│ │ -  0x004cfb90 364d0a00 c900801c 80ea0900 cc00801c 6M..............
│ │ -  0x004cfba0 49270900 9100801c 36ac0900 9900801c I'......6.......
│ │ +  0x004cfb90 5d4d0a00 c900801c a7ea0900 cc00801c ]M..............
│ │ +  0x004cfba0 49270900 9100801c 5dac0900 9900801c I'......].......
│ │    0x004cfbb0 00d60800 8900801c 95b80800 9800801c ................
│ │    0x004cfbc0 55ab0800 f000801c bf630a00 df00801c U........c......
│ │    0x004cfbd0 0a920700 8a00801c b5ca0700 6b00801c ............k...
│ │    0x004cfbe0 808a0700 8b00801c aab80800 b700801c ................
│ │    0x004cfbf0 3d2a0800 9400801c d0050800 9500801c =*..............
│ │    0x004cfc00 72ab0800 00000000 00000000 dce50700 r...............
│ │    0x004cfc10 02000000 00000000 04000000 ffffffff ................
│ │ -  0x004cfc20 ea540a00 02000000 00000000 04000000 .T..............
│ │ -  0x004cfc30 ffffffff edcc0900 02000000 00000000 ................
│ │ +  0x004cfc20 11550a00 02000000 00000000 04000000 .U..............
│ │ +  0x004cfc30 ffffffff 14cd0900 02000000 00000000 ................
│ │    0x004cfc40 04000000 ffffffff c6ea0800 02000000 ................
│ │ -  0x004cfc50 00000000 04000000 ffffffff 945e0900 .............^..
│ │ +  0x004cfc50 00000000 04000000 ffffffff bb5e0900 .............^..
│ │    0x004cfc60 01000000 00000000 04000000 ffffffff ................
│ │ -  0x004cfc70 8ee30900 01000000 00000000 04000000 ................
│ │ +  0x004cfc70 b5e30900 01000000 00000000 04000000 ................
│ │    0x004cfc80 ffffffff ab020900 01000000 00000000 ................
│ │ -  0x004cfc90 04000000 ffffffff 10110a00 01000000 ................
│ │ -  0x004cfca0 00000000 04000000 ffffffff 20740900 ............ t..
│ │ +  0x004cfc90 04000000 ffffffff 37110a00 01000000 ........7.......
│ │ +  0x004cfca0 00000000 04000000 ffffffff 47740900 ............Gt..
│ │    0x004cfcb0 01000000 00000000 04000000 ffffffff ................
│ │    0x004cfcc0 00000000 00000000 00000000 00000000 ................
│ │ -  0x004cfcd0 00000000 ea540a00 02000000 00000000 .....T..........
│ │ -  0x004cfce0 04000000 ffffffff edcc0900 02000000 ................
│ │ +  0x004cfcd0 00000000 11550a00 02000000 00000000 .....U..........
│ │ +  0x004cfce0 04000000 ffffffff 14cd0900 02000000 ................
│ │    0x004cfcf0 00000000 04000000 ffffffff cafe0800 ................
│ │    0x004cfd00 02000000 00000000 04000000 ffffffff ................
│ │ -  0x004cfd10 2c740900 02000000 00000000 04000000 ,t..............
│ │ +  0x004cfd10 53740900 02000000 00000000 04000000 St..............
│ │    0x004cfd20 ffffffff 8b880700 05000000 00000000 ................
│ │    0x004cfd30 00000000 ffffffff 01aa0800 05000000 ................
│ │ -  0x004cfd40 00000000 00000000 ffffffff 936f0900 .............o..
│ │ +  0x004cfd40 00000000 00000000 ffffffff ba6f0900 .............o..
│ │    0x004cfd50 07000000 00000000 00000000 ffffffff ................
│ │    0x004cfd60 00000000 00000000 00000000 00000000 ................
│ │    0x004cfd70 00000000 cafe0800 02000000 00000000 ................
│ │ -  0x004cfd80 04000000 ffffffff 2c740900 02000000 ........,t......
│ │ +  0x004cfd80 04000000 ffffffff 53740900 02000000 ........St......
│ │    0x004cfd90 00000000 04000000 ffffffff c3b80800 ................
│ │    0x004cfda0 02000000 00000000 04000000 ffffffff ................
│ │    0x004cfdb0 3ed00700 02000000 00000000 04000000 >...............
│ │    0x004cfdc0 ffffffff e7830700 02000000 00000000 ................
│ │    0x004cfdd0 04000000 ffffffff 00000000 00000000 ................
│ │ -  0x004cfde0 00000000 00000000 00000000 ea540a00 .............T..
│ │ +  0x004cfde0 00000000 00000000 00000000 11550a00 .............U..
│ │    0x004cfdf0 02000000 00000000 04000000 ffffffff ................
│ │ -  0x004cfe00 edcc0900 02000000 00000000 04000000 ................
│ │ +  0x004cfe00 14cd0900 02000000 00000000 04000000 ................
│ │    0x004cfe10 ffffffff fcdf0700 02000000 00000000 ................
│ │    0x004cfe20 04000000 ffffffff 8b880700 05000000 ................
│ │    0x004cfe30 00000000 00000000 ffffffff 01aa0800 ................
│ │    0x004cfe40 05000000 00000000 00000000 ffffffff ................
│ │    0x004cfe50 99ec0700 05000000 00000000 00000000 ................
│ │    0x004cfe60 ffffffff d8310900 02000000 00000000 .....1..........
│ │    0x004cfe70 04000000 ffffffff c8a90800 05000000 ................
│ │    0x004cfe80 00000000 00000000 ffffffff b3590800 .............Y..
│ │    0x004cfe90 02000000 00000000 04000000 ffffffff ................
│ │    0x004cfea0 00000000 00000000 00000000 00000000 ................
│ │ -  0x004cfeb0 00000000 edcc0900 02000000 00000000 ................
│ │ +  0x004cfeb0 00000000 14cd0900 02000000 00000000 ................
│ │    0x004cfec0 04000000 ffffffff 99ec0700 05000000 ................
│ │    0x004cfed0 00000000 00000000 ffffffff 24eb0800 ............$...
│ │    0x004cfee0 05000000 00000000 00000000 ffffffff ................
│ │    0x004cfef0 821a0800 05000000 00000000 00000000 ................
│ │    0x004cff00 ffffffff a6c00800 05000000 00000000 ................
│ │    0x004cff10 00000000 ffffffff 00000000 00000000 ................
│ │    0x004cff20 00000000 00000000 00000000 c6ea0800 ................
│ ├── readelf --wide --decompress --hex-dump=.data {}
│ │ @@ -5,115 +5,115 @@
│ │    0x004de8f0 01130003 00000000 00000000 00100000 ................
│ │    0x004de900 40000000 04030000 04030000 00000000 @...............
│ │    0x004de910 00000000 08000000 04000400 80000000 ................
│ │    0x004de920 80000000 01000000 aa410800 aa410800 .........A...A..
│ │    0x004de930 02130003 00000000 00000000 00200000 ............. ..
│ │    0x004de940 40000000 04030000 04030000 00000000 @...............
│ │    0x004de950 00000000 08000000 05000400 00010000 ................
│ │ -  0x004de960 00010000 01000000 4c6b0900 4c6b0900 ........Lk..Lk..
│ │ +  0x004de960 00010000 01000000 736b0900 736b0900 ........sk..sk..
│ │    0x004de970 03130003 00000000 00000000 00000800 ................
│ │    0x004de980 40000000 04030000 04030000 00000000 @...............
│ │    0x004de990 00000000 08000000 04000400 00010000 ................
│ │    0x004de9a0 00010000 01000000 c1410800 c1410800 .........A...A..
│ │    0x004de9b0 04130003 00000000 00000000 00400000 .............@..
│ │    0x004de9c0 40000000 04030000 04030000 00000000 @...............
│ │    0x004de9d0 00000000 28000000 04000000 80000000 ....(...........
│ │ -  0x004de9e0 80000000 01000000 76c40900 76c40900 ........v...v...
│ │ +  0x004de9e0 80000000 01000000 9dc40900 9dc40900 ................
│ │    0x004de9f0 05130003 00000000 00000000 00000100 ................
│ │    0x004dea00 40000000 04030000 04030000 00000000 @...............
│ │    0x004dea10 00000000 24000000 04000000 40000000 ....$.......@...
│ │    0x004dea20 80000000 01000000 09b90800 09b90800 ................
│ │    0x004dea30 b4c00003 00000000 00000000 20000000 ............ ...
│ │    0x004dea40 10000000 04030000 04030000 00000000 ................
│ │    0x004dea50 00000000 21000000 04000000 00000000 ....!...........
│ │    0x004dea60 00010000 01000000 60710800 60710800 ........`q..`q..
│ │    0x004dea70 b5c00003 00000000 00000000 20000000 ............ ...
│ │    0x004dea80 20000000 04030000 04030000 00000000  ...............
│ │    0x004dea90 00000000 21000000 05000000 00000000 ....!...........
│ │ -  0x004deaa0 80010000 01000000 696b0900 64110900 ........ik..d...
│ │ +  0x004deaa0 80010000 01000000 906b0900 64110900 .........k..d...
│ │    0x004deab0 01000003 01000000 01000000 20000000 ............ ...
│ │    0x004deac0 01000000 00030000 03030000 00010000 ................
│ │    0x004dead0 fdfe0000 01000000 09090000 00000000 ................
│ │ -  0x004deae0 00000000 01000000 8e970900 78cb0700 ............x...
│ │ +  0x004deae0 00000000 01000000 b5970900 78cb0700 ............x...
│ │    0x004deaf0 02000003 01000000 01000000 20000000 ............ ...
│ │    0x004deb00 02000000 00030000 03030000 00010000 ................
│ │    0x004deb10 fdfe0000 11000000 09090000 00000000 ................
│ │    0x004deb20 00000000 01000000 32ce0800 16e30700 ........2.......
│ │    0x004deb30 2f000003 01000000 01000000 40000000 /...........@...
│ │    0x004deb40 02000000 00030000 03030000 00010000 ................
│ │    0x004deb50 fdfe0000 18000000 09090000 80000000 ................
│ │ -  0x004deb60 80000000 01000000 e1800900 726b0900 ............rk..
│ │ +  0x004deb60 80000000 01000000 08810900 996b0900 .............k..
│ │    0x004deb70 32000003 02000000 02000000 40000000 2...........@...
│ │    0x004deb80 02000000 00030000 03030000 00010000 ................
│ │    0x004deb90 fdfe0000 38000000 09090000 80000000 ....8...........
│ │    0x004deba0 80000000 01000000 82e20800 8ecb0700 ................
│ │    0x004debb0 33000003 02000000 01000000 40000000 3...........@...
│ │    0x004debc0 02000000 00030000 03030000 00010000 ................
│ │    0x004debd0 fdfe0000 18000000 09090000 80000000 ................
│ │    0x004debe0 80000000 01000000 8bfc0700 93b00700 ................
│ │    0x004debf0 34000003 02000000 04000000 40000000 4...........@...
│ │    0x004dec00 02000000 00030000 03030000 00010000 ................
│ │    0x004dec10 fdfe0000 38000000 09090000 80000000 ....8...........
│ │ -  0x004dec20 80000000 01000000 71090a00 d31f0a00 ........q.......
│ │ +  0x004dec20 80000000 01000000 98090a00 fa1f0a00 ................
│ │    0x004dec30 35000003 01000000 01000000 80000000 5...............
│ │    0x004dec40 02000000 00030000 03030000 00010000 ................
│ │    0x004dec50 fdfe0000 18000000 09090000 00010000 ................
│ │ -  0x004dec60 00010000 01000000 1bb90800 936b0900 .............k..
│ │ +  0x004dec60 00010000 01000000 1bb90800 ba6b0900 .............k..
│ │    0x004dec70 38000003 02000000 02000000 80000000 8...............
│ │    0x004dec80 02000000 00030000 03030000 00010000 ................
│ │    0x004dec90 fdfe0000 38000000 09090000 00010000 ....8...........
│ │    0x004deca0 00010000 01000000 0a990700 a22a0800 .............*..
│ │    0x004decb0 39000003 02000000 01000000 80000000 9...............
│ │    0x004decc0 02000000 00030000 03030000 00010000 ................
│ │    0x004decd0 fdfe0000 18000000 09090000 00010000 ................
│ │ -  0x004dece0 00010000 01000000 57360a00 1d990700 ........W6......
│ │ +  0x004dece0 00010000 01000000 7e360a00 1d990700 ........~6......
│ │    0x004decf0 3a000003 02000000 04000000 80000000 :...............
│ │    0x004ded00 02000000 00030000 03030000 00010000 ................
│ │    0x004ded10 fdfe0000 38000000 09090000 00010000 ....8...........
│ │ -  0x004ded20 00010000 01000000 b46b0900 33e30700 .........k..3...
│ │ +  0x004ded20 00010000 01000000 db6b0900 33e30700 .........k..3...
│ │    0x004ded30 3b000003 01000000 01000000 20000000 ;........... ...
│ │    0x004ded40 10000000 03030000 03030000 fdfe0000 ................
│ │    0x004ded50 fdfe0000 11000000 09090000 00000000 ................
│ │ -  0x004ded60 00000000 01000000 d2a10800 f44d0a00 .............M..
│ │ +  0x004ded60 00000000 01000000 d2a10800 1b4e0a00 .............N..
│ │    0x004ded70 3c000003 01000000 01000000 40000000 <...........@...
│ │    0x004ded80 10000000 03030000 03030000 fdfe0000 ................
│ │    0x004ded90 fdfe0000 18000000 09090000 80000000 ................
│ │    0x004deda0 80000000 01000000 3dce0800 96890800 ........=.......
│ │    0x004dedb0 3d000003 01000000 01000000 80000000 =...............
│ │    0x004dedc0 10000000 03030000 03030000 fdfe0000 ................
│ │    0x004dedd0 fdfe0000 18000000 09090000 00010000 ................
│ │ -  0x004dede0 00010000 01000000 4ce30700 47f20900 ........L...G...
│ │ +  0x004dede0 00010000 01000000 4ce30700 6ef20900 ........L...n...
│ │    0x004dedf0 40000003 02000000 02000000 40000000 @...........@...
│ │    0x004dee00 10000000 03030000 03030000 fdfe0000 ................
│ │    0x004dee10 fdfe0000 38000000 09090000 80000000 ....8...........
│ │ -  0x004dee20 80000000 01000000 72710800 44db0900 ........rq..D...
│ │ +  0x004dee20 80000000 01000000 72710800 6bdb0900 ........rq..k...
│ │    0x004dee30 67000003 02000000 01000000 40000000 g...........@...
│ │    0x004dee40 10000000 03030000 03030000 fdfe0000 ................
│ │    0x004dee50 fdfe0000 18000000 09090000 80000000 ................
│ │    0x004dee60 80000000 01000000 e0a10800 95e20800 ................
│ │    0x004dee70 6a000003 02000000 02000000 80000000 j...............
│ │    0x004dee80 10000000 03030000 03030000 fdfe0000 ................
│ │    0x004dee90 fdfe0000 38000000 09090000 00010000 ....8...........
│ │ -  0x004deea0 00010000 01000000 68db0900 f01f0a00 ........h.......
│ │ +  0x004deea0 00010000 01000000 8fdb0900 17200a00 ............. ..
│ │    0x004deeb0 6b000003 02000000 01000000 80000000 k...............
│ │    0x004deec0 10000000 03030000 03030000 fdfe0000 ................
│ │    0x004deed0 fdfe0000 18000000 09090000 00010000 ................
│ │ -  0x004deee0 00010000 01000000 a5270900 a7560900 .........'...V..
│ │ +  0x004deee0 00010000 01000000 a5270900 ce560900 .........'...V..
│ │    0x004deef0 6c000003 02000000 04000000 40000000 l...........@...
│ │    0x004def00 10000000 03030000 03030000 fdfe0000 ................
│ │    0x004def10 fdfe0000 38000000 09090000 80000000 ....8...........
│ │    0x004def20 80000000 01000000 807f0700 b7270900 .............'..
│ │    0x004def30 6d000003 02000000 04000000 80000000 m...............
│ │    0x004def40 10000000 03030000 03030000 fdfe0000 ................
│ │    0x004def50 fdfe0000 38000000 09090000 00010000 ....8...........
│ │ -  0x004def60 00010000 01000000 76ac0900 d8410800 ........v....A..
│ │ +  0x004def60 00010000 01000000 9dac0900 d8410800 .............A..
│ │    0x004def70 9c000003 01000000 01000000 00100000 ................
│ │    0x004def80 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004def90 fdfe0000 18000000 04040000 80000000 ................
│ │ -  0x004defa0 80000000 01000000 97970900 b6890800 ................
│ │ +  0x004defa0 80000000 01000000 be970900 b6890800 ................
│ │    0x004defb0 9d000003 01000000 01000000 00200000 ............. ..
│ │    0x004defc0 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004defd0 fdfe0000 18000000 05050000 00010000 ................
│ │    0x004defe0 00010000 01000000 5f5a0800 0c410900 ........_Z...A..
│ │    0x004deff0 9e000003 02000000 01000000 00100000 ................
│ │    0x004df000 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004df010 fdfe0000 18000000 04040000 80000000 ................
│ │ @@ -121,67 +121,67 @@
│ │    0x004df030 9f000003 02000000 01000000 00200000 ............. ..
│ │    0x004df040 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004df050 fdfe0000 18000000 05050000 00010000 ................
│ │    0x004df060 00010000 01000000 9afc0700 fa890800 ................
│ │    0x004df070 a2000003 02000000 02000000 00100000 ................
│ │    0x004df080 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004df090 fdfe0000 38000000 04040000 80000000 ....8...........
│ │ -  0x004df0a0 80000000 01000000 14200a00 cb560900 ......... ...V..
│ │ +  0x004df0a0 80000000 01000000 3b200a00 f2560900 ........; ...V..
│ │    0x004df0b0 a3000003 02000000 02000000 00200000 ............. ..
│ │    0x004df0c0 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004df0d0 fdfe0000 38000000 05050000 00010000 ....8...........
│ │ -  0x004df0e0 00010000 01000000 c06b0900 88ac0900 .........k......
│ │ +  0x004df0e0 00010000 01000000 e76b0900 afac0900 .........k......
│ │    0x004df0f0 a6000003 02000000 04000000 00100000 ................
│ │    0x004df100 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004df110 fdfe0000 38000000 04040000 80000000 ....8...........
│ │    0x004df120 80000000 01000000 30410900 b4fc0700 ........0A......
│ │    0x004df130 a7000003 02000000 04000000 00200000 ............. ..
│ │    0x004df140 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004df150 fdfe0000 38000000 05050000 00010000 ....8...........
│ │ -  0x004df160 00010000 01000000 d8fc0700 8fc40900 ................
│ │ +  0x004df160 00010000 01000000 d8fc0700 b6c40900 ................
│ │    0x004df170 9cc00003 01000000 01000000 00400000 .............@..
│ │    0x004df180 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004df190 fdfe0000 28000000 04040000 80000000 ....(...........
│ │    0x004df1a0 80000000 01000000 7a110900 91120800 ........z.......
│ │    0x004df1b0 9dc00003 01000000 01000000 00800000 ................
│ │    0x004df1c0 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004df1d0 fdfe0000 28000000 04040000 00010000 ....(...........
│ │ -  0x004df1e0 00010000 01000000 f4800900 66360a00 ............f6..
│ │ +  0x004df1e0 00010000 01000000 1b810900 8d360a00 .............6..
│ │    0x004df1f0 9ec00003 02000000 01000000 00400000 .............@..
│ │    0x004df200 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004df210 fdfe0000 28000000 04040000 80000000 ....(...........
│ │    0x004df220 80000000 01000000 e3fc0700 b4b00700 ................
│ │    0x004df230 9fc00003 02000000 01000000 00800000 ................
│ │    0x004df240 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004df250 fdfe0000 28000000 04040000 00010000 ....(...........
│ │ -  0x004df260 00010000 01000000 d66b0900 62e30700 .........k..b...
│ │ +  0x004df260 00010000 01000000 fd6b0900 62e30700 .........k..b...
│ │    0x004df270 a0c00003 01000000 01000000 00000100 ................
│ │    0x004df280 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004df290 fdfe0000 24000000 04040000 40000000 ....$.......@...
│ │ -  0x004df2a0 80000000 01000000 f6a10800 7edb0900 ............~...
│ │ +  0x004df2a0 80000000 01000000 f6a10800 a5db0900 ................
│ │    0x004df2b0 a1c00003 01000000 01000000 00000200 ................
│ │    0x004df2c0 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004df2d0 fdfe0000 24000000 04040000 40000000 ....$.......@...
│ │ -  0x004df2e0 00010000 01000000 6bf20900 73fa0800 ........k...s...
│ │ +  0x004df2e0 00010000 01000000 92f20900 73fa0800 ............s...
│ │    0x004df2f0 a2c00003 02000000 01000000 00000100 ................
│ │    0x004df300 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004df310 fdfe0000 24000000 04040000 40000000 ....$.......@...
│ │ -  0x004df320 80000000 01000000 927f0700 144e0a00 .............N..
│ │ +  0x004df320 80000000 01000000 927f0700 3b4e0a00 ............;N..
│ │    0x004df330 a3c00003 02000000 01000000 00000200 ................
│ │    0x004df340 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004df350 fdfe0000 24000000 04040000 40000000 ....$.......@...
│ │ -  0x004df360 00010000 01000000 a8c40900 afcb0700 ................
│ │ +  0x004df360 00010000 01000000 cfc40900 afcb0700 ................
│ │    0x004df370 a4c00003 08000000 10000000 00400000 .............@..
│ │    0x004df380 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004df390 fdfe0000 28000000 04040000 80000000 ....(...........
│ │    0x004df3a0 80000000 01000000 7de30700 f8410800 ........}....A..
│ │    0x004df3b0 a5c00003 08000000 10000000 00800000 ................
│ │    0x004df3c0 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004df3d0 fdfe0000 28000000 04040000 00010000 ....(...........
│ │ -  0x004df3e0 00010000 01000000 acac0900 02a20800 ................
│ │ +  0x004df3e0 00010000 01000000 d3ac0900 02a20800 ................
│ │    0x004df3f0 a6c00003 00010000 10000000 00400000 .............@..
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│ │    0x004df410 fdfe0000 28000000 04040000 80000000 ....(...........
│ │    0x004df420 80000000 01000000 2eb90800 c32a0800 .............*..
│ │    0x004df430 a7c00003 00010000 10000000 00800000 ................
│ │    0x004df440 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004df450 fdfe0000 28000000 04040000 00010000 ....(...........
│ │ @@ -189,135 +189,135 @@
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│ │    0x004df490 fdfe0000 24000000 04040000 40000000 ....$.......@...
│ │    0x004df4a0 80000000 01000000 d1b00700 88710800 .............q..
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│ │ +  0x004df4e0 00010000 01000000 e1b00700 a3090a00 ................
│ │    0x004df4f0 aac00003 00010000 10000000 00000100 ................
│ │    0x004df500 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004df510 fdfe0000 24000000 04040000 40000000 ....$.......@...
│ │    0x004df520 80000000 01000000 51b90800 1fa20800 ........Q.......
│ │    0x004df530 abc00003 00010000 10000000 00000200 ................
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│ │ -  0x004df560 00010000 01000000 9b090a00 4bce0800 ............K...
│ │ +  0x004df560 00010000 01000000 c2090a00 4bce0800 ............K...
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│ │ +  0x004df5a0 80000000 01000000 c0db0900 c8cb0700 ................
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│ │ -  0x004df5e0 00010000 01000000 bfac0900 85110900 ................
│ │ +  0x004df5e0 00010000 01000000 e6ac0900 85110900 ................
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│ │ -  0x004df620 80000000 01000000 d3e20800 e26b0900 .............k..
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│ │    0x004df650 fdfe0000 24000000 04040000 40000000 ....$.......@...
│ │ -  0x004df660 00010000 01000000 a3710800 056c0900 .........q...l..
│ │ +  0x004df660 00010000 01000000 a3710800 2c6c0900 .........q..,l..
│ │    0x004df670 06c00003 04000000 08000000 20000000 ............ ...
│ │    0x004df680 02000000 01030000 03030000 00010000 ................
│ │    0x004df690 fdfe0000 11000000 09090000 00000000 ................
│ │    0x004df6a0 00000000 01000000 8ce30700 46410900 ............FA..
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│ │    0x004df6c0 02000000 01030000 03030000 00010000 ................
│ │    0x004df6d0 fdfe0000 18000000 09090000 80000000 ................
│ │ -  0x004df6e0 80000000 01000000 236c0900 334e0a00 ........#l..3N..
│ │ +  0x004df6e0 80000000 01000000 4a6c0900 5a4e0a00 ........Jl..ZN..
│ │    0x004df6f0 0ac00003 04000000 08000000 80000000 ................
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│ │    0x004df730 10c00003 04000000 01000000 20000000 ............ ...
│ │    0x004df740 02000000 01030000 03030000 00010000 ................
│ │    0x004df750 fdfe0000 11000000 09090000 00000000 ................
│ │ -  0x004df760 00000000 01000000 b0db0900 1e8a0800 ................
│ │ +  0x004df760 00000000 01000000 d7db0900 1e8a0800 ................
│ │    0x004df770 13c00003 04000000 01000000 40000000 ............@...
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│ │    0x004df790 fdfe0000 18000000 09090000 80000000 ................
│ │    0x004df7a0 80000000 01000000 aa120800 f6fc0700 ................
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│ │ -  0x004df7e0 00010000 01000000 b7c40900 3e990700 ............>...
│ │ +  0x004df7e0 00010000 01000000 dec40900 3e990700 ............>...
│ │    0x004df7f0 15c00003 04000000 04000000 20000000 ............ ...
│ │    0x004df800 02000000 01030000 03030000 00010000 ................
│ │    0x004df810 fdfe0000 11000000 09090000 00000000 ................
│ │ -  0x004df820 00000000 01000000 418a0800 83360a00 ........A....6..
│ │ +  0x004df820 00000000 01000000 418a0800 aa360a00 ........A....6..
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│ │    0x004df850 fdfe0000 38000000 09090000 80000000 ....8...........
│ │ -  0x004df860 80000000 01000000 2e200a00 ebe20800 ......... ......
│ │ +  0x004df860 80000000 01000000 55200a00 ebe20800 ........U ......
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│ │    0x004df950 fdfe0000 18000000 04040000 80000000 ................
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│ │    0x004df9a0 00010000 01000000 5a990700 f5b00700 ........Z.......
│ │    0x004df9b0 2bc00003 04000000 08000000 00100000 +...............
│ │    0x004df9c0 40000000 03030000 03030000 fdfe0000 @...............
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│ │ -  0x004df9e0 80000000 01000000 17570900 35570900 .........W..5W..
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│ │    0x004df9f0 2cc00003 04000000 08000000 00200000 ,............ ..
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│ │ -  0x004dfa20 00010000 01000000 c6c40900 3a6c0900 ............:l..
│ │ +  0x004dfa20 00010000 01000000 edc40900 616c0900 ............al..
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│ │ -  0x004dfa60 80000000 01000000 7ff20900 3f200a00 ............? ..
│ │ +  0x004dfa60 80000000 01000000 a6f20900 66200a00 ............f ..
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│ │    0x004dfac0 02000000 00030000 03030000 00010000 ................
│ │    0x004dfad0 fdfe0000 11000000 09090000 00000000 ................
│ │ -  0x004dfae0 00000000 01000000 9bf20900 11420800 .............B..
│ │ +  0x004dfae0 00000000 01000000 c2f20900 11420800 .............B..
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│ │    0x004dfb00 02000000 00030000 03030000 00010000 ................
│ │    0x004dfb10 fdfe0000 11000000 09090000 00000000 ................
│ │ -  0x004dfb20 00000000 01000000 a9970900 bf120800 ................
│ │ +  0x004dfb20 00000000 01000000 d0970900 bf120800 ................
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│ │    0x004dfb60 00000000 01000000 78990700 c5fa0800 ........x.......
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│ │    0x004dfbf0 90000003 00010000 10000000 40000000 ............@...
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│ │    0x004dfc10 fdfe0000 18000000 09090000 80000000 ................
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│ │    0x004dfc30 91000003 00010000 10000000 80000000 ................
│ │    0x004dfc40 02000000 00030000 03030000 00010000 ................
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│ │    0x004dfca0 80000000 01000000 b8710800 2b420800 .........q..+B..
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│ │    0x004dfcc0 02000000 00030000 03030000 00010000 ................
│ │    0x004dfcd0 fdfe0000 18000000 09090000 00010000 ................
│ │ @@ -329,39 +329,39 @@
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│ │    0x004dfd40 40000000 03030000 03030000 fdfe0000 @...............
│ │    0x004dfd50 fdfe0000 18000000 05050000 00010000 ................
│ │    0x004dfd60 00010000 01000000 d9120800 14280900 .............(..
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│ │    0x004dfd90 fdfe0000 18000000 04040000 80000000 ................
│ │ -  0x004dfda0 80000000 01000000 8b990700 00dc0900 ................
│ │ +  0x004dfda0 80000000 01000000 8b990700 27dc0900 ............'...
│ │    0x004dfdb0 ab000003 00010000 10000000 00200000 ............. ..
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│ │    0x004dfdd0 fdfe0000 18000000 05050000 00010000 ................
│ │    0x004dfde0 00010000 01000000 a3e30700 f3120800 ................
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│ │ -  0x004dfe60 00010000 01000000 e9710800 e2c40900 .........q......
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│ │    0x004dfe90 fdfe0000 18000000 09090000 80000000 ................
│ │    0x004dfea0 80000000 01000000 30b10700 17130800 ........0.......
│ │    0x004dfeb0 af000003 08000000 10000000 80000000 ................
│ │    0x004dfec0 20000000 01030000 03030000 00010000  ...............
│ │    0x004dfed0 fdfe0000 18000000 05050000 00010000 ................
│ │ -  0x004dfee0 00010000 01000000 a6360a00 c27f0700 .........6......
│ │ +  0x004dfee0 00010000 01000000 cd360a00 c27f0700 .........6......
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│ │    0x004dff00 10000000 01030000 03030000 00010000 ................
│ │    0x004dff10 fdfe0000 11000000 09090000 00000000 ................
│ │ -  0x004dff20 00000000 01000000 65200a00 b6360a00 ........e ...6..
│ │ +  0x004dff20 00000000 01000000 8c200a00 dd360a00 ......... ...6..
│ │    0x004dff30 b1000003 08000000 10000000 20000000 ............ ...
│ │    0x004dff40 20000000 01030000 03030000 00010000  ...............
│ │    0x004dff50 fdfe0000 11000000 05050000 00000000 ................
│ │    0x004dff60 00000000 01000000 be110900 a3410900 .............A..
│ │    0x004dff70 b2000003 00010000 10000000 40000000 ............@...
│ │    0x004dff80 10000000 01030000 03030000 00010000 ................
│ │    0x004dff90 fdfe0000 18000000 09090000 80000000 ................
│ │ @@ -369,107 +369,107 @@
│ │    0x004dffb0 b3000003 00010000 10000000 80000000 ................
│ │    0x004dffc0 20000000 01030000 03030000 00010000  ...............
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│ │    0x004dffe0 00010000 01000000 945a0800 bde30700 .........Z......
│ │    0x004dfff0 b4000003 00010000 10000000 20000000 ............ ...
│ │    0x004e0000 10000000 01030000 03030000 00010000 ................
│ │    0x004e0010 fdfe0000 11000000 09090000 00000000 ................
│ │ -  0x004e0020 00000000 01000000 02c50900 d7ac0900 ................
│ │ +  0x004e0020 00000000 01000000 29c50900 feac0900 ........).......
│ │    0x004e0030 b5000003 00010000 10000000 20000000 ............ ...
│ │    0x004e0040 20000000 01030000 03030000 00010000  ...............
│ │    0x004e0050 fdfe0000 11000000 05050000 00000000 ................
│ │ -  0x004e0060 00000000 01000000 75200a00 70420800 ........u ..pB..
│ │ +  0x004e0060 00000000 01000000 9c200a00 70420800 ......... ..pB..
│ │    0x004e0070 b6000003 40000000 01000000 40000000 ....@.......@...
│ │    0x004e0080 10000000 01030000 03030000 00010000 ................
│ │    0x004e0090 fdfe0000 18000000 09090000 80000000 ................
│ │ -  0x004e00a0 80000000 01000000 16c50900 704e0a00 ............pN..
│ │ +  0x004e00a0 80000000 01000000 3dc50900 974e0a00 ........=....N..
│ │    0x004e00b0 b7000003 40000000 01000000 80000000 ....@...........
│ │    0x004e00c0 20000000 01030000 03030000 00010000  ...............
│ │    0x004e00d0 fdfe0000 18000000 05050000 00010000 ................
│ │    0x004e00e0 00010000 01000000 76a20800 e02a0800 ........v....*..
│ │    0x004e00f0 b8000003 40000000 01000000 20000000 ....@....... ...
│ │    0x004e0100 10000000 01030000 03030000 00010000 ................
│ │    0x004e0110 fdfe0000 11000000 09090000 00000000 ................
│ │ -  0x004e0120 00000000 01000000 8f200a00 c3f20900 ......... ......
│ │ +  0x004e0120 00000000 01000000 b6200a00 eaf20900 ......... ......
│ │    0x004e0130 b9000003 40000000 01000000 20000000 ....@....... ...
│ │    0x004e0140 20000000 01030000 03030000 00010000  ...............
│ │    0x004e0150 fdfe0000 11000000 05050000 00000000 ................
│ │    0x004e0160 00000000 01000000 a85a0800 fd2a0800 .........Z...*..
│ │    0x004e0170 35c00003 80000000 10000000 40000000 5...........@...
│ │    0x004e0180 02000000 01030000 03030000 00010000 ................
│ │    0x004e0190 fdfe0000 18000000 09090000 80000000 ................
│ │ -  0x004e01a0 80000000 01000000 cf360a00 ba970900 .........6......
│ │ +  0x004e01a0 80000000 01000000 f6360a00 e1970900 .........6......
│ │    0x004e01b0 36c00003 80000000 10000000 80000000 6...............
│ │    0x004e01c0 02000000 01030000 03030000 00010000 ................
│ │    0x004e01d0 fdfe0000 18000000 09090000 00010000 ................
│ │ -  0x004e01e0 00010000 01000000 dae30700 cf090a00 ................
│ │ +  0x004e01e0 00010000 01000000 dae30700 f6090a00 ................
│ │    0x004e01f0 37c00003 80000000 10000000 40000000 7...........@...
│ │    0x004e0200 10000000 01030000 03030000 00010000 ................
│ │    0x004e0210 fdfe0000 18000000 09090000 80000000 ................
│ │    0x004e0220 80000000 01000000 8aa20800 19720800 .............r..
│ │    0x004e0230 38c00003 80000000 10000000 80000000 8...............
│ │    0x004e0240 20000000 01030000 03030000 00010000  ...............
│ │    0x004e0250 fdfe0000 18000000 05050000 00010000 ................
│ │    0x004e0260 00010000 01000000 0ee30800 46b10700 ............F...
│ │    0x004e0270 39c00003 80000000 10000000 20000000 9........... ...
│ │    0x004e0280 02000000 01030000 03030000 00010000 ................
│ │    0x004e0290 fdfe0000 11000000 09090000 00000000 ................
│ │ -  0x004e02a0 00000000 01000000 944e0a00 e8360a00 .........N...6..
│ │ +  0x004e02a0 00000000 01000000 bb4e0a00 0f370a00 .........N...7..
│ │    0x004e02b0 3ac00003 80000000 10000000 20000000 :........... ...
│ │    0x004e02c0 10000000 01030000 03030000 00010000 ................
│ │    0x004e02d0 fdfe0000 11000000 09090000 00000000 ................
│ │ -  0x004e02e0 00000000 01000000 dd970900 a3200a00 ............. ..
│ │ +  0x004e02e0 00000000 01000000 04980900 ca200a00 ............. ..
│ │    0x004e02f0 3bc00003 80000000 10000000 20000000 ;........... ...
│ │    0x004e0300 20000000 01030000 03030000 00010000  ...............
│ │    0x004e0310 fdfe0000 11000000 05050000 00000000 ................
│ │    0x004e0320 00000000 01000000 202b0800 94420800 ........ +...B..
│ │    0x004e0330 1dc00003 20000000 40000000 40000000 .... ...@...@...
│ │    0x004e0340 02000000 00030000 03030000 00010000 ................
│ │    0x004e0350 fdfe0000 08000000 09090000 80000000 ................
│ │    0x004e0360 80000000 01000000 d8110900 f6e30700 ................
│ │    0x004e0370 1ec00003 20000000 01000000 40000000 .... .......@...
│ │    0x004e0380 02000000 00030000 03030000 00010000 ................
│ │    0x004e0390 fdfe0000 08000000 09090000 80000000 ................
│ │ -  0x004e03a0 80000000 01000000 aa4e0a00 b5420800 .........N...B..
│ │ +  0x004e03a0 80000000 01000000 d14e0a00 b5420800 .........N...B..
│ │    0x004e03b0 1fc00003 20000000 02000000 40000000 .... .......@...
│ │    0x004e03c0 02000000 00030000 03030000 00010000 ................
│ │    0x004e03d0 fdfe0000 28000000 09090000 80000000 ....(...........
│ │ -  0x004e03e0 80000000 01000000 5d570900 19fb0800 ........]W......
│ │ +  0x004e03e0 80000000 01000000 84570900 19fb0800 .........W......
│ │    0x004e03f0 20c00003 20000000 40000000 80000000  ... ...@.......
│ │    0x004e0400 02000000 00030000 03030000 00010000 ................
│ │    0x004e0410 fdfe0000 08000000 09090000 00010000 ................
│ │ -  0x004e0420 00010000 01000000 846c0900 c15a0800 .........l...Z..
│ │ +  0x004e0420 00010000 01000000 ab6c0900 c15a0800 .........l...Z..
│ │    0x004e0430 21c00003 20000000 01000000 80000000 !... ...........
│ │    0x004e0440 02000000 00030000 03030000 00010000 ................
│ │    0x004e0450 fdfe0000 08000000 09090000 00010000 ................
│ │ -  0x004e0460 00010000 01000000 1e810900 07370a00 .............7..
│ │ +  0x004e0460 00010000 01000000 45810900 2e370a00 ........E....7..
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│ │    0x004e04e0 00010000 01000000 342b0800 da420800 ........4+...B..
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│ │ -  0x004e0520 00010000 01000000 3afb0800 1ead0900 ........:.......
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│ │ @@ -477,127 +477,127 @@
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│ │ -  0x004e0ce0 00010000 01000000 49dc0900 38430800 ........I...8C..
│ │ +  0x004e0ce0 00010000 01000000 70dc0900 38430800 ........p...8C..
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│ │    0x004e0d90 00000000 08000000 02020100 00010000 ................
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│ │    0x004e0dc0 04000000 01030000 03030000 00000000 ................
│ │    0x004e0dd0 00000000 01000000 02020000 00000000 ................
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│ │    0x004e0df0 02c10003 10000000 a0000000 00000400 ................
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│ │    0x004e0e10 00000000 08000000 06060100 00010000 ................
│ │    0x004e0e20 00010000 01000000 bb8a0800 00000000 ................
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│ │ @@ -613,43 +613,43 @@
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│ │    0x004e11e0 00010000 01000000 82130800 21e30800 ............!...
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│ │ +  0x004e12a0 80000000 01000000 eadc0900 a5fb0800 ................
│ │    0x004e12b0 61c00003 04000000 01000000 00002000 a............. .
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│ │    0x004e12d0 fdfe0000 28000000 05050000 00010000 ....(...........
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│ │ +  0x004e12e0 00010000 01000000 7f0a0a00 03dd0900 ................
│ │    0x004e12f0 6ac00003 08000000 10000000 00001000 j...............
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│ │ +  0x004e13a0 80000000 01000000 24dd0900 ccfb0800 ........$.......
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│ │    0x004e1470 ff000003 00000000 00000000 00000000 ................
│ │    0x004e1480 00000000 00000000 00000000 00000000 ................
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│ │    0x004e14a0 00000000 00000000 26800700 26800700 ........&...&...
│ │    0x004e14b0 00560003 00000000 00000000 00000000 .V..............
│ │    0x004e14c0 00000000 00000000 00000000 00000000 ................
│ │    0x004e14d0 00000000 00000000 00000000 00000000 ................
│ │ @@ -710,69 +710,69 @@
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│ │    0x004e1520 14bb0a00 00000000 00000000 5c9d2700 ............\.'.
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│ │    0x004e1560 5ca22700 01000000 00000000 00000000 \.'.............
│ │ -  0x004e1570 00000000 00000000 d1ca0900 f0152900 ..............).
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│ │    0x004e15b0 28a92900 00000000 64a92900 f4a92900 (.).....d.)...).
│ │    0x004e15c0 64aa2900 00000000 00000000 b0aa2900 d.)...........).
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│ │ +  0x004e1760 00000017 c8180900 0000001c 2bf80900 ............+...
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│ │ +  0x004e1780 00000019 f3870900 00008019 23790800 ............#y..
│ │    0x004e1790 0000001a b4eb0700 00000016 32790800 ............2y..
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│ │ +  0x004e17e0 03000800 b1cc0900 04000800 10910800 ................
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│ │ +  0x004e18d0 09010800 899d0900 0a010800 ad870700 ................
│ │    0x004e18e0 0b010800 bf870700 0c010800 52790800 ............Ry..
│ │    0x004e18f0 0d010800 d5180900 0e010800 e8030800 ................
│ │    0x004e1900 0f010c00 89ea0800 10010c00 d0870700 ................
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│ │    0x004e1930 01000000 50502e00 0c512e00 c0592e00 ....PP...Q...Y..
│ │    0x004e1940 00000000 00000000 00000000 ec592e00 .............Y..
│ │ @@ -791,37 +791,37 @@
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│ │    0x004e1a20 00000000 00000000 00000000 00000000 ................
│ │    0x004e1a30 00000000 00000000 00000000 00000000 ................
│ │    0x004e1a40 00000000 00000000 00000000 ffffffff ................
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│ │    0x004e1a70 00000000 2c2c3400 d42b3400 842c3400 ....,,4..+4..,4.
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│ │ -  0x004e1a90 834a0800 96c10800 5b920800 20560a00 .J......[... V..
│ │ -  0x004e1aa0 f5880700 30030900 00000000 03b50900 ....0...........
│ │ +  0x004e1a80 13480900 a3f90900 b5270a00 5fcd0900 .H.......'.._...
│ │ +  0x004e1a90 834a0800 96c10800 5b920800 47560a00 .J......[...GV..
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│ │    0x004e1ab0 92a10700 2bd50800 01890700 0f890700 ....+...........
│ │ -  0x004e1ac0 11b50900 65aa0800 a2c10800 39d50800 ....e.......9...
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│ │ +  0x004e1ac0 38b50900 65aa0800 a2c10800 39d50800 8...e.......9...
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│ │ +  0x004e1ae0 a27a0800 a3190900 be040800 d5880900 .z..............
│ │    0x004e1af0 8f4a0800 56ed0700 1d1b0800 00000000 .J..V...........
│ │ -  0x004e1b00 041b4e00 608f0900 08d23400 74d53400 ..N.`.....4.t.4.
│ │ +  0x004e1b00 041b4e00 878f0900 08d23400 74d53400 ..N.......4.t.4.
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│ │    0x004e1b20 acee3400 c0ee3400 00040000 00000000 ..4...4.........
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│ │ -  0x004e1b40 507b0900 1c8f4b00 088f4b00 835e0a00 P{....K...K..^..
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│ │ -  0x004e1b80 448f4b00 a48e4b00 ba8f0900 448f4b00 D.K...K.....D.K.
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│ │ -  0x004e1d80 59c30700 86e50800 01000000 b0300a00 Y............0..
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│ │    0x004e2050 5c273800 0eca0800 84000000 00000000 \'8.............
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│ │ +  0x004e2160 00000000 20000000 00000000 040d0a00 .... ...........
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│ │    0x004e2180 39910800 02000000 00000000 04000000 9...............
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│ │    0x004e21c0 04000000 00000000 00000000 ffffffff ................
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│ │ -  0x004e21f0 00000000 ffffffff 9a270a00 01000000 .........'......
│ │ +  0x004e21f0 00000000 ffffffff c1270a00 01000000 .........'......
│ │    0x004e2200 00000000 04000000 ffffffff 62030900 ............b...
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│ │    0x004e2220 00000000 00000000 00000000 00000000 ................
│ │ -  0x004e2230 00000000 a4860900 04000000 00000000 ................
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│ │    0x004e2240 00000000 ffffffff e82f0900 01000000 ........./......
│ │    0x004e2250 00000000 04000000 ffffffff 84600800 .............`..
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│ │    0x004e2270 68860700 04000000 00000000 00000000 h...............
│ │    0x004e2280 ffffffff a69f0700 04000000 00000000 ................
│ │    0x004e2290 00000000 ffffffff 04430900 02000000 .........C......
│ │    0x004e22a0 00000000 00000000 ffffffff c8450900 .............E..
│ │    0x004e22b0 02000000 00000000 00000000 ffffffff ................
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│ │ -  0x004e22d0 ffffffff 8c710900 05000000 00000000 .....q..........
│ │ -  0x004e22e0 00000000 ffffffff 33f70900 02000000 ........3.......
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│ │ +  0x004e22e0 00000000 ffffffff 5af70900 02000000 ........Z.......
│ │    0x004e22f0 00000000 00000000 ffffffff 07780800 .............x..
│ │    0x004e2300 02000000 00000000 00000000 ffffffff ................
│ │    0x004e2310 eae40800 05000000 00000000 00000000 ................
│ │    0x004e2320 ffffffff 75880800 05000000 00000000 ....u...........
│ │    0x004e2330 00000000 ffffffff 00000000 00000000 ................
│ │ -  0x004e2340 00000000 00000000 00000000 a4860900 ................
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│ │    0x004e2350 04000000 00000000 00000000 ffffffff ................
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│ │    0x004e2370 ffffffff 75880800 05000000 00000000 ....u...........
│ │    0x004e2380 00000000 ffffffff 00000000 00000000 ................
│ │ -  0x004e2390 00000000 00000000 00000000 22250a00 ............"%..
│ │ +  0x004e2390 00000000 00000000 00000000 49250a00 ............I%..
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│ │ -  0x004e23c0 00000000 22250a00 05000000 00000000 ...."%..........
│ │ -  0x004e23d0 00000000 ffffffff 9a980900 04000000 ................
│ │ +  0x004e23c0 00000000 49250a00 05000000 00000000 ....I%..........
│ │ +  0x004e23d0 00000000 ffffffff c1980900 04000000 ................
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│ │    0x004e23f0 00000000 00000000 00000000 00000000 ................
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│ │    0x004e2440 00000000 00000000 00000000 00000000 ................
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│ │    0x004e2480 00000000 00000000 ffffffff 20820700 ............ ...
│ │    0x004e2490 04000000 00000000 00000000 ffffffff ................
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│ │ -  0x004e24b0 ffffffff e2ea0900 04000000 00000000 ................
│ │ -  0x004e24c0 00000000 ffffffff ea550a00 04000000 .........U......
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│ │ +  0x004e24b0 ffffffff 09eb0900 04000000 00000000 ................
│ │ +  0x004e24c0 00000000 ffffffff 11560a00 04000000 .........V......
│ │    0x004e24d0 00000000 00000000 ffffffff 39920800 ............9...
│ │    0x004e24e0 01000000 00000000 04000000 ffffffff ................
│ │    0x004e24f0 00000000 00000000 00000000 00000000 ................
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│ │    0x004e2530 00000000 58014d00 00000000 ff000000 ....X.M.........